//+FHDR--------------------------------------------------------------------------------------------------------
//  Company: 
//-----------------------------------------------------------------------------------------------------------------
//  File Name             :    dacif.v
//  Department            :    
//  Author                :    PWY
//  Author's Tel          :     
//-----------------------------------------------------------------------------------------------------------------
//  Relese History
//  Version     Date            Author          Description
//  0.4         2024-03-12      PWY
//-----------------------------------------------------------------------------------------------------------------
//  Keywords            :       
//
//-----------------------------------------------------------------------------------------------------------------
//  Parameter
//
//-----------------------------------------------------------------------------------------------------------------
//  Purpose                 :
//                      
//-----------------------------------------------------------------------------------------------------------------
//  Target Device:        
//  Tool versions:        
//-----------------------------------------------------------------------------------------------------------------
//  Reuse Issues
//  Reset Strategy: 
//  Clock Domains: 
//  Critical Timing:
//  Asynchronous I/F:
//  Synthesizable (y/n): 
//  Other:
//-FHDR--------------------------------------------------------------------------------------------------------
 
module dacif (
   input         clk
  ,input         rstn
  //DAC mode select
  ,input  [1:0]  dac_mode_sel         //2'b00:NRZ mode;2'b01:MIX mode;
                                      //2'b10:2xNRZ mode;2'b00:reserve;
  ,input  [2 :0] intp_mode            //3'b000:x1;3'b001:x2;3'b010:x4;
                                      //3'b011:x8;3'b100:x16;
  ,input  din_vld
  ,output dout_vld
  //mixer data input 
  ,input  [15:0] din0
  ,input  [15:0] din1
  ,input  [15:0] din2
  ,input  [15:0] din3
  ,input  [15:0] din4
  ,input  [15:0] din5
  ,input  [15:0] din6
  ,input  [15:0] din7
  ,input  [15:0] din8
  ,input  [15:0] din9
  ,input  [15:0] din10
  ,input  [15:0] din11
  ,input  [15:0] din12
  ,input  [15:0] din13
  ,input  [15:0] din14
  ,input  [15:0] din15
  //data output
  ,output [15:0] dout0
  ,output [15:0] dout1
  ,output [15:0] dout2
  ,output [15:0] dout3
  ,output [15:0] dout4
  ,output [15:0] dout5
  ,output [15:0] dout6
  ,output [15:0] dout7
  ,output [15:0] dout8
  ,output [15:0] dout9
  ,output [15:0] dout10
  ,output [15:0] dout11
  ,output [15:0] dout12
  ,output [15:0] dout13
  ,output [15:0] dout14
  ,output [15:0] dout15 
);

////////////////////////////////////////////////////
// regs
////////////////////////////////////////////////////
reg [15:0] dout0_r ;
reg [15:0] dout1_r ;
reg [15:0] dout2_r ;
reg [15:0] dout3_r ;
reg [15:0] dout4_r ;
reg [15:0] dout5_r ;
reg [15:0] dout6_r ;
reg [15:0] dout7_r ;
reg [15:0] dout8_r ;
reg [15:0] dout9_r ;
reg [15:0] dout10_r;
reg [15:0] dout11_r;
reg [15:0] dout12_r;
reg [15:0] dout13_r;
reg [15:0] dout14_r;
reg [15:0] dout15_r;

reg [15:0] mux_p_0;
reg [15:0] mux_p_1;
reg [15:0] mux_p_2;
reg [15:0] mux_p_3;
reg [15:0] mux_p_4;
reg [15:0] mux_p_5;
reg [15:0] mux_p_6;
reg [15:0] mux_p_7;
reg [15:0] mux_p_8;
reg [15:0] mux_p_9;
reg [15:0] mux_p_a;
reg [15:0] mux_p_b;
reg [15:0] mux_p_c;
reg [15:0] mux_p_d;
reg [15:0] mux_p_e;
reg [15:0] mux_p_f;

reg [1:0] dacif_vld_dly;
////////////////////////////////////////////////////
// intp mode select
////////////////////////////////////////////////////
always@(posedge clk) begin
  case(intp_mode)
    3'b000  : begin
              mux_p_0   <= {~din15[15],din15[14:0]};
              mux_p_1   <= 16'h8000;
              mux_p_2   <= 16'h8000;
              mux_p_3   <= 16'h8000;
              mux_p_4   <= 16'h8000;
              mux_p_5   <= 16'h8000;
              mux_p_6   <= 16'h8000;
              mux_p_7   <= 16'h8000;
              mux_p_8   <= 16'h8000;
              mux_p_9   <= 16'h8000;
              mux_p_a   <= 16'h8000;
              mux_p_b   <= 16'h8000;
              mux_p_c   <= 16'h8000;
              mux_p_d   <= 16'h8000;
              mux_p_e   <= 16'h8000;
              mux_p_f   <= 16'h8000; 
    end
    3'b001  : begin
              mux_p_0   <= {~din7[15],din7[14:0]};
              mux_p_1   <= {~din15[15],din15[14:0]};
              mux_p_2   <= 16'h8000  ;
              mux_p_3   <= 16'h8000  ;
              mux_p_4   <= 16'h8000  ;
              mux_p_5   <= 16'h8000  ;
              mux_p_6   <= 16'h8000  ;
              mux_p_7   <= 16'h8000  ;
              mux_p_8   <= 16'h8000  ;
              mux_p_9   <= 16'h8000  ;
              mux_p_a   <= 16'h8000  ;
              mux_p_b   <= 16'h8000  ;
              mux_p_c   <= 16'h8000  ;
              mux_p_d   <= 16'h8000  ;
              mux_p_e   <= 16'h8000  ;
              mux_p_f   <= 16'h8000  ; 
    end
    3'b010  : begin
              mux_p_0   <= {~din3[15],din3[14:0]}  ;
              mux_p_1   <= {~din7[15],din7[14:0]}  ;
              mux_p_2   <= {~din11[15],din11[14:0]}  ;
              mux_p_3   <= {~din15[15],din15[14:0]};
              mux_p_4   <= 16'h8000;
              mux_p_5   <= 16'h8000;
              mux_p_6   <= 16'h8000;
              mux_p_7   <= 16'h8000;
              mux_p_8   <= 16'h8000;
              mux_p_9   <= 16'h8000;
              mux_p_a   <= 16'h8000;
              mux_p_b   <= 16'h8000;
              mux_p_c   <= 16'h8000;
              mux_p_d   <= 16'h8000;
              mux_p_e   <= 16'h8000;
              mux_p_f   <= 16'h8000; 
    end
    3'b011  : begin
              mux_p_0   <= {~din1[15],din1[14:0]}  ;
              mux_p_1   <= {~din3[15],din3[14:0]}  ;
              mux_p_2   <= {~din5[15],din5[14:0]}  ;
              mux_p_3   <= {~din7[15],din7[14:0]}  ;
              mux_p_4   <= {~din9[15],din9[14:0]}  ;
              mux_p_5   <= {~din11[15],din11[14:0]};
              mux_p_6   <= {~din13[15],din13[14:0]};
              mux_p_7   <= {~din15[15],din15[14:0]};
              mux_p_8   <= 16'h8000 ;
              mux_p_9   <= 16'h8000 ;
              mux_p_a   <= 16'h8000 ;
              mux_p_b   <= 16'h8000 ;
              mux_p_c   <= 16'h8000 ;
              mux_p_d   <= 16'h8000 ;
              mux_p_e   <= 16'h8000 ;
              mux_p_f   <= 16'h8000 ;
    end
    3'b100  : begin
              mux_p_0   <= {~din0[15],din0[14:0]}  ;
              mux_p_1   <= {~din1[15],din1[14:0]}  ;
              mux_p_2   <= {~din2[15],din2[14:0]}  ;
              mux_p_3   <= {~din3[15],din3[14:0]}  ;
              mux_p_4   <= {~din4[15],din4[14:0]}  ;
              mux_p_5   <= {~din5[15],din5[14:0]}  ;
              mux_p_6   <= {~din6[15],din6[14:0]}  ;
              mux_p_7   <= {~din7[15],din7[14:0]}  ;
              mux_p_8   <= {~din8[15],din8[14:0]}  ;
              mux_p_9   <= {~din9[15],din9[14:0]}  ;
              mux_p_a   <= {~din10[15],din10[14:0]};
              mux_p_b   <= {~din11[15],din11[14:0]};
              mux_p_c   <= {~din12[15],din12[14:0]};
              mux_p_d   <= {~din13[15],din13[14:0]};
              mux_p_e   <= {~din14[15],din14[14:0]};
              mux_p_f   <= {~din15[15],din15[14:0]}; 
    end
    default : begin
              mux_p_0   <= 16'h8000;
              mux_p_1   <= 16'h8000;
              mux_p_2   <= 16'h8000;
              mux_p_3   <= 16'h8000;
              mux_p_4   <= 16'h8000;
              mux_p_5   <= 16'h8000;
              mux_p_6   <= 16'h8000;
              mux_p_7   <= 16'h8000;
              mux_p_8   <= 16'h8000;
              mux_p_9   <= 16'h8000;
              mux_p_a   <= 16'h8000;
              mux_p_b   <= 16'h8000;
              mux_p_c   <= 16'h8000;
              mux_p_d   <= 16'h8000;
              mux_p_e   <= 16'h8000;
              mux_p_f   <= 16'h8000; 
    end
  endcase
end  

////////////////////////////////////////////////////
// mode select
////////////////////////////////////////////////////
always @(posedge clk or negedge rstn) begin
  if(rstn == 1'b0) begin
    dout0_r  <= 16'h8000;
    dout1_r  <= 16'h8000;
    dout2_r  <= 16'h8000;
    dout3_r  <= 16'h8000; 
    dout4_r  <= 16'h8000;
    dout5_r  <= 16'h8000;
    dout6_r  <= 16'h8000;
    dout7_r  <= 16'h8000;
    dout8_r  <= 16'h8000;
    dout9_r  <= 16'h8000;
    dout10_r <= 16'h8000;
    dout11_r <= 16'h8000;
    dout12_r <= 16'h8000;
    dout13_r <= 16'h8000;
    dout14_r <= 16'h8000;
    dout15_r <= 16'h8000; 
  end
  else begin
    case(dac_mode_sel)
      2'b00    : begin
                 dout0_r  <= mux_p_0;
                 dout1_r  <= mux_p_1;
                 dout2_r  <= mux_p_2;
                 dout3_r  <= mux_p_3; 
                 dout4_r  <= mux_p_4;
                 dout5_r  <= mux_p_5;
                 dout6_r  <= mux_p_6;
                 dout7_r  <= mux_p_7;
                 dout8_r  <= mux_p_0;
                 dout9_r  <= mux_p_1;
                 dout10_r <= mux_p_2;
                 dout11_r <= mux_p_3;
                 dout12_r <= mux_p_4;
                 dout13_r <= mux_p_5;
                 dout14_r <= mux_p_6;
                 dout15_r <= mux_p_7;
      end
      2'b01    : begin
                 dout0_r  <= mux_p_0;
                 dout1_r  <= mux_p_1;
                 dout2_r  <= mux_p_2;
                 dout3_r  <= mux_p_3; 
                 dout4_r  <= mux_p_4;
                 dout5_r  <= mux_p_5;
                 dout6_r  <= mux_p_6;
                 dout7_r  <= mux_p_7;
                 dout8_r  <= ~mux_p_0;
                 dout9_r  <= ~mux_p_1;
                 dout10_r <= ~mux_p_2;
                 dout11_r <= ~mux_p_3;
                 dout12_r <= ~mux_p_4;
                 dout13_r <= ~mux_p_5;
                 dout14_r <= ~mux_p_6;
                 dout15_r <= ~mux_p_7;
      end
      2'b10    : begin
                 dout0_r  <= mux_p_0;
                 dout1_r  <= mux_p_2;
                 dout2_r  <= mux_p_4;
                 dout3_r  <= mux_p_6; 
                 dout4_r  <= mux_p_8;
                 dout5_r  <= mux_p_a;
                 dout6_r  <= mux_p_c;
                 dout7_r  <= mux_p_e;
                 dout8_r  <= mux_p_1;
                 dout9_r  <= mux_p_3;
                 dout10_r <= mux_p_5;
                 dout11_r <= mux_p_7;
                 dout12_r <= mux_p_9;
                 dout13_r <= mux_p_b;
                 dout14_r <= mux_p_d;
                 dout15_r <= mux_p_f;
      end
      2'b11    : begin
                 dout0_r  <= mux_p_0;
                 dout1_r  <= mux_p_1;
                 dout2_r  <= mux_p_2;
                 dout3_r  <= mux_p_3; 
                 dout4_r  <= mux_p_4;
                 dout5_r  <= mux_p_5;
                 dout6_r  <= mux_p_6;
                 dout7_r  <= mux_p_7;
                 dout8_r  <= mux_p_8;
                 dout9_r  <= mux_p_9;
                 dout10_r <= mux_p_a;
                 dout11_r <= mux_p_b;
                 dout12_r <= mux_p_c;
                 dout13_r <= mux_p_d;
                 dout14_r <= mux_p_e;
                 dout15_r <= mux_p_f;
      end
    endcase
  end
end

assign dout0  = dout0_r  ;
assign dout1  = dout1_r  ;
assign dout2  = dout2_r  ;
assign dout3  = dout3_r  ;
assign dout4  = dout4_r  ;
assign dout5  = dout5_r  ;
assign dout6  = dout6_r  ;
assign dout7  = dout7_r  ;
assign dout8  = dout8_r  ;
assign dout9  = dout9_r  ;
assign dout10 = dout10_r ;
assign dout11 = dout11_r ;
assign dout12 = dout12_r ;
assign dout13 = dout13_r ;
assign dout14 = dout14_r ;
assign dout15 = dout15_r ;

//vld
always @(posedge clk or negedge rstn) begin
  if(rstn == 1'b0) begin
     dacif_vld_dly <= 2'b0;
  end
  else begin
     dacif_vld_dly <= {dacif_vld_dly[0],din_vld};
  end
end 

assign dout_vld = dacif_vld_dly[1];

endmodule