//+FHDR-------------------------------------------------------------------------------------------------------- // Company: //----------------------------------------------------------------------------------------------------------------- // File Name : digital_top.v // Department : // Author : pwy // Author's Tel : //----------------------------------------------------------------------------------------------------------------- // Relese History // Version Date Author Description // 1.2 2024-04-16 pwy XYZ control the top-level module //----------------------------------------------------------------------------------------------------------------- // Keywords : // //----------------------------------------------------------------------------------------------------------------- // Parameter // //----------------------------------------------------------------------------------------------------------------- // Purpose : // //----------------------------------------------------------------------------------------------------------------- // Target Device: // Tool versions: //----------------------------------------------------------------------------------------------------------------- // Reuse Issues // Reset Strategy: // Clock Domains: // Critical Timing: // Asynchronous I/F: // Synthesizable (y/n): // Other: //-FHDR-------------------------------------------------------------------------------------------------------- `include "../define/chip_define.v" module digital_top ( //-------------------------clcok pin from pll------------------------------------------------- input clk // System Main Clock //-------------------------Power on reset pin from por---------------------------------------- ,input por_rstn // Power on reset, active low //------------------------------digital IO---------------------------------------------------- ,input async_rstn // hardware Reset, active low //sync ,input sync_in // Chip synchronization signal input, high pulse valid ,output sync_out // Chip synchronization signal output, high pulse valid //Feedback signal ,input [1 :0] ch0_feedback // Ch0 Feedback signals from the readout chip `ifdef CHANNEL_IS_FOUR ,input [1 :0] ch1_feedback // Ch1 Feedback signals from the readout chip ,input [1 :0] ch2_feedback // Ch2 Feedback signals from the readout chip ,input [1 :0] ch3_feedback // Ch3 Feedback signals from the readout chip `endif //config chip id ,input [4 :0] cfgid // During power-on initialization, the IO configuration // values are read as the chip ID number //spi port ,input sclk // Spi Clock ,input csn // Spi Chip Select active low ,input mosi // Spi Mosi ,output miso // Spi Miso ,output oen // Spi Miso output enable //irq ,output irq // Interrupt signal in the chip, high level active //------------------------------PLL cfg pin---------------------------------------------------- ,output ref_sel // Clock source selection for a frequency divider; // 1'b0:External clock source // 1'b1:internal phase-locked loop clock source ,output ref_en // Input reference clock enable // 1'b0:enable,1'b1:disable ,output ref_s2d_en // Referenced clock differential to single-ended conversion enable // 1'b0:enable,1'b1:disable ,output [6 :0] p_cnt // P counter ,output pfd_delay // PFD Dead Zone ,output pfd_dff_Set // Setting the PFD register,active high ,output pfd_dff_4and // PFD output polarity ,output [3 :0] spd_div // SPD Frequency Divider ,output spd_pulse_width // Pulse Width of SPD ,output spd_pulse_sw // Pulse sw of SPD ,output cpc_sel // current source selection ,output [1 :0] swcp_i // PTAT current switch ,output [3 :0] sw_ptat_r // PTAT current adjustment ,output [1 :0] sw_fll_cpi // Phase-locked loop charge pump current ,output sw_fll_delay // PLL Dead Zone ,output pfd_sel // PFD Loop selection ,output spd_sel // SPD Loop selection ,output fll_sel // FLL Loop selection ,output vco_tc // VCO temperature compensation ,output vco_tcr // VCO temperature compensation resistor ,output vco_gain_adj // VCO gain adjustment ,output vco_gain_adj_r // VCO gain adjustment resistor ,output [2 :0] vco_cur_adj // VCO current adjustment ,output vco_buff_en // VCO buff enable,active high ,output vco_en // VCO enable,active high ,output [2 :0] pll_dpwr_adj // PLL frequency division output power adjustment ,output [6 :0] vco_fb_adj // VCO frequency band adjustment ,output afc_en // AFC enable ,output afc_shutdown // AFC module shutdown signal ,output [0 :0] afc_det_speed // AFC detection speed ,output [0 :0] flag_out_sel // Read and choose the signs ,output afc_reset // AFC reset ,output [10 :0] afc_cnt // AFC frequency band adjustment function counter // counting time adjustment ,output [10 :0] afc_ld_cnt // Adjust the counting time of the AFC lock detection // feature counter ,output [3 :0] afc_pres // Adjusting the resolution of the AFC comparator ,output [14 :0] afc_ld_tcc // AFC Lock Detection Function Target Cycle Count ,output [14 :0] afc_fb_tcc // Target number of cycles for AFC frequency band // adjustment function ,output sync_clr // PLL div sync clr,low active ,output pll_rstn // PLL reset,active low ,output [0 :0] div_rstn_sel // div rstn select, 1'b0: ext clear, 1'b1:inter pll lock ,output [1 :0] test_clk_sel // test clk select, 2'b00:DIV1 clk, 2'b01:DIV2 clk, 2'b10:DIV4 clk, 2'b11:DIV8 clk ,output [0 :0] test_clk_oen // test clk output enable, 1'b0:disenable, 1'b1:enable ,output [7 :0] dig_clk_sel // digital main clk select, one hot code,bit[0]-->0 degree phase,bit[1]-->45 degree phase.....bit[7]-->315degree phae ,output clkrx_pdn // CLock Rx Power Down ,input pll_lock // PLL LOCK //------------------------------Ch0 DAC cfg pin---------------------------------------------------- ,output ch0_dac_Prbs ,output [14 :0] ch0_dac_Set0 ,output [14 :0] ch0_dac_Set1 ,output [14 :0] ch0_dac_Set2 ,output [14 :0] ch0_dac_Set3 ,output [14 :0] ch0_dac_Set4 ,output [14 :0] ch0_dac_Set5 ,output [14 :0] ch0_dac_Set6 ,output [14 :0] ch0_dac_Set7 ,output [14 :0] ch0_dac_Set8 ,output [14 :0] ch0_dac_Set9 ,output [14 :0] ch0_dac_Set10 ,output [14 :0] ch0_dac_Set11 ,output [14 :0] ch0_dac_Set12 ,output [14 :0] ch0_dac_Set13 ,output [14 :0] ch0_dac_Set14 ,output [14 :0] ch0_dac_Set15 ,output [2 :0] ch0_dac_addr ,output [2 :0] ch0_dac_dw ,output [8 :0] ch0_dac_ref ,output [16 :0] ch0_dac_Prbs_rst0 ,output [16 :0] ch0_dac_Prbs_set0 ,output [16 :0] ch0_dac_Prbs_rst1 ,output [16 :0] ch0_dac_Prbs_set1 ,output ch0_dac_Cal_sig ,output ch0_dac_Cal_rstn ,output ch0_dac_Cal_div_rstn ,input ch0_dac_Cal_end `ifdef CHANNEL_IS_FOUR //------------------------------Ch1 DAC cfg pin---------------------------------------------------- ,output ch1_dac_Prbs ,output [14 :0] ch1_dac_Set0 ,output [14 :0] ch1_dac_Set1 ,output [14 :0] ch1_dac_Set2 ,output [14 :0] ch1_dac_Set3 ,output [14 :0] ch1_dac_Set4 ,output [14 :0] ch1_dac_Set5 ,output [14 :0] ch1_dac_Set6 ,output [14 :0] ch1_dac_Set7 ,output [14 :0] ch1_dac_Set8 ,output [14 :0] ch1_dac_Set9 ,output [14 :0] ch1_dac_Set10 ,output [14 :0] ch1_dac_Set11 ,output [14 :0] ch1_dac_Set12 ,output [14 :0] ch1_dac_Set13 ,output [14 :0] ch1_dac_Set14 ,output [14 :0] ch1_dac_Set15 ,output [2 :0] ch1_dac_addr ,output [2 :0] ch1_dac_dw ,output [8 :0] ch1_dac_ref ,output [16 :0] ch1_dac_Prbs_rst0 ,output [16 :0] ch1_dac_Prbs_set0 ,output [16 :0] ch1_dac_Prbs_rst1 ,output [16 :0] ch1_dac_Prbs_set1 ,output ch1_dac_Cal_sig ,output ch1_dac_Cal_rstn ,output ch1_dac_Cal_div_rstn ,output ch1_dac_Digitalclk ,input ch1_dac_Cal_end //------------------------------Ch2 DAC cfg pin---------------------------------------------------- ,output ch2_dac_Prbs ,output [14 :0] ch2_dac_Set0 ,output [14 :0] ch2_dac_Set1 ,output [14 :0] ch2_dac_Set2 ,output [14 :0] ch2_dac_Set3 ,output [14 :0] ch2_dac_Set4 ,output [14 :0] ch2_dac_Set5 ,output [14 :0] ch2_dac_Set6 ,output [14 :0] ch2_dac_Set7 ,output [14 :0] ch2_dac_Set8 ,output [14 :0] ch2_dac_Set9 ,output [14 :0] ch2_dac_Set10 ,output [14 :0] ch2_dac_Set11 ,output [14 :0] ch2_dac_Set12 ,output [14 :0] ch2_dac_Set13 ,output [14 :0] ch2_dac_Set14 ,output [14 :0] ch2_dac_Set15 ,output [2 :0] ch2_dac_addr ,output [2 :0] ch2_dac_dw ,output [8 :0] ch2_dac_ref ,output [16 :0] ch2_dac_Prbs_rst0 ,output [16 :0] ch2_dac_Prbs_set0 ,output [16 :0] ch2_dac_Prbs_rst1 ,output [16 :0] ch2_dac_Prbs_set1 ,output ch2_dac_Cal_sig ,output ch2_dac_Cal_rstn ,output ch2_dac_Cal_div_rstn ,output ch2_dac_Digitalclk ,input ch2_dac_Cal_end //------------------------------Ch3 DAC cfg pin---------------------------------------------------- ,output ch3_dac_Prbs ,output [14 :0] ch3_dac_Set0 ,output [14 :0] ch3_dac_Set1 ,output [14 :0] ch3_dac_Set2 ,output [14 :0] ch3_dac_Set3 ,output [14 :0] ch3_dac_Set4 ,output [14 :0] ch3_dac_Set5 ,output [14 :0] ch3_dac_Set6 ,output [14 :0] ch3_dac_Set7 ,output [14 :0] ch3_dac_Set8 ,output [14 :0] ch3_dac_Set9 ,output [14 :0] ch3_dac_Set10 ,output [14 :0] ch3_dac_Set11 ,output [14 :0] ch3_dac_Set12 ,output [14 :0] ch3_dac_Set13 ,output [14 :0] ch3_dac_Set14 ,output [14 :0] ch3_dac_Set15 ,output [2 :0] ch3_dac_addr ,output [2 :0] ch3_dac_dw ,output [8 :0] ch3_dac_ref ,output [16 :0] ch3_dac_Prbs_rst0 ,output [16 :0] ch3_dac_Prbs_set0 ,output [16 :0] ch3_dac_Prbs_rst1 ,output [16 :0] ch3_dac_Prbs_set1 ,output ch3_dac_Cal_sig ,output ch3_dac_Cal_rstn ,output ch3_dac_Cal_div_rstn ,output ch3_dac_Digitalclk ,input ch3_dac_Cal_end `endif //------------------------------Ch0 DSP data out---------------------------------------------------- `ifdef CHANNEL_XY_ON ,output [15 :0] ch0_xy_dsp_dout0 ,output [15 :0] ch0_xy_dsp_dout1 ,output [15 :0] ch0_xy_dsp_dout2 ,output [15 :0] ch0_xy_dsp_dout3 ,output [15 :0] ch0_xy_dsp_dout4 ,output [15 :0] ch0_xy_dsp_dout5 ,output [15 :0] ch0_xy_dsp_dout6 ,output [15 :0] ch0_xy_dsp_dout7 ,output [15 :0] ch0_xy_dsp_dout8 ,output [15 :0] ch0_xy_dsp_dout9 ,output [15 :0] ch0_xy_dsp_dout10 ,output [15 :0] ch0_xy_dsp_dout11 ,output [15 :0] ch0_xy_dsp_dout12 ,output [15 :0] ch0_xy_dsp_dout13 ,output [15 :0] ch0_xy_dsp_dout14 ,output [15 :0] ch0_xy_dsp_dout15 `endif `ifdef CHANNEL_Z_ON ,output [15 :0] ch0_z_dsp_dout0 ,output [15 :0] ch0_z_dsp_dout1 ,output [15 :0] ch0_z_dsp_dout2 ,output [15 :0] ch0_z_dsp_dout3 `endif `ifdef CHANNEL_IS_FOUR //------------------------------Ch1 DSP data out---------------------------------------------------- `ifdef CHANNEL_XY_ON ,output [15 :0] ch1_xy_dsp_dout0 ,output [15 :0] ch1_xy_dsp_dout1 ,output [15 :0] ch1_xy_dsp_dout2 ,output [15 :0] ch1_xy_dsp_dout3 ,output [15 :0] ch1_xy_dsp_dout4 ,output [15 :0] ch1_xy_dsp_dout5 ,output [15 :0] ch1_xy_dsp_dout6 ,output [15 :0] ch1_xy_dsp_dout7 ,output [15 :0] ch1_xy_dsp_dout8 ,output [15 :0] ch1_xy_dsp_dout9 ,output [15 :0] ch1_xy_dsp_dout10 ,output [15 :0] ch1_xy_dsp_dout11 ,output [15 :0] ch1_xy_dsp_dout12 ,output [15 :0] ch1_xy_dsp_dout13 ,output [15 :0] ch1_xy_dsp_dout14 ,output [15 :0] ch1_xy_dsp_dout15 `endif `ifdef CHANNEL_Z_ON ,output [15 :0] ch1_z_dsp_dout0 ,output [15 :0] ch1_z_dsp_dout1 ,output [15 :0] ch1_z_dsp_dout2 ,output [15 :0] ch1_z_dsp_dout3 `endif //------------------------------Ch2 DSP data out---------------------------------------------------- `ifdef CHANNEL_XY_ON ,output [15 :0] ch2_xy_dsp_dout0 ,output [15 :0] ch2_xy_dsp_dout1 ,output [15 :0] ch2_xy_dsp_dout2 ,output [15 :0] ch2_xy_dsp_dout3 ,output [15 :0] ch2_xy_dsp_dout4 ,output [15 :0] ch2_xy_dsp_dout5 ,output [15 :0] ch2_xy_dsp_dout6 ,output [15 :0] ch2_xy_dsp_dout7 ,output [15 :0] ch2_xy_dsp_dout8 ,output [15 :0] ch2_xy_dsp_dout9 ,output [15 :0] ch2_xy_dsp_dout10 ,output [15 :0] ch2_xy_dsp_dout11 ,output [15 :0] ch2_xy_dsp_dout12 ,output [15 :0] ch2_xy_dsp_dout13 ,output [15 :0] ch2_xy_dsp_dout14 ,output [15 :0] ch2_xy_dsp_dout15 `endif `ifdef CHANNEL_Z_ON ,output [15 :0] ch2_z_dsp_dout0 ,output [15 :0] ch2_z_dsp_dout1 ,output [15 :0] ch2_z_dsp_dout2 ,output [15 :0] ch2_z_dsp_dout3 `endif //------------------------------Ch3 DSP data out---------------------------------------------------- `ifdef CHANNEL_XY_ON ,output [15 :0] ch3_xy_dsp_dout0 ,output [15 :0] ch3_xy_dsp_dout1 ,output [15 :0] ch3_xy_dsp_dout2 ,output [15 :0] ch3_xy_dsp_dout3 ,output [15 :0] ch3_xy_dsp_dout4 ,output [15 :0] ch3_xy_dsp_dout5 ,output [15 :0] ch3_xy_dsp_dout6 ,output [15 :0] ch3_xy_dsp_dout7 ,output [15 :0] ch3_xy_dsp_dout8 ,output [15 :0] ch3_xy_dsp_dout9 ,output [15 :0] ch3_xy_dsp_dout10 ,output [15 :0] ch3_xy_dsp_dout11 ,output [15 :0] ch3_xy_dsp_dout12 ,output [15 :0] ch3_xy_dsp_dout13 ,output [15 :0] ch3_xy_dsp_dout14 ,output [15 :0] ch3_xy_dsp_dout15 `endif `ifdef CHANNEL_Z_ON ,output [15 :0] ch3_z_dsp_dout0 ,output [15 :0] ch3_z_dsp_dout1 ,output [15 :0] ch3_z_dsp_dout2 ,output [15 :0] ch3_z_dsp_dout3 `endif `endif ); //------------------------------spi_slave instantiation start---------------------------------- // spi_slave //--------------------------------------------------------------------------------------------- sram_if#(25,32) mst(clk); sram_if#(20,32) slv[25:0](clk); //connect pll wire [31 :0] pll_wrdata ; wire pll_wren ; wire [7 :0] pll_rwaddr ; wire pll_rden ; wire [31 :0] pll_rddata ; //connect system wire [31 :0] sys_wrdata ; wire sys_wren ; wire [24 :0] sys_rwaddr ; wire sys_rden ; wire [31 :0] sys_rddata ; wire pll_rstn_o; assign pll_rstn = pll_rstn_o; assign mst.wben = 4'hf; spi_slave U_spi_slave ( .clk ( clk ) ,.rst_n ( pll_rstn_o ) ,.cfgid ( cfgid ) ,.sclk ( sclk ) ,.csn ( csn ) ,.mosi ( mosi ) ,.miso ( miso ) ,.oen ( oen ) ,.pll_wrdata ( pll_wrdata ) ,.pll_wren ( pll_wren ) ,.pll_rwaddr ( pll_rwaddr ) ,.pll_rden ( pll_rden ) ,.pll_rddata ( pll_rddata ) ,.sys_wrdata ( mst.din ) ,.sys_wren ( mst.wren ) ,.sys_rwaddr ( mst.addr ) ,.sys_rden ( mst.rden ) ,.sys_rddata ( mst.dout ) ); //--------------------------------------------------------------------------------------------- // spi_slave //------------------------------spi_slave instantiation end------------------------------------ //------------------------------intpll_regfile instantiation start----------------------------- // intpll_regfile //--------------------------------------------------------------------------------------------- wire div_sync_en ; wire sync_oe ; intpll_regfile U_intpll_regfile ( .clk ( sclk ) ,.rst_n ( pll_rstn_o ) ,.wrdata ( pll_wrdata ) ,.wren ( pll_wren ) ,.rwaddr ( pll_rwaddr[7:0] ) ,.rden ( pll_rden ) ,.rddata ( pll_rddata ) ,.ref_sel ( ref_sel ) ,.ref_en ( ref_en ) ,.ref_s2d_en ( ref_s2d_en ) ,.p_cnt ( p_cnt ) ,.pfd_delay ( pfd_delay ) ,.pfd_dff_Set ( pfd_dff_Set ) ,.pfd_dff_4and ( pfd_dff_4and ) ,.spd_div ( spd_div ) ,.spd_pulse_width ( spd_pulse_width ) ,.spd_pulse_sw ( spd_pulse_sw ) ,.cpc_sel ( cpc_sel ) ,.swcp_i ( swcp_i ) ,.sw_ptat_r ( sw_ptat_r ) ,.sw_fll_cpi ( sw_fll_cpi ) ,.sw_fll_delay ( sw_fll_delay ) ,.pfd_sel ( pfd_sel ) ,.spd_sel ( spd_sel ) ,.fll_sel ( fll_sel ) ,.vco_tc ( vco_tc ) ,.vco_tcr ( vco_tcr ) ,.vco_gain_adj ( vco_gain_adj ) ,.vco_gain_adj_r ( vco_gain_adj_r ) ,.vco_cur_adj ( vco_cur_adj ) ,.vco_buff_en ( vco_buff_en ) ,.vco_en ( vco_en ) ,.pll_dpwr_adj ( pll_dpwr_adj ) ,.vco_fb_adj ( vco_fb_adj ) ,.afc_en ( afc_en ) ,.afc_shutdown ( afc_shutdown ) ,.afc_det_speed ( afc_det_speed ) ,.flag_out_sel ( flag_out_sel ) ,.afc_reset ( afc_reset ) ,.afc_cnt ( afc_cnt ) ,.afc_ld_cnt ( afc_ld_cnt ) ,.afc_pres ( afc_pres ) ,.afc_ld_tcc ( afc_ld_tcc ) ,.afc_fb_tcc ( afc_fb_tcc ) ,.div_rstn_sel ( div_rstn_sel ) ,.test_clk_sel ( test_clk_sel ) ,.test_clk_oen ( test_clk_oen ) ,.dig_clk_sel ( dig_clk_sel ) ,.div_sync_en ( div_sync_en ) ,.sync_oe ( sync_oe ) ,.clkrx_pdn ( clkrx_pdn ) ,.pll_lock ( pll_lock ) ); //--------------------------------------------------------------------------------------------- // intpll_regfile //------------------------------intpll_regfile instantiation end------------------------------- //----------------------------spi_bus_decoder instantiation start------------------------------ // intpll_regfile //--------------------------------------------------------------------------------------------- spi_bus_decoder #( .SLVNUM ( `SLVNUM ) ,.SPIBUS_CMD_REG ( `SPIBUS_CMD_REG ) ,.SPIBUS_OUT_REG ( `SPIBUS_OUT_REG ) ) U_spi_bus_decoder ( .clk ( clk ) ,.rst_n ( pll_rstn_o ) ,.mst ( mst ) ,.slv ( slv ) ); //--------------------------------------------------------------------------------------------- // spi_bus_decoder //------------------------------spi_bus_decoder instantiation end------------------------------ //-----------------------------system_regfile instantiation start------------------------------ // system_regfile as slave device 0 //--------------------------------------------------------------------------------------------- wire dbg_enable ; wire dbg_data_sel ; wire [3 :0] dbg_ch_sel ; wire dbg_upd ; wire ch0_proc_cft ; wire ch0_ldst_addr_unalgn ; wire ch0_dec_err ; wire ch0_exit_irq ; wire ch1_proc_cft ; wire ch1_ldst_addr_unalgn ; wire ch1_dec_err ; wire ch1_exit_irq ; wire ch2_proc_cft ; wire ch2_ldst_addr_unalgn ; wire ch2_dec_err ; wire ch2_exit_irq ; wire ch3_proc_cft ; wire ch3_ldst_addr_unalgn ; wire ch3_dec_err ; wire ch3_exit_irq ; wire sys_soft_rstn ; wire ch0_soft_rstn ; wire ch1_soft_rstn ; wire ch2_soft_rstn ; wire ch3_soft_rstn ; //When designed for single-channel, open this macro `ifndef CHANNEL_IS_FOUR assign ch1_proc_cft = 1'b0; assign ch1_ldst_addr_unalgn = 1'b0; assign ch1_dec_err = 1'b0; assign ch1_exit_irq = 1'b0; assign ch2_proc_cft = 1'b0; assign ch2_ldst_addr_unalgn = 1'b0; assign ch2_dec_err = 1'b0; assign ch2_exit_irq = 1'b0; assign ch3_proc_cft = 1'b0; assign ch3_ldst_addr_unalgn = 1'b0; assign ch3_dec_err = 1'b0; assign ch3_exit_irq = 1'b0; `endif system_regfile U_system_regfile ( .clk ( clk ) ,.rst_n ( pll_rstn_o ) ,.wrdata ( slv[0].din ) ,.wren ( slv[0].wren ) ,.rwaddr ( slv[0].addr[15:0] ) ,.rden ( slv[0].rden ) ,.rddata ( slv[0].dout ) ,.dbg_enable ( dbg_enable ) ,.dbg_data_sel ( dbg_data_sel ) ,.dbg_ch_sel ( dbg_ch_sel ) ,.dbg_upd ( dbg_upd ) ,.ch0_proc_cft ( ch0_proc_cft ) ,.ch0_ldst_addr_unalgn ( ch0_ldst_addr_unalgn ) ,.ch0_dec_err ( ch0_dec_err ) ,.ch0_exit_irq ( ch0_exit_irq ) ,.ch1_proc_cft ( ch1_proc_cft ) ,.ch1_ldst_addr_unalgn ( ch1_ldst_addr_unalgn ) ,.ch1_dec_err ( ch1_dec_err ) ,.ch1_exit_irq ( ch1_exit_irq ) ,.ch2_proc_cft ( ch2_proc_cft ) ,.ch2_ldst_addr_unalgn ( ch2_ldst_addr_unalgn ) ,.ch2_dec_err ( ch2_dec_err ) ,.ch2_exit_irq ( ch2_exit_irq ) ,.ch3_proc_cft ( ch3_proc_cft ) ,.ch3_ldst_addr_unalgn ( ch3_ldst_addr_unalgn ) ,.ch3_dec_err ( ch3_dec_err ) ,.ch3_exit_irq ( ch3_exit_irq ) ,.sys_soft_rstn ( sys_soft_rstn ) ,.ch0_soft_rstn ( ch0_soft_rstn ) ,.ch1_soft_rstn ( ch1_soft_rstn ) ,.ch2_soft_rstn ( ch2_soft_rstn ) ,.ch3_soft_rstn ( ch3_soft_rstn ) ,.irq ( irq ) ); //--------------------------------------------------------------------------------------------- // system_regfile //------------------------------system_regfile instantiation end------------------------------- //--------------------------------------------------------------------------------------------- // sync_int //------------------------------sync_int instantiation start----------------------------------- wire sync_oe_s; syncer #(1, 2) sync_oe_syncer (clk, pll_rstn_o, sync_oe, sync_oe_s); wire div_sync_en_s; syncer #(1, 2) div_sync_en_syncer (clk, pll_rstn_o, div_sync_en, div_sync_en_s); wire sync_int; sync_buf #( ) U_sync_buf ( .clk ( clk ) ,.rst_n ( pll_rstn_o ) ,.ext_ena ( sync_oe_s ) ,.clr_ena_sync ( div_sync_en_s ) ,.clr_ena ( div_sync_en ) ,.sync_in ( sync_in ) ,.sync_int ( sync_int ) ,.sync_ext ( sync_out ) ,.sync_clr ( sync_clr ) ); //--------------------------------------------------------------------------------------------- // sync_int //------------------------------sync_int instantiation end------------------------------------- //--------------------------------------------------------------------------------------------- // rst_gen_unit instantiation start //--------------------------------------------------------------------------------------------- wire ch0_rstn_o; wire ch1_rstn_o; wire ch2_rstn_o; wire ch3_rstn_o; rst_gen_unit U_rst_gen_unit ( .async_rstn_i ( async_rstn ) ,.por_rstn_i ( por_rstn ) ,.sys_soft_resetn_i ( sys_soft_rstn ) ,.ch0_soft_rstn_i ( ch0_soft_rstn ) ,.ch1_soft_rstn_i ( ch1_soft_rstn ) ,.ch2_soft_rstn_i ( ch2_soft_rstn ) ,.ch3_soft_rstn_i ( ch3_soft_rstn ) ,.clk ( clk ) ,.ch0_rstn_o ( ch0_rstn_o ) ,.ch1_rstn_o ( ch1_rstn_o ) ,.ch2_rstn_o ( ch2_rstn_o ) ,.ch3_rstn_o ( ch3_rstn_o ) ,.pll_rstn_o ( pll_rstn_o ) ); //--------------------------------------------------------------------------------------------- // rst_gen_unit instantiation end //--------------------------------------------------------------------------------------------- //--------------------------------------------------------------------------------------------- // channel 0 instantiation start //--------------------------------------------------------------------------------------------- wire [15:0] ch0_awg_data_i ; wire [15:0] ch0_awg_data_q ; wire [0 :0] ch0_awg_vld ; `ifdef CHANNEL_XY_ON wire ch0_xy_dsp_dout_vld ; `endif channel_top U0_channel_top ( .clk ( clk ) ,.rst_n ( ch0_rstn_o ) ,.sync_int ( sync_int ) ,.dec_o_ilegl ( ch0_dec_err ) ,.agu_o_addr_unalgn ( ch0_ldst_addr_unalgn ) ,.awg_proc_cft ( ch0_proc_cft ) ,.mcu_ext_o_intr ( ch0_exit_irq ) ,.fb_st_in ( ch0_feedback ) //ch0 itcm addr space --> 0x0010_0000 ~ 0x001F_FFFF ,.itcm_i_rwaddr ( slv[1].addr[14:0] ) ,.itcm_i_wrdata ( slv[1].din ) ,.itcm_i_wren ( slv[1].wren ) ,.itcm_i_wrmask ( 4'h0 ) ,.itcm_i_rden ( slv[1].rden ) ,.itcm_o_rddata ( slv[1].dout ) //ch0 itcm addr space --> 0x0020_0000 ~ 0x002F_FFFF ,.dtcm_i_rwaddr ( slv[2].addr[14:0] ) ,.dtcm_i_wrdata ( slv[2].din ) ,.dtcm_i_wren ( slv[2].wren ) ,.dtcm_i_wrmask ( 4'h0 ) ,.dtcm_i_rden ( slv[2].rden ) ,.dtcm_o_rddata ( slv[2].dout ) //ch0 dtcm addr space --> 0x0030_0000 ~ 0x003F_FFFF ,.ctrl_rwaddr ( slv[3].addr[15:0] ) ,.ctrl_wrdata ( slv[3].din ) ,.ctrl_wren ( slv[3].wren ) ,.ctrl_rden ( slv[3].rden ) ,.ctrl_rddata ( slv[3].dout ) //ch0 envelope ID addr space --> 0x0040_0000 ~ 0x004F_FFFF ,.enve_id_brwaddr ( slv[4].addr[7:0] ) ,.enve_id_bwrdata ( slv[4].din ) ,.enve_id_bwren ( slv[4].wren ) ,.enve_id_brden ( slv[4].rden ) ,.enve_id_brddata ( slv[4].dout ) //ch0 envelope memory addr space --> 0x0050_0000 ~ 0x005F_FFFF ,.enve_brwaddr ( slv[5].addr[14:0] ) ,.enve_bwrdata ( slv[5].din ) ,.enve_bwren ( slv[5].wren ) ,.enve_brden ( slv[5].rden ) ,.enve_brddata ( slv[5].dout ) //ch0 dac regfile addr space --> 0x0060_0000 ~ 0x006F_FFFF ,.dac_rwaddr ( slv[6].addr[15:0] ) ,.dac_wrdata ( slv[6].din ) ,.dac_wren ( slv[6].wren ) ,.dac_rden ( slv[6].rden ) ,.dac_rddata ( slv[6].dout ) ,.dac_Prbs ( ch0_dac_Prbs ) ,.dac_Set0 ( ch0_dac_Set0 ) ,.dac_Set1 ( ch0_dac_Set1 ) ,.dac_Set2 ( ch0_dac_Set2 ) ,.dac_Set3 ( ch0_dac_Set3 ) ,.dac_Set4 ( ch0_dac_Set4 ) ,.dac_Set5 ( ch0_dac_Set5 ) ,.dac_Set6 ( ch0_dac_Set6 ) ,.dac_Set7 ( ch0_dac_Set7 ) ,.dac_Set8 ( ch0_dac_Set8 ) ,.dac_Set9 ( ch0_dac_Set9 ) ,.dac_Set10 ( ch0_dac_Set10 ) ,.dac_Set11 ( ch0_dac_Set11 ) ,.dac_Set12 ( ch0_dac_Set12 ) ,.dac_Set13 ( ch0_dac_Set13 ) ,.dac_Set14 ( ch0_dac_Set14 ) ,.dac_Set15 ( ch0_dac_Set15 ) ,.dac_addr ( ch0_dac_addr ) ,.dac_dw ( ch0_dac_dw ) ,.dac_ref ( ch0_dac_ref ) ,.dac_Prbs_rst0 ( ch0_dac_Prbs_rst0 ) ,.dac_Prbs_set0 ( ch0_dac_Prbs_set0 ) ,.dac_Prbs_rst1 ( ch0_dac_Prbs_rst1 ) ,.dac_Prbs_set1 ( ch0_dac_Prbs_set1 ) ,.dac_Cal_sig ( ch0_dac_Cal_sig ) ,.dac_Cal_rstn ( ch0_dac_Cal_rstn ) ,.Cal_div_rstn ( ch0_dac_Cal_div_rstn ) ,.dac_Cal_end ( ch0_dac_Cal_end ) ,.awg_data_i_o ( ch0_awg_data_i ) ,.awg_data_q_o ( ch0_awg_data_q ) ,.awg_vld_o ( ch0_awg_vld ) `ifdef CHANNEL_XY_ON ,.xy_dsp_dout0 ( ch0_xy_dsp_dout0 ) ,.xy_dsp_dout1 ( ch0_xy_dsp_dout1 ) ,.xy_dsp_dout2 ( ch0_xy_dsp_dout2 ) ,.xy_dsp_dout3 ( ch0_xy_dsp_dout3 ) ,.xy_dsp_dout4 ( ch0_xy_dsp_dout4 ) ,.xy_dsp_dout5 ( ch0_xy_dsp_dout5 ) ,.xy_dsp_dout6 ( ch0_xy_dsp_dout6 ) ,.xy_dsp_dout7 ( ch0_xy_dsp_dout7 ) ,.xy_dsp_dout8 ( ch0_xy_dsp_dout8 ) ,.xy_dsp_dout9 ( ch0_xy_dsp_dout9 ) ,.xy_dsp_dout10 ( ch0_xy_dsp_dout10 ) ,.xy_dsp_dout11 ( ch0_xy_dsp_dout11 ) ,.xy_dsp_dout12 ( ch0_xy_dsp_dout12 ) ,.xy_dsp_dout13 ( ch0_xy_dsp_dout13 ) ,.xy_dsp_dout14 ( ch0_xy_dsp_dout14 ) ,.xy_dsp_dout15 ( ch0_xy_dsp_dout15 ) ,.xy_dsp_dout_vld ( ch0_xy_dsp_dout_vld ) `endif `ifdef CHANNEL_Z_ON ,.z_dsp_dout0 ( ch0_z_dsp_dout0 ) ,.z_dsp_dout1 ( ch0_z_dsp_dout1 ) ,.z_dsp_dout2 ( ch0_z_dsp_dout2 ) ,.z_dsp_dout3 ( ch0_z_dsp_dout3 ) `endif ); //--------------------------------------------------------------------------------------------- // channel 0 instantiation end //--------------------------------------------------------------------------------------------- `ifdef CHANNEL_IS_FOUR //--------------------------------------------------------------------------------------------- // channel 1 instantiation start //--------------------------------------------------------------------------------------------- wire [15:0] ch1_awg_data_i ; wire [15:0] ch1_awg_data_q ; wire [15:0] ch1_awg_vld ; `ifdef CHANNEL_XY_ON wire ch1_xy_dsp_dout_vld ; `endif channel_top U1_channel_top ( .clk ( clk ) ,.rst_n ( ch1_rstn_o ) ,.sync_int ( sync_int ) ,.dec_o_ilegl ( ch1_dec_err ) ,.agu_o_addr_unalgn ( ch1_ldst_addr_unalgn ) ,.awg_proc_cft ( ch1_proc_cft ) ,.mcu_ext_o_intr ( ch1_exit_irq ) ,.fb_st_in ( ch1_feedback ) //ch1 itcm addr space --> 0x0070_0000 ~ 0x007F_FFFF ,.itcm_i_rwaddr ( slv[7].addr[14:0] ) ,.itcm_i_wrdata ( slv[7].din ) ,.itcm_i_wren ( slv[7].wren ) ,.itcm_i_wrmask ( 4'h0 ) ,.itcm_i_rden ( slv[7].rden ) ,.itcm_o_rddata ( slv[7].dout ) //ch1 itcm addr space --> 0x0080_0000 ~ 0x008F_FFFF ,.dtcm_i_rwaddr ( slv[8].addr[14:0] ) ,.dtcm_i_wrdata ( slv[8].din ) ,.dtcm_i_wren ( slv[8].wren ) ,.dtcm_i_wrmask ( 4'h0 ) ,.dtcm_i_rden ( slv[8].rden ) ,.dtcm_o_rddata ( slv[8].dout ) //ch1 dtcm addr space --> 0x0090_0000 ~ 0x009F_FFFF ,.ctrl_rwaddr ( slv[9].addr[15:0] ) ,.ctrl_wrdata ( slv[9].din ) ,.ctrl_wren ( slv[9].wren ) ,.ctrl_rden ( slv[9].rden ) ,.ctrl_rddata ( slv[9].dout ) //ch1 envelope ID addr space --> 0x00A0_0000 ~ 0x00AF_FFFF ,.enve_id_brwaddr ( slv[10].addr[7:0] ) ,.enve_id_bwrdata ( slv[10].din ) ,.enve_id_bwren ( slv[10].wren ) ,.enve_id_brden ( slv[10].rden ) ,.enve_id_brddata ( slv[10].dout ) //ch1 envelope memory addr space --> 0x00B0_0000 ~ 0x0005F_FFFF ,.enve_brwaddr ( slv[11].addr[14:0] ) ,.enve_bwrdata ( slv[11].din ) ,.enve_bwren ( slv[11].wren ) ,.enve_brden ( slv[11].rden ) ,.enve_brddata ( slv[11].dout ) //ch1 dac regfile addr space --> 0x00C0_0000 ~ 0x00CF_FFFFF ,.dac_rwaddr ( slv[12].addr[15:0] ) ,.dac_wrdata ( slv[12].din ) ,.dac_wren ( slv[12].wren ) ,.dac_rden ( slv[12].rden ) ,.dac_rddata ( slv[12].dout ) ,.dac_Prbs ( ch1_dac_Prbs ) ,.dac_Set0 ( ch1_dac_Set0 ) ,.dac_Set1 ( ch1_dac_Set1 ) ,.dac_Set2 ( ch1_dac_Set2 ) ,.dac_Set3 ( ch1_dac_Set3 ) ,.dac_Set4 ( ch1_dac_Set4 ) ,.dac_Set5 ( ch1_dac_Set5 ) ,.dac_Set6 ( ch1_dac_Set6 ) ,.dac_Set7 ( ch1_dac_Set7 ) ,.dac_Set8 ( ch1_dac_Set8 ) ,.dac_Set9 ( ch1_dac_Set9 ) ,.dac_Set10 ( ch1_dac_Set10 ) ,.dac_Set11 ( ch1_dac_Set11 ) ,.dac_Set12 ( ch1_dac_Set12 ) ,.dac_Set13 ( ch1_dac_Set13 ) ,.dac_Set14 ( ch1_dac_Set14 ) ,.dac_Set15 ( ch1_dac_Set15 ) ,.dac_addr ( ch1_dac_addr ) ,.dac_dw ( ch1_dac_dw ) ,.dac_ref ( ch1_dac_ref ) ,.dac_Prbs_rst0 ( ch1_dac_Prbs_rst0 ) ,.dac_Prbs_set0 ( ch1_dac_Prbs_set0 ) ,.dac_Prbs_rst1 ( ch1_dac_Prbs_rst1 ) ,.dac_Prbs_set1 ( ch1_dac_Prbs_set1 ) ,.dac_Cal_sig ( ch1_dac_Cal_sig ) ,.dac_Cal_rstn ( ch1_dac_Cal_rstn ) ,.Cal_div_rstn ( ch1_dac_Cal_div_rstn ) ,.dac_Cal_end ( ch1_dac_Cal_end ) ,.awg_data_i_o ( ch1_awg_data_i ) ,.awg_data_q_o ( ch1_awg_data_q ) ,.awg_vld_o ( ch1_awg_vld ) `ifdef CHANNEL_XY_ON ,.xy_dsp_dout0 ( ch1_xy_dsp_dout0 ) ,.xy_dsp_dout1 ( ch1_xy_dsp_dout1 ) ,.xy_dsp_dout2 ( ch1_xy_dsp_dout2 ) ,.xy_dsp_dout3 ( ch1_xy_dsp_dout3 ) ,.xy_dsp_dout4 ( ch1_xy_dsp_dout4 ) ,.xy_dsp_dout5 ( ch1_xy_dsp_dout5 ) ,.xy_dsp_dout6 ( ch1_xy_dsp_dout6 ) ,.xy_dsp_dout7 ( ch1_xy_dsp_dout7 ) ,.xy_dsp_dout8 ( ch1_xy_dsp_dout8 ) ,.xy_dsp_dout9 ( ch1_xy_dsp_dout9 ) ,.xy_dsp_dout10 ( ch1_xy_dsp_dout10 ) ,.xy_dsp_dout11 ( ch1_xy_dsp_dout11 ) ,.xy_dsp_dout12 ( ch1_xy_dsp_dout12 ) ,.xy_dsp_dout13 ( ch1_xy_dsp_dout13 ) ,.xy_dsp_dout14 ( ch1_xy_dsp_dout14 ) ,.xy_dsp_dout15 ( ch1_xy_dsp_dout15 ) ,.xy_dsp_dout_vld ( ch1_xy_dsp_dout_vld ) `endif `ifdef CHANNEL_Z_ON ,.z_dsp_dout0 ( ch1_z_dsp_dout0 ) ,.z_dsp_dout1 ( ch1_z_dsp_dout1 ) ,.z_dsp_dout2 ( ch1_z_dsp_dout2 ) ,.z_dsp_dout3 ( ch1_z_dsp_dout3 ) `endif ); //--------------------------------------------------------------------------------------------- // channel 1 instantiation end //--------------------------------------------------------------------------------------------- //--------------------------------------------------------------------------------------------- // channel 2 instantiation start //--------------------------------------------------------------------------------------------- wire [15:0] ch2_awg_data_i ; wire [15:0] ch2_awg_data_q ; wire [15:0] ch2_awg_vld ; `ifdef CHANNEL_XY_ON wire ch2_xy_dsp_dout_vld ; `endif channel_top U2_channel_top ( .clk ( clk ) ,.rst_n ( ch2_rstn_o ) ,.sync_int ( sync_int ) ,.dec_o_ilegl ( ch2_dec_err ) ,.agu_o_addr_unalgn ( ch2_ldst_addr_unalgn ) ,.awg_proc_cft ( ch2_proc_cft ) ,.mcu_ext_o_intr ( ch2_exit_irq ) ,.fb_st_in ( ch2_feedback ) //ch1 itcm addr space --> 0x00D0_0000 ~ 0x00DF_FFFF ,.itcm_i_rwaddr ( slv[13].addr[14:0] ) ,.itcm_i_wrdata ( slv[13].din ) ,.itcm_i_wren ( slv[13].wren ) ,.itcm_i_wrmask ( 4'h0 ) ,.itcm_i_rden ( slv[13].rden ) ,.itcm_o_rddata ( slv[13].dout ) //ch1 itcm addr space --> 0x00E0_0000 ~ 0x00EF_FFFF ,.dtcm_i_rwaddr ( slv[14].addr[14:0] ) ,.dtcm_i_wrdata ( slv[14].din ) ,.dtcm_i_wren ( slv[14].wren ) ,.dtcm_i_wrmask ( 4'h0 ) ,.dtcm_i_rden ( slv[14].rden ) ,.dtcm_o_rddata ( slv[14].dout ) //ch1 dtcm addr space --> 0x00F0_0000 ~ 0x00FF_FFFF ,.ctrl_rwaddr ( slv[15].addr[15:0] ) ,.ctrl_wrdata ( slv[15].din ) ,.ctrl_wren ( slv[15].wren ) ,.ctrl_rden ( slv[15].rden ) ,.ctrl_rddata ( slv[15].dout ) //ch1 envelope ID addr space --> 0x0100_0000 ~ 0x010F_FFFF ,.enve_id_brwaddr ( slv[16].addr[7:0] ) ,.enve_id_bwrdata ( slv[16].din ) ,.enve_id_bwren ( slv[16].wren ) ,.enve_id_brden ( slv[16].rden ) ,.enve_id_brddata ( slv[16].dout ) //ch1 envelope memory addr space --> 0x0110_0000 ~ 0x0105F_FFFF ,.enve_brwaddr ( slv[17].addr[14:0] ) ,.enve_bwrdata ( slv[17].din ) ,.enve_bwren ( slv[17].wren ) ,.enve_brden ( slv[17].rden ) ,.enve_brddata ( slv[17].dout ) //ch1 dac regfile addr space --> 0x0120_0000 ~ 0x012F_FFFFF ,.dac_rwaddr ( slv[18].addr[15:0] ) ,.dac_wrdata ( slv[18].din ) ,.dac_wren ( slv[18].wren ) ,.dac_rden ( slv[18].rden ) ,.dac_rddata ( slv[18].dout ) ,.dac_Prbs ( ch2_dac_Prbs ) ,.dac_Set0 ( ch2_dac_Set0 ) ,.dac_Set1 ( ch2_dac_Set1 ) ,.dac_Set2 ( ch2_dac_Set2 ) ,.dac_Set3 ( ch2_dac_Set3 ) ,.dac_Set4 ( ch2_dac_Set4 ) ,.dac_Set5 ( ch2_dac_Set5 ) ,.dac_Set6 ( ch2_dac_Set6 ) ,.dac_Set7 ( ch2_dac_Set7 ) ,.dac_Set8 ( ch2_dac_Set8 ) ,.dac_Set9 ( ch2_dac_Set9 ) ,.dac_Set10 ( ch2_dac_Set10 ) ,.dac_Set11 ( ch2_dac_Set11 ) ,.dac_Set12 ( ch2_dac_Set12 ) ,.dac_Set13 ( ch2_dac_Set13 ) ,.dac_Set14 ( ch2_dac_Set14 ) ,.dac_Set15 ( ch2_dac_Set15 ) ,.dac_addr ( ch2_dac_addr ) ,.dac_dw ( ch2_dac_dw ) ,.dac_ref ( ch2_dac_ref ) ,.dac_Prbs_rst0 ( ch2_dac_Prbs_rst0 ) ,.dac_Prbs_set0 ( ch2_dac_Prbs_set0 ) ,.dac_Prbs_rst1 ( ch2_dac_Prbs_rst1 ) ,.dac_Prbs_set1 ( ch2_dac_Prbs_set1 ) ,.dac_Cal_sig ( ch2_dac_Cal_sig ) ,.dac_Cal_rstn ( ch2_dac_Cal_rstn ) ,.Cal_div_rstn ( ch2_dac_Cal_div_rstn ) ,.dac_Cal_end ( ch2_dac_Cal_end ) ,.awg_data_i_o ( ch2_awg_data_i ) ,.awg_data_q_o ( ch2_awg_data_q ) ,.awg_vld_o ( ch2_awg_vld ) `ifdef CHANNEL_XY_ON ,.xy_dsp_dout0 ( ch2_xy_dsp_dout0 ) ,.xy_dsp_dout1 ( ch2_xy_dsp_dout1 ) ,.xy_dsp_dout2 ( ch2_xy_dsp_dout2 ) ,.xy_dsp_dout3 ( ch2_xy_dsp_dout3 ) ,.xy_dsp_dout4 ( ch2_xy_dsp_dout4 ) ,.xy_dsp_dout5 ( ch2_xy_dsp_dout5 ) ,.xy_dsp_dout6 ( ch2_xy_dsp_dout6 ) ,.xy_dsp_dout7 ( ch2_xy_dsp_dout7 ) ,.xy_dsp_dout8 ( ch2_xy_dsp_dout8 ) ,.xy_dsp_dout9 ( ch2_xy_dsp_dout9 ) ,.xy_dsp_dout10 ( ch2_xy_dsp_dout10 ) ,.xy_dsp_dout11 ( ch2_xy_dsp_dout11 ) ,.xy_dsp_dout12 ( ch2_xy_dsp_dout12 ) ,.xy_dsp_dout13 ( ch2_xy_dsp_dout13 ) ,.xy_dsp_dout14 ( ch2_xy_dsp_dout14 ) ,.xy_dsp_dout15 ( ch2_xy_dsp_dout15 ) ,.xy_dsp_dout_vld ( ch2_xy_dsp_dout_vld ) `endif `ifdef CHANNEL_Z_ON ,.z_dsp_dout0 ( ch2_z_dsp_dout0 ) ,.z_dsp_dout1 ( ch2_z_dsp_dout1 ) ,.z_dsp_dout2 ( ch2_z_dsp_dout2 ) ,.z_dsp_dout3 ( ch2_z_dsp_dout3 ) `endif ); //--------------------------------------------------------------------------------------------- // channel 2 instantiation end //--------------------------------------------------------------------------------------------- //--------------------------------------------------------------------------------------------- // channel 3 instantiation start //--------------------------------------------------------------------------------------------- wire [15:0] ch3_awg_data_i ; wire [15:0] ch3_awg_data_q ; wire [15:0] ch3_awg_vld ; `ifdef CHANNEL_XY_ON wire ch3_xy_dsp_dout_vld ; `endif channel_top U3_channel_top ( .clk ( clk ) ,.rst_n ( ch3_rstn_o ) ,.sync_int ( sync_int ) ,.dec_o_ilegl ( ch3_dec_err ) ,.agu_o_addr_unalgn ( ch3_ldst_addr_unalgn ) ,.awg_proc_cft ( ch3_proc_cft ) ,.mcu_ext_o_intr ( ch3_exit_irq ) ,.fb_st_in ( ch3_feedback ) //ch1 itcm addr space --> 0x0130_0000 ~ 0x013F_FFFF ,.itcm_i_rwaddr ( slv[19].addr[14:0] ) ,.itcm_i_wrdata ( slv[19].din ) ,.itcm_i_wren ( slv[19].wren ) ,.itcm_i_wrmask ( 4'h0 ) ,.itcm_i_rden ( slv[19].rden ) ,.itcm_o_rddata ( slv[19].dout ) //ch1 itcm addr space --> 0x0140_0000 ~ 0x014F_FFFF ,.dtcm_i_rwaddr ( slv[20].addr[14:0] ) ,.dtcm_i_wrdata ( slv[20].din ) ,.dtcm_i_wren ( slv[20].wren ) ,.dtcm_i_wrmask ( 4'h0 ) ,.dtcm_i_rden ( slv[20].rden ) ,.dtcm_o_rddata ( slv[20].dout ) //ch1 dtcm addr space --> 0x0150_0000 ~ 0x015F_FFFF ,.ctrl_rwaddr ( slv[21].addr[15:0] ) ,.ctrl_wrdata ( slv[21].din ) ,.ctrl_wren ( slv[21].wren ) ,.ctrl_rden ( slv[21].rden ) ,.ctrl_rddata ( slv[21].dout ) //ch1 envelope ID addr space --> 0x0160_0000 ~ 0x016F_FFFF ,.enve_id_brwaddr ( slv[22].addr[7:0] ) ,.enve_id_bwrdata ( slv[22].din ) ,.enve_id_bwren ( slv[22].wren ) ,.enve_id_brden ( slv[22].rden ) ,.enve_id_brddata ( slv[22].dout ) //ch1 envelope memory addr space --> 0x0170_0000 ~ 0x0105F_FFFF ,.enve_brwaddr ( slv[23].addr[14:0] ) ,.enve_bwrdata ( slv[23].din ) ,.enve_bwren ( slv[23].wren ) ,.enve_brden ( slv[23].rden ) ,.enve_brddata ( slv[23].dout ) //ch1 dac regfile addr space --> 0x0180_0000 ~ 0x018F_FFFFF ,.dac_rwaddr ( slv[24].addr[15:0] ) ,.dac_wrdata ( slv[24].din ) ,.dac_wren ( slv[24].wren ) ,.dac_rden ( slv[24].rden ) ,.dac_rddata ( slv[24].dout ) ,.dac_Prbs ( ch3_dac_Prbs ) ,.dac_Set0 ( ch3_dac_Set0 ) ,.dac_Set1 ( ch3_dac_Set1 ) ,.dac_Set2 ( ch3_dac_Set2 ) ,.dac_Set3 ( ch3_dac_Set3 ) ,.dac_Set4 ( ch3_dac_Set4 ) ,.dac_Set5 ( ch3_dac_Set5 ) ,.dac_Set6 ( ch3_dac_Set6 ) ,.dac_Set7 ( ch3_dac_Set7 ) ,.dac_Set8 ( ch3_dac_Set8 ) ,.dac_Set9 ( ch3_dac_Set9 ) ,.dac_Set10 ( ch3_dac_Set10 ) ,.dac_Set11 ( ch3_dac_Set11 ) ,.dac_Set12 ( ch3_dac_Set12 ) ,.dac_Set13 ( ch3_dac_Set13 ) ,.dac_Set14 ( ch3_dac_Set14 ) ,.dac_Set15 ( ch3_dac_Set15 ) ,.dac_addr ( ch3_dac_addr ) ,.dac_dw ( ch3_dac_dw ) ,.dac_ref ( ch3_dac_ref ) ,.dac_Prbs_rst0 ( ch3_dac_Prbs_rst0 ) ,.dac_Prbs_set0 ( ch3_dac_Prbs_set0 ) ,.dac_Prbs_rst1 ( ch3_dac_Prbs_rst1 ) ,.dac_Prbs_set1 ( ch3_dac_Prbs_set1 ) ,.dac_Cal_sig ( ch3_dac_Cal_sig ) ,.dac_Cal_rstn ( ch3_dac_Cal_rstn ) ,.Cal_div_rstn ( ch3_dac_Cal_div_rstn ) ,.dac_Cal_end ( ch3_dac_Cal_end ) ,.awg_data_i_o ( ch3_awg_data_i ) ,.awg_data_q_o ( ch3_awg_data_q ) ,.awg_vld_o ( ch3_awg_vld ) `ifdef CHANNEL_XY_ON ,.xy_dsp_dout0 ( ch3_xy_dsp_dout0 ) ,.xy_dsp_dout1 ( ch3_xy_dsp_dout1 ) ,.xy_dsp_dout2 ( ch3_xy_dsp_dout2 ) ,.xy_dsp_dout3 ( ch3_xy_dsp_dout3 ) ,.xy_dsp_dout4 ( ch3_xy_dsp_dout4 ) ,.xy_dsp_dout5 ( ch3_xy_dsp_dout5 ) ,.xy_dsp_dout6 ( ch3_xy_dsp_dout6 ) ,.xy_dsp_dout7 ( ch3_xy_dsp_dout7 ) ,.xy_dsp_dout8 ( ch3_xy_dsp_dout8 ) ,.xy_dsp_dout9 ( ch3_xy_dsp_dout9 ) ,.xy_dsp_dout10 ( ch3_xy_dsp_dout10 ) ,.xy_dsp_dout11 ( ch3_xy_dsp_dout11 ) ,.xy_dsp_dout12 ( ch3_xy_dsp_dout12 ) ,.xy_dsp_dout13 ( ch3_xy_dsp_dout13 ) ,.xy_dsp_dout14 ( ch3_xy_dsp_dout14 ) ,.xy_dsp_dout15 ( ch3_xy_dsp_dout15 ) ,.xy_dsp_dout_vld ( ch3_xy_dsp_dout_vld ) `endif `ifdef CHANNEL_Z_ON ,.z_dsp_dout0 ( ch3_z_dsp_dout0 ) ,.z_dsp_dout1 ( ch3_z_dsp_dout1 ) ,.z_dsp_dout2 ( ch3_z_dsp_dout2 ) ,.z_dsp_dout3 ( ch3_z_dsp_dout3 ) `endif ); //--------------------------------------------------------------------------------------------- // channel 3 instantiation end //--------------------------------------------------------------------------------------------- `endif //--------------------------------------------------------------------------------------------- // debug module instantiation start //--------------------------------------------------------------------------------------------- wire ch0_dsp_vld ; wire [15 :0] ch0_dsp_data [15:0] ; wire ch1_dsp_vld ; wire [15 :0] ch1_dsp_data [15:0] ; wire ch2_dsp_vld ; wire [15 :0] ch2_dsp_data [15:0] ; wire ch3_dsp_vld ; wire [15 :0] ch3_dsp_data [15:0] ; //channel 0 xy dsp data assign ch0_dsp_vld = ch0_xy_dsp_dout_vld ; assign ch0_dsp_data[0 ] = ch0_xy_dsp_dout0 ; assign ch0_dsp_data[1 ] = ch0_xy_dsp_dout1 ; assign ch0_dsp_data[2 ] = ch0_xy_dsp_dout2 ; assign ch0_dsp_data[3 ] = ch0_xy_dsp_dout3 ; assign ch0_dsp_data[4 ] = ch0_xy_dsp_dout4 ; assign ch0_dsp_data[5 ] = ch0_xy_dsp_dout5 ; assign ch0_dsp_data[6 ] = ch0_xy_dsp_dout6 ; assign ch0_dsp_data[7 ] = ch0_xy_dsp_dout7 ; assign ch0_dsp_data[8 ] = ch0_xy_dsp_dout8 ; assign ch0_dsp_data[9 ] = ch0_xy_dsp_dout9 ; assign ch0_dsp_data[10] = ch0_xy_dsp_dout10 ; assign ch0_dsp_data[11] = ch0_xy_dsp_dout11 ; assign ch0_dsp_data[12] = ch0_xy_dsp_dout12 ; assign ch0_dsp_data[13] = ch0_xy_dsp_dout13 ; assign ch0_dsp_data[14] = ch0_xy_dsp_dout14 ; assign ch0_dsp_data[15] = ch0_xy_dsp_dout15 ; `ifdef CHANNEL_IS_FOUR //channel 1 xy dsp data assign ch1_dsp_vld = ch1_xy_dsp_dout_vld ; assign ch1_dsp_data[0 ] = ch1_xy_dsp_dout0 ; assign ch1_dsp_data[1 ] = ch1_xy_dsp_dout1 ; assign ch1_dsp_data[2 ] = ch1_xy_dsp_dout2 ; assign ch1_dsp_data[3 ] = ch1_xy_dsp_dout3 ; assign ch1_dsp_data[4 ] = ch1_xy_dsp_dout4 ; assign ch1_dsp_data[5 ] = ch1_xy_dsp_dout5 ; assign ch1_dsp_data[6 ] = ch1_xy_dsp_dout6 ; assign ch1_dsp_data[7 ] = ch1_xy_dsp_dout7 ; assign ch1_dsp_data[8 ] = ch1_xy_dsp_dout8 ; assign ch1_dsp_data[9 ] = ch1_xy_dsp_dout9 ; assign ch1_dsp_data[10] = ch1_xy_dsp_dout10 ; assign ch1_dsp_data[11] = ch1_xy_dsp_dout11 ; assign ch1_dsp_data[12] = ch1_xy_dsp_dout12 ; assign ch1_dsp_data[13] = ch1_xy_dsp_dout13 ; assign ch1_dsp_data[14] = ch1_xy_dsp_dout14 ; assign ch1_dsp_data[15] = ch1_xy_dsp_dout15 ; //channel 2 xy dsp data assign ch2_dsp_vld = ch2_xy_dsp_dout_vld ; assign ch2_dsp_data[0 ] = ch2_xy_dsp_dout0 ; assign ch2_dsp_data[1 ] = ch2_xy_dsp_dout1 ; assign ch2_dsp_data[2 ] = ch2_xy_dsp_dout2 ; assign ch2_dsp_data[3 ] = ch2_xy_dsp_dout3 ; assign ch2_dsp_data[4 ] = ch2_xy_dsp_dout4 ; assign ch2_dsp_data[5 ] = ch2_xy_dsp_dout5 ; assign ch2_dsp_data[6 ] = ch2_xy_dsp_dout6 ; assign ch2_dsp_data[7 ] = ch2_xy_dsp_dout7 ; assign ch2_dsp_data[8 ] = ch2_xy_dsp_dout8 ; assign ch2_dsp_data[9 ] = ch2_xy_dsp_dout9 ; assign ch2_dsp_data[10] = ch2_xy_dsp_dout10 ; assign ch2_dsp_data[11] = ch2_xy_dsp_dout11 ; assign ch2_dsp_data[12] = ch2_xy_dsp_dout12 ; assign ch2_dsp_data[13] = ch2_xy_dsp_dout13 ; assign ch2_dsp_data[14] = ch2_xy_dsp_dout14 ; assign ch2_dsp_data[15] = ch2_xy_dsp_dout15 ; //channel 3 xy dsp data assign ch3_dsp_vld = ch3_xy_dsp_dout_vld ; assign ch3_dsp_data[0 ] = ch3_xy_dsp_dout0 ; assign ch3_dsp_data[1 ] = ch3_xy_dsp_dout1 ; assign ch3_dsp_data[2 ] = ch3_xy_dsp_dout2 ; assign ch3_dsp_data[3 ] = ch3_xy_dsp_dout3 ; assign ch3_dsp_data[4 ] = ch3_xy_dsp_dout4 ; assign ch3_dsp_data[5 ] = ch3_xy_dsp_dout5 ; assign ch3_dsp_data[6 ] = ch3_xy_dsp_dout6 ; assign ch3_dsp_data[7 ] = ch3_xy_dsp_dout7 ; assign ch3_dsp_data[8 ] = ch3_xy_dsp_dout8 ; assign ch3_dsp_data[9 ] = ch3_xy_dsp_dout9 ; assign ch3_dsp_data[10] = ch3_xy_dsp_dout10 ; assign ch3_dsp_data[11] = ch3_xy_dsp_dout11 ; assign ch3_dsp_data[12] = ch3_xy_dsp_dout12 ; assign ch3_dsp_data[13] = ch3_xy_dsp_dout13 ; assign ch3_dsp_data[14] = ch3_xy_dsp_dout14 ; assign ch3_dsp_data[15] = ch3_xy_dsp_dout15 ; `endif //When designed for single-channel, open this macro `ifndef CHANNEL_IS_FOUR //channel 1 xy dsp data assign ch1_dsp_vld = 1'b0 ; assign ch1_dsp_data[0 ] = 16'h0 ; assign ch1_dsp_data[1 ] = 16'h0 ; assign ch1_dsp_data[2 ] = 16'h0 ; assign ch1_dsp_data[3 ] = 16'h0 ; assign ch1_dsp_data[4 ] = 16'h0 ; assign ch1_dsp_data[5 ] = 16'h0 ; assign ch1_dsp_data[6 ] = 16'h0 ; assign ch1_dsp_data[7 ] = 16'h0 ; assign ch1_dsp_data[8 ] = 16'h0 ; assign ch1_dsp_data[9 ] = 16'h0 ; assign ch1_dsp_data[10] = 16'h0 ; assign ch1_dsp_data[11] = 16'h0 ; assign ch1_dsp_data[12] = 16'h0 ; assign ch1_dsp_data[13] = 16'h0 ; assign ch1_dsp_data[14] = 16'h0 ; assign ch1_dsp_data[15] = 16'h0 ; //channel 2 xy dsp data assign ch2_dsp_vld = 1'b0 ; assign ch2_dsp_data[0 ] = 16'h0 ; assign ch2_dsp_data[1 ] = 16'h0 ; assign ch2_dsp_data[2 ] = 16'h0 ; assign ch2_dsp_data[3 ] = 16'h0 ; assign ch2_dsp_data[4 ] = 16'h0 ; assign ch2_dsp_data[5 ] = 16'h0 ; assign ch2_dsp_data[6 ] = 16'h0 ; assign ch2_dsp_data[7 ] = 16'h0 ; assign ch2_dsp_data[8 ] = 16'h0 ; assign ch2_dsp_data[9 ] = 16'h0 ; assign ch2_dsp_data[10] = 16'h0 ; assign ch2_dsp_data[11] = 16'h0 ; assign ch2_dsp_data[12] = 16'h0 ; assign ch2_dsp_data[13] = 16'h0 ; assign ch2_dsp_data[14] = 16'h0 ; assign ch2_dsp_data[15] = 16'h0 ; //channel 3 xy dsp data assign ch3_dsp_vld = 1'b0 ; assign ch3_dsp_data[0 ] = 16'h0 ; assign ch3_dsp_data[1 ] = 16'h0 ; assign ch3_dsp_data[2 ] = 16'h0 ; assign ch3_dsp_data[3 ] = 16'h0 ; assign ch3_dsp_data[4 ] = 16'h0 ; assign ch3_dsp_data[5 ] = 16'h0 ; assign ch3_dsp_data[6 ] = 16'h0 ; assign ch3_dsp_data[7 ] = 16'h0 ; assign ch3_dsp_data[8 ] = 16'h0 ; assign ch3_dsp_data[9 ] = 16'h0 ; assign ch3_dsp_data[10] = 16'h0 ; assign ch3_dsp_data[11] = 16'h0 ; assign ch3_dsp_data[12] = 16'h0 ; assign ch3_dsp_data[13] = 16'h0 ; assign ch3_dsp_data[14] = 16'h0 ; assign ch3_dsp_data[15] = 16'h0 ; wire [15:0] ch1_awg_data_i = 16'b0 ; wire [15:0] ch1_awg_data_q = 16'b0 ; wire [0 :0] ch1_awg_vld = 1'b0 ; wire [15:0] ch2_awg_data_i = 16'b0 ; wire [15:0] ch2_awg_data_q = 16'b0 ; wire [0 :0] ch2_awg_vld = 1'b0 ; wire [15:0] ch3_awg_data_i = 16'b0 ; wire [15:0] ch3_awg_data_q = 16'b0 ; wire [0 :0] ch3_awg_vld = 1'b0 ; `endif debug_top U_debug_top ( //system port .clk ( clk ) ,.rst_n ( pll_rstn_o ) ,.debug_enable ( dbg_enable ) ,.debug_data_sel ( dbg_data_sel ) ,.debug_ch_sel ( dbg_ch_sel ) ,.debug_update ( dbg_upd ) ,.ch0_mod_data_i ( ch0_awg_data_i ) ,.ch0_mod_data_q ( ch0_awg_data_q ) ,.ch0_mod_vld ( ch0_awg_vld ) ,.ch1_mod_data_i ( ch1_awg_data_i ) ,.ch1_mod_data_q ( ch1_awg_data_q ) ,.ch1_mod_vld ( ch1_awg_vld ) ,.ch2_mod_data_i ( ch2_awg_data_i ) ,.ch2_mod_data_q ( ch2_awg_data_q ) ,.ch2_mod_vld ( ch2_awg_vld ) ,.ch3_mod_data_i ( ch3_awg_data_i ) ,.ch3_mod_data_q ( ch3_awg_data_q ) ,.ch3_mod_vld ( ch3_awg_vld ) ,.ch0_dsp_data ( ch0_dsp_data ) ,.ch0_dsp_vld ( ch0_dsp_vld ) ,.ch1_dsp_data ( ch1_dsp_data ) ,.ch1_dsp_vld ( ch1_dsp_vld ) ,.ch2_dsp_data ( ch2_dsp_data ) ,.ch2_dsp_vld ( ch2_dsp_vld ) ,.ch3_dsp_data ( ch3_dsp_data ) ,.ch3_dsp_vld ( ch3_dsp_vld ) ,.dbg_sram_in ( slv[25].slave ) ); //--------------------------------------------------------------------------------------------- // debug module instantiation end //--------------------------------------------------------------------------------------------- endmodule `include "../define/chip_undefine.v"