//+FHDR-------------------------------------------------------------------------------------------------------- // Company: //----------------------------------------------------------------------------------------------------------------- // File Name : channel_top.v // Department : // Author : pwy // Author's Tel : //----------------------------------------------------------------------------------------------------------------- // Relese History // Version Date Author Description // 1.2 2024-04-16 pwy XYZ channel the top-level module //----------------------------------------------------------------------------------------------------------------- // Keywords : // //----------------------------------------------------------------------------------------------------------------- // Parameter // //----------------------------------------------------------------------------------------------------------------- // Purpose : // //----------------------------------------------------------------------------------------------------------------- // Target Device: // Tool versions: //----------------------------------------------------------------------------------------------------------------- // Reuse Issues // Reset Strategy: // Clock Domains: // Critical Timing: // Asynchronous I/F: // Synthesizable (y/n): // Other: //-FHDR------------------------------------------------------------------------------------------------------------ `include "../define/chip_define.v" `include "../qubitmcu/qbmcu_defines.v" module channel_top ( //system port input clk ,input rst_n //Sync Start ,input sync_int //Decoded port ,output dec_o_ilegl //Misaligned memory address ,output agu_o_addr_unalgn // ,output awg_proc_cft ,output mcu_ext_o_intr //Feedback signal from the readout chip ,input [1 :0] fb_st_in //ITCM ,input [`QBMCU_DTCM_ADDR_SIZE-1 :0] itcm_i_rwaddr ,input [`QBMCU_XLEN-1 :0] itcm_i_wrdata ,input itcm_i_wren ,input [`QBMCU_XLEN/8-1 :0] itcm_i_wrmask ,input itcm_i_rden ,output [`QBMCU_XLEN-1 :0] itcm_o_rddata //DTCM ,input [`QBMCU_DTCM_ADDR_SIZE-1 :0] dtcm_i_rwaddr ,input [`QBMCU_XLEN-1 :0] dtcm_i_wrdata ,input dtcm_i_wren ,input [`QBMCU_XLEN/8-1 :0] dtcm_i_wrmask ,input dtcm_i_rden ,output [`QBMCU_XLEN-1 :0] dtcm_o_rddata //ctrl regfile ,input [31 :0] ctrl_wrdata ,input ctrl_wren ,input [15 :0] ctrl_rwaddr ,input ctrl_rden ,output [31 :0] ctrl_rddata //Envelope storage read/write signal ,input [31 :0] enve_bwrdata ,input [0 :0] enve_bwren ,input [14 :0] enve_brwaddr ,input [0 :0] enve_brden ,output [31 :0] enve_brddata //envelope index lookup table read-write signal ,input [31 :0] enve_id_bwrdata ,input [0 :0] enve_id_bwren ,input [7 :0] enve_id_brwaddr ,input [0 :0] enve_id_brden ,output [31 :0] enve_id_brddata //DAC cfg //dac regfile ,input [31 :0] dac_wrdata ,input dac_wren ,input [15 :0] dac_rwaddr ,input dac_rden ,output [31 :0] dac_rddata ,output dac_Prbs ,output [14 :0] dac_Set0 ,output [14 :0] dac_Set1 ,output [14 :0] dac_Set2 ,output [14 :0] dac_Set3 ,output [14 :0] dac_Set4 ,output [14 :0] dac_Set5 ,output [14 :0] dac_Set6 ,output [14 :0] dac_Set7 ,output [14 :0] dac_Set8 ,output [14 :0] dac_Set9 ,output [14 :0] dac_Set10 ,output [14 :0] dac_Set11 ,output [14 :0] dac_Set12 ,output [14 :0] dac_Set13 ,output [14 :0] dac_Set14 ,output [14 :0] dac_Set15 ,output [2 :0] dac_addr ,output [2 :0] dac_dw ,output [8 :0] dac_ref ,output [16 :0] dac_Prbs_rst0 ,output [16 :0] dac_Prbs_set0 ,output [16 :0] dac_Prbs_rst1 ,output [16 :0] dac_Prbs_set1 ,output dac_Cal_sig ,output dac_Cal_rstn ,output Cal_div_rstn ,input dac_Cal_end //awg data output ,output [15 :0] awg_data_i_o ,output [15 :0] awg_data_q_o ,output awg_vld_o `ifdef CHANNEL_XY_ON //dsp data output ,output [15 :0] xy_dsp_dout0 ,output [15 :0] xy_dsp_dout1 ,output [15 :0] xy_dsp_dout2 ,output [15 :0] xy_dsp_dout3 ,output [15 :0] xy_dsp_dout4 ,output [15 :0] xy_dsp_dout5 ,output [15 :0] xy_dsp_dout6 ,output [15 :0] xy_dsp_dout7 ,output [15 :0] xy_dsp_dout8 ,output [15 :0] xy_dsp_dout9 ,output [15 :0] xy_dsp_dout10 ,output [15 :0] xy_dsp_dout11 ,output [15 :0] xy_dsp_dout12 ,output [15 :0] xy_dsp_dout13 ,output [15 :0] xy_dsp_dout14 ,output [15 :0] xy_dsp_dout15 ,output xy_dsp_dout_vld `endif `ifdef CHANNEL_Z_ON //Z dsp output ,output [15 :0] z_dsp_dout0 ,output [15 :0] z_dsp_dout1 ,output [15 :0] z_dsp_dout2 ,output [15 :0] z_dsp_dout3 `endif ); //--------------------------------------------------------------------------------------------- // qbmcu instantiation start //--------------------------------------------------------------------------------------------- wire [`QBMCU_PC_SIZE-1 :0] ifu_i_pc_rtvec = 32'h0 ; wire [`QBMCU_PC_SIZE-1 :0] ifu_o_req_pc ; wire ifu_o_req ; wire [`QBMCU_INSTR_SIZE-1:0] ifu_rsp_instr ; wire [`QBMCU_ADDR_SIZE-1 :0] agu_o_addr ; wire [`QBMCU_XLEN-1 :0] agu_o_wrdata ; wire agu_o_wren ; wire [`QBMCU_XLEN/8-1 :0] agu_o_wrmask ; wire agu_o_rden ; wire [`QBMCU_XLEN-1 :0] agu_i_rddata ; wire ext_o_send ; wire ext_o_sendc ; wire [`QBMCU_XLEN-1 :0] ext_o_codeword ; wire [2 :0] qbmcu_o_fsm_st ; qbmcu U_qbmcu ( .clk ( clk ) ,.rst_n ( rst_n ) ,.qbmcu_i_start ( sync_int ) ,.qbmcu_o_fsm_st ( qbmcu_o_fsm_st ) ,.ifu_i_pc_rtvec ( ifu_i_pc_rtvec ) ,.ifu_o_req_pc ( ifu_o_req_pc ) ,.ifu_o_req ( ifu_o_req ) ,.ifu_rsp_instr ( ifu_rsp_instr ) ,.dec_o_ilegl ( dec_o_ilegl ) ,.agu_o_addr ( agu_o_addr ) ,.agu_o_wrdata ( agu_o_wrdata ) ,.agu_o_wren ( agu_o_wren ) ,.agu_o_wrmask ( agu_o_wrmask ) ,.agu_o_rden ( agu_o_rden ) ,.agu_i_rddata ( agu_i_rddata ) ,.agu_o_addr_unalgn ( agu_o_addr_unalgn ) ,.ext_o_send ( ext_o_send ) ,.ext_o_sendc ( ext_o_sendc ) ,.ext_o_codeword ( ext_o_codeword ) ,.ext_o_intr ( mcu_ext_o_intr ) ); //--------------------------------------------------------------------------------------------- // qbmcu instantiation end //--------------------------------------------------------------------------------------------- //--------------------------------------------------------------------------------------------- // MCU runtime counter instantiation start //--------------------------------------------------------------------------------------------- defparam qbmcu_runtime.width = 32; //MCU runtime wire [31 :0] run_time ; DW03_updn_ctr qbmcu_runtime ( .clk ( clk ) // clock input ,.reset ( rst_n ) // asynchronous reset input (active low) ,.data ( 32'd0 ) // data used for load operation ,.up_dn ( 1'b1 ) // up/down control input (0=down, 1-up) ,.load ( ~sync_int ) // load operation control input (active low) ,.cen ( |qbmcu_o_fsm_st ) // count enable control input (active high enable) ,.count ( run_time ) // count value output ,.tercnt ( ) // terminal count output flag (active high) ); //--------------------------------------------------------------------------------------------- // MCU runtime counter instantiation end //--------------------------------------------------------------------------------------------- //--------------------------------------------------------------------------------------------- // fetch instructions number counter instantiation start //--------------------------------------------------------------------------------------------- defparam instrnum.width = 32; //Count the number of fetch instructions wire [31 :0] instr_num ; DW03_updn_ctr instrnum ( .clk ( clk ) // clock input ,.reset ( rst_n ) // asynchronous reset input (active low) ,.data ( 32'd0 ) // data used for load operation ,.up_dn ( 1'b1 ) // up/down control input (0=down, 1-up) ,.load ( ~sync_int ) // load operation control input (active low) ,.cen ( ifu_o_req ) // count enable control input (active high enable) ,.count ( instr_num ) // count value output ,.tercnt ( ) // terminal count output flag (active high) ); //--------------------------------------------------------------------------------------------- // fetch instructions number counter instantiation end //--------------------------------------------------------------------------------------------- //--------------------------------------------------------------------------------------------- // qbmcu_busdecoder instantiation start //--------------------------------------------------------------------------------------------- wire [`QBMCU_ADDR_SIZE-1 :0] dsram_o_rwaddr ; wire [`QBMCU_XLEN-1 :0] dsram_o_wrdata ; wire dsram_o_wren ; wire [`QBMCU_XLEN/8-1 :0] dsram_o_wrmask ; wire dsram_o_rden ; wire [`QBMCU_XLEN-1 :0] dsram_i_rddata ; wire [`QBMCU_ADDR_SIZE-1 :0] preg_o_rwaddr ; wire [`QBMCU_XLEN-1 :0] preg_o_wrdata ; wire preg_o_wren ; wire [`QBMCU_XLEN/8-1 :0] preg_o_wrmask ; wire preg_o_rden ; wire [`QBMCU_XLEN-1 :0] preg_i_rddata ; qbmcu_busdecoder #( .S0_BASEADDR ( 32'h0010_0000 ) ,.S1_BASEADDR ( 32'h0020_0000 ) )U_qbmcu_busdecoder ( .wren ( agu_o_wren ) ,.wrmask ( agu_o_wrmask ) ,.wrdata ( agu_o_wrdata ) ,.rwaddr ( agu_o_addr ) ,.rden ( agu_o_rden ) ,.rddata ( agu_i_rddata ) ,.s0_wren ( dsram_o_wren ) ,.s0_wrmask ( dsram_o_wrmask ) ,.s0_rwaddr ( dsram_o_rwaddr ) ,.s0_wrdata ( dsram_o_wrdata ) ,.s0_rden ( dsram_o_rden ) ,.s0_rddata ( dsram_i_rddata ) ,.s1_wren ( preg_o_wren ) ,.s1_wrmask ( preg_o_wrmask ) ,.s1_rwaddr ( preg_o_rwaddr ) ,.s1_wrdata ( preg_o_wrdata ) ,.s1_rden ( preg_o_rden ) ,.s1_rddata ( preg_i_rddata ) ); //--------------------------------------------------------------------------------------------- // qbmcu_busdecoder instantiation end //--------------------------------------------------------------------------------------------- //--------------------------------------------------------------------------------------------- // mcu_regfile instantiation start //--------------------------------------------------------------------------------------------- //MCU and SPI interface for interaction wire [31 :0] mcu_param [3:0] ; // MCU parameter 0~3 wire [31 :0] mcu_result [3:0] ; // MCU result 0~3 //lookup table data ; wire [31 :0] mcu_cwfr [3:0] ; // Carrier frequency ctrl word 0~3 wire [15 :0] mcu_gapr [7:0] ; // Carrier phase ctrl word 0~3 wire [15 :0] mcu_ampr [3:0] ; // Carrier Amplitude 0~3 wire [15 :0] mcu_baisr [3:0] ; // Carrier Bais 0~3 //CFG Port wire mcu_nco_pha_clr ; wire [15 :0] mcu_rz_pha ; wire [1:0] fb_st_in_s; syncer #(2, 2) fb_st_in_syncer (clk, rst_n, fb_st_in, fb_st_in_s); mcu_regfile U_mcu_regfile ( .clk ( clk ) ,.rst_n ( rst_n ) ,.rwaddr ( preg_o_rwaddr[15:0] ) ,.wrdata ( preg_o_wrdata ) ,.wren ( preg_o_wren ) ,.wrmask ( preg_o_wrmask ) ,.rden ( preg_o_rden ) ,.rddata ( preg_i_rddata ) ,.fb_st_info ( fb_st_in_s ) ,.run_time ( run_time ) ,.instr_num ( instr_num ) ,.mcu_param ( mcu_param ) ,.mcu_result ( mcu_result ) ,.mcu_cwfr ( mcu_cwfr ) ,.mcu_gapr ( mcu_gapr ) ,.mcu_ampr ( mcu_ampr ) ,.mcu_baisr ( mcu_baisr ) ,.mcu_nco_pha_clr ( mcu_nco_pha_clr ) ,.mcu_rz_pha ( mcu_rz_pha ) ); //--------------------------------------------------------------------------------------------- // mcu_regfile instantiation end //--------------------------------------------------------------------------------------------- //--------------------------------------------------------------------------------------------- // U_ITCM instantiation start //--------------------------------------------------------------------------------------------- wire itcm_portb_wen = ~itcm_i_wren & itcm_i_rden; wire itcm_portb_cen = ~(itcm_i_wren | itcm_i_rden); dpram #( .DATAWIDTH ( 32 ) ,.ADDRWIDTH ( 15 ) ) U_ITCM ( .PortClk ( clk ) ,.PortAAddr ( ifu_o_req_pc[`QBMCU_ITCM_ADDR_SIZE-1:0] ) ,.PortADataIn ( 32'b0 ) ,.PortAWriteEnable ( 1'b1 ) ,.PortAChipEnable ( ~ifu_o_req ) ,.PortAByteWriteEnable ( 4'b0 ) ,.PortADataOut ( ifu_rsp_instr ) ,.PortBAddr ( itcm_i_rwaddr[14:0] ) ,.PortBDataIn ( itcm_i_wrdata ) ,.PortBWriteEnable ( itcm_portb_wen ) ,.PortBChipEnable ( itcm_portb_cen ) ,.PortBByteWriteEnable ( itcm_i_wrmask ) ,.PortBDataOut ( itcm_o_rddata ) ); //--------------------------------------------------------------------------------------------- // U_ITCM instantiation end //--------------------------------------------------------------------------------------------- //////////////////////////////////////////////////////////////////////////////////////////////////////////// //DTCM //////////////////////////////////////////////////////////////////////////////////////////////////////////// wire dtcm_portb_wen = ~dtcm_i_wren & dtcm_i_rden; wire dtcm_portb_cen = ~(dtcm_i_wren | dtcm_i_rden); dpram #( .DATAWIDTH ( 32 ) ,.ADDRWIDTH ( 15 ) ) U_DTCM ( .PortClk ( clk ) ,.PortAAddr ( dsram_o_rwaddr[`QBMCU_DTCM_ADDR_SIZE-1:0] ) ,.PortADataIn ( dsram_o_wrdata ) ,.PortAWriteEnable ( ~dsram_o_wren ) ,.PortAChipEnable ( ~(dsram_o_rden | dsram_o_wren) ) ,.PortAByteWriteEnable ( ~dsram_o_wrmask ) ,.PortADataOut ( dsram_i_rddata ) ,.PortBAddr ( dtcm_i_rwaddr[14:0] ) ,.PortBDataIn ( dtcm_i_wrdata ) ,.PortBWriteEnable ( dtcm_portb_wen ) ,.PortBChipEnable ( dtcm_portb_cen ) ,.PortBByteWriteEnable ( dtcm_i_wrmask ) ,.PortBDataOut ( dtcm_o_rddata ) ); //--------------------------------------------------------------------------------------------- // ctrl_regfile instantiation start //--------------------------------------------------------------------------------------------- wire [1 :0] fb_st_int ; //awg cfg wire mod_sel_sideband ; //DSP cfg wire qam_nco_sclr_en ; wire qam_nco_clr ; wire [47 :0] qam_fcw ; wire [15 :0] qam_pha ; wire [1 :0] qam_mod ; wire qam_sel_sideband ; wire [2 :0] intp_mode ; wire [1 :0] role_sel ; wire [1 :0] dac_mode_sel ; wire enve_read_fsm_st ; wire bais_i_ov ; wire bais_q_ov ; wire dout_sel ; wire dsp_alwayson ; wire mod_dout_sel = dout_sel ; ctrl_regfile U_ctrl_regfile ( .clk ( clk ) ,.rst_n ( rst_n ) ,.wrdata ( ctrl_wrdata ) ,.wren ( ctrl_wren ) ,.rwaddr ( ctrl_rwaddr ) ,.rden ( ctrl_rden ) ,.rddata ( ctrl_rddata ) ,.fb_st_i ( fb_st_in_s ) ,.run_time ( run_time ) ,.instr_num ( instr_num ) ,.bais_i_ov ( bais_i_ov ) ,.bais_q_ov ( bais_q_ov ) ,.awg_ctrl_fsm_st ( enve_read_fsm_st ) ,.mcu_param0 ( mcu_param[0] ) ,.mcu_param1 ( mcu_param[1] ) ,.mcu_param2 ( mcu_param[2] ) ,.mcu_param3 ( mcu_param[3] ) ,.mcu_result0 ( mcu_result[0] ) ,.mcu_result1 ( mcu_result[1] ) ,.mcu_result2 ( mcu_result[2] ) ,.mcu_result3 ( mcu_result[3] ) ,.fb_st_o ( fb_st_int ) ,.mod_sel_sideband ( mod_sel_sideband ) ,.qam_nco_clr ( qam_nco_clr ) ,.qam_nco_sclr_en ( qam_nco_sclr_en ) ,.qam_fcw ( qam_fcw ) ,.qam_pha ( qam_pha ) ,.qam_mod ( qam_mod ) ,.qam_sel_sideband ( qam_sel_sideband ) ,.intp_mode ( intp_mode ) ,.role_sel ( role_sel ) ,.dout_sel ( dout_sel ) ,.dac_mode_sel ( dac_mode_sel ) ,.dsp_alwayson ( dsp_alwayson ) ); //--------------------------------------------------------------------------------------------- // ctrl_regfile instantiation end //--------------------------------------------------------------------------------------------- //--------------------------------------------------------------------------------------------- // awg_top instantiation start //--------------------------------------------------------------------------------------------- wire [15 :0] awg_data_i ; wire [15 :0] awg_data_q ; wire awg_vld ; wire mod_pha_sfot_clr = ~rst_n; assign awg_data_i_o = awg_data_i ; assign awg_data_q_o = awg_data_q ; assign awg_vld_o = awg_vld ; awg_top U_awg_top ( .clk ( clk ) ,.rst_n ( rst_n ) ,.mcu_cwfr ( mcu_cwfr ) ,.mcu_gapr ( mcu_gapr ) ,.mcu_ampr ( mcu_ampr ) ,.mcu_baisr ( mcu_baisr ) ,.mcu_nco_pha_clr ( mcu_nco_pha_clr ) ,.mcu_rz_pha ( mcu_rz_pha ) ,.send ( ext_o_send ) ,.sendc ( ext_o_sendc ) ,.codeword ( ext_o_codeword ) ,.fb_st ( fb_st_int ) ,.enve_bwrdata ( enve_bwrdata ) ,.enve_bwren ( enve_bwren ) ,.enve_brwaddr ( enve_brwaddr ) ,.enve_brden ( enve_brden ) ,.enve_brddata ( enve_brddata ) ,.enve_id_bwrdata ( enve_id_bwrdata ) ,.enve_id_bwren ( enve_id_bwren ) ,.enve_id_brwaddr ( enve_id_brwaddr ) ,.enve_id_brden ( enve_id_brden ) ,.enve_id_brddata ( enve_id_brddata ) ,.enve_read_fsm_st ( enve_read_fsm_st ) ,.proc_cft ( awg_proc_cft ) ,.mod_sideband_sel ( mod_sel_sideband ) ,.mod_pha_sfot_clr ( mod_pha_sfot_clr ) ,.role_sel ( role_sel ) ,.mod_dout_sel ( mod_dout_sel ) ,.awg_data_i ( awg_data_i ) ,.awg_data_q ( awg_data_q ) ,.awg_vld ( awg_vld ) ,.bais_i_ov ( bais_i_ov ) ,.bais_q_ov ( bais_q_ov ) ); //--------------------------------------------------------------------------------------------- // awg_top instantiation end //--------------------------------------------------------------------------------------------- `ifdef CHANNEL_XY_ON //--------------------------------------------------------------------------------------------- // xy's dsp instantiation start //--------------------------------------------------------------------------------------------- wire qam_anco_clr = qam_nco_sclr_en ? ~sync_int : 1'b0; wire mix_enable = ~(role_sel[1]); xy_dsp U_xy_dsp ( .clk ( clk ) ,.rstn ( rst_n ) ,.phase_manual_clr ( qam_nco_clr ) ,.phase_auto_clr ( qam_anco_clr ) ,.fcw ( qam_fcw ) ,.pha ( qam_pha ) ,.qam_mod ( qam_mod ) ,.sel_sideband ( qam_sel_sideband ) ,.intp_mode ( intp_mode ) ,.dac_mode_sel ( dac_mode_sel ) ,.mix_enable ( mix_enable ) ,.dsp_alwayson ( dsp_alwayson ) ,.din_i ( awg_data_i ) ,.din_q ( awg_data_q ) ,.din_vld ( awg_vld ) ,.dout0 ( xy_dsp_dout0 ) ,.dout1 ( xy_dsp_dout1 ) ,.dout2 ( xy_dsp_dout2 ) ,.dout3 ( xy_dsp_dout3 ) ,.dout4 ( xy_dsp_dout4 ) ,.dout5 ( xy_dsp_dout5 ) ,.dout6 ( xy_dsp_dout6 ) ,.dout7 ( xy_dsp_dout7 ) ,.dout8 ( xy_dsp_dout8 ) ,.dout9 ( xy_dsp_dout9 ) ,.dout10 ( xy_dsp_dout10 ) ,.dout11 ( xy_dsp_dout11 ) ,.dout12 ( xy_dsp_dout12 ) ,.dout13 ( xy_dsp_dout13 ) ,.dout14 ( xy_dsp_dout14 ) ,.dout15 ( xy_dsp_dout15 ) ,.dout_vld ( xy_dsp_dout_vld ) ); //--------------------------------------------------------------------------------------------- // xy's dsp instantiation end //--------------------------------------------------------------------------------------------- `endif `ifdef CHANNEL_Z_ON //--------------------------------------------------------------------------------------------- // z_data_mux instantiation start //--------------------------------------------------------------------------------------------- wire z_dout_sel = dout_sel; wire [15:0] z_dsp_data0 = 16'h0000; wire [15:0] z_dsp_data1 = 16'h0000; wire [15:0] z_dsp_data2 = 16'h0000; wire [15:0] z_dsp_data3 = 16'h0000; z_data_mux U_z_data_mux ( .clk ( clk ) ,.rst_n ( rst_n ) ,.sel ( z_dout_sel ) ,.z_dsp_data0 ( z_dsp_data0 ) ,.z_dsp_data1 ( z_dsp_data1 ) ,.z_dsp_data2 ( z_dsp_data2 ) ,.z_dsp_data3 ( z_dsp_data3 ) ,.xy_dsp_data0 ( xy_dsp_dout0 ) ,.xy_dsp_data1 ( xy_dsp_dout1 ) ,.xy_dsp_data2 ( xy_dsp_dout2 ) ,.xy_dsp_data3 ( xy_dsp_dout3 ) ,.mux_data_0 ( z_dsp_dout0 ) ,.mux_data_1 ( z_dsp_dout1 ) ,.mux_data_2 ( z_dsp_dout2 ) ,.mux_data_3 ( z_dsp_dout3 ) ); //--------------------------------------------------------------------------------------------- // z_data_mux instantiation end //--------------------------------------------------------------------------------------------- `endif //--------------------------------------------------------------------------------------------- //dac_regfile instantiation start //--------------------------------------------------------------------------------------------- dac_regfile U_ch0_dac_regfile ( .clk ( clk ) ,.rstn ( rst_n ) ,.wrdata ( dac_wrdata ) ,.wren ( dac_wren ) ,.rwaddr ( dac_rwaddr ) ,.rden ( dac_rden ) ,.rddata ( dac_rddata ) ,.Prbs ( dac_Prbs ) ,.Set0 ( dac_Set0 ) ,.Set1 ( dac_Set1 ) ,.Set2 ( dac_Set2 ) ,.Set3 ( dac_Set3 ) ,.Set4 ( dac_Set4 ) ,.Set5 ( dac_Set5 ) ,.Set6 ( dac_Set6 ) ,.Set7 ( dac_Set7 ) ,.Set8 ( dac_Set8 ) ,.Set9 ( dac_Set9 ) ,.Set10 ( dac_Set10 ) ,.Set11 ( dac_Set11 ) ,.Set12 ( dac_Set12 ) ,.Set13 ( dac_Set13 ) ,.Set14 ( dac_Set14 ) ,.Set15 ( dac_Set15 ) ,.Dac_addr ( dac_addr ) ,.Dac_dw ( dac_dw ) ,.Dac_ref ( dac_ref ) ,.Prbs_rst0 ( dac_Prbs_rst0 ) ,.Prbs_set0 ( dac_Prbs_set0 ) ,.Prbs_rst1 ( dac_Prbs_rst1 ) ,.Prbs_set1 ( dac_Prbs_set1 ) ,.Cal_sig ( dac_Cal_sig ) ,.Cal_end ( dac_Cal_end ) ,.Cal_rstn ( dac_Cal_rstn ) ,.Cal_div_rstn ( Cal_div_rstn ) ); endmodule `include "../define/chip_undefine.v" `include "../qubitmcu/qbmcu_undefines.v"