module sync_buf #(
)(
    input   logic   clk,
	input   logic   rst_n,
    input   logic   ext_ena,
    input   logic   clr_ena,
	input   logic   clr_ena_sync,
    input   logic   sync_in,
    output  logic   sync_int,
    output  logic   sync_ext,
    output  logic   sync_clr
);



logic [2:0] sync_r;
always @(posedge clk or negedge rst_n) begin
  if(!rst_n) begin
    sync_r[2:0] <= 3'b000;               
    sync_int <= 1'b0;     
    sync_ext <= 1'b0;                  
  end
  else begin
    sync_r[2:0] <= {sync_r[1:0],sync_in};               // delay two clock
    sync_int <= (sync_r[2:1] == 2'b01) & !clr_ena_sync;      // detect pos edge
    sync_ext <= sync_r[2] & ext_ena;                    // sync input to clk
  end
end

assign sync_clr = ~(clr_ena & sync_in);                 // controlled buf out

endmodule