`timescale 1ns/1ps
//====================================================
//Author : pwy
//Date   : 2020-06-24
//Des    : async set & sync release
//====================================================
module rst_sync(
input	clk_d      ,
input	async_rstn ,
output  sync_rstn
);

reg rstn_s1;
reg rstn_s2;

always@(posedge clk_d or negedge async_rstn)begin
	if(!async_rstn)begin
		rstn_s1 <=1'b0;
		rstn_s2 <=1'b0;
	end
	else begin
		rstn_s1 <=1'b1;
		rstn_s2 <=rstn_s1;
	end
end

assign sync_rstn = rstn_s2;

endmodule