//+FHDR--------------------------------------------------------------------------------------------------------
//  Company: 
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//  File Name             :    qbmcu_exu_alu_ext.v
//  Department            :    
//  Author                :    PWY
//  Author's Tel          :     
//-----------------------------------------------------------------------------------------------------------------
//  Relese History
//  Version     Date            Author          Description
//  0.1         2024-03-13      PWY             The Write-Back module to arbitrate the write-back request to regfile
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//  Keywords            :       
//
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//  Parameter
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//  Purpose                 :
//                      
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//  Target Device:        
//  Tool versions:        
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//  Reuse Issues
//  Reset Strategy: 
//  Clock Domains: 
//  Critical Timing:
//  Asynchronous I/F:
//  Synthesizable (y/n): 
//  Other:
//-FHDR--------------------------------------------------------------------------------------------------------
                                                                         
`include "qbmcu_defines.v"

module qbmcu_wbck(
  //system port
   input                                 clk
  ,input                                 rst_n
  //The enable signal from the master control state machine
  ,input                                 wbck_i_active
  //Write-back target register index from the decoding module
  ,input  [`QBMCU_RFIDX_WIDTH-1      :0] wbck_i_rdidx
  //Write enable for the write-back target register from the decoding module
  ,input                                 wbck_i_rdwen
  //////////////////////////////////////////////////////////////
  // The BJP Write-Back Interface
  ,input [`QBMCU_XLEN-1              :0] bjp_i_wbck_wdat
  ,input                                 bjp_i_wbck_valid
  // The AGU Write-Back Interface
  ,input [`QBMCU_XLEN-1              :0] agu_i_wbck_wdat
  ,input                                 agu_i_wbck_valid
  // The ALU Write-Back Interface
  ,input [`QBMCU_XLEN-1              :0] alu_i_wbck_wdat
  ,input                                 alu_i_wbck_valid
  // The Ext Write-Back Interface
  ,input [`QBMCU_XLEN-1              :0] ext_i_wbck_wdat
  ,input                                 ext_i_wbck_valid

  //////////////////////////////////////////////////////////////
  // The Final arbitrated Write-Back Interface to Regfile
  ,output                                wbck_o_ena
  ,output  [`QBMCU_XLEN-1            :0] wbck_o_wdat
  ,output  [`QBMCU_RFIDX_WIDTH-1     :0] wbck_o_rdidx

  );

//Write-back data multiplexer
wire [`QBMCU_XLEN-1:0] wbck_i_wdat = {`QBMCU_XLEN{bjp_i_wbck_valid}} & bjp_i_wbck_wdat
                                   | {`QBMCU_XLEN{agu_i_wbck_valid}} & agu_i_wbck_wdat
								   | {`QBMCU_XLEN{alu_i_wbck_valid}} & alu_i_wbck_wdat
								   | {`QBMCU_XLEN{ext_i_wbck_valid}} & ext_i_wbck_wdat;
								   

//Assigning Write-back module output signal values
wire wbck_o_ena_w   = wbck_i_rdwen & wbck_i_active;

sirv_gnrl_dffr #(1)wbck_o_ena_dffr (wbck_o_ena_w, wbck_o_ena, clk, rst_n);

assign wbck_o_wdat  = wbck_i_wdat[`QBMCU_XLEN-1:0];
//assign wbck_o_rdidx = wbck_i_rdidx;

sirv_gnrl_dfflr #(`QBMCU_RFIDX_WIDTH)wbck_o_rdidx_dfflr (wbck_i_active, wbck_i_rdidx, wbck_o_rdidx, clk, rst_n);


endmodule                                      
                                               
`include "qbmcu_undefines.v"