//+FHDR--------------------------------------------------------------------------------------------------------
//  Company: 
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//  File Name             :    qbmcu_regfile.v
//  Department            :    
//  Author                :    PWY
//  Author's Tel          :     
//-----------------------------------------------------------------------------------------------------------------
//  Relese History
//  Version     Date            Author   Description
//  0.1         2024-03-13      PWY      The Regfile module to implement the core's general purpose registers file
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//  Keywords            :       
//
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//  Parameter
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//  Purpose                 :
//                      
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//  Target Device:        
//  Tool versions:        
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//  Reuse Issues
//  Reset Strategy: 
//  Clock Domains: 
//  Critical Timing:
//  Asynchronous I/F:
//  Synthesizable (y/n): 
//  Other:
//-FHDR--------------------------------------------------------------------------------------------------------
                                                                         
`include "qbmcu_defines.v"

module qbmcu_regfile(
   input                           clk
  ,input                           rst_n
  ,input  [`QBMCU_RFIDX_WIDTH-1:0] read_src1_idx
  ,input  [`QBMCU_RFIDX_WIDTH-1:0] read_src2_idx
  ,output [`QBMCU_XLEN-1       :0] read_src1_dat
  ,output [`QBMCU_XLEN-1       :0] read_src2_dat

  ,input                           wbck_dest_wen
  ,input  [`QBMCU_RFIDX_WIDTH-1:0] wbck_dest_idx
  ,input  [`QBMCU_XLEN-1       :0] wbck_dest_dat                             
  );

wire [`QBMCU_XLEN-1     :0] rf_r [`QBMCU_RFREG_NUM-1:0];
wire [`QBMCU_RFREG_NUM-1:0] rf_wen;
  
genvar i;
generate //{
  for (i=0; i<`QBMCU_RFREG_NUM; i=i+1) begin:regfile//{
  
    if(i==0) begin: rf0
      // x0 cannot be wrote since it is constant-zeros
      assign rf_wen[i] = 1'b0;
      assign rf_r[i] = `QBMCU_XLEN'b0;
    end
    else begin: rfno0
      assign rf_wen[i] = wbck_dest_wen & (wbck_dest_idx == i) ;
      sirv_gnrl_dfflr #(`QBMCU_XLEN) rf_dfflr (rf_wen[i], wbck_dest_dat, rf_r[i], clk, rst_n);
    end
  
  end//}
endgenerate//}

assign read_src1_dat = rf_r[read_src1_idx];
assign read_src2_dat = rf_r[read_src2_idx];

      
endmodule

`include "qbmcu_undefines.v"