//+FHDR--------------------------------------------------------------------------------------------------------
//  Company: 
//-----------------------------------------------------------------------------------------------------------------
//  File Name             :    qbmcu_ifu.v
//  Department            :    
//  Author                :    PWY
//  Author's Tel          :     
//-----------------------------------------------------------------------------------------------------------------
//  Relese History
//  Version     Date            Author          Description
//  0.1         2024-03-13      PWY             The ifetch module to generate next PC and bus request
//-----------------------------------------------------------------------------------------------------------------
//  Keywords            :       
//
//-----------------------------------------------------------------------------------------------------------------
//  Parameter
//
//-----------------------------------------------------------------------------------------------------------------
//  Purpose                 :
//                      
//-----------------------------------------------------------------------------------------------------------------
//  Target Device:        
//  Tool versions:        
//-----------------------------------------------------------------------------------------------------------------
//  Reuse Issues
//  Reset Strategy: 
//  Clock Domains: 
//  Critical Timing:
//  Asynchronous I/F:
//  Synthesizable (y/n): 
//  Other:
//-FHDR--------------------------------------------------------------------------------------------------------
                                                                         

`include "qbmcu_defines.v"

module qbmcu_ifu(
   input                          clk            // System Clock            
  ,input                          rst_n          // System reset,active low
  ,input                          ifu_active     // IFU module Active from MCU FSM
  ,input                          exu_active     // IFU module Active from MCU FSM
  ,input  [`QBMCU_PC_SIZE-1   :0] pc_rtvec       // Initial PC 
  ,output [`QBMCU_PC_SIZE-1   :0] ifu_req_pc     // Fetch PC
  ,output                         ifu_req        // Fetch req
  
  ,input  [`QBMCU_INSTR_SIZE-1:0] ifu_rsp_instr  // Response instruction
  // The IR stage to DEC interface
  ,output [`QBMCU_INSTR_SIZE-1:0] ifu_o_ir       // The instruction register
  ,output [`QBMCU_PC_SIZE-1   :0] ifu_o_pc       // The PC register along with
  ,input                          ifupc_rst
  ,input                          update_pc_req
  ,input  [`QBMCU_PC_SIZE-1   :0] update_pc_value  
  );


wire                          ifu_req_w;   
wire [`QBMCU_PC_SIZE-1    :0] pc_r;
//wire                          pc_ena;
//wire [`QBMCU_INSTR_SIZE-1 :0] ifu_ir_r;// The instruction register
//wire [`QBMCU_PC_SIZE-1    :0] ifu_pc_r;// The PC register

wire [`QBMCU_PC_SIZE-1:0] pc_nxt_pre;
wire [`QBMCU_PC_SIZE-1:0] pc_nxt;
//ifu_req 
assign ifu_req_w = ifu_active;

 
											   
wire [`QBMCU_PC_SIZE-1:0] pc_add_op1 = 
                                     (rst_n == 1'b0 | ifupc_rst) ? pc_rtvec :
                                                       pc_r;

wire [`QBMCU_PC_SIZE-1:0] pc_add_op2 =  
                                     (rst_n == 1'b0 | ifupc_rst) ? `QBMCU_PC_SIZE'b0 :
                                                       32'h4 ;

assign pc_nxt_pre = pc_add_op1 + pc_add_op2;
//pc_nxt 
assign pc_nxt = update_pc_req ? {update_pc_value[`QBMCU_PC_SIZE-1:1],1'b0} :
                                {pc_nxt_pre[`QBMCU_PC_SIZE-1:1]     ,1'b0};											   
                


// The PC will need to be updated when MCU's FSM is IFU status
//sirv_gnrl_dffr #(1) pc_ena_dffr (ifu_active, pc_ena, clk, rst_n);
//pc_r
sirv_gnrl_dfflr #(`QBMCU_PC_SIZE) pc_dfflr (exu_active, pc_nxt, pc_r, clk, rst_n & ~ifupc_rst);
/*
always @(posedge clk or negedge rst_n) begin
  if(rst_n == 1'b0) begin
    pc_r <= `QBMCU_PC_SIZE'h0;
  end
  else if(ifupc_rst) begin
     pc_r <= `QBMCU_PC_SIZE'h0;
  end
  else if(exu_active) begin
    pc_r <= pc_nxt;
  end
end
*/
// IFU-IR loaded with the returned instruction from the IFetch RSP channel
wire [`QBMCU_INSTR_SIZE-1:0] ifu_ir_nxt = ifu_rsp_instr;
//ifu_ir_r
//sirv_gnrl_dfflr #(`QBMCU_INSTR_SIZE) ifu_ir_dfflr (ifu_active, ifu_ir_nxt, ifu_ir_r, clk, rst_n);

//ifu_pc_r
//sirv_gnrl_dfflr #(`QBMCU_PC_SIZE) ifu_pc_dfflr (ifu_active, pc_r,  ifu_pc_r, clk, rst_n);

//ifu_req_pc
assign ifu_req_pc = pc_r;

assign ifu_req    = ifu_req_w;
//assign ifu_req    = pc_ena;
  
assign ifu_o_ir   = ifu_ir_nxt;
assign ifu_o_pc   = pc_r;
 
endmodule
`include "qbmcu_undefines.v"