//+FHDR--------------------------------------------------------------------------------------------------------
//  Company: 
//-----------------------------------------------------------------------------------------------------------------
//  File Name             :    qbmcu_fsm.v
//  Department            :    
//  Author                :    PWY
//  Author's Tel          :     
//-----------------------------------------------------------------------------------------------------------------
//  Relese History
//  Version     Date            Author          Description
//  0.1         2024-03-13      PWY             The ifetch module to generate next PC and bus request
//-----------------------------------------------------------------------------------------------------------------
//  Keywords            :       
//
//-----------------------------------------------------------------------------------------------------------------
//  Parameter
//
//-----------------------------------------------------------------------------------------------------------------
//  Purpose                 :
//                      
//-----------------------------------------------------------------------------------------------------------------
//  Target Device:        
//  Tool versions:        
//-----------------------------------------------------------------------------------------------------------------
//  Reuse Issues
//  Reset Strategy: 
//  Clock Domains: 
//  Critical Timing:
//  Asynchronous I/F:
//  Synthesizable (y/n): 
//  Other:
//-FHDR--------------------------------------------------------------------------------------------------------
                                                                         
`include "qbmcu_defines.v"

module qbmcu_fsm (
   input          clk
  ,input          rst_n
  ,input          start
  ,input          exit
  ,input          ext_wait
  ,input          qbmcu_timer_done
  ,input          dec_ilegl
  ,input          agu_addr_unalgn 
  ,output         ifupc_rst
  ,output         ifu_active
  ,output         wb_active
  ,output         dec_active
  ,output         exu_active
  ,output [2:0]   qbmcu_fsm_st        
);

localparam IDLE  = 3'b000,
           IFUWB = 3'b001,
		   DEC   = 3'b010,
		   EXU   = 3'b011,
		   WAIT  = 3'b100;

wire [2:0] state_c;
wire [2:0] state_n;		  
wire       ilde2ifuwb;
wire       ifuwb2dec;
wire       dec2exu;
wire       exu2ifuwb;
wire       exu2idle;
wire       exu2wait;
wire       wait2ifuwb;

//The first section of the state machine
//state_c
sirv_gnrl_dffr #(3) state_c_dffr (state_n, state_c, clk, rst_n);

//////////////////////////////////////////////////////////////
//fsm
//////////////////////////////////////////////////////////////

//state_n
assign state_n   = //(rst_n == 1'b0)                    ? IDLE    : 
                   ((state_c == IDLE ) && ilde2ifuwb) ? IFUWB   :
                   ((state_c == IFUWB) && ifuwb2dec ) ? DEC     :
				   ((state_c == DEC  ) && dec2exu   ) ? EXU     :
				   ((state_c == EXU  ) && exu2idle  ) ? IDLE    :
				   ((state_c == EXU  ) && exu2ifuwb ) ? IFUWB   :
				   ((state_c == EXU  ) && exu2wait  ) ? WAIT    :
				   ((state_c == WAIT ) && wait2ifuwb) ? IFUWB   :
				                                        state_c ;																										

//Generating jump conditions for state machines
assign ilde2ifuwb = (state_c == IDLE ) && start;
assign ifuwb2dec  = (state_c == IFUWB) ;
assign dec2exu    = (state_c == DEC  ) ;
assign exu2ifuwb  = (state_c == EXU  ) && !ext_wait && !(exit | dec_ilegl | agu_addr_unalgn);
assign exu2wait   = (state_c == EXU  ) &&  ext_wait && !(exit | dec_ilegl | agu_addr_unalgn);
assign exu2idle   = (state_c == EXU  ) && (exit | dec_ilegl | agu_addr_unalgn);
assign wait2ifuwb = (state_c == WAIT ) && qbmcu_timer_done ;

//Output signal generation
//ifupc_rst
sirv_gnrl_dffr #(1) ifupc_rst_dffr (exu2idle, ifupc_rst, clk, rst_n);
//ifu_active
sirv_gnrl_dffr #(1) ifu_active_dffr (ilde2ifuwb | exu2ifuwb | wait2ifuwb, ifu_active, clk, rst_n);
//wb_active
sirv_gnrl_dffr #(1) wb_active_dffr (exu2ifuwb | wait2ifuwb, wb_active, clk, rst_n);
//dec_active
sirv_gnrl_dffr #(1) dec_active_dffr (ifuwb2dec, dec_active, clk, rst_n);
//exu_active
sirv_gnrl_dffr #(1) exu_active_dffr (dec2exu, exu_active, clk, rst_n);
//qbmcu_fsm_st
sirv_gnrl_dffr #(3) qbmcu_fsm_st_dffr (state_c, qbmcu_fsm_st, clk, rst_n);


endmodule
`include "qbmcu_undefines.v"