//+FHDR--------------------------------------------------------------------------------------------------------
//  Company: 
//-----------------------------------------------------------------------------------------------------------------
//  File Name             :    qbmcu_exu_ext.v
//  Department            :    
//  Author                :    PWY
//  Author's Tel          :     
//-----------------------------------------------------------------------------------------------------------------
//  Relese History
//  Version     Date            Author          Description
//  0.1         2024-03-13      PWY             This module to implement the regular EXT instructions
//-----------------------------------------------------------------------------------------------------------------
//  Keywords            :       
//
//-----------------------------------------------------------------------------------------------------------------
//  Parameter
//
//-----------------------------------------------------------------------------------------------------------------
//  Purpose                 :
//                      
//-----------------------------------------------------------------------------------------------------------------
//  Target Device:        
//  Tool versions:        
//-----------------------------------------------------------------------------------------------------------------
//  Reuse Issues
//  Reset Strategy: 
//  Clock Domains: 
//  Critical Timing:
//  Asynchronous I/F:
//  Synthesizable (y/n): 
//  Other:
//-FHDR--------------------------------------------------------------------------------------------------------
                                                                         
`include "qbmcu_defines.v"
                                                                        

module qbmcu_exu_ext(
  //system port
   input                                 clk
  ,input                                 rst_n
  //////////////////////////////////////////////////////////////
  //////////////////////////////////////////////////////////////
  ,input  [`QBMCU_XLEN-1             :0] ext_i_rs1
  ,input  [`QBMCU_XLEN-1             :0] ext_i_imm
  ,input  [`QBMCU_DECINFO_EXT_WIDTH-1:0] ext_i_info
  ,input                                 ext_i_op
  //The enable signal from the master control state machine
  ,input                                 ext_i_active

  //////////////////////////////////////////////////////////////
  //////////////////////////////////////////////////////////////
  // 
  // The operands and info to peripheral
  ,output                                ext_o_wait_valid
  ,output                                ext_o_wait 
  ,output [`QBMCU_XLEN-1             :0] ext_o_wait_cnt
  ,output                                ext_o_send
  ,output                                ext_o_sendc   
  ,output [`QBMCU_XLEN-1             :0] ext_o_codeword 
  ,output                                ext_o_exit
  ,output                                ext_o_intr  
  ,output [`QBMCU_XLEN-1             :0] ext_o_wbck_wdat
  ,output                                ext_o_wbck_valid
  );


wire [`QBMCU_XLEN-1:0] ext_req_alu_op1  = ext_i_rs1;
wire [`QBMCU_XLEN-1:0] ext_req_alu_op2  = ext_i_imm;

wire [`QBMCU_XLEN-1:0] ext_req_alu_res  = ext_req_alu_op1 + ext_req_alu_op2;
wire alu_req_alu_wait   = ext_i_op & ext_i_info [`QBMCU_DECINFO_EXT_WAIT  ];
wire alu_req_alu_send   = ext_i_op & ext_i_info [`QBMCU_DECINFO_EXT_SEND  ];
wire alu_req_alu_sendc  = ext_i_op & ext_i_info [`QBMCU_DECINFO_EXT_SENDC ];
wire alu_req_alu_exit   = ext_i_op & ext_i_info [`QBMCU_DECINFO_EXT_EXIT  ];
wire alu_req_alu_exiti  = ext_i_op & ext_i_info [`QBMCU_DECINFO_EXT_EXITI ];

//ext_o_codeword
sirv_gnrl_dfflr #(`QBMCU_XLEN) ext_o_codeword_dfflr (ext_i_active, ext_req_alu_res, ext_o_codeword, clk, rst_n);

//ext_o_wait_cnt
//sirv_gnrl_dfflr #(`QBMCU_XLEN) ext_o_wait_cnt_dfflr (ext_i_active, ext_req_alu_res, ext_o_wait_cnt, clk, rst_n);
assign ext_o_wait_cnt = ext_req_alu_res;
//ext_o_wait
wire ext_wait = ext_i_active & alu_req_alu_wait;
//sirv_gnrl_dffr #(1) ext_o_wait_dffr (ext_wait, ext_o_wait, clk, rst_n);
assign ext_o_wait = ext_wait;

wire ext_o_wait_valid_en = ext_wait | ext_i_active;
wire ext_o_wait_valid_v  = ext_wait ?     1'b1 :
                           ext_i_active ? 1'b0 :
						                  1'b0 ;
sirv_gnrl_dfflr #(1) ext_o_wait_valid_dfflr (ext_o_wait_valid_en, ext_o_wait_valid_v, ext_o_wait_valid, clk, rst_n);
//ext_o_send
wire ext_send = ext_i_active & alu_req_alu_send;
sirv_gnrl_dffr #(1) ext_o_send_dffr (ext_send, ext_o_send, clk, rst_n);

//ext_o_sendc
wire ext_sendc = ext_i_active & alu_req_alu_sendc;
sirv_gnrl_dffr #(1) ext_o_sendc_dffr (ext_sendc, ext_o_sendc, clk, rst_n);

//ext_o_exit
assign ext_o_exit = alu_req_alu_exit | alu_req_alu_exiti;
//sirv_gnrl_dfflr #(1) ext_o_exit_dfflr (ext_i_active, ext_exit, ext_o_exit, clk, rst_n);

//ext_o_intr
wire ext_intr = ext_i_active & alu_req_alu_exiti;
sirv_gnrl_dffr #(1) ext_o_intr_dffr (ext_intr, ext_o_intr, clk, rst_n);

/////////////////////////////////////////////////////////////////////////////////////////////
//
/////////////////////////////////////////////////////////////////////////////////////////////
//ext_i_active_r
wire ext_i_active_r;
sirv_gnrl_dffr #(1) ext_i_active_r_dffr (ext_i_active,  ext_i_active_r, clk, rst_n);  
//ext_o_wbck_wdat
sirv_gnrl_dfflr #(`QBMCU_XLEN) ext_o_wbck_wdat_dfflr (ext_i_active_r, ext_req_alu_res,  ext_o_wbck_wdat, clk, rst_n);
//ext_o_wbck_valid
sirv_gnrl_dfflr #(1) ext_o_wbck_valid_dfflr (ext_i_active_r, ext_i_op,  ext_o_wbck_valid, clk, rst_n);


endmodule
`include "qbmcu_undefines.v"