//+FHDR-------------------------------------------------------------------------------------------------------- // Company: //----------------------------------------------------------------------------------------------------------------- // File Name : qbmcu_exu.v // Department : // Author : PWY // Author's Tel : //----------------------------------------------------------------------------------------------------------------- // Relese History // Version Date Author Description // 0.1 2024-03-13 PWY The EXU module to implement entire Execution Stage //----------------------------------------------------------------------------------------------------------------- // Keywords : // //----------------------------------------------------------------------------------------------------------------- // Parameter // //----------------------------------------------------------------------------------------------------------------- // Purpose : // //----------------------------------------------------------------------------------------------------------------- // Target Device: // Tool versions: //----------------------------------------------------------------------------------------------------------------- // Reuse Issues // Reset Strategy: // Clock Domains: // Critical Timing: // Asynchronous I/F: // Synthesizable (y/n): // Other: //-FHDR-------------------------------------------------------------------------------------------------------- `include "qbmcu_defines.v" module qbmcu_exu( //system port input clk ,input rst_n ////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////// // The Handshake Interface // ,input [`QBMCU_XLEN-1 :0] exu_i_rs1 ,input [`QBMCU_XLEN-1 :0] exu_i_rs2 ,input [`QBMCU_XLEN-1 :0] exu_i_imm ,input [`QBMCU_PC_SIZE-1 :0] exu_i_pc ,input [`QBMCU_DECINFO_WIDTH-1 :0] exu_i_info ,input exu_i_ilegl //The enable signal from the master control state machine ,input exu_i_active ////////////////////////////////////////////////////////////// //Data sent to the write-back module //write back interface ,output [`QBMCU_XLEN-1 :0] bjp_o_wbck_wdat ,output bjp_o_wbck_valid ////////////////////////////////////////////////////////////// //update the value of the program counter (PC) ,output bjp_update_pc_req ,output [`QBMCU_PC_SIZE-1 :0] bjp_update_pc_value // The operands and info to peripheral ,output ext_o_wait_valid ,output ext_o_wait ,output [`QBMCU_XLEN-1 :0] ext_o_wait_cnt ,output ext_o_send ,output ext_o_sendc ,output [`QBMCU_XLEN-1 :0] ext_o_codeword ,output ext_o_exit ,output ext_o_intr ,output [`QBMCU_XLEN-1 :0] ext_o_wbck_wdat ,output ext_o_wbck_valid ////////////////////////////////////////////////////////////// //Address, data, and enable signals connected to the memory space ,output [`QBMCU_ADDR_SIZE-1 :0] agu_o_addr ,output [`QBMCU_XLEN-1 :0] agu_o_wdata ,output agu_o_wren // Write enable ,output agu_o_rden // Read enable ,output [`QBMCU_XLEN/8-1 :0] agu_o_wmask ,input [`QBMCU_XLEN-1 :0] agu_i_rdata //Data sent to the write-back module //write back interface ,output [`QBMCU_XLEN-1 :0] agu_o_wbck_wdat ,output agu_o_wbck_valid //Misaligned memory address ,output agu_o_addr_unalgn // The Write-Back Interface for Special (unaligned ldst instructions) ,output [`QBMCU_XLEN-1 :0] alu_o_wbck_wdat ,output alu_o_wbck_valid ); //////////////////////////////////////////////////////////////////////////////////////////////////////////// //AGU //////////////////////////////////////////////////////////////////////////////////////////////////////////// wire [`QBMCU_XLEN-1 :0] agu_i_rs1 ; wire [`QBMCU_XLEN-1 :0] agu_i_rs2 ; wire [`QBMCU_XLEN-1 :0] agu_i_imm ; wire [`QBMCU_DECINFO_WIDTH-1 :0] agu_i_info ; wire agu_i_op ; //qbmcu_datalatch_agu qbmcu_datalatch #( .DECINFO_GRP_OP ( `QBMCU_DECINFO_GRP_AGU ) ) U_qubitmcu_datalatch_agu ( .i_rs1 ( exu_i_rs1 ) ,.i_rs2 ( exu_i_rs2 ) ,.i_imm ( exu_i_imm ) ,.i_info ( exu_i_info ) ,.i_pc ( exu_i_pc ) ,.i_ilegl ( exu_i_ilegl ) ,.o_rs1 ( agu_i_rs1 ) ,.o_rs2 ( agu_i_rs2 ) ,.o_imm ( agu_i_imm ) ,.o_info ( agu_i_info ) ,.o_pc ( ) ,.o_op ( agu_i_op ) ); //qbmcu_exu_lsuagu qbmcu_exu_lsuagu U_qbmcu_exu_lsuagu ( .clk ( clk ) ,.rst_n ( rst_n ) ,.agu_i_rs1 ( agu_i_rs1 ) ,.agu_i_rs2 ( agu_i_rs2 ) ,.agu_i_imm ( agu_i_imm ) ,.agu_i_info ( agu_i_info[`QBMCU_DECINFO_AGU_WIDTH-1:0]) ,.agu_i_op ( agu_i_op ) ,.agu_i_active ( exu_i_active ) ,.agu_o_addr ( agu_o_addr ) ,.agu_o_wdata ( agu_o_wdata ) ,.agu_o_wren ( agu_o_wren ) ,.agu_o_rden ( agu_o_rden ) ,.agu_o_wmask ( agu_o_wmask ) ,.agu_i_rdata ( agu_i_rdata ) ,.agu_o_wbck_wdat ( agu_o_wbck_wdat ) ,.agu_o_wbck_valid ( agu_o_wbck_valid ) ,.agu_o_addr_unalgn ( agu_o_addr_unalgn ) ); //////////////////////////////////////////////////////////////////////////////////////////////////////////// //EXT //////////////////////////////////////////////////////////////////////////////////////////////////////////// wire [`QBMCU_XLEN-1 :0] ext_i_rs1 ; wire [`QBMCU_XLEN-1 :0] ext_i_imm ; wire [`QBMCU_DECINFO_WIDTH-1 :0] ext_i_info ; wire ext_i_op ; //qbmcu_datalatch_ext qbmcu_datalatch #( .DECINFO_GRP_OP ( `QBMCU_DECINFO_GRP_EXT ) ) U_qubitmcu_datalatch_ext ( .i_rs1 ( exu_i_rs1 ) ,.i_rs2 ( exu_i_rs2 ) ,.i_imm ( exu_i_imm ) ,.i_info ( exu_i_info ) ,.i_pc ( exu_i_pc ) ,.i_ilegl ( exu_i_ilegl ) ,.o_rs1 ( ext_i_rs1 ) ,.o_rs2 ( ) ,.o_imm ( ext_i_imm ) ,.o_info ( ext_i_info ) ,.o_pc ( ) ,.o_op ( ext_i_op ) ); //qbmcu_exu_ext qbmcu_exu_ext U_qbmcu_exu_ext ( .clk ( clk ) ,.rst_n ( rst_n ) ,.ext_i_rs1 ( ext_i_rs1 ) ,.ext_i_imm ( ext_i_imm ) ,.ext_i_info ( ext_i_info[`QBMCU_DECINFO_EXT_WIDTH-1:0]) ,.ext_i_op ( ext_i_op ) ,.ext_o_wait_valid ( ext_o_wait_valid ) ,.ext_i_active ( exu_i_active ) ,.ext_o_wait ( ext_o_wait ) ,.ext_o_wait_cnt ( ext_o_wait_cnt ) ,.ext_o_send ( ext_o_send ) ,.ext_o_sendc ( ext_o_sendc ) ,.ext_o_codeword ( ext_o_codeword ) ,.ext_o_exit ( ext_o_exit ) ,.ext_o_intr ( ext_o_intr ) ,.ext_o_wbck_wdat ( ext_o_wbck_wdat ) ,.ext_o_wbck_valid ( ext_o_wbck_valid ) ); //////////////////////////////////////////////////////////////////////////////////////////////////////////// //BJP //////////////////////////////////////////////////////////////////////////////////////////////////////////// wire [`QBMCU_XLEN-1 :0] bjp_i_rs1 ; wire [`QBMCU_XLEN-1 :0] bjp_i_rs2 ; wire [`QBMCU_XLEN-1 :0] bjp_i_imm ; wire [`QBMCU_DECINFO_WIDTH-1 :0] bjp_i_info ; wire [`QBMCU_PC_SIZE-1 :0] bjp_i_pc ; wire bjp_i_op ; ////////////////////////////////////////////////////////////// // To share the ALU datapath // The operands and info to ALU wire [`QBMCU_XLEN-1 :0] bjp_req_alu_op1 ; wire [`QBMCU_XLEN-1 :0] bjp_req_alu_op2 ; wire bjp_req_alu_cmp_eq ; wire bjp_req_alu_cmp_ne ; wire bjp_req_alu_cmp_lt ; wire bjp_req_alu_cmp_gt ; wire bjp_req_alu_cmp_ltu ; wire bjp_req_alu_cmp_gtu ; wire bjp_req_alu_add ; wire bjp_req_alu_cmp_res ; wire [`QBMCU_XLEN-1 :0] bjp_req_alu_add_res ; //qbmcu_datalatch_bjp qbmcu_datalatch #( .DECINFO_GRP_OP ( `QBMCU_DECINFO_GRP_BJP ) ) U_qubitmcu_datalatch_bjp ( .i_rs1 ( exu_i_rs1 ) ,.i_rs2 ( exu_i_rs2 ) ,.i_imm ( exu_i_imm ) ,.i_info ( exu_i_info ) ,.i_pc ( exu_i_pc ) ,.i_ilegl ( exu_i_ilegl ) ,.o_rs1 ( bjp_i_rs1 ) ,.o_rs2 ( bjp_i_rs2 ) ,.o_imm ( bjp_i_imm ) ,.o_info ( bjp_i_info ) ,.o_pc ( bjp_i_pc ) ,.o_op ( bjp_i_op ) ); //qbmcu_exu_bjp qbmcu_exu_bjp U_qbmcu_exu_bjp ( .clk ( clk ) ,.rst_n ( rst_n ) ,.bjp_i_rs1 ( bjp_i_rs1 ) ,.bjp_i_rs2 ( bjp_i_rs2 ) ,.bjp_i_imm ( bjp_i_imm ) ,.bjp_i_pc ( bjp_i_pc ) ,.bjp_i_info ( bjp_i_info[`QBMCU_DECINFO_BJP_WIDTH-1:0]) ,.bjp_i_op ( bjp_i_op ) ,.bjp_i_active ( exu_i_active ) ,.bjp_o_wbck_valid ( bjp_o_wbck_valid ) ,.bjp_o_wbck_wdat ( bjp_o_wbck_wdat ) ,.update_pc_req ( bjp_update_pc_req ) ,.update_pc_value ( bjp_update_pc_value ) ,.bjp_req_alu_op1 ( bjp_req_alu_op1 ) ,.bjp_req_alu_op2 ( bjp_req_alu_op2 ) ,.bjp_req_alu_cmp_eq ( bjp_req_alu_cmp_eq ) ,.bjp_req_alu_cmp_ne ( bjp_req_alu_cmp_ne ) ,.bjp_req_alu_cmp_lt ( bjp_req_alu_cmp_lt ) ,.bjp_req_alu_cmp_gt ( bjp_req_alu_cmp_gt ) ,.bjp_req_alu_cmp_ltu ( bjp_req_alu_cmp_ltu ) ,.bjp_req_alu_cmp_gtu ( bjp_req_alu_cmp_gtu ) ,.bjp_req_alu_add ( bjp_req_alu_add ) ,.bjp_req_alu_cmp_res ( bjp_req_alu_cmp_res ) ,.bjp_req_alu_add_res ( bjp_req_alu_add_res ) ); //////////////////////////////////////////////////////////////////////////////////////////////////////////// //ALU //////////////////////////////////////////////////////////////////////////////////////////////////////////// wire [`QBMCU_XLEN-1 :0] alu_i_rs1 ; wire [`QBMCU_XLEN-1 :0] alu_i_rs2 ; wire [`QBMCU_XLEN-1 :0] alu_i_imm ; wire [`QBMCU_DECINFO_WIDTH-1 :0] alu_i_info ; wire [`QBMCU_PC_SIZE-1 :0] alu_i_pc ; wire alu_i_op ; ////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////// // To share the ALU datapath // // The operands and info to ALU wire alu_req_alu_add ; wire alu_req_alu_sub ; wire alu_req_alu_xor ; wire alu_req_alu_sll ; wire alu_req_alu_srl ; wire alu_req_alu_sra ; wire alu_req_alu_or ; wire alu_req_alu_and ; wire alu_req_alu_slt ; wire alu_req_alu_sltu ; wire alu_req_alu_lui ; wire [`QBMCU_XLEN-1 :0] alu_req_alu_op1 ; wire [`QBMCU_XLEN-1 :0] alu_req_alu_op2 ; wire [`QBMCU_XLEN-1 :0] alu_req_alu_res ; //qbmcu_datalatch_alu qbmcu_datalatch #( .DECINFO_GRP_OP ( `QBMCU_DECINFO_GRP_ALU ) ) U_qbmcu_datalatch_alu ( .i_rs1 ( exu_i_rs1 ) ,.i_rs2 ( exu_i_rs2 ) ,.i_imm ( exu_i_imm ) ,.i_info ( exu_i_info ) ,.i_pc ( exu_i_pc ) ,.i_ilegl ( exu_i_ilegl ) ,.o_rs1 ( alu_i_rs1 ) ,.o_rs2 ( alu_i_rs2 ) ,.o_imm ( alu_i_imm ) ,.o_info ( alu_i_info ) ,.o_pc ( alu_i_pc ) ,.o_op ( alu_i_op ) ); //qbmcu_exu_alu_rglr qbmcu_exu_alu U_qbmcu_exu_alu ( .clk ( clk ) ,.rst_n ( rst_n ) ,.alu_i_rs1 ( alu_i_rs1 ) ,.alu_i_rs2 ( alu_i_rs2 ) ,.alu_i_imm ( alu_i_imm ) ,.alu_i_pc ( alu_i_pc ) ,.alu_i_info ( alu_i_info[`QBMCU_DECINFO_ALU_WIDTH-1:0]) ,.alu_i_op ( alu_i_op ) ,.alu_i_active ( exu_i_active ) ,.alu_o_wbck_wdat ( alu_o_wbck_wdat ) ,.alu_o_wbck_valid ( alu_o_wbck_valid ) ,.alu_req_alu_add ( alu_req_alu_add ) ,.alu_req_alu_sub ( alu_req_alu_sub ) ,.alu_req_alu_xor ( alu_req_alu_xor ) ,.alu_req_alu_sll ( alu_req_alu_sll ) ,.alu_req_alu_srl ( alu_req_alu_srl ) ,.alu_req_alu_sra ( alu_req_alu_sra ) ,.alu_req_alu_or ( alu_req_alu_or ) ,.alu_req_alu_and ( alu_req_alu_and ) ,.alu_req_alu_slt ( alu_req_alu_slt ) ,.alu_req_alu_sltu ( alu_req_alu_sltu ) ,.alu_req_alu_lui ( alu_req_alu_lui ) ,.alu_req_alu_op1 ( alu_req_alu_op1 ) ,.alu_req_alu_op2 ( alu_req_alu_op2 ) ,.alu_req_alu_res ( alu_req_alu_res ) ); //////////////////////////////////////////////////////////////////////////////////////////////////////////// //DPATH //////////////////////////////////////////////////////////////////////////////////////////////////////////// qbmcu_exu_dpath U_qbmcu_exu_dpath ( .alu_req_alu ( alu_i_op ) ,.alu_req_alu_add ( alu_req_alu_add ) ,.alu_req_alu_sub ( alu_req_alu_sub ) ,.alu_req_alu_xor ( alu_req_alu_xor ) ,.alu_req_alu_sll ( alu_req_alu_sll ) ,.alu_req_alu_srl ( alu_req_alu_srl ) ,.alu_req_alu_sra ( alu_req_alu_sra ) ,.alu_req_alu_or ( alu_req_alu_or ) ,.alu_req_alu_and ( alu_req_alu_and ) ,.alu_req_alu_slt ( alu_req_alu_slt ) ,.alu_req_alu_sltu ( alu_req_alu_sltu ) ,.alu_req_alu_lui ( alu_req_alu_lui ) ,.alu_req_alu_op1 ( alu_req_alu_op1 ) ,.alu_req_alu_op2 ( alu_req_alu_op2 ) ,.alu_req_alu_res ( alu_req_alu_res ) ,.bjp_req_alu ( bjp_i_op ) ,.bjp_req_alu_op1 ( bjp_req_alu_op1 ) ,.bjp_req_alu_op2 ( bjp_req_alu_op2 ) ,.bjp_req_alu_cmp_eq ( bjp_req_alu_cmp_eq ) ,.bjp_req_alu_cmp_ne ( bjp_req_alu_cmp_ne ) ,.bjp_req_alu_cmp_lt ( bjp_req_alu_cmp_lt ) ,.bjp_req_alu_cmp_gt ( bjp_req_alu_cmp_gt ) ,.bjp_req_alu_cmp_ltu ( bjp_req_alu_cmp_ltu ) ,.bjp_req_alu_cmp_gtu ( bjp_req_alu_cmp_gtu ) ,.bjp_req_alu_add ( bjp_req_alu_add ) ,.bjp_req_alu_cmp_res ( bjp_req_alu_cmp_res ) ,.bjp_req_alu_add_res ( bjp_req_alu_add_res ) ); endmodule `include "qbmcu_undefines.v"