//+FHDR-------------------------------------------------------------------------------------------------------- // Company: //----------------------------------------------------------------------------------------------------------------- // File Name : qbmcu.v // Department : // Author : PWY // Author's Tel : //----------------------------------------------------------------------------------------------------------------- // Relese History // Version Date Author Description // 0.1 2024-03-13 PWY Quantum Bit Measurement and Control Microprocessor //----------------------------------------------------------------------------------------------------------------- // Keywords : // //----------------------------------------------------------------------------------------------------------------- // Parameter // //----------------------------------------------------------------------------------------------------------------- // Purpose : // //----------------------------------------------------------------------------------------------------------------- // Target Device: // Tool versions: //----------------------------------------------------------------------------------------------------------------- // Reuse Issues // Reset Strategy: // Clock Domains: // Critical Timing: // Asynchronous I/F: // Synthesizable (y/n): // Other: //-FHDR-------------------------------------------------------------------------------------------------------- `include "qbmcu_defines.v" module qbmcu( //system port input clk ,input rst_n //Sync Start ,input qbmcu_i_start ,output [2 :0] qbmcu_o_fsm_st //IFU port ,input [`QBMCU_PC_SIZE-1 :0] ifu_i_pc_rtvec // Initial PC ,output [`QBMCU_PC_SIZE-1 :0] ifu_o_req_pc // Fetch PC ,output ifu_o_req // Fetch req ,input [`QBMCU_INSTR_SIZE-1 :0] ifu_rsp_instr //Decoded port ,output dec_o_ilegl //LDST port //Address, data, and enable signals connected to the memory space ,output [`QBMCU_ADDR_SIZE-1 :0] agu_o_addr ,output [`QBMCU_XLEN-1 :0] agu_o_wrdata ,output agu_o_wren // Write enable ,output [`QBMCU_XLEN/8-1 :0] agu_o_wrmask ,output agu_o_rden // Read enable ,input [`QBMCU_XLEN-1 :0] agu_i_rddata //Misaligned memory address ,output agu_o_addr_unalgn //Extend instructions port // The operands and info to peripheral ,output ext_o_send ,output ext_o_sendc ,output [`QBMCU_XLEN-1 :0] ext_o_codeword ,output ext_o_intr ); //////////////////////////////////////////////////////////////////////////////////////////////////////////// //qbmcu_fsm //////////////////////////////////////////////////////////////////////////////////////////////////////////// wire ifupc_rst ; wire ifu_active ; wire wb_active ; wire dec_active ; wire exu_active ; wire ext_wait ; wire ext_o_exit ; wire qbmcu_i_timer_done ; qbmcu_fsm U_qbmcu_fsm ( .clk ( clk ) ,.rst_n ( rst_n ) ,.start ( qbmcu_i_start ) ,.exit ( ext_o_exit ) ,.ext_wait ( ext_wait ) ,.qbmcu_timer_done ( qbmcu_i_timer_done ) ,.agu_addr_unalgn ( agu_o_addr_unalgn ) ,.dec_ilegl ( dec_o_ilegl ) ,.ifupc_rst ( ifupc_rst ) ,.wb_active ( wb_active ) ,.ifu_active ( ifu_active ) ,.dec_active ( dec_active ) ,.exu_active ( exu_active ) ,.qbmcu_fsm_st ( qbmcu_o_fsm_st ) ); //////////////////////////////////////////////////////////////////////////////////////////////////////////// //qbmcu_ifu_ifetch //////////////////////////////////////////////////////////////////////////////////////////////////////////// wire [`QBMCU_INSTR_SIZE-1:0] ifu_ir ; wire [`QBMCU_PC_SIZE-1 :0] ifu_pc ; wire update_pc_req ; wire [`QBMCU_PC_SIZE-1 :0] update_pc_value ; qbmcu_ifu U_qbmcu_ifu ( .clk ( clk ) ,.rst_n ( rst_n ) ,.ifu_active ( ifu_active ) ,.exu_active ( exu_active ) ,.pc_rtvec ( ifu_i_pc_rtvec ) ,.ifu_req_pc ( ifu_o_req_pc ) ,.ifu_req ( ifu_o_req ) ,.ifu_rsp_instr ( ifu_rsp_instr ) ,.ifu_o_ir ( ifu_ir ) ,.ifu_o_pc ( ifu_pc ) ,.ifupc_rst ( ifupc_rst ) ,.update_pc_req ( update_pc_req ) ,.update_pc_value ( update_pc_value ) ); //////////////////////////////////////////////////////////////////////////////////////////////////////////// //qbmcu_decode //////////////////////////////////////////////////////////////////////////////////////////////////////////// //wire dec_rs1en ; //wire dec_rs2en ; wire dec_rdwen ; wire [`QBMCU_RFIDX_WIDTH-1 :0] dec_rs1idx ; wire [`QBMCU_RFIDX_WIDTH-1 :0] dec_rs2idx ; wire [`QBMCU_RFIDX_WIDTH-1 :0] dec_rdidx ; wire [`QBMCU_DECINFO_WIDTH-1:0] dec_info ; wire [`QBMCU_XLEN-1 :0] dec_imm ; wire [`QBMCU_PC_SIZE-1 :0] dec_pc ; qbmcu_decode qbmcu_decode ( .clk ( clk ) ,.rst_n ( rst_n ) ,.dec_i_active ( dec_active ) ,.dec_i_instr ( ifu_ir ) ,.dec_i_pc ( ifu_pc ) //,.dec_o_rs1en ( dec_rs1en ) //,.dec_o_rs2en ( dec_rs2en ) ,.dec_o_rdwen ( dec_rdwen ) ,.dec_o_rs1idx ( dec_rs1idx ) ,.dec_o_rs2idx ( dec_rs2idx ) ,.dec_o_rdidx ( dec_rdidx ) ,.dec_o_info ( dec_info ) ,.dec_o_imm ( dec_imm ) ,.dec_o_pc ( dec_pc ) ,.dec_o_ilegl ( dec_o_ilegl ) ); //////////////////////////////////////////////////////////////////////////////////////////////////////////// //qbmcu_exu //////////////////////////////////////////////////////////////////////////////////////////////////////////// wire [`QBMCU_XLEN-1 :0] exu_rs1 ; wire [`QBMCU_XLEN-1 :0] exu_rs2 ; wire [`QBMCU_XLEN-1 :0] bjp_wbck_wdat ; wire bjp_wbck_valid ; wire [`QBMCU_XLEN-1 :0] agu_wbck_wdat ; wire agu_wbck_valid ; wire [`QBMCU_XLEN-1 :0] alu_wbck_wdat ; wire alu_wbck_valid ; wire [`QBMCU_XLEN-1 :0] ext_wbck_wdat ; wire ext_wbck_valid ; wire [`QBMCU_XLEN-1 :0] ext_wait_cnt ; ////////////////////////////////////////////////////////////// //Address, data, and enable signals connected to the memory space wire ext_o_wait_valid ; qbmcu_exu U_qbmcu_exu ( .clk ( clk ) ,.rst_n ( rst_n ) ,.exu_i_rs1 ( exu_rs1 ) ,.exu_i_rs2 ( exu_rs2 ) ,.exu_i_imm ( dec_imm ) ,.exu_i_pc ( dec_pc ) ,.exu_i_info ( dec_info ) ,.exu_i_ilegl ( dec_o_ilegl ) ,.exu_i_active ( exu_active ) ,.bjp_o_wbck_wdat ( bjp_wbck_wdat ) ,.bjp_o_wbck_valid ( bjp_wbck_valid ) ,.bjp_update_pc_req ( update_pc_req ) ,.bjp_update_pc_value ( update_pc_value ) ,.ext_o_wait_valid ( ext_o_wait_valid ) ,.ext_o_wait ( ext_wait ) ,.ext_o_wait_cnt ( ext_wait_cnt ) ,.ext_o_send ( ext_o_send ) ,.ext_o_sendc ( ext_o_sendc ) ,.ext_o_codeword ( ext_o_codeword ) ,.ext_o_exit ( ext_o_exit ) ,.ext_o_intr ( ext_o_intr ) ,.ext_o_wbck_wdat ( ext_wbck_wdat ) ,.ext_o_wbck_valid ( ext_wbck_valid ) ,.agu_o_addr ( agu_o_addr ) ,.agu_o_wdata ( agu_o_wrdata ) ,.agu_o_wren ( agu_o_wren ) ,.agu_o_rden ( agu_o_rden ) ,.agu_o_wmask ( agu_o_wrmask ) ,.agu_i_rdata ( agu_i_rddata ) ,.agu_o_addr_unalgn ( agu_o_addr_unalgn ) ,.agu_o_wbck_wdat ( agu_wbck_wdat ) ,.agu_o_wbck_valid ( agu_wbck_valid ) ,.alu_o_wbck_wdat ( alu_wbck_wdat ) ,.alu_o_wbck_valid ( alu_wbck_valid ) ); //////////////////////////////////////////////////////////////////////////////////////////////////////////// //qbmcu_wbck //////////////////////////////////////////////////////////////////////////////////////////////////////////// wire wbck_ena ; wire [`QBMCU_XLEN-1 :0] wbck_wdat ; wire [`QBMCU_RFIDX_WIDTH-1 :0] wbck_rdidx ; qbmcu_wbck U_qbmcu_wbck ( .clk ( clk ) ,.rst_n ( rst_n ) ,.wbck_i_active ( wb_active ) ,.wbck_i_rdidx ( dec_rdidx ) ,.wbck_i_rdwen ( dec_rdwen ) ,.bjp_i_wbck_wdat ( bjp_wbck_wdat ) ,.bjp_i_wbck_valid ( bjp_wbck_valid ) ,.agu_i_wbck_wdat ( agu_wbck_wdat ) ,.agu_i_wbck_valid ( agu_wbck_valid ) ,.alu_i_wbck_wdat ( alu_wbck_wdat ) ,.alu_i_wbck_valid ( alu_wbck_valid ) ,.ext_i_wbck_wdat ( ext_wbck_wdat ) ,.ext_i_wbck_valid ( ext_wbck_valid ) ,.wbck_o_ena ( wbck_ena ) ,.wbck_o_rdidx ( wbck_rdidx ) ,.wbck_o_wdat ( wbck_wdat ) ); //////////////////////////////////////////////////////////////////////////////////////////////////////////// //qbmcu_regfile //////////////////////////////////////////////////////////////////////////////////////////////////////////// qbmcu_regfile U_qbmcu_regfile ( .clk ( clk ) ,.rst_n ( rst_n ) ,.read_src1_idx ( dec_rs1idx ) ,.read_src2_idx ( dec_rs2idx ) ,.read_src1_dat ( exu_rs1 ) ,.read_src2_dat ( exu_rs2 ) ,.wbck_dest_wen ( wbck_ena ) ,.wbck_dest_idx ( wbck_rdidx ) ,.wbck_dest_dat ( wbck_wdat ) ); //////////////////////////////////////////////////////////////////////////////////////////////////////////// //DW03_updn_ctr //////////////////////////////////////////////////////////////////////////////////////////////////////////// defparam U_DW03_updn_ctr.width = 32; DW03_updn_ctr U_DW03_updn_ctr ( .clk ( clk )// clock input ,.reset ( rst_n )// asynchronous reset input (active low) ,.data ( ext_wait_cnt-1'b1 )// data used for load operation ,.up_dn ( 1'b0 )// up/down control input (0=down, 1-up) ,.load ( !ext_wait )// load operation control input (active low) ,.cen ( ext_o_wait_valid )// count enable control input (active high enable) ,.count ( )// count value output ,.tercnt ( qbmcu_i_timer_done ) // terminal count output flag (active high) ); endmodule `include "qbmcu_undefines.v"