//+FHDR-------------------------------------------------------------------------------------------------------- // Company: //----------------------------------------------------------------------------------------------------------------- // File Name : mcu_regfile.v // Department : // Author : PWY // Author's Tel : //----------------------------------------------------------------------------------------------------------------- // Relese History // Version Date Author Description // 0.1 2024-03-13 PWY MCU dedicated register file //----------------------------------------------------------------------------------------------------------------- // Keywords : // //----------------------------------------------------------------------------------------------------------------- // Parameter // //----------------------------------------------------------------------------------------------------------------- // Purpose : // //----------------------------------------------------------------------------------------------------------------- // Target Device: // Tool versions: //----------------------------------------------------------------------------------------------------------------- // Reuse Issues // Reset Strategy: // Clock Domains: // Critical Timing: // Asynchronous I/F: // Synthesizable (y/n): // Other: //-FHDR-------------------------------------------------------------------------------------------------------- // ----------------------------------------------------------- // -- Register address offset macros // ----------------------------------------------------------- //MCU parameter register 0 `define MCUPARAR0 16'h00 //MCU parameter register 1 `define MCUPARAR1 16'h04 //MCU parameter register 2 `define MCUPARAR2 16'h08 //MCU parameter register 3 `define MCUPARAR3 16'h0C //MCU result register 0 `define MCURESR0 16'h10 //MCU result register 1 `define MCURESR1 16'h14 //MCU result register 2 `define MCURESR2 16'h18 //MCU result register 3 `define MCURESR3 16'h1C //carrier frequency register 0 `define CWFR0 16'h40 //carrier frequency register 1 `define CWFR1 16'h44 //carrier frequency register 2 `define CWFR2 16'h48 //carrier frequency register 3 `define CWFR3 16'h4C //carrier phase zeroing register `define CWPRR 16'h50 //Gate-attached phase register 0 `define GAPR0 16'h54 //Gate-attached phase register 1 `define GAPR1 16'h58 //Gate-attached phase register 2 `define GAPR2 16'h5C //Gate-attached phase register 3 `define GAPR3 16'h60 //Gate-attached phase register 4 `define GAPR4 16'h64 //Gate-attached phase register 5 `define GAPR5 16'h68 //Gate-attached phase register 6 `define GAPR6 16'h6C //Gate-attached phase register 7 `define GAPR7 16'h70 //Line correction phase register `define LCPR 16'h74 //Amplitude register 0 `define AMPR0 16'h78 //Amplitude register 1 `define AMPR1 16'h7C //Amplitude register 2 `define AMPR2 16'h80 //Amplitude register 3 `define AMPR3 16'h84 //Bias Register 0 `define BIASR0 16'h88 //Bias Register 1 `define BIASR1 16'h8C //Bias Register 2 `define BIASR2 16'h90 //Bias Register 3 `define BIASR3 16'h94 //Run-time register `define RTIMR 16'h98 //Instruction count register `define ICNTR 16'h9C //Feedback state information register `define FSIR 16'hA0 //Interpolator Selection Register `define INTPSELR 16'hA4 module mcu_regfile ( //system port input clk // System Main Clock ,input rst_n // Spi Reset active low //rw op port ,input [31 :0] wrdata // write data ,input wren // write enable ,input [3 :0] wrmask ,input [15 :0] rwaddr // read & write address ,input rden // read enable ,output [31 :0] rddata // read data ,input [1 :0] fb_st_info ,input [31 :0] run_time ,input [31 :0] instr_num //MCU and SPI interface for interaction ,input [31 :0] mcu_param [3:0] // MCU parameter 0~3 ,output [31 :0] mcu_result [3:0] // MCU result 0~3 //lookup table data ,output [31 :0] mcu_cwfr [3:0] // Carrier frequency ctrl word 0~3 ,output [15 :0] mcu_gapr [7:0] // Carrier phase ctrl word 0~3 ,output [15 :0] mcu_ampr [3:0] // Carrier Amplitude 0~3 ,output [15 :0] mcu_baisr [3:0] // Carrier Bais 0~3 //CFG Port ,output [1 :0] mcu_intp_sel //2'b00:HBF;2'b01:Nearest-neighbor interpolator; ,output mcu_nco_pha_clr ,output [15 :0] mcu_rz_pha ); localparam L = 1'b0, H = 1'b1; // ------------------------------------------------------ // -- Register enable (select) wires // ------------------------------------------------------ wire mcuparar0en ; // MCUPARAR0 select wire mcuparar1en ; // MCUPARAR1 select wire mcuparar2en ; // MCUPARAR2 select wire mcuparar3en ; // MCUPARAR3 select wire mcuresr0en ; // MCURESR0 select wire mcuresr1en ; // MCURESR1 select wire mcuresr2en ; // MCURESR2 select wire mcuresr3en ; // MCURESR3 select wire cwfr0en ; // CWFR0 select wire cwfr1en ; // CWFR1 select wire cwfr2en ; // CWFR2 select wire cwfr3en ; // CWFR3 select wire cwprren ; // CWPRR select wire gapr0en ; // GAPR0 select wire gapr1en ; // GAPR1 select wire gapr2en ; // GAPR2 select wire gapr3en ; // GAPR3 select wire gapr4en ; // GAPR4 select wire gapr5en ; // GAPR5 select wire gapr6en ; // GAPR6 select wire gapr7en ; // GAPR7 select wire lcpren ; // LCPR select wire ampr0en ; // AMPR0 select wire ampr1en ; // AMPR1 select wire ampr2en ; // AMPR2 select wire ampr3en ; // AMPR3 select wire baisr0en ; // BIASR0 select wire baisr1en ; // BIASR1 select wire baisr2en ; // BIASR2 select wire baisr3en ; // BIASR3 select wire rtimren ; // RTIMR select wire icntren ; // ICNTR select wire fsiren ; // FSIR select wire intpselren ; // INTPSELR select // ------------------------------------------------------ // -- Register write enable wires // ------------------------------------------------------ wire mcuresr0we ; // MCURESR0 write enable wire mcuresr1we ; // MCURESR1 write enable wire mcuresr2we ; // MCURESR2 write enable wire mcuresr3we ; // MCURESR3 write enable wire cwfr0we ; // CWFR0 write enable wire cwfr1we ; // CWFR1 write enable wire cwfr2we ; // CWFR2 write enable wire cwfr3we ; // CWFR3 write enable wire cwprrwe ; // CWPRR write enable wire gapr0we ; // GAPR0 write enable wire gapr1we ; // GAPR1 write enable wire gapr2we ; // GAPR2 write enable wire gapr3we ; // GAPR3 write enable wire gapr4we ; // GAPR4 write enable wire gapr5we ; // GAPR5 write enable wire gapr6we ; // GAPR6 write enable wire gapr7we ; // GAPR7 write enable wire lcprwe ; // LCPR write enable wire ampr0we ; // AMPR0 write enable wire ampr1we ; // AMPR1 write enable wire ampr2we ; // AMPR2 write enable wire ampr3we ; // AMPR3 write enable wire baisr0we ; // BIASR0 write enable wire baisr1we ; // BIASR1 write enable wire baisr2we ; // BIASR2 write enable wire baisr3we ; // BIASR3 write enable wire intpselrwe ; // INTPSELR select // ------------------------------------------------------ // -- Misc wires // ------------------------------------------------------ // ------------------------------------------------------ // -- Misc Registers // ------------------------------------------------------ wire [31 :0] mcuparar0 ; // MCUPARAR0 register wire [31 :0] mcuparar1 ; // MCUPARAR1 register wire [31 :0] mcuparar2 ; // MCUPARAR2 register wire [31 :0] mcuparar3 ; // MCUPARAR3 register wire [31 :0] mcuresr0 ; // MCURESR0 register wire [31 :0] mcuresr1 ; // MCURESR1 register wire [31 :0] mcuresr2 ; // MCURESR2 register wire [31 :0] mcuresr3 ; // MCURESR3 register wire [31 :0] cwfr0 ; // CWFR0 register wire [31 :0] cwfr1 ; // CWFR1 register wire [31 :0] cwfr2 ; // CWFR2 register wire [31 :0] cwfr3 ; // CWFR3 register wire [0 :0] cwprr ; // CWPRR register wire [15 :0] gapr0 ; // GAPR0 register////////////////////16bit but assign to 31:16? wire [15 :0] gapr1 ; // GAPR1 register wire [15 :0] gapr2 ; // GAPR2 register wire [15 :0] gapr3 ; // GAPR3 register wire [15 :0] gapr4 ; // GAPR4 register wire [15 :0] gapr5 ; // GAPR5 register wire [15 :0] gapr6 ; // GAPR6 register wire [15 :0] gapr7 ; // GAPR7 register wire [15 :0] lcpr ; // LCPR register wire [15 :0] ampr0 ; // AMPR0 register wire [15 :0] ampr1 ; // AMPR1 register wire [15 :0] ampr2 ; // AMPR2 register wire [15 :0] ampr3 ; // AMPR3 register wire [15 :0] baisr0 ; // BIASR0 register wire [15 :0] baisr1 ; // BIASR1 register wire [15 :0] baisr2 ; // BIASR2 register wire [15 :0] baisr3 ; // BIASR3 register wire [31 :0] rtimr ; // RTIMR register wire [31 :0] icntr ; // ICNTR register wire [1 :0] fsir ; // FSIR register wire [1 :0] intpselr ; // INTPSELR register reg [31: 0] rddata_reg ; // ------------------------------------------------------ // -- Address decoder // // Decodes the register address offset input(reg_addr) // to produce enable (select) signals for each of the // SW-registers in the macrocell. The reg_addr input // is bits [15:0] of the paddr bus. // ------------------------------------------------------ assign mcuparar0en = (rwaddr[15:2] == `MCUPARAR0 >> 2) ? 1'b1 : 1'b0; assign mcuparar1en = (rwaddr[15:2] == `MCUPARAR1 >> 2) ? 1'b1 : 1'b0; assign mcuparar2en = (rwaddr[15:2] == `MCUPARAR2 >> 2) ? 1'b1 : 1'b0; assign mcuparar3en = (rwaddr[15:2] == `MCUPARAR3 >> 2) ? 1'b1 : 1'b0; assign mcuresr0en = (rwaddr[15:2] == `MCURESR0 >> 2) ? 1'b1 : 1'b0; assign mcuresr1en = (rwaddr[15:2] == `MCURESR1 >> 2) ? 1'b1 : 1'b0; assign mcuresr2en = (rwaddr[15:2] == `MCURESR2 >> 2) ? 1'b1 : 1'b0; assign mcuresr3en = (rwaddr[15:2] == `MCURESR3 >> 2) ? 1'b1 : 1'b0; assign cwfr0en = (rwaddr[15:2] == `CWFR0 >> 2) ? 1'b1 : 1'b0; assign cwfr1en = (rwaddr[15:2] == `CWFR1 >> 2) ? 1'b1 : 1'b0; assign cwfr2en = (rwaddr[15:2] == `CWFR2 >> 2) ? 1'b1 : 1'b0; assign cwfr3en = (rwaddr[15:2] == `CWFR3 >> 2) ? 1'b1 : 1'b0; assign cwprren = (rwaddr[15:2] == `CWPRR >> 2) ? 1'b1 : 1'b0; assign gapr0en = (rwaddr[15:2] == `GAPR0 >> 2) ? 1'b1 : 1'b0; assign gapr1en = (rwaddr[15:2] == `GAPR1 >> 2) ? 1'b1 : 1'b0; assign gapr2en = (rwaddr[15:2] == `GAPR2 >> 2) ? 1'b1 : 1'b0; assign gapr3en = (rwaddr[15:2] == `GAPR3 >> 2) ? 1'b1 : 1'b0; assign gapr4en = (rwaddr[15:2] == `GAPR4 >> 2) ? 1'b1 : 1'b0; assign gapr5en = (rwaddr[15:2] == `GAPR5 >> 2) ? 1'b1 : 1'b0; assign gapr6en = (rwaddr[15:2] == `GAPR6 >> 2) ? 1'b1 : 1'b0; assign gapr7en = (rwaddr[15:2] == `GAPR7 >> 2) ? 1'b1 : 1'b0; assign lcpren = (rwaddr[15:2] == `LCPR >> 2) ? 1'b1 : 1'b0; assign ampr0en = (rwaddr[15:2] == `AMPR0 >> 2) ? 1'b1 : 1'b0; assign ampr1en = (rwaddr[15:2] == `AMPR1 >> 2) ? 1'b1 : 1'b0; assign ampr2en = (rwaddr[15:2] == `AMPR2 >> 2) ? 1'b1 : 1'b0; assign ampr3en = (rwaddr[15:2] == `AMPR3 >> 2) ? 1'b1 : 1'b0; assign baisr0en = (rwaddr[15:2] == `BIASR0 >> 2) ? 1'b1 : 1'b0; assign baisr1en = (rwaddr[15:2] == `BIASR1 >> 2) ? 1'b1 : 1'b0; assign baisr2en = (rwaddr[15:2] == `BIASR2 >> 2) ? 1'b1 : 1'b0; assign baisr3en = (rwaddr[15:2] == `BIASR3 >> 2) ? 1'b1 : 1'b0; assign rtimren = (rwaddr[15:2] == `RTIMR >> 2) ? 1'b1 : 1'b0; assign icntren = (rwaddr[15:2] == `ICNTR >> 2) ? 1'b1 : 1'b0; assign fsiren = (rwaddr[15:2] == `FSIR >> 2) ? 1'b1 : 1'b0; assign intpselren = (rwaddr[15:2] == `INTPSELR >> 2) ? 1'b1 : 1'b0; // ------------------------------------------------------ // -- Write enable signals // // Write enable signals for writable SW-registers. // The write enable for each register is the ANDed // result of the register enable and the input reg_wren // ------------------------------------------------------ assign mcuresr0we = mcuresr0en & wren; assign mcuresr1we = mcuresr1en & wren; assign mcuresr2we = mcuresr2en & wren; assign mcuresr3we = mcuresr3en & wren; assign cwfr0we = cwfr0en & wren; assign cwfr1we = cwfr1en & wren; assign cwfr2we = cwfr2en & wren; assign cwfr3we = cwfr3en & wren; assign cwprrwe = cwprren & wren; assign gapr0we = gapr0en & wren; assign gapr1we = gapr1en & wren; assign gapr2we = gapr2en & wren; assign gapr3we = gapr3en & wren; assign gapr4we = gapr4en & wren; assign gapr5we = gapr5en & wren; assign gapr6we = gapr6en & wren; assign gapr7we = gapr7en & wren; assign lcprwe = lcpren & wren; assign ampr0we = ampr0en & wren; assign ampr1we = ampr1en & wren; assign ampr2we = ampr2en & wren; assign ampr3we = ampr3en & wren; assign baisr0we = baisr0en & wren; assign baisr1we = baisr1en & wren; assign baisr2we = baisr2en & wren; assign baisr3we = baisr3en & wren; assign intpselrwe = intpselren & wren; // ------------------------------------------------------ // -- mcuresr0 register // // Write mcuresr0 for 'MCURESR0' : 32-bit register // Register is split into the following bit fields // // [31:0] --> mcuresr0 // ------------------------------------------------------ wire [31:0] mcuresr0_w; assign mcuresr0_w[31:24] = wrmask[3] ? wrdata[31:24] : mcuresr0[31:24]; assign mcuresr0_w[23:16] = wrmask[2] ? wrdata[23:16] : mcuresr0[23:16]; assign mcuresr0_w[15 :8] = wrmask[1] ? wrdata[15 :8] : mcuresr0[15 :8]; assign mcuresr0_w[7 :0] = wrmask[0] ? wrdata[7 :0] : mcuresr0[7 :0]; sirv_gnrl_dfflr #(32) mcuresr0_dfflr (mcuresr0we, mcuresr0_w[31:0], mcuresr0, clk, rst_n); // ------------------------------------------------------ // -- mcuresr1 register // // Write mcuresr1 for 'MCURESR1' : 32-bit register // Register is split into the following bit fields // // [31:0] --> mcuresr1 // ------------------------------------------------------ wire [31:0] mcuresr1_w; assign mcuresr1_w[31:24] = wrmask[3] ? wrdata[31:24] : mcuresr1[31:24]; assign mcuresr1_w[23:16] = wrmask[2] ? wrdata[23:16] : mcuresr1[23:16]; assign mcuresr1_w[15 :8] = wrmask[1] ? wrdata[15 :8] : mcuresr1[15 :8]; assign mcuresr1_w[7 :0] = wrmask[0] ? wrdata[7 :0] : mcuresr1[7 :0]; sirv_gnrl_dfflr #(32) mcuresr1_dfflr (mcuresr1we, mcuresr1_w[31:0], mcuresr1, clk, rst_n); // ------------------------------------------------------ // -- mcuresr2 register // // Write mcuresr2 for 'MCURESR2' : 32-bit register // Register is split into the following bit fields // // [31:0] --> mcuresr2 // ------------------------------------------------------ wire [31:0] mcuresr2_w; assign mcuresr2_w[31:24] = wrmask[3] ? wrdata[31:24] : mcuresr2[31:24]; assign mcuresr2_w[23:16] = wrmask[2] ? wrdata[23:16] : mcuresr2[23:16]; assign mcuresr2_w[15 :8] = wrmask[1] ? wrdata[15 :8] : mcuresr2[15 :8]; assign mcuresr2_w[7 :0] = wrmask[0] ? wrdata[7 :0] : mcuresr2[7 :0]; sirv_gnrl_dfflr #(32) mcuresr2_dfflr (mcuresr2we, mcuresr2_w[31:0], mcuresr2, clk, rst_n); // ------------------------------------------------------ // -- mcuresr3 register // // Write mcuresr3 for 'MCURESR3' : 32-bit register // Register is split into the following bit fields // // [31:0] --> mcuresr3 // ------------------------------------------------------ wire [31:0] mcuresr3_w; assign mcuresr3_w[31:24] = wrmask[3] ? wrdata[31:24] : mcuresr3[31:24]; assign mcuresr3_w[23:16] = wrmask[2] ? wrdata[23:16] : mcuresr3[23:16]; assign mcuresr3_w[15 :8] = wrmask[1] ? wrdata[15 :8] : mcuresr3[15 :8]; assign mcuresr3_w[7 :0] = wrmask[0] ? wrdata[7 :0] : mcuresr3[7 :0]; sirv_gnrl_dfflr #(32) mcuresr3_dfflr (mcuresr3we, mcuresr3_w[31:0], mcuresr3, clk, rst_n); // ------------------------------------------------------ // -- cwfr0 register // // Write cwfr0 for 'CWFR0' : 32-bit register // Register is split into the following bit fields // // [31:0] --> cwfr0 // ------------------------------------------------------ wire [31:0] cwfr0_w; assign cwfr0_w[31:24] = wrmask[3] ? wrdata[31:24] : cwfr0[31:24]; assign cwfr0_w[23:16] = wrmask[2] ? wrdata[23:16] : cwfr0[23:16]; assign cwfr0_w[15 :8] = wrmask[1] ? wrdata[15 :8] : cwfr0[15 :8]; assign cwfr0_w[7 :0] = wrmask[0] ? wrdata[7 :0] : cwfr0[7 :0]; sirv_gnrl_dfflr #(32) cwfr0_dfflr (cwfr0we, cwfr0_w[31:0], cwfr0, clk, rst_n); // ------------------------------------------------------ // -- cwfr1 register // // Write cwfr1 for 'CWFR1' : 32-bit register // Register is split into the following bit fields // // [31:16] --> cwfr1 // ------------------------------------------------------ wire [31:0] cwfr1_w; assign cwfr1_w[31:24] = wrmask[3] ? wrdata[31:24] : cwfr1[31:24]; assign cwfr1_w[23:16] = wrmask[2] ? wrdata[23:16] : cwfr1[23:16]; assign cwfr1_w[15 :8] = wrmask[1] ? wrdata[15 :8] : cwfr1[15 :8]; assign cwfr1_w[7 :0] = wrmask[0] ? wrdata[7 :0] : cwfr1[7 :0]; sirv_gnrl_dfflr #(32) cwfr1_dfflr (cwfr1we, cwfr1_w[31:0], cwfr1, clk, rst_n); // ------------------------------------------------------ // -- cwfr2 register // // Write cwfr2 for 'CWFR2' : 32-bit register // Register is split into the following bit fields // // [31:16] --> cwfr2 // ------------------------------------------------------ wire [31:0] cwfr2_w; assign cwfr2_w[31:24] = wrmask[3] ? wrdata[31:24] : cwfr2[31:24]; assign cwfr2_w[23:16] = wrmask[2] ? wrdata[23:16] : cwfr2[23:16]; assign cwfr2_w[15 :8] = wrmask[1] ? wrdata[15 :8] : cwfr2[15 :8]; assign cwfr2_w[7 :0] = wrmask[0] ? wrdata[7 :0] : cwfr2[7 :0]; sirv_gnrl_dfflr #(32) cwfr2_dfflr (cwfr2we, cwfr2_w[31:0], cwfr2, clk, rst_n); // ------------------------------------------------------ // -- cwfr3 register // // Write cwfr3 for 'CWFR3' : 32-bit register // Register is split into the following bit fields // // [31:16] --> cwfr3 // ------------------------------------------------------ wire [31:0] cwfr3_w; assign cwfr3_w[31:24] = wrmask[3] ? wrdata[31:24] : cwfr3[31:24]; assign cwfr3_w[23:16] = wrmask[2] ? wrdata[23:16] : cwfr3[23:16]; assign cwfr3_w[15 :8] = wrmask[1] ? wrdata[15 :8] : cwfr3[15 :8]; assign cwfr3_w[7 :0] = wrmask[0] ? wrdata[7 :0] : cwfr3[7 :0]; sirv_gnrl_dfflr #(32) cwfr3_dfflr (cwfr3we, cwfr3_w[31:0], cwfr3, clk, rst_n); // ------------------------------------------------------ // -- cwprr register(self-clearing) // // Write cwprr for 'CWPRR' : 32-bit register // Register is split into the following bit fields // // [0] --> cwprr // ------------------------------------------------------ wire cwprr_w = wrmask[0] & cwprrwe & wrdata[0]; sirv_gnrl_dffr #(1) cwprr_dffr (cwprr_w, cwprr, clk, rst_n); // ------------------------------------------------------ // -- gapr0 register // // Write gapr0 for 'GAPR0' : 32-bit register // Register is split into the following bit fields // // [31:16] --> gapr0 // ------------------------------------------------------ wire [31:0] gapr0_w; assign gapr0_w[31:24] = wrmask[3] ? wrdata[31:24] : gapr0[15: 8];/////////////////////////////////////////////////////////////31:26->15:8 assign gapr0_w[23:16] = wrmask[2] ? wrdata[23:16] : gapr0[ 7: 0];/////////////////////////////////////////////////////////////23:16->7:0 sirv_gnrl_dfflr #(16) gapr0_dfflr (gapr0we, gapr0_w[31:16], gapr0, clk, rst_n); // ------------------------------------------------------ // -- gapr1 register // // Write gapr1 for 'GAPR1' : 32-bit register // Register is split into the following bit fields // // [31:16] --> gapr1 // ------------------------------------------------------ wire [31:0] gapr1_w; assign gapr1_w[31:24] = wrmask[3] ? wrdata[31:24] : gapr1[15: 8];///////////////////////////////////////////////////////////// assign gapr1_w[23:16] = wrmask[2] ? wrdata[23:16] : gapr1[ 7: 0];///////////////////////////////////////////////////////////// sirv_gnrl_dfflr #(16) gapr1_dfflr (gapr1we, gapr1_w[31:16], gapr1, clk, rst_n); // ------------------------------------------------------ // -- gapr2 register // // Write gapr2 for 'GAPR2' : 32-bit register // Register is split into the following bit fields // // [31:16] --> gapr2 // ------------------------------------------------------ wire [31:0] gapr2_w; assign gapr2_w[31:24] = wrmask[3] ? wrdata[31:24] : gapr2[15: 8];///////////////////////////////////////////////////////////// assign gapr2_w[23:16] = wrmask[2] ? wrdata[23:16] : gapr2[ 7: 0];///////////////////////////////////////////////////////////// sirv_gnrl_dfflr #(16) gapr2_dfflr (gapr2we, gapr2_w[31:16], gapr2, clk, rst_n); // ------------------------------------------------------ // -- gapr3 register // // Write gapr3 for 'GAPR3' : 32-bit register // Register is split into the following bit fields // // [31:16] --> gapr3 // ------------------------------------------------------ wire [31:0] gapr3_w; assign gapr3_w[31:24] = wrmask[3] ? wrdata[31:24] : gapr3[15: 8];///////////////////////////////////////////////////////////// assign gapr3_w[23:16] = wrmask[2] ? wrdata[23:16] : gapr3[ 7: 0];///////////////////////////////////////////////////////////// sirv_gnrl_dfflr #(16) gapr3_dfflr (gapr3we, gapr3_w[31:16], gapr3, clk, rst_n); // ------------------------------------------------------ // -- gapr4 register // // Write gapr4 for 'GAPR4' : 32-bit register // Register is split into the following bit fields // // [31:16] --> gapr4 // ------------------------------------------------------ wire [31:0] gapr4_w; assign gapr4_w[31:24] = wrmask[3] ? wrdata[31:24] : gapr4[15: 8];///////////////////////////////////////////////////////////// assign gapr4_w[23:16] = wrmask[2] ? wrdata[23:16] : gapr4[ 7: 0];///////////////////////////////////////////////////////////// sirv_gnrl_dfflr #(16) gapr4_dfflr (gapr4we, gapr4_w[31:16], gapr4, clk, rst_n); // ------------------------------------------------------ // -- gapr5 register // // Write gapr5 for 'GAPR5' : 32-bit register // Register is split into the following bit fields // // [31:16] --> gapr5 // ------------------------------------------------------ wire [31:0] gapr5_w; assign gapr5_w[31:24] = wrmask[3] ? wrdata[31:24] : gapr5[15: 8];///////////////////////////////////////////////////////////// assign gapr5_w[23:16] = wrmask[2] ? wrdata[23:16] : gapr5[ 7: 0];///////////////////////////////////////////////////////////// sirv_gnrl_dfflr #(16) gapr5_dfflr (gapr5we, gapr5_w[31:16], gapr5, clk, rst_n); // ------------------------------------------------------ // -- gapr6 register // // Write gapr6 for 'GAPR6' : 32-bit register // Register is split into the following bit fields // // [31:16] --> gapr6 // ------------------------------------------------------ wire [31:0] gapr6_w; assign gapr6_w[31:24] = wrmask[3] ? wrdata[31:24] : gapr6[15: 8];///////////////////////////////////////////////////////////// assign gapr6_w[23:16] = wrmask[2] ? wrdata[23:16] : gapr6[ 7: 0];///////////////////////////////////////////////////////////// sirv_gnrl_dfflr #(16) gapr6_dfflr (gapr6we, gapr6_w[31:16], gapr6, clk, rst_n); // ------------------------------------------------------ // -- gapr7 register // // Write gapr7 for 'GAPR7' : 32-bit register // Register is split into the following bit fields // // [31:16] --> gapr7 // ------------------------------------------------------ wire [31:0] gapr7_w; assign gapr7_w[31:24] = wrmask[3] ? wrdata[31:24] : gapr7[15: 8];///////////////////////////////////////////////////////////// assign gapr7_w[23:16] = wrmask[2] ? wrdata[23:16] : gapr7[ 7: 0];///////////////////////////////////////////////////////////// sirv_gnrl_dfflr #(16) gapr7_dfflr (gapr7we, gapr7_w[31:16], gapr7, clk, rst_n); // ------------------------------------------------------ // -- lcpr register // // Write lcpr for 'LCPR' : 32-bit register // Register is split into the following bit fields // // [31:16] --> lcpr // ------------------------------------------------------ wire [31:0] lcpr_w; assign lcpr_w[31:24] = wrmask[3] ? wrdata[31:24] : lcpr[15: 8];///////////////////////////////////////////////////////////// assign lcpr_w[23:16] = wrmask[2] ? wrdata[23:16] : lcpr[ 7: 0];///////////////////////////////////////////////////////////// sirv_gnrl_dfflr #(16) lcpr_dfflr (lcprwe, lcpr_w[31:16], lcpr, clk, rst_n); // ------------------------------------------------------ // -- ampr0 register // // Write ampr0 for 'AMPR0' : 32-bit register // Register is split into the following bit fields // // [31:16] --> ampr0 // ------------------------------------------------------ wire [31:0] ampr0_w; assign ampr0_w[31:24] = wrmask[3] ? wrdata[31:24] : ampr0[15: 8];///////////////////////////////////////////////////////////// assign ampr0_w[23:16] = wrmask[2] ? wrdata[23:16] : ampr0[ 7: 0];///////////////////////////////////////////////////////////// sirv_gnrl_dfflr #(16) ampr0_dfflr (ampr0we, ampr0_w[31:16], ampr0, clk, rst_n); // ------------------------------------------------------ // -- ampr1 register // // Write ampr1 for 'AMPR10' : 32-bit register // Register is split into the following bit fields // // [31:16] --> ampr1 // ------------------------------------------------------ wire [31:0] ampr1_w; assign ampr1_w[31:24] = wrmask[3] ? wrdata[31:24] : ampr1[15: 8];///////////////////////////////////////////////////////////// assign ampr1_w[23:16] = wrmask[2] ? wrdata[23:16] : ampr1[ 7: 0];///////////////////////////////////////////////////////////// sirv_gnrl_dfflr #(16) ampr1_dfflr (ampr1we, ampr1_w[31:16], ampr1, clk, rst_n); // ------------------------------------------------------ // -- ampr2 register // // Write ampr2 for 'AMPR2' : 32-bit register // Register is split into the following bit fields // // [31:16] --> ampr2 // ------------------------------------------------------ wire [31:0] ampr2_w; assign ampr2_w[31:24] = wrmask[3] ? wrdata[31:24] : ampr2[15: 8];///////////////////////////////////////////////////////////// assign ampr2_w[23:16] = wrmask[2] ? wrdata[23:16] : ampr2[ 7: 0];///////////////////////////////////////////////////////////// sirv_gnrl_dfflr #(16) ampr2_dfflr (ampr2we, ampr2_w[31:16], ampr2, clk, rst_n); // ------------------------------------------------------ // -- ampr3 register // // Write ampr3 for 'AMPR3' : 32-bit register // Register is split into the following bit fields // // [31:16] --> ampr3 // ------------------------------------------------------ wire [31:0] ampr3_w; assign ampr3_w[31:24] = wrmask[3] ? wrdata[31:24] : ampr3[15: 8];///////////////////////////////////////////////////////////// assign ampr3_w[23:16] = wrmask[2] ? wrdata[23:16] : ampr3[ 7: 0];///////////////////////////////////////////////////////////// sirv_gnrl_dfflr #(16) ampr3_dfflr (ampr3we, ampr3_w[31:16], ampr3, clk, rst_n); // ------------------------------------------------------ // -- baisr0 register // // Write baisr0 for 'BIASR0' : 32-bit register // Register is split into the following bit fields // // [31:16] --> baisr0 // ------------------------------------------------------ wire [31:0] baisr0_w; assign baisr0_w[31:24] = wrmask[3] ? wrdata[31:24] : baisr0[15: 8];///////////////////////////////////////////////////////////// assign baisr0_w[23:16] = wrmask[2] ? wrdata[23:16] : baisr0[ 7: 0];///////////////////////////////////////////////////////////// sirv_gnrl_dfflr #(16) baisr0_dfflr (baisr0we, baisr0_w[31:16], baisr0, clk, rst_n); // ------------------------------------------------------ // -- baisr1 register // // Write baisr1 for 'BIASR1' : 32-bit register // Register is split into the following bit fields // // [31:16] --> baisr1 // ------------------------------------------------------ wire [31:0] baisr1_w; assign baisr1_w[31:24] = wrmask[3] ? wrdata[31:24] : baisr1[15: 8];///////////////////////////////////////////////////////////// assign baisr1_w[23:16] = wrmask[2] ? wrdata[23:16] : baisr1[ 7: 0];///////////////////////////////////////////////////////////// sirv_gnrl_dfflr #(16) baisr1_dfflr (baisr1we, baisr1_w[31:16], baisr1, clk, rst_n); // ------------------------------------------------------ // -- baisr2 register // // Write baisr2 for 'BIASR2' : 32-bit register // Register is split into the following bit fields // // [31:16] --> baisr2 // ------------------------------------------------------ wire [31:0] baisr2_w; assign baisr2_w[31:24] = wrmask[3] ? wrdata[31:24] : baisr2[15: 8];///////////////////////////////////////////////////////////// assign baisr2_w[23:16] = wrmask[2] ? wrdata[23:16] : baisr2[ 7: 0];///////////////////////////////////////////////////////////// sirv_gnrl_dfflr #(16) baisr2_dfflr (baisr2we, baisr2_w[31:16], baisr2, clk, rst_n); // ------------------------------------------------------ // -- baisr3 register // // Write baisr3 for 'BIASR3' : 32-bit register // Register is split into the following bit fields // // [31:16] --> baisr3 // ------------------------------------------------------ wire [31:0] baisr3_w; assign baisr3_w[31:24] = wrmask[3] ? wrdata[31:24] : baisr3[15: 8];///////////////////////////////////////////////////////////// assign baisr3_w[23:16] = wrmask[2] ? wrdata[23:16] : baisr3[ 7: 0];///////////////////////////////////////////////////////////// sirv_gnrl_dfflr #(16) baisr3_dfflr (baisr3we, baisr3_w[31:16], baisr3, clk, rst_n); // ------------------------------------------------------ // -- intpselr register // // Write intpselr for 'INTPSELR' : 32-bit register // Register is split into the following bit fields // // [1:0] --> intpselr // ------------------------------------------------------ wire [1:0] intpselr_w; assign intpselr_w[1:0] = wrmask[0] ? wrdata[1:0] : intpselr[1:0]; sirv_gnrl_dfflr #(2) intpselr_dfflr (intpselrwe, intpselr_w[1:0], intpselr, clk, rst_n); // ------------------------------------------------------ // -- mcuparar0 // ------------------------------------------------------ sirv_gnrl_dffr #(32) mcuparar0_dffr (mcu_param[0], mcuparar0, clk, rst_n); // ------------------------------------------------------ // -- mcuparar1 // ------------------------------------------------------ sirv_gnrl_dffr #(32) mcuparar1_dffr (mcu_param[1], mcuparar1, clk, rst_n); // ------------------------------------------------------ // -- mcuparar2 // ------------------------------------------------------ sirv_gnrl_dffr #(32) mcuparar2_dffr (mcu_param[2], mcuparar2, clk, rst_n); // ------------------------------------------------------ // -- mcuparar3 // ------------------------------------------------------ sirv_gnrl_dffr #(32) mcuparar3_dffr (mcu_param[3], mcuparar3, clk, rst_n); // ------------------------------------------------------ // -- rtimr // ------------------------------------------------------ sirv_gnrl_dffr #(32) rtimr_dffr (run_time, rtimr, clk, rst_n); // ------------------------------------------------------ // -- icntr // ------------------------------------------------------ sirv_gnrl_dffr #(32) icntr_dffr (instr_num, icntr, clk, rst_n); // ------------------------------------------------------ // -- fsir // ------------------------------------------------------ sirv_gnrl_dffr #(2) fsir_dffr (fb_st_info[1:0], fsir, clk, rst_n);////////////////////////////////////////////[1:0] // ------------------------------------------------------ // -- Read data mux // // -- The data from the selected register is // -- placed on a zero-padded 32-bit read data bus. // ------------------------------------------------------ always @(*) begin : RDDATA_PROC rddata_reg = {32{1'b0}}; if(mcuparar0en == H ) rddata_reg[31:0] = mcuparar0 ; if(mcuparar1en == H ) rddata_reg[31:0] = mcuparar1 ; if(mcuparar2en == H ) rddata_reg[31:0] = mcuparar2 ; if(mcuparar3en == H ) rddata_reg[31:0] = mcuparar3 ; if(mcuresr0en == H ) rddata_reg[31:0] = mcuresr0 ; if(mcuresr1en == H ) rddata_reg[31:0] = mcuresr1 ; if(mcuresr2en == H ) rddata_reg[31:0] = mcuresr2 ; if(mcuresr3en == H ) rddata_reg[31:0] = mcuresr3 ; if(cwfr0en == H ) rddata_reg[31:0] = cwfr0 ; if(cwfr1en == H ) rddata_reg[31:0] = cwfr1 ; if(cwfr2en == H ) rddata_reg[31:0] = cwfr2 ; if(cwfr3en == H ) rddata_reg[31:0] = cwfr3 ; if(cwprren == H ) rddata_reg[0 :0] = cwprr ; if(gapr0en == H ) rddata_reg[15:0] = gapr0 ; if(gapr1en == H ) rddata_reg[15:0] = gapr1 ; if(gapr2en == H ) rddata_reg[15:0] = gapr2 ; if(gapr3en == H ) rddata_reg[15:0] = gapr3 ; if(gapr4en == H ) rddata_reg[15:0] = gapr4 ; if(gapr5en == H ) rddata_reg[15:0] = gapr5 ; if(gapr6en == H ) rddata_reg[15:0] = gapr6 ; if(gapr7en == H ) rddata_reg[15:0] = gapr7 ; if(lcpren == H ) rddata_reg[15:0] = lcpr ; if(ampr0en == H ) rddata_reg[15:0] = ampr0 ; if(ampr1en == H ) rddata_reg[15:0] = ampr1 ; if(ampr2en == H ) rddata_reg[15:0] = ampr2 ; if(ampr3en == H ) rddata_reg[15:0] = ampr3 ; if(baisr0en == H ) rddata_reg[15:0] = baisr0 ; if(baisr1en == H ) rddata_reg[15:0] = baisr1 ; if(baisr2en == H ) rddata_reg[15:0] = baisr2 ; if(baisr3en == H ) rddata_reg[15:0] = baisr3 ; if(rtimren == H ) rddata_reg[31:0] = rtimr ; if(icntren == H ) rddata_reg[31:0] = icntr ; if(fsiren == H ) rddata_reg[1 :0] = fsir ; if(intpselren == H ) rddata_reg[1 :0] = intpselr ;//////////////////////////////////////////////////////////// end // ------------------------------------------------------ // -- Output signals assignment // ------------------------------------------------------ //mcu result assign mcu_result[0] = mcuresr0 ; assign mcu_result[1] = mcuresr1 ; assign mcu_result[2] = mcuresr2 ; assign mcu_result[3] = mcuresr3 ; //nco_fwc lookup table output assign mcu_cwfr[0] = cwfr0; assign mcu_cwfr[1] = cwfr1; assign mcu_cwfr[2] = cwfr2; assign mcu_cwfr[3] = cwfr3; //nco_pha lookup table output assign mcu_gapr[0] = gapr0; ////////////////////////////////////////////////16bit assign to 32bit(?) assign mcu_gapr[1] = gapr1; assign mcu_gapr[2] = gapr2; assign mcu_gapr[3] = gapr3; assign mcu_gapr[4] = gapr4; assign mcu_gapr[5] = gapr5; assign mcu_gapr[6] = gapr6; assign mcu_gapr[7] = gapr7; //amp lookup table output assign mcu_ampr[0] = ampr0; assign mcu_ampr[1] = ampr1; assign mcu_ampr[2] = ampr2; assign mcu_ampr[3] = ampr3; //bais lookup table output assign mcu_baisr[0] = baisr0; assign mcu_baisr[1] = baisr1; assign mcu_baisr[2] = baisr2; assign mcu_baisr[3] = baisr3; //CFG Port assign mcu_nco_pha_clr = cwprr; assign mcu_rz_pha = lcpr; assign mcu_intp_sel = intpselr; //rddata //assign rddata = rddata_reg ; sirv_gnrl_dffr #(32) rddata_dffr (rddata_reg, rddata, clk, rst_n);//////////////////////// endmodule `undef MCUPARAR0 `undef MCUPARAR1 `undef MCUPARAR2 `undef MCUPARAR3 `undef MCURESR0 `undef MCURESR1 `undef MCURESR2 `undef MCURESR3 `undef CWFR0 `undef CWFR1 `undef CWFR2 `undef CWFR3 `undef CWPRR `undef GAPR0 `undef GAPR1 `undef GAPR2 `undef GAPR3 `undef GAPR4 `undef GAPR5 `undef GAPR6 `undef GAPR7 `undef LCPR `undef AMPR0 `undef AMPR1 `undef AMPR2 `undef AMPR3 `undef BIASR0 `undef BIASR1 `undef BIASR2 `undef BIASR3 `undef RTIMR `undef ICNTR `undef FSIR