//+FHDR--------------------------------------------------------------------------------------------------------
//  Company: 
//-----------------------------------------------------------------------------------------------------------------
//  File Name             :    v.v
//  Department            :    
//  Author                :    PWY
//  Author's Tel          :     
//-----------------------------------------------------------------------------------------------------------------
//  Relese History
//  Version     Date            Author          Description
//  0.1         2024-03-13      PWY             AWG output data bais set
//-----------------------------------------------------------------------------------------------------------------
//  Keywords            :       
//
//-----------------------------------------------------------------------------------------------------------------
//  Parameter
//
//-----------------------------------------------------------------------------------------------------------------
//  Purpose                 :
//                      
//-----------------------------------------------------------------------------------------------------------------
//  Target Device:        
//  Tool versions:        
//-----------------------------------------------------------------------------------------------------------------
//  Reuse Issues
//  Reset Strategy: 
//  Clock Domains: 
//  Critical Timing:
//  Asynchronous I/F:
//  Synthesizable (y/n): 
//  Other:
//-FHDR--------------------------------------------------------------------------------------------------------

module baisset (
  //System Signal
   input         Dig_Clk              //Module Clock
  ,input         Dig_Resetn           //Module Reset Signal
  //FM Data_in
  ,input  [15:0] Bais_Data_I_i          //Bais_data_I
  ,input  [15:0] Bais_Data_Q_i          //Bais_data_Q
  ,input         Bais_Vld_i             //Bais_data is valid
  //AM 
  ,input  [15:0] Bais    	         //Bais
  ,input         Bais_Enable  	     //1'b0: disable Bais,1'b1:enable Bais
  //Output Bais data 
  ,output [15:0] Bais_Data_I_o         //Bais output data for I
  ,output [15:0] Bais_Data_Q_o         //Bais output data for Q
  ,output        Bais_Vld_o            //Bais output data vld 
  ,output        Bais_I_Ov
  ,output        Bais_Q_Ov
);

wire [17:0] temp_data_i =  Bais_Enable ? {{2{Bais_Data_I_i[15]}},Bais_Data_I_i} + {{2{Bais[15]}},Bais} : {{2{Bais_Data_I_i[15]}},Bais_Data_I_i};
wire [17:0] temp_data_q =  Bais_Enable ? {{2{Bais_Data_Q_i[15]}},Bais_Data_Q_i} + {{2{Bais[15]}},Bais} : {{2{Bais_Data_Q_i[15]}},Bais_Data_Q_i};

//output data
sirv_gnrl_dffr #(16) Bais_Data_I_o_dffr (temp_data_i[15:0], Bais_Data_I_o, Dig_Clk, Dig_Resetn);
sirv_gnrl_dffr #(16) Bais_Data_Q_o_dffr (temp_data_q[15:0], Bais_Data_Q_o, Dig_Clk, Dig_Resetn);

//output vld
sirv_gnrl_dffr #(1) Bais_Vld_o_dffr (Bais_Vld_i, Bais_Vld_o, Dig_Clk, Dig_Resetn);

//output overflow flag
sirv_gnrl_dfflr #(1) Bais_I_Ov_dfflr (Bais_Vld_i, temp_data_i[17] ^ temp_data_i[16], Bais_I_Ov, Dig_Clk, Dig_Resetn);
sirv_gnrl_dfflr #(1) Bais_Q_Ov_dfflr (Bais_Vld_i, temp_data_q[17] ^ temp_data_q[16], Bais_Q_Ov, Dig_Clk, Dig_Resetn);

endmodule