//  Relese History
//  Version     Date            Author          Description
//  1.2         2024-06-01        ZYZ
//-----------------------------------------------------------------------------------------------------------------
//  Keywords            :   1.add Env_vld 
// 			    2.add Mod_vld  
//		            3.change the use of Mod_enable 
//			    4.divide modem into FM and AM		
//			    5.change amp : unsigned [16:0]Amp to signed [15:0]Amp
// 			             
//						   
//					   
//-----------------------------------------------------------------------------------------------------------------
//  Parameter
//
//-----------------------------------------------------------------------------------------------------------------
//  Purpose                 :
//                      
//-----------------------------------------------------------------------------------------------------------------
//  Target Device:        
//  Tool versions:        
//-----------------------------------------------------------------------------------------------------------------
//  Reuse Issues
//  Reset Strategy: 
//  Clock Domains: 
//  Critical Timing:
//  Asynchronous I/F:
//  Synthesizable (y/n): 
//  Other:
//-FHDR--------------------------------------------------------------------------------------------------------
module ampmod (
  //System Signal
   input         Dig_Clk            //Module Clock
  ,input         Dig_Resetn         //Module Reset Signal
  //FM Data_in
  ,input  [15:0] Mod_Data_I          //FM_data_I
  ,input  [15:0] Mod_Data_Q          //FM_data_Q
  ,input         Mod_Vld             //FM_data is valid
  //AM 
  ,input  [15:0] Amp    	     //amplitude
  ,input         Amod_Enable  	     //1'b0: disable modem,1'b1:enable modem
  //Output modem data 
  ,output [15:0] Amod_Data_I         //Modem output data for I
  ,output [15:0] Amod_Data_Q         //Modem output data for Q
  ,output        Amod_Vld            //Modem output data vld 
);
//FM_data
wire [15:0] Mod_Data_I_w;
wire [15:0] Mod_Data_Q_w;

//The temporary result Regs of a multiplication operation.
wire [31:0] I_Amp_tmp;
wire [31:0] Q_Amp_tmp;

//Output of IQ data stored in registers.
reg [15:0] I_Amp_tmp_r;
reg [15:0] Q_Amp_tmp_r;

//AM_vld delay
reg [2:0]  ampmod_data_vld_dly;


assign Mod_Data_I_w = Amod_Enable ? Mod_Data_I : 16'b0;
assign Mod_Data_Q_w = Amod_Enable ? Mod_Data_Q : 16'b0;

////////////////////////////////////
DW_mult_pipe       #(
   .a_width         ( 16            )
  ,.b_width         ( 16            )
  ,.num_stages      ( 3             )
  ,.stall_mode      ( 0             )
  ,.rst_mode        ( 1             ) 
  ,.op_iso_mode     ( 0             ) 
  ) inst_I_Amp      ( 
   .clk             ( Dig_Clk       )
  ,.rst_n           ( Dig_Resetn    )
  ,.en              ( 1'b1          )
  ,.a               ( Mod_Data_I_w  )
  ,.b               (   Amp   	    )
  ,.tc              ( 1'b1          )
  ,.product         ( I_Amp_tmp     )
  );

DW_mult_pipe       #(
   .a_width         ( 16            )
  ,.b_width         ( 16            )
  ,.num_stages      ( 3             )
  ,.stall_mode      ( 0             )
  ,.rst_mode        ( 1             ) 
  ,.op_iso_mode     ( 0             ) 
  ) inst_Q_Amp      ( 
   .clk             ( Dig_Clk       )
  ,.rst_n           ( Dig_Resetn    )
  ,.en              ( 1'b1   	    )
  ,.a               ( Mod_Data_Q_w  )
  ,.b               ( Amp    	    )
  ,.tc              ( 1'b1          )
  ,.product         ( Q_Amp_tmp     )
  );

always@(posedge Dig_Clk or negedge Dig_Resetn)begin
  if(Dig_Resetn == 1'b0) begin
    I_Amp_tmp_r <= 16'b0;
  end
  else if (I_Amp_tmp[31:30] == 2'b01)begin
    I_Amp_tmp_r <= 16'd32767;
  end 
  else if(I_Amp_tmp[31:30] == 2'b10)begin
    I_Amp_tmp_r <= -16'd32768;
  end
  else begin
    I_Amp_tmp_r <= {I_Amp_tmp[31],I_Amp_tmp[29:15]} + I_Amp_tmp[14];
  end
end

always@(posedge Dig_Clk or negedge Dig_Resetn)begin
  if(Dig_Resetn == 1'b0) begin
    Q_Amp_tmp_r <= 16'd0;
  end
  else if (Q_Amp_tmp[31:30] == 2'b01)begin
    Q_Amp_tmp_r <= 16'd32767;
  end 
  else if(I_Amp_tmp[31:30] == 2'b10)begin
    Q_Amp_tmp_r <= -16'd32768;
  end
  else begin
    Q_Amp_tmp_r <= {Q_Amp_tmp[31],Q_Amp_tmp[29:15]} + Q_Amp_tmp[14];
  end
end

assign Amod_Data_I = I_Amp_tmp_r;
assign Amod_Data_Q = Q_Amp_tmp_r;

//ampmod_data_vld_dly
always @(posedge Dig_Clk or negedge Dig_Resetn) begin
  if(Dig_Resetn == 1'b0) begin
    ampmod_data_vld_dly <= 3'b0;
  end
  else begin
    ampmod_data_vld_dly <= {ampmod_data_vld_dly[2:0], Amod_Enable & Mod_Vld};
  end
end 

assign Amod_Vld = ampmod_data_vld_dly[2];

endmodule