//+FHDR--------------------------------------------------------------------------------------------------------
//  Company: 
//-----------------------------------------------------------------------------------------------------------------
//  File Name             :    ssram_model.v
//  Department            :    
//  Author                :    PWY
//  Author's Tel          :     
//-----------------------------------------------------------------------------------------------------------------
//  Relese History
//  Version     Date            Author          Description
//  1.0         2022-08-25      PWY
//-----------------------------------------------------------------------------------------------------------------
//  Keywords            :       
//
//-----------------------------------------------------------------------------------------------------------------
//  Parameter
//
//-----------------------------------------------------------------------------------------------------------------
//  Purpose                 :
//                      
//-----------------------------------------------------------------------------------------------------------------
//  Target Device:        
//  Tool versions:        
//-----------------------------------------------------------------------------------------------------------------
//  Reuse Issues
//  Reset Strategy: 
//  Clock Domains: 
//  Critical Timing:
//  Asynchronous I/F:
//  Synthesizable (y/n): 
//  Other:
//-FHDR--------------------------------------------------------------------------------------------------------

module dpram_model #(
   parameter  DATAWIDTH = 32
  ,parameter  ADDRWIDTH = 13
)(
   input                          PortClk
  ,input      [(ADDRWIDTH-1)  :0] PortAAddr
  ,input      [(DATAWIDTH-1)  :0] PortADataIn
  ,input                          PortAWriteEnable
  ,input                          PortAChipEnable       //active low
  ,input      [(DATAWIDTH/8)-1:0] PortAByteWriteEnable
  ,output reg [(DATAWIDTH-1)  :0] PortADataOut
  
  ,input      [(ADDRWIDTH-1)  :0] PortBAddr
  ,input      [(DATAWIDTH-1)  :0] PortBDataIn
  ,input                          PortBWriteEnable
  ,input                          PortBChipEnable       //active low
  ,input      [(DATAWIDTH/8)-1:0] PortBByteWriteEnable
  ,output reg [(DATAWIDTH-1)  :0] PortBDataOut
);



////////////////////////////////////////////////////////////////////////////////
//Function
////////////////////////////////////////////////////////////////////////////////  	
function integer clog2(input integer bit_depth);
  begin
    for(clog2=0;bit_depth>0;clog2=clog2+1)
      bit_depth =bit_depth>>1;
  end
endfunction

localparam LSB  = clog2(DATAWIDTH/8 -1);

localparam NUM      = DATAWIDTH/8;

localparam MEMDEPTH = 2**(ADDRWIDTH-LSB);

generate
  genvar i;
  for(i=0;i<NUM;i=i+1) begin :dpram_model
    reg [7:0] mem [(MEMDEPTH-1):0] /* synthesis syn_ramstyle = "no_rw_check" */;
    always @(posedge PortClk) begin
      if(!PortAWriteEnable && !PortAByteWriteEnable[i] && !PortAChipEnable) begin
        mem[PortAAddr]               <= PortADataIn[8*(i+1)-1-:8];
        //PortADataOut[8*(i+1)-1-:8]    <= PortADataIn[8*(i+1)-1-:8];
      end
    end
	
	always @(posedge PortClk) begin
	  if(!PortBWriteEnable && !PortBByteWriteEnable[i] && !PortBChipEnable) begin
        mem[PortBAddr]               <= PortBDataIn[8*(i+1)-1-:8];
        //PortADataOut[8*(i+1)-1-:8]    <= PortADataIn[8*(i+1)-1-:8];
      end
    end
	
	always @(posedge PortClk) begin
	  PortADataOut[8*(i+1)-1-:8]    <= mem[PortAAddr[ADDRWIDTH-1:0]];
    end
  
    always @(posedge PortClk) begin
	  PortBDataOut[8*(i+1)-1-:8]    <= mem[PortBAddr[ADDRWIDTH-1:0]];
    end
  end
  
endgenerate
endmodule