//+FHDR-------------------------------------------------------------------------------------------------------- // Company: //----------------------------------------------------------------------------------------------------------------- // File Name : iopad.v // Department : // Author : pwy // Author's Tel : //----------------------------------------------------------------------------------------------------------------- // Relese History // Version Date Author Description // 1.2 2024-06-12 pwy Integrate a digital module and two SPI modules with PLL //----------------------------------------------------------------------------------------------------------------- // Keywords : // //----------------------------------------------------------------------------------------------------------------- // Parameter // //----------------------------------------------------------------------------------------------------------------- // Purpose : // //----------------------------------------------------------------------------------------------------------------- // Target Device: // Tool versions: //----------------------------------------------------------------------------------------------------------------- // Reuse Issues // Reset Strategy: // Clock Domains: // Critical Timing: // Asynchronous I/F: // Synthesizable (y/n): // Other: //-FHDR-------------------------------------------------------------------------------------------------------- `include "../define/chip_define.v" module iopad ( //+++++++++++++++++++++++++++++++++++++++++++++// // PAD Strat // //+++++++++++++++++++++++++++++++++++++++++++++// input PI_async_rstn // hardware Reset, active low //sync ,input PI_sync_in // Chip synchronization signal input, high pulse valid ,output PO_sync_out // Chip synchronization signal output, high pulse valid //Feedback signal ,input [1 :0] PI_ch0_feedback // Ch0 Feedback signals from the readout chip `ifdef CHANNEL_IS_FOUR ,input [1 :0] PI_ch1_feedback // Ch1 Feedback signals from the readout chip ,input [1 :0] PI_ch2_feedback // Ch2 Feedback signals from the readout chip ,input [1 :0] PI_ch3_feedback // Ch3 Feedback signals from the readout chip `endif //config chip id ,input [4 :0] PI_cfgid // During power-on initialization, the IO configuration // values are read as the chip ID number //spi port ,input PI_sclk // Spi Clock ,input PI_csn // Spi Chip Select active low ,input PI_mosi // Spi Mosi ,output PO_miso // Spi Miso //irq ,output PO_irq // Interrupt signal in the chip, high level active //+++++++++++++++++++++++++++++++++++++++++++++// // PAD End // //+++++++++++++++++++++++++++++++++++++++++++++// //+++++++++++++++++++++++++++++++++++++++++++++// // Internal signal Start // //+++++++++++++++++++++++++++++++++++++++++++++// ,output async_rstn // hardware Reset, active low //sync ,output sync_in // Chip synchronization signal input, high pulse valid ,input sync_out // Chip synchronization signal output, high pulse valid //Feedback signal ,output [1 :0] ch0_feedback // Ch0 Feedback signals from the readout chip `ifdef CHANNEL_IS_FOUR ,output [1 :0] ch1_feedback // Ch1 Feedback signals from the readout chip ,output [1 :0] ch2_feedback // Ch2 Feedback signals from the readout chip ,output [1 :0] ch3_feedback // Ch3 Feedback signals from the readout chip `endif //config chip id ,output [4 :0] cfgid // During power-on initialization, the IO configuration // values are read as the chip ID number //spi port ,output sclk // Spi Clock ,output csn // Spi Chip Select active low ,output mosi // Spi Mosi ,input miso // Spi Miso ,input oen // Spi Miso output enable //irq ,input irq // Interrupt signal in the chip, high level active ); `ifdef TSMC_IC //++++++++++++++++++++++++++++++++++++++++++++++++++// // ASIC PAD --> TSMC // //++++++++++++++++++++++++++++++++++++++++++++++++++// //PI_async_rstn PDUW04SDGZ_V_G PDUW08SDGZ_V_G_async_rstn ( .I ( 1'b0 ) ,.OEN ( 1'b1 ) ,.REN ( 1'b0 ) ,.PAD ( PI_async_rstn ) ,.C ( async_rstn ) ); //sync_in PDDW04SDGZ_V_G PDDW04SDGZ_V_G_sync_in ( .I ( 1'b0 ) ,.OEN ( 1'b1 ) ,.REN ( 1'b0 ) ,.PAD ( PI_sync_in ) ,.C ( sync_in ) ); //sync_out PDDW04SDGZ_V_G PDDW08SDGZ_V_G_sync_out ( .I ( sync_out ) ,.OEN ( 1'b0 ) ,.REN ( 1'b0 ) ,.PAD ( PO_sync_out ) ,.C ( ) ); //ch0_feedback PDDW04SDGZ_V_G PDDW04SDGZ_V_G_ch0_feedback0 ( .I ( 1'b0 ) ,.OEN ( 1'b1 ) ,.REN ( 1'b0 ) ,.PAD ( PI_ch0_feedback[0] ) ,.C ( ch0_feedback[0] ) ); PDDW04SDGZ_V_G PDDW04SDGZ_V_G_ch0_feedback1 ( .I ( 1'b0 ) ,.OEN ( 1'b1 ) ,.REN ( 1'b0 ) ,.PAD ( PI_ch0_feedback[1] ) ,.C ( ch0_feedback[1] ) ); //cfgid PDDW04SDGZ_V_G PDDW04DGZ_V_G_cfgid0 ( .I ( 1'b0 ) ,.OEN ( 1'b1 ) ,.REN ( 1'b0 ) ,.PAD ( PI_cfgid[0] ) ,.C ( cfgid[0] ) ); PDDW04SDGZ_V_G PDDW04DGZ_V_G_cfgid1 ( .I ( 1'b0 ) ,.OEN ( 1'b1 ) ,.REN ( 1'b0 ) ,.PAD ( PI_cfgid[1] ) ,.C ( cfgid[1] ) ); PDDW04SDGZ_V_G PDDW04DGZ_V_G_cfgid2 ( .I ( 1'b0 ) ,.OEN ( 1'b1 ) ,.REN ( 1'b0 ) ,.PAD ( PI_cfgid[2] ) ,.C ( cfgid[2] ) ); PDDW04SDGZ_V_G PDDW04DGZ_V_G_cfgid3 ( .I ( 1'b0 ) ,.OEN ( 1'b1 ) ,.REN ( 1'b0 ) ,.PAD ( PI_cfgid[3] ) ,.C ( cfgid[3] ) ); PDDW04SDGZ_V_G PDDW04DGZ_V_G_cfgid4 ( .I ( 1'b0 ) ,.OEN ( 1'b1 ) ,.REN ( 1'b0 ) ,.PAD ( PI_cfgid[4] ) ,.C ( cfgid[4] ) ); //sclk PDUW04SDGZ_V_G PDUW04SDGZ_V_G_sclk ( .I ( 1'b0 ) ,.OEN ( 1'b1 ) ,.REN ( 1'b0 ) ,.PAD ( PI_sclk ) ,.C ( sclk ) ); //csn PDUW04SDGZ_V_G PDUW04SDGZ_V_G_csn ( .I ( 1'b0 ) ,.OEN ( 1'b1 ) ,.REN ( 1'b0 ) ,.PAD ( PI_csn ) ,.C ( csn ) ); //mosi PDDW08SDGZ_V_G PDUW08SDGZ_V_G_mosi ( .I ( 1'b0 ) ,.OEN ( 1'b1 ) ,.REN ( 1'b0 ) ,.PAD ( PI_mosi ) ,.C ( mosi ) ); //miso PDUW08SDGZ_V_G PDUW08SDGZ_V_G_miso ( .I ( miso ) ,.OEN ( oen ) ,.REN ( 1'b0 ) ,.PAD ( PO_miso ) ,.C ( ) ); //irq PDDW08SDGZ_V_G PDDW08SDGZ_V_G_irq ( .I ( irq ) ,.OEN ( 1'b0 ) ,.REN ( 1'b0 ) ,.PAD ( PO_irq ) ,.C ( ) ); `elsif XILINX_FPGA //++++++++++++++++++++++++++++++++++++++++++++++++++// // FPGA PAD --> Xlinx // //++++++++++++++++++++++++++++++++++++++++++++++++++// //async_rstn assign async_rstn = PI_async_rstn ; //sync_in assign sync_in = PI_sync_in ; //sync_out assign PO_sync_out = sync_out ; //Feedback signal assign ch0_feedback = PI_ch0_feedback ; `ifdef CHANNEL_IS_FOUR assign ch1_feedback = PI_ch1_feedback ; assign ch2_feedback = PI_ch2_feedback ; assign ch3_feedback = PI_ch3_feedback ; `endif //config chip id assign cfgid = PI_cfgid ; //spi port assign sclk = PI_sclk ; assign csn = PI_csn ; assign mosi = PI_mosi ; assign PO_miso = oen ? 1'bz : miso ; //irq assign PO_irq = irq ; `endif endmodule `include "../define/chip_undefine.v"