//+FHDR-------------------------------------------------------------------------------------------------------- // Company: //----------------------------------------------------------------------------------------------------------------- // File Name : debug_top.v // Department : // Author : PWY // Author's Tel : //----------------------------------------------------------------------------------------------------------------- // Relese History // Version Date Author Description // 0.1 2024-04-13 PWY debug top-level // 0.2 2024-06-20 PWY dbg_sramb_wben = dbg_sram_out.wben -> dbg_sramb_wben = ~dbg_sram_out.wben //----------------------------------------------------------------------------------------------------------------- // Keywords : // //----------------------------------------------------------------------------------------------------------------- // Parameter // //----------------------------------------------------------------------------------------------------------------- // Purpose : // //----------------------------------------------------------------------------------------------------------------- // Target Device: // Tool versions: //----------------------------------------------------------------------------------------------------------------- // Reuse Issues // Reset Strategy: // Clock Domains: // Critical Timing: // Asynchronous I/F: // Synthesizable (y/n): // Other: //-FHDR-------------------------------------------------------------------------------------------------------- module debug_top ( //system port input clk // System Main Clock ,input rst_n // Spi Reset active low //---------------from ctrl regfile------------------------------------ ,input debug_enable //active high ,input debug_data_sel //1'b0-->mod;1'b1-->dsp ,input [3 :0] debug_ch_sel //2'b00-->ch0;2'b01-->ch1;2'b10-->ch2;2'b11-->ch3; //---------------to system regfile------------------------------------ ,output debug_update //active high //---------------connect mod------------------------------------------ ,input [15 :0] ch0_mod_data_i ,input [15 :0] ch0_mod_data_q ,input ch0_mod_vld ,input [15 :0] ch1_mod_data_i ,input [15 :0] ch1_mod_data_q ,input ch1_mod_vld ,input [15 :0] ch2_mod_data_i ,input [15 :0] ch2_mod_data_q ,input ch2_mod_vld ,input [15 :0] ch3_mod_data_i ,input [15 :0] ch3_mod_data_q ,input ch3_mod_vld //---------------connect mod------------------------------------------ ,input [15 :0] ch0_dsp_data [15:0] ,input ch0_dsp_vld ,input [15 :0] ch1_dsp_data [15:0] ,input ch1_dsp_vld ,input [15 :0] ch2_dsp_data [15:0] ,input ch2_dsp_vld ,input [15 :0] ch3_dsp_data [15:0] ,input ch3_dsp_vld //---------------connect SPI bus -------------------------------------- ,sram_if.slave dbg_sram_in ); //--------------------------------------------------------------------------------------------- //debug sampling //--------------------------------------------------------------------------------------------- wire [11 :0] debug_rwaddr ; wire [255:0] debug_wrdata ; wire [31 :0] debug_bwen ; wire debug_wren ; wire debug_cen ; debug_sampling U_debug_sampling ( .clk ( clk ) ,.rst_n ( rst_n ) ,.debug_enable ( debug_enable ) ,.debug_data_sel ( debug_data_sel ) ,.debug_ch_sel ( debug_ch_sel ) ,.debug_update ( debug_update ) ,.ch0_mod_data_i ( ch0_mod_data_i ) ,.ch0_mod_data_q ( ch0_mod_data_q ) ,.ch0_mod_vld ( ch0_mod_vld ) ,.ch1_mod_data_i ( ch1_mod_data_i ) ,.ch1_mod_data_q ( ch1_mod_data_q ) ,.ch1_mod_vld ( ch1_mod_vld ) ,.ch2_mod_data_i ( ch2_mod_data_i ) ,.ch2_mod_data_q ( ch2_mod_data_q ) ,.ch2_mod_vld ( ch2_mod_vld ) ,.ch3_mod_data_i ( ch3_mod_data_i ) ,.ch3_mod_data_q ( ch3_mod_data_q ) ,.ch3_mod_vld ( ch3_mod_vld ) ,.ch0_dsp_data ( ch0_dsp_data ) ,.ch0_dsp_vld ( ch0_dsp_vld ) ,.ch1_dsp_data ( ch1_dsp_data ) ,.ch1_dsp_vld ( ch1_dsp_vld ) ,.ch2_dsp_data ( ch2_dsp_data ) ,.ch2_dsp_vld ( ch2_dsp_vld ) ,.ch3_dsp_data ( ch3_dsp_data ) ,.ch3_dsp_vld ( ch3_dsp_vld ) ,.debug_rwaddr ( debug_rwaddr ) ,.debug_wrdata ( debug_wrdata ) ,.debug_bwen ( debug_bwen ) ,.debug_wren ( debug_wren ) ,.debug_cen ( debug_cen ) ); //--------------------------------------------------------------------------------------------- //debug SRAM (512w x 128d) //--------------------------------------------------------------------------------------------- sram_if #(12,256) dbg_sram_out(clk); wire [255:0] dbg_sramb_dout ; wire [11 :0] dbg_sramb_addr = dbg_sram_out.addr[11:0] ; wire [255:0] dbg_sramb_din = dbg_sram_out.din ; wire [31 :0] dbg_sramb_wben = ~dbg_sram_out.wben ; wire dbg_sramb_wren = ~dbg_sram_out.wren & dbg_sram_out.rden ; wire dbg_sramb_cen = ~(dbg_sram_out.wren | dbg_sram_out.rden); assign dbg_sram_out.dout = dbg_sramb_dout; dpram #( .DATAWIDTH ( 256 ) ,.ADDRWIDTH ( 12 ) ) U_dbg_sram ( .PortClk ( clk ) ,.PortAAddr ( debug_rwaddr ) ,.PortADataIn ( debug_wrdata ) ,.PortAWriteEnable ( debug_wren ) ,.PortAChipEnable ( debug_cen ) ,.PortAByteWriteEnable ( debug_bwen ) ,.PortADataOut ( ) ,.PortBAddr ( dbg_sramb_addr ) ,.PortBDataIn ( dbg_sramb_din ) ,.PortBWriteEnable ( dbg_sramb_wren ) ,.PortBChipEnable ( dbg_sramb_cen ) ,.PortBByteWriteEnable ( dbg_sramb_wben ) ,.PortBDataOut ( dbg_sramb_dout ) ); //--------------------------------------------------------------------------------------------- //debug SRAM (512w x 128d) //--------------------------------------------------------------------------------------------- sram_dmux_w #( .ADDR_WIDTH ( 12 ) ,.DATA_WIDTH_I ( 32 ) ,.DATA_WIDTH_O ( 256 ) ) U_sram_dmux_w ( .clk ( clk ) ,.rst_n ( rst_n ) ,.port_in ( dbg_sram_in ) ,.port_out ( dbg_sram_out ) ); endmodule