`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 2024/03/19 10:41:08 // Design Name: // Module Name: intpll_regfile // Project Name: // Target Devices: // Tool Versions: // Description: // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// // ----------------------------------------------------------- // -- Register address offset macros // ----------------------------------------------------------- //Int pll Ctrl Register `define INTPLL_REFCTRL 8'h00 `define INTPLL_PCNT 8'h04 `define INTPLL_PFDCTRL 8'h08 `define INTPLL_SPDCTRL 8'h0C `define INTPLL_PTATCTRL 8'h10 `define INTPLL_FLLCTRL 8'h14 `define INTPLL_SELCTRL 8'h18 `define INTPLL_VCOCTRL 8'h1C `define INTPLL_VCOFBADJ 8'h20 `define INTPLL_AFCCTRL 8'h24 `define INTPLL_AFCCNT 8'h28 `define INTPLL_AFCLDCNT 8'h2C `define INTPLL_AFCPRES 8'h30 `define INTPLL_AFCLDTCC 8'h34 `define INTPLL_AFCFBTCC 8'h38 `define INTPLL_DIVCFG 8'h3C `define INTPLL_TCLKCFG 8'h40 `define INTPLL_DCLKSEL 8'h44 `define INTPLL_STATUS 8'h48 `define INTPLL_SYNCFG 8'h4C `define INTPLL_UPDATE 8'h50 `define INTPLL_CLKRXPD 8'h54 module intpll_regfile ( //system port input clk // System Main Clock ,input rst_n // Spi Reset active low //rw op port ,input [31 :0] wrdata // write data ,input wren // write enable ,input [7 :0] rwaddr // read & write address ,input rden // read enable ,output [31 :0] rddata // read data ,output ref_sel // Clock source selection for a frequency divider; // 1'b0:External clock source // 1'b1:internal phase-locked loop clock source ,output ref_en // Input reference clock enable // 1'b0:enable,1'b1:disable ,output ref_s2d_en // Referenced clock differential to single-ended conversion enable // 1'b0:enable,1'b1:disable ,output [6 :0] p_cnt // P counter ,output pfd_delay // PFD Dead Zone ,output pfd_dff_Set // Setting the PFD register,active high ,output pfd_dff_4and // PFD output polarity ,output [3 :0] spd_div // SPD Frequency Divider ,output spd_pulse_width // Pulse Width of SPD ,output spd_pulse_sw // Pulse sw of SPD ,output cpc_sel // current source selection ,output [1 :0] swcp_i // PTAT current switch ,output [3 :0] sw_ptat_r // PTAT current adjustment ,output [1 :0] sw_fll_cpi // Phase-locked loop charge pump current ,output sw_fll_delay // PLL Dead Zone ,output pfd_sel // PFD Loop selection ,output spd_sel // SPD Loop selection ,output fll_sel // FLL Loop selection ,output vco_tc // VCO temperature compensation ,output vco_tcr // VCO temperature compensation resistor ,output vco_gain_adj // VCO gain adjustment ,output vco_gain_adj_r // VCO gain adjustment resistor ,output [2 :0] vco_cur_adj // VCO current adjustment ,output vco_buff_en // VCO buff enable,active high ,output vco_en // VCO enable,active high ,output [2 :0] pll_dpwr_adj // PLL frequency division output power adjustment ,output [6 :0] vco_fb_adj // VCO frequency band adjustment ,output afc_en // AFC enable ,output afc_shutdown // AFC module shutdown signal ,output [0 :0] afc_det_speed // AFC detection speed ,output [0 :0] flag_out_sel // Read and choose the signs ,output afc_reset // AFC reset ,output [10 :0] afc_cnt // AFC frequency band adjustment function counter // counting time adjustment ,output [10 :0] afc_ld_cnt // Adjust the counting time of the AFC lock detection // feature counter ,output [3 :0] afc_pres // Adjusting the resolution of the AFC comparator ,output [14 :0] afc_ld_tcc // AFC Lock Detection Function Target Cycle Count ,output [14 :0] afc_fb_tcc // Target number of cycles for AFC frequency band // adjustment function ,output [0 :0] div_rstn_sel // div rstn select, 1'b0: ext clear, 1'b1:inter pll lock ,output [1 :0] test_clk_sel // test clk select, 2'b00:DIV1 clk, 2'b01:DIV2 clk, 2'b10:DIV4 clk, 2'b11:DIV8 clk ,output [0 :0] test_clk_oen // test clk output enable, 1'b0:disenable, 1'b1:enable ,output [7 :0] dig_clk_sel // digital main clk select, one hot code,bit[0]-->0 degree phase,bit[1]-->45 degree phase.....bit[7]-->315degree phae ,output [0 :0] div_sync_en // Frequency Divider Synchronous Clear Enable ,output sync_oe // SYNC signal output enable, hign active ,output clkrx_pdn // Clock Rx Power down, Ative Low ,input pll_lock // PLL LOCK ); localparam L = 1'b0, H = 1'b1; // ------------------------------------------------------ // -- Register enable (select) wires // ------------------------------------------------------ wire refctrlen ; wire pcnten ; wire pfdctrlen ; wire spdctrlen ; wire ptatctrlen ; wire fllctrlen ; wire selctrlen ; wire vcoctrlen ; wire vcofbadjen ; wire afcctrlen ; wire afccnten ; wire afcldcnten ; wire afcpresen ; wire afcldtccen ; wire afcfbtccen ; wire divcfgen ; wire tclkcfgen ; wire dclkselen ; wire statusen ; wire synccfgen ; wire updateen ; wire clkrxpden ; // ------------------------------------------------------ // -- Register write enable wires // ------------------------------------------------------ wire refctrlwe ; wire pcntwe ; wire pfdctrlwe ; wire spdctrlwe ; wire ptatctrlwe ; wire fllctrlwe ; wire selctrlwe ; wire vcoctrlwe ; wire vcofbadjwe ; wire afcctrlwe ; wire afccntwe ; wire afcldcntwe ; wire afcpreswe ; wire afcldtccwe ; wire afcfbtccwe ; wire divcfgwe ; wire tclkcfgwe ; wire dclkselwe ; wire synccfgwe ; wire updatewe ; wire clkrxpdwe ; // ------------------------------------------------------ // -- Misc Registers // ------------------------------------------------------ wire [2 :0] refctrl_r ; wire [6 :0] pcnt_r ; wire [2 :0] pfdctrl_r ; wire [5 :0] spdctrl_r ; wire [6 :0] ptatctrl_r ; wire [2 :0] fllctrl_r ; wire [2 :0] selctrl_r ; wire [11:0] vcoctrl_r ; wire [6 :0] vcofbadj_r ; wire [4 :0] afcctrl_r ; wire [10:0] afccnt_r ; wire [10:0] afcldcnt_r ; wire [3 :0] afcpres_r ; wire [14:0] afcldtcc_r ; wire [14:0] afcfbtcc_r ; wire [0 :0] divrstsel_r ; wire [2 :0] testclk_r ; wire [7 :0] digclksel_r ; wire [1 :0] sync_r ; wire clkrxpd_r ; wire [2 :0] refctrl_updr ; wire [6 :0] pcnt_updr ; wire [2 :0] pfdctrl_updr ; wire [5 :0] spdctrl_updr ; wire [6 :0] ptatctrl_updr ; wire [2 :0] fllctrl_updr ; wire [2 :0] selctrl_updr ; wire [11:0] vcoctrl_updr ; wire [6 :0] vcofbadj_updr ; wire [4 :0] afcctrl_updr ; wire [10:0] afccnt_updr ; wire [10:0] afcldcnt_updr ; wire [3 :0] afcpres_updr ; wire [14:0] afcldtcc_updr ; wire [14:0] afcfbtcc_updr ; reg [31 :0] rddata_reg ; // ------------------------------------------------------ // -- Address decoder // // Decodes the register address offset input(reg_addr) // to produce enable (select) signals for each of the // SW-registers in the macrocell. The reg_addr input // is bits [15:0] of the paddr bus. // ------------------------------------------------------ assign refctrlen = (rwaddr[7:2] == `INTPLL_REFCTRL >>2) ? 1'b1 : 1'b0; assign pcnten = (rwaddr[7:2] == `INTPLL_PCNT >>2) ? 1'b1 : 1'b0; assign pfdctrlen = (rwaddr[7:2] == `INTPLL_PFDCTRL >>2) ? 1'b1 : 1'b0; assign spdctrlen = (rwaddr[7:2] == `INTPLL_SPDCTRL >>2) ? 1'b1 : 1'b0; assign ptatctrlen = (rwaddr[7:2] == `INTPLL_PTATCTRL >>2) ? 1'b1 : 1'b0; assign fllctrlen = (rwaddr[7:2] == `INTPLL_FLLCTRL >>2) ? 1'b1 : 1'b0; assign selctrlen = (rwaddr[7:2] == `INTPLL_SELCTRL >>2) ? 1'b1 : 1'b0; assign vcoctrlen = (rwaddr[7:2] == `INTPLL_VCOCTRL >>2) ? 1'b1 : 1'b0; assign vcofbadjen = (rwaddr[7:2] == `INTPLL_VCOFBADJ >>2) ? 1'b1 : 1'b0; assign afcctrlen = (rwaddr[7:2] == `INTPLL_AFCCTRL >>2) ? 1'b1 : 1'b0; assign afccnten = (rwaddr[7:2] == `INTPLL_AFCCNT >>2) ? 1'b1 : 1'b0; assign afcldcnten = (rwaddr[7:2] == `INTPLL_AFCLDCNT >>2) ? 1'b1 : 1'b0; assign afcpresen = (rwaddr[7:2] == `INTPLL_AFCPRES >>2) ? 1'b1 : 1'b0; assign afcldtccen = (rwaddr[7:2] == `INTPLL_AFCLDTCC >>2) ? 1'b1 : 1'b0; assign afcfbtccen = (rwaddr[7:2] == `INTPLL_AFCFBTCC >>2) ? 1'b1 : 1'b0; assign divcfgen = (rwaddr[7:2] == `INTPLL_DIVCFG >>2) ? 1'b1 : 1'b0; assign tclkcfgen = (rwaddr[7:2] == `INTPLL_TCLKCFG >>2) ? 1'b1 : 1'b0; assign dclkselen = (rwaddr[7:2] == `INTPLL_DCLKSEL >>2) ? 1'b1 : 1'b0; assign statusen = (rwaddr[7:2] == `INTPLL_STATUS >>2) ? 1'b1 : 1'b0; assign synccfgen = (rwaddr[7:2] == `INTPLL_SYNCFG >>2) ? 1'b1 : 1'b0; assign updateen = (rwaddr[7:2] == `INTPLL_UPDATE >>2) ? 1'b1 : 1'b0; assign clkrxpden = (rwaddr[7:2] == `INTPLL_CLKRXPD >>2) ? 1'b1 : 1'b0; // ------------------------------------------------------ // -- Write enable signals // // Write enable signals for writable SW-registers. // The write enable for each register is the ANDed // result of the register enable and the input reg_wren // ------------------------------------------------------ assign refctrlwe = refctrlen & wren; assign pcntwe = pcnten & wren; assign pfdctrlwe = pfdctrlen & wren; assign spdctrlwe = spdctrlen & wren; assign ptatctrlwe = ptatctrlen & wren; assign fllctrlwe = fllctrlen & wren; assign selctrlwe = selctrlen & wren; assign vcoctrlwe = vcoctrlen & wren; assign vcofbadjwe = vcofbadjen & wren; assign afcctrlwe = afcctrlen & wren; assign afccntwe = afccnten & wren; assign afcldcntwe = afcldcnten & wren; assign afcpreswe = afcpresen & wren; assign afcldtccwe = afcldtccen & wren; assign afcfbtccwe = afcfbtccen & wren; assign divcfgwe = divcfgen & wren; assign tclkcfgwe = tclkcfgen & wren; assign dclkselwe = dclkselen & wren; assign synccfgwe = synccfgen & wren; assign updatewe = updateen & wren; assign clkrxpdwe = clkrxpden & wren; // ------------------------------------------------------ // -- refctrl_r Register // // Write refctrl_r for 'REFCTRL' : 32-bit register // Register is split into the following bit fields // // [2] --> ref_s2d_en default : 1'b1 // [1] --> ref_en default : 1'b1 // [0] --> ref_sel default : 1'b0 // ------------------------------------------------------ sirv_gnrl_dfflrd #(3) refctrl_dfflrd (3'b110, refctrlwe, wrdata[2:0], refctrl_r, clk, rst_n); //update sirv_gnrl_dfflrd #(3) refctrl_updr_dfflrd (3'b110, updatewe, refctrl_r, refctrl_updr, clk, rst_n); // ------------------------------------------------------ // -- pcnt_r Register // // Write pcnt_r for 'PCNT' : 32-bit register // Register is split into the following bit fields // // [6 : 0] --> pcnt default : 7'b000_1100 // ------------------------------------------------------ sirv_gnrl_dfflrd #(7) pcnt_dfflrd (7'b000_1100, pcntwe, wrdata[6:0], pcnt_r, clk, rst_n); //update sirv_gnrl_dfflrd #(7) pcnt_updr_dfflrd (7'b000_1100, updatewe, pcnt_r, pcnt_updr, clk, rst_n); // ------------------------------------------------------ // -- pfdctrl_r Register // // Write pfdctrl_reg for 'REFCTRL' : 32-bit register // Register is split into the following bit fields // // [2] --> pfd_dff_4and default : 1'b1 // [1] --> pfd_dff_Set default : 1'b1 // [0] --> pfd_delay default : 1'b0 // ------------------------------------------------------ sirv_gnrl_dfflrd #(3) pfdctrl_dfflrd (3'b110, pfdctrlwe, wrdata[2:0], pfdctrl_r, clk, rst_n);////////////////////////////////////////////// //update sirv_gnrl_dfflrd #(3) pfdctrl_updr_dfflrd (3'b110, updatewe, pfdctrl_r, pfdctrl_updr, clk, rst_n); // ------------------------------------------------------ // -- spdctrl_r Register // // Write spdctrl_r for 'SPDCTRL' : 32-bit register // Register is split into the following bit fields // // [5 ] spd_pulse_sw default : 1'b0 // [4 ] spd_pulse_width default : 1'b0 // [3:0] spd_div default : 4'b0100 // ------------------------------------------------------ sirv_gnrl_dfflrd #(6) spdctrl_dfflrd (6'b00_0100, spdctrlwe, wrdata[5:0], spdctrl_r, clk, rst_n); //update sirv_gnrl_dfflrd #(6) spdctrl_updr_dfflrd (6'b00_0100, updatewe, spdctrl_r, spdctrl_updr, clk, rst_n); // ------------------------------------------------------ // -- ptatctrl_r Register // // Write ptatctrl_r for 'PTATCTRL' : 32-bit register // Register is split into the following bit fields // // [6 ] cpc_sel default : 1'b1 // [5:4] swcp_i default : 2'b01 // [3:0] sw_ptat_r default : 4'b1000 // ------------------------------------------------------ sirv_gnrl_dfflrd #(7) ptatctrl_dfflrd (7'b101_1000, ptatctrlwe, wrdata[6:0], ptatctrl_r, clk, rst_n); //update sirv_gnrl_dfflrd #(7) ptatctrl_updr_dfflrd (7'b101_1000, updatewe, ptatctrl_r, ptatctrl_updr, clk, rst_n); // ------------------------------------------------------ // -- fllctrl_r Register // // Write fllctrl_r for 'FLLCTRL' : 32-bit register // Register is split into the following bit fields // // [2 ] sw_fll_delay default : 1'b0 // [1:0] sw_fll_cpi default : 2'b11 // ------------------------------------------------------ sirv_gnrl_dfflrd #(3) fllctrl_dfflrd (3'b011, fllctrlwe, wrdata[2:0], fllctrl_r, clk, rst_n); //update sirv_gnrl_dfflrd #(3) fllctrl_updr_dfflrd (3'b011, updatewe, fllctrl_r, fllctrl_updr, clk, rst_n); // ------------------------------------------------------ // -- selctrl_r Register // // Write selctrl_r for 'SELCTRL' : 32-bit register // Register is split into the following bit fields // // [2] fll_sel default : 1'b0 // [1] spd_sel default : 1'b1 // [0] pfd_sel default : 1'b0 // ------------------------------------------------------ sirv_gnrl_dfflrd #(3) selctrl_dfflrd (3'b010, selctrlwe, wrdata[2:0], selctrl_r, clk, rst_n); //update sirv_gnrl_dfflrd #(3) selctrl_updr_dfflrd (3'b010, updatewe, selctrl_r, selctrl_updr, clk, rst_n); // ------------------------------------------------------ // -- vcoctrl_r Register // // Write vcoctrl_r for 'VCOCTRL' : 32-bit register // Register is split into the following bit fields // // [11:9] pll_dpwr_adj default : 3'b111 // [8 ] vco_en default : 1'b1 // [7 ] vco_buff_en default : 1'b1 // [6 :4] vco_cur_adj default : 3'b111 // [3 ] vco_gain_adj_r default : 1'b0 // [2 ] vco_gain_adj default : 1'b0 // [1 ] vco_tcr default : 1'b0 // [0 ] vco_tc default : 1'b0 // ------------------------------------------------------ sirv_gnrl_dfflrd #(12) vcoctrl_dfflrd (12'b1111_1111_0000, vcoctrlwe, wrdata[11:0], vcoctrl_r, clk, rst_n); //update sirv_gnrl_dfflrd #(12) vcoctrl_updr_dfflrd (12'b1111_1111_0000, updatewe, vcoctrl_r, vcoctrl_updr, clk, rst_n); // ------------------------------------------------------ // -- vcofbadj_r Register // // Write vcofbadj_r for 'VCOFBADJ' : 32-bit register // Register is split into the following bit fields // // [6 : 0] --> vco_fb_adj default : 7'b000_0000 // ------------------------------------------------------ sirv_gnrl_dfflrd #(7) vcofbadj_dfflrd (7'b000_0000, vcofbadjwe, wrdata[6:0], vcofbadj_r, clk, rst_n); //update sirv_gnrl_dfflrd #(7) vcofbadj_updr_dfflrd (7'b000_0000, updatewe, vcofbadj_r, vcofbadj_updr, clk, rst_n); // ------------------------------------------------------ // -- afcctrl_r Register // // Write afcctrl_r for 'AFCCTRL' : 32-bit register // Register is split into the following bit fields // // [4] afc_det_speed // default : 1'b0 // [3] flag_out_sel // default : 1'b0 // [2] afc_shutdown // default : 1'b0 // [1] afc_reset // default : 1'b0 // [0] afc_en // default : 1'b0 // ------------------------------------------------------ sirv_gnrl_dfflrd #(5) afcctrl_dfflrd (5'b0_0000, afcctrlwe, wrdata[4:0], afcctrl_r, clk, rst_n); //update sirv_gnrl_dfflrd #(5) afcctrl_updr_dfflrd (5'b0_0000, updatewe, afcctrl_r, afcctrl_updr, clk, rst_n); // ------------------------------------------------------ // -- afccnt_r Register // // Write afccnt_r for 'AFCCnt' : 32-bit register // Register is split into the following bit fields // // [10:0] --> afc_cnt default : 11'b000_1100_1000 // ------------------------------------------------------ sirv_gnrl_dfflrd #(11) afccnt_dfflrd (11'b000_1100_1000, afccntwe, wrdata[10:0], afccnt_r, clk, rst_n); //update sirv_gnrl_dfflrd #(11) afccnt_updr_dfflrd (11'b000_1100_1000, updatewe, afccnt_r, afccnt_updr, clk, rst_n); // ------------------------------------------------------ // -- afccnt_r Register // // Write afcldcnt_r for 'AFCLDCnt' : 32-bit register // Register is split into the following bit fields // // [10:0] --> afcld_cnt default : 11'b110_0100_0000 // ------------------------------------------------------ sirv_gnrl_dfflrd #(11) afcldcnt_dfflrd (11'b110_0100_0000, afcldcntwe, wrdata[10:0], afcldcnt_r, clk, rst_n); //update sirv_gnrl_dfflrd #(11) afcldcnt_updr_dfflrd (11'b110_0100_0000, updatewe, afcldcnt_r, afcldcnt_updr, clk, rst_n); // ------------------------------------------------------ // -- afcpres_r Register // // Write afcpres_r for 'AFCPRES' : 32-bit register // Register is split into the following bit fields // // [3:0] --> afc_pres default : 4'b0011 // ------------------------------------------------------ sirv_gnrl_dfflrd #(4) afcpres_dfflrd (4'b0011, afcpreswe, wrdata[3:0], afcpres_r, clk, rst_n); //update sirv_gnrl_dfflrd #(4) afcpres_updr_dfflrd (4'b0011, updatewe, afcpres_r, afcpres_updr, clk, rst_n); // ------------------------------------------------------ // -- afcldtcc_r Register // // Write afcldtcc_r for 'AFCLDTCC' : 32-bit register // Register is split into the following bit fields // // [14:0] --> afc_ld_tcc default : 15'b0 // ------------------------------------------------------ sirv_gnrl_dfflrd #(15) afcldtcc_dfflrd (15'b0, afcldtccwe, wrdata[14:0], afcldtcc_r, clk, rst_n); //update sirv_gnrl_dfflrd #(15) afcldtcc_updr_dfflrd (15'b0, updatewe, afcldtcc_r, afcldtcc_updr, clk, rst_n); // ------------------------------------------------------ // -- afcfbtcc_r Register // // Write afcfbtcc_r for 'AFCLDTCC' : 32-bit register // Register is split into the following bit fields // // [14:0] --> afc_fb_tcc default : 15'b0 // ------------------------------------------------------ sirv_gnrl_dfflrd #(15) afcfbtcc_dfflrd (15'b0, afcfbtccwe, wrdata[14:0], afcfbtcc_r, clk, rst_n); //update sirv_gnrl_dfflrd #(15) afcfbtcc_updr_dfflrd (15'b0, updatewe, afcfbtcc_r, afcfbtcc_updr, clk, rst_n); // ------------------------------------------------------ // -- divrstsel_r Register // // Write divrstsel_r for 'DIVCFG' : 32-bit register // Register is split into the following bit fields // // [0] --> divrstsel default : 1'b0 // ------------------------------------------------------ sirv_gnrl_dfflrd #(1) divrstsel_r_dfflrd (1'b0, divcfgwe, wrdata[0], divrstsel_r, clk, rst_n); // ------------------------------------------------------ // -- testclk_r Register // // Write divclksel_r for 'TCLKCFG' : 32-bit register // Register is split into the following bit fields // // [1:0] --> testclksel default : 1'b0 // [2] --> testclkoen default : 1'b0 // ------------------------------------------------------ sirv_gnrl_dfflrd #(3) testclk_r_dfflrd (3'b0, tclkcfgwe, wrdata[2:0], testclk_r, clk, rst_n); // ------------------------------------------------------ // -- digclksel_r Register // // Write digclksel_r for 'DIGCLKSEL' : 32-bit register // Register is split into the following bit fields // // [7:0] --> digclksel default : 1'b0 // ------------------------------------------------------ sirv_gnrl_dfflrd #(8) digclksel_r_dfflrd (8'b0000_0001, dclkselwe, wrdata[7:0], digclksel_r, clk, rst_n); // ------------------------------------------------------ // -- clkrxpd_r Register // // Write digclksel_r for 'CLKRXPD' : 32-bit register // Register is split into the following bit fields // // [0:0] --> clkrxpd default : 1'b0 // ------------------------------------------------------ sirv_gnrl_dfflrd #(1) clkrxpd_r_dfflrd (1'b0, clkrxpdwe, wrdata[0], clkrxpd_r, clk, rst_n); // ------------------------------------------------------ // -- sync_r Register // // Write divsync_r for 'SYNCFG' : 32-bit register // Register is split into the following bit fields // // [0] --> divsync default : 1'b0 // [1] --> sync_oe default : 1'b0 // ------------------------------------------------------ sirv_gnrl_dfflrd #(2) sync_dfflrd (2'b0, synccfgwe, wrdata[1:0], sync_r, clk, rst_n); // ------------------------------------------------------ // -- Read data mux // // -- The data from the selected register is // -- placed on a zero-padded 32-bit read data bus. // ------------------------------------------------------ always @(*) begin : RDDATA_PROC rddata_reg = {32{1'b0}}; if(refctrlen == H ) rddata_reg[2 :0] = refctrl_r ; if(pcnten == H ) rddata_reg[6 :0] = pcnt_r ; if(pfdctrlen == H ) rddata_reg[2 :0] = pfdctrl_r ; if(spdctrlen == H ) rddata_reg[5 :0] = spdctrl_r ; if(ptatctrlen == H ) rddata_reg[6 :0] = ptatctrl_r ; if(fllctrlen == H ) rddata_reg[2 :0] = fllctrl_r ; if(selctrlen == H ) rddata_reg[2 :0] = selctrl_r ; if(vcoctrlen == H ) rddata_reg[11:0] = vcoctrl_r ; if(vcofbadjen == H ) rddata_reg[6 :0] = vcofbadj_r ; if(afcctrlen == H ) rddata_reg[4 :0] = afcctrl_r ; if(afccnten == H ) rddata_reg[10:0] = afccnt_r ; if(afcldcnten == H ) rddata_reg[10:0] = afcldcnt_r ; if(afcpresen == H ) rddata_reg[3 :0] = afcpres_r ; if(afcldtccen == H ) rddata_reg[14:0] = afcldtcc_r ; if(afcfbtccen == H ) rddata_reg[14:0] = afcfbtcc_r ; if(divcfgen == H ) rddata_reg[0 :0] = divrstsel_r ; if(tclkcfgen == H ) rddata_reg[2 :0] = testclk_r ; if(dclkselen == H ) rddata_reg[7 :0] = digclksel_r ; if(statusen == H ) rddata_reg[0 :0] = pll_lock ; if(synccfgen == H ) rddata_reg[1 :0] = sync_r ; if(clkrxpden == H ) rddata_reg[1 :0] = clkrxpd_r ; end //rddata sirv_gnrl_dfflr #(32) rddata_dfflr (rden, rddata_reg, rddata, clk, rst_n); // ------------------------------------------------------ // -- Output signals assignment // ------------------------------------------------------ assign ref_sel = refctrl_updr[0] ; // Clock source selection for a frequency divider; // 1'b0:External clock source // 1'b1:internal phase-locked loop clock source assign ref_en = refctrl_updr[1] ; // Input reference clock enable // 1'b0:enable,1'b1:disable assign ref_s2d_en = refctrl_updr[2] ; // Referenced clock differential to single-ended conversion enable // 1'b0:enable,1'b1:disable assign p_cnt = pcnt_updr[6:0] ; // P counter assign pfd_delay = pfdctrl_updr[0] ; // PFD Dead Zone assign pfd_dff_Set = pfdctrl_updr[1] ; // Setting the PFD register,active high assign pfd_dff_4and = pfdctrl_updr[2] ; // PFD output polarity assign spd_div = spdctrl_updr[3:0] ; // SPD Frequency Divider assign spd_pulse_width = spdctrl_updr[4] ; // Pulse Width of SPD assign spd_pulse_sw = spdctrl_updr[5] ; // Pulse sw of SPD assign cpc_sel = ptatctrl_updr[6] ; // current source selection assign swcp_i = ptatctrl_updr[5:4] ; // PTAT current switch assign sw_ptat_r = ptatctrl_updr[3:0] ; // PTAT current adjustment assign sw_fll_cpi = fllctrl_updr[1:0] ; // Phase-locked loop charge pump current assign sw_fll_delay = fllctrl_updr[2] ; // PLL Dead Zone assign pfd_sel = selctrl_updr[0] ; // PFD Loop selection assign spd_sel = selctrl_updr[1] ; // SPD Loop selection assign fll_sel = selctrl_updr[2] ; // FLL Loop selection assign vco_tc = vcoctrl_updr[0] ; // VCO temperature compensation assign vco_tcr = vcoctrl_updr[1] ; // VCO temperature compensation resistor assign vco_gain_adj = vcoctrl_updr[2] ; // VCO gain adjustment assign vco_gain_adj_r = vcoctrl_updr[3] ; // VCO gain adjustment resistor assign vco_cur_adj = vcoctrl_updr[6:4] ; // VCO current adjustment assign vco_buff_en = vcoctrl_updr[7] ; // VCO buff enable,active high assign vco_en = vcoctrl_updr[8] ; // VCO enable,active high assign pll_dpwr_adj = vcoctrl_updr[11:9] ; // PLL frequency division output power adjustment assign vco_fb_adj = vcofbadj_updr[6:0] ; // VCO frequency band adjustment assign afc_en = afcctrl_updr[0] ; // AFC enable assign afc_reset = afcctrl_updr[1] ; // AFC reset assign afc_shutdown = afcctrl_updr[2] ; // AFC module shutdown signal assign flag_out_sel = afcctrl_updr[3] ; // Read and choose the signs assign afc_det_speed = afcctrl_updr[4] ; // AFC detection speed assign afc_cnt = afccnt_updr[10:0] ; // AFC frequency band adjustment function counter // counting time adjustment assign afc_ld_cnt = afcldcnt_updr[10:0] ; // Adjust the counting time of the AFC lock detection // feature counter assign afc_pres = afcpres_updr[3:0] ; // Adjusting the resolution of the AFC comparator assign afc_ld_tcc = afcldtcc_updr[14:0] ; // AFC Lock Detection Function Target Cycle Count assign afc_fb_tcc = afcfbtcc_updr[14:0] ; // Target number of cycles for AFC frequency band // adjustment function assign div_rstn_sel = divrstsel_r[0:0] ; // assign test_clk_sel = testclk_r[1:0] ; // assign test_clk_oen = testclk_r[2] ; // assign dig_clk_sel = digclksel_r[7:0] ; // assign div_sync_en = sync_r[0] ; // Frequency Divider Synchronous Clear Enable assign sync_oe = sync_r[1] ; // SYNC signal output enable, hign active assign clkrx_pdn = clkrxpd_r ; endmodule `undef INTPLL_REFCTRL `undef INTPLL_PCNT `undef INTPLL_PFDCTRL `undef INTPLL_SPDCTRL `undef INTPLL_PTATCTRL `undef INTPLL_FLLCTRL `undef INTPLL_SELCTRL `undef INTPLL_VCOCTRL `undef INTPLL_VCOFBADJ `undef INTPLL_AFCCTRL `undef INTPLL_AFCCNT `undef INTPLL_AFCLDCNT `undef INTPLL_AFCPRES `undef INTPLL_AFCLDTCC `undef INTPLL_AFCFBTCC `undef INTPLL_DIVCFG `undef INTPLL_TCLKCFG `undef INTPLL_DCLKSEL `undef INTPLL_STATUS `undef INTPLL_SYNCFG `undef INTPLL_UPDATE