//+FHDR--------------------------------------------------------------------------------------------------------
//  Company: 
//-----------------------------------------------------------------------------------------------------------------
//  File Name             :    awg_ctrl.v
//  Department            :    
//  Author                :    PWY
//  Author's Tel          :     
//-----------------------------------------------------------------------------------------------------------------
//  Relese History
//  Version     Date            Author          Description
//  0.1         2024-03-13      PWY             Configuration parameters lookup tabl
//-----------------------------------------------------------------------------------------------------------------
//  Keywords            :       
//
//-----------------------------------------------------------------------------------------------------------------
//  Parameter
//
//-----------------------------------------------------------------------------------------------------------------
//  Purpose                 :
//                      
//-----------------------------------------------------------------------------------------------------------------
//  Target Device:        
//  Tool versions:        
//-----------------------------------------------------------------------------------------------------------------
//  Reuse Issues
//  Reset Strategy: 
//  Clock Domains: 
//  Critical Timing:
//  Asynchronous I/F:
//  Synthesizable (y/n): 
//  Other:
//-FHDR--------------------------------------------------------------------------------------------------------


module param_lut (
   clk        
  ,rst_n      
  ,param_i    
  ,index_i    
  ,index_vld_i
  ,param_o    
);

//=================================================
function integer clog2(input integer depth);
begin
        for(clog2=0;depth>1;clog2=clog2+1)
                depth =depth>>1;
end
endfunction
//=================================================
parameter  DXLEN = 32;
parameter  PNUM  = 4;
//=================================================

//system port
input                      clk                   ;       
input                      rst_n                 ;        
input  [DXLEN-1       :0]  param_i    [PNUM-1:0] ;
input  [clog2(PNUM)-1 :0]  index_i               ;
input                      index_vld_i           ;
output [DXLEN-1       :0]  param_o               ;

generate
  genvar i;
  wire [PNUM-1  :0] cs_slv;
  wire [DXLEN-1 :0] dtemp [PNUM-1:0];
  
  for(i=0;i<PNUM;i=i+1) begin: CS_SLV
    assign cs_slv[i] = (index_i == i );
    if(i==0)begin: DTEMP0
      assign dtemp[i] = (cs_slv[i]) ? param_i[i] : 32'b0;
	end
    else begin: DTEMP1_32
      assign dtemp[i] = (cs_slv[i]) ? param_i[i] : dtemp[i-1];
	end
  end
endgenerate


//paramter register
sirv_gnrl_dfflr #(DXLEN) param_dfflr (index_vld_i, dtemp[PNUM-1], param_o, clk, rst_n);

endmodule