//+FHDR--------------------------------------------------------------------------------------------------------
//  Company: 
//-----------------------------------------------------------------------------------------------------------------
//  File Name             :    modout_mux.v
//  Department            :    
//  Author                :    PWY
//  Author's Tel          :     
//-----------------------------------------------------------------------------------------------------------------
//  Relese History
//  Version     Date            Author          Description
//  0.1         2024-05-13      PWY             debug top-level
//-----------------------------------------------------------------------------------------------------------------
//  Keywords            :       
//
//-----------------------------------------------------------------------------------------------------------------
//  Parameter
//
//-----------------------------------------------------------------------------------------------------------------
//  Purpose                 :
//                      
//-----------------------------------------------------------------------------------------------------------------
//  Target Device:        
//  Tool versions:        
//-----------------------------------------------------------------------------------------------------------------
//  Reuse Issues
//  Reset Strategy: 
//  Clock Domains: 
//  Critical Timing:
//  Asynchronous I/F:
//  Synthesizable (y/n): 
//  Other:
//-FHDR--------------------------------------------------------------------------------------------------------

module modout_mux (
//system port
   input         clk                             // System Main Clock
  ,input         rst_n                           // Spi Reset active low
  //---------------from ctrl regfile------------------------------------
  ,input         sel                             // 1'b0 --> mod modem data; 1'b1 --> mod nco data
  //mod nco data
  ,input  [15:0] sin
  ,input  [15:0] cos
  //mod modem data
  ,input  [15:0] mod_data_i
  ,input  [15:0] mod_data_q
  ,input         mod_data_vld
  //mux out data
  ,output [15:0] mux_data_i
  ,output [15:0] mux_data_q
  ,output        mux_data_vld
);

wire [15:0] mux_data_i_w   = sel ? sin  : mod_data_i;
wire [15:0] mux_data_q_w   = sel ? cos  : mod_data_q;
wire        mux_data_vld_w = sel ? 1'b1 : mod_data_vld;

`ifdef MODDOUT_MUX_REG
sirv_gnrl_dffr #(16) mux_data_i_dffr   (mux_data_i_w  , mux_data_i  , clk, rst_n);
sirv_gnrl_dffr #(16) mux_data_q_dffr   (mux_data_q_w  , mux_data_q  , clk, rst_n);
sirv_gnrl_dffr #(1 ) mux_data_vld_dffr (mux_data_vld_w, mux_data_vld, clk, rst_n);
`else
assign  mux_data_i    = mux_data_i_w    ; 
assign  mux_data_q    = mux_data_q_w    ;
assign  mux_data_vld  = mux_data_vld_w  ;
`endif
endmodule