//+FHDR-------------------------------------------------------------------------------------------------------- // Company: //----------------------------------------------------------------------------------------------------------------- // File Name : ctrl_regfile.v // Department : // Author : PWY // Author's Tel : //----------------------------------------------------------------------------------------------------------------- // Relese History // Version Date Author Description // 0.1 2024-03-13 PWY AWG dedicated register file // 0.2 2024-05-13 PWY //----------------------------------------------------------------------------------------------------------------- // Keywords : // //----------------------------------------------------------------------------------------------------------------- // Parameter // //----------------------------------------------------------------------------------------------------------------- // Purpose : // //----------------------------------------------------------------------------------------------------------------- // Target Device: // Tool versions: //----------------------------------------------------------------------------------------------------------------- // Reuse Issues // Reset Strategy: // Clock Domains: // Critical Timing: // Asynchronous I/F: // Synthesizable (y/n): // Other: //-FHDR-------------------------------------------------------------------------------------------------------- // ----------------------------------------------------------- // -- Register address offset macros // ----------------------------------------------------------- //MCU parameter register 0 `define MCUPARAR0 16'h00 //MCU parameter register 1 `define MCUPARAR1 16'h04 //MCU parameter register 2 `define MCUPARAR2 16'h08 //MCU parameter register 3 `define MCUPARAR3 16'h0C //MCU result register 0 `define MCURESR0 16'h10 //MCU result register 1 `define MCURESR1 16'h14 //MCU result register 2 `define MCURESR2 16'h18 //MCU result register 3 `define MCURESR3 16'h1C //Run-time register `define RTIMR 16'h98 //Instruction count register `define ICNTR 16'h9C //Feedback state information register `define FSIR 16'hA0 //Modulator Operation Mode Register `define MODMR 16'h100 //Interpolator Operation Mode Register `define INTPMR 16'h104 //Frequency Mixer NCO Clear Register `define MIXNCOCR 16'h108 //Frequency Mixer NCO Frequency Control Word High 32-bit Register `define MIXNFCWHR 16'h10C //Frequency Mixer NCO Frequency Control Word Low 16-bit Register `define MIXNFCWLR 16'h110 //Frequency Mixer NCO Phase Control Word Register `define MIXNPHAR 16'h114 //Frequency Mixer Operating Mode Register `define MIXMR 16'h118 //Frequency Mixer Output Data Type Register `define MIXODTR 16'h11C //Frequency Mixer Output Data Format Register `define MIXODFR 16'h120 //Roler Selection Register `define ROLER 16'h128 //Mixed-frequency NCO sync clear enable Register `define MIXNCOSCER 16'h12C //AWG data out type select Register `define MODDOTR 16'h130 //Status Register `define STR 16'h134 //AWG always on Register `define DSPAOR 16'h138 module ctrl_regfile ( //system port input clk // System Main Clock ,input rst_n // Spi Reset active low //rw op port ,input [31 :0] wrdata // write data ,input wren // write enable ,input [15 :0] rwaddr // read & write address ,input rden // read enable ,output [31 :0] rddata // read data ,input [1 :0] fb_st_i ,input [31 :0] run_time ,input [31 :0] instr_num ,input bais_i_ov ,input bais_q_ov ,input awg_ctrl_fsm_st //MCU and SPI interface for interaction ,output [31 :0] mcu_param0 // MCU parameter 0 ,output [31 :0] mcu_param1 // MCU parameter 1 ,output [31 :0] mcu_param2 // MCU parameter 2 ,output [31 :0] mcu_param3 // MCU parameter 3 ,input [31 :0] mcu_result0 // MCU result 0 ,input [31 :0] mcu_result1 // MCU result 1 ,input [31 :0] mcu_result2 // MCU result 2 ,input [31 :0] mcu_result3 // MCU result 3 ,output [1 :0] fb_st_o //awg cfg ,output mod_sel_sideband //1'b0:Upper sideband;1'b1:Lower sideband; //DSP cfg ,output qam_nco_clr ,output qam_nco_sclr_en ,output [47 :0] qam_fcw//////////////////////////////////////////////////////////////////////////////////////////////////// ,output [15 :0] qam_pha ////////////////////////////////////////////////////////////////////////////////////////////// ,output [1 :0] qam_mod //2'b00:bypass;2'b01:mix; //2'b10:cos;2'b11:sin; ,output qam_sel_sideband //1'b0:Upper sideband;1'b1:Lower sideband; ,output [2 :0] intp_mode //3'b000:x1;3'b001:x2;3'b010:x4; //3'b011:x8;3'b100:x16; ,output [1 :0] role_sel //[0] --> 1'b0: xy-chip;1'b1: z-chip; //[1] --> 1'b0:AC mode;1'b1: DC mode; //Please note that when the role is set to xy-chip, //only AC mode is supported. ,output [1 :0] dac_mode_sel //2'b00:NRZ mode;2'b01:MIX mode; //2'b10:2xNRZ mode;2'b00:reserve; ,output dout_sel //1'b0 --> mod modem data; 1'b1 --> mod nco data //1'b0 --> Z dsp data for ZDAC; 1'b1 --> xy dsp data for ZDAC ,output dsp_alwayson //1'b0 --> dsp output data vaild depend on awg vaild; //1'b1 --> dsp output data always vaild; ); localparam L = 1'b0, H = 1'b1; // ------------------------------------------------------ // -- Register enable (select) wires // ------------------------------------------------------ wire mcuparar0en ; // MCUPARAR0 select wire mcuparar1en ; // MCUPARAR1 select wire mcuparar2en ; // MCUPARAR2 select wire mcuparar3en ; // MCUPARAR3 select wire mcuresr0en ; // MCURESR0 select wire mcuresr1en ; // MCURESR1 select wire mcuresr2en ; // MCURESR2 select wire mcuresr3en ; // MCURESR3 select wire rtimren ; // RTIMR select wire icntren ; // ICNTR select wire fsiren ; // FSIR select wire modmren ; // MODMR select wire intpmren ; // INTPMR select wire mixncocren ; // MIXNCOCR select wire mixnfcwhren ; // MIXNFCWHR select wire mixnfcwlren ; // MIXNFCWLR select wire mixnpharen ; // MIXNPHAR select wire mixmren ; // MIXMR select wire mixodtren ; // MIXODTR select wire mixodfren ; // MIXODFR select wire roleren ; // ROLER select wire mixncosceren ; // MIXNCOSCER select wire stren ; // BAISOVR select wire moddotren ; // MODDOTR select wire dspaoren ; // DSPAOR select // ------------------------------------------------------ // -- Register write enable wires // ------------------------------------------------------ wire mcuparar0we ; // MCUPARAR0 write enable wire mcuparar1we ; // MCUPARAR1 write enable wire mcuparar2we ; // MCUPARAR2 write enable wire mcuparar3we ; // MCUPARAR3 write enable wire modmrwe ; // MODMR write enable wire intpmrwe ; // INTPMR write enable wire mixncocrwe ; // MIXNCOCR write enable wire mixnfcwhrwe ; // MIXNFCWHR write enable wire mixnfcwlrwe ; // MIXNFCWLR write enable wire mixnpharwe ; // MIXNPHAR write enable wire mixmrwe ; // MIXMR write enable wire mixodtrwe ; // MIXODTR write enable wire mixodfrwe ; // MIXODFR write enable wire rolerwe ; // ROLER write enable wire mixncoscerwe ; // MIXNCOSCER write enable wire moddotrwe ; // MODDOTR write enable wire dspaorwe ; // DSPAOR write enable // ------------------------------------------------------ // -- Misc wires // ------------------------------------------------------ // ------------------------------------------------------ // -- Misc Registers // ------------------------------------------------------ wire [31 :0] mcuparar0 ; // MCUPARAR0 register wire [31 :0] mcuparar1 ; // MCUPARAR1 register wire [31 :0] mcuparar2 ; // MCUPARAR2 register wire [31 :0] mcuparar3 ; // MCUPARAR3 register wire [31 :0] mcuresr0 ; // MCURESR0 register wire [31 :0] mcuresr1 ; // MCURESR1 register wire [31 :0] mcuresr2 ; // MCURESR2 register wire [31 :0] mcuresr3 ; // MCURESR3 register wire [31 :0] rtimr ; // RTIMR register wire [31 :0] icntr ; // ICNTR register wire [1 :0] fsir ; // FSIR register wire [0 :0] modmr ; // MODMR register wire [2 :0] intpmr ; // INTPMR register wire [0 :0] mixncocr ; // MIXNCOCR register wire [31 :0] mixnfcwhr ; // MIXNFCWHR register wire [15 :0] mixnfcwlr ; // MIXNFCWLR register wire [15 :0] mixnphar ; // MIXNPHAR register wire [0 :0] mixmr ; // MIXMR register wire [1 :0] mixodtr ; // MIXODTR register wire [1 :0] mixodfr ; // MIXODFR register wire [1 :0] roler ; // ROLER register wire [0 :0] dspaor ; // DSPAOR register wire [0 :0] mixncoscer ; // MIXNCOSCER register wire moddotr ; // MODDOTR register reg [31: 0] rddata_reg ; // ------------------------------------------------------ // -- Address decoder // // Decodes the register address offset input(reg_addr) // to produce enable (select) signals for each of the // SW-registers in the macrocell. The reg_addr input // is bits [15:0] of the paddr bus. // ------------------------------------------------------ assign mcuparar0en = (rwaddr[15:2] == `MCUPARAR0 >> 2) ? 1'b1 : 1'b0; assign mcuparar1en = (rwaddr[15:2] == `MCUPARAR1 >> 2) ? 1'b1 : 1'b0; assign mcuparar2en = (rwaddr[15:2] == `MCUPARAR2 >> 2) ? 1'b1 : 1'b0; assign mcuparar3en = (rwaddr[15:2] == `MCUPARAR3 >> 2) ? 1'b1 : 1'b0; assign mcuresr0en = (rwaddr[15:2] == `MCURESR0 >> 2) ? 1'b1 : 1'b0; assign mcuresr1en = (rwaddr[15:2] == `MCURESR1 >> 2) ? 1'b1 : 1'b0; assign mcuresr2en = (rwaddr[15:2] == `MCURESR2 >> 2) ? 1'b1 : 1'b0; assign mcuresr3en = (rwaddr[15:2] == `MCURESR3 >> 2) ? 1'b1 : 1'b0; assign rtimren = (rwaddr[15:2] == `RTIMR >> 2) ? 1'b1 : 1'b0; assign icntren = (rwaddr[15:2] == `ICNTR >> 2) ? 1'b1 : 1'b0; assign fsiren = (rwaddr[15:2] == `FSIR >> 2) ? 1'b1 : 1'b0; assign modmren = (rwaddr[15:2] == `MODMR >> 2) ? 1'b1 : 1'b0; assign intpmren = (rwaddr[15:2] == `INTPMR >> 2) ? 1'b1 : 1'b0; assign mixncocren = (rwaddr[15:2] == `MIXNCOCR >> 2) ? 1'b1 : 1'b0; assign mixnfcwhren = (rwaddr[15:2] == `MIXNFCWHR >> 2) ? 1'b1 : 1'b0; assign mixnfcwlren = (rwaddr[15:2] == `MIXNFCWLR >> 2) ? 1'b1 : 1'b0; assign mixnpharen = (rwaddr[15:2] == `MIXNPHAR >> 2) ? 1'b1 : 1'b0; assign mixmren = (rwaddr[15:2] == `MIXMR >> 2) ? 1'b1 : 1'b0; assign mixodtren = (rwaddr[15:2] == `MIXODTR >> 2) ? 1'b1 : 1'b0; assign mixodfren = (rwaddr[15:2] == `MIXODFR >> 2) ? 1'b1 : 1'b0; assign roleren = (rwaddr[15:2] == `ROLER >> 2) ? 1'b1 : 1'b0; assign mixncosceren = (rwaddr[15:2] == `MIXNCOSCER >> 2) ? 1'b1 : 1'b0; assign stren = (rwaddr[15:2] == `STR >> 2) ? 1'b1 : 1'b0; assign moddotren = (rwaddr[15:2] == `MODDOTR >> 2) ? 1'b1 : 1'b0; assign dspaoren = (rwaddr[15:2] == `DSPAOR >> 2) ? 1'b1 : 1'b0; // ------------------------------------------------------ // -- Write enable signals // // Write enable signals for writable SW-registers. // The write enable for each register is the ANDed // result of the register enable and the input reg_wren // ------------------------------------------------------ assign mcuparar0we = mcuparar0en & wren; assign mcuparar1we = mcuparar1en & wren; assign mcuparar2we = mcuparar2en & wren; assign mcuparar3we = mcuparar3en & wren; assign modmrwe = modmren & wren;/////////// assign intpmrwe = intpmren & wren; assign mixncocrwe = mixncocren & wren; assign mixnfcwhrwe = mixnfcwhren & wren; assign mixnfcwlrwe = mixnfcwlren & wren; assign mixnpharwe = mixnpharen & wren; assign mixmrwe = mixmren & wren; assign mixodtrwe = mixodtren & wren; assign mixodfrwe = mixodfren & wren; assign rolerwe = roleren & wren; assign mixncoscerwe = mixncosceren & wren; assign moddotrwe = moddotren & wren; assign dspaorwe = dspaoren & wren; // ------------------------------------------------------ // -- mcuparar0 register // // Write mcuparar0 for 'MCUPARAR0' : 32-bit register // Register is split into the following bit fields // // [31:0] --> mcuparar0 // ------------------------------------------------------ sirv_gnrl_dfflr #(32) mcuparar0_dfflr (mcuparar0we, wrdata[31:0], mcuparar0, clk, rst_n); // ------------------------------------------------------ // -- mcuparar1 register // // Write mcuparar1 for 'MCUPARAR1' : 32-bit register // Register is split into the following bit fields // // [31:0] --> mcuparar1 // ------------------------------------------------------ sirv_gnrl_dfflr #(32) mcuparar1_dfflr (mcuparar1we, wrdata[31:0], mcuparar1, clk, rst_n); // ------------------------------------------------------ // -- mcuparar2 register // // Write mcuparar2 for 'MCUPARAR2' : 32-bit register // Register is split into the following bit fields // // [31:0] --> mcuparar2 // ------------------------------------------------------ sirv_gnrl_dfflr #(32) mcuparar2_dfflr (mcuparar2we, wrdata[31:0], mcuparar2, clk, rst_n); // ------------------------------------------------------ // -- mcuparar3 register // // Write mcuparar3 for 'MCUPARAR3' : 32-bit register // Register is split into the following bit fields // // [31:0] --> mcuparar3 // ------------------------------------------------------ sirv_gnrl_dfflr #(32) mcuparar3_dfflr (mcuparar3we, wrdata[31:0], mcuparar3, clk, rst_n); // ------------------------------------------------------ // -- modmr register // // Write modmr for 'MODMR' : 32-bit register // Register is split into the following bit fields // // [0] --> modmr // ------------------------------------------------------ sirv_gnrl_dfflr #(1) modmr_dfflr (modmrwe, wrdata[0], modmr, clk, rst_n); // ------------------------------------------------------ // -- intpmr register // // Write intpmr for 'INTPMR' : 32-bit register // Register is split into the following bit fields // // [2:0] --> intpmr // ------------------------------------------------------ sirv_gnrl_dfflr #(3) intpmr_dfflr (intpmrwe, wrdata[2:0], intpmr, clk, rst_n); // ------------------------------------------------------ // -- mixncocr register // // Write mixncocr for 'MIXNCOCR' : 32-bit register // Register is split into the following bit fields // // [0] --> mixncocr // ------------------------------------------------------ sirv_gnrl_dfflr #(1) mixncocr_dfflr (mixncocrwe, wrdata[0], mixncocr, clk, rst_n); // ------------------------------------------------------ // -- mixnfcwhr register // // Write mixnfcwhr for 'MIXNFCWHR' : 32-bit register // Register is split into the following bit fields // // [31:0] --> mixnfcwhr // ------------------------------------------------------ sirv_gnrl_dfflr #(32) mixnfcwhr_dfflr (mixnfcwhrwe, wrdata[31:0], mixnfcwhr, clk, rst_n); // ------------------------------------------------------ // -- mixnfcwlr register // // Write mixnfcwlr for 'MIXNFCWHR' : 32-bit register // Register is split into the following bit fields // // [31:16] --> mixnfcwlr // ------------------------------------------------------ sirv_gnrl_dfflr #(16) mixnfcwlr_dfflr (mixnfcwlrwe, wrdata[31:16], mixnfcwlr, clk, rst_n); // ------------------------------------------------------ // -- mixnphar register // // Write mixnphar for 'MIXNPHAR' : 32-bit register // Register is split into the following bit fields // // [31:16] --> mixnphar // ------------------------------------------------------ sirv_gnrl_dfflr #(16) mixnphar_dfflr (mixnpharwe, wrdata[31:16], mixnphar, clk, rst_n); // ------------------------------------------------------ // -- mixmr register // // Write mixmr for 'MIXNPHAR' : 32-bit register // Register is split into the following bit fields // // [0] --> mixmr // ------------------------------------------------------ sirv_gnrl_dfflr #(1) mixmr_dfflr (mixmrwe, wrdata[0], mixmr, clk, rst_n); // ------------------------------------------------------ // -- mixodtr register // // Write mixodtr for 'MIXNPHAR' : 32-bit register // Register is split into the following bit fields // // [1:0] --> mixodtr // ------------------------------------------------------ sirv_gnrl_dfflr #(2) mixodtr_dfflr (mixodtrwe, wrdata[1:0], mixodtr, clk, rst_n); // ------------------------------------------------------ // -- mixodfr register // // Write mixodfr for 'MIXODFR' : 32-bit register // Register is split into the following bit fields // // [1:0] --> mixodfr // ------------------------------------------------------ sirv_gnrl_dfflr #(2) mixodfr_dfflr (mixodfrwe, wrdata[1:0], mixodfr, clk, rst_n); // ------------------------------------------------------ // -- roler register // // Write roler for 'ROLER' : 32-bit register // Register is split into the following bit fields // // [1] --> AC or DC mode select // [0] --> xy-chip or z-chip select // ------------------------------------------------------ sirv_gnrl_dfflr #(1) roler0_dfflr (rolerwe, wrdata[0], roler[0], clk, rst_n); //Please note that when the role is set to xy-chip, only AC mode is supported. wire mode_w = wrdata[0] & wrdata[1]; // 0 | 0 | x // 0 | 1 | 0 // 1 | 1 | 1 sirv_gnrl_dfflr #(1) roler1_dfflr (rolerwe, mode_w, roler[1], clk, rst_n); // ------------------------------------------------------ // -- mixncoscer register // // Write mixncoscer for 'mixncoscer' : 32-bit register // Register is split into the following bit fields // // [0] --> mixncoscer // ------------------------------------------------------ sirv_gnrl_dfflr #(1) mixncoscer_dfflr (mixncoscerwe, wrdata[0], mixncoscer, clk, rst_n); // ------------------------------------------------------ // -- moddotr register // // Write moddotr for 'moddotr' : 32-bit register // Register is split into the following bit fields // // [0] --> moddotr // ------------------------------------------------------ sirv_gnrl_dfflr #(1) moddotr_dfflr (moddotrwe, wrdata[0], moddotr, clk, rst_n); // ------------------------------------------------------ // -- dspaor register // // Write dspaor for 'dspaor' : 32-bit register // Register is split into the following bit fields // // [0] --> dspaor // ------------------------------------------------------ sirv_gnrl_dfflrs #(1) dspaor_dfflrs (dspaorwe, wrdata[0], dspaor, clk, rst_n); // ------------------------------------------------------ // -- mcuresr0 // ------------------------------------------------------ sirv_gnrl_dffr #(32) mcuparar0_dffr (mcu_result0, mcuresr0, clk, rst_n); // ------------------------------------------------------ // -- mcuresr1 // ------------------------------------------------------ sirv_gnrl_dffr #(32) mcuparar1_dffr (mcu_result1, mcuresr1, clk, rst_n); // ------------------------------------------------------ // -- mcuresr2 // ------------------------------------------------------ sirv_gnrl_dffr #(32) mcuparar2_dffr (mcu_result2, mcuresr2, clk, rst_n); // ------------------------------------------------------ // -- mcuresr3 // ------------------------------------------------------ sirv_gnrl_dffr #(32) mcuparar3_dffr (mcu_result3, mcuresr3, clk, rst_n); // ------------------------------------------------------ // -- rtimr // ------------------------------------------------------ sirv_gnrl_dffr #(32) rtimr_dffr (run_time, rtimr, clk, rst_n); // ------------------------------------------------------ // -- icntr // ------------------------------------------------------ sirv_gnrl_dffr #(32) icntr_dffr (instr_num, icntr, clk, rst_n); // ------------------------------------------------------ // -- fsir // ------------------------------------------------------ sirv_gnrl_dffr #(2) fsir_dffr (fb_st_i[1:0], fsir, clk, rst_n);//////////////////////////////////////////////////////////[1:0] // ------------------------------------------------------ // -- Read data mux // // -- The data from the selected register is // -- placed on a zero-padded 32-bit read data bus. // ------------------------------------------------------ always @(*) begin : RDDATA_PROC rddata_reg = {32{1'b0}}; if(mcuparar0en == H ) rddata_reg[31:0] = mcuparar0 ; if(mcuparar1en == H ) rddata_reg[31:0] = mcuparar1 ; if(mcuparar2en == H ) rddata_reg[31:0] = mcuparar2 ; if(mcuparar3en == H ) rddata_reg[31:0] = mcuparar3 ; if(mcuresr0en == H ) rddata_reg[31:0] = mcuresr0 ; if(mcuresr1en == H ) rddata_reg[31:0] = mcuresr1 ; if(mcuresr2en == H ) rddata_reg[31:0] = mcuresr2 ; if(mcuresr3en == H ) rddata_reg[31:0] = mcuresr3 ; if(rtimren == H ) rddata_reg[31:0] = rtimr ; if(icntren == H ) rddata_reg[31:0] = icntr ; if(fsiren == H ) rddata_reg[1 :0] = fsir ; if(modmren == H ) rddata_reg[0 :0] = modmr ; if(intpmren == H ) rddata_reg[2 :0] = intpmr ; if(roleren == H ) rddata_reg[1 :0] = roler ; if(mixncocren == H ) rddata_reg[0 :0] = mixncocr ; if(mixnfcwhren == H ) rddata_reg[31:0] = mixnfcwhr ; if(mixnfcwlren == H ) rddata_reg[15:0] = mixnfcwlr ; if(mixnpharen == H ) rddata_reg[15:0] = mixnphar ; if(mixmren == H ) rddata_reg[0 :0] = mixmr ; if(mixodtren == H ) rddata_reg[1 :0] = mixodtr ; if(mixodfren == H ) rddata_reg[1 :0] = mixodfr ; if(mixncosceren == H ) rddata_reg[0 :0] = mixncoscer ; if(moddotren == H ) rddata_reg[0 :0] = moddotr ; if(stren == H ) rddata_reg[2 :0] = {bais_q_ov,bais_i_ov,awg_ctrl_fsm_st} ; if(dspaoren == H ) rddata_reg[0 :0] = dspaor ; end // ------------------------------------------------------ // -- Output signals assignment // ------------------------------------------------------ //mcu result assign mcu_param0 = mcuparar0 ; assign mcu_param1 = mcuparar1 ; assign mcu_param2 = mcuparar2 ; assign mcu_param3 = mcuparar3 ; //fb_st_o assign fb_st_o = fsir ; //awg cfg assign mod_sel_sideband = modmr ; //DSP cfg assign qam_nco_clr = mixncocr ; assign qam_fcw = {mixnfcwhr,mixnfcwlr} ; assign qam_pha = mixnphar ; assign qam_mod = mixodtr ; assign qam_sel_sideband = mixmr ; assign intp_mode = intpmr ; assign dac_mode_sel = mixodfr ; assign qam_nco_sclr_en = mixncoscer ; assign role_sel = roler ; assign dout_sel = moddotr ; assign dsp_alwayson = dspaor ; //rddata sirv_gnrl_dffr #(32) rddata_dffr (rddata_reg, rddata, clk, rst_n); endmodule `undef MCUPARAR0 `undef MCUPARAR1 `undef MCUPARAR2 `undef MCUPARAR3 `undef MCURESR0 `undef MCURESR1 `undef MCURESR2 `undef MCURESR3 `undef RTIMR `undef ICNTR `undef FSIR `undef MODMR `undef INTPMR `undef MIXNCOCR `undef MIXNFCWHR `undef MIXNFCWLR `undef MIXNPHAR `undef MIXMR `undef MIXODTR `undef MIXODFR `undef MIXNCOSCER `undef MODDOTR `undef STR