//+FHDR--------------------------------------------------------------------------------------------------------
//  Company: 
//-----------------------------------------------------------------------------------------------------------------
//  File Name             :    codeword_decode.v
//  Department            :    
//  Author                :    PWY
//  Author's Tel          :     
//-----------------------------------------------------------------------------------------------------------------
//  Relese History
//  Version     Date            Author          Description
//  0.1         2024-03-13      PWY             Analyze the code words sent by the MCU
//-----------------------------------------------------------------------------------------------------------------
//  Keywords            :       
//
//-----------------------------------------------------------------------------------------------------------------
//  Parameter
//
//-----------------------------------------------------------------------------------------------------------------
//  Purpose                 :
//                      
//-----------------------------------------------------------------------------------------------------------------
//  Target Device:        
//  Tool versions:        
//-----------------------------------------------------------------------------------------------------------------
//  Reuse Issues
//  Reset Strategy: 
//  Clock Domains: 
//  Critical Timing:
//  Asynchronous I/F:
//  Synthesizable (y/n): 
//  Other:
//-FHDR--------------------------------------------------------------------------------------------------------


module codeword_decode (
  //system port
   input          clk                      // System Main Clock
  ,input          rst_n                    // Spi Reset active low
  //Extend instructions port
  // The operands and info to peripheral
  ,input          send_i
  ,input          sendc_i   
  ,input  [31 :0] codeword_i 
  ,input  [1  :0] fb_st_i
  //The output data remains as the last waveform value
  ,output         wave_hold_o
  //Bais lookup table index
  ,output [1  :0] bais_index_o
  //Amplitude lookup table index
  ,output [1  :0] amp_index_o
  //Gate appended phase lookup table index
  ,output [2  :0] nco_pha_index_o
  //Carrier frequency lookup table index
  ,output [1  :0] nco_fcw_index_o
  //envelope lookup table index
  ,output [7  :0] envelope_index_o
  //Index valid
  ,output         index_vld_o
);

//Sending waveforms according to feedback conditions
wire send_cond = sendc_i | codeword_i[20];

//The output data remains as the last waveform value
wire wave_hold_w = codeword_i[19];

//Bais lookup table index
wire [1  :0] bais_index_w = codeword_i[16:15];

//Amplitude lookup table index
wire [1  :0] amp_index_w = codeword_i[14:13];

//Gate appended phase lookup table index
wire [2  :0] nco_pha_index_w = codeword_i[12:10];

//Carrier frequency lookup table index
wire [1  :0] nco_fcw_index_w = codeword_i[9:8];

//envelope lookup table index
wire [7  :0] envelope_index_w = send_cond ? codeword_i[7:0] + fb_st_i : codeword_i[7:0]; 

//Valid Signal Generation
wire index_vld_w = send_i | sendc_i;

/////////////////////////////////////////////////////////
//Output data register
/////////////////////////////////////////////////////////

//wave_hold_o
sirv_gnrl_dfflr #(1) wave_hold_dfflr (index_vld_w, wave_hold_w, wave_hold_o, clk, rst_n);

//bais_index_o
sirv_gnrl_dfflr #(2) bais_index_dfflr (index_vld_w, bais_index_w, bais_index_o, clk, rst_n);

//amp_index_o
sirv_gnrl_dfflr #(2) amp_index_dfflr (index_vld_w, amp_index_w, amp_index_o, clk, rst_n);

//nco_pha_index_o
sirv_gnrl_dfflr #(3) nco_pha_index_dfflr (index_vld_w, nco_pha_index_w, nco_pha_index_o, clk, rst_n);

//nco_fcw_index_o
sirv_gnrl_dfflr #(2) nco_fcw_index_dfflr (index_vld_w, nco_fcw_index_w, nco_fcw_index_o, clk, rst_n);

//envelope_index_o
sirv_gnrl_dfflr #(8) envelope_index_dfflr (index_vld_w, envelope_index_w, envelope_index_o, clk, rst_n);

//index_vld_o
sirv_gnrl_dffr #(1)  index_vld_dffr (index_vld_w ,index_vld_o, clk, rst_n);



endmodule