//+FHDR-------------------------------------------------------------------------------------------------------- // Company: //----------------------------------------------------------------------------------------------------------------- // File Name : awg_top.v // Department : // Author : PWY // Author's Tel : //----------------------------------------------------------------------------------------------------------------- // Relese History // Version Date Author Description // 0.1 2024-03-13 PWY MCU dedicated register file //----------------------------------------------------------------------------------------------------------------- // Keywords : // //----------------------------------------------------------------------------------------------------------------- // Parameter // //----------------------------------------------------------------------------------------------------------------- // Purpose : // //----------------------------------------------------------------------------------------------------------------- // Target Device: // Tool versions: //----------------------------------------------------------------------------------------------------------------- // Reuse Issues // Reset Strategy: // Clock Domains: // Critical Timing: // Asynchronous I/F: // Synthesizable (y/n): // Other: //-FHDR-------------------------------------------------------------------------------------------------------- module awg_top ( //system port input clk // System Main Clock ,input rst_n // Spi Reset active low //----------------------------from mcu----------------------------------------------------------- //lookup table data ,input [31 :0] mcu_cwfr [3:0] // Carrier frequency ctrl word 0~3 ,input [15 :0] mcu_gapr [7:0] // Carrier phase ctrl word 0~7 ,input [15 :0] mcu_ampr [3:0] // Amplitude 0~3 ,input [15 :0] mcu_baisr [3:0] // Bais 0~3 //CFG Port ,input mcu_nco_pha_clr ,input [15 :0] mcu_rz_pha // The operands and info to peripheral ,input send ,input sendc ,input [31 :0] codeword ,input [1 :0] fb_st //----------------------------from spi----------------------------------------------------------- //Envelope storage read/write signal ,input [31 :0] enve_bwrdata ,input [0 :0] enve_bwren ,input [14 :0] enve_brwaddr ,input [0 :0] enve_brden ,output [31 :0] enve_brddata //envelope index lookup table read-write signal ,input [31 :0] enve_id_bwrdata ,input [0 :0] enve_id_bwren ,input [7 :0] enve_id_brwaddr ,input [0 :0] enve_id_brden ,output [31 :0] enve_id_brddata //----------------------------to ctrl regfile------------------------------------------------------ //Envelope read fsm status ,output [0 :0] enve_read_fsm_st //Process conflict ,output proc_cft //----------------------------from ctrl regfile------------------------------------------------------ ,input mod_sideband_sel //1'b0: Mod_data_i = Icoswd+Qsinwd, Mod_data_q = Isinwd+Qcoswd //1'b1: Mod_data_i = Icoswd-Qsinwd, Mod_data_q = -Isinwd+Qcoswd ,input mod_pha_sfot_clr ,input [1 :0] role_sel //[0] --> 1'b0: xy-chip;1'b1: z-chip; //[1] --> 1'b0: AC mode;1'b1: DC mode; ,input mod_dout_sel //1'b0 --> mod modem data; 1'b1 --> mod nco data //1'b1 --> awg output data always vaild; //----------------------------to DSP---------------------------------------------------------------- //Output awg data ,output [15 :0] awg_data_i ,output [15 :0] awg_data_q ,output awg_vld ,output bais_i_ov ,output bais_q_ov ); //------------------------------------------------------------------------------------------ //codeword decode //------------------------------------------------------------------------------------------ wire wave_hold ; wire [1 :0] bais_index ; wire [1 :0] amp_index ; wire [2 :0] nco_pha_index ; wire [1 :0] nco_fcw_index ; wire [7 :0] envelope_index ; wire index_vld ; codeword_decode U_codeword_decode ( .clk ( clk ) ,.rst_n ( rst_n ) ,.send_i ( send ) ,.sendc_i ( sendc ) ,.codeword_i ( codeword ) ,.fb_st_i ( fb_st ) ,.wave_hold_o ( wave_hold ) ,.bais_index_o ( bais_index ) ,.amp_index_o ( amp_index ) ,.nco_pha_index_o ( nco_pha_index ) ,.nco_fcw_index_o ( nco_fcw_index ) ,.envelope_index_o ( envelope_index ) ,.index_vld_o ( index_vld ) ); //------------------------------------------------------------------------------------------ //Carrier frequency ctrl word LUT //------------------------------------------------------------------------------------------ wire [31:0] mod_nco_fcw_i; param_lut #( .DXLEN ( 32 ) ,.PNUM ( 4 ) ) fcw_lut ( .clk ( clk ) ,.rst_n ( rst_n ) ,.param_i ( mcu_cwfr ) ,.index_i ( nco_fcw_index ) ,.index_vld_i ( index_vld ) ,.param_o ( mod_nco_fcw_i ) ); //------------------------------------------------------------------------------------------ //Carrier phase ctrl word 0~7 //------------------------------------------------------------------------------------------ wire [15:0] mod_nco_pha_i; param_lut #( .DXLEN ( 16 ) ,.PNUM ( 8 ) ) pha_lut ( .clk ( clk ) ,.rst_n ( rst_n ) ,.param_i ( mcu_gapr ) ,.index_i ( nco_pha_index ) ,.index_vld_i ( index_vld ) ,.param_o ( mod_nco_pha_i ) ); //------------------------------------------------------------------------------------------ // Amplitude 0~3 //------------------------------------------------------------------------------------------ wire [15:0] mod_amp_i; param_lut #( .DXLEN ( 16 ) ,.PNUM ( 4 ) ) ampr_lut ( .clk ( clk ) ,.rst_n ( rst_n ) ,.param_i ( mcu_ampr ) ,.index_i ( amp_index ) ,.index_vld_i ( index_vld ) ,.param_o ( mod_amp_i ) ); //------------------------------------------------------------------------------------------ // Bais 0~3 //------------------------------------------------------------------------------------------ wire [15:0] z_bais_i; param_lut #( .DXLEN ( 16 ) ,.PNUM ( 4 ) ) bais_lut ( .clk ( clk ) ,.rst_n ( rst_n ) ,.param_i ( mcu_baisr ) ,.index_i ( bais_index ) ,.index_vld_i ( index_vld ) ,.param_o ( z_bais_i ) ); //------------------------------------------------------------------------------------------ // enve_id_dpram //------------------------------------------------------------------------------------------ wire enve_index_vld ; sirv_gnrl_dffr #(1) enve_index_vld_dffr (index_vld, enve_index_vld, clk, rst_n); //Envelope LUT Clock wire [0 :0] Enve_Id_PortClk = clk ; //The envelope LUT A port is connected to the internal codeword decode wire [7 :0] Enve_Id_PortAAddr = envelope_index << 2 ; //To align the address, the signal is left-shifted by 2 bits //as the memory bytes are presented in byte addresses wire [31 :0] Enve_Id_PortADataIn = 32'h0 ; wire [0 :0] Enve_Id_PortAWriteEnable = 1'b1 ; wire [0 :0] Enve_Id_PortAChipEnable = ~index_vld ; wire [32/8-1:0] Enve_Id_PortAByteWriteEnable = 4'b0000 ; wire [31 :0] Enve_Id_PortADataOut ; wire [31 :0] enve_id_info = Enve_Id_PortADataOut ; //The B port of the envelope LUT connects to an external SPI bus decode wire [7 :0] Enve_Id_PortBAddr = enve_id_brwaddr ; wire [31 :0] Enve_Id_PortBDataIn = enve_id_bwrdata ; wire [0 :0] Enve_Id_PortBWriteEnable = ~enve_id_bwren & enve_id_brden ; wire [0 :0] Enve_Id_PortBChipEnable = ~(enve_id_bwren | enve_id_brden) ; wire [32/8-1:0] Enve_Id_PortBByteWriteEnable = 4'b0000 ; wire [31 :0] Enve_Id_PortBDataOut ; assign enve_id_brddata = Enve_Id_PortBDataOut ; wire [15 :0] enve_start_addr = enve_id_info[31:16]; wire [15 :0] enve_len = enve_id_info[15:0 ]; dpram #( .DATAWIDTH ( 32 ) ,.ADDRWIDTH ( 8 ) ) enve_id_dpram ( .PortClk ( Enve_Id_PortClk ) ,.PortAAddr ( Enve_Id_PortAAddr ) ,.PortADataIn ( Enve_Id_PortADataIn ) ,.PortAWriteEnable ( Enve_Id_PortAWriteEnable ) ,.PortAChipEnable ( Enve_Id_PortAChipEnable ) ,.PortAByteWriteEnable ( Enve_Id_PortAByteWriteEnable ) ,.PortADataOut ( Enve_Id_PortADataOut ) ,.PortBAddr ( Enve_Id_PortBAddr ) ,.PortBDataIn ( Enve_Id_PortBDataIn ) ,.PortBWriteEnable ( Enve_Id_PortBWriteEnable ) ,.PortBChipEnable ( Enve_Id_PortBChipEnable ) ,.PortBByteWriteEnable ( Enve_Id_PortBByteWriteEnable ) ,.PortBDataOut ( Enve_Id_PortBDataOut ) ); //------------------------------------------------------------------------------------------ // enve_id_dpram //------------------------------------------------------------------------------------------ wire enve_arden ; wire [15 :0] enve_ardaddr ; wire [31 :0] enve_arddata ; wire [15 :0] enve_idata ; wire [15 :0] enve_qdata ; wire [0 :0] enve_vld ; wire [31 :0] mod_nco_fcw ; wire [15 :0] mod_nco_pha ; wire mod_pha_clr ; wire [15 :0] mod_amp ; wire [15 :0] z_bais ; awg_ctrl U_awg_ctrl ( .clk ( clk ) ,.rst_n ( rst_n ) ,.enve_index_vld_i ( enve_index_vld ) ,.enve_start_addr_i ( enve_start_addr ) ,.enve_len_i ( enve_len ) ,.wave_hold_i ( wave_hold ) ,.enve_rden_o ( enve_arden ) ,.enve_rdaddr_o ( enve_ardaddr ) ,.enve_rddata_i ( enve_arddata ) ,.enve_idata_o ( enve_idata ) ,.enve_qdata_o ( enve_qdata ) ,.enve_vld_o ( enve_vld ) ,.enve_read_fsm_st_o ( enve_read_fsm_st ) ,.proc_cft_o ( proc_cft ) ,.muc_mod_nco_fcw_i ( mod_nco_fcw_i ) ,.muc_mod_nco_pha_i ( mod_nco_pha_i ) ,.muc_mod_nco_rz_pha_i ( mcu_rz_pha ) ,.muc_mod_pha_clr_i ( mcu_nco_pha_clr ) ,.muc_mod_amp_i ( mod_amp_i ) ,.muc_z_bais_i ( z_bais_i ) ,.mod_nco_fcw_o ( mod_nco_fcw ) ,.mod_nco_pha_o ( mod_nco_pha ) ,.mod_pha_clr_o ( mod_pha_clr ) ,.mod_amp_o ( mod_amp ) ,.z_bais_o ( z_bais ) ); //------------------------------------------------------------------------------------------ // envelope dpram //------------------------------------------------------------------------------------------ //Envelope Memory Clock wire [0 :0] Enve_PortClk = clk ; //The envelope storage A port is connected to the internal AWG controller wire [14 :0] Enve_PortAAddr = enve_ardaddr[14:0] ; wire [31 :0] Enve_PortADataIn = 32'h0 ; wire [0 :0] Enve_PortAWriteEnable = 1'b1 ; wire [0 :0] Enve_PortAChipEnable = ~enve_arden ; wire [32/8-1:0] Enve_PortAByteWriteEnable = 4'b0000 ; wire [31 :0] Enve_PortADataOut ; assign enve_arddata = Enve_PortADataOut ; //The B port of the envelope storage connects to an external SPI bus decode wire [14 :0] Enve_PortBAddr = enve_brwaddr[14:0] ; wire [31 :0] Enve_PortBDataIn = enve_bwrdata ; wire [0 :0] Enve_PortBWriteEnable = ~enve_bwren & enve_brden ; wire [0 :0] Enve_PortBChipEnable = ~(enve_bwren | enve_brden) ; wire [32/8-1:0] Enve_PortBByteWriteEnable = 4'b0000 ; wire [31 :0] Enve_PortBDataOut ; assign enve_brddata = Enve_PortBDataOut ; dpram #( .DATAWIDTH ( 32 ) ,.ADDRWIDTH ( 15 ) ) enve_dpram ( .PortClk ( Enve_PortClk ) ,.PortAAddr ( Enve_PortAAddr ) ,.PortADataIn ( Enve_PortADataIn ) ,.PortAWriteEnable ( Enve_PortAWriteEnable ) ,.PortAChipEnable ( Enve_PortAChipEnable ) ,.PortAByteWriteEnable ( Enve_PortAByteWriteEnable ) ,.PortADataOut ( Enve_PortADataOut ) ,.PortBAddr ( Enve_PortBAddr ) ,.PortBDataIn ( Enve_PortBDataIn ) ,.PortBWriteEnable ( Enve_PortBWriteEnable ) ,.PortBChipEnable ( Enve_PortBChipEnable ) ,.PortBByteWriteEnable ( Enve_PortBByteWriteEnable ) ,.PortBDataOut ( Enve_PortBDataOut ) ); //------------------------------------------------------------------------------------------ // mod nco //------------------------------------------------------------------------------------------ wire [15:0] mod_nco_sin; wire [15:0] mod_nco_cos; NCO_CH1 U_mod_nco ( .clk ( clk ) ,.rstn ( rst_n ) ,.phase_manual_clr ( mod_pha_clr ) ,.phase_auto_clr ( mod_pha_sfot_clr ) ,.fcw ( {mod_nco_fcw,16'h0} ) ,.pha ( mod_nco_pha ) ,.cos ( mod_nco_cos ) ,.sin ( mod_nco_sin ) ); //------------------------------------------------------------------------------------------ // ampmod //------------------------------------------------------------------------------------------ //Config Signal wire Amod_Enable = 1'b1; wire [15 :0] Amod_Data_I ; wire [15 :0] Amod_Data_Q ; wire Amod_Vld ; ampmod U_ampmod ( .Dig_Clk ( clk ) ,.Dig_Resetn ( rst_n ) ,.Mod_Data_I ( enve_idata ) ,.Mod_Data_Q ( enve_qdata ) ,.Mod_Vld ( enve_vld ) ,.Amp ( mod_amp ) ,.Amod_Enable ( Amod_Enable ) ,.Amod_Data_I ( Amod_Data_I ) ,.Amod_Data_Q ( Amod_Data_Q ) ,.Amod_Vld ( Amod_Vld ) ); //------------------------------------------------------------------------------------------ // freqmod //------------------------------------------------------------------------------------------ wire [15:0] fmod_data_i ; wire [15:0] fmod_data_q ; wire fmod_vld ; wire mod_enable = ~(role_sel[1]); wire [15:0] data_i = {16{mod_enable}} & Amod_Data_I ; wire [15:0] data_q = {16{mod_enable}} & Amod_Data_Q ; wire vld = mod_enable & Amod_Vld ; freqmod U_freqmod ( .Dig_Clk ( clk ) ,.Dig_Resetn ( rst_n ) ,.Env_Idata ( data_i ) ,.Env_Qdata ( data_q ) ,.Env_Vld ( vld ) ,.Nco_Sin ( mod_nco_sin ) ,.Nco_Cos ( mod_nco_cos ) ,.Mod_Sideband_Sel ( mod_sideband_sel ) ,.Mod_Enable ( mod_enable ) ,.Mod_Data_I ( fmod_data_i ) ,.Mod_Data_Q ( fmod_data_q ) ,.Mod_Vld ( fmod_vld ) ); //------------------------------------------------------------------------------------------ // baisset //------------------------------------------------------------------------------------------ //Output modem data wire [15:0] Bais_Data_I_i = mod_enable ? fmod_data_i : Amod_Data_I; wire [15:0] Bais_Data_Q_i = mod_enable ? fmod_data_q : Amod_Data_Q; wire Bais_Vld_i = mod_enable ? fmod_vld : Amod_Vld ; wire [15:0] Bais = z_bais ; wire Bais_Enable = role_sel[0] ; wire [15:0] bais_data_i; wire [15:0] bais_data_q; wire [0 :0] bais_data_vld; baisset U_baisset ( .Dig_Clk ( clk ) ,.Dig_Resetn ( rst_n ) ,.Bais_Data_I_i ( Bais_Data_I_i ) ,.Bais_Data_Q_i ( Bais_Data_Q_i ) ,.Bais_Vld_i ( Bais_Vld_i ) ,.Bais ( Bais ) ,.Bais_Enable ( Bais_Enable ) ,.Bais_Data_I_o ( bais_data_i ) ,.Bais_Data_Q_o ( bais_data_q ) ,.Bais_Vld_o ( bais_data_vld ) ,.Bais_I_Ov ( bais_i_ov ) ,.Bais_Q_Ov ( bais_q_ov ) ); modout_mux U_modout_mux ( .clk ( clk ) ,.rst_n ( rst_n ) ,.sel ( mod_dout_sel ) ,.sin ( mod_nco_sin ) ,.cos ( mod_nco_cos ) ,.mod_data_i ( bais_data_i ) ,.mod_data_q ( bais_data_q ) ,.mod_data_vld ( bais_data_vld ) ,.mux_data_i ( awg_data_i ) ,.mux_data_q ( awg_data_q ) ,.mux_data_vld ( awg_vld ) ); endmodule