module TB(); initial begin $fsdbDumpfile("TB1.fsdb"); $fsdbDumpvars(0, TB); //$fsdbDumpMDA(); end reg clk; reg rstn; initial begin #0; rstn = 1'b0; clk = 1'b0; #10; rstn = 1'b1; end always #0.5 clk = ~clk; reg [31:0] cnt; always@(posedge clk or negedge rstn) if(!rstn) cnt <= 32'd0; else cnt <= cnt + 32'd1; initial begin wait(cnt[31]==1'b1) $finish(0); end wire miso; // Spi Miso wire miso_oen; // Spi Miso output enable spi_if dut_if(clk,rstn); /*spi_slave dut( .clk (clk ) ,.rstn (rstn ) ,.sclk (dut_if.sclk ) ,.csn (dut_if.csn ) ,.mosi (dut_if.mosi ) ,.miso (miso ) ,.miso_oen (miso_oen ) ,.error_check (dut_if.error_check ) );//*/ spi_to_sram dut( .clk (clk ) ,.spi_rstn (rstn ) ,.sclk (dut_if.sclk ) ,.csn (dut_if.csn ) ,.mosi (dut_if.mosi ) ,.miso (miso ) ,.miso_oen (miso_oen ) ,.error_check (dut_if.error_check ) ,.addr (mst.addr ) ,.wren (mst.wren ) ,.wrdata (mst.din ) ,.rden (mst.rden ) ,.rddata (mst.dout ) );//*/ reg [4:0] scnt; always@(posedge dut_if.sclk or posedge dut_if.csn) if(dut_if.csn) scnt <= 5'd0; else if(dut_if.csn==1'b0) scnt <= scnt + 5'd1; sram_if#(25,32) mst(clk); sram_if#(25,32) slv[31:0](clk); generate genvar i; for(i=3;i<31;i++) begin: sram spram_model #( .width(32), .depth(1048576) ) sram_block( .clka (clk ) ,.ena (slv[i].wren ) ,.dina (slv[i].din ) ,.addra (slv[i].addr[19:0] ) ,.clkb (clk ) ,.enb (slv[i].rden ) ,.doutb (slv[i].dout ) ,.addrb (slv[i].addr[19:0] ) ); end endgenerate//*/ //*****************************reg_files inst*************************************** //**********************************SYS********************************** sysreg_if sys_if(clk,rstn); system_regfile system_reg_inst( .clk (clk ) ,.rst_n (rstn ) ,.wrdata (slv[0].din ) ,.wren (slv[0].wren ) ,.rwaddr (slv[0].addr[15:0] ) ,.rden (slv[0].rden ) ,.rddata (slv[0].dout ) ,.pll_lock (sys_if.pll_lock ) ,.pll_lost_lock (sys_if.pll_lost_lock ) ,.ch0_dbg_upd (sys_if.ch0_dbg_upd ) ,.ch0_dbg_fifo_e (sys_if.ch0_dbg_fifo_e ) ,.ch0_dbg_fifo_f (sys_if.ch0_dbg_fifo_f ) ,.ch0_ldst_addr_unalgn (sys_if.ch0_ldst_addr_unalgn ) ,.ch0_dec_err (sys_if.ch0_dec_err ) ,.ch0_exit_irq (sys_if.ch0_exit_irq ) ,.ch1_dbg_upd (sys_if.ch1_dbg_upd ) ,.ch1_dbg_fifo_e (sys_if.ch1_dbg_fifo_e ) ,.ch1_dbg_fifo_f (sys_if.ch1_dbg_fifo_f ) ,.ch1_ldst_addr_unalgn (sys_if.ch1_ldst_addr_unalgn ) ,.ch1_dec_err (sys_if.ch1_dec_err ) ,.ch1_exit_irq (sys_if.ch1_exit_irq ) ,.ch2_dbg_upd (sys_if.ch2_dbg_upd ) ,.ch2_dbg_fifo_e (sys_if.ch2_dbg_fifo_e ) ,.ch2_dbg_fifo_f (sys_if.ch2_dbg_fifo_f ) ,.ch2_ldst_addr_unalgn (sys_if.ch2_ldst_addr_unalgn ) ,.ch2_dec_err (sys_if.ch2_dec_err ) ,.ch2_exit_irq (sys_if.ch2_exit_irq ) ,.ch3_dbg_upd (sys_if.ch3_dbg_upd ) ,.ch3_dbg_fifo_e (sys_if.ch3_dbg_fifo_e ) ,.ch3_dbg_fifo_f (sys_if.ch3_dbg_fifo_f ) ,.ch3_ldst_addr_unalgn (sys_if.ch3_ldst_addr_unalgn ) ,.ch3_dec_err (sys_if.ch3_dec_err ) ,.ch3_exit_irq (sys_if.ch3_exit_irq ) ,.sys_soft_rstn (sys_if.soft_rstn[0] ) ,.mcu_soft_rstn (sys_if.soft_rstn[1] ) ,.awg_soft_rstn (sys_if.soft_rstn[2] ) ,.dac_soft_rstn (sys_if.soft_rstn[3] ) ,.irq (sys_if.irq ) ); reg cr; always@(negedge clk or negedge rstn) begin if(!rstn) cr <= 1'b0; else if(cnt=='h3dcd1) cr <= 1; else if(cr) cr <= 0; end //assign sys_if.pll_lock = cr; //assign sys_if.pll_lock = system_reg_inst.icr; //**********************************MCU********************************** //MCU and SPI interface for interaction mcureg_if mcu_if(clk,rstn); wire[31:0] mp[3:0]; reg[31:0] mr; always@(negedge clk or negedge rstn) begin if(!rstn) mr <= 32'b0; else if(cnt=='h124bd) mr <= 32'hffff_ffff; else if(mr) mr <= 0; end //assign mcu_if.mcu_param = {32'b0,mr,32'b0,32'b0};//*/ mcu_regfile mcu_reg_inst( .clk (clk ) ,.rst_n (rstn ) ,.wrdata (slv[1].din ) ,.wren (slv[1].wren ) ,.wrmask (mcu_if.wrmask ) ,.rwaddr (slv[1].addr[15:0] ) ,.rden (slv[1].rden ) ,.rddata (slv[1].dout ) ,.fb_st_info (mcu_if.fb_st_info ) ,.run_time (mcu_if.run_time ) ,.instr_num (mcu_if.instr_num ) ,.mcu_param (mcu_if.mcu_param ) ,.mcu_result (mcu_if.mcu_result ) ,.mcu_cwfr (mcu_if.mcu_cwfr ) ,.mcu_gapr (mcu_if.mcu_gapr ) ,.mcu_ampr (mcu_if.mcu_ampr ) ,.mcu_baisr (mcu_if.mcu_baisr ) ,.mcu_intp_sel (mcu_if.mcu_intp_sel ) ,.mcu_nco_pha_clr (mcu_if.mcu_nco_pha_clr ) ,.mcu_rz_pha (mcu_if.mcu_rz_pha ) );//*/ //**********************************AWG********************************** awgreg_if awg_if(clk,rstn); wire[31:0] ap; reg[31:0] ar; always@(negedge clk or negedge rstn) begin if(!rstn) ar <= 32'b0; else if(cnt=='h456f) ar <= 32'hffff_ffff; else if(ar) ar <= 0; end //assign awg_if.mcu_result2 = ar; awg_regfile awg_reg_inst( .clk (clk ) ,.rst_n (rstn ) ,.wrdata (slv[2].din ) ,.wren (slv[2].wren ) ,.rwaddr (slv[2].addr[15:0] ) ,.rden (slv[2].rden ) ,.rddata (slv[2].dout ) ,.fb_st_i (awg_if.fb_st_i ) ,.run_time (awg_if.run_time ) ,.instr_num (awg_if.instr_num ) ,.mcu_param0 (awg_if.mcu_param0 ) ,.mcu_param1 (awg_if.mcu_param1 ) ,.mcu_param2 (awg_if.mcu_param2 ) ,.mcu_param3 (awg_if.mcu_param3 ) ,.mcu_result0 (awg_if.mcu_result0 ) ,.mcu_result1 (awg_if.mcu_result1 ) ,.mcu_result2 (awg_if.mcu_result2 ) ,.mcu_result3 (awg_if.mcu_result3 ) ,.fb_st_o (awg_if.fb_st_o ) ,.mod_sel_sideband (awg_if.mod_sel_sideband ) ,.qam_nco_clr (awg_if.qam_nco_clr ) ,.qam_fcw (awg_if.qam_fcw ) ,.qam_pha (awg_if.qam_pha ) ,.qam_mod (awg_if.qam_mod ) ,.qam_sel_sideband (awg_if.qam_sel_sideband ) ,.intp_mode (awg_if.intp_mode ) ,.intp_sel (awg_if.intp_sel ) ,.dac_mode_sel (awg_if.dac_mode_sel ) ,.tc_bypass (awg_if.tc_bypass ) ,.tcparr0 (awg_if.tcparr0 ) ,.tcparr1 (awg_if.tcparr1 ) ,.tcparr2 (awg_if.tcparr2 ) ,.tcparr3 (awg_if.tcparr3 ) ,.tcparr4 (awg_if.tcparr4 ) ,.tcparr5 (awg_if.tcparr5 ) ,.tcpbrr0 (awg_if.tcpbrr0 ) ,.tcpbrr1 (awg_if.tcpbrr1 ) ,.tcpbrr2 (awg_if.tcpbrr2 ) ,.tcpbrr3 (awg_if.tcpbrr3 ) ,.tcpbrr4 (awg_if.tcpbrr4 ) ,.tcpbrr5 (awg_if.tcpbrr5 ) ,.tcpair0 (awg_if.tcpair0 ) ,.tcpair1 (awg_if.tcpair1 ) ,.tcpair2 (awg_if.tcpair2 ) ,.tcpair3 (awg_if.tcpair3 ) ,.tcpair4 (awg_if.tcpair4 ) ,.tcpair5 (awg_if.tcpair5 ) ,.tcpbir0 (awg_if.tcpbir0 ) ,.tcpbir1 (awg_if.tcpbir1 ) ,.tcpbir2 (awg_if.tcpbir2 ) ,.tcpbir3 (awg_if.tcpbir3 ) ,.tcpbir4 (awg_if.tcpbir4 ) ,.tcpbir5 (awg_if.tcpbir5 ) ); spi_bus_decoder#(32,1,1) spi_bus_decode_inst( .clk (clk ) ,.rst_n (rstn ) ,.mst (mst.slave ) ,.slv (slv.master ) ); assign dut_if.miso = (miso_oen) ? 1'bz : miso; //case3 test(dut_if,sys_if,mst); //case4 test(dut_if,mcu_if,mst); //case5 test(dut_if,awg_if,mst); case6 test(dut_if,sys_if,mcu_if,awg_if,mst); endmodule