interface sysreg_if(input clk,input rstn); 

//output port
  logic	     	dbg_enable	;
  logic	     	dbg_data_sel;
  logic	[1  :0] dbg_ch_sel 	;//[3:0]
  logic	[32 :0]	status		;
  logic [ 4 :0]	soft_rstn	;
  logic	irq                 ;

  

endinterface : sysreg_if