wire ram_clk = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CLK;
wire ram_cs = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CEBA;
wire reg_clk = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.clk;
wire reg_en = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_wen;
reg ram_cs_dly1 ;
reg reg_en_dly1 ;
always @(posedge ram_clk) begin
    ram_cs_dly1 <= ~ram_cs;
    reg_en_dly1 <= reg_en;
end
reg signed [31:0] data;
int q;
initial begin
    #1ns;
    //@(posedge ram_cs_dly1 );
    #5ns;
    //while(1)begin
        #1ns;
			REGFILE_CHECK(6'd2,32'hffff_ffff);
			for(int j = 1; j < 32; j++) begin
			  $display("* loop[%x]", j);
			  //REGFILE_CHECK(6'd2,j);
			  data = 32'h8000_0000;
			  REGFILE_CHECK(6'd1,32'h8000_0000);
			  if(j == 1) begin
			    q = 32;
			  end
			  else if(j == 2) begin
			    q = 17;
			  end
			  else if(j == 3) begin
			    q = 12;
			  end
			  else if(j == 4) begin
			    q = 9;
			  end
			  else if(j == 5) begin
			    q = 8;
			  end
			  else if(j == 6) begin
			    q = 7;
			  end
			  else if(j == 7) begin
			    q = 6;
			  end
			  else if(j == 8) begin
			    q = 5;
			  end
			  else if(j == 9) begin
			    q = 5;
			  end
			  else if(j == 10) begin
			    q = 5;
			  end
			  else if(j == 11) begin
			    q = 4;
			  end
			  else if(j == 12) begin
			    q = 4;
			  end
			  else if(j == 13) begin
			    q = 4;
			  end
			  else if(j == 15) begin
			    q = 4;
			  end
			  else if(j >= 16 & j < 31) begin
			    q = 3;
			  end
			  else if(j == 31) begin
			    q = 2;
			  end
			  
			  for(int i = 1; i < q; i++) begin
			    REGFILE_CHECK(6'd1,data>>>i*j);
			  end
			end
			REGFILE_CHECK(6'd3,32'hffff_ffff);
    //@(posedge reg_en_dly1 );
            
    #10us;
    TEST_PASS;
end

task DRAM_DATA_CHECK;
    input   [9:0]   addr    ;
    input   [31:0]  edata   ;

    logic   [31:0]  ram_data;

    @(posedge ram_cs_dly1 );
    @(posedge ram_clk );
     //$monitor($time, " Simulation time: %t", $time);
    if(ram_cs_dly1) begin
        ram_data = `TB_DRAM.mem[addr];
        //$display("* RAM_DATA[%x]: %x | EXP_DATA: %x ",addr,ram_data, edata);
        if(ram_data !== edata) begin
            $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,ram_data, edata);
            #1us;
            TEST_FAIL;
        end
        $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, ram_data, edata);
    end
    else begin
            $display("* DRAM CS is High => Error!!!");
            TEST_FAIL;
    end
endtask

task REGFILE_CHECK;
    input   [4:0]   addr    ;
    input   [31:0]  edata   ;

    logic   [31:0]  reg_data;
    @(posedge reg_en );
    @(posedge reg_clk);
    if(reg_en)begin
        reg_data = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_dat;
        if(reg_data !== edata) begin
            $display("* REG_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,reg_data, edata);
            #1us;
            TEST_FAIL;
        end
        $display("* REG_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, reg_data, edata);
    end
    else begin
            $display("* REG WR EN is High => Error!!!");
            TEST_FAIL;
    end

endtask

initial begin
    #10000us;
    $display("\n----------------------------------------\n");
    $display("\t Timeout Error !!!!\n");
    TEST_FAIL;
end