wire ram_clk = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CLK;
wire ram_cs = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CEBA;
wire reg_clk = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.clk;
wire reg_en = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_wen;
reg ram_cs_dly1 ;
reg reg_en_dly1 ;
always @(posedge ram_clk) begin
    ram_cs_dly1 <= ~ram_cs;
    reg_en_dly1 <= reg_en;
end


initial begin
    #1ns;
    //@(posedge ram_cs_dly1 );
    #5ns;
    //while(1)begin
        #1ns;
    //@(posedge reg_en_dly1 );
	        REGFILE_CHECK(6'd2 ,32'h0000_07ff);
			REGFILE_CHECK(6'd3 ,32'hffff_f000);
            REGFILE_CHECK(6'd1 ,32'hffff_f7ff);
			REGFILE_CHECK(6'd1 ,32'hffff_fffe);
			REGFILE_CHECK(6'd1 ,32'hffff_ffff);
            REGFILE_CHECK(6'd2 ,32'hffff_fffe);
			REGFILE_CHECK(6'd3 ,32'hffff_fffe);
			REGFILE_CHECK(6'd4 ,32'hffff_fffe);
			REGFILE_CHECK(6'd5 ,32'hffff_fffe);
			REGFILE_CHECK(6'd6 ,32'hffff_fffe);
			REGFILE_CHECK(6'd7 ,32'hffff_fffe);
			REGFILE_CHECK(6'd8 ,32'hffff_fffe);
			REGFILE_CHECK(6'd9 ,32'hffff_fffe);
			REGFILE_CHECK(6'd10,32'hffff_fffe);
			REGFILE_CHECK(6'd11,32'hffff_fffe);
			REGFILE_CHECK(6'd12,32'hffff_fffe);
			REGFILE_CHECK(6'd13,32'hffff_fffe);
			REGFILE_CHECK(6'd14,32'hffff_fffe);
			REGFILE_CHECK(6'd15,32'hffff_fffe);
			REGFILE_CHECK(6'd16,32'hffff_fffe);
			REGFILE_CHECK(6'd17,32'hffff_fffe);
			REGFILE_CHECK(6'd18,32'hffff_fffe);
			REGFILE_CHECK(6'd19,32'hffff_fffe);
			REGFILE_CHECK(6'd20,32'hffff_fffe);
			REGFILE_CHECK(6'd21,32'hffff_fffe);
			REGFILE_CHECK(6'd22,32'hffff_fffe);
			REGFILE_CHECK(6'd23,32'hffff_fffe);
			REGFILE_CHECK(6'd24,32'hffff_fffe);
			REGFILE_CHECK(6'd25,32'hffff_fffe);
			REGFILE_CHECK(6'd26,32'hffff_fffe);
			REGFILE_CHECK(6'd27,32'hffff_fffe);
			REGFILE_CHECK(6'd28,32'hffff_fffe);
			REGFILE_CHECK(6'd29,32'hffff_fffe);
			REGFILE_CHECK(6'd30,32'hffff_fffe);
			REGFILE_CHECK(6'd31,32'hffff_fffe);
    #10us;
    TEST_PASS;
end

task DRAM_DATA_CHECK;
    input   [9:0]   addr    ;
    input   [31:0]  edata   ;

    logic   [31:0]  ram_data;

    @(posedge ram_cs_dly1 );
    @(posedge ram_clk );
     //$monitor($time, " Simulation time: %t", $time);
    if(ram_cs_dly1) begin
        ram_data = `TB_DRAM.mem[addr];
        //$display("* RAM_DATA[%x]: %x | EXP_DATA: %x ",addr,ram_data, edata);
        if(ram_data !== edata) begin
            $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,ram_data, edata);
            #1us;
            TEST_FAIL;
        end
        $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, ram_data, edata);
    end
    else begin
            $display("* DRAM CS is High => Error!!!");
            TEST_FAIL;
    end
endtask

task REGFILE_CHECK;
    input   [4:0]   addr    ;
    input   [31:0]  edata   ;

    logic   [31:0]  reg_data;
    @(posedge reg_en );
    @(posedge reg_clk);
    if(reg_en)begin
        reg_data = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_dat;
        if(reg_data !== edata) begin
            $display("* REG_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,reg_data, edata);
            #1us;
            //TEST_FAIL;
        end
        $display("* REG_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, reg_data, edata);
    end
    else begin
            $display("* REG WR EN is High => Error!!!");
            //TEST_FAIL;
    end

endtask

initial begin
    #100us;
    $display("\n----------------------------------------\n");
    $display("\t Timeout Error !!!!\n");
    TEST_FAIL;
end