//+FHDR-------------------------------------------------------------------------------------------------------- // Company: //----------------------------------------------------------------------------------------------------------------- // File Name : CHIP_TOP.v // Department : // Author : pwy // Author's Tel : //----------------------------------------------------------------------------------------------------------------- // Relese History // Version Date Author Description // 1.2 2024-04-16 pwy XYZ channel the top-level module //----------------------------------------------------------------------------------------------------------------- // Keywords : // //----------------------------------------------------------------------------------------------------------------- // Parameter // //----------------------------------------------------------------------------------------------------------------- // Purpose : // //----------------------------------------------------------------------------------------------------------------- // Target Device: // Tool versions: //----------------------------------------------------------------------------------------------------------------- // Reuse Issues // Reset Strategy: // Clock Domains: // Critical Timing: // Asynchronous I/F: // Synthesizable (y/n): // Other: //-FHDR------------------------------------------------------------------------------------------------------------ module CHIP_TOP( input sys_clk , input sys_rst_n , output led_test ); //================================================================================= // Parameter declaration //================================================================================= //================================================================================= // Signal declaration //================================================================================= wire clk = sys_clk ; wire rst_n = sys_rst_n ; wire fb_st_in = 2'b10; reg sync_int ; initial begin sync_int = 1'b0; #10000 sync_int = 1'b1; #100 sync_int = 1'b0; end //================================================================================= // Body //================================================================================= //--------------------------------------------------------------------------------------------- // qbmcu instantiation start //--------------------------------------------------------------------------------------------- wire [`QBMCU_PC_SIZE-1 :0] ifu_i_pc_rtvec = 32'h0 ; wire [`QBMCU_PC_SIZE-1 :0] ifu_o_req_pc ; wire ifu_o_req ; wire [`QBMCU_INSTR_SIZE-1:0] ifu_rsp_instr ; wire dec_o_ilegl ; wire agu_o_addr_unalgn ; wire ext_o_send ; wire ext_o_sendc ; wire ext_o_codeword ; wire ext_o_intr ; wire [`QBMCU_ADDR_SIZE-1 :0] agu_o_addr ; wire [`QBMCU_XLEN-1 :0] agu_o_wrdata ; wire agu_o_wren ; wire [`QBMCU_XLEN/8-1 :0] agu_o_wrmask ; wire agu_o_rden ; wire [`QBMCU_XLEN-1 :0] agu_i_rddata ; wire [2 :0] qbmcu_o_fsm_st ; qbmcu U_qbmcu ( .clk ( clk ) ,.rst_n ( rst_n ) ,.qbmcu_i_start ( sync_int ) ,.qbmcu_o_fsm_st ( qbmcu_o_fsm_st ) ,.ifu_i_pc_rtvec ( ifu_i_pc_rtvec ) ,.ifu_o_req_pc ( ifu_o_req_pc ) ,.ifu_o_req ( ifu_o_req ) ,.ifu_rsp_instr ( ifu_rsp_instr ) ,.dec_o_ilegl ( dec_o_ilegl ) ,.agu_o_addr ( agu_o_addr ) ,.agu_o_wrdata ( agu_o_wrdata ) ,.agu_o_wren ( agu_o_wren ) ,.agu_o_wrmask ( agu_o_wrmask ) ,.agu_o_rden ( agu_o_rden ) ,.agu_i_rddata ( agu_i_rddata ) ,.agu_o_addr_unalgn ( agu_o_addr_unalgn ) ,.ext_o_send ( ext_o_send ) ,.ext_o_sendc ( ext_o_sendc ) ,.ext_o_codeword ( ext_o_codeword ) ,.ext_o_intr ( ext_o_intr ) ); //--------------------------------------------------------------------------------------------- // qbmcu instantiation end //--------------------------------------------------------------------------------------------- //--------------------------------------------------------------------------------------------- // MCU runtime counter instantiation start //--------------------------------------------------------------------------------------------- defparam qbmcu_runtime.width = 32; //MCU runtime wire [31 :0] run_time ; DW03_updn_ctr qbmcu_runtime ( .clk ( clk ) // clock input ,.reset ( rst_n ) // asynchronous reset input (active low) ,.data ( 32'd0 ) // data used for load operation ,.up_dn ( 1'b1 ) // up/down control input (0=down, 1-up) ,.load ( ~sync_int ) // load operation control input (active low) ,.cen ( |qbmcu_o_fsm_st ) // count enable control input (active high enable) ,.count ( run_time ) // count value output ,.tercnt ( ) // terminal count output flag (active high) ); //--------------------------------------------------------------------------------------------- // MCU runtime counter instantiation end //--------------------------------------------------------------------------------------------- //--------------------------------------------------------------------------------------------- // fetch instructions number counter instantiation start //--------------------------------------------------------------------------------------------- defparam instr_num.width = 32; //Count the number of fetch instructions wire [31 :0] run_instr_num ; DW03_updn_ctr instr_num ( .clk ( clk ) // clock input ,.reset ( rst_n ) // asynchronous reset input (active low) ,.data ( 32'd0 ) // data used for load operation ,.up_dn ( 1'b1 ) // up/down control input (0=down, 1-up) ,.load ( ~sync_int ) // load operation control input (active low) ,.cen ( ifu_o_req ) // count enable control input (active high enable) ,.count ( run_instr_num ) // count value output ,.tercnt ( ) // terminal count output flag (active high) ); //--------------------------------------------------------------------------------------------- // fetch instructions number counter instantiation end //--------------------------------------------------------------------------------------------- //--------------------------------------------------------------------------------------------- // qbmcu_busdecoder instantiation start //--------------------------------------------------------------------------------------------- wire [`QBMCU_ADDR_SIZE-1 :0] dsram_o_rwaddr ; wire [`QBMCU_XLEN-1 :0] dsram_o_wrdata ; wire dsram_o_wren ; wire [`QBMCU_XLEN/8-1 :0] dsram_o_wrmask ; wire dsram_o_rden ; wire [`QBMCU_XLEN-1 :0] dsram_i_rddata ; wire [`QBMCU_ADDR_SIZE-1 :0] preg_o_rwaddr ; wire [`QBMCU_XLEN-1 :0] preg_o_wrdata ; wire preg_o_wren ; wire [`QBMCU_XLEN/8-1 :0] preg_o_wrmask ; wire preg_o_rden ; wire [`QBMCU_XLEN-1 :0] preg_i_rddata ; qbmcu_busdecoder #( .S0_BASEADDR ( 32'h0010_0000 ) ,.S1_BASEADDR ( 32'h0020_0000 ) )U_qbmcu_busdecoder ( .wren ( agu_o_wren ) ,.wrmask ( agu_o_wrmask ) ,.wrdata ( agu_o_wrdata ) ,.rwaddr ( agu_o_addr ) ,.rden ( agu_o_rden ) ,.rddata ( agu_i_rddata ) ,.s0_wren ( dsram_o_wren ) ,.s0_wrmask ( dsram_o_wrmask ) ,.s0_rwaddr ( dsram_o_rwaddr ) ,.s0_wrdata ( dsram_o_wrdata ) ,.s0_rden ( dsram_o_rden ) ,.s0_rddata ( dsram_i_rddata ) ,.s1_wren ( preg_o_wren ) ,.s1_wrmask ( preg_o_wrmask ) ,.s1_rwaddr ( preg_o_rwaddr ) ,.s1_wrdata ( preg_o_wrdata ) ,.s1_rden ( preg_o_rden ) ,.s1_rddata ( preg_i_rddata ) ); //--------------------------------------------------------------------------------------------- // qbmcu_busdecoder instantiation end //--------------------------------------------------------------------------------------------- //--------------------------------------------------------------------------------------------- // mcu_regfile instantiation start //--------------------------------------------------------------------------------------------- //MCU and SPI interface for interaction wire [31 :0] mcu_param [3:0] ; // MCU parameter 0~3 wire [31 :0] mcu_result [3:0] ; // MCU result 0~3 //lookup table data ; wire [31 :0] mcu_cwfr [3:0] ; // Carrier frequency ctrl word 0~3 wire [15 :0] mcu_gapr [7:0] ; // Carrier phase ctrl word 0~3 wire [15 :0] mcu_ampr [3:0] ; // Carrier Amplitude 0~3 wire [15 :0] mcu_baisr [3:0] ; // Carrier Bais 0~3 //CFG Port wire [1 :0] mcu_intp_sel ; //2'b00:HBF;2'b01:Nearest-neighbor interpolator; wire mcu_nco_pha_clr ; wire [15 :0] mcu_rz_pha ; mcu_regfile U_mcu_regfile ( .clk ( clk ) ,.rst_n ( rst_n ) ,.rwaddr ( preg_o_rwaddr ) ,.wrdata ( preg_o_wrdata ) ,.wren ( preg_o_wren ) ,.wrmask ( preg_o_wrmask ) ,.rden ( preg_o_rden ) ,.rddata ( preg_i_rddata ) ,.fb_st_info ( fb_st_in ) ,.run_time ( run_time ) ,.instr_num ( run_instr_num ) ,.mcu_param ( mcu_param ) ,.mcu_result ( mcu_result ) ,.mcu_cwfr ( mcu_cwfr ) ,.mcu_gapr ( mcu_gapr ) ,.mcu_ampr ( mcu_ampr ) ,.mcu_baisr ( mcu_baisr ) ,.mcu_intp_sel ( mcu_intp_sel ) ,.mcu_nco_pha_clr ( mcu_nco_pha_clr ) ,.mcu_rz_pha ( mcu_rz_pha ) ); //--------------------------------------------------------------------------------------------- // mcu_regfile instantiation end //--------------------------------------------------------------------------------------------- //--------------------------------------------------------------------------------------------- // U_ITCM instantiation start //--------------------------------------------------------------------------------------------- dpram #( .DATAWIDTH ( 32 ) ,.ADDRWIDTH ( 15 ) ) U_ITCM ( .PortClk ( clk ) ,.PortAAddr ( ifu_o_req_pc[`QBMCU_ITCM_ADDR_SIZE-1:0] ) ,.PortADataIn ( 32'b0 ) ,.PortAWriteEnable ( 1'b1 ) ,.PortAChipEnable ( ~ifu_o_req ) ,.PortAByteWriteEnable ( 4'b0 ) ,.PortADataOut ( ifu_rsp_instr ) ,.PortBAddr ( `QBMCU_ITCM_ADDR_SIZE'b0 ) ,.PortBDataIn ( 32'b0 ) ,.PortBWriteEnable ( 1'b1 ) ,.PortBChipEnable ( 1'b0 ) ,.PortBByteWriteEnable ( 4'b0 ) ,.PortBDataOut ( ) ); //--------------------------------------------------------------------------------------------- // U_ITCM instantiation end //--------------------------------------------------------------------------------------------- //////////////////////////////////////////////////////////////////////////////////////////////////////////// //DTCM //////////////////////////////////////////////////////////////////////////////////////////////////////////// dpram #( .DATAWIDTH ( 32 ) ,.ADDRWIDTH ( 15 ) ) U_DTCM ( .PortClk ( clk ) ,.PortAAddr ( dsram_o_rwaddr[`QBMCU_DTCM_ADDR_SIZE-1:0] ) ,.PortADataIn ( dsram_o_wrdata ) ,.PortAWriteEnable ( ~dsram_o_wren ) ,.PortAChipEnable ( ~(dsram_o_rden | dsram_o_wren) ) ,.PortAByteWriteEnable ( ~dsram_o_wrmask ) ,.PortADataOut ( dsram_i_rddata ) ,.PortBAddr ( `QBMCU_ITCM_ADDR_SIZE'b0 ) ,.PortBDataIn ( 32'b0 ) ,.PortBWriteEnable ( 1'b1 ) ,.PortBChipEnable ( 1'b0 ) ,.PortBByteWriteEnable ( 4'b0 ) ,.PortBDataOut ( ) ); endmodule