interface pllreg_if(input clk,input rstn); 

  //input port
   logic  [31 :0] wrdata          // write data
  ;logic          wren            // write enable
  ;logic  [15 :0] rwaddr          // read & write address
  ;logic          rden            // read enable
  ;logic          pll_lock        // PLL LOCK

  //output port
  ;logic [31 :0] rddata          // read data
  
  ;logic         ref_sel         // Clock source selection for a frequency divider; 
                                  // 1'b0:External clock source
								  // 1'b1:internal phase-locked loop clock source
  ;logic         ref_en          // logic reference clock enable
                                  // 1'b0:enable;1'b1:disable
  ;logic         ref_s2d_en      // Referenced clock differential to single-ended conversion enable
                                  // 1'b0:enable;1'b1:disable
  ;logic [6  :0] p_cnt           // P counter
  ;logic         pfd_delay       // PFD Dead Zone
  ;logic         pfd_dff_Set     // Setting the PFD register;active high
  ;logic         pfd_dff_4and    // PFD logic polarity
  ;logic [3  :0] spd_div         // SPD Frequency Divider
  ;logic         spd_pulse_width // Pulse Width of SPD
  ;logic         spd_pulse_sw    // Pulse sw of SPD
  ;logic         cpc_sel         // current source selection
  ;logic [1  :0] swcp_i          // PTAT current switch
  ;logic [3  :0] sw_ptat_r       // PTAT current adjustment
  ;logic [1  :0] sw_fll_cpi      // Phase-locked loop charge pump current
  ;logic         sw_fll_delay    // PLL Dead Zone
  ;logic         pfd_sel         // PFD Loop selection
  ;logic         spd_sel         // SPD Loop selection
  ;logic         fll_sel         // FLL Loop selection
  ;logic         vco_tc          // VCO temperature compensation
  ;logic         vco_tcr         // VCO temperature compensation resistor
  ;logic         vco_gain_adj    // VCO gain adjustment
  ;logic         vco_gain_adj_r  // VCO gain adjustment resistor
  ;logic [2  :0] vco_cur_adj     // VCO current adjustment
  ;logic         vco_buff_en     // VCO buff enable;active high
  ;logic         vco_en          // VCO enable;active high
  ;logic [2  :0] pll_dpwr_adj    // PLL frequency division logic power adjustment
  ;logic [6  :0] vco_fb_adj      // VCO frequency band adjustment
  ;logic         afc_en          // AFC enable
  ;logic         afc_shutdown    // AFC module shutdown signal
  ;logic [0  :0] afc_det_speed   // AFC detection speed 
  ;logic [0  :0] flag_out_sel    // Read and choose the signs
  ;logic         afc_reset       // AFC reset
  ;logic [10 :0] afc_cnt         // AFC frequency band adjustment function counter 
                                  // counting time adjustment
  ;logic [10 :0] afc_ld_cnt      // Adjust the counting time of the AFC lock detection 
                                  // feature counter							  
  ;logic [3  :0] afc_pres        // Adjusting the resolution of the AFC comparator
  ;logic [14 :0] afc_ld_tcc      // AFC Lock Detection Function Target Cycle Count
  ;logic [14 :0] afc_fb_tcc      // Target number of cycles for AFC frequency band 
                                  // adjustment function
  ;logic [0  :0] div_rstn_sel    // div rstn select, 1'b0: ext clear, 1'b1:inter pll lock
  ;logic [1  :0] test_clk_sel    // test clk select, 2'b00:DIV1 clk, 2'b01:DIV2 clk, 2'b10:DIV4 clk, 2'b11:DIV8 clk
  ;logic [0  :0] test_clk_oen    // test clk output enable, 1'b0:disenable, 1'b1:enable
  ;logic [7  :0] dig_clk_sel     // digital main clk select, one hot code,bit[0]-->0 degree phase,bit[1]-->45 degree phase.....bit[7]-->315degree  phae 
  ;logic [0  :0] div_sync_en     // Frequency Divider Synchronous Clear Enable
  ;logic         sync_oe;



  

endinterface : pllreg_if