//For mcu_regfile, the ROreg: mcu_para/rtimr/icntr/fsir are updated by the inputs //at this clk_posedge due to dff(inputs->regs) class mcu_refmodel; virtual mcureg_if mif; virtual spi_if wif; virtual sram_if#(25,32) xif; //poor-quality register model bit[31:0] rm[42]; //members to be sent to scoreboard int rst_error[5]; bit[31:0] dout[$]; mcureg_trans mcuout[$]; function new(); endfunction extern task do_imitate(); extern task RWreg_write (bit[24:0] addr,bit[32:0] din ); extern task ROreg_update (bit[24:0] addr ); extern task reg_read (bit[24:0] addr ); extern task output_trace (bit[24:0] addr ); endclass : mcu_refmodel task mcu_refmodel::do_imitate(); int i=0,j=0; rm[ 0] = 32'h0; //MCUPARAR0 rm[ 1] = 32'h0; //MCUPARAR1 rm[ 2] = 32'h0; //MCUPARAR2 rm[ 3] = 32'h0; //MCUPARAR3 rm[ 4] = 32'h0; //MCURESR0 rm[ 5] = 32'h0; //MCURESR1 rm[ 6] = 32'h0; //MCURESR2 rm[ 7] = 32'h0; //MCURESR3 rm[16] = 32'h0; //CWFR0 rm[17] = 32'h0; //CWFR1 rm[18] = 32'h0; //CWFR2 rm[19] = 32'h0; //CWFR3 rm[20] = 32'h0; //CWPRR rm[21] = 32'h0; //GAPR0 rm[22] = 32'h0; //GAPR1 rm[23] = 32'h0; //GAPR2 rm[24] = 32'h0; //GAPR3 rm[25] = 32'h0; //GAPR4 rm[26] = 32'h0; //GAPR5 rm[27] = 32'h0; //GAPR6 rm[28] = 32'h0; //GAPR7 rm[29] = 32'h0; //LCPR rm[30] = 32'h0; //AMPR0 rm[31] = 32'h0; //AMPR1 rm[32] = 32'h0; //AMPR2 rm[33] = 32'h0; //AMPR3 rm[34] = 32'h0; //BIASR0 rm[35] = 32'h0; //BIASR1 rm[36] = 32'h0; //BIASR2 rm[37] = 32'h0; //BIASR3 rm[38] = 32'h0; //RTIMR rm[39] = 32'h0; //ICNTR rm[40] = 32'h0; //FSIR rm[41] = 32'h0; //INTPSELR fork while(1) begin: write_reg_RW @(negedge xif.wren); RWreg_write(xif.addr,xif.din); end: write_reg_RW while(1) begin: update_reg_RO @(negedge xif.rden); ROreg_update(xif.addr); end: update_reg_RO while(1) begin: read_reg @(negedge xif.rden); reg_read(xif.addr); end: read_reg while(1) begin: output_port @(negedge xif.wren); output_trace(xif.addr); end: output_port join endtask: do_imitate task mcu_refmodel::RWreg_write(bit[24:0] addr,bit[32:0] din); bit[31:0] wrmask; //make mask into 32bit wrmask = {{8{mif.wrmask[3]}},{8{mif.wrmask[2]}},{8{mif.wrmask[1]}},{8{mif.wrmask[0]}}}; //delay caused by decoder @(posedge wif.clk); case(addr[24: 2]) 23'h1C0004: rm[ 4] = wrmask ? din : rm[ 4]; //MCURESR0 23'h1C0005: rm[ 5] = wrmask ? din : rm[ 5]; //MCURESR1 23'h1C0006: rm[ 6] = wrmask ? din : rm[ 6]; //MCURESR2 23'h1C0007: rm[ 7] = wrmask ? din : rm[ 7]; //MCURESR3 23'h1C0010: rm[16] = wrmask ? din : rm[16]; //CWFR0 23'h1C0011: rm[17] = wrmask ? din : rm[17]; //CWFR1 23'h1C0012: rm[18] = wrmask ? din : rm[18]; //CWFR2 23'h1C0013: rm[19] = wrmask ? din : rm[19]; //CWFR3 23'h1C0014: rm[20] = wrmask[0 : 0] ? {din[0 : 0],rm[20][31: 1]} : rm[20]; //CWPRR 23'h1C0015: rm[21] = wrmask[31:16] ? {din[31:16],rm[21][31:16]} : rm[21]; //GAPR0 23'h1C0016: rm[22] = wrmask[31:16] ? {din[31:16],rm[22][31:16]} : rm[22]; //GAPR1 23'h1C0017: rm[23] = wrmask[31:16] ? {din[31:16],rm[23][31:16]} : rm[23]; //GAPR2 23'h1C0018: rm[24] = wrmask[31:16] ? {din[31:16],rm[24][31:16]} : rm[24]; //GAPR3 23'h1C0019: rm[25] = wrmask[31:16] ? {din[31:16],rm[25][31:16]} : rm[25]; //GAPR4 23'h1C001a: rm[26] = wrmask[31:16] ? {din[31:16],rm[26][31:16]} : rm[26]; //GAPR5 23'h1C001b: rm[27] = wrmask[31:16] ? {din[31:16],rm[27][31:16]} : rm[27]; //GAPR6 23'h1C001c: rm[28] = wrmask[31:16] ? {din[31:16],rm[28][31:16]} : rm[28]; //GAPR7 23'h1C001d: rm[29] = wrmask[31:16] ? {din[31:16],rm[29][31:16]} : rm[29]; //LCPR 23'h1C001e: rm[30] = wrmask[31:16] ? {din[31:16],rm[30][31:16]} : rm[30]; //AMPR0 23'h1C001f: rm[31] = wrmask[31:16] ? {din[31:16],rm[31][31:16]} : rm[31]; //AMPR1 23'h1C0020: rm[32] = wrmask[31:16] ? {din[31:16],rm[32][31:16]} : rm[32]; //AMPR2 23'h1C0021: rm[33] = wrmask[31:16] ? {din[31:16],rm[33][31:16]} : rm[33]; //AMPR3 23'h1C0022: rm[34] = wrmask[31:16] ? {din[31:16],rm[34][31:16]} : rm[34]; //BIASR0 23'h1C0023: rm[35] = wrmask[31:16] ? {din[31:16],rm[35][31:16]} : rm[35]; //BIASR1 23'h1C0024: rm[36] = wrmask[31:16] ? {din[31:16],rm[36][31:16]} : rm[36]; //BIASR2 23'h1C0025: rm[37] = wrmask[31:16] ? {din[31:16],rm[37][31:16]} : rm[37]; //BIASR3 23'h1C0029: rm[41] = wrmask[1 : 0] ? {rm[37][31:2 ],din[1 : 0]} : rm[41]; //INTPSELR endcase @(posedge wif.clk); case(addr[24: 2]) 23'h04_0014: rm[12] = 32'b0; endcase /* $display("mask:%h",wrmask); $display("addr:%0h",addr); $display("rm[%d]:%h",addr[15:2],rm[addr[15: 2]]); $display("din:%h",din);//*/ endtask: RWreg_write task mcu_refmodel::ROreg_update(bit[24:0] addr); //@(posedge wif.clk); rm[ 0] = mif.mcu_param[0]; //MCUPARAR0 rm[ 1] = mif.mcu_param[1]; //MCUPARAR1 rm[ 2] = mif.mcu_param[2]; //MCUPARAR2 rm[ 3] = mif.mcu_param[3]; //MCUPARAR3 rm[38] = mif.run_time ; //RTIMR rm[39] = mif.instr_num ; //ICNTR rm[40] = {rm[32][31:2],mif.fb_st_info[1:0]}; //FSIR endtask: ROreg_update task mcu_refmodel::reg_read(bit[24:0] addr); //delay caused be decoder //@(posedge wif.clk); case(addr[24: 2]) 23'h1C0000: dout.push_back(rm[ 0]); //MCUPARAR0 23'h1C0001: dout.push_back(rm[ 1]); //MCUPARAR1 23'h1C0002: dout.push_back(rm[ 2]); //MCUPARAR2 23'h1C0003: dout.push_back(rm[ 3]); //MCUPARAR3 23'h1C0004: dout.push_back(rm[ 4]); //MCURESR0 23'h1C0005: dout.push_back(rm[ 5]); //MCURESR1 23'h1C0006: dout.push_back(rm[ 6]); //MCURESR2 23'h1C0007: dout.push_back(rm[ 7]); //MCURESR3 23'h1C0008: dout.push_back(32'b0) ; 23'h1C0010: dout.push_back(rm[16]); //CWFR0 23'h1C0011: dout.push_back(rm[17]); //CWFR1 23'h1C0012: dout.push_back(rm[18]); //CWFR2 23'h1C0013: dout.push_back(rm[19]); //CWFR3 23'h1C0014: dout.push_back(rm[20]); //CWPRR 23'h1C0015: dout.push_back(rm[21]); //GAPR0 23'h1C0016: dout.push_back(rm[22]); //GAPR1 23'h1C0017: dout.push_back(rm[23]); //GAPR2 23'h1C0018: dout.push_back(rm[24]); //GAPR3 23'h1C0019: dout.push_back(rm[25]); //GAPR4 23'h1C001a: dout.push_back(rm[26]); //GAPR5 23'h1C001b: dout.push_back(rm[27]); //GAPR6 23'h1C001c: dout.push_back(rm[28]); //GAPR7 23'h1C001d: dout.push_back(rm[29]); //LCPR 23'h1C001e: dout.push_back(rm[30]); //AMPR0 23'h1C001f: dout.push_back(rm[31]); //AMPR1 23'h1C0020: dout.push_back(rm[32]); //AMPR2 23'h1C0021: dout.push_back(rm[33]); //AMPR3 23'h1C0022: dout.push_back(rm[34]); //BIASR0 23'h1C0023: dout.push_back(rm[35]); //BIASR1 23'h1C0024: dout.push_back(rm[36]); //BIASR2 23'h1C0025: dout.push_back(rm[37]); //BIASR3 23'h1C0026: dout.push_back(rm[38]); //RTIMR 23'h1C0027: dout.push_back(rm[39]); //ICNTR 23'h1C0028: dout.push_back(rm[40]); //FSIR 23'h1C0029: dout.push_back(rm[41]); //INTPSELR 23'h1C002a: dout.push_back(32'b0) ; endcase // $display("dout:%h",dout[$]); endtask: reg_read task mcu_refmodel::output_trace(bit[24:0] addr); mcureg_trans tr_temp; //delay caused by decoder @(posedge wif.clk); @(negedge wif.clk); tr_temp = new(); if(addr[24:20] == 5'h7) begin tr_temp.mcu_result[0] = rm[ 4] ; //MCURESR0 tr_temp.mcu_result[1] = rm[ 5] ; //MCURESR1 tr_temp.mcu_result[2] = rm[ 6] ; //MCURESR2 tr_temp.mcu_result[3] = rm[ 7] ; //MCURESR3 tr_temp.mcu_cwfr[0] = rm[16] ; //CWFR0 tr_temp.mcu_cwfr[1] = rm[17] ; //CWFR1 tr_temp.mcu_cwfr[2] = rm[18] ; //CWFR2 tr_temp.mcu_cwfr[3] = rm[19] ; //CWFR3 tr_temp.mcu_nco_pha_clr = rm[20][0 : 0]; //CWPRR tr_temp.mcu_gapr[0] = rm[21][31:16]; //GAPR0 tr_temp.mcu_gapr[1] = rm[22][31:16]; //GAPR1 tr_temp.mcu_gapr[2] = rm[23][31:16]; //GAPR2 tr_temp.mcu_gapr[3] = rm[24][31:16]; //GAPR3 tr_temp.mcu_gapr[4] = rm[25][31:16]; //GAPR4 tr_temp.mcu_gapr[5] = rm[26][31:16]; //GAPR5 tr_temp.mcu_gapr[6] = rm[27][31:16]; //GAPR6 tr_temp.mcu_gapr[7] = rm[28][31:16]; //GAPR7 tr_temp.mcu_rz_pha = rm[29][15: 0]; //LCPR tr_temp.mcu_ampr[0] = rm[30][31:16]; //AMPR0 tr_temp.mcu_ampr[1] = rm[31][31:16]; //AMPR1 tr_temp.mcu_ampr[2] = rm[32][31:16]; //AMPR2 tr_temp.mcu_ampr[3] = rm[33][31:16]; //AMPR3 tr_temp.mcu_baisr[0] = rm[34][31:16]; //BIASR0 tr_temp.mcu_baisr[1] = rm[35][31:16]; //BIASR1 tr_temp.mcu_baisr[2] = rm[36][31:16]; //BIASR2 tr_temp.mcu_baisr[3] = rm[37][31:16]; //BIASR3 tr_temp.mcu_intp_sel = rm[38][1 : 0]; //INTPSELR mcuout.push_back(tr_temp); end //$display("addr:%0h",addr); //$display("rm:",rm); //$display("din:%h",din); endtask: output_trace