{
    "tsdn28hpcpuhdb4096x32m4mw_170a": [
        "tsdn28hpcpuhdb4096x32m4mw_170a",
        "d6TPd",
        "module",
        14
    ],
    "tsdn28hpcpuhdb128x128m4mw_170a_Int_Array": [
        "tsdn28hpcpuhdb128x128m4mw_170a_Int_Array",
        "eFLuy",
        "module",
        13
    ],
    "_vcs_unit__3598111382": [
        "_vcs_unit__3598111382",
        "QyjH7",
        "module",
        1
    ],
    "std": [
        "std",
        "reYIK",
        "module",
        2
    ],
    "tsdn28hpcpuhdb64x32m4mw_170a_Int_Array": [
        "tsdn28hpcpuhdb64x32m4mw_170a_Int_Array",
        "JweIx",
        "module",
        16
    ],
    "tsdn28hpcpuhdb4096x32m4mw_170a_Int_Array": [
        "tsdn28hpcpuhdb4096x32m4mw_170a_Int_Array",
        "ay4xz",
        "module",
        15
    ],
    "sram_if": [
        "sram_if",
        "NABmh",
        "module",
        3
    ],
    "DUC_HB2": [
        "DUC_HB2",
        "ksFw4",
        "module",
        30
    ],
    "modout_mux": [
        "modout_mux",
        "jEu9i",
        "module",
        7
    ],
    "spi_if": [
        "spi_if",
        "IHYdB",
        "module",
        42
    ],
    "qbmcu_datalatch": [
        "qbmcu_datalatch",
        "MsCBG",
        "module",
        21
    ],
    "sirv_gnrl_dffl": [
        "sirv_gnrl_dffl",
        "BM4bj",
        "module",
        8
    ],
    "sram_if_0000": [
        "sram_if_0000",
        "nJgqZ",
        "module",
        4
    ],
    "DAC_DEM_4": [
        "DAC_DEM_4",
        "WqW9L",
        "module",
        36
    ],
    "tsdn28hpcpuhdb128x128m4mw_170a": [
        "tsdn28hpcpuhdb128x128m4mw_170a",
        "rShyv",
        "module",
        12
    ],
    "ctrl_regfile": [
        "ctrl_regfile",
        "mLA3J",
        "module",
        5
    ],
    "xyz_chip_top": [
        "xyz_chip_top",
        "VHUBa",
        "module",
        27
    ],
    "param_lut_0002": [
        "param_lut_0002",
        "nJN5E",
        "module",
        6
    ],
    "sirv_gnrl_ltch": [
        "sirv_gnrl_ltch",
        "UTi0b",
        "module",
        9
    ],
    "PH2AMP": [
        "PH2AMP",
        "iYIEc",
        "module",
        17
    ],
    "dacif": [
        "dacif",
        "SMgga",
        "module",
        28
    ],
    "qbmcu_regfile_0000": [
        "qbmcu_regfile_0000",
        "Hit7c",
        "module",
        22
    ],
    "dac_regfile": [
        "dac_regfile",
        "LR0zI",
        "module",
        10
    ],
    "debug_top": [
        "debug_top",
        "gNaPt",
        "module",
        11
    ],
    "mcu_regfile": [
        "mcu_regfile",
        "HWLgR",
        "module",
        18
    ],
    "TB": [
        "TB",
        "sH4Fc",
        "module",
        37
    ],
    "DUC_HB4": [
        "DUC_HB4",
        "zwWSN",
        "module",
        32
    ],
    "thermo2binary_top": [
        "thermo2binary_top",
        "N7Gsb",
        "module",
        43
    ],
    "qbmcu_busdecoder": [
        "qbmcu_busdecoder",
        "jAiwN",
        "module",
        19
    ],
    "xy_dsp": [
        "xy_dsp",
        "U33JQ",
        "module",
        29
    ],
    "qbmcu": [
        "qbmcu",
        "xnbfb",
        "module",
        20
    ],
    "rst_gen_unit": [
        "rst_gen_unit",
        "anuMN",
        "module",
        23
    ],
    "spi_slave": [
        "spi_slave",
        "eAsJz",
        "module",
        24
    ],
    "system_regfile": [
        "system_regfile",
        "W3x1b",
        "module",
        25
    ],
    "channel_top": [
        "channel_top",
        "xFWdC",
        "module",
        26
    ],
    "DUC_HB3": [
        "DUC_HB3",
        "Rdd8k",
        "module",
        31
    ],
    "DUC4": [
        "DUC4",
        "cwtAY",
        "module",
        33
    ],
    "DAC_DEM": [
        "DAC_DEM",
        "brTVz",
        "module",
        34
    ],
    "DAC_DEM_16": [
        "DAC_DEM_16",
        "gcyA4",
        "module",
        35
    ],
    "DW_mult_pipe_0000_0000": [
        "DW_mult_pipe_0000_0000",
        "HNRiG",
        "module",
        38
    ],
    "DW_mult_pipe_0000_0002": [
        "DW_mult_pipe_0000_0002",
        "SiiVi",
        "module",
        39
    ],
    "DW01_addsub": [
        "DW01_addsub",
        "KysYq",
        "module",
        41
    ],
    "...MASTER...": [
        "SIM",
        "amcQw",
        "module",
        44
    ]
}