`timescale 1ns/1ps
//`define FPGA_TEST
//`define SRAM32KB_FILENAME "./mcu.cde"
//`define AHB_RAM_SMIC_MODEL
//`define AHB_RAM_FPGA_SRAM_MODEL
//`define AHB_ROM_SMIC_MODEL_16KB
//`define AHB_ROM_SMIC_MODEL_8KB
//`define SMIC_PAD
// `define FPGA_PAD
//`include "qbmcu_defines.v"
module TB;

//======================================================================
initial begin
  $fsdbAutoSwitchDumpfile(500, "./verdplus.fsdb", 1000000);
  $fsdbDumpvars();
end 
//======================================================================
//clock & reset & bootsel
//======================================================================
logic       clk           ;
logic       rst_n         ;
logic       qbmcu_i_start ;
parameter SYS_PERIOD = 1.33;
//sys_clk --> 50M, 0 phase
initial begin
  clk  =0;
  forever # (SYS_PERIOD/2) clk = ~clk;
end 


//hresetn
initial begin
  rst_n = 0;
  #1000;
  rst_n = 0;
  #1000;
  rst_n = 1;
 // $display("m%");
end

logic  [31:0]  mcu_cwfr    [3:0]   ;               
logic  [31:0]  mcu_gapr    [7:0]   ;             
logic  [31:0]  mcu_ampr    [3:0]   ;             
logic  [31:0]  mcu_baisr   [3:0]   ;             
logic  [1 :0]  mcu_intp_sel        ;          
logic          mcu_nco_pha_clr     ;
logic  [15:0]  mcu_rz_pha          ;
logic          send                ;
logic          sendc               ;
logic  [31 :0] codeword            ;
logic  [1  :0] fb_st               ;
logic  [31 :0] enve_bwrdata        ;
logic  [0  :0] enve_bwren          ;
logic  [24 :0] enve_brwaddr        ;
logic  [0  :0] enve_brden  = 1'b0  ;
logic  [31 :0] enve_brddata        ;
logic  [31 :0] enve_id_bwrdata     ;
logic  [0  :0] enve_id_bwren       ;
logic  [24 :0] enve_id_brwaddr     ;
logic  [0  :0] enve_id_brden = 1'b0;
logic  [31 :0] enve_id_brddata     ;
logic  [0  :0] enve_read_fsm_st    ;
logic          proc_cft            ;
logic          mod_sideband_sel    ;
logic          mod_pha_sfot_clr    ;
logic  [1  :0] role_sel            ;
logic  [1  :0] intp_sel            ;
logic  [15 :0] mod_data_i          ;
logic  [15 :0] mod_data_q          ;
logic          mod_vld             ;

/////////////////////////////////////////////////////////////////////////////////////
//mcu_cwfr
assign mcu_cwfr[0] = 32'h1000_0000;
assign mcu_cwfr[1] = 32'h0800_0000;
assign mcu_cwfr[2] = 32'h0400_0000;
assign mcu_cwfr[3] = 32'h0200_0000;
//mcu_gapr
assign mcu_gapr[0] = 16'h0000;
assign mcu_gapr[1] = 16'h0800;
assign mcu_gapr[2] = 16'h0400;
assign mcu_gapr[3] = 16'h0200;
assign mcu_gapr[4] = 16'h1000;
assign mcu_gapr[5] = 16'h0800;
assign mcu_gapr[6] = 16'h0400;
assign mcu_gapr[7] = 16'h0200;
//mcu_ampr
assign mcu_ampr[0] = 16'hf000;
assign mcu_ampr[1] = 16'h8000;
assign mcu_ampr[2] = 16'h4000;
assign mcu_ampr[3] = 16'h2000;
//mcu_baisr
assign mcu_baisr[0] = 16'h0100;
assign mcu_baisr[1] = 16'h0200;
assign mcu_baisr[2] = 16'h0300;
assign mcu_baisr[3] = 16'h0400;




always @(posedge clk or negedge rst_n) begin
  if(!rst_n) begin
    enve_bwrdata  <= '0;
	enve_bwren    <= '0;
	enve_brwaddr  <= '0;
  end
  else begin
    if(enve_bwrdata == 32'd8191) begin
	  enve_bwrdata  <= enve_bwrdata;
	  enve_bwren    <= '0;
	  enve_brwaddr  <= enve_brwaddr;
	end
	else begin
	  enve_bwrdata  <= enve_bwrdata + 1'b1;
	  enve_bwren    <= '1;
	  enve_brwaddr  <= {enve_bwrdata[11:2],2'b00};
	end
  end
end


always @(posedge clk or negedge rst_n) begin
  if(!rst_n) begin
    enve_id_bwrdata  <= {16'd0,16'd20};
	enve_id_bwren    <= '0;
	enve_id_brwaddr  <= '0;
  end
  else begin
    if(enve_id_brwaddr[7:2] == 6'd63) begin
	  enve_id_bwrdata  <= enve_id_bwrdata;
	  enve_id_bwren    <= '0;
	  enve_id_brwaddr  <= enve_id_brwaddr;
	end
	else begin
	  enve_id_bwrdata  <={enve_id_bwrdata[31:16] + 16'd20,enve_id_bwrdata[15:0] + 16'd20};
	  enve_id_bwren    <= '1;
	  enve_id_brwaddr  <= enve_id_brwaddr + 16'd4;
	end
  end
end

//mod_sideband_sel
assign mod_sideband_sel = 1'b0;

//mod_pha_sfot_clr
assign mod_pha_sfot_clr = 1'b0;

//role_sel


logic [31:0] cnt_c;

wire add_cnt = 'b1;
			   
wire end_cnt = 1'b0;

wire [31:0] cnt_n = end_cnt ? 32'h0        :
                    add_cnt ? cnt_c + 1'b1 :
					          cnt_c        ;


sirv_gnrl_dffr #(32) cnt_c_dffr (cnt_n, cnt_c, clk, rst_n);



always @(posedge clk or negedge rst_n) begin
  if(!rst_n) begin
    role_sel        <= 2'b00;
	mcu_intp_sel    <= 2'b00;
	mcu_nco_pha_clr <= 1'b0;
	mcu_rz_pha      <= 16'b0;
	send            <= 1'b0;
	sendc           <= 1'b0;
	codeword        <= 32'b0;
	fb_st           <= 2'b00;
  end
  else if(cnt_c == 32'd1000) begin
    role_sel        <= 2'b00;
	mcu_intp_sel    <= 2'b11;
	mcu_nco_pha_clr <= 1'b0;
	mcu_rz_pha      <= 16'b0;
	send            <= 1'b1;
	sendc           <= 1'b0;
	codeword        <= 32'b000000000000_0_0000_01_101_11_00000100;
	fb_st           <= 2'b00;
  end
  else if(cnt_c == 32'd1001) begin
    role_sel        <= 2'b00;
	mcu_intp_sel    <= 2'b11;
	mcu_nco_pha_clr <= 1'b0;
	mcu_rz_pha      <= 16'd5;
	send            <= 1'b0;
	sendc           <= 1'b0;
	codeword        <= 32'b000000000000_0_0000_01_101_11_00000100;
	fb_st           <= 2'b00;
  end
  else if(cnt_c == 32'd10000) begin
    role_sel        <= 2'b00;
	mcu_intp_sel    <= 2'b11;
	mcu_nco_pha_clr <= 1'b0;
	mcu_rz_pha      <= 16'd88;
	send            <= 1'b1;
	sendc           <= 1'b0;
	codeword        <= 32'b000000000000_1_0000_01_101_11_00000100;
	fb_st           <= 2'b00;
  end
  else if(cnt_c == 32'd10001) begin
    role_sel        <= 2'b00;
    mcu_intp_sel    <= 2'b11;
    mcu_nco_pha_clr <= 1'b0;
    mcu_rz_pha      <= 16'b0;
    send            <= 1'b0;
    sendc           <= 1'b0;
    codeword        <= 32'b000000000000_0_0000_01_101_11_00000100;
    fb_st           <= 2'b00;
  end
  else if(cnt_c == 32'd20000) begin
    role_sel        <= 2'b00;
    mcu_intp_sel    <= 2'b11;
    mcu_nco_pha_clr <= 1'b0;
    mcu_rz_pha      <= 16'b0;
    send            <= 1'b0;
    sendc           <= 1'b1;
    codeword        <= 32'b000000000000_0_0000_01_101_11_00000100;
    fb_st           <= 2'b01;
  end
  else if(cnt_c == 32'd20001) begin
    role_sel        <= 2'b00;
    mcu_intp_sel    <= 2'b11;
    mcu_nco_pha_clr <= 1'b0;
    mcu_rz_pha      <= 16'b0;
    send            <= 1'b0;
    sendc           <= 1'b0;
    codeword        <= 32'b000000000000_0_0000_01_000_11_00000100;
    fb_st           <= 2'b01;
  end
  else if(cnt_c == 32'd30000) begin
    role_sel        <= 2'b00;
    mcu_intp_sel    <= 2'b11;
    mcu_nco_pha_clr <= 1'b0;
    mcu_rz_pha      <= 16'hf000;
    send            <= 1'b1;
    sendc           <= 1'b0;
    codeword        <= 32'b000000000000_0_0000_00_000_11_00000100;
    fb_st           <= 2'b01;
  end
  else if(cnt_c == 32'd30001) begin
    role_sel        <= 2'b00;
    mcu_intp_sel    <= 2'b11;
    mcu_nco_pha_clr <= 1'b0;
    mcu_rz_pha      <= 16'hf000;
    send            <= 1'b0;
    sendc           <= 1'b0;
    codeword        <= 32'b000000000000_0_0000_00_000_11_00000100;
    fb_st           <= 2'b01;
  end
  else if(cnt_c == 32'd30002) begin
    role_sel        <= 2'b00;
    mcu_intp_sel    <= 2'b11;
    mcu_nco_pha_clr <= 1'b0;
    mcu_rz_pha      <= 16'hf000;
    send            <= 1'b0;
    sendc           <= 1'b0;
    codeword        <= 32'b000000000000_0_0000_00_000_11_00000100;
    fb_st           <= 2'b01;
  end
  else if(cnt_c == 32'd40000) begin
    role_sel        <= 2'b00;
    mcu_intp_sel    <= 2'b11;
    mcu_nco_pha_clr <= 1'b0;
    mcu_rz_pha      <= 16'h1000;
    send            <= 1'b1;
    sendc           <= 1'b0;
    codeword        <= 32'b000000000000_0_0000_00_000_11_00000100;
    fb_st           <= 2'b01;
  end
  else if(cnt_c == 32'd40001) begin
    role_sel        <= 2'b00;
    mcu_intp_sel    <= 2'b11;
    mcu_nco_pha_clr <= 1'b0;
    mcu_rz_pha      <= 16'h1000;
    send            <= 1'b0;
    sendc           <= 1'b0;
    codeword        <= 32'b000000000000_0_0000_00_000_11_00000100;
    fb_st           <= 2'b01;
  end
end 
  
awg_top U_awg_top            (
   .clk                      ( clk                      )                             
  ,.rst_n                    ( rst_n                    )        
  ,.mcu_cwfr                 ( mcu_cwfr                 )   
  ,.mcu_gapr                 ( mcu_gapr                 )   
  ,.mcu_ampr                 ( mcu_ampr                 )   
  ,.mcu_baisr                ( mcu_baisr                )   
  ,.mcu_intp_sel             ( mcu_intp_sel             )     
  ,.mcu_nco_pha_clr          ( mcu_nco_pha_clr          )
  ,.mcu_rz_pha               ( mcu_rz_pha               )
  ,.send                     ( send                     )
  ,.sendc                    ( sendc                    )
  ,.codeword                 ( codeword                 )
  ,.fb_st                    ( fb_st                    )
  ,.enve_bwrdata             ( enve_bwrdata             )
  ,.enve_bwren               ( enve_bwren               )
  ,.enve_brwaddr             ( enve_brwaddr             )
  ,.enve_brden               ( enve_brden               )
  ,.enve_brddata             ( enve_brddata             )
  ,.enve_id_bwrdata          ( enve_id_bwrdata          )
  ,.enve_id_bwren            ( enve_id_bwren            )
  ,.enve_id_brwaddr          ( enve_id_brwaddr          )
  ,.enve_id_brden            ( enve_id_brden            )
  ,.enve_id_brddata          ( enve_id_brddata          )
  ,.enve_read_fsm_st         ( enve_read_fsm_st         )
  ,.proc_cft                 ( proc_cft                 )
  ,.mod_sideband_sel         ( mod_sideband_sel         )
  ,.mod_pha_sfot_clr         ( mod_pha_sfot_clr         )
  ,.role_sel                 ( role_sel                 )
  ,.intp_sel                 ( intp_sel                 )
  ,.mod_data_i               ( mod_data_i               )
  ,.mod_data_q               ( mod_data_q               )
  ,.mod_vld                  ( mod_vld                  )
  );

 initial	begin
	wait(cnt_c == 32'd100000)
			$finish(0);
end 

endmodule