first commit
This commit is contained in:
commit
af5b47d920
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@ -0,0 +1,17 @@
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VCS = vcs -full64 -sverilog +lint=TFIPC-L +v2k -debug_access+all +define+DUMP_FSDB -lca -q -timescale=1ns/1ps +nospecify -P /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/pli.a -l compile.log -R +plusarg_save +ntb_random_seed_automatic -cm line+cond+fsm+tgl+branch
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SIMV = ./simv -l sim.log -cm_dir ./coverage/test1db -cm line+cond+fsm+tgl+branch
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all:comp run
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comp:
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${VCS} -f files.f +incdir+./../rtl/qubitmcu
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run:
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${SIMV}
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file:
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find ../../rtl -name "*.*v" > files.f
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dbg:
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verdi -sverilog -f files.f -top TB -nologo &
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cov:
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urg -lca -dir simv.vdb -report both -dir ./coverage/test1db
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clean:
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rm -rf DVE* simv* *log ucli.key verdiLog urgReport csrc novas.conf novas_dump.log *.fsdb *.dat *.daidir *.vdb *.vf *.txt both coverage *~
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@ -0,0 +1,30 @@
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//2024-06-24 linear search for sys
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program case6(spi_if my_if,pllreg_if pll_if,dacreg_if dac_if,sysreg_if sys_if,mcureg_if mcu_if,awgreg_if awg_if,sram_if xif);
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env my_env;
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initial begin
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my_env = new();
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my_env.wif = my_if;
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my_env.pif = pll_if;
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my_env.dif = dac_if;
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my_env.vif = sys_if;
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my_env.mif = mcu_if;
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my_env.aif = awg_if;
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my_env.xif = xif;
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my_env.pktnum = 30;
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my_env.build();
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my_env.run();
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//$display($get_coverage());
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end
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endprogram
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@ -0,0 +1,129 @@
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../rtl/define/chip_define.v
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../rtl/qubitmcu/qbmcu_defines.v
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../tb/spi_tb/spi_if.sv
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../tb/sysreg_tb/sysreg_if.sv
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../tb/pllreg_tb/pllreg_if.sv
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../tb/mcureg_tb/mcureg_if.sv
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../tb/awgreg_tb/awgreg_if.sv
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spi_trans.sv
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spi_driver.sv
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../tb/spi_tb/spi_monitor.sv
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../tb/spi_tb/spi_scb.sv
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../tb/sram_tb/ramreg_scb.sv
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../tb/sram_tb/ram_refmodel.sv
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../tb/sysreg_tb/sysreg_trans.sv
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../tb/sysreg_tb/sysreg_monitor.sv
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../tb/sysreg_tb/sys_refmodel.sv
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../tb/sysreg_tb/sysreg_scb.sv
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../tb/pllreg_tb/pllreg_trans.sv
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../tb/pllreg_tb/pllreg_driver.sv
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../tb/pllreg_tb/pllreg_monitor.sv
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../tb/pllreg_tb/pll_refmodel.sv
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../tb/pllreg_tb/pllreg_scb.sv
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../tb/dacreg_tb/dacreg_trans.sv
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../tb/dacreg_tb/dacreg_if.sv
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../tb/dacreg_tb/dacreg_monitor.sv
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../tb/dacreg_tb/dac_refmodel.sv
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../tb/dacreg_tb/dacreg_scb.sv
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../tb/mcureg_tb/mcureg_trans.sv
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../tb/mcureg_tb/mcureg_monitor.sv
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../tb/mcureg_tb/mcu_refmodel.sv
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../tb/mcureg_tb/mcureg_scb.sv
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../tb/awgreg_tb/awgreg_trans.sv
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../tb/awgreg_tb/awgreg_monitor.sv
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../tb/awgreg_tb/awg_refmodel.sv
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../tb/awgreg_tb/awgreg_scb.sv
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../tb/env.sv
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case6.sv
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../tb/tb.sv
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../rtl/memory/sram_if.sv
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../rtl/awg/awg_ctrl.v
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../rtl/awg/awg_top.sv
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../rtl/awg/codeword_decode.v
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../rtl/awg/ctrl_regfile.v
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../rtl/awg/param_lut.sv
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../rtl/awg/modout_mux.v
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../rtl/clk/intpll_regfile.v
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../rtl/comm/sirv_gnrl_dffs.v
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../rtl/comm/sirv_gnrl_xchecker.v
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../rtl/dac_regfile/dac_regfile.v
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../rtl/debug/debug_sample.sv
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../rtl/debug/debug_top.sv
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../rtl/memory/dpram.v
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../rtl/memory/dpram_model.v
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../rtl/memory/sram_dmux.sv
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../rtl/memory/tsdn28hpcpuhdb128x128m4mw_170a_ffg0p99v0c.v
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../rtl/memory/tsdn28hpcpuhdb4096x32m4mw_170a_ffg0p99v0c.v
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../rtl/memory/tsdn28hpcpuhdb64x32m4mw_170a_ffg0p99v0c.v
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../rtl/memory/tsmc_dpram.v
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../rtl/modem/ampmod.v
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../rtl/modem/baisset.v
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../rtl/modem/freqmod.v
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../rtl/nco/coef_c.v
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../rtl/nco/coef_s.v
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../rtl/nco/cos_op.v
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../rtl/nco/nco.v
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../rtl/nco/nco_ch1.v
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../rtl/nco/p_nco.v
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../rtl/nco/p_nco_ch1.v
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../rtl/nco/ph2amp.v
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../rtl/nco/pipe_acc_48bit.v
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../rtl/nco/pipe_add_48bit.v
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../rtl/nco/sin_op.v
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../rtl/perips/DW03_updn_ctr.v
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../rtl/perips/qbmcu_busdecoder.v
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../rtl/perips/mcu_regfile.sv
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../rtl/qubitmcu/qbmcu.v
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../rtl/qubitmcu/qbmcu_datalock.v
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../rtl/qubitmcu/qbmcu_decode.v
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../rtl/qubitmcu/qbmcu_exu.v
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../rtl/qubitmcu/qbmcu_exu_alu.v
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../rtl/qubitmcu/qbmcu_exu_bjp.v
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../rtl/qubitmcu/qbmcu_exu_dpath.v
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../rtl/qubitmcu/qbmcu_exu_ext.v
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../rtl/qubitmcu/qbmcu_exu_lsuagu.v
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../rtl/qubitmcu/qbmcu_fsm.v
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../rtl/qubitmcu/qbmcu_ifu.v
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../rtl/qubitmcu/qbmcu_regfile.v
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../rtl/qubitmcu/qbmcu_wbck.v
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../rtl/rstgen/rst_gen_unit.v
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../rtl/rstgen/rst_sync.v
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../rtl/spi/spi_bus_decoder.sv
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../rtl/spi/spi_pll.v
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../rtl/spi/spi_slave.v
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../rtl/spi/spi_sys.v
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../rtl/sync/sync_buf.sv
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../rtl/system_regfile/system_regfile.v
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../rtl/top/channel_top.sv
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../rtl/top/digital_top.sv
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../rtl/top/xyz_chip_top.v
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../rtl/top/z_data_mux.v
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../rtl/xy_dsp/dacif/dacif.v
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../rtl/xy_dsp/dsp_top/xy_dsp.v
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../rtl/xy_dsp/duc/duc_hb1_pipe_shift.v
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../rtl/xy_dsp/duc/duc_hb1_top.v
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../rtl/xy_dsp/duc/duc_hb2_pipe_shift.v
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../rtl/xy_dsp/duc/duc_hb2_top_s.v
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../rtl/xy_dsp/duc/duc_hb3_pipe_shift.v
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../rtl/xy_dsp/duc/duc_hb3_top_s2.v
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../rtl/xy_dsp/duc/duc_hb4_pipe_shift.v
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../rtl/xy_dsp/duc/duc_hb4_top_s3.v
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../rtl/xy_dsp/duc/duc4.v
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../rtl/xy_dsp/qam/qam_top.v
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../rtl/xy_dsp/qam/ssb.v
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../rtl/dem/DAC_DEM_4.v
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../rtl/dem/DAC_DEM_16.v
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../rtl/dem/DAC_DEM.v
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../tb/digital_top/DW_mult_pipe.v
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../tb/digital_top/DW01_addsub.v
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../tb/digital_top/DW02_mult.v
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../tb/digital_top/clk_gen.v
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../tb/chip_top/thermo2binary_top.v
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../tb/chip_top/thermo7_binary3.v
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../tb/chip_top/thermo15_binary4.v
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../rtl/io/iopad.v
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../rtl/io/tphn28hpcpgv18.v
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../rtl/comm/syncer.v
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../rtl/qubitmcu/qbmcu_undefines.v
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../rtl/define/chip_undefine.v
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,401 @@
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//2024-06-24 linear search for all addr
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class spi_driver;
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static bit my_cmd=1'b0;
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static bit[24:0] last_addr=25'h190_0000;
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static int last_size;
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static bit[24:0] addr_list[$];
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//MOSI data pkt, other input_signals are not packed
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spi_trans m_trans;
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//interface
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virtual spi_if vif;
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//MOSI data_stream input to SPI(DUT)
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bit stream[$];
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//parameter for randomization
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int pktnum;
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int interval;
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int half_sclk;
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bit autarchy;
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rand int error_time;
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constraint cstr{
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error_time <= 544;
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error_time >= -544;
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}
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covergroup SYSAddr;
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coverpoint m_trans.addr{
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bins IDR = {[25'h00:25'h03]};
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bins VIDR = {[25'h04:25'h07]};
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bins DATER = {[25'h08:25'h0B]};
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bins VERR = {[25'h0C:25'h0F]};
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bins TESTR = {[25'h10:25'h13]};
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bins IMR = {[25'h14:25'h17]};
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bins ISR = {[25'h18:25'h1B]};
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bins SFRTR = {[25'h1C:25'h1F]};
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bins SFRR = {[25'h20:25'h23]};
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bins CH0RSTR = {[25'h24:25'h27]};
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bins CH1RSTR = {[25'h28:25'h2B]};
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bins CH2RSTR = {[25'h2C:25'h2F]};
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bins CH3RSTR = {[25'h30:25'h33]};
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bins DBGCFGR = {[25'h34:25'h37]};
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bins MISR = {[25'h40:25'h43]};
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}
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option.per_instance = 1;
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endgroup
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covergroup INSTRAddr;
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coverpoint m_trans.addr{
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bins INSTRCTION[8192] = {[25'h010_0000:25'h010_7FFF]};
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}
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option.per_instance = 1;
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endgroup
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covergroup DATAAddr;
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coverpoint m_trans.addr{
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bins DATA[8192] = {[25'h020_0000:25'h020_7FFF]};
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}
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option.per_instance = 1;
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endgroup
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covergroup CTRAddr;
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coverpoint m_trans.addr{
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bins MCUPARAR0 = {[25'h30_0000:25'h30_0003]};
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bins MCUPARAR1 = {[25'h30_0004:25'h30_0007]};
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bins MCUPARAR2 = {[25'h30_0008:25'h30_000B]};
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bins MCUPARAR3 = {[25'h30_000C:25'h30_000F]};
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bins MCURESR0 = {[25'h30_0010:25'h30_0013]};
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bins MCURESR1 = {[25'h30_0014:25'h30_0017]};
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bins MCURESR2 = {[25'h30_0018:25'h30_001B]};
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bins MCURESR3 = {[25'h30_001C:25'h30_001F]};
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bins RTIMR = {[25'h30_0098:25'h30_009B]};
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bins ICNTR = {[25'h30_009C:25'h30_009F]};
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bins FSIR = {[25'h30_00A0:25'h30_00A3]};
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bins MODMR = {[25'h30_0100:25'h30_0103]};
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bins INTPMR = {[25'h30_0104:25'h30_0107]};
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bins MIXNCOCR = {[25'h30_0108:25'h30_010B]};
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bins MIXNFCWHR = {[25'h30_010C:25'h30_010F]};
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bins MIXNFCWLR = {[25'h30_0110:25'h30_0113]};
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bins MIXNPHAR = {[25'h30_0114:25'h30_0117]};
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bins MIXMR = {[25'h30_0118:25'h30_011B]};
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bins MIXODTR = {[25'h30_011C:25'h30_011F]};
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bins MIXODFR = {[25'h30_0120:25'h30_0123]};
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bins ROLER = {[25'h30_0128:25'h30_012B]};
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bins MIXNCOSCER = {[25'h30_012C:25'h30_012F]};
|
||||
bins MODDOTR = {[25'h30_0130:25'h30_0133]};
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||||
bins STR = {[25'h30_0134:25'h30_0137]};
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||||
}
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||||
option.per_instance = 1;
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||||
endgroup
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||||
|
||||
covergroup ENVELOPEIDAddr;
|
||||
coverpoint m_trans.addr{
|
||||
bins ENVELOPEID[64] = {[25'h040_0000:25'h040_00FF]};
|
||||
}
|
||||
option.per_instance = 1;
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||||
endgroup
|
||||
|
||||
covergroup ENVELOPEDATAAddr;
|
||||
coverpoint m_trans.addr{
|
||||
bins ENVELOPEDATA[8192] = {[25'h050_0000:25'h050_7FFF]};
|
||||
}
|
||||
option.per_instance = 1;
|
||||
endgroup
|
||||
|
||||
covergroup DACAddr;
|
||||
coverpoint m_trans.addr{
|
||||
bins PRBSCR = {[25'h060_0000:25'h060_0003]};
|
||||
bins SET0CR = {[25'h060_0004:25'h060_0007]};
|
||||
bins SET1CR = {[25'h060_0008:25'h060_000B]};
|
||||
bins SET2CR = {[25'h060_000C:25'h060_000F]};
|
||||
bins SET3CR = {[25'h060_0010:25'h060_0013]};
|
||||
bins SET4CR = {[25'h060_0014:25'h060_0017]};
|
||||
bins SET5CR = {[25'h060_0018:25'h060_001B]};
|
||||
bins SET6CR = {[25'h060_001C:25'h060_001F]};
|
||||
bins SET7CR = {[25'h060_0020:25'h060_0023]};
|
||||
bins SET8CR = {[25'h060_0024:25'h060_0027]};
|
||||
bins SET9CR = {[25'h060_0028:25'h060_002B]};
|
||||
bins SET10CR = {[25'h060_002C:25'h060_002F]};
|
||||
bins SET11CR = {[25'h060_0030:25'h060_0033]};
|
||||
bins SET12CR = {[25'h060_0034:25'h060_0037]};
|
||||
bins SET13CR = {[25'h060_0038:25'h060_003B]};
|
||||
bins SET14CR = {[25'h060_003C:25'h060_003F]};
|
||||
bins SET15CR = {[25'h060_0040:25'h060_0043]};
|
||||
bins DACADDR = {[25'h060_0044:25'h060_0047]};
|
||||
bins DACDW = {[25'h060_0048:25'h060_004B]};
|
||||
bins DACREF = {[25'h060_004C:25'h060_004F]};
|
||||
bins PRBSRST0 = {[25'h060_0050:25'h060_0053]};
|
||||
bins PRBSSET0 = {[25'h060_0054:25'h060_0057]};
|
||||
bins PRBSRST1 = {[25'h060_0058:25'h060_005B]};
|
||||
bins PRBSSET1 = {[25'h060_005C:25'h060_005F]};
|
||||
bins PRBSREV = {[25'h060_0060:25'h060_0063]};
|
||||
bins CALSIG = {[25'h060_0064:25'h060_0067]};
|
||||
bins CALEND = {[25'h060_0068:25'h060_006B]};
|
||||
bins CALRSTN = {[25'h060_006C:25'h060_006F]};
|
||||
bins CALDIVRSTN = {[25'h060_0070:25'h060_0073]};
|
||||
}
|
||||
option.per_instance = 1;
|
||||
endgroup
|
||||
|
||||
covergroup MCUAddr;
|
||||
coverpoint m_trans.addr{
|
||||
bins MCUPARAR0 = {[25'h70_0000:25'h70_0003]};
|
||||
bins MCUPARAR1 = {[25'h70_0004:25'h70_0007]};
|
||||
bins MCUPARAR2 = {[25'h70_0008:25'h70_000B]};
|
||||
bins MCUPARAR3 = {[25'h70_000C:25'h70_000F]};
|
||||
bins MCURESR0 = {[25'h70_0010:25'h70_0013]};
|
||||
bins MCURESR1 = {[25'h70_0014:25'h70_0017]};
|
||||
bins MCURESR2 = {[25'h70_0018:25'h70_001B]};
|
||||
bins MCURESR3 = {[25'h70_001C:25'h70_001F]};
|
||||
bins CWFR0 = {[25'h70_0040:25'h70_0043]};
|
||||
bins CWFR1 = {[25'h70_0044:25'h70_0047]};
|
||||
bins CWFR2 = {[25'h70_0048:25'h70_004B]};
|
||||
bins CWFR3 = {[25'h70_004C:25'h70_004F]};
|
||||
bins CWPRR = {[25'h70_0050:25'h70_0053]};
|
||||
bins GAPR0 = {[25'h70_0054:25'h70_0057]};
|
||||
bins GAPR1 = {[25'h70_0058:25'h70_005B]};
|
||||
bins GAPR2 = {[25'h70_005C:25'h70_005F]};
|
||||
bins GAPR3 = {[25'h70_0060:25'h70_0063]};
|
||||
bins GAPR4 = {[25'h70_0064:25'h70_0067]};
|
||||
bins GAPR5 = {[25'h70_0068:25'h70_006B]};
|
||||
bins GAPR6 = {[25'h70_006C:25'h70_006F]};
|
||||
bins GAPR7 = {[25'h70_0070:25'h70_0073]};
|
||||
bins LCPR = {[25'h70_0074:25'h70_0077]};
|
||||
bins AMPR0 = {[25'h70_0078:25'h70_007B]};
|
||||
bins AMPR1 = {[25'h70_007C:25'h70_007F]};
|
||||
bins AMPR2 = {[25'h70_0080:25'h70_0083]};
|
||||
bins AMPR3 = {[25'h70_0084:25'h70_0087]};
|
||||
bins BIASR0 = {[25'h70_0088:25'h70_008B]};
|
||||
bins BIASR1 = {[25'h70_008C:25'h70_008F]};
|
||||
bins BIASR2 = {[25'h70_0090:25'h70_0093]};
|
||||
bins BIASR3 = {[25'h70_0094:25'h70_0097]};
|
||||
bins RTIMR = {[25'h70_0098:25'h70_009B]};
|
||||
bins ICNTR = {[25'h70_009C:25'h70_009F]};
|
||||
bins FSIR = {[25'h70_00A0:25'h70_00A3]};
|
||||
bins INTPSELR = {[25'h70_00A4:25'h70_00A7]};
|
||||
}
|
||||
option.per_instance = 1;
|
||||
endgroup
|
||||
|
||||
covergroup DBGAddr;
|
||||
coverpoint m_trans.addr{
|
||||
bins DBGAddr[1024] = {[25'h190_0000:25'h190_0FFF]};
|
||||
}
|
||||
option.per_instance = 1;
|
||||
endgroup
|
||||
|
||||
|
||||
covergroup PLLAddr;
|
||||
coverpoint m_trans.addr{
|
||||
bins INTPLL_REFCTRL = {[25'h1f0_0000:25'h1f0_0003]};
|
||||
bins INTPLL_PCNT = {[25'h1f0_0004:25'h1f0_0007]};
|
||||
bins INTPLL_PFDCTRL = {[25'h1f0_0008:25'h1f0_000B]};
|
||||
bins INTPLL_SPDCTRL = {[25'h1f0_000C:25'h1f0_000F]};
|
||||
bins INTPLL_PTATCTRL = {[25'h1f0_0010:25'h1f0_0013]};
|
||||
bins INTPLL_FLLCTRL = {[25'h1f0_0014:25'h1f0_0017]};
|
||||
bins INTPLL_SELCTRL = {[25'h1f0_0018:25'h1f0_001B]};
|
||||
bins INTPLL_VCOCTRL = {[25'h1f0_001C:25'h1f0_001F]};
|
||||
bins INTPLL_VCOFBADJ = {[25'h1f0_0020:25'h1f0_0023]};
|
||||
bins INTPLL_AFCCTRL = {[25'h1f0_0024:25'h1f0_0027]};
|
||||
bins INTPLL_AFCCNT = {[25'h1f0_0028:25'h1f0_002B]};
|
||||
bins INTPLL_AFCLDCNT = {[25'h1f0_002C:25'h1f0_002F]};
|
||||
bins INTPLL_AFCPRES = {[25'h1f0_0030:25'h1f0_0033]};
|
||||
bins INTPLL_AFCLDTCC = {[25'h1f0_0034:25'h1f0_0037]};
|
||||
bins INTPLL_AFCFBTCC = {[25'h1f0_0038:25'h1f0_003B]};
|
||||
bins INTPLL_DIVCFG = {[25'h1f0_003C:25'h1f0_003F]};
|
||||
bins INTPLL_TCLKCFG = {[25'h1f0_0040:25'h1f0_0043]};
|
||||
bins INTPLL_DCLKSEL = {[25'h1f0_0044:25'h1f0_0047]};
|
||||
bins INTPLL_STATUS = {[25'h1f0_0048:25'h1f0_004B]};
|
||||
bins INTPLL_SYNCFG = {[25'h1f0_004C:25'h1f0_004F]};
|
||||
bins INTPLL_UPDATE = {[25'h1f0_0050:25'h1f0_0053]};
|
||||
bins INTPLL_CLKRXPD = {[25'h1f0_0054:25'h1f0_0057]};
|
||||
}
|
||||
option.per_instance = 1;
|
||||
endgroup
|
||||
|
||||
|
||||
function new();
|
||||
SYSAddr = new();
|
||||
INSTRAddr = new();
|
||||
DATAAddr = new();
|
||||
CTRAddr = new();
|
||||
ENVELOPEIDAddr = new();
|
||||
ENVELOPEDATAAddr = new();
|
||||
DACAddr = new();
|
||||
MCUAddr = new();
|
||||
DBGAddr = new();
|
||||
PLLAddr = new();
|
||||
endfunction
|
||||
extern task do_drive();
|
||||
extern task make_pkt(spi_trans tr);
|
||||
|
||||
endclass : spi_driver
|
||||
|
||||
task spi_driver::do_drive();
|
||||
int i=0,j=0;
|
||||
|
||||
for(i=0;i<14;i++)
|
||||
addr_list[i]=4*i;
|
||||
addr_list[14] = 25'h000_0040;
|
||||
addr_list.delete(8);
|
||||
addr_list.delete(8);
|
||||
// $display(addr_list);
|
||||
|
||||
pktnum=addr_list.size()*2;
|
||||
|
||||
$display("pkt_num:\t%0d",pktnum);
|
||||
|
||||
while(!vif.rstn) begin
|
||||
vif.csn = 1'b1;
|
||||
vif.sclk = 1'b1;
|
||||
@(posedge vif.clk);
|
||||
end
|
||||
|
||||
for(j=0;j<pktnum;j++) begin
|
||||
|
||||
m_trans = new();
|
||||
|
||||
if(!m_trans.randomize() with {
|
||||
cmd==my_cmd;
|
||||
(cmd==1'b0 || data.size()==last_size);
|
||||
//(cmd==1'b0 || addr==last_addr);
|
||||
addr == addr_list[j/2];
|
||||
// addr[24:20] == 5'h0 || //sys
|
||||
// addr[24:20] == 5'h1 || //instruction srams
|
||||
// addr[24:20] == 5'h2 || //data srams
|
||||
// addr[24:20] == 5'h3 || //awg
|
||||
// addr[24:20] == 5'h4 || //envelope id srams
|
||||
// addr[24:20] == 5'h5 || //envelope data srams
|
||||
// addr[24:20] == 5'h6 || //dac
|
||||
// addr[24:20] == 5'h7 || //mcu
|
||||
// addr[24:20] == 5'h19 || //dbg srams
|
||||
// addr[24:20] == 5'h1F ; //pll
|
||||
addr[24: 20] == 5'h0;
|
||||
addr[1:0] == 0;
|
||||
// data.size == 2;
|
||||
interval == 50;
|
||||
})
|
||||
$fatal(0,"Randomize Failed");
|
||||
if(m_trans.cmd == 1'b0) begin
|
||||
last_addr = m_trans.addr;
|
||||
last_size = m_trans.data.size();
|
||||
end
|
||||
my_cmd = ~my_cmd;
|
||||
//Autarchy: Testcase force to assign some params
|
||||
interval = m_trans.interval;
|
||||
if(!autarchy) begin
|
||||
half_sclk = m_trans.half_sclk;
|
||||
end
|
||||
if((m_trans.addr <= 25'h000_001F) &&
|
||||
((m_trans.addr + (m_trans.data.size()-1) * 4) >= 25'h000_001C))
|
||||
m_trans.data[(25'h000_001C - m_trans.addr)/4] =
|
||||
m_trans.data[(25'h000_001C - m_trans.addr)/4] % 4 + 1;
|
||||
|
||||
|
||||
|
||||
make_pkt(m_trans);
|
||||
|
||||
//$display(m_trans.addr);
|
||||
|
||||
SYSAddr.sample();
|
||||
INSTRAddr.sample();
|
||||
DATAAddr.sample();
|
||||
CTRAddr.sample();
|
||||
ENVELOPEIDAddr.sample();
|
||||
ENVELOPEDATAAddr.sample();
|
||||
DACAddr.sample();
|
||||
MCUAddr.sample();
|
||||
DBGAddr.sample();
|
||||
PLLAddr.sample();
|
||||
|
||||
repeat(interval)
|
||||
@(posedge vif.clk);
|
||||
|
||||
//pktnum--;
|
||||
end
|
||||
|
||||
|
||||
$finish(0);
|
||||
//$display(SYSAddr.get_inst_coverage());
|
||||
//$display(MCUAddr.get_inst_coverage());
|
||||
//$display(AWGAddr.get_inst_coverage());
|
||||
|
||||
endtask : do_drive
|
||||
|
||||
|
||||
task spi_driver::make_pkt(spi_trans tr);
|
||||
int i=0,j=0;
|
||||
int cs_time,mo_time;
|
||||
|
||||
//*****************initialize chip_select and input_clk******************//
|
||||
vif.csn <= 1'b1;
|
||||
vif.sclk <= 1'b1;
|
||||
vif.mosi <= stream[0];
|
||||
vif.cfgid <= tr.cfgid;
|
||||
@(posedge vif.clk);
|
||||
vif.csn <= 1'b0;
|
||||
vif.sclk <= 1'b1;
|
||||
|
||||
//unpack into bitstream
|
||||
stream.delete();
|
||||
tr.unpack(stream);
|
||||
|
||||
//mosi valid time: time for bitstream to be all sent
|
||||
//csn valid_time: maybe a delay after or ahead of mosi_finished
|
||||
mo_time = (stream.size()+1)*2*half_sclk;
|
||||
cs_time = (pktnum==1) ? (mo_time + error_time%mo_time) : mo_time;
|
||||
|
||||
//$display("***************************ONE PKT DRIVERED***************************");
|
||||
//$display("half_sclk:\t%0d\t\t\t\t\t\t **",half_sclk);
|
||||
//$display("interval:\t%0d\t\t\t\t\t\t **",interval);
|
||||
//$display("error_time:\t%0d\t\t\t\t\t\t **",error_time);
|
||||
//$display("data_size:\t%0d\t\t\t\t\t\t **",tr.data.size());
|
||||
//$display("cmd:\t\t%0d\t\t\t\t\t\t **",tr.cmd);
|
||||
//$display("id:\t\t%h\t\t\t\t\t\t **",tr.cfgid);
|
||||
//$display("addr:\t\t%h\t\t\t\t\t\t **",tr.addr);
|
||||
//$display(stream);
|
||||
//if(!tr.cmd)
|
||||
//for(i=0;i<tr.data.size;i++)
|
||||
//$display("mosi:\t\t%h\t\t **",tr.data[i]);
|
||||
|
||||
//********************drive the stream onto interface********************//
|
||||
fork
|
||||
|
||||
|
||||
//************************Make sclk************************//
|
||||
begin
|
||||
for(j=0;j<cs_time;j++) begin
|
||||
if(j % half_sclk == 0 && j!=0)
|
||||
vif.sclk <= ~vif.sclk;
|
||||
@(posedge vif.clk);
|
||||
end
|
||||
vif.sclk = 1'b1;
|
||||
@(posedge vif.clk);
|
||||
vif.csn = 1'b1;
|
||||
end
|
||||
|
||||
//************************Send data************************//
|
||||
begin
|
||||
for(i=0;i<mo_time;i++) begin
|
||||
// data will be sampled at posedge,
|
||||
// so prepare them at the negedge before each posedge
|
||||
if(i % (2*half_sclk) == half_sclk)begin
|
||||
vif.mosi <= stream[(i/half_sclk-1)/2];
|
||||
//$display(i);
|
||||
end
|
||||
@(posedge vif.clk);
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
join
|
||||
|
||||
//$display("**********************************************************************");
|
||||
|
||||
endtask
|
||||
|
||||
|
|
@ -0,0 +1,168 @@
|
|||
class spi_trans;
|
||||
|
||||
//Properties for Randomizing the MOSI
|
||||
rand bit cmd;
|
||||
randc bit[24:0] addr;
|
||||
rand bit[ 4:0] cfgid;
|
||||
rand bit[31:0] data[$];
|
||||
|
||||
//Properties for Randomizing the pkt_sent process
|
||||
rand int interval;
|
||||
rand int half_sclk;
|
||||
|
||||
|
||||
constraint cstr {
|
||||
data.size() >= 1;
|
||||
data.size() <= 1;//not solid
|
||||
interval <= 1000;
|
||||
interval >= 0;
|
||||
half_sclk <= 32;
|
||||
half_sclk >= 4;
|
||||
//Select system_regfile
|
||||
(addr >= 25'h000_0000 &&
|
||||
//addr <= 25'h000_0037 &&
|
||||
int'(addr) <= int'(25'h000_003B) - int'(data.size()*4) &&
|
||||
addr != 25'h000_0020 &&
|
||||
addr != 25'h000_0024) ||
|
||||
(addr == 25'h000_0040) ||
|
||||
//Select instruction SRAMs 8192X32bit 32KB
|
||||
(addr >= 25'h010_0000 &&
|
||||
//addr <= 25'h010_7FFF &&
|
||||
int'(addr) <= 25'h010_8003 - data.size()*4) ||
|
||||
//Select data SRAMs 8192X32bit 32KB
|
||||
(addr >= 25'h020_0000 &&
|
||||
//addr <= 25'h020_7FFF &&
|
||||
int'(addr) <= 25'h020_8003 - data.size()*4) ||
|
||||
//Select awg_regfile
|
||||
(addr >= 25'h030_0000 &&
|
||||
//addr <= 25'h030_001F &&
|
||||
int'(addr) <= int'(25'h030_0023) - int'(data.size()*4)) ||
|
||||
(addr >= 25'h030_0098 &&
|
||||
//addr <= 25'h030_00A3 &&
|
||||
int'(addr) <= int'(25'h030_00A7) - int'(data.size()*4)) ||
|
||||
(addr >= 25'h030_0100 &&
|
||||
//addr <= 25'h030_0123 &&
|
||||
int'(addr) <= int'(25'h030_0127) - int'(data.size()*4)) ||
|
||||
(addr >= 25'h030_0128 &&
|
||||
//addr <= 25'h030_0137 &&
|
||||
int'(addr) <= int'(25'h030_013B) - int'(data.size()*4)) ||
|
||||
//Select envelope ID SRAMs 64X32bit 256B
|
||||
(addr >= 25'h040_0000 &&
|
||||
//addr <= 25'h040_00FF &&
|
||||
int'(addr) <= 25'h040_0103 - data.size()*4) ||
|
||||
//Select envelope data SRAMs 8192X32bit 32KB
|
||||
(addr >= 25'h050_0000 &&
|
||||
//addr <= 25'h050_7FFF &&
|
||||
int'(addr) <= 25'h050_8003 - data.size()*4) ||
|
||||
//Select dac_regfile
|
||||
(addr >= 25'h060_0000 &&
|
||||
//addr <= 25'h060_0073 &&
|
||||
int'(addr) <= int'(25'h060_0077) - int'(data.size()*4)) ||
|
||||
//Select mcu_regfile
|
||||
(addr >= 25'h070_0000 &&
|
||||
//addr <= 25'h070_01F &&
|
||||
int'(addr) <= int'(25'h070_0023) - int'(data.size()*4)) ||
|
||||
(addr >= 25'h070_0040 &&
|
||||
//addr <= 25'h070_00A7 &&
|
||||
int'(addr) <= int'(25'h070_00AB) - int'(data.size()*4)) ||
|
||||
//Select DBG SRAMs 256X128bit 4KB
|
||||
(addr >= 25'h190_0000 &&
|
||||
//addr <= 25'h190_0FFF &&
|
||||
int'(addr) <= 25'h190_1003 - data.size()*4) ||
|
||||
//Select intpll_regfile
|
||||
(addr >= 25'h1f0_0000 &&
|
||||
//addr <= 25'h1f0_0057 &&
|
||||
int'(addr) <= int'(25'h1f0_005B) - int'(data.size()*4)) ;
|
||||
}
|
||||
|
||||
function new();
|
||||
endfunction
|
||||
|
||||
extern function bit compare(spi_trans rhs_);
|
||||
extern function void print(integer fid);
|
||||
extern function void unpack(ref bit stream[$]);
|
||||
extern function void pack(bit stream[$]);
|
||||
|
||||
endclass : spi_trans
|
||||
|
||||
|
||||
|
||||
function bit spi_trans::compare(spi_trans rhs_);
|
||||
bit result=1'b1;
|
||||
int i=0;
|
||||
|
||||
result = ((cmd == rhs_.cmd) &&
|
||||
(addr == rhs_.addr) &&
|
||||
(cfgid == rhs_.cfgid));
|
||||
|
||||
if(this.data.size() != rhs_.data.size()) begin
|
||||
$display("data_sizes are different");
|
||||
result = 1'b0;
|
||||
end
|
||||
else
|
||||
for(i=0;i<data.size();i++)begin
|
||||
if(data[i] != rhs_.data[i])
|
||||
result = 1'b0;
|
||||
end
|
||||
|
||||
return result;
|
||||
endfunction : compare
|
||||
|
||||
|
||||
function void spi_trans::print(integer fid);
|
||||
int i=0;
|
||||
if(!cmd)$fwrite(fid,"----------ONE-PKT-DRIVEN----------\n");
|
||||
else $fwrite(fid,"---------ONE-PKT-COLLECTED--------\n");
|
||||
$fwrite(fid,"cmd:\t%h\n",cmd);
|
||||
$fwrite(fid,"addr:\t%h\n",addr);
|
||||
$fwrite(fid,"cfgid:\t%h\n",cfgid);
|
||||
for(i=0;i<data.size();i++)begin
|
||||
$fwrite(fid,"data[%2d]='h%h\n",i,data[i]);
|
||||
end
|
||||
endfunction : print
|
||||
|
||||
|
||||
function void spi_trans::unpack(ref bit stream[$]);
|
||||
int i=0,j=0;
|
||||
|
||||
stream[0]=cmd;
|
||||
|
||||
for(i=0;i<25;i++)
|
||||
stream[i+1] = addr[24-i];
|
||||
|
||||
for(i=0;i<5;i++)
|
||||
stream[i+26]= cfgid[4-i];
|
||||
|
||||
stream[31]=0;
|
||||
|
||||
for(i=0;i<data.size();i++)begin
|
||||
//$display("i=%2d,datai=%b",i,data[i]);
|
||||
for(j=0;j<32;j++)begin
|
||||
stream[32+i*32+j]=data[i][31-j];
|
||||
//$display("i=%2d,j=%2d,streamij=%b",i,j,stream[32+i*32+j]);
|
||||
end
|
||||
end
|
||||
|
||||
endfunction
|
||||
|
||||
function void spi_trans::pack(bit stream[$]);
|
||||
int i=0;
|
||||
bit[31:0] data_temp=32'b0;
|
||||
|
||||
cmd = stream.pop_front();
|
||||
|
||||
for(i=0;i<25;i++)
|
||||
addr[24-i] = stream.pop_front();
|
||||
|
||||
for(i=0;i<5;i++)
|
||||
cfgid[4-i] = stream.pop_front();
|
||||
|
||||
//reserved
|
||||
stream.pop_front();
|
||||
|
||||
while(stream.size()>0)begin
|
||||
for(i=0;i<32;i++)
|
||||
data_temp[31-i] = stream.pop_front();
|
||||
data.push_back(data_temp);
|
||||
end
|
||||
endfunction
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
VCS = vcs -full64 -sverilog +lint=TFIPC-L +v2k -debug_access+all +define+DUMP_FSDB -lca -q -timescale=1ns/1ps +nospecify -P /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/pli.a -l compile.log -R +plusarg_save +ntb_random_seed_automatic -cm line+cond+fsm+tgl+branch
|
||||
|
||||
SIMV = ./simv -l sim.log -cm_dir ./coverage/test1db -cm line+cond+fsm+tgl+branch
|
||||
all:comp run
|
||||
|
||||
comp:
|
||||
${VCS} -f files.f +incdir+./../rtl/qubitmcu
|
||||
run:
|
||||
${SIMV}
|
||||
file:
|
||||
find ../../rtl -name "*.*v" > files.f
|
||||
dbg:
|
||||
verdi -sverilog -f files.f -top TB -nologo &
|
||||
cov:
|
||||
urg -lca -dir simv.vdb -report both -dir ./coverage/test1db
|
||||
clean:
|
||||
rm -rf DVE* simv* TB1* *log ucli.key verdiLog urgReport csrc both coverage novas.conf novas_dump.log reports.txt *.fsdb *.dat *.daidir *.vdb *.vf*~
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
|
||||
program case6(spi_if my_if,pllreg_if pll_if,dacreg_if dac_if,sysreg_if sys_if,mcureg_if mcu_if,awgreg_if awg_if,sram_if xif);
|
||||
|
||||
env my_env;
|
||||
|
||||
initial begin
|
||||
|
||||
my_env = new();
|
||||
|
||||
my_env.wif = my_if;
|
||||
my_env.pif = pll_if;
|
||||
my_env.dif = dac_if;
|
||||
my_env.vif = sys_if;
|
||||
my_env.mif = mcu_if;
|
||||
my_env.aif = awg_if;
|
||||
my_env.xif = xif;
|
||||
my_env.pktnum = 30;
|
||||
|
||||
|
||||
my_env.build();
|
||||
|
||||
my_env.run();
|
||||
|
||||
//$display($get_coverage());
|
||||
|
||||
end
|
||||
|
||||
endprogram
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,129 @@
|
|||
../rtl/define/chip_define.v
|
||||
../rtl/qubitmcu/qbmcu_defines.v
|
||||
spi_trans.sv
|
||||
spi_driver.sv
|
||||
../tb/spi_tb/spi_if.sv
|
||||
../tb/sysreg_tb/sysreg_if.sv
|
||||
../tb/pllreg_tb/pllreg_if.sv
|
||||
../tb/mcureg_tb/mcureg_if.sv
|
||||
../tb/awgreg_tb/awgreg_if.sv
|
||||
../tb/spi_tb/spi_monitor.sv
|
||||
../tb/spi_tb/spi_scb.sv
|
||||
../tb/sram_tb/ramreg_scb.sv
|
||||
../tb/sram_tb/ram_refmodel.sv
|
||||
../tb/sysreg_tb/sysreg_trans.sv
|
||||
../tb/sysreg_tb/sysreg_monitor.sv
|
||||
../tb/sysreg_tb/sys_refmodel.sv
|
||||
../tb/sysreg_tb/sysreg_scb.sv
|
||||
../tb/pllreg_tb/pllreg_trans.sv
|
||||
../tb/pllreg_tb/pllreg_driver.sv
|
||||
../tb/pllreg_tb/pllreg_monitor.sv
|
||||
../tb/pllreg_tb/pll_refmodel.sv
|
||||
../tb/pllreg_tb/pllreg_scb.sv
|
||||
../tb/dacreg_tb/dacreg_trans.sv
|
||||
../tb/dacreg_tb/dacreg_if.sv
|
||||
../tb/dacreg_tb/dacreg_monitor.sv
|
||||
../tb/dacreg_tb/dac_refmodel.sv
|
||||
../tb/dacreg_tb/dacreg_scb.sv
|
||||
../tb/mcureg_tb/mcureg_trans.sv
|
||||
../tb/mcureg_tb/mcureg_monitor.sv
|
||||
../tb/mcureg_tb/mcu_refmodel.sv
|
||||
../tb/mcureg_tb/mcureg_scb.sv
|
||||
../tb/awgreg_tb/awgreg_trans.sv
|
||||
../tb/awgreg_tb/awgreg_monitor.sv
|
||||
../tb/awgreg_tb/awg_refmodel.sv
|
||||
../tb/awgreg_tb/awgreg_scb.sv
|
||||
../tb/env.sv
|
||||
case6.sv
|
||||
../tb/tb.sv
|
||||
../rtl/memory/sram_if.sv
|
||||
../rtl/awg/awg_ctrl.v
|
||||
../rtl/awg/awg_top.sv
|
||||
../rtl/awg/codeword_decode.v
|
||||
../rtl/awg/ctrl_regfile.v
|
||||
../rtl/awg/param_lut.sv
|
||||
../rtl/awg/modout_mux.v
|
||||
../rtl/clk/intpll_regfile.v
|
||||
../rtl/comm/sirv_gnrl_dffs.v
|
||||
../rtl/comm/sirv_gnrl_xchecker.v
|
||||
../rtl/dac_regfile/dac_regfile.v
|
||||
../rtl/debug/debug_sample.sv
|
||||
../rtl/debug/debug_top.sv
|
||||
../rtl/memory/dpram.v
|
||||
../rtl/memory/dpram_model.v
|
||||
../rtl/memory/sram_dmux.sv
|
||||
../rtl/memory/tsdn28hpcpuhdb128x128m4mw_170a_ffg0p99v0c.v
|
||||
../rtl/memory/tsdn28hpcpuhdb4096x32m4mw_170a_ffg0p99v0c.v
|
||||
../rtl/memory/tsdn28hpcpuhdb64x32m4mw_170a_ffg0p99v0c.v
|
||||
../rtl/memory/tsmc_dpram.v
|
||||
../rtl/modem/ampmod.v
|
||||
../rtl/modem/baisset.v
|
||||
../rtl/modem/freqmod.v
|
||||
../rtl/nco/coef_c.v
|
||||
../rtl/nco/coef_s.v
|
||||
../rtl/nco/cos_op.v
|
||||
../rtl/nco/nco.v
|
||||
../rtl/nco/nco_ch1.v
|
||||
../rtl/nco/p_nco.v
|
||||
../rtl/nco/p_nco_ch1.v
|
||||
../rtl/nco/ph2amp.v
|
||||
../rtl/nco/pipe_acc_48bit.v
|
||||
../rtl/nco/pipe_add_48bit.v
|
||||
../rtl/nco/sin_op.v
|
||||
../rtl/perips/DW03_updn_ctr.v
|
||||
../rtl/perips/qbmcu_busdecoder.v
|
||||
../rtl/perips/mcu_regfile.sv
|
||||
../rtl/qubitmcu/qbmcu.v
|
||||
../rtl/qubitmcu/qbmcu_datalock.v
|
||||
../rtl/qubitmcu/qbmcu_decode.v
|
||||
../rtl/qubitmcu/qbmcu_exu.v
|
||||
../rtl/qubitmcu/qbmcu_exu_alu.v
|
||||
../rtl/qubitmcu/qbmcu_exu_bjp.v
|
||||
../rtl/qubitmcu/qbmcu_exu_dpath.v
|
||||
../rtl/qubitmcu/qbmcu_exu_ext.v
|
||||
../rtl/qubitmcu/qbmcu_exu_lsuagu.v
|
||||
../rtl/qubitmcu/qbmcu_fsm.v
|
||||
../rtl/qubitmcu/qbmcu_ifu.v
|
||||
../rtl/qubitmcu/qbmcu_regfile.v
|
||||
../rtl/qubitmcu/qbmcu_wbck.v
|
||||
../rtl/rstgen/rst_gen_unit.v
|
||||
../rtl/rstgen/rst_sync.v
|
||||
../rtl/spi/spi_bus_decoder.sv
|
||||
../rtl/spi/spi_pll.v
|
||||
../rtl/spi/spi_slave.v
|
||||
../rtl/spi/spi_sys_20240624.v
|
||||
../rtl/sync/sync_buf.sv
|
||||
../rtl/system_regfile/system_regfile.v
|
||||
../rtl/top/channel_top.sv
|
||||
../rtl/top/digital_top.sv
|
||||
../rtl/top/xyz_chip_top.v
|
||||
../rtl/top/z_data_mux.v
|
||||
../rtl/xy_dsp/dacif/dacif.v
|
||||
../rtl/xy_dsp/dsp_top/xy_dsp.v
|
||||
../rtl/xy_dsp/duc/duc_hb1_pipe_shift.v
|
||||
../rtl/xy_dsp/duc/duc_hb1_top.v
|
||||
../rtl/xy_dsp/duc/duc_hb2_pipe_shift.v
|
||||
../rtl/xy_dsp/duc/duc_hb2_top_s.v
|
||||
../rtl/xy_dsp/duc/duc_hb3_pipe_shift.v
|
||||
../rtl/xy_dsp/duc/duc_hb3_top_s2.v
|
||||
../rtl/xy_dsp/duc/duc_hb4_pipe_shift.v
|
||||
../rtl/xy_dsp/duc/duc_hb4_top_s3.v
|
||||
../rtl/xy_dsp/duc/duc4.v
|
||||
../rtl/xy_dsp/qam/qam_top.v
|
||||
../rtl/xy_dsp/qam/ssb.v
|
||||
../rtl/dem/DAC_DEM_4.v
|
||||
../rtl/dem/DAC_DEM_16.v
|
||||
../rtl/dem/DAC_DEM.v
|
||||
../tb/digital_top/DW_mult_pipe.v
|
||||
../tb/digital_top/DW01_addsub.v
|
||||
../tb/digital_top/DW02_mult.v
|
||||
../tb/digital_top/clk_gen.v
|
||||
../tb/chip_top/thermo2binary_top.v
|
||||
../tb/chip_top/thermo7_binary3.v
|
||||
../tb/chip_top/thermo15_binary4.v
|
||||
../rtl/io/iopad.v
|
||||
../rtl/io/tphn28hpcpgv18.v
|
||||
../rtl/comm/syncer.v
|
||||
../rtl/qubitmcu/qbmcu_undefines.v
|
||||
../rtl/define/chip_undefine.v
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,389 @@
|
|||
//2024-06-24,randc with random search
|
||||
class spi_driver;
|
||||
|
||||
static bit my_cmd=1'b0;
|
||||
static bit[24:0] last_addr;
|
||||
static int last_size;
|
||||
|
||||
//MOSI data pkt, other input_signals are not packed
|
||||
spi_trans m_trans;
|
||||
|
||||
//interface
|
||||
virtual spi_if vif;
|
||||
|
||||
//MOSI data_stream input to SPI(DUT)
|
||||
bit stream[$];
|
||||
|
||||
//parameter for randomization
|
||||
int pktnum;
|
||||
int interval;
|
||||
int half_sclk;
|
||||
bit autarchy;
|
||||
rand int error_time;
|
||||
|
||||
constraint cstr{
|
||||
error_time <= 544;
|
||||
error_time >= -544;
|
||||
}
|
||||
|
||||
covergroup SYSAddr;
|
||||
coverpoint m_trans.addr{
|
||||
bins IDR = {[25'h00:25'h03]};
|
||||
bins VIDR = {[25'h04:25'h07]};
|
||||
bins DATER = {[25'h08:25'h0B]};
|
||||
bins VERR = {[25'h0C:25'h0F]};
|
||||
bins TESTR = {[25'h10:25'h13]};
|
||||
bins IMR = {[25'h14:25'h17]};
|
||||
bins ISR = {[25'h18:25'h1B]};
|
||||
bins SFRTR = {[25'h1C:25'h1F]};
|
||||
bins SFRR = {[25'h20:25'h23]};
|
||||
bins CH0RSTR = {[25'h24:25'h27]};
|
||||
bins CH1RSTR = {[25'h28:25'h2B]};
|
||||
bins CH2RSTR = {[25'h2C:25'h2F]};
|
||||
bins CH3RSTR = {[25'h30:25'h33]};
|
||||
bins DBGCFGR = {[25'h34:25'h37]};
|
||||
bins MISR = {[25'h40:25'h43]};
|
||||
}
|
||||
option.per_instance = 1;
|
||||
endgroup
|
||||
|
||||
covergroup INSTRAddr;
|
||||
coverpoint m_trans.addr{
|
||||
bins INSTRCTION[8192] = {[25'h010_0000:25'h010_7FFF]};
|
||||
}
|
||||
option.per_instance = 1;
|
||||
endgroup
|
||||
|
||||
covergroup DATAAddr;
|
||||
coverpoint m_trans.addr{
|
||||
bins DATA[8192] = {[25'h020_0000:25'h020_7FFF]};
|
||||
}
|
||||
option.per_instance = 1;
|
||||
endgroup
|
||||
|
||||
covergroup CTRAddr;
|
||||
coverpoint m_trans.addr{
|
||||
bins MCUPARAR0 = {[25'h30_0000:25'h30_0003]};
|
||||
bins MCUPARAR1 = {[25'h30_0004:25'h30_0007]};
|
||||
bins MCUPARAR2 = {[25'h30_0008:25'h30_000B]};
|
||||
bins MCUPARAR3 = {[25'h30_000C:25'h30_000F]};
|
||||
bins MCURESR0 = {[25'h30_0010:25'h30_0013]};
|
||||
bins MCURESR1 = {[25'h30_0014:25'h30_0017]};
|
||||
bins MCURESR2 = {[25'h30_0018:25'h30_001B]};
|
||||
bins MCURESR3 = {[25'h30_001C:25'h30_001F]};
|
||||
bins RTIMR = {[25'h30_0098:25'h30_009B]};
|
||||
bins ICNTR = {[25'h30_009C:25'h30_009F]};
|
||||
bins FSIR = {[25'h30_00A0:25'h30_00A3]};
|
||||
bins MODMR = {[25'h30_0100:25'h30_0103]};
|
||||
bins INTPMR = {[25'h30_0104:25'h30_0107]};
|
||||
bins MIXNCOCR = {[25'h30_0108:25'h30_010B]};
|
||||
bins MIXNFCWHR = {[25'h30_010C:25'h30_010F]};
|
||||
bins MIXNFCWLR = {[25'h30_0110:25'h30_0113]};
|
||||
bins MIXNPHAR = {[25'h30_0114:25'h30_0117]};
|
||||
bins MIXMR = {[25'h30_0118:25'h30_011B]};
|
||||
bins MIXODTR = {[25'h30_011C:25'h30_011F]};
|
||||
bins MIXODFR = {[25'h30_0120:25'h30_0123]};
|
||||
|
||||
bins ROLER = {[25'h30_0128:25'h30_012B]};
|
||||
bins MIXNCOSCER = {[25'h30_012C:25'h30_012F]};
|
||||
bins MODDOTR = {[25'h30_0130:25'h30_0133]};
|
||||
bins STR = {[25'h30_0134:25'h30_0137]};
|
||||
}
|
||||
option.per_instance = 1;
|
||||
endgroup
|
||||
|
||||
covergroup ENVELOPEIDAddr;
|
||||
coverpoint m_trans.addr{
|
||||
bins ENVELOPEID[64] = {[25'h040_0000:25'h040_00FF]};
|
||||
}
|
||||
option.per_instance = 1;
|
||||
endgroup
|
||||
|
||||
covergroup ENVELOPEDATAAddr;
|
||||
coverpoint m_trans.addr{
|
||||
bins ENVELOPEDATA[8192] = {[25'h050_0000:25'h050_7FFF]};
|
||||
}
|
||||
option.per_instance = 1;
|
||||
endgroup
|
||||
|
||||
covergroup DACAddr;
|
||||
coverpoint m_trans.addr{
|
||||
bins PRBSCR = {[25'h060_0000:25'h060_0003]};
|
||||
bins SET0CR = {[25'h060_0004:25'h060_0007]};
|
||||
bins SET1CR = {[25'h060_0008:25'h060_000B]};
|
||||
bins SET2CR = {[25'h060_000C:25'h060_000F]};
|
||||
bins SET3CR = {[25'h060_0010:25'h060_0013]};
|
||||
bins SET4CR = {[25'h060_0014:25'h060_0017]};
|
||||
bins SET5CR = {[25'h060_0018:25'h060_001B]};
|
||||
bins SET6CR = {[25'h060_001C:25'h060_001F]};
|
||||
bins SET7CR = {[25'h060_0020:25'h060_0023]};
|
||||
bins SET8CR = {[25'h060_0024:25'h060_0027]};
|
||||
bins SET9CR = {[25'h060_0028:25'h060_002B]};
|
||||
bins SET10CR = {[25'h060_002C:25'h060_002F]};
|
||||
bins SET11CR = {[25'h060_0030:25'h060_0033]};
|
||||
bins SET12CR = {[25'h060_0034:25'h060_0037]};
|
||||
bins SET13CR = {[25'h060_0038:25'h060_003B]};
|
||||
bins SET14CR = {[25'h060_003C:25'h060_003F]};
|
||||
bins SET15CR = {[25'h060_0040:25'h060_0043]};
|
||||
bins DACADDR = {[25'h060_0044:25'h060_0047]};
|
||||
bins DACDW = {[25'h060_0048:25'h060_004B]};
|
||||
bins DACREF = {[25'h060_004C:25'h060_004F]};
|
||||
bins PRBSRST0 = {[25'h060_0050:25'h060_0053]};
|
||||
bins PRBSSET0 = {[25'h060_0054:25'h060_0057]};
|
||||
bins PRBSRST1 = {[25'h060_0058:25'h060_005B]};
|
||||
bins PRBSSET1 = {[25'h060_005C:25'h060_005F]};
|
||||
bins PRBSREV = {[25'h060_0060:25'h060_0063]};
|
||||
bins CALSIG = {[25'h060_0064:25'h060_0067]};
|
||||
bins CALEND = {[25'h060_0068:25'h060_006B]};
|
||||
bins CALRSTN = {[25'h060_006C:25'h060_006F]};
|
||||
bins CALDIVRSTN = {[25'h060_0070:25'h060_0073]};
|
||||
}
|
||||
option.per_instance = 1;
|
||||
endgroup
|
||||
|
||||
covergroup MCUAddr;
|
||||
coverpoint m_trans.addr{
|
||||
bins MCUPARAR0 = {[25'h70_0000:25'h70_0003]};
|
||||
bins MCUPARAR1 = {[25'h70_0004:25'h70_0007]};
|
||||
bins MCUPARAR2 = {[25'h70_0008:25'h70_000B]};
|
||||
bins MCUPARAR3 = {[25'h70_000C:25'h70_000F]};
|
||||
bins MCURESR0 = {[25'h70_0010:25'h70_0013]};
|
||||
bins MCURESR1 = {[25'h70_0014:25'h70_0017]};
|
||||
bins MCURESR2 = {[25'h70_0018:25'h70_001B]};
|
||||
bins MCURESR3 = {[25'h70_001C:25'h70_001F]};
|
||||
bins CWFR0 = {[25'h70_0040:25'h70_0043]};
|
||||
bins CWFR1 = {[25'h70_0044:25'h70_0047]};
|
||||
bins CWFR2 = {[25'h70_0048:25'h70_004B]};
|
||||
bins CWFR3 = {[25'h70_004C:25'h70_004F]};
|
||||
bins CWPRR = {[25'h70_0050:25'h70_0053]};
|
||||
bins GAPR0 = {[25'h70_0054:25'h70_0057]};
|
||||
bins GAPR1 = {[25'h70_0058:25'h70_005B]};
|
||||
bins GAPR2 = {[25'h70_005C:25'h70_005F]};
|
||||
bins GAPR3 = {[25'h70_0060:25'h70_0063]};
|
||||
bins GAPR4 = {[25'h70_0064:25'h70_0067]};
|
||||
bins GAPR5 = {[25'h70_0068:25'h70_006B]};
|
||||
bins GAPR6 = {[25'h70_006C:25'h70_006F]};
|
||||
bins GAPR7 = {[25'h70_0070:25'h70_0073]};
|
||||
bins LCPR = {[25'h70_0074:25'h70_0077]};
|
||||
bins AMPR0 = {[25'h70_0078:25'h70_007B]};
|
||||
bins AMPR1 = {[25'h70_007C:25'h70_007F]};
|
||||
bins AMPR2 = {[25'h70_0080:25'h70_0083]};
|
||||
bins AMPR3 = {[25'h70_0084:25'h70_0087]};
|
||||
bins BIASR0 = {[25'h70_0088:25'h70_008B]};
|
||||
bins BIASR1 = {[25'h70_008C:25'h70_008F]};
|
||||
bins BIASR2 = {[25'h70_0090:25'h70_0093]};
|
||||
bins BIASR3 = {[25'h70_0094:25'h70_0097]};
|
||||
bins RTIMR = {[25'h70_0098:25'h70_009B]};
|
||||
bins ICNTR = {[25'h70_009C:25'h70_009F]};
|
||||
bins FSIR = {[25'h70_00A0:25'h70_00A3]};
|
||||
bins INTPSELR = {[25'h70_00A4:25'h70_00A7]};
|
||||
}
|
||||
option.per_instance = 1;
|
||||
endgroup
|
||||
|
||||
covergroup DBGAddr;
|
||||
coverpoint m_trans.addr{
|
||||
bins DBGAddr[1024] = {[25'h190_0000:25'h190_0FFF]};
|
||||
}
|
||||
option.per_instance = 1;
|
||||
endgroup
|
||||
|
||||
|
||||
covergroup PLLAddr;
|
||||
coverpoint m_trans.addr{
|
||||
bins INTPLL_REFCTRL = {[25'h1f0_0000:25'h1f0_0003]};
|
||||
bins INTPLL_PCNT = {[25'h1f0_0004:25'h1f0_0007]};
|
||||
bins INTPLL_PFDCTRL = {[25'h1f0_0008:25'h1f0_000B]};
|
||||
bins INTPLL_SPDCTRL = {[25'h1f0_000C:25'h1f0_000F]};
|
||||
bins INTPLL_PTATCTRL = {[25'h1f0_0010:25'h1f0_0013]};
|
||||
bins INTPLL_FLLCTRL = {[25'h1f0_0014:25'h1f0_0017]};
|
||||
bins INTPLL_SELCTRL = {[25'h1f0_0018:25'h1f0_001B]};
|
||||
bins INTPLL_VCOCTRL = {[25'h1f0_001C:25'h1f0_001F]};
|
||||
bins INTPLL_VCOFBADJ = {[25'h1f0_0020:25'h1f0_0023]};
|
||||
bins INTPLL_AFCCTRL = {[25'h1f0_0024:25'h1f0_0027]};
|
||||
bins INTPLL_AFCCNT = {[25'h1f0_0028:25'h1f0_002B]};
|
||||
bins INTPLL_AFCLDCNT = {[25'h1f0_002C:25'h1f0_002F]};
|
||||
bins INTPLL_AFCPRES = {[25'h1f0_0030:25'h1f0_0033]};
|
||||
bins INTPLL_AFCLDTCC = {[25'h1f0_0034:25'h1f0_0037]};
|
||||
bins INTPLL_AFCFBTCC = {[25'h1f0_0038:25'h1f0_003B]};
|
||||
bins INTPLL_DIVCFG = {[25'h1f0_003C:25'h1f0_003F]};
|
||||
bins INTPLL_TCLKCFG = {[25'h1f0_0040:25'h1f0_0043]};
|
||||
bins INTPLL_DCLKSEL = {[25'h1f0_0044:25'h1f0_0047]};
|
||||
bins INTPLL_STATUS = {[25'h1f0_0048:25'h1f0_004B]};
|
||||
bins INTPLL_SYNCFG = {[25'h1f0_004C:25'h1f0_004F]};
|
||||
bins INTPLL_UPDATE = {[25'h1f0_0050:25'h1f0_0053]};
|
||||
bins INTPLL_CLKRXPD = {[25'h1f0_0054:25'h1f0_0057]};
|
||||
}
|
||||
option.per_instance = 1;
|
||||
endgroup
|
||||
|
||||
|
||||
function new();
|
||||
SYSAddr = new();
|
||||
INSTRAddr = new();
|
||||
DATAAddr = new();
|
||||
CTRAddr = new();
|
||||
ENVELOPEIDAddr = new();
|
||||
ENVELOPEDATAAddr = new();
|
||||
DACAddr = new();
|
||||
MCUAddr = new();
|
||||
DBGAddr = new();
|
||||
PLLAddr = new();
|
||||
endfunction
|
||||
extern task do_drive();
|
||||
extern task make_pkt(spi_trans tr);
|
||||
|
||||
endclass : spi_driver
|
||||
|
||||
task spi_driver::do_drive();
|
||||
|
||||
$display("pkt_num:\t%0d",pktnum);
|
||||
|
||||
while(!vif.rstn) begin
|
||||
vif.csn = 1'b1;
|
||||
vif.sclk = 1'b1;
|
||||
@(posedge vif.clk);
|
||||
end
|
||||
|
||||
while(pktnum>0) begin
|
||||
m_trans = new();
|
||||
|
||||
if(!m_trans.randomize() with {
|
||||
cmd==my_cmd;
|
||||
(cmd==1'b0 || data.size()==last_size);
|
||||
(cmd==1'b0 || addr==last_addr);
|
||||
// addr[24:20] == 5'h0 || //sys
|
||||
// addr[24:20] == 5'h1 || //instruction srams
|
||||
// addr[24:20] == 5'h2 || //data srams
|
||||
// addr[24:20] == 5'h3 || //awg
|
||||
// addr[24:20] == 5'h4 || //envelope id srams
|
||||
// addr[24:20] == 5'h5 || //envelope data srams
|
||||
// addr[24:20] == 5'h6 || //dac
|
||||
// addr[24:20] == 5'h7 || //mcu
|
||||
// addr[24:20] == 5'h19 || //dbg srams
|
||||
// addr[24:20] == 5'h1F ; //pll
|
||||
addr[24: 20] == 5'h6;
|
||||
addr[1:0] == 0;
|
||||
// data.size == 2;
|
||||
interval == 50;
|
||||
})
|
||||
$fatal(0,"Randomize Failed");
|
||||
if(m_trans.cmd == 1'b0) begin
|
||||
last_addr = m_trans.addr;
|
||||
last_size = m_trans.data.size();
|
||||
end
|
||||
my_cmd = ~my_cmd;
|
||||
//Autarchy: Testcase force to assign some params
|
||||
interval = m_trans.interval;
|
||||
if(!autarchy) begin
|
||||
half_sclk = m_trans.half_sclk;
|
||||
end
|
||||
if((m_trans.addr <= 25'h000_001F) &&
|
||||
((m_trans.addr + (m_trans.data.size()-1) * 4) >= 25'h000_001C))
|
||||
m_trans.data[(25'h000_001C - m_trans.addr)/4] =
|
||||
m_trans.data[(25'h000_001C - m_trans.addr)/4] % 4 + 1;
|
||||
|
||||
|
||||
|
||||
make_pkt(m_trans);
|
||||
|
||||
// $display(m_trans.addr);
|
||||
|
||||
SYSAddr.sample();
|
||||
INSTRAddr.sample();
|
||||
DATAAddr.sample();
|
||||
CTRAddr.sample();
|
||||
ENVELOPEIDAddr.sample();
|
||||
ENVELOPEDATAAddr.sample();
|
||||
DACAddr.sample();
|
||||
MCUAddr.sample();
|
||||
DBGAddr.sample();
|
||||
PLLAddr.sample();
|
||||
|
||||
repeat(interval)
|
||||
@(posedge vif.clk);
|
||||
|
||||
pktnum--;
|
||||
end
|
||||
|
||||
|
||||
$finish(0);
|
||||
//$display(SYSAddr.get_inst_coverage());
|
||||
//$display(MCUAddr.get_inst_coverage());
|
||||
//$display(AWGAddr.get_inst_coverage());
|
||||
|
||||
endtask : do_drive
|
||||
|
||||
|
||||
task spi_driver::make_pkt(spi_trans tr);
|
||||
int i=0,j=0;
|
||||
int cs_time,mo_time;
|
||||
|
||||
//*****************initialize chip_select and input_clk******************//
|
||||
vif.csn <= 1'b1;
|
||||
vif.sclk <= 1'b1;
|
||||
vif.mosi <= stream[0];
|
||||
vif.cfgid <= tr.cfgid;
|
||||
@(posedge vif.clk);
|
||||
vif.csn <= 1'b0;
|
||||
vif.sclk <= 1'b1;
|
||||
|
||||
//unpack into bitstream
|
||||
stream.delete();
|
||||
tr.unpack(stream);
|
||||
|
||||
//mosi valid time: time for bitstream to be all sent
|
||||
//csn valid_time: maybe a delay after or ahead of mosi_finished
|
||||
mo_time = (stream.size()+1)*2*half_sclk;
|
||||
cs_time = (pktnum==1) ? (mo_time + error_time%mo_time) : mo_time;
|
||||
|
||||
//$display("***************************ONE PKT DRIVERED***************************");
|
||||
//$display("half_sclk:\t%0d\t\t\t\t\t\t **",half_sclk);
|
||||
//$display("interval:\t%0d\t\t\t\t\t\t **",interval);
|
||||
//$display("error_time:\t%0d\t\t\t\t\t\t **",error_time);
|
||||
//$display("data_size:\t%0d\t\t\t\t\t\t **",tr.data.size());
|
||||
//$display("cmd:\t\t%0d\t\t\t\t\t\t **",tr.cmd);
|
||||
//$display("id:\t\t%h\t\t\t\t\t\t **",tr.cfgid);
|
||||
//$display("addr:\t\t%h\t\t\t\t\t\t **",tr.addr);
|
||||
//$display(stream);
|
||||
//if(!tr.cmd)
|
||||
//for(i=0;i<tr.data.size;i++)
|
||||
//$display("mosi:\t\t%h\t\t **",tr.data[i]);
|
||||
|
||||
//********************drive the stream onto interface********************//
|
||||
fork
|
||||
|
||||
|
||||
//************************Make sclk************************//
|
||||
begin
|
||||
for(j=0;j<cs_time;j++) begin
|
||||
if(j % half_sclk == 0 && j!=0)
|
||||
vif.sclk <= ~vif.sclk;
|
||||
@(posedge vif.clk);
|
||||
end
|
||||
vif.sclk = 1'b1;
|
||||
@(posedge vif.clk);
|
||||
vif.csn = 1'b1;
|
||||
end
|
||||
|
||||
//************************Send data************************//
|
||||
begin
|
||||
for(i=0;i<mo_time;i++) begin
|
||||
// data will be sampled at posedge,
|
||||
// so prepare them at the negedge before each posedge
|
||||
if(i % (2*half_sclk) == half_sclk)begin
|
||||
vif.mosi <= stream[(i/half_sclk-1)/2];
|
||||
//$write(vif.mosi);
|
||||
//$display(i);
|
||||
end
|
||||
@(posedge vif.clk);
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
join
|
||||
|
||||
//$display("**********************************************************************");
|
||||
|
||||
endtask
|
||||
|
||||
|
|
@ -0,0 +1,171 @@
|
|||
class spi_trans;
|
||||
|
||||
//Properties for Randomizing the MOSI
|
||||
rand bit cmd;
|
||||
rand bit[24:0] addr;
|
||||
rand bit[ 4:0] cfgid;
|
||||
rand bit[31:0] data[$];
|
||||
|
||||
//Properties for Randomizing the pkt_sent process
|
||||
rand int interval;
|
||||
rand int half_sclk;
|
||||
|
||||
|
||||
constraint cstr {
|
||||
data.size() >= 1;
|
||||
data.size() <= 16;//not solid
|
||||
interval <= 1000;
|
||||
interval >= 0;
|
||||
half_sclk <= 32;
|
||||
half_sclk >= 4;
|
||||
//Select system_regfile
|
||||
(addr >= 25'h000_0000 &&
|
||||
//addr <= 25'h000_001F &&
|
||||
int'(addr) <= int'(25'h000_0023) - int'(data.size()*4) ||
|
||||
addr >= 25'h000_0028 &&
|
||||
//addr <= 25'h000_0037 &&
|
||||
int'(addr) <= int'(25'h000_003B) - int'(data.size()*4) &&
|
||||
addr != 25'h000_0020 &&
|
||||
addr != 25'h000_0024) ||
|
||||
(addr == 25'h000_0040) ||
|
||||
//Select instruction SRAMs 8192X32bit 32KB
|
||||
(addr >= 25'h010_0000 &&
|
||||
//addr <= 25'h010_7FFF &&
|
||||
int'(addr) <= 25'h010_8003 - data.size()*4) ||
|
||||
//Select data SRAMs 8192X32bit 32KB
|
||||
(addr >= 25'h020_0000 &&
|
||||
//addr <= 25'h020_7FFF &&
|
||||
int'(addr) <= 25'h020_8003 - data.size()*4) ||
|
||||
//Select awg_regfile
|
||||
(addr >= 25'h030_0000 &&
|
||||
//addr <= 25'h030_001F &&
|
||||
int'(addr) <= int'(25'h030_0023) - int'(data.size()*4)) ||
|
||||
(addr >= 25'h030_0098 &&
|
||||
//addr <= 25'h030_00A3 &&
|
||||
int'(addr) <= int'(25'h030_00A7) - int'(data.size()*4)) ||
|
||||
(addr >= 25'h030_0100 &&
|
||||
//addr <= 25'h030_0123 &&
|
||||
int'(addr) <= int'(25'h030_0127) - int'(data.size()*4)) ||
|
||||
(addr >= 25'h030_0128 &&
|
||||
//addr <= 25'h030_0137 &&
|
||||
int'(addr) <= int'(25'h030_013B) - int'(data.size()*4)) ||
|
||||
//Select envelope ID SRAMs 64X32bit 256B
|
||||
(addr >= 25'h040_0000 &&
|
||||
//addr <= 25'h040_00FF &&
|
||||
int'(addr) <= 25'h040_0103 - data.size()*4) ||
|
||||
//Select envelope data SRAMs 8192X32bit 32KB
|
||||
(addr >= 25'h050_0000 &&
|
||||
//addr <= 25'h050_7FFF &&
|
||||
int'(addr) <= 25'h050_8003 - data.size()*4) ||
|
||||
//Select dac_regfile
|
||||
(addr >= 25'h060_0000 &&
|
||||
//addr <= 25'h060_0073 &&
|
||||
int'(addr) <= int'(25'h060_0077) - int'(data.size()*4)) ||
|
||||
//Select mcu_regfile
|
||||
(addr >= 25'h070_0000 &&
|
||||
//addr <= 25'h070_01F &&
|
||||
int'(addr) <= int'(25'h070_0023) - int'(data.size()*4)) ||
|
||||
(addr >= 25'h070_0040 &&
|
||||
//addr <= 25'h070_00A7 &&
|
||||
int'(addr) <= int'(25'h070_00AB) - int'(data.size()*4)) ||
|
||||
//Select DBG SRAMs 256X128bit 4KB
|
||||
(addr >= 25'h190_0000 &&
|
||||
//addr <= 25'h190_0FFF &&
|
||||
int'(addr) <= 25'h190_1003 - data.size()*4) ||
|
||||
//Select intpll_regfile
|
||||
(addr >= 25'h1f0_0000 &&
|
||||
//addr <= 25'h1f0_0057 &&
|
||||
int'(addr) <= int'(25'h1f0_005B) - int'(data.size()*4)) ;
|
||||
}
|
||||
|
||||
function new();
|
||||
endfunction
|
||||
|
||||
extern function bit compare(spi_trans rhs_);
|
||||
extern function void print(integer fid);
|
||||
extern function void unpack(ref bit stream[$]);
|
||||
extern function void pack(bit stream[$]);
|
||||
|
||||
endclass : spi_trans
|
||||
|
||||
|
||||
|
||||
function bit spi_trans::compare(spi_trans rhs_);
|
||||
bit result=1'b1;
|
||||
int i=0;
|
||||
|
||||
result = ((cmd == rhs_.cmd) &&
|
||||
(addr == rhs_.addr) &&
|
||||
(cfgid == rhs_.cfgid));
|
||||
|
||||
if(this.data.size() != rhs_.data.size()) begin
|
||||
$display("data_sizes are different");
|
||||
result = 1'b0;
|
||||
end
|
||||
else
|
||||
for(i=0;i<data.size();i++)begin
|
||||
if(data[i] != rhs_.data[i])
|
||||
result = 1'b0;
|
||||
end
|
||||
|
||||
return result;
|
||||
endfunction : compare
|
||||
|
||||
|
||||
function void spi_trans::print(integer fid);
|
||||
int i=0;
|
||||
if(!cmd)$fwrite(fid,"----------ONE-PKT-DRIVEN----------\n");
|
||||
else $fwrite(fid,"---------ONE-PKT-COLLECTED--------\n");
|
||||
$fwrite(fid,"cmd:\t%h\n",cmd);
|
||||
$fwrite(fid,"addr:\t%h\n",addr);
|
||||
$fwrite(fid,"cfgid:\t%h\n",cfgid);
|
||||
for(i=0;i<data.size();i++)begin
|
||||
$fwrite(fid,"data[%2d]='h%h\n",i,data[i]);
|
||||
end
|
||||
endfunction : print
|
||||
|
||||
|
||||
function void spi_trans::unpack(ref bit stream[$]);
|
||||
int i=0,j=0;
|
||||
|
||||
stream[0]=cmd;
|
||||
|
||||
for(i=0;i<25;i++)
|
||||
stream[i+1] = addr[24-i];
|
||||
|
||||
for(i=0;i<5;i++)
|
||||
stream[i+26]= cfgid[4-i];
|
||||
|
||||
stream[31]=0;
|
||||
|
||||
for(i=0;i<data.size();i++)begin
|
||||
//$display("i=%2d,datai=%b",i,data[i]);
|
||||
for(j=0;j<32;j++)begin
|
||||
stream[32+i*32+j]=data[i][31-j];
|
||||
//$display("i=%2d,j=%2d,streamij=%b",i,j,stream[32+i*32+j]);
|
||||
end
|
||||
end
|
||||
|
||||
endfunction
|
||||
|
||||
function void spi_trans::pack(bit stream[$]);
|
||||
int i=0;
|
||||
bit[31:0] data_temp=32'b0;
|
||||
|
||||
cmd = stream.pop_front();
|
||||
|
||||
for(i=0;i<25;i++)
|
||||
addr[24-i] = stream.pop_front();
|
||||
|
||||
for(i=0;i<5;i++)
|
||||
cfgid[4-i] = stream.pop_front();
|
||||
|
||||
//reserved
|
||||
stream.pop_front();
|
||||
|
||||
while(stream.size()>0)begin
|
||||
for(i=0;i<32;i++)
|
||||
data_temp[31-i] = stream.pop_front();
|
||||
data.push_back(data_temp);
|
||||
end
|
||||
endfunction
|
||||
|
|
@ -0,0 +1,281 @@
|
|||
//+FHDR--------------------------------------------------------------------------------------------------------
|
||||
// Company:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// File Name : awg_ctrl.v
|
||||
// Department :
|
||||
// Author : PWY
|
||||
// Author's Tel :
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Relese History
|
||||
// Version Date Author Description
|
||||
// 0.1 2024-03-13 PWY Envelope readout, modulation NCO control, and interpolator selection
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Keywords :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Parameter
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Purpose :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Target Device:
|
||||
// Tool versions:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Reuse Issues
|
||||
// Reset Strategy:
|
||||
// Clock Domains:
|
||||
// Critical Timing:
|
||||
// Asynchronous I/F:
|
||||
// Synthesizable (y/n):
|
||||
// Other:
|
||||
//-FHDR--------------------------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
///////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
//Key timing diagram
|
||||
///////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
// -------------------------------------
|
||||
// | |
|
||||
//wave_hold_i - -----------------------
|
||||
// -------------------------------------
|
||||
// | |
|
||||
//wave_hold --------- ---------------
|
||||
// -------------------------------------
|
||||
// | |
|
||||
//wave_hold_r1 -------------- -----------
|
||||
// -------------------------------------
|
||||
// | |
|
||||
//wave_hold_2 ------------------ --------
|
||||
// ---- ----
|
||||
// | | | |
|
||||
//ilde2read ---- -------------------------------- ---------------
|
||||
// ----
|
||||
// | |
|
||||
//read2idle --------------------------------- ---------------------
|
||||
// ---------------------------------------------------------------
|
||||
//state_c | idle | read | idle | read
|
||||
// ---------------------------------------------------------------
|
||||
// ---------------------------------------------------------------
|
||||
//state_n | idle | read | idle | read
|
||||
// ---------------------------------------------------------------
|
||||
// ---------------------------------------------------------------
|
||||
//enve_rddata_i | invalid | valid | idle | valid
|
||||
// ---------------------------------------------------------------
|
||||
// ----
|
||||
// | |
|
||||
//end_cnt_r ------------------------------------ ---------------------
|
||||
// ---------------------------------------------------------------
|
||||
//last_rddata | invalid | enve_rddata_i
|
||||
// ---------------------------------------------------------------
|
||||
// ---------------------------------------------------------------
|
||||
//enve_data_w | invalid | enve_rddata_i | last_rddata |
|
||||
// ---------------------------------------------------------------
|
||||
// ------------------------- ----------
|
||||
// | | |
|
||||
//enve_vld_w ---------------- -----------
|
||||
// ------------------------------------------
|
||||
// |
|
||||
//enve_vld_o ----------------
|
||||
|
||||
//After two cycles of a valid signal(enve_index_vld_i), output the envelope data(enve_idata_o & enve_qdata_o & enve_vld_o)
|
||||
|
||||
module awg_ctrl (
|
||||
//system port
|
||||
input clk // System Main Clock
|
||||
,input rst_n // Spi Reset active low
|
||||
//Envelope index Information
|
||||
,input enve_index_vld_i
|
||||
,input [15 :0] enve_start_addr_i
|
||||
,input [15 :0] enve_len_i
|
||||
,input wave_hold_i
|
||||
//Envelope memory read signals
|
||||
,output enve_rden_o
|
||||
,output [15 :0] enve_rdaddr_o
|
||||
,input [31 :0] enve_rddata_i
|
||||
//Envelope outpiut
|
||||
,output [15 :0] enve_idata_o
|
||||
,output [15 :0] enve_qdata_o
|
||||
,output [0 :0] enve_vld_o
|
||||
//Envelope read fsm status
|
||||
,output [0 :0] enve_read_fsm_st_o
|
||||
//Process conflict
|
||||
,output proc_cft_o
|
||||
//modulation NCO control signals
|
||||
//Data from the lookup table
|
||||
,input [31:0] muc_mod_nco_fcw_i
|
||||
,input [15:0] muc_mod_nco_pha_i
|
||||
,input [15:0] muc_mod_nco_rz_pha_i
|
||||
,input muc_mod_pha_clr_i
|
||||
//Modulating nCO control signal output
|
||||
,output [31:0] mod_nco_fcw_o
|
||||
,output [15:0] mod_nco_pha_o
|
||||
,output mod_pha_clr_o
|
||||
//Other parameters register
|
||||
,input [15:0] muc_mod_amp_i
|
||||
,input [15:0] muc_z_bais_i
|
||||
,output [15:0] mod_amp_o
|
||||
,output [15:0] z_bais_o
|
||||
|
||||
);
|
||||
|
||||
|
||||
localparam IDLE = 1'b0,
|
||||
READ = 1'b1;
|
||||
|
||||
|
||||
|
||||
wire [0:0] state_c;
|
||||
wire [0:0] state_n;
|
||||
wire ilde2read;
|
||||
wire read2idle;
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
//Envelope readout
|
||||
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
// ------------------------------------------------------
|
||||
// -- read envelope memory count
|
||||
// ------------------------------------------------------
|
||||
wire [15:0] enve_len;
|
||||
wire [15:0] cnt_c;
|
||||
|
||||
wire add_cnt = (state_c == READ );
|
||||
|
||||
wire end_cnt = add_cnt & (cnt_c == enve_len-1);
|
||||
|
||||
wire [15:0] cnt_n = end_cnt ? 32'h0 :
|
||||
add_cnt ? cnt_c + 1'b1 :
|
||||
cnt_c ;
|
||||
|
||||
|
||||
sirv_gnrl_dffr #(16) cnt_c_dffr (cnt_n, cnt_c, clk, rst_n);
|
||||
//The first section of the state machine
|
||||
//state_c
|
||||
sirv_gnrl_dffr #(1) state_c_dffr (state_n, state_c, clk, rst_n);
|
||||
|
||||
//////////////////////////////////////////////////////////////
|
||||
//fsm
|
||||
//////////////////////////////////////////////////////////////
|
||||
|
||||
//state_n
|
||||
assign state_n = ((state_c == IDLE ) && ilde2read ) ? READ :
|
||||
((state_c == READ ) && read2idle ) ? IDLE :
|
||||
state_c ;
|
||||
|
||||
//Generating jump conditions for state machines
|
||||
assign ilde2read = (state_c == IDLE ) && enve_index_vld_i;
|
||||
assign read2idle = (state_c == READ ) && end_cnt && ~enve_index_vld_i;
|
||||
|
||||
/////////////////////////////////////////////////////////////////////
|
||||
//Signal Latching
|
||||
/////////////////////////////////////////////////////////////////////
|
||||
|
||||
//enve_start_addr
|
||||
wire [15:0] enve_start_addr;
|
||||
//sirv_gnrl_dfflr #(16) enve_start_addr_dfflr (ilde2read, enve_start_addr_i, enve_start_addr, clk, rst_n);
|
||||
sirv_gnrl_dfflr #(16) enve_start_addr_dfflr (enve_index_vld_i, enve_start_addr_i, enve_start_addr, clk, rst_n);
|
||||
//enve_len
|
||||
|
||||
//sirv_gnrl_dfflr #(16) enve_len_dfflr (ilde2read, enve_len_i, enve_len, clk, rst_n);
|
||||
sirv_gnrl_dfflr #(16) enve_len_dfflr (enve_index_vld_i, enve_len_i, enve_len, clk, rst_n);
|
||||
|
||||
//wave_hold
|
||||
wire wave_hold;
|
||||
//sirv_gnrl_dfflr #(1) wave_hold_dfflr (ilde2read, wave_hold_i, wave_hold, clk, rst_n);
|
||||
sirv_gnrl_dfflr #(1) wave_hold_dfflr (enve_index_vld_i, wave_hold_i, wave_hold, clk, rst_n);
|
||||
wire wave_hold_r1;
|
||||
sirv_gnrl_dffr #(1) wave_hold_r1_dffr (wave_hold, wave_hold_r1, clk, rst_n);
|
||||
wire wave_hold_r2;
|
||||
sirv_gnrl_dffr #(1) wave_hold_r2_dffr (wave_hold_r1, wave_hold_r2, clk, rst_n);
|
||||
|
||||
|
||||
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- Generate Read Envelope Storage Signal
|
||||
// ------------------------------------------------------
|
||||
|
||||
assign enve_rden_o = (state_c == READ );
|
||||
assign enve_rdaddr_o = enve_start_addr + (cnt_c << 2);
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- Receive envelope data
|
||||
// ------------------------------------------------------
|
||||
|
||||
//Lock and store the last piece of data
|
||||
|
||||
wire end_cnt_r;
|
||||
sirv_gnrl_dffr #(1) end_cnt_r_dffr (end_cnt, end_cnt_r, clk, rst_n);
|
||||
|
||||
wire [31:0] last_rddata;
|
||||
sirv_gnrl_dfflr #(32) last_rddata_dfflr (end_cnt_r, enve_rddata_i[31 :0], last_rddata, clk, rst_n);
|
||||
|
||||
//enve_vld_w
|
||||
wire enve_vld_w = enve_rden_o | wave_hold_r1;
|
||||
wire [1:0] enve_vld_r;
|
||||
|
||||
//wire [31:0] enve_data_w = {32{enve_vld_r[0]}} & enve_rddata_i
|
||||
// | {32{wave_hold_r2 }} & last_rddata ;
|
||||
|
||||
//M--20240516
|
||||
wire [31:0] enve_data_w = enve_vld_r[0] ? enve_rddata_i :
|
||||
wave_hold_r2 ? last_rddata :
|
||||
32'h0;
|
||||
|
||||
sirv_gnrl_dffr #(2) enve_vld_r_dffr ({enve_vld_r[0],enve_vld_w}, enve_vld_r, clk, rst_n);
|
||||
//enve_vld_o
|
||||
assign enve_vld_o = enve_vld_r[1];
|
||||
|
||||
//enve_idata_o
|
||||
sirv_gnrl_dffr #(16) enve_idata_o_dffr (enve_data_w[31:16], enve_idata_o, clk, rst_n);
|
||||
//enve_qdata_o
|
||||
sirv_gnrl_dffr #(16) enve_qdata_o_dffr (enve_data_w[15 :0], enve_qdata_o, clk, rst_n);
|
||||
|
||||
|
||||
//Process conflict
|
||||
wire proc_cft_w = (state_c == READ ) & enve_index_vld_i & ~end_cnt;
|
||||
sirv_gnrl_dffr #(1) proc_cft_dffr (proc_cft_w, proc_cft_o, clk, rst_n);
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
//NCO control
|
||||
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
//---------------------------------------------------------------------------------------------
|
||||
//To ensure the stability of the NCO control signals throughout the entire readout process,
|
||||
//the state machine locks the NCO control signals upon entering the readout state.
|
||||
//---------------------------------------------------------------------------------------------
|
||||
wire [1:0] ilde2read_r;
|
||||
sirv_gnrl_dffr #(2) ilde2read_r_dffr ({ilde2read_r[0],enve_index_vld_i}, ilde2read_r, clk, rst_n);
|
||||
//----------------------------------------------------------
|
||||
//Modulation NCO frequency-controlled word processing
|
||||
//----------------------------------------------------------
|
||||
|
||||
//Align the frequency-controlled word with the envelope output signal in timing
|
||||
sirv_gnrl_dfflr #(32) mod_nco_fcw_o_dfflr (enve_index_vld_i, muc_mod_nco_fcw_i, mod_nco_fcw_o, clk, rst_n);
|
||||
|
||||
//----------------------------------------------------------
|
||||
//Modulation NCO phase control word processing
|
||||
//----------------------------------------------------------
|
||||
|
||||
//Align the phase control word with the envelope output signal in timing
|
||||
|
||||
sirv_gnrl_dfflr #(16) mod_nco_pha_r_dfflr (enve_index_vld_i, muc_mod_nco_pha_i + muc_mod_nco_rz_pha_i, mod_nco_pha_o, clk, rst_n);
|
||||
|
||||
|
||||
//----------------------------------------------------------
|
||||
//Modulating NCO phase clean signal processing
|
||||
//----------------------------------------------------------
|
||||
assign mod_pha_clr_o = muc_mod_pha_clr_i;
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
//mod_amp_o & z_bais_o
|
||||
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
//Align the mod_amp_o with the envelope output signal in timing
|
||||
sirv_gnrl_dfflr #(16) mod_amp_o_dfflr (ilde2read_r[1], muc_mod_amp_i, mod_amp_o, clk, rst_n);
|
||||
|
||||
//Align the z_bais_o with the envelope output signal in timing
|
||||
sirv_gnrl_dfflr #(16) z_bais_o_dfflr (ilde2read_r[1], muc_z_bais_i, z_bais_o, clk, rst_n);
|
||||
|
||||
//enve_read_fsm_st_o
|
||||
assign enve_read_fsm_st_o = state_c;
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,430 @@
|
|||
//+FHDR--------------------------------------------------------------------------------------------------------
|
||||
// Company:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// File Name : awg_top.v
|
||||
// Department :
|
||||
// Author : PWY
|
||||
// Author's Tel :
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Relese History
|
||||
// Version Date Author Description
|
||||
// 0.1 2024-03-13 PWY MCU dedicated register file
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Keywords :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Parameter
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Purpose :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Target Device:
|
||||
// Tool versions:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Reuse Issues
|
||||
// Reset Strategy:
|
||||
// Clock Domains:
|
||||
// Critical Timing:
|
||||
// Asynchronous I/F:
|
||||
// Synthesizable (y/n):
|
||||
// Other:
|
||||
//-FHDR--------------------------------------------------------------------------------------------------------
|
||||
|
||||
module awg_top (
|
||||
//system port
|
||||
input clk // System Main Clock
|
||||
,input rst_n // Spi Reset active low
|
||||
//----------------------------from mcu-----------------------------------------------------------
|
||||
//lookup table data
|
||||
,input [31 :0] mcu_cwfr [3:0] // Carrier frequency ctrl word 0~3
|
||||
,input [15 :0] mcu_gapr [7:0] // Carrier phase ctrl word 0~7
|
||||
,input [15 :0] mcu_ampr [3:0] // Amplitude 0~3
|
||||
,input [15 :0] mcu_baisr [3:0] // Bais 0~3
|
||||
//CFG Port
|
||||
,input mcu_nco_pha_clr
|
||||
,input [15 :0] mcu_rz_pha
|
||||
// The operands and info to peripheral
|
||||
,input send
|
||||
,input sendc
|
||||
,input [31 :0] codeword
|
||||
,input [1 :0] fb_st
|
||||
//----------------------------from spi-----------------------------------------------------------
|
||||
//Envelope storage read/write signal
|
||||
,input [31 :0] enve_bwrdata
|
||||
,input [0 :0] enve_bwren
|
||||
,input [14 :0] enve_brwaddr
|
||||
,input [0 :0] enve_brden
|
||||
,output [31 :0] enve_brddata
|
||||
//envelope index lookup table read-write signal
|
||||
,input [31 :0] enve_id_bwrdata
|
||||
,input [0 :0] enve_id_bwren
|
||||
,input [7 :0] enve_id_brwaddr
|
||||
,input [0 :0] enve_id_brden
|
||||
,output [31 :0] enve_id_brddata
|
||||
//----------------------------to ctrl regfile------------------------------------------------------
|
||||
//Envelope read fsm status
|
||||
,output [0 :0] enve_read_fsm_st
|
||||
//Process conflict
|
||||
,output proc_cft
|
||||
//----------------------------from ctrl regfile------------------------------------------------------
|
||||
,input mod_sideband_sel //1'b0: Mod_data_i = Icoswd+Qsinwd, Mod_data_q = Isinwd+Qcoswd
|
||||
//1'b1: Mod_data_i = Icoswd-Qsinwd, Mod_data_q = -Isinwd+Qcoswd
|
||||
,input mod_pha_sfot_clr
|
||||
,input [1 :0] role_sel //[0] --> 1'b0: xy-chip;1'b1: z-chip;
|
||||
//[1] --> 1'b0: AC mode;1'b1: DC mode;
|
||||
,input mod_dout_sel //1'b0 --> mod modem data; 1'b1 --> mod nco data
|
||||
//1'b1 --> awg output data always vaild;
|
||||
//----------------------------to DSP----------------------------------------------------------------
|
||||
//Output awg data
|
||||
,output [15 :0] awg_data_i
|
||||
,output [15 :0] awg_data_q
|
||||
,output awg_vld
|
||||
,output bais_i_ov
|
||||
,output bais_q_ov
|
||||
);
|
||||
|
||||
//------------------------------------------------------------------------------------------
|
||||
//codeword decode
|
||||
//------------------------------------------------------------------------------------------
|
||||
wire wave_hold ;
|
||||
wire [1 :0] bais_index ;
|
||||
wire [1 :0] amp_index ;
|
||||
wire [2 :0] nco_pha_index ;
|
||||
wire [1 :0] nco_fcw_index ;
|
||||
wire [7 :0] envelope_index ;
|
||||
wire index_vld ;
|
||||
codeword_decode U_codeword_decode (
|
||||
.clk ( clk )
|
||||
,.rst_n ( rst_n )
|
||||
,.send_i ( send )
|
||||
,.sendc_i ( sendc )
|
||||
,.codeword_i ( codeword )
|
||||
,.fb_st_i ( fb_st )
|
||||
,.wave_hold_o ( wave_hold )
|
||||
,.bais_index_o ( bais_index )
|
||||
,.amp_index_o ( amp_index )
|
||||
,.nco_pha_index_o ( nco_pha_index )
|
||||
,.nco_fcw_index_o ( nco_fcw_index )
|
||||
,.envelope_index_o ( envelope_index )
|
||||
,.index_vld_o ( index_vld )
|
||||
);
|
||||
|
||||
//------------------------------------------------------------------------------------------
|
||||
//Carrier frequency ctrl word LUT
|
||||
//------------------------------------------------------------------------------------------
|
||||
wire [31:0] mod_nco_fcw_i;
|
||||
param_lut #(
|
||||
.DXLEN ( 32 )
|
||||
,.PNUM ( 4 )
|
||||
) fcw_lut (
|
||||
.clk ( clk )
|
||||
,.rst_n ( rst_n )
|
||||
,.param_i ( mcu_cwfr )
|
||||
,.index_i ( nco_fcw_index )
|
||||
,.index_vld_i ( index_vld )
|
||||
,.param_o ( mod_nco_fcw_i )
|
||||
);
|
||||
|
||||
//------------------------------------------------------------------------------------------
|
||||
//Carrier phase ctrl word 0~7
|
||||
//------------------------------------------------------------------------------------------
|
||||
wire [15:0] mod_nco_pha_i;
|
||||
param_lut #(
|
||||
.DXLEN ( 16 )
|
||||
,.PNUM ( 8 )
|
||||
) pha_lut (
|
||||
.clk ( clk )
|
||||
,.rst_n ( rst_n )
|
||||
,.param_i ( mcu_gapr )
|
||||
,.index_i ( nco_pha_index )
|
||||
,.index_vld_i ( index_vld )
|
||||
,.param_o ( mod_nco_pha_i )
|
||||
);
|
||||
|
||||
//------------------------------------------------------------------------------------------
|
||||
// Amplitude 0~3
|
||||
//------------------------------------------------------------------------------------------
|
||||
wire [15:0] mod_amp_i;
|
||||
param_lut #(
|
||||
.DXLEN ( 16 )
|
||||
,.PNUM ( 4 )
|
||||
) ampr_lut (
|
||||
.clk ( clk )
|
||||
,.rst_n ( rst_n )
|
||||
,.param_i ( mcu_ampr )
|
||||
,.index_i ( amp_index )
|
||||
,.index_vld_i ( index_vld )
|
||||
,.param_o ( mod_amp_i )
|
||||
);
|
||||
|
||||
//------------------------------------------------------------------------------------------
|
||||
// Bais 0~3
|
||||
//------------------------------------------------------------------------------------------
|
||||
wire [15:0] z_bais_i;
|
||||
param_lut #(
|
||||
.DXLEN ( 16 )
|
||||
,.PNUM ( 4 )
|
||||
) bais_lut (
|
||||
.clk ( clk )
|
||||
,.rst_n ( rst_n )
|
||||
,.param_i ( mcu_baisr )
|
||||
,.index_i ( bais_index )
|
||||
,.index_vld_i ( index_vld )
|
||||
,.param_o ( z_bais_i )
|
||||
);
|
||||
|
||||
//------------------------------------------------------------------------------------------
|
||||
// enve_id_dpram
|
||||
//------------------------------------------------------------------------------------------
|
||||
|
||||
wire enve_index_vld ;
|
||||
sirv_gnrl_dffr #(1) enve_index_vld_dffr (index_vld, enve_index_vld, clk, rst_n);
|
||||
|
||||
//Envelope LUT Clock
|
||||
wire [0 :0] Enve_Id_PortClk = clk ;
|
||||
//The envelope LUT A port is connected to the internal codeword decode
|
||||
wire [7 :0] Enve_Id_PortAAddr = envelope_index << 2 ; //To align the address, the signal is left-shifted by 2 bits
|
||||
//as the memory bytes are presented in byte addresses
|
||||
wire [31 :0] Enve_Id_PortADataIn = 32'h0 ;
|
||||
wire [0 :0] Enve_Id_PortAWriteEnable = 1'b1 ;
|
||||
wire [0 :0] Enve_Id_PortAChipEnable = ~index_vld ;
|
||||
wire [32/8-1:0] Enve_Id_PortAByteWriteEnable = 4'b0000 ;
|
||||
wire [31 :0] Enve_Id_PortADataOut ;
|
||||
wire [31 :0] enve_id_info = Enve_Id_PortADataOut ;
|
||||
//The B port of the envelope LUT connects to an external SPI bus decode
|
||||
wire [7 :0] Enve_Id_PortBAddr = enve_id_brwaddr ;
|
||||
wire [31 :0] Enve_Id_PortBDataIn = enve_id_bwrdata ;
|
||||
wire [0 :0] Enve_Id_PortBWriteEnable = ~enve_id_bwren & enve_id_brden ;
|
||||
wire [0 :0] Enve_Id_PortBChipEnable = ~(enve_id_bwren | enve_id_brden) ;
|
||||
wire [32/8-1:0] Enve_Id_PortBByteWriteEnable = 4'b0000 ;
|
||||
wire [31 :0] Enve_Id_PortBDataOut ;
|
||||
assign enve_id_brddata = Enve_Id_PortBDataOut ;
|
||||
|
||||
wire [15 :0] enve_start_addr = enve_id_info[31:16];
|
||||
wire [15 :0] enve_len = enve_id_info[15:0 ];
|
||||
|
||||
dpram #(
|
||||
.DATAWIDTH ( 32 )
|
||||
,.ADDRWIDTH ( 8 )
|
||||
) enve_id_dpram (
|
||||
.PortClk ( Enve_Id_PortClk )
|
||||
,.PortAAddr ( Enve_Id_PortAAddr )
|
||||
,.PortADataIn ( Enve_Id_PortADataIn )
|
||||
,.PortAWriteEnable ( Enve_Id_PortAWriteEnable )
|
||||
,.PortAChipEnable ( Enve_Id_PortAChipEnable )
|
||||
,.PortAByteWriteEnable ( Enve_Id_PortAByteWriteEnable )
|
||||
,.PortADataOut ( Enve_Id_PortADataOut )
|
||||
,.PortBAddr ( Enve_Id_PortBAddr )
|
||||
,.PortBDataIn ( Enve_Id_PortBDataIn )
|
||||
,.PortBWriteEnable ( Enve_Id_PortBWriteEnable )
|
||||
,.PortBChipEnable ( Enve_Id_PortBChipEnable )
|
||||
,.PortBByteWriteEnable ( Enve_Id_PortBByteWriteEnable )
|
||||
,.PortBDataOut ( Enve_Id_PortBDataOut )
|
||||
);
|
||||
|
||||
//------------------------------------------------------------------------------------------
|
||||
// enve_id_dpram
|
||||
//------------------------------------------------------------------------------------------
|
||||
|
||||
wire enve_arden ;
|
||||
wire [15 :0] enve_ardaddr ;
|
||||
wire [31 :0] enve_arddata ;
|
||||
wire [15 :0] enve_idata ;
|
||||
wire [15 :0] enve_qdata ;
|
||||
wire [0 :0] enve_vld ;
|
||||
wire [31 :0] mod_nco_fcw ;
|
||||
wire [15 :0] mod_nco_pha ;
|
||||
wire mod_pha_clr ;
|
||||
wire [15 :0] mod_amp ;
|
||||
wire [15 :0] z_bais ;
|
||||
|
||||
awg_ctrl U_awg_ctrl (
|
||||
.clk ( clk )
|
||||
,.rst_n ( rst_n )
|
||||
,.enve_index_vld_i ( enve_index_vld )
|
||||
,.enve_start_addr_i ( enve_start_addr )
|
||||
,.enve_len_i ( enve_len )
|
||||
,.wave_hold_i ( wave_hold )
|
||||
,.enve_rden_o ( enve_arden )
|
||||
,.enve_rdaddr_o ( enve_ardaddr )
|
||||
,.enve_rddata_i ( enve_arddata )
|
||||
,.enve_idata_o ( enve_idata )
|
||||
,.enve_qdata_o ( enve_qdata )
|
||||
,.enve_vld_o ( enve_vld )
|
||||
,.enve_read_fsm_st_o ( enve_read_fsm_st )
|
||||
,.proc_cft_o ( proc_cft )
|
||||
,.muc_mod_nco_fcw_i ( mod_nco_fcw_i )
|
||||
,.muc_mod_nco_pha_i ( mod_nco_pha_i )
|
||||
,.muc_mod_nco_rz_pha_i ( mcu_rz_pha )
|
||||
,.muc_mod_pha_clr_i ( mcu_nco_pha_clr )
|
||||
,.muc_mod_amp_i ( mod_amp_i )
|
||||
,.muc_z_bais_i ( z_bais_i )
|
||||
,.mod_nco_fcw_o ( mod_nco_fcw )
|
||||
,.mod_nco_pha_o ( mod_nco_pha )
|
||||
,.mod_pha_clr_o ( mod_pha_clr )
|
||||
,.mod_amp_o ( mod_amp )
|
||||
,.z_bais_o ( z_bais )
|
||||
);
|
||||
|
||||
//------------------------------------------------------------------------------------------
|
||||
// envelope dpram
|
||||
//------------------------------------------------------------------------------------------
|
||||
|
||||
//Envelope Memory Clock
|
||||
wire [0 :0] Enve_PortClk = clk ;
|
||||
//The envelope storage A port is connected to the internal AWG controller
|
||||
wire [14 :0] Enve_PortAAddr = enve_ardaddr[14:0] ;
|
||||
wire [31 :0] Enve_PortADataIn = 32'h0 ;
|
||||
wire [0 :0] Enve_PortAWriteEnable = 1'b1 ;
|
||||
wire [0 :0] Enve_PortAChipEnable = ~enve_arden ;
|
||||
wire [32/8-1:0] Enve_PortAByteWriteEnable = 4'b0000 ;
|
||||
wire [31 :0] Enve_PortADataOut ;
|
||||
assign enve_arddata = Enve_PortADataOut ;
|
||||
//The B port of the envelope storage connects to an external SPI bus decode
|
||||
wire [14 :0] Enve_PortBAddr = enve_brwaddr[14:0] ;
|
||||
wire [31 :0] Enve_PortBDataIn = enve_bwrdata ;
|
||||
wire [0 :0] Enve_PortBWriteEnable = ~enve_bwren & enve_brden ;
|
||||
wire [0 :0] Enve_PortBChipEnable = ~(enve_bwren | enve_brden) ;
|
||||
wire [32/8-1:0] Enve_PortBByteWriteEnable = 4'b0000 ;
|
||||
wire [31 :0] Enve_PortBDataOut ;
|
||||
assign enve_brddata = Enve_PortBDataOut ;
|
||||
|
||||
dpram #(
|
||||
.DATAWIDTH ( 32 )
|
||||
,.ADDRWIDTH ( 15 )
|
||||
) enve_dpram (
|
||||
.PortClk ( Enve_PortClk )
|
||||
,.PortAAddr ( Enve_PortAAddr )
|
||||
,.PortADataIn ( Enve_PortADataIn )
|
||||
,.PortAWriteEnable ( Enve_PortAWriteEnable )
|
||||
,.PortAChipEnable ( Enve_PortAChipEnable )
|
||||
,.PortAByteWriteEnable ( Enve_PortAByteWriteEnable )
|
||||
,.PortADataOut ( Enve_PortADataOut )
|
||||
,.PortBAddr ( Enve_PortBAddr )
|
||||
,.PortBDataIn ( Enve_PortBDataIn )
|
||||
,.PortBWriteEnable ( Enve_PortBWriteEnable )
|
||||
,.PortBChipEnable ( Enve_PortBChipEnable )
|
||||
,.PortBByteWriteEnable ( Enve_PortBByteWriteEnable )
|
||||
,.PortBDataOut ( Enve_PortBDataOut )
|
||||
);
|
||||
|
||||
//------------------------------------------------------------------------------------------
|
||||
// mod nco
|
||||
//------------------------------------------------------------------------------------------
|
||||
wire [15:0] mod_nco_sin;
|
||||
wire [15:0] mod_nco_cos;
|
||||
|
||||
NCO_CH1 U_mod_nco (
|
||||
.clk ( clk )
|
||||
,.rstn ( rst_n )
|
||||
,.phase_manual_clr ( mod_pha_clr )
|
||||
,.phase_auto_clr ( mod_pha_sfot_clr )
|
||||
,.fcw ( {mod_nco_fcw,16'h0} )
|
||||
,.pha ( mod_nco_pha )
|
||||
,.cos ( mod_nco_cos )
|
||||
,.sin ( mod_nco_sin )
|
||||
);
|
||||
|
||||
//------------------------------------------------------------------------------------------
|
||||
// ampmod
|
||||
//------------------------------------------------------------------------------------------
|
||||
//Config Signal
|
||||
wire Amod_Enable = 1'b1;
|
||||
wire [15 :0] Amod_Data_I ;
|
||||
wire [15 :0] Amod_Data_Q ;
|
||||
wire Amod_Vld ;
|
||||
|
||||
ampmod U_ampmod (
|
||||
.Dig_Clk ( clk )
|
||||
,.Dig_Resetn ( rst_n )
|
||||
,.Mod_Data_I ( enve_idata )
|
||||
,.Mod_Data_Q ( enve_qdata )
|
||||
,.Mod_Vld ( enve_vld )
|
||||
,.Amp ( mod_amp )
|
||||
,.Amod_Enable ( Amod_Enable )
|
||||
,.Amod_Data_I ( Amod_Data_I )
|
||||
,.Amod_Data_Q ( Amod_Data_Q )
|
||||
,.Amod_Vld ( Amod_Vld )
|
||||
);
|
||||
|
||||
//------------------------------------------------------------------------------------------
|
||||
// freqmod
|
||||
//------------------------------------------------------------------------------------------
|
||||
wire [15:0] fmod_data_i ;
|
||||
wire [15:0] fmod_data_q ;
|
||||
wire fmod_vld ;
|
||||
|
||||
wire mod_enable = ~(role_sel[1]);
|
||||
|
||||
wire [15:0] data_i = {16{mod_enable}} & Amod_Data_I ;
|
||||
wire [15:0] data_q = {16{mod_enable}} & Amod_Data_Q ;
|
||||
wire vld = mod_enable & Amod_Vld ;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
freqmod U_freqmod (
|
||||
.Dig_Clk ( clk )
|
||||
,.Dig_Resetn ( rst_n )
|
||||
,.Env_Idata ( data_i )
|
||||
,.Env_Qdata ( data_q )
|
||||
,.Env_Vld ( vld )
|
||||
,.Nco_Sin ( mod_nco_sin )
|
||||
,.Nco_Cos ( mod_nco_cos )
|
||||
,.Mod_Sideband_Sel ( mod_sideband_sel )
|
||||
,.Mod_Enable ( mod_enable )
|
||||
,.Mod_Data_I ( fmod_data_i )
|
||||
,.Mod_Data_Q ( fmod_data_q )
|
||||
,.Mod_Vld ( fmod_vld )
|
||||
);
|
||||
|
||||
|
||||
|
||||
//------------------------------------------------------------------------------------------
|
||||
// baisset
|
||||
//------------------------------------------------------------------------------------------
|
||||
//Output modem data
|
||||
wire [15:0] Bais_Data_I_i = mod_enable ? fmod_data_i : Amod_Data_I;
|
||||
wire [15:0] Bais_Data_Q_i = mod_enable ? fmod_data_q : Amod_Data_Q;
|
||||
wire Bais_Vld_i = mod_enable ? fmod_vld : Amod_Vld ;
|
||||
|
||||
wire [15:0] Bais = z_bais ;
|
||||
wire Bais_Enable = role_sel[0] ;
|
||||
|
||||
wire [15:0] bais_data_i;
|
||||
wire [15:0] bais_data_q;
|
||||
wire [0 :0] bais_data_vld;
|
||||
|
||||
baisset U_baisset (
|
||||
.Dig_Clk ( clk )
|
||||
,.Dig_Resetn ( rst_n )
|
||||
,.Bais_Data_I_i ( Bais_Data_I_i )
|
||||
,.Bais_Data_Q_i ( Bais_Data_Q_i )
|
||||
,.Bais_Vld_i ( Bais_Vld_i )
|
||||
,.Bais ( Bais )
|
||||
,.Bais_Enable ( Bais_Enable )
|
||||
,.Bais_Data_I_o ( bais_data_i )
|
||||
,.Bais_Data_Q_o ( bais_data_q )
|
||||
,.Bais_Vld_o ( bais_data_vld )
|
||||
,.Bais_I_Ov ( bais_i_ov )
|
||||
,.Bais_Q_Ov ( bais_q_ov )
|
||||
);
|
||||
|
||||
|
||||
modout_mux U_modout_mux (
|
||||
.clk ( clk )
|
||||
,.rst_n ( rst_n )
|
||||
,.sel ( mod_dout_sel )
|
||||
,.sin ( mod_nco_sin )
|
||||
,.cos ( mod_nco_cos )
|
||||
,.mod_data_i ( bais_data_i )
|
||||
,.mod_data_q ( bais_data_q )
|
||||
,.mod_data_vld ( bais_data_vld )
|
||||
,.mux_data_i ( awg_data_i )
|
||||
,.mux_data_q ( awg_data_q )
|
||||
,.mux_data_vld ( awg_vld )
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,112 @@
|
|||
//+FHDR--------------------------------------------------------------------------------------------------------
|
||||
// Company:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// File Name : codeword_decode.v
|
||||
// Department :
|
||||
// Author : PWY
|
||||
// Author's Tel :
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Relese History
|
||||
// Version Date Author Description
|
||||
// 0.1 2024-03-13 PWY Analyze the code words sent by the MCU
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Keywords :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Parameter
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Purpose :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Target Device:
|
||||
// Tool versions:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Reuse Issues
|
||||
// Reset Strategy:
|
||||
// Clock Domains:
|
||||
// Critical Timing:
|
||||
// Asynchronous I/F:
|
||||
// Synthesizable (y/n):
|
||||
// Other:
|
||||
//-FHDR--------------------------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
module codeword_decode (
|
||||
//system port
|
||||
input clk // System Main Clock
|
||||
,input rst_n // Spi Reset active low
|
||||
//Extend instructions port
|
||||
// The operands and info to peripheral
|
||||
,input send_i
|
||||
,input sendc_i
|
||||
,input [31 :0] codeword_i
|
||||
,input [1 :0] fb_st_i
|
||||
//The output data remains as the last waveform value
|
||||
,output wave_hold_o
|
||||
//Bais lookup table index
|
||||
,output [1 :0] bais_index_o
|
||||
//Amplitude lookup table index
|
||||
,output [1 :0] amp_index_o
|
||||
//Gate appended phase lookup table index
|
||||
,output [2 :0] nco_pha_index_o
|
||||
//Carrier frequency lookup table index
|
||||
,output [1 :0] nco_fcw_index_o
|
||||
//envelope lookup table index
|
||||
,output [7 :0] envelope_index_o
|
||||
//Index valid
|
||||
,output index_vld_o
|
||||
);
|
||||
|
||||
//Sending waveforms according to feedback conditions
|
||||
wire send_cond = sendc_i | codeword_i[20];
|
||||
|
||||
//The output data remains as the last waveform value
|
||||
wire wave_hold_w = codeword_i[19];
|
||||
|
||||
//Bais lookup table index
|
||||
wire [1 :0] bais_index_w = codeword_i[16:15];
|
||||
|
||||
//Amplitude lookup table index
|
||||
wire [1 :0] amp_index_w = codeword_i[14:13];
|
||||
|
||||
//Gate appended phase lookup table index
|
||||
wire [2 :0] nco_pha_index_w = codeword_i[12:10];
|
||||
|
||||
//Carrier frequency lookup table index
|
||||
wire [1 :0] nco_fcw_index_w = codeword_i[9:8];
|
||||
|
||||
//envelope lookup table index
|
||||
wire [7 :0] envelope_index_w = send_cond ? codeword_i[7:0] + fb_st_i : codeword_i[7:0];
|
||||
|
||||
//Valid Signal Generation
|
||||
wire index_vld_w = send_i | sendc_i;
|
||||
|
||||
/////////////////////////////////////////////////////////
|
||||
//Output data register
|
||||
/////////////////////////////////////////////////////////
|
||||
|
||||
//wave_hold_o
|
||||
sirv_gnrl_dfflr #(1) wave_hold_dfflr (index_vld_w, wave_hold_w, wave_hold_o, clk, rst_n);
|
||||
|
||||
//bais_index_o
|
||||
sirv_gnrl_dfflr #(2) bais_index_dfflr (index_vld_w, bais_index_w, bais_index_o, clk, rst_n);
|
||||
|
||||
//amp_index_o
|
||||
sirv_gnrl_dfflr #(2) amp_index_dfflr (index_vld_w, amp_index_w, amp_index_o, clk, rst_n);
|
||||
|
||||
//nco_pha_index_o
|
||||
sirv_gnrl_dfflr #(3) nco_pha_index_dfflr (index_vld_w, nco_pha_index_w, nco_pha_index_o, clk, rst_n);
|
||||
|
||||
//nco_fcw_index_o
|
||||
sirv_gnrl_dfflr #(2) nco_fcw_index_dfflr (index_vld_w, nco_fcw_index_w, nco_fcw_index_o, clk, rst_n);
|
||||
|
||||
//envelope_index_o
|
||||
sirv_gnrl_dfflr #(8) envelope_index_dfflr (index_vld_w, envelope_index_w, envelope_index_o, clk, rst_n);
|
||||
|
||||
//index_vld_o
|
||||
sirv_gnrl_dffr #(1) index_vld_dffr (index_vld_w ,index_vld_o, clk, rst_n);
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,593 @@
|
|||
//+FHDR--------------------------------------------------------------------------------------------------------
|
||||
// Company:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// File Name : ctrl_regfile.v
|
||||
// Department :
|
||||
// Author : PWY
|
||||
// Author's Tel :
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Relese History
|
||||
// Version Date Author Description
|
||||
// 0.1 2024-03-13 PWY AWG dedicated register file
|
||||
// 0.2 2024-05-13 PWY
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Keywords :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Parameter
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Purpose :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Target Device:
|
||||
// Tool versions:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Reuse Issues
|
||||
// Reset Strategy:
|
||||
// Clock Domains:
|
||||
// Critical Timing:
|
||||
// Asynchronous I/F:
|
||||
// Synthesizable (y/n):
|
||||
// Other:
|
||||
//-FHDR--------------------------------------------------------------------------------------------------------
|
||||
|
||||
// -----------------------------------------------------------
|
||||
// -- Register address offset macros
|
||||
// -----------------------------------------------------------
|
||||
//MCU parameter register 0
|
||||
`define MCUPARAR0 16'h00
|
||||
//MCU parameter register 1
|
||||
`define MCUPARAR1 16'h04
|
||||
//MCU parameter register 2
|
||||
`define MCUPARAR2 16'h08
|
||||
//MCU parameter register 3
|
||||
`define MCUPARAR3 16'h0C
|
||||
//MCU result register 0
|
||||
`define MCURESR0 16'h10
|
||||
//MCU result register 1
|
||||
`define MCURESR1 16'h14
|
||||
//MCU result register 2
|
||||
`define MCURESR2 16'h18
|
||||
//MCU result register 3
|
||||
`define MCURESR3 16'h1C
|
||||
//Run-time register
|
||||
`define RTIMR 16'h98
|
||||
//Instruction count register
|
||||
`define ICNTR 16'h9C
|
||||
//Feedback state information register
|
||||
`define FSIR 16'hA0
|
||||
//Modulator Operation Mode Register
|
||||
`define MODMR 16'h100
|
||||
//Interpolator Operation Mode Register
|
||||
`define INTPMR 16'h104
|
||||
//Frequency Mixer NCO Clear Register
|
||||
`define MIXNCOCR 16'h108
|
||||
//Frequency Mixer NCO Frequency Control Word High 32-bit Register
|
||||
`define MIXNFCWHR 16'h10C
|
||||
//Frequency Mixer NCO Frequency Control Word Low 16-bit Register
|
||||
`define MIXNFCWLR 16'h110
|
||||
//Frequency Mixer NCO Phase Control Word Register
|
||||
`define MIXNPHAR 16'h114
|
||||
//Frequency Mixer Operating Mode Register
|
||||
`define MIXMR 16'h118
|
||||
//Frequency Mixer Output Data Type Register
|
||||
`define MIXODTR 16'h11C
|
||||
//Frequency Mixer Output Data Format Register
|
||||
`define MIXODFR 16'h120
|
||||
//Roler Selection Register
|
||||
`define ROLER 16'h128
|
||||
|
||||
//Mixed-frequency NCO sync clear enable Register
|
||||
`define MIXNCOSCER 16'h12C
|
||||
//AWG data out type select Register
|
||||
`define MODDOTR 16'h130
|
||||
//Status Register
|
||||
`define STR 16'h134
|
||||
|
||||
//AWG always on Register
|
||||
`define DSPAOR 16'h138
|
||||
|
||||
module ctrl_regfile (
|
||||
//system port
|
||||
input clk // System Main Clock
|
||||
,input rst_n // Spi Reset active low
|
||||
//rw op port
|
||||
,input [31 :0] wrdata // write data
|
||||
,input wren // write enable
|
||||
,input [15 :0] rwaddr // read & write address
|
||||
,input rden // read enable
|
||||
,output [31 :0] rddata // read data
|
||||
,input [1 :0] fb_st_i
|
||||
,input [31 :0] run_time
|
||||
,input [31 :0] instr_num
|
||||
,input bais_i_ov
|
||||
,input bais_q_ov
|
||||
,input awg_ctrl_fsm_st
|
||||
//MCU and SPI interface for interaction
|
||||
,output [31 :0] mcu_param0 // MCU parameter 0
|
||||
,output [31 :0] mcu_param1 // MCU parameter 1
|
||||
,output [31 :0] mcu_param2 // MCU parameter 2
|
||||
,output [31 :0] mcu_param3 // MCU parameter 3
|
||||
,input [31 :0] mcu_result0 // MCU result 0
|
||||
,input [31 :0] mcu_result1 // MCU result 1
|
||||
,input [31 :0] mcu_result2 // MCU result 2
|
||||
,input [31 :0] mcu_result3 // MCU result 3
|
||||
,output [1 :0] fb_st_o
|
||||
//awg cfg
|
||||
,output mod_sel_sideband //1'b0:Upper sideband;1'b1:Lower sideband;
|
||||
//DSP cfg
|
||||
,output qam_nco_clr
|
||||
,output qam_nco_sclr_en
|
||||
,output [47 :0] qam_fcw////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
,output [15 :0] qam_pha //////////////////////////////////////////////////////////////////////////////////////////////
|
||||
,output [1 :0] qam_mod //2'b00:bypass;2'b01:mix;
|
||||
//2'b10:cos;2'b11:sin;
|
||||
,output qam_sel_sideband //1'b0:Upper sideband;1'b1:Lower sideband;
|
||||
,output [2 :0] intp_mode //3'b000:x1;3'b001:x2;3'b010:x4;
|
||||
//3'b011:x8;3'b100:x16;
|
||||
,output [1 :0] role_sel //[0] --> 1'b0: xy-chip;1'b1: z-chip;
|
||||
//[1] --> 1'b0:AC mode;1'b1: DC mode;
|
||||
//Please note that when the role is set to xy-chip,
|
||||
//only AC mode is supported.
|
||||
,output [1 :0] dac_mode_sel //2'b00:NRZ mode;2'b01:MIX mode;
|
||||
//2'b10:2xNRZ mode;2'b00:reserve;
|
||||
,output dout_sel //1'b0 --> mod modem data; 1'b1 --> mod nco data
|
||||
//1'b0 --> Z dsp data for ZDAC; 1'b1 --> xy dsp data for ZDAC
|
||||
,output dsp_alwayson //1'b0 --> dsp output data vaild depend on awg vaild;
|
||||
//1'b1 --> dsp output data always vaild;
|
||||
|
||||
);
|
||||
|
||||
localparam L = 1'b0,
|
||||
H = 1'b1;
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- Register enable (select) wires
|
||||
// ------------------------------------------------------
|
||||
wire mcuparar0en ; // MCUPARAR0 select
|
||||
wire mcuparar1en ; // MCUPARAR1 select
|
||||
wire mcuparar2en ; // MCUPARAR2 select
|
||||
wire mcuparar3en ; // MCUPARAR3 select
|
||||
wire mcuresr0en ; // MCURESR0 select
|
||||
wire mcuresr1en ; // MCURESR1 select
|
||||
wire mcuresr2en ; // MCURESR2 select
|
||||
wire mcuresr3en ; // MCURESR3 select
|
||||
wire rtimren ; // RTIMR select
|
||||
wire icntren ; // ICNTR select
|
||||
wire fsiren ; // FSIR select
|
||||
wire modmren ; // MODMR select
|
||||
wire intpmren ; // INTPMR select
|
||||
wire mixncocren ; // MIXNCOCR select
|
||||
wire mixnfcwhren ; // MIXNFCWHR select
|
||||
wire mixnfcwlren ; // MIXNFCWLR select
|
||||
wire mixnpharen ; // MIXNPHAR select
|
||||
wire mixmren ; // MIXMR select
|
||||
wire mixodtren ; // MIXODTR select
|
||||
wire mixodfren ; // MIXODFR select
|
||||
wire roleren ; // ROLER select
|
||||
wire mixncosceren ; // MIXNCOSCER select
|
||||
wire stren ; // BAISOVR select
|
||||
wire moddotren ; // MODDOTR select
|
||||
wire dspaoren ; // DSPAOR select
|
||||
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- Register write enable wires
|
||||
// ------------------------------------------------------
|
||||
wire mcuparar0we ; // MCUPARAR0 write enable
|
||||
wire mcuparar1we ; // MCUPARAR1 write enable
|
||||
wire mcuparar2we ; // MCUPARAR2 write enable
|
||||
wire mcuparar3we ; // MCUPARAR3 write enable
|
||||
wire modmrwe ; // MODMR write enable
|
||||
wire intpmrwe ; // INTPMR write enable
|
||||
wire mixncocrwe ; // MIXNCOCR write enable
|
||||
wire mixnfcwhrwe ; // MIXNFCWHR write enable
|
||||
wire mixnfcwlrwe ; // MIXNFCWLR write enable
|
||||
wire mixnpharwe ; // MIXNPHAR write enable
|
||||
wire mixmrwe ; // MIXMR write enable
|
||||
wire mixodtrwe ; // MIXODTR write enable
|
||||
wire mixodfrwe ; // MIXODFR write enable
|
||||
wire rolerwe ; // ROLER write enable
|
||||
wire mixncoscerwe ; // MIXNCOSCER write enable
|
||||
wire moddotrwe ; // MODDOTR write enable
|
||||
wire dspaorwe ; // DSPAOR write enable
|
||||
// ------------------------------------------------------
|
||||
// -- Misc wires
|
||||
// ------------------------------------------------------
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- Misc Registers
|
||||
// ------------------------------------------------------
|
||||
|
||||
wire [31 :0] mcuparar0 ; // MCUPARAR0 register
|
||||
wire [31 :0] mcuparar1 ; // MCUPARAR1 register
|
||||
wire [31 :0] mcuparar2 ; // MCUPARAR2 register
|
||||
wire [31 :0] mcuparar3 ; // MCUPARAR3 register
|
||||
wire [31 :0] mcuresr0 ; // MCURESR0 register
|
||||
wire [31 :0] mcuresr1 ; // MCURESR1 register
|
||||
wire [31 :0] mcuresr2 ; // MCURESR2 register
|
||||
wire [31 :0] mcuresr3 ; // MCURESR3 register
|
||||
wire [31 :0] rtimr ; // RTIMR register
|
||||
wire [31 :0] icntr ; // ICNTR register
|
||||
wire [1 :0] fsir ; // FSIR register
|
||||
wire [0 :0] modmr ; // MODMR register
|
||||
wire [2 :0] intpmr ; // INTPMR register
|
||||
wire [0 :0] mixncocr ; // MIXNCOCR register
|
||||
wire [31 :0] mixnfcwhr ; // MIXNFCWHR register
|
||||
wire [15 :0] mixnfcwlr ; // MIXNFCWLR register
|
||||
wire [15 :0] mixnphar ; // MIXNPHAR register
|
||||
wire [0 :0] mixmr ; // MIXMR register
|
||||
wire [1 :0] mixodtr ; // MIXODTR register
|
||||
wire [1 :0] mixodfr ; // MIXODFR register
|
||||
wire [1 :0] roler ; // ROLER register
|
||||
wire [0 :0] dspaor ; // DSPAOR register
|
||||
|
||||
wire [0 :0] mixncoscer ; // MIXNCOSCER register
|
||||
wire moddotr ; // MODDOTR register
|
||||
|
||||
reg [31: 0] rddata_reg ;
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- Address decoder
|
||||
//
|
||||
// Decodes the register address offset input(reg_addr)
|
||||
// to produce enable (select) signals for each of the
|
||||
// SW-registers in the macrocell. The reg_addr input
|
||||
// is bits [15:0] of the paddr bus.
|
||||
// ------------------------------------------------------
|
||||
assign mcuparar0en = (rwaddr[15:2] == `MCUPARAR0 >> 2) ? 1'b1 : 1'b0;
|
||||
assign mcuparar1en = (rwaddr[15:2] == `MCUPARAR1 >> 2) ? 1'b1 : 1'b0;
|
||||
assign mcuparar2en = (rwaddr[15:2] == `MCUPARAR2 >> 2) ? 1'b1 : 1'b0;
|
||||
assign mcuparar3en = (rwaddr[15:2] == `MCUPARAR3 >> 2) ? 1'b1 : 1'b0;
|
||||
assign mcuresr0en = (rwaddr[15:2] == `MCURESR0 >> 2) ? 1'b1 : 1'b0;
|
||||
assign mcuresr1en = (rwaddr[15:2] == `MCURESR1 >> 2) ? 1'b1 : 1'b0;
|
||||
assign mcuresr2en = (rwaddr[15:2] == `MCURESR2 >> 2) ? 1'b1 : 1'b0;
|
||||
assign mcuresr3en = (rwaddr[15:2] == `MCURESR3 >> 2) ? 1'b1 : 1'b0;
|
||||
assign rtimren = (rwaddr[15:2] == `RTIMR >> 2) ? 1'b1 : 1'b0;
|
||||
assign icntren = (rwaddr[15:2] == `ICNTR >> 2) ? 1'b1 : 1'b0;
|
||||
assign fsiren = (rwaddr[15:2] == `FSIR >> 2) ? 1'b1 : 1'b0;
|
||||
assign modmren = (rwaddr[15:2] == `MODMR >> 2) ? 1'b1 : 1'b0;
|
||||
assign intpmren = (rwaddr[15:2] == `INTPMR >> 2) ? 1'b1 : 1'b0;
|
||||
assign mixncocren = (rwaddr[15:2] == `MIXNCOCR >> 2) ? 1'b1 : 1'b0;
|
||||
assign mixnfcwhren = (rwaddr[15:2] == `MIXNFCWHR >> 2) ? 1'b1 : 1'b0;
|
||||
assign mixnfcwlren = (rwaddr[15:2] == `MIXNFCWLR >> 2) ? 1'b1 : 1'b0;
|
||||
assign mixnpharen = (rwaddr[15:2] == `MIXNPHAR >> 2) ? 1'b1 : 1'b0;
|
||||
assign mixmren = (rwaddr[15:2] == `MIXMR >> 2) ? 1'b1 : 1'b0;
|
||||
assign mixodtren = (rwaddr[15:2] == `MIXODTR >> 2) ? 1'b1 : 1'b0;
|
||||
assign mixodfren = (rwaddr[15:2] == `MIXODFR >> 2) ? 1'b1 : 1'b0;
|
||||
assign roleren = (rwaddr[15:2] == `ROLER >> 2) ? 1'b1 : 1'b0;
|
||||
assign mixncosceren = (rwaddr[15:2] == `MIXNCOSCER >> 2) ? 1'b1 : 1'b0;
|
||||
assign stren = (rwaddr[15:2] == `STR >> 2) ? 1'b1 : 1'b0;
|
||||
assign moddotren = (rwaddr[15:2] == `MODDOTR >> 2) ? 1'b1 : 1'b0;
|
||||
assign dspaoren = (rwaddr[15:2] == `DSPAOR >> 2) ? 1'b1 : 1'b0;
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- Write enable signals
|
||||
//
|
||||
// Write enable signals for writable SW-registers.
|
||||
// The write enable for each register is the ANDed
|
||||
// result of the register enable and the input reg_wren
|
||||
// ------------------------------------------------------
|
||||
assign mcuparar0we = mcuparar0en & wren;
|
||||
assign mcuparar1we = mcuparar1en & wren;
|
||||
assign mcuparar2we = mcuparar2en & wren;
|
||||
assign mcuparar3we = mcuparar3en & wren;
|
||||
assign modmrwe = modmren & wren;///////////
|
||||
assign intpmrwe = intpmren & wren;
|
||||
assign mixncocrwe = mixncocren & wren;
|
||||
assign mixnfcwhrwe = mixnfcwhren & wren;
|
||||
assign mixnfcwlrwe = mixnfcwlren & wren;
|
||||
assign mixnpharwe = mixnpharen & wren;
|
||||
assign mixmrwe = mixmren & wren;
|
||||
assign mixodtrwe = mixodtren & wren;
|
||||
assign mixodfrwe = mixodfren & wren;
|
||||
assign rolerwe = roleren & wren;
|
||||
assign mixncoscerwe = mixncosceren & wren;
|
||||
assign moddotrwe = moddotren & wren;
|
||||
assign dspaorwe = dspaoren & wren;
|
||||
// ------------------------------------------------------
|
||||
// -- mcuparar0 register
|
||||
//
|
||||
// Write mcuparar0 for 'MCUPARAR0' : 32-bit register
|
||||
// Register is split into the following bit fields
|
||||
//
|
||||
// [31:0] --> mcuparar0
|
||||
// ------------------------------------------------------
|
||||
sirv_gnrl_dfflr #(32) mcuparar0_dfflr (mcuparar0we, wrdata[31:0], mcuparar0, clk, rst_n);
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- mcuparar1 register
|
||||
//
|
||||
// Write mcuparar1 for 'MCUPARAR1' : 32-bit register
|
||||
// Register is split into the following bit fields
|
||||
//
|
||||
// [31:0] --> mcuparar1
|
||||
// ------------------------------------------------------
|
||||
sirv_gnrl_dfflr #(32) mcuparar1_dfflr (mcuparar1we, wrdata[31:0], mcuparar1, clk, rst_n);
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- mcuparar2 register
|
||||
//
|
||||
// Write mcuparar2 for 'MCUPARAR2' : 32-bit register
|
||||
// Register is split into the following bit fields
|
||||
//
|
||||
// [31:0] --> mcuparar2
|
||||
// ------------------------------------------------------
|
||||
sirv_gnrl_dfflr #(32) mcuparar2_dfflr (mcuparar2we, wrdata[31:0], mcuparar2, clk, rst_n);
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- mcuparar3 register
|
||||
//
|
||||
// Write mcuparar3 for 'MCUPARAR3' : 32-bit register
|
||||
// Register is split into the following bit fields
|
||||
//
|
||||
// [31:0] --> mcuparar3
|
||||
// ------------------------------------------------------
|
||||
sirv_gnrl_dfflr #(32) mcuparar3_dfflr (mcuparar3we, wrdata[31:0], mcuparar3, clk, rst_n);
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- modmr register
|
||||
//
|
||||
// Write modmr for 'MODMR' : 32-bit register
|
||||
// Register is split into the following bit fields
|
||||
//
|
||||
// [0] --> modmr
|
||||
// ------------------------------------------------------
|
||||
sirv_gnrl_dfflr #(1) modmr_dfflr (modmrwe, wrdata[0], modmr, clk, rst_n);
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- intpmr register
|
||||
//
|
||||
// Write intpmr for 'INTPMR' : 32-bit register
|
||||
// Register is split into the following bit fields
|
||||
//
|
||||
// [2:0] --> intpmr
|
||||
// ------------------------------------------------------
|
||||
sirv_gnrl_dfflr #(3) intpmr_dfflr (intpmrwe, wrdata[2:0], intpmr, clk, rst_n);
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- mixncocr register
|
||||
//
|
||||
// Write mixncocr for 'MIXNCOCR' : 32-bit register
|
||||
// Register is split into the following bit fields
|
||||
//
|
||||
// [0] --> mixncocr
|
||||
// ------------------------------------------------------
|
||||
sirv_gnrl_dfflr #(1) mixncocr_dfflr (mixncocrwe, wrdata[0], mixncocr, clk, rst_n);
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- mixnfcwhr register
|
||||
//
|
||||
// Write mixnfcwhr for 'MIXNFCWHR' : 32-bit register
|
||||
// Register is split into the following bit fields
|
||||
//
|
||||
// [31:0] --> mixnfcwhr
|
||||
// ------------------------------------------------------
|
||||
sirv_gnrl_dfflr #(32) mixnfcwhr_dfflr (mixnfcwhrwe, wrdata[31:0], mixnfcwhr, clk, rst_n);
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- mixnfcwlr register
|
||||
//
|
||||
// Write mixnfcwlr for 'MIXNFCWHR' : 32-bit register
|
||||
// Register is split into the following bit fields
|
||||
//
|
||||
// [31:16] --> mixnfcwlr
|
||||
// ------------------------------------------------------
|
||||
sirv_gnrl_dfflr #(16) mixnfcwlr_dfflr (mixnfcwlrwe, wrdata[31:16], mixnfcwlr, clk, rst_n);
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- mixnphar register
|
||||
//
|
||||
// Write mixnphar for 'MIXNPHAR' : 32-bit register
|
||||
// Register is split into the following bit fields
|
||||
//
|
||||
// [31:16] --> mixnphar
|
||||
// ------------------------------------------------------
|
||||
sirv_gnrl_dfflr #(16) mixnphar_dfflr (mixnpharwe, wrdata[31:16], mixnphar, clk, rst_n);
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- mixmr register
|
||||
//
|
||||
// Write mixmr for 'MIXNPHAR' : 32-bit register
|
||||
// Register is split into the following bit fields
|
||||
//
|
||||
// [0] --> mixmr
|
||||
// ------------------------------------------------------
|
||||
sirv_gnrl_dfflr #(1) mixmr_dfflr (mixmrwe, wrdata[0], mixmr, clk, rst_n);
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- mixodtr register
|
||||
//
|
||||
// Write mixodtr for 'MIXNPHAR' : 32-bit register
|
||||
// Register is split into the following bit fields
|
||||
//
|
||||
// [1:0] --> mixodtr
|
||||
// ------------------------------------------------------
|
||||
sirv_gnrl_dfflr #(2) mixodtr_dfflr (mixodtrwe, wrdata[1:0], mixodtr, clk, rst_n);
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- mixodfr register
|
||||
//
|
||||
// Write mixodfr for 'MIXODFR' : 32-bit register
|
||||
// Register is split into the following bit fields
|
||||
//
|
||||
// [1:0] --> mixodfr
|
||||
// ------------------------------------------------------
|
||||
sirv_gnrl_dfflr #(2) mixodfr_dfflr (mixodfrwe, wrdata[1:0], mixodfr, clk, rst_n);
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- roler register
|
||||
//
|
||||
// Write roler for 'ROLER' : 32-bit register
|
||||
// Register is split into the following bit fields
|
||||
//
|
||||
// [1] --> AC or DC mode select
|
||||
// [0] --> xy-chip or z-chip select
|
||||
// ------------------------------------------------------
|
||||
sirv_gnrl_dfflr #(1) roler0_dfflr (rolerwe, wrdata[0], roler[0], clk, rst_n);
|
||||
|
||||
//Please note that when the role is set to xy-chip, only AC mode is supported.
|
||||
wire mode_w = wrdata[0] & wrdata[1];
|
||||
// 0 | 0 | x
|
||||
// 0 | 1 | 0
|
||||
// 1 | 1 | 1
|
||||
|
||||
sirv_gnrl_dfflr #(1) roler1_dfflr (rolerwe, mode_w, roler[1], clk, rst_n);
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- mixncoscer register
|
||||
//
|
||||
// Write mixncoscer for 'mixncoscer' : 32-bit register
|
||||
// Register is split into the following bit fields
|
||||
//
|
||||
// [0] --> mixncoscer
|
||||
// ------------------------------------------------------
|
||||
sirv_gnrl_dfflr #(1) mixncoscer_dfflr (mixncoscerwe, wrdata[0], mixncoscer, clk, rst_n);
|
||||
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- moddotr register
|
||||
//
|
||||
// Write moddotr for 'moddotr' : 32-bit register
|
||||
// Register is split into the following bit fields
|
||||
//
|
||||
// [0] --> moddotr
|
||||
// ------------------------------------------------------
|
||||
sirv_gnrl_dfflr #(1) moddotr_dfflr (moddotrwe, wrdata[0], moddotr, clk, rst_n);
|
||||
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- dspaor register
|
||||
//
|
||||
// Write dspaor for 'dspaor' : 32-bit register
|
||||
// Register is split into the following bit fields
|
||||
//
|
||||
// [0] --> dspaor
|
||||
// ------------------------------------------------------
|
||||
sirv_gnrl_dfflrs #(1) dspaor_dfflrs (dspaorwe, wrdata[0], dspaor, clk, rst_n);
|
||||
|
||||
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- mcuresr0
|
||||
// ------------------------------------------------------
|
||||
sirv_gnrl_dffr #(32) mcuparar0_dffr (mcu_result0, mcuresr0, clk, rst_n);
|
||||
// ------------------------------------------------------
|
||||
// -- mcuresr1
|
||||
// ------------------------------------------------------
|
||||
sirv_gnrl_dffr #(32) mcuparar1_dffr (mcu_result1, mcuresr1, clk, rst_n);
|
||||
// ------------------------------------------------------
|
||||
// -- mcuresr2
|
||||
// ------------------------------------------------------
|
||||
sirv_gnrl_dffr #(32) mcuparar2_dffr (mcu_result2, mcuresr2, clk, rst_n);
|
||||
// ------------------------------------------------------
|
||||
// -- mcuresr3
|
||||
// ------------------------------------------------------
|
||||
sirv_gnrl_dffr #(32) mcuparar3_dffr (mcu_result3, mcuresr3, clk, rst_n);
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- rtimr
|
||||
// ------------------------------------------------------
|
||||
sirv_gnrl_dffr #(32) rtimr_dffr (run_time, rtimr, clk, rst_n);
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- icntr
|
||||
// ------------------------------------------------------
|
||||
sirv_gnrl_dffr #(32) icntr_dffr (instr_num, icntr, clk, rst_n);
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- fsir
|
||||
// ------------------------------------------------------
|
||||
sirv_gnrl_dffr #(2) fsir_dffr (fb_st_i[1:0], fsir, clk, rst_n);//////////////////////////////////////////////////////////[1:0]
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- Read data mux
|
||||
//
|
||||
// -- The data from the selected register is
|
||||
// -- placed on a zero-padded 32-bit read data bus.
|
||||
// ------------------------------------------------------
|
||||
always @(*) begin : RDDATA_PROC
|
||||
rddata_reg = {32{1'b0}};
|
||||
if(mcuparar0en == H ) rddata_reg[31:0] = mcuparar0 ;
|
||||
if(mcuparar1en == H ) rddata_reg[31:0] = mcuparar1 ;
|
||||
if(mcuparar2en == H ) rddata_reg[31:0] = mcuparar2 ;
|
||||
if(mcuparar3en == H ) rddata_reg[31:0] = mcuparar3 ;
|
||||
if(mcuresr0en == H ) rddata_reg[31:0] = mcuresr0 ;
|
||||
if(mcuresr1en == H ) rddata_reg[31:0] = mcuresr1 ;
|
||||
if(mcuresr2en == H ) rddata_reg[31:0] = mcuresr2 ;
|
||||
if(mcuresr3en == H ) rddata_reg[31:0] = mcuresr3 ;
|
||||
if(rtimren == H ) rddata_reg[31:0] = rtimr ;
|
||||
if(icntren == H ) rddata_reg[31:0] = icntr ;
|
||||
if(fsiren == H ) rddata_reg[1 :0] = fsir ;
|
||||
if(modmren == H ) rddata_reg[0 :0] = modmr ;
|
||||
if(intpmren == H ) rddata_reg[2 :0] = intpmr ;
|
||||
if(roleren == H ) rddata_reg[1 :0] = roler ;
|
||||
if(mixncocren == H ) rddata_reg[0 :0] = mixncocr ;
|
||||
if(mixnfcwhren == H ) rddata_reg[31:0] = mixnfcwhr ;
|
||||
if(mixnfcwlren == H ) rddata_reg[15:0] = mixnfcwlr ;
|
||||
if(mixnpharen == H ) rddata_reg[15:0] = mixnphar ;
|
||||
if(mixmren == H ) rddata_reg[0 :0] = mixmr ;
|
||||
if(mixodtren == H ) rddata_reg[1 :0] = mixodtr ;
|
||||
if(mixodfren == H ) rddata_reg[1 :0] = mixodfr ;
|
||||
if(mixncosceren == H ) rddata_reg[0 :0] = mixncoscer ;
|
||||
if(moddotren == H ) rddata_reg[0 :0] = moddotr ;
|
||||
if(stren == H ) rddata_reg[2 :0] = {bais_q_ov,bais_i_ov,awg_ctrl_fsm_st} ;
|
||||
if(dspaoren == H ) rddata_reg[0 :0] = dspaor ;
|
||||
end
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- Output signals assignment
|
||||
// ------------------------------------------------------
|
||||
|
||||
//mcu result
|
||||
assign mcu_param0 = mcuparar0 ;
|
||||
assign mcu_param1 = mcuparar1 ;
|
||||
assign mcu_param2 = mcuparar2 ;
|
||||
assign mcu_param3 = mcuparar3 ;
|
||||
|
||||
//fb_st_o
|
||||
assign fb_st_o = fsir ;
|
||||
//awg cfg
|
||||
assign mod_sel_sideband = modmr ;
|
||||
//DSP cfg
|
||||
assign qam_nco_clr = mixncocr ;
|
||||
assign qam_fcw = {mixnfcwhr,mixnfcwlr} ;
|
||||
assign qam_pha = mixnphar ;
|
||||
assign qam_mod = mixodtr ;
|
||||
assign qam_sel_sideband = mixmr ;
|
||||
assign intp_mode = intpmr ;
|
||||
assign dac_mode_sel = mixodfr ;
|
||||
assign qam_nco_sclr_en = mixncoscer ;
|
||||
assign role_sel = roler ;
|
||||
|
||||
assign dout_sel = moddotr ;
|
||||
|
||||
assign dsp_alwayson = dspaor ;
|
||||
//rddata
|
||||
sirv_gnrl_dffr #(32) rddata_dffr (rddata_reg, rddata, clk, rst_n);
|
||||
endmodule
|
||||
|
||||
`undef MCUPARAR0
|
||||
`undef MCUPARAR1
|
||||
`undef MCUPARAR2
|
||||
`undef MCUPARAR3
|
||||
`undef MCURESR0
|
||||
`undef MCURESR1
|
||||
`undef MCURESR2
|
||||
`undef MCURESR3
|
||||
`undef RTIMR
|
||||
`undef ICNTR
|
||||
`undef FSIR
|
||||
`undef MODMR
|
||||
`undef INTPMR
|
||||
`undef MIXNCOCR
|
||||
`undef MIXNFCWHR
|
||||
`undef MIXNFCWLR
|
||||
`undef MIXNPHAR
|
||||
`undef MIXMR
|
||||
`undef MIXODTR
|
||||
`undef MIXODFR
|
||||
`undef MIXNCOSCER
|
||||
`undef MODDOTR
|
||||
`undef STR
|
||||
|
|
@ -0,0 +1,66 @@
|
|||
//+FHDR--------------------------------------------------------------------------------------------------------
|
||||
// Company:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// File Name : modout_mux.v
|
||||
// Department :
|
||||
// Author : PWY
|
||||
// Author's Tel :
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Relese History
|
||||
// Version Date Author Description
|
||||
// 0.1 2024-05-13 PWY debug top-level
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Keywords :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Parameter
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Purpose :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Target Device:
|
||||
// Tool versions:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Reuse Issues
|
||||
// Reset Strategy:
|
||||
// Clock Domains:
|
||||
// Critical Timing:
|
||||
// Asynchronous I/F:
|
||||
// Synthesizable (y/n):
|
||||
// Other:
|
||||
//-FHDR--------------------------------------------------------------------------------------------------------
|
||||
|
||||
module modout_mux (
|
||||
//system port
|
||||
input clk // System Main Clock
|
||||
,input rst_n // Spi Reset active low
|
||||
//---------------from ctrl regfile------------------------------------
|
||||
,input sel // 1'b0 --> mod modem data; 1'b1 --> mod nco data
|
||||
//mod nco data
|
||||
,input [15:0] sin
|
||||
,input [15:0] cos
|
||||
//mod modem data
|
||||
,input [15:0] mod_data_i
|
||||
,input [15:0] mod_data_q
|
||||
,input mod_data_vld
|
||||
//mux out data
|
||||
,output [15:0] mux_data_i
|
||||
,output [15:0] mux_data_q
|
||||
,output mux_data_vld
|
||||
);
|
||||
|
||||
wire [15:0] mux_data_i_w = sel ? sin : mod_data_i;
|
||||
wire [15:0] mux_data_q_w = sel ? cos : mod_data_q;
|
||||
wire mux_data_vld_w = sel ? 1'b1 : mod_data_vld;
|
||||
|
||||
`ifdef MODDOUT_MUX_REG
|
||||
sirv_gnrl_dffr #(16) mux_data_i_dffr (mux_data_i_w , mux_data_i , clk, rst_n);
|
||||
sirv_gnrl_dffr #(16) mux_data_q_dffr (mux_data_q_w , mux_data_q , clk, rst_n);
|
||||
sirv_gnrl_dffr #(1 ) mux_data_vld_dffr (mux_data_vld_w, mux_data_vld, clk, rst_n);
|
||||
`else
|
||||
assign mux_data_i = mux_data_i_w ;
|
||||
assign mux_data_q = mux_data_q_w ;
|
||||
assign mux_data_vld = mux_data_vld_w ;
|
||||
`endif
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,84 @@
|
|||
//+FHDR--------------------------------------------------------------------------------------------------------
|
||||
// Company:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// File Name : awg_ctrl.v
|
||||
// Department :
|
||||
// Author : PWY
|
||||
// Author's Tel :
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Relese History
|
||||
// Version Date Author Description
|
||||
// 0.1 2024-03-13 PWY Configuration parameters lookup tabl
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Keywords :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Parameter
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Purpose :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Target Device:
|
||||
// Tool versions:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Reuse Issues
|
||||
// Reset Strategy:
|
||||
// Clock Domains:
|
||||
// Critical Timing:
|
||||
// Asynchronous I/F:
|
||||
// Synthesizable (y/n):
|
||||
// Other:
|
||||
//-FHDR--------------------------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
module param_lut (
|
||||
clk
|
||||
,rst_n
|
||||
,param_i
|
||||
,index_i
|
||||
,index_vld_i
|
||||
,param_o
|
||||
);
|
||||
|
||||
//=================================================
|
||||
function integer clog2(input integer depth);
|
||||
begin
|
||||
for(clog2=0;depth>1;clog2=clog2+1)
|
||||
depth =depth>>1;
|
||||
end
|
||||
endfunction
|
||||
//=================================================
|
||||
parameter DXLEN = 32;
|
||||
parameter PNUM = 4;
|
||||
//=================================================
|
||||
|
||||
//system port
|
||||
input clk ;
|
||||
input rst_n ;
|
||||
input [DXLEN-1 :0] param_i [PNUM-1:0] ;
|
||||
input [clog2(PNUM)-1 :0] index_i ;
|
||||
input index_vld_i ;
|
||||
output [DXLEN-1 :0] param_o ;
|
||||
|
||||
generate
|
||||
genvar i;
|
||||
wire [PNUM-1 :0] cs_slv;
|
||||
wire [DXLEN-1 :0] dtemp [PNUM-1:0];
|
||||
|
||||
for(i=0;i<PNUM;i=i+1) begin: CS_SLV
|
||||
assign cs_slv[i] = (index_i == i );
|
||||
if(i==0)begin: DTEMP0
|
||||
assign dtemp[i] = (cs_slv[i]) ? param_i[i] : 32'b0;
|
||||
end
|
||||
else begin: DTEMP1_32
|
||||
assign dtemp[i] = (cs_slv[i]) ? param_i[i] : dtemp[i-1];
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
|
||||
//paramter register
|
||||
sirv_gnrl_dfflr #(DXLEN) param_dfflr (index_vld_i, dtemp[PNUM-1], param_o, clk, rst_n);
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,692 @@
|
|||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 2024/03/19 10:41:08
|
||||
// Design Name:
|
||||
// Module Name: intpll_regfile
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// -----------------------------------------------------------
|
||||
// -- Register address offset macros
|
||||
// -----------------------------------------------------------
|
||||
//Int pll Ctrl Register
|
||||
`define INTPLL_REFCTRL 8'h00
|
||||
`define INTPLL_PCNT 8'h04
|
||||
`define INTPLL_PFDCTRL 8'h08
|
||||
`define INTPLL_SPDCTRL 8'h0C
|
||||
`define INTPLL_PTATCTRL 8'h10
|
||||
`define INTPLL_FLLCTRL 8'h14
|
||||
`define INTPLL_SELCTRL 8'h18
|
||||
`define INTPLL_VCOCTRL 8'h1C
|
||||
`define INTPLL_VCOFBADJ 8'h20
|
||||
`define INTPLL_AFCCTRL 8'h24
|
||||
`define INTPLL_AFCCNT 8'h28
|
||||
`define INTPLL_AFCLDCNT 8'h2C
|
||||
`define INTPLL_AFCPRES 8'h30
|
||||
`define INTPLL_AFCLDTCC 8'h34
|
||||
`define INTPLL_AFCFBTCC 8'h38
|
||||
`define INTPLL_DIVCFG 8'h3C
|
||||
`define INTPLL_TCLKCFG 8'h40
|
||||
`define INTPLL_DCLKSEL 8'h44
|
||||
`define INTPLL_STATUS 8'h48
|
||||
`define INTPLL_SYNCFG 8'h4C
|
||||
`define INTPLL_UPDATE 8'h50
|
||||
`define INTPLL_CLKRXPD 8'h54
|
||||
|
||||
|
||||
module intpll_regfile (
|
||||
//system port
|
||||
input clk // System Main Clock
|
||||
,input rst_n // Spi Reset active low
|
||||
//rw op port
|
||||
,input [31 :0] wrdata // write data
|
||||
,input wren // write enable
|
||||
,input [7 :0] rwaddr // read & write address
|
||||
,input rden // read enable
|
||||
,output [31 :0] rddata // read data
|
||||
|
||||
,output ref_sel // Clock source selection for a frequency divider;
|
||||
// 1'b0:External clock source
|
||||
// 1'b1:internal phase-locked loop clock source
|
||||
,output ref_en // Input reference clock enable
|
||||
// 1'b0:enable,1'b1:disable
|
||||
,output ref_s2d_en // Referenced clock differential to single-ended conversion enable
|
||||
// 1'b0:enable,1'b1:disable
|
||||
,output [6 :0] p_cnt // P counter
|
||||
,output pfd_delay // PFD Dead Zone
|
||||
,output pfd_dff_Set // Setting the PFD register,active high
|
||||
,output pfd_dff_4and // PFD output polarity
|
||||
,output [3 :0] spd_div // SPD Frequency Divider
|
||||
,output spd_pulse_width // Pulse Width of SPD
|
||||
,output spd_pulse_sw // Pulse sw of SPD
|
||||
,output cpc_sel // current source selection
|
||||
,output [1 :0] swcp_i // PTAT current switch
|
||||
,output [3 :0] sw_ptat_r // PTAT current adjustment
|
||||
,output [1 :0] sw_fll_cpi // Phase-locked loop charge pump current
|
||||
,output sw_fll_delay // PLL Dead Zone
|
||||
,output pfd_sel // PFD Loop selection
|
||||
,output spd_sel // SPD Loop selection
|
||||
,output fll_sel // FLL Loop selection
|
||||
,output vco_tc // VCO temperature compensation
|
||||
,output vco_tcr // VCO temperature compensation resistor
|
||||
,output vco_gain_adj // VCO gain adjustment
|
||||
,output vco_gain_adj_r // VCO gain adjustment resistor
|
||||
,output [2 :0] vco_cur_adj // VCO current adjustment
|
||||
,output vco_buff_en // VCO buff enable,active high
|
||||
,output vco_en // VCO enable,active high
|
||||
,output [2 :0] pll_dpwr_adj // PLL frequency division output power adjustment
|
||||
,output [6 :0] vco_fb_adj // VCO frequency band adjustment
|
||||
,output afc_en // AFC enable
|
||||
,output afc_shutdown // AFC module shutdown signal
|
||||
,output [0 :0] afc_det_speed // AFC detection speed
|
||||
,output [0 :0] flag_out_sel // Read and choose the signs
|
||||
,output afc_reset // AFC reset
|
||||
,output [10 :0] afc_cnt // AFC frequency band adjustment function counter
|
||||
// counting time adjustment
|
||||
,output [10 :0] afc_ld_cnt // Adjust the counting time of the AFC lock detection
|
||||
// feature counter
|
||||
,output [3 :0] afc_pres // Adjusting the resolution of the AFC comparator
|
||||
,output [14 :0] afc_ld_tcc // AFC Lock Detection Function Target Cycle Count
|
||||
,output [14 :0] afc_fb_tcc // Target number of cycles for AFC frequency band
|
||||
// adjustment function
|
||||
,output [0 :0] div_rstn_sel // div rstn select, 1'b0: ext clear, 1'b1:inter pll lock
|
||||
,output [1 :0] test_clk_sel // test clk select, 2'b00:DIV1 clk, 2'b01:DIV2 clk, 2'b10:DIV4 clk, 2'b11:DIV8 clk
|
||||
,output [0 :0] test_clk_oen // test clk output enable, 1'b0:disenable, 1'b1:enable
|
||||
,output [7 :0] dig_clk_sel // digital main clk select, one hot code,bit[0]-->0 degree phase,bit[1]-->45 degree phase.....bit[7]-->315degree phae
|
||||
,output [0 :0] div_sync_en // Frequency Divider Synchronous Clear Enable
|
||||
,output sync_oe // SYNC signal output enable, hign active
|
||||
,output clkrx_pdn // Clock Rx Power down, Ative Low
|
||||
,input pll_lock // PLL LOCK
|
||||
);
|
||||
|
||||
localparam L = 1'b0,
|
||||
H = 1'b1;
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- Register enable (select) wires
|
||||
// ------------------------------------------------------
|
||||
wire refctrlen ;
|
||||
wire pcnten ;
|
||||
wire pfdctrlen ;
|
||||
wire spdctrlen ;
|
||||
wire ptatctrlen ;
|
||||
wire fllctrlen ;
|
||||
wire selctrlen ;
|
||||
wire vcoctrlen ;
|
||||
wire vcofbadjen ;
|
||||
wire afcctrlen ;
|
||||
wire afccnten ;
|
||||
wire afcldcnten ;
|
||||
wire afcpresen ;
|
||||
wire afcldtccen ;
|
||||
wire afcfbtccen ;
|
||||
wire divcfgen ;
|
||||
wire tclkcfgen ;
|
||||
wire dclkselen ;
|
||||
wire statusen ;
|
||||
wire synccfgen ;
|
||||
wire updateen ;
|
||||
wire clkrxpden ;
|
||||
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- Register write enable wires
|
||||
// ------------------------------------------------------
|
||||
wire refctrlwe ;
|
||||
wire pcntwe ;
|
||||
wire pfdctrlwe ;
|
||||
wire spdctrlwe ;
|
||||
wire ptatctrlwe ;
|
||||
wire fllctrlwe ;
|
||||
wire selctrlwe ;
|
||||
wire vcoctrlwe ;
|
||||
wire vcofbadjwe ;
|
||||
wire afcctrlwe ;
|
||||
wire afccntwe ;
|
||||
wire afcldcntwe ;
|
||||
wire afcpreswe ;
|
||||
wire afcldtccwe ;
|
||||
wire afcfbtccwe ;
|
||||
wire divcfgwe ;
|
||||
wire tclkcfgwe ;
|
||||
wire dclkselwe ;
|
||||
wire synccfgwe ;
|
||||
wire updatewe ;
|
||||
wire clkrxpdwe ;
|
||||
// ------------------------------------------------------
|
||||
// -- Misc Registers
|
||||
// ------------------------------------------------------
|
||||
wire [2 :0] refctrl_r ;
|
||||
wire [6 :0] pcnt_r ;
|
||||
wire [2 :0] pfdctrl_r ;
|
||||
wire [5 :0] spdctrl_r ;
|
||||
wire [6 :0] ptatctrl_r ;
|
||||
wire [2 :0] fllctrl_r ;
|
||||
wire [2 :0] selctrl_r ;
|
||||
wire [11:0] vcoctrl_r ;
|
||||
wire [6 :0] vcofbadj_r ;
|
||||
wire [4 :0] afcctrl_r ;
|
||||
wire [10:0] afccnt_r ;
|
||||
wire [10:0] afcldcnt_r ;
|
||||
wire [3 :0] afcpres_r ;
|
||||
wire [14:0] afcldtcc_r ;
|
||||
wire [14:0] afcfbtcc_r ;
|
||||
wire [0 :0] divrstsel_r ;
|
||||
wire [2 :0] testclk_r ;
|
||||
wire [7 :0] digclksel_r ;
|
||||
wire [1 :0] sync_r ;
|
||||
wire clkrxpd_r ;
|
||||
|
||||
|
||||
|
||||
wire [2 :0] refctrl_updr ;
|
||||
wire [6 :0] pcnt_updr ;
|
||||
wire [2 :0] pfdctrl_updr ;
|
||||
wire [5 :0] spdctrl_updr ;
|
||||
wire [6 :0] ptatctrl_updr ;
|
||||
wire [2 :0] fllctrl_updr ;
|
||||
wire [2 :0] selctrl_updr ;
|
||||
wire [11:0] vcoctrl_updr ;
|
||||
wire [6 :0] vcofbadj_updr ;
|
||||
wire [4 :0] afcctrl_updr ;
|
||||
wire [10:0] afccnt_updr ;
|
||||
wire [10:0] afcldcnt_updr ;
|
||||
wire [3 :0] afcpres_updr ;
|
||||
wire [14:0] afcldtcc_updr ;
|
||||
wire [14:0] afcfbtcc_updr ;
|
||||
|
||||
|
||||
|
||||
reg [31 :0] rddata_reg ;
|
||||
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- Address decoder
|
||||
//
|
||||
// Decodes the register address offset input(reg_addr)
|
||||
// to produce enable (select) signals for each of the
|
||||
// SW-registers in the macrocell. The reg_addr input
|
||||
// is bits [15:0] of the paddr bus.
|
||||
// ------------------------------------------------------
|
||||
assign refctrlen = (rwaddr[7:2] == `INTPLL_REFCTRL >>2) ? 1'b1 : 1'b0;
|
||||
assign pcnten = (rwaddr[7:2] == `INTPLL_PCNT >>2) ? 1'b1 : 1'b0;
|
||||
assign pfdctrlen = (rwaddr[7:2] == `INTPLL_PFDCTRL >>2) ? 1'b1 : 1'b0;
|
||||
assign spdctrlen = (rwaddr[7:2] == `INTPLL_SPDCTRL >>2) ? 1'b1 : 1'b0;
|
||||
assign ptatctrlen = (rwaddr[7:2] == `INTPLL_PTATCTRL >>2) ? 1'b1 : 1'b0;
|
||||
assign fllctrlen = (rwaddr[7:2] == `INTPLL_FLLCTRL >>2) ? 1'b1 : 1'b0;
|
||||
assign selctrlen = (rwaddr[7:2] == `INTPLL_SELCTRL >>2) ? 1'b1 : 1'b0;
|
||||
assign vcoctrlen = (rwaddr[7:2] == `INTPLL_VCOCTRL >>2) ? 1'b1 : 1'b0;
|
||||
assign vcofbadjen = (rwaddr[7:2] == `INTPLL_VCOFBADJ >>2) ? 1'b1 : 1'b0;
|
||||
assign afcctrlen = (rwaddr[7:2] == `INTPLL_AFCCTRL >>2) ? 1'b1 : 1'b0;
|
||||
assign afccnten = (rwaddr[7:2] == `INTPLL_AFCCNT >>2) ? 1'b1 : 1'b0;
|
||||
assign afcldcnten = (rwaddr[7:2] == `INTPLL_AFCLDCNT >>2) ? 1'b1 : 1'b0;
|
||||
assign afcpresen = (rwaddr[7:2] == `INTPLL_AFCPRES >>2) ? 1'b1 : 1'b0;
|
||||
assign afcldtccen = (rwaddr[7:2] == `INTPLL_AFCLDTCC >>2) ? 1'b1 : 1'b0;
|
||||
assign afcfbtccen = (rwaddr[7:2] == `INTPLL_AFCFBTCC >>2) ? 1'b1 : 1'b0;
|
||||
assign divcfgen = (rwaddr[7:2] == `INTPLL_DIVCFG >>2) ? 1'b1 : 1'b0;
|
||||
assign tclkcfgen = (rwaddr[7:2] == `INTPLL_TCLKCFG >>2) ? 1'b1 : 1'b0;
|
||||
assign dclkselen = (rwaddr[7:2] == `INTPLL_DCLKSEL >>2) ? 1'b1 : 1'b0;
|
||||
assign statusen = (rwaddr[7:2] == `INTPLL_STATUS >>2) ? 1'b1 : 1'b0;
|
||||
assign synccfgen = (rwaddr[7:2] == `INTPLL_SYNCFG >>2) ? 1'b1 : 1'b0;
|
||||
assign updateen = (rwaddr[7:2] == `INTPLL_UPDATE >>2) ? 1'b1 : 1'b0;
|
||||
assign clkrxpden = (rwaddr[7:2] == `INTPLL_CLKRXPD >>2) ? 1'b1 : 1'b0;
|
||||
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- Write enable signals
|
||||
//
|
||||
// Write enable signals for writable SW-registers.
|
||||
// The write enable for each register is the ANDed
|
||||
// result of the register enable and the input reg_wren
|
||||
// ------------------------------------------------------
|
||||
assign refctrlwe = refctrlen & wren;
|
||||
assign pcntwe = pcnten & wren;
|
||||
assign pfdctrlwe = pfdctrlen & wren;
|
||||
assign spdctrlwe = spdctrlen & wren;
|
||||
assign ptatctrlwe = ptatctrlen & wren;
|
||||
assign fllctrlwe = fllctrlen & wren;
|
||||
assign selctrlwe = selctrlen & wren;
|
||||
assign vcoctrlwe = vcoctrlen & wren;
|
||||
assign vcofbadjwe = vcofbadjen & wren;
|
||||
assign afcctrlwe = afcctrlen & wren;
|
||||
assign afccntwe = afccnten & wren;
|
||||
assign afcldcntwe = afcldcnten & wren;
|
||||
assign afcpreswe = afcpresen & wren;
|
||||
assign afcldtccwe = afcldtccen & wren;
|
||||
assign afcfbtccwe = afcfbtccen & wren;
|
||||
assign divcfgwe = divcfgen & wren;
|
||||
assign tclkcfgwe = tclkcfgen & wren;
|
||||
assign dclkselwe = dclkselen & wren;
|
||||
assign synccfgwe = synccfgen & wren;
|
||||
assign updatewe = updateen & wren;
|
||||
assign clkrxpdwe = clkrxpden & wren;
|
||||
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- refctrl_r Register
|
||||
//
|
||||
// Write refctrl_r for 'REFCTRL' : 32-bit register
|
||||
// Register is split into the following bit fields
|
||||
//
|
||||
// [2] --> ref_s2d_en default : 1'b1
|
||||
// [1] --> ref_en default : 1'b1
|
||||
// [0] --> ref_sel default : 1'b0
|
||||
// ------------------------------------------------------
|
||||
|
||||
sirv_gnrl_dfflrd #(3) refctrl_dfflrd (3'b110, refctrlwe, wrdata[2:0], refctrl_r, clk, rst_n);
|
||||
|
||||
//update
|
||||
sirv_gnrl_dfflrd #(3) refctrl_updr_dfflrd (3'b110, updatewe, refctrl_r, refctrl_updr, clk, rst_n);
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- pcnt_r Register
|
||||
//
|
||||
// Write pcnt_r for 'PCNT' : 32-bit register
|
||||
// Register is split into the following bit fields
|
||||
//
|
||||
// [6 : 0] --> pcnt default : 7'b000_1100
|
||||
// ------------------------------------------------------
|
||||
|
||||
sirv_gnrl_dfflrd #(7) pcnt_dfflrd (7'b000_1100, pcntwe, wrdata[6:0], pcnt_r, clk, rst_n);
|
||||
|
||||
//update
|
||||
sirv_gnrl_dfflrd #(7) pcnt_updr_dfflrd (7'b000_1100, updatewe, pcnt_r, pcnt_updr, clk, rst_n);
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- pfdctrl_r Register
|
||||
//
|
||||
// Write pfdctrl_reg for 'REFCTRL' : 32-bit register
|
||||
// Register is split into the following bit fields
|
||||
//
|
||||
// [2] --> pfd_dff_4and default : 1'b1
|
||||
// [1] --> pfd_dff_Set default : 1'b1
|
||||
// [0] --> pfd_delay default : 1'b0
|
||||
// ------------------------------------------------------
|
||||
|
||||
sirv_gnrl_dfflrd #(3) pfdctrl_dfflrd (3'b110, pfdctrlwe, wrdata[2:0], pfdctrl_r, clk, rst_n);//////////////////////////////////////////////
|
||||
|
||||
//update
|
||||
sirv_gnrl_dfflrd #(3) pfdctrl_updr_dfflrd (3'b110, updatewe, pfdctrl_r, pfdctrl_updr, clk, rst_n);
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- spdctrl_r Register
|
||||
//
|
||||
// Write spdctrl_r for 'SPDCTRL' : 32-bit register
|
||||
// Register is split into the following bit fields
|
||||
//
|
||||
// [5 ] spd_pulse_sw default : 1'b0
|
||||
// [4 ] spd_pulse_width default : 1'b0
|
||||
// [3:0] spd_div default : 4'b0100
|
||||
// ------------------------------------------------------
|
||||
|
||||
sirv_gnrl_dfflrd #(6) spdctrl_dfflrd (6'b00_0100, spdctrlwe, wrdata[5:0], spdctrl_r, clk, rst_n);
|
||||
|
||||
//update
|
||||
sirv_gnrl_dfflrd #(6) spdctrl_updr_dfflrd (6'b00_0100, updatewe, spdctrl_r, spdctrl_updr, clk, rst_n);
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- ptatctrl_r Register
|
||||
//
|
||||
// Write ptatctrl_r for 'PTATCTRL' : 32-bit register
|
||||
// Register is split into the following bit fields
|
||||
//
|
||||
// [6 ] cpc_sel default : 1'b1
|
||||
// [5:4] swcp_i default : 2'b01
|
||||
// [3:0] sw_ptat_r default : 4'b1000
|
||||
// ------------------------------------------------------
|
||||
|
||||
sirv_gnrl_dfflrd #(7) ptatctrl_dfflrd (7'b101_1000, ptatctrlwe, wrdata[6:0], ptatctrl_r, clk, rst_n);
|
||||
|
||||
//update
|
||||
sirv_gnrl_dfflrd #(7) ptatctrl_updr_dfflrd (7'b101_1000, updatewe, ptatctrl_r, ptatctrl_updr, clk, rst_n);
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- fllctrl_r Register
|
||||
//
|
||||
// Write fllctrl_r for 'FLLCTRL' : 32-bit register
|
||||
// Register is split into the following bit fields
|
||||
//
|
||||
// [2 ] sw_fll_delay default : 1'b0
|
||||
// [1:0] sw_fll_cpi default : 2'b11
|
||||
// ------------------------------------------------------
|
||||
|
||||
sirv_gnrl_dfflrd #(3) fllctrl_dfflrd (3'b011, fllctrlwe, wrdata[2:0], fllctrl_r, clk, rst_n);
|
||||
|
||||
//update
|
||||
sirv_gnrl_dfflrd #(3) fllctrl_updr_dfflrd (3'b011, updatewe, fllctrl_r, fllctrl_updr, clk, rst_n);
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- selctrl_r Register
|
||||
//
|
||||
// Write selctrl_r for 'SELCTRL' : 32-bit register
|
||||
// Register is split into the following bit fields
|
||||
//
|
||||
// [2] fll_sel default : 1'b0
|
||||
// [1] spd_sel default : 1'b1
|
||||
// [0] pfd_sel default : 1'b0
|
||||
// ------------------------------------------------------
|
||||
|
||||
sirv_gnrl_dfflrd #(3) selctrl_dfflrd (3'b010, selctrlwe, wrdata[2:0], selctrl_r, clk, rst_n);
|
||||
|
||||
//update
|
||||
sirv_gnrl_dfflrd #(3) selctrl_updr_dfflrd (3'b010, updatewe, selctrl_r, selctrl_updr, clk, rst_n);
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- vcoctrl_r Register
|
||||
//
|
||||
// Write vcoctrl_r for 'VCOCTRL' : 32-bit register
|
||||
// Register is split into the following bit fields
|
||||
//
|
||||
// [11:9] pll_dpwr_adj default : 3'b111
|
||||
// [8 ] vco_en default : 1'b1
|
||||
// [7 ] vco_buff_en default : 1'b1
|
||||
// [6 :4] vco_cur_adj default : 3'b111
|
||||
// [3 ] vco_gain_adj_r default : 1'b0
|
||||
// [2 ] vco_gain_adj default : 1'b0
|
||||
// [1 ] vco_tcr default : 1'b0
|
||||
// [0 ] vco_tc default : 1'b0
|
||||
// ------------------------------------------------------
|
||||
|
||||
sirv_gnrl_dfflrd #(12) vcoctrl_dfflrd (12'b1111_1111_0000, vcoctrlwe, wrdata[11:0], vcoctrl_r, clk, rst_n);
|
||||
|
||||
//update
|
||||
sirv_gnrl_dfflrd #(12) vcoctrl_updr_dfflrd (12'b1111_1111_0000, updatewe, vcoctrl_r, vcoctrl_updr, clk, rst_n);
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- vcofbadj_r Register
|
||||
//
|
||||
// Write vcofbadj_r for 'VCOFBADJ' : 32-bit register
|
||||
// Register is split into the following bit fields
|
||||
//
|
||||
// [6 : 0] --> vco_fb_adj default : 7'b000_0000
|
||||
// ------------------------------------------------------
|
||||
|
||||
sirv_gnrl_dfflrd #(7) vcofbadj_dfflrd (7'b000_0000, vcofbadjwe, wrdata[6:0], vcofbadj_r, clk, rst_n);
|
||||
|
||||
//update
|
||||
sirv_gnrl_dfflrd #(7) vcofbadj_updr_dfflrd (7'b000_0000, updatewe, vcofbadj_r, vcofbadj_updr, clk, rst_n);
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- afcctrl_r Register
|
||||
//
|
||||
// Write afcctrl_r for 'AFCCTRL' : 32-bit register
|
||||
// Register is split into the following bit fields
|
||||
//
|
||||
// [4] afc_det_speed // default : 1'b0
|
||||
// [3] flag_out_sel // default : 1'b0
|
||||
// [2] afc_shutdown // default : 1'b0
|
||||
// [1] afc_reset // default : 1'b0
|
||||
// [0] afc_en // default : 1'b0
|
||||
// ------------------------------------------------------
|
||||
|
||||
sirv_gnrl_dfflrd #(5) afcctrl_dfflrd (5'b0_0000, afcctrlwe, wrdata[4:0], afcctrl_r, clk, rst_n);
|
||||
|
||||
//update
|
||||
sirv_gnrl_dfflrd #(5) afcctrl_updr_dfflrd (5'b0_0000, updatewe, afcctrl_r, afcctrl_updr, clk, rst_n);
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- afccnt_r Register
|
||||
//
|
||||
// Write afccnt_r for 'AFCCnt' : 32-bit register
|
||||
// Register is split into the following bit fields
|
||||
//
|
||||
// [10:0] --> afc_cnt default : 11'b000_1100_1000
|
||||
// ------------------------------------------------------
|
||||
|
||||
sirv_gnrl_dfflrd #(11) afccnt_dfflrd (11'b000_1100_1000, afccntwe, wrdata[10:0], afccnt_r, clk, rst_n);
|
||||
|
||||
//update
|
||||
sirv_gnrl_dfflrd #(11) afccnt_updr_dfflrd (11'b000_1100_1000, updatewe, afccnt_r, afccnt_updr, clk, rst_n);
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- afccnt_r Register
|
||||
//
|
||||
// Write afcldcnt_r for 'AFCLDCnt' : 32-bit register
|
||||
// Register is split into the following bit fields
|
||||
//
|
||||
// [10:0] --> afcld_cnt default : 11'b110_0100_0000
|
||||
// ------------------------------------------------------
|
||||
|
||||
sirv_gnrl_dfflrd #(11) afcldcnt_dfflrd (11'b110_0100_0000, afcldcntwe, wrdata[10:0], afcldcnt_r, clk, rst_n);
|
||||
|
||||
//update
|
||||
sirv_gnrl_dfflrd #(11) afcldcnt_updr_dfflrd (11'b110_0100_0000, updatewe, afcldcnt_r, afcldcnt_updr, clk, rst_n);
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- afcpres_r Register
|
||||
//
|
||||
// Write afcpres_r for 'AFCPRES' : 32-bit register
|
||||
// Register is split into the following bit fields
|
||||
//
|
||||
// [3:0] --> afc_pres default : 4'b0011
|
||||
// ------------------------------------------------------
|
||||
|
||||
sirv_gnrl_dfflrd #(4) afcpres_dfflrd (4'b0011, afcpreswe, wrdata[3:0], afcpres_r, clk, rst_n);
|
||||
|
||||
//update
|
||||
sirv_gnrl_dfflrd #(4) afcpres_updr_dfflrd (4'b0011, updatewe, afcpres_r, afcpres_updr, clk, rst_n);
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- afcldtcc_r Register
|
||||
//
|
||||
// Write afcldtcc_r for 'AFCLDTCC' : 32-bit register
|
||||
// Register is split into the following bit fields
|
||||
//
|
||||
// [14:0] --> afc_ld_tcc default : 15'b0
|
||||
// ------------------------------------------------------
|
||||
|
||||
sirv_gnrl_dfflrd #(15) afcldtcc_dfflrd (15'b0, afcldtccwe, wrdata[14:0], afcldtcc_r, clk, rst_n);
|
||||
|
||||
//update
|
||||
sirv_gnrl_dfflrd #(15) afcldtcc_updr_dfflrd (15'b0, updatewe, afcldtcc_r, afcldtcc_updr, clk, rst_n);
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- afcfbtcc_r Register
|
||||
//
|
||||
// Write afcfbtcc_r for 'AFCLDTCC' : 32-bit register
|
||||
// Register is split into the following bit fields
|
||||
//
|
||||
// [14:0] --> afc_fb_tcc default : 15'b0
|
||||
// ------------------------------------------------------
|
||||
|
||||
sirv_gnrl_dfflrd #(15) afcfbtcc_dfflrd (15'b0, afcfbtccwe, wrdata[14:0], afcfbtcc_r, clk, rst_n);
|
||||
|
||||
//update
|
||||
sirv_gnrl_dfflrd #(15) afcfbtcc_updr_dfflrd (15'b0, updatewe, afcfbtcc_r, afcfbtcc_updr, clk, rst_n);
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- divrstsel_r Register
|
||||
//
|
||||
// Write divrstsel_r for 'DIVCFG' : 32-bit register
|
||||
// Register is split into the following bit fields
|
||||
//
|
||||
// [0] --> divrstsel default : 1'b0
|
||||
// ------------------------------------------------------
|
||||
|
||||
sirv_gnrl_dfflrd #(1) divrstsel_r_dfflrd (1'b0, divcfgwe, wrdata[0], divrstsel_r, clk, rst_n);
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- testclk_r Register
|
||||
//
|
||||
// Write divclksel_r for 'TCLKCFG' : 32-bit register
|
||||
// Register is split into the following bit fields
|
||||
//
|
||||
// [1:0] --> testclksel default : 1'b0
|
||||
// [2] --> testclkoen default : 1'b0
|
||||
// ------------------------------------------------------
|
||||
|
||||
sirv_gnrl_dfflrd #(3) testclk_r_dfflrd (3'b0, tclkcfgwe, wrdata[2:0], testclk_r, clk, rst_n);
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- digclksel_r Register
|
||||
//
|
||||
// Write digclksel_r for 'DIGCLKSEL' : 32-bit register
|
||||
// Register is split into the following bit fields
|
||||
//
|
||||
// [7:0] --> digclksel default : 1'b0
|
||||
// ------------------------------------------------------
|
||||
|
||||
sirv_gnrl_dfflrd #(8) digclksel_r_dfflrd (8'b0000_0001, dclkselwe, wrdata[7:0], digclksel_r, clk, rst_n);
|
||||
|
||||
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- clkrxpd_r Register
|
||||
//
|
||||
// Write digclksel_r for 'CLKRXPD' : 32-bit register
|
||||
// Register is split into the following bit fields
|
||||
//
|
||||
// [0:0] --> clkrxpd default : 1'b0
|
||||
// ------------------------------------------------------
|
||||
|
||||
sirv_gnrl_dfflrd #(1) clkrxpd_r_dfflrd (1'b0, clkrxpdwe, wrdata[0], clkrxpd_r, clk, rst_n);
|
||||
|
||||
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- sync_r Register
|
||||
//
|
||||
// Write divsync_r for 'SYNCFG' : 32-bit register
|
||||
// Register is split into the following bit fields
|
||||
//
|
||||
// [0] --> divsync default : 1'b0
|
||||
// [1] --> sync_oe default : 1'b0
|
||||
// ------------------------------------------------------
|
||||
|
||||
sirv_gnrl_dfflrd #(2) sync_dfflrd (2'b0, synccfgwe, wrdata[1:0], sync_r, clk, rst_n);
|
||||
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- Read data mux
|
||||
//
|
||||
// -- The data from the selected register is
|
||||
// -- placed on a zero-padded 32-bit read data bus.
|
||||
// ------------------------------------------------------
|
||||
always @(*) begin : RDDATA_PROC
|
||||
rddata_reg = {32{1'b0}};
|
||||
if(refctrlen == H ) rddata_reg[2 :0] = refctrl_r ;
|
||||
if(pcnten == H ) rddata_reg[6 :0] = pcnt_r ;
|
||||
if(pfdctrlen == H ) rddata_reg[2 :0] = pfdctrl_r ;
|
||||
if(spdctrlen == H ) rddata_reg[5 :0] = spdctrl_r ;
|
||||
if(ptatctrlen == H ) rddata_reg[6 :0] = ptatctrl_r ;
|
||||
if(fllctrlen == H ) rddata_reg[2 :0] = fllctrl_r ;
|
||||
if(selctrlen == H ) rddata_reg[2 :0] = selctrl_r ;
|
||||
if(vcoctrlen == H ) rddata_reg[11:0] = vcoctrl_r ;
|
||||
if(vcofbadjen == H ) rddata_reg[6 :0] = vcofbadj_r ;
|
||||
if(afcctrlen == H ) rddata_reg[4 :0] = afcctrl_r ;
|
||||
if(afccnten == H ) rddata_reg[10:0] = afccnt_r ;
|
||||
if(afcldcnten == H ) rddata_reg[10:0] = afcldcnt_r ;
|
||||
if(afcpresen == H ) rddata_reg[3 :0] = afcpres_r ;
|
||||
if(afcldtccen == H ) rddata_reg[14:0] = afcldtcc_r ;
|
||||
if(afcfbtccen == H ) rddata_reg[14:0] = afcfbtcc_r ;
|
||||
if(divcfgen == H ) rddata_reg[0 :0] = divrstsel_r ;
|
||||
if(tclkcfgen == H ) rddata_reg[2 :0] = testclk_r ;
|
||||
if(dclkselen == H ) rddata_reg[7 :0] = digclksel_r ;
|
||||
if(statusen == H ) rddata_reg[0 :0] = pll_lock ;
|
||||
if(synccfgen == H ) rddata_reg[1 :0] = sync_r ;
|
||||
if(clkrxpden == H ) rddata_reg[1 :0] = clkrxpd_r ;
|
||||
|
||||
end
|
||||
|
||||
|
||||
//rddata
|
||||
sirv_gnrl_dfflr #(32) rddata_dfflr (rden, rddata_reg, rddata, clk, rst_n);
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- Output signals assignment
|
||||
// ------------------------------------------------------
|
||||
assign ref_sel = refctrl_updr[0] ; // Clock source selection for a frequency divider;
|
||||
// 1'b0:External clock source
|
||||
// 1'b1:internal phase-locked loop clock source
|
||||
assign ref_en = refctrl_updr[1] ; // Input reference clock enable
|
||||
// 1'b0:enable,1'b1:disable
|
||||
assign ref_s2d_en = refctrl_updr[2] ; // Referenced clock differential to single-ended conversion enable
|
||||
// 1'b0:enable,1'b1:disable
|
||||
assign p_cnt = pcnt_updr[6:0] ; // P counter
|
||||
assign pfd_delay = pfdctrl_updr[0] ; // PFD Dead Zone
|
||||
assign pfd_dff_Set = pfdctrl_updr[1] ; // Setting the PFD register,active high
|
||||
assign pfd_dff_4and = pfdctrl_updr[2] ; // PFD output polarity
|
||||
assign spd_div = spdctrl_updr[3:0] ; // SPD Frequency Divider
|
||||
assign spd_pulse_width = spdctrl_updr[4] ; // Pulse Width of SPD
|
||||
assign spd_pulse_sw = spdctrl_updr[5] ; // Pulse sw of SPD
|
||||
assign cpc_sel = ptatctrl_updr[6] ; // current source selection
|
||||
assign swcp_i = ptatctrl_updr[5:4] ; // PTAT current switch
|
||||
assign sw_ptat_r = ptatctrl_updr[3:0] ; // PTAT current adjustment
|
||||
assign sw_fll_cpi = fllctrl_updr[1:0] ; // Phase-locked loop charge pump current
|
||||
assign sw_fll_delay = fllctrl_updr[2] ; // PLL Dead Zone
|
||||
assign pfd_sel = selctrl_updr[0] ; // PFD Loop selection
|
||||
assign spd_sel = selctrl_updr[1] ; // SPD Loop selection
|
||||
assign fll_sel = selctrl_updr[2] ; // FLL Loop selection
|
||||
assign vco_tc = vcoctrl_updr[0] ; // VCO temperature compensation
|
||||
assign vco_tcr = vcoctrl_updr[1] ; // VCO temperature compensation resistor
|
||||
assign vco_gain_adj = vcoctrl_updr[2] ; // VCO gain adjustment
|
||||
assign vco_gain_adj_r = vcoctrl_updr[3] ; // VCO gain adjustment resistor
|
||||
assign vco_cur_adj = vcoctrl_updr[6:4] ; // VCO current adjustment
|
||||
assign vco_buff_en = vcoctrl_updr[7] ; // VCO buff enable,active high
|
||||
assign vco_en = vcoctrl_updr[8] ; // VCO enable,active high
|
||||
assign pll_dpwr_adj = vcoctrl_updr[11:9] ; // PLL frequency division output power adjustment
|
||||
assign vco_fb_adj = vcofbadj_updr[6:0] ; // VCO frequency band adjustment
|
||||
assign afc_en = afcctrl_updr[0] ; // AFC enable
|
||||
assign afc_reset = afcctrl_updr[1] ; // AFC reset
|
||||
assign afc_shutdown = afcctrl_updr[2] ; // AFC module shutdown signal
|
||||
assign flag_out_sel = afcctrl_updr[3] ; // Read and choose the signs
|
||||
assign afc_det_speed = afcctrl_updr[4] ; // AFC detection speed
|
||||
assign afc_cnt = afccnt_updr[10:0] ; // AFC frequency band adjustment function counter
|
||||
// counting time adjustment
|
||||
assign afc_ld_cnt = afcldcnt_updr[10:0] ; // Adjust the counting time of the AFC lock detection
|
||||
// feature counter
|
||||
assign afc_pres = afcpres_updr[3:0] ; // Adjusting the resolution of the AFC comparator
|
||||
assign afc_ld_tcc = afcldtcc_updr[14:0] ; // AFC Lock Detection Function Target Cycle Count
|
||||
assign afc_fb_tcc = afcfbtcc_updr[14:0] ; // Target number of cycles for AFC frequency band
|
||||
// adjustment function
|
||||
assign div_rstn_sel = divrstsel_r[0:0] ; //
|
||||
assign test_clk_sel = testclk_r[1:0] ; //
|
||||
assign test_clk_oen = testclk_r[2] ; //
|
||||
assign dig_clk_sel = digclksel_r[7:0] ; //
|
||||
|
||||
assign div_sync_en = sync_r[0] ; // Frequency Divider Synchronous Clear Enable
|
||||
|
||||
assign sync_oe = sync_r[1] ; // SYNC signal output enable, hign active
|
||||
|
||||
assign clkrx_pdn = clkrxpd_r ;
|
||||
|
||||
endmodule
|
||||
|
||||
`undef INTPLL_REFCTRL
|
||||
`undef INTPLL_PCNT
|
||||
`undef INTPLL_PFDCTRL
|
||||
`undef INTPLL_SPDCTRL
|
||||
`undef INTPLL_PTATCTRL
|
||||
`undef INTPLL_FLLCTRL
|
||||
`undef INTPLL_SELCTRL
|
||||
`undef INTPLL_VCOCTRL
|
||||
`undef INTPLL_VCOFBADJ
|
||||
`undef INTPLL_AFCCTRL
|
||||
`undef INTPLL_AFCCNT
|
||||
`undef INTPLL_AFCLDCNT
|
||||
`undef INTPLL_AFCPRES
|
||||
`undef INTPLL_AFCLDTCC
|
||||
`undef INTPLL_AFCFBTCC
|
||||
`undef INTPLL_DIVCFG
|
||||
`undef INTPLL_TCLKCFG
|
||||
`undef INTPLL_DCLKSEL
|
||||
`undef INTPLL_STATUS
|
||||
`undef INTPLL_SYNCFG
|
||||
`undef INTPLL_UPDATE
|
||||
|
|
@ -0,0 +1,694 @@
|
|||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 2024/03/19 10:41:08
|
||||
// Design Name:
|
||||
// Module Name: intpll_regfile
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// -----------------------------------------------------------
|
||||
// -- Register address offset macros
|
||||
// -----------------------------------------------------------
|
||||
//Int pll Ctrl Register
|
||||
`define INTPLL_REFCTRL 8'h00
|
||||
`define INTPLL_PCNT 8'h04
|
||||
`define INTPLL_PFDCTRL 8'h08
|
||||
`define INTPLL_SPDCTRL 8'h0C
|
||||
`define INTPLL_PTATCTRL 8'h10
|
||||
`define INTPLL_FLLCTRL 8'h14
|
||||
`define INTPLL_SELCTRL 8'h18
|
||||
`define INTPLL_VCOCTRL 8'h1C
|
||||
`define INTPLL_VCOFBADJ 8'h20
|
||||
`define INTPLL_AFCCTRL 8'h24
|
||||
`define INTPLL_AFCCNT 8'h28
|
||||
`define INTPLL_AFCLDCNT 8'h2C
|
||||
`define INTPLL_AFCPRES 8'h30
|
||||
`define INTPLL_AFCLDTCC 8'h34
|
||||
`define INTPLL_AFCFBTCC 8'h38
|
||||
`define INTPLL_DIVCFG 8'h3C
|
||||
`define INTPLL_TCLKCFG 8'h40
|
||||
`define INTPLL_DCLKSEL 8'h44
|
||||
`define INTPLL_STATUS 8'h48
|
||||
`define INTPLL_SYNCFG 8'h4C
|
||||
`define INTPLL_UPDATE 8'h50
|
||||
`define INTPLL_CLKRXPD 8'h54
|
||||
|
||||
|
||||
module intpll_regfile (
|
||||
//system port
|
||||
input clk // System Main Clock
|
||||
,input rst_n // Spi Reset active low
|
||||
//rw op port
|
||||
,input [31 :0] wrdata // write data
|
||||
,input wren // write enable
|
||||
,input [7 :0] rwaddr // read & write address
|
||||
,input rden // read enable
|
||||
,output [31 :0] rddata // read data
|
||||
|
||||
,output ref_sel // Clock source selection for a frequency divider;
|
||||
// 1'b0:External clock source
|
||||
// 1'b1:internal phase-locked loop clock source
|
||||
,output ref_en // Input reference clock enable
|
||||
// 1'b0:enable,1'b1:disable
|
||||
,output ref_s2d_en // Referenced clock differential to single-ended conversion enable
|
||||
// 1'b0:enable,1'b1:disable
|
||||
,output [6 :0] p_cnt // P counter
|
||||
,output pfd_delay // PFD Dead Zone
|
||||
,output pfd_dff_Set // Setting the PFD register,active high
|
||||
,output pfd_dff_4and // PFD output polarity
|
||||
,output [3 :0] spd_div // SPD Frequency Divider
|
||||
,output spd_pulse_width // Pulse Width of SPD
|
||||
,output spd_pulse_sw // Pulse sw of SPD
|
||||
,output cpc_sel // current source selection
|
||||
,output [1 :0] swcp_i // PTAT current switch
|
||||
,output [3 :0] sw_ptat_r // PTAT current adjustment
|
||||
,output [1 :0] sw_fll_cpi // Phase-locked loop charge pump current
|
||||
,output sw_fll_delay // PLL Dead Zone
|
||||
,output pfd_sel // PFD Loop selection
|
||||
,output spd_sel // SPD Loop selection
|
||||
,output fll_sel // FLL Loop selection
|
||||
,output vco_tc // VCO temperature compensation
|
||||
,output vco_tcr // VCO temperature compensation resistor
|
||||
,output vco_gain_adj // VCO gain adjustment
|
||||
,output vco_gain_adj_r // VCO gain adjustment resistor
|
||||
,output [2 :0] vco_cur_adj // VCO current adjustment
|
||||
,output vco_buff_en // VCO buff enable,active high
|
||||
,output vco_en // VCO enable,active high
|
||||
,output [2 :0] pll_dpwr_adj // PLL frequency division output power adjustment
|
||||
,output [6 :0] vco_fb_adj // VCO frequency band adjustment
|
||||
,output afc_en // AFC enable
|
||||
,output afc_shutdown // AFC module shutdown signal
|
||||
,output [0 :0] afc_det_speed // AFC detection speed
|
||||
,output [0 :0] flag_out_sel // Read and choose the signs
|
||||
,output afc_reset // AFC reset
|
||||
,output [10 :0] afc_cnt // AFC frequency band adjustment function counter
|
||||
// counting time adjustment
|
||||
,output [10 :0] afc_ld_cnt // Adjust the counting time of the AFC lock detection
|
||||
// feature counter
|
||||
,output [3 :0] afc_pres // Adjusting the resolution of the AFC comparator
|
||||
,output [14 :0] afc_ld_tcc // AFC Lock Detection Function Target Cycle Count
|
||||
,output [14 :0] afc_fb_tcc // Target number of cycles for AFC frequency band
|
||||
// adjustment function
|
||||
,output [0 :0] div_rstn_sel // div rstn select, 1'b0: ext clear, 1'b1:inter pll lock
|
||||
,output [1 :0] test_clk_sel // test clk select, 2'b00:DIV1 clk, 2'b01:DIV2 clk, 2'b10:DIV4 clk, 2'b11:DIV8 clk
|
||||
,output [0 :0] test_clk_oen // test clk output enable, 1'b0:disenable, 1'b1:enable
|
||||
,output [7 :0] dig_clk_sel // digital main clk select, one hot code,bit[0]-->0 degree phase,bit[1]-->45 degree phase.....bit[7]-->315degree phae
|
||||
,output [0 :0] div_sync_en // Frequency Divider Synchronous Clear Enable
|
||||
,output sync_oe // SYNC signal output enable, hign active
|
||||
,output clkrx_pdn // Clock Rx Power down, Ative Low
|
||||
,input pll_lock // PLL LOCK
|
||||
);
|
||||
|
||||
localparam L = 1'b0,
|
||||
H = 1'b1;
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- Register enable (select) wires
|
||||
// ------------------------------------------------------
|
||||
wire refctrlen ;
|
||||
wire pcnten ;
|
||||
wire pfdctrlen ;
|
||||
wire spdctrlen ;
|
||||
wire ptatctrlen ;
|
||||
wire fllctrlen ;
|
||||
wire selctrlen ;
|
||||
wire vcoctrlen ;
|
||||
wire vcofbadjen ;
|
||||
wire afcctrlen ;
|
||||
wire afccnten ;
|
||||
wire afcldcnten ;
|
||||
wire afcpresen ;
|
||||
wire afcldtccen ;
|
||||
wire afcfbtccen ;
|
||||
wire divcfgen ;
|
||||
wire tclkcfgen ;
|
||||
wire dclkselen ;
|
||||
wire statusen ;
|
||||
wire synccfgen ;
|
||||
wire updateen ;
|
||||
wire clkrxpden ;
|
||||
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- Register write enable wires
|
||||
// ------------------------------------------------------
|
||||
wire refctrlwe ;
|
||||
wire pcntwe ;
|
||||
wire pfdctrlwe ;
|
||||
wire spdctrlwe ;
|
||||
wire ptatctrlwe ;
|
||||
wire fllctrlwe ;
|
||||
wire selctrlwe ;
|
||||
wire vcoctrlwe ;
|
||||
wire vcofbadjwe ;
|
||||
wire afcctrlwe ;
|
||||
wire afccntwe ;
|
||||
wire afcldcntwe ;
|
||||
wire afcpreswe ;
|
||||
wire afcldtccwe ;
|
||||
wire afcfbtccwe ;
|
||||
wire divcfgwe ;
|
||||
wire tclkcfgwe ;
|
||||
wire dclkselwe ;
|
||||
wire synccfgwe ;
|
||||
wire updatewe ;
|
||||
wire clkrxpdwe ;
|
||||
// ------------------------------------------------------
|
||||
// -- Misc Registers
|
||||
// ------------------------------------------------------
|
||||
wire [2 :0] refctrl_r ;
|
||||
wire [6 :0] pcnt_r ;
|
||||
wire [2 :0] pfdctrl_r ;
|
||||
wire [5 :0] spdctrl_r ;
|
||||
wire [6 :0] ptatctrl_r ;
|
||||
wire [2 :0] fllctrl_r ;
|
||||
wire [2 :0] selctrl_r ;
|
||||
wire [11:0] vcoctrl_r ;
|
||||
wire [6 :0] vcofbadj_r ;
|
||||
wire [4 :0] afcctrl_r ;
|
||||
wire [10:0] afccnt_r ;
|
||||
wire [10:0] afcldcnt_r ;
|
||||
wire [3 :0] afcpres_r ;
|
||||
wire [14:0] afcldtcc_r ;
|
||||
wire [14:0] afcfbtcc_r ;
|
||||
wire [0 :0] divrstsel_r ;
|
||||
wire [2 :0] testclk_r ;
|
||||
wire [7 :0] digclksel_r ;
|
||||
wire [1 :0] sync_r ;
|
||||
wire clkrxpd_r ;
|
||||
|
||||
|
||||
|
||||
wire [2 :0] refctrl_updr ;
|
||||
wire [6 :0] pcnt_updr ;
|
||||
wire [2 :0] pfdctrl_updr ;
|
||||
wire [5 :0] spdctrl_updr ;
|
||||
wire [6 :0] ptatctrl_updr ;
|
||||
wire [2 :0] fllctrl_updr ;
|
||||
wire [2 :0] selctrl_updr ;
|
||||
wire [11:0] vcoctrl_updr ;
|
||||
wire [6 :0] vcofbadj_updr ;
|
||||
wire [4 :0] afcctrl_updr ;
|
||||
wire [10:0] afccnt_updr ;
|
||||
wire [10:0] afcldcnt_updr ;
|
||||
wire [3 :0] afcpres_updr ;
|
||||
wire [14:0] afcldtcc_updr ;
|
||||
wire [14:0] afcfbtcc_updr ;
|
||||
|
||||
|
||||
|
||||
reg [15 :0] rddata_reg ;
|
||||
|
||||
wire [15 :0] wrdata_h = wrdata[31:16];
|
||||
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- Address decoder
|
||||
//
|
||||
// Decodes the register address offset input(reg_addr)
|
||||
// to produce enable (select) signals for each of the
|
||||
// SW-registers in the macrocell. The reg_addr input
|
||||
// is bits [15:0] of the paddr bus.
|
||||
// ------------------------------------------------------
|
||||
assign refctrlen = (rwaddr[7:2] == `INTPLL_REFCTRL >>2) ? 1'b1 : 1'b0;
|
||||
assign pcnten = (rwaddr[7:2] == `INTPLL_PCNT >>2) ? 1'b1 : 1'b0;
|
||||
assign pfdctrlen = (rwaddr[7:2] == `INTPLL_PFDCTRL >>2) ? 1'b1 : 1'b0;
|
||||
assign spdctrlen = (rwaddr[7:2] == `INTPLL_SPDCTRL >>2) ? 1'b1 : 1'b0;
|
||||
assign ptatctrlen = (rwaddr[7:2] == `INTPLL_PTATCTRL >>2) ? 1'b1 : 1'b0;
|
||||
assign fllctrlen = (rwaddr[7:2] == `INTPLL_FLLCTRL >>2) ? 1'b1 : 1'b0;
|
||||
assign selctrlen = (rwaddr[7:2] == `INTPLL_SELCTRL >>2) ? 1'b1 : 1'b0;
|
||||
assign vcoctrlen = (rwaddr[7:2] == `INTPLL_VCOCTRL >>2) ? 1'b1 : 1'b0;
|
||||
assign vcofbadjen = (rwaddr[7:2] == `INTPLL_VCOFBADJ >>2) ? 1'b1 : 1'b0;
|
||||
assign afcctrlen = (rwaddr[7:2] == `INTPLL_AFCCTRL >>2) ? 1'b1 : 1'b0;
|
||||
assign afccnten = (rwaddr[7:2] == `INTPLL_AFCCNT >>2) ? 1'b1 : 1'b0;
|
||||
assign afcldcnten = (rwaddr[7:2] == `INTPLL_AFCLDCNT >>2) ? 1'b1 : 1'b0;
|
||||
assign afcpresen = (rwaddr[7:2] == `INTPLL_AFCPRES >>2) ? 1'b1 : 1'b0;
|
||||
assign afcldtccen = (rwaddr[7:2] == `INTPLL_AFCLDTCC >>2) ? 1'b1 : 1'b0;
|
||||
assign afcfbtccen = (rwaddr[7:2] == `INTPLL_AFCFBTCC >>2) ? 1'b1 : 1'b0;
|
||||
assign divcfgen = (rwaddr[7:2] == `INTPLL_DIVCFG >>2) ? 1'b1 : 1'b0;
|
||||
assign tclkcfgen = (rwaddr[7:2] == `INTPLL_TCLKCFG >>2) ? 1'b1 : 1'b0;
|
||||
assign dclkselen = (rwaddr[7:2] == `INTPLL_DCLKSEL >>2) ? 1'b1 : 1'b0;
|
||||
assign statusen = (rwaddr[7:2] == `INTPLL_STATUS >>2) ? 1'b1 : 1'b0;
|
||||
assign synccfgen = (rwaddr[7:2] == `INTPLL_SYNCFG >>2) ? 1'b1 : 1'b0;
|
||||
assign updateen = (rwaddr[7:2] == `INTPLL_UPDATE >>2) ? 1'b1 : 1'b0;
|
||||
assign clkrxpden = (rwaddr[7:2] == `INTPLL_CLKRXPD >>2) ? 1'b1 : 1'b0;
|
||||
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- Write enable signals
|
||||
//
|
||||
// Write enable signals for writable SW-registers.
|
||||
// The write enable for each register is the ANDed
|
||||
// result of the register enable and the input reg_wren
|
||||
// ------------------------------------------------------
|
||||
assign refctrlwe = refctrlen & wren;
|
||||
assign pcntwe = pcnten & wren;
|
||||
assign pfdctrlwe = pfdctrlen & wren;
|
||||
assign spdctrlwe = spdctrlen & wren;
|
||||
assign ptatctrlwe = ptatctrlen & wren;
|
||||
assign fllctrlwe = fllctrlen & wren;
|
||||
assign selctrlwe = selctrlen & wren;
|
||||
assign vcoctrlwe = vcoctrlen & wren;
|
||||
assign vcofbadjwe = vcofbadjen & wren;
|
||||
assign afcctrlwe = afcctrlen & wren;
|
||||
assign afccntwe = afccnten & wren;
|
||||
assign afcldcntwe = afcldcnten & wren;
|
||||
assign afcpreswe = afcpresen & wren;
|
||||
assign afcldtccwe = afcldtccen & wren;
|
||||
assign afcfbtccwe = afcfbtccen & wren;
|
||||
assign divcfgwe = divcfgen & wren;
|
||||
assign tclkcfgwe = tclkcfgen & wren;
|
||||
assign dclkselwe = dclkselen & wren;
|
||||
assign synccfgwe = synccfgen & wren;
|
||||
assign updatewe = updateen & wren;
|
||||
assign clkrxpdwe = clkrxpden & wren;
|
||||
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- refctrl_r Register
|
||||
//
|
||||
// Write refctrl_r for 'REFCTRL' : 32-bit register
|
||||
// Register is split into the following bit fields
|
||||
//
|
||||
// [2] --> ref_s2d_en default : 1'b1
|
||||
// [1] --> ref_en default : 1'b1
|
||||
// [0] --> ref_sel default : 1'b0
|
||||
// ------------------------------------------------------
|
||||
|
||||
sirv_gnrl_dfflrd #(3) refctrl_dfflrd (3'b110, refctrlwe, wrdata_h[2:0], refctrl_r, clk, rst_n);
|
||||
|
||||
//update
|
||||
sirv_gnrl_dfflrd #(3) refctrl_updr_dfflrd (3'b110, updatewe, refctrl_r, refctrl_updr, clk, rst_n);
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- pcnt_r Register
|
||||
//
|
||||
// Write pcnt_r for 'PCNT' : 32-bit register
|
||||
// Register is split into the following bit fields
|
||||
//
|
||||
// [6 : 0] --> pcnt default : 7'b000_1100
|
||||
// ------------------------------------------------------
|
||||
|
||||
sirv_gnrl_dfflrd #(7) pcnt_dfflrd (7'b000_1100, pcntwe, wrdata_h[6:0], pcnt_r, clk, rst_n);
|
||||
|
||||
//update
|
||||
sirv_gnrl_dfflrd #(7) pcnt_updr_dfflrd (7'b000_1100, updatewe, pcnt_r, pcnt_updr, clk, rst_n);
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- pfdctrl_r Register
|
||||
//
|
||||
// Write pfdctrl_reg for 'REFCTRL' : 32-bit register
|
||||
// Register is split into the following bit fields
|
||||
//
|
||||
// [2] --> pfd_dff_4and default : 1'b1
|
||||
// [1] --> pfd_dff_Set default : 1'b1
|
||||
// [0] --> pfd_delay default : 1'b0
|
||||
// ------------------------------------------------------
|
||||
|
||||
sirv_gnrl_dfflrd #(3) pfdctrl_dfflrd (3'b110, pfdctrlwe, wrdata_h[2:0], pfdctrl_r, clk, rst_n);//////////////////////////////////////////////
|
||||
|
||||
//update
|
||||
sirv_gnrl_dfflrd #(3) pfdctrl_updr_dfflrd (3'b110, updatewe, pfdctrl_r, pfdctrl_updr, clk, rst_n);
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- spdctrl_r Register
|
||||
//
|
||||
// Write spdctrl_r for 'SPDCTRL' : 32-bit register
|
||||
// Register is split into the following bit fields
|
||||
//
|
||||
// [5 ] spd_pulse_sw default : 1'b0
|
||||
// [4 ] spd_pulse_width default : 1'b0
|
||||
// [3:0] spd_div default : 4'b0100
|
||||
// ------------------------------------------------------
|
||||
|
||||
sirv_gnrl_dfflrd #(6) spdctrl_dfflrd (6'b00_0100, spdctrlwe, wrdata_h[5:0], spdctrl_r, clk, rst_n);
|
||||
|
||||
//update
|
||||
sirv_gnrl_dfflrd #(6) spdctrl_updr_dfflrd (6'b00_0100, updatewe, spdctrl_r, spdctrl_updr, clk, rst_n);
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- ptatctrl_r Register
|
||||
//
|
||||
// Write ptatctrl_r for 'PTATCTRL' : 32-bit register
|
||||
// Register is split into the following bit fields
|
||||
//
|
||||
// [6 ] cpc_sel default : 1'b1
|
||||
// [5:4] swcp_i default : 2'b01
|
||||
// [3:0] sw_ptat_r default : 4'b1000
|
||||
// ------------------------------------------------------
|
||||
|
||||
sirv_gnrl_dfflrd #(7) ptatctrl_dfflrd (7'b101_1000, ptatctrlwe, wrdata_h[6:0], ptatctrl_r, clk, rst_n);
|
||||
|
||||
//update
|
||||
sirv_gnrl_dfflrd #(7) ptatctrl_updr_dfflrd (7'b101_1000, updatewe, ptatctrl_r, ptatctrl_updr, clk, rst_n);
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- fllctrl_r Register
|
||||
//
|
||||
// Write fllctrl_r for 'FLLCTRL' : 32-bit register
|
||||
// Register is split into the following bit fields
|
||||
//
|
||||
// [2 ] sw_fll_delay default : 1'b0
|
||||
// [1:0] sw_fll_cpi default : 2'b11
|
||||
// ------------------------------------------------------
|
||||
|
||||
sirv_gnrl_dfflrd #(3) fllctrl_dfflrd (3'b011, fllctrlwe, wrdata_h[2:0], fllctrl_r, clk, rst_n);
|
||||
|
||||
//update
|
||||
sirv_gnrl_dfflrd #(3) fllctrl_updr_dfflrd (3'b011, updatewe, fllctrl_r, fllctrl_updr, clk, rst_n);
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- selctrl_r Register
|
||||
//
|
||||
// Write selctrl_r for 'SELCTRL' : 32-bit register
|
||||
// Register is split into the following bit fields
|
||||
//
|
||||
// [2] fll_sel default : 1'b0
|
||||
// [1] spd_sel default : 1'b1
|
||||
// [0] pfd_sel default : 1'b0
|
||||
// ------------------------------------------------------
|
||||
|
||||
sirv_gnrl_dfflrd #(3) selctrl_dfflrd (3'b010, selctrlwe, wrdata_h[2:0], selctrl_r, clk, rst_n);
|
||||
|
||||
//update
|
||||
sirv_gnrl_dfflrd #(3) selctrl_updr_dfflrd (3'b010, updatewe, selctrl_r, selctrl_updr, clk, rst_n);
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- vcoctrl_r Register
|
||||
//
|
||||
// Write vcoctrl_r for 'VCOCTRL' : 32-bit register
|
||||
// Register is split into the following bit fields
|
||||
//
|
||||
// [11:9] pll_dpwr_adj default : 3'b111
|
||||
// [8 ] vco_en default : 1'b1
|
||||
// [7 ] vco_buff_en default : 1'b1
|
||||
// [6 :4] vco_cur_adj default : 3'b111
|
||||
// [3 ] vco_gain_adj_r default : 1'b0
|
||||
// [2 ] vco_gain_adj default : 1'b0
|
||||
// [1 ] vco_tcr default : 1'b0
|
||||
// [0 ] vco_tc default : 1'b0
|
||||
// ------------------------------------------------------
|
||||
|
||||
sirv_gnrl_dfflrd #(12) vcoctrl_dfflrd (12'b1111_1111_0000, vcoctrlwe, wrdata_h[11:0], vcoctrl_r, clk, rst_n);
|
||||
|
||||
//update
|
||||
sirv_gnrl_dfflrd #(12) vcoctrl_updr_dfflrd (12'b1111_1111_0000, updatewe, vcoctrl_r, vcoctrl_updr, clk, rst_n);
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- vcofbadj_r Register
|
||||
//
|
||||
// Write vcofbadj_r for 'VCOFBADJ' : 32-bit register
|
||||
// Register is split into the following bit fields
|
||||
//
|
||||
// [6 : 0] --> vco_fb_adj default : 7'b000_0000
|
||||
// ------------------------------------------------------
|
||||
|
||||
sirv_gnrl_dfflrd #(7) vcofbadj_dfflrd (7'b000_0000, vcofbadjwe, wrdata_h[6:0], vcofbadj_r, clk, rst_n);
|
||||
|
||||
//update
|
||||
sirv_gnrl_dfflrd #(7) vcofbadj_updr_dfflrd (7'b000_0000, updatewe, vcofbadj_r, vcofbadj_updr, clk, rst_n);
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- afcctrl_r Register
|
||||
//
|
||||
// Write afcctrl_r for 'AFCCTRL' : 32-bit register
|
||||
// Register is split into the following bit fields
|
||||
//
|
||||
// [4] afc_det_speed // default : 1'b0
|
||||
// [3] flag_out_sel // default : 1'b0
|
||||
// [2] afc_shutdown // default : 1'b0
|
||||
// [1] afc_reset // default : 1'b0
|
||||
// [0] afc_en // default : 1'b0
|
||||
// ------------------------------------------------------
|
||||
|
||||
sirv_gnrl_dfflrd #(5) afcctrl_dfflrd (5'b0_0000, afcctrlwe, wrdata_h[4:0], afcctrl_r, clk, rst_n);
|
||||
|
||||
//update
|
||||
sirv_gnrl_dfflrd #(5) afcctrl_updr_dfflrd (5'b0_0000, updatewe, afcctrl_r, afcctrl_updr, clk, rst_n);
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- afccnt_r Register
|
||||
//
|
||||
// Write afccnt_r for 'AFCCnt' : 32-bit register
|
||||
// Register is split into the following bit fields
|
||||
//
|
||||
// [10:0] --> afc_cnt default : 11'b000_1100_1000
|
||||
// ------------------------------------------------------
|
||||
|
||||
sirv_gnrl_dfflrd #(11) afccnt_dfflrd (11'b000_1100_1000, afccntwe, wrdata_h[10:0], afccnt_r, clk, rst_n);
|
||||
|
||||
//update
|
||||
sirv_gnrl_dfflrd #(11) afccnt_updr_dfflrd (11'b000_1100_1000, updatewe, afccnt_r, afccnt_updr, clk, rst_n);
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- afccnt_r Register
|
||||
//
|
||||
// Write afcldcnt_r for 'AFCLDCnt' : 32-bit register
|
||||
// Register is split into the following bit fields
|
||||
//
|
||||
// [10:0] --> afcld_cnt default : 11'b110_0100_0000
|
||||
// ------------------------------------------------------
|
||||
|
||||
sirv_gnrl_dfflrd #(11) afcldcnt_dfflrd (11'b110_0100_0000, afcldcntwe, wrdata_h[10:0], afcldcnt_r, clk, rst_n);
|
||||
|
||||
//update
|
||||
sirv_gnrl_dfflrd #(11) afcldcnt_updr_dfflrd (11'b110_0100_0000, updatewe, afcldcnt_r, afcldcnt_updr, clk, rst_n);
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- afcpres_r Register
|
||||
//
|
||||
// Write afcpres_r for 'AFCPRES' : 32-bit register
|
||||
// Register is split into the following bit fields
|
||||
//
|
||||
// [3:0] --> afc_pres default : 4'b0011
|
||||
// ------------------------------------------------------
|
||||
|
||||
sirv_gnrl_dfflrd #(4) afcpres_dfflrd (4'b0011, afcpreswe, wrdata_h[3:0], afcpres_r, clk, rst_n);
|
||||
|
||||
//update
|
||||
sirv_gnrl_dfflrd #(4) afcpres_updr_dfflrd (4'b0011, updatewe, afcpres_r, afcpres_updr, clk, rst_n);
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- afcldtcc_r Register
|
||||
//
|
||||
// Write afcldtcc_r for 'AFCLDTCC' : 32-bit register
|
||||
// Register is split into the following bit fields
|
||||
//
|
||||
// [14:0] --> afc_ld_tcc default : 15'b0
|
||||
// ------------------------------------------------------
|
||||
|
||||
sirv_gnrl_dfflrd #(15) afcldtcc_dfflrd (15'b0, afcldtccwe, wrdata_h[14:0], afcldtcc_r, clk, rst_n);
|
||||
|
||||
//update
|
||||
sirv_gnrl_dfflrd #(15) afcldtcc_updr_dfflrd (15'b0, updatewe, afcldtcc_r, afcldtcc_updr, clk, rst_n);
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- afcfbtcc_r Register
|
||||
//
|
||||
// Write afcfbtcc_r for 'AFCLDTCC' : 32-bit register
|
||||
// Register is split into the following bit fields
|
||||
//
|
||||
// [14:0] --> afc_fb_tcc default : 15'b0
|
||||
// ------------------------------------------------------
|
||||
|
||||
sirv_gnrl_dfflrd #(15) afcfbtcc_dfflrd (15'b0, afcfbtccwe, wrdata_h[14:0], afcfbtcc_r, clk, rst_n);
|
||||
|
||||
//update
|
||||
sirv_gnrl_dfflrd #(15) afcfbtcc_updr_dfflrd (15'b0, updatewe, afcfbtcc_r, afcfbtcc_updr, clk, rst_n);
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- divrstsel_r Register
|
||||
//
|
||||
// Write divrstsel_r for 'DIVCFG' : 32-bit register
|
||||
// Register is split into the following bit fields
|
||||
//
|
||||
// [0] --> divrstsel default : 1'b0
|
||||
// ------------------------------------------------------
|
||||
|
||||
sirv_gnrl_dfflrd #(1) divrstsel_r_dfflrd (1'b0, divcfgwe, wrdata_h[0], divrstsel_r, clk, rst_n);
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- testclk_r Register
|
||||
//
|
||||
// Write divclksel_r for 'TCLKCFG' : 32-bit register
|
||||
// Register is split into the following bit fields
|
||||
//
|
||||
// [1:0] --> testclksel default : 1'b0
|
||||
// [2] --> testclkoen default : 1'b0
|
||||
// ------------------------------------------------------
|
||||
|
||||
sirv_gnrl_dfflrd #(3) testclk_r_dfflrd (3'b0, tclkcfgwe, wrdata_h[2:0], testclk_r, clk, rst_n);
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- digclksel_r Register
|
||||
//
|
||||
// Write digclksel_r for 'DIGCLKSEL' : 32-bit register
|
||||
// Register is split into the following bit fields
|
||||
//
|
||||
// [7:0] --> digclksel default : 1'b0
|
||||
// ------------------------------------------------------
|
||||
|
||||
sirv_gnrl_dfflrd #(8) digclksel_r_dfflrd (8'b0000_0001, dclkselwe, wrdata_h[7:0], digclksel_r, clk, rst_n);
|
||||
|
||||
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- clkrxpd_r Register
|
||||
//
|
||||
// Write digclksel_r for 'CLKRXPD' : 32-bit register
|
||||
// Register is split into the following bit fields
|
||||
//
|
||||
// [0:0] --> clkrxpd default : 1'b0
|
||||
// ------------------------------------------------------
|
||||
|
||||
sirv_gnrl_dfflrd #(1) clkrxpd_r_dfflrd (1'b0, clkrxpdwe, wrdata_h[0], clkrxpd_r, clk, rst_n);
|
||||
|
||||
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- sync_r Register
|
||||
//
|
||||
// Write divsync_r for 'SYNCFG' : 32-bit register
|
||||
// Register is split into the following bit fields
|
||||
//
|
||||
// [0] --> divsync default : 1'b0
|
||||
// [1] --> sync_oe default : 1'b0
|
||||
// ------------------------------------------------------
|
||||
|
||||
sirv_gnrl_dfflrd #(2) sync_dfflrd (2'b0, synccfgwe, wrdata_h[1:0], sync_r, clk, rst_n);
|
||||
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- Read data mux
|
||||
//
|
||||
// -- The data from the selected register is
|
||||
// -- placed on a zero-padded 32-bit read data bus.
|
||||
// ------------------------------------------------------
|
||||
always @(*) begin : RDDATA_PROC
|
||||
rddata_reg = {16{1'b0}};
|
||||
if(refctrlen == H ) rddata_reg[2 :0] = refctrl_r ;
|
||||
if(pcnten == H ) rddata_reg[6 :0] = pcnt_r ;
|
||||
if(pfdctrlen == H ) rddata_reg[2 :0] = pfdctrl_r ;
|
||||
if(spdctrlen == H ) rddata_reg[5 :0] = spdctrl_r ;
|
||||
if(ptatctrlen == H ) rddata_reg[6 :0] = ptatctrl_r ;
|
||||
if(fllctrlen == H ) rddata_reg[2 :0] = fllctrl_r ;
|
||||
if(selctrlen == H ) rddata_reg[2 :0] = selctrl_r ;
|
||||
if(vcoctrlen == H ) rddata_reg[11:0] = vcoctrl_r ;
|
||||
if(vcofbadjen == H ) rddata_reg[6 :0] = vcofbadj_r ;
|
||||
if(afcctrlen == H ) rddata_reg[4 :0] = afcctrl_r ;
|
||||
if(afccnten == H ) rddata_reg[10:0] = afccnt_r ;
|
||||
if(afcldcnten == H ) rddata_reg[10:0] = afcldcnt_r ;
|
||||
if(afcpresen == H ) rddata_reg[3 :0] = afcpres_r ;
|
||||
if(afcldtccen == H ) rddata_reg[14:0] = afcldtcc_r ;
|
||||
if(afcfbtccen == H ) rddata_reg[14:0] = afcfbtcc_r ;
|
||||
if(divcfgen == H ) rddata_reg[0 :0] = divrstsel_r ;
|
||||
if(tclkcfgen == H ) rddata_reg[2 :0] = testclk_r ;
|
||||
if(dclkselen == H ) rddata_reg[7 :0] = digclksel_r ;
|
||||
if(statusen == H ) rddata_reg[0 :0] = pll_lock ;
|
||||
if(synccfgen == H ) rddata_reg[1 :0] = sync_r ;
|
||||
if(clkrxpden == H ) rddata_reg[1 :0] = clkrxpd_r ;
|
||||
|
||||
end
|
||||
|
||||
|
||||
//rddata
|
||||
sirv_gnrl_dfflr #(32) rddata_dfflr (rden, {rddata_reg,16'h0}, rddata, clk, rst_n);
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- Output signals assignment
|
||||
// ------------------------------------------------------
|
||||
assign ref_sel = refctrl_updr[0] ; // Clock source selection for a frequency divider;
|
||||
// 1'b0:External clock source
|
||||
// 1'b1:internal phase-locked loop clock source
|
||||
assign ref_en = refctrl_updr[1] ; // Input reference clock enable
|
||||
// 1'b0:enable,1'b1:disable
|
||||
assign ref_s2d_en = refctrl_updr[2] ; // Referenced clock differential to single-ended conversion enable
|
||||
// 1'b0:enable,1'b1:disable
|
||||
assign p_cnt = pcnt_updr[6:0] ; // P counter
|
||||
assign pfd_delay = pfdctrl_updr[0] ; // PFD Dead Zone
|
||||
assign pfd_dff_Set = pfdctrl_updr[1] ; // Setting the PFD register,active high
|
||||
assign pfd_dff_4and = pfdctrl_updr[2] ; // PFD output polarity
|
||||
assign spd_div = spdctrl_updr[3:0] ; // SPD Frequency Divider
|
||||
assign spd_pulse_width = spdctrl_updr[4] ; // Pulse Width of SPD
|
||||
assign spd_pulse_sw = spdctrl_updr[5] ; // Pulse sw of SPD
|
||||
assign cpc_sel = ptatctrl_updr[6] ; // current source selection
|
||||
assign swcp_i = ptatctrl_updr[5:4] ; // PTAT current switch
|
||||
assign sw_ptat_r = ptatctrl_updr[3:0] ; // PTAT current adjustment
|
||||
assign sw_fll_cpi = fllctrl_updr[1:0] ; // Phase-locked loop charge pump current
|
||||
assign sw_fll_delay = fllctrl_updr[2] ; // PLL Dead Zone
|
||||
assign pfd_sel = selctrl_updr[0] ; // PFD Loop selection
|
||||
assign spd_sel = selctrl_updr[1] ; // SPD Loop selection
|
||||
assign fll_sel = selctrl_updr[2] ; // FLL Loop selection
|
||||
assign vco_tc = vcoctrl_updr[0] ; // VCO temperature compensation
|
||||
assign vco_tcr = vcoctrl_updr[1] ; // VCO temperature compensation resistor
|
||||
assign vco_gain_adj = vcoctrl_updr[2] ; // VCO gain adjustment
|
||||
assign vco_gain_adj_r = vcoctrl_updr[3] ; // VCO gain adjustment resistor
|
||||
assign vco_cur_adj = vcoctrl_updr[6:4] ; // VCO current adjustment
|
||||
assign vco_buff_en = vcoctrl_updr[7] ; // VCO buff enable,active high
|
||||
assign vco_en = vcoctrl_updr[8] ; // VCO enable,active high
|
||||
assign pll_dpwr_adj = vcoctrl_updr[11:9] ; // PLL frequency division output power adjustment
|
||||
assign vco_fb_adj = vcofbadj_updr[6:0] ; // VCO frequency band adjustment
|
||||
assign afc_en = afcctrl_updr[0] ; // AFC enable
|
||||
assign afc_reset = afcctrl_updr[1] ; // AFC reset
|
||||
assign afc_shutdown = afcctrl_updr[2] ; // AFC module shutdown signal
|
||||
assign flag_out_sel = afcctrl_updr[3] ; // Read and choose the signs
|
||||
assign afc_det_speed = afcctrl_updr[4] ; // AFC detection speed
|
||||
assign afc_cnt = afccnt_updr[10:0] ; // AFC frequency band adjustment function counter
|
||||
// counting time adjustment
|
||||
assign afc_ld_cnt = afcldcnt_updr[10:0] ; // Adjust the counting time of the AFC lock detection
|
||||
// feature counter
|
||||
assign afc_pres = afcpres_updr[3:0] ; // Adjusting the resolution of the AFC comparator
|
||||
assign afc_ld_tcc = afcldtcc_updr[14:0] ; // AFC Lock Detection Function Target Cycle Count
|
||||
assign afc_fb_tcc = afcfbtcc_updr[14:0] ; // Target number of cycles for AFC frequency band
|
||||
// adjustment function
|
||||
assign div_rstn_sel = divrstsel_r[0:0] ; //
|
||||
assign test_clk_sel = testclk_r[1:0] ; //
|
||||
assign test_clk_oen = testclk_r[2] ; //
|
||||
assign dig_clk_sel = digclksel_r[7:0] ; //
|
||||
|
||||
assign div_sync_en = sync_r[0] ; // Frequency Divider Synchronous Clear Enable
|
||||
|
||||
assign sync_oe = sync_r[1] ; // SYNC signal output enable, hign active
|
||||
|
||||
assign clkrx_pdn = clkrxpd_r ;
|
||||
|
||||
endmodule
|
||||
|
||||
`undef INTPLL_REFCTRL
|
||||
`undef INTPLL_PCNT
|
||||
`undef INTPLL_PFDCTRL
|
||||
`undef INTPLL_SPDCTRL
|
||||
`undef INTPLL_PTATCTRL
|
||||
`undef INTPLL_FLLCTRL
|
||||
`undef INTPLL_SELCTRL
|
||||
`undef INTPLL_VCOCTRL
|
||||
`undef INTPLL_VCOFBADJ
|
||||
`undef INTPLL_AFCCTRL
|
||||
`undef INTPLL_AFCCNT
|
||||
`undef INTPLL_AFCLDCNT
|
||||
`undef INTPLL_AFCPRES
|
||||
`undef INTPLL_AFCLDTCC
|
||||
`undef INTPLL_AFCFBTCC
|
||||
`undef INTPLL_DIVCFG
|
||||
`undef INTPLL_TCLKCFG
|
||||
`undef INTPLL_DCLKSEL
|
||||
`undef INTPLL_STATUS
|
||||
`undef INTPLL_SYNCFG
|
||||
`undef INTPLL_UPDATE
|
||||
|
|
@ -0,0 +1,326 @@
|
|||
/*
|
||||
Copyright 2018-2020 Nuclei System Technology, Inc.
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
//=====================================================================
|
||||
//
|
||||
// Designer : Bob Hu
|
||||
//
|
||||
// Description:
|
||||
// All of the general DFF and Latch modules
|
||||
//
|
||||
// ====================================================================
|
||||
|
||||
//
|
||||
|
||||
|
||||
//
|
||||
// ===========================================================================
|
||||
//
|
||||
// Description:
|
||||
// Verilog module sirv_gnrl DFF with Load-enable and Reset
|
||||
// Default reset value is 1
|
||||
//
|
||||
// ===========================================================================
|
||||
`define DISABLE_SV_ASSERTION
|
||||
`define dly #0.2
|
||||
module sirv_gnrl_dfflrs # (
|
||||
parameter DW = 32
|
||||
) (
|
||||
|
||||
input lden,
|
||||
input [DW-1:0] dnxt,
|
||||
output [DW-1:0] qout,
|
||||
|
||||
input clk,
|
||||
input rst_n
|
||||
);
|
||||
|
||||
reg [DW-1:0] qout_r;
|
||||
|
||||
always @(posedge clk or negedge rst_n)
|
||||
begin : DFFLRS_PROC
|
||||
if (rst_n == 1'b0)
|
||||
qout_r <= {DW{1'b1}};
|
||||
else if (lden == 1'b1)
|
||||
qout_r <= `dly dnxt;
|
||||
end
|
||||
|
||||
assign qout = qout_r;
|
||||
|
||||
`ifndef FPGA_SOURCE//{
|
||||
`ifndef DISABLE_SV_ASSERTION//{
|
||||
//synopsys translate_off
|
||||
sirv_gnrl_xchecker # (
|
||||
.DW(1)
|
||||
) sirv_gnrl_xchecker(
|
||||
.i_dat(lden),
|
||||
.clk (clk)
|
||||
);
|
||||
//synopsys translate_on
|
||||
`endif//}
|
||||
`endif//}
|
||||
|
||||
|
||||
endmodule
|
||||
// ===========================================================================
|
||||
//
|
||||
// Description:
|
||||
// Verilog module sirv_gnrl DFF with Load-enable and Reset
|
||||
// Default reset value is 0
|
||||
//
|
||||
// ===========================================================================
|
||||
|
||||
module sirv_gnrl_dfflr # (
|
||||
parameter DW = 32
|
||||
) (
|
||||
|
||||
input lden,
|
||||
input [DW-1:0] dnxt,
|
||||
output [DW-1:0] qout,
|
||||
|
||||
input clk,
|
||||
input rst_n
|
||||
);
|
||||
|
||||
reg [DW-1:0] qout_r;
|
||||
|
||||
always @(posedge clk or negedge rst_n)
|
||||
begin : DFFLR_PROC
|
||||
if (rst_n == 1'b0)
|
||||
qout_r <= {DW{1'b0}};
|
||||
else if (lden == 1'b1)
|
||||
qout_r <= `dly dnxt;
|
||||
end
|
||||
|
||||
assign qout = qout_r;
|
||||
|
||||
`ifndef FPGA_SOURCE//{
|
||||
`ifndef DISABLE_SV_ASSERTION//{
|
||||
//synopsys translate_off
|
||||
sirv_gnrl_xchecker # (
|
||||
.DW(1)
|
||||
) sirv_gnrl_xchecker(
|
||||
.i_dat(lden),
|
||||
.clk (clk)
|
||||
);
|
||||
//synopsys translate_on
|
||||
`endif//}
|
||||
`endif//}
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
// ===========================================================================
|
||||
//
|
||||
// Description:
|
||||
// Verilog module sirv_gnrl DFF with Load-enable and Reset
|
||||
// Default reset value is input
|
||||
//
|
||||
// ===========================================================================
|
||||
|
||||
module sirv_gnrl_dfflrd # (
|
||||
parameter DW = 32
|
||||
) (
|
||||
input [DW-1:0] init,
|
||||
input lden,
|
||||
input [DW-1:0] dnxt,
|
||||
output [DW-1:0] qout,
|
||||
|
||||
input clk,
|
||||
input rst_n
|
||||
);
|
||||
|
||||
reg [DW-1:0] qout_r;
|
||||
|
||||
always @(posedge clk or negedge rst_n)
|
||||
begin : DFFLR_PROC
|
||||
if (rst_n == 1'b0)
|
||||
qout_r <= init;
|
||||
else if (lden == 1'b1)
|
||||
qout_r <= `dly dnxt;
|
||||
end
|
||||
|
||||
assign qout = qout_r;
|
||||
|
||||
`ifndef FPGA_SOURCE//{
|
||||
`ifndef DISABLE_SV_ASSERTION//{
|
||||
//synopsys translate_off
|
||||
sirv_gnrl_xchecker # (
|
||||
.DW(1)
|
||||
) sirv_gnrl_xchecker(
|
||||
.i_dat(lden),
|
||||
.clk (clk)
|
||||
);
|
||||
//synopsys translate_on
|
||||
`endif//}
|
||||
`endif//}
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
// ===========================================================================
|
||||
//
|
||||
// Description:
|
||||
// Verilog module sirv_gnrl DFF with Load-enable, no reset
|
||||
//
|
||||
// ===========================================================================
|
||||
|
||||
module sirv_gnrl_dffl # (
|
||||
parameter DW = 32
|
||||
) (
|
||||
|
||||
input lden,
|
||||
input [DW-1:0] dnxt,
|
||||
output [DW-1:0] qout,
|
||||
|
||||
input clk
|
||||
);
|
||||
|
||||
reg [DW-1:0] qout_r;
|
||||
|
||||
always @(posedge clk)
|
||||
begin : DFFL_PROC
|
||||
if (lden == 1'b1)
|
||||
qout_r <= `dly dnxt;
|
||||
end
|
||||
|
||||
assign qout = qout_r;
|
||||
|
||||
`ifndef FPGA_SOURCE//{
|
||||
`ifndef DISABLE_SV_ASSERTION//{
|
||||
//synopsys translate_off
|
||||
sirv_gnrl_xchecker # (
|
||||
.DW(1)
|
||||
) sirv_gnrl_xchecker(
|
||||
.i_dat(lden),
|
||||
.clk (clk)
|
||||
);
|
||||
//synopsys translate_on
|
||||
`endif//}
|
||||
`endif//}
|
||||
|
||||
|
||||
endmodule
|
||||
// ===========================================================================
|
||||
//
|
||||
// Description:
|
||||
// Verilog module sirv_gnrl DFF with Reset, no load-enable
|
||||
// Default reset value is 1
|
||||
//
|
||||
// ===========================================================================
|
||||
|
||||
module sirv_gnrl_dffrs # (
|
||||
parameter DW = 32
|
||||
) (
|
||||
|
||||
input [DW-1:0] dnxt,
|
||||
output [DW-1:0] qout,
|
||||
|
||||
input clk,
|
||||
input rst_n
|
||||
);
|
||||
|
||||
reg [DW-1:0] qout_r;
|
||||
|
||||
always @(posedge clk or negedge rst_n)
|
||||
begin : DFFRS_PROC
|
||||
if (rst_n == 1'b0)
|
||||
qout_r <= {DW{1'b1}};
|
||||
else
|
||||
qout_r <= `dly dnxt;
|
||||
end
|
||||
|
||||
assign qout = qout_r;
|
||||
|
||||
endmodule
|
||||
// ===========================================================================
|
||||
//
|
||||
// Description:
|
||||
// Verilog module sirv_gnrl DFF with Reset, no load-enable
|
||||
// Default reset value is 0
|
||||
//
|
||||
// ===========================================================================
|
||||
|
||||
module sirv_gnrl_dffr # (
|
||||
parameter DW = 32
|
||||
) (
|
||||
|
||||
input [DW-1:0] dnxt,
|
||||
output [DW-1:0] qout,
|
||||
|
||||
input clk,
|
||||
input rst_n
|
||||
);
|
||||
|
||||
reg [DW-1:0] qout_r;
|
||||
|
||||
always @(posedge clk or negedge rst_n)
|
||||
begin : DFFR_PROC
|
||||
if (rst_n == 1'b0)
|
||||
qout_r <= {DW{1'b0}};
|
||||
else
|
||||
qout_r <= `dly dnxt;
|
||||
end
|
||||
|
||||
assign qout = qout_r;
|
||||
|
||||
endmodule
|
||||
// ===========================================================================
|
||||
//
|
||||
// Description:
|
||||
// Verilog module for general latch
|
||||
//
|
||||
// ===========================================================================
|
||||
|
||||
module sirv_gnrl_ltch # (
|
||||
parameter DW = 32
|
||||
) (
|
||||
|
||||
//input test_mode,
|
||||
input lden,
|
||||
input [DW-1:0] dnxt,
|
||||
output [DW-1:0] qout
|
||||
);
|
||||
|
||||
reg [DW-1:0] qout_r;
|
||||
|
||||
always @ *
|
||||
begin : LTCH_PROC
|
||||
if (lden == 1'b1)
|
||||
qout_r <= dnxt;
|
||||
end
|
||||
|
||||
//assign qout = test_mode ? dnxt : qout_r;
|
||||
assign qout = qout_r;
|
||||
|
||||
`ifndef FPGA_SOURCE//{
|
||||
`ifndef DISABLE_SV_ASSERTION//{
|
||||
//synopsys translate_off
|
||||
always_comb
|
||||
begin
|
||||
CHECK_THE_X_VALUE:
|
||||
assert (lden !== 1'bx)
|
||||
else $fatal ("\n Error: Oops, detected a X value!!! This should never happen. \n");
|
||||
end
|
||||
|
||||
//synopsys translate_on
|
||||
`endif//}
|
||||
`endif//}
|
||||
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,49 @@
|
|||
/*
|
||||
Copyright 2018-2020 Nuclei System Technology, Inc.
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
//=====================================================================
|
||||
//
|
||||
// Designer : Bob Hu
|
||||
//
|
||||
// Description:
|
||||
// Verilog module for X checker
|
||||
//
|
||||
// ====================================================================
|
||||
|
||||
|
||||
`ifndef FPGA_SOURCE//{
|
||||
`ifndef DISABLE_SV_ASSERTION//{
|
||||
//synopsys translate_off
|
||||
module sirv_gnrl_xchecker # (
|
||||
parameter DW = 32
|
||||
) (
|
||||
input [DW-1:0] i_dat,
|
||||
input clk
|
||||
);
|
||||
|
||||
|
||||
CHECK_THE_X_VALUE:
|
||||
assert property (@(posedge clk)
|
||||
((^(i_dat)) !== 1'bx)
|
||||
)
|
||||
else $fatal ("\n Error: Oops, detected a X value!!! This should never happen. \n");
|
||||
|
||||
endmodule
|
||||
//synopsys translate_on
|
||||
`endif//}
|
||||
`endif//}
|
||||
|
|
@ -0,0 +1,58 @@
|
|||
//+FHDR--------------------------------------------------------------------------------------------------------
|
||||
// Company:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// File Name : syncer.v
|
||||
// Department :
|
||||
// Author : PWY
|
||||
// Author's Tel :
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Relese History
|
||||
// Version Date Author Description
|
||||
// 0.1 2024-03-13 PWY AWG dedicated register file
|
||||
// 0.2 2024-05-13 PWY
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Keywords :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Parameter
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Purpose :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Target Device:
|
||||
// Tool versions:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Reuse Issues
|
||||
// Reset Strategy:
|
||||
// Clock Domains:
|
||||
// Critical Timing:
|
||||
// Asynchronous I/F:
|
||||
// Synthesizable (y/n):
|
||||
// Other:
|
||||
//-FHDR--------------------------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
module syncer # (
|
||||
parameter width = 1
|
||||
,parameter stage = 2
|
||||
)
|
||||
(
|
||||
input clk_d
|
||||
,input rstn_d
|
||||
,input [width-1:0] data_s
|
||||
,output [width-1:0] data_d
|
||||
);
|
||||
|
||||
generate
|
||||
genvar i;
|
||||
wire [width-1:0] data_temp[stage-1:0];
|
||||
sirv_gnrl_dffr #(width) data_temp0_dffr (data_s ,data_temp[0], clk_d, rstn_d);
|
||||
for(i=1;i<stage;i=i+1) begin: SYNCER
|
||||
sirv_gnrl_dffr #(width) data_tempn0_dffr (data_temp[i-1] ,data_temp[i], clk_d, rstn_d);
|
||||
end
|
||||
endgenerate
|
||||
|
||||
assign data_d = data_temp[stage-1];
|
||||
|
||||
endmodule
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,233 @@
|
|||
//+FHDR--------------------------------------------------------------------------------------------------------
|
||||
// Company:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// File Name : debug_sample.v
|
||||
// Department :
|
||||
// Author : PWY
|
||||
// Author's Tel :
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Relese History
|
||||
// Version Date Author Description
|
||||
// 0.1 2024-03-13 PWY Debugging data sampling
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Keywords :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Parameter
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Purpose :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Target Device:
|
||||
// Tool versions:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Reuse Issues
|
||||
// Reset Strategy:
|
||||
// Clock Domains:
|
||||
// Critical Timing:
|
||||
// Asynchronous I/F:
|
||||
// Synthesizable (y/n):
|
||||
// Other:
|
||||
//-FHDR--------------------------------------------------------------------------------------------------------
|
||||
|
||||
module debug_sampling (
|
||||
//system port
|
||||
input clk // System Main Clock
|
||||
,input rst_n // Spi Reset active low
|
||||
//---------------from ctrl regfile------------------------------------
|
||||
,input debug_enable //active high
|
||||
,input debug_data_sel //1'b0-->mod;1'b1-->dsp
|
||||
,input [3 :0] debug_ch_sel //4'b0001-->ch0;4'b0010-->ch1;
|
||||
//4'b0100-->ch2;4'b1000-->ch3;
|
||||
//---------------to system regfile------------------------------------
|
||||
,output debug_update //active high
|
||||
//---------------connect mod------------------------------------------
|
||||
,input [15 :0] ch0_mod_data_i
|
||||
,input [15 :0] ch0_mod_data_q
|
||||
,input ch0_mod_vld
|
||||
,input [15 :0] ch1_mod_data_i
|
||||
,input [15 :0] ch1_mod_data_q
|
||||
,input ch1_mod_vld
|
||||
,input [15 :0] ch2_mod_data_i
|
||||
,input [15 :0] ch2_mod_data_q
|
||||
,input ch2_mod_vld
|
||||
,input [15 :0] ch3_mod_data_i
|
||||
,input [15 :0] ch3_mod_data_q
|
||||
,input ch3_mod_vld
|
||||
//---------------connect mod------------------------------------------
|
||||
,input [15 :0] ch0_dsp_data [15:0]
|
||||
,input ch0_dsp_vld
|
||||
,input [15 :0] ch1_dsp_data [15:0]
|
||||
,input ch1_dsp_vld
|
||||
,input [15 :0] ch2_dsp_data [15:0]
|
||||
,input ch2_dsp_vld
|
||||
,input [15 :0] ch3_dsp_data [15:0]
|
||||
,input ch3_dsp_vld
|
||||
//---------------debug memory mod------------------------------------------
|
||||
,output [11 :0] debug_rwaddr
|
||||
,output [255:0] debug_wrdata
|
||||
,output [31 :0] debug_bwen
|
||||
,output debug_wren
|
||||
,output debug_cen
|
||||
);
|
||||
|
||||
|
||||
//
|
||||
logic mod_vld;
|
||||
logic dsp_vld;
|
||||
|
||||
//---------------addr gen----------------------------------------------------
|
||||
|
||||
|
||||
|
||||
wire end_cnt_flag;
|
||||
|
||||
wire [9 :0] cnt_c;
|
||||
|
||||
wire add_cnt = debug_enable & ((~debug_data_sel & mod_vld) | (debug_data_sel & dsp_vld)) & ~end_cnt_flag;
|
||||
|
||||
wire end_cnt = add_cnt & ((~debug_data_sel & cnt_c == 10'd1023) | (debug_data_sel & cnt_c ==9'd127));
|
||||
|
||||
wire end_cnt_flag_w = end_cnt ? 1'b1 :
|
||||
~debug_enable ? 1'b0 : 1'b0;
|
||||
sirv_gnrl_dfflr #(1) end_cnt_flag_dfflr ((end_cnt | ~debug_enable), end_cnt_flag_w, end_cnt_flag, clk, rst_n);
|
||||
|
||||
wire [9 :0] cnt_n = ~debug_enable ? 10'd0 :
|
||||
end_cnt ? cnt_c :
|
||||
add_cnt ? cnt_c + 1'b1 :
|
||||
cnt_c ;
|
||||
|
||||
|
||||
sirv_gnrl_dffr #(10) cnt_c_dffr (cnt_n, cnt_c, clk, rst_n);
|
||||
|
||||
//---------------mod Data integration------------------------------------------
|
||||
|
||||
assign mod_vld = debug_ch_sel[0] & ch0_mod_vld
|
||||
| debug_ch_sel[1] & ch1_mod_vld
|
||||
| debug_ch_sel[2] & ch2_mod_vld
|
||||
| debug_ch_sel[3] & ch3_mod_vld ;
|
||||
|
||||
wire [31:0] mod_data = {32{debug_ch_sel[0]}} & {ch0_mod_data_i,ch0_mod_data_q}
|
||||
| {32{debug_ch_sel[1]}} & {ch1_mod_data_i,ch1_mod_data_q}
|
||||
| {32{debug_ch_sel[2]}} & {ch2_mod_data_i,ch2_mod_data_q}
|
||||
| {32{debug_ch_sel[3]}} & {ch3_mod_data_i,ch3_mod_data_q} ;
|
||||
|
||||
|
||||
|
||||
|
||||
logic [255:0] mod_data_c;
|
||||
logic [255:0] mod_data_n;
|
||||
|
||||
assign mod_data_n = add_cnt ? {mod_data,mod_data_c[255:32]} :
|
||||
mod_data_c ;
|
||||
|
||||
wire [255:0] mod_wrdata = mod_data_c ;
|
||||
sirv_gnrl_dffr #(256) mod_data_c_dffr (mod_data_n, mod_data_c, clk, rst_n);
|
||||
|
||||
//active low
|
||||
wire mod_cen_w = ~((cnt_c[2:0] == 3'h7) & add_cnt);
|
||||
wire mod_cen;
|
||||
sirv_gnrl_dffrs #(1) mod_cen_dffrs (mod_cen_w, mod_cen, clk, rst_n);
|
||||
|
||||
wire [11:0] mod_addr ;
|
||||
|
||||
sirv_gnrl_dffr #(12) mod_addr_dffr ({cnt_c,2'b00}, mod_addr, clk, rst_n);
|
||||
|
||||
//---------------dsp Data integration------------------------------------------
|
||||
assign dsp_vld = debug_ch_sel[0] & ch0_dsp_vld
|
||||
| debug_ch_sel[1] & ch1_dsp_vld
|
||||
| debug_ch_sel[2] & ch2_dsp_vld
|
||||
| debug_ch_sel[3] & ch3_dsp_vld ;
|
||||
|
||||
wire [255:0] dsp_data = debug_ch_sel[0] ? { ch0_dsp_data[15]
|
||||
,ch0_dsp_data[14]
|
||||
,ch0_dsp_data[13]
|
||||
,ch0_dsp_data[12]
|
||||
,ch0_dsp_data[11]
|
||||
,ch0_dsp_data[10]
|
||||
,ch0_dsp_data[9 ]
|
||||
,ch0_dsp_data[8 ]
|
||||
,ch0_dsp_data[7 ]
|
||||
,ch0_dsp_data[6 ]
|
||||
,ch0_dsp_data[5 ]
|
||||
,ch0_dsp_data[4 ]
|
||||
,ch0_dsp_data[3 ]
|
||||
,ch0_dsp_data[2 ]
|
||||
,ch0_dsp_data[1 ]
|
||||
,ch0_dsp_data[0 ]} :
|
||||
debug_ch_sel[1] ? { ch1_dsp_data[15]
|
||||
,ch1_dsp_data[14]
|
||||
,ch1_dsp_data[13]
|
||||
,ch1_dsp_data[12]
|
||||
,ch1_dsp_data[11]
|
||||
,ch1_dsp_data[10]
|
||||
,ch1_dsp_data[9 ]
|
||||
,ch1_dsp_data[8 ]
|
||||
,ch1_dsp_data[7 ]
|
||||
,ch1_dsp_data[6 ]
|
||||
,ch1_dsp_data[5 ]
|
||||
,ch1_dsp_data[4 ]
|
||||
,ch1_dsp_data[3 ]
|
||||
,ch1_dsp_data[2 ]
|
||||
,ch1_dsp_data[1 ]
|
||||
,ch1_dsp_data[0 ]} :
|
||||
debug_ch_sel[2] ? { ch2_dsp_data[15]
|
||||
,ch2_dsp_data[14]
|
||||
,ch2_dsp_data[13]
|
||||
,ch2_dsp_data[12]
|
||||
,ch2_dsp_data[11]
|
||||
,ch2_dsp_data[10]
|
||||
,ch2_dsp_data[9 ]
|
||||
,ch2_dsp_data[8 ]
|
||||
,ch2_dsp_data[7 ]
|
||||
,ch2_dsp_data[6 ]
|
||||
,ch2_dsp_data[5 ]
|
||||
,ch2_dsp_data[4 ]
|
||||
,ch2_dsp_data[3 ]
|
||||
,ch2_dsp_data[2 ]
|
||||
,ch2_dsp_data[1 ]
|
||||
,ch2_dsp_data[0 ]} :
|
||||
debug_ch_sel[3] ? { ch3_dsp_data[15]
|
||||
,ch3_dsp_data[14]
|
||||
,ch3_dsp_data[13]
|
||||
,ch3_dsp_data[12]
|
||||
,ch3_dsp_data[11]
|
||||
,ch3_dsp_data[10]
|
||||
,ch3_dsp_data[9 ]
|
||||
,ch3_dsp_data[8 ]
|
||||
,ch3_dsp_data[7 ]
|
||||
,ch3_dsp_data[6 ]
|
||||
,ch3_dsp_data[5 ]
|
||||
,ch3_dsp_data[4 ]
|
||||
,ch3_dsp_data[3 ]
|
||||
,ch3_dsp_data[2 ]
|
||||
,ch3_dsp_data[1 ]
|
||||
,ch3_dsp_data[0 ]} : 255'h0;
|
||||
|
||||
wire [11 :0] dsp_addr = {cnt_c[6:0],5'b00000} ;
|
||||
wire dsp_cen = ~add_cnt ; //active low
|
||||
wire [255:0] dsp_wrdata = dsp_data ;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
// data & cmd mux
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
wire [11 :0] mem_addr = debug_data_sel ? dsp_addr : mod_addr ;
|
||||
wire mem_cen = debug_data_sel ? dsp_cen : mod_cen ; //active low
|
||||
wire [255:0] mem_wrdata = debug_data_sel ? dsp_wrdata : mod_wrdata ;
|
||||
|
||||
|
||||
sirv_gnrl_dffr #(12) mem_addr_dffr (mem_addr, debug_rwaddr, clk, rst_n);
|
||||
|
||||
sirv_gnrl_dffr #(1) mem_cen_dffr (mem_cen, debug_cen, clk, rst_n);
|
||||
|
||||
sirv_gnrl_dffr #(256) mem_wrdata_dffr (mem_wrdata, debug_wrdata, clk, rst_n);
|
||||
|
||||
|
||||
assign debug_bwen = 32'b0;
|
||||
assign debug_wren = 1'b0;
|
||||
|
||||
//debug_update
|
||||
sirv_gnrl_dffr #(1) debug_update_dffr (end_cnt, debug_update, clk, rst_n);
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,162 @@
|
|||
//+FHDR--------------------------------------------------------------------------------------------------------
|
||||
// Company:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// File Name : debug_top.v
|
||||
// Department :
|
||||
// Author : PWY
|
||||
// Author's Tel :
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Relese History
|
||||
// Version Date Author Description
|
||||
// 0.1 2024-04-13 PWY debug top-level
|
||||
// 0.2 2024-06-20 PWY dbg_sramb_wben = dbg_sram_out.wben -> dbg_sramb_wben = ~dbg_sram_out.wben
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Keywords :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Parameter
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Purpose :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Target Device:
|
||||
// Tool versions:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Reuse Issues
|
||||
// Reset Strategy:
|
||||
// Clock Domains:
|
||||
// Critical Timing:
|
||||
// Asynchronous I/F:
|
||||
// Synthesizable (y/n):
|
||||
// Other:
|
||||
//-FHDR--------------------------------------------------------------------------------------------------------
|
||||
|
||||
module debug_top (
|
||||
//system port
|
||||
input clk // System Main Clock
|
||||
,input rst_n // Spi Reset active low
|
||||
//---------------from ctrl regfile------------------------------------
|
||||
,input debug_enable //active high
|
||||
,input debug_data_sel //1'b0-->mod;1'b1-->dsp
|
||||
,input [3 :0] debug_ch_sel //2'b00-->ch0;2'b01-->ch1;2'b10-->ch2;2'b11-->ch3;
|
||||
//---------------to system regfile------------------------------------
|
||||
,output debug_update //active high
|
||||
//---------------connect mod------------------------------------------
|
||||
,input [15 :0] ch0_mod_data_i
|
||||
,input [15 :0] ch0_mod_data_q
|
||||
,input ch0_mod_vld
|
||||
,input [15 :0] ch1_mod_data_i
|
||||
,input [15 :0] ch1_mod_data_q
|
||||
,input ch1_mod_vld
|
||||
,input [15 :0] ch2_mod_data_i
|
||||
,input [15 :0] ch2_mod_data_q
|
||||
,input ch2_mod_vld
|
||||
,input [15 :0] ch3_mod_data_i
|
||||
,input [15 :0] ch3_mod_data_q
|
||||
,input ch3_mod_vld
|
||||
//---------------connect mod------------------------------------------
|
||||
,input [15 :0] ch0_dsp_data [15:0]
|
||||
,input ch0_dsp_vld
|
||||
,input [15 :0] ch1_dsp_data [15:0]
|
||||
,input ch1_dsp_vld
|
||||
,input [15 :0] ch2_dsp_data [15:0]
|
||||
,input ch2_dsp_vld
|
||||
,input [15 :0] ch3_dsp_data [15:0]
|
||||
,input ch3_dsp_vld
|
||||
//---------------connect SPI bus --------------------------------------
|
||||
,sram_if.slave dbg_sram_in
|
||||
);
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------------------------
|
||||
//debug sampling
|
||||
//---------------------------------------------------------------------------------------------
|
||||
|
||||
wire [11 :0] debug_rwaddr ;
|
||||
wire [255:0] debug_wrdata ;
|
||||
wire [31 :0] debug_bwen ;
|
||||
wire debug_wren ;
|
||||
wire debug_cen ;
|
||||
|
||||
debug_sampling U_debug_sampling (
|
||||
.clk ( clk )
|
||||
,.rst_n ( rst_n )
|
||||
,.debug_enable ( debug_enable )
|
||||
,.debug_data_sel ( debug_data_sel )
|
||||
,.debug_ch_sel ( debug_ch_sel )
|
||||
,.debug_update ( debug_update )
|
||||
,.ch0_mod_data_i ( ch0_mod_data_i )
|
||||
,.ch0_mod_data_q ( ch0_mod_data_q )
|
||||
,.ch0_mod_vld ( ch0_mod_vld )
|
||||
,.ch1_mod_data_i ( ch1_mod_data_i )
|
||||
,.ch1_mod_data_q ( ch1_mod_data_q )
|
||||
,.ch1_mod_vld ( ch1_mod_vld )
|
||||
,.ch2_mod_data_i ( ch2_mod_data_i )
|
||||
,.ch2_mod_data_q ( ch2_mod_data_q )
|
||||
,.ch2_mod_vld ( ch2_mod_vld )
|
||||
,.ch3_mod_data_i ( ch3_mod_data_i )
|
||||
,.ch3_mod_data_q ( ch3_mod_data_q )
|
||||
,.ch3_mod_vld ( ch3_mod_vld )
|
||||
,.ch0_dsp_data ( ch0_dsp_data )
|
||||
,.ch0_dsp_vld ( ch0_dsp_vld )
|
||||
,.ch1_dsp_data ( ch1_dsp_data )
|
||||
,.ch1_dsp_vld ( ch1_dsp_vld )
|
||||
,.ch2_dsp_data ( ch2_dsp_data )
|
||||
,.ch2_dsp_vld ( ch2_dsp_vld )
|
||||
,.ch3_dsp_data ( ch3_dsp_data )
|
||||
,.ch3_dsp_vld ( ch3_dsp_vld )
|
||||
,.debug_rwaddr ( debug_rwaddr )
|
||||
,.debug_wrdata ( debug_wrdata )
|
||||
,.debug_bwen ( debug_bwen )
|
||||
,.debug_wren ( debug_wren )
|
||||
,.debug_cen ( debug_cen )
|
||||
);
|
||||
|
||||
//---------------------------------------------------------------------------------------------
|
||||
//debug SRAM (512w x 128d)
|
||||
//---------------------------------------------------------------------------------------------
|
||||
sram_if #(12,256) dbg_sram_out(clk);
|
||||
wire [255:0] dbg_sramb_dout ;
|
||||
wire [11 :0] dbg_sramb_addr = dbg_sram_out.addr[11:0] ;
|
||||
wire [255:0] dbg_sramb_din = dbg_sram_out.din ;
|
||||
wire [31 :0] dbg_sramb_wben = ~dbg_sram_out.wben ;
|
||||
wire dbg_sramb_wren = ~dbg_sram_out.wren & dbg_sram_out.rden ;
|
||||
wire dbg_sramb_cen = ~(dbg_sram_out.wren | dbg_sram_out.rden);
|
||||
assign dbg_sram_out.dout = dbg_sramb_dout;
|
||||
|
||||
|
||||
dpram #(
|
||||
.DATAWIDTH ( 256 )
|
||||
,.ADDRWIDTH ( 12 )
|
||||
) U_dbg_sram (
|
||||
.PortClk ( clk )
|
||||
,.PortAAddr ( debug_rwaddr )
|
||||
,.PortADataIn ( debug_wrdata )
|
||||
,.PortAWriteEnable ( debug_wren )
|
||||
,.PortAChipEnable ( debug_cen )
|
||||
,.PortAByteWriteEnable ( debug_bwen )
|
||||
,.PortADataOut ( )
|
||||
,.PortBAddr ( dbg_sramb_addr )
|
||||
,.PortBDataIn ( dbg_sramb_din )
|
||||
,.PortBWriteEnable ( dbg_sramb_wren )
|
||||
,.PortBChipEnable ( dbg_sramb_cen )
|
||||
,.PortBByteWriteEnable ( dbg_sramb_wben )
|
||||
,.PortBDataOut ( dbg_sramb_dout )
|
||||
);
|
||||
|
||||
//---------------------------------------------------------------------------------------------
|
||||
//debug SRAM (512w x 128d)
|
||||
//---------------------------------------------------------------------------------------------
|
||||
sram_dmux_w #(
|
||||
.ADDR_WIDTH ( 12 )
|
||||
,.DATA_WIDTH_I ( 32 )
|
||||
,.DATA_WIDTH_O ( 256 )
|
||||
) U_sram_dmux_w (
|
||||
.clk ( clk )
|
||||
,.rst_n ( rst_n )
|
||||
,.port_in ( dbg_sram_in )
|
||||
,.port_out ( dbg_sram_out )
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,23 @@
|
|||
|
||||
//Defining Memory Types
|
||||
|
||||
//`define BEHAVIOR_SIM
|
||||
//`define XILINX_FPGA
|
||||
`define TSMC_IC
|
||||
//Is the chip a 4-channel one?
|
||||
//`define CHANNEL_IS_FOUR 1
|
||||
|
||||
|
||||
//Whether to instantiate the XY-channel
|
||||
`define CHANNEL_XY_ON 1
|
||||
//Whether to instantiate the Z-channel
|
||||
`define CHANNEL_Z_ON 1
|
||||
|
||||
//Setting the Number of SPI Slave Devices
|
||||
`define SLVNUM 26
|
||||
//Whether SPI Bus Commands Are Buffered
|
||||
`define SPIBUS_CMD_REG 1
|
||||
//Whether SPI Bus Readout Are Buffered
|
||||
`define SPIBUS_OUT_REG 0
|
||||
//Whether Mod mux dout Are Buffered
|
||||
//`define MODDOUT_MUX_REG
|
||||
|
|
@ -0,0 +1,22 @@
|
|||
|
||||
//`undef BEHAVIOR_SIM
|
||||
//`undef XILINX_FPGA
|
||||
`undef TSMC_IC
|
||||
//Is the chip a 4-channel one?
|
||||
//`undef CHANNEL_IS_FOUR
|
||||
|
||||
|
||||
//Whether to instantiate the XY-channel
|
||||
`undef CHANNEL_XY_ON
|
||||
//Whether to instantiate the Z-channel
|
||||
`undef CHANNEL_Z_ON
|
||||
|
||||
//Setting the Number of SPI Slave Devices
|
||||
`undef SLVNUM
|
||||
//Whether SPI Bus Commands Are Buffered
|
||||
`undef SPIBUS_CMD_REG
|
||||
//Whether SPI Bus Readout Are Buffered
|
||||
`undef SPIBUS_OUT_REG
|
||||
|
||||
//Whether Mod mux dout Are Buffered
|
||||
//`undef MODDOUT_MUX_REG
|
||||
|
|
@ -0,0 +1,181 @@
|
|||
module DAC_DEM ( clk_in,
|
||||
data_in,
|
||||
prbs_en,
|
||||
set,
|
||||
DEM_LSB_OUT,
|
||||
DEM_ISB_OUT,
|
||||
DEM_MSB_OUT
|
||||
);
|
||||
|
||||
|
||||
|
||||
input clk_in, prbs_en;
|
||||
input [15:0] data_in;
|
||||
input [14:0] set;
|
||||
output [8:0] DEM_LSB_OUT;
|
||||
output [6:0] DEM_ISB_OUT;
|
||||
output [14:0] DEM_MSB_OUT;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
reg [14:0]r_shift_data;
|
||||
|
||||
always @(posedge clk_in or negedge prbs_en)
|
||||
begin
|
||||
if(!prbs_en)
|
||||
|
||||
r_shift_data <=set;
|
||||
|
||||
else
|
||||
|
||||
begin
|
||||
|
||||
r_shift_data[0] <=r_shift_data[14]^r_shift_data[13];
|
||||
|
||||
r_shift_data[1] <= r_shift_data[0];
|
||||
|
||||
r_shift_data[2] <= r_shift_data[1];
|
||||
|
||||
r_shift_data[3] <= r_shift_data[2];
|
||||
|
||||
r_shift_data[4] <= r_shift_data[3];
|
||||
|
||||
r_shift_data[5] <= r_shift_data[4];
|
||||
|
||||
r_shift_data[6] <= r_shift_data[5];
|
||||
|
||||
r_shift_data[7] <= r_shift_data[6];
|
||||
|
||||
r_shift_data[8] <= r_shift_data[7];
|
||||
|
||||
r_shift_data[9] <= r_shift_data[8];
|
||||
|
||||
r_shift_data[10] <= r_shift_data[9];
|
||||
|
||||
r_shift_data[11] <= r_shift_data[10];
|
||||
|
||||
r_shift_data[12] <= r_shift_data[11];
|
||||
|
||||
r_shift_data[13] <= r_shift_data[12];
|
||||
|
||||
r_shift_data[14] <= r_shift_data[13];
|
||||
|
||||
end
|
||||
end
|
||||
|
||||
wire [3:0]dd;
|
||||
wire [2:0]ddi;
|
||||
assign dd = {r_shift_data[0],r_shift_data[5], r_shift_data[10],r_shift_data[14]};
|
||||
|
||||
assign ddi = { r_shift_data[3], r_shift_data[7], r_shift_data[12]};
|
||||
|
||||
|
||||
|
||||
reg [14:0] r_MSB_BUF0;
|
||||
|
||||
always @(posedge clk_in)
|
||||
|
||||
begin
|
||||
|
||||
case(dd[3:0])
|
||||
|
||||
4'd0: r_MSB_BUF0 <= {data_in[15],data_in[15],data_in[15],data_in[15],data_in[15],data_in[15],data_in[15],data_in[15],data_in[14],data_in[14],data_in[14],data_in[14],data_in[13],data_in[13],data_in[12]};
|
||||
|
||||
4'd1: r_MSB_BUF0 <= {data_in[15],data_in[15],data_in[15],data_in[15],data_in[15],data_in[15],data_in[15],data_in[14],data_in[14],data_in[14],data_in[14],data_in[13],data_in[13],data_in[12],data_in[15]};
|
||||
|
||||
4'd2: r_MSB_BUF0 <= {data_in[15],data_in[15],data_in[15],data_in[15],data_in[15],data_in[15],data_in[14],data_in[14],data_in[14],data_in[14],data_in[13],data_in[13],data_in[12],data_in[15],data_in[15]};
|
||||
|
||||
4'd3: r_MSB_BUF0 <= {data_in[15],data_in[15],data_in[15],data_in[15],data_in[15],data_in[14],data_in[14],data_in[14],data_in[14],data_in[13],data_in[13],data_in[12],data_in[15],data_in[15],data_in[15]};
|
||||
|
||||
4'd4: r_MSB_BUF0 <= {data_in[15],data_in[15],data_in[15],data_in[15],data_in[14],data_in[14],data_in[14],data_in[14],data_in[13],data_in[13],data_in[12],data_in[15],data_in[15],data_in[15],data_in[15]};
|
||||
|
||||
4'd5: r_MSB_BUF0 <= {data_in[15],data_in[15],data_in[15],data_in[14],data_in[14],data_in[14],data_in[14],data_in[13],data_in[13],data_in[12],data_in[15],data_in[15],data_in[15],data_in[15],data_in[15]};
|
||||
|
||||
4'd6: r_MSB_BUF0 <= {data_in[15],data_in[15],data_in[14],data_in[14],data_in[14],data_in[14],data_in[13],data_in[13],data_in[12],data_in[15],data_in[15],data_in[15],data_in[15],data_in[15],data_in[15]};
|
||||
|
||||
4'd7: r_MSB_BUF0 <= {data_in[15],data_in[14],data_in[14],data_in[14],data_in[14],data_in[13],data_in[13],data_in[12],data_in[15],data_in[15],data_in[15],data_in[15],data_in[15],data_in[15],data_in[15]};
|
||||
|
||||
4'd8: r_MSB_BUF0 <= {data_in[14],data_in[14],data_in[14],data_in[14],data_in[13],data_in[13],data_in[12],data_in[15],data_in[15],data_in[15],data_in[15],data_in[15],data_in[15],data_in[15],data_in[15]};
|
||||
|
||||
4'd9: r_MSB_BUF0 <= {data_in[14],data_in[14],data_in[14],data_in[13],data_in[13],data_in[12],data_in[15],data_in[15],data_in[15],data_in[15],data_in[15],data_in[15],data_in[15],data_in[15],data_in[14]};
|
||||
|
||||
4'd10: r_MSB_BUF0 <= {data_in[14],data_in[14],data_in[13],data_in[13],data_in[12],data_in[15],data_in[15],data_in[15],data_in[15],data_in[15],data_in[15],data_in[15],data_in[15],data_in[14],data_in[14]};
|
||||
|
||||
4'd11: r_MSB_BUF0 <= {data_in[14],data_in[13],data_in[13],data_in[12],data_in[15],data_in[15],data_in[15],data_in[15],data_in[15],data_in[15],data_in[15],data_in[15],data_in[14],data_in[14],data_in[14]};
|
||||
|
||||
4'd12: r_MSB_BUF0 <= {data_in[13],data_in[13],data_in[12],data_in[15],data_in[15],data_in[15],data_in[15],data_in[15],data_in[15],data_in[15],data_in[15],data_in[14],data_in[14],data_in[14],data_in[14]};
|
||||
|
||||
4'd13: r_MSB_BUF0 <= {data_in[13],data_in[12],data_in[15],data_in[15],data_in[15],data_in[15],data_in[15],data_in[15],data_in[15],data_in[15],data_in[14],data_in[14],data_in[14],data_in[14],data_in[13]};
|
||||
|
||||
4'd14: r_MSB_BUF0 <= {data_in[12],data_in[15],data_in[15],data_in[15],data_in[15],data_in[15],data_in[15],data_in[15],data_in[15],data_in[14],data_in[14],data_in[14],data_in[14],data_in[13],data_in[13]};
|
||||
|
||||
4'd15: r_MSB_BUF0 <= {data_in[15],data_in[15],data_in[15],data_in[15],data_in[15],data_in[15],data_in[15],data_in[15],data_in[14],data_in[14],data_in[14],data_in[14],data_in[13],data_in[13],data_in[12]};
|
||||
|
||||
|
||||
endcase
|
||||
|
||||
end
|
||||
|
||||
|
||||
reg [6:0] r_ISB_BUF0;
|
||||
|
||||
always @(posedge clk_in)
|
||||
|
||||
begin
|
||||
|
||||
case(ddi[2:0])
|
||||
|
||||
3'd0: r_ISB_BUF0 <= {data_in[11],data_in[11],data_in[11],data_in[11],data_in[10],data_in[10],data_in[9]};
|
||||
|
||||
3'd1: r_ISB_BUF0 <= {data_in[11],data_in[11],data_in[11],data_in[10],data_in[10],data_in[9],data_in[11]};
|
||||
|
||||
3'd2: r_ISB_BUF0 <= {data_in[11],data_in[11],data_in[10],data_in[10],data_in[9],data_in[11],data_in[11]};
|
||||
|
||||
3'd3: r_ISB_BUF0 <= {data_in[11],data_in[10],data_in[10],data_in[9],data_in[11],data_in[11],data_in[11]};
|
||||
|
||||
3'd4: r_ISB_BUF0 <= {data_in[10],data_in[10],data_in[9],data_in[11],data_in[11],data_in[11],data_in[11]};
|
||||
|
||||
3'd5: r_ISB_BUF0 <= {data_in[10],data_in[9],data_in[11],data_in[11],data_in[11],data_in[11],data_in[10]};
|
||||
|
||||
3'd6: r_ISB_BUF0 <= {data_in[9],data_in[11],data_in[11],data_in[11],data_in[11],data_in[10],data_in[10]};
|
||||
|
||||
3'd7: r_ISB_BUF0 <= {data_in[11],data_in[11],data_in[11],data_in[11],data_in[10],data_in[10],data_in[9]};
|
||||
|
||||
endcase
|
||||
|
||||
end
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
reg [8:0] r_LSB_BUF0;
|
||||
|
||||
always @(posedge clk_in)
|
||||
|
||||
begin
|
||||
|
||||
r_LSB_BUF0 <= {data_in[8],data_in[7],data_in[6],data_in[5],data_in[4],data_in[3],data_in[2],data_in[1],data_in[0]};
|
||||
|
||||
end
|
||||
|
||||
|
||||
|
||||
assign DEM_LSB_OUT = r_LSB_BUF0;
|
||||
|
||||
assign DEM_ISB_OUT = r_ISB_BUF0;
|
||||
|
||||
assign DEM_MSB_OUT = r_MSB_BUF0;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
|
|
@ -0,0 +1,202 @@
|
|||
module DAC_DEM_16 (CLK_IN,prbs_en,
|
||||
|
||||
set0,set1,set2,set3,set4,set5,set6,set7,set8,set9,set10,set11,set12,set13,set14,set15,
|
||||
|
||||
DATA_IN0,DATA_IN1,DATA_IN2,DATA_IN3,DATA_IN4,DATA_IN5,DATA_IN6,DATA_IN7,DATA_IN8,DATA_IN9,DATA_IN10,DATA_IN11,DATA_IN12,DATA_IN13,DATA_IN14,DATA_IN15,
|
||||
|
||||
A_DEM_MSB_OUT0,A_DEM_MSB_OUT1,A_DEM_MSB_OUT2,A_DEM_MSB_OUT3,A_DEM_MSB_OUT4,A_DEM_MSB_OUT5,A_DEM_MSB_OUT6,A_DEM_MSB_OUT7,
|
||||
|
||||
B_DEM_MSB_OUT0,B_DEM_MSB_OUT1,B_DEM_MSB_OUT2,B_DEM_MSB_OUT3,B_DEM_MSB_OUT4,B_DEM_MSB_OUT5,B_DEM_MSB_OUT6,B_DEM_MSB_OUT7,
|
||||
|
||||
A_DEM_ISB_OUT0,A_DEM_ISB_OUT1,A_DEM_ISB_OUT2,A_DEM_ISB_OUT3,A_DEM_ISB_OUT4,A_DEM_ISB_OUT5,A_DEM_ISB_OUT6,A_DEM_ISB_OUT7,
|
||||
|
||||
B_DEM_ISB_OUT0,B_DEM_ISB_OUT1,B_DEM_ISB_OUT2,B_DEM_ISB_OUT3,B_DEM_ISB_OUT4,B_DEM_ISB_OUT5,B_DEM_ISB_OUT6,B_DEM_ISB_OUT7,
|
||||
|
||||
A_DEM_LSB_OUT0,A_DEM_LSB_OUT1,A_DEM_LSB_OUT2,A_DEM_LSB_OUT3,A_DEM_LSB_OUT4,A_DEM_LSB_OUT5,A_DEM_LSB_OUT6,A_DEM_LSB_OUT7,
|
||||
|
||||
B_DEM_LSB_OUT0,B_DEM_LSB_OUT1,B_DEM_LSB_OUT2,B_DEM_LSB_OUT3,B_DEM_LSB_OUT4,B_DEM_LSB_OUT5,B_DEM_LSB_OUT6,B_DEM_LSB_OUT7
|
||||
);
|
||||
|
||||
input CLK_IN;
|
||||
|
||||
input prbs_en;
|
||||
|
||||
input [14:0] set0,set1,set2,set3,set4,set5,set6,set7,set8,set9,set10,set11,set12,set13,set14,set15;
|
||||
|
||||
input [15:0] DATA_IN0,DATA_IN1,DATA_IN2,DATA_IN3,DATA_IN4,DATA_IN5,DATA_IN6,DATA_IN7,DATA_IN8,DATA_IN9,DATA_IN10,DATA_IN11,DATA_IN12,DATA_IN13,DATA_IN14,DATA_IN15;
|
||||
|
||||
output [14:0] A_DEM_MSB_OUT0,A_DEM_MSB_OUT1,A_DEM_MSB_OUT2,A_DEM_MSB_OUT3,A_DEM_MSB_OUT4,A_DEM_MSB_OUT5,A_DEM_MSB_OUT6,A_DEM_MSB_OUT7;
|
||||
|
||||
output [14:0] B_DEM_MSB_OUT0,B_DEM_MSB_OUT1,B_DEM_MSB_OUT2,B_DEM_MSB_OUT3,B_DEM_MSB_OUT4,B_DEM_MSB_OUT5,B_DEM_MSB_OUT6,B_DEM_MSB_OUT7;
|
||||
|
||||
output [6:0] A_DEM_ISB_OUT0,A_DEM_ISB_OUT1,A_DEM_ISB_OUT2,A_DEM_ISB_OUT3,A_DEM_ISB_OUT4,A_DEM_ISB_OUT5,A_DEM_ISB_OUT6,A_DEM_ISB_OUT7;
|
||||
|
||||
output [6:0] B_DEM_ISB_OUT0,B_DEM_ISB_OUT1,B_DEM_ISB_OUT2,B_DEM_ISB_OUT3,B_DEM_ISB_OUT4,B_DEM_ISB_OUT5,B_DEM_ISB_OUT6,B_DEM_ISB_OUT7;
|
||||
|
||||
output [8:0] A_DEM_LSB_OUT0,A_DEM_LSB_OUT1,A_DEM_LSB_OUT2,A_DEM_LSB_OUT3,A_DEM_LSB_OUT4,A_DEM_LSB_OUT5,A_DEM_LSB_OUT6,A_DEM_LSB_OUT7;
|
||||
|
||||
output [8:0] B_DEM_LSB_OUT0,B_DEM_LSB_OUT1,B_DEM_LSB_OUT2,B_DEM_LSB_OUT3,B_DEM_LSB_OUT4,B_DEM_LSB_OUT5,B_DEM_LSB_OUT6,B_DEM_LSB_OUT7;
|
||||
|
||||
DAC_DEM A_DEM_0(
|
||||
.clk_in (CLK_IN),
|
||||
.data_in (DATA_IN0),
|
||||
.prbs_en (prbs_en),
|
||||
.set (set0),
|
||||
.DEM_LSB_OUT (A_DEM_LSB_OUT0),
|
||||
.DEM_ISB_OUT (A_DEM_ISB_OUT0),
|
||||
.DEM_MSB_OUT (A_DEM_MSB_OUT0)
|
||||
);
|
||||
|
||||
DAC_DEM A_DEM_1(
|
||||
.clk_in (CLK_IN),
|
||||
.data_in (DATA_IN1),
|
||||
.prbs_en (prbs_en),
|
||||
.set (set1),
|
||||
.DEM_LSB_OUT (A_DEM_LSB_OUT1),
|
||||
.DEM_ISB_OUT (A_DEM_ISB_OUT1),
|
||||
.DEM_MSB_OUT (A_DEM_MSB_OUT1)
|
||||
);
|
||||
|
||||
DAC_DEM A_DEM_2(
|
||||
.clk_in (CLK_IN),
|
||||
.data_in (DATA_IN2),
|
||||
.prbs_en (prbs_en),
|
||||
.set (set2),
|
||||
.DEM_LSB_OUT (A_DEM_LSB_OUT2),
|
||||
.DEM_ISB_OUT (A_DEM_ISB_OUT2),
|
||||
.DEM_MSB_OUT (A_DEM_MSB_OUT2)
|
||||
);
|
||||
|
||||
DAC_DEM A_DEM_3(
|
||||
.clk_in (CLK_IN),
|
||||
.data_in (DATA_IN3),
|
||||
.prbs_en (prbs_en),
|
||||
.set (set3),
|
||||
.DEM_LSB_OUT (A_DEM_LSB_OUT3),
|
||||
.DEM_ISB_OUT (A_DEM_ISB_OUT3),
|
||||
.DEM_MSB_OUT (A_DEM_MSB_OUT3)
|
||||
);
|
||||
|
||||
DAC_DEM A_DEM_4(
|
||||
.clk_in (CLK_IN),
|
||||
.data_in (DATA_IN4),
|
||||
.prbs_en (prbs_en),
|
||||
.set (set4),
|
||||
.DEM_LSB_OUT (A_DEM_LSB_OUT4),
|
||||
.DEM_ISB_OUT (A_DEM_ISB_OUT4),
|
||||
.DEM_MSB_OUT (A_DEM_MSB_OUT4)
|
||||
);
|
||||
|
||||
DAC_DEM A_DEM_5(
|
||||
.clk_in (CLK_IN),
|
||||
.data_in (DATA_IN5),
|
||||
.prbs_en (prbs_en),
|
||||
.set (set5),
|
||||
.DEM_LSB_OUT (A_DEM_LSB_OUT5),
|
||||
.DEM_ISB_OUT (A_DEM_ISB_OUT5),
|
||||
.DEM_MSB_OUT (A_DEM_MSB_OUT5)
|
||||
);
|
||||
|
||||
DAC_DEM A_DEM_6(
|
||||
.clk_in (CLK_IN),
|
||||
.data_in (DATA_IN6),
|
||||
.prbs_en (prbs_en),
|
||||
.set (set6),
|
||||
.DEM_LSB_OUT (A_DEM_LSB_OUT6),
|
||||
.DEM_ISB_OUT (A_DEM_ISB_OUT6),
|
||||
.DEM_MSB_OUT (A_DEM_MSB_OUT6)
|
||||
);
|
||||
|
||||
DAC_DEM A_DEM_7(
|
||||
.clk_in (CLK_IN),
|
||||
.data_in (DATA_IN7),
|
||||
.prbs_en (prbs_en),
|
||||
.set (set7),
|
||||
.DEM_LSB_OUT (A_DEM_LSB_OUT7),
|
||||
.DEM_ISB_OUT (A_DEM_ISB_OUT7),
|
||||
.DEM_MSB_OUT (A_DEM_MSB_OUT7)
|
||||
);
|
||||
|
||||
DAC_DEM B_DEM_0(
|
||||
.clk_in (CLK_IN),
|
||||
.data_in (DATA_IN8),
|
||||
.prbs_en (prbs_en),
|
||||
.set (set8),
|
||||
.DEM_LSB_OUT (B_DEM_LSB_OUT0),
|
||||
.DEM_ISB_OUT (B_DEM_ISB_OUT0),
|
||||
.DEM_MSB_OUT (B_DEM_MSB_OUT0)
|
||||
);
|
||||
|
||||
DAC_DEM B_DEM_1(
|
||||
.clk_in (CLK_IN),
|
||||
.data_in (DATA_IN9),
|
||||
.prbs_en (prbs_en),
|
||||
.set (set9),
|
||||
.DEM_LSB_OUT (B_DEM_LSB_OUT1),
|
||||
.DEM_ISB_OUT (B_DEM_ISB_OUT1),
|
||||
.DEM_MSB_OUT (B_DEM_MSB_OUT1)
|
||||
);
|
||||
|
||||
DAC_DEM B_DEM_2(
|
||||
.clk_in (CLK_IN),
|
||||
.data_in (DATA_IN10),
|
||||
.prbs_en (prbs_en),
|
||||
.set (set10),
|
||||
.DEM_LSB_OUT (B_DEM_LSB_OUT2),
|
||||
.DEM_ISB_OUT (B_DEM_ISB_OUT2),
|
||||
.DEM_MSB_OUT (B_DEM_MSB_OUT2)
|
||||
);
|
||||
|
||||
DAC_DEM B_DEM_3(
|
||||
.clk_in (CLK_IN),
|
||||
.data_in (DATA_IN11),
|
||||
.prbs_en (prbs_en),
|
||||
.set (set11),
|
||||
.DEM_LSB_OUT (B_DEM_LSB_OUT3),
|
||||
.DEM_ISB_OUT (B_DEM_ISB_OUT3),
|
||||
.DEM_MSB_OUT (B_DEM_MSB_OUT3)
|
||||
);
|
||||
|
||||
DAC_DEM B_DEM_4(
|
||||
.clk_in (CLK_IN),
|
||||
.data_in (DATA_IN12),
|
||||
.prbs_en (prbs_en),
|
||||
.set (set12),
|
||||
.DEM_LSB_OUT (B_DEM_LSB_OUT4),
|
||||
.DEM_ISB_OUT (B_DEM_ISB_OUT4),
|
||||
.DEM_MSB_OUT (B_DEM_MSB_OUT4)
|
||||
);
|
||||
|
||||
DAC_DEM B_DEM_5(
|
||||
.clk_in (CLK_IN),
|
||||
.data_in (DATA_IN13),
|
||||
.prbs_en (prbs_en),
|
||||
.set (set13),
|
||||
.DEM_LSB_OUT (B_DEM_LSB_OUT5),
|
||||
.DEM_ISB_OUT (B_DEM_ISB_OUT5),
|
||||
.DEM_MSB_OUT (B_DEM_MSB_OUT5)
|
||||
);
|
||||
|
||||
DAC_DEM B_DEM_6(
|
||||
.clk_in (CLK_IN),
|
||||
.data_in (DATA_IN14),
|
||||
.prbs_en (prbs_en),
|
||||
.set (set14),
|
||||
.DEM_LSB_OUT (B_DEM_LSB_OUT6),
|
||||
.DEM_ISB_OUT (B_DEM_ISB_OUT6),
|
||||
.DEM_MSB_OUT (B_DEM_MSB_OUT6)
|
||||
);
|
||||
|
||||
DAC_DEM B_DEM_7(
|
||||
.clk_in (CLK_IN),
|
||||
.data_in (DATA_IN15),
|
||||
.prbs_en (prbs_en),
|
||||
.set (set15),
|
||||
.DEM_LSB_OUT (B_DEM_LSB_OUT7),
|
||||
.DEM_ISB_OUT (B_DEM_ISB_OUT7),
|
||||
.DEM_MSB_OUT (B_DEM_MSB_OUT7)
|
||||
);
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
|
|
@ -0,0 +1,83 @@
|
|||
module DAC_DEM_4 (CLK_IN,prbs_en,
|
||||
|
||||
set0,set1,set2,set3,
|
||||
|
||||
DATA_IN0,DATA_IN1,DATA_IN2,DATA_IN3,
|
||||
|
||||
DEM_MSB_OUT0,DEM_MSB_OUT1,DEM_MSB_OUT2,DEM_MSB_OUT3,
|
||||
|
||||
|
||||
|
||||
DEM_ISB_OUT0,DEM_ISB_OUT1,DEM_ISB_OUT2,DEM_ISB_OUT3,
|
||||
|
||||
|
||||
|
||||
DEM_LSB_OUT0,DEM_LSB_OUT1,DEM_LSB_OUT2,DEM_LSB_OUT3
|
||||
|
||||
|
||||
);
|
||||
|
||||
input CLK_IN;
|
||||
|
||||
input prbs_en;
|
||||
|
||||
input [14:0] set0,set1,set2,set3;
|
||||
|
||||
input [15:0] DATA_IN0,DATA_IN1,DATA_IN2,DATA_IN3;
|
||||
|
||||
output [14:0] DEM_MSB_OUT0,DEM_MSB_OUT1,DEM_MSB_OUT2,DEM_MSB_OUT3;
|
||||
|
||||
|
||||
|
||||
output [6:0] DEM_ISB_OUT0,DEM_ISB_OUT1,DEM_ISB_OUT2,DEM_ISB_OUT3;
|
||||
|
||||
|
||||
|
||||
output [8:0] DEM_LSB_OUT0,DEM_LSB_OUT1,DEM_LSB_OUT2,DEM_LSB_OUT3;
|
||||
|
||||
|
||||
|
||||
DAC_DEM A_DEM_0(
|
||||
.clk_in (CLK_IN),
|
||||
.data_in (DATA_IN0),
|
||||
.prbs_en (prbs_en),
|
||||
.set (set0),
|
||||
.DEM_LSB_OUT (DEM_LSB_OUT0),
|
||||
.DEM_ISB_OUT (DEM_ISB_OUT0),
|
||||
.DEM_MSB_OUT (DEM_MSB_OUT0)
|
||||
);
|
||||
|
||||
DAC_DEM A_DEM_1(
|
||||
.clk_in (CLK_IN),
|
||||
.data_in (DATA_IN1),
|
||||
.prbs_en (prbs_en),
|
||||
.set (set1),
|
||||
.DEM_LSB_OUT (DEM_LSB_OUT1),
|
||||
.DEM_ISB_OUT (DEM_ISB_OUT1),
|
||||
.DEM_MSB_OUT (DEM_MSB_OUT1)
|
||||
);
|
||||
|
||||
DAC_DEM A_DEM_2(
|
||||
.clk_in (CLK_IN),
|
||||
.data_in (DATA_IN2),
|
||||
.prbs_en (prbs_en),
|
||||
.set (set2),
|
||||
.DEM_LSB_OUT (DEM_LSB_OUT2),
|
||||
.DEM_ISB_OUT (DEM_ISB_OUT2),
|
||||
.DEM_MSB_OUT (DEM_MSB_OUT2)
|
||||
);
|
||||
|
||||
DAC_DEM A_DEM_3(
|
||||
.clk_in (CLK_IN),
|
||||
.data_in (DATA_IN3),
|
||||
.prbs_en (prbs_en),
|
||||
.set (set3),
|
||||
.DEM_LSB_OUT (DEM_LSB_OUT3),
|
||||
.DEM_ISB_OUT (DEM_ISB_OUT3),
|
||||
.DEM_MSB_OUT (DEM_MSB_OUT3)
|
||||
);
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
|
|
@ -0,0 +1,253 @@
|
|||
//+FHDR--------------------------------------------------------------------------------------------------------
|
||||
// Company:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// File Name : iopad.v
|
||||
// Department :
|
||||
// Author : pwy
|
||||
// Author's Tel :
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Relese History
|
||||
// Version Date Author Description
|
||||
// 1.2 2024-06-12 pwy Integrate a digital module and two SPI modules with PLL
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Keywords :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Parameter
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Purpose :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Target Device:
|
||||
// Tool versions:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Reuse Issues
|
||||
// Reset Strategy:
|
||||
// Clock Domains:
|
||||
// Critical Timing:
|
||||
// Asynchronous I/F:
|
||||
// Synthesizable (y/n):
|
||||
// Other:
|
||||
//-FHDR--------------------------------------------------------------------------------------------------------
|
||||
`include "../define/chip_define.v"
|
||||
module iopad (
|
||||
//+++++++++++++++++++++++++++++++++++++++++++++//
|
||||
// PAD Strat //
|
||||
//+++++++++++++++++++++++++++++++++++++++++++++//
|
||||
input PI_async_rstn // hardware Reset, active low
|
||||
//sync
|
||||
,input PI_sync_in // Chip synchronization signal input, high pulse valid
|
||||
,output PO_sync_out // Chip synchronization signal output, high pulse valid
|
||||
//Feedback signal
|
||||
,input [1 :0] PI_ch0_feedback // Ch0 Feedback signals from the readout chip
|
||||
`ifdef CHANNEL_IS_FOUR
|
||||
,input [1 :0] PI_ch1_feedback // Ch1 Feedback signals from the readout chip
|
||||
,input [1 :0] PI_ch2_feedback // Ch2 Feedback signals from the readout chip
|
||||
,input [1 :0] PI_ch3_feedback // Ch3 Feedback signals from the readout chip
|
||||
`endif
|
||||
//config chip id
|
||||
,input [4 :0] PI_cfgid // During power-on initialization, the IO configuration
|
||||
// values are read as the chip ID number
|
||||
//spi port
|
||||
,input PI_sclk // Spi Clock
|
||||
,input PI_csn // Spi Chip Select active low
|
||||
,input PI_mosi // Spi Mosi
|
||||
,output PO_miso // Spi Miso
|
||||
//irq
|
||||
,output PO_irq // Interrupt signal in the chip, high level active
|
||||
//+++++++++++++++++++++++++++++++++++++++++++++//
|
||||
// PAD End //
|
||||
//+++++++++++++++++++++++++++++++++++++++++++++//
|
||||
|
||||
//+++++++++++++++++++++++++++++++++++++++++++++//
|
||||
// Internal signal Start //
|
||||
//+++++++++++++++++++++++++++++++++++++++++++++//
|
||||
,output async_rstn // hardware Reset, active low
|
||||
//sync
|
||||
,output sync_in // Chip synchronization signal input, high pulse valid
|
||||
,input sync_out // Chip synchronization signal output, high pulse valid
|
||||
//Feedback signal
|
||||
,output [1 :0] ch0_feedback // Ch0 Feedback signals from the readout chip
|
||||
`ifdef CHANNEL_IS_FOUR
|
||||
,output [1 :0] ch1_feedback // Ch1 Feedback signals from the readout chip
|
||||
,output [1 :0] ch2_feedback // Ch2 Feedback signals from the readout chip
|
||||
,output [1 :0] ch3_feedback // Ch3 Feedback signals from the readout chip
|
||||
`endif
|
||||
//config chip id
|
||||
,output [4 :0] cfgid // During power-on initialization, the IO configuration
|
||||
// values are read as the chip ID number
|
||||
//spi port
|
||||
,output sclk // Spi Clock
|
||||
,output csn // Spi Chip Select active low
|
||||
,output mosi // Spi Mosi
|
||||
,input miso // Spi Miso
|
||||
,input oen // Spi Miso output enable
|
||||
//irq
|
||||
,input irq // Interrupt signal in the chip, high level active
|
||||
);
|
||||
|
||||
`ifdef TSMC_IC
|
||||
//++++++++++++++++++++++++++++++++++++++++++++++++++//
|
||||
// ASIC PAD --> TSMC //
|
||||
//++++++++++++++++++++++++++++++++++++++++++++++++++//
|
||||
//PI_async_rstn
|
||||
PDUW04SDGZ_V_G PDUW08SDGZ_V_G_async_rstn (
|
||||
.I ( 1'b0 )
|
||||
,.OEN ( 1'b1 )
|
||||
,.REN ( 1'b0 )
|
||||
,.PAD ( PI_async_rstn )
|
||||
,.C ( async_rstn )
|
||||
);
|
||||
|
||||
//sync_in
|
||||
PDDW04SDGZ_V_G PDDW04SDGZ_V_G_sync_in (
|
||||
.I ( 1'b0 )
|
||||
,.OEN ( 1'b1 )
|
||||
,.REN ( 1'b0 )
|
||||
,.PAD ( PI_sync_in )
|
||||
,.C ( sync_in )
|
||||
);
|
||||
|
||||
//sync_out
|
||||
PDDW04SDGZ_V_G PDDW08SDGZ_V_G_sync_out (
|
||||
.I ( sync_out )
|
||||
,.OEN ( 1'b0 )
|
||||
,.REN ( 1'b0 )
|
||||
,.PAD ( PO_sync_out )
|
||||
,.C ( )
|
||||
);
|
||||
|
||||
//ch0_feedback
|
||||
PDDW04SDGZ_V_G PDDW04SDGZ_V_G_ch0_feedback0 (
|
||||
.I ( 1'b0 )
|
||||
,.OEN ( 1'b1 )
|
||||
,.REN ( 1'b0 )
|
||||
,.PAD ( PI_ch0_feedback[0] )
|
||||
,.C ( ch0_feedback[0] )
|
||||
);
|
||||
|
||||
PDDW04SDGZ_V_G PDDW04SDGZ_V_G_ch0_feedback1 (
|
||||
.I ( 1'b0 )
|
||||
,.OEN ( 1'b1 )
|
||||
,.REN ( 1'b0 )
|
||||
,.PAD ( PI_ch0_feedback[1] )
|
||||
,.C ( ch0_feedback[1] )
|
||||
);
|
||||
|
||||
//cfgid
|
||||
PDDW04SDGZ_V_G PDDW04DGZ_V_G_cfgid0 (
|
||||
.I ( 1'b0 )
|
||||
,.OEN ( 1'b1 )
|
||||
,.REN ( 1'b0 )
|
||||
,.PAD ( PI_cfgid[0] )
|
||||
,.C ( cfgid[0] )
|
||||
);
|
||||
|
||||
PDDW04SDGZ_V_G PDDW04DGZ_V_G_cfgid1 (
|
||||
.I ( 1'b0 )
|
||||
,.OEN ( 1'b1 )
|
||||
,.REN ( 1'b0 )
|
||||
,.PAD ( PI_cfgid[1] )
|
||||
,.C ( cfgid[1] )
|
||||
);
|
||||
|
||||
PDDW04SDGZ_V_G PDDW04DGZ_V_G_cfgid2 (
|
||||
.I ( 1'b0 )
|
||||
,.OEN ( 1'b1 )
|
||||
,.REN ( 1'b0 )
|
||||
,.PAD ( PI_cfgid[2] )
|
||||
,.C ( cfgid[2] )
|
||||
);
|
||||
|
||||
PDDW04SDGZ_V_G PDDW04DGZ_V_G_cfgid3 (
|
||||
.I ( 1'b0 )
|
||||
,.OEN ( 1'b1 )
|
||||
,.REN ( 1'b0 )
|
||||
,.PAD ( PI_cfgid[3] )
|
||||
,.C ( cfgid[3] )
|
||||
);
|
||||
|
||||
PDDW04SDGZ_V_G PDDW04DGZ_V_G_cfgid4 (
|
||||
.I ( 1'b0 )
|
||||
,.OEN ( 1'b1 )
|
||||
,.REN ( 1'b0 )
|
||||
,.PAD ( PI_cfgid[4] )
|
||||
,.C ( cfgid[4] )
|
||||
);
|
||||
|
||||
//sclk
|
||||
PDUW04SDGZ_V_G PDUW04SDGZ_V_G_sclk (
|
||||
.I ( 1'b0 )
|
||||
,.OEN ( 1'b1 )
|
||||
,.REN ( 1'b0 )
|
||||
,.PAD ( PI_sclk )
|
||||
,.C ( sclk )
|
||||
);
|
||||
|
||||
//csn
|
||||
PDUW04SDGZ_V_G PDUW04SDGZ_V_G_csn (
|
||||
.I ( 1'b0 )
|
||||
,.OEN ( 1'b1 )
|
||||
,.REN ( 1'b0 )
|
||||
,.PAD ( PI_csn )
|
||||
,.C ( csn )
|
||||
);
|
||||
|
||||
//mosi
|
||||
PDDW08SDGZ_V_G PDUW08SDGZ_V_G_mosi (
|
||||
.I ( 1'b0 )
|
||||
,.OEN ( 1'b1 )
|
||||
,.REN ( 1'b0 )
|
||||
,.PAD ( PI_mosi )
|
||||
,.C ( mosi )
|
||||
);
|
||||
|
||||
//miso
|
||||
PDUW08SDGZ_V_G PDUW08SDGZ_V_G_miso (
|
||||
.I ( miso )
|
||||
,.OEN ( oen )
|
||||
,.REN ( 1'b0 )
|
||||
,.PAD ( PO_miso )
|
||||
,.C ( )
|
||||
);
|
||||
|
||||
//irq
|
||||
PDDW08SDGZ_V_G PDDW08SDGZ_V_G_irq (
|
||||
.I ( irq )
|
||||
,.OEN ( 1'b0 )
|
||||
,.REN ( 1'b0 )
|
||||
,.PAD ( PO_irq )
|
||||
,.C ( )
|
||||
);
|
||||
|
||||
`elsif XILINX_FPGA
|
||||
//++++++++++++++++++++++++++++++++++++++++++++++++++//
|
||||
// FPGA PAD --> Xlinx //
|
||||
//++++++++++++++++++++++++++++++++++++++++++++++++++//
|
||||
//async_rstn
|
||||
assign async_rstn = PI_async_rstn ;
|
||||
//sync_in
|
||||
assign sync_in = PI_sync_in ;
|
||||
//sync_out
|
||||
assign PO_sync_out = sync_out ;
|
||||
//Feedback signal
|
||||
assign ch0_feedback = PI_ch0_feedback ;
|
||||
`ifdef CHANNEL_IS_FOUR
|
||||
assign ch1_feedback = PI_ch1_feedback ;
|
||||
assign ch2_feedback = PI_ch2_feedback ;
|
||||
assign ch3_feedback = PI_ch3_feedback ;
|
||||
`endif
|
||||
//config chip id
|
||||
assign cfgid = PI_cfgid ;
|
||||
//spi port
|
||||
assign sclk = PI_sclk ;
|
||||
assign csn = PI_csn ;
|
||||
assign mosi = PI_mosi ;
|
||||
assign PO_miso = oen ? 1'bz : miso ;
|
||||
//irq
|
||||
assign PO_irq = irq ;
|
||||
`endif
|
||||
|
||||
endmodule
|
||||
`include "../define/chip_undefine.v"
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,90 @@
|
|||
|
||||
`include "../define/chip_define.v"
|
||||
//`define TSMC_INITIALIZE_MEM
|
||||
module dpram #(
|
||||
parameter DATAWIDTH = 32
|
||||
,parameter ADDRWIDTH = 13
|
||||
)(
|
||||
input PortClk
|
||||
,input [ADDRWIDTH-1 :0] PortAAddr
|
||||
,input [DATAWIDTH-1 :0] PortADataIn
|
||||
,input PortAWriteEnable //active low
|
||||
,input PortAChipEnable //active low
|
||||
,input [(DATAWIDTH/8)-1 :0] PortAByteWriteEnable //active low
|
||||
,output [DATAWIDTH-1 :0] PortADataOut
|
||||
|
||||
,input [ADDRWIDTH-1 :0] PortBAddr
|
||||
,input [DATAWIDTH-1 :0] PortBDataIn
|
||||
,input PortBWriteEnable //active low
|
||||
,input PortBChipEnable //active low
|
||||
,input [(DATAWIDTH/8)-1 :0] PortBByteWriteEnable //active low
|
||||
,output [DATAWIDTH-1 :0] PortBDataOut
|
||||
);
|
||||
|
||||
//==================================================================================
|
||||
//XPM¡¡£í£å£í£ï£ò£ù
|
||||
//==================================================================================
|
||||
|
||||
`ifdef BEHAVIOR_SIM
|
||||
dpram_model #(
|
||||
.DATAWIDTH ( DATAWIDTH )
|
||||
,.ADDRWIDTH ( ADDRWIDTH )
|
||||
) dpram_model (
|
||||
.PortClk ( PortClk )
|
||||
,.PortAWriteEnable ( PortAWriteEnable )
|
||||
,.PortAChipEnable ( PortAChipEnable )
|
||||
,.PortAByteWriteEnable ( PortAByteWriteEnable )
|
||||
,.PortAAddr ( PortAAddr )
|
||||
,.PortADataIn ( PortADataIn )
|
||||
,.PortADataOut ( PortADataOut )
|
||||
,.PortBWriteEnable ( PortBWriteEnable )
|
||||
,.PortBChipEnable ( PortBChipEnable )
|
||||
,.PortBByteWriteEnable ( PortBByteWriteEnable_w )
|
||||
,.PortBAddr ( PortBAddr )
|
||||
,.PortBDataIn ( PortBDataIn )
|
||||
,.PortBDataOut ( PortBDataOut )
|
||||
);
|
||||
`elsif XINLINX_FPGA
|
||||
xil_tdpram #(
|
||||
.DATAWIDTH ( DATAWIDTH )
|
||||
,.ADDRWIDTH ( ADDRWIDTH )
|
||||
) U_xil_tdpram (
|
||||
.PortClk ( PortClk )
|
||||
,.PortAAddr ( PortAAddr )
|
||||
,.PortADataIn ( PortADataIn )
|
||||
,.PortAWriteEnable ( PortAWriteEnable )
|
||||
,.PortAChipEnable ( PortAChipEnable )
|
||||
,.PortAByteWriteEnable ( PortAByteWriteEnable )
|
||||
,.PortADataOut ( PortADataOut )
|
||||
,.PortBAddr ( PortBAddr )
|
||||
,.PortBDataIn ( PortBDataIn )
|
||||
,.PortBWriteEnable ( PortBWriteEnable )
|
||||
,.PortBChipEnable ( PortBChipEnable )
|
||||
,.PortBByteWriteEnable ( PortBByteWriteEnable )
|
||||
,.PortBDataOut ( PortBDataOut )
|
||||
);
|
||||
`elsif TSMC_IC
|
||||
tsmc_dpram #(
|
||||
.DATAWIDTH ( DATAWIDTH )
|
||||
,.ADDRWIDTH ( ADDRWIDTH )
|
||||
) U_tsmc_dpram (
|
||||
.PortClk ( PortClk )
|
||||
,.PortAAddr ( PortAAddr )
|
||||
,.PortADataIn ( PortADataIn )
|
||||
,.PortAWriteEnable ( PortAWriteEnable )
|
||||
,.PortAChipEnable ( PortAChipEnable )
|
||||
,.PortAByteWriteEnable ( PortAByteWriteEnable )
|
||||
,.PortADataOut ( PortADataOut )
|
||||
,.PortBAddr ( PortBAddr )
|
||||
,.PortBDataIn ( PortBDataIn )
|
||||
,.PortBWriteEnable ( PortBWriteEnable )
|
||||
,.PortBChipEnable ( PortBChipEnable )
|
||||
,.PortBByteWriteEnable ( PortBByteWriteEnable )
|
||||
,.PortBDataOut ( PortBDataOut )
|
||||
);
|
||||
`endif
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
`include "../define/chip_undefine.v"
|
||||
|
|
@ -0,0 +1,100 @@
|
|||
//+FHDR--------------------------------------------------------------------------------------------------------
|
||||
// Company:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// File Name : ssram_model.v
|
||||
// Department :
|
||||
// Author : PWY
|
||||
// Author's Tel :
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Relese History
|
||||
// Version Date Author Description
|
||||
// 1.0 2022-08-25 PWY
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Keywords :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Parameter
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Purpose :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Target Device:
|
||||
// Tool versions:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Reuse Issues
|
||||
// Reset Strategy:
|
||||
// Clock Domains:
|
||||
// Critical Timing:
|
||||
// Asynchronous I/F:
|
||||
// Synthesizable (y/n):
|
||||
// Other:
|
||||
//-FHDR--------------------------------------------------------------------------------------------------------
|
||||
|
||||
module dpram_model #(
|
||||
parameter DATAWIDTH = 32
|
||||
,parameter ADDRWIDTH = 13
|
||||
)(
|
||||
input PortClk
|
||||
,input [(ADDRWIDTH-1) :0] PortAAddr
|
||||
,input [(DATAWIDTH-1) :0] PortADataIn
|
||||
,input PortAWriteEnable
|
||||
,input PortAChipEnable //active low
|
||||
,input [(DATAWIDTH/8)-1:0] PortAByteWriteEnable
|
||||
,output reg [(DATAWIDTH-1) :0] PortADataOut
|
||||
|
||||
,input [(ADDRWIDTH-1) :0] PortBAddr
|
||||
,input [(DATAWIDTH-1) :0] PortBDataIn
|
||||
,input PortBWriteEnable
|
||||
,input PortBChipEnable //active low
|
||||
,input [(DATAWIDTH/8)-1:0] PortBByteWriteEnable
|
||||
,output reg [(DATAWIDTH-1) :0] PortBDataOut
|
||||
);
|
||||
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
//Function
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
function integer clog2(input integer bit_depth);
|
||||
begin
|
||||
for(clog2=0;bit_depth>0;clog2=clog2+1)
|
||||
bit_depth =bit_depth>>1;
|
||||
end
|
||||
endfunction
|
||||
|
||||
localparam LSB = clog2(DATAWIDTH/8 -1);
|
||||
|
||||
localparam NUM = DATAWIDTH/8;
|
||||
|
||||
localparam MEMDEPTH = 2**(ADDRWIDTH-LSB);
|
||||
|
||||
generate
|
||||
genvar i;
|
||||
for(i=0;i<NUM;i=i+1) begin :dpram_model
|
||||
reg [7:0] mem [(MEMDEPTH-1):0] /* synthesis syn_ramstyle = "no_rw_check" */;
|
||||
always @(posedge PortClk) begin
|
||||
if(!PortAWriteEnable && !PortAByteWriteEnable[i] && !PortAChipEnable) begin
|
||||
mem[PortAAddr] <= PortADataIn[8*(i+1)-1-:8];
|
||||
//PortADataOut[8*(i+1)-1-:8] <= PortADataIn[8*(i+1)-1-:8];
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge PortClk) begin
|
||||
if(!PortBWriteEnable && !PortBByteWriteEnable[i] && !PortBChipEnable) begin
|
||||
mem[PortBAddr] <= PortBDataIn[8*(i+1)-1-:8];
|
||||
//PortADataOut[8*(i+1)-1-:8] <= PortADataIn[8*(i+1)-1-:8];
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge PortClk) begin
|
||||
PortADataOut[8*(i+1)-1-:8] <= mem[PortAAddr[ADDRWIDTH-1:0]];
|
||||
end
|
||||
|
||||
always @(posedge PortClk) begin
|
||||
PortBDataOut[8*(i+1)-1-:8] <= mem[PortBAddr[ADDRWIDTH-1:0]];
|
||||
end
|
||||
end
|
||||
|
||||
endgenerate
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,106 @@
|
|||
|
||||
/*
|
||||
// module dmux
|
||||
module sram_dmux_m #(
|
||||
parameter ADDR_WIDTH_I = 11, // input port addr width
|
||||
parameter ADDR_WIDTH_O = 10, // output port addr width
|
||||
parameter DATA_WIDTH = 64 // in/output port data width
|
||||
)(
|
||||
input logic clk,
|
||||
input logic rst_n,
|
||||
sram_if.slave port_in,
|
||||
sram_if.master port_out[2**(ADDR_WIDTH_I-ADDR_WIDTH_O)-1:0]
|
||||
);
|
||||
localparam ASEL_WIDTH = ADDR_WIDTH_I-ADDR_WIDTH_O;
|
||||
logic [ASEL_WIDTH-1:0] data_sel, data_out_sel;
|
||||
assign data_sel = port_in.addr[ADDR_WIDTH_I-1 : ADDR_WIDTH_O];
|
||||
always @(posedge clk or negedge rst_n) begin
|
||||
if(!rst_n) begin
|
||||
data_out_sel <= 0;
|
||||
end else begin
|
||||
data_out_sel <= data_sel;
|
||||
end
|
||||
end
|
||||
|
||||
logic [DATA_WIDTH-1:0] dout_data[2**(ASEL_WIDTH)-1:0];
|
||||
genvar i;
|
||||
generate
|
||||
for (i = 0; i < 2**ASEL_WIDTH; i++) begin
|
||||
assign port_out[i].addr = (i == data_sel) ? port_in.addr[ADDR_WIDTH_O-1:0] : 0;
|
||||
assign port_out[i].wren = (i == data_sel) ? port_in.wren : 0;
|
||||
assign port_out[i].rden = (i == data_sel) ? port_in.rden : 0;
|
||||
assign port_out[i].din = (i == data_sel) ? port_in.din : 0;
|
||||
assign port_out[i].wben = (i == data_sel) ? port_in.wben : 0;
|
||||
assign dout_data[i]= port_out[i].dout;
|
||||
end
|
||||
endgenerate
|
||||
assign port_in.dout = dout_data[data_out_sel];
|
||||
|
||||
endmodule
|
||||
*/
|
||||
|
||||
// word dmux
|
||||
module sram_dmux_w #(
|
||||
parameter ADDR_WIDTH = 11, // input port addr width
|
||||
parameter DATA_WIDTH_I = 32, // input port data width
|
||||
parameter DATA_WIDTH_O = 64 // output port data width
|
||||
)(
|
||||
input logic clk,
|
||||
input logic rst_n,
|
||||
sram_if.slave port_in,
|
||||
sram_if.master port_out
|
||||
);
|
||||
|
||||
// calculate and buffer word select bit
|
||||
localparam DL = $clog2(DATA_WIDTH_I/8);
|
||||
localparam DH = $clog2(DATA_WIDTH_O/8);
|
||||
localparam WSEL_WIDTH = DH - DL;
|
||||
logic [WSEL_WIDTH-1:0] data_sel, data_out_sel;
|
||||
assign data_sel = port_in.addr[DH-1:DL];
|
||||
always @(posedge clk or negedge rst_n) begin
|
||||
if(!rst_n) begin
|
||||
data_out_sel <= 0;
|
||||
end else begin
|
||||
data_out_sel <= data_sel;
|
||||
end
|
||||
end
|
||||
//
|
||||
assign port_out.addr = port_in.addr;
|
||||
assign port_out.wren = port_in.wren;
|
||||
assign port_out.rden = port_in.rden;
|
||||
genvar i;
|
||||
generate
|
||||
for (i = 0; i < 2**(WSEL_WIDTH); i++) begin
|
||||
assign port_out.din[DATA_WIDTH_I*i +: DATA_WIDTH_I] = (i == data_sel) ? port_in.din : 0;
|
||||
assign port_out.wben[DATA_WIDTH_I/8*i +: DATA_WIDTH_I/8] = (i == data_sel) ? port_in.wben : 0;
|
||||
end
|
||||
endgenerate
|
||||
assign port_in.dout = port_out.dout[DATA_WIDTH_I*data_out_sel +: DATA_WIDTH_I];
|
||||
|
||||
endmodule
|
||||
|
||||
/*
|
||||
// data split
|
||||
module sram_split #(
|
||||
parameter ADDR_WIDTH = 11, // input port addr width
|
||||
parameter DATA_WIDTH_I = 64, // input port data width
|
||||
parameter DATA_WIDTH_O = 32 // output port data width
|
||||
)(
|
||||
sram_if.slave port_in,
|
||||
sram_if.master port_out[DATA_WIDTH_I/DATA_WIDTH_O-1:0]
|
||||
);
|
||||
localparam DH = $clog2(DATA_WIDTH_I/8);
|
||||
localparam DL = $clog2(DATA_WIDTH_O/8);
|
||||
genvar i;
|
||||
generate
|
||||
for (i = 0; i < DATA_WIDTH_I/DATA_WIDTH_O; i++) begin
|
||||
assign port_out[i].addr = {port_in.addr[ADDR_WIDTH-1:DH], {DL{1'b0}}};
|
||||
assign port_out[i].rden = port_in.rden;
|
||||
assign port_out[i].wren = port_in.wren;
|
||||
assign port_out[i].din = port_in.din[i*DATA_WIDTH_O +: DATA_WIDTH_O];
|
||||
assign port_out[i].wben = port_in.wben[i*DATA_WIDTH_O/8 +: DATA_WIDTH_O/8];
|
||||
assign port_in.dout[i*DATA_WIDTH_O +: DATA_WIDTH_O] = port_out[i].dout;
|
||||
end
|
||||
endgenerate
|
||||
endmodule
|
||||
*/
|
||||
|
|
@ -0,0 +1,58 @@
|
|||
interface sram_if #(parameter ADDR_WIDTH = 8, parameter DATA_WIDTH = 32)(input bit clk);
|
||||
// Signals for interfacing with the SRAM
|
||||
logic [ADDR_WIDTH-1:0] addr;
|
||||
logic [DATA_WIDTH-1:0] din;
|
||||
logic [DATA_WIDTH-1:0] dout;
|
||||
logic rden;
|
||||
logic wren;
|
||||
logic [DATA_WIDTH/8-1:0] wben;
|
||||
|
||||
modport master(
|
||||
output addr,
|
||||
output din,
|
||||
input dout,
|
||||
output wren,
|
||||
output rden,
|
||||
output wben
|
||||
);
|
||||
|
||||
modport slave (
|
||||
input addr,
|
||||
input din,
|
||||
output dout,
|
||||
input wren,
|
||||
input rden,
|
||||
input wben
|
||||
);
|
||||
/*
|
||||
// synopsys translate_off
|
||||
// write operation
|
||||
task write;
|
||||
input logic [ADDR_WIDTH-1:0] addr_in;
|
||||
input logic [DATA_WIDTH-1:0] data_in;
|
||||
input logic [DATA_WIDTH/8-1:0] byte_enable;
|
||||
begin
|
||||
addr = addr_in;
|
||||
din = data_in;
|
||||
wben = byte_enable;
|
||||
wren = 1;
|
||||
rden = 0;
|
||||
@(posedge clk);
|
||||
wren = 0;
|
||||
end
|
||||
endtask
|
||||
|
||||
// read oepration
|
||||
task read;
|
||||
input logic [ADDR_WIDTH-1:0] addr_in;
|
||||
begin
|
||||
addr = addr_in;
|
||||
wren = 0;
|
||||
rden = 1;
|
||||
@(posedge clk);
|
||||
rden = 0;
|
||||
end
|
||||
endtask
|
||||
// synopsys translate_on
|
||||
*/
|
||||
endinterface
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,215 @@
|
|||
|
||||
|
||||
module tsmc_dpram #(
|
||||
parameter DATAWIDTH = 32
|
||||
,parameter ADDRWIDTH = 14
|
||||
)(
|
||||
input PortClk
|
||||
,input [ADDRWIDTH-1 :0] PortAAddr
|
||||
,input [DATAWIDTH-1 :0] PortADataIn
|
||||
,input PortAWriteEnable //active low
|
||||
,input PortAChipEnable //active low
|
||||
,input [(DATAWIDTH/8)-1 :0] PortAByteWriteEnable //active low
|
||||
,output [DATAWIDTH-1 :0] PortADataOut
|
||||
|
||||
,input [ADDRWIDTH-1 :0] PortBAddr
|
||||
,input [DATAWIDTH-1 :0] PortBDataIn
|
||||
,input PortBWriteEnable //active low
|
||||
,input PortBChipEnable //active low
|
||||
,input [(DATAWIDTH/8)-1 :0] PortBByteWriteEnable //active low
|
||||
,output [DATAWIDTH-1 :0] PortBDataOut
|
||||
);
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
//Function
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
function integer clog2(input integer bit_depth);
|
||||
begin
|
||||
for(clog2=0;bit_depth>0;clog2=clog2+1)
|
||||
bit_depth =bit_depth>>1;
|
||||
end
|
||||
endfunction
|
||||
|
||||
localparam LSB = clog2(DATAWIDTH/8 -1);
|
||||
|
||||
generate
|
||||
if((DATAWIDTH == 32) && (ADDRWIDTH == 15)) begin:dpram_32X4096_generation
|
||||
|
||||
wire [DATAWIDTH-1:0] BWEBA;
|
||||
wire [DATAWIDTH-1:0] BWEBB;
|
||||
|
||||
assign BWEBA = {{8{PortAByteWriteEnable[3]}},{8{PortAByteWriteEnable[2]}},{8{PortAByteWriteEnable[1]}},{8{PortAByteWriteEnable[0]}}};
|
||||
assign BWEBB = {{8{PortBByteWriteEnable[3]}},{8{PortBByteWriteEnable[2]}},{8{PortBByteWriteEnable[1]}},{8{PortBByteWriteEnable[0]}}};
|
||||
|
||||
wire U0_CEBA;
|
||||
wire U0_CEBB;
|
||||
wire U1_CEBA;
|
||||
wire U1_CEBB;
|
||||
|
||||
assign U0_CEBA = PortAAddr[ADDRWIDTH-1] | PortAChipEnable;
|
||||
assign U0_CEBB = PortBAddr[ADDRWIDTH-1] | PortBChipEnable;
|
||||
|
||||
assign U1_CEBA = ~PortAAddr[ADDRWIDTH-1] | PortAChipEnable;
|
||||
assign U1_CEBB = ~PortBAddr[ADDRWIDTH-1] | PortBChipEnable;
|
||||
|
||||
wire [DATAWIDTH-1:0] U0_QA;
|
||||
wire [DATAWIDTH-1:0] U0_QB;
|
||||
wire [DATAWIDTH-1:0] U1_QA;
|
||||
wire [DATAWIDTH-1:0] U1_QB;
|
||||
|
||||
reg AA_1D_MSB;
|
||||
reg AB_1D_MSB;
|
||||
|
||||
always @(posedge PortClk) begin
|
||||
if(PortAWriteEnable == 1'b1) begin
|
||||
AA_1D_MSB <= PortAAddr[ADDRWIDTH-1];
|
||||
end
|
||||
else begin
|
||||
AA_1D_MSB <= AA_1D_MSB;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge PortClk) begin
|
||||
if(PortBWriteEnable == 1'b1) begin
|
||||
AB_1D_MSB <= PortBAddr[ADDRWIDTH-1];
|
||||
end
|
||||
else begin
|
||||
AB_1D_MSB <= AB_1D_MSB;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
assign PortADataOut = {DATAWIDTH{~AA_1D_MSB}} & U0_QA
|
||||
| {DATAWIDTH{AA_1D_MSB}} & U1_QA;
|
||||
|
||||
|
||||
assign PortBDataOut = {DATAWIDTH{~AB_1D_MSB}} & U0_QB
|
||||
| {DATAWIDTH{AB_1D_MSB}} & U1_QB;
|
||||
tsdn28hpcpuhdb4096x32m4mw_170a U0_TSDN28HPCPUHDB4096X32M4MW (
|
||||
.CLK ( PortClk )
|
||||
,.CEBA ( U0_CEBA )
|
||||
,.WEBA ( PortAWriteEnable )
|
||||
,.BWEBA ( BWEBA )
|
||||
,.AA ( PortAAddr[ADDRWIDTH-2:LSB] )
|
||||
,.DA ( PortADataIn )
|
||||
,.QA ( U0_QA )
|
||||
,.CEBB ( U0_CEBB )
|
||||
,.WEBB ( PortBWriteEnable )
|
||||
,.BWEBB ( BWEBB )
|
||||
,.AB ( PortBAddr[ADDRWIDTH-2:LSB] )
|
||||
,.DB ( PortBDataIn )
|
||||
,.QB ( U0_QB )
|
||||
,.RTSEL ( 2'b00 )
|
||||
,.WTSEL ( 2'b00 )
|
||||
,.PTSEL ( 2'b00 )
|
||||
);
|
||||
|
||||
tsdn28hpcpuhdb4096x32m4mw_170a U1_TSDN28HPCPUHDB4096X32M4MW (
|
||||
.CLK ( PortClk )
|
||||
,.CEBA ( U1_CEBA )
|
||||
,.WEBA ( PortAWriteEnable )
|
||||
,.BWEBA ( BWEBA )
|
||||
,.AA ( PortAAddr[ADDRWIDTH-2:LSB] )
|
||||
,.DA ( PortADataIn )
|
||||
,.QA ( U1_QA )
|
||||
,.CEBB ( U1_CEBB )
|
||||
,.WEBB ( PortBWriteEnable )
|
||||
,.BWEBB ( BWEBB )
|
||||
,.AB ( PortBAddr[ADDRWIDTH-2:LSB] )
|
||||
,.DB ( PortBDataIn )
|
||||
,.QB ( U1_QB )
|
||||
,.RTSEL ( 2'b00 )
|
||||
,.WTSEL ( 2'b00 )
|
||||
,.PTSEL ( 2'b00 )
|
||||
);
|
||||
end
|
||||
|
||||
else if((DATAWIDTH == 32) && (ADDRWIDTH == 8)) begin:spram_32X64_generation
|
||||
wire [DATAWIDTH-1:0] BWEBA = {{8{PortAByteWriteEnable[3]}},{8{PortAByteWriteEnable[2]}},{8{PortAByteWriteEnable[1]}},{8{PortAByteWriteEnable[0]}}};
|
||||
wire [DATAWIDTH-1:0] BWEBB = {{8{PortBByteWriteEnable[3]}},{8{PortBByteWriteEnable[2]}},{8{PortBByteWriteEnable[1]}},{8{PortBByteWriteEnable[0]}}};
|
||||
tsdn28hpcpuhdb64x32m4mw_170a U_tsdn28hpcpuhdb64x32m4mw_170a (
|
||||
.CLK ( PortClk )
|
||||
,.CEBA ( PortAChipEnable )
|
||||
,.WEBA ( PortAWriteEnable )
|
||||
,.BWEBA ( BWEBA )
|
||||
,.AA ( PortAAddr[ADDRWIDTH-1:LSB] )
|
||||
,.DA ( PortADataIn )
|
||||
,.QA ( PortADataOut )
|
||||
,.CEBB ( PortBChipEnable )
|
||||
,.WEBB ( PortBWriteEnable )
|
||||
,.BWEBB ( BWEBB )
|
||||
,.AB ( PortBAddr[ADDRWIDTH-1:LSB] )
|
||||
,.DB ( PortBDataIn )
|
||||
,.QB ( PortBDataOut )
|
||||
,.RTSEL ( 2'b00 )
|
||||
,.WTSEL ( 2'b00 )
|
||||
,.PTSEL ( 2'b00 )
|
||||
);
|
||||
end
|
||||
else if((DATAWIDTH == 256) && (ADDRWIDTH == 12)) begin:spram_512X128_generation
|
||||
genvar i;
|
||||
wire [DATAWIDTH-1:0] BWEBA ;
|
||||
wire [DATAWIDTH-1:0] BWEBB ;
|
||||
for(i=0;i<DATAWIDTH/8;i=i+1) begin
|
||||
assign BWEBA[8*i+:8] = {8{PortAByteWriteEnable[i]}};
|
||||
assign BWEBB[8*i+:8] = {8{PortBByteWriteEnable[i]}};
|
||||
end
|
||||
tsdn28hpcpuhdb128x128m4mw_170a U0_tsdn28hpcpuhdb128x128m4mw_170a (
|
||||
.CLK ( PortClk )
|
||||
,.CEBA ( PortAChipEnable )
|
||||
,.WEBA ( PortAWriteEnable )
|
||||
,.BWEBA ( BWEBA[127:0] )
|
||||
,.AA ( PortAAddr[ADDRWIDTH-1:LSB] )
|
||||
,.DA ( PortADataIn[127:0] )
|
||||
,.QA ( PortADataOut[127:0] )
|
||||
,.CEBB ( PortBChipEnable )
|
||||
,.WEBB ( PortBWriteEnable )
|
||||
,.BWEBB ( BWEBB[127:0] )
|
||||
,.AB ( PortBAddr[ADDRWIDTH-1:LSB] )
|
||||
,.DB ( PortBDataIn[127:0] )
|
||||
,.QB ( PortBDataOut[127:0] )
|
||||
,.RTSEL ( 2'b00 )
|
||||
,.WTSEL ( 2'b00 )
|
||||
,.PTSEL ( 2'b00 )
|
||||
);
|
||||
tsdn28hpcpuhdb128x128m4mw_170a U1_tsdn28hpcpuhdb128x128m4mw_170a (
|
||||
.CLK ( PortClk )
|
||||
,.CEBA ( PortAChipEnable )
|
||||
,.WEBA ( PortAWriteEnable )
|
||||
,.BWEBA ( BWEBA[255:128] )
|
||||
,.AA ( PortAAddr[ADDRWIDTH-1:LSB] )
|
||||
,.DA ( PortADataIn[255:128] )
|
||||
,.QA ( PortADataOut[255:128] )
|
||||
,.CEBB ( PortBChipEnable )
|
||||
,.WEBB ( PortBWriteEnable )
|
||||
,.BWEBB ( BWEBB[255:128] )
|
||||
,.AB ( PortBAddr[ADDRWIDTH-1:LSB] )
|
||||
,.DB ( PortBDataIn[255:128] )
|
||||
,.QB ( PortBDataOut[255:128] )
|
||||
,.RTSEL ( 2'b00 )
|
||||
,.WTSEL ( 2'b00 )
|
||||
,.PTSEL ( 2'b00 )
|
||||
);
|
||||
|
||||
end
|
||||
else begin:dpram_model_generation
|
||||
dpram_model #(
|
||||
.DATAWIDTH ( DATAWIDTH )
|
||||
,.ADDRWIDTH ( ADDRWIDTH-LSB )
|
||||
) U_dpram_model (
|
||||
.PortClk ( PortClk )
|
||||
,.PortAWriteEnable ( PortAWriteEnable )
|
||||
,.PortAChipEnable ( PortAChipEnable )
|
||||
,.PortAByteWriteEnable ( PortAByteWriteEnable )
|
||||
,.PortAAddr ( PortAAddr[ADDRWIDTH-1:LSB] )
|
||||
,.PortADataIn ( PortADataIn )
|
||||
,.PortADataOut ( PortADataOut )
|
||||
,.PortBWriteEnable ( PortBWriteEnable )
|
||||
,.PortBChipEnable ( PortBChipEnable )
|
||||
,.PortBByteWriteEnable ( PortBByteWriteEnable )
|
||||
,.PortBAddr ( PortBAddr[ADDRWIDTH-1:LSB] )
|
||||
,.PortBDataIn ( PortBDataIn )
|
||||
,.PortBDataOut ( PortBDataOut )
|
||||
);
|
||||
end
|
||||
endgenerate
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,156 @@
|
|||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 2019/07/03 13:29:31
|
||||
// Design Name:
|
||||
// Module Name: xil_tdpram
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
//`define XINLINX_FPGA
|
||||
|
||||
module xil_tdpram #(
|
||||
parameter DATAWIDTH = 32
|
||||
,parameter ADDRWIDTH = 12
|
||||
)(
|
||||
input PortClk
|
||||
,input [ADDRWIDTH-1 :0] PortAAddr
|
||||
,input [DATAWIDTH-1 :0] PortADataIn
|
||||
,input PortAWriteEnable //active low
|
||||
,input PortAChipEnable //active low
|
||||
,input [(DATAWIDTH/8)-1 :0] PortAByteWriteEnable //active low
|
||||
,output [DATAWIDTH-1 :0] PortADataOut
|
||||
|
||||
,input [ADDRWIDTH-1 :0] PortBAddr
|
||||
,input [DATAWIDTH-1 :0] PortBDataIn
|
||||
,input PortBWriteEnable //active low
|
||||
,input PortBChipEnable //active low
|
||||
,input [(DATAWIDTH/8)-1 :0] PortBByteWriteEnable //active low
|
||||
,output [DATAWIDTH-1 :0] PortBDataOut
|
||||
);
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
//Function
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
function integer clog2(input integer bit_depth);
|
||||
begin
|
||||
for(clog2=0;bit_depth>0;clog2=clog2+1)
|
||||
bit_depth =bit_depth>>1;
|
||||
end
|
||||
endfunction
|
||||
|
||||
localparam LSB = clog2(DATAWIDTH/8 -1);
|
||||
localparam MAW = ADDRWIDTH - LSB;
|
||||
localparam MB =(DATAWIDTH)*(32'h0000_0001<<MAW);
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
//XPM
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
wire [(DATAWIDTH/8)-1 :0] PortAByteWriteEnable_w = {(DATAWIDTH/8){PortAWriteEnable | PortAChipEnable}} | PortAByteWriteEnable;
|
||||
wire [(DATAWIDTH/8)-1 :0] PortBByteWriteEnable_w = {(DATAWIDTH/8){PortBWriteEnable | PortBChipEnable}} | PortBByteWriteEnable;
|
||||
xpm_memory_tdpram #(
|
||||
.CLOCKING_MODE ( "common_clock" ) // String
|
||||
,.ECC_MODE ( "no_ecc" ) // String
|
||||
,.MEMORY_INIT_FILE ( "none" ) // String
|
||||
,.MEMORY_INIT_PARAM ( "0" ) // String
|
||||
,.MEMORY_OPTIMIZATION ( "true" ) // String
|
||||
,.MEMORY_PRIMITIVE ( "auto" ) // String
|
||||
,.AUTO_SLEEP_TIME ( 0 ) // DECIMAL
|
||||
,.CASCADE_HEIGHT ( 0 ) // DECIMAL
|
||||
,.SIM_ASSERT_CHK ( 0 ) // DECIMAL; 0=disable simulation messages, 1=enable simulation messages
|
||||
,.USE_EMBEDDED_CONSTRAINT ( 0 ) // DECIMAL
|
||||
,.USE_MEM_INIT ( 1 ) // DECIMAL
|
||||
,.WAKEUP_TIME ( "disable_sleep" ) // String
|
||||
,.MESSAGE_CONTROL ( 0 ) // DECIMAL
|
||||
,.MEMORY_SIZE ( MB ) // DECIMAL
|
||||
|
||||
,.ADDR_WIDTH_A ( MAW ) // DECIMAL
|
||||
,.BYTE_WRITE_WIDTH_A ( 8 ) // DECIMAL
|
||||
,.WRITE_DATA_WIDTH_A ( DATAWIDTH ) // DECIMAL
|
||||
,.READ_DATA_WIDTH_A ( DATAWIDTH ) // DECIMAL
|
||||
,.READ_LATENCY_A ( 1 ) // DECIMAL
|
||||
,.READ_RESET_VALUE_A ( "0" ) // String
|
||||
,.RST_MODE_A ( "SYNC" ) // String
|
||||
,.WRITE_MODE_A ( "no_change" ) // String
|
||||
|
||||
,.ADDR_WIDTH_B ( MAW ) // DECIMAL
|
||||
,.BYTE_WRITE_WIDTH_B ( 8 ) // DECIMAL
|
||||
,.WRITE_DATA_WIDTH_B ( DATAWIDTH ) // DECIMAL
|
||||
,.READ_DATA_WIDTH_B ( DATAWIDTH ) // DECIMAL
|
||||
,.READ_LATENCY_B ( 1 ) // DECIMAL
|
||||
,.READ_RESET_VALUE_B ( "0" ) // String
|
||||
,.RST_MODE_B ( "SYNC" ) // String
|
||||
,.WRITE_MODE_B ( "no_change" ) // String
|
||||
) xpm_memory_tdpram_inst (
|
||||
|
||||
.rsta ( 0 ) // 1-bit input: Reset signal for the final port A output register stage.
|
||||
// Synchronously resets output port douta to the value specified by
|
||||
// parameter READ_RESET_VALUE_A.
|
||||
,.clka ( PortClk ) // 1-bit input: Clock signal for port A. Also clocks port B when
|
||||
// parameter CLOCKING_MODE is "common_clock".
|
||||
,.regcea ( 0 ) // 1-bit input: Clock Enable for the last register stage on the output
|
||||
// data path.
|
||||
,.ena ( 1'b1 ) // 1-bit input: Memory enable signal for port A. Must be high on clock
|
||||
// cycles when read or write operations are initiated. Pipelined
|
||||
// internally.
|
||||
,.wea ( ~PortAByteWriteEnable_w ) // WRITE_DATA_WIDTH_A/BYTE_WRITE_WIDTH_A-bit input: Write enable vector
|
||||
// for port A input data port dina. 1 bit wide when word-wide writes are
|
||||
// used. In byte-wide write configurations, each bit controls the
|
||||
// writing one byte of dina to address addra. For example, to
|
||||
// synchronously write only bits [15-8] of dina when WRITE_DATA_WIDTH_A
|
||||
// is 32, wea would be 4'b0010.
|
||||
,.addra ( PortAAddr[ADDRWIDTH-1 : LSB] ) // ADDR_WIDTH_A-bit input: Address for port A write and read operations.
|
||||
,.dina ( PortADataIn ) // WRITE_DATA_WIDTH_A-bit input: Data input for port A write operations.
|
||||
,.douta ( PortADataOut ) // READ_DATA_WIDTH_A-bit output: Data output for port A read operations.
|
||||
,.dbiterra ( ) // 1-bit output: Status signal to indicate double bit error occurrence
|
||||
// on the data output of port A.
|
||||
,.sbiterra ( ) // 1-bit output: Status signal to indicate single bit error occurrence
|
||||
// on the data output of port A.
|
||||
,.injectdbiterra ( 1'b0 ) // 1-bit input: Controls double bit error injection on input data when
|
||||
// ECC enabled (Error injection capability is not available in
|
||||
// "decode_only" mode).
|
||||
,.injectsbiterra ( 1'b0 ) // 1-bit input: Controls single bit error injection on input data when
|
||||
// ECC enabled (Error injection capability is not available in
|
||||
// "decode_only" mode).
|
||||
|
||||
,.rstb ( 0 ) // 1-bit input: Reset signal for the final port B output register stage.
|
||||
// Synchronously resets output port douta to the value specified by
|
||||
// parameter READ_RESET_VALUE_B.
|
||||
,.clkb ( PortClk ) // 1-bit input: Clock signal for port B. Also clocks port A when
|
||||
// parameter CLOCKING_MODE is "common_clock".
|
||||
,.regceb ( 0 ) // 1-bit input: Clock Enable for the last register stage on the output
|
||||
// data path.
|
||||
,.enb ( 1'b1 ) // 1-bit input: Memory enable signal for port B. Must be high on clock
|
||||
// cycles when read or write operations are initiated. Pipelined
|
||||
// internally.
|
||||
,.web ( ~PortBByteWriteEnable_w ) // WRITE_DATA_WIDTH_B/BYTE_WRITE_WIDTH_B-bit input: Write enable vector
|
||||
// for port B input data port dina. 1 bit wide when word-wide writes are
|
||||
// used. In byte-wide write configurations, each bit controls the
|
||||
// writing one byte of dinb to address addrb. For example, to
|
||||
// synchronously write only bits [15-8] of dina when WRITE_DATA_WIDTH_B
|
||||
// is 32, wea would be 4'b0010.
|
||||
,.addrb ( PortBAddr[ADDRWIDTH-1 : LSB] ) // ADDR_WIDTH_B-bit input: Address for port B write and read operations.
|
||||
,.dinb ( PortBDataIn ) // WRITE_DATA_WIDTH_A-bit input: Data input for port B write operations.
|
||||
,.doutb ( PortBDataOut ) // READ_DATA_WIDTH_A-bit output: Data output for port B read operations.
|
||||
,.dbiterrb ( ) // 1-bit output: Status signal to indicate double bit error occurrence
|
||||
// on the data output of port B.
|
||||
,.sbiterrb ( ) // 1-bit output: Status signal to indicate single bit error occurrence
|
||||
// on the data output of port B.
|
||||
,.injectdbiterrb ( 1'b0 ) // 1-bit input: Controls double bit error injection on input data when
|
||||
// ECC enabled (Error injection capability is not available in
|
||||
// "decode_only" mode).
|
||||
,.injectsbiterrb ( 1'b0 ) // 1-bit input: Controls single bit error injection on input data when
|
||||
// ECC enabled (Error injection capability is not available in
|
||||
// "decode_only" mode).
|
||||
,.sleep ( 1'b0 ) // 1-bit input: sleep signal to enable the dynamic power saving feature.
|
||||
);
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,146 @@
|
|||
// Relese History
|
||||
// Version Date Author Description
|
||||
// 1.2 2024-06-01 ZYZ
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Keywords : 1.add Env_vld
|
||||
// 2.add Mod_vld
|
||||
// 3.change the use of Mod_enable
|
||||
// 4.divide modem into FM and AM
|
||||
// 5.change amp : unsigned [16:0]Amp to signed [15:0]Amp
|
||||
//
|
||||
//
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Parameter
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Purpose :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Target Device:
|
||||
// Tool versions:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Reuse Issues
|
||||
// Reset Strategy:
|
||||
// Clock Domains:
|
||||
// Critical Timing:
|
||||
// Asynchronous I/F:
|
||||
// Synthesizable (y/n):
|
||||
// Other:
|
||||
//-FHDR--------------------------------------------------------------------------------------------------------
|
||||
module ampmod (
|
||||
//System Signal
|
||||
input Dig_Clk //Module Clock
|
||||
,input Dig_Resetn //Module Reset Signal
|
||||
//FM Data_in
|
||||
,input [15:0] Mod_Data_I //FM_data_I
|
||||
,input [15:0] Mod_Data_Q //FM_data_Q
|
||||
,input Mod_Vld //FM_data is valid
|
||||
//AM
|
||||
,input [15:0] Amp //amplitude
|
||||
,input Amod_Enable //1'b0: disable modem,1'b1:enable modem
|
||||
//Output modem data
|
||||
,output [15:0] Amod_Data_I //Modem output data for I
|
||||
,output [15:0] Amod_Data_Q //Modem output data for Q
|
||||
,output Amod_Vld //Modem output data vld
|
||||
);
|
||||
//FM_data
|
||||
wire [15:0] Mod_Data_I_w;
|
||||
wire [15:0] Mod_Data_Q_w;
|
||||
|
||||
//The temporary result Regs of a multiplication operation.
|
||||
wire [31:0] I_Amp_tmp;
|
||||
wire [31:0] Q_Amp_tmp;
|
||||
|
||||
//Output of IQ data stored in registers.
|
||||
reg [15:0] I_Amp_tmp_r;
|
||||
reg [15:0] Q_Amp_tmp_r;
|
||||
|
||||
//AM_vld delay
|
||||
reg [2:0] ampmod_data_vld_dly;
|
||||
|
||||
|
||||
assign Mod_Data_I_w = Amod_Enable ? Mod_Data_I : 16'b0;
|
||||
assign Mod_Data_Q_w = Amod_Enable ? Mod_Data_Q : 16'b0;
|
||||
|
||||
////////////////////////////////////
|
||||
DW_mult_pipe #(
|
||||
.a_width ( 16 )
|
||||
,.b_width ( 16 )
|
||||
,.num_stages ( 3 )
|
||||
,.stall_mode ( 0 )
|
||||
,.rst_mode ( 1 )
|
||||
,.op_iso_mode ( 0 )
|
||||
) inst_I_Amp (
|
||||
.clk ( Dig_Clk )
|
||||
,.rst_n ( Dig_Resetn )
|
||||
,.en ( 1'b1 )
|
||||
,.a ( Mod_Data_I_w )
|
||||
,.b ( Amp )
|
||||
,.tc ( 1'b1 )
|
||||
,.product ( I_Amp_tmp )
|
||||
);
|
||||
|
||||
DW_mult_pipe #(
|
||||
.a_width ( 16 )
|
||||
,.b_width ( 16 )
|
||||
,.num_stages ( 3 )
|
||||
,.stall_mode ( 0 )
|
||||
,.rst_mode ( 1 )
|
||||
,.op_iso_mode ( 0 )
|
||||
) inst_Q_Amp (
|
||||
.clk ( Dig_Clk )
|
||||
,.rst_n ( Dig_Resetn )
|
||||
,.en ( 1'b1 )
|
||||
,.a ( Mod_Data_Q_w )
|
||||
,.b ( Amp )
|
||||
,.tc ( 1'b1 )
|
||||
,.product ( Q_Amp_tmp )
|
||||
);
|
||||
|
||||
always@(posedge Dig_Clk or negedge Dig_Resetn)begin
|
||||
if(Dig_Resetn == 1'b0) begin
|
||||
I_Amp_tmp_r <= 16'b0;
|
||||
end
|
||||
else if (I_Amp_tmp[31:30] == 2'b01)begin
|
||||
I_Amp_tmp_r <= 16'd32767;
|
||||
end
|
||||
else if(I_Amp_tmp[31:30] == 2'b10)begin
|
||||
I_Amp_tmp_r <= -16'd32768;
|
||||
end
|
||||
else begin
|
||||
I_Amp_tmp_r <= {I_Amp_tmp[31],I_Amp_tmp[29:15]} + I_Amp_tmp[14];
|
||||
end
|
||||
end
|
||||
|
||||
always@(posedge Dig_Clk or negedge Dig_Resetn)begin
|
||||
if(Dig_Resetn == 1'b0) begin
|
||||
Q_Amp_tmp_r <= 16'd0;
|
||||
end
|
||||
else if (Q_Amp_tmp[31:30] == 2'b01)begin
|
||||
Q_Amp_tmp_r <= 16'd32767;
|
||||
end
|
||||
else if(I_Amp_tmp[31:30] == 2'b10)begin
|
||||
Q_Amp_tmp_r <= -16'd32768;
|
||||
end
|
||||
else begin
|
||||
Q_Amp_tmp_r <= {Q_Amp_tmp[31],Q_Amp_tmp[29:15]} + Q_Amp_tmp[14];
|
||||
end
|
||||
end
|
||||
|
||||
assign Amod_Data_I = I_Amp_tmp_r;
|
||||
assign Amod_Data_Q = Q_Amp_tmp_r;
|
||||
|
||||
//ampmod_data_vld_dly
|
||||
always @(posedge Dig_Clk or negedge Dig_Resetn) begin
|
||||
if(Dig_Resetn == 1'b0) begin
|
||||
ampmod_data_vld_dly <= 3'b0;
|
||||
end
|
||||
else begin
|
||||
ampmod_data_vld_dly <= {ampmod_data_vld_dly[2:0], Amod_Enable & Mod_Vld};
|
||||
end
|
||||
end
|
||||
|
||||
assign Amod_Vld = ampmod_data_vld_dly[2];
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,67 @@
|
|||
//+FHDR--------------------------------------------------------------------------------------------------------
|
||||
// Company:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// File Name : v.v
|
||||
// Department :
|
||||
// Author : PWY
|
||||
// Author's Tel :
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Relese History
|
||||
// Version Date Author Description
|
||||
// 0.1 2024-03-13 PWY AWG output data bais set
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Keywords :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Parameter
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Purpose :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Target Device:
|
||||
// Tool versions:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Reuse Issues
|
||||
// Reset Strategy:
|
||||
// Clock Domains:
|
||||
// Critical Timing:
|
||||
// Asynchronous I/F:
|
||||
// Synthesizable (y/n):
|
||||
// Other:
|
||||
//-FHDR--------------------------------------------------------------------------------------------------------
|
||||
|
||||
module baisset (
|
||||
//System Signal
|
||||
input Dig_Clk //Module Clock
|
||||
,input Dig_Resetn //Module Reset Signal
|
||||
//FM Data_in
|
||||
,input [15:0] Bais_Data_I_i //Bais_data_I
|
||||
,input [15:0] Bais_Data_Q_i //Bais_data_Q
|
||||
,input Bais_Vld_i //Bais_data is valid
|
||||
//AM
|
||||
,input [15:0] Bais //Bais
|
||||
,input Bais_Enable //1'b0: disable Bais,1'b1:enable Bais
|
||||
//Output Bais data
|
||||
,output [15:0] Bais_Data_I_o //Bais output data for I
|
||||
,output [15:0] Bais_Data_Q_o //Bais output data for Q
|
||||
,output Bais_Vld_o //Bais output data vld
|
||||
,output Bais_I_Ov
|
||||
,output Bais_Q_Ov
|
||||
);
|
||||
|
||||
wire [17:0] temp_data_i = Bais_Enable ? {{2{Bais_Data_I_i[15]}},Bais_Data_I_i} + {{2{Bais[15]}},Bais} : {{2{Bais_Data_I_i[15]}},Bais_Data_I_i};
|
||||
wire [17:0] temp_data_q = Bais_Enable ? {{2{Bais_Data_Q_i[15]}},Bais_Data_Q_i} + {{2{Bais[15]}},Bais} : {{2{Bais_Data_Q_i[15]}},Bais_Data_Q_i};
|
||||
|
||||
//output data
|
||||
sirv_gnrl_dffr #(16) Bais_Data_I_o_dffr (temp_data_i[15:0], Bais_Data_I_o, Dig_Clk, Dig_Resetn);
|
||||
sirv_gnrl_dffr #(16) Bais_Data_Q_o_dffr (temp_data_q[15:0], Bais_Data_Q_o, Dig_Clk, Dig_Resetn);
|
||||
|
||||
//output vld
|
||||
sirv_gnrl_dffr #(1) Bais_Vld_o_dffr (Bais_Vld_i, Bais_Vld_o, Dig_Clk, Dig_Resetn);
|
||||
|
||||
//output overflow flag
|
||||
sirv_gnrl_dfflr #(1) Bais_I_Ov_dfflr (Bais_Vld_i, temp_data_i[17] ^ temp_data_i[16], Bais_I_Ov, Dig_Clk, Dig_Resetn);
|
||||
sirv_gnrl_dfflr #(1) Bais_Q_Ov_dfflr (Bais_Vld_i, temp_data_q[17] ^ temp_data_q[16], Bais_Q_Ov, Dig_Clk, Dig_Resetn);
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,336 @@
|
|||
// Relese History
|
||||
// Version Date Author Description
|
||||
// 1.1 2024-04-08 ZYZ
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Keywords : 1.add Env_vld
|
||||
// 2.add Mod_vld
|
||||
// 3.change the use of Mod_enable
|
||||
// 4.divide modem into FM and AM
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Parameter
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Purpose :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Target Device:
|
||||
// Tool versions:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Reuse Issues
|
||||
// Reset Strategy:
|
||||
// Clock Domains:
|
||||
// Critical Timing:
|
||||
// Asynchronous I/F:
|
||||
// Synthesizable (y/n):
|
||||
// Other:
|
||||
//-FHDR--------------------------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
module freqmod (
|
||||
//System Signal
|
||||
input Dig_Clk //Module Clock
|
||||
,input Dig_Resetn //Module Reset Signal
|
||||
//Envelope Data
|
||||
,input signed [15:0] Env_Idata //env_i is signed (two's complement)
|
||||
,input signed [15:0] Env_Qdata //env_q is signed (two's complement)
|
||||
,input Env_Vld //env data is vld
|
||||
//Nco data
|
||||
,input signed [15:0] Nco_Sin //nco_sin is signed (two's complement)
|
||||
,input signed [15:0] Nco_Cos //nco_cos is signed (two's complement)
|
||||
//Config Signal
|
||||
,input Mod_Sideband_Sel //1'b0: Mod_data_i = Icoswd+Qsinwd, Mod_data_q = -Isinwd+Qcoswd
|
||||
//1'b1: Mod_data_i = Icoswd-Qsinwd, Mod_data_q = Isinwd+Qcoswd
|
||||
,input Mod_Enable //1'b0: disable Modem,1'b1:enable modem
|
||||
//Output modem data
|
||||
,output signed [15:0] Mod_Data_I //Modem output data for I
|
||||
,output signed [15:0] Mod_Data_Q //Modem output data for Q
|
||||
,output Mod_Vld //Modem output data vld
|
||||
);
|
||||
|
||||
//////////////////////////////////////////////////////////////
|
||||
// Wire & reg
|
||||
//////////////////////////////////////////////////////////////
|
||||
//The temporary result Regs of a multiplication operation.
|
||||
wire signed [31:0] mult_isin_tmp;
|
||||
wire signed [31:0] mult_icos_tmp;
|
||||
wire signed [31:0] mult_qsin_tmp;
|
||||
wire signed [31:0] mult_qcos_tmp;
|
||||
|
||||
//The processing of a multiplication result.
|
||||
wire signed [15:0] mult_isin_w;
|
||||
wire signed [15:0] mult_icos_w;
|
||||
wire signed [15:0] mult_qsin_w;
|
||||
wire signed [15:0] mult_qcos_w;
|
||||
|
||||
//The multiplier processing result register.
|
||||
reg signed [15:0] mult_isin_r;
|
||||
reg signed [15:0] mult_icos_r;
|
||||
reg signed [15:0] mult_qsin_r;
|
||||
reg signed [15:0] mult_qcos_r;
|
||||
|
||||
//Temporary storage of IQ data.
|
||||
wire signed [16:0] adder0_icosqsin_tmp;
|
||||
wire signed [16:0] adder1_isinqcos_tmp;
|
||||
|
||||
//Output of IQ data stored in registers.
|
||||
reg signed [15:0] adder0_icosqsin_r;
|
||||
reg signed [15:0] adder1_isinqcos_r;
|
||||
|
||||
|
||||
//Modulation data valid flag Regs.
|
||||
reg [7 :0] freqmod_data_vld_dly;
|
||||
|
||||
//shifting register,Env_Idata
|
||||
reg signed [15:0] Env_Idata_r1;
|
||||
reg signed [15:0] Env_Idata_r2;
|
||||
reg signed [15:0] Env_Idata_r3;
|
||||
reg signed [15:0] Env_Idata_r4;
|
||||
|
||||
|
||||
always @(posedge Dig_Clk or negedge Dig_Resetn) begin
|
||||
if(!Dig_Resetn)
|
||||
begin
|
||||
Env_Idata_r1 <= 16'b0;
|
||||
Env_Idata_r2 <= 16'b0;
|
||||
Env_Idata_r3 <= 16'b0;
|
||||
Env_Idata_r4 <= 16'b0;
|
||||
end
|
||||
else if(~Mod_Enable)
|
||||
begin
|
||||
Env_Idata_r1 <= 16'b0;
|
||||
Env_Idata_r2 <= Env_Idata_r1;
|
||||
Env_Idata_r3 <= Env_Idata_r2;
|
||||
Env_Idata_r4 <= Env_Idata_r3;
|
||||
end
|
||||
else begin
|
||||
Env_Idata_r1 <= Env_Idata;
|
||||
Env_Idata_r2 <= Env_Idata_r1;
|
||||
Env_Idata_r3 <= Env_Idata_r2;
|
||||
Env_Idata_r4 <= Env_Idata_r3;
|
||||
end
|
||||
end
|
||||
|
||||
//shifting register,Env_Qdata
|
||||
reg signed [15:0] Env_Qdata_r1;
|
||||
reg signed [15:0] Env_Qdata_r2;
|
||||
reg signed [15:0] Env_Qdata_r3;
|
||||
reg signed [15:0] Env_Qdata_r4;
|
||||
|
||||
always @(posedge Dig_Clk or negedge Dig_Resetn) begin
|
||||
if(!Dig_Resetn)
|
||||
begin
|
||||
Env_Qdata_r1 <= 16'b0;
|
||||
Env_Qdata_r2 <= 16'b0;
|
||||
Env_Qdata_r3 <= 16'b0;
|
||||
Env_Qdata_r4 <= 16'b0;
|
||||
|
||||
end
|
||||
else if(~Mod_Enable)
|
||||
begin
|
||||
Env_Qdata_r1 <= 16'b0;
|
||||
Env_Qdata_r2 <= Env_Qdata_r1;
|
||||
Env_Qdata_r3 <= Env_Qdata_r2;
|
||||
Env_Qdata_r4 <= Env_Qdata_r3;
|
||||
end
|
||||
else begin
|
||||
Env_Qdata_r1 <= Env_Qdata;
|
||||
Env_Qdata_r2 <= Env_Qdata_r1;
|
||||
Env_Qdata_r3 <= Env_Qdata_r2;
|
||||
Env_Qdata_r4 <= Env_Qdata_r3;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
//////////////////////////////////////////////////////////////
|
||||
// Orthogonal modulation
|
||||
//////////////////////////////////////////////////////////////
|
||||
//DW_mult_pipe Instantiation -> Env_Idata * Nco_Sin
|
||||
DW_mult_pipe #(
|
||||
.a_width ( 16 )
|
||||
,.b_width ( 16 )
|
||||
,.num_stages ( 3 )
|
||||
,.stall_mode ( 0 )
|
||||
,.rst_mode ( 1 )
|
||||
,.op_iso_mode ( 0 )
|
||||
) inst_isin_mult (
|
||||
.clk ( Dig_Clk )
|
||||
,.rst_n ( Dig_Resetn )
|
||||
,.en ( 1'b1 )
|
||||
,.a ( Env_Idata_r4 )
|
||||
,.b ( Nco_Sin )
|
||||
,.tc ( 1'b1 )
|
||||
,.product ( mult_isin_tmp )
|
||||
);
|
||||
|
||||
|
||||
//DW_mult_pipe Instantiation -> Env_Idata * Nco_Cos
|
||||
DW_mult_pipe #(
|
||||
.a_width ( 16 )
|
||||
,.b_width ( 16 )
|
||||
,.num_stages ( 3 )
|
||||
,.stall_mode ( 0 )
|
||||
,.rst_mode ( 1 )
|
||||
,.op_iso_mode ( 0 )
|
||||
) inst_icos_mult (
|
||||
.clk ( Dig_Clk )
|
||||
,.rst_n ( Dig_Resetn )
|
||||
,.en ( 1'b1 )
|
||||
,.a ( Env_Idata_r4 )
|
||||
,.b ( Nco_Cos )
|
||||
,.tc ( 1'b1 )
|
||||
,.product ( mult_icos_tmp )
|
||||
);
|
||||
|
||||
//DW_mult_pipe Instantiation -> Env_Qdata * Nco_Sin
|
||||
DW_mult_pipe #(
|
||||
.a_width ( 16 )
|
||||
,.b_width ( 16 )
|
||||
,.num_stages ( 3 )
|
||||
,.stall_mode ( 0 )
|
||||
,.rst_mode ( 1 )
|
||||
,.op_iso_mode ( 0 )
|
||||
) inst_qsin_mult (
|
||||
.clk ( Dig_Clk )
|
||||
,.rst_n ( Dig_Resetn )
|
||||
,.en ( 1'b1 )
|
||||
,.a ( Env_Qdata_r4 )
|
||||
,.b ( Nco_Sin )
|
||||
,.tc ( 1'b1 )
|
||||
,.product ( mult_qsin_tmp )
|
||||
);
|
||||
|
||||
//DW_mult_pipe Instantiation -> Env_Qdata * Nco_Cos
|
||||
DW_mult_pipe #(
|
||||
.a_width ( 16 )
|
||||
,.b_width ( 16 )
|
||||
,.num_stages ( 3 )
|
||||
,.stall_mode ( 0 )
|
||||
,.rst_mode ( 1 )
|
||||
,.op_iso_mode ( 0 )
|
||||
) inst_qcos_mult (
|
||||
.clk ( Dig_Clk )
|
||||
,.rst_n ( Dig_Resetn )
|
||||
,.en ( 1'b1 )
|
||||
,.a ( Env_Qdata_r4 )
|
||||
,.b ( Nco_Cos )
|
||||
,.tc ( 1'b1 )
|
||||
,.product ( mult_qcos_tmp )
|
||||
);
|
||||
|
||||
//////////////////////////////////////////////////////////////
|
||||
// The processing of a multiplication result.
|
||||
//////////////////////////////////////////////////////////////
|
||||
assign mult_isin_w = {mult_isin_tmp[31],mult_isin_tmp[29:15]} +mult_isin_tmp[14];
|
||||
assign mult_icos_w = {mult_icos_tmp[31],mult_icos_tmp[29:15]} +mult_icos_tmp[14];
|
||||
assign mult_qsin_w = {mult_qsin_tmp[31],mult_qsin_tmp[29:15]} +mult_qsin_tmp[14];
|
||||
assign mult_qcos_w = {mult_qcos_tmp[31],mult_qcos_tmp[29:15]} +mult_qcos_tmp[14];
|
||||
//////////////////////////////////////////////////////////////
|
||||
// The multiplier processing result register.
|
||||
//////////////////////////////////////////////////////////////
|
||||
//mult_isin_r
|
||||
always @(posedge Dig_Clk or negedge Dig_Resetn) begin
|
||||
if(Dig_Resetn == 1'b0) begin
|
||||
mult_isin_r <= 16'd0;
|
||||
end
|
||||
else begin
|
||||
mult_isin_r <= mult_isin_w;
|
||||
end
|
||||
end
|
||||
|
||||
//mult_icos_r
|
||||
always @(posedge Dig_Clk or negedge Dig_Resetn) begin
|
||||
if(Dig_Resetn == 1'b0) begin
|
||||
mult_icos_r <= 16'd0;
|
||||
end
|
||||
else begin
|
||||
mult_icos_r <= mult_icos_w;
|
||||
end
|
||||
end
|
||||
|
||||
//mult_qsin_r
|
||||
always @(posedge Dig_Clk or negedge Dig_Resetn) begin
|
||||
if(Dig_Resetn == 1'b0) begin
|
||||
mult_qsin_r <= 16'd0;
|
||||
end
|
||||
else begin
|
||||
mult_qsin_r <= mult_qsin_w;
|
||||
end
|
||||
end
|
||||
|
||||
//mult_qcos_r
|
||||
always @(posedge Dig_Clk or negedge Dig_Resetn) begin
|
||||
if(Dig_Resetn == 1'b0) begin
|
||||
mult_qcos_r <= 16'd0;
|
||||
end
|
||||
else begin
|
||||
mult_qcos_r <= mult_qcos_w;
|
||||
end
|
||||
end
|
||||
|
||||
//////////////////////////////////////////////////////////////
|
||||
// Orthogonal modulation
|
||||
//////////////////////////////////////////////////////////////
|
||||
|
||||
assign adder0_icosqsin_tmp = ~Mod_Sideband_Sel ? (mult_icos_r + mult_qsin_r):(mult_icos_r - mult_qsin_r);
|
||||
//1'b0: adder0_icosqsin_tmp = Icoswd+Qsinwd, 1'b1:adder0_icosqsin_tmp = Icoswd-Qsinwd
|
||||
|
||||
assign adder1_isinqcos_tmp = Mod_Sideband_Sel ? (mult_isin_r + mult_qcos_r):(-mult_isin_r + mult_qcos_r);
|
||||
//1'b0: adder1_isinqcos_tmp = Isinwd+Qcoswd, 1'b1:adder1_isinqcos_tmp = -Isinwd+Qcoswd
|
||||
|
||||
//////////////////////////////////////////////////////////////
|
||||
// Output of IQ data stored in registers.
|
||||
//////////////////////////////////////////////////////////////
|
||||
|
||||
always @(posedge Dig_Clk or negedge Dig_Resetn) begin
|
||||
if(Dig_Resetn == 1'b0) begin
|
||||
adder0_icosqsin_r <= 16'd0;
|
||||
end
|
||||
else if(adder0_icosqsin_tmp[16:15] == 2'b01)begin
|
||||
adder0_icosqsin_r <= 32767;
|
||||
end
|
||||
else if (adder0_icosqsin_tmp[16:15] == 2'b10)begin
|
||||
adder0_icosqsin_r <= -32768;
|
||||
end
|
||||
else begin
|
||||
adder0_icosqsin_r <= {adder0_icosqsin_tmp[16],adder0_icosqsin_tmp[14:0]};
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge Dig_Clk or negedge Dig_Resetn) begin
|
||||
if(Dig_Resetn == 1'b0) begin
|
||||
adder1_isinqcos_r <= 16'd0;
|
||||
end
|
||||
else if (adder1_isinqcos_tmp[16:15] == 2'b01)begin
|
||||
adder1_isinqcos_r <= 32767;
|
||||
end
|
||||
else if (adder1_isinqcos_tmp[16:15] == 2'b10)begin
|
||||
adder1_isinqcos_r <= -32768;
|
||||
end
|
||||
else begin
|
||||
adder1_isinqcos_r <= {adder1_isinqcos_tmp[16],adder1_isinqcos_tmp[14:0]};
|
||||
end
|
||||
end
|
||||
|
||||
assign Mod_Data_I = adder0_icosqsin_r;
|
||||
assign Mod_Data_Q = adder1_isinqcos_r;
|
||||
//////////////////////////////////////////////////////////////
|
||||
// Generation of Mod_Vld signal.
|
||||
//////////////////////////////////////////////////////////////
|
||||
//mod_data_vld_dly
|
||||
always @(posedge Dig_Clk or negedge Dig_Resetn) begin
|
||||
if(Dig_Resetn == 1'b0) begin
|
||||
freqmod_data_vld_dly <= 8'b0;
|
||||
end
|
||||
else begin
|
||||
freqmod_data_vld_dly <= {freqmod_data_vld_dly[6:0], Mod_Enable & Env_Vld};
|
||||
end
|
||||
end
|
||||
|
||||
assign Mod_Vld = freqmod_data_vld_dly[7];
|
||||
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,150 @@
|
|||
module COEF_C(
|
||||
index ,
|
||||
C0_C ,
|
||||
C1_C ,
|
||||
C2_C
|
||||
);
|
||||
input [4:0] index;
|
||||
|
||||
output [17:0] C0_C;
|
||||
output [11:0] C1_C;
|
||||
output [5:0] C2_C;
|
||||
|
||||
reg [17:0] C0_C;
|
||||
reg [11:0] C1_C;
|
||||
reg [5:0] C2_C;
|
||||
|
||||
|
||||
|
||||
//------------------------
|
||||
//----C0_C OK
|
||||
always@(*)
|
||||
begin
|
||||
|
||||
case(index)
|
||||
5'd 0 : C0_C =18'h3ffff;
|
||||
5'd 1 : C0_C =18'h3ffb1;
|
||||
5'd 2 : C0_C =18'h3fec4;
|
||||
5'd 3 : C0_C =18'h3fd3a;
|
||||
5'd 4 : C0_C =18'h3fb12;
|
||||
5'd 5 : C0_C =18'h3f84d;
|
||||
5'd 6 : C0_C =18'h3f4eb;
|
||||
5'd 7 : C0_C =18'h3f0ed;
|
||||
5'd 8 : C0_C =18'h3ec53;
|
||||
5'd 9 : C0_C =18'h3e71e;
|
||||
5'd10 : C0_C =18'h3e150;
|
||||
5'd11 : C0_C =18'h3dae8;
|
||||
5'd12 : C0_C =18'h3d3e8;
|
||||
5'd13 : C0_C =18'h3cc51;
|
||||
5'd14 : C0_C =18'h3c424;
|
||||
5'd15 : C0_C =18'h3bb62;
|
||||
5'd16 : C0_C =18'h3b20d;
|
||||
5'd17 : C0_C =18'h3a827;
|
||||
5'd18 : C0_C =18'h39daf;
|
||||
5'd19 : C0_C =18'h392a9;
|
||||
5'd20 : C0_C =18'h38716;
|
||||
5'd21 : C0_C =18'h37af8;
|
||||
5'd22 : C0_C =18'h36e50;
|
||||
5'd23 : C0_C =18'h36121;
|
||||
5'd24 : C0_C =18'h3536d;
|
||||
5'd25 : C0_C =18'h34535;
|
||||
5'd26 : C0_C =18'h3367c;
|
||||
5'd27 : C0_C =18'h32744;
|
||||
5'd28 : C0_C =18'h31790;
|
||||
5'd29 : C0_C =18'h30762;
|
||||
5'd30 : C0_C =18'h2f6bc;
|
||||
5'd31 : C0_C =18'h2e5a1;
|
||||
// default : C0_C = C0_C;
|
||||
endcase
|
||||
|
||||
end
|
||||
|
||||
//------------------------
|
||||
//----C1_C OK
|
||||
always@(*)
|
||||
begin
|
||||
|
||||
case(index)
|
||||
5'd 0 : C1_C =12'd 0;
|
||||
5'd 1 : C1_C =12'd 79;
|
||||
5'd 2 : C1_C =12'd 158;
|
||||
5'd 3 : C1_C =12'd 237;
|
||||
5'd 4 : C1_C =12'd 315;
|
||||
5'd 5 : C1_C =12'd 394;
|
||||
5'd 6 : C1_C =12'd 472;
|
||||
5'd 7 : C1_C =12'd 550;
|
||||
5'd 8 : C1_C =12'd 628;
|
||||
5'd 9 : C1_C =12'd 705;
|
||||
5'd10 : C1_C =12'd 782;
|
||||
5'd11 : C1_C =12'd 858;
|
||||
5'd12 : C1_C =12'd 934;
|
||||
5'd13 : C1_C =12'd1009;
|
||||
5'd14 : C1_C =12'd1084;
|
||||
5'd15 : C1_C =12'd1158;
|
||||
5'd16 : C1_C =12'd1231;
|
||||
5'd17 : C1_C =12'd1304;
|
||||
5'd18 : C1_C =12'd1376;
|
||||
5'd19 : C1_C =12'd1446;
|
||||
5'd20 : C1_C =12'd1517;
|
||||
5'd21 : C1_C =12'd1586;
|
||||
5'd22 : C1_C =12'd1654;
|
||||
5'd23 : C1_C =12'd1721;
|
||||
5'd24 : C1_C =12'd1787;
|
||||
5'd25 : C1_C =12'd1852;
|
||||
5'd26 : C1_C =12'd1916;
|
||||
5'd27 : C1_C =12'd1979;
|
||||
5'd28 : C1_C =12'd2041;
|
||||
5'd29 : C1_C =12'd2101;
|
||||
5'd30 : C1_C =12'd2161;
|
||||
5'd31 : C1_C =12'd2218;
|
||||
// default : C1_C = C1_C;
|
||||
endcase
|
||||
|
||||
end
|
||||
//------------------------
|
||||
//----C2_C
|
||||
always@(*)
|
||||
begin
|
||||
|
||||
|
||||
case(index)
|
||||
5'd 0 : C2_C =6'd39;
|
||||
5'd 1 : C2_C =6'd39;
|
||||
5'd 2 : C2_C =6'd39;
|
||||
5'd 3 : C2_C =6'd39;
|
||||
5'd 4 : C2_C =6'd39;
|
||||
5'd 5 : C2_C =6'd39;
|
||||
5'd 6 : C2_C =6'd39;
|
||||
5'd 7 : C2_C =6'd39;
|
||||
5'd 8 : C2_C =6'd39;
|
||||
5'd 9 : C2_C =6'd38;
|
||||
5'd10 : C2_C =6'd38;
|
||||
5'd11 : C2_C =6'd38;
|
||||
5'd12 : C2_C =6'd38;
|
||||
5'd13 : C2_C =6'd37;
|
||||
5'd14 : C2_C =6'd37;
|
||||
5'd15 : C2_C =6'd37;
|
||||
5'd16 : C2_C =6'd36;
|
||||
5'd17 : C2_C =6'd36;
|
||||
5'd18 : C2_C =6'd35;
|
||||
5'd19 : C2_C =6'd35;
|
||||
5'd20 : C2_C =6'd35;
|
||||
5'd21 : C2_C =6'd34;
|
||||
5'd22 : C2_C =6'd34;
|
||||
5'd23 : C2_C =6'd33;
|
||||
5'd24 : C2_C =6'd33;
|
||||
5'd25 : C2_C =6'd32;
|
||||
5'd26 : C2_C =6'd31;
|
||||
5'd27 : C2_C =6'd31;
|
||||
5'd28 : C2_C =6'd30;
|
||||
5'd29 : C2_C =6'd30;
|
||||
5'd30 : C2_C =6'd29;
|
||||
5'd31 : C2_C =6'd28;
|
||||
// default : C2_C = C2_C;
|
||||
endcase
|
||||
|
||||
|
||||
end
|
||||
endmodule
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,155 @@
|
|||
module COEF_S(
|
||||
|
||||
index ,
|
||||
C0_S ,
|
||||
C1_S ,
|
||||
C2_S
|
||||
|
||||
);
|
||||
|
||||
input [4:0] index;
|
||||
|
||||
output [17:0] C0_S;
|
||||
output [11:0] C1_S;
|
||||
output [4:0] C2_S;
|
||||
|
||||
|
||||
reg [17:0] C0_S;
|
||||
reg [11:0] C1_S;
|
||||
reg [4:0] C2_S;
|
||||
|
||||
//------------------------
|
||||
//----C0_S
|
||||
always@(*)
|
||||
begin
|
||||
|
||||
case(index)
|
||||
5'd 0 : C0_S =18'd 0;
|
||||
5'd 1 : C0_S =18'd 6433;
|
||||
5'd 2 : C0_S =18'd 12863;
|
||||
5'd 3 : C0_S =18'd 19284;
|
||||
5'd 4 : C0_S =18'd 25695;
|
||||
5'd 5 : C0_S =18'd 32089;
|
||||
5'd 6 : C0_S =18'd 38464;
|
||||
5'd 7 : C0_S =18'd 44817;
|
||||
5'd 8 : C0_S =18'd 51142;
|
||||
5'd 9 : C0_S =18'd 57436;
|
||||
5'd10 : C0_S =18'd 63696;
|
||||
5'd11 : C0_S =18'd 69917;
|
||||
5'd12 : C0_S =18'd 76096;
|
||||
5'd13 : C0_S =18'd 82230;
|
||||
5'd14 : C0_S =18'd 88314;
|
||||
5'd15 : C0_S =18'd 94344;
|
||||
5'd16 : C0_S =18'd100318;
|
||||
5'd17 : C0_S =18'd106232;
|
||||
5'd18 : C0_S =18'd112081;
|
||||
5'd19 : C0_S =18'd117863;
|
||||
5'd20 : C0_S =18'd123574;
|
||||
5'd21 : C0_S =18'd129210;
|
||||
5'd22 : C0_S =18'd134769;
|
||||
5'd23 : C0_S =18'd140246;
|
||||
5'd24 : C0_S =18'd145639;
|
||||
5'd25 : C0_S =18'd150945;
|
||||
5'd26 : C0_S =18'd156159;
|
||||
5'd27 : C0_S =18'd161279;
|
||||
5'd28 : C0_S =18'd166302;
|
||||
5'd29 : C0_S =18'd171225;
|
||||
5'd30 : C0_S =18'd176045;
|
||||
5'd31 : C0_S =18'd180759;
|
||||
// default : C0_S = C0_S;
|
||||
endcase
|
||||
|
||||
end
|
||||
|
||||
//------------------------
|
||||
|
||||
|
||||
//------------------------
|
||||
//----C1_S OK
|
||||
always@(*)
|
||||
begin
|
||||
|
||||
case(index)
|
||||
5'd 0 : C1_S =12'd3217;
|
||||
5'd 1 : C1_S =12'd3216;
|
||||
5'd 2 : C1_S =12'd3213;
|
||||
5'd 3 : C1_S =12'd3208;
|
||||
5'd 4 : C1_S =12'd3202;
|
||||
5'd 5 : C1_S =12'd3193;
|
||||
5'd 6 : C1_S =12'd3182;
|
||||
5'd 7 : C1_S =12'd3170;
|
||||
5'd 8 : C1_S =12'd3155;
|
||||
5'd 9 : C1_S =12'd3139;
|
||||
5'd10 : C1_S =12'd3121;
|
||||
5'd11 : C1_S =12'd3101;
|
||||
5'd12 : C1_S =12'd3079;
|
||||
5'd13 : C1_S =12'd3055;
|
||||
5'd14 : C1_S =12'd3029;
|
||||
5'd15 : C1_S =12'd3002;
|
||||
5'd16 : C1_S =12'd2972;
|
||||
5'd17 : C1_S =12'd2941;
|
||||
5'd18 : C1_S =12'd2908;
|
||||
5'd19 : C1_S =12'd2874;
|
||||
5'd20 : C1_S =12'd2837;
|
||||
5'd21 : C1_S =12'd2799;
|
||||
5'd22 : C1_S =12'd2759;
|
||||
5'd23 : C1_S =12'd2718;
|
||||
5'd24 : C1_S =12'd2675;
|
||||
5'd25 : C1_S =12'd2630;
|
||||
5'd26 : C1_S =12'd2584;
|
||||
5'd27 : C1_S =12'd2536;
|
||||
5'd28 : C1_S =12'd2487;
|
||||
5'd29 : C1_S =12'd2436;
|
||||
5'd30 : C1_S =12'd2384;
|
||||
5'd31 : C1_S =12'd2330;
|
||||
// default : C1_S = C1_S;
|
||||
endcase
|
||||
|
||||
end
|
||||
|
||||
//------------------------
|
||||
//----C2_S
|
||||
always@(*)
|
||||
begin
|
||||
|
||||
case(index)
|
||||
5'd 0 : C2_S =5'd 0;
|
||||
5'd 1 : C2_S =5'd 1;
|
||||
5'd 2 : C2_S =5'd 2;
|
||||
5'd 3 : C2_S =5'd 3;
|
||||
5'd 4 : C2_S =5'd 4;
|
||||
5'd 5 : C2_S =5'd 5;
|
||||
5'd 6 : C2_S =5'd 6;
|
||||
5'd 7 : C2_S =5'd 7;
|
||||
5'd 8 : C2_S =5'd 8;
|
||||
5'd 9 : C2_S =5'd 9;
|
||||
5'd10 : C2_S =5'd10;
|
||||
5'd11 : C2_S =5'd11;
|
||||
5'd12 : C2_S =5'd12;
|
||||
5'd13 : C2_S =5'd13;
|
||||
5'd14 : C2_S =5'd14;
|
||||
5'd15 : C2_S =5'd15;
|
||||
5'd16 : C2_S =5'd16;
|
||||
5'd17 : C2_S =5'd16;
|
||||
5'd18 : C2_S =5'd17;
|
||||
5'd19 : C2_S =5'd18;
|
||||
5'd20 : C2_S =5'd19;
|
||||
5'd21 : C2_S =5'd20;
|
||||
5'd22 : C2_S =5'd21;
|
||||
5'd23 : C2_S =5'd22;
|
||||
5'd24 : C2_S =5'd22;
|
||||
5'd25 : C2_S =5'd23;
|
||||
5'd26 : C2_S =5'd24;
|
||||
5'd27 : C2_S =5'd25;
|
||||
5'd28 : C2_S =5'd25;
|
||||
5'd29 : C2_S =5'd26;
|
||||
5'd30 : C2_S =5'd27;
|
||||
5'd31 : C2_S =5'd28;
|
||||
// default : C2_S = C2_S;
|
||||
endcase
|
||||
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,144 @@
|
|||
module COS_OP(
|
||||
clk ,
|
||||
rstn ,
|
||||
pha_map ,
|
||||
pha_indx_msb ,
|
||||
cos_op_o
|
||||
);
|
||||
|
||||
input clk;
|
||||
input rstn;
|
||||
input [18:0] pha_map;
|
||||
output [2:0] pha_indx_msb;
|
||||
output [14:0] cos_op_o;
|
||||
|
||||
wire [2:0] pha_indx_msb_w;
|
||||
assign pha_indx_msb_w=pha_map[18:16];
|
||||
|
||||
wire [15:0] pha_indx_lsb;
|
||||
assign pha_indx_lsb=pha_map[15:0];
|
||||
wire [15:0] pha_op;
|
||||
assign pha_op=pha_indx_msb_w[0]?(~pha_indx_lsb):pha_indx_lsb;
|
||||
|
||||
wire [4:0] indx;
|
||||
assign indx=pha_op[15:11];
|
||||
wire [10:0] x_w;
|
||||
assign x_w=pha_op[10:0];
|
||||
wire [17:0] c0;
|
||||
wire [11:0] c1;
|
||||
wire [5:0] c2;
|
||||
|
||||
|
||||
COEF_C coef_c_inst1(
|
||||
.index(indx) ,
|
||||
.C0_C(c0) ,
|
||||
.C1_C(c1) ,
|
||||
.C2_C(c2)
|
||||
);
|
||||
|
||||
reg[17:0] c0_r1;
|
||||
reg[17:0] c0_r2;
|
||||
reg[17:0] c0_r3;
|
||||
reg[17:0] c0_r4;
|
||||
reg[17:0] c0_r5;
|
||||
reg[17:0] c0_r6;
|
||||
always@(posedge clk)
|
||||
begin
|
||||
c0_r1<=c0;
|
||||
c0_r2<=c0_r1;
|
||||
c0_r3<=c0_r2;
|
||||
c0_r4<=c0_r3;
|
||||
c0_r5<=c0_r4;
|
||||
c0_r6<=c0_r5;
|
||||
end
|
||||
reg [11:0] c1_r1;
|
||||
reg [11:0] c1_r2;
|
||||
reg [11:0] c1_r3;
|
||||
always@(posedge clk)
|
||||
begin
|
||||
c1_r1<=c1;
|
||||
c1_r2<=c1_r1;
|
||||
c1_r3<=c1_r2;
|
||||
end
|
||||
reg [5:0] c2_r1;
|
||||
always@(posedge clk)
|
||||
c2_r1<=c2;
|
||||
reg[10:0] x_r1;
|
||||
reg[10:0] x_r2;
|
||||
reg[10:0] x_r3;
|
||||
reg[10:0] x_r4;
|
||||
always@(posedge clk)
|
||||
begin
|
||||
x_r1<=x_w;
|
||||
x_r2<=x_r1;
|
||||
x_r3<=x_r2;
|
||||
x_r4<=x_r3;
|
||||
end
|
||||
|
||||
wire [16:0] c2x;
|
||||
|
||||
DW_mult_pipe #(11,6,2,0,1) inst_mult_0(
|
||||
.clk (clk ),
|
||||
.rst_n (rstn ),
|
||||
.en (1'b1 ),
|
||||
.a (x_r1 ),
|
||||
.b (c2_r1 ),
|
||||
.tc (1'b0 ),
|
||||
.product (c2x )
|
||||
);
|
||||
|
||||
wire [5:0] c2x_w;
|
||||
assign c2x_w=c2x[10]?(c2x[16:11]+6'd1):c2x[16:11];
|
||||
|
||||
reg [11:0] c2xc1;
|
||||
always@(posedge clk)
|
||||
c2xc1<=c1_r2+c2x_w;
|
||||
wire [22:0] c2xc1x;
|
||||
DW_mult_pipe #(11,12,3,0,1) inst_mult_1(
|
||||
.clk (clk ),
|
||||
.rst_n (rstn ),
|
||||
.en (1'b1 ),
|
||||
.a (x_r3 ),
|
||||
.b (c2xc1 ),
|
||||
.tc (1'b0 ),
|
||||
.product (c2xc1x )
|
||||
);
|
||||
|
||||
|
||||
wire [12:0] c2xc1x_w;
|
||||
assign c2xc1x_w=c2xc1x[9]?(c2xc1x[22:10]+13'd1):c2xc1x[22:10];
|
||||
reg [12:0] c2xc1x_r;
|
||||
always@(posedge clk)
|
||||
c2xc1x_r<=c2xc1x_w;
|
||||
wire [17:0] c2xc1xc0;
|
||||
assign c2xc1xc0 =c0_r6-c2xc1x_r;
|
||||
|
||||
wire[15:0] c2xc1xc0_w1;
|
||||
assign c2xc1xc0_w1=c2xc1xc0[2]?({1'b0,c2xc1xc0[17:3]}+15'd1):{1'b0,c2xc1xc0[17:3]};
|
||||
|
||||
wire[14:0] c2xc1xc0_w;
|
||||
assign c2xc1xc0_w=(c2xc1xc0_w1>=15'd32767)?15'd32767:c2xc1xc0_w1[14:0];
|
||||
reg [14:0] c2xc1xc0_r;
|
||||
always@(posedge clk)
|
||||
c2xc1xc0_r<=c2xc1xc0_w;
|
||||
assign cos_op_o=c2xc1xc0_r;
|
||||
reg[2:0] pha_indx_msb_r1;
|
||||
reg[2:0] pha_indx_msb_r2;
|
||||
reg[2:0] pha_indx_msb_r3;
|
||||
reg[2:0] pha_indx_msb_r4;
|
||||
reg[2:0] pha_indx_msb_r5;
|
||||
reg[2:0] pha_indx_msb_r6;
|
||||
reg[2:0] pha_indx_msb_r7;
|
||||
always@(posedge clk)
|
||||
begin
|
||||
pha_indx_msb_r1<=pha_indx_msb_w;
|
||||
pha_indx_msb_r2<=pha_indx_msb_r1;
|
||||
pha_indx_msb_r3<=pha_indx_msb_r2;
|
||||
pha_indx_msb_r4<=pha_indx_msb_r3;
|
||||
pha_indx_msb_r5<=pha_indx_msb_r4;
|
||||
pha_indx_msb_r6<=pha_indx_msb_r5;
|
||||
pha_indx_msb_r7<=pha_indx_msb_r6;
|
||||
end
|
||||
|
||||
assign pha_indx_msb=pha_indx_msb_r7;
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,240 @@
|
|||
module NCO(
|
||||
clk,
|
||||
rstn,
|
||||
phase_manual_clr,
|
||||
phase_auto_clr,
|
||||
fcw,
|
||||
pha,
|
||||
|
||||
cos_0,
|
||||
cos_1,
|
||||
cos_2,
|
||||
cos_3,
|
||||
cos_4,
|
||||
cos_5,
|
||||
cos_6,
|
||||
cos_7,
|
||||
cos_8,
|
||||
cos_9,
|
||||
cos_10,
|
||||
cos_11,
|
||||
cos_12,
|
||||
cos_13,
|
||||
cos_14,
|
||||
cos_15,
|
||||
|
||||
sin_0,
|
||||
sin_1,
|
||||
sin_2,
|
||||
sin_3,
|
||||
sin_4,
|
||||
sin_5,
|
||||
sin_6,
|
||||
sin_7,
|
||||
sin_8,
|
||||
sin_9,
|
||||
sin_10,
|
||||
sin_11,
|
||||
sin_12,
|
||||
sin_13,
|
||||
sin_14,
|
||||
sin_15
|
||||
);
|
||||
|
||||
input clk;
|
||||
input rstn;
|
||||
input phase_manual_clr;
|
||||
input phase_auto_clr;
|
||||
input [47:0] fcw;
|
||||
input [15:0] pha;
|
||||
|
||||
output [15:0] cos_0;
|
||||
output [15:0] cos_1;
|
||||
output [15:0] cos_2;
|
||||
output [15:0] cos_3;
|
||||
output [15:0] cos_4;
|
||||
output [15:0] cos_5;
|
||||
output [15:0] cos_6;
|
||||
output [15:0] cos_7;
|
||||
output [15:0] cos_8;
|
||||
output [15:0] cos_9;
|
||||
output [15:0] cos_10;
|
||||
output [15:0] cos_11;
|
||||
output [15:0] cos_12;
|
||||
output [15:0] cos_13;
|
||||
output [15:0] cos_14;
|
||||
output [15:0] cos_15;
|
||||
|
||||
|
||||
output [15:0] sin_0;
|
||||
output [15:0] sin_1;
|
||||
output [15:0] sin_2;
|
||||
output [15:0] sin_3;
|
||||
output [15:0] sin_4;
|
||||
output [15:0] sin_5;
|
||||
output [15:0] sin_6;
|
||||
output [15:0] sin_7;
|
||||
output [15:0] sin_8;
|
||||
output [15:0] sin_9;
|
||||
output [15:0] sin_10;
|
||||
output [15:0] sin_11;
|
||||
output [15:0] sin_12;
|
||||
output [15:0] sin_13;
|
||||
output [15:0] sin_14;
|
||||
output [15:0] sin_15;
|
||||
|
||||
|
||||
reg [47:0] fcw1_r1;
|
||||
reg [47:0] fcw2_r1;
|
||||
reg [47:0] fcw3_r1;
|
||||
reg [47:0] fcw4_r1;
|
||||
reg [47:0] fcw5_r1;
|
||||
reg [47:0] fcw6_r1;
|
||||
reg [47:0] fcw7_r1;
|
||||
reg [47:0] fcw8_r1;
|
||||
reg [47:0] fcw9_r1;
|
||||
reg [47:0] fcw10_r1;
|
||||
reg [47:0] fcw11_r1;
|
||||
reg [47:0] fcw12_r1;
|
||||
reg [47:0] fcw13_r1;
|
||||
reg [47:0] fcw14_r1;
|
||||
reg [47:0] fcw15_r1;
|
||||
reg [47:0] fcw16_r1;
|
||||
|
||||
|
||||
wire [47:0] fcw2_w;
|
||||
wire [47:0] fcw4_w;
|
||||
wire [47:0] fcw8_w;
|
||||
wire [47:0] fcw16_w;
|
||||
|
||||
reg [15:0] pha_r;
|
||||
|
||||
assign fcw2_w=fcw<<3'd1;
|
||||
assign fcw4_w=fcw<<3'd2;
|
||||
assign fcw8_w=fcw<<3'd3;
|
||||
assign fcw16_w=fcw<<3'd4;
|
||||
|
||||
always@(posedge clk or negedge rstn)
|
||||
if(!rstn)
|
||||
begin
|
||||
fcw1_r1 <=48'd0;
|
||||
fcw2_r1 <=48'd0;
|
||||
fcw3_r1 <=48'd0;
|
||||
fcw4_r1 <=48'd0;
|
||||
fcw5_r1 <=48'd0;
|
||||
fcw6_r1 <=48'd0;
|
||||
fcw7_r1 <=48'd0;
|
||||
fcw8_r1 <=48'd0;
|
||||
fcw9_r1 <=48'd0;
|
||||
fcw10_r1 <=48'd0;
|
||||
fcw11_r1 <=48'd0;
|
||||
fcw12_r1 <=48'd0;
|
||||
fcw13_r1 <=48'd0;
|
||||
fcw14_r1 <=48'd0;
|
||||
fcw15_r1 <=48'd0;
|
||||
fcw16_r1 <=48'd0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
fcw1_r1 <=fcw;
|
||||
fcw2_r1 <=fcw2_w;
|
||||
fcw3_r1 <=fcw2_w+fcw;
|
||||
fcw4_r1 <=fcw4_w;
|
||||
fcw5_r1 <=fcw4_w+fcw;
|
||||
fcw6_r1 <=fcw4_w+fcw2_w;
|
||||
fcw7_r1 <=fcw8_w-fcw;
|
||||
fcw8_r1 <=fcw8_w;
|
||||
fcw9_r1 <=fcw8_w+fcw;
|
||||
fcw10_r1 <=fcw8_w+fcw2_w;
|
||||
fcw11_r1 <=fcw8_w+fcw2_w+fcw;
|
||||
fcw12_r1 <=fcw8_w+fcw4_w;
|
||||
fcw13_r1 <=fcw8_w+fcw4_w+fcw;
|
||||
fcw14_r1 <=fcw16_w-fcw2_w;
|
||||
fcw15_r1 <=fcw16_w-fcw;
|
||||
fcw16_r1 <=fcw16_w;
|
||||
|
||||
end
|
||||
|
||||
always @(posedge clk or negedge rstn) begin
|
||||
if(!rstn) begin
|
||||
pha_r <= 16'd0;
|
||||
end
|
||||
else begin
|
||||
pha_r <= pha;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
wire clr_acc;
|
||||
wire clr_fix;
|
||||
assign clr_acc = phase_auto_clr | phase_manual_clr;
|
||||
assign clr_fix = phase_manual_clr;
|
||||
|
||||
wire [15:0] s1_i_o;
|
||||
wire [15:0] s2_i_o;
|
||||
wire [15:0] s3_i_o;
|
||||
|
||||
P_NCO inst_p_nco(
|
||||
.clk (clk ),
|
||||
.rstn (rstn ),
|
||||
.clr (clr_fix ),
|
||||
.clr_acc (clr_acc ),
|
||||
.pha (pha_r ),
|
||||
.s1 (s1_i_o ),
|
||||
.s2 (s2_i_o ),
|
||||
.s3 (s3_i_o ),
|
||||
.s1_o (s1_i_o ),
|
||||
.s2_o (s2_i_o ),
|
||||
.s3_o (s3_i_o ),
|
||||
.fcw1 (fcw1_r1 ),
|
||||
.fcw2 (fcw2_r1 ),
|
||||
.fcw3 (fcw3_r1 ),
|
||||
.fcw4 (fcw4_r1 ),
|
||||
.fcw5 (fcw5_r1 ),
|
||||
.fcw6 (fcw6_r1 ),
|
||||
.fcw7 (fcw7_r1 ),
|
||||
.fcw8 (fcw8_r1 ),
|
||||
.fcw9 (fcw9_r1 ),
|
||||
.fcw10 (fcw10_r1 ),
|
||||
.fcw11 (fcw11_r1 ),
|
||||
.fcw12 (fcw12_r1 ),
|
||||
.fcw13 (fcw13_r1 ),
|
||||
.fcw14 (fcw14_r1 ),
|
||||
.fcw15 (fcw15_r1 ),
|
||||
.fcw16 (fcw16_r1 ),
|
||||
.cos_0 (cos_0 ),
|
||||
.cos_1 (cos_1 ),
|
||||
.cos_2 (cos_2 ),
|
||||
.cos_3 (cos_3 ),
|
||||
.cos_4 (cos_4 ),
|
||||
.cos_5 (cos_5 ),
|
||||
.cos_6 (cos_6 ),
|
||||
.cos_7 (cos_7 ),
|
||||
.cos_8 (cos_8 ),
|
||||
.cos_9 (cos_9 ),
|
||||
.cos_10 (cos_10 ),
|
||||
.cos_11 (cos_11 ),
|
||||
.cos_12 (cos_12 ),
|
||||
.cos_13 (cos_13 ),
|
||||
.cos_14 (cos_14 ),
|
||||
.cos_15 (cos_15 ),
|
||||
|
||||
.sin_0 (sin_0 ),
|
||||
.sin_1 (sin_1 ),
|
||||
.sin_2 (sin_2 ),
|
||||
.sin_3 (sin_3 ),
|
||||
.sin_4 (sin_4 ),
|
||||
.sin_5 (sin_5 ),
|
||||
.sin_6 (sin_6 ),
|
||||
.sin_7 (sin_7 ),
|
||||
.sin_8 (sin_8 ),
|
||||
.sin_9 (sin_9 ),
|
||||
.sin_10 (sin_10 ),
|
||||
.sin_11 (sin_11 ),
|
||||
.sin_12 (sin_12 ),
|
||||
.sin_13 (sin_13 ),
|
||||
.sin_14 (sin_14 ),
|
||||
.sin_15 (sin_15 )
|
||||
|
||||
);
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,51 @@
|
|||
module NCO_CH1(
|
||||
clk,
|
||||
rstn,
|
||||
phase_manual_clr,
|
||||
phase_auto_clr,
|
||||
fcw,
|
||||
pha,
|
||||
|
||||
cos,
|
||||
|
||||
sin
|
||||
);
|
||||
|
||||
input clk;
|
||||
input rstn;
|
||||
input phase_manual_clr;
|
||||
input phase_auto_clr;
|
||||
input [47:0] fcw;
|
||||
input [15:0] pha;
|
||||
|
||||
output [15:0] cos;
|
||||
output [15:0] sin;
|
||||
|
||||
|
||||
wire clr_acc;
|
||||
wire clr_fix;
|
||||
assign clr_acc = phase_auto_clr | phase_manual_clr;
|
||||
assign clr_fix = phase_manual_clr;
|
||||
|
||||
wire [15:0] s1_i_o;
|
||||
wire [15:0] s2_i_o;
|
||||
wire [15:0] s3_i_o;
|
||||
|
||||
P_NCO_CH1 inst_p_nco(
|
||||
.clk (clk ),
|
||||
.rstn (rstn ),
|
||||
.clr (clr_fix ),
|
||||
.clr_acc (clr_acc ),
|
||||
.pha (pha ),
|
||||
.s1 (s1_i_o ),
|
||||
.s2 (s2_i_o ),
|
||||
.s3 (s3_i_o ),
|
||||
.s1_o (s1_i_o ),
|
||||
.s2_o (s2_i_o ),
|
||||
.s3_o (s3_i_o ),
|
||||
.fcw (fcw ),
|
||||
.cos (cos ),
|
||||
.sin (sin )
|
||||
|
||||
);
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,292 @@
|
|||
module P_NCO(
|
||||
clk,
|
||||
rstn,
|
||||
clr,
|
||||
clr_acc,
|
||||
pha,
|
||||
|
||||
s1,
|
||||
s2,
|
||||
s3,
|
||||
|
||||
s1_o,
|
||||
s2_o,
|
||||
s3_o,
|
||||
|
||||
fcw1,
|
||||
fcw2,
|
||||
fcw3,
|
||||
fcw4,
|
||||
fcw5,
|
||||
fcw6,
|
||||
fcw7,
|
||||
fcw8,
|
||||
fcw9,
|
||||
fcw10,
|
||||
fcw11,
|
||||
fcw12,
|
||||
fcw13,
|
||||
fcw14,
|
||||
fcw15,
|
||||
fcw16,
|
||||
|
||||
cos_0,
|
||||
cos_1,
|
||||
cos_2,
|
||||
cos_3,
|
||||
cos_4,
|
||||
cos_5,
|
||||
cos_6,
|
||||
cos_7,
|
||||
cos_8,
|
||||
cos_9,
|
||||
cos_10,
|
||||
cos_11,
|
||||
cos_12,
|
||||
cos_13,
|
||||
cos_14,
|
||||
cos_15,
|
||||
|
||||
sin_0,
|
||||
sin_1,
|
||||
sin_2,
|
||||
sin_3,
|
||||
sin_4,
|
||||
sin_5,
|
||||
sin_6,
|
||||
sin_7,
|
||||
sin_8,
|
||||
sin_9,
|
||||
sin_10,
|
||||
sin_11,
|
||||
sin_12,
|
||||
sin_13,
|
||||
sin_14,
|
||||
sin_15
|
||||
);
|
||||
|
||||
input clk;
|
||||
input rstn;
|
||||
input clr;
|
||||
input clr_acc;
|
||||
input [15:0] pha;
|
||||
|
||||
input [15:0] s1;
|
||||
input [15:0] s2;
|
||||
input [15:0] s3;
|
||||
|
||||
output [15:0] s1_o;
|
||||
output [15:0] s2_o;
|
||||
output [15:0] s3_o;
|
||||
|
||||
output [15:0] cos_0;
|
||||
output [15:0] cos_1;
|
||||
output [15:0] cos_2;
|
||||
output [15:0] cos_3;
|
||||
output [15:0] cos_4;
|
||||
output [15:0] cos_5;
|
||||
output [15:0] cos_6;
|
||||
output [15:0] cos_7;
|
||||
output [15:0] cos_8;
|
||||
output [15:0] cos_9;
|
||||
output [15:0] cos_10;
|
||||
output [15:0] cos_11;
|
||||
output [15:0] cos_12;
|
||||
output [15:0] cos_13;
|
||||
output [15:0] cos_14;
|
||||
output [15:0] cos_15;
|
||||
|
||||
|
||||
output [15:0] sin_0;
|
||||
output [15:0] sin_1;
|
||||
output [15:0] sin_2;
|
||||
output [15:0] sin_3;
|
||||
output [15:0] sin_4;
|
||||
output [15:0] sin_5;
|
||||
output [15:0] sin_6;
|
||||
output [15:0] sin_7;
|
||||
output [15:0] sin_8;
|
||||
output [15:0] sin_9;
|
||||
output [15:0] sin_10;
|
||||
output [15:0] sin_11;
|
||||
output [15:0] sin_12;
|
||||
output [15:0] sin_13;
|
||||
output [15:0] sin_14;
|
||||
output [15:0] sin_15;
|
||||
|
||||
|
||||
input [47:0] fcw1;
|
||||
input [47:0] fcw2;
|
||||
input [47:0] fcw3;
|
||||
input [47:0] fcw4;
|
||||
input [47:0] fcw5;
|
||||
input [47:0] fcw6;
|
||||
input [47:0] fcw7;
|
||||
input [47:0] fcw8;
|
||||
input [47:0] fcw9;
|
||||
input [47:0] fcw10;
|
||||
input [47:0] fcw11;
|
||||
input [47:0] fcw12;
|
||||
input [47:0] fcw13;
|
||||
input [47:0] fcw14;
|
||||
input [47:0] fcw15;
|
||||
input [47:0] fcw16;
|
||||
|
||||
|
||||
reg [15:0] pha_r;
|
||||
always@(posedge clk or negedge rstn)
|
||||
if(!rstn)
|
||||
pha_r <= 16'd0;
|
||||
else
|
||||
pha_r <= pha;
|
||||
|
||||
wire [18:0] pha0;
|
||||
wire [18:0] pha1;
|
||||
wire [18:0] pha2;
|
||||
wire [18:0] pha3;
|
||||
wire [18:0] pha4;
|
||||
wire [18:0] pha5;
|
||||
wire [18:0] pha6;
|
||||
wire [18:0] pha7;
|
||||
wire [18:0] pha8;
|
||||
wire [18:0] pha9;
|
||||
wire [18:0] pha10;
|
||||
wire [18:0] pha11;
|
||||
wire [18:0] pha12;
|
||||
wire [18:0] pha13;
|
||||
wire [18:0] pha14;
|
||||
wire [18:0] pha15;
|
||||
|
||||
PIPE3_ADD_48BIT inst_pipe_0(.clk(clk),.rstn(rstn),.in(fcw1),.clr(clr),.ptw(pha_r),.s1(s1),.s2(s2),.s3(s3),.out(pha0));
|
||||
PIPE3_ADD_48BIT inst_pipe_1(.clk(clk),.rstn(rstn),.in(fcw2),.clr(clr),.ptw(pha_r),.s1(s1),.s2(s2),.s3(s3),.out(pha1));
|
||||
PIPE3_ADD_48BIT inst_pipe_2(.clk(clk),.rstn(rstn),.in(fcw3),.clr(clr),.ptw(pha_r),.s1(s1),.s2(s2),.s3(s3),.out(pha2));
|
||||
PIPE3_ADD_48BIT inst_pipe_3(.clk(clk),.rstn(rstn),.in(fcw4),.clr(clr),.ptw(pha_r),.s1(s1),.s2(s2),.s3(s3),.out(pha3));
|
||||
PIPE3_ADD_48BIT inst_pipe_4(.clk(clk),.rstn(rstn),.in(fcw5),.clr(clr),.ptw(pha_r),.s1(s1),.s2(s2),.s3(s3),.out(pha4));
|
||||
PIPE3_ADD_48BIT inst_pipe_5(.clk(clk),.rstn(rstn),.in(fcw6),.clr(clr),.ptw(pha_r),.s1(s1),.s2(s2),.s3(s3),.out(pha5));
|
||||
PIPE3_ADD_48BIT inst_pipe_6(.clk(clk),.rstn(rstn),.in(fcw7),.clr(clr),.ptw(pha_r),.s1(s1),.s2(s2),.s3(s3),.out(pha6));
|
||||
PIPE3_ADD_48BIT inst_pipe_7(.clk(clk),.rstn(rstn),.in(fcw8),.clr(clr),.ptw(pha_r),.s1(s1),.s2(s2),.s3(s3),.out(pha7));
|
||||
PIPE3_ADD_48BIT inst_pipe_8(.clk(clk),.rstn(rstn),.in(fcw9),.clr(clr),.ptw(pha_r),.s1(s1),.s2(s2),.s3(s3),.out(pha8));
|
||||
PIPE3_ADD_48BIT inst_pipe_9(.clk(clk),.rstn(rstn),.in(fcw10),.clr(clr),.ptw(pha_r),.s1(s1),.s2(s2),.s3(s3),.out(pha9));
|
||||
PIPE3_ADD_48BIT inst_pipe_10(.clk(clk),.rstn(rstn),.in(fcw11),.clr(clr),.ptw(pha_r),.s1(s1),.s2(s2),.s3(s3),.out(pha10));
|
||||
PIPE3_ADD_48BIT inst_pipe_11(.clk(clk),.rstn(rstn),.in(fcw12),.clr(clr),.ptw(pha_r),.s1(s1),.s2(s2),.s3(s3),.out(pha11));
|
||||
PIPE3_ADD_48BIT inst_pipe_12(.clk(clk),.rstn(rstn),.in(fcw13),.clr(clr),.ptw(pha_r),.s1(s1),.s2(s2),.s3(s3),.out(pha12));
|
||||
PIPE3_ADD_48BIT inst_pipe_13(.clk(clk),.rstn(rstn),.in(fcw14),.clr(clr),.ptw(pha_r),.s1(s1),.s2(s2),.s3(s3),.out(pha13));
|
||||
PIPE3_ADD_48BIT inst_pipe_14(.clk(clk),.rstn(rstn),.in(fcw15),.clr(clr),.ptw(pha_r),.s1(s1),.s2(s2),.s3(s3),.out(pha14));
|
||||
PIPE3_ACC_48BIT inst_pipe_15(.clk(clk),.rstn(rstn),.in(fcw16),.clr(clr_acc),.ptw(pha),.s_o_1(s1_o),.s_o_2(s2_o),.s_o_3(s3_o),.s_i_1(s1),.s_i_2(s2),.s_i_3(s3),.out(pha15));
|
||||
|
||||
PH2AMP inst_ph2amp_0(
|
||||
.clk(clk) ,
|
||||
.rstn(rstn) ,
|
||||
.pha_map(pha0) ,
|
||||
.sin_o(sin_0) ,
|
||||
.cos_o(cos_0)
|
||||
);
|
||||
PH2AMP inst_ph2amp_1(
|
||||
.clk(clk) ,
|
||||
.rstn(rstn) ,
|
||||
.pha_map(pha1) ,
|
||||
.sin_o(sin_1) ,
|
||||
.cos_o(cos_1)
|
||||
);
|
||||
PH2AMP inst_ph2amp_2(
|
||||
.clk(clk) ,
|
||||
.rstn(rstn) ,
|
||||
.pha_map(pha2) ,
|
||||
.sin_o(sin_2) ,
|
||||
.cos_o(cos_2)
|
||||
);
|
||||
PH2AMP inst_ph2amp_3(
|
||||
.clk(clk) ,
|
||||
.rstn(rstn) ,
|
||||
.pha_map(pha3) ,
|
||||
.sin_o(sin_3) ,
|
||||
.cos_o(cos_3)
|
||||
);
|
||||
PH2AMP inst_ph2amp_4(
|
||||
.clk(clk) ,
|
||||
.rstn(rstn) ,
|
||||
.pha_map(pha4) ,
|
||||
.sin_o(sin_4) ,
|
||||
.cos_o(cos_4)
|
||||
);
|
||||
PH2AMP inst_ph2amp_5(
|
||||
.clk(clk) ,
|
||||
.rstn(rstn) ,
|
||||
.pha_map(pha5) ,
|
||||
.sin_o(sin_5) ,
|
||||
.cos_o(cos_5)
|
||||
);
|
||||
PH2AMP inst_ph2amp_6(
|
||||
.clk(clk) ,
|
||||
.rstn(rstn) ,
|
||||
.pha_map(pha6) ,
|
||||
.sin_o(sin_6) ,
|
||||
.cos_o(cos_6)
|
||||
);
|
||||
PH2AMP inst_ph2amp_7(
|
||||
.clk(clk) ,
|
||||
.rstn(rstn) ,
|
||||
.pha_map(pha7) ,
|
||||
.sin_o(sin_7) ,
|
||||
.cos_o(cos_7)
|
||||
);
|
||||
|
||||
PH2AMP inst_ph2amp_8(
|
||||
.clk(clk) ,
|
||||
.rstn(rstn) ,
|
||||
.pha_map(pha8) ,
|
||||
.sin_o(sin_8) ,
|
||||
.cos_o(cos_8)
|
||||
);
|
||||
PH2AMP inst_ph2amp_9(
|
||||
.clk(clk) ,
|
||||
.rstn(rstn) ,
|
||||
.pha_map(pha9) ,
|
||||
.sin_o(sin_9) ,
|
||||
.cos_o(cos_9)
|
||||
);
|
||||
PH2AMP inst_ph2amp_10(
|
||||
.clk(clk) ,
|
||||
.rstn(rstn) ,
|
||||
.pha_map(pha10) ,
|
||||
.sin_o(sin_10) ,
|
||||
.cos_o(cos_10)
|
||||
);
|
||||
PH2AMP inst_ph2amp_11(
|
||||
.clk(clk) ,
|
||||
.rstn(rstn) ,
|
||||
.pha_map(pha11) ,
|
||||
.sin_o(sin_11) ,
|
||||
.cos_o(cos_11)
|
||||
);
|
||||
PH2AMP inst_ph2amp_12(
|
||||
.clk(clk) ,
|
||||
.rstn(rstn) ,
|
||||
.pha_map(pha12) ,
|
||||
.sin_o(sin_12) ,
|
||||
.cos_o(cos_12)
|
||||
);
|
||||
PH2AMP inst_ph2amp_13(
|
||||
.clk(clk) ,
|
||||
.rstn(rstn) ,
|
||||
.pha_map(pha13) ,
|
||||
.sin_o(sin_13) ,
|
||||
.cos_o(cos_13)
|
||||
);
|
||||
PH2AMP inst_ph2amp_14(
|
||||
.clk(clk) ,
|
||||
.rstn(rstn) ,
|
||||
.pha_map(pha14) ,
|
||||
.sin_o(sin_14) ,
|
||||
.cos_o(cos_14)
|
||||
);
|
||||
PH2AMP inst_ph2amp_15(
|
||||
.clk(clk) ,
|
||||
.rstn(rstn) ,
|
||||
.pha_map(pha15) ,
|
||||
.sin_o(sin_15) ,
|
||||
.cos_o(cos_15)
|
||||
);
|
||||
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,65 @@
|
|||
module P_NCO_CH1(
|
||||
clk,
|
||||
rstn,
|
||||
clr,
|
||||
clr_acc,
|
||||
pha,
|
||||
|
||||
s1,
|
||||
s2,
|
||||
s3,
|
||||
|
||||
s1_o,
|
||||
s2_o,
|
||||
s3_o,
|
||||
|
||||
fcw,
|
||||
|
||||
cos,
|
||||
sin
|
||||
);
|
||||
|
||||
input clk;
|
||||
input rstn;
|
||||
input clr;
|
||||
input clr_acc;
|
||||
input [15:0] pha;
|
||||
|
||||
input [15:0] s1;
|
||||
input [15:0] s2;
|
||||
input [15:0] s3;
|
||||
|
||||
output [15:0] s1_o;
|
||||
output [15:0] s2_o;
|
||||
output [15:0] s3_o;
|
||||
|
||||
output [15:0] cos;
|
||||
output [15:0] sin;
|
||||
|
||||
|
||||
input [47:0] fcw;
|
||||
|
||||
|
||||
reg [15:0] pha_r;
|
||||
always@(posedge clk or negedge rstn)
|
||||
if(!rstn)
|
||||
pha_r <= 16'd0;
|
||||
else
|
||||
pha_r <= pha;
|
||||
|
||||
|
||||
|
||||
|
||||
wire [18:0] pha0;
|
||||
|
||||
PIPE3_ACC_48BIT inst_pipe(.clk(clk),.rstn(rstn),.in(fcw),.clr(clr_acc),.ptw(pha_r),.s_o_1(s1_o),.s_o_2(s2_o),.s_o_3(s3_o),.s_i_1(s1),.s_i_2(s2),.s_i_3(s3),.out(pha0));
|
||||
|
||||
PH2AMP inst_ph2amp_0(
|
||||
.clk(clk) ,
|
||||
.rstn(rstn) ,
|
||||
.pha_map(pha0) ,
|
||||
.sin_o(sin) ,
|
||||
.cos_o(cos)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,83 @@
|
|||
module PH2AMP(
|
||||
clk ,
|
||||
rstn ,
|
||||
pha_map ,
|
||||
sin_o ,
|
||||
cos_o
|
||||
);
|
||||
input clk;
|
||||
input rstn;
|
||||
input [18:0] pha_map;
|
||||
|
||||
output [15:0] sin_o;
|
||||
output [15:0] cos_o;
|
||||
|
||||
//wire [2:0] pha_indx_msb_s;
|
||||
wire [14:0] sin_w;
|
||||
SIN_OP inst_sin_op(
|
||||
.clk(clk),
|
||||
.rstn(rstn),
|
||||
.pha_map(pha_map),
|
||||
// .pha_indx_msb(pha_indx_msb_s),
|
||||
.sin_op_o(sin_w)
|
||||
);
|
||||
wire [2:0] pha_indx_msb_c;
|
||||
wire [14:0] cos_w;
|
||||
COS_OP inst_cos_op(
|
||||
.clk(clk) ,
|
||||
.rstn(rstn) ,
|
||||
.pha_map(pha_map) ,
|
||||
.pha_indx_msb(pha_indx_msb_c),
|
||||
.cos_op_o(cos_w)
|
||||
);
|
||||
wire[15:0] cos_w_1;
|
||||
wire[15:0] sin_w_1;
|
||||
wire[15:0] cos_w_0;
|
||||
wire[15:0] sin_w_0;//0:-,1:+
|
||||
|
||||
assign cos_w_1={1'b0,cos_w};
|
||||
assign sin_w_1={1'b0,sin_w};
|
||||
assign cos_w_0=(cos_w_1==16'd0)?16'd0:~cos_w_1+16'd1;
|
||||
assign sin_w_0=(sin_w_1==16'd0)?16'd0:~sin_w_1+16'd1;
|
||||
|
||||
reg[15:0] cos_tmp;
|
||||
reg[15:0] sin_tmp;
|
||||
always@(posedge clk)
|
||||
case(pha_indx_msb_c)//synopsys parallel_case
|
||||
3'b000:begin
|
||||
cos_tmp<=cos_w_1;
|
||||
sin_tmp<=sin_w_1;
|
||||
end
|
||||
3'b001:begin
|
||||
cos_tmp<=sin_w_1;
|
||||
sin_tmp<=cos_w_1;
|
||||
end
|
||||
3'b010:begin
|
||||
cos_tmp<=sin_w_0;
|
||||
sin_tmp<=cos_w_1;
|
||||
end
|
||||
3'b011:begin
|
||||
cos_tmp<=cos_w_0;
|
||||
sin_tmp<=sin_w_1;
|
||||
end
|
||||
3'b100:begin
|
||||
cos_tmp<=cos_w_0;
|
||||
sin_tmp<=sin_w_0;
|
||||
end
|
||||
3'b101:begin
|
||||
cos_tmp<=sin_w_0;
|
||||
sin_tmp<=cos_w_0;
|
||||
end
|
||||
3'b110:begin
|
||||
cos_tmp<=sin_w_1;
|
||||
sin_tmp<=cos_w_0;
|
||||
end
|
||||
3'b111:begin
|
||||
cos_tmp<=cos_w_1;
|
||||
sin_tmp<=sin_w_0;
|
||||
end
|
||||
endcase
|
||||
|
||||
assign sin_o=sin_tmp;
|
||||
assign cos_o=cos_tmp;
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,64 @@
|
|||
|
||||
|
||||
module PIPE3_ACC_48BIT(
|
||||
clk,
|
||||
rstn,
|
||||
in,
|
||||
clr,
|
||||
ptw,
|
||||
s_i_1,
|
||||
s_i_2,
|
||||
s_i_3,
|
||||
s_o_1,
|
||||
s_o_2,
|
||||
s_o_3,
|
||||
out
|
||||
);
|
||||
|
||||
//---
|
||||
|
||||
input clk;
|
||||
input rstn;
|
||||
input [47:0] in;
|
||||
input clr;
|
||||
input [15:0] ptw;
|
||||
|
||||
input [15:0] s_i_1;
|
||||
input [15:0] s_i_2;
|
||||
input [15:0] s_i_3;
|
||||
|
||||
output [15:0] s_o_1;
|
||||
output [15:0] s_o_2;
|
||||
output [15:0] s_o_3;
|
||||
output [18:0] out;
|
||||
|
||||
//----------------------------------------------------------------------------------------------------
|
||||
|
||||
reg [47:0] acc;
|
||||
always@(posedge clk or negedge rstn)
|
||||
if(!rstn)
|
||||
acc<=48'h0;
|
||||
else if(clr)
|
||||
acc<=48'h0;
|
||||
else
|
||||
acc<={s_i_1,s_i_2,s_i_3}+in;
|
||||
|
||||
|
||||
//----------------------------------------------------------------------------------------------------
|
||||
wire [15:0] s1;
|
||||
wire [15:0] s2;
|
||||
wire [15:0] s3;
|
||||
|
||||
assign s_o_1 = acc[47:32];
|
||||
assign s_o_2 = acc[31:16];
|
||||
assign s_o_3 = acc[15:0];
|
||||
|
||||
wire[18:0] pha_w;
|
||||
assign pha_w=acc[47:29];
|
||||
reg[18:0] pha_r;
|
||||
always@(posedge clk)
|
||||
pha_r<=pha_w+{ptw,3'b0};
|
||||
|
||||
assign out=pha_r;
|
||||
//END
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,50 @@
|
|||
|
||||
|
||||
module PIPE3_ADD_48BIT(
|
||||
clk,
|
||||
rstn,
|
||||
in,
|
||||
clr,
|
||||
ptw,
|
||||
s1,
|
||||
s2,
|
||||
s3,
|
||||
out
|
||||
);
|
||||
|
||||
//---
|
||||
|
||||
input clk;
|
||||
input rstn;
|
||||
input [47:0] in;
|
||||
input clr;
|
||||
input [15:0] ptw;
|
||||
|
||||
input [15:0] s1;
|
||||
input [15:0] s2;
|
||||
input [15:0] s3;
|
||||
output [18:0] out;
|
||||
|
||||
|
||||
//----------------------------------------------------------------------------------------------------
|
||||
|
||||
reg [47:0] acc;
|
||||
always@(posedge clk or negedge rstn)
|
||||
if(!rstn)
|
||||
acc<=48'h0;
|
||||
else if(clr)
|
||||
acc<=48'h0;
|
||||
else
|
||||
acc<={s1,s2,s3}+in;
|
||||
//---
|
||||
|
||||
wire[18:0] pha_w;
|
||||
assign pha_w=acc[47:29];
|
||||
reg[18:0] pha_r;
|
||||
always@(posedge clk)
|
||||
pha_r<=pha_w+{ptw,3'b0};
|
||||
|
||||
|
||||
assign out=pha_r;
|
||||
//END
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,144 @@
|
|||
module SIN_OP(
|
||||
clk,
|
||||
rstn,
|
||||
pha_map,
|
||||
// pha_indx_msb,
|
||||
sin_op_o
|
||||
);
|
||||
|
||||
input clk;
|
||||
input rstn;
|
||||
input[18:0] pha_map;
|
||||
//output [2:0] pha_indx_msb;
|
||||
output [14:0] sin_op_o;
|
||||
|
||||
wire [2:0] pha_indx_msb_w;
|
||||
assign pha_indx_msb_w=pha_map[18:16];
|
||||
|
||||
wire [15:0] pha_indx_lsb;
|
||||
assign pha_indx_lsb=pha_map[15:0];
|
||||
wire [15:0] pha_op;
|
||||
assign pha_op=pha_indx_msb_w[0]?(~pha_indx_lsb):pha_indx_lsb;
|
||||
|
||||
wire [4:0] indx;
|
||||
assign indx=pha_op[15:11];
|
||||
wire [10:0] x_w;
|
||||
assign x_w=pha_op[10:0];
|
||||
wire [17:0] c0;
|
||||
wire [11:0] c1;
|
||||
wire [4:0] c2;
|
||||
|
||||
COEF_S coef_s_inst1(
|
||||
.index(indx) ,
|
||||
.C0_S(c0) ,
|
||||
.C1_S(c1) ,
|
||||
.C2_S(c2)
|
||||
);
|
||||
|
||||
reg[17:0] c0_r1;
|
||||
reg[17:0] c0_r2;
|
||||
reg[17:0] c0_r3;
|
||||
reg[17:0] c0_r4;
|
||||
reg[17:0] c0_r5;
|
||||
reg[17:0] c0_r6;
|
||||
always@(posedge clk)
|
||||
begin
|
||||
c0_r1<=c0;
|
||||
c0_r2<=c0_r1;
|
||||
c0_r3<=c0_r2;
|
||||
c0_r4<=c0_r3;
|
||||
c0_r5<=c0_r4;
|
||||
c0_r6<=c0_r5;
|
||||
end
|
||||
reg [11:0] c1_r1;
|
||||
reg [11:0] c1_r2;
|
||||
reg [11:0] c1_r3;
|
||||
always@(posedge clk)
|
||||
begin
|
||||
c1_r1<=c1;
|
||||
c1_r2<=c1_r1;
|
||||
c1_r3<=c1_r2;
|
||||
end
|
||||
reg [4:0] c2_r1;
|
||||
always@(posedge clk)
|
||||
c2_r1<=c2;
|
||||
reg[10:0] x_r1;
|
||||
reg[10:0] x_r2;
|
||||
reg[10:0] x_r3;
|
||||
reg[10:0] x_r4;
|
||||
always@(posedge clk)
|
||||
begin
|
||||
x_r1<=x_w;
|
||||
x_r2<=x_r1;
|
||||
x_r3<=x_r2;
|
||||
x_r4<=x_r3;
|
||||
end
|
||||
|
||||
wire [15:0] c2x;
|
||||
|
||||
DW_mult_pipe #(11,5,2,0,1) inst_mult_0(
|
||||
.clk (clk ),
|
||||
.rst_n (rstn ),
|
||||
.en (1'b1 ),
|
||||
.a (x_r1 ),
|
||||
.b (c2_r1 ),
|
||||
.tc (1'b0 ),
|
||||
.product (c2x )
|
||||
);
|
||||
|
||||
|
||||
wire [4:0] c2x_w;
|
||||
assign c2x_w=c2x[10]?(c2x[15:11]+5'd1):c2x[15:11];
|
||||
reg [11:0] c2xc1;
|
||||
always@(posedge clk)
|
||||
c2xc1<=c1_r2-c2x_w;
|
||||
|
||||
wire [22:0] c2xc1x;
|
||||
|
||||
DW_mult_pipe #(11,12,3,0,1) inst_mult_1(
|
||||
.clk (clk ),
|
||||
.rst_n (rstn ),
|
||||
.en (1'b1 ),
|
||||
.a (x_r3 ),
|
||||
.b (c2xc1 ),
|
||||
.tc (1'b0 ),
|
||||
.product (c2xc1x )
|
||||
);
|
||||
|
||||
wire [12:0] c2xc1x_w;
|
||||
assign c2xc1x_w=c2xc1x[9]?(c2xc1x[22:10]+13'd1):c2xc1x[22:10];
|
||||
reg [12:0] c2xc1x_r;
|
||||
always@(posedge clk)
|
||||
c2xc1x_r<=c2xc1x_w;
|
||||
wire[17:0] c2xc1xc0;
|
||||
assign c2xc1xc0=c0_r6+c2xc1x_r;
|
||||
wire [14:0] c2xc1xc0_w;
|
||||
assign c2xc1xc0_w=c2xc1xc0[2]?(c2xc1xc0[17:3]+13'd1):c2xc1xc0[17:3];
|
||||
reg [14:0] c2xc1xc0_r;
|
||||
always@(posedge clk)
|
||||
c2xc1xc0_r<=c2xc1xc0_w;
|
||||
|
||||
assign sin_op_o=c2xc1xc0_r;
|
||||
/*
|
||||
reg[2:0] pha_indx_msb_r1;
|
||||
reg[2:0] pha_indx_msb_r2;
|
||||
reg[2:0] pha_indx_msb_r3;
|
||||
reg[2:0] pha_indx_msb_r4;
|
||||
reg[2:0] pha_indx_msb_r5;
|
||||
reg[2:0] pha_indx_msb_r6;
|
||||
reg[2:0] pha_indx_msb_r7;
|
||||
always@(posedge clk)
|
||||
begin
|
||||
pha_indx_msb_r1<=pha_indx_msb_w;
|
||||
pha_indx_msb_r2<=pha_indx_msb_r1;
|
||||
pha_indx_msb_r3<=pha_indx_msb_r2;
|
||||
pha_indx_msb_r4<=pha_indx_msb_r3;
|
||||
pha_indx_msb_r5<=pha_indx_msb_r4;
|
||||
pha_indx_msb_r6<=pha_indx_msb_r5;
|
||||
pha_indx_msb_r7<=pha_indx_msb_r6;
|
||||
end
|
||||
|
||||
end
|
||||
assign pha_indx_msb=pha_indx_msb_r7;
|
||||
*/
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,126 @@
|
|||
////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// This confidential and proprietary software may be used only
|
||||
// as authorized by a licensing agreement from Synopsys Inc.
|
||||
// In the event of publication, the following notice is applicable:
|
||||
//
|
||||
// (C) COPYRIGHT 1994 - 2015 SYNOPSYS INC.
|
||||
// ALL RIGHTS RESERVED
|
||||
//
|
||||
// The entire notice above must be reproduced on all authorized
|
||||
// copies.
|
||||
//
|
||||
// AUTHOR: Anatoly Sokhatsky July 10, 1994
|
||||
//
|
||||
// VERSION: Simulation Architecture
|
||||
//
|
||||
// DesignWare_version: 0781642f
|
||||
// DesignWare_release: K-2015.06-DWBB_201506.0
|
||||
//
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
//-----------------------------------------------------------------------------------
|
||||
//
|
||||
// ABSTRACT: Up/Down Counter
|
||||
// parameterizable wordlength (width > 0)
|
||||
// clk - positive edge-triggering clock
|
||||
// reset - asynchronous reset (active low)
|
||||
// data - data load input
|
||||
// cen - counter enable
|
||||
// count - counter state
|
||||
//
|
||||
// MODIFIED : GN Feb. 16th, 1996
|
||||
// changed dw03 to DW03
|
||||
// remove $generic
|
||||
// defined paramter = 8
|
||||
//
|
||||
// RJK June 19, 1997
|
||||
// Corrected faulty tercnt detection mechanism
|
||||
//
|
||||
// Rong Sep. 1999
|
||||
// Add x-handling
|
||||
//
|
||||
// RJK May 17, 2000
|
||||
// Updated to latest coding style to avoid blocking vs.
|
||||
// nonblocking assignment problems (STAR 103980)
|
||||
//-------------------------------------------------------------------------------
|
||||
|
||||
module DW03_updn_ctr (
|
||||
// input ports
|
||||
data, // data used for load operation
|
||||
up_dn, // up/down control input (0=down, 1-up)
|
||||
load, // load operation control input (active low)
|
||||
cen, // count enable control input (active high enable)
|
||||
clk, // clock input
|
||||
reset, // asynchronous reset input (active low)
|
||||
|
||||
// output ports
|
||||
count, // count value output
|
||||
tercnt // terminal count output flag (active high)
|
||||
);
|
||||
|
||||
parameter width = 8;
|
||||
|
||||
// port list declaration in order
|
||||
input [width-1 : 0] data;
|
||||
input up_dn, load, cen, clk, reset;
|
||||
output [width-1 : 0] count;
|
||||
output tercnt;
|
||||
|
||||
// synopsys translate_off
|
||||
|
||||
reg [width-1 : 0] cur_state;
|
||||
wire [width-1 : 0] next_state;
|
||||
|
||||
assign count = cur_state;
|
||||
|
||||
|
||||
always @ (posedge clk or negedge reset) begin : P_clk_registers
|
||||
|
||||
if (reset === 1'b0)
|
||||
cur_state <= {width{1'b0}};
|
||||
|
||||
else begin
|
||||
|
||||
if (reset === 1'b1)
|
||||
cur_state <= next_state;
|
||||
|
||||
else
|
||||
cur_state <= {width{reset ^ reset}};
|
||||
|
||||
end
|
||||
end // P_clk_registers
|
||||
|
||||
|
||||
assign next_state = (load == 1'b0)? data | {width{1'b0}} :
|
||||
( (cen == 1'b0)? cur_state :
|
||||
( (up_dn == 1'b0)? cur_state + {width{1'b1}} :
|
||||
cur_state - {width{1'b1}} ) );
|
||||
|
||||
|
||||
assign tercnt = (up_dn == 1'b0)? ( (cur_state == {width{1'b0}})? 1'b1 : 1'b0 ) :
|
||||
( (cur_state == {width{1'b1}})? 1'b1 : 1'b0 );
|
||||
|
||||
|
||||
|
||||
initial begin : parameter_check
|
||||
|
||||
|
||||
if ( width < 1 ) begin
|
||||
$display(
|
||||
"ERROR: %m :\n Invalid value (%d) for parameter width (lower bound: 1 )",
|
||||
width );
|
||||
$finish;
|
||||
end
|
||||
|
||||
end // parameter_check
|
||||
|
||||
|
||||
always @ (clk) begin : P_monitor_clk
|
||||
if ( (clk !== 1'b0) && (clk !== 1'b1) && ($time > 0) )
|
||||
$display( "WARNING: %m :\n at time = %t, detected unknown value, %b, on clk input.",
|
||||
$time, clk );
|
||||
end // P_monitor_clk
|
||||
|
||||
// synopsys translate_on
|
||||
|
||||
endmodule // DW03_updn_ctr
|
||||
|
|
@ -0,0 +1,819 @@
|
|||
//+FHDR--------------------------------------------------------------------------------------------------------
|
||||
// Company:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// File Name : mcu_regfile.v
|
||||
// Department :
|
||||
// Author : PWY
|
||||
// Author's Tel :
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Relese History
|
||||
// Version Date Author Description
|
||||
// 0.1 2024-03-13 PWY MCU dedicated register file
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Keywords :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Parameter
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Purpose :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Target Device:
|
||||
// Tool versions:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Reuse Issues
|
||||
// Reset Strategy:
|
||||
// Clock Domains:
|
||||
// Critical Timing:
|
||||
// Asynchronous I/F:
|
||||
// Synthesizable (y/n):
|
||||
// Other:
|
||||
//-FHDR--------------------------------------------------------------------------------------------------------
|
||||
|
||||
// -----------------------------------------------------------
|
||||
// -- Register address offset macros
|
||||
// -----------------------------------------------------------
|
||||
//MCU parameter register 0
|
||||
`define MCUPARAR0 16'h00
|
||||
//MCU parameter register 1
|
||||
`define MCUPARAR1 16'h04
|
||||
//MCU parameter register 2
|
||||
`define MCUPARAR2 16'h08
|
||||
//MCU parameter register 3
|
||||
`define MCUPARAR3 16'h0C
|
||||
//MCU result register 0
|
||||
`define MCURESR0 16'h10
|
||||
//MCU result register 1
|
||||
`define MCURESR1 16'h14
|
||||
//MCU result register 2
|
||||
`define MCURESR2 16'h18
|
||||
//MCU result register 3
|
||||
`define MCURESR3 16'h1C
|
||||
//carrier frequency register 0
|
||||
`define CWFR0 16'h40
|
||||
//carrier frequency register 1
|
||||
`define CWFR1 16'h44
|
||||
//carrier frequency register 2
|
||||
`define CWFR2 16'h48
|
||||
//carrier frequency register 3
|
||||
`define CWFR3 16'h4C
|
||||
//carrier phase zeroing register
|
||||
`define CWPRR 16'h50
|
||||
//Gate-attached phase register 0
|
||||
`define GAPR0 16'h54
|
||||
//Gate-attached phase register 1
|
||||
`define GAPR1 16'h58
|
||||
//Gate-attached phase register 2
|
||||
`define GAPR2 16'h5C
|
||||
//Gate-attached phase register 3
|
||||
`define GAPR3 16'h60
|
||||
//Gate-attached phase register 4
|
||||
`define GAPR4 16'h64
|
||||
//Gate-attached phase register 5
|
||||
`define GAPR5 16'h68
|
||||
//Gate-attached phase register 6
|
||||
`define GAPR6 16'h6C
|
||||
//Gate-attached phase register 7
|
||||
`define GAPR7 16'h70
|
||||
//Line correction phase register
|
||||
`define LCPR 16'h74
|
||||
//Amplitude register 0
|
||||
`define AMPR0 16'h78
|
||||
//Amplitude register 1
|
||||
`define AMPR1 16'h7C
|
||||
//Amplitude register 2
|
||||
`define AMPR2 16'h80
|
||||
//Amplitude register 3
|
||||
`define AMPR3 16'h84
|
||||
//Bias Register 0
|
||||
`define BIASR0 16'h88
|
||||
//Bias Register 1
|
||||
`define BIASR1 16'h8C
|
||||
//Bias Register 2
|
||||
`define BIASR2 16'h90
|
||||
//Bias Register 3
|
||||
`define BIASR3 16'h94
|
||||
//Run-time register
|
||||
`define RTIMR 16'h98
|
||||
//Instruction count register
|
||||
`define ICNTR 16'h9C
|
||||
//Feedback state information register
|
||||
`define FSIR 16'hA0
|
||||
|
||||
module mcu_regfile (
|
||||
//system port
|
||||
input clk // System Main Clock
|
||||
,input rst_n // Spi Reset active low
|
||||
//rw op port
|
||||
,input [31 :0] wrdata // write data
|
||||
,input wren // write enable
|
||||
,input [3 :0] wrmask
|
||||
,input [15 :0] rwaddr // read & write address
|
||||
,input rden // read enable
|
||||
,output [31 :0] rddata // read data
|
||||
,input [1 :0] fb_st_info
|
||||
,input [31 :0] run_time
|
||||
,input [31 :0] instr_num
|
||||
//MCU and SPI interface for interaction
|
||||
,input [31 :0] mcu_param [3:0] // MCU parameter 0~3
|
||||
,output [31 :0] mcu_result [3:0] // MCU result 0~3
|
||||
//lookup table data
|
||||
,output [31 :0] mcu_cwfr [3:0] // Carrier frequency ctrl word 0~3
|
||||
,output [15 :0] mcu_gapr [7:0] // Carrier phase ctrl word 0~3
|
||||
,output [15 :0] mcu_ampr [3:0] // Carrier Amplitude 0~3
|
||||
,output [15 :0] mcu_baisr [3:0] // Carrier Bais 0~3
|
||||
//CFG Port
|
||||
,output mcu_nco_pha_clr
|
||||
,output [15 :0] mcu_rz_pha
|
||||
);
|
||||
|
||||
localparam L = 1'b0,
|
||||
H = 1'b1;
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- Register enable (select) wires
|
||||
// ------------------------------------------------------
|
||||
wire mcuparar0en ; // MCUPARAR0 select
|
||||
wire mcuparar1en ; // MCUPARAR1 select
|
||||
wire mcuparar2en ; // MCUPARAR2 select
|
||||
wire mcuparar3en ; // MCUPARAR3 select
|
||||
wire mcuresr0en ; // MCURESR0 select
|
||||
wire mcuresr1en ; // MCURESR1 select
|
||||
wire mcuresr2en ; // MCURESR2 select
|
||||
wire mcuresr3en ; // MCURESR3 select
|
||||
wire cwfr0en ; // CWFR0 select
|
||||
wire cwfr1en ; // CWFR1 select
|
||||
wire cwfr2en ; // CWFR2 select
|
||||
wire cwfr3en ; // CWFR3 select
|
||||
wire cwprren ; // CWPRR select
|
||||
wire gapr0en ; // GAPR0 select
|
||||
wire gapr1en ; // GAPR1 select
|
||||
wire gapr2en ; // GAPR2 select
|
||||
wire gapr3en ; // GAPR3 select
|
||||
wire gapr4en ; // GAPR4 select
|
||||
wire gapr5en ; // GAPR5 select
|
||||
wire gapr6en ; // GAPR6 select
|
||||
wire gapr7en ; // GAPR7 select
|
||||
wire lcpren ; // LCPR select
|
||||
wire ampr0en ; // AMPR0 select
|
||||
wire ampr1en ; // AMPR1 select
|
||||
wire ampr2en ; // AMPR2 select
|
||||
wire ampr3en ; // AMPR3 select
|
||||
wire baisr0en ; // BIASR0 select
|
||||
wire baisr1en ; // BIASR1 select
|
||||
wire baisr2en ; // BIASR2 select
|
||||
wire baisr3en ; // BIASR3 select
|
||||
wire rtimren ; // RTIMR select
|
||||
wire icntren ; // ICNTR select
|
||||
wire fsiren ; // FSIR select
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- Register write enable wires
|
||||
// ------------------------------------------------------
|
||||
wire mcuresr0we ; // MCURESR0 write enable
|
||||
wire mcuresr1we ; // MCURESR1 write enable
|
||||
wire mcuresr2we ; // MCURESR2 write enable
|
||||
wire mcuresr3we ; // MCURESR3 write enable
|
||||
wire cwfr0we ; // CWFR0 write enable
|
||||
wire cwfr1we ; // CWFR1 write enable
|
||||
wire cwfr2we ; // CWFR2 write enable
|
||||
wire cwfr3we ; // CWFR3 write enable
|
||||
wire cwprrwe ; // CWPRR write enable
|
||||
wire gapr0we ; // GAPR0 write enable
|
||||
wire gapr1we ; // GAPR1 write enable
|
||||
wire gapr2we ; // GAPR2 write enable
|
||||
wire gapr3we ; // GAPR3 write enable
|
||||
wire gapr4we ; // GAPR4 write enable
|
||||
wire gapr5we ; // GAPR5 write enable
|
||||
wire gapr6we ; // GAPR6 write enable
|
||||
wire gapr7we ; // GAPR7 write enable
|
||||
wire lcprwe ; // LCPR write enable
|
||||
wire ampr0we ; // AMPR0 write enable
|
||||
wire ampr1we ; // AMPR1 write enable
|
||||
wire ampr2we ; // AMPR2 write enable
|
||||
wire ampr3we ; // AMPR3 write enable
|
||||
wire baisr0we ; // BIASR0 write enable
|
||||
wire baisr1we ; // BIASR1 write enable
|
||||
wire baisr2we ; // BIASR2 write enable
|
||||
wire baisr3we ; // BIASR3 write enable
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- Misc wires
|
||||
// ------------------------------------------------------
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- Misc Registers
|
||||
// ------------------------------------------------------
|
||||
wire [31 :0] mcuparar0 ; // MCUPARAR0 register
|
||||
wire [31 :0] mcuparar1 ; // MCUPARAR1 register
|
||||
wire [31 :0] mcuparar2 ; // MCUPARAR2 register
|
||||
wire [31 :0] mcuparar3 ; // MCUPARAR3 register
|
||||
wire [31 :0] mcuresr0 ; // MCURESR0 register
|
||||
wire [31 :0] mcuresr1 ; // MCURESR1 register
|
||||
wire [31 :0] mcuresr2 ; // MCURESR2 register
|
||||
wire [31 :0] mcuresr3 ; // MCURESR3 register
|
||||
wire [31 :0] cwfr0 ; // CWFR0 register
|
||||
wire [31 :0] cwfr1 ; // CWFR1 register
|
||||
wire [31 :0] cwfr2 ; // CWFR2 register
|
||||
wire [31 :0] cwfr3 ; // CWFR3 register
|
||||
wire [0 :0] cwprr ; // CWPRR register
|
||||
wire [15 :0] gapr0 ; // GAPR0 register////////////////////16bit but assign to 31:16?
|
||||
wire [15 :0] gapr1 ; // GAPR1 register
|
||||
wire [15 :0] gapr2 ; // GAPR2 register
|
||||
wire [15 :0] gapr3 ; // GAPR3 register
|
||||
wire [15 :0] gapr4 ; // GAPR4 register
|
||||
wire [15 :0] gapr5 ; // GAPR5 register
|
||||
wire [15 :0] gapr6 ; // GAPR6 register
|
||||
wire [15 :0] gapr7 ; // GAPR7 register
|
||||
wire [15 :0] lcpr ; // LCPR register
|
||||
wire [15 :0] ampr0 ; // AMPR0 register
|
||||
wire [15 :0] ampr1 ; // AMPR1 register
|
||||
wire [15 :0] ampr2 ; // AMPR2 register
|
||||
wire [15 :0] ampr3 ; // AMPR3 register
|
||||
wire [15 :0] baisr0 ; // BIASR0 register
|
||||
wire [15 :0] baisr1 ; // BIASR1 register
|
||||
wire [15 :0] baisr2 ; // BIASR2 register
|
||||
wire [15 :0] baisr3 ; // BIASR3 register
|
||||
wire [31 :0] rtimr ; // RTIMR register
|
||||
wire [31 :0] icntr ; // ICNTR register
|
||||
wire [1 :0] fsir ; // FSIR register
|
||||
|
||||
reg [31: 0] rddata_reg ;
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- Address decoder
|
||||
//
|
||||
// Decodes the register address offset input(reg_addr)
|
||||
// to produce enable (select) signals for each of the
|
||||
// SW-registers in the macrocell. The reg_addr input
|
||||
// is bits [15:0] of the paddr bus.
|
||||
// ------------------------------------------------------
|
||||
assign mcuparar0en = (rwaddr[15:2] == `MCUPARAR0 >> 2) ? 1'b1 : 1'b0;
|
||||
assign mcuparar1en = (rwaddr[15:2] == `MCUPARAR1 >> 2) ? 1'b1 : 1'b0;
|
||||
assign mcuparar2en = (rwaddr[15:2] == `MCUPARAR2 >> 2) ? 1'b1 : 1'b0;
|
||||
assign mcuparar3en = (rwaddr[15:2] == `MCUPARAR3 >> 2) ? 1'b1 : 1'b0;
|
||||
assign mcuresr0en = (rwaddr[15:2] == `MCURESR0 >> 2) ? 1'b1 : 1'b0;
|
||||
assign mcuresr1en = (rwaddr[15:2] == `MCURESR1 >> 2) ? 1'b1 : 1'b0;
|
||||
assign mcuresr2en = (rwaddr[15:2] == `MCURESR2 >> 2) ? 1'b1 : 1'b0;
|
||||
assign mcuresr3en = (rwaddr[15:2] == `MCURESR3 >> 2) ? 1'b1 : 1'b0;
|
||||
assign cwfr0en = (rwaddr[15:2] == `CWFR0 >> 2) ? 1'b1 : 1'b0;
|
||||
assign cwfr1en = (rwaddr[15:2] == `CWFR1 >> 2) ? 1'b1 : 1'b0;
|
||||
assign cwfr2en = (rwaddr[15:2] == `CWFR2 >> 2) ? 1'b1 : 1'b0;
|
||||
assign cwfr3en = (rwaddr[15:2] == `CWFR3 >> 2) ? 1'b1 : 1'b0;
|
||||
assign cwprren = (rwaddr[15:2] == `CWPRR >> 2) ? 1'b1 : 1'b0;
|
||||
assign gapr0en = (rwaddr[15:2] == `GAPR0 >> 2) ? 1'b1 : 1'b0;
|
||||
assign gapr1en = (rwaddr[15:2] == `GAPR1 >> 2) ? 1'b1 : 1'b0;
|
||||
assign gapr2en = (rwaddr[15:2] == `GAPR2 >> 2) ? 1'b1 : 1'b0;
|
||||
assign gapr3en = (rwaddr[15:2] == `GAPR3 >> 2) ? 1'b1 : 1'b0;
|
||||
assign gapr4en = (rwaddr[15:2] == `GAPR4 >> 2) ? 1'b1 : 1'b0;
|
||||
assign gapr5en = (rwaddr[15:2] == `GAPR5 >> 2) ? 1'b1 : 1'b0;
|
||||
assign gapr6en = (rwaddr[15:2] == `GAPR6 >> 2) ? 1'b1 : 1'b0;
|
||||
assign gapr7en = (rwaddr[15:2] == `GAPR7 >> 2) ? 1'b1 : 1'b0;
|
||||
assign lcpren = (rwaddr[15:2] == `LCPR >> 2) ? 1'b1 : 1'b0;
|
||||
assign ampr0en = (rwaddr[15:2] == `AMPR0 >> 2) ? 1'b1 : 1'b0;
|
||||
assign ampr1en = (rwaddr[15:2] == `AMPR1 >> 2) ? 1'b1 : 1'b0;
|
||||
assign ampr2en = (rwaddr[15:2] == `AMPR2 >> 2) ? 1'b1 : 1'b0;
|
||||
assign ampr3en = (rwaddr[15:2] == `AMPR3 >> 2) ? 1'b1 : 1'b0;
|
||||
assign baisr0en = (rwaddr[15:2] == `BIASR0 >> 2) ? 1'b1 : 1'b0;
|
||||
assign baisr1en = (rwaddr[15:2] == `BIASR1 >> 2) ? 1'b1 : 1'b0;
|
||||
assign baisr2en = (rwaddr[15:2] == `BIASR2 >> 2) ? 1'b1 : 1'b0;
|
||||
assign baisr3en = (rwaddr[15:2] == `BIASR3 >> 2) ? 1'b1 : 1'b0;
|
||||
assign rtimren = (rwaddr[15:2] == `RTIMR >> 2) ? 1'b1 : 1'b0;
|
||||
assign icntren = (rwaddr[15:2] == `ICNTR >> 2) ? 1'b1 : 1'b0;
|
||||
assign fsiren = (rwaddr[15:2] == `FSIR >> 2) ? 1'b1 : 1'b0;
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- Write enable signals
|
||||
//
|
||||
// Write enable signals for writable SW-registers.
|
||||
// The write enable for each register is the ANDed
|
||||
// result of the register enable and the input reg_wren
|
||||
// ------------------------------------------------------
|
||||
assign mcuresr0we = mcuresr0en & wren;
|
||||
assign mcuresr1we = mcuresr1en & wren;
|
||||
assign mcuresr2we = mcuresr2en & wren;
|
||||
assign mcuresr3we = mcuresr3en & wren;
|
||||
assign cwfr0we = cwfr0en & wren;
|
||||
assign cwfr1we = cwfr1en & wren;
|
||||
assign cwfr2we = cwfr2en & wren;
|
||||
assign cwfr3we = cwfr3en & wren;
|
||||
assign cwprrwe = cwprren & wren;
|
||||
assign gapr0we = gapr0en & wren;
|
||||
assign gapr1we = gapr1en & wren;
|
||||
assign gapr2we = gapr2en & wren;
|
||||
assign gapr3we = gapr3en & wren;
|
||||
assign gapr4we = gapr4en & wren;
|
||||
assign gapr5we = gapr5en & wren;
|
||||
assign gapr6we = gapr6en & wren;
|
||||
assign gapr7we = gapr7en & wren;
|
||||
assign lcprwe = lcpren & wren;
|
||||
assign ampr0we = ampr0en & wren;
|
||||
assign ampr1we = ampr1en & wren;
|
||||
assign ampr2we = ampr2en & wren;
|
||||
assign ampr3we = ampr3en & wren;
|
||||
assign baisr0we = baisr0en & wren;
|
||||
assign baisr1we = baisr1en & wren;
|
||||
assign baisr2we = baisr2en & wren;
|
||||
assign baisr3we = baisr3en & wren;
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- mcuresr0 register
|
||||
//
|
||||
// Write mcuresr0 for 'MCURESR0' : 32-bit register
|
||||
// Register is split into the following bit fields
|
||||
//
|
||||
// [31:0] --> mcuresr0
|
||||
// ------------------------------------------------------
|
||||
wire [31:0] mcuresr0_w;
|
||||
assign mcuresr0_w[31:24] = wrmask[3] ? wrdata[31:24] : mcuresr0[31:24];
|
||||
assign mcuresr0_w[23:16] = wrmask[2] ? wrdata[23:16] : mcuresr0[23:16];
|
||||
assign mcuresr0_w[15 :8] = wrmask[1] ? wrdata[15 :8] : mcuresr0[15 :8];
|
||||
assign mcuresr0_w[7 :0] = wrmask[0] ? wrdata[7 :0] : mcuresr0[7 :0];
|
||||
sirv_gnrl_dfflr #(32) mcuresr0_dfflr (mcuresr0we, mcuresr0_w[31:0], mcuresr0, clk, rst_n);
|
||||
// ------------------------------------------------------
|
||||
// -- mcuresr1 register
|
||||
//
|
||||
// Write mcuresr1 for 'MCURESR1' : 32-bit register
|
||||
// Register is split into the following bit fields
|
||||
//
|
||||
// [31:0] --> mcuresr1
|
||||
// ------------------------------------------------------
|
||||
wire [31:0] mcuresr1_w;
|
||||
assign mcuresr1_w[31:24] = wrmask[3] ? wrdata[31:24] : mcuresr1[31:24];
|
||||
assign mcuresr1_w[23:16] = wrmask[2] ? wrdata[23:16] : mcuresr1[23:16];
|
||||
assign mcuresr1_w[15 :8] = wrmask[1] ? wrdata[15 :8] : mcuresr1[15 :8];
|
||||
assign mcuresr1_w[7 :0] = wrmask[0] ? wrdata[7 :0] : mcuresr1[7 :0];
|
||||
sirv_gnrl_dfflr #(32) mcuresr1_dfflr (mcuresr1we, mcuresr1_w[31:0], mcuresr1, clk, rst_n);
|
||||
// ------------------------------------------------------
|
||||
// -- mcuresr2 register
|
||||
//
|
||||
// Write mcuresr2 for 'MCURESR2' : 32-bit register
|
||||
// Register is split into the following bit fields
|
||||
//
|
||||
// [31:0] --> mcuresr2
|
||||
// ------------------------------------------------------
|
||||
wire [31:0] mcuresr2_w;
|
||||
assign mcuresr2_w[31:24] = wrmask[3] ? wrdata[31:24] : mcuresr2[31:24];
|
||||
assign mcuresr2_w[23:16] = wrmask[2] ? wrdata[23:16] : mcuresr2[23:16];
|
||||
assign mcuresr2_w[15 :8] = wrmask[1] ? wrdata[15 :8] : mcuresr2[15 :8];
|
||||
assign mcuresr2_w[7 :0] = wrmask[0] ? wrdata[7 :0] : mcuresr2[7 :0];
|
||||
sirv_gnrl_dfflr #(32) mcuresr2_dfflr (mcuresr2we, mcuresr2_w[31:0], mcuresr2, clk, rst_n);
|
||||
// ------------------------------------------------------
|
||||
// -- mcuresr3 register
|
||||
//
|
||||
// Write mcuresr3 for 'MCURESR3' : 32-bit register
|
||||
// Register is split into the following bit fields
|
||||
//
|
||||
// [31:0] --> mcuresr3
|
||||
// ------------------------------------------------------
|
||||
wire [31:0] mcuresr3_w;
|
||||
assign mcuresr3_w[31:24] = wrmask[3] ? wrdata[31:24] : mcuresr3[31:24];
|
||||
assign mcuresr3_w[23:16] = wrmask[2] ? wrdata[23:16] : mcuresr3[23:16];
|
||||
assign mcuresr3_w[15 :8] = wrmask[1] ? wrdata[15 :8] : mcuresr3[15 :8];
|
||||
assign mcuresr3_w[7 :0] = wrmask[0] ? wrdata[7 :0] : mcuresr3[7 :0];
|
||||
sirv_gnrl_dfflr #(32) mcuresr3_dfflr (mcuresr3we, mcuresr3_w[31:0], mcuresr3, clk, rst_n);
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- cwfr0 register
|
||||
//
|
||||
// Write cwfr0 for 'CWFR0' : 32-bit register
|
||||
// Register is split into the following bit fields
|
||||
//
|
||||
// [31:0] --> cwfr0
|
||||
// ------------------------------------------------------
|
||||
wire [31:0] cwfr0_w;
|
||||
assign cwfr0_w[31:24] = wrmask[3] ? wrdata[31:24] : cwfr0[31:24];
|
||||
assign cwfr0_w[23:16] = wrmask[2] ? wrdata[23:16] : cwfr0[23:16];
|
||||
assign cwfr0_w[15 :8] = wrmask[1] ? wrdata[15 :8] : cwfr0[15 :8];
|
||||
assign cwfr0_w[7 :0] = wrmask[0] ? wrdata[7 :0] : cwfr0[7 :0];
|
||||
sirv_gnrl_dfflr #(32) cwfr0_dfflr (cwfr0we, cwfr0_w[31:0], cwfr0, clk, rst_n);
|
||||
// ------------------------------------------------------
|
||||
// -- cwfr1 register
|
||||
//
|
||||
// Write cwfr1 for 'CWFR1' : 32-bit register
|
||||
// Register is split into the following bit fields
|
||||
//
|
||||
// [31:16] --> cwfr1
|
||||
// ------------------------------------------------------
|
||||
wire [31:0] cwfr1_w;
|
||||
assign cwfr1_w[31:24] = wrmask[3] ? wrdata[31:24] : cwfr1[31:24];
|
||||
assign cwfr1_w[23:16] = wrmask[2] ? wrdata[23:16] : cwfr1[23:16];
|
||||
assign cwfr1_w[15 :8] = wrmask[1] ? wrdata[15 :8] : cwfr1[15 :8];
|
||||
assign cwfr1_w[7 :0] = wrmask[0] ? wrdata[7 :0] : cwfr1[7 :0];
|
||||
sirv_gnrl_dfflr #(32) cwfr1_dfflr (cwfr1we, cwfr1_w[31:0], cwfr1, clk, rst_n);
|
||||
// ------------------------------------------------------
|
||||
// -- cwfr2 register
|
||||
//
|
||||
// Write cwfr2 for 'CWFR2' : 32-bit register
|
||||
// Register is split into the following bit fields
|
||||
//
|
||||
// [31:16] --> cwfr2
|
||||
// ------------------------------------------------------
|
||||
wire [31:0] cwfr2_w;
|
||||
assign cwfr2_w[31:24] = wrmask[3] ? wrdata[31:24] : cwfr2[31:24];
|
||||
assign cwfr2_w[23:16] = wrmask[2] ? wrdata[23:16] : cwfr2[23:16];
|
||||
assign cwfr2_w[15 :8] = wrmask[1] ? wrdata[15 :8] : cwfr2[15 :8];
|
||||
assign cwfr2_w[7 :0] = wrmask[0] ? wrdata[7 :0] : cwfr2[7 :0];
|
||||
sirv_gnrl_dfflr #(32) cwfr2_dfflr (cwfr2we, cwfr2_w[31:0], cwfr2, clk, rst_n);
|
||||
// ------------------------------------------------------
|
||||
// -- cwfr3 register
|
||||
//
|
||||
// Write cwfr3 for 'CWFR3' : 32-bit register
|
||||
// Register is split into the following bit fields
|
||||
//
|
||||
// [31:16] --> cwfr3
|
||||
// ------------------------------------------------------
|
||||
wire [31:0] cwfr3_w;
|
||||
assign cwfr3_w[31:24] = wrmask[3] ? wrdata[31:24] : cwfr3[31:24];
|
||||
assign cwfr3_w[23:16] = wrmask[2] ? wrdata[23:16] : cwfr3[23:16];
|
||||
assign cwfr3_w[15 :8] = wrmask[1] ? wrdata[15 :8] : cwfr3[15 :8];
|
||||
assign cwfr3_w[7 :0] = wrmask[0] ? wrdata[7 :0] : cwfr3[7 :0];
|
||||
sirv_gnrl_dfflr #(32) cwfr3_dfflr (cwfr3we, cwfr3_w[31:0], cwfr3, clk, rst_n);
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- cwprr register(self-clearing)
|
||||
//
|
||||
// Write cwprr for 'CWPRR' : 32-bit register
|
||||
// Register is split into the following bit fields
|
||||
//
|
||||
// [0] --> cwprr
|
||||
// ------------------------------------------------------
|
||||
wire cwprr_w = wrmask[0] & cwprrwe & wrdata[0];
|
||||
|
||||
sirv_gnrl_dffr #(1) cwprr_dffr (cwprr_w, cwprr, clk, rst_n);
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- gapr0 register
|
||||
//
|
||||
// Write gapr0 for 'GAPR0' : 32-bit register
|
||||
// Register is split into the following bit fields
|
||||
//
|
||||
// [31:16] --> gapr0
|
||||
// ------------------------------------------------------
|
||||
wire [31:0] gapr0_w;
|
||||
assign gapr0_w[31:24] = wrmask[3] ? wrdata[31:24] : gapr0[15: 8];/////////////////////////////////////////////////////////////31:26->15:8
|
||||
assign gapr0_w[23:16] = wrmask[2] ? wrdata[23:16] : gapr0[ 7: 0];/////////////////////////////////////////////////////////////23:16->7:0
|
||||
sirv_gnrl_dfflr #(16) gapr0_dfflr (gapr0we, gapr0_w[31:16], gapr0, clk, rst_n);
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- gapr1 register
|
||||
//
|
||||
// Write gapr1 for 'GAPR1' : 32-bit register
|
||||
// Register is split into the following bit fields
|
||||
//
|
||||
// [31:16] --> gapr1
|
||||
// ------------------------------------------------------
|
||||
wire [31:0] gapr1_w;
|
||||
assign gapr1_w[31:24] = wrmask[3] ? wrdata[31:24] : gapr1[15: 8];/////////////////////////////////////////////////////////////
|
||||
assign gapr1_w[23:16] = wrmask[2] ? wrdata[23:16] : gapr1[ 7: 0];/////////////////////////////////////////////////////////////
|
||||
sirv_gnrl_dfflr #(16) gapr1_dfflr (gapr1we, gapr1_w[31:16], gapr1, clk, rst_n);
|
||||
// ------------------------------------------------------
|
||||
// -- gapr2 register
|
||||
//
|
||||
// Write gapr2 for 'GAPR2' : 32-bit register
|
||||
// Register is split into the following bit fields
|
||||
//
|
||||
// [31:16] --> gapr2
|
||||
// ------------------------------------------------------
|
||||
wire [31:0] gapr2_w;
|
||||
assign gapr2_w[31:24] = wrmask[3] ? wrdata[31:24] : gapr2[15: 8];/////////////////////////////////////////////////////////////
|
||||
assign gapr2_w[23:16] = wrmask[2] ? wrdata[23:16] : gapr2[ 7: 0];/////////////////////////////////////////////////////////////
|
||||
sirv_gnrl_dfflr #(16) gapr2_dfflr (gapr2we, gapr2_w[31:16], gapr2, clk, rst_n);
|
||||
// ------------------------------------------------------
|
||||
// -- gapr3 register
|
||||
//
|
||||
// Write gapr3 for 'GAPR3' : 32-bit register
|
||||
// Register is split into the following bit fields
|
||||
//
|
||||
// [31:16] --> gapr3
|
||||
// ------------------------------------------------------
|
||||
wire [31:0] gapr3_w;
|
||||
assign gapr3_w[31:24] = wrmask[3] ? wrdata[31:24] : gapr3[15: 8];/////////////////////////////////////////////////////////////
|
||||
assign gapr3_w[23:16] = wrmask[2] ? wrdata[23:16] : gapr3[ 7: 0];/////////////////////////////////////////////////////////////
|
||||
sirv_gnrl_dfflr #(16) gapr3_dfflr (gapr3we, gapr3_w[31:16], gapr3, clk, rst_n);
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- gapr4 register
|
||||
//
|
||||
// Write gapr4 for 'GAPR4' : 32-bit register
|
||||
// Register is split into the following bit fields
|
||||
//
|
||||
// [31:16] --> gapr4
|
||||
// ------------------------------------------------------
|
||||
wire [31:0] gapr4_w;
|
||||
assign gapr4_w[31:24] = wrmask[3] ? wrdata[31:24] : gapr4[15: 8];/////////////////////////////////////////////////////////////
|
||||
assign gapr4_w[23:16] = wrmask[2] ? wrdata[23:16] : gapr4[ 7: 0];/////////////////////////////////////////////////////////////
|
||||
sirv_gnrl_dfflr #(16) gapr4_dfflr (gapr4we, gapr4_w[31:16], gapr4, clk, rst_n);
|
||||
// ------------------------------------------------------
|
||||
// -- gapr5 register
|
||||
//
|
||||
// Write gapr5 for 'GAPR5' : 32-bit register
|
||||
// Register is split into the following bit fields
|
||||
//
|
||||
// [31:16] --> gapr5
|
||||
// ------------------------------------------------------
|
||||
wire [31:0] gapr5_w;
|
||||
assign gapr5_w[31:24] = wrmask[3] ? wrdata[31:24] : gapr5[15: 8];/////////////////////////////////////////////////////////////
|
||||
assign gapr5_w[23:16] = wrmask[2] ? wrdata[23:16] : gapr5[ 7: 0];/////////////////////////////////////////////////////////////
|
||||
sirv_gnrl_dfflr #(16) gapr5_dfflr (gapr5we, gapr5_w[31:16], gapr5, clk, rst_n);
|
||||
// ------------------------------------------------------
|
||||
// -- gapr6 register
|
||||
//
|
||||
// Write gapr6 for 'GAPR6' : 32-bit register
|
||||
// Register is split into the following bit fields
|
||||
//
|
||||
// [31:16] --> gapr6
|
||||
// ------------------------------------------------------
|
||||
wire [31:0] gapr6_w;
|
||||
assign gapr6_w[31:24] = wrmask[3] ? wrdata[31:24] : gapr6[15: 8];/////////////////////////////////////////////////////////////
|
||||
assign gapr6_w[23:16] = wrmask[2] ? wrdata[23:16] : gapr6[ 7: 0];/////////////////////////////////////////////////////////////
|
||||
sirv_gnrl_dfflr #(16) gapr6_dfflr (gapr6we, gapr6_w[31:16], gapr6, clk, rst_n);
|
||||
// ------------------------------------------------------
|
||||
// -- gapr7 register
|
||||
//
|
||||
// Write gapr7 for 'GAPR7' : 32-bit register
|
||||
// Register is split into the following bit fields
|
||||
//
|
||||
// [31:16] --> gapr7
|
||||
// ------------------------------------------------------
|
||||
wire [31:0] gapr7_w;
|
||||
assign gapr7_w[31:24] = wrmask[3] ? wrdata[31:24] : gapr7[15: 8];/////////////////////////////////////////////////////////////
|
||||
assign gapr7_w[23:16] = wrmask[2] ? wrdata[23:16] : gapr7[ 7: 0];/////////////////////////////////////////////////////////////
|
||||
sirv_gnrl_dfflr #(16) gapr7_dfflr (gapr7we, gapr7_w[31:16], gapr7, clk, rst_n);
|
||||
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- lcpr register
|
||||
//
|
||||
// Write lcpr for 'LCPR' : 32-bit register
|
||||
// Register is split into the following bit fields
|
||||
//
|
||||
// [31:16] --> lcpr
|
||||
// ------------------------------------------------------
|
||||
wire [31:0] lcpr_w;
|
||||
assign lcpr_w[31:24] = wrmask[3] ? wrdata[31:24] : lcpr[15: 8];/////////////////////////////////////////////////////////////
|
||||
assign lcpr_w[23:16] = wrmask[2] ? wrdata[23:16] : lcpr[ 7: 0];/////////////////////////////////////////////////////////////
|
||||
sirv_gnrl_dfflr #(16) lcpr_dfflr (lcprwe, lcpr_w[31:16], lcpr, clk, rst_n);
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- ampr0 register
|
||||
//
|
||||
// Write ampr0 for 'AMPR0' : 32-bit register
|
||||
// Register is split into the following bit fields
|
||||
//
|
||||
// [31:16] --> ampr0
|
||||
// ------------------------------------------------------
|
||||
wire [31:0] ampr0_w;
|
||||
assign ampr0_w[31:24] = wrmask[3] ? wrdata[31:24] : ampr0[15: 8];/////////////////////////////////////////////////////////////
|
||||
assign ampr0_w[23:16] = wrmask[2] ? wrdata[23:16] : ampr0[ 7: 0];/////////////////////////////////////////////////////////////
|
||||
sirv_gnrl_dfflr #(16) ampr0_dfflr (ampr0we, ampr0_w[31:16], ampr0, clk, rst_n);
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- ampr1 register
|
||||
//
|
||||
// Write ampr1 for 'AMPR10' : 32-bit register
|
||||
// Register is split into the following bit fields
|
||||
//
|
||||
// [31:16] --> ampr1
|
||||
// ------------------------------------------------------
|
||||
wire [31:0] ampr1_w;
|
||||
assign ampr1_w[31:24] = wrmask[3] ? wrdata[31:24] : ampr1[15: 8];/////////////////////////////////////////////////////////////
|
||||
assign ampr1_w[23:16] = wrmask[2] ? wrdata[23:16] : ampr1[ 7: 0];/////////////////////////////////////////////////////////////
|
||||
sirv_gnrl_dfflr #(16) ampr1_dfflr (ampr1we, ampr1_w[31:16], ampr1, clk, rst_n);
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- ampr2 register
|
||||
//
|
||||
// Write ampr2 for 'AMPR2' : 32-bit register
|
||||
// Register is split into the following bit fields
|
||||
//
|
||||
// [31:16] --> ampr2
|
||||
// ------------------------------------------------------
|
||||
wire [31:0] ampr2_w;
|
||||
assign ampr2_w[31:24] = wrmask[3] ? wrdata[31:24] : ampr2[15: 8];/////////////////////////////////////////////////////////////
|
||||
assign ampr2_w[23:16] = wrmask[2] ? wrdata[23:16] : ampr2[ 7: 0];/////////////////////////////////////////////////////////////
|
||||
sirv_gnrl_dfflr #(16) ampr2_dfflr (ampr2we, ampr2_w[31:16], ampr2, clk, rst_n);
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- ampr3 register
|
||||
//
|
||||
// Write ampr3 for 'AMPR3' : 32-bit register
|
||||
// Register is split into the following bit fields
|
||||
//
|
||||
// [31:16] --> ampr3
|
||||
// ------------------------------------------------------
|
||||
wire [31:0] ampr3_w;
|
||||
assign ampr3_w[31:24] = wrmask[3] ? wrdata[31:24] : ampr3[15: 8];/////////////////////////////////////////////////////////////
|
||||
assign ampr3_w[23:16] = wrmask[2] ? wrdata[23:16] : ampr3[ 7: 0];/////////////////////////////////////////////////////////////
|
||||
sirv_gnrl_dfflr #(16) ampr3_dfflr (ampr3we, ampr3_w[31:16], ampr3, clk, rst_n);
|
||||
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- baisr0 register
|
||||
//
|
||||
// Write baisr0 for 'BIASR0' : 32-bit register
|
||||
// Register is split into the following bit fields
|
||||
//
|
||||
// [31:16] --> baisr0
|
||||
// ------------------------------------------------------
|
||||
wire [31:0] baisr0_w;
|
||||
assign baisr0_w[31:24] = wrmask[3] ? wrdata[31:24] : baisr0[15: 8];/////////////////////////////////////////////////////////////
|
||||
assign baisr0_w[23:16] = wrmask[2] ? wrdata[23:16] : baisr0[ 7: 0];/////////////////////////////////////////////////////////////
|
||||
sirv_gnrl_dfflr #(16) baisr0_dfflr (baisr0we, baisr0_w[31:16], baisr0, clk, rst_n);
|
||||
// ------------------------------------------------------
|
||||
// -- baisr1 register
|
||||
//
|
||||
// Write baisr1 for 'BIASR1' : 32-bit register
|
||||
// Register is split into the following bit fields
|
||||
//
|
||||
// [31:16] --> baisr1
|
||||
// ------------------------------------------------------
|
||||
wire [31:0] baisr1_w;
|
||||
assign baisr1_w[31:24] = wrmask[3] ? wrdata[31:24] : baisr1[15: 8];/////////////////////////////////////////////////////////////
|
||||
assign baisr1_w[23:16] = wrmask[2] ? wrdata[23:16] : baisr1[ 7: 0];/////////////////////////////////////////////////////////////
|
||||
sirv_gnrl_dfflr #(16) baisr1_dfflr (baisr1we, baisr1_w[31:16], baisr1, clk, rst_n);
|
||||
// ------------------------------------------------------
|
||||
// -- baisr2 register
|
||||
//
|
||||
// Write baisr2 for 'BIASR2' : 32-bit register
|
||||
// Register is split into the following bit fields
|
||||
//
|
||||
// [31:16] --> baisr2
|
||||
// ------------------------------------------------------
|
||||
wire [31:0] baisr2_w;
|
||||
assign baisr2_w[31:24] = wrmask[3] ? wrdata[31:24] : baisr2[15: 8];/////////////////////////////////////////////////////////////
|
||||
assign baisr2_w[23:16] = wrmask[2] ? wrdata[23:16] : baisr2[ 7: 0];/////////////////////////////////////////////////////////////
|
||||
sirv_gnrl_dfflr #(16) baisr2_dfflr (baisr2we, baisr2_w[31:16], baisr2, clk, rst_n);
|
||||
// ------------------------------------------------------
|
||||
// -- baisr3 register
|
||||
//
|
||||
// Write baisr3 for 'BIASR3' : 32-bit register
|
||||
// Register is split into the following bit fields
|
||||
//
|
||||
// [31:16] --> baisr3
|
||||
// ------------------------------------------------------
|
||||
wire [31:0] baisr3_w;
|
||||
assign baisr3_w[31:24] = wrmask[3] ? wrdata[31:24] : baisr3[15: 8];/////////////////////////////////////////////////////////////
|
||||
assign baisr3_w[23:16] = wrmask[2] ? wrdata[23:16] : baisr3[ 7: 0];/////////////////////////////////////////////////////////////
|
||||
sirv_gnrl_dfflr #(16) baisr3_dfflr (baisr3we, baisr3_w[31:16], baisr3, clk, rst_n);
|
||||
|
||||
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- mcuparar0
|
||||
// ------------------------------------------------------
|
||||
sirv_gnrl_dffr #(32) mcuparar0_dffr (mcu_param[0], mcuparar0, clk, rst_n);
|
||||
// ------------------------------------------------------
|
||||
// -- mcuparar1
|
||||
// ------------------------------------------------------
|
||||
sirv_gnrl_dffr #(32) mcuparar1_dffr (mcu_param[1], mcuparar1, clk, rst_n);
|
||||
// ------------------------------------------------------
|
||||
// -- mcuparar2
|
||||
// ------------------------------------------------------
|
||||
sirv_gnrl_dffr #(32) mcuparar2_dffr (mcu_param[2], mcuparar2, clk, rst_n);
|
||||
// ------------------------------------------------------
|
||||
// -- mcuparar3
|
||||
// ------------------------------------------------------
|
||||
sirv_gnrl_dffr #(32) mcuparar3_dffr (mcu_param[3], mcuparar3, clk, rst_n);
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- rtimr
|
||||
// ------------------------------------------------------
|
||||
sirv_gnrl_dffr #(32) rtimr_dffr (run_time, rtimr, clk, rst_n);
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- icntr
|
||||
// ------------------------------------------------------
|
||||
sirv_gnrl_dffr #(32) icntr_dffr (instr_num, icntr, clk, rst_n);
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- fsir
|
||||
// ------------------------------------------------------
|
||||
sirv_gnrl_dffr #(2) fsir_dffr (fb_st_info[1:0], fsir, clk, rst_n);////////////////////////////////////////////[1:0]
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- Read data mux
|
||||
//
|
||||
// -- The data from the selected register is
|
||||
// -- placed on a zero-padded 32-bit read data bus.
|
||||
// ------------------------------------------------------
|
||||
always @(*) begin : RDDATA_PROC
|
||||
rddata_reg = {32{1'b0}};
|
||||
if(mcuparar0en == H ) rddata_reg[31 :0] = mcuparar0 ;
|
||||
if(mcuparar1en == H ) rddata_reg[31 :0] = mcuparar1 ;
|
||||
if(mcuparar2en == H ) rddata_reg[31 :0] = mcuparar2 ;
|
||||
if(mcuparar3en == H ) rddata_reg[31 :0] = mcuparar3 ;
|
||||
if(mcuresr0en == H ) rddata_reg[31 :0] = mcuresr0 ;
|
||||
if(mcuresr1en == H ) rddata_reg[31 :0] = mcuresr1 ;
|
||||
if(mcuresr2en == H ) rddata_reg[31 :0] = mcuresr2 ;
|
||||
if(mcuresr3en == H ) rddata_reg[31 :0] = mcuresr3 ;
|
||||
if(cwfr0en == H ) rddata_reg[31 :0] = cwfr0 ;
|
||||
if(cwfr1en == H ) rddata_reg[31 :0] = cwfr1 ;
|
||||
if(cwfr2en == H ) rddata_reg[31 :0] = cwfr2 ;
|
||||
if(cwfr3en == H ) rddata_reg[31 :0] = cwfr3 ;
|
||||
if(cwprren == H ) rddata_reg[0 :0] = cwprr ;
|
||||
if(gapr0en == H ) rddata_reg[31:16] = gapr0 ;
|
||||
if(gapr1en == H ) rddata_reg[31:16] = gapr1 ;
|
||||
if(gapr2en == H ) rddata_reg[31:16] = gapr2 ;
|
||||
if(gapr3en == H ) rddata_reg[31:16] = gapr3 ;
|
||||
if(gapr4en == H ) rddata_reg[31:16] = gapr4 ;
|
||||
if(gapr5en == H ) rddata_reg[31:16] = gapr5 ;
|
||||
if(gapr6en == H ) rddata_reg[31:16] = gapr6 ;
|
||||
if(gapr7en == H ) rddata_reg[31:16] = gapr7 ;
|
||||
if(lcpren == H ) rddata_reg[31:16] = lcpr ;
|
||||
if(ampr0en == H ) rddata_reg[31:16] = ampr0 ;
|
||||
if(ampr1en == H ) rddata_reg[31:16] = ampr1 ;
|
||||
if(ampr2en == H ) rddata_reg[31:16] = ampr2 ;
|
||||
if(ampr3en == H ) rddata_reg[31:16] = ampr3 ;
|
||||
if(baisr0en == H ) rddata_reg[31:16] = baisr0 ;
|
||||
if(baisr1en == H ) rddata_reg[31:16] = baisr1 ;
|
||||
if(baisr2en == H ) rddata_reg[31:16] = baisr2 ;
|
||||
if(baisr3en == H ) rddata_reg[31:16] = baisr3 ;
|
||||
if(rtimren == H ) rddata_reg[31 :0] = rtimr ;
|
||||
if(icntren == H ) rddata_reg[31 :0] = icntr ;
|
||||
if(fsiren == H ) rddata_reg[1 :0] = fsir ;
|
||||
end
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- Output signals assignment
|
||||
// ------------------------------------------------------
|
||||
//mcu result
|
||||
assign mcu_result[0] = mcuresr0 ;
|
||||
assign mcu_result[1] = mcuresr1 ;
|
||||
assign mcu_result[2] = mcuresr2 ;
|
||||
assign mcu_result[3] = mcuresr3 ;
|
||||
|
||||
//nco_fwc lookup table output
|
||||
assign mcu_cwfr[0] = cwfr0;
|
||||
assign mcu_cwfr[1] = cwfr1;
|
||||
assign mcu_cwfr[2] = cwfr2;
|
||||
assign mcu_cwfr[3] = cwfr3;
|
||||
|
||||
//nco_pha lookup table output
|
||||
assign mcu_gapr[0] = gapr0; ////////////////////////////////////////////////16bit assign to 32bit(?)
|
||||
assign mcu_gapr[1] = gapr1;
|
||||
assign mcu_gapr[2] = gapr2;
|
||||
assign mcu_gapr[3] = gapr3;
|
||||
assign mcu_gapr[4] = gapr4;
|
||||
assign mcu_gapr[5] = gapr5;
|
||||
assign mcu_gapr[6] = gapr6;
|
||||
assign mcu_gapr[7] = gapr7;
|
||||
|
||||
//amp lookup table output
|
||||
assign mcu_ampr[0] = ampr0;
|
||||
assign mcu_ampr[1] = ampr1;
|
||||
assign mcu_ampr[2] = ampr2;
|
||||
assign mcu_ampr[3] = ampr3;
|
||||
|
||||
//bais lookup table output
|
||||
assign mcu_baisr[0] = baisr0;
|
||||
assign mcu_baisr[1] = baisr1;
|
||||
assign mcu_baisr[2] = baisr2;
|
||||
assign mcu_baisr[3] = baisr3;
|
||||
|
||||
//CFG Port
|
||||
assign mcu_nco_pha_clr = cwprr;
|
||||
assign mcu_rz_pha = lcpr;
|
||||
//rddata
|
||||
//assign rddata = rddata_reg ;
|
||||
sirv_gnrl_dffr #(32) rddata_dffr (rddata_reg, rddata, clk, rst_n);////////////////////////
|
||||
endmodule
|
||||
|
||||
`undef MCUPARAR0
|
||||
`undef MCUPARAR1
|
||||
`undef MCUPARAR2
|
||||
`undef MCUPARAR3
|
||||
`undef MCURESR0
|
||||
`undef MCURESR1
|
||||
`undef MCURESR2
|
||||
`undef MCURESR3
|
||||
`undef CWFR0
|
||||
`undef CWFR1
|
||||
`undef CWFR2
|
||||
`undef CWFR3
|
||||
`undef CWPRR
|
||||
`undef GAPR0
|
||||
`undef GAPR1
|
||||
`undef GAPR2
|
||||
`undef GAPR3
|
||||
`undef GAPR4
|
||||
`undef GAPR5
|
||||
`undef GAPR6
|
||||
`undef GAPR7
|
||||
`undef LCPR
|
||||
`undef AMPR0
|
||||
`undef AMPR1
|
||||
`undef AMPR2
|
||||
`undef AMPR3
|
||||
`undef BIASR0
|
||||
`undef BIASR1
|
||||
`undef BIASR2
|
||||
`undef BIASR3
|
||||
`undef RTIMR
|
||||
`undef ICNTR
|
||||
`undef FSIR
|
||||
|
|
@ -0,0 +1,113 @@
|
|||
//+FHDR--------------------------------------------------------------------------------------------------------
|
||||
// Company:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// File Name : qbmcu_busdecoder.v
|
||||
// Department :
|
||||
// Author : PWY
|
||||
// Author's Tel :
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Relese History
|
||||
// Version Date Author Description
|
||||
// 1.0 2022-08-25 PWY
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Keywords :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Parameter
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Purpose :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Target Device:
|
||||
// Tool versions:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Reuse Issues
|
||||
// Reset Strategy:
|
||||
// Clock Domains:
|
||||
// Critical Timing:
|
||||
// Asynchronous I/F:
|
||||
// Synthesizable (y/n):
|
||||
// Other:
|
||||
//-FHDR--------------------------------------------------------------------------------------------------------
|
||||
|
||||
`include "../qubitmcu/qbmcu_defines.v"
|
||||
|
||||
module qbmcu_busdecoder #(
|
||||
parameter S0_BASEADDR = 32'h0010_0000
|
||||
,parameter S1_BASEADDR = 32'h0020_0000
|
||||
)(
|
||||
//rw op port
|
||||
input wren // write enable
|
||||
,input [`QBMCU_XLEN/8-1 :0] wrmask // write mask
|
||||
,input [`QBMCU_XLEN-1 :0] wrdata // write data
|
||||
,input [`QBMCU_ADDR_SIZE-1:0] rwaddr // read & write addr
|
||||
,input rden // read enable
|
||||
,output [`QBMCU_XLEN-1 :0] rddata // read data
|
||||
//data sram read and write signals
|
||||
,output s0_wren // s0 write enable
|
||||
,output [`QBMCU_XLEN/8-1 :0] s0_wrmask // write mask
|
||||
,output [`QBMCU_ADDR_SIZE-1:0] s0_rwaddr // s0 read & write addr
|
||||
,output [`QBMCU_XLEN-1 :0] s0_wrdata // s0 write data
|
||||
,output s0_rden // s0 read enable
|
||||
,input [`QBMCU_XLEN-1 :0] s0_rddata // s0 read data
|
||||
//mcu perips reg read and write signals
|
||||
,output s1_wren // s1 write enable
|
||||
,output [`QBMCU_XLEN/8-1 :0] s1_wrmask // write mask
|
||||
,output [`QBMCU_ADDR_SIZE-1:0] s1_rwaddr // s1 read & write addr
|
||||
,output [`QBMCU_XLEN-1 :0] s1_wrdata // s1 write data
|
||||
,output s1_rden // s1 read enable
|
||||
,input [`QBMCU_XLEN-1 :0] s1_rddata // s1 read data
|
||||
);
|
||||
|
||||
wire s0_sel;
|
||||
wire s1_sel;
|
||||
|
||||
//s0_sel
|
||||
assign s0_sel = (rwaddr[`QBMCU_ADDR_SIZE-1:16] == S0_BASEADDR >> 16);
|
||||
//s1_sel
|
||||
assign s1_sel = (rwaddr[`QBMCU_ADDR_SIZE-1:16] == S1_BASEADDR >> 16);
|
||||
|
||||
|
||||
//s0_wren
|
||||
assign s0_wren = s0_sel & wren;
|
||||
//s1_wren
|
||||
assign s1_wren = s1_sel & wren;
|
||||
|
||||
//s0_wrmask
|
||||
assign s0_wrmask = {`QBMCU_XLEN/8{s0_sel}} & wrmask;
|
||||
//s1_wrmask
|
||||
assign s1_wrmask = {`QBMCU_XLEN/8{s1_sel}} & wrmask;
|
||||
|
||||
//s0_rden
|
||||
assign s0_rden = s0_sel & rden;
|
||||
//s1_rden
|
||||
assign s1_rden = s1_sel & rden;
|
||||
|
||||
|
||||
//s0_rwaddr
|
||||
assign s0_rwaddr = {`QBMCU_ADDR_SIZE{s0_sel}} & rwaddr;
|
||||
//s1_rwaddr
|
||||
assign s1_rwaddr = {`QBMCU_ADDR_SIZE{s1_sel}} & rwaddr;
|
||||
|
||||
//s0_wrdata
|
||||
assign s0_wrdata = {`QBMCU_XLEN{s0_sel}} & wrdata;
|
||||
//s1_wrdata
|
||||
assign s1_wrdata = {`QBMCU_XLEN{s1_sel}} & wrdata;
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- Read data mux
|
||||
//
|
||||
// -- The data from the selected register is
|
||||
// -- placed on a zero-padded 32-bit read data bus.
|
||||
// ------------------------------------------------------
|
||||
|
||||
wire [`QBMCU_XLEN-1:0] rddata_w = {`QBMCU_XLEN{s0_sel}} & s0_rddata
|
||||
| {`QBMCU_XLEN{s1_sel}} & s1_rddata;
|
||||
|
||||
//rddata
|
||||
assign rddata = rddata_w;
|
||||
|
||||
endmodule
|
||||
|
||||
`include "../qubitmcu/qbmcu_undefines.v"
|
||||
|
|
@ -0,0 +1,840 @@
|
|||
//+FHDR--------------------------------------------------------------------------------------------------------
|
||||
// Company:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// File Name : mcu_regfile.v
|
||||
// Department :
|
||||
// Author : PWY
|
||||
// Author's Tel :
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Relese History
|
||||
// Version Date Author Description
|
||||
// 0.1 2024-03-13 PWY MCU dedicated register file
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Keywords :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Parameter
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Purpose :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Target Device:
|
||||
// Tool versions:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Reuse Issues
|
||||
// Reset Strategy:
|
||||
// Clock Domains:
|
||||
// Critical Timing:
|
||||
// Asynchronous I/F:
|
||||
// Synthesizable (y/n):
|
||||
// Other:
|
||||
//-FHDR--------------------------------------------------------------------------------------------------------
|
||||
|
||||
// -----------------------------------------------------------
|
||||
// -- Register address offset macros
|
||||
// -----------------------------------------------------------
|
||||
//MCU parameter register 0
|
||||
`define MCUPARAR0 16'h00
|
||||
//MCU parameter register 1
|
||||
`define MCUPARAR1 16'h04
|
||||
//MCU parameter register 2
|
||||
`define MCUPARAR2 16'h08
|
||||
//MCU parameter register 3
|
||||
`define MCUPARAR3 16'h0C
|
||||
//MCU result register 0
|
||||
`define MCURESR0 16'h10
|
||||
//MCU result register 1
|
||||
`define MCURESR1 16'h14
|
||||
//MCU result register 2
|
||||
`define MCURESR2 16'h18
|
||||
//MCU result register 3
|
||||
`define MCURESR3 16'h1C
|
||||
//carrier frequency register 0
|
||||
`define CWFR0 16'h40
|
||||
//carrier frequency register 1
|
||||
`define CWFR1 16'h44
|
||||
//carrier frequency register 2
|
||||
`define CWFR2 16'h48
|
||||
//carrier frequency register 3
|
||||
`define CWFR3 16'h4C
|
||||
//carrier phase zeroing register
|
||||
`define CWPRR 16'h50
|
||||
//Gate-attached phase register 0
|
||||
`define GAPR0 16'h54
|
||||
//Gate-attached phase register 1
|
||||
`define GAPR1 16'h58
|
||||
//Gate-attached phase register 2
|
||||
`define GAPR2 16'h5C
|
||||
//Gate-attached phase register 3
|
||||
`define GAPR3 16'h60
|
||||
//Gate-attached phase register 4
|
||||
`define GAPR4 16'h64
|
||||
//Gate-attached phase register 5
|
||||
`define GAPR5 16'h68
|
||||
//Gate-attached phase register 6
|
||||
`define GAPR6 16'h6C
|
||||
//Gate-attached phase register 7
|
||||
`define GAPR7 16'h70
|
||||
//Line correction phase register
|
||||
`define LCPR 16'h74
|
||||
//Amplitude register 0
|
||||
`define AMPR0 16'h78
|
||||
//Amplitude register 1
|
||||
`define AMPR1 16'h7C
|
||||
//Amplitude register 2
|
||||
`define AMPR2 16'h80
|
||||
//Amplitude register 3
|
||||
`define AMPR3 16'h84
|
||||
//Bias Register 0
|
||||
`define BIASR0 16'h88
|
||||
//Bias Register 1
|
||||
`define BIASR1 16'h8C
|
||||
//Bias Register 2
|
||||
`define BIASR2 16'h90
|
||||
//Bias Register 3
|
||||
`define BIASR3 16'h94
|
||||
//Run-time register
|
||||
`define RTIMR 16'h98
|
||||
//Instruction count register
|
||||
`define ICNTR 16'h9C
|
||||
//Feedback state information register
|
||||
`define FSIR 16'hA0
|
||||
//Interpolator Selection Register
|
||||
`define INTPSELR 16'hA4
|
||||
|
||||
module mcu_regfile (
|
||||
//system port
|
||||
input clk // System Main Clock
|
||||
,input rst_n // Spi Reset active low
|
||||
//rw op port
|
||||
,input [31 :0] wrdata // write data
|
||||
,input wren // write enable
|
||||
,input [3 :0] wrmask
|
||||
,input [15 :0] rwaddr // read & write address
|
||||
,input rden // read enable
|
||||
,output [31 :0] rddata // read data
|
||||
,input [1 :0] fb_st_info
|
||||
,input [31 :0] run_time
|
||||
,input [31 :0] instr_num
|
||||
//MCU and SPI interface for interaction
|
||||
,input [31 :0] mcu_param [3:0] // MCU parameter 0~3
|
||||
,output [31 :0] mcu_result [3:0] // MCU result 0~3
|
||||
//lookup table data
|
||||
,output [31 :0] mcu_cwfr [3:0] // Carrier frequency ctrl word 0~3
|
||||
,output [15 :0] mcu_gapr [7:0] // Carrier phase ctrl word 0~3
|
||||
,output [15 :0] mcu_ampr [3:0] // Carrier Amplitude 0~3
|
||||
,output [15 :0] mcu_baisr [3:0] // Carrier Bais 0~3
|
||||
//CFG Port
|
||||
,output [1 :0] mcu_intp_sel //2'b00:HBF;2'b01:Nearest-neighbor interpolator;
|
||||
,output mcu_nco_pha_clr
|
||||
,output [15 :0] mcu_rz_pha
|
||||
);
|
||||
|
||||
localparam L = 1'b0,
|
||||
H = 1'b1;
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- Register enable (select) wires
|
||||
// ------------------------------------------------------
|
||||
wire mcuparar0en ; // MCUPARAR0 select
|
||||
wire mcuparar1en ; // MCUPARAR1 select
|
||||
wire mcuparar2en ; // MCUPARAR2 select
|
||||
wire mcuparar3en ; // MCUPARAR3 select
|
||||
wire mcuresr0en ; // MCURESR0 select
|
||||
wire mcuresr1en ; // MCURESR1 select
|
||||
wire mcuresr2en ; // MCURESR2 select
|
||||
wire mcuresr3en ; // MCURESR3 select
|
||||
wire cwfr0en ; // CWFR0 select
|
||||
wire cwfr1en ; // CWFR1 select
|
||||
wire cwfr2en ; // CWFR2 select
|
||||
wire cwfr3en ; // CWFR3 select
|
||||
wire cwprren ; // CWPRR select
|
||||
wire gapr0en ; // GAPR0 select
|
||||
wire gapr1en ; // GAPR1 select
|
||||
wire gapr2en ; // GAPR2 select
|
||||
wire gapr3en ; // GAPR3 select
|
||||
wire gapr4en ; // GAPR4 select
|
||||
wire gapr5en ; // GAPR5 select
|
||||
wire gapr6en ; // GAPR6 select
|
||||
wire gapr7en ; // GAPR7 select
|
||||
wire lcpren ; // LCPR select
|
||||
wire ampr0en ; // AMPR0 select
|
||||
wire ampr1en ; // AMPR1 select
|
||||
wire ampr2en ; // AMPR2 select
|
||||
wire ampr3en ; // AMPR3 select
|
||||
wire baisr0en ; // BIASR0 select
|
||||
wire baisr1en ; // BIASR1 select
|
||||
wire baisr2en ; // BIASR2 select
|
||||
wire baisr3en ; // BIASR3 select
|
||||
wire rtimren ; // RTIMR select
|
||||
wire icntren ; // ICNTR select
|
||||
wire fsiren ; // FSIR select
|
||||
wire intpselren ; // INTPSELR select
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- Register write enable wires
|
||||
// ------------------------------------------------------
|
||||
wire mcuresr0we ; // MCURESR0 write enable
|
||||
wire mcuresr1we ; // MCURESR1 write enable
|
||||
wire mcuresr2we ; // MCURESR2 write enable
|
||||
wire mcuresr3we ; // MCURESR3 write enable
|
||||
wire cwfr0we ; // CWFR0 write enable
|
||||
wire cwfr1we ; // CWFR1 write enable
|
||||
wire cwfr2we ; // CWFR2 write enable
|
||||
wire cwfr3we ; // CWFR3 write enable
|
||||
wire cwprrwe ; // CWPRR write enable
|
||||
wire gapr0we ; // GAPR0 write enable
|
||||
wire gapr1we ; // GAPR1 write enable
|
||||
wire gapr2we ; // GAPR2 write enable
|
||||
wire gapr3we ; // GAPR3 write enable
|
||||
wire gapr4we ; // GAPR4 write enable
|
||||
wire gapr5we ; // GAPR5 write enable
|
||||
wire gapr6we ; // GAPR6 write enable
|
||||
wire gapr7we ; // GAPR7 write enable
|
||||
wire lcprwe ; // LCPR write enable
|
||||
wire ampr0we ; // AMPR0 write enable
|
||||
wire ampr1we ; // AMPR1 write enable
|
||||
wire ampr2we ; // AMPR2 write enable
|
||||
wire ampr3we ; // AMPR3 write enable
|
||||
wire baisr0we ; // BIASR0 write enable
|
||||
wire baisr1we ; // BIASR1 write enable
|
||||
wire baisr2we ; // BIASR2 write enable
|
||||
wire baisr3we ; // BIASR3 write enable
|
||||
wire intpselrwe ; // INTPSELR select
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- Misc wires
|
||||
// ------------------------------------------------------
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- Misc Registers
|
||||
// ------------------------------------------------------
|
||||
wire [31 :0] mcuparar0 ; // MCUPARAR0 register
|
||||
wire [31 :0] mcuparar1 ; // MCUPARAR1 register
|
||||
wire [31 :0] mcuparar2 ; // MCUPARAR2 register
|
||||
wire [31 :0] mcuparar3 ; // MCUPARAR3 register
|
||||
wire [31 :0] mcuresr0 ; // MCURESR0 register
|
||||
wire [31 :0] mcuresr1 ; // MCURESR1 register
|
||||
wire [31 :0] mcuresr2 ; // MCURESR2 register
|
||||
wire [31 :0] mcuresr3 ; // MCURESR3 register
|
||||
wire [31 :0] cwfr0 ; // CWFR0 register
|
||||
wire [31 :0] cwfr1 ; // CWFR1 register
|
||||
wire [31 :0] cwfr2 ; // CWFR2 register
|
||||
wire [31 :0] cwfr3 ; // CWFR3 register
|
||||
wire [0 :0] cwprr ; // CWPRR register
|
||||
wire [15 :0] gapr0 ; // GAPR0 register////////////////////16bit but assign to 31:16?
|
||||
wire [15 :0] gapr1 ; // GAPR1 register
|
||||
wire [15 :0] gapr2 ; // GAPR2 register
|
||||
wire [15 :0] gapr3 ; // GAPR3 register
|
||||
wire [15 :0] gapr4 ; // GAPR4 register
|
||||
wire [15 :0] gapr5 ; // GAPR5 register
|
||||
wire [15 :0] gapr6 ; // GAPR6 register
|
||||
wire [15 :0] gapr7 ; // GAPR7 register
|
||||
wire [15 :0] lcpr ; // LCPR register
|
||||
wire [15 :0] ampr0 ; // AMPR0 register
|
||||
wire [15 :0] ampr1 ; // AMPR1 register
|
||||
wire [15 :0] ampr2 ; // AMPR2 register
|
||||
wire [15 :0] ampr3 ; // AMPR3 register
|
||||
wire [15 :0] baisr0 ; // BIASR0 register
|
||||
wire [15 :0] baisr1 ; // BIASR1 register
|
||||
wire [15 :0] baisr2 ; // BIASR2 register
|
||||
wire [15 :0] baisr3 ; // BIASR3 register
|
||||
wire [31 :0] rtimr ; // RTIMR register
|
||||
wire [31 :0] icntr ; // ICNTR register
|
||||
wire [1 :0] fsir ; // FSIR register
|
||||
wire [1 :0] intpselr ; // INTPSELR register
|
||||
|
||||
reg [31: 0] rddata_reg ;
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- Address decoder
|
||||
//
|
||||
// Decodes the register address offset input(reg_addr)
|
||||
// to produce enable (select) signals for each of the
|
||||
// SW-registers in the macrocell. The reg_addr input
|
||||
// is bits [15:0] of the paddr bus.
|
||||
// ------------------------------------------------------
|
||||
assign mcuparar0en = (rwaddr[15:2] == `MCUPARAR0 >> 2) ? 1'b1 : 1'b0;
|
||||
assign mcuparar1en = (rwaddr[15:2] == `MCUPARAR1 >> 2) ? 1'b1 : 1'b0;
|
||||
assign mcuparar2en = (rwaddr[15:2] == `MCUPARAR2 >> 2) ? 1'b1 : 1'b0;
|
||||
assign mcuparar3en = (rwaddr[15:2] == `MCUPARAR3 >> 2) ? 1'b1 : 1'b0;
|
||||
assign mcuresr0en = (rwaddr[15:2] == `MCURESR0 >> 2) ? 1'b1 : 1'b0;
|
||||
assign mcuresr1en = (rwaddr[15:2] == `MCURESR1 >> 2) ? 1'b1 : 1'b0;
|
||||
assign mcuresr2en = (rwaddr[15:2] == `MCURESR2 >> 2) ? 1'b1 : 1'b0;
|
||||
assign mcuresr3en = (rwaddr[15:2] == `MCURESR3 >> 2) ? 1'b1 : 1'b0;
|
||||
assign cwfr0en = (rwaddr[15:2] == `CWFR0 >> 2) ? 1'b1 : 1'b0;
|
||||
assign cwfr1en = (rwaddr[15:2] == `CWFR1 >> 2) ? 1'b1 : 1'b0;
|
||||
assign cwfr2en = (rwaddr[15:2] == `CWFR2 >> 2) ? 1'b1 : 1'b0;
|
||||
assign cwfr3en = (rwaddr[15:2] == `CWFR3 >> 2) ? 1'b1 : 1'b0;
|
||||
assign cwprren = (rwaddr[15:2] == `CWPRR >> 2) ? 1'b1 : 1'b0;
|
||||
assign gapr0en = (rwaddr[15:2] == `GAPR0 >> 2) ? 1'b1 : 1'b0;
|
||||
assign gapr1en = (rwaddr[15:2] == `GAPR1 >> 2) ? 1'b1 : 1'b0;
|
||||
assign gapr2en = (rwaddr[15:2] == `GAPR2 >> 2) ? 1'b1 : 1'b0;
|
||||
assign gapr3en = (rwaddr[15:2] == `GAPR3 >> 2) ? 1'b1 : 1'b0;
|
||||
assign gapr4en = (rwaddr[15:2] == `GAPR4 >> 2) ? 1'b1 : 1'b0;
|
||||
assign gapr5en = (rwaddr[15:2] == `GAPR5 >> 2) ? 1'b1 : 1'b0;
|
||||
assign gapr6en = (rwaddr[15:2] == `GAPR6 >> 2) ? 1'b1 : 1'b0;
|
||||
assign gapr7en = (rwaddr[15:2] == `GAPR7 >> 2) ? 1'b1 : 1'b0;
|
||||
assign lcpren = (rwaddr[15:2] == `LCPR >> 2) ? 1'b1 : 1'b0;
|
||||
assign ampr0en = (rwaddr[15:2] == `AMPR0 >> 2) ? 1'b1 : 1'b0;
|
||||
assign ampr1en = (rwaddr[15:2] == `AMPR1 >> 2) ? 1'b1 : 1'b0;
|
||||
assign ampr2en = (rwaddr[15:2] == `AMPR2 >> 2) ? 1'b1 : 1'b0;
|
||||
assign ampr3en = (rwaddr[15:2] == `AMPR3 >> 2) ? 1'b1 : 1'b0;
|
||||
assign baisr0en = (rwaddr[15:2] == `BIASR0 >> 2) ? 1'b1 : 1'b0;
|
||||
assign baisr1en = (rwaddr[15:2] == `BIASR1 >> 2) ? 1'b1 : 1'b0;
|
||||
assign baisr2en = (rwaddr[15:2] == `BIASR2 >> 2) ? 1'b1 : 1'b0;
|
||||
assign baisr3en = (rwaddr[15:2] == `BIASR3 >> 2) ? 1'b1 : 1'b0;
|
||||
assign rtimren = (rwaddr[15:2] == `RTIMR >> 2) ? 1'b1 : 1'b0;
|
||||
assign icntren = (rwaddr[15:2] == `ICNTR >> 2) ? 1'b1 : 1'b0;
|
||||
assign fsiren = (rwaddr[15:2] == `FSIR >> 2) ? 1'b1 : 1'b0;
|
||||
assign intpselren = (rwaddr[15:2] == `INTPSELR >> 2) ? 1'b1 : 1'b0;
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- Write enable signals
|
||||
//
|
||||
// Write enable signals for writable SW-registers.
|
||||
// The write enable for each register is the ANDed
|
||||
// result of the register enable and the input reg_wren
|
||||
// ------------------------------------------------------
|
||||
assign mcuresr0we = mcuresr0en & wren;
|
||||
assign mcuresr1we = mcuresr1en & wren;
|
||||
assign mcuresr2we = mcuresr2en & wren;
|
||||
assign mcuresr3we = mcuresr3en & wren;
|
||||
assign cwfr0we = cwfr0en & wren;
|
||||
assign cwfr1we = cwfr1en & wren;
|
||||
assign cwfr2we = cwfr2en & wren;
|
||||
assign cwfr3we = cwfr3en & wren;
|
||||
assign cwprrwe = cwprren & wren;
|
||||
assign gapr0we = gapr0en & wren;
|
||||
assign gapr1we = gapr1en & wren;
|
||||
assign gapr2we = gapr2en & wren;
|
||||
assign gapr3we = gapr3en & wren;
|
||||
assign gapr4we = gapr4en & wren;
|
||||
assign gapr5we = gapr5en & wren;
|
||||
assign gapr6we = gapr6en & wren;
|
||||
assign gapr7we = gapr7en & wren;
|
||||
assign lcprwe = lcpren & wren;
|
||||
assign ampr0we = ampr0en & wren;
|
||||
assign ampr1we = ampr1en & wren;
|
||||
assign ampr2we = ampr2en & wren;
|
||||
assign ampr3we = ampr3en & wren;
|
||||
assign baisr0we = baisr0en & wren;
|
||||
assign baisr1we = baisr1en & wren;
|
||||
assign baisr2we = baisr2en & wren;
|
||||
assign baisr3we = baisr3en & wren;
|
||||
assign intpselrwe = intpselren & wren;
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- mcuresr0 register
|
||||
//
|
||||
// Write mcuresr0 for 'MCURESR0' : 32-bit register
|
||||
// Register is split into the following bit fields
|
||||
//
|
||||
// [31:0] --> mcuresr0
|
||||
// ------------------------------------------------------
|
||||
wire [31:0] mcuresr0_w;
|
||||
assign mcuresr0_w[31:24] = wrmask[3] ? wrdata[31:24] : mcuresr0[31:24];
|
||||
assign mcuresr0_w[23:16] = wrmask[2] ? wrdata[23:16] : mcuresr0[23:16];
|
||||
assign mcuresr0_w[15 :8] = wrmask[1] ? wrdata[15 :8] : mcuresr0[15 :8];
|
||||
assign mcuresr0_w[7 :0] = wrmask[0] ? wrdata[7 :0] : mcuresr0[7 :0];
|
||||
sirv_gnrl_dfflr #(32) mcuresr0_dfflr (mcuresr0we, mcuresr0_w[31:0], mcuresr0, clk, rst_n);
|
||||
// ------------------------------------------------------
|
||||
// -- mcuresr1 register
|
||||
//
|
||||
// Write mcuresr1 for 'MCURESR1' : 32-bit register
|
||||
// Register is split into the following bit fields
|
||||
//
|
||||
// [31:0] --> mcuresr1
|
||||
// ------------------------------------------------------
|
||||
wire [31:0] mcuresr1_w;
|
||||
assign mcuresr1_w[31:24] = wrmask[3] ? wrdata[31:24] : mcuresr1[31:24];
|
||||
assign mcuresr1_w[23:16] = wrmask[2] ? wrdata[23:16] : mcuresr1[23:16];
|
||||
assign mcuresr1_w[15 :8] = wrmask[1] ? wrdata[15 :8] : mcuresr1[15 :8];
|
||||
assign mcuresr1_w[7 :0] = wrmask[0] ? wrdata[7 :0] : mcuresr1[7 :0];
|
||||
sirv_gnrl_dfflr #(32) mcuresr1_dfflr (mcuresr1we, mcuresr1_w[31:0], mcuresr1, clk, rst_n);
|
||||
// ------------------------------------------------------
|
||||
// -- mcuresr2 register
|
||||
//
|
||||
// Write mcuresr2 for 'MCURESR2' : 32-bit register
|
||||
// Register is split into the following bit fields
|
||||
//
|
||||
// [31:0] --> mcuresr2
|
||||
// ------------------------------------------------------
|
||||
wire [31:0] mcuresr2_w;
|
||||
assign mcuresr2_w[31:24] = wrmask[3] ? wrdata[31:24] : mcuresr2[31:24];
|
||||
assign mcuresr2_w[23:16] = wrmask[2] ? wrdata[23:16] : mcuresr2[23:16];
|
||||
assign mcuresr2_w[15 :8] = wrmask[1] ? wrdata[15 :8] : mcuresr2[15 :8];
|
||||
assign mcuresr2_w[7 :0] = wrmask[0] ? wrdata[7 :0] : mcuresr2[7 :0];
|
||||
sirv_gnrl_dfflr #(32) mcuresr2_dfflr (mcuresr2we, mcuresr2_w[31:0], mcuresr2, clk, rst_n);
|
||||
// ------------------------------------------------------
|
||||
// -- mcuresr3 register
|
||||
//
|
||||
// Write mcuresr3 for 'MCURESR3' : 32-bit register
|
||||
// Register is split into the following bit fields
|
||||
//
|
||||
// [31:0] --> mcuresr3
|
||||
// ------------------------------------------------------
|
||||
wire [31:0] mcuresr3_w;
|
||||
assign mcuresr3_w[31:24] = wrmask[3] ? wrdata[31:24] : mcuresr3[31:24];
|
||||
assign mcuresr3_w[23:16] = wrmask[2] ? wrdata[23:16] : mcuresr3[23:16];
|
||||
assign mcuresr3_w[15 :8] = wrmask[1] ? wrdata[15 :8] : mcuresr3[15 :8];
|
||||
assign mcuresr3_w[7 :0] = wrmask[0] ? wrdata[7 :0] : mcuresr3[7 :0];
|
||||
sirv_gnrl_dfflr #(32) mcuresr3_dfflr (mcuresr3we, mcuresr3_w[31:0], mcuresr3, clk, rst_n);
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- cwfr0 register
|
||||
//
|
||||
// Write cwfr0 for 'CWFR0' : 32-bit register
|
||||
// Register is split into the following bit fields
|
||||
//
|
||||
// [31:0] --> cwfr0
|
||||
// ------------------------------------------------------
|
||||
wire [31:0] cwfr0_w;
|
||||
assign cwfr0_w[31:24] = wrmask[3] ? wrdata[31:24] : cwfr0[31:24];
|
||||
assign cwfr0_w[23:16] = wrmask[2] ? wrdata[23:16] : cwfr0[23:16];
|
||||
assign cwfr0_w[15 :8] = wrmask[1] ? wrdata[15 :8] : cwfr0[15 :8];
|
||||
assign cwfr0_w[7 :0] = wrmask[0] ? wrdata[7 :0] : cwfr0[7 :0];
|
||||
sirv_gnrl_dfflr #(32) cwfr0_dfflr (cwfr0we, cwfr0_w[31:0], cwfr0, clk, rst_n);
|
||||
// ------------------------------------------------------
|
||||
// -- cwfr1 register
|
||||
//
|
||||
// Write cwfr1 for 'CWFR1' : 32-bit register
|
||||
// Register is split into the following bit fields
|
||||
//
|
||||
// [31:16] --> cwfr1
|
||||
// ------------------------------------------------------
|
||||
wire [31:0] cwfr1_w;
|
||||
assign cwfr1_w[31:24] = wrmask[3] ? wrdata[31:24] : cwfr1[31:24];
|
||||
assign cwfr1_w[23:16] = wrmask[2] ? wrdata[23:16] : cwfr1[23:16];
|
||||
assign cwfr1_w[15 :8] = wrmask[1] ? wrdata[15 :8] : cwfr1[15 :8];
|
||||
assign cwfr1_w[7 :0] = wrmask[0] ? wrdata[7 :0] : cwfr1[7 :0];
|
||||
sirv_gnrl_dfflr #(32) cwfr1_dfflr (cwfr1we, cwfr1_w[31:0], cwfr1, clk, rst_n);
|
||||
// ------------------------------------------------------
|
||||
// -- cwfr2 register
|
||||
//
|
||||
// Write cwfr2 for 'CWFR2' : 32-bit register
|
||||
// Register is split into the following bit fields
|
||||
//
|
||||
// [31:16] --> cwfr2
|
||||
// ------------------------------------------------------
|
||||
wire [31:0] cwfr2_w;
|
||||
assign cwfr2_w[31:24] = wrmask[3] ? wrdata[31:24] : cwfr2[31:24];
|
||||
assign cwfr2_w[23:16] = wrmask[2] ? wrdata[23:16] : cwfr2[23:16];
|
||||
assign cwfr2_w[15 :8] = wrmask[1] ? wrdata[15 :8] : cwfr2[15 :8];
|
||||
assign cwfr2_w[7 :0] = wrmask[0] ? wrdata[7 :0] : cwfr2[7 :0];
|
||||
sirv_gnrl_dfflr #(32) cwfr2_dfflr (cwfr2we, cwfr2_w[31:0], cwfr2, clk, rst_n);
|
||||
// ------------------------------------------------------
|
||||
// -- cwfr3 register
|
||||
//
|
||||
// Write cwfr3 for 'CWFR3' : 32-bit register
|
||||
// Register is split into the following bit fields
|
||||
//
|
||||
// [31:16] --> cwfr3
|
||||
// ------------------------------------------------------
|
||||
wire [31:0] cwfr3_w;
|
||||
assign cwfr3_w[31:24] = wrmask[3] ? wrdata[31:24] : cwfr3[31:24];
|
||||
assign cwfr3_w[23:16] = wrmask[2] ? wrdata[23:16] : cwfr3[23:16];
|
||||
assign cwfr3_w[15 :8] = wrmask[1] ? wrdata[15 :8] : cwfr3[15 :8];
|
||||
assign cwfr3_w[7 :0] = wrmask[0] ? wrdata[7 :0] : cwfr3[7 :0];
|
||||
sirv_gnrl_dfflr #(32) cwfr3_dfflr (cwfr3we, cwfr3_w[31:0], cwfr3, clk, rst_n);
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- cwprr register(self-clearing)
|
||||
//
|
||||
// Write cwprr for 'CWPRR' : 32-bit register
|
||||
// Register is split into the following bit fields
|
||||
//
|
||||
// [0] --> cwprr
|
||||
// ------------------------------------------------------
|
||||
wire cwprr_w = wrmask[0] & cwprrwe & wrdata[0];
|
||||
|
||||
sirv_gnrl_dffr #(1) cwprr_dffr (cwprr_w, cwprr, clk, rst_n);
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- gapr0 register
|
||||
//
|
||||
// Write gapr0 for 'GAPR0' : 32-bit register
|
||||
// Register is split into the following bit fields
|
||||
//
|
||||
// [31:16] --> gapr0
|
||||
// ------------------------------------------------------
|
||||
wire [31:0] gapr0_w;
|
||||
assign gapr0_w[31:24] = wrmask[3] ? wrdata[31:24] : gapr0[15: 8];/////////////////////////////////////////////////////////////31:26->15:8
|
||||
assign gapr0_w[23:16] = wrmask[2] ? wrdata[23:16] : gapr0[ 7: 0];/////////////////////////////////////////////////////////////23:16->7:0
|
||||
sirv_gnrl_dfflr #(16) gapr0_dfflr (gapr0we, gapr0_w[31:16], gapr0, clk, rst_n);
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- gapr1 register
|
||||
//
|
||||
// Write gapr1 for 'GAPR1' : 32-bit register
|
||||
// Register is split into the following bit fields
|
||||
//
|
||||
// [31:16] --> gapr1
|
||||
// ------------------------------------------------------
|
||||
wire [31:0] gapr1_w;
|
||||
assign gapr1_w[31:24] = wrmask[3] ? wrdata[31:24] : gapr1[15: 8];/////////////////////////////////////////////////////////////
|
||||
assign gapr1_w[23:16] = wrmask[2] ? wrdata[23:16] : gapr1[ 7: 0];/////////////////////////////////////////////////////////////
|
||||
sirv_gnrl_dfflr #(16) gapr1_dfflr (gapr1we, gapr1_w[31:16], gapr1, clk, rst_n);
|
||||
// ------------------------------------------------------
|
||||
// -- gapr2 register
|
||||
//
|
||||
// Write gapr2 for 'GAPR2' : 32-bit register
|
||||
// Register is split into the following bit fields
|
||||
//
|
||||
// [31:16] --> gapr2
|
||||
// ------------------------------------------------------
|
||||
wire [31:0] gapr2_w;
|
||||
assign gapr2_w[31:24] = wrmask[3] ? wrdata[31:24] : gapr2[15: 8];/////////////////////////////////////////////////////////////
|
||||
assign gapr2_w[23:16] = wrmask[2] ? wrdata[23:16] : gapr2[ 7: 0];/////////////////////////////////////////////////////////////
|
||||
sirv_gnrl_dfflr #(16) gapr2_dfflr (gapr2we, gapr2_w[31:16], gapr2, clk, rst_n);
|
||||
// ------------------------------------------------------
|
||||
// -- gapr3 register
|
||||
//
|
||||
// Write gapr3 for 'GAPR3' : 32-bit register
|
||||
// Register is split into the following bit fields
|
||||
//
|
||||
// [31:16] --> gapr3
|
||||
// ------------------------------------------------------
|
||||
wire [31:0] gapr3_w;
|
||||
assign gapr3_w[31:24] = wrmask[3] ? wrdata[31:24] : gapr3[15: 8];/////////////////////////////////////////////////////////////
|
||||
assign gapr3_w[23:16] = wrmask[2] ? wrdata[23:16] : gapr3[ 7: 0];/////////////////////////////////////////////////////////////
|
||||
sirv_gnrl_dfflr #(16) gapr3_dfflr (gapr3we, gapr3_w[31:16], gapr3, clk, rst_n);
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- gapr4 register
|
||||
//
|
||||
// Write gapr4 for 'GAPR4' : 32-bit register
|
||||
// Register is split into the following bit fields
|
||||
//
|
||||
// [31:16] --> gapr4
|
||||
// ------------------------------------------------------
|
||||
wire [31:0] gapr4_w;
|
||||
assign gapr4_w[31:24] = wrmask[3] ? wrdata[31:24] : gapr4[15: 8];/////////////////////////////////////////////////////////////
|
||||
assign gapr4_w[23:16] = wrmask[2] ? wrdata[23:16] : gapr4[ 7: 0];/////////////////////////////////////////////////////////////
|
||||
sirv_gnrl_dfflr #(16) gapr4_dfflr (gapr4we, gapr4_w[31:16], gapr4, clk, rst_n);
|
||||
// ------------------------------------------------------
|
||||
// -- gapr5 register
|
||||
//
|
||||
// Write gapr5 for 'GAPR5' : 32-bit register
|
||||
// Register is split into the following bit fields
|
||||
//
|
||||
// [31:16] --> gapr5
|
||||
// ------------------------------------------------------
|
||||
wire [31:0] gapr5_w;
|
||||
assign gapr5_w[31:24] = wrmask[3] ? wrdata[31:24] : gapr5[15: 8];/////////////////////////////////////////////////////////////
|
||||
assign gapr5_w[23:16] = wrmask[2] ? wrdata[23:16] : gapr5[ 7: 0];/////////////////////////////////////////////////////////////
|
||||
sirv_gnrl_dfflr #(16) gapr5_dfflr (gapr5we, gapr5_w[31:16], gapr5, clk, rst_n);
|
||||
// ------------------------------------------------------
|
||||
// -- gapr6 register
|
||||
//
|
||||
// Write gapr6 for 'GAPR6' : 32-bit register
|
||||
// Register is split into the following bit fields
|
||||
//
|
||||
// [31:16] --> gapr6
|
||||
// ------------------------------------------------------
|
||||
wire [31:0] gapr6_w;
|
||||
assign gapr6_w[31:24] = wrmask[3] ? wrdata[31:24] : gapr6[15: 8];/////////////////////////////////////////////////////////////
|
||||
assign gapr6_w[23:16] = wrmask[2] ? wrdata[23:16] : gapr6[ 7: 0];/////////////////////////////////////////////////////////////
|
||||
sirv_gnrl_dfflr #(16) gapr6_dfflr (gapr6we, gapr6_w[31:16], gapr6, clk, rst_n);
|
||||
// ------------------------------------------------------
|
||||
// -- gapr7 register
|
||||
//
|
||||
// Write gapr7 for 'GAPR7' : 32-bit register
|
||||
// Register is split into the following bit fields
|
||||
//
|
||||
// [31:16] --> gapr7
|
||||
// ------------------------------------------------------
|
||||
wire [31:0] gapr7_w;
|
||||
assign gapr7_w[31:24] = wrmask[3] ? wrdata[31:24] : gapr7[15: 8];/////////////////////////////////////////////////////////////
|
||||
assign gapr7_w[23:16] = wrmask[2] ? wrdata[23:16] : gapr7[ 7: 0];/////////////////////////////////////////////////////////////
|
||||
sirv_gnrl_dfflr #(16) gapr7_dfflr (gapr7we, gapr7_w[31:16], gapr7, clk, rst_n);
|
||||
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- lcpr register
|
||||
//
|
||||
// Write lcpr for 'LCPR' : 32-bit register
|
||||
// Register is split into the following bit fields
|
||||
//
|
||||
// [31:16] --> lcpr
|
||||
// ------------------------------------------------------
|
||||
wire [31:0] lcpr_w;
|
||||
assign lcpr_w[31:24] = wrmask[3] ? wrdata[31:24] : lcpr[15: 8];/////////////////////////////////////////////////////////////
|
||||
assign lcpr_w[23:16] = wrmask[2] ? wrdata[23:16] : lcpr[ 7: 0];/////////////////////////////////////////////////////////////
|
||||
sirv_gnrl_dfflr #(16) lcpr_dfflr (lcprwe, lcpr_w[31:16], lcpr, clk, rst_n);
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- ampr0 register
|
||||
//
|
||||
// Write ampr0 for 'AMPR0' : 32-bit register
|
||||
// Register is split into the following bit fields
|
||||
//
|
||||
// [31:16] --> ampr0
|
||||
// ------------------------------------------------------
|
||||
wire [31:0] ampr0_w;
|
||||
assign ampr0_w[31:24] = wrmask[3] ? wrdata[31:24] : ampr0[15: 8];/////////////////////////////////////////////////////////////
|
||||
assign ampr0_w[23:16] = wrmask[2] ? wrdata[23:16] : ampr0[ 7: 0];/////////////////////////////////////////////////////////////
|
||||
sirv_gnrl_dfflr #(16) ampr0_dfflr (ampr0we, ampr0_w[31:16], ampr0, clk, rst_n);
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- ampr1 register
|
||||
//
|
||||
// Write ampr1 for 'AMPR10' : 32-bit register
|
||||
// Register is split into the following bit fields
|
||||
//
|
||||
// [31:16] --> ampr1
|
||||
// ------------------------------------------------------
|
||||
wire [31:0] ampr1_w;
|
||||
assign ampr1_w[31:24] = wrmask[3] ? wrdata[31:24] : ampr1[15: 8];/////////////////////////////////////////////////////////////
|
||||
assign ampr1_w[23:16] = wrmask[2] ? wrdata[23:16] : ampr1[ 7: 0];/////////////////////////////////////////////////////////////
|
||||
sirv_gnrl_dfflr #(16) ampr1_dfflr (ampr1we, ampr1_w[31:16], ampr1, clk, rst_n);
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- ampr2 register
|
||||
//
|
||||
// Write ampr2 for 'AMPR2' : 32-bit register
|
||||
// Register is split into the following bit fields
|
||||
//
|
||||
// [31:16] --> ampr2
|
||||
// ------------------------------------------------------
|
||||
wire [31:0] ampr2_w;
|
||||
assign ampr2_w[31:24] = wrmask[3] ? wrdata[31:24] : ampr2[15: 8];/////////////////////////////////////////////////////////////
|
||||
assign ampr2_w[23:16] = wrmask[2] ? wrdata[23:16] : ampr2[ 7: 0];/////////////////////////////////////////////////////////////
|
||||
sirv_gnrl_dfflr #(16) ampr2_dfflr (ampr2we, ampr2_w[31:16], ampr2, clk, rst_n);
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- ampr3 register
|
||||
//
|
||||
// Write ampr3 for 'AMPR3' : 32-bit register
|
||||
// Register is split into the following bit fields
|
||||
//
|
||||
// [31:16] --> ampr3
|
||||
// ------------------------------------------------------
|
||||
wire [31:0] ampr3_w;
|
||||
assign ampr3_w[31:24] = wrmask[3] ? wrdata[31:24] : ampr3[15: 8];/////////////////////////////////////////////////////////////
|
||||
assign ampr3_w[23:16] = wrmask[2] ? wrdata[23:16] : ampr3[ 7: 0];/////////////////////////////////////////////////////////////
|
||||
sirv_gnrl_dfflr #(16) ampr3_dfflr (ampr3we, ampr3_w[31:16], ampr3, clk, rst_n);
|
||||
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- baisr0 register
|
||||
//
|
||||
// Write baisr0 for 'BIASR0' : 32-bit register
|
||||
// Register is split into the following bit fields
|
||||
//
|
||||
// [31:16] --> baisr0
|
||||
// ------------------------------------------------------
|
||||
wire [31:0] baisr0_w;
|
||||
assign baisr0_w[31:24] = wrmask[3] ? wrdata[31:24] : baisr0[15: 8];/////////////////////////////////////////////////////////////
|
||||
assign baisr0_w[23:16] = wrmask[2] ? wrdata[23:16] : baisr0[ 7: 0];/////////////////////////////////////////////////////////////
|
||||
sirv_gnrl_dfflr #(16) baisr0_dfflr (baisr0we, baisr0_w[31:16], baisr0, clk, rst_n);
|
||||
// ------------------------------------------------------
|
||||
// -- baisr1 register
|
||||
//
|
||||
// Write baisr1 for 'BIASR1' : 32-bit register
|
||||
// Register is split into the following bit fields
|
||||
//
|
||||
// [31:16] --> baisr1
|
||||
// ------------------------------------------------------
|
||||
wire [31:0] baisr1_w;
|
||||
assign baisr1_w[31:24] = wrmask[3] ? wrdata[31:24] : baisr1[15: 8];/////////////////////////////////////////////////////////////
|
||||
assign baisr1_w[23:16] = wrmask[2] ? wrdata[23:16] : baisr1[ 7: 0];/////////////////////////////////////////////////////////////
|
||||
sirv_gnrl_dfflr #(16) baisr1_dfflr (baisr1we, baisr1_w[31:16], baisr1, clk, rst_n);
|
||||
// ------------------------------------------------------
|
||||
// -- baisr2 register
|
||||
//
|
||||
// Write baisr2 for 'BIASR2' : 32-bit register
|
||||
// Register is split into the following bit fields
|
||||
//
|
||||
// [31:16] --> baisr2
|
||||
// ------------------------------------------------------
|
||||
wire [31:0] baisr2_w;
|
||||
assign baisr2_w[31:24] = wrmask[3] ? wrdata[31:24] : baisr2[15: 8];/////////////////////////////////////////////////////////////
|
||||
assign baisr2_w[23:16] = wrmask[2] ? wrdata[23:16] : baisr2[ 7: 0];/////////////////////////////////////////////////////////////
|
||||
sirv_gnrl_dfflr #(16) baisr2_dfflr (baisr2we, baisr2_w[31:16], baisr2, clk, rst_n);
|
||||
// ------------------------------------------------------
|
||||
// -- baisr3 register
|
||||
//
|
||||
// Write baisr3 for 'BIASR3' : 32-bit register
|
||||
// Register is split into the following bit fields
|
||||
//
|
||||
// [31:16] --> baisr3
|
||||
// ------------------------------------------------------
|
||||
wire [31:0] baisr3_w;
|
||||
assign baisr3_w[31:24] = wrmask[3] ? wrdata[31:24] : baisr3[15: 8];/////////////////////////////////////////////////////////////
|
||||
assign baisr3_w[23:16] = wrmask[2] ? wrdata[23:16] : baisr3[ 7: 0];/////////////////////////////////////////////////////////////
|
||||
sirv_gnrl_dfflr #(16) baisr3_dfflr (baisr3we, baisr3_w[31:16], baisr3, clk, rst_n);
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- intpselr register
|
||||
//
|
||||
// Write intpselr for 'INTPSELR' : 32-bit register
|
||||
// Register is split into the following bit fields
|
||||
//
|
||||
// [1:0] --> intpselr
|
||||
// ------------------------------------------------------
|
||||
wire [1:0] intpselr_w;
|
||||
assign intpselr_w[1:0] = wrmask[0] ? wrdata[1:0] : intpselr[1:0];
|
||||
sirv_gnrl_dfflr #(2) intpselr_dfflr (intpselrwe, intpselr_w[1:0], intpselr, clk, rst_n);
|
||||
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- mcuparar0
|
||||
// ------------------------------------------------------
|
||||
sirv_gnrl_dffr #(32) mcuparar0_dffr (mcu_param[0], mcuparar0, clk, rst_n);
|
||||
// ------------------------------------------------------
|
||||
// -- mcuparar1
|
||||
// ------------------------------------------------------
|
||||
sirv_gnrl_dffr #(32) mcuparar1_dffr (mcu_param[1], mcuparar1, clk, rst_n);
|
||||
// ------------------------------------------------------
|
||||
// -- mcuparar2
|
||||
// ------------------------------------------------------
|
||||
sirv_gnrl_dffr #(32) mcuparar2_dffr (mcu_param[2], mcuparar2, clk, rst_n);
|
||||
// ------------------------------------------------------
|
||||
// -- mcuparar3
|
||||
// ------------------------------------------------------
|
||||
sirv_gnrl_dffr #(32) mcuparar3_dffr (mcu_param[3], mcuparar3, clk, rst_n);
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- rtimr
|
||||
// ------------------------------------------------------
|
||||
sirv_gnrl_dffr #(32) rtimr_dffr (run_time, rtimr, clk, rst_n);
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- icntr
|
||||
// ------------------------------------------------------
|
||||
sirv_gnrl_dffr #(32) icntr_dffr (instr_num, icntr, clk, rst_n);
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- fsir
|
||||
// ------------------------------------------------------
|
||||
sirv_gnrl_dffr #(2) fsir_dffr (fb_st_info[1:0], fsir, clk, rst_n);////////////////////////////////////////////[1:0]
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- Read data mux
|
||||
//
|
||||
// -- The data from the selected register is
|
||||
// -- placed on a zero-padded 32-bit read data bus.
|
||||
// ------------------------------------------------------
|
||||
always @(*) begin : RDDATA_PROC
|
||||
rddata_reg = {32{1'b0}};
|
||||
if(mcuparar0en == H ) rddata_reg[31:0] = mcuparar0 ;
|
||||
if(mcuparar1en == H ) rddata_reg[31:0] = mcuparar1 ;
|
||||
if(mcuparar2en == H ) rddata_reg[31:0] = mcuparar2 ;
|
||||
if(mcuparar3en == H ) rddata_reg[31:0] = mcuparar3 ;
|
||||
if(mcuresr0en == H ) rddata_reg[31:0] = mcuresr0 ;
|
||||
if(mcuresr1en == H ) rddata_reg[31:0] = mcuresr1 ;
|
||||
if(mcuresr2en == H ) rddata_reg[31:0] = mcuresr2 ;
|
||||
if(mcuresr3en == H ) rddata_reg[31:0] = mcuresr3 ;
|
||||
if(cwfr0en == H ) rddata_reg[31:0] = cwfr0 ;
|
||||
if(cwfr1en == H ) rddata_reg[31:0] = cwfr1 ;
|
||||
if(cwfr2en == H ) rddata_reg[31:0] = cwfr2 ;
|
||||
if(cwfr3en == H ) rddata_reg[31:0] = cwfr3 ;
|
||||
if(cwprren == H ) rddata_reg[0 :0] = cwprr ;
|
||||
if(gapr0en == H ) rddata_reg[15:0] = gapr0 ;
|
||||
if(gapr1en == H ) rddata_reg[15:0] = gapr1 ;
|
||||
if(gapr2en == H ) rddata_reg[15:0] = gapr2 ;
|
||||
if(gapr3en == H ) rddata_reg[15:0] = gapr3 ;
|
||||
if(gapr4en == H ) rddata_reg[15:0] = gapr4 ;
|
||||
if(gapr5en == H ) rddata_reg[15:0] = gapr5 ;
|
||||
if(gapr6en == H ) rddata_reg[15:0] = gapr6 ;
|
||||
if(gapr7en == H ) rddata_reg[15:0] = gapr7 ;
|
||||
if(lcpren == H ) rddata_reg[15:0] = lcpr ;
|
||||
if(ampr0en == H ) rddata_reg[15:0] = ampr0 ;
|
||||
if(ampr1en == H ) rddata_reg[15:0] = ampr1 ;
|
||||
if(ampr2en == H ) rddata_reg[15:0] = ampr2 ;
|
||||
if(ampr3en == H ) rddata_reg[15:0] = ampr3 ;
|
||||
if(baisr0en == H ) rddata_reg[15:0] = baisr0 ;
|
||||
if(baisr1en == H ) rddata_reg[15:0] = baisr1 ;
|
||||
if(baisr2en == H ) rddata_reg[15:0] = baisr2 ;
|
||||
if(baisr3en == H ) rddata_reg[15:0] = baisr3 ;
|
||||
if(rtimren == H ) rddata_reg[31:0] = rtimr ;
|
||||
if(icntren == H ) rddata_reg[31:0] = icntr ;
|
||||
if(fsiren == H ) rddata_reg[1 :0] = fsir ;
|
||||
if(intpselren == H ) rddata_reg[1 :0] = intpselr ;////////////////////////////////////////////////////////////
|
||||
end
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- Output signals assignment
|
||||
// ------------------------------------------------------
|
||||
//mcu result
|
||||
assign mcu_result[0] = mcuresr0 ;
|
||||
assign mcu_result[1] = mcuresr1 ;
|
||||
assign mcu_result[2] = mcuresr2 ;
|
||||
assign mcu_result[3] = mcuresr3 ;
|
||||
|
||||
//nco_fwc lookup table output
|
||||
assign mcu_cwfr[0] = cwfr0;
|
||||
assign mcu_cwfr[1] = cwfr1;
|
||||
assign mcu_cwfr[2] = cwfr2;
|
||||
assign mcu_cwfr[3] = cwfr3;
|
||||
|
||||
//nco_pha lookup table output
|
||||
assign mcu_gapr[0] = gapr0; ////////////////////////////////////////////////16bit assign to 32bit(?)
|
||||
assign mcu_gapr[1] = gapr1;
|
||||
assign mcu_gapr[2] = gapr2;
|
||||
assign mcu_gapr[3] = gapr3;
|
||||
assign mcu_gapr[4] = gapr4;
|
||||
assign mcu_gapr[5] = gapr5;
|
||||
assign mcu_gapr[6] = gapr6;
|
||||
assign mcu_gapr[7] = gapr7;
|
||||
|
||||
//amp lookup table output
|
||||
assign mcu_ampr[0] = ampr0;
|
||||
assign mcu_ampr[1] = ampr1;
|
||||
assign mcu_ampr[2] = ampr2;
|
||||
assign mcu_ampr[3] = ampr3;
|
||||
|
||||
//bais lookup table output
|
||||
assign mcu_baisr[0] = baisr0;
|
||||
assign mcu_baisr[1] = baisr1;
|
||||
assign mcu_baisr[2] = baisr2;
|
||||
assign mcu_baisr[3] = baisr3;
|
||||
|
||||
//CFG Port
|
||||
assign mcu_nco_pha_clr = cwprr;
|
||||
assign mcu_rz_pha = lcpr;
|
||||
assign mcu_intp_sel = intpselr;
|
||||
//rddata
|
||||
//assign rddata = rddata_reg ;
|
||||
sirv_gnrl_dffr #(32) rddata_dffr (rddata_reg, rddata, clk, rst_n);////////////////////////
|
||||
endmodule
|
||||
|
||||
`undef MCUPARAR0
|
||||
`undef MCUPARAR1
|
||||
`undef MCUPARAR2
|
||||
`undef MCUPARAR3
|
||||
`undef MCURESR0
|
||||
`undef MCURESR1
|
||||
`undef MCURESR2
|
||||
`undef MCURESR3
|
||||
`undef CWFR0
|
||||
`undef CWFR1
|
||||
`undef CWFR2
|
||||
`undef CWFR3
|
||||
`undef CWPRR
|
||||
`undef GAPR0
|
||||
`undef GAPR1
|
||||
`undef GAPR2
|
||||
`undef GAPR3
|
||||
`undef GAPR4
|
||||
`undef GAPR5
|
||||
`undef GAPR6
|
||||
`undef GAPR7
|
||||
`undef LCPR
|
||||
`undef AMPR0
|
||||
`undef AMPR1
|
||||
`undef AMPR2
|
||||
`undef AMPR3
|
||||
`undef BIASR0
|
||||
`undef BIASR1
|
||||
`undef BIASR2
|
||||
`undef BIASR3
|
||||
`undef RTIMR
|
||||
`undef ICNTR
|
||||
`undef FSIR
|
||||
|
|
@ -0,0 +1,271 @@
|
|||
//+FHDR--------------------------------------------------------------------------------------------------------
|
||||
// Company:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// File Name : qbmcu.v
|
||||
// Department :
|
||||
// Author : PWY
|
||||
// Author's Tel :
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Relese History
|
||||
// Version Date Author Description
|
||||
// 0.1 2024-03-13 PWY Quantum Bit Measurement and Control Microprocessor
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Keywords :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Parameter
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Purpose :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Target Device:
|
||||
// Tool versions:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Reuse Issues
|
||||
// Reset Strategy:
|
||||
// Clock Domains:
|
||||
// Critical Timing:
|
||||
// Asynchronous I/F:
|
||||
// Synthesizable (y/n):
|
||||
// Other:
|
||||
//-FHDR--------------------------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
`include "qbmcu_defines.v"
|
||||
|
||||
module qbmcu(
|
||||
//system port
|
||||
input clk
|
||||
,input rst_n
|
||||
//Sync Start
|
||||
,input qbmcu_i_start
|
||||
,output [2 :0] qbmcu_o_fsm_st
|
||||
//IFU port
|
||||
,input [`QBMCU_PC_SIZE-1 :0] ifu_i_pc_rtvec // Initial PC
|
||||
,output [`QBMCU_PC_SIZE-1 :0] ifu_o_req_pc // Fetch PC
|
||||
,output ifu_o_req // Fetch req
|
||||
,input [`QBMCU_INSTR_SIZE-1 :0] ifu_rsp_instr
|
||||
//Decoded port
|
||||
,output dec_o_ilegl
|
||||
//LDST port
|
||||
//Address, data, and enable signals connected to the memory space
|
||||
,output [`QBMCU_ADDR_SIZE-1 :0] agu_o_addr
|
||||
,output [`QBMCU_XLEN-1 :0] agu_o_wrdata
|
||||
,output agu_o_wren // Write enable
|
||||
,output [`QBMCU_XLEN/8-1 :0] agu_o_wrmask
|
||||
,output agu_o_rden // Read enable
|
||||
,input [`QBMCU_XLEN-1 :0] agu_i_rddata
|
||||
//Misaligned memory address
|
||||
,output agu_o_addr_unalgn
|
||||
//Extend instructions port
|
||||
// The operands and info to peripheral
|
||||
,output ext_o_send
|
||||
,output ext_o_sendc
|
||||
,output [`QBMCU_XLEN-1 :0] ext_o_codeword
|
||||
,output ext_o_intr
|
||||
);
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
//qbmcu_fsm
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
wire ifupc_rst ;
|
||||
wire ifu_active ;
|
||||
wire wb_active ;
|
||||
wire dec_active ;
|
||||
wire exu_active ;
|
||||
wire ext_wait ;
|
||||
wire ext_o_exit ;
|
||||
wire qbmcu_i_timer_done ;
|
||||
|
||||
qbmcu_fsm U_qbmcu_fsm (
|
||||
.clk ( clk )
|
||||
,.rst_n ( rst_n )
|
||||
,.start ( qbmcu_i_start )
|
||||
,.exit ( ext_o_exit )
|
||||
,.ext_wait ( ext_wait )
|
||||
,.qbmcu_timer_done ( qbmcu_i_timer_done )
|
||||
,.agu_addr_unalgn ( agu_o_addr_unalgn )
|
||||
,.dec_ilegl ( dec_o_ilegl )
|
||||
,.ifupc_rst ( ifupc_rst )
|
||||
,.wb_active ( wb_active )
|
||||
,.ifu_active ( ifu_active )
|
||||
,.dec_active ( dec_active )
|
||||
,.exu_active ( exu_active )
|
||||
,.qbmcu_fsm_st ( qbmcu_o_fsm_st )
|
||||
);
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
//qbmcu_ifu_ifetch
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
wire [`QBMCU_INSTR_SIZE-1:0] ifu_ir ;
|
||||
wire [`QBMCU_PC_SIZE-1 :0] ifu_pc ;
|
||||
wire update_pc_req ;
|
||||
wire [`QBMCU_PC_SIZE-1 :0] update_pc_value ;
|
||||
|
||||
qbmcu_ifu U_qbmcu_ifu (
|
||||
.clk ( clk )
|
||||
,.rst_n ( rst_n )
|
||||
,.ifu_active ( ifu_active )
|
||||
,.exu_active ( exu_active )
|
||||
,.pc_rtvec ( ifu_i_pc_rtvec )
|
||||
,.ifu_req_pc ( ifu_o_req_pc )
|
||||
,.ifu_req ( ifu_o_req )
|
||||
,.ifu_rsp_instr ( ifu_rsp_instr )
|
||||
,.ifu_o_ir ( ifu_ir )
|
||||
,.ifu_o_pc ( ifu_pc )
|
||||
,.ifupc_rst ( ifupc_rst )
|
||||
,.update_pc_req ( update_pc_req )
|
||||
,.update_pc_value ( update_pc_value )
|
||||
);
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
//qbmcu_decode
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
//wire dec_rs1en ;
|
||||
//wire dec_rs2en ;
|
||||
wire dec_rdwen ;
|
||||
wire [`QBMCU_RFIDX_WIDTH-1 :0] dec_rs1idx ;
|
||||
wire [`QBMCU_RFIDX_WIDTH-1 :0] dec_rs2idx ;
|
||||
wire [`QBMCU_RFIDX_WIDTH-1 :0] dec_rdidx ;
|
||||
wire [`QBMCU_DECINFO_WIDTH-1:0] dec_info ;
|
||||
wire [`QBMCU_XLEN-1 :0] dec_imm ;
|
||||
wire [`QBMCU_PC_SIZE-1 :0] dec_pc ;
|
||||
|
||||
qbmcu_decode qbmcu_decode (
|
||||
.clk ( clk )
|
||||
,.rst_n ( rst_n )
|
||||
,.dec_i_active ( dec_active )
|
||||
,.dec_i_instr ( ifu_ir )
|
||||
,.dec_i_pc ( ifu_pc )
|
||||
//,.dec_o_rs1en ( dec_rs1en )
|
||||
//,.dec_o_rs2en ( dec_rs2en )
|
||||
,.dec_o_rdwen ( dec_rdwen )
|
||||
,.dec_o_rs1idx ( dec_rs1idx )
|
||||
,.dec_o_rs2idx ( dec_rs2idx )
|
||||
,.dec_o_rdidx ( dec_rdidx )
|
||||
,.dec_o_info ( dec_info )
|
||||
,.dec_o_imm ( dec_imm )
|
||||
,.dec_o_pc ( dec_pc )
|
||||
,.dec_o_ilegl ( dec_o_ilegl )
|
||||
);
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
//qbmcu_exu
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
wire [`QBMCU_XLEN-1 :0] exu_rs1 ;
|
||||
wire [`QBMCU_XLEN-1 :0] exu_rs2 ;
|
||||
wire [`QBMCU_XLEN-1 :0] bjp_wbck_wdat ;
|
||||
wire bjp_wbck_valid ;
|
||||
wire [`QBMCU_XLEN-1 :0] agu_wbck_wdat ;
|
||||
wire agu_wbck_valid ;
|
||||
wire [`QBMCU_XLEN-1 :0] alu_wbck_wdat ;
|
||||
wire alu_wbck_valid ;
|
||||
wire [`QBMCU_XLEN-1 :0] ext_wbck_wdat ;
|
||||
wire ext_wbck_valid ;
|
||||
wire [`QBMCU_XLEN-1 :0] ext_wait_cnt ;
|
||||
|
||||
//////////////////////////////////////////////////////////////
|
||||
//Address, data, and enable signals connected to the memory space
|
||||
wire ext_o_wait_valid ;
|
||||
|
||||
qbmcu_exu U_qbmcu_exu (
|
||||
.clk ( clk )
|
||||
,.rst_n ( rst_n )
|
||||
,.exu_i_rs1 ( exu_rs1 )
|
||||
,.exu_i_rs2 ( exu_rs2 )
|
||||
,.exu_i_imm ( dec_imm )
|
||||
,.exu_i_pc ( dec_pc )
|
||||
,.exu_i_info ( dec_info )
|
||||
,.exu_i_ilegl ( dec_o_ilegl )
|
||||
,.exu_i_active ( exu_active )
|
||||
,.bjp_o_wbck_wdat ( bjp_wbck_wdat )
|
||||
,.bjp_o_wbck_valid ( bjp_wbck_valid )
|
||||
,.bjp_update_pc_req ( update_pc_req )
|
||||
,.bjp_update_pc_value ( update_pc_value )
|
||||
,.ext_o_wait_valid ( ext_o_wait_valid )
|
||||
,.ext_o_wait ( ext_wait )
|
||||
,.ext_o_wait_cnt ( ext_wait_cnt )
|
||||
,.ext_o_send ( ext_o_send )
|
||||
,.ext_o_sendc ( ext_o_sendc )
|
||||
,.ext_o_codeword ( ext_o_codeword )
|
||||
,.ext_o_exit ( ext_o_exit )
|
||||
,.ext_o_intr ( ext_o_intr )
|
||||
,.ext_o_wbck_wdat ( ext_wbck_wdat )
|
||||
,.ext_o_wbck_valid ( ext_wbck_valid )
|
||||
,.agu_o_addr ( agu_o_addr )
|
||||
,.agu_o_wdata ( agu_o_wrdata )
|
||||
,.agu_o_wren ( agu_o_wren )
|
||||
,.agu_o_rden ( agu_o_rden )
|
||||
,.agu_o_wmask ( agu_o_wrmask )
|
||||
,.agu_i_rdata ( agu_i_rddata )
|
||||
,.agu_o_addr_unalgn ( agu_o_addr_unalgn )
|
||||
,.agu_o_wbck_wdat ( agu_wbck_wdat )
|
||||
,.agu_o_wbck_valid ( agu_wbck_valid )
|
||||
,.alu_o_wbck_wdat ( alu_wbck_wdat )
|
||||
,.alu_o_wbck_valid ( alu_wbck_valid )
|
||||
);
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
//qbmcu_wbck
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
wire wbck_ena ;
|
||||
wire [`QBMCU_XLEN-1 :0] wbck_wdat ;
|
||||
wire [`QBMCU_RFIDX_WIDTH-1 :0] wbck_rdidx ;
|
||||
|
||||
qbmcu_wbck U_qbmcu_wbck (
|
||||
.clk ( clk )
|
||||
,.rst_n ( rst_n )
|
||||
,.wbck_i_active ( wb_active )
|
||||
,.wbck_i_rdidx ( dec_rdidx )
|
||||
,.wbck_i_rdwen ( dec_rdwen )
|
||||
,.bjp_i_wbck_wdat ( bjp_wbck_wdat )
|
||||
,.bjp_i_wbck_valid ( bjp_wbck_valid )
|
||||
,.agu_i_wbck_wdat ( agu_wbck_wdat )
|
||||
,.agu_i_wbck_valid ( agu_wbck_valid )
|
||||
,.alu_i_wbck_wdat ( alu_wbck_wdat )
|
||||
,.alu_i_wbck_valid ( alu_wbck_valid )
|
||||
,.ext_i_wbck_wdat ( ext_wbck_wdat )
|
||||
,.ext_i_wbck_valid ( ext_wbck_valid )
|
||||
,.wbck_o_ena ( wbck_ena )
|
||||
,.wbck_o_rdidx ( wbck_rdidx )
|
||||
,.wbck_o_wdat ( wbck_wdat )
|
||||
);
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
//qbmcu_regfile
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
qbmcu_regfile U_qbmcu_regfile (
|
||||
.clk ( clk )
|
||||
,.rst_n ( rst_n )
|
||||
,.read_src1_idx ( dec_rs1idx )
|
||||
,.read_src2_idx ( dec_rs2idx )
|
||||
,.read_src1_dat ( exu_rs1 )
|
||||
,.read_src2_dat ( exu_rs2 )
|
||||
,.wbck_dest_wen ( wbck_ena )
|
||||
,.wbck_dest_idx ( wbck_rdidx )
|
||||
,.wbck_dest_dat ( wbck_wdat )
|
||||
);
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
//DW03_updn_ctr
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
defparam U_DW03_updn_ctr.width = 32;
|
||||
DW03_updn_ctr U_DW03_updn_ctr (
|
||||
.clk ( clk )// clock input
|
||||
,.reset ( rst_n )// asynchronous reset input (active low)
|
||||
,.data ( ext_wait_cnt-1'b1 )// data used for load operation
|
||||
,.up_dn ( 1'b0 )// up/down control input (0=down, 1-up)
|
||||
,.load ( !ext_wait )// load operation control input (active low)
|
||||
,.cen ( ext_o_wait_valid )// count enable control input (active high enable)
|
||||
,.count ( )// count value output
|
||||
,.tercnt ( qbmcu_i_timer_done ) // terminal count output flag (active high)
|
||||
);
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
`include "qbmcu_undefines.v"
|
||||
|
|
@ -0,0 +1,113 @@
|
|||
//+FHDR--------------------------------------------------------------------------------------------------------
|
||||
// Company:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// File Name : qbmcu_busdecoder.v
|
||||
// Department :
|
||||
// Author : PWY
|
||||
// Author's Tel :
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Relese History
|
||||
// Version Date Author Description
|
||||
// 1.0 2022-08-25 PWY
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Keywords :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Parameter
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Purpose :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Target Device:
|
||||
// Tool versions:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Reuse Issues
|
||||
// Reset Strategy:
|
||||
// Clock Domains:
|
||||
// Critical Timing:
|
||||
// Asynchronous I/F:
|
||||
// Synthesizable (y/n):
|
||||
// Other:
|
||||
//-FHDR--------------------------------------------------------------------------------------------------------
|
||||
|
||||
`include "qbmcu_defines.v"
|
||||
|
||||
module qbmcu_busdecoder #(
|
||||
parameter S0_BASEADDR = 32'h0010_0000
|
||||
,parameter S1_BASEADDR = 32'h0020_0000
|
||||
)(
|
||||
//rw op port
|
||||
input wren // write enable
|
||||
,input [`QBMCU_XLEN/8-1 :0] wrmask // write mask
|
||||
,input [`QBMCU_XLEN-1 :0] wrdata // write data
|
||||
,input [`QBMCU_ADDR_SIZE-1:0] rwaddr // read & write addr
|
||||
,input rden // read enable
|
||||
,output [`QBMCU_XLEN-1 :0] rddata // read data
|
||||
//data sram read and write signals
|
||||
,output s0_wren // s0 write enable
|
||||
,output [`QBMCU_XLEN/8-1 :0] s0_wrmask // write mask
|
||||
,output [`QBMCU_ADDR_SIZE-1:0] s0_rwaddr // s0 read & write addr
|
||||
,output [`QBMCU_XLEN-1 :0] s0_wrdata // s0 write data
|
||||
,output s0_rden // s0 read enable
|
||||
,input [`QBMCU_XLEN-1 :0] s0_rddata // s0 read data
|
||||
//mcu perips reg read and write signals
|
||||
,output s1_wren // s1 write enable
|
||||
,output [`QBMCU_XLEN/8-1 :0] s1_wrmask // write mask
|
||||
,output [`QBMCU_ADDR_SIZE-1:0] s1_rwaddr // s1 read & write addr
|
||||
,output [`QBMCU_XLEN-1 :0] s1_wrdata // s1 write data
|
||||
,output s1_rden // s1 read enable
|
||||
,input [`QBMCU_XLEN-1 :0] s1_rddata // s1 read data
|
||||
);
|
||||
|
||||
wire s0_sel;
|
||||
wire s1_sel;
|
||||
|
||||
//s0_sel
|
||||
assign s0_sel = (rwaddr[`QBMCU_ADDR_SIZE-1:16] == S0_BASEADDR >> 16);
|
||||
//s1_sel
|
||||
assign s1_sel = (rwaddr[`QBMCU_ADDR_SIZE-1:16] == S1_BASEADDR >> 16);
|
||||
|
||||
|
||||
//s0_wren
|
||||
assign s0_wren = s0_sel & wren;
|
||||
//s1_wren
|
||||
assign s1_wren = s1_sel & wren;
|
||||
|
||||
//s0_wrmask
|
||||
assign s0_wrmask = {`QBMCU_XLEN/8{s0_sel}} & wrmask;
|
||||
//s1_wrmask
|
||||
assign s1_wrmask = {`QBMCU_XLEN/8{s1_sel}} & wrmask;
|
||||
|
||||
//s0_rden
|
||||
assign s0_rden = s0_sel & rden;
|
||||
//s1_rden
|
||||
assign s1_rden = s1_sel & rden;
|
||||
|
||||
|
||||
//s0_rwaddr
|
||||
assign s0_rwaddr = {`QBMCU_ADDR_SIZE{s0_sel}} & rwaddr;
|
||||
//s1_rwaddr
|
||||
assign s1_rwaddr = {`QBMCU_ADDR_SIZE{s1_sel}} & rwaddr;
|
||||
|
||||
//s0_wrdata
|
||||
assign s0_wrdata = {`QBMCU_XLEN{s0_sel}} & wrdata;
|
||||
//s1_wrdata
|
||||
assign s1_wrdata = {`QBMCU_XLEN{s1_sel}} & wrdata;
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- Read data mux
|
||||
//
|
||||
// -- The data from the selected register is
|
||||
// -- placed on a zero-padded 32-bit read data bus.
|
||||
// ------------------------------------------------------
|
||||
|
||||
wire [`QBMCU_XLEN-1:0] rddata_w = {`QBMCU_XLEN{s0_sel}} & s0_rddata
|
||||
| {`QBMCU_XLEN{s1_sel}} & s1_rddata;
|
||||
|
||||
//rddata
|
||||
assign rddata = rddata_w;
|
||||
|
||||
endmodule
|
||||
|
||||
`include "qbmcu_undefines.v"
|
||||
|
|
@ -0,0 +1,69 @@
|
|||
//+FHDR--------------------------------------------------------------------------------------------------------
|
||||
// Company:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// File Name : qbmcu_datalatch.v
|
||||
// Department :
|
||||
// Author : PWY
|
||||
// Author's Tel :
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Relese History
|
||||
// Version Date Author Description
|
||||
// 0.1 2024-03-13 PWY The operation of latch and hold, eliminating invalid toggling to
|
||||
// reduce dynamic power consumption.
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Keywords :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Parameter
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Purpose :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Target Device:
|
||||
// Tool versions:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Reuse Issues
|
||||
// Reset Strategy:
|
||||
// Clock Domains:
|
||||
// Critical Timing:
|
||||
// Asynchronous I/F:
|
||||
// Synthesizable (y/n):
|
||||
// Other:
|
||||
//-FHDR--------------------------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
`include "qbmcu_defines.v"
|
||||
|
||||
module qbmcu_datalatch #(
|
||||
parameter DECINFO_GRP_OP = `QBMCU_DECINFO_GRP_AGU )
|
||||
(
|
||||
input [`QBMCU_XLEN-1 :0] i_rs1
|
||||
,input [`QBMCU_XLEN-1 :0] i_rs2
|
||||
,input [`QBMCU_XLEN-1 :0] i_imm
|
||||
,input [`QBMCU_DECINFO_WIDTH-1 :0] i_info
|
||||
,input [`QBMCU_PC_SIZE-1 :0] i_pc
|
||||
,input i_ilegl
|
||||
|
||||
,output [`QBMCU_XLEN-1 :0] o_rs1
|
||||
,output [`QBMCU_XLEN-1 :0] o_rs2
|
||||
,output [`QBMCU_XLEN-1 :0] o_imm
|
||||
,output [`QBMCU_DECINFO_WIDTH-1 :0] o_info
|
||||
,output [`QBMCU_PC_SIZE-1 :0] o_pc
|
||||
,output o_op
|
||||
);
|
||||
|
||||
|
||||
wire op = (~i_ilegl) & (i_info[`QBMCU_DECINFO_GRP] == DECINFO_GRP_OP);
|
||||
|
||||
|
||||
assign o_rs1 = {`QBMCU_XLEN {op}} & i_rs1 ;
|
||||
assign o_rs2 = {`QBMCU_XLEN {op}} & i_rs2 ;
|
||||
assign o_imm = {`QBMCU_XLEN {op}} & i_imm ;
|
||||
assign o_info = {`QBMCU_DECINFO_WIDTH{op}} & i_info ;
|
||||
assign o_pc = {`QBMCU_PC_SIZE {op}} & i_pc ;
|
||||
|
||||
assign o_op = op;
|
||||
|
||||
endmodule
|
||||
`include "qbmcu_undefines.v"
|
||||
|
|
@ -0,0 +1,480 @@
|
|||
//+FHDR--------------------------------------------------------------------------------------------------------
|
||||
// Company:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// File Name : qbmcu_decode.v
|
||||
// Department :
|
||||
// Author : PWY
|
||||
// Author's Tel :
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Relese History
|
||||
// Version Date Author Description
|
||||
// 0.1 2024-03-13 PWY The decode module to decode the instruction details
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Keywords :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Parameter
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Purpose :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Target Device:
|
||||
// Tool versions:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Reuse Issues
|
||||
// Reset Strategy:
|
||||
// Clock Domains:
|
||||
// Critical Timing:
|
||||
// Asynchronous I/F:
|
||||
// Synthesizable (y/n):
|
||||
// Other:
|
||||
//-FHDR--------------------------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
`include "qbmcu_defines.v"
|
||||
|
||||
module qbmcu_decode(
|
||||
input clk // System Clock
|
||||
,input rst_n // System reset,active low
|
||||
,input dec_i_active // DEC module Active from MCU FSM
|
||||
//////////////////////////////////////////////////////////////
|
||||
// The IR stage to Decoder
|
||||
,input [`QBMCU_INSTR_SIZE-1 :0] dec_i_instr
|
||||
,input [`QBMCU_PC_SIZE-1 :0] dec_i_pc
|
||||
|
||||
//////////////////////////////////////////////////////////////
|
||||
// The Decoded Info-Bus
|
||||
//,output dec_o_rs1en
|
||||
//,output dec_o_rs2en
|
||||
,output dec_o_rdwen
|
||||
,output [`QBMCU_RFIDX_WIDTH-1 :0] dec_o_rs1idx
|
||||
,output [`QBMCU_RFIDX_WIDTH-1 :0] dec_o_rs2idx
|
||||
,output [`QBMCU_RFIDX_WIDTH-1 :0] dec_o_rdidx
|
||||
,output [`QBMCU_DECINFO_WIDTH-1:0] dec_o_info
|
||||
,output [`QBMCU_XLEN-1 :0] dec_o_imm
|
||||
,output [`QBMCU_PC_SIZE-1 :0] dec_o_pc
|
||||
,output dec_o_ilegl
|
||||
);
|
||||
|
||||
wire dec_i_active_r;
|
||||
wire [`QBMCU_DECINFO_WIDTH-1:0] dec_info_w;
|
||||
|
||||
//dec_i_active_r
|
||||
//sirv_gnrl_dffr #(1) dec_i_active_r_dffr (dec_i_active, dec_i_active_r, clk, rst_n);
|
||||
assign dec_i_active_r = dec_i_active;
|
||||
|
||||
///////////////////////////////////////////////////////////////
|
||||
//Instruction decoding
|
||||
///////////////////////////////////////////////////////////////
|
||||
wire [32-1:0] rv32_instr = dec_i_instr;
|
||||
|
||||
wire [6:0] opcode = rv32_instr[6:0];
|
||||
|
||||
//wire opcode_1_0_00 = (opcode[1:0] == 2'b00);
|
||||
//wire opcode_1_0_01 = (opcode[1:0] == 2'b01);
|
||||
//wire opcode_1_0_10 = (opcode[1:0] == 2'b10);
|
||||
wire opcode_1_0_11 = (opcode[1:0] == 2'b11);
|
||||
|
||||
wire rv32 = (~(dec_i_instr[4:2] == 3'b111)) & opcode_1_0_11;
|
||||
|
||||
wire [4:0] rv32_rd = rv32_instr[11:7];
|
||||
wire [2:0] rv32_func3 = rv32_instr[14:12];
|
||||
wire [4:0] rv32_rs1 = rv32_instr[19:15];
|
||||
wire [4:0] rv32_rs2 = rv32_instr[24:20];
|
||||
wire [6:0] rv32_func7 = rv32_instr[31:25];
|
||||
|
||||
// We generate the signals and reused them as much as possible to save gatecounts
|
||||
wire opcode_4_2_000 = (opcode[4:2] == 3'b000);
|
||||
wire opcode_4_2_001 = (opcode[4:2] == 3'b001);
|
||||
wire opcode_4_2_010 = (opcode[4:2] == 3'b010);
|
||||
wire opcode_4_2_011 = (opcode[4:2] == 3'b011);
|
||||
wire opcode_4_2_100 = (opcode[4:2] == 3'b100);
|
||||
wire opcode_4_2_101 = (opcode[4:2] == 3'b101);
|
||||
//wire opcode_4_2_110 = (opcode[4:2] == 3'b110);
|
||||
wire opcode_4_2_111 = (opcode[4:2] == 3'b111);
|
||||
wire opcode_6_5_00 = (opcode[6:5] == 2'b00);
|
||||
wire opcode_6_5_01 = (opcode[6:5] == 2'b01);
|
||||
//wire opcode_6_5_10 = (opcode[6:5] == 2'b10);
|
||||
wire opcode_6_5_11 = (opcode[6:5] == 2'b11);
|
||||
|
||||
wire rv32_func3_000 = (rv32_func3 == 3'b000);
|
||||
wire rv32_func3_001 = (rv32_func3 == 3'b001);
|
||||
wire rv32_func3_010 = (rv32_func3 == 3'b010);
|
||||
wire rv32_func3_011 = (rv32_func3 == 3'b011);
|
||||
wire rv32_func3_100 = (rv32_func3 == 3'b100);
|
||||
wire rv32_func3_101 = (rv32_func3 == 3'b101);
|
||||
wire rv32_func3_110 = (rv32_func3 == 3'b110);
|
||||
wire rv32_func3_111 = (rv32_func3 == 3'b111);
|
||||
|
||||
wire rv32_func7_0000000 = (rv32_func7 == 7'b0000000);
|
||||
wire rv32_func7_0100000 = (rv32_func7 == 7'b0100000);
|
||||
wire rv32_func7_1111111 = (rv32_func7 == 7'b1111111);
|
||||
|
||||
|
||||
wire rv32_rs1_x0 = (rv32_rs1 == 5'b00000);
|
||||
wire rv32_rs2_x0 = (rv32_rs2 == 5'b00000);
|
||||
//wire rv32_rs2_x1 = (rv32_rs2 == 5'b00001);
|
||||
wire rv32_rd_x0 = (rv32_rd == 5'b00000);
|
||||
//wire rv32_rd_x2 = (rv32_rd == 5'b00010);
|
||||
|
||||
wire rv32_rs1_x31 = (rv32_rs1 == 5'b11111);
|
||||
wire rv32_rs2_x31 = (rv32_rs2 == 5'b11111);
|
||||
wire rv32_rd_x31 = (rv32_rd == 5'b11111);
|
||||
|
||||
wire rv32_load = opcode_6_5_00 & opcode_4_2_000 & opcode_1_0_11; //LB
|
||||
wire rv32_store = opcode_6_5_01 & opcode_4_2_000 & opcode_1_0_11; //SB
|
||||
|
||||
wire rv32_branch = opcode_6_5_11 & opcode_4_2_000 & opcode_1_0_11; //B
|
||||
|
||||
wire rv32_jalr = opcode_6_5_11 & opcode_4_2_001 & opcode_1_0_11; //JALR
|
||||
|
||||
wire rv32_custom0 = opcode_6_5_00 & opcode_4_2_010 & opcode_1_0_11; //WAIT SENDC SEND
|
||||
wire rv32_custom1 = opcode_6_5_01 & opcode_4_2_010 & opcode_1_0_11; //EXIT EXIT_IRQ
|
||||
|
||||
wire rv32_jal = opcode_6_5_11 & opcode_4_2_011 & opcode_1_0_11; //JAL
|
||||
|
||||
wire rv32_op_imm = opcode_6_5_00 & opcode_4_2_100 & opcode_1_0_11; //ADDI
|
||||
wire rv32_op = opcode_6_5_01 & opcode_4_2_100 & opcode_1_0_11; //ADD
|
||||
|
||||
wire rv32_auipc = opcode_6_5_00 & opcode_4_2_101 & opcode_1_0_11; //AUIPC
|
||||
wire rv32_lui = opcode_6_5_01 & opcode_4_2_101 & opcode_1_0_11; //LUI
|
||||
|
||||
|
||||
// ===========================================================================
|
||||
// Branch Instructions
|
||||
wire rv32_beq = rv32_branch & rv32_func3_000; //B beq
|
||||
wire rv32_bne = rv32_branch & rv32_func3_001; //B bne
|
||||
wire rv32_blt = rv32_branch & rv32_func3_100; //B blt
|
||||
wire rv32_bgt = rv32_branch & rv32_func3_101; //B bge
|
||||
wire rv32_bltu = rv32_branch & rv32_func3_110; //B bltu
|
||||
wire rv32_bgtu = rv32_branch & rv32_func3_111; //B bgeu
|
||||
|
||||
|
||||
// ===========================================================================
|
||||
// The Branch and system group of instructions will be handled by BJP
|
||||
|
||||
wire dec_jal = rv32_jal ;
|
||||
wire dec_jalr = rv32_jalr;
|
||||
wire dec_bxx = rv32_branch;
|
||||
wire dec_bjp = dec_jal | dec_jalr | dec_bxx;
|
||||
|
||||
wire bjp_op = dec_bjp ;
|
||||
|
||||
wire [`QBMCU_DECINFO_BJP_WIDTH-1:0] bjp_info_bus;
|
||||
assign bjp_info_bus[`QBMCU_DECINFO_GRP ] = `QBMCU_DECINFO_GRP_BJP;
|
||||
assign bjp_info_bus[`QBMCU_DECINFO_RV32 ] = rv32;
|
||||
assign bjp_info_bus[`QBMCU_DECINFO_BJP_JUMP ] = dec_jal | dec_jalr;
|
||||
assign bjp_info_bus[`QBMCU_DECINFO_BJP_JALR ] = dec_jalr;
|
||||
assign bjp_info_bus[`QBMCU_DECINFO_BJP_BEQ ] = rv32_beq ;
|
||||
assign bjp_info_bus[`QBMCU_DECINFO_BJP_BNE ] = rv32_bne ;
|
||||
assign bjp_info_bus[`QBMCU_DECINFO_BJP_BLT ] = rv32_blt;
|
||||
assign bjp_info_bus[`QBMCU_DECINFO_BJP_BGT ] = rv32_bgt ;
|
||||
assign bjp_info_bus[`QBMCU_DECINFO_BJP_BLTU ] = rv32_bltu;
|
||||
assign bjp_info_bus[`QBMCU_DECINFO_BJP_BGTU ] = rv32_bgtu;
|
||||
assign bjp_info_bus[`QBMCU_DECINFO_BJP_BXX ] = dec_bxx;
|
||||
|
||||
|
||||
// ===========================================================================
|
||||
// ALU Instructions
|
||||
wire rv32_addi = rv32_op_imm & rv32_func3_000; // I addi
|
||||
wire rv32_slti = rv32_op_imm & rv32_func3_010; // I slti
|
||||
wire rv32_sltiu = rv32_op_imm & rv32_func3_011; // I sltiu
|
||||
wire rv32_xori = rv32_op_imm & rv32_func3_100; // I xori
|
||||
wire rv32_ori = rv32_op_imm & rv32_func3_110; // I ori
|
||||
wire rv32_andi = rv32_op_imm & rv32_func3_111; // I andi
|
||||
|
||||
wire rv32_slli = rv32_op_imm & rv32_func3_001 & (rv32_instr[31:26] == 6'b000000); // I slli
|
||||
wire rv32_srli = rv32_op_imm & rv32_func3_101 & (rv32_instr[31:26] == 6'b000000); // I srli
|
||||
wire rv32_srai = rv32_op_imm & rv32_func3_101 & (rv32_instr[31:26] == 6'b010000); // I srai
|
||||
|
||||
wire rv32_sxxi_shamt_legl = (rv32_instr[25] == 1'b0); //shamt[5] must be zero for RV32I
|
||||
wire rv32_sxxi_shamt_ilgl = (rv32_slli | rv32_srli | rv32_srai) & (~rv32_sxxi_shamt_legl);
|
||||
|
||||
wire rv32_add = rv32_op & rv32_func3_000 & rv32_func7_0000000; // R add
|
||||
wire rv32_sub = rv32_op & rv32_func3_000 & rv32_func7_0100000; // R sub
|
||||
wire rv32_sll = rv32_op & rv32_func3_001 & rv32_func7_0000000; // R sll
|
||||
wire rv32_slt = rv32_op & rv32_func3_010 & rv32_func7_0000000; // R slt
|
||||
wire rv32_sltu = rv32_op & rv32_func3_011 & rv32_func7_0000000; // R sltu
|
||||
wire rv32_xor = rv32_op & rv32_func3_100 & rv32_func7_0000000; // R xor
|
||||
wire rv32_srl = rv32_op & rv32_func3_101 & rv32_func7_0000000; // R srl
|
||||
wire rv32_sra = rv32_op & rv32_func3_101 & rv32_func7_0100000; // R sra
|
||||
wire rv32_or = rv32_op & rv32_func3_110 & rv32_func7_0000000; // R or
|
||||
wire rv32_and = rv32_op & rv32_func3_111 & rv32_func7_0000000; // R and
|
||||
|
||||
wire rv32_nop = rv32_addi & rv32_rs1_x0 & rv32_rd_x0 & (~(|rv32_instr[31:20]));
|
||||
|
||||
wire alu_op = (~rv32_sxxi_shamt_ilgl) &
|
||||
( rv32_op_imm
|
||||
| rv32_op
|
||||
| rv32_auipc
|
||||
| rv32_lui
|
||||
| rv32_nop)
|
||||
;
|
||||
wire need_imm;
|
||||
wire [`QBMCU_DECINFO_ALU_WIDTH-1:0] alu_info_bus;
|
||||
assign alu_info_bus[`QBMCU_DECINFO_GRP ] = `QBMCU_DECINFO_GRP_ALU;
|
||||
assign alu_info_bus[`QBMCU_DECINFO_RV32 ] = rv32;
|
||||
assign alu_info_bus[`QBMCU_DECINFO_ALU_ADD ] = rv32_add | rv32_addi | rv32_auipc ;
|
||||
assign alu_info_bus[`QBMCU_DECINFO_ALU_SUB ] = rv32_sub ;
|
||||
assign alu_info_bus[`QBMCU_DECINFO_ALU_SLT ] = rv32_slt | rv32_slti;
|
||||
assign alu_info_bus[`QBMCU_DECINFO_ALU_SLTU ] = rv32_sltu | rv32_sltiu;
|
||||
assign alu_info_bus[`QBMCU_DECINFO_ALU_XOR ] = rv32_xor | rv32_xori ;
|
||||
assign alu_info_bus[`QBMCU_DECINFO_ALU_SLL ] = rv32_sll | rv32_slli ;
|
||||
assign alu_info_bus[`QBMCU_DECINFO_ALU_SRL ] = rv32_srl | rv32_srli ;
|
||||
assign alu_info_bus[`QBMCU_DECINFO_ALU_SRA ] = rv32_sra | rv32_srai ;
|
||||
assign alu_info_bus[`QBMCU_DECINFO_ALU_OR ] = rv32_or | rv32_ori ;
|
||||
assign alu_info_bus[`QBMCU_DECINFO_ALU_AND ] = rv32_and | rv32_andi ;
|
||||
assign alu_info_bus[`QBMCU_DECINFO_ALU_LUI ] = rv32_lui ;
|
||||
assign alu_info_bus[`QBMCU_DECINFO_ALU_OP2IMM] = need_imm;
|
||||
assign alu_info_bus[`QBMCU_DECINFO_ALU_OP1PC ] = rv32_auipc;
|
||||
assign alu_info_bus[`QBMCU_DECINFO_ALU_NOP ] = rv32_nop;
|
||||
|
||||
// ===========================================================================
|
||||
// Load/Store Instructions
|
||||
//wire rv32_lb = rv32_load & rv32_func3_000; // I lb
|
||||
//wire rv32_lh = rv32_load & rv32_func3_001; // I lh
|
||||
//wire rv32_lw = rv32_load & rv32_func3_010; // I lw
|
||||
//wire rv32_lbu = rv32_load & rv32_func3_100; // I lbu
|
||||
//wire rv32_lhu = rv32_load & rv32_func3_101; // I lhu
|
||||
|
||||
//wire rv32_sb = rv32_store & rv32_func3_000; // S sb
|
||||
//wire rv32_sh = rv32_store & rv32_func3_001; // S sh
|
||||
//wire rv32_sw = rv32_store & rv32_func3_010; // S sw
|
||||
|
||||
|
||||
// Load/Store Data Size
|
||||
wire [1:0] lsu_info_size = rv32_func3[1:0] ;
|
||||
// Load/Store Data Sign
|
||||
wire lsu_info_usign = rv32_func3[2];
|
||||
|
||||
|
||||
wire ldst_op = rv32_load | rv32_store;
|
||||
|
||||
wire [`QBMCU_DECINFO_AGU_WIDTH-1:0] agu_info_bus;
|
||||
assign agu_info_bus[`QBMCU_DECINFO_GRP ] = `QBMCU_DECINFO_GRP_AGU;
|
||||
assign agu_info_bus[`QBMCU_DECINFO_RV32 ] = rv32;
|
||||
assign agu_info_bus[`QBMCU_DECINFO_AGU_LOAD ] = rv32_load ;
|
||||
assign agu_info_bus[`QBMCU_DECINFO_AGU_STORE ] = rv32_store ;
|
||||
assign agu_info_bus[`QBMCU_DECINFO_AGU_SIZE ] = lsu_info_size;
|
||||
assign agu_info_bus[`QBMCU_DECINFO_AGU_USIGN ] = lsu_info_usign;
|
||||
assign agu_info_bus[`QBMCU_DECINFO_AGU_OP2IMM ] = need_imm;
|
||||
|
||||
// ===========================================================================
|
||||
// Expand instructions : WAIT SEND SENC EXIT EiXT_IRQ
|
||||
wire rv32_wait = rv32_custom0 & rv32_func3_000; //WAIT
|
||||
wire rv32_send = rv32_custom0 & rv32_func3_010; //SEND
|
||||
wire rv32_sendc = rv32_custom0 & rv32_func3_011; //WAIT
|
||||
|
||||
wire rv32_exit = rv32_custom1 & rv32_func3_000; //EXIT
|
||||
wire rv32_exiti = rv32_custom1 & rv32_func3_001; //EXIT_IRQ
|
||||
|
||||
wire ext_op = (~rv32_sxxi_shamt_ilgl) &
|
||||
( rv32_wait
|
||||
| rv32_send
|
||||
| rv32_sendc
|
||||
| rv32_exit
|
||||
| rv32_exiti)
|
||||
;
|
||||
wire [`QBMCU_DECINFO_EXT_WIDTH-1:0] ext_info_bus;
|
||||
assign ext_info_bus[`QBMCU_DECINFO_GRP ] = `QBMCU_DECINFO_GRP_EXT;
|
||||
assign ext_info_bus[`QBMCU_DECINFO_RV32 ] = rv32;
|
||||
assign ext_info_bus[`QBMCU_DECINFO_EXT_WAIT ] = rv32_wait;
|
||||
assign ext_info_bus[`QBMCU_DECINFO_EXT_SEND ] = rv32_send;
|
||||
assign ext_info_bus[`QBMCU_DECINFO_EXT_SENDC ] = rv32_sendc;
|
||||
assign ext_info_bus[`QBMCU_DECINFO_EXT_EXIT ] = rv32_exit;
|
||||
assign ext_info_bus[`QBMCU_DECINFO_EXT_EXITI ] = rv32_exiti ;
|
||||
assign ext_info_bus[`QBMCU_DECINFO_EXT_OP2IMM] = need_imm;
|
||||
|
||||
|
||||
// Reuse the common signals as much as possible to save gatecounts
|
||||
wire rv32_all0s_ilgl = rv32_func7_0000000
|
||||
& rv32_rs2_x0
|
||||
& rv32_rs1_x0
|
||||
& rv32_func3_000
|
||||
& rv32_rd_x0
|
||||
& opcode_6_5_00
|
||||
& opcode_4_2_000
|
||||
& (opcode[1:0] == 2'b00);
|
||||
|
||||
wire rv32_all1s_ilgl = rv32_func7_1111111
|
||||
& rv32_rs2_x31
|
||||
& rv32_rs1_x31
|
||||
& rv32_func3_111
|
||||
& rv32_rd_x31
|
||||
& opcode_6_5_11
|
||||
& opcode_4_2_111
|
||||
& (opcode[1:0] == 2'b11);
|
||||
|
||||
|
||||
wire rv_all0s1s_ilgl = (rv32_all0s_ilgl | rv32_all1s_ilgl);
|
||||
|
||||
//
|
||||
// All the RV32I need RD register except the
|
||||
// * Branch, Store,
|
||||
wire rv32_need_rd = (~rv32_rd_x0 )
|
||||
& (~rv32_branch )
|
||||
& (~rv32_store )
|
||||
& (~rv32_custom1);
|
||||
|
||||
// All the RV32I need RS1 register except the
|
||||
// * lui
|
||||
// * auipc
|
||||
// * jal
|
||||
//wire rv32_need_rs1 = (~rv32_rs1_x0)
|
||||
// & (~rv32_lui )
|
||||
// & (~rv32_auipc )
|
||||
// & (~rv32_jal );
|
||||
|
||||
// Following RV32IMA instructions need RS2 register
|
||||
// * branch
|
||||
// * store
|
||||
// * rv32_op
|
||||
//wire rv32_need_rs2 = (~rv32_rs2_x0)
|
||||
// & ((rv32_branch)
|
||||
// | (rv32_store )
|
||||
// | (rv32_op ));
|
||||
|
||||
wire [31:0] rv32_i_imm = {
|
||||
{20{rv32_instr[31]}}
|
||||
, rv32_instr[31:20]
|
||||
};
|
||||
|
||||
wire [31:0] rv32_s_imm = {
|
||||
{20{rv32_instr[31]}}
|
||||
, rv32_instr[31:25]
|
||||
, rv32_instr[11:7]
|
||||
};
|
||||
|
||||
|
||||
wire [31:0] rv32_b_imm = {
|
||||
{19{rv32_instr[31]}}
|
||||
, rv32_instr[31]
|
||||
, rv32_instr[7]
|
||||
, rv32_instr[30:25]
|
||||
, rv32_instr[11:8]
|
||||
, 1'b0
|
||||
};
|
||||
|
||||
wire [31:0] rv32_u_imm = {rv32_instr[31:12],12'b0};
|
||||
|
||||
wire [31:0] rv32_j_imm = {
|
||||
{11{rv32_instr[31]}}
|
||||
, rv32_instr[31]
|
||||
, rv32_instr[19:12]
|
||||
, rv32_instr[20]
|
||||
, rv32_instr[30:21]
|
||||
, 1'b0
|
||||
};
|
||||
//expand immediate operands
|
||||
wire [31:0] rv32_e_imm = rv32_i_imm;
|
||||
|
||||
// It will select i-type immediate when
|
||||
// * rv32_op_imm
|
||||
// * rv32_jalr
|
||||
// * rv32_load
|
||||
wire rv32_imm_sel_i = rv32_op_imm | rv32_jalr | rv32_load;
|
||||
//wire rv32_imm_sel_jalr = rv32_jalr;
|
||||
//wire [31:0] rv32_jalr_imm = rv32_i_imm;
|
||||
|
||||
// It will select u-type immediate when
|
||||
// * rv32_lui, rv32_auipc
|
||||
wire rv32_imm_sel_u = rv32_lui | rv32_auipc;
|
||||
|
||||
// It will select j-type immediate when
|
||||
// * rv32_jal
|
||||
wire rv32_imm_sel_j = rv32_jal;
|
||||
//wire rv32_imm_sel_jal = rv32_jal;
|
||||
//wire [31:0] rv32_jal_imm = rv32_j_imm;
|
||||
|
||||
// It will select b-type immediate when
|
||||
// * rv32_branch
|
||||
wire rv32_imm_sel_b = rv32_branch;
|
||||
//wire rv32_imm_sel_bxx = rv32_branch;
|
||||
//wire [31:0] rv32_bxx_imm = rv32_b_imm;
|
||||
|
||||
// It will select s-type immediate when
|
||||
// * rv32_store
|
||||
wire rv32_imm_sel_s = rv32_store;
|
||||
|
||||
// It will select e-type immediate when
|
||||
// * rv32_custom0
|
||||
// * rv32_custom1
|
||||
wire rv32_imm_sel_e = rv32_custom0 | rv32_custom1;
|
||||
|
||||
|
||||
wire [31:0] rv32_imm =
|
||||
({32{rv32_imm_sel_i}} & rv32_i_imm)
|
||||
| ({32{rv32_imm_sel_s}} & rv32_s_imm)
|
||||
| ({32{rv32_imm_sel_b}} & rv32_b_imm)
|
||||
| ({32{rv32_imm_sel_u}} & rv32_u_imm)
|
||||
| ({32{rv32_imm_sel_j}} & rv32_j_imm)
|
||||
| ({32{rv32_imm_sel_e}} & rv32_e_imm)
|
||||
;
|
||||
|
||||
wire rv32_need_imm =
|
||||
rv32_imm_sel_i
|
||||
| rv32_imm_sel_s
|
||||
| rv32_imm_sel_b
|
||||
| rv32_imm_sel_u
|
||||
| rv32_imm_sel_j
|
||||
| rv32_imm_sel_e
|
||||
;
|
||||
|
||||
|
||||
assign need_imm = rv32_need_imm ;
|
||||
|
||||
//dec_o_imm
|
||||
sirv_gnrl_dfflr #(`QBMCU_XLEN) dec_o_imm_dfflr (dec_i_active_r, rv32_imm, dec_o_imm, clk, rst_n);
|
||||
|
||||
//dec_o_pc
|
||||
sirv_gnrl_dfflr #(`QBMCU_PC_SIZE) dec_o_pc_dfflr (dec_i_active_r, dec_i_pc, dec_o_pc, clk, rst_n);
|
||||
|
||||
|
||||
assign dec_info_w =
|
||||
({`QBMCU_DECINFO_WIDTH{alu_op}} & {{`QBMCU_DECINFO_WIDTH-`QBMCU_DECINFO_ALU_WIDTH{1'b0}},alu_info_bus})
|
||||
| ({`QBMCU_DECINFO_WIDTH{ldst_op}} & {{`QBMCU_DECINFO_WIDTH-`QBMCU_DECINFO_AGU_WIDTH{1'b0}},agu_info_bus})
|
||||
| ({`QBMCU_DECINFO_WIDTH{bjp_op}} & {{`QBMCU_DECINFO_WIDTH-`QBMCU_DECINFO_BJP_WIDTH{1'b0}},bjp_info_bus})
|
||||
| ({`QBMCU_DECINFO_WIDTH{ext_op}} & {{`QBMCU_DECINFO_WIDTH-`QBMCU_DECINFO_EXT_WIDTH{1'b0}},ext_info_bus})
|
||||
;
|
||||
|
||||
//dec_o_info
|
||||
sirv_gnrl_dfflr #(`QBMCU_DECINFO_WIDTH) dec_o_info_dfflr (dec_i_active_r, dec_info_w, dec_o_info, clk, rst_n);
|
||||
|
||||
|
||||
//dec_o_rs1idx
|
||||
sirv_gnrl_dfflr #(`QBMCU_RFIDX_WIDTH) dec_o_rs1idx_dfflr (dec_i_active_r, rv32_rs1[`QBMCU_RFIDX_WIDTH-1:0], dec_o_rs1idx, clk, rst_n);
|
||||
//dec_o_rs2idx
|
||||
sirv_gnrl_dfflr #(`QBMCU_RFIDX_WIDTH) dec_o_rs2idx_dfflr (dec_i_active_r, rv32_rs2[`QBMCU_RFIDX_WIDTH-1:0], dec_o_rs2idx, clk, rst_n);
|
||||
//dec_o_rdidx
|
||||
sirv_gnrl_dfflr #(`QBMCU_RFIDX_WIDTH) dec_o_rdidx_dfflr (dec_i_active_r, rv32_rd[`QBMCU_RFIDX_WIDTH-1:0], dec_o_rdidx, clk, rst_n);
|
||||
|
||||
//dec_o_rs1en
|
||||
//sirv_gnrl_dfflr #(1) dec_o_rs1en_dfflr (dec_i_active_r, rv32_need_rs1, dec_o_rs1en, clk, rst_n);
|
||||
//dec_o_rs2en
|
||||
//sirv_gnrl_dfflr #(1) dec_o_rs2en_dfflr (dec_i_active_r, rv32_need_rs2, dec_o_rs2en, clk, rst_n);
|
||||
//dec_o_rdwen
|
||||
sirv_gnrl_dfflr #(1) dec_o_rdwen_dfflr (dec_i_active_r, rv32_need_rd, dec_o_rdwen, clk, rst_n);
|
||||
|
||||
wire legl_ops =
|
||||
alu_op
|
||||
| ldst_op
|
||||
| bjp_op
|
||||
| ext_op
|
||||
;
|
||||
|
||||
wire rv_index_ilgl = 1'b0;
|
||||
|
||||
|
||||
wire dec_ilegl_w =
|
||||
(rv_all0s1s_ilgl)
|
||||
| (rv_index_ilgl)
|
||||
| (rv32_sxxi_shamt_ilgl)
|
||||
| (~legl_ops);
|
||||
|
||||
//dec_o_ilegl
|
||||
sirv_gnrl_dfflr #(1) dec_o_ilegl_dfflr (dec_i_active_r, dec_ilegl_w, dec_o_ilegl, clk, rst_n);
|
||||
endmodule
|
||||
|
||||
|
||||
`include "qbmcu_undefines.v"
|
||||
|
|
@ -0,0 +1,223 @@
|
|||
//+FHDR--------------------------------------------------------------------------------------------------------
|
||||
// Company:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// File Name : qbmcu.v
|
||||
// Department :
|
||||
// Author : PWY
|
||||
// Author's Tel :
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Relese History
|
||||
// Version Date Author Description
|
||||
// 0.1 2024-03-13 PWY The files to include all the macro defines
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Keywords :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Parameter
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Purpose :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Target Device:
|
||||
// Tool versions:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Reuse Issues
|
||||
// Reset Strategy:
|
||||
// Clock Domains:
|
||||
// Critical Timing:
|
||||
// Asynchronous I/F:
|
||||
// Synthesizable (y/n):
|
||||
// Other:
|
||||
//-FHDR--------------------------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
/////// ISA relevant macro
|
||||
//
|
||||
//system address width
|
||||
`define QBMCU_ADDR_SIZE 32
|
||||
|
||||
//PC width
|
||||
`define QBMCU_PC_SIZE 32
|
||||
|
||||
//system data width
|
||||
`define QBMCU_XLEN 32
|
||||
//system instruction width
|
||||
`define QBMCU_INSTR_SIZE 32
|
||||
|
||||
//register array index bit width
|
||||
`define QBMCU_RFIDX_WIDTH 5
|
||||
//number of register arrays
|
||||
`define QBMCU_RFREG_NUM 32
|
||||
|
||||
//base address of instruction memory
|
||||
//initial value of the program counter (PC) -> 0x0000_0000
|
||||
`define QBMCU_ITCM_ADDR_BASE 32'h0000_0000
|
||||
//base address of data memory
|
||||
`define QBMCU_DTCM_ADDR_BASE 32'h0010_0000
|
||||
|
||||
//data memory address width
|
||||
`define QBMCU_DTCM_ADDR_SIZE 15
|
||||
|
||||
//instruction memory address width
|
||||
`define QBMCU_ITCM_ADDR_SIZE 15
|
||||
|
||||
//BUS memory address width
|
||||
`define QBMCU_BUS_ADDR_SIZE 25
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
/////// ALU relevant macro
|
||||
//
|
||||
|
||||
`define QBMCU_ALU_ADDER_WIDTH (`QBMCU_XLEN+1)
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
/////// Decode relevant macro
|
||||
//
|
||||
`define QBMCU_DECINFO_GRP_WIDTH 3
|
||||
`define QBMCU_DECINFO_GRP_ALU `QBMCU_DECINFO_GRP_WIDTH'd0
|
||||
`define QBMCU_DECINFO_GRP_AGU `QBMCU_DECINFO_GRP_WIDTH'd1
|
||||
`define QBMCU_DECINFO_GRP_BJP `QBMCU_DECINFO_GRP_WIDTH'd2
|
||||
`define QBMCU_DECINFO_GRP_EXT `QBMCU_DECINFO_GRP_WIDTH'd3
|
||||
|
||||
|
||||
`define QBMCU_DECINFO_GRP_LSB 0
|
||||
`define QBMCU_DECINFO_GRP_MSB (`QBMCU_DECINFO_GRP_LSB+`QBMCU_DECINFO_GRP_WIDTH-1)
|
||||
`define QBMCU_DECINFO_GRP `QBMCU_DECINFO_GRP_MSB:`QBMCU_DECINFO_GRP_LSB
|
||||
`define QBMCU_DECINFO_RV32_LSB (`QBMCU_DECINFO_GRP_MSB+1)
|
||||
`define QBMCU_DECINFO_RV32_MSB (`QBMCU_DECINFO_RV32_LSB+1-1)
|
||||
`define QBMCU_DECINFO_RV32 `QBMCU_DECINFO_RV32_MSB:`QBMCU_DECINFO_RV32_LSB
|
||||
|
||||
`define QBMCU_DECINFO_SUBDECINFO_LSB (`QBMCU_DECINFO_RV32_MSB+1)
|
||||
|
||||
// ALU group
|
||||
`define QBMCU_DECINFO_ALU_ADD_LSB `QBMCU_DECINFO_SUBDECINFO_LSB
|
||||
`define QBMCU_DECINFO_ALU_ADD_MSB (`QBMCU_DECINFO_ALU_ADD_LSB+1-1)
|
||||
`define QBMCU_DECINFO_ALU_ADD `QBMCU_DECINFO_ALU_ADD_MSB :`QBMCU_DECINFO_ALU_ADD_LSB
|
||||
`define QBMCU_DECINFO_ALU_SUB_LSB (`QBMCU_DECINFO_ALU_ADD_MSB+1)
|
||||
`define QBMCU_DECINFO_ALU_SUB_MSB (`QBMCU_DECINFO_ALU_SUB_LSB+1-1)
|
||||
`define QBMCU_DECINFO_ALU_SUB `QBMCU_DECINFO_ALU_SUB_MSB :`QBMCU_DECINFO_ALU_SUB_LSB
|
||||
`define QBMCU_DECINFO_ALU_XOR_LSB (`QBMCU_DECINFO_ALU_SUB_MSB+1)
|
||||
`define QBMCU_DECINFO_ALU_XOR_MSB (`QBMCU_DECINFO_ALU_XOR_LSB+1-1)
|
||||
`define QBMCU_DECINFO_ALU_XOR `QBMCU_DECINFO_ALU_XOR_MSB :`QBMCU_DECINFO_ALU_XOR_LSB
|
||||
`define QBMCU_DECINFO_ALU_SLL_LSB (`QBMCU_DECINFO_ALU_XOR_MSB+1)
|
||||
`define QBMCU_DECINFO_ALU_SLL_MSB (`QBMCU_DECINFO_ALU_SLL_LSB+1-1)
|
||||
`define QBMCU_DECINFO_ALU_SLL `QBMCU_DECINFO_ALU_SLL_MSB :`QBMCU_DECINFO_ALU_SLL_LSB
|
||||
`define QBMCU_DECINFO_ALU_SRL_LSB (`QBMCU_DECINFO_ALU_SLL_MSB+1)
|
||||
`define QBMCU_DECINFO_ALU_SRL_MSB (`QBMCU_DECINFO_ALU_SRL_LSB+1-1)
|
||||
`define QBMCU_DECINFO_ALU_SRL `QBMCU_DECINFO_ALU_SRL_MSB :`QBMCU_DECINFO_ALU_SRL_LSB
|
||||
`define QBMCU_DECINFO_ALU_SRA_LSB (`QBMCU_DECINFO_ALU_SRL_MSB+1)
|
||||
`define QBMCU_DECINFO_ALU_SRA_MSB (`QBMCU_DECINFO_ALU_SRA_LSB+1-1)
|
||||
`define QBMCU_DECINFO_ALU_SRA `QBMCU_DECINFO_ALU_SRA_MSB :`QBMCU_DECINFO_ALU_SRA_LSB
|
||||
`define QBMCU_DECINFO_ALU_OR_LSB (`QBMCU_DECINFO_ALU_SRA_MSB+1)
|
||||
`define QBMCU_DECINFO_ALU_OR_MSB (`QBMCU_DECINFO_ALU_OR_LSB+1-1)
|
||||
`define QBMCU_DECINFO_ALU_OR `QBMCU_DECINFO_ALU_OR_MSB :`QBMCU_DECINFO_ALU_OR_LSB
|
||||
`define QBMCU_DECINFO_ALU_AND_LSB (`QBMCU_DECINFO_ALU_OR_MSB+1)
|
||||
`define QBMCU_DECINFO_ALU_AND_MSB (`QBMCU_DECINFO_ALU_AND_LSB+1-1)
|
||||
`define QBMCU_DECINFO_ALU_AND `QBMCU_DECINFO_ALU_AND_MSB :`QBMCU_DECINFO_ALU_AND_LSB
|
||||
`define QBMCU_DECINFO_ALU_SLT_LSB (`QBMCU_DECINFO_ALU_AND_MSB+1)
|
||||
`define QBMCU_DECINFO_ALU_SLT_MSB (`QBMCU_DECINFO_ALU_SLT_LSB+1-1)
|
||||
`define QBMCU_DECINFO_ALU_SLT `QBMCU_DECINFO_ALU_SLT_MSB :`QBMCU_DECINFO_ALU_SLT_LSB
|
||||
`define QBMCU_DECINFO_ALU_SLTU_LSB (`QBMCU_DECINFO_ALU_SLT_MSB+1)
|
||||
`define QBMCU_DECINFO_ALU_SLTU_MSB (`QBMCU_DECINFO_ALU_SLTU_LSB+1-1)
|
||||
`define QBMCU_DECINFO_ALU_SLTU `QBMCU_DECINFO_ALU_SLTU_MSB:`QBMCU_DECINFO_ALU_SLTU_LSB
|
||||
`define QBMCU_DECINFO_ALU_LUI_LSB (`QBMCU_DECINFO_ALU_SLTU_MSB+1)
|
||||
`define QBMCU_DECINFO_ALU_LUI_MSB (`QBMCU_DECINFO_ALU_LUI_LSB+1-1)
|
||||
`define QBMCU_DECINFO_ALU_LUI `QBMCU_DECINFO_ALU_LUI_MSB :`QBMCU_DECINFO_ALU_LUI_LSB
|
||||
`define QBMCU_DECINFO_ALU_OP2IMM_LSB (`QBMCU_DECINFO_ALU_LUI_MSB+1)
|
||||
`define QBMCU_DECINFO_ALU_OP2IMM_MSB (`QBMCU_DECINFO_ALU_OP2IMM_LSB+1-1)
|
||||
`define QBMCU_DECINFO_ALU_OP2IMM `QBMCU_DECINFO_ALU_OP2IMM_MSB :`QBMCU_DECINFO_ALU_OP2IMM_LSB
|
||||
`define QBMCU_DECINFO_ALU_OP1PC_LSB (`QBMCU_DECINFO_ALU_OP2IMM_MSB+1)
|
||||
`define QBMCU_DECINFO_ALU_OP1PC_MSB (`QBMCU_DECINFO_ALU_OP1PC_LSB+1-1)
|
||||
`define QBMCU_DECINFO_ALU_OP1PC `QBMCU_DECINFO_ALU_OP1PC_MSB :`QBMCU_DECINFO_ALU_OP1PC_LSB
|
||||
`define QBMCU_DECINFO_ALU_NOP_LSB (`QBMCU_DECINFO_ALU_OP1PC_MSB+1)
|
||||
`define QBMCU_DECINFO_ALU_NOP_MSB (`QBMCU_DECINFO_ALU_NOP_LSB+1-1)
|
||||
`define QBMCU_DECINFO_ALU_NOP `QBMCU_DECINFO_ALU_NOP_MSB :`QBMCU_DECINFO_ALU_NOP_LSB
|
||||
|
||||
`define QBMCU_DECINFO_ALU_WIDTH (`QBMCU_DECINFO_ALU_NOP_MSB+1)
|
||||
|
||||
//AGU group
|
||||
`define QBMCU_DECINFO_AGU_LOAD_LSB `QBMCU_DECINFO_SUBDECINFO_LSB
|
||||
`define QBMCU_DECINFO_AGU_LOAD_MSB (`QBMCU_DECINFO_AGU_LOAD_LSB+1-1)
|
||||
`define QBMCU_DECINFO_AGU_LOAD `QBMCU_DECINFO_AGU_LOAD_MSB :`QBMCU_DECINFO_AGU_LOAD_LSB
|
||||
`define QBMCU_DECINFO_AGU_STORE_LSB (`QBMCU_DECINFO_AGU_LOAD_MSB+1)
|
||||
`define QBMCU_DECINFO_AGU_STORE_MSB (`QBMCU_DECINFO_AGU_STORE_LSB+1-1)
|
||||
`define QBMCU_DECINFO_AGU_STORE `QBMCU_DECINFO_AGU_STORE_MSB :`QBMCU_DECINFO_AGU_STORE_LSB
|
||||
`define QBMCU_DECINFO_AGU_SIZE_LSB (`QBMCU_DECINFO_AGU_STORE_MSB+1)
|
||||
`define QBMCU_DECINFO_AGU_SIZE_MSB (`QBMCU_DECINFO_AGU_SIZE_LSB+2-1)
|
||||
`define QBMCU_DECINFO_AGU_SIZE `QBMCU_DECINFO_AGU_SIZE_MSB :`QBMCU_DECINFO_AGU_SIZE_LSB
|
||||
`define QBMCU_DECINFO_AGU_USIGN_LSB (`QBMCU_DECINFO_AGU_SIZE_MSB+1)
|
||||
`define QBMCU_DECINFO_AGU_USIGN_MSB (`QBMCU_DECINFO_AGU_USIGN_LSB+1-1)
|
||||
`define QBMCU_DECINFO_AGU_USIGN `QBMCU_DECINFO_AGU_USIGN_MSB :`QBMCU_DECINFO_AGU_USIGN_LSB
|
||||
`define QBMCU_DECINFO_AGU_OP2IMM_LSB (`QBMCU_DECINFO_AGU_USIGN_MSB+1)
|
||||
`define QBMCU_DECINFO_AGU_OP2IMM_MSB (`QBMCU_DECINFO_AGU_OP2IMM_LSB+1-1)
|
||||
`define QBMCU_DECINFO_AGU_OP2IMM `QBMCU_DECINFO_AGU_OP2IMM_MSB:`QBMCU_DECINFO_AGU_OP2IMM_LSB
|
||||
|
||||
`define QBMCU_DECINFO_AGU_WIDTH (`QBMCU_DECINFO_AGU_OP2IMM_MSB+1)
|
||||
|
||||
// Bxx group
|
||||
`define QBMCU_DECINFO_BJP_JUMP_LSB `QBMCU_DECINFO_SUBDECINFO_LSB
|
||||
`define QBMCU_DECINFO_BJP_JUMP_MSB (`QBMCU_DECINFO_BJP_JUMP_LSB+1-1)
|
||||
`define QBMCU_DECINFO_BJP_JUMP `QBMCU_DECINFO_BJP_JUMP_MSB :`QBMCU_DECINFO_BJP_JUMP_LSB
|
||||
`define QBMCU_DECINFO_BJP_BPRDT_LSB (`QBMCU_DECINFO_BJP_JUMP_MSB+1)
|
||||
`define QBMCU_DECINFO_BJP_BPRDT_MSB (`QBMCU_DECINFO_BJP_BPRDT_LSB+1-1)
|
||||
`define QBMCU_DECINFO_BJP_JALR `QBMCU_DECINFO_BJP_BPRDT_MSB:`QBMCU_DECINFO_BJP_BPRDT_LSB
|
||||
`define QBMCU_DECINFO_BJP_BEQ_LSB (`QBMCU_DECINFO_BJP_BPRDT_MSB+1)
|
||||
`define QBMCU_DECINFO_BJP_BEQ_MSB (`QBMCU_DECINFO_BJP_BEQ_LSB+1-1)
|
||||
`define QBMCU_DECINFO_BJP_BEQ `QBMCU_DECINFO_BJP_BEQ_MSB :`QBMCU_DECINFO_BJP_BEQ_LSB
|
||||
`define QBMCU_DECINFO_BJP_BNE_LSB (`QBMCU_DECINFO_BJP_BEQ_MSB+1)
|
||||
`define QBMCU_DECINFO_BJP_BNE_MSB (`QBMCU_DECINFO_BJP_BNE_LSB+1-1)
|
||||
`define QBMCU_DECINFO_BJP_BNE `QBMCU_DECINFO_BJP_BNE_MSB :`QBMCU_DECINFO_BJP_BNE_LSB
|
||||
`define QBMCU_DECINFO_BJP_BLT_LSB (`QBMCU_DECINFO_BJP_BNE_MSB+1)
|
||||
`define QBMCU_DECINFO_BJP_BLT_MSB (`QBMCU_DECINFO_BJP_BLT_LSB+1-1)
|
||||
`define QBMCU_DECINFO_BJP_BLT `QBMCU_DECINFO_BJP_BLT_MSB :`QBMCU_DECINFO_BJP_BLT_LSB
|
||||
`define QBMCU_DECINFO_BJP_BGT_LSB (`QBMCU_DECINFO_BJP_BLT_MSB+1)
|
||||
`define QBMCU_DECINFO_BJP_BGT_MSB (`QBMCU_DECINFO_BJP_BGT_LSB+1-1)
|
||||
`define QBMCU_DECINFO_BJP_BGT `QBMCU_DECINFO_BJP_BGT_MSB :`QBMCU_DECINFO_BJP_BGT_LSB
|
||||
`define QBMCU_DECINFO_BJP_BLTU_LSB (`QBMCU_DECINFO_BJP_BGT_MSB+1)
|
||||
`define QBMCU_DECINFO_BJP_BLTU_MSB (`QBMCU_DECINFO_BJP_BLTU_LSB+1-1)
|
||||
`define QBMCU_DECINFO_BJP_BLTU `QBMCU_DECINFO_BJP_BLTU_MSB :`QBMCU_DECINFO_BJP_BLTU_LSB
|
||||
`define QBMCU_DECINFO_BJP_BGTU_LSB (`QBMCU_DECINFO_BJP_BLTU_MSB+1)
|
||||
`define QBMCU_DECINFO_BJP_BGTU_MSB (`QBMCU_DECINFO_BJP_BGTU_LSB+1-1)
|
||||
`define QBMCU_DECINFO_BJP_BGTU `QBMCU_DECINFO_BJP_BGTU_MSB :`QBMCU_DECINFO_BJP_BGTU_LSB
|
||||
`define QBMCU_DECINFO_BJP_BXX_LSB (`QBMCU_DECINFO_BJP_BGTU_MSB+1)
|
||||
`define QBMCU_DECINFO_BJP_BXX_MSB (`QBMCU_DECINFO_BJP_BXX_LSB+1-1)
|
||||
`define QBMCU_DECINFO_BJP_BXX `QBMCU_DECINFO_BJP_BXX_MSB :`QBMCU_DECINFO_BJP_BXX_LSB
|
||||
|
||||
`define QBMCU_DECINFO_BJP_WIDTH (`QBMCU_DECINFO_BJP_BXX_MSB+1)
|
||||
|
||||
|
||||
// EXT group
|
||||
`define QBMCU_DECINFO_EXT_WAIT_LSB `QBMCU_DECINFO_SUBDECINFO_LSB
|
||||
`define QBMCU_DECINFO_EXT_WAIT_MSB (`QBMCU_DECINFO_EXT_WAIT_LSB+1-1)
|
||||
`define QBMCU_DECINFO_EXT_WAIT `QBMCU_DECINFO_EXT_WAIT_MSB:`QBMCU_DECINFO_EXT_WAIT_LSB
|
||||
`define QBMCU_DECINFO_EXT_SEND_LSB (`QBMCU_DECINFO_EXT_WAIT_MSB+1)
|
||||
`define QBMCU_DECINFO_EXT_SEND_MSB (`QBMCU_DECINFO_EXT_SEND_LSB+1-1)
|
||||
`define QBMCU_DECINFO_EXT_SEND `QBMCU_DECINFO_EXT_SEND_MSB:`QBMCU_DECINFO_EXT_SEND_LSB
|
||||
`define QBMCU_DECINFO_EXT_SENDC_LSB (`QBMCU_DECINFO_EXT_SEND_MSB+1)
|
||||
`define QBMCU_DECINFO_EXT_SENDC_MSB (`QBMCU_DECINFO_EXT_SENDC_LSB+1-1)
|
||||
`define QBMCU_DECINFO_EXT_SENDC `QBMCU_DECINFO_EXT_SENDC_MSB:`QBMCU_DECINFO_EXT_SENDC_LSB
|
||||
`define QBMCU_DECINFO_EXT_EXIT_LSB (`QBMCU_DECINFO_EXT_SENDC_MSB+1)
|
||||
`define QBMCU_DECINFO_EXT_EXIT_MSB (`QBMCU_DECINFO_EXT_EXIT_LSB+1-1)
|
||||
`define QBMCU_DECINFO_EXT_EXIT `QBMCU_DECINFO_EXT_EXIT_MSB:`QBMCU_DECINFO_EXT_EXIT_LSB
|
||||
`define QBMCU_DECINFO_EXT_EXITI_LSB (`QBMCU_DECINFO_EXT_EXIT_MSB+1)
|
||||
`define QBMCU_DECINFO_EXT_EXITI_MSB (`QBMCU_DECINFO_EXT_EXITI_LSB+1-1)
|
||||
`define QBMCU_DECINFO_EXT_EXITI `QBMCU_DECINFO_EXT_EXITI_MSB:`QBMCU_DECINFO_EXT_EXITI_LSB
|
||||
`define QBMCU_DECINFO_EXT_OP2IMM_LSB (`QBMCU_DECINFO_EXT_EXITI_MSB+1)
|
||||
`define QBMCU_DECINFO_EXT_OP2IMM_MSB (`QBMCU_DECINFO_EXT_OP2IMM_LSB+1-1)
|
||||
`define QBMCU_DECINFO_EXT_OP2IMM `QBMCU_DECINFO_EXT_OP2IMM_MSB:`QBMCU_DECINFO_EXT_OP2IMM_LSB
|
||||
|
||||
`define QBMCU_DECINFO_EXT_WIDTH (`QBMCU_DECINFO_EXT_OP2IMM_MSB+1)
|
||||
|
||||
// Choose the longest group as the final DEC info width
|
||||
`define QBMCU_DECINFO_WIDTH (`QBMCU_DECINFO_ALU_WIDTH+1)
|
||||
|
||||
|
|
@ -0,0 +1,385 @@
|
|||
//+FHDR--------------------------------------------------------------------------------------------------------
|
||||
// Company:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// File Name : qbmcu_exu.v
|
||||
// Department :
|
||||
// Author : PWY
|
||||
// Author's Tel :
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Relese History
|
||||
// Version Date Author Description
|
||||
// 0.1 2024-03-13 PWY The EXU module to implement entire Execution Stage
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Keywords :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Parameter
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Purpose :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Target Device:
|
||||
// Tool versions:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Reuse Issues
|
||||
// Reset Strategy:
|
||||
// Clock Domains:
|
||||
// Critical Timing:
|
||||
// Asynchronous I/F:
|
||||
// Synthesizable (y/n):
|
||||
// Other:
|
||||
//-FHDR--------------------------------------------------------------------------------------------------------
|
||||
|
||||
`include "qbmcu_defines.v"
|
||||
|
||||
|
||||
module qbmcu_exu(
|
||||
//system port
|
||||
input clk
|
||||
,input rst_n
|
||||
//////////////////////////////////////////////////////////////
|
||||
//////////////////////////////////////////////////////////////
|
||||
// The Handshake Interface
|
||||
//
|
||||
,input [`QBMCU_XLEN-1 :0] exu_i_rs1
|
||||
,input [`QBMCU_XLEN-1 :0] exu_i_rs2
|
||||
,input [`QBMCU_XLEN-1 :0] exu_i_imm
|
||||
,input [`QBMCU_PC_SIZE-1 :0] exu_i_pc
|
||||
,input [`QBMCU_DECINFO_WIDTH-1 :0] exu_i_info
|
||||
,input exu_i_ilegl
|
||||
|
||||
//The enable signal from the master control state machine
|
||||
,input exu_i_active
|
||||
|
||||
//////////////////////////////////////////////////////////////
|
||||
//Data sent to the write-back module
|
||||
//write back interface
|
||||
,output [`QBMCU_XLEN-1 :0] bjp_o_wbck_wdat
|
||||
,output bjp_o_wbck_valid
|
||||
//////////////////////////////////////////////////////////////
|
||||
//update the value of the program counter (PC)
|
||||
,output bjp_update_pc_req
|
||||
,output [`QBMCU_PC_SIZE-1 :0] bjp_update_pc_value
|
||||
|
||||
// The operands and info to peripheral
|
||||
,output ext_o_wait_valid
|
||||
,output ext_o_wait
|
||||
,output [`QBMCU_XLEN-1 :0] ext_o_wait_cnt
|
||||
,output ext_o_send
|
||||
,output ext_o_sendc
|
||||
,output [`QBMCU_XLEN-1 :0] ext_o_codeword
|
||||
,output ext_o_exit
|
||||
,output ext_o_intr
|
||||
,output [`QBMCU_XLEN-1 :0] ext_o_wbck_wdat
|
||||
,output ext_o_wbck_valid
|
||||
|
||||
//////////////////////////////////////////////////////////////
|
||||
//Address, data, and enable signals connected to the memory space
|
||||
,output [`QBMCU_ADDR_SIZE-1 :0] agu_o_addr
|
||||
,output [`QBMCU_XLEN-1 :0] agu_o_wdata
|
||||
,output agu_o_wren // Write enable
|
||||
,output agu_o_rden // Read enable
|
||||
,output [`QBMCU_XLEN/8-1 :0] agu_o_wmask
|
||||
,input [`QBMCU_XLEN-1 :0] agu_i_rdata
|
||||
|
||||
//Data sent to the write-back module
|
||||
//write back interface
|
||||
,output [`QBMCU_XLEN-1 :0] agu_o_wbck_wdat
|
||||
,output agu_o_wbck_valid
|
||||
//Misaligned memory address
|
||||
,output agu_o_addr_unalgn
|
||||
|
||||
// The Write-Back Interface for Special (unaligned ldst instructions)
|
||||
,output [`QBMCU_XLEN-1 :0] alu_o_wbck_wdat
|
||||
,output alu_o_wbck_valid
|
||||
|
||||
);
|
||||
|
||||
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
//AGU
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
wire [`QBMCU_XLEN-1 :0] agu_i_rs1 ;
|
||||
wire [`QBMCU_XLEN-1 :0] agu_i_rs2 ;
|
||||
wire [`QBMCU_XLEN-1 :0] agu_i_imm ;
|
||||
wire [`QBMCU_DECINFO_WIDTH-1 :0] agu_i_info ;
|
||||
wire agu_i_op ;
|
||||
|
||||
//qbmcu_datalatch_agu
|
||||
qbmcu_datalatch #(
|
||||
.DECINFO_GRP_OP ( `QBMCU_DECINFO_GRP_AGU )
|
||||
) U_qubitmcu_datalatch_agu
|
||||
(
|
||||
.i_rs1 ( exu_i_rs1 )
|
||||
,.i_rs2 ( exu_i_rs2 )
|
||||
,.i_imm ( exu_i_imm )
|
||||
,.i_info ( exu_i_info )
|
||||
,.i_pc ( exu_i_pc )
|
||||
,.i_ilegl ( exu_i_ilegl )
|
||||
,.o_rs1 ( agu_i_rs1 )
|
||||
,.o_rs2 ( agu_i_rs2 )
|
||||
,.o_imm ( agu_i_imm )
|
||||
,.o_info ( agu_i_info )
|
||||
,.o_pc ( )
|
||||
,.o_op ( agu_i_op )
|
||||
);
|
||||
|
||||
//qbmcu_exu_lsuagu
|
||||
qbmcu_exu_lsuagu U_qbmcu_exu_lsuagu (
|
||||
.clk ( clk )
|
||||
,.rst_n ( rst_n )
|
||||
,.agu_i_rs1 ( agu_i_rs1 )
|
||||
,.agu_i_rs2 ( agu_i_rs2 )
|
||||
,.agu_i_imm ( agu_i_imm )
|
||||
,.agu_i_info ( agu_i_info[`QBMCU_DECINFO_AGU_WIDTH-1:0])
|
||||
,.agu_i_op ( agu_i_op )
|
||||
,.agu_i_active ( exu_i_active )
|
||||
,.agu_o_addr ( agu_o_addr )
|
||||
,.agu_o_wdata ( agu_o_wdata )
|
||||
,.agu_o_wren ( agu_o_wren )
|
||||
,.agu_o_rden ( agu_o_rden )
|
||||
,.agu_o_wmask ( agu_o_wmask )
|
||||
,.agu_i_rdata ( agu_i_rdata )
|
||||
,.agu_o_wbck_wdat ( agu_o_wbck_wdat )
|
||||
,.agu_o_wbck_valid ( agu_o_wbck_valid )
|
||||
,.agu_o_addr_unalgn ( agu_o_addr_unalgn )
|
||||
);
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
//EXT
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
wire [`QBMCU_XLEN-1 :0] ext_i_rs1 ;
|
||||
wire [`QBMCU_XLEN-1 :0] ext_i_imm ;
|
||||
wire [`QBMCU_DECINFO_WIDTH-1 :0] ext_i_info ;
|
||||
wire ext_i_op ;
|
||||
|
||||
//qbmcu_datalatch_ext
|
||||
qbmcu_datalatch #(
|
||||
.DECINFO_GRP_OP ( `QBMCU_DECINFO_GRP_EXT )
|
||||
) U_qubitmcu_datalatch_ext
|
||||
(
|
||||
.i_rs1 ( exu_i_rs1 )
|
||||
,.i_rs2 ( exu_i_rs2 )
|
||||
,.i_imm ( exu_i_imm )
|
||||
,.i_info ( exu_i_info )
|
||||
,.i_pc ( exu_i_pc )
|
||||
,.i_ilegl ( exu_i_ilegl )
|
||||
,.o_rs1 ( ext_i_rs1 )
|
||||
,.o_rs2 ( )
|
||||
,.o_imm ( ext_i_imm )
|
||||
,.o_info ( ext_i_info )
|
||||
,.o_pc ( )
|
||||
,.o_op ( ext_i_op )
|
||||
);
|
||||
|
||||
//qbmcu_exu_ext
|
||||
qbmcu_exu_ext U_qbmcu_exu_ext (
|
||||
.clk ( clk )
|
||||
,.rst_n ( rst_n )
|
||||
,.ext_i_rs1 ( ext_i_rs1 )
|
||||
,.ext_i_imm ( ext_i_imm )
|
||||
,.ext_i_info ( ext_i_info[`QBMCU_DECINFO_EXT_WIDTH-1:0])
|
||||
,.ext_i_op ( ext_i_op )
|
||||
,.ext_o_wait_valid ( ext_o_wait_valid )
|
||||
,.ext_i_active ( exu_i_active )
|
||||
,.ext_o_wait ( ext_o_wait )
|
||||
,.ext_o_wait_cnt ( ext_o_wait_cnt )
|
||||
,.ext_o_send ( ext_o_send )
|
||||
,.ext_o_sendc ( ext_o_sendc )
|
||||
,.ext_o_codeword ( ext_o_codeword )
|
||||
,.ext_o_exit ( ext_o_exit )
|
||||
,.ext_o_intr ( ext_o_intr )
|
||||
,.ext_o_wbck_wdat ( ext_o_wbck_wdat )
|
||||
,.ext_o_wbck_valid ( ext_o_wbck_valid )
|
||||
);
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
//BJP
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
wire [`QBMCU_XLEN-1 :0] bjp_i_rs1 ;
|
||||
wire [`QBMCU_XLEN-1 :0] bjp_i_rs2 ;
|
||||
wire [`QBMCU_XLEN-1 :0] bjp_i_imm ;
|
||||
wire [`QBMCU_DECINFO_WIDTH-1 :0] bjp_i_info ;
|
||||
wire [`QBMCU_PC_SIZE-1 :0] bjp_i_pc ;
|
||||
wire bjp_i_op ;
|
||||
|
||||
//////////////////////////////////////////////////////////////
|
||||
// To share the ALU datapath
|
||||
// The operands and info to ALU
|
||||
wire [`QBMCU_XLEN-1 :0] bjp_req_alu_op1 ;
|
||||
wire [`QBMCU_XLEN-1 :0] bjp_req_alu_op2 ;
|
||||
wire bjp_req_alu_cmp_eq ;
|
||||
wire bjp_req_alu_cmp_ne ;
|
||||
wire bjp_req_alu_cmp_lt ;
|
||||
wire bjp_req_alu_cmp_gt ;
|
||||
wire bjp_req_alu_cmp_ltu ;
|
||||
wire bjp_req_alu_cmp_gtu ;
|
||||
wire bjp_req_alu_add ;
|
||||
wire bjp_req_alu_cmp_res ;
|
||||
wire [`QBMCU_XLEN-1 :0] bjp_req_alu_add_res ;
|
||||
|
||||
//qbmcu_datalatch_bjp
|
||||
qbmcu_datalatch #(
|
||||
.DECINFO_GRP_OP ( `QBMCU_DECINFO_GRP_BJP )
|
||||
) U_qubitmcu_datalatch_bjp
|
||||
(
|
||||
.i_rs1 ( exu_i_rs1 )
|
||||
,.i_rs2 ( exu_i_rs2 )
|
||||
,.i_imm ( exu_i_imm )
|
||||
,.i_info ( exu_i_info )
|
||||
,.i_pc ( exu_i_pc )
|
||||
,.i_ilegl ( exu_i_ilegl )
|
||||
,.o_rs1 ( bjp_i_rs1 )
|
||||
,.o_rs2 ( bjp_i_rs2 )
|
||||
,.o_imm ( bjp_i_imm )
|
||||
,.o_info ( bjp_i_info )
|
||||
,.o_pc ( bjp_i_pc )
|
||||
,.o_op ( bjp_i_op )
|
||||
);
|
||||
|
||||
|
||||
//qbmcu_exu_bjp
|
||||
qbmcu_exu_bjp U_qbmcu_exu_bjp (
|
||||
.clk ( clk )
|
||||
,.rst_n ( rst_n )
|
||||
,.bjp_i_rs1 ( bjp_i_rs1 )
|
||||
,.bjp_i_rs2 ( bjp_i_rs2 )
|
||||
,.bjp_i_imm ( bjp_i_imm )
|
||||
,.bjp_i_pc ( bjp_i_pc )
|
||||
,.bjp_i_info ( bjp_i_info[`QBMCU_DECINFO_BJP_WIDTH-1:0])
|
||||
,.bjp_i_op ( bjp_i_op )
|
||||
,.bjp_i_active ( exu_i_active )
|
||||
,.bjp_o_wbck_valid ( bjp_o_wbck_valid )
|
||||
,.bjp_o_wbck_wdat ( bjp_o_wbck_wdat )
|
||||
,.update_pc_req ( bjp_update_pc_req )
|
||||
,.update_pc_value ( bjp_update_pc_value )
|
||||
,.bjp_req_alu_op1 ( bjp_req_alu_op1 )
|
||||
,.bjp_req_alu_op2 ( bjp_req_alu_op2 )
|
||||
,.bjp_req_alu_cmp_eq ( bjp_req_alu_cmp_eq )
|
||||
,.bjp_req_alu_cmp_ne ( bjp_req_alu_cmp_ne )
|
||||
,.bjp_req_alu_cmp_lt ( bjp_req_alu_cmp_lt )
|
||||
,.bjp_req_alu_cmp_gt ( bjp_req_alu_cmp_gt )
|
||||
,.bjp_req_alu_cmp_ltu ( bjp_req_alu_cmp_ltu )
|
||||
,.bjp_req_alu_cmp_gtu ( bjp_req_alu_cmp_gtu )
|
||||
,.bjp_req_alu_add ( bjp_req_alu_add )
|
||||
,.bjp_req_alu_cmp_res ( bjp_req_alu_cmp_res )
|
||||
,.bjp_req_alu_add_res ( bjp_req_alu_add_res )
|
||||
);
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
//ALU
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
wire [`QBMCU_XLEN-1 :0] alu_i_rs1 ;
|
||||
wire [`QBMCU_XLEN-1 :0] alu_i_rs2 ;
|
||||
wire [`QBMCU_XLEN-1 :0] alu_i_imm ;
|
||||
wire [`QBMCU_DECINFO_WIDTH-1 :0] alu_i_info ;
|
||||
wire [`QBMCU_PC_SIZE-1 :0] alu_i_pc ;
|
||||
wire alu_i_op ;
|
||||
//////////////////////////////////////////////////////////////
|
||||
//////////////////////////////////////////////////////////////
|
||||
// To share the ALU datapath
|
||||
//
|
||||
// The operands and info to ALU
|
||||
wire alu_req_alu_add ;
|
||||
wire alu_req_alu_sub ;
|
||||
wire alu_req_alu_xor ;
|
||||
wire alu_req_alu_sll ;
|
||||
wire alu_req_alu_srl ;
|
||||
wire alu_req_alu_sra ;
|
||||
wire alu_req_alu_or ;
|
||||
wire alu_req_alu_and ;
|
||||
wire alu_req_alu_slt ;
|
||||
wire alu_req_alu_sltu ;
|
||||
wire alu_req_alu_lui ;
|
||||
wire [`QBMCU_XLEN-1 :0] alu_req_alu_op1 ;
|
||||
wire [`QBMCU_XLEN-1 :0] alu_req_alu_op2 ;
|
||||
wire [`QBMCU_XLEN-1 :0] alu_req_alu_res ;
|
||||
|
||||
//qbmcu_datalatch_alu
|
||||
qbmcu_datalatch #(
|
||||
.DECINFO_GRP_OP ( `QBMCU_DECINFO_GRP_ALU )
|
||||
) U_qbmcu_datalatch_alu
|
||||
(
|
||||
.i_rs1 ( exu_i_rs1 )
|
||||
,.i_rs2 ( exu_i_rs2 )
|
||||
,.i_imm ( exu_i_imm )
|
||||
,.i_info ( exu_i_info )
|
||||
,.i_pc ( exu_i_pc )
|
||||
,.i_ilegl ( exu_i_ilegl )
|
||||
,.o_rs1 ( alu_i_rs1 )
|
||||
,.o_rs2 ( alu_i_rs2 )
|
||||
,.o_imm ( alu_i_imm )
|
||||
,.o_info ( alu_i_info )
|
||||
,.o_pc ( alu_i_pc )
|
||||
,.o_op ( alu_i_op )
|
||||
);
|
||||
|
||||
//qbmcu_exu_alu_rglr
|
||||
qbmcu_exu_alu U_qbmcu_exu_alu (
|
||||
.clk ( clk )
|
||||
,.rst_n ( rst_n )
|
||||
,.alu_i_rs1 ( alu_i_rs1 )
|
||||
,.alu_i_rs2 ( alu_i_rs2 )
|
||||
,.alu_i_imm ( alu_i_imm )
|
||||
,.alu_i_pc ( alu_i_pc )
|
||||
,.alu_i_info ( alu_i_info[`QBMCU_DECINFO_ALU_WIDTH-1:0])
|
||||
,.alu_i_op ( alu_i_op )
|
||||
,.alu_i_active ( exu_i_active )
|
||||
,.alu_o_wbck_wdat ( alu_o_wbck_wdat )
|
||||
,.alu_o_wbck_valid ( alu_o_wbck_valid )
|
||||
,.alu_req_alu_add ( alu_req_alu_add )
|
||||
,.alu_req_alu_sub ( alu_req_alu_sub )
|
||||
,.alu_req_alu_xor ( alu_req_alu_xor )
|
||||
,.alu_req_alu_sll ( alu_req_alu_sll )
|
||||
,.alu_req_alu_srl ( alu_req_alu_srl )
|
||||
,.alu_req_alu_sra ( alu_req_alu_sra )
|
||||
,.alu_req_alu_or ( alu_req_alu_or )
|
||||
,.alu_req_alu_and ( alu_req_alu_and )
|
||||
,.alu_req_alu_slt ( alu_req_alu_slt )
|
||||
,.alu_req_alu_sltu ( alu_req_alu_sltu )
|
||||
,.alu_req_alu_lui ( alu_req_alu_lui )
|
||||
,.alu_req_alu_op1 ( alu_req_alu_op1 )
|
||||
,.alu_req_alu_op2 ( alu_req_alu_op2 )
|
||||
,.alu_req_alu_res ( alu_req_alu_res )
|
||||
);
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
//DPATH
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
qbmcu_exu_dpath U_qbmcu_exu_dpath (
|
||||
.alu_req_alu ( alu_i_op )
|
||||
,.alu_req_alu_add ( alu_req_alu_add )
|
||||
,.alu_req_alu_sub ( alu_req_alu_sub )
|
||||
,.alu_req_alu_xor ( alu_req_alu_xor )
|
||||
,.alu_req_alu_sll ( alu_req_alu_sll )
|
||||
,.alu_req_alu_srl ( alu_req_alu_srl )
|
||||
,.alu_req_alu_sra ( alu_req_alu_sra )
|
||||
,.alu_req_alu_or ( alu_req_alu_or )
|
||||
,.alu_req_alu_and ( alu_req_alu_and )
|
||||
,.alu_req_alu_slt ( alu_req_alu_slt )
|
||||
,.alu_req_alu_sltu ( alu_req_alu_sltu )
|
||||
,.alu_req_alu_lui ( alu_req_alu_lui )
|
||||
,.alu_req_alu_op1 ( alu_req_alu_op1 )
|
||||
,.alu_req_alu_op2 ( alu_req_alu_op2 )
|
||||
,.alu_req_alu_res ( alu_req_alu_res )
|
||||
,.bjp_req_alu ( bjp_i_op )
|
||||
,.bjp_req_alu_op1 ( bjp_req_alu_op1 )
|
||||
,.bjp_req_alu_op2 ( bjp_req_alu_op2 )
|
||||
,.bjp_req_alu_cmp_eq ( bjp_req_alu_cmp_eq )
|
||||
,.bjp_req_alu_cmp_ne ( bjp_req_alu_cmp_ne )
|
||||
,.bjp_req_alu_cmp_lt ( bjp_req_alu_cmp_lt )
|
||||
,.bjp_req_alu_cmp_gt ( bjp_req_alu_cmp_gt )
|
||||
,.bjp_req_alu_cmp_ltu ( bjp_req_alu_cmp_ltu )
|
||||
,.bjp_req_alu_cmp_gtu ( bjp_req_alu_cmp_gtu )
|
||||
,.bjp_req_alu_add ( bjp_req_alu_add )
|
||||
,.bjp_req_alu_cmp_res ( bjp_req_alu_cmp_res )
|
||||
,.bjp_req_alu_add_res ( bjp_req_alu_add_res )
|
||||
);
|
||||
endmodule
|
||||
|
||||
|
||||
`include "qbmcu_undefines.v"
|
||||
|
|
@ -0,0 +1,106 @@
|
|||
//+FHDR--------------------------------------------------------------------------------------------------------
|
||||
// Company:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// File Name : qbmcu_exu_alu.v
|
||||
// Department :
|
||||
// Author : PWY
|
||||
// Author's Tel :
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Relese History
|
||||
// Version Date Author Description
|
||||
// 0.1 2024-03-13 PWY This module to implement the regular ALU instructions
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Keywords :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Parameter
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Purpose :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Target Device:
|
||||
// Tool versions:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Reuse Issues
|
||||
// Reset Strategy:
|
||||
// Clock Domains:
|
||||
// Critical Timing:
|
||||
// Asynchronous I/F:
|
||||
// Synthesizable (y/n):
|
||||
// Other:
|
||||
//-FHDR--------------------------------------------------------------------------------------------------------
|
||||
|
||||
`include "qbmcu_defines.v"
|
||||
|
||||
|
||||
module qbmcu_exu_alu(
|
||||
//system port
|
||||
input clk
|
||||
,input rst_n
|
||||
//////////////////////////////////////////////////////////////
|
||||
//////////////////////////////////////////////////////////////
|
||||
,input [`QBMCU_XLEN-1 :0] alu_i_rs1
|
||||
,input [`QBMCU_XLEN-1 :0] alu_i_rs2
|
||||
,input [`QBMCU_XLEN-1 :0] alu_i_imm
|
||||
,input [`QBMCU_PC_SIZE-1 :0] alu_i_pc
|
||||
,input [`QBMCU_DECINFO_ALU_WIDTH-1:0] alu_i_info
|
||||
,input alu_i_op
|
||||
//The enable signal from the master control state machine
|
||||
,input alu_i_active
|
||||
//////////////////////////////////////////////////////////////
|
||||
//////////////////////////////////////////////////////////////
|
||||
// The Write-Back Interface for Special (unaligned ldst and AMO instructions)
|
||||
,output [`QBMCU_XLEN-1 :0] alu_o_wbck_wdat
|
||||
,output alu_o_wbck_valid
|
||||
//////////////////////////////////////////////////////////////
|
||||
//////////////////////////////////////////////////////////////
|
||||
// To share the ALU datapath
|
||||
//
|
||||
// The operands and info to ALU
|
||||
,output alu_req_alu_add
|
||||
,output alu_req_alu_sub
|
||||
,output alu_req_alu_xor
|
||||
,output alu_req_alu_sll
|
||||
,output alu_req_alu_srl
|
||||
,output alu_req_alu_sra
|
||||
,output alu_req_alu_or
|
||||
,output alu_req_alu_and
|
||||
,output alu_req_alu_slt
|
||||
,output alu_req_alu_sltu
|
||||
,output alu_req_alu_lui
|
||||
,output [`QBMCU_XLEN-1 :0] alu_req_alu_op1
|
||||
,output [`QBMCU_XLEN-1 :0] alu_req_alu_op2
|
||||
|
||||
,input [`QBMCU_XLEN-1 :0] alu_req_alu_res
|
||||
);
|
||||
wire alu_i_active_r;
|
||||
wire op2imm = alu_i_op & alu_i_info [`QBMCU_DECINFO_ALU_OP2IMM ];
|
||||
wire op1pc = alu_i_op & alu_i_info [`QBMCU_DECINFO_ALU_OP1PC ];
|
||||
|
||||
assign alu_req_alu_op1 = op1pc ? alu_i_pc : alu_i_rs1;
|
||||
assign alu_req_alu_op2 = op2imm ? alu_i_imm : alu_i_rs2;
|
||||
|
||||
wire nop = alu_i_op & alu_i_info [`QBMCU_DECINFO_ALU_NOP ] ;
|
||||
|
||||
// The NOP is encoded as ADDI, so need to uncheck it
|
||||
assign alu_req_alu_add = alu_i_op & alu_i_info [`QBMCU_DECINFO_ALU_ADD ] & (~nop);
|
||||
assign alu_req_alu_sub = alu_i_op & alu_i_info [`QBMCU_DECINFO_ALU_SUB ];
|
||||
assign alu_req_alu_xor = alu_i_op & alu_i_info [`QBMCU_DECINFO_ALU_XOR ];
|
||||
assign alu_req_alu_sll = alu_i_op & alu_i_info [`QBMCU_DECINFO_ALU_SLL ];
|
||||
assign alu_req_alu_srl = alu_i_op & alu_i_info [`QBMCU_DECINFO_ALU_SRL ];
|
||||
assign alu_req_alu_sra = alu_i_op & alu_i_info [`QBMCU_DECINFO_ALU_SRA ];
|
||||
assign alu_req_alu_or = alu_i_op & alu_i_info [`QBMCU_DECINFO_ALU_OR ];
|
||||
assign alu_req_alu_and = alu_i_op & alu_i_info [`QBMCU_DECINFO_ALU_AND ];
|
||||
assign alu_req_alu_slt = alu_i_op & alu_i_info [`QBMCU_DECINFO_ALU_SLT ];
|
||||
assign alu_req_alu_sltu = alu_i_op & alu_i_info [`QBMCU_DECINFO_ALU_SLTU];
|
||||
assign alu_req_alu_lui = alu_i_op & alu_i_info [`QBMCU_DECINFO_ALU_LUI ];
|
||||
|
||||
//alu_i_active_r
|
||||
sirv_gnrl_dffr #(1) alu_i_active_r_dffr (alu_i_active, alu_i_active_r, clk, rst_n);
|
||||
//alu_o_wbck_wdat
|
||||
sirv_gnrl_dfflr #(`QBMCU_XLEN) alu_o_wbck_wdat_dfflr (alu_i_active_r, alu_req_alu_res, alu_o_wbck_wdat, clk, rst_n);
|
||||
//alu_o_wbck_valid
|
||||
sirv_gnrl_dfflr #(1) alu_o_wbck_valid_dfflr (alu_i_active_r, alu_i_op, alu_o_wbck_valid, clk, rst_n);
|
||||
endmodule
|
||||
`include "qbmcu_undefines.v"
|
||||
|
|
@ -0,0 +1,134 @@
|
|||
//+FHDR--------------------------------------------------------------------------------------------------------
|
||||
// Company:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// File Name : qbmcu_exu_bjp.v
|
||||
// Department :
|
||||
// Author : PWY
|
||||
// Author's Tel :
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Relese History
|
||||
// Version Date Author Description
|
||||
// 0.1 2024-03-13 PWY This module to implement the Conditional Branch Instructions,
|
||||
// which is mostly share the datapath with ALU adder to resolve the comparasion
|
||||
// result to save gatecount to mininum
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Keywords :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Parameter
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Purpose :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Target Device:
|
||||
// Tool versions:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Reuse Issues
|
||||
// Reset Strategy:
|
||||
// Clock Domains:
|
||||
// Critical Timing:
|
||||
// Asynchronous I/F:
|
||||
// Synthesizable (y/n):
|
||||
// Other:
|
||||
//-FHDR--------------------------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
`include "qbmcu_defines.v"
|
||||
|
||||
|
||||
module qbmcu_exu_bjp(
|
||||
//system port
|
||||
input clk
|
||||
,input rst_n
|
||||
//////////////////////////////////////////////////////////////
|
||||
//////////////////////////////////////////////////////////////
|
||||
// The Handshake Interface
|
||||
//
|
||||
,input [`QBMCU_XLEN-1 :0] bjp_i_rs1
|
||||
,input [`QBMCU_XLEN-1 :0] bjp_i_rs2
|
||||
,input [`QBMCU_XLEN-1 :0] bjp_i_imm
|
||||
,input [`QBMCU_PC_SIZE-1 :0] bjp_i_pc
|
||||
,input [`QBMCU_DECINFO_BJP_WIDTH-1:0] bjp_i_info
|
||||
,input bjp_i_op
|
||||
//The enable signal from the master control state machine
|
||||
,input bjp_i_active
|
||||
|
||||
//////////////////////////////////////////////////////////////
|
||||
//Data sent to the write-back module
|
||||
//write back interface
|
||||
,output [`QBMCU_XLEN-1 :0] bjp_o_wbck_wdat
|
||||
,output bjp_o_wbck_valid
|
||||
//////////////////////////////////////////////////////////////
|
||||
//update the value of the program counter (PC)
|
||||
,output update_pc_req
|
||||
,output [`QBMCU_PC_SIZE-1 :0] update_pc_value
|
||||
//////////////////////////////////////////////////////////////
|
||||
// To share the ALU datapath
|
||||
// The operands and info to ALU
|
||||
,output [`QBMCU_XLEN-1 :0] bjp_req_alu_op1
|
||||
,output [`QBMCU_XLEN-1 :0] bjp_req_alu_op2
|
||||
,output bjp_req_alu_cmp_eq
|
||||
,output bjp_req_alu_cmp_ne
|
||||
,output bjp_req_alu_cmp_lt
|
||||
,output bjp_req_alu_cmp_gt
|
||||
,output bjp_req_alu_cmp_ltu
|
||||
,output bjp_req_alu_cmp_gtu
|
||||
,output bjp_req_alu_add
|
||||
|
||||
,input bjp_req_alu_cmp_res
|
||||
,input [`QBMCU_XLEN-1 :0] bjp_req_alu_add_res
|
||||
);
|
||||
|
||||
|
||||
wire bxx = bjp_i_op & bjp_i_info [`QBMCU_DECINFO_BJP_BXX ];
|
||||
wire jump = bjp_i_op & bjp_i_info [`QBMCU_DECINFO_BJP_JUMP ];
|
||||
wire jalr = bjp_i_op & bjp_i_info [`QBMCU_DECINFO_BJP_JALR ];
|
||||
|
||||
wire wbck_link = jump;
|
||||
|
||||
assign bjp_req_alu_op1 = wbck_link ?
|
||||
bjp_i_pc
|
||||
: bjp_i_rs1;
|
||||
assign bjp_req_alu_op2 = wbck_link ?
|
||||
`QBMCU_XLEN'd4
|
||||
: bjp_i_rs2;
|
||||
|
||||
wire cmt_bjp = bxx | jump;
|
||||
|
||||
|
||||
assign bjp_req_alu_cmp_eq = bjp_i_op & bjp_i_info [`QBMCU_DECINFO_BJP_BEQ ];
|
||||
assign bjp_req_alu_cmp_ne = bjp_i_op & bjp_i_info [`QBMCU_DECINFO_BJP_BNE ];
|
||||
assign bjp_req_alu_cmp_lt = bjp_i_op & bjp_i_info [`QBMCU_DECINFO_BJP_BLT ];
|
||||
assign bjp_req_alu_cmp_gt = bjp_i_op & bjp_i_info [`QBMCU_DECINFO_BJP_BGT ];
|
||||
assign bjp_req_alu_cmp_ltu = bjp_i_op & bjp_i_info [`QBMCU_DECINFO_BJP_BLTU ];
|
||||
assign bjp_req_alu_cmp_gtu = bjp_i_op & bjp_i_info [`QBMCU_DECINFO_BJP_BGTU ];
|
||||
|
||||
assign bjp_req_alu_add = wbck_link;
|
||||
|
||||
wire cmt_rslv = jump ? 1'b1 : bjp_req_alu_cmp_res;
|
||||
|
||||
|
||||
//bjp_o_wbck_wdat
|
||||
sirv_gnrl_dfflr #(`QBMCU_XLEN) bjp_o_wbck_wdat_dfflr (bjp_i_active, bjp_req_alu_add_res, bjp_o_wbck_wdat, clk, rst_n);
|
||||
//bjp_o_wbck_valid
|
||||
sirv_gnrl_dfflr #(1) bjp_o_wbck_valid_dfflr (bjp_i_active, bjp_i_op, bjp_o_wbck_valid, clk, rst_n);
|
||||
|
||||
wire [`QBMCU_PC_SIZE-1:0] pc_temp = jalr ? bjp_i_rs1 : bjp_i_pc;
|
||||
|
||||
wire [`QBMCU_PC_SIZE-1:0] update_pc_value_w = (pc_temp + bjp_i_imm[`QBMCU_PC_SIZE-1:0]);
|
||||
wire update_pc_req_w = cmt_bjp & cmt_rslv;
|
||||
|
||||
//wire bjp_i_active_r;
|
||||
//sirv_gnrl_dffr #(1)bjp_i_active_r_dffr (bjp_i_active, bjp_i_active_r, clk, rst_n);
|
||||
|
||||
//update_pc_vaule
|
||||
//sirv_gnrl_dfflr #(`QBMCU_PC_SIZE) update_pc_vaule_dfflr (bjp_i_active_r, update_pc_value_w, update_pc_value, clk, rst_n);
|
||||
//update_pc_req
|
||||
//sirv_gnrl_dfflr #(1) update_pc_req_dfflr (bjp_i_active_r, update_pc_req_w, update_pc_req, clk, rst_n);
|
||||
|
||||
assign update_pc_value = update_pc_value_w;
|
||||
assign update_pc_req = update_pc_req_w;
|
||||
endmodule
|
||||
|
||||
`include "qbmcu_undefines.v"
|
||||
|
|
@ -0,0 +1,365 @@
|
|||
//+FHDR--------------------------------------------------------------------------------------------------------
|
||||
// Company:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// File Name : qbmcu_exu_dpath.v
|
||||
// Department :
|
||||
// Author : PWY
|
||||
// Author's Tel :
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Relese History
|
||||
// Version Date Author Description
|
||||
// 0.1 2024-03-13 PWY This module to implement the datapath of ALU
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Keywords :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Parameter
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Purpose :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Target Device:
|
||||
// Tool versions:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Reuse Issues
|
||||
// Reset Strategy:
|
||||
// Clock Domains:
|
||||
// Critical Timing:
|
||||
// Asynchronous I/F:
|
||||
// Synthesizable (y/n):
|
||||
// Other:
|
||||
//-FHDR--------------------------------------------------------------------------------------------------------
|
||||
|
||||
`include "qbmcu_defines.v"
|
||||
|
||||
module qbmcu_exu_dpath(
|
||||
//////////////////////////////////////////////////////
|
||||
// ALU request the datapath
|
||||
input alu_req_alu
|
||||
,input alu_req_alu_add
|
||||
,input alu_req_alu_sub
|
||||
,input alu_req_alu_xor
|
||||
,input alu_req_alu_sll
|
||||
,input alu_req_alu_srl
|
||||
,input alu_req_alu_sra
|
||||
,input alu_req_alu_or
|
||||
,input alu_req_alu_and
|
||||
,input alu_req_alu_slt
|
||||
,input alu_req_alu_sltu
|
||||
,input alu_req_alu_lui
|
||||
,input [`QBMCU_XLEN-1:0] alu_req_alu_op1
|
||||
,input [`QBMCU_XLEN-1:0] alu_req_alu_op2
|
||||
,output [`QBMCU_XLEN-1:0] alu_req_alu_res
|
||||
|
||||
//////////////////////////////////////////////////////
|
||||
// BJP request the datapath
|
||||
,input bjp_req_alu
|
||||
,input [`QBMCU_XLEN-1:0] bjp_req_alu_op1
|
||||
,input [`QBMCU_XLEN-1:0] bjp_req_alu_op2
|
||||
,input bjp_req_alu_cmp_eq
|
||||
,input bjp_req_alu_cmp_ne
|
||||
,input bjp_req_alu_cmp_lt
|
||||
,input bjp_req_alu_cmp_gt
|
||||
,input bjp_req_alu_cmp_ltu
|
||||
,input bjp_req_alu_cmp_gtu
|
||||
,input bjp_req_alu_add
|
||||
,output bjp_req_alu_cmp_res
|
||||
,output [`QBMCU_XLEN-1:0] bjp_req_alu_add_res
|
||||
);
|
||||
|
||||
|
||||
wire [`QBMCU_XLEN-1:0] mux_op1;
|
||||
wire [`QBMCU_XLEN-1:0] mux_op2;
|
||||
|
||||
wire [`QBMCU_XLEN-1:0] misc_op1 = mux_op1[`QBMCU_XLEN-1:0];
|
||||
wire [`QBMCU_XLEN-1:0] misc_op2 = mux_op2[`QBMCU_XLEN-1:0];
|
||||
|
||||
// Only the regular ALU use shifter
|
||||
wire [`QBMCU_XLEN-1:0] shifter_op1 = alu_req_alu_op1[`QBMCU_XLEN-1:0];
|
||||
wire [`QBMCU_XLEN-1:0] shifter_op2 = alu_req_alu_op2[`QBMCU_XLEN-1:0];
|
||||
|
||||
wire op_add;
|
||||
wire op_sub;
|
||||
wire op_addsub = op_add | op_sub;
|
||||
|
||||
wire op_or;
|
||||
wire op_xor;
|
||||
wire op_and;
|
||||
|
||||
wire op_sll;
|
||||
wire op_srl;
|
||||
wire op_sra;
|
||||
|
||||
wire op_slt;
|
||||
wire op_sltu;
|
||||
|
||||
wire op_mvop2;
|
||||
|
||||
|
||||
wire op_cmp_eq ;
|
||||
wire op_cmp_ne ;
|
||||
wire op_cmp_lt ;
|
||||
wire op_cmp_gt ;
|
||||
wire op_cmp_ltu;
|
||||
wire op_cmp_gtu;
|
||||
|
||||
wire cmp_res;
|
||||
|
||||
|
||||
//////////////////////////////////////////////////////////////
|
||||
// Impelment the Left-Shifter
|
||||
//
|
||||
// The Left-Shifter will be used to handle the shift op
|
||||
wire [`QBMCU_XLEN-1:0] shifter_in1;
|
||||
wire [5-1:0] shifter_in2;
|
||||
wire [`QBMCU_XLEN-1:0] shifter_res;
|
||||
|
||||
|
||||
wire op_shift = op_sra | op_sll | op_srl;
|
||||
|
||||
// Make sure to use logic-gating to gateoff the
|
||||
assign shifter_in1 = {`QBMCU_XLEN{op_shift}} &
|
||||
// In order to save area and just use one left-shifter, we
|
||||
// convert the right-shift op into left-shift operation
|
||||
(
|
||||
(op_sra | op_srl) ?
|
||||
{
|
||||
shifter_op1[00],shifter_op1[01],shifter_op1[02],shifter_op1[03],
|
||||
shifter_op1[04],shifter_op1[05],shifter_op1[06],shifter_op1[07],
|
||||
shifter_op1[08],shifter_op1[09],shifter_op1[10],shifter_op1[11],
|
||||
shifter_op1[12],shifter_op1[13],shifter_op1[14],shifter_op1[15],
|
||||
shifter_op1[16],shifter_op1[17],shifter_op1[18],shifter_op1[19],
|
||||
shifter_op1[20],shifter_op1[21],shifter_op1[22],shifter_op1[23],
|
||||
shifter_op1[24],shifter_op1[25],shifter_op1[26],shifter_op1[27],
|
||||
shifter_op1[28],shifter_op1[29],shifter_op1[30],shifter_op1[31]
|
||||
} : shifter_op1
|
||||
);
|
||||
assign shifter_in2 = {5{op_shift}} & shifter_op2[4:0];
|
||||
|
||||
assign shifter_res = (shifter_in1 << shifter_in2);
|
||||
|
||||
wire [`QBMCU_XLEN-1:0] sll_res = shifter_res;
|
||||
wire [`QBMCU_XLEN-1:0] srl_res =
|
||||
{
|
||||
shifter_res[00],shifter_res[01],shifter_res[02],shifter_res[03],
|
||||
shifter_res[04],shifter_res[05],shifter_res[06],shifter_res[07],
|
||||
shifter_res[08],shifter_res[09],shifter_res[10],shifter_res[11],
|
||||
shifter_res[12],shifter_res[13],shifter_res[14],shifter_res[15],
|
||||
shifter_res[16],shifter_res[17],shifter_res[18],shifter_res[19],
|
||||
shifter_res[20],shifter_res[21],shifter_res[22],shifter_res[23],
|
||||
shifter_res[24],shifter_res[25],shifter_res[26],shifter_res[27],
|
||||
shifter_res[28],shifter_res[29],shifter_res[30],shifter_res[31]
|
||||
};
|
||||
|
||||
wire [`QBMCU_XLEN-1:0] eff_mask = (~(`QBMCU_XLEN'b0)) >> shifter_in2;
|
||||
wire [`QBMCU_XLEN-1:0] sra_res =
|
||||
(srl_res & eff_mask) | ({32{shifter_op1[31]}} & (~eff_mask));
|
||||
|
||||
|
||||
|
||||
//////////////////////////////////////////////////////////////
|
||||
// Impelment the Adder
|
||||
//
|
||||
// The Adder will be reused to handle the add/sub/compare op
|
||||
// all other unit request ALU-adder with 32bits opereand without sign extended
|
||||
wire op_unsigned = op_sltu | op_cmp_ltu | op_cmp_gtu;
|
||||
wire [`QBMCU_ALU_ADDER_WIDTH-1:0] misc_adder_op1 =
|
||||
{{`QBMCU_ALU_ADDER_WIDTH-`QBMCU_XLEN{(~op_unsigned) & misc_op1[`QBMCU_XLEN-1]}},misc_op1};
|
||||
wire [`QBMCU_ALU_ADDER_WIDTH-1:0] misc_adder_op2 =
|
||||
{{`QBMCU_ALU_ADDER_WIDTH-`QBMCU_XLEN{(~op_unsigned) & misc_op2[`QBMCU_XLEN-1]}},misc_op2};
|
||||
|
||||
|
||||
wire [`QBMCU_ALU_ADDER_WIDTH-1:0] adder_op1 = misc_adder_op1;
|
||||
wire [`QBMCU_ALU_ADDER_WIDTH-1:0] adder_op2 = misc_adder_op2;
|
||||
|
||||
wire adder_cin;
|
||||
wire [`QBMCU_ALU_ADDER_WIDTH-1:0] adder_in1;
|
||||
wire [`QBMCU_ALU_ADDER_WIDTH-1:0] adder_in2;
|
||||
wire [`QBMCU_ALU_ADDER_WIDTH-1:0] adder_res;
|
||||
|
||||
wire adder_add;
|
||||
wire adder_sub;
|
||||
|
||||
assign adder_add = op_add;
|
||||
assign adder_sub =
|
||||
(
|
||||
// The original sub instruction
|
||||
(op_sub)
|
||||
// The compare lt or gt instruction
|
||||
| (op_cmp_lt | op_cmp_gt |
|
||||
op_cmp_ltu | op_cmp_gtu |
|
||||
op_slt | op_sltu
|
||||
));
|
||||
|
||||
wire adder_addsub = adder_add | adder_sub;
|
||||
|
||||
|
||||
// Make sure to use logic-gating to gateoff the
|
||||
assign adder_in1 = {`QBMCU_ALU_ADDER_WIDTH{adder_addsub}} & (adder_op1);
|
||||
assign adder_in2 = {`QBMCU_ALU_ADDER_WIDTH{adder_addsub}} & (adder_sub ? (~adder_op2) : adder_op2);
|
||||
assign adder_cin = adder_addsub & adder_sub;
|
||||
|
||||
assign adder_res = adder_in1 + adder_in2 + adder_cin;
|
||||
|
||||
|
||||
|
||||
//////////////////////////////////////////////////////////////
|
||||
// Impelment the XOR-er
|
||||
//
|
||||
// The XOR-er will be reused to handle the XOR and compare op
|
||||
|
||||
wire [`QBMCU_XLEN-1:0] xorer_in1;
|
||||
wire [`QBMCU_XLEN-1:0] xorer_in2;
|
||||
|
||||
wire xorer_op =
|
||||
op_xor
|
||||
// The compare eq or ne instruction
|
||||
| (op_cmp_eq | op_cmp_ne);
|
||||
|
||||
// Make sure to use logic-gating to gateoff the
|
||||
assign xorer_in1 = {`QBMCU_XLEN{xorer_op}} & misc_op1;
|
||||
assign xorer_in2 = {`QBMCU_XLEN{xorer_op}} & misc_op2;
|
||||
|
||||
wire [`QBMCU_XLEN-1:0] xorer_res = xorer_in1 ^ xorer_in2;
|
||||
// The OR and AND is too light-weight, so no need to gate off
|
||||
wire [`QBMCU_XLEN-1:0] orer_res = misc_op1 | misc_op2;
|
||||
wire [`QBMCU_XLEN-1:0] ander_res = misc_op1 & misc_op2;
|
||||
|
||||
|
||||
//////////////////////////////////////////////////////////////
|
||||
// Generate the CMP operation result
|
||||
// It is Non-Equal if the XOR result have any bit non-zero
|
||||
wire neq = (|xorer_res);
|
||||
wire cmp_res_ne = (op_cmp_ne & neq);
|
||||
// It is Equal if it is not Non-Equal
|
||||
wire cmp_res_eq = op_cmp_eq & (~neq);
|
||||
// It is Less-Than if the adder result is negative
|
||||
wire cmp_res_lt = op_cmp_lt & adder_res[`QBMCU_XLEN];
|
||||
wire cmp_res_ltu = op_cmp_ltu & adder_res[`QBMCU_XLEN];
|
||||
// It is Greater-Than if the adder result is postive
|
||||
wire op1_gt_op2 = (~adder_res[`QBMCU_XLEN]);
|
||||
wire cmp_res_gt = op_cmp_gt & op1_gt_op2;
|
||||
wire cmp_res_gtu = op_cmp_gtu & op1_gt_op2;
|
||||
|
||||
assign cmp_res = cmp_res_eq
|
||||
| cmp_res_ne
|
||||
| cmp_res_lt
|
||||
| cmp_res_gt
|
||||
| cmp_res_ltu
|
||||
| cmp_res_gtu;
|
||||
|
||||
//////////////////////////////////////////////////////////////
|
||||
// Generate the mvop2 result
|
||||
// Just directly use op2 since the op2 will be the immediate
|
||||
wire [`QBMCU_XLEN-1:0] mvop2_res = misc_op2;
|
||||
|
||||
//////////////////////////////////////////////////////////////
|
||||
// Generate the SLT and SLTU result
|
||||
// Just directly use op2 since the op2 will be the immediate
|
||||
wire op_slttu = (op_slt | op_sltu);
|
||||
// The SLT and SLTU is reusing the adder to do the comparasion
|
||||
// It is Less-Than if the adder result is negative
|
||||
wire slttu_cmp_lt = op_slttu & adder_res[`QBMCU_XLEN];
|
||||
wire [`QBMCU_XLEN-1:0] slttu_res =
|
||||
slttu_cmp_lt ?
|
||||
`QBMCU_XLEN'b1 : `QBMCU_XLEN'b0;
|
||||
|
||||
//////////////////////////////////////////////////////////////
|
||||
// Generate the final result
|
||||
wire [`QBMCU_XLEN-1:0] alu_dpath_res =
|
||||
({`QBMCU_XLEN{op_or }} & orer_res )
|
||||
| ({`QBMCU_XLEN{op_and }} & ander_res)
|
||||
| ({`QBMCU_XLEN{op_xor }} & xorer_res)
|
||||
| ({`QBMCU_XLEN{op_addsub }} & adder_res[`QBMCU_XLEN-1:0])
|
||||
| ({`QBMCU_XLEN{op_srl }} & srl_res)
|
||||
| ({`QBMCU_XLEN{op_sll }} & sll_res)
|
||||
| ({`QBMCU_XLEN{op_sra }} & sra_res)
|
||||
| ({`QBMCU_XLEN{op_mvop2 }} & mvop2_res)
|
||||
| ({`QBMCU_XLEN{op_slttu }} & slttu_res)
|
||||
;
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////
|
||||
/////////////////////////////////////////////////////////////////////
|
||||
/////////////////////////////////////////////////////////////////////
|
||||
// The ALU-Datapath Mux for the requestors
|
||||
|
||||
localparam DPATH_MUX_WIDTH = ((`QBMCU_XLEN*2)+17);
|
||||
|
||||
assign {
|
||||
mux_op1
|
||||
,mux_op2
|
||||
,op_add
|
||||
,op_sub
|
||||
,op_or
|
||||
,op_xor
|
||||
,op_and
|
||||
,op_sll
|
||||
,op_srl
|
||||
,op_sra
|
||||
,op_slt
|
||||
,op_sltu
|
||||
,op_mvop2
|
||||
,op_cmp_eq
|
||||
,op_cmp_ne
|
||||
,op_cmp_lt
|
||||
,op_cmp_gt
|
||||
,op_cmp_ltu
|
||||
,op_cmp_gtu
|
||||
}
|
||||
=
|
||||
({DPATH_MUX_WIDTH{alu_req_alu}} & {
|
||||
alu_req_alu_op1
|
||||
,alu_req_alu_op2
|
||||
,alu_req_alu_add
|
||||
,alu_req_alu_sub
|
||||
,alu_req_alu_or
|
||||
,alu_req_alu_xor
|
||||
,alu_req_alu_and
|
||||
,alu_req_alu_sll
|
||||
,alu_req_alu_srl
|
||||
,alu_req_alu_sra
|
||||
,alu_req_alu_slt
|
||||
,alu_req_alu_sltu
|
||||
,alu_req_alu_lui// LUI just move-Op2 operation
|
||||
,1'b0
|
||||
,1'b0
|
||||
,1'b0
|
||||
,1'b0
|
||||
,1'b0
|
||||
,1'b0
|
||||
})
|
||||
| ({DPATH_MUX_WIDTH{bjp_req_alu}} & {
|
||||
bjp_req_alu_op1
|
||||
,bjp_req_alu_op2
|
||||
,bjp_req_alu_add
|
||||
,1'b0
|
||||
,1'b0
|
||||
,1'b0
|
||||
,1'b0
|
||||
,1'b0
|
||||
,1'b0
|
||||
,1'b0
|
||||
,1'b0
|
||||
,1'b0
|
||||
,1'b0
|
||||
,bjp_req_alu_cmp_eq
|
||||
,bjp_req_alu_cmp_ne
|
||||
,bjp_req_alu_cmp_lt
|
||||
,bjp_req_alu_cmp_gt
|
||||
,bjp_req_alu_cmp_ltu
|
||||
,bjp_req_alu_cmp_gtu
|
||||
|
||||
})
|
||||
;
|
||||
|
||||
assign alu_req_alu_res = alu_dpath_res[`QBMCU_XLEN-1:0];
|
||||
assign bjp_req_alu_add_res = alu_dpath_res[`QBMCU_XLEN-1:0];
|
||||
assign bjp_req_alu_cmp_res = cmp_res;
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
`include "qbmcu_undefines.v"
|
||||
|
||||
|
|
@ -0,0 +1,122 @@
|
|||
//+FHDR--------------------------------------------------------------------------------------------------------
|
||||
// Company:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// File Name : qbmcu_exu_ext.v
|
||||
// Department :
|
||||
// Author : PWY
|
||||
// Author's Tel :
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Relese History
|
||||
// Version Date Author Description
|
||||
// 0.1 2024-03-13 PWY This module to implement the regular EXT instructions
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Keywords :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Parameter
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Purpose :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Target Device:
|
||||
// Tool versions:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Reuse Issues
|
||||
// Reset Strategy:
|
||||
// Clock Domains:
|
||||
// Critical Timing:
|
||||
// Asynchronous I/F:
|
||||
// Synthesizable (y/n):
|
||||
// Other:
|
||||
//-FHDR--------------------------------------------------------------------------------------------------------
|
||||
|
||||
`include "qbmcu_defines.v"
|
||||
|
||||
|
||||
module qbmcu_exu_ext(
|
||||
//system port
|
||||
input clk
|
||||
,input rst_n
|
||||
//////////////////////////////////////////////////////////////
|
||||
//////////////////////////////////////////////////////////////
|
||||
,input [`QBMCU_XLEN-1 :0] ext_i_rs1
|
||||
,input [`QBMCU_XLEN-1 :0] ext_i_imm
|
||||
,input [`QBMCU_DECINFO_EXT_WIDTH-1:0] ext_i_info
|
||||
,input ext_i_op
|
||||
//The enable signal from the master control state machine
|
||||
,input ext_i_active
|
||||
|
||||
//////////////////////////////////////////////////////////////
|
||||
//////////////////////////////////////////////////////////////
|
||||
//
|
||||
// The operands and info to peripheral
|
||||
,output ext_o_wait_valid
|
||||
,output ext_o_wait
|
||||
,output [`QBMCU_XLEN-1 :0] ext_o_wait_cnt
|
||||
,output ext_o_send
|
||||
,output ext_o_sendc
|
||||
,output [`QBMCU_XLEN-1 :0] ext_o_codeword
|
||||
,output ext_o_exit
|
||||
,output ext_o_intr
|
||||
,output [`QBMCU_XLEN-1 :0] ext_o_wbck_wdat
|
||||
,output ext_o_wbck_valid
|
||||
);
|
||||
|
||||
|
||||
wire [`QBMCU_XLEN-1:0] ext_req_alu_op1 = ext_i_rs1;
|
||||
wire [`QBMCU_XLEN-1:0] ext_req_alu_op2 = ext_i_imm;
|
||||
|
||||
wire [`QBMCU_XLEN-1:0] ext_req_alu_res = ext_req_alu_op1 + ext_req_alu_op2;
|
||||
wire alu_req_alu_wait = ext_i_op & ext_i_info [`QBMCU_DECINFO_EXT_WAIT ];
|
||||
wire alu_req_alu_send = ext_i_op & ext_i_info [`QBMCU_DECINFO_EXT_SEND ];
|
||||
wire alu_req_alu_sendc = ext_i_op & ext_i_info [`QBMCU_DECINFO_EXT_SENDC ];
|
||||
wire alu_req_alu_exit = ext_i_op & ext_i_info [`QBMCU_DECINFO_EXT_EXIT ];
|
||||
wire alu_req_alu_exiti = ext_i_op & ext_i_info [`QBMCU_DECINFO_EXT_EXITI ];
|
||||
|
||||
//ext_o_codeword
|
||||
sirv_gnrl_dfflr #(`QBMCU_XLEN) ext_o_codeword_dfflr (ext_i_active, ext_req_alu_res, ext_o_codeword, clk, rst_n);
|
||||
|
||||
//ext_o_wait_cnt
|
||||
//sirv_gnrl_dfflr #(`QBMCU_XLEN) ext_o_wait_cnt_dfflr (ext_i_active, ext_req_alu_res, ext_o_wait_cnt, clk, rst_n);
|
||||
assign ext_o_wait_cnt = ext_req_alu_res;
|
||||
//ext_o_wait
|
||||
wire ext_wait = ext_i_active & alu_req_alu_wait;
|
||||
//sirv_gnrl_dffr #(1) ext_o_wait_dffr (ext_wait, ext_o_wait, clk, rst_n);
|
||||
assign ext_o_wait = ext_wait;
|
||||
|
||||
wire ext_o_wait_valid_en = ext_wait | ext_i_active;
|
||||
wire ext_o_wait_valid_v = ext_wait ? 1'b1 :
|
||||
ext_i_active ? 1'b0 :
|
||||
1'b0 ;
|
||||
sirv_gnrl_dfflr #(1) ext_o_wait_valid_dfflr (ext_o_wait_valid_en, ext_o_wait_valid_v, ext_o_wait_valid, clk, rst_n);
|
||||
//ext_o_send
|
||||
wire ext_send = ext_i_active & alu_req_alu_send;
|
||||
sirv_gnrl_dffr #(1) ext_o_send_dffr (ext_send, ext_o_send, clk, rst_n);
|
||||
|
||||
//ext_o_sendc
|
||||
wire ext_sendc = ext_i_active & alu_req_alu_sendc;
|
||||
sirv_gnrl_dffr #(1) ext_o_sendc_dffr (ext_sendc, ext_o_sendc, clk, rst_n);
|
||||
|
||||
//ext_o_exit
|
||||
assign ext_o_exit = alu_req_alu_exit | alu_req_alu_exiti;
|
||||
//sirv_gnrl_dfflr #(1) ext_o_exit_dfflr (ext_i_active, ext_exit, ext_o_exit, clk, rst_n);
|
||||
|
||||
//ext_o_intr
|
||||
wire ext_intr = ext_i_active & alu_req_alu_exiti;
|
||||
sirv_gnrl_dffr #(1) ext_o_intr_dffr (ext_intr, ext_o_intr, clk, rst_n);
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
/////////////////////////////////////////////////////////////////////////////////////////////
|
||||
//ext_i_active_r
|
||||
wire ext_i_active_r;
|
||||
sirv_gnrl_dffr #(1) ext_i_active_r_dffr (ext_i_active, ext_i_active_r, clk, rst_n);
|
||||
//ext_o_wbck_wdat
|
||||
sirv_gnrl_dfflr #(`QBMCU_XLEN) ext_o_wbck_wdat_dfflr (ext_i_active_r, ext_req_alu_res, ext_o_wbck_wdat, clk, rst_n);
|
||||
//ext_o_wbck_valid
|
||||
sirv_gnrl_dfflr #(1) ext_o_wbck_valid_dfflr (ext_i_active_r, ext_i_op, ext_o_wbck_valid, clk, rst_n);
|
||||
|
||||
|
||||
endmodule
|
||||
`include "qbmcu_undefines.v"
|
||||
|
|
@ -0,0 +1,175 @@
|
|||
//+FHDR--------------------------------------------------------------------------------------------------------
|
||||
// Company:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// File Name : qbmcu_exu_lsuagu.v
|
||||
// Department :
|
||||
// Author : PWY
|
||||
// Author's Tel :
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Relese History
|
||||
// Version Date Author Description
|
||||
// 0.1 2024-03-13 PWY This module to implement the AGU (address generation unit
|
||||
// for load/store instructions)
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Keywords :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Parameter
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Purpose :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Target Device:
|
||||
// Tool versions:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Reuse Issues
|
||||
// Reset Strategy:
|
||||
// Clock Domains:
|
||||
// Critical Timing:
|
||||
// Asynchronous I/F:
|
||||
// Synthesizable (y/n):
|
||||
// Other:
|
||||
//-FHDR--------------------------------------------------------------------------------------------------------
|
||||
|
||||
`include "qbmcu_defines.v"
|
||||
|
||||
module qbmcu_exu_lsuagu(
|
||||
//system port
|
||||
input clk
|
||||
,input rst_n
|
||||
//////////////////////////////////////////////////////////////
|
||||
//The operands and instruction information from the decoding module
|
||||
,input [`QBMCU_XLEN-1 :0] agu_i_rs1
|
||||
,input [`QBMCU_XLEN-1 :0] agu_i_rs2
|
||||
,input [`QBMCU_XLEN-1 :0] agu_i_imm
|
||||
,input [`QBMCU_DECINFO_AGU_WIDTH-1:0] agu_i_info
|
||||
,input agu_i_op
|
||||
//The enable signal from the master control state machine
|
||||
,input agu_i_active
|
||||
//////////////////////////////////////////////////////////////
|
||||
//Address, data, and enable signals connected to the memory space
|
||||
,output [`QBMCU_ADDR_SIZE-1 :0] agu_o_addr
|
||||
,output [`QBMCU_XLEN-1 :0] agu_o_wdata
|
||||
,output agu_o_wren // Write enable
|
||||
,output agu_o_rden // Read enable
|
||||
,output [`QBMCU_XLEN/8-1 :0] agu_o_wmask
|
||||
,input [`QBMCU_XLEN-1 :0] agu_i_rdata
|
||||
//////////////////////////////////////////////////////////////
|
||||
//Data sent to the write-back module
|
||||
//write back interface
|
||||
,output [`QBMCU_XLEN-1 :0] agu_o_wbck_wdat
|
||||
,output agu_o_wbck_valid
|
||||
//Misaligned memory address
|
||||
,output agu_o_addr_unalgn
|
||||
);
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//Memory Address Generation
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
//Generate Operand 1
|
||||
wire [`QBMCU_XLEN-1:0] agu_addr_gen_op1 = agu_i_rs1;
|
||||
|
||||
//The Operand 2 of the memory access instructions are immediate values
|
||||
wire [`QBMCU_XLEN-1:0] agu_addr_gen_op2 = agu_i_imm;
|
||||
|
||||
wire [`QBMCU_ADDR_SIZE-1:0] agu_addr = agu_addr_gen_op1 + agu_addr_gen_op2;
|
||||
|
||||
//Fetch memory access instruction
|
||||
//Load operation
|
||||
wire agu_i_load = agu_i_op & agu_i_info [`QBMCU_DECINFO_AGU_LOAD ] ;
|
||||
//Store operation
|
||||
wire agu_i_store = agu_i_op & agu_i_info [`QBMCU_DECINFO_AGU_STORE ] ;
|
||||
|
||||
//Fetching memory size
|
||||
wire [1:0] agu_i_size = {2{agu_i_op}} & agu_i_info [`QBMCU_DECINFO_AGU_SIZE ];
|
||||
//sign extraction
|
||||
wire agu_i_usign = agu_i_op & agu_i_info [`QBMCU_DECINFO_AGU_USIGN ];
|
||||
|
||||
//Generate size information
|
||||
wire agu_i_size_b = (agu_i_size == 2'b00);
|
||||
wire agu_i_size_hw = (agu_i_size == 2'b01);
|
||||
wire agu_i_size_w = (agu_i_size == 2'b10);
|
||||
|
||||
//Generation of misaligned memory access signal
|
||||
wire agu_i_addr_unalgn =
|
||||
(agu_i_size_hw & agu_addr[0] )
|
||||
| (agu_i_size_w & (|agu_addr[1:0]));
|
||||
|
||||
wire agu_addr_unalgn = agu_i_addr_unalgn;
|
||||
|
||||
//Abnormal memory access operation
|
||||
wire agu_i_unalgnld = (agu_addr_unalgn & agu_i_load);
|
||||
wire agu_i_unalgnst = (agu_addr_unalgn & agu_i_store) ;
|
||||
wire agu_i_unalgnldst = (agu_i_unalgnld | agu_i_unalgnst);
|
||||
|
||||
//Normal memory access operation
|
||||
wire agu_i_algnld = (~agu_addr_unalgn) & agu_i_load;
|
||||
wire agu_i_algnst = (~agu_addr_unalgn) & agu_i_store;
|
||||
wire agu_i_algnldst = (agu_i_algnld | agu_i_algnst);
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//Read/Write Command, and Data Generation
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//write enable, active hight
|
||||
wire agu_wren = (agu_i_algnldst & agu_i_store) & agu_i_active;
|
||||
//read enable, active hight
|
||||
wire agu_rden = (agu_i_algnldst & agu_i_load ) & agu_i_active;
|
||||
//write data
|
||||
wire [`QBMCU_XLEN-1:0] algnst_wdata =
|
||||
({`QBMCU_XLEN{agu_i_size_b }} & {4{agu_i_rs2[ 7:0]}})
|
||||
| ({`QBMCU_XLEN{agu_i_size_hw}} & {2{agu_i_rs2[15:0]}})
|
||||
| ({`QBMCU_XLEN{agu_i_size_w }} & {1{agu_i_rs2[31:0]}});
|
||||
|
||||
//write mask
|
||||
wire [`QBMCU_XLEN/8-1:0] algnst_wmask =
|
||||
({`QBMCU_XLEN/8{agu_i_size_b }} & (4'b0001 << agu_addr[1:0]))
|
||||
| ({`QBMCU_XLEN/8{agu_i_size_hw}} & (4'b0011 << {agu_addr[1],1'b0}))
|
||||
| ({`QBMCU_XLEN/8{agu_i_size_w }} & (4'b1111));
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Write-Back Data Generation
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
wire agu_lbu = agu_i_size_b & agu_i_usign;
|
||||
wire agu_lb = agu_i_size_b & ~agu_i_usign;
|
||||
wire agu_lhu = agu_i_size_hw & agu_i_usign;
|
||||
wire agu_lh = agu_i_size_hw & ~agu_i_usign;
|
||||
wire agu_lw = agu_i_size_w;
|
||||
|
||||
//Write-Back Data
|
||||
wire [`QBMCU_XLEN-1:0] agu_wbck_wdat =
|
||||
( ({`QBMCU_XLEN{agu_lbu}} & {{24{ 1'b0}} , agu_i_rdata[8*(agu_addr[1:0]+1)-1-:8]})
|
||||
| ({`QBMCU_XLEN{agu_lb }} & {{24{agu_i_rdata[8*(agu_addr[1:0]+1)-1]}}, agu_i_rdata[8*(agu_addr[1:0]+1)-1-:8]})
|
||||
| ({`QBMCU_XLEN{agu_lhu}} & {{16{ 1'b0}} , agu_i_rdata[16*(agu_addr[1]+1)-1-:16]})
|
||||
| ({`QBMCU_XLEN{agu_lh }} & {{16{agu_i_rdata[16*(agu_addr[1]+1)-1]}} , agu_i_rdata[16*(agu_addr[1]+1)-1-:16]})
|
||||
| ({`QBMCU_XLEN{agu_lw }} & agu_i_rdata[31:0]));
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// Output
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//agu_o_wren
|
||||
sirv_gnrl_dffr #(1) agu_o_wren_dffr (agu_wren, agu_o_wren, clk, rst_n);
|
||||
//agu_o_wdata
|
||||
sirv_gnrl_dfflr #(`QBMCU_XLEN) agu_o_wdata_dfflr (agu_i_active, algnst_wdata, agu_o_wdata, clk, rst_n);
|
||||
//agu_o_wmask
|
||||
sirv_gnrl_dfflr #(`QBMCU_XLEN/8) agu_o_wmask_dfflr (agu_i_active, algnst_wmask, agu_o_wmask, clk, rst_n);
|
||||
//agu_o_addr
|
||||
sirv_gnrl_dfflr #(`QBMCU_ADDR_SIZE) agu_o_addr_dfflr (agu_i_active, agu_addr, agu_o_addr, clk, rst_n);
|
||||
|
||||
//agu_o_rden
|
||||
sirv_gnrl_dffr #(1) agu_o_rden_dffr (agu_rden, agu_o_rden, clk, rst_n);
|
||||
|
||||
//agu_o_wbck_wdat
|
||||
//sirv_gnrl_dffr #(`QBMCU_XLEN) agu_o_wbck_wdat_dffr (agu_wbck_wdat, agu_o_wbck_wdat, clk, rst_n);
|
||||
assign agu_o_wbck_wdat = agu_wbck_wdat;
|
||||
//agu_o_wbck_valid
|
||||
sirv_gnrl_dfflr #(1) agu_o_wbck_valid_dfflr (agu_i_active, agu_i_op, agu_o_wbck_valid, clk, rst_n);
|
||||
|
||||
//agu_o_addr_unalgn
|
||||
sirv_gnrl_dfflr #(1) agu_o_addr_unalgn_dfflr (agu_i_active, agu_i_unalgnldst, agu_o_addr_unalgn, clk, rst_n);
|
||||
|
||||
endmodule
|
||||
|
||||
`include "qbmcu_undefines.v"
|
||||
|
||||
|
|
@ -0,0 +1,113 @@
|
|||
//+FHDR--------------------------------------------------------------------------------------------------------
|
||||
// Company:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// File Name : qbmcu_fsm.v
|
||||
// Department :
|
||||
// Author : PWY
|
||||
// Author's Tel :
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Relese History
|
||||
// Version Date Author Description
|
||||
// 0.1 2024-03-13 PWY The ifetch module to generate next PC and bus request
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Keywords :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Parameter
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Purpose :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Target Device:
|
||||
// Tool versions:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Reuse Issues
|
||||
// Reset Strategy:
|
||||
// Clock Domains:
|
||||
// Critical Timing:
|
||||
// Asynchronous I/F:
|
||||
// Synthesizable (y/n):
|
||||
// Other:
|
||||
//-FHDR--------------------------------------------------------------------------------------------------------
|
||||
|
||||
`include "qbmcu_defines.v"
|
||||
|
||||
module qbmcu_fsm (
|
||||
input clk
|
||||
,input rst_n
|
||||
,input start
|
||||
,input exit
|
||||
,input ext_wait
|
||||
,input qbmcu_timer_done
|
||||
,input dec_ilegl
|
||||
,input agu_addr_unalgn
|
||||
,output ifupc_rst
|
||||
,output ifu_active
|
||||
,output wb_active
|
||||
,output dec_active
|
||||
,output exu_active
|
||||
,output [2:0] qbmcu_fsm_st
|
||||
);
|
||||
|
||||
localparam IDLE = 3'b000,
|
||||
IFUWB = 3'b001,
|
||||
DEC = 3'b010,
|
||||
EXU = 3'b011,
|
||||
WAIT = 3'b100;
|
||||
|
||||
wire [2:0] state_c;
|
||||
wire [2:0] state_n;
|
||||
wire ilde2ifuwb;
|
||||
wire ifuwb2dec;
|
||||
wire dec2exu;
|
||||
wire exu2ifuwb;
|
||||
wire exu2idle;
|
||||
wire exu2wait;
|
||||
wire wait2ifuwb;
|
||||
|
||||
//The first section of the state machine
|
||||
//state_c
|
||||
sirv_gnrl_dffr #(3) state_c_dffr (state_n, state_c, clk, rst_n);
|
||||
|
||||
//////////////////////////////////////////////////////////////
|
||||
//fsm
|
||||
//////////////////////////////////////////////////////////////
|
||||
|
||||
//state_n
|
||||
assign state_n = //(rst_n == 1'b0) ? IDLE :
|
||||
((state_c == IDLE ) && ilde2ifuwb) ? IFUWB :
|
||||
((state_c == IFUWB) && ifuwb2dec ) ? DEC :
|
||||
((state_c == DEC ) && dec2exu ) ? EXU :
|
||||
((state_c == EXU ) && exu2idle ) ? IDLE :
|
||||
((state_c == EXU ) && exu2ifuwb ) ? IFUWB :
|
||||
((state_c == EXU ) && exu2wait ) ? WAIT :
|
||||
((state_c == WAIT ) && wait2ifuwb) ? IFUWB :
|
||||
state_c ;
|
||||
|
||||
//Generating jump conditions for state machines
|
||||
assign ilde2ifuwb = (state_c == IDLE ) && start;
|
||||
assign ifuwb2dec = (state_c == IFUWB) ;
|
||||
assign dec2exu = (state_c == DEC ) ;
|
||||
assign exu2ifuwb = (state_c == EXU ) && !ext_wait && !(exit | dec_ilegl | agu_addr_unalgn);
|
||||
assign exu2wait = (state_c == EXU ) && ext_wait && !(exit | dec_ilegl | agu_addr_unalgn);
|
||||
assign exu2idle = (state_c == EXU ) && (exit | dec_ilegl | agu_addr_unalgn);
|
||||
assign wait2ifuwb = (state_c == WAIT ) && qbmcu_timer_done ;
|
||||
|
||||
//Output signal generation
|
||||
//ifupc_rst
|
||||
sirv_gnrl_dffr #(1) ifupc_rst_dffr (exu2idle, ifupc_rst, clk, rst_n);
|
||||
//ifu_active
|
||||
sirv_gnrl_dffr #(1) ifu_active_dffr (ilde2ifuwb | exu2ifuwb | wait2ifuwb, ifu_active, clk, rst_n);
|
||||
//wb_active
|
||||
sirv_gnrl_dffr #(1) wb_active_dffr (exu2ifuwb | wait2ifuwb, wb_active, clk, rst_n);
|
||||
//dec_active
|
||||
sirv_gnrl_dffr #(1) dec_active_dffr (ifuwb2dec, dec_active, clk, rst_n);
|
||||
//exu_active
|
||||
sirv_gnrl_dffr #(1) exu_active_dffr (dec2exu, exu_active, clk, rst_n);
|
||||
//qbmcu_fsm_st
|
||||
sirv_gnrl_dffr #(3) qbmcu_fsm_st_dffr (state_c, qbmcu_fsm_st, clk, rst_n);
|
||||
|
||||
|
||||
endmodule
|
||||
`include "qbmcu_undefines.v"
|
||||
|
|
@ -0,0 +1,119 @@
|
|||
//+FHDR--------------------------------------------------------------------------------------------------------
|
||||
// Company:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// File Name : qbmcu_ifu.v
|
||||
// Department :
|
||||
// Author : PWY
|
||||
// Author's Tel :
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Relese History
|
||||
// Version Date Author Description
|
||||
// 0.1 2024-03-13 PWY The ifetch module to generate next PC and bus request
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Keywords :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Parameter
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Purpose :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Target Device:
|
||||
// Tool versions:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Reuse Issues
|
||||
// Reset Strategy:
|
||||
// Clock Domains:
|
||||
// Critical Timing:
|
||||
// Asynchronous I/F:
|
||||
// Synthesizable (y/n):
|
||||
// Other:
|
||||
//-FHDR--------------------------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
`include "qbmcu_defines.v"
|
||||
|
||||
module qbmcu_ifu(
|
||||
input clk // System Clock
|
||||
,input rst_n // System reset,active low
|
||||
,input ifu_active // IFU module Active from MCU FSM
|
||||
,input exu_active // IFU module Active from MCU FSM
|
||||
,input [`QBMCU_PC_SIZE-1 :0] pc_rtvec // Initial PC
|
||||
,output [`QBMCU_PC_SIZE-1 :0] ifu_req_pc // Fetch PC
|
||||
,output ifu_req // Fetch req
|
||||
|
||||
,input [`QBMCU_INSTR_SIZE-1:0] ifu_rsp_instr // Response instruction
|
||||
// The IR stage to DEC interface
|
||||
,output [`QBMCU_INSTR_SIZE-1:0] ifu_o_ir // The instruction register
|
||||
,output [`QBMCU_PC_SIZE-1 :0] ifu_o_pc // The PC register along with
|
||||
,input ifupc_rst
|
||||
,input update_pc_req
|
||||
,input [`QBMCU_PC_SIZE-1 :0] update_pc_value
|
||||
);
|
||||
|
||||
|
||||
wire ifu_req_w;
|
||||
wire [`QBMCU_PC_SIZE-1 :0] pc_r;
|
||||
//wire pc_ena;
|
||||
//wire [`QBMCU_INSTR_SIZE-1 :0] ifu_ir_r;// The instruction register
|
||||
//wire [`QBMCU_PC_SIZE-1 :0] ifu_pc_r;// The PC register
|
||||
|
||||
wire [`QBMCU_PC_SIZE-1:0] pc_nxt_pre;
|
||||
wire [`QBMCU_PC_SIZE-1:0] pc_nxt;
|
||||
//ifu_req
|
||||
assign ifu_req_w = ifu_active;
|
||||
|
||||
|
||||
|
||||
wire [`QBMCU_PC_SIZE-1:0] pc_add_op1 =
|
||||
(rst_n == 1'b0 | ifupc_rst) ? pc_rtvec :
|
||||
pc_r;
|
||||
|
||||
wire [`QBMCU_PC_SIZE-1:0] pc_add_op2 =
|
||||
(rst_n == 1'b0 | ifupc_rst) ? `QBMCU_PC_SIZE'b0 :
|
||||
32'h4 ;
|
||||
|
||||
assign pc_nxt_pre = pc_add_op1 + pc_add_op2;
|
||||
//pc_nxt
|
||||
assign pc_nxt = update_pc_req ? {update_pc_value[`QBMCU_PC_SIZE-1:1],1'b0} :
|
||||
{pc_nxt_pre[`QBMCU_PC_SIZE-1:1] ,1'b0};
|
||||
|
||||
|
||||
|
||||
// The PC will need to be updated when MCU's FSM is IFU status
|
||||
//sirv_gnrl_dffr #(1) pc_ena_dffr (ifu_active, pc_ena, clk, rst_n);
|
||||
//pc_r
|
||||
sirv_gnrl_dfflr #(`QBMCU_PC_SIZE) pc_dfflr (exu_active, pc_nxt, pc_r, clk, rst_n & ~ifupc_rst);
|
||||
/*
|
||||
always @(posedge clk or negedge rst_n) begin
|
||||
if(rst_n == 1'b0) begin
|
||||
pc_r <= `QBMCU_PC_SIZE'h0;
|
||||
end
|
||||
else if(ifupc_rst) begin
|
||||
pc_r <= `QBMCU_PC_SIZE'h0;
|
||||
end
|
||||
else if(exu_active) begin
|
||||
pc_r <= pc_nxt;
|
||||
end
|
||||
end
|
||||
*/
|
||||
// IFU-IR loaded with the returned instruction from the IFetch RSP channel
|
||||
wire [`QBMCU_INSTR_SIZE-1:0] ifu_ir_nxt = ifu_rsp_instr;
|
||||
//ifu_ir_r
|
||||
//sirv_gnrl_dfflr #(`QBMCU_INSTR_SIZE) ifu_ir_dfflr (ifu_active, ifu_ir_nxt, ifu_ir_r, clk, rst_n);
|
||||
|
||||
//ifu_pc_r
|
||||
//sirv_gnrl_dfflr #(`QBMCU_PC_SIZE) ifu_pc_dfflr (ifu_active, pc_r, ifu_pc_r, clk, rst_n);
|
||||
|
||||
//ifu_req_pc
|
||||
assign ifu_req_pc = pc_r;
|
||||
|
||||
assign ifu_req = ifu_req_w;
|
||||
//assign ifu_req = pc_ena;
|
||||
|
||||
assign ifu_o_ir = ifu_ir_nxt;
|
||||
assign ifu_o_pc = pc_r;
|
||||
|
||||
endmodule
|
||||
`include "qbmcu_undefines.v"
|
||||
|
|
@ -0,0 +1,75 @@
|
|||
//+FHDR--------------------------------------------------------------------------------------------------------
|
||||
// Company:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// File Name : qbmcu_regfile.v
|
||||
// Department :
|
||||
// Author : PWY
|
||||
// Author's Tel :
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Relese History
|
||||
// Version Date Author Description
|
||||
// 0.1 2024-03-13 PWY The Regfile module to implement the core's general purpose registers file
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Keywords :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Parameter
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Purpose :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Target Device:
|
||||
// Tool versions:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Reuse Issues
|
||||
// Reset Strategy:
|
||||
// Clock Domains:
|
||||
// Critical Timing:
|
||||
// Asynchronous I/F:
|
||||
// Synthesizable (y/n):
|
||||
// Other:
|
||||
//-FHDR--------------------------------------------------------------------------------------------------------
|
||||
|
||||
`include "qbmcu_defines.v"
|
||||
|
||||
module qbmcu_regfile(
|
||||
input clk
|
||||
,input rst_n
|
||||
,input [`QBMCU_RFIDX_WIDTH-1:0] read_src1_idx
|
||||
,input [`QBMCU_RFIDX_WIDTH-1:0] read_src2_idx
|
||||
,output [`QBMCU_XLEN-1 :0] read_src1_dat
|
||||
,output [`QBMCU_XLEN-1 :0] read_src2_dat
|
||||
|
||||
,input wbck_dest_wen
|
||||
,input [`QBMCU_RFIDX_WIDTH-1:0] wbck_dest_idx
|
||||
,input [`QBMCU_XLEN-1 :0] wbck_dest_dat
|
||||
);
|
||||
|
||||
wire [`QBMCU_XLEN-1 :0] rf_r [`QBMCU_RFREG_NUM-1:0];
|
||||
wire [`QBMCU_RFREG_NUM-1:0] rf_wen;
|
||||
|
||||
genvar i;
|
||||
generate //{
|
||||
for (i=0; i<`QBMCU_RFREG_NUM; i=i+1) begin:regfile//{
|
||||
|
||||
if(i==0) begin: rf0
|
||||
// x0 cannot be wrote since it is constant-zeros
|
||||
assign rf_wen[i] = 1'b0;
|
||||
assign rf_r[i] = `QBMCU_XLEN'b0;
|
||||
end
|
||||
else begin: rfno0
|
||||
assign rf_wen[i] = wbck_dest_wen & (wbck_dest_idx == i) ;
|
||||
sirv_gnrl_dfflr #(`QBMCU_XLEN) rf_dfflr (rf_wen[i], wbck_dest_dat, rf_r[i], clk, rst_n);
|
||||
end
|
||||
|
||||
end//}
|
||||
endgenerate//}
|
||||
|
||||
assign read_src1_dat = rf_r[read_src1_idx];
|
||||
assign read_src2_dat = rf_r[read_src2_idx];
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
`include "qbmcu_undefines.v"
|
||||
|
|
@ -0,0 +1,219 @@
|
|||
//+FHDR--------------------------------------------------------------------------------------------------------
|
||||
// Company:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// File Name : qbmcu.v
|
||||
// Department :
|
||||
// Author : PWY
|
||||
// Author's Tel :
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Relese History
|
||||
// Version Date Author Description
|
||||
// 0.1 2024-03-13 PWY The files to include all the macro undefs
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Keywords :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Parameter
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Purpose :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Target Device:
|
||||
// Tool versions:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Reuse Issues
|
||||
// Reset Strategy:
|
||||
// Clock Domains:
|
||||
// Critical Timing:
|
||||
// Asynchronous I/F:
|
||||
// Synthesizable (y/n):
|
||||
// Other:
|
||||
//-FHDR--------------------------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
/////// ISA relevant macro
|
||||
//
|
||||
//system address width
|
||||
`undef QBMCU_ADDR_SIZE
|
||||
|
||||
//PC width
|
||||
`undef QBMCU_PC_SIZE
|
||||
|
||||
//system data width
|
||||
`undef QBMCU_XLEN
|
||||
//system instruction width
|
||||
`undef QBMCU_INSTR_SIZE
|
||||
|
||||
//register array index bit width
|
||||
`undef QBMCU_RFIDX_WIDTH
|
||||
//number of register arrays
|
||||
`undef QBMCU_RFREG_NUM
|
||||
|
||||
//base address of instruction memory
|
||||
//initial value of the program counter (PC) -> 0x0000_0000
|
||||
`undef QBMCU_DTCM_ADDR_BASE
|
||||
//base address of data memory
|
||||
`undef QBMCU_ITCM_ADDR_BASE
|
||||
|
||||
//data memory address width
|
||||
`undef QBMCU_DTCM_ADDR_SIZE
|
||||
|
||||
//instruction memory address width
|
||||
`undef QBMCU_ITCM_ADDR_SIZE
|
||||
|
||||
//BUS memory address width
|
||||
`undef QBMCU_BUS_ADDR_SIZE
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
/////// ALU relevant macro
|
||||
//
|
||||
|
||||
`undef QBMCU_ALU_ADDER_WIDTH
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
/////// Decode relevant macro
|
||||
//
|
||||
`undef QBMCU_DECINFO_GRP_WIDTH
|
||||
`undef QBMCU_DECINFO_GRP_ALU
|
||||
`undef QBMCU_DECINFO_GRP_AGU
|
||||
`undef QBMCU_DECINFO_GRP_BJP
|
||||
`undef QBMCU_DECINFO_GRP_EXT
|
||||
|
||||
|
||||
`undef QBMCU_DECINFO_GRP_LSB
|
||||
`undef QBMCU_DECINFO_GRP_MSB
|
||||
`undef QBMCU_DECINFO_GRP
|
||||
`undef QBMCU_DECINFO_RV32_LSB
|
||||
`undef QBMCU_DECINFO_RV32_MSB
|
||||
`undef QBMCU_DECINFO_RV32
|
||||
|
||||
`undef QBMCU_DECINFO_SUBDECINFO_LSB
|
||||
|
||||
// ALU group
|
||||
`undef QBMCU_DECINFO_ALU_ADD_LSB
|
||||
`undef QBMCU_DECINFO_ALU_ADD_MSB
|
||||
`undef QBMCU_DECINFO_ALU_ADD
|
||||
`undef QBMCU_DECINFO_ALU_SUB_LSB
|
||||
`undef QBMCU_DECINFO_ALU_SUB_MSB
|
||||
`undef QBMCU_DECINFO_ALU_SUB
|
||||
`undef QBMCU_DECINFO_ALU_XOR_LSB
|
||||
`undef QBMCU_DECINFO_ALU_XOR_MSB
|
||||
`undef QBMCU_DECINFO_ALU_XOR
|
||||
`undef QBMCU_DECINFO_ALU_SLL_LSB
|
||||
`undef QBMCU_DECINFO_ALU_SLL_MSB
|
||||
`undef QBMCU_DECINFO_ALU_SLL
|
||||
`undef QBMCU_DECINFO_ALU_SRL_LSB
|
||||
`undef QBMCU_DECINFO_ALU_SRL_MSB
|
||||
`undef QBMCU_DECINFO_ALU_SRL
|
||||
`undef QBMCU_DECINFO_ALU_SRA_LSB
|
||||
`undef QBMCU_DECINFO_ALU_SRA_MSB
|
||||
`undef QBMCU_DECINFO_ALU_SRA
|
||||
`undef QBMCU_DECINFO_ALU_OR_LSB
|
||||
`undef QBMCU_DECINFO_ALU_OR_MSB
|
||||
`undef QBMCU_DECINFO_ALU_OR
|
||||
`undef QBMCU_DECINFO_ALU_AND_LSB
|
||||
`undef QBMCU_DECINFO_ALU_AND_MSB
|
||||
`undef QBMCU_DECINFO_ALU_AND
|
||||
`undef QBMCU_DECINFO_ALU_SLT_LSB
|
||||
`undef QBMCU_DECINFO_ALU_SLT_MSB
|
||||
`undef QBMCU_DECINFO_ALU_SLT
|
||||
`undef QBMCU_DECINFO_ALU_SLTU_LSB
|
||||
`undef QBMCU_DECINFO_ALU_SLTU_MSB
|
||||
`undef QBMCU_DECINFO_ALU_SLTU
|
||||
`undef QBMCU_DECINFO_ALU_LUI_LSB
|
||||
`undef QBMCU_DECINFO_ALU_LUI_MSB
|
||||
`undef QBMCU_DECINFO_ALU_LUI
|
||||
`undef QBMCU_DECINFO_ALU_OP2IMM_LSB
|
||||
`undef QBMCU_DECINFO_ALU_OP2IMM_MSB
|
||||
`undef QBMCU_DECINFO_ALU_OP2IMM
|
||||
`undef QBMCU_DECINFO_ALU_OP1PC_LSB
|
||||
`undef QBMCU_DECINFO_ALU_OP1PC_MSB
|
||||
`undef QBMCU_DECINFO_ALU_OP1PC
|
||||
`undef QBMCU_DECINFO_ALU_NOP_LSB
|
||||
`undef QBMCU_DECINFO_ALU_NOP_MSB
|
||||
`undef QBMCU_DECINFO_ALU_NOP
|
||||
`undef QBMCU_DECINFO_ALU_WIDTH
|
||||
|
||||
//AGU group
|
||||
`undef QBMCU_DECINFO_AGU_LOAD_LSB
|
||||
`undef QBMCU_DECINFO_AGU_LOAD_MSB
|
||||
`undef QBMCU_DECINFO_AGU_LOAD
|
||||
`undef QBMCU_DECINFO_AGU_STORE_LSB
|
||||
`undef QBMCU_DECINFO_AGU_STORE_MSB
|
||||
`undef QBMCU_DECINFO_AGU_STORE
|
||||
`undef QBMCU_DECINFO_AGU_SIZE_LSB
|
||||
`undef QBMCU_DECINFO_AGU_SIZE_MSB
|
||||
`undef QBMCU_DECINFO_AGU_SIZE
|
||||
`undef QBMCU_DECINFO_AGU_USIGN_LSB
|
||||
`undef QBMCU_DECINFO_AGU_USIGN_MSB
|
||||
`undef QBMCU_DECINFO_AGU_USIGN
|
||||
`undef QBMCU_DECINFO_AGU_OP2IMM_LSB
|
||||
`undef QBMCU_DECINFO_AGU_OP2IMM_MSB
|
||||
`undef QBMCU_DECINFO_AGU_OP2IMM
|
||||
`undef QBMCU_DECINFO_AGU_WIDTH
|
||||
|
||||
// Bxx group
|
||||
`undef QBMCU_DECINFO_BJP_JUMP_LSB
|
||||
`undef QBMCU_DECINFO_BJP_JUMP_MSB
|
||||
`undef QBMCU_DECINFO_BJP_JUMP
|
||||
`undef QBMCU_DECINFO_BJP_BPRDT_LSB
|
||||
`undef QBMCU_DECINFO_BJP_BPRDT_MSB
|
||||
`undef QBMCU_DECINFO_BJP_JALR
|
||||
`undef QBMCU_DECINFO_BJP_BEQ_LSB
|
||||
`undef QBMCU_DECINFO_BJP_BEQ_MSB
|
||||
`undef QBMCU_DECINFO_BJP_BEQ
|
||||
`undef QBMCU_DECINFO_BJP_BNE_LSB
|
||||
`undef QBMCU_DECINFO_BJP_BNE_MSB
|
||||
`undef QBMCU_DECINFO_BJP_BNE
|
||||
`undef QBMCU_DECINFO_BJP_BLT_LSB
|
||||
`undef QBMCU_DECINFO_BJP_BLT_MSB
|
||||
`undef QBMCU_DECINFO_BJP_BLT
|
||||
`undef QBMCU_DECINFO_BJP_BGT_LSB
|
||||
`undef QBMCU_DECINFO_BJP_BGT_MSB
|
||||
`undef QBMCU_DECINFO_BJP_BGT
|
||||
`undef QBMCU_DECINFO_BJP_BLTU_LSB
|
||||
`undef QBMCU_DECINFO_BJP_BLTU_MSB
|
||||
`undef QBMCU_DECINFO_BJP_BLTU
|
||||
`undef QBMCU_DECINFO_BJP_BGTU_LSB
|
||||
`undef QBMCU_DECINFO_BJP_BGTU_MSB
|
||||
`undef QBMCU_DECINFO_BJP_BGTU
|
||||
`undef QBMCU_DECINFO_BJP_BXX_LSB
|
||||
`undef QBMCU_DECINFO_BJP_BXX_MSB
|
||||
`undef QBMCU_DECINFO_BJP_BXX
|
||||
`undef QBMCU_DECINFO_BJP_WIDTH
|
||||
|
||||
|
||||
// EXT group
|
||||
`undef QBMCU_DECINFO_EXT_WAIT_LSB
|
||||
`undef QBMCU_DECINFO_EXT_WAIT_MSB
|
||||
`undef QBMCU_DECINFO_EXT_WAIT
|
||||
`undef QBMCU_DECINFO_EXT_SEND_LSB
|
||||
`undef QBMCU_DECINFO_EXT_SEND_MSB
|
||||
`undef QBMCU_DECINFO_EXT_SEND
|
||||
`undef QBMCU_DECINFO_EXT_SENDC_LSB
|
||||
`undef QBMCU_DECINFO_EXT_SENDC_MSB
|
||||
`undef QBMCU_DECINFO_EXT_SENDC
|
||||
`undef QBMCU_DECINFO_EXT_EXIT_LSB
|
||||
`undef QBMCU_DECINFO_EXT_EXIT_MSB
|
||||
`undef QBMCU_DECINFO_EXT_EXIT
|
||||
`undef QBMCU_DECINFO_EXT_EXITI_LSB
|
||||
`undef QBMCU_DECINFO_EXT_EXITI_MSB
|
||||
`undef QBMCU_DECINFO_EXT_EXITI
|
||||
`undef QBMCU_DECINFO_EXT_OP2IMM_LSB
|
||||
`undef QBMCU_DECINFO_EXT_OP2IMM_MSB
|
||||
`undef QBMCU_DECINFO_EXT_OP2IMM
|
||||
`undef QBMCU_DECINFO_EXT_WIDTH
|
||||
|
||||
// Choose the longest group as the final DEC info width
|
||||
`undef QBMCU_DECINFO_WIDTH
|
||||
|
||||
|
|
@ -0,0 +1,89 @@
|
|||
//+FHDR--------------------------------------------------------------------------------------------------------
|
||||
// Company:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// File Name : qbmcu_exu_alu_ext.v
|
||||
// Department :
|
||||
// Author : PWY
|
||||
// Author's Tel :
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Relese History
|
||||
// Version Date Author Description
|
||||
// 0.1 2024-03-13 PWY The Write-Back module to arbitrate the write-back request to regfile
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Keywords :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Parameter
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Purpose :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Target Device:
|
||||
// Tool versions:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Reuse Issues
|
||||
// Reset Strategy:
|
||||
// Clock Domains:
|
||||
// Critical Timing:
|
||||
// Asynchronous I/F:
|
||||
// Synthesizable (y/n):
|
||||
// Other:
|
||||
//-FHDR--------------------------------------------------------------------------------------------------------
|
||||
|
||||
`include "qbmcu_defines.v"
|
||||
|
||||
module qbmcu_wbck(
|
||||
//system port
|
||||
input clk
|
||||
,input rst_n
|
||||
//The enable signal from the master control state machine
|
||||
,input wbck_i_active
|
||||
//Write-back target register index from the decoding module
|
||||
,input [`QBMCU_RFIDX_WIDTH-1 :0] wbck_i_rdidx
|
||||
//Write enable for the write-back target register from the decoding module
|
||||
,input wbck_i_rdwen
|
||||
//////////////////////////////////////////////////////////////
|
||||
// The BJP Write-Back Interface
|
||||
,input [`QBMCU_XLEN-1 :0] bjp_i_wbck_wdat
|
||||
,input bjp_i_wbck_valid
|
||||
// The AGU Write-Back Interface
|
||||
,input [`QBMCU_XLEN-1 :0] agu_i_wbck_wdat
|
||||
,input agu_i_wbck_valid
|
||||
// The ALU Write-Back Interface
|
||||
,input [`QBMCU_XLEN-1 :0] alu_i_wbck_wdat
|
||||
,input alu_i_wbck_valid
|
||||
// The Ext Write-Back Interface
|
||||
,input [`QBMCU_XLEN-1 :0] ext_i_wbck_wdat
|
||||
,input ext_i_wbck_valid
|
||||
|
||||
//////////////////////////////////////////////////////////////
|
||||
// The Final arbitrated Write-Back Interface to Regfile
|
||||
,output wbck_o_ena
|
||||
,output [`QBMCU_XLEN-1 :0] wbck_o_wdat
|
||||
,output [`QBMCU_RFIDX_WIDTH-1 :0] wbck_o_rdidx
|
||||
|
||||
);
|
||||
|
||||
//Write-back data multiplexer
|
||||
wire [`QBMCU_XLEN-1:0] wbck_i_wdat = {`QBMCU_XLEN{bjp_i_wbck_valid}} & bjp_i_wbck_wdat
|
||||
| {`QBMCU_XLEN{agu_i_wbck_valid}} & agu_i_wbck_wdat
|
||||
| {`QBMCU_XLEN{alu_i_wbck_valid}} & alu_i_wbck_wdat
|
||||
| {`QBMCU_XLEN{ext_i_wbck_valid}} & ext_i_wbck_wdat;
|
||||
|
||||
|
||||
//Assigning Write-back module output signal values
|
||||
wire wbck_o_ena_w = wbck_i_rdwen & wbck_i_active;
|
||||
|
||||
sirv_gnrl_dffr #(1)wbck_o_ena_dffr (wbck_o_ena_w, wbck_o_ena, clk, rst_n);
|
||||
|
||||
assign wbck_o_wdat = wbck_i_wdat[`QBMCU_XLEN-1:0];
|
||||
//assign wbck_o_rdidx = wbck_i_rdidx;
|
||||
|
||||
sirv_gnrl_dfflr #(`QBMCU_RFIDX_WIDTH)wbck_o_rdidx_dfflr (wbck_i_active, wbck_i_rdidx, wbck_o_rdidx, clk, rst_n);
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
`include "qbmcu_undefines.v"
|
||||
|
||||
|
|
@ -0,0 +1,64 @@
|
|||
`timescale 1ns/1ps
|
||||
//====================================================
|
||||
//Author : pwy
|
||||
//Date : 2024-04-04
|
||||
//Des : async set & sync release management unit
|
||||
//====================================================
|
||||
module rst_gen_unit(
|
||||
//ext hardware async reset -- low active
|
||||
input async_rstn_i
|
||||
//power-on reset -- low active
|
||||
,input por_rstn_i
|
||||
//sys soft reset -- low active
|
||||
,input sys_soft_resetn_i
|
||||
//ch0 soft reset -- low active
|
||||
,input ch0_soft_rstn_i
|
||||
//ch1 soft reset -- low active
|
||||
,input ch1_soft_rstn_i
|
||||
//ch2 soft reset -- low active
|
||||
,input ch2_soft_rstn_i
|
||||
//ch3 soft reset -- low active
|
||||
,input ch3_soft_rstn_i
|
||||
//clock
|
||||
,input clk
|
||||
//reset output -- low active
|
||||
,output ch0_rstn_o
|
||||
,output ch1_rstn_o
|
||||
,output ch2_rstn_o
|
||||
,output ch3_rstn_o
|
||||
//Phase-locked loop reset -- low active
|
||||
,output pll_rstn_o
|
||||
);
|
||||
|
||||
//ch0 reset --> async_rstn_i & por_rstn_i & sys_soft_resetn_i & ch0_soft_rstn_i
|
||||
rst_sync ch0_rstn_sync (
|
||||
.clk_d ( clk )
|
||||
,.async_rstn ( async_rstn_i & por_rstn_i & sys_soft_resetn_i & ch0_soft_rstn_i )
|
||||
,.sync_rstn ( ch0_rstn_o )
|
||||
);
|
||||
|
||||
//ch1 reset --> async_rstn_i & por_rstn_i & sys_soft_resetn_i & ch1_soft_rstn_i
|
||||
rst_sync ch1_rstn_sync (
|
||||
.clk_d ( clk )
|
||||
,.async_rstn ( async_rstn_i & por_rstn_i & sys_soft_resetn_i & ch1_soft_rstn_i )
|
||||
,.sync_rstn ( ch1_rstn_o )
|
||||
);
|
||||
|
||||
//ch2 reset --> async_rstn_i & por_rstn_i & sys_soft_resetn_i & ch2_soft_rstn_i
|
||||
rst_sync ch2_rstn_sync (
|
||||
.clk_d ( clk )
|
||||
,.async_rstn ( async_rstn_i & por_rstn_i & sys_soft_resetn_i & ch2_soft_rstn_i )
|
||||
,.sync_rstn ( ch2_rstn_o )
|
||||
);
|
||||
|
||||
//ch3 reset --> async_rstn_i & por_rstn_i & sys_soft_resetn_i & ch3_soft_rstn_i
|
||||
rst_sync ch3_rstn_sync (
|
||||
.clk_d ( clk )
|
||||
,.async_rstn ( async_rstn_i & por_rstn_i & sys_soft_resetn_i & ch3_soft_rstn_i )
|
||||
,.sync_rstn ( ch3_rstn_o )
|
||||
);
|
||||
|
||||
//Phase-locked loop reset -- low active
|
||||
assign pll_rstn_o = async_rstn_i & por_rstn_i;
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,29 @@
|
|||
`timescale 1ns/1ps
|
||||
//====================================================
|
||||
//Author : pwy
|
||||
//Date : 2020-06-24
|
||||
//Des : async set & sync release
|
||||
//====================================================
|
||||
module rst_sync(
|
||||
input clk_d ,
|
||||
input async_rstn ,
|
||||
output sync_rstn
|
||||
);
|
||||
|
||||
reg rstn_s1;
|
||||
reg rstn_s2;
|
||||
|
||||
always@(posedge clk_d or negedge async_rstn)begin
|
||||
if(!async_rstn)begin
|
||||
rstn_s1 <=1'b0;
|
||||
rstn_s2 <=1'b0;
|
||||
end
|
||||
else begin
|
||||
rstn_s1 <=1'b1;
|
||||
rstn_s2 <=rstn_s1;
|
||||
end
|
||||
end
|
||||
|
||||
assign sync_rstn = rstn_s2;
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,91 @@
|
|||
//+FHDR--------------------------------------------------------------------------------------------------------
|
||||
// Company:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// File Name : spi_bus_decoder.v
|
||||
// Department :
|
||||
// Author : PWY
|
||||
// Author's Tel :
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Relese History
|
||||
// Version Date Author Description
|
||||
// 0.1 2024-03-13 PWY Serial Peripheral Interface BUS Decoder
|
||||
// 0.2 2024-06-15 PWY The slave interface address will be reduced from 25 bits to 20 bits.
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Keywords :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Parameter
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Purpose :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Target Device:
|
||||
// Tool versions:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Reuse Issues
|
||||
// Reset Strategy:
|
||||
// Clock Domains:
|
||||
// Critical Timing:
|
||||
// Asynchronous I/F:
|
||||
// Synthesizable (y/n):
|
||||
// Other:
|
||||
//-FHDR--------------------------------------------------------------------------------------------------------
|
||||
|
||||
module spi_bus_decoder #(
|
||||
parameter SLVNUM = 32
|
||||
,parameter SPIBUS_CMD_REG = 1
|
||||
,parameter SPIBUS_OUT_REG = 1
|
||||
)(
|
||||
input clk
|
||||
,input rst_n
|
||||
,sram_if.slave mst
|
||||
,sram_if.master slv [SLVNUM-1:0] //s and m exchange
|
||||
);
|
||||
|
||||
|
||||
generate
|
||||
genvar i;
|
||||
logic [SLVNUM-1:0] cs_slv;
|
||||
logic [31 :0] dtemp[SLVNUM-1:0];
|
||||
|
||||
for(i=0;i<SLVNUM;i=i+1) begin: MAIN
|
||||
//generating device chip select signal
|
||||
//the largest 5bit addr is used to select among 32 SRAM
|
||||
assign cs_slv[i] = (mst.addr[24:20] == i );
|
||||
//generating device read/write signal
|
||||
if(SPIBUS_CMD_REG == 1) begin :CMD_REG
|
||||
sirv_gnrl_dffr #(20) rwaddr_dffr ({20{cs_slv[i]}} & mst.addr[19:0] ,slv[i].addr, clk, rst_n);
|
||||
sirv_gnrl_dffr #(32) wrdata_dffr ({32{cs_slv[i]}} & mst.din ,slv[i].din, clk, rst_n);
|
||||
sirv_gnrl_dffr #(1) wren_dffr (cs_slv[i] & mst.wren ,slv[i].wren, clk, rst_n);
|
||||
sirv_gnrl_dffr #(1) reen_dffr (cs_slv[i] & mst.rden ,slv[i].rden, clk, rst_n);
|
||||
end
|
||||
else begin :CMD_DONT_REG
|
||||
assign slv[i].addr = {20{cs_slv[i]}} & mst.addr[19:0];
|
||||
assign slv[i].wren = cs_slv[i] & mst.wren;
|
||||
assign slv[i].rden = cs_slv[i] & mst.rden;
|
||||
assign slv[i].din = {32{cs_slv[i]}} & mst.din;
|
||||
end
|
||||
|
||||
assign slv[i].wben = {4{cs_slv[i]}} & mst.wben;
|
||||
|
||||
if(i==0) begin: DETMP0
|
||||
assign dtemp[i] = (cs_slv[i]) ? slv[i].dout : 32'b0;
|
||||
end
|
||||
else begin: DETMP1_32
|
||||
assign dtemp[i] = (cs_slv[i]) ? slv[i].dout : dtemp[i-1];
|
||||
end
|
||||
end
|
||||
//read data from register
|
||||
if(SPIBUS_OUT_REG == 1) begin :OUT_REG
|
||||
wire [3:0] rden_dly;
|
||||
sirv_gnrl_dffr #(4) rddata_dffr ({rden_dly[2:0],mst.rden}, rden_dly[3:0], clk, rst_n);
|
||||
sirv_gnrl_dfflr #(32) rddata_dfflr (rden_dly[3],dtemp[SLVNUM-1], mst.dout, clk, rst_n);
|
||||
end
|
||||
else begin : OUT_DONT_REG
|
||||
assign mst.dout = dtemp[SLVNUM-1];
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
|
||||
|
|
@ -0,0 +1,233 @@
|
|||
//+FHDR--------------------------------------------------------------------------------------------------------
|
||||
// Company:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// File Name : spi_pll.v
|
||||
// Department :
|
||||
// Author : PWY
|
||||
// Author's Tel :
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Relese History
|
||||
// Version Date Author Description
|
||||
// 0.1 2024-04-10 PWY Dedicated SPI interface for phase-locked loops (PLLs)
|
||||
// 0.2 2024-04-11 PWY Alter frame format
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Keywords :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Parameter
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Purpose :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Target Device:
|
||||
// Tool versions:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Reuse Issues
|
||||
// Reset Strategy:
|
||||
// Clock Domains:
|
||||
// Critical Timing:
|
||||
// Asynchronous I/F:
|
||||
// Synthesizable (y/n):
|
||||
// Other:
|
||||
//-FHDR--------------------------------------------------------------------------------------------------------
|
||||
|
||||
//-----------------------------Spi Frame-------------------------------------------------------------------------------------
|
||||
////MSB------------->>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>.....................................................>>>>>>>>------->LSB
|
||||
///|<-----------MSB 32 bits-------------------------->||<--Second 32-bit---->||<-------x 32-bit---->||<-------n 32-bit---->|
|
||||
// +-----++----------------------++------------++-----++---------------------++---------------------++---------------------+
|
||||
// | 31 || 30:6 || 5:1 || 0 || 31:0 || ...... || 31:0 |
|
||||
// +-----++----------------------++------------++-----++---------------------++---------------------++---------------------+
|
||||
// +-----++----------------------++------------++-----++---------------------++---------------------++---------------------+
|
||||
// | wnr || addr[24:0] || CHIPID ||resv || data[31:0] || ...... || data[31:0] |
|
||||
// +-----++----------------------++------------++-----++---------------------++---------------------++---------------------+
|
||||
//-----------------------------Spi Frame-------------------------------------------------------------------------------------
|
||||
`timescale 1ns/1ps
|
||||
|
||||
module spi_pll (
|
||||
//reset active low
|
||||
input rst_n
|
||||
//cfg ID
|
||||
,input [4 :0] cfgid //ID number for the entire chip
|
||||
//SPI interface
|
||||
,input csn
|
||||
,input sclk
|
||||
,input mosi
|
||||
,output miso
|
||||
,output oen
|
||||
//SPI Select signal
|
||||
,output sel
|
||||
//regfile interface
|
||||
,output [31 :0] wrdata
|
||||
,output wren
|
||||
,output [7 :0] rwaddr
|
||||
,output rden
|
||||
,input [31 :0] rddata
|
||||
);
|
||||
|
||||
wire sel_w ;
|
||||
wire wnr ;
|
||||
wire [4 :0] addr_m5b ;
|
||||
wire [7 :0] addr_l8b ;
|
||||
wire [4 :0] chipid ;
|
||||
|
||||
wire data_valid ;
|
||||
//wire [31:0] rddata ;//////////////////////////////////////
|
||||
//reg rden_reg ;//////////////////////////////////////
|
||||
|
||||
//spi_rstn
|
||||
wire spi_rstn = rst_n & (~csn);
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////
|
||||
//bit count
|
||||
//////////////////////////////////////////////////////////////////////////
|
||||
wire [4:0] bit_cnt;
|
||||
//add_cnt
|
||||
wire add_cnt = ~csn;
|
||||
//end_cnt
|
||||
wire end_cnt = add_cnt & (bit_cnt == 5'd31);
|
||||
|
||||
|
||||
|
||||
wire [4:0] cnt_n = end_cnt ? 5'd0 :
|
||||
add_cnt ? bit_cnt + 5'b1 :
|
||||
bit_cnt ;
|
||||
|
||||
|
||||
sirv_gnrl_dffr #(5) bit_cnt_dffr (cnt_n, bit_cnt, sclk, spi_rstn);
|
||||
|
||||
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
//Determine whether the current input is an SPI command or data
|
||||
//Detect the falling edge on the most significant bit of the counter.
|
||||
//If a falling edge occurs, it indicates that the SPI frame has
|
||||
//entered the data transmission phase.
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
wire bit_cnt_r;
|
||||
wire bit_cnt_falling = bit_cnt_r & ~bit_cnt[4];
|
||||
|
||||
sirv_gnrl_dffr #(1) bit_cnt_r_dffr (bit_cnt[4], bit_cnt_r, sclk, spi_rstn);
|
||||
|
||||
|
||||
//cmd_or_data:"High" represents data, "low" represents commands
|
||||
wire cmd_or_data;
|
||||
|
||||
sirv_gnrl_dfflr #(1) cmd_or_data_dfflr (bit_cnt_falling, 1'b1, cmd_or_data, sclk, spi_rstn);
|
||||
|
||||
wire second_falling;
|
||||
|
||||
sirv_gnrl_dfflr #(1) second_falling_dfflr (bit_cnt_falling & cmd_or_data, 1'b1, second_falling, sclk, spi_rstn);
|
||||
|
||||
///////////////////////////////////////////////////////////////////////
|
||||
//SPI data sample (Load mosi data)
|
||||
///////////////////////////////////////////////////////////////////////
|
||||
|
||||
generate
|
||||
genvar i;
|
||||
wire [31:0] recv_vld ;
|
||||
wire [31:0] mosi_reg ;
|
||||
for(i=0;i<32;i=i+1) begin: spi_pll_recv
|
||||
assign recv_vld[i] = add_cnt & (bit_cnt == i );
|
||||
sirv_gnrl_dfflr #(1) spi_din_dfflr (recv_vld[i], mosi, mosi_reg[31-i], sclk, spi_rstn);
|
||||
end
|
||||
endgenerate
|
||||
|
||||
//addr valid
|
||||
wire addr_vaild = ~cmd_or_data & add_cnt & (bit_cnt == 5'd26);
|
||||
|
||||
//CMD Update
|
||||
sirv_gnrl_dfflr #(1) wnr_dfflr (addr_vaild, mosi_reg[31], wnr, sclk, spi_rstn);
|
||||
|
||||
//addr_m5b Update
|
||||
sirv_gnrl_dfflr #(5) addr_m5b_dfflr (addr_vaild, mosi_reg[30:26], addr_m5b, sclk, spi_rstn);
|
||||
|
||||
//addr_l8b Update
|
||||
sirv_gnrl_dfflr #(8) addr_l8b_dfflr (addr_vaild, mosi_reg[13:6], addr_l8b, sclk, spi_rstn);
|
||||
|
||||
//chipid Valid
|
||||
wire chipid_vld = ~cmd_or_data & add_cnt & (bit_cnt == 5'd31);
|
||||
//chipid Update
|
||||
sirv_gnrl_dfflr #(5) chipid_dfflr (chipid_vld, mosi_reg[5:1], chipid, sclk, spi_rstn);
|
||||
|
||||
//sel_w
|
||||
assign sel_w = (addr_m5b == 5'b11111) & (chipid == cfgid);
|
||||
|
||||
|
||||
|
||||
//recv data valid
|
||||
assign data_valid = cmd_or_data & (bit_cnt == 5'd31);
|
||||
//assign data_valid = cmd_or_data & (bit_cnt == 5'd31);///////20240514
|
||||
//wren
|
||||
assign wren = data_valid & sel_w & ~wnr;
|
||||
|
||||
//rden
|
||||
//assign rden = add_cnt & (bit_cnt == 5'd30);/////////////////////////
|
||||
//assign rden = add_cnt & (bit_cnt == 5'd30) & sel_w;/////////////////////////20240514
|
||||
assign rden = add_cnt & (bit_cnt == 5'd30) & wnr;/////////////////////////20240604
|
||||
|
||||
wire rddata_update;
|
||||
sirv_gnrl_dffr #(1) rddata_update_dffr (rden, rddata_update, sclk, spi_rstn);
|
||||
|
||||
//wrdata
|
||||
assign wrdata = {mosi_reg[31:1],mosi};
|
||||
|
||||
///////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
//Address generation for read and write operations
|
||||
//The address to be used for updating in the next
|
||||
//27 clock cycles in the read-write state
|
||||
///////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
wire addr_update = ((wnr & cmd_or_data) | second_falling) & add_cnt & (bit_cnt == 5'd29);
|
||||
//wire addr_update = cmd_or_data & add_cnt & (bit_cnt == 5'd27);
|
||||
|
||||
wire [7:0] addr_c;
|
||||
|
||||
wire [7:0] addr_n = ~cmd_or_data ? addr_l8b :
|
||||
addr_update ? addr_c + 8'd4 :
|
||||
addr_c ;
|
||||
|
||||
sirv_gnrl_dffr #(8) addr_c_dffr (addr_n, addr_c, sclk, spi_rstn);
|
||||
|
||||
assign rwaddr = addr_c;
|
||||
|
||||
//sel
|
||||
assign sel = sel_w;
|
||||
|
||||
//oen
|
||||
//assign oen = ~(sel_w & wnr & ~csn);
|
||||
wire oen_w = ~(sel_w & wnr & ~csn);
|
||||
sirv_gnrl_dffrs #(1) oen_dffrs (oen_w, oen, sclk, spi_rstn);
|
||||
//data output
|
||||
wire[31:0] miso_reg;
|
||||
wire[31:0] miso_wire;
|
||||
sirv_gnrl_dfflr #(32) miso_reg_dfflr (rddata_update, rddata, miso_reg, sclk, spi_rstn);
|
||||
assign miso_wire = miso_reg;
|
||||
|
||||
///////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
//SPI send data
|
||||
///////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
generate
|
||||
genvar j;
|
||||
wire [31:0] send_vld ;
|
||||
wire [31:0] dtemp ;
|
||||
for(j=0;j<32;j=j+1) begin: spi_pll_send
|
||||
//assign send_vld[j] = (bit_cnt == ((j==31) ? 0 : (j+1)) );
|
||||
assign send_vld[j] = (bit_cnt == j );
|
||||
if(j==0) begin: dtemp0
|
||||
assign dtemp[j] = (send_vld[j]) ? miso_wire[31-j] : 1'b0;
|
||||
end
|
||||
else begin: dtemp1_32
|
||||
assign dtemp[j] = (send_vld[j]) ? miso_wire[31-j] : dtemp[j-1];
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
assign miso = dtemp[31];
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,106 @@
|
|||
//+FHDR--------------------------------------------------------------------------------------------------------
|
||||
// Company:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// File Name : spi_top.v
|
||||
// Department :
|
||||
// Author : pwy
|
||||
// Author's Tel :
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Relese History
|
||||
// Version Date Author Description
|
||||
// 1.2 2024-04-02 pwy Integrate a digital module and two SPI modules with PLL
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Keywords :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Parameter
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Purpose :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Target Device:
|
||||
// Tool versions:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Reuse Issues
|
||||
// Reset Strategy:
|
||||
// Clock Domains:
|
||||
// Critical Timing:
|
||||
// Asynchronous I/F:
|
||||
// Synthesizable (y/n):
|
||||
// Other:
|
||||
//-FHDR--------------------------------------------------------------------------------------------------------
|
||||
|
||||
module spi_slave (
|
||||
//system port
|
||||
input clk // System Main Clock
|
||||
,input rst_n // Spi Reset active low
|
||||
//spi port
|
||||
,input sclk // Spi Clock
|
||||
,input csn // Spi Chip Select active low
|
||||
,input mosi // Spi Mosi
|
||||
,input [4 :0] cfgid
|
||||
,output miso // Spi Miso
|
||||
,output oen // Spi Miso output enable
|
||||
//connect pll
|
||||
,output [31 :0] pll_wrdata
|
||||
,output pll_wren
|
||||
,output [7 :0] pll_rwaddr
|
||||
,output pll_rden
|
||||
,input [31 :0] pll_rddata
|
||||
//connect system
|
||||
,output [31 :0] sys_wrdata
|
||||
,output sys_wren
|
||||
,output [24 :0] sys_rwaddr
|
||||
,output sys_rden
|
||||
,input [31 :0] sys_rddata
|
||||
);
|
||||
|
||||
////////////////////////////////////////////////////////////////
|
||||
// pll spi
|
||||
////////////////////////////////////////////////////////////////
|
||||
wire pll_miso ;
|
||||
wire pll_oen ;
|
||||
wire pll_sel ;
|
||||
|
||||
spi_pll U_spi_pll (
|
||||
.rst_n ( rst_n )
|
||||
,.cfgid ( cfgid )
|
||||
,.csn ( csn )
|
||||
,.sclk ( sclk )
|
||||
,.mosi ( mosi )
|
||||
,.miso ( pll_miso )
|
||||
,.oen ( pll_oen )
|
||||
,.sel ( pll_sel )
|
||||
,.wrdata ( pll_wrdata )
|
||||
,.wren ( pll_wren )
|
||||
,.rwaddr ( pll_rwaddr )
|
||||
,.rden ( pll_rden )
|
||||
,.rddata ( pll_rddata )
|
||||
);
|
||||
|
||||
////////////////////////////////////////////////////////////////
|
||||
//sys pll
|
||||
////////////////////////////////////////////////////////////////
|
||||
wire sys_miso ;
|
||||
wire sys_oen ;
|
||||
spi_sys U_spi_sys (
|
||||
.clk ( clk )
|
||||
,.rst_n ( rst_n )
|
||||
,.cfgid ( cfgid )
|
||||
,.sclk ( sclk )
|
||||
,.csn ( csn )
|
||||
,.mosi ( mosi )
|
||||
,.miso ( sys_miso )
|
||||
,.oen ( sys_oen )
|
||||
,.wrdata ( sys_wrdata )
|
||||
,.addr ( sys_rwaddr )
|
||||
,.wren ( sys_wren )
|
||||
,.rden ( sys_rden )
|
||||
,.rddata ( sys_rddata )
|
||||
);
|
||||
|
||||
assign miso = pll_sel ? pll_miso : sys_miso ;
|
||||
assign oen = pll_sel ? pll_oen : sys_oen ;
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,291 @@
|
|||
//+FHDR--------------------------------------------------------------------------------------------------------
|
||||
// Company:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// File Name : spi_sys.v
|
||||
// Department :
|
||||
// Author : PWY
|
||||
// Author's Tel :
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Relese History
|
||||
// Version Date Author Description
|
||||
// 0.1 2024-04-13 PWY SPI BUS for System
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Keywords :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Parameter
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Purpose :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Target Device:
|
||||
// Tool versions:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Reuse Issues
|
||||
// Reset Strategy:
|
||||
// Clock Domains:
|
||||
// Critical Timing:
|
||||
// Asynchronous I/F:
|
||||
// Synthesizable (y/n):
|
||||
// Other:
|
||||
//-FHDR--------------------------------------------------------------------------------------------------------
|
||||
|
||||
//-----------------------------Spi Frame-------------------------------------------------------------------------------------
|
||||
////MSB------------->>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>..............................................>>>>>>>>------->LSB
|
||||
///|<-----------MSB 32 bits------------------->||<---------Second 32-bit---->||<-------x 32-bit---->||<-------n 32-bit---->|
|
||||
// +-----++----------------------++------------++-----++---------------------++---------------------++---------------------+
|
||||
// | 31 || 30:6 || 5:1 || 0 || 31:0 || ...... || 31:0 |
|
||||
// +-----++----------------------++------------++-----++---------------------++---------------------++---------------------+
|
||||
// +-----++----------------------++------------++-----++---------------------++---------------------++---------------------+
|
||||
// | wnr || addr[24:0] || CHIPID ||resv || data[31:0] || ...... || data[31:0] |
|
||||
// +-----++----------------------++------------++-----++---------------------++---------------------++---------------------+
|
||||
//-----------------------------Spi Frame-------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
module spi_sys (
|
||||
//system port
|
||||
input clk // System Main Clock
|
||||
,input rst_n // Spi Reset active low
|
||||
//cfg ID
|
||||
,input [4 :0] cfgid //ID number for the entire chip
|
||||
//spi port
|
||||
,input sclk // Spi Clock
|
||||
,input csn // Spi Chip Select active low
|
||||
,input mosi // Spi Mosi
|
||||
,output miso // Spi Miso
|
||||
,output oen // Spi Miso output enable
|
||||
|
||||
,output [31:0] wrdata //write data to sram
|
||||
,output [24:0] addr //sram address
|
||||
,output wren //write enable sram
|
||||
,output rden //rden enable sram
|
||||
,input [31:0] rddata //read data from sram
|
||||
|
||||
);
|
||||
|
||||
localparam IDLE = 2'b00,
|
||||
RECVCMD = 2'b01,
|
||||
WRITE = 2'b10,
|
||||
READ = 2'b11;
|
||||
//-----------------------------------------------------------------------
|
||||
//SPI module reset processing
|
||||
//-----------------------------------------------------------------------
|
||||
//spi_rstn
|
||||
//wire spi_rstn;
|
||||
//assign spi_rstn = rst_n & (~csn);
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////
|
||||
//capture the sck
|
||||
//////////////////////////////////////////////////////////////////////////
|
||||
wire [2:0] sclk_reg;
|
||||
//sync sclk to the main clock using a 3-bits shift register
|
||||
sirv_gnrl_dffrs #(3) sclk_reg_dffrs ({sclk_reg[1:0],sclk}, sclk_reg, clk, rst_n);
|
||||
|
||||
//sclk's rising edges
|
||||
wire sclk_p = (sclk_reg[2:1] == 2'b01);
|
||||
|
||||
//sclk's falling edges
|
||||
//assign sclk_n = (sclk_reg[2:1] == 2'b10);
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////
|
||||
//capture the csn
|
||||
//////////////////////////////////////////////////////////////////////////
|
||||
wire [2:0] csn_reg;
|
||||
//sync csn to the main clock using a 2-bits shift register
|
||||
|
||||
sirv_gnrl_dffrs #(3) csn_reg_dffrs ({csn_reg[1:0],csn}, csn_reg, clk, rst_n);
|
||||
// csn is active low
|
||||
wire csn_active = ~csn_reg[1];
|
||||
|
||||
//csn's rising edges
|
||||
wire csn_p = (csn_reg[2:1] == 2'b01);
|
||||
|
||||
//csn's falling edges
|
||||
wire csn_n = (csn_reg[2:1] == 2'b10);
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////
|
||||
//capture the mosi
|
||||
//////////////////////////////////////////////////////////////////////////
|
||||
wire [1:0] mosi_reg;
|
||||
//sync mosi to the main clock using a 2-bits shift register
|
||||
|
||||
sirv_gnrl_dffr #(2) mosi_reg_dffr ({mosi_reg[0],mosi}, mosi_reg, clk, rst_n);
|
||||
//mosi_data
|
||||
wire mosi_data = mosi_reg[1];
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////
|
||||
//cnt
|
||||
//////////////////////////////////////////////////////////////////////////
|
||||
wire [4:0] cnt_c;
|
||||
//add_cnt
|
||||
assign add_cnt = sclk_p && csn_active;
|
||||
//end_cnt
|
||||
assign end_cnt = (add_cnt && (cnt_c == 5'd31)) | csn_p;
|
||||
|
||||
wire [4:0] cnt_n = end_cnt ? 5'h0 :
|
||||
add_cnt ? cnt_c + 5'b1 :
|
||||
cnt_c ;
|
||||
|
||||
|
||||
sirv_gnrl_dffr #(5) cnt_c_dffr (cnt_n, cnt_c, clk, rst_n);
|
||||
|
||||
|
||||
///////////////////////////////////////////////////////////////////////
|
||||
//SPI data sample
|
||||
///////////////////////////////////////////////////////////////////////
|
||||
|
||||
generate
|
||||
genvar i;
|
||||
wire [31:0] recv_vld ;
|
||||
wire [31:0] spi_din ;
|
||||
for(i=0;i<32;i=i+1) begin: spi_sys_recv
|
||||
assign recv_vld[i] = add_cnt & (cnt_c == i );
|
||||
sirv_gnrl_dfflr #(1) spi_din_dfflr (recv_vld[i], mosi_data, spi_din[31-i], clk, rst_n);
|
||||
end
|
||||
endgenerate
|
||||
|
||||
|
||||
wire [1:0] state_c;
|
||||
wire [1:0] state_n;
|
||||
|
||||
|
||||
///////////////////////////////////////////////////////////////////////
|
||||
//init_addr capture
|
||||
///////////////////////////////////////////////////////////////////////
|
||||
wire [24:0] initaddr;
|
||||
wire initaddr_vld = (state_c == RECVCMD ) & add_cnt && (cnt_c == 5'd26);
|
||||
wire [1:0] initaddr_vld_r;
|
||||
sirv_gnrl_dffr #(2) initaddr_vld_r_dffr ({initaddr_vld_r[0],initaddr_vld}, initaddr_vld_r, clk, rst_n);
|
||||
|
||||
sirv_gnrl_dfflr #(25) initaddr_dfflr (initaddr_vld_r[0], spi_din[30:6], initaddr, clk, rst_n);
|
||||
|
||||
///////////////////////////////////////////////////////////////////////
|
||||
//CMD capture
|
||||
///////////////////////////////////////////////////////////////////////
|
||||
wire cmd ;
|
||||
sirv_gnrl_dfflr #(1) cmd_dfflr ( initaddr_vld_r[0], spi_din[31], cmd, clk, rst_n);
|
||||
|
||||
///////////////////////////////////////////////////////////////////////
|
||||
//CHIPID capture
|
||||
///////////////////////////////////////////////////////////////////////
|
||||
wire [4:0] chipid;
|
||||
wire [1:0] chipid_vld_r;
|
||||
wire chipid_vld = (state_c == RECVCMD ) & add_cnt & (cnt_c == 5'd30);
|
||||
//register cmd_vld to align it with cmd
|
||||
sirv_gnrl_dffr #(2) chipid_vld_r_dffr ({chipid_vld_r[0],chipid_vld}, chipid_vld_r, clk, rst_n);
|
||||
|
||||
sirv_gnrl_dfflr #(5) chipid_dfflr (chipid_vld_r[0], spi_din[5:1], chipid, clk, rst_n);
|
||||
|
||||
///////////////////////////////////////////////////////////////////////
|
||||
//ID matching determination
|
||||
///////////////////////////////////////////////////////////////////////
|
||||
wire chipid_match = (chipid == cfgid);
|
||||
wire chipid_dismatch = (chipid != cfgid);
|
||||
|
||||
|
||||
|
||||
///////////////////////////////////////////////////////////////////////
|
||||
//SPI Module State Machine
|
||||
///////////////////////////////////////////////////////////////////////
|
||||
|
||||
//Generating jump conditions for state machines
|
||||
wire ilde2recvcmd = (state_c == IDLE ) && csn_active && csn_n ;
|
||||
wire recvcmd2ilde = (state_c == RECVCMD ) && chipid_dismatch & end_cnt;
|
||||
wire recvcmd2write = (state_c == RECVCMD ) && chipid_match && ~cmd & end_cnt;
|
||||
wire recvcmd2read = (state_c == RECVCMD ) && chipid_match && cmd & end_cnt;
|
||||
wire write2idle = (state_c == WRITE ) && csn_p;
|
||||
wire read2idle = (state_c == READ ) && csn_p;
|
||||
|
||||
//The first section of the state machine
|
||||
//state_c
|
||||
sirv_gnrl_dffr #(2) state_c_dffr (state_n, state_c, clk, rst_n);
|
||||
|
||||
//state_n
|
||||
assign state_n = ((state_c == IDLE ) && ilde2recvcmd ) ? RECVCMD :
|
||||
((state_c == RECVCMD ) && recvcmd2ilde ) ? IDLE :
|
||||
((state_c == RECVCMD ) && recvcmd2write ) ? WRITE :
|
||||
((state_c == RECVCMD ) && recvcmd2read ) ? READ :
|
||||
((state_c == WRITE ) && write2idle ) ? IDLE :
|
||||
((state_c == READ ) && read2idle ) ? IDLE :
|
||||
state_c ;
|
||||
|
||||
|
||||
///////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
//Address generation for read and write operations
|
||||
//The address to be used for updating in the next
|
||||
//27 clock cycles in the read-write state
|
||||
///////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
wire second_falling;
|
||||
wire second_falling_w = (state_c == WRITE);
|
||||
sirv_gnrl_dfflr #(1) second_falling_dfflr (end_cnt ,second_falling_w, second_falling, clk, rst_n);
|
||||
|
||||
wire addr_update = ((state_c == READ) | ((state_c == WRITE) & second_falling)) & add_cnt & (cnt_c == 5'd27);
|
||||
wire [24:0] addr_c;
|
||||
|
||||
wire [24:0] addr_n = ilde2recvcmd ? 25'd0 :
|
||||
initaddr_vld_r[1] ? initaddr :
|
||||
addr_update ? addr_c + 25'd4 :
|
||||
addr_c ;
|
||||
|
||||
sirv_gnrl_dffr #(25) addr_c_dffr (addr_n, addr_c, clk, rst_n);
|
||||
|
||||
assign addr = addr_c;
|
||||
|
||||
///////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
//Write data and write signals generation
|
||||
///////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
wire wren_r;
|
||||
|
||||
wire wren_w = (state_c == WRITE) & add_cnt & (cnt_c == 5'd31);
|
||||
//wdata
|
||||
sirv_gnrl_dfflr #(32) wrdata_dfflr (wren_r, spi_din[31:0], wrdata, clk, rst_n);
|
||||
//wren_r
|
||||
|
||||
sirv_gnrl_dffr #(1) wren_r_dffr (wren_w, wren_r, clk, rst_n);
|
||||
|
||||
//wren
|
||||
sirv_gnrl_dffr #(1) wren_dffr (wren_r, wren, clk, rst_n);
|
||||
|
||||
///////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
//read signals generation
|
||||
///////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
wire rden_w = cmd & add_cnt & (cnt_c == 5'd28);
|
||||
sirv_gnrl_dffr #(1) rden_dffr (rden_w, rden, clk, rst_n);
|
||||
|
||||
//Read data register
|
||||
wire rddata_vld = cmd & add_cnt & (cnt_c == 5'd30);
|
||||
wire [31:0] rddata_reg;
|
||||
sirv_gnrl_dfflr #(32) rddata_reg_dfflr (rddata_vld, rddata[31:0], rddata_reg, clk, rst_n);
|
||||
|
||||
|
||||
///////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
//SPI send data update
|
||||
///////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
wire [31:0] spi_dout ;
|
||||
wire update_flag = cmd & add_cnt & (cnt_c == 5'd31);
|
||||
|
||||
wire [31:0] rddata_sr = update_flag ? rddata_reg[31:0] :
|
||||
((state_c == READ) & add_cnt) ? {spi_dout[31:0],1'b0} :
|
||||
spi_dout ;
|
||||
|
||||
sirv_gnrl_dffr #(32) spi_dout_dffr (rddata_sr, spi_dout, clk, rst_n);
|
||||
|
||||
|
||||
///////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
//SPI send data
|
||||
///////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
assign miso = spi_dout[31];
|
||||
|
||||
|
||||
|
||||
///////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
//SPI output enable
|
||||
///////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
sirv_gnrl_dffrs #(1) oen_dffr (~(state_c == READ), oen, clk, rst_n);
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,292 @@
|
|||
//+FHDR--------------------------------------------------------------------------------------------------------
|
||||
// Company:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// File Name : spi_sys.v
|
||||
// Department :
|
||||
// Author : PWY
|
||||
// Author's Tel :
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Relese History
|
||||
// Version Date Author Description
|
||||
// 0.1 2024-04-13 PWY SPI BUS for System
|
||||
// 0.2 2024-06-24 PWY {spi_dout[31:0],1'b0} -> {spi_dout[30:0],1'b0}
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Keywords :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Parameter
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Purpose :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Target Device:
|
||||
// Tool versions:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Reuse Issues
|
||||
// Reset Strategy:
|
||||
// Clock Domains:
|
||||
// Critical Timing:
|
||||
// Asynchronous I/F:
|
||||
// Synthesizable (y/n):
|
||||
// Other:
|
||||
//-FHDR--------------------------------------------------------------------------------------------------------
|
||||
|
||||
//-----------------------------Spi Frame-------------------------------------------------------------------------------------
|
||||
////MSB------------->>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>..............................................>>>>>>>>------->LSB
|
||||
///|<-----------MSB 32 bits------------------->||<---------Second 32-bit---->||<-------x 32-bit---->||<-------n 32-bit---->|
|
||||
// +-----++----------------------++------------++-----++---------------------++---------------------++---------------------+
|
||||
// | 31 || 30:6 || 5:1 || 0 || 31:0 || ...... || 31:0 |
|
||||
// +-----++----------------------++------------++-----++---------------------++---------------------++---------------------+
|
||||
// +-----++----------------------++------------++-----++---------------------++---------------------++---------------------+
|
||||
// | wnr || addr[24:0] || CHIPID ||resv || data[31:0] || ...... || data[31:0] |
|
||||
// +-----++----------------------++------------++-----++---------------------++---------------------++---------------------+
|
||||
//-----------------------------Spi Frame-------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
module spi_sys (
|
||||
//system port
|
||||
input clk // System Main Clock
|
||||
,input rst_n // Spi Reset active low
|
||||
//cfg ID
|
||||
,input [4 :0] cfgid //ID number for the entire chip
|
||||
//spi port
|
||||
,input sclk // Spi Clock
|
||||
,input csn // Spi Chip Select active low
|
||||
,input mosi // Spi Mosi
|
||||
,output miso // Spi Miso
|
||||
,output oen // Spi Miso output enable
|
||||
|
||||
,output [31:0] wrdata //write data to sram
|
||||
,output [24:0] addr //sram address
|
||||
,output wren //write enable sram
|
||||
,output rden //rden enable sram
|
||||
,input [31:0] rddata //read data from sram
|
||||
|
||||
);
|
||||
|
||||
localparam IDLE = 2'b00,
|
||||
RECVCMD = 2'b01,
|
||||
WRITE = 2'b10,
|
||||
READ = 2'b11;
|
||||
//-----------------------------------------------------------------------
|
||||
//SPI module reset processing
|
||||
//-----------------------------------------------------------------------
|
||||
//spi_rstn
|
||||
//wire spi_rstn;
|
||||
//assign spi_rstn = rst_n & (~csn);
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////
|
||||
//capture the sck
|
||||
//////////////////////////////////////////////////////////////////////////
|
||||
wire [2:0] sclk_reg;
|
||||
//sync sclk to the main clock using a 3-bits shift register
|
||||
sirv_gnrl_dffrs #(3) sclk_reg_dffrs ({sclk_reg[1:0],sclk}, sclk_reg, clk, rst_n);
|
||||
|
||||
//sclk's rising edges
|
||||
wire sclk_p = (sclk_reg[2:1] == 2'b01);
|
||||
|
||||
//sclk's falling edges
|
||||
//assign sclk_n = (sclk_reg[2:1] == 2'b10);
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////
|
||||
//capture the csn
|
||||
//////////////////////////////////////////////////////////////////////////
|
||||
wire [2:0] csn_reg;
|
||||
//sync csn to the main clock using a 2-bits shift register
|
||||
|
||||
sirv_gnrl_dffrs #(3) csn_reg_dffrs ({csn_reg[1:0],csn}, csn_reg, clk, rst_n);
|
||||
// csn is active low
|
||||
wire csn_active = ~csn_reg[1];
|
||||
|
||||
//csn's rising edges
|
||||
wire csn_p = (csn_reg[2:1] == 2'b01);
|
||||
|
||||
//csn's falling edges
|
||||
wire csn_n = (csn_reg[2:1] == 2'b10);
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////
|
||||
//capture the mosi
|
||||
//////////////////////////////////////////////////////////////////////////
|
||||
wire [1:0] mosi_reg;
|
||||
//sync mosi to the main clock using a 2-bits shift register
|
||||
|
||||
sirv_gnrl_dffr #(2) mosi_reg_dffr ({mosi_reg[0],mosi}, mosi_reg, clk, rst_n);
|
||||
//mosi_data
|
||||
wire mosi_data = mosi_reg[1];
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////
|
||||
//cnt
|
||||
//////////////////////////////////////////////////////////////////////////
|
||||
wire [4:0] cnt_c;
|
||||
//add_cnt
|
||||
assign add_cnt = sclk_p && csn_active;
|
||||
//end_cnt
|
||||
assign end_cnt = (add_cnt && (cnt_c == 5'd31)) | csn_p;
|
||||
|
||||
wire [4:0] cnt_n = end_cnt ? 5'h0 :
|
||||
add_cnt ? cnt_c + 5'b1 :
|
||||
cnt_c ;
|
||||
|
||||
|
||||
sirv_gnrl_dffr #(5) cnt_c_dffr (cnt_n, cnt_c, clk, rst_n);
|
||||
|
||||
|
||||
///////////////////////////////////////////////////////////////////////
|
||||
//SPI data sample
|
||||
///////////////////////////////////////////////////////////////////////
|
||||
|
||||
generate
|
||||
genvar i;
|
||||
wire [31:0] recv_vld ;
|
||||
wire [31:0] spi_din ;
|
||||
for(i=0;i<32;i=i+1) begin: spi_sys_recv
|
||||
assign recv_vld[i] = add_cnt & (cnt_c == i );
|
||||
sirv_gnrl_dfflr #(1) spi_din_dfflr (recv_vld[i], mosi_data, spi_din[31-i], clk, rst_n);
|
||||
end
|
||||
endgenerate
|
||||
|
||||
|
||||
wire [1:0] state_c;
|
||||
wire [1:0] state_n;
|
||||
|
||||
|
||||
///////////////////////////////////////////////////////////////////////
|
||||
//init_addr capture
|
||||
///////////////////////////////////////////////////////////////////////
|
||||
wire [24:0] initaddr;
|
||||
wire initaddr_vld = (state_c == RECVCMD ) & add_cnt && (cnt_c == 5'd26);
|
||||
wire [1:0] initaddr_vld_r;
|
||||
sirv_gnrl_dffr #(2) initaddr_vld_r_dffr ({initaddr_vld_r[0],initaddr_vld}, initaddr_vld_r, clk, rst_n);
|
||||
|
||||
sirv_gnrl_dfflr #(25) initaddr_dfflr (initaddr_vld_r[0], spi_din[30:6], initaddr, clk, rst_n);
|
||||
|
||||
///////////////////////////////////////////////////////////////////////
|
||||
//CMD capture
|
||||
///////////////////////////////////////////////////////////////////////
|
||||
wire cmd ;
|
||||
sirv_gnrl_dfflr #(1) cmd_dfflr ( initaddr_vld_r[0], spi_din[31], cmd, clk, rst_n);
|
||||
|
||||
///////////////////////////////////////////////////////////////////////
|
||||
//CHIPID capture
|
||||
///////////////////////////////////////////////////////////////////////
|
||||
wire [4:0] chipid;
|
||||
wire [1:0] chipid_vld_r;
|
||||
wire chipid_vld = (state_c == RECVCMD ) & add_cnt & (cnt_c == 5'd30);
|
||||
//register cmd_vld to align it with cmd
|
||||
sirv_gnrl_dffr #(2) chipid_vld_r_dffr ({chipid_vld_r[0],chipid_vld}, chipid_vld_r, clk, rst_n);
|
||||
|
||||
sirv_gnrl_dfflr #(5) chipid_dfflr (chipid_vld_r[0], spi_din[5:1], chipid, clk, rst_n);
|
||||
|
||||
///////////////////////////////////////////////////////////////////////
|
||||
//ID matching determination
|
||||
///////////////////////////////////////////////////////////////////////
|
||||
wire chipid_match = (chipid == cfgid);
|
||||
wire chipid_dismatch = (chipid != cfgid);
|
||||
|
||||
|
||||
|
||||
///////////////////////////////////////////////////////////////////////
|
||||
//SPI Module State Machine
|
||||
///////////////////////////////////////////////////////////////////////
|
||||
|
||||
//Generating jump conditions for state machines
|
||||
wire ilde2recvcmd = (state_c == IDLE ) && csn_active && csn_n ;
|
||||
wire recvcmd2ilde = (state_c == RECVCMD ) && chipid_dismatch & end_cnt;
|
||||
wire recvcmd2write = (state_c == RECVCMD ) && chipid_match && ~cmd & end_cnt;
|
||||
wire recvcmd2read = (state_c == RECVCMD ) && chipid_match && cmd & end_cnt;
|
||||
wire write2idle = (state_c == WRITE ) && csn_p;
|
||||
wire read2idle = (state_c == READ ) && csn_p;
|
||||
|
||||
//The first section of the state machine
|
||||
//state_c
|
||||
sirv_gnrl_dffr #(2) state_c_dffr (state_n, state_c, clk, rst_n);
|
||||
|
||||
//state_n
|
||||
assign state_n = ((state_c == IDLE ) && ilde2recvcmd ) ? RECVCMD :
|
||||
((state_c == RECVCMD ) && recvcmd2ilde ) ? IDLE :
|
||||
((state_c == RECVCMD ) && recvcmd2write ) ? WRITE :
|
||||
((state_c == RECVCMD ) && recvcmd2read ) ? READ :
|
||||
((state_c == WRITE ) && write2idle ) ? IDLE :
|
||||
((state_c == READ ) && read2idle ) ? IDLE :
|
||||
state_c ;
|
||||
|
||||
|
||||
///////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
//Address generation for read and write operations
|
||||
//The address to be used for updating in the next
|
||||
//27 clock cycles in the read-write state
|
||||
///////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
wire second_falling;
|
||||
wire second_falling_w = (state_c == WRITE);
|
||||
sirv_gnrl_dfflr #(1) second_falling_dfflr (end_cnt ,second_falling_w, second_falling, clk, rst_n);
|
||||
|
||||
wire addr_update = ((state_c == READ) | ((state_c == WRITE) & second_falling)) & add_cnt & (cnt_c == 5'd27);
|
||||
wire [24:0] addr_c;
|
||||
|
||||
wire [24:0] addr_n = ilde2recvcmd ? 25'd0 :
|
||||
initaddr_vld_r[1] ? initaddr :
|
||||
addr_update ? addr_c + 25'd4 :
|
||||
addr_c ;
|
||||
|
||||
sirv_gnrl_dffr #(25) addr_c_dffr (addr_n, addr_c, clk, rst_n);
|
||||
|
||||
assign addr = addr_c;
|
||||
|
||||
///////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
//Write data and write signals generation
|
||||
///////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
wire wren_r;
|
||||
|
||||
wire wren_w = (state_c == WRITE) & add_cnt & (cnt_c == 5'd31);
|
||||
//wdata
|
||||
sirv_gnrl_dfflr #(32) wrdata_dfflr (wren_r, spi_din[31:0], wrdata, clk, rst_n);
|
||||
//wren_r
|
||||
|
||||
sirv_gnrl_dffr #(1) wren_r_dffr (wren_w, wren_r, clk, rst_n);
|
||||
|
||||
//wren
|
||||
sirv_gnrl_dffr #(1) wren_dffr (wren_r, wren, clk, rst_n);
|
||||
|
||||
///////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
//read signals generation
|
||||
///////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
wire rden_w = cmd & add_cnt & (cnt_c == 5'd28);
|
||||
sirv_gnrl_dffr #(1) rden_dffr (rden_w, rden, clk, rst_n);
|
||||
|
||||
//Read data register
|
||||
wire rddata_vld = cmd & add_cnt & (cnt_c == 5'd30);
|
||||
wire [31:0] rddata_reg;
|
||||
sirv_gnrl_dfflr #(32) rddata_reg_dfflr (rddata_vld, rddata[31:0], rddata_reg, clk, rst_n);
|
||||
|
||||
|
||||
///////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
//SPI send data update
|
||||
///////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
wire [31:0] spi_dout ;
|
||||
wire update_flag = cmd & add_cnt & (cnt_c == 5'd31);
|
||||
|
||||
wire [31:0] rddata_sr = update_flag ? rddata_reg[31:0] :
|
||||
((state_c == READ) & add_cnt) ? {spi_dout[30:0],1'b0} : //M 2024-06-24
|
||||
spi_dout ;
|
||||
|
||||
sirv_gnrl_dffr #(32) spi_dout_dffr (rddata_sr, spi_dout, clk, rst_n);
|
||||
|
||||
|
||||
///////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
//SPI send data
|
||||
///////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
assign miso = spi_dout[31];
|
||||
|
||||
|
||||
|
||||
///////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
//SPI output enable
|
||||
///////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
sirv_gnrl_dffrs #(1) oen_dffr (~(state_c == READ), oen, clk, rst_n);
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,68 @@
|
|||
module spram_model #(
|
||||
parameter width = 32
|
||||
,parameter depth = 256
|
||||
)(
|
||||
clka,
|
||||
ena,
|
||||
dina,
|
||||
addra,
|
||||
|
||||
clkb,
|
||||
enb,
|
||||
doutb,
|
||||
addrb
|
||||
);
|
||||
|
||||
//=================================================
|
||||
function integer clog2(input integer depth);
|
||||
begin
|
||||
for(clog2=0;depth>0;clog2=clog2+1)
|
||||
depth =depth>>1;
|
||||
end
|
||||
endfunction
|
||||
//=================================================
|
||||
|
||||
localparam aw = clog2(depth-1);
|
||||
//=================================================
|
||||
input clka;
|
||||
input ena;
|
||||
input [width-1:0] dina;
|
||||
input [aw-1:0] addra;
|
||||
|
||||
input clkb;
|
||||
input enb;
|
||||
output [width-1:0] doutb;
|
||||
input [aw-1:0] addrb;
|
||||
|
||||
|
||||
//================================================
|
||||
wire clka;
|
||||
wire ena;
|
||||
wire [width-1:0] dina;
|
||||
wire [aw-1:0] addra;
|
||||
|
||||
wire clkb;
|
||||
wire enb;
|
||||
reg [width-1:0] doutb;
|
||||
wire [aw-1:0] addrb;
|
||||
|
||||
|
||||
//================================================
|
||||
reg [width-1:0] mem[0:depth-1];
|
||||
|
||||
always@(posedge clka)begin
|
||||
if(ena)begin
|
||||
mem[addra] <=dina;
|
||||
end
|
||||
end
|
||||
|
||||
always@(posedge clkb)begin
|
||||
if(enb)begin
|
||||
doutb <=mem[addrb];
|
||||
end
|
||||
else begin
|
||||
doutb <=doutb;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,32 @@
|
|||
module sync_buf #(
|
||||
)(
|
||||
input logic clk,
|
||||
input logic rst_n,
|
||||
input logic ext_ena,
|
||||
input logic clr_ena,
|
||||
input logic clr_ena_sync,
|
||||
input logic sync_in,
|
||||
output logic sync_int,
|
||||
output logic sync_ext,
|
||||
output logic sync_clr
|
||||
);
|
||||
|
||||
|
||||
|
||||
logic [2:0] sync_r;
|
||||
always @(posedge clk or negedge rst_n) begin
|
||||
if(!rst_n) begin
|
||||
sync_r[2:0] <= 3'b000;
|
||||
sync_int <= 1'b0;
|
||||
sync_ext <= 1'b0;
|
||||
end
|
||||
else begin
|
||||
sync_r[2:0] <= {sync_r[1:0],sync_in}; // delay two clock
|
||||
sync_int <= (sync_r[2:1] == 2'b01) & !clr_ena_sync; // detect pos edge
|
||||
sync_ext <= sync_r[2] & ext_ena; // sync input to clk
|
||||
end
|
||||
end
|
||||
|
||||
assign sync_clr = ~(clr_ena & sync_in); // controlled buf out
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,637 @@
|
|||
//+FHDR--------------------------------------------------------------------------------------------------------
|
||||
// Company:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// File Name : ssytem_regfile.v
|
||||
// Department :
|
||||
// Author : PWY
|
||||
// Author's Tel :
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Relese History
|
||||
// Version Date Author Description
|
||||
// 1.0 2022-08-25 PWY
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Keywords :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Parameter
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Purpose :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Target Device:
|
||||
// Tool versions:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Reuse Issues
|
||||
// Reset Strategy:
|
||||
// Clock Domains:
|
||||
// Critical Timing:
|
||||
// Asynchronous I/F:
|
||||
// Synthesizable (y/n):
|
||||
// Other:
|
||||
//-FHDR--------------------------------------------------------------------------------------------------------
|
||||
|
||||
// -----------------------------------------------------------
|
||||
// -- Register address offset macros
|
||||
// -----------------------------------------------------------
|
||||
//Identity Register
|
||||
`define IDR 16'h00
|
||||
//Vendor Code Register
|
||||
`define VIDR 16'h04
|
||||
//RTL Freeze Date Register
|
||||
`define DATER 16'h08
|
||||
//Version Register
|
||||
`define VERR 16'h0C
|
||||
//Wirte And Read Test Register
|
||||
`define TESTR 16'h10
|
||||
//Interrupt Mask Register
|
||||
//[31:29] --> Reserved
|
||||
//[28 ] --> DBG UPD Interrupt Mask
|
||||
//[27 ] --> CH3 AWG Conflict nterrupt Mask
|
||||
//[26 ] --> CH3 LDST ADDR UNALGN Interrupt Mask
|
||||
//[25 ] --> CH3 DEC ERR Interrupt Mask
|
||||
//[24 ] --> CH3 EXITI Interrupt Mask
|
||||
//[23:20] --> Reserved
|
||||
//[19 ] --> CH2 AWG Conflict nterrupt Mask
|
||||
//[18 ] --> CH2 LDST ADDR UNALGN Interrupt Mask
|
||||
//[17 ] --> CH2 DEC ERR Interrupt Mask
|
||||
//[16 ] --> CH2 EXITI Interrupt Mask
|
||||
//[15:12] --> Reserved
|
||||
//[11 ] --> CH1 AWG Conflict nterrupt Mask
|
||||
//[10 ] --> CH1 LDST ADDR UNALGN Interrupt Mask
|
||||
//[9 ] --> CH1 DEC ERR Interrupt Mask
|
||||
//[8 ] --> CH1 EXITI Interrupt Mask
|
||||
//[7 :4] --> Reserved
|
||||
//[3 ] --> CH1 AWG Conflict nterrupt Mask
|
||||
//[2 ] --> CH1 LDST ADDR UNALGN Interrupt Mask
|
||||
//[1 ] --> CH1 DEC ERR Interrupt Mask
|
||||
//[0 ] --> CH1 EXITI Interrupt Mask
|
||||
`define IMR 16'h14
|
||||
//[31:29] --> Reserved
|
||||
//[28 ] --> DBG UPD Interrupt Status
|
||||
//[27 ] --> CH3 AWG Conflict nterrupt Status
|
||||
//[26 ] --> CH3 LDST ADDR UNALGN Interrupt Status
|
||||
//[25 ] --> CH3 DEC ERR Interrupt Status
|
||||
//[24 ] --> CH3 EXITI Interrupt Status
|
||||
//[23:20] --> Reserved
|
||||
//[19 ] --> CH2 AWG Conflict Status
|
||||
//[18 ] --> CH2 LDST ADDR UNALGN Interrupt Status
|
||||
//[17 ] --> CH2 DEC ERR Interrupt Status
|
||||
//[16 ] --> CH2 EXITI Interrupt Status
|
||||
//[15:12] --> Reserved
|
||||
//[11 ] --> CH1 AWG Conflict nterrupt Status
|
||||
//[10 ] --> CH1 LDST ADDR UNALGN Interrupt Status
|
||||
//[9 ] --> CH1 DEC ERR Interrupt Status
|
||||
//[8 ] --> CH1 EXITI Interrupt Status
|
||||
//[7 :4] --> Reserved
|
||||
//[3 ] --> CH1 AWG Conflict nterrupt Status
|
||||
//[2 ] --> CH1 LDST ADDR UNALGN Interrupt Status
|
||||
//[1 ] --> CH1 DEC ERR Interrupt Status
|
||||
//[0 ] --> CH1 EXITI Interrupt Status
|
||||
`define ISR 16'h18
|
||||
//Soft Reset Time Register
|
||||
`define SFRTR 16'h1C
|
||||
//Soft Reset Register
|
||||
`define SFRR 16'h20
|
||||
//CH0 Soft Reset Register
|
||||
`define CH0RSTR 16'h24
|
||||
//CH1Soft Reset Register
|
||||
`define CH1RSTR 16'h28
|
||||
//CH2 Soft Reset Register
|
||||
`define CH2RSTR 16'h2C
|
||||
//CH3 Soft Reset Register
|
||||
`define CH3RSTR 16'h30
|
||||
//Debug config Register
|
||||
`define DBGCFGR 16'h34
|
||||
//Post Masking Interrupt Status Register
|
||||
//Interrupt Status Register
|
||||
//[31:29] --> Reserved
|
||||
//[28 ] --> DBG UPD Interrupt Status
|
||||
//[27 ] --> CH3 AWG Conflict nterrupt Status
|
||||
//[26 ] --> CH3 LDST ADDR UNALGN Masking Interrupt Status
|
||||
//[25 ] --> CH3 DEC ERR Masking Interrupt Status
|
||||
//[24 ] --> CH3 EXITI Masking Interrupt Status
|
||||
//[23:20] --> Reserved
|
||||
//[19 ] --> CH2 AWG Conflict Status
|
||||
//[18 ] --> CH2 LDST ADDR UNALGN Masking Interrupt Status
|
||||
//[17 ] --> CH2 DEC ERR Masking Interrupt Status
|
||||
//[16 ] --> CH2 EXITI Masking Interrupt Status
|
||||
//[15:12] --> Reserved
|
||||
//[11 ] --> CH1 AWG Conflict nterrupt Status
|
||||
//[10 ] --> CH1 LDST ADDR UNALGN Masking Interrupt Status
|
||||
//[9 ] --> CH1 DEC ERR Masking Interrupt Status
|
||||
//[8 ] --> CH1 EXITI Masking Interrupt Status
|
||||
//[7 :4] --> Reserved
|
||||
//[3 ] --> CH1 AWG Conflict nterrupt Status
|
||||
//[2 ] --> CH1 LDST ADDR UNALGN Masking Interrupt Status
|
||||
//[1 ] --> CH1 DEC ERR Masking Interrupt Status
|
||||
//[0 ] --> CH1 EXITI Masking Interrupt Status
|
||||
`define MISR 16'h40
|
||||
|
||||
|
||||
module system_regfile (
|
||||
//system port
|
||||
input clk // System Main Clock
|
||||
,input rst_n // Spi Reset active low
|
||||
//rw op port
|
||||
,input [31 :0] wrdata // write data
|
||||
,input wren // write enable
|
||||
,input [15 :0] rwaddr // read & write address
|
||||
,input rden // read enable
|
||||
,output [31 :0] rddata // read data
|
||||
//debug cfg port
|
||||
,output dbg_enable //active high
|
||||
,output dbg_data_sel //1'b0-->mod;1'b1-->dsp
|
||||
,output [3 :0] dbg_ch_sel //4'b0001-->ch0;4'b0010-->ch1;
|
||||
//4'b0100-->ch2;4'b1000-->ch3;
|
||||
//debug status Port
|
||||
,input dbg_upd
|
||||
//ch0 status Port
|
||||
,input ch0_proc_cft
|
||||
,input ch0_ldst_addr_unalgn
|
||||
,input ch0_dec_err
|
||||
,input ch0_exit_irq
|
||||
//ch1 status Port
|
||||
,input ch1_proc_cft
|
||||
,input ch1_ldst_addr_unalgn
|
||||
,input ch1_dec_err
|
||||
,input ch1_exit_irq
|
||||
//ch2 status Port
|
||||
,input ch2_proc_cft
|
||||
,input ch2_ldst_addr_unalgn
|
||||
,input ch2_dec_err
|
||||
,input ch2_exit_irq
|
||||
//ch3 status Port
|
||||
,input ch3_proc_cft
|
||||
,input ch3_ldst_addr_unalgn
|
||||
,input ch3_dec_err
|
||||
,input ch3_exit_irq
|
||||
//Soft Reset out
|
||||
,output sys_soft_rstn
|
||||
,output ch0_soft_rstn
|
||||
,output ch1_soft_rstn
|
||||
,output ch2_soft_rstn
|
||||
,output ch3_soft_rstn
|
||||
//Interrupt output port
|
||||
,output irq
|
||||
);
|
||||
|
||||
localparam L = 1'b0,
|
||||
H = 1'b1;
|
||||
|
||||
localparam IDRD = 32'h41574743;
|
||||
localparam VIDRD = 32'h55535443;
|
||||
localparam DATERD = 32'h20220831;
|
||||
localparam VERSION = 32'h00000001;
|
||||
localparam TESTRD = 32'h01234567;
|
||||
// ------------------------------------------------------
|
||||
// -- Register enable (select) wires
|
||||
// ------------------------------------------------------
|
||||
wire idren; // idr select
|
||||
wire vidren; // vidr select
|
||||
wire dateren; // dater select
|
||||
wire verren; // dater select
|
||||
wire testren; // testr select
|
||||
wire imren; // imr select
|
||||
wire isren; // isr select
|
||||
wire misren; // imsr select
|
||||
wire sfrtren; // sfrtr select
|
||||
wire sfrren; // sfrr select
|
||||
wire ch0rstren; // mcurstr select
|
||||
wire ch1rstren; // awgrstr select
|
||||
wire ch2rstren; // adacrstr select
|
||||
wire ch3rstren; // adacrstr select
|
||||
wire dbgcfgren; // adacrstr select
|
||||
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- Register write enable wires
|
||||
// ------------------------------------------------------
|
||||
wire testrwe; // testr write enable
|
||||
wire imrwe; // imr write enable
|
||||
wire misrwe; // imsr write enable
|
||||
wire sfrtrwe; // sfrtr write enable
|
||||
wire sfrrwe; // sfrr write enable
|
||||
wire ch0rstrwe; // mcurstr select
|
||||
wire ch1rstrwe; // awgrstr select
|
||||
wire ch2rstrwe; // adacrstr select
|
||||
wire ch3rstrwe; // adacrstr select
|
||||
wire dbgcfgrwe; // adacrstr write enable
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- Misc wires
|
||||
// ------------------------------------------------------
|
||||
wire [31 :0] irisr ; // original interrupt status wire
|
||||
wire icr ; // interrupt status clear wire
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- Misc Registers
|
||||
// ------------------------------------------------------
|
||||
wire [31 :0] testr ;
|
||||
wire [31 :0] imr ;
|
||||
wire [31 :0] isr ;
|
||||
wire [31 :0] misr ;
|
||||
wire [31 :0] sfrtr ;
|
||||
wire [0 :0] sfrr ;
|
||||
wire [0 :0] ch0rstr ;
|
||||
wire [0 :0] ch1rstr ;
|
||||
wire [0 :0] ch2rstr ;
|
||||
wire [0 :0] ch3rstr ;
|
||||
wire [5 :0] dbgcfgr ;
|
||||
|
||||
reg [31 :0] rddata_reg ;
|
||||
|
||||
|
||||
wire dbg_upd_r ;
|
||||
//ch0 status reg
|
||||
wire ch0_proc_cft_r ;
|
||||
wire ch0_ldst_addr_unalgn_r ;
|
||||
wire ch0_dec_err_r ;
|
||||
wire ch0_exit_irq_r ;
|
||||
//ch1 status reg
|
||||
wire ch1_proc_cft_r ;
|
||||
wire ch1_dbg_fifo_f_r ;
|
||||
wire ch1_ldst_addr_unalgn_r ;
|
||||
wire ch1_dec_err_r ;
|
||||
wire ch1_exit_irq_r ;
|
||||
//ch2 status reg
|
||||
wire ch2_proc_cft_r ;
|
||||
wire ch2_ldst_addr_unalgn_r ;
|
||||
wire ch2_dec_err_r ;
|
||||
wire ch2_exit_irq_r ;
|
||||
//ch3 status reg
|
||||
wire ch3_proc_cft_r ;
|
||||
wire ch3_ldst_addr_unalgn_r ;
|
||||
wire ch3_dec_err_r ;
|
||||
wire ch3_exit_irq_r ;
|
||||
|
||||
wire sys_soft_rstn_r ;
|
||||
wire ch0_soft_rstn_r ;
|
||||
wire ch1_soft_rstn_r ;
|
||||
wire ch2_soft_rstn_r ;
|
||||
wire ch3_soft_rstn_r ;
|
||||
// ------------------------------------------------------
|
||||
// -- Address decoder
|
||||
//
|
||||
// Decodes the register address offset input(reg_addr)
|
||||
// to produce enable (select) signals for each of the
|
||||
// SW-registers in the macrocell. The reg_addr input
|
||||
// is bits [8:0] of the paddr bus.
|
||||
// ------------------------------------------------------
|
||||
assign idren = (rwaddr[15:2] == `IDR >> 2) ? 1'b1 : 1'b0;
|
||||
assign vidren = (rwaddr[15:2] == `VIDR >> 2) ? 1'b1 : 1'b0;
|
||||
assign dateren = (rwaddr[15:2] == `DATER >> 2) ? 1'b1 : 1'b0;
|
||||
assign verren = (rwaddr[15:2] == `VERR >> 2) ? 1'b1 : 1'b0;
|
||||
assign testren = (rwaddr[15:2] == `TESTR >> 2) ? 1'b1 : 1'b0;
|
||||
assign imren = (rwaddr[15:2] == `IMR >> 2) ? 1'b1 : 1'b0;
|
||||
assign isren = (rwaddr[15:2] == `ISR >> 2) ? 1'b1 : 1'b0;
|
||||
assign misren = (rwaddr[15:2] == `MISR >> 2) ? 1'b1 : 1'b0;
|
||||
assign sfrtren = (rwaddr[15:2] == `SFRTR >> 2) ? 1'b1 : 1'b0;
|
||||
assign sfrren = (rwaddr[15:2] == `SFRR >> 2) ? 1'b1 : 1'b0;
|
||||
assign ch0rstren = (rwaddr[15:2] == `CH0RSTR >> 2) ? 1'b1 : 1'b0;
|
||||
assign ch1rstren = (rwaddr[15:2] == `CH1RSTR >> 2) ? 1'b1 : 1'b0;
|
||||
assign ch2rstren = (rwaddr[15:2] == `CH2RSTR >> 2) ? 1'b1 : 1'b0;
|
||||
assign ch3rstren = (rwaddr[15:2] == `CH3RSTR >> 2) ? 1'b1 : 1'b0;
|
||||
assign dbgcfgren = (rwaddr[15:2] == `DBGCFGR >> 2) ? 1'b1 : 1'b0;
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- Write enable signals
|
||||
//
|
||||
// Write enable signals for writable SW-registers.
|
||||
// The write enable for each register is the ANDed
|
||||
// result of the register enable and the input reg_wren
|
||||
// ------------------------------------------------------
|
||||
assign testrwe = testren & wren;
|
||||
assign imrwe = imren & wren;
|
||||
assign sfrtrwe = sfrtren & wren;
|
||||
assign sfrrwe = sfrren & wren;
|
||||
assign ch0rstrwe = ch0rstren & wren;
|
||||
assign ch1rstrwe = ch1rstren & wren;
|
||||
assign ch2rstrwe = ch2rstren & wren;
|
||||
assign ch3rstrwe = ch3rstren & wren;
|
||||
assign dbgcfgrwe = dbgcfgren & wren;
|
||||
|
||||
// ---------------------------------------------------------------------------------------------------
|
||||
// -- interrupt Mask Register
|
||||
//
|
||||
// Write interrupt Mask for 'imr' : 12-bit register
|
||||
// Register is split into the following bit fields
|
||||
//
|
||||
//Interrupt Mask Register
|
||||
//[31:29] --> Reserved
|
||||
//[28 ] --> DBG UPD Interrupt Mask
|
||||
//[27 ] --> CH3 AWG Conflict nterrupt Mask
|
||||
//[26 ] --> CH3 LDST ADDR UNALGN Interrupt Mask
|
||||
//[25 ] --> CH3 DEC ERR Interrupt Mask
|
||||
//[24 ] --> CH3 EXITI Interrupt Mask
|
||||
//[23:20] --> Reserved
|
||||
//[19 ] --> CH2 AWG Conflict nterrupt Mask
|
||||
//[18 ] --> CH2 LDST ADDR UNALGN Interrupt Mask
|
||||
//[17 ] --> CH2 DEC ERR Interrupt Mask
|
||||
//[16 ] --> CH2 EXITI Interrupt Mask
|
||||
//[15:12] --> Reserved
|
||||
//[11 ] --> CH1 AWG Conflict nterrupt Mask
|
||||
//[10 ] --> CH1 LDST ADDR UNALGN Interrupt Mask
|
||||
//[9 ] --> CH1 DEC ERR Interrupt Mask
|
||||
//[8 ] --> CH1 EXITI Interrupt Mask
|
||||
//[7 :4] --> Reserved
|
||||
//[3 ] --> CH1 AWG Conflict nterrupt Mask
|
||||
//[2 ] --> CH1 LDST ADDR UNALGN Interrupt Mask
|
||||
//[1 ] --> CH1 DEC ERR Interrupt Mask
|
||||
//[0 ] --> CH1 EXITI Interrupt Mask
|
||||
// ---------------------------------------------------------------------------------------------------
|
||||
sirv_gnrl_dfflr #(32) imr_dfflr (imrwe, wrdata[31:0], imr, clk, rst_n);
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- testr Register
|
||||
//
|
||||
// Write testr for 'TESTR' : 32-bit register
|
||||
// Register is split into the following bit fields
|
||||
//
|
||||
// [31:0] --> testr
|
||||
// ------------------------------------------------------
|
||||
sirv_gnrl_dfflrd #(32) testr_dfflrd (TESTRD, testrwe, wrdata[31:0], testr, clk, rst_n);
|
||||
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- Soft Reset Count Register
|
||||
//
|
||||
// Write Soft Reset Count for 'sfrtcr' : 6-bit register
|
||||
// Register is split into the following bit fields
|
||||
//
|
||||
// [31:0] --> sfrtcr,default value 32'd300
|
||||
// ------------------------------------------------------
|
||||
sirv_gnrl_dfflrd #(32) sfrtr_dfflrd (32'd300, sfrtrwe, wrdata[31:0], sfrtr, clk, rst_n);/////////////////////////////sfrtcr-->sfrtr
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- debug config Register
|
||||
//
|
||||
//
|
||||
// [3:0] --> dbgcfgr,default value 4'b0000
|
||||
// ------------------------------------------------------
|
||||
sirv_gnrl_dfflr #(6) dbgcfgr_dfflr (dbgcfgrwe, wrdata[5:0], dbgcfgr, clk, rst_n);
|
||||
// ------------------------------------------------------
|
||||
// -- soft reset count
|
||||
// ------------------------------------------------------
|
||||
|
||||
wire [31:0] cnt_c;
|
||||
|
||||
wire add_cnt = (sys_soft_rstn_r == L)
|
||||
| (ch0_soft_rstn_r == L)
|
||||
| (ch1_soft_rstn_r == L)
|
||||
| (ch2_soft_rstn_r == L)
|
||||
| (ch3_soft_rstn_r == L);
|
||||
|
||||
wire end_cnt = add_cnt & (cnt_c == sfrtr-1);
|
||||
|
||||
wire [31:0] cnt_n = end_cnt ? 32'h0 :
|
||||
add_cnt ? cnt_c + 1'b1 :
|
||||
cnt_c ;
|
||||
|
||||
|
||||
sirv_gnrl_dffr #(32) cnt_c_dffr (cnt_n, cnt_c, clk, rst_n);
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- Soft Reset Register
|
||||
//
|
||||
// Write Soft Reset for 'sfrtr' : 1-bit register
|
||||
// Register is split into the following bit fields
|
||||
//
|
||||
// [16'h0024] --> System Soft Reset ,low active
|
||||
// [16'h0028] --> MCU Soft Reset ,low active
|
||||
// [16'h002C] --> AWG Soft Reset ,low active
|
||||
// [16'h0030] --> DAC Soft Reset ,low active
|
||||
// ------------------------------------------------------
|
||||
|
||||
//sys_soft_rstn_r
|
||||
wire sys_soft_rstn_en = end_cnt | sfrrwe;
|
||||
wire sys_soft_rstn_w = end_cnt ? 1'b1 :
|
||||
sfrrwe ? 1'b0 :
|
||||
1'b1 ;
|
||||
sirv_gnrl_dfflrs #(1) sys_soft_rstn_r_dffls (sys_soft_rstn_en, sys_soft_rstn_w, sys_soft_rstn_r, clk, rst_n);
|
||||
|
||||
//ch0_soft_rstn_r
|
||||
wire ch0_soft_rstn_en = end_cnt | ch0rstrwe;
|
||||
wire ch0_soft_rstn_r_w = end_cnt ? 1'b1 :
|
||||
ch0rstrwe ? 1'b0 :
|
||||
1'b1 ;
|
||||
sirv_gnrl_dfflrs #(1) ch0_soft_rstn_r_dffls (ch0_soft_rstn_en, ch0_soft_rstn_r_w, ch0_soft_rstn_r, clk, rst_n);
|
||||
|
||||
//ch1_soft_rstn_r
|
||||
wire ch1_soft_rstn_en = end_cnt | ch1rstrwe;
|
||||
wire ch1_soft_rstn_w = end_cnt ? 1'b1 :
|
||||
ch1rstrwe ? 1'b0 :
|
||||
1'b1 ;
|
||||
sirv_gnrl_dfflrs #(1) ch1_soft_rstn_r_dffls (ch1_soft_rstn_en, ch1_soft_rstn_w, ch1_soft_rstn_r, clk, rst_n);
|
||||
|
||||
//ch2_soft_rstn_r
|
||||
wire ch2_soft_rstn_en = end_cnt | ch2rstrwe;
|
||||
wire ch2_soft_rstn_w = end_cnt ? 1'b1 :
|
||||
ch2rstrwe ? 1'b0 :
|
||||
1'b1 ;
|
||||
sirv_gnrl_dfflrs #(1) ch2_soft_rstn_r_dffls (ch2_soft_rstn_en, ch2_soft_rstn_w, ch2_soft_rstn_r, clk, rst_n);
|
||||
|
||||
//ch3_soft_rstn_r
|
||||
wire ch3_soft_rstn_en = end_cnt | ch3rstrwe;
|
||||
wire ch3_soft_rstn_w = end_cnt ? 1'b1 :
|
||||
ch3rstrwe ? 1'b0 :
|
||||
1'b1 ;
|
||||
sirv_gnrl_dfflrs #(1) ch3_soft_rstn_r_dffls (ch3_soft_rstn_en, ch3_soft_rstn_w, ch3_soft_rstn_r, clk, rst_n);
|
||||
|
||||
|
||||
assign sys_soft_rstn = sys_soft_rstn_r;
|
||||
assign ch0_soft_rstn = ch0_soft_rstn_r;
|
||||
assign ch1_soft_rstn = ch1_soft_rstn_r;
|
||||
assign ch2_soft_rstn = ch2_soft_rstn_r;
|
||||
assign ch3_soft_rstn = ch3_soft_rstn_r;
|
||||
// ------------------------------------------------------
|
||||
// -- Read data mux
|
||||
//
|
||||
// -- The data from the selected register is
|
||||
// -- placed on a zero-padded 32-bit read data bus.
|
||||
// ------------------------------------------------------
|
||||
always @(*) begin : RDDATA_PROC
|
||||
rddata_reg = {32{1'b0}};
|
||||
if(idren == H ) rddata_reg[31:0] = IDRD;
|
||||
if(vidren == H ) rddata_reg[31:0] = VIDRD;
|
||||
if(dateren == H ) rddata_reg[31:0] = DATERD;
|
||||
if(verren == H ) rddata_reg[31:0] = VERSION;
|
||||
if(testren == H ) rddata_reg[31:0] = testr;
|
||||
if(imren == H ) rddata_reg[31:0] = imr;
|
||||
if(isren == H ) rddata_reg[31:0] = isr;
|
||||
if(misren == H ) rddata_reg[31:0] = misr;
|
||||
if(sfrtren == H ) rddata_reg[31:0] = sfrtr;
|
||||
if(dbgcfgren == H ) rddata_reg[5 :0] = dbgcfgr;
|
||||
end
|
||||
|
||||
//rddata
|
||||
sirv_gnrl_dffr #(32) rddata_dffr (rddata_reg, rddata, clk, rst_n);
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- interrupt status
|
||||
// ------------------------------------------------------
|
||||
|
||||
//read misr clear interrupts
|
||||
assign icr = (misren) && rden;
|
||||
|
||||
|
||||
//dbg_upd_r
|
||||
wire dbg_upd_en = icr | dbg_upd;
|
||||
wire dbg_upd_w = ~icr | dbg_upd;
|
||||
sirv_gnrl_dfflr #(1) dbg_upd_r_dfflr (dbg_upd_en, dbg_upd_w, dbg_upd_r, clk, rst_n);
|
||||
|
||||
//ch0_proc_cft_r
|
||||
wire ch0_proc_cft_en = icr | ch0_proc_cft;
|
||||
wire ch0_proc_cft_w = ~icr | ch0_proc_cft;
|
||||
sirv_gnrl_dfflr #(1) ch0_proc_cft_r_dfflr (ch0_proc_cft_en, ch0_proc_cft_w, ch0_proc_cft_r, clk, rst_n);
|
||||
|
||||
//ch0_ldst_addr_unalgn_r
|
||||
wire ch0_ldst_addr_unalgn_en = icr | ch0_ldst_addr_unalgn;
|
||||
wire ch0_ldst_addr_unalgn_w = ~icr | ch0_ldst_addr_unalgn;
|
||||
sirv_gnrl_dfflr #(1) ch0_ldst_addr_unalgn_r_dfflr (ch0_ldst_addr_unalgn_en, ch0_ldst_addr_unalgn_w, ch0_ldst_addr_unalgn_r, clk, rst_n);
|
||||
|
||||
//ch0_dec_err_r
|
||||
wire ch0_dec_err_en = icr | ch0_dec_err;
|
||||
wire ch0_dec_err_w = ~icr | ch0_dec_err;
|
||||
sirv_gnrl_dfflr #(1) ch0_dec_err_r_dfflr (ch0_dec_err_en, ch0_dec_err_w, ch0_dec_err_r, clk, rst_n);
|
||||
|
||||
//ch0_exit_irq_r
|
||||
wire ch0_exit_irq_en = icr | ch0_exit_irq;
|
||||
wire ch0_exit_irq_w = ~icr | ch0_exit_irq;
|
||||
sirv_gnrl_dfflr #(1) ch0_exit_irq_r_dfflr (ch0_exit_irq_en, ch0_exit_irq_w, ch0_exit_irq_r, clk, rst_n);
|
||||
|
||||
|
||||
//ch1_proc_cft_r
|
||||
wire ch1_proc_cft_en = icr | ch1_proc_cft;
|
||||
wire ch1_proc_cft_w = ~icr | ch1_proc_cft;
|
||||
sirv_gnrl_dfflr #(1) ch1_proc_cft_r_dfflr (ch1_proc_cft_en, ch1_proc_cft_w, ch1_proc_cft_r, clk, rst_n);
|
||||
|
||||
//ch1_ldst_addr_unalgn_r
|
||||
wire ch1_ldst_addr_unalgn_en = icr | ch1_ldst_addr_unalgn;
|
||||
wire ch1_ldst_addr_unalgn_w = ~icr | ch1_ldst_addr_unalgn;
|
||||
sirv_gnrl_dfflr #(1) ch1_ldst_addr_unalgn_r_dfflr (ch1_ldst_addr_unalgn_en, ch1_ldst_addr_unalgn_w, ch1_ldst_addr_unalgn_r, clk, rst_n);
|
||||
|
||||
//ch1_dec_err_r
|
||||
wire ch1_dec_err_en = icr | ch1_dec_err;
|
||||
wire ch1_dec_err_w = ~icr | ch1_dec_err;
|
||||
sirv_gnrl_dfflr #(1) ch1_dec_err_r_dfflr (ch1_dec_err_en, ch1_dec_err_w, ch1_dec_err_r, clk, rst_n);
|
||||
|
||||
//ch1_exit_irq_r
|
||||
wire ch1_exit_irq_en = icr | ch1_exit_irq;
|
||||
wire ch1_exit_irq_w = ~icr | ch1_exit_irq;
|
||||
sirv_gnrl_dfflr #(1) ch1_exit_irq_r_dfflr (ch1_exit_irq_en, ch1_exit_irq_w, ch1_exit_irq_r, clk, rst_n);
|
||||
|
||||
//ch2_proc_cft_r
|
||||
wire ch2_proc_cft_en = icr | ch2_proc_cft;
|
||||
wire ch2_proc_cft_w = ~icr | ch2_proc_cft;
|
||||
sirv_gnrl_dfflr #(1) ch2_proc_cft_r_dfflr (ch2_proc_cft_en, ch2_proc_cft_w, ch2_proc_cft_r, clk, rst_n);
|
||||
|
||||
//ch2_ldst_addr_unalgn_r
|
||||
wire ch2_ldst_addr_unalgn_en = icr | ch2_ldst_addr_unalgn;
|
||||
wire ch2_ldst_addr_unalgn_w = ~icr | ch2_ldst_addr_unalgn;
|
||||
sirv_gnrl_dfflr #(1) ch2_ldst_addr_unalgn_r_dfflr (ch2_ldst_addr_unalgn_en, ch2_ldst_addr_unalgn_w, ch2_ldst_addr_unalgn_r, clk, rst_n);
|
||||
|
||||
//ch2_dec_err_r
|
||||
wire ch2_dec_err_en = icr | ch2_dec_err;
|
||||
wire ch2_dec_err_w = ~icr | ch2_dec_err;
|
||||
sirv_gnrl_dfflr #(1) ch2_dec_err_r_dfflr (ch2_dec_err_en, ch2_dec_err_w, ch2_dec_err_r, clk, rst_n);
|
||||
|
||||
//ch2_exit_irq_r
|
||||
wire ch2_exit_irq_en = icr | ch2_exit_irq;
|
||||
wire ch2_exit_irq_w = ~icr | ch2_exit_irq;
|
||||
sirv_gnrl_dfflr #(1) ch2_exit_irq_r_dfflr (ch2_exit_irq_en, ch2_exit_irq_w, ch2_exit_irq_r, clk, rst_n);
|
||||
|
||||
//ch3_proc_cft_r
|
||||
wire ch3_proc_cft_en = icr | ch3_proc_cft;
|
||||
wire ch3_proc_cft_w = ~icr | ch3_proc_cft;
|
||||
sirv_gnrl_dfflr #(1) ch3_proc_cft_r_dfflr (ch3_proc_cft_en, ch3_proc_cft_w, ch3_proc_cft_r, clk, rst_n);
|
||||
|
||||
//ch3_ldst_addr_unalgn_r
|
||||
wire ch3_ldst_addr_unalgn_en = icr | ch3_ldst_addr_unalgn;
|
||||
wire ch3_ldst_addr_unalgn_w = ~icr | ch3_ldst_addr_unalgn;
|
||||
sirv_gnrl_dfflr #(1) ch3_ldst_addr_unalgn_r_dfflr (ch3_ldst_addr_unalgn_en, ch3_ldst_addr_unalgn_w, ch3_ldst_addr_unalgn_r, clk, rst_n);
|
||||
|
||||
//ch3_dec_err_r
|
||||
wire ch3_dec_err_en = icr | ch3_dec_err;
|
||||
wire ch3_dec_err_w = ~icr | ch3_dec_err;
|
||||
sirv_gnrl_dfflr #(1) ch3_dec_err_r_dfflr (ch3_dec_err_en, ch3_dec_err_w, ch3_dec_err_r, clk, rst_n);
|
||||
|
||||
//ch3_exit_irq_r
|
||||
wire ch3_exit_irq_en = icr | ch3_exit_irq;
|
||||
wire ch3_exit_irq_w = ~icr | ch3_exit_irq;
|
||||
sirv_gnrl_dfflr #(1) ch3_exit_irq_r_dfflr (ch3_exit_irq_en, ch3_exit_irq_w, ch3_exit_irq_r, clk, rst_n);
|
||||
|
||||
//irisr
|
||||
assign irisr[31] = L ;
|
||||
assign irisr[30] = L ;
|
||||
assign irisr[29] = L ;
|
||||
assign irisr[28] = dbg_upd_r ;
|
||||
assign irisr[27] = ch3_proc_cft_r ;
|
||||
assign irisr[26] = ch3_ldst_addr_unalgn_r ;
|
||||
assign irisr[25] = ch3_dec_err_r ;
|
||||
assign irisr[24] = ch3_exit_irq_r ;
|
||||
assign irisr[23] = L ;
|
||||
assign irisr[22] = L ;
|
||||
assign irisr[21] = L ;
|
||||
assign irisr[20] = L ;
|
||||
assign irisr[19] = ch2_proc_cft_r ;
|
||||
assign irisr[18] = ch2_ldst_addr_unalgn_r ;
|
||||
assign irisr[17] = ch2_dec_err_r ;
|
||||
assign irisr[16] = ch2_exit_irq_r ;
|
||||
assign irisr[15] = L ;
|
||||
assign irisr[14] = L ;
|
||||
assign irisr[13] = L ;
|
||||
assign irisr[12] = L ;
|
||||
assign irisr[11] = ch1_proc_cft_r ;
|
||||
assign irisr[10] = ch1_ldst_addr_unalgn_r ;
|
||||
assign irisr[9 ] = ch1_dec_err_r ;
|
||||
assign irisr[8 ] = ch1_exit_irq_r ;
|
||||
assign irisr[7 ] = L ;
|
||||
assign irisr[6 ] = L ;
|
||||
assign irisr[5 ] = L ;
|
||||
assign irisr[4 ] = L ;
|
||||
assign irisr[3 ] = ch0_proc_cft_r ;
|
||||
assign irisr[2 ] = ch0_ldst_addr_unalgn_r ;
|
||||
assign irisr[1 ] = ch0_dec_err_r ;
|
||||
assign irisr[0 ] = ch0_exit_irq_r ;
|
||||
|
||||
// ------------------------------------------------------
|
||||
// -- Interrupt Status Register - Read Only
|
||||
//
|
||||
// This register contains the status of all
|
||||
// XYZ Chip interrupts after masking.
|
||||
// ------------------------------------------------------
|
||||
sirv_gnrl_dffr #(32) isr_dffr (irisr, isr, clk, rst_n);
|
||||
|
||||
//misr
|
||||
wire[31:0] misr_w = imr & irisr;
|
||||
sirv_gnrl_dffr #(32) misr_dffr (misr_w, misr, clk, rst_n);
|
||||
|
||||
//irq
|
||||
wire irq_w = |misr;
|
||||
sirv_gnrl_dffr #(1) irq_dffr (irq_w, irq, clk, rst_n);
|
||||
|
||||
//debug cfg
|
||||
|
||||
assign dbg_enable = dbgcfgr[0];
|
||||
assign dbg_data_sel = dbgcfgr[1];
|
||||
assign dbg_ch_sel = dbgcfgr[5:2];
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
`undef IDR
|
||||
`undef VIDR
|
||||
`undef DATER
|
||||
`undef VERR
|
||||
`undef TESTR
|
||||
`undef IMR
|
||||
`undef ISR
|
||||
`undef MISR
|
||||
`undef SFRTR
|
||||
`undef SFRR
|
||||
`undef CH0RSTR
|
||||
`undef CH1RSTR
|
||||
`undef CH2RSTR
|
||||
`undef CH3RSTR
|
||||
`undef DBGCFGR
|
||||
|
|
@ -0,0 +1,633 @@
|
|||
//+FHDR--------------------------------------------------------------------------------------------------------
|
||||
// Company:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// File Name : channel_top.v
|
||||
// Department :
|
||||
// Author : pwy
|
||||
// Author's Tel :
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Relese History
|
||||
// Version Date Author Description
|
||||
// 1.2 2024-04-16 pwy XYZ channel the top-level module
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Keywords :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Parameter
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Purpose :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Target Device:
|
||||
// Tool versions:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Reuse Issues
|
||||
// Reset Strategy:
|
||||
// Clock Domains:
|
||||
// Critical Timing:
|
||||
// Asynchronous I/F:
|
||||
// Synthesizable (y/n):
|
||||
// Other:
|
||||
//-FHDR------------------------------------------------------------------------------------------------------------
|
||||
`include "../define/chip_define.v"
|
||||
`include "../qubitmcu/qbmcu_defines.v"
|
||||
module channel_top (
|
||||
//system port
|
||||
input clk
|
||||
,input rst_n
|
||||
//Sync Start
|
||||
,input sync_int
|
||||
//Decoded port
|
||||
,output dec_o_ilegl
|
||||
//Misaligned memory address
|
||||
,output agu_o_addr_unalgn
|
||||
//
|
||||
,output awg_proc_cft
|
||||
,output mcu_ext_o_intr
|
||||
//Feedback signal from the readout chip
|
||||
,input [1 :0] fb_st_in
|
||||
//ITCM
|
||||
,input [`QBMCU_DTCM_ADDR_SIZE-1 :0] itcm_i_rwaddr
|
||||
,input [`QBMCU_XLEN-1 :0] itcm_i_wrdata
|
||||
,input itcm_i_wren
|
||||
,input [`QBMCU_XLEN/8-1 :0] itcm_i_wrmask
|
||||
,input itcm_i_rden
|
||||
,output [`QBMCU_XLEN-1 :0] itcm_o_rddata
|
||||
//DTCM
|
||||
,input [`QBMCU_DTCM_ADDR_SIZE-1 :0] dtcm_i_rwaddr
|
||||
,input [`QBMCU_XLEN-1 :0] dtcm_i_wrdata
|
||||
,input dtcm_i_wren
|
||||
,input [`QBMCU_XLEN/8-1 :0] dtcm_i_wrmask
|
||||
,input dtcm_i_rden
|
||||
,output [`QBMCU_XLEN-1 :0] dtcm_o_rddata
|
||||
//ctrl regfile
|
||||
,input [31 :0] ctrl_wrdata
|
||||
,input ctrl_wren
|
||||
,input [15 :0] ctrl_rwaddr
|
||||
,input ctrl_rden
|
||||
,output [31 :0] ctrl_rddata
|
||||
//Envelope storage read/write signal
|
||||
,input [31 :0] enve_bwrdata
|
||||
,input [0 :0] enve_bwren
|
||||
,input [14 :0] enve_brwaddr
|
||||
,input [0 :0] enve_brden
|
||||
,output [31 :0] enve_brddata
|
||||
//envelope index lookup table read-write signal
|
||||
,input [31 :0] enve_id_bwrdata
|
||||
,input [0 :0] enve_id_bwren
|
||||
,input [7 :0] enve_id_brwaddr
|
||||
,input [0 :0] enve_id_brden
|
||||
,output [31 :0] enve_id_brddata
|
||||
//DAC cfg
|
||||
//dac regfile
|
||||
,input [31 :0] dac_wrdata
|
||||
,input dac_wren
|
||||
,input [15 :0] dac_rwaddr
|
||||
,input dac_rden
|
||||
,output [31 :0] dac_rddata
|
||||
,output dac_Prbs
|
||||
,output [14 :0] dac_Set0
|
||||
,output [14 :0] dac_Set1
|
||||
,output [14 :0] dac_Set2
|
||||
,output [14 :0] dac_Set3
|
||||
,output [14 :0] dac_Set4
|
||||
,output [14 :0] dac_Set5
|
||||
,output [14 :0] dac_Set6
|
||||
,output [14 :0] dac_Set7
|
||||
,output [14 :0] dac_Set8
|
||||
,output [14 :0] dac_Set9
|
||||
,output [14 :0] dac_Set10
|
||||
,output [14 :0] dac_Set11
|
||||
,output [14 :0] dac_Set12
|
||||
,output [14 :0] dac_Set13
|
||||
,output [14 :0] dac_Set14
|
||||
,output [14 :0] dac_Set15
|
||||
,output [2 :0] dac_addr
|
||||
,output [2 :0] dac_dw
|
||||
,output [8 :0] dac_ref
|
||||
,output [16 :0] dac_Prbs_rst0
|
||||
,output [16 :0] dac_Prbs_set0
|
||||
,output [16 :0] dac_Prbs_rst1
|
||||
,output [16 :0] dac_Prbs_set1
|
||||
,output dac_Cal_sig
|
||||
,output dac_Cal_rstn
|
||||
,output Cal_div_rstn
|
||||
,input dac_Cal_end
|
||||
//awg data output
|
||||
,output [15 :0] awg_data_i_o
|
||||
,output [15 :0] awg_data_q_o
|
||||
,output awg_vld_o
|
||||
`ifdef CHANNEL_XY_ON
|
||||
//dsp data output
|
||||
,output [15 :0] xy_dsp_dout0
|
||||
,output [15 :0] xy_dsp_dout1
|
||||
,output [15 :0] xy_dsp_dout2
|
||||
,output [15 :0] xy_dsp_dout3
|
||||
,output [15 :0] xy_dsp_dout4
|
||||
,output [15 :0] xy_dsp_dout5
|
||||
,output [15 :0] xy_dsp_dout6
|
||||
,output [15 :0] xy_dsp_dout7
|
||||
,output [15 :0] xy_dsp_dout8
|
||||
,output [15 :0] xy_dsp_dout9
|
||||
,output [15 :0] xy_dsp_dout10
|
||||
,output [15 :0] xy_dsp_dout11
|
||||
,output [15 :0] xy_dsp_dout12
|
||||
,output [15 :0] xy_dsp_dout13
|
||||
,output [15 :0] xy_dsp_dout14
|
||||
,output [15 :0] xy_dsp_dout15
|
||||
,output xy_dsp_dout_vld
|
||||
`endif
|
||||
`ifdef CHANNEL_Z_ON
|
||||
//Z dsp output
|
||||
,output [15 :0] z_dsp_dout0
|
||||
,output [15 :0] z_dsp_dout1
|
||||
,output [15 :0] z_dsp_dout2
|
||||
,output [15 :0] z_dsp_dout3
|
||||
`endif
|
||||
|
||||
|
||||
);
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------------------------
|
||||
// qbmcu instantiation start
|
||||
//---------------------------------------------------------------------------------------------
|
||||
wire [`QBMCU_PC_SIZE-1 :0] ifu_i_pc_rtvec = 32'h0 ;
|
||||
wire [`QBMCU_PC_SIZE-1 :0] ifu_o_req_pc ;
|
||||
wire ifu_o_req ;
|
||||
wire [`QBMCU_INSTR_SIZE-1:0] ifu_rsp_instr ;
|
||||
|
||||
wire [`QBMCU_ADDR_SIZE-1 :0] agu_o_addr ;
|
||||
wire [`QBMCU_XLEN-1 :0] agu_o_wrdata ;
|
||||
wire agu_o_wren ;
|
||||
wire [`QBMCU_XLEN/8-1 :0] agu_o_wrmask ;
|
||||
wire agu_o_rden ;
|
||||
wire [`QBMCU_XLEN-1 :0] agu_i_rddata ;
|
||||
|
||||
wire ext_o_send ;
|
||||
wire ext_o_sendc ;
|
||||
wire [`QBMCU_XLEN-1 :0] ext_o_codeword ;
|
||||
wire [2 :0] qbmcu_o_fsm_st ;
|
||||
|
||||
qbmcu U_qbmcu (
|
||||
.clk ( clk )
|
||||
,.rst_n ( rst_n )
|
||||
,.qbmcu_i_start ( sync_int )
|
||||
,.qbmcu_o_fsm_st ( qbmcu_o_fsm_st )
|
||||
,.ifu_i_pc_rtvec ( ifu_i_pc_rtvec )
|
||||
,.ifu_o_req_pc ( ifu_o_req_pc )
|
||||
,.ifu_o_req ( ifu_o_req )
|
||||
,.ifu_rsp_instr ( ifu_rsp_instr )
|
||||
,.dec_o_ilegl ( dec_o_ilegl )
|
||||
,.agu_o_addr ( agu_o_addr )
|
||||
,.agu_o_wrdata ( agu_o_wrdata )
|
||||
,.agu_o_wren ( agu_o_wren )
|
||||
,.agu_o_wrmask ( agu_o_wrmask )
|
||||
,.agu_o_rden ( agu_o_rden )
|
||||
,.agu_i_rddata ( agu_i_rddata )
|
||||
,.agu_o_addr_unalgn ( agu_o_addr_unalgn )
|
||||
,.ext_o_send ( ext_o_send )
|
||||
,.ext_o_sendc ( ext_o_sendc )
|
||||
,.ext_o_codeword ( ext_o_codeword )
|
||||
,.ext_o_intr ( mcu_ext_o_intr )
|
||||
);
|
||||
//---------------------------------------------------------------------------------------------
|
||||
// qbmcu instantiation end
|
||||
//---------------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------------------------
|
||||
// MCU runtime counter instantiation start
|
||||
//---------------------------------------------------------------------------------------------
|
||||
defparam qbmcu_runtime.width = 32;
|
||||
//MCU runtime
|
||||
wire [31 :0] run_time ;
|
||||
DW03_updn_ctr qbmcu_runtime (
|
||||
.clk ( clk ) // clock input
|
||||
,.reset ( rst_n ) // asynchronous reset input (active low)
|
||||
,.data ( 32'd0 ) // data used for load operation
|
||||
,.up_dn ( 1'b1 ) // up/down control input (0=down, 1-up)
|
||||
,.load ( ~sync_int ) // load operation control input (active low)
|
||||
,.cen ( |qbmcu_o_fsm_st ) // count enable control input (active high enable)
|
||||
,.count ( run_time ) // count value output
|
||||
,.tercnt ( ) // terminal count output flag (active high)
|
||||
);
|
||||
//---------------------------------------------------------------------------------------------
|
||||
// MCU runtime counter instantiation end
|
||||
//---------------------------------------------------------------------------------------------
|
||||
|
||||
//---------------------------------------------------------------------------------------------
|
||||
// fetch instructions number counter instantiation start
|
||||
//---------------------------------------------------------------------------------------------
|
||||
defparam instrnum.width = 32;
|
||||
//Count the number of fetch instructions
|
||||
wire [31 :0] instr_num ;
|
||||
DW03_updn_ctr instrnum (
|
||||
.clk ( clk ) // clock input
|
||||
,.reset ( rst_n ) // asynchronous reset input (active low)
|
||||
,.data ( 32'd0 ) // data used for load operation
|
||||
,.up_dn ( 1'b1 ) // up/down control input (0=down, 1-up)
|
||||
,.load ( ~sync_int ) // load operation control input (active low)
|
||||
,.cen ( ifu_o_req ) // count enable control input (active high enable)
|
||||
,.count ( instr_num ) // count value output
|
||||
,.tercnt ( ) // terminal count output flag (active high)
|
||||
);
|
||||
//---------------------------------------------------------------------------------------------
|
||||
// fetch instructions number counter instantiation end
|
||||
//---------------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------------------------
|
||||
// qbmcu_busdecoder instantiation start
|
||||
//---------------------------------------------------------------------------------------------
|
||||
|
||||
wire [`QBMCU_ADDR_SIZE-1 :0] dsram_o_rwaddr ;
|
||||
wire [`QBMCU_XLEN-1 :0] dsram_o_wrdata ;
|
||||
wire dsram_o_wren ;
|
||||
wire [`QBMCU_XLEN/8-1 :0] dsram_o_wrmask ;
|
||||
wire dsram_o_rden ;
|
||||
wire [`QBMCU_XLEN-1 :0] dsram_i_rddata ;
|
||||
wire [`QBMCU_ADDR_SIZE-1 :0] preg_o_rwaddr ;
|
||||
wire [`QBMCU_XLEN-1 :0] preg_o_wrdata ;
|
||||
wire preg_o_wren ;
|
||||
wire [`QBMCU_XLEN/8-1 :0] preg_o_wrmask ;
|
||||
wire preg_o_rden ;
|
||||
wire [`QBMCU_XLEN-1 :0] preg_i_rddata ;
|
||||
|
||||
qbmcu_busdecoder #(
|
||||
.S0_BASEADDR ( 32'h0010_0000 )
|
||||
,.S1_BASEADDR ( 32'h0020_0000 )
|
||||
)U_qbmcu_busdecoder (
|
||||
.wren ( agu_o_wren )
|
||||
,.wrmask ( agu_o_wrmask )
|
||||
,.wrdata ( agu_o_wrdata )
|
||||
,.rwaddr ( agu_o_addr )
|
||||
,.rden ( agu_o_rden )
|
||||
,.rddata ( agu_i_rddata )
|
||||
,.s0_wren ( dsram_o_wren )
|
||||
,.s0_wrmask ( dsram_o_wrmask )
|
||||
,.s0_rwaddr ( dsram_o_rwaddr )
|
||||
,.s0_wrdata ( dsram_o_wrdata )
|
||||
,.s0_rden ( dsram_o_rden )
|
||||
,.s0_rddata ( dsram_i_rddata )
|
||||
,.s1_wren ( preg_o_wren )
|
||||
,.s1_wrmask ( preg_o_wrmask )
|
||||
,.s1_rwaddr ( preg_o_rwaddr )
|
||||
,.s1_wrdata ( preg_o_wrdata )
|
||||
,.s1_rden ( preg_o_rden )
|
||||
,.s1_rddata ( preg_i_rddata )
|
||||
);
|
||||
|
||||
//---------------------------------------------------------------------------------------------
|
||||
// qbmcu_busdecoder instantiation end
|
||||
//---------------------------------------------------------------------------------------------
|
||||
|
||||
//---------------------------------------------------------------------------------------------
|
||||
// mcu_regfile instantiation start
|
||||
//---------------------------------------------------------------------------------------------
|
||||
|
||||
//MCU and SPI interface for interaction
|
||||
wire [31 :0] mcu_param [3:0] ; // MCU parameter 0~3
|
||||
wire [31 :0] mcu_result [3:0] ; // MCU result 0~3
|
||||
//lookup table data ;
|
||||
wire [31 :0] mcu_cwfr [3:0] ; // Carrier frequency ctrl word 0~3
|
||||
wire [15 :0] mcu_gapr [7:0] ; // Carrier phase ctrl word 0~3
|
||||
wire [15 :0] mcu_ampr [3:0] ; // Carrier Amplitude 0~3
|
||||
wire [15 :0] mcu_baisr [3:0] ; // Carrier Bais 0~3
|
||||
//CFG Port
|
||||
wire mcu_nco_pha_clr ;
|
||||
wire [15 :0] mcu_rz_pha ;
|
||||
|
||||
wire [1:0] fb_st_in_s;
|
||||
syncer #(2, 2) fb_st_in_syncer (clk, rst_n, fb_st_in, fb_st_in_s);
|
||||
|
||||
mcu_regfile U_mcu_regfile (
|
||||
.clk ( clk )
|
||||
,.rst_n ( rst_n )
|
||||
,.rwaddr ( preg_o_rwaddr[15:0] )
|
||||
,.wrdata ( preg_o_wrdata )
|
||||
,.wren ( preg_o_wren )
|
||||
,.wrmask ( preg_o_wrmask )
|
||||
,.rden ( preg_o_rden )
|
||||
,.rddata ( preg_i_rddata )
|
||||
,.fb_st_info ( fb_st_in_s )
|
||||
,.run_time ( run_time )
|
||||
,.instr_num ( instr_num )
|
||||
,.mcu_param ( mcu_param )
|
||||
,.mcu_result ( mcu_result )
|
||||
,.mcu_cwfr ( mcu_cwfr )
|
||||
,.mcu_gapr ( mcu_gapr )
|
||||
,.mcu_ampr ( mcu_ampr )
|
||||
,.mcu_baisr ( mcu_baisr )
|
||||
,.mcu_nco_pha_clr ( mcu_nco_pha_clr )
|
||||
,.mcu_rz_pha ( mcu_rz_pha )
|
||||
);
|
||||
//---------------------------------------------------------------------------------------------
|
||||
// mcu_regfile instantiation end
|
||||
//---------------------------------------------------------------------------------------------
|
||||
|
||||
//---------------------------------------------------------------------------------------------
|
||||
// U_ITCM instantiation start
|
||||
//---------------------------------------------------------------------------------------------
|
||||
wire itcm_portb_wen = ~itcm_i_wren & itcm_i_rden;
|
||||
wire itcm_portb_cen = ~(itcm_i_wren | itcm_i_rden);
|
||||
dpram #(
|
||||
.DATAWIDTH ( 32 )
|
||||
,.ADDRWIDTH ( 15 )
|
||||
) U_ITCM (
|
||||
.PortClk ( clk )
|
||||
,.PortAAddr ( ifu_o_req_pc[`QBMCU_ITCM_ADDR_SIZE-1:0] )
|
||||
,.PortADataIn ( 32'b0 )
|
||||
,.PortAWriteEnable ( 1'b1 )
|
||||
,.PortAChipEnable ( ~ifu_o_req )
|
||||
,.PortAByteWriteEnable ( 4'b0 )
|
||||
,.PortADataOut ( ifu_rsp_instr )
|
||||
,.PortBAddr ( itcm_i_rwaddr[14:0] )
|
||||
,.PortBDataIn ( itcm_i_wrdata )
|
||||
,.PortBWriteEnable ( itcm_portb_wen )
|
||||
,.PortBChipEnable ( itcm_portb_cen )
|
||||
,.PortBByteWriteEnable ( itcm_i_wrmask )
|
||||
,.PortBDataOut ( itcm_o_rddata )
|
||||
);
|
||||
//---------------------------------------------------------------------------------------------
|
||||
// U_ITCM instantiation end
|
||||
//---------------------------------------------------------------------------------------------
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
//DTCM
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
wire dtcm_portb_wen = ~dtcm_i_wren & dtcm_i_rden;
|
||||
wire dtcm_portb_cen = ~(dtcm_i_wren | dtcm_i_rden);
|
||||
|
||||
dpram #(
|
||||
.DATAWIDTH ( 32 )
|
||||
,.ADDRWIDTH ( 15 )
|
||||
) U_DTCM (
|
||||
.PortClk ( clk )
|
||||
,.PortAAddr ( dsram_o_rwaddr[`QBMCU_DTCM_ADDR_SIZE-1:0] )
|
||||
,.PortADataIn ( dsram_o_wrdata )
|
||||
,.PortAWriteEnable ( ~dsram_o_wren )
|
||||
,.PortAChipEnable ( ~(dsram_o_rden | dsram_o_wren) )
|
||||
,.PortAByteWriteEnable ( ~dsram_o_wrmask )
|
||||
,.PortADataOut ( dsram_i_rddata )
|
||||
,.PortBAddr ( dtcm_i_rwaddr[14:0] )
|
||||
,.PortBDataIn ( dtcm_i_wrdata )
|
||||
,.PortBWriteEnable ( dtcm_portb_wen )
|
||||
,.PortBChipEnable ( dtcm_portb_cen )
|
||||
,.PortBByteWriteEnable ( dtcm_i_wrmask )
|
||||
,.PortBDataOut ( dtcm_o_rddata )
|
||||
);
|
||||
|
||||
//---------------------------------------------------------------------------------------------
|
||||
// ctrl_regfile instantiation start
|
||||
//---------------------------------------------------------------------------------------------
|
||||
wire [1 :0] fb_st_int ;
|
||||
//awg cfg
|
||||
wire mod_sel_sideband ;
|
||||
//DSP cfg
|
||||
wire qam_nco_sclr_en ;
|
||||
wire qam_nco_clr ;
|
||||
wire [47 :0] qam_fcw ;
|
||||
wire [15 :0] qam_pha ;
|
||||
wire [1 :0] qam_mod ;
|
||||
wire qam_sel_sideband ;
|
||||
wire [2 :0] intp_mode ;
|
||||
wire [1 :0] role_sel ;
|
||||
wire [1 :0] dac_mode_sel ;
|
||||
wire enve_read_fsm_st ;
|
||||
|
||||
wire bais_i_ov ;
|
||||
wire bais_q_ov ;
|
||||
wire dout_sel ;
|
||||
|
||||
wire dsp_alwayson ;
|
||||
|
||||
wire mod_dout_sel = dout_sel ;
|
||||
|
||||
|
||||
|
||||
ctrl_regfile U_ctrl_regfile (
|
||||
.clk ( clk )
|
||||
,.rst_n ( rst_n )
|
||||
,.wrdata ( ctrl_wrdata )
|
||||
,.wren ( ctrl_wren )
|
||||
,.rwaddr ( ctrl_rwaddr )
|
||||
,.rden ( ctrl_rden )
|
||||
,.rddata ( ctrl_rddata )
|
||||
,.fb_st_i ( fb_st_in_s )
|
||||
,.run_time ( run_time )
|
||||
,.instr_num ( instr_num )
|
||||
,.bais_i_ov ( bais_i_ov )
|
||||
,.bais_q_ov ( bais_q_ov )
|
||||
,.awg_ctrl_fsm_st ( enve_read_fsm_st )
|
||||
,.mcu_param0 ( mcu_param[0] )
|
||||
,.mcu_param1 ( mcu_param[1] )
|
||||
,.mcu_param2 ( mcu_param[2] )
|
||||
,.mcu_param3 ( mcu_param[3] )
|
||||
,.mcu_result0 ( mcu_result[0] )
|
||||
,.mcu_result1 ( mcu_result[1] )
|
||||
,.mcu_result2 ( mcu_result[2] )
|
||||
,.mcu_result3 ( mcu_result[3] )
|
||||
,.fb_st_o ( fb_st_int )
|
||||
,.mod_sel_sideband ( mod_sel_sideband )
|
||||
,.qam_nco_clr ( qam_nco_clr )
|
||||
,.qam_nco_sclr_en ( qam_nco_sclr_en )
|
||||
,.qam_fcw ( qam_fcw )
|
||||
,.qam_pha ( qam_pha )
|
||||
,.qam_mod ( qam_mod )
|
||||
,.qam_sel_sideband ( qam_sel_sideband )
|
||||
,.intp_mode ( intp_mode )
|
||||
,.role_sel ( role_sel )
|
||||
,.dout_sel ( dout_sel )
|
||||
,.dac_mode_sel ( dac_mode_sel )
|
||||
,.dsp_alwayson ( dsp_alwayson )
|
||||
);
|
||||
//---------------------------------------------------------------------------------------------
|
||||
// ctrl_regfile instantiation end
|
||||
//---------------------------------------------------------------------------------------------
|
||||
|
||||
//---------------------------------------------------------------------------------------------
|
||||
// awg_top instantiation start
|
||||
//---------------------------------------------------------------------------------------------
|
||||
|
||||
wire [15 :0] awg_data_i ;
|
||||
wire [15 :0] awg_data_q ;
|
||||
wire awg_vld ;
|
||||
wire mod_pha_sfot_clr = ~rst_n;
|
||||
|
||||
assign awg_data_i_o = awg_data_i ;
|
||||
assign awg_data_q_o = awg_data_q ;
|
||||
assign awg_vld_o = awg_vld ;
|
||||
|
||||
awg_top U_awg_top (
|
||||
.clk ( clk )
|
||||
,.rst_n ( rst_n )
|
||||
,.mcu_cwfr ( mcu_cwfr )
|
||||
,.mcu_gapr ( mcu_gapr )
|
||||
,.mcu_ampr ( mcu_ampr )
|
||||
,.mcu_baisr ( mcu_baisr )
|
||||
,.mcu_nco_pha_clr ( mcu_nco_pha_clr )
|
||||
,.mcu_rz_pha ( mcu_rz_pha )
|
||||
,.send ( ext_o_send )
|
||||
,.sendc ( ext_o_sendc )
|
||||
,.codeword ( ext_o_codeword )
|
||||
,.fb_st ( fb_st_int )
|
||||
,.enve_bwrdata ( enve_bwrdata )
|
||||
,.enve_bwren ( enve_bwren )
|
||||
,.enve_brwaddr ( enve_brwaddr )
|
||||
,.enve_brden ( enve_brden )
|
||||
,.enve_brddata ( enve_brddata )
|
||||
,.enve_id_bwrdata ( enve_id_bwrdata )
|
||||
,.enve_id_bwren ( enve_id_bwren )
|
||||
,.enve_id_brwaddr ( enve_id_brwaddr )
|
||||
,.enve_id_brden ( enve_id_brden )
|
||||
,.enve_id_brddata ( enve_id_brddata )
|
||||
,.enve_read_fsm_st ( enve_read_fsm_st )
|
||||
,.proc_cft ( awg_proc_cft )
|
||||
,.mod_sideband_sel ( mod_sel_sideband )
|
||||
,.mod_pha_sfot_clr ( mod_pha_sfot_clr )
|
||||
,.role_sel ( role_sel )
|
||||
,.mod_dout_sel ( mod_dout_sel )
|
||||
,.awg_data_i ( awg_data_i )
|
||||
,.awg_data_q ( awg_data_q )
|
||||
,.awg_vld ( awg_vld )
|
||||
,.bais_i_ov ( bais_i_ov )
|
||||
,.bais_q_ov ( bais_q_ov )
|
||||
);
|
||||
|
||||
//---------------------------------------------------------------------------------------------
|
||||
// awg_top instantiation end
|
||||
//---------------------------------------------------------------------------------------------
|
||||
|
||||
`ifdef CHANNEL_XY_ON
|
||||
//---------------------------------------------------------------------------------------------
|
||||
// xy's dsp instantiation start
|
||||
//---------------------------------------------------------------------------------------------
|
||||
|
||||
wire qam_anco_clr = qam_nco_sclr_en ? ~sync_int : 1'b0;
|
||||
|
||||
wire mix_enable = ~(role_sel[1]);
|
||||
|
||||
xy_dsp U_xy_dsp (
|
||||
.clk ( clk )
|
||||
,.rstn ( rst_n )
|
||||
,.phase_manual_clr ( qam_nco_clr )
|
||||
,.phase_auto_clr ( qam_anco_clr )
|
||||
,.fcw ( qam_fcw )
|
||||
,.pha ( qam_pha )
|
||||
,.qam_mod ( qam_mod )
|
||||
,.sel_sideband ( qam_sel_sideband )
|
||||
,.intp_mode ( intp_mode )
|
||||
,.dac_mode_sel ( dac_mode_sel )
|
||||
,.mix_enable ( mix_enable )
|
||||
,.dsp_alwayson ( dsp_alwayson )
|
||||
,.din_i ( awg_data_i )
|
||||
,.din_q ( awg_data_q )
|
||||
,.din_vld ( awg_vld )
|
||||
,.dout0 ( xy_dsp_dout0 )
|
||||
,.dout1 ( xy_dsp_dout1 )
|
||||
,.dout2 ( xy_dsp_dout2 )
|
||||
,.dout3 ( xy_dsp_dout3 )
|
||||
,.dout4 ( xy_dsp_dout4 )
|
||||
,.dout5 ( xy_dsp_dout5 )
|
||||
,.dout6 ( xy_dsp_dout6 )
|
||||
,.dout7 ( xy_dsp_dout7 )
|
||||
,.dout8 ( xy_dsp_dout8 )
|
||||
,.dout9 ( xy_dsp_dout9 )
|
||||
,.dout10 ( xy_dsp_dout10 )
|
||||
,.dout11 ( xy_dsp_dout11 )
|
||||
,.dout12 ( xy_dsp_dout12 )
|
||||
,.dout13 ( xy_dsp_dout13 )
|
||||
,.dout14 ( xy_dsp_dout14 )
|
||||
,.dout15 ( xy_dsp_dout15 )
|
||||
,.dout_vld ( xy_dsp_dout_vld )
|
||||
);
|
||||
//---------------------------------------------------------------------------------------------
|
||||
// xy's dsp instantiation end
|
||||
//---------------------------------------------------------------------------------------------
|
||||
`endif
|
||||
|
||||
`ifdef CHANNEL_Z_ON
|
||||
//---------------------------------------------------------------------------------------------
|
||||
// z_data_mux instantiation start
|
||||
//---------------------------------------------------------------------------------------------
|
||||
|
||||
wire z_dout_sel = dout_sel;
|
||||
|
||||
|
||||
wire [15:0] z_dsp_data0 = 16'h0000;
|
||||
wire [15:0] z_dsp_data1 = 16'h0000;
|
||||
wire [15:0] z_dsp_data2 = 16'h0000;
|
||||
wire [15:0] z_dsp_data3 = 16'h0000;
|
||||
|
||||
z_data_mux U_z_data_mux (
|
||||
.clk ( clk )
|
||||
,.rst_n ( rst_n )
|
||||
,.sel ( z_dout_sel )
|
||||
,.z_dsp_data0 ( z_dsp_data0 )
|
||||
,.z_dsp_data1 ( z_dsp_data1 )
|
||||
,.z_dsp_data2 ( z_dsp_data2 )
|
||||
,.z_dsp_data3 ( z_dsp_data3 )
|
||||
,.xy_dsp_data0 ( xy_dsp_dout0 )
|
||||
,.xy_dsp_data1 ( xy_dsp_dout1 )
|
||||
,.xy_dsp_data2 ( xy_dsp_dout2 )
|
||||
,.xy_dsp_data3 ( xy_dsp_dout3 )
|
||||
,.mux_data_0 ( z_dsp_dout0 )
|
||||
,.mux_data_1 ( z_dsp_dout1 )
|
||||
,.mux_data_2 ( z_dsp_dout2 )
|
||||
,.mux_data_3 ( z_dsp_dout3 )
|
||||
);
|
||||
|
||||
//---------------------------------------------------------------------------------------------
|
||||
// z_data_mux instantiation end
|
||||
//---------------------------------------------------------------------------------------------
|
||||
`endif
|
||||
|
||||
//---------------------------------------------------------------------------------------------
|
||||
//dac_regfile instantiation start
|
||||
//---------------------------------------------------------------------------------------------
|
||||
|
||||
dac_regfile U_ch0_dac_regfile (
|
||||
.clk ( clk )
|
||||
,.rstn ( rst_n )
|
||||
,.wrdata ( dac_wrdata )
|
||||
,.wren ( dac_wren )
|
||||
,.rwaddr ( dac_rwaddr )
|
||||
,.rden ( dac_rden )
|
||||
,.rddata ( dac_rddata )
|
||||
,.Prbs ( dac_Prbs )
|
||||
,.Set0 ( dac_Set0 )
|
||||
,.Set1 ( dac_Set1 )
|
||||
,.Set2 ( dac_Set2 )
|
||||
,.Set3 ( dac_Set3 )
|
||||
,.Set4 ( dac_Set4 )
|
||||
,.Set5 ( dac_Set5 )
|
||||
,.Set6 ( dac_Set6 )
|
||||
,.Set7 ( dac_Set7 )
|
||||
,.Set8 ( dac_Set8 )
|
||||
,.Set9 ( dac_Set9 )
|
||||
,.Set10 ( dac_Set10 )
|
||||
,.Set11 ( dac_Set11 )
|
||||
,.Set12 ( dac_Set12 )
|
||||
,.Set13 ( dac_Set13 )
|
||||
,.Set14 ( dac_Set14 )
|
||||
,.Set15 ( dac_Set15 )
|
||||
,.Dac_addr ( dac_addr )
|
||||
,.Dac_dw ( dac_dw )
|
||||
,.Dac_ref ( dac_ref )
|
||||
,.Prbs_rst0 ( dac_Prbs_rst0 )
|
||||
,.Prbs_set0 ( dac_Prbs_set0 )
|
||||
,.Prbs_rst1 ( dac_Prbs_rst1 )
|
||||
,.Prbs_set1 ( dac_Prbs_set1 )
|
||||
,.Cal_sig ( dac_Cal_sig )
|
||||
,.Cal_end ( dac_Cal_end )
|
||||
,.Cal_rstn ( dac_Cal_rstn )
|
||||
,.Cal_div_rstn ( Cal_div_rstn )
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
`include "../define/chip_undefine.v"
|
||||
`include "../qubitmcu/qbmcu_undefines.v"
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,69 @@
|
|||
//+FHDR--------------------------------------------------------------------------------------------------------
|
||||
// Company:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// File Name : z_data_mux.v
|
||||
// Department :
|
||||
// Author : PWY
|
||||
// Author's Tel :
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Relese History
|
||||
// Version Date Author Description
|
||||
// 0.1 2024-05-13 PWY debug top-level
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Keywords :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Parameter
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Purpose :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Target Device:
|
||||
// Tool versions:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Reuse Issues
|
||||
// Reset Strategy:
|
||||
// Clock Domains:
|
||||
// Critical Timing:
|
||||
// Asynchronous I/F:
|
||||
// Synthesizable (y/n):
|
||||
// Other:
|
||||
//-FHDR--------------------------------------------------------------------------------------------------------
|
||||
|
||||
module z_data_mux (
|
||||
//system port
|
||||
input clk // System Main Clock
|
||||
,input rst_n // Spi Reset active low
|
||||
//---------------from ctrl regfile------------------------------------
|
||||
,input sel // 1'b0 --> mod modem data; 1'b1 --> mod nco data
|
||||
//Z dsp data
|
||||
,input [15:0] z_dsp_data0
|
||||
,input [15:0] z_dsp_data1
|
||||
,input [15:0] z_dsp_data2
|
||||
,input [15:0] z_dsp_data3
|
||||
//XY dsp data
|
||||
,input [15:0] xy_dsp_data0
|
||||
,input [15:0] xy_dsp_data1
|
||||
,input [15:0] xy_dsp_data2
|
||||
,input [15:0] xy_dsp_data3
|
||||
//mux out data
|
||||
,output [15:0] mux_data_0
|
||||
,output [15:0] mux_data_1
|
||||
,output [15:0] mux_data_2
|
||||
,output [15:0] mux_data_3
|
||||
);
|
||||
|
||||
|
||||
wire [15:0] mux_data_0_w = sel ? xy_dsp_data0 : z_dsp_data0;
|
||||
wire [15:0] mux_data_1_w = sel ? xy_dsp_data1 : z_dsp_data1;
|
||||
wire [15:0] mux_data_2_w = sel ? xy_dsp_data2 : z_dsp_data2;
|
||||
wire [15:0] mux_data_3_w = sel ? xy_dsp_data3 : z_dsp_data3;
|
||||
|
||||
sirv_gnrl_dffr #(16) mux_data_0_dffr (mux_data_0_w , mux_data_0 , clk, rst_n);
|
||||
sirv_gnrl_dffr #(16) mux_data_1_dffr (mux_data_1_w , mux_data_1 , clk, rst_n);
|
||||
sirv_gnrl_dffr #(16) mux_data_2_dffr (mux_data_2_w , mux_data_2 , clk, rst_n);
|
||||
sirv_gnrl_dffr #(16) mux_data_3_dffr (mux_data_3_w , mux_data_3 , clk, rst_n);
|
||||
endmodule
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,363 @@
|
|||
//+FHDR--------------------------------------------------------------------------------------------------------
|
||||
// Company:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// File Name : dacif.v
|
||||
// Department :
|
||||
// Author : PWY
|
||||
// Author's Tel :
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Relese History
|
||||
// Version Date Author Description
|
||||
// 0.4 2024-03-12 PWY
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Keywords :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Parameter
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Purpose :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Target Device:
|
||||
// Tool versions:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Reuse Issues
|
||||
// Reset Strategy:
|
||||
// Clock Domains:
|
||||
// Critical Timing:
|
||||
// Asynchronous I/F:
|
||||
// Synthesizable (y/n):
|
||||
// Other:
|
||||
//-FHDR--------------------------------------------------------------------------------------------------------
|
||||
|
||||
module dacif (
|
||||
input clk
|
||||
,input rstn
|
||||
//DAC mode select
|
||||
,input [1:0] dac_mode_sel //2'b00:NRZ mode;2'b01:MIX mode;
|
||||
//2'b10:2xNRZ mode;2'b00:reserve;
|
||||
,input [2 :0] intp_mode //3'b000:x1;3'b001:x2;3'b010:x4;
|
||||
//3'b011:x8;3'b100:x16;
|
||||
,input din_vld
|
||||
,output dout_vld
|
||||
//mixer data input
|
||||
,input [15:0] din0
|
||||
,input [15:0] din1
|
||||
,input [15:0] din2
|
||||
,input [15:0] din3
|
||||
,input [15:0] din4
|
||||
,input [15:0] din5
|
||||
,input [15:0] din6
|
||||
,input [15:0] din7
|
||||
,input [15:0] din8
|
||||
,input [15:0] din9
|
||||
,input [15:0] din10
|
||||
,input [15:0] din11
|
||||
,input [15:0] din12
|
||||
,input [15:0] din13
|
||||
,input [15:0] din14
|
||||
,input [15:0] din15
|
||||
//data output
|
||||
,output [15:0] dout0
|
||||
,output [15:0] dout1
|
||||
,output [15:0] dout2
|
||||
,output [15:0] dout3
|
||||
,output [15:0] dout4
|
||||
,output [15:0] dout5
|
||||
,output [15:0] dout6
|
||||
,output [15:0] dout7
|
||||
,output [15:0] dout8
|
||||
,output [15:0] dout9
|
||||
,output [15:0] dout10
|
||||
,output [15:0] dout11
|
||||
,output [15:0] dout12
|
||||
,output [15:0] dout13
|
||||
,output [15:0] dout14
|
||||
,output [15:0] dout15
|
||||
);
|
||||
|
||||
////////////////////////////////////////////////////
|
||||
// regs
|
||||
////////////////////////////////////////////////////
|
||||
reg [15:0] dout0_r ;
|
||||
reg [15:0] dout1_r ;
|
||||
reg [15:0] dout2_r ;
|
||||
reg [15:0] dout3_r ;
|
||||
reg [15:0] dout4_r ;
|
||||
reg [15:0] dout5_r ;
|
||||
reg [15:0] dout6_r ;
|
||||
reg [15:0] dout7_r ;
|
||||
reg [15:0] dout8_r ;
|
||||
reg [15:0] dout9_r ;
|
||||
reg [15:0] dout10_r;
|
||||
reg [15:0] dout11_r;
|
||||
reg [15:0] dout12_r;
|
||||
reg [15:0] dout13_r;
|
||||
reg [15:0] dout14_r;
|
||||
reg [15:0] dout15_r;
|
||||
|
||||
reg [15:0] mux_p_0;
|
||||
reg [15:0] mux_p_1;
|
||||
reg [15:0] mux_p_2;
|
||||
reg [15:0] mux_p_3;
|
||||
reg [15:0] mux_p_4;
|
||||
reg [15:0] mux_p_5;
|
||||
reg [15:0] mux_p_6;
|
||||
reg [15:0] mux_p_7;
|
||||
reg [15:0] mux_p_8;
|
||||
reg [15:0] mux_p_9;
|
||||
reg [15:0] mux_p_a;
|
||||
reg [15:0] mux_p_b;
|
||||
reg [15:0] mux_p_c;
|
||||
reg [15:0] mux_p_d;
|
||||
reg [15:0] mux_p_e;
|
||||
reg [15:0] mux_p_f;
|
||||
|
||||
reg [1:0] dacif_vld_dly;
|
||||
////////////////////////////////////////////////////
|
||||
// intp mode select
|
||||
////////////////////////////////////////////////////
|
||||
always@(posedge clk) begin
|
||||
case(intp_mode)
|
||||
3'b000 : begin
|
||||
mux_p_0 <= {~din15[15],din15[14:0]};
|
||||
mux_p_1 <= 16'h8000;
|
||||
mux_p_2 <= 16'h8000;
|
||||
mux_p_3 <= 16'h8000;
|
||||
mux_p_4 <= 16'h8000;
|
||||
mux_p_5 <= 16'h8000;
|
||||
mux_p_6 <= 16'h8000;
|
||||
mux_p_7 <= 16'h8000;
|
||||
mux_p_8 <= 16'h8000;
|
||||
mux_p_9 <= 16'h8000;
|
||||
mux_p_a <= 16'h8000;
|
||||
mux_p_b <= 16'h8000;
|
||||
mux_p_c <= 16'h8000;
|
||||
mux_p_d <= 16'h8000;
|
||||
mux_p_e <= 16'h8000;
|
||||
mux_p_f <= 16'h8000;
|
||||
end
|
||||
3'b001 : begin
|
||||
mux_p_0 <= {~din7[15],din7[14:0]};
|
||||
mux_p_1 <= {~din15[15],din15[14:0]};
|
||||
mux_p_2 <= 16'h8000 ;
|
||||
mux_p_3 <= 16'h8000 ;
|
||||
mux_p_4 <= 16'h8000 ;
|
||||
mux_p_5 <= 16'h8000 ;
|
||||
mux_p_6 <= 16'h8000 ;
|
||||
mux_p_7 <= 16'h8000 ;
|
||||
mux_p_8 <= 16'h8000 ;
|
||||
mux_p_9 <= 16'h8000 ;
|
||||
mux_p_a <= 16'h8000 ;
|
||||
mux_p_b <= 16'h8000 ;
|
||||
mux_p_c <= 16'h8000 ;
|
||||
mux_p_d <= 16'h8000 ;
|
||||
mux_p_e <= 16'h8000 ;
|
||||
mux_p_f <= 16'h8000 ;
|
||||
end
|
||||
3'b010 : begin
|
||||
mux_p_0 <= {~din3[15],din3[14:0]} ;
|
||||
mux_p_1 <= {~din7[15],din7[14:0]} ;
|
||||
mux_p_2 <= {~din11[15],din11[14:0]} ;
|
||||
mux_p_3 <= {~din15[15],din15[14:0]};
|
||||
mux_p_4 <= 16'h8000;
|
||||
mux_p_5 <= 16'h8000;
|
||||
mux_p_6 <= 16'h8000;
|
||||
mux_p_7 <= 16'h8000;
|
||||
mux_p_8 <= 16'h8000;
|
||||
mux_p_9 <= 16'h8000;
|
||||
mux_p_a <= 16'h8000;
|
||||
mux_p_b <= 16'h8000;
|
||||
mux_p_c <= 16'h8000;
|
||||
mux_p_d <= 16'h8000;
|
||||
mux_p_e <= 16'h8000;
|
||||
mux_p_f <= 16'h8000;
|
||||
end
|
||||
3'b011 : begin
|
||||
mux_p_0 <= {~din1[15],din1[14:0]} ;
|
||||
mux_p_1 <= {~din3[15],din3[14:0]} ;
|
||||
mux_p_2 <= {~din5[15],din5[14:0]} ;
|
||||
mux_p_3 <= {~din7[15],din7[14:0]} ;
|
||||
mux_p_4 <= {~din9[15],din9[14:0]} ;
|
||||
mux_p_5 <= {~din11[15],din11[14:0]};
|
||||
mux_p_6 <= {~din13[15],din13[14:0]};
|
||||
mux_p_7 <= {~din15[15],din15[14:0]};
|
||||
mux_p_8 <= 16'h8000 ;
|
||||
mux_p_9 <= 16'h8000 ;
|
||||
mux_p_a <= 16'h8000 ;
|
||||
mux_p_b <= 16'h8000 ;
|
||||
mux_p_c <= 16'h8000 ;
|
||||
mux_p_d <= 16'h8000 ;
|
||||
mux_p_e <= 16'h8000 ;
|
||||
mux_p_f <= 16'h8000 ;
|
||||
end
|
||||
3'b100 : begin
|
||||
mux_p_0 <= {~din0[15],din0[14:0]} ;
|
||||
mux_p_1 <= {~din1[15],din1[14:0]} ;
|
||||
mux_p_2 <= {~din2[15],din2[14:0]} ;
|
||||
mux_p_3 <= {~din3[15],din3[14:0]} ;
|
||||
mux_p_4 <= {~din4[15],din4[14:0]} ;
|
||||
mux_p_5 <= {~din5[15],din5[14:0]} ;
|
||||
mux_p_6 <= {~din6[15],din6[14:0]} ;
|
||||
mux_p_7 <= {~din7[15],din7[14:0]} ;
|
||||
mux_p_8 <= {~din8[15],din8[14:0]} ;
|
||||
mux_p_9 <= {~din9[15],din9[14:0]} ;
|
||||
mux_p_a <= {~din10[15],din10[14:0]};
|
||||
mux_p_b <= {~din11[15],din11[14:0]};
|
||||
mux_p_c <= {~din12[15],din12[14:0]};
|
||||
mux_p_d <= {~din13[15],din13[14:0]};
|
||||
mux_p_e <= {~din14[15],din14[14:0]};
|
||||
mux_p_f <= {~din15[15],din15[14:0]};
|
||||
end
|
||||
default : begin
|
||||
mux_p_0 <= 16'h8000;
|
||||
mux_p_1 <= 16'h8000;
|
||||
mux_p_2 <= 16'h8000;
|
||||
mux_p_3 <= 16'h8000;
|
||||
mux_p_4 <= 16'h8000;
|
||||
mux_p_5 <= 16'h8000;
|
||||
mux_p_6 <= 16'h8000;
|
||||
mux_p_7 <= 16'h8000;
|
||||
mux_p_8 <= 16'h8000;
|
||||
mux_p_9 <= 16'h8000;
|
||||
mux_p_a <= 16'h8000;
|
||||
mux_p_b <= 16'h8000;
|
||||
mux_p_c <= 16'h8000;
|
||||
mux_p_d <= 16'h8000;
|
||||
mux_p_e <= 16'h8000;
|
||||
mux_p_f <= 16'h8000;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
////////////////////////////////////////////////////
|
||||
// mode select
|
||||
////////////////////////////////////////////////////
|
||||
always @(posedge clk or negedge rstn) begin
|
||||
if(rstn == 1'b0) begin
|
||||
dout0_r <= 16'h8000;
|
||||
dout1_r <= 16'h8000;
|
||||
dout2_r <= 16'h8000;
|
||||
dout3_r <= 16'h8000;
|
||||
dout4_r <= 16'h8000;
|
||||
dout5_r <= 16'h8000;
|
||||
dout6_r <= 16'h8000;
|
||||
dout7_r <= 16'h8000;
|
||||
dout8_r <= 16'h8000;
|
||||
dout9_r <= 16'h8000;
|
||||
dout10_r <= 16'h8000;
|
||||
dout11_r <= 16'h8000;
|
||||
dout12_r <= 16'h8000;
|
||||
dout13_r <= 16'h8000;
|
||||
dout14_r <= 16'h8000;
|
||||
dout15_r <= 16'h8000;
|
||||
end
|
||||
else begin
|
||||
case(dac_mode_sel)
|
||||
2'b00 : begin
|
||||
dout0_r <= mux_p_0;
|
||||
dout1_r <= mux_p_1;
|
||||
dout2_r <= mux_p_2;
|
||||
dout3_r <= mux_p_3;
|
||||
dout4_r <= mux_p_4;
|
||||
dout5_r <= mux_p_5;
|
||||
dout6_r <= mux_p_6;
|
||||
dout7_r <= mux_p_7;
|
||||
dout8_r <= mux_p_0;
|
||||
dout9_r <= mux_p_1;
|
||||
dout10_r <= mux_p_2;
|
||||
dout11_r <= mux_p_3;
|
||||
dout12_r <= mux_p_4;
|
||||
dout13_r <= mux_p_5;
|
||||
dout14_r <= mux_p_6;
|
||||
dout15_r <= mux_p_7;
|
||||
end
|
||||
2'b01 : begin
|
||||
dout0_r <= mux_p_0;
|
||||
dout1_r <= mux_p_1;
|
||||
dout2_r <= mux_p_2;
|
||||
dout3_r <= mux_p_3;
|
||||
dout4_r <= mux_p_4;
|
||||
dout5_r <= mux_p_5;
|
||||
dout6_r <= mux_p_6;
|
||||
dout7_r <= mux_p_7;
|
||||
dout8_r <= ~mux_p_0;
|
||||
dout9_r <= ~mux_p_1;
|
||||
dout10_r <= ~mux_p_2;
|
||||
dout11_r <= ~mux_p_3;
|
||||
dout12_r <= ~mux_p_4;
|
||||
dout13_r <= ~mux_p_5;
|
||||
dout14_r <= ~mux_p_6;
|
||||
dout15_r <= ~mux_p_7;
|
||||
end
|
||||
2'b10 : begin
|
||||
dout0_r <= mux_p_0;
|
||||
dout1_r <= mux_p_2;
|
||||
dout2_r <= mux_p_4;
|
||||
dout3_r <= mux_p_6;
|
||||
dout4_r <= mux_p_8;
|
||||
dout5_r <= mux_p_a;
|
||||
dout6_r <= mux_p_c;
|
||||
dout7_r <= mux_p_e;
|
||||
dout8_r <= mux_p_1;
|
||||
dout9_r <= mux_p_3;
|
||||
dout10_r <= mux_p_5;
|
||||
dout11_r <= mux_p_7;
|
||||
dout12_r <= mux_p_9;
|
||||
dout13_r <= mux_p_b;
|
||||
dout14_r <= mux_p_d;
|
||||
dout15_r <= mux_p_f;
|
||||
end
|
||||
2'b11 : begin
|
||||
dout0_r <= mux_p_0;
|
||||
dout1_r <= mux_p_1;
|
||||
dout2_r <= mux_p_2;
|
||||
dout3_r <= mux_p_3;
|
||||
dout4_r <= mux_p_4;
|
||||
dout5_r <= mux_p_5;
|
||||
dout6_r <= mux_p_6;
|
||||
dout7_r <= mux_p_7;
|
||||
dout8_r <= mux_p_8;
|
||||
dout9_r <= mux_p_9;
|
||||
dout10_r <= mux_p_a;
|
||||
dout11_r <= mux_p_b;
|
||||
dout12_r <= mux_p_c;
|
||||
dout13_r <= mux_p_d;
|
||||
dout14_r <= mux_p_e;
|
||||
dout15_r <= mux_p_f;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
assign dout0 = dout0_r ;
|
||||
assign dout1 = dout1_r ;
|
||||
assign dout2 = dout2_r ;
|
||||
assign dout3 = dout3_r ;
|
||||
assign dout4 = dout4_r ;
|
||||
assign dout5 = dout5_r ;
|
||||
assign dout6 = dout6_r ;
|
||||
assign dout7 = dout7_r ;
|
||||
assign dout8 = dout8_r ;
|
||||
assign dout9 = dout9_r ;
|
||||
assign dout10 = dout10_r ;
|
||||
assign dout11 = dout11_r ;
|
||||
assign dout12 = dout12_r ;
|
||||
assign dout13 = dout13_r ;
|
||||
assign dout14 = dout14_r ;
|
||||
assign dout15 = dout15_r ;
|
||||
|
||||
//vld
|
||||
always @(posedge clk or negedge rstn) begin
|
||||
if(rstn == 1'b0) begin
|
||||
dacif_vld_dly <= 2'b0;
|
||||
end
|
||||
else begin
|
||||
dacif_vld_dly <= {dacif_vld_dly[0],din_vld};
|
||||
end
|
||||
end
|
||||
|
||||
assign dout_vld = dacif_vld_dly[1];
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,272 @@
|
|||
//+FHDR--------------------------------------------------------------------------------------------------------
|
||||
// Company:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// File Name : dsp_top.v
|
||||
// Department :
|
||||
// Author : PWY
|
||||
// Author's Tel :
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Relese History
|
||||
// Version Date Author Description
|
||||
// 0.4 2024-03-12 PWY
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Keywords :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Parameter
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Purpose :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Target Device:
|
||||
// Tool versions:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Reuse Issues
|
||||
// Reset Strategy:
|
||||
// Clock Domains:
|
||||
// Critical Timing:
|
||||
// Asynchronous I/F:
|
||||
// Synthesizable (y/n):
|
||||
// Other:
|
||||
//-FHDR--------------------------------------------------------------------------------------------------------
|
||||
module dsp_top (
|
||||
input clk
|
||||
,input rstn
|
||||
,input phase_manual_clr
|
||||
,input phase_auto_clr
|
||||
,input [47:0] fcw
|
||||
,input [15:0] pha
|
||||
,input [1 :0] qam_mod //2'b00:bypass;2'b01:mix;
|
||||
//2'b10:cos;2'b11:sin;
|
||||
,input sel_sideband //1'b0:Upper sideband;1'b1:Lower sideband;
|
||||
,input [2 :0] intp_mode //3'b000:x1;3'b001:x2;3'b010:x4;
|
||||
//3'b011:x8;3'b100:x16;
|
||||
,input [1:0] dac_mode_sel //2'b00:NRZ mode;2'b01:MIX mode;
|
||||
//2'b10:2xNRZ mode;2'b00:reserve;
|
||||
,input [15:0] din_i
|
||||
|
||||
,input [15:0] din_q
|
||||
|
||||
//data output
|
||||
,output [15:0] dout0
|
||||
,output [15:0] dout1
|
||||
,output [15:0] dout2
|
||||
,output [15:0] dout3
|
||||
,output [15:0] dout4
|
||||
,output [15:0] dout5
|
||||
,output [15:0] dout6
|
||||
,output [15:0] dout7
|
||||
,output [15:0] dout8
|
||||
,output [15:0] dout9
|
||||
,output [15:0] dout10
|
||||
,output [15:0] dout11
|
||||
,output [15:0] dout12
|
||||
,output [15:0] dout13
|
||||
,output [15:0] dout14
|
||||
,output [15:0] dout15
|
||||
);
|
||||
|
||||
wire [15:0] dt_i_0;
|
||||
wire [15:0] dt_i_1;
|
||||
wire [15:0] dt_i_2;
|
||||
wire [15:0] dt_i_3;
|
||||
wire [15:0] dt_i_4;
|
||||
wire [15:0] dt_i_5;
|
||||
wire [15:0] dt_i_6;
|
||||
wire [15:0] dt_i_7;
|
||||
wire [15:0] dt_i_8;
|
||||
wire [15:0] dt_i_9;
|
||||
wire [15:0] dt_i_a;
|
||||
wire [15:0] dt_i_b;
|
||||
wire [15:0] dt_i_c;
|
||||
wire [15:0] dt_i_d;
|
||||
wire [15:0] dt_i_e;
|
||||
wire [15:0] dt_i_f;
|
||||
|
||||
wire [15:0] dt_q_0;
|
||||
wire [15:0] dt_q_1;
|
||||
wire [15:0] dt_q_2;
|
||||
wire [15:0] dt_q_3;
|
||||
wire [15:0] dt_q_4;
|
||||
wire [15:0] dt_q_5;
|
||||
wire [15:0] dt_q_6;
|
||||
wire [15:0] dt_q_7;
|
||||
wire [15:0] dt_q_8;
|
||||
wire [15:0] dt_q_9;
|
||||
wire [15:0] dt_q_a;
|
||||
wire [15:0] dt_q_b;
|
||||
wire [15:0] dt_q_c;
|
||||
wire [15:0] dt_q_d;
|
||||
wire [15:0] dt_q_e;
|
||||
wire [15:0] dt_q_f;
|
||||
|
||||
|
||||
DUC4 inst_duc_top_i (
|
||||
.clkl ( clk )
|
||||
,.rstn ( rstn )
|
||||
,.intp_mode ( intp_mode )
|
||||
|
||||
,.din ( din_i )
|
||||
|
||||
,.dout_p0 ( dt_i_0 )
|
||||
,.dout_p1 ( dt_i_1 )
|
||||
,.dout_p2 ( dt_i_2 )
|
||||
,.dout_p3 ( dt_i_3 )
|
||||
,.dout_p4 ( dt_i_4 )
|
||||
,.dout_p5 ( dt_i_5 )
|
||||
,.dout_p6 ( dt_i_6 )
|
||||
,.dout_p7 ( dt_i_7 )
|
||||
,.dout_p8 ( dt_i_8 )
|
||||
,.dout_p9 ( dt_i_9 )
|
||||
,.dout_pa ( dt_i_a )
|
||||
,.dout_pb ( dt_i_b )
|
||||
,.dout_pc ( dt_i_c )
|
||||
,.dout_pd ( dt_i_d )
|
||||
,.dout_pe ( dt_i_e )
|
||||
,.dout_pf ( dt_i_f )
|
||||
);
|
||||
|
||||
|
||||
DUC4 inst_duc_top_q (
|
||||
.clkl ( clk )
|
||||
,.rstn ( rstn )
|
||||
,.intp_mode ( intp_mode )
|
||||
|
||||
,.din ( din_q )
|
||||
|
||||
,.dout_p0 ( dt_q_0 )
|
||||
,.dout_p1 ( dt_q_1 )
|
||||
,.dout_p2 ( dt_q_2 )
|
||||
,.dout_p3 ( dt_q_3 )
|
||||
,.dout_p4 ( dt_q_4 )
|
||||
,.dout_p5 ( dt_q_5 )
|
||||
,.dout_p6 ( dt_q_6 )
|
||||
,.dout_p7 ( dt_q_7 )
|
||||
,.dout_p8 ( dt_q_8 )
|
||||
,.dout_p9 ( dt_q_9 )
|
||||
,.dout_pa ( dt_q_a )
|
||||
,.dout_pb ( dt_q_b )
|
||||
,.dout_pc ( dt_q_c )
|
||||
,.dout_pd ( dt_q_d )
|
||||
,.dout_pe ( dt_q_e )
|
||||
,.dout_pf ( dt_q_f )
|
||||
);
|
||||
|
||||
|
||||
wire [15:0] qam_0;
|
||||
wire [15:0] qam_1;
|
||||
wire [15:0] qam_2;
|
||||
wire [15:0] qam_3;
|
||||
wire [15:0] qam_4;
|
||||
wire [15:0] qam_5;
|
||||
wire [15:0] qam_6;
|
||||
wire [15:0] qam_7;
|
||||
wire [15:0] qam_8;
|
||||
wire [15:0] qam_9;
|
||||
wire [15:0] qam_a;
|
||||
wire [15:0] qam_b;
|
||||
wire [15:0] qam_c;
|
||||
wire [15:0] qam_d;
|
||||
wire [15:0] qam_e;
|
||||
wire [15:0] qam_f;
|
||||
|
||||
QAM_TOP inst_qam_top (
|
||||
.clk ( clk )
|
||||
,.rstn ( rstn )
|
||||
,.phase_manual_clr ( phase_manual_clr )
|
||||
,.phase_auto_clr ( phase_auto_clr )
|
||||
,.fcw ( fcw )
|
||||
,.pha ( pha )
|
||||
,.qam_mod ( qam_mod )
|
||||
,.sel_sideband ( sel_sideband )
|
||||
,.din_i_0 ( dt_i_0 )
|
||||
,.din_i_1 ( dt_i_1 )
|
||||
,.din_i_2 ( dt_i_2 )
|
||||
,.din_i_3 ( dt_i_3 )
|
||||
,.din_i_4 ( dt_i_4 )
|
||||
,.din_i_5 ( dt_i_5 )
|
||||
,.din_i_6 ( dt_i_6 )
|
||||
,.din_i_7 ( dt_i_7 )
|
||||
,.din_i_8 ( dt_i_8 )
|
||||
,.din_i_9 ( dt_i_9 )
|
||||
,.din_i_10 ( dt_i_a )
|
||||
,.din_i_11 ( dt_i_b )
|
||||
,.din_i_12 ( dt_i_c )
|
||||
,.din_i_13 ( dt_i_d )
|
||||
,.din_i_14 ( dt_i_e )
|
||||
,.din_i_15 ( dt_i_f )
|
||||
,.din_q_0 ( dt_q_0 )
|
||||
,.din_q_1 ( dt_q_1 )
|
||||
,.din_q_2 ( dt_q_2 )
|
||||
,.din_q_3 ( dt_q_3 )
|
||||
,.din_q_4 ( dt_q_4 )
|
||||
,.din_q_5 ( dt_q_5 )
|
||||
,.din_q_6 ( dt_q_6 )
|
||||
,.din_q_7 ( dt_q_7 )
|
||||
,.din_q_8 ( dt_q_8 )
|
||||
,.din_q_9 ( dt_q_9 )
|
||||
,.din_q_10 ( dt_q_a )
|
||||
,.din_q_11 ( dt_q_b )
|
||||
,.din_q_12 ( dt_q_c )
|
||||
,.din_q_13 ( dt_q_d )
|
||||
,.din_q_14 ( dt_q_e )
|
||||
,.din_q_15 ( dt_q_f )
|
||||
,.dout_i_0 ( qam_0 )
|
||||
,.dout_i_1 ( qam_1 )
|
||||
,.dout_i_2 ( qam_2 )
|
||||
,.dout_i_3 ( qam_3 )
|
||||
,.dout_i_4 ( qam_4 )
|
||||
,.dout_i_5 ( qam_5 )
|
||||
,.dout_i_6 ( qam_6 )
|
||||
,.dout_i_7 ( qam_7 )
|
||||
,.dout_i_8 ( qam_8 )
|
||||
,.dout_i_9 ( qam_9 )
|
||||
,.dout_i_10 ( qam_a )
|
||||
,.dout_i_11 ( qam_b )
|
||||
,.dout_i_12 ( qam_c )
|
||||
,.dout_i_13 ( qam_d )
|
||||
,.dout_i_14 ( qam_e )
|
||||
,.dout_i_15 ( qam_f )
|
||||
);
|
||||
|
||||
dacif dacif_inst (
|
||||
.clk ( clk )
|
||||
,.rstn ( rstn )
|
||||
,.dac_mode_sel ( dac_mode_sel )
|
||||
,.intp_mode ( intp_mode )
|
||||
,.din0 ( qam_0 )
|
||||
,.din1 ( qam_1 )
|
||||
,.din2 ( qam_2 )
|
||||
,.din3 ( qam_3 )
|
||||
,.din4 ( qam_4 )
|
||||
,.din5 ( qam_5 )
|
||||
,.din6 ( qam_6 )
|
||||
,.din7 ( qam_7 )
|
||||
,.din8 ( qam_8 )
|
||||
,.din9 ( qam_9 )
|
||||
,.din10 ( qam_a )
|
||||
,.din11 ( qam_b )
|
||||
,.din12 ( qam_c )
|
||||
,.din13 ( qam_d )
|
||||
,.din14 ( qam_e )
|
||||
,.din15 ( qam_f )
|
||||
,.dout0 ( dout0 )
|
||||
,.dout1 ( dout1 )
|
||||
,.dout2 ( dout2 )
|
||||
,.dout3 ( dout3 )
|
||||
,.dout4 ( dout4 )
|
||||
,.dout5 ( dout5 )
|
||||
,.dout6 ( dout6 )
|
||||
,.dout7 ( dout7 )
|
||||
,.dout8 ( dout8 )
|
||||
,.dout9 ( dout9 )
|
||||
,.dout10 ( dout10 )
|
||||
,.dout11 ( dout11 )
|
||||
,.dout12 ( dout12 )
|
||||
,.dout13 ( dout13 )
|
||||
,.dout14 ( dout14 )
|
||||
,.dout15 ( dout15 )
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,303 @@
|
|||
//+FHDR--------------------------------------------------------------------------------------------------------
|
||||
// Company:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// File Name : XY_dsp.v
|
||||
// Department :
|
||||
// Author : PWY
|
||||
// Author's Tel :
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Relese History
|
||||
// Version Date Author Description
|
||||
// 0.4 2024-03-12 PWY
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Keywords :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Parameter
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Purpose :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Target Device:
|
||||
// Tool versions:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Reuse Issues
|
||||
// Reset Strategy:
|
||||
// Clock Domains:
|
||||
// Critical Timing:
|
||||
// Asynchronous I/F:
|
||||
// Synthesizable (y/n):
|
||||
// Other:
|
||||
//-FHDR--------------------------------------------------------------------------------------------------------
|
||||
module xy_dsp (
|
||||
input clk
|
||||
,input rstn
|
||||
,input phase_manual_clr
|
||||
,input phase_auto_clr
|
||||
|
||||
,input [47:0] fcw
|
||||
,input [15:0] pha
|
||||
,input [1 :0] qam_mod //2'b00:bypass;2'b01:mix;
|
||||
//2'b10:cos;2'b11:sin;
|
||||
,input sel_sideband //1'b0:Upper sideband;1'b1:Lower sideband;
|
||||
,input [2 :0] intp_mode //3'b000:x1;3'b001:x2;3'b010:x4;
|
||||
//3'b011:x8;3'b100:x16;
|
||||
,input [1 :0] dac_mode_sel //2'b00:NRZ mode;2'b01:MIX mode;
|
||||
//2'b10:2xNRZ mode;2'b00:reserve;
|
||||
,input mix_enable
|
||||
|
||||
,input dsp_alwayson
|
||||
|
||||
,input [15:0] din_i
|
||||
|
||||
,input [15:0] din_q
|
||||
,input din_vld
|
||||
//data output
|
||||
,output [15:0] dout0
|
||||
,output [15:0] dout1
|
||||
,output [15:0] dout2
|
||||
,output [15:0] dout3
|
||||
,output [15:0] dout4
|
||||
,output [15:0] dout5
|
||||
,output [15:0] dout6
|
||||
,output [15:0] dout7
|
||||
,output [15:0] dout8
|
||||
,output [15:0] dout9
|
||||
,output [15:0] dout10
|
||||
,output [15:0] dout11
|
||||
,output [15:0] dout12
|
||||
,output [15:0] dout13
|
||||
,output [15:0] dout14
|
||||
,output [15:0] dout15
|
||||
,output dout_vld
|
||||
);
|
||||
|
||||
wire [15:0] dt_i_0;
|
||||
wire [15:0] dt_i_1;
|
||||
wire [15:0] dt_i_2;
|
||||
wire [15:0] dt_i_3;
|
||||
wire [15:0] dt_i_4;
|
||||
wire [15:0] dt_i_5;
|
||||
wire [15:0] dt_i_6;
|
||||
wire [15:0] dt_i_7;
|
||||
wire [15:0] dt_i_8;
|
||||
wire [15:0] dt_i_9;
|
||||
wire [15:0] dt_i_a;
|
||||
wire [15:0] dt_i_b;
|
||||
wire [15:0] dt_i_c;
|
||||
wire [15:0] dt_i_d;
|
||||
wire [15:0] dt_i_e;
|
||||
wire [15:0] dt_i_f;
|
||||
|
||||
wire [15:0] dt_q_0;
|
||||
wire [15:0] dt_q_1;
|
||||
wire [15:0] dt_q_2;
|
||||
wire [15:0] dt_q_3;
|
||||
wire [15:0] dt_q_4;
|
||||
wire [15:0] dt_q_5;
|
||||
wire [15:0] dt_q_6;
|
||||
wire [15:0] dt_q_7;
|
||||
wire [15:0] dt_q_8;
|
||||
wire [15:0] dt_q_9;
|
||||
wire [15:0] dt_q_a;
|
||||
wire [15:0] dt_q_b;
|
||||
wire [15:0] dt_q_c;
|
||||
wire [15:0] dt_q_d;
|
||||
wire [15:0] dt_q_e;
|
||||
wire [15:0] dt_q_f;
|
||||
|
||||
//DUC valid signal
|
||||
wire dout_vld_duc_i;
|
||||
wire dout_vld_duc_q;
|
||||
|
||||
//mix valid signal
|
||||
wire dout_vld_mix;
|
||||
|
||||
|
||||
|
||||
|
||||
DUC4 inst_duc_top_i (
|
||||
.clkl ( clk )
|
||||
,.rstn ( rstn )
|
||||
,.intp_mode ( intp_mode )
|
||||
,.dsp_alwayson ( dsp_alwayson )
|
||||
,.din ( din_i )
|
||||
|
||||
,.data_vldi ( din_vld )
|
||||
,.data_vldo ( dout_vld_duc_i )
|
||||
|
||||
,.dout_p0 ( dt_i_0 )
|
||||
,.dout_p1 ( dt_i_1 )
|
||||
,.dout_p2 ( dt_i_2 )
|
||||
,.dout_p3 ( dt_i_3 )
|
||||
,.dout_p4 ( dt_i_4 )
|
||||
,.dout_p5 ( dt_i_5 )
|
||||
,.dout_p6 ( dt_i_6 )
|
||||
,.dout_p7 ( dt_i_7 )
|
||||
,.dout_p8 ( dt_i_8 )
|
||||
,.dout_p9 ( dt_i_9 )
|
||||
,.dout_pa ( dt_i_a )
|
||||
,.dout_pb ( dt_i_b )
|
||||
,.dout_pc ( dt_i_c )
|
||||
,.dout_pd ( dt_i_d )
|
||||
,.dout_pe ( dt_i_e )
|
||||
,.dout_pf ( dt_i_f )
|
||||
);
|
||||
|
||||
|
||||
DUC4 inst_duc_top_q (
|
||||
.clkl ( clk )
|
||||
,.rstn ( rstn )
|
||||
,.intp_mode ( intp_mode )
|
||||
,.dsp_alwayson ( dsp_alwayson )
|
||||
,.din ( din_q )
|
||||
|
||||
,.data_vldi ( din_vld )
|
||||
,.data_vldo ( dout_vld_duc_q )
|
||||
|
||||
,.dout_p0 ( dt_q_0 )
|
||||
,.dout_p1 ( dt_q_1 )
|
||||
,.dout_p2 ( dt_q_2 )
|
||||
,.dout_p3 ( dt_q_3 )
|
||||
,.dout_p4 ( dt_q_4 )
|
||||
,.dout_p5 ( dt_q_5 )
|
||||
,.dout_p6 ( dt_q_6 )
|
||||
,.dout_p7 ( dt_q_7 )
|
||||
,.dout_p8 ( dt_q_8 )
|
||||
,.dout_p9 ( dt_q_9 )
|
||||
,.dout_pa ( dt_q_a )
|
||||
,.dout_pb ( dt_q_b )
|
||||
,.dout_pc ( dt_q_c )
|
||||
,.dout_pd ( dt_q_d )
|
||||
,.dout_pe ( dt_q_e )
|
||||
,.dout_pf ( dt_q_f )
|
||||
);
|
||||
|
||||
|
||||
wire [15:0] qam_0;
|
||||
wire [15:0] qam_1;
|
||||
wire [15:0] qam_2;
|
||||
wire [15:0] qam_3;
|
||||
wire [15:0] qam_4;
|
||||
wire [15:0] qam_5;
|
||||
wire [15:0] qam_6;
|
||||
wire [15:0] qam_7;
|
||||
wire [15:0] qam_8;
|
||||
wire [15:0] qam_9;
|
||||
wire [15:0] qam_a;
|
||||
wire [15:0] qam_b;
|
||||
wire [15:0] qam_c;
|
||||
wire [15:0] qam_d;
|
||||
wire [15:0] qam_e;
|
||||
wire [15:0] qam_f;
|
||||
|
||||
QAM_TOP inst_qam_top (
|
||||
.clk ( clk )
|
||||
,.rstn ( rstn )
|
||||
,.phase_manual_clr ( phase_manual_clr )
|
||||
,.phase_auto_clr ( phase_auto_clr )
|
||||
,.fcw ( fcw )
|
||||
,.pha ( pha )
|
||||
,.qam_mod ( qam_mod )
|
||||
,.sel_sideband ( sel_sideband )
|
||||
|
||||
,.mix_enable ( mix_enable )
|
||||
,.din_vld ( dout_vld_duc_i & dout_vld_duc_q )
|
||||
,.dout_vld ( dout_vld_mix )
|
||||
|
||||
,.din_i_0 ( dt_i_0 )
|
||||
,.din_i_1 ( dt_i_1 )
|
||||
,.din_i_2 ( dt_i_2 )
|
||||
,.din_i_3 ( dt_i_3 )
|
||||
,.din_i_4 ( dt_i_4 )
|
||||
,.din_i_5 ( dt_i_5 )
|
||||
,.din_i_6 ( dt_i_6 )
|
||||
,.din_i_7 ( dt_i_7 )
|
||||
,.din_i_8 ( dt_i_8 )
|
||||
,.din_i_9 ( dt_i_9 )
|
||||
,.din_i_10 ( dt_i_a )
|
||||
,.din_i_11 ( dt_i_b )
|
||||
,.din_i_12 ( dt_i_c )
|
||||
,.din_i_13 ( dt_i_d )
|
||||
,.din_i_14 ( dt_i_e )
|
||||
,.din_i_15 ( dt_i_f )
|
||||
,.din_q_0 ( dt_q_0 )
|
||||
,.din_q_1 ( dt_q_1 )
|
||||
,.din_q_2 ( dt_q_2 )
|
||||
,.din_q_3 ( dt_q_3 )
|
||||
,.din_q_4 ( dt_q_4 )
|
||||
,.din_q_5 ( dt_q_5 )
|
||||
,.din_q_6 ( dt_q_6 )
|
||||
,.din_q_7 ( dt_q_7 )
|
||||
,.din_q_8 ( dt_q_8 )
|
||||
,.din_q_9 ( dt_q_9 )
|
||||
,.din_q_10 ( dt_q_a )
|
||||
,.din_q_11 ( dt_q_b )
|
||||
,.din_q_12 ( dt_q_c )
|
||||
,.din_q_13 ( dt_q_d )
|
||||
,.din_q_14 ( dt_q_e )
|
||||
,.din_q_15 ( dt_q_f )
|
||||
,.dout_i_0 ( qam_0 )
|
||||
,.dout_i_1 ( qam_1 )
|
||||
,.dout_i_2 ( qam_2 )
|
||||
,.dout_i_3 ( qam_3 )
|
||||
,.dout_i_4 ( qam_4 )
|
||||
,.dout_i_5 ( qam_5 )
|
||||
,.dout_i_6 ( qam_6 )
|
||||
,.dout_i_7 ( qam_7 )
|
||||
,.dout_i_8 ( qam_8 )
|
||||
,.dout_i_9 ( qam_9 )
|
||||
,.dout_i_10 ( qam_a )
|
||||
,.dout_i_11 ( qam_b )
|
||||
,.dout_i_12 ( qam_c )
|
||||
,.dout_i_13 ( qam_d )
|
||||
,.dout_i_14 ( qam_e )
|
||||
,.dout_i_15 ( qam_f )
|
||||
);
|
||||
|
||||
dacif dacif_inst (
|
||||
.clk ( clk )
|
||||
,.rstn ( rstn )
|
||||
,.dac_mode_sel ( dac_mode_sel )
|
||||
,.intp_mode ( intp_mode )
|
||||
|
||||
,.din_vld ( dout_vld_mix )
|
||||
,.dout_vld ( dout_vld )
|
||||
|
||||
,.din0 ( qam_0 )
|
||||
,.din1 ( qam_1 )
|
||||
,.din2 ( qam_2 )
|
||||
,.din3 ( qam_3 )
|
||||
,.din4 ( qam_4 )
|
||||
,.din5 ( qam_5 )
|
||||
,.din6 ( qam_6 )
|
||||
,.din7 ( qam_7 )
|
||||
,.din8 ( qam_8 )
|
||||
,.din9 ( qam_9 )
|
||||
,.din10 ( qam_a )
|
||||
,.din11 ( qam_b )
|
||||
,.din12 ( qam_c )
|
||||
,.din13 ( qam_d )
|
||||
,.din14 ( qam_e )
|
||||
,.din15 ( qam_f )
|
||||
,.dout0 ( dout0 )
|
||||
,.dout1 ( dout1 )
|
||||
,.dout2 ( dout2 )
|
||||
,.dout3 ( dout3 )
|
||||
,.dout4 ( dout4 )
|
||||
,.dout5 ( dout5 )
|
||||
,.dout6 ( dout6 )
|
||||
,.dout7 ( dout7 )
|
||||
,.dout8 ( dout8 )
|
||||
,.dout9 ( dout9 )
|
||||
,.dout10 ( dout10 )
|
||||
,.dout11 ( dout11 )
|
||||
,.dout12 ( dout12 )
|
||||
,.dout13 ( dout13 )
|
||||
,.dout14 ( dout14 )
|
||||
,.dout15 ( dout15 )
|
||||
);
|
||||
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,321 @@
|
|||
module DUC4(
|
||||
input clkl
|
||||
,input rstn
|
||||
,input [2 :0] intp_mode //3'b000:x1;3'b001:x2;3'b010:x4;3'b011:x8;3'b100:x16;
|
||||
,input dsp_alwayson
|
||||
,input data_vldi
|
||||
,input [15:0] din
|
||||
,output [15:0] dout_p0
|
||||
,output [15:0] dout_p1
|
||||
,output [15:0] dout_p2
|
||||
,output [15:0] dout_p3
|
||||
,output [15:0] dout_p4
|
||||
,output [15:0] dout_p5
|
||||
,output [15:0] dout_p6
|
||||
,output [15:0] dout_p7
|
||||
,output [15:0] dout_p8
|
||||
,output [15:0] dout_p9
|
||||
,output [15:0] dout_pa
|
||||
,output [15:0] dout_pb
|
||||
,output [15:0] dout_pc
|
||||
,output [15:0] dout_pd
|
||||
,output [15:0] dout_pe
|
||||
,output [15:0] dout_pf
|
||||
,output data_vldo
|
||||
);
|
||||
|
||||
wire [15:0] dt1_p_0;
|
||||
wire [15:0] dt1_p_1;
|
||||
|
||||
wire [15:0] dt2_p_0;
|
||||
wire [15:0] dt2_p_1;
|
||||
wire [15:0] dt2_p_2;
|
||||
wire [15:0] dt2_p_3;
|
||||
|
||||
wire [15:0] dt3_p_0;
|
||||
wire [15:0] dt3_p_1;
|
||||
wire [15:0] dt3_p_2;
|
||||
wire [15:0] dt3_p_3;
|
||||
wire [15:0] dt3_p_4;
|
||||
wire [15:0] dt3_p_5;
|
||||
wire [15:0] dt3_p_6;
|
||||
wire [15:0] dt3_p_7;
|
||||
|
||||
wire [15:0] dt4_p_0;
|
||||
wire [15:0] dt4_p_1;
|
||||
wire [15:0] dt4_p_2;
|
||||
wire [15:0] dt4_p_3;
|
||||
wire [15:0] dt4_p_4;
|
||||
wire [15:0] dt4_p_5;
|
||||
wire [15:0] dt4_p_6;
|
||||
wire [15:0] dt4_p_7;
|
||||
wire [15:0] dt4_p_8;
|
||||
wire [15:0] dt4_p_9;
|
||||
wire [15:0] dt4_p_a;
|
||||
wire [15:0] dt4_p_b;
|
||||
wire [15:0] dt4_p_c;
|
||||
wire [15:0] dt4_p_d;
|
||||
wire [15:0] dt4_p_e;
|
||||
wire [15:0] dt4_p_f;
|
||||
|
||||
reg [15:0] mux_p_0;
|
||||
reg [15:0] mux_p_1;
|
||||
reg [15:0] mux_p_2;
|
||||
reg [15:0] mux_p_3;
|
||||
reg [15:0] mux_p_4;
|
||||
reg [15:0] mux_p_5;
|
||||
reg [15:0] mux_p_6;
|
||||
reg [15:0] mux_p_7;
|
||||
reg [15:0] mux_p_8;
|
||||
reg [15:0] mux_p_9;
|
||||
reg [15:0] mux_p_a;
|
||||
reg [15:0] mux_p_b;
|
||||
reg [15:0] mux_p_c;
|
||||
reg [15:0] mux_p_d;
|
||||
reg [15:0] mux_p_e;
|
||||
reg [15:0] mux_p_f;
|
||||
|
||||
reg [70:0] DUC4_data_vld_r;
|
||||
|
||||
always@(posedge clkl or negedge rstn)
|
||||
if(!rstn)
|
||||
begin
|
||||
DUC4_data_vld_r <= 9'b0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
DUC4_data_vld_r <= {DUC4_data_vld_r[70:0], data_vldi};
|
||||
end
|
||||
|
||||
///////////////////////////////////////////////////////
|
||||
//DUC_HB1_TOP inst
|
||||
///////////////////////////////////////////////////////
|
||||
DUC_HB1_TOP U0_DUC_HB1_TOP (
|
||||
.clkl ( clkl )
|
||||
,.rstn ( rstn )
|
||||
,.din ( din )
|
||||
,.dout_p0 ( dt1_p_0 )
|
||||
,.dout_p1 ( dt1_p_1 )
|
||||
);
|
||||
|
||||
|
||||
///////////////////////////////////////////////////////
|
||||
//DUC_HB2_TOP_S inst1
|
||||
///////////////////////////////////////////////////////
|
||||
|
||||
DUC_HB2_TOP_S U1_DUC_HB2_TOP (
|
||||
.clkl ( clkl )
|
||||
,.rstn ( rstn )
|
||||
,.din0 ( dt1_p_1 )
|
||||
,.din1 ( dt1_p_0 )
|
||||
,.dout_p0 ( dt2_p_0 )
|
||||
,.dout_p1 ( dt2_p_1 )
|
||||
,.dout_p2 ( dt2_p_2 )
|
||||
,.dout_p3 ( dt2_p_3 )
|
||||
);
|
||||
|
||||
///////////////////////////////////////////////////////
|
||||
//DUC_HB3_TOP_S2 inst1
|
||||
///////////////////////////////////////////////////////
|
||||
|
||||
DUC_HB3_TOP_S2 U1_DUC_HB3_TOP (
|
||||
.clkl ( clkl )
|
||||
,.rstn ( rstn )
|
||||
,.din0 ( dt2_p_2 )
|
||||
,.din1 ( dt2_p_3 )
|
||||
,.din2 ( dt2_p_0 )
|
||||
,.din3 ( dt2_p_1 )
|
||||
,.dout_p0 ( dt3_p_0 )
|
||||
,.dout_p1 ( dt3_p_1 )
|
||||
,.dout_p2 ( dt3_p_2 )
|
||||
,.dout_p3 ( dt3_p_3 )
|
||||
,.dout_p4 ( dt3_p_4 )
|
||||
,.dout_p5 ( dt3_p_5 )
|
||||
,.dout_p6 ( dt3_p_6 )
|
||||
,.dout_p7 ( dt3_p_7 )
|
||||
);
|
||||
|
||||
///////////////////////////////////////////////////////
|
||||
//DUC_HB4_TOP_S3 inst1
|
||||
///////////////////////////////////////////////////////
|
||||
|
||||
DUC_HB4_TOP_S3 U1_DUC_HB4_TOP (
|
||||
.clkl ( clkl )
|
||||
,.rstn ( rstn )
|
||||
,.din0 ( dt3_p_6 )
|
||||
,.din1 ( dt3_p_7 )
|
||||
,.din2 ( dt3_p_4 )
|
||||
,.din3 ( dt3_p_5 )
|
||||
,.din4 ( dt3_p_2 )
|
||||
,.din5 ( dt3_p_3 )
|
||||
,.din6 ( dt3_p_0 )
|
||||
,.din7 ( dt3_p_1 )
|
||||
,.dout_p0 ( dt4_p_0 )
|
||||
,.dout_p1 ( dt4_p_1 )
|
||||
,.dout_p2 ( dt4_p_2 )
|
||||
,.dout_p3 ( dt4_p_3 )
|
||||
,.dout_p4 ( dt4_p_4 )
|
||||
,.dout_p5 ( dt4_p_5 )
|
||||
,.dout_p6 ( dt4_p_6 )
|
||||
,.dout_p7 ( dt4_p_7 )
|
||||
,.dout_p8 ( dt4_p_8 )
|
||||
,.dout_p9 ( dt4_p_9 )
|
||||
,.dout_pa ( dt4_p_a )
|
||||
,.dout_pb ( dt4_p_b )
|
||||
,.dout_pc ( dt4_p_c )
|
||||
,.dout_pd ( dt4_p_d )
|
||||
,.dout_pe ( dt4_p_e )
|
||||
,.dout_pf ( dt4_p_f )
|
||||
);
|
||||
|
||||
always@(posedge clkl) begin
|
||||
case(intp_mode)
|
||||
3'b000 : begin
|
||||
mux_p_0 <= din;
|
||||
mux_p_1 <= 16'h0;
|
||||
mux_p_2 <= 16'h0;
|
||||
mux_p_3 <= 16'h0;
|
||||
mux_p_4 <= 16'h0;
|
||||
mux_p_5 <= 16'h0;
|
||||
mux_p_6 <= 16'h0;
|
||||
mux_p_7 <= 16'h0;
|
||||
mux_p_8 <= 16'h0;
|
||||
mux_p_9 <= 16'h0;
|
||||
mux_p_a <= 16'h0;
|
||||
mux_p_b <= 16'h0;
|
||||
mux_p_c <= 16'h0;
|
||||
mux_p_d <= 16'h0;
|
||||
mux_p_e <= 16'h0;
|
||||
mux_p_f <= 16'h0;
|
||||
end
|
||||
3'b001 : begin
|
||||
mux_p_0 <= dt1_p_0;
|
||||
mux_p_1 <= 16'h0;
|
||||
mux_p_2 <= 16'h0;
|
||||
mux_p_3 <= 16'h0;
|
||||
mux_p_4 <= 16'h0;
|
||||
mux_p_5 <= 16'h0;
|
||||
mux_p_6 <= 16'h0;
|
||||
mux_p_7 <= 16'h0;
|
||||
mux_p_8 <= dt1_p_1;
|
||||
mux_p_9 <= 16'h0;
|
||||
mux_p_a <= 16'h0;
|
||||
mux_p_b <= 16'h0;
|
||||
mux_p_c <= 16'h0;
|
||||
mux_p_d <= 16'h0;
|
||||
mux_p_e <= 16'h0;
|
||||
mux_p_f <= 16'h0;
|
||||
end
|
||||
3'b010 : begin
|
||||
mux_p_0 <= dt2_p_1;
|
||||
mux_p_1 <= 16'h0;
|
||||
mux_p_2 <= 16'h0;
|
||||
mux_p_3 <= 16'h0;
|
||||
mux_p_4 <= dt2_p_0;
|
||||
mux_p_5 <= 16'h0;
|
||||
mux_p_6 <= 16'h0;
|
||||
mux_p_7 <= 16'h0;
|
||||
mux_p_8 <= dt2_p_3;
|
||||
mux_p_9 <= 16'h0;
|
||||
mux_p_a <= 16'h0;
|
||||
mux_p_b <= 16'h0;
|
||||
mux_p_c <= dt2_p_2;
|
||||
mux_p_d <= 16'h0;
|
||||
mux_p_e <= 16'h0;
|
||||
mux_p_f <= 16'h0;
|
||||
end
|
||||
3'b011 : begin
|
||||
mux_p_0 <= dt3_p_1;
|
||||
mux_p_1 <= 16'h0;
|
||||
mux_p_2 <= dt3_p_0;
|
||||
mux_p_3 <= 16'h0;
|
||||
mux_p_4 <= dt3_p_3;
|
||||
mux_p_5 <= 16'h0;
|
||||
mux_p_6 <= dt3_p_2;
|
||||
mux_p_7 <= 16'h0;
|
||||
mux_p_8 <= dt3_p_5;
|
||||
mux_p_9 <= 16'h0;
|
||||
mux_p_a <= dt3_p_4;
|
||||
mux_p_b <= 16'h0;
|
||||
mux_p_c <= dt3_p_7;
|
||||
mux_p_d <= 16'h0;
|
||||
mux_p_e <= dt3_p_6;
|
||||
mux_p_f <= 16'h0;
|
||||
end
|
||||
3'b100 : begin
|
||||
mux_p_0 <= dt4_p_1;
|
||||
mux_p_1 <= dt4_p_0;
|
||||
mux_p_2 <= dt4_p_3;
|
||||
mux_p_3 <= dt4_p_2;
|
||||
mux_p_4 <= dt4_p_5;
|
||||
mux_p_5 <= dt4_p_4;
|
||||
mux_p_6 <= dt4_p_7;
|
||||
mux_p_7 <= dt4_p_6;
|
||||
mux_p_8 <= dt4_p_9;
|
||||
mux_p_9 <= dt4_p_8;
|
||||
mux_p_a <= dt4_p_b;
|
||||
mux_p_b <= dt4_p_a;
|
||||
mux_p_c <= dt4_p_d;
|
||||
mux_p_d <= dt4_p_c;
|
||||
mux_p_e <= dt4_p_f;
|
||||
mux_p_f <= dt4_p_e;
|
||||
end
|
||||
default : begin
|
||||
mux_p_0 <= 16'h0;
|
||||
mux_p_1 <= 16'h0;
|
||||
mux_p_2 <= 16'h0;
|
||||
mux_p_3 <= 16'h0;
|
||||
mux_p_4 <= 16'h0;
|
||||
mux_p_5 <= 16'h0;
|
||||
mux_p_6 <= 16'h0;
|
||||
mux_p_7 <= 16'h0;
|
||||
mux_p_8 <= 16'h0;
|
||||
mux_p_9 <= 16'h0;
|
||||
mux_p_a <= 16'h0;
|
||||
mux_p_b <= 16'h0;
|
||||
mux_p_c <= 16'h0;
|
||||
mux_p_d <= 16'h0;
|
||||
mux_p_e <= 16'h0;
|
||||
mux_p_f <= 16'h0;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
assign dout_p0 = mux_p_f ;
|
||||
assign dout_p1 = mux_p_e ;
|
||||
assign dout_p2 = mux_p_d ;
|
||||
assign dout_p3 = mux_p_c ;
|
||||
assign dout_p4 = mux_p_b ;
|
||||
assign dout_p5 = mux_p_a ;
|
||||
assign dout_p6 = mux_p_9 ;
|
||||
assign dout_p7 = mux_p_8 ;
|
||||
assign dout_p8 = mux_p_7 ;
|
||||
assign dout_p9 = mux_p_6 ;
|
||||
assign dout_pa = mux_p_5 ;
|
||||
assign dout_pb = mux_p_4 ;
|
||||
assign dout_pc = mux_p_3 ;
|
||||
assign dout_pd = mux_p_2 ;
|
||||
assign dout_pe = mux_p_1 ;
|
||||
assign dout_pf = mux_p_0 ;
|
||||
|
||||
reg data_vldo_t;
|
||||
|
||||
always@(posedge clkl) begin
|
||||
if(dsp_alwayson) begin
|
||||
data_vldo_t <= 1'b1;
|
||||
end
|
||||
else begin
|
||||
case(intp_mode)
|
||||
3'b000 : data_vldo_t <= data_vldi;
|
||||
3'b001 : data_vldo_t <= DUC4_data_vld_r[21];
|
||||
3'b010 : data_vldo_t <= DUC4_data_vld_r[28];
|
||||
3'b011 : data_vldo_t <= DUC4_data_vld_r[33];
|
||||
3'b100 : data_vldo_t <= DUC4_data_vld_r[37];
|
||||
default : data_vldo_t <= data_vldi;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
assign data_vldo = data_vldo_t;
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,595 @@
|
|||
//+FHDR--------------------------------------------------------------------------------------------------------
|
||||
// Company:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// File Name : duc_hb1_shift.v
|
||||
// Department :
|
||||
// Author :
|
||||
// Author's Tel :
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Relese History
|
||||
// Version Date Author Description
|
||||
// 0.8 2024-03-26 thfu add pipeline
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Keywords :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Parameter
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Purpose :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Target Device:
|
||||
// Tool versions:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Reuse Issues
|
||||
// Reset Strategy:
|
||||
// Clock Domains:
|
||||
// Critical Timing:
|
||||
// Asynchronous I/F:
|
||||
// Synthesizable (y/n):
|
||||
// Other:
|
||||
//-FHDR--------------------------------------------------------------------------------------------------------
|
||||
|
||||
module DUC_HB1 (
|
||||
clk,
|
||||
rstn,
|
||||
din_0,
|
||||
din_1,
|
||||
din_2,
|
||||
din_3,
|
||||
din_4,
|
||||
din_5,
|
||||
din_6,
|
||||
din_7,
|
||||
din_8,
|
||||
din_9,
|
||||
din_10,
|
||||
din_11,
|
||||
din_12,
|
||||
din_13,
|
||||
din_14,
|
||||
din_15,
|
||||
din_16,
|
||||
din_17,
|
||||
din_18,
|
||||
din_19,
|
||||
din_20,
|
||||
din_21,
|
||||
din_22,
|
||||
din_23,
|
||||
din_24,
|
||||
din_25,
|
||||
din_26,
|
||||
din_27,
|
||||
din_28,
|
||||
din_29,
|
||||
din_30,
|
||||
din_31,
|
||||
din_32,
|
||||
din_33,
|
||||
din_34,
|
||||
din_35,
|
||||
dout
|
||||
);
|
||||
input clk;
|
||||
input rstn;
|
||||
input signed [15:0] din_0;
|
||||
input signed [15:0] din_1;
|
||||
input signed [15:0] din_2;
|
||||
input signed [15:0] din_3;
|
||||
input signed [15:0] din_4;
|
||||
input signed [15:0] din_5;
|
||||
input signed [15:0] din_6;
|
||||
input signed [15:0] din_7;
|
||||
input signed [15:0] din_8;
|
||||
input signed [15:0] din_9;
|
||||
input signed [15:0] din_10;
|
||||
input signed [15:0] din_11;
|
||||
input signed [15:0] din_12;
|
||||
input signed [15:0] din_13;
|
||||
input signed [15:0] din_14;
|
||||
input signed [15:0] din_15;
|
||||
input signed [15:0] din_16;
|
||||
input signed [15:0] din_17;
|
||||
input signed [15:0] din_18;
|
||||
input signed [15:0] din_19;
|
||||
input signed [15:0] din_20;
|
||||
input signed [15:0] din_21;
|
||||
input signed [15:0] din_22;
|
||||
input signed [15:0] din_23;
|
||||
input signed [15:0] din_24;
|
||||
input signed [15:0] din_25;
|
||||
input signed [15:0] din_26;
|
||||
input signed [15:0] din_27;
|
||||
input signed [15:0] din_28;
|
||||
input signed [15:0] din_29;
|
||||
input signed [15:0] din_30;
|
||||
input signed [15:0] din_31;
|
||||
input signed [15:0] din_32;
|
||||
input signed [15:0] din_33;
|
||||
input signed [15:0] din_34;
|
||||
input signed [15:0] din_35;
|
||||
|
||||
|
||||
output signed [15:0] dout;
|
||||
|
||||
parameter c0 = -20'd28;
|
||||
parameter c1 = 20'd82;
|
||||
parameter c2 = -20'd194;
|
||||
parameter c3 = 20'd397;
|
||||
parameter c4 = -20'd737;
|
||||
parameter c5 = 20'd1275;
|
||||
parameter c6 = -20'd2084;
|
||||
parameter c7 = 20'd3258;
|
||||
parameter c8 = -20'd4910;
|
||||
parameter c9 = 20'd7184;
|
||||
parameter c10 = -20'd10274;
|
||||
parameter c11 = 20'd14457;
|
||||
parameter c12 = -20'd20187;
|
||||
parameter c13 = 20'd28286;
|
||||
parameter c14 = -20'd40513;
|
||||
parameter c15 = 20'd61451;
|
||||
parameter c16 = -20'd108000;
|
||||
parameter c17 = 20'd332673;
|
||||
|
||||
reg signed [16:0] sum_0_35;
|
||||
reg signed [16:0] sum_1_34;
|
||||
reg signed [16:0] sum_2_33;
|
||||
reg signed [16:0] sum_3_32;
|
||||
reg signed [16:0] sum_4_31;
|
||||
reg signed [16:0] sum_5_30;
|
||||
reg signed [16:0] sum_6_29;
|
||||
reg signed [16:0] sum_7_28;
|
||||
reg signed [16:0] sum_8_27;
|
||||
reg signed [16:0] sum_9_26;
|
||||
reg signed [16:0] sum_10_25;
|
||||
reg signed [16:0] sum_11_24;
|
||||
reg signed [16:0] sum_12_23;
|
||||
reg signed [16:0] sum_13_22;
|
||||
reg signed [16:0] sum_14_21;
|
||||
reg signed [16:0] sum_15_20;
|
||||
reg signed [16:0] sum_16_19;
|
||||
reg signed [16:0] sum_17_18;
|
||||
|
||||
always@(posedge clk or negedge rstn) begin
|
||||
if(!rstn) begin
|
||||
sum_0_35 <= 'h0;
|
||||
sum_1_34 <= 'h0;
|
||||
sum_2_33 <= 'h0;
|
||||
sum_3_32 <= 'h0;
|
||||
sum_4_31 <= 'h0;
|
||||
sum_5_30 <= 'h0;
|
||||
sum_6_29 <= 'h0;
|
||||
sum_7_28 <= 'h0;
|
||||
sum_8_27 <= 'h0;
|
||||
sum_9_26 <= 'h0;
|
||||
sum_10_25 <= 'h0;
|
||||
sum_11_24 <= 'h0;
|
||||
sum_12_23 <= 'h0;
|
||||
sum_13_22 <= 'h0;
|
||||
sum_14_21 <= 'h0;
|
||||
sum_15_20 <= 'h0;
|
||||
sum_16_19 <= 'h0;
|
||||
sum_17_18 <= 'h0;
|
||||
end
|
||||
else begin
|
||||
sum_0_35 <= {{1 {din_0[15]}},din_0} + {{1 {din_35[15]}},din_35};
|
||||
sum_1_34 <= {{1 {din_1[15]}},din_1} + {{1 {din_34[15]}},din_34};
|
||||
sum_2_33 <= {{1 {din_2[15]}},din_2} + {{1 {din_33[15]}},din_33};
|
||||
sum_3_32 <= {{1 {din_3[15]}},din_3} + {{1 {din_32[15]}},din_32};
|
||||
sum_4_31 <= {{1 {din_4[15]}},din_4} + {{1 {din_31[15]}},din_31};
|
||||
sum_5_30 <= {{1 {din_5[15]}},din_5} + {{1 {din_30[15]}},din_30};
|
||||
sum_6_29 <= {{1 {din_6[15]}},din_6} + {{1 {din_29[15]}},din_29};
|
||||
sum_7_28 <= {{1 {din_7[15]}},din_7} + {{1 {din_28[15]}},din_28};
|
||||
sum_8_27 <= {{1 {din_8[15]}},din_8} + {{1 {din_27[15]}},din_27};
|
||||
sum_9_26 <= {{1 {din_9[15]}},din_9} + {{1 {din_26[15]}},din_26};
|
||||
sum_10_25 <= {{1 {din_10[15]}},din_10} + {{1 {din_25[15]}},din_25};
|
||||
sum_11_24 <= {{1 {din_11[15]}},din_11} + {{1 {din_24[15]}},din_24};
|
||||
sum_12_23 <= {{1 {din_12[15]}},din_12} + {{1 {din_23[15]}},din_23};
|
||||
sum_13_22 <= {{1 {din_13[15]}},din_13} + {{1 {din_22[15]}},din_22};
|
||||
sum_14_21 <= {{1 {din_14[15]}},din_14} + {{1 {din_21[15]}},din_21};
|
||||
sum_15_20 <= {{1 {din_15[15]}},din_15} + {{1 {din_20[15]}},din_20};
|
||||
sum_16_19 <= {{1 {din_16[15]}},din_16} + {{1 {din_19[15]}},din_19};
|
||||
sum_17_18 <= {{1 {din_17[15]}},din_17} + {{1 {din_18[15]}},din_18};
|
||||
end
|
||||
end
|
||||
|
||||
wire signed [17:0] mult_c0_sum0;
|
||||
|
||||
assign mult_c0_sum0 = {sum_0_35,1'b0};
|
||||
|
||||
reg signed [17:0] mult_c0_sum;
|
||||
|
||||
always@(posedge clk or negedge rstn) begin
|
||||
if(!rstn)
|
||||
mult_c0_sum <= 'h0;
|
||||
else
|
||||
mult_c0_sum <= mult_c0_sum0;
|
||||
end
|
||||
|
||||
wire signed [16:0] mult_c1_sum0;
|
||||
wire signed [18:0] mult_c1_sum1;
|
||||
|
||||
assign mult_c1_sum0 = sum_1_34;
|
||||
assign mult_c1_sum1 = {sum_1_34,2'b0};
|
||||
|
||||
reg signed [19:0] mult_c1_sum;
|
||||
|
||||
always@(posedge clk or negedge rstn)
|
||||
if(!rstn)
|
||||
mult_c1_sum <= 'h0;
|
||||
else
|
||||
mult_c1_sum <= {{3{mult_c1_sum0[16]}},mult_c1_sum0} + {{1{mult_c1_sum1[18]}},mult_c1_sum1};
|
||||
|
||||
|
||||
wire signed [18:0] mult_c2_sum0;
|
||||
wire signed [19:0] mult_c2_sum1;
|
||||
|
||||
assign mult_c2_sum0 = {sum_2_33,2'b0};
|
||||
assign mult_c2_sum1 = {sum_2_33,3'b0};
|
||||
|
||||
reg signed [20:0] mult_c2_sum;
|
||||
|
||||
always@(posedge clk or negedge rstn)
|
||||
if(!rstn)
|
||||
mult_c2_sum <= 'h0;
|
||||
else
|
||||
mult_c2_sum <= {{2{mult_c2_sum0[18]}},mult_c2_sum0} + {{1{mult_c2_sum1[19]}},mult_c2_sum1};
|
||||
|
||||
|
||||
wire signed [16:0] mult_c3_sum0;
|
||||
wire signed [19:0] mult_c3_sum1;
|
||||
wire signed [20:0] mult_c3_sum2;
|
||||
|
||||
assign mult_c3_sum0 = sum_3_32;
|
||||
assign mult_c3_sum1 = {sum_3_32,3'b0};
|
||||
assign mult_c3_sum2 = {sum_3_32,4'b0};
|
||||
|
||||
reg signed [21:0] mult_c3_sum;
|
||||
|
||||
always@(posedge clk or negedge rstn)
|
||||
if(!rstn)
|
||||
mult_c3_sum <= 'h0;
|
||||
else
|
||||
mult_c3_sum <= {{5{mult_c3_sum0[16]}},mult_c3_sum0} + {{2{mult_c3_sum1[19]}},mult_c3_sum1} + {{1{mult_c3_sum2[20]}},mult_c3_sum2};
|
||||
|
||||
|
||||
|
||||
wire signed [17:0] mult_c4_sum0;
|
||||
wire signed [20:0] mult_c4_sum1;
|
||||
wire signed [21:0] mult_c4_sum2;
|
||||
|
||||
assign mult_c4_sum0 = {sum_4_31,1'b0};
|
||||
assign mult_c4_sum1 = {sum_4_31,4'b0};
|
||||
assign mult_c4_sum2 = {sum_4_31,5'b0};
|
||||
|
||||
reg signed [22:0] mult_c4_sum;
|
||||
|
||||
always@(posedge clk or negedge rstn)
|
||||
if(!rstn)
|
||||
mult_c4_sum <= 'h0;
|
||||
else
|
||||
mult_c4_sum <= - {{5{mult_c4_sum0[17]}},mult_c4_sum0} + {{2{mult_c4_sum1[20]}},mult_c4_sum1} + {{1{mult_c4_sum2[21]}},mult_c4_sum2};
|
||||
|
||||
|
||||
|
||||
wire signed [20:0] mult_c5_sum0;
|
||||
wire signed [21:0] mult_c5_sum1;
|
||||
wire signed [23:0] mult_c5_sum2;
|
||||
|
||||
assign mult_c5_sum0 = {sum_5_30,4'b0};
|
||||
assign mult_c5_sum1 = {sum_5_30,5'b0};
|
||||
assign mult_c5_sum2 = {sum_5_30,7'b0};
|
||||
|
||||
reg signed [24:0] mult_c5_sum;
|
||||
|
||||
always@(posedge clk or negedge rstn)
|
||||
if(!rstn)
|
||||
mult_c5_sum <= 'h0;
|
||||
else
|
||||
mult_c5_sum <= -{{4{mult_c5_sum0[20]}},mult_c5_sum0} - {{3{mult_c5_sum1[21]}},mult_c5_sum1} + {{1{mult_c5_sum2[23]}},mult_c5_sum2};
|
||||
|
||||
|
||||
|
||||
|
||||
wire signed [17:0] mult_c6_sum0;
|
||||
wire signed [23:0] mult_c6_sum1;
|
||||
|
||||
assign mult_c6_sum0 = {sum_6_29,1'b0};
|
||||
assign mult_c6_sum1 = {sum_6_29,7'b0};
|
||||
|
||||
reg signed [24:0] mult_c6_sum;
|
||||
|
||||
always@(posedge clk or negedge rstn)
|
||||
if(!rstn)
|
||||
mult_c6_sum <= 'h0;
|
||||
else
|
||||
mult_c6_sum <= {{7{mult_c6_sum0[17]}},mult_c6_sum0} + {{1{mult_c6_sum1[23]}},mult_c6_sum1};
|
||||
|
||||
|
||||
|
||||
wire signed [18:0] mult_c7_sum0;
|
||||
wire signed [20:0] mult_c7_sum1;
|
||||
wire signed [21:0] mult_c7_sum2;
|
||||
wire signed [24:0] mult_c7_sum3;
|
||||
|
||||
assign mult_c7_sum0 = {sum_7_28,2'b0};
|
||||
assign mult_c7_sum1 = {sum_7_28,4'b0};
|
||||
assign mult_c7_sum2 = {sum_7_28,5'b0};
|
||||
assign mult_c7_sum3 = {sum_7_28,8'b0};
|
||||
|
||||
reg signed [25:0] mult_c7_sum;
|
||||
|
||||
always@(posedge clk or negedge rstn)
|
||||
if(!rstn)
|
||||
mult_c7_sum <= 'h0;
|
||||
else
|
||||
mult_c7_sum <= -{{7{mult_c7_sum0[18]}},mult_c7_sum0} - {{5{mult_c7_sum1[20]}},mult_c7_sum1} - {{4{mult_c7_sum2[21]}},mult_c7_sum2} + {{1{mult_c7_sum3[24]}},mult_c7_sum3};
|
||||
|
||||
|
||||
|
||||
wire signed [16:0] mult_c8_sum0;
|
||||
wire signed [17:0] mult_c8_sum1;
|
||||
wire signed [20:0] mult_c8_sum2;
|
||||
wire signed [21:0] mult_c8_sum3;
|
||||
wire signed [24:0] mult_c8_sum4;
|
||||
|
||||
assign mult_c8_sum0 = sum_8_27;
|
||||
assign mult_c8_sum1 = {sum_8_27,1'b0};
|
||||
assign mult_c8_sum2 = {sum_8_27,4'b0};
|
||||
assign mult_c8_sum3 = {sum_8_27,5'b0};
|
||||
assign mult_c8_sum4 = {sum_8_27,8'b0};
|
||||
|
||||
reg signed [25:0] mult_c8_sum;
|
||||
|
||||
always@(posedge clk or negedge rstn)
|
||||
if(!rstn)
|
||||
mult_c8_sum <= 'h0;
|
||||
else
|
||||
mult_c8_sum <= {{9{mult_c8_sum0[16]}},mult_c8_sum0} + {{8{mult_c8_sum1[17]}},mult_c8_sum1} + {{5{mult_c8_sum2[20]}},mult_c8_sum2} + {{4{mult_c8_sum3[21]}},mult_c8_sum3} + {{1{mult_c8_sum4[24]}},mult_c8_sum4};
|
||||
|
||||
|
||||
|
||||
wire signed [16:0] mult_c9_sum0;
|
||||
wire signed [22:0] mult_c9_sum1;
|
||||
wire signed [25:0] mult_c9_sum2;
|
||||
|
||||
assign mult_c9_sum0 = sum_9_26;
|
||||
assign mult_c9_sum1 = {sum_9_26,6'b0};
|
||||
assign mult_c9_sum2 = {sum_9_26,9'b0};
|
||||
|
||||
reg signed [26:0] mult_c9_sum;
|
||||
|
||||
always@(posedge clk or negedge rstn)
|
||||
if(!rstn)
|
||||
mult_c9_sum <= 'h0;
|
||||
else
|
||||
mult_c9_sum <= {{10{mult_c9_sum0[16]}},mult_c9_sum0} - {{4{mult_c9_sum1[22]}},mult_c9_sum1} + {{1{mult_c9_sum2[25]}},mult_c9_sum2};
|
||||
|
||||
|
||||
|
||||
|
||||
wire signed [17:0] mult_c10_sum0;
|
||||
wire signed [23:0] mult_c10_sum1;
|
||||
wire signed [25:0] mult_c10_sum2;
|
||||
|
||||
assign mult_c10_sum0 = {sum_10_25,1'b0};
|
||||
assign mult_c10_sum1 = {sum_10_25,7'b0};
|
||||
assign mult_c10_sum2 = {sum_10_25,9'b0};
|
||||
|
||||
reg signed [26:0] mult_c10_sum;
|
||||
|
||||
always@(posedge clk or negedge rstn)
|
||||
if(!rstn)
|
||||
mult_c10_sum <= 'h0;
|
||||
else
|
||||
mult_c10_sum <= {{9{mult_c10_sum0[17]}},mult_c10_sum0} + {{3{mult_c10_sum1[23]}},mult_c10_sum1} + {{1{mult_c10_sum2[25]}},mult_c10_sum2};
|
||||
|
||||
|
||||
|
||||
wire signed [19:0] mult_c11_sum0;
|
||||
wire signed [23:0] mult_c11_sum1;
|
||||
wire signed [26:0] mult_c11_sum2;
|
||||
|
||||
assign mult_c11_sum0 = {sum_11_24,3'b0};
|
||||
assign mult_c11_sum1 = {sum_11_24,7'b0};
|
||||
assign mult_c11_sum2 = {sum_11_24,10'b0};
|
||||
|
||||
reg signed [27:0] mult_c11_sum;
|
||||
|
||||
always@(posedge clk or negedge rstn)
|
||||
if(!rstn)
|
||||
mult_c11_sum <= 'h0;
|
||||
else
|
||||
mult_c11_sum <= {{8{mult_c11_sum0[19]}},mult_c11_sum0} - {{4{mult_c11_sum1[23]}},mult_c11_sum1} + {{1{mult_c11_sum2[26]}},mult_c11_sum2};
|
||||
|
||||
|
||||
|
||||
wire signed [17:0] mult_c12_sum0;
|
||||
wire signed [20:0] mult_c12_sum1;
|
||||
wire signed [24:0] mult_c12_sum2;
|
||||
wire signed [25:0] mult_c12_sum3;
|
||||
wire signed [27:0] mult_c12_sum4;
|
||||
|
||||
assign mult_c12_sum0 = {sum_12_23,1'b0};
|
||||
assign mult_c12_sum1 = {sum_12_23,4'b0};
|
||||
assign mult_c12_sum2 = {sum_12_23,8'b0};
|
||||
assign mult_c12_sum3 = {sum_12_23,9'b0};
|
||||
assign mult_c12_sum4 = {sum_12_23,11'b0};
|
||||
|
||||
reg signed [28:0] mult_c12_sum;
|
||||
|
||||
always@(posedge clk or negedge rstn)
|
||||
if(!rstn)
|
||||
mult_c12_sum <= 'h0;
|
||||
else
|
||||
mult_c12_sum <= - {{11{mult_c12_sum0[17]}},mult_c12_sum0} - {{8{mult_c12_sum1[20]}},mult_c12_sum1} - {{4{mult_c12_sum2[24]}},mult_c12_sum2} - {{3{mult_c12_sum3[25]}},mult_c12_sum3} + {{1{mult_c12_sum4[27]}},mult_c12_sum4};
|
||||
|
||||
|
||||
|
||||
wire signed [19:0] mult_c13_sum0;
|
||||
wire signed [20:0] mult_c13_sum1;
|
||||
wire signed [24:0] mult_c13_sum2;
|
||||
wire signed [27:0] mult_c13_sum3;
|
||||
|
||||
assign mult_c13_sum0 = {sum_13_22,3'b0};
|
||||
assign mult_c13_sum1 = {sum_13_22,4'b0};
|
||||
assign mult_c13_sum2 = {sum_13_22,8'b0};
|
||||
assign mult_c13_sum3 = {sum_13_22,11'b0};
|
||||
|
||||
reg signed [28:0] mult_c13_sum;
|
||||
|
||||
always@(posedge clk or negedge rstn)
|
||||
if(!rstn)
|
||||
mult_c13_sum <= 'h0;
|
||||
else
|
||||
mult_c13_sum <= - {{9{mult_c13_sum0[19]}},mult_c13_sum0} - {{8{mult_c13_sum1[20]}},mult_c13_sum1} - {{4{mult_c13_sum2[24]}},mult_c13_sum2} + {{1{mult_c13_sum3[27]}},mult_c13_sum3};
|
||||
|
||||
|
||||
|
||||
wire signed [18:0] mult_c14_sum0;
|
||||
wire signed [21:0] mult_c14_sum1;
|
||||
wire signed [25:0] mult_c14_sum2;
|
||||
wire signed [27:0] mult_c14_sum3;
|
||||
|
||||
assign mult_c14_sum0 = {sum_14_21,2'b0};
|
||||
assign mult_c14_sum1 = {sum_14_21,5'b0};
|
||||
assign mult_c14_sum2 = {sum_14_21,9'b0};
|
||||
assign mult_c14_sum3 = {sum_14_21,11'b0};
|
||||
|
||||
reg signed [28:0] mult_c14_sum;
|
||||
|
||||
always@(posedge clk or negedge rstn)
|
||||
if(!rstn)
|
||||
mult_c14_sum <= 'h0;
|
||||
else
|
||||
mult_c14_sum <= {{10{mult_c14_sum0[18]}},mult_c14_sum0} - {{7{mult_c14_sum1[21]}},mult_c14_sum1} + {{3{mult_c14_sum2[25]}},mult_c14_sum2} + {{1{mult_c14_sum3[27]}},mult_c14_sum3};
|
||||
|
||||
|
||||
|
||||
wire signed [16:0] mult_c15_sum0;
|
||||
wire signed [24:0] mult_c15_sum1;
|
||||
wire signed [28:0] mult_c15_sum2;
|
||||
|
||||
assign mult_c15_sum0 = sum_15_20;
|
||||
assign mult_c15_sum1 = {sum_15_20,8'b0};
|
||||
assign mult_c15_sum2 = {sum_15_20,12'b0};
|
||||
|
||||
reg signed [29:0] mult_c15_sum;
|
||||
|
||||
always@(posedge clk or negedge rstn)
|
||||
if(!rstn)
|
||||
mult_c15_sum <= 'h0;
|
||||
else
|
||||
mult_c15_sum <= {{13{mult_c15_sum0[16]}},mult_c15_sum0} - {{5{mult_c15_sum1[24]}},mult_c15_sum1} + {{1{mult_c15_sum2[28]}},mult_c15_sum2};
|
||||
|
||||
|
||||
|
||||
wire signed [17:0] mult_c16_sum0;
|
||||
wire signed [21:0] mult_c16_sum1;
|
||||
wire signed [22:0] mult_c16_sum2;
|
||||
wire signed [25:0] mult_c16_sum3;
|
||||
wire signed [27:0] mult_c16_sum4;
|
||||
wire signed [28:0] mult_c16_sum5;
|
||||
|
||||
assign mult_c16_sum0 = {sum_16_19,1'b0};
|
||||
assign mult_c16_sum1 = {sum_16_19,5'b0};
|
||||
assign mult_c16_sum2 = {sum_16_19,6'b0};
|
||||
assign mult_c16_sum3 = {sum_16_19,9'b0};
|
||||
assign mult_c16_sum4 = {sum_16_19,11'b0};
|
||||
assign mult_c16_sum5 = {sum_16_19,12'b0};
|
||||
|
||||
reg signed [29:0] mult_c16_sum;
|
||||
|
||||
always@(posedge clk or negedge rstn)
|
||||
if(!rstn)
|
||||
mult_c16_sum <= 'h0;
|
||||
else
|
||||
mult_c16_sum <= -{{12{mult_c16_sum0[17]}},mult_c16_sum0} + {{8{mult_c16_sum1[21]}},mult_c16_sum1} + {{7{mult_c16_sum2[22]}},mult_c16_sum2} + {{4{mult_c16_sum3[25]}},mult_c16_sum3} + {{2{mult_c16_sum4[27]}},mult_c16_sum4} + {{1{mult_c16_sum5[28]}},mult_c16_sum5};
|
||||
|
||||
|
||||
|
||||
wire signed [19:0] mult_c17_sum0;
|
||||
wire signed [22:0] mult_c17_sum1;
|
||||
wire signed [24:0] mult_c17_sum2;
|
||||
wire signed [28:0] mult_c17_sum3;
|
||||
wire signed [30:0] mult_c17_sum4;
|
||||
|
||||
assign mult_c17_sum0 = {sum_17_18,3'b0};
|
||||
assign mult_c17_sum1 = {sum_17_18,6'b0};
|
||||
assign mult_c17_sum2 = {sum_17_18,8'b0};
|
||||
assign mult_c17_sum3 = {sum_17_18,12'b0};
|
||||
assign mult_c17_sum4 = {sum_17_18,14'b0};
|
||||
|
||||
reg signed [31:0] mult_c17_sum;
|
||||
|
||||
always@(posedge clk or negedge rstn)
|
||||
if(!rstn)
|
||||
mult_c17_sum <= 'h0;
|
||||
else
|
||||
mult_c17_sum <= - {{12{mult_c17_sum0[19]}},mult_c17_sum0} + {{9{mult_c17_sum1[22]}},mult_c17_sum1} + {{7{mult_c17_sum2[24]}},mult_c17_sum2} + {{3{mult_c17_sum3[28]}},mult_c17_sum3} + {{1{mult_c17_sum4[30]}},mult_c17_sum4};
|
||||
|
||||
|
||||
|
||||
reg signed [22:0] mult_sum_r1;
|
||||
reg signed [27:0] mult_sum_r2;
|
||||
reg signed [30:0] mult_sum_r3;
|
||||
reg signed [32:0] mult_sum_r4;
|
||||
|
||||
always@(posedge clk or negedge rstn)
|
||||
if(!rstn)
|
||||
mult_sum_r1 <= 'h0;
|
||||
else
|
||||
mult_sum_r1 <= -{{5{mult_c0_sum[17]}},mult_c0_sum} + {{3{mult_c1_sum[19]}},mult_c1_sum} - {{2{mult_c2_sum[20]}},mult_c2_sum} + {{1{mult_c3_sum[21]}},mult_c3_sum};
|
||||
|
||||
always@(posedge clk or negedge rstn)
|
||||
if(!rstn)
|
||||
mult_sum_r2 <= 'h0;
|
||||
else
|
||||
mult_sum_r2 <= -{{5{mult_c4_sum[22]}},mult_c4_sum} + {{3{mult_c5_sum[24]}},mult_c5_sum} - {{3{mult_c6_sum[24]}},mult_c6_sum} + {{2{mult_c7_sum[25]}},mult_c7_sum};
|
||||
|
||||
always@(posedge clk or negedge rstn)
|
||||
if(!rstn)
|
||||
mult_sum_r3 <= 'h0;
|
||||
else
|
||||
mult_sum_r3 <= -{{5{mult_c8_sum[25]}},mult_c8_sum} + {{4{mult_c9_sum[26]}},mult_c9_sum} - {{4{mult_c10_sum[26]}},mult_c10_sum} + {{3{mult_c11_sum[27]}},mult_c11_sum} - {{2{mult_c12_sum[28]}},mult_c12_sum};
|
||||
|
||||
always@(posedge clk or negedge rstn)
|
||||
if(!rstn)
|
||||
mult_sum_r4 <= 'h0;
|
||||
else
|
||||
mult_sum_r4 <= {{4{mult_c13_sum[28]}},mult_c13_sum} - {{4{mult_c14_sum[28]}},mult_c14_sum} + {{3{mult_c15_sum[29]}},mult_c15_sum} - {{3{mult_c16_sum[29]}},mult_c16_sum} + {{1{mult_c17_sum[31]}},mult_c17_sum};
|
||||
|
||||
reg signed [33:0] mult_sum;
|
||||
|
||||
always@(posedge clk or negedge rstn)
|
||||
if(!rstn)
|
||||
mult_sum <= 'h0;
|
||||
else
|
||||
mult_sum <= mult_sum_r1 + mult_sum_r2 + mult_sum_r3 + mult_sum_r4;
|
||||
|
||||
|
||||
reg signed [15:0] dout0;
|
||||
|
||||
wire [19:0] dout0_w;
|
||||
|
||||
assign dout0_w = mult_sum[33:15] + mult_sum[14];
|
||||
|
||||
always@(posedge clk or negedge rstn)
|
||||
if(!rstn)
|
||||
dout0 <= 'h0;
|
||||
else if(dout0_w[16:15]==2'b01)
|
||||
dout0 <= 16'd32767;
|
||||
else if(dout0_w[16:15]==2'b10)
|
||||
dout0 <= -16'd32768;
|
||||
else
|
||||
dout0 <= dout0_w[15:0];
|
||||
|
||||
assign dout = dout0;
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,178 @@
|
|||
module DUC_HB1_TOP (clkl,
|
||||
rstn,
|
||||
din,
|
||||
dout_p0,
|
||||
dout_p1
|
||||
);
|
||||
input clkl,rstn;
|
||||
input [15:0] din;
|
||||
|
||||
output [15:0] dout_p0;
|
||||
output [15:0] dout_p1;
|
||||
|
||||
|
||||
reg [15:0] din_r1;
|
||||
reg [15:0] din_r2;
|
||||
reg [15:0] din_r3;
|
||||
reg [15:0] din_r4;
|
||||
reg [15:0] din_r5;
|
||||
reg [15:0] din_r6;
|
||||
reg [15:0] din_r7;
|
||||
reg [15:0] din_r8;
|
||||
reg [15:0] din_r9;
|
||||
reg [15:0] din_r10;
|
||||
reg [15:0] din_r11;
|
||||
reg [15:0] din_r12;
|
||||
reg [15:0] din_r13;
|
||||
reg [15:0] din_r14;
|
||||
reg [15:0] din_r15;
|
||||
reg [15:0] din_r16;
|
||||
reg [15:0] din_r17;
|
||||
reg [15:0] din_r18;
|
||||
reg [15:0] din_r19;
|
||||
reg [15:0] din_r20;
|
||||
reg [15:0] din_r21;
|
||||
reg [15:0] din_r22;
|
||||
reg [15:0] din_r23;
|
||||
reg [15:0] din_r24;
|
||||
reg [15:0] din_r25;
|
||||
reg [15:0] din_r26;
|
||||
reg [15:0] din_r27;
|
||||
reg [15:0] din_r28;
|
||||
reg [15:0] din_r29;
|
||||
reg [15:0] din_r30;
|
||||
reg [15:0] din_r31;
|
||||
reg [15:0] din_r32;
|
||||
reg [15:0] din_r33;
|
||||
reg [15:0] din_r34;
|
||||
reg [15:0] din_r35;
|
||||
|
||||
always@(posedge clkl or negedge rstn)
|
||||
if(!rstn)
|
||||
begin
|
||||
din_r1 <= 'b0;
|
||||
din_r2 <= 'b0;
|
||||
din_r3 <= 'b0;
|
||||
din_r4 <= 'b0;
|
||||
din_r5 <= 'b0;
|
||||
din_r6 <= 'b0;
|
||||
din_r7 <= 'b0;
|
||||
din_r8 <= 'b0;
|
||||
din_r9 <= 'b0;
|
||||
din_r10 <= 'b0;
|
||||
din_r11 <= 'b0;
|
||||
din_r12 <= 'b0;
|
||||
din_r13 <= 'b0;
|
||||
din_r14 <= 'b0;
|
||||
din_r15 <= 'b0;
|
||||
din_r16 <= 'b0;
|
||||
din_r17 <= 'b0;
|
||||
din_r18 <= 'b0;
|
||||
din_r19 <= 'b0;
|
||||
din_r20 <= 'b0;
|
||||
din_r21 <= 'b0;
|
||||
din_r22 <= 'b0;
|
||||
din_r23 <= 'b0;
|
||||
din_r24 <= 'b0;
|
||||
din_r25 <= 'b0;
|
||||
din_r26 <= 'b0;
|
||||
din_r27 <= 'b0;
|
||||
din_r28 <= 'b0;
|
||||
din_r29 <= 'b0;
|
||||
din_r30 <= 'b0;
|
||||
din_r31 <= 'b0;
|
||||
din_r32 <= 'b0;
|
||||
din_r33 <= 'b0;
|
||||
din_r34 <= 'b0;
|
||||
din_r35 <= 'b0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
din_r1 <= din;
|
||||
din_r2 <= din_r1;
|
||||
din_r3 <= din_r2;
|
||||
din_r4 <= din_r3;
|
||||
din_r5 <= din_r4;
|
||||
din_r6 <= din_r5;
|
||||
din_r7 <= din_r6;
|
||||
din_r8 <= din_r7;
|
||||
din_r9 <= din_r8;
|
||||
din_r10 <= din_r9;
|
||||
din_r11 <= din_r10;
|
||||
din_r12 <= din_r11;
|
||||
din_r13 <= din_r12;
|
||||
din_r14 <= din_r13;
|
||||
din_r15 <= din_r14;
|
||||
din_r16 <= din_r15;
|
||||
din_r17 <= din_r16;
|
||||
din_r18 <= din_r17;
|
||||
din_r19 <= din_r18;
|
||||
din_r20 <= din_r19;
|
||||
din_r21 <= din_r20;
|
||||
din_r22 <= din_r21;
|
||||
din_r23 <= din_r22;
|
||||
din_r24 <= din_r23;
|
||||
din_r25 <= din_r24;
|
||||
din_r26 <= din_r25;
|
||||
din_r27 <= din_r26;
|
||||
din_r28 <= din_r27;
|
||||
din_r29 <= din_r28;
|
||||
din_r30 <= din_r29;
|
||||
din_r31 <= din_r30;
|
||||
din_r32 <= din_r31;
|
||||
din_r33 <= din_r32;
|
||||
din_r34 <= din_r33;
|
||||
din_r35 <= din_r34;
|
||||
end
|
||||
|
||||
|
||||
|
||||
|
||||
DUC_HB1 inst_duc_hb1(
|
||||
.clk (clkl),
|
||||
.rstn (rstn),
|
||||
.din_0 (din),
|
||||
.din_1 (din_r1),
|
||||
.din_2 (din_r2),
|
||||
.din_3 (din_r3),
|
||||
.din_4 (din_r4),
|
||||
.din_5 (din_r5),
|
||||
.din_6 (din_r6),
|
||||
.din_7 (din_r7),
|
||||
.din_8 (din_r8),
|
||||
.din_9 (din_r9),
|
||||
.din_10 (din_r10),
|
||||
.din_11 (din_r11),
|
||||
.din_12 (din_r12),
|
||||
.din_13 (din_r13),
|
||||
.din_14 (din_r14),
|
||||
.din_15 (din_r15),
|
||||
.din_16 (din_r16),
|
||||
.din_17 (din_r17),
|
||||
.din_18 (din_r18),
|
||||
.din_19 (din_r19),
|
||||
.din_20 (din_r20),
|
||||
.din_21 (din_r21),
|
||||
.din_22 (din_r22),
|
||||
.din_23 (din_r23),
|
||||
.din_24 (din_r24),
|
||||
.din_25 (din_r25),
|
||||
.din_26 (din_r26),
|
||||
.din_27 (din_r27),
|
||||
.din_28 (din_r28),
|
||||
.din_29 (din_r29),
|
||||
.din_30 (din_r30),
|
||||
.din_31 (din_r31),
|
||||
.din_32 (din_r32),
|
||||
.din_33 (din_r33),
|
||||
.din_34 (din_r34),
|
||||
.din_35 (din_r35),
|
||||
.dout (dout_p1)
|
||||
);
|
||||
|
||||
|
||||
assign dout_p0 = din_r22;
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,259 @@
|
|||
//+FHDR--------------------------------------------------------------------------------------------------------
|
||||
// Company:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// File Name : duc_hb2_shift.v
|
||||
// Department :
|
||||
// Author : thfu
|
||||
// Author's Tel :
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Relese History
|
||||
// Version Date Author Description
|
||||
// 0.8 2024-03-26 thfu add pipeline
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Keywords :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Parameter
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Purpose :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Target Device:
|
||||
// Tool versions:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Reuse Issues
|
||||
// Reset Strategy:
|
||||
// Clock Domains:
|
||||
// Critical Timing:
|
||||
// Asynchronous I/F:
|
||||
// Synthesizable (y/n):
|
||||
// Other:
|
||||
//-FHDR--------------------------------------------------------------------------------------------------------
|
||||
module DUC_HB2 (
|
||||
clk,
|
||||
rstn,
|
||||
din_0,
|
||||
din_1,
|
||||
din_2,
|
||||
din_3,
|
||||
din_4,
|
||||
din_5,
|
||||
din_6,
|
||||
din_7,
|
||||
din_8,
|
||||
din_9,
|
||||
din_a,
|
||||
din_b,
|
||||
dout
|
||||
);
|
||||
input clk;
|
||||
input rstn;
|
||||
input signed [15:0] din_0;
|
||||
input signed [15:0] din_1;
|
||||
input signed [15:0] din_2;
|
||||
input signed [15:0] din_3;
|
||||
input signed [15:0] din_4;
|
||||
input signed [15:0] din_5;
|
||||
input signed [15:0] din_6;
|
||||
input signed [15:0] din_7;
|
||||
input signed [15:0] din_8;
|
||||
input signed [15:0] din_9;
|
||||
input signed [15:0] din_a;
|
||||
input signed [15:0] din_b;
|
||||
|
||||
output signed [15:0] dout;
|
||||
|
||||
parameter c0 = -18'd91;
|
||||
parameter c1 = 18'd659;
|
||||
parameter c2 = -18'd2663;
|
||||
parameter c3 = 18'd8009;
|
||||
parameter c4 = -18'd21490;
|
||||
parameter c5 = 18'd81112;
|
||||
|
||||
reg signed [16:0] sum_0_b;
|
||||
reg signed [16:0] sum_1_a;
|
||||
reg signed [16:0] sum_2_9;
|
||||
reg signed [16:0] sum_3_8;
|
||||
reg signed [16:0] sum_4_7;
|
||||
reg signed [16:0] sum_5_6;
|
||||
always@(posedge clk or negedge rstn)
|
||||
if(!rstn)
|
||||
begin
|
||||
sum_0_b <= 'h0;
|
||||
sum_1_a <= 'h0;
|
||||
sum_2_9 <= 'h0;
|
||||
sum_3_8 <= 'h0;
|
||||
sum_4_7 <= 'h0;
|
||||
sum_5_6 <= 'h0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
sum_0_b <= {{1 {din_0[15]}},din_0} + {{1 {din_b[15]}},din_b};
|
||||
sum_1_a <= {{1 {din_1[15]}},din_1} + {{1 {din_a[15]}},din_a};
|
||||
sum_2_9 <= {{1 {din_2[15]}},din_2} + {{1 {din_9[15]}},din_9};
|
||||
sum_3_8 <= {{1 {din_3[15]}},din_3} + {{1 {din_8[15]}},din_8};
|
||||
sum_4_7 <= {{1 {din_4[15]}},din_4} + {{1 {din_7[15]}},din_7};
|
||||
sum_5_6 <= {{1 {din_5[15]}},din_5} + {{1 {din_6[15]}},din_6};
|
||||
end
|
||||
|
||||
|
||||
wire signed [16:0] mult_c0_sum0;
|
||||
wire signed [19:0] mult_c0_sum1;
|
||||
wire signed [21:0] mult_c0_sum2;
|
||||
|
||||
assign mult_c0_sum0 = sum_0_b;
|
||||
assign mult_c0_sum1 = {sum_0_b,3'b0};
|
||||
assign mult_c0_sum2 = {sum_0_b,5'b0};
|
||||
|
||||
reg signed [22:0] mult_c0_sum;
|
||||
|
||||
always@(posedge clk or negedge rstn)
|
||||
if(!rstn)
|
||||
mult_c0_sum <= 'h0;
|
||||
else
|
||||
mult_c0_sum <= -{{6{mult_c0_sum0[16]}},mult_c0_sum0} - {{3{mult_c0_sum1[19]}},mult_c0_sum1} + {{1{mult_c0_sum2[21]}},mult_c0_sum2};
|
||||
|
||||
|
||||
wire signed [16:0] mult_c1_sum0;
|
||||
wire signed [18:0] mult_c1_sum1;
|
||||
wire signed [21:0] mult_c1_sum2;
|
||||
wire signed [23:0] mult_c1_sum3;
|
||||
|
||||
assign mult_c1_sum0 = sum_1_a;
|
||||
assign mult_c1_sum1 = {sum_1_a,2'b0};
|
||||
assign mult_c1_sum2 = {sum_1_a,5'b0};
|
||||
assign mult_c1_sum3 = {sum_1_a,7'b0};
|
||||
|
||||
reg signed [24:0] mult_c1_sum;
|
||||
|
||||
always@(posedge clk or negedge rstn)
|
||||
if(!rstn)
|
||||
mult_c1_sum <= 'h0;
|
||||
else
|
||||
mult_c1_sum <= {{8{mult_c1_sum0[16]}},mult_c1_sum0} + {{6{mult_c1_sum1[18]}},mult_c1_sum1} + {{3{mult_c1_sum2[21]}},mult_c1_sum2} + {{1{mult_c1_sum3[23]}},mult_c1_sum3};
|
||||
|
||||
|
||||
|
||||
wire signed [17:0] mult_c2_sum0;
|
||||
wire signed [18:0] mult_c2_sum1;
|
||||
wire signed [21:0] mult_c2_sum2;
|
||||
wire signed [22:0] mult_c2_sum3;
|
||||
wire signed [24:0] mult_c2_sum4;
|
||||
wire signed [26:0] mult_c2_sum5;
|
||||
|
||||
assign mult_c2_sum0 = {sum_2_9,1'b0};
|
||||
assign mult_c2_sum1 = {sum_2_9,2'b0};
|
||||
assign mult_c2_sum2 = {sum_2_9,5'b0};
|
||||
assign mult_c2_sum3 = {sum_2_9,6'b0};
|
||||
assign mult_c2_sum4 = {sum_2_9,8'b0};
|
||||
assign mult_c2_sum5 = {sum_2_9,10'b0};
|
||||
|
||||
reg signed [27:0] mult_c2_sum;
|
||||
|
||||
always@(posedge clk or negedge rstn)
|
||||
if(!rstn)
|
||||
mult_c2_sum <= 'h0;
|
||||
else
|
||||
mult_c2_sum <= -{{10{mult_c2_sum0[17]}},mult_c2_sum0} - {{9{mult_c2_sum1[18]}},mult_c2_sum1} - {{6{mult_c2_sum2[21]}},mult_c2_sum2} - {{5{mult_c2_sum3[22]}},mult_c2_sum3} - {{3{mult_c2_sum4[24]}},mult_c2_sum4} + {{1{mult_c2_sum5[26]}},mult_c2_sum5};
|
||||
|
||||
|
||||
wire signed [17:0] mult_c3_sum0;
|
||||
wire signed [20:0] mult_c3_sum1;
|
||||
wire signed [22:0] mult_c3_sum2;
|
||||
wire signed [27:0] mult_c3_sum3;
|
||||
|
||||
assign mult_c3_sum0 = {sum_3_8,1'b0};
|
||||
assign mult_c3_sum1 = {sum_3_8,4'b0};
|
||||
assign mult_c3_sum2 = {sum_3_8,6'b0};
|
||||
assign mult_c3_sum3 = {sum_3_8,11'b0};
|
||||
|
||||
reg signed [28:0] mult_c3_sum;
|
||||
|
||||
always@(posedge clk or negedge rstn)
|
||||
if(!rstn)
|
||||
mult_c3_sum <= 'h0;
|
||||
else
|
||||
mult_c3_sum <= {{11{mult_c3_sum0[17]}},mult_c3_sum0} + {{8{mult_c3_sum1[20]}},mult_c3_sum1} - {{6{mult_c3_sum2[22]}},mult_c3_sum2} + {{1{mult_c3_sum3[27]}},mult_c3_sum3};
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
wire signed [16:0] mult_c4_sum0;
|
||||
wire signed [18:0] mult_c4_sum1;
|
||||
wire signed [24:0] mult_c4_sum2;
|
||||
wire signed [26:0] mult_c4_sum3;
|
||||
wire signed [28:0] mult_c4_sum4;
|
||||
|
||||
assign mult_c4_sum0 = sum_4_7;
|
||||
assign mult_c4_sum1 = {sum_4_7,2'b0};
|
||||
assign mult_c4_sum2 = {sum_4_7,8'b0};
|
||||
assign mult_c4_sum3 = {sum_4_7,10'b0};
|
||||
assign mult_c4_sum4 = {sum_4_7,12'b0};
|
||||
|
||||
reg signed [29:0] mult_c4_sum;
|
||||
|
||||
always@(posedge clk or negedge rstn)
|
||||
if(!rstn)
|
||||
mult_c4_sum <= 'h0;
|
||||
else
|
||||
mult_c4_sum <= {{13{mult_c4_sum0[16]}},mult_c4_sum0} - {{11{mult_c4_sum1[18]}},mult_c4_sum1} + {{5{mult_c4_sum2[24]}},mult_c4_sum2} + {{3{mult_c4_sum3[26]}},mult_c4_sum3} + {{1{mult_c4_sum4[28]}},mult_c4_sum4};
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
wire signed [17:0] mult_c5_sum0;
|
||||
wire signed [18:0] mult_c5_sum1;
|
||||
wire signed [20:0] mult_c5_sum2;
|
||||
wire signed [21:0] mult_c5_sum3;
|
||||
wire signed [24:0] mult_c5_sum4;
|
||||
wire signed [28:0] mult_c5_sum5;
|
||||
wire signed [30:0] mult_c5_sum6;
|
||||
|
||||
assign mult_c5_sum0 = {sum_5_6,1'b0};
|
||||
assign mult_c5_sum1 = {sum_5_6,2'b0};
|
||||
assign mult_c5_sum2 = {sum_5_6,4'b0};
|
||||
assign mult_c5_sum3 = {sum_5_6,5'b0};
|
||||
assign mult_c5_sum4 = {sum_5_6,8'b0};
|
||||
assign mult_c5_sum5 = {sum_5_6,12'b0};
|
||||
assign mult_c5_sum6 = {sum_5_6,14'b0};
|
||||
|
||||
reg signed [31:0] mult_c5_sum;
|
||||
|
||||
always@(posedge clk or negedge rstn)
|
||||
if(!rstn)
|
||||
mult_c5_sum <= 'h0;
|
||||
else
|
||||
mult_c5_sum <= {{14{mult_c5_sum0[17]}},mult_c5_sum0} + {{13{mult_c5_sum1[18]}},mult_c5_sum1} + {{11{mult_c5_sum2[20]}},mult_c5_sum2} + {{10{mult_c5_sum3[21]}},mult_c5_sum3} - {{7{mult_c5_sum4[24]}},mult_c5_sum4} + {{3{mult_c5_sum5[28]}},mult_c5_sum5} + {{1{mult_c5_sum6[30]}},mult_c5_sum6};
|
||||
|
||||
reg signed [32:0] mult_sum;
|
||||
|
||||
always@(posedge clk or negedge rstn)
|
||||
if(!rstn)
|
||||
mult_sum <= 'h0;
|
||||
else
|
||||
mult_sum <= -{{10{mult_c0_sum[22]}},mult_c0_sum} + {{8{mult_c1_sum[24]}},mult_c1_sum} - {{5{mult_c2_sum[27]}},mult_c2_sum} + {{4{mult_c3_sum[28]}},mult_c3_sum} - {{3{mult_c4_sum[29]}},mult_c4_sum} + {{1{mult_c5_sum[31]}},mult_c5_sum};
|
||||
|
||||
wire signed [17:0] dout0_w;
|
||||
|
||||
reg signed [15:0] dout0;
|
||||
|
||||
assign dout0_w = mult_sum[32:15]+mult_sum[14];
|
||||
|
||||
always@(posedge clk or negedge rstn)
|
||||
if(!rstn)
|
||||
dout0 <= 'h0;
|
||||
else if(dout0_w[16:15]==2'b01)
|
||||
dout0 <= 16'd32767;
|
||||
else if(dout0_w[16:15]==2'b10)
|
||||
dout0 <= -16'd32768;
|
||||
else
|
||||
dout0 <= dout0_w[15:0];
|
||||
|
||||
assign dout = dout0;
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,118 @@
|
|||
module DUC_HB2_TOP_S (clkl,
|
||||
rstn,
|
||||
din0,
|
||||
din1,
|
||||
dout_p0,
|
||||
dout_p1,
|
||||
dout_p2,
|
||||
dout_p3
|
||||
);
|
||||
input clkl,rstn;
|
||||
input [15:0] din0;
|
||||
input [15:0] din1;
|
||||
|
||||
output [15:0] dout_p0;
|
||||
output [15:0] dout_p1;
|
||||
output [15:0] dout_p2;
|
||||
output [15:0] dout_p3;
|
||||
|
||||
|
||||
reg [15:0] din_r1;
|
||||
reg [15:0] din_r2;
|
||||
reg [15:0] din_r3;
|
||||
reg [15:0] din_r4;
|
||||
reg [15:0] din_r5;
|
||||
reg [15:0] din_r6;
|
||||
reg [15:0] din_r7;
|
||||
reg [15:0] din_r8;
|
||||
reg [15:0] din_r9;
|
||||
reg [15:0] din_r10;
|
||||
reg [15:0] din_r11;
|
||||
reg [15:0] din_r12;
|
||||
reg [15:0] din_r13;
|
||||
reg [15:0] din_r14;
|
||||
|
||||
always@(posedge clkl or negedge rstn)
|
||||
if(!rstn)
|
||||
begin
|
||||
din_r1 <= 'b0;
|
||||
din_r2 <= 'b0;
|
||||
din_r3 <= 'b0;
|
||||
din_r4 <= 'b0;
|
||||
din_r5 <= 'b0;
|
||||
din_r6 <= 'b0;
|
||||
din_r7 <= 'b0;
|
||||
din_r8 <= 'b0;
|
||||
din_r9 <= 'b0;
|
||||
din_r10 <= 'b0;
|
||||
din_r11 <= 'b0;
|
||||
din_r12 <= 'b0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
din_r1 <= din1;
|
||||
din_r3 <= din_r1;
|
||||
din_r5 <= din_r3;
|
||||
din_r7 <= din_r5;
|
||||
din_r9 <= din_r7;
|
||||
din_r11 <= din_r9;
|
||||
din_r13 <= din_r11;
|
||||
|
||||
din_r2 <= din0;
|
||||
din_r4 <= din_r2;
|
||||
din_r6 <= din_r4;
|
||||
din_r8 <= din_r6;
|
||||
din_r10 <= din_r8;
|
||||
din_r12 <= din_r10;
|
||||
din_r14 <= din_r12;
|
||||
end
|
||||
|
||||
|
||||
|
||||
|
||||
DUC_HB2 inst0_duc_hb2(
|
||||
.clk (clkl),
|
||||
.rstn (rstn),
|
||||
.din_0 (din1),
|
||||
.din_1 (din0),
|
||||
.din_2 (din_r1),
|
||||
.din_3 (din_r2),
|
||||
.din_4 (din_r3),
|
||||
.din_5 (din_r4),
|
||||
.din_6 (din_r5), //dout_p0
|
||||
.din_7 (din_r6),
|
||||
.din_8 (din_r7),
|
||||
.din_9 (din_r8),
|
||||
.din_a (din_r9),
|
||||
.din_b (din_r10),
|
||||
.dout (dout_p1)
|
||||
);
|
||||
|
||||
|
||||
assign dout_p0 = din_r13;
|
||||
|
||||
|
||||
DUC_HB2 inst1_duc_hb2(
|
||||
.clk (clkl),
|
||||
.rstn (rstn),
|
||||
.din_0 (din0),
|
||||
.din_1 (din_r1),
|
||||
.din_2 (din_r2),
|
||||
.din_3 (din_r3),
|
||||
.din_4 (din_r4),
|
||||
.din_5 (din_r5),
|
||||
.din_6 (din_r6), //dout_p2
|
||||
.din_7 (din_r7),
|
||||
.din_8 (din_r8),
|
||||
.din_9 (din_r9),
|
||||
.din_a (din_r10),
|
||||
.din_b (din_r11),
|
||||
.dout (dout_p3)
|
||||
);
|
||||
|
||||
|
||||
assign dout_p2 = din_r14;
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,193 @@
|
|||
//+FHDR--------------------------------------------------------------------------------------------------------
|
||||
// Company:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// File Name : duc_hb3_shift.v
|
||||
// Department :
|
||||
// Author :
|
||||
// Author's Tel :
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Relese History
|
||||
// Version Date Author Description
|
||||
// 0.8 2024-03-26 thfu output register
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Keywords :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Parameter
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Purpose :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Target Device:
|
||||
// Tool versions:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Reuse Issues
|
||||
// Reset Strategy:
|
||||
// Clock Domains:
|
||||
// Critical Timing:
|
||||
// Asynchronous I/F:
|
||||
// Synthesizable (y/n):
|
||||
// Other:
|
||||
//-FHDR--------------------------------------------------------------------------------------------------------
|
||||
module DUC_HB3 (
|
||||
clk,
|
||||
rstn,
|
||||
din_0,
|
||||
din_1,
|
||||
din_2,
|
||||
din_3,
|
||||
din_4,
|
||||
din_5,
|
||||
din_6,
|
||||
din_7,
|
||||
dout
|
||||
);
|
||||
input clk;
|
||||
input rstn;
|
||||
input signed [15:0] din_0;
|
||||
input signed [15:0] din_1;
|
||||
input signed [15:0] din_2;
|
||||
input signed [15:0] din_3;
|
||||
input signed [15:0] din_4;
|
||||
input signed [15:0] din_5;
|
||||
input signed [15:0] din_6;
|
||||
input signed [15:0] din_7;
|
||||
|
||||
output signed [15:0] dout;
|
||||
|
||||
parameter c0 = -17'd210;
|
||||
parameter c1 = 17'd1799;
|
||||
parameter c2 = -17'd8234;
|
||||
parameter c3 = 17'd39413;
|
||||
|
||||
reg signed [16:0] sum_0_7;
|
||||
reg signed [16:0] sum_1_6;
|
||||
reg signed [16:0] sum_2_5;
|
||||
reg signed [16:0] sum_3_4;
|
||||
|
||||
|
||||
always@(posedge clk or negedge rstn)
|
||||
if(!rstn)
|
||||
begin
|
||||
sum_0_7 <= 'h0;
|
||||
sum_1_6 <= 'h0;
|
||||
sum_2_5 <= 'h0;
|
||||
sum_3_4 <= 'h0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
sum_0_7 <= {{1 {din_0[15]}},din_0} + {{1 {din_7[15]}},din_7};
|
||||
sum_1_6 <= {{1 {din_1[15]}},din_1} + {{1 {din_6[15]}},din_6};
|
||||
sum_2_5 <= {{1 {din_2[15]}},din_2} + {{1 {din_5[15]}},din_5};
|
||||
sum_3_4 <= {{1 {din_3[15]}},din_3} + {{1 {din_4[15]}},din_4};
|
||||
end
|
||||
|
||||
|
||||
wire signed [16:0] mult_c0_sum0;
|
||||
wire signed [19:0] mult_c0_sum1;
|
||||
wire signed [21:0] mult_c0_sum2;
|
||||
wire signed [22:0] mult_c0_sum3;
|
||||
|
||||
assign mult_c0_sum0 = sum_0_7;
|
||||
assign mult_c0_sum1 = {sum_0_7,3'b0};
|
||||
assign mult_c0_sum2 = {sum_0_7,5'b0};
|
||||
assign mult_c0_sum3 = {sum_0_7,6'b0};
|
||||
|
||||
reg signed [23:0] mult_c0_sum;
|
||||
|
||||
always@(posedge clk or negedge rstn)
|
||||
if(!rstn)
|
||||
mult_c0_sum <= 'h0;
|
||||
else
|
||||
mult_c0_sum <= {{7{mult_c0_sum0[16]}},mult_c0_sum0} + {{4{mult_c0_sum1[19]}},mult_c0_sum1} + {{2{mult_c0_sum2[21]}},mult_c0_sum2} + {{1{mult_c0_sum3[22]}},mult_c0_sum3};
|
||||
|
||||
|
||||
wire signed [18:0] mult_c1_sum0;
|
||||
wire signed [23:0] mult_c1_sum1;
|
||||
wire signed [26:0] mult_c1_sum2;
|
||||
|
||||
assign mult_c1_sum0 = {sum_1_6,2'b0};
|
||||
assign mult_c1_sum1 = {sum_1_6,7'b0};
|
||||
assign mult_c1_sum2 = {sum_1_6,10'b0};
|
||||
|
||||
reg signed [27:0] mult_c1_sum;
|
||||
always@(posedge clk or negedge rstn)
|
||||
if(!rstn)
|
||||
mult_c1_sum <= 'h0;
|
||||
else
|
||||
mult_c1_sum <= {{9{mult_c1_sum0[18]}},mult_c1_sum0} - {{4{mult_c1_sum1[23]}},mult_c1_sum1} + {{1{mult_c1_sum2[26]}},mult_c1_sum2};
|
||||
|
||||
|
||||
wire signed [16:0] mult_c2_sum0;
|
||||
wire signed [18:0] mult_c2_sum1;
|
||||
wire signed [20:0] mult_c2_sum2;
|
||||
wire signed [28:0] mult_c2_sum3;
|
||||
|
||||
assign mult_c2_sum0 = sum_2_5;
|
||||
assign mult_c2_sum1 = {sum_2_5,2'b0};
|
||||
assign mult_c2_sum2 = {sum_2_5,4'b0};
|
||||
assign mult_c2_sum3 = {sum_2_5,12'b0};
|
||||
|
||||
reg signed [29:0] mult_c2_sum;
|
||||
|
||||
always@(posedge clk or negedge rstn)
|
||||
if(!rstn)
|
||||
mult_c2_sum <= 'h0;
|
||||
else
|
||||
mult_c2_sum <= {{13{mult_c2_sum0[16]}},mult_c2_sum0} + {{11{mult_c2_sum1[18]}},mult_c2_sum1} + {{9{mult_c2_sum2[20]}},mult_c2_sum2} + {{1{mult_c2_sum3[28]}},mult_c2_sum3};
|
||||
|
||||
|
||||
wire signed [16:0] mult_c3_sum0;
|
||||
wire signed [17:0] mult_c3_sum1;
|
||||
wire signed [19:0] mult_c3_sum2;
|
||||
wire signed [24:0] mult_c3_sum3;
|
||||
wire signed [26:0] mult_c3_sum4;
|
||||
wire signed [27:0] mult_c3_sum5;
|
||||
wire signed [30:0] mult_c3_sum6;
|
||||
;
|
||||
assign mult_c3_sum0 = sum_3_4;
|
||||
assign mult_c3_sum1 = {sum_3_4,1'b0};
|
||||
assign mult_c3_sum2 = {sum_3_4,3'b0};
|
||||
assign mult_c3_sum3 = {sum_3_4,8'b0};
|
||||
assign mult_c3_sum4 = {sum_3_4,10'b0};
|
||||
assign mult_c3_sum5 = {sum_3_4,11'b0};
|
||||
assign mult_c3_sum6 = {sum_3_4,14'b0};
|
||||
|
||||
reg signed [31:0] mult_c3_sum;
|
||||
|
||||
always@(posedge clk or negedge rstn)
|
||||
if(!rstn)
|
||||
mult_c3_sum <= 'h0;
|
||||
else
|
||||
mult_c3_sum <= {{15{mult_c3_sum0[16]}},mult_c3_sum0} + {{14{mult_c3_sum1[17]}},mult_c3_sum1} - {{12{mult_c3_sum2[19]}},mult_c3_sum2} + {{7{mult_c3_sum3[24]}},mult_c3_sum3} + {{5{mult_c3_sum4[26]}},mult_c3_sum4} + {{4{mult_c3_sum5[27]}},mult_c3_sum5} + {{1{mult_c3_sum6[30]}},mult_c3_sum6};
|
||||
|
||||
|
||||
reg signed [32:0] mult_sum;
|
||||
|
||||
always@(posedge clk or negedge rstn)
|
||||
if(!rstn)
|
||||
mult_sum <= 'h0;
|
||||
else
|
||||
mult_sum <= -{{9{mult_c0_sum[23]}},mult_c0_sum} + {{5{mult_c1_sum[27]}},mult_c1_sum} - {{3{mult_c2_sum[29]}},mult_c2_sum} + {{1{mult_c3_sum[31]}},mult_c3_sum};
|
||||
|
||||
wire signed [17:0] dout0_w;
|
||||
|
||||
reg signed [15:0] dout0;
|
||||
|
||||
assign dout0_w = mult_sum[32:15]+mult_sum[14];
|
||||
|
||||
always@(posedge clk or negedge rstn)
|
||||
if(!rstn)
|
||||
dout0 <= 'h0;
|
||||
else if(dout0_w[16:15]==2'b01)
|
||||
dout0 <= 16'd32767;
|
||||
else if(dout0_w[16:15]==2'b10)
|
||||
dout0 <= -16'd32768;
|
||||
else
|
||||
dout0 <= dout0_w[15:0];
|
||||
|
||||
assign dout = dout0;
|
||||
|
||||
endmodule
|
||||
|
||||
|
|
@ -0,0 +1,197 @@
|
|||
//+FHDR--------------------------------------------------------------------------------------------------------
|
||||
// Company:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// File Name : duc_hb3_shift.v
|
||||
// Department :
|
||||
// Author :
|
||||
// Author's Tel :
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Relese History
|
||||
// Version Date Author Description
|
||||
// 0.8 2024-03-26 thfu modify delay
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Keywords :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Parameter
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Purpose :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Target Device:
|
||||
// Tool versions:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Reuse Issues
|
||||
// Reset Strategy:
|
||||
// Clock Domains:
|
||||
// Critical Timing:
|
||||
// Asynchronous I/F:
|
||||
// Synthesizable (y/n):
|
||||
// Other:
|
||||
//-FHDR--------------------------------------------------------------------------------------------------------
|
||||
module DUC_HB3_TOP_S2 (clkl,
|
||||
rstn,
|
||||
din0,
|
||||
din1,
|
||||
din2,
|
||||
din3,
|
||||
dout_p0,
|
||||
dout_p1,
|
||||
dout_p2,
|
||||
dout_p3,
|
||||
dout_p4,
|
||||
dout_p5,
|
||||
dout_p6,
|
||||
dout_p7
|
||||
);
|
||||
input clkl,rstn;
|
||||
input [15:0] din0;
|
||||
input [15:0] din1;
|
||||
input [15:0] din2;
|
||||
input [15:0] din3;
|
||||
|
||||
output [15:0] dout_p0;
|
||||
output [15:0] dout_p1;
|
||||
output [15:0] dout_p2;
|
||||
output [15:0] dout_p3;
|
||||
output [15:0] dout_p4;
|
||||
output [15:0] dout_p5;
|
||||
output [15:0] dout_p6;
|
||||
output [15:0] dout_p7;
|
||||
|
||||
|
||||
reg [15:0] din_r1;
|
||||
reg [15:0] din_r2;
|
||||
reg [15:0] din_r3;
|
||||
reg [15:0] din_r4;
|
||||
reg [15:0] din_r5;
|
||||
reg [15:0] din_r6;
|
||||
reg [15:0] din_r7;
|
||||
reg [15:0] din_r8;
|
||||
reg [15:0] din_r9;
|
||||
reg [15:0] din_r10;
|
||||
reg [15:0] din_r11;
|
||||
reg [15:0] din_r12;
|
||||
reg [15:0] din_r13;
|
||||
reg [15:0] din_r14;
|
||||
reg [15:0] din_r15;
|
||||
reg [15:0] din_r16;
|
||||
reg [15:0] din_r17;
|
||||
reg [15:0] din_r18;
|
||||
reg [15:0] din_r19;
|
||||
reg [15:0] din_r20;
|
||||
|
||||
always@(posedge clkl or negedge rstn)
|
||||
if(!rstn)
|
||||
begin
|
||||
din_r1 <= 'b0;
|
||||
din_r2 <= 'b0;
|
||||
din_r3 <= 'b0;
|
||||
din_r4 <= 'b0;
|
||||
din_r5 <= 'b0;
|
||||
din_r6 <= 'b0;
|
||||
din_r7 <= 'b0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
din_r1 <= din3;
|
||||
din_r5 <= din_r1;
|
||||
din_r9 <= din_r5;
|
||||
din_r13 <= din_r9;
|
||||
din_r17 <= din_r13;
|
||||
|
||||
|
||||
din_r2 <= din2;
|
||||
din_r6 <= din_r2;
|
||||
din_r10 <= din_r6;
|
||||
din_r14 <= din_r10;
|
||||
din_r18 <= din_r14;
|
||||
|
||||
|
||||
din_r3 <= din1;
|
||||
din_r7 <= din_r3;
|
||||
din_r11 <= din_r7;
|
||||
din_r15 <= din_r11;
|
||||
din_r19 <= din_r15;
|
||||
|
||||
din_r4 <= din0;
|
||||
din_r8 <= din_r4;
|
||||
din_r12 <= din_r8;
|
||||
din_r16 <= din_r12;
|
||||
din_r20 <= din_r16;
|
||||
|
||||
end
|
||||
|
||||
|
||||
|
||||
|
||||
DUC_HB3 inst0_duc_hb3(
|
||||
.clk (clkl),
|
||||
.rstn (rstn),
|
||||
.din_0 (din3),
|
||||
.din_1 (din2),
|
||||
.din_2 (din1),
|
||||
.din_3 (din0),
|
||||
.din_4 (din_r1),
|
||||
.din_5 (din_r2),
|
||||
.din_6 (din_r3),
|
||||
.din_7 (din_r4),
|
||||
.dout (dout_p1)
|
||||
);
|
||||
|
||||
|
||||
assign dout_p0 = din_r17;
|
||||
|
||||
|
||||
DUC_HB3 inst1_duc_hb3(
|
||||
.clk (clkl),
|
||||
.rstn (rstn),
|
||||
.din_0 (din2),
|
||||
.din_1 (din1),
|
||||
.din_2 (din0),
|
||||
.din_3 (din_r1),
|
||||
.din_4 (din_r2),
|
||||
.din_5 (din_r3),
|
||||
.din_6 (din_r4),
|
||||
.din_7 (din_r5),
|
||||
.dout (dout_p3)
|
||||
);
|
||||
|
||||
assign dout_p2 = din_r18;
|
||||
|
||||
DUC_HB3 inst2_duc_hb3(
|
||||
.clk (clkl),
|
||||
.rstn (rstn),
|
||||
.din_0 (din1),
|
||||
.din_1 (din0),
|
||||
.din_2 (din_r1),
|
||||
.din_3 (din_r2),
|
||||
.din_4 (din_r3),
|
||||
.din_5 (din_r4),
|
||||
.din_6 (din_r5),
|
||||
.din_7 (din_r6),
|
||||
.dout (dout_p5)
|
||||
);
|
||||
|
||||
assign dout_p4 = din_r19;
|
||||
|
||||
DUC_HB3 inst3_duc_hb3(
|
||||
.clk (clkl),
|
||||
.rstn (rstn),
|
||||
.din_0 (din0),
|
||||
.din_1 (din_r1),
|
||||
.din_2 (din_r2),
|
||||
.din_3 (din_r3),
|
||||
.din_4 (din_r4),
|
||||
.din_5 (din_r5),
|
||||
.din_6 (din_r6),
|
||||
.din_7 (din_r7),
|
||||
.dout (dout_p7)
|
||||
);
|
||||
|
||||
assign dout_p6 = din_r20;
|
||||
endmodule
|
||||
|
||||
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue