commit af5b47d92092d8369c5f9b0a946ed40741fd2355 Author: thfu <2779155576@qq.com> Date: Tue Jun 25 16:41:01 2024 +0800 first commit diff --git a/case1/Makefile b/case1/Makefile new file mode 100644 index 0000000..7c14990 --- /dev/null +++ b/case1/Makefile @@ -0,0 +1,17 @@ +VCS = vcs -full64 -sverilog +lint=TFIPC-L +v2k -debug_access+all +define+DUMP_FSDB -lca -q -timescale=1ns/1ps +nospecify -P /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/pli.a -l compile.log -R +plusarg_save +ntb_random_seed_automatic -cm line+cond+fsm+tgl+branch + +SIMV = ./simv -l sim.log -cm_dir ./coverage/test1db -cm line+cond+fsm+tgl+branch +all:comp run + +comp: + ${VCS} -f files.f +incdir+./../rtl/qubitmcu +run: + ${SIMV} +file: + find ../../rtl -name "*.*v" > files.f +dbg: + verdi -sverilog -f files.f -top TB -nologo & +cov: + urg -lca -dir simv.vdb -report both -dir ./coverage/test1db +clean: + rm -rf DVE* simv* *log ucli.key verdiLog urgReport csrc novas.conf novas_dump.log *.fsdb *.dat *.daidir *.vdb *.vf *.txt both coverage *~ diff --git a/case1/case6.sv b/case1/case6.sv new file mode 100644 index 0000000..ba5db82 --- /dev/null +++ b/case1/case6.sv @@ -0,0 +1,30 @@ +//2024-06-24 linear search for sys +program case6(spi_if my_if,pllreg_if pll_if,dacreg_if dac_if,sysreg_if sys_if,mcureg_if mcu_if,awgreg_if awg_if,sram_if xif); + + env my_env; + + initial begin + + my_env = new(); + + my_env.wif = my_if; + my_env.pif = pll_if; + my_env.dif = dac_if; + my_env.vif = sys_if; + my_env.mif = mcu_if; + my_env.aif = awg_if; + my_env.xif = xif; + my_env.pktnum = 30; + + + my_env.build(); + + my_env.run(); + + //$display($get_coverage()); + + end + +endprogram + + diff --git a/case1/files.f b/case1/files.f new file mode 100644 index 0000000..9639644 --- /dev/null +++ b/case1/files.f @@ -0,0 +1,129 @@ +../rtl/define/chip_define.v +../rtl/qubitmcu/qbmcu_defines.v +../tb/spi_tb/spi_if.sv +../tb/sysreg_tb/sysreg_if.sv +../tb/pllreg_tb/pllreg_if.sv +../tb/mcureg_tb/mcureg_if.sv +../tb/awgreg_tb/awgreg_if.sv +spi_trans.sv +spi_driver.sv +../tb/spi_tb/spi_monitor.sv +../tb/spi_tb/spi_scb.sv +../tb/sram_tb/ramreg_scb.sv +../tb/sram_tb/ram_refmodel.sv +../tb/sysreg_tb/sysreg_trans.sv +../tb/sysreg_tb/sysreg_monitor.sv +../tb/sysreg_tb/sys_refmodel.sv +../tb/sysreg_tb/sysreg_scb.sv +../tb/pllreg_tb/pllreg_trans.sv +../tb/pllreg_tb/pllreg_driver.sv +../tb/pllreg_tb/pllreg_monitor.sv +../tb/pllreg_tb/pll_refmodel.sv +../tb/pllreg_tb/pllreg_scb.sv +../tb/dacreg_tb/dacreg_trans.sv +../tb/dacreg_tb/dacreg_if.sv +../tb/dacreg_tb/dacreg_monitor.sv +../tb/dacreg_tb/dac_refmodel.sv +../tb/dacreg_tb/dacreg_scb.sv +../tb/mcureg_tb/mcureg_trans.sv +../tb/mcureg_tb/mcureg_monitor.sv +../tb/mcureg_tb/mcu_refmodel.sv +../tb/mcureg_tb/mcureg_scb.sv +../tb/awgreg_tb/awgreg_trans.sv +../tb/awgreg_tb/awgreg_monitor.sv +../tb/awgreg_tb/awg_refmodel.sv +../tb/awgreg_tb/awgreg_scb.sv +../tb/env.sv +case6.sv +../tb/tb.sv +../rtl/memory/sram_if.sv +../rtl/awg/awg_ctrl.v +../rtl/awg/awg_top.sv +../rtl/awg/codeword_decode.v +../rtl/awg/ctrl_regfile.v +../rtl/awg/param_lut.sv +../rtl/awg/modout_mux.v +../rtl/clk/intpll_regfile.v +../rtl/comm/sirv_gnrl_dffs.v +../rtl/comm/sirv_gnrl_xchecker.v +../rtl/dac_regfile/dac_regfile.v +../rtl/debug/debug_sample.sv +../rtl/debug/debug_top.sv +../rtl/memory/dpram.v +../rtl/memory/dpram_model.v +../rtl/memory/sram_dmux.sv +../rtl/memory/tsdn28hpcpuhdb128x128m4mw_170a_ffg0p99v0c.v +../rtl/memory/tsdn28hpcpuhdb4096x32m4mw_170a_ffg0p99v0c.v +../rtl/memory/tsdn28hpcpuhdb64x32m4mw_170a_ffg0p99v0c.v +../rtl/memory/tsmc_dpram.v +../rtl/modem/ampmod.v +../rtl/modem/baisset.v +../rtl/modem/freqmod.v +../rtl/nco/coef_c.v +../rtl/nco/coef_s.v +../rtl/nco/cos_op.v +../rtl/nco/nco.v +../rtl/nco/nco_ch1.v +../rtl/nco/p_nco.v +../rtl/nco/p_nco_ch1.v +../rtl/nco/ph2amp.v +../rtl/nco/pipe_acc_48bit.v +../rtl/nco/pipe_add_48bit.v +../rtl/nco/sin_op.v +../rtl/perips/DW03_updn_ctr.v +../rtl/perips/qbmcu_busdecoder.v +../rtl/perips/mcu_regfile.sv +../rtl/qubitmcu/qbmcu.v +../rtl/qubitmcu/qbmcu_datalock.v +../rtl/qubitmcu/qbmcu_decode.v +../rtl/qubitmcu/qbmcu_exu.v +../rtl/qubitmcu/qbmcu_exu_alu.v +../rtl/qubitmcu/qbmcu_exu_bjp.v +../rtl/qubitmcu/qbmcu_exu_dpath.v +../rtl/qubitmcu/qbmcu_exu_ext.v +../rtl/qubitmcu/qbmcu_exu_lsuagu.v +../rtl/qubitmcu/qbmcu_fsm.v +../rtl/qubitmcu/qbmcu_ifu.v +../rtl/qubitmcu/qbmcu_regfile.v +../rtl/qubitmcu/qbmcu_wbck.v +../rtl/rstgen/rst_gen_unit.v +../rtl/rstgen/rst_sync.v +../rtl/spi/spi_bus_decoder.sv +../rtl/spi/spi_pll.v +../rtl/spi/spi_slave.v +../rtl/spi/spi_sys.v +../rtl/sync/sync_buf.sv +../rtl/system_regfile/system_regfile.v +../rtl/top/channel_top.sv +../rtl/top/digital_top.sv +../rtl/top/xyz_chip_top.v +../rtl/top/z_data_mux.v +../rtl/xy_dsp/dacif/dacif.v +../rtl/xy_dsp/dsp_top/xy_dsp.v +../rtl/xy_dsp/duc/duc_hb1_pipe_shift.v +../rtl/xy_dsp/duc/duc_hb1_top.v +../rtl/xy_dsp/duc/duc_hb2_pipe_shift.v +../rtl/xy_dsp/duc/duc_hb2_top_s.v +../rtl/xy_dsp/duc/duc_hb3_pipe_shift.v +../rtl/xy_dsp/duc/duc_hb3_top_s2.v +../rtl/xy_dsp/duc/duc_hb4_pipe_shift.v +../rtl/xy_dsp/duc/duc_hb4_top_s3.v +../rtl/xy_dsp/duc/duc4.v +../rtl/xy_dsp/qam/qam_top.v +../rtl/xy_dsp/qam/ssb.v +../rtl/dem/DAC_DEM_4.v +../rtl/dem/DAC_DEM_16.v +../rtl/dem/DAC_DEM.v +../tb/digital_top/DW_mult_pipe.v +../tb/digital_top/DW01_addsub.v +../tb/digital_top/DW02_mult.v +../tb/digital_top/clk_gen.v +../tb/chip_top/thermo2binary_top.v +../tb/chip_top/thermo7_binary3.v +../tb/chip_top/thermo15_binary4.v +../rtl/io/iopad.v +../rtl/io/tphn28hpcpgv18.v +../rtl/comm/syncer.v +../rtl/qubitmcu/qbmcu_undefines.v +../rtl/define/chip_undefine.v + diff --git a/case1/novas.rc b/case1/novas.rc new file mode 100644 index 0000000..1c13f13 --- /dev/null +++ b/case1/novas.rc @@ -0,0 +1,1313 @@ +@verdi rc file Version 1.0 +[Library] +work = ./work +[Annotation] +3D_Active_Annotation = FALSE +[CommandSyntax.finsim] +InvokeCommand = +FullFileName = TRUE +Separator = . +SimPromptSign = ">" +HierNameLevel = 1 +RunContinue = "continue" +Finish = "quit" +UseAbsTime = FALSE +NextTime = "run 1" +NextNTime = "run ${SimBPTime}" +NextEvent = "run 1" +Reset = +ObjPosBreak = "break posedge ${SimBPObj}" +ObjNegBreak = "break negedge ${SimBPObj}" +ObjAnyBreak = "break change ${SimBPObj}" +ObjLevelBreak = +LineBreak = "breakline ${SimBPFile} ${SimBPLine}" +AbsTimeBreak = "break abstimeaf ${SimBPTime}" +RelTimeBreak = "break reltimeaf ${SimBPTime}" +EnableBP = "breakon ${SimBPId}" +DisableBP = "breakoff ${SimBPId}" +DeleteBP = "breakclr ${SimBPId}" +DeleteAllBP = "breakclr" +SimSetScope = "cd ${SimDmpObj}" +[CommandSyntax.ikos] +InvokeCommand = "setvar debussy true;elaborate -p ${SimTop} -s ${SimArch}; run until 0;fsdbInteractive; " +FullFileName = TRUE +NeedTimeUnit = TRUE +NormalizeTimeUnit = TRUE +Separator = / +HierNameLevel = 2 +RunContinue = "run" +Finish = "exit" +NextTime = "run ${SimBPTime} ${SimTimeUnit}" +NextNTime = "run for ${SimBPTime} ${SimTimeUnit}" +NextEvent = "step 1" +Reset = "reset" +ObjPosBreak = "stop if ${SimBPObj} = \"'1'\"" +ObjNegBreak = "stop if ${SimBPObj} = \"'0'\"" +ObjAnyBreak = +ObjLevelBreak = "stop if ${SimBPObj} = ${SimBPValue}" +LineBreak = "stop at ${SimBPFile}:${SimBPLine}" +AbsTimeBreak = +RelTimeBreak = +EnableBP = "enable ${SimBPId}" +DisableBP = "disable ${SimBPId}" +DeleteBP = "delete ${SimBPId}" +DeleteAllBP = "delete *" +[CommandSyntax.verisity] +InvokeCommand = +FullFileName = FALSE +Separator = . +SimPromptSign = "> " +HierNameLevel = 1 +RunContinue = "." +Finish = "$finish;" +NextTime = "$db_steptime(1);" +NextNTime = "$db_steptime(${SimBPTime});" +NextEvent = "$db_step;" +SimSetScope = "$scope(${SimDmpObj});" +Reset = "$reset;" +ObjPosBreak = "$db_breakonposedge(${SimBPObj});" +ObjNegBreak = "$db_breakonnegedge(${SimBPObj});" +ObjAnyBreak = "$db_breakwhen(${SimBPObj});" +ObjLevelBreak = "$db_breakwhen(${SimBPObj}, ${SimBPValue});" +LineBreak = "$db_breakatline(${SimBPLine}, ${SimBPScope}, \"${SimBPFile}\");" +AbsTimeBreak = "$db_breakbeforetime(${SimBPTime});" +RelTimeBreak = "$db_breakbeforetime(${SimBPTime});" +EnableBP = "$db_enablebreak(${SimBPId});" +DisableBP = "$db_disablebreak(${SimBPId});" +DeleteBP = "$db_deletebreak(${SimBPId});" +DeleteAllBP = "$db_deletebreak;" +FSDBInit = "$novasInteractive;" +FSDBDumpvars = "$novasDumpvars(0, ${SimDmpObj});" +FSDBDumpsingle = "$novasDumpsingle(${SimDmpObj});" +FSDBDumpvarsInFile = "$novasDumpvarsToFile(\"${SimDmpFile}\");" +FSDBDumpMem = "$novasDumpMemNow(${SimDmpObj}, ${SimDmpBegin}, ${SimDmpSize});" +[CoverageDetail] +cross_filter_limit = 1000 +branch_limit_vector_display = 50 +showgrid = TRUE +reuseFirst = TRUE +justify = TRUE +scrollbar_mode = per pane +test_combo_left_truncate = TRUE +instance_combo_left_truncate = TRUE +loop_navigation = TRUE +condSubExpr = 20 +tglMda = 1000 +linecoverable = 100000 +lineuncovered = 50000 +tglcoverable = 30000 +tgluncovered = 30000 +pendingMax = 1000 +show_full_more = FALSE +[CoverageHier] +showgrid = FALSE +[CoverageWeight] +Assert = 1 +Covergroup = 1 +Line = 1 +Condition = 1 +Toggle = 1 +FSM = 1 +Branch = 1 +[DesignTree] +IfShowModule = {TRUE, FALSE} +[DisabledMessages] +version = Verdi_O-2018.09-SP2 +152174613 = disabled +[Editor] +editorName = TurboEditor +[Emacs] +EmacsFont = "Clean 14" +EmacsBG = white +EmacsFG = black +[Exclusion] +enableAsDefault = TRUE +saveAsDefault = TRUE +saveManually = TRUE +illegalBehavior = FALSE +DisplayExcludedItem = FALSE +adaptiveExclusion = TRUE +warningExcludeInstance = TRUE +favorite_exclude_annotation = "" +[FSM] +viewport = 65 336 387 479 +WndBk-FillColor = Gray3 +Background-FillColor = gray5 +prefKey_Link-FillColor = yellow4 +prefKey_Link-TextColor = black +Trap = red3 +Hilight = blue4 +Window = Gray3 +Selected = white +Trans. = green2 +State = black +Init. = black +SmartTips = TRUE +VectorFont = FALSE +StopAskBkgndColor = FALSE +ShowStateAction = FALSE +ShowTransAction = FALSE +ShowTransCond = FALSE +StateLable = NAME +StateValueRadix = ORIG +State-LineColor = ID_BLACK +State-LineWidth = 1 +State-FillColor = ID_BLUE2 +State-TextColor = ID_WHITE +Init_State-LineColor = ID_BLACK +Init_State-LineWidth = 2 +Init_State-FillColor = ID_YELLOW2 +Init_State-TextColor = ID_BLACK +Reset_State-LineColor = ID_BLACK +Reset_State-LineWidth = 2 +Reset_State-FillColor = ID_YELLOW7 +Reset_State-TextColor = ID_BLACK +Trap_State-LineColor = ID_RED2 +Trap_State-LineWidth = 2 +Trap_State-FillColor = ID_CYAN5 +Trap_State-TextColor = ID_RED2 +State_Action-LineColor = ID_BLACK +State_Action-LineWidth = 1 +State_Action-FillColor = ID_WHITE +State_Action-TextColor = ID_BLACK +Junction-LineColor = ID_BLACK +Junction-LineWidth = 1 +Junction-FillColor = ID_GREEN2 +Junction-TextColor = ID_BLACK +Connection-LineColor = ID_BLACK +Connection-LineWidth = 1 +Connection-FillColor = ID_GRAY5 +Connection-TextColor = ID_BLACK +prefKey_Port-LineColor = ID_BLACK +prefKey_Port-LineWidth = 1 +prefKey_Port-FillColor = ID_ORANGE6 +prefKey_Port-TextColor = ID_YELLOW2 +Transition-LineColor = ID_BLACK +Transition-LineWidth = 1 +Transition-FillColor = ID_WHITE +Transition-TextColor = ID_BLACK +Trans_Condition-LineColor = ID_BLACK +Trans_Condition-LineWidth = 1 +Trans_Condition-FillColor = ID_WHITE +Trans_Condition-TextColor = ID_ORANGE2 +Trans_Action-LineColor = ID_BLACK +Trans_Action-LineWidth = 1 +Trans_Action-FillColor = ID_WHITE +Trans_Action-TextColor = ID_GREEN2 +SelectedSet-LineColor = ID_RED2 +SelectedSet-LineWidth = 1 +SelectedSet-FillColor = ID_RED2 +SelectedSet-TextColor = ID_WHITE +StickSet-LineColor = ID_ORANGE5 +StickSet-LineWidth = 1 +StickSet-FillColor = ID_PURPLE6 +StickSet-TextColor = ID_BLACK +HilightSet-LineColor = ID_RED5 +HilightSet-LineWidth = 1 +HilightSet-FillColor = ID_RED7 +HilightSet-TextColor = ID_BLUE5 +ControlPoint-LineColor = ID_BLACK +ControlPoint-LineWidth = 1 +ControlPoint-FillColor = ID_WHITE +Bundle-LineColor = ID_BLACK +Bundle-LineWidth = 1 +Bundle-FillColor = ID_WHITE +Bundle-TextColor = ID_BLUE4 +QtBackground-FillColor = ID_GRAY6 +prefKey_Link-LineColor = ID_ORANGE2 +prefKey_Link-LineWidth = 1 +Selection-LineColor = ID_BLUE2 +Selection-LineWidth = 1 +[FSM_Dlg-Print] +Orientation = Landscape +[FileBrowser] +nWaveOpenFsdbDirHistory = "\"/home/ICer/thfu/XYZ/Test/v1.6/case1/TB1.fsdb\"" +[Form] +version = Verdi_O-2018.09-SP2 +[General] +autoSaveSession = FALSE +TclAutoSource = +cmd_enter_form = FALSE +SyncBrowserDir = TRUE +version = Verdi_O-2018.09-SP2 +SignalCaseInSensitive = FALSE +ShowWndCtntDuringResizing = FALSE +[GlobalProp] +ErrWindow_Font = Helvetica_M_R_12 +[Globals] +app_default_font = Bitstream Vera Sans,10,-1,5,50,0,0,0,0,0 +app_fixed_width_font = Courier,10,-1,5,50,0,0,0,0,0 +text_encoding = Unicode(utf8) +smart_resize = TRUE +smart_resize_child_limit = 2000 +tooltip_max_width = 200 +tooltip_max_height = 20 +tooltip_viewer_key = F3 +tooltip_display_time = 1000 +bookmark_name_length_limit = 12 +disable_tooltip = FALSE +auto_load_source = TRUE +max_array_size = 4096 +filter_when_typing = TRUE +filter_keep_children = TRUE +filter_syntax = Wildcards +filter_keystroke_interval = 800 +filter_case_sensitive = FALSE +filter_full_path = FALSE +load_detail_for_funcov = FALSE +sort_limit = 100000 +ignoreDBVersionChecking = FALSE +[HB] +ViewSchematic = FALSE +windowLayout = 0 0 804 500 182 214 804 148 +import_filter = *.v; *.vc; *.f +designTreeFont = *-adobe-courier-medium-r-*-*-12-*-*-*-*-*-iso8859-* +import_filter_vhdl = *.vhd; *.vhdl; *.f +import_default_language = Verilog +import_filter_verilog = *.v; *.vc; *.f +simulation_file_type = *.fsdb;*.fsdb.gz;*.fsdb.bz2;*.ff;*.dump +PrefetchViewableAnnot = TRUE +[Hier] +filterTimeout = 1500 +[ImportLiberty] +SearchPriority = .lib++ +bSkipStateCell = False +bImportPowerInfo = False +bSkipFFCell = False +bScpecifyCellNameCase = False +bSpecifyPinNameCase = False +CellNameToCase = +PinNameToCase = +[Language] +EditWindow_Font = COURIER12 +Background = ID_WHITE +Comment = ID_GRAY4 +Keyword = ID_BLUE5 +UserKeyword = ID_GREEN2 +Text = ID_BLACK +SelText = ID_WHITE +SelBackground = ID_BLUE2 +[Library.Ikos] +pack = ./work.lib++ +vital = ./work.lib++ +work = ./work.lib++ +std = ${dls_std}.lib++ +ieee = ${dls_ieee}.lib++ +synopsys = ${dls_synopsys}.lib++ +silc = ${dls_silc}.lib++ +ikos = ${dls_ikos}.lib++ +novas = ${VOYAGER_LIB_VHDL}/${VOYAGER_MACHINE}/novas.lib++ +[MDT] +ART_RF_SP = spr[0-9]*bx[0-9]* +ART_RF_2P = dpr[0-9]*bx[0-9]* +ART_SRAM_SP = spm[0-9]*bx[0-9]* +ART_SRAM_DP = dpm[0-9]*bx[0-9]* +VIR_SRAM_SP = hdsd1_[0-9]*x[0-9]*cm4sw1 +VIR_SRAM_DP = hdsd2_[0-9]*x[0-9]*cm4sw1 +VIR_RF_SP = rfsd1_[0-9]*x[0-9]*cm2sw0 +VIR_RF_DP = rfsd2_[0-9]*x[0-9]*cm2sw1 +VIR_STAR_SRAM_SP = shsd1_[0-9]*x[0-9]*cm4sw0 +[NPExpanding] +functiongroups = FALSE +modules = FALSE +[NPFilter] +showAssertion = TRUE +showCoverGroup = TRUE +showProperty = TRUE +showSequence = TRUE +showDollarUnit = TRUE +[OldFontRC] +Wave_legend_window_font = -f COURIER12 -c ID_CYAN5 +Wave_value_window_font = -f COURIER12 -c ID_CYAN5 +Wave_curve_window_font = -f COURIER12 -c ID_CYAN5 +Wave_group_name_font = -f COURIER12 -c ID_GREEN5 +Wave_ruler_value_font = -f COURIER12 -c ID_CYAN5 +Wave_analog_ruler_value_font = -f COURIER12 -c ID_CYAN5 +Wave_comment_string_font = -f COURIER12 -c ID_RED5 +HB_designTreeFont = *-adobe-courier-medium-r-*-*-12-*-*-*-*-*-iso8859-* +Text_font = COURIER12 +nMemory_font = Fixed 14 +Wave_getsignal_form_font = -f COURIER12 +Text_annotFont = Helvetica_M_R_10 +[OtherEditor] +cmd1 = "xterm -font 9x15 -fg black -bg gray -e" +name = "vi" +options = "+${CurLine} ${CurFullFileName}" +[Power] +PowerDownInstance = ID_GRAY1 +RetentionSignal = ID_YELLOW2 +IsolationSignal = ID_RED6 +LevelShiftedSignal = ID_GREEN6 +PowerSwitchObject = ID_ORANGE5 +AlwaysOnObject = ID_GREEN5 +PowerNet = ID_RED2 +GroundNet = ID_RED2 +SimulationOnly = ID_CYAN3 +SRSN/SPA = ID_CYAN3 +CNSSignal = ID_CYAN3 +RPTRSignal = ID_CYAN3 +AcknowledgeSignal = ID_CYAN3 +BoundaryPort = ID_CYAN3 +DisplayInstrumentedCell = TRUE +ShowCmdByFile = FALSE +ShowPstAnnot = FALSE +ShowIsoSymbol = TRUE +ExtractIsoSameNets = FALSE +AnnotateSignal = TRUE +HighlightPowerObject = TRUE +HighlightPowerDomain = TRUE +TraceThroughInstruLowPower = FALSE +BrightenPowerColorInSchematicWindow = FALSE +ShowAlias = FALSE +ShowVoltage = TRUE +MatchTreeNodesCaseInsensitive = FALSE +SearchHBNodeDynamically = FALSE +ContinueTracingSupplyOrLogicNet = FALSE +[Print] +PrinterName = lp +FileName = test.ps +PaperSize = A4 - 210x297 (mm) +ColorPrint = FALSE +[PropertyTools] +saveWaveformStat = TRUE +savePropStat = FALSE +savePropDtl = TRUE +[QtDialog] +openFileDlg = 978,491,602,483 +QwUserAskDlg = 1118,667,324,134 +[Relationship] +hideRecursiceNode = FALSE +[Session Cache] +3 = string (session file name) +4 = string (session file name) +5 = string (session file name) +1 = /home/ICer/thfu/XYZ/Test/v1.6/case1/verdiLog/novas_autosave.ses +2 = /home/ICer/verdiLog/novas_autosave.ses +[Simulation] +scsPath = scsim +scsOption = +xlPath = verilog +xlOption = +ncPath = ncsim +ncOption = -f ncsim.args +osciPath = gdb +osciOption = +vcsPath = simv +vcsOption = +mtiPath = vsim +mtiOption = +vhncPath = ncsim +vhncOption = -log debussy.nc.log +mixncPath = ncsim +mixncOption = -log debussy.mixnc.log +speedsimPath = +speedsimOption = +mti_vlogPath = vsim +mti_vlogOption = novas_vlog +vcs_mixPath = simv +vcs_mixOption = -vhdlrun "-vhpi debussy:FSDBDumpCmd" +scs_mixPath = scsim +scs_mixOption = -vhpi debussy:FSDBDumpCmd +interactiveDebugging = {True, False} +KeepBreakPoints = False +ScsDebugAll = False +simType = {vcssv, xl, nc, vcs, mti, mti_vlog, vhnc, scs, mixnc} +thirdpartyIdx = -1 +iscCmdSep = FALSE +NoAppendOption = False +[SimulationPlus] +xlPath = verilog +xlOption = +ncPath = ncsim +ncOption = -f ncsim.args +vcsPath = simv +vcsOption = +mti_vlogPath = vsim +mti_vlogOption = novas_vlog +mtiPath = vsim +mtiOption = +vhncPath = ncsim +vhncOption = -log debussy.nc.log +speedsimPath = verilog +speedsimOption = +mixncPath = ncsim +mixncOption = -log debussy.mixnc.log +scsPath = scsim +scsOption = +vcs_mixPath = simv +vcs_mixOption = -vhdlrun "-vhpi debussy:FSDBDumpCmd" +scs_mixPath = scsim +scs_mixOption = -vhpi debussy:FSDBDumpCmd +vcs_svPath = simv +vcs_svOption = +simType = vcssv +thirdpartyIdx = -1 +interactiveDebugging = FALSE +KeepBreakPoints = FALSE +iscCmdSep = FALSE +ScsDebugAll = FALSE +NoAppendOption = FALSE +invokeSimPath = work +[SimulationPlus2] +eventDumpUnfinish = FALSE +[Source] +wordWrapOn = TRUE +viewReuse = TRUE +lineNumberOn = TRUE +warnOutdatedDlg = TRUE +showEncrypt = FALSE +loadInclude = FALSE +showColorForActive = FALSE +tabWidth = 8 +editor = vi +reload = Never +sync_active_to_source = TRUE +navigateAsColored = FALSE +navigateCovered = FALSE +navigateUncovered = TRUE +navigateExcluded = FALSE +not_ask_for_source_path = FALSE +expandMacroOn = TRUE +expandMacroInstancesThreshold = 10000 +[SourceVHDL] +vhSimType = ModelSim +ohSimType = VerilogXL +[TclShell] +nLineSize = 1024 +[Test] +verbose_progress = FALSE +[TestBenchBrowser] +-showUVMDynamicHierTreeWin = FALSE +[Text] +hdlTypeName = blue4 +hdlLibrary = blue4 +viewport = 396 392 445 487 +hdlOther = ID_BLACK +hdlComment = ID_GRAY1 +hdlKeyword = ID_BLUE5 +hdlEntity = ID_BLACK +hdlEntityInst = ID_BLACK +hdlSignal = ID_RED2 +hdlInSignal = ID_RED2 +hdlOutSignal = ID_RED2 +hdlInOutSignal = ID_RED2 +hdlOperator = ID_BLACK +hdlMinus = ID_BLACK +hdlSymbol = ID_BLACK +hdlString = ID_BLACK +hdlNumberBase = ID_BLACK +hdlNumber = ID_BLACK +hdlLiteral = ID_BLACK +hdlIdentifier = ID_BLACK +hdlSystemTask = ID_BLACK +hdlParameter = ID_BLACK +hdlIncFile = ID_BLACK +hdlDataFile = ID_BLACK +hdlCDSkipIf = ID_GRAY1 +hdlMacro = ID_BLACK +hdlMacroValue = ID_BLACK +hdlPlainText = ID_BLACK +hdlOvaId = ID_PURPLE2 +hdlPslId = ID_PURPLE2 +HvlEId = ID_BLACK +HvlVERAId = ID_BLACK +hdlEscSignal = ID_BLACK +hdlEscInSignal = ID_BLACK +hdlEscOutSignal = ID_BLACK +hdlEscInOutSignal = ID_BLACK +textBackgroundColor = ID_GRAY6 +textHiliteBK = ID_BLUE5 +textHiliteText = ID_WHITE +textTracedMark = ID_GREEN2 +textLineNo = ID_BLACK +textFoldedLineNo = ID_RED5 +textUserKeyword = ID_GREEN2 +textParaAnnotText = ID_BLACK +textFuncAnnotText = ID_BLUE2 +textAnnotText = ID_BLACK +textUserDefAnnotText = ID_BLACK +ComputedSignal = ID_PURPLE5 +textAnnotTextShadow = ID_WHITE +parenthesisBGColor = ID_YELLOW5 +codeInParenthesis = ID_CYAN5 +text3DLight = ID_WHITE +text3DShadow = ID_BLACK +textHvlDriver = ID_GREEN3 +textHvlLoad = ID_YELLOW3 +textHvlDriverLoad = ID_BLUE3 +irOutline = ID_RED2 +irDriver = ID_YELLOW5 +irLoad = ID_BLACK +irBookMark = ID_YELLOW2 +irIndicator = ID_WHITE +irBreakpoint = ID_GREEN5 +irCurLine = ID_BLUE5 +hdlVhEntity = ID_BLACK +hdlArchitecture = ID_BLACK +hdlPackage = ID_BLUE5 +hdlRefPackage = ID_BLUE5 +hdlAlias = ID_BLACK +hdlGeneric = ID_BLUE5 +specialAnnotShadow = ID_BLUE1 +hdlZeroInHead = ID_GREEN2 +hdlZeroInComment = ID_GREEN2 +hdlPslHead = ID_BLACK +hdlPslComment = ID_BLACK +hdlSynopsysHead = ID_GREEN2 +hdlSynopsysComment = ID_GREEN2 +pdmlIdentifier = ID_BLACK +pdmlCommand = ID_BLACK +pdmlMacro = ID_BLACK +font = COURIER12 +annotFont = Helvetica_M_R_10 +[Text.1] +viewport = -1 27 2560 1337 45 +[TextPrinter] +Orientation = Landscape +Indicator = FALSE +LineNum = TRUE +FontSize = 7 +Column = 2 +Annotation = TRUE +[Texteditor] +TexteditorFont = "Clean 14" +TexteditorBG = white +TexteditorFG = black +[ThirdParty] +ThirdPartySimTool = verisity surefire ikos finsim +[TurboEditor] +autoBackup = TRUE +[UserButton.mixnc] +Button1 = "Dump All Signals" "call fsdbDumpvars\n" +Button2 = "Next 1000 Time" "run 1000 -relative\n" +Button3 = "Next ? Time" "run ${Arg:Next Time} -relative\n" +Button4 = "Run Next" "run -next\n" +Button5 = "Run Step" "run -step\n" +Button6 = "Run Return" "run -return\n" +Button7 = "Show Variables" "value {${NCSelVars}}\n" +Button8 = "FSDB Ver" "call fsdbVersion" +Button9 = "Dump On" "call fsdbDumpon" +Button10 = "Dump Off" "call fsdbDumpoff" +Button11 = "All Tasks" "call" +Button12 = "Dump Selected Instance" "call fsdbDumpvars 1 ${SelInst}" +[UserButton.mti] +Button1 = "Dump All Signals" "fsdbDumpvars\n" +Button2 = "Next 1000 Time" "run 1000\n" +Button3 = "Next ? Time" "run ${Arg:Next Time}\n" +Button4 = "Show Variables" "exa ${SelVars}\n" +Button5 = "Force Variable" "force -freeze ${SelVar} ${Arg:New Value} 0\n" +Button6 = "Release Variable" "noforce ${SelVar}\n" +Button7 = "Deposit Variable" "force -deposit ${SelVar} ${Arg:New Value} 0\n" +[UserButton.mti_vlog] +Button1 = "Dump All Signals" "fsdbDumpvars\n" +Button2 = "Next 1000 Time" "run 1000\n" +Button3 = "Next ? Time" "run ${Arg:Next Time}\n" +Button4 = "Show Variables" "exa ${SelVars}\n" +Button5 = "Force Variable" "force -freeze ${SelVar} ${Arg:New Value} 0\n" +Button6 = "Release Variable" "noforce ${SelVar}\n" +Button7 = "Deposit Variable" "force -deposit ${SelVar} ${Arg:New Value} 0\n" +[UserButton.nc] +Button1 = "Dump All Signals" "call fsdbDumpvars\n" +Button2 = "Next 1000 Time" "run 1000 -relative\n" +Button3 = "Next ? Time" "run ${Arg:Next Time} -relative\n" +Button4 = "Run Next" "run -next\n" +Button5 = "Run Step" "run -step\n" +Button6 = "Run Return" "run -return\n" +Button7 = "Show Variables" "value {${NCSelVars}}\n" +[UserButton.scs] +Button1 = "Dump All Signals" "call fsdbDumpvars(0, \"${TopScope}\");\n" +Button2 = "Next 1000 Time" "run 1000 \n" +Button3 = "Next ? Time" "run ${Arg:Next Time} \n" +Button4 = "Run Step" "step\n" +Button5 = "Show Variables" "ls -v {${SelVars}}\n" +[UserButton.vhnc] +Button1 = "Dump All Signals" "call fsdbDumpvars\n" +Button2 = "Next 1000 Time" "run 1000 -relative\n" +Button3 = "Next ? Time" "run ${Arg:Next Time} -relative\n" +Button4 = "Run Next" "run -next\n" +Button5 = "Run Step" "run -step\n" +Button6 = "Run Return" "run -return\n" +Button7 = "Show Variables" "value {${NCSelVars}}\n" +[UserButton.xl] +Button13 = "Dump Off" "$fsdbDumpoff;\n" +Button12 = "Dump On" "$fsdbDumpon;\n" +Button11 = "Delete Focus" "$db_deletefocus(${treeSelScope});\n" +Button10 = "Set Focus" "$db_setfocus(${treeSelScope});\n" +Button9 = "Deposit Variable" "$deposit(${SelVar},${Arg:New Value});\n" +Button8 = "Release Variable" "release ${SelVar};\n" +Button7 = "Force Variable" "force ${SelVar} = ${Arg:New Value};\n" +Button6 = "Show Variables" "$showvars(${SelVars});\n" +Button5 = "Next ? Event" "$db_step(${Arg:Next Event});\n" +Button4 = "Next Event" "$db_step(1);\n" +Button3 = "Next ? Time" "#${Arg:Next Time} $stop;.\n" +Button2 = "Next 1000 Time" "#1000 $stop;.\n" +Button1 = "Dump All Signals" "$fsdbDumpvars;\n" +[VIA] +viaLogViewerDefaultRuleOneSearchForm = "share/VIA/Apps/PredefinedRules/Misc/Onesearch_rule.rc" +[VIA.oneSearch.preference] +DefaultDisplayTimeUnit = "1.000000ns" +DefaultLogTimeUnit = "1.000000ns" +[VIA.oneSearch.preference.vgifColumnSettingRC] +[VIA.oneSearch.preference.vgifColumnSettingRC.setting0] +parRuleSets = "" +[VIA.oneSearch.preference.vgifColumnSettingRC.setting0.column0] +name = Severity +width = 60 +visualIndex = 1 +isHidden = TRUE +isUserChangeColumnVisible = FALSE +[VIA.oneSearch.preference.vgifColumnSettingRC.setting0.column1] +name = Time +width = 60 +visualIndex = 0 +isHidden = TRUE +isUserChangeColumnVisible = FALSE +[VIA.oneSearch.preference.vgifColumnSettingRC.setting0.column2] +name = Code +width = 60 +visualIndex = 2 +isHidden = TRUE +isUserChangeColumnVisible = FALSE +[VIA.oneSearch.preference.vgifColumnSettingRC.setting0.column3] +name = Type +width = 60 +visualIndex = 3 +isHidden = TRUE +isUserChangeColumnVisible = FALSE +[VIA.oneSearch.preference.vgifColumnSettingRC.setting0.column4] +name = Message +width = 2000 +visualIndex = 4 +isHidden = FALSE +isUserChangeColumnVisible = FALSE +[Vi] +ViFont = "Clean 14" +ViBG = white +ViFG = black +[Wave] +ovaEventSuccessColor = -c ID_CYAN5 +ovaEventFailureColor = -c ID_RED5 +ovaBooleanSuccessColor = -c ID_CYAN5 +ovaBooleanFailureColor = -c ID_RED5 +ovaAssertSuccessColor = -c ID_GREEN5 +ovaAssertFailureColor = -c ID_RED5 +ovaForbidSuccessColor = -c ID_GREEN5 +SigGroupRuleFile = +DisplayFileName = FALSE +waveform_vertical_scroll_bar = TRUE +scope_to_save_with_macro +open_file_dir +open_rc_file_dir +getSignalForm = 0 0 800 479 100 30 100 30 +viewPort = 0 27 2560 590 100 65 +signalSpacing = 5 +digitalSignalHeight = 15 +analogSignalHeight = 98 +commentSignalHeight = 98 +transactionSignalHeight = 98 +messageSignalHeight = 98 +minCompErrWidth = 4 +DragZoomTolerance = 4 +maxTransExpandedLayer = 10 +WaveMaxPoint = 512 +legendBackground = -c ID_BLACK +valueBackground = -c ID_BLACK +curveBackground = -c ID_BLACK +getSignalSignalList_BackgroundColor = -c ID_GRAY6 +glitchColor = -c ID_RED5 +cursor = -c ID_YELLOW5 -lw 1 -ls long_dashed +marker = -c ID_WHITE -lw 1 -ls dash_dot_l +usermarker = -c ID_GREEN5 -lw 1 -ls long_dashed +trace = -c ID_GRAY5 -lw 1 -ls long_dashed +grid = -c ID_WHITE -lw 1 -ls short_dashed +rulerBackground = -c ID_GRAY3 +rulerForeground = -c ID_YELLOW5 +busTextColor = -c ID_ORANGE8 +legendForeground = -c ID_CYAN5 +valueForeground = -c ID_CYAN5 +curveForeground = -c ID_CYAN5 +groupNameColor = -c ID_GREEN5 +commentStringColor = -c ID_RED5 +region(Active)Background = -c ID_YELLOW1 +region(NBA)Background = -c ID_RED1 +region(Re-Active)Background = -c ID_YELLOW3 +region(Re-NBA)Background = -c ID_RED3 +region(VHDL-Delta)Background = -c ID_ORANGE3 +region(Dump-Off)Background = -c ID_GRAY4 +High_Light = -c ID_GRAY2 +Input_Signal = -c ID_RED5 +Output_Signal = -c ID_GREEN5 +InOut_Signal = -c ID_BLUE5 +Net_Signal = -c ID_YELLOW5 +Register_Signal = -c ID_PURPLE5 +Verilog_Signal = -c ID_CYAN5 +VHDL_Signal = -c ID_ORANGE5 +SystemC_Signal = -c ID_BLUE7 +Dump_Off_Color = -c ID_BLUE2 +Compress_Bar_Color = -c ID_YELLOW4 +Vector_Dense_Block_Color = -c ID_ORANGE8 +Scalar_Dense_Block_Color = -c ID_GREEN6 +Analog_Dense_Block_Color = -c ID_PURPLE2 +Composite_Dense_Block_Color = -c ID_ORANGE5 +RPTR_Power_Off_Layer = -c ID_CYAN3 -stipple dots +DB_Power_Off_Layer = -c ID_BLUE4 -stipple dots +SPA_Driver_Power_Off_Layer = -c ID_ORANGE4 -stipple dots +SPA_Receiver_Power_Off_Layer = -c ID_GREEN5 -stipple dots +SRSN_Power_Off_Layer = -c ID_GREEN4 -stipple dots +Isolation_Power_Off_Layer = -c ID_RED4 -stipple dots +PD_Power_Off_Layer = -c ID_GRAY4 -stipple dots +Isolation_Layer = -c ID_RED4 -stipple vLine +Retention_Level_Trigger_Layer = -c ID_ORANGE1 -stipple fill_solid +Retention_Edge_Trigger_Layer = -c ID_YELLOW6 -stipple fill_solid +Driving_Power_Off_Layer = -c ID_YELLOW2 -stipple x +Toggle_Layer = -c ID_YELLOW4 -stipple slash +analogRealStyle = pwl +analogVoltageStyle = pwl +analogCurrentStyle = pwl +analogOthersStyle = pwl +busSignalLayer = -c ID_ORANGE8 +busXLayer = -c ID_RED5 +busZLayer = -c ID_ORANGE6 +busMixedLayer = -c ID_GREEN5 +busNotComputedLayer = -c ID_GRAY1 +busNoValueLayer = -c ID_BLUE2 +signalGridLayer = -c ID_WHITE +analogGridLayer = -c ID_GRAY6 +analogRulerLayer = -c ID_GRAY6 +keywordLayer = -c ID_RED5 +loadedLayer = -c ID_BLUE5 +loadingLayer = -c ID_BLACK +qdsCurMarkerLayer = -c ID_BLUE5 +qdsBrkMarkerLayer = -c ID_GREEN5 +qdsTrgMarkerLayer = -c ID_RED5 +arrowDefaultColor = -c ID_ORANGE6 +startNodeArrowColor = -c ID_WHITE +endNodeArrowColor = -c ID_YELLOW5 +propertyEventMatchColor = -c ID_GREEN5 +propertyEventNoMatchColor = -c ID_RED5 +propertyVacuousSuccessMatchColor = -c ID_YELLOW2 +propertyStatusBoundaryColor = -c ID_WHITE +propertyBooleanSuccessColor = -c ID_CYAN5 +propertyBooleanFailureColor = -c ID_RED5 +propertyAssertSuccessColor = -c ID_GREEN5 +propertyAssertFailureColor = -c ID_RED5 +propertyForbidSuccessColor = -c ID_GREEN5 +transactionForegroundColor = -c ID_YELLOW8 +transactionBackgroundColor = -c ID_BLACK +transactionHighLightColor = -c ID_CYAN6 +transactionRelationshipColor = -c ID_PURPLE6 +transactionErrorTypeColor = -c ID_RED5 +coverageFullyCoveredColor = -c ID_GREEN5 +coverageNoCoverageColor = -c ID_RED5 +coveragePartialCoverageColor = -c ID_YELLOW5 +coverageReferenceLineColor = -c ID_GRAY4 +messageForegroundColor = -c ID_YELLOW4 +messageBackgroundColor = -c ID_PURPLE1 +messageHighLightColor = -c ID_CYAN6 +messageInformationColor = -c ID_RED5 +ComputedAnnotColor = -c ID_PURPLE5 +fsvSecurityDataColor = -c ID_PURPLE3 +qdsAutoBusGroup = TRUE +qdsTimeStampMode = FALSE +qdsVbfBusOrderAscending = FALSE +openDumpFilter = *.fsdb;*.vf;*.jf +DumpFileFilter = *.vcd +RestoreSignalFilter = *.rc +SaveSignalFilter = *.rc +AddAliasFilter = *.alias;*.adb +CompareSignalFilter = *.err +ConvertFFFilter = *.vcd;*.out;*.tr0;*.xp;*.raw;*.wfm +Scroll_Ratio = 100 +Zoom_Ratio = 10 +EventSequence_SyncCursorTime = TRUE +EventSequence_Sorting = FALSE +EventSequence_RemoveGrid = FALSE +EventSequence_IsGridMode = FALSE +SetDefaultRadix_global = FALSE +DefaultRadix = Hex +SigSearchSignalMatchCase = FALSE +SigSearchSignalScopeOption = FALSE +SigSearchSignalSamenetInterface = FALSE +SigSearchSignalFullScope = FALSE +SigSearchSignalWithRegExp = FALSE +SigSearchDynamically = FALSE +SigDisplayBySelectionOrder = FALSE +SigDisplayRowMajor = FALSE +SigDragSelFollowColumn = FALSE +SigDisplayHierarchyBox = TRUE +SigDisplaySubscopeBox = TRUE +SigDisplayEmptyScope = TRUE +SigDisplaySignalNavigationBox = FALSE +SigDisplayFormBus = TRUE +SigShowSubProgram = TRUE +SigSearchScopeDynamically = TRUE +SigCollapseSubtreeNodes = FALSE +activeFileApplyToAnnotation = FALSE +GrpSelMode = TRUE +dispGridCount = FALSE +hierarchyName = FALSE +partial_level_name = FALSE +partial_level_head = 1 +partial_level_tail = 1 +displayMessageLabelOnly = TRUE +autoInsertDumpoffs = TRUE +displayMessageCallStack = FALSE +displayCallStackWithFullSections = TRUE +displayCallStackWithLastSection = FALSE +limitMessageMaxWidth = FALSE +messageMaxWidth = 50 +displayTransBySpecificColor = FALSE +fittedTransHeight = FALSE +snap = TRUE +gravitySnap = FALSE +displayLeadingZero = FALSE +displayGlitchs = FALSE +allfileTimeRange = FALSE +fixDelta = FALSE +displayCursorMarker = FALSE +autoUpdate = FALSE +restoreFromActiveFile = TRUE +restoreToEnd = FALSE +dispCompErr = TRUE +showMsgDes = TRUE +anaAutoFit = FALSE +anaAutoPattn = FALSE +anaAuto100VertFit = FALSE +displayDeltaY = FALSE +centerCursor = FALSE +denseBlockDrawing = TRUE +relativeFreqPrecision = 3 +showMarkerAbsolute = FALSE +showMarkerAdjacent = FALSE +showMarkerRelative = FALSE +showMarkerFrequency = FALSE +stickCursorMarkerOnWaveform = TRUE +keepMarkerAtEndTimeOfTransaction = FALSE +doubleClickToExpandTransaction = TRUE +expandTransactionAssociatedSignals = TRUE +expandTransactionAttributeSignals = FALSE +WaveExtendLastTick = TRUE +InOutSignal = FALSE +NetRegisterSignal = FALSE +VerilogVHDLSignal = FALSE +LabelMarker = TRUE +ResolveSymbolicLink = TRUE +signal_rc_abspath = TRUE +signal_rc_no_natural_bus_range = FALSE +save_scope_with_macro = FALSE +TipInSignalWin = FALSE +DisplayPackedSiganlInBitwiseManner = FALSE +DisplaySignalTypeAheadOfSignalName = TRUE ICON +TipInCurveWin = FALSE +MouseGesturesInCurveWin = TRUE +DisplayLSBsFirst = FALSE +PaintSpecificColorPattern = TRUE +ModuleName = TRUE +form_all_memory_signal = FALSE +formBusSignalFromPartSelects = FALSE +read_value_change_on_demand_for_drawing = FALSE +load_scopes_on_demand = on 5 +TransitionMode = TRUE +DisplayRadix = FALSE +SchemaX = FALSE +Hilight = TRUE +UseBeforeValue = FALSE +DisplayFileNameAheadOfSignalName = FALSE +DisplayFileNumberAheadOfSignalName = FALSE +DisplayValueSpace = TRUE +FitAnaByBusSize = FALSE +displayTransactionAttributeName = FALSE +expandOverlappedTrans = FALSE +dispSamplePointForAttrSig = TRUE +dispClassName = TRUE +ReloadActiveFileOnly = FALSE +NormalizeEVCD = FALSE +OverwriteAliasWithRC = TRUE +overlay_added_analog_signals = FALSE +case_insensitive = FALSE +vhdlVariableCalculate = TRUE +showError = TRUE +signal_vertical_scroll_bar = TRUE +showPortNameForDroppedInstance = FALSE +truncateFilePathInTitleBar = TRUE +filterPropVacuousSuccess = FALSE +includeLocalSignals = FALSE +encloseSignalsByGroup = TRUE +resaveSignals = TRUE +adjustBusPrefix = adjustBus_ +adjustBusBits = 1 +adjustBusSettings = 69889 +maskPowerOff = TRUE +maskIsolation = TRUE +maskRetention = TRUE +maskDrivingPowerOff = TRUE +maskToggle = TRUE +autoBackupSignals = off 5 "\"/home/ICer/verdiLog\"" "\"novas_autosave_sig\"" +signal_rc_attribute = 65535 +signal_rc_alias_attribute = 0 +ConvertAttr1 = -inc FALSE +ConvertAttr2 = -hier FALSE +ConvertAttr3 = -ucase FALSE +ConvertAttr4 = -lcase FALSE +ConvertAttr5 = -org FALSE +ConvertAttr6 = -mem 24 +ConvertAttr7 = -deli . +ConvertAttr8 = -hier_scope FALSE +ConvertAttr9 = -inst_array FALSE +ConvertAttr10 = -vhdlnaming FALSE +ConvertAttr11 = -orgScope FALSE +analogFmtPrecision = Automatic 2 +confirmOverwrite = TRUE +confirmExit = TRUE +confirmGetAll = TRUE +printTimeRange = TRUE 0.000000 0.000000 0.000000 +printPageRange = TRUE 1 1 +printOption = 0 +printBasic = 1 0 0 FALSE FALSE +printDest = -printer {} +printSignature = {%f %h %t} {} +curveWindow_Drag&Drop_Mode = TRUE +hspiceIncOpenMode = TRUE +pcSelectMode = TRUE +hierarchyDelimiter = / +RecentFile1 = "\"/home/ICer/thfu/XYZ/Test/v1.6/case1/TB1.fsdb\"" +open_file_time_range = FALSE +value_window_aligment = Right +signal_window_alignment = Auto +ShowDeltaTime = TRUE +legend_window_font = -f COURIER12 -c ID_CYAN5 +value_window_font = -f COURIER12 -c ID_CYAN5 +curve_window_font = -f COURIER12 -c ID_CYAN5 +group_name_font = -f COURIER12 -c ID_GREEN5 +ruler_value_font = -f COURIER12 -c ID_CYAN5 +analog_ruler_value_font = -f COURIER12 -c ID_CYAN5 +comment_string_font = -f COURIER12 -c ID_RED5 +getsignal_form_font = -f COURIER12 +SigsCheckNum = on 1000 +filter_synthesized_net = off n +filterOutNet = on +filter_synthesized_instance = off +filterOutInstance = on +showGroupTree = TRUE +hierGroupDelim = / +MsgSeverityColor = {y \"Severity\"==\"1\" ID_RED5} {y \"Severity\"==\"2\" ID_RED6} {y \"Severity\"==\"3\" ID_RED7} {y \"Severity\"==\"4\" ID_RED8} {y \"Severity\"==\"5\" ID_ORANGE5} {y \"Severity\"==\"6\" ID_ORANGE6} {y \"Severity\"==\"7\" ID_ORANGE7} {y \"Severity\"==\"8\" \ +ID_GREEN7} {y \"Severity\"==\"9\" ID_GREEN6} {y \"Severity\"==\"10\" ID_GREEN5} +AutoApplySeverityColor = TRUE +AutoAdjustMsgWidthByLabel = off +verilogStrengthDispType = type1 +waveDblClkActiveTrace = on +autoConnectTBrowser = FALSE +connectTBrowserInContainer = TRUE +SEQShowComparisonIcon = TRUE +SEQAddDriverLoadInSameGroup = TRUE +autoSyncCursorMarker = FALSE +autoSyncHorizontalRange = FALSE +autoSyncVerticalScroll = FALSE +[cov_hier_name_column] +justify = TRUE +[coverageColors] +sou_uncov = TRUE +sou_pc = TRUE +sou_cov = TRUE +sou_exuncov = TRUE +sou_excov = TRUE +sou_unreach = TRUE +sou_unreachcon = TRUE +sou_fillColor_uncov = red +sou_fillColor_pc = yellow +sou_fillColor_cov = green3 +sou_fillColor_exuncov = grey +sou_fillColor_excov = #3C9371 +sou_fillColor_unreach = grey +sou_fillColor_unreachcon = orange +numberOfBins = 6 +rangeMin_0 = 0 +rangeMax_0 = 20 +fillColor_0 = #FF6464 +rangeMin_1 = 20 +rangeMax_1 = 40 +fillColor_1 = #FF9999 +rangeMin_2 = 40 +rangeMax_2 = 60 +fillColor_2 = #FF8040 +rangeMin_3 = 60 +rangeMax_3 = 80 +fillColor_3 = #FFFF99 +rangeMin_4 = 80 +rangeMax_4 = 100 +fillColor_4 = #99FF99 +rangeMin_5 = 100 +rangeMax_5 = 100 +fillColor_5 = #64FF64 +[coveragesetting] +assertTopoMode = FALSE +urgAppendOptions = +group_instance_new_format_name = TRUE +showvalue = FALSE +computeGroupsScoreByRatio = FALSE +computeGroupsScoreByInst = FALSE +showConditionId = FALSE +showfullhier = FALSE +nameLeftAlignment = TRUE +showAllInfoInTooltips = FALSE +copyItemHvpName = TRUE +ignoreGroupWeight = FALSE +absTestName = FALSE +HvpMergeTool = +ShowMergeMenuItem = FALSE +fsmScoreMode = transition +[eco] +NameRule = +IsFreezeSilicon = FALSE +cellQuantityManagement = FALSE +ManageMode = INSTANCE_NAME +SpareCellsPinsManagement = TRUE +LogCommitReport = FALSE +InputPinStatus = 1 +OutputPinStatus = 2 +RevisedComponentColor = ID_BLUE5 +SpareCellColor = ID_RED5 +UserName = ICer +CommentFormat = Novas ECO updated by ${UserName} ${Date} ${Time} +PrefixN = eco_n +PrefixP = eco_p +PrefixI = eco_i +DefaultTieUpNet = 1'b1 +DefaultTieDownNet = 1'b0 +MultipleInstantiations = TRUE +KeepClockPinConnection = FALSE +KeepAsyncResetPinConnection = FALSE +ScriptFileModeType = 1 +MagmaScriptPower = VDD +MagmaScriptGround = GND +ShowModeMsg = TRUE +AstroScriptPower = VDD +AstroScriptGround = VSS +ClearFloatingPorts = FALSE +[eco_connection] +Port/NetIsUnique = TRUE +SerialNet = 0 +SerialPort = 0 +SerialInst = 0 +[finsim] +TPLanguage = Verilog +TPName = Super-FinSim +TPPath = TOP.sim +TPOption = +AddImportArgument = FALSE +LineBreakWithScope = FALSE +StopAfterCompileOption = -i +[hvpsetting] +importExcelXMLOptions = +use_test_loca_as_source = FALSE +autoTurnOffHideMeetGoalInit = FALSE +autoTurnOffHideMeetGoal = TRUE +autoTurnOffModifierInit = FALSE +autoTurnOffModifier = TRUE +enableNumbering = TRUE +autoSaveCheck = TRUE +autoSaveTime = 5 +ShowMissingScore = TRUE +enableFeatureId = FALSE +enable_HVP_FEAT_ID = FALSE +enableMeasureConcealment = FALSE +HvpCloneHierShowMsgAgain = 1 +HvpCloneHierType = tree +HvpCloneHierMetrics = Line,Cond,FSM,Toggle,Branch,Assert +autoRecalPlanAfterLoadingCovDBUserDataPlan = false +warnMeAutoRecalPlanAfterLoadingCovDBUserDataPlan = true +autoRecalExclWithPlan = false +warnMeAutoRecalExclWithPlan = true +autoRecalPlanWithExcl = false +warnMeAutoRecalPlanWithExcl = true +warnPopupWarnWhenMultiFilters = true +warnPopupWarnIfHvpReadOnly = true +unmappedObjsReportLevel = def_var_inst +unmappedObjsReportInst = true +unmappedObjsNumOfObjs = High +[ikos] +TPLanguage = VHDL +TPName = Voyager +TPPath = vsh +TPOption = -X +AddImportArgument = FALSE +LineBreakWithScope = FALSE +StopAfterCompileOption = -i +[imp] +options = NULL +libPath = NULL +libDir = NULL +[nCompare] +ErrorViewport = 80 180 800 550 +EditorViewport = 409 287 676 475 +EditorHeightWidth = 802 380 +WaveCommand = "novas" +WaveArgs = "-nWave" +[nCompare.Wnd0] +ViewByHier = FALSE +[nMemory] +dispMode = ADDR_HINT +addrColWidth = 120 +valueColWidth = 100 +showCellBitRangeWithAddr = TRUE +wordsShownInOneRow = 8 +syncCursorTime = FALSE +fixCellColumnWidth = FALSE +font = Courier 12 +[planColors] +plan_fillColor_inactive = lightGray +plan_fillColor_warning = orange +plan_fillColor_error = red +plan_fillColor_invalid = #F0DCDB +plan_fillColor_subplan = lightGray +[schematics] +viewport = 178 262 638 516 +schBackgroundColor = black lineSolid +schBackgroundColor_qt = #000000 qt_solidLine 1 +schBodyColor = orange6 lineSolid +schBodyColor_qt = #ffb973 qt_solidLine 1 +schAsmBodyColor = blue7 lineSolid +schAsmBodyColor_qt = #a5a5ff qt_solidLine 1 +schPortColor = orange6 lineSolid +schPortColor_qt = #ffb973 qt_solidLine 1 +schCellNameColor = Gray6 lineSolid +schCellNameColor_qt = #e0e0e0 qt_solidLine 1 +schCLKNetColor = red6 lineSolid +schCLKNetColor_qt = #ff7373 qt_solidLine 1 +schPWRNetColor = red4 lineSolid +schPWRNetColor_qt = #ff0101 qt_solidLine 1 +schGNDNetColor = cyan4 lineSolid +schGNDNetColor_qt = #01ffff qt_solidLine 1 +schSIGNetColor = green8 lineSolid +schSIGNetColor_qt = #cdffcd qt_solidLine 1 +schTraceColor = yellow4 lineSolid +schTraceColor_qt = #ffff01 qt_solidLine 2 +schBackAnnotateColor = white lineSolid +schBackAnnotateColor_qt = #ffffff qt_solidLine 1 +schValue0 = yellow4 lineSolid +schValue0_qt = #ffff01 qt_solidLine 1 +schValue1 = green3 lineSolid +schValue1_qt = #008000 qt_solidLine 1 +schValueX = red4 lineSolid +schValueX_qt = #ff0101 qt_solidLine 1 +schValueZ = purple7 lineSolid +schValueZ_qt = #ffcdff qt_solidLine 1 +dimColor = cyan2 lineSolid +dimColor_qt = #008080 qt_solidLine 1 +schPreSelColor = green4 lineDash +schPreSelColor_qt = #01ff01 qt_dashLine 2 +schSIGBusNetColor = green8 lineSolid +schSIGBusNetColor_qt = #cdffcd qt_solidLine +schGNDBusNetColor = cyan4 lineSolid +schGNDBusNetColor_qt = #01ffff qt_solidLine +schPWRBusNetColor = red4 lineSolid +schPWRBusNetColor_qt = #ff0101 qt_solidLine +schCLKBusNetColor = red6 lineSolid +schCLKBusNetColor_qt = #ff7373 qt_solidLine +schEdgeSensitiveColor = orange6 lineSolid +schEdgeSensitiveColor_qt = #ffb973 qt_solidLine +schAnnotColor = cyan4 lineSolid +schAnnotColor_qt = #01ffff qt_solidLine +schInstNameColor = orange6 lineSolid +schInstNameColor_qt = #ffb973 qt_solidLine +schPortNameColor = cyan4 lineSolid +schPortNameColor_qt = #01ffff qt_solidLine +schAsmLatchColor = cyan4 lineSolid +schAsmLatchColor_qt = #01ffff qt_solidLine +schAsmRegColor = cyan4 lineSolid +schAsmRegColor_qt = #01ffff qt_solidLine +schAsmTriColor = cyan4 lineSolid +schAsmTriColor_qt = #01ffff qt_solidLine +pre_select = True +ShowPassThroughNet = False +ComputedAnnotColor = ID_PURPLE5 +[schematics_print] +Signature = FALSE +DesignName = PCU +DesignerName = bai +SignatureLocation = LowerRight +MultiPage = TRUE +AutoSliver = FALSE +[sourceColors] +BackgroundActive = gray88 +BackgroundInactive = lightgray +InactiveCode = dimgray +Selection = darkblue +Standard = black +Keyword = blue +Comment = gray25 +Number = black +String = black +Identifier = darkred +Inline = green +colorIdentifier = green +Value = darkgreen +MacroBackground = white +Missing = #400040 +[specColors] +top_plan_linked = #ADFFA6 +top_plan_ignore = #D3D3D3 +top_plan_todo = #EECBAD +sub_plan_ignore = #919191 +sub_plan_todo = #EFAFAF +sub_plan_linked = darkorange +[spec_link_setting] +use_spline = true +goto_section = false +exclude_ignore = true +truncate_abstract = false +abstract_length = 999 +compare_strategy = 2 +auto_apply_margin = FALSE +margin_top = 0.80 +margin_bottom = 0.80 +margin_left = 0.50 +margin_right = 0.50 +margin_unit = inches +[spiceDebug] +ThroughNet = ID_YELLOW5 +InstrumentSig = ID_GREEN5 +InterfaceElement = ID_GREEN5 +Run-timeInterfaceElement = ID_BLUE5 +HighlightThroughNet = TRUE +HighlightInterfaceElement = TRUE +HighlightRuntimeInterfaceElement = TRUE +HighlightSameNet = TRUE +[surefire] +TPLanguage = Verilog +TPName = SureFire +TPPath = verilog +TPOption = +AddImportArgument = TRUE +LineBreakWithScope = TRUE +StopAfterCompileOption = -tcl +[turboSchema_Printer_Options] +Orientation = Landscape +[turbo_library] +bdb_load_scope = +[vdCovFilteringSearchesStrings] +keepLastUsedFiltersMaxNum = 10 +[verisity] +TPLanguage = Verilog +TPName = "Verisity SpeXsim" +TPPath = vlg +TPOption = +AddImportArgument = FALSE +LineBreakWithScope = TRUE +StopAfterCompileOption = -s +[wave.0] +viewPort = 0 27 2560 590 100 65 +[wave.1] +viewPort = 127 219 960 332 100 65 +[wave.2] +viewPort = 38 314 686 205 100 65 +[wave.3] +viewPort = 63 63 700 400 65 41 +[wave.4] +viewPort = 84 84 700 400 65 41 +[wave.5] +viewPort = 92 105 700 400 65 41 +[wave.6] +viewPort = 0 0 700 400 65 41 +[wave.7] +viewPort = 21 21 700 400 65 41 diff --git a/case1/spi_driver.sv b/case1/spi_driver.sv new file mode 100644 index 0000000..e0c6904 --- /dev/null +++ b/case1/spi_driver.sv @@ -0,0 +1,401 @@ +//2024-06-24 linear search for all addr +class spi_driver; + + static bit my_cmd=1'b0; + static bit[24:0] last_addr=25'h190_0000; + static int last_size; + static bit[24:0] addr_list[$]; + + //MOSI data pkt, other input_signals are not packed + spi_trans m_trans; + + //interface + virtual spi_if vif; + + //MOSI data_stream input to SPI(DUT) + bit stream[$]; + + //parameter for randomization + int pktnum; + int interval; + int half_sclk; + bit autarchy; + rand int error_time; + + constraint cstr{ + error_time <= 544; + error_time >= -544; + } + + covergroup SYSAddr; + coverpoint m_trans.addr{ + bins IDR = {[25'h00:25'h03]}; + bins VIDR = {[25'h04:25'h07]}; + bins DATER = {[25'h08:25'h0B]}; + bins VERR = {[25'h0C:25'h0F]}; + bins TESTR = {[25'h10:25'h13]}; + bins IMR = {[25'h14:25'h17]}; + bins ISR = {[25'h18:25'h1B]}; + bins SFRTR = {[25'h1C:25'h1F]}; + bins SFRR = {[25'h20:25'h23]}; + bins CH0RSTR = {[25'h24:25'h27]}; + bins CH1RSTR = {[25'h28:25'h2B]}; + bins CH2RSTR = {[25'h2C:25'h2F]}; + bins CH3RSTR = {[25'h30:25'h33]}; + bins DBGCFGR = {[25'h34:25'h37]}; + bins MISR = {[25'h40:25'h43]}; + } + option.per_instance = 1; + endgroup + + covergroup INSTRAddr; + coverpoint m_trans.addr{ + bins INSTRCTION[8192] = {[25'h010_0000:25'h010_7FFF]}; + } + option.per_instance = 1; + endgroup + + covergroup DATAAddr; + coverpoint m_trans.addr{ + bins DATA[8192] = {[25'h020_0000:25'h020_7FFF]}; + } + option.per_instance = 1; + endgroup + + covergroup CTRAddr; + coverpoint m_trans.addr{ + bins MCUPARAR0 = {[25'h30_0000:25'h30_0003]}; + bins MCUPARAR1 = {[25'h30_0004:25'h30_0007]}; + bins MCUPARAR2 = {[25'h30_0008:25'h30_000B]}; + bins MCUPARAR3 = {[25'h30_000C:25'h30_000F]}; + bins MCURESR0 = {[25'h30_0010:25'h30_0013]}; + bins MCURESR1 = {[25'h30_0014:25'h30_0017]}; + bins MCURESR2 = {[25'h30_0018:25'h30_001B]}; + bins MCURESR3 = {[25'h30_001C:25'h30_001F]}; + bins RTIMR = {[25'h30_0098:25'h30_009B]}; + bins ICNTR = {[25'h30_009C:25'h30_009F]}; + bins FSIR = {[25'h30_00A0:25'h30_00A3]}; + bins MODMR = {[25'h30_0100:25'h30_0103]}; + bins INTPMR = {[25'h30_0104:25'h30_0107]}; + bins MIXNCOCR = {[25'h30_0108:25'h30_010B]}; + bins MIXNFCWHR = {[25'h30_010C:25'h30_010F]}; + bins MIXNFCWLR = {[25'h30_0110:25'h30_0113]}; + bins MIXNPHAR = {[25'h30_0114:25'h30_0117]}; + bins MIXMR = {[25'h30_0118:25'h30_011B]}; + bins MIXODTR = {[25'h30_011C:25'h30_011F]}; + bins MIXODFR = {[25'h30_0120:25'h30_0123]}; + + bins ROLER = {[25'h30_0128:25'h30_012B]}; + bins MIXNCOSCER = {[25'h30_012C:25'h30_012F]}; + bins MODDOTR = {[25'h30_0130:25'h30_0133]}; + bins STR = {[25'h30_0134:25'h30_0137]}; + } + option.per_instance = 1; + endgroup + + covergroup ENVELOPEIDAddr; + coverpoint m_trans.addr{ + bins ENVELOPEID[64] = {[25'h040_0000:25'h040_00FF]}; + } + option.per_instance = 1; + endgroup + + covergroup ENVELOPEDATAAddr; + coverpoint m_trans.addr{ + bins ENVELOPEDATA[8192] = {[25'h050_0000:25'h050_7FFF]}; + } + option.per_instance = 1; + endgroup + + covergroup DACAddr; + coverpoint m_trans.addr{ + bins PRBSCR = {[25'h060_0000:25'h060_0003]}; + bins SET0CR = {[25'h060_0004:25'h060_0007]}; + bins SET1CR = {[25'h060_0008:25'h060_000B]}; + bins SET2CR = {[25'h060_000C:25'h060_000F]}; + bins SET3CR = {[25'h060_0010:25'h060_0013]}; + bins SET4CR = {[25'h060_0014:25'h060_0017]}; + bins SET5CR = {[25'h060_0018:25'h060_001B]}; + bins SET6CR = {[25'h060_001C:25'h060_001F]}; + bins SET7CR = {[25'h060_0020:25'h060_0023]}; + bins SET8CR = {[25'h060_0024:25'h060_0027]}; + bins SET9CR = {[25'h060_0028:25'h060_002B]}; + bins SET10CR = {[25'h060_002C:25'h060_002F]}; + bins SET11CR = {[25'h060_0030:25'h060_0033]}; + bins SET12CR = {[25'h060_0034:25'h060_0037]}; + bins SET13CR = {[25'h060_0038:25'h060_003B]}; + bins SET14CR = {[25'h060_003C:25'h060_003F]}; + bins SET15CR = {[25'h060_0040:25'h060_0043]}; + bins DACADDR = {[25'h060_0044:25'h060_0047]}; + bins DACDW = {[25'h060_0048:25'h060_004B]}; + bins DACREF = {[25'h060_004C:25'h060_004F]}; + bins PRBSRST0 = {[25'h060_0050:25'h060_0053]}; + bins PRBSSET0 = {[25'h060_0054:25'h060_0057]}; + bins PRBSRST1 = {[25'h060_0058:25'h060_005B]}; + bins PRBSSET1 = {[25'h060_005C:25'h060_005F]}; + bins PRBSREV = {[25'h060_0060:25'h060_0063]}; + bins CALSIG = {[25'h060_0064:25'h060_0067]}; + bins CALEND = {[25'h060_0068:25'h060_006B]}; + bins CALRSTN = {[25'h060_006C:25'h060_006F]}; + bins CALDIVRSTN = {[25'h060_0070:25'h060_0073]}; + } + option.per_instance = 1; + endgroup + + covergroup MCUAddr; + coverpoint m_trans.addr{ + bins MCUPARAR0 = {[25'h70_0000:25'h70_0003]}; + bins MCUPARAR1 = {[25'h70_0004:25'h70_0007]}; + bins MCUPARAR2 = {[25'h70_0008:25'h70_000B]}; + bins MCUPARAR3 = {[25'h70_000C:25'h70_000F]}; + bins MCURESR0 = {[25'h70_0010:25'h70_0013]}; + bins MCURESR1 = {[25'h70_0014:25'h70_0017]}; + bins MCURESR2 = {[25'h70_0018:25'h70_001B]}; + bins MCURESR3 = {[25'h70_001C:25'h70_001F]}; + bins CWFR0 = {[25'h70_0040:25'h70_0043]}; + bins CWFR1 = {[25'h70_0044:25'h70_0047]}; + bins CWFR2 = {[25'h70_0048:25'h70_004B]}; + bins CWFR3 = {[25'h70_004C:25'h70_004F]}; + bins CWPRR = {[25'h70_0050:25'h70_0053]}; + bins GAPR0 = {[25'h70_0054:25'h70_0057]}; + bins GAPR1 = {[25'h70_0058:25'h70_005B]}; + bins GAPR2 = {[25'h70_005C:25'h70_005F]}; + bins GAPR3 = {[25'h70_0060:25'h70_0063]}; + bins GAPR4 = {[25'h70_0064:25'h70_0067]}; + bins GAPR5 = {[25'h70_0068:25'h70_006B]}; + bins GAPR6 = {[25'h70_006C:25'h70_006F]}; + bins GAPR7 = {[25'h70_0070:25'h70_0073]}; + bins LCPR = {[25'h70_0074:25'h70_0077]}; + bins AMPR0 = {[25'h70_0078:25'h70_007B]}; + bins AMPR1 = {[25'h70_007C:25'h70_007F]}; + bins AMPR2 = {[25'h70_0080:25'h70_0083]}; + bins AMPR3 = {[25'h70_0084:25'h70_0087]}; + bins BIASR0 = {[25'h70_0088:25'h70_008B]}; + bins BIASR1 = {[25'h70_008C:25'h70_008F]}; + bins BIASR2 = {[25'h70_0090:25'h70_0093]}; + bins BIASR3 = {[25'h70_0094:25'h70_0097]}; + bins RTIMR = {[25'h70_0098:25'h70_009B]}; + bins ICNTR = {[25'h70_009C:25'h70_009F]}; + bins FSIR = {[25'h70_00A0:25'h70_00A3]}; + bins INTPSELR = {[25'h70_00A4:25'h70_00A7]}; + } + option.per_instance = 1; + endgroup + + covergroup DBGAddr; + coverpoint m_trans.addr{ + bins DBGAddr[1024] = {[25'h190_0000:25'h190_0FFF]}; + } + option.per_instance = 1; + endgroup + + + covergroup PLLAddr; + coverpoint m_trans.addr{ + bins INTPLL_REFCTRL = {[25'h1f0_0000:25'h1f0_0003]}; + bins INTPLL_PCNT = {[25'h1f0_0004:25'h1f0_0007]}; + bins INTPLL_PFDCTRL = {[25'h1f0_0008:25'h1f0_000B]}; + bins INTPLL_SPDCTRL = {[25'h1f0_000C:25'h1f0_000F]}; + bins INTPLL_PTATCTRL = {[25'h1f0_0010:25'h1f0_0013]}; + bins INTPLL_FLLCTRL = {[25'h1f0_0014:25'h1f0_0017]}; + bins INTPLL_SELCTRL = {[25'h1f0_0018:25'h1f0_001B]}; + bins INTPLL_VCOCTRL = {[25'h1f0_001C:25'h1f0_001F]}; + bins INTPLL_VCOFBADJ = {[25'h1f0_0020:25'h1f0_0023]}; + bins INTPLL_AFCCTRL = {[25'h1f0_0024:25'h1f0_0027]}; + bins INTPLL_AFCCNT = {[25'h1f0_0028:25'h1f0_002B]}; + bins INTPLL_AFCLDCNT = {[25'h1f0_002C:25'h1f0_002F]}; + bins INTPLL_AFCPRES = {[25'h1f0_0030:25'h1f0_0033]}; + bins INTPLL_AFCLDTCC = {[25'h1f0_0034:25'h1f0_0037]}; + bins INTPLL_AFCFBTCC = {[25'h1f0_0038:25'h1f0_003B]}; + bins INTPLL_DIVCFG = {[25'h1f0_003C:25'h1f0_003F]}; + bins INTPLL_TCLKCFG = {[25'h1f0_0040:25'h1f0_0043]}; + bins INTPLL_DCLKSEL = {[25'h1f0_0044:25'h1f0_0047]}; + bins INTPLL_STATUS = {[25'h1f0_0048:25'h1f0_004B]}; + bins INTPLL_SYNCFG = {[25'h1f0_004C:25'h1f0_004F]}; + bins INTPLL_UPDATE = {[25'h1f0_0050:25'h1f0_0053]}; + bins INTPLL_CLKRXPD = {[25'h1f0_0054:25'h1f0_0057]}; +} + option.per_instance = 1; + endgroup + + + function new(); + SYSAddr = new(); + INSTRAddr = new(); + DATAAddr = new(); + CTRAddr = new(); + ENVELOPEIDAddr = new(); + ENVELOPEDATAAddr = new(); + DACAddr = new(); + MCUAddr = new(); + DBGAddr = new(); + PLLAddr = new(); + endfunction + extern task do_drive(); + extern task make_pkt(spi_trans tr); + +endclass : spi_driver + +task spi_driver::do_drive(); + int i=0,j=0; + + for(i=0;i<14;i++) + addr_list[i]=4*i; + addr_list[14] = 25'h000_0040; + addr_list.delete(8); + addr_list.delete(8); + // $display(addr_list); + + pktnum=addr_list.size()*2; + + $display("pkt_num:\t%0d",pktnum); + + while(!vif.rstn) begin + vif.csn = 1'b1; + vif.sclk = 1'b1; + @(posedge vif.clk); + end + + for(j=0;j= 25'h000_001C)) + m_trans.data[(25'h000_001C - m_trans.addr)/4] = + m_trans.data[(25'h000_001C - m_trans.addr)/4] % 4 + 1; + + + + make_pkt(m_trans); + + //$display(m_trans.addr); + + SYSAddr.sample(); + INSTRAddr.sample(); + DATAAddr.sample(); + CTRAddr.sample(); + ENVELOPEIDAddr.sample(); + ENVELOPEDATAAddr.sample(); + DACAddr.sample(); + MCUAddr.sample(); + DBGAddr.sample(); + PLLAddr.sample(); + + repeat(interval) + @(posedge vif.clk); + + //pktnum--; + end + + + $finish(0); + //$display(SYSAddr.get_inst_coverage()); + //$display(MCUAddr.get_inst_coverage()); + //$display(AWGAddr.get_inst_coverage()); + +endtask : do_drive + + +task spi_driver::make_pkt(spi_trans tr); + int i=0,j=0; + int cs_time,mo_time; + + //*****************initialize chip_select and input_clk******************// + vif.csn <= 1'b1; + vif.sclk <= 1'b1; + vif.mosi <= stream[0]; + vif.cfgid <= tr.cfgid; + @(posedge vif.clk); + vif.csn <= 1'b0; + vif.sclk <= 1'b1; + + //unpack into bitstream + stream.delete(); + tr.unpack(stream); + + //mosi valid time: time for bitstream to be all sent + //csn valid_time: maybe a delay after or ahead of mosi_finished + mo_time = (stream.size()+1)*2*half_sclk; + cs_time = (pktnum==1) ? (mo_time + error_time%mo_time) : mo_time; + + //$display("***************************ONE PKT DRIVERED***************************"); + //$display("half_sclk:\t%0d\t\t\t\t\t\t **",half_sclk); + //$display("interval:\t%0d\t\t\t\t\t\t **",interval); + //$display("error_time:\t%0d\t\t\t\t\t\t **",error_time); + //$display("data_size:\t%0d\t\t\t\t\t\t **",tr.data.size()); + //$display("cmd:\t\t%0d\t\t\t\t\t\t **",tr.cmd); + //$display("id:\t\t%h\t\t\t\t\t\t **",tr.cfgid); + //$display("addr:\t\t%h\t\t\t\t\t\t **",tr.addr); + //$display(stream); + //if(!tr.cmd) + //for(i=0;i= 1; + data.size() <= 1;//not solid + interval <= 1000; + interval >= 0; + half_sclk <= 32; + half_sclk >= 4; + //Select system_regfile + (addr >= 25'h000_0000 && + //addr <= 25'h000_0037 && + int'(addr) <= int'(25'h000_003B) - int'(data.size()*4) && + addr != 25'h000_0020 && + addr != 25'h000_0024) || + (addr == 25'h000_0040) || + //Select instruction SRAMs 8192X32bit 32KB + (addr >= 25'h010_0000 && + //addr <= 25'h010_7FFF && + int'(addr) <= 25'h010_8003 - data.size()*4) || + //Select data SRAMs 8192X32bit 32KB + (addr >= 25'h020_0000 && + //addr <= 25'h020_7FFF && + int'(addr) <= 25'h020_8003 - data.size()*4) || + //Select awg_regfile + (addr >= 25'h030_0000 && + //addr <= 25'h030_001F && + int'(addr) <= int'(25'h030_0023) - int'(data.size()*4)) || + (addr >= 25'h030_0098 && + //addr <= 25'h030_00A3 && + int'(addr) <= int'(25'h030_00A7) - int'(data.size()*4)) || + (addr >= 25'h030_0100 && + //addr <= 25'h030_0123 && + int'(addr) <= int'(25'h030_0127) - int'(data.size()*4)) || + (addr >= 25'h030_0128 && + //addr <= 25'h030_0137 && + int'(addr) <= int'(25'h030_013B) - int'(data.size()*4)) || + //Select envelope ID SRAMs 64X32bit 256B + (addr >= 25'h040_0000 && + //addr <= 25'h040_00FF && + int'(addr) <= 25'h040_0103 - data.size()*4) || + //Select envelope data SRAMs 8192X32bit 32KB + (addr >= 25'h050_0000 && + //addr <= 25'h050_7FFF && + int'(addr) <= 25'h050_8003 - data.size()*4) || + //Select dac_regfile + (addr >= 25'h060_0000 && + //addr <= 25'h060_0073 && + int'(addr) <= int'(25'h060_0077) - int'(data.size()*4)) || + //Select mcu_regfile + (addr >= 25'h070_0000 && + //addr <= 25'h070_01F && + int'(addr) <= int'(25'h070_0023) - int'(data.size()*4)) || + (addr >= 25'h070_0040 && + //addr <= 25'h070_00A7 && + int'(addr) <= int'(25'h070_00AB) - int'(data.size()*4)) || + //Select DBG SRAMs 256X128bit 4KB + (addr >= 25'h190_0000 && + //addr <= 25'h190_0FFF && + int'(addr) <= 25'h190_1003 - data.size()*4) || + //Select intpll_regfile + (addr >= 25'h1f0_0000 && + //addr <= 25'h1f0_0057 && + int'(addr) <= int'(25'h1f0_005B) - int'(data.size()*4)) ; + } + + function new(); + endfunction + + extern function bit compare(spi_trans rhs_); + extern function void print(integer fid); + extern function void unpack(ref bit stream[$]); + extern function void pack(bit stream[$]); + +endclass : spi_trans + + + +function bit spi_trans::compare(spi_trans rhs_); + bit result=1'b1; + int i=0; + + result = ((cmd == rhs_.cmd) && + (addr == rhs_.addr) && + (cfgid == rhs_.cfgid)); + + if(this.data.size() != rhs_.data.size()) begin + $display("data_sizes are different"); + result = 1'b0; + end + else + for(i=0;i0)begin + for(i=0;i<32;i++) + data_temp[31-i] = stream.pop_front(); + data.push_back(data_temp); + end +endfunction diff --git a/case2/Makefile b/case2/Makefile new file mode 100644 index 0000000..e8b0c94 --- /dev/null +++ b/case2/Makefile @@ -0,0 +1,17 @@ +VCS = vcs -full64 -sverilog +lint=TFIPC-L +v2k -debug_access+all +define+DUMP_FSDB -lca -q -timescale=1ns/1ps +nospecify -P /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/pli.a -l compile.log -R +plusarg_save +ntb_random_seed_automatic -cm line+cond+fsm+tgl+branch + +SIMV = ./simv -l sim.log -cm_dir ./coverage/test1db -cm line+cond+fsm+tgl+branch +all:comp run + +comp: + ${VCS} -f files.f +incdir+./../rtl/qubitmcu +run: + ${SIMV} +file: + find ../../rtl -name "*.*v" > files.f +dbg: + verdi -sverilog -f files.f -top TB -nologo & +cov: + urg -lca -dir simv.vdb -report both -dir ./coverage/test1db +clean: + rm -rf DVE* simv* TB1* *log ucli.key verdiLog urgReport csrc both coverage novas.conf novas_dump.log reports.txt *.fsdb *.dat *.daidir *.vdb *.vf*~ diff --git a/case2/case6.sv b/case2/case6.sv new file mode 100644 index 0000000..a93a6f3 --- /dev/null +++ b/case2/case6.sv @@ -0,0 +1,30 @@ + +program case6(spi_if my_if,pllreg_if pll_if,dacreg_if dac_if,sysreg_if sys_if,mcureg_if mcu_if,awgreg_if awg_if,sram_if xif); + + env my_env; + + initial begin + + my_env = new(); + + my_env.wif = my_if; + my_env.pif = pll_if; + my_env.dif = dac_if; + my_env.vif = sys_if; + my_env.mif = mcu_if; + my_env.aif = awg_if; + my_env.xif = xif; + my_env.pktnum = 30; + + + my_env.build(); + + my_env.run(); + + //$display($get_coverage()); + + end + +endprogram + + diff --git a/case2/files.f b/case2/files.f new file mode 100644 index 0000000..364e6b7 --- /dev/null +++ b/case2/files.f @@ -0,0 +1,129 @@ +../rtl/define/chip_define.v +../rtl/qubitmcu/qbmcu_defines.v +spi_trans.sv +spi_driver.sv +../tb/spi_tb/spi_if.sv +../tb/sysreg_tb/sysreg_if.sv +../tb/pllreg_tb/pllreg_if.sv +../tb/mcureg_tb/mcureg_if.sv +../tb/awgreg_tb/awgreg_if.sv +../tb/spi_tb/spi_monitor.sv +../tb/spi_tb/spi_scb.sv +../tb/sram_tb/ramreg_scb.sv +../tb/sram_tb/ram_refmodel.sv +../tb/sysreg_tb/sysreg_trans.sv +../tb/sysreg_tb/sysreg_monitor.sv +../tb/sysreg_tb/sys_refmodel.sv +../tb/sysreg_tb/sysreg_scb.sv +../tb/pllreg_tb/pllreg_trans.sv +../tb/pllreg_tb/pllreg_driver.sv +../tb/pllreg_tb/pllreg_monitor.sv +../tb/pllreg_tb/pll_refmodel.sv +../tb/pllreg_tb/pllreg_scb.sv +../tb/dacreg_tb/dacreg_trans.sv +../tb/dacreg_tb/dacreg_if.sv +../tb/dacreg_tb/dacreg_monitor.sv +../tb/dacreg_tb/dac_refmodel.sv +../tb/dacreg_tb/dacreg_scb.sv +../tb/mcureg_tb/mcureg_trans.sv +../tb/mcureg_tb/mcureg_monitor.sv +../tb/mcureg_tb/mcu_refmodel.sv +../tb/mcureg_tb/mcureg_scb.sv +../tb/awgreg_tb/awgreg_trans.sv +../tb/awgreg_tb/awgreg_monitor.sv +../tb/awgreg_tb/awg_refmodel.sv +../tb/awgreg_tb/awgreg_scb.sv +../tb/env.sv +case6.sv +../tb/tb.sv +../rtl/memory/sram_if.sv +../rtl/awg/awg_ctrl.v +../rtl/awg/awg_top.sv +../rtl/awg/codeword_decode.v +../rtl/awg/ctrl_regfile.v +../rtl/awg/param_lut.sv +../rtl/awg/modout_mux.v +../rtl/clk/intpll_regfile.v +../rtl/comm/sirv_gnrl_dffs.v +../rtl/comm/sirv_gnrl_xchecker.v +../rtl/dac_regfile/dac_regfile.v +../rtl/debug/debug_sample.sv +../rtl/debug/debug_top.sv +../rtl/memory/dpram.v +../rtl/memory/dpram_model.v +../rtl/memory/sram_dmux.sv +../rtl/memory/tsdn28hpcpuhdb128x128m4mw_170a_ffg0p99v0c.v +../rtl/memory/tsdn28hpcpuhdb4096x32m4mw_170a_ffg0p99v0c.v +../rtl/memory/tsdn28hpcpuhdb64x32m4mw_170a_ffg0p99v0c.v +../rtl/memory/tsmc_dpram.v +../rtl/modem/ampmod.v +../rtl/modem/baisset.v +../rtl/modem/freqmod.v +../rtl/nco/coef_c.v +../rtl/nco/coef_s.v +../rtl/nco/cos_op.v +../rtl/nco/nco.v +../rtl/nco/nco_ch1.v +../rtl/nco/p_nco.v +../rtl/nco/p_nco_ch1.v +../rtl/nco/ph2amp.v +../rtl/nco/pipe_acc_48bit.v +../rtl/nco/pipe_add_48bit.v +../rtl/nco/sin_op.v +../rtl/perips/DW03_updn_ctr.v +../rtl/perips/qbmcu_busdecoder.v +../rtl/perips/mcu_regfile.sv +../rtl/qubitmcu/qbmcu.v +../rtl/qubitmcu/qbmcu_datalock.v +../rtl/qubitmcu/qbmcu_decode.v +../rtl/qubitmcu/qbmcu_exu.v +../rtl/qubitmcu/qbmcu_exu_alu.v +../rtl/qubitmcu/qbmcu_exu_bjp.v +../rtl/qubitmcu/qbmcu_exu_dpath.v +../rtl/qubitmcu/qbmcu_exu_ext.v +../rtl/qubitmcu/qbmcu_exu_lsuagu.v +../rtl/qubitmcu/qbmcu_fsm.v +../rtl/qubitmcu/qbmcu_ifu.v +../rtl/qubitmcu/qbmcu_regfile.v +../rtl/qubitmcu/qbmcu_wbck.v +../rtl/rstgen/rst_gen_unit.v +../rtl/rstgen/rst_sync.v +../rtl/spi/spi_bus_decoder.sv +../rtl/spi/spi_pll.v +../rtl/spi/spi_slave.v +../rtl/spi/spi_sys_20240624.v +../rtl/sync/sync_buf.sv +../rtl/system_regfile/system_regfile.v +../rtl/top/channel_top.sv +../rtl/top/digital_top.sv +../rtl/top/xyz_chip_top.v +../rtl/top/z_data_mux.v +../rtl/xy_dsp/dacif/dacif.v +../rtl/xy_dsp/dsp_top/xy_dsp.v +../rtl/xy_dsp/duc/duc_hb1_pipe_shift.v +../rtl/xy_dsp/duc/duc_hb1_top.v +../rtl/xy_dsp/duc/duc_hb2_pipe_shift.v +../rtl/xy_dsp/duc/duc_hb2_top_s.v +../rtl/xy_dsp/duc/duc_hb3_pipe_shift.v +../rtl/xy_dsp/duc/duc_hb3_top_s2.v +../rtl/xy_dsp/duc/duc_hb4_pipe_shift.v +../rtl/xy_dsp/duc/duc_hb4_top_s3.v +../rtl/xy_dsp/duc/duc4.v +../rtl/xy_dsp/qam/qam_top.v +../rtl/xy_dsp/qam/ssb.v +../rtl/dem/DAC_DEM_4.v +../rtl/dem/DAC_DEM_16.v +../rtl/dem/DAC_DEM.v +../tb/digital_top/DW_mult_pipe.v +../tb/digital_top/DW01_addsub.v +../tb/digital_top/DW02_mult.v +../tb/digital_top/clk_gen.v +../tb/chip_top/thermo2binary_top.v +../tb/chip_top/thermo7_binary3.v +../tb/chip_top/thermo15_binary4.v +../rtl/io/iopad.v +../rtl/io/tphn28hpcpgv18.v +../rtl/comm/syncer.v +../rtl/qubitmcu/qbmcu_undefines.v +../rtl/define/chip_undefine.v + diff --git a/case2/novas.rc b/case2/novas.rc new file mode 100644 index 0000000..ca3fdba --- /dev/null +++ b/case2/novas.rc @@ -0,0 +1,1313 @@ +@verdi rc file Version 1.0 +[Library] +work = ./work +[Annotation] +3D_Active_Annotation = FALSE +[CommandSyntax.finsim] +InvokeCommand = +FullFileName = TRUE +Separator = . +SimPromptSign = ">" +HierNameLevel = 1 +RunContinue = "continue" +Finish = "quit" +UseAbsTime = FALSE +NextTime = "run 1" +NextNTime = "run ${SimBPTime}" +NextEvent = "run 1" +Reset = +ObjPosBreak = "break posedge ${SimBPObj}" +ObjNegBreak = "break negedge ${SimBPObj}" +ObjAnyBreak = "break change ${SimBPObj}" +ObjLevelBreak = +LineBreak = "breakline ${SimBPFile} ${SimBPLine}" +AbsTimeBreak = "break abstimeaf ${SimBPTime}" +RelTimeBreak = "break reltimeaf ${SimBPTime}" +EnableBP = "breakon ${SimBPId}" +DisableBP = "breakoff ${SimBPId}" +DeleteBP = "breakclr ${SimBPId}" +DeleteAllBP = "breakclr" +SimSetScope = "cd ${SimDmpObj}" +[CommandSyntax.ikos] +InvokeCommand = "setvar debussy true;elaborate -p ${SimTop} -s ${SimArch}; run until 0;fsdbInteractive; " +FullFileName = TRUE +NeedTimeUnit = TRUE +NormalizeTimeUnit = TRUE +Separator = / +HierNameLevel = 2 +RunContinue = "run" +Finish = "exit" +NextTime = "run ${SimBPTime} ${SimTimeUnit}" +NextNTime = "run for ${SimBPTime} ${SimTimeUnit}" +NextEvent = "step 1" +Reset = "reset" +ObjPosBreak = "stop if ${SimBPObj} = \"'1'\"" +ObjNegBreak = "stop if ${SimBPObj} = \"'0'\"" +ObjAnyBreak = +ObjLevelBreak = "stop if ${SimBPObj} = ${SimBPValue}" +LineBreak = "stop at ${SimBPFile}:${SimBPLine}" +AbsTimeBreak = +RelTimeBreak = +EnableBP = "enable ${SimBPId}" +DisableBP = "disable ${SimBPId}" +DeleteBP = "delete ${SimBPId}" +DeleteAllBP = "delete *" +[CommandSyntax.verisity] +InvokeCommand = +FullFileName = FALSE +Separator = . +SimPromptSign = "> " +HierNameLevel = 1 +RunContinue = "." +Finish = "$finish;" +NextTime = "$db_steptime(1);" +NextNTime = "$db_steptime(${SimBPTime});" +NextEvent = "$db_step;" +SimSetScope = "$scope(${SimDmpObj});" +Reset = "$reset;" +ObjPosBreak = "$db_breakonposedge(${SimBPObj});" +ObjNegBreak = "$db_breakonnegedge(${SimBPObj});" +ObjAnyBreak = "$db_breakwhen(${SimBPObj});" +ObjLevelBreak = "$db_breakwhen(${SimBPObj}, ${SimBPValue});" +LineBreak = "$db_breakatline(${SimBPLine}, ${SimBPScope}, \"${SimBPFile}\");" +AbsTimeBreak = "$db_breakbeforetime(${SimBPTime});" +RelTimeBreak = "$db_breakbeforetime(${SimBPTime});" +EnableBP = "$db_enablebreak(${SimBPId});" +DisableBP = "$db_disablebreak(${SimBPId});" +DeleteBP = "$db_deletebreak(${SimBPId});" +DeleteAllBP = "$db_deletebreak;" +FSDBInit = "$novasInteractive;" +FSDBDumpvars = "$novasDumpvars(0, ${SimDmpObj});" +FSDBDumpsingle = "$novasDumpsingle(${SimDmpObj});" +FSDBDumpvarsInFile = "$novasDumpvarsToFile(\"${SimDmpFile}\");" +FSDBDumpMem = "$novasDumpMemNow(${SimDmpObj}, ${SimDmpBegin}, ${SimDmpSize});" +[CoverageDetail] +cross_filter_limit = 1000 +branch_limit_vector_display = 50 +showgrid = TRUE +reuseFirst = TRUE +justify = TRUE +scrollbar_mode = per pane +test_combo_left_truncate = TRUE +instance_combo_left_truncate = TRUE +loop_navigation = TRUE +condSubExpr = 20 +tglMda = 1000 +linecoverable = 100000 +lineuncovered = 50000 +tglcoverable = 30000 +tgluncovered = 30000 +pendingMax = 1000 +show_full_more = FALSE +[CoverageHier] +showgrid = FALSE +[CoverageWeight] +Assert = 1 +Covergroup = 1 +Line = 1 +Condition = 1 +Toggle = 1 +FSM = 1 +Branch = 1 +[DesignTree] +IfShowModule = {TRUE, FALSE} +[DisabledMessages] +version = Verdi_O-2018.09-SP2 +152174613 = disabled +[Editor] +editorName = TurboEditor +[Emacs] +EmacsFont = "Clean 14" +EmacsBG = white +EmacsFG = black +[Exclusion] +enableAsDefault = TRUE +saveAsDefault = TRUE +saveManually = TRUE +illegalBehavior = FALSE +DisplayExcludedItem = FALSE +adaptiveExclusion = TRUE +warningExcludeInstance = TRUE +favorite_exclude_annotation = "" +[FSM] +viewport = 65 336 387 479 +WndBk-FillColor = Gray3 +Background-FillColor = gray5 +prefKey_Link-FillColor = yellow4 +prefKey_Link-TextColor = black +Trap = red3 +Hilight = blue4 +Window = Gray3 +Selected = white +Trans. = green2 +State = black +Init. = black +SmartTips = TRUE +VectorFont = FALSE +StopAskBkgndColor = FALSE +ShowStateAction = FALSE +ShowTransAction = FALSE +ShowTransCond = FALSE +StateLable = NAME +StateValueRadix = ORIG +State-LineColor = ID_BLACK +State-LineWidth = 1 +State-FillColor = ID_BLUE2 +State-TextColor = ID_WHITE +Init_State-LineColor = ID_BLACK +Init_State-LineWidth = 2 +Init_State-FillColor = ID_YELLOW2 +Init_State-TextColor = ID_BLACK +Reset_State-LineColor = ID_BLACK +Reset_State-LineWidth = 2 +Reset_State-FillColor = ID_YELLOW7 +Reset_State-TextColor = ID_BLACK +Trap_State-LineColor = ID_RED2 +Trap_State-LineWidth = 2 +Trap_State-FillColor = ID_CYAN5 +Trap_State-TextColor = ID_RED2 +State_Action-LineColor = ID_BLACK +State_Action-LineWidth = 1 +State_Action-FillColor = ID_WHITE +State_Action-TextColor = ID_BLACK +Junction-LineColor = ID_BLACK +Junction-LineWidth = 1 +Junction-FillColor = ID_GREEN2 +Junction-TextColor = ID_BLACK +Connection-LineColor = ID_BLACK +Connection-LineWidth = 1 +Connection-FillColor = ID_GRAY5 +Connection-TextColor = ID_BLACK +prefKey_Port-LineColor = ID_BLACK +prefKey_Port-LineWidth = 1 +prefKey_Port-FillColor = ID_ORANGE6 +prefKey_Port-TextColor = ID_YELLOW2 +Transition-LineColor = ID_BLACK +Transition-LineWidth = 1 +Transition-FillColor = ID_WHITE +Transition-TextColor = ID_BLACK +Trans_Condition-LineColor = ID_BLACK +Trans_Condition-LineWidth = 1 +Trans_Condition-FillColor = ID_WHITE +Trans_Condition-TextColor = ID_ORANGE2 +Trans_Action-LineColor = ID_BLACK +Trans_Action-LineWidth = 1 +Trans_Action-FillColor = ID_WHITE +Trans_Action-TextColor = ID_GREEN2 +SelectedSet-LineColor = ID_RED2 +SelectedSet-LineWidth = 1 +SelectedSet-FillColor = ID_RED2 +SelectedSet-TextColor = ID_WHITE +StickSet-LineColor = ID_ORANGE5 +StickSet-LineWidth = 1 +StickSet-FillColor = ID_PURPLE6 +StickSet-TextColor = ID_BLACK +HilightSet-LineColor = ID_RED5 +HilightSet-LineWidth = 1 +HilightSet-FillColor = ID_RED7 +HilightSet-TextColor = ID_BLUE5 +ControlPoint-LineColor = ID_BLACK +ControlPoint-LineWidth = 1 +ControlPoint-FillColor = ID_WHITE +Bundle-LineColor = ID_BLACK +Bundle-LineWidth = 1 +Bundle-FillColor = ID_WHITE +Bundle-TextColor = ID_BLUE4 +QtBackground-FillColor = ID_GRAY6 +prefKey_Link-LineColor = ID_ORANGE2 +prefKey_Link-LineWidth = 1 +Selection-LineColor = ID_BLUE2 +Selection-LineWidth = 1 +[FSM_Dlg-Print] +Orientation = Landscape +[FileBrowser] +nWaveOpenFsdbDirHistory = "\"/home/ICer/thfu/XYZ/Test/v1.6/case2/TB1.fsdb\"" +[Form] +version = Verdi_O-2018.09-SP2 +[General] +autoSaveSession = FALSE +TclAutoSource = +cmd_enter_form = FALSE +SyncBrowserDir = TRUE +version = Verdi_O-2018.09-SP2 +SignalCaseInSensitive = FALSE +ShowWndCtntDuringResizing = FALSE +[GlobalProp] +ErrWindow_Font = Helvetica_M_R_12 +[Globals] +app_default_font = Bitstream Vera Sans,10,-1,5,50,0,0,0,0,0 +app_fixed_width_font = Courier,10,-1,5,50,0,0,0,0,0 +text_encoding = Unicode(utf8) +smart_resize = TRUE +smart_resize_child_limit = 2000 +tooltip_max_width = 200 +tooltip_max_height = 20 +tooltip_viewer_key = F3 +tooltip_display_time = 1000 +bookmark_name_length_limit = 12 +disable_tooltip = FALSE +auto_load_source = TRUE +max_array_size = 4096 +filter_when_typing = TRUE +filter_keep_children = TRUE +filter_syntax = Wildcards +filter_keystroke_interval = 800 +filter_case_sensitive = FALSE +filter_full_path = FALSE +load_detail_for_funcov = FALSE +sort_limit = 100000 +ignoreDBVersionChecking = FALSE +[HB] +ViewSchematic = FALSE +windowLayout = 0 0 804 500 182 214 804 148 +import_filter = *.v; *.vc; *.f +designTreeFont = *-adobe-courier-medium-r-*-*-12-*-*-*-*-*-iso8859-* +import_filter_vhdl = *.vhd; *.vhdl; *.f +import_default_language = Verilog +import_filter_verilog = *.v; *.vc; *.f +simulation_file_type = *.fsdb;*.fsdb.gz;*.fsdb.bz2;*.ff;*.dump +PrefetchViewableAnnot = TRUE +[Hier] +filterTimeout = 1500 +[ImportLiberty] +SearchPriority = .lib++ +bSkipStateCell = False +bImportPowerInfo = False +bSkipFFCell = False +bScpecifyCellNameCase = False +bSpecifyPinNameCase = False +CellNameToCase = +PinNameToCase = +[Language] +EditWindow_Font = COURIER12 +Background = ID_WHITE +Comment = ID_GRAY4 +Keyword = ID_BLUE5 +UserKeyword = ID_GREEN2 +Text = ID_BLACK +SelText = ID_WHITE +SelBackground = ID_BLUE2 +[Library.Ikos] +pack = ./work.lib++ +vital = ./work.lib++ +work = ./work.lib++ +std = ${dls_std}.lib++ +ieee = ${dls_ieee}.lib++ +synopsys = ${dls_synopsys}.lib++ +silc = ${dls_silc}.lib++ +ikos = ${dls_ikos}.lib++ +novas = ${VOYAGER_LIB_VHDL}/${VOYAGER_MACHINE}/novas.lib++ +[MDT] +ART_RF_SP = spr[0-9]*bx[0-9]* +ART_RF_2P = dpr[0-9]*bx[0-9]* +ART_SRAM_SP = spm[0-9]*bx[0-9]* +ART_SRAM_DP = dpm[0-9]*bx[0-9]* +VIR_SRAM_SP = hdsd1_[0-9]*x[0-9]*cm4sw1 +VIR_SRAM_DP = hdsd2_[0-9]*x[0-9]*cm4sw1 +VIR_RF_SP = rfsd1_[0-9]*x[0-9]*cm2sw0 +VIR_RF_DP = rfsd2_[0-9]*x[0-9]*cm2sw1 +VIR_STAR_SRAM_SP = shsd1_[0-9]*x[0-9]*cm4sw0 +[NPExpanding] +functiongroups = FALSE +modules = FALSE +[NPFilter] +showAssertion = TRUE +showCoverGroup = TRUE +showProperty = TRUE +showSequence = TRUE +showDollarUnit = TRUE +[OldFontRC] +Wave_legend_window_font = -f COURIER12 -c ID_CYAN5 +Wave_value_window_font = -f COURIER12 -c ID_CYAN5 +Wave_curve_window_font = -f COURIER12 -c ID_CYAN5 +Wave_group_name_font = -f COURIER12 -c ID_GREEN5 +Wave_ruler_value_font = -f COURIER12 -c ID_CYAN5 +Wave_analog_ruler_value_font = -f COURIER12 -c ID_CYAN5 +Wave_comment_string_font = -f COURIER12 -c ID_RED5 +HB_designTreeFont = *-adobe-courier-medium-r-*-*-12-*-*-*-*-*-iso8859-* +Text_font = COURIER12 +nMemory_font = Fixed 14 +Wave_getsignal_form_font = -f COURIER12 +Text_annotFont = Helvetica_M_R_10 +[OtherEditor] +cmd1 = "xterm -font 9x15 -fg black -bg gray -e" +name = "vi" +options = "+${CurLine} ${CurFullFileName}" +[Power] +PowerDownInstance = ID_GRAY1 +RetentionSignal = ID_YELLOW2 +IsolationSignal = ID_RED6 +LevelShiftedSignal = ID_GREEN6 +PowerSwitchObject = ID_ORANGE5 +AlwaysOnObject = ID_GREEN5 +PowerNet = ID_RED2 +GroundNet = ID_RED2 +SimulationOnly = ID_CYAN3 +SRSN/SPA = ID_CYAN3 +CNSSignal = ID_CYAN3 +RPTRSignal = ID_CYAN3 +AcknowledgeSignal = ID_CYAN3 +BoundaryPort = ID_CYAN3 +DisplayInstrumentedCell = TRUE +ShowCmdByFile = FALSE +ShowPstAnnot = FALSE +ShowIsoSymbol = TRUE +ExtractIsoSameNets = FALSE +AnnotateSignal = TRUE +HighlightPowerObject = TRUE +HighlightPowerDomain = TRUE +TraceThroughInstruLowPower = FALSE +BrightenPowerColorInSchematicWindow = FALSE +ShowAlias = FALSE +ShowVoltage = TRUE +MatchTreeNodesCaseInsensitive = FALSE +SearchHBNodeDynamically = FALSE +ContinueTracingSupplyOrLogicNet = FALSE +[Print] +PrinterName = lp +FileName = test.ps +PaperSize = A4 - 210x297 (mm) +ColorPrint = FALSE +[PropertyTools] +saveWaveformStat = TRUE +savePropStat = FALSE +savePropDtl = TRUE +[QtDialog] +openFileDlg = 978,491,602,483 +GoToLineForm_base = 1162,677,234,111 +QwUserAskDlg = 1118,667,324,134 +[Relationship] +hideRecursiceNode = FALSE +[Session Cache] +3 = string (session file name) +4 = string (session file name) +5 = string (session file name) +1 = /home/ICer/thfu/XYZ/Test/v1.6/case2/verdiLog/novas_autosave.ses +2 = /home/ICer/verdiLog/novas_autosave.ses +[Simulation] +scsPath = scsim +scsOption = +xlPath = verilog +xlOption = +ncPath = ncsim +ncOption = -f ncsim.args +osciPath = gdb +osciOption = +vcsPath = simv +vcsOption = +mtiPath = vsim +mtiOption = +vhncPath = ncsim +vhncOption = -log debussy.nc.log +mixncPath = ncsim +mixncOption = -log debussy.mixnc.log +speedsimPath = +speedsimOption = +mti_vlogPath = vsim +mti_vlogOption = novas_vlog +vcs_mixPath = simv +vcs_mixOption = -vhdlrun "-vhpi debussy:FSDBDumpCmd" +scs_mixPath = scsim +scs_mixOption = -vhpi debussy:FSDBDumpCmd +interactiveDebugging = {True, False} +KeepBreakPoints = False +ScsDebugAll = False +simType = {vcssv, xl, nc, vcs, mti, mti_vlog, vhnc, scs, mixnc} +thirdpartyIdx = -1 +iscCmdSep = FALSE +NoAppendOption = False +[SimulationPlus] +xlPath = verilog +xlOption = +ncPath = ncsim +ncOption = -f ncsim.args +vcsPath = simv +vcsOption = +mti_vlogPath = vsim +mti_vlogOption = novas_vlog +mtiPath = vsim +mtiOption = +vhncPath = ncsim +vhncOption = -log debussy.nc.log +speedsimPath = verilog +speedsimOption = +mixncPath = ncsim +mixncOption = -log debussy.mixnc.log +scsPath = scsim +scsOption = +vcs_mixPath = simv +vcs_mixOption = -vhdlrun "-vhpi debussy:FSDBDumpCmd" +scs_mixPath = scsim +scs_mixOption = -vhpi debussy:FSDBDumpCmd +vcs_svPath = simv +vcs_svOption = +simType = vcssv +thirdpartyIdx = -1 +interactiveDebugging = FALSE +KeepBreakPoints = FALSE +iscCmdSep = FALSE +ScsDebugAll = FALSE +NoAppendOption = FALSE +invokeSimPath = work +[SimulationPlus2] +eventDumpUnfinish = FALSE +[Source] +wordWrapOn = TRUE +viewReuse = TRUE +lineNumberOn = TRUE +warnOutdatedDlg = TRUE +showEncrypt = FALSE +loadInclude = FALSE +showColorForActive = FALSE +tabWidth = 8 +editor = vi +reload = Never +sync_active_to_source = TRUE +navigateAsColored = FALSE +navigateCovered = FALSE +navigateUncovered = TRUE +navigateExcluded = FALSE +not_ask_for_source_path = FALSE +expandMacroOn = TRUE +expandMacroInstancesThreshold = 10000 +[SourceVHDL] +vhSimType = ModelSim +ohSimType = VerilogXL +[TclShell] +nLineSize = 1024 +[Test] +verbose_progress = FALSE +[TestBenchBrowser] +-showUVMDynamicHierTreeWin = FALSE +[Text] +hdlTypeName = blue4 +hdlLibrary = blue4 +viewport = 396 392 445 487 +hdlOther = ID_BLACK +hdlComment = ID_GRAY1 +hdlKeyword = ID_BLUE5 +hdlEntity = ID_BLACK +hdlEntityInst = ID_BLACK +hdlSignal = ID_RED2 +hdlInSignal = ID_RED2 +hdlOutSignal = ID_RED2 +hdlInOutSignal = ID_RED2 +hdlOperator = ID_BLACK +hdlMinus = ID_BLACK +hdlSymbol = ID_BLACK +hdlString = ID_BLACK +hdlNumberBase = ID_BLACK +hdlNumber = ID_BLACK +hdlLiteral = ID_BLACK +hdlIdentifier = ID_BLACK +hdlSystemTask = ID_BLACK +hdlParameter = ID_BLACK +hdlIncFile = ID_BLACK +hdlDataFile = ID_BLACK +hdlCDSkipIf = ID_GRAY1 +hdlMacro = ID_BLACK +hdlMacroValue = ID_BLACK +hdlPlainText = ID_BLACK +hdlOvaId = ID_PURPLE2 +hdlPslId = ID_PURPLE2 +HvlEId = ID_BLACK +HvlVERAId = ID_BLACK +hdlEscSignal = ID_BLACK +hdlEscInSignal = ID_BLACK +hdlEscOutSignal = ID_BLACK +hdlEscInOutSignal = ID_BLACK +textBackgroundColor = ID_GRAY6 +textHiliteBK = ID_BLUE5 +textHiliteText = ID_WHITE +textTracedMark = ID_GREEN2 +textLineNo = ID_BLACK +textFoldedLineNo = ID_RED5 +textUserKeyword = ID_GREEN2 +textParaAnnotText = ID_BLACK +textFuncAnnotText = ID_BLUE2 +textAnnotText = ID_BLACK +textUserDefAnnotText = ID_BLACK +ComputedSignal = ID_PURPLE5 +textAnnotTextShadow = ID_WHITE +parenthesisBGColor = ID_YELLOW5 +codeInParenthesis = ID_CYAN5 +text3DLight = ID_WHITE +text3DShadow = ID_BLACK +textHvlDriver = ID_GREEN3 +textHvlLoad = ID_YELLOW3 +textHvlDriverLoad = ID_BLUE3 +irOutline = ID_RED2 +irDriver = ID_YELLOW5 +irLoad = ID_BLACK +irBookMark = ID_YELLOW2 +irIndicator = ID_WHITE +irBreakpoint = ID_GREEN5 +irCurLine = ID_BLUE5 +hdlVhEntity = ID_BLACK +hdlArchitecture = ID_BLACK +hdlPackage = ID_BLUE5 +hdlRefPackage = ID_BLUE5 +hdlAlias = ID_BLACK +hdlGeneric = ID_BLUE5 +specialAnnotShadow = ID_BLUE1 +hdlZeroInHead = ID_GREEN2 +hdlZeroInComment = ID_GREEN2 +hdlPslHead = ID_BLACK +hdlPslComment = ID_BLACK +hdlSynopsysHead = ID_GREEN2 +hdlSynopsysComment = ID_GREEN2 +pdmlIdentifier = ID_BLACK +pdmlCommand = ID_BLACK +pdmlMacro = ID_BLACK +font = COURIER12 +annotFont = Helvetica_M_R_10 +[Text.1] +viewport = -1 27 2560 1337 45 +[TextPrinter] +Orientation = Landscape +Indicator = FALSE +LineNum = TRUE +FontSize = 7 +Column = 2 +Annotation = TRUE +[Texteditor] +TexteditorFont = "Clean 14" +TexteditorBG = white +TexteditorFG = black +[ThirdParty] +ThirdPartySimTool = verisity surefire ikos finsim +[TurboEditor] +autoBackup = TRUE +[UserButton.mixnc] +Button1 = "Dump All Signals" "call fsdbDumpvars\n" +Button2 = "Next 1000 Time" "run 1000 -relative\n" +Button3 = "Next ? Time" "run ${Arg:Next Time} -relative\n" +Button4 = "Run Next" "run -next\n" +Button5 = "Run Step" "run -step\n" +Button6 = "Run Return" "run -return\n" +Button7 = "Show Variables" "value {${NCSelVars}}\n" +Button8 = "FSDB Ver" "call fsdbVersion" +Button9 = "Dump On" "call fsdbDumpon" +Button10 = "Dump Off" "call fsdbDumpoff" +Button11 = "All Tasks" "call" +Button12 = "Dump Selected Instance" "call fsdbDumpvars 1 ${SelInst}" +[UserButton.mti] +Button1 = "Dump All Signals" "fsdbDumpvars\n" +Button2 = "Next 1000 Time" "run 1000\n" +Button3 = "Next ? Time" "run ${Arg:Next Time}\n" +Button4 = "Show Variables" "exa ${SelVars}\n" +Button5 = "Force Variable" "force -freeze ${SelVar} ${Arg:New Value} 0\n" +Button6 = "Release Variable" "noforce ${SelVar}\n" +Button7 = "Deposit Variable" "force -deposit ${SelVar} ${Arg:New Value} 0\n" +[UserButton.mti_vlog] +Button1 = "Dump All Signals" "fsdbDumpvars\n" +Button2 = "Next 1000 Time" "run 1000\n" +Button3 = "Next ? Time" "run ${Arg:Next Time}\n" +Button4 = "Show Variables" "exa ${SelVars}\n" +Button5 = "Force Variable" "force -freeze ${SelVar} ${Arg:New Value} 0\n" +Button6 = "Release Variable" "noforce ${SelVar}\n" +Button7 = "Deposit Variable" "force -deposit ${SelVar} ${Arg:New Value} 0\n" +[UserButton.nc] +Button1 = "Dump All Signals" "call fsdbDumpvars\n" +Button2 = "Next 1000 Time" "run 1000 -relative\n" +Button3 = "Next ? Time" "run ${Arg:Next Time} -relative\n" +Button4 = "Run Next" "run -next\n" +Button5 = "Run Step" "run -step\n" +Button6 = "Run Return" "run -return\n" +Button7 = "Show Variables" "value {${NCSelVars}}\n" +[UserButton.scs] +Button1 = "Dump All Signals" "call fsdbDumpvars(0, \"${TopScope}\");\n" +Button2 = "Next 1000 Time" "run 1000 \n" +Button3 = "Next ? Time" "run ${Arg:Next Time} \n" +Button4 = "Run Step" "step\n" +Button5 = "Show Variables" "ls -v {${SelVars}}\n" +[UserButton.vhnc] +Button1 = "Dump All Signals" "call fsdbDumpvars\n" +Button2 = "Next 1000 Time" "run 1000 -relative\n" +Button3 = "Next ? Time" "run ${Arg:Next Time} -relative\n" +Button4 = "Run Next" "run -next\n" +Button5 = "Run Step" "run -step\n" +Button6 = "Run Return" "run -return\n" +Button7 = "Show Variables" "value {${NCSelVars}}\n" +[UserButton.xl] +Button13 = "Dump Off" "$fsdbDumpoff;\n" +Button12 = "Dump On" "$fsdbDumpon;\n" +Button11 = "Delete Focus" "$db_deletefocus(${treeSelScope});\n" +Button10 = "Set Focus" "$db_setfocus(${treeSelScope});\n" +Button9 = "Deposit Variable" "$deposit(${SelVar},${Arg:New Value});\n" +Button8 = "Release Variable" "release ${SelVar};\n" +Button7 = "Force Variable" "force ${SelVar} = ${Arg:New Value};\n" +Button6 = "Show Variables" "$showvars(${SelVars});\n" +Button5 = "Next ? Event" "$db_step(${Arg:Next Event});\n" +Button4 = "Next Event" "$db_step(1);\n" +Button3 = "Next ? Time" "#${Arg:Next Time} $stop;.\n" +Button2 = "Next 1000 Time" "#1000 $stop;.\n" +Button1 = "Dump All Signals" "$fsdbDumpvars;\n" +[VIA] +viaLogViewerDefaultRuleOneSearchForm = "share/VIA/Apps/PredefinedRules/Misc/Onesearch_rule.rc" +[VIA.oneSearch.preference] +DefaultDisplayTimeUnit = "1.000000ns" +DefaultLogTimeUnit = "1.000000ns" +[VIA.oneSearch.preference.vgifColumnSettingRC] +[VIA.oneSearch.preference.vgifColumnSettingRC.setting0] +parRuleSets = "" +[VIA.oneSearch.preference.vgifColumnSettingRC.setting0.column0] +name = Severity +width = 60 +visualIndex = 1 +isHidden = TRUE +isUserChangeColumnVisible = FALSE +[VIA.oneSearch.preference.vgifColumnSettingRC.setting0.column1] +name = Time +width = 60 +visualIndex = 0 +isHidden = TRUE +isUserChangeColumnVisible = FALSE +[VIA.oneSearch.preference.vgifColumnSettingRC.setting0.column2] +name = Code +width = 60 +visualIndex = 2 +isHidden = TRUE +isUserChangeColumnVisible = FALSE +[VIA.oneSearch.preference.vgifColumnSettingRC.setting0.column3] +name = Type +width = 60 +visualIndex = 3 +isHidden = TRUE +isUserChangeColumnVisible = FALSE +[VIA.oneSearch.preference.vgifColumnSettingRC.setting0.column4] +name = Message +width = 2000 +visualIndex = 4 +isHidden = FALSE +isUserChangeColumnVisible = FALSE +[Vi] +ViFont = "Clean 14" +ViBG = white +ViFG = black +[Wave] +ovaEventSuccessColor = -c ID_CYAN5 +ovaEventFailureColor = -c ID_RED5 +ovaBooleanSuccessColor = -c ID_CYAN5 +ovaBooleanFailureColor = -c ID_RED5 +ovaAssertSuccessColor = -c ID_GREEN5 +ovaAssertFailureColor = -c ID_RED5 +ovaForbidSuccessColor = -c ID_GREEN5 +SigGroupRuleFile = +DisplayFileName = FALSE +waveform_vertical_scroll_bar = TRUE +scope_to_save_with_macro +open_file_dir +open_rc_file_dir +getSignalForm = 0 0 800 479 100 30 100 30 +viewPort = 0 27 2560 588 100 65 +signalSpacing = 5 +digitalSignalHeight = 15 +analogSignalHeight = 98 +commentSignalHeight = 98 +transactionSignalHeight = 98 +messageSignalHeight = 98 +minCompErrWidth = 4 +DragZoomTolerance = 4 +maxTransExpandedLayer = 10 +WaveMaxPoint = 512 +legendBackground = -c ID_BLACK +valueBackground = -c ID_BLACK +curveBackground = -c ID_BLACK +getSignalSignalList_BackgroundColor = -c ID_GRAY6 +glitchColor = -c ID_RED5 +cursor = -c ID_YELLOW5 -lw 1 -ls long_dashed +marker = -c ID_WHITE -lw 1 -ls dash_dot_l +usermarker = -c ID_GREEN5 -lw 1 -ls long_dashed +trace = -c ID_GRAY5 -lw 1 -ls long_dashed +grid = -c ID_WHITE -lw 1 -ls short_dashed +rulerBackground = -c ID_GRAY3 +rulerForeground = -c ID_YELLOW5 +busTextColor = -c ID_ORANGE8 +legendForeground = -c ID_CYAN5 +valueForeground = -c ID_CYAN5 +curveForeground = -c ID_CYAN5 +groupNameColor = -c ID_GREEN5 +commentStringColor = -c ID_RED5 +region(Active)Background = -c ID_YELLOW1 +region(NBA)Background = -c ID_RED1 +region(Re-Active)Background = -c ID_YELLOW3 +region(Re-NBA)Background = -c ID_RED3 +region(VHDL-Delta)Background = -c ID_ORANGE3 +region(Dump-Off)Background = -c ID_GRAY4 +High_Light = -c ID_GRAY2 +Input_Signal = -c ID_RED5 +Output_Signal = -c ID_GREEN5 +InOut_Signal = -c ID_BLUE5 +Net_Signal = -c ID_YELLOW5 +Register_Signal = -c ID_PURPLE5 +Verilog_Signal = -c ID_CYAN5 +VHDL_Signal = -c ID_ORANGE5 +SystemC_Signal = -c ID_BLUE7 +Dump_Off_Color = -c ID_BLUE2 +Compress_Bar_Color = -c ID_YELLOW4 +Vector_Dense_Block_Color = -c ID_ORANGE8 +Scalar_Dense_Block_Color = -c ID_GREEN6 +Analog_Dense_Block_Color = -c ID_PURPLE2 +Composite_Dense_Block_Color = -c ID_ORANGE5 +RPTR_Power_Off_Layer = -c ID_CYAN3 -stipple dots +DB_Power_Off_Layer = -c ID_BLUE4 -stipple dots +SPA_Driver_Power_Off_Layer = -c ID_ORANGE4 -stipple dots +SPA_Receiver_Power_Off_Layer = -c ID_GREEN5 -stipple dots +SRSN_Power_Off_Layer = -c ID_GREEN4 -stipple dots +Isolation_Power_Off_Layer = -c ID_RED4 -stipple dots +PD_Power_Off_Layer = -c ID_GRAY4 -stipple dots +Isolation_Layer = -c ID_RED4 -stipple vLine +Retention_Level_Trigger_Layer = -c ID_ORANGE1 -stipple fill_solid +Retention_Edge_Trigger_Layer = -c ID_YELLOW6 -stipple fill_solid +Driving_Power_Off_Layer = -c ID_YELLOW2 -stipple x +Toggle_Layer = -c ID_YELLOW4 -stipple slash +analogRealStyle = pwl +analogVoltageStyle = pwl +analogCurrentStyle = pwl +analogOthersStyle = pwl +busSignalLayer = -c ID_ORANGE8 +busZLayer = -c ID_ORANGE6 +busMixedLayer = -c ID_GREEN5 +busNotComputedLayer = -c ID_GRAY1 +busNoValueLayer = -c ID_BLUE2 +signalGridLayer = -c ID_WHITE +analogGridLayer = -c ID_GRAY6 +analogRulerLayer = -c ID_GRAY6 +keywordLayer = -c ID_RED5 +loadedLayer = -c ID_BLUE5 +loadingLayer = -c ID_BLACK +qdsCurMarkerLayer = -c ID_BLUE5 +qdsBrkMarkerLayer = -c ID_GREEN5 +qdsTrgMarkerLayer = -c ID_RED5 +arrowDefaultColor = -c ID_ORANGE6 +startNodeArrowColor = -c ID_WHITE +endNodeArrowColor = -c ID_YELLOW5 +propertyEventMatchColor = -c ID_GREEN5 +propertyEventNoMatchColor = -c ID_RED5 +propertyVacuousSuccessMatchColor = -c ID_YELLOW2 +propertyStatusBoundaryColor = -c ID_WHITE +propertyBooleanSuccessColor = -c ID_CYAN5 +propertyBooleanFailureColor = -c ID_RED5 +propertyAssertSuccessColor = -c ID_GREEN5 +propertyAssertFailureColor = -c ID_RED5 +propertyForbidSuccessColor = -c ID_GREEN5 +transactionForegroundColor = -c ID_YELLOW8 +transactionBackgroundColor = -c ID_BLACK +transactionHighLightColor = -c ID_CYAN6 +transactionRelationshipColor = -c ID_PURPLE6 +transactionErrorTypeColor = -c ID_RED5 +coverageFullyCoveredColor = -c ID_GREEN5 +coverageNoCoverageColor = -c ID_RED5 +coveragePartialCoverageColor = -c ID_YELLOW5 +coverageReferenceLineColor = -c ID_GRAY4 +messageForegroundColor = -c ID_YELLOW4 +messageBackgroundColor = -c ID_PURPLE1 +messageHighLightColor = -c ID_CYAN6 +messageInformationColor = -c ID_RED5 +ComputedAnnotColor = -c ID_PURPLE5 +fsvSecurityDataColor = -c ID_PURPLE3 +qdsAutoBusGroup = TRUE +qdsTimeStampMode = FALSE +qdsVbfBusOrderAscending = FALSE +openDumpFilter = *.fsdb;*.vf;*.jf +DumpFileFilter = *.vcd +RestoreSignalFilter = *.rc +SaveSignalFilter = *.rc +AddAliasFilter = *.alias;*.adb +CompareSignalFilter = *.err +ConvertFFFilter = *.vcd;*.out;*.tr0;*.xp;*.raw;*.wfm +Scroll_Ratio = 100 +Zoom_Ratio = 10 +EventSequence_SyncCursorTime = TRUE +EventSequence_Sorting = FALSE +EventSequence_RemoveGrid = FALSE +EventSequence_IsGridMode = FALSE +SetDefaultRadix_global = FALSE +DefaultRadix = Hex +SigSearchSignalMatchCase = FALSE +SigSearchSignalScopeOption = FALSE +SigSearchSignalSamenetInterface = FALSE +SigSearchSignalFullScope = FALSE +SigSearchSignalWithRegExp = FALSE +SigSearchDynamically = FALSE +SigDisplayBySelectionOrder = FALSE +SigDisplayRowMajor = FALSE +SigDragSelFollowColumn = FALSE +SigDisplayHierarchyBox = TRUE +SigDisplaySubscopeBox = TRUE +SigDisplayEmptyScope = TRUE +SigDisplaySignalNavigationBox = FALSE +SigDisplayFormBus = TRUE +SigShowSubProgram = TRUE +SigSearchScopeDynamically = TRUE +SigCollapseSubtreeNodes = FALSE +activeFileApplyToAnnotation = FALSE +GrpSelMode = TRUE +dispGridCount = FALSE +hierarchyName = FALSE +partial_level_name = FALSE +partial_level_head = 1 +partial_level_tail = 1 +displayMessageLabelOnly = TRUE +autoInsertDumpoffs = TRUE +displayMessageCallStack = FALSE +displayCallStackWithFullSections = TRUE +displayCallStackWithLastSection = FALSE +limitMessageMaxWidth = FALSE +messageMaxWidth = 50 +displayTransBySpecificColor = FALSE +fittedTransHeight = FALSE +snap = TRUE +gravitySnap = FALSE +displayLeadingZero = FALSE +displayGlitchs = FALSE +allfileTimeRange = FALSE +fixDelta = FALSE +displayCursorMarker = FALSE +autoUpdate = FALSE +restoreFromActiveFile = TRUE +restoreToEnd = FALSE +dispCompErr = TRUE +showMsgDes = TRUE +anaAutoFit = FALSE +anaAutoPattn = FALSE +anaAuto100VertFit = FALSE +displayDeltaY = FALSE +centerCursor = FALSE +denseBlockDrawing = TRUE +relativeFreqPrecision = 3 +showMarkerAbsolute = FALSE +showMarkerAdjacent = FALSE +showMarkerRelative = FALSE +showMarkerFrequency = FALSE +stickCursorMarkerOnWaveform = TRUE +keepMarkerAtEndTimeOfTransaction = FALSE +doubleClickToExpandTransaction = TRUE +expandTransactionAssociatedSignals = TRUE +expandTransactionAttributeSignals = FALSE +WaveExtendLastTick = TRUE +InOutSignal = FALSE +NetRegisterSignal = FALSE +VerilogVHDLSignal = FALSE +LabelMarker = TRUE +ResolveSymbolicLink = TRUE +signal_rc_abspath = TRUE +signal_rc_no_natural_bus_range = FALSE +save_scope_with_macro = FALSE +TipInSignalWin = FALSE +DisplayPackedSiganlInBitwiseManner = FALSE +DisplaySignalTypeAheadOfSignalName = TRUE ICON +TipInCurveWin = FALSE +MouseGesturesInCurveWin = TRUE +DisplayLSBsFirst = FALSE +PaintSpecificColorPattern = TRUE +ModuleName = TRUE +form_all_memory_signal = FALSE +formBusSignalFromPartSelects = FALSE +read_value_change_on_demand_for_drawing = FALSE +load_scopes_on_demand = on 5 +TransitionMode = TRUE +DisplayRadix = FALSE +SchemaX = FALSE +Hilight = TRUE +UseBeforeValue = FALSE +DisplayFileNameAheadOfSignalName = FALSE +DisplayFileNumberAheadOfSignalName = FALSE +DisplayValueSpace = TRUE +FitAnaByBusSize = FALSE +displayTransactionAttributeName = FALSE +expandOverlappedTrans = FALSE +dispSamplePointForAttrSig = TRUE +dispClassName = TRUE +ReloadActiveFileOnly = FALSE +NormalizeEVCD = FALSE +OverwriteAliasWithRC = TRUE +overlay_added_analog_signals = FALSE +case_insensitive = FALSE +vhdlVariableCalculate = TRUE +showError = TRUE +signal_vertical_scroll_bar = TRUE +showPortNameForDroppedInstance = FALSE +truncateFilePathInTitleBar = TRUE +filterPropVacuousSuccess = FALSE +includeLocalSignals = FALSE +encloseSignalsByGroup = TRUE +resaveSignals = TRUE +adjustBusPrefix = adjustBus_ +adjustBusBits = 1 +adjustBusSettings = 69889 +maskPowerOff = TRUE +maskIsolation = TRUE +maskRetention = TRUE +maskDrivingPowerOff = TRUE +maskToggle = TRUE +autoBackupSignals = off 5 "\"/home/ICer/verdiLog\"" "\"novas_autosave_sig\"" +signal_rc_attribute = 65535 +signal_rc_alias_attribute = 0 +ConvertAttr1 = -inc FALSE +ConvertAttr2 = -hier FALSE +ConvertAttr3 = -ucase FALSE +ConvertAttr4 = -lcase FALSE +ConvertAttr5 = -org FALSE +ConvertAttr6 = -mem 24 +ConvertAttr7 = -deli . +ConvertAttr8 = -hier_scope FALSE +ConvertAttr9 = -inst_array FALSE +ConvertAttr10 = -vhdlnaming FALSE +ConvertAttr11 = -orgScope FALSE +analogFmtPrecision = Automatic 2 +confirmOverwrite = TRUE +confirmExit = TRUE +confirmGetAll = TRUE +printTimeRange = TRUE 0.000000 0.000000 0.000000 +printPageRange = TRUE 1 1 +printOption = 0 +printBasic = 1 0 0 FALSE FALSE +printDest = -printer {} +printSignature = {%f %h %t} {} +curveWindow_Drag&Drop_Mode = TRUE +hspiceIncOpenMode = TRUE +pcSelectMode = TRUE +hierarchyDelimiter = / +RecentFile1 = "\"/home/ICer/thfu/XYZ/Test/v1.6/case2/TB1.fsdb\"" +open_file_time_range = FALSE +value_window_aligment = Right +signal_window_alignment = Auto +ShowDeltaTime = TRUE +legend_window_font = -f COURIER12 -c ID_CYAN5 +value_window_font = -f COURIER12 -c ID_CYAN5 +curve_window_font = -f COURIER12 -c ID_CYAN5 +group_name_font = -f COURIER12 -c ID_GREEN5 +ruler_value_font = -f COURIER12 -c ID_CYAN5 +analog_ruler_value_font = -f COURIER12 -c ID_CYAN5 +comment_string_font = -f COURIER12 -c ID_RED5 +getsignal_form_font = -f COURIER12 +SigsCheckNum = on 1000 +filter_synthesized_net = off n +filterOutNet = on +filter_synthesized_instance = off +filterOutInstance = on +showGroupTree = TRUE +hierGroupDelim = / +MsgSeverityColor = {y \"Severity\"==\"1\" ID_RED5} {y \"Severity\"==\"2\" ID_RED6} {y \"Severity\"==\"3\" ID_RED7} {y \"Severity\"==\"4\" ID_RED8} {y \"Severity\"==\"5\" ID_ORANGE5} {y \"Severity\"==\"6\" ID_ORANGE6} {y \"Severity\"==\"7\" ID_ORANGE7} {y \"Severity\"==\"8\" \ +ID_GREEN7} {y \"Severity\"==\"9\" ID_GREEN6} {y \"Severity\"==\"10\" ID_GREEN5} +AutoApplySeverityColor = TRUE +AutoAdjustMsgWidthByLabel = off +verilogStrengthDispType = type1 +waveDblClkActiveTrace = on +autoConnectTBrowser = FALSE +connectTBrowserInContainer = TRUE +SEQShowComparisonIcon = TRUE +SEQAddDriverLoadInSameGroup = TRUE +autoSyncCursorMarker = FALSE +autoSyncHorizontalRange = FALSE +autoSyncVerticalScroll = FALSE +[cov_hier_name_column] +justify = TRUE +[coverageColors] +sou_uncov = TRUE +sou_pc = TRUE +sou_cov = TRUE +sou_exuncov = TRUE +sou_excov = TRUE +sou_unreach = TRUE +sou_unreachcon = TRUE +sou_fillColor_uncov = red +sou_fillColor_pc = yellow +sou_fillColor_cov = green3 +sou_fillColor_exuncov = grey +sou_fillColor_excov = #3C9371 +sou_fillColor_unreach = grey +sou_fillColor_unreachcon = orange +numberOfBins = 6 +rangeMin_0 = 0 +rangeMax_0 = 20 +fillColor_0 = #FF6464 +rangeMin_1 = 20 +rangeMax_1 = 40 +fillColor_1 = #FF9999 +rangeMin_2 = 40 +rangeMax_2 = 60 +fillColor_2 = #FF8040 +rangeMin_3 = 60 +rangeMax_3 = 80 +fillColor_3 = #FFFF99 +rangeMin_4 = 80 +rangeMax_4 = 100 +fillColor_4 = #99FF99 +rangeMin_5 = 100 +rangeMax_5 = 100 +fillColor_5 = #64FF64 +[coveragesetting] +assertTopoMode = FALSE +urgAppendOptions = +group_instance_new_format_name = TRUE +showvalue = FALSE +computeGroupsScoreByRatio = FALSE +computeGroupsScoreByInst = FALSE +showConditionId = FALSE +showfullhier = FALSE +nameLeftAlignment = TRUE +showAllInfoInTooltips = FALSE +copyItemHvpName = TRUE +ignoreGroupWeight = FALSE +absTestName = FALSE +HvpMergeTool = +ShowMergeMenuItem = FALSE +fsmScoreMode = transition +[eco] +NameRule = +IsFreezeSilicon = FALSE +cellQuantityManagement = FALSE +ManageMode = INSTANCE_NAME +SpareCellsPinsManagement = TRUE +LogCommitReport = FALSE +InputPinStatus = 1 +OutputPinStatus = 2 +RevisedComponentColor = ID_BLUE5 +SpareCellColor = ID_RED5 +UserName = ICer +CommentFormat = Novas ECO updated by ${UserName} ${Date} ${Time} +PrefixN = eco_n +PrefixP = eco_p +PrefixI = eco_i +DefaultTieUpNet = 1'b1 +DefaultTieDownNet = 1'b0 +MultipleInstantiations = TRUE +KeepClockPinConnection = FALSE +KeepAsyncResetPinConnection = FALSE +ScriptFileModeType = 1 +MagmaScriptPower = VDD +MagmaScriptGround = GND +ShowModeMsg = TRUE +AstroScriptPower = VDD +AstroScriptGround = VSS +ClearFloatingPorts = FALSE +[eco_connection] +Port/NetIsUnique = TRUE +SerialNet = 0 +SerialPort = 0 +SerialInst = 0 +[finsim] +TPLanguage = Verilog +TPName = Super-FinSim +TPPath = TOP.sim +TPOption = +AddImportArgument = FALSE +LineBreakWithScope = FALSE +StopAfterCompileOption = -i +[hvpsetting] +importExcelXMLOptions = +use_test_loca_as_source = FALSE +autoTurnOffHideMeetGoalInit = FALSE +autoTurnOffHideMeetGoal = TRUE +autoTurnOffModifierInit = FALSE +autoTurnOffModifier = TRUE +enableNumbering = TRUE +autoSaveCheck = TRUE +autoSaveTime = 5 +ShowMissingScore = TRUE +enableFeatureId = FALSE +enable_HVP_FEAT_ID = FALSE +enableMeasureConcealment = FALSE +HvpCloneHierShowMsgAgain = 1 +HvpCloneHierType = tree +HvpCloneHierMetrics = Line,Cond,FSM,Toggle,Branch,Assert +autoRecalPlanAfterLoadingCovDBUserDataPlan = false +warnMeAutoRecalPlanAfterLoadingCovDBUserDataPlan = true +autoRecalExclWithPlan = false +warnMeAutoRecalExclWithPlan = true +autoRecalPlanWithExcl = false +warnMeAutoRecalPlanWithExcl = true +warnPopupWarnWhenMultiFilters = true +warnPopupWarnIfHvpReadOnly = true +unmappedObjsReportLevel = def_var_inst +unmappedObjsReportInst = true +unmappedObjsNumOfObjs = High +[ikos] +TPLanguage = VHDL +TPName = Voyager +TPPath = vsh +TPOption = -X +AddImportArgument = FALSE +LineBreakWithScope = FALSE +StopAfterCompileOption = -i +[imp] +options = NULL +libPath = NULL +libDir = NULL +[nCompare] +ErrorViewport = 80 180 800 550 +EditorViewport = 409 287 676 475 +EditorHeightWidth = 802 380 +WaveCommand = "novas" +WaveArgs = "-nWave" +[nCompare.Wnd0] +ViewByHier = FALSE +[nMemory] +dispMode = ADDR_HINT +addrColWidth = 120 +valueColWidth = 100 +showCellBitRangeWithAddr = TRUE +wordsShownInOneRow = 8 +syncCursorTime = FALSE +fixCellColumnWidth = FALSE +font = Courier 12 +[planColors] +plan_fillColor_inactive = lightGray +plan_fillColor_warning = orange +plan_fillColor_error = red +plan_fillColor_invalid = #F0DCDB +plan_fillColor_subplan = lightGray +[schematics] +viewport = 178 262 638 516 +schBackgroundColor = black lineSolid +schBackgroundColor_qt = #000000 qt_solidLine 1 +schBodyColor = orange6 lineSolid +schBodyColor_qt = #ffb973 qt_solidLine 1 +schAsmBodyColor = blue7 lineSolid +schAsmBodyColor_qt = #a5a5ff qt_solidLine 1 +schPortColor = orange6 lineSolid +schPortColor_qt = #ffb973 qt_solidLine 1 +schCellNameColor = Gray6 lineSolid +schCellNameColor_qt = #e0e0e0 qt_solidLine 1 +schCLKNetColor = red6 lineSolid +schCLKNetColor_qt = #ff7373 qt_solidLine 1 +schPWRNetColor = red4 lineSolid +schPWRNetColor_qt = #ff0101 qt_solidLine 1 +schGNDNetColor = cyan4 lineSolid +schGNDNetColor_qt = #01ffff qt_solidLine 1 +schSIGNetColor = green8 lineSolid +schSIGNetColor_qt = #cdffcd qt_solidLine 1 +schTraceColor = yellow4 lineSolid +schTraceColor_qt = #ffff01 qt_solidLine 2 +schBackAnnotateColor = white lineSolid +schBackAnnotateColor_qt = #ffffff qt_solidLine 1 +schValue0 = yellow4 lineSolid +schValue0_qt = #ffff01 qt_solidLine 1 +schValue1 = green3 lineSolid +schValue1_qt = #008000 qt_solidLine 1 +schValueX = red4 lineSolid +schValueX_qt = #ff0101 qt_solidLine 1 +schValueZ = purple7 lineSolid +schValueZ_qt = #ffcdff qt_solidLine 1 +dimColor = cyan2 lineSolid +dimColor_qt = #008080 qt_solidLine 1 +schPreSelColor = green4 lineDash +schPreSelColor_qt = #01ff01 qt_dashLine 2 +schSIGBusNetColor = green8 lineSolid +schSIGBusNetColor_qt = #cdffcd qt_solidLine +schGNDBusNetColor = cyan4 lineSolid +schGNDBusNetColor_qt = #01ffff qt_solidLine +schPWRBusNetColor = red4 lineSolid +schPWRBusNetColor_qt = #ff0101 qt_solidLine +schCLKBusNetColor = red6 lineSolid +schCLKBusNetColor_qt = #ff7373 qt_solidLine +schEdgeSensitiveColor = orange6 lineSolid +schEdgeSensitiveColor_qt = #ffb973 qt_solidLine +schAnnotColor = cyan4 lineSolid +schAnnotColor_qt = #01ffff qt_solidLine +schInstNameColor = orange6 lineSolid +schInstNameColor_qt = #ffb973 qt_solidLine +schPortNameColor = cyan4 lineSolid +schPortNameColor_qt = #01ffff qt_solidLine +schAsmLatchColor = cyan4 lineSolid +schAsmLatchColor_qt = #01ffff qt_solidLine +schAsmRegColor = cyan4 lineSolid +schAsmRegColor_qt = #01ffff qt_solidLine +schAsmTriColor = cyan4 lineSolid +schAsmTriColor_qt = #01ffff qt_solidLine +pre_select = True +ShowPassThroughNet = False +ComputedAnnotColor = ID_PURPLE5 +[schematics_print] +Signature = FALSE +DesignName = PCU +DesignerName = bai +SignatureLocation = LowerRight +MultiPage = TRUE +AutoSliver = FALSE +[sourceColors] +BackgroundActive = gray88 +BackgroundInactive = lightgray +InactiveCode = dimgray +Selection = darkblue +Standard = black +Keyword = blue +Comment = gray25 +Number = black +String = black +Identifier = darkred +Inline = green +colorIdentifier = green +Value = darkgreen +MacroBackground = white +Missing = #400040 +[specColors] +top_plan_linked = #ADFFA6 +top_plan_ignore = #D3D3D3 +top_plan_todo = #EECBAD +sub_plan_ignore = #919191 +sub_plan_todo = #EFAFAF +sub_plan_linked = darkorange +[spec_link_setting] +use_spline = true +goto_section = false +exclude_ignore = true +truncate_abstract = false +abstract_length = 999 +compare_strategy = 2 +auto_apply_margin = FALSE +margin_top = 0.80 +margin_bottom = 0.80 +margin_left = 0.50 +margin_right = 0.50 +margin_unit = inches +[spiceDebug] +ThroughNet = ID_YELLOW5 +InstrumentSig = ID_GREEN5 +InterfaceElement = ID_GREEN5 +Run-timeInterfaceElement = ID_BLUE5 +HighlightThroughNet = TRUE +HighlightInterfaceElement = TRUE +HighlightRuntimeInterfaceElement = TRUE +HighlightSameNet = TRUE +[surefire] +TPLanguage = Verilog +TPName = SureFire +TPPath = verilog +TPOption = +AddImportArgument = TRUE +LineBreakWithScope = TRUE +StopAfterCompileOption = -tcl +[turboSchema_Printer_Options] +Orientation = Landscape +[turbo_library] +bdb_load_scope = +[vdCovFilteringSearchesStrings] +keepLastUsedFiltersMaxNum = 10 +[verisity] +TPLanguage = Verilog +TPName = "Verisity SpeXsim" +TPPath = vlg +TPOption = +AddImportArgument = FALSE +LineBreakWithScope = TRUE +StopAfterCompileOption = -s +[wave.0] +viewPort = 0 27 2560 588 100 65 +[wave.1] +viewPort = 127 219 960 332 100 65 +[wave.2] +viewPort = 38 314 686 205 100 65 +[wave.3] +viewPort = 63 63 700 400 65 41 +[wave.4] +viewPort = 84 84 700 400 65 41 +[wave.5] +viewPort = 92 105 700 400 65 41 +[wave.6] +viewPort = 0 0 700 400 65 41 +[wave.7] +viewPort = 21 21 700 400 65 41 diff --git a/case2/spi_driver.sv b/case2/spi_driver.sv new file mode 100644 index 0000000..a8492d8 --- /dev/null +++ b/case2/spi_driver.sv @@ -0,0 +1,389 @@ +//2024-06-24,randc with random search +class spi_driver; + + static bit my_cmd=1'b0; + static bit[24:0] last_addr; + static int last_size; + + //MOSI data pkt, other input_signals are not packed + spi_trans m_trans; + + //interface + virtual spi_if vif; + + //MOSI data_stream input to SPI(DUT) + bit stream[$]; + + //parameter for randomization + int pktnum; + int interval; + int half_sclk; + bit autarchy; + rand int error_time; + + constraint cstr{ + error_time <= 544; + error_time >= -544; + } + + covergroup SYSAddr; + coverpoint m_trans.addr{ + bins IDR = {[25'h00:25'h03]}; + bins VIDR = {[25'h04:25'h07]}; + bins DATER = {[25'h08:25'h0B]}; + bins VERR = {[25'h0C:25'h0F]}; + bins TESTR = {[25'h10:25'h13]}; + bins IMR = {[25'h14:25'h17]}; + bins ISR = {[25'h18:25'h1B]}; + bins SFRTR = {[25'h1C:25'h1F]}; + bins SFRR = {[25'h20:25'h23]}; + bins CH0RSTR = {[25'h24:25'h27]}; + bins CH1RSTR = {[25'h28:25'h2B]}; + bins CH2RSTR = {[25'h2C:25'h2F]}; + bins CH3RSTR = {[25'h30:25'h33]}; + bins DBGCFGR = {[25'h34:25'h37]}; + bins MISR = {[25'h40:25'h43]}; + } + option.per_instance = 1; + endgroup + + covergroup INSTRAddr; + coverpoint m_trans.addr{ + bins INSTRCTION[8192] = {[25'h010_0000:25'h010_7FFF]}; + } + option.per_instance = 1; + endgroup + + covergroup DATAAddr; + coverpoint m_trans.addr{ + bins DATA[8192] = {[25'h020_0000:25'h020_7FFF]}; + } + option.per_instance = 1; + endgroup + + covergroup CTRAddr; + coverpoint m_trans.addr{ + bins MCUPARAR0 = {[25'h30_0000:25'h30_0003]}; + bins MCUPARAR1 = {[25'h30_0004:25'h30_0007]}; + bins MCUPARAR2 = {[25'h30_0008:25'h30_000B]}; + bins MCUPARAR3 = {[25'h30_000C:25'h30_000F]}; + bins MCURESR0 = {[25'h30_0010:25'h30_0013]}; + bins MCURESR1 = {[25'h30_0014:25'h30_0017]}; + bins MCURESR2 = {[25'h30_0018:25'h30_001B]}; + bins MCURESR3 = {[25'h30_001C:25'h30_001F]}; + bins RTIMR = {[25'h30_0098:25'h30_009B]}; + bins ICNTR = {[25'h30_009C:25'h30_009F]}; + bins FSIR = {[25'h30_00A0:25'h30_00A3]}; + bins MODMR = {[25'h30_0100:25'h30_0103]}; + bins INTPMR = {[25'h30_0104:25'h30_0107]}; + bins MIXNCOCR = {[25'h30_0108:25'h30_010B]}; + bins MIXNFCWHR = {[25'h30_010C:25'h30_010F]}; + bins MIXNFCWLR = {[25'h30_0110:25'h30_0113]}; + bins MIXNPHAR = {[25'h30_0114:25'h30_0117]}; + bins MIXMR = {[25'h30_0118:25'h30_011B]}; + bins MIXODTR = {[25'h30_011C:25'h30_011F]}; + bins MIXODFR = {[25'h30_0120:25'h30_0123]}; + + bins ROLER = {[25'h30_0128:25'h30_012B]}; + bins MIXNCOSCER = {[25'h30_012C:25'h30_012F]}; + bins MODDOTR = {[25'h30_0130:25'h30_0133]}; + bins STR = {[25'h30_0134:25'h30_0137]}; + } + option.per_instance = 1; + endgroup + + covergroup ENVELOPEIDAddr; + coverpoint m_trans.addr{ + bins ENVELOPEID[64] = {[25'h040_0000:25'h040_00FF]}; + } + option.per_instance = 1; + endgroup + + covergroup ENVELOPEDATAAddr; + coverpoint m_trans.addr{ + bins ENVELOPEDATA[8192] = {[25'h050_0000:25'h050_7FFF]}; + } + option.per_instance = 1; + endgroup + + covergroup DACAddr; + coverpoint m_trans.addr{ + bins PRBSCR = {[25'h060_0000:25'h060_0003]}; + bins SET0CR = {[25'h060_0004:25'h060_0007]}; + bins SET1CR = {[25'h060_0008:25'h060_000B]}; + bins SET2CR = {[25'h060_000C:25'h060_000F]}; + bins SET3CR = {[25'h060_0010:25'h060_0013]}; + bins SET4CR = {[25'h060_0014:25'h060_0017]}; + bins SET5CR = {[25'h060_0018:25'h060_001B]}; + bins SET6CR = {[25'h060_001C:25'h060_001F]}; + bins SET7CR = {[25'h060_0020:25'h060_0023]}; + bins SET8CR = {[25'h060_0024:25'h060_0027]}; + bins SET9CR = {[25'h060_0028:25'h060_002B]}; + bins SET10CR = {[25'h060_002C:25'h060_002F]}; + bins SET11CR = {[25'h060_0030:25'h060_0033]}; + bins SET12CR = {[25'h060_0034:25'h060_0037]}; + bins SET13CR = {[25'h060_0038:25'h060_003B]}; + bins SET14CR = {[25'h060_003C:25'h060_003F]}; + bins SET15CR = {[25'h060_0040:25'h060_0043]}; + bins DACADDR = {[25'h060_0044:25'h060_0047]}; + bins DACDW = {[25'h060_0048:25'h060_004B]}; + bins DACREF = {[25'h060_004C:25'h060_004F]}; + bins PRBSRST0 = {[25'h060_0050:25'h060_0053]}; + bins PRBSSET0 = {[25'h060_0054:25'h060_0057]}; + bins PRBSRST1 = {[25'h060_0058:25'h060_005B]}; + bins PRBSSET1 = {[25'h060_005C:25'h060_005F]}; + bins PRBSREV = {[25'h060_0060:25'h060_0063]}; + bins CALSIG = {[25'h060_0064:25'h060_0067]}; + bins CALEND = {[25'h060_0068:25'h060_006B]}; + bins CALRSTN = {[25'h060_006C:25'h060_006F]}; + bins CALDIVRSTN = {[25'h060_0070:25'h060_0073]}; + } + option.per_instance = 1; + endgroup + + covergroup MCUAddr; + coverpoint m_trans.addr{ + bins MCUPARAR0 = {[25'h70_0000:25'h70_0003]}; + bins MCUPARAR1 = {[25'h70_0004:25'h70_0007]}; + bins MCUPARAR2 = {[25'h70_0008:25'h70_000B]}; + bins MCUPARAR3 = {[25'h70_000C:25'h70_000F]}; + bins MCURESR0 = {[25'h70_0010:25'h70_0013]}; + bins MCURESR1 = {[25'h70_0014:25'h70_0017]}; + bins MCURESR2 = {[25'h70_0018:25'h70_001B]}; + bins MCURESR3 = {[25'h70_001C:25'h70_001F]}; + bins CWFR0 = {[25'h70_0040:25'h70_0043]}; + bins CWFR1 = {[25'h70_0044:25'h70_0047]}; + bins CWFR2 = {[25'h70_0048:25'h70_004B]}; + bins CWFR3 = {[25'h70_004C:25'h70_004F]}; + bins CWPRR = {[25'h70_0050:25'h70_0053]}; + bins GAPR0 = {[25'h70_0054:25'h70_0057]}; + bins GAPR1 = {[25'h70_0058:25'h70_005B]}; + bins GAPR2 = {[25'h70_005C:25'h70_005F]}; + bins GAPR3 = {[25'h70_0060:25'h70_0063]}; + bins GAPR4 = {[25'h70_0064:25'h70_0067]}; + bins GAPR5 = {[25'h70_0068:25'h70_006B]}; + bins GAPR6 = {[25'h70_006C:25'h70_006F]}; + bins GAPR7 = {[25'h70_0070:25'h70_0073]}; + bins LCPR = {[25'h70_0074:25'h70_0077]}; + bins AMPR0 = {[25'h70_0078:25'h70_007B]}; + bins AMPR1 = {[25'h70_007C:25'h70_007F]}; + bins AMPR2 = {[25'h70_0080:25'h70_0083]}; + bins AMPR3 = {[25'h70_0084:25'h70_0087]}; + bins BIASR0 = {[25'h70_0088:25'h70_008B]}; + bins BIASR1 = {[25'h70_008C:25'h70_008F]}; + bins BIASR2 = {[25'h70_0090:25'h70_0093]}; + bins BIASR3 = {[25'h70_0094:25'h70_0097]}; + bins RTIMR = {[25'h70_0098:25'h70_009B]}; + bins ICNTR = {[25'h70_009C:25'h70_009F]}; + bins FSIR = {[25'h70_00A0:25'h70_00A3]}; + bins INTPSELR = {[25'h70_00A4:25'h70_00A7]}; + } + option.per_instance = 1; + endgroup + + covergroup DBGAddr; + coverpoint m_trans.addr{ + bins DBGAddr[1024] = {[25'h190_0000:25'h190_0FFF]}; + } + option.per_instance = 1; + endgroup + + + covergroup PLLAddr; + coverpoint m_trans.addr{ + bins INTPLL_REFCTRL = {[25'h1f0_0000:25'h1f0_0003]}; + bins INTPLL_PCNT = {[25'h1f0_0004:25'h1f0_0007]}; + bins INTPLL_PFDCTRL = {[25'h1f0_0008:25'h1f0_000B]}; + bins INTPLL_SPDCTRL = {[25'h1f0_000C:25'h1f0_000F]}; + bins INTPLL_PTATCTRL = {[25'h1f0_0010:25'h1f0_0013]}; + bins INTPLL_FLLCTRL = {[25'h1f0_0014:25'h1f0_0017]}; + bins INTPLL_SELCTRL = {[25'h1f0_0018:25'h1f0_001B]}; + bins INTPLL_VCOCTRL = {[25'h1f0_001C:25'h1f0_001F]}; + bins INTPLL_VCOFBADJ = {[25'h1f0_0020:25'h1f0_0023]}; + bins INTPLL_AFCCTRL = {[25'h1f0_0024:25'h1f0_0027]}; + bins INTPLL_AFCCNT = {[25'h1f0_0028:25'h1f0_002B]}; + bins INTPLL_AFCLDCNT = {[25'h1f0_002C:25'h1f0_002F]}; + bins INTPLL_AFCPRES = {[25'h1f0_0030:25'h1f0_0033]}; + bins INTPLL_AFCLDTCC = {[25'h1f0_0034:25'h1f0_0037]}; + bins INTPLL_AFCFBTCC = {[25'h1f0_0038:25'h1f0_003B]}; + bins INTPLL_DIVCFG = {[25'h1f0_003C:25'h1f0_003F]}; + bins INTPLL_TCLKCFG = {[25'h1f0_0040:25'h1f0_0043]}; + bins INTPLL_DCLKSEL = {[25'h1f0_0044:25'h1f0_0047]}; + bins INTPLL_STATUS = {[25'h1f0_0048:25'h1f0_004B]}; + bins INTPLL_SYNCFG = {[25'h1f0_004C:25'h1f0_004F]}; + bins INTPLL_UPDATE = {[25'h1f0_0050:25'h1f0_0053]}; + bins INTPLL_CLKRXPD = {[25'h1f0_0054:25'h1f0_0057]}; +} + option.per_instance = 1; + endgroup + + + function new(); + SYSAddr = new(); + INSTRAddr = new(); + DATAAddr = new(); + CTRAddr = new(); + ENVELOPEIDAddr = new(); + ENVELOPEDATAAddr = new(); + DACAddr = new(); + MCUAddr = new(); + DBGAddr = new(); + PLLAddr = new(); + endfunction + extern task do_drive(); + extern task make_pkt(spi_trans tr); + +endclass : spi_driver + +task spi_driver::do_drive(); + + $display("pkt_num:\t%0d",pktnum); + + while(!vif.rstn) begin + vif.csn = 1'b1; + vif.sclk = 1'b1; + @(posedge vif.clk); + end + +while(pktnum>0) begin + m_trans = new(); + + if(!m_trans.randomize() with { + cmd==my_cmd; + (cmd==1'b0 || data.size()==last_size); + (cmd==1'b0 || addr==last_addr); +// addr[24:20] == 5'h0 || //sys +// addr[24:20] == 5'h1 || //instruction srams +// addr[24:20] == 5'h2 || //data srams +// addr[24:20] == 5'h3 || //awg +// addr[24:20] == 5'h4 || //envelope id srams +// addr[24:20] == 5'h5 || //envelope data srams +// addr[24:20] == 5'h6 || //dac +// addr[24:20] == 5'h7 || //mcu +// addr[24:20] == 5'h19 || //dbg srams +// addr[24:20] == 5'h1F ; //pll + addr[24: 20] == 5'h6; + addr[1:0] == 0; +// data.size == 2; + interval == 50; + }) + $fatal(0,"Randomize Failed"); + if(m_trans.cmd == 1'b0) begin + last_addr = m_trans.addr; + last_size = m_trans.data.size(); + end + my_cmd = ~my_cmd; + //Autarchy: Testcase force to assign some params + interval = m_trans.interval; + if(!autarchy) begin + half_sclk = m_trans.half_sclk; + end + if((m_trans.addr <= 25'h000_001F) && + ((m_trans.addr + (m_trans.data.size()-1) * 4) >= 25'h000_001C)) + m_trans.data[(25'h000_001C - m_trans.addr)/4] = + m_trans.data[(25'h000_001C - m_trans.addr)/4] % 4 + 1; + + + + make_pkt(m_trans); + + // $display(m_trans.addr); + + SYSAddr.sample(); + INSTRAddr.sample(); + DATAAddr.sample(); + CTRAddr.sample(); + ENVELOPEIDAddr.sample(); + ENVELOPEDATAAddr.sample(); + DACAddr.sample(); + MCUAddr.sample(); + DBGAddr.sample(); + PLLAddr.sample(); + + repeat(interval) + @(posedge vif.clk); + + pktnum--; + end + + + $finish(0); + //$display(SYSAddr.get_inst_coverage()); + //$display(MCUAddr.get_inst_coverage()); + //$display(AWGAddr.get_inst_coverage()); + +endtask : do_drive + + +task spi_driver::make_pkt(spi_trans tr); + int i=0,j=0; + int cs_time,mo_time; + + //*****************initialize chip_select and input_clk******************// + vif.csn <= 1'b1; + vif.sclk <= 1'b1; + vif.mosi <= stream[0]; + vif.cfgid <= tr.cfgid; + @(posedge vif.clk); + vif.csn <= 1'b0; + vif.sclk <= 1'b1; + + //unpack into bitstream + stream.delete(); + tr.unpack(stream); + + //mosi valid time: time for bitstream to be all sent + //csn valid_time: maybe a delay after or ahead of mosi_finished + mo_time = (stream.size()+1)*2*half_sclk; + cs_time = (pktnum==1) ? (mo_time + error_time%mo_time) : mo_time; + + //$display("***************************ONE PKT DRIVERED***************************"); + //$display("half_sclk:\t%0d\t\t\t\t\t\t **",half_sclk); + //$display("interval:\t%0d\t\t\t\t\t\t **",interval); + //$display("error_time:\t%0d\t\t\t\t\t\t **",error_time); + //$display("data_size:\t%0d\t\t\t\t\t\t **",tr.data.size()); + //$display("cmd:\t\t%0d\t\t\t\t\t\t **",tr.cmd); + //$display("id:\t\t%h\t\t\t\t\t\t **",tr.cfgid); + //$display("addr:\t\t%h\t\t\t\t\t\t **",tr.addr); + //$display(stream); + //if(!tr.cmd) + //for(i=0;i= 1; + data.size() <= 16;//not solid + interval <= 1000; + interval >= 0; + half_sclk <= 32; + half_sclk >= 4; + //Select system_regfile + (addr >= 25'h000_0000 && + //addr <= 25'h000_001F && + int'(addr) <= int'(25'h000_0023) - int'(data.size()*4) || + addr >= 25'h000_0028 && + //addr <= 25'h000_0037 && + int'(addr) <= int'(25'h000_003B) - int'(data.size()*4) && + addr != 25'h000_0020 && + addr != 25'h000_0024) || + (addr == 25'h000_0040) || + //Select instruction SRAMs 8192X32bit 32KB + (addr >= 25'h010_0000 && + //addr <= 25'h010_7FFF && + int'(addr) <= 25'h010_8003 - data.size()*4) || + //Select data SRAMs 8192X32bit 32KB + (addr >= 25'h020_0000 && + //addr <= 25'h020_7FFF && + int'(addr) <= 25'h020_8003 - data.size()*4) || + //Select awg_regfile + (addr >= 25'h030_0000 && + //addr <= 25'h030_001F && + int'(addr) <= int'(25'h030_0023) - int'(data.size()*4)) || + (addr >= 25'h030_0098 && + //addr <= 25'h030_00A3 && + int'(addr) <= int'(25'h030_00A7) - int'(data.size()*4)) || + (addr >= 25'h030_0100 && + //addr <= 25'h030_0123 && + int'(addr) <= int'(25'h030_0127) - int'(data.size()*4)) || + (addr >= 25'h030_0128 && + //addr <= 25'h030_0137 && + int'(addr) <= int'(25'h030_013B) - int'(data.size()*4)) || + //Select envelope ID SRAMs 64X32bit 256B + (addr >= 25'h040_0000 && + //addr <= 25'h040_00FF && + int'(addr) <= 25'h040_0103 - data.size()*4) || + //Select envelope data SRAMs 8192X32bit 32KB + (addr >= 25'h050_0000 && + //addr <= 25'h050_7FFF && + int'(addr) <= 25'h050_8003 - data.size()*4) || + //Select dac_regfile + (addr >= 25'h060_0000 && + //addr <= 25'h060_0073 && + int'(addr) <= int'(25'h060_0077) - int'(data.size()*4)) || + //Select mcu_regfile + (addr >= 25'h070_0000 && + //addr <= 25'h070_01F && + int'(addr) <= int'(25'h070_0023) - int'(data.size()*4)) || + (addr >= 25'h070_0040 && + //addr <= 25'h070_00A7 && + int'(addr) <= int'(25'h070_00AB) - int'(data.size()*4)) || + //Select DBG SRAMs 256X128bit 4KB + (addr >= 25'h190_0000 && + //addr <= 25'h190_0FFF && + int'(addr) <= 25'h190_1003 - data.size()*4) || + //Select intpll_regfile + (addr >= 25'h1f0_0000 && + //addr <= 25'h1f0_0057 && + int'(addr) <= int'(25'h1f0_005B) - int'(data.size()*4)) ; + } + + function new(); + endfunction + + extern function bit compare(spi_trans rhs_); + extern function void print(integer fid); + extern function void unpack(ref bit stream[$]); + extern function void pack(bit stream[$]); + +endclass : spi_trans + + + +function bit spi_trans::compare(spi_trans rhs_); + bit result=1'b1; + int i=0; + + result = ((cmd == rhs_.cmd) && + (addr == rhs_.addr) && + (cfgid == rhs_.cfgid)); + + if(this.data.size() != rhs_.data.size()) begin + $display("data_sizes are different"); + result = 1'b0; + end + else + for(i=0;i0)begin + for(i=0;i<32;i++) + data_temp[31-i] = stream.pop_front(); + data.push_back(data_temp); + end +endfunction diff --git a/rtl/awg/awg_ctrl.v b/rtl/awg/awg_ctrl.v new file mode 100644 index 0000000..6c152e8 --- /dev/null +++ b/rtl/awg/awg_ctrl.v @@ -0,0 +1,281 @@ +//+FHDR-------------------------------------------------------------------------------------------------------- +// Company: +//----------------------------------------------------------------------------------------------------------------- +// File Name : awg_ctrl.v +// Department : +// Author : PWY +// Author's Tel : +//----------------------------------------------------------------------------------------------------------------- +// Relese History +// Version Date Author Description +// 0.1 2024-03-13 PWY Envelope readout, modulation NCO control, and interpolator selection +//----------------------------------------------------------------------------------------------------------------- +// Keywords : +// +//----------------------------------------------------------------------------------------------------------------- +// Parameter +// +//----------------------------------------------------------------------------------------------------------------- +// Purpose : +// +//----------------------------------------------------------------------------------------------------------------- +// Target Device: +// Tool versions: +//----------------------------------------------------------------------------------------------------------------- +// Reuse Issues +// Reset Strategy: +// Clock Domains: +// Critical Timing: +// Asynchronous I/F: +// Synthesizable (y/n): +// Other: +//-FHDR-------------------------------------------------------------------------------------------------------- + + +/////////////////////////////////////////////////////////////////////////////////////////////////////// +//Key timing diagram +/////////////////////////////////////////////////////////////////////////////////////////////////////// +// ------------------------------------- +// | | +//wave_hold_i - ----------------------- +// ------------------------------------- +// | | +//wave_hold --------- --------------- +// ------------------------------------- +// | | +//wave_hold_r1 -------------- ----------- +// ------------------------------------- +// | | +//wave_hold_2 ------------------ -------- +// ---- ---- +// | | | | +//ilde2read ---- -------------------------------- --------------- +// ---- +// | | +//read2idle --------------------------------- --------------------- +// --------------------------------------------------------------- +//state_c | idle | read | idle | read +// --------------------------------------------------------------- +// --------------------------------------------------------------- +//state_n | idle | read | idle | read +// --------------------------------------------------------------- +// --------------------------------------------------------------- +//enve_rddata_i | invalid | valid | idle | valid +// --------------------------------------------------------------- +// ---- +// | | +//end_cnt_r ------------------------------------ --------------------- +// --------------------------------------------------------------- +//last_rddata | invalid | enve_rddata_i +// --------------------------------------------------------------- +// --------------------------------------------------------------- +//enve_data_w | invalid | enve_rddata_i | last_rddata | +// --------------------------------------------------------------- +// ------------------------- ---------- +// | | | +//enve_vld_w ---------------- ----------- +// ------------------------------------------ +// | +//enve_vld_o ---------------- + +//After two cycles of a valid signal(enve_index_vld_i), output the envelope data(enve_idata_o & enve_qdata_o & enve_vld_o) + +module awg_ctrl ( + //system port + input clk // System Main Clock + ,input rst_n // Spi Reset active low + //Envelope index Information + ,input enve_index_vld_i + ,input [15 :0] enve_start_addr_i + ,input [15 :0] enve_len_i + ,input wave_hold_i + //Envelope memory read signals + ,output enve_rden_o + ,output [15 :0] enve_rdaddr_o + ,input [31 :0] enve_rddata_i + //Envelope outpiut + ,output [15 :0] enve_idata_o + ,output [15 :0] enve_qdata_o + ,output [0 :0] enve_vld_o + //Envelope read fsm status + ,output [0 :0] enve_read_fsm_st_o + //Process conflict + ,output proc_cft_o + //modulation NCO control signals + //Data from the lookup table + ,input [31:0] muc_mod_nco_fcw_i + ,input [15:0] muc_mod_nco_pha_i + ,input [15:0] muc_mod_nco_rz_pha_i + ,input muc_mod_pha_clr_i + //Modulating nCO control signal output + ,output [31:0] mod_nco_fcw_o + ,output [15:0] mod_nco_pha_o + ,output mod_pha_clr_o + //Other parameters register + ,input [15:0] muc_mod_amp_i + ,input [15:0] muc_z_bais_i + ,output [15:0] mod_amp_o + ,output [15:0] z_bais_o + +); + + +localparam IDLE = 1'b0, + READ = 1'b1; + + + +wire [0:0] state_c; +wire [0:0] state_n; +wire ilde2read; +wire read2idle; + +////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +//Envelope readout +////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +// ------------------------------------------------------ +// -- read envelope memory count +// ------------------------------------------------------ +wire [15:0] enve_len; +wire [15:0] cnt_c; + +wire add_cnt = (state_c == READ ); + +wire end_cnt = add_cnt & (cnt_c == enve_len-1); + +wire [15:0] cnt_n = end_cnt ? 32'h0 : + add_cnt ? cnt_c + 1'b1 : + cnt_c ; + + +sirv_gnrl_dffr #(16) cnt_c_dffr (cnt_n, cnt_c, clk, rst_n); +//The first section of the state machine +//state_c +sirv_gnrl_dffr #(1) state_c_dffr (state_n, state_c, clk, rst_n); + +////////////////////////////////////////////////////////////// +//fsm +////////////////////////////////////////////////////////////// + +//state_n +assign state_n = ((state_c == IDLE ) && ilde2read ) ? READ : + ((state_c == READ ) && read2idle ) ? IDLE : + state_c ; + +//Generating jump conditions for state machines +assign ilde2read = (state_c == IDLE ) && enve_index_vld_i; +assign read2idle = (state_c == READ ) && end_cnt && ~enve_index_vld_i; + +///////////////////////////////////////////////////////////////////// +//Signal Latching +///////////////////////////////////////////////////////////////////// + +//enve_start_addr +wire [15:0] enve_start_addr; +//sirv_gnrl_dfflr #(16) enve_start_addr_dfflr (ilde2read, enve_start_addr_i, enve_start_addr, clk, rst_n); +sirv_gnrl_dfflr #(16) enve_start_addr_dfflr (enve_index_vld_i, enve_start_addr_i, enve_start_addr, clk, rst_n); +//enve_len + +//sirv_gnrl_dfflr #(16) enve_len_dfflr (ilde2read, enve_len_i, enve_len, clk, rst_n); +sirv_gnrl_dfflr #(16) enve_len_dfflr (enve_index_vld_i, enve_len_i, enve_len, clk, rst_n); + +//wave_hold +wire wave_hold; +//sirv_gnrl_dfflr #(1) wave_hold_dfflr (ilde2read, wave_hold_i, wave_hold, clk, rst_n); +sirv_gnrl_dfflr #(1) wave_hold_dfflr (enve_index_vld_i, wave_hold_i, wave_hold, clk, rst_n); +wire wave_hold_r1; +sirv_gnrl_dffr #(1) wave_hold_r1_dffr (wave_hold, wave_hold_r1, clk, rst_n); +wire wave_hold_r2; +sirv_gnrl_dffr #(1) wave_hold_r2_dffr (wave_hold_r1, wave_hold_r2, clk, rst_n); + + + + +// ------------------------------------------------------ +// -- Generate Read Envelope Storage Signal +// ------------------------------------------------------ + +assign enve_rden_o = (state_c == READ ); +assign enve_rdaddr_o = enve_start_addr + (cnt_c << 2); + +// ------------------------------------------------------ +// -- Receive envelope data +// ------------------------------------------------------ + +//Lock and store the last piece of data + +wire end_cnt_r; +sirv_gnrl_dffr #(1) end_cnt_r_dffr (end_cnt, end_cnt_r, clk, rst_n); + +wire [31:0] last_rddata; +sirv_gnrl_dfflr #(32) last_rddata_dfflr (end_cnt_r, enve_rddata_i[31 :0], last_rddata, clk, rst_n); + +//enve_vld_w +wire enve_vld_w = enve_rden_o | wave_hold_r1; +wire [1:0] enve_vld_r; + +//wire [31:0] enve_data_w = {32{enve_vld_r[0]}} & enve_rddata_i +// | {32{wave_hold_r2 }} & last_rddata ; + +//M--20240516 +wire [31:0] enve_data_w = enve_vld_r[0] ? enve_rddata_i : + wave_hold_r2 ? last_rddata : + 32'h0; + +sirv_gnrl_dffr #(2) enve_vld_r_dffr ({enve_vld_r[0],enve_vld_w}, enve_vld_r, clk, rst_n); +//enve_vld_o +assign enve_vld_o = enve_vld_r[1]; + +//enve_idata_o +sirv_gnrl_dffr #(16) enve_idata_o_dffr (enve_data_w[31:16], enve_idata_o, clk, rst_n); +//enve_qdata_o +sirv_gnrl_dffr #(16) enve_qdata_o_dffr (enve_data_w[15 :0], enve_qdata_o, clk, rst_n); + + +//Process conflict +wire proc_cft_w = (state_c == READ ) & enve_index_vld_i & ~end_cnt; +sirv_gnrl_dffr #(1) proc_cft_dffr (proc_cft_w, proc_cft_o, clk, rst_n); + +////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +//NCO control +////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +//--------------------------------------------------------------------------------------------- +//To ensure the stability of the NCO control signals throughout the entire readout process, +//the state machine locks the NCO control signals upon entering the readout state. +//--------------------------------------------------------------------------------------------- +wire [1:0] ilde2read_r; +sirv_gnrl_dffr #(2) ilde2read_r_dffr ({ilde2read_r[0],enve_index_vld_i}, ilde2read_r, clk, rst_n); +//---------------------------------------------------------- +//Modulation NCO frequency-controlled word processing +//---------------------------------------------------------- + +//Align the frequency-controlled word with the envelope output signal in timing +sirv_gnrl_dfflr #(32) mod_nco_fcw_o_dfflr (enve_index_vld_i, muc_mod_nco_fcw_i, mod_nco_fcw_o, clk, rst_n); + +//---------------------------------------------------------- +//Modulation NCO phase control word processing +//---------------------------------------------------------- + +//Align the phase control word with the envelope output signal in timing + +sirv_gnrl_dfflr #(16) mod_nco_pha_r_dfflr (enve_index_vld_i, muc_mod_nco_pha_i + muc_mod_nco_rz_pha_i, mod_nco_pha_o, clk, rst_n); + + +//---------------------------------------------------------- +//Modulating NCO phase clean signal processing +//---------------------------------------------------------- +assign mod_pha_clr_o = muc_mod_pha_clr_i; + +////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +//mod_amp_o & z_bais_o +////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + +//Align the mod_amp_o with the envelope output signal in timing +sirv_gnrl_dfflr #(16) mod_amp_o_dfflr (ilde2read_r[1], muc_mod_amp_i, mod_amp_o, clk, rst_n); + +//Align the z_bais_o with the envelope output signal in timing +sirv_gnrl_dfflr #(16) z_bais_o_dfflr (ilde2read_r[1], muc_z_bais_i, z_bais_o, clk, rst_n); + +//enve_read_fsm_st_o +assign enve_read_fsm_st_o = state_c; +endmodule \ No newline at end of file diff --git a/rtl/awg/awg_top.sv b/rtl/awg/awg_top.sv new file mode 100644 index 0000000..a7f7aff --- /dev/null +++ b/rtl/awg/awg_top.sv @@ -0,0 +1,430 @@ +//+FHDR-------------------------------------------------------------------------------------------------------- +// Company: +//----------------------------------------------------------------------------------------------------------------- +// File Name : awg_top.v +// Department : +// Author : PWY +// Author's Tel : +//----------------------------------------------------------------------------------------------------------------- +// Relese History +// Version Date Author Description +// 0.1 2024-03-13 PWY MCU dedicated register file +//----------------------------------------------------------------------------------------------------------------- +// Keywords : +// +//----------------------------------------------------------------------------------------------------------------- +// Parameter +// +//----------------------------------------------------------------------------------------------------------------- +// Purpose : +// +//----------------------------------------------------------------------------------------------------------------- +// Target Device: +// Tool versions: +//----------------------------------------------------------------------------------------------------------------- +// Reuse Issues +// Reset Strategy: +// Clock Domains: +// Critical Timing: +// Asynchronous I/F: +// Synthesizable (y/n): +// Other: +//-FHDR-------------------------------------------------------------------------------------------------------- + +module awg_top ( + //system port + input clk // System Main Clock + ,input rst_n // Spi Reset active low + //----------------------------from mcu----------------------------------------------------------- + //lookup table data + ,input [31 :0] mcu_cwfr [3:0] // Carrier frequency ctrl word 0~3 + ,input [15 :0] mcu_gapr [7:0] // Carrier phase ctrl word 0~7 + ,input [15 :0] mcu_ampr [3:0] // Amplitude 0~3 + ,input [15 :0] mcu_baisr [3:0] // Bais 0~3 + //CFG Port + ,input mcu_nco_pha_clr + ,input [15 :0] mcu_rz_pha + // The operands and info to peripheral + ,input send + ,input sendc + ,input [31 :0] codeword + ,input [1 :0] fb_st + //----------------------------from spi----------------------------------------------------------- + //Envelope storage read/write signal + ,input [31 :0] enve_bwrdata + ,input [0 :0] enve_bwren + ,input [14 :0] enve_brwaddr + ,input [0 :0] enve_brden + ,output [31 :0] enve_brddata + //envelope index lookup table read-write signal + ,input [31 :0] enve_id_bwrdata + ,input [0 :0] enve_id_bwren + ,input [7 :0] enve_id_brwaddr + ,input [0 :0] enve_id_brden + ,output [31 :0] enve_id_brddata + //----------------------------to ctrl regfile------------------------------------------------------ + //Envelope read fsm status + ,output [0 :0] enve_read_fsm_st + //Process conflict + ,output proc_cft + //----------------------------from ctrl regfile------------------------------------------------------ + ,input mod_sideband_sel //1'b0: Mod_data_i = Icoswd+Qsinwd, Mod_data_q = Isinwd+Qcoswd + //1'b1: Mod_data_i = Icoswd-Qsinwd, Mod_data_q = -Isinwd+Qcoswd + ,input mod_pha_sfot_clr + ,input [1 :0] role_sel //[0] --> 1'b0: xy-chip;1'b1: z-chip; + //[1] --> 1'b0: AC mode;1'b1: DC mode; + ,input mod_dout_sel //1'b0 --> mod modem data; 1'b1 --> mod nco data + //1'b1 --> awg output data always vaild; + //----------------------------to DSP---------------------------------------------------------------- + //Output awg data + ,output [15 :0] awg_data_i + ,output [15 :0] awg_data_q + ,output awg_vld + ,output bais_i_ov + ,output bais_q_ov + ); + +//------------------------------------------------------------------------------------------ +//codeword decode +//------------------------------------------------------------------------------------------ +wire wave_hold ; +wire [1 :0] bais_index ; +wire [1 :0] amp_index ; +wire [2 :0] nco_pha_index ; +wire [1 :0] nco_fcw_index ; +wire [7 :0] envelope_index ; +wire index_vld ; +codeword_decode U_codeword_decode ( + .clk ( clk ) + ,.rst_n ( rst_n ) + ,.send_i ( send ) + ,.sendc_i ( sendc ) + ,.codeword_i ( codeword ) + ,.fb_st_i ( fb_st ) + ,.wave_hold_o ( wave_hold ) + ,.bais_index_o ( bais_index ) + ,.amp_index_o ( amp_index ) + ,.nco_pha_index_o ( nco_pha_index ) + ,.nco_fcw_index_o ( nco_fcw_index ) + ,.envelope_index_o ( envelope_index ) + ,.index_vld_o ( index_vld ) +); + +//------------------------------------------------------------------------------------------ +//Carrier frequency ctrl word LUT +//------------------------------------------------------------------------------------------ +wire [31:0] mod_nco_fcw_i; +param_lut #( + .DXLEN ( 32 ) + ,.PNUM ( 4 ) + ) fcw_lut ( + .clk ( clk ) + ,.rst_n ( rst_n ) + ,.param_i ( mcu_cwfr ) + ,.index_i ( nco_fcw_index ) + ,.index_vld_i ( index_vld ) + ,.param_o ( mod_nco_fcw_i ) +); + +//------------------------------------------------------------------------------------------ +//Carrier phase ctrl word 0~7 +//------------------------------------------------------------------------------------------ +wire [15:0] mod_nco_pha_i; +param_lut #( + .DXLEN ( 16 ) + ,.PNUM ( 8 ) + ) pha_lut ( + .clk ( clk ) + ,.rst_n ( rst_n ) + ,.param_i ( mcu_gapr ) + ,.index_i ( nco_pha_index ) + ,.index_vld_i ( index_vld ) + ,.param_o ( mod_nco_pha_i ) +); + +//------------------------------------------------------------------------------------------ +// Amplitude 0~3 +//------------------------------------------------------------------------------------------ +wire [15:0] mod_amp_i; +param_lut #( + .DXLEN ( 16 ) + ,.PNUM ( 4 ) + ) ampr_lut ( + .clk ( clk ) + ,.rst_n ( rst_n ) + ,.param_i ( mcu_ampr ) + ,.index_i ( amp_index ) + ,.index_vld_i ( index_vld ) + ,.param_o ( mod_amp_i ) +); + +//------------------------------------------------------------------------------------------ +// Bais 0~3 +//------------------------------------------------------------------------------------------ +wire [15:0] z_bais_i; +param_lut #( + .DXLEN ( 16 ) + ,.PNUM ( 4 ) + ) bais_lut ( + .clk ( clk ) + ,.rst_n ( rst_n ) + ,.param_i ( mcu_baisr ) + ,.index_i ( bais_index ) + ,.index_vld_i ( index_vld ) + ,.param_o ( z_bais_i ) +); + +//------------------------------------------------------------------------------------------ +// enve_id_dpram +//------------------------------------------------------------------------------------------ + +wire enve_index_vld ; +sirv_gnrl_dffr #(1) enve_index_vld_dffr (index_vld, enve_index_vld, clk, rst_n); + +//Envelope LUT Clock +wire [0 :0] Enve_Id_PortClk = clk ; +//The envelope LUT A port is connected to the internal codeword decode +wire [7 :0] Enve_Id_PortAAddr = envelope_index << 2 ; //To align the address, the signal is left-shifted by 2 bits + //as the memory bytes are presented in byte addresses +wire [31 :0] Enve_Id_PortADataIn = 32'h0 ; +wire [0 :0] Enve_Id_PortAWriteEnable = 1'b1 ; +wire [0 :0] Enve_Id_PortAChipEnable = ~index_vld ; +wire [32/8-1:0] Enve_Id_PortAByteWriteEnable = 4'b0000 ; +wire [31 :0] Enve_Id_PortADataOut ; +wire [31 :0] enve_id_info = Enve_Id_PortADataOut ; +//The B port of the envelope LUT connects to an external SPI bus decode +wire [7 :0] Enve_Id_PortBAddr = enve_id_brwaddr ; +wire [31 :0] Enve_Id_PortBDataIn = enve_id_bwrdata ; +wire [0 :0] Enve_Id_PortBWriteEnable = ~enve_id_bwren & enve_id_brden ; +wire [0 :0] Enve_Id_PortBChipEnable = ~(enve_id_bwren | enve_id_brden) ; +wire [32/8-1:0] Enve_Id_PortBByteWriteEnable = 4'b0000 ; +wire [31 :0] Enve_Id_PortBDataOut ; +assign enve_id_brddata = Enve_Id_PortBDataOut ; + +wire [15 :0] enve_start_addr = enve_id_info[31:16]; +wire [15 :0] enve_len = enve_id_info[15:0 ]; + +dpram #( + .DATAWIDTH ( 32 ) + ,.ADDRWIDTH ( 8 ) + ) enve_id_dpram ( + .PortClk ( Enve_Id_PortClk ) + ,.PortAAddr ( Enve_Id_PortAAddr ) + ,.PortADataIn ( Enve_Id_PortADataIn ) + ,.PortAWriteEnable ( Enve_Id_PortAWriteEnable ) + ,.PortAChipEnable ( Enve_Id_PortAChipEnable ) + ,.PortAByteWriteEnable ( Enve_Id_PortAByteWriteEnable ) + ,.PortADataOut ( Enve_Id_PortADataOut ) + ,.PortBAddr ( Enve_Id_PortBAddr ) + ,.PortBDataIn ( Enve_Id_PortBDataIn ) + ,.PortBWriteEnable ( Enve_Id_PortBWriteEnable ) + ,.PortBChipEnable ( Enve_Id_PortBChipEnable ) + ,.PortBByteWriteEnable ( Enve_Id_PortBByteWriteEnable ) + ,.PortBDataOut ( Enve_Id_PortBDataOut ) +); + +//------------------------------------------------------------------------------------------ +// enve_id_dpram +//------------------------------------------------------------------------------------------ + +wire enve_arden ; +wire [15 :0] enve_ardaddr ; +wire [31 :0] enve_arddata ; +wire [15 :0] enve_idata ; +wire [15 :0] enve_qdata ; +wire [0 :0] enve_vld ; +wire [31 :0] mod_nco_fcw ; +wire [15 :0] mod_nco_pha ; +wire mod_pha_clr ; +wire [15 :0] mod_amp ; +wire [15 :0] z_bais ; + +awg_ctrl U_awg_ctrl ( + .clk ( clk ) + ,.rst_n ( rst_n ) + ,.enve_index_vld_i ( enve_index_vld ) + ,.enve_start_addr_i ( enve_start_addr ) + ,.enve_len_i ( enve_len ) + ,.wave_hold_i ( wave_hold ) + ,.enve_rden_o ( enve_arden ) + ,.enve_rdaddr_o ( enve_ardaddr ) + ,.enve_rddata_i ( enve_arddata ) + ,.enve_idata_o ( enve_idata ) + ,.enve_qdata_o ( enve_qdata ) + ,.enve_vld_o ( enve_vld ) + ,.enve_read_fsm_st_o ( enve_read_fsm_st ) + ,.proc_cft_o ( proc_cft ) + ,.muc_mod_nco_fcw_i ( mod_nco_fcw_i ) + ,.muc_mod_nco_pha_i ( mod_nco_pha_i ) + ,.muc_mod_nco_rz_pha_i ( mcu_rz_pha ) + ,.muc_mod_pha_clr_i ( mcu_nco_pha_clr ) + ,.muc_mod_amp_i ( mod_amp_i ) + ,.muc_z_bais_i ( z_bais_i ) + ,.mod_nco_fcw_o ( mod_nco_fcw ) + ,.mod_nco_pha_o ( mod_nco_pha ) + ,.mod_pha_clr_o ( mod_pha_clr ) + ,.mod_amp_o ( mod_amp ) + ,.z_bais_o ( z_bais ) +); + +//------------------------------------------------------------------------------------------ +// envelope dpram +//------------------------------------------------------------------------------------------ + +//Envelope Memory Clock +wire [0 :0] Enve_PortClk = clk ; +//The envelope storage A port is connected to the internal AWG controller +wire [14 :0] Enve_PortAAddr = enve_ardaddr[14:0] ; +wire [31 :0] Enve_PortADataIn = 32'h0 ; +wire [0 :0] Enve_PortAWriteEnable = 1'b1 ; +wire [0 :0] Enve_PortAChipEnable = ~enve_arden ; +wire [32/8-1:0] Enve_PortAByteWriteEnable = 4'b0000 ; +wire [31 :0] Enve_PortADataOut ; +assign enve_arddata = Enve_PortADataOut ; +//The B port of the envelope storage connects to an external SPI bus decode +wire [14 :0] Enve_PortBAddr = enve_brwaddr[14:0] ; +wire [31 :0] Enve_PortBDataIn = enve_bwrdata ; +wire [0 :0] Enve_PortBWriteEnable = ~enve_bwren & enve_brden ; +wire [0 :0] Enve_PortBChipEnable = ~(enve_bwren | enve_brden) ; +wire [32/8-1:0] Enve_PortBByteWriteEnable = 4'b0000 ; +wire [31 :0] Enve_PortBDataOut ; +assign enve_brddata = Enve_PortBDataOut ; + +dpram #( + .DATAWIDTH ( 32 ) + ,.ADDRWIDTH ( 15 ) + ) enve_dpram ( + .PortClk ( Enve_PortClk ) + ,.PortAAddr ( Enve_PortAAddr ) + ,.PortADataIn ( Enve_PortADataIn ) + ,.PortAWriteEnable ( Enve_PortAWriteEnable ) + ,.PortAChipEnable ( Enve_PortAChipEnable ) + ,.PortAByteWriteEnable ( Enve_PortAByteWriteEnable ) + ,.PortADataOut ( Enve_PortADataOut ) + ,.PortBAddr ( Enve_PortBAddr ) + ,.PortBDataIn ( Enve_PortBDataIn ) + ,.PortBWriteEnable ( Enve_PortBWriteEnable ) + ,.PortBChipEnable ( Enve_PortBChipEnable ) + ,.PortBByteWriteEnable ( Enve_PortBByteWriteEnable ) + ,.PortBDataOut ( Enve_PortBDataOut ) +); + +//------------------------------------------------------------------------------------------ +// mod nco +//------------------------------------------------------------------------------------------ +wire [15:0] mod_nco_sin; +wire [15:0] mod_nco_cos; + +NCO_CH1 U_mod_nco ( + .clk ( clk ) + ,.rstn ( rst_n ) + ,.phase_manual_clr ( mod_pha_clr ) + ,.phase_auto_clr ( mod_pha_sfot_clr ) + ,.fcw ( {mod_nco_fcw,16'h0} ) + ,.pha ( mod_nco_pha ) + ,.cos ( mod_nco_cos ) + ,.sin ( mod_nco_sin ) + ); + + //------------------------------------------------------------------------------------------ +// ampmod +//------------------------------------------------------------------------------------------ +//Config Signal +wire Amod_Enable = 1'b1; +wire [15 :0] Amod_Data_I ; +wire [15 :0] Amod_Data_Q ; +wire Amod_Vld ; + +ampmod U_ampmod ( + .Dig_Clk ( clk ) + ,.Dig_Resetn ( rst_n ) + ,.Mod_Data_I ( enve_idata ) + ,.Mod_Data_Q ( enve_qdata ) + ,.Mod_Vld ( enve_vld ) + ,.Amp ( mod_amp ) + ,.Amod_Enable ( Amod_Enable ) + ,.Amod_Data_I ( Amod_Data_I ) + ,.Amod_Data_Q ( Amod_Data_Q ) + ,.Amod_Vld ( Amod_Vld ) + ); + +//------------------------------------------------------------------------------------------ +// freqmod +//------------------------------------------------------------------------------------------ +wire [15:0] fmod_data_i ; +wire [15:0] fmod_data_q ; +wire fmod_vld ; + +wire mod_enable = ~(role_sel[1]); + +wire [15:0] data_i = {16{mod_enable}} & Amod_Data_I ; +wire [15:0] data_q = {16{mod_enable}} & Amod_Data_Q ; +wire vld = mod_enable & Amod_Vld ; + + + + + +freqmod U_freqmod ( + .Dig_Clk ( clk ) + ,.Dig_Resetn ( rst_n ) + ,.Env_Idata ( data_i ) + ,.Env_Qdata ( data_q ) + ,.Env_Vld ( vld ) + ,.Nco_Sin ( mod_nco_sin ) + ,.Nco_Cos ( mod_nco_cos ) + ,.Mod_Sideband_Sel ( mod_sideband_sel ) + ,.Mod_Enable ( mod_enable ) + ,.Mod_Data_I ( fmod_data_i ) + ,.Mod_Data_Q ( fmod_data_q ) + ,.Mod_Vld ( fmod_vld ) + ); + + + +//------------------------------------------------------------------------------------------ +// baisset +//------------------------------------------------------------------------------------------ +//Output modem data +wire [15:0] Bais_Data_I_i = mod_enable ? fmod_data_i : Amod_Data_I; +wire [15:0] Bais_Data_Q_i = mod_enable ? fmod_data_q : Amod_Data_Q; +wire Bais_Vld_i = mod_enable ? fmod_vld : Amod_Vld ; + +wire [15:0] Bais = z_bais ; +wire Bais_Enable = role_sel[0] ; + +wire [15:0] bais_data_i; +wire [15:0] bais_data_q; +wire [0 :0] bais_data_vld; + +baisset U_baisset ( + .Dig_Clk ( clk ) + ,.Dig_Resetn ( rst_n ) + ,.Bais_Data_I_i ( Bais_Data_I_i ) + ,.Bais_Data_Q_i ( Bais_Data_Q_i ) + ,.Bais_Vld_i ( Bais_Vld_i ) + ,.Bais ( Bais ) + ,.Bais_Enable ( Bais_Enable ) + ,.Bais_Data_I_o ( bais_data_i ) + ,.Bais_Data_Q_o ( bais_data_q ) + ,.Bais_Vld_o ( bais_data_vld ) + ,.Bais_I_Ov ( bais_i_ov ) + ,.Bais_Q_Ov ( bais_q_ov ) +); + + +modout_mux U_modout_mux ( + .clk ( clk ) + ,.rst_n ( rst_n ) + ,.sel ( mod_dout_sel ) + ,.sin ( mod_nco_sin ) + ,.cos ( mod_nco_cos ) + ,.mod_data_i ( bais_data_i ) + ,.mod_data_q ( bais_data_q ) + ,.mod_data_vld ( bais_data_vld ) + ,.mux_data_i ( awg_data_i ) + ,.mux_data_q ( awg_data_q ) + ,.mux_data_vld ( awg_vld ) +); + +endmodule \ No newline at end of file diff --git a/rtl/awg/codeword_decode.v b/rtl/awg/codeword_decode.v new file mode 100644 index 0000000..86c3507 --- /dev/null +++ b/rtl/awg/codeword_decode.v @@ -0,0 +1,112 @@ +//+FHDR-------------------------------------------------------------------------------------------------------- +// Company: +//----------------------------------------------------------------------------------------------------------------- +// File Name : codeword_decode.v +// Department : +// Author : PWY +// Author's Tel : +//----------------------------------------------------------------------------------------------------------------- +// Relese History +// Version Date Author Description +// 0.1 2024-03-13 PWY Analyze the code words sent by the MCU +//----------------------------------------------------------------------------------------------------------------- +// Keywords : +// +//----------------------------------------------------------------------------------------------------------------- +// Parameter +// +//----------------------------------------------------------------------------------------------------------------- +// Purpose : +// +//----------------------------------------------------------------------------------------------------------------- +// Target Device: +// Tool versions: +//----------------------------------------------------------------------------------------------------------------- +// Reuse Issues +// Reset Strategy: +// Clock Domains: +// Critical Timing: +// Asynchronous I/F: +// Synthesizable (y/n): +// Other: +//-FHDR-------------------------------------------------------------------------------------------------------- + + +module codeword_decode ( + //system port + input clk // System Main Clock + ,input rst_n // Spi Reset active low + //Extend instructions port + // The operands and info to peripheral + ,input send_i + ,input sendc_i + ,input [31 :0] codeword_i + ,input [1 :0] fb_st_i + //The output data remains as the last waveform value + ,output wave_hold_o + //Bais lookup table index + ,output [1 :0] bais_index_o + //Amplitude lookup table index + ,output [1 :0] amp_index_o + //Gate appended phase lookup table index + ,output [2 :0] nco_pha_index_o + //Carrier frequency lookup table index + ,output [1 :0] nco_fcw_index_o + //envelope lookup table index + ,output [7 :0] envelope_index_o + //Index valid + ,output index_vld_o +); + +//Sending waveforms according to feedback conditions +wire send_cond = sendc_i | codeword_i[20]; + +//The output data remains as the last waveform value +wire wave_hold_w = codeword_i[19]; + +//Bais lookup table index +wire [1 :0] bais_index_w = codeword_i[16:15]; + +//Amplitude lookup table index +wire [1 :0] amp_index_w = codeword_i[14:13]; + +//Gate appended phase lookup table index +wire [2 :0] nco_pha_index_w = codeword_i[12:10]; + +//Carrier frequency lookup table index +wire [1 :0] nco_fcw_index_w = codeword_i[9:8]; + +//envelope lookup table index +wire [7 :0] envelope_index_w = send_cond ? codeword_i[7:0] + fb_st_i : codeword_i[7:0]; + +//Valid Signal Generation +wire index_vld_w = send_i | sendc_i; + +///////////////////////////////////////////////////////// +//Output data register +///////////////////////////////////////////////////////// + +//wave_hold_o +sirv_gnrl_dfflr #(1) wave_hold_dfflr (index_vld_w, wave_hold_w, wave_hold_o, clk, rst_n); + +//bais_index_o +sirv_gnrl_dfflr #(2) bais_index_dfflr (index_vld_w, bais_index_w, bais_index_o, clk, rst_n); + +//amp_index_o +sirv_gnrl_dfflr #(2) amp_index_dfflr (index_vld_w, amp_index_w, amp_index_o, clk, rst_n); + +//nco_pha_index_o +sirv_gnrl_dfflr #(3) nco_pha_index_dfflr (index_vld_w, nco_pha_index_w, nco_pha_index_o, clk, rst_n); + +//nco_fcw_index_o +sirv_gnrl_dfflr #(2) nco_fcw_index_dfflr (index_vld_w, nco_fcw_index_w, nco_fcw_index_o, clk, rst_n); + +//envelope_index_o +sirv_gnrl_dfflr #(8) envelope_index_dfflr (index_vld_w, envelope_index_w, envelope_index_o, clk, rst_n); + +//index_vld_o +sirv_gnrl_dffr #(1) index_vld_dffr (index_vld_w ,index_vld_o, clk, rst_n); + + + +endmodule \ No newline at end of file diff --git a/rtl/awg/ctrl_regfile.v b/rtl/awg/ctrl_regfile.v new file mode 100644 index 0000000..37551dc --- /dev/null +++ b/rtl/awg/ctrl_regfile.v @@ -0,0 +1,593 @@ +//+FHDR-------------------------------------------------------------------------------------------------------- +// Company: +//----------------------------------------------------------------------------------------------------------------- +// File Name : ctrl_regfile.v +// Department : +// Author : PWY +// Author's Tel : +//----------------------------------------------------------------------------------------------------------------- +// Relese History +// Version Date Author Description +// 0.1 2024-03-13 PWY AWG dedicated register file +// 0.2 2024-05-13 PWY +//----------------------------------------------------------------------------------------------------------------- +// Keywords : +// +//----------------------------------------------------------------------------------------------------------------- +// Parameter +// +//----------------------------------------------------------------------------------------------------------------- +// Purpose : +// +//----------------------------------------------------------------------------------------------------------------- +// Target Device: +// Tool versions: +//----------------------------------------------------------------------------------------------------------------- +// Reuse Issues +// Reset Strategy: +// Clock Domains: +// Critical Timing: +// Asynchronous I/F: +// Synthesizable (y/n): +// Other: +//-FHDR-------------------------------------------------------------------------------------------------------- + +// ----------------------------------------------------------- +// -- Register address offset macros +// ----------------------------------------------------------- +//MCU parameter register 0 +`define MCUPARAR0 16'h00 +//MCU parameter register 1 +`define MCUPARAR1 16'h04 +//MCU parameter register 2 +`define MCUPARAR2 16'h08 +//MCU parameter register 3 +`define MCUPARAR3 16'h0C +//MCU result register 0 +`define MCURESR0 16'h10 +//MCU result register 1 +`define MCURESR1 16'h14 +//MCU result register 2 +`define MCURESR2 16'h18 +//MCU result register 3 +`define MCURESR3 16'h1C +//Run-time register +`define RTIMR 16'h98 +//Instruction count register +`define ICNTR 16'h9C +//Feedback state information register +`define FSIR 16'hA0 +//Modulator Operation Mode Register +`define MODMR 16'h100 +//Interpolator Operation Mode Register +`define INTPMR 16'h104 +//Frequency Mixer NCO Clear Register +`define MIXNCOCR 16'h108 +//Frequency Mixer NCO Frequency Control Word High 32-bit Register +`define MIXNFCWHR 16'h10C +//Frequency Mixer NCO Frequency Control Word Low 16-bit Register +`define MIXNFCWLR 16'h110 +//Frequency Mixer NCO Phase Control Word Register +`define MIXNPHAR 16'h114 +//Frequency Mixer Operating Mode Register +`define MIXMR 16'h118 +//Frequency Mixer Output Data Type Register +`define MIXODTR 16'h11C +//Frequency Mixer Output Data Format Register +`define MIXODFR 16'h120 +//Roler Selection Register +`define ROLER 16'h128 + +//Mixed-frequency NCO sync clear enable Register +`define MIXNCOSCER 16'h12C +//AWG data out type select Register +`define MODDOTR 16'h130 +//Status Register +`define STR 16'h134 + +//AWG always on Register +`define DSPAOR 16'h138 + +module ctrl_regfile ( + //system port + input clk // System Main Clock + ,input rst_n // Spi Reset active low + //rw op port + ,input [31 :0] wrdata // write data + ,input wren // write enable + ,input [15 :0] rwaddr // read & write address + ,input rden // read enable + ,output [31 :0] rddata // read data + ,input [1 :0] fb_st_i + ,input [31 :0] run_time + ,input [31 :0] instr_num + ,input bais_i_ov + ,input bais_q_ov + ,input awg_ctrl_fsm_st + //MCU and SPI interface for interaction + ,output [31 :0] mcu_param0 // MCU parameter 0 + ,output [31 :0] mcu_param1 // MCU parameter 1 + ,output [31 :0] mcu_param2 // MCU parameter 2 + ,output [31 :0] mcu_param3 // MCU parameter 3 + ,input [31 :0] mcu_result0 // MCU result 0 + ,input [31 :0] mcu_result1 // MCU result 1 + ,input [31 :0] mcu_result2 // MCU result 2 + ,input [31 :0] mcu_result3 // MCU result 3 + ,output [1 :0] fb_st_o + //awg cfg + ,output mod_sel_sideband //1'b0:Upper sideband;1'b1:Lower sideband; + //DSP cfg + ,output qam_nco_clr + ,output qam_nco_sclr_en + ,output [47 :0] qam_fcw//////////////////////////////////////////////////////////////////////////////////////////////////// + ,output [15 :0] qam_pha ////////////////////////////////////////////////////////////////////////////////////////////// + ,output [1 :0] qam_mod //2'b00:bypass;2'b01:mix; + //2'b10:cos;2'b11:sin; + ,output qam_sel_sideband //1'b0:Upper sideband;1'b1:Lower sideband; + ,output [2 :0] intp_mode //3'b000:x1;3'b001:x2;3'b010:x4; + //3'b011:x8;3'b100:x16; + ,output [1 :0] role_sel //[0] --> 1'b0: xy-chip;1'b1: z-chip; + //[1] --> 1'b0:AC mode;1'b1: DC mode; + //Please note that when the role is set to xy-chip, + //only AC mode is supported. + ,output [1 :0] dac_mode_sel //2'b00:NRZ mode;2'b01:MIX mode; + //2'b10:2xNRZ mode;2'b00:reserve; + ,output dout_sel //1'b0 --> mod modem data; 1'b1 --> mod nco data + //1'b0 --> Z dsp data for ZDAC; 1'b1 --> xy dsp data for ZDAC + ,output dsp_alwayson //1'b0 --> dsp output data vaild depend on awg vaild; + //1'b1 --> dsp output data always vaild; + +); + +localparam L = 1'b0, + H = 1'b1; + +// ------------------------------------------------------ +// -- Register enable (select) wires +// ------------------------------------------------------ +wire mcuparar0en ; // MCUPARAR0 select +wire mcuparar1en ; // MCUPARAR1 select +wire mcuparar2en ; // MCUPARAR2 select +wire mcuparar3en ; // MCUPARAR3 select +wire mcuresr0en ; // MCURESR0 select +wire mcuresr1en ; // MCURESR1 select +wire mcuresr2en ; // MCURESR2 select +wire mcuresr3en ; // MCURESR3 select +wire rtimren ; // RTIMR select +wire icntren ; // ICNTR select +wire fsiren ; // FSIR select +wire modmren ; // MODMR select +wire intpmren ; // INTPMR select +wire mixncocren ; // MIXNCOCR select +wire mixnfcwhren ; // MIXNFCWHR select +wire mixnfcwlren ; // MIXNFCWLR select +wire mixnpharen ; // MIXNPHAR select +wire mixmren ; // MIXMR select +wire mixodtren ; // MIXODTR select +wire mixodfren ; // MIXODFR select +wire roleren ; // ROLER select +wire mixncosceren ; // MIXNCOSCER select +wire stren ; // BAISOVR select +wire moddotren ; // MODDOTR select +wire dspaoren ; // DSPAOR select + + +// ------------------------------------------------------ +// -- Register write enable wires +// ------------------------------------------------------ +wire mcuparar0we ; // MCUPARAR0 write enable +wire mcuparar1we ; // MCUPARAR1 write enable +wire mcuparar2we ; // MCUPARAR2 write enable +wire mcuparar3we ; // MCUPARAR3 write enable +wire modmrwe ; // MODMR write enable +wire intpmrwe ; // INTPMR write enable +wire mixncocrwe ; // MIXNCOCR write enable +wire mixnfcwhrwe ; // MIXNFCWHR write enable +wire mixnfcwlrwe ; // MIXNFCWLR write enable +wire mixnpharwe ; // MIXNPHAR write enable +wire mixmrwe ; // MIXMR write enable +wire mixodtrwe ; // MIXODTR write enable +wire mixodfrwe ; // MIXODFR write enable +wire rolerwe ; // ROLER write enable +wire mixncoscerwe ; // MIXNCOSCER write enable +wire moddotrwe ; // MODDOTR write enable +wire dspaorwe ; // DSPAOR write enable +// ------------------------------------------------------ +// -- Misc wires +// ------------------------------------------------------ + +// ------------------------------------------------------ +// -- Misc Registers +// ------------------------------------------------------ + +wire [31 :0] mcuparar0 ; // MCUPARAR0 register +wire [31 :0] mcuparar1 ; // MCUPARAR1 register +wire [31 :0] mcuparar2 ; // MCUPARAR2 register +wire [31 :0] mcuparar3 ; // MCUPARAR3 register +wire [31 :0] mcuresr0 ; // MCURESR0 register +wire [31 :0] mcuresr1 ; // MCURESR1 register +wire [31 :0] mcuresr2 ; // MCURESR2 register +wire [31 :0] mcuresr3 ; // MCURESR3 register +wire [31 :0] rtimr ; // RTIMR register +wire [31 :0] icntr ; // ICNTR register +wire [1 :0] fsir ; // FSIR register +wire [0 :0] modmr ; // MODMR register +wire [2 :0] intpmr ; // INTPMR register +wire [0 :0] mixncocr ; // MIXNCOCR register +wire [31 :0] mixnfcwhr ; // MIXNFCWHR register +wire [15 :0] mixnfcwlr ; // MIXNFCWLR register +wire [15 :0] mixnphar ; // MIXNPHAR register +wire [0 :0] mixmr ; // MIXMR register +wire [1 :0] mixodtr ; // MIXODTR register +wire [1 :0] mixodfr ; // MIXODFR register +wire [1 :0] roler ; // ROLER register +wire [0 :0] dspaor ; // DSPAOR register + +wire [0 :0] mixncoscer ; // MIXNCOSCER register +wire moddotr ; // MODDOTR register + +reg [31: 0] rddata_reg ; + +// ------------------------------------------------------ +// -- Address decoder +// +// Decodes the register address offset input(reg_addr) +// to produce enable (select) signals for each of the +// SW-registers in the macrocell. The reg_addr input +// is bits [15:0] of the paddr bus. +// ------------------------------------------------------ +assign mcuparar0en = (rwaddr[15:2] == `MCUPARAR0 >> 2) ? 1'b1 : 1'b0; +assign mcuparar1en = (rwaddr[15:2] == `MCUPARAR1 >> 2) ? 1'b1 : 1'b0; +assign mcuparar2en = (rwaddr[15:2] == `MCUPARAR2 >> 2) ? 1'b1 : 1'b0; +assign mcuparar3en = (rwaddr[15:2] == `MCUPARAR3 >> 2) ? 1'b1 : 1'b0; +assign mcuresr0en = (rwaddr[15:2] == `MCURESR0 >> 2) ? 1'b1 : 1'b0; +assign mcuresr1en = (rwaddr[15:2] == `MCURESR1 >> 2) ? 1'b1 : 1'b0; +assign mcuresr2en = (rwaddr[15:2] == `MCURESR2 >> 2) ? 1'b1 : 1'b0; +assign mcuresr3en = (rwaddr[15:2] == `MCURESR3 >> 2) ? 1'b1 : 1'b0; +assign rtimren = (rwaddr[15:2] == `RTIMR >> 2) ? 1'b1 : 1'b0; +assign icntren = (rwaddr[15:2] == `ICNTR >> 2) ? 1'b1 : 1'b0; +assign fsiren = (rwaddr[15:2] == `FSIR >> 2) ? 1'b1 : 1'b0; +assign modmren = (rwaddr[15:2] == `MODMR >> 2) ? 1'b1 : 1'b0; +assign intpmren = (rwaddr[15:2] == `INTPMR >> 2) ? 1'b1 : 1'b0; +assign mixncocren = (rwaddr[15:2] == `MIXNCOCR >> 2) ? 1'b1 : 1'b0; +assign mixnfcwhren = (rwaddr[15:2] == `MIXNFCWHR >> 2) ? 1'b1 : 1'b0; +assign mixnfcwlren = (rwaddr[15:2] == `MIXNFCWLR >> 2) ? 1'b1 : 1'b0; +assign mixnpharen = (rwaddr[15:2] == `MIXNPHAR >> 2) ? 1'b1 : 1'b0; +assign mixmren = (rwaddr[15:2] == `MIXMR >> 2) ? 1'b1 : 1'b0; +assign mixodtren = (rwaddr[15:2] == `MIXODTR >> 2) ? 1'b1 : 1'b0; +assign mixodfren = (rwaddr[15:2] == `MIXODFR >> 2) ? 1'b1 : 1'b0; +assign roleren = (rwaddr[15:2] == `ROLER >> 2) ? 1'b1 : 1'b0; +assign mixncosceren = (rwaddr[15:2] == `MIXNCOSCER >> 2) ? 1'b1 : 1'b0; +assign stren = (rwaddr[15:2] == `STR >> 2) ? 1'b1 : 1'b0; +assign moddotren = (rwaddr[15:2] == `MODDOTR >> 2) ? 1'b1 : 1'b0; +assign dspaoren = (rwaddr[15:2] == `DSPAOR >> 2) ? 1'b1 : 1'b0; + +// ------------------------------------------------------ +// -- Write enable signals +// +// Write enable signals for writable SW-registers. +// The write enable for each register is the ANDed +// result of the register enable and the input reg_wren +// ------------------------------------------------------ +assign mcuparar0we = mcuparar0en & wren; +assign mcuparar1we = mcuparar1en & wren; +assign mcuparar2we = mcuparar2en & wren; +assign mcuparar3we = mcuparar3en & wren; +assign modmrwe = modmren & wren;/////////// +assign intpmrwe = intpmren & wren; +assign mixncocrwe = mixncocren & wren; +assign mixnfcwhrwe = mixnfcwhren & wren; +assign mixnfcwlrwe = mixnfcwlren & wren; +assign mixnpharwe = mixnpharen & wren; +assign mixmrwe = mixmren & wren; +assign mixodtrwe = mixodtren & wren; +assign mixodfrwe = mixodfren & wren; +assign rolerwe = roleren & wren; +assign mixncoscerwe = mixncosceren & wren; +assign moddotrwe = moddotren & wren; +assign dspaorwe = dspaoren & wren; +// ------------------------------------------------------ +// -- mcuparar0 register +// +// Write mcuparar0 for 'MCUPARAR0' : 32-bit register +// Register is split into the following bit fields +// +// [31:0] --> mcuparar0 +// ------------------------------------------------------ +sirv_gnrl_dfflr #(32) mcuparar0_dfflr (mcuparar0we, wrdata[31:0], mcuparar0, clk, rst_n); + +// ------------------------------------------------------ +// -- mcuparar1 register +// +// Write mcuparar1 for 'MCUPARAR1' : 32-bit register +// Register is split into the following bit fields +// +// [31:0] --> mcuparar1 +// ------------------------------------------------------ +sirv_gnrl_dfflr #(32) mcuparar1_dfflr (mcuparar1we, wrdata[31:0], mcuparar1, clk, rst_n); + +// ------------------------------------------------------ +// -- mcuparar2 register +// +// Write mcuparar2 for 'MCUPARAR2' : 32-bit register +// Register is split into the following bit fields +// +// [31:0] --> mcuparar2 +// ------------------------------------------------------ +sirv_gnrl_dfflr #(32) mcuparar2_dfflr (mcuparar2we, wrdata[31:0], mcuparar2, clk, rst_n); + +// ------------------------------------------------------ +// -- mcuparar3 register +// +// Write mcuparar3 for 'MCUPARAR3' : 32-bit register +// Register is split into the following bit fields +// +// [31:0] --> mcuparar3 +// ------------------------------------------------------ +sirv_gnrl_dfflr #(32) mcuparar3_dfflr (mcuparar3we, wrdata[31:0], mcuparar3, clk, rst_n); + +// ------------------------------------------------------ +// -- modmr register +// +// Write modmr for 'MODMR' : 32-bit register +// Register is split into the following bit fields +// +// [0] --> modmr +// ------------------------------------------------------ +sirv_gnrl_dfflr #(1) modmr_dfflr (modmrwe, wrdata[0], modmr, clk, rst_n); + +// ------------------------------------------------------ +// -- intpmr register +// +// Write intpmr for 'INTPMR' : 32-bit register +// Register is split into the following bit fields +// +// [2:0] --> intpmr +// ------------------------------------------------------ +sirv_gnrl_dfflr #(3) intpmr_dfflr (intpmrwe, wrdata[2:0], intpmr, clk, rst_n); + +// ------------------------------------------------------ +// -- mixncocr register +// +// Write mixncocr for 'MIXNCOCR' : 32-bit register +// Register is split into the following bit fields +// +// [0] --> mixncocr +// ------------------------------------------------------ +sirv_gnrl_dfflr #(1) mixncocr_dfflr (mixncocrwe, wrdata[0], mixncocr, clk, rst_n); + +// ------------------------------------------------------ +// -- mixnfcwhr register +// +// Write mixnfcwhr for 'MIXNFCWHR' : 32-bit register +// Register is split into the following bit fields +// +// [31:0] --> mixnfcwhr +// ------------------------------------------------------ +sirv_gnrl_dfflr #(32) mixnfcwhr_dfflr (mixnfcwhrwe, wrdata[31:0], mixnfcwhr, clk, rst_n); + +// ------------------------------------------------------ +// -- mixnfcwlr register +// +// Write mixnfcwlr for 'MIXNFCWHR' : 32-bit register +// Register is split into the following bit fields +// +// [31:16] --> mixnfcwlr +// ------------------------------------------------------ +sirv_gnrl_dfflr #(16) mixnfcwlr_dfflr (mixnfcwlrwe, wrdata[31:16], mixnfcwlr, clk, rst_n); + +// ------------------------------------------------------ +// -- mixnphar register +// +// Write mixnphar for 'MIXNPHAR' : 32-bit register +// Register is split into the following bit fields +// +// [31:16] --> mixnphar +// ------------------------------------------------------ +sirv_gnrl_dfflr #(16) mixnphar_dfflr (mixnpharwe, wrdata[31:16], mixnphar, clk, rst_n); + +// ------------------------------------------------------ +// -- mixmr register +// +// Write mixmr for 'MIXNPHAR' : 32-bit register +// Register is split into the following bit fields +// +// [0] --> mixmr +// ------------------------------------------------------ +sirv_gnrl_dfflr #(1) mixmr_dfflr (mixmrwe, wrdata[0], mixmr, clk, rst_n); + +// ------------------------------------------------------ +// -- mixodtr register +// +// Write mixodtr for 'MIXNPHAR' : 32-bit register +// Register is split into the following bit fields +// +// [1:0] --> mixodtr +// ------------------------------------------------------ +sirv_gnrl_dfflr #(2) mixodtr_dfflr (mixodtrwe, wrdata[1:0], mixodtr, clk, rst_n); + +// ------------------------------------------------------ +// -- mixodfr register +// +// Write mixodfr for 'MIXODFR' : 32-bit register +// Register is split into the following bit fields +// +// [1:0] --> mixodfr +// ------------------------------------------------------ +sirv_gnrl_dfflr #(2) mixodfr_dfflr (mixodfrwe, wrdata[1:0], mixodfr, clk, rst_n); + +// ------------------------------------------------------ +// -- roler register +// +// Write roler for 'ROLER' : 32-bit register +// Register is split into the following bit fields +// +// [1] --> AC or DC mode select +// [0] --> xy-chip or z-chip select +// ------------------------------------------------------ +sirv_gnrl_dfflr #(1) roler0_dfflr (rolerwe, wrdata[0], roler[0], clk, rst_n); + +//Please note that when the role is set to xy-chip, only AC mode is supported. +wire mode_w = wrdata[0] & wrdata[1]; +// 0 | 0 | x +// 0 | 1 | 0 +// 1 | 1 | 1 + +sirv_gnrl_dfflr #(1) roler1_dfflr (rolerwe, mode_w, roler[1], clk, rst_n); + +// ------------------------------------------------------ +// -- mixncoscer register +// +// Write mixncoscer for 'mixncoscer' : 32-bit register +// Register is split into the following bit fields +// +// [0] --> mixncoscer +// ------------------------------------------------------ +sirv_gnrl_dfflr #(1) mixncoscer_dfflr (mixncoscerwe, wrdata[0], mixncoscer, clk, rst_n); + + +// ------------------------------------------------------ +// -- moddotr register +// +// Write moddotr for 'moddotr' : 32-bit register +// Register is split into the following bit fields +// +// [0] --> moddotr +// ------------------------------------------------------ +sirv_gnrl_dfflr #(1) moddotr_dfflr (moddotrwe, wrdata[0], moddotr, clk, rst_n); + + +// ------------------------------------------------------ +// -- dspaor register +// +// Write dspaor for 'dspaor' : 32-bit register +// Register is split into the following bit fields +// +// [0] --> dspaor +// ------------------------------------------------------ +sirv_gnrl_dfflrs #(1) dspaor_dfflrs (dspaorwe, wrdata[0], dspaor, clk, rst_n); + + + +// ------------------------------------------------------ +// -- mcuresr0 +// ------------------------------------------------------ +sirv_gnrl_dffr #(32) mcuparar0_dffr (mcu_result0, mcuresr0, clk, rst_n); +// ------------------------------------------------------ +// -- mcuresr1 +// ------------------------------------------------------ +sirv_gnrl_dffr #(32) mcuparar1_dffr (mcu_result1, mcuresr1, clk, rst_n); +// ------------------------------------------------------ +// -- mcuresr2 +// ------------------------------------------------------ +sirv_gnrl_dffr #(32) mcuparar2_dffr (mcu_result2, mcuresr2, clk, rst_n); +// ------------------------------------------------------ +// -- mcuresr3 +// ------------------------------------------------------ +sirv_gnrl_dffr #(32) mcuparar3_dffr (mcu_result3, mcuresr3, clk, rst_n); + +// ------------------------------------------------------ +// -- rtimr +// ------------------------------------------------------ +sirv_gnrl_dffr #(32) rtimr_dffr (run_time, rtimr, clk, rst_n); + +// ------------------------------------------------------ +// -- icntr +// ------------------------------------------------------ +sirv_gnrl_dffr #(32) icntr_dffr (instr_num, icntr, clk, rst_n); + +// ------------------------------------------------------ +// -- fsir +// ------------------------------------------------------ +sirv_gnrl_dffr #(2) fsir_dffr (fb_st_i[1:0], fsir, clk, rst_n);//////////////////////////////////////////////////////////[1:0] + +// ------------------------------------------------------ +// -- Read data mux +// +// -- The data from the selected register is +// -- placed on a zero-padded 32-bit read data bus. +// ------------------------------------------------------ +always @(*) begin : RDDATA_PROC + rddata_reg = {32{1'b0}}; + if(mcuparar0en == H ) rddata_reg[31:0] = mcuparar0 ; + if(mcuparar1en == H ) rddata_reg[31:0] = mcuparar1 ; + if(mcuparar2en == H ) rddata_reg[31:0] = mcuparar2 ; + if(mcuparar3en == H ) rddata_reg[31:0] = mcuparar3 ; + if(mcuresr0en == H ) rddata_reg[31:0] = mcuresr0 ; + if(mcuresr1en == H ) rddata_reg[31:0] = mcuresr1 ; + if(mcuresr2en == H ) rddata_reg[31:0] = mcuresr2 ; + if(mcuresr3en == H ) rddata_reg[31:0] = mcuresr3 ; + if(rtimren == H ) rddata_reg[31:0] = rtimr ; + if(icntren == H ) rddata_reg[31:0] = icntr ; + if(fsiren == H ) rddata_reg[1 :0] = fsir ; + if(modmren == H ) rddata_reg[0 :0] = modmr ; + if(intpmren == H ) rddata_reg[2 :0] = intpmr ; + if(roleren == H ) rddata_reg[1 :0] = roler ; + if(mixncocren == H ) rddata_reg[0 :0] = mixncocr ; + if(mixnfcwhren == H ) rddata_reg[31:0] = mixnfcwhr ; + if(mixnfcwlren == H ) rddata_reg[15:0] = mixnfcwlr ; + if(mixnpharen == H ) rddata_reg[15:0] = mixnphar ; + if(mixmren == H ) rddata_reg[0 :0] = mixmr ; + if(mixodtren == H ) rddata_reg[1 :0] = mixodtr ; + if(mixodfren == H ) rddata_reg[1 :0] = mixodfr ; + if(mixncosceren == H ) rddata_reg[0 :0] = mixncoscer ; + if(moddotren == H ) rddata_reg[0 :0] = moddotr ; + if(stren == H ) rddata_reg[2 :0] = {bais_q_ov,bais_i_ov,awg_ctrl_fsm_st} ; + if(dspaoren == H ) rddata_reg[0 :0] = dspaor ; +end + +// ------------------------------------------------------ +// -- Output signals assignment +// ------------------------------------------------------ + +//mcu result +assign mcu_param0 = mcuparar0 ; +assign mcu_param1 = mcuparar1 ; +assign mcu_param2 = mcuparar2 ; +assign mcu_param3 = mcuparar3 ; + +//fb_st_o +assign fb_st_o = fsir ; +//awg cfg + assign mod_sel_sideband = modmr ; +//DSP cfg +assign qam_nco_clr = mixncocr ; +assign qam_fcw = {mixnfcwhr,mixnfcwlr} ; +assign qam_pha = mixnphar ; +assign qam_mod = mixodtr ; +assign qam_sel_sideband = mixmr ; +assign intp_mode = intpmr ; +assign dac_mode_sel = mixodfr ; +assign qam_nco_sclr_en = mixncoscer ; +assign role_sel = roler ; + +assign dout_sel = moddotr ; + +assign dsp_alwayson = dspaor ; +//rddata +sirv_gnrl_dffr #(32) rddata_dffr (rddata_reg, rddata, clk, rst_n); +endmodule + +`undef MCUPARAR0 +`undef MCUPARAR1 +`undef MCUPARAR2 +`undef MCUPARAR3 +`undef MCURESR0 +`undef MCURESR1 +`undef MCURESR2 +`undef MCURESR3 +`undef RTIMR +`undef ICNTR +`undef FSIR +`undef MODMR +`undef INTPMR +`undef MIXNCOCR +`undef MIXNFCWHR +`undef MIXNFCWLR +`undef MIXNPHAR +`undef MIXMR +`undef MIXODTR +`undef MIXODFR +`undef MIXNCOSCER +`undef MODDOTR +`undef STR diff --git a/rtl/awg/modout_mux.v b/rtl/awg/modout_mux.v new file mode 100644 index 0000000..67b7174 --- /dev/null +++ b/rtl/awg/modout_mux.v @@ -0,0 +1,66 @@ +//+FHDR-------------------------------------------------------------------------------------------------------- +// Company: +//----------------------------------------------------------------------------------------------------------------- +// File Name : modout_mux.v +// Department : +// Author : PWY +// Author's Tel : +//----------------------------------------------------------------------------------------------------------------- +// Relese History +// Version Date Author Description +// 0.1 2024-05-13 PWY debug top-level +//----------------------------------------------------------------------------------------------------------------- +// Keywords : +// +//----------------------------------------------------------------------------------------------------------------- +// Parameter +// +//----------------------------------------------------------------------------------------------------------------- +// Purpose : +// +//----------------------------------------------------------------------------------------------------------------- +// Target Device: +// Tool versions: +//----------------------------------------------------------------------------------------------------------------- +// Reuse Issues +// Reset Strategy: +// Clock Domains: +// Critical Timing: +// Asynchronous I/F: +// Synthesizable (y/n): +// Other: +//-FHDR-------------------------------------------------------------------------------------------------------- + +module modout_mux ( +//system port + input clk // System Main Clock + ,input rst_n // Spi Reset active low + //---------------from ctrl regfile------------------------------------ + ,input sel // 1'b0 --> mod modem data; 1'b1 --> mod nco data + //mod nco data + ,input [15:0] sin + ,input [15:0] cos + //mod modem data + ,input [15:0] mod_data_i + ,input [15:0] mod_data_q + ,input mod_data_vld + //mux out data + ,output [15:0] mux_data_i + ,output [15:0] mux_data_q + ,output mux_data_vld +); + +wire [15:0] mux_data_i_w = sel ? sin : mod_data_i; +wire [15:0] mux_data_q_w = sel ? cos : mod_data_q; +wire mux_data_vld_w = sel ? 1'b1 : mod_data_vld; + +`ifdef MODDOUT_MUX_REG +sirv_gnrl_dffr #(16) mux_data_i_dffr (mux_data_i_w , mux_data_i , clk, rst_n); +sirv_gnrl_dffr #(16) mux_data_q_dffr (mux_data_q_w , mux_data_q , clk, rst_n); +sirv_gnrl_dffr #(1 ) mux_data_vld_dffr (mux_data_vld_w, mux_data_vld, clk, rst_n); +`else +assign mux_data_i = mux_data_i_w ; +assign mux_data_q = mux_data_q_w ; +assign mux_data_vld = mux_data_vld_w ; +`endif +endmodule \ No newline at end of file diff --git a/rtl/awg/param_lut.sv b/rtl/awg/param_lut.sv new file mode 100644 index 0000000..19b92bb --- /dev/null +++ b/rtl/awg/param_lut.sv @@ -0,0 +1,84 @@ +//+FHDR-------------------------------------------------------------------------------------------------------- +// Company: +//----------------------------------------------------------------------------------------------------------------- +// File Name : awg_ctrl.v +// Department : +// Author : PWY +// Author's Tel : +//----------------------------------------------------------------------------------------------------------------- +// Relese History +// Version Date Author Description +// 0.1 2024-03-13 PWY Configuration parameters lookup tabl +//----------------------------------------------------------------------------------------------------------------- +// Keywords : +// +//----------------------------------------------------------------------------------------------------------------- +// Parameter +// +//----------------------------------------------------------------------------------------------------------------- +// Purpose : +// +//----------------------------------------------------------------------------------------------------------------- +// Target Device: +// Tool versions: +//----------------------------------------------------------------------------------------------------------------- +// Reuse Issues +// Reset Strategy: +// Clock Domains: +// Critical Timing: +// Asynchronous I/F: +// Synthesizable (y/n): +// Other: +//-FHDR-------------------------------------------------------------------------------------------------------- + + +module param_lut ( + clk + ,rst_n + ,param_i + ,index_i + ,index_vld_i + ,param_o +); + +//================================================= +function integer clog2(input integer depth); +begin + for(clog2=0;depth>1;clog2=clog2+1) + depth =depth>>1; +end +endfunction +//================================================= +parameter DXLEN = 32; +parameter PNUM = 4; +//================================================= + +//system port +input clk ; +input rst_n ; +input [DXLEN-1 :0] param_i [PNUM-1:0] ; +input [clog2(PNUM)-1 :0] index_i ; +input index_vld_i ; +output [DXLEN-1 :0] param_o ; + +generate + genvar i; + wire [PNUM-1 :0] cs_slv; + wire [DXLEN-1 :0] dtemp [PNUM-1:0]; + + for(i=0;i0 degree phase,bit[1]-->45 degree phase.....bit[7]-->315degree phae + ,output [0 :0] div_sync_en // Frequency Divider Synchronous Clear Enable + ,output sync_oe // SYNC signal output enable, hign active + ,output clkrx_pdn // Clock Rx Power down, Ative Low + ,input pll_lock // PLL LOCK +); + +localparam L = 1'b0, + H = 1'b1; + +// ------------------------------------------------------ +// -- Register enable (select) wires +// ------------------------------------------------------ +wire refctrlen ; +wire pcnten ; +wire pfdctrlen ; +wire spdctrlen ; +wire ptatctrlen ; +wire fllctrlen ; +wire selctrlen ; +wire vcoctrlen ; +wire vcofbadjen ; +wire afcctrlen ; +wire afccnten ; +wire afcldcnten ; +wire afcpresen ; +wire afcldtccen ; +wire afcfbtccen ; +wire divcfgen ; +wire tclkcfgen ; +wire dclkselen ; +wire statusen ; +wire synccfgen ; +wire updateen ; +wire clkrxpden ; + + +// ------------------------------------------------------ +// -- Register write enable wires +// ------------------------------------------------------ +wire refctrlwe ; +wire pcntwe ; +wire pfdctrlwe ; +wire spdctrlwe ; +wire ptatctrlwe ; +wire fllctrlwe ; +wire selctrlwe ; +wire vcoctrlwe ; +wire vcofbadjwe ; +wire afcctrlwe ; +wire afccntwe ; +wire afcldcntwe ; +wire afcpreswe ; +wire afcldtccwe ; +wire afcfbtccwe ; +wire divcfgwe ; +wire tclkcfgwe ; +wire dclkselwe ; +wire synccfgwe ; +wire updatewe ; +wire clkrxpdwe ; +// ------------------------------------------------------ +// -- Misc Registers +// ------------------------------------------------------ +wire [2 :0] refctrl_r ; +wire [6 :0] pcnt_r ; +wire [2 :0] pfdctrl_r ; +wire [5 :0] spdctrl_r ; +wire [6 :0] ptatctrl_r ; +wire [2 :0] fllctrl_r ; +wire [2 :0] selctrl_r ; +wire [11:0] vcoctrl_r ; +wire [6 :0] vcofbadj_r ; +wire [4 :0] afcctrl_r ; +wire [10:0] afccnt_r ; +wire [10:0] afcldcnt_r ; +wire [3 :0] afcpres_r ; +wire [14:0] afcldtcc_r ; +wire [14:0] afcfbtcc_r ; +wire [0 :0] divrstsel_r ; +wire [2 :0] testclk_r ; +wire [7 :0] digclksel_r ; +wire [1 :0] sync_r ; +wire clkrxpd_r ; + + + +wire [2 :0] refctrl_updr ; +wire [6 :0] pcnt_updr ; +wire [2 :0] pfdctrl_updr ; +wire [5 :0] spdctrl_updr ; +wire [6 :0] ptatctrl_updr ; +wire [2 :0] fllctrl_updr ; +wire [2 :0] selctrl_updr ; +wire [11:0] vcoctrl_updr ; +wire [6 :0] vcofbadj_updr ; +wire [4 :0] afcctrl_updr ; +wire [10:0] afccnt_updr ; +wire [10:0] afcldcnt_updr ; +wire [3 :0] afcpres_updr ; +wire [14:0] afcldtcc_updr ; +wire [14:0] afcfbtcc_updr ; + + + +reg [31 :0] rddata_reg ; + + +// ------------------------------------------------------ +// -- Address decoder +// +// Decodes the register address offset input(reg_addr) +// to produce enable (select) signals for each of the +// SW-registers in the macrocell. The reg_addr input +// is bits [15:0] of the paddr bus. +// ------------------------------------------------------ +assign refctrlen = (rwaddr[7:2] == `INTPLL_REFCTRL >>2) ? 1'b1 : 1'b0; +assign pcnten = (rwaddr[7:2] == `INTPLL_PCNT >>2) ? 1'b1 : 1'b0; +assign pfdctrlen = (rwaddr[7:2] == `INTPLL_PFDCTRL >>2) ? 1'b1 : 1'b0; +assign spdctrlen = (rwaddr[7:2] == `INTPLL_SPDCTRL >>2) ? 1'b1 : 1'b0; +assign ptatctrlen = (rwaddr[7:2] == `INTPLL_PTATCTRL >>2) ? 1'b1 : 1'b0; +assign fllctrlen = (rwaddr[7:2] == `INTPLL_FLLCTRL >>2) ? 1'b1 : 1'b0; +assign selctrlen = (rwaddr[7:2] == `INTPLL_SELCTRL >>2) ? 1'b1 : 1'b0; +assign vcoctrlen = (rwaddr[7:2] == `INTPLL_VCOCTRL >>2) ? 1'b1 : 1'b0; +assign vcofbadjen = (rwaddr[7:2] == `INTPLL_VCOFBADJ >>2) ? 1'b1 : 1'b0; +assign afcctrlen = (rwaddr[7:2] == `INTPLL_AFCCTRL >>2) ? 1'b1 : 1'b0; +assign afccnten = (rwaddr[7:2] == `INTPLL_AFCCNT >>2) ? 1'b1 : 1'b0; +assign afcldcnten = (rwaddr[7:2] == `INTPLL_AFCLDCNT >>2) ? 1'b1 : 1'b0; +assign afcpresen = (rwaddr[7:2] == `INTPLL_AFCPRES >>2) ? 1'b1 : 1'b0; +assign afcldtccen = (rwaddr[7:2] == `INTPLL_AFCLDTCC >>2) ? 1'b1 : 1'b0; +assign afcfbtccen = (rwaddr[7:2] == `INTPLL_AFCFBTCC >>2) ? 1'b1 : 1'b0; +assign divcfgen = (rwaddr[7:2] == `INTPLL_DIVCFG >>2) ? 1'b1 : 1'b0; +assign tclkcfgen = (rwaddr[7:2] == `INTPLL_TCLKCFG >>2) ? 1'b1 : 1'b0; +assign dclkselen = (rwaddr[7:2] == `INTPLL_DCLKSEL >>2) ? 1'b1 : 1'b0; +assign statusen = (rwaddr[7:2] == `INTPLL_STATUS >>2) ? 1'b1 : 1'b0; +assign synccfgen = (rwaddr[7:2] == `INTPLL_SYNCFG >>2) ? 1'b1 : 1'b0; +assign updateen = (rwaddr[7:2] == `INTPLL_UPDATE >>2) ? 1'b1 : 1'b0; +assign clkrxpden = (rwaddr[7:2] == `INTPLL_CLKRXPD >>2) ? 1'b1 : 1'b0; + + +// ------------------------------------------------------ +// -- Write enable signals +// +// Write enable signals for writable SW-registers. +// The write enable for each register is the ANDed +// result of the register enable and the input reg_wren +// ------------------------------------------------------ +assign refctrlwe = refctrlen & wren; +assign pcntwe = pcnten & wren; +assign pfdctrlwe = pfdctrlen & wren; +assign spdctrlwe = spdctrlen & wren; +assign ptatctrlwe = ptatctrlen & wren; +assign fllctrlwe = fllctrlen & wren; +assign selctrlwe = selctrlen & wren; +assign vcoctrlwe = vcoctrlen & wren; +assign vcofbadjwe = vcofbadjen & wren; +assign afcctrlwe = afcctrlen & wren; +assign afccntwe = afccnten & wren; +assign afcldcntwe = afcldcnten & wren; +assign afcpreswe = afcpresen & wren; +assign afcldtccwe = afcldtccen & wren; +assign afcfbtccwe = afcfbtccen & wren; +assign divcfgwe = divcfgen & wren; +assign tclkcfgwe = tclkcfgen & wren; +assign dclkselwe = dclkselen & wren; +assign synccfgwe = synccfgen & wren; +assign updatewe = updateen & wren; +assign clkrxpdwe = clkrxpden & wren; + + +// ------------------------------------------------------ +// -- refctrl_r Register +// +// Write refctrl_r for 'REFCTRL' : 32-bit register +// Register is split into the following bit fields +// +// [2] --> ref_s2d_en default : 1'b1 +// [1] --> ref_en default : 1'b1 +// [0] --> ref_sel default : 1'b0 +// ------------------------------------------------------ + +sirv_gnrl_dfflrd #(3) refctrl_dfflrd (3'b110, refctrlwe, wrdata[2:0], refctrl_r, clk, rst_n); + +//update +sirv_gnrl_dfflrd #(3) refctrl_updr_dfflrd (3'b110, updatewe, refctrl_r, refctrl_updr, clk, rst_n); + +// ------------------------------------------------------ +// -- pcnt_r Register +// +// Write pcnt_r for 'PCNT' : 32-bit register +// Register is split into the following bit fields +// +// [6 : 0] --> pcnt default : 7'b000_1100 +// ------------------------------------------------------ + +sirv_gnrl_dfflrd #(7) pcnt_dfflrd (7'b000_1100, pcntwe, wrdata[6:0], pcnt_r, clk, rst_n); + +//update +sirv_gnrl_dfflrd #(7) pcnt_updr_dfflrd (7'b000_1100, updatewe, pcnt_r, pcnt_updr, clk, rst_n); + +// ------------------------------------------------------ +// -- pfdctrl_r Register +// +// Write pfdctrl_reg for 'REFCTRL' : 32-bit register +// Register is split into the following bit fields +// +// [2] --> pfd_dff_4and default : 1'b1 +// [1] --> pfd_dff_Set default : 1'b1 +// [0] --> pfd_delay default : 1'b0 +// ------------------------------------------------------ + +sirv_gnrl_dfflrd #(3) pfdctrl_dfflrd (3'b110, pfdctrlwe, wrdata[2:0], pfdctrl_r, clk, rst_n);////////////////////////////////////////////// + +//update +sirv_gnrl_dfflrd #(3) pfdctrl_updr_dfflrd (3'b110, updatewe, pfdctrl_r, pfdctrl_updr, clk, rst_n); + +// ------------------------------------------------------ +// -- spdctrl_r Register +// +// Write spdctrl_r for 'SPDCTRL' : 32-bit register +// Register is split into the following bit fields +// +// [5 ] spd_pulse_sw default : 1'b0 +// [4 ] spd_pulse_width default : 1'b0 +// [3:0] spd_div default : 4'b0100 +// ------------------------------------------------------ + +sirv_gnrl_dfflrd #(6) spdctrl_dfflrd (6'b00_0100, spdctrlwe, wrdata[5:0], spdctrl_r, clk, rst_n); + +//update +sirv_gnrl_dfflrd #(6) spdctrl_updr_dfflrd (6'b00_0100, updatewe, spdctrl_r, spdctrl_updr, clk, rst_n); + +// ------------------------------------------------------ +// -- ptatctrl_r Register +// +// Write ptatctrl_r for 'PTATCTRL' : 32-bit register +// Register is split into the following bit fields +// +// [6 ] cpc_sel default : 1'b1 +// [5:4] swcp_i default : 2'b01 +// [3:0] sw_ptat_r default : 4'b1000 +// ------------------------------------------------------ + +sirv_gnrl_dfflrd #(7) ptatctrl_dfflrd (7'b101_1000, ptatctrlwe, wrdata[6:0], ptatctrl_r, clk, rst_n); + +//update +sirv_gnrl_dfflrd #(7) ptatctrl_updr_dfflrd (7'b101_1000, updatewe, ptatctrl_r, ptatctrl_updr, clk, rst_n); + +// ------------------------------------------------------ +// -- fllctrl_r Register +// +// Write fllctrl_r for 'FLLCTRL' : 32-bit register +// Register is split into the following bit fields +// +// [2 ] sw_fll_delay default : 1'b0 +// [1:0] sw_fll_cpi default : 2'b11 +// ------------------------------------------------------ + +sirv_gnrl_dfflrd #(3) fllctrl_dfflrd (3'b011, fllctrlwe, wrdata[2:0], fllctrl_r, clk, rst_n); + +//update +sirv_gnrl_dfflrd #(3) fllctrl_updr_dfflrd (3'b011, updatewe, fllctrl_r, fllctrl_updr, clk, rst_n); + +// ------------------------------------------------------ +// -- selctrl_r Register +// +// Write selctrl_r for 'SELCTRL' : 32-bit register +// Register is split into the following bit fields +// +// [2] fll_sel default : 1'b0 +// [1] spd_sel default : 1'b1 +// [0] pfd_sel default : 1'b0 +// ------------------------------------------------------ + +sirv_gnrl_dfflrd #(3) selctrl_dfflrd (3'b010, selctrlwe, wrdata[2:0], selctrl_r, clk, rst_n); + +//update +sirv_gnrl_dfflrd #(3) selctrl_updr_dfflrd (3'b010, updatewe, selctrl_r, selctrl_updr, clk, rst_n); + +// ------------------------------------------------------ +// -- vcoctrl_r Register +// +// Write vcoctrl_r for 'VCOCTRL' : 32-bit register +// Register is split into the following bit fields +// +// [11:9] pll_dpwr_adj default : 3'b111 +// [8 ] vco_en default : 1'b1 +// [7 ] vco_buff_en default : 1'b1 +// [6 :4] vco_cur_adj default : 3'b111 +// [3 ] vco_gain_adj_r default : 1'b0 +// [2 ] vco_gain_adj default : 1'b0 +// [1 ] vco_tcr default : 1'b0 +// [0 ] vco_tc default : 1'b0 +// ------------------------------------------------------ + +sirv_gnrl_dfflrd #(12) vcoctrl_dfflrd (12'b1111_1111_0000, vcoctrlwe, wrdata[11:0], vcoctrl_r, clk, rst_n); + +//update +sirv_gnrl_dfflrd #(12) vcoctrl_updr_dfflrd (12'b1111_1111_0000, updatewe, vcoctrl_r, vcoctrl_updr, clk, rst_n); + +// ------------------------------------------------------ +// -- vcofbadj_r Register +// +// Write vcofbadj_r for 'VCOFBADJ' : 32-bit register +// Register is split into the following bit fields +// +// [6 : 0] --> vco_fb_adj default : 7'b000_0000 +// ------------------------------------------------------ + +sirv_gnrl_dfflrd #(7) vcofbadj_dfflrd (7'b000_0000, vcofbadjwe, wrdata[6:0], vcofbadj_r, clk, rst_n); + +//update +sirv_gnrl_dfflrd #(7) vcofbadj_updr_dfflrd (7'b000_0000, updatewe, vcofbadj_r, vcofbadj_updr, clk, rst_n); + +// ------------------------------------------------------ +// -- afcctrl_r Register +// +// Write afcctrl_r for 'AFCCTRL' : 32-bit register +// Register is split into the following bit fields +// +// [4] afc_det_speed // default : 1'b0 +// [3] flag_out_sel // default : 1'b0 +// [2] afc_shutdown // default : 1'b0 +// [1] afc_reset // default : 1'b0 +// [0] afc_en // default : 1'b0 +// ------------------------------------------------------ + +sirv_gnrl_dfflrd #(5) afcctrl_dfflrd (5'b0_0000, afcctrlwe, wrdata[4:0], afcctrl_r, clk, rst_n); + +//update +sirv_gnrl_dfflrd #(5) afcctrl_updr_dfflrd (5'b0_0000, updatewe, afcctrl_r, afcctrl_updr, clk, rst_n); + +// ------------------------------------------------------ +// -- afccnt_r Register +// +// Write afccnt_r for 'AFCCnt' : 32-bit register +// Register is split into the following bit fields +// +// [10:0] --> afc_cnt default : 11'b000_1100_1000 +// ------------------------------------------------------ + +sirv_gnrl_dfflrd #(11) afccnt_dfflrd (11'b000_1100_1000, afccntwe, wrdata[10:0], afccnt_r, clk, rst_n); + +//update +sirv_gnrl_dfflrd #(11) afccnt_updr_dfflrd (11'b000_1100_1000, updatewe, afccnt_r, afccnt_updr, clk, rst_n); + +// ------------------------------------------------------ +// -- afccnt_r Register +// +// Write afcldcnt_r for 'AFCLDCnt' : 32-bit register +// Register is split into the following bit fields +// +// [10:0] --> afcld_cnt default : 11'b110_0100_0000 +// ------------------------------------------------------ + +sirv_gnrl_dfflrd #(11) afcldcnt_dfflrd (11'b110_0100_0000, afcldcntwe, wrdata[10:0], afcldcnt_r, clk, rst_n); + +//update +sirv_gnrl_dfflrd #(11) afcldcnt_updr_dfflrd (11'b110_0100_0000, updatewe, afcldcnt_r, afcldcnt_updr, clk, rst_n); + +// ------------------------------------------------------ +// -- afcpres_r Register +// +// Write afcpres_r for 'AFCPRES' : 32-bit register +// Register is split into the following bit fields +// +// [3:0] --> afc_pres default : 4'b0011 +// ------------------------------------------------------ + +sirv_gnrl_dfflrd #(4) afcpres_dfflrd (4'b0011, afcpreswe, wrdata[3:0], afcpres_r, clk, rst_n); + +//update +sirv_gnrl_dfflrd #(4) afcpres_updr_dfflrd (4'b0011, updatewe, afcpres_r, afcpres_updr, clk, rst_n); + +// ------------------------------------------------------ +// -- afcldtcc_r Register +// +// Write afcldtcc_r for 'AFCLDTCC' : 32-bit register +// Register is split into the following bit fields +// +// [14:0] --> afc_ld_tcc default : 15'b0 +// ------------------------------------------------------ + +sirv_gnrl_dfflrd #(15) afcldtcc_dfflrd (15'b0, afcldtccwe, wrdata[14:0], afcldtcc_r, clk, rst_n); + +//update +sirv_gnrl_dfflrd #(15) afcldtcc_updr_dfflrd (15'b0, updatewe, afcldtcc_r, afcldtcc_updr, clk, rst_n); + +// ------------------------------------------------------ +// -- afcfbtcc_r Register +// +// Write afcfbtcc_r for 'AFCLDTCC' : 32-bit register +// Register is split into the following bit fields +// +// [14:0] --> afc_fb_tcc default : 15'b0 +// ------------------------------------------------------ + +sirv_gnrl_dfflrd #(15) afcfbtcc_dfflrd (15'b0, afcfbtccwe, wrdata[14:0], afcfbtcc_r, clk, rst_n); + +//update +sirv_gnrl_dfflrd #(15) afcfbtcc_updr_dfflrd (15'b0, updatewe, afcfbtcc_r, afcfbtcc_updr, clk, rst_n); + + + + + +// ------------------------------------------------------ +// -- divrstsel_r Register +// +// Write divrstsel_r for 'DIVCFG' : 32-bit register +// Register is split into the following bit fields +// +// [0] --> divrstsel default : 1'b0 +// ------------------------------------------------------ + +sirv_gnrl_dfflrd #(1) divrstsel_r_dfflrd (1'b0, divcfgwe, wrdata[0], divrstsel_r, clk, rst_n); + +// ------------------------------------------------------ +// -- testclk_r Register +// +// Write divclksel_r for 'TCLKCFG' : 32-bit register +// Register is split into the following bit fields +// +// [1:0] --> testclksel default : 1'b0 +// [2] --> testclkoen default : 1'b0 +// ------------------------------------------------------ + +sirv_gnrl_dfflrd #(3) testclk_r_dfflrd (3'b0, tclkcfgwe, wrdata[2:0], testclk_r, clk, rst_n); + +// ------------------------------------------------------ +// -- digclksel_r Register +// +// Write digclksel_r for 'DIGCLKSEL' : 32-bit register +// Register is split into the following bit fields +// +// [7:0] --> digclksel default : 1'b0 +// ------------------------------------------------------ + +sirv_gnrl_dfflrd #(8) digclksel_r_dfflrd (8'b0000_0001, dclkselwe, wrdata[7:0], digclksel_r, clk, rst_n); + + + +// ------------------------------------------------------ +// -- clkrxpd_r Register +// +// Write digclksel_r for 'CLKRXPD' : 32-bit register +// Register is split into the following bit fields +// +// [0:0] --> clkrxpd default : 1'b0 +// ------------------------------------------------------ + +sirv_gnrl_dfflrd #(1) clkrxpd_r_dfflrd (1'b0, clkrxpdwe, wrdata[0], clkrxpd_r, clk, rst_n); + + + +// ------------------------------------------------------ +// -- sync_r Register +// +// Write divsync_r for 'SYNCFG' : 32-bit register +// Register is split into the following bit fields +// +// [0] --> divsync default : 1'b0 +// [1] --> sync_oe default : 1'b0 +// ------------------------------------------------------ + +sirv_gnrl_dfflrd #(2) sync_dfflrd (2'b0, synccfgwe, wrdata[1:0], sync_r, clk, rst_n); + + +// ------------------------------------------------------ +// -- Read data mux +// +// -- The data from the selected register is +// -- placed on a zero-padded 32-bit read data bus. +// ------------------------------------------------------ +always @(*) begin : RDDATA_PROC + rddata_reg = {32{1'b0}}; + if(refctrlen == H ) rddata_reg[2 :0] = refctrl_r ; + if(pcnten == H ) rddata_reg[6 :0] = pcnt_r ; + if(pfdctrlen == H ) rddata_reg[2 :0] = pfdctrl_r ; + if(spdctrlen == H ) rddata_reg[5 :0] = spdctrl_r ; + if(ptatctrlen == H ) rddata_reg[6 :0] = ptatctrl_r ; + if(fllctrlen == H ) rddata_reg[2 :0] = fllctrl_r ; + if(selctrlen == H ) rddata_reg[2 :0] = selctrl_r ; + if(vcoctrlen == H ) rddata_reg[11:0] = vcoctrl_r ; + if(vcofbadjen == H ) rddata_reg[6 :0] = vcofbadj_r ; + if(afcctrlen == H ) rddata_reg[4 :0] = afcctrl_r ; + if(afccnten == H ) rddata_reg[10:0] = afccnt_r ; + if(afcldcnten == H ) rddata_reg[10:0] = afcldcnt_r ; + if(afcpresen == H ) rddata_reg[3 :0] = afcpres_r ; + if(afcldtccen == H ) rddata_reg[14:0] = afcldtcc_r ; + if(afcfbtccen == H ) rddata_reg[14:0] = afcfbtcc_r ; + if(divcfgen == H ) rddata_reg[0 :0] = divrstsel_r ; + if(tclkcfgen == H ) rddata_reg[2 :0] = testclk_r ; + if(dclkselen == H ) rddata_reg[7 :0] = digclksel_r ; + if(statusen == H ) rddata_reg[0 :0] = pll_lock ; + if(synccfgen == H ) rddata_reg[1 :0] = sync_r ; + if(clkrxpden == H ) rddata_reg[1 :0] = clkrxpd_r ; + +end + + +//rddata +sirv_gnrl_dfflr #(32) rddata_dfflr (rden, rddata_reg, rddata, clk, rst_n); + +// ------------------------------------------------------ +// -- Output signals assignment +// ------------------------------------------------------ +assign ref_sel = refctrl_updr[0] ; // Clock source selection for a frequency divider; + // 1'b0:External clock source + // 1'b1:internal phase-locked loop clock source +assign ref_en = refctrl_updr[1] ; // Input reference clock enable + // 1'b0:enable,1'b1:disable +assign ref_s2d_en = refctrl_updr[2] ; // Referenced clock differential to single-ended conversion enable + // 1'b0:enable,1'b1:disable +assign p_cnt = pcnt_updr[6:0] ; // P counter +assign pfd_delay = pfdctrl_updr[0] ; // PFD Dead Zone +assign pfd_dff_Set = pfdctrl_updr[1] ; // Setting the PFD register,active high +assign pfd_dff_4and = pfdctrl_updr[2] ; // PFD output polarity +assign spd_div = spdctrl_updr[3:0] ; // SPD Frequency Divider +assign spd_pulse_width = spdctrl_updr[4] ; // Pulse Width of SPD +assign spd_pulse_sw = spdctrl_updr[5] ; // Pulse sw of SPD +assign cpc_sel = ptatctrl_updr[6] ; // current source selection +assign swcp_i = ptatctrl_updr[5:4] ; // PTAT current switch +assign sw_ptat_r = ptatctrl_updr[3:0] ; // PTAT current adjustment +assign sw_fll_cpi = fllctrl_updr[1:0] ; // Phase-locked loop charge pump current +assign sw_fll_delay = fllctrl_updr[2] ; // PLL Dead Zone +assign pfd_sel = selctrl_updr[0] ; // PFD Loop selection +assign spd_sel = selctrl_updr[1] ; // SPD Loop selection +assign fll_sel = selctrl_updr[2] ; // FLL Loop selection +assign vco_tc = vcoctrl_updr[0] ; // VCO temperature compensation +assign vco_tcr = vcoctrl_updr[1] ; // VCO temperature compensation resistor +assign vco_gain_adj = vcoctrl_updr[2] ; // VCO gain adjustment +assign vco_gain_adj_r = vcoctrl_updr[3] ; // VCO gain adjustment resistor +assign vco_cur_adj = vcoctrl_updr[6:4] ; // VCO current adjustment +assign vco_buff_en = vcoctrl_updr[7] ; // VCO buff enable,active high +assign vco_en = vcoctrl_updr[8] ; // VCO enable,active high +assign pll_dpwr_adj = vcoctrl_updr[11:9] ; // PLL frequency division output power adjustment +assign vco_fb_adj = vcofbadj_updr[6:0] ; // VCO frequency band adjustment +assign afc_en = afcctrl_updr[0] ; // AFC enable +assign afc_reset = afcctrl_updr[1] ; // AFC reset +assign afc_shutdown = afcctrl_updr[2] ; // AFC module shutdown signal +assign flag_out_sel = afcctrl_updr[3] ; // Read and choose the signs +assign afc_det_speed = afcctrl_updr[4] ; // AFC detection speed +assign afc_cnt = afccnt_updr[10:0] ; // AFC frequency band adjustment function counter + // counting time adjustment +assign afc_ld_cnt = afcldcnt_updr[10:0] ; // Adjust the counting time of the AFC lock detection + // feature counter +assign afc_pres = afcpres_updr[3:0] ; // Adjusting the resolution of the AFC comparator +assign afc_ld_tcc = afcldtcc_updr[14:0] ; // AFC Lock Detection Function Target Cycle Count +assign afc_fb_tcc = afcfbtcc_updr[14:0] ; // Target number of cycles for AFC frequency band + // adjustment function +assign div_rstn_sel = divrstsel_r[0:0] ; // +assign test_clk_sel = testclk_r[1:0] ; // +assign test_clk_oen = testclk_r[2] ; // +assign dig_clk_sel = digclksel_r[7:0] ; // + +assign div_sync_en = sync_r[0] ; // Frequency Divider Synchronous Clear Enable + +assign sync_oe = sync_r[1] ; // SYNC signal output enable, hign active + +assign clkrx_pdn = clkrxpd_r ; + +endmodule + +`undef INTPLL_REFCTRL +`undef INTPLL_PCNT +`undef INTPLL_PFDCTRL +`undef INTPLL_SPDCTRL +`undef INTPLL_PTATCTRL +`undef INTPLL_FLLCTRL +`undef INTPLL_SELCTRL +`undef INTPLL_VCOCTRL +`undef INTPLL_VCOFBADJ +`undef INTPLL_AFCCTRL +`undef INTPLL_AFCCNT +`undef INTPLL_AFCLDCNT +`undef INTPLL_AFCPRES +`undef INTPLL_AFCLDTCC +`undef INTPLL_AFCFBTCC +`undef INTPLL_DIVCFG +`undef INTPLL_TCLKCFG +`undef INTPLL_DCLKSEL +`undef INTPLL_STATUS +`undef INTPLL_SYNCFG +`undef INTPLL_UPDATE diff --git a/rtl/clk/intpll_regfile.v b/rtl/clk/intpll_regfile.v new file mode 100644 index 0000000..70d51f0 --- /dev/null +++ b/rtl/clk/intpll_regfile.v @@ -0,0 +1,694 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2024/03/19 10:41:08 +// Design Name: +// Module Name: intpll_regfile +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + +// ----------------------------------------------------------- +// -- Register address offset macros +// ----------------------------------------------------------- +//Int pll Ctrl Register +`define INTPLL_REFCTRL 8'h00 +`define INTPLL_PCNT 8'h04 +`define INTPLL_PFDCTRL 8'h08 +`define INTPLL_SPDCTRL 8'h0C +`define INTPLL_PTATCTRL 8'h10 +`define INTPLL_FLLCTRL 8'h14 +`define INTPLL_SELCTRL 8'h18 +`define INTPLL_VCOCTRL 8'h1C +`define INTPLL_VCOFBADJ 8'h20 +`define INTPLL_AFCCTRL 8'h24 +`define INTPLL_AFCCNT 8'h28 +`define INTPLL_AFCLDCNT 8'h2C +`define INTPLL_AFCPRES 8'h30 +`define INTPLL_AFCLDTCC 8'h34 +`define INTPLL_AFCFBTCC 8'h38 +`define INTPLL_DIVCFG 8'h3C +`define INTPLL_TCLKCFG 8'h40 +`define INTPLL_DCLKSEL 8'h44 +`define INTPLL_STATUS 8'h48 +`define INTPLL_SYNCFG 8'h4C +`define INTPLL_UPDATE 8'h50 +`define INTPLL_CLKRXPD 8'h54 + + +module intpll_regfile ( + //system port + input clk // System Main Clock + ,input rst_n // Spi Reset active low + //rw op port + ,input [31 :0] wrdata // write data + ,input wren // write enable + ,input [7 :0] rwaddr // read & write address + ,input rden // read enable + ,output [31 :0] rddata // read data + + ,output ref_sel // Clock source selection for a frequency divider; + // 1'b0:External clock source + // 1'b1:internal phase-locked loop clock source + ,output ref_en // Input reference clock enable + // 1'b0:enable,1'b1:disable + ,output ref_s2d_en // Referenced clock differential to single-ended conversion enable + // 1'b0:enable,1'b1:disable + ,output [6 :0] p_cnt // P counter + ,output pfd_delay // PFD Dead Zone + ,output pfd_dff_Set // Setting the PFD register,active high + ,output pfd_dff_4and // PFD output polarity + ,output [3 :0] spd_div // SPD Frequency Divider + ,output spd_pulse_width // Pulse Width of SPD + ,output spd_pulse_sw // Pulse sw of SPD + ,output cpc_sel // current source selection + ,output [1 :0] swcp_i // PTAT current switch + ,output [3 :0] sw_ptat_r // PTAT current adjustment + ,output [1 :0] sw_fll_cpi // Phase-locked loop charge pump current + ,output sw_fll_delay // PLL Dead Zone + ,output pfd_sel // PFD Loop selection + ,output spd_sel // SPD Loop selection + ,output fll_sel // FLL Loop selection + ,output vco_tc // VCO temperature compensation + ,output vco_tcr // VCO temperature compensation resistor + ,output vco_gain_adj // VCO gain adjustment + ,output vco_gain_adj_r // VCO gain adjustment resistor + ,output [2 :0] vco_cur_adj // VCO current adjustment + ,output vco_buff_en // VCO buff enable,active high + ,output vco_en // VCO enable,active high + ,output [2 :0] pll_dpwr_adj // PLL frequency division output power adjustment + ,output [6 :0] vco_fb_adj // VCO frequency band adjustment + ,output afc_en // AFC enable + ,output afc_shutdown // AFC module shutdown signal + ,output [0 :0] afc_det_speed // AFC detection speed + ,output [0 :0] flag_out_sel // Read and choose the signs + ,output afc_reset // AFC reset + ,output [10 :0] afc_cnt // AFC frequency band adjustment function counter + // counting time adjustment + ,output [10 :0] afc_ld_cnt // Adjust the counting time of the AFC lock detection + // feature counter + ,output [3 :0] afc_pres // Adjusting the resolution of the AFC comparator + ,output [14 :0] afc_ld_tcc // AFC Lock Detection Function Target Cycle Count + ,output [14 :0] afc_fb_tcc // Target number of cycles for AFC frequency band + // adjustment function + ,output [0 :0] div_rstn_sel // div rstn select, 1'b0: ext clear, 1'b1:inter pll lock + ,output [1 :0] test_clk_sel // test clk select, 2'b00:DIV1 clk, 2'b01:DIV2 clk, 2'b10:DIV4 clk, 2'b11:DIV8 clk + ,output [0 :0] test_clk_oen // test clk output enable, 1'b0:disenable, 1'b1:enable + ,output [7 :0] dig_clk_sel // digital main clk select, one hot code,bit[0]-->0 degree phase,bit[1]-->45 degree phase.....bit[7]-->315degree phae + ,output [0 :0] div_sync_en // Frequency Divider Synchronous Clear Enable + ,output sync_oe // SYNC signal output enable, hign active + ,output clkrx_pdn // Clock Rx Power down, Ative Low + ,input pll_lock // PLL LOCK +); + +localparam L = 1'b0, + H = 1'b1; + +// ------------------------------------------------------ +// -- Register enable (select) wires +// ------------------------------------------------------ +wire refctrlen ; +wire pcnten ; +wire pfdctrlen ; +wire spdctrlen ; +wire ptatctrlen ; +wire fllctrlen ; +wire selctrlen ; +wire vcoctrlen ; +wire vcofbadjen ; +wire afcctrlen ; +wire afccnten ; +wire afcldcnten ; +wire afcpresen ; +wire afcldtccen ; +wire afcfbtccen ; +wire divcfgen ; +wire tclkcfgen ; +wire dclkselen ; +wire statusen ; +wire synccfgen ; +wire updateen ; +wire clkrxpden ; + + +// ------------------------------------------------------ +// -- Register write enable wires +// ------------------------------------------------------ +wire refctrlwe ; +wire pcntwe ; +wire pfdctrlwe ; +wire spdctrlwe ; +wire ptatctrlwe ; +wire fllctrlwe ; +wire selctrlwe ; +wire vcoctrlwe ; +wire vcofbadjwe ; +wire afcctrlwe ; +wire afccntwe ; +wire afcldcntwe ; +wire afcpreswe ; +wire afcldtccwe ; +wire afcfbtccwe ; +wire divcfgwe ; +wire tclkcfgwe ; +wire dclkselwe ; +wire synccfgwe ; +wire updatewe ; +wire clkrxpdwe ; +// ------------------------------------------------------ +// -- Misc Registers +// ------------------------------------------------------ +wire [2 :0] refctrl_r ; +wire [6 :0] pcnt_r ; +wire [2 :0] pfdctrl_r ; +wire [5 :0] spdctrl_r ; +wire [6 :0] ptatctrl_r ; +wire [2 :0] fllctrl_r ; +wire [2 :0] selctrl_r ; +wire [11:0] vcoctrl_r ; +wire [6 :0] vcofbadj_r ; +wire [4 :0] afcctrl_r ; +wire [10:0] afccnt_r ; +wire [10:0] afcldcnt_r ; +wire [3 :0] afcpres_r ; +wire [14:0] afcldtcc_r ; +wire [14:0] afcfbtcc_r ; +wire [0 :0] divrstsel_r ; +wire [2 :0] testclk_r ; +wire [7 :0] digclksel_r ; +wire [1 :0] sync_r ; +wire clkrxpd_r ; + + + +wire [2 :0] refctrl_updr ; +wire [6 :0] pcnt_updr ; +wire [2 :0] pfdctrl_updr ; +wire [5 :0] spdctrl_updr ; +wire [6 :0] ptatctrl_updr ; +wire [2 :0] fllctrl_updr ; +wire [2 :0] selctrl_updr ; +wire [11:0] vcoctrl_updr ; +wire [6 :0] vcofbadj_updr ; +wire [4 :0] afcctrl_updr ; +wire [10:0] afccnt_updr ; +wire [10:0] afcldcnt_updr ; +wire [3 :0] afcpres_updr ; +wire [14:0] afcldtcc_updr ; +wire [14:0] afcfbtcc_updr ; + + + +reg [15 :0] rddata_reg ; + +wire [15 :0] wrdata_h = wrdata[31:16]; + + +// ------------------------------------------------------ +// -- Address decoder +// +// Decodes the register address offset input(reg_addr) +// to produce enable (select) signals for each of the +// SW-registers in the macrocell. The reg_addr input +// is bits [15:0] of the paddr bus. +// ------------------------------------------------------ +assign refctrlen = (rwaddr[7:2] == `INTPLL_REFCTRL >>2) ? 1'b1 : 1'b0; +assign pcnten = (rwaddr[7:2] == `INTPLL_PCNT >>2) ? 1'b1 : 1'b0; +assign pfdctrlen = (rwaddr[7:2] == `INTPLL_PFDCTRL >>2) ? 1'b1 : 1'b0; +assign spdctrlen = (rwaddr[7:2] == `INTPLL_SPDCTRL >>2) ? 1'b1 : 1'b0; +assign ptatctrlen = (rwaddr[7:2] == `INTPLL_PTATCTRL >>2) ? 1'b1 : 1'b0; +assign fllctrlen = (rwaddr[7:2] == `INTPLL_FLLCTRL >>2) ? 1'b1 : 1'b0; +assign selctrlen = (rwaddr[7:2] == `INTPLL_SELCTRL >>2) ? 1'b1 : 1'b0; +assign vcoctrlen = (rwaddr[7:2] == `INTPLL_VCOCTRL >>2) ? 1'b1 : 1'b0; +assign vcofbadjen = (rwaddr[7:2] == `INTPLL_VCOFBADJ >>2) ? 1'b1 : 1'b0; +assign afcctrlen = (rwaddr[7:2] == `INTPLL_AFCCTRL >>2) ? 1'b1 : 1'b0; +assign afccnten = (rwaddr[7:2] == `INTPLL_AFCCNT >>2) ? 1'b1 : 1'b0; +assign afcldcnten = (rwaddr[7:2] == `INTPLL_AFCLDCNT >>2) ? 1'b1 : 1'b0; +assign afcpresen = (rwaddr[7:2] == `INTPLL_AFCPRES >>2) ? 1'b1 : 1'b0; +assign afcldtccen = (rwaddr[7:2] == `INTPLL_AFCLDTCC >>2) ? 1'b1 : 1'b0; +assign afcfbtccen = (rwaddr[7:2] == `INTPLL_AFCFBTCC >>2) ? 1'b1 : 1'b0; +assign divcfgen = (rwaddr[7:2] == `INTPLL_DIVCFG >>2) ? 1'b1 : 1'b0; +assign tclkcfgen = (rwaddr[7:2] == `INTPLL_TCLKCFG >>2) ? 1'b1 : 1'b0; +assign dclkselen = (rwaddr[7:2] == `INTPLL_DCLKSEL >>2) ? 1'b1 : 1'b0; +assign statusen = (rwaddr[7:2] == `INTPLL_STATUS >>2) ? 1'b1 : 1'b0; +assign synccfgen = (rwaddr[7:2] == `INTPLL_SYNCFG >>2) ? 1'b1 : 1'b0; +assign updateen = (rwaddr[7:2] == `INTPLL_UPDATE >>2) ? 1'b1 : 1'b0; +assign clkrxpden = (rwaddr[7:2] == `INTPLL_CLKRXPD >>2) ? 1'b1 : 1'b0; + + +// ------------------------------------------------------ +// -- Write enable signals +// +// Write enable signals for writable SW-registers. +// The write enable for each register is the ANDed +// result of the register enable and the input reg_wren +// ------------------------------------------------------ +assign refctrlwe = refctrlen & wren; +assign pcntwe = pcnten & wren; +assign pfdctrlwe = pfdctrlen & wren; +assign spdctrlwe = spdctrlen & wren; +assign ptatctrlwe = ptatctrlen & wren; +assign fllctrlwe = fllctrlen & wren; +assign selctrlwe = selctrlen & wren; +assign vcoctrlwe = vcoctrlen & wren; +assign vcofbadjwe = vcofbadjen & wren; +assign afcctrlwe = afcctrlen & wren; +assign afccntwe = afccnten & wren; +assign afcldcntwe = afcldcnten & wren; +assign afcpreswe = afcpresen & wren; +assign afcldtccwe = afcldtccen & wren; +assign afcfbtccwe = afcfbtccen & wren; +assign divcfgwe = divcfgen & wren; +assign tclkcfgwe = tclkcfgen & wren; +assign dclkselwe = dclkselen & wren; +assign synccfgwe = synccfgen & wren; +assign updatewe = updateen & wren; +assign clkrxpdwe = clkrxpden & wren; + + +// ------------------------------------------------------ +// -- refctrl_r Register +// +// Write refctrl_r for 'REFCTRL' : 32-bit register +// Register is split into the following bit fields +// +// [2] --> ref_s2d_en default : 1'b1 +// [1] --> ref_en default : 1'b1 +// [0] --> ref_sel default : 1'b0 +// ------------------------------------------------------ + +sirv_gnrl_dfflrd #(3) refctrl_dfflrd (3'b110, refctrlwe, wrdata_h[2:0], refctrl_r, clk, rst_n); + +//update +sirv_gnrl_dfflrd #(3) refctrl_updr_dfflrd (3'b110, updatewe, refctrl_r, refctrl_updr, clk, rst_n); + +// ------------------------------------------------------ +// -- pcnt_r Register +// +// Write pcnt_r for 'PCNT' : 32-bit register +// Register is split into the following bit fields +// +// [6 : 0] --> pcnt default : 7'b000_1100 +// ------------------------------------------------------ + +sirv_gnrl_dfflrd #(7) pcnt_dfflrd (7'b000_1100, pcntwe, wrdata_h[6:0], pcnt_r, clk, rst_n); + +//update +sirv_gnrl_dfflrd #(7) pcnt_updr_dfflrd (7'b000_1100, updatewe, pcnt_r, pcnt_updr, clk, rst_n); + +// ------------------------------------------------------ +// -- pfdctrl_r Register +// +// Write pfdctrl_reg for 'REFCTRL' : 32-bit register +// Register is split into the following bit fields +// +// [2] --> pfd_dff_4and default : 1'b1 +// [1] --> pfd_dff_Set default : 1'b1 +// [0] --> pfd_delay default : 1'b0 +// ------------------------------------------------------ + +sirv_gnrl_dfflrd #(3) pfdctrl_dfflrd (3'b110, pfdctrlwe, wrdata_h[2:0], pfdctrl_r, clk, rst_n);////////////////////////////////////////////// + +//update +sirv_gnrl_dfflrd #(3) pfdctrl_updr_dfflrd (3'b110, updatewe, pfdctrl_r, pfdctrl_updr, clk, rst_n); + +// ------------------------------------------------------ +// -- spdctrl_r Register +// +// Write spdctrl_r for 'SPDCTRL' : 32-bit register +// Register is split into the following bit fields +// +// [5 ] spd_pulse_sw default : 1'b0 +// [4 ] spd_pulse_width default : 1'b0 +// [3:0] spd_div default : 4'b0100 +// ------------------------------------------------------ + +sirv_gnrl_dfflrd #(6) spdctrl_dfflrd (6'b00_0100, spdctrlwe, wrdata_h[5:0], spdctrl_r, clk, rst_n); + +//update +sirv_gnrl_dfflrd #(6) spdctrl_updr_dfflrd (6'b00_0100, updatewe, spdctrl_r, spdctrl_updr, clk, rst_n); + +// ------------------------------------------------------ +// -- ptatctrl_r Register +// +// Write ptatctrl_r for 'PTATCTRL' : 32-bit register +// Register is split into the following bit fields +// +// [6 ] cpc_sel default : 1'b1 +// [5:4] swcp_i default : 2'b01 +// [3:0] sw_ptat_r default : 4'b1000 +// ------------------------------------------------------ + +sirv_gnrl_dfflrd #(7) ptatctrl_dfflrd (7'b101_1000, ptatctrlwe, wrdata_h[6:0], ptatctrl_r, clk, rst_n); + +//update +sirv_gnrl_dfflrd #(7) ptatctrl_updr_dfflrd (7'b101_1000, updatewe, ptatctrl_r, ptatctrl_updr, clk, rst_n); + +// ------------------------------------------------------ +// -- fllctrl_r Register +// +// Write fllctrl_r for 'FLLCTRL' : 32-bit register +// Register is split into the following bit fields +// +// [2 ] sw_fll_delay default : 1'b0 +// [1:0] sw_fll_cpi default : 2'b11 +// ------------------------------------------------------ + +sirv_gnrl_dfflrd #(3) fllctrl_dfflrd (3'b011, fllctrlwe, wrdata_h[2:0], fllctrl_r, clk, rst_n); + +//update +sirv_gnrl_dfflrd #(3) fllctrl_updr_dfflrd (3'b011, updatewe, fllctrl_r, fllctrl_updr, clk, rst_n); + +// ------------------------------------------------------ +// -- selctrl_r Register +// +// Write selctrl_r for 'SELCTRL' : 32-bit register +// Register is split into the following bit fields +// +// [2] fll_sel default : 1'b0 +// [1] spd_sel default : 1'b1 +// [0] pfd_sel default : 1'b0 +// ------------------------------------------------------ + +sirv_gnrl_dfflrd #(3) selctrl_dfflrd (3'b010, selctrlwe, wrdata_h[2:0], selctrl_r, clk, rst_n); + +//update +sirv_gnrl_dfflrd #(3) selctrl_updr_dfflrd (3'b010, updatewe, selctrl_r, selctrl_updr, clk, rst_n); + +// ------------------------------------------------------ +// -- vcoctrl_r Register +// +// Write vcoctrl_r for 'VCOCTRL' : 32-bit register +// Register is split into the following bit fields +// +// [11:9] pll_dpwr_adj default : 3'b111 +// [8 ] vco_en default : 1'b1 +// [7 ] vco_buff_en default : 1'b1 +// [6 :4] vco_cur_adj default : 3'b111 +// [3 ] vco_gain_adj_r default : 1'b0 +// [2 ] vco_gain_adj default : 1'b0 +// [1 ] vco_tcr default : 1'b0 +// [0 ] vco_tc default : 1'b0 +// ------------------------------------------------------ + +sirv_gnrl_dfflrd #(12) vcoctrl_dfflrd (12'b1111_1111_0000, vcoctrlwe, wrdata_h[11:0], vcoctrl_r, clk, rst_n); + +//update +sirv_gnrl_dfflrd #(12) vcoctrl_updr_dfflrd (12'b1111_1111_0000, updatewe, vcoctrl_r, vcoctrl_updr, clk, rst_n); + +// ------------------------------------------------------ +// -- vcofbadj_r Register +// +// Write vcofbadj_r for 'VCOFBADJ' : 32-bit register +// Register is split into the following bit fields +// +// [6 : 0] --> vco_fb_adj default : 7'b000_0000 +// ------------------------------------------------------ + +sirv_gnrl_dfflrd #(7) vcofbadj_dfflrd (7'b000_0000, vcofbadjwe, wrdata_h[6:0], vcofbadj_r, clk, rst_n); + +//update +sirv_gnrl_dfflrd #(7) vcofbadj_updr_dfflrd (7'b000_0000, updatewe, vcofbadj_r, vcofbadj_updr, clk, rst_n); + +// ------------------------------------------------------ +// -- afcctrl_r Register +// +// Write afcctrl_r for 'AFCCTRL' : 32-bit register +// Register is split into the following bit fields +// +// [4] afc_det_speed // default : 1'b0 +// [3] flag_out_sel // default : 1'b0 +// [2] afc_shutdown // default : 1'b0 +// [1] afc_reset // default : 1'b0 +// [0] afc_en // default : 1'b0 +// ------------------------------------------------------ + +sirv_gnrl_dfflrd #(5) afcctrl_dfflrd (5'b0_0000, afcctrlwe, wrdata_h[4:0], afcctrl_r, clk, rst_n); + +//update +sirv_gnrl_dfflrd #(5) afcctrl_updr_dfflrd (5'b0_0000, updatewe, afcctrl_r, afcctrl_updr, clk, rst_n); + +// ------------------------------------------------------ +// -- afccnt_r Register +// +// Write afccnt_r for 'AFCCnt' : 32-bit register +// Register is split into the following bit fields +// +// [10:0] --> afc_cnt default : 11'b000_1100_1000 +// ------------------------------------------------------ + +sirv_gnrl_dfflrd #(11) afccnt_dfflrd (11'b000_1100_1000, afccntwe, wrdata_h[10:0], afccnt_r, clk, rst_n); + +//update +sirv_gnrl_dfflrd #(11) afccnt_updr_dfflrd (11'b000_1100_1000, updatewe, afccnt_r, afccnt_updr, clk, rst_n); + +// ------------------------------------------------------ +// -- afccnt_r Register +// +// Write afcldcnt_r for 'AFCLDCnt' : 32-bit register +// Register is split into the following bit fields +// +// [10:0] --> afcld_cnt default : 11'b110_0100_0000 +// ------------------------------------------------------ + +sirv_gnrl_dfflrd #(11) afcldcnt_dfflrd (11'b110_0100_0000, afcldcntwe, wrdata_h[10:0], afcldcnt_r, clk, rst_n); + +//update +sirv_gnrl_dfflrd #(11) afcldcnt_updr_dfflrd (11'b110_0100_0000, updatewe, afcldcnt_r, afcldcnt_updr, clk, rst_n); + +// ------------------------------------------------------ +// -- afcpres_r Register +// +// Write afcpres_r for 'AFCPRES' : 32-bit register +// Register is split into the following bit fields +// +// [3:0] --> afc_pres default : 4'b0011 +// ------------------------------------------------------ + +sirv_gnrl_dfflrd #(4) afcpres_dfflrd (4'b0011, afcpreswe, wrdata_h[3:0], afcpres_r, clk, rst_n); + +//update +sirv_gnrl_dfflrd #(4) afcpres_updr_dfflrd (4'b0011, updatewe, afcpres_r, afcpres_updr, clk, rst_n); + +// ------------------------------------------------------ +// -- afcldtcc_r Register +// +// Write afcldtcc_r for 'AFCLDTCC' : 32-bit register +// Register is split into the following bit fields +// +// [14:0] --> afc_ld_tcc default : 15'b0 +// ------------------------------------------------------ + +sirv_gnrl_dfflrd #(15) afcldtcc_dfflrd (15'b0, afcldtccwe, wrdata_h[14:0], afcldtcc_r, clk, rst_n); + +//update +sirv_gnrl_dfflrd #(15) afcldtcc_updr_dfflrd (15'b0, updatewe, afcldtcc_r, afcldtcc_updr, clk, rst_n); + +// ------------------------------------------------------ +// -- afcfbtcc_r Register +// +// Write afcfbtcc_r for 'AFCLDTCC' : 32-bit register +// Register is split into the following bit fields +// +// [14:0] --> afc_fb_tcc default : 15'b0 +// ------------------------------------------------------ + +sirv_gnrl_dfflrd #(15) afcfbtcc_dfflrd (15'b0, afcfbtccwe, wrdata_h[14:0], afcfbtcc_r, clk, rst_n); + +//update +sirv_gnrl_dfflrd #(15) afcfbtcc_updr_dfflrd (15'b0, updatewe, afcfbtcc_r, afcfbtcc_updr, clk, rst_n); + + + + + +// ------------------------------------------------------ +// -- divrstsel_r Register +// +// Write divrstsel_r for 'DIVCFG' : 32-bit register +// Register is split into the following bit fields +// +// [0] --> divrstsel default : 1'b0 +// ------------------------------------------------------ + +sirv_gnrl_dfflrd #(1) divrstsel_r_dfflrd (1'b0, divcfgwe, wrdata_h[0], divrstsel_r, clk, rst_n); + +// ------------------------------------------------------ +// -- testclk_r Register +// +// Write divclksel_r for 'TCLKCFG' : 32-bit register +// Register is split into the following bit fields +// +// [1:0] --> testclksel default : 1'b0 +// [2] --> testclkoen default : 1'b0 +// ------------------------------------------------------ + +sirv_gnrl_dfflrd #(3) testclk_r_dfflrd (3'b0, tclkcfgwe, wrdata_h[2:0], testclk_r, clk, rst_n); + +// ------------------------------------------------------ +// -- digclksel_r Register +// +// Write digclksel_r for 'DIGCLKSEL' : 32-bit register +// Register is split into the following bit fields +// +// [7:0] --> digclksel default : 1'b0 +// ------------------------------------------------------ + +sirv_gnrl_dfflrd #(8) digclksel_r_dfflrd (8'b0000_0001, dclkselwe, wrdata_h[7:0], digclksel_r, clk, rst_n); + + + +// ------------------------------------------------------ +// -- clkrxpd_r Register +// +// Write digclksel_r for 'CLKRXPD' : 32-bit register +// Register is split into the following bit fields +// +// [0:0] --> clkrxpd default : 1'b0 +// ------------------------------------------------------ + +sirv_gnrl_dfflrd #(1) clkrxpd_r_dfflrd (1'b0, clkrxpdwe, wrdata_h[0], clkrxpd_r, clk, rst_n); + + + +// ------------------------------------------------------ +// -- sync_r Register +// +// Write divsync_r for 'SYNCFG' : 32-bit register +// Register is split into the following bit fields +// +// [0] --> divsync default : 1'b0 +// [1] --> sync_oe default : 1'b0 +// ------------------------------------------------------ + +sirv_gnrl_dfflrd #(2) sync_dfflrd (2'b0, synccfgwe, wrdata_h[1:0], sync_r, clk, rst_n); + + +// ------------------------------------------------------ +// -- Read data mux +// +// -- The data from the selected register is +// -- placed on a zero-padded 32-bit read data bus. +// ------------------------------------------------------ +always @(*) begin : RDDATA_PROC + rddata_reg = {16{1'b0}}; + if(refctrlen == H ) rddata_reg[2 :0] = refctrl_r ; + if(pcnten == H ) rddata_reg[6 :0] = pcnt_r ; + if(pfdctrlen == H ) rddata_reg[2 :0] = pfdctrl_r ; + if(spdctrlen == H ) rddata_reg[5 :0] = spdctrl_r ; + if(ptatctrlen == H ) rddata_reg[6 :0] = ptatctrl_r ; + if(fllctrlen == H ) rddata_reg[2 :0] = fllctrl_r ; + if(selctrlen == H ) rddata_reg[2 :0] = selctrl_r ; + if(vcoctrlen == H ) rddata_reg[11:0] = vcoctrl_r ; + if(vcofbadjen == H ) rddata_reg[6 :0] = vcofbadj_r ; + if(afcctrlen == H ) rddata_reg[4 :0] = afcctrl_r ; + if(afccnten == H ) rddata_reg[10:0] = afccnt_r ; + if(afcldcnten == H ) rddata_reg[10:0] = afcldcnt_r ; + if(afcpresen == H ) rddata_reg[3 :0] = afcpres_r ; + if(afcldtccen == H ) rddata_reg[14:0] = afcldtcc_r ; + if(afcfbtccen == H ) rddata_reg[14:0] = afcfbtcc_r ; + if(divcfgen == H ) rddata_reg[0 :0] = divrstsel_r ; + if(tclkcfgen == H ) rddata_reg[2 :0] = testclk_r ; + if(dclkselen == H ) rddata_reg[7 :0] = digclksel_r ; + if(statusen == H ) rddata_reg[0 :0] = pll_lock ; + if(synccfgen == H ) rddata_reg[1 :0] = sync_r ; + if(clkrxpden == H ) rddata_reg[1 :0] = clkrxpd_r ; + +end + + +//rddata +sirv_gnrl_dfflr #(32) rddata_dfflr (rden, {rddata_reg,16'h0}, rddata, clk, rst_n); + +// ------------------------------------------------------ +// -- Output signals assignment +// ------------------------------------------------------ +assign ref_sel = refctrl_updr[0] ; // Clock source selection for a frequency divider; + // 1'b0:External clock source + // 1'b1:internal phase-locked loop clock source +assign ref_en = refctrl_updr[1] ; // Input reference clock enable + // 1'b0:enable,1'b1:disable +assign ref_s2d_en = refctrl_updr[2] ; // Referenced clock differential to single-ended conversion enable + // 1'b0:enable,1'b1:disable +assign p_cnt = pcnt_updr[6:0] ; // P counter +assign pfd_delay = pfdctrl_updr[0] ; // PFD Dead Zone +assign pfd_dff_Set = pfdctrl_updr[1] ; // Setting the PFD register,active high +assign pfd_dff_4and = pfdctrl_updr[2] ; // PFD output polarity +assign spd_div = spdctrl_updr[3:0] ; // SPD Frequency Divider +assign spd_pulse_width = spdctrl_updr[4] ; // Pulse Width of SPD +assign spd_pulse_sw = spdctrl_updr[5] ; // Pulse sw of SPD +assign cpc_sel = ptatctrl_updr[6] ; // current source selection +assign swcp_i = ptatctrl_updr[5:4] ; // PTAT current switch +assign sw_ptat_r = ptatctrl_updr[3:0] ; // PTAT current adjustment +assign sw_fll_cpi = fllctrl_updr[1:0] ; // Phase-locked loop charge pump current +assign sw_fll_delay = fllctrl_updr[2] ; // PLL Dead Zone +assign pfd_sel = selctrl_updr[0] ; // PFD Loop selection +assign spd_sel = selctrl_updr[1] ; // SPD Loop selection +assign fll_sel = selctrl_updr[2] ; // FLL Loop selection +assign vco_tc = vcoctrl_updr[0] ; // VCO temperature compensation +assign vco_tcr = vcoctrl_updr[1] ; // VCO temperature compensation resistor +assign vco_gain_adj = vcoctrl_updr[2] ; // VCO gain adjustment +assign vco_gain_adj_r = vcoctrl_updr[3] ; // VCO gain adjustment resistor +assign vco_cur_adj = vcoctrl_updr[6:4] ; // VCO current adjustment +assign vco_buff_en = vcoctrl_updr[7] ; // VCO buff enable,active high +assign vco_en = vcoctrl_updr[8] ; // VCO enable,active high +assign pll_dpwr_adj = vcoctrl_updr[11:9] ; // PLL frequency division output power adjustment +assign vco_fb_adj = vcofbadj_updr[6:0] ; // VCO frequency band adjustment +assign afc_en = afcctrl_updr[0] ; // AFC enable +assign afc_reset = afcctrl_updr[1] ; // AFC reset +assign afc_shutdown = afcctrl_updr[2] ; // AFC module shutdown signal +assign flag_out_sel = afcctrl_updr[3] ; // Read and choose the signs +assign afc_det_speed = afcctrl_updr[4] ; // AFC detection speed +assign afc_cnt = afccnt_updr[10:0] ; // AFC frequency band adjustment function counter + // counting time adjustment +assign afc_ld_cnt = afcldcnt_updr[10:0] ; // Adjust the counting time of the AFC lock detection + // feature counter +assign afc_pres = afcpres_updr[3:0] ; // Adjusting the resolution of the AFC comparator +assign afc_ld_tcc = afcldtcc_updr[14:0] ; // AFC Lock Detection Function Target Cycle Count +assign afc_fb_tcc = afcfbtcc_updr[14:0] ; // Target number of cycles for AFC frequency band + // adjustment function +assign div_rstn_sel = divrstsel_r[0:0] ; // +assign test_clk_sel = testclk_r[1:0] ; // +assign test_clk_oen = testclk_r[2] ; // +assign dig_clk_sel = digclksel_r[7:0] ; // + +assign div_sync_en = sync_r[0] ; // Frequency Divider Synchronous Clear Enable + +assign sync_oe = sync_r[1] ; // SYNC signal output enable, hign active + +assign clkrx_pdn = clkrxpd_r ; + +endmodule + +`undef INTPLL_REFCTRL +`undef INTPLL_PCNT +`undef INTPLL_PFDCTRL +`undef INTPLL_SPDCTRL +`undef INTPLL_PTATCTRL +`undef INTPLL_FLLCTRL +`undef INTPLL_SELCTRL +`undef INTPLL_VCOCTRL +`undef INTPLL_VCOFBADJ +`undef INTPLL_AFCCTRL +`undef INTPLL_AFCCNT +`undef INTPLL_AFCLDCNT +`undef INTPLL_AFCPRES +`undef INTPLL_AFCLDTCC +`undef INTPLL_AFCFBTCC +`undef INTPLL_DIVCFG +`undef INTPLL_TCLKCFG +`undef INTPLL_DCLKSEL +`undef INTPLL_STATUS +`undef INTPLL_SYNCFG +`undef INTPLL_UPDATE diff --git a/rtl/comm/sirv_gnrl_dffs.v b/rtl/comm/sirv_gnrl_dffs.v new file mode 100644 index 0000000..09e8ba1 --- /dev/null +++ b/rtl/comm/sirv_gnrl_dffs.v @@ -0,0 +1,326 @@ + /* + Copyright 2018-2020 Nuclei System Technology, Inc. + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + */ + + + +//===================================================================== +// +// Designer : Bob Hu +// +// Description: +// All of the general DFF and Latch modules +// +// ==================================================================== + +// + + +// +// =========================================================================== +// +// Description: +// Verilog module sirv_gnrl DFF with Load-enable and Reset +// Default reset value is 1 +// +// =========================================================================== +`define DISABLE_SV_ASSERTION +`define dly #0.2 +module sirv_gnrl_dfflrs # ( + parameter DW = 32 +) ( + + input lden, + input [DW-1:0] dnxt, + output [DW-1:0] qout, + + input clk, + input rst_n +); + +reg [DW-1:0] qout_r; + +always @(posedge clk or negedge rst_n) +begin : DFFLRS_PROC + if (rst_n == 1'b0) + qout_r <= {DW{1'b1}}; + else if (lden == 1'b1) + qout_r <= `dly dnxt; +end + +assign qout = qout_r; + +`ifndef FPGA_SOURCE//{ +`ifndef DISABLE_SV_ASSERTION//{ +//synopsys translate_off +sirv_gnrl_xchecker # ( + .DW(1) +) sirv_gnrl_xchecker( + .i_dat(lden), + .clk (clk) +); +//synopsys translate_on +`endif//} +`endif//} + + +endmodule +// =========================================================================== +// +// Description: +// Verilog module sirv_gnrl DFF with Load-enable and Reset +// Default reset value is 0 +// +// =========================================================================== + +module sirv_gnrl_dfflr # ( + parameter DW = 32 +) ( + + input lden, + input [DW-1:0] dnxt, + output [DW-1:0] qout, + + input clk, + input rst_n +); + +reg [DW-1:0] qout_r; + +always @(posedge clk or negedge rst_n) +begin : DFFLR_PROC + if (rst_n == 1'b0) + qout_r <= {DW{1'b0}}; + else if (lden == 1'b1) + qout_r <= `dly dnxt; +end + +assign qout = qout_r; + +`ifndef FPGA_SOURCE//{ +`ifndef DISABLE_SV_ASSERTION//{ +//synopsys translate_off +sirv_gnrl_xchecker # ( + .DW(1) +) sirv_gnrl_xchecker( + .i_dat(lden), + .clk (clk) +); +//synopsys translate_on +`endif//} +`endif//} + + +endmodule + +// =========================================================================== +// +// Description: +// Verilog module sirv_gnrl DFF with Load-enable and Reset +// Default reset value is input +// +// =========================================================================== + +module sirv_gnrl_dfflrd # ( + parameter DW = 32 +) ( + input [DW-1:0] init, + input lden, + input [DW-1:0] dnxt, + output [DW-1:0] qout, + + input clk, + input rst_n +); + +reg [DW-1:0] qout_r; + +always @(posedge clk or negedge rst_n) +begin : DFFLR_PROC + if (rst_n == 1'b0) + qout_r <= init; + else if (lden == 1'b1) + qout_r <= `dly dnxt; +end + +assign qout = qout_r; + +`ifndef FPGA_SOURCE//{ +`ifndef DISABLE_SV_ASSERTION//{ +//synopsys translate_off +sirv_gnrl_xchecker # ( + .DW(1) +) sirv_gnrl_xchecker( + .i_dat(lden), + .clk (clk) +); +//synopsys translate_on +`endif//} +`endif//} + + +endmodule + +// =========================================================================== +// +// Description: +// Verilog module sirv_gnrl DFF with Load-enable, no reset +// +// =========================================================================== + +module sirv_gnrl_dffl # ( + parameter DW = 32 +) ( + + input lden, + input [DW-1:0] dnxt, + output [DW-1:0] qout, + + input clk +); + +reg [DW-1:0] qout_r; + +always @(posedge clk) +begin : DFFL_PROC + if (lden == 1'b1) + qout_r <= `dly dnxt; +end + +assign qout = qout_r; + +`ifndef FPGA_SOURCE//{ +`ifndef DISABLE_SV_ASSERTION//{ +//synopsys translate_off +sirv_gnrl_xchecker # ( + .DW(1) +) sirv_gnrl_xchecker( + .i_dat(lden), + .clk (clk) +); +//synopsys translate_on +`endif//} +`endif//} + + +endmodule +// =========================================================================== +// +// Description: +// Verilog module sirv_gnrl DFF with Reset, no load-enable +// Default reset value is 1 +// +// =========================================================================== + +module sirv_gnrl_dffrs # ( + parameter DW = 32 +) ( + + input [DW-1:0] dnxt, + output [DW-1:0] qout, + + input clk, + input rst_n +); + +reg [DW-1:0] qout_r; + +always @(posedge clk or negedge rst_n) +begin : DFFRS_PROC + if (rst_n == 1'b0) + qout_r <= {DW{1'b1}}; + else + qout_r <= `dly dnxt; +end + +assign qout = qout_r; + +endmodule +// =========================================================================== +// +// Description: +// Verilog module sirv_gnrl DFF with Reset, no load-enable +// Default reset value is 0 +// +// =========================================================================== + +module sirv_gnrl_dffr # ( + parameter DW = 32 +) ( + + input [DW-1:0] dnxt, + output [DW-1:0] qout, + + input clk, + input rst_n +); + +reg [DW-1:0] qout_r; + +always @(posedge clk or negedge rst_n) +begin : DFFR_PROC + if (rst_n == 1'b0) + qout_r <= {DW{1'b0}}; + else + qout_r <= `dly dnxt; +end + +assign qout = qout_r; + +endmodule +// =========================================================================== +// +// Description: +// Verilog module for general latch +// +// =========================================================================== + +module sirv_gnrl_ltch # ( + parameter DW = 32 +) ( + + //input test_mode, + input lden, + input [DW-1:0] dnxt, + output [DW-1:0] qout +); + +reg [DW-1:0] qout_r; + +always @ * +begin : LTCH_PROC + if (lden == 1'b1) + qout_r <= dnxt; +end + +//assign qout = test_mode ? dnxt : qout_r; +assign qout = qout_r; + +`ifndef FPGA_SOURCE//{ +`ifndef DISABLE_SV_ASSERTION//{ +//synopsys translate_off +always_comb +begin + CHECK_THE_X_VALUE: + assert (lden !== 1'bx) + else $fatal ("\n Error: Oops, detected a X value!!! This should never happen. \n"); +end + +//synopsys translate_on +`endif//} +`endif//} + + +endmodule diff --git a/rtl/comm/sirv_gnrl_xchecker.v b/rtl/comm/sirv_gnrl_xchecker.v new file mode 100644 index 0000000..6e9df85 --- /dev/null +++ b/rtl/comm/sirv_gnrl_xchecker.v @@ -0,0 +1,49 @@ + /* + Copyright 2018-2020 Nuclei System Technology, Inc. + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + */ + + + +//===================================================================== +// +// Designer : Bob Hu +// +// Description: +// Verilog module for X checker +// +// ==================================================================== + + +`ifndef FPGA_SOURCE//{ +`ifndef DISABLE_SV_ASSERTION//{ +//synopsys translate_off +module sirv_gnrl_xchecker # ( + parameter DW = 32 +) ( + input [DW-1:0] i_dat, + input clk +); + + +CHECK_THE_X_VALUE: + assert property (@(posedge clk) + ((^(i_dat)) !== 1'bx) + ) + else $fatal ("\n Error: Oops, detected a X value!!! This should never happen. \n"); + +endmodule +//synopsys translate_on +`endif//} +`endif//} diff --git a/rtl/comm/syncer.v b/rtl/comm/syncer.v new file mode 100644 index 0000000..6d4e0a2 --- /dev/null +++ b/rtl/comm/syncer.v @@ -0,0 +1,58 @@ +//+FHDR-------------------------------------------------------------------------------------------------------- +// Company: +//----------------------------------------------------------------------------------------------------------------- +// File Name : syncer.v +// Department : +// Author : PWY +// Author's Tel : +//----------------------------------------------------------------------------------------------------------------- +// Relese History +// Version Date Author Description +// 0.1 2024-03-13 PWY AWG dedicated register file +// 0.2 2024-05-13 PWY +//----------------------------------------------------------------------------------------------------------------- +// Keywords : +// +//----------------------------------------------------------------------------------------------------------------- +// Parameter +// +//----------------------------------------------------------------------------------------------------------------- +// Purpose : +// +//----------------------------------------------------------------------------------------------------------------- +// Target Device: +// Tool versions: +//----------------------------------------------------------------------------------------------------------------- +// Reuse Issues +// Reset Strategy: +// Clock Domains: +// Critical Timing: +// Asynchronous I/F: +// Synthesizable (y/n): +// Other: +//-FHDR-------------------------------------------------------------------------------------------------------- + + +module syncer # ( + parameter width = 1 + ,parameter stage = 2 + ) + ( + input clk_d + ,input rstn_d + ,input [width-1:0] data_s + ,output [width-1:0] data_d +); + +generate + genvar i; + wire [width-1:0] data_temp[stage-1:0]; + sirv_gnrl_dffr #(width) data_temp0_dffr (data_s ,data_temp[0], clk_d, rstn_d); + for(i=1;i> 2) ? 1'b1 : 1'b0; +assign set0en = (rwaddr[15:2] == `SET0CR >> 2) ? 1'b1 : 1'b0; +assign set1en = (rwaddr[15:2] == `SET1CR >> 2) ? 1'b1 : 1'b0; +assign set2en = (rwaddr[15:2] == `SET2CR >> 2) ? 1'b1 : 1'b0; +assign set3en = (rwaddr[15:2] == `SET3CR >> 2) ? 1'b1 : 1'b0; +assign set4en = (rwaddr[15:2] == `SET4CR >> 2) ? 1'b1 : 1'b0; +assign set5en = (rwaddr[15:2] == `SET5CR >> 2) ? 1'b1 : 1'b0; +assign set6en = (rwaddr[15:2] == `SET6CR >> 2) ? 1'b1 : 1'b0; +assign set7en = (rwaddr[15:2] == `SET7CR >> 2) ? 1'b1 : 1'b0; +assign set8en = (rwaddr[15:2] == `SET8CR >> 2) ? 1'b1 : 1'b0; +assign set9en = (rwaddr[15:2] == `SET9CR >> 2) ? 1'b1 : 1'b0; +assign set10en = (rwaddr[15:2] == `SET10CR >> 2) ? 1'b1 : 1'b0; +assign set11en = (rwaddr[15:2] == `SET11CR >> 2) ? 1'b1 : 1'b0; +assign set12en = (rwaddr[15:2] == `SET12CR >> 2) ? 1'b1 : 1'b0; +assign set13en = (rwaddr[15:2] == `SET13CR >> 2) ? 1'b1 : 1'b0; +assign set14en = (rwaddr[15:2] == `SET14CR >> 2) ? 1'b1 : 1'b0; +assign set15en = (rwaddr[15:2] == `SET15CR >> 2) ? 1'b1 : 1'b0; +assign dacaddren = (rwaddr[15:2] == `DACADDR >> 2) ? 1'b1 : 1'b0; +assign dacdwen = (rwaddr[15:2] == `DACDW >> 2) ? 1'b1 : 1'b0; +assign dacrefen = (rwaddr[15:2] == `DACREF >> 2) ? 1'b1 : 1'b0; +assign prbsrst0en = (rwaddr[15:2] == `PRBSRST0 >> 2) ? 1'b1 : 1'b0; +assign prbsset0en = (rwaddr[15:2] == `PRBSSET0 >> 2) ? 1'b1 : 1'b0; +assign prbsrst1en = (rwaddr[15:2] == `PRBSRST1 >> 2) ? 1'b1 : 1'b0; +assign prbsset1en = (rwaddr[15:2] == `PRBSSET1 >> 2) ? 1'b1 : 1'b0; +assign prbsreven = (rwaddr[15:2] == `PRBSREV >> 2) ? 1'b1 : 1'b0; +assign calsigen = (rwaddr[15:2] == `CALSIG >> 2) ? 1'b1 : 1'b0; +assign calenden = (rwaddr[15:2] == `CALEND >> 2) ? 1'b1 : 1'b0; +assign calrstnen = (rwaddr[15:2] == `CALRSTN >> 2) ? 1'b1 : 1'b0; +assign caldivrstnen = (rwaddr[15:2] == `CALDIVRSTN >> 2) ? 1'b1 : 1'b0; + +// ------------------------------------------------------ +// -- Write enable signals +// +// Write enable signals for writable SW-registers. +// The write enable for each register is the ANDed +// result of the register enable and the input reg_wren +// ------------------------------------------------------ +assign prbswe = prbsen & wren; +assign set0we = set0en & wren; +assign set1we = set1en & wren; +assign set2we = set2en & wren; +assign set3we = set3en & wren; +assign set4we = set4en & wren; +assign set5we = set5en & wren; +assign set6we = set6en & wren; +assign set7we = set7en & wren; +assign set8we = set8en & wren; +assign set9we = set9en & wren; +assign set10we = set10en & wren; +assign set11we = set11en & wren; +assign set12we = set12en & wren; +assign set13we = set13en & wren; +assign set14we = set14en & wren; +assign set15we = set15en & wren; + +assign dacaddrwe = dacaddren & wren; +assign dacdwwe = dacdwen & wren; +assign dacrefwe = dacrefen & wren; + +assign prbsrst0we = prbsrst0en & wren; +assign prbsset0we = prbsset0en & wren; +assign prbsrst1we = prbsrst1en & wren; +assign prbsset1we = prbsset1en & wren; +assign prbsrevwe = prbsreven & wren; + +assign calsigwe = calsigen & wren; +assign calrstnwe = calrstnen & wren; +assign caldivrstnwe = caldivrstnen & wren; + + + + +// ------------------------------------------------------ +// -- prbs_reg Register +// +// Write prbs_reg for 'PRBS' : 32-bit register +// Register is split into the following bit fields +// +// [0] --> prbs_reg +// ------------------------------------------------------ +always @(posedge clk or negedge rstn) begin : PRBS_PROC + if(rstn == L) begin + prbs_reg <= L; + end + else begin + if(prbswe == H) begin + prbs_reg <= wrdata[0]; + end + else begin + prbs_reg <= prbs_reg; // hold current value + end + end +end + +// ------------------------------------------------------ +// -- set0_reg Register +// +// Write set0_reg for 'SET0' : 32-bit register +// Register is split into the following bit fields +// +// [14 : 0] --> set0_reg +// ------------------------------------------------------ +always @(posedge clk or negedge rstn) begin : SET0_PROC + if(rstn == L) begin + set0_reg <= 15'b100_0001_0011_1110; + end + else begin + if(set0we == H) begin + set0_reg <= wrdata[14 : 0]; + end + else begin + set0_reg <= set0_reg; // hold current value + end + end +end + +// ------------------------------------------------------ +// -- set1_reg Register +// +// Write set1_reg for 'SET1' : 32-bit register +// Register is split into the following bit fields +// +// [14 : 0] --> set1_reg +// ------------------------------------------------------ +always @(posedge clk or negedge rstn) begin : SET1_PROC + if(rstn == L) begin + set1_reg <= 15'b011_1001_0001_0000; + end + else begin + if(set1we == H) begin + set1_reg <= wrdata[14 : 0]; + end + else begin + set1_reg <= set1_reg; // hold current value + end + end +end + +// ------------------------------------------------------ +// -- set2_reg Register +// +// Write set2_reg for 'SET2' : 32-bit register +// Register is split into the following bit fields +// +// [14 : 0] --> set2_reg +// ------------------------------------------------------ +always @(posedge clk or negedge rstn) begin : SET2_PROC + if(rstn == L) begin + set2_reg <= 15'b111_1000_0000_1111; + end + else begin + if(set2we == H) begin + set2_reg <= wrdata[14 : 0]; + end + else begin + set2_reg <= set2_reg; // hold current value + end + end +end + +// ------------------------------------------------------ +// -- set3_reg Register +// +// Write set3_reg for 'SET3' : 32-bit register +// Register is split into the following bit fields +// +// [14 : 0] --> set3_reg +// ------------------------------------------------------ +always @(posedge clk or negedge rstn) begin : SET3_PROC + if(rstn == L) begin + set3_reg <= 15'b000_1010_1101_0100; + end + else begin + if(set3we == H) begin + set3_reg <= wrdata[14 : 0]; + end + else begin + set3_reg <= set3_reg; // hold current value + end + end +end + +// ------------------------------------------------------ +// -- set4_reg Register +// +// Write set4_reg for 'SET4' : 32-bit register +// Register is split into the following bit fields +// +// [14 : 0] --> set4_reg +// ------------------------------------------------------ +always @(posedge clk or negedge rstn) begin : SET4_PROC + if(rstn == L) begin + set4_reg <= 15'b000_0101_0110_1001; + end + else begin + if(set4we == H) begin + set4_reg <= wrdata[14 : 0]; + end + else begin + set4_reg <= set4_reg; // hold current value + end + end +end + +// ------------------------------------------------------ +// -- set5_reg Register +// +// Write set5_reg for 'SET5' : 32-bit register +// Register is split into the following bit fields +// +// [14 : 0] --> set5_reg +// ------------------------------------------------------ +always @(posedge clk or negedge rstn) begin : SET5_PROC + if(rstn == L) begin + set5_reg <= 15'b110_1111_0011_0001; + end + else begin + if(set5we == H) begin + set5_reg <= wrdata[14 : 0]; + end + else begin + set5_reg <= set5_reg; // hold current value + end + end +end + +// ------------------------------------------------------ +// -- set6_reg Register +// +// Write set6_reg for 'SET6' : 32-bit register +// Register is split into the following bit fields +// +// [14 : 0] --> set6_reg +// ------------------------------------------------------ +always @(posedge clk or negedge rstn) begin : SET6_PROC + if(rstn == L) begin + set6_reg <= 15'b101_1010_0011_1000; + end + else begin + if(set6we == H) begin + set6_reg <= wrdata[14 : 0]; + end + else begin + set6_reg <= set6_reg; // hold current value + end + end +end + +// ------------------------------------------------------ +// -- set7_reg Register +// +// Write set7_reg for 'SET7' : 32-bit register +// Register is split into the following bit fields +// +// [14 : 0] --> set7_reg +// ------------------------------------------------------ +always @(posedge clk or negedge rstn) begin : SET7_PROC + if(rstn == L) begin + set7_reg <= 15'b101_0110_0110_0000; + end + else begin + if(set7we == H) begin + set7_reg <= wrdata[14 : 0]; + end + else begin + set7_reg <= set7_reg; // hold current value + end + end +end + +// ------------------------------------------------------ +// -- set8_reg Register +// +// Write set0_reg for 'SET8' : 32-bit register +// Register is split into the following bit fields +// +// [14 : 0] --> set8_reg +// ------------------------------------------------------ +always @(posedge clk or negedge rstn) begin : SET8_PROC + if(rstn == L) begin + set8_reg <= 15'b100_1111_1000_0011; + end + else begin + if(set8we == H) begin + set8_reg <= wrdata[14 : 0]; + end + else begin + set8_reg <= set8_reg; // hold current value + end + end +end + +// ------------------------------------------------------ +// -- set9_reg Register +// +// Write set9_reg for 'SET0' : 32-bit register +// Register is split into the following bit fields +// +// [14 : 0] --> set9_reg +// ------------------------------------------------------ +always @(posedge clk or negedge rstn) begin : SET9_PROC + if(rstn == L) begin + set9_reg <= 15'b010_1110_1001_0101; + end + else begin + if(set9we == H) begin + set9_reg <= wrdata[14 : 0]; + end + else begin + set9_reg <= set9_reg; // hold current value + end + end +end + +// ------------------------------------------------------ +// -- set10_reg Register +// +// Write set10_reg for 'SET10' : 32-bit register +// Register is split into the following bit fields +// +// [14 : 0] --> set10_reg +// ------------------------------------------------------ +always @(posedge clk or negedge rstn) begin : SET10_PROC + if(rstn == L) begin + set10_reg <= 15'b101_0100_0001_0111; + end + else begin + if(set10we == H) begin + set10_reg <= wrdata[14 : 0]; + end + else begin + set10_reg <= set10_reg; // hold current value + end + end +end + +// ------------------------------------------------------ +// -- set11_reg Register +// +// Write set11_reg for 'SET11' : 32-bit register +// Register is split into the following bit fields +// +// [14 : 0] --> set11_reg +// ------------------------------------------------------ +always @(posedge clk or negedge rstn) begin : SET11_PROC + if(rstn == L) begin + set11_reg <= 15'b001_0110_1101_1110; + end + else begin + if(set11we == H) begin + set11_reg <= wrdata[14 : 0]; + end + else begin + set11_reg <= set11_reg; // hold current value + end + end +end + +// ------------------------------------------------------ +// -- set12_reg Register +// +// Write set12_reg for 'SET12' : 32-bit register +// Register is split into the following bit fields +// +// [14 : 0] --> set12_reg +// ------------------------------------------------------ +always @(posedge clk or negedge rstn) begin : SET12_PROC + if(rstn == L) begin + set12_reg <= 15'b000_1110_1110_1001; + end + else begin + if(set12we == H) begin + set12_reg <= wrdata[14 : 0]; + end + else begin + set12_reg <= set12_reg; // hold current value + end + end +end + +// ------------------------------------------------------ +// -- set13_reg Register +// +// Write set13_reg for 'SET13' : 32-bit register +// Register is split into the following bit fields +// +// [14 : 0] --> set13_reg +// ------------------------------------------------------ +always @(posedge clk or negedge rstn) begin : SET13_PROC + if(rstn == L) begin + set13_reg <= 15'b001_0110_1001_1100; + end + else begin + if(set13we == H) begin + set13_reg <= wrdata[14 : 0]; + end + else begin + set13_reg <= set13_reg; // hold current value + end + end +end + +// ------------------------------------------------------ +// -- set14_reg Register +// +// Write set14_reg for 'SET14' : 32-bit register +// Register is split into the following bit fields +// +// [14 : 0] --> set14_reg +// ------------------------------------------------------ +always @(posedge clk or negedge rstn) begin : SET14_PROC + if(rstn == L) begin + set14_reg <= 15'b001_0001_0011_0101; + end + else begin + if(set14we == H) begin + set14_reg <= wrdata[14 : 0]; + end + else begin + set14_reg <= set14_reg; // hold current value + end + end +end + +// ------------------------------------------------------ +// -- set15_reg Register +// +// Write set15_reg for 'SET15' : 32-bit register +// Register is split into the following bit fields +// +// [14 : 0] --> set15_reg +// ------------------------------------------------------ +always @(posedge clk or negedge rstn) begin : SET15_PROC + if(rstn == L) begin + set15_reg <= 15'b101_1101_1101_0001; + end + else begin + if(set15we == H) begin + set15_reg <= wrdata[14 : 0]; + end + else begin + set15_reg <= set15_reg; // hold current value + end + end +end + +// ------------------------------------------------------ +// -- dacaddr_reg Register +// +// Write dacaddr_reg for 'DACADDR' : 32-bit register +// Register is split into the following bit fields +// +// [2 : 0] --> dacaddr_reg +// ------------------------------------------------------ +always @(posedge clk or negedge rstn) begin : DACADDR_PROC + if(rstn == L) begin + dacaddr_reg <= 3'b000; + end + else begin + if(dacaddrwe == H) begin + dacaddr_reg <= wrdata[2 : 0]; + end + else begin + dacaddr_reg <= dacaddr_reg; // hold current value + end + end +end + +// ------------------------------------------------------ +// -- dacdw_reg Register +// +// Write dacdw_reg for 'DACDW' : 32-bit register +// Register is split into the following bit fields +// +// [2 : 0] --> dacdw_reg +// ------------------------------------------------------ +always @(posedge clk or negedge rstn) begin : DACDW_PROC + if(rstn == L) begin + dacdw_reg <= 3'b000; + end + else begin + if(dacdwwe == H) begin + dacdw_reg <= wrdata[2 : 0]; + end + else begin + dacdw_reg <= dacdw_reg; // hold current value + end + end +end + +// ------------------------------------------------------ +// -- dacref_reg Register +// +// Write dacref_reg for 'DACREF' : 32-bit register +// Register is split into the following bit fields +// +// [8 : 0] --> dacref_reg +// ------------------------------------------------------ +always @(posedge clk or negedge rstn) begin : DACREF_PROC + if(rstn == L) begin + dacref_reg <= 9'b0_1000_1000; + end + else begin + if(dacrefwe == H) begin + dacref_reg <= wrdata[8 : 0]; + end + else begin + dacref_reg <= dacref_reg; // hold current value + end + end +end + +// ------------------------------------------------------ +// -- prbsrst0_reg Register +// +// Write prbsrst0_reg for 'PRBSRST0' : 32-bit register +// Register is split into the following bit fields +// +// [16 : 0] --> prbsrst0_reg +// ------------------------------------------------------ +always @(posedge clk or negedge rstn) begin : PRBSRST0_PROC + if(rstn == L) begin + prbsrst0_reg <= 17'b0_0000_0001_1111_1111; + end + else begin + if(prbsrst0we == H) begin + prbsrst0_reg <= wrdata[16 : 0]; + end + else if(prbsrevwe) begin + prbsrst0_reg <= 17'b0_0000_0000_0000_0000; + end + else begin + prbsrst0_reg <= prbsrst0_reg; // hold current value + end + end +end + +// ------------------------------------------------------ +// -- prbsset0_reg Register +// +// Write prbsset0_reg for 'PRBSRST0' : 32-bit register +// Register is split into the following bit fields +// +// [16 : 0] --> prbsset0_reg +// ------------------------------------------------------ +always @(posedge clk or negedge rstn) begin : PRBSSET0_PROC + if(rstn == L) begin + prbsset0_reg <= 17'b1_1111_1110_0000_0000; + end + else begin + if(prbsset0we == H) begin + prbsset0_reg <= wrdata[16 : 0]; + end + else if(prbsrevwe) begin + prbsset0_reg <= 17'b0_0000_0000_0000_0000; + end + else begin + prbsset0_reg <= prbsset0_reg; // hold current value + end + end +end + +// ------------------------------------------------------ +// -- prbsrst1_reg Register +// +// Write prbsrst1_reg for 'PRBSRST1' : 32-bit register +// Register is split into the following bit fields +// +// [16 : 0] --> prbsrst1_reg +// ------------------------------------------------------ +always @(posedge clk or negedge rstn) begin : PRBSRST1_PROC + if(rstn == L) begin + prbsrst1_reg <= 17'b0_0000_0000_1111_1111; + end + else begin + if(prbsrst1we == H) begin + prbsrst1_reg <= wrdata[16 : 0]; + end + else if(prbsrevwe) begin + prbsrst1_reg <= 17'b0_0000_0000_0000_0000; + end + else begin + prbsrst1_reg <= prbsrst1_reg; // hold current value + end + end +end + +// ------------------------------------------------------ +// -- prbsset1_reg Register +// +// Write prbsset1_reg for 'PRBSRST1' : 32-bit register +// Register is split into the following bit fields +// +// [16 : 0] --> prbsset1_reg +// ------------------------------------------------------ +always @(posedge clk or negedge rstn) begin : PRBSSET1_PROC + if(rstn == L) begin + prbsset1_reg <= 17'b1_1111_1111_0000_0000; + end + else begin + if(prbsset1we == H) begin + prbsset1_reg <= wrdata[16 : 0]; + end + else if(prbsrevwe) begin + prbsset1_reg <= 17'b0_0000_0000_0000_0000; + end + else begin + prbsset1_reg <= prbsset1_reg; // hold current value + end + end +end + + + +// ------------------------------------------------------ +// -- calsig_reg Register +// +// Write calsig_reg for 'CALSIG' : 32-bit register +// Register is split into the following bit fields +// +// [0] --> calsig_reg +// ------------------------------------------------------ +always @(posedge clk or negedge rstn) begin : CALSIG_PROC + if(rstn == L) begin + calsig_reg <= 1'b0; + end + else begin + if(calsigwe == H) begin + calsig_reg <= wrdata[0]; + end + else begin + calsig_reg <= calsig_reg; // hold current value + end + end +end + +// ------------------------------------------------------ +// -- calend_reg Register +// +// Write calend_reg for 'CALEND' : 32-bit register +// Register is split into the following bit fields +// +// [0] --> calend_reg +// ------------------------------------------------------ +always @(posedge clk or negedge rstn) begin : CALEND_PROC + if(rstn == L) begin + calend_reg <= 1'b0; + end + else begin + calend_reg <= Cal_end; + end +end + +// ------------------------------------------------------ +// -- calrstn_reg Register +// +// Write calrstn_reg for 'CALRSTN' : 32-bit register +// Register is split into the following bit fields +// +// [0] --> calrstn_reg +// ------------------------------------------------------ +always @(posedge clk or negedge rstn) begin : CALRSTN_PROC + if(rstn == L) begin + calrstn_reg <= 1'b0; + end + else if(calrstnwe) begin + calrstn_reg <= wrdata[0]; + end + else begin + calrstn_reg <= calrstn_reg; + end +end + + +// ------------------------------------------------------ +// -- caldivrstn_reg Register +// +// Write caldivrstn_reg for 'CALDIVRSTN' : 32-bit register +// Register is split into the following bit fields +// +// [0] --> caldivrstn_reg +// ------------------------------------------------------ +always @(posedge clk or negedge rstn) begin : CALDIVRSTN_PROC + if(rstn == L) begin + caldivrstn_reg <= 1'b1; + end + else if(caldivrstnwe) begin + caldivrstn_reg <= wrdata[0]; + end + else begin + caldivrstn_reg <= caldivrstn_reg; + end +end + + +// ------------------------------------------------------ +// -- Read data mux +// +// -- The data from the selected register is +// -- placed on a zero-padded 32-bit read data bus. +// ------------------------------------------------------ +always @(*) begin : RDDATA_PROC + rddata_reg = {32{1'b0}}; + if(prbsen == H ) rddata_reg[0 ] = prbs_reg ; + if(set0en == H ) rddata_reg[14:0] = set0_reg ; + if(set1en == H ) rddata_reg[14:0] = set1_reg ; + if(set2en == H ) rddata_reg[14:0] = set2_reg ; + if(set3en == H ) rddata_reg[14:0] = set3_reg ; + if(set4en == H ) rddata_reg[14:0] = set4_reg ; + if(set5en == H ) rddata_reg[14:0] = set5_reg ; + if(set6en == H ) rddata_reg[14:0] = set6_reg ; + if(set7en == H ) rddata_reg[14:0] = set7_reg ; + if(set8en == H ) rddata_reg[14:0] = set8_reg ; + if(set9en == H ) rddata_reg[14:0] = set9_reg ; + if(set10en == H ) rddata_reg[14:0] = set10_reg ; + if(set11en == H ) rddata_reg[14:0] = set11_reg ; + if(set12en == H ) rddata_reg[14:0] = set12_reg ; + if(set13en == H ) rddata_reg[14:0] = set13_reg ; + if(set14en == H ) rddata_reg[14:0] = set14_reg ; + if(set15en == H ) rddata_reg[14:0] = set15_reg ; + + if(dacaddren == H ) rddata_reg[2 :0] = dacaddr_reg ; + if(dacdwen == H ) rddata_reg[2 :0] = dacdw_reg ; + if(dacrefen == H ) rddata_reg[8 :0] = dacref_reg ; + + if(prbsrst0en == H ) rddata_reg[16:0] = prbsrst0_reg ; + if(prbsset0en == H ) rddata_reg[16:0] = prbsset0_reg ; + if(prbsrst1en == H ) rddata_reg[16:0] = prbsrst1_reg ; + if(prbsset1en == H ) rddata_reg[16:0] = prbsset1_reg ; + + if(calsigen == H ) rddata_reg[0 ] = calsig_reg ; + if(calenden == H ) rddata_reg[0 ] = calend_reg ; + if(calrstnen == H ) rddata_reg[0 ] = calrstn_reg ; + if(caldivrstnen == H ) rddata_reg[0 ] = caldivrstn_reg ; +end + +//rddata +sirv_gnrl_dffr #(32) rddata_dffr (rddata_reg, rddata, clk, rstn); + +// ------------------------------------------------------ +// -- Output signals assignment +// ------------------------------------------------------ +assign Prbs = prbs_reg ; +assign Set0 = set0_reg ; +assign Set1 = set1_reg ; +assign Set2 = set2_reg ; +assign Set3 = set3_reg ; +assign Set4 = set4_reg ; +assign Set5 = set5_reg ; +assign Set6 = set6_reg ; +assign Set7 = set7_reg ; +assign Set8 = set8_reg ; +assign Set9 = set9_reg ; +assign Set10 = set10_reg ; +assign Set11 = set11_reg ; +assign Set12 = set12_reg ; +assign Set13 = set13_reg ; +assign Set14 = set14_reg ; +assign Set15 = set15_reg ; + +assign Dac_addr = dacaddr_reg ; +assign Dac_dw = dacdw_reg ; +assign Dac_ref = dacref_reg ; + +assign Prbs_rst0 = prbsrst0_reg ; +assign Prbs_set0 = prbsset0_reg ; +assign Prbs_rst1 = prbsrst1_reg ; +assign Prbs_set1 = prbsset1_reg ; + +assign Cal_sig = calsig_reg ; +assign Cal_rstn = calrstn_reg ; + +assign Cal_div_rstn = caldivrstn_reg ; + +endmodule + +`undef PRBSCR +`undef SET0CR +`undef SET1CR +`undef SET2CR +`undef SET3CR +`undef SET4CR +`undef SET5CR +`undef SET6CR +`undef SET7CR +`undef SET8CR +`undef SET9CR +`undef SET10CR +`undef SET11CR +`undef SET12CR +`undef SET13CR +`undef SET14CR +`undef SET15CR + +`undef DACADDR +`undef DACDW +`undef DACREF + +`undef PRBSRST0 +`undef PRBSSET0 +`undef PRBSRST1 +`undef PRBSSET1 +`undef PRBSREV + +`undef CALSIG +`undef CALEND +`undef CALRSTN +`undef CALDIVRSTN diff --git a/rtl/debug/debug_sample.sv b/rtl/debug/debug_sample.sv new file mode 100644 index 0000000..6073b17 --- /dev/null +++ b/rtl/debug/debug_sample.sv @@ -0,0 +1,233 @@ +//+FHDR-------------------------------------------------------------------------------------------------------- +// Company: +//----------------------------------------------------------------------------------------------------------------- +// File Name : debug_sample.v +// Department : +// Author : PWY +// Author's Tel : +//----------------------------------------------------------------------------------------------------------------- +// Relese History +// Version Date Author Description +// 0.1 2024-03-13 PWY Debugging data sampling +//----------------------------------------------------------------------------------------------------------------- +// Keywords : +// +//----------------------------------------------------------------------------------------------------------------- +// Parameter +// +//----------------------------------------------------------------------------------------------------------------- +// Purpose : +// +//----------------------------------------------------------------------------------------------------------------- +// Target Device: +// Tool versions: +//----------------------------------------------------------------------------------------------------------------- +// Reuse Issues +// Reset Strategy: +// Clock Domains: +// Critical Timing: +// Asynchronous I/F: +// Synthesizable (y/n): +// Other: +//-FHDR-------------------------------------------------------------------------------------------------------- + +module debug_sampling ( + //system port + input clk // System Main Clock + ,input rst_n // Spi Reset active low + //---------------from ctrl regfile------------------------------------ + ,input debug_enable //active high + ,input debug_data_sel //1'b0-->mod;1'b1-->dsp + ,input [3 :0] debug_ch_sel //4'b0001-->ch0;4'b0010-->ch1; + //4'b0100-->ch2;4'b1000-->ch3; + //---------------to system regfile------------------------------------ + ,output debug_update //active high + //---------------connect mod------------------------------------------ + ,input [15 :0] ch0_mod_data_i + ,input [15 :0] ch0_mod_data_q + ,input ch0_mod_vld + ,input [15 :0] ch1_mod_data_i + ,input [15 :0] ch1_mod_data_q + ,input ch1_mod_vld + ,input [15 :0] ch2_mod_data_i + ,input [15 :0] ch2_mod_data_q + ,input ch2_mod_vld + ,input [15 :0] ch3_mod_data_i + ,input [15 :0] ch3_mod_data_q + ,input ch3_mod_vld + //---------------connect mod------------------------------------------ + ,input [15 :0] ch0_dsp_data [15:0] + ,input ch0_dsp_vld + ,input [15 :0] ch1_dsp_data [15:0] + ,input ch1_dsp_vld + ,input [15 :0] ch2_dsp_data [15:0] + ,input ch2_dsp_vld + ,input [15 :0] ch3_dsp_data [15:0] + ,input ch3_dsp_vld + //---------------debug memory mod------------------------------------------ + ,output [11 :0] debug_rwaddr + ,output [255:0] debug_wrdata + ,output [31 :0] debug_bwen + ,output debug_wren + ,output debug_cen +); + + +// +logic mod_vld; +logic dsp_vld; + +//---------------addr gen---------------------------------------------------- + + + +wire end_cnt_flag; + +wire [9 :0] cnt_c; + +wire add_cnt = debug_enable & ((~debug_data_sel & mod_vld) | (debug_data_sel & dsp_vld)) & ~end_cnt_flag; + +wire end_cnt = add_cnt & ((~debug_data_sel & cnt_c == 10'd1023) | (debug_data_sel & cnt_c ==9'd127)); + +wire end_cnt_flag_w = end_cnt ? 1'b1 : + ~debug_enable ? 1'b0 : 1'b0; +sirv_gnrl_dfflr #(1) end_cnt_flag_dfflr ((end_cnt | ~debug_enable), end_cnt_flag_w, end_cnt_flag, clk, rst_n); + +wire [9 :0] cnt_n = ~debug_enable ? 10'd0 : + end_cnt ? cnt_c : + add_cnt ? cnt_c + 1'b1 : + cnt_c ; + + +sirv_gnrl_dffr #(10) cnt_c_dffr (cnt_n, cnt_c, clk, rst_n); + +//---------------mod Data integration------------------------------------------ + +assign mod_vld = debug_ch_sel[0] & ch0_mod_vld + | debug_ch_sel[1] & ch1_mod_vld + | debug_ch_sel[2] & ch2_mod_vld + | debug_ch_sel[3] & ch3_mod_vld ; + +wire [31:0] mod_data = {32{debug_ch_sel[0]}} & {ch0_mod_data_i,ch0_mod_data_q} + | {32{debug_ch_sel[1]}} & {ch1_mod_data_i,ch1_mod_data_q} + | {32{debug_ch_sel[2]}} & {ch2_mod_data_i,ch2_mod_data_q} + | {32{debug_ch_sel[3]}} & {ch3_mod_data_i,ch3_mod_data_q} ; + + + + +logic [255:0] mod_data_c; +logic [255:0] mod_data_n; + +assign mod_data_n = add_cnt ? {mod_data,mod_data_c[255:32]} : + mod_data_c ; + +wire [255:0] mod_wrdata = mod_data_c ; +sirv_gnrl_dffr #(256) mod_data_c_dffr (mod_data_n, mod_data_c, clk, rst_n); + +//active low +wire mod_cen_w = ~((cnt_c[2:0] == 3'h7) & add_cnt); +wire mod_cen; +sirv_gnrl_dffrs #(1) mod_cen_dffrs (mod_cen_w, mod_cen, clk, rst_n); + +wire [11:0] mod_addr ; + +sirv_gnrl_dffr #(12) mod_addr_dffr ({cnt_c,2'b00}, mod_addr, clk, rst_n); + +//---------------dsp Data integration------------------------------------------ +assign dsp_vld = debug_ch_sel[0] & ch0_dsp_vld + | debug_ch_sel[1] & ch1_dsp_vld + | debug_ch_sel[2] & ch2_dsp_vld + | debug_ch_sel[3] & ch3_dsp_vld ; + +wire [255:0] dsp_data = debug_ch_sel[0] ? { ch0_dsp_data[15] + ,ch0_dsp_data[14] + ,ch0_dsp_data[13] + ,ch0_dsp_data[12] + ,ch0_dsp_data[11] + ,ch0_dsp_data[10] + ,ch0_dsp_data[9 ] + ,ch0_dsp_data[8 ] + ,ch0_dsp_data[7 ] + ,ch0_dsp_data[6 ] + ,ch0_dsp_data[5 ] + ,ch0_dsp_data[4 ] + ,ch0_dsp_data[3 ] + ,ch0_dsp_data[2 ] + ,ch0_dsp_data[1 ] + ,ch0_dsp_data[0 ]} : + debug_ch_sel[1] ? { ch1_dsp_data[15] + ,ch1_dsp_data[14] + ,ch1_dsp_data[13] + ,ch1_dsp_data[12] + ,ch1_dsp_data[11] + ,ch1_dsp_data[10] + ,ch1_dsp_data[9 ] + ,ch1_dsp_data[8 ] + ,ch1_dsp_data[7 ] + ,ch1_dsp_data[6 ] + ,ch1_dsp_data[5 ] + ,ch1_dsp_data[4 ] + ,ch1_dsp_data[3 ] + ,ch1_dsp_data[2 ] + ,ch1_dsp_data[1 ] + ,ch1_dsp_data[0 ]} : + debug_ch_sel[2] ? { ch2_dsp_data[15] + ,ch2_dsp_data[14] + ,ch2_dsp_data[13] + ,ch2_dsp_data[12] + ,ch2_dsp_data[11] + ,ch2_dsp_data[10] + ,ch2_dsp_data[9 ] + ,ch2_dsp_data[8 ] + ,ch2_dsp_data[7 ] + ,ch2_dsp_data[6 ] + ,ch2_dsp_data[5 ] + ,ch2_dsp_data[4 ] + ,ch2_dsp_data[3 ] + ,ch2_dsp_data[2 ] + ,ch2_dsp_data[1 ] + ,ch2_dsp_data[0 ]} : + debug_ch_sel[3] ? { ch3_dsp_data[15] + ,ch3_dsp_data[14] + ,ch3_dsp_data[13] + ,ch3_dsp_data[12] + ,ch3_dsp_data[11] + ,ch3_dsp_data[10] + ,ch3_dsp_data[9 ] + ,ch3_dsp_data[8 ] + ,ch3_dsp_data[7 ] + ,ch3_dsp_data[6 ] + ,ch3_dsp_data[5 ] + ,ch3_dsp_data[4 ] + ,ch3_dsp_data[3 ] + ,ch3_dsp_data[2 ] + ,ch3_dsp_data[1 ] + ,ch3_dsp_data[0 ]} : 255'h0; + +wire [11 :0] dsp_addr = {cnt_c[6:0],5'b00000} ; +wire dsp_cen = ~add_cnt ; //active low +wire [255:0] dsp_wrdata = dsp_data ; + +//////////////////////////////////////////////////////////////////////////////////////////////////// +// data & cmd mux +//////////////////////////////////////////////////////////////////////////////////////////////////// +wire [11 :0] mem_addr = debug_data_sel ? dsp_addr : mod_addr ; +wire mem_cen = debug_data_sel ? dsp_cen : mod_cen ; //active low +wire [255:0] mem_wrdata = debug_data_sel ? dsp_wrdata : mod_wrdata ; + + +sirv_gnrl_dffr #(12) mem_addr_dffr (mem_addr, debug_rwaddr, clk, rst_n); + +sirv_gnrl_dffr #(1) mem_cen_dffr (mem_cen, debug_cen, clk, rst_n); + +sirv_gnrl_dffr #(256) mem_wrdata_dffr (mem_wrdata, debug_wrdata, clk, rst_n); + + +assign debug_bwen = 32'b0; +assign debug_wren = 1'b0; + +//debug_update +sirv_gnrl_dffr #(1) debug_update_dffr (end_cnt, debug_update, clk, rst_n); + +endmodule \ No newline at end of file diff --git a/rtl/debug/debug_top.sv b/rtl/debug/debug_top.sv new file mode 100644 index 0000000..3e3c6aa --- /dev/null +++ b/rtl/debug/debug_top.sv @@ -0,0 +1,162 @@ +//+FHDR-------------------------------------------------------------------------------------------------------- +// Company: +//----------------------------------------------------------------------------------------------------------------- +// File Name : debug_top.v +// Department : +// Author : PWY +// Author's Tel : +//----------------------------------------------------------------------------------------------------------------- +// Relese History +// Version Date Author Description +// 0.1 2024-04-13 PWY debug top-level +// 0.2 2024-06-20 PWY dbg_sramb_wben = dbg_sram_out.wben -> dbg_sramb_wben = ~dbg_sram_out.wben +//----------------------------------------------------------------------------------------------------------------- +// Keywords : +// +//----------------------------------------------------------------------------------------------------------------- +// Parameter +// +//----------------------------------------------------------------------------------------------------------------- +// Purpose : +// +//----------------------------------------------------------------------------------------------------------------- +// Target Device: +// Tool versions: +//----------------------------------------------------------------------------------------------------------------- +// Reuse Issues +// Reset Strategy: +// Clock Domains: +// Critical Timing: +// Asynchronous I/F: +// Synthesizable (y/n): +// Other: +//-FHDR-------------------------------------------------------------------------------------------------------- + +module debug_top ( + //system port + input clk // System Main Clock + ,input rst_n // Spi Reset active low + //---------------from ctrl regfile------------------------------------ + ,input debug_enable //active high + ,input debug_data_sel //1'b0-->mod;1'b1-->dsp + ,input [3 :0] debug_ch_sel //2'b00-->ch0;2'b01-->ch1;2'b10-->ch2;2'b11-->ch3; + //---------------to system regfile------------------------------------ + ,output debug_update //active high + //---------------connect mod------------------------------------------ + ,input [15 :0] ch0_mod_data_i + ,input [15 :0] ch0_mod_data_q + ,input ch0_mod_vld + ,input [15 :0] ch1_mod_data_i + ,input [15 :0] ch1_mod_data_q + ,input ch1_mod_vld + ,input [15 :0] ch2_mod_data_i + ,input [15 :0] ch2_mod_data_q + ,input ch2_mod_vld + ,input [15 :0] ch3_mod_data_i + ,input [15 :0] ch3_mod_data_q + ,input ch3_mod_vld + //---------------connect mod------------------------------------------ + ,input [15 :0] ch0_dsp_data [15:0] + ,input ch0_dsp_vld + ,input [15 :0] ch1_dsp_data [15:0] + ,input ch1_dsp_vld + ,input [15 :0] ch2_dsp_data [15:0] + ,input ch2_dsp_vld + ,input [15 :0] ch3_dsp_data [15:0] + ,input ch3_dsp_vld + //---------------connect SPI bus -------------------------------------- + ,sram_if.slave dbg_sram_in +); + + +//--------------------------------------------------------------------------------------------- +//debug sampling +//--------------------------------------------------------------------------------------------- + +wire [11 :0] debug_rwaddr ; +wire [255:0] debug_wrdata ; +wire [31 :0] debug_bwen ; +wire debug_wren ; +wire debug_cen ; + +debug_sampling U_debug_sampling ( + .clk ( clk ) + ,.rst_n ( rst_n ) + ,.debug_enable ( debug_enable ) + ,.debug_data_sel ( debug_data_sel ) + ,.debug_ch_sel ( debug_ch_sel ) + ,.debug_update ( debug_update ) + ,.ch0_mod_data_i ( ch0_mod_data_i ) + ,.ch0_mod_data_q ( ch0_mod_data_q ) + ,.ch0_mod_vld ( ch0_mod_vld ) + ,.ch1_mod_data_i ( ch1_mod_data_i ) + ,.ch1_mod_data_q ( ch1_mod_data_q ) + ,.ch1_mod_vld ( ch1_mod_vld ) + ,.ch2_mod_data_i ( ch2_mod_data_i ) + ,.ch2_mod_data_q ( ch2_mod_data_q ) + ,.ch2_mod_vld ( ch2_mod_vld ) + ,.ch3_mod_data_i ( ch3_mod_data_i ) + ,.ch3_mod_data_q ( ch3_mod_data_q ) + ,.ch3_mod_vld ( ch3_mod_vld ) + ,.ch0_dsp_data ( ch0_dsp_data ) + ,.ch0_dsp_vld ( ch0_dsp_vld ) + ,.ch1_dsp_data ( ch1_dsp_data ) + ,.ch1_dsp_vld ( ch1_dsp_vld ) + ,.ch2_dsp_data ( ch2_dsp_data ) + ,.ch2_dsp_vld ( ch2_dsp_vld ) + ,.ch3_dsp_data ( ch3_dsp_data ) + ,.ch3_dsp_vld ( ch3_dsp_vld ) + ,.debug_rwaddr ( debug_rwaddr ) + ,.debug_wrdata ( debug_wrdata ) + ,.debug_bwen ( debug_bwen ) + ,.debug_wren ( debug_wren ) + ,.debug_cen ( debug_cen ) +); + +//--------------------------------------------------------------------------------------------- +//debug SRAM (512w x 128d) +//--------------------------------------------------------------------------------------------- +sram_if #(12,256) dbg_sram_out(clk); +wire [255:0] dbg_sramb_dout ; +wire [11 :0] dbg_sramb_addr = dbg_sram_out.addr[11:0] ; +wire [255:0] dbg_sramb_din = dbg_sram_out.din ; +wire [31 :0] dbg_sramb_wben = ~dbg_sram_out.wben ; +wire dbg_sramb_wren = ~dbg_sram_out.wren & dbg_sram_out.rden ; +wire dbg_sramb_cen = ~(dbg_sram_out.wren | dbg_sram_out.rden); +assign dbg_sram_out.dout = dbg_sramb_dout; + + +dpram #( + .DATAWIDTH ( 256 ) + ,.ADDRWIDTH ( 12 ) + ) U_dbg_sram ( + .PortClk ( clk ) + ,.PortAAddr ( debug_rwaddr ) + ,.PortADataIn ( debug_wrdata ) + ,.PortAWriteEnable ( debug_wren ) + ,.PortAChipEnable ( debug_cen ) + ,.PortAByteWriteEnable ( debug_bwen ) + ,.PortADataOut ( ) + ,.PortBAddr ( dbg_sramb_addr ) + ,.PortBDataIn ( dbg_sramb_din ) + ,.PortBWriteEnable ( dbg_sramb_wren ) + ,.PortBChipEnable ( dbg_sramb_cen ) + ,.PortBByteWriteEnable ( dbg_sramb_wben ) + ,.PortBDataOut ( dbg_sramb_dout ) +); + +//--------------------------------------------------------------------------------------------- +//debug SRAM (512w x 128d) +//--------------------------------------------------------------------------------------------- +sram_dmux_w #( + .ADDR_WIDTH ( 12 ) + ,.DATA_WIDTH_I ( 32 ) + ,.DATA_WIDTH_O ( 256 ) + ) U_sram_dmux_w ( + .clk ( clk ) + ,.rst_n ( rst_n ) + ,.port_in ( dbg_sram_in ) + ,.port_out ( dbg_sram_out ) + ); + +endmodule diff --git a/rtl/define/chip_define.v b/rtl/define/chip_define.v new file mode 100644 index 0000000..01c8c87 --- /dev/null +++ b/rtl/define/chip_define.v @@ -0,0 +1,23 @@ + +//Defining Memory Types + +//`define BEHAVIOR_SIM +//`define XILINX_FPGA +`define TSMC_IC +//Is the chip a 4-channel one? +//`define CHANNEL_IS_FOUR 1 + + +//Whether to instantiate the XY-channel +`define CHANNEL_XY_ON 1 +//Whether to instantiate the Z-channel +`define CHANNEL_Z_ON 1 + +//Setting the Number of SPI Slave Devices +`define SLVNUM 26 +//Whether SPI Bus Commands Are Buffered +`define SPIBUS_CMD_REG 1 +//Whether SPI Bus Readout Are Buffered +`define SPIBUS_OUT_REG 0 +//Whether Mod mux dout Are Buffered +//`define MODDOUT_MUX_REG diff --git a/rtl/define/chip_undefine.v b/rtl/define/chip_undefine.v new file mode 100644 index 0000000..8bf7060 --- /dev/null +++ b/rtl/define/chip_undefine.v @@ -0,0 +1,22 @@ + +//`undef BEHAVIOR_SIM +//`undef XILINX_FPGA +`undef TSMC_IC +//Is the chip a 4-channel one? +//`undef CHANNEL_IS_FOUR + + +//Whether to instantiate the XY-channel +`undef CHANNEL_XY_ON +//Whether to instantiate the Z-channel +`undef CHANNEL_Z_ON + +//Setting the Number of SPI Slave Devices +`undef SLVNUM +//Whether SPI Bus Commands Are Buffered +`undef SPIBUS_CMD_REG +//Whether SPI Bus Readout Are Buffered +`undef SPIBUS_OUT_REG + +//Whether Mod mux dout Are Buffered +//`undef MODDOUT_MUX_REG diff --git a/rtl/dem/DAC_DEM.v b/rtl/dem/DAC_DEM.v new file mode 100644 index 0000000..a148253 --- /dev/null +++ b/rtl/dem/DAC_DEM.v @@ -0,0 +1,181 @@ +module DAC_DEM ( clk_in, + data_in, + prbs_en, + set, + DEM_LSB_OUT, + DEM_ISB_OUT, + DEM_MSB_OUT +); + + + +input clk_in, prbs_en; +input [15:0] data_in; +input [14:0] set; +output [8:0] DEM_LSB_OUT; +output [6:0] DEM_ISB_OUT; +output [14:0] DEM_MSB_OUT; + + + + + + +reg [14:0]r_shift_data; + +always @(posedge clk_in or negedge prbs_en) +begin + if(!prbs_en) + + r_shift_data <=set; + + else + + begin + + r_shift_data[0] <=r_shift_data[14]^r_shift_data[13]; + + r_shift_data[1] <= r_shift_data[0]; + + r_shift_data[2] <= r_shift_data[1]; + + r_shift_data[3] <= r_shift_data[2]; + + r_shift_data[4] <= r_shift_data[3]; + + r_shift_data[5] <= r_shift_data[4]; + + r_shift_data[6] <= r_shift_data[5]; + + r_shift_data[7] <= r_shift_data[6]; + + r_shift_data[8] <= r_shift_data[7]; + + r_shift_data[9] <= r_shift_data[8]; + + r_shift_data[10] <= r_shift_data[9]; + + r_shift_data[11] <= r_shift_data[10]; + + r_shift_data[12] <= r_shift_data[11]; + + r_shift_data[13] <= r_shift_data[12]; + + r_shift_data[14] <= r_shift_data[13]; + + end +end + +wire [3:0]dd; +wire [2:0]ddi; +assign dd = {r_shift_data[0],r_shift_data[5], r_shift_data[10],r_shift_data[14]}; + +assign ddi = { r_shift_data[3], r_shift_data[7], r_shift_data[12]}; + + + +reg [14:0] r_MSB_BUF0; + +always @(posedge clk_in) + +begin + + case(dd[3:0]) + + 4'd0: r_MSB_BUF0 <= {data_in[15],data_in[15],data_in[15],data_in[15],data_in[15],data_in[15],data_in[15],data_in[15],data_in[14],data_in[14],data_in[14],data_in[14],data_in[13],data_in[13],data_in[12]}; + + 4'd1: r_MSB_BUF0 <= {data_in[15],data_in[15],data_in[15],data_in[15],data_in[15],data_in[15],data_in[15],data_in[14],data_in[14],data_in[14],data_in[14],data_in[13],data_in[13],data_in[12],data_in[15]}; + + 4'd2: r_MSB_BUF0 <= {data_in[15],data_in[15],data_in[15],data_in[15],data_in[15],data_in[15],data_in[14],data_in[14],data_in[14],data_in[14],data_in[13],data_in[13],data_in[12],data_in[15],data_in[15]}; + + 4'd3: r_MSB_BUF0 <= {data_in[15],data_in[15],data_in[15],data_in[15],data_in[15],data_in[14],data_in[14],data_in[14],data_in[14],data_in[13],data_in[13],data_in[12],data_in[15],data_in[15],data_in[15]}; + + 4'd4: r_MSB_BUF0 <= {data_in[15],data_in[15],data_in[15],data_in[15],data_in[14],data_in[14],data_in[14],data_in[14],data_in[13],data_in[13],data_in[12],data_in[15],data_in[15],data_in[15],data_in[15]}; + + 4'd5: r_MSB_BUF0 <= {data_in[15],data_in[15],data_in[15],data_in[14],data_in[14],data_in[14],data_in[14],data_in[13],data_in[13],data_in[12],data_in[15],data_in[15],data_in[15],data_in[15],data_in[15]}; + + 4'd6: r_MSB_BUF0 <= {data_in[15],data_in[15],data_in[14],data_in[14],data_in[14],data_in[14],data_in[13],data_in[13],data_in[12],data_in[15],data_in[15],data_in[15],data_in[15],data_in[15],data_in[15]}; + + 4'd7: r_MSB_BUF0 <= {data_in[15],data_in[14],data_in[14],data_in[14],data_in[14],data_in[13],data_in[13],data_in[12],data_in[15],data_in[15],data_in[15],data_in[15],data_in[15],data_in[15],data_in[15]}; + + 4'd8: r_MSB_BUF0 <= {data_in[14],data_in[14],data_in[14],data_in[14],data_in[13],data_in[13],data_in[12],data_in[15],data_in[15],data_in[15],data_in[15],data_in[15],data_in[15],data_in[15],data_in[15]}; + + 4'd9: r_MSB_BUF0 <= {data_in[14],data_in[14],data_in[14],data_in[13],data_in[13],data_in[12],data_in[15],data_in[15],data_in[15],data_in[15],data_in[15],data_in[15],data_in[15],data_in[15],data_in[14]}; + + 4'd10: r_MSB_BUF0 <= {data_in[14],data_in[14],data_in[13],data_in[13],data_in[12],data_in[15],data_in[15],data_in[15],data_in[15],data_in[15],data_in[15],data_in[15],data_in[15],data_in[14],data_in[14]}; + + 4'd11: r_MSB_BUF0 <= {data_in[14],data_in[13],data_in[13],data_in[12],data_in[15],data_in[15],data_in[15],data_in[15],data_in[15],data_in[15],data_in[15],data_in[15],data_in[14],data_in[14],data_in[14]}; + + 4'd12: r_MSB_BUF0 <= {data_in[13],data_in[13],data_in[12],data_in[15],data_in[15],data_in[15],data_in[15],data_in[15],data_in[15],data_in[15],data_in[15],data_in[14],data_in[14],data_in[14],data_in[14]}; + + 4'd13: r_MSB_BUF0 <= {data_in[13],data_in[12],data_in[15],data_in[15],data_in[15],data_in[15],data_in[15],data_in[15],data_in[15],data_in[15],data_in[14],data_in[14],data_in[14],data_in[14],data_in[13]}; + + 4'd14: r_MSB_BUF0 <= {data_in[12],data_in[15],data_in[15],data_in[15],data_in[15],data_in[15],data_in[15],data_in[15],data_in[15],data_in[14],data_in[14],data_in[14],data_in[14],data_in[13],data_in[13]}; + + 4'd15: r_MSB_BUF0 <= {data_in[15],data_in[15],data_in[15],data_in[15],data_in[15],data_in[15],data_in[15],data_in[15],data_in[14],data_in[14],data_in[14],data_in[14],data_in[13],data_in[13],data_in[12]}; + + + endcase + +end + + +reg [6:0] r_ISB_BUF0; + +always @(posedge clk_in) + +begin + + case(ddi[2:0]) + + 3'd0: r_ISB_BUF0 <= {data_in[11],data_in[11],data_in[11],data_in[11],data_in[10],data_in[10],data_in[9]}; + + 3'd1: r_ISB_BUF0 <= {data_in[11],data_in[11],data_in[11],data_in[10],data_in[10],data_in[9],data_in[11]}; + + 3'd2: r_ISB_BUF0 <= {data_in[11],data_in[11],data_in[10],data_in[10],data_in[9],data_in[11],data_in[11]}; + + 3'd3: r_ISB_BUF0 <= {data_in[11],data_in[10],data_in[10],data_in[9],data_in[11],data_in[11],data_in[11]}; + + 3'd4: r_ISB_BUF0 <= {data_in[10],data_in[10],data_in[9],data_in[11],data_in[11],data_in[11],data_in[11]}; + + 3'd5: r_ISB_BUF0 <= {data_in[10],data_in[9],data_in[11],data_in[11],data_in[11],data_in[11],data_in[10]}; + + 3'd6: r_ISB_BUF0 <= {data_in[9],data_in[11],data_in[11],data_in[11],data_in[11],data_in[10],data_in[10]}; + + 3'd7: r_ISB_BUF0 <= {data_in[11],data_in[11],data_in[11],data_in[11],data_in[10],data_in[10],data_in[9]}; + + endcase + +end + + + + + + + + +reg [8:0] r_LSB_BUF0; + +always @(posedge clk_in) + +begin + + r_LSB_BUF0 <= {data_in[8],data_in[7],data_in[6],data_in[5],data_in[4],data_in[3],data_in[2],data_in[1],data_in[0]}; + +end + + + +assign DEM_LSB_OUT = r_LSB_BUF0; + +assign DEM_ISB_OUT = r_ISB_BUF0; + +assign DEM_MSB_OUT = r_MSB_BUF0; + + + + + +endmodule + diff --git a/rtl/dem/DAC_DEM_16.v b/rtl/dem/DAC_DEM_16.v new file mode 100644 index 0000000..ff98a9c --- /dev/null +++ b/rtl/dem/DAC_DEM_16.v @@ -0,0 +1,202 @@ +module DAC_DEM_16 (CLK_IN,prbs_en, + +set0,set1,set2,set3,set4,set5,set6,set7,set8,set9,set10,set11,set12,set13,set14,set15, + +DATA_IN0,DATA_IN1,DATA_IN2,DATA_IN3,DATA_IN4,DATA_IN5,DATA_IN6,DATA_IN7,DATA_IN8,DATA_IN9,DATA_IN10,DATA_IN11,DATA_IN12,DATA_IN13,DATA_IN14,DATA_IN15, + +A_DEM_MSB_OUT0,A_DEM_MSB_OUT1,A_DEM_MSB_OUT2,A_DEM_MSB_OUT3,A_DEM_MSB_OUT4,A_DEM_MSB_OUT5,A_DEM_MSB_OUT6,A_DEM_MSB_OUT7, + +B_DEM_MSB_OUT0,B_DEM_MSB_OUT1,B_DEM_MSB_OUT2,B_DEM_MSB_OUT3,B_DEM_MSB_OUT4,B_DEM_MSB_OUT5,B_DEM_MSB_OUT6,B_DEM_MSB_OUT7, + +A_DEM_ISB_OUT0,A_DEM_ISB_OUT1,A_DEM_ISB_OUT2,A_DEM_ISB_OUT3,A_DEM_ISB_OUT4,A_DEM_ISB_OUT5,A_DEM_ISB_OUT6,A_DEM_ISB_OUT7, + +B_DEM_ISB_OUT0,B_DEM_ISB_OUT1,B_DEM_ISB_OUT2,B_DEM_ISB_OUT3,B_DEM_ISB_OUT4,B_DEM_ISB_OUT5,B_DEM_ISB_OUT6,B_DEM_ISB_OUT7, + +A_DEM_LSB_OUT0,A_DEM_LSB_OUT1,A_DEM_LSB_OUT2,A_DEM_LSB_OUT3,A_DEM_LSB_OUT4,A_DEM_LSB_OUT5,A_DEM_LSB_OUT6,A_DEM_LSB_OUT7, + +B_DEM_LSB_OUT0,B_DEM_LSB_OUT1,B_DEM_LSB_OUT2,B_DEM_LSB_OUT3,B_DEM_LSB_OUT4,B_DEM_LSB_OUT5,B_DEM_LSB_OUT6,B_DEM_LSB_OUT7 +); + +input CLK_IN; + +input prbs_en; + +input [14:0] set0,set1,set2,set3,set4,set5,set6,set7,set8,set9,set10,set11,set12,set13,set14,set15; + +input [15:0] DATA_IN0,DATA_IN1,DATA_IN2,DATA_IN3,DATA_IN4,DATA_IN5,DATA_IN6,DATA_IN7,DATA_IN8,DATA_IN9,DATA_IN10,DATA_IN11,DATA_IN12,DATA_IN13,DATA_IN14,DATA_IN15; + +output [14:0] A_DEM_MSB_OUT0,A_DEM_MSB_OUT1,A_DEM_MSB_OUT2,A_DEM_MSB_OUT3,A_DEM_MSB_OUT4,A_DEM_MSB_OUT5,A_DEM_MSB_OUT6,A_DEM_MSB_OUT7; + +output [14:0] B_DEM_MSB_OUT0,B_DEM_MSB_OUT1,B_DEM_MSB_OUT2,B_DEM_MSB_OUT3,B_DEM_MSB_OUT4,B_DEM_MSB_OUT5,B_DEM_MSB_OUT6,B_DEM_MSB_OUT7; + +output [6:0] A_DEM_ISB_OUT0,A_DEM_ISB_OUT1,A_DEM_ISB_OUT2,A_DEM_ISB_OUT3,A_DEM_ISB_OUT4,A_DEM_ISB_OUT5,A_DEM_ISB_OUT6,A_DEM_ISB_OUT7; + +output [6:0] B_DEM_ISB_OUT0,B_DEM_ISB_OUT1,B_DEM_ISB_OUT2,B_DEM_ISB_OUT3,B_DEM_ISB_OUT4,B_DEM_ISB_OUT5,B_DEM_ISB_OUT6,B_DEM_ISB_OUT7; + +output [8:0] A_DEM_LSB_OUT0,A_DEM_LSB_OUT1,A_DEM_LSB_OUT2,A_DEM_LSB_OUT3,A_DEM_LSB_OUT4,A_DEM_LSB_OUT5,A_DEM_LSB_OUT6,A_DEM_LSB_OUT7; + +output [8:0] B_DEM_LSB_OUT0,B_DEM_LSB_OUT1,B_DEM_LSB_OUT2,B_DEM_LSB_OUT3,B_DEM_LSB_OUT4,B_DEM_LSB_OUT5,B_DEM_LSB_OUT6,B_DEM_LSB_OUT7; + + DAC_DEM A_DEM_0( + .clk_in (CLK_IN), + .data_in (DATA_IN0), + .prbs_en (prbs_en), + .set (set0), + .DEM_LSB_OUT (A_DEM_LSB_OUT0), + .DEM_ISB_OUT (A_DEM_ISB_OUT0), + .DEM_MSB_OUT (A_DEM_MSB_OUT0) +); + + DAC_DEM A_DEM_1( + .clk_in (CLK_IN), + .data_in (DATA_IN1), + .prbs_en (prbs_en), + .set (set1), + .DEM_LSB_OUT (A_DEM_LSB_OUT1), + .DEM_ISB_OUT (A_DEM_ISB_OUT1), + .DEM_MSB_OUT (A_DEM_MSB_OUT1) +); + + DAC_DEM A_DEM_2( + .clk_in (CLK_IN), + .data_in (DATA_IN2), + .prbs_en (prbs_en), + .set (set2), + .DEM_LSB_OUT (A_DEM_LSB_OUT2), + .DEM_ISB_OUT (A_DEM_ISB_OUT2), + .DEM_MSB_OUT (A_DEM_MSB_OUT2) +); + + DAC_DEM A_DEM_3( + .clk_in (CLK_IN), + .data_in (DATA_IN3), + .prbs_en (prbs_en), + .set (set3), + .DEM_LSB_OUT (A_DEM_LSB_OUT3), + .DEM_ISB_OUT (A_DEM_ISB_OUT3), + .DEM_MSB_OUT (A_DEM_MSB_OUT3) +); + + DAC_DEM A_DEM_4( + .clk_in (CLK_IN), + .data_in (DATA_IN4), + .prbs_en (prbs_en), + .set (set4), + .DEM_LSB_OUT (A_DEM_LSB_OUT4), + .DEM_ISB_OUT (A_DEM_ISB_OUT4), + .DEM_MSB_OUT (A_DEM_MSB_OUT4) +); + + DAC_DEM A_DEM_5( + .clk_in (CLK_IN), + .data_in (DATA_IN5), + .prbs_en (prbs_en), + .set (set5), + .DEM_LSB_OUT (A_DEM_LSB_OUT5), + .DEM_ISB_OUT (A_DEM_ISB_OUT5), + .DEM_MSB_OUT (A_DEM_MSB_OUT5) +); + + DAC_DEM A_DEM_6( + .clk_in (CLK_IN), + .data_in (DATA_IN6), + .prbs_en (prbs_en), + .set (set6), + .DEM_LSB_OUT (A_DEM_LSB_OUT6), + .DEM_ISB_OUT (A_DEM_ISB_OUT6), + .DEM_MSB_OUT (A_DEM_MSB_OUT6) +); + + DAC_DEM A_DEM_7( + .clk_in (CLK_IN), + .data_in (DATA_IN7), + .prbs_en (prbs_en), + .set (set7), + .DEM_LSB_OUT (A_DEM_LSB_OUT7), + .DEM_ISB_OUT (A_DEM_ISB_OUT7), + .DEM_MSB_OUT (A_DEM_MSB_OUT7) +); + + DAC_DEM B_DEM_0( + .clk_in (CLK_IN), + .data_in (DATA_IN8), + .prbs_en (prbs_en), + .set (set8), + .DEM_LSB_OUT (B_DEM_LSB_OUT0), + .DEM_ISB_OUT (B_DEM_ISB_OUT0), + .DEM_MSB_OUT (B_DEM_MSB_OUT0) +); + + DAC_DEM B_DEM_1( + .clk_in (CLK_IN), + .data_in (DATA_IN9), + .prbs_en (prbs_en), + .set (set9), + .DEM_LSB_OUT (B_DEM_LSB_OUT1), + .DEM_ISB_OUT (B_DEM_ISB_OUT1), + .DEM_MSB_OUT (B_DEM_MSB_OUT1) +); + + DAC_DEM B_DEM_2( + .clk_in (CLK_IN), + .data_in (DATA_IN10), + .prbs_en (prbs_en), + .set (set10), + .DEM_LSB_OUT (B_DEM_LSB_OUT2), + .DEM_ISB_OUT (B_DEM_ISB_OUT2), + .DEM_MSB_OUT (B_DEM_MSB_OUT2) +); + + DAC_DEM B_DEM_3( + .clk_in (CLK_IN), + .data_in (DATA_IN11), + .prbs_en (prbs_en), + .set (set11), + .DEM_LSB_OUT (B_DEM_LSB_OUT3), + .DEM_ISB_OUT (B_DEM_ISB_OUT3), + .DEM_MSB_OUT (B_DEM_MSB_OUT3) +); + + DAC_DEM B_DEM_4( + .clk_in (CLK_IN), + .data_in (DATA_IN12), + .prbs_en (prbs_en), + .set (set12), + .DEM_LSB_OUT (B_DEM_LSB_OUT4), + .DEM_ISB_OUT (B_DEM_ISB_OUT4), + .DEM_MSB_OUT (B_DEM_MSB_OUT4) +); + + DAC_DEM B_DEM_5( + .clk_in (CLK_IN), + .data_in (DATA_IN13), + .prbs_en (prbs_en), + .set (set13), + .DEM_LSB_OUT (B_DEM_LSB_OUT5), + .DEM_ISB_OUT (B_DEM_ISB_OUT5), + .DEM_MSB_OUT (B_DEM_MSB_OUT5) +); + + DAC_DEM B_DEM_6( + .clk_in (CLK_IN), + .data_in (DATA_IN14), + .prbs_en (prbs_en), + .set (set14), + .DEM_LSB_OUT (B_DEM_LSB_OUT6), + .DEM_ISB_OUT (B_DEM_ISB_OUT6), + .DEM_MSB_OUT (B_DEM_MSB_OUT6) +); + + DAC_DEM B_DEM_7( + .clk_in (CLK_IN), + .data_in (DATA_IN15), + .prbs_en (prbs_en), + .set (set15), + .DEM_LSB_OUT (B_DEM_LSB_OUT7), + .DEM_ISB_OUT (B_DEM_ISB_OUT7), + .DEM_MSB_OUT (B_DEM_MSB_OUT7) +); + + +endmodule + diff --git a/rtl/dem/DAC_DEM_4.v b/rtl/dem/DAC_DEM_4.v new file mode 100644 index 0000000..c4073cb --- /dev/null +++ b/rtl/dem/DAC_DEM_4.v @@ -0,0 +1,83 @@ +module DAC_DEM_4 (CLK_IN,prbs_en, + +set0,set1,set2,set3, + +DATA_IN0,DATA_IN1,DATA_IN2,DATA_IN3, + +DEM_MSB_OUT0,DEM_MSB_OUT1,DEM_MSB_OUT2,DEM_MSB_OUT3, + + + +DEM_ISB_OUT0,DEM_ISB_OUT1,DEM_ISB_OUT2,DEM_ISB_OUT3, + + + +DEM_LSB_OUT0,DEM_LSB_OUT1,DEM_LSB_OUT2,DEM_LSB_OUT3 + + +); + +input CLK_IN; + +input prbs_en; + +input [14:0] set0,set1,set2,set3; + +input [15:0] DATA_IN0,DATA_IN1,DATA_IN2,DATA_IN3; + +output [14:0] DEM_MSB_OUT0,DEM_MSB_OUT1,DEM_MSB_OUT2,DEM_MSB_OUT3; + + + +output [6:0] DEM_ISB_OUT0,DEM_ISB_OUT1,DEM_ISB_OUT2,DEM_ISB_OUT3; + + + +output [8:0] DEM_LSB_OUT0,DEM_LSB_OUT1,DEM_LSB_OUT2,DEM_LSB_OUT3; + + + + DAC_DEM A_DEM_0( + .clk_in (CLK_IN), + .data_in (DATA_IN0), + .prbs_en (prbs_en), + .set (set0), + .DEM_LSB_OUT (DEM_LSB_OUT0), + .DEM_ISB_OUT (DEM_ISB_OUT0), + .DEM_MSB_OUT (DEM_MSB_OUT0) +); + + DAC_DEM A_DEM_1( + .clk_in (CLK_IN), + .data_in (DATA_IN1), + .prbs_en (prbs_en), + .set (set1), + .DEM_LSB_OUT (DEM_LSB_OUT1), + .DEM_ISB_OUT (DEM_ISB_OUT1), + .DEM_MSB_OUT (DEM_MSB_OUT1) +); + + DAC_DEM A_DEM_2( + .clk_in (CLK_IN), + .data_in (DATA_IN2), + .prbs_en (prbs_en), + .set (set2), + .DEM_LSB_OUT (DEM_LSB_OUT2), + .DEM_ISB_OUT (DEM_ISB_OUT2), + .DEM_MSB_OUT (DEM_MSB_OUT2) +); + + DAC_DEM A_DEM_3( + .clk_in (CLK_IN), + .data_in (DATA_IN3), + .prbs_en (prbs_en), + .set (set3), + .DEM_LSB_OUT (DEM_LSB_OUT3), + .DEM_ISB_OUT (DEM_ISB_OUT3), + .DEM_MSB_OUT (DEM_MSB_OUT3) +); + + + +endmodule + diff --git a/rtl/io/iopad.v b/rtl/io/iopad.v new file mode 100644 index 0000000..5bfab9f --- /dev/null +++ b/rtl/io/iopad.v @@ -0,0 +1,253 @@ +//+FHDR-------------------------------------------------------------------------------------------------------- +// Company: +//----------------------------------------------------------------------------------------------------------------- +// File Name : iopad.v +// Department : +// Author : pwy +// Author's Tel : +//----------------------------------------------------------------------------------------------------------------- +// Relese History +// Version Date Author Description +// 1.2 2024-06-12 pwy Integrate a digital module and two SPI modules with PLL +//----------------------------------------------------------------------------------------------------------------- +// Keywords : +// +//----------------------------------------------------------------------------------------------------------------- +// Parameter +// +//----------------------------------------------------------------------------------------------------------------- +// Purpose : +// +//----------------------------------------------------------------------------------------------------------------- +// Target Device: +// Tool versions: +//----------------------------------------------------------------------------------------------------------------- +// Reuse Issues +// Reset Strategy: +// Clock Domains: +// Critical Timing: +// Asynchronous I/F: +// Synthesizable (y/n): +// Other: +//-FHDR-------------------------------------------------------------------------------------------------------- +`include "../define/chip_define.v" +module iopad ( + //+++++++++++++++++++++++++++++++++++++++++++++// + // PAD Strat // + //+++++++++++++++++++++++++++++++++++++++++++++// + input PI_async_rstn // hardware Reset, active low + //sync + ,input PI_sync_in // Chip synchronization signal input, high pulse valid + ,output PO_sync_out // Chip synchronization signal output, high pulse valid + //Feedback signal + ,input [1 :0] PI_ch0_feedback // Ch0 Feedback signals from the readout chip + `ifdef CHANNEL_IS_FOUR + ,input [1 :0] PI_ch1_feedback // Ch1 Feedback signals from the readout chip + ,input [1 :0] PI_ch2_feedback // Ch2 Feedback signals from the readout chip + ,input [1 :0] PI_ch3_feedback // Ch3 Feedback signals from the readout chip + `endif + //config chip id + ,input [4 :0] PI_cfgid // During power-on initialization, the IO configuration + // values are read as the chip ID number + //spi port + ,input PI_sclk // Spi Clock + ,input PI_csn // Spi Chip Select active low + ,input PI_mosi // Spi Mosi + ,output PO_miso // Spi Miso + //irq + ,output PO_irq // Interrupt signal in the chip, high level active + //+++++++++++++++++++++++++++++++++++++++++++++// + // PAD End // + //+++++++++++++++++++++++++++++++++++++++++++++// + + //+++++++++++++++++++++++++++++++++++++++++++++// + // Internal signal Start // + //+++++++++++++++++++++++++++++++++++++++++++++// + ,output async_rstn // hardware Reset, active low + //sync + ,output sync_in // Chip synchronization signal input, high pulse valid + ,input sync_out // Chip synchronization signal output, high pulse valid + //Feedback signal + ,output [1 :0] ch0_feedback // Ch0 Feedback signals from the readout chip + `ifdef CHANNEL_IS_FOUR + ,output [1 :0] ch1_feedback // Ch1 Feedback signals from the readout chip + ,output [1 :0] ch2_feedback // Ch2 Feedback signals from the readout chip + ,output [1 :0] ch3_feedback // Ch3 Feedback signals from the readout chip + `endif + //config chip id + ,output [4 :0] cfgid // During power-on initialization, the IO configuration + // values are read as the chip ID number + //spi port + ,output sclk // Spi Clock + ,output csn // Spi Chip Select active low + ,output mosi // Spi Mosi + ,input miso // Spi Miso + ,input oen // Spi Miso output enable + //irq + ,input irq // Interrupt signal in the chip, high level active +); + +`ifdef TSMC_IC +//++++++++++++++++++++++++++++++++++++++++++++++++++// +// ASIC PAD --> TSMC // +//++++++++++++++++++++++++++++++++++++++++++++++++++// +//PI_async_rstn +PDUW04SDGZ_V_G PDUW08SDGZ_V_G_async_rstn ( + .I ( 1'b0 ) + ,.OEN ( 1'b1 ) + ,.REN ( 1'b0 ) + ,.PAD ( PI_async_rstn ) + ,.C ( async_rstn ) +); + +//sync_in +PDDW04SDGZ_V_G PDDW04SDGZ_V_G_sync_in ( + .I ( 1'b0 ) + ,.OEN ( 1'b1 ) + ,.REN ( 1'b0 ) + ,.PAD ( PI_sync_in ) + ,.C ( sync_in ) +); + +//sync_out +PDDW04SDGZ_V_G PDDW08SDGZ_V_G_sync_out ( + .I ( sync_out ) + ,.OEN ( 1'b0 ) + ,.REN ( 1'b0 ) + ,.PAD ( PO_sync_out ) + ,.C ( ) +); + +//ch0_feedback +PDDW04SDGZ_V_G PDDW04SDGZ_V_G_ch0_feedback0 ( + .I ( 1'b0 ) + ,.OEN ( 1'b1 ) + ,.REN ( 1'b0 ) + ,.PAD ( PI_ch0_feedback[0] ) + ,.C ( ch0_feedback[0] ) +); + +PDDW04SDGZ_V_G PDDW04SDGZ_V_G_ch0_feedback1 ( + .I ( 1'b0 ) + ,.OEN ( 1'b1 ) + ,.REN ( 1'b0 ) + ,.PAD ( PI_ch0_feedback[1] ) + ,.C ( ch0_feedback[1] ) +); + +//cfgid +PDDW04SDGZ_V_G PDDW04DGZ_V_G_cfgid0 ( + .I ( 1'b0 ) + ,.OEN ( 1'b1 ) + ,.REN ( 1'b0 ) + ,.PAD ( PI_cfgid[0] ) + ,.C ( cfgid[0] ) +); + +PDDW04SDGZ_V_G PDDW04DGZ_V_G_cfgid1 ( + .I ( 1'b0 ) + ,.OEN ( 1'b1 ) + ,.REN ( 1'b0 ) + ,.PAD ( PI_cfgid[1] ) + ,.C ( cfgid[1] ) +); + +PDDW04SDGZ_V_G PDDW04DGZ_V_G_cfgid2 ( + .I ( 1'b0 ) + ,.OEN ( 1'b1 ) + ,.REN ( 1'b0 ) + ,.PAD ( PI_cfgid[2] ) + ,.C ( cfgid[2] ) +); + +PDDW04SDGZ_V_G PDDW04DGZ_V_G_cfgid3 ( + .I ( 1'b0 ) + ,.OEN ( 1'b1 ) + ,.REN ( 1'b0 ) + ,.PAD ( PI_cfgid[3] ) + ,.C ( cfgid[3] ) +); + +PDDW04SDGZ_V_G PDDW04DGZ_V_G_cfgid4 ( + .I ( 1'b0 ) + ,.OEN ( 1'b1 ) + ,.REN ( 1'b0 ) + ,.PAD ( PI_cfgid[4] ) + ,.C ( cfgid[4] ) +); + +//sclk +PDUW04SDGZ_V_G PDUW04SDGZ_V_G_sclk ( + .I ( 1'b0 ) + ,.OEN ( 1'b1 ) + ,.REN ( 1'b0 ) + ,.PAD ( PI_sclk ) + ,.C ( sclk ) +); + +//csn +PDUW04SDGZ_V_G PDUW04SDGZ_V_G_csn ( + .I ( 1'b0 ) + ,.OEN ( 1'b1 ) + ,.REN ( 1'b0 ) + ,.PAD ( PI_csn ) + ,.C ( csn ) +); + +//mosi +PDDW08SDGZ_V_G PDUW08SDGZ_V_G_mosi ( + .I ( 1'b0 ) + ,.OEN ( 1'b1 ) + ,.REN ( 1'b0 ) + ,.PAD ( PI_mosi ) + ,.C ( mosi ) +); + +//miso +PDUW08SDGZ_V_G PDUW08SDGZ_V_G_miso ( + .I ( miso ) + ,.OEN ( oen ) + ,.REN ( 1'b0 ) + ,.PAD ( PO_miso ) + ,.C ( ) +); + +//irq +PDDW08SDGZ_V_G PDDW08SDGZ_V_G_irq ( + .I ( irq ) + ,.OEN ( 1'b0 ) + ,.REN ( 1'b0 ) + ,.PAD ( PO_irq ) + ,.C ( ) +); + +`elsif XILINX_FPGA +//++++++++++++++++++++++++++++++++++++++++++++++++++// +// FPGA PAD --> Xlinx // +//++++++++++++++++++++++++++++++++++++++++++++++++++// +//async_rstn +assign async_rstn = PI_async_rstn ; +//sync_in +assign sync_in = PI_sync_in ; +//sync_out +assign PO_sync_out = sync_out ; +//Feedback signal +assign ch0_feedback = PI_ch0_feedback ; +`ifdef CHANNEL_IS_FOUR +assign ch1_feedback = PI_ch1_feedback ; +assign ch2_feedback = PI_ch2_feedback ; +assign ch3_feedback = PI_ch3_feedback ; +`endif +//config chip id +assign cfgid = PI_cfgid ; +//spi port +assign sclk = PI_sclk ; +assign csn = PI_csn ; +assign mosi = PI_mosi ; +assign PO_miso = oen ? 1'bz : miso ; +//irq +assign PO_irq = irq ; +`endif + +endmodule +`include "../define/chip_undefine.v" \ No newline at end of file diff --git a/rtl/io/tphn28hpcpgv18.v b/rtl/io/tphn28hpcpgv18.v new file mode 100644 index 0000000..916bd30 --- /dev/null +++ b/rtl/io/tphn28hpcpgv18.v @@ -0,0 +1,2509 @@ +///////////////////////////////////////////////////////////////////////////////////////////// +/// TSMC Library/IP Product +/// Filename: tphn28hpcpgv18.v +/// Technology: CLN28HT +/// Product Type: Standard I/O +/// Product Name: tphn28hpcpgv18 +/// Version: 110a +//////////////////////////////////////////////////////////////////////////////////////////// +//// +/// STATEMENT OF USE +/// +/// This information contains confidential and proprietary information of TSMC. +/// No part of this information may be reproduced, transmitted, transcribed, +/// stored in a retrieval system, or translated into any human or computer +/// language, in any form or by any means, electronic, mechanical, magnetic, +/// optical, chemical, manual, or otherwise, without the prior written permission +/// of TSMC. This information was prepared for informational purpose and is for +/// use by TSMC's customers only. TSMC reserves the right to make changes in the +/// information at any time and without notice. +/// +//////////////////////////////////////////////////////////////////////////////////////////// +`timescale 1ns/10ps + +`celldefine +module PCLAMP_G (VDDESD,VSSESD); + inout VDDESD,VSSESD; + tran (VDDESD,VDDESD); + tran (VSSESD,VSSESD); +endmodule +`endcelldefine + +`celldefine +module PCLAMPC_H_G (VDDESD, VSSESD); + inout VDDESD, VSSESD; + tran (VDDESD, VDDESD); + tran (VSSESD, VSSESD); +endmodule +`endcelldefine + +`celldefine +module PCLAMPC_V_G (VDDESD, VSSESD); + inout VDDESD, VSSESD; + tran (VDDESD, VDDESD); + tran (VSSESD, VSSESD); +endmodule +`endcelldefine + +`celldefine +module PDB3A_H_G (AIO); + inout AIO; + tran (AIO,AIO); +endmodule +`endcelldefine + +`celldefine +module PDB3A_V_G (AIO); + inout AIO; + tran (AIO,AIO); +endmodule +`endcelldefine + +`celldefine +module PDB3AC_H_G (AIO); + inout AIO; + tran (AIO,AIO); +endmodule +`endcelldefine + +`celldefine +module PDB3AC_V_G (AIO); + inout AIO; + tran (AIO,AIO); +endmodule +`endcelldefine + +`celldefine +module PDDW04DGZ_H_G (I, OEN, REN, PAD, C); + input I, OEN, REN; + inout PAD; + output C; + + wire MG, pull_pad, pull_c; + parameter PullTime = 10000; + + bufif0 (PAD_q, I, OEN); + pmos (MG, PAD_q, 1'b0); + bufif1 (weak1, weak0) (PAD_i, 1'b0, pull_pad); + pmos (MG, PAD_i, 1'b0); + pmos (PAD, MG, 1'b0); + bufif1 (C_buf, PAD, 1'b1); + bufif1 (weak0,weak1) (C_buf, 1'b0, pull_c); + buf (C, C_buf); + not (RE, REN); + buf #(PullTime,0) (pull_pad, RE); + buf (pull_c, RE); + +`ifdef TETRAMAX +`else + always @(PAD) begin + if (PAD === 1'bx && !$test$plusargs("bus_conflict_off") && $countdrivers(PAD)) + $display("%t ++BUS CONFLICT++ : %m", $realtime); + end + + specify + (I => PAD)=(0, 0); + (OEN => PAD)=(0, 0, 0, 0, 0, 0); + (PAD => C)=(0, 0); + endspecify +`endif +endmodule +`endcelldefine + +`celldefine +module PDDW04DGZ_V_G (I, OEN, REN, PAD, C); + input I, OEN, REN; + inout PAD; + output C; + + wire MG, pull_pad, pull_c; + parameter PullTime = 10000; + + bufif0 (PAD_q, I, OEN); + pmos (MG, PAD_q, 1'b0); + bufif1 (weak1, weak0) (PAD_i, 1'b0, pull_pad); + pmos (MG, PAD_i, 1'b0); + pmos (PAD, MG, 1'b0); + bufif1 (C_buf, PAD, 1'b1); + bufif1 (weak0,weak1) (C_buf, 1'b0, pull_c); + buf (C, C_buf); + not (RE, REN); + buf #(PullTime,0) (pull_pad, RE); + buf (pull_c, RE); + +`ifdef TETRAMAX +`else + always @(PAD) begin + if (PAD === 1'bx && !$test$plusargs("bus_conflict_off") && $countdrivers(PAD)) + $display("%t ++BUS CONFLICT++ : %m", $realtime); + end + + specify + (I => PAD)=(0, 0); + (OEN => PAD)=(0, 0, 0, 0, 0, 0); + (PAD => C)=(0, 0); + endspecify +`endif +endmodule +`endcelldefine + +`celldefine +module PDDW04SDGZ_H_G (I, OEN, REN, PAD, C); + input I, OEN, REN; + inout PAD; + output C; + + wire MG, pull_pad, pull_c; + parameter PullTime = 10000; + + bufif0 (PAD_q, I, OEN); + pmos (MG, PAD_q, 1'b0); + bufif1 (weak1, weak0) (PAD_i, 1'b0, pull_pad); + pmos (MG, PAD_i, 1'b0); + pmos (PAD, MG, 1'b0); + bufif1 (C_buf, PAD, 1'b1); + bufif1 (weak0,weak1) (C_buf, 1'b0, pull_c); + buf (C, C_buf); + not (RE, REN); + buf #(PullTime,0) (pull_pad, RE); + buf (pull_c, RE); + +`ifdef TETRAMAX +`else + always @(PAD) begin + if (PAD === 1'bx && !$test$plusargs("bus_conflict_off") && $countdrivers(PAD)) + $display("%t ++BUS CONFLICT++ : %m", $realtime); + end + + specify + (I => PAD)=(0, 0); + (OEN => PAD)=(0, 0, 0, 0, 0, 0); + (PAD => C)=(0, 0); + endspecify +`endif +endmodule +`endcelldefine + +`celldefine +module PDDW04SDGZ_V_G (I, OEN, REN, PAD, C); + input I, OEN, REN; + inout PAD; + output C; + + wire MG, pull_pad, pull_c; + parameter PullTime = 10000; + + bufif0 (PAD_q, I, OEN); + pmos (MG, PAD_q, 1'b0); + bufif1 (weak1, weak0) (PAD_i, 1'b0, pull_pad); + pmos (MG, PAD_i, 1'b0); + pmos (PAD, MG, 1'b0); + bufif1 (C_buf, PAD, 1'b1); + bufif1 (weak0,weak1) (C_buf, 1'b0, pull_c); + buf (C, C_buf); + not (RE, REN); + buf #(PullTime,0) (pull_pad, RE); + buf (pull_c, RE); + +`ifdef TETRAMAX +`else + always @(PAD) begin + if (PAD === 1'bx && !$test$plusargs("bus_conflict_off") && $countdrivers(PAD)) + $display("%t ++BUS CONFLICT++ : %m", $realtime); + end + + specify + (I => PAD)=(0, 0); + (OEN => PAD)=(0, 0, 0, 0, 0, 0); + (PAD => C)=(0, 0); + endspecify +`endif +endmodule +`endcelldefine + +`celldefine +module PDDW08DGZ_H_G (I, OEN, REN, PAD, C); + input I, OEN, REN; + inout PAD; + output C; + + wire MG, pull_pad, pull_c; + parameter PullTime = 10000; + + bufif0 (PAD_q, I, OEN); + pmos (MG, PAD_q, 1'b0); + bufif1 (weak1, weak0) (PAD_i, 1'b0, pull_pad); + pmos (MG, PAD_i, 1'b0); + pmos (PAD, MG, 1'b0); + bufif1 (C_buf, PAD, 1'b1); + bufif1 (weak0,weak1) (C_buf, 1'b0, pull_c); + buf (C, C_buf); + not (RE, REN); + buf #(PullTime,0) (pull_pad, RE); + buf (pull_c, RE); + +`ifdef TETRAMAX +`else + always @(PAD) begin + if (PAD === 1'bx && !$test$plusargs("bus_conflict_off") && $countdrivers(PAD)) + $display("%t ++BUS CONFLICT++ : %m", $realtime); + end + + specify + (I => PAD)=(0, 0); + (OEN => PAD)=(0, 0, 0, 0, 0, 0); + (PAD => C)=(0, 0); + endspecify +`endif +endmodule +`endcelldefine + +`celldefine +module PDDW08DGZ_V_G (I, OEN, REN, PAD, C); + input I, OEN, REN; + inout PAD; + output C; + + wire MG, pull_pad, pull_c; + parameter PullTime = 10000; + + bufif0 (PAD_q, I, OEN); + pmos (MG, PAD_q, 1'b0); + bufif1 (weak1, weak0) (PAD_i, 1'b0, pull_pad); + pmos (MG, PAD_i, 1'b0); + pmos (PAD, MG, 1'b0); + bufif1 (C_buf, PAD, 1'b1); + bufif1 (weak0,weak1) (C_buf, 1'b0, pull_c); + buf (C, C_buf); + not (RE, REN); + buf #(PullTime,0) (pull_pad, RE); + buf (pull_c, RE); + +`ifdef TETRAMAX +`else + always @(PAD) begin + if (PAD === 1'bx && !$test$plusargs("bus_conflict_off") && $countdrivers(PAD)) + $display("%t ++BUS CONFLICT++ : %m", $realtime); + end + + specify + (I => PAD)=(0, 0); + (OEN => PAD)=(0, 0, 0, 0, 0, 0); + (PAD => C)=(0, 0); + endspecify +`endif +endmodule +`endcelldefine + +`celldefine +module PDDW08SDGZ_H_G (I, OEN, REN, PAD, C); + input I, OEN, REN; + inout PAD; + output C; + + wire MG, pull_pad, pull_c; + parameter PullTime = 10000; + + bufif0 (PAD_q, I, OEN); + pmos (MG, PAD_q, 1'b0); + bufif1 (weak1, weak0) (PAD_i, 1'b0, pull_pad); + pmos (MG, PAD_i, 1'b0); + pmos (PAD, MG, 1'b0); + bufif1 (C_buf, PAD, 1'b1); + bufif1 (weak0,weak1) (C_buf, 1'b0, pull_c); + buf (C, C_buf); + not (RE, REN); + buf #(PullTime,0) (pull_pad, RE); + buf (pull_c, RE); + +`ifdef TETRAMAX +`else + always @(PAD) begin + if (PAD === 1'bx && !$test$plusargs("bus_conflict_off") && $countdrivers(PAD)) + $display("%t ++BUS CONFLICT++ : %m", $realtime); + end + + specify + (I => PAD)=(0, 0); + (OEN => PAD)=(0, 0, 0, 0, 0, 0); + (PAD => C)=(0, 0); + endspecify +`endif +endmodule +`endcelldefine + +`celldefine +module PDDW08SDGZ_V_G (I, OEN, REN, PAD, C); + input I, OEN, REN; + inout PAD; + output C; + + wire MG, pull_pad, pull_c; + parameter PullTime = 10000; + + bufif0 (PAD_q, I, OEN); + pmos (MG, PAD_q, 1'b0); + bufif1 (weak1, weak0) (PAD_i, 1'b0, pull_pad); + pmos (MG, PAD_i, 1'b0); + pmos (PAD, MG, 1'b0); + bufif1 (C_buf, PAD, 1'b1); + bufif1 (weak0,weak1) (C_buf, 1'b0, pull_c); + buf (C, C_buf); + not (RE, REN); + buf #(PullTime,0) (pull_pad, RE); + buf (pull_c, RE); + +`ifdef TETRAMAX +`else + always @(PAD) begin + if (PAD === 1'bx && !$test$plusargs("bus_conflict_off") && $countdrivers(PAD)) + $display("%t ++BUS CONFLICT++ : %m", $realtime); + end + + specify + (I => PAD)=(0, 0); + (OEN => PAD)=(0, 0, 0, 0, 0, 0); + (PAD => C)=(0, 0); + endspecify +`endif +endmodule +`endcelldefine + +`celldefine +module PDDW12DGZ_H_G (I, OEN, REN, PAD, C); + input I, OEN, REN; + inout PAD; + output C; + + wire MG, pull_pad, pull_c; + parameter PullTime = 10000; + + bufif0 (PAD_q, I, OEN); + pmos (MG, PAD_q, 1'b0); + bufif1 (weak1, weak0) (PAD_i, 1'b0, pull_pad); + pmos (MG, PAD_i, 1'b0); + pmos (PAD, MG, 1'b0); + bufif1 (C_buf, PAD, 1'b1); + bufif1 (weak0,weak1) (C_buf, 1'b0, pull_c); + buf (C, C_buf); + not (RE, REN); + buf #(PullTime,0) (pull_pad, RE); + buf (pull_c, RE); + +`ifdef TETRAMAX +`else + always @(PAD) begin + if (PAD === 1'bx && !$test$plusargs("bus_conflict_off") && $countdrivers(PAD)) + $display("%t ++BUS CONFLICT++ : %m", $realtime); + end + + specify + (I => PAD)=(0, 0); + (OEN => PAD)=(0, 0, 0, 0, 0, 0); + (PAD => C)=(0, 0); + endspecify +`endif +endmodule +`endcelldefine + +`celldefine +module PDDW12DGZ_V_G (I, OEN, REN, PAD, C); + input I, OEN, REN; + inout PAD; + output C; + + wire MG, pull_pad, pull_c; + parameter PullTime = 10000; + + bufif0 (PAD_q, I, OEN); + pmos (MG, PAD_q, 1'b0); + bufif1 (weak1, weak0) (PAD_i, 1'b0, pull_pad); + pmos (MG, PAD_i, 1'b0); + pmos (PAD, MG, 1'b0); + bufif1 (C_buf, PAD, 1'b1); + bufif1 (weak0,weak1) (C_buf, 1'b0, pull_c); + buf (C, C_buf); + not (RE, REN); + buf #(PullTime,0) (pull_pad, RE); + buf (pull_c, RE); + +`ifdef TETRAMAX +`else + always @(PAD) begin + if (PAD === 1'bx && !$test$plusargs("bus_conflict_off") && $countdrivers(PAD)) + $display("%t ++BUS CONFLICT++ : %m", $realtime); + end + + specify + (I => PAD)=(0, 0); + (OEN => PAD)=(0, 0, 0, 0, 0, 0); + (PAD => C)=(0, 0); + endspecify +`endif +endmodule +`endcelldefine + +`celldefine +module PDDW12SDGZ_H_G (I, OEN, REN, PAD, C); + input I, OEN, REN; + inout PAD; + output C; + + wire MG, pull_pad, pull_c; + parameter PullTime = 10000; + + bufif0 (PAD_q, I, OEN); + pmos (MG, PAD_q, 1'b0); + bufif1 (weak1, weak0) (PAD_i, 1'b0, pull_pad); + pmos (MG, PAD_i, 1'b0); + pmos (PAD, MG, 1'b0); + bufif1 (C_buf, PAD, 1'b1); + bufif1 (weak0,weak1) (C_buf, 1'b0, pull_c); + buf (C, C_buf); + not (RE, REN); + buf #(PullTime,0) (pull_pad, RE); + buf (pull_c, RE); + +`ifdef TETRAMAX +`else + always @(PAD) begin + if (PAD === 1'bx && !$test$plusargs("bus_conflict_off") && $countdrivers(PAD)) + $display("%t ++BUS CONFLICT++ : %m", $realtime); + end + + specify + (I => PAD)=(0, 0); + (OEN => PAD)=(0, 0, 0, 0, 0, 0); + (PAD => C)=(0, 0); + endspecify +`endif +endmodule +`endcelldefine + +`celldefine +module PDDW12SDGZ_V_G (I, OEN, REN, PAD, C); + input I, OEN, REN; + inout PAD; + output C; + + wire MG, pull_pad, pull_c; + parameter PullTime = 10000; + + bufif0 (PAD_q, I, OEN); + pmos (MG, PAD_q, 1'b0); + bufif1 (weak1, weak0) (PAD_i, 1'b0, pull_pad); + pmos (MG, PAD_i, 1'b0); + pmos (PAD, MG, 1'b0); + bufif1 (C_buf, PAD, 1'b1); + bufif1 (weak0,weak1) (C_buf, 1'b0, pull_c); + buf (C, C_buf); + not (RE, REN); + buf #(PullTime,0) (pull_pad, RE); + buf (pull_c, RE); + +`ifdef TETRAMAX +`else + always @(PAD) begin + if (PAD === 1'bx && !$test$plusargs("bus_conflict_off") && $countdrivers(PAD)) + $display("%t ++BUS CONFLICT++ : %m", $realtime); + end + + specify + (I => PAD)=(0, 0); + (OEN => PAD)=(0, 0, 0, 0, 0, 0); + (PAD => C)=(0, 0); + endspecify +`endif +endmodule +`endcelldefine + +`celldefine +module PDDW16DGZ_H_G (I, OEN, REN, PAD, C); + input I, OEN, REN; + inout PAD; + output C; + + wire MG, pull_pad, pull_c; + parameter PullTime = 10000; + + bufif0 (PAD_q, I, OEN); + pmos (MG, PAD_q, 1'b0); + bufif1 (weak1, weak0) (PAD_i, 1'b0, pull_pad); + pmos (MG, PAD_i, 1'b0); + pmos (PAD, MG, 1'b0); + bufif1 (C_buf, PAD, 1'b1); + bufif1 (weak0,weak1) (C_buf, 1'b0, pull_c); + buf (C, C_buf); + not (RE, REN); + buf #(PullTime,0) (pull_pad, RE); + buf (pull_c, RE); + +`ifdef TETRAMAX +`else + always @(PAD) begin + if (PAD === 1'bx && !$test$plusargs("bus_conflict_off") && $countdrivers(PAD)) + $display("%t ++BUS CONFLICT++ : %m", $realtime); + end + + specify + (I => PAD)=(0, 0); + (OEN => PAD)=(0, 0, 0, 0, 0, 0); + (PAD => C)=(0, 0); + endspecify +`endif +endmodule +`endcelldefine + +`celldefine +module PDDW16DGZ_V_G (I, OEN, REN, PAD, C); + input I, OEN, REN; + inout PAD; + output C; + + wire MG, pull_pad, pull_c; + parameter PullTime = 10000; + + bufif0 (PAD_q, I, OEN); + pmos (MG, PAD_q, 1'b0); + bufif1 (weak1, weak0) (PAD_i, 1'b0, pull_pad); + pmos (MG, PAD_i, 1'b0); + pmos (PAD, MG, 1'b0); + bufif1 (C_buf, PAD, 1'b1); + bufif1 (weak0,weak1) (C_buf, 1'b0, pull_c); + buf (C, C_buf); + not (RE, REN); + buf #(PullTime,0) (pull_pad, RE); + buf (pull_c, RE); + +`ifdef TETRAMAX +`else + always @(PAD) begin + if (PAD === 1'bx && !$test$plusargs("bus_conflict_off") && $countdrivers(PAD)) + $display("%t ++BUS CONFLICT++ : %m", $realtime); + end + + specify + (I => PAD)=(0, 0); + (OEN => PAD)=(0, 0, 0, 0, 0, 0); + (PAD => C)=(0, 0); + endspecify +`endif +endmodule +`endcelldefine + +`celldefine +module PDDW16SDGZ_H_G (I, OEN, REN, PAD, C); + input I, OEN, REN; + inout PAD; + output C; + + wire MG, pull_pad, pull_c; + parameter PullTime = 10000; + + bufif0 (PAD_q, I, OEN); + pmos (MG, PAD_q, 1'b0); + bufif1 (weak1, weak0) (PAD_i, 1'b0, pull_pad); + pmos (MG, PAD_i, 1'b0); + pmos (PAD, MG, 1'b0); + bufif1 (C_buf, PAD, 1'b1); + bufif1 (weak0,weak1) (C_buf, 1'b0, pull_c); + buf (C, C_buf); + not (RE, REN); + buf #(PullTime,0) (pull_pad, RE); + buf (pull_c, RE); + +`ifdef TETRAMAX +`else + always @(PAD) begin + if (PAD === 1'bx && !$test$plusargs("bus_conflict_off") && $countdrivers(PAD)) + $display("%t ++BUS CONFLICT++ : %m", $realtime); + end + + specify + (I => PAD)=(0, 0); + (OEN => PAD)=(0, 0, 0, 0, 0, 0); + (PAD => C)=(0, 0); + endspecify +`endif +endmodule +`endcelldefine + +`celldefine +module PDDW16SDGZ_V_G (I, OEN, REN, PAD, C); + input I, OEN, REN; + inout PAD; + output C; + + wire MG, pull_pad, pull_c; + parameter PullTime = 10000; + + bufif0 (PAD_q, I, OEN); + pmos (MG, PAD_q, 1'b0); + bufif1 (weak1, weak0) (PAD_i, 1'b0, pull_pad); + pmos (MG, PAD_i, 1'b0); + pmos (PAD, MG, 1'b0); + bufif1 (C_buf, PAD, 1'b1); + bufif1 (weak0,weak1) (C_buf, 1'b0, pull_c); + buf (C, C_buf); + not (RE, REN); + buf #(PullTime,0) (pull_pad, RE); + buf (pull_c, RE); + +`ifdef TETRAMAX +`else + always @(PAD) begin + if (PAD === 1'bx && !$test$plusargs("bus_conflict_off") && $countdrivers(PAD)) + $display("%t ++BUS CONFLICT++ : %m", $realtime); + end + + specify + (I => PAD)=(0, 0); + (OEN => PAD)=(0, 0, 0, 0, 0, 0); + (PAD => C)=(0, 0); + endspecify +`endif +endmodule +`endcelldefine + +`celldefine +module PDUW04DGZ_H_G (I, OEN, REN, PAD, C); + input I, OEN, REN; + inout PAD; + output C; + + wire MG, pull_pad, pull_c; + parameter PullTime = 10000; + + bufif0 (PAD_q, I, OEN); + pmos (MG, PAD_q, 1'b0); + bufif1 (weak1, weak0) (PAD_i, 1'b1, pull_pad); + pmos (MG, PAD_i, 1'b0); + pmos (PAD, MG, 1'b0); + bufif1 (C_buf, PAD, 1'b1); + bufif1 (weak0,weak1) (C_buf, 1'b1, pull_c); + buf (C, C_buf); + not (RE, REN); + buf #(PullTime,0) (pull_pad, RE); + buf (pull_c, RE); + +`ifdef TETRAMAX +`else + always @(PAD) begin + if (PAD === 1'bx && !$test$plusargs("bus_conflict_off") && $countdrivers(PAD)) + $display("%t ++BUS CONFLICT++ : %m", $realtime); + end + + specify + (I => PAD)=(0, 0); + (OEN => PAD)=(0, 0, 0, 0, 0, 0); + (PAD => C)=(0, 0); + endspecify +`endif +endmodule +`endcelldefine + +`celldefine +module PDUW04DGZ_V_G (I, OEN, REN, PAD, C); + input I, OEN, REN; + inout PAD; + output C; + + wire MG, pull_pad, pull_c; + parameter PullTime = 10000; + + bufif0 (PAD_q, I, OEN); + pmos (MG, PAD_q, 1'b0); + bufif1 (weak1, weak0) (PAD_i, 1'b1, pull_pad); + pmos (MG, PAD_i, 1'b0); + pmos (PAD, MG, 1'b0); + bufif1 (C_buf, PAD, 1'b1); + bufif1 (weak0,weak1) (C_buf, 1'b1, pull_c); + buf (C, C_buf); + not (RE, REN); + buf #(PullTime,0) (pull_pad, RE); + buf (pull_c, RE); + +`ifdef TETRAMAX +`else + always @(PAD) begin + if (PAD === 1'bx && !$test$plusargs("bus_conflict_off") && $countdrivers(PAD)) + $display("%t ++BUS CONFLICT++ : %m", $realtime); + end + + specify + (I => PAD)=(0, 0); + (OEN => PAD)=(0, 0, 0, 0, 0, 0); + (PAD => C)=(0, 0); + endspecify +`endif +endmodule +`endcelldefine + +`celldefine +module PDUW04SDGZ_H_G (I, OEN, REN, PAD, C); + input I, OEN, REN; + inout PAD; + output C; + + wire MG, pull_pad, pull_c; + parameter PullTime = 10000; + + bufif0 (PAD_q, I, OEN); + pmos (MG, PAD_q, 1'b0); + bufif1 (weak1, weak0) (PAD_i, 1'b1, pull_pad); + pmos (MG, PAD_i, 1'b0); + pmos (PAD, MG, 1'b0); + bufif1 (C_buf, PAD, 1'b1); + bufif1 (weak0,weak1) (C_buf, 1'b1, pull_c); + buf (C, C_buf); + not (RE, REN); + buf #(PullTime,0) (pull_pad, RE); + buf (pull_c, RE); + +`ifdef TETRAMAX +`else + always @(PAD) begin + if (PAD === 1'bx && !$test$plusargs("bus_conflict_off") && $countdrivers(PAD)) + $display("%t ++BUS CONFLICT++ : %m", $realtime); + end + + specify + (I => PAD)=(0, 0); + (OEN => PAD)=(0, 0, 0, 0, 0, 0); + (PAD => C)=(0, 0); + endspecify +`endif +endmodule +`endcelldefine + +`celldefine +module PDUW04SDGZ_V_G (I, OEN, REN, PAD, C); + input I, OEN, REN; + inout PAD; + output C; + + wire MG, pull_pad, pull_c; + parameter PullTime = 10000; + + bufif0 (PAD_q, I, OEN); + pmos (MG, PAD_q, 1'b0); + bufif1 (weak1, weak0) (PAD_i, 1'b1, pull_pad); + pmos (MG, PAD_i, 1'b0); + pmos (PAD, MG, 1'b0); + bufif1 (C_buf, PAD, 1'b1); + bufif1 (weak0,weak1) (C_buf, 1'b1, pull_c); + buf (C, C_buf); + not (RE, REN); + buf #(PullTime,0) (pull_pad, RE); + buf (pull_c, RE); + +`ifdef TETRAMAX +`else + always @(PAD) begin + if (PAD === 1'bx && !$test$plusargs("bus_conflict_off") && $countdrivers(PAD)) + $display("%t ++BUS CONFLICT++ : %m", $realtime); + end + + specify + (I => PAD)=(0, 0); + (OEN => PAD)=(0, 0, 0, 0, 0, 0); + (PAD => C)=(0, 0); + endspecify +`endif +endmodule +`endcelldefine + +`celldefine +module PDUW08DGZ_H_G (I, OEN, REN, PAD, C); + input I, OEN, REN; + inout PAD; + output C; + + wire MG, pull_pad, pull_c; + parameter PullTime = 10000; + + bufif0 (PAD_q, I, OEN); + pmos (MG, PAD_q, 1'b0); + bufif1 (weak1, weak0) (PAD_i, 1'b1, pull_pad); + pmos (MG, PAD_i, 1'b0); + pmos (PAD, MG, 1'b0); + bufif1 (C_buf, PAD, 1'b1); + bufif1 (weak0,weak1) (C_buf, 1'b1, pull_c); + buf (C, C_buf); + not (RE, REN); + buf #(PullTime,0) (pull_pad, RE); + buf (pull_c, RE); + +`ifdef TETRAMAX +`else + always @(PAD) begin + if (PAD === 1'bx && !$test$plusargs("bus_conflict_off") && $countdrivers(PAD)) + $display("%t ++BUS CONFLICT++ : %m", $realtime); + end + + specify + (I => PAD)=(0, 0); + (OEN => PAD)=(0, 0, 0, 0, 0, 0); + (PAD => C)=(0, 0); + endspecify +`endif +endmodule +`endcelldefine + +`celldefine +module PDUW08DGZ_V_G (I, OEN, REN, PAD, C); + input I, OEN, REN; + inout PAD; + output C; + + wire MG, pull_pad, pull_c; + parameter PullTime = 10000; + + bufif0 (PAD_q, I, OEN); + pmos (MG, PAD_q, 1'b0); + bufif1 (weak1, weak0) (PAD_i, 1'b1, pull_pad); + pmos (MG, PAD_i, 1'b0); + pmos (PAD, MG, 1'b0); + bufif1 (C_buf, PAD, 1'b1); + bufif1 (weak0,weak1) (C_buf, 1'b1, pull_c); + buf (C, C_buf); + not (RE, REN); + buf #(PullTime,0) (pull_pad, RE); + buf (pull_c, RE); + +`ifdef TETRAMAX +`else + always @(PAD) begin + if (PAD === 1'bx && !$test$plusargs("bus_conflict_off") && $countdrivers(PAD)) + $display("%t ++BUS CONFLICT++ : %m", $realtime); + end + + specify + (I => PAD)=(0, 0); + (OEN => PAD)=(0, 0, 0, 0, 0, 0); + (PAD => C)=(0, 0); + endspecify +`endif +endmodule +`endcelldefine + +`celldefine +module PDUW08SDGZ_H_G (I, OEN, REN, PAD, C); + input I, OEN, REN; + inout PAD; + output C; + + wire MG, pull_pad, pull_c; + parameter PullTime = 10000; + + bufif0 (PAD_q, I, OEN); + pmos (MG, PAD_q, 1'b0); + bufif1 (weak1, weak0) (PAD_i, 1'b1, pull_pad); + pmos (MG, PAD_i, 1'b0); + pmos (PAD, MG, 1'b0); + bufif1 (C_buf, PAD, 1'b1); + bufif1 (weak0,weak1) (C_buf, 1'b1, pull_c); + buf (C, C_buf); + not (RE, REN); + buf #(PullTime,0) (pull_pad, RE); + buf (pull_c, RE); + +`ifdef TETRAMAX +`else + always @(PAD) begin + if (PAD === 1'bx && !$test$plusargs("bus_conflict_off") && $countdrivers(PAD)) + $display("%t ++BUS CONFLICT++ : %m", $realtime); + end + + specify + (I => PAD)=(0, 0); + (OEN => PAD)=(0, 0, 0, 0, 0, 0); + (PAD => C)=(0, 0); + endspecify +`endif +endmodule +`endcelldefine + +`celldefine +module PDUW08SDGZ_V_G (I, OEN, REN, PAD, C); + input I, OEN, REN; + inout PAD; + output C; + + wire MG, pull_pad, pull_c; + parameter PullTime = 10000; + + bufif0 (PAD_q, I, OEN); + pmos (MG, PAD_q, 1'b0); + bufif1 (weak1, weak0) (PAD_i, 1'b1, pull_pad); + pmos (MG, PAD_i, 1'b0); + pmos (PAD, MG, 1'b0); + bufif1 (C_buf, PAD, 1'b1); + bufif1 (weak0,weak1) (C_buf, 1'b1, pull_c); + buf (C, C_buf); + not (RE, REN); + buf #(PullTime,0) (pull_pad, RE); + buf (pull_c, RE); + +`ifdef TETRAMAX +`else + always @(PAD) begin + if (PAD === 1'bx && !$test$plusargs("bus_conflict_off") && $countdrivers(PAD)) + $display("%t ++BUS CONFLICT++ : %m", $realtime); + end + + specify + (I => PAD)=(0, 0); + (OEN => PAD)=(0, 0, 0, 0, 0, 0); + (PAD => C)=(0, 0); + endspecify +`endif +endmodule +`endcelldefine + +`celldefine +module PDUW12DGZ_H_G (I, OEN, REN, PAD, C); + input I, OEN, REN; + inout PAD; + output C; + + wire MG, pull_pad, pull_c; + parameter PullTime = 10000; + + bufif0 (PAD_q, I, OEN); + pmos (MG, PAD_q, 1'b0); + bufif1 (weak1, weak0) (PAD_i, 1'b1, pull_pad); + pmos (MG, PAD_i, 1'b0); + pmos (PAD, MG, 1'b0); + bufif1 (C_buf, PAD, 1'b1); + bufif1 (weak0,weak1) (C_buf, 1'b1, pull_c); + buf (C, C_buf); + not (RE, REN); + buf #(PullTime,0) (pull_pad, RE); + buf (pull_c, RE); + +`ifdef TETRAMAX +`else + always @(PAD) begin + if (PAD === 1'bx && !$test$plusargs("bus_conflict_off") && $countdrivers(PAD)) + $display("%t ++BUS CONFLICT++ : %m", $realtime); + end + + specify + (I => PAD)=(0, 0); + (OEN => PAD)=(0, 0, 0, 0, 0, 0); + (PAD => C)=(0, 0); + endspecify +`endif +endmodule +`endcelldefine + +`celldefine +module PDUW12DGZ_V_G (I, OEN, REN, PAD, C); + input I, OEN, REN; + inout PAD; + output C; + + wire MG, pull_pad, pull_c; + parameter PullTime = 10000; + + bufif0 (PAD_q, I, OEN); + pmos (MG, PAD_q, 1'b0); + bufif1 (weak1, weak0) (PAD_i, 1'b1, pull_pad); + pmos (MG, PAD_i, 1'b0); + pmos (PAD, MG, 1'b0); + bufif1 (C_buf, PAD, 1'b1); + bufif1 (weak0,weak1) (C_buf, 1'b1, pull_c); + buf (C, C_buf); + not (RE, REN); + buf #(PullTime,0) (pull_pad, RE); + buf (pull_c, RE); + +`ifdef TETRAMAX +`else + always @(PAD) begin + if (PAD === 1'bx && !$test$plusargs("bus_conflict_off") && $countdrivers(PAD)) + $display("%t ++BUS CONFLICT++ : %m", $realtime); + end + + specify + (I => PAD)=(0, 0); + (OEN => PAD)=(0, 0, 0, 0, 0, 0); + (PAD => C)=(0, 0); + endspecify +`endif +endmodule +`endcelldefine + +`celldefine +module PDUW12SDGZ_H_G (I, OEN, REN, PAD, C); + input I, OEN, REN; + inout PAD; + output C; + + wire MG, pull_pad, pull_c; + parameter PullTime = 10000; + + bufif0 (PAD_q, I, OEN); + pmos (MG, PAD_q, 1'b0); + bufif1 (weak1, weak0) (PAD_i, 1'b1, pull_pad); + pmos (MG, PAD_i, 1'b0); + pmos (PAD, MG, 1'b0); + bufif1 (C_buf, PAD, 1'b1); + bufif1 (weak0,weak1) (C_buf, 1'b1, pull_c); + buf (C, C_buf); + not (RE, REN); + buf #(PullTime,0) (pull_pad, RE); + buf (pull_c, RE); + +`ifdef TETRAMAX +`else + always @(PAD) begin + if (PAD === 1'bx && !$test$plusargs("bus_conflict_off") && $countdrivers(PAD)) + $display("%t ++BUS CONFLICT++ : %m", $realtime); + end + + specify + (I => PAD)=(0, 0); + (OEN => PAD)=(0, 0, 0, 0, 0, 0); + (PAD => C)=(0, 0); + endspecify +`endif +endmodule +`endcelldefine + +`celldefine +module PDUW12SDGZ_V_G (I, OEN, REN, PAD, C); + input I, OEN, REN; + inout PAD; + output C; + + wire MG, pull_pad, pull_c; + parameter PullTime = 10000; + + bufif0 (PAD_q, I, OEN); + pmos (MG, PAD_q, 1'b0); + bufif1 (weak1, weak0) (PAD_i, 1'b1, pull_pad); + pmos (MG, PAD_i, 1'b0); + pmos (PAD, MG, 1'b0); + bufif1 (C_buf, PAD, 1'b1); + bufif1 (weak0,weak1) (C_buf, 1'b1, pull_c); + buf (C, C_buf); + not (RE, REN); + buf #(PullTime,0) (pull_pad, RE); + buf (pull_c, RE); + +`ifdef TETRAMAX +`else + always @(PAD) begin + if (PAD === 1'bx && !$test$plusargs("bus_conflict_off") && $countdrivers(PAD)) + $display("%t ++BUS CONFLICT++ : %m", $realtime); + end + + specify + (I => PAD)=(0, 0); + (OEN => PAD)=(0, 0, 0, 0, 0, 0); + (PAD => C)=(0, 0); + endspecify +`endif +endmodule +`endcelldefine + +`celldefine +module PDUW16DGZ_H_G (I, OEN, REN, PAD, C); + input I, OEN, REN; + inout PAD; + output C; + + wire MG, pull_pad, pull_c; + parameter PullTime = 10000; + + bufif0 (PAD_q, I, OEN); + pmos (MG, PAD_q, 1'b0); + bufif1 (weak1, weak0) (PAD_i, 1'b1, pull_pad); + pmos (MG, PAD_i, 1'b0); + pmos (PAD, MG, 1'b0); + bufif1 (C_buf, PAD, 1'b1); + bufif1 (weak0,weak1) (C_buf, 1'b1, pull_c); + buf (C, C_buf); + not (RE, REN); + buf #(PullTime,0) (pull_pad, RE); + buf (pull_c, RE); + +`ifdef TETRAMAX +`else + always @(PAD) begin + if (PAD === 1'bx && !$test$plusargs("bus_conflict_off") && $countdrivers(PAD)) + $display("%t ++BUS CONFLICT++ : %m", $realtime); + end + + specify + (I => PAD)=(0, 0); + (OEN => PAD)=(0, 0, 0, 0, 0, 0); + (PAD => C)=(0, 0); + endspecify +`endif +endmodule +`endcelldefine + +`celldefine +module PDUW16DGZ_V_G (I, OEN, REN, PAD, C); + input I, OEN, REN; + inout PAD; + output C; + + wire MG, pull_pad, pull_c; + parameter PullTime = 10000; + + bufif0 (PAD_q, I, OEN); + pmos (MG, PAD_q, 1'b0); + bufif1 (weak1, weak0) (PAD_i, 1'b1, pull_pad); + pmos (MG, PAD_i, 1'b0); + pmos (PAD, MG, 1'b0); + bufif1 (C_buf, PAD, 1'b1); + bufif1 (weak0,weak1) (C_buf, 1'b1, pull_c); + buf (C, C_buf); + not (RE, REN); + buf #(PullTime,0) (pull_pad, RE); + buf (pull_c, RE); + +`ifdef TETRAMAX +`else + always @(PAD) begin + if (PAD === 1'bx && !$test$plusargs("bus_conflict_off") && $countdrivers(PAD)) + $display("%t ++BUS CONFLICT++ : %m", $realtime); + end + + specify + (I => PAD)=(0, 0); + (OEN => PAD)=(0, 0, 0, 0, 0, 0); + (PAD => C)=(0, 0); + endspecify +`endif +endmodule +`endcelldefine + +`celldefine +module PDUW16SDGZ_H_G (I, OEN, REN, PAD, C); + input I, OEN, REN; + inout PAD; + output C; + + wire MG, pull_pad, pull_c; + parameter PullTime = 10000; + + bufif0 (PAD_q, I, OEN); + pmos (MG, PAD_q, 1'b0); + bufif1 (weak1, weak0) (PAD_i, 1'b1, pull_pad); + pmos (MG, PAD_i, 1'b0); + pmos (PAD, MG, 1'b0); + bufif1 (C_buf, PAD, 1'b1); + bufif1 (weak0,weak1) (C_buf, 1'b1, pull_c); + buf (C, C_buf); + not (RE, REN); + buf #(PullTime,0) (pull_pad, RE); + buf (pull_c, RE); + +`ifdef TETRAMAX +`else + always @(PAD) begin + if (PAD === 1'bx && !$test$plusargs("bus_conflict_off") && $countdrivers(PAD)) + $display("%t ++BUS CONFLICT++ : %m", $realtime); + end + + specify + (I => PAD)=(0, 0); + (OEN => PAD)=(0, 0, 0, 0, 0, 0); + (PAD => C)=(0, 0); + endspecify +`endif +endmodule +`endcelldefine + +`celldefine +module PDUW16SDGZ_V_G (I, OEN, REN, PAD, C); + input I, OEN, REN; + inout PAD; + output C; + + wire MG, pull_pad, pull_c; + parameter PullTime = 10000; + + bufif0 (PAD_q, I, OEN); + pmos (MG, PAD_q, 1'b0); + bufif1 (weak1, weak0) (PAD_i, 1'b1, pull_pad); + pmos (MG, PAD_i, 1'b0); + pmos (PAD, MG, 1'b0); + bufif1 (C_buf, PAD, 1'b1); + bufif1 (weak0,weak1) (C_buf, 1'b1, pull_c); + buf (C, C_buf); + not (RE, REN); + buf #(PullTime,0) (pull_pad, RE); + buf (pull_c, RE); + +`ifdef TETRAMAX +`else + always @(PAD) begin + if (PAD === 1'bx && !$test$plusargs("bus_conflict_off") && $countdrivers(PAD)) + $display("%t ++BUS CONFLICT++ : %m", $realtime); + end + + specify + (I => PAD)=(0, 0); + (OEN => PAD)=(0, 0, 0, 0, 0, 0); + (PAD => C)=(0, 0); + endspecify +`endif +endmodule +`endcelldefine + +`celldefine +module PDXOEDG_H_G (E, DS0, DS1, XIN, XOUT, XC); + input E, DS0, DS1, XIN; + output XC, XOUT; + not (XC, XOUT); + nand (XOUT, E, XIN); + pmos (DS0_tmp, DS0, 1'b0); + pmos (DS1_tmp, DS1, 1'b0); + specify + if (DS0 == 1'b0 && DS1 == 1'b0) (E => XC)=(0, 0); + if (DS0 == 1'b0 && DS1 == 1'b1) (E => XC)=(0, 0); + if (DS0 == 1'b1 && DS1 == 1'b0) (E => XC)=(0, 0); + if (DS0 == 1'b1 && DS1 == 1'b1) (E => XC)=(0, 0); + if (DS0 == 1'b0 && DS1 == 1'b0) (E => XOUT)=(0, 0); + if (DS0 == 1'b0 && DS1 == 1'b1) (E => XOUT)=(0, 0); + if (DS0 == 1'b1 && DS1 == 1'b0) (E => XOUT)=(0, 0); + if (DS0 == 1'b1 && DS1 == 1'b1) (E => XOUT)=(0, 0); + if (DS0 == 1'b0 && DS1 == 1'b0) (XIN => XC)=(0, 0); + if (DS0 == 1'b0 && DS1 == 1'b1) (XIN => XC)=(0, 0); + if (DS0 == 1'b1 && DS1 == 1'b0) (XIN => XC)=(0, 0); + if (DS0 == 1'b1 && DS1 == 1'b1) (XIN => XC)=(0, 0); + if (DS0 == 1'b0 && DS1 == 1'b0) (XIN => XOUT)=(0, 0); + if (DS0 == 1'b0 && DS1 == 1'b1) (XIN => XOUT)=(0, 0); + if (DS0 == 1'b1 && DS1 == 1'b0) (XIN => XOUT)=(0, 0); + if (DS0 == 1'b1 && DS1 == 1'b1) (XIN => XOUT)=(0, 0); + endspecify +endmodule +`endcelldefine + +`celldefine +module PDXOEDG_V_G (E, DS0, DS1, XIN, XOUT, XC); + input E, DS0, DS1, XIN; + output XC, XOUT; + not (XC, XOUT); + nand (XOUT, E, XIN); + pmos (DS0_tmp, DS0, 1'b0); + pmos (DS1_tmp, DS1, 1'b0); + specify + if (DS0 == 1'b0 && DS1 == 1'b0) (E => XC)=(0, 0); + if (DS0 == 1'b0 && DS1 == 1'b1) (E => XC)=(0, 0); + if (DS0 == 1'b1 && DS1 == 1'b0) (E => XC)=(0, 0); + if (DS0 == 1'b1 && DS1 == 1'b1) (E => XC)=(0, 0); + if (DS0 == 1'b0 && DS1 == 1'b0) (E => XOUT)=(0, 0); + if (DS0 == 1'b0 && DS1 == 1'b1) (E => XOUT)=(0, 0); + if (DS0 == 1'b1 && DS1 == 1'b0) (E => XOUT)=(0, 0); + if (DS0 == 1'b1 && DS1 == 1'b1) (E => XOUT)=(0, 0); + if (DS0 == 1'b0 && DS1 == 1'b0) (XIN => XC)=(0, 0); + if (DS0 == 1'b0 && DS1 == 1'b1) (XIN => XC)=(0, 0); + if (DS0 == 1'b1 && DS1 == 1'b0) (XIN => XC)=(0, 0); + if (DS0 == 1'b1 && DS1 == 1'b1) (XIN => XC)=(0, 0); + if (DS0 == 1'b0 && DS1 == 1'b0) (XIN => XOUT)=(0, 0); + if (DS0 == 1'b0 && DS1 == 1'b1) (XIN => XOUT)=(0, 0); + if (DS0 == 1'b1 && DS1 == 1'b0) (XIN => XOUT)=(0, 0); + if (DS0 == 1'b1 && DS1 == 1'b1) (XIN => XOUT)=(0, 0); + endspecify +endmodule +`endcelldefine + +`celldefine +module PENDCAP_G (); +endmodule +`endcelldefine + +`celldefine +module PENDCAPA_G (); +endmodule +`endcelldefine + +`celldefine +module PRCUT_G (); +endmodule +`endcelldefine + +`celldefine +module PRCUTA_G (); +endmodule +`endcelldefine + +`celldefine +module PRDW08DGZ_H_G (I, OEN, REN, PAD, C); + input I, OEN, REN; + inout PAD; + output C; + + wire MG, pull_pad, pull_c; + parameter PullTime = 10000; + + bufif0 (PAD_q, I, OEN); + pmos (MG, PAD_q, 1'b0); + bufif1 (weak1, weak0) (PAD_i, 1'b0, pull_pad); + pmos (MG, PAD_i, 1'b0); + pmos (PAD, MG, 1'b0); + bufif1 (C_buf, PAD, 1'b1); + bufif1 (weak0,weak1) (C_buf, 1'b0, pull_c); + buf (C, C_buf); + not (RE, REN); + buf #(PullTime,0) (pull_pad, RE); + buf (pull_c, RE); + +`ifdef TETRAMAX +`else + always @(PAD) begin + if (PAD === 1'bx && !$test$plusargs("bus_conflict_off") && $countdrivers(PAD)) + $display("%t ++BUS CONFLICT++ : %m", $realtime); + end + + specify + (I => PAD)=(0, 0); + (OEN => PAD)=(0, 0, 0, 0, 0, 0); + (PAD => C)=(0, 0); + endspecify +`endif +endmodule +`endcelldefine + +`celldefine +module PRDW08DGZ_V_G (I, OEN, REN, PAD, C); + input I, OEN, REN; + inout PAD; + output C; + + wire MG, pull_pad, pull_c; + parameter PullTime = 10000; + + bufif0 (PAD_q, I, OEN); + pmos (MG, PAD_q, 1'b0); + bufif1 (weak1, weak0) (PAD_i, 1'b0, pull_pad); + pmos (MG, PAD_i, 1'b0); + pmos (PAD, MG, 1'b0); + bufif1 (C_buf, PAD, 1'b1); + bufif1 (weak0,weak1) (C_buf, 1'b0, pull_c); + buf (C, C_buf); + not (RE, REN); + buf #(PullTime,0) (pull_pad, RE); + buf (pull_c, RE); + +`ifdef TETRAMAX +`else + always @(PAD) begin + if (PAD === 1'bx && !$test$plusargs("bus_conflict_off") && $countdrivers(PAD)) + $display("%t ++BUS CONFLICT++ : %m", $realtime); + end + + specify + (I => PAD)=(0, 0); + (OEN => PAD)=(0, 0, 0, 0, 0, 0); + (PAD => C)=(0, 0); + endspecify +`endif +endmodule +`endcelldefine + +`celldefine +module PRDW08SDGZ_H_G (I, OEN, REN, PAD, C); + input I, OEN, REN; + inout PAD; + output C; + + wire MG, pull_pad, pull_c; + parameter PullTime = 10000; + + bufif0 (PAD_q, I, OEN); + pmos (MG, PAD_q, 1'b0); + bufif1 (weak1, weak0) (PAD_i, 1'b0, pull_pad); + pmos (MG, PAD_i, 1'b0); + pmos (PAD, MG, 1'b0); + bufif1 (C_buf, PAD, 1'b1); + bufif1 (weak0,weak1) (C_buf, 1'b0, pull_c); + buf (C, C_buf); + not (RE, REN); + buf #(PullTime,0) (pull_pad, RE); + buf (pull_c, RE); + +`ifdef TETRAMAX +`else + always @(PAD) begin + if (PAD === 1'bx && !$test$plusargs("bus_conflict_off") && $countdrivers(PAD)) + $display("%t ++BUS CONFLICT++ : %m", $realtime); + end + + specify + (I => PAD)=(0, 0); + (OEN => PAD)=(0, 0, 0, 0, 0, 0); + (PAD => C)=(0, 0); + endspecify +`endif +endmodule +`endcelldefine + +`celldefine +module PRDW08SDGZ_V_G (I, OEN, REN, PAD, C); + input I, OEN, REN; + inout PAD; + output C; + + wire MG, pull_pad, pull_c; + parameter PullTime = 10000; + + bufif0 (PAD_q, I, OEN); + pmos (MG, PAD_q, 1'b0); + bufif1 (weak1, weak0) (PAD_i, 1'b0, pull_pad); + pmos (MG, PAD_i, 1'b0); + pmos (PAD, MG, 1'b0); + bufif1 (C_buf, PAD, 1'b1); + bufif1 (weak0,weak1) (C_buf, 1'b0, pull_c); + buf (C, C_buf); + not (RE, REN); + buf #(PullTime,0) (pull_pad, RE); + buf (pull_c, RE); + +`ifdef TETRAMAX +`else + always @(PAD) begin + if (PAD === 1'bx && !$test$plusargs("bus_conflict_off") && $countdrivers(PAD)) + $display("%t ++BUS CONFLICT++ : %m", $realtime); + end + + specify + (I => PAD)=(0, 0); + (OEN => PAD)=(0, 0, 0, 0, 0, 0); + (PAD => C)=(0, 0); + endspecify +`endif +endmodule +`endcelldefine + +`celldefine +module PRDW12DGZ_H_G (I, OEN, REN, PAD, C); + input I, OEN, REN; + inout PAD; + output C; + + wire MG, pull_pad, pull_c; + parameter PullTime = 10000; + + bufif0 (PAD_q, I, OEN); + pmos (MG, PAD_q, 1'b0); + bufif1 (weak1, weak0) (PAD_i, 1'b0, pull_pad); + pmos (MG, PAD_i, 1'b0); + pmos (PAD, MG, 1'b0); + bufif1 (C_buf, PAD, 1'b1); + bufif1 (weak0,weak1) (C_buf, 1'b0, pull_c); + buf (C, C_buf); + not (RE, REN); + buf #(PullTime,0) (pull_pad, RE); + buf (pull_c, RE); + +`ifdef TETRAMAX +`else + always @(PAD) begin + if (PAD === 1'bx && !$test$plusargs("bus_conflict_off") && $countdrivers(PAD)) + $display("%t ++BUS CONFLICT++ : %m", $realtime); + end + + specify + (I => PAD)=(0, 0); + (OEN => PAD)=(0, 0, 0, 0, 0, 0); + (PAD => C)=(0, 0); + endspecify +`endif +endmodule +`endcelldefine + +`celldefine +module PRDW12DGZ_V_G (I, OEN, REN, PAD, C); + input I, OEN, REN; + inout PAD; + output C; + + wire MG, pull_pad, pull_c; + parameter PullTime = 10000; + + bufif0 (PAD_q, I, OEN); + pmos (MG, PAD_q, 1'b0); + bufif1 (weak1, weak0) (PAD_i, 1'b0, pull_pad); + pmos (MG, PAD_i, 1'b0); + pmos (PAD, MG, 1'b0); + bufif1 (C_buf, PAD, 1'b1); + bufif1 (weak0,weak1) (C_buf, 1'b0, pull_c); + buf (C, C_buf); + not (RE, REN); + buf #(PullTime,0) (pull_pad, RE); + buf (pull_c, RE); + +`ifdef TETRAMAX +`else + always @(PAD) begin + if (PAD === 1'bx && !$test$plusargs("bus_conflict_off") && $countdrivers(PAD)) + $display("%t ++BUS CONFLICT++ : %m", $realtime); + end + + specify + (I => PAD)=(0, 0); + (OEN => PAD)=(0, 0, 0, 0, 0, 0); + (PAD => C)=(0, 0); + endspecify +`endif +endmodule +`endcelldefine + +`celldefine +module PRDW12SDGZ_H_G (I, OEN, REN, PAD, C); + input I, OEN, REN; + inout PAD; + output C; + + wire MG, pull_pad, pull_c; + parameter PullTime = 10000; + + bufif0 (PAD_q, I, OEN); + pmos (MG, PAD_q, 1'b0); + bufif1 (weak1, weak0) (PAD_i, 1'b0, pull_pad); + pmos (MG, PAD_i, 1'b0); + pmos (PAD, MG, 1'b0); + bufif1 (C_buf, PAD, 1'b1); + bufif1 (weak0,weak1) (C_buf, 1'b0, pull_c); + buf (C, C_buf); + not (RE, REN); + buf #(PullTime,0) (pull_pad, RE); + buf (pull_c, RE); + +`ifdef TETRAMAX +`else + always @(PAD) begin + if (PAD === 1'bx && !$test$plusargs("bus_conflict_off") && $countdrivers(PAD)) + $display("%t ++BUS CONFLICT++ : %m", $realtime); + end + + specify + (I => PAD)=(0, 0); + (OEN => PAD)=(0, 0, 0, 0, 0, 0); + (PAD => C)=(0, 0); + endspecify +`endif +endmodule +`endcelldefine + +`celldefine +module PRDW12SDGZ_V_G (I, OEN, REN, PAD, C); + input I, OEN, REN; + inout PAD; + output C; + + wire MG, pull_pad, pull_c; + parameter PullTime = 10000; + + bufif0 (PAD_q, I, OEN); + pmos (MG, PAD_q, 1'b0); + bufif1 (weak1, weak0) (PAD_i, 1'b0, pull_pad); + pmos (MG, PAD_i, 1'b0); + pmos (PAD, MG, 1'b0); + bufif1 (C_buf, PAD, 1'b1); + bufif1 (weak0,weak1) (C_buf, 1'b0, pull_c); + buf (C, C_buf); + not (RE, REN); + buf #(PullTime,0) (pull_pad, RE); + buf (pull_c, RE); + +`ifdef TETRAMAX +`else + always @(PAD) begin + if (PAD === 1'bx && !$test$plusargs("bus_conflict_off") && $countdrivers(PAD)) + $display("%t ++BUS CONFLICT++ : %m", $realtime); + end + + specify + (I => PAD)=(0, 0); + (OEN => PAD)=(0, 0, 0, 0, 0, 0); + (PAD => C)=(0, 0); + endspecify +`endif +endmodule +`endcelldefine + +`celldefine +module PRDW16DGZ_H_G (I, OEN, REN, PAD, C); + input I, OEN, REN; + inout PAD; + output C; + + wire MG, pull_pad, pull_c; + parameter PullTime = 10000; + + bufif0 (PAD_q, I, OEN); + pmos (MG, PAD_q, 1'b0); + bufif1 (weak1, weak0) (PAD_i, 1'b0, pull_pad); + pmos (MG, PAD_i, 1'b0); + pmos (PAD, MG, 1'b0); + bufif1 (C_buf, PAD, 1'b1); + bufif1 (weak0,weak1) (C_buf, 1'b0, pull_c); + buf (C, C_buf); + not (RE, REN); + buf #(PullTime,0) (pull_pad, RE); + buf (pull_c, RE); + +`ifdef TETRAMAX +`else + always @(PAD) begin + if (PAD === 1'bx && !$test$plusargs("bus_conflict_off") && $countdrivers(PAD)) + $display("%t ++BUS CONFLICT++ : %m", $realtime); + end + + specify + (I => PAD)=(0, 0); + (OEN => PAD)=(0, 0, 0, 0, 0, 0); + (PAD => C)=(0, 0); + endspecify +`endif +endmodule +`endcelldefine + +`celldefine +module PRDW16DGZ_V_G (I, OEN, REN, PAD, C); + input I, OEN, REN; + inout PAD; + output C; + + wire MG, pull_pad, pull_c; + parameter PullTime = 10000; + + bufif0 (PAD_q, I, OEN); + pmos (MG, PAD_q, 1'b0); + bufif1 (weak1, weak0) (PAD_i, 1'b0, pull_pad); + pmos (MG, PAD_i, 1'b0); + pmos (PAD, MG, 1'b0); + bufif1 (C_buf, PAD, 1'b1); + bufif1 (weak0,weak1) (C_buf, 1'b0, pull_c); + buf (C, C_buf); + not (RE, REN); + buf #(PullTime,0) (pull_pad, RE); + buf (pull_c, RE); + +`ifdef TETRAMAX +`else + always @(PAD) begin + if (PAD === 1'bx && !$test$plusargs("bus_conflict_off") && $countdrivers(PAD)) + $display("%t ++BUS CONFLICT++ : %m", $realtime); + end + + specify + (I => PAD)=(0, 0); + (OEN => PAD)=(0, 0, 0, 0, 0, 0); + (PAD => C)=(0, 0); + endspecify +`endif +endmodule +`endcelldefine + +`celldefine +module PRDW16SDGZ_H_G (I, OEN, REN, PAD, C); + input I, OEN, REN; + inout PAD; + output C; + + wire MG, pull_pad, pull_c; + parameter PullTime = 10000; + + bufif0 (PAD_q, I, OEN); + pmos (MG, PAD_q, 1'b0); + bufif1 (weak1, weak0) (PAD_i, 1'b0, pull_pad); + pmos (MG, PAD_i, 1'b0); + pmos (PAD, MG, 1'b0); + bufif1 (C_buf, PAD, 1'b1); + bufif1 (weak0,weak1) (C_buf, 1'b0, pull_c); + buf (C, C_buf); + not (RE, REN); + buf #(PullTime,0) (pull_pad, RE); + buf (pull_c, RE); + +`ifdef TETRAMAX +`else + always @(PAD) begin + if (PAD === 1'bx && !$test$plusargs("bus_conflict_off") && $countdrivers(PAD)) + $display("%t ++BUS CONFLICT++ : %m", $realtime); + end + + specify + (I => PAD)=(0, 0); + (OEN => PAD)=(0, 0, 0, 0, 0, 0); + (PAD => C)=(0, 0); + endspecify +`endif +endmodule +`endcelldefine + +`celldefine +module PRDW16SDGZ_V_G (I, OEN, REN, PAD, C); + input I, OEN, REN; + inout PAD; + output C; + + wire MG, pull_pad, pull_c; + parameter PullTime = 10000; + + bufif0 (PAD_q, I, OEN); + pmos (MG, PAD_q, 1'b0); + bufif1 (weak1, weak0) (PAD_i, 1'b0, pull_pad); + pmos (MG, PAD_i, 1'b0); + pmos (PAD, MG, 1'b0); + bufif1 (C_buf, PAD, 1'b1); + bufif1 (weak0,weak1) (C_buf, 1'b0, pull_c); + buf (C, C_buf); + not (RE, REN); + buf #(PullTime,0) (pull_pad, RE); + buf (pull_c, RE); + +`ifdef TETRAMAX +`else + always @(PAD) begin + if (PAD === 1'bx && !$test$plusargs("bus_conflict_off") && $countdrivers(PAD)) + $display("%t ++BUS CONFLICT++ : %m", $realtime); + end + + specify + (I => PAD)=(0, 0); + (OEN => PAD)=(0, 0, 0, 0, 0, 0); + (PAD => C)=(0, 0); + endspecify +`endif +endmodule +`endcelldefine + +`celldefine +module PRUW08DGZ_H_G (I, OEN, REN, PAD, C); + input I, OEN, REN; + inout PAD; + output C; + + wire MG, pull_pad, pull_c; + parameter PullTime = 10000; + + bufif0 (PAD_q, I, OEN); + pmos (MG, PAD_q, 1'b0); + bufif1 (weak1, weak0) (PAD_i, 1'b1, pull_pad); + pmos (MG, PAD_i, 1'b0); + pmos (PAD, MG, 1'b0); + bufif1 (C_buf, PAD, 1'b1); + bufif1 (weak0,weak1) (C_buf, 1'b1, pull_c); + buf (C, C_buf); + not (RE, REN); + buf #(PullTime,0) (pull_pad, RE); + buf (pull_c, RE); + +`ifdef TETRAMAX +`else + always @(PAD) begin + if (PAD === 1'bx && !$test$plusargs("bus_conflict_off") && $countdrivers(PAD)) + $display("%t ++BUS CONFLICT++ : %m", $realtime); + end + + specify + (I => PAD)=(0, 0); + (OEN => PAD)=(0, 0, 0, 0, 0, 0); + (PAD => C)=(0, 0); + endspecify +`endif +endmodule +`endcelldefine + +`celldefine +module PRUW08DGZ_V_G (I, OEN, REN, PAD, C); + input I, OEN, REN; + inout PAD; + output C; + + wire MG, pull_pad, pull_c; + parameter PullTime = 10000; + + bufif0 (PAD_q, I, OEN); + pmos (MG, PAD_q, 1'b0); + bufif1 (weak1, weak0) (PAD_i, 1'b1, pull_pad); + pmos (MG, PAD_i, 1'b0); + pmos (PAD, MG, 1'b0); + bufif1 (C_buf, PAD, 1'b1); + bufif1 (weak0,weak1) (C_buf, 1'b1, pull_c); + buf (C, C_buf); + not (RE, REN); + buf #(PullTime,0) (pull_pad, RE); + buf (pull_c, RE); + +`ifdef TETRAMAX +`else + always @(PAD) begin + if (PAD === 1'bx && !$test$plusargs("bus_conflict_off") && $countdrivers(PAD)) + $display("%t ++BUS CONFLICT++ : %m", $realtime); + end + + specify + (I => PAD)=(0, 0); + (OEN => PAD)=(0, 0, 0, 0, 0, 0); + (PAD => C)=(0, 0); + endspecify +`endif +endmodule +`endcelldefine + +`celldefine +module PRUW08SDGZ_H_G (I, OEN, REN, PAD, C); + input I, OEN, REN; + inout PAD; + output C; + + wire MG, pull_pad, pull_c; + parameter PullTime = 10000; + + bufif0 (PAD_q, I, OEN); + pmos (MG, PAD_q, 1'b0); + bufif1 (weak1, weak0) (PAD_i, 1'b1, pull_pad); + pmos (MG, PAD_i, 1'b0); + pmos (PAD, MG, 1'b0); + bufif1 (C_buf, PAD, 1'b1); + bufif1 (weak0,weak1) (C_buf, 1'b1, pull_c); + buf (C, C_buf); + not (RE, REN); + buf #(PullTime,0) (pull_pad, RE); + buf (pull_c, RE); + +`ifdef TETRAMAX +`else + always @(PAD) begin + if (PAD === 1'bx && !$test$plusargs("bus_conflict_off") && $countdrivers(PAD)) + $display("%t ++BUS CONFLICT++ : %m", $realtime); + end + + specify + (I => PAD)=(0, 0); + (OEN => PAD)=(0, 0, 0, 0, 0, 0); + (PAD => C)=(0, 0); + endspecify +`endif +endmodule +`endcelldefine + +`celldefine +module PRUW08SDGZ_V_G (I, OEN, REN, PAD, C); + input I, OEN, REN; + inout PAD; + output C; + + wire MG, pull_pad, pull_c; + parameter PullTime = 10000; + + bufif0 (PAD_q, I, OEN); + pmos (MG, PAD_q, 1'b0); + bufif1 (weak1, weak0) (PAD_i, 1'b1, pull_pad); + pmos (MG, PAD_i, 1'b0); + pmos (PAD, MG, 1'b0); + bufif1 (C_buf, PAD, 1'b1); + bufif1 (weak0,weak1) (C_buf, 1'b1, pull_c); + buf (C, C_buf); + not (RE, REN); + buf #(PullTime,0) (pull_pad, RE); + buf (pull_c, RE); + +`ifdef TETRAMAX +`else + always @(PAD) begin + if (PAD === 1'bx && !$test$plusargs("bus_conflict_off") && $countdrivers(PAD)) + $display("%t ++BUS CONFLICT++ : %m", $realtime); + end + + specify + (I => PAD)=(0, 0); + (OEN => PAD)=(0, 0, 0, 0, 0, 0); + (PAD => C)=(0, 0); + endspecify +`endif +endmodule +`endcelldefine + +`celldefine +module PRUW12DGZ_H_G (I, OEN, REN, PAD, C); + input I, OEN, REN; + inout PAD; + output C; + + wire MG, pull_pad, pull_c; + parameter PullTime = 10000; + + bufif0 (PAD_q, I, OEN); + pmos (MG, PAD_q, 1'b0); + bufif1 (weak1, weak0) (PAD_i, 1'b1, pull_pad); + pmos (MG, PAD_i, 1'b0); + pmos (PAD, MG, 1'b0); + bufif1 (C_buf, PAD, 1'b1); + bufif1 (weak0,weak1) (C_buf, 1'b1, pull_c); + buf (C, C_buf); + not (RE, REN); + buf #(PullTime,0) (pull_pad, RE); + buf (pull_c, RE); + +`ifdef TETRAMAX +`else + always @(PAD) begin + if (PAD === 1'bx && !$test$plusargs("bus_conflict_off") && $countdrivers(PAD)) + $display("%t ++BUS CONFLICT++ : %m", $realtime); + end + + specify + (I => PAD)=(0, 0); + (OEN => PAD)=(0, 0, 0, 0, 0, 0); + (PAD => C)=(0, 0); + endspecify +`endif +endmodule +`endcelldefine + +`celldefine +module PRUW12DGZ_V_G (I, OEN, REN, PAD, C); + input I, OEN, REN; + inout PAD; + output C; + + wire MG, pull_pad, pull_c; + parameter PullTime = 10000; + + bufif0 (PAD_q, I, OEN); + pmos (MG, PAD_q, 1'b0); + bufif1 (weak1, weak0) (PAD_i, 1'b1, pull_pad); + pmos (MG, PAD_i, 1'b0); + pmos (PAD, MG, 1'b0); + bufif1 (C_buf, PAD, 1'b1); + bufif1 (weak0,weak1) (C_buf, 1'b1, pull_c); + buf (C, C_buf); + not (RE, REN); + buf #(PullTime,0) (pull_pad, RE); + buf (pull_c, RE); + +`ifdef TETRAMAX +`else + always @(PAD) begin + if (PAD === 1'bx && !$test$plusargs("bus_conflict_off") && $countdrivers(PAD)) + $display("%t ++BUS CONFLICT++ : %m", $realtime); + end + + specify + (I => PAD)=(0, 0); + (OEN => PAD)=(0, 0, 0, 0, 0, 0); + (PAD => C)=(0, 0); + endspecify +`endif +endmodule +`endcelldefine + +`celldefine +module PRUW12SDGZ_H_G (I, OEN, REN, PAD, C); + input I, OEN, REN; + inout PAD; + output C; + + wire MG, pull_pad, pull_c; + parameter PullTime = 10000; + + bufif0 (PAD_q, I, OEN); + pmos (MG, PAD_q, 1'b0); + bufif1 (weak1, weak0) (PAD_i, 1'b1, pull_pad); + pmos (MG, PAD_i, 1'b0); + pmos (PAD, MG, 1'b0); + bufif1 (C_buf, PAD, 1'b1); + bufif1 (weak0,weak1) (C_buf, 1'b1, pull_c); + buf (C, C_buf); + not (RE, REN); + buf #(PullTime,0) (pull_pad, RE); + buf (pull_c, RE); + +`ifdef TETRAMAX +`else + always @(PAD) begin + if (PAD === 1'bx && !$test$plusargs("bus_conflict_off") && $countdrivers(PAD)) + $display("%t ++BUS CONFLICT++ : %m", $realtime); + end + + specify + (I => PAD)=(0, 0); + (OEN => PAD)=(0, 0, 0, 0, 0, 0); + (PAD => C)=(0, 0); + endspecify +`endif +endmodule +`endcelldefine + +`celldefine +module PRUW12SDGZ_V_G (I, OEN, REN, PAD, C); + input I, OEN, REN; + inout PAD; + output C; + + wire MG, pull_pad, pull_c; + parameter PullTime = 10000; + + bufif0 (PAD_q, I, OEN); + pmos (MG, PAD_q, 1'b0); + bufif1 (weak1, weak0) (PAD_i, 1'b1, pull_pad); + pmos (MG, PAD_i, 1'b0); + pmos (PAD, MG, 1'b0); + bufif1 (C_buf, PAD, 1'b1); + bufif1 (weak0,weak1) (C_buf, 1'b1, pull_c); + buf (C, C_buf); + not (RE, REN); + buf #(PullTime,0) (pull_pad, RE); + buf (pull_c, RE); + +`ifdef TETRAMAX +`else + always @(PAD) begin + if (PAD === 1'bx && !$test$plusargs("bus_conflict_off") && $countdrivers(PAD)) + $display("%t ++BUS CONFLICT++ : %m", $realtime); + end + + specify + (I => PAD)=(0, 0); + (OEN => PAD)=(0, 0, 0, 0, 0, 0); + (PAD => C)=(0, 0); + endspecify +`endif +endmodule +`endcelldefine + +`celldefine +module PRUW16DGZ_H_G (I, OEN, REN, PAD, C); + input I, OEN, REN; + inout PAD; + output C; + + wire MG, pull_pad, pull_c; + parameter PullTime = 10000; + + bufif0 (PAD_q, I, OEN); + pmos (MG, PAD_q, 1'b0); + bufif1 (weak1, weak0) (PAD_i, 1'b1, pull_pad); + pmos (MG, PAD_i, 1'b0); + pmos (PAD, MG, 1'b0); + bufif1 (C_buf, PAD, 1'b1); + bufif1 (weak0,weak1) (C_buf, 1'b1, pull_c); + buf (C, C_buf); + not (RE, REN); + buf #(PullTime,0) (pull_pad, RE); + buf (pull_c, RE); + +`ifdef TETRAMAX +`else + always @(PAD) begin + if (PAD === 1'bx && !$test$plusargs("bus_conflict_off") && $countdrivers(PAD)) + $display("%t ++BUS CONFLICT++ : %m", $realtime); + end + + specify + (I => PAD)=(0, 0); + (OEN => PAD)=(0, 0, 0, 0, 0, 0); + (PAD => C)=(0, 0); + endspecify +`endif +endmodule +`endcelldefine + +`celldefine +module PRUW16DGZ_V_G (I, OEN, REN, PAD, C); + input I, OEN, REN; + inout PAD; + output C; + + wire MG, pull_pad, pull_c; + parameter PullTime = 10000; + + bufif0 (PAD_q, I, OEN); + pmos (MG, PAD_q, 1'b0); + bufif1 (weak1, weak0) (PAD_i, 1'b1, pull_pad); + pmos (MG, PAD_i, 1'b0); + pmos (PAD, MG, 1'b0); + bufif1 (C_buf, PAD, 1'b1); + bufif1 (weak0,weak1) (C_buf, 1'b1, pull_c); + buf (C, C_buf); + not (RE, REN); + buf #(PullTime,0) (pull_pad, RE); + buf (pull_c, RE); + +`ifdef TETRAMAX +`else + always @(PAD) begin + if (PAD === 1'bx && !$test$plusargs("bus_conflict_off") && $countdrivers(PAD)) + $display("%t ++BUS CONFLICT++ : %m", $realtime); + end + + specify + (I => PAD)=(0, 0); + (OEN => PAD)=(0, 0, 0, 0, 0, 0); + (PAD => C)=(0, 0); + endspecify +`endif +endmodule +`endcelldefine + +`celldefine +module PRUW16SDGZ_H_G (I, OEN, REN, PAD, C); + input I, OEN, REN; + inout PAD; + output C; + + wire MG, pull_pad, pull_c; + parameter PullTime = 10000; + + bufif0 (PAD_q, I, OEN); + pmos (MG, PAD_q, 1'b0); + bufif1 (weak1, weak0) (PAD_i, 1'b1, pull_pad); + pmos (MG, PAD_i, 1'b0); + pmos (PAD, MG, 1'b0); + bufif1 (C_buf, PAD, 1'b1); + bufif1 (weak0,weak1) (C_buf, 1'b1, pull_c); + buf (C, C_buf); + not (RE, REN); + buf #(PullTime,0) (pull_pad, RE); + buf (pull_c, RE); + +`ifdef TETRAMAX +`else + always @(PAD) begin + if (PAD === 1'bx && !$test$plusargs("bus_conflict_off") && $countdrivers(PAD)) + $display("%t ++BUS CONFLICT++ : %m", $realtime); + end + + specify + (I => PAD)=(0, 0); + (OEN => PAD)=(0, 0, 0, 0, 0, 0); + (PAD => C)=(0, 0); + endspecify +`endif +endmodule +`endcelldefine + +`celldefine +module PRUW16SDGZ_V_G (I, OEN, REN, PAD, C); + input I, OEN, REN; + inout PAD; + output C; + + wire MG, pull_pad, pull_c; + parameter PullTime = 10000; + + bufif0 (PAD_q, I, OEN); + pmos (MG, PAD_q, 1'b0); + bufif1 (weak1, weak0) (PAD_i, 1'b1, pull_pad); + pmos (MG, PAD_i, 1'b0); + pmos (PAD, MG, 1'b0); + bufif1 (C_buf, PAD, 1'b1); + bufif1 (weak0,weak1) (C_buf, 1'b1, pull_c); + buf (C, C_buf); + not (RE, REN); + buf #(PullTime,0) (pull_pad, RE); + buf (pull_c, RE); + +`ifdef TETRAMAX +`else + always @(PAD) begin + if (PAD === 1'bx && !$test$plusargs("bus_conflict_off") && $countdrivers(PAD)) + $display("%t ++BUS CONFLICT++ : %m", $realtime); + end + + specify + (I => PAD)=(0, 0); + (OEN => PAD)=(0, 0, 0, 0, 0, 0); + (PAD => C)=(0, 0); + endspecify +`endif +endmodule +`endcelldefine + +`celldefine +module PVDD1A_H_G (AVDD); + inout AVDD; + tran (AVDD,AVDD); +endmodule +`endcelldefine + +`celldefine +module PVDD1A_V_G (AVDD); + inout AVDD; + tran (AVDD,AVDD); +endmodule +`endcelldefine + +`celldefine +module PVDD1AC_H_G (AVDD); + inout AVDD; + tran (AVDD,AVDD); +endmodule +`endcelldefine + +`celldefine +module PVDD1AC_V_G (AVDD); + inout AVDD; + tran (AVDD,AVDD); +endmodule +`endcelldefine + +`celldefine +module PVDD1ANA_H_G (AVDD); + inout AVDD; + tran (AVDD, AVDD); +endmodule +`endcelldefine + +`celldefine +module PVDD1ANA_V_G (AVDD); + inout AVDD; + tran (AVDD, AVDD); +endmodule +`endcelldefine + +`celldefine +module PVDD1DGZ_H_G (VDD); + inout VDD; + tran (VDD,VDD); +endmodule +`endcelldefine + +`celldefine +module PVDD1DGZ_V_G (VDD); + inout VDD; + tran (VDD,VDD); +endmodule +`endcelldefine + +`celldefine +module PVDD2ANA_H_G (AVDD); + inout AVDD; + tran (AVDD, AVDD); +endmodule +`endcelldefine + +`celldefine +module PVDD2ANA_V_G (AVDD); + inout AVDD; + tran (AVDD, AVDD); +endmodule +`endcelldefine + +`celldefine +module PVDD2DGZ_H_G (VDDPST); + inout VDDPST; + tran (VDDPST,VDDPST); +endmodule +`endcelldefine + +`celldefine +module PVDD2DGZ_V_G (VDDPST); + inout VDDPST; + tran (VDDPST,VDDPST); +endmodule +`endcelldefine + +`celldefine +module PVDD2POC_H_G (VDDPST); + inout VDDPST; + tran (VDDPST, VDDPST); +endmodule +`endcelldefine + +`celldefine +module PVDD2POC_V_G (VDDPST); + inout VDDPST; + tran (VDDPST, VDDPST); +endmodule +`endcelldefine + +`celldefine +module PVDD3A_H_G (AVDD,TAVDD); + inout AVDD,TAVDD; + tran (AVDD,TAVDD); +endmodule +`endcelldefine + +`celldefine +module PVDD3A_V_G (AVDD,TAVDD); + inout AVDD,TAVDD; + tran (AVDD,TAVDD); +endmodule +`endcelldefine + +`celldefine +module PVDD3AC_H_G (AVDD,TACVDD); + inout AVDD,TACVDD; + tran (AVDD,TACVDD); +endmodule +`endcelldefine + +`celldefine +module PVDD3AC_V_G (AVDD,TACVDD); + inout AVDD,TACVDD; + tran (AVDD,TACVDD); +endmodule +`endcelldefine + +`celldefine +module PVSS1A_H_G (AVSS); + inout AVSS; + tran (AVSS,AVSS); +endmodule +`endcelldefine + +`celldefine +module PVSS1A_V_G (AVSS); + inout AVSS; + tran (AVSS,AVSS); +endmodule +`endcelldefine + +`celldefine +module PVSS1AC_H_G (AVSS); + inout AVSS; + tran (AVSS,AVSS); +endmodule +`endcelldefine + +`celldefine +module PVSS1AC_V_G (AVSS); + inout AVSS; + tran (AVSS,AVSS); +endmodule +`endcelldefine + +`celldefine +module PVSS1ANA_H_G (AVSS); + inout AVSS; + tran (AVSS, AVSS); +endmodule + +`endcelldefine + +`celldefine +module PVSS1ANA_V_G (AVSS); + inout AVSS; + tran (AVSS, AVSS); +endmodule + +`endcelldefine + +`celldefine +module PVSS1DGZ_H_G (VSS); + inout VSS; + tran (VSS,VSS); +endmodule +`endcelldefine + +`celldefine +module PVSS1DGZ_V_G (VSS); + inout VSS; + tran (VSS,VSS); +endmodule +`endcelldefine + +`celldefine +module PVSS2A_H_G (VSS); + inout VSS; + tran (VSS,VSS); +endmodule +`endcelldefine + +`celldefine +module PVSS2A_V_G (VSS); + inout VSS; + tran (VSS,VSS); +endmodule +`endcelldefine + +`celldefine +module PVSS2AC_H_G (VSS); + inout VSS; + tran (VSS,VSS); +endmodule +`endcelldefine + +`celldefine +module PVSS2AC_V_G (VSS); + inout VSS; + tran (VSS,VSS); +endmodule +`endcelldefine + +`celldefine +module PVSS2ANA_H_G (AVSS); + inout AVSS; + tran (AVSS, AVSS); +endmodule + +`endcelldefine + +`celldefine +module PVSS2ANA_V_G (AVSS); + inout AVSS; + tran (AVSS, AVSS); +endmodule + +`endcelldefine + +`celldefine +module PVSS2DGZ_H_G (VSSPST); + inout VSSPST; + tran (VSSPST,VSSPST); +endmodule +`endcelldefine + +`celldefine +module PVSS2DGZ_V_G (VSSPST); + inout VSSPST; + tran (VSSPST,VSSPST); +endmodule +`endcelldefine + +`celldefine +module PVSS3A_H_G (AVSS,TAVSS); + inout AVSS,TAVSS; + tran (AVSS,TAVSS); +endmodule +`endcelldefine + +`celldefine +module PVSS3A_V_G (AVSS,TAVSS); + inout AVSS,TAVSS; + tran (AVSS,TAVSS); +endmodule +`endcelldefine + +`celldefine +module PVSS3AC_H_G (AVSS,TACVSS); + inout AVSS,TACVSS; + tran (AVSS,TACVSS); +endmodule +`endcelldefine + +`celldefine +module PVSS3AC_V_G (AVSS,TACVSS); + inout AVSS,TACVSS; + tran (AVSS,TACVSS); +endmodule +`endcelldefine + +`celldefine +module PVSS3DGZ_H_G (VSS); + inout VSS; + tran (VSS,VSS); +endmodule +`endcelldefine + +`celldefine +module PVSS3DGZ_V_G (VSS); + inout VSS; + tran (VSS,VSS); +endmodule +`endcelldefine + diff --git a/rtl/memory/dpram.v b/rtl/memory/dpram.v new file mode 100644 index 0000000..053b29b --- /dev/null +++ b/rtl/memory/dpram.v @@ -0,0 +1,90 @@ + +`include "../define/chip_define.v" +//`define TSMC_INITIALIZE_MEM +module dpram #( + parameter DATAWIDTH = 32 + ,parameter ADDRWIDTH = 13 +)( + input PortClk + ,input [ADDRWIDTH-1 :0] PortAAddr + ,input [DATAWIDTH-1 :0] PortADataIn + ,input PortAWriteEnable //active low + ,input PortAChipEnable //active low + ,input [(DATAWIDTH/8)-1 :0] PortAByteWriteEnable //active low + ,output [DATAWIDTH-1 :0] PortADataOut + + ,input [ADDRWIDTH-1 :0] PortBAddr + ,input [DATAWIDTH-1 :0] PortBDataIn + ,input PortBWriteEnable //active low + ,input PortBChipEnable //active low + ,input [(DATAWIDTH/8)-1 :0] PortBByteWriteEnable //active low + ,output [DATAWIDTH-1 :0] PortBDataOut +); + +//================================================================================== +//XPM¡¡£í£å£í£ï£ò£ù +//================================================================================== + +`ifdef BEHAVIOR_SIM + dpram_model #( + .DATAWIDTH ( DATAWIDTH ) + ,.ADDRWIDTH ( ADDRWIDTH ) + ) dpram_model ( + .PortClk ( PortClk ) + ,.PortAWriteEnable ( PortAWriteEnable ) + ,.PortAChipEnable ( PortAChipEnable ) + ,.PortAByteWriteEnable ( PortAByteWriteEnable ) + ,.PortAAddr ( PortAAddr ) + ,.PortADataIn ( PortADataIn ) + ,.PortADataOut ( PortADataOut ) + ,.PortBWriteEnable ( PortBWriteEnable ) + ,.PortBChipEnable ( PortBChipEnable ) + ,.PortBByteWriteEnable ( PortBByteWriteEnable_w ) + ,.PortBAddr ( PortBAddr ) + ,.PortBDataIn ( PortBDataIn ) + ,.PortBDataOut ( PortBDataOut ) + ); +`elsif XINLINX_FPGA + xil_tdpram #( + .DATAWIDTH ( DATAWIDTH ) + ,.ADDRWIDTH ( ADDRWIDTH ) + ) U_xil_tdpram ( + .PortClk ( PortClk ) + ,.PortAAddr ( PortAAddr ) + ,.PortADataIn ( PortADataIn ) + ,.PortAWriteEnable ( PortAWriteEnable ) + ,.PortAChipEnable ( PortAChipEnable ) + ,.PortAByteWriteEnable ( PortAByteWriteEnable ) + ,.PortADataOut ( PortADataOut ) + ,.PortBAddr ( PortBAddr ) + ,.PortBDataIn ( PortBDataIn ) + ,.PortBWriteEnable ( PortBWriteEnable ) + ,.PortBChipEnable ( PortBChipEnable ) + ,.PortBByteWriteEnable ( PortBByteWriteEnable ) + ,.PortBDataOut ( PortBDataOut ) + ); +`elsif TSMC_IC + tsmc_dpram #( + .DATAWIDTH ( DATAWIDTH ) + ,.ADDRWIDTH ( ADDRWIDTH ) + ) U_tsmc_dpram ( + .PortClk ( PortClk ) + ,.PortAAddr ( PortAAddr ) + ,.PortADataIn ( PortADataIn ) + ,.PortAWriteEnable ( PortAWriteEnable ) + ,.PortAChipEnable ( PortAChipEnable ) + ,.PortAByteWriteEnable ( PortAByteWriteEnable ) + ,.PortADataOut ( PortADataOut ) + ,.PortBAddr ( PortBAddr ) + ,.PortBDataIn ( PortBDataIn ) + ,.PortBWriteEnable ( PortBWriteEnable ) + ,.PortBChipEnable ( PortBChipEnable ) + ,.PortBByteWriteEnable ( PortBByteWriteEnable ) + ,.PortBDataOut ( PortBDataOut ) + ); +`endif + + +endmodule + +`include "../define/chip_undefine.v" diff --git a/rtl/memory/dpram_model.v b/rtl/memory/dpram_model.v new file mode 100644 index 0000000..4b1d588 --- /dev/null +++ b/rtl/memory/dpram_model.v @@ -0,0 +1,100 @@ +//+FHDR-------------------------------------------------------------------------------------------------------- +// Company: +//----------------------------------------------------------------------------------------------------------------- +// File Name : ssram_model.v +// Department : +// Author : PWY +// Author's Tel : +//----------------------------------------------------------------------------------------------------------------- +// Relese History +// Version Date Author Description +// 1.0 2022-08-25 PWY +//----------------------------------------------------------------------------------------------------------------- +// Keywords : +// +//----------------------------------------------------------------------------------------------------------------- +// Parameter +// +//----------------------------------------------------------------------------------------------------------------- +// Purpose : +// +//----------------------------------------------------------------------------------------------------------------- +// Target Device: +// Tool versions: +//----------------------------------------------------------------------------------------------------------------- +// Reuse Issues +// Reset Strategy: +// Clock Domains: +// Critical Timing: +// Asynchronous I/F: +// Synthesizable (y/n): +// Other: +//-FHDR-------------------------------------------------------------------------------------------------------- + +module dpram_model #( + parameter DATAWIDTH = 32 + ,parameter ADDRWIDTH = 13 +)( + input PortClk + ,input [(ADDRWIDTH-1) :0] PortAAddr + ,input [(DATAWIDTH-1) :0] PortADataIn + ,input PortAWriteEnable + ,input PortAChipEnable //active low + ,input [(DATAWIDTH/8)-1:0] PortAByteWriteEnable + ,output reg [(DATAWIDTH-1) :0] PortADataOut + + ,input [(ADDRWIDTH-1) :0] PortBAddr + ,input [(DATAWIDTH-1) :0] PortBDataIn + ,input PortBWriteEnable + ,input PortBChipEnable //active low + ,input [(DATAWIDTH/8)-1:0] PortBByteWriteEnable + ,output reg [(DATAWIDTH-1) :0] PortBDataOut +); + + + +//////////////////////////////////////////////////////////////////////////////// +//Function +//////////////////////////////////////////////////////////////////////////////// +function integer clog2(input integer bit_depth); + begin + for(clog2=0;bit_depth>0;clog2=clog2+1) + bit_depth =bit_depth>>1; + end +endfunction + +localparam LSB = clog2(DATAWIDTH/8 -1); + +localparam NUM = DATAWIDTH/8; + +localparam MEMDEPTH = 2**(ADDRWIDTH-LSB); + +generate + genvar i; + for(i=0;i (QA[0] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[0] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[1] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[1] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[2] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[2] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[3] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[3] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[4] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[4] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[5] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[5] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[6] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[6] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[7] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[7] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[8] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[8] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[9] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[9] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[10] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[10] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[11] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[11] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[12] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[12] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[13] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[13] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[14] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[14] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[15] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[15] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[16] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[16] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[17] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[17] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[18] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[18] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[19] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[19] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[20] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[20] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[21] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[21] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[22] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[22] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[23] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[23] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[24] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[24] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[25] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[25] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[26] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[26] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[27] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[27] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[28] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[28] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[29] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[29] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[30] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[30] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[31] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[31] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[32] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[32] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[33] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[33] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[34] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[34] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[35] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[35] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[36] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[36] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[37] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[37] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[38] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[38] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[39] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[39] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[40] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[40] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[41] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[41] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[42] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[42] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[43] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[43] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[44] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[44] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[45] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[45] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[46] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[46] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[47] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[47] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[48] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[48] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[49] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[49] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[50] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[50] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[51] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[51] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[52] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[52] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[53] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[53] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[54] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[54] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[55] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[55] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[56] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[56] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[57] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[57] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[58] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[58] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[59] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[59] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[60] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[60] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[61] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[61] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[62] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[62] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[63] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[63] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[64] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[64] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[65] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[65] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[66] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[66] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[67] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[67] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[68] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[68] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[69] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[69] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[70] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[70] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[71] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[71] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[72] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[72] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[73] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[73] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[74] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[74] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[75] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[75] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[76] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[76] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[77] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[77] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[78] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[78] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[79] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[79] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[80] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[80] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[81] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[81] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[82] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[82] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[83] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[83] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[84] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[84] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[85] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[85] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[86] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[86] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[87] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[87] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[88] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[88] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[89] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[89] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[90] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[90] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[91] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[91] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[92] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[92] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[93] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[93] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[94] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[94] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[95] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[95] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[96] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[96] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[97] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[97] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[98] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[98] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[99] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[99] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[100] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[100] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[101] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[101] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[102] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[102] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[103] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[103] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[104] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[104] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[105] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[105] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[106] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[106] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[107] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[107] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[108] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[108] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[109] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[109] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[110] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[110] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[111] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[111] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[112] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[112] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[113] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[113] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[114] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[114] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[115] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[115] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[116] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[116] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[117] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[117] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[118] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[118] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[119] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[119] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[120] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[120] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[121] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[121] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[122] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[122] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[123] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[123] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[124] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[124] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[125] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[125] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[126] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[126] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[127] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[127] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +endspecify +`endif + +initial begin + assign EN = 1; + RDA = 1; + RDB = 1; + ABL = 1'b1; + AAL = {M{1'b0}}; + BWEBAL = {N{1'b1}}; + BWEBBL = {N{1'b1}}; + CEBAL = 1'b1; + CEBBL = 1'b1; + clk_count = 0; + sd_mode = 0; + invalid_aslp = 1'b0; + invalid_bslp = 1'b0; + invalid_adslp = 1'b0; + invalid_bdslp = 1'b0; + invalid_sdwk_dslp = 1'b0; +end + +`ifdef TSMC_INITIALIZE_MEM +initial + begin +`ifdef TSMC_INITIALIZE_FORMAT_BINARY + #(INITIAL_MEM_DELAY) $readmemb(cdeFileInit, MX.mem, 0, W-1); +`else + #(INITIAL_MEM_DELAY) $readmemh(cdeFileInit, MX.mem, 0, W-1); +`endif + end +`endif // `ifdef TSMC_INITIALIZE_MEM + +`ifdef TSMC_INITIALIZE_FAULT +initial + begin +`ifdef TSMC_INITIALIZE_FORMAT_BINARY + #(INITIAL_FAULT_DELAY) $readmemb(cdeFileFault, MX.mem_fault, 0, W-1); +`else + #(INITIAL_FAULT_DELAY) $readmemh(cdeFileFault, MX.mem_fault, 0, W-1); +`endif + end +`endif // `ifdef TSMC_INITIALIZE_FAULT + + +always @(bRTSEL) begin + if (bSLP === 1'b0 && bDSLP === 1'b0 && bSD === 1'b0) begin + if(($realtime > 0) && (!CEBAL || !CEBBL) ) begin +`ifdef no_warning +`else + $display("\tWarning %m : input RTSEL should not be toggled when CEBA/CEBB is low at simulation time %t\n", $realtime); +`endif + `ifdef TSMC_CM_UNIT_DELAY + #(SRAM_DELAY); + `endif + bQA = {N{1'bx}}; + bQB = {N{1'bx}}; + xMemoryAll; + end + end +end +always @(bWTSEL) begin + if (bSLP === 1'b0 && bDSLP === 1'b0 && bSD === 1'b0) begin + if(($realtime > 0) && (!CEBAL || !CEBBL) ) begin +`ifdef no_warning +`else + $display("\tWarning %m : input WTSEL should not be toggled when CEBA/CEBB is low at simulation time %t\n", $realtime); +`endif + `ifdef TSMC_CM_UNIT_DELAY + #(SRAM_DELAY); + `endif + bQA = {N{1'bx}}; + bQB = {N{1'bx}}; + xMemoryAll; + end + end +end +always @(bPTSEL) begin + if (bSLP === 1'b0 && bDSLP === 1'b0 && bSD === 1'b0) begin + if(($realtime > 0) && (!CEBAL || !CEBBL) ) begin +`ifdef no_warning +`else + $display("\tWarning %m : input PTSEL should not be toggled when CEBA/CEBB is low at simulation time %t\n", $realtime); +`endif + `ifdef TSMC_CM_UNIT_DELAY + #(SRAM_DELAY); + `endif + bQA = {N{1'bx}}; + bQB = {N{1'bx}}; + xMemoryAll; + end + end +end + +`ifdef TSMC_NO_TESTPINS_WARNING +`else +always @(bCLKA or bCLKB or bRTSEL) +begin + if(bSLP === 1'b0 && bDSLP === 1'b0 && bSD === 1'b0) begin + if((bRTSEL !== 2'b00) && ($realtime > 0)) + begin + $display("\tError %m : input RTSEL should be set to 2'b00 at simulation time %t\n", $realtime); + $display("\tError %m : Please refer the datasheet for the RTSEL setting in the different segment and mux configuration\n"); + bQA <= #0.01 {N{1'bx}}; + bQB <= #0.01 {N{1'bx}}; + AAL <= {M{1'bx}}; + BWEBAL <= {N{1'b0}}; + end + end +end + +always @(bCLKA or bCLKB or bWTSEL) +begin + if(bSLP === 1'b0 && bDSLP === 1'b0 && bSD === 1'b0) begin + if((bWTSEL !== 2'b00) && ($realtime > 0)) + begin + $display("\tError %m : input WTSEL should be set to 2'b00 at simulation time %t\n", $realtime); + $display("\tError %m : Please refer the datasheet for the WTSEL setting in the different segment and mux configuration\n"); + bQA <= #0.01 {N{1'bx}}; + bQB <= #0.01 {N{1'bx}}; + AAL <= {M{1'bx}}; + BWEBAL <= {N{1'b0}}; + end + end +end + +always @(bCLKA or bCLKB or bPTSEL) +begin + if(bSLP === 1'b0 && bDSLP === 1'b0 && bSD === 1'b0) begin + if((bPTSEL !== 2'b00) && ($realtime > 0)) + begin + $display("\tError %m : input PTSEL should be set to 2'b00 at simulation time %t\n", $realtime); + $display("\tError %m : Please refer the datasheet for the PTSEL setting in the different segment and mux configuration\n"); + bQA <= #0.01 {N{1'bx}}; + bQB <= #0.01 {N{1'bx}}; + AAL <= {M{1'bx}}; + BWEBAL <= {N{1'b0}}; + end + end +end + +`endif + +//always @(bTMA or bTMB) begin +// if(bSLP === 1'b0 && bDSLP === 1'b0 && bSD === 1'b0 && bTMA === 1'b1 && bTMB === 1'b1) begin +// if( MES_ALL=="ON" && $realtime != 0) +// begin +// $display("\nWarning %m : TMA and TMB cannot both be 1 at the same time, at %t. >>", $realtime); +// end +// xMemoryAll; +//`ifdef TSMC_CM_UNIT_DELAY +// bQA <= #(SRAM_DELAY + 0.001) {N{1'bx}}; +// bQB <= #(SRAM_DELAY + 0.001) {N{1'bx}}; +//`else +// bQA <= #0.01 {N{1'bx}}; +// bQB <= #0.01 {N{1'bx}}; +//`endif +// end +//end + +always @(bCLKA) +begin : CLKAOP + if(bSLP === 1'b0 && bDSLP === 1'b0 && bSD === 1'b0 && invalid_sdwk_dslp === 1'b0) begin + if(bCLKA === 1'bx) + begin + if( MES_ALL=="ON" && $realtime != 0) + begin + $display("\nWarning %m : CLK unknown at %t. >>", $realtime); + end + xMemoryAll; + bQA <= #0.01 {N{1'bx}}; + end + else if(bCLKA === 1'b1 && RCLKA === 1'b0) + begin + if(bCEBA === 1'bx) + begin + if( MES_ALL=="ON" && $realtime != 0) + begin + $display("\nWarning %m CEBA unknown at %t. >>", $realtime); + end + xMemoryAll; + bQA <= #0.01 {N{1'bx}}; + end + else if(bWEBA === 1'bx && bCEBA === 1'b0) + begin + if( MES_ALL=="ON" && $realtime != 0) + begin + $display("\nWarning %m WEBA unknown at %t. >>", $realtime); + end + xMemoryAll; + bQA <= #0.01 {N{1'bx}}; + end + else begin + WEBAL = bWEBA; + CEBAL = bCEBA; + if(^bAA === 1'bx && bWEBA === 1'b0 && bCEBA === 1'b0) + begin + if( MES_ALL=="ON" && $realtime != 0) + begin + $display("\nWarning %m WRITE AA unknown at %t. >>", $realtime); + end + xMemoryAll; + end + else if(^bAA === 1'bx && bWEBA === 1'b1 && bCEBA === 1'b0) + begin + if( MES_ALL=="ON" && $realtime != 0) + begin + $display("\nWarning %m READ AA unknown at %t. >>", $realtime); + end + xMemoryAll; + bQA <= #0.01 {N{1'bx}}; + end + else + begin + if(!bCEBA) + begin // begin if(bCEBA) + AAL = bAA; + DAL = bDA; + if(bWEBA === 1'b1 && clk_count == 0) + begin + RDA = ~RDA; + end + if(bWEBA === 1'b0) + begin + for (i = 0; i < N; i = i + 1) + begin + if(!bBWEBA[i] && !bWEBA) + begin + BWEBAL[i] = 1'b0; + end + if(bWEBA === 1'bx || bBWEBA[i] === 1'bx) + begin + BWEBAL[i] = 1'b0; + DAL[i] = 1'bx; + end + end + if(^bBWEBA === 1'bx) + begin + if( MES_ALL=="ON" && $realtime != 0) + begin + $display("\nWarning %m BWEBA unknown at %t. >>", $realtime); + end + end + end + end + end + end + + CEBBL = bCEBB; + if(bCEBB === 1'b0) begin + WEBBL = bWEBB; + ABL = bAB; + bBWEBBL = bBWEBB; + bDBL = bDB; + end + #0.001; + + if(CEBBL === 1'bx) + begin + if( MES_ALL=="ON" && $realtime != 0) + begin + $display("\nWarning %m CEBB unknown at %t. >>", $realtime); + end + xMemoryAll; + bQB <= #0.01 {N{1'bx}}; + end + else if(WEBBL === 1'bx && CEBBL === 1'b0) + begin + if( MES_ALL=="ON" && $realtime != 0) + begin + $display("\nWarning %m WEBB unknown at %t. >>", $realtime); + end + xMemoryAll; + bQB <= #0.01 {N{1'bx}}; + end + else + begin + if(^ABL === 1'bx && WEBBL === 1'b0 && CEBBL === 1'b0) + begin + if( MES_ALL=="ON" && $realtime != 0) + begin + $display("\nWarning %m WRITE AB unknown at %t. >>", $realtime); + end + xMemoryAll; + end + else if(^ABL === 1'bx && WEBBL === 1'b1 && CEBBL === 1'b0) + begin + if( MES_ALL=="ON" && $realtime != 0) + begin + $display("\nWarning %m READ AB unknown at %t. >>", $realtime); + end + xMemoryAll; + bQB <= #0.01 {N{1'bx}}; + end + else begin + if(!CEBBL) + begin // begin if(CEBBL) + DBL = bDBL; + if(WEBBL === 1'b1 && clk_count == 0) + begin + RDB = ~RDB; + end + if(WEBBL !== 1'b1) + begin + for (i = 0; i < N; i = i + 1) + begin + if(!bBWEBBL[i] && !WEBBL) + begin + BWEBBL[i] = 1'b0; + end + if(WEBBL === 1'bx || bBWEBBL[i] === 1'bx) + begin + BWEBBL[i] = 1'b0; + DBL[i] = 1'bx; + end + end + if(^bBWEBBL === 1'bx) + begin + if( MES_ALL=="ON" && $realtime != 0) + begin + $display("\nWarning %m BWEBB unknown at %t. >>", $realtime); + end + end + end + end + end + end + end + end + #0.001 RCLKA = bCLKA; + +end + + + +always @(RDA or QAL) +begin : CLKAROP + if(bSLP === 1'b0 && bDSLP === 1'b0 && bSD === 1'b0 && invalid_sdwk_dslp === 1'b0 && bAWT === 1'b0) begin + if(!CEBAL && WEBAL && clk_count == 0) + begin + begin +`ifdef TSMC_CM_UNIT_DELAY + #(SRAM_DELAY); +`else + bQA = {N{1'bx}}; + #0.01; +`endif + bQA <= QAL; + end + end // if(!CEBAL && WEBAL && clk_count == 0) + end +end // always @ (RDA or QAL) + +always @(RDB or QBL) +begin : CLKBROP + if(bSLP === 1'b0 && bDSLP === 1'b0 && bSD === 1'b0 && invalid_sdwk_dslp === 1'b0 && bAWT === 1'b0) begin + if(!CEBBL && WEBBL && clk_count == 0) + begin + begin +`ifdef TSMC_CM_UNIT_DELAY + #(SRAM_DELAY); +`else + bQB = {N{1'bx}}; + #0.01; +`endif + bQB <= QBL; + end + end // if(!bAWT && !CEBBL && WEBBL && clk_count == 0) + end +end // always @ (RDB or QBL) + + + + + +always @(BWEBAL) +begin + BWEBAL = #0.01 {N{1'b1}}; +end + +always @(BWEBBL) +begin + BWEBBL = #0.01 {N{1'b1}}; +end + + +`ifdef TSMC_CM_UNIT_DELAY +`else +always @(valid_testpin) begin + AAL <= {M{1'bx}}; + BWEBAL <= {N{1'b0}}; + BWEBBL <= {N{1'b0}}; + bQA = #0.01 {N{1'bx}}; + bQB = #0.01 {N{1'bx}}; +end + + +always @(valid_ck) +begin + if (iCEBA === 1'b0) begin + #0.002; + AAL = {M{1'bx}}; + BWEBAL = {N{1'b0}}; + bQA = #0.01 {N{1'bx}}; + end + + if (iCEBB === 1'b0) begin + #0.002; + ABL = {M{1'bx}}; + BWEBBL = {N{1'b0}}; + bQB = #0.01 {N{1'bx}}; + end +end + + +always @(valid_cka) +begin + + #0.002; + AAL = {M{1'bx}}; + BWEBAL = {N{1'b0}}; + bQA = #0.01 {N{1'bx}}; +end + +always @(valid_ckb) +begin + + #0.002; + ABL = {M{1'bx}}; + BWEBBL = {N{1'b0}}; + bQB = #0.01 {N{1'bx}}; +end + + +always @(valid_aa) +begin + + if(!WEBAL) + begin + #0.002; + BWEBAL = {N{1'b0}}; + AAL = {M{1'bx}}; + end + else + begin + #0.002; + BWEBAL = {N{1'b0}}; + AAL = {M{1'bx}}; + bQA = #0.01 {N{1'bx}}; + end +end + +always @(valid_ab) +begin + + if(!WEBBL) + begin + BWEBBL = {N{1'b0}}; + ABL = {M{1'bx}}; + end + else + begin + #0.002; + BWEBBL = {N{1'b0}}; + ABL = {M{1'bx}}; + bQB = #0.01 {N{1'bx}}; + end +end + +always @(valid_da0) +begin + + DAL[0] = 1'bx; + BWEBAL[0] = 1'b0; +end + +always @(valid_db0) +begin + disable CLKAOP; + DBL[0] = 1'bx; + BWEBBL[0] = 1'b0; +end + +always @(valid_bwa0) +begin + + DAL[0] = 1'bx; + BWEBAL[0] = 1'b0; +end + +always @(valid_bwb0) +begin + disable CLKAOP; + DBL[0] = 1'bx; + BWEBBL[0] = 1'b0; +end +always @(valid_da1) +begin + + DAL[1] = 1'bx; + BWEBAL[1] = 1'b0; +end + +always @(valid_db1) +begin + disable CLKAOP; + DBL[1] = 1'bx; + BWEBBL[1] = 1'b0; +end + +always @(valid_bwa1) +begin + + DAL[1] = 1'bx; + BWEBAL[1] = 1'b0; +end + +always @(valid_bwb1) +begin + disable CLKAOP; + DBL[1] = 1'bx; + BWEBBL[1] = 1'b0; +end +always @(valid_da2) +begin + + DAL[2] = 1'bx; + BWEBAL[2] = 1'b0; +end + +always @(valid_db2) +begin + disable CLKAOP; + DBL[2] = 1'bx; + BWEBBL[2] = 1'b0; +end + +always @(valid_bwa2) +begin + + DAL[2] = 1'bx; + BWEBAL[2] = 1'b0; +end + +always @(valid_bwb2) +begin + disable CLKAOP; + DBL[2] = 1'bx; + BWEBBL[2] = 1'b0; +end +always @(valid_da3) +begin + + DAL[3] = 1'bx; + BWEBAL[3] = 1'b0; +end + +always @(valid_db3) +begin + disable CLKAOP; + DBL[3] = 1'bx; + BWEBBL[3] = 1'b0; +end + +always @(valid_bwa3) +begin + + DAL[3] = 1'bx; + BWEBAL[3] = 1'b0; +end + +always @(valid_bwb3) +begin + disable CLKAOP; + DBL[3] = 1'bx; + BWEBBL[3] = 1'b0; +end +always @(valid_da4) +begin + + DAL[4] = 1'bx; + BWEBAL[4] = 1'b0; +end + +always @(valid_db4) +begin + disable CLKAOP; + DBL[4] = 1'bx; + BWEBBL[4] = 1'b0; +end + +always @(valid_bwa4) +begin + + DAL[4] = 1'bx; + BWEBAL[4] = 1'b0; +end + +always @(valid_bwb4) +begin + disable CLKAOP; + DBL[4] = 1'bx; + BWEBBL[4] = 1'b0; +end +always @(valid_da5) +begin + + DAL[5] = 1'bx; + BWEBAL[5] = 1'b0; +end + +always @(valid_db5) +begin + disable CLKAOP; + DBL[5] = 1'bx; + BWEBBL[5] = 1'b0; +end + +always @(valid_bwa5) +begin + + DAL[5] = 1'bx; + BWEBAL[5] = 1'b0; +end + +always @(valid_bwb5) +begin + disable CLKAOP; + DBL[5] = 1'bx; + BWEBBL[5] = 1'b0; +end +always @(valid_da6) +begin + + DAL[6] = 1'bx; + BWEBAL[6] = 1'b0; +end + +always @(valid_db6) +begin + disable CLKAOP; + DBL[6] = 1'bx; + BWEBBL[6] = 1'b0; +end + +always @(valid_bwa6) +begin + + DAL[6] = 1'bx; + BWEBAL[6] = 1'b0; +end + +always @(valid_bwb6) +begin + disable CLKAOP; + DBL[6] = 1'bx; + BWEBBL[6] = 1'b0; +end +always @(valid_da7) +begin + + DAL[7] = 1'bx; + BWEBAL[7] = 1'b0; +end + +always @(valid_db7) +begin + disable CLKAOP; + DBL[7] = 1'bx; + BWEBBL[7] = 1'b0; +end + +always @(valid_bwa7) +begin + + DAL[7] = 1'bx; + BWEBAL[7] = 1'b0; +end + +always @(valid_bwb7) +begin + disable CLKAOP; + DBL[7] = 1'bx; + BWEBBL[7] = 1'b0; +end +always @(valid_da8) +begin + + DAL[8] = 1'bx; + BWEBAL[8] = 1'b0; +end + +always @(valid_db8) +begin + disable CLKAOP; + DBL[8] = 1'bx; + BWEBBL[8] = 1'b0; +end + +always @(valid_bwa8) +begin + + DAL[8] = 1'bx; + BWEBAL[8] = 1'b0; +end + +always @(valid_bwb8) +begin + disable CLKAOP; + DBL[8] = 1'bx; + BWEBBL[8] = 1'b0; +end +always @(valid_da9) +begin + + DAL[9] = 1'bx; + BWEBAL[9] = 1'b0; +end + +always @(valid_db9) +begin + disable CLKAOP; + DBL[9] = 1'bx; + BWEBBL[9] = 1'b0; +end + +always @(valid_bwa9) +begin + + DAL[9] = 1'bx; + BWEBAL[9] = 1'b0; +end + +always @(valid_bwb9) +begin + disable CLKAOP; + DBL[9] = 1'bx; + BWEBBL[9] = 1'b0; +end +always @(valid_da10) +begin + + DAL[10] = 1'bx; + BWEBAL[10] = 1'b0; +end + +always @(valid_db10) +begin + disable CLKAOP; + DBL[10] = 1'bx; + BWEBBL[10] = 1'b0; +end + +always @(valid_bwa10) +begin + + DAL[10] = 1'bx; + BWEBAL[10] = 1'b0; +end + +always @(valid_bwb10) +begin + disable CLKAOP; + DBL[10] = 1'bx; + BWEBBL[10] = 1'b0; +end +always @(valid_da11) +begin + + DAL[11] = 1'bx; + BWEBAL[11] = 1'b0; +end + +always @(valid_db11) +begin + disable CLKAOP; + DBL[11] = 1'bx; + BWEBBL[11] = 1'b0; +end + +always @(valid_bwa11) +begin + + DAL[11] = 1'bx; + BWEBAL[11] = 1'b0; +end + +always @(valid_bwb11) +begin + disable CLKAOP; + DBL[11] = 1'bx; + BWEBBL[11] = 1'b0; +end +always @(valid_da12) +begin + + DAL[12] = 1'bx; + BWEBAL[12] = 1'b0; +end + +always @(valid_db12) +begin + disable CLKAOP; + DBL[12] = 1'bx; + BWEBBL[12] = 1'b0; +end + +always @(valid_bwa12) +begin + + DAL[12] = 1'bx; + BWEBAL[12] = 1'b0; +end + +always @(valid_bwb12) +begin + disable CLKAOP; + DBL[12] = 1'bx; + BWEBBL[12] = 1'b0; +end +always @(valid_da13) +begin + + DAL[13] = 1'bx; + BWEBAL[13] = 1'b0; +end + +always @(valid_db13) +begin + disable CLKAOP; + DBL[13] = 1'bx; + BWEBBL[13] = 1'b0; +end + +always @(valid_bwa13) +begin + + DAL[13] = 1'bx; + BWEBAL[13] = 1'b0; +end + +always @(valid_bwb13) +begin + disable CLKAOP; + DBL[13] = 1'bx; + BWEBBL[13] = 1'b0; +end +always @(valid_da14) +begin + + DAL[14] = 1'bx; + BWEBAL[14] = 1'b0; +end + +always @(valid_db14) +begin + disable CLKAOP; + DBL[14] = 1'bx; + BWEBBL[14] = 1'b0; +end + +always @(valid_bwa14) +begin + + DAL[14] = 1'bx; + BWEBAL[14] = 1'b0; +end + +always @(valid_bwb14) +begin + disable CLKAOP; + DBL[14] = 1'bx; + BWEBBL[14] = 1'b0; +end +always @(valid_da15) +begin + + DAL[15] = 1'bx; + BWEBAL[15] = 1'b0; +end + +always @(valid_db15) +begin + disable CLKAOP; + DBL[15] = 1'bx; + BWEBBL[15] = 1'b0; +end + +always @(valid_bwa15) +begin + + DAL[15] = 1'bx; + BWEBAL[15] = 1'b0; +end + +always @(valid_bwb15) +begin + disable CLKAOP; + DBL[15] = 1'bx; + BWEBBL[15] = 1'b0; +end +always @(valid_da16) +begin + + DAL[16] = 1'bx; + BWEBAL[16] = 1'b0; +end + +always @(valid_db16) +begin + disable CLKAOP; + DBL[16] = 1'bx; + BWEBBL[16] = 1'b0; +end + +always @(valid_bwa16) +begin + + DAL[16] = 1'bx; + BWEBAL[16] = 1'b0; +end + +always @(valid_bwb16) +begin + disable CLKAOP; + DBL[16] = 1'bx; + BWEBBL[16] = 1'b0; +end +always @(valid_da17) +begin + + DAL[17] = 1'bx; + BWEBAL[17] = 1'b0; +end + +always @(valid_db17) +begin + disable CLKAOP; + DBL[17] = 1'bx; + BWEBBL[17] = 1'b0; +end + +always @(valid_bwa17) +begin + + DAL[17] = 1'bx; + BWEBAL[17] = 1'b0; +end + +always @(valid_bwb17) +begin + disable CLKAOP; + DBL[17] = 1'bx; + BWEBBL[17] = 1'b0; +end +always @(valid_da18) +begin + + DAL[18] = 1'bx; + BWEBAL[18] = 1'b0; +end + +always @(valid_db18) +begin + disable CLKAOP; + DBL[18] = 1'bx; + BWEBBL[18] = 1'b0; +end + +always @(valid_bwa18) +begin + + DAL[18] = 1'bx; + BWEBAL[18] = 1'b0; +end + +always @(valid_bwb18) +begin + disable CLKAOP; + DBL[18] = 1'bx; + BWEBBL[18] = 1'b0; +end +always @(valid_da19) +begin + + DAL[19] = 1'bx; + BWEBAL[19] = 1'b0; +end + +always @(valid_db19) +begin + disable CLKAOP; + DBL[19] = 1'bx; + BWEBBL[19] = 1'b0; +end + +always @(valid_bwa19) +begin + + DAL[19] = 1'bx; + BWEBAL[19] = 1'b0; +end + +always @(valid_bwb19) +begin + disable CLKAOP; + DBL[19] = 1'bx; + BWEBBL[19] = 1'b0; +end +always @(valid_da20) +begin + + DAL[20] = 1'bx; + BWEBAL[20] = 1'b0; +end + +always @(valid_db20) +begin + disable CLKAOP; + DBL[20] = 1'bx; + BWEBBL[20] = 1'b0; +end + +always @(valid_bwa20) +begin + + DAL[20] = 1'bx; + BWEBAL[20] = 1'b0; +end + +always @(valid_bwb20) +begin + disable CLKAOP; + DBL[20] = 1'bx; + BWEBBL[20] = 1'b0; +end +always @(valid_da21) +begin + + DAL[21] = 1'bx; + BWEBAL[21] = 1'b0; +end + +always @(valid_db21) +begin + disable CLKAOP; + DBL[21] = 1'bx; + BWEBBL[21] = 1'b0; +end + +always @(valid_bwa21) +begin + + DAL[21] = 1'bx; + BWEBAL[21] = 1'b0; +end + +always @(valid_bwb21) +begin + disable CLKAOP; + DBL[21] = 1'bx; + BWEBBL[21] = 1'b0; +end +always @(valid_da22) +begin + + DAL[22] = 1'bx; + BWEBAL[22] = 1'b0; +end + +always @(valid_db22) +begin + disable CLKAOP; + DBL[22] = 1'bx; + BWEBBL[22] = 1'b0; +end + +always @(valid_bwa22) +begin + + DAL[22] = 1'bx; + BWEBAL[22] = 1'b0; +end + +always @(valid_bwb22) +begin + disable CLKAOP; + DBL[22] = 1'bx; + BWEBBL[22] = 1'b0; +end +always @(valid_da23) +begin + + DAL[23] = 1'bx; + BWEBAL[23] = 1'b0; +end + +always @(valid_db23) +begin + disable CLKAOP; + DBL[23] = 1'bx; + BWEBBL[23] = 1'b0; +end + +always @(valid_bwa23) +begin + + DAL[23] = 1'bx; + BWEBAL[23] = 1'b0; +end + +always @(valid_bwb23) +begin + disable CLKAOP; + DBL[23] = 1'bx; + BWEBBL[23] = 1'b0; +end +always @(valid_da24) +begin + + DAL[24] = 1'bx; + BWEBAL[24] = 1'b0; +end + +always @(valid_db24) +begin + disable CLKAOP; + DBL[24] = 1'bx; + BWEBBL[24] = 1'b0; +end + +always @(valid_bwa24) +begin + + DAL[24] = 1'bx; + BWEBAL[24] = 1'b0; +end + +always @(valid_bwb24) +begin + disable CLKAOP; + DBL[24] = 1'bx; + BWEBBL[24] = 1'b0; +end +always @(valid_da25) +begin + + DAL[25] = 1'bx; + BWEBAL[25] = 1'b0; +end + +always @(valid_db25) +begin + disable CLKAOP; + DBL[25] = 1'bx; + BWEBBL[25] = 1'b0; +end + +always @(valid_bwa25) +begin + + DAL[25] = 1'bx; + BWEBAL[25] = 1'b0; +end + +always @(valid_bwb25) +begin + disable CLKAOP; + DBL[25] = 1'bx; + BWEBBL[25] = 1'b0; +end +always @(valid_da26) +begin + + DAL[26] = 1'bx; + BWEBAL[26] = 1'b0; +end + +always @(valid_db26) +begin + disable CLKAOP; + DBL[26] = 1'bx; + BWEBBL[26] = 1'b0; +end + +always @(valid_bwa26) +begin + + DAL[26] = 1'bx; + BWEBAL[26] = 1'b0; +end + +always @(valid_bwb26) +begin + disable CLKAOP; + DBL[26] = 1'bx; + BWEBBL[26] = 1'b0; +end +always @(valid_da27) +begin + + DAL[27] = 1'bx; + BWEBAL[27] = 1'b0; +end + +always @(valid_db27) +begin + disable CLKAOP; + DBL[27] = 1'bx; + BWEBBL[27] = 1'b0; +end + +always @(valid_bwa27) +begin + + DAL[27] = 1'bx; + BWEBAL[27] = 1'b0; +end + +always @(valid_bwb27) +begin + disable CLKAOP; + DBL[27] = 1'bx; + BWEBBL[27] = 1'b0; +end +always @(valid_da28) +begin + + DAL[28] = 1'bx; + BWEBAL[28] = 1'b0; +end + +always @(valid_db28) +begin + disable CLKAOP; + DBL[28] = 1'bx; + BWEBBL[28] = 1'b0; +end + +always @(valid_bwa28) +begin + + DAL[28] = 1'bx; + BWEBAL[28] = 1'b0; +end + +always @(valid_bwb28) +begin + disable CLKAOP; + DBL[28] = 1'bx; + BWEBBL[28] = 1'b0; +end +always @(valid_da29) +begin + + DAL[29] = 1'bx; + BWEBAL[29] = 1'b0; +end + +always @(valid_db29) +begin + disable CLKAOP; + DBL[29] = 1'bx; + BWEBBL[29] = 1'b0; +end + +always @(valid_bwa29) +begin + + DAL[29] = 1'bx; + BWEBAL[29] = 1'b0; +end + +always @(valid_bwb29) +begin + disable CLKAOP; + DBL[29] = 1'bx; + BWEBBL[29] = 1'b0; +end +always @(valid_da30) +begin + + DAL[30] = 1'bx; + BWEBAL[30] = 1'b0; +end + +always @(valid_db30) +begin + disable CLKAOP; + DBL[30] = 1'bx; + BWEBBL[30] = 1'b0; +end + +always @(valid_bwa30) +begin + + DAL[30] = 1'bx; + BWEBAL[30] = 1'b0; +end + +always @(valid_bwb30) +begin + disable CLKAOP; + DBL[30] = 1'bx; + BWEBBL[30] = 1'b0; +end +always @(valid_da31) +begin + + DAL[31] = 1'bx; + BWEBAL[31] = 1'b0; +end + +always @(valid_db31) +begin + disable CLKAOP; + DBL[31] = 1'bx; + BWEBBL[31] = 1'b0; +end + +always @(valid_bwa31) +begin + + DAL[31] = 1'bx; + BWEBAL[31] = 1'b0; +end + +always @(valid_bwb31) +begin + disable CLKAOP; + DBL[31] = 1'bx; + BWEBBL[31] = 1'b0; +end +always @(valid_da32) +begin + + DAL[32] = 1'bx; + BWEBAL[32] = 1'b0; +end + +always @(valid_db32) +begin + disable CLKAOP; + DBL[32] = 1'bx; + BWEBBL[32] = 1'b0; +end + +always @(valid_bwa32) +begin + + DAL[32] = 1'bx; + BWEBAL[32] = 1'b0; +end + +always @(valid_bwb32) +begin + disable CLKAOP; + DBL[32] = 1'bx; + BWEBBL[32] = 1'b0; +end +always @(valid_da33) +begin + + DAL[33] = 1'bx; + BWEBAL[33] = 1'b0; +end + +always @(valid_db33) +begin + disable CLKAOP; + DBL[33] = 1'bx; + BWEBBL[33] = 1'b0; +end + +always @(valid_bwa33) +begin + + DAL[33] = 1'bx; + BWEBAL[33] = 1'b0; +end + +always @(valid_bwb33) +begin + disable CLKAOP; + DBL[33] = 1'bx; + BWEBBL[33] = 1'b0; +end +always @(valid_da34) +begin + + DAL[34] = 1'bx; + BWEBAL[34] = 1'b0; +end + +always @(valid_db34) +begin + disable CLKAOP; + DBL[34] = 1'bx; + BWEBBL[34] = 1'b0; +end + +always @(valid_bwa34) +begin + + DAL[34] = 1'bx; + BWEBAL[34] = 1'b0; +end + +always @(valid_bwb34) +begin + disable CLKAOP; + DBL[34] = 1'bx; + BWEBBL[34] = 1'b0; +end +always @(valid_da35) +begin + + DAL[35] = 1'bx; + BWEBAL[35] = 1'b0; +end + +always @(valid_db35) +begin + disable CLKAOP; + DBL[35] = 1'bx; + BWEBBL[35] = 1'b0; +end + +always @(valid_bwa35) +begin + + DAL[35] = 1'bx; + BWEBAL[35] = 1'b0; +end + +always @(valid_bwb35) +begin + disable CLKAOP; + DBL[35] = 1'bx; + BWEBBL[35] = 1'b0; +end +always @(valid_da36) +begin + + DAL[36] = 1'bx; + BWEBAL[36] = 1'b0; +end + +always @(valid_db36) +begin + disable CLKAOP; + DBL[36] = 1'bx; + BWEBBL[36] = 1'b0; +end + +always @(valid_bwa36) +begin + + DAL[36] = 1'bx; + BWEBAL[36] = 1'b0; +end + +always @(valid_bwb36) +begin + disable CLKAOP; + DBL[36] = 1'bx; + BWEBBL[36] = 1'b0; +end +always @(valid_da37) +begin + + DAL[37] = 1'bx; + BWEBAL[37] = 1'b0; +end + +always @(valid_db37) +begin + disable CLKAOP; + DBL[37] = 1'bx; + BWEBBL[37] = 1'b0; +end + +always @(valid_bwa37) +begin + + DAL[37] = 1'bx; + BWEBAL[37] = 1'b0; +end + +always @(valid_bwb37) +begin + disable CLKAOP; + DBL[37] = 1'bx; + BWEBBL[37] = 1'b0; +end +always @(valid_da38) +begin + + DAL[38] = 1'bx; + BWEBAL[38] = 1'b0; +end + +always @(valid_db38) +begin + disable CLKAOP; + DBL[38] = 1'bx; + BWEBBL[38] = 1'b0; +end + +always @(valid_bwa38) +begin + + DAL[38] = 1'bx; + BWEBAL[38] = 1'b0; +end + +always @(valid_bwb38) +begin + disable CLKAOP; + DBL[38] = 1'bx; + BWEBBL[38] = 1'b0; +end +always @(valid_da39) +begin + + DAL[39] = 1'bx; + BWEBAL[39] = 1'b0; +end + +always @(valid_db39) +begin + disable CLKAOP; + DBL[39] = 1'bx; + BWEBBL[39] = 1'b0; +end + +always @(valid_bwa39) +begin + + DAL[39] = 1'bx; + BWEBAL[39] = 1'b0; +end + +always @(valid_bwb39) +begin + disable CLKAOP; + DBL[39] = 1'bx; + BWEBBL[39] = 1'b0; +end +always @(valid_da40) +begin + + DAL[40] = 1'bx; + BWEBAL[40] = 1'b0; +end + +always @(valid_db40) +begin + disable CLKAOP; + DBL[40] = 1'bx; + BWEBBL[40] = 1'b0; +end + +always @(valid_bwa40) +begin + + DAL[40] = 1'bx; + BWEBAL[40] = 1'b0; +end + +always @(valid_bwb40) +begin + disable CLKAOP; + DBL[40] = 1'bx; + BWEBBL[40] = 1'b0; +end +always @(valid_da41) +begin + + DAL[41] = 1'bx; + BWEBAL[41] = 1'b0; +end + +always @(valid_db41) +begin + disable CLKAOP; + DBL[41] = 1'bx; + BWEBBL[41] = 1'b0; +end + +always @(valid_bwa41) +begin + + DAL[41] = 1'bx; + BWEBAL[41] = 1'b0; +end + +always @(valid_bwb41) +begin + disable CLKAOP; + DBL[41] = 1'bx; + BWEBBL[41] = 1'b0; +end +always @(valid_da42) +begin + + DAL[42] = 1'bx; + BWEBAL[42] = 1'b0; +end + +always @(valid_db42) +begin + disable CLKAOP; + DBL[42] = 1'bx; + BWEBBL[42] = 1'b0; +end + +always @(valid_bwa42) +begin + + DAL[42] = 1'bx; + BWEBAL[42] = 1'b0; +end + +always @(valid_bwb42) +begin + disable CLKAOP; + DBL[42] = 1'bx; + BWEBBL[42] = 1'b0; +end +always @(valid_da43) +begin + + DAL[43] = 1'bx; + BWEBAL[43] = 1'b0; +end + +always @(valid_db43) +begin + disable CLKAOP; + DBL[43] = 1'bx; + BWEBBL[43] = 1'b0; +end + +always @(valid_bwa43) +begin + + DAL[43] = 1'bx; + BWEBAL[43] = 1'b0; +end + +always @(valid_bwb43) +begin + disable CLKAOP; + DBL[43] = 1'bx; + BWEBBL[43] = 1'b0; +end +always @(valid_da44) +begin + + DAL[44] = 1'bx; + BWEBAL[44] = 1'b0; +end + +always @(valid_db44) +begin + disable CLKAOP; + DBL[44] = 1'bx; + BWEBBL[44] = 1'b0; +end + +always @(valid_bwa44) +begin + + DAL[44] = 1'bx; + BWEBAL[44] = 1'b0; +end + +always @(valid_bwb44) +begin + disable CLKAOP; + DBL[44] = 1'bx; + BWEBBL[44] = 1'b0; +end +always @(valid_da45) +begin + + DAL[45] = 1'bx; + BWEBAL[45] = 1'b0; +end + +always @(valid_db45) +begin + disable CLKAOP; + DBL[45] = 1'bx; + BWEBBL[45] = 1'b0; +end + +always @(valid_bwa45) +begin + + DAL[45] = 1'bx; + BWEBAL[45] = 1'b0; +end + +always @(valid_bwb45) +begin + disable CLKAOP; + DBL[45] = 1'bx; + BWEBBL[45] = 1'b0; +end +always @(valid_da46) +begin + + DAL[46] = 1'bx; + BWEBAL[46] = 1'b0; +end + +always @(valid_db46) +begin + disable CLKAOP; + DBL[46] = 1'bx; + BWEBBL[46] = 1'b0; +end + +always @(valid_bwa46) +begin + + DAL[46] = 1'bx; + BWEBAL[46] = 1'b0; +end + +always @(valid_bwb46) +begin + disable CLKAOP; + DBL[46] = 1'bx; + BWEBBL[46] = 1'b0; +end +always @(valid_da47) +begin + + DAL[47] = 1'bx; + BWEBAL[47] = 1'b0; +end + +always @(valid_db47) +begin + disable CLKAOP; + DBL[47] = 1'bx; + BWEBBL[47] = 1'b0; +end + +always @(valid_bwa47) +begin + + DAL[47] = 1'bx; + BWEBAL[47] = 1'b0; +end + +always @(valid_bwb47) +begin + disable CLKAOP; + DBL[47] = 1'bx; + BWEBBL[47] = 1'b0; +end +always @(valid_da48) +begin + + DAL[48] = 1'bx; + BWEBAL[48] = 1'b0; +end + +always @(valid_db48) +begin + disable CLKAOP; + DBL[48] = 1'bx; + BWEBBL[48] = 1'b0; +end + +always @(valid_bwa48) +begin + + DAL[48] = 1'bx; + BWEBAL[48] = 1'b0; +end + +always @(valid_bwb48) +begin + disable CLKAOP; + DBL[48] = 1'bx; + BWEBBL[48] = 1'b0; +end +always @(valid_da49) +begin + + DAL[49] = 1'bx; + BWEBAL[49] = 1'b0; +end + +always @(valid_db49) +begin + disable CLKAOP; + DBL[49] = 1'bx; + BWEBBL[49] = 1'b0; +end + +always @(valid_bwa49) +begin + + DAL[49] = 1'bx; + BWEBAL[49] = 1'b0; +end + +always @(valid_bwb49) +begin + disable CLKAOP; + DBL[49] = 1'bx; + BWEBBL[49] = 1'b0; +end +always @(valid_da50) +begin + + DAL[50] = 1'bx; + BWEBAL[50] = 1'b0; +end + +always @(valid_db50) +begin + disable CLKAOP; + DBL[50] = 1'bx; + BWEBBL[50] = 1'b0; +end + +always @(valid_bwa50) +begin + + DAL[50] = 1'bx; + BWEBAL[50] = 1'b0; +end + +always @(valid_bwb50) +begin + disable CLKAOP; + DBL[50] = 1'bx; + BWEBBL[50] = 1'b0; +end +always @(valid_da51) +begin + + DAL[51] = 1'bx; + BWEBAL[51] = 1'b0; +end + +always @(valid_db51) +begin + disable CLKAOP; + DBL[51] = 1'bx; + BWEBBL[51] = 1'b0; +end + +always @(valid_bwa51) +begin + + DAL[51] = 1'bx; + BWEBAL[51] = 1'b0; +end + +always @(valid_bwb51) +begin + disable CLKAOP; + DBL[51] = 1'bx; + BWEBBL[51] = 1'b0; +end +always @(valid_da52) +begin + + DAL[52] = 1'bx; + BWEBAL[52] = 1'b0; +end + +always @(valid_db52) +begin + disable CLKAOP; + DBL[52] = 1'bx; + BWEBBL[52] = 1'b0; +end + +always @(valid_bwa52) +begin + + DAL[52] = 1'bx; + BWEBAL[52] = 1'b0; +end + +always @(valid_bwb52) +begin + disable CLKAOP; + DBL[52] = 1'bx; + BWEBBL[52] = 1'b0; +end +always @(valid_da53) +begin + + DAL[53] = 1'bx; + BWEBAL[53] = 1'b0; +end + +always @(valid_db53) +begin + disable CLKAOP; + DBL[53] = 1'bx; + BWEBBL[53] = 1'b0; +end + +always @(valid_bwa53) +begin + + DAL[53] = 1'bx; + BWEBAL[53] = 1'b0; +end + +always @(valid_bwb53) +begin + disable CLKAOP; + DBL[53] = 1'bx; + BWEBBL[53] = 1'b0; +end +always @(valid_da54) +begin + + DAL[54] = 1'bx; + BWEBAL[54] = 1'b0; +end + +always @(valid_db54) +begin + disable CLKAOP; + DBL[54] = 1'bx; + BWEBBL[54] = 1'b0; +end + +always @(valid_bwa54) +begin + + DAL[54] = 1'bx; + BWEBAL[54] = 1'b0; +end + +always @(valid_bwb54) +begin + disable CLKAOP; + DBL[54] = 1'bx; + BWEBBL[54] = 1'b0; +end +always @(valid_da55) +begin + + DAL[55] = 1'bx; + BWEBAL[55] = 1'b0; +end + +always @(valid_db55) +begin + disable CLKAOP; + DBL[55] = 1'bx; + BWEBBL[55] = 1'b0; +end + +always @(valid_bwa55) +begin + + DAL[55] = 1'bx; + BWEBAL[55] = 1'b0; +end + +always @(valid_bwb55) +begin + disable CLKAOP; + DBL[55] = 1'bx; + BWEBBL[55] = 1'b0; +end +always @(valid_da56) +begin + + DAL[56] = 1'bx; + BWEBAL[56] = 1'b0; +end + +always @(valid_db56) +begin + disable CLKAOP; + DBL[56] = 1'bx; + BWEBBL[56] = 1'b0; +end + +always @(valid_bwa56) +begin + + DAL[56] = 1'bx; + BWEBAL[56] = 1'b0; +end + +always @(valid_bwb56) +begin + disable CLKAOP; + DBL[56] = 1'bx; + BWEBBL[56] = 1'b0; +end +always @(valid_da57) +begin + + DAL[57] = 1'bx; + BWEBAL[57] = 1'b0; +end + +always @(valid_db57) +begin + disable CLKAOP; + DBL[57] = 1'bx; + BWEBBL[57] = 1'b0; +end + +always @(valid_bwa57) +begin + + DAL[57] = 1'bx; + BWEBAL[57] = 1'b0; +end + +always @(valid_bwb57) +begin + disable CLKAOP; + DBL[57] = 1'bx; + BWEBBL[57] = 1'b0; +end +always @(valid_da58) +begin + + DAL[58] = 1'bx; + BWEBAL[58] = 1'b0; +end + +always @(valid_db58) +begin + disable CLKAOP; + DBL[58] = 1'bx; + BWEBBL[58] = 1'b0; +end + +always @(valid_bwa58) +begin + + DAL[58] = 1'bx; + BWEBAL[58] = 1'b0; +end + +always @(valid_bwb58) +begin + disable CLKAOP; + DBL[58] = 1'bx; + BWEBBL[58] = 1'b0; +end +always @(valid_da59) +begin + + DAL[59] = 1'bx; + BWEBAL[59] = 1'b0; +end + +always @(valid_db59) +begin + disable CLKAOP; + DBL[59] = 1'bx; + BWEBBL[59] = 1'b0; +end + +always @(valid_bwa59) +begin + + DAL[59] = 1'bx; + BWEBAL[59] = 1'b0; +end + +always @(valid_bwb59) +begin + disable CLKAOP; + DBL[59] = 1'bx; + BWEBBL[59] = 1'b0; +end +always @(valid_da60) +begin + + DAL[60] = 1'bx; + BWEBAL[60] = 1'b0; +end + +always @(valid_db60) +begin + disable CLKAOP; + DBL[60] = 1'bx; + BWEBBL[60] = 1'b0; +end + +always @(valid_bwa60) +begin + + DAL[60] = 1'bx; + BWEBAL[60] = 1'b0; +end + +always @(valid_bwb60) +begin + disable CLKAOP; + DBL[60] = 1'bx; + BWEBBL[60] = 1'b0; +end +always @(valid_da61) +begin + + DAL[61] = 1'bx; + BWEBAL[61] = 1'b0; +end + +always @(valid_db61) +begin + disable CLKAOP; + DBL[61] = 1'bx; + BWEBBL[61] = 1'b0; +end + +always @(valid_bwa61) +begin + + DAL[61] = 1'bx; + BWEBAL[61] = 1'b0; +end + +always @(valid_bwb61) +begin + disable CLKAOP; + DBL[61] = 1'bx; + BWEBBL[61] = 1'b0; +end +always @(valid_da62) +begin + + DAL[62] = 1'bx; + BWEBAL[62] = 1'b0; +end + +always @(valid_db62) +begin + disable CLKAOP; + DBL[62] = 1'bx; + BWEBBL[62] = 1'b0; +end + +always @(valid_bwa62) +begin + + DAL[62] = 1'bx; + BWEBAL[62] = 1'b0; +end + +always @(valid_bwb62) +begin + disable CLKAOP; + DBL[62] = 1'bx; + BWEBBL[62] = 1'b0; +end +always @(valid_da63) +begin + + DAL[63] = 1'bx; + BWEBAL[63] = 1'b0; +end + +always @(valid_db63) +begin + disable CLKAOP; + DBL[63] = 1'bx; + BWEBBL[63] = 1'b0; +end + +always @(valid_bwa63) +begin + + DAL[63] = 1'bx; + BWEBAL[63] = 1'b0; +end + +always @(valid_bwb63) +begin + disable CLKAOP; + DBL[63] = 1'bx; + BWEBBL[63] = 1'b0; +end +always @(valid_da64) +begin + + DAL[64] = 1'bx; + BWEBAL[64] = 1'b0; +end + +always @(valid_db64) +begin + disable CLKAOP; + DBL[64] = 1'bx; + BWEBBL[64] = 1'b0; +end + +always @(valid_bwa64) +begin + + DAL[64] = 1'bx; + BWEBAL[64] = 1'b0; +end + +always @(valid_bwb64) +begin + disable CLKAOP; + DBL[64] = 1'bx; + BWEBBL[64] = 1'b0; +end +always @(valid_da65) +begin + + DAL[65] = 1'bx; + BWEBAL[65] = 1'b0; +end + +always @(valid_db65) +begin + disable CLKAOP; + DBL[65] = 1'bx; + BWEBBL[65] = 1'b0; +end + +always @(valid_bwa65) +begin + + DAL[65] = 1'bx; + BWEBAL[65] = 1'b0; +end + +always @(valid_bwb65) +begin + disable CLKAOP; + DBL[65] = 1'bx; + BWEBBL[65] = 1'b0; +end +always @(valid_da66) +begin + + DAL[66] = 1'bx; + BWEBAL[66] = 1'b0; +end + +always @(valid_db66) +begin + disable CLKAOP; + DBL[66] = 1'bx; + BWEBBL[66] = 1'b0; +end + +always @(valid_bwa66) +begin + + DAL[66] = 1'bx; + BWEBAL[66] = 1'b0; +end + +always @(valid_bwb66) +begin + disable CLKAOP; + DBL[66] = 1'bx; + BWEBBL[66] = 1'b0; +end +always @(valid_da67) +begin + + DAL[67] = 1'bx; + BWEBAL[67] = 1'b0; +end + +always @(valid_db67) +begin + disable CLKAOP; + DBL[67] = 1'bx; + BWEBBL[67] = 1'b0; +end + +always @(valid_bwa67) +begin + + DAL[67] = 1'bx; + BWEBAL[67] = 1'b0; +end + +always @(valid_bwb67) +begin + disable CLKAOP; + DBL[67] = 1'bx; + BWEBBL[67] = 1'b0; +end +always @(valid_da68) +begin + + DAL[68] = 1'bx; + BWEBAL[68] = 1'b0; +end + +always @(valid_db68) +begin + disable CLKAOP; + DBL[68] = 1'bx; + BWEBBL[68] = 1'b0; +end + +always @(valid_bwa68) +begin + + DAL[68] = 1'bx; + BWEBAL[68] = 1'b0; +end + +always @(valid_bwb68) +begin + disable CLKAOP; + DBL[68] = 1'bx; + BWEBBL[68] = 1'b0; +end +always @(valid_da69) +begin + + DAL[69] = 1'bx; + BWEBAL[69] = 1'b0; +end + +always @(valid_db69) +begin + disable CLKAOP; + DBL[69] = 1'bx; + BWEBBL[69] = 1'b0; +end + +always @(valid_bwa69) +begin + + DAL[69] = 1'bx; + BWEBAL[69] = 1'b0; +end + +always @(valid_bwb69) +begin + disable CLKAOP; + DBL[69] = 1'bx; + BWEBBL[69] = 1'b0; +end +always @(valid_da70) +begin + + DAL[70] = 1'bx; + BWEBAL[70] = 1'b0; +end + +always @(valid_db70) +begin + disable CLKAOP; + DBL[70] = 1'bx; + BWEBBL[70] = 1'b0; +end + +always @(valid_bwa70) +begin + + DAL[70] = 1'bx; + BWEBAL[70] = 1'b0; +end + +always @(valid_bwb70) +begin + disable CLKAOP; + DBL[70] = 1'bx; + BWEBBL[70] = 1'b0; +end +always @(valid_da71) +begin + + DAL[71] = 1'bx; + BWEBAL[71] = 1'b0; +end + +always @(valid_db71) +begin + disable CLKAOP; + DBL[71] = 1'bx; + BWEBBL[71] = 1'b0; +end + +always @(valid_bwa71) +begin + + DAL[71] = 1'bx; + BWEBAL[71] = 1'b0; +end + +always @(valid_bwb71) +begin + disable CLKAOP; + DBL[71] = 1'bx; + BWEBBL[71] = 1'b0; +end +always @(valid_da72) +begin + + DAL[72] = 1'bx; + BWEBAL[72] = 1'b0; +end + +always @(valid_db72) +begin + disable CLKAOP; + DBL[72] = 1'bx; + BWEBBL[72] = 1'b0; +end + +always @(valid_bwa72) +begin + + DAL[72] = 1'bx; + BWEBAL[72] = 1'b0; +end + +always @(valid_bwb72) +begin + disable CLKAOP; + DBL[72] = 1'bx; + BWEBBL[72] = 1'b0; +end +always @(valid_da73) +begin + + DAL[73] = 1'bx; + BWEBAL[73] = 1'b0; +end + +always @(valid_db73) +begin + disable CLKAOP; + DBL[73] = 1'bx; + BWEBBL[73] = 1'b0; +end + +always @(valid_bwa73) +begin + + DAL[73] = 1'bx; + BWEBAL[73] = 1'b0; +end + +always @(valid_bwb73) +begin + disable CLKAOP; + DBL[73] = 1'bx; + BWEBBL[73] = 1'b0; +end +always @(valid_da74) +begin + + DAL[74] = 1'bx; + BWEBAL[74] = 1'b0; +end + +always @(valid_db74) +begin + disable CLKAOP; + DBL[74] = 1'bx; + BWEBBL[74] = 1'b0; +end + +always @(valid_bwa74) +begin + + DAL[74] = 1'bx; + BWEBAL[74] = 1'b0; +end + +always @(valid_bwb74) +begin + disable CLKAOP; + DBL[74] = 1'bx; + BWEBBL[74] = 1'b0; +end +always @(valid_da75) +begin + + DAL[75] = 1'bx; + BWEBAL[75] = 1'b0; +end + +always @(valid_db75) +begin + disable CLKAOP; + DBL[75] = 1'bx; + BWEBBL[75] = 1'b0; +end + +always @(valid_bwa75) +begin + + DAL[75] = 1'bx; + BWEBAL[75] = 1'b0; +end + +always @(valid_bwb75) +begin + disable CLKAOP; + DBL[75] = 1'bx; + BWEBBL[75] = 1'b0; +end +always @(valid_da76) +begin + + DAL[76] = 1'bx; + BWEBAL[76] = 1'b0; +end + +always @(valid_db76) +begin + disable CLKAOP; + DBL[76] = 1'bx; + BWEBBL[76] = 1'b0; +end + +always @(valid_bwa76) +begin + + DAL[76] = 1'bx; + BWEBAL[76] = 1'b0; +end + +always @(valid_bwb76) +begin + disable CLKAOP; + DBL[76] = 1'bx; + BWEBBL[76] = 1'b0; +end +always @(valid_da77) +begin + + DAL[77] = 1'bx; + BWEBAL[77] = 1'b0; +end + +always @(valid_db77) +begin + disable CLKAOP; + DBL[77] = 1'bx; + BWEBBL[77] = 1'b0; +end + +always @(valid_bwa77) +begin + + DAL[77] = 1'bx; + BWEBAL[77] = 1'b0; +end + +always @(valid_bwb77) +begin + disable CLKAOP; + DBL[77] = 1'bx; + BWEBBL[77] = 1'b0; +end +always @(valid_da78) +begin + + DAL[78] = 1'bx; + BWEBAL[78] = 1'b0; +end + +always @(valid_db78) +begin + disable CLKAOP; + DBL[78] = 1'bx; + BWEBBL[78] = 1'b0; +end + +always @(valid_bwa78) +begin + + DAL[78] = 1'bx; + BWEBAL[78] = 1'b0; +end + +always @(valid_bwb78) +begin + disable CLKAOP; + DBL[78] = 1'bx; + BWEBBL[78] = 1'b0; +end +always @(valid_da79) +begin + + DAL[79] = 1'bx; + BWEBAL[79] = 1'b0; +end + +always @(valid_db79) +begin + disable CLKAOP; + DBL[79] = 1'bx; + BWEBBL[79] = 1'b0; +end + +always @(valid_bwa79) +begin + + DAL[79] = 1'bx; + BWEBAL[79] = 1'b0; +end + +always @(valid_bwb79) +begin + disable CLKAOP; + DBL[79] = 1'bx; + BWEBBL[79] = 1'b0; +end +always @(valid_da80) +begin + + DAL[80] = 1'bx; + BWEBAL[80] = 1'b0; +end + +always @(valid_db80) +begin + disable CLKAOP; + DBL[80] = 1'bx; + BWEBBL[80] = 1'b0; +end + +always @(valid_bwa80) +begin + + DAL[80] = 1'bx; + BWEBAL[80] = 1'b0; +end + +always @(valid_bwb80) +begin + disable CLKAOP; + DBL[80] = 1'bx; + BWEBBL[80] = 1'b0; +end +always @(valid_da81) +begin + + DAL[81] = 1'bx; + BWEBAL[81] = 1'b0; +end + +always @(valid_db81) +begin + disable CLKAOP; + DBL[81] = 1'bx; + BWEBBL[81] = 1'b0; +end + +always @(valid_bwa81) +begin + + DAL[81] = 1'bx; + BWEBAL[81] = 1'b0; +end + +always @(valid_bwb81) +begin + disable CLKAOP; + DBL[81] = 1'bx; + BWEBBL[81] = 1'b0; +end +always @(valid_da82) +begin + + DAL[82] = 1'bx; + BWEBAL[82] = 1'b0; +end + +always @(valid_db82) +begin + disable CLKAOP; + DBL[82] = 1'bx; + BWEBBL[82] = 1'b0; +end + +always @(valid_bwa82) +begin + + DAL[82] = 1'bx; + BWEBAL[82] = 1'b0; +end + +always @(valid_bwb82) +begin + disable CLKAOP; + DBL[82] = 1'bx; + BWEBBL[82] = 1'b0; +end +always @(valid_da83) +begin + + DAL[83] = 1'bx; + BWEBAL[83] = 1'b0; +end + +always @(valid_db83) +begin + disable CLKAOP; + DBL[83] = 1'bx; + BWEBBL[83] = 1'b0; +end + +always @(valid_bwa83) +begin + + DAL[83] = 1'bx; + BWEBAL[83] = 1'b0; +end + +always @(valid_bwb83) +begin + disable CLKAOP; + DBL[83] = 1'bx; + BWEBBL[83] = 1'b0; +end +always @(valid_da84) +begin + + DAL[84] = 1'bx; + BWEBAL[84] = 1'b0; +end + +always @(valid_db84) +begin + disable CLKAOP; + DBL[84] = 1'bx; + BWEBBL[84] = 1'b0; +end + +always @(valid_bwa84) +begin + + DAL[84] = 1'bx; + BWEBAL[84] = 1'b0; +end + +always @(valid_bwb84) +begin + disable CLKAOP; + DBL[84] = 1'bx; + BWEBBL[84] = 1'b0; +end +always @(valid_da85) +begin + + DAL[85] = 1'bx; + BWEBAL[85] = 1'b0; +end + +always @(valid_db85) +begin + disable CLKAOP; + DBL[85] = 1'bx; + BWEBBL[85] = 1'b0; +end + +always @(valid_bwa85) +begin + + DAL[85] = 1'bx; + BWEBAL[85] = 1'b0; +end + +always @(valid_bwb85) +begin + disable CLKAOP; + DBL[85] = 1'bx; + BWEBBL[85] = 1'b0; +end +always @(valid_da86) +begin + + DAL[86] = 1'bx; + BWEBAL[86] = 1'b0; +end + +always @(valid_db86) +begin + disable CLKAOP; + DBL[86] = 1'bx; + BWEBBL[86] = 1'b0; +end + +always @(valid_bwa86) +begin + + DAL[86] = 1'bx; + BWEBAL[86] = 1'b0; +end + +always @(valid_bwb86) +begin + disable CLKAOP; + DBL[86] = 1'bx; + BWEBBL[86] = 1'b0; +end +always @(valid_da87) +begin + + DAL[87] = 1'bx; + BWEBAL[87] = 1'b0; +end + +always @(valid_db87) +begin + disable CLKAOP; + DBL[87] = 1'bx; + BWEBBL[87] = 1'b0; +end + +always @(valid_bwa87) +begin + + DAL[87] = 1'bx; + BWEBAL[87] = 1'b0; +end + +always @(valid_bwb87) +begin + disable CLKAOP; + DBL[87] = 1'bx; + BWEBBL[87] = 1'b0; +end +always @(valid_da88) +begin + + DAL[88] = 1'bx; + BWEBAL[88] = 1'b0; +end + +always @(valid_db88) +begin + disable CLKAOP; + DBL[88] = 1'bx; + BWEBBL[88] = 1'b0; +end + +always @(valid_bwa88) +begin + + DAL[88] = 1'bx; + BWEBAL[88] = 1'b0; +end + +always @(valid_bwb88) +begin + disable CLKAOP; + DBL[88] = 1'bx; + BWEBBL[88] = 1'b0; +end +always @(valid_da89) +begin + + DAL[89] = 1'bx; + BWEBAL[89] = 1'b0; +end + +always @(valid_db89) +begin + disable CLKAOP; + DBL[89] = 1'bx; + BWEBBL[89] = 1'b0; +end + +always @(valid_bwa89) +begin + + DAL[89] = 1'bx; + BWEBAL[89] = 1'b0; +end + +always @(valid_bwb89) +begin + disable CLKAOP; + DBL[89] = 1'bx; + BWEBBL[89] = 1'b0; +end +always @(valid_da90) +begin + + DAL[90] = 1'bx; + BWEBAL[90] = 1'b0; +end + +always @(valid_db90) +begin + disable CLKAOP; + DBL[90] = 1'bx; + BWEBBL[90] = 1'b0; +end + +always @(valid_bwa90) +begin + + DAL[90] = 1'bx; + BWEBAL[90] = 1'b0; +end + +always @(valid_bwb90) +begin + disable CLKAOP; + DBL[90] = 1'bx; + BWEBBL[90] = 1'b0; +end +always @(valid_da91) +begin + + DAL[91] = 1'bx; + BWEBAL[91] = 1'b0; +end + +always @(valid_db91) +begin + disable CLKAOP; + DBL[91] = 1'bx; + BWEBBL[91] = 1'b0; +end + +always @(valid_bwa91) +begin + + DAL[91] = 1'bx; + BWEBAL[91] = 1'b0; +end + +always @(valid_bwb91) +begin + disable CLKAOP; + DBL[91] = 1'bx; + BWEBBL[91] = 1'b0; +end +always @(valid_da92) +begin + + DAL[92] = 1'bx; + BWEBAL[92] = 1'b0; +end + +always @(valid_db92) +begin + disable CLKAOP; + DBL[92] = 1'bx; + BWEBBL[92] = 1'b0; +end + +always @(valid_bwa92) +begin + + DAL[92] = 1'bx; + BWEBAL[92] = 1'b0; +end + +always @(valid_bwb92) +begin + disable CLKAOP; + DBL[92] = 1'bx; + BWEBBL[92] = 1'b0; +end +always @(valid_da93) +begin + + DAL[93] = 1'bx; + BWEBAL[93] = 1'b0; +end + +always @(valid_db93) +begin + disable CLKAOP; + DBL[93] = 1'bx; + BWEBBL[93] = 1'b0; +end + +always @(valid_bwa93) +begin + + DAL[93] = 1'bx; + BWEBAL[93] = 1'b0; +end + +always @(valid_bwb93) +begin + disable CLKAOP; + DBL[93] = 1'bx; + BWEBBL[93] = 1'b0; +end +always @(valid_da94) +begin + + DAL[94] = 1'bx; + BWEBAL[94] = 1'b0; +end + +always @(valid_db94) +begin + disable CLKAOP; + DBL[94] = 1'bx; + BWEBBL[94] = 1'b0; +end + +always @(valid_bwa94) +begin + + DAL[94] = 1'bx; + BWEBAL[94] = 1'b0; +end + +always @(valid_bwb94) +begin + disable CLKAOP; + DBL[94] = 1'bx; + BWEBBL[94] = 1'b0; +end +always @(valid_da95) +begin + + DAL[95] = 1'bx; + BWEBAL[95] = 1'b0; +end + +always @(valid_db95) +begin + disable CLKAOP; + DBL[95] = 1'bx; + BWEBBL[95] = 1'b0; +end + +always @(valid_bwa95) +begin + + DAL[95] = 1'bx; + BWEBAL[95] = 1'b0; +end + +always @(valid_bwb95) +begin + disable CLKAOP; + DBL[95] = 1'bx; + BWEBBL[95] = 1'b0; +end +always @(valid_da96) +begin + + DAL[96] = 1'bx; + BWEBAL[96] = 1'b0; +end + +always @(valid_db96) +begin + disable CLKAOP; + DBL[96] = 1'bx; + BWEBBL[96] = 1'b0; +end + +always @(valid_bwa96) +begin + + DAL[96] = 1'bx; + BWEBAL[96] = 1'b0; +end + +always @(valid_bwb96) +begin + disable CLKAOP; + DBL[96] = 1'bx; + BWEBBL[96] = 1'b0; +end +always @(valid_da97) +begin + + DAL[97] = 1'bx; + BWEBAL[97] = 1'b0; +end + +always @(valid_db97) +begin + disable CLKAOP; + DBL[97] = 1'bx; + BWEBBL[97] = 1'b0; +end + +always @(valid_bwa97) +begin + + DAL[97] = 1'bx; + BWEBAL[97] = 1'b0; +end + +always @(valid_bwb97) +begin + disable CLKAOP; + DBL[97] = 1'bx; + BWEBBL[97] = 1'b0; +end +always @(valid_da98) +begin + + DAL[98] = 1'bx; + BWEBAL[98] = 1'b0; +end + +always @(valid_db98) +begin + disable CLKAOP; + DBL[98] = 1'bx; + BWEBBL[98] = 1'b0; +end + +always @(valid_bwa98) +begin + + DAL[98] = 1'bx; + BWEBAL[98] = 1'b0; +end + +always @(valid_bwb98) +begin + disable CLKAOP; + DBL[98] = 1'bx; + BWEBBL[98] = 1'b0; +end +always @(valid_da99) +begin + + DAL[99] = 1'bx; + BWEBAL[99] = 1'b0; +end + +always @(valid_db99) +begin + disable CLKAOP; + DBL[99] = 1'bx; + BWEBBL[99] = 1'b0; +end + +always @(valid_bwa99) +begin + + DAL[99] = 1'bx; + BWEBAL[99] = 1'b0; +end + +always @(valid_bwb99) +begin + disable CLKAOP; + DBL[99] = 1'bx; + BWEBBL[99] = 1'b0; +end +always @(valid_da100) +begin + + DAL[100] = 1'bx; + BWEBAL[100] = 1'b0; +end + +always @(valid_db100) +begin + disable CLKAOP; + DBL[100] = 1'bx; + BWEBBL[100] = 1'b0; +end + +always @(valid_bwa100) +begin + + DAL[100] = 1'bx; + BWEBAL[100] = 1'b0; +end + +always @(valid_bwb100) +begin + disable CLKAOP; + DBL[100] = 1'bx; + BWEBBL[100] = 1'b0; +end +always @(valid_da101) +begin + + DAL[101] = 1'bx; + BWEBAL[101] = 1'b0; +end + +always @(valid_db101) +begin + disable CLKAOP; + DBL[101] = 1'bx; + BWEBBL[101] = 1'b0; +end + +always @(valid_bwa101) +begin + + DAL[101] = 1'bx; + BWEBAL[101] = 1'b0; +end + +always @(valid_bwb101) +begin + disable CLKAOP; + DBL[101] = 1'bx; + BWEBBL[101] = 1'b0; +end +always @(valid_da102) +begin + + DAL[102] = 1'bx; + BWEBAL[102] = 1'b0; +end + +always @(valid_db102) +begin + disable CLKAOP; + DBL[102] = 1'bx; + BWEBBL[102] = 1'b0; +end + +always @(valid_bwa102) +begin + + DAL[102] = 1'bx; + BWEBAL[102] = 1'b0; +end + +always @(valid_bwb102) +begin + disable CLKAOP; + DBL[102] = 1'bx; + BWEBBL[102] = 1'b0; +end +always @(valid_da103) +begin + + DAL[103] = 1'bx; + BWEBAL[103] = 1'b0; +end + +always @(valid_db103) +begin + disable CLKAOP; + DBL[103] = 1'bx; + BWEBBL[103] = 1'b0; +end + +always @(valid_bwa103) +begin + + DAL[103] = 1'bx; + BWEBAL[103] = 1'b0; +end + +always @(valid_bwb103) +begin + disable CLKAOP; + DBL[103] = 1'bx; + BWEBBL[103] = 1'b0; +end +always @(valid_da104) +begin + + DAL[104] = 1'bx; + BWEBAL[104] = 1'b0; +end + +always @(valid_db104) +begin + disable CLKAOP; + DBL[104] = 1'bx; + BWEBBL[104] = 1'b0; +end + +always @(valid_bwa104) +begin + + DAL[104] = 1'bx; + BWEBAL[104] = 1'b0; +end + +always @(valid_bwb104) +begin + disable CLKAOP; + DBL[104] = 1'bx; + BWEBBL[104] = 1'b0; +end +always @(valid_da105) +begin + + DAL[105] = 1'bx; + BWEBAL[105] = 1'b0; +end + +always @(valid_db105) +begin + disable CLKAOP; + DBL[105] = 1'bx; + BWEBBL[105] = 1'b0; +end + +always @(valid_bwa105) +begin + + DAL[105] = 1'bx; + BWEBAL[105] = 1'b0; +end + +always @(valid_bwb105) +begin + disable CLKAOP; + DBL[105] = 1'bx; + BWEBBL[105] = 1'b0; +end +always @(valid_da106) +begin + + DAL[106] = 1'bx; + BWEBAL[106] = 1'b0; +end + +always @(valid_db106) +begin + disable CLKAOP; + DBL[106] = 1'bx; + BWEBBL[106] = 1'b0; +end + +always @(valid_bwa106) +begin + + DAL[106] = 1'bx; + BWEBAL[106] = 1'b0; +end + +always @(valid_bwb106) +begin + disable CLKAOP; + DBL[106] = 1'bx; + BWEBBL[106] = 1'b0; +end +always @(valid_da107) +begin + + DAL[107] = 1'bx; + BWEBAL[107] = 1'b0; +end + +always @(valid_db107) +begin + disable CLKAOP; + DBL[107] = 1'bx; + BWEBBL[107] = 1'b0; +end + +always @(valid_bwa107) +begin + + DAL[107] = 1'bx; + BWEBAL[107] = 1'b0; +end + +always @(valid_bwb107) +begin + disable CLKAOP; + DBL[107] = 1'bx; + BWEBBL[107] = 1'b0; +end +always @(valid_da108) +begin + + DAL[108] = 1'bx; + BWEBAL[108] = 1'b0; +end + +always @(valid_db108) +begin + disable CLKAOP; + DBL[108] = 1'bx; + BWEBBL[108] = 1'b0; +end + +always @(valid_bwa108) +begin + + DAL[108] = 1'bx; + BWEBAL[108] = 1'b0; +end + +always @(valid_bwb108) +begin + disable CLKAOP; + DBL[108] = 1'bx; + BWEBBL[108] = 1'b0; +end +always @(valid_da109) +begin + + DAL[109] = 1'bx; + BWEBAL[109] = 1'b0; +end + +always @(valid_db109) +begin + disable CLKAOP; + DBL[109] = 1'bx; + BWEBBL[109] = 1'b0; +end + +always @(valid_bwa109) +begin + + DAL[109] = 1'bx; + BWEBAL[109] = 1'b0; +end + +always @(valid_bwb109) +begin + disable CLKAOP; + DBL[109] = 1'bx; + BWEBBL[109] = 1'b0; +end +always @(valid_da110) +begin + + DAL[110] = 1'bx; + BWEBAL[110] = 1'b0; +end + +always @(valid_db110) +begin + disable CLKAOP; + DBL[110] = 1'bx; + BWEBBL[110] = 1'b0; +end + +always @(valid_bwa110) +begin + + DAL[110] = 1'bx; + BWEBAL[110] = 1'b0; +end + +always @(valid_bwb110) +begin + disable CLKAOP; + DBL[110] = 1'bx; + BWEBBL[110] = 1'b0; +end +always @(valid_da111) +begin + + DAL[111] = 1'bx; + BWEBAL[111] = 1'b0; +end + +always @(valid_db111) +begin + disable CLKAOP; + DBL[111] = 1'bx; + BWEBBL[111] = 1'b0; +end + +always @(valid_bwa111) +begin + + DAL[111] = 1'bx; + BWEBAL[111] = 1'b0; +end + +always @(valid_bwb111) +begin + disable CLKAOP; + DBL[111] = 1'bx; + BWEBBL[111] = 1'b0; +end +always @(valid_da112) +begin + + DAL[112] = 1'bx; + BWEBAL[112] = 1'b0; +end + +always @(valid_db112) +begin + disable CLKAOP; + DBL[112] = 1'bx; + BWEBBL[112] = 1'b0; +end + +always @(valid_bwa112) +begin + + DAL[112] = 1'bx; + BWEBAL[112] = 1'b0; +end + +always @(valid_bwb112) +begin + disable CLKAOP; + DBL[112] = 1'bx; + BWEBBL[112] = 1'b0; +end +always @(valid_da113) +begin + + DAL[113] = 1'bx; + BWEBAL[113] = 1'b0; +end + +always @(valid_db113) +begin + disable CLKAOP; + DBL[113] = 1'bx; + BWEBBL[113] = 1'b0; +end + +always @(valid_bwa113) +begin + + DAL[113] = 1'bx; + BWEBAL[113] = 1'b0; +end + +always @(valid_bwb113) +begin + disable CLKAOP; + DBL[113] = 1'bx; + BWEBBL[113] = 1'b0; +end +always @(valid_da114) +begin + + DAL[114] = 1'bx; + BWEBAL[114] = 1'b0; +end + +always @(valid_db114) +begin + disable CLKAOP; + DBL[114] = 1'bx; + BWEBBL[114] = 1'b0; +end + +always @(valid_bwa114) +begin + + DAL[114] = 1'bx; + BWEBAL[114] = 1'b0; +end + +always @(valid_bwb114) +begin + disable CLKAOP; + DBL[114] = 1'bx; + BWEBBL[114] = 1'b0; +end +always @(valid_da115) +begin + + DAL[115] = 1'bx; + BWEBAL[115] = 1'b0; +end + +always @(valid_db115) +begin + disable CLKAOP; + DBL[115] = 1'bx; + BWEBBL[115] = 1'b0; +end + +always @(valid_bwa115) +begin + + DAL[115] = 1'bx; + BWEBAL[115] = 1'b0; +end + +always @(valid_bwb115) +begin + disable CLKAOP; + DBL[115] = 1'bx; + BWEBBL[115] = 1'b0; +end +always @(valid_da116) +begin + + DAL[116] = 1'bx; + BWEBAL[116] = 1'b0; +end + +always @(valid_db116) +begin + disable CLKAOP; + DBL[116] = 1'bx; + BWEBBL[116] = 1'b0; +end + +always @(valid_bwa116) +begin + + DAL[116] = 1'bx; + BWEBAL[116] = 1'b0; +end + +always @(valid_bwb116) +begin + disable CLKAOP; + DBL[116] = 1'bx; + BWEBBL[116] = 1'b0; +end +always @(valid_da117) +begin + + DAL[117] = 1'bx; + BWEBAL[117] = 1'b0; +end + +always @(valid_db117) +begin + disable CLKAOP; + DBL[117] = 1'bx; + BWEBBL[117] = 1'b0; +end + +always @(valid_bwa117) +begin + + DAL[117] = 1'bx; + BWEBAL[117] = 1'b0; +end + +always @(valid_bwb117) +begin + disable CLKAOP; + DBL[117] = 1'bx; + BWEBBL[117] = 1'b0; +end +always @(valid_da118) +begin + + DAL[118] = 1'bx; + BWEBAL[118] = 1'b0; +end + +always @(valid_db118) +begin + disable CLKAOP; + DBL[118] = 1'bx; + BWEBBL[118] = 1'b0; +end + +always @(valid_bwa118) +begin + + DAL[118] = 1'bx; + BWEBAL[118] = 1'b0; +end + +always @(valid_bwb118) +begin + disable CLKAOP; + DBL[118] = 1'bx; + BWEBBL[118] = 1'b0; +end +always @(valid_da119) +begin + + DAL[119] = 1'bx; + BWEBAL[119] = 1'b0; +end + +always @(valid_db119) +begin + disable CLKAOP; + DBL[119] = 1'bx; + BWEBBL[119] = 1'b0; +end + +always @(valid_bwa119) +begin + + DAL[119] = 1'bx; + BWEBAL[119] = 1'b0; +end + +always @(valid_bwb119) +begin + disable CLKAOP; + DBL[119] = 1'bx; + BWEBBL[119] = 1'b0; +end +always @(valid_da120) +begin + + DAL[120] = 1'bx; + BWEBAL[120] = 1'b0; +end + +always @(valid_db120) +begin + disable CLKAOP; + DBL[120] = 1'bx; + BWEBBL[120] = 1'b0; +end + +always @(valid_bwa120) +begin + + DAL[120] = 1'bx; + BWEBAL[120] = 1'b0; +end + +always @(valid_bwb120) +begin + disable CLKAOP; + DBL[120] = 1'bx; + BWEBBL[120] = 1'b0; +end +always @(valid_da121) +begin + + DAL[121] = 1'bx; + BWEBAL[121] = 1'b0; +end + +always @(valid_db121) +begin + disable CLKAOP; + DBL[121] = 1'bx; + BWEBBL[121] = 1'b0; +end + +always @(valid_bwa121) +begin + + DAL[121] = 1'bx; + BWEBAL[121] = 1'b0; +end + +always @(valid_bwb121) +begin + disable CLKAOP; + DBL[121] = 1'bx; + BWEBBL[121] = 1'b0; +end +always @(valid_da122) +begin + + DAL[122] = 1'bx; + BWEBAL[122] = 1'b0; +end + +always @(valid_db122) +begin + disable CLKAOP; + DBL[122] = 1'bx; + BWEBBL[122] = 1'b0; +end + +always @(valid_bwa122) +begin + + DAL[122] = 1'bx; + BWEBAL[122] = 1'b0; +end + +always @(valid_bwb122) +begin + disable CLKAOP; + DBL[122] = 1'bx; + BWEBBL[122] = 1'b0; +end +always @(valid_da123) +begin + + DAL[123] = 1'bx; + BWEBAL[123] = 1'b0; +end + +always @(valid_db123) +begin + disable CLKAOP; + DBL[123] = 1'bx; + BWEBBL[123] = 1'b0; +end + +always @(valid_bwa123) +begin + + DAL[123] = 1'bx; + BWEBAL[123] = 1'b0; +end + +always @(valid_bwb123) +begin + disable CLKAOP; + DBL[123] = 1'bx; + BWEBBL[123] = 1'b0; +end +always @(valid_da124) +begin + + DAL[124] = 1'bx; + BWEBAL[124] = 1'b0; +end + +always @(valid_db124) +begin + disable CLKAOP; + DBL[124] = 1'bx; + BWEBBL[124] = 1'b0; +end + +always @(valid_bwa124) +begin + + DAL[124] = 1'bx; + BWEBAL[124] = 1'b0; +end + +always @(valid_bwb124) +begin + disable CLKAOP; + DBL[124] = 1'bx; + BWEBBL[124] = 1'b0; +end +always @(valid_da125) +begin + + DAL[125] = 1'bx; + BWEBAL[125] = 1'b0; +end + +always @(valid_db125) +begin + disable CLKAOP; + DBL[125] = 1'bx; + BWEBBL[125] = 1'b0; +end + +always @(valid_bwa125) +begin + + DAL[125] = 1'bx; + BWEBAL[125] = 1'b0; +end + +always @(valid_bwb125) +begin + disable CLKAOP; + DBL[125] = 1'bx; + BWEBBL[125] = 1'b0; +end +always @(valid_da126) +begin + + DAL[126] = 1'bx; + BWEBAL[126] = 1'b0; +end + +always @(valid_db126) +begin + disable CLKAOP; + DBL[126] = 1'bx; + BWEBBL[126] = 1'b0; +end + +always @(valid_bwa126) +begin + + DAL[126] = 1'bx; + BWEBAL[126] = 1'b0; +end + +always @(valid_bwb126) +begin + disable CLKAOP; + DBL[126] = 1'bx; + BWEBBL[126] = 1'b0; +end +always @(valid_da127) +begin + + DAL[127] = 1'bx; + BWEBAL[127] = 1'b0; +end + +always @(valid_db127) +begin + disable CLKAOP; + DBL[127] = 1'bx; + BWEBBL[127] = 1'b0; +end + +always @(valid_bwa127) +begin + + DAL[127] = 1'bx; + BWEBAL[127] = 1'b0; +end + +always @(valid_bwb127) +begin + disable CLKAOP; + DBL[127] = 1'bx; + BWEBBL[127] = 1'b0; +end + +always @(valid_cea) +begin + + #0.002; + BWEBAL = {N{1'b0}}; + AAL = {M{1'bx}}; + bQA = #0.01 {N{1'bx}}; +end + +always @(valid_ceb) +begin + + #0.002; + BWEBBL = {N{1'b0}}; + ABL = {M{1'bx}}; + bQB = #0.01 {N{1'bx}}; +end + +always @(valid_wea) +begin + #0.002; + BWEBAL = {N{1'b0}}; + AAL = {M{1'bx}}; + bQA = #0.01 {N{1'bx}}; +end + +always @(valid_web) +begin + #0.002; + BWEBBL = {N{1'b0}}; + ABL = {M{1'bx}}; + bQB = #0.01 {N{1'bx}}; +end + +`endif + +// Task for printing the memory between specified addresses.. +task printMemoryFromTo; + input [M - 1:0] from; // memory content are printed, start from this address. + input [M - 1:0] to; // memory content are printed, end at this address. + begin + MX.printMemoryFromTo(from, to); + end +endtask + +// Task for printing entire memory, including normal array and redundancy array. +task printMemory; + begin + MX.printMemory; + end +endtask + +task xMemoryAll; + begin + MX.xMemoryAll; + end +endtask + +task zeroMemoryAll; + begin + MX.zeroMemoryAll; + end +endtask + +// Task for Loading a perdefined set of data from an external file. +task preloadData; + input [256*8:1] infile; // Max 256 character File Name + begin + MX.preloadData(infile); + end +endtask + +tsdn28hpcpuhdb128x128m4mw_170a_Int_Array #(2,2,W,N,M,MES_ALL) MX (.D({DAL,DBL}),.BW({BWEBAL,BWEBBL}), + .AW({AAL,ABL}),.EN(EN),.AAR(AAL),.ABR(ABL),.RDA(RDA),.RDB(RDB),.QA(QAL),.QB(QBL)); + +endmodule + + `disable_portfaults + `nosuppress_faults + `endcelldefine + + /* + The module ports are parameterizable vectors. + */ + module tsdn28hpcpuhdb128x128m4mw_170a_Int_Array (D, BW, AW, EN, AAR, ABR, RDA, RDB, QA, QB); + parameter Nread = 2; // Number of Read Ports + parameter Nwrite = 2; // Number of Write Ports + parameter Nword = 2; // Number of Words + parameter Ndata = 1; // Number of Data Bits / Word + parameter Naddr = 1; // Number of Address Bits / Word + parameter MES_ALL = "ON"; + parameter dly = 0.000; + // Cannot define inputs/outputs as memories + input [Ndata*Nwrite-1:0] D; // Data Word(s) + input [Ndata*Nwrite-1:0] BW; // Negative Bit Write Enable + input [Naddr*Nwrite-1:0] AW; // Write Address(es) + input EN; // Positive Write Enable + input RDA; // Positive Write Enable + input RDB; // Positive Write Enable + input [Naddr-1:0] AAR; // Read Address(es) + input [Naddr-1:0] ABR; // Read Address(es) + output [Ndata-1:0] QA; // Output Data Word(s) + output [Ndata-1:0] QB; // Output Data Word(s) + reg [Ndata-1:0] QA; + reg [Ndata-1:0] QB; + reg [Ndata-1:0] mem [Nword-1:0]; + reg [Ndata-1:0] mem_fault [Nword-1:0]; + reg chgmem; // Toggled when write to mem + reg [Nwrite-1:0] wwe; // Positive Word Write Enable for each Port + reg we; // Positive Write Enable for all Ports + integer waddr[Nwrite-1:0]; // Write Address for each Enabled Port + integer address; // Current address + reg [Naddr-1:0] abuf; // Address of current port + reg [Ndata-1:0] dbuf; // Data for current port + reg [Naddr-1:0] abuf_ra; // Address of current port + reg [Ndata-1:0] dbuf_ra; // Data for current port + reg [Naddr-1:0] abuf_rb; // Address of current port + reg [Ndata-1:0] dbuf_rb; // Data for current port + reg [Ndata-1:0] bwbuf; // Bit Write enable for current port + reg dup; // Is the address a duplicate? + integer log; // Log file descriptor + integer ip, ip2, ib, iba_r, ibb_r, iw, iwb, i; // Vector indices + + + initial + begin + if(log[0] === 1'bx) + log = 1; + chgmem = 1'b0; + end + + + always @(D or BW or AW or EN) + begin: WRITE //{ + if(EN !== 1'b0) + begin //{ Possible write + we = 1'b0; + // Mark any write enabled ports & get write addresses + for (ip = 0 ; ip < Nwrite ; ip = ip + 1) + begin //{ + ib = ip * Ndata; + iw = ib + Ndata; + while (ib < iw && BW[ib] === 1'b1) + begin + ib = ib + 1; + end + if(ib == iw) + begin + wwe[ip] = 1'b0; + end + else + begin //{ ip write enabled + iw = ip * Naddr; + for (ib = 0 ; ib < Naddr ; ib = ib + 1) + begin //{ + abuf[ib] = AW[iw+ib]; + if(abuf[ib] !== 1'b0 && abuf[ib] !== 1'b1) + begin + ib = Naddr; + end + end //} + if(ib == Naddr) + begin //{ + if(abuf < Nword) + begin //{ Valid address + waddr[ip] = abuf; + wwe[ip] = 1'b1; + if(we == 1'b0) + begin + chgmem = ~chgmem; + we = EN; + end + end //} + else + begin //{ Out of range address + wwe[ip] = 1'b0; + if( MES_ALL=="ON" && $realtime != 0) + $fdisplay (log, + "\nWarning! Int_Array instance, %m:", + "\n\t Port %0d", ip, + " write address x'%0h'", abuf, + " out of range at time %t.", $realtime, + "\n\t Port %0d data not written to memory.", ip); + end //} + end //} + else + begin //{ unknown write address + for (ib = 0 ; ib < Ndata ; ib = ib + 1) + begin + dbuf[ib] = 1'bx; + end + for (iw = 0 ; iw < Nword ; iw = iw + 1) + begin + mem[iw] = dbuf; + end + chgmem = ~chgmem; + disable WRITE; + end //} + end //} ip write enabled + end //} for ip + if(we === 1'b1) + begin //{ active write enable + for (ip = 0 ; ip < Nwrite ; ip = ip + 1) + begin //{ + if(wwe[ip]) + begin //{ write enabled bits of write port ip + address = waddr[ip]; + dbuf = mem[address]; + iw = ip * Ndata; + for (ib = 0 ; ib < Ndata ; ib = ib + 1) + begin //{ + iwb = iw + ib; + if(BW[iwb] === 1'b0) + begin + dbuf[ib] = D[iwb]; + end + else + if(BW[iwb] !== 1'b1) + begin + dbuf[ib] = 1'bx; + end + end //} + // Check other ports for same address & + // common write enable bits active + dup = 0; + for (ip2 = ip + 1 ; ip2 < Nwrite ; ip2 = ip2 + 1) + begin //{ + if(wwe[ip2] && address == waddr[ip2]) + begin //{ + // initialize bwbuf if first dup + if(!dup) + begin + for (ib = 0 ; ib < Ndata ; ib = ib + 1) + begin + bwbuf[ib] = BW[iw+ib]; + end + dup = 1; + end + iw = ip2 * Ndata; + for (ib = 0 ; ib < Ndata ; ib = ib + 1) + begin //{ + iwb = iw + ib; + // New: Always set X if BW X + if(BW[iwb] === 1'b0) + begin //{ + if(bwbuf[ib] !== 1'b1) + begin + if(D[iwb] !== dbuf[ib]) + begin + dbuf[ib] = 1'bx; + end + end + else + begin + dbuf[ib] = D[iwb]; + bwbuf[ib] = 1'b0; + end + end //} + else if(BW[iwb] !== 1'b1) + begin + dbuf[ib] = 1'bx; + bwbuf[ib] = 1'bx; + end + end //} for each bit + wwe[ip2] = 1'b0; + end //} Port ip2 address matches port ip + end //} for each port beyond ip (ip2=ip+1) + // Write dbuf to memory + mem[address] = dbuf; + end //} wwe[ip] - write port ip enabled + end //} for each write port ip + end //} active write enable + else if(we !== 1'b0) + begin //{ unknown write enable + for (ip = 0 ; ip < Nwrite ; ip = ip + 1) + begin //{ + if(wwe[ip]) + begin //{ write X to enabled bits of write port ip + address = waddr[ip]; + dbuf = mem[address]; + iw = ip * Ndata; + for (ib = 0 ; ib < Ndata ; ib = ib + 1) + begin //{ + if(BW[iw+ib] !== 1'b1) + begin + dbuf[ib] = 1'bx; + end + end //} + mem[address] = dbuf; + if( MES_ALL=="ON" && $realtime != 0) + $fdisplay (log, + "\nWarning! Int_Array instance, %m:", + "\n\t Enable pin unknown at time %t.", $realtime, + "\n\t Enabled bits at port %0d", ip, + " write address x'%0h' set unknown.", address); + end //} wwe[ip] - write port ip enabled + end //} for each write port ip + end //} unknown write enable + end //} possible write (EN != 0) + end //} always @(D or BW or AW or EN) + + + // Read memory + always @(AAR or RDA) + begin //{ + for (iba_r = 0 ; iba_r < Naddr ; iba_r = iba_r + 1) + begin + abuf_ra[iba_r] = AAR[iba_r]; + if(abuf_ra[iba_r] !== 0 && abuf_ra[iba_r] !== 1) + begin + iba_r = Naddr; + end + end + if(iba_r == Naddr && abuf_ra < Nword) + begin //{ Read valid address + `ifdef TSMC_INITIALIZE_FAULT + dbuf_ra = mem[abuf_ra] ^ mem_fault[abuf_ra]; + `else + dbuf_ra = mem[abuf_ra]; + `endif + for (iba_r = 0 ; iba_r < Ndata ; iba_r = iba_r + 1) + begin + if(QA[iba_r] == dbuf_ra[iba_r]) + begin + QA[iba_r] <= #(dly) dbuf_ra[iba_r]; + end + else + begin + QA[iba_r] <= #(dly) dbuf_ra[iba_r]; + end // else + end // for + end //} valid address + else + begin //{ Invalid address + if(iba_r <= Naddr) begin + if( MES_ALL=="ON" && $realtime != 0) + $fwrite (log, "\nWarning! Int_Array instance, %m:", + "\n\t Port A read address"); + if( MES_ALL=="ON" && $realtime != 0) + $fwrite (log, " x'%0h' out of range", abuf_ra); + if( MES_ALL=="ON" && $realtime != 0) + $fdisplay (log, + " at time %t.", $realtime, + "\n\t Port A outputs set to unknown."); + end + + for (iba_r = 0 ; iba_r < Ndata ; iba_r = iba_r + 1) + QA[iba_r] <= #(dly) 1'bx; + end //} invalid address + end //} always @(chgmem or AR) + + // Read memory + always @(ABR or RDB) + begin //{ + for (ibb_r = 0 ; ibb_r < Naddr ; ibb_r = ibb_r + 1) + begin + abuf_rb[ibb_r] = ABR[ibb_r]; + if(abuf_rb[ibb_r] !== 0 && abuf_rb[ibb_r] !== 1) + begin + ibb_r = Naddr; + end + end + if(ibb_r == Naddr && abuf_rb < Nword) + begin //{ Read valid address + `ifdef TSMC_INITIALIZE_FAULT + dbuf_rb = mem[abuf_rb] ^ mem_fault[abuf_rb]; + `else + dbuf_rb = mem[abuf_rb]; + `endif + for (ibb_r = 0 ; ibb_r < Ndata ; ibb_r = ibb_r + 1) + begin + if(QB[ibb_r] == dbuf_rb[ibb_r]) + begin + QB[ibb_r] <= #(dly) dbuf_rb[ibb_r]; + end + else + begin + QB[ibb_r] <= #(dly) dbuf_rb[ibb_r]; + end // else + end // for + end //} valid address + else + begin //{ Invalid address + if(ibb_r <= Naddr) begin + if( MES_ALL=="ON" && $realtime != 0) + $fwrite (log, "\nWarning! Int_Array instance, %m:", + "\n\t Port B read address"); + if( MES_ALL=="ON" && $realtime != 0) + $fwrite (log, " x'%0h' out of range", abuf_rb); + if( MES_ALL=="ON" && $realtime != 0) + $fdisplay (log, + " at time %t.", $realtime, + "\n\t Port B outputs set to unknown."); + end + for (ibb_r = 0 ; ibb_r < Ndata ; ibb_r = ibb_r + 1) + QB[ibb_r] <= #(dly) 1'bx; + end //} invalid address + end //} always @(chgmem or AR) + + + // Task for loading contents of a memory + task preloadData; + input [256*8:1] infile; // Max 256 character File Name + begin + $display ("%m: Reading file, %0s, into the register file", infile); + `ifdef TSMC_INITIALIZE_FORMAT_BINARY + $readmemb (infile, mem, 0, Nword-1); + `else + $readmemh (infile, mem, 0, Nword-1); + `endif + end + endtask + + // Task for displaying contents of a memory + task printMemoryFromTo; + input [Naddr - 1:0] from; // memory content are printed, start from this address. + input [Naddr - 1:0] to; // memory content are printed, end at this address. + integer i; + begin //{ + $display ("\n%m: Memory content dump"); + if(from < 0 || from > to || to >= Nword) + begin + $display ("Error! Invalid address range (%0d, %0d).", from, to, + "\nUsage: %m (from, to);", + "\n where from >= 0 and to <= %0d.", Nword-1); + end + else + begin + $display ("\n Address\tValue"); + for (i = from ; i <= to ; i = i + 1) + $display ("%d\t%b", i, mem[i]); + end + end //} + endtask //} + + // Task for printing entire memory, including normal array and redundancy array. + task printMemory; + integer i; + begin + $display ("Dumping register file..."); + $display("@ Address, content-----"); + for (i = 0; i < Nword; i = i + 1) begin + $display("@%d, %b", i, mem[i]); + end + end + endtask + + task xMemoryAll; + begin + for (ib = 0 ; ib < Ndata ; ib = ib + 1) + dbuf[ib] = 1'bx; + for (iw = 0 ; iw < Nword ; iw = iw + 1) + mem[iw] = dbuf; + end + endtask + + task zeroMemoryAll; + begin + for (ib = 0 ; ib < Ndata ; ib = ib + 1) + dbuf[ib] = 1'b0; + for (iw = 0 ; iw < Nword ; iw = iw + 1) + mem[iw] = dbuf; + end + endtask + endmodule + + + diff --git a/rtl/memory/tsdn28hpcpuhdb4096x32m4mw_170a_ffg0p99v0c.v b/rtl/memory/tsdn28hpcpuhdb4096x32m4mw_170a_ffg0p99v0c.v new file mode 100644 index 0000000..d6dae0f --- /dev/null +++ b/rtl/memory/tsdn28hpcpuhdb4096x32m4mw_170a_ffg0p99v0c.v @@ -0,0 +1,2991 @@ +//*#*********************************************************************************************************************/ +//*# Software : TSMC MEMORY COMPILER tsn28hpcpuhddpsram_2012.02.00.d.170a */ +//*# Technology : TSMC 28nm CMOS LOGIC High Performance Compact Mobile 1P10M HKMG CU_ELK 0.9V */ +//*# Memory Type : TSMC 28nm High Performance Compact Mobile Ultra High Density Dual Port SRAM with d127 bit cell SVT Periphery */ +//*# Library Name : tsdn28hpcpuhdb4096x32m4mw (user specify : tsdn28hpcpuhdb4096x32m4mw_170a) */ +//*# Library Version: 170a */ +//*# Generated Time : 2024/04/10, 14:02:43 */ +//*#*********************************************************************************************************************/ +//*# */ +//*# STATEMENT OF USE */ +//*# */ +//*# This information contains confidential and proprietary information of TSMC. */ +//*# No part of this information may be reproduced, transmitted, transcribed, */ +//*# stored in a retrieval system, or translated into any human or computer */ +//*# language, in any form or by any means, electronic, mechanical, magnetic, */ +//*# optical, chemical, manual, or otherwise, without the prior written permission */ +//*# of TSMC. This information was prepared for informational purpose and is for */ +//*# use by TSMC's customers only. TSMC reserves the right to make changes in the */ +//*# information at any time and without notice. */ +//*# */ +//*#*********************************************************************************************************************/ +///*******************************************************************************/ +//* Usage Limitation: PLEASE READ CAREFULLY FOR CORRECT USAGE */ +//* The model doesn't support the control enable, data, address signals */ +//* transition at positive clock edge. */ +//* Please have some timing delays between control/data/address and clock signals*/ +//* to ensure the correct behavior. */ +//* */ +//* Please be careful when using non 2^n memory. */ +//* In a non-fully decoded array, a write cycle to a nonexistent address location*/ +//* does not change the memory array contents and output remains the same. */ +//* In a non-fully decoded array, a read cycle to a nonexistent address location */ +//* does not change the memory array contents but output becomes unknown. */ +//* */ +//* In the verilog model, the behavior of unknown clock will corrupt the */ +//* memory data and make output unknown regardless of CEB signal. But in the */ +//* silicon, the unknown clock at CEB high, the memory and output data will be */ +//* held. The verilog model behavior is more conservative in this condition. */ +//* */ +//* The model doesn't identify physical column and row address */ +//* */ +//* The verilog model provides TSMC_CM_UNIT_DELAY mode for the fast function */ +//* simulation. */ +//* All timing values in the specification are not checked in the */ +//* TSMC_CM_UNIT_DELAY mode simulation. */ +//* */ +//* */ +//* */ +//* Please use the verilog simulator version with $recrem timing check support. */ +//* Some earlier simulator versions might support $recovery only, not $recrem. */ +//* */ +//* Template Version : S_01_61101 */ +//****************************************************************************** */ +//* Macro Usage : (+define[MACRO] for Verilog compiliers) */ +//* +TSMC_CM_UNIT_DELAY : Enable fast function simulation. */ +//* +no_warning : Disable all runtime warnings message from this model. */ +//* +TSMC_INITIALIZE_MEM : Initialize the memory data in verilog format. */ +//* +TSMC_INITIALIZE_FAULT : Initialize the memory fault data in verilog format. */ +//* +TSMC_NO_TESTPINS_WARNING : Disable the wrong test pins connection error */ +//* message if necessary. */ +//****************************************************************************** */ + +`resetall +`celldefine + +`timescale 1ns/1ps +`delay_mode_path +`suppress_faults +`enable_portfaults + +module tsdn28hpcpuhdb4096x32m4mw_170a + ( + RTSEL, + WTSEL, + PTSEL, + AA, + DA, + BWEBA, + WEBA,CEBA,CLK, + AB, + DB, + BWEBB, + WEBB,CEBB, + QA, + QB + ); + +// Parameter declarations +parameter N = 32; +parameter W = 4096; +parameter M = 12; +parameter RA = 10; + + wire SLP=1'b0; + wire DSLP=1'b0; + wire SD=1'b0; + input [1:0] RTSEL; + input [1:0] WTSEL; + input [1:0] PTSEL; + +// Input-Output declarations + + input [M-1:0] AA; + input [N-1:0] DA; + input [N-1:0] BWEBA; + + input WEBA; + input CEBA; + input CLK; + input [M-1:0] AB; + input [N-1:0] DB; + input [N-1:0] BWEBB; + input WEBB; + input CEBB; + output [N-1:0] QA; + output [N-1:0] QB; + +`ifdef no_warning +parameter MES_ALL = "OFF"; +`else +parameter MES_ALL = "ON"; +`endif + +`ifdef TSMC_CM_UNIT_DELAY +parameter SRAM_DELAY = 0.010; +`endif +`ifdef TSMC_INITIALIZE_MEM +parameter INITIAL_MEM_DELAY = 0.01; +`else + `ifdef TSMC_INITIALIZE_MEM_USING_DEFAULT_TASKS +parameter INITIAL_MEM_DELAY = 0.01; + `endif +`endif +`ifdef TSMC_INITIALIZE_FAULT +parameter INITIAL_FAULT_DELAY = 0.01; +`endif + +`ifdef TSMC_INITIALIZE_MEM +parameter cdeFileInit = "tsdn28hpcpuhdb4096x32m4mw_170a_initial.cde"; +`endif +`ifdef TSMC_INITIALIZE_FAULT +parameter cdeFileFault = "tsdn28hpcpuhdb4096x32m4mw_170a_fault.cde"; +`endif + +// Registers +reg invalid_aslp; +reg invalid_bslp; +reg invalid_adslp; +reg invalid_bdslp; +reg invalid_sdwk_dslp; + +reg [N-1:0] DAL; +reg [N-1:0] DBL; +reg [N-1:0] bDBL; + +reg [N-1:0] BWEBAL; +reg [N-1:0] BWEBBL; +reg [N-1:0] bBWEBBL; + +reg [M-1:0] AAL; +reg [M-1:0] ABL; + +reg WEBAL,CEBAL; +reg WEBBL,CEBBL; + +wire [N-1:0] QAL; +wire [N-1:0] QBL; + +reg valid_testpin; + + +reg valid_ck,valid_cka,valid_ckb; +reg valid_cea, valid_ceb; +reg valid_wea, valid_web; +reg valid_aa; +reg valid_ab; +reg valid_contentiona,valid_contentionb,valid_contentionc; +reg valid_da31, valid_da30, valid_da29, valid_da28, valid_da27, valid_da26, valid_da25, valid_da24, valid_da23, valid_da22, valid_da21, valid_da20, valid_da19, valid_da18, valid_da17, valid_da16, valid_da15, valid_da14, valid_da13, valid_da12, valid_da11, valid_da10, valid_da9, valid_da8, valid_da7, valid_da6, valid_da5, valid_da4, valid_da3, valid_da2, valid_da1, valid_da0; +reg valid_db31, valid_db30, valid_db29, valid_db28, valid_db27, valid_db26, valid_db25, valid_db24, valid_db23, valid_db22, valid_db21, valid_db20, valid_db19, valid_db18, valid_db17, valid_db16, valid_db15, valid_db14, valid_db13, valid_db12, valid_db11, valid_db10, valid_db9, valid_db8, valid_db7, valid_db6, valid_db5, valid_db4, valid_db3, valid_db2, valid_db1, valid_db0; +reg valid_bwa31, valid_bwa30, valid_bwa29, valid_bwa28, valid_bwa27, valid_bwa26, valid_bwa25, valid_bwa24, valid_bwa23, valid_bwa22, valid_bwa21, valid_bwa20, valid_bwa19, valid_bwa18, valid_bwa17, valid_bwa16, valid_bwa15, valid_bwa14, valid_bwa13, valid_bwa12, valid_bwa11, valid_bwa10, valid_bwa9, valid_bwa8, valid_bwa7, valid_bwa6, valid_bwa5, valid_bwa4, valid_bwa3, valid_bwa2, valid_bwa1, valid_bwa0; +reg valid_bwb31, valid_bwb30, valid_bwb29, valid_bwb28, valid_bwb27, valid_bwb26, valid_bwb25, valid_bwb24, valid_bwb23, valid_bwb22, valid_bwb21, valid_bwb20, valid_bwb19, valid_bwb18, valid_bwb17, valid_bwb16, valid_bwb15, valid_bwb14, valid_bwb13, valid_bwb12, valid_bwb11, valid_bwb10, valid_bwb9, valid_bwb8, valid_bwb7, valid_bwb6, valid_bwb5, valid_bwb4, valid_bwb3, valid_bwb2, valid_bwb1, valid_bwb0; + +reg EN; +reg RDA, RDB; + +reg RCLKA,RCLKB; + + +wire [1:0] bRTSEL; +wire [1:0] bWTSEL; +wire [1:0] bPTSEL; + + +wire [N-1:0] bBWEBA; +wire [N-1:0] bBWEBB; + +wire [N-1:0] bDA; +wire [N-1:0] bDB; + +wire [M-1:0] bAA; +wire [M-1:0] bAB; +wire [RA-1:0] rowAA; +wire [RA-1:0] rowAB; + +wire bWEBA,bWEBB; +wire bCEBA,bCEBB; +wire bCLKA,bCLKB; + +reg [N-1:0] bQA; +reg [N-1:0] bQB; + +wire bBIST; +wire WEA,WEB,CSA,CSB; +wire bAWT = 1'b0; +wire iCEBA = bCEBA; +wire iCEBB = bCEBB; +wire iCLKA = bCLKA; +wire iCLKB = bCLKB; +wire [N-1:0] iBWEBA = bBWEBA; +wire [N-1:0] iBWEBB = bBWEBB; + +wire [N-1:0] bbQA; +wire [N-1:0] bbQB; + +integer i; +integer clk_count; +integer sd_mode; + + + + +// Address Inputs +buf sAA0 (bAA[0], AA[0]); +buf sAB0 (bAB[0], AB[0]); +buf sAA1 (bAA[1], AA[1]); +buf sAB1 (bAB[1], AB[1]); +buf sAA2 (bAA[2], AA[2]); +buf sAB2 (bAB[2], AB[2]); +buf sAA3 (bAA[3], AA[3]); +buf sAB3 (bAB[3], AB[3]); +buf sAA4 (bAA[4], AA[4]); +buf sAB4 (bAB[4], AB[4]); +buf sAA5 (bAA[5], AA[5]); +buf sAB5 (bAB[5], AB[5]); +buf sAA6 (bAA[6], AA[6]); +buf sAB6 (bAB[6], AB[6]); +buf sAA7 (bAA[7], AA[7]); +buf sAB7 (bAB[7], AB[7]); +buf sAA8 (bAA[8], AA[8]); +buf sAB8 (bAB[8], AB[8]); +buf sAA9 (bAA[9], AA[9]); +buf sAB9 (bAB[9], AB[9]); +buf sAA10 (bAA[10], AA[10]); +buf sAB10 (bAB[10], AB[10]); +buf sAA11 (bAA[11], AA[11]); +buf sAB11 (bAB[11], AB[11]); +buf srAA0 (rowAA[0], AA[2]); +buf srAB0 (rowAB[0], AB[2]); +buf srAA1 (rowAA[1], AA[3]); +buf srAB1 (rowAB[1], AB[3]); +buf srAA2 (rowAA[2], AA[4]); +buf srAB2 (rowAB[2], AB[4]); +buf srAA3 (rowAA[3], AA[5]); +buf srAB3 (rowAB[3], AB[5]); +buf srAA4 (rowAA[4], AA[6]); +buf srAB4 (rowAB[4], AB[6]); +buf srAA5 (rowAA[5], AA[7]); +buf srAB5 (rowAB[5], AB[7]); +buf srAA6 (rowAA[6], AA[8]); +buf srAB6 (rowAB[6], AB[8]); +buf srAA7 (rowAA[7], AA[9]); +buf srAB7 (rowAB[7], AB[9]); +buf srAA8 (rowAA[8], AA[10]); +buf srAB8 (rowAB[8], AB[10]); +buf srAA9 (rowAA[9], AA[11]); +buf srAB9 (rowAB[9], AB[11]); + + +// Bit Write/Data Inputs +buf sDA0 (bDA[0], DA[0]); +buf sDB0 (bDB[0], DB[0]); +buf sDA1 (bDA[1], DA[1]); +buf sDB1 (bDB[1], DB[1]); +buf sDA2 (bDA[2], DA[2]); +buf sDB2 (bDB[2], DB[2]); +buf sDA3 (bDA[3], DA[3]); +buf sDB3 (bDB[3], DB[3]); +buf sDA4 (bDA[4], DA[4]); +buf sDB4 (bDB[4], DB[4]); +buf sDA5 (bDA[5], DA[5]); +buf sDB5 (bDB[5], DB[5]); +buf sDA6 (bDA[6], DA[6]); +buf sDB6 (bDB[6], DB[6]); +buf sDA7 (bDA[7], DA[7]); +buf sDB7 (bDB[7], DB[7]); +buf sDA8 (bDA[8], DA[8]); +buf sDB8 (bDB[8], DB[8]); +buf sDA9 (bDA[9], DA[9]); +buf sDB9 (bDB[9], DB[9]); +buf sDA10 (bDA[10], DA[10]); +buf sDB10 (bDB[10], DB[10]); +buf sDA11 (bDA[11], DA[11]); +buf sDB11 (bDB[11], DB[11]); +buf sDA12 (bDA[12], DA[12]); +buf sDB12 (bDB[12], DB[12]); +buf sDA13 (bDA[13], DA[13]); +buf sDB13 (bDB[13], DB[13]); +buf sDA14 (bDA[14], DA[14]); +buf sDB14 (bDB[14], DB[14]); +buf sDA15 (bDA[15], DA[15]); +buf sDB15 (bDB[15], DB[15]); +buf sDA16 (bDA[16], DA[16]); +buf sDB16 (bDB[16], DB[16]); +buf sDA17 (bDA[17], DA[17]); +buf sDB17 (bDB[17], DB[17]); +buf sDA18 (bDA[18], DA[18]); +buf sDB18 (bDB[18], DB[18]); +buf sDA19 (bDA[19], DA[19]); +buf sDB19 (bDB[19], DB[19]); +buf sDA20 (bDA[20], DA[20]); +buf sDB20 (bDB[20], DB[20]); +buf sDA21 (bDA[21], DA[21]); +buf sDB21 (bDB[21], DB[21]); +buf sDA22 (bDA[22], DA[22]); +buf sDB22 (bDB[22], DB[22]); +buf sDA23 (bDA[23], DA[23]); +buf sDB23 (bDB[23], DB[23]); +buf sDA24 (bDA[24], DA[24]); +buf sDB24 (bDB[24], DB[24]); +buf sDA25 (bDA[25], DA[25]); +buf sDB25 (bDB[25], DB[25]); +buf sDA26 (bDA[26], DA[26]); +buf sDB26 (bDB[26], DB[26]); +buf sDA27 (bDA[27], DA[27]); +buf sDB27 (bDB[27], DB[27]); +buf sDA28 (bDA[28], DA[28]); +buf sDB28 (bDB[28], DB[28]); +buf sDA29 (bDA[29], DA[29]); +buf sDB29 (bDB[29], DB[29]); +buf sDA30 (bDA[30], DA[30]); +buf sDB30 (bDB[30], DB[30]); +buf sDA31 (bDA[31], DA[31]); +buf sDB31 (bDB[31], DB[31]); + + +buf sBWEBA0 (bBWEBA[0], BWEBA[0]); +buf sBWEBB0 (bBWEBB[0], BWEBB[0]); +buf sBWEBA1 (bBWEBA[1], BWEBA[1]); +buf sBWEBB1 (bBWEBB[1], BWEBB[1]); +buf sBWEBA2 (bBWEBA[2], BWEBA[2]); +buf sBWEBB2 (bBWEBB[2], BWEBB[2]); +buf sBWEBA3 (bBWEBA[3], BWEBA[3]); +buf sBWEBB3 (bBWEBB[3], BWEBB[3]); +buf sBWEBA4 (bBWEBA[4], BWEBA[4]); +buf sBWEBB4 (bBWEBB[4], BWEBB[4]); +buf sBWEBA5 (bBWEBA[5], BWEBA[5]); +buf sBWEBB5 (bBWEBB[5], BWEBB[5]); +buf sBWEBA6 (bBWEBA[6], BWEBA[6]); +buf sBWEBB6 (bBWEBB[6], BWEBB[6]); +buf sBWEBA7 (bBWEBA[7], BWEBA[7]); +buf sBWEBB7 (bBWEBB[7], BWEBB[7]); +buf sBWEBA8 (bBWEBA[8], BWEBA[8]); +buf sBWEBB8 (bBWEBB[8], BWEBB[8]); +buf sBWEBA9 (bBWEBA[9], BWEBA[9]); +buf sBWEBB9 (bBWEBB[9], BWEBB[9]); +buf sBWEBA10 (bBWEBA[10], BWEBA[10]); +buf sBWEBB10 (bBWEBB[10], BWEBB[10]); +buf sBWEBA11 (bBWEBA[11], BWEBA[11]); +buf sBWEBB11 (bBWEBB[11], BWEBB[11]); +buf sBWEBA12 (bBWEBA[12], BWEBA[12]); +buf sBWEBB12 (bBWEBB[12], BWEBB[12]); +buf sBWEBA13 (bBWEBA[13], BWEBA[13]); +buf sBWEBB13 (bBWEBB[13], BWEBB[13]); +buf sBWEBA14 (bBWEBA[14], BWEBA[14]); +buf sBWEBB14 (bBWEBB[14], BWEBB[14]); +buf sBWEBA15 (bBWEBA[15], BWEBA[15]); +buf sBWEBB15 (bBWEBB[15], BWEBB[15]); +buf sBWEBA16 (bBWEBA[16], BWEBA[16]); +buf sBWEBB16 (bBWEBB[16], BWEBB[16]); +buf sBWEBA17 (bBWEBA[17], BWEBA[17]); +buf sBWEBB17 (bBWEBB[17], BWEBB[17]); +buf sBWEBA18 (bBWEBA[18], BWEBA[18]); +buf sBWEBB18 (bBWEBB[18], BWEBB[18]); +buf sBWEBA19 (bBWEBA[19], BWEBA[19]); +buf sBWEBB19 (bBWEBB[19], BWEBB[19]); +buf sBWEBA20 (bBWEBA[20], BWEBA[20]); +buf sBWEBB20 (bBWEBB[20], BWEBB[20]); +buf sBWEBA21 (bBWEBA[21], BWEBA[21]); +buf sBWEBB21 (bBWEBB[21], BWEBB[21]); +buf sBWEBA22 (bBWEBA[22], BWEBA[22]); +buf sBWEBB22 (bBWEBB[22], BWEBB[22]); +buf sBWEBA23 (bBWEBA[23], BWEBA[23]); +buf sBWEBB23 (bBWEBB[23], BWEBB[23]); +buf sBWEBA24 (bBWEBA[24], BWEBA[24]); +buf sBWEBB24 (bBWEBB[24], BWEBB[24]); +buf sBWEBA25 (bBWEBA[25], BWEBA[25]); +buf sBWEBB25 (bBWEBB[25], BWEBB[25]); +buf sBWEBA26 (bBWEBA[26], BWEBA[26]); +buf sBWEBB26 (bBWEBB[26], BWEBB[26]); +buf sBWEBA27 (bBWEBA[27], BWEBA[27]); +buf sBWEBB27 (bBWEBB[27], BWEBB[27]); +buf sBWEBA28 (bBWEBA[28], BWEBA[28]); +buf sBWEBB28 (bBWEBB[28], BWEBB[28]); +buf sBWEBA29 (bBWEBA[29], BWEBA[29]); +buf sBWEBB29 (bBWEBB[29], BWEBB[29]); +buf sBWEBA30 (bBWEBA[30], BWEBA[30]); +buf sBWEBB30 (bBWEBB[30], BWEBB[30]); +buf sBWEBA31 (bBWEBA[31], BWEBA[31]); +buf sBWEBB31 (bBWEBB[31], BWEBB[31]); + + +// Input Controls +buf sWEBA (bWEBA, WEBA); +buf sWEBB (bWEBB, WEBB); +wire bSLP = 1'b0; +wire bDSLP = 1'b0; +wire bSD = 1'b0; + +buf sCEBA (bCEBA, CEBA); +buf sCEBB (bCEBB, CEBB); + +buf sCLKA (bCLKA, CLK); +buf sCLKB (bCLKB, CLK); +assign bBIST = 1'b0; + +buf sRTSEL0 (bRTSEL[0], RTSEL[0]); +buf sRTSEL1 (bRTSEL[1], RTSEL[1]); +buf sWTSEL0 (bWTSEL[0], WTSEL[0]); +buf sWTSEL1 (bWTSEL[1], WTSEL[1]); +buf sPTSEL0 (bPTSEL[0], PTSEL[0]); +buf sPTSEL1 (bPTSEL[1], PTSEL[1]); + +// Output Data +buf sQA0 (QA[0], bbQA[0]); +buf sQA1 (QA[1], bbQA[1]); +buf sQA2 (QA[2], bbQA[2]); +buf sQA3 (QA[3], bbQA[3]); +buf sQA4 (QA[4], bbQA[4]); +buf sQA5 (QA[5], bbQA[5]); +buf sQA6 (QA[6], bbQA[6]); +buf sQA7 (QA[7], bbQA[7]); +buf sQA8 (QA[8], bbQA[8]); +buf sQA9 (QA[9], bbQA[9]); +buf sQA10 (QA[10], bbQA[10]); +buf sQA11 (QA[11], bbQA[11]); +buf sQA12 (QA[12], bbQA[12]); +buf sQA13 (QA[13], bbQA[13]); +buf sQA14 (QA[14], bbQA[14]); +buf sQA15 (QA[15], bbQA[15]); +buf sQA16 (QA[16], bbQA[16]); +buf sQA17 (QA[17], bbQA[17]); +buf sQA18 (QA[18], bbQA[18]); +buf sQA19 (QA[19], bbQA[19]); +buf sQA20 (QA[20], bbQA[20]); +buf sQA21 (QA[21], bbQA[21]); +buf sQA22 (QA[22], bbQA[22]); +buf sQA23 (QA[23], bbQA[23]); +buf sQA24 (QA[24], bbQA[24]); +buf sQA25 (QA[25], bbQA[25]); +buf sQA26 (QA[26], bbQA[26]); +buf sQA27 (QA[27], bbQA[27]); +buf sQA28 (QA[28], bbQA[28]); +buf sQA29 (QA[29], bbQA[29]); +buf sQA30 (QA[30], bbQA[30]); +buf sQA31 (QA[31], bbQA[31]); + +buf sQB0 (QB[0], bbQB[0]); +buf sQB1 (QB[1], bbQB[1]); +buf sQB2 (QB[2], bbQB[2]); +buf sQB3 (QB[3], bbQB[3]); +buf sQB4 (QB[4], bbQB[4]); +buf sQB5 (QB[5], bbQB[5]); +buf sQB6 (QB[6], bbQB[6]); +buf sQB7 (QB[7], bbQB[7]); +buf sQB8 (QB[8], bbQB[8]); +buf sQB9 (QB[9], bbQB[9]); +buf sQB10 (QB[10], bbQB[10]); +buf sQB11 (QB[11], bbQB[11]); +buf sQB12 (QB[12], bbQB[12]); +buf sQB13 (QB[13], bbQB[13]); +buf sQB14 (QB[14], bbQB[14]); +buf sQB15 (QB[15], bbQB[15]); +buf sQB16 (QB[16], bbQB[16]); +buf sQB17 (QB[17], bbQB[17]); +buf sQB18 (QB[18], bbQB[18]); +buf sQB19 (QB[19], bbQB[19]); +buf sQB20 (QB[20], bbQB[20]); +buf sQB21 (QB[21], bbQB[21]); +buf sQB22 (QB[22], bbQB[22]); +buf sQB23 (QB[23], bbQB[23]); +buf sQB24 (QB[24], bbQB[24]); +buf sQB25 (QB[25], bbQB[25]); +buf sQB26 (QB[26], bbQB[26]); +buf sQB27 (QB[27], bbQB[27]); +buf sQB28 (QB[28], bbQB[28]); +buf sQB29 (QB[29], bbQB[29]); +buf sQB30 (QB[30], bbQB[30]); +buf sQB31 (QB[31], bbQB[31]); + +assign bbQA=bQA; +assign bbQB=bQB; + +//and sWEA (WEA, !bWEBA, !bCEBA); +//and sWEB (WEB, !bWEBB, !bCEBB); +assign WEA = !bSLP & !bDSLP & !bSD & !bCEBA & !bWEBA; +assign WEB = !bSLP & !bDSLP & !bSD & !bCEBB & !bWEBB; + +//buf sCSA (CSA, !bCEBA); +//buf sCSB (CSB, !bCEBB); +assign CSA = !bSLP & !bDSLP & !bSD & !bCEBA; +assign CSB = !bSLP & !bDSLP & !bSD & !bCEBB; + +wire check_noidle_b = ~CEBBL & ~bSD & ~bDSLP & ~bSLP; +wire check_idle_b = CEBBL & ~bSD & ~bDSLP & ~bSLP; +wire check_noidle_a = ~CEBAL & ~bSD & ~bDSLP & ~bSLP; +wire check_idle_a = CEBAL & ~bSD & ~bDSLP & ~bSLP; +wire check_noidle_norm_b = check_noidle_b & ~bBIST; +wire check_noidle_bist_b = check_noidle_b & bBIST; +wire check_idle_norm_b = check_idle_b & ~bBIST; +wire check_idle_bist_b = check_idle_b & bBIST; +wire check_noidle_norm_a = check_noidle_a & ~bBIST; +wire check_noidle_bist_a = check_noidle_a & bBIST; +wire check_idle_norm_a = check_idle_a & !bBIST; +wire check_idle_bist_a = check_idle_a & bBIST; + +wire check_ceb = (~iCEBA | ~iCEBB) & ~bSD & ~bDSLP & ~bSLP; +wire check_ceba = ~iCEBA & ~bSD & ~bDSLP & ~bSLP; +wire check_cebb = ~iCEBB & ~bSD & ~bDSLP & ~bSLP; +wire check_cebm = (~iCEBA | ~iCEBB) & ~bSD & ~bDSLP & ~bSLP; +wire check_ceb_a = ~iCEBA & iCEBB & ~bSD & ~bDSLP & ~bSLP; +wire check_ceb_b = iCEBA & ~iCEBB & ~bSD & ~bDSLP & ~bSLP; +wire check_ceb_ab = ~iCEBA & ~iCEBB & ~bSD & ~bDSLP & ~bSLP; + + + + + +wire check_slp = !bSD & !bDSLP; +wire check_dslp = !bSD & !bSLP; + + +`ifdef TSMC_CM_UNIT_DELAY +`else +specify + specparam PATHPULSE$ = ( 0, 0.001 ); + +specparam +tckl = 0.0874246, +tckh = 0.0874246, +tcyc = 0.6773873, + + +taas = 0.0529846, +taah = 0.0587300, +tdas = 0.0100000, +tdah = 0.0703054, +tcas = 0.0766600, +tcah = 0.0771677, +twas = 0.0713800, +twah = 0.0580700, +tbwas = 0.0114977, +tbwah = 0.0699331, + +tabs = 0.0100000, +tabh = 0.0771677, +tdbs = 0.0100000, +tdbh = 0.1017654, +tcbs = 0.0766600, +tcbh = 0.0771677, +twbs = 0.0100000, +twbh = 0.0771677, +tbwbs = 0.0100000, +tbwbh = 0.1018754, + +ttests = 0.677, +ttesth = 0.677, +tcda = 0.3574728, +tcdb = 0.6773873, +`ifdef TSMC_CM_READ_X_SQUASHING +tholda = 0.3574728, +tholdb = 0.6773873; +`else +tholda = 0.2078315, +tholdb = 0.4702658; +`endif + + $setuphold (posedge CLK &&& check_noidle_a, posedge RTSEL[0], ttests, 0, valid_testpin); + $setuphold (posedge CLK &&& check_noidle_a, negedge RTSEL[0], ttests, 0, valid_testpin); + $setuphold (posedge CLK &&& check_idle_a, posedge RTSEL[0], 0, ttesth, valid_testpin); + $setuphold (posedge CLK &&& check_idle_a, negedge RTSEL[0], 0, ttesth, valid_testpin); + $setuphold (posedge CLK &&& check_noidle_a, posedge RTSEL[1], ttests, 0, valid_testpin); + $setuphold (posedge CLK &&& check_noidle_a, negedge RTSEL[1], ttests, 0, valid_testpin); + $setuphold (posedge CLK &&& check_idle_a, posedge RTSEL[1], 0, ttesth, valid_testpin); + $setuphold (posedge CLK &&& check_idle_a, negedge RTSEL[1], 0, ttesth, valid_testpin); + $setuphold (posedge CLK &&& check_noidle_a, posedge WTSEL[0], ttests, 0, valid_testpin); + $setuphold (posedge CLK &&& check_noidle_a, negedge WTSEL[0], ttests, 0, valid_testpin); + $setuphold (posedge CLK &&& check_idle_a, posedge WTSEL[0], 0, ttesth, valid_testpin); + $setuphold (posedge CLK &&& check_idle_a, negedge WTSEL[0], 0, ttesth, valid_testpin); + $setuphold (posedge CLK &&& check_noidle_a, posedge WTSEL[1], ttests, 0, valid_testpin); + $setuphold (posedge CLK &&& check_noidle_a, negedge WTSEL[1], ttests, 0, valid_testpin); + $setuphold (posedge CLK &&& check_idle_a, posedge WTSEL[1], 0, ttesth, valid_testpin); + $setuphold (posedge CLK &&& check_idle_a, negedge WTSEL[1], 0, ttesth, valid_testpin); + $setuphold (posedge CLK &&& check_noidle_a, posedge PTSEL[0], ttests, 0, valid_testpin); + $setuphold (posedge CLK &&& check_noidle_a, negedge PTSEL[0], ttests, 0, valid_testpin); + $setuphold (posedge CLK &&& check_idle_a, posedge PTSEL[0], 0, ttesth, valid_testpin); + $setuphold (posedge CLK &&& check_idle_a, negedge PTSEL[0], 0, ttesth, valid_testpin); + $setuphold (posedge CLK &&& check_noidle_a, posedge PTSEL[1], ttests, 0, valid_testpin); + $setuphold (posedge CLK &&& check_noidle_a, negedge PTSEL[1], ttests, 0, valid_testpin); + $setuphold (posedge CLK &&& check_idle_a, posedge PTSEL[1], 0, ttesth, valid_testpin); + $setuphold (posedge CLK &&& check_idle_a, negedge PTSEL[1], 0, ttesth, valid_testpin); + $setuphold (posedge CLK &&& check_noidle_b, posedge RTSEL[0], ttests, 0, valid_testpin); + $setuphold (posedge CLK &&& check_noidle_b, negedge RTSEL[0], ttests, 0, valid_testpin); + $setuphold (posedge CLK &&& check_idle_b, posedge RTSEL[0], 0, ttesth, valid_testpin); + $setuphold (posedge CLK &&& check_idle_b, negedge RTSEL[0], 0, ttesth, valid_testpin); + $setuphold (posedge CLK &&& check_noidle_b, posedge RTSEL[1], ttests, 0, valid_testpin); + $setuphold (posedge CLK &&& check_noidle_b, negedge RTSEL[1], ttests, 0, valid_testpin); + $setuphold (posedge CLK &&& check_idle_b, posedge RTSEL[1], 0, ttesth, valid_testpin); + $setuphold (posedge CLK &&& check_idle_b, negedge RTSEL[1], 0, ttesth, valid_testpin); + $setuphold (posedge CLK &&& check_noidle_b, posedge WTSEL[0], ttests, 0, valid_testpin); + $setuphold (posedge CLK &&& check_noidle_b, negedge WTSEL[0], ttests, 0, valid_testpin); + $setuphold (posedge CLK &&& check_idle_b, posedge WTSEL[0], 0, ttesth, valid_testpin); + $setuphold (posedge CLK &&& check_idle_b, negedge WTSEL[0], 0, ttesth, valid_testpin); + $setuphold (posedge CLK &&& check_noidle_b, posedge WTSEL[1], ttests, 0, valid_testpin); + $setuphold (posedge CLK &&& check_noidle_b, negedge WTSEL[1], ttests, 0, valid_testpin); + $setuphold (posedge CLK &&& check_idle_b, posedge WTSEL[1], 0, ttesth, valid_testpin); + $setuphold (posedge CLK &&& check_idle_b, negedge WTSEL[1], 0, ttesth, valid_testpin); + $setuphold (posedge CLK &&& check_noidle_b, posedge PTSEL[0], ttests, 0, valid_testpin); + $setuphold (posedge CLK &&& check_noidle_b, negedge PTSEL[0], ttests, 0, valid_testpin); + $setuphold (posedge CLK &&& check_idle_b, posedge PTSEL[0], 0, ttesth, valid_testpin); + $setuphold (posedge CLK &&& check_idle_b, negedge PTSEL[0], 0, ttesth, valid_testpin); + $setuphold (posedge CLK &&& check_noidle_b, posedge PTSEL[1], ttests, 0, valid_testpin); + $setuphold (posedge CLK &&& check_noidle_b, negedge PTSEL[1], ttests, 0, valid_testpin); + $setuphold (posedge CLK &&& check_idle_b, posedge PTSEL[1], 0, ttesth, valid_testpin); + $setuphold (posedge CLK &&& check_idle_b, negedge PTSEL[1], 0, ttesth, valid_testpin); + + + + + + + + + + + $setuphold (posedge CLK &&& CSA, posedge AA[0], taas, taah, valid_aa); + $setuphold (posedge CLK &&& CSA, negedge AA[0], taas, taah, valid_aa); + $setuphold (posedge CLK &&& CSB, posedge AB[0], tabs, tabh, valid_ab); + $setuphold (posedge CLK &&& CSB, negedge AB[0], tabs, tabh, valid_ab); + $setuphold (posedge CLK &&& CSA, posedge AA[1], taas, taah, valid_aa); + $setuphold (posedge CLK &&& CSA, negedge AA[1], taas, taah, valid_aa); + $setuphold (posedge CLK &&& CSB, posedge AB[1], tabs, tabh, valid_ab); + $setuphold (posedge CLK &&& CSB, negedge AB[1], tabs, tabh, valid_ab); + $setuphold (posedge CLK &&& CSA, posedge AA[2], taas, taah, valid_aa); + $setuphold (posedge CLK &&& CSA, negedge AA[2], taas, taah, valid_aa); + $setuphold (posedge CLK &&& CSB, posedge AB[2], tabs, tabh, valid_ab); + $setuphold (posedge CLK &&& CSB, negedge AB[2], tabs, tabh, valid_ab); + $setuphold (posedge CLK &&& CSA, posedge AA[3], taas, taah, valid_aa); + $setuphold (posedge CLK &&& CSA, negedge AA[3], taas, taah, valid_aa); + $setuphold (posedge CLK &&& CSB, posedge AB[3], tabs, tabh, valid_ab); + $setuphold (posedge CLK &&& CSB, negedge AB[3], tabs, tabh, valid_ab); + $setuphold (posedge CLK &&& CSA, posedge AA[4], taas, taah, valid_aa); + $setuphold (posedge CLK &&& CSA, negedge AA[4], taas, taah, valid_aa); + $setuphold (posedge CLK &&& CSB, posedge AB[4], tabs, tabh, valid_ab); + $setuphold (posedge CLK &&& CSB, negedge AB[4], tabs, tabh, valid_ab); + $setuphold (posedge CLK &&& CSA, posedge AA[5], taas, taah, valid_aa); + $setuphold (posedge CLK &&& CSA, negedge AA[5], taas, taah, valid_aa); + $setuphold (posedge CLK &&& CSB, posedge AB[5], tabs, tabh, valid_ab); + $setuphold (posedge CLK &&& CSB, negedge AB[5], tabs, tabh, valid_ab); + $setuphold (posedge CLK &&& CSA, posedge AA[6], taas, taah, valid_aa); + $setuphold (posedge CLK &&& CSA, negedge AA[6], taas, taah, valid_aa); + $setuphold (posedge CLK &&& CSB, posedge AB[6], tabs, tabh, valid_ab); + $setuphold (posedge CLK &&& CSB, negedge AB[6], tabs, tabh, valid_ab); + $setuphold (posedge CLK &&& CSA, posedge AA[7], taas, taah, valid_aa); + $setuphold (posedge CLK &&& CSA, negedge AA[7], taas, taah, valid_aa); + $setuphold (posedge CLK &&& CSB, posedge AB[7], tabs, tabh, valid_ab); + $setuphold (posedge CLK &&& CSB, negedge AB[7], tabs, tabh, valid_ab); + $setuphold (posedge CLK &&& CSA, posedge AA[8], taas, taah, valid_aa); + $setuphold (posedge CLK &&& CSA, negedge AA[8], taas, taah, valid_aa); + $setuphold (posedge CLK &&& CSB, posedge AB[8], tabs, tabh, valid_ab); + $setuphold (posedge CLK &&& CSB, negedge AB[8], tabs, tabh, valid_ab); + $setuphold (posedge CLK &&& CSA, posedge AA[9], taas, taah, valid_aa); + $setuphold (posedge CLK &&& CSA, negedge AA[9], taas, taah, valid_aa); + $setuphold (posedge CLK &&& CSB, posedge AB[9], tabs, tabh, valid_ab); + $setuphold (posedge CLK &&& CSB, negedge AB[9], tabs, tabh, valid_ab); + $setuphold (posedge CLK &&& CSA, posedge AA[10], taas, taah, valid_aa); + $setuphold (posedge CLK &&& CSA, negedge AA[10], taas, taah, valid_aa); + $setuphold (posedge CLK &&& CSB, posedge AB[10], tabs, tabh, valid_ab); + $setuphold (posedge CLK &&& CSB, negedge AB[10], tabs, tabh, valid_ab); + $setuphold (posedge CLK &&& CSA, posedge AA[11], taas, taah, valid_aa); + $setuphold (posedge CLK &&& CSA, negedge AA[11], taas, taah, valid_aa); + $setuphold (posedge CLK &&& CSB, posedge AB[11], tabs, tabh, valid_ab); + $setuphold (posedge CLK &&& CSB, negedge AB[11], tabs, tabh, valid_ab); + + $setuphold (posedge CLK &&& WEA, posedge DA[0], tdas, tdah, valid_da0); + $setuphold (posedge CLK &&& WEA, negedge DA[0], tdas, tdah, valid_da0); + $setuphold (posedge CLK &&& WEB, posedge DB[0], tdbs, tdbh, valid_db0); + $setuphold (posedge CLK &&& WEB, negedge DB[0], tdbs, tdbh, valid_db0); + + $setuphold (posedge CLK &&& WEA, posedge BWEBA[0], tbwas, tbwah, valid_bwa0); + $setuphold (posedge CLK &&& WEA, negedge BWEBA[0], tbwas, tbwah, valid_bwa0); + $setuphold (posedge CLK &&& WEB, posedge BWEBB[0], tbwbs, tbwbh, valid_bwb0); + $setuphold (posedge CLK &&& WEB, negedge BWEBB[0], tbwbs, tbwbh, valid_bwb0); + $setuphold (posedge CLK &&& WEA, posedge DA[1], tdas, tdah, valid_da1); + $setuphold (posedge CLK &&& WEA, negedge DA[1], tdas, tdah, valid_da1); + $setuphold (posedge CLK &&& WEB, posedge DB[1], tdbs, tdbh, valid_db1); + $setuphold (posedge CLK &&& WEB, negedge DB[1], tdbs, tdbh, valid_db1); + + $setuphold (posedge CLK &&& WEA, posedge BWEBA[1], tbwas, tbwah, valid_bwa1); + $setuphold (posedge CLK &&& WEA, negedge BWEBA[1], tbwas, tbwah, valid_bwa1); + $setuphold (posedge CLK &&& WEB, posedge BWEBB[1], tbwbs, tbwbh, valid_bwb1); + $setuphold (posedge CLK &&& WEB, negedge BWEBB[1], tbwbs, tbwbh, valid_bwb1); + $setuphold (posedge CLK &&& WEA, posedge DA[2], tdas, tdah, valid_da2); + $setuphold (posedge CLK &&& WEA, negedge DA[2], tdas, tdah, valid_da2); + $setuphold (posedge CLK &&& WEB, posedge DB[2], tdbs, tdbh, valid_db2); + $setuphold (posedge CLK &&& WEB, negedge DB[2], tdbs, tdbh, valid_db2); + + $setuphold (posedge CLK &&& WEA, posedge BWEBA[2], tbwas, tbwah, valid_bwa2); + $setuphold (posedge CLK &&& WEA, negedge BWEBA[2], tbwas, tbwah, valid_bwa2); + $setuphold (posedge CLK &&& WEB, posedge BWEBB[2], tbwbs, tbwbh, valid_bwb2); + $setuphold (posedge CLK &&& WEB, negedge BWEBB[2], tbwbs, tbwbh, valid_bwb2); + $setuphold (posedge CLK &&& WEA, posedge DA[3], tdas, tdah, valid_da3); + $setuphold (posedge CLK &&& WEA, negedge DA[3], tdas, tdah, valid_da3); + $setuphold (posedge CLK &&& WEB, posedge DB[3], tdbs, tdbh, valid_db3); + $setuphold (posedge CLK &&& WEB, negedge DB[3], tdbs, tdbh, valid_db3); + + $setuphold (posedge CLK &&& WEA, posedge BWEBA[3], tbwas, tbwah, valid_bwa3); + $setuphold (posedge CLK &&& WEA, negedge BWEBA[3], tbwas, tbwah, valid_bwa3); + $setuphold (posedge CLK &&& WEB, posedge BWEBB[3], tbwbs, tbwbh, valid_bwb3); + $setuphold (posedge CLK &&& WEB, negedge BWEBB[3], tbwbs, tbwbh, valid_bwb3); + $setuphold (posedge CLK &&& WEA, posedge DA[4], tdas, tdah, valid_da4); + $setuphold (posedge CLK &&& WEA, negedge DA[4], tdas, tdah, valid_da4); + $setuphold (posedge CLK &&& WEB, posedge DB[4], tdbs, tdbh, valid_db4); + $setuphold (posedge CLK &&& WEB, negedge DB[4], tdbs, tdbh, valid_db4); + + $setuphold (posedge CLK &&& WEA, posedge BWEBA[4], tbwas, tbwah, valid_bwa4); + $setuphold (posedge CLK &&& WEA, negedge BWEBA[4], tbwas, tbwah, valid_bwa4); + $setuphold (posedge CLK &&& WEB, posedge BWEBB[4], tbwbs, tbwbh, valid_bwb4); + $setuphold (posedge CLK &&& WEB, negedge BWEBB[4], tbwbs, tbwbh, valid_bwb4); + $setuphold (posedge CLK &&& WEA, posedge DA[5], tdas, tdah, valid_da5); + $setuphold (posedge CLK &&& WEA, negedge DA[5], tdas, tdah, valid_da5); + $setuphold (posedge CLK &&& WEB, posedge DB[5], tdbs, tdbh, valid_db5); + $setuphold (posedge CLK &&& WEB, negedge DB[5], tdbs, tdbh, valid_db5); + + $setuphold (posedge CLK &&& WEA, posedge BWEBA[5], tbwas, tbwah, valid_bwa5); + $setuphold (posedge CLK &&& WEA, negedge BWEBA[5], tbwas, tbwah, valid_bwa5); + $setuphold (posedge CLK &&& WEB, posedge BWEBB[5], tbwbs, tbwbh, valid_bwb5); + $setuphold (posedge CLK &&& WEB, negedge BWEBB[5], tbwbs, tbwbh, valid_bwb5); + $setuphold (posedge CLK &&& WEA, posedge DA[6], tdas, tdah, valid_da6); + $setuphold (posedge CLK &&& WEA, negedge DA[6], tdas, tdah, valid_da6); + $setuphold (posedge CLK &&& WEB, posedge DB[6], tdbs, tdbh, valid_db6); + $setuphold (posedge CLK &&& WEB, negedge DB[6], tdbs, tdbh, valid_db6); + + $setuphold (posedge CLK &&& WEA, posedge BWEBA[6], tbwas, tbwah, valid_bwa6); + $setuphold (posedge CLK &&& WEA, negedge BWEBA[6], tbwas, tbwah, valid_bwa6); + $setuphold (posedge CLK &&& WEB, posedge BWEBB[6], tbwbs, tbwbh, valid_bwb6); + $setuphold (posedge CLK &&& WEB, negedge BWEBB[6], tbwbs, tbwbh, valid_bwb6); + $setuphold (posedge CLK &&& WEA, posedge DA[7], tdas, tdah, valid_da7); + $setuphold (posedge CLK &&& WEA, negedge DA[7], tdas, tdah, valid_da7); + $setuphold (posedge CLK &&& WEB, posedge DB[7], tdbs, tdbh, valid_db7); + $setuphold (posedge CLK &&& WEB, negedge DB[7], tdbs, tdbh, valid_db7); + + $setuphold (posedge CLK &&& WEA, posedge BWEBA[7], tbwas, tbwah, valid_bwa7); + $setuphold (posedge CLK &&& WEA, negedge BWEBA[7], tbwas, tbwah, valid_bwa7); + $setuphold (posedge CLK &&& WEB, posedge BWEBB[7], tbwbs, tbwbh, valid_bwb7); + $setuphold (posedge CLK &&& WEB, negedge BWEBB[7], tbwbs, tbwbh, valid_bwb7); + $setuphold (posedge CLK &&& WEA, posedge DA[8], tdas, tdah, valid_da8); + $setuphold (posedge CLK &&& WEA, negedge DA[8], tdas, tdah, valid_da8); + $setuphold (posedge CLK &&& WEB, posedge DB[8], tdbs, tdbh, valid_db8); + $setuphold (posedge CLK &&& WEB, negedge DB[8], tdbs, tdbh, valid_db8); + + $setuphold (posedge CLK &&& WEA, posedge BWEBA[8], tbwas, tbwah, valid_bwa8); + $setuphold (posedge CLK &&& WEA, negedge BWEBA[8], tbwas, tbwah, valid_bwa8); + $setuphold (posedge CLK &&& WEB, posedge BWEBB[8], tbwbs, tbwbh, valid_bwb8); + $setuphold (posedge CLK &&& WEB, negedge BWEBB[8], tbwbs, tbwbh, valid_bwb8); + $setuphold (posedge CLK &&& WEA, posedge DA[9], tdas, tdah, valid_da9); + $setuphold (posedge CLK &&& WEA, negedge DA[9], tdas, tdah, valid_da9); + $setuphold (posedge CLK &&& WEB, posedge DB[9], tdbs, tdbh, valid_db9); + $setuphold (posedge CLK &&& WEB, negedge DB[9], tdbs, tdbh, valid_db9); + + $setuphold (posedge CLK &&& WEA, posedge BWEBA[9], tbwas, tbwah, valid_bwa9); + $setuphold (posedge CLK &&& WEA, negedge BWEBA[9], tbwas, tbwah, valid_bwa9); + $setuphold (posedge CLK &&& WEB, posedge BWEBB[9], tbwbs, tbwbh, valid_bwb9); + $setuphold (posedge CLK &&& WEB, negedge BWEBB[9], tbwbs, tbwbh, valid_bwb9); + $setuphold (posedge CLK &&& WEA, posedge DA[10], tdas, tdah, valid_da10); + $setuphold (posedge CLK &&& WEA, negedge DA[10], tdas, tdah, valid_da10); + $setuphold (posedge CLK &&& WEB, posedge DB[10], tdbs, tdbh, valid_db10); + $setuphold (posedge CLK &&& WEB, negedge DB[10], tdbs, tdbh, valid_db10); + + $setuphold (posedge CLK &&& WEA, posedge BWEBA[10], tbwas, tbwah, valid_bwa10); + $setuphold (posedge CLK &&& WEA, negedge BWEBA[10], tbwas, tbwah, valid_bwa10); + $setuphold (posedge CLK &&& WEB, posedge BWEBB[10], tbwbs, tbwbh, valid_bwb10); + $setuphold (posedge CLK &&& WEB, negedge BWEBB[10], tbwbs, tbwbh, valid_bwb10); + $setuphold (posedge CLK &&& WEA, posedge DA[11], tdas, tdah, valid_da11); + $setuphold (posedge CLK &&& WEA, negedge DA[11], tdas, tdah, valid_da11); + $setuphold (posedge CLK &&& WEB, posedge DB[11], tdbs, tdbh, valid_db11); + $setuphold (posedge CLK &&& WEB, negedge DB[11], tdbs, tdbh, valid_db11); + + $setuphold (posedge CLK &&& WEA, posedge BWEBA[11], tbwas, tbwah, valid_bwa11); + $setuphold (posedge CLK &&& WEA, negedge BWEBA[11], tbwas, tbwah, valid_bwa11); + $setuphold (posedge CLK &&& WEB, posedge BWEBB[11], tbwbs, tbwbh, valid_bwb11); + $setuphold (posedge CLK &&& WEB, negedge BWEBB[11], tbwbs, tbwbh, valid_bwb11); + $setuphold (posedge CLK &&& WEA, posedge DA[12], tdas, tdah, valid_da12); + $setuphold (posedge CLK &&& WEA, negedge DA[12], tdas, tdah, valid_da12); + $setuphold (posedge CLK &&& WEB, posedge DB[12], tdbs, tdbh, valid_db12); + $setuphold (posedge CLK &&& WEB, negedge DB[12], tdbs, tdbh, valid_db12); + + $setuphold (posedge CLK &&& WEA, posedge BWEBA[12], tbwas, tbwah, valid_bwa12); + $setuphold (posedge CLK &&& WEA, negedge BWEBA[12], tbwas, tbwah, valid_bwa12); + $setuphold (posedge CLK &&& WEB, posedge BWEBB[12], tbwbs, tbwbh, valid_bwb12); + $setuphold (posedge CLK &&& WEB, negedge BWEBB[12], tbwbs, tbwbh, valid_bwb12); + $setuphold (posedge CLK &&& WEA, posedge DA[13], tdas, tdah, valid_da13); + $setuphold (posedge CLK &&& WEA, negedge DA[13], tdas, tdah, valid_da13); + $setuphold (posedge CLK &&& WEB, posedge DB[13], tdbs, tdbh, valid_db13); + $setuphold (posedge CLK &&& WEB, negedge DB[13], tdbs, tdbh, valid_db13); + + $setuphold (posedge CLK &&& WEA, posedge BWEBA[13], tbwas, tbwah, valid_bwa13); + $setuphold (posedge CLK &&& WEA, negedge BWEBA[13], tbwas, tbwah, valid_bwa13); + $setuphold (posedge CLK &&& WEB, posedge BWEBB[13], tbwbs, tbwbh, valid_bwb13); + $setuphold (posedge CLK &&& WEB, negedge BWEBB[13], tbwbs, tbwbh, valid_bwb13); + $setuphold (posedge CLK &&& WEA, posedge DA[14], tdas, tdah, valid_da14); + $setuphold (posedge CLK &&& WEA, negedge DA[14], tdas, tdah, valid_da14); + $setuphold (posedge CLK &&& WEB, posedge DB[14], tdbs, tdbh, valid_db14); + $setuphold (posedge CLK &&& WEB, negedge DB[14], tdbs, tdbh, valid_db14); + + $setuphold (posedge CLK &&& WEA, posedge BWEBA[14], tbwas, tbwah, valid_bwa14); + $setuphold (posedge CLK &&& WEA, negedge BWEBA[14], tbwas, tbwah, valid_bwa14); + $setuphold (posedge CLK &&& WEB, posedge BWEBB[14], tbwbs, tbwbh, valid_bwb14); + $setuphold (posedge CLK &&& WEB, negedge BWEBB[14], tbwbs, tbwbh, valid_bwb14); + $setuphold (posedge CLK &&& WEA, posedge DA[15], tdas, tdah, valid_da15); + $setuphold (posedge CLK &&& WEA, negedge DA[15], tdas, tdah, valid_da15); + $setuphold (posedge CLK &&& WEB, posedge DB[15], tdbs, tdbh, valid_db15); + $setuphold (posedge CLK &&& WEB, negedge DB[15], tdbs, tdbh, valid_db15); + + $setuphold (posedge CLK &&& WEA, posedge BWEBA[15], tbwas, tbwah, valid_bwa15); + $setuphold (posedge CLK &&& WEA, negedge BWEBA[15], tbwas, tbwah, valid_bwa15); + $setuphold (posedge CLK &&& WEB, posedge BWEBB[15], tbwbs, tbwbh, valid_bwb15); + $setuphold (posedge CLK &&& WEB, negedge BWEBB[15], tbwbs, tbwbh, valid_bwb15); + $setuphold (posedge CLK &&& WEA, posedge DA[16], tdas, tdah, valid_da16); + $setuphold (posedge CLK &&& WEA, negedge DA[16], tdas, tdah, valid_da16); + $setuphold (posedge CLK &&& WEB, posedge DB[16], tdbs, tdbh, valid_db16); + $setuphold (posedge CLK &&& WEB, negedge DB[16], tdbs, tdbh, valid_db16); + + $setuphold (posedge CLK &&& WEA, posedge BWEBA[16], tbwas, tbwah, valid_bwa16); + $setuphold (posedge CLK &&& WEA, negedge BWEBA[16], tbwas, tbwah, valid_bwa16); + $setuphold (posedge CLK &&& WEB, posedge BWEBB[16], tbwbs, tbwbh, valid_bwb16); + $setuphold (posedge CLK &&& WEB, negedge BWEBB[16], tbwbs, tbwbh, valid_bwb16); + $setuphold (posedge CLK &&& WEA, posedge DA[17], tdas, tdah, valid_da17); + $setuphold (posedge CLK &&& WEA, negedge DA[17], tdas, tdah, valid_da17); + $setuphold (posedge CLK &&& WEB, posedge DB[17], tdbs, tdbh, valid_db17); + $setuphold (posedge CLK &&& WEB, negedge DB[17], tdbs, tdbh, valid_db17); + + $setuphold (posedge CLK &&& WEA, posedge BWEBA[17], tbwas, tbwah, valid_bwa17); + $setuphold (posedge CLK &&& WEA, negedge BWEBA[17], tbwas, tbwah, valid_bwa17); + $setuphold (posedge CLK &&& WEB, posedge BWEBB[17], tbwbs, tbwbh, valid_bwb17); + $setuphold (posedge CLK &&& WEB, negedge BWEBB[17], tbwbs, tbwbh, valid_bwb17); + $setuphold (posedge CLK &&& WEA, posedge DA[18], tdas, tdah, valid_da18); + $setuphold (posedge CLK &&& WEA, negedge DA[18], tdas, tdah, valid_da18); + $setuphold (posedge CLK &&& WEB, posedge DB[18], tdbs, tdbh, valid_db18); + $setuphold (posedge CLK &&& WEB, negedge DB[18], tdbs, tdbh, valid_db18); + + $setuphold (posedge CLK &&& WEA, posedge BWEBA[18], tbwas, tbwah, valid_bwa18); + $setuphold (posedge CLK &&& WEA, negedge BWEBA[18], tbwas, tbwah, valid_bwa18); + $setuphold (posedge CLK &&& WEB, posedge BWEBB[18], tbwbs, tbwbh, valid_bwb18); + $setuphold (posedge CLK &&& WEB, negedge BWEBB[18], tbwbs, tbwbh, valid_bwb18); + $setuphold (posedge CLK &&& WEA, posedge DA[19], tdas, tdah, valid_da19); + $setuphold (posedge CLK &&& WEA, negedge DA[19], tdas, tdah, valid_da19); + $setuphold (posedge CLK &&& WEB, posedge DB[19], tdbs, tdbh, valid_db19); + $setuphold (posedge CLK &&& WEB, negedge DB[19], tdbs, tdbh, valid_db19); + + $setuphold (posedge CLK &&& WEA, posedge BWEBA[19], tbwas, tbwah, valid_bwa19); + $setuphold (posedge CLK &&& WEA, negedge BWEBA[19], tbwas, tbwah, valid_bwa19); + $setuphold (posedge CLK &&& WEB, posedge BWEBB[19], tbwbs, tbwbh, valid_bwb19); + $setuphold (posedge CLK &&& WEB, negedge BWEBB[19], tbwbs, tbwbh, valid_bwb19); + $setuphold (posedge CLK &&& WEA, posedge DA[20], tdas, tdah, valid_da20); + $setuphold (posedge CLK &&& WEA, negedge DA[20], tdas, tdah, valid_da20); + $setuphold (posedge CLK &&& WEB, posedge DB[20], tdbs, tdbh, valid_db20); + $setuphold (posedge CLK &&& WEB, negedge DB[20], tdbs, tdbh, valid_db20); + + $setuphold (posedge CLK &&& WEA, posedge BWEBA[20], tbwas, tbwah, valid_bwa20); + $setuphold (posedge CLK &&& WEA, negedge BWEBA[20], tbwas, tbwah, valid_bwa20); + $setuphold (posedge CLK &&& WEB, posedge BWEBB[20], tbwbs, tbwbh, valid_bwb20); + $setuphold (posedge CLK &&& WEB, negedge BWEBB[20], tbwbs, tbwbh, valid_bwb20); + $setuphold (posedge CLK &&& WEA, posedge DA[21], tdas, tdah, valid_da21); + $setuphold (posedge CLK &&& WEA, negedge DA[21], tdas, tdah, valid_da21); + $setuphold (posedge CLK &&& WEB, posedge DB[21], tdbs, tdbh, valid_db21); + $setuphold (posedge CLK &&& WEB, negedge DB[21], tdbs, tdbh, valid_db21); + + $setuphold (posedge CLK &&& WEA, posedge BWEBA[21], tbwas, tbwah, valid_bwa21); + $setuphold (posedge CLK &&& WEA, negedge BWEBA[21], tbwas, tbwah, valid_bwa21); + $setuphold (posedge CLK &&& WEB, posedge BWEBB[21], tbwbs, tbwbh, valid_bwb21); + $setuphold (posedge CLK &&& WEB, negedge BWEBB[21], tbwbs, tbwbh, valid_bwb21); + $setuphold (posedge CLK &&& WEA, posedge DA[22], tdas, tdah, valid_da22); + $setuphold (posedge CLK &&& WEA, negedge DA[22], tdas, tdah, valid_da22); + $setuphold (posedge CLK &&& WEB, posedge DB[22], tdbs, tdbh, valid_db22); + $setuphold (posedge CLK &&& WEB, negedge DB[22], tdbs, tdbh, valid_db22); + + $setuphold (posedge CLK &&& WEA, posedge BWEBA[22], tbwas, tbwah, valid_bwa22); + $setuphold (posedge CLK &&& WEA, negedge BWEBA[22], tbwas, tbwah, valid_bwa22); + $setuphold (posedge CLK &&& WEB, posedge BWEBB[22], tbwbs, tbwbh, valid_bwb22); + $setuphold (posedge CLK &&& WEB, negedge BWEBB[22], tbwbs, tbwbh, valid_bwb22); + $setuphold (posedge CLK &&& WEA, posedge DA[23], tdas, tdah, valid_da23); + $setuphold (posedge CLK &&& WEA, negedge DA[23], tdas, tdah, valid_da23); + $setuphold (posedge CLK &&& WEB, posedge DB[23], tdbs, tdbh, valid_db23); + $setuphold (posedge CLK &&& WEB, negedge DB[23], tdbs, tdbh, valid_db23); + + $setuphold (posedge CLK &&& WEA, posedge BWEBA[23], tbwas, tbwah, valid_bwa23); + $setuphold (posedge CLK &&& WEA, negedge BWEBA[23], tbwas, tbwah, valid_bwa23); + $setuphold (posedge CLK &&& WEB, posedge BWEBB[23], tbwbs, tbwbh, valid_bwb23); + $setuphold (posedge CLK &&& WEB, negedge BWEBB[23], tbwbs, tbwbh, valid_bwb23); + $setuphold (posedge CLK &&& WEA, posedge DA[24], tdas, tdah, valid_da24); + $setuphold (posedge CLK &&& WEA, negedge DA[24], tdas, tdah, valid_da24); + $setuphold (posedge CLK &&& WEB, posedge DB[24], tdbs, tdbh, valid_db24); + $setuphold (posedge CLK &&& WEB, negedge DB[24], tdbs, tdbh, valid_db24); + + $setuphold (posedge CLK &&& WEA, posedge BWEBA[24], tbwas, tbwah, valid_bwa24); + $setuphold (posedge CLK &&& WEA, negedge BWEBA[24], tbwas, tbwah, valid_bwa24); + $setuphold (posedge CLK &&& WEB, posedge BWEBB[24], tbwbs, tbwbh, valid_bwb24); + $setuphold (posedge CLK &&& WEB, negedge BWEBB[24], tbwbs, tbwbh, valid_bwb24); + $setuphold (posedge CLK &&& WEA, posedge DA[25], tdas, tdah, valid_da25); + $setuphold (posedge CLK &&& WEA, negedge DA[25], tdas, tdah, valid_da25); + $setuphold (posedge CLK &&& WEB, posedge DB[25], tdbs, tdbh, valid_db25); + $setuphold (posedge CLK &&& WEB, negedge DB[25], tdbs, tdbh, valid_db25); + + $setuphold (posedge CLK &&& WEA, posedge BWEBA[25], tbwas, tbwah, valid_bwa25); + $setuphold (posedge CLK &&& WEA, negedge BWEBA[25], tbwas, tbwah, valid_bwa25); + $setuphold (posedge CLK &&& WEB, posedge BWEBB[25], tbwbs, tbwbh, valid_bwb25); + $setuphold (posedge CLK &&& WEB, negedge BWEBB[25], tbwbs, tbwbh, valid_bwb25); + $setuphold (posedge CLK &&& WEA, posedge DA[26], tdas, tdah, valid_da26); + $setuphold (posedge CLK &&& WEA, negedge DA[26], tdas, tdah, valid_da26); + $setuphold (posedge CLK &&& WEB, posedge DB[26], tdbs, tdbh, valid_db26); + $setuphold (posedge CLK &&& WEB, negedge DB[26], tdbs, tdbh, valid_db26); + + $setuphold (posedge CLK &&& WEA, posedge BWEBA[26], tbwas, tbwah, valid_bwa26); + $setuphold (posedge CLK &&& WEA, negedge BWEBA[26], tbwas, tbwah, valid_bwa26); + $setuphold (posedge CLK &&& WEB, posedge BWEBB[26], tbwbs, tbwbh, valid_bwb26); + $setuphold (posedge CLK &&& WEB, negedge BWEBB[26], tbwbs, tbwbh, valid_bwb26); + $setuphold (posedge CLK &&& WEA, posedge DA[27], tdas, tdah, valid_da27); + $setuphold (posedge CLK &&& WEA, negedge DA[27], tdas, tdah, valid_da27); + $setuphold (posedge CLK &&& WEB, posedge DB[27], tdbs, tdbh, valid_db27); + $setuphold (posedge CLK &&& WEB, negedge DB[27], tdbs, tdbh, valid_db27); + + $setuphold (posedge CLK &&& WEA, posedge BWEBA[27], tbwas, tbwah, valid_bwa27); + $setuphold (posedge CLK &&& WEA, negedge BWEBA[27], tbwas, tbwah, valid_bwa27); + $setuphold (posedge CLK &&& WEB, posedge BWEBB[27], tbwbs, tbwbh, valid_bwb27); + $setuphold (posedge CLK &&& WEB, negedge BWEBB[27], tbwbs, tbwbh, valid_bwb27); + $setuphold (posedge CLK &&& WEA, posedge DA[28], tdas, tdah, valid_da28); + $setuphold (posedge CLK &&& WEA, negedge DA[28], tdas, tdah, valid_da28); + $setuphold (posedge CLK &&& WEB, posedge DB[28], tdbs, tdbh, valid_db28); + $setuphold (posedge CLK &&& WEB, negedge DB[28], tdbs, tdbh, valid_db28); + + $setuphold (posedge CLK &&& WEA, posedge BWEBA[28], tbwas, tbwah, valid_bwa28); + $setuphold (posedge CLK &&& WEA, negedge BWEBA[28], tbwas, tbwah, valid_bwa28); + $setuphold (posedge CLK &&& WEB, posedge BWEBB[28], tbwbs, tbwbh, valid_bwb28); + $setuphold (posedge CLK &&& WEB, negedge BWEBB[28], tbwbs, tbwbh, valid_bwb28); + $setuphold (posedge CLK &&& WEA, posedge DA[29], tdas, tdah, valid_da29); + $setuphold (posedge CLK &&& WEA, negedge DA[29], tdas, tdah, valid_da29); + $setuphold (posedge CLK &&& WEB, posedge DB[29], tdbs, tdbh, valid_db29); + $setuphold (posedge CLK &&& WEB, negedge DB[29], tdbs, tdbh, valid_db29); + + $setuphold (posedge CLK &&& WEA, posedge BWEBA[29], tbwas, tbwah, valid_bwa29); + $setuphold (posedge CLK &&& WEA, negedge BWEBA[29], tbwas, tbwah, valid_bwa29); + $setuphold (posedge CLK &&& WEB, posedge BWEBB[29], tbwbs, tbwbh, valid_bwb29); + $setuphold (posedge CLK &&& WEB, negedge BWEBB[29], tbwbs, tbwbh, valid_bwb29); + $setuphold (posedge CLK &&& WEA, posedge DA[30], tdas, tdah, valid_da30); + $setuphold (posedge CLK &&& WEA, negedge DA[30], tdas, tdah, valid_da30); + $setuphold (posedge CLK &&& WEB, posedge DB[30], tdbs, tdbh, valid_db30); + $setuphold (posedge CLK &&& WEB, negedge DB[30], tdbs, tdbh, valid_db30); + + $setuphold (posedge CLK &&& WEA, posedge BWEBA[30], tbwas, tbwah, valid_bwa30); + $setuphold (posedge CLK &&& WEA, negedge BWEBA[30], tbwas, tbwah, valid_bwa30); + $setuphold (posedge CLK &&& WEB, posedge BWEBB[30], tbwbs, tbwbh, valid_bwb30); + $setuphold (posedge CLK &&& WEB, negedge BWEBB[30], tbwbs, tbwbh, valid_bwb30); + $setuphold (posedge CLK &&& WEA, posedge DA[31], tdas, tdah, valid_da31); + $setuphold (posedge CLK &&& WEA, negedge DA[31], tdas, tdah, valid_da31); + $setuphold (posedge CLK &&& WEB, posedge DB[31], tdbs, tdbh, valid_db31); + $setuphold (posedge CLK &&& WEB, negedge DB[31], tdbs, tdbh, valid_db31); + + $setuphold (posedge CLK &&& WEA, posedge BWEBA[31], tbwas, tbwah, valid_bwa31); + $setuphold (posedge CLK &&& WEA, negedge BWEBA[31], tbwas, tbwah, valid_bwa31); + $setuphold (posedge CLK &&& WEB, posedge BWEBB[31], tbwbs, tbwbh, valid_bwb31); + $setuphold (posedge CLK &&& WEB, negedge BWEBB[31], tbwbs, tbwbh, valid_bwb31); + $setuphold (posedge CLK &&& CSA, posedge WEBA, twas, twah, valid_wea); + $setuphold (posedge CLK &&& CSA, negedge WEBA, twas, twah, valid_wea); + $setuphold (posedge CLK &&& CSB, posedge WEBB, twbs, twbh, valid_web); + $setuphold (posedge CLK &&& CSB, negedge WEBB, twbs, twbh, valid_web); + + $setuphold (posedge CLK, posedge CEBA, tcas, tcah, valid_cea); + $setuphold (posedge CLK, negedge CEBA, tcas, tcah, valid_cea); + $setuphold (posedge CLK, posedge CEBB, tcbs, tcbh, valid_ceb); + $setuphold (posedge CLK, negedge CEBB, tcbs, tcbh, valid_ceb); + + $width (negedge CLK &&& check_ceb, tckl, 0, valid_ck); + $width (posedge CLK &&& check_ceb, tckh, 0, valid_ck); + $period (posedge CLK &&& check_ceb, tcyc, valid_ck); + $period (negedge CLK &&& check_ceb, tcyc, valid_ck); + + +if(!CEBA & WEBA) (posedge CLK => (QA[0] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[0] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[1] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[1] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[2] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[2] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[3] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[3] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[4] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[4] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[5] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[5] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[6] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[6] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[7] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[7] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[8] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[8] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[9] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[9] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[10] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[10] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[11] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[11] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[12] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[12] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[13] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[13] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[14] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[14] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[15] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[15] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[16] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[16] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[17] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[17] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[18] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[18] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[19] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[19] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[20] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[20] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[21] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[21] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[22] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[22] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[23] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[23] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[24] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[24] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[25] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[25] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[26] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[26] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[27] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[27] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[28] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[28] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[29] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[29] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[30] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[30] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[31] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[31] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +endspecify +`endif + +initial begin + assign EN = 1; + RDA = 1; + RDB = 1; + ABL = 1'b1; + AAL = {M{1'b0}}; + BWEBAL = {N{1'b1}}; + BWEBBL = {N{1'b1}}; + CEBAL = 1'b1; + CEBBL = 1'b1; + clk_count = 0; + sd_mode = 0; + invalid_aslp = 1'b0; + invalid_bslp = 1'b0; + invalid_adslp = 1'b0; + invalid_bdslp = 1'b0; + invalid_sdwk_dslp = 1'b0; +end + +`ifdef TSMC_INITIALIZE_MEM +initial + begin +`ifdef TSMC_INITIALIZE_FORMAT_BINARY + #(INITIAL_MEM_DELAY) $readmemb(cdeFileInit, MX.mem, 0, W-1); +`else + #(INITIAL_MEM_DELAY) $readmemh(cdeFileInit, MX.mem, 0, W-1); +`endif + end +`endif // `ifdef TSMC_INITIALIZE_MEM + +`ifdef TSMC_INITIALIZE_FAULT +initial + begin +`ifdef TSMC_INITIALIZE_FORMAT_BINARY + #(INITIAL_FAULT_DELAY) $readmemb(cdeFileFault, MX.mem_fault, 0, W-1); +`else + #(INITIAL_FAULT_DELAY) $readmemh(cdeFileFault, MX.mem_fault, 0, W-1); +`endif + end +`endif // `ifdef TSMC_INITIALIZE_FAULT + + +always @(bRTSEL) begin + if (bSLP === 1'b0 && bDSLP === 1'b0 && bSD === 1'b0) begin + if(($realtime > 0) && (!CEBAL || !CEBBL) ) begin +`ifdef no_warning +`else + $display("\tWarning %m : input RTSEL should not be toggled when CEBA/CEBB is low at simulation time %t\n", $realtime); +`endif + `ifdef TSMC_CM_UNIT_DELAY + #(SRAM_DELAY); + `endif + bQA = {N{1'bx}}; + bQB = {N{1'bx}}; + xMemoryAll; + end + end +end +always @(bWTSEL) begin + if (bSLP === 1'b0 && bDSLP === 1'b0 && bSD === 1'b0) begin + if(($realtime > 0) && (!CEBAL || !CEBBL) ) begin +`ifdef no_warning +`else + $display("\tWarning %m : input WTSEL should not be toggled when CEBA/CEBB is low at simulation time %t\n", $realtime); +`endif + `ifdef TSMC_CM_UNIT_DELAY + #(SRAM_DELAY); + `endif + bQA = {N{1'bx}}; + bQB = {N{1'bx}}; + xMemoryAll; + end + end +end +always @(bPTSEL) begin + if (bSLP === 1'b0 && bDSLP === 1'b0 && bSD === 1'b0) begin + if(($realtime > 0) && (!CEBAL || !CEBBL) ) begin +`ifdef no_warning +`else + $display("\tWarning %m : input PTSEL should not be toggled when CEBA/CEBB is low at simulation time %t\n", $realtime); +`endif + `ifdef TSMC_CM_UNIT_DELAY + #(SRAM_DELAY); + `endif + bQA = {N{1'bx}}; + bQB = {N{1'bx}}; + xMemoryAll; + end + end +end + +`ifdef TSMC_NO_TESTPINS_WARNING +`else +always @(bCLKA or bCLKB or bRTSEL) +begin + if(bSLP === 1'b0 && bDSLP === 1'b0 && bSD === 1'b0) begin + if((bRTSEL !== 2'b00) && ($realtime > 0)) + begin + $display("\tError %m : input RTSEL should be set to 2'b00 at simulation time %t\n", $realtime); + $display("\tError %m : Please refer the datasheet for the RTSEL setting in the different segment and mux configuration\n"); + bQA <= #0.01 {N{1'bx}}; + bQB <= #0.01 {N{1'bx}}; + AAL <= {M{1'bx}}; + BWEBAL <= {N{1'b0}}; + end + end +end + +always @(bCLKA or bCLKB or bWTSEL) +begin + if(bSLP === 1'b0 && bDSLP === 1'b0 && bSD === 1'b0) begin + if((bWTSEL !== 2'b00) && ($realtime > 0)) + begin + $display("\tError %m : input WTSEL should be set to 2'b00 at simulation time %t\n", $realtime); + $display("\tError %m : Please refer the datasheet for the WTSEL setting in the different segment and mux configuration\n"); + bQA <= #0.01 {N{1'bx}}; + bQB <= #0.01 {N{1'bx}}; + AAL <= {M{1'bx}}; + BWEBAL <= {N{1'b0}}; + end + end +end + +always @(bCLKA or bCLKB or bPTSEL) +begin + if(bSLP === 1'b0 && bDSLP === 1'b0 && bSD === 1'b0) begin + if((bPTSEL !== 2'b00) && ($realtime > 0)) + begin + $display("\tError %m : input PTSEL should be set to 2'b00 at simulation time %t\n", $realtime); + $display("\tError %m : Please refer the datasheet for the PTSEL setting in the different segment and mux configuration\n"); + bQA <= #0.01 {N{1'bx}}; + bQB <= #0.01 {N{1'bx}}; + AAL <= {M{1'bx}}; + BWEBAL <= {N{1'b0}}; + end + end +end + +`endif + +//always @(bTMA or bTMB) begin +// if(bSLP === 1'b0 && bDSLP === 1'b0 && bSD === 1'b0 && bTMA === 1'b1 && bTMB === 1'b1) begin +// if( MES_ALL=="ON" && $realtime != 0) +// begin +// $display("\nWarning %m : TMA and TMB cannot both be 1 at the same time, at %t. >>", $realtime); +// end +// xMemoryAll; +//`ifdef TSMC_CM_UNIT_DELAY +// bQA <= #(SRAM_DELAY + 0.001) {N{1'bx}}; +// bQB <= #(SRAM_DELAY + 0.001) {N{1'bx}}; +//`else +// bQA <= #0.01 {N{1'bx}}; +// bQB <= #0.01 {N{1'bx}}; +//`endif +// end +//end + +always @(bCLKA) +begin : CLKAOP + if(bSLP === 1'b0 && bDSLP === 1'b0 && bSD === 1'b0 && invalid_sdwk_dslp === 1'b0) begin + if(bCLKA === 1'bx) + begin + if( MES_ALL=="ON" && $realtime != 0) + begin + $display("\nWarning %m : CLK unknown at %t. >>", $realtime); + end + xMemoryAll; + bQA <= #0.01 {N{1'bx}}; + end + else if(bCLKA === 1'b1 && RCLKA === 1'b0) + begin + if(bCEBA === 1'bx) + begin + if( MES_ALL=="ON" && $realtime != 0) + begin + $display("\nWarning %m CEBA unknown at %t. >>", $realtime); + end + xMemoryAll; + bQA <= #0.01 {N{1'bx}}; + end + else if(bWEBA === 1'bx && bCEBA === 1'b0) + begin + if( MES_ALL=="ON" && $realtime != 0) + begin + $display("\nWarning %m WEBA unknown at %t. >>", $realtime); + end + xMemoryAll; + bQA <= #0.01 {N{1'bx}}; + end + else begin + WEBAL = bWEBA; + CEBAL = bCEBA; + if(^bAA === 1'bx && bWEBA === 1'b0 && bCEBA === 1'b0) + begin + if( MES_ALL=="ON" && $realtime != 0) + begin + $display("\nWarning %m WRITE AA unknown at %t. >>", $realtime); + end + xMemoryAll; + end + else if(^bAA === 1'bx && bWEBA === 1'b1 && bCEBA === 1'b0) + begin + if( MES_ALL=="ON" && $realtime != 0) + begin + $display("\nWarning %m READ AA unknown at %t. >>", $realtime); + end + xMemoryAll; + bQA <= #0.01 {N{1'bx}}; + end + else + begin + if(!bCEBA) + begin // begin if(bCEBA) + AAL = bAA; + DAL = bDA; + if(bWEBA === 1'b1 && clk_count == 0) + begin + RDA = ~RDA; + end + if(bWEBA === 1'b0) + begin + for (i = 0; i < N; i = i + 1) + begin + if(!bBWEBA[i] && !bWEBA) + begin + BWEBAL[i] = 1'b0; + end + if(bWEBA === 1'bx || bBWEBA[i] === 1'bx) + begin + BWEBAL[i] = 1'b0; + DAL[i] = 1'bx; + end + end + if(^bBWEBA === 1'bx) + begin + if( MES_ALL=="ON" && $realtime != 0) + begin + $display("\nWarning %m BWEBA unknown at %t. >>", $realtime); + end + end + end + end + end + end + + CEBBL = bCEBB; + if(bCEBB === 1'b0) begin + WEBBL = bWEBB; + ABL = bAB; + bBWEBBL = bBWEBB; + bDBL = bDB; + end + #0.001; + + if(CEBBL === 1'bx) + begin + if( MES_ALL=="ON" && $realtime != 0) + begin + $display("\nWarning %m CEBB unknown at %t. >>", $realtime); + end + xMemoryAll; + bQB <= #0.01 {N{1'bx}}; + end + else if(WEBBL === 1'bx && CEBBL === 1'b0) + begin + if( MES_ALL=="ON" && $realtime != 0) + begin + $display("\nWarning %m WEBB unknown at %t. >>", $realtime); + end + xMemoryAll; + bQB <= #0.01 {N{1'bx}}; + end + else + begin + if(^ABL === 1'bx && WEBBL === 1'b0 && CEBBL === 1'b0) + begin + if( MES_ALL=="ON" && $realtime != 0) + begin + $display("\nWarning %m WRITE AB unknown at %t. >>", $realtime); + end + xMemoryAll; + end + else if(^ABL === 1'bx && WEBBL === 1'b1 && CEBBL === 1'b0) + begin + if( MES_ALL=="ON" && $realtime != 0) + begin + $display("\nWarning %m READ AB unknown at %t. >>", $realtime); + end + xMemoryAll; + bQB <= #0.01 {N{1'bx}}; + end + else begin + if(!CEBBL) + begin // begin if(CEBBL) + DBL = bDBL; + if(WEBBL === 1'b1 && clk_count == 0) + begin + RDB = ~RDB; + end + if(WEBBL !== 1'b1) + begin + for (i = 0; i < N; i = i + 1) + begin + if(!bBWEBBL[i] && !WEBBL) + begin + BWEBBL[i] = 1'b0; + end + if(WEBBL === 1'bx || bBWEBBL[i] === 1'bx) + begin + BWEBBL[i] = 1'b0; + DBL[i] = 1'bx; + end + end + if(^bBWEBBL === 1'bx) + begin + if( MES_ALL=="ON" && $realtime != 0) + begin + $display("\nWarning %m BWEBB unknown at %t. >>", $realtime); + end + end + end + end + end + end + end + end + #0.001 RCLKA = bCLKA; + +end + + + +always @(RDA or QAL) +begin : CLKAROP + if(bSLP === 1'b0 && bDSLP === 1'b0 && bSD === 1'b0 && invalid_sdwk_dslp === 1'b0 && bAWT === 1'b0) begin + if(!CEBAL && WEBAL && clk_count == 0) + begin + begin +`ifdef TSMC_CM_UNIT_DELAY + #(SRAM_DELAY); +`else + bQA = {N{1'bx}}; + #0.01; +`endif + bQA <= QAL; + end + end // if(!CEBAL && WEBAL && clk_count == 0) + end +end // always @ (RDA or QAL) + +always @(RDB or QBL) +begin : CLKBROP + if(bSLP === 1'b0 && bDSLP === 1'b0 && bSD === 1'b0 && invalid_sdwk_dslp === 1'b0 && bAWT === 1'b0) begin + if(!CEBBL && WEBBL && clk_count == 0) + begin + begin +`ifdef TSMC_CM_UNIT_DELAY + #(SRAM_DELAY); +`else + bQB = {N{1'bx}}; + #0.01; +`endif + bQB <= QBL; + end + end // if(!bAWT && !CEBBL && WEBBL && clk_count == 0) + end +end // always @ (RDB or QBL) + + + + + +always @(BWEBAL) +begin + BWEBAL = #0.01 {N{1'b1}}; +end + +always @(BWEBBL) +begin + BWEBBL = #0.01 {N{1'b1}}; +end + + +`ifdef TSMC_CM_UNIT_DELAY +`else +always @(valid_testpin) begin + AAL <= {M{1'bx}}; + BWEBAL <= {N{1'b0}}; + BWEBBL <= {N{1'b0}}; + bQA = #0.01 {N{1'bx}}; + bQB = #0.01 {N{1'bx}}; +end + + +always @(valid_ck) +begin + if (iCEBA === 1'b0) begin + #0.002; + AAL = {M{1'bx}}; + BWEBAL = {N{1'b0}}; + bQA = #0.01 {N{1'bx}}; + end + + if (iCEBB === 1'b0) begin + #0.002; + ABL = {M{1'bx}}; + BWEBBL = {N{1'b0}}; + bQB = #0.01 {N{1'bx}}; + end +end + + +always @(valid_cka) +begin + + #0.002; + AAL = {M{1'bx}}; + BWEBAL = {N{1'b0}}; + bQA = #0.01 {N{1'bx}}; +end + +always @(valid_ckb) +begin + + #0.002; + ABL = {M{1'bx}}; + BWEBBL = {N{1'b0}}; + bQB = #0.01 {N{1'bx}}; +end + + +always @(valid_aa) +begin + + if(!WEBAL) + begin + #0.002; + BWEBAL = {N{1'b0}}; + AAL = {M{1'bx}}; + end + else + begin + #0.002; + BWEBAL = {N{1'b0}}; + AAL = {M{1'bx}}; + bQA = #0.01 {N{1'bx}}; + end +end + +always @(valid_ab) +begin + + if(!WEBBL) + begin + BWEBBL = {N{1'b0}}; + ABL = {M{1'bx}}; + end + else + begin + #0.002; + BWEBBL = {N{1'b0}}; + ABL = {M{1'bx}}; + bQB = #0.01 {N{1'bx}}; + end +end + +always @(valid_da0) +begin + + DAL[0] = 1'bx; + BWEBAL[0] = 1'b0; +end + +always @(valid_db0) +begin + disable CLKAOP; + DBL[0] = 1'bx; + BWEBBL[0] = 1'b0; +end + +always @(valid_bwa0) +begin + + DAL[0] = 1'bx; + BWEBAL[0] = 1'b0; +end + +always @(valid_bwb0) +begin + disable CLKAOP; + DBL[0] = 1'bx; + BWEBBL[0] = 1'b0; +end +always @(valid_da1) +begin + + DAL[1] = 1'bx; + BWEBAL[1] = 1'b0; +end + +always @(valid_db1) +begin + disable CLKAOP; + DBL[1] = 1'bx; + BWEBBL[1] = 1'b0; +end + +always @(valid_bwa1) +begin + + DAL[1] = 1'bx; + BWEBAL[1] = 1'b0; +end + +always @(valid_bwb1) +begin + disable CLKAOP; + DBL[1] = 1'bx; + BWEBBL[1] = 1'b0; +end +always @(valid_da2) +begin + + DAL[2] = 1'bx; + BWEBAL[2] = 1'b0; +end + +always @(valid_db2) +begin + disable CLKAOP; + DBL[2] = 1'bx; + BWEBBL[2] = 1'b0; +end + +always @(valid_bwa2) +begin + + DAL[2] = 1'bx; + BWEBAL[2] = 1'b0; +end + +always @(valid_bwb2) +begin + disable CLKAOP; + DBL[2] = 1'bx; + BWEBBL[2] = 1'b0; +end +always @(valid_da3) +begin + + DAL[3] = 1'bx; + BWEBAL[3] = 1'b0; +end + +always @(valid_db3) +begin + disable CLKAOP; + DBL[3] = 1'bx; + BWEBBL[3] = 1'b0; +end + +always @(valid_bwa3) +begin + + DAL[3] = 1'bx; + BWEBAL[3] = 1'b0; +end + +always @(valid_bwb3) +begin + disable CLKAOP; + DBL[3] = 1'bx; + BWEBBL[3] = 1'b0; +end +always @(valid_da4) +begin + + DAL[4] = 1'bx; + BWEBAL[4] = 1'b0; +end + +always @(valid_db4) +begin + disable CLKAOP; + DBL[4] = 1'bx; + BWEBBL[4] = 1'b0; +end + +always @(valid_bwa4) +begin + + DAL[4] = 1'bx; + BWEBAL[4] = 1'b0; +end + +always @(valid_bwb4) +begin + disable CLKAOP; + DBL[4] = 1'bx; + BWEBBL[4] = 1'b0; +end +always @(valid_da5) +begin + + DAL[5] = 1'bx; + BWEBAL[5] = 1'b0; +end + +always @(valid_db5) +begin + disable CLKAOP; + DBL[5] = 1'bx; + BWEBBL[5] = 1'b0; +end + +always @(valid_bwa5) +begin + + DAL[5] = 1'bx; + BWEBAL[5] = 1'b0; +end + +always @(valid_bwb5) +begin + disable CLKAOP; + DBL[5] = 1'bx; + BWEBBL[5] = 1'b0; +end +always @(valid_da6) +begin + + DAL[6] = 1'bx; + BWEBAL[6] = 1'b0; +end + +always @(valid_db6) +begin + disable CLKAOP; + DBL[6] = 1'bx; + BWEBBL[6] = 1'b0; +end + +always @(valid_bwa6) +begin + + DAL[6] = 1'bx; + BWEBAL[6] = 1'b0; +end + +always @(valid_bwb6) +begin + disable CLKAOP; + DBL[6] = 1'bx; + BWEBBL[6] = 1'b0; +end +always @(valid_da7) +begin + + DAL[7] = 1'bx; + BWEBAL[7] = 1'b0; +end + +always @(valid_db7) +begin + disable CLKAOP; + DBL[7] = 1'bx; + BWEBBL[7] = 1'b0; +end + +always @(valid_bwa7) +begin + + DAL[7] = 1'bx; + BWEBAL[7] = 1'b0; +end + +always @(valid_bwb7) +begin + disable CLKAOP; + DBL[7] = 1'bx; + BWEBBL[7] = 1'b0; +end +always @(valid_da8) +begin + + DAL[8] = 1'bx; + BWEBAL[8] = 1'b0; +end + +always @(valid_db8) +begin + disable CLKAOP; + DBL[8] = 1'bx; + BWEBBL[8] = 1'b0; +end + +always @(valid_bwa8) +begin + + DAL[8] = 1'bx; + BWEBAL[8] = 1'b0; +end + +always @(valid_bwb8) +begin + disable CLKAOP; + DBL[8] = 1'bx; + BWEBBL[8] = 1'b0; +end +always @(valid_da9) +begin + + DAL[9] = 1'bx; + BWEBAL[9] = 1'b0; +end + +always @(valid_db9) +begin + disable CLKAOP; + DBL[9] = 1'bx; + BWEBBL[9] = 1'b0; +end + +always @(valid_bwa9) +begin + + DAL[9] = 1'bx; + BWEBAL[9] = 1'b0; +end + +always @(valid_bwb9) +begin + disable CLKAOP; + DBL[9] = 1'bx; + BWEBBL[9] = 1'b0; +end +always @(valid_da10) +begin + + DAL[10] = 1'bx; + BWEBAL[10] = 1'b0; +end + +always @(valid_db10) +begin + disable CLKAOP; + DBL[10] = 1'bx; + BWEBBL[10] = 1'b0; +end + +always @(valid_bwa10) +begin + + DAL[10] = 1'bx; + BWEBAL[10] = 1'b0; +end + +always @(valid_bwb10) +begin + disable CLKAOP; + DBL[10] = 1'bx; + BWEBBL[10] = 1'b0; +end +always @(valid_da11) +begin + + DAL[11] = 1'bx; + BWEBAL[11] = 1'b0; +end + +always @(valid_db11) +begin + disable CLKAOP; + DBL[11] = 1'bx; + BWEBBL[11] = 1'b0; +end + +always @(valid_bwa11) +begin + + DAL[11] = 1'bx; + BWEBAL[11] = 1'b0; +end + +always @(valid_bwb11) +begin + disable CLKAOP; + DBL[11] = 1'bx; + BWEBBL[11] = 1'b0; +end +always @(valid_da12) +begin + + DAL[12] = 1'bx; + BWEBAL[12] = 1'b0; +end + +always @(valid_db12) +begin + disable CLKAOP; + DBL[12] = 1'bx; + BWEBBL[12] = 1'b0; +end + +always @(valid_bwa12) +begin + + DAL[12] = 1'bx; + BWEBAL[12] = 1'b0; +end + +always @(valid_bwb12) +begin + disable CLKAOP; + DBL[12] = 1'bx; + BWEBBL[12] = 1'b0; +end +always @(valid_da13) +begin + + DAL[13] = 1'bx; + BWEBAL[13] = 1'b0; +end + +always @(valid_db13) +begin + disable CLKAOP; + DBL[13] = 1'bx; + BWEBBL[13] = 1'b0; +end + +always @(valid_bwa13) +begin + + DAL[13] = 1'bx; + BWEBAL[13] = 1'b0; +end + +always @(valid_bwb13) +begin + disable CLKAOP; + DBL[13] = 1'bx; + BWEBBL[13] = 1'b0; +end +always @(valid_da14) +begin + + DAL[14] = 1'bx; + BWEBAL[14] = 1'b0; +end + +always @(valid_db14) +begin + disable CLKAOP; + DBL[14] = 1'bx; + BWEBBL[14] = 1'b0; +end + +always @(valid_bwa14) +begin + + DAL[14] = 1'bx; + BWEBAL[14] = 1'b0; +end + +always @(valid_bwb14) +begin + disable CLKAOP; + DBL[14] = 1'bx; + BWEBBL[14] = 1'b0; +end +always @(valid_da15) +begin + + DAL[15] = 1'bx; + BWEBAL[15] = 1'b0; +end + +always @(valid_db15) +begin + disable CLKAOP; + DBL[15] = 1'bx; + BWEBBL[15] = 1'b0; +end + +always @(valid_bwa15) +begin + + DAL[15] = 1'bx; + BWEBAL[15] = 1'b0; +end + +always @(valid_bwb15) +begin + disable CLKAOP; + DBL[15] = 1'bx; + BWEBBL[15] = 1'b0; +end +always @(valid_da16) +begin + + DAL[16] = 1'bx; + BWEBAL[16] = 1'b0; +end + +always @(valid_db16) +begin + disable CLKAOP; + DBL[16] = 1'bx; + BWEBBL[16] = 1'b0; +end + +always @(valid_bwa16) +begin + + DAL[16] = 1'bx; + BWEBAL[16] = 1'b0; +end + +always @(valid_bwb16) +begin + disable CLKAOP; + DBL[16] = 1'bx; + BWEBBL[16] = 1'b0; +end +always @(valid_da17) +begin + + DAL[17] = 1'bx; + BWEBAL[17] = 1'b0; +end + +always @(valid_db17) +begin + disable CLKAOP; + DBL[17] = 1'bx; + BWEBBL[17] = 1'b0; +end + +always @(valid_bwa17) +begin + + DAL[17] = 1'bx; + BWEBAL[17] = 1'b0; +end + +always @(valid_bwb17) +begin + disable CLKAOP; + DBL[17] = 1'bx; + BWEBBL[17] = 1'b0; +end +always @(valid_da18) +begin + + DAL[18] = 1'bx; + BWEBAL[18] = 1'b0; +end + +always @(valid_db18) +begin + disable CLKAOP; + DBL[18] = 1'bx; + BWEBBL[18] = 1'b0; +end + +always @(valid_bwa18) +begin + + DAL[18] = 1'bx; + BWEBAL[18] = 1'b0; +end + +always @(valid_bwb18) +begin + disable CLKAOP; + DBL[18] = 1'bx; + BWEBBL[18] = 1'b0; +end +always @(valid_da19) +begin + + DAL[19] = 1'bx; + BWEBAL[19] = 1'b0; +end + +always @(valid_db19) +begin + disable CLKAOP; + DBL[19] = 1'bx; + BWEBBL[19] = 1'b0; +end + +always @(valid_bwa19) +begin + + DAL[19] = 1'bx; + BWEBAL[19] = 1'b0; +end + +always @(valid_bwb19) +begin + disable CLKAOP; + DBL[19] = 1'bx; + BWEBBL[19] = 1'b0; +end +always @(valid_da20) +begin + + DAL[20] = 1'bx; + BWEBAL[20] = 1'b0; +end + +always @(valid_db20) +begin + disable CLKAOP; + DBL[20] = 1'bx; + BWEBBL[20] = 1'b0; +end + +always @(valid_bwa20) +begin + + DAL[20] = 1'bx; + BWEBAL[20] = 1'b0; +end + +always @(valid_bwb20) +begin + disable CLKAOP; + DBL[20] = 1'bx; + BWEBBL[20] = 1'b0; +end +always @(valid_da21) +begin + + DAL[21] = 1'bx; + BWEBAL[21] = 1'b0; +end + +always @(valid_db21) +begin + disable CLKAOP; + DBL[21] = 1'bx; + BWEBBL[21] = 1'b0; +end + +always @(valid_bwa21) +begin + + DAL[21] = 1'bx; + BWEBAL[21] = 1'b0; +end + +always @(valid_bwb21) +begin + disable CLKAOP; + DBL[21] = 1'bx; + BWEBBL[21] = 1'b0; +end +always @(valid_da22) +begin + + DAL[22] = 1'bx; + BWEBAL[22] = 1'b0; +end + +always @(valid_db22) +begin + disable CLKAOP; + DBL[22] = 1'bx; + BWEBBL[22] = 1'b0; +end + +always @(valid_bwa22) +begin + + DAL[22] = 1'bx; + BWEBAL[22] = 1'b0; +end + +always @(valid_bwb22) +begin + disable CLKAOP; + DBL[22] = 1'bx; + BWEBBL[22] = 1'b0; +end +always @(valid_da23) +begin + + DAL[23] = 1'bx; + BWEBAL[23] = 1'b0; +end + +always @(valid_db23) +begin + disable CLKAOP; + DBL[23] = 1'bx; + BWEBBL[23] = 1'b0; +end + +always @(valid_bwa23) +begin + + DAL[23] = 1'bx; + BWEBAL[23] = 1'b0; +end + +always @(valid_bwb23) +begin + disable CLKAOP; + DBL[23] = 1'bx; + BWEBBL[23] = 1'b0; +end +always @(valid_da24) +begin + + DAL[24] = 1'bx; + BWEBAL[24] = 1'b0; +end + +always @(valid_db24) +begin + disable CLKAOP; + DBL[24] = 1'bx; + BWEBBL[24] = 1'b0; +end + +always @(valid_bwa24) +begin + + DAL[24] = 1'bx; + BWEBAL[24] = 1'b0; +end + +always @(valid_bwb24) +begin + disable CLKAOP; + DBL[24] = 1'bx; + BWEBBL[24] = 1'b0; +end +always @(valid_da25) +begin + + DAL[25] = 1'bx; + BWEBAL[25] = 1'b0; +end + +always @(valid_db25) +begin + disable CLKAOP; + DBL[25] = 1'bx; + BWEBBL[25] = 1'b0; +end + +always @(valid_bwa25) +begin + + DAL[25] = 1'bx; + BWEBAL[25] = 1'b0; +end + +always @(valid_bwb25) +begin + disable CLKAOP; + DBL[25] = 1'bx; + BWEBBL[25] = 1'b0; +end +always @(valid_da26) +begin + + DAL[26] = 1'bx; + BWEBAL[26] = 1'b0; +end + +always @(valid_db26) +begin + disable CLKAOP; + DBL[26] = 1'bx; + BWEBBL[26] = 1'b0; +end + +always @(valid_bwa26) +begin + + DAL[26] = 1'bx; + BWEBAL[26] = 1'b0; +end + +always @(valid_bwb26) +begin + disable CLKAOP; + DBL[26] = 1'bx; + BWEBBL[26] = 1'b0; +end +always @(valid_da27) +begin + + DAL[27] = 1'bx; + BWEBAL[27] = 1'b0; +end + +always @(valid_db27) +begin + disable CLKAOP; + DBL[27] = 1'bx; + BWEBBL[27] = 1'b0; +end + +always @(valid_bwa27) +begin + + DAL[27] = 1'bx; + BWEBAL[27] = 1'b0; +end + +always @(valid_bwb27) +begin + disable CLKAOP; + DBL[27] = 1'bx; + BWEBBL[27] = 1'b0; +end +always @(valid_da28) +begin + + DAL[28] = 1'bx; + BWEBAL[28] = 1'b0; +end + +always @(valid_db28) +begin + disable CLKAOP; + DBL[28] = 1'bx; + BWEBBL[28] = 1'b0; +end + +always @(valid_bwa28) +begin + + DAL[28] = 1'bx; + BWEBAL[28] = 1'b0; +end + +always @(valid_bwb28) +begin + disable CLKAOP; + DBL[28] = 1'bx; + BWEBBL[28] = 1'b0; +end +always @(valid_da29) +begin + + DAL[29] = 1'bx; + BWEBAL[29] = 1'b0; +end + +always @(valid_db29) +begin + disable CLKAOP; + DBL[29] = 1'bx; + BWEBBL[29] = 1'b0; +end + +always @(valid_bwa29) +begin + + DAL[29] = 1'bx; + BWEBAL[29] = 1'b0; +end + +always @(valid_bwb29) +begin + disable CLKAOP; + DBL[29] = 1'bx; + BWEBBL[29] = 1'b0; +end +always @(valid_da30) +begin + + DAL[30] = 1'bx; + BWEBAL[30] = 1'b0; +end + +always @(valid_db30) +begin + disable CLKAOP; + DBL[30] = 1'bx; + BWEBBL[30] = 1'b0; +end + +always @(valid_bwa30) +begin + + DAL[30] = 1'bx; + BWEBAL[30] = 1'b0; +end + +always @(valid_bwb30) +begin + disable CLKAOP; + DBL[30] = 1'bx; + BWEBBL[30] = 1'b0; +end +always @(valid_da31) +begin + + DAL[31] = 1'bx; + BWEBAL[31] = 1'b0; +end + +always @(valid_db31) +begin + disable CLKAOP; + DBL[31] = 1'bx; + BWEBBL[31] = 1'b0; +end + +always @(valid_bwa31) +begin + + DAL[31] = 1'bx; + BWEBAL[31] = 1'b0; +end + +always @(valid_bwb31) +begin + disable CLKAOP; + DBL[31] = 1'bx; + BWEBBL[31] = 1'b0; +end + +always @(valid_cea) +begin + + #0.002; + BWEBAL = {N{1'b0}}; + AAL = {M{1'bx}}; + bQA = #0.01 {N{1'bx}}; +end + +always @(valid_ceb) +begin + + #0.002; + BWEBBL = {N{1'b0}}; + ABL = {M{1'bx}}; + bQB = #0.01 {N{1'bx}}; +end + +always @(valid_wea) +begin + #0.002; + BWEBAL = {N{1'b0}}; + AAL = {M{1'bx}}; + bQA = #0.01 {N{1'bx}}; +end + +always @(valid_web) +begin + #0.002; + BWEBBL = {N{1'b0}}; + ABL = {M{1'bx}}; + bQB = #0.01 {N{1'bx}}; +end + +`endif + +// Task for printing the memory between specified addresses.. +task printMemoryFromTo; + input [M - 1:0] from; // memory content are printed, start from this address. + input [M - 1:0] to; // memory content are printed, end at this address. + begin + MX.printMemoryFromTo(from, to); + end +endtask + +// Task for printing entire memory, including normal array and redundancy array. +task printMemory; + begin + MX.printMemory; + end +endtask + +task xMemoryAll; + begin + MX.xMemoryAll; + end +endtask + +task zeroMemoryAll; + begin + MX.zeroMemoryAll; + end +endtask + +// Task for Loading a perdefined set of data from an external file. +task preloadData; + input [256*8:1] infile; // Max 256 character File Name + begin + MX.preloadData(infile); + end +endtask + +tsdn28hpcpuhdb4096x32m4mw_170a_Int_Array #(2,2,W,N,M,MES_ALL) MX (.D({DAL,DBL}),.BW({BWEBAL,BWEBBL}), + .AW({AAL,ABL}),.EN(EN),.AAR(AAL),.ABR(ABL),.RDA(RDA),.RDB(RDB),.QA(QAL),.QB(QBL)); + +endmodule + + `disable_portfaults + `nosuppress_faults + `endcelldefine + + /* + The module ports are parameterizable vectors. + */ + module tsdn28hpcpuhdb4096x32m4mw_170a_Int_Array (D, BW, AW, EN, AAR, ABR, RDA, RDB, QA, QB); + parameter Nread = 2; // Number of Read Ports + parameter Nwrite = 2; // Number of Write Ports + parameter Nword = 2; // Number of Words + parameter Ndata = 1; // Number of Data Bits / Word + parameter Naddr = 1; // Number of Address Bits / Word + parameter MES_ALL = "ON"; + parameter dly = 0.000; + // Cannot define inputs/outputs as memories + input [Ndata*Nwrite-1:0] D; // Data Word(s) + input [Ndata*Nwrite-1:0] BW; // Negative Bit Write Enable + input [Naddr*Nwrite-1:0] AW; // Write Address(es) + input EN; // Positive Write Enable + input RDA; // Positive Write Enable + input RDB; // Positive Write Enable + input [Naddr-1:0] AAR; // Read Address(es) + input [Naddr-1:0] ABR; // Read Address(es) + output [Ndata-1:0] QA; // Output Data Word(s) + output [Ndata-1:0] QB; // Output Data Word(s) + reg [Ndata-1:0] QA; + reg [Ndata-1:0] QB; + reg [Ndata-1:0] mem [Nword-1:0]; + reg [Ndata-1:0] mem_fault [Nword-1:0]; + reg chgmem; // Toggled when write to mem + reg [Nwrite-1:0] wwe; // Positive Word Write Enable for each Port + reg we; // Positive Write Enable for all Ports + integer waddr[Nwrite-1:0]; // Write Address for each Enabled Port + integer address; // Current address + reg [Naddr-1:0] abuf; // Address of current port + reg [Ndata-1:0] dbuf; // Data for current port + reg [Naddr-1:0] abuf_ra; // Address of current port + reg [Ndata-1:0] dbuf_ra; // Data for current port + reg [Naddr-1:0] abuf_rb; // Address of current port + reg [Ndata-1:0] dbuf_rb; // Data for current port + reg [Ndata-1:0] bwbuf; // Bit Write enable for current port + reg dup; // Is the address a duplicate? + integer log; // Log file descriptor + integer ip, ip2, ib, iba_r, ibb_r, iw, iwb, i; // Vector indices + + + initial + begin + if(log[0] === 1'bx) + log = 1; + chgmem = 1'b0; + end + + + always @(D or BW or AW or EN) + begin: WRITE //{ + if(EN !== 1'b0) + begin //{ Possible write + we = 1'b0; + // Mark any write enabled ports & get write addresses + for (ip = 0 ; ip < Nwrite ; ip = ip + 1) + begin //{ + ib = ip * Ndata; + iw = ib + Ndata; + while (ib < iw && BW[ib] === 1'b1) + begin + ib = ib + 1; + end + if(ib == iw) + begin + wwe[ip] = 1'b0; + end + else + begin //{ ip write enabled + iw = ip * Naddr; + for (ib = 0 ; ib < Naddr ; ib = ib + 1) + begin //{ + abuf[ib] = AW[iw+ib]; + if(abuf[ib] !== 1'b0 && abuf[ib] !== 1'b1) + begin + ib = Naddr; + end + end //} + if(ib == Naddr) + begin //{ + if(abuf < Nword) + begin //{ Valid address + waddr[ip] = abuf; + wwe[ip] = 1'b1; + if(we == 1'b0) + begin + chgmem = ~chgmem; + we = EN; + end + end //} + else + begin //{ Out of range address + wwe[ip] = 1'b0; + if( MES_ALL=="ON" && $realtime != 0) + $fdisplay (log, + "\nWarning! Int_Array instance, %m:", + "\n\t Port %0d", ip, + " write address x'%0h'", abuf, + " out of range at time %t.", $realtime, + "\n\t Port %0d data not written to memory.", ip); + end //} + end //} + else + begin //{ unknown write address + for (ib = 0 ; ib < Ndata ; ib = ib + 1) + begin + dbuf[ib] = 1'bx; + end + for (iw = 0 ; iw < Nword ; iw = iw + 1) + begin + mem[iw] = dbuf; + end + chgmem = ~chgmem; + disable WRITE; + end //} + end //} ip write enabled + end //} for ip + if(we === 1'b1) + begin //{ active write enable + for (ip = 0 ; ip < Nwrite ; ip = ip + 1) + begin //{ + if(wwe[ip]) + begin //{ write enabled bits of write port ip + address = waddr[ip]; + dbuf = mem[address]; + iw = ip * Ndata; + for (ib = 0 ; ib < Ndata ; ib = ib + 1) + begin //{ + iwb = iw + ib; + if(BW[iwb] === 1'b0) + begin + dbuf[ib] = D[iwb]; + end + else + if(BW[iwb] !== 1'b1) + begin + dbuf[ib] = 1'bx; + end + end //} + // Check other ports for same address & + // common write enable bits active + dup = 0; + for (ip2 = ip + 1 ; ip2 < Nwrite ; ip2 = ip2 + 1) + begin //{ + if(wwe[ip2] && address == waddr[ip2]) + begin //{ + // initialize bwbuf if first dup + if(!dup) + begin + for (ib = 0 ; ib < Ndata ; ib = ib + 1) + begin + bwbuf[ib] = BW[iw+ib]; + end + dup = 1; + end + iw = ip2 * Ndata; + for (ib = 0 ; ib < Ndata ; ib = ib + 1) + begin //{ + iwb = iw + ib; + // New: Always set X if BW X + if(BW[iwb] === 1'b0) + begin //{ + if(bwbuf[ib] !== 1'b1) + begin + if(D[iwb] !== dbuf[ib]) + begin + dbuf[ib] = 1'bx; + end + end + else + begin + dbuf[ib] = D[iwb]; + bwbuf[ib] = 1'b0; + end + end //} + else if(BW[iwb] !== 1'b1) + begin + dbuf[ib] = 1'bx; + bwbuf[ib] = 1'bx; + end + end //} for each bit + wwe[ip2] = 1'b0; + end //} Port ip2 address matches port ip + end //} for each port beyond ip (ip2=ip+1) + // Write dbuf to memory + mem[address] = dbuf; + end //} wwe[ip] - write port ip enabled + end //} for each write port ip + end //} active write enable + else if(we !== 1'b0) + begin //{ unknown write enable + for (ip = 0 ; ip < Nwrite ; ip = ip + 1) + begin //{ + if(wwe[ip]) + begin //{ write X to enabled bits of write port ip + address = waddr[ip]; + dbuf = mem[address]; + iw = ip * Ndata; + for (ib = 0 ; ib < Ndata ; ib = ib + 1) + begin //{ + if(BW[iw+ib] !== 1'b1) + begin + dbuf[ib] = 1'bx; + end + end //} + mem[address] = dbuf; + if( MES_ALL=="ON" && $realtime != 0) + $fdisplay (log, + "\nWarning! Int_Array instance, %m:", + "\n\t Enable pin unknown at time %t.", $realtime, + "\n\t Enabled bits at port %0d", ip, + " write address x'%0h' set unknown.", address); + end //} wwe[ip] - write port ip enabled + end //} for each write port ip + end //} unknown write enable + end //} possible write (EN != 0) + end //} always @(D or BW or AW or EN) + + + // Read memory + always @(AAR or RDA) + begin //{ + for (iba_r = 0 ; iba_r < Naddr ; iba_r = iba_r + 1) + begin + abuf_ra[iba_r] = AAR[iba_r]; + if(abuf_ra[iba_r] !== 0 && abuf_ra[iba_r] !== 1) + begin + iba_r = Naddr; + end + end + if(iba_r == Naddr && abuf_ra < Nword) + begin //{ Read valid address + `ifdef TSMC_INITIALIZE_FAULT + dbuf_ra = mem[abuf_ra] ^ mem_fault[abuf_ra]; + `else + dbuf_ra = mem[abuf_ra]; + `endif + for (iba_r = 0 ; iba_r < Ndata ; iba_r = iba_r + 1) + begin + if(QA[iba_r] == dbuf_ra[iba_r]) + begin + QA[iba_r] <= #(dly) dbuf_ra[iba_r]; + end + else + begin + QA[iba_r] <= #(dly) dbuf_ra[iba_r]; + end // else + end // for + end //} valid address + else + begin //{ Invalid address + if(iba_r <= Naddr) begin + if( MES_ALL=="ON" && $realtime != 0) + $fwrite (log, "\nWarning! Int_Array instance, %m:", + "\n\t Port A read address"); + if( MES_ALL=="ON" && $realtime != 0) + $fwrite (log, " x'%0h' out of range", abuf_ra); + if( MES_ALL=="ON" && $realtime != 0) + $fdisplay (log, + " at time %t.", $realtime, + "\n\t Port A outputs set to unknown."); + end + + for (iba_r = 0 ; iba_r < Ndata ; iba_r = iba_r + 1) + QA[iba_r] <= #(dly) 1'bx; + end //} invalid address + end //} always @(chgmem or AR) + + // Read memory + always @(ABR or RDB) + begin //{ + for (ibb_r = 0 ; ibb_r < Naddr ; ibb_r = ibb_r + 1) + begin + abuf_rb[ibb_r] = ABR[ibb_r]; + if(abuf_rb[ibb_r] !== 0 && abuf_rb[ibb_r] !== 1) + begin + ibb_r = Naddr; + end + end + if(ibb_r == Naddr && abuf_rb < Nword) + begin //{ Read valid address + `ifdef TSMC_INITIALIZE_FAULT + dbuf_rb = mem[abuf_rb] ^ mem_fault[abuf_rb]; + `else + dbuf_rb = mem[abuf_rb]; + `endif + for (ibb_r = 0 ; ibb_r < Ndata ; ibb_r = ibb_r + 1) + begin + if(QB[ibb_r] == dbuf_rb[ibb_r]) + begin + QB[ibb_r] <= #(dly) dbuf_rb[ibb_r]; + end + else + begin + QB[ibb_r] <= #(dly) dbuf_rb[ibb_r]; + end // else + end // for + end //} valid address + else + begin //{ Invalid address + if(ibb_r <= Naddr) begin + if( MES_ALL=="ON" && $realtime != 0) + $fwrite (log, "\nWarning! Int_Array instance, %m:", + "\n\t Port B read address"); + if( MES_ALL=="ON" && $realtime != 0) + $fwrite (log, " x'%0h' out of range", abuf_rb); + if( MES_ALL=="ON" && $realtime != 0) + $fdisplay (log, + " at time %t.", $realtime, + "\n\t Port B outputs set to unknown."); + end + for (ibb_r = 0 ; ibb_r < Ndata ; ibb_r = ibb_r + 1) + QB[ibb_r] <= #(dly) 1'bx; + end //} invalid address + end //} always @(chgmem or AR) + + + // Task for loading contents of a memory + task preloadData; + input [256*8:1] infile; // Max 256 character File Name + begin + $display ("%m: Reading file, %0s, into the register file", infile); + `ifdef TSMC_INITIALIZE_FORMAT_BINARY + $readmemb (infile, mem, 0, Nword-1); + `else + $readmemh (infile, mem, 0, Nword-1); + `endif + end + endtask + + // Task for displaying contents of a memory + task printMemoryFromTo; + input [Naddr - 1:0] from; // memory content are printed, start from this address. + input [Naddr - 1:0] to; // memory content are printed, end at this address. + integer i; + begin //{ + $display ("\n%m: Memory content dump"); + if(from < 0 || from > to || to >= Nword) + begin + $display ("Error! Invalid address range (%0d, %0d).", from, to, + "\nUsage: %m (from, to);", + "\n where from >= 0 and to <= %0d.", Nword-1); + end + else + begin + $display ("\n Address\tValue"); + for (i = from ; i <= to ; i = i + 1) + $display ("%d\t%b", i, mem[i]); + end + end //} + endtask //} + + // Task for printing entire memory, including normal array and redundancy array. + task printMemory; + integer i; + begin + $display ("Dumping register file..."); + $display("@ Address, content-----"); + for (i = 0; i < Nword; i = i + 1) begin + $display("@%d, %b", i, mem[i]); + end + end + endtask + + task xMemoryAll; + begin + for (ib = 0 ; ib < Ndata ; ib = ib + 1) + dbuf[ib] = 1'bx; + for (iw = 0 ; iw < Nword ; iw = iw + 1) + mem[iw] = dbuf; + end + endtask + + task zeroMemoryAll; + begin + for (ib = 0 ; ib < Ndata ; ib = ib + 1) + dbuf[ib] = 1'b0; + for (iw = 0 ; iw < Nword ; iw = iw + 1) + mem[iw] = dbuf; + end + endtask + endmodule + + + diff --git a/rtl/memory/tsdn28hpcpuhdb64x32m4mw_170a_ffg0p99v0c.v b/rtl/memory/tsdn28hpcpuhdb64x32m4mw_170a_ffg0p99v0c.v new file mode 100644 index 0000000..ace66c0 --- /dev/null +++ b/rtl/memory/tsdn28hpcpuhdb64x32m4mw_170a_ffg0p99v0c.v @@ -0,0 +1,2943 @@ +//*#*********************************************************************************************************************/ +//*# Software : TSMC MEMORY COMPILER tsn28hpcpuhddpsram_2012.02.00.d.170a */ +//*# Technology : TSMC 28nm CMOS LOGIC High Performance Compact Mobile 1P10M HKMG CU_ELK 0.9V */ +//*# Memory Type : TSMC 28nm High Performance Compact Mobile Ultra High Density Dual Port SRAM with d127 bit cell SVT Periphery */ +//*# Library Name : tsdn28hpcpuhdb64x32m4mw (user specify : tsdn28hpcpuhdb64x32m4mw_170a) */ +//*# Library Version: 170a */ +//*# Generated Time : 2024/04/10, 14:02:40 */ +//*#*********************************************************************************************************************/ +//*# */ +//*# STATEMENT OF USE */ +//*# */ +//*# This information contains confidential and proprietary information of TSMC. */ +//*# No part of this information may be reproduced, transmitted, transcribed, */ +//*# stored in a retrieval system, or translated into any human or computer */ +//*# language, in any form or by any means, electronic, mechanical, magnetic, */ +//*# optical, chemical, manual, or otherwise, without the prior written permission */ +//*# of TSMC. This information was prepared for informational purpose and is for */ +//*# use by TSMC's customers only. TSMC reserves the right to make changes in the */ +//*# information at any time and without notice. */ +//*# */ +//*#*********************************************************************************************************************/ +///*******************************************************************************/ +//* Usage Limitation: PLEASE READ CAREFULLY FOR CORRECT USAGE */ +//* The model doesn't support the control enable, data, address signals */ +//* transition at positive clock edge. */ +//* Please have some timing delays between control/data/address and clock signals*/ +//* to ensure the correct behavior. */ +//* */ +//* Please be careful when using non 2^n memory. */ +//* In a non-fully decoded array, a write cycle to a nonexistent address location*/ +//* does not change the memory array contents and output remains the same. */ +//* In a non-fully decoded array, a read cycle to a nonexistent address location */ +//* does not change the memory array contents but output becomes unknown. */ +//* */ +//* In the verilog model, the behavior of unknown clock will corrupt the */ +//* memory data and make output unknown regardless of CEB signal. But in the */ +//* silicon, the unknown clock at CEB high, the memory and output data will be */ +//* held. The verilog model behavior is more conservative in this condition. */ +//* */ +//* The model doesn't identify physical column and row address */ +//* */ +//* The verilog model provides TSMC_CM_UNIT_DELAY mode for the fast function */ +//* simulation. */ +//* All timing values in the specification are not checked in the */ +//* TSMC_CM_UNIT_DELAY mode simulation. */ +//* */ +//* */ +//* */ +//* Please use the verilog simulator version with $recrem timing check support. */ +//* Some earlier simulator versions might support $recovery only, not $recrem. */ +//* */ +//* Template Version : S_01_61101 */ +//****************************************************************************** */ +//* Macro Usage : (+define[MACRO] for Verilog compiliers) */ +//* +TSMC_CM_UNIT_DELAY : Enable fast function simulation. */ +//* +no_warning : Disable all runtime warnings message from this model. */ +//* +TSMC_INITIALIZE_MEM : Initialize the memory data in verilog format. */ +//* +TSMC_INITIALIZE_FAULT : Initialize the memory fault data in verilog format. */ +//* +TSMC_NO_TESTPINS_WARNING : Disable the wrong test pins connection error */ +//* message if necessary. */ +//****************************************************************************** */ + +`resetall +`celldefine + +`timescale 1ns/1ps +`delay_mode_path +`suppress_faults +`enable_portfaults + +module tsdn28hpcpuhdb64x32m4mw_170a + ( + RTSEL, + WTSEL, + PTSEL, + AA, + DA, + BWEBA, + WEBA,CEBA,CLK, + AB, + DB, + BWEBB, + WEBB,CEBB, + QA, + QB + ); + +// Parameter declarations +parameter N = 32; +parameter W = 64; +parameter M = 6; +parameter RA = 4; + + wire SLP=1'b0; + wire DSLP=1'b0; + wire SD=1'b0; + input [1:0] RTSEL; + input [1:0] WTSEL; + input [1:0] PTSEL; + +// Input-Output declarations + + input [M-1:0] AA; + input [N-1:0] DA; + input [N-1:0] BWEBA; + + input WEBA; + input CEBA; + input CLK; + input [M-1:0] AB; + input [N-1:0] DB; + input [N-1:0] BWEBB; + input WEBB; + input CEBB; + output [N-1:0] QA; + output [N-1:0] QB; + +`ifdef no_warning +parameter MES_ALL = "OFF"; +`else +parameter MES_ALL = "ON"; +`endif + +`ifdef TSMC_CM_UNIT_DELAY +parameter SRAM_DELAY = 0.010; +`endif +`ifdef TSMC_INITIALIZE_MEM +parameter INITIAL_MEM_DELAY = 0.01; +`else + `ifdef TSMC_INITIALIZE_MEM_USING_DEFAULT_TASKS +parameter INITIAL_MEM_DELAY = 0.01; + `endif +`endif +`ifdef TSMC_INITIALIZE_FAULT +parameter INITIAL_FAULT_DELAY = 0.01; +`endif + +`ifdef TSMC_INITIALIZE_MEM +parameter cdeFileInit = "tsdn28hpcpuhdb64x32m4mw_170a_initial.cde"; +`endif +`ifdef TSMC_INITIALIZE_FAULT +parameter cdeFileFault = "tsdn28hpcpuhdb64x32m4mw_170a_fault.cde"; +`endif + +// Registers +reg invalid_aslp; +reg invalid_bslp; +reg invalid_adslp; +reg invalid_bdslp; +reg invalid_sdwk_dslp; + +reg [N-1:0] DAL; +reg [N-1:0] DBL; +reg [N-1:0] bDBL; + +reg [N-1:0] BWEBAL; +reg [N-1:0] BWEBBL; +reg [N-1:0] bBWEBBL; + +reg [M-1:0] AAL; +reg [M-1:0] ABL; + +reg WEBAL,CEBAL; +reg WEBBL,CEBBL; + +wire [N-1:0] QAL; +wire [N-1:0] QBL; + +reg valid_testpin; + + +reg valid_ck,valid_cka,valid_ckb; +reg valid_cea, valid_ceb; +reg valid_wea, valid_web; +reg valid_aa; +reg valid_ab; +reg valid_contentiona,valid_contentionb,valid_contentionc; +reg valid_da31, valid_da30, valid_da29, valid_da28, valid_da27, valid_da26, valid_da25, valid_da24, valid_da23, valid_da22, valid_da21, valid_da20, valid_da19, valid_da18, valid_da17, valid_da16, valid_da15, valid_da14, valid_da13, valid_da12, valid_da11, valid_da10, valid_da9, valid_da8, valid_da7, valid_da6, valid_da5, valid_da4, valid_da3, valid_da2, valid_da1, valid_da0; +reg valid_db31, valid_db30, valid_db29, valid_db28, valid_db27, valid_db26, valid_db25, valid_db24, valid_db23, valid_db22, valid_db21, valid_db20, valid_db19, valid_db18, valid_db17, valid_db16, valid_db15, valid_db14, valid_db13, valid_db12, valid_db11, valid_db10, valid_db9, valid_db8, valid_db7, valid_db6, valid_db5, valid_db4, valid_db3, valid_db2, valid_db1, valid_db0; +reg valid_bwa31, valid_bwa30, valid_bwa29, valid_bwa28, valid_bwa27, valid_bwa26, valid_bwa25, valid_bwa24, valid_bwa23, valid_bwa22, valid_bwa21, valid_bwa20, valid_bwa19, valid_bwa18, valid_bwa17, valid_bwa16, valid_bwa15, valid_bwa14, valid_bwa13, valid_bwa12, valid_bwa11, valid_bwa10, valid_bwa9, valid_bwa8, valid_bwa7, valid_bwa6, valid_bwa5, valid_bwa4, valid_bwa3, valid_bwa2, valid_bwa1, valid_bwa0; +reg valid_bwb31, valid_bwb30, valid_bwb29, valid_bwb28, valid_bwb27, valid_bwb26, valid_bwb25, valid_bwb24, valid_bwb23, valid_bwb22, valid_bwb21, valid_bwb20, valid_bwb19, valid_bwb18, valid_bwb17, valid_bwb16, valid_bwb15, valid_bwb14, valid_bwb13, valid_bwb12, valid_bwb11, valid_bwb10, valid_bwb9, valid_bwb8, valid_bwb7, valid_bwb6, valid_bwb5, valid_bwb4, valid_bwb3, valid_bwb2, valid_bwb1, valid_bwb0; + +reg EN; +reg RDA, RDB; + +reg RCLKA,RCLKB; + + +wire [1:0] bRTSEL; +wire [1:0] bWTSEL; +wire [1:0] bPTSEL; + + +wire [N-1:0] bBWEBA; +wire [N-1:0] bBWEBB; + +wire [N-1:0] bDA; +wire [N-1:0] bDB; + +wire [M-1:0] bAA; +wire [M-1:0] bAB; +wire [RA-1:0] rowAA; +wire [RA-1:0] rowAB; + +wire bWEBA,bWEBB; +wire bCEBA,bCEBB; +wire bCLKA,bCLKB; + +reg [N-1:0] bQA; +reg [N-1:0] bQB; + +wire bBIST; +wire WEA,WEB,CSA,CSB; +wire bAWT = 1'b0; +wire iCEBA = bCEBA; +wire iCEBB = bCEBB; +wire iCLKA = bCLKA; +wire iCLKB = bCLKB; +wire [N-1:0] iBWEBA = bBWEBA; +wire [N-1:0] iBWEBB = bBWEBB; + +wire [N-1:0] bbQA; +wire [N-1:0] bbQB; + +integer i; +integer clk_count; +integer sd_mode; + + + + +// Address Inputs +buf sAA0 (bAA[0], AA[0]); +buf sAB0 (bAB[0], AB[0]); +buf sAA1 (bAA[1], AA[1]); +buf sAB1 (bAB[1], AB[1]); +buf sAA2 (bAA[2], AA[2]); +buf sAB2 (bAB[2], AB[2]); +buf sAA3 (bAA[3], AA[3]); +buf sAB3 (bAB[3], AB[3]); +buf sAA4 (bAA[4], AA[4]); +buf sAB4 (bAB[4], AB[4]); +buf sAA5 (bAA[5], AA[5]); +buf sAB5 (bAB[5], AB[5]); +buf srAA0 (rowAA[0], AA[2]); +buf srAB0 (rowAB[0], AB[2]); +buf srAA1 (rowAA[1], AA[3]); +buf srAB1 (rowAB[1], AB[3]); +buf srAA2 (rowAA[2], AA[4]); +buf srAB2 (rowAB[2], AB[4]); +buf srAA3 (rowAA[3], AA[5]); +buf srAB3 (rowAB[3], AB[5]); + + +// Bit Write/Data Inputs +buf sDA0 (bDA[0], DA[0]); +buf sDB0 (bDB[0], DB[0]); +buf sDA1 (bDA[1], DA[1]); +buf sDB1 (bDB[1], DB[1]); +buf sDA2 (bDA[2], DA[2]); +buf sDB2 (bDB[2], DB[2]); +buf sDA3 (bDA[3], DA[3]); +buf sDB3 (bDB[3], DB[3]); +buf sDA4 (bDA[4], DA[4]); +buf sDB4 (bDB[4], DB[4]); +buf sDA5 (bDA[5], DA[5]); +buf sDB5 (bDB[5], DB[5]); +buf sDA6 (bDA[6], DA[6]); +buf sDB6 (bDB[6], DB[6]); +buf sDA7 (bDA[7], DA[7]); +buf sDB7 (bDB[7], DB[7]); +buf sDA8 (bDA[8], DA[8]); +buf sDB8 (bDB[8], DB[8]); +buf sDA9 (bDA[9], DA[9]); +buf sDB9 (bDB[9], DB[9]); +buf sDA10 (bDA[10], DA[10]); +buf sDB10 (bDB[10], DB[10]); +buf sDA11 (bDA[11], DA[11]); +buf sDB11 (bDB[11], DB[11]); +buf sDA12 (bDA[12], DA[12]); +buf sDB12 (bDB[12], DB[12]); +buf sDA13 (bDA[13], DA[13]); +buf sDB13 (bDB[13], DB[13]); +buf sDA14 (bDA[14], DA[14]); +buf sDB14 (bDB[14], DB[14]); +buf sDA15 (bDA[15], DA[15]); +buf sDB15 (bDB[15], DB[15]); +buf sDA16 (bDA[16], DA[16]); +buf sDB16 (bDB[16], DB[16]); +buf sDA17 (bDA[17], DA[17]); +buf sDB17 (bDB[17], DB[17]); +buf sDA18 (bDA[18], DA[18]); +buf sDB18 (bDB[18], DB[18]); +buf sDA19 (bDA[19], DA[19]); +buf sDB19 (bDB[19], DB[19]); +buf sDA20 (bDA[20], DA[20]); +buf sDB20 (bDB[20], DB[20]); +buf sDA21 (bDA[21], DA[21]); +buf sDB21 (bDB[21], DB[21]); +buf sDA22 (bDA[22], DA[22]); +buf sDB22 (bDB[22], DB[22]); +buf sDA23 (bDA[23], DA[23]); +buf sDB23 (bDB[23], DB[23]); +buf sDA24 (bDA[24], DA[24]); +buf sDB24 (bDB[24], DB[24]); +buf sDA25 (bDA[25], DA[25]); +buf sDB25 (bDB[25], DB[25]); +buf sDA26 (bDA[26], DA[26]); +buf sDB26 (bDB[26], DB[26]); +buf sDA27 (bDA[27], DA[27]); +buf sDB27 (bDB[27], DB[27]); +buf sDA28 (bDA[28], DA[28]); +buf sDB28 (bDB[28], DB[28]); +buf sDA29 (bDA[29], DA[29]); +buf sDB29 (bDB[29], DB[29]); +buf sDA30 (bDA[30], DA[30]); +buf sDB30 (bDB[30], DB[30]); +buf sDA31 (bDA[31], DA[31]); +buf sDB31 (bDB[31], DB[31]); + + +buf sBWEBA0 (bBWEBA[0], BWEBA[0]); +buf sBWEBB0 (bBWEBB[0], BWEBB[0]); +buf sBWEBA1 (bBWEBA[1], BWEBA[1]); +buf sBWEBB1 (bBWEBB[1], BWEBB[1]); +buf sBWEBA2 (bBWEBA[2], BWEBA[2]); +buf sBWEBB2 (bBWEBB[2], BWEBB[2]); +buf sBWEBA3 (bBWEBA[3], BWEBA[3]); +buf sBWEBB3 (bBWEBB[3], BWEBB[3]); +buf sBWEBA4 (bBWEBA[4], BWEBA[4]); +buf sBWEBB4 (bBWEBB[4], BWEBB[4]); +buf sBWEBA5 (bBWEBA[5], BWEBA[5]); +buf sBWEBB5 (bBWEBB[5], BWEBB[5]); +buf sBWEBA6 (bBWEBA[6], BWEBA[6]); +buf sBWEBB6 (bBWEBB[6], BWEBB[6]); +buf sBWEBA7 (bBWEBA[7], BWEBA[7]); +buf sBWEBB7 (bBWEBB[7], BWEBB[7]); +buf sBWEBA8 (bBWEBA[8], BWEBA[8]); +buf sBWEBB8 (bBWEBB[8], BWEBB[8]); +buf sBWEBA9 (bBWEBA[9], BWEBA[9]); +buf sBWEBB9 (bBWEBB[9], BWEBB[9]); +buf sBWEBA10 (bBWEBA[10], BWEBA[10]); +buf sBWEBB10 (bBWEBB[10], BWEBB[10]); +buf sBWEBA11 (bBWEBA[11], BWEBA[11]); +buf sBWEBB11 (bBWEBB[11], BWEBB[11]); +buf sBWEBA12 (bBWEBA[12], BWEBA[12]); +buf sBWEBB12 (bBWEBB[12], BWEBB[12]); +buf sBWEBA13 (bBWEBA[13], BWEBA[13]); +buf sBWEBB13 (bBWEBB[13], BWEBB[13]); +buf sBWEBA14 (bBWEBA[14], BWEBA[14]); +buf sBWEBB14 (bBWEBB[14], BWEBB[14]); +buf sBWEBA15 (bBWEBA[15], BWEBA[15]); +buf sBWEBB15 (bBWEBB[15], BWEBB[15]); +buf sBWEBA16 (bBWEBA[16], BWEBA[16]); +buf sBWEBB16 (bBWEBB[16], BWEBB[16]); +buf sBWEBA17 (bBWEBA[17], BWEBA[17]); +buf sBWEBB17 (bBWEBB[17], BWEBB[17]); +buf sBWEBA18 (bBWEBA[18], BWEBA[18]); +buf sBWEBB18 (bBWEBB[18], BWEBB[18]); +buf sBWEBA19 (bBWEBA[19], BWEBA[19]); +buf sBWEBB19 (bBWEBB[19], BWEBB[19]); +buf sBWEBA20 (bBWEBA[20], BWEBA[20]); +buf sBWEBB20 (bBWEBB[20], BWEBB[20]); +buf sBWEBA21 (bBWEBA[21], BWEBA[21]); +buf sBWEBB21 (bBWEBB[21], BWEBB[21]); +buf sBWEBA22 (bBWEBA[22], BWEBA[22]); +buf sBWEBB22 (bBWEBB[22], BWEBB[22]); +buf sBWEBA23 (bBWEBA[23], BWEBA[23]); +buf sBWEBB23 (bBWEBB[23], BWEBB[23]); +buf sBWEBA24 (bBWEBA[24], BWEBA[24]); +buf sBWEBB24 (bBWEBB[24], BWEBB[24]); +buf sBWEBA25 (bBWEBA[25], BWEBA[25]); +buf sBWEBB25 (bBWEBB[25], BWEBB[25]); +buf sBWEBA26 (bBWEBA[26], BWEBA[26]); +buf sBWEBB26 (bBWEBB[26], BWEBB[26]); +buf sBWEBA27 (bBWEBA[27], BWEBA[27]); +buf sBWEBB27 (bBWEBB[27], BWEBB[27]); +buf sBWEBA28 (bBWEBA[28], BWEBA[28]); +buf sBWEBB28 (bBWEBB[28], BWEBB[28]); +buf sBWEBA29 (bBWEBA[29], BWEBA[29]); +buf sBWEBB29 (bBWEBB[29], BWEBB[29]); +buf sBWEBA30 (bBWEBA[30], BWEBA[30]); +buf sBWEBB30 (bBWEBB[30], BWEBB[30]); +buf sBWEBA31 (bBWEBA[31], BWEBA[31]); +buf sBWEBB31 (bBWEBB[31], BWEBB[31]); + + +// Input Controls +buf sWEBA (bWEBA, WEBA); +buf sWEBB (bWEBB, WEBB); +wire bSLP = 1'b0; +wire bDSLP = 1'b0; +wire bSD = 1'b0; + +buf sCEBA (bCEBA, CEBA); +buf sCEBB (bCEBB, CEBB); + +buf sCLKA (bCLKA, CLK); +buf sCLKB (bCLKB, CLK); +assign bBIST = 1'b0; + +buf sRTSEL0 (bRTSEL[0], RTSEL[0]); +buf sRTSEL1 (bRTSEL[1], RTSEL[1]); +buf sWTSEL0 (bWTSEL[0], WTSEL[0]); +buf sWTSEL1 (bWTSEL[1], WTSEL[1]); +buf sPTSEL0 (bPTSEL[0], PTSEL[0]); +buf sPTSEL1 (bPTSEL[1], PTSEL[1]); + +// Output Data +buf sQA0 (QA[0], bbQA[0]); +buf sQA1 (QA[1], bbQA[1]); +buf sQA2 (QA[2], bbQA[2]); +buf sQA3 (QA[3], bbQA[3]); +buf sQA4 (QA[4], bbQA[4]); +buf sQA5 (QA[5], bbQA[5]); +buf sQA6 (QA[6], bbQA[6]); +buf sQA7 (QA[7], bbQA[7]); +buf sQA8 (QA[8], bbQA[8]); +buf sQA9 (QA[9], bbQA[9]); +buf sQA10 (QA[10], bbQA[10]); +buf sQA11 (QA[11], bbQA[11]); +buf sQA12 (QA[12], bbQA[12]); +buf sQA13 (QA[13], bbQA[13]); +buf sQA14 (QA[14], bbQA[14]); +buf sQA15 (QA[15], bbQA[15]); +buf sQA16 (QA[16], bbQA[16]); +buf sQA17 (QA[17], bbQA[17]); +buf sQA18 (QA[18], bbQA[18]); +buf sQA19 (QA[19], bbQA[19]); +buf sQA20 (QA[20], bbQA[20]); +buf sQA21 (QA[21], bbQA[21]); +buf sQA22 (QA[22], bbQA[22]); +buf sQA23 (QA[23], bbQA[23]); +buf sQA24 (QA[24], bbQA[24]); +buf sQA25 (QA[25], bbQA[25]); +buf sQA26 (QA[26], bbQA[26]); +buf sQA27 (QA[27], bbQA[27]); +buf sQA28 (QA[28], bbQA[28]); +buf sQA29 (QA[29], bbQA[29]); +buf sQA30 (QA[30], bbQA[30]); +buf sQA31 (QA[31], bbQA[31]); + +buf sQB0 (QB[0], bbQB[0]); +buf sQB1 (QB[1], bbQB[1]); +buf sQB2 (QB[2], bbQB[2]); +buf sQB3 (QB[3], bbQB[3]); +buf sQB4 (QB[4], bbQB[4]); +buf sQB5 (QB[5], bbQB[5]); +buf sQB6 (QB[6], bbQB[6]); +buf sQB7 (QB[7], bbQB[7]); +buf sQB8 (QB[8], bbQB[8]); +buf sQB9 (QB[9], bbQB[9]); +buf sQB10 (QB[10], bbQB[10]); +buf sQB11 (QB[11], bbQB[11]); +buf sQB12 (QB[12], bbQB[12]); +buf sQB13 (QB[13], bbQB[13]); +buf sQB14 (QB[14], bbQB[14]); +buf sQB15 (QB[15], bbQB[15]); +buf sQB16 (QB[16], bbQB[16]); +buf sQB17 (QB[17], bbQB[17]); +buf sQB18 (QB[18], bbQB[18]); +buf sQB19 (QB[19], bbQB[19]); +buf sQB20 (QB[20], bbQB[20]); +buf sQB21 (QB[21], bbQB[21]); +buf sQB22 (QB[22], bbQB[22]); +buf sQB23 (QB[23], bbQB[23]); +buf sQB24 (QB[24], bbQB[24]); +buf sQB25 (QB[25], bbQB[25]); +buf sQB26 (QB[26], bbQB[26]); +buf sQB27 (QB[27], bbQB[27]); +buf sQB28 (QB[28], bbQB[28]); +buf sQB29 (QB[29], bbQB[29]); +buf sQB30 (QB[30], bbQB[30]); +buf sQB31 (QB[31], bbQB[31]); + +assign bbQA=bQA; +assign bbQB=bQB; + +//and sWEA (WEA, !bWEBA, !bCEBA); +//and sWEB (WEB, !bWEBB, !bCEBB); +assign WEA = !bSLP & !bDSLP & !bSD & !bCEBA & !bWEBA; +assign WEB = !bSLP & !bDSLP & !bSD & !bCEBB & !bWEBB; + +//buf sCSA (CSA, !bCEBA); +//buf sCSB (CSB, !bCEBB); +assign CSA = !bSLP & !bDSLP & !bSD & !bCEBA; +assign CSB = !bSLP & !bDSLP & !bSD & !bCEBB; + +wire check_noidle_b = ~CEBBL & ~bSD & ~bDSLP & ~bSLP; +wire check_idle_b = CEBBL & ~bSD & ~bDSLP & ~bSLP; +wire check_noidle_a = ~CEBAL & ~bSD & ~bDSLP & ~bSLP; +wire check_idle_a = CEBAL & ~bSD & ~bDSLP & ~bSLP; +wire check_noidle_norm_b = check_noidle_b & ~bBIST; +wire check_noidle_bist_b = check_noidle_b & bBIST; +wire check_idle_norm_b = check_idle_b & ~bBIST; +wire check_idle_bist_b = check_idle_b & bBIST; +wire check_noidle_norm_a = check_noidle_a & ~bBIST; +wire check_noidle_bist_a = check_noidle_a & bBIST; +wire check_idle_norm_a = check_idle_a & !bBIST; +wire check_idle_bist_a = check_idle_a & bBIST; + +wire check_ceb = (~iCEBA | ~iCEBB) & ~bSD & ~bDSLP & ~bSLP; +wire check_ceba = ~iCEBA & ~bSD & ~bDSLP & ~bSLP; +wire check_cebb = ~iCEBB & ~bSD & ~bDSLP & ~bSLP; +wire check_cebm = (~iCEBA | ~iCEBB) & ~bSD & ~bDSLP & ~bSLP; +wire check_ceb_a = ~iCEBA & iCEBB & ~bSD & ~bDSLP & ~bSLP; +wire check_ceb_b = iCEBA & ~iCEBB & ~bSD & ~bDSLP & ~bSLP; +wire check_ceb_ab = ~iCEBA & ~iCEBB & ~bSD & ~bDSLP & ~bSLP; + + + + + +wire check_slp = !bSD & !bDSLP; +wire check_dslp = !bSD & !bSLP; + + +`ifdef TSMC_CM_UNIT_DELAY +`else +specify + specparam PATHPULSE$ = ( 0, 0.001 ); + +specparam +tckl = 0.0874826, +tckh = 0.0874826, +tcyc = 0.5520369, + + +taas = 0.0529629, +taah = 0.0589500, +tdas = 0.0100000, +tdah = 0.0704311, +tcas = 0.0766141, +tcah = 0.0771363, +twas = 0.0710609, +twah = 0.0581437, +tbwas = 0.0113817, +tbwah = 0.0701011, + +tabs = 0.0100000, +tabh = 0.0771363, +tdbs = 0.0100000, +tdbh = 0.1016880, +tcbs = 0.0766141, +tcbh = 0.0771363, +twbs = 0.0100000, +twbh = 0.0771363, +tbwbs = 0.0100000, +tbwbh = 0.1017557, + +ttests = 0.552, +ttesth = 0.552, +tcda = 0.2460178, +tcdb = 0.5222804, +`ifdef TSMC_CM_READ_X_SQUASHING +tholda = 0.2460178, +tholdb = 0.5222804; +`else +tholda = 0.1698300, +tholdb = 0.3964251; +`endif + + $setuphold (posedge CLK &&& check_noidle_a, posedge RTSEL[0], ttests, 0, valid_testpin); + $setuphold (posedge CLK &&& check_noidle_a, negedge RTSEL[0], ttests, 0, valid_testpin); + $setuphold (posedge CLK &&& check_idle_a, posedge RTSEL[0], 0, ttesth, valid_testpin); + $setuphold (posedge CLK &&& check_idle_a, negedge RTSEL[0], 0, ttesth, valid_testpin); + $setuphold (posedge CLK &&& check_noidle_a, posedge RTSEL[1], ttests, 0, valid_testpin); + $setuphold (posedge CLK &&& check_noidle_a, negedge RTSEL[1], ttests, 0, valid_testpin); + $setuphold (posedge CLK &&& check_idle_a, posedge RTSEL[1], 0, ttesth, valid_testpin); + $setuphold (posedge CLK &&& check_idle_a, negedge RTSEL[1], 0, ttesth, valid_testpin); + $setuphold (posedge CLK &&& check_noidle_a, posedge WTSEL[0], ttests, 0, valid_testpin); + $setuphold (posedge CLK &&& check_noidle_a, negedge WTSEL[0], ttests, 0, valid_testpin); + $setuphold (posedge CLK &&& check_idle_a, posedge WTSEL[0], 0, ttesth, valid_testpin); + $setuphold (posedge CLK &&& check_idle_a, negedge WTSEL[0], 0, ttesth, valid_testpin); + $setuphold (posedge CLK &&& check_noidle_a, posedge WTSEL[1], ttests, 0, valid_testpin); + $setuphold (posedge CLK &&& check_noidle_a, negedge WTSEL[1], ttests, 0, valid_testpin); + $setuphold (posedge CLK &&& check_idle_a, posedge WTSEL[1], 0, ttesth, valid_testpin); + $setuphold (posedge CLK &&& check_idle_a, negedge WTSEL[1], 0, ttesth, valid_testpin); + $setuphold (posedge CLK &&& check_noidle_a, posedge PTSEL[0], ttests, 0, valid_testpin); + $setuphold (posedge CLK &&& check_noidle_a, negedge PTSEL[0], ttests, 0, valid_testpin); + $setuphold (posedge CLK &&& check_idle_a, posedge PTSEL[0], 0, ttesth, valid_testpin); + $setuphold (posedge CLK &&& check_idle_a, negedge PTSEL[0], 0, ttesth, valid_testpin); + $setuphold (posedge CLK &&& check_noidle_a, posedge PTSEL[1], ttests, 0, valid_testpin); + $setuphold (posedge CLK &&& check_noidle_a, negedge PTSEL[1], ttests, 0, valid_testpin); + $setuphold (posedge CLK &&& check_idle_a, posedge PTSEL[1], 0, ttesth, valid_testpin); + $setuphold (posedge CLK &&& check_idle_a, negedge PTSEL[1], 0, ttesth, valid_testpin); + $setuphold (posedge CLK &&& check_noidle_b, posedge RTSEL[0], ttests, 0, valid_testpin); + $setuphold (posedge CLK &&& check_noidle_b, negedge RTSEL[0], ttests, 0, valid_testpin); + $setuphold (posedge CLK &&& check_idle_b, posedge RTSEL[0], 0, ttesth, valid_testpin); + $setuphold (posedge CLK &&& check_idle_b, negedge RTSEL[0], 0, ttesth, valid_testpin); + $setuphold (posedge CLK &&& check_noidle_b, posedge RTSEL[1], ttests, 0, valid_testpin); + $setuphold (posedge CLK &&& check_noidle_b, negedge RTSEL[1], ttests, 0, valid_testpin); + $setuphold (posedge CLK &&& check_idle_b, posedge RTSEL[1], 0, ttesth, valid_testpin); + $setuphold (posedge CLK &&& check_idle_b, negedge RTSEL[1], 0, ttesth, valid_testpin); + $setuphold (posedge CLK &&& check_noidle_b, posedge WTSEL[0], ttests, 0, valid_testpin); + $setuphold (posedge CLK &&& check_noidle_b, negedge WTSEL[0], ttests, 0, valid_testpin); + $setuphold (posedge CLK &&& check_idle_b, posedge WTSEL[0], 0, ttesth, valid_testpin); + $setuphold (posedge CLK &&& check_idle_b, negedge WTSEL[0], 0, ttesth, valid_testpin); + $setuphold (posedge CLK &&& check_noidle_b, posedge WTSEL[1], ttests, 0, valid_testpin); + $setuphold (posedge CLK &&& check_noidle_b, negedge WTSEL[1], ttests, 0, valid_testpin); + $setuphold (posedge CLK &&& check_idle_b, posedge WTSEL[1], 0, ttesth, valid_testpin); + $setuphold (posedge CLK &&& check_idle_b, negedge WTSEL[1], 0, ttesth, valid_testpin); + $setuphold (posedge CLK &&& check_noidle_b, posedge PTSEL[0], ttests, 0, valid_testpin); + $setuphold (posedge CLK &&& check_noidle_b, negedge PTSEL[0], ttests, 0, valid_testpin); + $setuphold (posedge CLK &&& check_idle_b, posedge PTSEL[0], 0, ttesth, valid_testpin); + $setuphold (posedge CLK &&& check_idle_b, negedge PTSEL[0], 0, ttesth, valid_testpin); + $setuphold (posedge CLK &&& check_noidle_b, posedge PTSEL[1], ttests, 0, valid_testpin); + $setuphold (posedge CLK &&& check_noidle_b, negedge PTSEL[1], ttests, 0, valid_testpin); + $setuphold (posedge CLK &&& check_idle_b, posedge PTSEL[1], 0, ttesth, valid_testpin); + $setuphold (posedge CLK &&& check_idle_b, negedge PTSEL[1], 0, ttesth, valid_testpin); + + + + + + + + + + + $setuphold (posedge CLK &&& CSA, posedge AA[0], taas, taah, valid_aa); + $setuphold (posedge CLK &&& CSA, negedge AA[0], taas, taah, valid_aa); + $setuphold (posedge CLK &&& CSB, posedge AB[0], tabs, tabh, valid_ab); + $setuphold (posedge CLK &&& CSB, negedge AB[0], tabs, tabh, valid_ab); + $setuphold (posedge CLK &&& CSA, posedge AA[1], taas, taah, valid_aa); + $setuphold (posedge CLK &&& CSA, negedge AA[1], taas, taah, valid_aa); + $setuphold (posedge CLK &&& CSB, posedge AB[1], tabs, tabh, valid_ab); + $setuphold (posedge CLK &&& CSB, negedge AB[1], tabs, tabh, valid_ab); + $setuphold (posedge CLK &&& CSA, posedge AA[2], taas, taah, valid_aa); + $setuphold (posedge CLK &&& CSA, negedge AA[2], taas, taah, valid_aa); + $setuphold (posedge CLK &&& CSB, posedge AB[2], tabs, tabh, valid_ab); + $setuphold (posedge CLK &&& CSB, negedge AB[2], tabs, tabh, valid_ab); + $setuphold (posedge CLK &&& CSA, posedge AA[3], taas, taah, valid_aa); + $setuphold (posedge CLK &&& CSA, negedge AA[3], taas, taah, valid_aa); + $setuphold (posedge CLK &&& CSB, posedge AB[3], tabs, tabh, valid_ab); + $setuphold (posedge CLK &&& CSB, negedge AB[3], tabs, tabh, valid_ab); + $setuphold (posedge CLK &&& CSA, posedge AA[4], taas, taah, valid_aa); + $setuphold (posedge CLK &&& CSA, negedge AA[4], taas, taah, valid_aa); + $setuphold (posedge CLK &&& CSB, posedge AB[4], tabs, tabh, valid_ab); + $setuphold (posedge CLK &&& CSB, negedge AB[4], tabs, tabh, valid_ab); + $setuphold (posedge CLK &&& CSA, posedge AA[5], taas, taah, valid_aa); + $setuphold (posedge CLK &&& CSA, negedge AA[5], taas, taah, valid_aa); + $setuphold (posedge CLK &&& CSB, posedge AB[5], tabs, tabh, valid_ab); + $setuphold (posedge CLK &&& CSB, negedge AB[5], tabs, tabh, valid_ab); + + $setuphold (posedge CLK &&& WEA, posedge DA[0], tdas, tdah, valid_da0); + $setuphold (posedge CLK &&& WEA, negedge DA[0], tdas, tdah, valid_da0); + $setuphold (posedge CLK &&& WEB, posedge DB[0], tdbs, tdbh, valid_db0); + $setuphold (posedge CLK &&& WEB, negedge DB[0], tdbs, tdbh, valid_db0); + + $setuphold (posedge CLK &&& WEA, posedge BWEBA[0], tbwas, tbwah, valid_bwa0); + $setuphold (posedge CLK &&& WEA, negedge BWEBA[0], tbwas, tbwah, valid_bwa0); + $setuphold (posedge CLK &&& WEB, posedge BWEBB[0], tbwbs, tbwbh, valid_bwb0); + $setuphold (posedge CLK &&& WEB, negedge BWEBB[0], tbwbs, tbwbh, valid_bwb0); + $setuphold (posedge CLK &&& WEA, posedge DA[1], tdas, tdah, valid_da1); + $setuphold (posedge CLK &&& WEA, negedge DA[1], tdas, tdah, valid_da1); + $setuphold (posedge CLK &&& WEB, posedge DB[1], tdbs, tdbh, valid_db1); + $setuphold (posedge CLK &&& WEB, negedge DB[1], tdbs, tdbh, valid_db1); + + $setuphold (posedge CLK &&& WEA, posedge BWEBA[1], tbwas, tbwah, valid_bwa1); + $setuphold (posedge CLK &&& WEA, negedge BWEBA[1], tbwas, tbwah, valid_bwa1); + $setuphold (posedge CLK &&& WEB, posedge BWEBB[1], tbwbs, tbwbh, valid_bwb1); + $setuphold (posedge CLK &&& WEB, negedge BWEBB[1], tbwbs, tbwbh, valid_bwb1); + $setuphold (posedge CLK &&& WEA, posedge DA[2], tdas, tdah, valid_da2); + $setuphold (posedge CLK &&& WEA, negedge DA[2], tdas, tdah, valid_da2); + $setuphold (posedge CLK &&& WEB, posedge DB[2], tdbs, tdbh, valid_db2); + $setuphold (posedge CLK &&& WEB, negedge DB[2], tdbs, tdbh, valid_db2); + + $setuphold (posedge CLK &&& WEA, posedge BWEBA[2], tbwas, tbwah, valid_bwa2); + $setuphold (posedge CLK &&& WEA, negedge BWEBA[2], tbwas, tbwah, valid_bwa2); + $setuphold (posedge CLK &&& WEB, posedge BWEBB[2], tbwbs, tbwbh, valid_bwb2); + $setuphold (posedge CLK &&& WEB, negedge BWEBB[2], tbwbs, tbwbh, valid_bwb2); + $setuphold (posedge CLK &&& WEA, posedge DA[3], tdas, tdah, valid_da3); + $setuphold (posedge CLK &&& WEA, negedge DA[3], tdas, tdah, valid_da3); + $setuphold (posedge CLK &&& WEB, posedge DB[3], tdbs, tdbh, valid_db3); + $setuphold (posedge CLK &&& WEB, negedge DB[3], tdbs, tdbh, valid_db3); + + $setuphold (posedge CLK &&& WEA, posedge BWEBA[3], tbwas, tbwah, valid_bwa3); + $setuphold (posedge CLK &&& WEA, negedge BWEBA[3], tbwas, tbwah, valid_bwa3); + $setuphold (posedge CLK &&& WEB, posedge BWEBB[3], tbwbs, tbwbh, valid_bwb3); + $setuphold (posedge CLK &&& WEB, negedge BWEBB[3], tbwbs, tbwbh, valid_bwb3); + $setuphold (posedge CLK &&& WEA, posedge DA[4], tdas, tdah, valid_da4); + $setuphold (posedge CLK &&& WEA, negedge DA[4], tdas, tdah, valid_da4); + $setuphold (posedge CLK &&& WEB, posedge DB[4], tdbs, tdbh, valid_db4); + $setuphold (posedge CLK &&& WEB, negedge DB[4], tdbs, tdbh, valid_db4); + + $setuphold (posedge CLK &&& WEA, posedge BWEBA[4], tbwas, tbwah, valid_bwa4); + $setuphold (posedge CLK &&& WEA, negedge BWEBA[4], tbwas, tbwah, valid_bwa4); + $setuphold (posedge CLK &&& WEB, posedge BWEBB[4], tbwbs, tbwbh, valid_bwb4); + $setuphold (posedge CLK &&& WEB, negedge BWEBB[4], tbwbs, tbwbh, valid_bwb4); + $setuphold (posedge CLK &&& WEA, posedge DA[5], tdas, tdah, valid_da5); + $setuphold (posedge CLK &&& WEA, negedge DA[5], tdas, tdah, valid_da5); + $setuphold (posedge CLK &&& WEB, posedge DB[5], tdbs, tdbh, valid_db5); + $setuphold (posedge CLK &&& WEB, negedge DB[5], tdbs, tdbh, valid_db5); + + $setuphold (posedge CLK &&& WEA, posedge BWEBA[5], tbwas, tbwah, valid_bwa5); + $setuphold (posedge CLK &&& WEA, negedge BWEBA[5], tbwas, tbwah, valid_bwa5); + $setuphold (posedge CLK &&& WEB, posedge BWEBB[5], tbwbs, tbwbh, valid_bwb5); + $setuphold (posedge CLK &&& WEB, negedge BWEBB[5], tbwbs, tbwbh, valid_bwb5); + $setuphold (posedge CLK &&& WEA, posedge DA[6], tdas, tdah, valid_da6); + $setuphold (posedge CLK &&& WEA, negedge DA[6], tdas, tdah, valid_da6); + $setuphold (posedge CLK &&& WEB, posedge DB[6], tdbs, tdbh, valid_db6); + $setuphold (posedge CLK &&& WEB, negedge DB[6], tdbs, tdbh, valid_db6); + + $setuphold (posedge CLK &&& WEA, posedge BWEBA[6], tbwas, tbwah, valid_bwa6); + $setuphold (posedge CLK &&& WEA, negedge BWEBA[6], tbwas, tbwah, valid_bwa6); + $setuphold (posedge CLK &&& WEB, posedge BWEBB[6], tbwbs, tbwbh, valid_bwb6); + $setuphold (posedge CLK &&& WEB, negedge BWEBB[6], tbwbs, tbwbh, valid_bwb6); + $setuphold (posedge CLK &&& WEA, posedge DA[7], tdas, tdah, valid_da7); + $setuphold (posedge CLK &&& WEA, negedge DA[7], tdas, tdah, valid_da7); + $setuphold (posedge CLK &&& WEB, posedge DB[7], tdbs, tdbh, valid_db7); + $setuphold (posedge CLK &&& WEB, negedge DB[7], tdbs, tdbh, valid_db7); + + $setuphold (posedge CLK &&& WEA, posedge BWEBA[7], tbwas, tbwah, valid_bwa7); + $setuphold (posedge CLK &&& WEA, negedge BWEBA[7], tbwas, tbwah, valid_bwa7); + $setuphold (posedge CLK &&& WEB, posedge BWEBB[7], tbwbs, tbwbh, valid_bwb7); + $setuphold (posedge CLK &&& WEB, negedge BWEBB[7], tbwbs, tbwbh, valid_bwb7); + $setuphold (posedge CLK &&& WEA, posedge DA[8], tdas, tdah, valid_da8); + $setuphold (posedge CLK &&& WEA, negedge DA[8], tdas, tdah, valid_da8); + $setuphold (posedge CLK &&& WEB, posedge DB[8], tdbs, tdbh, valid_db8); + $setuphold (posedge CLK &&& WEB, negedge DB[8], tdbs, tdbh, valid_db8); + + $setuphold (posedge CLK &&& WEA, posedge BWEBA[8], tbwas, tbwah, valid_bwa8); + $setuphold (posedge CLK &&& WEA, negedge BWEBA[8], tbwas, tbwah, valid_bwa8); + $setuphold (posedge CLK &&& WEB, posedge BWEBB[8], tbwbs, tbwbh, valid_bwb8); + $setuphold (posedge CLK &&& WEB, negedge BWEBB[8], tbwbs, tbwbh, valid_bwb8); + $setuphold (posedge CLK &&& WEA, posedge DA[9], tdas, tdah, valid_da9); + $setuphold (posedge CLK &&& WEA, negedge DA[9], tdas, tdah, valid_da9); + $setuphold (posedge CLK &&& WEB, posedge DB[9], tdbs, tdbh, valid_db9); + $setuphold (posedge CLK &&& WEB, negedge DB[9], tdbs, tdbh, valid_db9); + + $setuphold (posedge CLK &&& WEA, posedge BWEBA[9], tbwas, tbwah, valid_bwa9); + $setuphold (posedge CLK &&& WEA, negedge BWEBA[9], tbwas, tbwah, valid_bwa9); + $setuphold (posedge CLK &&& WEB, posedge BWEBB[9], tbwbs, tbwbh, valid_bwb9); + $setuphold (posedge CLK &&& WEB, negedge BWEBB[9], tbwbs, tbwbh, valid_bwb9); + $setuphold (posedge CLK &&& WEA, posedge DA[10], tdas, tdah, valid_da10); + $setuphold (posedge CLK &&& WEA, negedge DA[10], tdas, tdah, valid_da10); + $setuphold (posedge CLK &&& WEB, posedge DB[10], tdbs, tdbh, valid_db10); + $setuphold (posedge CLK &&& WEB, negedge DB[10], tdbs, tdbh, valid_db10); + + $setuphold (posedge CLK &&& WEA, posedge BWEBA[10], tbwas, tbwah, valid_bwa10); + $setuphold (posedge CLK &&& WEA, negedge BWEBA[10], tbwas, tbwah, valid_bwa10); + $setuphold (posedge CLK &&& WEB, posedge BWEBB[10], tbwbs, tbwbh, valid_bwb10); + $setuphold (posedge CLK &&& WEB, negedge BWEBB[10], tbwbs, tbwbh, valid_bwb10); + $setuphold (posedge CLK &&& WEA, posedge DA[11], tdas, tdah, valid_da11); + $setuphold (posedge CLK &&& WEA, negedge DA[11], tdas, tdah, valid_da11); + $setuphold (posedge CLK &&& WEB, posedge DB[11], tdbs, tdbh, valid_db11); + $setuphold (posedge CLK &&& WEB, negedge DB[11], tdbs, tdbh, valid_db11); + + $setuphold (posedge CLK &&& WEA, posedge BWEBA[11], tbwas, tbwah, valid_bwa11); + $setuphold (posedge CLK &&& WEA, negedge BWEBA[11], tbwas, tbwah, valid_bwa11); + $setuphold (posedge CLK &&& WEB, posedge BWEBB[11], tbwbs, tbwbh, valid_bwb11); + $setuphold (posedge CLK &&& WEB, negedge BWEBB[11], tbwbs, tbwbh, valid_bwb11); + $setuphold (posedge CLK &&& WEA, posedge DA[12], tdas, tdah, valid_da12); + $setuphold (posedge CLK &&& WEA, negedge DA[12], tdas, tdah, valid_da12); + $setuphold (posedge CLK &&& WEB, posedge DB[12], tdbs, tdbh, valid_db12); + $setuphold (posedge CLK &&& WEB, negedge DB[12], tdbs, tdbh, valid_db12); + + $setuphold (posedge CLK &&& WEA, posedge BWEBA[12], tbwas, tbwah, valid_bwa12); + $setuphold (posedge CLK &&& WEA, negedge BWEBA[12], tbwas, tbwah, valid_bwa12); + $setuphold (posedge CLK &&& WEB, posedge BWEBB[12], tbwbs, tbwbh, valid_bwb12); + $setuphold (posedge CLK &&& WEB, negedge BWEBB[12], tbwbs, tbwbh, valid_bwb12); + $setuphold (posedge CLK &&& WEA, posedge DA[13], tdas, tdah, valid_da13); + $setuphold (posedge CLK &&& WEA, negedge DA[13], tdas, tdah, valid_da13); + $setuphold (posedge CLK &&& WEB, posedge DB[13], tdbs, tdbh, valid_db13); + $setuphold (posedge CLK &&& WEB, negedge DB[13], tdbs, tdbh, valid_db13); + + $setuphold (posedge CLK &&& WEA, posedge BWEBA[13], tbwas, tbwah, valid_bwa13); + $setuphold (posedge CLK &&& WEA, negedge BWEBA[13], tbwas, tbwah, valid_bwa13); + $setuphold (posedge CLK &&& WEB, posedge BWEBB[13], tbwbs, tbwbh, valid_bwb13); + $setuphold (posedge CLK &&& WEB, negedge BWEBB[13], tbwbs, tbwbh, valid_bwb13); + $setuphold (posedge CLK &&& WEA, posedge DA[14], tdas, tdah, valid_da14); + $setuphold (posedge CLK &&& WEA, negedge DA[14], tdas, tdah, valid_da14); + $setuphold (posedge CLK &&& WEB, posedge DB[14], tdbs, tdbh, valid_db14); + $setuphold (posedge CLK &&& WEB, negedge DB[14], tdbs, tdbh, valid_db14); + + $setuphold (posedge CLK &&& WEA, posedge BWEBA[14], tbwas, tbwah, valid_bwa14); + $setuphold (posedge CLK &&& WEA, negedge BWEBA[14], tbwas, tbwah, valid_bwa14); + $setuphold (posedge CLK &&& WEB, posedge BWEBB[14], tbwbs, tbwbh, valid_bwb14); + $setuphold (posedge CLK &&& WEB, negedge BWEBB[14], tbwbs, tbwbh, valid_bwb14); + $setuphold (posedge CLK &&& WEA, posedge DA[15], tdas, tdah, valid_da15); + $setuphold (posedge CLK &&& WEA, negedge DA[15], tdas, tdah, valid_da15); + $setuphold (posedge CLK &&& WEB, posedge DB[15], tdbs, tdbh, valid_db15); + $setuphold (posedge CLK &&& WEB, negedge DB[15], tdbs, tdbh, valid_db15); + + $setuphold (posedge CLK &&& WEA, posedge BWEBA[15], tbwas, tbwah, valid_bwa15); + $setuphold (posedge CLK &&& WEA, negedge BWEBA[15], tbwas, tbwah, valid_bwa15); + $setuphold (posedge CLK &&& WEB, posedge BWEBB[15], tbwbs, tbwbh, valid_bwb15); + $setuphold (posedge CLK &&& WEB, negedge BWEBB[15], tbwbs, tbwbh, valid_bwb15); + $setuphold (posedge CLK &&& WEA, posedge DA[16], tdas, tdah, valid_da16); + $setuphold (posedge CLK &&& WEA, negedge DA[16], tdas, tdah, valid_da16); + $setuphold (posedge CLK &&& WEB, posedge DB[16], tdbs, tdbh, valid_db16); + $setuphold (posedge CLK &&& WEB, negedge DB[16], tdbs, tdbh, valid_db16); + + $setuphold (posedge CLK &&& WEA, posedge BWEBA[16], tbwas, tbwah, valid_bwa16); + $setuphold (posedge CLK &&& WEA, negedge BWEBA[16], tbwas, tbwah, valid_bwa16); + $setuphold (posedge CLK &&& WEB, posedge BWEBB[16], tbwbs, tbwbh, valid_bwb16); + $setuphold (posedge CLK &&& WEB, negedge BWEBB[16], tbwbs, tbwbh, valid_bwb16); + $setuphold (posedge CLK &&& WEA, posedge DA[17], tdas, tdah, valid_da17); + $setuphold (posedge CLK &&& WEA, negedge DA[17], tdas, tdah, valid_da17); + $setuphold (posedge CLK &&& WEB, posedge DB[17], tdbs, tdbh, valid_db17); + $setuphold (posedge CLK &&& WEB, negedge DB[17], tdbs, tdbh, valid_db17); + + $setuphold (posedge CLK &&& WEA, posedge BWEBA[17], tbwas, tbwah, valid_bwa17); + $setuphold (posedge CLK &&& WEA, negedge BWEBA[17], tbwas, tbwah, valid_bwa17); + $setuphold (posedge CLK &&& WEB, posedge BWEBB[17], tbwbs, tbwbh, valid_bwb17); + $setuphold (posedge CLK &&& WEB, negedge BWEBB[17], tbwbs, tbwbh, valid_bwb17); + $setuphold (posedge CLK &&& WEA, posedge DA[18], tdas, tdah, valid_da18); + $setuphold (posedge CLK &&& WEA, negedge DA[18], tdas, tdah, valid_da18); + $setuphold (posedge CLK &&& WEB, posedge DB[18], tdbs, tdbh, valid_db18); + $setuphold (posedge CLK &&& WEB, negedge DB[18], tdbs, tdbh, valid_db18); + + $setuphold (posedge CLK &&& WEA, posedge BWEBA[18], tbwas, tbwah, valid_bwa18); + $setuphold (posedge CLK &&& WEA, negedge BWEBA[18], tbwas, tbwah, valid_bwa18); + $setuphold (posedge CLK &&& WEB, posedge BWEBB[18], tbwbs, tbwbh, valid_bwb18); + $setuphold (posedge CLK &&& WEB, negedge BWEBB[18], tbwbs, tbwbh, valid_bwb18); + $setuphold (posedge CLK &&& WEA, posedge DA[19], tdas, tdah, valid_da19); + $setuphold (posedge CLK &&& WEA, negedge DA[19], tdas, tdah, valid_da19); + $setuphold (posedge CLK &&& WEB, posedge DB[19], tdbs, tdbh, valid_db19); + $setuphold (posedge CLK &&& WEB, negedge DB[19], tdbs, tdbh, valid_db19); + + $setuphold (posedge CLK &&& WEA, posedge BWEBA[19], tbwas, tbwah, valid_bwa19); + $setuphold (posedge CLK &&& WEA, negedge BWEBA[19], tbwas, tbwah, valid_bwa19); + $setuphold (posedge CLK &&& WEB, posedge BWEBB[19], tbwbs, tbwbh, valid_bwb19); + $setuphold (posedge CLK &&& WEB, negedge BWEBB[19], tbwbs, tbwbh, valid_bwb19); + $setuphold (posedge CLK &&& WEA, posedge DA[20], tdas, tdah, valid_da20); + $setuphold (posedge CLK &&& WEA, negedge DA[20], tdas, tdah, valid_da20); + $setuphold (posedge CLK &&& WEB, posedge DB[20], tdbs, tdbh, valid_db20); + $setuphold (posedge CLK &&& WEB, negedge DB[20], tdbs, tdbh, valid_db20); + + $setuphold (posedge CLK &&& WEA, posedge BWEBA[20], tbwas, tbwah, valid_bwa20); + $setuphold (posedge CLK &&& WEA, negedge BWEBA[20], tbwas, tbwah, valid_bwa20); + $setuphold (posedge CLK &&& WEB, posedge BWEBB[20], tbwbs, tbwbh, valid_bwb20); + $setuphold (posedge CLK &&& WEB, negedge BWEBB[20], tbwbs, tbwbh, valid_bwb20); + $setuphold (posedge CLK &&& WEA, posedge DA[21], tdas, tdah, valid_da21); + $setuphold (posedge CLK &&& WEA, negedge DA[21], tdas, tdah, valid_da21); + $setuphold (posedge CLK &&& WEB, posedge DB[21], tdbs, tdbh, valid_db21); + $setuphold (posedge CLK &&& WEB, negedge DB[21], tdbs, tdbh, valid_db21); + + $setuphold (posedge CLK &&& WEA, posedge BWEBA[21], tbwas, tbwah, valid_bwa21); + $setuphold (posedge CLK &&& WEA, negedge BWEBA[21], tbwas, tbwah, valid_bwa21); + $setuphold (posedge CLK &&& WEB, posedge BWEBB[21], tbwbs, tbwbh, valid_bwb21); + $setuphold (posedge CLK &&& WEB, negedge BWEBB[21], tbwbs, tbwbh, valid_bwb21); + $setuphold (posedge CLK &&& WEA, posedge DA[22], tdas, tdah, valid_da22); + $setuphold (posedge CLK &&& WEA, negedge DA[22], tdas, tdah, valid_da22); + $setuphold (posedge CLK &&& WEB, posedge DB[22], tdbs, tdbh, valid_db22); + $setuphold (posedge CLK &&& WEB, negedge DB[22], tdbs, tdbh, valid_db22); + + $setuphold (posedge CLK &&& WEA, posedge BWEBA[22], tbwas, tbwah, valid_bwa22); + $setuphold (posedge CLK &&& WEA, negedge BWEBA[22], tbwas, tbwah, valid_bwa22); + $setuphold (posedge CLK &&& WEB, posedge BWEBB[22], tbwbs, tbwbh, valid_bwb22); + $setuphold (posedge CLK &&& WEB, negedge BWEBB[22], tbwbs, tbwbh, valid_bwb22); + $setuphold (posedge CLK &&& WEA, posedge DA[23], tdas, tdah, valid_da23); + $setuphold (posedge CLK &&& WEA, negedge DA[23], tdas, tdah, valid_da23); + $setuphold (posedge CLK &&& WEB, posedge DB[23], tdbs, tdbh, valid_db23); + $setuphold (posedge CLK &&& WEB, negedge DB[23], tdbs, tdbh, valid_db23); + + $setuphold (posedge CLK &&& WEA, posedge BWEBA[23], tbwas, tbwah, valid_bwa23); + $setuphold (posedge CLK &&& WEA, negedge BWEBA[23], tbwas, tbwah, valid_bwa23); + $setuphold (posedge CLK &&& WEB, posedge BWEBB[23], tbwbs, tbwbh, valid_bwb23); + $setuphold (posedge CLK &&& WEB, negedge BWEBB[23], tbwbs, tbwbh, valid_bwb23); + $setuphold (posedge CLK &&& WEA, posedge DA[24], tdas, tdah, valid_da24); + $setuphold (posedge CLK &&& WEA, negedge DA[24], tdas, tdah, valid_da24); + $setuphold (posedge CLK &&& WEB, posedge DB[24], tdbs, tdbh, valid_db24); + $setuphold (posedge CLK &&& WEB, negedge DB[24], tdbs, tdbh, valid_db24); + + $setuphold (posedge CLK &&& WEA, posedge BWEBA[24], tbwas, tbwah, valid_bwa24); + $setuphold (posedge CLK &&& WEA, negedge BWEBA[24], tbwas, tbwah, valid_bwa24); + $setuphold (posedge CLK &&& WEB, posedge BWEBB[24], tbwbs, tbwbh, valid_bwb24); + $setuphold (posedge CLK &&& WEB, negedge BWEBB[24], tbwbs, tbwbh, valid_bwb24); + $setuphold (posedge CLK &&& WEA, posedge DA[25], tdas, tdah, valid_da25); + $setuphold (posedge CLK &&& WEA, negedge DA[25], tdas, tdah, valid_da25); + $setuphold (posedge CLK &&& WEB, posedge DB[25], tdbs, tdbh, valid_db25); + $setuphold (posedge CLK &&& WEB, negedge DB[25], tdbs, tdbh, valid_db25); + + $setuphold (posedge CLK &&& WEA, posedge BWEBA[25], tbwas, tbwah, valid_bwa25); + $setuphold (posedge CLK &&& WEA, negedge BWEBA[25], tbwas, tbwah, valid_bwa25); + $setuphold (posedge CLK &&& WEB, posedge BWEBB[25], tbwbs, tbwbh, valid_bwb25); + $setuphold (posedge CLK &&& WEB, negedge BWEBB[25], tbwbs, tbwbh, valid_bwb25); + $setuphold (posedge CLK &&& WEA, posedge DA[26], tdas, tdah, valid_da26); + $setuphold (posedge CLK &&& WEA, negedge DA[26], tdas, tdah, valid_da26); + $setuphold (posedge CLK &&& WEB, posedge DB[26], tdbs, tdbh, valid_db26); + $setuphold (posedge CLK &&& WEB, negedge DB[26], tdbs, tdbh, valid_db26); + + $setuphold (posedge CLK &&& WEA, posedge BWEBA[26], tbwas, tbwah, valid_bwa26); + $setuphold (posedge CLK &&& WEA, negedge BWEBA[26], tbwas, tbwah, valid_bwa26); + $setuphold (posedge CLK &&& WEB, posedge BWEBB[26], tbwbs, tbwbh, valid_bwb26); + $setuphold (posedge CLK &&& WEB, negedge BWEBB[26], tbwbs, tbwbh, valid_bwb26); + $setuphold (posedge CLK &&& WEA, posedge DA[27], tdas, tdah, valid_da27); + $setuphold (posedge CLK &&& WEA, negedge DA[27], tdas, tdah, valid_da27); + $setuphold (posedge CLK &&& WEB, posedge DB[27], tdbs, tdbh, valid_db27); + $setuphold (posedge CLK &&& WEB, negedge DB[27], tdbs, tdbh, valid_db27); + + $setuphold (posedge CLK &&& WEA, posedge BWEBA[27], tbwas, tbwah, valid_bwa27); + $setuphold (posedge CLK &&& WEA, negedge BWEBA[27], tbwas, tbwah, valid_bwa27); + $setuphold (posedge CLK &&& WEB, posedge BWEBB[27], tbwbs, tbwbh, valid_bwb27); + $setuphold (posedge CLK &&& WEB, negedge BWEBB[27], tbwbs, tbwbh, valid_bwb27); + $setuphold (posedge CLK &&& WEA, posedge DA[28], tdas, tdah, valid_da28); + $setuphold (posedge CLK &&& WEA, negedge DA[28], tdas, tdah, valid_da28); + $setuphold (posedge CLK &&& WEB, posedge DB[28], tdbs, tdbh, valid_db28); + $setuphold (posedge CLK &&& WEB, negedge DB[28], tdbs, tdbh, valid_db28); + + $setuphold (posedge CLK &&& WEA, posedge BWEBA[28], tbwas, tbwah, valid_bwa28); + $setuphold (posedge CLK &&& WEA, negedge BWEBA[28], tbwas, tbwah, valid_bwa28); + $setuphold (posedge CLK &&& WEB, posedge BWEBB[28], tbwbs, tbwbh, valid_bwb28); + $setuphold (posedge CLK &&& WEB, negedge BWEBB[28], tbwbs, tbwbh, valid_bwb28); + $setuphold (posedge CLK &&& WEA, posedge DA[29], tdas, tdah, valid_da29); + $setuphold (posedge CLK &&& WEA, negedge DA[29], tdas, tdah, valid_da29); + $setuphold (posedge CLK &&& WEB, posedge DB[29], tdbs, tdbh, valid_db29); + $setuphold (posedge CLK &&& WEB, negedge DB[29], tdbs, tdbh, valid_db29); + + $setuphold (posedge CLK &&& WEA, posedge BWEBA[29], tbwas, tbwah, valid_bwa29); + $setuphold (posedge CLK &&& WEA, negedge BWEBA[29], tbwas, tbwah, valid_bwa29); + $setuphold (posedge CLK &&& WEB, posedge BWEBB[29], tbwbs, tbwbh, valid_bwb29); + $setuphold (posedge CLK &&& WEB, negedge BWEBB[29], tbwbs, tbwbh, valid_bwb29); + $setuphold (posedge CLK &&& WEA, posedge DA[30], tdas, tdah, valid_da30); + $setuphold (posedge CLK &&& WEA, negedge DA[30], tdas, tdah, valid_da30); + $setuphold (posedge CLK &&& WEB, posedge DB[30], tdbs, tdbh, valid_db30); + $setuphold (posedge CLK &&& WEB, negedge DB[30], tdbs, tdbh, valid_db30); + + $setuphold (posedge CLK &&& WEA, posedge BWEBA[30], tbwas, tbwah, valid_bwa30); + $setuphold (posedge CLK &&& WEA, negedge BWEBA[30], tbwas, tbwah, valid_bwa30); + $setuphold (posedge CLK &&& WEB, posedge BWEBB[30], tbwbs, tbwbh, valid_bwb30); + $setuphold (posedge CLK &&& WEB, negedge BWEBB[30], tbwbs, tbwbh, valid_bwb30); + $setuphold (posedge CLK &&& WEA, posedge DA[31], tdas, tdah, valid_da31); + $setuphold (posedge CLK &&& WEA, negedge DA[31], tdas, tdah, valid_da31); + $setuphold (posedge CLK &&& WEB, posedge DB[31], tdbs, tdbh, valid_db31); + $setuphold (posedge CLK &&& WEB, negedge DB[31], tdbs, tdbh, valid_db31); + + $setuphold (posedge CLK &&& WEA, posedge BWEBA[31], tbwas, tbwah, valid_bwa31); + $setuphold (posedge CLK &&& WEA, negedge BWEBA[31], tbwas, tbwah, valid_bwa31); + $setuphold (posedge CLK &&& WEB, posedge BWEBB[31], tbwbs, tbwbh, valid_bwb31); + $setuphold (posedge CLK &&& WEB, negedge BWEBB[31], tbwbs, tbwbh, valid_bwb31); + $setuphold (posedge CLK &&& CSA, posedge WEBA, twas, twah, valid_wea); + $setuphold (posedge CLK &&& CSA, negedge WEBA, twas, twah, valid_wea); + $setuphold (posedge CLK &&& CSB, posedge WEBB, twbs, twbh, valid_web); + $setuphold (posedge CLK &&& CSB, negedge WEBB, twbs, twbh, valid_web); + + $setuphold (posedge CLK, posedge CEBA, tcas, tcah, valid_cea); + $setuphold (posedge CLK, negedge CEBA, tcas, tcah, valid_cea); + $setuphold (posedge CLK, posedge CEBB, tcbs, tcbh, valid_ceb); + $setuphold (posedge CLK, negedge CEBB, tcbs, tcbh, valid_ceb); + + $width (negedge CLK &&& check_ceb, tckl, 0, valid_ck); + $width (posedge CLK &&& check_ceb, tckh, 0, valid_ck); + $period (posedge CLK &&& check_ceb, tcyc, valid_ck); + $period (negedge CLK &&& check_ceb, tcyc, valid_ck); + + +if(!CEBA & WEBA) (posedge CLK => (QA[0] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[0] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[1] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[1] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[2] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[2] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[3] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[3] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[4] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[4] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[5] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[5] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[6] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[6] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[7] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[7] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[8] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[8] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[9] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[9] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[10] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[10] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[11] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[11] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[12] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[12] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[13] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[13] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[14] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[14] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[15] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[15] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[16] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[16] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[17] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[17] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[18] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[18] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[19] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[19] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[20] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[20] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[21] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[21] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[22] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[22] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[23] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[23] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[24] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[24] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[25] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[25] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[26] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[26] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[27] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[27] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[28] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[28] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[29] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[29] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[30] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[30] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +if(!CEBA & WEBA) (posedge CLK => (QA[31] : 1'bx)) = (tcda,tcda,tholda,tcda,tholda,tcda); +if(!CEBB & WEBB) (posedge CLK => (QB[31] : 1'bx)) = (tcdb,tcdb,tholdb,tcdb,tholdb,tcdb); + + + + +endspecify +`endif + +initial begin + assign EN = 1; + RDA = 1; + RDB = 1; + ABL = 1'b1; + AAL = {M{1'b0}}; + BWEBAL = {N{1'b1}}; + BWEBBL = {N{1'b1}}; + CEBAL = 1'b1; + CEBBL = 1'b1; + clk_count = 0; + sd_mode = 0; + invalid_aslp = 1'b0; + invalid_bslp = 1'b0; + invalid_adslp = 1'b0; + invalid_bdslp = 1'b0; + invalid_sdwk_dslp = 1'b0; +end + +`ifdef TSMC_INITIALIZE_MEM +initial + begin +`ifdef TSMC_INITIALIZE_FORMAT_BINARY + #(INITIAL_MEM_DELAY) $readmemb(cdeFileInit, MX.mem, 0, W-1); +`else + #(INITIAL_MEM_DELAY) $readmemh(cdeFileInit, MX.mem, 0, W-1); +`endif + end +`endif // `ifdef TSMC_INITIALIZE_MEM + +`ifdef TSMC_INITIALIZE_FAULT +initial + begin +`ifdef TSMC_INITIALIZE_FORMAT_BINARY + #(INITIAL_FAULT_DELAY) $readmemb(cdeFileFault, MX.mem_fault, 0, W-1); +`else + #(INITIAL_FAULT_DELAY) $readmemh(cdeFileFault, MX.mem_fault, 0, W-1); +`endif + end +`endif // `ifdef TSMC_INITIALIZE_FAULT + + +always @(bRTSEL) begin + if (bSLP === 1'b0 && bDSLP === 1'b0 && bSD === 1'b0) begin + if(($realtime > 0) && (!CEBAL || !CEBBL) ) begin +`ifdef no_warning +`else + $display("\tWarning %m : input RTSEL should not be toggled when CEBA/CEBB is low at simulation time %t\n", $realtime); +`endif + `ifdef TSMC_CM_UNIT_DELAY + #(SRAM_DELAY); + `endif + bQA = {N{1'bx}}; + bQB = {N{1'bx}}; + xMemoryAll; + end + end +end +always @(bWTSEL) begin + if (bSLP === 1'b0 && bDSLP === 1'b0 && bSD === 1'b0) begin + if(($realtime > 0) && (!CEBAL || !CEBBL) ) begin +`ifdef no_warning +`else + $display("\tWarning %m : input WTSEL should not be toggled when CEBA/CEBB is low at simulation time %t\n", $realtime); +`endif + `ifdef TSMC_CM_UNIT_DELAY + #(SRAM_DELAY); + `endif + bQA = {N{1'bx}}; + bQB = {N{1'bx}}; + xMemoryAll; + end + end +end +always @(bPTSEL) begin + if (bSLP === 1'b0 && bDSLP === 1'b0 && bSD === 1'b0) begin + if(($realtime > 0) && (!CEBAL || !CEBBL) ) begin +`ifdef no_warning +`else + $display("\tWarning %m : input PTSEL should not be toggled when CEBA/CEBB is low at simulation time %t\n", $realtime); +`endif + `ifdef TSMC_CM_UNIT_DELAY + #(SRAM_DELAY); + `endif + bQA = {N{1'bx}}; + bQB = {N{1'bx}}; + xMemoryAll; + end + end +end + +`ifdef TSMC_NO_TESTPINS_WARNING +`else +always @(bCLKA or bCLKB or bRTSEL) +begin + if(bSLP === 1'b0 && bDSLP === 1'b0 && bSD === 1'b0) begin + if((bRTSEL !== 2'b00) && ($realtime > 0)) + begin + $display("\tError %m : input RTSEL should be set to 2'b00 at simulation time %t\n", $realtime); + $display("\tError %m : Please refer the datasheet for the RTSEL setting in the different segment and mux configuration\n"); + bQA <= #0.01 {N{1'bx}}; + bQB <= #0.01 {N{1'bx}}; + AAL <= {M{1'bx}}; + BWEBAL <= {N{1'b0}}; + end + end +end + +always @(bCLKA or bCLKB or bWTSEL) +begin + if(bSLP === 1'b0 && bDSLP === 1'b0 && bSD === 1'b0) begin + if((bWTSEL !== 2'b00) && ($realtime > 0)) + begin + $display("\tError %m : input WTSEL should be set to 2'b00 at simulation time %t\n", $realtime); + $display("\tError %m : Please refer the datasheet for the WTSEL setting in the different segment and mux configuration\n"); + bQA <= #0.01 {N{1'bx}}; + bQB <= #0.01 {N{1'bx}}; + AAL <= {M{1'bx}}; + BWEBAL <= {N{1'b0}}; + end + end +end + +always @(bCLKA or bCLKB or bPTSEL) +begin + if(bSLP === 1'b0 && bDSLP === 1'b0 && bSD === 1'b0) begin + if((bPTSEL !== 2'b00) && ($realtime > 0)) + begin + $display("\tError %m : input PTSEL should be set to 2'b00 at simulation time %t\n", $realtime); + $display("\tError %m : Please refer the datasheet for the PTSEL setting in the different segment and mux configuration\n"); + bQA <= #0.01 {N{1'bx}}; + bQB <= #0.01 {N{1'bx}}; + AAL <= {M{1'bx}}; + BWEBAL <= {N{1'b0}}; + end + end +end + +`endif + +//always @(bTMA or bTMB) begin +// if(bSLP === 1'b0 && bDSLP === 1'b0 && bSD === 1'b0 && bTMA === 1'b1 && bTMB === 1'b1) begin +// if( MES_ALL=="ON" && $realtime != 0) +// begin +// $display("\nWarning %m : TMA and TMB cannot both be 1 at the same time, at %t. >>", $realtime); +// end +// xMemoryAll; +//`ifdef TSMC_CM_UNIT_DELAY +// bQA <= #(SRAM_DELAY + 0.001) {N{1'bx}}; +// bQB <= #(SRAM_DELAY + 0.001) {N{1'bx}}; +//`else +// bQA <= #0.01 {N{1'bx}}; +// bQB <= #0.01 {N{1'bx}}; +//`endif +// end +//end + +always @(bCLKA) +begin : CLKAOP + if(bSLP === 1'b0 && bDSLP === 1'b0 && bSD === 1'b0 && invalid_sdwk_dslp === 1'b0) begin + if(bCLKA === 1'bx) + begin + if( MES_ALL=="ON" && $realtime != 0) + begin + $display("\nWarning %m : CLK unknown at %t. >>", $realtime); + end + xMemoryAll; + bQA <= #0.01 {N{1'bx}}; + end + else if(bCLKA === 1'b1 && RCLKA === 1'b0) + begin + if(bCEBA === 1'bx) + begin + if( MES_ALL=="ON" && $realtime != 0) + begin + $display("\nWarning %m CEBA unknown at %t. >>", $realtime); + end + xMemoryAll; + bQA <= #0.01 {N{1'bx}}; + end + else if(bWEBA === 1'bx && bCEBA === 1'b0) + begin + if( MES_ALL=="ON" && $realtime != 0) + begin + $display("\nWarning %m WEBA unknown at %t. >>", $realtime); + end + xMemoryAll; + bQA <= #0.01 {N{1'bx}}; + end + else begin + WEBAL = bWEBA; + CEBAL = bCEBA; + if(^bAA === 1'bx && bWEBA === 1'b0 && bCEBA === 1'b0) + begin + if( MES_ALL=="ON" && $realtime != 0) + begin + $display("\nWarning %m WRITE AA unknown at %t. >>", $realtime); + end + xMemoryAll; + end + else if(^bAA === 1'bx && bWEBA === 1'b1 && bCEBA === 1'b0) + begin + if( MES_ALL=="ON" && $realtime != 0) + begin + $display("\nWarning %m READ AA unknown at %t. >>", $realtime); + end + xMemoryAll; + bQA <= #0.01 {N{1'bx}}; + end + else + begin + if(!bCEBA) + begin // begin if(bCEBA) + AAL = bAA; + DAL = bDA; + if(bWEBA === 1'b1 && clk_count == 0) + begin + RDA = ~RDA; + end + if(bWEBA === 1'b0) + begin + for (i = 0; i < N; i = i + 1) + begin + if(!bBWEBA[i] && !bWEBA) + begin + BWEBAL[i] = 1'b0; + end + if(bWEBA === 1'bx || bBWEBA[i] === 1'bx) + begin + BWEBAL[i] = 1'b0; + DAL[i] = 1'bx; + end + end + if(^bBWEBA === 1'bx) + begin + if( MES_ALL=="ON" && $realtime != 0) + begin + $display("\nWarning %m BWEBA unknown at %t. >>", $realtime); + end + end + end + end + end + end + + CEBBL = bCEBB; + if(bCEBB === 1'b0) begin + WEBBL = bWEBB; + ABL = bAB; + bBWEBBL = bBWEBB; + bDBL = bDB; + end + #0.001; + + if(CEBBL === 1'bx) + begin + if( MES_ALL=="ON" && $realtime != 0) + begin + $display("\nWarning %m CEBB unknown at %t. >>", $realtime); + end + xMemoryAll; + bQB <= #0.01 {N{1'bx}}; + end + else if(WEBBL === 1'bx && CEBBL === 1'b0) + begin + if( MES_ALL=="ON" && $realtime != 0) + begin + $display("\nWarning %m WEBB unknown at %t. >>", $realtime); + end + xMemoryAll; + bQB <= #0.01 {N{1'bx}}; + end + else + begin + if(^ABL === 1'bx && WEBBL === 1'b0 && CEBBL === 1'b0) + begin + if( MES_ALL=="ON" && $realtime != 0) + begin + $display("\nWarning %m WRITE AB unknown at %t. >>", $realtime); + end + xMemoryAll; + end + else if(^ABL === 1'bx && WEBBL === 1'b1 && CEBBL === 1'b0) + begin + if( MES_ALL=="ON" && $realtime != 0) + begin + $display("\nWarning %m READ AB unknown at %t. >>", $realtime); + end + xMemoryAll; + bQB <= #0.01 {N{1'bx}}; + end + else begin + if(!CEBBL) + begin // begin if(CEBBL) + DBL = bDBL; + if(WEBBL === 1'b1 && clk_count == 0) + begin + RDB = ~RDB; + end + if(WEBBL !== 1'b1) + begin + for (i = 0; i < N; i = i + 1) + begin + if(!bBWEBBL[i] && !WEBBL) + begin + BWEBBL[i] = 1'b0; + end + if(WEBBL === 1'bx || bBWEBBL[i] === 1'bx) + begin + BWEBBL[i] = 1'b0; + DBL[i] = 1'bx; + end + end + if(^bBWEBBL === 1'bx) + begin + if( MES_ALL=="ON" && $realtime != 0) + begin + $display("\nWarning %m BWEBB unknown at %t. >>", $realtime); + end + end + end + end + end + end + end + end + #0.001 RCLKA = bCLKA; + +end + + + +always @(RDA or QAL) +begin : CLKAROP + if(bSLP === 1'b0 && bDSLP === 1'b0 && bSD === 1'b0 && invalid_sdwk_dslp === 1'b0 && bAWT === 1'b0) begin + if(!CEBAL && WEBAL && clk_count == 0) + begin + begin +`ifdef TSMC_CM_UNIT_DELAY + #(SRAM_DELAY); +`else + bQA = {N{1'bx}}; + #0.01; +`endif + bQA <= QAL; + end + end // if(!CEBAL && WEBAL && clk_count == 0) + end +end // always @ (RDA or QAL) + +always @(RDB or QBL) +begin : CLKBROP + if(bSLP === 1'b0 && bDSLP === 1'b0 && bSD === 1'b0 && invalid_sdwk_dslp === 1'b0 && bAWT === 1'b0) begin + if(!CEBBL && WEBBL && clk_count == 0) + begin + begin +`ifdef TSMC_CM_UNIT_DELAY + #(SRAM_DELAY); +`else + bQB = {N{1'bx}}; + #0.01; +`endif + bQB <= QBL; + end + end // if(!bAWT && !CEBBL && WEBBL && clk_count == 0) + end +end // always @ (RDB or QBL) + + + + + +always @(BWEBAL) +begin + BWEBAL = #0.01 {N{1'b1}}; +end + +always @(BWEBBL) +begin + BWEBBL = #0.01 {N{1'b1}}; +end + + +`ifdef TSMC_CM_UNIT_DELAY +`else +always @(valid_testpin) begin + AAL <= {M{1'bx}}; + BWEBAL <= {N{1'b0}}; + BWEBBL <= {N{1'b0}}; + bQA = #0.01 {N{1'bx}}; + bQB = #0.01 {N{1'bx}}; +end + + +always @(valid_ck) +begin + if (iCEBA === 1'b0) begin + #0.002; + AAL = {M{1'bx}}; + BWEBAL = {N{1'b0}}; + bQA = #0.01 {N{1'bx}}; + end + + if (iCEBB === 1'b0) begin + #0.002; + ABL = {M{1'bx}}; + BWEBBL = {N{1'b0}}; + bQB = #0.01 {N{1'bx}}; + end +end + + +always @(valid_cka) +begin + + #0.002; + AAL = {M{1'bx}}; + BWEBAL = {N{1'b0}}; + bQA = #0.01 {N{1'bx}}; +end + +always @(valid_ckb) +begin + + #0.002; + ABL = {M{1'bx}}; + BWEBBL = {N{1'b0}}; + bQB = #0.01 {N{1'bx}}; +end + + +always @(valid_aa) +begin + + if(!WEBAL) + begin + #0.002; + BWEBAL = {N{1'b0}}; + AAL = {M{1'bx}}; + end + else + begin + #0.002; + BWEBAL = {N{1'b0}}; + AAL = {M{1'bx}}; + bQA = #0.01 {N{1'bx}}; + end +end + +always @(valid_ab) +begin + + if(!WEBBL) + begin + BWEBBL = {N{1'b0}}; + ABL = {M{1'bx}}; + end + else + begin + #0.002; + BWEBBL = {N{1'b0}}; + ABL = {M{1'bx}}; + bQB = #0.01 {N{1'bx}}; + end +end + +always @(valid_da0) +begin + + DAL[0] = 1'bx; + BWEBAL[0] = 1'b0; +end + +always @(valid_db0) +begin + disable CLKAOP; + DBL[0] = 1'bx; + BWEBBL[0] = 1'b0; +end + +always @(valid_bwa0) +begin + + DAL[0] = 1'bx; + BWEBAL[0] = 1'b0; +end + +always @(valid_bwb0) +begin + disable CLKAOP; + DBL[0] = 1'bx; + BWEBBL[0] = 1'b0; +end +always @(valid_da1) +begin + + DAL[1] = 1'bx; + BWEBAL[1] = 1'b0; +end + +always @(valid_db1) +begin + disable CLKAOP; + DBL[1] = 1'bx; + BWEBBL[1] = 1'b0; +end + +always @(valid_bwa1) +begin + + DAL[1] = 1'bx; + BWEBAL[1] = 1'b0; +end + +always @(valid_bwb1) +begin + disable CLKAOP; + DBL[1] = 1'bx; + BWEBBL[1] = 1'b0; +end +always @(valid_da2) +begin + + DAL[2] = 1'bx; + BWEBAL[2] = 1'b0; +end + +always @(valid_db2) +begin + disable CLKAOP; + DBL[2] = 1'bx; + BWEBBL[2] = 1'b0; +end + +always @(valid_bwa2) +begin + + DAL[2] = 1'bx; + BWEBAL[2] = 1'b0; +end + +always @(valid_bwb2) +begin + disable CLKAOP; + DBL[2] = 1'bx; + BWEBBL[2] = 1'b0; +end +always @(valid_da3) +begin + + DAL[3] = 1'bx; + BWEBAL[3] = 1'b0; +end + +always @(valid_db3) +begin + disable CLKAOP; + DBL[3] = 1'bx; + BWEBBL[3] = 1'b0; +end + +always @(valid_bwa3) +begin + + DAL[3] = 1'bx; + BWEBAL[3] = 1'b0; +end + +always @(valid_bwb3) +begin + disable CLKAOP; + DBL[3] = 1'bx; + BWEBBL[3] = 1'b0; +end +always @(valid_da4) +begin + + DAL[4] = 1'bx; + BWEBAL[4] = 1'b0; +end + +always @(valid_db4) +begin + disable CLKAOP; + DBL[4] = 1'bx; + BWEBBL[4] = 1'b0; +end + +always @(valid_bwa4) +begin + + DAL[4] = 1'bx; + BWEBAL[4] = 1'b0; +end + +always @(valid_bwb4) +begin + disable CLKAOP; + DBL[4] = 1'bx; + BWEBBL[4] = 1'b0; +end +always @(valid_da5) +begin + + DAL[5] = 1'bx; + BWEBAL[5] = 1'b0; +end + +always @(valid_db5) +begin + disable CLKAOP; + DBL[5] = 1'bx; + BWEBBL[5] = 1'b0; +end + +always @(valid_bwa5) +begin + + DAL[5] = 1'bx; + BWEBAL[5] = 1'b0; +end + +always @(valid_bwb5) +begin + disable CLKAOP; + DBL[5] = 1'bx; + BWEBBL[5] = 1'b0; +end +always @(valid_da6) +begin + + DAL[6] = 1'bx; + BWEBAL[6] = 1'b0; +end + +always @(valid_db6) +begin + disable CLKAOP; + DBL[6] = 1'bx; + BWEBBL[6] = 1'b0; +end + +always @(valid_bwa6) +begin + + DAL[6] = 1'bx; + BWEBAL[6] = 1'b0; +end + +always @(valid_bwb6) +begin + disable CLKAOP; + DBL[6] = 1'bx; + BWEBBL[6] = 1'b0; +end +always @(valid_da7) +begin + + DAL[7] = 1'bx; + BWEBAL[7] = 1'b0; +end + +always @(valid_db7) +begin + disable CLKAOP; + DBL[7] = 1'bx; + BWEBBL[7] = 1'b0; +end + +always @(valid_bwa7) +begin + + DAL[7] = 1'bx; + BWEBAL[7] = 1'b0; +end + +always @(valid_bwb7) +begin + disable CLKAOP; + DBL[7] = 1'bx; + BWEBBL[7] = 1'b0; +end +always @(valid_da8) +begin + + DAL[8] = 1'bx; + BWEBAL[8] = 1'b0; +end + +always @(valid_db8) +begin + disable CLKAOP; + DBL[8] = 1'bx; + BWEBBL[8] = 1'b0; +end + +always @(valid_bwa8) +begin + + DAL[8] = 1'bx; + BWEBAL[8] = 1'b0; +end + +always @(valid_bwb8) +begin + disable CLKAOP; + DBL[8] = 1'bx; + BWEBBL[8] = 1'b0; +end +always @(valid_da9) +begin + + DAL[9] = 1'bx; + BWEBAL[9] = 1'b0; +end + +always @(valid_db9) +begin + disable CLKAOP; + DBL[9] = 1'bx; + BWEBBL[9] = 1'b0; +end + +always @(valid_bwa9) +begin + + DAL[9] = 1'bx; + BWEBAL[9] = 1'b0; +end + +always @(valid_bwb9) +begin + disable CLKAOP; + DBL[9] = 1'bx; + BWEBBL[9] = 1'b0; +end +always @(valid_da10) +begin + + DAL[10] = 1'bx; + BWEBAL[10] = 1'b0; +end + +always @(valid_db10) +begin + disable CLKAOP; + DBL[10] = 1'bx; + BWEBBL[10] = 1'b0; +end + +always @(valid_bwa10) +begin + + DAL[10] = 1'bx; + BWEBAL[10] = 1'b0; +end + +always @(valid_bwb10) +begin + disable CLKAOP; + DBL[10] = 1'bx; + BWEBBL[10] = 1'b0; +end +always @(valid_da11) +begin + + DAL[11] = 1'bx; + BWEBAL[11] = 1'b0; +end + +always @(valid_db11) +begin + disable CLKAOP; + DBL[11] = 1'bx; + BWEBBL[11] = 1'b0; +end + +always @(valid_bwa11) +begin + + DAL[11] = 1'bx; + BWEBAL[11] = 1'b0; +end + +always @(valid_bwb11) +begin + disable CLKAOP; + DBL[11] = 1'bx; + BWEBBL[11] = 1'b0; +end +always @(valid_da12) +begin + + DAL[12] = 1'bx; + BWEBAL[12] = 1'b0; +end + +always @(valid_db12) +begin + disable CLKAOP; + DBL[12] = 1'bx; + BWEBBL[12] = 1'b0; +end + +always @(valid_bwa12) +begin + + DAL[12] = 1'bx; + BWEBAL[12] = 1'b0; +end + +always @(valid_bwb12) +begin + disable CLKAOP; + DBL[12] = 1'bx; + BWEBBL[12] = 1'b0; +end +always @(valid_da13) +begin + + DAL[13] = 1'bx; + BWEBAL[13] = 1'b0; +end + +always @(valid_db13) +begin + disable CLKAOP; + DBL[13] = 1'bx; + BWEBBL[13] = 1'b0; +end + +always @(valid_bwa13) +begin + + DAL[13] = 1'bx; + BWEBAL[13] = 1'b0; +end + +always @(valid_bwb13) +begin + disable CLKAOP; + DBL[13] = 1'bx; + BWEBBL[13] = 1'b0; +end +always @(valid_da14) +begin + + DAL[14] = 1'bx; + BWEBAL[14] = 1'b0; +end + +always @(valid_db14) +begin + disable CLKAOP; + DBL[14] = 1'bx; + BWEBBL[14] = 1'b0; +end + +always @(valid_bwa14) +begin + + DAL[14] = 1'bx; + BWEBAL[14] = 1'b0; +end + +always @(valid_bwb14) +begin + disable CLKAOP; + DBL[14] = 1'bx; + BWEBBL[14] = 1'b0; +end +always @(valid_da15) +begin + + DAL[15] = 1'bx; + BWEBAL[15] = 1'b0; +end + +always @(valid_db15) +begin + disable CLKAOP; + DBL[15] = 1'bx; + BWEBBL[15] = 1'b0; +end + +always @(valid_bwa15) +begin + + DAL[15] = 1'bx; + BWEBAL[15] = 1'b0; +end + +always @(valid_bwb15) +begin + disable CLKAOP; + DBL[15] = 1'bx; + BWEBBL[15] = 1'b0; +end +always @(valid_da16) +begin + + DAL[16] = 1'bx; + BWEBAL[16] = 1'b0; +end + +always @(valid_db16) +begin + disable CLKAOP; + DBL[16] = 1'bx; + BWEBBL[16] = 1'b0; +end + +always @(valid_bwa16) +begin + + DAL[16] = 1'bx; + BWEBAL[16] = 1'b0; +end + +always @(valid_bwb16) +begin + disable CLKAOP; + DBL[16] = 1'bx; + BWEBBL[16] = 1'b0; +end +always @(valid_da17) +begin + + DAL[17] = 1'bx; + BWEBAL[17] = 1'b0; +end + +always @(valid_db17) +begin + disable CLKAOP; + DBL[17] = 1'bx; + BWEBBL[17] = 1'b0; +end + +always @(valid_bwa17) +begin + + DAL[17] = 1'bx; + BWEBAL[17] = 1'b0; +end + +always @(valid_bwb17) +begin + disable CLKAOP; + DBL[17] = 1'bx; + BWEBBL[17] = 1'b0; +end +always @(valid_da18) +begin + + DAL[18] = 1'bx; + BWEBAL[18] = 1'b0; +end + +always @(valid_db18) +begin + disable CLKAOP; + DBL[18] = 1'bx; + BWEBBL[18] = 1'b0; +end + +always @(valid_bwa18) +begin + + DAL[18] = 1'bx; + BWEBAL[18] = 1'b0; +end + +always @(valid_bwb18) +begin + disable CLKAOP; + DBL[18] = 1'bx; + BWEBBL[18] = 1'b0; +end +always @(valid_da19) +begin + + DAL[19] = 1'bx; + BWEBAL[19] = 1'b0; +end + +always @(valid_db19) +begin + disable CLKAOP; + DBL[19] = 1'bx; + BWEBBL[19] = 1'b0; +end + +always @(valid_bwa19) +begin + + DAL[19] = 1'bx; + BWEBAL[19] = 1'b0; +end + +always @(valid_bwb19) +begin + disable CLKAOP; + DBL[19] = 1'bx; + BWEBBL[19] = 1'b0; +end +always @(valid_da20) +begin + + DAL[20] = 1'bx; + BWEBAL[20] = 1'b0; +end + +always @(valid_db20) +begin + disable CLKAOP; + DBL[20] = 1'bx; + BWEBBL[20] = 1'b0; +end + +always @(valid_bwa20) +begin + + DAL[20] = 1'bx; + BWEBAL[20] = 1'b0; +end + +always @(valid_bwb20) +begin + disable CLKAOP; + DBL[20] = 1'bx; + BWEBBL[20] = 1'b0; +end +always @(valid_da21) +begin + + DAL[21] = 1'bx; + BWEBAL[21] = 1'b0; +end + +always @(valid_db21) +begin + disable CLKAOP; + DBL[21] = 1'bx; + BWEBBL[21] = 1'b0; +end + +always @(valid_bwa21) +begin + + DAL[21] = 1'bx; + BWEBAL[21] = 1'b0; +end + +always @(valid_bwb21) +begin + disable CLKAOP; + DBL[21] = 1'bx; + BWEBBL[21] = 1'b0; +end +always @(valid_da22) +begin + + DAL[22] = 1'bx; + BWEBAL[22] = 1'b0; +end + +always @(valid_db22) +begin + disable CLKAOP; + DBL[22] = 1'bx; + BWEBBL[22] = 1'b0; +end + +always @(valid_bwa22) +begin + + DAL[22] = 1'bx; + BWEBAL[22] = 1'b0; +end + +always @(valid_bwb22) +begin + disable CLKAOP; + DBL[22] = 1'bx; + BWEBBL[22] = 1'b0; +end +always @(valid_da23) +begin + + DAL[23] = 1'bx; + BWEBAL[23] = 1'b0; +end + +always @(valid_db23) +begin + disable CLKAOP; + DBL[23] = 1'bx; + BWEBBL[23] = 1'b0; +end + +always @(valid_bwa23) +begin + + DAL[23] = 1'bx; + BWEBAL[23] = 1'b0; +end + +always @(valid_bwb23) +begin + disable CLKAOP; + DBL[23] = 1'bx; + BWEBBL[23] = 1'b0; +end +always @(valid_da24) +begin + + DAL[24] = 1'bx; + BWEBAL[24] = 1'b0; +end + +always @(valid_db24) +begin + disable CLKAOP; + DBL[24] = 1'bx; + BWEBBL[24] = 1'b0; +end + +always @(valid_bwa24) +begin + + DAL[24] = 1'bx; + BWEBAL[24] = 1'b0; +end + +always @(valid_bwb24) +begin + disable CLKAOP; + DBL[24] = 1'bx; + BWEBBL[24] = 1'b0; +end +always @(valid_da25) +begin + + DAL[25] = 1'bx; + BWEBAL[25] = 1'b0; +end + +always @(valid_db25) +begin + disable CLKAOP; + DBL[25] = 1'bx; + BWEBBL[25] = 1'b0; +end + +always @(valid_bwa25) +begin + + DAL[25] = 1'bx; + BWEBAL[25] = 1'b0; +end + +always @(valid_bwb25) +begin + disable CLKAOP; + DBL[25] = 1'bx; + BWEBBL[25] = 1'b0; +end +always @(valid_da26) +begin + + DAL[26] = 1'bx; + BWEBAL[26] = 1'b0; +end + +always @(valid_db26) +begin + disable CLKAOP; + DBL[26] = 1'bx; + BWEBBL[26] = 1'b0; +end + +always @(valid_bwa26) +begin + + DAL[26] = 1'bx; + BWEBAL[26] = 1'b0; +end + +always @(valid_bwb26) +begin + disable CLKAOP; + DBL[26] = 1'bx; + BWEBBL[26] = 1'b0; +end +always @(valid_da27) +begin + + DAL[27] = 1'bx; + BWEBAL[27] = 1'b0; +end + +always @(valid_db27) +begin + disable CLKAOP; + DBL[27] = 1'bx; + BWEBBL[27] = 1'b0; +end + +always @(valid_bwa27) +begin + + DAL[27] = 1'bx; + BWEBAL[27] = 1'b0; +end + +always @(valid_bwb27) +begin + disable CLKAOP; + DBL[27] = 1'bx; + BWEBBL[27] = 1'b0; +end +always @(valid_da28) +begin + + DAL[28] = 1'bx; + BWEBAL[28] = 1'b0; +end + +always @(valid_db28) +begin + disable CLKAOP; + DBL[28] = 1'bx; + BWEBBL[28] = 1'b0; +end + +always @(valid_bwa28) +begin + + DAL[28] = 1'bx; + BWEBAL[28] = 1'b0; +end + +always @(valid_bwb28) +begin + disable CLKAOP; + DBL[28] = 1'bx; + BWEBBL[28] = 1'b0; +end +always @(valid_da29) +begin + + DAL[29] = 1'bx; + BWEBAL[29] = 1'b0; +end + +always @(valid_db29) +begin + disable CLKAOP; + DBL[29] = 1'bx; + BWEBBL[29] = 1'b0; +end + +always @(valid_bwa29) +begin + + DAL[29] = 1'bx; + BWEBAL[29] = 1'b0; +end + +always @(valid_bwb29) +begin + disable CLKAOP; + DBL[29] = 1'bx; + BWEBBL[29] = 1'b0; +end +always @(valid_da30) +begin + + DAL[30] = 1'bx; + BWEBAL[30] = 1'b0; +end + +always @(valid_db30) +begin + disable CLKAOP; + DBL[30] = 1'bx; + BWEBBL[30] = 1'b0; +end + +always @(valid_bwa30) +begin + + DAL[30] = 1'bx; + BWEBAL[30] = 1'b0; +end + +always @(valid_bwb30) +begin + disable CLKAOP; + DBL[30] = 1'bx; + BWEBBL[30] = 1'b0; +end +always @(valid_da31) +begin + + DAL[31] = 1'bx; + BWEBAL[31] = 1'b0; +end + +always @(valid_db31) +begin + disable CLKAOP; + DBL[31] = 1'bx; + BWEBBL[31] = 1'b0; +end + +always @(valid_bwa31) +begin + + DAL[31] = 1'bx; + BWEBAL[31] = 1'b0; +end + +always @(valid_bwb31) +begin + disable CLKAOP; + DBL[31] = 1'bx; + BWEBBL[31] = 1'b0; +end + +always @(valid_cea) +begin + + #0.002; + BWEBAL = {N{1'b0}}; + AAL = {M{1'bx}}; + bQA = #0.01 {N{1'bx}}; +end + +always @(valid_ceb) +begin + + #0.002; + BWEBBL = {N{1'b0}}; + ABL = {M{1'bx}}; + bQB = #0.01 {N{1'bx}}; +end + +always @(valid_wea) +begin + #0.002; + BWEBAL = {N{1'b0}}; + AAL = {M{1'bx}}; + bQA = #0.01 {N{1'bx}}; +end + +always @(valid_web) +begin + #0.002; + BWEBBL = {N{1'b0}}; + ABL = {M{1'bx}}; + bQB = #0.01 {N{1'bx}}; +end + +`endif + +// Task for printing the memory between specified addresses.. +task printMemoryFromTo; + input [M - 1:0] from; // memory content are printed, start from this address. + input [M - 1:0] to; // memory content are printed, end at this address. + begin + MX.printMemoryFromTo(from, to); + end +endtask + +// Task for printing entire memory, including normal array and redundancy array. +task printMemory; + begin + MX.printMemory; + end +endtask + +task xMemoryAll; + begin + MX.xMemoryAll; + end +endtask + +task zeroMemoryAll; + begin + MX.zeroMemoryAll; + end +endtask + +// Task for Loading a perdefined set of data from an external file. +task preloadData; + input [256*8:1] infile; // Max 256 character File Name + begin + MX.preloadData(infile); + end +endtask + +tsdn28hpcpuhdb64x32m4mw_170a_Int_Array #(2,2,W,N,M,MES_ALL) MX (.D({DAL,DBL}),.BW({BWEBAL,BWEBBL}), + .AW({AAL,ABL}),.EN(EN),.AAR(AAL),.ABR(ABL),.RDA(RDA),.RDB(RDB),.QA(QAL),.QB(QBL)); + +endmodule + + `disable_portfaults + `nosuppress_faults + `endcelldefine + + /* + The module ports are parameterizable vectors. + */ + module tsdn28hpcpuhdb64x32m4mw_170a_Int_Array (D, BW, AW, EN, AAR, ABR, RDA, RDB, QA, QB); + parameter Nread = 2; // Number of Read Ports + parameter Nwrite = 2; // Number of Write Ports + parameter Nword = 2; // Number of Words + parameter Ndata = 1; // Number of Data Bits / Word + parameter Naddr = 1; // Number of Address Bits / Word + parameter MES_ALL = "ON"; + parameter dly = 0.000; + // Cannot define inputs/outputs as memories + input [Ndata*Nwrite-1:0] D; // Data Word(s) + input [Ndata*Nwrite-1:0] BW; // Negative Bit Write Enable + input [Naddr*Nwrite-1:0] AW; // Write Address(es) + input EN; // Positive Write Enable + input RDA; // Positive Write Enable + input RDB; // Positive Write Enable + input [Naddr-1:0] AAR; // Read Address(es) + input [Naddr-1:0] ABR; // Read Address(es) + output [Ndata-1:0] QA; // Output Data Word(s) + output [Ndata-1:0] QB; // Output Data Word(s) + reg [Ndata-1:0] QA; + reg [Ndata-1:0] QB; + reg [Ndata-1:0] mem [Nword-1:0]; + reg [Ndata-1:0] mem_fault [Nword-1:0]; + reg chgmem; // Toggled when write to mem + reg [Nwrite-1:0] wwe; // Positive Word Write Enable for each Port + reg we; // Positive Write Enable for all Ports + integer waddr[Nwrite-1:0]; // Write Address for each Enabled Port + integer address; // Current address + reg [Naddr-1:0] abuf; // Address of current port + reg [Ndata-1:0] dbuf; // Data for current port + reg [Naddr-1:0] abuf_ra; // Address of current port + reg [Ndata-1:0] dbuf_ra; // Data for current port + reg [Naddr-1:0] abuf_rb; // Address of current port + reg [Ndata-1:0] dbuf_rb; // Data for current port + reg [Ndata-1:0] bwbuf; // Bit Write enable for current port + reg dup; // Is the address a duplicate? + integer log; // Log file descriptor + integer ip, ip2, ib, iba_r, ibb_r, iw, iwb, i; // Vector indices + + + initial + begin + if(log[0] === 1'bx) + log = 1; + chgmem = 1'b0; + end + + + always @(D or BW or AW or EN) + begin: WRITE //{ + if(EN !== 1'b0) + begin //{ Possible write + we = 1'b0; + // Mark any write enabled ports & get write addresses + for (ip = 0 ; ip < Nwrite ; ip = ip + 1) + begin //{ + ib = ip * Ndata; + iw = ib + Ndata; + while (ib < iw && BW[ib] === 1'b1) + begin + ib = ib + 1; + end + if(ib == iw) + begin + wwe[ip] = 1'b0; + end + else + begin //{ ip write enabled + iw = ip * Naddr; + for (ib = 0 ; ib < Naddr ; ib = ib + 1) + begin //{ + abuf[ib] = AW[iw+ib]; + if(abuf[ib] !== 1'b0 && abuf[ib] !== 1'b1) + begin + ib = Naddr; + end + end //} + if(ib == Naddr) + begin //{ + if(abuf < Nword) + begin //{ Valid address + waddr[ip] = abuf; + wwe[ip] = 1'b1; + if(we == 1'b0) + begin + chgmem = ~chgmem; + we = EN; + end + end //} + else + begin //{ Out of range address + wwe[ip] = 1'b0; + if( MES_ALL=="ON" && $realtime != 0) + $fdisplay (log, + "\nWarning! Int_Array instance, %m:", + "\n\t Port %0d", ip, + " write address x'%0h'", abuf, + " out of range at time %t.", $realtime, + "\n\t Port %0d data not written to memory.", ip); + end //} + end //} + else + begin //{ unknown write address + for (ib = 0 ; ib < Ndata ; ib = ib + 1) + begin + dbuf[ib] = 1'bx; + end + for (iw = 0 ; iw < Nword ; iw = iw + 1) + begin + mem[iw] = dbuf; + end + chgmem = ~chgmem; + disable WRITE; + end //} + end //} ip write enabled + end //} for ip + if(we === 1'b1) + begin //{ active write enable + for (ip = 0 ; ip < Nwrite ; ip = ip + 1) + begin //{ + if(wwe[ip]) + begin //{ write enabled bits of write port ip + address = waddr[ip]; + dbuf = mem[address]; + iw = ip * Ndata; + for (ib = 0 ; ib < Ndata ; ib = ib + 1) + begin //{ + iwb = iw + ib; + if(BW[iwb] === 1'b0) + begin + dbuf[ib] = D[iwb]; + end + else + if(BW[iwb] !== 1'b1) + begin + dbuf[ib] = 1'bx; + end + end //} + // Check other ports for same address & + // common write enable bits active + dup = 0; + for (ip2 = ip + 1 ; ip2 < Nwrite ; ip2 = ip2 + 1) + begin //{ + if(wwe[ip2] && address == waddr[ip2]) + begin //{ + // initialize bwbuf if first dup + if(!dup) + begin + for (ib = 0 ; ib < Ndata ; ib = ib + 1) + begin + bwbuf[ib] = BW[iw+ib]; + end + dup = 1; + end + iw = ip2 * Ndata; + for (ib = 0 ; ib < Ndata ; ib = ib + 1) + begin //{ + iwb = iw + ib; + // New: Always set X if BW X + if(BW[iwb] === 1'b0) + begin //{ + if(bwbuf[ib] !== 1'b1) + begin + if(D[iwb] !== dbuf[ib]) + begin + dbuf[ib] = 1'bx; + end + end + else + begin + dbuf[ib] = D[iwb]; + bwbuf[ib] = 1'b0; + end + end //} + else if(BW[iwb] !== 1'b1) + begin + dbuf[ib] = 1'bx; + bwbuf[ib] = 1'bx; + end + end //} for each bit + wwe[ip2] = 1'b0; + end //} Port ip2 address matches port ip + end //} for each port beyond ip (ip2=ip+1) + // Write dbuf to memory + mem[address] = dbuf; + end //} wwe[ip] - write port ip enabled + end //} for each write port ip + end //} active write enable + else if(we !== 1'b0) + begin //{ unknown write enable + for (ip = 0 ; ip < Nwrite ; ip = ip + 1) + begin //{ + if(wwe[ip]) + begin //{ write X to enabled bits of write port ip + address = waddr[ip]; + dbuf = mem[address]; + iw = ip * Ndata; + for (ib = 0 ; ib < Ndata ; ib = ib + 1) + begin //{ + if(BW[iw+ib] !== 1'b1) + begin + dbuf[ib] = 1'bx; + end + end //} + mem[address] = dbuf; + if( MES_ALL=="ON" && $realtime != 0) + $fdisplay (log, + "\nWarning! Int_Array instance, %m:", + "\n\t Enable pin unknown at time %t.", $realtime, + "\n\t Enabled bits at port %0d", ip, + " write address x'%0h' set unknown.", address); + end //} wwe[ip] - write port ip enabled + end //} for each write port ip + end //} unknown write enable + end //} possible write (EN != 0) + end //} always @(D or BW or AW or EN) + + + // Read memory + always @(AAR or RDA) + begin //{ + for (iba_r = 0 ; iba_r < Naddr ; iba_r = iba_r + 1) + begin + abuf_ra[iba_r] = AAR[iba_r]; + if(abuf_ra[iba_r] !== 0 && abuf_ra[iba_r] !== 1) + begin + iba_r = Naddr; + end + end + if(iba_r == Naddr && abuf_ra < Nword) + begin //{ Read valid address + `ifdef TSMC_INITIALIZE_FAULT + dbuf_ra = mem[abuf_ra] ^ mem_fault[abuf_ra]; + `else + dbuf_ra = mem[abuf_ra]; + `endif + for (iba_r = 0 ; iba_r < Ndata ; iba_r = iba_r + 1) + begin + if(QA[iba_r] == dbuf_ra[iba_r]) + begin + QA[iba_r] <= #(dly) dbuf_ra[iba_r]; + end + else + begin + QA[iba_r] <= #(dly) dbuf_ra[iba_r]; + end // else + end // for + end //} valid address + else + begin //{ Invalid address + if(iba_r <= Naddr) begin + if( MES_ALL=="ON" && $realtime != 0) + $fwrite (log, "\nWarning! Int_Array instance, %m:", + "\n\t Port A read address"); + if( MES_ALL=="ON" && $realtime != 0) + $fwrite (log, " x'%0h' out of range", abuf_ra); + if( MES_ALL=="ON" && $realtime != 0) + $fdisplay (log, + " at time %t.", $realtime, + "\n\t Port A outputs set to unknown."); + end + + for (iba_r = 0 ; iba_r < Ndata ; iba_r = iba_r + 1) + QA[iba_r] <= #(dly) 1'bx; + end //} invalid address + end //} always @(chgmem or AR) + + // Read memory + always @(ABR or RDB) + begin //{ + for (ibb_r = 0 ; ibb_r < Naddr ; ibb_r = ibb_r + 1) + begin + abuf_rb[ibb_r] = ABR[ibb_r]; + if(abuf_rb[ibb_r] !== 0 && abuf_rb[ibb_r] !== 1) + begin + ibb_r = Naddr; + end + end + if(ibb_r == Naddr && abuf_rb < Nword) + begin //{ Read valid address + `ifdef TSMC_INITIALIZE_FAULT + dbuf_rb = mem[abuf_rb] ^ mem_fault[abuf_rb]; + `else + dbuf_rb = mem[abuf_rb]; + `endif + for (ibb_r = 0 ; ibb_r < Ndata ; ibb_r = ibb_r + 1) + begin + if(QB[ibb_r] == dbuf_rb[ibb_r]) + begin + QB[ibb_r] <= #(dly) dbuf_rb[ibb_r]; + end + else + begin + QB[ibb_r] <= #(dly) dbuf_rb[ibb_r]; + end // else + end // for + end //} valid address + else + begin //{ Invalid address + if(ibb_r <= Naddr) begin + if( MES_ALL=="ON" && $realtime != 0) + $fwrite (log, "\nWarning! Int_Array instance, %m:", + "\n\t Port B read address"); + if( MES_ALL=="ON" && $realtime != 0) + $fwrite (log, " x'%0h' out of range", abuf_rb); + if( MES_ALL=="ON" && $realtime != 0) + $fdisplay (log, + " at time %t.", $realtime, + "\n\t Port B outputs set to unknown."); + end + for (ibb_r = 0 ; ibb_r < Ndata ; ibb_r = ibb_r + 1) + QB[ibb_r] <= #(dly) 1'bx; + end //} invalid address + end //} always @(chgmem or AR) + + + // Task for loading contents of a memory + task preloadData; + input [256*8:1] infile; // Max 256 character File Name + begin + $display ("%m: Reading file, %0s, into the register file", infile); + `ifdef TSMC_INITIALIZE_FORMAT_BINARY + $readmemb (infile, mem, 0, Nword-1); + `else + $readmemh (infile, mem, 0, Nword-1); + `endif + end + endtask + + // Task for displaying contents of a memory + task printMemoryFromTo; + input [Naddr - 1:0] from; // memory content are printed, start from this address. + input [Naddr - 1:0] to; // memory content are printed, end at this address. + integer i; + begin //{ + $display ("\n%m: Memory content dump"); + if(from < 0 || from > to || to >= Nword) + begin + $display ("Error! Invalid address range (%0d, %0d).", from, to, + "\nUsage: %m (from, to);", + "\n where from >= 0 and to <= %0d.", Nword-1); + end + else + begin + $display ("\n Address\tValue"); + for (i = from ; i <= to ; i = i + 1) + $display ("%d\t%b", i, mem[i]); + end + end //} + endtask //} + + // Task for printing entire memory, including normal array and redundancy array. + task printMemory; + integer i; + begin + $display ("Dumping register file..."); + $display("@ Address, content-----"); + for (i = 0; i < Nword; i = i + 1) begin + $display("@%d, %b", i, mem[i]); + end + end + endtask + + task xMemoryAll; + begin + for (ib = 0 ; ib < Ndata ; ib = ib + 1) + dbuf[ib] = 1'bx; + for (iw = 0 ; iw < Nword ; iw = iw + 1) + mem[iw] = dbuf; + end + endtask + + task zeroMemoryAll; + begin + for (ib = 0 ; ib < Ndata ; ib = ib + 1) + dbuf[ib] = 1'b0; + for (iw = 0 ; iw < Nword ; iw = iw + 1) + mem[iw] = dbuf; + end + endtask + endmodule + + + diff --git a/rtl/memory/tsmc_dpram.v b/rtl/memory/tsmc_dpram.v new file mode 100644 index 0000000..80f55e8 --- /dev/null +++ b/rtl/memory/tsmc_dpram.v @@ -0,0 +1,215 @@ + + +module tsmc_dpram #( + parameter DATAWIDTH = 32 + ,parameter ADDRWIDTH = 14 +)( + input PortClk + ,input [ADDRWIDTH-1 :0] PortAAddr + ,input [DATAWIDTH-1 :0] PortADataIn + ,input PortAWriteEnable //active low + ,input PortAChipEnable //active low + ,input [(DATAWIDTH/8)-1 :0] PortAByteWriteEnable //active low + ,output [DATAWIDTH-1 :0] PortADataOut + + ,input [ADDRWIDTH-1 :0] PortBAddr + ,input [DATAWIDTH-1 :0] PortBDataIn + ,input PortBWriteEnable //active low + ,input PortBChipEnable //active low + ,input [(DATAWIDTH/8)-1 :0] PortBByteWriteEnable //active low + ,output [DATAWIDTH-1 :0] PortBDataOut +); +//////////////////////////////////////////////////////////////////////////////// +//Function +//////////////////////////////////////////////////////////////////////////////// +function integer clog2(input integer bit_depth); + begin + for(clog2=0;bit_depth>0;clog2=clog2+1) + bit_depth =bit_depth>>1; + end +endfunction + +localparam LSB = clog2(DATAWIDTH/8 -1); + +generate + if((DATAWIDTH == 32) && (ADDRWIDTH == 15)) begin:dpram_32X4096_generation + + wire [DATAWIDTH-1:0] BWEBA; + wire [DATAWIDTH-1:0] BWEBB; + + assign BWEBA = {{8{PortAByteWriteEnable[3]}},{8{PortAByteWriteEnable[2]}},{8{PortAByteWriteEnable[1]}},{8{PortAByteWriteEnable[0]}}}; + assign BWEBB = {{8{PortBByteWriteEnable[3]}},{8{PortBByteWriteEnable[2]}},{8{PortBByteWriteEnable[1]}},{8{PortBByteWriteEnable[0]}}}; + + wire U0_CEBA; + wire U0_CEBB; + wire U1_CEBA; + wire U1_CEBB; + + assign U0_CEBA = PortAAddr[ADDRWIDTH-1] | PortAChipEnable; + assign U0_CEBB = PortBAddr[ADDRWIDTH-1] | PortBChipEnable; + + assign U1_CEBA = ~PortAAddr[ADDRWIDTH-1] | PortAChipEnable; + assign U1_CEBB = ~PortBAddr[ADDRWIDTH-1] | PortBChipEnable; + + wire [DATAWIDTH-1:0] U0_QA; + wire [DATAWIDTH-1:0] U0_QB; + wire [DATAWIDTH-1:0] U1_QA; + wire [DATAWIDTH-1:0] U1_QB; + + reg AA_1D_MSB; + reg AB_1D_MSB; + + always @(posedge PortClk) begin + if(PortAWriteEnable == 1'b1) begin + AA_1D_MSB <= PortAAddr[ADDRWIDTH-1]; + end + else begin + AA_1D_MSB <= AA_1D_MSB; + end + end + + always @(posedge PortClk) begin + if(PortBWriteEnable == 1'b1) begin + AB_1D_MSB <= PortBAddr[ADDRWIDTH-1]; + end + else begin + AB_1D_MSB <= AB_1D_MSB; + end + end + + + assign PortADataOut = {DATAWIDTH{~AA_1D_MSB}} & U0_QA + | {DATAWIDTH{AA_1D_MSB}} & U1_QA; + + + assign PortBDataOut = {DATAWIDTH{~AB_1D_MSB}} & U0_QB + | {DATAWIDTH{AB_1D_MSB}} & U1_QB; + tsdn28hpcpuhdb4096x32m4mw_170a U0_TSDN28HPCPUHDB4096X32M4MW ( + .CLK ( PortClk ) + ,.CEBA ( U0_CEBA ) + ,.WEBA ( PortAWriteEnable ) + ,.BWEBA ( BWEBA ) + ,.AA ( PortAAddr[ADDRWIDTH-2:LSB] ) + ,.DA ( PortADataIn ) + ,.QA ( U0_QA ) + ,.CEBB ( U0_CEBB ) + ,.WEBB ( PortBWriteEnable ) + ,.BWEBB ( BWEBB ) + ,.AB ( PortBAddr[ADDRWIDTH-2:LSB] ) + ,.DB ( PortBDataIn ) + ,.QB ( U0_QB ) + ,.RTSEL ( 2'b00 ) + ,.WTSEL ( 2'b00 ) + ,.PTSEL ( 2'b00 ) + ); + + tsdn28hpcpuhdb4096x32m4mw_170a U1_TSDN28HPCPUHDB4096X32M4MW ( + .CLK ( PortClk ) + ,.CEBA ( U1_CEBA ) + ,.WEBA ( PortAWriteEnable ) + ,.BWEBA ( BWEBA ) + ,.AA ( PortAAddr[ADDRWIDTH-2:LSB] ) + ,.DA ( PortADataIn ) + ,.QA ( U1_QA ) + ,.CEBB ( U1_CEBB ) + ,.WEBB ( PortBWriteEnable ) + ,.BWEBB ( BWEBB ) + ,.AB ( PortBAddr[ADDRWIDTH-2:LSB] ) + ,.DB ( PortBDataIn ) + ,.QB ( U1_QB ) + ,.RTSEL ( 2'b00 ) + ,.WTSEL ( 2'b00 ) + ,.PTSEL ( 2'b00 ) + ); + end + + else if((DATAWIDTH == 32) && (ADDRWIDTH == 8)) begin:spram_32X64_generation + wire [DATAWIDTH-1:0] BWEBA = {{8{PortAByteWriteEnable[3]}},{8{PortAByteWriteEnable[2]}},{8{PortAByteWriteEnable[1]}},{8{PortAByteWriteEnable[0]}}}; + wire [DATAWIDTH-1:0] BWEBB = {{8{PortBByteWriteEnable[3]}},{8{PortBByteWriteEnable[2]}},{8{PortBByteWriteEnable[1]}},{8{PortBByteWriteEnable[0]}}}; + tsdn28hpcpuhdb64x32m4mw_170a U_tsdn28hpcpuhdb64x32m4mw_170a ( + .CLK ( PortClk ) + ,.CEBA ( PortAChipEnable ) + ,.WEBA ( PortAWriteEnable ) + ,.BWEBA ( BWEBA ) + ,.AA ( PortAAddr[ADDRWIDTH-1:LSB] ) + ,.DA ( PortADataIn ) + ,.QA ( PortADataOut ) + ,.CEBB ( PortBChipEnable ) + ,.WEBB ( PortBWriteEnable ) + ,.BWEBB ( BWEBB ) + ,.AB ( PortBAddr[ADDRWIDTH-1:LSB] ) + ,.DB ( PortBDataIn ) + ,.QB ( PortBDataOut ) + ,.RTSEL ( 2'b00 ) + ,.WTSEL ( 2'b00 ) + ,.PTSEL ( 2'b00 ) + ); + end + else if((DATAWIDTH == 256) && (ADDRWIDTH == 12)) begin:spram_512X128_generation + genvar i; + wire [DATAWIDTH-1:0] BWEBA ; + wire [DATAWIDTH-1:0] BWEBB ; + for(i=0;i0;clog2=clog2+1) + bit_depth =bit_depth>>1; + end +endfunction + +localparam LSB = clog2(DATAWIDTH/8 -1); +localparam MAW = ADDRWIDTH - LSB; +localparam MB =(DATAWIDTH)*(32'h0000_0001< Env_Idata * Nco_Sin +DW_mult_pipe #( + .a_width ( 16 ) + ,.b_width ( 16 ) + ,.num_stages ( 3 ) + ,.stall_mode ( 0 ) + ,.rst_mode ( 1 ) + ,.op_iso_mode ( 0 ) + ) inst_isin_mult ( + .clk ( Dig_Clk ) + ,.rst_n ( Dig_Resetn ) + ,.en ( 1'b1 ) + ,.a ( Env_Idata_r4 ) + ,.b ( Nco_Sin ) + ,.tc ( 1'b1 ) + ,.product ( mult_isin_tmp ) + ); + + +//DW_mult_pipe Instantiation -> Env_Idata * Nco_Cos +DW_mult_pipe #( + .a_width ( 16 ) + ,.b_width ( 16 ) + ,.num_stages ( 3 ) + ,.stall_mode ( 0 ) + ,.rst_mode ( 1 ) + ,.op_iso_mode ( 0 ) + ) inst_icos_mult ( + .clk ( Dig_Clk ) + ,.rst_n ( Dig_Resetn ) + ,.en ( 1'b1 ) + ,.a ( Env_Idata_r4 ) + ,.b ( Nco_Cos ) + ,.tc ( 1'b1 ) + ,.product ( mult_icos_tmp ) + ); + +//DW_mult_pipe Instantiation -> Env_Qdata * Nco_Sin +DW_mult_pipe #( + .a_width ( 16 ) + ,.b_width ( 16 ) + ,.num_stages ( 3 ) + ,.stall_mode ( 0 ) + ,.rst_mode ( 1 ) + ,.op_iso_mode ( 0 ) + ) inst_qsin_mult ( + .clk ( Dig_Clk ) + ,.rst_n ( Dig_Resetn ) + ,.en ( 1'b1 ) + ,.a ( Env_Qdata_r4 ) + ,.b ( Nco_Sin ) + ,.tc ( 1'b1 ) + ,.product ( mult_qsin_tmp ) + ); + +//DW_mult_pipe Instantiation -> Env_Qdata * Nco_Cos +DW_mult_pipe #( + .a_width ( 16 ) + ,.b_width ( 16 ) + ,.num_stages ( 3 ) + ,.stall_mode ( 0 ) + ,.rst_mode ( 1 ) + ,.op_iso_mode ( 0 ) + ) inst_qcos_mult ( + .clk ( Dig_Clk ) + ,.rst_n ( Dig_Resetn ) + ,.en ( 1'b1 ) + ,.a ( Env_Qdata_r4 ) + ,.b ( Nco_Cos ) + ,.tc ( 1'b1 ) + ,.product ( mult_qcos_tmp ) + ); + +////////////////////////////////////////////////////////////// +// The processing of a multiplication result. +////////////////////////////////////////////////////////////// +assign mult_isin_w = {mult_isin_tmp[31],mult_isin_tmp[29:15]} +mult_isin_tmp[14]; +assign mult_icos_w = {mult_icos_tmp[31],mult_icos_tmp[29:15]} +mult_icos_tmp[14]; +assign mult_qsin_w = {mult_qsin_tmp[31],mult_qsin_tmp[29:15]} +mult_qsin_tmp[14]; +assign mult_qcos_w = {mult_qcos_tmp[31],mult_qcos_tmp[29:15]} +mult_qcos_tmp[14]; +////////////////////////////////////////////////////////////// +// The multiplier processing result register. +////////////////////////////////////////////////////////////// +//mult_isin_r +always @(posedge Dig_Clk or negedge Dig_Resetn) begin + if(Dig_Resetn == 1'b0) begin + mult_isin_r <= 16'd0; + end + else begin + mult_isin_r <= mult_isin_w; + end +end + +//mult_icos_r +always @(posedge Dig_Clk or negedge Dig_Resetn) begin + if(Dig_Resetn == 1'b0) begin + mult_icos_r <= 16'd0; + end + else begin + mult_icos_r <= mult_icos_w; + end +end + +//mult_qsin_r +always @(posedge Dig_Clk or negedge Dig_Resetn) begin + if(Dig_Resetn == 1'b0) begin + mult_qsin_r <= 16'd0; + end + else begin + mult_qsin_r <= mult_qsin_w; + end +end + +//mult_qcos_r +always @(posedge Dig_Clk or negedge Dig_Resetn) begin + if(Dig_Resetn == 1'b0) begin + mult_qcos_r <= 16'd0; + end + else begin + mult_qcos_r <= mult_qcos_w; + end +end + +////////////////////////////////////////////////////////////// +// Orthogonal modulation +////////////////////////////////////////////////////////////// + +assign adder0_icosqsin_tmp = ~Mod_Sideband_Sel ? (mult_icos_r + mult_qsin_r):(mult_icos_r - mult_qsin_r); +//1'b0: adder0_icosqsin_tmp = Icoswd+Qsinwd, 1'b1:adder0_icosqsin_tmp = Icoswd-Qsinwd + +assign adder1_isinqcos_tmp = Mod_Sideband_Sel ? (mult_isin_r + mult_qcos_r):(-mult_isin_r + mult_qcos_r); +//1'b0: adder1_isinqcos_tmp = Isinwd+Qcoswd, 1'b1:adder1_isinqcos_tmp = -Isinwd+Qcoswd + +////////////////////////////////////////////////////////////// +// Output of IQ data stored in registers. +////////////////////////////////////////////////////////////// + +always @(posedge Dig_Clk or negedge Dig_Resetn) begin + if(Dig_Resetn == 1'b0) begin + adder0_icosqsin_r <= 16'd0; + end +else if(adder0_icosqsin_tmp[16:15] == 2'b01)begin + adder0_icosqsin_r <= 32767; + end +else if (adder0_icosqsin_tmp[16:15] == 2'b10)begin + adder0_icosqsin_r <= -32768; + end +else begin + adder0_icosqsin_r <= {adder0_icosqsin_tmp[16],adder0_icosqsin_tmp[14:0]}; + end +end + +always @(posedge Dig_Clk or negedge Dig_Resetn) begin + if(Dig_Resetn == 1'b0) begin + adder1_isinqcos_r <= 16'd0; + end +else if (adder1_isinqcos_tmp[16:15] == 2'b01)begin + adder1_isinqcos_r <= 32767; + end +else if (adder1_isinqcos_tmp[16:15] == 2'b10)begin + adder1_isinqcos_r <= -32768; + end +else begin + adder1_isinqcos_r <= {adder1_isinqcos_tmp[16],adder1_isinqcos_tmp[14:0]}; + end +end + +assign Mod_Data_I = adder0_icosqsin_r; +assign Mod_Data_Q = adder1_isinqcos_r; +////////////////////////////////////////////////////////////// +// Generation of Mod_Vld signal. +////////////////////////////////////////////////////////////// +//mod_data_vld_dly +always @(posedge Dig_Clk or negedge Dig_Resetn) begin + if(Dig_Resetn == 1'b0) begin + freqmod_data_vld_dly <= 8'b0; + end + else begin + freqmod_data_vld_dly <= {freqmod_data_vld_dly[6:0], Mod_Enable & Env_Vld}; + end +end + +assign Mod_Vld = freqmod_data_vld_dly[7]; + + +endmodule diff --git a/rtl/nco/coef_c.v b/rtl/nco/coef_c.v new file mode 100644 index 0000000..8563555 --- /dev/null +++ b/rtl/nco/coef_c.v @@ -0,0 +1,150 @@ +module COEF_C( + index , + C0_C , + C1_C , + C2_C + ); +input [4:0] index; + +output [17:0] C0_C; +output [11:0] C1_C; +output [5:0] C2_C; + +reg [17:0] C0_C; +reg [11:0] C1_C; +reg [5:0] C2_C; + + + +//------------------------ +//----C0_C OK +always@(*) +begin + + case(index) + 5'd 0 : C0_C =18'h3ffff; + 5'd 1 : C0_C =18'h3ffb1; + 5'd 2 : C0_C =18'h3fec4; + 5'd 3 : C0_C =18'h3fd3a; + 5'd 4 : C0_C =18'h3fb12; + 5'd 5 : C0_C =18'h3f84d; + 5'd 6 : C0_C =18'h3f4eb; + 5'd 7 : C0_C =18'h3f0ed; + 5'd 8 : C0_C =18'h3ec53; + 5'd 9 : C0_C =18'h3e71e; + 5'd10 : C0_C =18'h3e150; + 5'd11 : C0_C =18'h3dae8; + 5'd12 : C0_C =18'h3d3e8; + 5'd13 : C0_C =18'h3cc51; + 5'd14 : C0_C =18'h3c424; + 5'd15 : C0_C =18'h3bb62; + 5'd16 : C0_C =18'h3b20d; + 5'd17 : C0_C =18'h3a827; + 5'd18 : C0_C =18'h39daf; + 5'd19 : C0_C =18'h392a9; + 5'd20 : C0_C =18'h38716; + 5'd21 : C0_C =18'h37af8; + 5'd22 : C0_C =18'h36e50; + 5'd23 : C0_C =18'h36121; + 5'd24 : C0_C =18'h3536d; + 5'd25 : C0_C =18'h34535; + 5'd26 : C0_C =18'h3367c; + 5'd27 : C0_C =18'h32744; + 5'd28 : C0_C =18'h31790; + 5'd29 : C0_C =18'h30762; + 5'd30 : C0_C =18'h2f6bc; + 5'd31 : C0_C =18'h2e5a1; + // default : C0_C = C0_C; + endcase + +end + +//------------------------ +//----C1_C OK +always@(*) +begin + + case(index) + 5'd 0 : C1_C =12'd 0; + 5'd 1 : C1_C =12'd 79; + 5'd 2 : C1_C =12'd 158; + 5'd 3 : C1_C =12'd 237; + 5'd 4 : C1_C =12'd 315; + 5'd 5 : C1_C =12'd 394; + 5'd 6 : C1_C =12'd 472; + 5'd 7 : C1_C =12'd 550; + 5'd 8 : C1_C =12'd 628; + 5'd 9 : C1_C =12'd 705; + 5'd10 : C1_C =12'd 782; + 5'd11 : C1_C =12'd 858; + 5'd12 : C1_C =12'd 934; + 5'd13 : C1_C =12'd1009; + 5'd14 : C1_C =12'd1084; + 5'd15 : C1_C =12'd1158; + 5'd16 : C1_C =12'd1231; + 5'd17 : C1_C =12'd1304; + 5'd18 : C1_C =12'd1376; + 5'd19 : C1_C =12'd1446; + 5'd20 : C1_C =12'd1517; + 5'd21 : C1_C =12'd1586; + 5'd22 : C1_C =12'd1654; + 5'd23 : C1_C =12'd1721; + 5'd24 : C1_C =12'd1787; + 5'd25 : C1_C =12'd1852; + 5'd26 : C1_C =12'd1916; + 5'd27 : C1_C =12'd1979; + 5'd28 : C1_C =12'd2041; + 5'd29 : C1_C =12'd2101; + 5'd30 : C1_C =12'd2161; + 5'd31 : C1_C =12'd2218; + // default : C1_C = C1_C; + endcase + +end +//------------------------ +//----C2_C +always@(*) +begin + + + case(index) + 5'd 0 : C2_C =6'd39; + 5'd 1 : C2_C =6'd39; + 5'd 2 : C2_C =6'd39; + 5'd 3 : C2_C =6'd39; + 5'd 4 : C2_C =6'd39; + 5'd 5 : C2_C =6'd39; + 5'd 6 : C2_C =6'd39; + 5'd 7 : C2_C =6'd39; + 5'd 8 : C2_C =6'd39; + 5'd 9 : C2_C =6'd38; + 5'd10 : C2_C =6'd38; + 5'd11 : C2_C =6'd38; + 5'd12 : C2_C =6'd38; + 5'd13 : C2_C =6'd37; + 5'd14 : C2_C =6'd37; + 5'd15 : C2_C =6'd37; + 5'd16 : C2_C =6'd36; + 5'd17 : C2_C =6'd36; + 5'd18 : C2_C =6'd35; + 5'd19 : C2_C =6'd35; + 5'd20 : C2_C =6'd35; + 5'd21 : C2_C =6'd34; + 5'd22 : C2_C =6'd34; + 5'd23 : C2_C =6'd33; + 5'd24 : C2_C =6'd33; + 5'd25 : C2_C =6'd32; + 5'd26 : C2_C =6'd31; + 5'd27 : C2_C =6'd31; + 5'd28 : C2_C =6'd30; + 5'd29 : C2_C =6'd30; + 5'd30 : C2_C =6'd29; + 5'd31 : C2_C =6'd28; + // default : C2_C = C2_C; + endcase + + +end +endmodule + + diff --git a/rtl/nco/coef_s.v b/rtl/nco/coef_s.v new file mode 100644 index 0000000..4fcbba5 --- /dev/null +++ b/rtl/nco/coef_s.v @@ -0,0 +1,155 @@ +module COEF_S( + + index , + C0_S , + C1_S , + C2_S + + ); + +input [4:0] index; + +output [17:0] C0_S; +output [11:0] C1_S; +output [4:0] C2_S; + + +reg [17:0] C0_S; +reg [11:0] C1_S; +reg [4:0] C2_S; + +//------------------------ +//----C0_S +always@(*) +begin + + case(index) + 5'd 0 : C0_S =18'd 0; + 5'd 1 : C0_S =18'd 6433; + 5'd 2 : C0_S =18'd 12863; + 5'd 3 : C0_S =18'd 19284; + 5'd 4 : C0_S =18'd 25695; + 5'd 5 : C0_S =18'd 32089; + 5'd 6 : C0_S =18'd 38464; + 5'd 7 : C0_S =18'd 44817; + 5'd 8 : C0_S =18'd 51142; + 5'd 9 : C0_S =18'd 57436; + 5'd10 : C0_S =18'd 63696; + 5'd11 : C0_S =18'd 69917; + 5'd12 : C0_S =18'd 76096; + 5'd13 : C0_S =18'd 82230; + 5'd14 : C0_S =18'd 88314; + 5'd15 : C0_S =18'd 94344; + 5'd16 : C0_S =18'd100318; + 5'd17 : C0_S =18'd106232; + 5'd18 : C0_S =18'd112081; + 5'd19 : C0_S =18'd117863; + 5'd20 : C0_S =18'd123574; + 5'd21 : C0_S =18'd129210; + 5'd22 : C0_S =18'd134769; + 5'd23 : C0_S =18'd140246; + 5'd24 : C0_S =18'd145639; + 5'd25 : C0_S =18'd150945; + 5'd26 : C0_S =18'd156159; + 5'd27 : C0_S =18'd161279; + 5'd28 : C0_S =18'd166302; + 5'd29 : C0_S =18'd171225; + 5'd30 : C0_S =18'd176045; + 5'd31 : C0_S =18'd180759; + // default : C0_S = C0_S; + endcase + +end + +//------------------------ + + +//------------------------ +//----C1_S OK +always@(*) +begin + + case(index) + 5'd 0 : C1_S =12'd3217; + 5'd 1 : C1_S =12'd3216; + 5'd 2 : C1_S =12'd3213; + 5'd 3 : C1_S =12'd3208; + 5'd 4 : C1_S =12'd3202; + 5'd 5 : C1_S =12'd3193; + 5'd 6 : C1_S =12'd3182; + 5'd 7 : C1_S =12'd3170; + 5'd 8 : C1_S =12'd3155; + 5'd 9 : C1_S =12'd3139; + 5'd10 : C1_S =12'd3121; + 5'd11 : C1_S =12'd3101; + 5'd12 : C1_S =12'd3079; + 5'd13 : C1_S =12'd3055; + 5'd14 : C1_S =12'd3029; + 5'd15 : C1_S =12'd3002; + 5'd16 : C1_S =12'd2972; + 5'd17 : C1_S =12'd2941; + 5'd18 : C1_S =12'd2908; + 5'd19 : C1_S =12'd2874; + 5'd20 : C1_S =12'd2837; + 5'd21 : C1_S =12'd2799; + 5'd22 : C1_S =12'd2759; + 5'd23 : C1_S =12'd2718; + 5'd24 : C1_S =12'd2675; + 5'd25 : C1_S =12'd2630; + 5'd26 : C1_S =12'd2584; + 5'd27 : C1_S =12'd2536; + 5'd28 : C1_S =12'd2487; + 5'd29 : C1_S =12'd2436; + 5'd30 : C1_S =12'd2384; + 5'd31 : C1_S =12'd2330; + // default : C1_S = C1_S; + endcase + +end + +//------------------------ +//----C2_S +always@(*) +begin + + case(index) + 5'd 0 : C2_S =5'd 0; + 5'd 1 : C2_S =5'd 1; + 5'd 2 : C2_S =5'd 2; + 5'd 3 : C2_S =5'd 3; + 5'd 4 : C2_S =5'd 4; + 5'd 5 : C2_S =5'd 5; + 5'd 6 : C2_S =5'd 6; + 5'd 7 : C2_S =5'd 7; + 5'd 8 : C2_S =5'd 8; + 5'd 9 : C2_S =5'd 9; + 5'd10 : C2_S =5'd10; + 5'd11 : C2_S =5'd11; + 5'd12 : C2_S =5'd12; + 5'd13 : C2_S =5'd13; + 5'd14 : C2_S =5'd14; + 5'd15 : C2_S =5'd15; + 5'd16 : C2_S =5'd16; + 5'd17 : C2_S =5'd16; + 5'd18 : C2_S =5'd17; + 5'd19 : C2_S =5'd18; + 5'd20 : C2_S =5'd19; + 5'd21 : C2_S =5'd20; + 5'd22 : C2_S =5'd21; + 5'd23 : C2_S =5'd22; + 5'd24 : C2_S =5'd22; + 5'd25 : C2_S =5'd23; + 5'd26 : C2_S =5'd24; + 5'd27 : C2_S =5'd25; + 5'd28 : C2_S =5'd25; + 5'd29 : C2_S =5'd26; + 5'd30 : C2_S =5'd27; + 5'd31 : C2_S =5'd28; + // default : C2_S = C2_S; + endcase + +end + +endmodule + + diff --git a/rtl/nco/cos_op.v b/rtl/nco/cos_op.v new file mode 100644 index 0000000..25ded3c --- /dev/null +++ b/rtl/nco/cos_op.v @@ -0,0 +1,144 @@ +module COS_OP( + clk , + rstn , + pha_map , + pha_indx_msb , + cos_op_o + ); + +input clk; +input rstn; +input [18:0] pha_map; +output [2:0] pha_indx_msb; +output [14:0] cos_op_o; + +wire [2:0] pha_indx_msb_w; +assign pha_indx_msb_w=pha_map[18:16]; + +wire [15:0] pha_indx_lsb; +assign pha_indx_lsb=pha_map[15:0]; +wire [15:0] pha_op; +assign pha_op=pha_indx_msb_w[0]?(~pha_indx_lsb):pha_indx_lsb; + +wire [4:0] indx; +assign indx=pha_op[15:11]; +wire [10:0] x_w; +assign x_w=pha_op[10:0]; +wire [17:0] c0; +wire [11:0] c1; +wire [5:0] c2; + + +COEF_C coef_c_inst1( + .index(indx) , + .C0_C(c0) , + .C1_C(c1) , + .C2_C(c2) + ); + +reg[17:0] c0_r1; +reg[17:0] c0_r2; +reg[17:0] c0_r3; +reg[17:0] c0_r4; +reg[17:0] c0_r5; +reg[17:0] c0_r6; +always@(posedge clk) + begin + c0_r1<=c0; + c0_r2<=c0_r1; + c0_r3<=c0_r2; + c0_r4<=c0_r3; + c0_r5<=c0_r4; + c0_r6<=c0_r5; + end +reg [11:0] c1_r1; +reg [11:0] c1_r2; +reg [11:0] c1_r3; +always@(posedge clk) + begin + c1_r1<=c1; + c1_r2<=c1_r1; + c1_r3<=c1_r2; + end +reg [5:0] c2_r1; +always@(posedge clk) + c2_r1<=c2; +reg[10:0] x_r1; +reg[10:0] x_r2; +reg[10:0] x_r3; +reg[10:0] x_r4; +always@(posedge clk) + begin + x_r1<=x_w; + x_r2<=x_r1; + x_r3<=x_r2; + x_r4<=x_r3; + end + +wire [16:0] c2x; + +DW_mult_pipe #(11,6,2,0,1) inst_mult_0( + .clk (clk ), + .rst_n (rstn ), + .en (1'b1 ), + .a (x_r1 ), + .b (c2_r1 ), + .tc (1'b0 ), + .product (c2x ) + ); + +wire [5:0] c2x_w; +assign c2x_w=c2x[10]?(c2x[16:11]+6'd1):c2x[16:11]; + +reg [11:0] c2xc1; +always@(posedge clk) + c2xc1<=c1_r2+c2x_w; +wire [22:0] c2xc1x; +DW_mult_pipe #(11,12,3,0,1) inst_mult_1( + .clk (clk ), + .rst_n (rstn ), + .en (1'b1 ), + .a (x_r3 ), + .b (c2xc1 ), + .tc (1'b0 ), + .product (c2xc1x ) + ); + + +wire [12:0] c2xc1x_w; +assign c2xc1x_w=c2xc1x[9]?(c2xc1x[22:10]+13'd1):c2xc1x[22:10]; +reg [12:0] c2xc1x_r; +always@(posedge clk) + c2xc1x_r<=c2xc1x_w; +wire [17:0] c2xc1xc0; +assign c2xc1xc0 =c0_r6-c2xc1x_r; + +wire[15:0] c2xc1xc0_w1; +assign c2xc1xc0_w1=c2xc1xc0[2]?({1'b0,c2xc1xc0[17:3]}+15'd1):{1'b0,c2xc1xc0[17:3]}; + +wire[14:0] c2xc1xc0_w; +assign c2xc1xc0_w=(c2xc1xc0_w1>=15'd32767)?15'd32767:c2xc1xc0_w1[14:0]; +reg [14:0] c2xc1xc0_r; +always@(posedge clk) + c2xc1xc0_r<=c2xc1xc0_w; +assign cos_op_o=c2xc1xc0_r; +reg[2:0] pha_indx_msb_r1; +reg[2:0] pha_indx_msb_r2; +reg[2:0] pha_indx_msb_r3; +reg[2:0] pha_indx_msb_r4; +reg[2:0] pha_indx_msb_r5; +reg[2:0] pha_indx_msb_r6; +reg[2:0] pha_indx_msb_r7; +always@(posedge clk) + begin + pha_indx_msb_r1<=pha_indx_msb_w; + pha_indx_msb_r2<=pha_indx_msb_r1; + pha_indx_msb_r3<=pha_indx_msb_r2; + pha_indx_msb_r4<=pha_indx_msb_r3; + pha_indx_msb_r5<=pha_indx_msb_r4; + pha_indx_msb_r6<=pha_indx_msb_r5; + pha_indx_msb_r7<=pha_indx_msb_r6; + end + +assign pha_indx_msb=pha_indx_msb_r7; +endmodule diff --git a/rtl/nco/nco.v b/rtl/nco/nco.v new file mode 100644 index 0000000..1925f89 --- /dev/null +++ b/rtl/nco/nco.v @@ -0,0 +1,240 @@ +module NCO( + clk, + rstn, + phase_manual_clr, + phase_auto_clr, + fcw, + pha, + + cos_0, + cos_1, + cos_2, + cos_3, + cos_4, + cos_5, + cos_6, + cos_7, + cos_8, + cos_9, + cos_10, + cos_11, + cos_12, + cos_13, + cos_14, + cos_15, + + sin_0, + sin_1, + sin_2, + sin_3, + sin_4, + sin_5, + sin_6, + sin_7, + sin_8, + sin_9, + sin_10, + sin_11, + sin_12, + sin_13, + sin_14, + sin_15 + ); + +input clk; +input rstn; +input phase_manual_clr; +input phase_auto_clr; +input [47:0] fcw; +input [15:0] pha; + +output [15:0] cos_0; +output [15:0] cos_1; +output [15:0] cos_2; +output [15:0] cos_3; +output [15:0] cos_4; +output [15:0] cos_5; +output [15:0] cos_6; +output [15:0] cos_7; +output [15:0] cos_8; +output [15:0] cos_9; +output [15:0] cos_10; +output [15:0] cos_11; +output [15:0] cos_12; +output [15:0] cos_13; +output [15:0] cos_14; +output [15:0] cos_15; + + +output [15:0] sin_0; +output [15:0] sin_1; +output [15:0] sin_2; +output [15:0] sin_3; +output [15:0] sin_4; +output [15:0] sin_5; +output [15:0] sin_6; +output [15:0] sin_7; +output [15:0] sin_8; +output [15:0] sin_9; +output [15:0] sin_10; +output [15:0] sin_11; +output [15:0] sin_12; +output [15:0] sin_13; +output [15:0] sin_14; +output [15:0] sin_15; + + +reg [47:0] fcw1_r1; +reg [47:0] fcw2_r1; +reg [47:0] fcw3_r1; +reg [47:0] fcw4_r1; +reg [47:0] fcw5_r1; +reg [47:0] fcw6_r1; +reg [47:0] fcw7_r1; +reg [47:0] fcw8_r1; +reg [47:0] fcw9_r1; +reg [47:0] fcw10_r1; +reg [47:0] fcw11_r1; +reg [47:0] fcw12_r1; +reg [47:0] fcw13_r1; +reg [47:0] fcw14_r1; +reg [47:0] fcw15_r1; +reg [47:0] fcw16_r1; + + +wire [47:0] fcw2_w; +wire [47:0] fcw4_w; +wire [47:0] fcw8_w; +wire [47:0] fcw16_w; + +reg [15:0] pha_r; + +assign fcw2_w=fcw<<3'd1; +assign fcw4_w=fcw<<3'd2; +assign fcw8_w=fcw<<3'd3; +assign fcw16_w=fcw<<3'd4; + +always@(posedge clk or negedge rstn) + if(!rstn) + begin + fcw1_r1 <=48'd0; + fcw2_r1 <=48'd0; + fcw3_r1 <=48'd0; + fcw4_r1 <=48'd0; + fcw5_r1 <=48'd0; + fcw6_r1 <=48'd0; + fcw7_r1 <=48'd0; + fcw8_r1 <=48'd0; + fcw9_r1 <=48'd0; + fcw10_r1 <=48'd0; + fcw11_r1 <=48'd0; + fcw12_r1 <=48'd0; + fcw13_r1 <=48'd0; + fcw14_r1 <=48'd0; + fcw15_r1 <=48'd0; + fcw16_r1 <=48'd0; + end + else + begin + fcw1_r1 <=fcw; + fcw2_r1 <=fcw2_w; + fcw3_r1 <=fcw2_w+fcw; + fcw4_r1 <=fcw4_w; + fcw5_r1 <=fcw4_w+fcw; + fcw6_r1 <=fcw4_w+fcw2_w; + fcw7_r1 <=fcw8_w-fcw; + fcw8_r1 <=fcw8_w; + fcw9_r1 <=fcw8_w+fcw; + fcw10_r1 <=fcw8_w+fcw2_w; + fcw11_r1 <=fcw8_w+fcw2_w+fcw; + fcw12_r1 <=fcw8_w+fcw4_w; + fcw13_r1 <=fcw8_w+fcw4_w+fcw; + fcw14_r1 <=fcw16_w-fcw2_w; + fcw15_r1 <=fcw16_w-fcw; + fcw16_r1 <=fcw16_w; + + end + +always @(posedge clk or negedge rstn) begin + if(!rstn) begin + pha_r <= 16'd0; + end + else begin + pha_r <= pha; + end +end + + +wire clr_acc; +wire clr_fix; +assign clr_acc = phase_auto_clr | phase_manual_clr; +assign clr_fix = phase_manual_clr; + +wire [15:0] s1_i_o; +wire [15:0] s2_i_o; +wire [15:0] s3_i_o; + +P_NCO inst_p_nco( + .clk (clk ), + .rstn (rstn ), + .clr (clr_fix ), + .clr_acc (clr_acc ), + .pha (pha_r ), + .s1 (s1_i_o ), + .s2 (s2_i_o ), + .s3 (s3_i_o ), + .s1_o (s1_i_o ), + .s2_o (s2_i_o ), + .s3_o (s3_i_o ), + .fcw1 (fcw1_r1 ), + .fcw2 (fcw2_r1 ), + .fcw3 (fcw3_r1 ), + .fcw4 (fcw4_r1 ), + .fcw5 (fcw5_r1 ), + .fcw6 (fcw6_r1 ), + .fcw7 (fcw7_r1 ), + .fcw8 (fcw8_r1 ), + .fcw9 (fcw9_r1 ), + .fcw10 (fcw10_r1 ), + .fcw11 (fcw11_r1 ), + .fcw12 (fcw12_r1 ), + .fcw13 (fcw13_r1 ), + .fcw14 (fcw14_r1 ), + .fcw15 (fcw15_r1 ), + .fcw16 (fcw16_r1 ), + .cos_0 (cos_0 ), + .cos_1 (cos_1 ), + .cos_2 (cos_2 ), + .cos_3 (cos_3 ), + .cos_4 (cos_4 ), + .cos_5 (cos_5 ), + .cos_6 (cos_6 ), + .cos_7 (cos_7 ), + .cos_8 (cos_8 ), + .cos_9 (cos_9 ), + .cos_10 (cos_10 ), + .cos_11 (cos_11 ), + .cos_12 (cos_12 ), + .cos_13 (cos_13 ), + .cos_14 (cos_14 ), + .cos_15 (cos_15 ), + + .sin_0 (sin_0 ), + .sin_1 (sin_1 ), + .sin_2 (sin_2 ), + .sin_3 (sin_3 ), + .sin_4 (sin_4 ), + .sin_5 (sin_5 ), + .sin_6 (sin_6 ), + .sin_7 (sin_7 ), + .sin_8 (sin_8 ), + .sin_9 (sin_9 ), + .sin_10 (sin_10 ), + .sin_11 (sin_11 ), + .sin_12 (sin_12 ), + .sin_13 (sin_13 ), + .sin_14 (sin_14 ), + .sin_15 (sin_15 ) + + ); +endmodule diff --git a/rtl/nco/nco_ch1.v b/rtl/nco/nco_ch1.v new file mode 100644 index 0000000..859a7a9 --- /dev/null +++ b/rtl/nco/nco_ch1.v @@ -0,0 +1,51 @@ +module NCO_CH1( + clk, + rstn, + phase_manual_clr, + phase_auto_clr, + fcw, + pha, + + cos, + + sin + ); + +input clk; +input rstn; +input phase_manual_clr; +input phase_auto_clr; +input [47:0] fcw; +input [15:0] pha; + +output [15:0] cos; +output [15:0] sin; + + +wire clr_acc; +wire clr_fix; +assign clr_acc = phase_auto_clr | phase_manual_clr; +assign clr_fix = phase_manual_clr; + +wire [15:0] s1_i_o; +wire [15:0] s2_i_o; +wire [15:0] s3_i_o; + +P_NCO_CH1 inst_p_nco( + .clk (clk ), + .rstn (rstn ), + .clr (clr_fix ), + .clr_acc (clr_acc ), + .pha (pha ), + .s1 (s1_i_o ), + .s2 (s2_i_o ), + .s3 (s3_i_o ), + .s1_o (s1_i_o ), + .s2_o (s2_i_o ), + .s3_o (s3_i_o ), + .fcw (fcw ), + .cos (cos ), + .sin (sin ) + + ); +endmodule diff --git a/rtl/nco/p_nco.v b/rtl/nco/p_nco.v new file mode 100644 index 0000000..09af7fc --- /dev/null +++ b/rtl/nco/p_nco.v @@ -0,0 +1,292 @@ +module P_NCO( + clk, + rstn, + clr, + clr_acc, + pha, + + s1, + s2, + s3, + + s1_o, + s2_o, + s3_o, + + fcw1, + fcw2, + fcw3, + fcw4, + fcw5, + fcw6, + fcw7, + fcw8, + fcw9, + fcw10, + fcw11, + fcw12, + fcw13, + fcw14, + fcw15, + fcw16, + + cos_0, + cos_1, + cos_2, + cos_3, + cos_4, + cos_5, + cos_6, + cos_7, + cos_8, + cos_9, + cos_10, + cos_11, + cos_12, + cos_13, + cos_14, + cos_15, + + sin_0, + sin_1, + sin_2, + sin_3, + sin_4, + sin_5, + sin_6, + sin_7, + sin_8, + sin_9, + sin_10, + sin_11, + sin_12, + sin_13, + sin_14, + sin_15 + ); + +input clk; +input rstn; +input clr; +input clr_acc; +input [15:0] pha; + +input [15:0] s1; +input [15:0] s2; +input [15:0] s3; + +output [15:0] s1_o; +output [15:0] s2_o; +output [15:0] s3_o; + +output [15:0] cos_0; +output [15:0] cos_1; +output [15:0] cos_2; +output [15:0] cos_3; +output [15:0] cos_4; +output [15:0] cos_5; +output [15:0] cos_6; +output [15:0] cos_7; +output [15:0] cos_8; +output [15:0] cos_9; +output [15:0] cos_10; +output [15:0] cos_11; +output [15:0] cos_12; +output [15:0] cos_13; +output [15:0] cos_14; +output [15:0] cos_15; + + +output [15:0] sin_0; +output [15:0] sin_1; +output [15:0] sin_2; +output [15:0] sin_3; +output [15:0] sin_4; +output [15:0] sin_5; +output [15:0] sin_6; +output [15:0] sin_7; +output [15:0] sin_8; +output [15:0] sin_9; +output [15:0] sin_10; +output [15:0] sin_11; +output [15:0] sin_12; +output [15:0] sin_13; +output [15:0] sin_14; +output [15:0] sin_15; + + +input [47:0] fcw1; +input [47:0] fcw2; +input [47:0] fcw3; +input [47:0] fcw4; +input [47:0] fcw5; +input [47:0] fcw6; +input [47:0] fcw7; +input [47:0] fcw8; +input [47:0] fcw9; +input [47:0] fcw10; +input [47:0] fcw11; +input [47:0] fcw12; +input [47:0] fcw13; +input [47:0] fcw14; +input [47:0] fcw15; +input [47:0] fcw16; + + +reg [15:0] pha_r; +always@(posedge clk or negedge rstn) + if(!rstn) + pha_r <= 16'd0; + else + pha_r <= pha; + +wire [18:0] pha0; +wire [18:0] pha1; +wire [18:0] pha2; +wire [18:0] pha3; +wire [18:0] pha4; +wire [18:0] pha5; +wire [18:0] pha6; +wire [18:0] pha7; +wire [18:0] pha8; +wire [18:0] pha9; +wire [18:0] pha10; +wire [18:0] pha11; +wire [18:0] pha12; +wire [18:0] pha13; +wire [18:0] pha14; +wire [18:0] pha15; + +PIPE3_ADD_48BIT inst_pipe_0(.clk(clk),.rstn(rstn),.in(fcw1),.clr(clr),.ptw(pha_r),.s1(s1),.s2(s2),.s3(s3),.out(pha0)); +PIPE3_ADD_48BIT inst_pipe_1(.clk(clk),.rstn(rstn),.in(fcw2),.clr(clr),.ptw(pha_r),.s1(s1),.s2(s2),.s3(s3),.out(pha1)); +PIPE3_ADD_48BIT inst_pipe_2(.clk(clk),.rstn(rstn),.in(fcw3),.clr(clr),.ptw(pha_r),.s1(s1),.s2(s2),.s3(s3),.out(pha2)); +PIPE3_ADD_48BIT inst_pipe_3(.clk(clk),.rstn(rstn),.in(fcw4),.clr(clr),.ptw(pha_r),.s1(s1),.s2(s2),.s3(s3),.out(pha3)); +PIPE3_ADD_48BIT inst_pipe_4(.clk(clk),.rstn(rstn),.in(fcw5),.clr(clr),.ptw(pha_r),.s1(s1),.s2(s2),.s3(s3),.out(pha4)); +PIPE3_ADD_48BIT inst_pipe_5(.clk(clk),.rstn(rstn),.in(fcw6),.clr(clr),.ptw(pha_r),.s1(s1),.s2(s2),.s3(s3),.out(pha5)); +PIPE3_ADD_48BIT inst_pipe_6(.clk(clk),.rstn(rstn),.in(fcw7),.clr(clr),.ptw(pha_r),.s1(s1),.s2(s2),.s3(s3),.out(pha6)); +PIPE3_ADD_48BIT inst_pipe_7(.clk(clk),.rstn(rstn),.in(fcw8),.clr(clr),.ptw(pha_r),.s1(s1),.s2(s2),.s3(s3),.out(pha7)); +PIPE3_ADD_48BIT inst_pipe_8(.clk(clk),.rstn(rstn),.in(fcw9),.clr(clr),.ptw(pha_r),.s1(s1),.s2(s2),.s3(s3),.out(pha8)); +PIPE3_ADD_48BIT inst_pipe_9(.clk(clk),.rstn(rstn),.in(fcw10),.clr(clr),.ptw(pha_r),.s1(s1),.s2(s2),.s3(s3),.out(pha9)); +PIPE3_ADD_48BIT inst_pipe_10(.clk(clk),.rstn(rstn),.in(fcw11),.clr(clr),.ptw(pha_r),.s1(s1),.s2(s2),.s3(s3),.out(pha10)); +PIPE3_ADD_48BIT inst_pipe_11(.clk(clk),.rstn(rstn),.in(fcw12),.clr(clr),.ptw(pha_r),.s1(s1),.s2(s2),.s3(s3),.out(pha11)); +PIPE3_ADD_48BIT inst_pipe_12(.clk(clk),.rstn(rstn),.in(fcw13),.clr(clr),.ptw(pha_r),.s1(s1),.s2(s2),.s3(s3),.out(pha12)); +PIPE3_ADD_48BIT inst_pipe_13(.clk(clk),.rstn(rstn),.in(fcw14),.clr(clr),.ptw(pha_r),.s1(s1),.s2(s2),.s3(s3),.out(pha13)); +PIPE3_ADD_48BIT inst_pipe_14(.clk(clk),.rstn(rstn),.in(fcw15),.clr(clr),.ptw(pha_r),.s1(s1),.s2(s2),.s3(s3),.out(pha14)); +PIPE3_ACC_48BIT inst_pipe_15(.clk(clk),.rstn(rstn),.in(fcw16),.clr(clr_acc),.ptw(pha),.s_o_1(s1_o),.s_o_2(s2_o),.s_o_3(s3_o),.s_i_1(s1),.s_i_2(s2),.s_i_3(s3),.out(pha15)); + +PH2AMP inst_ph2amp_0( + .clk(clk) , + .rstn(rstn) , + .pha_map(pha0) , + .sin_o(sin_0) , + .cos_o(cos_0) + ); +PH2AMP inst_ph2amp_1( + .clk(clk) , + .rstn(rstn) , + .pha_map(pha1) , + .sin_o(sin_1) , + .cos_o(cos_1) + ); +PH2AMP inst_ph2amp_2( + .clk(clk) , + .rstn(rstn) , + .pha_map(pha2) , + .sin_o(sin_2) , + .cos_o(cos_2) + ); +PH2AMP inst_ph2amp_3( + .clk(clk) , + .rstn(rstn) , + .pha_map(pha3) , + .sin_o(sin_3) , + .cos_o(cos_3) + ); +PH2AMP inst_ph2amp_4( + .clk(clk) , + .rstn(rstn) , + .pha_map(pha4) , + .sin_o(sin_4) , + .cos_o(cos_4) + ); +PH2AMP inst_ph2amp_5( + .clk(clk) , + .rstn(rstn) , + .pha_map(pha5) , + .sin_o(sin_5) , + .cos_o(cos_5) + ); +PH2AMP inst_ph2amp_6( + .clk(clk) , + .rstn(rstn) , + .pha_map(pha6) , + .sin_o(sin_6) , + .cos_o(cos_6) + ); +PH2AMP inst_ph2amp_7( + .clk(clk) , + .rstn(rstn) , + .pha_map(pha7) , + .sin_o(sin_7) , + .cos_o(cos_7) + ); + +PH2AMP inst_ph2amp_8( + .clk(clk) , + .rstn(rstn) , + .pha_map(pha8) , + .sin_o(sin_8) , + .cos_o(cos_8) + ); +PH2AMP inst_ph2amp_9( + .clk(clk) , + .rstn(rstn) , + .pha_map(pha9) , + .sin_o(sin_9) , + .cos_o(cos_9) + ); +PH2AMP inst_ph2amp_10( + .clk(clk) , + .rstn(rstn) , + .pha_map(pha10) , + .sin_o(sin_10) , + .cos_o(cos_10) + ); +PH2AMP inst_ph2amp_11( + .clk(clk) , + .rstn(rstn) , + .pha_map(pha11) , + .sin_o(sin_11) , + .cos_o(cos_11) + ); +PH2AMP inst_ph2amp_12( + .clk(clk) , + .rstn(rstn) , + .pha_map(pha12) , + .sin_o(sin_12) , + .cos_o(cos_12) + ); +PH2AMP inst_ph2amp_13( + .clk(clk) , + .rstn(rstn) , + .pha_map(pha13) , + .sin_o(sin_13) , + .cos_o(cos_13) + ); +PH2AMP inst_ph2amp_14( + .clk(clk) , + .rstn(rstn) , + .pha_map(pha14) , + .sin_o(sin_14) , + .cos_o(cos_14) + ); +PH2AMP inst_ph2amp_15( + .clk(clk) , + .rstn(rstn) , + .pha_map(pha15) , + .sin_o(sin_15) , + .cos_o(cos_15) + ); + + +endmodule diff --git a/rtl/nco/p_nco_ch1.v b/rtl/nco/p_nco_ch1.v new file mode 100644 index 0000000..c25c1e8 --- /dev/null +++ b/rtl/nco/p_nco_ch1.v @@ -0,0 +1,65 @@ +module P_NCO_CH1( + clk, + rstn, + clr, + clr_acc, + pha, + + s1, + s2, + s3, + + s1_o, + s2_o, + s3_o, + + fcw, + + cos, + sin + ); + +input clk; +input rstn; +input clr; +input clr_acc; +input [15:0] pha; + +input [15:0] s1; +input [15:0] s2; +input [15:0] s3; + +output [15:0] s1_o; +output [15:0] s2_o; +output [15:0] s3_o; + +output [15:0] cos; +output [15:0] sin; + + +input [47:0] fcw; + + +reg [15:0] pha_r; +always@(posedge clk or negedge rstn) + if(!rstn) + pha_r <= 16'd0; + else + pha_r <= pha; + + + + +wire [18:0] pha0; + +PIPE3_ACC_48BIT inst_pipe(.clk(clk),.rstn(rstn),.in(fcw),.clr(clr_acc),.ptw(pha_r),.s_o_1(s1_o),.s_o_2(s2_o),.s_o_3(s3_o),.s_i_1(s1),.s_i_2(s2),.s_i_3(s3),.out(pha0)); + +PH2AMP inst_ph2amp_0( + .clk(clk) , + .rstn(rstn) , + .pha_map(pha0) , + .sin_o(sin) , + .cos_o(cos) + ); + +endmodule diff --git a/rtl/nco/ph2amp.v b/rtl/nco/ph2amp.v new file mode 100644 index 0000000..ef26d32 --- /dev/null +++ b/rtl/nco/ph2amp.v @@ -0,0 +1,83 @@ +module PH2AMP( + clk , + rstn , + pha_map , + sin_o , + cos_o + ); +input clk; +input rstn; +input [18:0] pha_map; + +output [15:0] sin_o; +output [15:0] cos_o; + +//wire [2:0] pha_indx_msb_s; +wire [14:0] sin_w; +SIN_OP inst_sin_op( + .clk(clk), + .rstn(rstn), + .pha_map(pha_map), + // .pha_indx_msb(pha_indx_msb_s), + .sin_op_o(sin_w) + ); +wire [2:0] pha_indx_msb_c; +wire [14:0] cos_w; +COS_OP inst_cos_op( + .clk(clk) , + .rstn(rstn) , + .pha_map(pha_map) , + .pha_indx_msb(pha_indx_msb_c), + .cos_op_o(cos_w) + ); +wire[15:0] cos_w_1; +wire[15:0] sin_w_1; +wire[15:0] cos_w_0; +wire[15:0] sin_w_0;//0:-,1:+ + +assign cos_w_1={1'b0,cos_w}; +assign sin_w_1={1'b0,sin_w}; +assign cos_w_0=(cos_w_1==16'd0)?16'd0:~cos_w_1+16'd1; +assign sin_w_0=(sin_w_1==16'd0)?16'd0:~sin_w_1+16'd1; + +reg[15:0] cos_tmp; +reg[15:0] sin_tmp; +always@(posedge clk) + case(pha_indx_msb_c)//synopsys parallel_case + 3'b000:begin + cos_tmp<=cos_w_1; + sin_tmp<=sin_w_1; + end + 3'b001:begin + cos_tmp<=sin_w_1; + sin_tmp<=cos_w_1; + end + 3'b010:begin + cos_tmp<=sin_w_0; + sin_tmp<=cos_w_1; + end + 3'b011:begin + cos_tmp<=cos_w_0; + sin_tmp<=sin_w_1; + end + 3'b100:begin + cos_tmp<=cos_w_0; + sin_tmp<=sin_w_0; + end + 3'b101:begin + cos_tmp<=sin_w_0; + sin_tmp<=cos_w_0; + end + 3'b110:begin + cos_tmp<=sin_w_1; + sin_tmp<=cos_w_0; + end + 3'b111:begin + cos_tmp<=cos_w_1; + sin_tmp<=sin_w_0; + end + endcase + +assign sin_o=sin_tmp; +assign cos_o=cos_tmp; +endmodule diff --git a/rtl/nco/pipe_acc_48bit.v b/rtl/nco/pipe_acc_48bit.v new file mode 100644 index 0000000..05ca377 --- /dev/null +++ b/rtl/nco/pipe_acc_48bit.v @@ -0,0 +1,64 @@ + + +module PIPE3_ACC_48BIT( + clk, + rstn, + in, + clr, + ptw, + s_i_1, + s_i_2, + s_i_3, + s_o_1, + s_o_2, + s_o_3, + out +); + +//--- + + input clk; + input rstn; + input [47:0] in; + input clr; + input [15:0] ptw; + + input [15:0] s_i_1; + input [15:0] s_i_2; + input [15:0] s_i_3; + + output [15:0] s_o_1; + output [15:0] s_o_2; + output [15:0] s_o_3; + output [18:0] out; + +//---------------------------------------------------------------------------------------------------- + + reg [47:0] acc; + always@(posedge clk or negedge rstn) + if(!rstn) + acc<=48'h0; + else if(clr) + acc<=48'h0; + else + acc<={s_i_1,s_i_2,s_i_3}+in; + + +//---------------------------------------------------------------------------------------------------- + wire [15:0] s1; + wire [15:0] s2; + wire [15:0] s3; + + assign s_o_1 = acc[47:32]; + assign s_o_2 = acc[31:16]; + assign s_o_3 = acc[15:0]; + + wire[18:0] pha_w; + assign pha_w=acc[47:29]; + reg[18:0] pha_r; + always@(posedge clk) + pha_r<=pha_w+{ptw,3'b0}; + + assign out=pha_r; +//END +endmodule diff --git a/rtl/nco/pipe_add_48bit.v b/rtl/nco/pipe_add_48bit.v new file mode 100644 index 0000000..aeb5aa0 --- /dev/null +++ b/rtl/nco/pipe_add_48bit.v @@ -0,0 +1,50 @@ + + +module PIPE3_ADD_48BIT( + clk, + rstn, + in, + clr, + ptw, + s1, + s2, + s3, + out +); + +//--- + + input clk; + input rstn; + input [47:0] in; + input clr; + input [15:0] ptw; + + input [15:0] s1; + input [15:0] s2; + input [15:0] s3; + output [18:0] out; + + +//---------------------------------------------------------------------------------------------------- + + reg [47:0] acc; + always@(posedge clk or negedge rstn) + if(!rstn) + acc<=48'h0; + else if(clr) + acc<=48'h0; + else + acc<={s1,s2,s3}+in; +//--- + +wire[18:0] pha_w; +assign pha_w=acc[47:29]; +reg[18:0] pha_r; +always@(posedge clk) + pha_r<=pha_w+{ptw,3'b0}; + + + assign out=pha_r; +//END +endmodule diff --git a/rtl/nco/sin_op.v b/rtl/nco/sin_op.v new file mode 100644 index 0000000..de9b6c4 --- /dev/null +++ b/rtl/nco/sin_op.v @@ -0,0 +1,144 @@ +module SIN_OP( + clk, + rstn, + pha_map, + // pha_indx_msb, + sin_op_o + ); + +input clk; +input rstn; +input[18:0] pha_map; +//output [2:0] pha_indx_msb; +output [14:0] sin_op_o; + +wire [2:0] pha_indx_msb_w; +assign pha_indx_msb_w=pha_map[18:16]; + +wire [15:0] pha_indx_lsb; +assign pha_indx_lsb=pha_map[15:0]; +wire [15:0] pha_op; +assign pha_op=pha_indx_msb_w[0]?(~pha_indx_lsb):pha_indx_lsb; + +wire [4:0] indx; +assign indx=pha_op[15:11]; +wire [10:0] x_w; +assign x_w=pha_op[10:0]; +wire [17:0] c0; +wire [11:0] c1; +wire [4:0] c2; + +COEF_S coef_s_inst1( + .index(indx) , + .C0_S(c0) , + .C1_S(c1) , + .C2_S(c2) + ); + +reg[17:0] c0_r1; +reg[17:0] c0_r2; +reg[17:0] c0_r3; +reg[17:0] c0_r4; +reg[17:0] c0_r5; +reg[17:0] c0_r6; +always@(posedge clk) + begin + c0_r1<=c0; + c0_r2<=c0_r1; + c0_r3<=c0_r2; + c0_r4<=c0_r3; + c0_r5<=c0_r4; + c0_r6<=c0_r5; + end +reg [11:0] c1_r1; +reg [11:0] c1_r2; +reg [11:0] c1_r3; +always@(posedge clk) + begin + c1_r1<=c1; + c1_r2<=c1_r1; + c1_r3<=c1_r2; + end +reg [4:0] c2_r1; +always@(posedge clk) + c2_r1<=c2; +reg[10:0] x_r1; +reg[10:0] x_r2; +reg[10:0] x_r3; +reg[10:0] x_r4; +always@(posedge clk) + begin + x_r1<=x_w; + x_r2<=x_r1; + x_r3<=x_r2; + x_r4<=x_r3; + end + +wire [15:0] c2x; + +DW_mult_pipe #(11,5,2,0,1) inst_mult_0( + .clk (clk ), + .rst_n (rstn ), + .en (1'b1 ), + .a (x_r1 ), + .b (c2_r1 ), + .tc (1'b0 ), + .product (c2x ) + ); + + +wire [4:0] c2x_w; +assign c2x_w=c2x[10]?(c2x[15:11]+5'd1):c2x[15:11]; +reg [11:0] c2xc1; +always@(posedge clk) + c2xc1<=c1_r2-c2x_w; + +wire [22:0] c2xc1x; + +DW_mult_pipe #(11,12,3,0,1) inst_mult_1( + .clk (clk ), + .rst_n (rstn ), + .en (1'b1 ), + .a (x_r3 ), + .b (c2xc1 ), + .tc (1'b0 ), + .product (c2xc1x ) + ); + +wire [12:0] c2xc1x_w; +assign c2xc1x_w=c2xc1x[9]?(c2xc1x[22:10]+13'd1):c2xc1x[22:10]; +reg [12:0] c2xc1x_r; +always@(posedge clk) + c2xc1x_r<=c2xc1x_w; +wire[17:0] c2xc1xc0; +assign c2xc1xc0=c0_r6+c2xc1x_r; +wire [14:0] c2xc1xc0_w; +assign c2xc1xc0_w=c2xc1xc0[2]?(c2xc1xc0[17:3]+13'd1):c2xc1xc0[17:3]; +reg [14:0] c2xc1xc0_r; +always@(posedge clk) + c2xc1xc0_r<=c2xc1xc0_w; + +assign sin_op_o=c2xc1xc0_r; +/* +reg[2:0] pha_indx_msb_r1; +reg[2:0] pha_indx_msb_r2; +reg[2:0] pha_indx_msb_r3; +reg[2:0] pha_indx_msb_r4; +reg[2:0] pha_indx_msb_r5; +reg[2:0] pha_indx_msb_r6; +reg[2:0] pha_indx_msb_r7; +always@(posedge clk) + begin + pha_indx_msb_r1<=pha_indx_msb_w; + pha_indx_msb_r2<=pha_indx_msb_r1; + pha_indx_msb_r3<=pha_indx_msb_r2; + pha_indx_msb_r4<=pha_indx_msb_r3; + pha_indx_msb_r5<=pha_indx_msb_r4; + pha_indx_msb_r6<=pha_indx_msb_r5; + pha_indx_msb_r7<=pha_indx_msb_r6; + end + +end +assign pha_indx_msb=pha_indx_msb_r7; +*/ +endmodule diff --git a/rtl/perips/DW03_updn_ctr.v b/rtl/perips/DW03_updn_ctr.v new file mode 100644 index 0000000..8f2688c --- /dev/null +++ b/rtl/perips/DW03_updn_ctr.v @@ -0,0 +1,126 @@ +//////////////////////////////////////////////////////////////////////////////// +// +// This confidential and proprietary software may be used only +// as authorized by a licensing agreement from Synopsys Inc. +// In the event of publication, the following notice is applicable: +// +// (C) COPYRIGHT 1994 - 2015 SYNOPSYS INC. +// ALL RIGHTS RESERVED +// +// The entire notice above must be reproduced on all authorized +// copies. +// +// AUTHOR: Anatoly Sokhatsky July 10, 1994 +// +// VERSION: Simulation Architecture +// +// DesignWare_version: 0781642f +// DesignWare_release: K-2015.06-DWBB_201506.0 +// +//////////////////////////////////////////////////////////////////////////////// +//----------------------------------------------------------------------------------- +// +// ABSTRACT: Up/Down Counter +// parameterizable wordlength (width > 0) +// clk - positive edge-triggering clock +// reset - asynchronous reset (active low) +// data - data load input +// cen - counter enable +// count - counter state +// +// MODIFIED : GN Feb. 16th, 1996 +// changed dw03 to DW03 +// remove $generic +// defined paramter = 8 +// +// RJK June 19, 1997 +// Corrected faulty tercnt detection mechanism +// +// Rong Sep. 1999 +// Add x-handling +// +// RJK May 17, 2000 +// Updated to latest coding style to avoid blocking vs. +// nonblocking assignment problems (STAR 103980) +//------------------------------------------------------------------------------- + +module DW03_updn_ctr ( + // input ports + data, // data used for load operation + up_dn, // up/down control input (0=down, 1-up) + load, // load operation control input (active low) + cen, // count enable control input (active high enable) + clk, // clock input + reset, // asynchronous reset input (active low) + + // output ports + count, // count value output + tercnt // terminal count output flag (active high) + ); + +parameter width = 8; + +// port list declaration in order +input [width-1 : 0] data; +input up_dn, load, cen, clk, reset; +output [width-1 : 0] count; +output tercnt; + +// synopsys translate_off + +reg [width-1 : 0] cur_state; +wire [width-1 : 0] next_state; + + assign count = cur_state; + + + always @ (posedge clk or negedge reset) begin : P_clk_registers + + if (reset === 1'b0) + cur_state <= {width{1'b0}}; + + else begin + + if (reset === 1'b1) + cur_state <= next_state; + + else + cur_state <= {width{reset ^ reset}}; + + end + end // P_clk_registers + + + assign next_state = (load == 1'b0)? data | {width{1'b0}} : + ( (cen == 1'b0)? cur_state : + ( (up_dn == 1'b0)? cur_state + {width{1'b1}} : + cur_state - {width{1'b1}} ) ); + + + assign tercnt = (up_dn == 1'b0)? ( (cur_state == {width{1'b0}})? 1'b1 : 1'b0 ) : + ( (cur_state == {width{1'b1}})? 1'b1 : 1'b0 ); + + + + initial begin : parameter_check + + + if ( width < 1 ) begin + $display( + "ERROR: %m :\n Invalid value (%d) for parameter width (lower bound: 1 )", + width ); + $finish; + end + + end // parameter_check + + + always @ (clk) begin : P_monitor_clk + if ( (clk !== 1'b0) && (clk !== 1'b1) && ($time > 0) ) + $display( "WARNING: %m :\n at time = %t, detected unknown value, %b, on clk input.", + $time, clk ); + end // P_monitor_clk + +// synopsys translate_on + +endmodule // DW03_updn_ctr diff --git a/rtl/perips/mcu_regfile.sv b/rtl/perips/mcu_regfile.sv new file mode 100644 index 0000000..9f4a013 --- /dev/null +++ b/rtl/perips/mcu_regfile.sv @@ -0,0 +1,819 @@ +//+FHDR-------------------------------------------------------------------------------------------------------- +// Company: +//----------------------------------------------------------------------------------------------------------------- +// File Name : mcu_regfile.v +// Department : +// Author : PWY +// Author's Tel : +//----------------------------------------------------------------------------------------------------------------- +// Relese History +// Version Date Author Description +// 0.1 2024-03-13 PWY MCU dedicated register file +//----------------------------------------------------------------------------------------------------------------- +// Keywords : +// +//----------------------------------------------------------------------------------------------------------------- +// Parameter +// +//----------------------------------------------------------------------------------------------------------------- +// Purpose : +// +//----------------------------------------------------------------------------------------------------------------- +// Target Device: +// Tool versions: +//----------------------------------------------------------------------------------------------------------------- +// Reuse Issues +// Reset Strategy: +// Clock Domains: +// Critical Timing: +// Asynchronous I/F: +// Synthesizable (y/n): +// Other: +//-FHDR-------------------------------------------------------------------------------------------------------- + +// ----------------------------------------------------------- +// -- Register address offset macros +// ----------------------------------------------------------- +//MCU parameter register 0 +`define MCUPARAR0 16'h00 +//MCU parameter register 1 +`define MCUPARAR1 16'h04 +//MCU parameter register 2 +`define MCUPARAR2 16'h08 +//MCU parameter register 3 +`define MCUPARAR3 16'h0C +//MCU result register 0 +`define MCURESR0 16'h10 +//MCU result register 1 +`define MCURESR1 16'h14 +//MCU result register 2 +`define MCURESR2 16'h18 +//MCU result register 3 +`define MCURESR3 16'h1C +//carrier frequency register 0 +`define CWFR0 16'h40 +//carrier frequency register 1 +`define CWFR1 16'h44 +//carrier frequency register 2 +`define CWFR2 16'h48 +//carrier frequency register 3 +`define CWFR3 16'h4C +//carrier phase zeroing register +`define CWPRR 16'h50 +//Gate-attached phase register 0 +`define GAPR0 16'h54 +//Gate-attached phase register 1 +`define GAPR1 16'h58 +//Gate-attached phase register 2 +`define GAPR2 16'h5C +//Gate-attached phase register 3 +`define GAPR3 16'h60 +//Gate-attached phase register 4 +`define GAPR4 16'h64 +//Gate-attached phase register 5 +`define GAPR5 16'h68 +//Gate-attached phase register 6 +`define GAPR6 16'h6C +//Gate-attached phase register 7 +`define GAPR7 16'h70 +//Line correction phase register +`define LCPR 16'h74 +//Amplitude register 0 +`define AMPR0 16'h78 +//Amplitude register 1 +`define AMPR1 16'h7C +//Amplitude register 2 +`define AMPR2 16'h80 +//Amplitude register 3 +`define AMPR3 16'h84 +//Bias Register 0 +`define BIASR0 16'h88 +//Bias Register 1 +`define BIASR1 16'h8C +//Bias Register 2 +`define BIASR2 16'h90 +//Bias Register 3 +`define BIASR3 16'h94 +//Run-time register +`define RTIMR 16'h98 +//Instruction count register +`define ICNTR 16'h9C +//Feedback state information register +`define FSIR 16'hA0 + +module mcu_regfile ( + //system port + input clk // System Main Clock + ,input rst_n // Spi Reset active low + //rw op port + ,input [31 :0] wrdata // write data + ,input wren // write enable + ,input [3 :0] wrmask + ,input [15 :0] rwaddr // read & write address + ,input rden // read enable + ,output [31 :0] rddata // read data + ,input [1 :0] fb_st_info + ,input [31 :0] run_time + ,input [31 :0] instr_num + //MCU and SPI interface for interaction + ,input [31 :0] mcu_param [3:0] // MCU parameter 0~3 + ,output [31 :0] mcu_result [3:0] // MCU result 0~3 + //lookup table data + ,output [31 :0] mcu_cwfr [3:0] // Carrier frequency ctrl word 0~3 + ,output [15 :0] mcu_gapr [7:0] // Carrier phase ctrl word 0~3 + ,output [15 :0] mcu_ampr [3:0] // Carrier Amplitude 0~3 + ,output [15 :0] mcu_baisr [3:0] // Carrier Bais 0~3 + //CFG Port + ,output mcu_nco_pha_clr + ,output [15 :0] mcu_rz_pha +); + +localparam L = 1'b0, + H = 1'b1; + +// ------------------------------------------------------ +// -- Register enable (select) wires +// ------------------------------------------------------ +wire mcuparar0en ; // MCUPARAR0 select +wire mcuparar1en ; // MCUPARAR1 select +wire mcuparar2en ; // MCUPARAR2 select +wire mcuparar3en ; // MCUPARAR3 select +wire mcuresr0en ; // MCURESR0 select +wire mcuresr1en ; // MCURESR1 select +wire mcuresr2en ; // MCURESR2 select +wire mcuresr3en ; // MCURESR3 select +wire cwfr0en ; // CWFR0 select +wire cwfr1en ; // CWFR1 select +wire cwfr2en ; // CWFR2 select +wire cwfr3en ; // CWFR3 select +wire cwprren ; // CWPRR select +wire gapr0en ; // GAPR0 select +wire gapr1en ; // GAPR1 select +wire gapr2en ; // GAPR2 select +wire gapr3en ; // GAPR3 select +wire gapr4en ; // GAPR4 select +wire gapr5en ; // GAPR5 select +wire gapr6en ; // GAPR6 select +wire gapr7en ; // GAPR7 select +wire lcpren ; // LCPR select +wire ampr0en ; // AMPR0 select +wire ampr1en ; // AMPR1 select +wire ampr2en ; // AMPR2 select +wire ampr3en ; // AMPR3 select +wire baisr0en ; // BIASR0 select +wire baisr1en ; // BIASR1 select +wire baisr2en ; // BIASR2 select +wire baisr3en ; // BIASR3 select +wire rtimren ; // RTIMR select +wire icntren ; // ICNTR select +wire fsiren ; // FSIR select + +// ------------------------------------------------------ +// -- Register write enable wires +// ------------------------------------------------------ +wire mcuresr0we ; // MCURESR0 write enable +wire mcuresr1we ; // MCURESR1 write enable +wire mcuresr2we ; // MCURESR2 write enable +wire mcuresr3we ; // MCURESR3 write enable +wire cwfr0we ; // CWFR0 write enable +wire cwfr1we ; // CWFR1 write enable +wire cwfr2we ; // CWFR2 write enable +wire cwfr3we ; // CWFR3 write enable +wire cwprrwe ; // CWPRR write enable +wire gapr0we ; // GAPR0 write enable +wire gapr1we ; // GAPR1 write enable +wire gapr2we ; // GAPR2 write enable +wire gapr3we ; // GAPR3 write enable +wire gapr4we ; // GAPR4 write enable +wire gapr5we ; // GAPR5 write enable +wire gapr6we ; // GAPR6 write enable +wire gapr7we ; // GAPR7 write enable +wire lcprwe ; // LCPR write enable +wire ampr0we ; // AMPR0 write enable +wire ampr1we ; // AMPR1 write enable +wire ampr2we ; // AMPR2 write enable +wire ampr3we ; // AMPR3 write enable +wire baisr0we ; // BIASR0 write enable +wire baisr1we ; // BIASR1 write enable +wire baisr2we ; // BIASR2 write enable +wire baisr3we ; // BIASR3 write enable + +// ------------------------------------------------------ +// -- Misc wires +// ------------------------------------------------------ + +// ------------------------------------------------------ +// -- Misc Registers +// ------------------------------------------------------ +wire [31 :0] mcuparar0 ; // MCUPARAR0 register +wire [31 :0] mcuparar1 ; // MCUPARAR1 register +wire [31 :0] mcuparar2 ; // MCUPARAR2 register +wire [31 :0] mcuparar3 ; // MCUPARAR3 register +wire [31 :0] mcuresr0 ; // MCURESR0 register +wire [31 :0] mcuresr1 ; // MCURESR1 register +wire [31 :0] mcuresr2 ; // MCURESR2 register +wire [31 :0] mcuresr3 ; // MCURESR3 register +wire [31 :0] cwfr0 ; // CWFR0 register +wire [31 :0] cwfr1 ; // CWFR1 register +wire [31 :0] cwfr2 ; // CWFR2 register +wire [31 :0] cwfr3 ; // CWFR3 register +wire [0 :0] cwprr ; // CWPRR register +wire [15 :0] gapr0 ; // GAPR0 register////////////////////16bit but assign to 31:16? +wire [15 :0] gapr1 ; // GAPR1 register +wire [15 :0] gapr2 ; // GAPR2 register +wire [15 :0] gapr3 ; // GAPR3 register +wire [15 :0] gapr4 ; // GAPR4 register +wire [15 :0] gapr5 ; // GAPR5 register +wire [15 :0] gapr6 ; // GAPR6 register +wire [15 :0] gapr7 ; // GAPR7 register +wire [15 :0] lcpr ; // LCPR register +wire [15 :0] ampr0 ; // AMPR0 register +wire [15 :0] ampr1 ; // AMPR1 register +wire [15 :0] ampr2 ; // AMPR2 register +wire [15 :0] ampr3 ; // AMPR3 register +wire [15 :0] baisr0 ; // BIASR0 register +wire [15 :0] baisr1 ; // BIASR1 register +wire [15 :0] baisr2 ; // BIASR2 register +wire [15 :0] baisr3 ; // BIASR3 register +wire [31 :0] rtimr ; // RTIMR register +wire [31 :0] icntr ; // ICNTR register +wire [1 :0] fsir ; // FSIR register + +reg [31: 0] rddata_reg ; + +// ------------------------------------------------------ +// -- Address decoder +// +// Decodes the register address offset input(reg_addr) +// to produce enable (select) signals for each of the +// SW-registers in the macrocell. The reg_addr input +// is bits [15:0] of the paddr bus. +// ------------------------------------------------------ +assign mcuparar0en = (rwaddr[15:2] == `MCUPARAR0 >> 2) ? 1'b1 : 1'b0; +assign mcuparar1en = (rwaddr[15:2] == `MCUPARAR1 >> 2) ? 1'b1 : 1'b0; +assign mcuparar2en = (rwaddr[15:2] == `MCUPARAR2 >> 2) ? 1'b1 : 1'b0; +assign mcuparar3en = (rwaddr[15:2] == `MCUPARAR3 >> 2) ? 1'b1 : 1'b0; +assign mcuresr0en = (rwaddr[15:2] == `MCURESR0 >> 2) ? 1'b1 : 1'b0; +assign mcuresr1en = (rwaddr[15:2] == `MCURESR1 >> 2) ? 1'b1 : 1'b0; +assign mcuresr2en = (rwaddr[15:2] == `MCURESR2 >> 2) ? 1'b1 : 1'b0; +assign mcuresr3en = (rwaddr[15:2] == `MCURESR3 >> 2) ? 1'b1 : 1'b0; +assign cwfr0en = (rwaddr[15:2] == `CWFR0 >> 2) ? 1'b1 : 1'b0; +assign cwfr1en = (rwaddr[15:2] == `CWFR1 >> 2) ? 1'b1 : 1'b0; +assign cwfr2en = (rwaddr[15:2] == `CWFR2 >> 2) ? 1'b1 : 1'b0; +assign cwfr3en = (rwaddr[15:2] == `CWFR3 >> 2) ? 1'b1 : 1'b0; +assign cwprren = (rwaddr[15:2] == `CWPRR >> 2) ? 1'b1 : 1'b0; +assign gapr0en = (rwaddr[15:2] == `GAPR0 >> 2) ? 1'b1 : 1'b0; +assign gapr1en = (rwaddr[15:2] == `GAPR1 >> 2) ? 1'b1 : 1'b0; +assign gapr2en = (rwaddr[15:2] == `GAPR2 >> 2) ? 1'b1 : 1'b0; +assign gapr3en = (rwaddr[15:2] == `GAPR3 >> 2) ? 1'b1 : 1'b0; +assign gapr4en = (rwaddr[15:2] == `GAPR4 >> 2) ? 1'b1 : 1'b0; +assign gapr5en = (rwaddr[15:2] == `GAPR5 >> 2) ? 1'b1 : 1'b0; +assign gapr6en = (rwaddr[15:2] == `GAPR6 >> 2) ? 1'b1 : 1'b0; +assign gapr7en = (rwaddr[15:2] == `GAPR7 >> 2) ? 1'b1 : 1'b0; +assign lcpren = (rwaddr[15:2] == `LCPR >> 2) ? 1'b1 : 1'b0; +assign ampr0en = (rwaddr[15:2] == `AMPR0 >> 2) ? 1'b1 : 1'b0; +assign ampr1en = (rwaddr[15:2] == `AMPR1 >> 2) ? 1'b1 : 1'b0; +assign ampr2en = (rwaddr[15:2] == `AMPR2 >> 2) ? 1'b1 : 1'b0; +assign ampr3en = (rwaddr[15:2] == `AMPR3 >> 2) ? 1'b1 : 1'b0; +assign baisr0en = (rwaddr[15:2] == `BIASR0 >> 2) ? 1'b1 : 1'b0; +assign baisr1en = (rwaddr[15:2] == `BIASR1 >> 2) ? 1'b1 : 1'b0; +assign baisr2en = (rwaddr[15:2] == `BIASR2 >> 2) ? 1'b1 : 1'b0; +assign baisr3en = (rwaddr[15:2] == `BIASR3 >> 2) ? 1'b1 : 1'b0; +assign rtimren = (rwaddr[15:2] == `RTIMR >> 2) ? 1'b1 : 1'b0; +assign icntren = (rwaddr[15:2] == `ICNTR >> 2) ? 1'b1 : 1'b0; +assign fsiren = (rwaddr[15:2] == `FSIR >> 2) ? 1'b1 : 1'b0; + +// ------------------------------------------------------ +// -- Write enable signals +// +// Write enable signals for writable SW-registers. +// The write enable for each register is the ANDed +// result of the register enable and the input reg_wren +// ------------------------------------------------------ +assign mcuresr0we = mcuresr0en & wren; +assign mcuresr1we = mcuresr1en & wren; +assign mcuresr2we = mcuresr2en & wren; +assign mcuresr3we = mcuresr3en & wren; +assign cwfr0we = cwfr0en & wren; +assign cwfr1we = cwfr1en & wren; +assign cwfr2we = cwfr2en & wren; +assign cwfr3we = cwfr3en & wren; +assign cwprrwe = cwprren & wren; +assign gapr0we = gapr0en & wren; +assign gapr1we = gapr1en & wren; +assign gapr2we = gapr2en & wren; +assign gapr3we = gapr3en & wren; +assign gapr4we = gapr4en & wren; +assign gapr5we = gapr5en & wren; +assign gapr6we = gapr6en & wren; +assign gapr7we = gapr7en & wren; +assign lcprwe = lcpren & wren; +assign ampr0we = ampr0en & wren; +assign ampr1we = ampr1en & wren; +assign ampr2we = ampr2en & wren; +assign ampr3we = ampr3en & wren; +assign baisr0we = baisr0en & wren; +assign baisr1we = baisr1en & wren; +assign baisr2we = baisr2en & wren; +assign baisr3we = baisr3en & wren; + +// ------------------------------------------------------ +// -- mcuresr0 register +// +// Write mcuresr0 for 'MCURESR0' : 32-bit register +// Register is split into the following bit fields +// +// [31:0] --> mcuresr0 +// ------------------------------------------------------ +wire [31:0] mcuresr0_w; +assign mcuresr0_w[31:24] = wrmask[3] ? wrdata[31:24] : mcuresr0[31:24]; +assign mcuresr0_w[23:16] = wrmask[2] ? wrdata[23:16] : mcuresr0[23:16]; +assign mcuresr0_w[15 :8] = wrmask[1] ? wrdata[15 :8] : mcuresr0[15 :8]; +assign mcuresr0_w[7 :0] = wrmask[0] ? wrdata[7 :0] : mcuresr0[7 :0]; +sirv_gnrl_dfflr #(32) mcuresr0_dfflr (mcuresr0we, mcuresr0_w[31:0], mcuresr0, clk, rst_n); +// ------------------------------------------------------ +// -- mcuresr1 register +// +// Write mcuresr1 for 'MCURESR1' : 32-bit register +// Register is split into the following bit fields +// +// [31:0] --> mcuresr1 +// ------------------------------------------------------ +wire [31:0] mcuresr1_w; +assign mcuresr1_w[31:24] = wrmask[3] ? wrdata[31:24] : mcuresr1[31:24]; +assign mcuresr1_w[23:16] = wrmask[2] ? wrdata[23:16] : mcuresr1[23:16]; +assign mcuresr1_w[15 :8] = wrmask[1] ? wrdata[15 :8] : mcuresr1[15 :8]; +assign mcuresr1_w[7 :0] = wrmask[0] ? wrdata[7 :0] : mcuresr1[7 :0]; +sirv_gnrl_dfflr #(32) mcuresr1_dfflr (mcuresr1we, mcuresr1_w[31:0], mcuresr1, clk, rst_n); +// ------------------------------------------------------ +// -- mcuresr2 register +// +// Write mcuresr2 for 'MCURESR2' : 32-bit register +// Register is split into the following bit fields +// +// [31:0] --> mcuresr2 +// ------------------------------------------------------ +wire [31:0] mcuresr2_w; +assign mcuresr2_w[31:24] = wrmask[3] ? wrdata[31:24] : mcuresr2[31:24]; +assign mcuresr2_w[23:16] = wrmask[2] ? wrdata[23:16] : mcuresr2[23:16]; +assign mcuresr2_w[15 :8] = wrmask[1] ? wrdata[15 :8] : mcuresr2[15 :8]; +assign mcuresr2_w[7 :0] = wrmask[0] ? wrdata[7 :0] : mcuresr2[7 :0]; +sirv_gnrl_dfflr #(32) mcuresr2_dfflr (mcuresr2we, mcuresr2_w[31:0], mcuresr2, clk, rst_n); +// ------------------------------------------------------ +// -- mcuresr3 register +// +// Write mcuresr3 for 'MCURESR3' : 32-bit register +// Register is split into the following bit fields +// +// [31:0] --> mcuresr3 +// ------------------------------------------------------ +wire [31:0] mcuresr3_w; +assign mcuresr3_w[31:24] = wrmask[3] ? wrdata[31:24] : mcuresr3[31:24]; +assign mcuresr3_w[23:16] = wrmask[2] ? wrdata[23:16] : mcuresr3[23:16]; +assign mcuresr3_w[15 :8] = wrmask[1] ? wrdata[15 :8] : mcuresr3[15 :8]; +assign mcuresr3_w[7 :0] = wrmask[0] ? wrdata[7 :0] : mcuresr3[7 :0]; +sirv_gnrl_dfflr #(32) mcuresr3_dfflr (mcuresr3we, mcuresr3_w[31:0], mcuresr3, clk, rst_n); + +// ------------------------------------------------------ +// -- cwfr0 register +// +// Write cwfr0 for 'CWFR0' : 32-bit register +// Register is split into the following bit fields +// +// [31:0] --> cwfr0 +// ------------------------------------------------------ +wire [31:0] cwfr0_w; +assign cwfr0_w[31:24] = wrmask[3] ? wrdata[31:24] : cwfr0[31:24]; +assign cwfr0_w[23:16] = wrmask[2] ? wrdata[23:16] : cwfr0[23:16]; +assign cwfr0_w[15 :8] = wrmask[1] ? wrdata[15 :8] : cwfr0[15 :8]; +assign cwfr0_w[7 :0] = wrmask[0] ? wrdata[7 :0] : cwfr0[7 :0]; +sirv_gnrl_dfflr #(32) cwfr0_dfflr (cwfr0we, cwfr0_w[31:0], cwfr0, clk, rst_n); +// ------------------------------------------------------ +// -- cwfr1 register +// +// Write cwfr1 for 'CWFR1' : 32-bit register +// Register is split into the following bit fields +// +// [31:16] --> cwfr1 +// ------------------------------------------------------ +wire [31:0] cwfr1_w; +assign cwfr1_w[31:24] = wrmask[3] ? wrdata[31:24] : cwfr1[31:24]; +assign cwfr1_w[23:16] = wrmask[2] ? wrdata[23:16] : cwfr1[23:16]; +assign cwfr1_w[15 :8] = wrmask[1] ? wrdata[15 :8] : cwfr1[15 :8]; +assign cwfr1_w[7 :0] = wrmask[0] ? wrdata[7 :0] : cwfr1[7 :0]; +sirv_gnrl_dfflr #(32) cwfr1_dfflr (cwfr1we, cwfr1_w[31:0], cwfr1, clk, rst_n); +// ------------------------------------------------------ +// -- cwfr2 register +// +// Write cwfr2 for 'CWFR2' : 32-bit register +// Register is split into the following bit fields +// +// [31:16] --> cwfr2 +// ------------------------------------------------------ +wire [31:0] cwfr2_w; +assign cwfr2_w[31:24] = wrmask[3] ? wrdata[31:24] : cwfr2[31:24]; +assign cwfr2_w[23:16] = wrmask[2] ? wrdata[23:16] : cwfr2[23:16]; +assign cwfr2_w[15 :8] = wrmask[1] ? wrdata[15 :8] : cwfr2[15 :8]; +assign cwfr2_w[7 :0] = wrmask[0] ? wrdata[7 :0] : cwfr2[7 :0]; +sirv_gnrl_dfflr #(32) cwfr2_dfflr (cwfr2we, cwfr2_w[31:0], cwfr2, clk, rst_n); +// ------------------------------------------------------ +// -- cwfr3 register +// +// Write cwfr3 for 'CWFR3' : 32-bit register +// Register is split into the following bit fields +// +// [31:16] --> cwfr3 +// ------------------------------------------------------ +wire [31:0] cwfr3_w; +assign cwfr3_w[31:24] = wrmask[3] ? wrdata[31:24] : cwfr3[31:24]; +assign cwfr3_w[23:16] = wrmask[2] ? wrdata[23:16] : cwfr3[23:16]; +assign cwfr3_w[15 :8] = wrmask[1] ? wrdata[15 :8] : cwfr3[15 :8]; +assign cwfr3_w[7 :0] = wrmask[0] ? wrdata[7 :0] : cwfr3[7 :0]; +sirv_gnrl_dfflr #(32) cwfr3_dfflr (cwfr3we, cwfr3_w[31:0], cwfr3, clk, rst_n); + +// ------------------------------------------------------ +// -- cwprr register(self-clearing) +// +// Write cwprr for 'CWPRR' : 32-bit register +// Register is split into the following bit fields +// +// [0] --> cwprr +// ------------------------------------------------------ +wire cwprr_w = wrmask[0] & cwprrwe & wrdata[0]; + +sirv_gnrl_dffr #(1) cwprr_dffr (cwprr_w, cwprr, clk, rst_n); + +// ------------------------------------------------------ +// -- gapr0 register +// +// Write gapr0 for 'GAPR0' : 32-bit register +// Register is split into the following bit fields +// +// [31:16] --> gapr0 +// ------------------------------------------------------ +wire [31:0] gapr0_w; +assign gapr0_w[31:24] = wrmask[3] ? wrdata[31:24] : gapr0[15: 8];/////////////////////////////////////////////////////////////31:26->15:8 +assign gapr0_w[23:16] = wrmask[2] ? wrdata[23:16] : gapr0[ 7: 0];/////////////////////////////////////////////////////////////23:16->7:0 +sirv_gnrl_dfflr #(16) gapr0_dfflr (gapr0we, gapr0_w[31:16], gapr0, clk, rst_n); + +// ------------------------------------------------------ +// -- gapr1 register +// +// Write gapr1 for 'GAPR1' : 32-bit register +// Register is split into the following bit fields +// +// [31:16] --> gapr1 +// ------------------------------------------------------ +wire [31:0] gapr1_w; +assign gapr1_w[31:24] = wrmask[3] ? wrdata[31:24] : gapr1[15: 8];///////////////////////////////////////////////////////////// +assign gapr1_w[23:16] = wrmask[2] ? wrdata[23:16] : gapr1[ 7: 0];///////////////////////////////////////////////////////////// +sirv_gnrl_dfflr #(16) gapr1_dfflr (gapr1we, gapr1_w[31:16], gapr1, clk, rst_n); +// ------------------------------------------------------ +// -- gapr2 register +// +// Write gapr2 for 'GAPR2' : 32-bit register +// Register is split into the following bit fields +// +// [31:16] --> gapr2 +// ------------------------------------------------------ +wire [31:0] gapr2_w; +assign gapr2_w[31:24] = wrmask[3] ? wrdata[31:24] : gapr2[15: 8];///////////////////////////////////////////////////////////// +assign gapr2_w[23:16] = wrmask[2] ? wrdata[23:16] : gapr2[ 7: 0];///////////////////////////////////////////////////////////// +sirv_gnrl_dfflr #(16) gapr2_dfflr (gapr2we, gapr2_w[31:16], gapr2, clk, rst_n); +// ------------------------------------------------------ +// -- gapr3 register +// +// Write gapr3 for 'GAPR3' : 32-bit register +// Register is split into the following bit fields +// +// [31:16] --> gapr3 +// ------------------------------------------------------ +wire [31:0] gapr3_w; +assign gapr3_w[31:24] = wrmask[3] ? wrdata[31:24] : gapr3[15: 8];///////////////////////////////////////////////////////////// +assign gapr3_w[23:16] = wrmask[2] ? wrdata[23:16] : gapr3[ 7: 0];///////////////////////////////////////////////////////////// +sirv_gnrl_dfflr #(16) gapr3_dfflr (gapr3we, gapr3_w[31:16], gapr3, clk, rst_n); + +// ------------------------------------------------------ +// -- gapr4 register +// +// Write gapr4 for 'GAPR4' : 32-bit register +// Register is split into the following bit fields +// +// [31:16] --> gapr4 +// ------------------------------------------------------ +wire [31:0] gapr4_w; +assign gapr4_w[31:24] = wrmask[3] ? wrdata[31:24] : gapr4[15: 8];///////////////////////////////////////////////////////////// +assign gapr4_w[23:16] = wrmask[2] ? wrdata[23:16] : gapr4[ 7: 0];///////////////////////////////////////////////////////////// +sirv_gnrl_dfflr #(16) gapr4_dfflr (gapr4we, gapr4_w[31:16], gapr4, clk, rst_n); +// ------------------------------------------------------ +// -- gapr5 register +// +// Write gapr5 for 'GAPR5' : 32-bit register +// Register is split into the following bit fields +// +// [31:16] --> gapr5 +// ------------------------------------------------------ +wire [31:0] gapr5_w; +assign gapr5_w[31:24] = wrmask[3] ? wrdata[31:24] : gapr5[15: 8];///////////////////////////////////////////////////////////// +assign gapr5_w[23:16] = wrmask[2] ? wrdata[23:16] : gapr5[ 7: 0];///////////////////////////////////////////////////////////// +sirv_gnrl_dfflr #(16) gapr5_dfflr (gapr5we, gapr5_w[31:16], gapr5, clk, rst_n); +// ------------------------------------------------------ +// -- gapr6 register +// +// Write gapr6 for 'GAPR6' : 32-bit register +// Register is split into the following bit fields +// +// [31:16] --> gapr6 +// ------------------------------------------------------ +wire [31:0] gapr6_w; +assign gapr6_w[31:24] = wrmask[3] ? wrdata[31:24] : gapr6[15: 8];///////////////////////////////////////////////////////////// +assign gapr6_w[23:16] = wrmask[2] ? wrdata[23:16] : gapr6[ 7: 0];///////////////////////////////////////////////////////////// +sirv_gnrl_dfflr #(16) gapr6_dfflr (gapr6we, gapr6_w[31:16], gapr6, clk, rst_n); +// ------------------------------------------------------ +// -- gapr7 register +// +// Write gapr7 for 'GAPR7' : 32-bit register +// Register is split into the following bit fields +// +// [31:16] --> gapr7 +// ------------------------------------------------------ +wire [31:0] gapr7_w; +assign gapr7_w[31:24] = wrmask[3] ? wrdata[31:24] : gapr7[15: 8];///////////////////////////////////////////////////////////// +assign gapr7_w[23:16] = wrmask[2] ? wrdata[23:16] : gapr7[ 7: 0];///////////////////////////////////////////////////////////// +sirv_gnrl_dfflr #(16) gapr7_dfflr (gapr7we, gapr7_w[31:16], gapr7, clk, rst_n); + + +// ------------------------------------------------------ +// -- lcpr register +// +// Write lcpr for 'LCPR' : 32-bit register +// Register is split into the following bit fields +// +// [31:16] --> lcpr +// ------------------------------------------------------ +wire [31:0] lcpr_w; +assign lcpr_w[31:24] = wrmask[3] ? wrdata[31:24] : lcpr[15: 8];///////////////////////////////////////////////////////////// +assign lcpr_w[23:16] = wrmask[2] ? wrdata[23:16] : lcpr[ 7: 0];///////////////////////////////////////////////////////////// +sirv_gnrl_dfflr #(16) lcpr_dfflr (lcprwe, lcpr_w[31:16], lcpr, clk, rst_n); + +// ------------------------------------------------------ +// -- ampr0 register +// +// Write ampr0 for 'AMPR0' : 32-bit register +// Register is split into the following bit fields +// +// [31:16] --> ampr0 +// ------------------------------------------------------ +wire [31:0] ampr0_w; +assign ampr0_w[31:24] = wrmask[3] ? wrdata[31:24] : ampr0[15: 8];///////////////////////////////////////////////////////////// +assign ampr0_w[23:16] = wrmask[2] ? wrdata[23:16] : ampr0[ 7: 0];///////////////////////////////////////////////////////////// +sirv_gnrl_dfflr #(16) ampr0_dfflr (ampr0we, ampr0_w[31:16], ampr0, clk, rst_n); + +// ------------------------------------------------------ +// -- ampr1 register +// +// Write ampr1 for 'AMPR10' : 32-bit register +// Register is split into the following bit fields +// +// [31:16] --> ampr1 +// ------------------------------------------------------ +wire [31:0] ampr1_w; +assign ampr1_w[31:24] = wrmask[3] ? wrdata[31:24] : ampr1[15: 8];///////////////////////////////////////////////////////////// +assign ampr1_w[23:16] = wrmask[2] ? wrdata[23:16] : ampr1[ 7: 0];///////////////////////////////////////////////////////////// +sirv_gnrl_dfflr #(16) ampr1_dfflr (ampr1we, ampr1_w[31:16], ampr1, clk, rst_n); + +// ------------------------------------------------------ +// -- ampr2 register +// +// Write ampr2 for 'AMPR2' : 32-bit register +// Register is split into the following bit fields +// +// [31:16] --> ampr2 +// ------------------------------------------------------ +wire [31:0] ampr2_w; +assign ampr2_w[31:24] = wrmask[3] ? wrdata[31:24] : ampr2[15: 8];///////////////////////////////////////////////////////////// +assign ampr2_w[23:16] = wrmask[2] ? wrdata[23:16] : ampr2[ 7: 0];///////////////////////////////////////////////////////////// +sirv_gnrl_dfflr #(16) ampr2_dfflr (ampr2we, ampr2_w[31:16], ampr2, clk, rst_n); + +// ------------------------------------------------------ +// -- ampr3 register +// +// Write ampr3 for 'AMPR3' : 32-bit register +// Register is split into the following bit fields +// +// [31:16] --> ampr3 +// ------------------------------------------------------ +wire [31:0] ampr3_w; +assign ampr3_w[31:24] = wrmask[3] ? wrdata[31:24] : ampr3[15: 8];///////////////////////////////////////////////////////////// +assign ampr3_w[23:16] = wrmask[2] ? wrdata[23:16] : ampr3[ 7: 0];///////////////////////////////////////////////////////////// +sirv_gnrl_dfflr #(16) ampr3_dfflr (ampr3we, ampr3_w[31:16], ampr3, clk, rst_n); + + +// ------------------------------------------------------ +// -- baisr0 register +// +// Write baisr0 for 'BIASR0' : 32-bit register +// Register is split into the following bit fields +// +// [31:16] --> baisr0 +// ------------------------------------------------------ +wire [31:0] baisr0_w; +assign baisr0_w[31:24] = wrmask[3] ? wrdata[31:24] : baisr0[15: 8];///////////////////////////////////////////////////////////// +assign baisr0_w[23:16] = wrmask[2] ? wrdata[23:16] : baisr0[ 7: 0];///////////////////////////////////////////////////////////// +sirv_gnrl_dfflr #(16) baisr0_dfflr (baisr0we, baisr0_w[31:16], baisr0, clk, rst_n); +// ------------------------------------------------------ +// -- baisr1 register +// +// Write baisr1 for 'BIASR1' : 32-bit register +// Register is split into the following bit fields +// +// [31:16] --> baisr1 +// ------------------------------------------------------ +wire [31:0] baisr1_w; +assign baisr1_w[31:24] = wrmask[3] ? wrdata[31:24] : baisr1[15: 8];///////////////////////////////////////////////////////////// +assign baisr1_w[23:16] = wrmask[2] ? wrdata[23:16] : baisr1[ 7: 0];///////////////////////////////////////////////////////////// +sirv_gnrl_dfflr #(16) baisr1_dfflr (baisr1we, baisr1_w[31:16], baisr1, clk, rst_n); +// ------------------------------------------------------ +// -- baisr2 register +// +// Write baisr2 for 'BIASR2' : 32-bit register +// Register is split into the following bit fields +// +// [31:16] --> baisr2 +// ------------------------------------------------------ +wire [31:0] baisr2_w; +assign baisr2_w[31:24] = wrmask[3] ? wrdata[31:24] : baisr2[15: 8];///////////////////////////////////////////////////////////// +assign baisr2_w[23:16] = wrmask[2] ? wrdata[23:16] : baisr2[ 7: 0];///////////////////////////////////////////////////////////// +sirv_gnrl_dfflr #(16) baisr2_dfflr (baisr2we, baisr2_w[31:16], baisr2, clk, rst_n); +// ------------------------------------------------------ +// -- baisr3 register +// +// Write baisr3 for 'BIASR3' : 32-bit register +// Register is split into the following bit fields +// +// [31:16] --> baisr3 +// ------------------------------------------------------ +wire [31:0] baisr3_w; +assign baisr3_w[31:24] = wrmask[3] ? wrdata[31:24] : baisr3[15: 8];///////////////////////////////////////////////////////////// +assign baisr3_w[23:16] = wrmask[2] ? wrdata[23:16] : baisr3[ 7: 0];///////////////////////////////////////////////////////////// +sirv_gnrl_dfflr #(16) baisr3_dfflr (baisr3we, baisr3_w[31:16], baisr3, clk, rst_n); + + + +// ------------------------------------------------------ +// -- mcuparar0 +// ------------------------------------------------------ +sirv_gnrl_dffr #(32) mcuparar0_dffr (mcu_param[0], mcuparar0, clk, rst_n); +// ------------------------------------------------------ +// -- mcuparar1 +// ------------------------------------------------------ +sirv_gnrl_dffr #(32) mcuparar1_dffr (mcu_param[1], mcuparar1, clk, rst_n); +// ------------------------------------------------------ +// -- mcuparar2 +// ------------------------------------------------------ +sirv_gnrl_dffr #(32) mcuparar2_dffr (mcu_param[2], mcuparar2, clk, rst_n); +// ------------------------------------------------------ +// -- mcuparar3 +// ------------------------------------------------------ +sirv_gnrl_dffr #(32) mcuparar3_dffr (mcu_param[3], mcuparar3, clk, rst_n); + +// ------------------------------------------------------ +// -- rtimr +// ------------------------------------------------------ +sirv_gnrl_dffr #(32) rtimr_dffr (run_time, rtimr, clk, rst_n); + +// ------------------------------------------------------ +// -- icntr +// ------------------------------------------------------ +sirv_gnrl_dffr #(32) icntr_dffr (instr_num, icntr, clk, rst_n); + +// ------------------------------------------------------ +// -- fsir +// ------------------------------------------------------ +sirv_gnrl_dffr #(2) fsir_dffr (fb_st_info[1:0], fsir, clk, rst_n);////////////////////////////////////////////[1:0] + + + + + +// ------------------------------------------------------ +// -- Read data mux +// +// -- The data from the selected register is +// -- placed on a zero-padded 32-bit read data bus. +// ------------------------------------------------------ +always @(*) begin : RDDATA_PROC + rddata_reg = {32{1'b0}}; + if(mcuparar0en == H ) rddata_reg[31 :0] = mcuparar0 ; + if(mcuparar1en == H ) rddata_reg[31 :0] = mcuparar1 ; + if(mcuparar2en == H ) rddata_reg[31 :0] = mcuparar2 ; + if(mcuparar3en == H ) rddata_reg[31 :0] = mcuparar3 ; + if(mcuresr0en == H ) rddata_reg[31 :0] = mcuresr0 ; + if(mcuresr1en == H ) rddata_reg[31 :0] = mcuresr1 ; + if(mcuresr2en == H ) rddata_reg[31 :0] = mcuresr2 ; + if(mcuresr3en == H ) rddata_reg[31 :0] = mcuresr3 ; + if(cwfr0en == H ) rddata_reg[31 :0] = cwfr0 ; + if(cwfr1en == H ) rddata_reg[31 :0] = cwfr1 ; + if(cwfr2en == H ) rddata_reg[31 :0] = cwfr2 ; + if(cwfr3en == H ) rddata_reg[31 :0] = cwfr3 ; + if(cwprren == H ) rddata_reg[0 :0] = cwprr ; + if(gapr0en == H ) rddata_reg[31:16] = gapr0 ; + if(gapr1en == H ) rddata_reg[31:16] = gapr1 ; + if(gapr2en == H ) rddata_reg[31:16] = gapr2 ; + if(gapr3en == H ) rddata_reg[31:16] = gapr3 ; + if(gapr4en == H ) rddata_reg[31:16] = gapr4 ; + if(gapr5en == H ) rddata_reg[31:16] = gapr5 ; + if(gapr6en == H ) rddata_reg[31:16] = gapr6 ; + if(gapr7en == H ) rddata_reg[31:16] = gapr7 ; + if(lcpren == H ) rddata_reg[31:16] = lcpr ; + if(ampr0en == H ) rddata_reg[31:16] = ampr0 ; + if(ampr1en == H ) rddata_reg[31:16] = ampr1 ; + if(ampr2en == H ) rddata_reg[31:16] = ampr2 ; + if(ampr3en == H ) rddata_reg[31:16] = ampr3 ; + if(baisr0en == H ) rddata_reg[31:16] = baisr0 ; + if(baisr1en == H ) rddata_reg[31:16] = baisr1 ; + if(baisr2en == H ) rddata_reg[31:16] = baisr2 ; + if(baisr3en == H ) rddata_reg[31:16] = baisr3 ; + if(rtimren == H ) rddata_reg[31 :0] = rtimr ; + if(icntren == H ) rddata_reg[31 :0] = icntr ; + if(fsiren == H ) rddata_reg[1 :0] = fsir ; +end + +// ------------------------------------------------------ +// -- Output signals assignment +// ------------------------------------------------------ +//mcu result +assign mcu_result[0] = mcuresr0 ; +assign mcu_result[1] = mcuresr1 ; +assign mcu_result[2] = mcuresr2 ; +assign mcu_result[3] = mcuresr3 ; + +//nco_fwc lookup table output +assign mcu_cwfr[0] = cwfr0; +assign mcu_cwfr[1] = cwfr1; +assign mcu_cwfr[2] = cwfr2; +assign mcu_cwfr[3] = cwfr3; + +//nco_pha lookup table output +assign mcu_gapr[0] = gapr0; ////////////////////////////////////////////////16bit assign to 32bit(?) +assign mcu_gapr[1] = gapr1; +assign mcu_gapr[2] = gapr2; +assign mcu_gapr[3] = gapr3; +assign mcu_gapr[4] = gapr4; +assign mcu_gapr[5] = gapr5; +assign mcu_gapr[6] = gapr6; +assign mcu_gapr[7] = gapr7; + +//amp lookup table output +assign mcu_ampr[0] = ampr0; +assign mcu_ampr[1] = ampr1; +assign mcu_ampr[2] = ampr2; +assign mcu_ampr[3] = ampr3; + +//bais lookup table output +assign mcu_baisr[0] = baisr0; +assign mcu_baisr[1] = baisr1; +assign mcu_baisr[2] = baisr2; +assign mcu_baisr[3] = baisr3; + +//CFG Port +assign mcu_nco_pha_clr = cwprr; +assign mcu_rz_pha = lcpr; +//rddata +//assign rddata = rddata_reg ; +sirv_gnrl_dffr #(32) rddata_dffr (rddata_reg, rddata, clk, rst_n);//////////////////////// +endmodule + +`undef MCUPARAR0 +`undef MCUPARAR1 +`undef MCUPARAR2 +`undef MCUPARAR3 +`undef MCURESR0 +`undef MCURESR1 +`undef MCURESR2 +`undef MCURESR3 +`undef CWFR0 +`undef CWFR1 +`undef CWFR2 +`undef CWFR3 +`undef CWPRR +`undef GAPR0 +`undef GAPR1 +`undef GAPR2 +`undef GAPR3 +`undef GAPR4 +`undef GAPR5 +`undef GAPR6 +`undef GAPR7 +`undef LCPR +`undef AMPR0 +`undef AMPR1 +`undef AMPR2 +`undef AMPR3 +`undef BIASR0 +`undef BIASR1 +`undef BIASR2 +`undef BIASR3 +`undef RTIMR +`undef ICNTR +`undef FSIR diff --git a/rtl/perips/qbmcu_busdecoder.v b/rtl/perips/qbmcu_busdecoder.v new file mode 100644 index 0000000..eb7d160 --- /dev/null +++ b/rtl/perips/qbmcu_busdecoder.v @@ -0,0 +1,113 @@ +//+FHDR-------------------------------------------------------------------------------------------------------- +// Company: +//----------------------------------------------------------------------------------------------------------------- +// File Name : qbmcu_busdecoder.v +// Department : +// Author : PWY +// Author's Tel : +//----------------------------------------------------------------------------------------------------------------- +// Relese History +// Version Date Author Description +// 1.0 2022-08-25 PWY +//----------------------------------------------------------------------------------------------------------------- +// Keywords : +// +//----------------------------------------------------------------------------------------------------------------- +// Parameter +// +//----------------------------------------------------------------------------------------------------------------- +// Purpose : +// +//----------------------------------------------------------------------------------------------------------------- +// Target Device: +// Tool versions: +//----------------------------------------------------------------------------------------------------------------- +// Reuse Issues +// Reset Strategy: +// Clock Domains: +// Critical Timing: +// Asynchronous I/F: +// Synthesizable (y/n): +// Other: +//-FHDR-------------------------------------------------------------------------------------------------------- + +`include "../qubitmcu/qbmcu_defines.v" + +module qbmcu_busdecoder #( + parameter S0_BASEADDR = 32'h0010_0000 + ,parameter S1_BASEADDR = 32'h0020_0000 +)( + //rw op port + input wren // write enable + ,input [`QBMCU_XLEN/8-1 :0] wrmask // write mask + ,input [`QBMCU_XLEN-1 :0] wrdata // write data + ,input [`QBMCU_ADDR_SIZE-1:0] rwaddr // read & write addr + ,input rden // read enable + ,output [`QBMCU_XLEN-1 :0] rddata // read data + //data sram read and write signals + ,output s0_wren // s0 write enable + ,output [`QBMCU_XLEN/8-1 :0] s0_wrmask // write mask + ,output [`QBMCU_ADDR_SIZE-1:0] s0_rwaddr // s0 read & write addr + ,output [`QBMCU_XLEN-1 :0] s0_wrdata // s0 write data + ,output s0_rden // s0 read enable + ,input [`QBMCU_XLEN-1 :0] s0_rddata // s0 read data + //mcu perips reg read and write signals + ,output s1_wren // s1 write enable + ,output [`QBMCU_XLEN/8-1 :0] s1_wrmask // write mask + ,output [`QBMCU_ADDR_SIZE-1:0] s1_rwaddr // s1 read & write addr + ,output [`QBMCU_XLEN-1 :0] s1_wrdata // s1 write data + ,output s1_rden // s1 read enable + ,input [`QBMCU_XLEN-1 :0] s1_rddata // s1 read data +); + +wire s0_sel; +wire s1_sel; + +//s0_sel +assign s0_sel = (rwaddr[`QBMCU_ADDR_SIZE-1:16] == S0_BASEADDR >> 16); +//s1_sel +assign s1_sel = (rwaddr[`QBMCU_ADDR_SIZE-1:16] == S1_BASEADDR >> 16); + + +//s0_wren +assign s0_wren = s0_sel & wren; +//s1_wren +assign s1_wren = s1_sel & wren; + +//s0_wrmask +assign s0_wrmask = {`QBMCU_XLEN/8{s0_sel}} & wrmask; +//s1_wrmask +assign s1_wrmask = {`QBMCU_XLEN/8{s1_sel}} & wrmask; + +//s0_rden +assign s0_rden = s0_sel & rden; +//s1_rden +assign s1_rden = s1_sel & rden; + + +//s0_rwaddr +assign s0_rwaddr = {`QBMCU_ADDR_SIZE{s0_sel}} & rwaddr; +//s1_rwaddr +assign s1_rwaddr = {`QBMCU_ADDR_SIZE{s1_sel}} & rwaddr; + +//s0_wrdata +assign s0_wrdata = {`QBMCU_XLEN{s0_sel}} & wrdata; +//s1_wrdata +assign s1_wrdata = {`QBMCU_XLEN{s1_sel}} & wrdata; + +// ------------------------------------------------------ +// -- Read data mux +// +// -- The data from the selected register is +// -- placed on a zero-padded 32-bit read data bus. +// ------------------------------------------------------ + +wire [`QBMCU_XLEN-1:0] rddata_w = {`QBMCU_XLEN{s0_sel}} & s0_rddata + | {`QBMCU_XLEN{s1_sel}} & s1_rddata; + +//rddata +assign rddata = rddata_w; + +endmodule + +`include "../qubitmcu/qbmcu_undefines.v" \ No newline at end of file diff --git a/rtl/qubitmcu/mcu_regfile.sv b/rtl/qubitmcu/mcu_regfile.sv new file mode 100644 index 0000000..eeeba28 --- /dev/null +++ b/rtl/qubitmcu/mcu_regfile.sv @@ -0,0 +1,840 @@ +//+FHDR-------------------------------------------------------------------------------------------------------- +// Company: +//----------------------------------------------------------------------------------------------------------------- +// File Name : mcu_regfile.v +// Department : +// Author : PWY +// Author's Tel : +//----------------------------------------------------------------------------------------------------------------- +// Relese History +// Version Date Author Description +// 0.1 2024-03-13 PWY MCU dedicated register file +//----------------------------------------------------------------------------------------------------------------- +// Keywords : +// +//----------------------------------------------------------------------------------------------------------------- +// Parameter +// +//----------------------------------------------------------------------------------------------------------------- +// Purpose : +// +//----------------------------------------------------------------------------------------------------------------- +// Target Device: +// Tool versions: +//----------------------------------------------------------------------------------------------------------------- +// Reuse Issues +// Reset Strategy: +// Clock Domains: +// Critical Timing: +// Asynchronous I/F: +// Synthesizable (y/n): +// Other: +//-FHDR-------------------------------------------------------------------------------------------------------- + +// ----------------------------------------------------------- +// -- Register address offset macros +// ----------------------------------------------------------- +//MCU parameter register 0 +`define MCUPARAR0 16'h00 +//MCU parameter register 1 +`define MCUPARAR1 16'h04 +//MCU parameter register 2 +`define MCUPARAR2 16'h08 +//MCU parameter register 3 +`define MCUPARAR3 16'h0C +//MCU result register 0 +`define MCURESR0 16'h10 +//MCU result register 1 +`define MCURESR1 16'h14 +//MCU result register 2 +`define MCURESR2 16'h18 +//MCU result register 3 +`define MCURESR3 16'h1C +//carrier frequency register 0 +`define CWFR0 16'h40 +//carrier frequency register 1 +`define CWFR1 16'h44 +//carrier frequency register 2 +`define CWFR2 16'h48 +//carrier frequency register 3 +`define CWFR3 16'h4C +//carrier phase zeroing register +`define CWPRR 16'h50 +//Gate-attached phase register 0 +`define GAPR0 16'h54 +//Gate-attached phase register 1 +`define GAPR1 16'h58 +//Gate-attached phase register 2 +`define GAPR2 16'h5C +//Gate-attached phase register 3 +`define GAPR3 16'h60 +//Gate-attached phase register 4 +`define GAPR4 16'h64 +//Gate-attached phase register 5 +`define GAPR5 16'h68 +//Gate-attached phase register 6 +`define GAPR6 16'h6C +//Gate-attached phase register 7 +`define GAPR7 16'h70 +//Line correction phase register +`define LCPR 16'h74 +//Amplitude register 0 +`define AMPR0 16'h78 +//Amplitude register 1 +`define AMPR1 16'h7C +//Amplitude register 2 +`define AMPR2 16'h80 +//Amplitude register 3 +`define AMPR3 16'h84 +//Bias Register 0 +`define BIASR0 16'h88 +//Bias Register 1 +`define BIASR1 16'h8C +//Bias Register 2 +`define BIASR2 16'h90 +//Bias Register 3 +`define BIASR3 16'h94 +//Run-time register +`define RTIMR 16'h98 +//Instruction count register +`define ICNTR 16'h9C +//Feedback state information register +`define FSIR 16'hA0 +//Interpolator Selection Register +`define INTPSELR 16'hA4 + +module mcu_regfile ( + //system port + input clk // System Main Clock + ,input rst_n // Spi Reset active low + //rw op port + ,input [31 :0] wrdata // write data + ,input wren // write enable + ,input [3 :0] wrmask + ,input [15 :0] rwaddr // read & write address + ,input rden // read enable + ,output [31 :0] rddata // read data + ,input [1 :0] fb_st_info + ,input [31 :0] run_time + ,input [31 :0] instr_num + //MCU and SPI interface for interaction + ,input [31 :0] mcu_param [3:0] // MCU parameter 0~3 + ,output [31 :0] mcu_result [3:0] // MCU result 0~3 + //lookup table data + ,output [31 :0] mcu_cwfr [3:0] // Carrier frequency ctrl word 0~3 + ,output [15 :0] mcu_gapr [7:0] // Carrier phase ctrl word 0~3 + ,output [15 :0] mcu_ampr [3:0] // Carrier Amplitude 0~3 + ,output [15 :0] mcu_baisr [3:0] // Carrier Bais 0~3 + //CFG Port + ,output [1 :0] mcu_intp_sel //2'b00:HBF;2'b01:Nearest-neighbor interpolator; + ,output mcu_nco_pha_clr + ,output [15 :0] mcu_rz_pha +); + +localparam L = 1'b0, + H = 1'b1; + +// ------------------------------------------------------ +// -- Register enable (select) wires +// ------------------------------------------------------ +wire mcuparar0en ; // MCUPARAR0 select +wire mcuparar1en ; // MCUPARAR1 select +wire mcuparar2en ; // MCUPARAR2 select +wire mcuparar3en ; // MCUPARAR3 select +wire mcuresr0en ; // MCURESR0 select +wire mcuresr1en ; // MCURESR1 select +wire mcuresr2en ; // MCURESR2 select +wire mcuresr3en ; // MCURESR3 select +wire cwfr0en ; // CWFR0 select +wire cwfr1en ; // CWFR1 select +wire cwfr2en ; // CWFR2 select +wire cwfr3en ; // CWFR3 select +wire cwprren ; // CWPRR select +wire gapr0en ; // GAPR0 select +wire gapr1en ; // GAPR1 select +wire gapr2en ; // GAPR2 select +wire gapr3en ; // GAPR3 select +wire gapr4en ; // GAPR4 select +wire gapr5en ; // GAPR5 select +wire gapr6en ; // GAPR6 select +wire gapr7en ; // GAPR7 select +wire lcpren ; // LCPR select +wire ampr0en ; // AMPR0 select +wire ampr1en ; // AMPR1 select +wire ampr2en ; // AMPR2 select +wire ampr3en ; // AMPR3 select +wire baisr0en ; // BIASR0 select +wire baisr1en ; // BIASR1 select +wire baisr2en ; // BIASR2 select +wire baisr3en ; // BIASR3 select +wire rtimren ; // RTIMR select +wire icntren ; // ICNTR select +wire fsiren ; // FSIR select +wire intpselren ; // INTPSELR select + +// ------------------------------------------------------ +// -- Register write enable wires +// ------------------------------------------------------ +wire mcuresr0we ; // MCURESR0 write enable +wire mcuresr1we ; // MCURESR1 write enable +wire mcuresr2we ; // MCURESR2 write enable +wire mcuresr3we ; // MCURESR3 write enable +wire cwfr0we ; // CWFR0 write enable +wire cwfr1we ; // CWFR1 write enable +wire cwfr2we ; // CWFR2 write enable +wire cwfr3we ; // CWFR3 write enable +wire cwprrwe ; // CWPRR write enable +wire gapr0we ; // GAPR0 write enable +wire gapr1we ; // GAPR1 write enable +wire gapr2we ; // GAPR2 write enable +wire gapr3we ; // GAPR3 write enable +wire gapr4we ; // GAPR4 write enable +wire gapr5we ; // GAPR5 write enable +wire gapr6we ; // GAPR6 write enable +wire gapr7we ; // GAPR7 write enable +wire lcprwe ; // LCPR write enable +wire ampr0we ; // AMPR0 write enable +wire ampr1we ; // AMPR1 write enable +wire ampr2we ; // AMPR2 write enable +wire ampr3we ; // AMPR3 write enable +wire baisr0we ; // BIASR0 write enable +wire baisr1we ; // BIASR1 write enable +wire baisr2we ; // BIASR2 write enable +wire baisr3we ; // BIASR3 write enable +wire intpselrwe ; // INTPSELR select + +// ------------------------------------------------------ +// -- Misc wires +// ------------------------------------------------------ + +// ------------------------------------------------------ +// -- Misc Registers +// ------------------------------------------------------ +wire [31 :0] mcuparar0 ; // MCUPARAR0 register +wire [31 :0] mcuparar1 ; // MCUPARAR1 register +wire [31 :0] mcuparar2 ; // MCUPARAR2 register +wire [31 :0] mcuparar3 ; // MCUPARAR3 register +wire [31 :0] mcuresr0 ; // MCURESR0 register +wire [31 :0] mcuresr1 ; // MCURESR1 register +wire [31 :0] mcuresr2 ; // MCURESR2 register +wire [31 :0] mcuresr3 ; // MCURESR3 register +wire [31 :0] cwfr0 ; // CWFR0 register +wire [31 :0] cwfr1 ; // CWFR1 register +wire [31 :0] cwfr2 ; // CWFR2 register +wire [31 :0] cwfr3 ; // CWFR3 register +wire [0 :0] cwprr ; // CWPRR register +wire [15 :0] gapr0 ; // GAPR0 register////////////////////16bit but assign to 31:16? +wire [15 :0] gapr1 ; // GAPR1 register +wire [15 :0] gapr2 ; // GAPR2 register +wire [15 :0] gapr3 ; // GAPR3 register +wire [15 :0] gapr4 ; // GAPR4 register +wire [15 :0] gapr5 ; // GAPR5 register +wire [15 :0] gapr6 ; // GAPR6 register +wire [15 :0] gapr7 ; // GAPR7 register +wire [15 :0] lcpr ; // LCPR register +wire [15 :0] ampr0 ; // AMPR0 register +wire [15 :0] ampr1 ; // AMPR1 register +wire [15 :0] ampr2 ; // AMPR2 register +wire [15 :0] ampr3 ; // AMPR3 register +wire [15 :0] baisr0 ; // BIASR0 register +wire [15 :0] baisr1 ; // BIASR1 register +wire [15 :0] baisr2 ; // BIASR2 register +wire [15 :0] baisr3 ; // BIASR3 register +wire [31 :0] rtimr ; // RTIMR register +wire [31 :0] icntr ; // ICNTR register +wire [1 :0] fsir ; // FSIR register +wire [1 :0] intpselr ; // INTPSELR register + +reg [31: 0] rddata_reg ; + +// ------------------------------------------------------ +// -- Address decoder +// +// Decodes the register address offset input(reg_addr) +// to produce enable (select) signals for each of the +// SW-registers in the macrocell. The reg_addr input +// is bits [15:0] of the paddr bus. +// ------------------------------------------------------ +assign mcuparar0en = (rwaddr[15:2] == `MCUPARAR0 >> 2) ? 1'b1 : 1'b0; +assign mcuparar1en = (rwaddr[15:2] == `MCUPARAR1 >> 2) ? 1'b1 : 1'b0; +assign mcuparar2en = (rwaddr[15:2] == `MCUPARAR2 >> 2) ? 1'b1 : 1'b0; +assign mcuparar3en = (rwaddr[15:2] == `MCUPARAR3 >> 2) ? 1'b1 : 1'b0; +assign mcuresr0en = (rwaddr[15:2] == `MCURESR0 >> 2) ? 1'b1 : 1'b0; +assign mcuresr1en = (rwaddr[15:2] == `MCURESR1 >> 2) ? 1'b1 : 1'b0; +assign mcuresr2en = (rwaddr[15:2] == `MCURESR2 >> 2) ? 1'b1 : 1'b0; +assign mcuresr3en = (rwaddr[15:2] == `MCURESR3 >> 2) ? 1'b1 : 1'b0; +assign cwfr0en = (rwaddr[15:2] == `CWFR0 >> 2) ? 1'b1 : 1'b0; +assign cwfr1en = (rwaddr[15:2] == `CWFR1 >> 2) ? 1'b1 : 1'b0; +assign cwfr2en = (rwaddr[15:2] == `CWFR2 >> 2) ? 1'b1 : 1'b0; +assign cwfr3en = (rwaddr[15:2] == `CWFR3 >> 2) ? 1'b1 : 1'b0; +assign cwprren = (rwaddr[15:2] == `CWPRR >> 2) ? 1'b1 : 1'b0; +assign gapr0en = (rwaddr[15:2] == `GAPR0 >> 2) ? 1'b1 : 1'b0; +assign gapr1en = (rwaddr[15:2] == `GAPR1 >> 2) ? 1'b1 : 1'b0; +assign gapr2en = (rwaddr[15:2] == `GAPR2 >> 2) ? 1'b1 : 1'b0; +assign gapr3en = (rwaddr[15:2] == `GAPR3 >> 2) ? 1'b1 : 1'b0; +assign gapr4en = (rwaddr[15:2] == `GAPR4 >> 2) ? 1'b1 : 1'b0; +assign gapr5en = (rwaddr[15:2] == `GAPR5 >> 2) ? 1'b1 : 1'b0; +assign gapr6en = (rwaddr[15:2] == `GAPR6 >> 2) ? 1'b1 : 1'b0; +assign gapr7en = (rwaddr[15:2] == `GAPR7 >> 2) ? 1'b1 : 1'b0; +assign lcpren = (rwaddr[15:2] == `LCPR >> 2) ? 1'b1 : 1'b0; +assign ampr0en = (rwaddr[15:2] == `AMPR0 >> 2) ? 1'b1 : 1'b0; +assign ampr1en = (rwaddr[15:2] == `AMPR1 >> 2) ? 1'b1 : 1'b0; +assign ampr2en = (rwaddr[15:2] == `AMPR2 >> 2) ? 1'b1 : 1'b0; +assign ampr3en = (rwaddr[15:2] == `AMPR3 >> 2) ? 1'b1 : 1'b0; +assign baisr0en = (rwaddr[15:2] == `BIASR0 >> 2) ? 1'b1 : 1'b0; +assign baisr1en = (rwaddr[15:2] == `BIASR1 >> 2) ? 1'b1 : 1'b0; +assign baisr2en = (rwaddr[15:2] == `BIASR2 >> 2) ? 1'b1 : 1'b0; +assign baisr3en = (rwaddr[15:2] == `BIASR3 >> 2) ? 1'b1 : 1'b0; +assign rtimren = (rwaddr[15:2] == `RTIMR >> 2) ? 1'b1 : 1'b0; +assign icntren = (rwaddr[15:2] == `ICNTR >> 2) ? 1'b1 : 1'b0; +assign fsiren = (rwaddr[15:2] == `FSIR >> 2) ? 1'b1 : 1'b0; +assign intpselren = (rwaddr[15:2] == `INTPSELR >> 2) ? 1'b1 : 1'b0; + +// ------------------------------------------------------ +// -- Write enable signals +// +// Write enable signals for writable SW-registers. +// The write enable for each register is the ANDed +// result of the register enable and the input reg_wren +// ------------------------------------------------------ +assign mcuresr0we = mcuresr0en & wren; +assign mcuresr1we = mcuresr1en & wren; +assign mcuresr2we = mcuresr2en & wren; +assign mcuresr3we = mcuresr3en & wren; +assign cwfr0we = cwfr0en & wren; +assign cwfr1we = cwfr1en & wren; +assign cwfr2we = cwfr2en & wren; +assign cwfr3we = cwfr3en & wren; +assign cwprrwe = cwprren & wren; +assign gapr0we = gapr0en & wren; +assign gapr1we = gapr1en & wren; +assign gapr2we = gapr2en & wren; +assign gapr3we = gapr3en & wren; +assign gapr4we = gapr4en & wren; +assign gapr5we = gapr5en & wren; +assign gapr6we = gapr6en & wren; +assign gapr7we = gapr7en & wren; +assign lcprwe = lcpren & wren; +assign ampr0we = ampr0en & wren; +assign ampr1we = ampr1en & wren; +assign ampr2we = ampr2en & wren; +assign ampr3we = ampr3en & wren; +assign baisr0we = baisr0en & wren; +assign baisr1we = baisr1en & wren; +assign baisr2we = baisr2en & wren; +assign baisr3we = baisr3en & wren; +assign intpselrwe = intpselren & wren; + +// ------------------------------------------------------ +// -- mcuresr0 register +// +// Write mcuresr0 for 'MCURESR0' : 32-bit register +// Register is split into the following bit fields +// +// [31:0] --> mcuresr0 +// ------------------------------------------------------ +wire [31:0] mcuresr0_w; +assign mcuresr0_w[31:24] = wrmask[3] ? wrdata[31:24] : mcuresr0[31:24]; +assign mcuresr0_w[23:16] = wrmask[2] ? wrdata[23:16] : mcuresr0[23:16]; +assign mcuresr0_w[15 :8] = wrmask[1] ? wrdata[15 :8] : mcuresr0[15 :8]; +assign mcuresr0_w[7 :0] = wrmask[0] ? wrdata[7 :0] : mcuresr0[7 :0]; +sirv_gnrl_dfflr #(32) mcuresr0_dfflr (mcuresr0we, mcuresr0_w[31:0], mcuresr0, clk, rst_n); +// ------------------------------------------------------ +// -- mcuresr1 register +// +// Write mcuresr1 for 'MCURESR1' : 32-bit register +// Register is split into the following bit fields +// +// [31:0] --> mcuresr1 +// ------------------------------------------------------ +wire [31:0] mcuresr1_w; +assign mcuresr1_w[31:24] = wrmask[3] ? wrdata[31:24] : mcuresr1[31:24]; +assign mcuresr1_w[23:16] = wrmask[2] ? wrdata[23:16] : mcuresr1[23:16]; +assign mcuresr1_w[15 :8] = wrmask[1] ? wrdata[15 :8] : mcuresr1[15 :8]; +assign mcuresr1_w[7 :0] = wrmask[0] ? wrdata[7 :0] : mcuresr1[7 :0]; +sirv_gnrl_dfflr #(32) mcuresr1_dfflr (mcuresr1we, mcuresr1_w[31:0], mcuresr1, clk, rst_n); +// ------------------------------------------------------ +// -- mcuresr2 register +// +// Write mcuresr2 for 'MCURESR2' : 32-bit register +// Register is split into the following bit fields +// +// [31:0] --> mcuresr2 +// ------------------------------------------------------ +wire [31:0] mcuresr2_w; +assign mcuresr2_w[31:24] = wrmask[3] ? wrdata[31:24] : mcuresr2[31:24]; +assign mcuresr2_w[23:16] = wrmask[2] ? wrdata[23:16] : mcuresr2[23:16]; +assign mcuresr2_w[15 :8] = wrmask[1] ? wrdata[15 :8] : mcuresr2[15 :8]; +assign mcuresr2_w[7 :0] = wrmask[0] ? wrdata[7 :0] : mcuresr2[7 :0]; +sirv_gnrl_dfflr #(32) mcuresr2_dfflr (mcuresr2we, mcuresr2_w[31:0], mcuresr2, clk, rst_n); +// ------------------------------------------------------ +// -- mcuresr3 register +// +// Write mcuresr3 for 'MCURESR3' : 32-bit register +// Register is split into the following bit fields +// +// [31:0] --> mcuresr3 +// ------------------------------------------------------ +wire [31:0] mcuresr3_w; +assign mcuresr3_w[31:24] = wrmask[3] ? wrdata[31:24] : mcuresr3[31:24]; +assign mcuresr3_w[23:16] = wrmask[2] ? wrdata[23:16] : mcuresr3[23:16]; +assign mcuresr3_w[15 :8] = wrmask[1] ? wrdata[15 :8] : mcuresr3[15 :8]; +assign mcuresr3_w[7 :0] = wrmask[0] ? wrdata[7 :0] : mcuresr3[7 :0]; +sirv_gnrl_dfflr #(32) mcuresr3_dfflr (mcuresr3we, mcuresr3_w[31:0], mcuresr3, clk, rst_n); + +// ------------------------------------------------------ +// -- cwfr0 register +// +// Write cwfr0 for 'CWFR0' : 32-bit register +// Register is split into the following bit fields +// +// [31:0] --> cwfr0 +// ------------------------------------------------------ +wire [31:0] cwfr0_w; +assign cwfr0_w[31:24] = wrmask[3] ? wrdata[31:24] : cwfr0[31:24]; +assign cwfr0_w[23:16] = wrmask[2] ? wrdata[23:16] : cwfr0[23:16]; +assign cwfr0_w[15 :8] = wrmask[1] ? wrdata[15 :8] : cwfr0[15 :8]; +assign cwfr0_w[7 :0] = wrmask[0] ? wrdata[7 :0] : cwfr0[7 :0]; +sirv_gnrl_dfflr #(32) cwfr0_dfflr (cwfr0we, cwfr0_w[31:0], cwfr0, clk, rst_n); +// ------------------------------------------------------ +// -- cwfr1 register +// +// Write cwfr1 for 'CWFR1' : 32-bit register +// Register is split into the following bit fields +// +// [31:16] --> cwfr1 +// ------------------------------------------------------ +wire [31:0] cwfr1_w; +assign cwfr1_w[31:24] = wrmask[3] ? wrdata[31:24] : cwfr1[31:24]; +assign cwfr1_w[23:16] = wrmask[2] ? wrdata[23:16] : cwfr1[23:16]; +assign cwfr1_w[15 :8] = wrmask[1] ? wrdata[15 :8] : cwfr1[15 :8]; +assign cwfr1_w[7 :0] = wrmask[0] ? wrdata[7 :0] : cwfr1[7 :0]; +sirv_gnrl_dfflr #(32) cwfr1_dfflr (cwfr1we, cwfr1_w[31:0], cwfr1, clk, rst_n); +// ------------------------------------------------------ +// -- cwfr2 register +// +// Write cwfr2 for 'CWFR2' : 32-bit register +// Register is split into the following bit fields +// +// [31:16] --> cwfr2 +// ------------------------------------------------------ +wire [31:0] cwfr2_w; +assign cwfr2_w[31:24] = wrmask[3] ? wrdata[31:24] : cwfr2[31:24]; +assign cwfr2_w[23:16] = wrmask[2] ? wrdata[23:16] : cwfr2[23:16]; +assign cwfr2_w[15 :8] = wrmask[1] ? wrdata[15 :8] : cwfr2[15 :8]; +assign cwfr2_w[7 :0] = wrmask[0] ? wrdata[7 :0] : cwfr2[7 :0]; +sirv_gnrl_dfflr #(32) cwfr2_dfflr (cwfr2we, cwfr2_w[31:0], cwfr2, clk, rst_n); +// ------------------------------------------------------ +// -- cwfr3 register +// +// Write cwfr3 for 'CWFR3' : 32-bit register +// Register is split into the following bit fields +// +// [31:16] --> cwfr3 +// ------------------------------------------------------ +wire [31:0] cwfr3_w; +assign cwfr3_w[31:24] = wrmask[3] ? wrdata[31:24] : cwfr3[31:24]; +assign cwfr3_w[23:16] = wrmask[2] ? wrdata[23:16] : cwfr3[23:16]; +assign cwfr3_w[15 :8] = wrmask[1] ? wrdata[15 :8] : cwfr3[15 :8]; +assign cwfr3_w[7 :0] = wrmask[0] ? wrdata[7 :0] : cwfr3[7 :0]; +sirv_gnrl_dfflr #(32) cwfr3_dfflr (cwfr3we, cwfr3_w[31:0], cwfr3, clk, rst_n); + +// ------------------------------------------------------ +// -- cwprr register(self-clearing) +// +// Write cwprr for 'CWPRR' : 32-bit register +// Register is split into the following bit fields +// +// [0] --> cwprr +// ------------------------------------------------------ +wire cwprr_w = wrmask[0] & cwprrwe & wrdata[0]; + +sirv_gnrl_dffr #(1) cwprr_dffr (cwprr_w, cwprr, clk, rst_n); + +// ------------------------------------------------------ +// -- gapr0 register +// +// Write gapr0 for 'GAPR0' : 32-bit register +// Register is split into the following bit fields +// +// [31:16] --> gapr0 +// ------------------------------------------------------ +wire [31:0] gapr0_w; +assign gapr0_w[31:24] = wrmask[3] ? wrdata[31:24] : gapr0[15: 8];/////////////////////////////////////////////////////////////31:26->15:8 +assign gapr0_w[23:16] = wrmask[2] ? wrdata[23:16] : gapr0[ 7: 0];/////////////////////////////////////////////////////////////23:16->7:0 +sirv_gnrl_dfflr #(16) gapr0_dfflr (gapr0we, gapr0_w[31:16], gapr0, clk, rst_n); + +// ------------------------------------------------------ +// -- gapr1 register +// +// Write gapr1 for 'GAPR1' : 32-bit register +// Register is split into the following bit fields +// +// [31:16] --> gapr1 +// ------------------------------------------------------ +wire [31:0] gapr1_w; +assign gapr1_w[31:24] = wrmask[3] ? wrdata[31:24] : gapr1[15: 8];///////////////////////////////////////////////////////////// +assign gapr1_w[23:16] = wrmask[2] ? wrdata[23:16] : gapr1[ 7: 0];///////////////////////////////////////////////////////////// +sirv_gnrl_dfflr #(16) gapr1_dfflr (gapr1we, gapr1_w[31:16], gapr1, clk, rst_n); +// ------------------------------------------------------ +// -- gapr2 register +// +// Write gapr2 for 'GAPR2' : 32-bit register +// Register is split into the following bit fields +// +// [31:16] --> gapr2 +// ------------------------------------------------------ +wire [31:0] gapr2_w; +assign gapr2_w[31:24] = wrmask[3] ? wrdata[31:24] : gapr2[15: 8];///////////////////////////////////////////////////////////// +assign gapr2_w[23:16] = wrmask[2] ? wrdata[23:16] : gapr2[ 7: 0];///////////////////////////////////////////////////////////// +sirv_gnrl_dfflr #(16) gapr2_dfflr (gapr2we, gapr2_w[31:16], gapr2, clk, rst_n); +// ------------------------------------------------------ +// -- gapr3 register +// +// Write gapr3 for 'GAPR3' : 32-bit register +// Register is split into the following bit fields +// +// [31:16] --> gapr3 +// ------------------------------------------------------ +wire [31:0] gapr3_w; +assign gapr3_w[31:24] = wrmask[3] ? wrdata[31:24] : gapr3[15: 8];///////////////////////////////////////////////////////////// +assign gapr3_w[23:16] = wrmask[2] ? wrdata[23:16] : gapr3[ 7: 0];///////////////////////////////////////////////////////////// +sirv_gnrl_dfflr #(16) gapr3_dfflr (gapr3we, gapr3_w[31:16], gapr3, clk, rst_n); + +// ------------------------------------------------------ +// -- gapr4 register +// +// Write gapr4 for 'GAPR4' : 32-bit register +// Register is split into the following bit fields +// +// [31:16] --> gapr4 +// ------------------------------------------------------ +wire [31:0] gapr4_w; +assign gapr4_w[31:24] = wrmask[3] ? wrdata[31:24] : gapr4[15: 8];///////////////////////////////////////////////////////////// +assign gapr4_w[23:16] = wrmask[2] ? wrdata[23:16] : gapr4[ 7: 0];///////////////////////////////////////////////////////////// +sirv_gnrl_dfflr #(16) gapr4_dfflr (gapr4we, gapr4_w[31:16], gapr4, clk, rst_n); +// ------------------------------------------------------ +// -- gapr5 register +// +// Write gapr5 for 'GAPR5' : 32-bit register +// Register is split into the following bit fields +// +// [31:16] --> gapr5 +// ------------------------------------------------------ +wire [31:0] gapr5_w; +assign gapr5_w[31:24] = wrmask[3] ? wrdata[31:24] : gapr5[15: 8];///////////////////////////////////////////////////////////// +assign gapr5_w[23:16] = wrmask[2] ? wrdata[23:16] : gapr5[ 7: 0];///////////////////////////////////////////////////////////// +sirv_gnrl_dfflr #(16) gapr5_dfflr (gapr5we, gapr5_w[31:16], gapr5, clk, rst_n); +// ------------------------------------------------------ +// -- gapr6 register +// +// Write gapr6 for 'GAPR6' : 32-bit register +// Register is split into the following bit fields +// +// [31:16] --> gapr6 +// ------------------------------------------------------ +wire [31:0] gapr6_w; +assign gapr6_w[31:24] = wrmask[3] ? wrdata[31:24] : gapr6[15: 8];///////////////////////////////////////////////////////////// +assign gapr6_w[23:16] = wrmask[2] ? wrdata[23:16] : gapr6[ 7: 0];///////////////////////////////////////////////////////////// +sirv_gnrl_dfflr #(16) gapr6_dfflr (gapr6we, gapr6_w[31:16], gapr6, clk, rst_n); +// ------------------------------------------------------ +// -- gapr7 register +// +// Write gapr7 for 'GAPR7' : 32-bit register +// Register is split into the following bit fields +// +// [31:16] --> gapr7 +// ------------------------------------------------------ +wire [31:0] gapr7_w; +assign gapr7_w[31:24] = wrmask[3] ? wrdata[31:24] : gapr7[15: 8];///////////////////////////////////////////////////////////// +assign gapr7_w[23:16] = wrmask[2] ? wrdata[23:16] : gapr7[ 7: 0];///////////////////////////////////////////////////////////// +sirv_gnrl_dfflr #(16) gapr7_dfflr (gapr7we, gapr7_w[31:16], gapr7, clk, rst_n); + + +// ------------------------------------------------------ +// -- lcpr register +// +// Write lcpr for 'LCPR' : 32-bit register +// Register is split into the following bit fields +// +// [31:16] --> lcpr +// ------------------------------------------------------ +wire [31:0] lcpr_w; +assign lcpr_w[31:24] = wrmask[3] ? wrdata[31:24] : lcpr[15: 8];///////////////////////////////////////////////////////////// +assign lcpr_w[23:16] = wrmask[2] ? wrdata[23:16] : lcpr[ 7: 0];///////////////////////////////////////////////////////////// +sirv_gnrl_dfflr #(16) lcpr_dfflr (lcprwe, lcpr_w[31:16], lcpr, clk, rst_n); + +// ------------------------------------------------------ +// -- ampr0 register +// +// Write ampr0 for 'AMPR0' : 32-bit register +// Register is split into the following bit fields +// +// [31:16] --> ampr0 +// ------------------------------------------------------ +wire [31:0] ampr0_w; +assign ampr0_w[31:24] = wrmask[3] ? wrdata[31:24] : ampr0[15: 8];///////////////////////////////////////////////////////////// +assign ampr0_w[23:16] = wrmask[2] ? wrdata[23:16] : ampr0[ 7: 0];///////////////////////////////////////////////////////////// +sirv_gnrl_dfflr #(16) ampr0_dfflr (ampr0we, ampr0_w[31:16], ampr0, clk, rst_n); + +// ------------------------------------------------------ +// -- ampr1 register +// +// Write ampr1 for 'AMPR10' : 32-bit register +// Register is split into the following bit fields +// +// [31:16] --> ampr1 +// ------------------------------------------------------ +wire [31:0] ampr1_w; +assign ampr1_w[31:24] = wrmask[3] ? wrdata[31:24] : ampr1[15: 8];///////////////////////////////////////////////////////////// +assign ampr1_w[23:16] = wrmask[2] ? wrdata[23:16] : ampr1[ 7: 0];///////////////////////////////////////////////////////////// +sirv_gnrl_dfflr #(16) ampr1_dfflr (ampr1we, ampr1_w[31:16], ampr1, clk, rst_n); + +// ------------------------------------------------------ +// -- ampr2 register +// +// Write ampr2 for 'AMPR2' : 32-bit register +// Register is split into the following bit fields +// +// [31:16] --> ampr2 +// ------------------------------------------------------ +wire [31:0] ampr2_w; +assign ampr2_w[31:24] = wrmask[3] ? wrdata[31:24] : ampr2[15: 8];///////////////////////////////////////////////////////////// +assign ampr2_w[23:16] = wrmask[2] ? wrdata[23:16] : ampr2[ 7: 0];///////////////////////////////////////////////////////////// +sirv_gnrl_dfflr #(16) ampr2_dfflr (ampr2we, ampr2_w[31:16], ampr2, clk, rst_n); + +// ------------------------------------------------------ +// -- ampr3 register +// +// Write ampr3 for 'AMPR3' : 32-bit register +// Register is split into the following bit fields +// +// [31:16] --> ampr3 +// ------------------------------------------------------ +wire [31:0] ampr3_w; +assign ampr3_w[31:24] = wrmask[3] ? wrdata[31:24] : ampr3[15: 8];///////////////////////////////////////////////////////////// +assign ampr3_w[23:16] = wrmask[2] ? wrdata[23:16] : ampr3[ 7: 0];///////////////////////////////////////////////////////////// +sirv_gnrl_dfflr #(16) ampr3_dfflr (ampr3we, ampr3_w[31:16], ampr3, clk, rst_n); + + +// ------------------------------------------------------ +// -- baisr0 register +// +// Write baisr0 for 'BIASR0' : 32-bit register +// Register is split into the following bit fields +// +// [31:16] --> baisr0 +// ------------------------------------------------------ +wire [31:0] baisr0_w; +assign baisr0_w[31:24] = wrmask[3] ? wrdata[31:24] : baisr0[15: 8];///////////////////////////////////////////////////////////// +assign baisr0_w[23:16] = wrmask[2] ? wrdata[23:16] : baisr0[ 7: 0];///////////////////////////////////////////////////////////// +sirv_gnrl_dfflr #(16) baisr0_dfflr (baisr0we, baisr0_w[31:16], baisr0, clk, rst_n); +// ------------------------------------------------------ +// -- baisr1 register +// +// Write baisr1 for 'BIASR1' : 32-bit register +// Register is split into the following bit fields +// +// [31:16] --> baisr1 +// ------------------------------------------------------ +wire [31:0] baisr1_w; +assign baisr1_w[31:24] = wrmask[3] ? wrdata[31:24] : baisr1[15: 8];///////////////////////////////////////////////////////////// +assign baisr1_w[23:16] = wrmask[2] ? wrdata[23:16] : baisr1[ 7: 0];///////////////////////////////////////////////////////////// +sirv_gnrl_dfflr #(16) baisr1_dfflr (baisr1we, baisr1_w[31:16], baisr1, clk, rst_n); +// ------------------------------------------------------ +// -- baisr2 register +// +// Write baisr2 for 'BIASR2' : 32-bit register +// Register is split into the following bit fields +// +// [31:16] --> baisr2 +// ------------------------------------------------------ +wire [31:0] baisr2_w; +assign baisr2_w[31:24] = wrmask[3] ? wrdata[31:24] : baisr2[15: 8];///////////////////////////////////////////////////////////// +assign baisr2_w[23:16] = wrmask[2] ? wrdata[23:16] : baisr2[ 7: 0];///////////////////////////////////////////////////////////// +sirv_gnrl_dfflr #(16) baisr2_dfflr (baisr2we, baisr2_w[31:16], baisr2, clk, rst_n); +// ------------------------------------------------------ +// -- baisr3 register +// +// Write baisr3 for 'BIASR3' : 32-bit register +// Register is split into the following bit fields +// +// [31:16] --> baisr3 +// ------------------------------------------------------ +wire [31:0] baisr3_w; +assign baisr3_w[31:24] = wrmask[3] ? wrdata[31:24] : baisr3[15: 8];///////////////////////////////////////////////////////////// +assign baisr3_w[23:16] = wrmask[2] ? wrdata[23:16] : baisr3[ 7: 0];///////////////////////////////////////////////////////////// +sirv_gnrl_dfflr #(16) baisr3_dfflr (baisr3we, baisr3_w[31:16], baisr3, clk, rst_n); + +// ------------------------------------------------------ +// -- intpselr register +// +// Write intpselr for 'INTPSELR' : 32-bit register +// Register is split into the following bit fields +// +// [1:0] --> intpselr +// ------------------------------------------------------ +wire [1:0] intpselr_w; +assign intpselr_w[1:0] = wrmask[0] ? wrdata[1:0] : intpselr[1:0]; +sirv_gnrl_dfflr #(2) intpselr_dfflr (intpselrwe, intpselr_w[1:0], intpselr, clk, rst_n); + + +// ------------------------------------------------------ +// -- mcuparar0 +// ------------------------------------------------------ +sirv_gnrl_dffr #(32) mcuparar0_dffr (mcu_param[0], mcuparar0, clk, rst_n); +// ------------------------------------------------------ +// -- mcuparar1 +// ------------------------------------------------------ +sirv_gnrl_dffr #(32) mcuparar1_dffr (mcu_param[1], mcuparar1, clk, rst_n); +// ------------------------------------------------------ +// -- mcuparar2 +// ------------------------------------------------------ +sirv_gnrl_dffr #(32) mcuparar2_dffr (mcu_param[2], mcuparar2, clk, rst_n); +// ------------------------------------------------------ +// -- mcuparar3 +// ------------------------------------------------------ +sirv_gnrl_dffr #(32) mcuparar3_dffr (mcu_param[3], mcuparar3, clk, rst_n); + +// ------------------------------------------------------ +// -- rtimr +// ------------------------------------------------------ +sirv_gnrl_dffr #(32) rtimr_dffr (run_time, rtimr, clk, rst_n); + +// ------------------------------------------------------ +// -- icntr +// ------------------------------------------------------ +sirv_gnrl_dffr #(32) icntr_dffr (instr_num, icntr, clk, rst_n); + +// ------------------------------------------------------ +// -- fsir +// ------------------------------------------------------ +sirv_gnrl_dffr #(2) fsir_dffr (fb_st_info[1:0], fsir, clk, rst_n);////////////////////////////////////////////[1:0] + + + + + +// ------------------------------------------------------ +// -- Read data mux +// +// -- The data from the selected register is +// -- placed on a zero-padded 32-bit read data bus. +// ------------------------------------------------------ +always @(*) begin : RDDATA_PROC + rddata_reg = {32{1'b0}}; + if(mcuparar0en == H ) rddata_reg[31:0] = mcuparar0 ; + if(mcuparar1en == H ) rddata_reg[31:0] = mcuparar1 ; + if(mcuparar2en == H ) rddata_reg[31:0] = mcuparar2 ; + if(mcuparar3en == H ) rddata_reg[31:0] = mcuparar3 ; + if(mcuresr0en == H ) rddata_reg[31:0] = mcuresr0 ; + if(mcuresr1en == H ) rddata_reg[31:0] = mcuresr1 ; + if(mcuresr2en == H ) rddata_reg[31:0] = mcuresr2 ; + if(mcuresr3en == H ) rddata_reg[31:0] = mcuresr3 ; + if(cwfr0en == H ) rddata_reg[31:0] = cwfr0 ; + if(cwfr1en == H ) rddata_reg[31:0] = cwfr1 ; + if(cwfr2en == H ) rddata_reg[31:0] = cwfr2 ; + if(cwfr3en == H ) rddata_reg[31:0] = cwfr3 ; + if(cwprren == H ) rddata_reg[0 :0] = cwprr ; + if(gapr0en == H ) rddata_reg[15:0] = gapr0 ; + if(gapr1en == H ) rddata_reg[15:0] = gapr1 ; + if(gapr2en == H ) rddata_reg[15:0] = gapr2 ; + if(gapr3en == H ) rddata_reg[15:0] = gapr3 ; + if(gapr4en == H ) rddata_reg[15:0] = gapr4 ; + if(gapr5en == H ) rddata_reg[15:0] = gapr5 ; + if(gapr6en == H ) rddata_reg[15:0] = gapr6 ; + if(gapr7en == H ) rddata_reg[15:0] = gapr7 ; + if(lcpren == H ) rddata_reg[15:0] = lcpr ; + if(ampr0en == H ) rddata_reg[15:0] = ampr0 ; + if(ampr1en == H ) rddata_reg[15:0] = ampr1 ; + if(ampr2en == H ) rddata_reg[15:0] = ampr2 ; + if(ampr3en == H ) rddata_reg[15:0] = ampr3 ; + if(baisr0en == H ) rddata_reg[15:0] = baisr0 ; + if(baisr1en == H ) rddata_reg[15:0] = baisr1 ; + if(baisr2en == H ) rddata_reg[15:0] = baisr2 ; + if(baisr3en == H ) rddata_reg[15:0] = baisr3 ; + if(rtimren == H ) rddata_reg[31:0] = rtimr ; + if(icntren == H ) rddata_reg[31:0] = icntr ; + if(fsiren == H ) rddata_reg[1 :0] = fsir ; + if(intpselren == H ) rddata_reg[1 :0] = intpselr ;//////////////////////////////////////////////////////////// +end + +// ------------------------------------------------------ +// -- Output signals assignment +// ------------------------------------------------------ +//mcu result +assign mcu_result[0] = mcuresr0 ; +assign mcu_result[1] = mcuresr1 ; +assign mcu_result[2] = mcuresr2 ; +assign mcu_result[3] = mcuresr3 ; + +//nco_fwc lookup table output +assign mcu_cwfr[0] = cwfr0; +assign mcu_cwfr[1] = cwfr1; +assign mcu_cwfr[2] = cwfr2; +assign mcu_cwfr[3] = cwfr3; + +//nco_pha lookup table output +assign mcu_gapr[0] = gapr0; ////////////////////////////////////////////////16bit assign to 32bit(?) +assign mcu_gapr[1] = gapr1; +assign mcu_gapr[2] = gapr2; +assign mcu_gapr[3] = gapr3; +assign mcu_gapr[4] = gapr4; +assign mcu_gapr[5] = gapr5; +assign mcu_gapr[6] = gapr6; +assign mcu_gapr[7] = gapr7; + +//amp lookup table output +assign mcu_ampr[0] = ampr0; +assign mcu_ampr[1] = ampr1; +assign mcu_ampr[2] = ampr2; +assign mcu_ampr[3] = ampr3; + +//bais lookup table output +assign mcu_baisr[0] = baisr0; +assign mcu_baisr[1] = baisr1; +assign mcu_baisr[2] = baisr2; +assign mcu_baisr[3] = baisr3; + +//CFG Port +assign mcu_nco_pha_clr = cwprr; +assign mcu_rz_pha = lcpr; +assign mcu_intp_sel = intpselr; +//rddata +//assign rddata = rddata_reg ; +sirv_gnrl_dffr #(32) rddata_dffr (rddata_reg, rddata, clk, rst_n);//////////////////////// +endmodule + +`undef MCUPARAR0 +`undef MCUPARAR1 +`undef MCUPARAR2 +`undef MCUPARAR3 +`undef MCURESR0 +`undef MCURESR1 +`undef MCURESR2 +`undef MCURESR3 +`undef CWFR0 +`undef CWFR1 +`undef CWFR2 +`undef CWFR3 +`undef CWPRR +`undef GAPR0 +`undef GAPR1 +`undef GAPR2 +`undef GAPR3 +`undef GAPR4 +`undef GAPR5 +`undef GAPR6 +`undef GAPR7 +`undef LCPR +`undef AMPR0 +`undef AMPR1 +`undef AMPR2 +`undef AMPR3 +`undef BIASR0 +`undef BIASR1 +`undef BIASR2 +`undef BIASR3 +`undef RTIMR +`undef ICNTR +`undef FSIR diff --git a/rtl/qubitmcu/qbmcu.v b/rtl/qubitmcu/qbmcu.v new file mode 100644 index 0000000..5526697 --- /dev/null +++ b/rtl/qubitmcu/qbmcu.v @@ -0,0 +1,271 @@ +//+FHDR-------------------------------------------------------------------------------------------------------- +// Company: +//----------------------------------------------------------------------------------------------------------------- +// File Name : qbmcu.v +// Department : +// Author : PWY +// Author's Tel : +//----------------------------------------------------------------------------------------------------------------- +// Relese History +// Version Date Author Description +// 0.1 2024-03-13 PWY Quantum Bit Measurement and Control Microprocessor +//----------------------------------------------------------------------------------------------------------------- +// Keywords : +// +//----------------------------------------------------------------------------------------------------------------- +// Parameter +// +//----------------------------------------------------------------------------------------------------------------- +// Purpose : +// +//----------------------------------------------------------------------------------------------------------------- +// Target Device: +// Tool versions: +//----------------------------------------------------------------------------------------------------------------- +// Reuse Issues +// Reset Strategy: +// Clock Domains: +// Critical Timing: +// Asynchronous I/F: +// Synthesizable (y/n): +// Other: +//-FHDR-------------------------------------------------------------------------------------------------------- + + +`include "qbmcu_defines.v" + +module qbmcu( + //system port + input clk + ,input rst_n + //Sync Start + ,input qbmcu_i_start + ,output [2 :0] qbmcu_o_fsm_st + //IFU port + ,input [`QBMCU_PC_SIZE-1 :0] ifu_i_pc_rtvec // Initial PC + ,output [`QBMCU_PC_SIZE-1 :0] ifu_o_req_pc // Fetch PC + ,output ifu_o_req // Fetch req + ,input [`QBMCU_INSTR_SIZE-1 :0] ifu_rsp_instr + //Decoded port + ,output dec_o_ilegl + //LDST port + //Address, data, and enable signals connected to the memory space + ,output [`QBMCU_ADDR_SIZE-1 :0] agu_o_addr + ,output [`QBMCU_XLEN-1 :0] agu_o_wrdata + ,output agu_o_wren // Write enable + ,output [`QBMCU_XLEN/8-1 :0] agu_o_wrmask + ,output agu_o_rden // Read enable + ,input [`QBMCU_XLEN-1 :0] agu_i_rddata + //Misaligned memory address + ,output agu_o_addr_unalgn + //Extend instructions port + // The operands and info to peripheral + ,output ext_o_send + ,output ext_o_sendc + ,output [`QBMCU_XLEN-1 :0] ext_o_codeword + ,output ext_o_intr + ); + +//////////////////////////////////////////////////////////////////////////////////////////////////////////// +//qbmcu_fsm +//////////////////////////////////////////////////////////////////////////////////////////////////////////// + +wire ifupc_rst ; +wire ifu_active ; +wire wb_active ; +wire dec_active ; +wire exu_active ; +wire ext_wait ; +wire ext_o_exit ; +wire qbmcu_i_timer_done ; + +qbmcu_fsm U_qbmcu_fsm ( + .clk ( clk ) + ,.rst_n ( rst_n ) + ,.start ( qbmcu_i_start ) + ,.exit ( ext_o_exit ) + ,.ext_wait ( ext_wait ) + ,.qbmcu_timer_done ( qbmcu_i_timer_done ) + ,.agu_addr_unalgn ( agu_o_addr_unalgn ) + ,.dec_ilegl ( dec_o_ilegl ) + ,.ifupc_rst ( ifupc_rst ) + ,.wb_active ( wb_active ) + ,.ifu_active ( ifu_active ) + ,.dec_active ( dec_active ) + ,.exu_active ( exu_active ) + ,.qbmcu_fsm_st ( qbmcu_o_fsm_st ) +); + + +//////////////////////////////////////////////////////////////////////////////////////////////////////////// +//qbmcu_ifu_ifetch +//////////////////////////////////////////////////////////////////////////////////////////////////////////// +wire [`QBMCU_INSTR_SIZE-1:0] ifu_ir ; +wire [`QBMCU_PC_SIZE-1 :0] ifu_pc ; +wire update_pc_req ; +wire [`QBMCU_PC_SIZE-1 :0] update_pc_value ; + +qbmcu_ifu U_qbmcu_ifu ( + .clk ( clk ) + ,.rst_n ( rst_n ) + ,.ifu_active ( ifu_active ) + ,.exu_active ( exu_active ) + ,.pc_rtvec ( ifu_i_pc_rtvec ) + ,.ifu_req_pc ( ifu_o_req_pc ) + ,.ifu_req ( ifu_o_req ) + ,.ifu_rsp_instr ( ifu_rsp_instr ) + ,.ifu_o_ir ( ifu_ir ) + ,.ifu_o_pc ( ifu_pc ) + ,.ifupc_rst ( ifupc_rst ) + ,.update_pc_req ( update_pc_req ) + ,.update_pc_value ( update_pc_value ) + ); + +//////////////////////////////////////////////////////////////////////////////////////////////////////////// +//qbmcu_decode +//////////////////////////////////////////////////////////////////////////////////////////////////////////// +//wire dec_rs1en ; +//wire dec_rs2en ; +wire dec_rdwen ; +wire [`QBMCU_RFIDX_WIDTH-1 :0] dec_rs1idx ; +wire [`QBMCU_RFIDX_WIDTH-1 :0] dec_rs2idx ; +wire [`QBMCU_RFIDX_WIDTH-1 :0] dec_rdidx ; +wire [`QBMCU_DECINFO_WIDTH-1:0] dec_info ; +wire [`QBMCU_XLEN-1 :0] dec_imm ; +wire [`QBMCU_PC_SIZE-1 :0] dec_pc ; + +qbmcu_decode qbmcu_decode ( + .clk ( clk ) + ,.rst_n ( rst_n ) + ,.dec_i_active ( dec_active ) + ,.dec_i_instr ( ifu_ir ) + ,.dec_i_pc ( ifu_pc ) + //,.dec_o_rs1en ( dec_rs1en ) + //,.dec_o_rs2en ( dec_rs2en ) + ,.dec_o_rdwen ( dec_rdwen ) + ,.dec_o_rs1idx ( dec_rs1idx ) + ,.dec_o_rs2idx ( dec_rs2idx ) + ,.dec_o_rdidx ( dec_rdidx ) + ,.dec_o_info ( dec_info ) + ,.dec_o_imm ( dec_imm ) + ,.dec_o_pc ( dec_pc ) + ,.dec_o_ilegl ( dec_o_ilegl ) + ); + +//////////////////////////////////////////////////////////////////////////////////////////////////////////// +//qbmcu_exu +//////////////////////////////////////////////////////////////////////////////////////////////////////////// +wire [`QBMCU_XLEN-1 :0] exu_rs1 ; +wire [`QBMCU_XLEN-1 :0] exu_rs2 ; +wire [`QBMCU_XLEN-1 :0] bjp_wbck_wdat ; +wire bjp_wbck_valid ; +wire [`QBMCU_XLEN-1 :0] agu_wbck_wdat ; +wire agu_wbck_valid ; +wire [`QBMCU_XLEN-1 :0] alu_wbck_wdat ; +wire alu_wbck_valid ; +wire [`QBMCU_XLEN-1 :0] ext_wbck_wdat ; +wire ext_wbck_valid ; +wire [`QBMCU_XLEN-1 :0] ext_wait_cnt ; + +////////////////////////////////////////////////////////////// +//Address, data, and enable signals connected to the memory space +wire ext_o_wait_valid ; + +qbmcu_exu U_qbmcu_exu ( + .clk ( clk ) + ,.rst_n ( rst_n ) + ,.exu_i_rs1 ( exu_rs1 ) + ,.exu_i_rs2 ( exu_rs2 ) + ,.exu_i_imm ( dec_imm ) + ,.exu_i_pc ( dec_pc ) + ,.exu_i_info ( dec_info ) + ,.exu_i_ilegl ( dec_o_ilegl ) + ,.exu_i_active ( exu_active ) + ,.bjp_o_wbck_wdat ( bjp_wbck_wdat ) + ,.bjp_o_wbck_valid ( bjp_wbck_valid ) + ,.bjp_update_pc_req ( update_pc_req ) + ,.bjp_update_pc_value ( update_pc_value ) + ,.ext_o_wait_valid ( ext_o_wait_valid ) + ,.ext_o_wait ( ext_wait ) + ,.ext_o_wait_cnt ( ext_wait_cnt ) + ,.ext_o_send ( ext_o_send ) + ,.ext_o_sendc ( ext_o_sendc ) + ,.ext_o_codeword ( ext_o_codeword ) + ,.ext_o_exit ( ext_o_exit ) + ,.ext_o_intr ( ext_o_intr ) + ,.ext_o_wbck_wdat ( ext_wbck_wdat ) + ,.ext_o_wbck_valid ( ext_wbck_valid ) + ,.agu_o_addr ( agu_o_addr ) + ,.agu_o_wdata ( agu_o_wrdata ) + ,.agu_o_wren ( agu_o_wren ) + ,.agu_o_rden ( agu_o_rden ) + ,.agu_o_wmask ( agu_o_wrmask ) + ,.agu_i_rdata ( agu_i_rddata ) + ,.agu_o_addr_unalgn ( agu_o_addr_unalgn ) + ,.agu_o_wbck_wdat ( agu_wbck_wdat ) + ,.agu_o_wbck_valid ( agu_wbck_valid ) + ,.alu_o_wbck_wdat ( alu_wbck_wdat ) + ,.alu_o_wbck_valid ( alu_wbck_valid ) + ); +//////////////////////////////////////////////////////////////////////////////////////////////////////////// +//qbmcu_wbck +//////////////////////////////////////////////////////////////////////////////////////////////////////////// +wire wbck_ena ; +wire [`QBMCU_XLEN-1 :0] wbck_wdat ; +wire [`QBMCU_RFIDX_WIDTH-1 :0] wbck_rdidx ; + +qbmcu_wbck U_qbmcu_wbck ( + .clk ( clk ) + ,.rst_n ( rst_n ) + ,.wbck_i_active ( wb_active ) + ,.wbck_i_rdidx ( dec_rdidx ) + ,.wbck_i_rdwen ( dec_rdwen ) + ,.bjp_i_wbck_wdat ( bjp_wbck_wdat ) + ,.bjp_i_wbck_valid ( bjp_wbck_valid ) + ,.agu_i_wbck_wdat ( agu_wbck_wdat ) + ,.agu_i_wbck_valid ( agu_wbck_valid ) + ,.alu_i_wbck_wdat ( alu_wbck_wdat ) + ,.alu_i_wbck_valid ( alu_wbck_valid ) + ,.ext_i_wbck_wdat ( ext_wbck_wdat ) + ,.ext_i_wbck_valid ( ext_wbck_valid ) + ,.wbck_o_ena ( wbck_ena ) + ,.wbck_o_rdidx ( wbck_rdidx ) + ,.wbck_o_wdat ( wbck_wdat ) + ); + +//////////////////////////////////////////////////////////////////////////////////////////////////////////// +//qbmcu_regfile +//////////////////////////////////////////////////////////////////////////////////////////////////////////// + +qbmcu_regfile U_qbmcu_regfile ( + .clk ( clk ) + ,.rst_n ( rst_n ) + ,.read_src1_idx ( dec_rs1idx ) + ,.read_src2_idx ( dec_rs2idx ) + ,.read_src1_dat ( exu_rs1 ) + ,.read_src2_dat ( exu_rs2 ) + ,.wbck_dest_wen ( wbck_ena ) + ,.wbck_dest_idx ( wbck_rdidx ) + ,.wbck_dest_dat ( wbck_wdat ) + ); + + +//////////////////////////////////////////////////////////////////////////////////////////////////////////// +//DW03_updn_ctr +//////////////////////////////////////////////////////////////////////////////////////////////////////////// +defparam U_DW03_updn_ctr.width = 32; +DW03_updn_ctr U_DW03_updn_ctr ( + .clk ( clk )// clock input + ,.reset ( rst_n )// asynchronous reset input (active low) + ,.data ( ext_wait_cnt-1'b1 )// data used for load operation + ,.up_dn ( 1'b0 )// up/down control input (0=down, 1-up) + ,.load ( !ext_wait )// load operation control input (active low) + ,.cen ( ext_o_wait_valid )// count enable control input (active high enable) + ,.count ( )// count value output + ,.tercnt ( qbmcu_i_timer_done ) // terminal count output flag (active high) + ); + + +endmodule + +`include "qbmcu_undefines.v" \ No newline at end of file diff --git a/rtl/qubitmcu/qbmcu_busdecoder.v b/rtl/qubitmcu/qbmcu_busdecoder.v new file mode 100644 index 0000000..4309fce --- /dev/null +++ b/rtl/qubitmcu/qbmcu_busdecoder.v @@ -0,0 +1,113 @@ +//+FHDR-------------------------------------------------------------------------------------------------------- +// Company: +//----------------------------------------------------------------------------------------------------------------- +// File Name : qbmcu_busdecoder.v +// Department : +// Author : PWY +// Author's Tel : +//----------------------------------------------------------------------------------------------------------------- +// Relese History +// Version Date Author Description +// 1.0 2022-08-25 PWY +//----------------------------------------------------------------------------------------------------------------- +// Keywords : +// +//----------------------------------------------------------------------------------------------------------------- +// Parameter +// +//----------------------------------------------------------------------------------------------------------------- +// Purpose : +// +//----------------------------------------------------------------------------------------------------------------- +// Target Device: +// Tool versions: +//----------------------------------------------------------------------------------------------------------------- +// Reuse Issues +// Reset Strategy: +// Clock Domains: +// Critical Timing: +// Asynchronous I/F: +// Synthesizable (y/n): +// Other: +//-FHDR-------------------------------------------------------------------------------------------------------- + +`include "qbmcu_defines.v" + +module qbmcu_busdecoder #( + parameter S0_BASEADDR = 32'h0010_0000 + ,parameter S1_BASEADDR = 32'h0020_0000 +)( + //rw op port + input wren // write enable + ,input [`QBMCU_XLEN/8-1 :0] wrmask // write mask + ,input [`QBMCU_XLEN-1 :0] wrdata // write data + ,input [`QBMCU_ADDR_SIZE-1:0] rwaddr // read & write addr + ,input rden // read enable + ,output [`QBMCU_XLEN-1 :0] rddata // read data + //data sram read and write signals + ,output s0_wren // s0 write enable + ,output [`QBMCU_XLEN/8-1 :0] s0_wrmask // write mask + ,output [`QBMCU_ADDR_SIZE-1:0] s0_rwaddr // s0 read & write addr + ,output [`QBMCU_XLEN-1 :0] s0_wrdata // s0 write data + ,output s0_rden // s0 read enable + ,input [`QBMCU_XLEN-1 :0] s0_rddata // s0 read data + //mcu perips reg read and write signals + ,output s1_wren // s1 write enable + ,output [`QBMCU_XLEN/8-1 :0] s1_wrmask // write mask + ,output [`QBMCU_ADDR_SIZE-1:0] s1_rwaddr // s1 read & write addr + ,output [`QBMCU_XLEN-1 :0] s1_wrdata // s1 write data + ,output s1_rden // s1 read enable + ,input [`QBMCU_XLEN-1 :0] s1_rddata // s1 read data +); + +wire s0_sel; +wire s1_sel; + +//s0_sel +assign s0_sel = (rwaddr[`QBMCU_ADDR_SIZE-1:16] == S0_BASEADDR >> 16); +//s1_sel +assign s1_sel = (rwaddr[`QBMCU_ADDR_SIZE-1:16] == S1_BASEADDR >> 16); + + +//s0_wren +assign s0_wren = s0_sel & wren; +//s1_wren +assign s1_wren = s1_sel & wren; + +//s0_wrmask +assign s0_wrmask = {`QBMCU_XLEN/8{s0_sel}} & wrmask; +//s1_wrmask +assign s1_wrmask = {`QBMCU_XLEN/8{s1_sel}} & wrmask; + +//s0_rden +assign s0_rden = s0_sel & rden; +//s1_rden +assign s1_rden = s1_sel & rden; + + +//s0_rwaddr +assign s0_rwaddr = {`QBMCU_ADDR_SIZE{s0_sel}} & rwaddr; +//s1_rwaddr +assign s1_rwaddr = {`QBMCU_ADDR_SIZE{s1_sel}} & rwaddr; + +//s0_wrdata +assign s0_wrdata = {`QBMCU_XLEN{s0_sel}} & wrdata; +//s1_wrdata +assign s1_wrdata = {`QBMCU_XLEN{s1_sel}} & wrdata; + +// ------------------------------------------------------ +// -- Read data mux +// +// -- The data from the selected register is +// -- placed on a zero-padded 32-bit read data bus. +// ------------------------------------------------------ + +wire [`QBMCU_XLEN-1:0] rddata_w = {`QBMCU_XLEN{s0_sel}} & s0_rddata + | {`QBMCU_XLEN{s1_sel}} & s1_rddata; + +//rddata +assign rddata = rddata_w; + +endmodule + +`include "qbmcu_undefines.v" \ No newline at end of file diff --git a/rtl/qubitmcu/qbmcu_datalock.v b/rtl/qubitmcu/qbmcu_datalock.v new file mode 100644 index 0000000..cf815f6 --- /dev/null +++ b/rtl/qubitmcu/qbmcu_datalock.v @@ -0,0 +1,69 @@ +//+FHDR-------------------------------------------------------------------------------------------------------- +// Company: +//----------------------------------------------------------------------------------------------------------------- +// File Name : qbmcu_datalatch.v +// Department : +// Author : PWY +// Author's Tel : +//----------------------------------------------------------------------------------------------------------------- +// Relese History +// Version Date Author Description +// 0.1 2024-03-13 PWY The operation of latch and hold, eliminating invalid toggling to +// reduce dynamic power consumption. +//----------------------------------------------------------------------------------------------------------------- +// Keywords : +// +//----------------------------------------------------------------------------------------------------------------- +// Parameter +// +//----------------------------------------------------------------------------------------------------------------- +// Purpose : +// +//----------------------------------------------------------------------------------------------------------------- +// Target Device: +// Tool versions: +//----------------------------------------------------------------------------------------------------------------- +// Reuse Issues +// Reset Strategy: +// Clock Domains: +// Critical Timing: +// Asynchronous I/F: +// Synthesizable (y/n): +// Other: +//-FHDR-------------------------------------------------------------------------------------------------------- + + +`include "qbmcu_defines.v" + +module qbmcu_datalatch #( + parameter DECINFO_GRP_OP = `QBMCU_DECINFO_GRP_AGU ) + ( + input [`QBMCU_XLEN-1 :0] i_rs1 + ,input [`QBMCU_XLEN-1 :0] i_rs2 + ,input [`QBMCU_XLEN-1 :0] i_imm + ,input [`QBMCU_DECINFO_WIDTH-1 :0] i_info + ,input [`QBMCU_PC_SIZE-1 :0] i_pc + ,input i_ilegl + + ,output [`QBMCU_XLEN-1 :0] o_rs1 + ,output [`QBMCU_XLEN-1 :0] o_rs2 + ,output [`QBMCU_XLEN-1 :0] o_imm + ,output [`QBMCU_DECINFO_WIDTH-1 :0] o_info + ,output [`QBMCU_PC_SIZE-1 :0] o_pc + ,output o_op + ); + + +wire op = (~i_ilegl) & (i_info[`QBMCU_DECINFO_GRP] == DECINFO_GRP_OP); + + +assign o_rs1 = {`QBMCU_XLEN {op}} & i_rs1 ; +assign o_rs2 = {`QBMCU_XLEN {op}} & i_rs2 ; +assign o_imm = {`QBMCU_XLEN {op}} & i_imm ; +assign o_info = {`QBMCU_DECINFO_WIDTH{op}} & i_info ; +assign o_pc = {`QBMCU_PC_SIZE {op}} & i_pc ; + +assign o_op = op; + +endmodule +`include "qbmcu_undefines.v" \ No newline at end of file diff --git a/rtl/qubitmcu/qbmcu_decode.v b/rtl/qubitmcu/qbmcu_decode.v new file mode 100644 index 0000000..7a1c48c --- /dev/null +++ b/rtl/qubitmcu/qbmcu_decode.v @@ -0,0 +1,480 @@ +//+FHDR-------------------------------------------------------------------------------------------------------- +// Company: +//----------------------------------------------------------------------------------------------------------------- +// File Name : qbmcu_decode.v +// Department : +// Author : PWY +// Author's Tel : +//----------------------------------------------------------------------------------------------------------------- +// Relese History +// Version Date Author Description +// 0.1 2024-03-13 PWY The decode module to decode the instruction details +//----------------------------------------------------------------------------------------------------------------- +// Keywords : +// +//----------------------------------------------------------------------------------------------------------------- +// Parameter +// +//----------------------------------------------------------------------------------------------------------------- +// Purpose : +// +//----------------------------------------------------------------------------------------------------------------- +// Target Device: +// Tool versions: +//----------------------------------------------------------------------------------------------------------------- +// Reuse Issues +// Reset Strategy: +// Clock Domains: +// Critical Timing: +// Asynchronous I/F: +// Synthesizable (y/n): +// Other: +//-FHDR-------------------------------------------------------------------------------------------------------- + + +`include "qbmcu_defines.v" + +module qbmcu_decode( + input clk // System Clock + ,input rst_n // System reset,active low + ,input dec_i_active // DEC module Active from MCU FSM + ////////////////////////////////////////////////////////////// + // The IR stage to Decoder + ,input [`QBMCU_INSTR_SIZE-1 :0] dec_i_instr + ,input [`QBMCU_PC_SIZE-1 :0] dec_i_pc + + ////////////////////////////////////////////////////////////// + // The Decoded Info-Bus + //,output dec_o_rs1en + //,output dec_o_rs2en + ,output dec_o_rdwen + ,output [`QBMCU_RFIDX_WIDTH-1 :0] dec_o_rs1idx + ,output [`QBMCU_RFIDX_WIDTH-1 :0] dec_o_rs2idx + ,output [`QBMCU_RFIDX_WIDTH-1 :0] dec_o_rdidx + ,output [`QBMCU_DECINFO_WIDTH-1:0] dec_o_info + ,output [`QBMCU_XLEN-1 :0] dec_o_imm + ,output [`QBMCU_PC_SIZE-1 :0] dec_o_pc + ,output dec_o_ilegl + ); + +wire dec_i_active_r; +wire [`QBMCU_DECINFO_WIDTH-1:0] dec_info_w; + +//dec_i_active_r +//sirv_gnrl_dffr #(1) dec_i_active_r_dffr (dec_i_active, dec_i_active_r, clk, rst_n); +assign dec_i_active_r = dec_i_active; + +/////////////////////////////////////////////////////////////// +//Instruction decoding +/////////////////////////////////////////////////////////////// +wire [32-1:0] rv32_instr = dec_i_instr; + +wire [6:0] opcode = rv32_instr[6:0]; + +//wire opcode_1_0_00 = (opcode[1:0] == 2'b00); +//wire opcode_1_0_01 = (opcode[1:0] == 2'b01); +//wire opcode_1_0_10 = (opcode[1:0] == 2'b10); +wire opcode_1_0_11 = (opcode[1:0] == 2'b11); + +wire rv32 = (~(dec_i_instr[4:2] == 3'b111)) & opcode_1_0_11; + +wire [4:0] rv32_rd = rv32_instr[11:7]; +wire [2:0] rv32_func3 = rv32_instr[14:12]; +wire [4:0] rv32_rs1 = rv32_instr[19:15]; +wire [4:0] rv32_rs2 = rv32_instr[24:20]; +wire [6:0] rv32_func7 = rv32_instr[31:25]; + +// We generate the signals and reused them as much as possible to save gatecounts +wire opcode_4_2_000 = (opcode[4:2] == 3'b000); +wire opcode_4_2_001 = (opcode[4:2] == 3'b001); +wire opcode_4_2_010 = (opcode[4:2] == 3'b010); +wire opcode_4_2_011 = (opcode[4:2] == 3'b011); +wire opcode_4_2_100 = (opcode[4:2] == 3'b100); +wire opcode_4_2_101 = (opcode[4:2] == 3'b101); +//wire opcode_4_2_110 = (opcode[4:2] == 3'b110); +wire opcode_4_2_111 = (opcode[4:2] == 3'b111); +wire opcode_6_5_00 = (opcode[6:5] == 2'b00); +wire opcode_6_5_01 = (opcode[6:5] == 2'b01); +//wire opcode_6_5_10 = (opcode[6:5] == 2'b10); +wire opcode_6_5_11 = (opcode[6:5] == 2'b11); + +wire rv32_func3_000 = (rv32_func3 == 3'b000); +wire rv32_func3_001 = (rv32_func3 == 3'b001); +wire rv32_func3_010 = (rv32_func3 == 3'b010); +wire rv32_func3_011 = (rv32_func3 == 3'b011); +wire rv32_func3_100 = (rv32_func3 == 3'b100); +wire rv32_func3_101 = (rv32_func3 == 3'b101); +wire rv32_func3_110 = (rv32_func3 == 3'b110); +wire rv32_func3_111 = (rv32_func3 == 3'b111); + +wire rv32_func7_0000000 = (rv32_func7 == 7'b0000000); +wire rv32_func7_0100000 = (rv32_func7 == 7'b0100000); +wire rv32_func7_1111111 = (rv32_func7 == 7'b1111111); + + +wire rv32_rs1_x0 = (rv32_rs1 == 5'b00000); +wire rv32_rs2_x0 = (rv32_rs2 == 5'b00000); +//wire rv32_rs2_x1 = (rv32_rs2 == 5'b00001); +wire rv32_rd_x0 = (rv32_rd == 5'b00000); +//wire rv32_rd_x2 = (rv32_rd == 5'b00010); + +wire rv32_rs1_x31 = (rv32_rs1 == 5'b11111); +wire rv32_rs2_x31 = (rv32_rs2 == 5'b11111); +wire rv32_rd_x31 = (rv32_rd == 5'b11111); + +wire rv32_load = opcode_6_5_00 & opcode_4_2_000 & opcode_1_0_11; //LB +wire rv32_store = opcode_6_5_01 & opcode_4_2_000 & opcode_1_0_11; //SB + +wire rv32_branch = opcode_6_5_11 & opcode_4_2_000 & opcode_1_0_11; //B + +wire rv32_jalr = opcode_6_5_11 & opcode_4_2_001 & opcode_1_0_11; //JALR + +wire rv32_custom0 = opcode_6_5_00 & opcode_4_2_010 & opcode_1_0_11; //WAIT SENDC SEND +wire rv32_custom1 = opcode_6_5_01 & opcode_4_2_010 & opcode_1_0_11; //EXIT EXIT_IRQ + +wire rv32_jal = opcode_6_5_11 & opcode_4_2_011 & opcode_1_0_11; //JAL + +wire rv32_op_imm = opcode_6_5_00 & opcode_4_2_100 & opcode_1_0_11; //ADDI +wire rv32_op = opcode_6_5_01 & opcode_4_2_100 & opcode_1_0_11; //ADD + +wire rv32_auipc = opcode_6_5_00 & opcode_4_2_101 & opcode_1_0_11; //AUIPC +wire rv32_lui = opcode_6_5_01 & opcode_4_2_101 & opcode_1_0_11; //LUI + + +// =========================================================================== +// Branch Instructions +wire rv32_beq = rv32_branch & rv32_func3_000; //B beq +wire rv32_bne = rv32_branch & rv32_func3_001; //B bne +wire rv32_blt = rv32_branch & rv32_func3_100; //B blt +wire rv32_bgt = rv32_branch & rv32_func3_101; //B bge +wire rv32_bltu = rv32_branch & rv32_func3_110; //B bltu +wire rv32_bgtu = rv32_branch & rv32_func3_111; //B bgeu + + +// =========================================================================== + // The Branch and system group of instructions will be handled by BJP + +wire dec_jal = rv32_jal ; +wire dec_jalr = rv32_jalr; +wire dec_bxx = rv32_branch; +wire dec_bjp = dec_jal | dec_jalr | dec_bxx; + +wire bjp_op = dec_bjp ; + +wire [`QBMCU_DECINFO_BJP_WIDTH-1:0] bjp_info_bus; +assign bjp_info_bus[`QBMCU_DECINFO_GRP ] = `QBMCU_DECINFO_GRP_BJP; +assign bjp_info_bus[`QBMCU_DECINFO_RV32 ] = rv32; +assign bjp_info_bus[`QBMCU_DECINFO_BJP_JUMP ] = dec_jal | dec_jalr; +assign bjp_info_bus[`QBMCU_DECINFO_BJP_JALR ] = dec_jalr; +assign bjp_info_bus[`QBMCU_DECINFO_BJP_BEQ ] = rv32_beq ; +assign bjp_info_bus[`QBMCU_DECINFO_BJP_BNE ] = rv32_bne ; +assign bjp_info_bus[`QBMCU_DECINFO_BJP_BLT ] = rv32_blt; +assign bjp_info_bus[`QBMCU_DECINFO_BJP_BGT ] = rv32_bgt ; +assign bjp_info_bus[`QBMCU_DECINFO_BJP_BLTU ] = rv32_bltu; +assign bjp_info_bus[`QBMCU_DECINFO_BJP_BGTU ] = rv32_bgtu; +assign bjp_info_bus[`QBMCU_DECINFO_BJP_BXX ] = dec_bxx; + + +// =========================================================================== +// ALU Instructions +wire rv32_addi = rv32_op_imm & rv32_func3_000; // I addi +wire rv32_slti = rv32_op_imm & rv32_func3_010; // I slti +wire rv32_sltiu = rv32_op_imm & rv32_func3_011; // I sltiu +wire rv32_xori = rv32_op_imm & rv32_func3_100; // I xori +wire rv32_ori = rv32_op_imm & rv32_func3_110; // I ori +wire rv32_andi = rv32_op_imm & rv32_func3_111; // I andi + +wire rv32_slli = rv32_op_imm & rv32_func3_001 & (rv32_instr[31:26] == 6'b000000); // I slli +wire rv32_srli = rv32_op_imm & rv32_func3_101 & (rv32_instr[31:26] == 6'b000000); // I srli +wire rv32_srai = rv32_op_imm & rv32_func3_101 & (rv32_instr[31:26] == 6'b010000); // I srai + +wire rv32_sxxi_shamt_legl = (rv32_instr[25] == 1'b0); //shamt[5] must be zero for RV32I +wire rv32_sxxi_shamt_ilgl = (rv32_slli | rv32_srli | rv32_srai) & (~rv32_sxxi_shamt_legl); + +wire rv32_add = rv32_op & rv32_func3_000 & rv32_func7_0000000; // R add +wire rv32_sub = rv32_op & rv32_func3_000 & rv32_func7_0100000; // R sub +wire rv32_sll = rv32_op & rv32_func3_001 & rv32_func7_0000000; // R sll +wire rv32_slt = rv32_op & rv32_func3_010 & rv32_func7_0000000; // R slt +wire rv32_sltu = rv32_op & rv32_func3_011 & rv32_func7_0000000; // R sltu +wire rv32_xor = rv32_op & rv32_func3_100 & rv32_func7_0000000; // R xor +wire rv32_srl = rv32_op & rv32_func3_101 & rv32_func7_0000000; // R srl +wire rv32_sra = rv32_op & rv32_func3_101 & rv32_func7_0100000; // R sra +wire rv32_or = rv32_op & rv32_func3_110 & rv32_func7_0000000; // R or +wire rv32_and = rv32_op & rv32_func3_111 & rv32_func7_0000000; // R and + +wire rv32_nop = rv32_addi & rv32_rs1_x0 & rv32_rd_x0 & (~(|rv32_instr[31:20])); + +wire alu_op = (~rv32_sxxi_shamt_ilgl) & + ( rv32_op_imm + | rv32_op + | rv32_auipc + | rv32_lui + | rv32_nop) + ; +wire need_imm; +wire [`QBMCU_DECINFO_ALU_WIDTH-1:0] alu_info_bus; +assign alu_info_bus[`QBMCU_DECINFO_GRP ] = `QBMCU_DECINFO_GRP_ALU; +assign alu_info_bus[`QBMCU_DECINFO_RV32 ] = rv32; +assign alu_info_bus[`QBMCU_DECINFO_ALU_ADD ] = rv32_add | rv32_addi | rv32_auipc ; +assign alu_info_bus[`QBMCU_DECINFO_ALU_SUB ] = rv32_sub ; +assign alu_info_bus[`QBMCU_DECINFO_ALU_SLT ] = rv32_slt | rv32_slti; +assign alu_info_bus[`QBMCU_DECINFO_ALU_SLTU ] = rv32_sltu | rv32_sltiu; +assign alu_info_bus[`QBMCU_DECINFO_ALU_XOR ] = rv32_xor | rv32_xori ; +assign alu_info_bus[`QBMCU_DECINFO_ALU_SLL ] = rv32_sll | rv32_slli ; +assign alu_info_bus[`QBMCU_DECINFO_ALU_SRL ] = rv32_srl | rv32_srli ; +assign alu_info_bus[`QBMCU_DECINFO_ALU_SRA ] = rv32_sra | rv32_srai ; +assign alu_info_bus[`QBMCU_DECINFO_ALU_OR ] = rv32_or | rv32_ori ; +assign alu_info_bus[`QBMCU_DECINFO_ALU_AND ] = rv32_and | rv32_andi ; +assign alu_info_bus[`QBMCU_DECINFO_ALU_LUI ] = rv32_lui ; +assign alu_info_bus[`QBMCU_DECINFO_ALU_OP2IMM] = need_imm; +assign alu_info_bus[`QBMCU_DECINFO_ALU_OP1PC ] = rv32_auipc; +assign alu_info_bus[`QBMCU_DECINFO_ALU_NOP ] = rv32_nop; + +// =========================================================================== +// Load/Store Instructions +//wire rv32_lb = rv32_load & rv32_func3_000; // I lb +//wire rv32_lh = rv32_load & rv32_func3_001; // I lh +//wire rv32_lw = rv32_load & rv32_func3_010; // I lw +//wire rv32_lbu = rv32_load & rv32_func3_100; // I lbu +//wire rv32_lhu = rv32_load & rv32_func3_101; // I lhu + +//wire rv32_sb = rv32_store & rv32_func3_000; // S sb +//wire rv32_sh = rv32_store & rv32_func3_001; // S sh +//wire rv32_sw = rv32_store & rv32_func3_010; // S sw + + +// Load/Store Data Size +wire [1:0] lsu_info_size = rv32_func3[1:0] ; +// Load/Store Data Sign +wire lsu_info_usign = rv32_func3[2]; + + +wire ldst_op = rv32_load | rv32_store; + +wire [`QBMCU_DECINFO_AGU_WIDTH-1:0] agu_info_bus; +assign agu_info_bus[`QBMCU_DECINFO_GRP ] = `QBMCU_DECINFO_GRP_AGU; +assign agu_info_bus[`QBMCU_DECINFO_RV32 ] = rv32; +assign agu_info_bus[`QBMCU_DECINFO_AGU_LOAD ] = rv32_load ; +assign agu_info_bus[`QBMCU_DECINFO_AGU_STORE ] = rv32_store ; +assign agu_info_bus[`QBMCU_DECINFO_AGU_SIZE ] = lsu_info_size; +assign agu_info_bus[`QBMCU_DECINFO_AGU_USIGN ] = lsu_info_usign; +assign agu_info_bus[`QBMCU_DECINFO_AGU_OP2IMM ] = need_imm; + +// =========================================================================== +// Expand instructions : WAIT SEND SENC EXIT EiXT_IRQ +wire rv32_wait = rv32_custom0 & rv32_func3_000; //WAIT +wire rv32_send = rv32_custom0 & rv32_func3_010; //SEND +wire rv32_sendc = rv32_custom0 & rv32_func3_011; //WAIT + +wire rv32_exit = rv32_custom1 & rv32_func3_000; //EXIT +wire rv32_exiti = rv32_custom1 & rv32_func3_001; //EXIT_IRQ + +wire ext_op = (~rv32_sxxi_shamt_ilgl) & + ( rv32_wait + | rv32_send + | rv32_sendc + | rv32_exit + | rv32_exiti) + ; +wire [`QBMCU_DECINFO_EXT_WIDTH-1:0] ext_info_bus; +assign ext_info_bus[`QBMCU_DECINFO_GRP ] = `QBMCU_DECINFO_GRP_EXT; +assign ext_info_bus[`QBMCU_DECINFO_RV32 ] = rv32; +assign ext_info_bus[`QBMCU_DECINFO_EXT_WAIT ] = rv32_wait; +assign ext_info_bus[`QBMCU_DECINFO_EXT_SEND ] = rv32_send; +assign ext_info_bus[`QBMCU_DECINFO_EXT_SENDC ] = rv32_sendc; +assign ext_info_bus[`QBMCU_DECINFO_EXT_EXIT ] = rv32_exit; +assign ext_info_bus[`QBMCU_DECINFO_EXT_EXITI ] = rv32_exiti ; +assign ext_info_bus[`QBMCU_DECINFO_EXT_OP2IMM] = need_imm; + + +// Reuse the common signals as much as possible to save gatecounts +wire rv32_all0s_ilgl = rv32_func7_0000000 + & rv32_rs2_x0 + & rv32_rs1_x0 + & rv32_func3_000 + & rv32_rd_x0 + & opcode_6_5_00 + & opcode_4_2_000 + & (opcode[1:0] == 2'b00); + +wire rv32_all1s_ilgl = rv32_func7_1111111 + & rv32_rs2_x31 + & rv32_rs1_x31 + & rv32_func3_111 + & rv32_rd_x31 + & opcode_6_5_11 + & opcode_4_2_111 + & (opcode[1:0] == 2'b11); + + +wire rv_all0s1s_ilgl = (rv32_all0s_ilgl | rv32_all1s_ilgl); + +// +// All the RV32I need RD register except the +// * Branch, Store, +wire rv32_need_rd = (~rv32_rd_x0 ) + & (~rv32_branch ) + & (~rv32_store ) + & (~rv32_custom1); + +// All the RV32I need RS1 register except the +// * lui +// * auipc +// * jal +//wire rv32_need_rs1 = (~rv32_rs1_x0) +// & (~rv32_lui ) +// & (~rv32_auipc ) +// & (~rv32_jal ); + +// Following RV32IMA instructions need RS2 register +// * branch +// * store +// * rv32_op +//wire rv32_need_rs2 = (~rv32_rs2_x0) +// & ((rv32_branch) +// | (rv32_store ) +// | (rv32_op )); + +wire [31:0] rv32_i_imm = { + {20{rv32_instr[31]}} + , rv32_instr[31:20] + }; + +wire [31:0] rv32_s_imm = { + {20{rv32_instr[31]}} + , rv32_instr[31:25] + , rv32_instr[11:7] + }; + + +wire [31:0] rv32_b_imm = { + {19{rv32_instr[31]}} + , rv32_instr[31] + , rv32_instr[7] + , rv32_instr[30:25] + , rv32_instr[11:8] + , 1'b0 + }; + +wire [31:0] rv32_u_imm = {rv32_instr[31:12],12'b0}; + +wire [31:0] rv32_j_imm = { + {11{rv32_instr[31]}} + , rv32_instr[31] + , rv32_instr[19:12] + , rv32_instr[20] + , rv32_instr[30:21] + , 1'b0 + }; +//expand immediate operands +wire [31:0] rv32_e_imm = rv32_i_imm; + +// It will select i-type immediate when +// * rv32_op_imm +// * rv32_jalr +// * rv32_load +wire rv32_imm_sel_i = rv32_op_imm | rv32_jalr | rv32_load; +//wire rv32_imm_sel_jalr = rv32_jalr; +//wire [31:0] rv32_jalr_imm = rv32_i_imm; + +// It will select u-type immediate when +// * rv32_lui, rv32_auipc +wire rv32_imm_sel_u = rv32_lui | rv32_auipc; + +// It will select j-type immediate when +// * rv32_jal +wire rv32_imm_sel_j = rv32_jal; +//wire rv32_imm_sel_jal = rv32_jal; +//wire [31:0] rv32_jal_imm = rv32_j_imm; + +// It will select b-type immediate when +// * rv32_branch +wire rv32_imm_sel_b = rv32_branch; +//wire rv32_imm_sel_bxx = rv32_branch; +//wire [31:0] rv32_bxx_imm = rv32_b_imm; + +// It will select s-type immediate when +// * rv32_store +wire rv32_imm_sel_s = rv32_store; + +// It will select e-type immediate when +// * rv32_custom0 +// * rv32_custom1 +wire rv32_imm_sel_e = rv32_custom0 | rv32_custom1; + + +wire [31:0] rv32_imm = + ({32{rv32_imm_sel_i}} & rv32_i_imm) + | ({32{rv32_imm_sel_s}} & rv32_s_imm) + | ({32{rv32_imm_sel_b}} & rv32_b_imm) + | ({32{rv32_imm_sel_u}} & rv32_u_imm) + | ({32{rv32_imm_sel_j}} & rv32_j_imm) + | ({32{rv32_imm_sel_e}} & rv32_e_imm) + ; + +wire rv32_need_imm = + rv32_imm_sel_i + | rv32_imm_sel_s + | rv32_imm_sel_b + | rv32_imm_sel_u + | rv32_imm_sel_j + | rv32_imm_sel_e + ; + + +assign need_imm = rv32_need_imm ; + +//dec_o_imm +sirv_gnrl_dfflr #(`QBMCU_XLEN) dec_o_imm_dfflr (dec_i_active_r, rv32_imm, dec_o_imm, clk, rst_n); + +//dec_o_pc +sirv_gnrl_dfflr #(`QBMCU_PC_SIZE) dec_o_pc_dfflr (dec_i_active_r, dec_i_pc, dec_o_pc, clk, rst_n); + + +assign dec_info_w = + ({`QBMCU_DECINFO_WIDTH{alu_op}} & {{`QBMCU_DECINFO_WIDTH-`QBMCU_DECINFO_ALU_WIDTH{1'b0}},alu_info_bus}) + | ({`QBMCU_DECINFO_WIDTH{ldst_op}} & {{`QBMCU_DECINFO_WIDTH-`QBMCU_DECINFO_AGU_WIDTH{1'b0}},agu_info_bus}) + | ({`QBMCU_DECINFO_WIDTH{bjp_op}} & {{`QBMCU_DECINFO_WIDTH-`QBMCU_DECINFO_BJP_WIDTH{1'b0}},bjp_info_bus}) + | ({`QBMCU_DECINFO_WIDTH{ext_op}} & {{`QBMCU_DECINFO_WIDTH-`QBMCU_DECINFO_EXT_WIDTH{1'b0}},ext_info_bus}) + ; + +//dec_o_info +sirv_gnrl_dfflr #(`QBMCU_DECINFO_WIDTH) dec_o_info_dfflr (dec_i_active_r, dec_info_w, dec_o_info, clk, rst_n); + + +//dec_o_rs1idx +sirv_gnrl_dfflr #(`QBMCU_RFIDX_WIDTH) dec_o_rs1idx_dfflr (dec_i_active_r, rv32_rs1[`QBMCU_RFIDX_WIDTH-1:0], dec_o_rs1idx, clk, rst_n); +//dec_o_rs2idx +sirv_gnrl_dfflr #(`QBMCU_RFIDX_WIDTH) dec_o_rs2idx_dfflr (dec_i_active_r, rv32_rs2[`QBMCU_RFIDX_WIDTH-1:0], dec_o_rs2idx, clk, rst_n); +//dec_o_rdidx +sirv_gnrl_dfflr #(`QBMCU_RFIDX_WIDTH) dec_o_rdidx_dfflr (dec_i_active_r, rv32_rd[`QBMCU_RFIDX_WIDTH-1:0], dec_o_rdidx, clk, rst_n); + +//dec_o_rs1en +//sirv_gnrl_dfflr #(1) dec_o_rs1en_dfflr (dec_i_active_r, rv32_need_rs1, dec_o_rs1en, clk, rst_n); +//dec_o_rs2en +//sirv_gnrl_dfflr #(1) dec_o_rs2en_dfflr (dec_i_active_r, rv32_need_rs2, dec_o_rs2en, clk, rst_n); +//dec_o_rdwen +sirv_gnrl_dfflr #(1) dec_o_rdwen_dfflr (dec_i_active_r, rv32_need_rd, dec_o_rdwen, clk, rst_n); + +wire legl_ops = + alu_op + | ldst_op + | bjp_op + | ext_op + ; + +wire rv_index_ilgl = 1'b0; + + +wire dec_ilegl_w = + (rv_all0s1s_ilgl) + | (rv_index_ilgl) + | (rv32_sxxi_shamt_ilgl) + | (~legl_ops); + +//dec_o_ilegl +sirv_gnrl_dfflr #(1) dec_o_ilegl_dfflr (dec_i_active_r, dec_ilegl_w, dec_o_ilegl, clk, rst_n); +endmodule + + +`include "qbmcu_undefines.v" diff --git a/rtl/qubitmcu/qbmcu_defines.v b/rtl/qubitmcu/qbmcu_defines.v new file mode 100644 index 0000000..590fe2b --- /dev/null +++ b/rtl/qubitmcu/qbmcu_defines.v @@ -0,0 +1,223 @@ + //+FHDR-------------------------------------------------------------------------------------------------------- +// Company: +//----------------------------------------------------------------------------------------------------------------- +// File Name : qbmcu.v +// Department : +// Author : PWY +// Author's Tel : +//----------------------------------------------------------------------------------------------------------------- +// Relese History +// Version Date Author Description +// 0.1 2024-03-13 PWY The files to include all the macro defines +//----------------------------------------------------------------------------------------------------------------- +// Keywords : +// +//----------------------------------------------------------------------------------------------------------------- +// Parameter +// +//----------------------------------------------------------------------------------------------------------------- +// Purpose : +// +//----------------------------------------------------------------------------------------------------------------- +// Target Device: +// Tool versions: +//----------------------------------------------------------------------------------------------------------------- +// Reuse Issues +// Reset Strategy: +// Clock Domains: +// Critical Timing: +// Asynchronous I/F: +// Synthesizable (y/n): +// Other: +//-FHDR-------------------------------------------------------------------------------------------------------- + + + +///////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////// +/////// ISA relevant macro +// +//system address width +`define QBMCU_ADDR_SIZE 32 + +//PC width +`define QBMCU_PC_SIZE 32 + +//system data width +`define QBMCU_XLEN 32 +//system instruction width +`define QBMCU_INSTR_SIZE 32 + +//register array index bit width +`define QBMCU_RFIDX_WIDTH 5 +//number of register arrays +`define QBMCU_RFREG_NUM 32 + +//base address of instruction memory +//initial value of the program counter (PC) -> 0x0000_0000 +`define QBMCU_ITCM_ADDR_BASE 32'h0000_0000 +//base address of data memory +`define QBMCU_DTCM_ADDR_BASE 32'h0010_0000 + +//data memory address width +`define QBMCU_DTCM_ADDR_SIZE 15 + +//instruction memory address width +`define QBMCU_ITCM_ADDR_SIZE 15 + +//BUS memory address width +`define QBMCU_BUS_ADDR_SIZE 25 + +///////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////// +/////// ALU relevant macro +// + +`define QBMCU_ALU_ADDER_WIDTH (`QBMCU_XLEN+1) + + +///////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////// +/////// Decode relevant macro +// + `define QBMCU_DECINFO_GRP_WIDTH 3 + `define QBMCU_DECINFO_GRP_ALU `QBMCU_DECINFO_GRP_WIDTH'd0 + `define QBMCU_DECINFO_GRP_AGU `QBMCU_DECINFO_GRP_WIDTH'd1 + `define QBMCU_DECINFO_GRP_BJP `QBMCU_DECINFO_GRP_WIDTH'd2 + `define QBMCU_DECINFO_GRP_EXT `QBMCU_DECINFO_GRP_WIDTH'd3 + + + `define QBMCU_DECINFO_GRP_LSB 0 + `define QBMCU_DECINFO_GRP_MSB (`QBMCU_DECINFO_GRP_LSB+`QBMCU_DECINFO_GRP_WIDTH-1) + `define QBMCU_DECINFO_GRP `QBMCU_DECINFO_GRP_MSB:`QBMCU_DECINFO_GRP_LSB + `define QBMCU_DECINFO_RV32_LSB (`QBMCU_DECINFO_GRP_MSB+1) + `define QBMCU_DECINFO_RV32_MSB (`QBMCU_DECINFO_RV32_LSB+1-1) + `define QBMCU_DECINFO_RV32 `QBMCU_DECINFO_RV32_MSB:`QBMCU_DECINFO_RV32_LSB + + `define QBMCU_DECINFO_SUBDECINFO_LSB (`QBMCU_DECINFO_RV32_MSB+1) + + // ALU group + `define QBMCU_DECINFO_ALU_ADD_LSB `QBMCU_DECINFO_SUBDECINFO_LSB + `define QBMCU_DECINFO_ALU_ADD_MSB (`QBMCU_DECINFO_ALU_ADD_LSB+1-1) + `define QBMCU_DECINFO_ALU_ADD `QBMCU_DECINFO_ALU_ADD_MSB :`QBMCU_DECINFO_ALU_ADD_LSB + `define QBMCU_DECINFO_ALU_SUB_LSB (`QBMCU_DECINFO_ALU_ADD_MSB+1) + `define QBMCU_DECINFO_ALU_SUB_MSB (`QBMCU_DECINFO_ALU_SUB_LSB+1-1) + `define QBMCU_DECINFO_ALU_SUB `QBMCU_DECINFO_ALU_SUB_MSB :`QBMCU_DECINFO_ALU_SUB_LSB + `define QBMCU_DECINFO_ALU_XOR_LSB (`QBMCU_DECINFO_ALU_SUB_MSB+1) + `define QBMCU_DECINFO_ALU_XOR_MSB (`QBMCU_DECINFO_ALU_XOR_LSB+1-1) + `define QBMCU_DECINFO_ALU_XOR `QBMCU_DECINFO_ALU_XOR_MSB :`QBMCU_DECINFO_ALU_XOR_LSB + `define QBMCU_DECINFO_ALU_SLL_LSB (`QBMCU_DECINFO_ALU_XOR_MSB+1) + `define QBMCU_DECINFO_ALU_SLL_MSB (`QBMCU_DECINFO_ALU_SLL_LSB+1-1) + `define QBMCU_DECINFO_ALU_SLL `QBMCU_DECINFO_ALU_SLL_MSB :`QBMCU_DECINFO_ALU_SLL_LSB + `define QBMCU_DECINFO_ALU_SRL_LSB (`QBMCU_DECINFO_ALU_SLL_MSB+1) + `define QBMCU_DECINFO_ALU_SRL_MSB (`QBMCU_DECINFO_ALU_SRL_LSB+1-1) + `define QBMCU_DECINFO_ALU_SRL `QBMCU_DECINFO_ALU_SRL_MSB :`QBMCU_DECINFO_ALU_SRL_LSB + `define QBMCU_DECINFO_ALU_SRA_LSB (`QBMCU_DECINFO_ALU_SRL_MSB+1) + `define QBMCU_DECINFO_ALU_SRA_MSB (`QBMCU_DECINFO_ALU_SRA_LSB+1-1) + `define QBMCU_DECINFO_ALU_SRA `QBMCU_DECINFO_ALU_SRA_MSB :`QBMCU_DECINFO_ALU_SRA_LSB + `define QBMCU_DECINFO_ALU_OR_LSB (`QBMCU_DECINFO_ALU_SRA_MSB+1) + `define QBMCU_DECINFO_ALU_OR_MSB (`QBMCU_DECINFO_ALU_OR_LSB+1-1) + `define QBMCU_DECINFO_ALU_OR `QBMCU_DECINFO_ALU_OR_MSB :`QBMCU_DECINFO_ALU_OR_LSB + `define QBMCU_DECINFO_ALU_AND_LSB (`QBMCU_DECINFO_ALU_OR_MSB+1) + `define QBMCU_DECINFO_ALU_AND_MSB (`QBMCU_DECINFO_ALU_AND_LSB+1-1) + `define QBMCU_DECINFO_ALU_AND `QBMCU_DECINFO_ALU_AND_MSB :`QBMCU_DECINFO_ALU_AND_LSB + `define QBMCU_DECINFO_ALU_SLT_LSB (`QBMCU_DECINFO_ALU_AND_MSB+1) + `define QBMCU_DECINFO_ALU_SLT_MSB (`QBMCU_DECINFO_ALU_SLT_LSB+1-1) + `define QBMCU_DECINFO_ALU_SLT `QBMCU_DECINFO_ALU_SLT_MSB :`QBMCU_DECINFO_ALU_SLT_LSB + `define QBMCU_DECINFO_ALU_SLTU_LSB (`QBMCU_DECINFO_ALU_SLT_MSB+1) + `define QBMCU_DECINFO_ALU_SLTU_MSB (`QBMCU_DECINFO_ALU_SLTU_LSB+1-1) + `define QBMCU_DECINFO_ALU_SLTU `QBMCU_DECINFO_ALU_SLTU_MSB:`QBMCU_DECINFO_ALU_SLTU_LSB + `define QBMCU_DECINFO_ALU_LUI_LSB (`QBMCU_DECINFO_ALU_SLTU_MSB+1) + `define QBMCU_DECINFO_ALU_LUI_MSB (`QBMCU_DECINFO_ALU_LUI_LSB+1-1) + `define QBMCU_DECINFO_ALU_LUI `QBMCU_DECINFO_ALU_LUI_MSB :`QBMCU_DECINFO_ALU_LUI_LSB + `define QBMCU_DECINFO_ALU_OP2IMM_LSB (`QBMCU_DECINFO_ALU_LUI_MSB+1) + `define QBMCU_DECINFO_ALU_OP2IMM_MSB (`QBMCU_DECINFO_ALU_OP2IMM_LSB+1-1) + `define QBMCU_DECINFO_ALU_OP2IMM `QBMCU_DECINFO_ALU_OP2IMM_MSB :`QBMCU_DECINFO_ALU_OP2IMM_LSB + `define QBMCU_DECINFO_ALU_OP1PC_LSB (`QBMCU_DECINFO_ALU_OP2IMM_MSB+1) + `define QBMCU_DECINFO_ALU_OP1PC_MSB (`QBMCU_DECINFO_ALU_OP1PC_LSB+1-1) + `define QBMCU_DECINFO_ALU_OP1PC `QBMCU_DECINFO_ALU_OP1PC_MSB :`QBMCU_DECINFO_ALU_OP1PC_LSB + `define QBMCU_DECINFO_ALU_NOP_LSB (`QBMCU_DECINFO_ALU_OP1PC_MSB+1) + `define QBMCU_DECINFO_ALU_NOP_MSB (`QBMCU_DECINFO_ALU_NOP_LSB+1-1) + `define QBMCU_DECINFO_ALU_NOP `QBMCU_DECINFO_ALU_NOP_MSB :`QBMCU_DECINFO_ALU_NOP_LSB + + `define QBMCU_DECINFO_ALU_WIDTH (`QBMCU_DECINFO_ALU_NOP_MSB+1) + + //AGU group + `define QBMCU_DECINFO_AGU_LOAD_LSB `QBMCU_DECINFO_SUBDECINFO_LSB + `define QBMCU_DECINFO_AGU_LOAD_MSB (`QBMCU_DECINFO_AGU_LOAD_LSB+1-1) + `define QBMCU_DECINFO_AGU_LOAD `QBMCU_DECINFO_AGU_LOAD_MSB :`QBMCU_DECINFO_AGU_LOAD_LSB + `define QBMCU_DECINFO_AGU_STORE_LSB (`QBMCU_DECINFO_AGU_LOAD_MSB+1) + `define QBMCU_DECINFO_AGU_STORE_MSB (`QBMCU_DECINFO_AGU_STORE_LSB+1-1) + `define QBMCU_DECINFO_AGU_STORE `QBMCU_DECINFO_AGU_STORE_MSB :`QBMCU_DECINFO_AGU_STORE_LSB + `define QBMCU_DECINFO_AGU_SIZE_LSB (`QBMCU_DECINFO_AGU_STORE_MSB+1) + `define QBMCU_DECINFO_AGU_SIZE_MSB (`QBMCU_DECINFO_AGU_SIZE_LSB+2-1) + `define QBMCU_DECINFO_AGU_SIZE `QBMCU_DECINFO_AGU_SIZE_MSB :`QBMCU_DECINFO_AGU_SIZE_LSB + `define QBMCU_DECINFO_AGU_USIGN_LSB (`QBMCU_DECINFO_AGU_SIZE_MSB+1) + `define QBMCU_DECINFO_AGU_USIGN_MSB (`QBMCU_DECINFO_AGU_USIGN_LSB+1-1) + `define QBMCU_DECINFO_AGU_USIGN `QBMCU_DECINFO_AGU_USIGN_MSB :`QBMCU_DECINFO_AGU_USIGN_LSB + `define QBMCU_DECINFO_AGU_OP2IMM_LSB (`QBMCU_DECINFO_AGU_USIGN_MSB+1) + `define QBMCU_DECINFO_AGU_OP2IMM_MSB (`QBMCU_DECINFO_AGU_OP2IMM_LSB+1-1) + `define QBMCU_DECINFO_AGU_OP2IMM `QBMCU_DECINFO_AGU_OP2IMM_MSB:`QBMCU_DECINFO_AGU_OP2IMM_LSB + + `define QBMCU_DECINFO_AGU_WIDTH (`QBMCU_DECINFO_AGU_OP2IMM_MSB+1) + + // Bxx group + `define QBMCU_DECINFO_BJP_JUMP_LSB `QBMCU_DECINFO_SUBDECINFO_LSB + `define QBMCU_DECINFO_BJP_JUMP_MSB (`QBMCU_DECINFO_BJP_JUMP_LSB+1-1) + `define QBMCU_DECINFO_BJP_JUMP `QBMCU_DECINFO_BJP_JUMP_MSB :`QBMCU_DECINFO_BJP_JUMP_LSB + `define QBMCU_DECINFO_BJP_BPRDT_LSB (`QBMCU_DECINFO_BJP_JUMP_MSB+1) + `define QBMCU_DECINFO_BJP_BPRDT_MSB (`QBMCU_DECINFO_BJP_BPRDT_LSB+1-1) + `define QBMCU_DECINFO_BJP_JALR `QBMCU_DECINFO_BJP_BPRDT_MSB:`QBMCU_DECINFO_BJP_BPRDT_LSB + `define QBMCU_DECINFO_BJP_BEQ_LSB (`QBMCU_DECINFO_BJP_BPRDT_MSB+1) + `define QBMCU_DECINFO_BJP_BEQ_MSB (`QBMCU_DECINFO_BJP_BEQ_LSB+1-1) + `define QBMCU_DECINFO_BJP_BEQ `QBMCU_DECINFO_BJP_BEQ_MSB :`QBMCU_DECINFO_BJP_BEQ_LSB + `define QBMCU_DECINFO_BJP_BNE_LSB (`QBMCU_DECINFO_BJP_BEQ_MSB+1) + `define QBMCU_DECINFO_BJP_BNE_MSB (`QBMCU_DECINFO_BJP_BNE_LSB+1-1) + `define QBMCU_DECINFO_BJP_BNE `QBMCU_DECINFO_BJP_BNE_MSB :`QBMCU_DECINFO_BJP_BNE_LSB + `define QBMCU_DECINFO_BJP_BLT_LSB (`QBMCU_DECINFO_BJP_BNE_MSB+1) + `define QBMCU_DECINFO_BJP_BLT_MSB (`QBMCU_DECINFO_BJP_BLT_LSB+1-1) + `define QBMCU_DECINFO_BJP_BLT `QBMCU_DECINFO_BJP_BLT_MSB :`QBMCU_DECINFO_BJP_BLT_LSB + `define QBMCU_DECINFO_BJP_BGT_LSB (`QBMCU_DECINFO_BJP_BLT_MSB+1) + `define QBMCU_DECINFO_BJP_BGT_MSB (`QBMCU_DECINFO_BJP_BGT_LSB+1-1) + `define QBMCU_DECINFO_BJP_BGT `QBMCU_DECINFO_BJP_BGT_MSB :`QBMCU_DECINFO_BJP_BGT_LSB + `define QBMCU_DECINFO_BJP_BLTU_LSB (`QBMCU_DECINFO_BJP_BGT_MSB+1) + `define QBMCU_DECINFO_BJP_BLTU_MSB (`QBMCU_DECINFO_BJP_BLTU_LSB+1-1) + `define QBMCU_DECINFO_BJP_BLTU `QBMCU_DECINFO_BJP_BLTU_MSB :`QBMCU_DECINFO_BJP_BLTU_LSB + `define QBMCU_DECINFO_BJP_BGTU_LSB (`QBMCU_DECINFO_BJP_BLTU_MSB+1) + `define QBMCU_DECINFO_BJP_BGTU_MSB (`QBMCU_DECINFO_BJP_BGTU_LSB+1-1) + `define QBMCU_DECINFO_BJP_BGTU `QBMCU_DECINFO_BJP_BGTU_MSB :`QBMCU_DECINFO_BJP_BGTU_LSB + `define QBMCU_DECINFO_BJP_BXX_LSB (`QBMCU_DECINFO_BJP_BGTU_MSB+1) + `define QBMCU_DECINFO_BJP_BXX_MSB (`QBMCU_DECINFO_BJP_BXX_LSB+1-1) + `define QBMCU_DECINFO_BJP_BXX `QBMCU_DECINFO_BJP_BXX_MSB :`QBMCU_DECINFO_BJP_BXX_LSB + +`define QBMCU_DECINFO_BJP_WIDTH (`QBMCU_DECINFO_BJP_BXX_MSB+1) + + + // EXT group + `define QBMCU_DECINFO_EXT_WAIT_LSB `QBMCU_DECINFO_SUBDECINFO_LSB + `define QBMCU_DECINFO_EXT_WAIT_MSB (`QBMCU_DECINFO_EXT_WAIT_LSB+1-1) + `define QBMCU_DECINFO_EXT_WAIT `QBMCU_DECINFO_EXT_WAIT_MSB:`QBMCU_DECINFO_EXT_WAIT_LSB + `define QBMCU_DECINFO_EXT_SEND_LSB (`QBMCU_DECINFO_EXT_WAIT_MSB+1) + `define QBMCU_DECINFO_EXT_SEND_MSB (`QBMCU_DECINFO_EXT_SEND_LSB+1-1) + `define QBMCU_DECINFO_EXT_SEND `QBMCU_DECINFO_EXT_SEND_MSB:`QBMCU_DECINFO_EXT_SEND_LSB + `define QBMCU_DECINFO_EXT_SENDC_LSB (`QBMCU_DECINFO_EXT_SEND_MSB+1) + `define QBMCU_DECINFO_EXT_SENDC_MSB (`QBMCU_DECINFO_EXT_SENDC_LSB+1-1) + `define QBMCU_DECINFO_EXT_SENDC `QBMCU_DECINFO_EXT_SENDC_MSB:`QBMCU_DECINFO_EXT_SENDC_LSB + `define QBMCU_DECINFO_EXT_EXIT_LSB (`QBMCU_DECINFO_EXT_SENDC_MSB+1) + `define QBMCU_DECINFO_EXT_EXIT_MSB (`QBMCU_DECINFO_EXT_EXIT_LSB+1-1) + `define QBMCU_DECINFO_EXT_EXIT `QBMCU_DECINFO_EXT_EXIT_MSB:`QBMCU_DECINFO_EXT_EXIT_LSB + `define QBMCU_DECINFO_EXT_EXITI_LSB (`QBMCU_DECINFO_EXT_EXIT_MSB+1) + `define QBMCU_DECINFO_EXT_EXITI_MSB (`QBMCU_DECINFO_EXT_EXITI_LSB+1-1) + `define QBMCU_DECINFO_EXT_EXITI `QBMCU_DECINFO_EXT_EXITI_MSB:`QBMCU_DECINFO_EXT_EXITI_LSB + `define QBMCU_DECINFO_EXT_OP2IMM_LSB (`QBMCU_DECINFO_EXT_EXITI_MSB+1) + `define QBMCU_DECINFO_EXT_OP2IMM_MSB (`QBMCU_DECINFO_EXT_OP2IMM_LSB+1-1) + `define QBMCU_DECINFO_EXT_OP2IMM `QBMCU_DECINFO_EXT_OP2IMM_MSB:`QBMCU_DECINFO_EXT_OP2IMM_LSB + +`define QBMCU_DECINFO_EXT_WIDTH (`QBMCU_DECINFO_EXT_OP2IMM_MSB+1) + +// Choose the longest group as the final DEC info width +`define QBMCU_DECINFO_WIDTH (`QBMCU_DECINFO_ALU_WIDTH+1) + diff --git a/rtl/qubitmcu/qbmcu_exu.v b/rtl/qubitmcu/qbmcu_exu.v new file mode 100644 index 0000000..f8169db --- /dev/null +++ b/rtl/qubitmcu/qbmcu_exu.v @@ -0,0 +1,385 @@ +//+FHDR-------------------------------------------------------------------------------------------------------- +// Company: +//----------------------------------------------------------------------------------------------------------------- +// File Name : qbmcu_exu.v +// Department : +// Author : PWY +// Author's Tel : +//----------------------------------------------------------------------------------------------------------------- +// Relese History +// Version Date Author Description +// 0.1 2024-03-13 PWY The EXU module to implement entire Execution Stage +//----------------------------------------------------------------------------------------------------------------- +// Keywords : +// +//----------------------------------------------------------------------------------------------------------------- +// Parameter +// +//----------------------------------------------------------------------------------------------------------------- +// Purpose : +// +//----------------------------------------------------------------------------------------------------------------- +// Target Device: +// Tool versions: +//----------------------------------------------------------------------------------------------------------------- +// Reuse Issues +// Reset Strategy: +// Clock Domains: +// Critical Timing: +// Asynchronous I/F: +// Synthesizable (y/n): +// Other: +//-FHDR-------------------------------------------------------------------------------------------------------- + +`include "qbmcu_defines.v" + + +module qbmcu_exu( + //system port + input clk + ,input rst_n + ////////////////////////////////////////////////////////////// + ////////////////////////////////////////////////////////////// + // The Handshake Interface + // + ,input [`QBMCU_XLEN-1 :0] exu_i_rs1 + ,input [`QBMCU_XLEN-1 :0] exu_i_rs2 + ,input [`QBMCU_XLEN-1 :0] exu_i_imm + ,input [`QBMCU_PC_SIZE-1 :0] exu_i_pc + ,input [`QBMCU_DECINFO_WIDTH-1 :0] exu_i_info + ,input exu_i_ilegl + + //The enable signal from the master control state machine + ,input exu_i_active + + ////////////////////////////////////////////////////////////// + //Data sent to the write-back module + //write back interface + ,output [`QBMCU_XLEN-1 :0] bjp_o_wbck_wdat + ,output bjp_o_wbck_valid + ////////////////////////////////////////////////////////////// + //update the value of the program counter (PC) + ,output bjp_update_pc_req + ,output [`QBMCU_PC_SIZE-1 :0] bjp_update_pc_value + + // The operands and info to peripheral + ,output ext_o_wait_valid + ,output ext_o_wait + ,output [`QBMCU_XLEN-1 :0] ext_o_wait_cnt + ,output ext_o_send + ,output ext_o_sendc + ,output [`QBMCU_XLEN-1 :0] ext_o_codeword + ,output ext_o_exit + ,output ext_o_intr + ,output [`QBMCU_XLEN-1 :0] ext_o_wbck_wdat + ,output ext_o_wbck_valid + + ////////////////////////////////////////////////////////////// + //Address, data, and enable signals connected to the memory space + ,output [`QBMCU_ADDR_SIZE-1 :0] agu_o_addr + ,output [`QBMCU_XLEN-1 :0] agu_o_wdata + ,output agu_o_wren // Write enable + ,output agu_o_rden // Read enable + ,output [`QBMCU_XLEN/8-1 :0] agu_o_wmask + ,input [`QBMCU_XLEN-1 :0] agu_i_rdata + + //Data sent to the write-back module + //write back interface + ,output [`QBMCU_XLEN-1 :0] agu_o_wbck_wdat + ,output agu_o_wbck_valid + //Misaligned memory address + ,output agu_o_addr_unalgn + + // The Write-Back Interface for Special (unaligned ldst instructions) + ,output [`QBMCU_XLEN-1 :0] alu_o_wbck_wdat + ,output alu_o_wbck_valid + + ); + + + + +//////////////////////////////////////////////////////////////////////////////////////////////////////////// +//AGU +//////////////////////////////////////////////////////////////////////////////////////////////////////////// +wire [`QBMCU_XLEN-1 :0] agu_i_rs1 ; +wire [`QBMCU_XLEN-1 :0] agu_i_rs2 ; +wire [`QBMCU_XLEN-1 :0] agu_i_imm ; +wire [`QBMCU_DECINFO_WIDTH-1 :0] agu_i_info ; +wire agu_i_op ; + +//qbmcu_datalatch_agu +qbmcu_datalatch #( + .DECINFO_GRP_OP ( `QBMCU_DECINFO_GRP_AGU ) + ) U_qubitmcu_datalatch_agu + ( + .i_rs1 ( exu_i_rs1 ) + ,.i_rs2 ( exu_i_rs2 ) + ,.i_imm ( exu_i_imm ) + ,.i_info ( exu_i_info ) + ,.i_pc ( exu_i_pc ) + ,.i_ilegl ( exu_i_ilegl ) + ,.o_rs1 ( agu_i_rs1 ) + ,.o_rs2 ( agu_i_rs2 ) + ,.o_imm ( agu_i_imm ) + ,.o_info ( agu_i_info ) + ,.o_pc ( ) + ,.o_op ( agu_i_op ) + ); + +//qbmcu_exu_lsuagu +qbmcu_exu_lsuagu U_qbmcu_exu_lsuagu ( + .clk ( clk ) + ,.rst_n ( rst_n ) + ,.agu_i_rs1 ( agu_i_rs1 ) + ,.agu_i_rs2 ( agu_i_rs2 ) + ,.agu_i_imm ( agu_i_imm ) + ,.agu_i_info ( agu_i_info[`QBMCU_DECINFO_AGU_WIDTH-1:0]) + ,.agu_i_op ( agu_i_op ) + ,.agu_i_active ( exu_i_active ) + ,.agu_o_addr ( agu_o_addr ) + ,.agu_o_wdata ( agu_o_wdata ) + ,.agu_o_wren ( agu_o_wren ) + ,.agu_o_rden ( agu_o_rden ) + ,.agu_o_wmask ( agu_o_wmask ) + ,.agu_i_rdata ( agu_i_rdata ) + ,.agu_o_wbck_wdat ( agu_o_wbck_wdat ) + ,.agu_o_wbck_valid ( agu_o_wbck_valid ) + ,.agu_o_addr_unalgn ( agu_o_addr_unalgn ) + ); + +//////////////////////////////////////////////////////////////////////////////////////////////////////////// +//EXT +//////////////////////////////////////////////////////////////////////////////////////////////////////////// +wire [`QBMCU_XLEN-1 :0] ext_i_rs1 ; +wire [`QBMCU_XLEN-1 :0] ext_i_imm ; +wire [`QBMCU_DECINFO_WIDTH-1 :0] ext_i_info ; +wire ext_i_op ; + +//qbmcu_datalatch_ext +qbmcu_datalatch #( + .DECINFO_GRP_OP ( `QBMCU_DECINFO_GRP_EXT ) + ) U_qubitmcu_datalatch_ext + ( + .i_rs1 ( exu_i_rs1 ) + ,.i_rs2 ( exu_i_rs2 ) + ,.i_imm ( exu_i_imm ) + ,.i_info ( exu_i_info ) + ,.i_pc ( exu_i_pc ) + ,.i_ilegl ( exu_i_ilegl ) + ,.o_rs1 ( ext_i_rs1 ) + ,.o_rs2 ( ) + ,.o_imm ( ext_i_imm ) + ,.o_info ( ext_i_info ) + ,.o_pc ( ) + ,.o_op ( ext_i_op ) + ); + +//qbmcu_exu_ext +qbmcu_exu_ext U_qbmcu_exu_ext ( + .clk ( clk ) + ,.rst_n ( rst_n ) + ,.ext_i_rs1 ( ext_i_rs1 ) + ,.ext_i_imm ( ext_i_imm ) + ,.ext_i_info ( ext_i_info[`QBMCU_DECINFO_EXT_WIDTH-1:0]) + ,.ext_i_op ( ext_i_op ) + ,.ext_o_wait_valid ( ext_o_wait_valid ) + ,.ext_i_active ( exu_i_active ) + ,.ext_o_wait ( ext_o_wait ) + ,.ext_o_wait_cnt ( ext_o_wait_cnt ) + ,.ext_o_send ( ext_o_send ) + ,.ext_o_sendc ( ext_o_sendc ) + ,.ext_o_codeword ( ext_o_codeword ) + ,.ext_o_exit ( ext_o_exit ) + ,.ext_o_intr ( ext_o_intr ) + ,.ext_o_wbck_wdat ( ext_o_wbck_wdat ) + ,.ext_o_wbck_valid ( ext_o_wbck_valid ) + ); + +//////////////////////////////////////////////////////////////////////////////////////////////////////////// +//BJP +//////////////////////////////////////////////////////////////////////////////////////////////////////////// +wire [`QBMCU_XLEN-1 :0] bjp_i_rs1 ; +wire [`QBMCU_XLEN-1 :0] bjp_i_rs2 ; +wire [`QBMCU_XLEN-1 :0] bjp_i_imm ; +wire [`QBMCU_DECINFO_WIDTH-1 :0] bjp_i_info ; +wire [`QBMCU_PC_SIZE-1 :0] bjp_i_pc ; +wire bjp_i_op ; + +////////////////////////////////////////////////////////////// +// To share the ALU datapath +// The operands and info to ALU +wire [`QBMCU_XLEN-1 :0] bjp_req_alu_op1 ; +wire [`QBMCU_XLEN-1 :0] bjp_req_alu_op2 ; +wire bjp_req_alu_cmp_eq ; +wire bjp_req_alu_cmp_ne ; +wire bjp_req_alu_cmp_lt ; +wire bjp_req_alu_cmp_gt ; +wire bjp_req_alu_cmp_ltu ; +wire bjp_req_alu_cmp_gtu ; +wire bjp_req_alu_add ; +wire bjp_req_alu_cmp_res ; +wire [`QBMCU_XLEN-1 :0] bjp_req_alu_add_res ; + +//qbmcu_datalatch_bjp +qbmcu_datalatch #( + .DECINFO_GRP_OP ( `QBMCU_DECINFO_GRP_BJP ) + ) U_qubitmcu_datalatch_bjp + ( + .i_rs1 ( exu_i_rs1 ) + ,.i_rs2 ( exu_i_rs2 ) + ,.i_imm ( exu_i_imm ) + ,.i_info ( exu_i_info ) + ,.i_pc ( exu_i_pc ) + ,.i_ilegl ( exu_i_ilegl ) + ,.o_rs1 ( bjp_i_rs1 ) + ,.o_rs2 ( bjp_i_rs2 ) + ,.o_imm ( bjp_i_imm ) + ,.o_info ( bjp_i_info ) + ,.o_pc ( bjp_i_pc ) + ,.o_op ( bjp_i_op ) + ); + + +//qbmcu_exu_bjp +qbmcu_exu_bjp U_qbmcu_exu_bjp ( + .clk ( clk ) + ,.rst_n ( rst_n ) + ,.bjp_i_rs1 ( bjp_i_rs1 ) + ,.bjp_i_rs2 ( bjp_i_rs2 ) + ,.bjp_i_imm ( bjp_i_imm ) + ,.bjp_i_pc ( bjp_i_pc ) + ,.bjp_i_info ( bjp_i_info[`QBMCU_DECINFO_BJP_WIDTH-1:0]) + ,.bjp_i_op ( bjp_i_op ) + ,.bjp_i_active ( exu_i_active ) + ,.bjp_o_wbck_valid ( bjp_o_wbck_valid ) + ,.bjp_o_wbck_wdat ( bjp_o_wbck_wdat ) + ,.update_pc_req ( bjp_update_pc_req ) + ,.update_pc_value ( bjp_update_pc_value ) + ,.bjp_req_alu_op1 ( bjp_req_alu_op1 ) + ,.bjp_req_alu_op2 ( bjp_req_alu_op2 ) + ,.bjp_req_alu_cmp_eq ( bjp_req_alu_cmp_eq ) + ,.bjp_req_alu_cmp_ne ( bjp_req_alu_cmp_ne ) + ,.bjp_req_alu_cmp_lt ( bjp_req_alu_cmp_lt ) + ,.bjp_req_alu_cmp_gt ( bjp_req_alu_cmp_gt ) + ,.bjp_req_alu_cmp_ltu ( bjp_req_alu_cmp_ltu ) + ,.bjp_req_alu_cmp_gtu ( bjp_req_alu_cmp_gtu ) + ,.bjp_req_alu_add ( bjp_req_alu_add ) + ,.bjp_req_alu_cmp_res ( bjp_req_alu_cmp_res ) + ,.bjp_req_alu_add_res ( bjp_req_alu_add_res ) + ); + +//////////////////////////////////////////////////////////////////////////////////////////////////////////// +//ALU +//////////////////////////////////////////////////////////////////////////////////////////////////////////// +wire [`QBMCU_XLEN-1 :0] alu_i_rs1 ; +wire [`QBMCU_XLEN-1 :0] alu_i_rs2 ; +wire [`QBMCU_XLEN-1 :0] alu_i_imm ; +wire [`QBMCU_DECINFO_WIDTH-1 :0] alu_i_info ; +wire [`QBMCU_PC_SIZE-1 :0] alu_i_pc ; +wire alu_i_op ; +////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////// +// To share the ALU datapath +// +// The operands and info to ALU +wire alu_req_alu_add ; +wire alu_req_alu_sub ; +wire alu_req_alu_xor ; +wire alu_req_alu_sll ; +wire alu_req_alu_srl ; +wire alu_req_alu_sra ; +wire alu_req_alu_or ; +wire alu_req_alu_and ; +wire alu_req_alu_slt ; +wire alu_req_alu_sltu ; +wire alu_req_alu_lui ; +wire [`QBMCU_XLEN-1 :0] alu_req_alu_op1 ; +wire [`QBMCU_XLEN-1 :0] alu_req_alu_op2 ; +wire [`QBMCU_XLEN-1 :0] alu_req_alu_res ; + +//qbmcu_datalatch_alu +qbmcu_datalatch #( + .DECINFO_GRP_OP ( `QBMCU_DECINFO_GRP_ALU ) + ) U_qbmcu_datalatch_alu + ( + .i_rs1 ( exu_i_rs1 ) + ,.i_rs2 ( exu_i_rs2 ) + ,.i_imm ( exu_i_imm ) + ,.i_info ( exu_i_info ) + ,.i_pc ( exu_i_pc ) + ,.i_ilegl ( exu_i_ilegl ) + ,.o_rs1 ( alu_i_rs1 ) + ,.o_rs2 ( alu_i_rs2 ) + ,.o_imm ( alu_i_imm ) + ,.o_info ( alu_i_info ) + ,.o_pc ( alu_i_pc ) + ,.o_op ( alu_i_op ) + ); + +//qbmcu_exu_alu_rglr +qbmcu_exu_alu U_qbmcu_exu_alu ( + .clk ( clk ) + ,.rst_n ( rst_n ) + ,.alu_i_rs1 ( alu_i_rs1 ) + ,.alu_i_rs2 ( alu_i_rs2 ) + ,.alu_i_imm ( alu_i_imm ) + ,.alu_i_pc ( alu_i_pc ) + ,.alu_i_info ( alu_i_info[`QBMCU_DECINFO_ALU_WIDTH-1:0]) + ,.alu_i_op ( alu_i_op ) + ,.alu_i_active ( exu_i_active ) + ,.alu_o_wbck_wdat ( alu_o_wbck_wdat ) + ,.alu_o_wbck_valid ( alu_o_wbck_valid ) + ,.alu_req_alu_add ( alu_req_alu_add ) + ,.alu_req_alu_sub ( alu_req_alu_sub ) + ,.alu_req_alu_xor ( alu_req_alu_xor ) + ,.alu_req_alu_sll ( alu_req_alu_sll ) + ,.alu_req_alu_srl ( alu_req_alu_srl ) + ,.alu_req_alu_sra ( alu_req_alu_sra ) + ,.alu_req_alu_or ( alu_req_alu_or ) + ,.alu_req_alu_and ( alu_req_alu_and ) + ,.alu_req_alu_slt ( alu_req_alu_slt ) + ,.alu_req_alu_sltu ( alu_req_alu_sltu ) + ,.alu_req_alu_lui ( alu_req_alu_lui ) + ,.alu_req_alu_op1 ( alu_req_alu_op1 ) + ,.alu_req_alu_op2 ( alu_req_alu_op2 ) + ,.alu_req_alu_res ( alu_req_alu_res ) + ); + +//////////////////////////////////////////////////////////////////////////////////////////////////////////// +//DPATH +//////////////////////////////////////////////////////////////////////////////////////////////////////////// + +qbmcu_exu_dpath U_qbmcu_exu_dpath ( + .alu_req_alu ( alu_i_op ) + ,.alu_req_alu_add ( alu_req_alu_add ) + ,.alu_req_alu_sub ( alu_req_alu_sub ) + ,.alu_req_alu_xor ( alu_req_alu_xor ) + ,.alu_req_alu_sll ( alu_req_alu_sll ) + ,.alu_req_alu_srl ( alu_req_alu_srl ) + ,.alu_req_alu_sra ( alu_req_alu_sra ) + ,.alu_req_alu_or ( alu_req_alu_or ) + ,.alu_req_alu_and ( alu_req_alu_and ) + ,.alu_req_alu_slt ( alu_req_alu_slt ) + ,.alu_req_alu_sltu ( alu_req_alu_sltu ) + ,.alu_req_alu_lui ( alu_req_alu_lui ) + ,.alu_req_alu_op1 ( alu_req_alu_op1 ) + ,.alu_req_alu_op2 ( alu_req_alu_op2 ) + ,.alu_req_alu_res ( alu_req_alu_res ) + ,.bjp_req_alu ( bjp_i_op ) + ,.bjp_req_alu_op1 ( bjp_req_alu_op1 ) + ,.bjp_req_alu_op2 ( bjp_req_alu_op2 ) + ,.bjp_req_alu_cmp_eq ( bjp_req_alu_cmp_eq ) + ,.bjp_req_alu_cmp_ne ( bjp_req_alu_cmp_ne ) + ,.bjp_req_alu_cmp_lt ( bjp_req_alu_cmp_lt ) + ,.bjp_req_alu_cmp_gt ( bjp_req_alu_cmp_gt ) + ,.bjp_req_alu_cmp_ltu ( bjp_req_alu_cmp_ltu ) + ,.bjp_req_alu_cmp_gtu ( bjp_req_alu_cmp_gtu ) + ,.bjp_req_alu_add ( bjp_req_alu_add ) + ,.bjp_req_alu_cmp_res ( bjp_req_alu_cmp_res ) + ,.bjp_req_alu_add_res ( bjp_req_alu_add_res ) + ); +endmodule + + +`include "qbmcu_undefines.v" diff --git a/rtl/qubitmcu/qbmcu_exu_alu.v b/rtl/qubitmcu/qbmcu_exu_alu.v new file mode 100644 index 0000000..5c2fdd9 --- /dev/null +++ b/rtl/qubitmcu/qbmcu_exu_alu.v @@ -0,0 +1,106 @@ +//+FHDR-------------------------------------------------------------------------------------------------------- +// Company: +//----------------------------------------------------------------------------------------------------------------- +// File Name : qbmcu_exu_alu.v +// Department : +// Author : PWY +// Author's Tel : +//----------------------------------------------------------------------------------------------------------------- +// Relese History +// Version Date Author Description +// 0.1 2024-03-13 PWY This module to implement the regular ALU instructions +//----------------------------------------------------------------------------------------------------------------- +// Keywords : +// +//----------------------------------------------------------------------------------------------------------------- +// Parameter +// +//----------------------------------------------------------------------------------------------------------------- +// Purpose : +// +//----------------------------------------------------------------------------------------------------------------- +// Target Device: +// Tool versions: +//----------------------------------------------------------------------------------------------------------------- +// Reuse Issues +// Reset Strategy: +// Clock Domains: +// Critical Timing: +// Asynchronous I/F: +// Synthesizable (y/n): +// Other: +//-FHDR-------------------------------------------------------------------------------------------------------- + +`include "qbmcu_defines.v" + + +module qbmcu_exu_alu( + //system port + input clk + ,input rst_n + ////////////////////////////////////////////////////////////// + ////////////////////////////////////////////////////////////// + ,input [`QBMCU_XLEN-1 :0] alu_i_rs1 + ,input [`QBMCU_XLEN-1 :0] alu_i_rs2 + ,input [`QBMCU_XLEN-1 :0] alu_i_imm + ,input [`QBMCU_PC_SIZE-1 :0] alu_i_pc + ,input [`QBMCU_DECINFO_ALU_WIDTH-1:0] alu_i_info + ,input alu_i_op + //The enable signal from the master control state machine + ,input alu_i_active + ////////////////////////////////////////////////////////////// + ////////////////////////////////////////////////////////////// + // The Write-Back Interface for Special (unaligned ldst and AMO instructions) + ,output [`QBMCU_XLEN-1 :0] alu_o_wbck_wdat + ,output alu_o_wbck_valid + ////////////////////////////////////////////////////////////// + ////////////////////////////////////////////////////////////// + // To share the ALU datapath + // + // The operands and info to ALU + ,output alu_req_alu_add + ,output alu_req_alu_sub + ,output alu_req_alu_xor + ,output alu_req_alu_sll + ,output alu_req_alu_srl + ,output alu_req_alu_sra + ,output alu_req_alu_or + ,output alu_req_alu_and + ,output alu_req_alu_slt + ,output alu_req_alu_sltu + ,output alu_req_alu_lui + ,output [`QBMCU_XLEN-1 :0] alu_req_alu_op1 + ,output [`QBMCU_XLEN-1 :0] alu_req_alu_op2 + + ,input [`QBMCU_XLEN-1 :0] alu_req_alu_res + ); +wire alu_i_active_r; +wire op2imm = alu_i_op & alu_i_info [`QBMCU_DECINFO_ALU_OP2IMM ]; +wire op1pc = alu_i_op & alu_i_info [`QBMCU_DECINFO_ALU_OP1PC ]; + +assign alu_req_alu_op1 = op1pc ? alu_i_pc : alu_i_rs1; +assign alu_req_alu_op2 = op2imm ? alu_i_imm : alu_i_rs2; + +wire nop = alu_i_op & alu_i_info [`QBMCU_DECINFO_ALU_NOP ] ; + + // The NOP is encoded as ADDI, so need to uncheck it +assign alu_req_alu_add = alu_i_op & alu_i_info [`QBMCU_DECINFO_ALU_ADD ] & (~nop); +assign alu_req_alu_sub = alu_i_op & alu_i_info [`QBMCU_DECINFO_ALU_SUB ]; +assign alu_req_alu_xor = alu_i_op & alu_i_info [`QBMCU_DECINFO_ALU_XOR ]; +assign alu_req_alu_sll = alu_i_op & alu_i_info [`QBMCU_DECINFO_ALU_SLL ]; +assign alu_req_alu_srl = alu_i_op & alu_i_info [`QBMCU_DECINFO_ALU_SRL ]; +assign alu_req_alu_sra = alu_i_op & alu_i_info [`QBMCU_DECINFO_ALU_SRA ]; +assign alu_req_alu_or = alu_i_op & alu_i_info [`QBMCU_DECINFO_ALU_OR ]; +assign alu_req_alu_and = alu_i_op & alu_i_info [`QBMCU_DECINFO_ALU_AND ]; +assign alu_req_alu_slt = alu_i_op & alu_i_info [`QBMCU_DECINFO_ALU_SLT ]; +assign alu_req_alu_sltu = alu_i_op & alu_i_info [`QBMCU_DECINFO_ALU_SLTU]; +assign alu_req_alu_lui = alu_i_op & alu_i_info [`QBMCU_DECINFO_ALU_LUI ]; + +//alu_i_active_r +sirv_gnrl_dffr #(1) alu_i_active_r_dffr (alu_i_active, alu_i_active_r, clk, rst_n); +//alu_o_wbck_wdat +sirv_gnrl_dfflr #(`QBMCU_XLEN) alu_o_wbck_wdat_dfflr (alu_i_active_r, alu_req_alu_res, alu_o_wbck_wdat, clk, rst_n); +//alu_o_wbck_valid +sirv_gnrl_dfflr #(1) alu_o_wbck_valid_dfflr (alu_i_active_r, alu_i_op, alu_o_wbck_valid, clk, rst_n); +endmodule +`include "qbmcu_undefines.v" \ No newline at end of file diff --git a/rtl/qubitmcu/qbmcu_exu_bjp.v b/rtl/qubitmcu/qbmcu_exu_bjp.v new file mode 100644 index 0000000..59dbdf1 --- /dev/null +++ b/rtl/qubitmcu/qbmcu_exu_bjp.v @@ -0,0 +1,134 @@ + //+FHDR-------------------------------------------------------------------------------------------------------- +// Company: +//----------------------------------------------------------------------------------------------------------------- +// File Name : qbmcu_exu_bjp.v +// Department : +// Author : PWY +// Author's Tel : +//----------------------------------------------------------------------------------------------------------------- +// Relese History +// Version Date Author Description +// 0.1 2024-03-13 PWY This module to implement the Conditional Branch Instructions, +// which is mostly share the datapath with ALU adder to resolve the comparasion +// result to save gatecount to mininum +//----------------------------------------------------------------------------------------------------------------- +// Keywords : +// +//----------------------------------------------------------------------------------------------------------------- +// Parameter +// +//----------------------------------------------------------------------------------------------------------------- +// Purpose : +// +//----------------------------------------------------------------------------------------------------------------- +// Target Device: +// Tool versions: +//----------------------------------------------------------------------------------------------------------------- +// Reuse Issues +// Reset Strategy: +// Clock Domains: +// Critical Timing: +// Asynchronous I/F: +// Synthesizable (y/n): +// Other: +//-FHDR-------------------------------------------------------------------------------------------------------- + + +`include "qbmcu_defines.v" + + +module qbmcu_exu_bjp( + //system port + input clk + ,input rst_n + ////////////////////////////////////////////////////////////// + ////////////////////////////////////////////////////////////// + // The Handshake Interface + // + ,input [`QBMCU_XLEN-1 :0] bjp_i_rs1 + ,input [`QBMCU_XLEN-1 :0] bjp_i_rs2 + ,input [`QBMCU_XLEN-1 :0] bjp_i_imm + ,input [`QBMCU_PC_SIZE-1 :0] bjp_i_pc + ,input [`QBMCU_DECINFO_BJP_WIDTH-1:0] bjp_i_info + ,input bjp_i_op + //The enable signal from the master control state machine + ,input bjp_i_active + + ////////////////////////////////////////////////////////////// + //Data sent to the write-back module + //write back interface + ,output [`QBMCU_XLEN-1 :0] bjp_o_wbck_wdat + ,output bjp_o_wbck_valid + ////////////////////////////////////////////////////////////// + //update the value of the program counter (PC) + ,output update_pc_req + ,output [`QBMCU_PC_SIZE-1 :0] update_pc_value + ////////////////////////////////////////////////////////////// + // To share the ALU datapath + // The operands and info to ALU + ,output [`QBMCU_XLEN-1 :0] bjp_req_alu_op1 + ,output [`QBMCU_XLEN-1 :0] bjp_req_alu_op2 + ,output bjp_req_alu_cmp_eq + ,output bjp_req_alu_cmp_ne + ,output bjp_req_alu_cmp_lt + ,output bjp_req_alu_cmp_gt + ,output bjp_req_alu_cmp_ltu + ,output bjp_req_alu_cmp_gtu + ,output bjp_req_alu_add + + ,input bjp_req_alu_cmp_res + ,input [`QBMCU_XLEN-1 :0] bjp_req_alu_add_res + ); + + +wire bxx = bjp_i_op & bjp_i_info [`QBMCU_DECINFO_BJP_BXX ]; +wire jump = bjp_i_op & bjp_i_info [`QBMCU_DECINFO_BJP_JUMP ]; +wire jalr = bjp_i_op & bjp_i_info [`QBMCU_DECINFO_BJP_JALR ]; + +wire wbck_link = jump; + +assign bjp_req_alu_op1 = wbck_link ? + bjp_i_pc + : bjp_i_rs1; +assign bjp_req_alu_op2 = wbck_link ? + `QBMCU_XLEN'd4 + : bjp_i_rs2; + +wire cmt_bjp = bxx | jump; + + +assign bjp_req_alu_cmp_eq = bjp_i_op & bjp_i_info [`QBMCU_DECINFO_BJP_BEQ ]; +assign bjp_req_alu_cmp_ne = bjp_i_op & bjp_i_info [`QBMCU_DECINFO_BJP_BNE ]; +assign bjp_req_alu_cmp_lt = bjp_i_op & bjp_i_info [`QBMCU_DECINFO_BJP_BLT ]; +assign bjp_req_alu_cmp_gt = bjp_i_op & bjp_i_info [`QBMCU_DECINFO_BJP_BGT ]; +assign bjp_req_alu_cmp_ltu = bjp_i_op & bjp_i_info [`QBMCU_DECINFO_BJP_BLTU ]; +assign bjp_req_alu_cmp_gtu = bjp_i_op & bjp_i_info [`QBMCU_DECINFO_BJP_BGTU ]; + +assign bjp_req_alu_add = wbck_link; + +wire cmt_rslv = jump ? 1'b1 : bjp_req_alu_cmp_res; + + +//bjp_o_wbck_wdat +sirv_gnrl_dfflr #(`QBMCU_XLEN) bjp_o_wbck_wdat_dfflr (bjp_i_active, bjp_req_alu_add_res, bjp_o_wbck_wdat, clk, rst_n); +//bjp_o_wbck_valid +sirv_gnrl_dfflr #(1) bjp_o_wbck_valid_dfflr (bjp_i_active, bjp_i_op, bjp_o_wbck_valid, clk, rst_n); + +wire [`QBMCU_PC_SIZE-1:0] pc_temp = jalr ? bjp_i_rs1 : bjp_i_pc; + +wire [`QBMCU_PC_SIZE-1:0] update_pc_value_w = (pc_temp + bjp_i_imm[`QBMCU_PC_SIZE-1:0]); +wire update_pc_req_w = cmt_bjp & cmt_rslv; + +//wire bjp_i_active_r; +//sirv_gnrl_dffr #(1)bjp_i_active_r_dffr (bjp_i_active, bjp_i_active_r, clk, rst_n); + +//update_pc_vaule +//sirv_gnrl_dfflr #(`QBMCU_PC_SIZE) update_pc_vaule_dfflr (bjp_i_active_r, update_pc_value_w, update_pc_value, clk, rst_n); +//update_pc_req +//sirv_gnrl_dfflr #(1) update_pc_req_dfflr (bjp_i_active_r, update_pc_req_w, update_pc_req, clk, rst_n); + +assign update_pc_value = update_pc_value_w; +assign update_pc_req = update_pc_req_w; +endmodule + +`include "qbmcu_undefines.v" \ No newline at end of file diff --git a/rtl/qubitmcu/qbmcu_exu_dpath.v b/rtl/qubitmcu/qbmcu_exu_dpath.v new file mode 100644 index 0000000..634e2bd --- /dev/null +++ b/rtl/qubitmcu/qbmcu_exu_dpath.v @@ -0,0 +1,365 @@ +//+FHDR-------------------------------------------------------------------------------------------------------- +// Company: +//----------------------------------------------------------------------------------------------------------------- +// File Name : qbmcu_exu_dpath.v +// Department : +// Author : PWY +// Author's Tel : +//----------------------------------------------------------------------------------------------------------------- +// Relese History +// Version Date Author Description +// 0.1 2024-03-13 PWY This module to implement the datapath of ALU +//----------------------------------------------------------------------------------------------------------------- +// Keywords : +// +//----------------------------------------------------------------------------------------------------------------- +// Parameter +// +//----------------------------------------------------------------------------------------------------------------- +// Purpose : +// +//----------------------------------------------------------------------------------------------------------------- +// Target Device: +// Tool versions: +//----------------------------------------------------------------------------------------------------------------- +// Reuse Issues +// Reset Strategy: +// Clock Domains: +// Critical Timing: +// Asynchronous I/F: +// Synthesizable (y/n): +// Other: +//-FHDR-------------------------------------------------------------------------------------------------------- + +`include "qbmcu_defines.v" + +module qbmcu_exu_dpath( + ////////////////////////////////////////////////////// + // ALU request the datapath + input alu_req_alu + ,input alu_req_alu_add + ,input alu_req_alu_sub + ,input alu_req_alu_xor + ,input alu_req_alu_sll + ,input alu_req_alu_srl + ,input alu_req_alu_sra + ,input alu_req_alu_or + ,input alu_req_alu_and + ,input alu_req_alu_slt + ,input alu_req_alu_sltu + ,input alu_req_alu_lui + ,input [`QBMCU_XLEN-1:0] alu_req_alu_op1 + ,input [`QBMCU_XLEN-1:0] alu_req_alu_op2 + ,output [`QBMCU_XLEN-1:0] alu_req_alu_res + + ////////////////////////////////////////////////////// + // BJP request the datapath + ,input bjp_req_alu + ,input [`QBMCU_XLEN-1:0] bjp_req_alu_op1 + ,input [`QBMCU_XLEN-1:0] bjp_req_alu_op2 + ,input bjp_req_alu_cmp_eq + ,input bjp_req_alu_cmp_ne + ,input bjp_req_alu_cmp_lt + ,input bjp_req_alu_cmp_gt + ,input bjp_req_alu_cmp_ltu + ,input bjp_req_alu_cmp_gtu + ,input bjp_req_alu_add + ,output bjp_req_alu_cmp_res + ,output [`QBMCU_XLEN-1:0] bjp_req_alu_add_res + ); + + + wire [`QBMCU_XLEN-1:0] mux_op1; + wire [`QBMCU_XLEN-1:0] mux_op2; + + wire [`QBMCU_XLEN-1:0] misc_op1 = mux_op1[`QBMCU_XLEN-1:0]; + wire [`QBMCU_XLEN-1:0] misc_op2 = mux_op2[`QBMCU_XLEN-1:0]; + + // Only the regular ALU use shifter + wire [`QBMCU_XLEN-1:0] shifter_op1 = alu_req_alu_op1[`QBMCU_XLEN-1:0]; + wire [`QBMCU_XLEN-1:0] shifter_op2 = alu_req_alu_op2[`QBMCU_XLEN-1:0]; + + wire op_add; + wire op_sub; + wire op_addsub = op_add | op_sub; + + wire op_or; + wire op_xor; + wire op_and; + + wire op_sll; + wire op_srl; + wire op_sra; + + wire op_slt; + wire op_sltu; + + wire op_mvop2; + + + wire op_cmp_eq ; + wire op_cmp_ne ; + wire op_cmp_lt ; + wire op_cmp_gt ; + wire op_cmp_ltu; + wire op_cmp_gtu; + + wire cmp_res; + + + ////////////////////////////////////////////////////////////// + // Impelment the Left-Shifter + // + // The Left-Shifter will be used to handle the shift op + wire [`QBMCU_XLEN-1:0] shifter_in1; + wire [5-1:0] shifter_in2; + wire [`QBMCU_XLEN-1:0] shifter_res; + + + wire op_shift = op_sra | op_sll | op_srl; + + // Make sure to use logic-gating to gateoff the + assign shifter_in1 = {`QBMCU_XLEN{op_shift}} & + // In order to save area and just use one left-shifter, we + // convert the right-shift op into left-shift operation + ( + (op_sra | op_srl) ? + { + shifter_op1[00],shifter_op1[01],shifter_op1[02],shifter_op1[03], + shifter_op1[04],shifter_op1[05],shifter_op1[06],shifter_op1[07], + shifter_op1[08],shifter_op1[09],shifter_op1[10],shifter_op1[11], + shifter_op1[12],shifter_op1[13],shifter_op1[14],shifter_op1[15], + shifter_op1[16],shifter_op1[17],shifter_op1[18],shifter_op1[19], + shifter_op1[20],shifter_op1[21],shifter_op1[22],shifter_op1[23], + shifter_op1[24],shifter_op1[25],shifter_op1[26],shifter_op1[27], + shifter_op1[28],shifter_op1[29],shifter_op1[30],shifter_op1[31] + } : shifter_op1 + ); + assign shifter_in2 = {5{op_shift}} & shifter_op2[4:0]; + + assign shifter_res = (shifter_in1 << shifter_in2); + + wire [`QBMCU_XLEN-1:0] sll_res = shifter_res; + wire [`QBMCU_XLEN-1:0] srl_res = + { + shifter_res[00],shifter_res[01],shifter_res[02],shifter_res[03], + shifter_res[04],shifter_res[05],shifter_res[06],shifter_res[07], + shifter_res[08],shifter_res[09],shifter_res[10],shifter_res[11], + shifter_res[12],shifter_res[13],shifter_res[14],shifter_res[15], + shifter_res[16],shifter_res[17],shifter_res[18],shifter_res[19], + shifter_res[20],shifter_res[21],shifter_res[22],shifter_res[23], + shifter_res[24],shifter_res[25],shifter_res[26],shifter_res[27], + shifter_res[28],shifter_res[29],shifter_res[30],shifter_res[31] + }; + + wire [`QBMCU_XLEN-1:0] eff_mask = (~(`QBMCU_XLEN'b0)) >> shifter_in2; + wire [`QBMCU_XLEN-1:0] sra_res = + (srl_res & eff_mask) | ({32{shifter_op1[31]}} & (~eff_mask)); + + + + ////////////////////////////////////////////////////////////// + // Impelment the Adder + // + // The Adder will be reused to handle the add/sub/compare op + // all other unit request ALU-adder with 32bits opereand without sign extended + wire op_unsigned = op_sltu | op_cmp_ltu | op_cmp_gtu; + wire [`QBMCU_ALU_ADDER_WIDTH-1:0] misc_adder_op1 = + {{`QBMCU_ALU_ADDER_WIDTH-`QBMCU_XLEN{(~op_unsigned) & misc_op1[`QBMCU_XLEN-1]}},misc_op1}; + wire [`QBMCU_ALU_ADDER_WIDTH-1:0] misc_adder_op2 = + {{`QBMCU_ALU_ADDER_WIDTH-`QBMCU_XLEN{(~op_unsigned) & misc_op2[`QBMCU_XLEN-1]}},misc_op2}; + + + wire [`QBMCU_ALU_ADDER_WIDTH-1:0] adder_op1 = misc_adder_op1; + wire [`QBMCU_ALU_ADDER_WIDTH-1:0] adder_op2 = misc_adder_op2; + + wire adder_cin; + wire [`QBMCU_ALU_ADDER_WIDTH-1:0] adder_in1; + wire [`QBMCU_ALU_ADDER_WIDTH-1:0] adder_in2; + wire [`QBMCU_ALU_ADDER_WIDTH-1:0] adder_res; + + wire adder_add; + wire adder_sub; + + assign adder_add = op_add; + assign adder_sub = + ( + // The original sub instruction + (op_sub) + // The compare lt or gt instruction + | (op_cmp_lt | op_cmp_gt | + op_cmp_ltu | op_cmp_gtu | + op_slt | op_sltu + )); + + wire adder_addsub = adder_add | adder_sub; + + + // Make sure to use logic-gating to gateoff the + assign adder_in1 = {`QBMCU_ALU_ADDER_WIDTH{adder_addsub}} & (adder_op1); + assign adder_in2 = {`QBMCU_ALU_ADDER_WIDTH{adder_addsub}} & (adder_sub ? (~adder_op2) : adder_op2); + assign adder_cin = adder_addsub & adder_sub; + + assign adder_res = adder_in1 + adder_in2 + adder_cin; + + + + ////////////////////////////////////////////////////////////// + // Impelment the XOR-er + // + // The XOR-er will be reused to handle the XOR and compare op + + wire [`QBMCU_XLEN-1:0] xorer_in1; + wire [`QBMCU_XLEN-1:0] xorer_in2; + + wire xorer_op = + op_xor + // The compare eq or ne instruction + | (op_cmp_eq | op_cmp_ne); + + // Make sure to use logic-gating to gateoff the + assign xorer_in1 = {`QBMCU_XLEN{xorer_op}} & misc_op1; + assign xorer_in2 = {`QBMCU_XLEN{xorer_op}} & misc_op2; + + wire [`QBMCU_XLEN-1:0] xorer_res = xorer_in1 ^ xorer_in2; + // The OR and AND is too light-weight, so no need to gate off + wire [`QBMCU_XLEN-1:0] orer_res = misc_op1 | misc_op2; + wire [`QBMCU_XLEN-1:0] ander_res = misc_op1 & misc_op2; + + + ////////////////////////////////////////////////////////////// + // Generate the CMP operation result + // It is Non-Equal if the XOR result have any bit non-zero + wire neq = (|xorer_res); + wire cmp_res_ne = (op_cmp_ne & neq); + // It is Equal if it is not Non-Equal + wire cmp_res_eq = op_cmp_eq & (~neq); + // It is Less-Than if the adder result is negative + wire cmp_res_lt = op_cmp_lt & adder_res[`QBMCU_XLEN]; + wire cmp_res_ltu = op_cmp_ltu & adder_res[`QBMCU_XLEN]; + // It is Greater-Than if the adder result is postive + wire op1_gt_op2 = (~adder_res[`QBMCU_XLEN]); + wire cmp_res_gt = op_cmp_gt & op1_gt_op2; + wire cmp_res_gtu = op_cmp_gtu & op1_gt_op2; + + assign cmp_res = cmp_res_eq + | cmp_res_ne + | cmp_res_lt + | cmp_res_gt + | cmp_res_ltu + | cmp_res_gtu; + + ////////////////////////////////////////////////////////////// + // Generate the mvop2 result + // Just directly use op2 since the op2 will be the immediate + wire [`QBMCU_XLEN-1:0] mvop2_res = misc_op2; + + ////////////////////////////////////////////////////////////// + // Generate the SLT and SLTU result + // Just directly use op2 since the op2 will be the immediate + wire op_slttu = (op_slt | op_sltu); + // The SLT and SLTU is reusing the adder to do the comparasion + // It is Less-Than if the adder result is negative + wire slttu_cmp_lt = op_slttu & adder_res[`QBMCU_XLEN]; + wire [`QBMCU_XLEN-1:0] slttu_res = + slttu_cmp_lt ? + `QBMCU_XLEN'b1 : `QBMCU_XLEN'b0; + + ////////////////////////////////////////////////////////////// + // Generate the final result + wire [`QBMCU_XLEN-1:0] alu_dpath_res = + ({`QBMCU_XLEN{op_or }} & orer_res ) + | ({`QBMCU_XLEN{op_and }} & ander_res) + | ({`QBMCU_XLEN{op_xor }} & xorer_res) + | ({`QBMCU_XLEN{op_addsub }} & adder_res[`QBMCU_XLEN-1:0]) + | ({`QBMCU_XLEN{op_srl }} & srl_res) + | ({`QBMCU_XLEN{op_sll }} & sll_res) + | ({`QBMCU_XLEN{op_sra }} & sra_res) + | ({`QBMCU_XLEN{op_mvop2 }} & mvop2_res) + | ({`QBMCU_XLEN{op_slttu }} & slttu_res) + ; + + + ///////////////////////////////////////////////////////////////////// + ///////////////////////////////////////////////////////////////////// + ///////////////////////////////////////////////////////////////////// + // The ALU-Datapath Mux for the requestors + + localparam DPATH_MUX_WIDTH = ((`QBMCU_XLEN*2)+17); + + assign { + mux_op1 + ,mux_op2 + ,op_add + ,op_sub + ,op_or + ,op_xor + ,op_and + ,op_sll + ,op_srl + ,op_sra + ,op_slt + ,op_sltu + ,op_mvop2 + ,op_cmp_eq + ,op_cmp_ne + ,op_cmp_lt + ,op_cmp_gt + ,op_cmp_ltu + ,op_cmp_gtu + } + = + ({DPATH_MUX_WIDTH{alu_req_alu}} & { + alu_req_alu_op1 + ,alu_req_alu_op2 + ,alu_req_alu_add + ,alu_req_alu_sub + ,alu_req_alu_or + ,alu_req_alu_xor + ,alu_req_alu_and + ,alu_req_alu_sll + ,alu_req_alu_srl + ,alu_req_alu_sra + ,alu_req_alu_slt + ,alu_req_alu_sltu + ,alu_req_alu_lui// LUI just move-Op2 operation + ,1'b0 + ,1'b0 + ,1'b0 + ,1'b0 + ,1'b0 + ,1'b0 + }) + | ({DPATH_MUX_WIDTH{bjp_req_alu}} & { + bjp_req_alu_op1 + ,bjp_req_alu_op2 + ,bjp_req_alu_add + ,1'b0 + ,1'b0 + ,1'b0 + ,1'b0 + ,1'b0 + ,1'b0 + ,1'b0 + ,1'b0 + ,1'b0 + ,1'b0 + ,bjp_req_alu_cmp_eq + ,bjp_req_alu_cmp_ne + ,bjp_req_alu_cmp_lt + ,bjp_req_alu_cmp_gt + ,bjp_req_alu_cmp_ltu + ,bjp_req_alu_cmp_gtu + + }) + ; + + assign alu_req_alu_res = alu_dpath_res[`QBMCU_XLEN-1:0]; + assign bjp_req_alu_add_res = alu_dpath_res[`QBMCU_XLEN-1:0]; + assign bjp_req_alu_cmp_res = cmp_res; + + +endmodule + +`include "qbmcu_undefines.v" + diff --git a/rtl/qubitmcu/qbmcu_exu_ext.v b/rtl/qubitmcu/qbmcu_exu_ext.v new file mode 100644 index 0000000..ce4acb2 --- /dev/null +++ b/rtl/qubitmcu/qbmcu_exu_ext.v @@ -0,0 +1,122 @@ +//+FHDR-------------------------------------------------------------------------------------------------------- +// Company: +//----------------------------------------------------------------------------------------------------------------- +// File Name : qbmcu_exu_ext.v +// Department : +// Author : PWY +// Author's Tel : +//----------------------------------------------------------------------------------------------------------------- +// Relese History +// Version Date Author Description +// 0.1 2024-03-13 PWY This module to implement the regular EXT instructions +//----------------------------------------------------------------------------------------------------------------- +// Keywords : +// +//----------------------------------------------------------------------------------------------------------------- +// Parameter +// +//----------------------------------------------------------------------------------------------------------------- +// Purpose : +// +//----------------------------------------------------------------------------------------------------------------- +// Target Device: +// Tool versions: +//----------------------------------------------------------------------------------------------------------------- +// Reuse Issues +// Reset Strategy: +// Clock Domains: +// Critical Timing: +// Asynchronous I/F: +// Synthesizable (y/n): +// Other: +//-FHDR-------------------------------------------------------------------------------------------------------- + +`include "qbmcu_defines.v" + + +module qbmcu_exu_ext( + //system port + input clk + ,input rst_n + ////////////////////////////////////////////////////////////// + ////////////////////////////////////////////////////////////// + ,input [`QBMCU_XLEN-1 :0] ext_i_rs1 + ,input [`QBMCU_XLEN-1 :0] ext_i_imm + ,input [`QBMCU_DECINFO_EXT_WIDTH-1:0] ext_i_info + ,input ext_i_op + //The enable signal from the master control state machine + ,input ext_i_active + + ////////////////////////////////////////////////////////////// + ////////////////////////////////////////////////////////////// + // + // The operands and info to peripheral + ,output ext_o_wait_valid + ,output ext_o_wait + ,output [`QBMCU_XLEN-1 :0] ext_o_wait_cnt + ,output ext_o_send + ,output ext_o_sendc + ,output [`QBMCU_XLEN-1 :0] ext_o_codeword + ,output ext_o_exit + ,output ext_o_intr + ,output [`QBMCU_XLEN-1 :0] ext_o_wbck_wdat + ,output ext_o_wbck_valid + ); + + +wire [`QBMCU_XLEN-1:0] ext_req_alu_op1 = ext_i_rs1; +wire [`QBMCU_XLEN-1:0] ext_req_alu_op2 = ext_i_imm; + +wire [`QBMCU_XLEN-1:0] ext_req_alu_res = ext_req_alu_op1 + ext_req_alu_op2; +wire alu_req_alu_wait = ext_i_op & ext_i_info [`QBMCU_DECINFO_EXT_WAIT ]; +wire alu_req_alu_send = ext_i_op & ext_i_info [`QBMCU_DECINFO_EXT_SEND ]; +wire alu_req_alu_sendc = ext_i_op & ext_i_info [`QBMCU_DECINFO_EXT_SENDC ]; +wire alu_req_alu_exit = ext_i_op & ext_i_info [`QBMCU_DECINFO_EXT_EXIT ]; +wire alu_req_alu_exiti = ext_i_op & ext_i_info [`QBMCU_DECINFO_EXT_EXITI ]; + +//ext_o_codeword +sirv_gnrl_dfflr #(`QBMCU_XLEN) ext_o_codeword_dfflr (ext_i_active, ext_req_alu_res, ext_o_codeword, clk, rst_n); + +//ext_o_wait_cnt +//sirv_gnrl_dfflr #(`QBMCU_XLEN) ext_o_wait_cnt_dfflr (ext_i_active, ext_req_alu_res, ext_o_wait_cnt, clk, rst_n); +assign ext_o_wait_cnt = ext_req_alu_res; +//ext_o_wait +wire ext_wait = ext_i_active & alu_req_alu_wait; +//sirv_gnrl_dffr #(1) ext_o_wait_dffr (ext_wait, ext_o_wait, clk, rst_n); +assign ext_o_wait = ext_wait; + +wire ext_o_wait_valid_en = ext_wait | ext_i_active; +wire ext_o_wait_valid_v = ext_wait ? 1'b1 : + ext_i_active ? 1'b0 : + 1'b0 ; +sirv_gnrl_dfflr #(1) ext_o_wait_valid_dfflr (ext_o_wait_valid_en, ext_o_wait_valid_v, ext_o_wait_valid, clk, rst_n); +//ext_o_send +wire ext_send = ext_i_active & alu_req_alu_send; +sirv_gnrl_dffr #(1) ext_o_send_dffr (ext_send, ext_o_send, clk, rst_n); + +//ext_o_sendc +wire ext_sendc = ext_i_active & alu_req_alu_sendc; +sirv_gnrl_dffr #(1) ext_o_sendc_dffr (ext_sendc, ext_o_sendc, clk, rst_n); + +//ext_o_exit +assign ext_o_exit = alu_req_alu_exit | alu_req_alu_exiti; +//sirv_gnrl_dfflr #(1) ext_o_exit_dfflr (ext_i_active, ext_exit, ext_o_exit, clk, rst_n); + +//ext_o_intr +wire ext_intr = ext_i_active & alu_req_alu_exiti; +sirv_gnrl_dffr #(1) ext_o_intr_dffr (ext_intr, ext_o_intr, clk, rst_n); + +///////////////////////////////////////////////////////////////////////////////////////////// +// +///////////////////////////////////////////////////////////////////////////////////////////// +//ext_i_active_r +wire ext_i_active_r; +sirv_gnrl_dffr #(1) ext_i_active_r_dffr (ext_i_active, ext_i_active_r, clk, rst_n); +//ext_o_wbck_wdat +sirv_gnrl_dfflr #(`QBMCU_XLEN) ext_o_wbck_wdat_dfflr (ext_i_active_r, ext_req_alu_res, ext_o_wbck_wdat, clk, rst_n); +//ext_o_wbck_valid +sirv_gnrl_dfflr #(1) ext_o_wbck_valid_dfflr (ext_i_active_r, ext_i_op, ext_o_wbck_valid, clk, rst_n); + + +endmodule +`include "qbmcu_undefines.v" \ No newline at end of file diff --git a/rtl/qubitmcu/qbmcu_exu_lsuagu.v b/rtl/qubitmcu/qbmcu_exu_lsuagu.v new file mode 100644 index 0000000..af97375 --- /dev/null +++ b/rtl/qubitmcu/qbmcu_exu_lsuagu.v @@ -0,0 +1,175 @@ +//+FHDR-------------------------------------------------------------------------------------------------------- +// Company: +//----------------------------------------------------------------------------------------------------------------- +// File Name : qbmcu_exu_lsuagu.v +// Department : +// Author : PWY +// Author's Tel : +//----------------------------------------------------------------------------------------------------------------- +// Relese History +// Version Date Author Description +// 0.1 2024-03-13 PWY This module to implement the AGU (address generation unit +// for load/store instructions) +//----------------------------------------------------------------------------------------------------------------- +// Keywords : +// +//----------------------------------------------------------------------------------------------------------------- +// Parameter +// +//----------------------------------------------------------------------------------------------------------------- +// Purpose : +// +//----------------------------------------------------------------------------------------------------------------- +// Target Device: +// Tool versions: +//----------------------------------------------------------------------------------------------------------------- +// Reuse Issues +// Reset Strategy: +// Clock Domains: +// Critical Timing: +// Asynchronous I/F: +// Synthesizable (y/n): +// Other: +//-FHDR-------------------------------------------------------------------------------------------------------- + +`include "qbmcu_defines.v" + +module qbmcu_exu_lsuagu( + //system port + input clk + ,input rst_n + ////////////////////////////////////////////////////////////// + //The operands and instruction information from the decoding module + ,input [`QBMCU_XLEN-1 :0] agu_i_rs1 + ,input [`QBMCU_XLEN-1 :0] agu_i_rs2 + ,input [`QBMCU_XLEN-1 :0] agu_i_imm + ,input [`QBMCU_DECINFO_AGU_WIDTH-1:0] agu_i_info + ,input agu_i_op + //The enable signal from the master control state machine + ,input agu_i_active + ////////////////////////////////////////////////////////////// + //Address, data, and enable signals connected to the memory space + ,output [`QBMCU_ADDR_SIZE-1 :0] agu_o_addr + ,output [`QBMCU_XLEN-1 :0] agu_o_wdata + ,output agu_o_wren // Write enable + ,output agu_o_rden // Read enable + ,output [`QBMCU_XLEN/8-1 :0] agu_o_wmask + ,input [`QBMCU_XLEN-1 :0] agu_i_rdata + ////////////////////////////////////////////////////////////// + //Data sent to the write-back module + //write back interface + ,output [`QBMCU_XLEN-1 :0] agu_o_wbck_wdat + ,output agu_o_wbck_valid + //Misaligned memory address + ,output agu_o_addr_unalgn + ); + +///////////////////////////////////////////////////////////////////////////////// +//Memory Address Generation +///////////////////////////////////////////////////////////////////////////////// + +//Generate Operand 1 +wire [`QBMCU_XLEN-1:0] agu_addr_gen_op1 = agu_i_rs1; + +//The Operand 2 of the memory access instructions are immediate values +wire [`QBMCU_XLEN-1:0] agu_addr_gen_op2 = agu_i_imm; + +wire [`QBMCU_ADDR_SIZE-1:0] agu_addr = agu_addr_gen_op1 + agu_addr_gen_op2; + +//Fetch memory access instruction +//Load operation +wire agu_i_load = agu_i_op & agu_i_info [`QBMCU_DECINFO_AGU_LOAD ] ; +//Store operation +wire agu_i_store = agu_i_op & agu_i_info [`QBMCU_DECINFO_AGU_STORE ] ; + +//Fetching memory size +wire [1:0] agu_i_size = {2{agu_i_op}} & agu_i_info [`QBMCU_DECINFO_AGU_SIZE ]; +//sign extraction +wire agu_i_usign = agu_i_op & agu_i_info [`QBMCU_DECINFO_AGU_USIGN ]; + +//Generate size information +wire agu_i_size_b = (agu_i_size == 2'b00); +wire agu_i_size_hw = (agu_i_size == 2'b01); +wire agu_i_size_w = (agu_i_size == 2'b10); + +//Generation of misaligned memory access signal +wire agu_i_addr_unalgn = + (agu_i_size_hw & agu_addr[0] ) + | (agu_i_size_w & (|agu_addr[1:0])); + +wire agu_addr_unalgn = agu_i_addr_unalgn; + +//Abnormal memory access operation +wire agu_i_unalgnld = (agu_addr_unalgn & agu_i_load); +wire agu_i_unalgnst = (agu_addr_unalgn & agu_i_store) ; +wire agu_i_unalgnldst = (agu_i_unalgnld | agu_i_unalgnst); + +//Normal memory access operation +wire agu_i_algnld = (~agu_addr_unalgn) & agu_i_load; +wire agu_i_algnst = (~agu_addr_unalgn) & agu_i_store; +wire agu_i_algnldst = (agu_i_algnld | agu_i_algnst); + +///////////////////////////////////////////////////////////////////////////////// +//Read/Write Command, and Data Generation +///////////////////////////////////////////////////////////////////////////////// +//write enable, active hight +wire agu_wren = (agu_i_algnldst & agu_i_store) & agu_i_active; +//read enable, active hight +wire agu_rden = (agu_i_algnldst & agu_i_load ) & agu_i_active; +//write data +wire [`QBMCU_XLEN-1:0] algnst_wdata = + ({`QBMCU_XLEN{agu_i_size_b }} & {4{agu_i_rs2[ 7:0]}}) + | ({`QBMCU_XLEN{agu_i_size_hw}} & {2{agu_i_rs2[15:0]}}) + | ({`QBMCU_XLEN{agu_i_size_w }} & {1{agu_i_rs2[31:0]}}); + +//write mask +wire [`QBMCU_XLEN/8-1:0] algnst_wmask = + ({`QBMCU_XLEN/8{agu_i_size_b }} & (4'b0001 << agu_addr[1:0])) + | ({`QBMCU_XLEN/8{agu_i_size_hw}} & (4'b0011 << {agu_addr[1],1'b0})) + | ({`QBMCU_XLEN/8{agu_i_size_w }} & (4'b1111)); + +///////////////////////////////////////////////////////////////////////////////// +// Write-Back Data Generation +///////////////////////////////////////////////////////////////////////////////// +wire agu_lbu = agu_i_size_b & agu_i_usign; +wire agu_lb = agu_i_size_b & ~agu_i_usign; +wire agu_lhu = agu_i_size_hw & agu_i_usign; +wire agu_lh = agu_i_size_hw & ~agu_i_usign; +wire agu_lw = agu_i_size_w; + +//Write-Back Data +wire [`QBMCU_XLEN-1:0] agu_wbck_wdat = + ( ({`QBMCU_XLEN{agu_lbu}} & {{24{ 1'b0}} , agu_i_rdata[8*(agu_addr[1:0]+1)-1-:8]}) + | ({`QBMCU_XLEN{agu_lb }} & {{24{agu_i_rdata[8*(agu_addr[1:0]+1)-1]}}, agu_i_rdata[8*(agu_addr[1:0]+1)-1-:8]}) + | ({`QBMCU_XLEN{agu_lhu}} & {{16{ 1'b0}} , agu_i_rdata[16*(agu_addr[1]+1)-1-:16]}) + | ({`QBMCU_XLEN{agu_lh }} & {{16{agu_i_rdata[16*(agu_addr[1]+1)-1]}} , agu_i_rdata[16*(agu_addr[1]+1)-1-:16]}) + | ({`QBMCU_XLEN{agu_lw }} & agu_i_rdata[31:0])); + +///////////////////////////////////////////////////////////////////////////////// +// Output +///////////////////////////////////////////////////////////////////////////////// +//agu_o_wren +sirv_gnrl_dffr #(1) agu_o_wren_dffr (agu_wren, agu_o_wren, clk, rst_n); +//agu_o_wdata +sirv_gnrl_dfflr #(`QBMCU_XLEN) agu_o_wdata_dfflr (agu_i_active, algnst_wdata, agu_o_wdata, clk, rst_n); +//agu_o_wmask +sirv_gnrl_dfflr #(`QBMCU_XLEN/8) agu_o_wmask_dfflr (agu_i_active, algnst_wmask, agu_o_wmask, clk, rst_n); +//agu_o_addr +sirv_gnrl_dfflr #(`QBMCU_ADDR_SIZE) agu_o_addr_dfflr (agu_i_active, agu_addr, agu_o_addr, clk, rst_n); + +//agu_o_rden +sirv_gnrl_dffr #(1) agu_o_rden_dffr (agu_rden, agu_o_rden, clk, rst_n); + +//agu_o_wbck_wdat +//sirv_gnrl_dffr #(`QBMCU_XLEN) agu_o_wbck_wdat_dffr (agu_wbck_wdat, agu_o_wbck_wdat, clk, rst_n); +assign agu_o_wbck_wdat = agu_wbck_wdat; +//agu_o_wbck_valid +sirv_gnrl_dfflr #(1) agu_o_wbck_valid_dfflr (agu_i_active, agu_i_op, agu_o_wbck_valid, clk, rst_n); + +//agu_o_addr_unalgn +sirv_gnrl_dfflr #(1) agu_o_addr_unalgn_dfflr (agu_i_active, agu_i_unalgnldst, agu_o_addr_unalgn, clk, rst_n); + +endmodule + +`include "qbmcu_undefines.v" + diff --git a/rtl/qubitmcu/qbmcu_fsm.v b/rtl/qubitmcu/qbmcu_fsm.v new file mode 100644 index 0000000..0671785 --- /dev/null +++ b/rtl/qubitmcu/qbmcu_fsm.v @@ -0,0 +1,113 @@ +//+FHDR-------------------------------------------------------------------------------------------------------- +// Company: +//----------------------------------------------------------------------------------------------------------------- +// File Name : qbmcu_fsm.v +// Department : +// Author : PWY +// Author's Tel : +//----------------------------------------------------------------------------------------------------------------- +// Relese History +// Version Date Author Description +// 0.1 2024-03-13 PWY The ifetch module to generate next PC and bus request +//----------------------------------------------------------------------------------------------------------------- +// Keywords : +// +//----------------------------------------------------------------------------------------------------------------- +// Parameter +// +//----------------------------------------------------------------------------------------------------------------- +// Purpose : +// +//----------------------------------------------------------------------------------------------------------------- +// Target Device: +// Tool versions: +//----------------------------------------------------------------------------------------------------------------- +// Reuse Issues +// Reset Strategy: +// Clock Domains: +// Critical Timing: +// Asynchronous I/F: +// Synthesizable (y/n): +// Other: +//-FHDR-------------------------------------------------------------------------------------------------------- + +`include "qbmcu_defines.v" + +module qbmcu_fsm ( + input clk + ,input rst_n + ,input start + ,input exit + ,input ext_wait + ,input qbmcu_timer_done + ,input dec_ilegl + ,input agu_addr_unalgn + ,output ifupc_rst + ,output ifu_active + ,output wb_active + ,output dec_active + ,output exu_active + ,output [2:0] qbmcu_fsm_st +); + +localparam IDLE = 3'b000, + IFUWB = 3'b001, + DEC = 3'b010, + EXU = 3'b011, + WAIT = 3'b100; + +wire [2:0] state_c; +wire [2:0] state_n; +wire ilde2ifuwb; +wire ifuwb2dec; +wire dec2exu; +wire exu2ifuwb; +wire exu2idle; +wire exu2wait; +wire wait2ifuwb; + +//The first section of the state machine +//state_c +sirv_gnrl_dffr #(3) state_c_dffr (state_n, state_c, clk, rst_n); + +////////////////////////////////////////////////////////////// +//fsm +////////////////////////////////////////////////////////////// + +//state_n +assign state_n = //(rst_n == 1'b0) ? IDLE : + ((state_c == IDLE ) && ilde2ifuwb) ? IFUWB : + ((state_c == IFUWB) && ifuwb2dec ) ? DEC : + ((state_c == DEC ) && dec2exu ) ? EXU : + ((state_c == EXU ) && exu2idle ) ? IDLE : + ((state_c == EXU ) && exu2ifuwb ) ? IFUWB : + ((state_c == EXU ) && exu2wait ) ? WAIT : + ((state_c == WAIT ) && wait2ifuwb) ? IFUWB : + state_c ; + +//Generating jump conditions for state machines +assign ilde2ifuwb = (state_c == IDLE ) && start; +assign ifuwb2dec = (state_c == IFUWB) ; +assign dec2exu = (state_c == DEC ) ; +assign exu2ifuwb = (state_c == EXU ) && !ext_wait && !(exit | dec_ilegl | agu_addr_unalgn); +assign exu2wait = (state_c == EXU ) && ext_wait && !(exit | dec_ilegl | agu_addr_unalgn); +assign exu2idle = (state_c == EXU ) && (exit | dec_ilegl | agu_addr_unalgn); +assign wait2ifuwb = (state_c == WAIT ) && qbmcu_timer_done ; + +//Output signal generation +//ifupc_rst +sirv_gnrl_dffr #(1) ifupc_rst_dffr (exu2idle, ifupc_rst, clk, rst_n); +//ifu_active +sirv_gnrl_dffr #(1) ifu_active_dffr (ilde2ifuwb | exu2ifuwb | wait2ifuwb, ifu_active, clk, rst_n); +//wb_active +sirv_gnrl_dffr #(1) wb_active_dffr (exu2ifuwb | wait2ifuwb, wb_active, clk, rst_n); +//dec_active +sirv_gnrl_dffr #(1) dec_active_dffr (ifuwb2dec, dec_active, clk, rst_n); +//exu_active +sirv_gnrl_dffr #(1) exu_active_dffr (dec2exu, exu_active, clk, rst_n); +//qbmcu_fsm_st +sirv_gnrl_dffr #(3) qbmcu_fsm_st_dffr (state_c, qbmcu_fsm_st, clk, rst_n); + + +endmodule +`include "qbmcu_undefines.v" \ No newline at end of file diff --git a/rtl/qubitmcu/qbmcu_ifu.v b/rtl/qubitmcu/qbmcu_ifu.v new file mode 100644 index 0000000..41b9096 --- /dev/null +++ b/rtl/qubitmcu/qbmcu_ifu.v @@ -0,0 +1,119 @@ +//+FHDR-------------------------------------------------------------------------------------------------------- +// Company: +//----------------------------------------------------------------------------------------------------------------- +// File Name : qbmcu_ifu.v +// Department : +// Author : PWY +// Author's Tel : +//----------------------------------------------------------------------------------------------------------------- +// Relese History +// Version Date Author Description +// 0.1 2024-03-13 PWY The ifetch module to generate next PC and bus request +//----------------------------------------------------------------------------------------------------------------- +// Keywords : +// +//----------------------------------------------------------------------------------------------------------------- +// Parameter +// +//----------------------------------------------------------------------------------------------------------------- +// Purpose : +// +//----------------------------------------------------------------------------------------------------------------- +// Target Device: +// Tool versions: +//----------------------------------------------------------------------------------------------------------------- +// Reuse Issues +// Reset Strategy: +// Clock Domains: +// Critical Timing: +// Asynchronous I/F: +// Synthesizable (y/n): +// Other: +//-FHDR-------------------------------------------------------------------------------------------------------- + + +`include "qbmcu_defines.v" + +module qbmcu_ifu( + input clk // System Clock + ,input rst_n // System reset,active low + ,input ifu_active // IFU module Active from MCU FSM + ,input exu_active // IFU module Active from MCU FSM + ,input [`QBMCU_PC_SIZE-1 :0] pc_rtvec // Initial PC + ,output [`QBMCU_PC_SIZE-1 :0] ifu_req_pc // Fetch PC + ,output ifu_req // Fetch req + + ,input [`QBMCU_INSTR_SIZE-1:0] ifu_rsp_instr // Response instruction + // The IR stage to DEC interface + ,output [`QBMCU_INSTR_SIZE-1:0] ifu_o_ir // The instruction register + ,output [`QBMCU_PC_SIZE-1 :0] ifu_o_pc // The PC register along with + ,input ifupc_rst + ,input update_pc_req + ,input [`QBMCU_PC_SIZE-1 :0] update_pc_value + ); + + +wire ifu_req_w; +wire [`QBMCU_PC_SIZE-1 :0] pc_r; +//wire pc_ena; +//wire [`QBMCU_INSTR_SIZE-1 :0] ifu_ir_r;// The instruction register +//wire [`QBMCU_PC_SIZE-1 :0] ifu_pc_r;// The PC register + +wire [`QBMCU_PC_SIZE-1:0] pc_nxt_pre; +wire [`QBMCU_PC_SIZE-1:0] pc_nxt; +//ifu_req +assign ifu_req_w = ifu_active; + + + +wire [`QBMCU_PC_SIZE-1:0] pc_add_op1 = + (rst_n == 1'b0 | ifupc_rst) ? pc_rtvec : + pc_r; + +wire [`QBMCU_PC_SIZE-1:0] pc_add_op2 = + (rst_n == 1'b0 | ifupc_rst) ? `QBMCU_PC_SIZE'b0 : + 32'h4 ; + +assign pc_nxt_pre = pc_add_op1 + pc_add_op2; +//pc_nxt +assign pc_nxt = update_pc_req ? {update_pc_value[`QBMCU_PC_SIZE-1:1],1'b0} : + {pc_nxt_pre[`QBMCU_PC_SIZE-1:1] ,1'b0}; + + + +// The PC will need to be updated when MCU's FSM is IFU status +//sirv_gnrl_dffr #(1) pc_ena_dffr (ifu_active, pc_ena, clk, rst_n); +//pc_r +sirv_gnrl_dfflr #(`QBMCU_PC_SIZE) pc_dfflr (exu_active, pc_nxt, pc_r, clk, rst_n & ~ifupc_rst); +/* +always @(posedge clk or negedge rst_n) begin + if(rst_n == 1'b0) begin + pc_r <= `QBMCU_PC_SIZE'h0; + end + else if(ifupc_rst) begin + pc_r <= `QBMCU_PC_SIZE'h0; + end + else if(exu_active) begin + pc_r <= pc_nxt; + end +end +*/ +// IFU-IR loaded with the returned instruction from the IFetch RSP channel +wire [`QBMCU_INSTR_SIZE-1:0] ifu_ir_nxt = ifu_rsp_instr; +//ifu_ir_r +//sirv_gnrl_dfflr #(`QBMCU_INSTR_SIZE) ifu_ir_dfflr (ifu_active, ifu_ir_nxt, ifu_ir_r, clk, rst_n); + +//ifu_pc_r +//sirv_gnrl_dfflr #(`QBMCU_PC_SIZE) ifu_pc_dfflr (ifu_active, pc_r, ifu_pc_r, clk, rst_n); + +//ifu_req_pc +assign ifu_req_pc = pc_r; + +assign ifu_req = ifu_req_w; +//assign ifu_req = pc_ena; + +assign ifu_o_ir = ifu_ir_nxt; +assign ifu_o_pc = pc_r; + +endmodule +`include "qbmcu_undefines.v" \ No newline at end of file diff --git a/rtl/qubitmcu/qbmcu_regfile.v b/rtl/qubitmcu/qbmcu_regfile.v new file mode 100644 index 0000000..cf5bb66 --- /dev/null +++ b/rtl/qubitmcu/qbmcu_regfile.v @@ -0,0 +1,75 @@ +//+FHDR-------------------------------------------------------------------------------------------------------- +// Company: +//----------------------------------------------------------------------------------------------------------------- +// File Name : qbmcu_regfile.v +// Department : +// Author : PWY +// Author's Tel : +//----------------------------------------------------------------------------------------------------------------- +// Relese History +// Version Date Author Description +// 0.1 2024-03-13 PWY The Regfile module to implement the core's general purpose registers file +//----------------------------------------------------------------------------------------------------------------- +// Keywords : +// +//----------------------------------------------------------------------------------------------------------------- +// Parameter +// +//----------------------------------------------------------------------------------------------------------------- +// Purpose : +// +//----------------------------------------------------------------------------------------------------------------- +// Target Device: +// Tool versions: +//----------------------------------------------------------------------------------------------------------------- +// Reuse Issues +// Reset Strategy: +// Clock Domains: +// Critical Timing: +// Asynchronous I/F: +// Synthesizable (y/n): +// Other: +//-FHDR-------------------------------------------------------------------------------------------------------- + +`include "qbmcu_defines.v" + +module qbmcu_regfile( + input clk + ,input rst_n + ,input [`QBMCU_RFIDX_WIDTH-1:0] read_src1_idx + ,input [`QBMCU_RFIDX_WIDTH-1:0] read_src2_idx + ,output [`QBMCU_XLEN-1 :0] read_src1_dat + ,output [`QBMCU_XLEN-1 :0] read_src2_dat + + ,input wbck_dest_wen + ,input [`QBMCU_RFIDX_WIDTH-1:0] wbck_dest_idx + ,input [`QBMCU_XLEN-1 :0] wbck_dest_dat + ); + +wire [`QBMCU_XLEN-1 :0] rf_r [`QBMCU_RFREG_NUM-1:0]; +wire [`QBMCU_RFREG_NUM-1:0] rf_wen; + +genvar i; +generate //{ + for (i=0; i<`QBMCU_RFREG_NUM; i=i+1) begin:regfile//{ + + if(i==0) begin: rf0 + // x0 cannot be wrote since it is constant-zeros + assign rf_wen[i] = 1'b0; + assign rf_r[i] = `QBMCU_XLEN'b0; + end + else begin: rfno0 + assign rf_wen[i] = wbck_dest_wen & (wbck_dest_idx == i) ; + sirv_gnrl_dfflr #(`QBMCU_XLEN) rf_dfflr (rf_wen[i], wbck_dest_dat, rf_r[i], clk, rst_n); + end + + end//} +endgenerate//} + +assign read_src1_dat = rf_r[read_src1_idx]; +assign read_src2_dat = rf_r[read_src2_idx]; + + +endmodule + +`include "qbmcu_undefines.v" \ No newline at end of file diff --git a/rtl/qubitmcu/qbmcu_undefines.v b/rtl/qubitmcu/qbmcu_undefines.v new file mode 100644 index 0000000..2650f70 --- /dev/null +++ b/rtl/qubitmcu/qbmcu_undefines.v @@ -0,0 +1,219 @@ + //+FHDR-------------------------------------------------------------------------------------------------------- +// Company: +//----------------------------------------------------------------------------------------------------------------- +// File Name : qbmcu.v +// Department : +// Author : PWY +// Author's Tel : +//----------------------------------------------------------------------------------------------------------------- +// Relese History +// Version Date Author Description +// 0.1 2024-03-13 PWY The files to include all the macro undefs +//----------------------------------------------------------------------------------------------------------------- +// Keywords : +// +//----------------------------------------------------------------------------------------------------------------- +// Parameter +// +//----------------------------------------------------------------------------------------------------------------- +// Purpose : +// +//----------------------------------------------------------------------------------------------------------------- +// Target Device: +// Tool versions: +//----------------------------------------------------------------------------------------------------------------- +// Reuse Issues +// Reset Strategy: +// Clock Domains: +// Critical Timing: +// Asynchronous I/F: +// Synthesizable (y/n): +// Other: +//-FHDR-------------------------------------------------------------------------------------------------------- + + + +///////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////// +/////// ISA relevant macro +// +//system address width +`undef QBMCU_ADDR_SIZE + +//PC width +`undef QBMCU_PC_SIZE + +//system data width +`undef QBMCU_XLEN +//system instruction width +`undef QBMCU_INSTR_SIZE + +//register array index bit width +`undef QBMCU_RFIDX_WIDTH +//number of register arrays +`undef QBMCU_RFREG_NUM + +//base address of instruction memory +//initial value of the program counter (PC) -> 0x0000_0000 +`undef QBMCU_DTCM_ADDR_BASE +//base address of data memory +`undef QBMCU_ITCM_ADDR_BASE + +//data memory address width +`undef QBMCU_DTCM_ADDR_SIZE + +//instruction memory address width +`undef QBMCU_ITCM_ADDR_SIZE + +//BUS memory address width +`undef QBMCU_BUS_ADDR_SIZE + +///////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////// +/////// ALU relevant macro +// + +`undef QBMCU_ALU_ADDER_WIDTH + + +///////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////// +/////// Decode relevant macro +// +`undef QBMCU_DECINFO_GRP_WIDTH +`undef QBMCU_DECINFO_GRP_ALU +`undef QBMCU_DECINFO_GRP_AGU +`undef QBMCU_DECINFO_GRP_BJP +`undef QBMCU_DECINFO_GRP_EXT + + +`undef QBMCU_DECINFO_GRP_LSB +`undef QBMCU_DECINFO_GRP_MSB +`undef QBMCU_DECINFO_GRP +`undef QBMCU_DECINFO_RV32_LSB +`undef QBMCU_DECINFO_RV32_MSB +`undef QBMCU_DECINFO_RV32 + +`undef QBMCU_DECINFO_SUBDECINFO_LSB + +// ALU group +`undef QBMCU_DECINFO_ALU_ADD_LSB +`undef QBMCU_DECINFO_ALU_ADD_MSB +`undef QBMCU_DECINFO_ALU_ADD +`undef QBMCU_DECINFO_ALU_SUB_LSB +`undef QBMCU_DECINFO_ALU_SUB_MSB +`undef QBMCU_DECINFO_ALU_SUB +`undef QBMCU_DECINFO_ALU_XOR_LSB +`undef QBMCU_DECINFO_ALU_XOR_MSB +`undef QBMCU_DECINFO_ALU_XOR +`undef QBMCU_DECINFO_ALU_SLL_LSB +`undef QBMCU_DECINFO_ALU_SLL_MSB +`undef QBMCU_DECINFO_ALU_SLL +`undef QBMCU_DECINFO_ALU_SRL_LSB +`undef QBMCU_DECINFO_ALU_SRL_MSB +`undef QBMCU_DECINFO_ALU_SRL +`undef QBMCU_DECINFO_ALU_SRA_LSB +`undef QBMCU_DECINFO_ALU_SRA_MSB +`undef QBMCU_DECINFO_ALU_SRA +`undef QBMCU_DECINFO_ALU_OR_LSB +`undef QBMCU_DECINFO_ALU_OR_MSB +`undef QBMCU_DECINFO_ALU_OR +`undef QBMCU_DECINFO_ALU_AND_LSB +`undef QBMCU_DECINFO_ALU_AND_MSB +`undef QBMCU_DECINFO_ALU_AND +`undef QBMCU_DECINFO_ALU_SLT_LSB +`undef QBMCU_DECINFO_ALU_SLT_MSB +`undef QBMCU_DECINFO_ALU_SLT +`undef QBMCU_DECINFO_ALU_SLTU_LSB +`undef QBMCU_DECINFO_ALU_SLTU_MSB +`undef QBMCU_DECINFO_ALU_SLTU +`undef QBMCU_DECINFO_ALU_LUI_LSB +`undef QBMCU_DECINFO_ALU_LUI_MSB +`undef QBMCU_DECINFO_ALU_LUI +`undef QBMCU_DECINFO_ALU_OP2IMM_LSB +`undef QBMCU_DECINFO_ALU_OP2IMM_MSB +`undef QBMCU_DECINFO_ALU_OP2IMM +`undef QBMCU_DECINFO_ALU_OP1PC_LSB +`undef QBMCU_DECINFO_ALU_OP1PC_MSB +`undef QBMCU_DECINFO_ALU_OP1PC +`undef QBMCU_DECINFO_ALU_NOP_LSB +`undef QBMCU_DECINFO_ALU_NOP_MSB +`undef QBMCU_DECINFO_ALU_NOP +`undef QBMCU_DECINFO_ALU_WIDTH + +//AGU group +`undef QBMCU_DECINFO_AGU_LOAD_LSB +`undef QBMCU_DECINFO_AGU_LOAD_MSB +`undef QBMCU_DECINFO_AGU_LOAD +`undef QBMCU_DECINFO_AGU_STORE_LSB +`undef QBMCU_DECINFO_AGU_STORE_MSB +`undef QBMCU_DECINFO_AGU_STORE +`undef QBMCU_DECINFO_AGU_SIZE_LSB +`undef QBMCU_DECINFO_AGU_SIZE_MSB +`undef QBMCU_DECINFO_AGU_SIZE +`undef QBMCU_DECINFO_AGU_USIGN_LSB +`undef QBMCU_DECINFO_AGU_USIGN_MSB +`undef QBMCU_DECINFO_AGU_USIGN +`undef QBMCU_DECINFO_AGU_OP2IMM_LSB +`undef QBMCU_DECINFO_AGU_OP2IMM_MSB +`undef QBMCU_DECINFO_AGU_OP2IMM +`undef QBMCU_DECINFO_AGU_WIDTH + +// Bxx group +`undef QBMCU_DECINFO_BJP_JUMP_LSB +`undef QBMCU_DECINFO_BJP_JUMP_MSB +`undef QBMCU_DECINFO_BJP_JUMP +`undef QBMCU_DECINFO_BJP_BPRDT_LSB +`undef QBMCU_DECINFO_BJP_BPRDT_MSB +`undef QBMCU_DECINFO_BJP_JALR +`undef QBMCU_DECINFO_BJP_BEQ_LSB +`undef QBMCU_DECINFO_BJP_BEQ_MSB +`undef QBMCU_DECINFO_BJP_BEQ +`undef QBMCU_DECINFO_BJP_BNE_LSB +`undef QBMCU_DECINFO_BJP_BNE_MSB +`undef QBMCU_DECINFO_BJP_BNE +`undef QBMCU_DECINFO_BJP_BLT_LSB +`undef QBMCU_DECINFO_BJP_BLT_MSB +`undef QBMCU_DECINFO_BJP_BLT +`undef QBMCU_DECINFO_BJP_BGT_LSB +`undef QBMCU_DECINFO_BJP_BGT_MSB +`undef QBMCU_DECINFO_BJP_BGT +`undef QBMCU_DECINFO_BJP_BLTU_LSB +`undef QBMCU_DECINFO_BJP_BLTU_MSB +`undef QBMCU_DECINFO_BJP_BLTU +`undef QBMCU_DECINFO_BJP_BGTU_LSB +`undef QBMCU_DECINFO_BJP_BGTU_MSB +`undef QBMCU_DECINFO_BJP_BGTU +`undef QBMCU_DECINFO_BJP_BXX_LSB +`undef QBMCU_DECINFO_BJP_BXX_MSB +`undef QBMCU_DECINFO_BJP_BXX +`undef QBMCU_DECINFO_BJP_WIDTH + + +// EXT group +`undef QBMCU_DECINFO_EXT_WAIT_LSB +`undef QBMCU_DECINFO_EXT_WAIT_MSB +`undef QBMCU_DECINFO_EXT_WAIT +`undef QBMCU_DECINFO_EXT_SEND_LSB +`undef QBMCU_DECINFO_EXT_SEND_MSB +`undef QBMCU_DECINFO_EXT_SEND +`undef QBMCU_DECINFO_EXT_SENDC_LSB +`undef QBMCU_DECINFO_EXT_SENDC_MSB +`undef QBMCU_DECINFO_EXT_SENDC +`undef QBMCU_DECINFO_EXT_EXIT_LSB +`undef QBMCU_DECINFO_EXT_EXIT_MSB +`undef QBMCU_DECINFO_EXT_EXIT +`undef QBMCU_DECINFO_EXT_EXITI_LSB +`undef QBMCU_DECINFO_EXT_EXITI_MSB +`undef QBMCU_DECINFO_EXT_EXITI +`undef QBMCU_DECINFO_EXT_OP2IMM_LSB +`undef QBMCU_DECINFO_EXT_OP2IMM_MSB +`undef QBMCU_DECINFO_EXT_OP2IMM +`undef QBMCU_DECINFO_EXT_WIDTH + +// Choose the longest group as the final DEC info width +`undef QBMCU_DECINFO_WIDTH + diff --git a/rtl/qubitmcu/qbmcu_wbck.v b/rtl/qubitmcu/qbmcu_wbck.v new file mode 100644 index 0000000..a08c1ec --- /dev/null +++ b/rtl/qubitmcu/qbmcu_wbck.v @@ -0,0 +1,89 @@ +//+FHDR-------------------------------------------------------------------------------------------------------- +// Company: +//----------------------------------------------------------------------------------------------------------------- +// File Name : qbmcu_exu_alu_ext.v +// Department : +// Author : PWY +// Author's Tel : +//----------------------------------------------------------------------------------------------------------------- +// Relese History +// Version Date Author Description +// 0.1 2024-03-13 PWY The Write-Back module to arbitrate the write-back request to regfile +//----------------------------------------------------------------------------------------------------------------- +// Keywords : +// +//----------------------------------------------------------------------------------------------------------------- +// Parameter +// +//----------------------------------------------------------------------------------------------------------------- +// Purpose : +// +//----------------------------------------------------------------------------------------------------------------- +// Target Device: +// Tool versions: +//----------------------------------------------------------------------------------------------------------------- +// Reuse Issues +// Reset Strategy: +// Clock Domains: +// Critical Timing: +// Asynchronous I/F: +// Synthesizable (y/n): +// Other: +//-FHDR-------------------------------------------------------------------------------------------------------- + +`include "qbmcu_defines.v" + +module qbmcu_wbck( + //system port + input clk + ,input rst_n + //The enable signal from the master control state machine + ,input wbck_i_active + //Write-back target register index from the decoding module + ,input [`QBMCU_RFIDX_WIDTH-1 :0] wbck_i_rdidx + //Write enable for the write-back target register from the decoding module + ,input wbck_i_rdwen + ////////////////////////////////////////////////////////////// + // The BJP Write-Back Interface + ,input [`QBMCU_XLEN-1 :0] bjp_i_wbck_wdat + ,input bjp_i_wbck_valid + // The AGU Write-Back Interface + ,input [`QBMCU_XLEN-1 :0] agu_i_wbck_wdat + ,input agu_i_wbck_valid + // The ALU Write-Back Interface + ,input [`QBMCU_XLEN-1 :0] alu_i_wbck_wdat + ,input alu_i_wbck_valid + // The Ext Write-Back Interface + ,input [`QBMCU_XLEN-1 :0] ext_i_wbck_wdat + ,input ext_i_wbck_valid + + ////////////////////////////////////////////////////////////// + // The Final arbitrated Write-Back Interface to Regfile + ,output wbck_o_ena + ,output [`QBMCU_XLEN-1 :0] wbck_o_wdat + ,output [`QBMCU_RFIDX_WIDTH-1 :0] wbck_o_rdidx + + ); + +//Write-back data multiplexer +wire [`QBMCU_XLEN-1:0] wbck_i_wdat = {`QBMCU_XLEN{bjp_i_wbck_valid}} & bjp_i_wbck_wdat + | {`QBMCU_XLEN{agu_i_wbck_valid}} & agu_i_wbck_wdat + | {`QBMCU_XLEN{alu_i_wbck_valid}} & alu_i_wbck_wdat + | {`QBMCU_XLEN{ext_i_wbck_valid}} & ext_i_wbck_wdat; + + +//Assigning Write-back module output signal values +wire wbck_o_ena_w = wbck_i_rdwen & wbck_i_active; + +sirv_gnrl_dffr #(1)wbck_o_ena_dffr (wbck_o_ena_w, wbck_o_ena, clk, rst_n); + +assign wbck_o_wdat = wbck_i_wdat[`QBMCU_XLEN-1:0]; +//assign wbck_o_rdidx = wbck_i_rdidx; + +sirv_gnrl_dfflr #(`QBMCU_RFIDX_WIDTH)wbck_o_rdidx_dfflr (wbck_i_active, wbck_i_rdidx, wbck_o_rdidx, clk, rst_n); + + +endmodule + +`include "qbmcu_undefines.v" + diff --git a/rtl/rstgen/rst_gen_unit.v b/rtl/rstgen/rst_gen_unit.v new file mode 100644 index 0000000..555216c --- /dev/null +++ b/rtl/rstgen/rst_gen_unit.v @@ -0,0 +1,64 @@ +`timescale 1ns/1ps +//==================================================== +//Author : pwy +//Date : 2024-04-04 +//Des : async set & sync release management unit +//==================================================== +module rst_gen_unit( + //ext hardware async reset -- low active + input async_rstn_i + //power-on reset -- low active + ,input por_rstn_i + //sys soft reset -- low active + ,input sys_soft_resetn_i + //ch0 soft reset -- low active + ,input ch0_soft_rstn_i + //ch1 soft reset -- low active + ,input ch1_soft_rstn_i + //ch2 soft reset -- low active + ,input ch2_soft_rstn_i + //ch3 soft reset -- low active + ,input ch3_soft_rstn_i + //clock + ,input clk + //reset output -- low active + ,output ch0_rstn_o + ,output ch1_rstn_o + ,output ch2_rstn_o + ,output ch3_rstn_o + //Phase-locked loop reset -- low active + ,output pll_rstn_o +); + +//ch0 reset --> async_rstn_i & por_rstn_i & sys_soft_resetn_i & ch0_soft_rstn_i +rst_sync ch0_rstn_sync ( + .clk_d ( clk ) + ,.async_rstn ( async_rstn_i & por_rstn_i & sys_soft_resetn_i & ch0_soft_rstn_i ) + ,.sync_rstn ( ch0_rstn_o ) +); + +//ch1 reset --> async_rstn_i & por_rstn_i & sys_soft_resetn_i & ch1_soft_rstn_i +rst_sync ch1_rstn_sync ( + .clk_d ( clk ) + ,.async_rstn ( async_rstn_i & por_rstn_i & sys_soft_resetn_i & ch1_soft_rstn_i ) + ,.sync_rstn ( ch1_rstn_o ) +); + +//ch2 reset --> async_rstn_i & por_rstn_i & sys_soft_resetn_i & ch2_soft_rstn_i +rst_sync ch2_rstn_sync ( + .clk_d ( clk ) + ,.async_rstn ( async_rstn_i & por_rstn_i & sys_soft_resetn_i & ch2_soft_rstn_i ) + ,.sync_rstn ( ch2_rstn_o ) +); + +//ch3 reset --> async_rstn_i & por_rstn_i & sys_soft_resetn_i & ch3_soft_rstn_i +rst_sync ch3_rstn_sync ( + .clk_d ( clk ) + ,.async_rstn ( async_rstn_i & por_rstn_i & sys_soft_resetn_i & ch3_soft_rstn_i ) + ,.sync_rstn ( ch3_rstn_o ) +); + +//Phase-locked loop reset -- low active +assign pll_rstn_o = async_rstn_i & por_rstn_i; + +endmodule diff --git a/rtl/rstgen/rst_sync.v b/rtl/rstgen/rst_sync.v new file mode 100644 index 0000000..c888918 --- /dev/null +++ b/rtl/rstgen/rst_sync.v @@ -0,0 +1,29 @@ +`timescale 1ns/1ps +//==================================================== +//Author : pwy +//Date : 2020-06-24 +//Des : async set & sync release +//==================================================== +module rst_sync( +input clk_d , +input async_rstn , +output sync_rstn +); + +reg rstn_s1; +reg rstn_s2; + +always@(posedge clk_d or negedge async_rstn)begin + if(!async_rstn)begin + rstn_s1 <=1'b0; + rstn_s2 <=1'b0; + end + else begin + rstn_s1 <=1'b1; + rstn_s2 <=rstn_s1; + end +end + +assign sync_rstn = rstn_s2; + +endmodule diff --git a/rtl/spi/spi_bus_decoder.sv b/rtl/spi/spi_bus_decoder.sv new file mode 100644 index 0000000..2912a49 --- /dev/null +++ b/rtl/spi/spi_bus_decoder.sv @@ -0,0 +1,91 @@ +//+FHDR-------------------------------------------------------------------------------------------------------- +// Company: +//----------------------------------------------------------------------------------------------------------------- +// File Name : spi_bus_decoder.v +// Department : +// Author : PWY +// Author's Tel : +//----------------------------------------------------------------------------------------------------------------- +// Relese History +// Version Date Author Description +// 0.1 2024-03-13 PWY Serial Peripheral Interface BUS Decoder +// 0.2 2024-06-15 PWY The slave interface address will be reduced from 25 bits to 20 bits. +//----------------------------------------------------------------------------------------------------------------- +// Keywords : +// +//----------------------------------------------------------------------------------------------------------------- +// Parameter +// +//----------------------------------------------------------------------------------------------------------------- +// Purpose : +// +//----------------------------------------------------------------------------------------------------------------- +// Target Device: +// Tool versions: +//----------------------------------------------------------------------------------------------------------------- +// Reuse Issues +// Reset Strategy: +// Clock Domains: +// Critical Timing: +// Asynchronous I/F: +// Synthesizable (y/n): +// Other: +//-FHDR-------------------------------------------------------------------------------------------------------- + +module spi_bus_decoder #( + parameter SLVNUM = 32 + ,parameter SPIBUS_CMD_REG = 1 + ,parameter SPIBUS_OUT_REG = 1 + )( + input clk + ,input rst_n + ,sram_if.slave mst + ,sram_if.master slv [SLVNUM-1:0] //s and m exchange + ); + + +generate + genvar i; + logic [SLVNUM-1:0] cs_slv; + logic [31 :0] dtemp[SLVNUM-1:0]; + + for(i=0;i>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>.....................................................>>>>>>>>------->LSB +///|<-----------MSB 32 bits-------------------------->||<--Second 32-bit---->||<-------x 32-bit---->||<-------n 32-bit---->| +// +-----++----------------------++------------++-----++---------------------++---------------------++---------------------+ +// | 31 || 30:6 || 5:1 || 0 || 31:0 || ...... || 31:0 | +// +-----++----------------------++------------++-----++---------------------++---------------------++---------------------+ +// +-----++----------------------++------------++-----++---------------------++---------------------++---------------------+ +// | wnr || addr[24:0] || CHIPID ||resv || data[31:0] || ...... || data[31:0] | +// +-----++----------------------++------------++-----++---------------------++---------------------++---------------------+ +//-----------------------------Spi Frame------------------------------------------------------------------------------------- +`timescale 1ns/1ps + +module spi_pll ( + //reset active low + input rst_n + //cfg ID + ,input [4 :0] cfgid //ID number for the entire chip + //SPI interface + ,input csn + ,input sclk + ,input mosi + ,output miso + ,output oen + //SPI Select signal + ,output sel + //regfile interface + ,output [31 :0] wrdata + ,output wren + ,output [7 :0] rwaddr + ,output rden + ,input [31 :0] rddata +); + +wire sel_w ; +wire wnr ; +wire [4 :0] addr_m5b ; +wire [7 :0] addr_l8b ; +wire [4 :0] chipid ; + +wire data_valid ; +//wire [31:0] rddata ;////////////////////////////////////// +//reg rden_reg ;////////////////////////////////////// + +//spi_rstn +wire spi_rstn = rst_n & (~csn); + +////////////////////////////////////////////////////////////////////////// +//bit count +////////////////////////////////////////////////////////////////////////// +wire [4:0] bit_cnt; +//add_cnt +wire add_cnt = ~csn; +//end_cnt +wire end_cnt = add_cnt & (bit_cnt == 5'd31); + + + +wire [4:0] cnt_n = end_cnt ? 5'd0 : + add_cnt ? bit_cnt + 5'b1 : + bit_cnt ; + + +sirv_gnrl_dffr #(5) bit_cnt_dffr (cnt_n, bit_cnt, sclk, spi_rstn); + + +/////////////////////////////////////////////////////////////////////////////// +//Determine whether the current input is an SPI command or data +//Detect the falling edge on the most significant bit of the counter. +//If a falling edge occurs, it indicates that the SPI frame has +//entered the data transmission phase. +/////////////////////////////////////////////////////////////////////////////// +wire bit_cnt_r; +wire bit_cnt_falling = bit_cnt_r & ~bit_cnt[4]; + +sirv_gnrl_dffr #(1) bit_cnt_r_dffr (bit_cnt[4], bit_cnt_r, sclk, spi_rstn); + + +//cmd_or_data:"High" represents data, "low" represents commands +wire cmd_or_data; + +sirv_gnrl_dfflr #(1) cmd_or_data_dfflr (bit_cnt_falling, 1'b1, cmd_or_data, sclk, spi_rstn); + +wire second_falling; + +sirv_gnrl_dfflr #(1) second_falling_dfflr (bit_cnt_falling & cmd_or_data, 1'b1, second_falling, sclk, spi_rstn); + +/////////////////////////////////////////////////////////////////////// +//SPI data sample (Load mosi data) +/////////////////////////////////////////////////////////////////////// + +generate + genvar i; + wire [31:0] recv_vld ; + wire [31:0] mosi_reg ; + for(i=0;i<32;i=i+1) begin: spi_pll_recv + assign recv_vld[i] = add_cnt & (bit_cnt == i ); + sirv_gnrl_dfflr #(1) spi_din_dfflr (recv_vld[i], mosi, mosi_reg[31-i], sclk, spi_rstn); + end +endgenerate + +//addr valid +wire addr_vaild = ~cmd_or_data & add_cnt & (bit_cnt == 5'd26); + +//CMD Update +sirv_gnrl_dfflr #(1) wnr_dfflr (addr_vaild, mosi_reg[31], wnr, sclk, spi_rstn); + +//addr_m5b Update +sirv_gnrl_dfflr #(5) addr_m5b_dfflr (addr_vaild, mosi_reg[30:26], addr_m5b, sclk, spi_rstn); + +//addr_l8b Update +sirv_gnrl_dfflr #(8) addr_l8b_dfflr (addr_vaild, mosi_reg[13:6], addr_l8b, sclk, spi_rstn); + +//chipid Valid +wire chipid_vld = ~cmd_or_data & add_cnt & (bit_cnt == 5'd31); +//chipid Update +sirv_gnrl_dfflr #(5) chipid_dfflr (chipid_vld, mosi_reg[5:1], chipid, sclk, spi_rstn); + +//sel_w +assign sel_w = (addr_m5b == 5'b11111) & (chipid == cfgid); + + + +//recv data valid +assign data_valid = cmd_or_data & (bit_cnt == 5'd31); +//assign data_valid = cmd_or_data & (bit_cnt == 5'd31);///////20240514 +//wren +assign wren = data_valid & sel_w & ~wnr; + +//rden +//assign rden = add_cnt & (bit_cnt == 5'd30);///////////////////////// +//assign rden = add_cnt & (bit_cnt == 5'd30) & sel_w;/////////////////////////20240514 +assign rden = add_cnt & (bit_cnt == 5'd30) & wnr;/////////////////////////20240604 + +wire rddata_update; +sirv_gnrl_dffr #(1) rddata_update_dffr (rden, rddata_update, sclk, spi_rstn); + +//wrdata +assign wrdata = {mosi_reg[31:1],mosi}; + +/////////////////////////////////////////////////////////////////////////////////////////////////////// +//Address generation for read and write operations +//The address to be used for updating in the next +//27 clock cycles in the read-write state +/////////////////////////////////////////////////////////////////////////////////////////////////////// + + +wire addr_update = ((wnr & cmd_or_data) | second_falling) & add_cnt & (bit_cnt == 5'd29); +//wire addr_update = cmd_or_data & add_cnt & (bit_cnt == 5'd27); + +wire [7:0] addr_c; + +wire [7:0] addr_n = ~cmd_or_data ? addr_l8b : + addr_update ? addr_c + 8'd4 : + addr_c ; + +sirv_gnrl_dffr #(8) addr_c_dffr (addr_n, addr_c, sclk, spi_rstn); + +assign rwaddr = addr_c; + +//sel +assign sel = sel_w; + +//oen +//assign oen = ~(sel_w & wnr & ~csn); +wire oen_w = ~(sel_w & wnr & ~csn); +sirv_gnrl_dffrs #(1) oen_dffrs (oen_w, oen, sclk, spi_rstn); +//data output +wire[31:0] miso_reg; +wire[31:0] miso_wire; +sirv_gnrl_dfflr #(32) miso_reg_dfflr (rddata_update, rddata, miso_reg, sclk, spi_rstn); +assign miso_wire = miso_reg; + +/////////////////////////////////////////////////////////////////////////////////////////////////////// +//SPI send data +/////////////////////////////////////////////////////////////////////////////////////////////////////// +generate + genvar j; + wire [31:0] send_vld ; + wire [31:0] dtemp ; + for(j=0;j<32;j=j+1) begin: spi_pll_send + //assign send_vld[j] = (bit_cnt == ((j==31) ? 0 : (j+1)) ); + assign send_vld[j] = (bit_cnt == j ); + if(j==0) begin: dtemp0 + assign dtemp[j] = (send_vld[j]) ? miso_wire[31-j] : 1'b0; + end + else begin: dtemp1_32 + assign dtemp[j] = (send_vld[j]) ? miso_wire[31-j] : dtemp[j-1]; + end + end +endgenerate + +assign miso = dtemp[31]; + +endmodule + + + + + diff --git a/rtl/spi/spi_slave.v b/rtl/spi/spi_slave.v new file mode 100644 index 0000000..32d3097 --- /dev/null +++ b/rtl/spi/spi_slave.v @@ -0,0 +1,106 @@ +//+FHDR-------------------------------------------------------------------------------------------------------- +// Company: +//----------------------------------------------------------------------------------------------------------------- +// File Name : spi_top.v +// Department : +// Author : pwy +// Author's Tel : +//----------------------------------------------------------------------------------------------------------------- +// Relese History +// Version Date Author Description +// 1.2 2024-04-02 pwy Integrate a digital module and two SPI modules with PLL +//----------------------------------------------------------------------------------------------------------------- +// Keywords : +// +//----------------------------------------------------------------------------------------------------------------- +// Parameter +// +//----------------------------------------------------------------------------------------------------------------- +// Purpose : +// +//----------------------------------------------------------------------------------------------------------------- +// Target Device: +// Tool versions: +//----------------------------------------------------------------------------------------------------------------- +// Reuse Issues +// Reset Strategy: +// Clock Domains: +// Critical Timing: +// Asynchronous I/F: +// Synthesizable (y/n): +// Other: +//-FHDR-------------------------------------------------------------------------------------------------------- + +module spi_slave ( + //system port + input clk // System Main Clock + ,input rst_n // Spi Reset active low + //spi port + ,input sclk // Spi Clock + ,input csn // Spi Chip Select active low + ,input mosi // Spi Mosi + ,input [4 :0] cfgid + ,output miso // Spi Miso + ,output oen // Spi Miso output enable + //connect pll + ,output [31 :0] pll_wrdata + ,output pll_wren + ,output [7 :0] pll_rwaddr + ,output pll_rden + ,input [31 :0] pll_rddata + //connect system + ,output [31 :0] sys_wrdata + ,output sys_wren + ,output [24 :0] sys_rwaddr + ,output sys_rden + ,input [31 :0] sys_rddata +); + +//////////////////////////////////////////////////////////////// +// pll spi +//////////////////////////////////////////////////////////////// +wire pll_miso ; +wire pll_oen ; +wire pll_sel ; + +spi_pll U_spi_pll ( + .rst_n ( rst_n ) + ,.cfgid ( cfgid ) + ,.csn ( csn ) + ,.sclk ( sclk ) + ,.mosi ( mosi ) + ,.miso ( pll_miso ) + ,.oen ( pll_oen ) + ,.sel ( pll_sel ) + ,.wrdata ( pll_wrdata ) + ,.wren ( pll_wren ) + ,.rwaddr ( pll_rwaddr ) + ,.rden ( pll_rden ) + ,.rddata ( pll_rddata ) +); + +//////////////////////////////////////////////////////////////// +//sys pll +//////////////////////////////////////////////////////////////// +wire sys_miso ; +wire sys_oen ; +spi_sys U_spi_sys ( + .clk ( clk ) + ,.rst_n ( rst_n ) + ,.cfgid ( cfgid ) + ,.sclk ( sclk ) + ,.csn ( csn ) + ,.mosi ( mosi ) + ,.miso ( sys_miso ) + ,.oen ( sys_oen ) + ,.wrdata ( sys_wrdata ) + ,.addr ( sys_rwaddr ) + ,.wren ( sys_wren ) + ,.rden ( sys_rden ) + ,.rddata ( sys_rddata ) +); + +assign miso = pll_sel ? pll_miso : sys_miso ; +assign oen = pll_sel ? pll_oen : sys_oen ; + +endmodule diff --git a/rtl/spi/spi_sys.v b/rtl/spi/spi_sys.v new file mode 100644 index 0000000..614b292 --- /dev/null +++ b/rtl/spi/spi_sys.v @@ -0,0 +1,291 @@ +//+FHDR-------------------------------------------------------------------------------------------------------- +// Company: +//----------------------------------------------------------------------------------------------------------------- +// File Name : spi_sys.v +// Department : +// Author : PWY +// Author's Tel : +//----------------------------------------------------------------------------------------------------------------- +// Relese History +// Version Date Author Description +// 0.1 2024-04-13 PWY SPI BUS for System +//----------------------------------------------------------------------------------------------------------------- +// Keywords : +// +//----------------------------------------------------------------------------------------------------------------- +// Parameter +// +//----------------------------------------------------------------------------------------------------------------- +// Purpose : +// +//----------------------------------------------------------------------------------------------------------------- +// Target Device: +// Tool versions: +//----------------------------------------------------------------------------------------------------------------- +// Reuse Issues +// Reset Strategy: +// Clock Domains: +// Critical Timing: +// Asynchronous I/F: +// Synthesizable (y/n): +// Other: +//-FHDR-------------------------------------------------------------------------------------------------------- + +//-----------------------------Spi Frame------------------------------------------------------------------------------------- +////MSB------------->>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>..............................................>>>>>>>>------->LSB +///|<-----------MSB 32 bits------------------->||<---------Second 32-bit---->||<-------x 32-bit---->||<-------n 32-bit---->| +// +-----++----------------------++------------++-----++---------------------++---------------------++---------------------+ +// | 31 || 30:6 || 5:1 || 0 || 31:0 || ...... || 31:0 | +// +-----++----------------------++------------++-----++---------------------++---------------------++---------------------+ +// +-----++----------------------++------------++-----++---------------------++---------------------++---------------------+ +// | wnr || addr[24:0] || CHIPID ||resv || data[31:0] || ...... || data[31:0] | +// +-----++----------------------++------------++-----++---------------------++---------------------++---------------------+ +//-----------------------------Spi Frame------------------------------------------------------------------------------------- + + +module spi_sys ( + //system port + input clk // System Main Clock + ,input rst_n // Spi Reset active low + //cfg ID + ,input [4 :0] cfgid //ID number for the entire chip + //spi port + ,input sclk // Spi Clock + ,input csn // Spi Chip Select active low + ,input mosi // Spi Mosi + ,output miso // Spi Miso + ,output oen // Spi Miso output enable + + ,output [31:0] wrdata //write data to sram + ,output [24:0] addr //sram address + ,output wren //write enable sram + ,output rden //rden enable sram + ,input [31:0] rddata //read data from sram + +); + +localparam IDLE = 2'b00, + RECVCMD = 2'b01, + WRITE = 2'b10, + READ = 2'b11; +//----------------------------------------------------------------------- +//SPI module reset processing +//----------------------------------------------------------------------- +//spi_rstn +//wire spi_rstn; +//assign spi_rstn = rst_n & (~csn); + +////////////////////////////////////////////////////////////////////////// +//capture the sck +////////////////////////////////////////////////////////////////////////// +wire [2:0] sclk_reg; +//sync sclk to the main clock using a 3-bits shift register +sirv_gnrl_dffrs #(3) sclk_reg_dffrs ({sclk_reg[1:0],sclk}, sclk_reg, clk, rst_n); + +//sclk's rising edges +wire sclk_p = (sclk_reg[2:1] == 2'b01); + +//sclk's falling edges +//assign sclk_n = (sclk_reg[2:1] == 2'b10); + +////////////////////////////////////////////////////////////////////////// +//capture the csn +////////////////////////////////////////////////////////////////////////// +wire [2:0] csn_reg; +//sync csn to the main clock using a 2-bits shift register + +sirv_gnrl_dffrs #(3) csn_reg_dffrs ({csn_reg[1:0],csn}, csn_reg, clk, rst_n); +// csn is active low +wire csn_active = ~csn_reg[1]; + +//csn's rising edges +wire csn_p = (csn_reg[2:1] == 2'b01); + +//csn's falling edges +wire csn_n = (csn_reg[2:1] == 2'b10); + +////////////////////////////////////////////////////////////////////////// +//capture the mosi +////////////////////////////////////////////////////////////////////////// +wire [1:0] mosi_reg; +//sync mosi to the main clock using a 2-bits shift register + +sirv_gnrl_dffr #(2) mosi_reg_dffr ({mosi_reg[0],mosi}, mosi_reg, clk, rst_n); +//mosi_data +wire mosi_data = mosi_reg[1]; + +////////////////////////////////////////////////////////////////////////// +//cnt +////////////////////////////////////////////////////////////////////////// +wire [4:0] cnt_c; +//add_cnt +assign add_cnt = sclk_p && csn_active; +//end_cnt +assign end_cnt = (add_cnt && (cnt_c == 5'd31)) | csn_p; + +wire [4:0] cnt_n = end_cnt ? 5'h0 : + add_cnt ? cnt_c + 5'b1 : + cnt_c ; + + +sirv_gnrl_dffr #(5) cnt_c_dffr (cnt_n, cnt_c, clk, rst_n); + + +/////////////////////////////////////////////////////////////////////// +//SPI data sample +/////////////////////////////////////////////////////////////////////// + +generate + genvar i; + wire [31:0] recv_vld ; + wire [31:0] spi_din ; + for(i=0;i<32;i=i+1) begin: spi_sys_recv + assign recv_vld[i] = add_cnt & (cnt_c == i ); + sirv_gnrl_dfflr #(1) spi_din_dfflr (recv_vld[i], mosi_data, spi_din[31-i], clk, rst_n); + end +endgenerate + + +wire [1:0] state_c; +wire [1:0] state_n; + + +/////////////////////////////////////////////////////////////////////// +//init_addr capture +/////////////////////////////////////////////////////////////////////// +wire [24:0] initaddr; +wire initaddr_vld = (state_c == RECVCMD ) & add_cnt && (cnt_c == 5'd26); +wire [1:0] initaddr_vld_r; +sirv_gnrl_dffr #(2) initaddr_vld_r_dffr ({initaddr_vld_r[0],initaddr_vld}, initaddr_vld_r, clk, rst_n); + +sirv_gnrl_dfflr #(25) initaddr_dfflr (initaddr_vld_r[0], spi_din[30:6], initaddr, clk, rst_n); + +/////////////////////////////////////////////////////////////////////// +//CMD capture +/////////////////////////////////////////////////////////////////////// +wire cmd ; +sirv_gnrl_dfflr #(1) cmd_dfflr ( initaddr_vld_r[0], spi_din[31], cmd, clk, rst_n); + +/////////////////////////////////////////////////////////////////////// +//CHIPID capture +/////////////////////////////////////////////////////////////////////// +wire [4:0] chipid; +wire [1:0] chipid_vld_r; +wire chipid_vld = (state_c == RECVCMD ) & add_cnt & (cnt_c == 5'd30); +//register cmd_vld to align it with cmd +sirv_gnrl_dffr #(2) chipid_vld_r_dffr ({chipid_vld_r[0],chipid_vld}, chipid_vld_r, clk, rst_n); + +sirv_gnrl_dfflr #(5) chipid_dfflr (chipid_vld_r[0], spi_din[5:1], chipid, clk, rst_n); + +/////////////////////////////////////////////////////////////////////// +//ID matching determination +/////////////////////////////////////////////////////////////////////// +wire chipid_match = (chipid == cfgid); +wire chipid_dismatch = (chipid != cfgid); + + + +/////////////////////////////////////////////////////////////////////// +//SPI Module State Machine +/////////////////////////////////////////////////////////////////////// + +//Generating jump conditions for state machines +wire ilde2recvcmd = (state_c == IDLE ) && csn_active && csn_n ; +wire recvcmd2ilde = (state_c == RECVCMD ) && chipid_dismatch & end_cnt; +wire recvcmd2write = (state_c == RECVCMD ) && chipid_match && ~cmd & end_cnt; +wire recvcmd2read = (state_c == RECVCMD ) && chipid_match && cmd & end_cnt; +wire write2idle = (state_c == WRITE ) && csn_p; +wire read2idle = (state_c == READ ) && csn_p; + +//The first section of the state machine +//state_c +sirv_gnrl_dffr #(2) state_c_dffr (state_n, state_c, clk, rst_n); + +//state_n +assign state_n = ((state_c == IDLE ) && ilde2recvcmd ) ? RECVCMD : + ((state_c == RECVCMD ) && recvcmd2ilde ) ? IDLE : + ((state_c == RECVCMD ) && recvcmd2write ) ? WRITE : + ((state_c == RECVCMD ) && recvcmd2read ) ? READ : + ((state_c == WRITE ) && write2idle ) ? IDLE : + ((state_c == READ ) && read2idle ) ? IDLE : + state_c ; + + +/////////////////////////////////////////////////////////////////////////////////////////////////////// +//Address generation for read and write operations +//The address to be used for updating in the next +//27 clock cycles in the read-write state +/////////////////////////////////////////////////////////////////////////////////////////////////////// +wire second_falling; +wire second_falling_w = (state_c == WRITE); +sirv_gnrl_dfflr #(1) second_falling_dfflr (end_cnt ,second_falling_w, second_falling, clk, rst_n); + +wire addr_update = ((state_c == READ) | ((state_c == WRITE) & second_falling)) & add_cnt & (cnt_c == 5'd27); +wire [24:0] addr_c; + +wire [24:0] addr_n = ilde2recvcmd ? 25'd0 : + initaddr_vld_r[1] ? initaddr : + addr_update ? addr_c + 25'd4 : + addr_c ; + +sirv_gnrl_dffr #(25) addr_c_dffr (addr_n, addr_c, clk, rst_n); + +assign addr = addr_c; + +/////////////////////////////////////////////////////////////////////////////////////////////////////// +//Write data and write signals generation +/////////////////////////////////////////////////////////////////////////////////////////////////////// +wire wren_r; + +wire wren_w = (state_c == WRITE) & add_cnt & (cnt_c == 5'd31); +//wdata +sirv_gnrl_dfflr #(32) wrdata_dfflr (wren_r, spi_din[31:0], wrdata, clk, rst_n); +//wren_r + +sirv_gnrl_dffr #(1) wren_r_dffr (wren_w, wren_r, clk, rst_n); + +//wren +sirv_gnrl_dffr #(1) wren_dffr (wren_r, wren, clk, rst_n); + +/////////////////////////////////////////////////////////////////////////////////////////////////////// +//read signals generation +/////////////////////////////////////////////////////////////////////////////////////////////////////// + +wire rden_w = cmd & add_cnt & (cnt_c == 5'd28); +sirv_gnrl_dffr #(1) rden_dffr (rden_w, rden, clk, rst_n); + +//Read data register +wire rddata_vld = cmd & add_cnt & (cnt_c == 5'd30); +wire [31:0] rddata_reg; +sirv_gnrl_dfflr #(32) rddata_reg_dfflr (rddata_vld, rddata[31:0], rddata_reg, clk, rst_n); + + +/////////////////////////////////////////////////////////////////////////////////////////////////////// +//SPI send data update +/////////////////////////////////////////////////////////////////////////////////////////////////////// +wire [31:0] spi_dout ; +wire update_flag = cmd & add_cnt & (cnt_c == 5'd31); + +wire [31:0] rddata_sr = update_flag ? rddata_reg[31:0] : + ((state_c == READ) & add_cnt) ? {spi_dout[31:0],1'b0} : + spi_dout ; + +sirv_gnrl_dffr #(32) spi_dout_dffr (rddata_sr, spi_dout, clk, rst_n); + + +/////////////////////////////////////////////////////////////////////////////////////////////////////// +//SPI send data +/////////////////////////////////////////////////////////////////////////////////////////////////////// + +assign miso = spi_dout[31]; + + + +/////////////////////////////////////////////////////////////////////////////////////////////////////// +//SPI output enable +/////////////////////////////////////////////////////////////////////////////////////////////////////// +sirv_gnrl_dffrs #(1) oen_dffr (~(state_c == READ), oen, clk, rst_n); + +endmodule + + diff --git a/rtl/spi/spi_sys_20240624.v b/rtl/spi/spi_sys_20240624.v new file mode 100644 index 0000000..b835ba9 --- /dev/null +++ b/rtl/spi/spi_sys_20240624.v @@ -0,0 +1,292 @@ +//+FHDR-------------------------------------------------------------------------------------------------------- +// Company: +//----------------------------------------------------------------------------------------------------------------- +// File Name : spi_sys.v +// Department : +// Author : PWY +// Author's Tel : +//----------------------------------------------------------------------------------------------------------------- +// Relese History +// Version Date Author Description +// 0.1 2024-04-13 PWY SPI BUS for System +// 0.2 2024-06-24 PWY {spi_dout[31:0],1'b0} -> {spi_dout[30:0],1'b0} +//----------------------------------------------------------------------------------------------------------------- +// Keywords : +// +//----------------------------------------------------------------------------------------------------------------- +// Parameter +// +//----------------------------------------------------------------------------------------------------------------- +// Purpose : +// +//----------------------------------------------------------------------------------------------------------------- +// Target Device: +// Tool versions: +//----------------------------------------------------------------------------------------------------------------- +// Reuse Issues +// Reset Strategy: +// Clock Domains: +// Critical Timing: +// Asynchronous I/F: +// Synthesizable (y/n): +// Other: +//-FHDR-------------------------------------------------------------------------------------------------------- + +//-----------------------------Spi Frame------------------------------------------------------------------------------------- +////MSB------------->>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>..............................................>>>>>>>>------->LSB +///|<-----------MSB 32 bits------------------->||<---------Second 32-bit---->||<-------x 32-bit---->||<-------n 32-bit---->| +// +-----++----------------------++------------++-----++---------------------++---------------------++---------------------+ +// | 31 || 30:6 || 5:1 || 0 || 31:0 || ...... || 31:0 | +// +-----++----------------------++------------++-----++---------------------++---------------------++---------------------+ +// +-----++----------------------++------------++-----++---------------------++---------------------++---------------------+ +// | wnr || addr[24:0] || CHIPID ||resv || data[31:0] || ...... || data[31:0] | +// +-----++----------------------++------------++-----++---------------------++---------------------++---------------------+ +//-----------------------------Spi Frame------------------------------------------------------------------------------------- + + +module spi_sys ( + //system port + input clk // System Main Clock + ,input rst_n // Spi Reset active low + //cfg ID + ,input [4 :0] cfgid //ID number for the entire chip + //spi port + ,input sclk // Spi Clock + ,input csn // Spi Chip Select active low + ,input mosi // Spi Mosi + ,output miso // Spi Miso + ,output oen // Spi Miso output enable + + ,output [31:0] wrdata //write data to sram + ,output [24:0] addr //sram address + ,output wren //write enable sram + ,output rden //rden enable sram + ,input [31:0] rddata //read data from sram + +); + +localparam IDLE = 2'b00, + RECVCMD = 2'b01, + WRITE = 2'b10, + READ = 2'b11; +//----------------------------------------------------------------------- +//SPI module reset processing +//----------------------------------------------------------------------- +//spi_rstn +//wire spi_rstn; +//assign spi_rstn = rst_n & (~csn); + +////////////////////////////////////////////////////////////////////////// +//capture the sck +////////////////////////////////////////////////////////////////////////// +wire [2:0] sclk_reg; +//sync sclk to the main clock using a 3-bits shift register +sirv_gnrl_dffrs #(3) sclk_reg_dffrs ({sclk_reg[1:0],sclk}, sclk_reg, clk, rst_n); + +//sclk's rising edges +wire sclk_p = (sclk_reg[2:1] == 2'b01); + +//sclk's falling edges +//assign sclk_n = (sclk_reg[2:1] == 2'b10); + +////////////////////////////////////////////////////////////////////////// +//capture the csn +////////////////////////////////////////////////////////////////////////// +wire [2:0] csn_reg; +//sync csn to the main clock using a 2-bits shift register + +sirv_gnrl_dffrs #(3) csn_reg_dffrs ({csn_reg[1:0],csn}, csn_reg, clk, rst_n); +// csn is active low +wire csn_active = ~csn_reg[1]; + +//csn's rising edges +wire csn_p = (csn_reg[2:1] == 2'b01); + +//csn's falling edges +wire csn_n = (csn_reg[2:1] == 2'b10); + +////////////////////////////////////////////////////////////////////////// +//capture the mosi +////////////////////////////////////////////////////////////////////////// +wire [1:0] mosi_reg; +//sync mosi to the main clock using a 2-bits shift register + +sirv_gnrl_dffr #(2) mosi_reg_dffr ({mosi_reg[0],mosi}, mosi_reg, clk, rst_n); +//mosi_data +wire mosi_data = mosi_reg[1]; + +////////////////////////////////////////////////////////////////////////// +//cnt +////////////////////////////////////////////////////////////////////////// +wire [4:0] cnt_c; +//add_cnt +assign add_cnt = sclk_p && csn_active; +//end_cnt +assign end_cnt = (add_cnt && (cnt_c == 5'd31)) | csn_p; + +wire [4:0] cnt_n = end_cnt ? 5'h0 : + add_cnt ? cnt_c + 5'b1 : + cnt_c ; + + +sirv_gnrl_dffr #(5) cnt_c_dffr (cnt_n, cnt_c, clk, rst_n); + + +/////////////////////////////////////////////////////////////////////// +//SPI data sample +/////////////////////////////////////////////////////////////////////// + +generate + genvar i; + wire [31:0] recv_vld ; + wire [31:0] spi_din ; + for(i=0;i<32;i=i+1) begin: spi_sys_recv + assign recv_vld[i] = add_cnt & (cnt_c == i ); + sirv_gnrl_dfflr #(1) spi_din_dfflr (recv_vld[i], mosi_data, spi_din[31-i], clk, rst_n); + end +endgenerate + + +wire [1:0] state_c; +wire [1:0] state_n; + + +/////////////////////////////////////////////////////////////////////// +//init_addr capture +/////////////////////////////////////////////////////////////////////// +wire [24:0] initaddr; +wire initaddr_vld = (state_c == RECVCMD ) & add_cnt && (cnt_c == 5'd26); +wire [1:0] initaddr_vld_r; +sirv_gnrl_dffr #(2) initaddr_vld_r_dffr ({initaddr_vld_r[0],initaddr_vld}, initaddr_vld_r, clk, rst_n); + +sirv_gnrl_dfflr #(25) initaddr_dfflr (initaddr_vld_r[0], spi_din[30:6], initaddr, clk, rst_n); + +/////////////////////////////////////////////////////////////////////// +//CMD capture +/////////////////////////////////////////////////////////////////////// +wire cmd ; +sirv_gnrl_dfflr #(1) cmd_dfflr ( initaddr_vld_r[0], spi_din[31], cmd, clk, rst_n); + +/////////////////////////////////////////////////////////////////////// +//CHIPID capture +/////////////////////////////////////////////////////////////////////// +wire [4:0] chipid; +wire [1:0] chipid_vld_r; +wire chipid_vld = (state_c == RECVCMD ) & add_cnt & (cnt_c == 5'd30); +//register cmd_vld to align it with cmd +sirv_gnrl_dffr #(2) chipid_vld_r_dffr ({chipid_vld_r[0],chipid_vld}, chipid_vld_r, clk, rst_n); + +sirv_gnrl_dfflr #(5) chipid_dfflr (chipid_vld_r[0], spi_din[5:1], chipid, clk, rst_n); + +/////////////////////////////////////////////////////////////////////// +//ID matching determination +/////////////////////////////////////////////////////////////////////// +wire chipid_match = (chipid == cfgid); +wire chipid_dismatch = (chipid != cfgid); + + + +/////////////////////////////////////////////////////////////////////// +//SPI Module State Machine +/////////////////////////////////////////////////////////////////////// + +//Generating jump conditions for state machines +wire ilde2recvcmd = (state_c == IDLE ) && csn_active && csn_n ; +wire recvcmd2ilde = (state_c == RECVCMD ) && chipid_dismatch & end_cnt; +wire recvcmd2write = (state_c == RECVCMD ) && chipid_match && ~cmd & end_cnt; +wire recvcmd2read = (state_c == RECVCMD ) && chipid_match && cmd & end_cnt; +wire write2idle = (state_c == WRITE ) && csn_p; +wire read2idle = (state_c == READ ) && csn_p; + +//The first section of the state machine +//state_c +sirv_gnrl_dffr #(2) state_c_dffr (state_n, state_c, clk, rst_n); + +//state_n +assign state_n = ((state_c == IDLE ) && ilde2recvcmd ) ? RECVCMD : + ((state_c == RECVCMD ) && recvcmd2ilde ) ? IDLE : + ((state_c == RECVCMD ) && recvcmd2write ) ? WRITE : + ((state_c == RECVCMD ) && recvcmd2read ) ? READ : + ((state_c == WRITE ) && write2idle ) ? IDLE : + ((state_c == READ ) && read2idle ) ? IDLE : + state_c ; + + +/////////////////////////////////////////////////////////////////////////////////////////////////////// +//Address generation for read and write operations +//The address to be used for updating in the next +//27 clock cycles in the read-write state +/////////////////////////////////////////////////////////////////////////////////////////////////////// +wire second_falling; +wire second_falling_w = (state_c == WRITE); +sirv_gnrl_dfflr #(1) second_falling_dfflr (end_cnt ,second_falling_w, second_falling, clk, rst_n); + +wire addr_update = ((state_c == READ) | ((state_c == WRITE) & second_falling)) & add_cnt & (cnt_c == 5'd27); +wire [24:0] addr_c; + +wire [24:0] addr_n = ilde2recvcmd ? 25'd0 : + initaddr_vld_r[1] ? initaddr : + addr_update ? addr_c + 25'd4 : + addr_c ; + +sirv_gnrl_dffr #(25) addr_c_dffr (addr_n, addr_c, clk, rst_n); + +assign addr = addr_c; + +/////////////////////////////////////////////////////////////////////////////////////////////////////// +//Write data and write signals generation +/////////////////////////////////////////////////////////////////////////////////////////////////////// +wire wren_r; + +wire wren_w = (state_c == WRITE) & add_cnt & (cnt_c == 5'd31); +//wdata +sirv_gnrl_dfflr #(32) wrdata_dfflr (wren_r, spi_din[31:0], wrdata, clk, rst_n); +//wren_r + +sirv_gnrl_dffr #(1) wren_r_dffr (wren_w, wren_r, clk, rst_n); + +//wren +sirv_gnrl_dffr #(1) wren_dffr (wren_r, wren, clk, rst_n); + +/////////////////////////////////////////////////////////////////////////////////////////////////////// +//read signals generation +/////////////////////////////////////////////////////////////////////////////////////////////////////// + +wire rden_w = cmd & add_cnt & (cnt_c == 5'd28); +sirv_gnrl_dffr #(1) rden_dffr (rden_w, rden, clk, rst_n); + +//Read data register +wire rddata_vld = cmd & add_cnt & (cnt_c == 5'd30); +wire [31:0] rddata_reg; +sirv_gnrl_dfflr #(32) rddata_reg_dfflr (rddata_vld, rddata[31:0], rddata_reg, clk, rst_n); + + +/////////////////////////////////////////////////////////////////////////////////////////////////////// +//SPI send data update +/////////////////////////////////////////////////////////////////////////////////////////////////////// +wire [31:0] spi_dout ; +wire update_flag = cmd & add_cnt & (cnt_c == 5'd31); + +wire [31:0] rddata_sr = update_flag ? rddata_reg[31:0] : + ((state_c == READ) & add_cnt) ? {spi_dout[30:0],1'b0} : //M 2024-06-24 + spi_dout ; + +sirv_gnrl_dffr #(32) spi_dout_dffr (rddata_sr, spi_dout, clk, rst_n); + + +/////////////////////////////////////////////////////////////////////////////////////////////////////// +//SPI send data +/////////////////////////////////////////////////////////////////////////////////////////////////////// + +assign miso = spi_dout[31]; + + + +/////////////////////////////////////////////////////////////////////////////////////////////////////// +//SPI output enable +/////////////////////////////////////////////////////////////////////////////////////////////////////// +sirv_gnrl_dffrs #(1) oen_dffr (~(state_c == READ), oen, clk, rst_n); + +endmodule + + diff --git a/rtl/spram_model_0.v b/rtl/spram_model_0.v new file mode 100644 index 0000000..38103c1 --- /dev/null +++ b/rtl/spram_model_0.v @@ -0,0 +1,68 @@ +module spram_model #( + parameter width = 32 + ,parameter depth = 256 +)( + clka, + ena, + dina, + addra, + + clkb, + enb, + doutb, + addrb +); + +//================================================= +function integer clog2(input integer depth); +begin + for(clog2=0;depth>0;clog2=clog2+1) + depth =depth>>1; +end +endfunction +//================================================= + +localparam aw = clog2(depth-1); +//================================================= +input clka; +input ena; +input [width-1:0] dina; +input [aw-1:0] addra; + +input clkb; +input enb; +output [width-1:0] doutb; +input [aw-1:0] addrb; + + +//================================================ +wire clka; +wire ena; +wire [width-1:0] dina; +wire [aw-1:0] addra; + +wire clkb; +wire enb; +reg [width-1:0] doutb; +wire [aw-1:0] addrb; + + +//================================================ +reg [width-1:0] mem[0:depth-1]; + +always@(posedge clka)begin + if(ena)begin + mem[addra] <=dina; + end +end + +always@(posedge clkb)begin + if(enb)begin + doutb <=mem[addrb]; + end + else begin + doutb <=doutb; + end +end + +endmodule diff --git a/rtl/sync/sync_buf.sv b/rtl/sync/sync_buf.sv new file mode 100644 index 0000000..7eef50c --- /dev/null +++ b/rtl/sync/sync_buf.sv @@ -0,0 +1,32 @@ +module sync_buf #( +)( + input logic clk, + input logic rst_n, + input logic ext_ena, + input logic clr_ena, + input logic clr_ena_sync, + input logic sync_in, + output logic sync_int, + output logic sync_ext, + output logic sync_clr +); + + + +logic [2:0] sync_r; +always @(posedge clk or negedge rst_n) begin + if(!rst_n) begin + sync_r[2:0] <= 3'b000; + sync_int <= 1'b0; + sync_ext <= 1'b0; + end + else begin + sync_r[2:0] <= {sync_r[1:0],sync_in}; // delay two clock + sync_int <= (sync_r[2:1] == 2'b01) & !clr_ena_sync; // detect pos edge + sync_ext <= sync_r[2] & ext_ena; // sync input to clk + end +end + +assign sync_clr = ~(clr_ena & sync_in); // controlled buf out + +endmodule \ No newline at end of file diff --git a/rtl/system_regfile/system_regfile.v b/rtl/system_regfile/system_regfile.v new file mode 100644 index 0000000..65c59c2 --- /dev/null +++ b/rtl/system_regfile/system_regfile.v @@ -0,0 +1,637 @@ +//+FHDR-------------------------------------------------------------------------------------------------------- +// Company: +//----------------------------------------------------------------------------------------------------------------- +// File Name : ssytem_regfile.v +// Department : +// Author : PWY +// Author's Tel : +//----------------------------------------------------------------------------------------------------------------- +// Relese History +// Version Date Author Description +// 1.0 2022-08-25 PWY +//----------------------------------------------------------------------------------------------------------------- +// Keywords : +// +//----------------------------------------------------------------------------------------------------------------- +// Parameter +// +//----------------------------------------------------------------------------------------------------------------- +// Purpose : +// +//----------------------------------------------------------------------------------------------------------------- +// Target Device: +// Tool versions: +//----------------------------------------------------------------------------------------------------------------- +// Reuse Issues +// Reset Strategy: +// Clock Domains: +// Critical Timing: +// Asynchronous I/F: +// Synthesizable (y/n): +// Other: +//-FHDR-------------------------------------------------------------------------------------------------------- + +// ----------------------------------------------------------- +// -- Register address offset macros +// ----------------------------------------------------------- +//Identity Register +`define IDR 16'h00 +//Vendor Code Register +`define VIDR 16'h04 +//RTL Freeze Date Register +`define DATER 16'h08 +//Version Register +`define VERR 16'h0C +//Wirte And Read Test Register +`define TESTR 16'h10 +//Interrupt Mask Register +//[31:29] --> Reserved +//[28 ] --> DBG UPD Interrupt Mask +//[27 ] --> CH3 AWG Conflict nterrupt Mask +//[26 ] --> CH3 LDST ADDR UNALGN Interrupt Mask +//[25 ] --> CH3 DEC ERR Interrupt Mask +//[24 ] --> CH3 EXITI Interrupt Mask +//[23:20] --> Reserved +//[19 ] --> CH2 AWG Conflict nterrupt Mask +//[18 ] --> CH2 LDST ADDR UNALGN Interrupt Mask +//[17 ] --> CH2 DEC ERR Interrupt Mask +//[16 ] --> CH2 EXITI Interrupt Mask +//[15:12] --> Reserved +//[11 ] --> CH1 AWG Conflict nterrupt Mask +//[10 ] --> CH1 LDST ADDR UNALGN Interrupt Mask +//[9 ] --> CH1 DEC ERR Interrupt Mask +//[8 ] --> CH1 EXITI Interrupt Mask +//[7 :4] --> Reserved +//[3 ] --> CH1 AWG Conflict nterrupt Mask +//[2 ] --> CH1 LDST ADDR UNALGN Interrupt Mask +//[1 ] --> CH1 DEC ERR Interrupt Mask +//[0 ] --> CH1 EXITI Interrupt Mask +`define IMR 16'h14 +//[31:29] --> Reserved +//[28 ] --> DBG UPD Interrupt Status +//[27 ] --> CH3 AWG Conflict nterrupt Status +//[26 ] --> CH3 LDST ADDR UNALGN Interrupt Status +//[25 ] --> CH3 DEC ERR Interrupt Status +//[24 ] --> CH3 EXITI Interrupt Status +//[23:20] --> Reserved +//[19 ] --> CH2 AWG Conflict Status +//[18 ] --> CH2 LDST ADDR UNALGN Interrupt Status +//[17 ] --> CH2 DEC ERR Interrupt Status +//[16 ] --> CH2 EXITI Interrupt Status +//[15:12] --> Reserved +//[11 ] --> CH1 AWG Conflict nterrupt Status +//[10 ] --> CH1 LDST ADDR UNALGN Interrupt Status +//[9 ] --> CH1 DEC ERR Interrupt Status +//[8 ] --> CH1 EXITI Interrupt Status +//[7 :4] --> Reserved +//[3 ] --> CH1 AWG Conflict nterrupt Status +//[2 ] --> CH1 LDST ADDR UNALGN Interrupt Status +//[1 ] --> CH1 DEC ERR Interrupt Status +//[0 ] --> CH1 EXITI Interrupt Status +`define ISR 16'h18 +//Soft Reset Time Register +`define SFRTR 16'h1C +//Soft Reset Register +`define SFRR 16'h20 +//CH0 Soft Reset Register +`define CH0RSTR 16'h24 +//CH1Soft Reset Register +`define CH1RSTR 16'h28 +//CH2 Soft Reset Register +`define CH2RSTR 16'h2C +//CH3 Soft Reset Register +`define CH3RSTR 16'h30 +//Debug config Register +`define DBGCFGR 16'h34 +//Post Masking Interrupt Status Register +//Interrupt Status Register +//[31:29] --> Reserved +//[28 ] --> DBG UPD Interrupt Status +//[27 ] --> CH3 AWG Conflict nterrupt Status +//[26 ] --> CH3 LDST ADDR UNALGN Masking Interrupt Status +//[25 ] --> CH3 DEC ERR Masking Interrupt Status +//[24 ] --> CH3 EXITI Masking Interrupt Status +//[23:20] --> Reserved +//[19 ] --> CH2 AWG Conflict Status +//[18 ] --> CH2 LDST ADDR UNALGN Masking Interrupt Status +//[17 ] --> CH2 DEC ERR Masking Interrupt Status +//[16 ] --> CH2 EXITI Masking Interrupt Status +//[15:12] --> Reserved +//[11 ] --> CH1 AWG Conflict nterrupt Status +//[10 ] --> CH1 LDST ADDR UNALGN Masking Interrupt Status +//[9 ] --> CH1 DEC ERR Masking Interrupt Status +//[8 ] --> CH1 EXITI Masking Interrupt Status +//[7 :4] --> Reserved +//[3 ] --> CH1 AWG Conflict nterrupt Status +//[2 ] --> CH1 LDST ADDR UNALGN Masking Interrupt Status +//[1 ] --> CH1 DEC ERR Masking Interrupt Status +//[0 ] --> CH1 EXITI Masking Interrupt Status +`define MISR 16'h40 + + +module system_regfile ( + //system port + input clk // System Main Clock + ,input rst_n // Spi Reset active low + //rw op port + ,input [31 :0] wrdata // write data + ,input wren // write enable + ,input [15 :0] rwaddr // read & write address + ,input rden // read enable + ,output [31 :0] rddata // read data + //debug cfg port + ,output dbg_enable //active high + ,output dbg_data_sel //1'b0-->mod;1'b1-->dsp + ,output [3 :0] dbg_ch_sel //4'b0001-->ch0;4'b0010-->ch1; + //4'b0100-->ch2;4'b1000-->ch3; + //debug status Port + ,input dbg_upd + //ch0 status Port + ,input ch0_proc_cft + ,input ch0_ldst_addr_unalgn + ,input ch0_dec_err + ,input ch0_exit_irq + //ch1 status Port + ,input ch1_proc_cft + ,input ch1_ldst_addr_unalgn + ,input ch1_dec_err + ,input ch1_exit_irq + //ch2 status Port + ,input ch2_proc_cft + ,input ch2_ldst_addr_unalgn + ,input ch2_dec_err + ,input ch2_exit_irq + //ch3 status Port + ,input ch3_proc_cft + ,input ch3_ldst_addr_unalgn + ,input ch3_dec_err + ,input ch3_exit_irq + //Soft Reset out + ,output sys_soft_rstn + ,output ch0_soft_rstn + ,output ch1_soft_rstn + ,output ch2_soft_rstn + ,output ch3_soft_rstn + //Interrupt output port + ,output irq +); + +localparam L = 1'b0, + H = 1'b1; + +localparam IDRD = 32'h41574743; +localparam VIDRD = 32'h55535443; +localparam DATERD = 32'h20220831; +localparam VERSION = 32'h00000001; +localparam TESTRD = 32'h01234567; +// ------------------------------------------------------ +// -- Register enable (select) wires +// ------------------------------------------------------ +wire idren; // idr select +wire vidren; // vidr select +wire dateren; // dater select +wire verren; // dater select +wire testren; // testr select +wire imren; // imr select +wire isren; // isr select +wire misren; // imsr select +wire sfrtren; // sfrtr select +wire sfrren; // sfrr select +wire ch0rstren; // mcurstr select +wire ch1rstren; // awgrstr select +wire ch2rstren; // adacrstr select +wire ch3rstren; // adacrstr select +wire dbgcfgren; // adacrstr select + + +// ------------------------------------------------------ +// -- Register write enable wires +// ------------------------------------------------------ +wire testrwe; // testr write enable +wire imrwe; // imr write enable +wire misrwe; // imsr write enable +wire sfrtrwe; // sfrtr write enable +wire sfrrwe; // sfrr write enable +wire ch0rstrwe; // mcurstr select +wire ch1rstrwe; // awgrstr select +wire ch2rstrwe; // adacrstr select +wire ch3rstrwe; // adacrstr select +wire dbgcfgrwe; // adacrstr write enable + +// ------------------------------------------------------ +// -- Misc wires +// ------------------------------------------------------ +wire [31 :0] irisr ; // original interrupt status wire +wire icr ; // interrupt status clear wire + +// ------------------------------------------------------ +// -- Misc Registers +// ------------------------------------------------------ +wire [31 :0] testr ; +wire [31 :0] imr ; +wire [31 :0] isr ; +wire [31 :0] misr ; +wire [31 :0] sfrtr ; +wire [0 :0] sfrr ; +wire [0 :0] ch0rstr ; +wire [0 :0] ch1rstr ; +wire [0 :0] ch2rstr ; +wire [0 :0] ch3rstr ; +wire [5 :0] dbgcfgr ; + +reg [31 :0] rddata_reg ; + + +wire dbg_upd_r ; +//ch0 status reg +wire ch0_proc_cft_r ; +wire ch0_ldst_addr_unalgn_r ; +wire ch0_dec_err_r ; +wire ch0_exit_irq_r ; +//ch1 status reg +wire ch1_proc_cft_r ; +wire ch1_dbg_fifo_f_r ; +wire ch1_ldst_addr_unalgn_r ; +wire ch1_dec_err_r ; +wire ch1_exit_irq_r ; +//ch2 status reg +wire ch2_proc_cft_r ; +wire ch2_ldst_addr_unalgn_r ; +wire ch2_dec_err_r ; +wire ch2_exit_irq_r ; +//ch3 status reg +wire ch3_proc_cft_r ; +wire ch3_ldst_addr_unalgn_r ; +wire ch3_dec_err_r ; +wire ch3_exit_irq_r ; + +wire sys_soft_rstn_r ; +wire ch0_soft_rstn_r ; +wire ch1_soft_rstn_r ; +wire ch2_soft_rstn_r ; +wire ch3_soft_rstn_r ; +// ------------------------------------------------------ +// -- Address decoder +// +// Decodes the register address offset input(reg_addr) +// to produce enable (select) signals for each of the +// SW-registers in the macrocell. The reg_addr input +// is bits [8:0] of the paddr bus. +// ------------------------------------------------------ +assign idren = (rwaddr[15:2] == `IDR >> 2) ? 1'b1 : 1'b0; +assign vidren = (rwaddr[15:2] == `VIDR >> 2) ? 1'b1 : 1'b0; +assign dateren = (rwaddr[15:2] == `DATER >> 2) ? 1'b1 : 1'b0; +assign verren = (rwaddr[15:2] == `VERR >> 2) ? 1'b1 : 1'b0; +assign testren = (rwaddr[15:2] == `TESTR >> 2) ? 1'b1 : 1'b0; +assign imren = (rwaddr[15:2] == `IMR >> 2) ? 1'b1 : 1'b0; +assign isren = (rwaddr[15:2] == `ISR >> 2) ? 1'b1 : 1'b0; +assign misren = (rwaddr[15:2] == `MISR >> 2) ? 1'b1 : 1'b0; +assign sfrtren = (rwaddr[15:2] == `SFRTR >> 2) ? 1'b1 : 1'b0; +assign sfrren = (rwaddr[15:2] == `SFRR >> 2) ? 1'b1 : 1'b0; +assign ch0rstren = (rwaddr[15:2] == `CH0RSTR >> 2) ? 1'b1 : 1'b0; +assign ch1rstren = (rwaddr[15:2] == `CH1RSTR >> 2) ? 1'b1 : 1'b0; +assign ch2rstren = (rwaddr[15:2] == `CH2RSTR >> 2) ? 1'b1 : 1'b0; +assign ch3rstren = (rwaddr[15:2] == `CH3RSTR >> 2) ? 1'b1 : 1'b0; +assign dbgcfgren = (rwaddr[15:2] == `DBGCFGR >> 2) ? 1'b1 : 1'b0; + +// ------------------------------------------------------ +// -- Write enable signals +// +// Write enable signals for writable SW-registers. +// The write enable for each register is the ANDed +// result of the register enable and the input reg_wren +// ------------------------------------------------------ +assign testrwe = testren & wren; +assign imrwe = imren & wren; +assign sfrtrwe = sfrtren & wren; +assign sfrrwe = sfrren & wren; +assign ch0rstrwe = ch0rstren & wren; +assign ch1rstrwe = ch1rstren & wren; +assign ch2rstrwe = ch2rstren & wren; +assign ch3rstrwe = ch3rstren & wren; +assign dbgcfgrwe = dbgcfgren & wren; + +// --------------------------------------------------------------------------------------------------- +// -- interrupt Mask Register +// +// Write interrupt Mask for 'imr' : 12-bit register +// Register is split into the following bit fields +// +//Interrupt Mask Register +//[31:29] --> Reserved +//[28 ] --> DBG UPD Interrupt Mask +//[27 ] --> CH3 AWG Conflict nterrupt Mask +//[26 ] --> CH3 LDST ADDR UNALGN Interrupt Mask +//[25 ] --> CH3 DEC ERR Interrupt Mask +//[24 ] --> CH3 EXITI Interrupt Mask +//[23:20] --> Reserved +//[19 ] --> CH2 AWG Conflict nterrupt Mask +//[18 ] --> CH2 LDST ADDR UNALGN Interrupt Mask +//[17 ] --> CH2 DEC ERR Interrupt Mask +//[16 ] --> CH2 EXITI Interrupt Mask +//[15:12] --> Reserved +//[11 ] --> CH1 AWG Conflict nterrupt Mask +//[10 ] --> CH1 LDST ADDR UNALGN Interrupt Mask +//[9 ] --> CH1 DEC ERR Interrupt Mask +//[8 ] --> CH1 EXITI Interrupt Mask +//[7 :4] --> Reserved +//[3 ] --> CH1 AWG Conflict nterrupt Mask +//[2 ] --> CH1 LDST ADDR UNALGN Interrupt Mask +//[1 ] --> CH1 DEC ERR Interrupt Mask +//[0 ] --> CH1 EXITI Interrupt Mask +// --------------------------------------------------------------------------------------------------- +sirv_gnrl_dfflr #(32) imr_dfflr (imrwe, wrdata[31:0], imr, clk, rst_n); + +// ------------------------------------------------------ +// -- testr Register +// +// Write testr for 'TESTR' : 32-bit register +// Register is split into the following bit fields +// +// [31:0] --> testr +// ------------------------------------------------------ +sirv_gnrl_dfflrd #(32) testr_dfflrd (TESTRD, testrwe, wrdata[31:0], testr, clk, rst_n); + + +// ------------------------------------------------------ +// -- Soft Reset Count Register +// +// Write Soft Reset Count for 'sfrtcr' : 6-bit register +// Register is split into the following bit fields +// +// [31:0] --> sfrtcr,default value 32'd300 +// ------------------------------------------------------ +sirv_gnrl_dfflrd #(32) sfrtr_dfflrd (32'd300, sfrtrwe, wrdata[31:0], sfrtr, clk, rst_n);/////////////////////////////sfrtcr-->sfrtr + +// ------------------------------------------------------ +// -- debug config Register +// +// +// [3:0] --> dbgcfgr,default value 4'b0000 +// ------------------------------------------------------ +sirv_gnrl_dfflr #(6) dbgcfgr_dfflr (dbgcfgrwe, wrdata[5:0], dbgcfgr, clk, rst_n); +// ------------------------------------------------------ +// -- soft reset count +// ------------------------------------------------------ + +wire [31:0] cnt_c; + +wire add_cnt = (sys_soft_rstn_r == L) + | (ch0_soft_rstn_r == L) + | (ch1_soft_rstn_r == L) + | (ch2_soft_rstn_r == L) + | (ch3_soft_rstn_r == L); + +wire end_cnt = add_cnt & (cnt_c == sfrtr-1); + +wire [31:0] cnt_n = end_cnt ? 32'h0 : + add_cnt ? cnt_c + 1'b1 : + cnt_c ; + + +sirv_gnrl_dffr #(32) cnt_c_dffr (cnt_n, cnt_c, clk, rst_n); + +// ------------------------------------------------------ +// -- Soft Reset Register +// +// Write Soft Reset for 'sfrtr' : 1-bit register +// Register is split into the following bit fields +// +// [16'h0024] --> System Soft Reset ,low active +// [16'h0028] --> MCU Soft Reset ,low active +// [16'h002C] --> AWG Soft Reset ,low active +// [16'h0030] --> DAC Soft Reset ,low active +// ------------------------------------------------------ + +//sys_soft_rstn_r +wire sys_soft_rstn_en = end_cnt | sfrrwe; +wire sys_soft_rstn_w = end_cnt ? 1'b1 : + sfrrwe ? 1'b0 : + 1'b1 ; +sirv_gnrl_dfflrs #(1) sys_soft_rstn_r_dffls (sys_soft_rstn_en, sys_soft_rstn_w, sys_soft_rstn_r, clk, rst_n); + +//ch0_soft_rstn_r +wire ch0_soft_rstn_en = end_cnt | ch0rstrwe; +wire ch0_soft_rstn_r_w = end_cnt ? 1'b1 : + ch0rstrwe ? 1'b0 : + 1'b1 ; +sirv_gnrl_dfflrs #(1) ch0_soft_rstn_r_dffls (ch0_soft_rstn_en, ch0_soft_rstn_r_w, ch0_soft_rstn_r, clk, rst_n); + +//ch1_soft_rstn_r +wire ch1_soft_rstn_en = end_cnt | ch1rstrwe; +wire ch1_soft_rstn_w = end_cnt ? 1'b1 : + ch1rstrwe ? 1'b0 : + 1'b1 ; +sirv_gnrl_dfflrs #(1) ch1_soft_rstn_r_dffls (ch1_soft_rstn_en, ch1_soft_rstn_w, ch1_soft_rstn_r, clk, rst_n); + +//ch2_soft_rstn_r +wire ch2_soft_rstn_en = end_cnt | ch2rstrwe; +wire ch2_soft_rstn_w = end_cnt ? 1'b1 : + ch2rstrwe ? 1'b0 : + 1'b1 ; +sirv_gnrl_dfflrs #(1) ch2_soft_rstn_r_dffls (ch2_soft_rstn_en, ch2_soft_rstn_w, ch2_soft_rstn_r, clk, rst_n); + +//ch3_soft_rstn_r +wire ch3_soft_rstn_en = end_cnt | ch3rstrwe; +wire ch3_soft_rstn_w = end_cnt ? 1'b1 : + ch3rstrwe ? 1'b0 : + 1'b1 ; +sirv_gnrl_dfflrs #(1) ch3_soft_rstn_r_dffls (ch3_soft_rstn_en, ch3_soft_rstn_w, ch3_soft_rstn_r, clk, rst_n); + + +assign sys_soft_rstn = sys_soft_rstn_r; +assign ch0_soft_rstn = ch0_soft_rstn_r; +assign ch1_soft_rstn = ch1_soft_rstn_r; +assign ch2_soft_rstn = ch2_soft_rstn_r; +assign ch3_soft_rstn = ch3_soft_rstn_r; +// ------------------------------------------------------ +// -- Read data mux +// +// -- The data from the selected register is +// -- placed on a zero-padded 32-bit read data bus. +// ------------------------------------------------------ +always @(*) begin : RDDATA_PROC + rddata_reg = {32{1'b0}}; + if(idren == H ) rddata_reg[31:0] = IDRD; + if(vidren == H ) rddata_reg[31:0] = VIDRD; + if(dateren == H ) rddata_reg[31:0] = DATERD; + if(verren == H ) rddata_reg[31:0] = VERSION; + if(testren == H ) rddata_reg[31:0] = testr; + if(imren == H ) rddata_reg[31:0] = imr; + if(isren == H ) rddata_reg[31:0] = isr; + if(misren == H ) rddata_reg[31:0] = misr; + if(sfrtren == H ) rddata_reg[31:0] = sfrtr; + if(dbgcfgren == H ) rddata_reg[5 :0] = dbgcfgr; +end + +//rddata +sirv_gnrl_dffr #(32) rddata_dffr (rddata_reg, rddata, clk, rst_n); + +// ------------------------------------------------------ +// -- interrupt status +// ------------------------------------------------------ + +//read misr clear interrupts +assign icr = (misren) && rden; + + +//dbg_upd_r +wire dbg_upd_en = icr | dbg_upd; +wire dbg_upd_w = ~icr | dbg_upd; +sirv_gnrl_dfflr #(1) dbg_upd_r_dfflr (dbg_upd_en, dbg_upd_w, dbg_upd_r, clk, rst_n); + +//ch0_proc_cft_r +wire ch0_proc_cft_en = icr | ch0_proc_cft; +wire ch0_proc_cft_w = ~icr | ch0_proc_cft; +sirv_gnrl_dfflr #(1) ch0_proc_cft_r_dfflr (ch0_proc_cft_en, ch0_proc_cft_w, ch0_proc_cft_r, clk, rst_n); + +//ch0_ldst_addr_unalgn_r +wire ch0_ldst_addr_unalgn_en = icr | ch0_ldst_addr_unalgn; +wire ch0_ldst_addr_unalgn_w = ~icr | ch0_ldst_addr_unalgn; +sirv_gnrl_dfflr #(1) ch0_ldst_addr_unalgn_r_dfflr (ch0_ldst_addr_unalgn_en, ch0_ldst_addr_unalgn_w, ch0_ldst_addr_unalgn_r, clk, rst_n); + +//ch0_dec_err_r +wire ch0_dec_err_en = icr | ch0_dec_err; +wire ch0_dec_err_w = ~icr | ch0_dec_err; +sirv_gnrl_dfflr #(1) ch0_dec_err_r_dfflr (ch0_dec_err_en, ch0_dec_err_w, ch0_dec_err_r, clk, rst_n); + +//ch0_exit_irq_r +wire ch0_exit_irq_en = icr | ch0_exit_irq; +wire ch0_exit_irq_w = ~icr | ch0_exit_irq; +sirv_gnrl_dfflr #(1) ch0_exit_irq_r_dfflr (ch0_exit_irq_en, ch0_exit_irq_w, ch0_exit_irq_r, clk, rst_n); + + +//ch1_proc_cft_r +wire ch1_proc_cft_en = icr | ch1_proc_cft; +wire ch1_proc_cft_w = ~icr | ch1_proc_cft; +sirv_gnrl_dfflr #(1) ch1_proc_cft_r_dfflr (ch1_proc_cft_en, ch1_proc_cft_w, ch1_proc_cft_r, clk, rst_n); + +//ch1_ldst_addr_unalgn_r +wire ch1_ldst_addr_unalgn_en = icr | ch1_ldst_addr_unalgn; +wire ch1_ldst_addr_unalgn_w = ~icr | ch1_ldst_addr_unalgn; +sirv_gnrl_dfflr #(1) ch1_ldst_addr_unalgn_r_dfflr (ch1_ldst_addr_unalgn_en, ch1_ldst_addr_unalgn_w, ch1_ldst_addr_unalgn_r, clk, rst_n); + +//ch1_dec_err_r +wire ch1_dec_err_en = icr | ch1_dec_err; +wire ch1_dec_err_w = ~icr | ch1_dec_err; +sirv_gnrl_dfflr #(1) ch1_dec_err_r_dfflr (ch1_dec_err_en, ch1_dec_err_w, ch1_dec_err_r, clk, rst_n); + +//ch1_exit_irq_r +wire ch1_exit_irq_en = icr | ch1_exit_irq; +wire ch1_exit_irq_w = ~icr | ch1_exit_irq; +sirv_gnrl_dfflr #(1) ch1_exit_irq_r_dfflr (ch1_exit_irq_en, ch1_exit_irq_w, ch1_exit_irq_r, clk, rst_n); + +//ch2_proc_cft_r +wire ch2_proc_cft_en = icr | ch2_proc_cft; +wire ch2_proc_cft_w = ~icr | ch2_proc_cft; +sirv_gnrl_dfflr #(1) ch2_proc_cft_r_dfflr (ch2_proc_cft_en, ch2_proc_cft_w, ch2_proc_cft_r, clk, rst_n); + +//ch2_ldst_addr_unalgn_r +wire ch2_ldst_addr_unalgn_en = icr | ch2_ldst_addr_unalgn; +wire ch2_ldst_addr_unalgn_w = ~icr | ch2_ldst_addr_unalgn; +sirv_gnrl_dfflr #(1) ch2_ldst_addr_unalgn_r_dfflr (ch2_ldst_addr_unalgn_en, ch2_ldst_addr_unalgn_w, ch2_ldst_addr_unalgn_r, clk, rst_n); + +//ch2_dec_err_r +wire ch2_dec_err_en = icr | ch2_dec_err; +wire ch2_dec_err_w = ~icr | ch2_dec_err; +sirv_gnrl_dfflr #(1) ch2_dec_err_r_dfflr (ch2_dec_err_en, ch2_dec_err_w, ch2_dec_err_r, clk, rst_n); + +//ch2_exit_irq_r +wire ch2_exit_irq_en = icr | ch2_exit_irq; +wire ch2_exit_irq_w = ~icr | ch2_exit_irq; +sirv_gnrl_dfflr #(1) ch2_exit_irq_r_dfflr (ch2_exit_irq_en, ch2_exit_irq_w, ch2_exit_irq_r, clk, rst_n); + +//ch3_proc_cft_r +wire ch3_proc_cft_en = icr | ch3_proc_cft; +wire ch3_proc_cft_w = ~icr | ch3_proc_cft; +sirv_gnrl_dfflr #(1) ch3_proc_cft_r_dfflr (ch3_proc_cft_en, ch3_proc_cft_w, ch3_proc_cft_r, clk, rst_n); + +//ch3_ldst_addr_unalgn_r +wire ch3_ldst_addr_unalgn_en = icr | ch3_ldst_addr_unalgn; +wire ch3_ldst_addr_unalgn_w = ~icr | ch3_ldst_addr_unalgn; +sirv_gnrl_dfflr #(1) ch3_ldst_addr_unalgn_r_dfflr (ch3_ldst_addr_unalgn_en, ch3_ldst_addr_unalgn_w, ch3_ldst_addr_unalgn_r, clk, rst_n); + +//ch3_dec_err_r +wire ch3_dec_err_en = icr | ch3_dec_err; +wire ch3_dec_err_w = ~icr | ch3_dec_err; +sirv_gnrl_dfflr #(1) ch3_dec_err_r_dfflr (ch3_dec_err_en, ch3_dec_err_w, ch3_dec_err_r, clk, rst_n); + +//ch3_exit_irq_r +wire ch3_exit_irq_en = icr | ch3_exit_irq; +wire ch3_exit_irq_w = ~icr | ch3_exit_irq; +sirv_gnrl_dfflr #(1) ch3_exit_irq_r_dfflr (ch3_exit_irq_en, ch3_exit_irq_w, ch3_exit_irq_r, clk, rst_n); + +//irisr +assign irisr[31] = L ; +assign irisr[30] = L ; +assign irisr[29] = L ; +assign irisr[28] = dbg_upd_r ; +assign irisr[27] = ch3_proc_cft_r ; +assign irisr[26] = ch3_ldst_addr_unalgn_r ; +assign irisr[25] = ch3_dec_err_r ; +assign irisr[24] = ch3_exit_irq_r ; +assign irisr[23] = L ; +assign irisr[22] = L ; +assign irisr[21] = L ; +assign irisr[20] = L ; +assign irisr[19] = ch2_proc_cft_r ; +assign irisr[18] = ch2_ldst_addr_unalgn_r ; +assign irisr[17] = ch2_dec_err_r ; +assign irisr[16] = ch2_exit_irq_r ; +assign irisr[15] = L ; +assign irisr[14] = L ; +assign irisr[13] = L ; +assign irisr[12] = L ; +assign irisr[11] = ch1_proc_cft_r ; +assign irisr[10] = ch1_ldst_addr_unalgn_r ; +assign irisr[9 ] = ch1_dec_err_r ; +assign irisr[8 ] = ch1_exit_irq_r ; +assign irisr[7 ] = L ; +assign irisr[6 ] = L ; +assign irisr[5 ] = L ; +assign irisr[4 ] = L ; +assign irisr[3 ] = ch0_proc_cft_r ; +assign irisr[2 ] = ch0_ldst_addr_unalgn_r ; +assign irisr[1 ] = ch0_dec_err_r ; +assign irisr[0 ] = ch0_exit_irq_r ; + +// ------------------------------------------------------ +// -- Interrupt Status Register - Read Only +// +// This register contains the status of all +// XYZ Chip interrupts after masking. +// ------------------------------------------------------ +sirv_gnrl_dffr #(32) isr_dffr (irisr, isr, clk, rst_n); + +//misr +wire[31:0] misr_w = imr & irisr; +sirv_gnrl_dffr #(32) misr_dffr (misr_w, misr, clk, rst_n); + +//irq +wire irq_w = |misr; +sirv_gnrl_dffr #(1) irq_dffr (irq_w, irq, clk, rst_n); + +//debug cfg + +assign dbg_enable = dbgcfgr[0]; +assign dbg_data_sel = dbgcfgr[1]; +assign dbg_ch_sel = dbgcfgr[5:2]; + +endmodule + + +`undef IDR +`undef VIDR +`undef DATER +`undef VERR +`undef TESTR +`undef IMR +`undef ISR +`undef MISR +`undef SFRTR +`undef SFRR +`undef CH0RSTR +`undef CH1RSTR +`undef CH2RSTR +`undef CH3RSTR +`undef DBGCFGR diff --git a/rtl/top/channel_top.sv b/rtl/top/channel_top.sv new file mode 100644 index 0000000..3d70dc6 --- /dev/null +++ b/rtl/top/channel_top.sv @@ -0,0 +1,633 @@ +//+FHDR-------------------------------------------------------------------------------------------------------- +// Company: +//----------------------------------------------------------------------------------------------------------------- +// File Name : channel_top.v +// Department : +// Author : pwy +// Author's Tel : +//----------------------------------------------------------------------------------------------------------------- +// Relese History +// Version Date Author Description +// 1.2 2024-04-16 pwy XYZ channel the top-level module +//----------------------------------------------------------------------------------------------------------------- +// Keywords : +// +//----------------------------------------------------------------------------------------------------------------- +// Parameter +// +//----------------------------------------------------------------------------------------------------------------- +// Purpose : +// +//----------------------------------------------------------------------------------------------------------------- +// Target Device: +// Tool versions: +//----------------------------------------------------------------------------------------------------------------- +// Reuse Issues +// Reset Strategy: +// Clock Domains: +// Critical Timing: +// Asynchronous I/F: +// Synthesizable (y/n): +// Other: +//-FHDR------------------------------------------------------------------------------------------------------------ +`include "../define/chip_define.v" +`include "../qubitmcu/qbmcu_defines.v" +module channel_top ( +//system port + input clk + ,input rst_n + //Sync Start + ,input sync_int + //Decoded port + ,output dec_o_ilegl + //Misaligned memory address + ,output agu_o_addr_unalgn + // + ,output awg_proc_cft + ,output mcu_ext_o_intr + //Feedback signal from the readout chip + ,input [1 :0] fb_st_in + //ITCM + ,input [`QBMCU_DTCM_ADDR_SIZE-1 :0] itcm_i_rwaddr + ,input [`QBMCU_XLEN-1 :0] itcm_i_wrdata + ,input itcm_i_wren + ,input [`QBMCU_XLEN/8-1 :0] itcm_i_wrmask + ,input itcm_i_rden + ,output [`QBMCU_XLEN-1 :0] itcm_o_rddata + //DTCM + ,input [`QBMCU_DTCM_ADDR_SIZE-1 :0] dtcm_i_rwaddr + ,input [`QBMCU_XLEN-1 :0] dtcm_i_wrdata + ,input dtcm_i_wren + ,input [`QBMCU_XLEN/8-1 :0] dtcm_i_wrmask + ,input dtcm_i_rden + ,output [`QBMCU_XLEN-1 :0] dtcm_o_rddata + //ctrl regfile + ,input [31 :0] ctrl_wrdata + ,input ctrl_wren + ,input [15 :0] ctrl_rwaddr + ,input ctrl_rden + ,output [31 :0] ctrl_rddata + //Envelope storage read/write signal + ,input [31 :0] enve_bwrdata + ,input [0 :0] enve_bwren + ,input [14 :0] enve_brwaddr + ,input [0 :0] enve_brden + ,output [31 :0] enve_brddata + //envelope index lookup table read-write signal + ,input [31 :0] enve_id_bwrdata + ,input [0 :0] enve_id_bwren + ,input [7 :0] enve_id_brwaddr + ,input [0 :0] enve_id_brden + ,output [31 :0] enve_id_brddata + //DAC cfg + //dac regfile + ,input [31 :0] dac_wrdata + ,input dac_wren + ,input [15 :0] dac_rwaddr + ,input dac_rden + ,output [31 :0] dac_rddata + ,output dac_Prbs + ,output [14 :0] dac_Set0 + ,output [14 :0] dac_Set1 + ,output [14 :0] dac_Set2 + ,output [14 :0] dac_Set3 + ,output [14 :0] dac_Set4 + ,output [14 :0] dac_Set5 + ,output [14 :0] dac_Set6 + ,output [14 :0] dac_Set7 + ,output [14 :0] dac_Set8 + ,output [14 :0] dac_Set9 + ,output [14 :0] dac_Set10 + ,output [14 :0] dac_Set11 + ,output [14 :0] dac_Set12 + ,output [14 :0] dac_Set13 + ,output [14 :0] dac_Set14 + ,output [14 :0] dac_Set15 + ,output [2 :0] dac_addr + ,output [2 :0] dac_dw + ,output [8 :0] dac_ref + ,output [16 :0] dac_Prbs_rst0 + ,output [16 :0] dac_Prbs_set0 + ,output [16 :0] dac_Prbs_rst1 + ,output [16 :0] dac_Prbs_set1 + ,output dac_Cal_sig + ,output dac_Cal_rstn + ,output Cal_div_rstn + ,input dac_Cal_end + //awg data output + ,output [15 :0] awg_data_i_o + ,output [15 :0] awg_data_q_o + ,output awg_vld_o + `ifdef CHANNEL_XY_ON + //dsp data output + ,output [15 :0] xy_dsp_dout0 + ,output [15 :0] xy_dsp_dout1 + ,output [15 :0] xy_dsp_dout2 + ,output [15 :0] xy_dsp_dout3 + ,output [15 :0] xy_dsp_dout4 + ,output [15 :0] xy_dsp_dout5 + ,output [15 :0] xy_dsp_dout6 + ,output [15 :0] xy_dsp_dout7 + ,output [15 :0] xy_dsp_dout8 + ,output [15 :0] xy_dsp_dout9 + ,output [15 :0] xy_dsp_dout10 + ,output [15 :0] xy_dsp_dout11 + ,output [15 :0] xy_dsp_dout12 + ,output [15 :0] xy_dsp_dout13 + ,output [15 :0] xy_dsp_dout14 + ,output [15 :0] xy_dsp_dout15 + ,output xy_dsp_dout_vld + `endif + `ifdef CHANNEL_Z_ON + //Z dsp output + ,output [15 :0] z_dsp_dout0 + ,output [15 :0] z_dsp_dout1 + ,output [15 :0] z_dsp_dout2 + ,output [15 :0] z_dsp_dout3 + `endif + + + ); + + +//--------------------------------------------------------------------------------------------- +// qbmcu instantiation start +//--------------------------------------------------------------------------------------------- +wire [`QBMCU_PC_SIZE-1 :0] ifu_i_pc_rtvec = 32'h0 ; +wire [`QBMCU_PC_SIZE-1 :0] ifu_o_req_pc ; +wire ifu_o_req ; +wire [`QBMCU_INSTR_SIZE-1:0] ifu_rsp_instr ; + +wire [`QBMCU_ADDR_SIZE-1 :0] agu_o_addr ; +wire [`QBMCU_XLEN-1 :0] agu_o_wrdata ; +wire agu_o_wren ; +wire [`QBMCU_XLEN/8-1 :0] agu_o_wrmask ; +wire agu_o_rden ; +wire [`QBMCU_XLEN-1 :0] agu_i_rddata ; + +wire ext_o_send ; +wire ext_o_sendc ; +wire [`QBMCU_XLEN-1 :0] ext_o_codeword ; +wire [2 :0] qbmcu_o_fsm_st ; + +qbmcu U_qbmcu ( + .clk ( clk ) + ,.rst_n ( rst_n ) + ,.qbmcu_i_start ( sync_int ) + ,.qbmcu_o_fsm_st ( qbmcu_o_fsm_st ) + ,.ifu_i_pc_rtvec ( ifu_i_pc_rtvec ) + ,.ifu_o_req_pc ( ifu_o_req_pc ) + ,.ifu_o_req ( ifu_o_req ) + ,.ifu_rsp_instr ( ifu_rsp_instr ) + ,.dec_o_ilegl ( dec_o_ilegl ) + ,.agu_o_addr ( agu_o_addr ) + ,.agu_o_wrdata ( agu_o_wrdata ) + ,.agu_o_wren ( agu_o_wren ) + ,.agu_o_wrmask ( agu_o_wrmask ) + ,.agu_o_rden ( agu_o_rden ) + ,.agu_i_rddata ( agu_i_rddata ) + ,.agu_o_addr_unalgn ( agu_o_addr_unalgn ) + ,.ext_o_send ( ext_o_send ) + ,.ext_o_sendc ( ext_o_sendc ) + ,.ext_o_codeword ( ext_o_codeword ) + ,.ext_o_intr ( mcu_ext_o_intr ) + ); +//--------------------------------------------------------------------------------------------- +// qbmcu instantiation end +//--------------------------------------------------------------------------------------------- + + +//--------------------------------------------------------------------------------------------- +// MCU runtime counter instantiation start +//--------------------------------------------------------------------------------------------- +defparam qbmcu_runtime.width = 32; +//MCU runtime +wire [31 :0] run_time ; +DW03_updn_ctr qbmcu_runtime ( + .clk ( clk ) // clock input + ,.reset ( rst_n ) // asynchronous reset input (active low) + ,.data ( 32'd0 ) // data used for load operation + ,.up_dn ( 1'b1 ) // up/down control input (0=down, 1-up) + ,.load ( ~sync_int ) // load operation control input (active low) + ,.cen ( |qbmcu_o_fsm_st ) // count enable control input (active high enable) + ,.count ( run_time ) // count value output + ,.tercnt ( ) // terminal count output flag (active high) + ); +//--------------------------------------------------------------------------------------------- +// MCU runtime counter instantiation end +//--------------------------------------------------------------------------------------------- + +//--------------------------------------------------------------------------------------------- +// fetch instructions number counter instantiation start +//--------------------------------------------------------------------------------------------- +defparam instrnum.width = 32; +//Count the number of fetch instructions +wire [31 :0] instr_num ; +DW03_updn_ctr instrnum ( + .clk ( clk ) // clock input + ,.reset ( rst_n ) // asynchronous reset input (active low) + ,.data ( 32'd0 ) // data used for load operation + ,.up_dn ( 1'b1 ) // up/down control input (0=down, 1-up) + ,.load ( ~sync_int ) // load operation control input (active low) + ,.cen ( ifu_o_req ) // count enable control input (active high enable) + ,.count ( instr_num ) // count value output + ,.tercnt ( ) // terminal count output flag (active high) + ); +//--------------------------------------------------------------------------------------------- +// fetch instructions number counter instantiation end +//--------------------------------------------------------------------------------------------- + + +//--------------------------------------------------------------------------------------------- +// qbmcu_busdecoder instantiation start +//--------------------------------------------------------------------------------------------- + +wire [`QBMCU_ADDR_SIZE-1 :0] dsram_o_rwaddr ; +wire [`QBMCU_XLEN-1 :0] dsram_o_wrdata ; +wire dsram_o_wren ; +wire [`QBMCU_XLEN/8-1 :0] dsram_o_wrmask ; +wire dsram_o_rden ; +wire [`QBMCU_XLEN-1 :0] dsram_i_rddata ; +wire [`QBMCU_ADDR_SIZE-1 :0] preg_o_rwaddr ; +wire [`QBMCU_XLEN-1 :0] preg_o_wrdata ; +wire preg_o_wren ; +wire [`QBMCU_XLEN/8-1 :0] preg_o_wrmask ; +wire preg_o_rden ; +wire [`QBMCU_XLEN-1 :0] preg_i_rddata ; + +qbmcu_busdecoder #( + .S0_BASEADDR ( 32'h0010_0000 ) + ,.S1_BASEADDR ( 32'h0020_0000 ) + )U_qbmcu_busdecoder ( + .wren ( agu_o_wren ) + ,.wrmask ( agu_o_wrmask ) + ,.wrdata ( agu_o_wrdata ) + ,.rwaddr ( agu_o_addr ) + ,.rden ( agu_o_rden ) + ,.rddata ( agu_i_rddata ) + ,.s0_wren ( dsram_o_wren ) + ,.s0_wrmask ( dsram_o_wrmask ) + ,.s0_rwaddr ( dsram_o_rwaddr ) + ,.s0_wrdata ( dsram_o_wrdata ) + ,.s0_rden ( dsram_o_rden ) + ,.s0_rddata ( dsram_i_rddata ) + ,.s1_wren ( preg_o_wren ) + ,.s1_wrmask ( preg_o_wrmask ) + ,.s1_rwaddr ( preg_o_rwaddr ) + ,.s1_wrdata ( preg_o_wrdata ) + ,.s1_rden ( preg_o_rden ) + ,.s1_rddata ( preg_i_rddata ) +); + +//--------------------------------------------------------------------------------------------- +// qbmcu_busdecoder instantiation end +//--------------------------------------------------------------------------------------------- + +//--------------------------------------------------------------------------------------------- +// mcu_regfile instantiation start +//--------------------------------------------------------------------------------------------- + + //MCU and SPI interface for interaction +wire [31 :0] mcu_param [3:0] ; // MCU parameter 0~3 +wire [31 :0] mcu_result [3:0] ; // MCU result 0~3 +//lookup table data ; +wire [31 :0] mcu_cwfr [3:0] ; // Carrier frequency ctrl word 0~3 +wire [15 :0] mcu_gapr [7:0] ; // Carrier phase ctrl word 0~3 +wire [15 :0] mcu_ampr [3:0] ; // Carrier Amplitude 0~3 +wire [15 :0] mcu_baisr [3:0] ; // Carrier Bais 0~3 +//CFG Port +wire mcu_nco_pha_clr ; +wire [15 :0] mcu_rz_pha ; + +wire [1:0] fb_st_in_s; +syncer #(2, 2) fb_st_in_syncer (clk, rst_n, fb_st_in, fb_st_in_s); + +mcu_regfile U_mcu_regfile ( + .clk ( clk ) + ,.rst_n ( rst_n ) + ,.rwaddr ( preg_o_rwaddr[15:0] ) + ,.wrdata ( preg_o_wrdata ) + ,.wren ( preg_o_wren ) + ,.wrmask ( preg_o_wrmask ) + ,.rden ( preg_o_rden ) + ,.rddata ( preg_i_rddata ) + ,.fb_st_info ( fb_st_in_s ) + ,.run_time ( run_time ) + ,.instr_num ( instr_num ) + ,.mcu_param ( mcu_param ) + ,.mcu_result ( mcu_result ) + ,.mcu_cwfr ( mcu_cwfr ) + ,.mcu_gapr ( mcu_gapr ) + ,.mcu_ampr ( mcu_ampr ) + ,.mcu_baisr ( mcu_baisr ) + ,.mcu_nco_pha_clr ( mcu_nco_pha_clr ) + ,.mcu_rz_pha ( mcu_rz_pha ) +); +//--------------------------------------------------------------------------------------------- +// mcu_regfile instantiation end +//--------------------------------------------------------------------------------------------- + +//--------------------------------------------------------------------------------------------- +// U_ITCM instantiation start +//--------------------------------------------------------------------------------------------- +wire itcm_portb_wen = ~itcm_i_wren & itcm_i_rden; +wire itcm_portb_cen = ~(itcm_i_wren | itcm_i_rden); +dpram #( + .DATAWIDTH ( 32 ) + ,.ADDRWIDTH ( 15 ) + ) U_ITCM ( + .PortClk ( clk ) + ,.PortAAddr ( ifu_o_req_pc[`QBMCU_ITCM_ADDR_SIZE-1:0] ) + ,.PortADataIn ( 32'b0 ) + ,.PortAWriteEnable ( 1'b1 ) + ,.PortAChipEnable ( ~ifu_o_req ) + ,.PortAByteWriteEnable ( 4'b0 ) + ,.PortADataOut ( ifu_rsp_instr ) + ,.PortBAddr ( itcm_i_rwaddr[14:0] ) + ,.PortBDataIn ( itcm_i_wrdata ) + ,.PortBWriteEnable ( itcm_portb_wen ) + ,.PortBChipEnable ( itcm_portb_cen ) + ,.PortBByteWriteEnable ( itcm_i_wrmask ) + ,.PortBDataOut ( itcm_o_rddata ) +); +//--------------------------------------------------------------------------------------------- +// U_ITCM instantiation end +//--------------------------------------------------------------------------------------------- + +//////////////////////////////////////////////////////////////////////////////////////////////////////////// +//DTCM +//////////////////////////////////////////////////////////////////////////////////////////////////////////// + +wire dtcm_portb_wen = ~dtcm_i_wren & dtcm_i_rden; +wire dtcm_portb_cen = ~(dtcm_i_wren | dtcm_i_rden); + +dpram #( + .DATAWIDTH ( 32 ) + ,.ADDRWIDTH ( 15 ) + ) U_DTCM ( + .PortClk ( clk ) + ,.PortAAddr ( dsram_o_rwaddr[`QBMCU_DTCM_ADDR_SIZE-1:0] ) + ,.PortADataIn ( dsram_o_wrdata ) + ,.PortAWriteEnable ( ~dsram_o_wren ) + ,.PortAChipEnable ( ~(dsram_o_rden | dsram_o_wren) ) + ,.PortAByteWriteEnable ( ~dsram_o_wrmask ) + ,.PortADataOut ( dsram_i_rddata ) + ,.PortBAddr ( dtcm_i_rwaddr[14:0] ) + ,.PortBDataIn ( dtcm_i_wrdata ) + ,.PortBWriteEnable ( dtcm_portb_wen ) + ,.PortBChipEnable ( dtcm_portb_cen ) + ,.PortBByteWriteEnable ( dtcm_i_wrmask ) + ,.PortBDataOut ( dtcm_o_rddata ) +); + +//--------------------------------------------------------------------------------------------- +// ctrl_regfile instantiation start +//--------------------------------------------------------------------------------------------- +wire [1 :0] fb_st_int ; +//awg cfg +wire mod_sel_sideband ; +//DSP cfg +wire qam_nco_sclr_en ; +wire qam_nco_clr ; +wire [47 :0] qam_fcw ; +wire [15 :0] qam_pha ; +wire [1 :0] qam_mod ; +wire qam_sel_sideband ; +wire [2 :0] intp_mode ; +wire [1 :0] role_sel ; +wire [1 :0] dac_mode_sel ; +wire enve_read_fsm_st ; + +wire bais_i_ov ; +wire bais_q_ov ; +wire dout_sel ; + +wire dsp_alwayson ; + +wire mod_dout_sel = dout_sel ; + + + +ctrl_regfile U_ctrl_regfile ( + .clk ( clk ) + ,.rst_n ( rst_n ) + ,.wrdata ( ctrl_wrdata ) + ,.wren ( ctrl_wren ) + ,.rwaddr ( ctrl_rwaddr ) + ,.rden ( ctrl_rden ) + ,.rddata ( ctrl_rddata ) + ,.fb_st_i ( fb_st_in_s ) + ,.run_time ( run_time ) + ,.instr_num ( instr_num ) + ,.bais_i_ov ( bais_i_ov ) + ,.bais_q_ov ( bais_q_ov ) + ,.awg_ctrl_fsm_st ( enve_read_fsm_st ) + ,.mcu_param0 ( mcu_param[0] ) + ,.mcu_param1 ( mcu_param[1] ) + ,.mcu_param2 ( mcu_param[2] ) + ,.mcu_param3 ( mcu_param[3] ) + ,.mcu_result0 ( mcu_result[0] ) + ,.mcu_result1 ( mcu_result[1] ) + ,.mcu_result2 ( mcu_result[2] ) + ,.mcu_result3 ( mcu_result[3] ) + ,.fb_st_o ( fb_st_int ) + ,.mod_sel_sideband ( mod_sel_sideband ) + ,.qam_nco_clr ( qam_nco_clr ) + ,.qam_nco_sclr_en ( qam_nco_sclr_en ) + ,.qam_fcw ( qam_fcw ) + ,.qam_pha ( qam_pha ) + ,.qam_mod ( qam_mod ) + ,.qam_sel_sideband ( qam_sel_sideband ) + ,.intp_mode ( intp_mode ) + ,.role_sel ( role_sel ) + ,.dout_sel ( dout_sel ) + ,.dac_mode_sel ( dac_mode_sel ) + ,.dsp_alwayson ( dsp_alwayson ) +); +//--------------------------------------------------------------------------------------------- +// ctrl_regfile instantiation end +//--------------------------------------------------------------------------------------------- + +//--------------------------------------------------------------------------------------------- +// awg_top instantiation start +//--------------------------------------------------------------------------------------------- + +wire [15 :0] awg_data_i ; +wire [15 :0] awg_data_q ; +wire awg_vld ; +wire mod_pha_sfot_clr = ~rst_n; + +assign awg_data_i_o = awg_data_i ; +assign awg_data_q_o = awg_data_q ; +assign awg_vld_o = awg_vld ; + +awg_top U_awg_top ( + .clk ( clk ) + ,.rst_n ( rst_n ) + ,.mcu_cwfr ( mcu_cwfr ) + ,.mcu_gapr ( mcu_gapr ) + ,.mcu_ampr ( mcu_ampr ) + ,.mcu_baisr ( mcu_baisr ) + ,.mcu_nco_pha_clr ( mcu_nco_pha_clr ) + ,.mcu_rz_pha ( mcu_rz_pha ) + ,.send ( ext_o_send ) + ,.sendc ( ext_o_sendc ) + ,.codeword ( ext_o_codeword ) + ,.fb_st ( fb_st_int ) + ,.enve_bwrdata ( enve_bwrdata ) + ,.enve_bwren ( enve_bwren ) + ,.enve_brwaddr ( enve_brwaddr ) + ,.enve_brden ( enve_brden ) + ,.enve_brddata ( enve_brddata ) + ,.enve_id_bwrdata ( enve_id_bwrdata ) + ,.enve_id_bwren ( enve_id_bwren ) + ,.enve_id_brwaddr ( enve_id_brwaddr ) + ,.enve_id_brden ( enve_id_brden ) + ,.enve_id_brddata ( enve_id_brddata ) + ,.enve_read_fsm_st ( enve_read_fsm_st ) + ,.proc_cft ( awg_proc_cft ) + ,.mod_sideband_sel ( mod_sel_sideband ) + ,.mod_pha_sfot_clr ( mod_pha_sfot_clr ) + ,.role_sel ( role_sel ) + ,.mod_dout_sel ( mod_dout_sel ) + ,.awg_data_i ( awg_data_i ) + ,.awg_data_q ( awg_data_q ) + ,.awg_vld ( awg_vld ) + ,.bais_i_ov ( bais_i_ov ) + ,.bais_q_ov ( bais_q_ov ) + ); + +//--------------------------------------------------------------------------------------------- +// awg_top instantiation end +//--------------------------------------------------------------------------------------------- + +`ifdef CHANNEL_XY_ON +//--------------------------------------------------------------------------------------------- +// xy's dsp instantiation start +//--------------------------------------------------------------------------------------------- + +wire qam_anco_clr = qam_nco_sclr_en ? ~sync_int : 1'b0; + +wire mix_enable = ~(role_sel[1]); + +xy_dsp U_xy_dsp ( + .clk ( clk ) + ,.rstn ( rst_n ) + ,.phase_manual_clr ( qam_nco_clr ) + ,.phase_auto_clr ( qam_anco_clr ) + ,.fcw ( qam_fcw ) + ,.pha ( qam_pha ) + ,.qam_mod ( qam_mod ) + ,.sel_sideband ( qam_sel_sideband ) + ,.intp_mode ( intp_mode ) + ,.dac_mode_sel ( dac_mode_sel ) + ,.mix_enable ( mix_enable ) + ,.dsp_alwayson ( dsp_alwayson ) + ,.din_i ( awg_data_i ) + ,.din_q ( awg_data_q ) + ,.din_vld ( awg_vld ) + ,.dout0 ( xy_dsp_dout0 ) + ,.dout1 ( xy_dsp_dout1 ) + ,.dout2 ( xy_dsp_dout2 ) + ,.dout3 ( xy_dsp_dout3 ) + ,.dout4 ( xy_dsp_dout4 ) + ,.dout5 ( xy_dsp_dout5 ) + ,.dout6 ( xy_dsp_dout6 ) + ,.dout7 ( xy_dsp_dout7 ) + ,.dout8 ( xy_dsp_dout8 ) + ,.dout9 ( xy_dsp_dout9 ) + ,.dout10 ( xy_dsp_dout10 ) + ,.dout11 ( xy_dsp_dout11 ) + ,.dout12 ( xy_dsp_dout12 ) + ,.dout13 ( xy_dsp_dout13 ) + ,.dout14 ( xy_dsp_dout14 ) + ,.dout15 ( xy_dsp_dout15 ) + ,.dout_vld ( xy_dsp_dout_vld ) + ); +//--------------------------------------------------------------------------------------------- +// xy's dsp instantiation end +//--------------------------------------------------------------------------------------------- +`endif + +`ifdef CHANNEL_Z_ON +//--------------------------------------------------------------------------------------------- +// z_data_mux instantiation start +//--------------------------------------------------------------------------------------------- + +wire z_dout_sel = dout_sel; + + +wire [15:0] z_dsp_data0 = 16'h0000; +wire [15:0] z_dsp_data1 = 16'h0000; +wire [15:0] z_dsp_data2 = 16'h0000; +wire [15:0] z_dsp_data3 = 16'h0000; + +z_data_mux U_z_data_mux ( + .clk ( clk ) + ,.rst_n ( rst_n ) + ,.sel ( z_dout_sel ) + ,.z_dsp_data0 ( z_dsp_data0 ) + ,.z_dsp_data1 ( z_dsp_data1 ) + ,.z_dsp_data2 ( z_dsp_data2 ) + ,.z_dsp_data3 ( z_dsp_data3 ) + ,.xy_dsp_data0 ( xy_dsp_dout0 ) + ,.xy_dsp_data1 ( xy_dsp_dout1 ) + ,.xy_dsp_data2 ( xy_dsp_dout2 ) + ,.xy_dsp_data3 ( xy_dsp_dout3 ) + ,.mux_data_0 ( z_dsp_dout0 ) + ,.mux_data_1 ( z_dsp_dout1 ) + ,.mux_data_2 ( z_dsp_dout2 ) + ,.mux_data_3 ( z_dsp_dout3 ) +); + +//--------------------------------------------------------------------------------------------- +// z_data_mux instantiation end +//--------------------------------------------------------------------------------------------- +`endif + +//--------------------------------------------------------------------------------------------- +//dac_regfile instantiation start +//--------------------------------------------------------------------------------------------- + +dac_regfile U_ch0_dac_regfile ( + .clk ( clk ) + ,.rstn ( rst_n ) + ,.wrdata ( dac_wrdata ) + ,.wren ( dac_wren ) + ,.rwaddr ( dac_rwaddr ) + ,.rden ( dac_rden ) + ,.rddata ( dac_rddata ) + ,.Prbs ( dac_Prbs ) + ,.Set0 ( dac_Set0 ) + ,.Set1 ( dac_Set1 ) + ,.Set2 ( dac_Set2 ) + ,.Set3 ( dac_Set3 ) + ,.Set4 ( dac_Set4 ) + ,.Set5 ( dac_Set5 ) + ,.Set6 ( dac_Set6 ) + ,.Set7 ( dac_Set7 ) + ,.Set8 ( dac_Set8 ) + ,.Set9 ( dac_Set9 ) + ,.Set10 ( dac_Set10 ) + ,.Set11 ( dac_Set11 ) + ,.Set12 ( dac_Set12 ) + ,.Set13 ( dac_Set13 ) + ,.Set14 ( dac_Set14 ) + ,.Set15 ( dac_Set15 ) + ,.Dac_addr ( dac_addr ) + ,.Dac_dw ( dac_dw ) + ,.Dac_ref ( dac_ref ) + ,.Prbs_rst0 ( dac_Prbs_rst0 ) + ,.Prbs_set0 ( dac_Prbs_set0 ) + ,.Prbs_rst1 ( dac_Prbs_rst1 ) + ,.Prbs_set1 ( dac_Prbs_set1 ) + ,.Cal_sig ( dac_Cal_sig ) + ,.Cal_end ( dac_Cal_end ) + ,.Cal_rstn ( dac_Cal_rstn ) + ,.Cal_div_rstn ( Cal_div_rstn ) +); + +endmodule + +`include "../define/chip_undefine.v" +`include "../qubitmcu/qbmcu_undefines.v" diff --git a/rtl/top/digital_top.sv b/rtl/top/digital_top.sv new file mode 100644 index 0000000..eed529b --- /dev/null +++ b/rtl/top/digital_top.sv @@ -0,0 +1,1294 @@ +//+FHDR-------------------------------------------------------------------------------------------------------- +// Company: +//----------------------------------------------------------------------------------------------------------------- +// File Name : digital_top.v +// Department : +// Author : pwy +// Author's Tel : +//----------------------------------------------------------------------------------------------------------------- +// Relese History +// Version Date Author Description +// 1.2 2024-04-16 pwy XYZ control the top-level module +//----------------------------------------------------------------------------------------------------------------- +// Keywords : +// +//----------------------------------------------------------------------------------------------------------------- +// Parameter +// +//----------------------------------------------------------------------------------------------------------------- +// Purpose : +// +//----------------------------------------------------------------------------------------------------------------- +// Target Device: +// Tool versions: +//----------------------------------------------------------------------------------------------------------------- +// Reuse Issues +// Reset Strategy: +// Clock Domains: +// Critical Timing: +// Asynchronous I/F: +// Synthesizable (y/n): +// Other: +//-FHDR-------------------------------------------------------------------------------------------------------- + +`include "../define/chip_define.v" + +module digital_top ( + //-------------------------clcok pin from pll------------------------------------------------- + input clk // System Main Clock + //-------------------------Power on reset pin from por---------------------------------------- + ,input por_rstn // Power on reset, active low + //------------------------------digital IO---------------------------------------------------- + + ,input async_rstn // hardware Reset, active low + //sync + ,input sync_in // Chip synchronization signal input, high pulse valid + ,output sync_out // Chip synchronization signal output, high pulse valid + //Feedback signal + ,input [1 :0] ch0_feedback // Ch0 Feedback signals from the readout chip + `ifdef CHANNEL_IS_FOUR + ,input [1 :0] ch1_feedback // Ch1 Feedback signals from the readout chip + ,input [1 :0] ch2_feedback // Ch2 Feedback signals from the readout chip + ,input [1 :0] ch3_feedback // Ch3 Feedback signals from the readout chip + `endif + //config chip id + ,input [4 :0] cfgid // During power-on initialization, the IO configuration + // values are read as the chip ID number + //spi port + ,input sclk // Spi Clock + ,input csn // Spi Chip Select active low + ,input mosi // Spi Mosi + ,output miso // Spi Miso + ,output oen // Spi Miso output enable + //irq + ,output irq // Interrupt signal in the chip, high level active + //------------------------------PLL cfg pin---------------------------------------------------- + ,output ref_sel // Clock source selection for a frequency divider; + // 1'b0:External clock source + // 1'b1:internal phase-locked loop clock source + ,output ref_en // Input reference clock enable + // 1'b0:enable,1'b1:disable + ,output ref_s2d_en // Referenced clock differential to single-ended conversion enable + // 1'b0:enable,1'b1:disable + ,output [6 :0] p_cnt // P counter + ,output pfd_delay // PFD Dead Zone + ,output pfd_dff_Set // Setting the PFD register,active high + ,output pfd_dff_4and // PFD output polarity + ,output [3 :0] spd_div // SPD Frequency Divider + ,output spd_pulse_width // Pulse Width of SPD + ,output spd_pulse_sw // Pulse sw of SPD + ,output cpc_sel // current source selection + ,output [1 :0] swcp_i // PTAT current switch + ,output [3 :0] sw_ptat_r // PTAT current adjustment + ,output [1 :0] sw_fll_cpi // Phase-locked loop charge pump current + ,output sw_fll_delay // PLL Dead Zone + ,output pfd_sel // PFD Loop selection + ,output spd_sel // SPD Loop selection + ,output fll_sel // FLL Loop selection + ,output vco_tc // VCO temperature compensation + ,output vco_tcr // VCO temperature compensation resistor + ,output vco_gain_adj // VCO gain adjustment + ,output vco_gain_adj_r // VCO gain adjustment resistor + ,output [2 :0] vco_cur_adj // VCO current adjustment + ,output vco_buff_en // VCO buff enable,active high + ,output vco_en // VCO enable,active high + ,output [2 :0] pll_dpwr_adj // PLL frequency division output power adjustment + ,output [6 :0] vco_fb_adj // VCO frequency band adjustment + ,output afc_en // AFC enable + ,output afc_shutdown // AFC module shutdown signal + ,output [0 :0] afc_det_speed // AFC detection speed + ,output [0 :0] flag_out_sel // Read and choose the signs + ,output afc_reset // AFC reset + ,output [10 :0] afc_cnt // AFC frequency band adjustment function counter + // counting time adjustment + ,output [10 :0] afc_ld_cnt // Adjust the counting time of the AFC lock detection + // feature counter + ,output [3 :0] afc_pres // Adjusting the resolution of the AFC comparator + ,output [14 :0] afc_ld_tcc // AFC Lock Detection Function Target Cycle Count + ,output [14 :0] afc_fb_tcc // Target number of cycles for AFC frequency band + // adjustment function + ,output sync_clr // PLL div sync clr,low active + ,output pll_rstn // PLL reset,active low + ,output [0 :0] div_rstn_sel // div rstn select, 1'b0: ext clear, 1'b1:inter pll lock + ,output [1 :0] test_clk_sel // test clk select, 2'b00:DIV1 clk, 2'b01:DIV2 clk, 2'b10:DIV4 clk, 2'b11:DIV8 clk + ,output [0 :0] test_clk_oen // test clk output enable, 1'b0:disenable, 1'b1:enable + ,output [7 :0] dig_clk_sel // digital main clk select, one hot code,bit[0]-->0 degree phase,bit[1]-->45 degree phase.....bit[7]-->315degree phae + ,output clkrx_pdn // CLock Rx Power Down + ,input pll_lock // PLL LOCK + //------------------------------Ch0 DAC cfg pin---------------------------------------------------- + ,output ch0_dac_Prbs + ,output [14 :0] ch0_dac_Set0 + ,output [14 :0] ch0_dac_Set1 + ,output [14 :0] ch0_dac_Set2 + ,output [14 :0] ch0_dac_Set3 + ,output [14 :0] ch0_dac_Set4 + ,output [14 :0] ch0_dac_Set5 + ,output [14 :0] ch0_dac_Set6 + ,output [14 :0] ch0_dac_Set7 + ,output [14 :0] ch0_dac_Set8 + ,output [14 :0] ch0_dac_Set9 + ,output [14 :0] ch0_dac_Set10 + ,output [14 :0] ch0_dac_Set11 + ,output [14 :0] ch0_dac_Set12 + ,output [14 :0] ch0_dac_Set13 + ,output [14 :0] ch0_dac_Set14 + ,output [14 :0] ch0_dac_Set15 + ,output [2 :0] ch0_dac_addr + ,output [2 :0] ch0_dac_dw + ,output [8 :0] ch0_dac_ref + ,output [16 :0] ch0_dac_Prbs_rst0 + ,output [16 :0] ch0_dac_Prbs_set0 + ,output [16 :0] ch0_dac_Prbs_rst1 + ,output [16 :0] ch0_dac_Prbs_set1 + ,output ch0_dac_Cal_sig + ,output ch0_dac_Cal_rstn + ,output ch0_dac_Cal_div_rstn + ,input ch0_dac_Cal_end + `ifdef CHANNEL_IS_FOUR + //------------------------------Ch1 DAC cfg pin---------------------------------------------------- + ,output ch1_dac_Prbs + ,output [14 :0] ch1_dac_Set0 + ,output [14 :0] ch1_dac_Set1 + ,output [14 :0] ch1_dac_Set2 + ,output [14 :0] ch1_dac_Set3 + ,output [14 :0] ch1_dac_Set4 + ,output [14 :0] ch1_dac_Set5 + ,output [14 :0] ch1_dac_Set6 + ,output [14 :0] ch1_dac_Set7 + ,output [14 :0] ch1_dac_Set8 + ,output [14 :0] ch1_dac_Set9 + ,output [14 :0] ch1_dac_Set10 + ,output [14 :0] ch1_dac_Set11 + ,output [14 :0] ch1_dac_Set12 + ,output [14 :0] ch1_dac_Set13 + ,output [14 :0] ch1_dac_Set14 + ,output [14 :0] ch1_dac_Set15 + ,output [2 :0] ch1_dac_addr + ,output [2 :0] ch1_dac_dw + ,output [8 :0] ch1_dac_ref + ,output [16 :0] ch1_dac_Prbs_rst0 + ,output [16 :0] ch1_dac_Prbs_set0 + ,output [16 :0] ch1_dac_Prbs_rst1 + ,output [16 :0] ch1_dac_Prbs_set1 + ,output ch1_dac_Cal_sig + ,output ch1_dac_Cal_rstn + ,output ch1_dac_Cal_div_rstn + ,output ch1_dac_Digitalclk + ,input ch1_dac_Cal_end + //------------------------------Ch2 DAC cfg pin---------------------------------------------------- + ,output ch2_dac_Prbs + ,output [14 :0] ch2_dac_Set0 + ,output [14 :0] ch2_dac_Set1 + ,output [14 :0] ch2_dac_Set2 + ,output [14 :0] ch2_dac_Set3 + ,output [14 :0] ch2_dac_Set4 + ,output [14 :0] ch2_dac_Set5 + ,output [14 :0] ch2_dac_Set6 + ,output [14 :0] ch2_dac_Set7 + ,output [14 :0] ch2_dac_Set8 + ,output [14 :0] ch2_dac_Set9 + ,output [14 :0] ch2_dac_Set10 + ,output [14 :0] ch2_dac_Set11 + ,output [14 :0] ch2_dac_Set12 + ,output [14 :0] ch2_dac_Set13 + ,output [14 :0] ch2_dac_Set14 + ,output [14 :0] ch2_dac_Set15 + ,output [2 :0] ch2_dac_addr + ,output [2 :0] ch2_dac_dw + ,output [8 :0] ch2_dac_ref + ,output [16 :0] ch2_dac_Prbs_rst0 + ,output [16 :0] ch2_dac_Prbs_set0 + ,output [16 :0] ch2_dac_Prbs_rst1 + ,output [16 :0] ch2_dac_Prbs_set1 + ,output ch2_dac_Cal_sig + ,output ch2_dac_Cal_rstn + ,output ch2_dac_Cal_div_rstn + ,output ch2_dac_Digitalclk + ,input ch2_dac_Cal_end + //------------------------------Ch3 DAC cfg pin---------------------------------------------------- + ,output ch3_dac_Prbs + ,output [14 :0] ch3_dac_Set0 + ,output [14 :0] ch3_dac_Set1 + ,output [14 :0] ch3_dac_Set2 + ,output [14 :0] ch3_dac_Set3 + ,output [14 :0] ch3_dac_Set4 + ,output [14 :0] ch3_dac_Set5 + ,output [14 :0] ch3_dac_Set6 + ,output [14 :0] ch3_dac_Set7 + ,output [14 :0] ch3_dac_Set8 + ,output [14 :0] ch3_dac_Set9 + ,output [14 :0] ch3_dac_Set10 + ,output [14 :0] ch3_dac_Set11 + ,output [14 :0] ch3_dac_Set12 + ,output [14 :0] ch3_dac_Set13 + ,output [14 :0] ch3_dac_Set14 + ,output [14 :0] ch3_dac_Set15 + ,output [2 :0] ch3_dac_addr + ,output [2 :0] ch3_dac_dw + ,output [8 :0] ch3_dac_ref + ,output [16 :0] ch3_dac_Prbs_rst0 + ,output [16 :0] ch3_dac_Prbs_set0 + ,output [16 :0] ch3_dac_Prbs_rst1 + ,output [16 :0] ch3_dac_Prbs_set1 + ,output ch3_dac_Cal_sig + ,output ch3_dac_Cal_rstn + ,output ch3_dac_Cal_div_rstn + ,output ch3_dac_Digitalclk + ,input ch3_dac_Cal_end + `endif + //------------------------------Ch0 DSP data out---------------------------------------------------- + `ifdef CHANNEL_XY_ON + ,output [15 :0] ch0_xy_dsp_dout0 + ,output [15 :0] ch0_xy_dsp_dout1 + ,output [15 :0] ch0_xy_dsp_dout2 + ,output [15 :0] ch0_xy_dsp_dout3 + ,output [15 :0] ch0_xy_dsp_dout4 + ,output [15 :0] ch0_xy_dsp_dout5 + ,output [15 :0] ch0_xy_dsp_dout6 + ,output [15 :0] ch0_xy_dsp_dout7 + ,output [15 :0] ch0_xy_dsp_dout8 + ,output [15 :0] ch0_xy_dsp_dout9 + ,output [15 :0] ch0_xy_dsp_dout10 + ,output [15 :0] ch0_xy_dsp_dout11 + ,output [15 :0] ch0_xy_dsp_dout12 + ,output [15 :0] ch0_xy_dsp_dout13 + ,output [15 :0] ch0_xy_dsp_dout14 + ,output [15 :0] ch0_xy_dsp_dout15 + `endif + `ifdef CHANNEL_Z_ON + ,output [15 :0] ch0_z_dsp_dout0 + ,output [15 :0] ch0_z_dsp_dout1 + ,output [15 :0] ch0_z_dsp_dout2 + ,output [15 :0] ch0_z_dsp_dout3 + `endif + `ifdef CHANNEL_IS_FOUR + //------------------------------Ch1 DSP data out---------------------------------------------------- + `ifdef CHANNEL_XY_ON + ,output [15 :0] ch1_xy_dsp_dout0 + ,output [15 :0] ch1_xy_dsp_dout1 + ,output [15 :0] ch1_xy_dsp_dout2 + ,output [15 :0] ch1_xy_dsp_dout3 + ,output [15 :0] ch1_xy_dsp_dout4 + ,output [15 :0] ch1_xy_dsp_dout5 + ,output [15 :0] ch1_xy_dsp_dout6 + ,output [15 :0] ch1_xy_dsp_dout7 + ,output [15 :0] ch1_xy_dsp_dout8 + ,output [15 :0] ch1_xy_dsp_dout9 + ,output [15 :0] ch1_xy_dsp_dout10 + ,output [15 :0] ch1_xy_dsp_dout11 + ,output [15 :0] ch1_xy_dsp_dout12 + ,output [15 :0] ch1_xy_dsp_dout13 + ,output [15 :0] ch1_xy_dsp_dout14 + ,output [15 :0] ch1_xy_dsp_dout15 + `endif + `ifdef CHANNEL_Z_ON + ,output [15 :0] ch1_z_dsp_dout0 + ,output [15 :0] ch1_z_dsp_dout1 + ,output [15 :0] ch1_z_dsp_dout2 + ,output [15 :0] ch1_z_dsp_dout3 + `endif + //------------------------------Ch2 DSP data out---------------------------------------------------- + `ifdef CHANNEL_XY_ON + ,output [15 :0] ch2_xy_dsp_dout0 + ,output [15 :0] ch2_xy_dsp_dout1 + ,output [15 :0] ch2_xy_dsp_dout2 + ,output [15 :0] ch2_xy_dsp_dout3 + ,output [15 :0] ch2_xy_dsp_dout4 + ,output [15 :0] ch2_xy_dsp_dout5 + ,output [15 :0] ch2_xy_dsp_dout6 + ,output [15 :0] ch2_xy_dsp_dout7 + ,output [15 :0] ch2_xy_dsp_dout8 + ,output [15 :0] ch2_xy_dsp_dout9 + ,output [15 :0] ch2_xy_dsp_dout10 + ,output [15 :0] ch2_xy_dsp_dout11 + ,output [15 :0] ch2_xy_dsp_dout12 + ,output [15 :0] ch2_xy_dsp_dout13 + ,output [15 :0] ch2_xy_dsp_dout14 + ,output [15 :0] ch2_xy_dsp_dout15 + `endif + `ifdef CHANNEL_Z_ON + ,output [15 :0] ch2_z_dsp_dout0 + ,output [15 :0] ch2_z_dsp_dout1 + ,output [15 :0] ch2_z_dsp_dout2 + ,output [15 :0] ch2_z_dsp_dout3 + `endif + //------------------------------Ch3 DSP data out---------------------------------------------------- + `ifdef CHANNEL_XY_ON + ,output [15 :0] ch3_xy_dsp_dout0 + ,output [15 :0] ch3_xy_dsp_dout1 + ,output [15 :0] ch3_xy_dsp_dout2 + ,output [15 :0] ch3_xy_dsp_dout3 + ,output [15 :0] ch3_xy_dsp_dout4 + ,output [15 :0] ch3_xy_dsp_dout5 + ,output [15 :0] ch3_xy_dsp_dout6 + ,output [15 :0] ch3_xy_dsp_dout7 + ,output [15 :0] ch3_xy_dsp_dout8 + ,output [15 :0] ch3_xy_dsp_dout9 + ,output [15 :0] ch3_xy_dsp_dout10 + ,output [15 :0] ch3_xy_dsp_dout11 + ,output [15 :0] ch3_xy_dsp_dout12 + ,output [15 :0] ch3_xy_dsp_dout13 + ,output [15 :0] ch3_xy_dsp_dout14 + ,output [15 :0] ch3_xy_dsp_dout15 + `endif + `ifdef CHANNEL_Z_ON + ,output [15 :0] ch3_z_dsp_dout0 + ,output [15 :0] ch3_z_dsp_dout1 + ,output [15 :0] ch3_z_dsp_dout2 + ,output [15 :0] ch3_z_dsp_dout3 + `endif + `endif +); + +//------------------------------spi_slave instantiation start---------------------------------- +// spi_slave +//--------------------------------------------------------------------------------------------- +sram_if#(25,32) mst(clk); +sram_if#(20,32) slv[25:0](clk); +//connect pll +wire [31 :0] pll_wrdata ; +wire pll_wren ; +wire [7 :0] pll_rwaddr ; +wire pll_rden ; +wire [31 :0] pll_rddata ; +//connect system +wire [31 :0] sys_wrdata ; +wire sys_wren ; +wire [24 :0] sys_rwaddr ; +wire sys_rden ; +wire [31 :0] sys_rddata ; + +wire pll_rstn_o; +assign pll_rstn = pll_rstn_o; + +assign mst.wben = 4'hf; + +spi_slave U_spi_slave ( + .clk ( clk ) + ,.rst_n ( pll_rstn_o ) + ,.cfgid ( cfgid ) + ,.sclk ( sclk ) + ,.csn ( csn ) + ,.mosi ( mosi ) + ,.miso ( miso ) + ,.oen ( oen ) + ,.pll_wrdata ( pll_wrdata ) + ,.pll_wren ( pll_wren ) + ,.pll_rwaddr ( pll_rwaddr ) + ,.pll_rden ( pll_rden ) + ,.pll_rddata ( pll_rddata ) + ,.sys_wrdata ( mst.din ) + ,.sys_wren ( mst.wren ) + ,.sys_rwaddr ( mst.addr ) + ,.sys_rden ( mst.rden ) + ,.sys_rddata ( mst.dout ) +); + +//--------------------------------------------------------------------------------------------- +// spi_slave +//------------------------------spi_slave instantiation end------------------------------------ + +//------------------------------intpll_regfile instantiation start----------------------------- +// intpll_regfile +//--------------------------------------------------------------------------------------------- + +wire div_sync_en ; +wire sync_oe ; + +intpll_regfile U_intpll_regfile ( + .clk ( sclk ) + ,.rst_n ( pll_rstn_o ) + ,.wrdata ( pll_wrdata ) + ,.wren ( pll_wren ) + ,.rwaddr ( pll_rwaddr[7:0] ) + ,.rden ( pll_rden ) + ,.rddata ( pll_rddata ) + ,.ref_sel ( ref_sel ) + ,.ref_en ( ref_en ) + ,.ref_s2d_en ( ref_s2d_en ) + ,.p_cnt ( p_cnt ) + ,.pfd_delay ( pfd_delay ) + ,.pfd_dff_Set ( pfd_dff_Set ) + ,.pfd_dff_4and ( pfd_dff_4and ) + ,.spd_div ( spd_div ) + ,.spd_pulse_width ( spd_pulse_width ) + ,.spd_pulse_sw ( spd_pulse_sw ) + ,.cpc_sel ( cpc_sel ) + ,.swcp_i ( swcp_i ) + ,.sw_ptat_r ( sw_ptat_r ) + ,.sw_fll_cpi ( sw_fll_cpi ) + ,.sw_fll_delay ( sw_fll_delay ) + ,.pfd_sel ( pfd_sel ) + ,.spd_sel ( spd_sel ) + ,.fll_sel ( fll_sel ) + ,.vco_tc ( vco_tc ) + ,.vco_tcr ( vco_tcr ) + ,.vco_gain_adj ( vco_gain_adj ) + ,.vco_gain_adj_r ( vco_gain_adj_r ) + ,.vco_cur_adj ( vco_cur_adj ) + ,.vco_buff_en ( vco_buff_en ) + ,.vco_en ( vco_en ) + ,.pll_dpwr_adj ( pll_dpwr_adj ) + ,.vco_fb_adj ( vco_fb_adj ) + ,.afc_en ( afc_en ) + ,.afc_shutdown ( afc_shutdown ) + ,.afc_det_speed ( afc_det_speed ) + ,.flag_out_sel ( flag_out_sel ) + ,.afc_reset ( afc_reset ) + ,.afc_cnt ( afc_cnt ) + ,.afc_ld_cnt ( afc_ld_cnt ) + ,.afc_pres ( afc_pres ) + ,.afc_ld_tcc ( afc_ld_tcc ) + ,.afc_fb_tcc ( afc_fb_tcc ) + ,.div_rstn_sel ( div_rstn_sel ) + ,.test_clk_sel ( test_clk_sel ) + ,.test_clk_oen ( test_clk_oen ) + ,.dig_clk_sel ( dig_clk_sel ) + ,.div_sync_en ( div_sync_en ) + ,.sync_oe ( sync_oe ) + ,.clkrx_pdn ( clkrx_pdn ) + ,.pll_lock ( pll_lock ) +); + + +//--------------------------------------------------------------------------------------------- +// intpll_regfile +//------------------------------intpll_regfile instantiation end------------------------------- + +//----------------------------spi_bus_decoder instantiation start------------------------------ +// intpll_regfile +//--------------------------------------------------------------------------------------------- + +spi_bus_decoder #( + .SLVNUM ( `SLVNUM ) + ,.SPIBUS_CMD_REG ( `SPIBUS_CMD_REG ) + ,.SPIBUS_OUT_REG ( `SPIBUS_OUT_REG ) + ) U_spi_bus_decoder ( + .clk ( clk ) + ,.rst_n ( pll_rstn_o ) + ,.mst ( mst ) + ,.slv ( slv ) + ); +//--------------------------------------------------------------------------------------------- +// spi_bus_decoder +//------------------------------spi_bus_decoder instantiation end------------------------------ + +//-----------------------------system_regfile instantiation start------------------------------ +// system_regfile as slave device 0 +//--------------------------------------------------------------------------------------------- +wire dbg_enable ; +wire dbg_data_sel ; +wire [3 :0] dbg_ch_sel ; +wire dbg_upd ; +wire ch0_proc_cft ; +wire ch0_ldst_addr_unalgn ; +wire ch0_dec_err ; +wire ch0_exit_irq ; +wire ch1_proc_cft ; +wire ch1_ldst_addr_unalgn ; +wire ch1_dec_err ; +wire ch1_exit_irq ; +wire ch2_proc_cft ; +wire ch2_ldst_addr_unalgn ; +wire ch2_dec_err ; +wire ch2_exit_irq ; +wire ch3_proc_cft ; +wire ch3_ldst_addr_unalgn ; +wire ch3_dec_err ; +wire ch3_exit_irq ; +wire sys_soft_rstn ; +wire ch0_soft_rstn ; +wire ch1_soft_rstn ; +wire ch2_soft_rstn ; +wire ch3_soft_rstn ; + +//When designed for single-channel, open this macro +`ifndef CHANNEL_IS_FOUR +assign ch1_proc_cft = 1'b0; +assign ch1_ldst_addr_unalgn = 1'b0; +assign ch1_dec_err = 1'b0; +assign ch1_exit_irq = 1'b0; +assign ch2_proc_cft = 1'b0; +assign ch2_ldst_addr_unalgn = 1'b0; +assign ch2_dec_err = 1'b0; +assign ch2_exit_irq = 1'b0; +assign ch3_proc_cft = 1'b0; +assign ch3_ldst_addr_unalgn = 1'b0; +assign ch3_dec_err = 1'b0; +assign ch3_exit_irq = 1'b0; +`endif + + +system_regfile U_system_regfile ( + .clk ( clk ) + ,.rst_n ( pll_rstn_o ) + ,.wrdata ( slv[0].din ) + ,.wren ( slv[0].wren ) + ,.rwaddr ( slv[0].addr[15:0] ) + ,.rden ( slv[0].rden ) + ,.rddata ( slv[0].dout ) + ,.dbg_enable ( dbg_enable ) + ,.dbg_data_sel ( dbg_data_sel ) + ,.dbg_ch_sel ( dbg_ch_sel ) + ,.dbg_upd ( dbg_upd ) + ,.ch0_proc_cft ( ch0_proc_cft ) + ,.ch0_ldst_addr_unalgn ( ch0_ldst_addr_unalgn ) + ,.ch0_dec_err ( ch0_dec_err ) + ,.ch0_exit_irq ( ch0_exit_irq ) + ,.ch1_proc_cft ( ch1_proc_cft ) + ,.ch1_ldst_addr_unalgn ( ch1_ldst_addr_unalgn ) + ,.ch1_dec_err ( ch1_dec_err ) + ,.ch1_exit_irq ( ch1_exit_irq ) + ,.ch2_proc_cft ( ch2_proc_cft ) + ,.ch2_ldst_addr_unalgn ( ch2_ldst_addr_unalgn ) + ,.ch2_dec_err ( ch2_dec_err ) + ,.ch2_exit_irq ( ch2_exit_irq ) + ,.ch3_proc_cft ( ch3_proc_cft ) + ,.ch3_ldst_addr_unalgn ( ch3_ldst_addr_unalgn ) + ,.ch3_dec_err ( ch3_dec_err ) + ,.ch3_exit_irq ( ch3_exit_irq ) + ,.sys_soft_rstn ( sys_soft_rstn ) + ,.ch0_soft_rstn ( ch0_soft_rstn ) + ,.ch1_soft_rstn ( ch1_soft_rstn ) + ,.ch2_soft_rstn ( ch2_soft_rstn ) + ,.ch3_soft_rstn ( ch3_soft_rstn ) + ,.irq ( irq ) +); + +//--------------------------------------------------------------------------------------------- +// system_regfile +//------------------------------system_regfile instantiation end------------------------------- + +//--------------------------------------------------------------------------------------------- +// sync_int +//------------------------------sync_int instantiation start----------------------------------- + +wire sync_oe_s; +syncer #(1, 2) sync_oe_syncer (clk, pll_rstn_o, sync_oe, sync_oe_s); + +wire div_sync_en_s; +syncer #(1, 2) div_sync_en_syncer (clk, pll_rstn_o, div_sync_en, div_sync_en_s); + +wire sync_int; + +sync_buf #( +) U_sync_buf ( + .clk ( clk ) + ,.rst_n ( pll_rstn_o ) + ,.ext_ena ( sync_oe_s ) + ,.clr_ena_sync ( div_sync_en_s ) + ,.clr_ena ( div_sync_en ) + ,.sync_in ( sync_in ) + ,.sync_int ( sync_int ) + ,.sync_ext ( sync_out ) + ,.sync_clr ( sync_clr ) +); + +//--------------------------------------------------------------------------------------------- +// sync_int +//------------------------------sync_int instantiation end------------------------------------- + +//--------------------------------------------------------------------------------------------- +// rst_gen_unit instantiation start +//--------------------------------------------------------------------------------------------- +wire ch0_rstn_o; +wire ch1_rstn_o; +wire ch2_rstn_o; +wire ch3_rstn_o; + + +rst_gen_unit U_rst_gen_unit ( + .async_rstn_i ( async_rstn ) + ,.por_rstn_i ( por_rstn ) + ,.sys_soft_resetn_i ( sys_soft_rstn ) + ,.ch0_soft_rstn_i ( ch0_soft_rstn ) + ,.ch1_soft_rstn_i ( ch1_soft_rstn ) + ,.ch2_soft_rstn_i ( ch2_soft_rstn ) + ,.ch3_soft_rstn_i ( ch3_soft_rstn ) + ,.clk ( clk ) + ,.ch0_rstn_o ( ch0_rstn_o ) + ,.ch1_rstn_o ( ch1_rstn_o ) + ,.ch2_rstn_o ( ch2_rstn_o ) + ,.ch3_rstn_o ( ch3_rstn_o ) + ,.pll_rstn_o ( pll_rstn_o ) +); +//--------------------------------------------------------------------------------------------- +// rst_gen_unit instantiation end +//--------------------------------------------------------------------------------------------- + +//--------------------------------------------------------------------------------------------- +// channel 0 instantiation start +//--------------------------------------------------------------------------------------------- + +wire [15:0] ch0_awg_data_i ; +wire [15:0] ch0_awg_data_q ; +wire [0 :0] ch0_awg_vld ; + + +`ifdef CHANNEL_XY_ON +wire ch0_xy_dsp_dout_vld ; +`endif + + +channel_top U0_channel_top ( + .clk ( clk ) + ,.rst_n ( ch0_rstn_o ) + ,.sync_int ( sync_int ) + ,.dec_o_ilegl ( ch0_dec_err ) + ,.agu_o_addr_unalgn ( ch0_ldst_addr_unalgn ) + ,.awg_proc_cft ( ch0_proc_cft ) + ,.mcu_ext_o_intr ( ch0_exit_irq ) + ,.fb_st_in ( ch0_feedback ) + //ch0 itcm addr space --> 0x0010_0000 ~ 0x001F_FFFF + ,.itcm_i_rwaddr ( slv[1].addr[14:0] ) + ,.itcm_i_wrdata ( slv[1].din ) + ,.itcm_i_wren ( slv[1].wren ) + ,.itcm_i_wrmask ( 4'h0 ) + ,.itcm_i_rden ( slv[1].rden ) + ,.itcm_o_rddata ( slv[1].dout ) + //ch0 itcm addr space --> 0x0020_0000 ~ 0x002F_FFFF + ,.dtcm_i_rwaddr ( slv[2].addr[14:0] ) + ,.dtcm_i_wrdata ( slv[2].din ) + ,.dtcm_i_wren ( slv[2].wren ) + ,.dtcm_i_wrmask ( 4'h0 ) + ,.dtcm_i_rden ( slv[2].rden ) + ,.dtcm_o_rddata ( slv[2].dout ) + //ch0 dtcm addr space --> 0x0030_0000 ~ 0x003F_FFFF + ,.ctrl_rwaddr ( slv[3].addr[15:0] ) + ,.ctrl_wrdata ( slv[3].din ) + ,.ctrl_wren ( slv[3].wren ) + ,.ctrl_rden ( slv[3].rden ) + ,.ctrl_rddata ( slv[3].dout ) + //ch0 envelope ID addr space --> 0x0040_0000 ~ 0x004F_FFFF + ,.enve_id_brwaddr ( slv[4].addr[7:0] ) + ,.enve_id_bwrdata ( slv[4].din ) + ,.enve_id_bwren ( slv[4].wren ) + ,.enve_id_brden ( slv[4].rden ) + ,.enve_id_brddata ( slv[4].dout ) + //ch0 envelope memory addr space --> 0x0050_0000 ~ 0x005F_FFFF + ,.enve_brwaddr ( slv[5].addr[14:0] ) + ,.enve_bwrdata ( slv[5].din ) + ,.enve_bwren ( slv[5].wren ) + ,.enve_brden ( slv[5].rden ) + ,.enve_brddata ( slv[5].dout ) + //ch0 dac regfile addr space --> 0x0060_0000 ~ 0x006F_FFFF + ,.dac_rwaddr ( slv[6].addr[15:0] ) + ,.dac_wrdata ( slv[6].din ) + ,.dac_wren ( slv[6].wren ) + ,.dac_rden ( slv[6].rden ) + ,.dac_rddata ( slv[6].dout ) + ,.dac_Prbs ( ch0_dac_Prbs ) + ,.dac_Set0 ( ch0_dac_Set0 ) + ,.dac_Set1 ( ch0_dac_Set1 ) + ,.dac_Set2 ( ch0_dac_Set2 ) + ,.dac_Set3 ( ch0_dac_Set3 ) + ,.dac_Set4 ( ch0_dac_Set4 ) + ,.dac_Set5 ( ch0_dac_Set5 ) + ,.dac_Set6 ( ch0_dac_Set6 ) + ,.dac_Set7 ( ch0_dac_Set7 ) + ,.dac_Set8 ( ch0_dac_Set8 ) + ,.dac_Set9 ( ch0_dac_Set9 ) + ,.dac_Set10 ( ch0_dac_Set10 ) + ,.dac_Set11 ( ch0_dac_Set11 ) + ,.dac_Set12 ( ch0_dac_Set12 ) + ,.dac_Set13 ( ch0_dac_Set13 ) + ,.dac_Set14 ( ch0_dac_Set14 ) + ,.dac_Set15 ( ch0_dac_Set15 ) + ,.dac_addr ( ch0_dac_addr ) + ,.dac_dw ( ch0_dac_dw ) + ,.dac_ref ( ch0_dac_ref ) + ,.dac_Prbs_rst0 ( ch0_dac_Prbs_rst0 ) + ,.dac_Prbs_set0 ( ch0_dac_Prbs_set0 ) + ,.dac_Prbs_rst1 ( ch0_dac_Prbs_rst1 ) + ,.dac_Prbs_set1 ( ch0_dac_Prbs_set1 ) + ,.dac_Cal_sig ( ch0_dac_Cal_sig ) + ,.dac_Cal_rstn ( ch0_dac_Cal_rstn ) + ,.Cal_div_rstn ( ch0_dac_Cal_div_rstn ) + ,.dac_Cal_end ( ch0_dac_Cal_end ) + ,.awg_data_i_o ( ch0_awg_data_i ) + ,.awg_data_q_o ( ch0_awg_data_q ) + ,.awg_vld_o ( ch0_awg_vld ) + `ifdef CHANNEL_XY_ON + ,.xy_dsp_dout0 ( ch0_xy_dsp_dout0 ) + ,.xy_dsp_dout1 ( ch0_xy_dsp_dout1 ) + ,.xy_dsp_dout2 ( ch0_xy_dsp_dout2 ) + ,.xy_dsp_dout3 ( ch0_xy_dsp_dout3 ) + ,.xy_dsp_dout4 ( ch0_xy_dsp_dout4 ) + ,.xy_dsp_dout5 ( ch0_xy_dsp_dout5 ) + ,.xy_dsp_dout6 ( ch0_xy_dsp_dout6 ) + ,.xy_dsp_dout7 ( ch0_xy_dsp_dout7 ) + ,.xy_dsp_dout8 ( ch0_xy_dsp_dout8 ) + ,.xy_dsp_dout9 ( ch0_xy_dsp_dout9 ) + ,.xy_dsp_dout10 ( ch0_xy_dsp_dout10 ) + ,.xy_dsp_dout11 ( ch0_xy_dsp_dout11 ) + ,.xy_dsp_dout12 ( ch0_xy_dsp_dout12 ) + ,.xy_dsp_dout13 ( ch0_xy_dsp_dout13 ) + ,.xy_dsp_dout14 ( ch0_xy_dsp_dout14 ) + ,.xy_dsp_dout15 ( ch0_xy_dsp_dout15 ) + ,.xy_dsp_dout_vld ( ch0_xy_dsp_dout_vld ) + `endif + `ifdef CHANNEL_Z_ON + ,.z_dsp_dout0 ( ch0_z_dsp_dout0 ) + ,.z_dsp_dout1 ( ch0_z_dsp_dout1 ) + ,.z_dsp_dout2 ( ch0_z_dsp_dout2 ) + ,.z_dsp_dout3 ( ch0_z_dsp_dout3 ) + `endif + ); +//--------------------------------------------------------------------------------------------- +// channel 0 instantiation end +//--------------------------------------------------------------------------------------------- + +`ifdef CHANNEL_IS_FOUR +//--------------------------------------------------------------------------------------------- +// channel 1 instantiation start +//--------------------------------------------------------------------------------------------- +wire [15:0] ch1_awg_data_i ; +wire [15:0] ch1_awg_data_q ; +wire [15:0] ch1_awg_vld ; +`ifdef CHANNEL_XY_ON +wire ch1_xy_dsp_dout_vld ; +`endif + + +channel_top U1_channel_top ( + .clk ( clk ) + ,.rst_n ( ch1_rstn_o ) + ,.sync_int ( sync_int ) + ,.dec_o_ilegl ( ch1_dec_err ) + ,.agu_o_addr_unalgn ( ch1_ldst_addr_unalgn ) + ,.awg_proc_cft ( ch1_proc_cft ) + ,.mcu_ext_o_intr ( ch1_exit_irq ) + ,.fb_st_in ( ch1_feedback ) + //ch1 itcm addr space --> 0x0070_0000 ~ 0x007F_FFFF + ,.itcm_i_rwaddr ( slv[7].addr[14:0] ) + ,.itcm_i_wrdata ( slv[7].din ) + ,.itcm_i_wren ( slv[7].wren ) + ,.itcm_i_wrmask ( 4'h0 ) + ,.itcm_i_rden ( slv[7].rden ) + ,.itcm_o_rddata ( slv[7].dout ) + //ch1 itcm addr space --> 0x0080_0000 ~ 0x008F_FFFF + ,.dtcm_i_rwaddr ( slv[8].addr[14:0] ) + ,.dtcm_i_wrdata ( slv[8].din ) + ,.dtcm_i_wren ( slv[8].wren ) + ,.dtcm_i_wrmask ( 4'h0 ) + ,.dtcm_i_rden ( slv[8].rden ) + ,.dtcm_o_rddata ( slv[8].dout ) + //ch1 dtcm addr space --> 0x0090_0000 ~ 0x009F_FFFF + ,.ctrl_rwaddr ( slv[9].addr[15:0] ) + ,.ctrl_wrdata ( slv[9].din ) + ,.ctrl_wren ( slv[9].wren ) + ,.ctrl_rden ( slv[9].rden ) + ,.ctrl_rddata ( slv[9].dout ) + //ch1 envelope ID addr space --> 0x00A0_0000 ~ 0x00AF_FFFF + ,.enve_id_brwaddr ( slv[10].addr[7:0] ) + ,.enve_id_bwrdata ( slv[10].din ) + ,.enve_id_bwren ( slv[10].wren ) + ,.enve_id_brden ( slv[10].rden ) + ,.enve_id_brddata ( slv[10].dout ) + //ch1 envelope memory addr space --> 0x00B0_0000 ~ 0x0005F_FFFF + ,.enve_brwaddr ( slv[11].addr[14:0] ) + ,.enve_bwrdata ( slv[11].din ) + ,.enve_bwren ( slv[11].wren ) + ,.enve_brden ( slv[11].rden ) + ,.enve_brddata ( slv[11].dout ) + //ch1 dac regfile addr space --> 0x00C0_0000 ~ 0x00CF_FFFFF + ,.dac_rwaddr ( slv[12].addr[15:0] ) + ,.dac_wrdata ( slv[12].din ) + ,.dac_wren ( slv[12].wren ) + ,.dac_rden ( slv[12].rden ) + ,.dac_rddata ( slv[12].dout ) + ,.dac_Prbs ( ch1_dac_Prbs ) + ,.dac_Set0 ( ch1_dac_Set0 ) + ,.dac_Set1 ( ch1_dac_Set1 ) + ,.dac_Set2 ( ch1_dac_Set2 ) + ,.dac_Set3 ( ch1_dac_Set3 ) + ,.dac_Set4 ( ch1_dac_Set4 ) + ,.dac_Set5 ( ch1_dac_Set5 ) + ,.dac_Set6 ( ch1_dac_Set6 ) + ,.dac_Set7 ( ch1_dac_Set7 ) + ,.dac_Set8 ( ch1_dac_Set8 ) + ,.dac_Set9 ( ch1_dac_Set9 ) + ,.dac_Set10 ( ch1_dac_Set10 ) + ,.dac_Set11 ( ch1_dac_Set11 ) + ,.dac_Set12 ( ch1_dac_Set12 ) + ,.dac_Set13 ( ch1_dac_Set13 ) + ,.dac_Set14 ( ch1_dac_Set14 ) + ,.dac_Set15 ( ch1_dac_Set15 ) + ,.dac_addr ( ch1_dac_addr ) + ,.dac_dw ( ch1_dac_dw ) + ,.dac_ref ( ch1_dac_ref ) + ,.dac_Prbs_rst0 ( ch1_dac_Prbs_rst0 ) + ,.dac_Prbs_set0 ( ch1_dac_Prbs_set0 ) + ,.dac_Prbs_rst1 ( ch1_dac_Prbs_rst1 ) + ,.dac_Prbs_set1 ( ch1_dac_Prbs_set1 ) + ,.dac_Cal_sig ( ch1_dac_Cal_sig ) + ,.dac_Cal_rstn ( ch1_dac_Cal_rstn ) + ,.Cal_div_rstn ( ch1_dac_Cal_div_rstn ) + ,.dac_Cal_end ( ch1_dac_Cal_end ) + ,.awg_data_i_o ( ch1_awg_data_i ) + ,.awg_data_q_o ( ch1_awg_data_q ) + ,.awg_vld_o ( ch1_awg_vld ) + `ifdef CHANNEL_XY_ON + ,.xy_dsp_dout0 ( ch1_xy_dsp_dout0 ) + ,.xy_dsp_dout1 ( ch1_xy_dsp_dout1 ) + ,.xy_dsp_dout2 ( ch1_xy_dsp_dout2 ) + ,.xy_dsp_dout3 ( ch1_xy_dsp_dout3 ) + ,.xy_dsp_dout4 ( ch1_xy_dsp_dout4 ) + ,.xy_dsp_dout5 ( ch1_xy_dsp_dout5 ) + ,.xy_dsp_dout6 ( ch1_xy_dsp_dout6 ) + ,.xy_dsp_dout7 ( ch1_xy_dsp_dout7 ) + ,.xy_dsp_dout8 ( ch1_xy_dsp_dout8 ) + ,.xy_dsp_dout9 ( ch1_xy_dsp_dout9 ) + ,.xy_dsp_dout10 ( ch1_xy_dsp_dout10 ) + ,.xy_dsp_dout11 ( ch1_xy_dsp_dout11 ) + ,.xy_dsp_dout12 ( ch1_xy_dsp_dout12 ) + ,.xy_dsp_dout13 ( ch1_xy_dsp_dout13 ) + ,.xy_dsp_dout14 ( ch1_xy_dsp_dout14 ) + ,.xy_dsp_dout15 ( ch1_xy_dsp_dout15 ) + ,.xy_dsp_dout_vld ( ch1_xy_dsp_dout_vld ) + `endif + `ifdef CHANNEL_Z_ON + ,.z_dsp_dout0 ( ch1_z_dsp_dout0 ) + ,.z_dsp_dout1 ( ch1_z_dsp_dout1 ) + ,.z_dsp_dout2 ( ch1_z_dsp_dout2 ) + ,.z_dsp_dout3 ( ch1_z_dsp_dout3 ) + `endif + ); +//--------------------------------------------------------------------------------------------- +// channel 1 instantiation end +//--------------------------------------------------------------------------------------------- + + +//--------------------------------------------------------------------------------------------- +// channel 2 instantiation start +//--------------------------------------------------------------------------------------------- + +wire [15:0] ch2_awg_data_i ; +wire [15:0] ch2_awg_data_q ; +wire [15:0] ch2_awg_vld ; +`ifdef CHANNEL_XY_ON +wire ch2_xy_dsp_dout_vld ; +`endif + +channel_top U2_channel_top ( + .clk ( clk ) + ,.rst_n ( ch2_rstn_o ) + ,.sync_int ( sync_int ) + ,.dec_o_ilegl ( ch2_dec_err ) + ,.agu_o_addr_unalgn ( ch2_ldst_addr_unalgn ) + ,.awg_proc_cft ( ch2_proc_cft ) + ,.mcu_ext_o_intr ( ch2_exit_irq ) + ,.fb_st_in ( ch2_feedback ) + //ch1 itcm addr space --> 0x00D0_0000 ~ 0x00DF_FFFF + ,.itcm_i_rwaddr ( slv[13].addr[14:0] ) + ,.itcm_i_wrdata ( slv[13].din ) + ,.itcm_i_wren ( slv[13].wren ) + ,.itcm_i_wrmask ( 4'h0 ) + ,.itcm_i_rden ( slv[13].rden ) + ,.itcm_o_rddata ( slv[13].dout ) + //ch1 itcm addr space --> 0x00E0_0000 ~ 0x00EF_FFFF + ,.dtcm_i_rwaddr ( slv[14].addr[14:0] ) + ,.dtcm_i_wrdata ( slv[14].din ) + ,.dtcm_i_wren ( slv[14].wren ) + ,.dtcm_i_wrmask ( 4'h0 ) + ,.dtcm_i_rden ( slv[14].rden ) + ,.dtcm_o_rddata ( slv[14].dout ) + //ch1 dtcm addr space --> 0x00F0_0000 ~ 0x00FF_FFFF + ,.ctrl_rwaddr ( slv[15].addr[15:0] ) + ,.ctrl_wrdata ( slv[15].din ) + ,.ctrl_wren ( slv[15].wren ) + ,.ctrl_rden ( slv[15].rden ) + ,.ctrl_rddata ( slv[15].dout ) + //ch1 envelope ID addr space --> 0x0100_0000 ~ 0x010F_FFFF + ,.enve_id_brwaddr ( slv[16].addr[7:0] ) + ,.enve_id_bwrdata ( slv[16].din ) + ,.enve_id_bwren ( slv[16].wren ) + ,.enve_id_brden ( slv[16].rden ) + ,.enve_id_brddata ( slv[16].dout ) + //ch1 envelope memory addr space --> 0x0110_0000 ~ 0x0105F_FFFF + ,.enve_brwaddr ( slv[17].addr[14:0] ) + ,.enve_bwrdata ( slv[17].din ) + ,.enve_bwren ( slv[17].wren ) + ,.enve_brden ( slv[17].rden ) + ,.enve_brddata ( slv[17].dout ) + //ch1 dac regfile addr space --> 0x0120_0000 ~ 0x012F_FFFFF + ,.dac_rwaddr ( slv[18].addr[15:0] ) + ,.dac_wrdata ( slv[18].din ) + ,.dac_wren ( slv[18].wren ) + ,.dac_rden ( slv[18].rden ) + ,.dac_rddata ( slv[18].dout ) + ,.dac_Prbs ( ch2_dac_Prbs ) + ,.dac_Set0 ( ch2_dac_Set0 ) + ,.dac_Set1 ( ch2_dac_Set1 ) + ,.dac_Set2 ( ch2_dac_Set2 ) + ,.dac_Set3 ( ch2_dac_Set3 ) + ,.dac_Set4 ( ch2_dac_Set4 ) + ,.dac_Set5 ( ch2_dac_Set5 ) + ,.dac_Set6 ( ch2_dac_Set6 ) + ,.dac_Set7 ( ch2_dac_Set7 ) + ,.dac_Set8 ( ch2_dac_Set8 ) + ,.dac_Set9 ( ch2_dac_Set9 ) + ,.dac_Set10 ( ch2_dac_Set10 ) + ,.dac_Set11 ( ch2_dac_Set11 ) + ,.dac_Set12 ( ch2_dac_Set12 ) + ,.dac_Set13 ( ch2_dac_Set13 ) + ,.dac_Set14 ( ch2_dac_Set14 ) + ,.dac_Set15 ( ch2_dac_Set15 ) + ,.dac_addr ( ch2_dac_addr ) + ,.dac_dw ( ch2_dac_dw ) + ,.dac_ref ( ch2_dac_ref ) + ,.dac_Prbs_rst0 ( ch2_dac_Prbs_rst0 ) + ,.dac_Prbs_set0 ( ch2_dac_Prbs_set0 ) + ,.dac_Prbs_rst1 ( ch2_dac_Prbs_rst1 ) + ,.dac_Prbs_set1 ( ch2_dac_Prbs_set1 ) + ,.dac_Cal_sig ( ch2_dac_Cal_sig ) + ,.dac_Cal_rstn ( ch2_dac_Cal_rstn ) + ,.Cal_div_rstn ( ch2_dac_Cal_div_rstn ) + ,.dac_Cal_end ( ch2_dac_Cal_end ) + ,.awg_data_i_o ( ch2_awg_data_i ) + ,.awg_data_q_o ( ch2_awg_data_q ) + ,.awg_vld_o ( ch2_awg_vld ) + `ifdef CHANNEL_XY_ON + ,.xy_dsp_dout0 ( ch2_xy_dsp_dout0 ) + ,.xy_dsp_dout1 ( ch2_xy_dsp_dout1 ) + ,.xy_dsp_dout2 ( ch2_xy_dsp_dout2 ) + ,.xy_dsp_dout3 ( ch2_xy_dsp_dout3 ) + ,.xy_dsp_dout4 ( ch2_xy_dsp_dout4 ) + ,.xy_dsp_dout5 ( ch2_xy_dsp_dout5 ) + ,.xy_dsp_dout6 ( ch2_xy_dsp_dout6 ) + ,.xy_dsp_dout7 ( ch2_xy_dsp_dout7 ) + ,.xy_dsp_dout8 ( ch2_xy_dsp_dout8 ) + ,.xy_dsp_dout9 ( ch2_xy_dsp_dout9 ) + ,.xy_dsp_dout10 ( ch2_xy_dsp_dout10 ) + ,.xy_dsp_dout11 ( ch2_xy_dsp_dout11 ) + ,.xy_dsp_dout12 ( ch2_xy_dsp_dout12 ) + ,.xy_dsp_dout13 ( ch2_xy_dsp_dout13 ) + ,.xy_dsp_dout14 ( ch2_xy_dsp_dout14 ) + ,.xy_dsp_dout15 ( ch2_xy_dsp_dout15 ) + ,.xy_dsp_dout_vld ( ch2_xy_dsp_dout_vld ) + `endif + `ifdef CHANNEL_Z_ON + ,.z_dsp_dout0 ( ch2_z_dsp_dout0 ) + ,.z_dsp_dout1 ( ch2_z_dsp_dout1 ) + ,.z_dsp_dout2 ( ch2_z_dsp_dout2 ) + ,.z_dsp_dout3 ( ch2_z_dsp_dout3 ) + `endif + ); +//--------------------------------------------------------------------------------------------- +// channel 2 instantiation end +//--------------------------------------------------------------------------------------------- + +//--------------------------------------------------------------------------------------------- +// channel 3 instantiation start +//--------------------------------------------------------------------------------------------- + +wire [15:0] ch3_awg_data_i ; +wire [15:0] ch3_awg_data_q ; +wire [15:0] ch3_awg_vld ; +`ifdef CHANNEL_XY_ON +wire ch3_xy_dsp_dout_vld ; +`endif + +channel_top U3_channel_top ( + .clk ( clk ) + ,.rst_n ( ch3_rstn_o ) + ,.sync_int ( sync_int ) + ,.dec_o_ilegl ( ch3_dec_err ) + ,.agu_o_addr_unalgn ( ch3_ldst_addr_unalgn ) + ,.awg_proc_cft ( ch3_proc_cft ) + ,.mcu_ext_o_intr ( ch3_exit_irq ) + ,.fb_st_in ( ch3_feedback ) + //ch1 itcm addr space --> 0x0130_0000 ~ 0x013F_FFFF + ,.itcm_i_rwaddr ( slv[19].addr[14:0] ) + ,.itcm_i_wrdata ( slv[19].din ) + ,.itcm_i_wren ( slv[19].wren ) + ,.itcm_i_wrmask ( 4'h0 ) + ,.itcm_i_rden ( slv[19].rden ) + ,.itcm_o_rddata ( slv[19].dout ) + //ch1 itcm addr space --> 0x0140_0000 ~ 0x014F_FFFF + ,.dtcm_i_rwaddr ( slv[20].addr[14:0] ) + ,.dtcm_i_wrdata ( slv[20].din ) + ,.dtcm_i_wren ( slv[20].wren ) + ,.dtcm_i_wrmask ( 4'h0 ) + ,.dtcm_i_rden ( slv[20].rden ) + ,.dtcm_o_rddata ( slv[20].dout ) + //ch1 dtcm addr space --> 0x0150_0000 ~ 0x015F_FFFF + ,.ctrl_rwaddr ( slv[21].addr[15:0] ) + ,.ctrl_wrdata ( slv[21].din ) + ,.ctrl_wren ( slv[21].wren ) + ,.ctrl_rden ( slv[21].rden ) + ,.ctrl_rddata ( slv[21].dout ) + //ch1 envelope ID addr space --> 0x0160_0000 ~ 0x016F_FFFF + ,.enve_id_brwaddr ( slv[22].addr[7:0] ) + ,.enve_id_bwrdata ( slv[22].din ) + ,.enve_id_bwren ( slv[22].wren ) + ,.enve_id_brden ( slv[22].rden ) + ,.enve_id_brddata ( slv[22].dout ) + //ch1 envelope memory addr space --> 0x0170_0000 ~ 0x0105F_FFFF + ,.enve_brwaddr ( slv[23].addr[14:0] ) + ,.enve_bwrdata ( slv[23].din ) + ,.enve_bwren ( slv[23].wren ) + ,.enve_brden ( slv[23].rden ) + ,.enve_brddata ( slv[23].dout ) + //ch1 dac regfile addr space --> 0x0180_0000 ~ 0x018F_FFFFF + ,.dac_rwaddr ( slv[24].addr[15:0] ) + ,.dac_wrdata ( slv[24].din ) + ,.dac_wren ( slv[24].wren ) + ,.dac_rden ( slv[24].rden ) + ,.dac_rddata ( slv[24].dout ) + ,.dac_Prbs ( ch3_dac_Prbs ) + ,.dac_Set0 ( ch3_dac_Set0 ) + ,.dac_Set1 ( ch3_dac_Set1 ) + ,.dac_Set2 ( ch3_dac_Set2 ) + ,.dac_Set3 ( ch3_dac_Set3 ) + ,.dac_Set4 ( ch3_dac_Set4 ) + ,.dac_Set5 ( ch3_dac_Set5 ) + ,.dac_Set6 ( ch3_dac_Set6 ) + ,.dac_Set7 ( ch3_dac_Set7 ) + ,.dac_Set8 ( ch3_dac_Set8 ) + ,.dac_Set9 ( ch3_dac_Set9 ) + ,.dac_Set10 ( ch3_dac_Set10 ) + ,.dac_Set11 ( ch3_dac_Set11 ) + ,.dac_Set12 ( ch3_dac_Set12 ) + ,.dac_Set13 ( ch3_dac_Set13 ) + ,.dac_Set14 ( ch3_dac_Set14 ) + ,.dac_Set15 ( ch3_dac_Set15 ) + ,.dac_addr ( ch3_dac_addr ) + ,.dac_dw ( ch3_dac_dw ) + ,.dac_ref ( ch3_dac_ref ) + ,.dac_Prbs_rst0 ( ch3_dac_Prbs_rst0 ) + ,.dac_Prbs_set0 ( ch3_dac_Prbs_set0 ) + ,.dac_Prbs_rst1 ( ch3_dac_Prbs_rst1 ) + ,.dac_Prbs_set1 ( ch3_dac_Prbs_set1 ) + ,.dac_Cal_sig ( ch3_dac_Cal_sig ) + ,.dac_Cal_rstn ( ch3_dac_Cal_rstn ) + ,.Cal_div_rstn ( ch3_dac_Cal_div_rstn ) + ,.dac_Cal_end ( ch3_dac_Cal_end ) + ,.awg_data_i_o ( ch3_awg_data_i ) + ,.awg_data_q_o ( ch3_awg_data_q ) + ,.awg_vld_o ( ch3_awg_vld ) + `ifdef CHANNEL_XY_ON + ,.xy_dsp_dout0 ( ch3_xy_dsp_dout0 ) + ,.xy_dsp_dout1 ( ch3_xy_dsp_dout1 ) + ,.xy_dsp_dout2 ( ch3_xy_dsp_dout2 ) + ,.xy_dsp_dout3 ( ch3_xy_dsp_dout3 ) + ,.xy_dsp_dout4 ( ch3_xy_dsp_dout4 ) + ,.xy_dsp_dout5 ( ch3_xy_dsp_dout5 ) + ,.xy_dsp_dout6 ( ch3_xy_dsp_dout6 ) + ,.xy_dsp_dout7 ( ch3_xy_dsp_dout7 ) + ,.xy_dsp_dout8 ( ch3_xy_dsp_dout8 ) + ,.xy_dsp_dout9 ( ch3_xy_dsp_dout9 ) + ,.xy_dsp_dout10 ( ch3_xy_dsp_dout10 ) + ,.xy_dsp_dout11 ( ch3_xy_dsp_dout11 ) + ,.xy_dsp_dout12 ( ch3_xy_dsp_dout12 ) + ,.xy_dsp_dout13 ( ch3_xy_dsp_dout13 ) + ,.xy_dsp_dout14 ( ch3_xy_dsp_dout14 ) + ,.xy_dsp_dout15 ( ch3_xy_dsp_dout15 ) + ,.xy_dsp_dout_vld ( ch3_xy_dsp_dout_vld ) + `endif + `ifdef CHANNEL_Z_ON + ,.z_dsp_dout0 ( ch3_z_dsp_dout0 ) + ,.z_dsp_dout1 ( ch3_z_dsp_dout1 ) + ,.z_dsp_dout2 ( ch3_z_dsp_dout2 ) + ,.z_dsp_dout3 ( ch3_z_dsp_dout3 ) + `endif + ); +//--------------------------------------------------------------------------------------------- +// channel 3 instantiation end +//--------------------------------------------------------------------------------------------- +`endif +//--------------------------------------------------------------------------------------------- +// debug module instantiation start +//--------------------------------------------------------------------------------------------- + +wire ch0_dsp_vld ; +wire [15 :0] ch0_dsp_data [15:0] ; +wire ch1_dsp_vld ; +wire [15 :0] ch1_dsp_data [15:0] ; +wire ch2_dsp_vld ; +wire [15 :0] ch2_dsp_data [15:0] ; +wire ch3_dsp_vld ; +wire [15 :0] ch3_dsp_data [15:0] ; + + +//channel 0 xy dsp data +assign ch0_dsp_vld = ch0_xy_dsp_dout_vld ; +assign ch0_dsp_data[0 ] = ch0_xy_dsp_dout0 ; +assign ch0_dsp_data[1 ] = ch0_xy_dsp_dout1 ; +assign ch0_dsp_data[2 ] = ch0_xy_dsp_dout2 ; +assign ch0_dsp_data[3 ] = ch0_xy_dsp_dout3 ; +assign ch0_dsp_data[4 ] = ch0_xy_dsp_dout4 ; +assign ch0_dsp_data[5 ] = ch0_xy_dsp_dout5 ; +assign ch0_dsp_data[6 ] = ch0_xy_dsp_dout6 ; +assign ch0_dsp_data[7 ] = ch0_xy_dsp_dout7 ; +assign ch0_dsp_data[8 ] = ch0_xy_dsp_dout8 ; +assign ch0_dsp_data[9 ] = ch0_xy_dsp_dout9 ; +assign ch0_dsp_data[10] = ch0_xy_dsp_dout10 ; +assign ch0_dsp_data[11] = ch0_xy_dsp_dout11 ; +assign ch0_dsp_data[12] = ch0_xy_dsp_dout12 ; +assign ch0_dsp_data[13] = ch0_xy_dsp_dout13 ; +assign ch0_dsp_data[14] = ch0_xy_dsp_dout14 ; +assign ch0_dsp_data[15] = ch0_xy_dsp_dout15 ; + +`ifdef CHANNEL_IS_FOUR +//channel 1 xy dsp data +assign ch1_dsp_vld = ch1_xy_dsp_dout_vld ; +assign ch1_dsp_data[0 ] = ch1_xy_dsp_dout0 ; +assign ch1_dsp_data[1 ] = ch1_xy_dsp_dout1 ; +assign ch1_dsp_data[2 ] = ch1_xy_dsp_dout2 ; +assign ch1_dsp_data[3 ] = ch1_xy_dsp_dout3 ; +assign ch1_dsp_data[4 ] = ch1_xy_dsp_dout4 ; +assign ch1_dsp_data[5 ] = ch1_xy_dsp_dout5 ; +assign ch1_dsp_data[6 ] = ch1_xy_dsp_dout6 ; +assign ch1_dsp_data[7 ] = ch1_xy_dsp_dout7 ; +assign ch1_dsp_data[8 ] = ch1_xy_dsp_dout8 ; +assign ch1_dsp_data[9 ] = ch1_xy_dsp_dout9 ; +assign ch1_dsp_data[10] = ch1_xy_dsp_dout10 ; +assign ch1_dsp_data[11] = ch1_xy_dsp_dout11 ; +assign ch1_dsp_data[12] = ch1_xy_dsp_dout12 ; +assign ch1_dsp_data[13] = ch1_xy_dsp_dout13 ; +assign ch1_dsp_data[14] = ch1_xy_dsp_dout14 ; +assign ch1_dsp_data[15] = ch1_xy_dsp_dout15 ; +//channel 2 xy dsp data +assign ch2_dsp_vld = ch2_xy_dsp_dout_vld ; +assign ch2_dsp_data[0 ] = ch2_xy_dsp_dout0 ; +assign ch2_dsp_data[1 ] = ch2_xy_dsp_dout1 ; +assign ch2_dsp_data[2 ] = ch2_xy_dsp_dout2 ; +assign ch2_dsp_data[3 ] = ch2_xy_dsp_dout3 ; +assign ch2_dsp_data[4 ] = ch2_xy_dsp_dout4 ; +assign ch2_dsp_data[5 ] = ch2_xy_dsp_dout5 ; +assign ch2_dsp_data[6 ] = ch2_xy_dsp_dout6 ; +assign ch2_dsp_data[7 ] = ch2_xy_dsp_dout7 ; +assign ch2_dsp_data[8 ] = ch2_xy_dsp_dout8 ; +assign ch2_dsp_data[9 ] = ch2_xy_dsp_dout9 ; +assign ch2_dsp_data[10] = ch2_xy_dsp_dout10 ; +assign ch2_dsp_data[11] = ch2_xy_dsp_dout11 ; +assign ch2_dsp_data[12] = ch2_xy_dsp_dout12 ; +assign ch2_dsp_data[13] = ch2_xy_dsp_dout13 ; +assign ch2_dsp_data[14] = ch2_xy_dsp_dout14 ; +assign ch2_dsp_data[15] = ch2_xy_dsp_dout15 ; +//channel 3 xy dsp data +assign ch3_dsp_vld = ch3_xy_dsp_dout_vld ; +assign ch3_dsp_data[0 ] = ch3_xy_dsp_dout0 ; +assign ch3_dsp_data[1 ] = ch3_xy_dsp_dout1 ; +assign ch3_dsp_data[2 ] = ch3_xy_dsp_dout2 ; +assign ch3_dsp_data[3 ] = ch3_xy_dsp_dout3 ; +assign ch3_dsp_data[4 ] = ch3_xy_dsp_dout4 ; +assign ch3_dsp_data[5 ] = ch3_xy_dsp_dout5 ; +assign ch3_dsp_data[6 ] = ch3_xy_dsp_dout6 ; +assign ch3_dsp_data[7 ] = ch3_xy_dsp_dout7 ; +assign ch3_dsp_data[8 ] = ch3_xy_dsp_dout8 ; +assign ch3_dsp_data[9 ] = ch3_xy_dsp_dout9 ; +assign ch3_dsp_data[10] = ch3_xy_dsp_dout10 ; +assign ch3_dsp_data[11] = ch3_xy_dsp_dout11 ; +assign ch3_dsp_data[12] = ch3_xy_dsp_dout12 ; +assign ch3_dsp_data[13] = ch3_xy_dsp_dout13 ; +assign ch3_dsp_data[14] = ch3_xy_dsp_dout14 ; +assign ch3_dsp_data[15] = ch3_xy_dsp_dout15 ; +`endif + +//When designed for single-channel, open this macro +`ifndef CHANNEL_IS_FOUR +//channel 1 xy dsp data +assign ch1_dsp_vld = 1'b0 ; +assign ch1_dsp_data[0 ] = 16'h0 ; +assign ch1_dsp_data[1 ] = 16'h0 ; +assign ch1_dsp_data[2 ] = 16'h0 ; +assign ch1_dsp_data[3 ] = 16'h0 ; +assign ch1_dsp_data[4 ] = 16'h0 ; +assign ch1_dsp_data[5 ] = 16'h0 ; +assign ch1_dsp_data[6 ] = 16'h0 ; +assign ch1_dsp_data[7 ] = 16'h0 ; +assign ch1_dsp_data[8 ] = 16'h0 ; +assign ch1_dsp_data[9 ] = 16'h0 ; +assign ch1_dsp_data[10] = 16'h0 ; +assign ch1_dsp_data[11] = 16'h0 ; +assign ch1_dsp_data[12] = 16'h0 ; +assign ch1_dsp_data[13] = 16'h0 ; +assign ch1_dsp_data[14] = 16'h0 ; +assign ch1_dsp_data[15] = 16'h0 ; +//channel 2 xy dsp data +assign ch2_dsp_vld = 1'b0 ; +assign ch2_dsp_data[0 ] = 16'h0 ; +assign ch2_dsp_data[1 ] = 16'h0 ; +assign ch2_dsp_data[2 ] = 16'h0 ; +assign ch2_dsp_data[3 ] = 16'h0 ; +assign ch2_dsp_data[4 ] = 16'h0 ; +assign ch2_dsp_data[5 ] = 16'h0 ; +assign ch2_dsp_data[6 ] = 16'h0 ; +assign ch2_dsp_data[7 ] = 16'h0 ; +assign ch2_dsp_data[8 ] = 16'h0 ; +assign ch2_dsp_data[9 ] = 16'h0 ; +assign ch2_dsp_data[10] = 16'h0 ; +assign ch2_dsp_data[11] = 16'h0 ; +assign ch2_dsp_data[12] = 16'h0 ; +assign ch2_dsp_data[13] = 16'h0 ; +assign ch2_dsp_data[14] = 16'h0 ; +assign ch2_dsp_data[15] = 16'h0 ; +//channel 3 xy dsp data +assign ch3_dsp_vld = 1'b0 ; +assign ch3_dsp_data[0 ] = 16'h0 ; +assign ch3_dsp_data[1 ] = 16'h0 ; +assign ch3_dsp_data[2 ] = 16'h0 ; +assign ch3_dsp_data[3 ] = 16'h0 ; +assign ch3_dsp_data[4 ] = 16'h0 ; +assign ch3_dsp_data[5 ] = 16'h0 ; +assign ch3_dsp_data[6 ] = 16'h0 ; +assign ch3_dsp_data[7 ] = 16'h0 ; +assign ch3_dsp_data[8 ] = 16'h0 ; +assign ch3_dsp_data[9 ] = 16'h0 ; +assign ch3_dsp_data[10] = 16'h0 ; +assign ch3_dsp_data[11] = 16'h0 ; +assign ch3_dsp_data[12] = 16'h0 ; +assign ch3_dsp_data[13] = 16'h0 ; +assign ch3_dsp_data[14] = 16'h0 ; +assign ch3_dsp_data[15] = 16'h0 ; + +wire [15:0] ch1_awg_data_i = 16'b0 ; +wire [15:0] ch1_awg_data_q = 16'b0 ; +wire [0 :0] ch1_awg_vld = 1'b0 ; +wire [15:0] ch2_awg_data_i = 16'b0 ; +wire [15:0] ch2_awg_data_q = 16'b0 ; +wire [0 :0] ch2_awg_vld = 1'b0 ; +wire [15:0] ch3_awg_data_i = 16'b0 ; +wire [15:0] ch3_awg_data_q = 16'b0 ; +wire [0 :0] ch3_awg_vld = 1'b0 ; +`endif + +debug_top U_debug_top ( + //system port + .clk ( clk ) + ,.rst_n ( pll_rstn_o ) + ,.debug_enable ( dbg_enable ) + ,.debug_data_sel ( dbg_data_sel ) + ,.debug_ch_sel ( dbg_ch_sel ) + ,.debug_update ( dbg_upd ) + ,.ch0_mod_data_i ( ch0_awg_data_i ) + ,.ch0_mod_data_q ( ch0_awg_data_q ) + ,.ch0_mod_vld ( ch0_awg_vld ) + ,.ch1_mod_data_i ( ch1_awg_data_i ) + ,.ch1_mod_data_q ( ch1_awg_data_q ) + ,.ch1_mod_vld ( ch1_awg_vld ) + ,.ch2_mod_data_i ( ch2_awg_data_i ) + ,.ch2_mod_data_q ( ch2_awg_data_q ) + ,.ch2_mod_vld ( ch2_awg_vld ) + ,.ch3_mod_data_i ( ch3_awg_data_i ) + ,.ch3_mod_data_q ( ch3_awg_data_q ) + ,.ch3_mod_vld ( ch3_awg_vld ) + ,.ch0_dsp_data ( ch0_dsp_data ) + ,.ch0_dsp_vld ( ch0_dsp_vld ) + ,.ch1_dsp_data ( ch1_dsp_data ) + ,.ch1_dsp_vld ( ch1_dsp_vld ) + ,.ch2_dsp_data ( ch2_dsp_data ) + ,.ch2_dsp_vld ( ch2_dsp_vld ) + ,.ch3_dsp_data ( ch3_dsp_data ) + ,.ch3_dsp_vld ( ch3_dsp_vld ) + ,.dbg_sram_in ( slv[25].slave ) +); + +//--------------------------------------------------------------------------------------------- +// debug module instantiation end +//--------------------------------------------------------------------------------------------- +endmodule + +`include "../define/chip_undefine.v" diff --git a/rtl/top/xyz_chip_top.v b/rtl/top/xyz_chip_top.v new file mode 100644 index 0000000..5d3e5f2 --- /dev/null +++ b/rtl/top/xyz_chip_top.v @@ -0,0 +1,1529 @@ +//+FHDR-------------------------------------------------------------------------------------------------------- +// Company: +//----------------------------------------------------------------------------------------------------------------- +// File Name : xyz_chip_top.v +// Department : +// Author : pwy +// Author's Tel : +//----------------------------------------------------------------------------------------------------------------- +// Relese History +// Version Date Author Description +// 1.2 2024-04-16 pwy XYZ control the top-level module +//----------------------------------------------------------------------------------------------------------------- +// Keywords : +// +//----------------------------------------------------------------------------------------------------------------- +// Parameter +// +//----------------------------------------------------------------------------------------------------------------- +// Purpose : +// +//----------------------------------------------------------------------------------------------------------------- +// Target Device: +// Tool versions: +//----------------------------------------------------------------------------------------------------------------- +// Reuse Issues +// Reset Strategy: +// Clock Domains: +// Critical Timing: +// Asynchronous I/F: +// Synthesizable (y/n): +// Other: +//-FHDR-------------------------------------------------------------------------------------------------------- + +`include "../define/chip_define.v" + +module xyz_chip_top ( + + //+++++++++++++++++++++++++++++++++++++++++++++// + // PAD Strat // + //+++++++++++++++++++++++++++++++++++++++++++++// + input PI_async_rstn // hardware Reset, active low + //sync + ,input PI_sync_in // Chip synchronization signal input, high pulse valid + ,output PO_sync_out // Chip synchronization signal output, high pulse valid + //Feedback signal + ,input [1 :0] PI_ch0_feedback // Ch0 Feedback signals from the readout chip + `ifdef CHANNEL_IS_FOUR + ,input [1 :0] PI_ch1_feedback // Ch1 Feedback signals from the readout chip + ,input [1 :0] PI_ch2_feedback // Ch2 Feedback signals from the readout chip + ,input [1 :0] PI_ch3_feedback // Ch3 Feedback signals from the readout chip + `endif + //config chip id + ,input [4 :0] PI_cfgid // During power-on initialization, the IO configuration + // values are read as the chip ID number + //spi port + ,input PI_sclk // Spi Clock + ,input PI_csn // Spi Chip Select active low + ,input PI_mosi // Spi Mosi + ,output PO_miso // Spi Miso + //irq + ,output PO_irq // Interrupt signal in the chip, high level active + //+++++++++++++++++++++++++++++++++++++++++++++// + // PAD End // + //+++++++++++++++++++++++++++++++++++++++++++++// + //+++++++++++++++++++++++++++++++++++++++++++++// + // PIN Strat // + //+++++++++++++++++++++++++++++++++++++++++++++// + //-------------------------clcok pin from pll------------------------------------------------- + ,input clk // System Main Clock + //-------------------------Power on reset pin from por---------------------------------------- + ,input por_rstn // Power on reset, active low + //------------------------------digital IO---------------------------------------------------- + //------------------------------PLL cfg pin---------------------------------------------------- + ,output ref_sel // Clock source selection for a frequency divider; + // 1'b0:External clock source + // 1'b1:internal phase-locked loop clock source + ,output ref_en // Input reference clock enable + // 1'b0:enable,1'b1:disable + ,output ref_s2d_en // Referenced clock differential to single-ended conversion enable + // 1'b0:enable,1'b1:disable + ,output [6 :0] p_cnt // P counter + ,output pfd_delay // PFD Dead Zone + ,output pfd_dff_Set // Setting the PFD register,active high + ,output pfd_dff_4and // PFD output polarity + ,output [3 :0] spd_div // SPD Frequency Divider + ,output spd_pulse_width // Pulse Width of SPD + ,output spd_pulse_sw // Pulse sw of SPD + ,output cpc_sel // current source selection + ,output [1 :0] swcp_i // PTAT current switch + ,output [3 :0] sw_ptat_r // PTAT current adjustment + ,output [1 :0] sw_fll_cpi // Phase-locked loop charge pump current + ,output sw_fll_delay // PLL Dead Zone + ,output pfd_sel // PFD Loop selection + ,output spd_sel // SPD Loop selection + ,output fll_sel // FLL Loop selection + ,output vco_tc // VCO temperature compensation + ,output vco_tcr // VCO temperature compensation resistor + ,output vco_gain_adj // VCO gain adjustment + ,output vco_gain_adj_r // VCO gain adjustment resistor + ,output [2 :0] vco_cur_adj // VCO current adjustment + ,output vco_buff_en // VCO buff enable,active high + ,output vco_en // VCO enable,active high + ,output [2 :0] pll_dpwr_adj // PLL frequency division output power adjustment + ,output [6 :0] vco_fb_adj // VCO frequency band adjustment + ,output afc_en // AFC enable + ,output afc_shutdown // AFC module shutdown signal + ,output [0 :0] afc_det_speed // AFC detection speed + ,output [0 :0] flag_out_sel // Read and choose the signs + ,output afc_reset // AFC reset + ,output [10 :0] afc_cnt // AFC frequency band adjustment function counter + // counting time adjustment + ,output [10 :0] afc_ld_cnt // Adjust the counting time of the AFC lock detection + // feature counter + ,output [3 :0] afc_pres // Adjusting the resolution of the AFC comparator + ,output [14 :0] afc_ld_tcc // AFC Lock Detection Function Target Cycle Count + ,output [14 :0] afc_fb_tcc // Target number of cycles for AFC frequency band + // adjustment function + ,output sync_clr // PLL div sync clr,low active + ,output pll_rstn // PLL reset,active low + ,output [0 :0] div_rstn_sel // div rstn select, 1'b0: ext clear, 1'b1:inter pll lock + ,output [1 :0] test_clk_sel // test clk select, 2'b00:DIV1 clk, 2'b01:DIV2 clk, 2'b10:DIV4 clk, 2'b11:DIV8 clk + ,output [0 :0] test_clk_oen // test clk output enable, 1'b0:disenable, 1'b1:enable + ,output [7 :0] dig_clk_sel // digital main clk select, one hot code,bit[0]-->0 degree phase,bit[1]-->45 degree phase.....bit[7]-->315degree phae + ,output clkrx_pdn // CLock Rx Power Down + ,input pll_lock // PLL LOCK + //------------------------------Ch0 DAC cfg pin---------------------------------------------------- + ,output [2 :0] ch0_dac_addr + ,output [2 :0] ch0_dac_dw + ,output [8 :0] ch0_dac_ref + ,output [16 :0] ch0_dac_Prbs_rst0 + ,output [16 :0] ch0_dac_Prbs_set0 + ,output [16 :0] ch0_dac_Prbs_rst1 + ,output [16 :0] ch0_dac_Prbs_set1 + ,output ch0_dac_Cal_sig + ,output ch0_dac_Cal_rstn + ,output ch0_dac_Cal_div_rstn + ,input ch0_dac_Cal_end + `ifdef CHANNEL_IS_FOUR + //------------------------------Ch1 DAC cfg pin---------------------------------------------------- + ,output [2 :0] ch1_dac_addr + ,output [2 :0] ch1_dac_dw + ,output [8 :0] ch1_dac_ref + ,output [16 :0] ch1_dac_Prbs_rst0 + ,output [16 :0] ch1_dac_Prbs_set0 + ,output [16 :0] ch1_dac_Prbs_rst1 + ,output [16 :0] ch1_dac_Prbs_set1 + ,output ch1_dac_Cal_sig + ,output ch1_dac_Cal_rstn + ,output ch1_dac_Cal_div_rstn + ,output ch1_dac_Digitalclk + ,input ch1_dac_Cal_end + //------------------------------Ch2 DAC cfg pin---------------------------------------------------- + ,output [2 :0] ch2_dac_addr + ,output [2 :0] ch2_dac_dw + ,output [8 :0] ch2_dac_ref + ,output [16 :0] ch2_dac_Prbs_rst0 + ,output [16 :0] ch2_dac_Prbs_set0 + ,output [16 :0] ch2_dac_Prbs_rst1 + ,output [16 :0] ch2_dac_Prbs_set1 + ,output ch2_dac_Cal_sig + ,output ch2_dac_Cal_rstn + ,output ch2_dac_Cal_div_rstn + ,output ch2_dac_Digitalclk + ,input ch2_dac_Cal_end + //------------------------------Ch3 DAC cfg pin---------------------------------------------------- + ,output [2 :0] ch3_dac_addr + ,output [2 :0] ch3_dac_dw + ,output [8 :0] ch3_dac_ref + ,output [16 :0] ch3_dac_Prbs_rst0 + ,output [16 :0] ch3_dac_Prbs_set0 + ,output [16 :0] ch3_dac_Prbs_rst1 + ,output [16 :0] ch3_dac_Prbs_set1 + ,output ch3_dac_Cal_sig + ,output ch3_dac_Cal_rstn + ,output ch3_dac_Cal_div_rstn + ,output ch3_dac_Digitalclk + ,input ch3_dac_Cal_end + `endif + //------------------------------Ch0 DSP data out---------------------------------------------------- + `ifdef CHANNEL_XY_ON + ,output [14:0] ch0_xy_A_DEM_MSB_OUT0 + ,output [14:0] ch0_xy_A_DEM_MSB_OUT1 + ,output [14:0] ch0_xy_A_DEM_MSB_OUT2 + ,output [14:0] ch0_xy_A_DEM_MSB_OUT3 + ,output [14:0] ch0_xy_A_DEM_MSB_OUT4 + ,output [14:0] ch0_xy_A_DEM_MSB_OUT5 + ,output [14:0] ch0_xy_A_DEM_MSB_OUT6 + ,output [14:0] ch0_xy_A_DEM_MSB_OUT7 + ,output [14:0] ch0_xy_B_DEM_MSB_OUT0 + ,output [14:0] ch0_xy_B_DEM_MSB_OUT1 + ,output [14:0] ch0_xy_B_DEM_MSB_OUT2 + ,output [14:0] ch0_xy_B_DEM_MSB_OUT3 + ,output [14:0] ch0_xy_B_DEM_MSB_OUT4 + ,output [14:0] ch0_xy_B_DEM_MSB_OUT5 + ,output [14:0] ch0_xy_B_DEM_MSB_OUT6 + ,output [14:0] ch0_xy_B_DEM_MSB_OUT7 + ,output [6 :0] ch0_xy_A_DEM_ISB_OUT0 + ,output [6 :0] ch0_xy_A_DEM_ISB_OUT1 + ,output [6 :0] ch0_xy_A_DEM_ISB_OUT2 + ,output [6 :0] ch0_xy_A_DEM_ISB_OUT3 + ,output [6 :0] ch0_xy_A_DEM_ISB_OUT4 + ,output [6 :0] ch0_xy_A_DEM_ISB_OUT5 + ,output [6 :0] ch0_xy_A_DEM_ISB_OUT6 + ,output [6 :0] ch0_xy_A_DEM_ISB_OUT7 + ,output [6 :0] ch0_xy_B_DEM_ISB_OUT0 + ,output [6 :0] ch0_xy_B_DEM_ISB_OUT1 + ,output [6 :0] ch0_xy_B_DEM_ISB_OUT2 + ,output [6 :0] ch0_xy_B_DEM_ISB_OUT3 + ,output [6 :0] ch0_xy_B_DEM_ISB_OUT4 + ,output [6 :0] ch0_xy_B_DEM_ISB_OUT5 + ,output [6 :0] ch0_xy_B_DEM_ISB_OUT6 + ,output [6 :0] ch0_xy_B_DEM_ISB_OUT7 + ,output [8 :0] ch0_xy_A_DEM_LSB_OUT0 + ,output [8 :0] ch0_xy_A_DEM_LSB_OUT1 + ,output [8 :0] ch0_xy_A_DEM_LSB_OUT2 + ,output [8 :0] ch0_xy_A_DEM_LSB_OUT3 + ,output [8 :0] ch0_xy_A_DEM_LSB_OUT4 + ,output [8 :0] ch0_xy_A_DEM_LSB_OUT5 + ,output [8 :0] ch0_xy_A_DEM_LSB_OUT6 + ,output [8 :0] ch0_xy_A_DEM_LSB_OUT7 + ,output [8 :0] ch0_xy_B_DEM_LSB_OUT0 + ,output [8 :0] ch0_xy_B_DEM_LSB_OUT1 + ,output [8 :0] ch0_xy_B_DEM_LSB_OUT2 + ,output [8 :0] ch0_xy_B_DEM_LSB_OUT3 + ,output [8 :0] ch0_xy_B_DEM_LSB_OUT4 + ,output [8 :0] ch0_xy_B_DEM_LSB_OUT5 + ,output [8 :0] ch0_xy_B_DEM_LSB_OUT6 + ,output [8 :0] ch0_xy_B_DEM_LSB_OUT7 + `endif + `ifdef CHANNEL_Z_ON + ,output [14 :0] ch0_z_DEM_MSB_OUT0 + ,output [14 :0] ch0_z_DEM_MSB_OUT1 + ,output [14 :0] ch0_z_DEM_MSB_OUT2 + ,output [14 :0] ch0_z_DEM_MSB_OUT3 + ,output [6 :0] ch0_z_DEM_ISB_OUT0 + ,output [6 :0] ch0_z_DEM_ISB_OUT1 + ,output [6 :0] ch0_z_DEM_ISB_OUT2 + ,output [6 :0] ch0_z_DEM_ISB_OUT3 + ,output [8 :0] ch0_z_DEM_LSB_OUT0 + ,output [8 :0] ch0_z_DEM_LSB_OUT1 + ,output [8 :0] ch0_z_DEM_LSB_OUT2 + ,output [8 :0] ch0_z_DEM_LSB_OUT3 + `endif + `ifdef CHANNEL_IS_FOUR + //------------------------------Ch1 DSP data out---------------------------------------------------- + `ifdef CHANNEL_XY_ON + ,output [14:0] ch1_xy_A_DEM_MSB_OUT0 + ,output [14:0] ch1_xy_A_DEM_MSB_OUT1 + ,output [14:0] ch1_xy_A_DEM_MSB_OUT2 + ,output [14:0] ch1_xy_A_DEM_MSB_OUT3 + ,output [14:0] ch1_xy_A_DEM_MSB_OUT4 + ,output [14:0] ch1_xy_A_DEM_MSB_OUT5 + ,output [14:0] ch1_xy_A_DEM_MSB_OUT6 + ,output [14:0] ch1_xy_A_DEM_MSB_OUT7 + ,output [14:0] ch1_xy_B_DEM_MSB_OUT0 + ,output [14:0] ch1_xy_B_DEM_MSB_OUT1 + ,output [14:0] ch1_xy_B_DEM_MSB_OUT2 + ,output [14:0] ch1_xy_B_DEM_MSB_OUT3 + ,output [14:0] ch1_xy_B_DEM_MSB_OUT4 + ,output [14:0] ch1_xy_B_DEM_MSB_OUT5 + ,output [14:0] ch1_xy_B_DEM_MSB_OUT6 + ,output [14:0] ch1_xy_B_DEM_MSB_OUT7 + ,output [6 :0] ch1_xy_A_DEM_ISB_OUT0 + ,output [6 :0] ch1_xy_A_DEM_ISB_OUT1 + ,output [6 :0] ch1_xy_A_DEM_ISB_OUT2 + ,output [6 :0] ch1_xy_A_DEM_ISB_OUT3 + ,output [6 :0] ch1_xy_A_DEM_ISB_OUT4 + ,output [6 :0] ch1_xy_A_DEM_ISB_OUT5 + ,output [6 :0] ch1_xy_A_DEM_ISB_OUT6 + ,output [6 :0] ch1_xy_A_DEM_ISB_OUT7 + ,output [6 :0] ch1_xy_B_DEM_ISB_OUT0 + ,output [6 :0] ch1_xy_B_DEM_ISB_OUT1 + ,output [6 :0] ch1_xy_B_DEM_ISB_OUT2 + ,output [6 :0] ch1_xy_B_DEM_ISB_OUT3 + ,output [6 :0] ch1_xy_B_DEM_ISB_OUT4 + ,output [6 :0] ch1_xy_B_DEM_ISB_OUT5 + ,output [6 :0] ch1_xy_B_DEM_ISB_OUT6 + ,output [6 :0] ch1_xy_B_DEM_ISB_OUT7 + ,output [8 :0] ch1_xy_A_DEM_LSB_OUT0 + ,output [8 :0] ch1_xy_A_DEM_LSB_OUT1 + ,output [8 :0] ch1_xy_A_DEM_LSB_OUT2 + ,output [8 :0] ch1_xy_A_DEM_LSB_OUT3 + ,output [8 :0] ch1_xy_A_DEM_LSB_OUT4 + ,output [8 :0] ch1_xy_A_DEM_LSB_OUT5 + ,output [8 :0] ch1_xy_A_DEM_LSB_OUT6 + ,output [8 :0] ch1_xy_A_DEM_LSB_OUT7 + ,output [8 :0] ch1_xy_B_DEM_LSB_OUT0 + ,output [8 :0] ch1_xy_B_DEM_LSB_OUT1 + ,output [8 :0] ch1_xy_B_DEM_LSB_OUT2 + ,output [8 :0] ch1_xy_B_DEM_LSB_OUT3 + ,output [8 :0] ch1_xy_B_DEM_LSB_OUT4 + ,output [8 :0] ch1_xy_B_DEM_LSB_OUT5 + ,output [8 :0] ch1_xy_B_DEM_LSB_OUT6 + ,output [8 :0] ch1_xy_B_DEM_LSB_OUT7 + `endif + `ifdef CHANNEL_Z_ON + ,output [14 :0] ch1_z_DEM_MSB_OUT0 + ,output [14 :0] ch1_z_DEM_MSB_OUT1 + ,output [14 :0] ch1_z_DEM_MSB_OUT2 + ,output [14 :0] ch1_z_DEM_MSB_OUT3 + ,output [6 :0] ch1_z_DEM_ISB_OUT0 + ,output [6 :0] ch1_z_DEM_ISB_OUT1 + ,output [6 :0] ch1_z_DEM_ISB_OUT2 + ,output [6 :0] ch1_z_DEM_ISB_OUT3 + ,output [8 :0] ch1_z_DEM_LSB_OUT0 + ,output [8 :0] ch1_z_DEM_LSB_OUT1 + ,output [8 :0] ch1_z_DEM_LSB_OUT2 + ,output [8 :0] ch1_z_DEM_LSB_OUT3 + `endif + //------------------------------Ch2 DSP data out---------------------------------------------------- + `ifdef CHANNEL_XY_ON + ,output [14:0] ch2_xy_A_DEM_MSB_OUT0 + ,output [14:0] ch2_xy_A_DEM_MSB_OUT1 + ,output [14:0] ch2_xy_A_DEM_MSB_OUT2 + ,output [14:0] ch2_xy_A_DEM_MSB_OUT3 + ,output [14:0] ch2_xy_A_DEM_MSB_OUT4 + ,output [14:0] ch2_xy_A_DEM_MSB_OUT5 + ,output [14:0] ch2_xy_A_DEM_MSB_OUT6 + ,output [14:0] ch2_xy_A_DEM_MSB_OUT7 + ,output [14:0] ch2_xy_B_DEM_MSB_OUT0 + ,output [14:0] ch2_xy_B_DEM_MSB_OUT1 + ,output [14:0] ch2_xy_B_DEM_MSB_OUT2 + ,output [14:0] ch2_xy_B_DEM_MSB_OUT3 + ,output [14:0] ch2_xy_B_DEM_MSB_OUT4 + ,output [14:0] ch2_xy_B_DEM_MSB_OUT5 + ,output [14:0] ch2_xy_B_DEM_MSB_OUT6 + ,output [14:0] ch2_xy_B_DEM_MSB_OUT7 + ,output [6 :0] ch2_xy_A_DEM_ISB_OUT0 + ,output [6 :0] ch2_xy_A_DEM_ISB_OUT1 + ,output [6 :0] ch2_xy_A_DEM_ISB_OUT2 + ,output [6 :0] ch2_xy_A_DEM_ISB_OUT3 + ,output [6 :0] ch2_xy_A_DEM_ISB_OUT4 + ,output [6 :0] ch2_xy_A_DEM_ISB_OUT5 + ,output [6 :0] ch2_xy_A_DEM_ISB_OUT6 + ,output [6 :0] ch2_xy_A_DEM_ISB_OUT7 + ,output [6 :0] ch2_xy_B_DEM_ISB_OUT0 + ,output [6 :0] ch2_xy_B_DEM_ISB_OUT1 + ,output [6 :0] ch2_xy_B_DEM_ISB_OUT2 + ,output [6 :0] ch2_xy_B_DEM_ISB_OUT3 + ,output [6 :0] ch2_xy_B_DEM_ISB_OUT4 + ,output [6 :0] ch2_xy_B_DEM_ISB_OUT5 + ,output [6 :0] ch2_xy_B_DEM_ISB_OUT6 + ,output [6 :0] ch2_xy_B_DEM_ISB_OUT7 + ,output [8 :0] ch2_xy_A_DEM_LSB_OUT0 + ,output [8 :0] ch2_xy_A_DEM_LSB_OUT1 + ,output [8 :0] ch2_xy_A_DEM_LSB_OUT2 + ,output [8 :0] ch2_xy_A_DEM_LSB_OUT3 + ,output [8 :0] ch2_xy_A_DEM_LSB_OUT4 + ,output [8 :0] ch2_xy_A_DEM_LSB_OUT5 + ,output [8 :0] ch2_xy_A_DEM_LSB_OUT6 + ,output [8 :0] ch2_xy_A_DEM_LSB_OUT7 + ,output [8 :0] ch2_xy_B_DEM_LSB_OUT0 + ,output [8 :0] ch2_xy_B_DEM_LSB_OUT1 + ,output [8 :0] ch2_xy_B_DEM_LSB_OUT2 + ,output [8 :0] ch2_xy_B_DEM_LSB_OUT3 + ,output [8 :0] ch2_xy_B_DEM_LSB_OUT4 + ,output [8 :0] ch2_xy_B_DEM_LSB_OUT5 + ,output [8 :0] ch2_xy_B_DEM_LSB_OUT6 + ,output [8 :0] ch2_xy_B_DEM_LSB_OUT7 + `endif + `ifdef CHANNEL_Z_ON + ,output [14 :0] ch2_z_DEM_MSB_OUT0 + ,output [14 :0] ch2_z_DEM_MSB_OUT1 + ,output [14 :0] ch2_z_DEM_MSB_OUT2 + ,output [14 :0] ch2_z_DEM_MSB_OUT3 + ,output [6 :0] ch2_z_DEM_ISB_OUT0 + ,output [6 :0] ch2_z_DEM_ISB_OUT1 + ,output [6 :0] ch2_z_DEM_ISB_OUT2 + ,output [6 :0] ch2_z_DEM_ISB_OUT3 + ,output [8 :0] ch2_z_DEM_LSB_OUT0 + ,output [8 :0] ch2_z_DEM_LSB_OUT1 + ,output [8 :0] ch2_z_DEM_LSB_OUT2 + ,output [8 :0] ch2_z_DEM_LSB_OUT3 + `endif + //------------------------------Ch3 DSP data out---------------------------------------------------- + `ifdef CHANNEL_XY_ON + ,output [14:0] ch3_xy_A_DEM_MSB_OUT0 + ,output [14:0] ch3_xy_A_DEM_MSB_OUT1 + ,output [14:0] ch3_xy_A_DEM_MSB_OUT2 + ,output [14:0] ch3_xy_A_DEM_MSB_OUT3 + ,output [14:0] ch3_xy_A_DEM_MSB_OUT4 + ,output [14:0] ch3_xy_A_DEM_MSB_OUT5 + ,output [14:0] ch3_xy_A_DEM_MSB_OUT6 + ,output [14:0] ch3_xy_A_DEM_MSB_OUT7 + ,output [14:0] ch3_xy_B_DEM_MSB_OUT0 + ,output [14:0] ch3_xy_B_DEM_MSB_OUT1 + ,output [14:0] ch3_xy_B_DEM_MSB_OUT2 + ,output [14:0] ch3_xy_B_DEM_MSB_OUT3 + ,output [14:0] ch3_xy_B_DEM_MSB_OUT4 + ,output [14:0] ch3_xy_B_DEM_MSB_OUT5 + ,output [14:0] ch3_xy_B_DEM_MSB_OUT6 + ,output [14:0] ch3_xy_B_DEM_MSB_OUT7 + ,output [6 :0] ch3_xy_A_DEM_ISB_OUT0 + ,output [6 :0] ch3_xy_A_DEM_ISB_OUT1 + ,output [6 :0] ch3_xy_A_DEM_ISB_OUT2 + ,output [6 :0] ch3_xy_A_DEM_ISB_OUT3 + ,output [6 :0] ch3_xy_A_DEM_ISB_OUT4 + ,output [6 :0] ch3_xy_A_DEM_ISB_OUT5 + ,output [6 :0] ch3_xy_A_DEM_ISB_OUT6 + ,output [6 :0] ch3_xy_A_DEM_ISB_OUT7 + ,output [6 :0] ch3_xy_B_DEM_ISB_OUT0 + ,output [6 :0] ch3_xy_B_DEM_ISB_OUT1 + ,output [6 :0] ch3_xy_B_DEM_ISB_OUT2 + ,output [6 :0] ch3_xy_B_DEM_ISB_OUT3 + ,output [6 :0] ch3_xy_B_DEM_ISB_OUT4 + ,output [6 :0] ch3_xy_B_DEM_ISB_OUT5 + ,output [6 :0] ch3_xy_B_DEM_ISB_OUT6 + ,output [6 :0] ch3_xy_B_DEM_ISB_OUT7 + ,output [8 :0] ch3_xy_A_DEM_LSB_OUT0 + ,output [8 :0] ch3_xy_A_DEM_LSB_OUT1 + ,output [8 :0] ch3_xy_A_DEM_LSB_OUT2 + ,output [8 :0] ch3_xy_A_DEM_LSB_OUT3 + ,output [8 :0] ch3_xy_A_DEM_LSB_OUT4 + ,output [8 :0] ch3_xy_A_DEM_LSB_OUT5 + ,output [8 :0] ch3_xy_A_DEM_LSB_OUT6 + ,output [8 :0] ch3_xy_A_DEM_LSB_OUT7 + ,output [8 :0] ch3_xy_B_DEM_LSB_OUT0 + ,output [8 :0] ch3_xy_B_DEM_LSB_OUT1 + ,output [8 :0] ch3_xy_B_DEM_LSB_OUT2 + ,output [8 :0] ch3_xy_B_DEM_LSB_OUT3 + ,output [8 :0] ch3_xy_B_DEM_LSB_OUT4 + ,output [8 :0] ch3_xy_B_DEM_LSB_OUT5 + ,output [8 :0] ch3_xy_B_DEM_LSB_OUT6 + ,output [8 :0] ch3_xy_B_DEM_LSB_OUT7 + `endif + `ifdef CHANNEL_Z_ON + ,output [14 :0] ch3_z_DEM_MSB_OUT0 + ,output [14 :0] ch3_z_DEM_MSB_OUT1 + ,output [14 :0] ch3_z_DEM_MSB_OUT2 + ,output [14 :0] ch3_z_DEM_MSB_OUT3 + ,output [6 :0] ch3_z_DEM_ISB_OUT0 + ,output [6 :0] ch3_z_DEM_ISB_OUT1 + ,output [6 :0] ch3_z_DEM_ISB_OUT2 + ,output [6 :0] ch3_z_DEM_ISB_OUT3 + ,output [8 :0] ch3_z_DEM_LSB_OUT0 + ,output [8 :0] ch3_z_DEM_LSB_OUT1 + ,output [8 :0] ch3_z_DEM_LSB_OUT2 + ,output [8 :0] ch3_z_DEM_LSB_OUT3 + `endif + `endif + //+++++++++++++++++++++++++++++++++++++++++++++// + // PIN END // + //+++++++++++++++++++++++++++++++++++++++++++++// +); + +//------------------------------iopad instantiation start-------------------------------------- +// iopad +//--------------------------------------------------------------------------------------------- +wire async_rstn ; +wire sync_in ; +wire sync_out ; +wire [1 :0] ch0_feedback ; +`ifdef CHANNEL_IS_FOUR +wire [1 :0] ch1_feedback ; +wire [1 :0] ch2_feedback ; +wire [1 :0] ch3_feedback ; +`endif +wire [4 :0] cfgid ; +wire sclk ; +wire csn ; +wire mosi ; +wire miso ; +wire oen ; +wire irq ; + +iopad U_iopad ( + //+++++++++++++++++++++++++++++++++++++++++++++// + // PAD Strat // + //+++++++++++++++++++++++++++++++++++++++++++++// + .PI_async_rstn ( PI_async_rstn ) + ,.PI_sync_in ( PI_sync_in ) + ,.PO_sync_out ( PO_sync_out ) + ,.PI_ch0_feedback ( PI_ch0_feedback ) + `ifdef CHANNEL_IS_FOUR + ,.PI_ch1_feedback ( PI_ch1_feedback ) + ,.PI_ch2_feedback ( PI_ch2_feedback ) + ,.PI_ch3_feedback ( PI_ch3_feedback ) + `endif + ,.PI_cfgid ( PI_cfgid ) + ,.PI_sclk ( PI_sclk ) + ,.PI_csn ( PI_csn ) + ,.PI_mosi ( PI_mosi ) + ,.PO_miso ( PO_miso ) + ,.PO_irq ( PO_irq ) + //+++++++++++++++++++++++++++++++++++++++++++++// + // PAD End // + //+++++++++++++++++++++++++++++++++++++++++++++// + + //+++++++++++++++++++++++++++++++++++++++++++++// + // Internal signal Start // + //+++++++++++++++++++++++++++++++++++++++++++++// + ,.async_rstn ( async_rstn ) + ,.sync_in ( sync_in ) + ,.sync_out ( sync_out ) + ,.ch0_feedback ( ch0_feedback ) + `ifdef CHANNEL_IS_FOUR + ,.ch1_feedback ( ch1_feedback ) + ,.ch2_feedback ( ch2_feedback ) + ,.ch3_feedback ( ch3_feedback ) + `endif + ,.cfgid ( cfgid ) + ,.sclk ( sclk ) + ,.csn ( csn ) + ,.mosi ( mosi ) + ,.miso ( miso ) + ,.oen ( oen ) + ,.irq ( irq ) +); +//------------------------------iopad instantiation end--------------------------------------- +// iopad +//--------------------------------------------------------------------------------------------- + +//------------------------------digital_top instantiation start-------------------------------- +// digital_top +//--------------------------------------------------------------------------------------------- + +wire ch0_dac_Prbs ; +wire [14 :0] ch0_dac_Set0 ; +wire [14 :0] ch0_dac_Set1 ; +wire [14 :0] ch0_dac_Set2 ; +wire [14 :0] ch0_dac_Set3 ; +wire [14 :0] ch0_dac_Set4 ; +wire [14 :0] ch0_dac_Set5 ; +wire [14 :0] ch0_dac_Set6 ; +wire [14 :0] ch0_dac_Set7 ; +wire [14 :0] ch0_dac_Set8 ; +wire [14 :0] ch0_dac_Set9 ; +wire [14 :0] ch0_dac_Set10 ; +wire [14 :0] ch0_dac_Set11 ; +wire [14 :0] ch0_dac_Set12 ; +wire [14 :0] ch0_dac_Set13 ; +wire [14 :0] ch0_dac_Set14 ; +wire [14 :0] ch0_dac_Set15 ; + +`ifdef CHANNEL_IS_FOUR +wire ch1_dac_Prbs ; +wire [14 :0] ch1_dac_Set0 ; +wire [14 :0] ch1_dac_Set1 ; +wire [14 :0] ch1_dac_Set2 ; +wire [14 :0] ch1_dac_Set3 ; +wire [14 :0] ch1_dac_Set4 ; +wire [14 :0] ch1_dac_Set5 ; +wire [14 :0] ch1_dac_Set6 ; +wire [14 :0] ch1_dac_Set7 ; +wire [14 :0] ch1_dac_Set8 ; +wire [14 :0] ch1_dac_Set9 ; +wire [14 :0] ch1_dac_Set10 ; +wire [14 :0] ch1_dac_Set11 ; +wire [14 :0] ch1_dac_Set12 ; +wire [14 :0] ch1_dac_Set13 ; +wire [14 :0] ch1_dac_Set14 ; +wire [14 :0] ch1_dac_Set15 ; + +wire ch2_dac_Prbs ; +wire [14 :0] ch2_dac_Set0 ; +wire [14 :0] ch2_dac_Set1 ; +wire [14 :0] ch2_dac_Set2 ; +wire [14 :0] ch2_dac_Set3 ; +wire [14 :0] ch2_dac_Set4 ; +wire [14 :0] ch2_dac_Set5 ; +wire [14 :0] ch2_dac_Set6 ; +wire [14 :0] ch2_dac_Set7 ; +wire [14 :0] ch2_dac_Set8 ; +wire [14 :0] ch2_dac_Set9 ; +wire [14 :0] ch2_dac_Set10 ; +wire [14 :0] ch2_dac_Set11 ; +wire [14 :0] ch2_dac_Set12 ; +wire [14 :0] ch2_dac_Set13 ; +wire [14 :0] ch2_dac_Set14 ; +wire [14 :0] ch2_dac_Set15 ; + +wire ch3_dac_Prbs ; +wire [14 :0] ch3_dac_Set0 ; +wire [14 :0] ch3_dac_Set1 ; +wire [14 :0] ch3_dac_Set2 ; +wire [14 :0] ch3_dac_Set3 ; +wire [14 :0] ch3_dac_Set4 ; +wire [14 :0] ch3_dac_Set5 ; +wire [14 :0] ch3_dac_Set6 ; +wire [14 :0] ch3_dac_Set7 ; +wire [14 :0] ch3_dac_Set8 ; +wire [14 :0] ch3_dac_Set9 ; +wire [14 :0] ch3_dac_Set10 ; +wire [14 :0] ch3_dac_Set11 ; +wire [14 :0] ch3_dac_Set12 ; +wire [14 :0] ch3_dac_Set13 ; +wire [14 :0] ch3_dac_Set14 ; +wire [14 :0] ch3_dac_Set15 ; +`endif + +`ifdef CHANNEL_XY_ON +wire [15 :0] ch0_xy_dsp_dout0 ; +wire [15 :0] ch0_xy_dsp_dout1 ; +wire [15 :0] ch0_xy_dsp_dout2 ; +wire [15 :0] ch0_xy_dsp_dout3 ; +wire [15 :0] ch0_xy_dsp_dout4 ; +wire [15 :0] ch0_xy_dsp_dout5 ; +wire [15 :0] ch0_xy_dsp_dout6 ; +wire [15 :0] ch0_xy_dsp_dout7 ; +wire [15 :0] ch0_xy_dsp_dout8 ; +wire [15 :0] ch0_xy_dsp_dout9 ; +wire [15 :0] ch0_xy_dsp_dout10 ; +wire [15 :0] ch0_xy_dsp_dout11 ; +wire [15 :0] ch0_xy_dsp_dout12 ; +wire [15 :0] ch0_xy_dsp_dout13 ; +wire [15 :0] ch0_xy_dsp_dout14 ; +wire [15 :0] ch0_xy_dsp_dout15 ; +`endif +`ifdef CHANNEL_Z_ON +wire [15 :0] ch0_z_dsp_dout0 ; +wire [15 :0] ch0_z_dsp_dout1 ; +wire [15 :0] ch0_z_dsp_dout2 ; +wire [15 :0] ch0_z_dsp_dout3 ; +`endif + +`ifdef CHANNEL_IS_FOUR +`ifdef CHANNEL_XY_ON +wire [15 :0] ch1_xy_dsp_dout0 ; +wire [15 :0] ch1_xy_dsp_dout1 ; +wire [15 :0] ch1_xy_dsp_dout2 ; +wire [15 :0] ch1_xy_dsp_dout3 ; +wire [15 :0] ch1_xy_dsp_dout4 ; +wire [15 :0] ch1_xy_dsp_dout5 ; +wire [15 :0] ch1_xy_dsp_dout6 ; +wire [15 :0] ch1_xy_dsp_dout7 ; +wire [15 :0] ch1_xy_dsp_dout8 ; +wire [15 :0] ch1_xy_dsp_dout9 ; +wire [15 :0] ch1_xy_dsp_dout10 ; +wire [15 :0] ch1_xy_dsp_dout11 ; +wire [15 :0] ch1_xy_dsp_dout12 ; +wire [15 :0] ch1_xy_dsp_dout13 ; +wire [15 :0] ch1_xy_dsp_dout14 ; +wire [15 :0] ch1_xy_dsp_dout15 ; +`endif +`ifdef CHANNEL_Z_ON +wire [15 :0] ch1_z_dsp_dout0 ; +wire [15 :0] ch1_z_dsp_dout1 ; +wire [15 :0] ch1_z_dsp_dout2 ; +wire [15 :0] ch1_z_dsp_dout3 ; +`endif + +`ifdef CHANNEL_XY_ON +wire [15 :0] ch2_xy_dsp_dout0 ; +wire [15 :0] ch2_xy_dsp_dout1 ; +wire [15 :0] ch2_xy_dsp_dout2 ; +wire [15 :0] ch2_xy_dsp_dout3 ; +wire [15 :0] ch2_xy_dsp_dout4 ; +wire [15 :0] ch2_xy_dsp_dout5 ; +wire [15 :0] ch2_xy_dsp_dout6 ; +wire [15 :0] ch2_xy_dsp_dout7 ; +wire [15 :0] ch2_xy_dsp_dout8 ; +wire [15 :0] ch2_xy_dsp_dout9 ; +wire [15 :0] ch2_xy_dsp_dout10 ; +wire [15 :0] ch2_xy_dsp_dout11 ; +wire [15 :0] ch2_xy_dsp_dout12 ; +wire [15 :0] ch2_xy_dsp_dout13 ; +wire [15 :0] ch2_xy_dsp_dout14 ; +wire [15 :0] ch2_xy_dsp_dout15 ; +`endif +`ifdef CHANNEL_Z_ON +wire [15 :0] ch2_z_dsp_dout0 ; +wire [15 :0] ch2_z_dsp_dout1 ; +wire [15 :0] ch2_z_dsp_dout2 ; +wire [15 :0] ch2_z_dsp_dout3 ; +`endif + +`ifdef CHANNEL_XY_ON +wire [15 :0] ch3_xy_dsp_dout0 ; +wire [15 :0] ch3_xy_dsp_dout1 ; +wire [15 :0] ch3_xy_dsp_dout2 ; +wire [15 :0] ch3_xy_dsp_dout3 ; +wire [15 :0] ch3_xy_dsp_dout4 ; +wire [15 :0] ch3_xy_dsp_dout5 ; +wire [15 :0] ch3_xy_dsp_dout6 ; +wire [15 :0] ch3_xy_dsp_dout7 ; +wire [15 :0] ch3_xy_dsp_dout8 ; +wire [15 :0] ch3_xy_dsp_dout9 ; +wire [15 :0] ch3_xy_dsp_dout10 ; +wire [15 :0] ch3_xy_dsp_dout11 ; +wire [15 :0] ch3_xy_dsp_dout12 ; +wire [15 :0] ch3_xy_dsp_dout13 ; +wire [15 :0] ch3_xy_dsp_dout14 ; +wire [15 :0] ch3_xy_dsp_dout15 ; +`endif +`ifdef CHANNEL_Z_ON +wire [15 :0] ch3_z_dsp_dout0 ; +wire [15 :0] ch3_z_dsp_dout1 ; +wire [15 :0] ch3_z_dsp_dout2 ; +wire [15 :0] ch3_z_dsp_dout3 ; +`endif +`endif + +digital_top U_digital_top ( + .clk ( clk ) + ,.por_rstn ( por_rstn ) + ,.async_rstn ( async_rstn ) + ,.sync_in ( sync_in ) + ,.sync_out ( sync_out ) + ,.ch0_feedback ( ch0_feedback ) + `ifdef CHANNEL_IS_FOUR + ,.ch1_feedback ( ch1_feedback ) + ,.ch2_feedback ( ch2_feedback ) + ,.ch3_feedback ( ch3_feedback ) + `endif + ,.cfgid ( cfgid ) + ,.sclk ( sclk ) + ,.csn ( csn ) + ,.mosi ( mosi ) + ,.miso ( miso ) + ,.oen ( oen ) + ,.irq ( irq ) + ,.ref_sel ( ref_sel ) + ,.ref_en ( ref_en ) + ,.ref_s2d_en ( ref_s2d_en ) + ,.p_cnt ( p_cnt ) + ,.pfd_delay ( pfd_delay ) + ,.pfd_dff_Set ( pfd_dff_Set ) + ,.pfd_dff_4and ( pfd_dff_4and ) + ,.spd_div ( spd_div ) + ,.spd_pulse_width ( spd_pulse_width ) + ,.spd_pulse_sw ( spd_pulse_sw ) + ,.cpc_sel ( cpc_sel ) + ,.swcp_i ( swcp_i ) + ,.sw_ptat_r ( sw_ptat_r ) + ,.sw_fll_cpi ( sw_fll_cpi ) + ,.sw_fll_delay ( sw_fll_delay ) + ,.pfd_sel ( pfd_sel ) + ,.spd_sel ( spd_sel ) + ,.fll_sel ( fll_sel ) + ,.vco_tc ( vco_tc ) + ,.vco_tcr ( vco_tcr ) + ,.vco_gain_adj ( vco_gain_adj ) + ,.vco_gain_adj_r ( vco_gain_adj_r ) + ,.vco_cur_adj ( vco_cur_adj ) + ,.vco_buff_en ( vco_buff_en ) + ,.vco_en ( vco_en ) + ,.pll_dpwr_adj ( pll_dpwr_adj ) + ,.vco_fb_adj ( vco_fb_adj ) + ,.afc_en ( afc_en ) + ,.afc_shutdown ( afc_shutdown ) + ,.afc_det_speed ( afc_det_speed ) + ,.flag_out_sel ( flag_out_sel ) + ,.afc_reset ( afc_reset ) + ,.afc_cnt ( afc_cnt ) + ,.afc_ld_cnt ( afc_ld_cnt ) + ,.afc_pres ( afc_pres ) + ,.afc_ld_tcc ( afc_ld_tcc ) + ,.afc_fb_tcc ( afc_fb_tcc ) + ,.sync_clr ( sync_clr ) + ,.pll_rstn ( pll_rstn ) + ,.div_rstn_sel ( div_rstn_sel ) + ,.test_clk_sel ( test_clk_sel ) + ,.test_clk_oen ( test_clk_oen ) + ,.dig_clk_sel ( dig_clk_sel ) + ,.clkrx_pdn ( clkrx_pdn ) + ,.pll_lock ( pll_lock ) + //------------------------------Ch0 DAC cfg pin---------------------------------------------------- + ,.ch0_dac_Prbs ( ch0_dac_Prbs ) + ,.ch0_dac_Set0 ( ch0_dac_Set0 ) + ,.ch0_dac_Set1 ( ch0_dac_Set1 ) + ,.ch0_dac_Set2 ( ch0_dac_Set2 ) + ,.ch0_dac_Set3 ( ch0_dac_Set3 ) + ,.ch0_dac_Set4 ( ch0_dac_Set4 ) + ,.ch0_dac_Set5 ( ch0_dac_Set5 ) + ,.ch0_dac_Set6 ( ch0_dac_Set6 ) + ,.ch0_dac_Set7 ( ch0_dac_Set7 ) + ,.ch0_dac_Set8 ( ch0_dac_Set8 ) + ,.ch0_dac_Set9 ( ch0_dac_Set9 ) + ,.ch0_dac_Set10 ( ch0_dac_Set10 ) + ,.ch0_dac_Set11 ( ch0_dac_Set11 ) + ,.ch0_dac_Set12 ( ch0_dac_Set12 ) + ,.ch0_dac_Set13 ( ch0_dac_Set13 ) + ,.ch0_dac_Set14 ( ch0_dac_Set14 ) + ,.ch0_dac_Set15 ( ch0_dac_Set15 ) + ,.ch0_dac_addr ( ch0_dac_addr ) + ,.ch0_dac_dw ( ch0_dac_dw ) + ,.ch0_dac_ref ( ch0_dac_ref ) + ,.ch0_dac_Prbs_rst0 ( ch0_dac_Prbs_rst0 ) + ,.ch0_dac_Prbs_set0 ( ch0_dac_Prbs_set0 ) + ,.ch0_dac_Prbs_rst1 ( ch0_dac_Prbs_rst1 ) + ,.ch0_dac_Prbs_set1 ( ch0_dac_Prbs_set1 ) + ,.ch0_dac_Cal_sig ( ch0_dac_Cal_sig ) + ,.ch0_dac_Cal_rstn ( ch0_dac_Cal_rstn ) + ,.ch0_dac_Cal_div_rstn ( ch0_dac_Cal_div_rstn ) + ,.ch0_dac_Cal_end ( ch0_dac_Cal_end ) + `ifdef CHANNEL_IS_FOUR + //------------------------------Ch1 DAC cfg pin---------------------------------------------------- + ,.ch1_dac_Prbs ( ch1_dac_Prbs ) + ,.ch1_dac_Set0 ( ch1_dac_Set0 ) + ,.ch1_dac_Set1 ( ch1_dac_Set1 ) + ,.ch1_dac_Set2 ( ch1_dac_Set2 ) + ,.ch1_dac_Set3 ( ch1_dac_Set3 ) + ,.ch1_dac_Set4 ( ch1_dac_Set4 ) + ,.ch1_dac_Set5 ( ch1_dac_Set5 ) + ,.ch1_dac_Set6 ( ch1_dac_Set6 ) + ,.ch1_dac_Set7 ( ch1_dac_Set7 ) + ,.ch1_dac_Set8 ( ch1_dac_Set8 ) + ,.ch1_dac_Set9 ( ch1_dac_Set9 ) + ,.ch1_dac_Set10 ( ch1_dac_Set10 ) + ,.ch1_dac_Set11 ( ch1_dac_Set11 ) + ,.ch1_dac_Set12 ( ch1_dac_Set12 ) + ,.ch1_dac_Set13 ( ch1_dac_Set13 ) + ,.ch1_dac_Set14 ( ch1_dac_Set14 ) + ,.ch1_dac_Set15 ( ch1_dac_Set15 ) + ,.ch1_dac_addr ( ch1_dac_addr ) + ,.ch1_dac_dw ( ch1_dac_dw ) + ,.ch1_dac_ref ( ch1_dac_ref ) + ,.ch1_dac_Prbs_rst0 ( ch1_dac_Prbs_rst0 ) + ,.ch1_dac_Prbs_set0 ( ch1_dac_Prbs_set0 ) + ,.ch1_dac_Prbs_rst1 ( ch1_dac_Prbs_rst1 ) + ,.ch1_dac_Prbs_set1 ( ch1_dac_Prbs_set1 ) + ,.ch1_dac_Cal_sig ( ch1_dac_Cal_sig ) + ,.ch1_dac_Cal_rstn ( ch1_dac_Cal_rstn ) + ,.ch1_dac_Cal_div_rstn ( ch1_dac_Cal_div_rstn ) + ,.ch1_dac_Cal_end ( ch1_dac_Cal_end ) + //------------------------------Ch2 DAC cfg pin---------------------------------------------------- + ,.ch2_dac_Prbs ( ch2_dac_Prbs ) + ,.ch2_dac_Set0 ( ch2_dac_Set0 ) + ,.ch2_dac_Set1 ( ch2_dac_Set1 ) + ,.ch2_dac_Set2 ( ch2_dac_Set2 ) + ,.ch2_dac_Set3 ( ch2_dac_Set3 ) + ,.ch2_dac_Set4 ( ch2_dac_Set4 ) + ,.ch2_dac_Set5 ( ch2_dac_Set5 ) + ,.ch2_dac_Set6 ( ch2_dac_Set6 ) + ,.ch2_dac_Set7 ( ch2_dac_Set7 ) + ,.ch2_dac_Set8 ( ch2_dac_Set8 ) + ,.ch2_dac_Set9 ( ch2_dac_Set9 ) + ,.ch2_dac_Set10 ( ch2_dac_Set10 ) + ,.ch2_dac_Set11 ( ch2_dac_Set11 ) + ,.ch2_dac_Set12 ( ch2_dac_Set12 ) + ,.ch2_dac_Set13 ( ch2_dac_Set13 ) + ,.ch2_dac_Set14 ( ch2_dac_Set14 ) + ,.ch2_dac_Set15 ( ch2_dac_Set15 ) + ,.ch2_dac_addr ( ch2_dac_addr ) + ,.ch2_dac_dw ( ch2_dac_dw ) + ,.ch2_dac_ref ( ch2_dac_ref ) + ,.ch2_dac_Prbs_rst0 ( ch2_dac_Prbs_rst0 ) + ,.ch2_dac_Prbs_set0 ( ch2_dac_Prbs_set0 ) + ,.ch2_dac_Prbs_rst1 ( ch2_dac_Prbs_rst1 ) + ,.ch2_dac_Prbs_set1 ( ch2_dac_Prbs_set1 ) + ,.ch2_dac_Cal_sig ( ch2_dac_Cal_sig ) + ,.ch2_dac_Cal_rstn ( ch2_dac_Cal_rstn ) + ,.ch2_dac_Cal_div_rstn ( ch2_dac_Cal_div_rstn ) + ,.ch2_dac_Cal_end ( ch2_dac_Cal_end ) + //------------------------------Ch3 DAC cfg pin---------------------------------------------------- + ,.ch3_dac_Prbs ( ch3_dac_Prbs ) + ,.ch3_dac_Set0 ( ch3_dac_Set0 ) + ,.ch3_dac_Set1 ( ch3_dac_Set1 ) + ,.ch3_dac_Set2 ( ch3_dac_Set2 ) + ,.ch3_dac_Set3 ( ch3_dac_Set3 ) + ,.ch3_dac_Set4 ( ch3_dac_Set4 ) + ,.ch3_dac_Set5 ( ch3_dac_Set5 ) + ,.ch3_dac_Set6 ( ch3_dac_Set6 ) + ,.ch3_dac_Set7 ( ch3_dac_Set7 ) + ,.ch3_dac_Set8 ( ch3_dac_Set8 ) + ,.ch3_dac_Set9 ( ch3_dac_Set9 ) + ,.ch3_dac_Set10 ( ch3_dac_Set10 ) + ,.ch3_dac_Set11 ( ch3_dac_Set11 ) + ,.ch3_dac_Set12 ( ch3_dac_Set12 ) + ,.ch3_dac_Set13 ( ch3_dac_Set13 ) + ,.ch3_dac_Set14 ( ch3_dac_Set14 ) + ,.ch3_dac_Set15 ( ch3_dac_Set15 ) + ,.ch3_dac_addr ( ch3_dac_addr ) + ,.ch3_dac_dw ( ch3_dac_dw ) + ,.ch3_dac_ref ( ch3_dac_ref ) + ,.ch3_dac_Prbs_rst0 ( ch3_dac_Prbs_rst0 ) + ,.ch3_dac_Prbs_set0 ( ch3_dac_Prbs_set0 ) + ,.ch3_dac_Prbs_rst1 ( ch3_dac_Prbs_rst1 ) + ,.ch3_dac_Prbs_set1 ( ch3_dac_Prbs_set1 ) + ,.ch3_dac_Cal_sig ( ch3_dac_Cal_sig ) + ,.ch3_dac_Cal_rstn ( ch3_dac_Cal_rstn ) + ,.ch3_dac_Cal_div_rstn ( ch3_dac_Cal_div_rstn ) + ,.ch3_dac_Cal_end ( ch3_dac_Cal_end ) + `endif + //------------------------------Ch0 DSP data out---------------------------------------------------- + `ifdef CHANNEL_XY_ON + ,.ch0_xy_dsp_dout0 ( ch0_xy_dsp_dout0 ) + ,.ch0_xy_dsp_dout1 ( ch0_xy_dsp_dout1 ) + ,.ch0_xy_dsp_dout2 ( ch0_xy_dsp_dout2 ) + ,.ch0_xy_dsp_dout3 ( ch0_xy_dsp_dout3 ) + ,.ch0_xy_dsp_dout4 ( ch0_xy_dsp_dout4 ) + ,.ch0_xy_dsp_dout5 ( ch0_xy_dsp_dout5 ) + ,.ch0_xy_dsp_dout6 ( ch0_xy_dsp_dout6 ) + ,.ch0_xy_dsp_dout7 ( ch0_xy_dsp_dout7 ) + ,.ch0_xy_dsp_dout8 ( ch0_xy_dsp_dout8 ) + ,.ch0_xy_dsp_dout9 ( ch0_xy_dsp_dout9 ) + ,.ch0_xy_dsp_dout10 ( ch0_xy_dsp_dout10 ) + ,.ch0_xy_dsp_dout11 ( ch0_xy_dsp_dout11 ) + ,.ch0_xy_dsp_dout12 ( ch0_xy_dsp_dout12 ) + ,.ch0_xy_dsp_dout13 ( ch0_xy_dsp_dout13 ) + ,.ch0_xy_dsp_dout14 ( ch0_xy_dsp_dout14 ) + ,.ch0_xy_dsp_dout15 ( ch0_xy_dsp_dout15 ) + `endif + `ifdef CHANNEL_Z_ON + ,.ch0_z_dsp_dout0 ( ch0_z_dsp_dout0 ) + ,.ch0_z_dsp_dout1 ( ch0_z_dsp_dout1 ) + ,.ch0_z_dsp_dout2 ( ch0_z_dsp_dout2 ) + ,.ch0_z_dsp_dout3 ( ch0_z_dsp_dout3 ) + `endif + `ifdef CHANNEL_IS_FOUR + //------------------------------Ch1 DSP data out---------------------------------------------------- + `ifdef CHANNEL_XY_ON + ,.ch1_xy_dsp_dout0 ( ch1_xy_dsp_dout0 ) + ,.ch1_xy_dsp_dout1 ( ch1_xy_dsp_dout1 ) + ,.ch1_xy_dsp_dout2 ( ch1_xy_dsp_dout2 ) + ,.ch1_xy_dsp_dout3 ( ch1_xy_dsp_dout3 ) + ,.ch1_xy_dsp_dout4 ( ch1_xy_dsp_dout4 ) + ,.ch1_xy_dsp_dout5 ( ch1_xy_dsp_dout5 ) + ,.ch1_xy_dsp_dout6 ( ch1_xy_dsp_dout6 ) + ,.ch1_xy_dsp_dout7 ( ch1_xy_dsp_dout7 ) + ,.ch1_xy_dsp_dout8 ( ch1_xy_dsp_dout8 ) + ,.ch1_xy_dsp_dout9 ( ch1_xy_dsp_dout9 ) + ,.ch1_xy_dsp_dout10 ( ch1_xy_dsp_dout10 ) + ,.ch1_xy_dsp_dout11 ( ch1_xy_dsp_dout11 ) + ,.ch1_xy_dsp_dout12 ( ch1_xy_dsp_dout12 ) + ,.ch1_xy_dsp_dout13 ( ch1_xy_dsp_dout13 ) + ,.ch1_xy_dsp_dout14 ( ch1_xy_dsp_dout14 ) + ,.ch1_xy_dsp_dout15 ( ch1_xy_dsp_dout15 ) + `endif + `ifdef CHANNEL_Z_ON + ,.ch1_z_dsp_dout0 ( ch1_z_dsp_dout0 ) + ,.ch1_z_dsp_dout1 ( ch1_z_dsp_dout1 ) + ,.ch1_z_dsp_dout2 ( ch1_z_dsp_dout2 ) + ,.ch1_z_dsp_dout3 ( ch1_z_dsp_dout3 ) + `endif + //------------------------------Ch2 DSP data out---------------------------------------------------- + `ifdef CHANNEL_XY_ON + ,.ch2_xy_dsp_dout0 ( ch2_xy_dsp_dout0 ) + ,.ch2_xy_dsp_dout1 ( ch2_xy_dsp_dout1 ) + ,.ch2_xy_dsp_dout2 ( ch2_xy_dsp_dout2 ) + ,.ch2_xy_dsp_dout3 ( ch2_xy_dsp_dout3 ) + ,.ch2_xy_dsp_dout4 ( ch2_xy_dsp_dout4 ) + ,.ch2_xy_dsp_dout5 ( ch2_xy_dsp_dout5 ) + ,.ch2_xy_dsp_dout6 ( ch2_xy_dsp_dout6 ) + ,.ch2_xy_dsp_dout7 ( ch2_xy_dsp_dout7 ) + ,.ch2_xy_dsp_dout8 ( ch2_xy_dsp_dout8 ) + ,.ch2_xy_dsp_dout9 ( ch2_xy_dsp_dout9 ) + ,.ch2_xy_dsp_dout10 ( ch2_xy_dsp_dout10 ) + ,.ch2_xy_dsp_dout11 ( ch2_xy_dsp_dout11 ) + ,.ch2_xy_dsp_dout12 ( ch2_xy_dsp_dout12 ) + ,.ch2_xy_dsp_dout13 ( ch2_xy_dsp_dout13 ) + ,.ch2_xy_dsp_dout14 ( ch2_xy_dsp_dout14 ) + ,.ch2_xy_dsp_dout15 ( ch2_xy_dsp_dout15 ) + `endif + `ifdef CHANNEL_Z_ON + ,.ch2_z_dsp_dout0 ( ch2_z_dsp_dout0 ) + ,.ch2_z_dsp_dout1 ( ch2_z_dsp_dout1 ) + ,.ch2_z_dsp_dout2 ( ch2_z_dsp_dout2 ) + ,.ch2_z_dsp_dout3 ( ch2_z_dsp_dout3 ) + `endif + //------------------------------Ch3 DSP data out---------------------------------------------------- + `ifdef CHANNEL_XY_ON + ,.ch3_xy_dsp_dout0 ( ch3_xy_dsp_dout0 ) + ,.ch3_xy_dsp_dout1 ( ch3_xy_dsp_dout1 ) + ,.ch3_xy_dsp_dout2 ( ch3_xy_dsp_dout2 ) + ,.ch3_xy_dsp_dout3 ( ch3_xy_dsp_dout3 ) + ,.ch3_xy_dsp_dout4 ( ch3_xy_dsp_dout4 ) + ,.ch3_xy_dsp_dout5 ( ch3_xy_dsp_dout5 ) + ,.ch3_xy_dsp_dout6 ( ch3_xy_dsp_dout6 ) + ,.ch3_xy_dsp_dout7 ( ch3_xy_dsp_dout7 ) + ,.ch3_xy_dsp_dout8 ( ch3_xy_dsp_dout8 ) + ,.ch3_xy_dsp_dout9 ( ch3_xy_dsp_dout9 ) + ,.ch3_xy_dsp_dout10 ( ch3_xy_dsp_dout10 ) + ,.ch3_xy_dsp_dout11 ( ch3_xy_dsp_dout11 ) + ,.ch3_xy_dsp_dout12 ( ch3_xy_dsp_dout12 ) + ,.ch3_xy_dsp_dout13 ( ch3_xy_dsp_dout13 ) + ,.ch3_xy_dsp_dout14 ( ch3_xy_dsp_dout14 ) + ,.ch3_xy_dsp_dout15 ( ch3_xy_dsp_dout15 ) + `endif + `ifdef CHANNEL_Z_ON + ,.ch3_z_dsp_dout0 ( ch3_z_dsp_dout0 ) + ,.ch3_z_dsp_dout1 ( ch3_z_dsp_dout1 ) + ,.ch3_z_dsp_dout2 ( ch3_z_dsp_dout2 ) + ,.ch3_z_dsp_dout3 ( ch3_z_dsp_dout3 ) + `endif + `endif +); + +//------------------------------digital_top instantiation end---------------------------------- +// digital_top +//--------------------------------------------------------------------------------------------- + + + +`ifdef CHANNEL_XY_ON +//------------------------------XY ch0 DAC_DEM_16 instantiation start-------------------------- +// DAC_DEM_16 +//--------------------------------------------------------------------------------------------- +DAC_DEM_16 U0_DAC_DEM_16 ( + .CLK_IN ( clk ) + ,.prbs_en ( ch0_dac_Prbs ) + ,.set0 ( ch0_dac_Set0 ) + ,.set1 ( ch0_dac_Set1 ) + ,.set2 ( ch0_dac_Set2 ) + ,.set3 ( ch0_dac_Set3 ) + ,.set4 ( ch0_dac_Set4 ) + ,.set5 ( ch0_dac_Set5 ) + ,.set6 ( ch0_dac_Set6 ) + ,.set7 ( ch0_dac_Set7 ) + ,.set8 ( ch0_dac_Set8 ) + ,.set9 ( ch0_dac_Set9 ) + ,.set10 ( ch0_dac_Set10 ) + ,.set11 ( ch0_dac_Set11 ) + ,.set12 ( ch0_dac_Set12 ) + ,.set13 ( ch0_dac_Set13 ) + ,.set14 ( ch0_dac_Set14 ) + ,.set15 ( ch0_dac_Set15 ) + + ,.DATA_IN0 ( ch0_xy_dsp_dout0 ) + ,.DATA_IN1 ( ch0_xy_dsp_dout1 ) + ,.DATA_IN2 ( ch0_xy_dsp_dout2 ) + ,.DATA_IN3 ( ch0_xy_dsp_dout3 ) + ,.DATA_IN4 ( ch0_xy_dsp_dout4 ) + ,.DATA_IN5 ( ch0_xy_dsp_dout5 ) + ,.DATA_IN6 ( ch0_xy_dsp_dout6 ) + ,.DATA_IN7 ( ch0_xy_dsp_dout7 ) + ,.DATA_IN8 ( ch0_xy_dsp_dout8 ) + ,.DATA_IN9 ( ch0_xy_dsp_dout9 ) + ,.DATA_IN10 ( ch0_xy_dsp_dout10 ) + ,.DATA_IN11 ( ch0_xy_dsp_dout11 ) + ,.DATA_IN12 ( ch0_xy_dsp_dout12 ) + ,.DATA_IN13 ( ch0_xy_dsp_dout13 ) + ,.DATA_IN14 ( ch0_xy_dsp_dout14 ) + ,.DATA_IN15 ( ch0_xy_dsp_dout15 ) + + ,.A_DEM_MSB_OUT0 ( ch0_xy_A_DEM_MSB_OUT0 ) + ,.A_DEM_MSB_OUT1 ( ch0_xy_A_DEM_MSB_OUT1 ) + ,.A_DEM_MSB_OUT2 ( ch0_xy_A_DEM_MSB_OUT2 ) + ,.A_DEM_MSB_OUT3 ( ch0_xy_A_DEM_MSB_OUT3 ) + ,.A_DEM_MSB_OUT4 ( ch0_xy_A_DEM_MSB_OUT4 ) + ,.A_DEM_MSB_OUT5 ( ch0_xy_A_DEM_MSB_OUT5 ) + ,.A_DEM_MSB_OUT6 ( ch0_xy_A_DEM_MSB_OUT6 ) + ,.A_DEM_MSB_OUT7 ( ch0_xy_A_DEM_MSB_OUT7 ) + + ,.A_DEM_ISB_OUT0 ( ch0_xy_A_DEM_ISB_OUT0 ) + ,.A_DEM_ISB_OUT1 ( ch0_xy_A_DEM_ISB_OUT1 ) + ,.A_DEM_ISB_OUT2 ( ch0_xy_A_DEM_ISB_OUT2 ) + ,.A_DEM_ISB_OUT3 ( ch0_xy_A_DEM_ISB_OUT3 ) + ,.A_DEM_ISB_OUT4 ( ch0_xy_A_DEM_ISB_OUT4 ) + ,.A_DEM_ISB_OUT5 ( ch0_xy_A_DEM_ISB_OUT5 ) + ,.A_DEM_ISB_OUT6 ( ch0_xy_A_DEM_ISB_OUT6 ) + ,.A_DEM_ISB_OUT7 ( ch0_xy_A_DEM_ISB_OUT7 ) + + ,.A_DEM_LSB_OUT0 ( ch0_xy_A_DEM_LSB_OUT0 ) + ,.A_DEM_LSB_OUT1 ( ch0_xy_A_DEM_LSB_OUT1 ) + ,.A_DEM_LSB_OUT2 ( ch0_xy_A_DEM_LSB_OUT2 ) + ,.A_DEM_LSB_OUT3 ( ch0_xy_A_DEM_LSB_OUT3 ) + ,.A_DEM_LSB_OUT4 ( ch0_xy_A_DEM_LSB_OUT4 ) + ,.A_DEM_LSB_OUT5 ( ch0_xy_A_DEM_LSB_OUT5 ) + ,.A_DEM_LSB_OUT6 ( ch0_xy_A_DEM_LSB_OUT6 ) + ,.A_DEM_LSB_OUT7 ( ch0_xy_A_DEM_LSB_OUT7 ) + + ,.B_DEM_MSB_OUT0 ( ch0_xy_B_DEM_MSB_OUT0 ) + ,.B_DEM_MSB_OUT1 ( ch0_xy_B_DEM_MSB_OUT1 ) + ,.B_DEM_MSB_OUT2 ( ch0_xy_B_DEM_MSB_OUT2 ) + ,.B_DEM_MSB_OUT3 ( ch0_xy_B_DEM_MSB_OUT3 ) + ,.B_DEM_MSB_OUT4 ( ch0_xy_B_DEM_MSB_OUT4 ) + ,.B_DEM_MSB_OUT5 ( ch0_xy_B_DEM_MSB_OUT5 ) + ,.B_DEM_MSB_OUT6 ( ch0_xy_B_DEM_MSB_OUT6 ) + ,.B_DEM_MSB_OUT7 ( ch0_xy_B_DEM_MSB_OUT7 ) + + ,.B_DEM_ISB_OUT0 ( ch0_xy_B_DEM_ISB_OUT0 ) + ,.B_DEM_ISB_OUT1 ( ch0_xy_B_DEM_ISB_OUT1 ) + ,.B_DEM_ISB_OUT2 ( ch0_xy_B_DEM_ISB_OUT2 ) + ,.B_DEM_ISB_OUT3 ( ch0_xy_B_DEM_ISB_OUT3 ) + ,.B_DEM_ISB_OUT4 ( ch0_xy_B_DEM_ISB_OUT4 ) + ,.B_DEM_ISB_OUT5 ( ch0_xy_B_DEM_ISB_OUT5 ) + ,.B_DEM_ISB_OUT6 ( ch0_xy_B_DEM_ISB_OUT6 ) + ,.B_DEM_ISB_OUT7 ( ch0_xy_B_DEM_ISB_OUT7 ) + + ,.B_DEM_LSB_OUT0 ( ch0_xy_B_DEM_LSB_OUT0 ) + ,.B_DEM_LSB_OUT1 ( ch0_xy_B_DEM_LSB_OUT1 ) + ,.B_DEM_LSB_OUT2 ( ch0_xy_B_DEM_LSB_OUT2 ) + ,.B_DEM_LSB_OUT3 ( ch0_xy_B_DEM_LSB_OUT3 ) + ,.B_DEM_LSB_OUT4 ( ch0_xy_B_DEM_LSB_OUT4 ) + ,.B_DEM_LSB_OUT5 ( ch0_xy_B_DEM_LSB_OUT5 ) + ,.B_DEM_LSB_OUT6 ( ch0_xy_B_DEM_LSB_OUT6 ) + ,.B_DEM_LSB_OUT7 ( ch0_xy_B_DEM_LSB_OUT7 ) + ); +`endif +//------------------------------XY ch0 DAC_DEM_16 instantiation end---------------------------- +// DAC_DEM_16 +//--------------------------------------------------------------------------------------------- + +//------------------------------Z ch0 DAC_DEM_16 instantiation start--------------------------- +// DAC_DEM_4 +//--------------------------------------------------------------------------------------------- + +`ifdef CHANNEL_Z_ON +DAC_DEM_4 U0_DAC_DEM_4 ( + .CLK_IN ( clk ) + ,.prbs_en ( ch0_dac_Prbs ) + ,.set0 ( ch0_dac_Set0 ) + ,.set1 ( ch0_dac_Set1 ) + ,.set2 ( ch0_dac_Set2 ) + ,.set3 ( ch0_dac_Set3 ) + ,.DATA_IN0 ( ch0_z_dsp_dout0 ) + ,.DATA_IN1 ( ch0_z_dsp_dout1 ) + ,.DATA_IN2 ( ch0_z_dsp_dout2 ) + ,.DATA_IN3 ( ch0_z_dsp_dout3 ) + ,.DEM_MSB_OUT0 ( ch0_z_DEM_MSB_OUT0 ) + ,.DEM_MSB_OUT1 ( ch0_z_DEM_MSB_OUT1 ) + ,.DEM_MSB_OUT2 ( ch0_z_DEM_MSB_OUT2 ) + ,.DEM_MSB_OUT3 ( ch0_z_DEM_MSB_OUT3 ) + ,.DEM_ISB_OUT0 ( ch0_z_DEM_ISB_OUT0 ) + ,.DEM_ISB_OUT1 ( ch0_z_DEM_ISB_OUT1 ) + ,.DEM_ISB_OUT2 ( ch0_z_DEM_ISB_OUT2 ) + ,.DEM_ISB_OUT3 ( ch0_z_DEM_ISB_OUT3 ) + ,.DEM_LSB_OUT0 ( ch0_z_DEM_LSB_OUT0 ) + ,.DEM_LSB_OUT1 ( ch0_z_DEM_LSB_OUT1 ) + ,.DEM_LSB_OUT2 ( ch0_z_DEM_LSB_OUT2 ) + ,.DEM_LSB_OUT3 ( ch0_z_DEM_LSB_OUT3 ) + ); +`endif +//------------------------------Z ch0 DAC_DEM instantiation end----------------------------- +// DAC_DEM_4 +//--------------------------------------------------------------------------------------------- + +`ifdef CHANNEL_IS_FOUR +`ifdef CHANNEL_XY_ON +//------------------------------XY ch1 DAC_DEM_16 instantiation start-------------------------- +// DAC_DEM_16 +//--------------------------------------------------------------------------------------------- +DAC_DEM_16 U1_DAC_DEM_16 ( + .CLK_IN ( clk ) + ,.prbs_en ( ch1_dac_Prbs ) + ,.set0 ( ch1_dac_Set0 ) + ,.set1 ( ch1_dac_Set1 ) + ,.set2 ( ch1_dac_Set2 ) + ,.set3 ( ch1_dac_Set3 ) + ,.set4 ( ch1_dac_Set4 ) + ,.set5 ( ch1_dac_Set5 ) + ,.set6 ( ch1_dac_Set6 ) + ,.set7 ( ch1_dac_Set7 ) + ,.set8 ( ch1_dac_Set8 ) + ,.set9 ( ch1_dac_Set9 ) + ,.set10 ( ch1_dac_Set10 ) + ,.set11 ( ch1_dac_Set11 ) + ,.set12 ( ch1_dac_Set12 ) + ,.set13 ( ch1_dac_Set13 ) + ,.set14 ( ch1_dac_Set14 ) + ,.set15 ( ch1_dac_Set15 ) + + ,.DATA_IN0 ( ch1_xy_dsp_dout0 ) + ,.DATA_IN1 ( ch1_xy_dsp_dout1 ) + ,.DATA_IN2 ( ch1_xy_dsp_dout2 ) + ,.DATA_IN3 ( ch1_xy_dsp_dout3 ) + ,.DATA_IN4 ( ch1_xy_dsp_dout4 ) + ,.DATA_IN5 ( ch1_xy_dsp_dout5 ) + ,.DATA_IN6 ( ch1_xy_dsp_dout6 ) + ,.DATA_IN7 ( ch1_xy_dsp_dout7 ) + ,.DATA_IN8 ( ch1_xy_dsp_dout8 ) + ,.DATA_IN9 ( ch1_xy_dsp_dout9 ) + ,.DATA_IN10 ( ch1_xy_dsp_dout10 ) + ,.DATA_IN11 ( ch1_xy_dsp_dout11 ) + ,.DATA_IN12 ( ch1_xy_dsp_dout12 ) + ,.DATA_IN13 ( ch1_xy_dsp_dout13 ) + ,.DATA_IN14 ( ch1_xy_dsp_dout14 ) + ,.DATA_IN15 ( ch1_xy_dsp_dout15 ) + + ,.A_DEM_MSB_OUT0 ( ch1_xy_A_DEM_MSB_OUT0 ) + ,.A_DEM_MSB_OUT1 ( ch1_xy_A_DEM_MSB_OUT1 ) + ,.A_DEM_MSB_OUT2 ( ch1_xy_A_DEM_MSB_OUT2 ) + ,.A_DEM_MSB_OUT3 ( ch1_xy_A_DEM_MSB_OUT3 ) + ,.A_DEM_MSB_OUT4 ( ch1_xy_A_DEM_MSB_OUT4 ) + ,.A_DEM_MSB_OUT5 ( ch1_xy_A_DEM_MSB_OUT5 ) + ,.A_DEM_MSB_OUT6 ( ch1_xy_A_DEM_MSB_OUT6 ) + ,.A_DEM_MSB_OUT7 ( ch1_xy_A_DEM_MSB_OUT7 ) + + ,.A_DEM_ISB_OUT0 ( ch1_xy_A_DEM_ISB_OUT0 ) + ,.A_DEM_ISB_OUT1 ( ch1_xy_A_DEM_ISB_OUT1 ) + ,.A_DEM_ISB_OUT2 ( ch1_xy_A_DEM_ISB_OUT2 ) + ,.A_DEM_ISB_OUT3 ( ch1_xy_A_DEM_ISB_OUT3 ) + ,.A_DEM_ISB_OUT4 ( ch1_xy_A_DEM_ISB_OUT4 ) + ,.A_DEM_ISB_OUT5 ( ch1_xy_A_DEM_ISB_OUT5 ) + ,.A_DEM_ISB_OUT6 ( ch1_xy_A_DEM_ISB_OUT6 ) + ,.A_DEM_ISB_OUT7 ( ch1_xy_A_DEM_ISB_OUT7 ) + + ,.A_DEM_LSB_OUT0 ( ch1_xy_A_DEM_LSB_OUT0 ) + ,.A_DEM_LSB_OUT1 ( ch1_xy_A_DEM_LSB_OUT1 ) + ,.A_DEM_LSB_OUT2 ( ch1_xy_A_DEM_LSB_OUT2 ) + ,.A_DEM_LSB_OUT3 ( ch1_xy_A_DEM_LSB_OUT3 ) + ,.A_DEM_LSB_OUT4 ( ch1_xy_A_DEM_LSB_OUT4 ) + ,.A_DEM_LSB_OUT5 ( ch1_xy_A_DEM_LSB_OUT5 ) + ,.A_DEM_LSB_OUT6 ( ch1_xy_A_DEM_LSB_OUT6 ) + ,.A_DEM_LSB_OUT7 ( ch1_xy_A_DEM_LSB_OUT7 ) + + ,.B_DEM_MSB_OUT0 ( ch1_xy_B_DEM_MSB_OUT0 ) + ,.B_DEM_MSB_OUT1 ( ch1_xy_B_DEM_MSB_OUT1 ) + ,.B_DEM_MSB_OUT2 ( ch1_xy_B_DEM_MSB_OUT2 ) + ,.B_DEM_MSB_OUT3 ( ch1_xy_B_DEM_MSB_OUT3 ) + ,.B_DEM_MSB_OUT4 ( ch1_xy_B_DEM_MSB_OUT4 ) + ,.B_DEM_MSB_OUT5 ( ch1_xy_B_DEM_MSB_OUT5 ) + ,.B_DEM_MSB_OUT6 ( ch1_xy_B_DEM_MSB_OUT6 ) + ,.B_DEM_MSB_OUT7 ( ch1_xy_B_DEM_MSB_OUT7 ) + + ,.B_DEM_ISB_OUT0 ( ch1_xy_B_DEM_ISB_OUT0 ) + ,.B_DEM_ISB_OUT1 ( ch1_xy_B_DEM_ISB_OUT1 ) + ,.B_DEM_ISB_OUT2 ( ch1_xy_B_DEM_ISB_OUT2 ) + ,.B_DEM_ISB_OUT3 ( ch1_xy_B_DEM_ISB_OUT3 ) + ,.B_DEM_ISB_OUT4 ( ch1_xy_B_DEM_ISB_OUT4 ) + ,.B_DEM_ISB_OUT5 ( ch1_xy_B_DEM_ISB_OUT5 ) + ,.B_DEM_ISB_OUT6 ( ch1_xy_B_DEM_ISB_OUT6 ) + ,.B_DEM_ISB_OUT7 ( ch1_xy_B_DEM_ISB_OUT7 ) + + ,.B_DEM_LSB_OUT0 ( ch1_xy_B_DEM_LSB_OUT0 ) + ,.B_DEM_LSB_OUT1 ( ch1_xy_B_DEM_LSB_OUT1 ) + ,.B_DEM_LSB_OUT2 ( ch1_xy_B_DEM_LSB_OUT2 ) + ,.B_DEM_LSB_OUT3 ( ch1_xy_B_DEM_LSB_OUT3 ) + ,.B_DEM_LSB_OUT4 ( ch1_xy_B_DEM_LSB_OUT4 ) + ,.B_DEM_LSB_OUT5 ( ch1_xy_B_DEM_LSB_OUT5 ) + ,.B_DEM_LSB_OUT6 ( ch1_xy_B_DEM_LSB_OUT6 ) + ,.B_DEM_LSB_OUT7 ( ch1_xy_B_DEM_LSB_OUT7 ) + ); +`endif +//------------------------------XY ch1 DAC_DEM_16 instantiation end---------------------------- +// DAC_DEM_16 +//--------------------------------------------------------------------------------------------- + +//------------------------------Z ch1 DAC_DEM_16 instantiation start--------------------------- +// DAC_DEM_4 +//--------------------------------------------------------------------------------------------- + +`ifdef CHANNEL_Z_ON +DAC_DEM_4 U1_DAC_DEM_4 ( + .CLK_IN ( clk ) + ,.prbs_en ( ch1_dac_Prbs ) + ,.set0 ( ch1_dac_Set0 ) + ,.set1 ( ch1_dac_Set1 ) + ,.set2 ( ch1_dac_Set2 ) + ,.set3 ( ch1_dac_Set3 ) + ,.DATA_IN0 ( ch1_z_dsp_dout0 ) + ,.DATA_IN1 ( ch1_z_dsp_dout1 ) + ,.DATA_IN2 ( ch1_z_dsp_dout2 ) + ,.DATA_IN3 ( ch1_z_dsp_dout3 ) + ,.DEM_MSB_OUT0 ( ch1_z_DEM_MSB_OUT0 ) + ,.DEM_MSB_OUT1 ( ch1_z_DEM_MSB_OUT1 ) + ,.DEM_MSB_OUT2 ( ch1_z_DEM_MSB_OUT2 ) + ,.DEM_MSB_OUT3 ( ch1_z_DEM_MSB_OUT3 ) + ,.DEM_ISB_OUT0 ( ch1_z_DEM_ISB_OUT0 ) + ,.DEM_ISB_OUT1 ( ch1_z_DEM_ISB_OUT1 ) + ,.DEM_ISB_OUT2 ( ch1_z_DEM_ISB_OUT2 ) + ,.DEM_ISB_OUT3 ( ch1_z_DEM_ISB_OUT3 ) + ,.DEM_LSB_OUT0 ( ch1_z_DEM_LSB_OUT0 ) + ,.DEM_LSB_OUT1 ( ch1_z_DEM_LSB_OUT1 ) + ,.DEM_LSB_OUT2 ( ch1_z_DEM_LSB_OUT2 ) + ,.DEM_LSB_OUT3 ( ch1_z_DEM_LSB_OUT3 ) + ); +`endif +//------------------------------Z ch1 DAC_DEM instantiation end----------------------------- +// DAC_DEM_4 +//--------------------------------------------------------------------------------------------- + +`ifdef CHANNEL_XY_ON +//------------------------------XY ch2 DAC_DEM_16 instantiation start-------------------------- +// DAC_DEM_16 +//--------------------------------------------------------------------------------------------- +DAC_DEM_16 U2_DAC_DEM_16 ( + .CLK_IN ( clk ) + ,.prbs_en ( ch2_dac_Prbs ) + ,.set0 ( ch2_dac_Set0 ) + ,.set1 ( ch2_dac_Set1 ) + ,.set2 ( ch2_dac_Set2 ) + ,.set3 ( ch2_dac_Set3 ) + ,.set4 ( ch2_dac_Set4 ) + ,.set5 ( ch2_dac_Set5 ) + ,.set6 ( ch2_dac_Set6 ) + ,.set7 ( ch2_dac_Set7 ) + ,.set8 ( ch2_dac_Set8 ) + ,.set9 ( ch2_dac_Set9 ) + ,.set10 ( ch2_dac_Set10 ) + ,.set11 ( ch2_dac_Set11 ) + ,.set12 ( ch2_dac_Set12 ) + ,.set13 ( ch2_dac_Set13 ) + ,.set14 ( ch2_dac_Set14 ) + ,.set15 ( ch2_dac_Set15 ) + + ,.DATA_IN0 ( ch2_xy_dsp_dout0 ) + ,.DATA_IN1 ( ch2_xy_dsp_dout1 ) + ,.DATA_IN2 ( ch2_xy_dsp_dout2 ) + ,.DATA_IN3 ( ch2_xy_dsp_dout3 ) + ,.DATA_IN4 ( ch2_xy_dsp_dout4 ) + ,.DATA_IN5 ( ch2_xy_dsp_dout5 ) + ,.DATA_IN6 ( ch2_xy_dsp_dout6 ) + ,.DATA_IN7 ( ch2_xy_dsp_dout7 ) + ,.DATA_IN8 ( ch2_xy_dsp_dout8 ) + ,.DATA_IN9 ( ch2_xy_dsp_dout9 ) + ,.DATA_IN10 ( ch2_xy_dsp_dout10 ) + ,.DATA_IN11 ( ch2_xy_dsp_dout11 ) + ,.DATA_IN12 ( ch2_xy_dsp_dout12 ) + ,.DATA_IN13 ( ch2_xy_dsp_dout13 ) + ,.DATA_IN14 ( ch2_xy_dsp_dout14 ) + ,.DATA_IN15 ( ch2_xy_dsp_dout15 ) + + ,.A_DEM_MSB_OUT0 ( ch2_xy_A_DEM_MSB_OUT0 ) + ,.A_DEM_MSB_OUT1 ( ch2_xy_A_DEM_MSB_OUT1 ) + ,.A_DEM_MSB_OUT2 ( ch2_xy_A_DEM_MSB_OUT2 ) + ,.A_DEM_MSB_OUT3 ( ch2_xy_A_DEM_MSB_OUT3 ) + ,.A_DEM_MSB_OUT4 ( ch2_xy_A_DEM_MSB_OUT4 ) + ,.A_DEM_MSB_OUT5 ( ch2_xy_A_DEM_MSB_OUT5 ) + ,.A_DEM_MSB_OUT6 ( ch2_xy_A_DEM_MSB_OUT6 ) + ,.A_DEM_MSB_OUT7 ( ch2_xy_A_DEM_MSB_OUT7 ) + + ,.A_DEM_ISB_OUT0 ( ch2_xy_A_DEM_ISB_OUT0 ) + ,.A_DEM_ISB_OUT1 ( ch2_xy_A_DEM_ISB_OUT1 ) + ,.A_DEM_ISB_OUT2 ( ch2_xy_A_DEM_ISB_OUT2 ) + ,.A_DEM_ISB_OUT3 ( ch2_xy_A_DEM_ISB_OUT3 ) + ,.A_DEM_ISB_OUT4 ( ch2_xy_A_DEM_ISB_OUT4 ) + ,.A_DEM_ISB_OUT5 ( ch2_xy_A_DEM_ISB_OUT5 ) + ,.A_DEM_ISB_OUT6 ( ch2_xy_A_DEM_ISB_OUT6 ) + ,.A_DEM_ISB_OUT7 ( ch2_xy_A_DEM_ISB_OUT7 ) + + ,.A_DEM_LSB_OUT0 ( ch2_xy_A_DEM_LSB_OUT0 ) + ,.A_DEM_LSB_OUT1 ( ch2_xy_A_DEM_LSB_OUT1 ) + ,.A_DEM_LSB_OUT2 ( ch2_xy_A_DEM_LSB_OUT2 ) + ,.A_DEM_LSB_OUT3 ( ch2_xy_A_DEM_LSB_OUT3 ) + ,.A_DEM_LSB_OUT4 ( ch2_xy_A_DEM_LSB_OUT4 ) + ,.A_DEM_LSB_OUT5 ( ch2_xy_A_DEM_LSB_OUT5 ) + ,.A_DEM_LSB_OUT6 ( ch2_xy_A_DEM_LSB_OUT6 ) + ,.A_DEM_LSB_OUT7 ( ch2_xy_A_DEM_LSB_OUT7 ) + + ,.B_DEM_MSB_OUT0 ( ch2_xy_B_DEM_MSB_OUT0 ) + ,.B_DEM_MSB_OUT1 ( ch2_xy_B_DEM_MSB_OUT1 ) + ,.B_DEM_MSB_OUT2 ( ch2_xy_B_DEM_MSB_OUT2 ) + ,.B_DEM_MSB_OUT3 ( ch2_xy_B_DEM_MSB_OUT3 ) + ,.B_DEM_MSB_OUT4 ( ch2_xy_B_DEM_MSB_OUT4 ) + ,.B_DEM_MSB_OUT5 ( ch2_xy_B_DEM_MSB_OUT5 ) + ,.B_DEM_MSB_OUT6 ( ch2_xy_B_DEM_MSB_OUT6 ) + ,.B_DEM_MSB_OUT7 ( ch2_xy_B_DEM_MSB_OUT7 ) + + ,.B_DEM_ISB_OUT0 ( ch2_xy_B_DEM_ISB_OUT0 ) + ,.B_DEM_ISB_OUT1 ( ch2_xy_B_DEM_ISB_OUT1 ) + ,.B_DEM_ISB_OUT2 ( ch2_xy_B_DEM_ISB_OUT2 ) + ,.B_DEM_ISB_OUT3 ( ch2_xy_B_DEM_ISB_OUT3 ) + ,.B_DEM_ISB_OUT4 ( ch2_xy_B_DEM_ISB_OUT4 ) + ,.B_DEM_ISB_OUT5 ( ch2_xy_B_DEM_ISB_OUT5 ) + ,.B_DEM_ISB_OUT6 ( ch2_xy_B_DEM_ISB_OUT6 ) + ,.B_DEM_ISB_OUT7 ( ch2_xy_B_DEM_ISB_OUT7 ) + + ,.B_DEM_LSB_OUT0 ( ch2_xy_B_DEM_LSB_OUT0 ) + ,.B_DEM_LSB_OUT1 ( ch2_xy_B_DEM_LSB_OUT1 ) + ,.B_DEM_LSB_OUT2 ( ch2_xy_B_DEM_LSB_OUT2 ) + ,.B_DEM_LSB_OUT3 ( ch2_xy_B_DEM_LSB_OUT3 ) + ,.B_DEM_LSB_OUT4 ( ch2_xy_B_DEM_LSB_OUT4 ) + ,.B_DEM_LSB_OUT5 ( ch2_xy_B_DEM_LSB_OUT5 ) + ,.B_DEM_LSB_OUT6 ( ch2_xy_B_DEM_LSB_OUT6 ) + ,.B_DEM_LSB_OUT7 ( ch2_xy_B_DEM_LSB_OUT7 ) + ); +`endif +//------------------------------XY ch2 DAC_DEM_16 instantiation end---------------------------- +// DAC_DEM_16 +//--------------------------------------------------------------------------------------------- + +//------------------------------Z ch2 DAC_DEM_16 instantiation start--------------------------- +// DAC_DEM_4 +//--------------------------------------------------------------------------------------------- + +`ifdef CHANNEL_Z_ON +DAC_DEM_4 U2_DAC_DEM_4 ( + .CLK_IN ( clk ) + ,.prbs_en ( ch2_dac_Prbs ) + ,.set0 ( ch2_dac_Set0 ) + ,.set1 ( ch2_dac_Set1 ) + ,.set2 ( ch2_dac_Set2 ) + ,.set3 ( ch2_dac_Set3 ) + ,.DATA_IN0 ( ch2_z_dsp_dout0 ) + ,.DATA_IN1 ( ch2_z_dsp_dout1 ) + ,.DATA_IN2 ( ch2_z_dsp_dout2 ) + ,.DATA_IN3 ( ch2_z_dsp_dout3 ) + ,.DEM_MSB_OUT0 ( ch2_z_DEM_MSB_OUT0 ) + ,.DEM_MSB_OUT1 ( ch2_z_DEM_MSB_OUT1 ) + ,.DEM_MSB_OUT2 ( ch2_z_DEM_MSB_OUT2 ) + ,.DEM_MSB_OUT3 ( ch2_z_DEM_MSB_OUT3 ) + ,.DEM_ISB_OUT0 ( ch2_z_DEM_ISB_OUT0 ) + ,.DEM_ISB_OUT1 ( ch2_z_DEM_ISB_OUT1 ) + ,.DEM_ISB_OUT2 ( ch2_z_DEM_ISB_OUT2 ) + ,.DEM_ISB_OUT3 ( ch2_z_DEM_ISB_OUT3 ) + ,.DEM_LSB_OUT0 ( ch2_z_DEM_LSB_OUT0 ) + ,.DEM_LSB_OUT1 ( ch2_z_DEM_LSB_OUT1 ) + ,.DEM_LSB_OUT2 ( ch2_z_DEM_LSB_OUT2 ) + ,.DEM_LSB_OUT3 ( ch2_z_DEM_LSB_OUT3 ) + ); +`endif +//------------------------------Z ch2 DAC_DEM instantiation end----------------------------- +// DAC_DEM_4 +//--------------------------------------------------------------------------------------------- + +`ifdef CHANNEL_XY_ON +//------------------------------XY ch3 DAC_DEM_16 instantiation start-------------------------- +// DAC_DEM_16 +//--------------------------------------------------------------------------------------------- +DAC_DEM_16 U3_DAC_DEM_16 ( + .CLK_IN ( clk ) + ,.prbs_en ( ch3_dac_Prbs ) + ,.set0 ( ch3_dac_Set0 ) + ,.set1 ( ch3_dac_Set1 ) + ,.set2 ( ch3_dac_Set2 ) + ,.set3 ( ch3_dac_Set3 ) + ,.set4 ( ch3_dac_Set4 ) + ,.set5 ( ch3_dac_Set5 ) + ,.set6 ( ch3_dac_Set6 ) + ,.set7 ( ch3_dac_Set7 ) + ,.set8 ( ch3_dac_Set8 ) + ,.set9 ( ch3_dac_Set9 ) + ,.set10 ( ch3_dac_Set10 ) + ,.set11 ( ch3_dac_Set11 ) + ,.set12 ( ch3_dac_Set12 ) + ,.set13 ( ch3_dac_Set13 ) + ,.set14 ( ch3_dac_Set14 ) + ,.set15 ( ch3_dac_Set15 ) + + ,.DATA_IN0 ( ch3_xy_dsp_dout0 ) + ,.DATA_IN1 ( ch3_xy_dsp_dout1 ) + ,.DATA_IN2 ( ch3_xy_dsp_dout2 ) + ,.DATA_IN3 ( ch3_xy_dsp_dout3 ) + ,.DATA_IN4 ( ch3_xy_dsp_dout4 ) + ,.DATA_IN5 ( ch3_xy_dsp_dout5 ) + ,.DATA_IN6 ( ch3_xy_dsp_dout6 ) + ,.DATA_IN7 ( ch3_xy_dsp_dout7 ) + ,.DATA_IN8 ( ch3_xy_dsp_dout8 ) + ,.DATA_IN9 ( ch3_xy_dsp_dout9 ) + ,.DATA_IN10 ( ch3_xy_dsp_dout10 ) + ,.DATA_IN11 ( ch3_xy_dsp_dout11 ) + ,.DATA_IN12 ( ch3_xy_dsp_dout12 ) + ,.DATA_IN13 ( ch3_xy_dsp_dout13 ) + ,.DATA_IN14 ( ch3_xy_dsp_dout14 ) + ,.DATA_IN15 ( ch3_xy_dsp_dout15 ) + + ,.A_DEM_MSB_OUT0 ( ch3_xy_A_DEM_MSB_OUT0 ) + ,.A_DEM_MSB_OUT1 ( ch3_xy_A_DEM_MSB_OUT1 ) + ,.A_DEM_MSB_OUT2 ( ch3_xy_A_DEM_MSB_OUT2 ) + ,.A_DEM_MSB_OUT3 ( ch3_xy_A_DEM_MSB_OUT3 ) + ,.A_DEM_MSB_OUT4 ( ch3_xy_A_DEM_MSB_OUT4 ) + ,.A_DEM_MSB_OUT5 ( ch3_xy_A_DEM_MSB_OUT5 ) + ,.A_DEM_MSB_OUT6 ( ch3_xy_A_DEM_MSB_OUT6 ) + ,.A_DEM_MSB_OUT7 ( ch3_xy_A_DEM_MSB_OUT7 ) + + ,.A_DEM_ISB_OUT0 ( ch3_xy_A_DEM_ISB_OUT0 ) + ,.A_DEM_ISB_OUT1 ( ch3_xy_A_DEM_ISB_OUT1 ) + ,.A_DEM_ISB_OUT2 ( ch3_xy_A_DEM_ISB_OUT2 ) + ,.A_DEM_ISB_OUT3 ( ch3_xy_A_DEM_ISB_OUT3 ) + ,.A_DEM_ISB_OUT4 ( ch3_xy_A_DEM_ISB_OUT4 ) + ,.A_DEM_ISB_OUT5 ( ch3_xy_A_DEM_ISB_OUT5 ) + ,.A_DEM_ISB_OUT6 ( ch3_xy_A_DEM_ISB_OUT6 ) + ,.A_DEM_ISB_OUT7 ( ch3_xy_A_DEM_ISB_OUT7 ) + + ,.A_DEM_LSB_OUT0 ( ch3_xy_A_DEM_LSB_OUT0 ) + ,.A_DEM_LSB_OUT1 ( ch3_xy_A_DEM_LSB_OUT1 ) + ,.A_DEM_LSB_OUT2 ( ch3_xy_A_DEM_LSB_OUT2 ) + ,.A_DEM_LSB_OUT3 ( ch3_xy_A_DEM_LSB_OUT3 ) + ,.A_DEM_LSB_OUT4 ( ch3_xy_A_DEM_LSB_OUT4 ) + ,.A_DEM_LSB_OUT5 ( ch3_xy_A_DEM_LSB_OUT5 ) + ,.A_DEM_LSB_OUT6 ( ch3_xy_A_DEM_LSB_OUT6 ) + ,.A_DEM_LSB_OUT7 ( ch3_xy_A_DEM_LSB_OUT7 ) + + ,.B_DEM_MSB_OUT0 ( ch3_xy_B_DEM_MSB_OUT0 ) + ,.B_DEM_MSB_OUT1 ( ch3_xy_B_DEM_MSB_OUT1 ) + ,.B_DEM_MSB_OUT2 ( ch3_xy_B_DEM_MSB_OUT2 ) + ,.B_DEM_MSB_OUT3 ( ch3_xy_B_DEM_MSB_OUT3 ) + ,.B_DEM_MSB_OUT4 ( ch3_xy_B_DEM_MSB_OUT4 ) + ,.B_DEM_MSB_OUT5 ( ch3_xy_B_DEM_MSB_OUT5 ) + ,.B_DEM_MSB_OUT6 ( ch3_xy_B_DEM_MSB_OUT6 ) + ,.B_DEM_MSB_OUT7 ( ch3_xy_B_DEM_MSB_OUT7 ) + + ,.B_DEM_ISB_OUT0 ( ch3_xy_B_DEM_ISB_OUT0 ) + ,.B_DEM_ISB_OUT1 ( ch3_xy_B_DEM_ISB_OUT1 ) + ,.B_DEM_ISB_OUT2 ( ch3_xy_B_DEM_ISB_OUT2 ) + ,.B_DEM_ISB_OUT3 ( ch3_xy_B_DEM_ISB_OUT3 ) + ,.B_DEM_ISB_OUT4 ( ch3_xy_B_DEM_ISB_OUT4 ) + ,.B_DEM_ISB_OUT5 ( ch3_xy_B_DEM_ISB_OUT5 ) + ,.B_DEM_ISB_OUT6 ( ch3_xy_B_DEM_ISB_OUT6 ) + ,.B_DEM_ISB_OUT7 ( ch3_xy_B_DEM_ISB_OUT7 ) + + ,.B_DEM_LSB_OUT0 ( ch3_xy_B_DEM_LSB_OUT0 ) + ,.B_DEM_LSB_OUT1 ( ch3_xy_B_DEM_LSB_OUT1 ) + ,.B_DEM_LSB_OUT2 ( ch3_xy_B_DEM_LSB_OUT2 ) + ,.B_DEM_LSB_OUT3 ( ch3_xy_B_DEM_LSB_OUT3 ) + ,.B_DEM_LSB_OUT4 ( ch3_xy_B_DEM_LSB_OUT4 ) + ,.B_DEM_LSB_OUT5 ( ch3_xy_B_DEM_LSB_OUT5 ) + ,.B_DEM_LSB_OUT6 ( ch3_xy_B_DEM_LSB_OUT6 ) + ,.B_DEM_LSB_OUT7 ( ch3_xy_B_DEM_LSB_OUT7 ) + ); +`endif +//------------------------------XY ch3 DAC_DEM_16 instantiation end---------------------------- +// DAC_DEM_16 +//--------------------------------------------------------------------------------------------- + +//------------------------------Z ch3 DAC_DEM_16 instantiation start--------------------------- +// DAC_DEM_4 +//--------------------------------------------------------------------------------------------- + +`ifdef CHANNEL_Z_ON +DAC_DEM_4 U3_DAC_DEM_4 ( + .CLK_IN ( clk ) + ,.prbs_en ( ch3_dac_Prbs ) + ,.set0 ( ch3_dac_Set0 ) + ,.set1 ( ch3_dac_Set1 ) + ,.set2 ( ch3_dac_Set2 ) + ,.set3 ( ch3_dac_Set3 ) + ,.DATA_IN0 ( ch3_z_dsp_dout0 ) + ,.DATA_IN1 ( ch3_z_dsp_dout1 ) + ,.DATA_IN2 ( ch3_z_dsp_dout2 ) + ,.DATA_IN3 ( ch3_z_dsp_dout3 ) + ,.DEM_MSB_OUT0 ( ch3_z_DEM_MSB_OUT0 ) + ,.DEM_MSB_OUT1 ( ch3_z_DEM_MSB_OUT1 ) + ,.DEM_MSB_OUT2 ( ch3_z_DEM_MSB_OUT2 ) + ,.DEM_MSB_OUT3 ( ch3_z_DEM_MSB_OUT3 ) + ,.DEM_ISB_OUT0 ( ch3_z_DEM_ISB_OUT0 ) + ,.DEM_ISB_OUT1 ( ch3_z_DEM_ISB_OUT1 ) + ,.DEM_ISB_OUT2 ( ch3_z_DEM_ISB_OUT2 ) + ,.DEM_ISB_OUT3 ( ch3_z_DEM_ISB_OUT3 ) + ,.DEM_LSB_OUT0 ( ch3_z_DEM_LSB_OUT0 ) + ,.DEM_LSB_OUT1 ( ch3_z_DEM_LSB_OUT1 ) + ,.DEM_LSB_OUT2 ( ch3_z_DEM_LSB_OUT2 ) + ,.DEM_LSB_OUT3 ( ch3_z_DEM_LSB_OUT3 ) + ); +`endif +//------------------------------Z ch3 DAC_DEM instantiation end----------------------------- +// DAC_DEM_4 +//--------------------------------------------------------------------------------------------- + +`endif + + + + + + +endmodule \ No newline at end of file diff --git a/rtl/top/z_data_mux.v b/rtl/top/z_data_mux.v new file mode 100644 index 0000000..3fbf505 --- /dev/null +++ b/rtl/top/z_data_mux.v @@ -0,0 +1,69 @@ +//+FHDR-------------------------------------------------------------------------------------------------------- +// Company: +//----------------------------------------------------------------------------------------------------------------- +// File Name : z_data_mux.v +// Department : +// Author : PWY +// Author's Tel : +//----------------------------------------------------------------------------------------------------------------- +// Relese History +// Version Date Author Description +// 0.1 2024-05-13 PWY debug top-level +//----------------------------------------------------------------------------------------------------------------- +// Keywords : +// +//----------------------------------------------------------------------------------------------------------------- +// Parameter +// +//----------------------------------------------------------------------------------------------------------------- +// Purpose : +// +//----------------------------------------------------------------------------------------------------------------- +// Target Device: +// Tool versions: +//----------------------------------------------------------------------------------------------------------------- +// Reuse Issues +// Reset Strategy: +// Clock Domains: +// Critical Timing: +// Asynchronous I/F: +// Synthesizable (y/n): +// Other: +//-FHDR-------------------------------------------------------------------------------------------------------- + +module z_data_mux ( +//system port + input clk // System Main Clock + ,input rst_n // Spi Reset active low + //---------------from ctrl regfile------------------------------------ + ,input sel // 1'b0 --> mod modem data; 1'b1 --> mod nco data + //Z dsp data + ,input [15:0] z_dsp_data0 + ,input [15:0] z_dsp_data1 + ,input [15:0] z_dsp_data2 + ,input [15:0] z_dsp_data3 + //XY dsp data + ,input [15:0] xy_dsp_data0 + ,input [15:0] xy_dsp_data1 + ,input [15:0] xy_dsp_data2 + ,input [15:0] xy_dsp_data3 + //mux out data + ,output [15:0] mux_data_0 + ,output [15:0] mux_data_1 + ,output [15:0] mux_data_2 + ,output [15:0] mux_data_3 +); + + +wire [15:0] mux_data_0_w = sel ? xy_dsp_data0 : z_dsp_data0; +wire [15:0] mux_data_1_w = sel ? xy_dsp_data1 : z_dsp_data1; +wire [15:0] mux_data_2_w = sel ? xy_dsp_data2 : z_dsp_data2; +wire [15:0] mux_data_3_w = sel ? xy_dsp_data3 : z_dsp_data3; + +sirv_gnrl_dffr #(16) mux_data_0_dffr (mux_data_0_w , mux_data_0 , clk, rst_n); +sirv_gnrl_dffr #(16) mux_data_1_dffr (mux_data_1_w , mux_data_1 , clk, rst_n); +sirv_gnrl_dffr #(16) mux_data_2_dffr (mux_data_2_w , mux_data_2 , clk, rst_n); +sirv_gnrl_dffr #(16) mux_data_3_dffr (mux_data_3_w , mux_data_3 , clk, rst_n); +endmodule + + diff --git a/rtl/xy_dsp/dacif/dacif.v b/rtl/xy_dsp/dacif/dacif.v new file mode 100644 index 0000000..92ac0f2 --- /dev/null +++ b/rtl/xy_dsp/dacif/dacif.v @@ -0,0 +1,363 @@ +//+FHDR-------------------------------------------------------------------------------------------------------- +// Company: +//----------------------------------------------------------------------------------------------------------------- +// File Name : dacif.v +// Department : +// Author : PWY +// Author's Tel : +//----------------------------------------------------------------------------------------------------------------- +// Relese History +// Version Date Author Description +// 0.4 2024-03-12 PWY +//----------------------------------------------------------------------------------------------------------------- +// Keywords : +// +//----------------------------------------------------------------------------------------------------------------- +// Parameter +// +//----------------------------------------------------------------------------------------------------------------- +// Purpose : +// +//----------------------------------------------------------------------------------------------------------------- +// Target Device: +// Tool versions: +//----------------------------------------------------------------------------------------------------------------- +// Reuse Issues +// Reset Strategy: +// Clock Domains: +// Critical Timing: +// Asynchronous I/F: +// Synthesizable (y/n): +// Other: +//-FHDR-------------------------------------------------------------------------------------------------------- + +module dacif ( + input clk + ,input rstn + //DAC mode select + ,input [1:0] dac_mode_sel //2'b00:NRZ mode;2'b01:MIX mode; + //2'b10:2xNRZ mode;2'b00:reserve; + ,input [2 :0] intp_mode //3'b000:x1;3'b001:x2;3'b010:x4; + //3'b011:x8;3'b100:x16; + ,input din_vld + ,output dout_vld + //mixer data input + ,input [15:0] din0 + ,input [15:0] din1 + ,input [15:0] din2 + ,input [15:0] din3 + ,input [15:0] din4 + ,input [15:0] din5 + ,input [15:0] din6 + ,input [15:0] din7 + ,input [15:0] din8 + ,input [15:0] din9 + ,input [15:0] din10 + ,input [15:0] din11 + ,input [15:0] din12 + ,input [15:0] din13 + ,input [15:0] din14 + ,input [15:0] din15 + //data output + ,output [15:0] dout0 + ,output [15:0] dout1 + ,output [15:0] dout2 + ,output [15:0] dout3 + ,output [15:0] dout4 + ,output [15:0] dout5 + ,output [15:0] dout6 + ,output [15:0] dout7 + ,output [15:0] dout8 + ,output [15:0] dout9 + ,output [15:0] dout10 + ,output [15:0] dout11 + ,output [15:0] dout12 + ,output [15:0] dout13 + ,output [15:0] dout14 + ,output [15:0] dout15 +); + +//////////////////////////////////////////////////// +// regs +//////////////////////////////////////////////////// +reg [15:0] dout0_r ; +reg [15:0] dout1_r ; +reg [15:0] dout2_r ; +reg [15:0] dout3_r ; +reg [15:0] dout4_r ; +reg [15:0] dout5_r ; +reg [15:0] dout6_r ; +reg [15:0] dout7_r ; +reg [15:0] dout8_r ; +reg [15:0] dout9_r ; +reg [15:0] dout10_r; +reg [15:0] dout11_r; +reg [15:0] dout12_r; +reg [15:0] dout13_r; +reg [15:0] dout14_r; +reg [15:0] dout15_r; + +reg [15:0] mux_p_0; +reg [15:0] mux_p_1; +reg [15:0] mux_p_2; +reg [15:0] mux_p_3; +reg [15:0] mux_p_4; +reg [15:0] mux_p_5; +reg [15:0] mux_p_6; +reg [15:0] mux_p_7; +reg [15:0] mux_p_8; +reg [15:0] mux_p_9; +reg [15:0] mux_p_a; +reg [15:0] mux_p_b; +reg [15:0] mux_p_c; +reg [15:0] mux_p_d; +reg [15:0] mux_p_e; +reg [15:0] mux_p_f; + +reg [1:0] dacif_vld_dly; +//////////////////////////////////////////////////// +// intp mode select +//////////////////////////////////////////////////// +always@(posedge clk) begin + case(intp_mode) + 3'b000 : begin + mux_p_0 <= {~din15[15],din15[14:0]}; + mux_p_1 <= 16'h8000; + mux_p_2 <= 16'h8000; + mux_p_3 <= 16'h8000; + mux_p_4 <= 16'h8000; + mux_p_5 <= 16'h8000; + mux_p_6 <= 16'h8000; + mux_p_7 <= 16'h8000; + mux_p_8 <= 16'h8000; + mux_p_9 <= 16'h8000; + mux_p_a <= 16'h8000; + mux_p_b <= 16'h8000; + mux_p_c <= 16'h8000; + mux_p_d <= 16'h8000; + mux_p_e <= 16'h8000; + mux_p_f <= 16'h8000; + end + 3'b001 : begin + mux_p_0 <= {~din7[15],din7[14:0]}; + mux_p_1 <= {~din15[15],din15[14:0]}; + mux_p_2 <= 16'h8000 ; + mux_p_3 <= 16'h8000 ; + mux_p_4 <= 16'h8000 ; + mux_p_5 <= 16'h8000 ; + mux_p_6 <= 16'h8000 ; + mux_p_7 <= 16'h8000 ; + mux_p_8 <= 16'h8000 ; + mux_p_9 <= 16'h8000 ; + mux_p_a <= 16'h8000 ; + mux_p_b <= 16'h8000 ; + mux_p_c <= 16'h8000 ; + mux_p_d <= 16'h8000 ; + mux_p_e <= 16'h8000 ; + mux_p_f <= 16'h8000 ; + end + 3'b010 : begin + mux_p_0 <= {~din3[15],din3[14:0]} ; + mux_p_1 <= {~din7[15],din7[14:0]} ; + mux_p_2 <= {~din11[15],din11[14:0]} ; + mux_p_3 <= {~din15[15],din15[14:0]}; + mux_p_4 <= 16'h8000; + mux_p_5 <= 16'h8000; + mux_p_6 <= 16'h8000; + mux_p_7 <= 16'h8000; + mux_p_8 <= 16'h8000; + mux_p_9 <= 16'h8000; + mux_p_a <= 16'h8000; + mux_p_b <= 16'h8000; + mux_p_c <= 16'h8000; + mux_p_d <= 16'h8000; + mux_p_e <= 16'h8000; + mux_p_f <= 16'h8000; + end + 3'b011 : begin + mux_p_0 <= {~din1[15],din1[14:0]} ; + mux_p_1 <= {~din3[15],din3[14:0]} ; + mux_p_2 <= {~din5[15],din5[14:0]} ; + mux_p_3 <= {~din7[15],din7[14:0]} ; + mux_p_4 <= {~din9[15],din9[14:0]} ; + mux_p_5 <= {~din11[15],din11[14:0]}; + mux_p_6 <= {~din13[15],din13[14:0]}; + mux_p_7 <= {~din15[15],din15[14:0]}; + mux_p_8 <= 16'h8000 ; + mux_p_9 <= 16'h8000 ; + mux_p_a <= 16'h8000 ; + mux_p_b <= 16'h8000 ; + mux_p_c <= 16'h8000 ; + mux_p_d <= 16'h8000 ; + mux_p_e <= 16'h8000 ; + mux_p_f <= 16'h8000 ; + end + 3'b100 : begin + mux_p_0 <= {~din0[15],din0[14:0]} ; + mux_p_1 <= {~din1[15],din1[14:0]} ; + mux_p_2 <= {~din2[15],din2[14:0]} ; + mux_p_3 <= {~din3[15],din3[14:0]} ; + mux_p_4 <= {~din4[15],din4[14:0]} ; + mux_p_5 <= {~din5[15],din5[14:0]} ; + mux_p_6 <= {~din6[15],din6[14:0]} ; + mux_p_7 <= {~din7[15],din7[14:0]} ; + mux_p_8 <= {~din8[15],din8[14:0]} ; + mux_p_9 <= {~din9[15],din9[14:0]} ; + mux_p_a <= {~din10[15],din10[14:0]}; + mux_p_b <= {~din11[15],din11[14:0]}; + mux_p_c <= {~din12[15],din12[14:0]}; + mux_p_d <= {~din13[15],din13[14:0]}; + mux_p_e <= {~din14[15],din14[14:0]}; + mux_p_f <= {~din15[15],din15[14:0]}; + end + default : begin + mux_p_0 <= 16'h8000; + mux_p_1 <= 16'h8000; + mux_p_2 <= 16'h8000; + mux_p_3 <= 16'h8000; + mux_p_4 <= 16'h8000; + mux_p_5 <= 16'h8000; + mux_p_6 <= 16'h8000; + mux_p_7 <= 16'h8000; + mux_p_8 <= 16'h8000; + mux_p_9 <= 16'h8000; + mux_p_a <= 16'h8000; + mux_p_b <= 16'h8000; + mux_p_c <= 16'h8000; + mux_p_d <= 16'h8000; + mux_p_e <= 16'h8000; + mux_p_f <= 16'h8000; + end + endcase +end + +//////////////////////////////////////////////////// +// mode select +//////////////////////////////////////////////////// +always @(posedge clk or negedge rstn) begin + if(rstn == 1'b0) begin + dout0_r <= 16'h8000; + dout1_r <= 16'h8000; + dout2_r <= 16'h8000; + dout3_r <= 16'h8000; + dout4_r <= 16'h8000; + dout5_r <= 16'h8000; + dout6_r <= 16'h8000; + dout7_r <= 16'h8000; + dout8_r <= 16'h8000; + dout9_r <= 16'h8000; + dout10_r <= 16'h8000; + dout11_r <= 16'h8000; + dout12_r <= 16'h8000; + dout13_r <= 16'h8000; + dout14_r <= 16'h8000; + dout15_r <= 16'h8000; + end + else begin + case(dac_mode_sel) + 2'b00 : begin + dout0_r <= mux_p_0; + dout1_r <= mux_p_1; + dout2_r <= mux_p_2; + dout3_r <= mux_p_3; + dout4_r <= mux_p_4; + dout5_r <= mux_p_5; + dout6_r <= mux_p_6; + dout7_r <= mux_p_7; + dout8_r <= mux_p_0; + dout9_r <= mux_p_1; + dout10_r <= mux_p_2; + dout11_r <= mux_p_3; + dout12_r <= mux_p_4; + dout13_r <= mux_p_5; + dout14_r <= mux_p_6; + dout15_r <= mux_p_7; + end + 2'b01 : begin + dout0_r <= mux_p_0; + dout1_r <= mux_p_1; + dout2_r <= mux_p_2; + dout3_r <= mux_p_3; + dout4_r <= mux_p_4; + dout5_r <= mux_p_5; + dout6_r <= mux_p_6; + dout7_r <= mux_p_7; + dout8_r <= ~mux_p_0; + dout9_r <= ~mux_p_1; + dout10_r <= ~mux_p_2; + dout11_r <= ~mux_p_3; + dout12_r <= ~mux_p_4; + dout13_r <= ~mux_p_5; + dout14_r <= ~mux_p_6; + dout15_r <= ~mux_p_7; + end + 2'b10 : begin + dout0_r <= mux_p_0; + dout1_r <= mux_p_2; + dout2_r <= mux_p_4; + dout3_r <= mux_p_6; + dout4_r <= mux_p_8; + dout5_r <= mux_p_a; + dout6_r <= mux_p_c; + dout7_r <= mux_p_e; + dout8_r <= mux_p_1; + dout9_r <= mux_p_3; + dout10_r <= mux_p_5; + dout11_r <= mux_p_7; + dout12_r <= mux_p_9; + dout13_r <= mux_p_b; + dout14_r <= mux_p_d; + dout15_r <= mux_p_f; + end + 2'b11 : begin + dout0_r <= mux_p_0; + dout1_r <= mux_p_1; + dout2_r <= mux_p_2; + dout3_r <= mux_p_3; + dout4_r <= mux_p_4; + dout5_r <= mux_p_5; + dout6_r <= mux_p_6; + dout7_r <= mux_p_7; + dout8_r <= mux_p_8; + dout9_r <= mux_p_9; + dout10_r <= mux_p_a; + dout11_r <= mux_p_b; + dout12_r <= mux_p_c; + dout13_r <= mux_p_d; + dout14_r <= mux_p_e; + dout15_r <= mux_p_f; + end + endcase + end +end + +assign dout0 = dout0_r ; +assign dout1 = dout1_r ; +assign dout2 = dout2_r ; +assign dout3 = dout3_r ; +assign dout4 = dout4_r ; +assign dout5 = dout5_r ; +assign dout6 = dout6_r ; +assign dout7 = dout7_r ; +assign dout8 = dout8_r ; +assign dout9 = dout9_r ; +assign dout10 = dout10_r ; +assign dout11 = dout11_r ; +assign dout12 = dout12_r ; +assign dout13 = dout13_r ; +assign dout14 = dout14_r ; +assign dout15 = dout15_r ; + +//vld +always @(posedge clk or negedge rstn) begin + if(rstn == 1'b0) begin + dacif_vld_dly <= 2'b0; + end + else begin + dacif_vld_dly <= {dacif_vld_dly[0],din_vld}; + end +end + +assign dout_vld = dacif_vld_dly[1]; + +endmodule diff --git a/rtl/xy_dsp/dsp_top/dsp_top.v b/rtl/xy_dsp/dsp_top/dsp_top.v new file mode 100644 index 0000000..6d50c06 --- /dev/null +++ b/rtl/xy_dsp/dsp_top/dsp_top.v @@ -0,0 +1,272 @@ +//+FHDR-------------------------------------------------------------------------------------------------------- +// Company: +//----------------------------------------------------------------------------------------------------------------- +// File Name : dsp_top.v +// Department : +// Author : PWY +// Author's Tel : +//----------------------------------------------------------------------------------------------------------------- +// Relese History +// Version Date Author Description +// 0.4 2024-03-12 PWY +//----------------------------------------------------------------------------------------------------------------- +// Keywords : +// +//----------------------------------------------------------------------------------------------------------------- +// Parameter +// +//----------------------------------------------------------------------------------------------------------------- +// Purpose : +// +//----------------------------------------------------------------------------------------------------------------- +// Target Device: +// Tool versions: +//----------------------------------------------------------------------------------------------------------------- +// Reuse Issues +// Reset Strategy: +// Clock Domains: +// Critical Timing: +// Asynchronous I/F: +// Synthesizable (y/n): +// Other: +//-FHDR-------------------------------------------------------------------------------------------------------- +module dsp_top ( + input clk + ,input rstn + ,input phase_manual_clr + ,input phase_auto_clr + ,input [47:0] fcw + ,input [15:0] pha + ,input [1 :0] qam_mod //2'b00:bypass;2'b01:mix; + //2'b10:cos;2'b11:sin; + ,input sel_sideband //1'b0:Upper sideband;1'b1:Lower sideband; + ,input [2 :0] intp_mode //3'b000:x1;3'b001:x2;3'b010:x4; + //3'b011:x8;3'b100:x16; + ,input [1:0] dac_mode_sel //2'b00:NRZ mode;2'b01:MIX mode; + //2'b10:2xNRZ mode;2'b00:reserve; + ,input [15:0] din_i + + ,input [15:0] din_q + + //data output + ,output [15:0] dout0 + ,output [15:0] dout1 + ,output [15:0] dout2 + ,output [15:0] dout3 + ,output [15:0] dout4 + ,output [15:0] dout5 + ,output [15:0] dout6 + ,output [15:0] dout7 + ,output [15:0] dout8 + ,output [15:0] dout9 + ,output [15:0] dout10 + ,output [15:0] dout11 + ,output [15:0] dout12 + ,output [15:0] dout13 + ,output [15:0] dout14 + ,output [15:0] dout15 + ); + +wire [15:0] dt_i_0; +wire [15:0] dt_i_1; +wire [15:0] dt_i_2; +wire [15:0] dt_i_3; +wire [15:0] dt_i_4; +wire [15:0] dt_i_5; +wire [15:0] dt_i_6; +wire [15:0] dt_i_7; +wire [15:0] dt_i_8; +wire [15:0] dt_i_9; +wire [15:0] dt_i_a; +wire [15:0] dt_i_b; +wire [15:0] dt_i_c; +wire [15:0] dt_i_d; +wire [15:0] dt_i_e; +wire [15:0] dt_i_f; + +wire [15:0] dt_q_0; +wire [15:0] dt_q_1; +wire [15:0] dt_q_2; +wire [15:0] dt_q_3; +wire [15:0] dt_q_4; +wire [15:0] dt_q_5; +wire [15:0] dt_q_6; +wire [15:0] dt_q_7; +wire [15:0] dt_q_8; +wire [15:0] dt_q_9; +wire [15:0] dt_q_a; +wire [15:0] dt_q_b; +wire [15:0] dt_q_c; +wire [15:0] dt_q_d; +wire [15:0] dt_q_e; +wire [15:0] dt_q_f; + + +DUC4 inst_duc_top_i ( + .clkl ( clk ) + ,.rstn ( rstn ) + ,.intp_mode ( intp_mode ) + + ,.din ( din_i ) + + ,.dout_p0 ( dt_i_0 ) + ,.dout_p1 ( dt_i_1 ) + ,.dout_p2 ( dt_i_2 ) + ,.dout_p3 ( dt_i_3 ) + ,.dout_p4 ( dt_i_4 ) + ,.dout_p5 ( dt_i_5 ) + ,.dout_p6 ( dt_i_6 ) + ,.dout_p7 ( dt_i_7 ) + ,.dout_p8 ( dt_i_8 ) + ,.dout_p9 ( dt_i_9 ) + ,.dout_pa ( dt_i_a ) + ,.dout_pb ( dt_i_b ) + ,.dout_pc ( dt_i_c ) + ,.dout_pd ( dt_i_d ) + ,.dout_pe ( dt_i_e ) + ,.dout_pf ( dt_i_f ) + ); + + +DUC4 inst_duc_top_q ( + .clkl ( clk ) + ,.rstn ( rstn ) + ,.intp_mode ( intp_mode ) + + ,.din ( din_q ) + + ,.dout_p0 ( dt_q_0 ) + ,.dout_p1 ( dt_q_1 ) + ,.dout_p2 ( dt_q_2 ) + ,.dout_p3 ( dt_q_3 ) + ,.dout_p4 ( dt_q_4 ) + ,.dout_p5 ( dt_q_5 ) + ,.dout_p6 ( dt_q_6 ) + ,.dout_p7 ( dt_q_7 ) + ,.dout_p8 ( dt_q_8 ) + ,.dout_p9 ( dt_q_9 ) + ,.dout_pa ( dt_q_a ) + ,.dout_pb ( dt_q_b ) + ,.dout_pc ( dt_q_c ) + ,.dout_pd ( dt_q_d ) + ,.dout_pe ( dt_q_e ) + ,.dout_pf ( dt_q_f ) + ); + + +wire [15:0] qam_0; +wire [15:0] qam_1; +wire [15:0] qam_2; +wire [15:0] qam_3; +wire [15:0] qam_4; +wire [15:0] qam_5; +wire [15:0] qam_6; +wire [15:0] qam_7; +wire [15:0] qam_8; +wire [15:0] qam_9; +wire [15:0] qam_a; +wire [15:0] qam_b; +wire [15:0] qam_c; +wire [15:0] qam_d; +wire [15:0] qam_e; +wire [15:0] qam_f; + +QAM_TOP inst_qam_top ( + .clk ( clk ) + ,.rstn ( rstn ) + ,.phase_manual_clr ( phase_manual_clr ) + ,.phase_auto_clr ( phase_auto_clr ) + ,.fcw ( fcw ) + ,.pha ( pha ) + ,.qam_mod ( qam_mod ) + ,.sel_sideband ( sel_sideband ) + ,.din_i_0 ( dt_i_0 ) + ,.din_i_1 ( dt_i_1 ) + ,.din_i_2 ( dt_i_2 ) + ,.din_i_3 ( dt_i_3 ) + ,.din_i_4 ( dt_i_4 ) + ,.din_i_5 ( dt_i_5 ) + ,.din_i_6 ( dt_i_6 ) + ,.din_i_7 ( dt_i_7 ) + ,.din_i_8 ( dt_i_8 ) + ,.din_i_9 ( dt_i_9 ) + ,.din_i_10 ( dt_i_a ) + ,.din_i_11 ( dt_i_b ) + ,.din_i_12 ( dt_i_c ) + ,.din_i_13 ( dt_i_d ) + ,.din_i_14 ( dt_i_e ) + ,.din_i_15 ( dt_i_f ) + ,.din_q_0 ( dt_q_0 ) + ,.din_q_1 ( dt_q_1 ) + ,.din_q_2 ( dt_q_2 ) + ,.din_q_3 ( dt_q_3 ) + ,.din_q_4 ( dt_q_4 ) + ,.din_q_5 ( dt_q_5 ) + ,.din_q_6 ( dt_q_6 ) + ,.din_q_7 ( dt_q_7 ) + ,.din_q_8 ( dt_q_8 ) + ,.din_q_9 ( dt_q_9 ) + ,.din_q_10 ( dt_q_a ) + ,.din_q_11 ( dt_q_b ) + ,.din_q_12 ( dt_q_c ) + ,.din_q_13 ( dt_q_d ) + ,.din_q_14 ( dt_q_e ) + ,.din_q_15 ( dt_q_f ) + ,.dout_i_0 ( qam_0 ) + ,.dout_i_1 ( qam_1 ) + ,.dout_i_2 ( qam_2 ) + ,.dout_i_3 ( qam_3 ) + ,.dout_i_4 ( qam_4 ) + ,.dout_i_5 ( qam_5 ) + ,.dout_i_6 ( qam_6 ) + ,.dout_i_7 ( qam_7 ) + ,.dout_i_8 ( qam_8 ) + ,.dout_i_9 ( qam_9 ) + ,.dout_i_10 ( qam_a ) + ,.dout_i_11 ( qam_b ) + ,.dout_i_12 ( qam_c ) + ,.dout_i_13 ( qam_d ) + ,.dout_i_14 ( qam_e ) + ,.dout_i_15 ( qam_f ) + ); + +dacif dacif_inst ( + .clk ( clk ) + ,.rstn ( rstn ) + ,.dac_mode_sel ( dac_mode_sel ) + ,.intp_mode ( intp_mode ) + ,.din0 ( qam_0 ) + ,.din1 ( qam_1 ) + ,.din2 ( qam_2 ) + ,.din3 ( qam_3 ) + ,.din4 ( qam_4 ) + ,.din5 ( qam_5 ) + ,.din6 ( qam_6 ) + ,.din7 ( qam_7 ) + ,.din8 ( qam_8 ) + ,.din9 ( qam_9 ) + ,.din10 ( qam_a ) + ,.din11 ( qam_b ) + ,.din12 ( qam_c ) + ,.din13 ( qam_d ) + ,.din14 ( qam_e ) + ,.din15 ( qam_f ) + ,.dout0 ( dout0 ) + ,.dout1 ( dout1 ) + ,.dout2 ( dout2 ) + ,.dout3 ( dout3 ) + ,.dout4 ( dout4 ) + ,.dout5 ( dout5 ) + ,.dout6 ( dout6 ) + ,.dout7 ( dout7 ) + ,.dout8 ( dout8 ) + ,.dout9 ( dout9 ) + ,.dout10 ( dout10 ) + ,.dout11 ( dout11 ) + ,.dout12 ( dout12 ) + ,.dout13 ( dout13 ) + ,.dout14 ( dout14 ) + ,.dout15 ( dout15 ) +); + +endmodule diff --git a/rtl/xy_dsp/dsp_top/xy_dsp.v b/rtl/xy_dsp/dsp_top/xy_dsp.v new file mode 100644 index 0000000..0704b07 --- /dev/null +++ b/rtl/xy_dsp/dsp_top/xy_dsp.v @@ -0,0 +1,303 @@ +//+FHDR-------------------------------------------------------------------------------------------------------- +// Company: +//----------------------------------------------------------------------------------------------------------------- +// File Name : XY_dsp.v +// Department : +// Author : PWY +// Author's Tel : +//----------------------------------------------------------------------------------------------------------------- +// Relese History +// Version Date Author Description +// 0.4 2024-03-12 PWY +//----------------------------------------------------------------------------------------------------------------- +// Keywords : +// +//----------------------------------------------------------------------------------------------------------------- +// Parameter +// +//----------------------------------------------------------------------------------------------------------------- +// Purpose : +// +//----------------------------------------------------------------------------------------------------------------- +// Target Device: +// Tool versions: +//----------------------------------------------------------------------------------------------------------------- +// Reuse Issues +// Reset Strategy: +// Clock Domains: +// Critical Timing: +// Asynchronous I/F: +// Synthesizable (y/n): +// Other: +//-FHDR-------------------------------------------------------------------------------------------------------- +module xy_dsp ( + input clk + ,input rstn + ,input phase_manual_clr + ,input phase_auto_clr + + ,input [47:0] fcw + ,input [15:0] pha + ,input [1 :0] qam_mod //2'b00:bypass;2'b01:mix; + //2'b10:cos;2'b11:sin; + ,input sel_sideband //1'b0:Upper sideband;1'b1:Lower sideband; + ,input [2 :0] intp_mode //3'b000:x1;3'b001:x2;3'b010:x4; + //3'b011:x8;3'b100:x16; + ,input [1 :0] dac_mode_sel //2'b00:NRZ mode;2'b01:MIX mode; + //2'b10:2xNRZ mode;2'b00:reserve; + ,input mix_enable + + ,input dsp_alwayson + + ,input [15:0] din_i + + ,input [15:0] din_q + ,input din_vld + //data output + ,output [15:0] dout0 + ,output [15:0] dout1 + ,output [15:0] dout2 + ,output [15:0] dout3 + ,output [15:0] dout4 + ,output [15:0] dout5 + ,output [15:0] dout6 + ,output [15:0] dout7 + ,output [15:0] dout8 + ,output [15:0] dout9 + ,output [15:0] dout10 + ,output [15:0] dout11 + ,output [15:0] dout12 + ,output [15:0] dout13 + ,output [15:0] dout14 + ,output [15:0] dout15 + ,output dout_vld + ); + +wire [15:0] dt_i_0; +wire [15:0] dt_i_1; +wire [15:0] dt_i_2; +wire [15:0] dt_i_3; +wire [15:0] dt_i_4; +wire [15:0] dt_i_5; +wire [15:0] dt_i_6; +wire [15:0] dt_i_7; +wire [15:0] dt_i_8; +wire [15:0] dt_i_9; +wire [15:0] dt_i_a; +wire [15:0] dt_i_b; +wire [15:0] dt_i_c; +wire [15:0] dt_i_d; +wire [15:0] dt_i_e; +wire [15:0] dt_i_f; + +wire [15:0] dt_q_0; +wire [15:0] dt_q_1; +wire [15:0] dt_q_2; +wire [15:0] dt_q_3; +wire [15:0] dt_q_4; +wire [15:0] dt_q_5; +wire [15:0] dt_q_6; +wire [15:0] dt_q_7; +wire [15:0] dt_q_8; +wire [15:0] dt_q_9; +wire [15:0] dt_q_a; +wire [15:0] dt_q_b; +wire [15:0] dt_q_c; +wire [15:0] dt_q_d; +wire [15:0] dt_q_e; +wire [15:0] dt_q_f; + +//DUC valid signal +wire dout_vld_duc_i; +wire dout_vld_duc_q; + +//mix valid signal +wire dout_vld_mix; + + + + +DUC4 inst_duc_top_i ( + .clkl ( clk ) + ,.rstn ( rstn ) + ,.intp_mode ( intp_mode ) + ,.dsp_alwayson ( dsp_alwayson ) + ,.din ( din_i ) + + ,.data_vldi ( din_vld ) + ,.data_vldo ( dout_vld_duc_i ) + + ,.dout_p0 ( dt_i_0 ) + ,.dout_p1 ( dt_i_1 ) + ,.dout_p2 ( dt_i_2 ) + ,.dout_p3 ( dt_i_3 ) + ,.dout_p4 ( dt_i_4 ) + ,.dout_p5 ( dt_i_5 ) + ,.dout_p6 ( dt_i_6 ) + ,.dout_p7 ( dt_i_7 ) + ,.dout_p8 ( dt_i_8 ) + ,.dout_p9 ( dt_i_9 ) + ,.dout_pa ( dt_i_a ) + ,.dout_pb ( dt_i_b ) + ,.dout_pc ( dt_i_c ) + ,.dout_pd ( dt_i_d ) + ,.dout_pe ( dt_i_e ) + ,.dout_pf ( dt_i_f ) + ); + + +DUC4 inst_duc_top_q ( + .clkl ( clk ) + ,.rstn ( rstn ) + ,.intp_mode ( intp_mode ) + ,.dsp_alwayson ( dsp_alwayson ) + ,.din ( din_q ) + + ,.data_vldi ( din_vld ) + ,.data_vldo ( dout_vld_duc_q ) + + ,.dout_p0 ( dt_q_0 ) + ,.dout_p1 ( dt_q_1 ) + ,.dout_p2 ( dt_q_2 ) + ,.dout_p3 ( dt_q_3 ) + ,.dout_p4 ( dt_q_4 ) + ,.dout_p5 ( dt_q_5 ) + ,.dout_p6 ( dt_q_6 ) + ,.dout_p7 ( dt_q_7 ) + ,.dout_p8 ( dt_q_8 ) + ,.dout_p9 ( dt_q_9 ) + ,.dout_pa ( dt_q_a ) + ,.dout_pb ( dt_q_b ) + ,.dout_pc ( dt_q_c ) + ,.dout_pd ( dt_q_d ) + ,.dout_pe ( dt_q_e ) + ,.dout_pf ( dt_q_f ) + ); + + +wire [15:0] qam_0; +wire [15:0] qam_1; +wire [15:0] qam_2; +wire [15:0] qam_3; +wire [15:0] qam_4; +wire [15:0] qam_5; +wire [15:0] qam_6; +wire [15:0] qam_7; +wire [15:0] qam_8; +wire [15:0] qam_9; +wire [15:0] qam_a; +wire [15:0] qam_b; +wire [15:0] qam_c; +wire [15:0] qam_d; +wire [15:0] qam_e; +wire [15:0] qam_f; + +QAM_TOP inst_qam_top ( + .clk ( clk ) + ,.rstn ( rstn ) + ,.phase_manual_clr ( phase_manual_clr ) + ,.phase_auto_clr ( phase_auto_clr ) + ,.fcw ( fcw ) + ,.pha ( pha ) + ,.qam_mod ( qam_mod ) + ,.sel_sideband ( sel_sideband ) + + ,.mix_enable ( mix_enable ) + ,.din_vld ( dout_vld_duc_i & dout_vld_duc_q ) + ,.dout_vld ( dout_vld_mix ) + + ,.din_i_0 ( dt_i_0 ) + ,.din_i_1 ( dt_i_1 ) + ,.din_i_2 ( dt_i_2 ) + ,.din_i_3 ( dt_i_3 ) + ,.din_i_4 ( dt_i_4 ) + ,.din_i_5 ( dt_i_5 ) + ,.din_i_6 ( dt_i_6 ) + ,.din_i_7 ( dt_i_7 ) + ,.din_i_8 ( dt_i_8 ) + ,.din_i_9 ( dt_i_9 ) + ,.din_i_10 ( dt_i_a ) + ,.din_i_11 ( dt_i_b ) + ,.din_i_12 ( dt_i_c ) + ,.din_i_13 ( dt_i_d ) + ,.din_i_14 ( dt_i_e ) + ,.din_i_15 ( dt_i_f ) + ,.din_q_0 ( dt_q_0 ) + ,.din_q_1 ( dt_q_1 ) + ,.din_q_2 ( dt_q_2 ) + ,.din_q_3 ( dt_q_3 ) + ,.din_q_4 ( dt_q_4 ) + ,.din_q_5 ( dt_q_5 ) + ,.din_q_6 ( dt_q_6 ) + ,.din_q_7 ( dt_q_7 ) + ,.din_q_8 ( dt_q_8 ) + ,.din_q_9 ( dt_q_9 ) + ,.din_q_10 ( dt_q_a ) + ,.din_q_11 ( dt_q_b ) + ,.din_q_12 ( dt_q_c ) + ,.din_q_13 ( dt_q_d ) + ,.din_q_14 ( dt_q_e ) + ,.din_q_15 ( dt_q_f ) + ,.dout_i_0 ( qam_0 ) + ,.dout_i_1 ( qam_1 ) + ,.dout_i_2 ( qam_2 ) + ,.dout_i_3 ( qam_3 ) + ,.dout_i_4 ( qam_4 ) + ,.dout_i_5 ( qam_5 ) + ,.dout_i_6 ( qam_6 ) + ,.dout_i_7 ( qam_7 ) + ,.dout_i_8 ( qam_8 ) + ,.dout_i_9 ( qam_9 ) + ,.dout_i_10 ( qam_a ) + ,.dout_i_11 ( qam_b ) + ,.dout_i_12 ( qam_c ) + ,.dout_i_13 ( qam_d ) + ,.dout_i_14 ( qam_e ) + ,.dout_i_15 ( qam_f ) + ); + +dacif dacif_inst ( + .clk ( clk ) + ,.rstn ( rstn ) + ,.dac_mode_sel ( dac_mode_sel ) + ,.intp_mode ( intp_mode ) + + ,.din_vld ( dout_vld_mix ) + ,.dout_vld ( dout_vld ) + + ,.din0 ( qam_0 ) + ,.din1 ( qam_1 ) + ,.din2 ( qam_2 ) + ,.din3 ( qam_3 ) + ,.din4 ( qam_4 ) + ,.din5 ( qam_5 ) + ,.din6 ( qam_6 ) + ,.din7 ( qam_7 ) + ,.din8 ( qam_8 ) + ,.din9 ( qam_9 ) + ,.din10 ( qam_a ) + ,.din11 ( qam_b ) + ,.din12 ( qam_c ) + ,.din13 ( qam_d ) + ,.din14 ( qam_e ) + ,.din15 ( qam_f ) + ,.dout0 ( dout0 ) + ,.dout1 ( dout1 ) + ,.dout2 ( dout2 ) + ,.dout3 ( dout3 ) + ,.dout4 ( dout4 ) + ,.dout5 ( dout5 ) + ,.dout6 ( dout6 ) + ,.dout7 ( dout7 ) + ,.dout8 ( dout8 ) + ,.dout9 ( dout9 ) + ,.dout10 ( dout10 ) + ,.dout11 ( dout11 ) + ,.dout12 ( dout12 ) + ,.dout13 ( dout13 ) + ,.dout14 ( dout14 ) + ,.dout15 ( dout15 ) +); + + +endmodule diff --git a/rtl/xy_dsp/duc/duc4.v b/rtl/xy_dsp/duc/duc4.v new file mode 100644 index 0000000..659a52f --- /dev/null +++ b/rtl/xy_dsp/duc/duc4.v @@ -0,0 +1,321 @@ +module DUC4( + input clkl + ,input rstn + ,input [2 :0] intp_mode //3'b000:x1;3'b001:x2;3'b010:x4;3'b011:x8;3'b100:x16; + ,input dsp_alwayson + ,input data_vldi + ,input [15:0] din + ,output [15:0] dout_p0 + ,output [15:0] dout_p1 + ,output [15:0] dout_p2 + ,output [15:0] dout_p3 + ,output [15:0] dout_p4 + ,output [15:0] dout_p5 + ,output [15:0] dout_p6 + ,output [15:0] dout_p7 + ,output [15:0] dout_p8 + ,output [15:0] dout_p9 + ,output [15:0] dout_pa + ,output [15:0] dout_pb + ,output [15:0] dout_pc + ,output [15:0] dout_pd + ,output [15:0] dout_pe + ,output [15:0] dout_pf + ,output data_vldo +); + +wire [15:0] dt1_p_0; +wire [15:0] dt1_p_1; + +wire [15:0] dt2_p_0; +wire [15:0] dt2_p_1; +wire [15:0] dt2_p_2; +wire [15:0] dt2_p_3; + +wire [15:0] dt3_p_0; +wire [15:0] dt3_p_1; +wire [15:0] dt3_p_2; +wire [15:0] dt3_p_3; +wire [15:0] dt3_p_4; +wire [15:0] dt3_p_5; +wire [15:0] dt3_p_6; +wire [15:0] dt3_p_7; + +wire [15:0] dt4_p_0; +wire [15:0] dt4_p_1; +wire [15:0] dt4_p_2; +wire [15:0] dt4_p_3; +wire [15:0] dt4_p_4; +wire [15:0] dt4_p_5; +wire [15:0] dt4_p_6; +wire [15:0] dt4_p_7; +wire [15:0] dt4_p_8; +wire [15:0] dt4_p_9; +wire [15:0] dt4_p_a; +wire [15:0] dt4_p_b; +wire [15:0] dt4_p_c; +wire [15:0] dt4_p_d; +wire [15:0] dt4_p_e; +wire [15:0] dt4_p_f; + +reg [15:0] mux_p_0; +reg [15:0] mux_p_1; +reg [15:0] mux_p_2; +reg [15:0] mux_p_3; +reg [15:0] mux_p_4; +reg [15:0] mux_p_5; +reg [15:0] mux_p_6; +reg [15:0] mux_p_7; +reg [15:0] mux_p_8; +reg [15:0] mux_p_9; +reg [15:0] mux_p_a; +reg [15:0] mux_p_b; +reg [15:0] mux_p_c; +reg [15:0] mux_p_d; +reg [15:0] mux_p_e; +reg [15:0] mux_p_f; + +reg [70:0] DUC4_data_vld_r; + +always@(posedge clkl or negedge rstn) + if(!rstn) + begin + DUC4_data_vld_r <= 9'b0; + end + else + begin + DUC4_data_vld_r <= {DUC4_data_vld_r[70:0], data_vldi}; + end + +/////////////////////////////////////////////////////// +//DUC_HB1_TOP inst +/////////////////////////////////////////////////////// +DUC_HB1_TOP U0_DUC_HB1_TOP ( + .clkl ( clkl ) + ,.rstn ( rstn ) + ,.din ( din ) + ,.dout_p0 ( dt1_p_0 ) + ,.dout_p1 ( dt1_p_1 ) + ); + + +/////////////////////////////////////////////////////// +//DUC_HB2_TOP_S inst1 +/////////////////////////////////////////////////////// + +DUC_HB2_TOP_S U1_DUC_HB2_TOP ( + .clkl ( clkl ) + ,.rstn ( rstn ) + ,.din0 ( dt1_p_1 ) + ,.din1 ( dt1_p_0 ) + ,.dout_p0 ( dt2_p_0 ) + ,.dout_p1 ( dt2_p_1 ) + ,.dout_p2 ( dt2_p_2 ) + ,.dout_p3 ( dt2_p_3 ) + ); + +/////////////////////////////////////////////////////// +//DUC_HB3_TOP_S2 inst1 +/////////////////////////////////////////////////////// + +DUC_HB3_TOP_S2 U1_DUC_HB3_TOP ( + .clkl ( clkl ) + ,.rstn ( rstn ) + ,.din0 ( dt2_p_2 ) + ,.din1 ( dt2_p_3 ) + ,.din2 ( dt2_p_0 ) + ,.din3 ( dt2_p_1 ) + ,.dout_p0 ( dt3_p_0 ) + ,.dout_p1 ( dt3_p_1 ) + ,.dout_p2 ( dt3_p_2 ) + ,.dout_p3 ( dt3_p_3 ) + ,.dout_p4 ( dt3_p_4 ) + ,.dout_p5 ( dt3_p_5 ) + ,.dout_p6 ( dt3_p_6 ) + ,.dout_p7 ( dt3_p_7 ) + ); + +/////////////////////////////////////////////////////// +//DUC_HB4_TOP_S3 inst1 +/////////////////////////////////////////////////////// + +DUC_HB4_TOP_S3 U1_DUC_HB4_TOP ( + .clkl ( clkl ) + ,.rstn ( rstn ) + ,.din0 ( dt3_p_6 ) + ,.din1 ( dt3_p_7 ) + ,.din2 ( dt3_p_4 ) + ,.din3 ( dt3_p_5 ) + ,.din4 ( dt3_p_2 ) + ,.din5 ( dt3_p_3 ) + ,.din6 ( dt3_p_0 ) + ,.din7 ( dt3_p_1 ) + ,.dout_p0 ( dt4_p_0 ) + ,.dout_p1 ( dt4_p_1 ) + ,.dout_p2 ( dt4_p_2 ) + ,.dout_p3 ( dt4_p_3 ) + ,.dout_p4 ( dt4_p_4 ) + ,.dout_p5 ( dt4_p_5 ) + ,.dout_p6 ( dt4_p_6 ) + ,.dout_p7 ( dt4_p_7 ) + ,.dout_p8 ( dt4_p_8 ) + ,.dout_p9 ( dt4_p_9 ) + ,.dout_pa ( dt4_p_a ) + ,.dout_pb ( dt4_p_b ) + ,.dout_pc ( dt4_p_c ) + ,.dout_pd ( dt4_p_d ) + ,.dout_pe ( dt4_p_e ) + ,.dout_pf ( dt4_p_f ) + ); + +always@(posedge clkl) begin + case(intp_mode) + 3'b000 : begin + mux_p_0 <= din; + mux_p_1 <= 16'h0; + mux_p_2 <= 16'h0; + mux_p_3 <= 16'h0; + mux_p_4 <= 16'h0; + mux_p_5 <= 16'h0; + mux_p_6 <= 16'h0; + mux_p_7 <= 16'h0; + mux_p_8 <= 16'h0; + mux_p_9 <= 16'h0; + mux_p_a <= 16'h0; + mux_p_b <= 16'h0; + mux_p_c <= 16'h0; + mux_p_d <= 16'h0; + mux_p_e <= 16'h0; + mux_p_f <= 16'h0; + end + 3'b001 : begin + mux_p_0 <= dt1_p_0; + mux_p_1 <= 16'h0; + mux_p_2 <= 16'h0; + mux_p_3 <= 16'h0; + mux_p_4 <= 16'h0; + mux_p_5 <= 16'h0; + mux_p_6 <= 16'h0; + mux_p_7 <= 16'h0; + mux_p_8 <= dt1_p_1; + mux_p_9 <= 16'h0; + mux_p_a <= 16'h0; + mux_p_b <= 16'h0; + mux_p_c <= 16'h0; + mux_p_d <= 16'h0; + mux_p_e <= 16'h0; + mux_p_f <= 16'h0; + end + 3'b010 : begin + mux_p_0 <= dt2_p_1; + mux_p_1 <= 16'h0; + mux_p_2 <= 16'h0; + mux_p_3 <= 16'h0; + mux_p_4 <= dt2_p_0; + mux_p_5 <= 16'h0; + mux_p_6 <= 16'h0; + mux_p_7 <= 16'h0; + mux_p_8 <= dt2_p_3; + mux_p_9 <= 16'h0; + mux_p_a <= 16'h0; + mux_p_b <= 16'h0; + mux_p_c <= dt2_p_2; + mux_p_d <= 16'h0; + mux_p_e <= 16'h0; + mux_p_f <= 16'h0; + end + 3'b011 : begin + mux_p_0 <= dt3_p_1; + mux_p_1 <= 16'h0; + mux_p_2 <= dt3_p_0; + mux_p_3 <= 16'h0; + mux_p_4 <= dt3_p_3; + mux_p_5 <= 16'h0; + mux_p_6 <= dt3_p_2; + mux_p_7 <= 16'h0; + mux_p_8 <= dt3_p_5; + mux_p_9 <= 16'h0; + mux_p_a <= dt3_p_4; + mux_p_b <= 16'h0; + mux_p_c <= dt3_p_7; + mux_p_d <= 16'h0; + mux_p_e <= dt3_p_6; + mux_p_f <= 16'h0; + end + 3'b100 : begin + mux_p_0 <= dt4_p_1; + mux_p_1 <= dt4_p_0; + mux_p_2 <= dt4_p_3; + mux_p_3 <= dt4_p_2; + mux_p_4 <= dt4_p_5; + mux_p_5 <= dt4_p_4; + mux_p_6 <= dt4_p_7; + mux_p_7 <= dt4_p_6; + mux_p_8 <= dt4_p_9; + mux_p_9 <= dt4_p_8; + mux_p_a <= dt4_p_b; + mux_p_b <= dt4_p_a; + mux_p_c <= dt4_p_d; + mux_p_d <= dt4_p_c; + mux_p_e <= dt4_p_f; + mux_p_f <= dt4_p_e; + end + default : begin + mux_p_0 <= 16'h0; + mux_p_1 <= 16'h0; + mux_p_2 <= 16'h0; + mux_p_3 <= 16'h0; + mux_p_4 <= 16'h0; + mux_p_5 <= 16'h0; + mux_p_6 <= 16'h0; + mux_p_7 <= 16'h0; + mux_p_8 <= 16'h0; + mux_p_9 <= 16'h0; + mux_p_a <= 16'h0; + mux_p_b <= 16'h0; + mux_p_c <= 16'h0; + mux_p_d <= 16'h0; + mux_p_e <= 16'h0; + mux_p_f <= 16'h0; + end + endcase +end + +assign dout_p0 = mux_p_f ; +assign dout_p1 = mux_p_e ; +assign dout_p2 = mux_p_d ; +assign dout_p3 = mux_p_c ; +assign dout_p4 = mux_p_b ; +assign dout_p5 = mux_p_a ; +assign dout_p6 = mux_p_9 ; +assign dout_p7 = mux_p_8 ; +assign dout_p8 = mux_p_7 ; +assign dout_p9 = mux_p_6 ; +assign dout_pa = mux_p_5 ; +assign dout_pb = mux_p_4 ; +assign dout_pc = mux_p_3 ; +assign dout_pd = mux_p_2 ; +assign dout_pe = mux_p_1 ; +assign dout_pf = mux_p_0 ; + +reg data_vldo_t; + +always@(posedge clkl) begin + if(dsp_alwayson) begin + data_vldo_t <= 1'b1; + end + else begin + case(intp_mode) + 3'b000 : data_vldo_t <= data_vldi; + 3'b001 : data_vldo_t <= DUC4_data_vld_r[21]; + 3'b010 : data_vldo_t <= DUC4_data_vld_r[28]; + 3'b011 : data_vldo_t <= DUC4_data_vld_r[33]; + 3'b100 : data_vldo_t <= DUC4_data_vld_r[37]; + default : data_vldo_t <= data_vldi; + endcase + end +end + +assign data_vldo = data_vldo_t; + +endmodule diff --git a/rtl/xy_dsp/duc/duc_hb1_pipe_shift.v b/rtl/xy_dsp/duc/duc_hb1_pipe_shift.v new file mode 100644 index 0000000..06d0dd3 --- /dev/null +++ b/rtl/xy_dsp/duc/duc_hb1_pipe_shift.v @@ -0,0 +1,595 @@ +//+FHDR-------------------------------------------------------------------------------------------------------- +// Company: +//----------------------------------------------------------------------------------------------------------------- +// File Name : duc_hb1_shift.v +// Department : +// Author : +// Author's Tel : +//----------------------------------------------------------------------------------------------------------------- +// Relese History +// Version Date Author Description +// 0.8 2024-03-26 thfu add pipeline +//----------------------------------------------------------------------------------------------------------------- +// Keywords : +// +//----------------------------------------------------------------------------------------------------------------- +// Parameter +// +//----------------------------------------------------------------------------------------------------------------- +// Purpose : +// +//----------------------------------------------------------------------------------------------------------------- +// Target Device: +// Tool versions: +//----------------------------------------------------------------------------------------------------------------- +// Reuse Issues +// Reset Strategy: +// Clock Domains: +// Critical Timing: +// Asynchronous I/F: +// Synthesizable (y/n): +// Other: +//-FHDR-------------------------------------------------------------------------------------------------------- + +module DUC_HB1 ( + clk, + rstn, + din_0, + din_1, + din_2, + din_3, + din_4, + din_5, + din_6, + din_7, + din_8, + din_9, + din_10, + din_11, + din_12, + din_13, + din_14, + din_15, + din_16, + din_17, + din_18, + din_19, + din_20, + din_21, + din_22, + din_23, + din_24, + din_25, + din_26, + din_27, + din_28, + din_29, + din_30, + din_31, + din_32, + din_33, + din_34, + din_35, + dout + ); +input clk; +input rstn; +input signed [15:0] din_0; +input signed [15:0] din_1; +input signed [15:0] din_2; +input signed [15:0] din_3; +input signed [15:0] din_4; +input signed [15:0] din_5; +input signed [15:0] din_6; +input signed [15:0] din_7; +input signed [15:0] din_8; +input signed [15:0] din_9; +input signed [15:0] din_10; +input signed [15:0] din_11; +input signed [15:0] din_12; +input signed [15:0] din_13; +input signed [15:0] din_14; +input signed [15:0] din_15; +input signed [15:0] din_16; +input signed [15:0] din_17; +input signed [15:0] din_18; +input signed [15:0] din_19; +input signed [15:0] din_20; +input signed [15:0] din_21; +input signed [15:0] din_22; +input signed [15:0] din_23; +input signed [15:0] din_24; +input signed [15:0] din_25; +input signed [15:0] din_26; +input signed [15:0] din_27; +input signed [15:0] din_28; +input signed [15:0] din_29; +input signed [15:0] din_30; +input signed [15:0] din_31; +input signed [15:0] din_32; +input signed [15:0] din_33; +input signed [15:0] din_34; +input signed [15:0] din_35; + + +output signed [15:0] dout; + +parameter c0 = -20'd28; +parameter c1 = 20'd82; +parameter c2 = -20'd194; +parameter c3 = 20'd397; +parameter c4 = -20'd737; +parameter c5 = 20'd1275; +parameter c6 = -20'd2084; +parameter c7 = 20'd3258; +parameter c8 = -20'd4910; +parameter c9 = 20'd7184; +parameter c10 = -20'd10274; +parameter c11 = 20'd14457; +parameter c12 = -20'd20187; +parameter c13 = 20'd28286; +parameter c14 = -20'd40513; +parameter c15 = 20'd61451; +parameter c16 = -20'd108000; +parameter c17 = 20'd332673; + +reg signed [16:0] sum_0_35; +reg signed [16:0] sum_1_34; +reg signed [16:0] sum_2_33; +reg signed [16:0] sum_3_32; +reg signed [16:0] sum_4_31; +reg signed [16:0] sum_5_30; +reg signed [16:0] sum_6_29; +reg signed [16:0] sum_7_28; +reg signed [16:0] sum_8_27; +reg signed [16:0] sum_9_26; +reg signed [16:0] sum_10_25; +reg signed [16:0] sum_11_24; +reg signed [16:0] sum_12_23; +reg signed [16:0] sum_13_22; +reg signed [16:0] sum_14_21; +reg signed [16:0] sum_15_20; +reg signed [16:0] sum_16_19; +reg signed [16:0] sum_17_18; + +always@(posedge clk or negedge rstn) begin + if(!rstn) begin + sum_0_35 <= 'h0; + sum_1_34 <= 'h0; + sum_2_33 <= 'h0; + sum_3_32 <= 'h0; + sum_4_31 <= 'h0; + sum_5_30 <= 'h0; + sum_6_29 <= 'h0; + sum_7_28 <= 'h0; + sum_8_27 <= 'h0; + sum_9_26 <= 'h0; + sum_10_25 <= 'h0; + sum_11_24 <= 'h0; + sum_12_23 <= 'h0; + sum_13_22 <= 'h0; + sum_14_21 <= 'h0; + sum_15_20 <= 'h0; + sum_16_19 <= 'h0; + sum_17_18 <= 'h0; + end + else begin + sum_0_35 <= {{1 {din_0[15]}},din_0} + {{1 {din_35[15]}},din_35}; + sum_1_34 <= {{1 {din_1[15]}},din_1} + {{1 {din_34[15]}},din_34}; + sum_2_33 <= {{1 {din_2[15]}},din_2} + {{1 {din_33[15]}},din_33}; + sum_3_32 <= {{1 {din_3[15]}},din_3} + {{1 {din_32[15]}},din_32}; + sum_4_31 <= {{1 {din_4[15]}},din_4} + {{1 {din_31[15]}},din_31}; + sum_5_30 <= {{1 {din_5[15]}},din_5} + {{1 {din_30[15]}},din_30}; + sum_6_29 <= {{1 {din_6[15]}},din_6} + {{1 {din_29[15]}},din_29}; + sum_7_28 <= {{1 {din_7[15]}},din_7} + {{1 {din_28[15]}},din_28}; + sum_8_27 <= {{1 {din_8[15]}},din_8} + {{1 {din_27[15]}},din_27}; + sum_9_26 <= {{1 {din_9[15]}},din_9} + {{1 {din_26[15]}},din_26}; + sum_10_25 <= {{1 {din_10[15]}},din_10} + {{1 {din_25[15]}},din_25}; + sum_11_24 <= {{1 {din_11[15]}},din_11} + {{1 {din_24[15]}},din_24}; + sum_12_23 <= {{1 {din_12[15]}},din_12} + {{1 {din_23[15]}},din_23}; + sum_13_22 <= {{1 {din_13[15]}},din_13} + {{1 {din_22[15]}},din_22}; + sum_14_21 <= {{1 {din_14[15]}},din_14} + {{1 {din_21[15]}},din_21}; + sum_15_20 <= {{1 {din_15[15]}},din_15} + {{1 {din_20[15]}},din_20}; + sum_16_19 <= {{1 {din_16[15]}},din_16} + {{1 {din_19[15]}},din_19}; + sum_17_18 <= {{1 {din_17[15]}},din_17} + {{1 {din_18[15]}},din_18}; + end +end + +wire signed [17:0] mult_c0_sum0; + +assign mult_c0_sum0 = {sum_0_35,1'b0}; + +reg signed [17:0] mult_c0_sum; + +always@(posedge clk or negedge rstn) begin + if(!rstn) + mult_c0_sum <= 'h0; + else + mult_c0_sum <= mult_c0_sum0; +end + +wire signed [16:0] mult_c1_sum0; +wire signed [18:0] mult_c1_sum1; + +assign mult_c1_sum0 = sum_1_34; +assign mult_c1_sum1 = {sum_1_34,2'b0}; + +reg signed [19:0] mult_c1_sum; + +always@(posedge clk or negedge rstn) + if(!rstn) + mult_c1_sum <= 'h0; + else + mult_c1_sum <= {{3{mult_c1_sum0[16]}},mult_c1_sum0} + {{1{mult_c1_sum1[18]}},mult_c1_sum1}; + + +wire signed [18:0] mult_c2_sum0; +wire signed [19:0] mult_c2_sum1; + +assign mult_c2_sum0 = {sum_2_33,2'b0}; +assign mult_c2_sum1 = {sum_2_33,3'b0}; + +reg signed [20:0] mult_c2_sum; + +always@(posedge clk or negedge rstn) + if(!rstn) + mult_c2_sum <= 'h0; + else + mult_c2_sum <= {{2{mult_c2_sum0[18]}},mult_c2_sum0} + {{1{mult_c2_sum1[19]}},mult_c2_sum1}; + + +wire signed [16:0] mult_c3_sum0; +wire signed [19:0] mult_c3_sum1; +wire signed [20:0] mult_c3_sum2; + +assign mult_c3_sum0 = sum_3_32; +assign mult_c3_sum1 = {sum_3_32,3'b0}; +assign mult_c3_sum2 = {sum_3_32,4'b0}; + +reg signed [21:0] mult_c3_sum; + +always@(posedge clk or negedge rstn) + if(!rstn) + mult_c3_sum <= 'h0; + else + mult_c3_sum <= {{5{mult_c3_sum0[16]}},mult_c3_sum0} + {{2{mult_c3_sum1[19]}},mult_c3_sum1} + {{1{mult_c3_sum2[20]}},mult_c3_sum2}; + + + +wire signed [17:0] mult_c4_sum0; +wire signed [20:0] mult_c4_sum1; +wire signed [21:0] mult_c4_sum2; + +assign mult_c4_sum0 = {sum_4_31,1'b0}; +assign mult_c4_sum1 = {sum_4_31,4'b0}; +assign mult_c4_sum2 = {sum_4_31,5'b0}; + +reg signed [22:0] mult_c4_sum; + +always@(posedge clk or negedge rstn) + if(!rstn) + mult_c4_sum <= 'h0; + else + mult_c4_sum <= - {{5{mult_c4_sum0[17]}},mult_c4_sum0} + {{2{mult_c4_sum1[20]}},mult_c4_sum1} + {{1{mult_c4_sum2[21]}},mult_c4_sum2}; + + + +wire signed [20:0] mult_c5_sum0; +wire signed [21:0] mult_c5_sum1; +wire signed [23:0] mult_c5_sum2; + +assign mult_c5_sum0 = {sum_5_30,4'b0}; +assign mult_c5_sum1 = {sum_5_30,5'b0}; +assign mult_c5_sum2 = {sum_5_30,7'b0}; + +reg signed [24:0] mult_c5_sum; + +always@(posedge clk or negedge rstn) + if(!rstn) + mult_c5_sum <= 'h0; + else + mult_c5_sum <= -{{4{mult_c5_sum0[20]}},mult_c5_sum0} - {{3{mult_c5_sum1[21]}},mult_c5_sum1} + {{1{mult_c5_sum2[23]}},mult_c5_sum2}; + + + + +wire signed [17:0] mult_c6_sum0; +wire signed [23:0] mult_c6_sum1; + +assign mult_c6_sum0 = {sum_6_29,1'b0}; +assign mult_c6_sum1 = {sum_6_29,7'b0}; + +reg signed [24:0] mult_c6_sum; + +always@(posedge clk or negedge rstn) + if(!rstn) + mult_c6_sum <= 'h0; + else + mult_c6_sum <= {{7{mult_c6_sum0[17]}},mult_c6_sum0} + {{1{mult_c6_sum1[23]}},mult_c6_sum1}; + + + +wire signed [18:0] mult_c7_sum0; +wire signed [20:0] mult_c7_sum1; +wire signed [21:0] mult_c7_sum2; +wire signed [24:0] mult_c7_sum3; + +assign mult_c7_sum0 = {sum_7_28,2'b0}; +assign mult_c7_sum1 = {sum_7_28,4'b0}; +assign mult_c7_sum2 = {sum_7_28,5'b0}; +assign mult_c7_sum3 = {sum_7_28,8'b0}; + +reg signed [25:0] mult_c7_sum; + +always@(posedge clk or negedge rstn) + if(!rstn) + mult_c7_sum <= 'h0; + else + mult_c7_sum <= -{{7{mult_c7_sum0[18]}},mult_c7_sum0} - {{5{mult_c7_sum1[20]}},mult_c7_sum1} - {{4{mult_c7_sum2[21]}},mult_c7_sum2} + {{1{mult_c7_sum3[24]}},mult_c7_sum3}; + + + +wire signed [16:0] mult_c8_sum0; +wire signed [17:0] mult_c8_sum1; +wire signed [20:0] mult_c8_sum2; +wire signed [21:0] mult_c8_sum3; +wire signed [24:0] mult_c8_sum4; + +assign mult_c8_sum0 = sum_8_27; +assign mult_c8_sum1 = {sum_8_27,1'b0}; +assign mult_c8_sum2 = {sum_8_27,4'b0}; +assign mult_c8_sum3 = {sum_8_27,5'b0}; +assign mult_c8_sum4 = {sum_8_27,8'b0}; + +reg signed [25:0] mult_c8_sum; + +always@(posedge clk or negedge rstn) + if(!rstn) + mult_c8_sum <= 'h0; + else + mult_c8_sum <= {{9{mult_c8_sum0[16]}},mult_c8_sum0} + {{8{mult_c8_sum1[17]}},mult_c8_sum1} + {{5{mult_c8_sum2[20]}},mult_c8_sum2} + {{4{mult_c8_sum3[21]}},mult_c8_sum3} + {{1{mult_c8_sum4[24]}},mult_c8_sum4}; + + + +wire signed [16:0] mult_c9_sum0; +wire signed [22:0] mult_c9_sum1; +wire signed [25:0] mult_c9_sum2; + +assign mult_c9_sum0 = sum_9_26; +assign mult_c9_sum1 = {sum_9_26,6'b0}; +assign mult_c9_sum2 = {sum_9_26,9'b0}; + +reg signed [26:0] mult_c9_sum; + +always@(posedge clk or negedge rstn) + if(!rstn) + mult_c9_sum <= 'h0; + else + mult_c9_sum <= {{10{mult_c9_sum0[16]}},mult_c9_sum0} - {{4{mult_c9_sum1[22]}},mult_c9_sum1} + {{1{mult_c9_sum2[25]}},mult_c9_sum2}; + + + + +wire signed [17:0] mult_c10_sum0; +wire signed [23:0] mult_c10_sum1; +wire signed [25:0] mult_c10_sum2; + +assign mult_c10_sum0 = {sum_10_25,1'b0}; +assign mult_c10_sum1 = {sum_10_25,7'b0}; +assign mult_c10_sum2 = {sum_10_25,9'b0}; + +reg signed [26:0] mult_c10_sum; + +always@(posedge clk or negedge rstn) + if(!rstn) + mult_c10_sum <= 'h0; + else + mult_c10_sum <= {{9{mult_c10_sum0[17]}},mult_c10_sum0} + {{3{mult_c10_sum1[23]}},mult_c10_sum1} + {{1{mult_c10_sum2[25]}},mult_c10_sum2}; + + + +wire signed [19:0] mult_c11_sum0; +wire signed [23:0] mult_c11_sum1; +wire signed [26:0] mult_c11_sum2; + +assign mult_c11_sum0 = {sum_11_24,3'b0}; +assign mult_c11_sum1 = {sum_11_24,7'b0}; +assign mult_c11_sum2 = {sum_11_24,10'b0}; + +reg signed [27:0] mult_c11_sum; + +always@(posedge clk or negedge rstn) + if(!rstn) + mult_c11_sum <= 'h0; + else + mult_c11_sum <= {{8{mult_c11_sum0[19]}},mult_c11_sum0} - {{4{mult_c11_sum1[23]}},mult_c11_sum1} + {{1{mult_c11_sum2[26]}},mult_c11_sum2}; + + + +wire signed [17:0] mult_c12_sum0; +wire signed [20:0] mult_c12_sum1; +wire signed [24:0] mult_c12_sum2; +wire signed [25:0] mult_c12_sum3; +wire signed [27:0] mult_c12_sum4; + +assign mult_c12_sum0 = {sum_12_23,1'b0}; +assign mult_c12_sum1 = {sum_12_23,4'b0}; +assign mult_c12_sum2 = {sum_12_23,8'b0}; +assign mult_c12_sum3 = {sum_12_23,9'b0}; +assign mult_c12_sum4 = {sum_12_23,11'b0}; + +reg signed [28:0] mult_c12_sum; + +always@(posedge clk or negedge rstn) + if(!rstn) + mult_c12_sum <= 'h0; + else + mult_c12_sum <= - {{11{mult_c12_sum0[17]}},mult_c12_sum0} - {{8{mult_c12_sum1[20]}},mult_c12_sum1} - {{4{mult_c12_sum2[24]}},mult_c12_sum2} - {{3{mult_c12_sum3[25]}},mult_c12_sum3} + {{1{mult_c12_sum4[27]}},mult_c12_sum4}; + + + +wire signed [19:0] mult_c13_sum0; +wire signed [20:0] mult_c13_sum1; +wire signed [24:0] mult_c13_sum2; +wire signed [27:0] mult_c13_sum3; + +assign mult_c13_sum0 = {sum_13_22,3'b0}; +assign mult_c13_sum1 = {sum_13_22,4'b0}; +assign mult_c13_sum2 = {sum_13_22,8'b0}; +assign mult_c13_sum3 = {sum_13_22,11'b0}; + +reg signed [28:0] mult_c13_sum; + +always@(posedge clk or negedge rstn) + if(!rstn) + mult_c13_sum <= 'h0; + else + mult_c13_sum <= - {{9{mult_c13_sum0[19]}},mult_c13_sum0} - {{8{mult_c13_sum1[20]}},mult_c13_sum1} - {{4{mult_c13_sum2[24]}},mult_c13_sum2} + {{1{mult_c13_sum3[27]}},mult_c13_sum3}; + + + +wire signed [18:0] mult_c14_sum0; +wire signed [21:0] mult_c14_sum1; +wire signed [25:0] mult_c14_sum2; +wire signed [27:0] mult_c14_sum3; + +assign mult_c14_sum0 = {sum_14_21,2'b0}; +assign mult_c14_sum1 = {sum_14_21,5'b0}; +assign mult_c14_sum2 = {sum_14_21,9'b0}; +assign mult_c14_sum3 = {sum_14_21,11'b0}; + +reg signed [28:0] mult_c14_sum; + +always@(posedge clk or negedge rstn) + if(!rstn) + mult_c14_sum <= 'h0; + else + mult_c14_sum <= {{10{mult_c14_sum0[18]}},mult_c14_sum0} - {{7{mult_c14_sum1[21]}},mult_c14_sum1} + {{3{mult_c14_sum2[25]}},mult_c14_sum2} + {{1{mult_c14_sum3[27]}},mult_c14_sum3}; + + + +wire signed [16:0] mult_c15_sum0; +wire signed [24:0] mult_c15_sum1; +wire signed [28:0] mult_c15_sum2; + +assign mult_c15_sum0 = sum_15_20; +assign mult_c15_sum1 = {sum_15_20,8'b0}; +assign mult_c15_sum2 = {sum_15_20,12'b0}; + +reg signed [29:0] mult_c15_sum; + +always@(posedge clk or negedge rstn) + if(!rstn) + mult_c15_sum <= 'h0; + else + mult_c15_sum <= {{13{mult_c15_sum0[16]}},mult_c15_sum0} - {{5{mult_c15_sum1[24]}},mult_c15_sum1} + {{1{mult_c15_sum2[28]}},mult_c15_sum2}; + + + +wire signed [17:0] mult_c16_sum0; +wire signed [21:0] mult_c16_sum1; +wire signed [22:0] mult_c16_sum2; +wire signed [25:0] mult_c16_sum3; +wire signed [27:0] mult_c16_sum4; +wire signed [28:0] mult_c16_sum5; + +assign mult_c16_sum0 = {sum_16_19,1'b0}; +assign mult_c16_sum1 = {sum_16_19,5'b0}; +assign mult_c16_sum2 = {sum_16_19,6'b0}; +assign mult_c16_sum3 = {sum_16_19,9'b0}; +assign mult_c16_sum4 = {sum_16_19,11'b0}; +assign mult_c16_sum5 = {sum_16_19,12'b0}; + +reg signed [29:0] mult_c16_sum; + +always@(posedge clk or negedge rstn) + if(!rstn) + mult_c16_sum <= 'h0; + else + mult_c16_sum <= -{{12{mult_c16_sum0[17]}},mult_c16_sum0} + {{8{mult_c16_sum1[21]}},mult_c16_sum1} + {{7{mult_c16_sum2[22]}},mult_c16_sum2} + {{4{mult_c16_sum3[25]}},mult_c16_sum3} + {{2{mult_c16_sum4[27]}},mult_c16_sum4} + {{1{mult_c16_sum5[28]}},mult_c16_sum5}; + + + +wire signed [19:0] mult_c17_sum0; +wire signed [22:0] mult_c17_sum1; +wire signed [24:0] mult_c17_sum2; +wire signed [28:0] mult_c17_sum3; +wire signed [30:0] mult_c17_sum4; + +assign mult_c17_sum0 = {sum_17_18,3'b0}; +assign mult_c17_sum1 = {sum_17_18,6'b0}; +assign mult_c17_sum2 = {sum_17_18,8'b0}; +assign mult_c17_sum3 = {sum_17_18,12'b0}; +assign mult_c17_sum4 = {sum_17_18,14'b0}; + +reg signed [31:0] mult_c17_sum; + +always@(posedge clk or negedge rstn) + if(!rstn) + mult_c17_sum <= 'h0; + else + mult_c17_sum <= - {{12{mult_c17_sum0[19]}},mult_c17_sum0} + {{9{mult_c17_sum1[22]}},mult_c17_sum1} + {{7{mult_c17_sum2[24]}},mult_c17_sum2} + {{3{mult_c17_sum3[28]}},mult_c17_sum3} + {{1{mult_c17_sum4[30]}},mult_c17_sum4}; + + + +reg signed [22:0] mult_sum_r1; +reg signed [27:0] mult_sum_r2; +reg signed [30:0] mult_sum_r3; +reg signed [32:0] mult_sum_r4; + +always@(posedge clk or negedge rstn) + if(!rstn) + mult_sum_r1 <= 'h0; + else + mult_sum_r1 <= -{{5{mult_c0_sum[17]}},mult_c0_sum} + {{3{mult_c1_sum[19]}},mult_c1_sum} - {{2{mult_c2_sum[20]}},mult_c2_sum} + {{1{mult_c3_sum[21]}},mult_c3_sum}; + +always@(posedge clk or negedge rstn) + if(!rstn) + mult_sum_r2 <= 'h0; + else + mult_sum_r2 <= -{{5{mult_c4_sum[22]}},mult_c4_sum} + {{3{mult_c5_sum[24]}},mult_c5_sum} - {{3{mult_c6_sum[24]}},mult_c6_sum} + {{2{mult_c7_sum[25]}},mult_c7_sum}; + +always@(posedge clk or negedge rstn) + if(!rstn) + mult_sum_r3 <= 'h0; + else + mult_sum_r3 <= -{{5{mult_c8_sum[25]}},mult_c8_sum} + {{4{mult_c9_sum[26]}},mult_c9_sum} - {{4{mult_c10_sum[26]}},mult_c10_sum} + {{3{mult_c11_sum[27]}},mult_c11_sum} - {{2{mult_c12_sum[28]}},mult_c12_sum}; + +always@(posedge clk or negedge rstn) + if(!rstn) + mult_sum_r4 <= 'h0; + else + mult_sum_r4 <= {{4{mult_c13_sum[28]}},mult_c13_sum} - {{4{mult_c14_sum[28]}},mult_c14_sum} + {{3{mult_c15_sum[29]}},mult_c15_sum} - {{3{mult_c16_sum[29]}},mult_c16_sum} + {{1{mult_c17_sum[31]}},mult_c17_sum}; + +reg signed [33:0] mult_sum; + +always@(posedge clk or negedge rstn) + if(!rstn) + mult_sum <= 'h0; + else + mult_sum <= mult_sum_r1 + mult_sum_r2 + mult_sum_r3 + mult_sum_r4; + + +reg signed [15:0] dout0; + +wire [19:0] dout0_w; + +assign dout0_w = mult_sum[33:15] + mult_sum[14]; + +always@(posedge clk or negedge rstn) + if(!rstn) + dout0 <= 'h0; + else if(dout0_w[16:15]==2'b01) + dout0 <= 16'd32767; + else if(dout0_w[16:15]==2'b10) + dout0 <= -16'd32768; + else + dout0 <= dout0_w[15:0]; + +assign dout = dout0; + + +endmodule + + + diff --git a/rtl/xy_dsp/duc/duc_hb1_top.v b/rtl/xy_dsp/duc/duc_hb1_top.v new file mode 100644 index 0000000..14974c8 --- /dev/null +++ b/rtl/xy_dsp/duc/duc_hb1_top.v @@ -0,0 +1,178 @@ +module DUC_HB1_TOP (clkl, + rstn, + din, + dout_p0, + dout_p1 + ); +input clkl,rstn; +input [15:0] din; + +output [15:0] dout_p0; +output [15:0] dout_p1; + + +reg [15:0] din_r1; +reg [15:0] din_r2; +reg [15:0] din_r3; +reg [15:0] din_r4; +reg [15:0] din_r5; +reg [15:0] din_r6; +reg [15:0] din_r7; +reg [15:0] din_r8; +reg [15:0] din_r9; +reg [15:0] din_r10; +reg [15:0] din_r11; +reg [15:0] din_r12; +reg [15:0] din_r13; +reg [15:0] din_r14; +reg [15:0] din_r15; +reg [15:0] din_r16; +reg [15:0] din_r17; +reg [15:0] din_r18; +reg [15:0] din_r19; +reg [15:0] din_r20; +reg [15:0] din_r21; +reg [15:0] din_r22; +reg [15:0] din_r23; +reg [15:0] din_r24; +reg [15:0] din_r25; +reg [15:0] din_r26; +reg [15:0] din_r27; +reg [15:0] din_r28; +reg [15:0] din_r29; +reg [15:0] din_r30; +reg [15:0] din_r31; +reg [15:0] din_r32; +reg [15:0] din_r33; +reg [15:0] din_r34; +reg [15:0] din_r35; + +always@(posedge clkl or negedge rstn) + if(!rstn) + begin + din_r1 <= 'b0; + din_r2 <= 'b0; + din_r3 <= 'b0; + din_r4 <= 'b0; + din_r5 <= 'b0; + din_r6 <= 'b0; + din_r7 <= 'b0; + din_r8 <= 'b0; + din_r9 <= 'b0; + din_r10 <= 'b0; + din_r11 <= 'b0; + din_r12 <= 'b0; + din_r13 <= 'b0; + din_r14 <= 'b0; + din_r15 <= 'b0; + din_r16 <= 'b0; + din_r17 <= 'b0; + din_r18 <= 'b0; + din_r19 <= 'b0; + din_r20 <= 'b0; + din_r21 <= 'b0; + din_r22 <= 'b0; + din_r23 <= 'b0; + din_r24 <= 'b0; + din_r25 <= 'b0; + din_r26 <= 'b0; + din_r27 <= 'b0; + din_r28 <= 'b0; + din_r29 <= 'b0; + din_r30 <= 'b0; + din_r31 <= 'b0; + din_r32 <= 'b0; + din_r33 <= 'b0; + din_r34 <= 'b0; + din_r35 <= 'b0; + end + else + begin + din_r1 <= din; + din_r2 <= din_r1; + din_r3 <= din_r2; + din_r4 <= din_r3; + din_r5 <= din_r4; + din_r6 <= din_r5; + din_r7 <= din_r6; + din_r8 <= din_r7; + din_r9 <= din_r8; + din_r10 <= din_r9; + din_r11 <= din_r10; + din_r12 <= din_r11; + din_r13 <= din_r12; + din_r14 <= din_r13; + din_r15 <= din_r14; + din_r16 <= din_r15; + din_r17 <= din_r16; + din_r18 <= din_r17; + din_r19 <= din_r18; + din_r20 <= din_r19; + din_r21 <= din_r20; + din_r22 <= din_r21; + din_r23 <= din_r22; + din_r24 <= din_r23; + din_r25 <= din_r24; + din_r26 <= din_r25; + din_r27 <= din_r26; + din_r28 <= din_r27; + din_r29 <= din_r28; + din_r30 <= din_r29; + din_r31 <= din_r30; + din_r32 <= din_r31; + din_r33 <= din_r32; + din_r34 <= din_r33; + din_r35 <= din_r34; + end + + + + +DUC_HB1 inst_duc_hb1( + .clk (clkl), + .rstn (rstn), + .din_0 (din), + .din_1 (din_r1), + .din_2 (din_r2), + .din_3 (din_r3), + .din_4 (din_r4), + .din_5 (din_r5), + .din_6 (din_r6), + .din_7 (din_r7), + .din_8 (din_r8), + .din_9 (din_r9), + .din_10 (din_r10), + .din_11 (din_r11), + .din_12 (din_r12), + .din_13 (din_r13), + .din_14 (din_r14), + .din_15 (din_r15), + .din_16 (din_r16), + .din_17 (din_r17), + .din_18 (din_r18), + .din_19 (din_r19), + .din_20 (din_r20), + .din_21 (din_r21), + .din_22 (din_r22), + .din_23 (din_r23), + .din_24 (din_r24), + .din_25 (din_r25), + .din_26 (din_r26), + .din_27 (din_r27), + .din_28 (din_r28), + .din_29 (din_r29), + .din_30 (din_r30), + .din_31 (din_r31), + .din_32 (din_r32), + .din_33 (din_r33), + .din_34 (din_r34), + .din_35 (din_r35), + .dout (dout_p1) + ); + + +assign dout_p0 = din_r22; + +endmodule + + diff --git a/rtl/xy_dsp/duc/duc_hb2_pipe_shift.v b/rtl/xy_dsp/duc/duc_hb2_pipe_shift.v new file mode 100644 index 0000000..560ed6f --- /dev/null +++ b/rtl/xy_dsp/duc/duc_hb2_pipe_shift.v @@ -0,0 +1,259 @@ +//+FHDR-------------------------------------------------------------------------------------------------------- +// Company: +//----------------------------------------------------------------------------------------------------------------- +// File Name : duc_hb2_shift.v +// Department : +// Author : thfu +// Author's Tel : +//----------------------------------------------------------------------------------------------------------------- +// Relese History +// Version Date Author Description +// 0.8 2024-03-26 thfu add pipeline +//----------------------------------------------------------------------------------------------------------------- +// Keywords : +// +//----------------------------------------------------------------------------------------------------------------- +// Parameter +// +//----------------------------------------------------------------------------------------------------------------- +// Purpose : +// +//----------------------------------------------------------------------------------------------------------------- +// Target Device: +// Tool versions: +//----------------------------------------------------------------------------------------------------------------- +// Reuse Issues +// Reset Strategy: +// Clock Domains: +// Critical Timing: +// Asynchronous I/F: +// Synthesizable (y/n): +// Other: +//-FHDR-------------------------------------------------------------------------------------------------------- +module DUC_HB2 ( + clk, + rstn, + din_0, + din_1, + din_2, + din_3, + din_4, + din_5, + din_6, + din_7, + din_8, + din_9, + din_a, + din_b, + dout + ); +input clk; +input rstn; +input signed [15:0] din_0; +input signed [15:0] din_1; +input signed [15:0] din_2; +input signed [15:0] din_3; +input signed [15:0] din_4; +input signed [15:0] din_5; +input signed [15:0] din_6; +input signed [15:0] din_7; +input signed [15:0] din_8; +input signed [15:0] din_9; +input signed [15:0] din_a; +input signed [15:0] din_b; + +output signed [15:0] dout; + +parameter c0 = -18'd91; +parameter c1 = 18'd659; +parameter c2 = -18'd2663; +parameter c3 = 18'd8009; +parameter c4 = -18'd21490; +parameter c5 = 18'd81112; + +reg signed [16:0] sum_0_b; +reg signed [16:0] sum_1_a; +reg signed [16:0] sum_2_9; +reg signed [16:0] sum_3_8; +reg signed [16:0] sum_4_7; +reg signed [16:0] sum_5_6; +always@(posedge clk or negedge rstn) + if(!rstn) + begin + sum_0_b <= 'h0; + sum_1_a <= 'h0; + sum_2_9 <= 'h0; + sum_3_8 <= 'h0; + sum_4_7 <= 'h0; + sum_5_6 <= 'h0; + end + else + begin + sum_0_b <= {{1 {din_0[15]}},din_0} + {{1 {din_b[15]}},din_b}; + sum_1_a <= {{1 {din_1[15]}},din_1} + {{1 {din_a[15]}},din_a}; + sum_2_9 <= {{1 {din_2[15]}},din_2} + {{1 {din_9[15]}},din_9}; + sum_3_8 <= {{1 {din_3[15]}},din_3} + {{1 {din_8[15]}},din_8}; + sum_4_7 <= {{1 {din_4[15]}},din_4} + {{1 {din_7[15]}},din_7}; + sum_5_6 <= {{1 {din_5[15]}},din_5} + {{1 {din_6[15]}},din_6}; + end + + +wire signed [16:0] mult_c0_sum0; +wire signed [19:0] mult_c0_sum1; +wire signed [21:0] mult_c0_sum2; + +assign mult_c0_sum0 = sum_0_b; +assign mult_c0_sum1 = {sum_0_b,3'b0}; +assign mult_c0_sum2 = {sum_0_b,5'b0}; + +reg signed [22:0] mult_c0_sum; + +always@(posedge clk or negedge rstn) + if(!rstn) + mult_c0_sum <= 'h0; + else + mult_c0_sum <= -{{6{mult_c0_sum0[16]}},mult_c0_sum0} - {{3{mult_c0_sum1[19]}},mult_c0_sum1} + {{1{mult_c0_sum2[21]}},mult_c0_sum2}; + + +wire signed [16:0] mult_c1_sum0; +wire signed [18:0] mult_c1_sum1; +wire signed [21:0] mult_c1_sum2; +wire signed [23:0] mult_c1_sum3; + +assign mult_c1_sum0 = sum_1_a; +assign mult_c1_sum1 = {sum_1_a,2'b0}; +assign mult_c1_sum2 = {sum_1_a,5'b0}; +assign mult_c1_sum3 = {sum_1_a,7'b0}; + +reg signed [24:0] mult_c1_sum; + +always@(posedge clk or negedge rstn) + if(!rstn) + mult_c1_sum <= 'h0; + else + mult_c1_sum <= {{8{mult_c1_sum0[16]}},mult_c1_sum0} + {{6{mult_c1_sum1[18]}},mult_c1_sum1} + {{3{mult_c1_sum2[21]}},mult_c1_sum2} + {{1{mult_c1_sum3[23]}},mult_c1_sum3}; + + + +wire signed [17:0] mult_c2_sum0; +wire signed [18:0] mult_c2_sum1; +wire signed [21:0] mult_c2_sum2; +wire signed [22:0] mult_c2_sum3; +wire signed [24:0] mult_c2_sum4; +wire signed [26:0] mult_c2_sum5; + +assign mult_c2_sum0 = {sum_2_9,1'b0}; +assign mult_c2_sum1 = {sum_2_9,2'b0}; +assign mult_c2_sum2 = {sum_2_9,5'b0}; +assign mult_c2_sum3 = {sum_2_9,6'b0}; +assign mult_c2_sum4 = {sum_2_9,8'b0}; +assign mult_c2_sum5 = {sum_2_9,10'b0}; + +reg signed [27:0] mult_c2_sum; + +always@(posedge clk or negedge rstn) + if(!rstn) + mult_c2_sum <= 'h0; + else + mult_c2_sum <= -{{10{mult_c2_sum0[17]}},mult_c2_sum0} - {{9{mult_c2_sum1[18]}},mult_c2_sum1} - {{6{mult_c2_sum2[21]}},mult_c2_sum2} - {{5{mult_c2_sum3[22]}},mult_c2_sum3} - {{3{mult_c2_sum4[24]}},mult_c2_sum4} + {{1{mult_c2_sum5[26]}},mult_c2_sum5}; + + +wire signed [17:0] mult_c3_sum0; +wire signed [20:0] mult_c3_sum1; +wire signed [22:0] mult_c3_sum2; +wire signed [27:0] mult_c3_sum3; + +assign mult_c3_sum0 = {sum_3_8,1'b0}; +assign mult_c3_sum1 = {sum_3_8,4'b0}; +assign mult_c3_sum2 = {sum_3_8,6'b0}; +assign mult_c3_sum3 = {sum_3_8,11'b0}; + +reg signed [28:0] mult_c3_sum; + +always@(posedge clk or negedge rstn) + if(!rstn) + mult_c3_sum <= 'h0; + else + mult_c3_sum <= {{11{mult_c3_sum0[17]}},mult_c3_sum0} + {{8{mult_c3_sum1[20]}},mult_c3_sum1} - {{6{mult_c3_sum2[22]}},mult_c3_sum2} + {{1{mult_c3_sum3[27]}},mult_c3_sum3}; + + + + + +wire signed [16:0] mult_c4_sum0; +wire signed [18:0] mult_c4_sum1; +wire signed [24:0] mult_c4_sum2; +wire signed [26:0] mult_c4_sum3; +wire signed [28:0] mult_c4_sum4; + +assign mult_c4_sum0 = sum_4_7; +assign mult_c4_sum1 = {sum_4_7,2'b0}; +assign mult_c4_sum2 = {sum_4_7,8'b0}; +assign mult_c4_sum3 = {sum_4_7,10'b0}; +assign mult_c4_sum4 = {sum_4_7,12'b0}; + +reg signed [29:0] mult_c4_sum; + +always@(posedge clk or negedge rstn) + if(!rstn) + mult_c4_sum <= 'h0; + else + mult_c4_sum <= {{13{mult_c4_sum0[16]}},mult_c4_sum0} - {{11{mult_c4_sum1[18]}},mult_c4_sum1} + {{5{mult_c4_sum2[24]}},mult_c4_sum2} + {{3{mult_c4_sum3[26]}},mult_c4_sum3} + {{1{mult_c4_sum4[28]}},mult_c4_sum4}; + + + + + +wire signed [17:0] mult_c5_sum0; +wire signed [18:0] mult_c5_sum1; +wire signed [20:0] mult_c5_sum2; +wire signed [21:0] mult_c5_sum3; +wire signed [24:0] mult_c5_sum4; +wire signed [28:0] mult_c5_sum5; +wire signed [30:0] mult_c5_sum6; + +assign mult_c5_sum0 = {sum_5_6,1'b0}; +assign mult_c5_sum1 = {sum_5_6,2'b0}; +assign mult_c5_sum2 = {sum_5_6,4'b0}; +assign mult_c5_sum3 = {sum_5_6,5'b0}; +assign mult_c5_sum4 = {sum_5_6,8'b0}; +assign mult_c5_sum5 = {sum_5_6,12'b0}; +assign mult_c5_sum6 = {sum_5_6,14'b0}; + +reg signed [31:0] mult_c5_sum; + +always@(posedge clk or negedge rstn) + if(!rstn) + mult_c5_sum <= 'h0; + else + mult_c5_sum <= {{14{mult_c5_sum0[17]}},mult_c5_sum0} + {{13{mult_c5_sum1[18]}},mult_c5_sum1} + {{11{mult_c5_sum2[20]}},mult_c5_sum2} + {{10{mult_c5_sum3[21]}},mult_c5_sum3} - {{7{mult_c5_sum4[24]}},mult_c5_sum4} + {{3{mult_c5_sum5[28]}},mult_c5_sum5} + {{1{mult_c5_sum6[30]}},mult_c5_sum6}; + +reg signed [32:0] mult_sum; + +always@(posedge clk or negedge rstn) + if(!rstn) + mult_sum <= 'h0; + else + mult_sum <= -{{10{mult_c0_sum[22]}},mult_c0_sum} + {{8{mult_c1_sum[24]}},mult_c1_sum} - {{5{mult_c2_sum[27]}},mult_c2_sum} + {{4{mult_c3_sum[28]}},mult_c3_sum} - {{3{mult_c4_sum[29]}},mult_c4_sum} + {{1{mult_c5_sum[31]}},mult_c5_sum}; + +wire signed [17:0] dout0_w; + +reg signed [15:0] dout0; + +assign dout0_w = mult_sum[32:15]+mult_sum[14]; + +always@(posedge clk or negedge rstn) + if(!rstn) + dout0 <= 'h0; + else if(dout0_w[16:15]==2'b01) + dout0 <= 16'd32767; + else if(dout0_w[16:15]==2'b10) + dout0 <= -16'd32768; + else + dout0 <= dout0_w[15:0]; + +assign dout = dout0; + +endmodule + + diff --git a/rtl/xy_dsp/duc/duc_hb2_top_s.v b/rtl/xy_dsp/duc/duc_hb2_top_s.v new file mode 100644 index 0000000..ea84b22 --- /dev/null +++ b/rtl/xy_dsp/duc/duc_hb2_top_s.v @@ -0,0 +1,118 @@ +module DUC_HB2_TOP_S (clkl, + rstn, + din0, + din1, + dout_p0, + dout_p1, + dout_p2, + dout_p3 + ); +input clkl,rstn; +input [15:0] din0; +input [15:0] din1; + +output [15:0] dout_p0; +output [15:0] dout_p1; +output [15:0] dout_p2; +output [15:0] dout_p3; + + +reg [15:0] din_r1; +reg [15:0] din_r2; +reg [15:0] din_r3; +reg [15:0] din_r4; +reg [15:0] din_r5; +reg [15:0] din_r6; +reg [15:0] din_r7; +reg [15:0] din_r8; +reg [15:0] din_r9; +reg [15:0] din_r10; +reg [15:0] din_r11; +reg [15:0] din_r12; +reg [15:0] din_r13; +reg [15:0] din_r14; + +always@(posedge clkl or negedge rstn) + if(!rstn) + begin + din_r1 <= 'b0; + din_r2 <= 'b0; + din_r3 <= 'b0; + din_r4 <= 'b0; + din_r5 <= 'b0; + din_r6 <= 'b0; + din_r7 <= 'b0; + din_r8 <= 'b0; + din_r9 <= 'b0; + din_r10 <= 'b0; + din_r11 <= 'b0; + din_r12 <= 'b0; + end + else + begin + din_r1 <= din1; + din_r3 <= din_r1; + din_r5 <= din_r3; + din_r7 <= din_r5; + din_r9 <= din_r7; + din_r11 <= din_r9; + din_r13 <= din_r11; + + din_r2 <= din0; + din_r4 <= din_r2; + din_r6 <= din_r4; + din_r8 <= din_r6; + din_r10 <= din_r8; + din_r12 <= din_r10; + din_r14 <= din_r12; + end + + + + +DUC_HB2 inst0_duc_hb2( + .clk (clkl), + .rstn (rstn), + .din_0 (din1), + .din_1 (din0), + .din_2 (din_r1), + .din_3 (din_r2), + .din_4 (din_r3), + .din_5 (din_r4), + .din_6 (din_r5), //dout_p0 + .din_7 (din_r6), + .din_8 (din_r7), + .din_9 (din_r8), + .din_a (din_r9), + .din_b (din_r10), + .dout (dout_p1) + ); + + +assign dout_p0 = din_r13; + + +DUC_HB2 inst1_duc_hb2( + .clk (clkl), + .rstn (rstn), + .din_0 (din0), + .din_1 (din_r1), + .din_2 (din_r2), + .din_3 (din_r3), + .din_4 (din_r4), + .din_5 (din_r5), + .din_6 (din_r6), //dout_p2 + .din_7 (din_r7), + .din_8 (din_r8), + .din_9 (din_r9), + .din_a (din_r10), + .din_b (din_r11), + .dout (dout_p3) + ); + + +assign dout_p2 = din_r14; + +endmodule + + diff --git a/rtl/xy_dsp/duc/duc_hb3_pipe_shift.v b/rtl/xy_dsp/duc/duc_hb3_pipe_shift.v new file mode 100644 index 0000000..233d2cd --- /dev/null +++ b/rtl/xy_dsp/duc/duc_hb3_pipe_shift.v @@ -0,0 +1,193 @@ +//+FHDR-------------------------------------------------------------------------------------------------------- +// Company: +//----------------------------------------------------------------------------------------------------------------- +// File Name : duc_hb3_shift.v +// Department : +// Author : +// Author's Tel : +//----------------------------------------------------------------------------------------------------------------- +// Relese History +// Version Date Author Description +// 0.8 2024-03-26 thfu output register +//----------------------------------------------------------------------------------------------------------------- +// Keywords : +// +//----------------------------------------------------------------------------------------------------------------- +// Parameter +// +//----------------------------------------------------------------------------------------------------------------- +// Purpose : +// +//----------------------------------------------------------------------------------------------------------------- +// Target Device: +// Tool versions: +//----------------------------------------------------------------------------------------------------------------- +// Reuse Issues +// Reset Strategy: +// Clock Domains: +// Critical Timing: +// Asynchronous I/F: +// Synthesizable (y/n): +// Other: +//-FHDR-------------------------------------------------------------------------------------------------------- +module DUC_HB3 ( + clk, + rstn, + din_0, + din_1, + din_2, + din_3, + din_4, + din_5, + din_6, + din_7, + dout + ); +input clk; +input rstn; +input signed [15:0] din_0; +input signed [15:0] din_1; +input signed [15:0] din_2; +input signed [15:0] din_3; +input signed [15:0] din_4; +input signed [15:0] din_5; +input signed [15:0] din_6; +input signed [15:0] din_7; + +output signed [15:0] dout; + +parameter c0 = -17'd210; +parameter c1 = 17'd1799; +parameter c2 = -17'd8234; +parameter c3 = 17'd39413; + +reg signed [16:0] sum_0_7; +reg signed [16:0] sum_1_6; +reg signed [16:0] sum_2_5; +reg signed [16:0] sum_3_4; + + +always@(posedge clk or negedge rstn) + if(!rstn) + begin + sum_0_7 <= 'h0; + sum_1_6 <= 'h0; + sum_2_5 <= 'h0; + sum_3_4 <= 'h0; + end + else + begin + sum_0_7 <= {{1 {din_0[15]}},din_0} + {{1 {din_7[15]}},din_7}; + sum_1_6 <= {{1 {din_1[15]}},din_1} + {{1 {din_6[15]}},din_6}; + sum_2_5 <= {{1 {din_2[15]}},din_2} + {{1 {din_5[15]}},din_5}; + sum_3_4 <= {{1 {din_3[15]}},din_3} + {{1 {din_4[15]}},din_4}; + end + + +wire signed [16:0] mult_c0_sum0; +wire signed [19:0] mult_c0_sum1; +wire signed [21:0] mult_c0_sum2; +wire signed [22:0] mult_c0_sum3; + +assign mult_c0_sum0 = sum_0_7; +assign mult_c0_sum1 = {sum_0_7,3'b0}; +assign mult_c0_sum2 = {sum_0_7,5'b0}; +assign mult_c0_sum3 = {sum_0_7,6'b0}; + +reg signed [23:0] mult_c0_sum; + +always@(posedge clk or negedge rstn) + if(!rstn) + mult_c0_sum <= 'h0; + else + mult_c0_sum <= {{7{mult_c0_sum0[16]}},mult_c0_sum0} + {{4{mult_c0_sum1[19]}},mult_c0_sum1} + {{2{mult_c0_sum2[21]}},mult_c0_sum2} + {{1{mult_c0_sum3[22]}},mult_c0_sum3}; + + +wire signed [18:0] mult_c1_sum0; +wire signed [23:0] mult_c1_sum1; +wire signed [26:0] mult_c1_sum2; + +assign mult_c1_sum0 = {sum_1_6,2'b0}; +assign mult_c1_sum1 = {sum_1_6,7'b0}; +assign mult_c1_sum2 = {sum_1_6,10'b0}; + +reg signed [27:0] mult_c1_sum; +always@(posedge clk or negedge rstn) + if(!rstn) + mult_c1_sum <= 'h0; + else + mult_c1_sum <= {{9{mult_c1_sum0[18]}},mult_c1_sum0} - {{4{mult_c1_sum1[23]}},mult_c1_sum1} + {{1{mult_c1_sum2[26]}},mult_c1_sum2}; + + +wire signed [16:0] mult_c2_sum0; +wire signed [18:0] mult_c2_sum1; +wire signed [20:0] mult_c2_sum2; +wire signed [28:0] mult_c2_sum3; + +assign mult_c2_sum0 = sum_2_5; +assign mult_c2_sum1 = {sum_2_5,2'b0}; +assign mult_c2_sum2 = {sum_2_5,4'b0}; +assign mult_c2_sum3 = {sum_2_5,12'b0}; + +reg signed [29:0] mult_c2_sum; + +always@(posedge clk or negedge rstn) + if(!rstn) + mult_c2_sum <= 'h0; + else + mult_c2_sum <= {{13{mult_c2_sum0[16]}},mult_c2_sum0} + {{11{mult_c2_sum1[18]}},mult_c2_sum1} + {{9{mult_c2_sum2[20]}},mult_c2_sum2} + {{1{mult_c2_sum3[28]}},mult_c2_sum3}; + + +wire signed [16:0] mult_c3_sum0; +wire signed [17:0] mult_c3_sum1; +wire signed [19:0] mult_c3_sum2; +wire signed [24:0] mult_c3_sum3; +wire signed [26:0] mult_c3_sum4; +wire signed [27:0] mult_c3_sum5; +wire signed [30:0] mult_c3_sum6; +; +assign mult_c3_sum0 = sum_3_4; +assign mult_c3_sum1 = {sum_3_4,1'b0}; +assign mult_c3_sum2 = {sum_3_4,3'b0}; +assign mult_c3_sum3 = {sum_3_4,8'b0}; +assign mult_c3_sum4 = {sum_3_4,10'b0}; +assign mult_c3_sum5 = {sum_3_4,11'b0}; +assign mult_c3_sum6 = {sum_3_4,14'b0}; + +reg signed [31:0] mult_c3_sum; + +always@(posedge clk or negedge rstn) + if(!rstn) + mult_c3_sum <= 'h0; + else + mult_c3_sum <= {{15{mult_c3_sum0[16]}},mult_c3_sum0} + {{14{mult_c3_sum1[17]}},mult_c3_sum1} - {{12{mult_c3_sum2[19]}},mult_c3_sum2} + {{7{mult_c3_sum3[24]}},mult_c3_sum3} + {{5{mult_c3_sum4[26]}},mult_c3_sum4} + {{4{mult_c3_sum5[27]}},mult_c3_sum5} + {{1{mult_c3_sum6[30]}},mult_c3_sum6}; + + +reg signed [32:0] mult_sum; + +always@(posedge clk or negedge rstn) + if(!rstn) + mult_sum <= 'h0; + else + mult_sum <= -{{9{mult_c0_sum[23]}},mult_c0_sum} + {{5{mult_c1_sum[27]}},mult_c1_sum} - {{3{mult_c2_sum[29]}},mult_c2_sum} + {{1{mult_c3_sum[31]}},mult_c3_sum}; + +wire signed [17:0] dout0_w; + +reg signed [15:0] dout0; + +assign dout0_w = mult_sum[32:15]+mult_sum[14]; + +always@(posedge clk or negedge rstn) + if(!rstn) + dout0 <= 'h0; + else if(dout0_w[16:15]==2'b01) + dout0 <= 16'd32767; + else if(dout0_w[16:15]==2'b10) + dout0 <= -16'd32768; + else + dout0 <= dout0_w[15:0]; + +assign dout = dout0; + +endmodule + diff --git a/rtl/xy_dsp/duc/duc_hb3_top_s2.v b/rtl/xy_dsp/duc/duc_hb3_top_s2.v new file mode 100644 index 0000000..a7304ed --- /dev/null +++ b/rtl/xy_dsp/duc/duc_hb3_top_s2.v @@ -0,0 +1,197 @@ +//+FHDR-------------------------------------------------------------------------------------------------------- +// Company: +//----------------------------------------------------------------------------------------------------------------- +// File Name : duc_hb3_shift.v +// Department : +// Author : +// Author's Tel : +//----------------------------------------------------------------------------------------------------------------- +// Relese History +// Version Date Author Description +// 0.8 2024-03-26 thfu modify delay +//----------------------------------------------------------------------------------------------------------------- +// Keywords : +// +//----------------------------------------------------------------------------------------------------------------- +// Parameter +// +//----------------------------------------------------------------------------------------------------------------- +// Purpose : +// +//----------------------------------------------------------------------------------------------------------------- +// Target Device: +// Tool versions: +//----------------------------------------------------------------------------------------------------------------- +// Reuse Issues +// Reset Strategy: +// Clock Domains: +// Critical Timing: +// Asynchronous I/F: +// Synthesizable (y/n): +// Other: +//-FHDR-------------------------------------------------------------------------------------------------------- +module DUC_HB3_TOP_S2 (clkl, + rstn, + din0, + din1, + din2, + din3, + dout_p0, + dout_p1, + dout_p2, + dout_p3, + dout_p4, + dout_p5, + dout_p6, + dout_p7 + ); +input clkl,rstn; +input [15:0] din0; +input [15:0] din1; +input [15:0] din2; +input [15:0] din3; + +output [15:0] dout_p0; +output [15:0] dout_p1; +output [15:0] dout_p2; +output [15:0] dout_p3; +output [15:0] dout_p4; +output [15:0] dout_p5; +output [15:0] dout_p6; +output [15:0] dout_p7; + + +reg [15:0] din_r1; +reg [15:0] din_r2; +reg [15:0] din_r3; +reg [15:0] din_r4; +reg [15:0] din_r5; +reg [15:0] din_r6; +reg [15:0] din_r7; +reg [15:0] din_r8; +reg [15:0] din_r9; +reg [15:0] din_r10; +reg [15:0] din_r11; +reg [15:0] din_r12; +reg [15:0] din_r13; +reg [15:0] din_r14; +reg [15:0] din_r15; +reg [15:0] din_r16; +reg [15:0] din_r17; +reg [15:0] din_r18; +reg [15:0] din_r19; +reg [15:0] din_r20; + +always@(posedge clkl or negedge rstn) + if(!rstn) + begin + din_r1 <= 'b0; + din_r2 <= 'b0; + din_r3 <= 'b0; + din_r4 <= 'b0; + din_r5 <= 'b0; + din_r6 <= 'b0; + din_r7 <= 'b0; + end + else + begin + din_r1 <= din3; + din_r5 <= din_r1; + din_r9 <= din_r5; + din_r13 <= din_r9; + din_r17 <= din_r13; + + + din_r2 <= din2; + din_r6 <= din_r2; + din_r10 <= din_r6; + din_r14 <= din_r10; + din_r18 <= din_r14; + + + din_r3 <= din1; + din_r7 <= din_r3; + din_r11 <= din_r7; + din_r15 <= din_r11; + din_r19 <= din_r15; + + din_r4 <= din0; + din_r8 <= din_r4; + din_r12 <= din_r8; + din_r16 <= din_r12; + din_r20 <= din_r16; + + end + + + + +DUC_HB3 inst0_duc_hb3( + .clk (clkl), + .rstn (rstn), + .din_0 (din3), + .din_1 (din2), + .din_2 (din1), + .din_3 (din0), + .din_4 (din_r1), + .din_5 (din_r2), + .din_6 (din_r3), + .din_7 (din_r4), + .dout (dout_p1) + ); + + +assign dout_p0 = din_r17; + + +DUC_HB3 inst1_duc_hb3( + .clk (clkl), + .rstn (rstn), + .din_0 (din2), + .din_1 (din1), + .din_2 (din0), + .din_3 (din_r1), + .din_4 (din_r2), + .din_5 (din_r3), + .din_6 (din_r4), + .din_7 (din_r5), + .dout (dout_p3) + ); + +assign dout_p2 = din_r18; + +DUC_HB3 inst2_duc_hb3( + .clk (clkl), + .rstn (rstn), + .din_0 (din1), + .din_1 (din0), + .din_2 (din_r1), + .din_3 (din_r2), + .din_4 (din_r3), + .din_5 (din_r4), + .din_6 (din_r5), + .din_7 (din_r6), + .dout (dout_p5) + ); + +assign dout_p4 = din_r19; + +DUC_HB3 inst3_duc_hb3( + .clk (clkl), + .rstn (rstn), + .din_0 (din0), + .din_1 (din_r1), + .din_2 (din_r2), + .din_3 (din_r3), + .din_4 (din_r4), + .din_5 (din_r5), + .din_6 (din_r6), + .din_7 (din_r7), + .dout (dout_p7) + ); + +assign dout_p6 = din_r20; +endmodule + + + diff --git a/rtl/xy_dsp/duc/duc_hb4_pipe_shift.v b/rtl/xy_dsp/duc/duc_hb4_pipe_shift.v new file mode 100644 index 0000000..261c637 --- /dev/null +++ b/rtl/xy_dsp/duc/duc_hb4_pipe_shift.v @@ -0,0 +1,169 @@ +//+FHDR-------------------------------------------------------------------------------------------------------- +// Company: +//----------------------------------------------------------------------------------------------------------------- +// File Name : duc_hb4_shift.v +// Department : +// Author : +// Author's Tel : +//----------------------------------------------------------------------------------------------------------------- +// Relese History +// Version Date Author Description +// 0.8 2024-03-26 thfu output register +//----------------------------------------------------------------------------------------------------------------- +// Keywords : +// +//----------------------------------------------------------------------------------------------------------------- +// Parameter +// +//----------------------------------------------------------------------------------------------------------------- +// Purpose : +// +//----------------------------------------------------------------------------------------------------------------- +// Target Device: +// Tool versions: +//----------------------------------------------------------------------------------------------------------------- +// Reuse Issues +// Reset Strategy: +// Clock Domains: +// Critical Timing: +// Asynchronous I/F: +// Synthesizable (y/n): +// Other: +//-FHDR-------------------------------------------------------------------------------------------------------- +module DUC_HB4 ( + clk, + rstn, + din_0, + din_1, + din_2, + din_3, + din_4, + din_5, + dout + ); +input clk; +input rstn; +input signed [15:0] din_0; +input signed [15:0] din_1; +input signed [15:0] din_2; +input signed [15:0] din_3; +input signed [15:0] din_4; +input signed [15:0] din_5; + +output signed [15:0] dout; + +wire signed [15:0] din_0; +wire signed [15:0] din_2; +wire signed [15:0] din_4; +wire signed [15:0] din_5; +wire signed [15:0] din_6; + + +parameter c0 = 14'd101; +parameter c1 = -14'd814; +parameter c2 = 14'd4809; + +reg signed [16:0] sum_0_5; +reg signed [16:0] sum_1_4; +reg signed [16:0] sum_2_3; + + +always@(posedge clk or negedge rstn) + if(!rstn) + begin + sum_0_5 <= 'h0; + sum_1_4 <= 'h0; + sum_2_3 <= 'h0; + end + else + begin + sum_0_5 <= {din_0[15],din_0} + {din_5[15],din_5}; + sum_1_4 <= {din_1[15],din_1} + {din_4[15],din_4}; + sum_2_3 <= {din_2[15],din_2} + {din_3[15],din_3}; + end + +wire signed [18:0] mult_c0_sum0; +wire signed [20:0] mult_c0_sum1; +wire signed [23:0] mult_c0_sum2; +wire signed [24:0] mult_c0_sum3; + +assign mult_c0_sum0 = {sum_0_5,2'b0}; +assign mult_c0_sum1 = {sum_0_5,4'b0}; +assign mult_c0_sum2 = {sum_0_5,7'b0}; +assign mult_c0_sum3 = {sum_0_5,8'b0}; + +reg signed [25:0] mult_c0_sum; +always@(posedge clk or negedge rstn) + if(!rstn) + mult_c0_sum <= 'h0; + else + mult_c0_sum <= {{7{mult_c0_sum0[18]}},mult_c0_sum0} + {{5{mult_c0_sum1[20]}},mult_c0_sum1} + {{2{mult_c0_sum2[23]}},mult_c0_sum2} + {{1{mult_c0_sum3[24]}},mult_c0_sum3}; + +wire signed [19:0] mult_c1_sum0; +wire signed [22:0] mult_c1_sum1; +wire signed [23:0] mult_c1_sum2; +wire signed [26:0] mult_c1_sum3; +wire signed [27:0] mult_c1_sum4; + +assign mult_c1_sum0 = {sum_1_4,3'b0}; +assign mult_c1_sum1 = {sum_1_4,6'b0}; +assign mult_c1_sum2 = {sum_1_4,7'b0}; +assign mult_c1_sum3 = {sum_1_4,10'b0}; +assign mult_c1_sum4 = {sum_1_4,11'b0}; + +reg signed [28:0] mult_c1_sum; +always@(posedge clk or negedge rstn) + if(!rstn) + mult_c1_sum <= 'h0; + else + mult_c1_sum <= -{{9{mult_c1_sum0[19]}},mult_c1_sum0} + {{6{mult_c1_sum1[22]}},mult_c1_sum1} + {{5{mult_c1_sum2[23]}},mult_c1_sum2} + {{2{mult_c1_sum3[26]}},mult_c1_sum3} + {{1{mult_c1_sum4[27]}},mult_c1_sum4}; + + +wire signed [18:0] mult_c2_sum0; +wire signed [21:0] mult_c2_sum1; +wire signed [24:0] mult_c2_sum2; +wire signed [25:0] mult_c2_sum3; +wire signed [27:0] mult_c2_sum4; +wire signed [30:0] mult_c2_sum5; + +assign mult_c2_sum0 = {sum_2_3,2'b0}; +assign mult_c2_sum1 = {sum_2_3,5'b0}; +assign mult_c2_sum2 = {sum_2_3,8'b0}; +assign mult_c2_sum3 = {sum_2_3,9'b0}; +assign mult_c2_sum4 = {sum_2_3,11'b0}; +assign mult_c2_sum5 = {sum_2_3,14'b0}; + +reg signed [31:0] mult_c2_sum; +always@(posedge clk or negedge rstn) + if(!rstn) + mult_c2_sum <= 'h0; + else + mult_c2_sum <= {{13{mult_c2_sum0[18]}},mult_c2_sum0} + {{10{mult_c2_sum1[21]}},mult_c2_sum1} + {{7{mult_c2_sum2[24]}},mult_c2_sum2} + {{6{mult_c2_sum3[25]}},mult_c2_sum3} + {{4{mult_c2_sum4[27]}},mult_c2_sum4} + {{1{mult_c2_sum5[30]}},mult_c2_sum5}; + + + +reg signed [32:0] mult_sum; +wire signed [17:0] dout0_w; +reg signed [15:0] dout0; + +always@(posedge clk or negedge rstn) + if(!rstn) + mult_sum <= 'h0; + else + mult_sum <= {{7{mult_c0_sum[25]}},mult_c0_sum} - {{4{mult_c1_sum[28]}},mult_c1_sum} + {{1{mult_c2_sum[31]}},mult_c2_sum}; + +assign dout0_w = mult_sum[32:15]+mult_sum[14]; + +always@(posedge clk or negedge rstn) + if(!rstn) + dout0 <= 'h0; + else if(dout0_w[16:15]==2'b01) + dout0 <= 16'd32767; + else if(dout0_w[16:15]==2'b10) + dout0 <= -16'd32768; + else + dout0 <= dout0_w[15:0]; + +assign dout = dout0; +endmodule + diff --git a/rtl/xy_dsp/duc/duc_hb4_top_s3.v b/rtl/xy_dsp/duc/duc_hb4_top_s3.v new file mode 100644 index 0000000..25fcccc --- /dev/null +++ b/rtl/xy_dsp/duc/duc_hb4_top_s3.v @@ -0,0 +1,319 @@ +//+FHDR-------------------------------------------------------------------------------------------------------- +// Company: +//----------------------------------------------------------------------------------------------------------------- +// File Name : duc_hb4_top_s3.v +// Department : +// Author : +// Author's Tel : +//----------------------------------------------------------------------------------------------------------------- +// Relese History +// Version Date Author Description +// 0.8 2024-03-26 thfu modify delay +//----------------------------------------------------------------------------------------------------------------- +// Keywords : +// +//----------------------------------------------------------------------------------------------------------------- +// Parameter +// +//----------------------------------------------------------------------------------------------------------------- +// Purpose : +// +//----------------------------------------------------------------------------------------------------------------- +// Target Device: +// Tool versions: +//----------------------------------------------------------------------------------------------------------------- +// Reuse Issues +// Reset Strategy: +// Clock Domains: +// Critical Timing: +// Asynchronous I/F: +// Synthesizable (y/n): +// Other: +//-FHDR-------------------------------------------------------------------------------------------------------- +module DUC_HB4_TOP_S3 (clkl, + rstn, + din0, + din1, + din2, + din3, + din4, + din5, + din6, + din7, + dout_p0, + dout_p1, + dout_p2, + dout_p3, + dout_p4, + dout_p5, + dout_p6, + dout_p7, + dout_p8, + dout_p9, + dout_pa, + dout_pb, + dout_pc, + dout_pd, + dout_pe, + dout_pf + ); +input clkl,rstn; + +input [15:0] din0; +input [15:0] din1; +input [15:0] din2; +input [15:0] din3; +input [15:0] din4; +input [15:0] din5; +input [15:0] din6; +input [15:0] din7; + +output [15:0] dout_p0; +output [15:0] dout_p1; +output [15:0] dout_p2; +output [15:0] dout_p3; +output [15:0] dout_p4; +output [15:0] dout_p5; +output [15:0] dout_p6; +output [15:0] dout_p7; +output [15:0] dout_p8; +output [15:0] dout_p9; +output [15:0] dout_pa; +output [15:0] dout_pb; +output [15:0] dout_pc; +output [15:0] dout_pd; +output [15:0] dout_pe; +output [15:0] dout_pf; + +reg [15:0] din_r1; +reg [15:0] din_r2; +reg [15:0] din_r3; +reg [15:0] din_r4; +reg [15:0] din_r5; +reg [15:0] din_r6; +reg [15:0] din_r7; +reg [15:0] din_r8; +reg [15:0] din_r9; +reg [15:0] din_r10; +reg [15:0] din_r11; +reg [15:0] din_r12; +reg [15:0] din_r13; +reg [15:0] din_r14; +reg [15:0] din_r15; +reg [15:0] din_r16; +reg [15:0] din_r17; +reg [15:0] din_r18; +reg [15:0] din_r19; +reg [15:0] din_r20; +reg [15:0] din_r21; +reg [15:0] din_r22; +reg [15:0] din_r23; +reg [15:0] din_r24; +reg [15:0] din_r25; +reg [15:0] din_r26; +reg [15:0] din_r27; +reg [15:0] din_r28; +reg [15:0] din_r29; +reg [15:0] din_r30; +reg [15:0] din_r31; +reg [15:0] din_r32; +reg [15:0] din_r33; +reg [15:0] din_r34; +reg [15:0] din_r35; + + +always@(posedge clkl or negedge rstn) + if(!rstn) + begin + din_r1 <= 'b0; + din_r2 <= 'b0; + din_r3 <= 'b0; + din_r4 <= 'b0; + din_r5 <= 'b0; + din_r6 <= 'b0; + din_r7 <= 'b0; + din_r8 <= 'b0; + din_r9 <= 'b0; + din_r10 <= 'b0; + din_r11 <= 'b0; + din_r12 <= 'b0; + din_r13 <= 'b0; + din_r14 <= 'b0; + end + else + begin + din_r1 <= din7; + din_r2 <= din6; + din_r3 <= din5; + din_r4 <= din4; + din_r5 <= din3; + din_r6 <= din2; + din_r7 <= din1; + din_r8 <= din0; + + din_r9 <= din_r1; + din_r17 <= din_r9; + din_r25 <= din_r17; + din_r33 <= din_r25; + + + din_r10 <= din_r2; + din_r18 <= din_r10; + din_r26 <= din_r18; + din_r34 <= din_r26; + + din_r11 <= din_r3; + din_r19 <= din_r11; + din_r27 <= din_r19; + din_r35 <= din_r27; + + din_r12 <= din_r4; + din_r20 <= din_r12; + din_r28 <= din_r20; + + din_r13 <= din_r5; + din_r21 <= din_r13; + din_r29 <= din_r21; + + din_r14 <= din_r6; + din_r22 <= din_r14; + din_r30 <= din_r22; + + din_r15 <= din_r7; + din_r23 <= din_r15; + din_r31 <= din_r23; + + din_r16 <= din_r8; + din_r24 <= din_r16; + din_r32 <= din_r24; + + + end + + + + +DUC_HB4 inst0_duc_hb4( + .clk (clkl), + .rstn (rstn), + .din_0 (din7), + .din_1 (din6), + .din_2 (din5), + .din_3 (din4), //dout_p0 + .din_4 (din3), + .din_5 (din2), + .dout (dout_p1) + ); + + +assign dout_p0 = din_r28; + + +DUC_HB4 inst1_duc_hb4( + .clk (clkl), + .rstn (rstn), + .din_0 (din6), + .din_1 (din5), + .din_2 (din4), + .din_3 (din3), //dout_p2 + .din_4 (din2), + .din_5 (din1), + .dout (dout_p3) + ); + + +assign dout_p2 = din_r29; + +DUC_HB4 inst2_duc_hb4( + .clk (clkl), + .rstn (rstn), + .din_0 (din5), + .din_1 (din4), + .din_2 (din3), + .din_3 (din2), //dout_p4 + .din_4 (din1), + .din_5 (din0), + .dout (dout_p5) + ); + + +assign dout_p4 = din_r30; + +DUC_HB4 inst3_duc_hb4( + .clk (clkl), + .rstn (rstn), + .din_0 (din4), + .din_1 (din3), + .din_2 (din2), + .din_3 (din1), //dout_p6 + .din_4 (din0), + .din_5 (din_r1), + .dout (dout_p7) + ); + + +assign dout_p6 = din_r31; + +DUC_HB4 inst4_duc_hb4( + .clk (clkl), + .rstn (rstn), + .din_0 (din3), + .din_1 (din2), + .din_2 (din1), + .din_3 (din0), //dout_p6 + .din_4 (din_r1), + .din_5 (din_r2), + .dout (dout_p9) + ); + + +assign dout_p8 = din_r32; + +DUC_HB4 inst5_duc_hb4( + .clk (clkl), + .rstn (rstn), + .din_0 (din2), + .din_1 (din1), + .din_2 (din0), + .din_3 (din_r1), //dout_p6 + .din_4 (din_r2), + .din_5 (din_r3), + .dout (dout_pb) + ); + + +assign dout_pa = din_r33; + +DUC_HB4 inst6_duc_hb4( + .clk (clkl), + .rstn (rstn), + .din_0 (din1), + .din_1 (din0), + .din_2 (din_r1), + .din_3 (din_r2), //dout_p6 + .din_4 (din_r3), + .din_5 (din_r4), + .dout (dout_pd) + ); + + +assign dout_pc = din_r34; + +DUC_HB4 inst7_duc_hb4( + .clk (clkl), + .rstn (rstn), + .din_0 (din0), + .din_1 (din_r1), + .din_2 (din_r2), + .din_3 (din_r3), //dout_p6 + .din_4 (din_r4), + .din_5 (din_r5), + .dout (dout_pf) + ); + + +assign dout_pe = din_r35; +endmodule + + + diff --git a/rtl/xy_dsp/qam/qam_top.v b/rtl/xy_dsp/qam/qam_top.v new file mode 100644 index 0000000..30a63e7 --- /dev/null +++ b/rtl/xy_dsp/qam/qam_top.v @@ -0,0 +1,467 @@ +//+FHDR-------------------------------------------------------------------------------------------------------- +// Company: +//----------------------------------------------------------------------------------------------------------------- +// File Name : QAM_TOP.v +// Department : +// Author : PWY +// Author's Tel : +//----------------------------------------------------------------------------------------------------------------- +// Relese History +// Version Date Author Description +// 0.4 2024-03-12 PWY +//----------------------------------------------------------------------------------------------------------------- +// Keywords : +// +//----------------------------------------------------------------------------------------------------------------- +// Parameter +// +//----------------------------------------------------------------------------------------------------------------- +// Purpose : +// +//----------------------------------------------------------------------------------------------------------------- +// Target Device: +// Tool versions: +//----------------------------------------------------------------------------------------------------------------- +// Reuse Issues +// Reset Strategy: +// Clock Domains: +// Critical Timing: +// Asynchronous I/F: +// Synthesizable (y/n): +// Other: +//-FHDR-------------------------------------------------------------------------------------------------------- +`timescale 1ns/1ns + +module QAM_TOP( + input clk + ,input rstn + ,input phase_manual_clr + ,input phase_auto_clr + ,input [47:0] fcw + ,input [15:0] pha + + ,input [1 :0] qam_mod //2'b00:bypass;2'b01:mix; + //2'b10:cos;2'b11:sin; + ,input sel_sideband + + ,input din_vld + ,input mix_enable + ,output dout_vld + + ,input [15:0] din_i_0 + ,input [15:0] din_i_1 + ,input [15:0] din_i_2 + ,input [15:0] din_i_3 + ,input [15:0] din_i_4 + ,input [15:0] din_i_5 + ,input [15:0] din_i_6 + ,input [15:0] din_i_7 + ,input [15:0] din_i_8 + ,input [15:0] din_i_9 + ,input [15:0] din_i_10 + ,input [15:0] din_i_11 + ,input [15:0] din_i_12 + ,input [15:0] din_i_13 + ,input [15:0] din_i_14 + ,input [15:0] din_i_15 + + ,input [15:0] din_q_0 + ,input [15:0] din_q_1 + ,input [15:0] din_q_2 + ,input [15:0] din_q_3 + ,input [15:0] din_q_4 + ,input [15:0] din_q_5 + ,input [15:0] din_q_6 + ,input [15:0] din_q_7 + ,input [15:0] din_q_8 + ,input [15:0] din_q_9 + ,input [15:0] din_q_10 + ,input [15:0] din_q_11 + ,input [15:0] din_q_12 + ,input [15:0] din_q_13 + ,input [15:0] din_q_14 + ,input [15:0] din_q_15 + + ,output [15:0] dout_i_0 + ,output [15:0] dout_i_1 + ,output [15:0] dout_i_2 + ,output [15:0] dout_i_3 + ,output [15:0] dout_i_4 + ,output [15:0] dout_i_5 + ,output [15:0] dout_i_6 + ,output [15:0] dout_i_7 + ,output [15:0] dout_i_8 + ,output [15:0] dout_i_9 + ,output [15:0] dout_i_10 + ,output [15:0] dout_i_11 + ,output [15:0] dout_i_12 + ,output [15:0] dout_i_13 + ,output [15:0] dout_i_14 + ,output [15:0] dout_i_15 + ); + + + +wire [15:0] cos_0; +wire [15:0] cos_1; +wire [15:0] cos_2; +wire [15:0] cos_3; +wire [15:0] cos_4; +wire [15:0] cos_5; +wire [15:0] cos_6; +wire [15:0] cos_7; +wire [15:0] cos_8; +wire [15:0] cos_9; +wire [15:0] cos_10; +wire [15:0] cos_11; +wire [15:0] cos_12; +wire [15:0] cos_13; +wire [15:0] cos_14; +wire [15:0] cos_15; +wire [15:0] sin_0; +wire [15:0] sin_1; +wire [15:0] sin_2; +wire [15:0] sin_3; +wire [15:0] sin_4; +wire [15:0] sin_5; +wire [15:0] sin_6; +wire [15:0] sin_7; +wire [15:0] sin_8; +wire [15:0] sin_9; +wire [15:0] sin_10; +wire [15:0] sin_11; +wire [15:0] sin_12; +wire [15:0] sin_13; +wire [15:0] sin_14; +wire [15:0] sin_15; + + +NCO inst_nco_0 ( + .clk ( clk ) + ,.rstn ( rstn ) + ,.phase_manual_clr ( phase_manual_clr ) + ,.phase_auto_clr ( phase_auto_clr ) + ,.fcw ( fcw ) + ,.pha ( pha ) + ,.cos_0 ( cos_0 ) + ,.cos_1 ( cos_1 ) + ,.cos_2 ( cos_2 ) + ,.cos_3 ( cos_3 ) + ,.cos_4 ( cos_4 ) + ,.cos_5 ( cos_5 ) + ,.cos_6 ( cos_6 ) + ,.cos_7 ( cos_7 ) + ,.cos_8 ( cos_8 ) + ,.cos_9 ( cos_9 ) + ,.cos_10 ( cos_10 ) + ,.cos_11 ( cos_11 ) + ,.cos_12 ( cos_12 ) + ,.cos_13 ( cos_13 ) + ,.cos_14 ( cos_14 ) + ,.cos_15 ( cos_15 ) + + ,.sin_0 ( sin_0 ) + ,.sin_1 ( sin_1 ) + ,.sin_2 ( sin_2 ) + ,.sin_3 ( sin_3 ) + ,.sin_4 ( sin_4 ) + ,.sin_5 ( sin_5 ) + ,.sin_6 ( sin_6 ) + ,.sin_7 ( sin_7 ) + ,.sin_8 ( sin_8 ) + ,.sin_9 ( sin_9 ) + ,.sin_10 ( sin_10 ) + ,.sin_11 ( sin_11 ) + ,.sin_12 ( sin_12 ) + ,.sin_13 ( sin_13 ) + ,.sin_14 ( sin_14 ) + ,.sin_15 ( sin_15 ) + ); + +wire [15:0] dt_i_0; +wire [15:0] dt_i_1; +wire [15:0] dt_i_2; +wire [15:0] dt_i_3; +wire [15:0] dt_i_4; +wire [15:0] dt_i_5; +wire [15:0] dt_i_6; +wire [15:0] dt_i_7; +wire [15:0] dt_i_8; +wire [15:0] dt_i_9; +wire [15:0] dt_i_10; +wire [15:0] dt_i_11; +wire [15:0] dt_i_12; +wire [15:0] dt_i_13; +wire [15:0] dt_i_14; +wire [15:0] dt_i_15; + + + +wire mix_dout_vld; + +SSB inst_ssb_i ( + .clk ( clk ) + ,.rstn ( rstn ) + ,.sel_sideband ( sel_sideband ) + ,.mix_enable ( mix_enable ) + ,.din_vld ( din_vld ) + ,.dout_vld ( mix_dout_vld ) + + ,.din_i0 ( din_i_0 ) + ,.din_i1 ( din_i_1 ) + ,.din_i2 ( din_i_2 ) + ,.din_i3 ( din_i_3 ) + ,.din_i4 ( din_i_4 ) + ,.din_i5 ( din_i_5 ) + ,.din_i6 ( din_i_6 ) + ,.din_i7 ( din_i_7 ) + ,.din_i8 ( din_i_8 ) + ,.din_i9 ( din_i_9 ) + ,.din_i10 ( din_i_10 ) + ,.din_i11 ( din_i_11 ) + ,.din_i12 ( din_i_12 ) + ,.din_i13 ( din_i_13 ) + ,.din_i14 ( din_i_14 ) + ,.din_i15 ( din_i_15 ) + + ,.din_q0 ( din_q_0 ) + ,.din_q1 ( din_q_1 ) + ,.din_q2 ( din_q_2 ) + ,.din_q3 ( din_q_3 ) + ,.din_q4 ( din_q_4 ) + ,.din_q5 ( din_q_5 ) + ,.din_q6 ( din_q_6 ) + ,.din_q7 ( din_q_7 ) + ,.din_q8 ( din_q_8 ) + ,.din_q9 ( din_q_9 ) + ,.din_q10 ( din_q_10 ) + ,.din_q11 ( din_q_11 ) + ,.din_q12 ( din_q_12 ) + ,.din_q13 ( din_q_13 ) + ,.din_q14 ( din_q_14 ) + ,.din_q15 ( din_q_15 ) + + ,.cos_0 ( cos_0 ) + ,.cos_1 ( cos_1 ) + ,.cos_2 ( cos_2 ) + ,.cos_3 ( cos_3 ) + ,.cos_4 ( cos_4 ) + ,.cos_5 ( cos_5 ) + ,.cos_6 ( cos_6 ) + ,.cos_7 ( cos_7 ) + ,.cos_8 ( cos_8 ) + ,.cos_9 ( cos_9 ) + ,.cos_10 ( cos_10 ) + ,.cos_11 ( cos_11 ) + ,.cos_12 ( cos_12 ) + ,.cos_13 ( cos_13 ) + ,.cos_14 ( cos_14 ) + ,.cos_15 ( cos_15 ) + + ,.sin_0 ( sin_0 ) + ,.sin_1 ( sin_1 ) + ,.sin_2 ( sin_2 ) + ,.sin_3 ( sin_3 ) + ,.sin_4 ( sin_4 ) + ,.sin_5 ( sin_5 ) + ,.sin_6 ( sin_6 ) + ,.sin_7 ( sin_7 ) + ,.sin_8 ( sin_8 ) + ,.sin_9 ( sin_9 ) + ,.sin_10 ( sin_10 ) + ,.sin_11 ( sin_11 ) + ,.sin_12 ( sin_12 ) + ,.sin_13 ( sin_13 ) + ,.sin_14 ( sin_14 ) + ,.sin_15 ( sin_15 ) + + ,.dout_0 ( dt_i_0 ) + ,.dout_1 ( dt_i_1 ) + ,.dout_2 ( dt_i_2 ) + ,.dout_3 ( dt_i_3 ) + ,.dout_4 ( dt_i_4 ) + ,.dout_5 ( dt_i_5 ) + ,.dout_6 ( dt_i_6 ) + ,.dout_7 ( dt_i_7 ) + ,.dout_8 ( dt_i_8 ) + ,.dout_9 ( dt_i_9 ) + ,.dout_10 ( dt_i_10 ) + ,.dout_11 ( dt_i_11 ) + ,.dout_12 ( dt_i_12 ) + ,.dout_13 ( dt_i_13 ) + ,.dout_14 ( dt_i_14 ) + ,.dout_15 ( dt_i_15 ) + + ); + + +reg [15:0] dout_i_r0; +reg [15:0] dout_i_r1; +reg [15:0] dout_i_r2; +reg [15:0] dout_i_r3; +reg [15:0] dout_i_r4; +reg [15:0] dout_i_r5; +reg [15:0] dout_i_r6; +reg [15:0] dout_i_r7; +reg [15:0] dout_i_r8; +reg [15:0] dout_i_r9; +reg [15:0] dout_i_r10; +reg [15:0] dout_i_r11; +reg [15:0] dout_i_r12; +reg [15:0] dout_i_r13; +reg [15:0] dout_i_r14; +reg [15:0] dout_i_r15; + +wire dout_vld_w = (qam_mod == 2'b00) ? din_vld : + (qam_mod == 2'b01) ? mix_dout_vld : + 1'b1 ; + + +always@(posedge clk or negedge rstn) begin + if(!rstn) begin + dout_i_r0 <= 16'h0; + dout_i_r1 <= 16'h0; + dout_i_r2 <= 16'h0; + dout_i_r3 <= 16'h0; + dout_i_r4 <= 16'h0; + dout_i_r5 <= 16'h0; + dout_i_r6 <= 16'h0; + dout_i_r7 <= 16'h0; + dout_i_r8 <= 16'h0; + dout_i_r9 <= 16'h0; + dout_i_r10 <= 16'h0; + dout_i_r11 <= 16'h0; + dout_i_r12 <= 16'h0; + dout_i_r13 <= 16'h0; + dout_i_r14 <= 16'h0; + dout_i_r15 <= 16'h0; + end + else if(dout_vld_w) begin + case(qam_mod) + 2'b00 : begin + dout_i_r0 <= din_i_0; + dout_i_r1 <= din_i_1; + dout_i_r2 <= din_i_2; + dout_i_r3 <= din_i_3; + dout_i_r4 <= din_i_4; + dout_i_r5 <= din_i_5; + dout_i_r6 <= din_i_6; + dout_i_r7 <= din_i_7; + dout_i_r8 <= din_i_8; + dout_i_r9 <= din_i_9; + dout_i_r10 <= din_i_10; + dout_i_r11 <= din_i_11; + dout_i_r12 <= din_i_12; + dout_i_r13 <= din_i_13; + dout_i_r14 <= din_i_14; + dout_i_r15 <= din_i_15; + end + 2'b01 : begin + dout_i_r0 <= dt_i_0; + dout_i_r1 <= dt_i_1; + dout_i_r2 <= dt_i_2; + dout_i_r3 <= dt_i_3; + dout_i_r4 <= dt_i_4; + dout_i_r5 <= dt_i_5; + dout_i_r6 <= dt_i_6; + dout_i_r7 <= dt_i_7; + dout_i_r8 <= dt_i_8; + dout_i_r9 <= dt_i_9; + dout_i_r10 <= dt_i_10; + dout_i_r11 <= dt_i_11; + dout_i_r12 <= dt_i_12; + dout_i_r13 <= dt_i_13; + dout_i_r14 <= dt_i_14; + dout_i_r15 <= dt_i_15; + end + 2'b10 : begin + dout_i_r0 <= cos_0; + dout_i_r1 <= cos_1; + dout_i_r2 <= cos_2; + dout_i_r3 <= cos_3; + dout_i_r4 <= cos_4; + dout_i_r5 <= cos_5; + dout_i_r6 <= cos_6; + dout_i_r7 <= cos_7; + dout_i_r8 <= cos_8; + dout_i_r9 <= cos_9; + dout_i_r10 <= cos_10; + dout_i_r11 <= cos_11; + dout_i_r12 <= cos_12; + dout_i_r13 <= cos_13; + dout_i_r14 <= cos_14; + dout_i_r15 <= cos_15; + end + default : begin + dout_i_r0 <= din_q_0 ; + dout_i_r1 <= din_q_1 ; + dout_i_r2 <= din_q_2 ; + dout_i_r3 <= din_q_3 ; + dout_i_r4 <= din_q_4 ; + dout_i_r5 <= din_q_5 ; + dout_i_r6 <= din_q_6 ; + dout_i_r7 <= din_q_7 ; + dout_i_r8 <= din_q_8 ; + dout_i_r9 <= din_q_9 ; + dout_i_r10 <= din_q_10 ; + dout_i_r11 <= din_q_11 ; + dout_i_r12 <= din_q_12 ; + dout_i_r13 <= din_q_13 ; + dout_i_r14 <= din_q_14 ; + dout_i_r15 <= din_q_15 ; + end + endcase + end + else begin + dout_i_r0 <= 16'h0; + dout_i_r1 <= 16'h0; + dout_i_r2 <= 16'h0; + dout_i_r3 <= 16'h0; + dout_i_r4 <= 16'h0; + dout_i_r5 <= 16'h0; + dout_i_r6 <= 16'h0; + dout_i_r7 <= 16'h0; + dout_i_r8 <= 16'h0; + dout_i_r9 <= 16'h0; + dout_i_r10 <= 16'h0; + dout_i_r11 <= 16'h0; + dout_i_r12 <= 16'h0; + dout_i_r13 <= 16'h0; + dout_i_r14 <= 16'h0; + dout_i_r15 <= 16'h0; + end +end + + +assign dout_i_0 = dout_i_r0 ; +assign dout_i_1 = dout_i_r1 ; +assign dout_i_2 = dout_i_r2 ; +assign dout_i_3 = dout_i_r3 ; +assign dout_i_4 = dout_i_r4 ; +assign dout_i_5 = dout_i_r5 ; +assign dout_i_6 = dout_i_r6 ; +assign dout_i_7 = dout_i_r7 ; +assign dout_i_8 = dout_i_r8 ; +assign dout_i_9 = dout_i_r9 ; +assign dout_i_10 = dout_i_r10 ; +assign dout_i_11 = dout_i_r11 ; +assign dout_i_12 = dout_i_r12 ; +assign dout_i_13 = dout_i_r13 ; +assign dout_i_14 = dout_i_r14 ; +assign dout_i_15 = dout_i_r15 ; + + +reg dout_vld_r; + +always @(posedge clk or negedge rstn) begin + if(rstn == 1'b0) begin + dout_vld_r <= 1'b0; + end + else begin + dout_vld_r <= dout_vld_w; + end +end + +assign dout_vld = dout_vld_r; + +endmodule diff --git a/rtl/xy_dsp/qam/ssb.v b/rtl/xy_dsp/qam/ssb.v new file mode 100644 index 0000000..21630c6 --- /dev/null +++ b/rtl/xy_dsp/qam/ssb.v @@ -0,0 +1,614 @@ +//+FHDR-------------------------------------------------------------------------------------------------------- +// Company: +//----------------------------------------------------------------------------------------------------------------- +// File Name : SSB.v +// Department : +// Author : PWY +// Author's Tel : +//----------------------------------------------------------------------------------------------------------------- +// Relese History +// Version Date Author Description +// 0.4 2024-03-12 PWY +//----------------------------------------------------------------------------------------------------------------- +// Keywords : +// +//----------------------------------------------------------------------------------------------------------------- +// Parameter +// +//----------------------------------------------------------------------------------------------------------------- +// Purpose : +// +//----------------------------------------------------------------------------------------------------------------- +// Target Device: +// Tool versions: +//----------------------------------------------------------------------------------------------------------------- +// Reuse Issues +// Reset Strategy: +// Clock Domains: +// Critical Timing: +// Asynchronous I/F: +// Synthesizable (y/n): +// Other: +//-FHDR-------------------------------------------------------------------------------------------------------- +module SSB( + input clk, + input rstn, + input sel_sideband, + + input din_vld, + input mix_enable, + output dout_vld, + + input signed [15:0] din_i0, + input signed [15:0] din_i1, + input signed [15:0] din_i2, + input signed [15:0] din_i3, + input signed [15:0] din_i4, + input signed [15:0] din_i5, + input signed [15:0] din_i6, + input signed [15:0] din_i7, + input signed [15:0] din_i8, + input signed [15:0] din_i9, + input signed [15:0] din_i10, + input signed [15:0] din_i11, + input signed [15:0] din_i12, + input signed [15:0] din_i13, + input signed [15:0] din_i14, + input signed [15:0] din_i15, + + + input signed [15:0] din_q0, + input signed [15:0] din_q1, + input signed [15:0] din_q2, + input signed [15:0] din_q3, + input signed [15:0] din_q4, + input signed [15:0] din_q5, + input signed [15:0] din_q6, + input signed [15:0] din_q7, + input signed [15:0] din_q8, + input signed [15:0] din_q9, + input signed [15:0] din_q10, + input signed [15:0] din_q11, + input signed [15:0] din_q12, + input signed [15:0] din_q13, + input signed [15:0] din_q14, + input signed [15:0] din_q15, + + input signed [15:0] cos_0, + input signed [15:0] cos_1, + input signed [15:0] cos_2, + input signed [15:0] cos_3, + input signed [15:0] cos_4, + input signed [15:0] cos_5, + input signed [15:0] cos_6, + input signed [15:0] cos_7, + input signed [15:0] cos_8, + input signed [15:0] cos_9, + input signed [15:0] cos_10, + input signed [15:0] cos_11, + input signed [15:0] cos_12, + input signed [15:0] cos_13, + input signed [15:0] cos_14, + input signed [15:0] cos_15, + + input signed [15:0] sin_0, + input signed [15:0] sin_1, + input signed [15:0] sin_2, + input signed [15:0] sin_3, + input signed [15:0] sin_4, + input signed [15:0] sin_5, + input signed [15:0] sin_6, + input signed [15:0] sin_7, + input signed [15:0] sin_8, + input signed [15:0] sin_9, + input signed [15:0] sin_10, + input signed [15:0] sin_11, + input signed [15:0] sin_12, + input signed [15:0] sin_13, + input signed [15:0] sin_14, + input signed [15:0] sin_15, + + + output signed [15:0] dout_0, + output signed [15:0] dout_1, + output signed [15:0] dout_2, + output signed [15:0] dout_3, + output signed [15:0] dout_4, + output signed [15:0] dout_5, + output signed [15:0] dout_6, + output signed [15:0] dout_7, + output signed [15:0] dout_8, + output signed [15:0] dout_9, + output signed [15:0] dout_10, + output signed [15:0] dout_11, + output signed [15:0] dout_12, + output signed [15:0] dout_13, + output signed [15:0] dout_14, + output signed [15:0] dout_15 + ); + +reg [3:0]mix_data_vld_dly; + +wire signed [31:0] mult_icos0_tmp; +wire signed [31:0] mult_icos1_tmp; +wire signed [31:0] mult_icos2_tmp; +wire signed [31:0] mult_icos3_tmp; +wire signed [31:0] mult_icos4_tmp; +wire signed [31:0] mult_icos5_tmp; +wire signed [31:0] mult_icos6_tmp; +wire signed [31:0] mult_icos7_tmp; +wire signed [31:0] mult_icos8_tmp; +wire signed [31:0] mult_icos9_tmp; +wire signed [31:0] mult_icos10_tmp; +wire signed [31:0] mult_icos11_tmp; +wire signed [31:0] mult_icos12_tmp; +wire signed [31:0] mult_icos13_tmp; +wire signed [31:0] mult_icos14_tmp; +wire signed [31:0] mult_icos15_tmp; + +DW_mult_pipe #(16,16,3,0,1) inst_icos0_mult(.clk(clk),.rst_n(rstn),.en(1'b1),.a(din_i0),.b(cos_0),.tc(1'b1),.product(mult_icos0_tmp)); +DW_mult_pipe #(16,16,3,0,1) inst_icos1_mult(.clk(clk),.rst_n(rstn),.en(1'b1),.a(din_i1),.b(cos_1),.tc(1'b1),.product(mult_icos1_tmp)); +DW_mult_pipe #(16,16,3,0,1) inst_icos2_mult(.clk(clk),.rst_n(rstn),.en(1'b1),.a(din_i2),.b(cos_2),.tc(1'b1),.product(mult_icos2_tmp)); +DW_mult_pipe #(16,16,3,0,1) inst_icos3_mult(.clk(clk),.rst_n(rstn),.en(1'b1),.a(din_i3),.b(cos_3),.tc(1'b1),.product(mult_icos3_tmp)); +DW_mult_pipe #(16,16,3,0,1) inst_icos4_mult(.clk(clk),.rst_n(rstn),.en(1'b1),.a(din_i4),.b(cos_4),.tc(1'b1),.product(mult_icos4_tmp)); +DW_mult_pipe #(16,16,3,0,1) inst_icos5_mult(.clk(clk),.rst_n(rstn),.en(1'b1),.a(din_i5),.b(cos_5),.tc(1'b1),.product(mult_icos5_tmp)); +DW_mult_pipe #(16,16,3,0,1) inst_icos6_mult(.clk(clk),.rst_n(rstn),.en(1'b1),.a(din_i6),.b(cos_6),.tc(1'b1),.product(mult_icos6_tmp)); +DW_mult_pipe #(16,16,3,0,1) inst_icos7_mult(.clk(clk),.rst_n(rstn),.en(1'b1),.a(din_i7),.b(cos_7),.tc(1'b1),.product(mult_icos7_tmp)); +DW_mult_pipe #(16,16,3,0,1) inst_icos8_mult(.clk(clk),.rst_n(rstn),.en(1'b1),.a(din_i8),.b(cos_8),.tc(1'b1),.product(mult_icos8_tmp)); +DW_mult_pipe #(16,16,3,0,1) inst_icos9_mult(.clk(clk),.rst_n(rstn),.en(1'b1),.a(din_i9),.b(cos_9),.tc(1'b1),.product(mult_icos9_tmp)); +DW_mult_pipe #(16,16,3,0,1) inst_icos10_mult(.clk(clk),.rst_n(rstn),.en(1'b1),.a(din_i10),.b(cos_10),.tc(1'b1),.product(mult_icos10_tmp)); +DW_mult_pipe #(16,16,3,0,1) inst_icos11_mult(.clk(clk),.rst_n(rstn),.en(1'b1),.a(din_i11),.b(cos_11),.tc(1'b1),.product(mult_icos11_tmp)); +DW_mult_pipe #(16,16,3,0,1) inst_icos12_mult(.clk(clk),.rst_n(rstn),.en(1'b1),.a(din_i12),.b(cos_12),.tc(1'b1),.product(mult_icos12_tmp)); +DW_mult_pipe #(16,16,3,0,1) inst_icos13_mult(.clk(clk),.rst_n(rstn),.en(1'b1),.a(din_i13),.b(cos_13),.tc(1'b1),.product(mult_icos13_tmp)); +DW_mult_pipe #(16,16,3,0,1) inst_icos14_mult(.clk(clk),.rst_n(rstn),.en(1'b1),.a(din_i14),.b(cos_14),.tc(1'b1),.product(mult_icos14_tmp)); +DW_mult_pipe #(16,16,3,0,1) inst_icos15_mult(.clk(clk),.rst_n(rstn),.en(1'b1),.a(din_i15),.b(cos_15),.tc(1'b1),.product(mult_icos15_tmp)); + + +wire signed [31:0] mult_qsin0_tmp; +wire signed [31:0] mult_qsin1_tmp; +wire signed [31:0] mult_qsin2_tmp; +wire signed [31:0] mult_qsin3_tmp; +wire signed [31:0] mult_qsin4_tmp; +wire signed [31:0] mult_qsin5_tmp; +wire signed [31:0] mult_qsin6_tmp; +wire signed [31:0] mult_qsin7_tmp; +wire signed [31:0] mult_qsin8_tmp; +wire signed [31:0] mult_qsin9_tmp; +wire signed [31:0] mult_qsin10_tmp; +wire signed [31:0] mult_qsin11_tmp; +wire signed [31:0] mult_qsin12_tmp; +wire signed [31:0] mult_qsin13_tmp; +wire signed [31:0] mult_qsin14_tmp; +wire signed [31:0] mult_qsin15_tmp; + + + +DW_mult_pipe #(16,16,3,0,1) inst_qsin0_mult(.clk(clk),.rst_n(rstn),.en(1'b1),.a(din_q0),.b(sin_0),.tc(1'b1),.product(mult_qsin0_tmp)); +DW_mult_pipe #(16,16,3,0,1) inst_qsin1_mult(.clk(clk),.rst_n(rstn),.en(1'b1),.a(din_q1),.b(sin_1),.tc(1'b1),.product(mult_qsin1_tmp)); +DW_mult_pipe #(16,16,3,0,1) inst_qsin2_mult(.clk(clk),.rst_n(rstn),.en(1'b1),.a(din_q2),.b(sin_2),.tc(1'b1),.product(mult_qsin2_tmp)); +DW_mult_pipe #(16,16,3,0,1) inst_qsin3_mult(.clk(clk),.rst_n(rstn),.en(1'b1),.a(din_q3),.b(sin_3),.tc(1'b1),.product(mult_qsin3_tmp)); +DW_mult_pipe #(16,16,3,0,1) inst_qsin4_mult(.clk(clk),.rst_n(rstn),.en(1'b1),.a(din_q4),.b(sin_4),.tc(1'b1),.product(mult_qsin4_tmp)); +DW_mult_pipe #(16,16,3,0,1) inst_qsin5_mult(.clk(clk),.rst_n(rstn),.en(1'b1),.a(din_q5),.b(sin_5),.tc(1'b1),.product(mult_qsin5_tmp)); +DW_mult_pipe #(16,16,3,0,1) inst_qsin6_mult(.clk(clk),.rst_n(rstn),.en(1'b1),.a(din_q6),.b(sin_6),.tc(1'b1),.product(mult_qsin6_tmp)); +DW_mult_pipe #(16,16,3,0,1) inst_qsin7_mult(.clk(clk),.rst_n(rstn),.en(1'b1),.a(din_q7),.b(sin_7),.tc(1'b1),.product(mult_qsin7_tmp)); +DW_mult_pipe #(16,16,3,0,1) inst_qsin8_mult(.clk(clk),.rst_n(rstn),.en(1'b1),.a(din_q8),.b(sin_8),.tc(1'b1),.product(mult_qsin8_tmp)); +DW_mult_pipe #(16,16,3,0,1) inst_qsin9_mult(.clk(clk),.rst_n(rstn),.en(1'b1),.a(din_q9),.b(sin_9),.tc(1'b1),.product(mult_qsin9_tmp)); +DW_mult_pipe #(16,16,3,0,1) inst_qsin10_mult(.clk(clk),.rst_n(rstn),.en(1'b1),.a(din_q10),.b(sin_10),.tc(1'b1),.product(mult_qsin10_tmp)); +DW_mult_pipe #(16,16,3,0,1) inst_qsin11_mult(.clk(clk),.rst_n(rstn),.en(1'b1),.a(din_q11),.b(sin_11),.tc(1'b1),.product(mult_qsin11_tmp)); +DW_mult_pipe #(16,16,3,0,1) inst_qsin12_mult(.clk(clk),.rst_n(rstn),.en(1'b1),.a(din_q12),.b(sin_12),.tc(1'b1),.product(mult_qsin12_tmp)); +DW_mult_pipe #(16,16,3,0,1) inst_qsin13_mult(.clk(clk),.rst_n(rstn),.en(1'b1),.a(din_q13),.b(sin_13),.tc(1'b1),.product(mult_qsin13_tmp)); +DW_mult_pipe #(16,16,3,0,1) inst_qsin14_mult(.clk(clk),.rst_n(rstn),.en(1'b1),.a(din_q14),.b(sin_14),.tc(1'b1),.product(mult_qsin14_tmp)); +DW_mult_pipe #(16,16,3,0,1) inst_qsin15_mult(.clk(clk),.rst_n(rstn),.en(1'b1),.a(din_q15),.b(sin_15),.tc(1'b1),.product(mult_qsin15_tmp)); + + +reg signed [15:0] mult_icos0; +reg signed [15:0] mult_icos1; +reg signed [15:0] mult_icos2; +reg signed [15:0] mult_icos3; +reg signed [15:0] mult_icos4; +reg signed [15:0] mult_icos5; +reg signed [15:0] mult_icos6; +reg signed [15:0] mult_icos7; +reg signed [15:0] mult_icos8; +reg signed [15:0] mult_icos9; +reg signed [15:0] mult_icos10; +reg signed [15:0] mult_icos11; +reg signed [15:0] mult_icos12; +reg signed [15:0] mult_icos13; +reg signed [15:0] mult_icos14; +reg signed [15:0] mult_icos15; + + +wire signed [15:0] mult_icos0_w; +wire signed [15:0] mult_icos1_w; +wire signed [15:0] mult_icos2_w; +wire signed [15:0] mult_icos3_w; +wire signed [15:0] mult_icos4_w; +wire signed [15:0] mult_icos5_w; +wire signed [15:0] mult_icos6_w; +wire signed [15:0] mult_icos7_w; +wire signed [15:0] mult_icos8_w; +wire signed [15:0] mult_icos9_w; +wire signed [15:0] mult_icos10_w; +wire signed [15:0] mult_icos11_w; +wire signed [15:0] mult_icos12_w; +wire signed [15:0] mult_icos13_w; +wire signed [15:0] mult_icos14_w; +wire signed [15:0] mult_icos15_w; + +assign mult_icos0_w = mult_icos0_tmp[14] ? {mult_icos0_tmp[31] , mult_icos0_tmp[29:15] } + 16'd1 : {mult_icos0_tmp[31] , mult_icos0_tmp[29:15] }; +assign mult_icos1_w = mult_icos1_tmp[14] ? {mult_icos1_tmp[31] , mult_icos1_tmp[29:15] } + 16'd1 : {mult_icos1_tmp[31] , mult_icos1_tmp[29:15] }; +assign mult_icos2_w = mult_icos2_tmp[14] ? {mult_icos2_tmp[31] , mult_icos2_tmp[29:15] } + 16'd1 : {mult_icos2_tmp[31] , mult_icos2_tmp[29:15] }; +assign mult_icos3_w = mult_icos3_tmp[14] ? {mult_icos3_tmp[31] , mult_icos3_tmp[29:15] } + 16'd1 : {mult_icos3_tmp[31] , mult_icos3_tmp[29:15] }; +assign mult_icos4_w = mult_icos4_tmp[14] ? {mult_icos4_tmp[31] , mult_icos4_tmp[29:15] } + 16'd1 : {mult_icos4_tmp[31] , mult_icos4_tmp[29:15] }; +assign mult_icos5_w = mult_icos5_tmp[14] ? {mult_icos5_tmp[31] , mult_icos5_tmp[29:15] } + 16'd1 : {mult_icos5_tmp[31] , mult_icos5_tmp[29:15] }; +assign mult_icos6_w = mult_icos6_tmp[14] ? {mult_icos6_tmp[31] , mult_icos6_tmp[29:15] } + 16'd1 : {mult_icos6_tmp[31] , mult_icos6_tmp[29:15] }; +assign mult_icos7_w = mult_icos7_tmp[14] ? {mult_icos7_tmp[31] , mult_icos7_tmp[29:15] } + 16'd1 : {mult_icos7_tmp[31] , mult_icos7_tmp[29:15] }; +assign mult_icos8_w = mult_icos8_tmp[14] ? {mult_icos8_tmp[31] , mult_icos8_tmp[29:15] } + 16'd1 : {mult_icos8_tmp[31] , mult_icos8_tmp[29:15] }; +assign mult_icos9_w = mult_icos9_tmp[14] ? {mult_icos9_tmp[31] , mult_icos9_tmp[29:15] } + 16'd1 : {mult_icos9_tmp[31] , mult_icos9_tmp[29:15] }; +assign mult_icos10_w =mult_icos10_tmp[14]? {mult_icos10_tmp[31], mult_icos10_tmp[29:15]} + 16'd1 : {mult_icos10_tmp[31], mult_icos10_tmp[29:15]}; +assign mult_icos11_w =mult_icos11_tmp[14]? {mult_icos11_tmp[31], mult_icos11_tmp[29:15]} + 16'd1 : {mult_icos11_tmp[31], mult_icos11_tmp[29:15]}; +assign mult_icos12_w =mult_icos12_tmp[14]? {mult_icos12_tmp[31], mult_icos12_tmp[29:15]} + 16'd1 : {mult_icos12_tmp[31], mult_icos12_tmp[29:15]}; +assign mult_icos13_w =mult_icos13_tmp[14]? {mult_icos13_tmp[31], mult_icos13_tmp[29:15]} + 16'd1 : {mult_icos13_tmp[31], mult_icos13_tmp[29:15]}; +assign mult_icos14_w =mult_icos14_tmp[14]? {mult_icos14_tmp[31], mult_icos14_tmp[29:15]} + 16'd1 : {mult_icos14_tmp[31], mult_icos14_tmp[29:15]}; +assign mult_icos15_w =mult_icos15_tmp[14]? {mult_icos15_tmp[31], mult_icos15_tmp[29:15]} + 16'd1 : {mult_icos15_tmp[31], mult_icos15_tmp[29:15]}; + + +always@(posedge clk)begin + if(mix_data_vld_dly[1]) + begin + mult_icos0 <= mult_icos0_w; + mult_icos1 <= mult_icos1_w; + mult_icos2 <= mult_icos2_w; + mult_icos3 <= mult_icos3_w; + mult_icos4 <= mult_icos4_w; + mult_icos5 <= mult_icos5_w; + mult_icos6 <= mult_icos6_w; + mult_icos7 <= mult_icos7_w; + mult_icos8 <= mult_icos8_w; + mult_icos9 <= mult_icos9_w; + mult_icos10 <= mult_icos10_w; + mult_icos11 <= mult_icos11_w; + mult_icos12 <= mult_icos12_w; + mult_icos13 <= mult_icos13_w; + mult_icos14 <= mult_icos14_w; + mult_icos15 <= mult_icos15_w; + end + else + begin + mult_icos0 <= 16'b0; + mult_icos1 <= 16'b0; + mult_icos2 <= 16'b0; + mult_icos3 <= 16'b0; + mult_icos4 <= 16'b0; + mult_icos5 <= 16'b0; + mult_icos6 <= 16'b0; + mult_icos7 <= 16'b0; + mult_icos8 <= 16'b0; + mult_icos9 <= 16'b0; + mult_icos10 <= 16'b0; + mult_icos11 <= 16'b0; + mult_icos12 <= 16'b0; + mult_icos13 <= 16'b0; + mult_icos14 <= 16'b0; + mult_icos15 <= 16'b0; + end +end + +reg signed [15:0] mult_qsin0; +reg signed [15:0] mult_qsin1; +reg signed [15:0] mult_qsin2; +reg signed [15:0] mult_qsin3; +reg signed [15:0] mult_qsin4; +reg signed [15:0] mult_qsin5; +reg signed [15:0] mult_qsin6; +reg signed [15:0] mult_qsin7; +reg signed [15:0] mult_qsin8; +reg signed [15:0] mult_qsin9; +reg signed [15:0] mult_qsin10; +reg signed [15:0] mult_qsin11; +reg signed [15:0] mult_qsin12; +reg signed [15:0] mult_qsin13; +reg signed [15:0] mult_qsin14; +reg signed [15:0] mult_qsin15; + + +wire signed [15:0] mult_qsin0_w; +wire signed [15:0] mult_qsin1_w; +wire signed [15:0] mult_qsin2_w; +wire signed [15:0] mult_qsin3_w; +wire signed [15:0] mult_qsin4_w; +wire signed [15:0] mult_qsin5_w; +wire signed [15:0] mult_qsin6_w; +wire signed [15:0] mult_qsin7_w; +wire signed [15:0] mult_qsin8_w; +wire signed [15:0] mult_qsin9_w; +wire signed [15:0] mult_qsin10_w; +wire signed [15:0] mult_qsin11_w; +wire signed [15:0] mult_qsin12_w; +wire signed [15:0] mult_qsin13_w; +wire signed [15:0] mult_qsin14_w; +wire signed [15:0] mult_qsin15_w; + +assign mult_qsin0_w = mult_qsin0_tmp[14] ? {mult_qsin0_tmp[31] , mult_qsin0_tmp[29:15] } + 16'd1 : {mult_qsin0_tmp[31] , mult_qsin0_tmp[29:15] }; +assign mult_qsin1_w = mult_qsin1_tmp[14] ? {mult_qsin1_tmp[31] , mult_qsin1_tmp[29:15] } + 16'd1 : {mult_qsin1_tmp[31] , mult_qsin1_tmp[29:15] }; +assign mult_qsin2_w = mult_qsin2_tmp[14] ? {mult_qsin2_tmp[31] , mult_qsin2_tmp[29:15] } + 16'd1 : {mult_qsin2_tmp[31] , mult_qsin2_tmp[29:15] }; +assign mult_qsin3_w = mult_qsin3_tmp[14] ? {mult_qsin3_tmp[31] , mult_qsin3_tmp[29:15] } + 16'd1 : {mult_qsin3_tmp[31] , mult_qsin3_tmp[29:15] }; +assign mult_qsin4_w = mult_qsin4_tmp[14] ? {mult_qsin4_tmp[31] , mult_qsin4_tmp[29:15] } + 16'd1 : {mult_qsin4_tmp[31] , mult_qsin4_tmp[29:15] }; +assign mult_qsin5_w = mult_qsin5_tmp[14] ? {mult_qsin5_tmp[31] , mult_qsin5_tmp[29:15] } + 16'd1 : {mult_qsin5_tmp[31] , mult_qsin5_tmp[29:15] }; +assign mult_qsin6_w = mult_qsin6_tmp[14] ? {mult_qsin6_tmp[31] , mult_qsin6_tmp[29:15] } + 16'd1 : {mult_qsin6_tmp[31] , mult_qsin6_tmp[29:15] }; +assign mult_qsin7_w = mult_qsin7_tmp[14] ? {mult_qsin7_tmp[31] , mult_qsin7_tmp[29:15] } + 16'd1 : {mult_qsin7_tmp[31] , mult_qsin7_tmp[29:15] }; +assign mult_qsin8_w = mult_qsin8_tmp[14] ? {mult_qsin8_tmp[31] , mult_qsin8_tmp[29:15] } + 16'd1 : {mult_qsin8_tmp[31] , mult_qsin8_tmp[29:15] }; +assign mult_qsin9_w = mult_qsin9_tmp[14] ? {mult_qsin9_tmp[31] , mult_qsin9_tmp[29:15] } + 16'd1 : {mult_qsin9_tmp[31] , mult_qsin9_tmp[29:15] }; +assign mult_qsin10_w = mult_qsin10_tmp[14]? {mult_qsin10_tmp[31], mult_qsin10_tmp[29:15]} + 16'd1 : {mult_qsin10_tmp[31], mult_qsin10_tmp[29:15]}; +assign mult_qsin11_w = mult_qsin11_tmp[14]? {mult_qsin11_tmp[31], mult_qsin11_tmp[29:15]} + 16'd1 : {mult_qsin11_tmp[31], mult_qsin11_tmp[29:15]}; +assign mult_qsin12_w = mult_qsin12_tmp[14]? {mult_qsin12_tmp[31], mult_qsin12_tmp[29:15]} + 16'd1 : {mult_qsin12_tmp[31], mult_qsin12_tmp[29:15]}; +assign mult_qsin13_w = mult_qsin13_tmp[14]? {mult_qsin13_tmp[31], mult_qsin13_tmp[29:15]} + 16'd1 : {mult_qsin13_tmp[31], mult_qsin13_tmp[29:15]}; +assign mult_qsin14_w = mult_qsin14_tmp[14]? {mult_qsin14_tmp[31], mult_qsin14_tmp[29:15]} + 16'd1 : {mult_qsin14_tmp[31], mult_qsin14_tmp[29:15]}; +assign mult_qsin15_w = mult_qsin15_tmp[14]? {mult_qsin15_tmp[31], mult_qsin15_tmp[29:15]} + 16'd1 : {mult_qsin15_tmp[31], mult_qsin15_tmp[29:15]}; + +always@(posedge clk)begin + if(mix_data_vld_dly[1]) begin + mult_qsin0 <= mult_qsin0_w; + mult_qsin1 <= mult_qsin1_w; + mult_qsin2 <= mult_qsin2_w; + mult_qsin3 <= mult_qsin3_w; + mult_qsin4 <= mult_qsin4_w; + mult_qsin5 <= mult_qsin5_w; + mult_qsin6 <= mult_qsin6_w; + mult_qsin7 <= mult_qsin7_w; + mult_qsin8 <= mult_qsin8_w; + mult_qsin9 <= mult_qsin9_w; + mult_qsin10 <= mult_qsin10_w; + mult_qsin11 <= mult_qsin11_w; + mult_qsin12 <= mult_qsin12_w; + mult_qsin13 <= mult_qsin13_w; + mult_qsin14 <= mult_qsin14_w; + mult_qsin15 <= mult_qsin15_w; + end + else begin + mult_qsin0 <= 16'b0; + mult_qsin1 <= 16'b0; + mult_qsin2 <= 16'b0; + mult_qsin3 <= 16'b0; + mult_qsin4 <= 16'b0; + mult_qsin5 <= 16'b0; + mult_qsin6 <= 16'b0; + mult_qsin7 <= 16'b0; + mult_qsin8 <= 16'b0; + mult_qsin9 <= 16'b0; + mult_qsin10 <= 16'b0; + mult_qsin11 <= 16'b0; + mult_qsin12 <= 16'b0; + mult_qsin13 <= 16'b0; + mult_qsin14 <= 16'b0; + mult_qsin15 <= 16'b0; + end +end + +wire signed [16:0] ssb0_pt; +wire signed [16:0] ssb1_pt; +wire signed [16:0] ssb2_pt; +wire signed [16:0] ssb3_pt; +wire signed [16:0] ssb4_pt; +wire signed [16:0] ssb5_pt; +wire signed [16:0] ssb6_pt; +wire signed [16:0] ssb7_pt; +wire signed [16:0] ssb8_pt; +wire signed [16:0] ssb9_pt; +wire signed [16:0] ssb10_pt; +wire signed [16:0] ssb11_pt; +wire signed [16:0] ssb12_pt; +wire signed [16:0] ssb13_pt; +wire signed [16:0] ssb14_pt; +wire signed [16:0] ssb15_pt; + + +/* +DW01_addsub #(16) inst_dw01_addsub_0(.A(mult_icos0),.B(mult_qsin0),.CI(1'b0),.ADD_SUB(sel_sideband),.SUM(ssb0_pt),.CO()); +DW01_addsub #(16) inst_dw01_addsub_1(.A(mult_icos1),.B(mult_qsin1),.CI(1'b0),.ADD_SUB(sel_sideband),.SUM(ssb1_pt),.CO()); +DW01_addsub #(16) inst_dw01_addsub_2(.A(mult_icos2),.B(mult_qsin2),.CI(1'b0),.ADD_SUB(sel_sideband),.SUM(ssb2_pt),.CO()); +DW01_addsub #(16) inst_dw01_addsub_3(.A(mult_icos3),.B(mult_qsin3),.CI(1'b0),.ADD_SUB(sel_sideband),.SUM(ssb3_pt),.CO()); +DW01_addsub #(16) inst_dw01_addsub_4(.A(mult_icos4),.B(mult_qsin4),.CI(1'b0),.ADD_SUB(sel_sideband),.SUM(ssb4_pt),.CO()); +DW01_addsub #(16) inst_dw01_addsub_5(.A(mult_icos5),.B(mult_qsin5),.CI(1'b0),.ADD_SUB(sel_sideband),.SUM(ssb5_pt),.CO()); +DW01_addsub #(16) inst_dw01_addsub_6(.A(mult_icos6),.B(mult_qsin6),.CI(1'b0),.ADD_SUB(sel_sideband),.SUM(ssb6_pt),.CO()); +DW01_addsub #(16) inst_dw01_addsub_7(.A(mult_icos7),.B(mult_qsin7),.CI(1'b0),.ADD_SUB(sel_sideband),.SUM(ssb7_pt),.CO()); +DW01_addsub #(16) inst_dw01_addsub_8(.A(mult_icos8),.B(mult_qsin8),.CI(1'b0),.ADD_SUB(sel_sideband),.SUM(ssb8_pt),.CO()); +DW01_addsub #(16) inst_dw01_addsub_9(.A(mult_icos9),.B(mult_qsin9),.CI(1'b0),.ADD_SUB(sel_sideband),.SUM(ssb9_pt),.CO()); +DW01_addsub #(16) inst_dw01_addsub_10(.A(mult_icos10),.B(mult_qsin10),.CI(1'b0),.ADD_SUB(sel_sideband),.SUM(ssb10_pt),.CO()); +DW01_addsub #(16) inst_dw01_addsub_11(.A(mult_icos11),.B(mult_qsin11),.CI(1'b0),.ADD_SUB(sel_sideband),.SUM(ssb11_pt),.CO()); +DW01_addsub #(16) inst_dw01_addsub_12(.A(mult_icos12),.B(mult_qsin12),.CI(1'b0),.ADD_SUB(sel_sideband),.SUM(ssb12_pt),.CO()); +DW01_addsub #(16) inst_dw01_addsub_13(.A(mult_icos13),.B(mult_qsin13),.CI(1'b0),.ADD_SUB(sel_sideband),.SUM(ssb13_pt),.CO()); +DW01_addsub #(16) inst_dw01_addsub_14(.A(mult_icos14),.B(mult_qsin14),.CI(1'b0),.ADD_SUB(sel_sideband),.SUM(ssb14_pt),.CO()); +DW01_addsub #(16) inst_dw01_addsub_15(.A(mult_icos15),.B(mult_qsin15),.CI(1'b0),.ADD_SUB(sel_sideband),.SUM(ssb15_pt),.CO()); +*/ + +assign ssb0_pt = sel_sideband ? mult_icos0 - mult_qsin0 : mult_icos0 + mult_qsin0 ; +assign ssb1_pt = sel_sideband ? mult_icos1 - mult_qsin1 : mult_icos1 + mult_qsin1 ; +assign ssb2_pt = sel_sideband ? mult_icos2 - mult_qsin2 : mult_icos2 + mult_qsin2 ; +assign ssb3_pt = sel_sideband ? mult_icos3 - mult_qsin3 : mult_icos3 + mult_qsin3 ; +assign ssb4_pt = sel_sideband ? mult_icos4 - mult_qsin4 : mult_icos4 + mult_qsin4 ; +assign ssb5_pt = sel_sideband ? mult_icos5 - mult_qsin5 : mult_icos5 + mult_qsin5 ; +assign ssb6_pt = sel_sideband ? mult_icos6 - mult_qsin6 : mult_icos6 + mult_qsin6 ; +assign ssb7_pt = sel_sideband ? mult_icos7 - mult_qsin7 : mult_icos7 + mult_qsin7 ; +assign ssb8_pt = sel_sideband ? mult_icos8 - mult_qsin8 : mult_icos8 + mult_qsin8 ; +assign ssb9_pt = sel_sideband ? mult_icos9 - mult_qsin9 : mult_icos9 + mult_qsin9 ; +assign ssb10_pt = sel_sideband ? mult_icos10 - mult_qsin10 : mult_icos10 + mult_qsin10; +assign ssb11_pt = sel_sideband ? mult_icos11 - mult_qsin11 : mult_icos11 + mult_qsin11; +assign ssb12_pt = sel_sideband ? mult_icos12 - mult_qsin12 : mult_icos12 + mult_qsin12; +assign ssb13_pt = sel_sideband ? mult_icos13 - mult_qsin13 : mult_icos13 + mult_qsin13; +assign ssb14_pt = sel_sideband ? mult_icos14 - mult_qsin14 : mult_icos14 + mult_qsin14; +assign ssb15_pt = sel_sideband ? mult_icos15 - mult_qsin15 : mult_icos15 + mult_qsin15; + +wire signed [15:0] ssb0_w; +wire signed [15:0] ssb1_w; +wire signed [15:0] ssb2_w; +wire signed [15:0] ssb3_w; +wire signed [15:0] ssb4_w; +wire signed [15:0] ssb5_w; +wire signed [15:0] ssb6_w; +wire signed [15:0] ssb7_w; +wire signed [15:0] ssb8_w; +wire signed [15:0] ssb9_w; +wire signed [15:0] ssb10_w; +wire signed [15:0] ssb11_w; +wire signed [15:0] ssb12_w; +wire signed [15:0] ssb13_w; +wire signed [15:0] ssb14_w; +wire signed [15:0] ssb15_w; + + + +assign ssb0_w = (ssb0_pt[16:15] == 2'b01) ? 16'd32767 : + (ssb0_pt[16:15] == 2'b10) ? -16'd32768 : + {ssb0_pt[16],ssb0_pt[14:0]}; + +assign ssb1_w = (ssb1_pt[16:15] == 2'b01) ? 16'd32767 : + (ssb1_pt[16:15] == 2'b10) ? -16'd32768 : + {ssb1_pt[16],ssb1_pt[14:0]}; + +assign ssb2_w = (ssb2_pt[16:15] == 2'b01) ? 16'd32767 : + (ssb2_pt[16:15] == 2'b10) ? -16'd32768 : + {ssb2_pt[16],ssb2_pt[14:0]}; + +assign ssb3_w = (ssb3_pt[16:15] == 2'b01) ? 16'd32767 : + (ssb3_pt[16:15] == 2'b10) ? -16'd32768 : + {ssb3_pt[16],ssb3_pt[14:0]}; + +assign ssb4_w = (ssb4_pt[16:15] == 2'b01) ? 16'd32767 : + (ssb4_pt[16:15] == 2'b10) ? -16'd32768 : + {ssb4_pt[16],ssb4_pt[14:0]}; + +assign ssb5_w = (ssb5_pt[16:15] == 2'b01) ? 16'd32767 : + (ssb5_pt[16:15] == 2'b10) ? -16'd32768 : + {ssb5_pt[16],ssb5_pt[14:0]}; + +assign ssb6_w = (ssb6_pt[16:15] == 2'b01) ? 16'd32767 : + (ssb6_pt[16:15] == 2'b10) ? -16'd32768 : + {ssb6_pt[16],ssb6_pt[14:0]}; + +assign ssb7_w = (ssb7_pt[16:15] == 2'b01) ? 16'd32767 : + (ssb7_pt[16:15] == 2'b10) ? -16'd32768 : + {ssb7_pt[16],ssb7_pt[14:0]}; + +assign ssb8_w = (ssb8_pt[16:15] == 2'b01) ? 16'd32767 : + (ssb8_pt[16:15] == 2'b10) ? -16'd32768 : + {ssb8_pt[16],ssb8_pt[14:0]}; + +assign ssb9_w = (ssb9_pt[16:15] == 2'b01) ? 16'd32767 : + (ssb9_pt[16:15] == 2'b10) ? -16'd32768 : + {ssb9_pt[16],ssb9_pt[14:0]}; + +assign ssb10_w = (ssb10_pt[16:15] == 2'b01) ? 16'd32767 : + (ssb10_pt[16:15] == 2'b10) ? -16'd32768 : + {ssb10_pt[16],ssb10_pt[14:0]}; + +assign ssb11_w = (ssb11_pt[16:15] == 2'b01) ? 16'd32767 : + (ssb11_pt[16:15] == 2'b10) ? -16'd32768 : + {ssb11_pt[16],ssb11_pt[14:0]}; + +assign ssb12_w = (ssb12_pt[16:15] == 2'b01) ? 16'd32767 : + (ssb12_pt[16:15] == 2'b10) ? -16'd32768 : + {ssb12_pt[16],ssb12_pt[14:0]}; + +assign ssb13_w = (ssb13_pt[16:15] == 2'b01) ? 16'd32767 : + (ssb13_pt[16:15] == 2'b10) ? -16'd32768 : + {ssb13_pt[16],ssb13_pt[14:0]}; + +assign ssb14_w = (ssb14_pt[16:15] == 2'b01) ? 16'd32767 : + (ssb14_pt[16:15] == 2'b10) ? -16'd32768 : + {ssb14_pt[16],ssb14_pt[14:0]}; + +assign ssb15_w = (ssb15_pt[16:15] == 2'b01) ? 16'd32767 : + (ssb15_pt[16:15] == 2'b10) ? -16'd32768 : + {ssb15_pt[16],ssb15_pt[14:0]}; + + + +reg signed [15:0] ssb0; +reg signed [15:0] ssb1; +reg signed [15:0] ssb2; +reg signed [15:0] ssb3; +reg signed [15:0] ssb4; +reg signed [15:0] ssb5; +reg signed [15:0] ssb6; +reg signed [15:0] ssb7; +reg signed [15:0] ssb8; +reg signed [15:0] ssb9; +reg signed [15:0] ssb10; +reg signed [15:0] ssb11; +reg signed [15:0] ssb12; +reg signed [15:0] ssb13; +reg signed [15:0] ssb14; +reg signed [15:0] ssb15; + +always@(posedge clk)begin + if(mix_data_vld_dly[2]) begin + ssb0 <= ssb0_w; + ssb1 <= ssb1_w; + ssb2 <= ssb2_w; + ssb3 <= ssb3_w; + ssb4 <= ssb4_w; + ssb5 <= ssb5_w; + ssb6 <= ssb6_w; + ssb7 <= ssb7_w; + ssb8 <= ssb8_w; + ssb9 <= ssb9_w; + ssb10 <= ssb10_w; + ssb11 <= ssb11_w; + ssb12 <= ssb12_w; + ssb13 <= ssb13_w; + ssb14 <= ssb14_w; + ssb15 <= ssb15_w; + end + else begin + ssb0 <= 16'b0; + ssb1 <= 16'b0; + ssb2 <= 16'b0; + ssb3 <= 16'b0; + ssb4 <= 16'b0; + ssb5 <= 16'b0; + ssb6 <= 16'b0; + ssb7 <= 16'b0; + ssb8 <= 16'b0; + ssb9 <= 16'b0; + ssb10 <= 16'b0; + ssb11 <= 16'b0; + ssb12 <= 16'b0; + ssb13 <= 16'b0; + ssb14 <= 16'b0; + ssb15 <= 16'b0; + end +end +assign dout_0 = ssb0; +assign dout_1 = ssb1; +assign dout_2 = ssb2; +assign dout_3 = ssb3; +assign dout_4 = ssb4; +assign dout_5 = ssb5; +assign dout_6 = ssb6; +assign dout_7 = ssb7; +assign dout_8 = ssb8; +assign dout_9 = ssb9; +assign dout_10 = ssb10; +assign dout_11 = ssb11; +assign dout_12 = ssb12; +assign dout_13 = ssb13; +assign dout_14 = ssb14; +assign dout_15 = ssb15; + + + + +always @(posedge clk or negedge rstn) begin + if(rstn == 1'b0) begin + mix_data_vld_dly <= 4'b0; + end + else begin + mix_data_vld_dly <= {mix_data_vld_dly[2:0], mix_enable & din_vld}; + end +end + +assign dout_vld = mix_data_vld_dly[3]; + +endmodule diff --git a/tb/awg_top/Makefile b/tb/awg_top/Makefile new file mode 100644 index 0000000..62674e9 --- /dev/null +++ b/tb/awg_top/Makefile @@ -0,0 +1,17 @@ +VCS = vcs -full64 -sverilog +lint=TFIPC-L +v2k -debug_access+all +define+DUMP_FSDB -lca -q -timescale=1ns/1ps +nospecify -P /opt/Synopsys/Verdi2015/share/PLI/VCS/LINUX64/novas_new_dumper.tab /opt/Synopsys/Verdi2015/share/PLI/VCS/LINUX64/pli.a -l compile.log + +SIMV = ./simv -l sim.log + +all:comp run + +comp: + ${VCS} -f files.f + +run: + ${SIMV} + +dbg: + verdi -sverilog -f files.f -top TB -nologo & + +clean: + rm -rf DVE* simv* *log ucli.key verdiLog urgReport csrc novas.* *.fsdb *.dat *.daidir *.vdb *~ diff --git a/tb/awg_top/TB.sv b/tb/awg_top/TB.sv new file mode 100644 index 0000000..19b4e16 --- /dev/null +++ b/tb/awg_top/TB.sv @@ -0,0 +1,330 @@ + `timescale 1ns/1ps +//`define FPGA_TEST +//`define SRAM32KB_FILENAME "./mcu.cde" +//`define AHB_RAM_SMIC_MODEL +//`define AHB_RAM_FPGA_SRAM_MODEL +//`define AHB_ROM_SMIC_MODEL_16KB +//`define AHB_ROM_SMIC_MODEL_8KB +//`define SMIC_PAD +// `define FPGA_PAD +//`include "qbmcu_defines.v" +module TB; + +//====================================================================== +initial begin + $fsdbAutoSwitchDumpfile(500, "./verdplus.fsdb", 1000000); + $fsdbDumpvars(); +end +//====================================================================== +//clock & reset & bootsel +//====================================================================== +logic clk ; +logic rst_n ; +logic qbmcu_i_start ; +parameter SYS_PERIOD = 1.33; +//sys_clk --> 50M, 0 phase +initial begin + clk =0; + forever # (SYS_PERIOD/2) clk = ~clk; +end + + +//hresetn +initial begin + rst_n = 0; + #1000; + rst_n = 0; + #1000; + rst_n = 1; + // $display("m%"); +end + +logic [31:0] mcu_cwfr [3:0] ; +logic [31:0] mcu_gapr [7:0] ; +logic [31:0] mcu_ampr [3:0] ; +logic [31:0] mcu_baisr [3:0] ; +logic [1 :0] mcu_intp_sel ; +logic mcu_nco_pha_clr ; +logic [15:0] mcu_rz_pha ; +logic send ; +logic sendc ; +logic [31 :0] codeword ; +logic [1 :0] fb_st ; +logic [31 :0] enve_bwrdata ; +logic [0 :0] enve_bwren ; +logic [24 :0] enve_brwaddr ; +logic [0 :0] enve_brden = 1'b0 ; +logic [31 :0] enve_brddata ; +logic [31 :0] enve_id_bwrdata ; +logic [0 :0] enve_id_bwren ; +logic [24 :0] enve_id_brwaddr ; +logic [0 :0] enve_id_brden = 1'b0; +logic [31 :0] enve_id_brddata ; +logic [0 :0] enve_read_fsm_st ; +logic proc_cft ; +logic mod_sideband_sel ; +logic mod_pha_sfot_clr ; +logic [1 :0] role_sel ; +logic [1 :0] intp_sel ; +logic [15 :0] mod_data_i ; +logic [15 :0] mod_data_q ; +logic mod_vld ; + +///////////////////////////////////////////////////////////////////////////////////// +//mcu_cwfr +assign mcu_cwfr[0] = 32'h1000_0000; +assign mcu_cwfr[1] = 32'h0800_0000; +assign mcu_cwfr[2] = 32'h0400_0000; +assign mcu_cwfr[3] = 32'h0200_0000; +//mcu_gapr +assign mcu_gapr[0] = 16'h0000; +assign mcu_gapr[1] = 16'h0800; +assign mcu_gapr[2] = 16'h0400; +assign mcu_gapr[3] = 16'h0200; +assign mcu_gapr[4] = 16'h1000; +assign mcu_gapr[5] = 16'h0800; +assign mcu_gapr[6] = 16'h0400; +assign mcu_gapr[7] = 16'h0200; +//mcu_ampr +assign mcu_ampr[0] = 16'hf000; +assign mcu_ampr[1] = 16'h8000; +assign mcu_ampr[2] = 16'h4000; +assign mcu_ampr[3] = 16'h2000; +//mcu_baisr +assign mcu_baisr[0] = 16'h0100; +assign mcu_baisr[1] = 16'h0200; +assign mcu_baisr[2] = 16'h0300; +assign mcu_baisr[3] = 16'h0400; + + + + +always @(posedge clk or negedge rst_n) begin + if(!rst_n) begin + enve_bwrdata <= '0; + enve_bwren <= '0; + enve_brwaddr <= '0; + end + else begin + if(enve_bwrdata == 32'd8191) begin + enve_bwrdata <= enve_bwrdata; + enve_bwren <= '0; + enve_brwaddr <= enve_brwaddr; + end + else begin + enve_bwrdata <= enve_bwrdata + 1'b1; + enve_bwren <= '1; + enve_brwaddr <= {enve_bwrdata[11:2],2'b00}; + end + end +end + + +always @(posedge clk or negedge rst_n) begin + if(!rst_n) begin + enve_id_bwrdata <= {16'd0,16'd20}; + enve_id_bwren <= '0; + enve_id_brwaddr <= '0; + end + else begin + if(enve_id_brwaddr[7:2] == 6'd63) begin + enve_id_bwrdata <= enve_id_bwrdata; + enve_id_bwren <= '0; + enve_id_brwaddr <= enve_id_brwaddr; + end + else begin + enve_id_bwrdata <={enve_id_bwrdata[31:16] + 16'd20,enve_id_bwrdata[15:0] + 16'd20}; + enve_id_bwren <= '1; + enve_id_brwaddr <= enve_id_brwaddr + 16'd4; + end + end +end + +//mod_sideband_sel +assign mod_sideband_sel = 1'b0; + +//mod_pha_sfot_clr +assign mod_pha_sfot_clr = 1'b0; + +//role_sel + + +logic [31:0] cnt_c; + +wire add_cnt = 'b1; + +wire end_cnt = 1'b0; + +wire [31:0] cnt_n = end_cnt ? 32'h0 : + add_cnt ? cnt_c + 1'b1 : + cnt_c ; + + +sirv_gnrl_dffr #(32) cnt_c_dffr (cnt_n, cnt_c, clk, rst_n); + + + +always @(posedge clk or negedge rst_n) begin + if(!rst_n) begin + role_sel <= 2'b00; + mcu_intp_sel <= 2'b00; + mcu_nco_pha_clr <= 1'b0; + mcu_rz_pha <= 16'b0; + send <= 1'b0; + sendc <= 1'b0; + codeword <= 32'b0; + fb_st <= 2'b00; + end + else if(cnt_c == 32'd1000) begin + role_sel <= 2'b00; + mcu_intp_sel <= 2'b11; + mcu_nco_pha_clr <= 1'b0; + mcu_rz_pha <= 16'b0; + send <= 1'b1; + sendc <= 1'b0; + codeword <= 32'b000000000000_0_0000_01_101_11_00000100; + fb_st <= 2'b00; + end + else if(cnt_c == 32'd1001) begin + role_sel <= 2'b00; + mcu_intp_sel <= 2'b11; + mcu_nco_pha_clr <= 1'b0; + mcu_rz_pha <= 16'd5; + send <= 1'b0; + sendc <= 1'b0; + codeword <= 32'b000000000000_0_0000_01_101_11_00000100; + fb_st <= 2'b00; + end + else if(cnt_c == 32'd10000) begin + role_sel <= 2'b00; + mcu_intp_sel <= 2'b11; + mcu_nco_pha_clr <= 1'b0; + mcu_rz_pha <= 16'd88; + send <= 1'b1; + sendc <= 1'b0; + codeword <= 32'b000000000000_1_0000_01_101_11_00000100; + fb_st <= 2'b00; + end + else if(cnt_c == 32'd10001) begin + role_sel <= 2'b00; + mcu_intp_sel <= 2'b11; + mcu_nco_pha_clr <= 1'b0; + mcu_rz_pha <= 16'b0; + send <= 1'b0; + sendc <= 1'b0; + codeword <= 32'b000000000000_0_0000_01_101_11_00000100; + fb_st <= 2'b00; + end + else if(cnt_c == 32'd20000) begin + role_sel <= 2'b00; + mcu_intp_sel <= 2'b11; + mcu_nco_pha_clr <= 1'b0; + mcu_rz_pha <= 16'b0; + send <= 1'b0; + sendc <= 1'b1; + codeword <= 32'b000000000000_0_0000_01_101_11_00000100; + fb_st <= 2'b01; + end + else if(cnt_c == 32'd20001) begin + role_sel <= 2'b00; + mcu_intp_sel <= 2'b11; + mcu_nco_pha_clr <= 1'b0; + mcu_rz_pha <= 16'b0; + send <= 1'b0; + sendc <= 1'b0; + codeword <= 32'b000000000000_0_0000_01_000_11_00000100; + fb_st <= 2'b01; + end + else if(cnt_c == 32'd30000) begin + role_sel <= 2'b00; + mcu_intp_sel <= 2'b11; + mcu_nco_pha_clr <= 1'b0; + mcu_rz_pha <= 16'hf000; + send <= 1'b1; + sendc <= 1'b0; + codeword <= 32'b000000000000_0_0000_00_000_11_00000100; + fb_st <= 2'b01; + end + else if(cnt_c == 32'd30001) begin + role_sel <= 2'b00; + mcu_intp_sel <= 2'b11; + mcu_nco_pha_clr <= 1'b0; + mcu_rz_pha <= 16'hf000; + send <= 1'b0; + sendc <= 1'b0; + codeword <= 32'b000000000000_0_0000_00_000_11_00000100; + fb_st <= 2'b01; + end + else if(cnt_c == 32'd30002) begin + role_sel <= 2'b00; + mcu_intp_sel <= 2'b11; + mcu_nco_pha_clr <= 1'b0; + mcu_rz_pha <= 16'hf000; + send <= 1'b0; + sendc <= 1'b0; + codeword <= 32'b000000000000_0_0000_00_000_11_00000100; + fb_st <= 2'b01; + end + else if(cnt_c == 32'd40000) begin + role_sel <= 2'b00; + mcu_intp_sel <= 2'b11; + mcu_nco_pha_clr <= 1'b0; + mcu_rz_pha <= 16'h1000; + send <= 1'b1; + sendc <= 1'b0; + codeword <= 32'b000000000000_0_0000_00_000_11_00000100; + fb_st <= 2'b01; + end + else if(cnt_c == 32'd40001) begin + role_sel <= 2'b00; + mcu_intp_sel <= 2'b11; + mcu_nco_pha_clr <= 1'b0; + mcu_rz_pha <= 16'h1000; + send <= 1'b0; + sendc <= 1'b0; + codeword <= 32'b000000000000_0_0000_00_000_11_00000100; + fb_st <= 2'b01; + end +end + +awg_top U_awg_top ( + .clk ( clk ) + ,.rst_n ( rst_n ) + ,.mcu_cwfr ( mcu_cwfr ) + ,.mcu_gapr ( mcu_gapr ) + ,.mcu_ampr ( mcu_ampr ) + ,.mcu_baisr ( mcu_baisr ) + ,.mcu_intp_sel ( mcu_intp_sel ) + ,.mcu_nco_pha_clr ( mcu_nco_pha_clr ) + ,.mcu_rz_pha ( mcu_rz_pha ) + ,.send ( send ) + ,.sendc ( sendc ) + ,.codeword ( codeword ) + ,.fb_st ( fb_st ) + ,.enve_bwrdata ( enve_bwrdata ) + ,.enve_bwren ( enve_bwren ) + ,.enve_brwaddr ( enve_brwaddr ) + ,.enve_brden ( enve_brden ) + ,.enve_brddata ( enve_brddata ) + ,.enve_id_bwrdata ( enve_id_bwrdata ) + ,.enve_id_bwren ( enve_id_bwren ) + ,.enve_id_brwaddr ( enve_id_brwaddr ) + ,.enve_id_brden ( enve_id_brden ) + ,.enve_id_brddata ( enve_id_brddata ) + ,.enve_read_fsm_st ( enve_read_fsm_st ) + ,.proc_cft ( proc_cft ) + ,.mod_sideband_sel ( mod_sideband_sel ) + ,.mod_pha_sfot_clr ( mod_pha_sfot_clr ) + ,.role_sel ( role_sel ) + ,.intp_sel ( intp_sel ) + ,.mod_data_i ( mod_data_i ) + ,.mod_data_q ( mod_data_q ) + ,.mod_vld ( mod_vld ) + ); + + initial begin + wait(cnt_c == 32'd100000) + $finish(0); +end + +endmodule diff --git a/tb/awgreg_tb/awg_refmodel.sv b/tb/awgreg_tb/awg_refmodel.sv new file mode 100644 index 0000000..d1038f5 --- /dev/null +++ b/tb/awgreg_tb/awg_refmodel.sv @@ -0,0 +1,228 @@ +//For awg_regfile, the ROreg: mcu_resr/rtimr/icntr/fsir are updated by the inputs +//at this clk_posedge due to dff(inputs->regs) +class awg_refmodel; + + virtual awgreg_if aif; + virtual spi_if wif; + virtual sram_if#(25,32) xif; + + + //poor-quality register model + bit[31:0] rm[24]; + + //members to be sent to scoreboard + int rst_error[5]; + bit[31:0] dout[$]; + awgreg_trans awgout[$]; + + + + function new(); + endfunction + extern task do_imitate(); + extern task RWreg_write (bit[24:0] addr,bit[32:0] din ); + extern task ROreg_update (bit[24:0] addr ); + extern task reg_read (bit[24:0] addr ); + extern task output_trace (bit[24:0] addr ); + +endclass : awg_refmodel + +task awg_refmodel::do_imitate(); + + int i=0,j=0; + + rm[ 0] = 32'h0; //MCUPARAR0 + rm[ 1] = 32'h0; //MCUPARAR1 + rm[ 2] = 32'h0; //MCUPARAR2 + rm[ 3] = 32'h0; //MCUPARAR3 + rm[ 4] = 32'h0; //MCURESR0 + rm[ 5] = 32'h0; //MCURESR1 + rm[ 6] = 32'h0; //MCURESR2 + rm[ 7] = 32'h0; //MCURESR3 + rm[ 8] = 32'h0; //PTIMR + rm[ 9] = 32'h0; //ICNTR + rm[10] = 32'h0; //FSIR + rm[11] = 32'h0; //MODMR + rm[12] = 32'h0; //INTPMR + rm[13] = 32'h0; //MIXNCOR + rm[14] = 32'h0; //MIXNFCWHR + rm[15] = 32'h0; //MIXNFCWLR + rm[16] = 32'h0; //MIXNPHAR + rm[17] = 32'h0; //MIXMR + rm[18] = 32'h0; //MIXODTR + rm[19] = 32'h0; //MIXODFR + rm[20] = 32'h0; //ROLER + rm[21] = 32'h0; //MIXNCOSCER + rm[22] = 32'h0; //MODDOTR + rm[23] = 32'h0; //STR + + fork + + + while(1) begin: write_reg_RW + + @(negedge xif.wren); + + RWreg_write(xif.addr,xif.din); + + end: write_reg_RW + + + + while(1) begin: update_reg_RO + + ROreg_update(xif.addr); + + end: update_reg_RO + + + while(1) begin: read_reg + + @(negedge xif.rden); + + reg_read(xif.addr); + + end: read_reg + + + + while(1) begin: output_port + + @(negedge xif.wren); + + output_trace(xif.addr); + + end: output_port + + + join + +endtask: do_imitate + + + +task awg_refmodel::RWreg_write(bit[24:0] addr,bit[32:0] din); + + + //delay caused by decoder + @(posedge wif.clk); + + case(addr[24: 2]) + 23'hC0000: rm[ 0] = din; //MCUPARAR0 + 23'hC0001: rm[ 1] = din; //MCUPARAR1 + 23'hC0002: rm[ 2] = din; //MCUPARAR2 + 23'hC0003: rm[ 3] = din; //MCUPARAR3 + 23'hC0040: rm[11] = {rm[11][31: 1],din[0 : 0]}; //MODMR + 23'hC0041: rm[12] = {rm[12][31: 3],din[2 : 0]}; //INTPMR + 23'hC0042: rm[13] = {rm[13][31: 1],din[0 : 0]}; //MIXNCOR + 23'hC0043: rm[14] = din; //MIXNFCWHR + 23'hC0044: rm[15] = {rm[15][31:16],din[31:16]}; //MIXNFCWLR + 23'hC0045: rm[16] = {rm[16][31:16],din[31:16]}; //MIXNPHAR + 23'hC0046: rm[17] = {rm[17][31: 1],din[0 : 0]}; //MIXMR + 23'hC0047: rm[18] = {rm[18][31: 2],din[1 : 0]}; //MIXODTR + 23'hC0048: rm[19] = {rm[19][31: 2],din[1 : 0]}; //MIXODFR + 23'hC004a: rm[20] = {rm[20][31: 2],din[1 : 0]}; //ROLER + 23'hC004b: rm[21] = {rm[21][31: 1],din[0 : 0]}; //MIXNCOSCER + 23'hC004c: rm[22] = {rm[22][31: 1],din[0 : 0]}; //MODDOTR + endcase +//$display("addr:%0h",addr); +//$display("rm:%h",rm[addr[24: 2]]); +//$display("din:%h",din); + +endtask: RWreg_write + + + +task awg_refmodel::ROreg_update(bit[24:0] addr); + + @(posedge wif.clk); + + rm[ 4] = aif.mcu_result0 ; //MCURESR0 + rm[ 5] = aif.mcu_result1 ; //MCURESR1 + rm[ 6] = aif.mcu_result2 ; //MCURESR2 + rm[ 7] = aif.mcu_result3 ; //MCURESR3 + rm[ 8] = aif.run_time ; //PTIMR + rm[ 9] = aif.instr_num ; //ICNTR + rm[10] = {rm[10][31:2],aif.fb_st_i[1:0]} ; //FSIR + rm[23] = {rm[23][31:3],aif.bais_q_ov,aif.bais_i_ov,aif.awg_ctrl_fsm_st} ; //STR + +endtask: ROreg_update + + +task awg_refmodel::reg_read(bit[24:0] addr); + + + //delay caused be decoder + //@(posedge wif.clk); + + case(addr[24: 2]) + 23'hC0000: dout.push_back(rm[ 0]); //MCUPARAR0 + 23'hC0001: dout.push_back(rm[ 1]); //MCUPARAR1 + 23'hC0002: dout.push_back(rm[ 2]); //MCUPARAR2 + 23'hC0003: dout.push_back(rm[ 3]); //MCUPARAR3 + 23'hC0004: dout.push_back(rm[ 4]); //MCURESR0 + 23'hC0005: dout.push_back(rm[ 5]); //MCURESR1 + 23'hC0006: dout.push_back(rm[ 6]); //MCURESR2 + 23'hC0007: dout.push_back(rm[ 7]); //MCURESR3 + 23'hC0008: dout.push_back(0); + 23'hC0026: dout.push_back(rm[ 8]); //PTIMR + 23'hC0027: dout.push_back(rm[ 9]); //ICNTR + 23'hC0028: dout.push_back(rm[10]); //FSIR + 23'hC0029: dout.push_back(0); + 23'hC0040: dout.push_back(rm[11]); //MODMR + 23'hC0041: dout.push_back(rm[12]); //INTPMR + 23'hC0042: dout.push_back(rm[13]); //MIXNCOR + 23'hC0043: dout.push_back(rm[14]); //MIXNFCWHR + 23'hC0044: dout.push_back(rm[15]); //MIXNFCWLR + 23'hC0045: dout.push_back(rm[16]); //MIXNPHAR + 23'hC0046: dout.push_back(rm[17]); //MIXMR + 23'hC0047: dout.push_back(rm[18]); //MIXODTR + 23'hC0048: dout.push_back(rm[19]); //MIXODFR + 23'hC0049: dout.push_back(0) ; + 23'hC004a: dout.push_back({rm[20][31:2],rm[20][1 : 1]&rm[20][0 :0],rm[20][0 : 0]}); //ROLER + 23'hC004b: dout.push_back(rm[21]); //MIXNCOSCER + 23'hC004c: dout.push_back(rm[22]); //MODDOTR + 23'hC004d: dout.push_back(rm[23]); //STR + 23'hC004e: dout.push_back(0); + endcase +//$display("addr:%0h,dout:%h",addr[24:2],dout[$]); + +endtask: reg_read + + + +task awg_refmodel::output_trace(bit[24:0] addr); + + awgreg_trans tr_temp; + if(addr[24:20 == 5'h3]) + begin + //delay caused by decoder + @(posedge wif.clk); + + @(negedge wif.clk); + tr_temp = new(); + tr_temp.mcu_param0 = rm[ 0] ; //MCUPARAR0 + tr_temp.mcu_param1 = rm[ 1] ; //MCUPARAR1 + tr_temp.mcu_param2 = rm[ 2] ; //MCUPARAR2 + tr_temp.mcu_param3 = rm[ 3] ; //MCUPARAR3 + tr_temp.fb_st_o = rm[10][1: 0] ; //FSIR + tr_temp.mod_sel_sideband = rm[11][0: 0] ; //MODMR + tr_temp.qam_nco_clr = rm[13][0 :0] ; //MIXNCOR + tr_temp.qam_nco_sclr_en = rm[21][0 :0] ; //MIXNCOSCER + tr_temp.qam_fcw = {rm[14],rm[15][15:0]} ; //MIXNFCWHR MIXNFCWLR + tr_temp.qam_pha = rm[16][15: 0] ; //MIXNPHAR + tr_temp.qam_mod = rm[18][1 : 0] ; //MIXODTR + tr_temp.qam_sel_sideband = rm[17][0 : 0] ; //MIXMR + tr_temp.intp_mode = rm[12][2 : 0] ; //INTPMR + tr_temp.role_sel[0] = rm[20][0 : 0] ; //ROLER[0] + tr_temp.role_sel[1] = rm[20][1 : 1]&rm[20][0 :0]; //ROLER[1] + tr_temp.dac_mode_sel = rm[19][1 : 0] ; //MIXODFR + tr_temp.dout_sel = rm[22][0 : 0] ; //MODDOTR + + awgout.push_back(tr_temp); + end +//$display("addr:%0h",addr); +//$display("rm:%h",rm[addr[24: 2]]); +//$display("din:%h",din); + +endtask: output_trace diff --git a/tb/awgreg_tb/awgreg_driver.sv b/tb/awgreg_tb/awgreg_driver.sv new file mode 100644 index 0000000..8dc929b --- /dev/null +++ b/tb/awgreg_tb/awgreg_driver.sv @@ -0,0 +1,73 @@ +class awgreg_driver; + + + awgreg_trans tr; + + //interface + virtual awgreg_if aif; + virtual spi_if wif; + + + function new(); + endfunction + extern task do_drive(); + extern task make_pkt(); + +endclass : awgreg_driver + +task awgreg_driver::do_drive(); + + aif.fb_st_i =2'b0 ; + aif.run_time =32'b0 ; + aif.instr_num =32'b0 ; + aif.bais_i_ov =1'b0 ; + aif.bais_q_ov =1'b0 ; + aif.awg_ctrl_fsm_st =1'b0 ; + aif.mcu_result0 =32'b0 ; // MCU result 0 + aif.mcu_result1 =32'b0 ; // MCU result 1 + aif.mcu_result2 =32'b0 ; // MCU result 2 + aif.mcu_result3 =32'b0 ; // MCU result 3 + + fork + + while(1) begin + make_pkt(); + end + + join + +endtask + +task awgreg_driver::make_pkt(); + int cnt=0; + + cnt = 0; + + + tr = new(); + if(!tr.randomize()) + $fatal(0,"Randomize Failed"); + + + while(cnt<2000) begin + @(posedge wif.clk); + + cnt = cnt + 1; + + case(cnt) + tr.fb_st_i_time: aif.fb_st_i <= tr.fb_st_i ; + tr.run_time_time: aif.run_time <= tr.run_time ; + tr.instr_num_time: aif.instr_num <= tr.instr_num ; + tr.bais_i_ov_time: aif.bais_i_ov <= tr.bais_i_ov ; + tr.bais_q_ov_time: aif.bais_q_ov <= tr.bais_q_ov ; + tr.awg_ctrl_fsm_st_time: aif.awg_ctrl_fsm_st <= tr.awg_ctrl_fsm_st; + tr.mcu_result0_time: aif.mcu_result0 <= tr.mcu_result0 ; + tr.mcu_result1_time: aif.mcu_result1 <= tr.mcu_result1 ; + tr.mcu_result2_time: aif.mcu_result2 <= tr.mcu_result2 ; + tr.mcu_result3_time: aif.mcu_result3 <= tr.mcu_result3 ; + endcase + + end + +endtask : make_pkt + diff --git a/tb/awgreg_tb/awgreg_env.sv b/tb/awgreg_tb/awgreg_env.sv new file mode 100644 index 0000000..531f56c --- /dev/null +++ b/tb/awgreg_tb/awgreg_env.sv @@ -0,0 +1,103 @@ +class awgreg_env; + + + static int pktnum; + + //Interface: + virtual awgreg_if aif; + virtual spi_if wif; + virtual sram_if#(25,32) xif; + + //Component: + spi_driver w_driver; + awgreg_driver a_driver; + spi_monitor w_monitor; + awg_refmodel a_model; + awgreg_monitor a_monitor; + awgreg_scoreboard a_scb; + + + function new(); + endfunction; + + extern function build(); + + extern task run(); + +endclass + +function awgreg_env::build(); + + w_driver = new(); + if(!w_driver.randomize() with { + error_time < 0; + }) + $fatal(0,"Randomize Failed"); + w_driver.pktnum = pktnum; + w_driver.vif = wif; + w_driver.autarchy = 1'b1; + w_driver.half_sclk = 4; + + w_monitor = new(); + w_monitor.wif = wif; + w_monitor.xif = xif; + + a_driver = new(); + a_driver.aif = aif; + a_driver.wif = wif; + + a_monitor = new(); + a_monitor.aif = aif; + a_monitor.xif = xif; + + a_model = new(); + a_model.aif = aif; + a_model.wif = wif; + a_model.xif = xif; + + a_scb = new(); + +endfunction + + +task awgreg_env::run(); + int error=0; + + fork + + w_driver.do_drive(); + + a_driver.do_drive(); + + w_monitor.do_mon(); + + a_monitor.do_mon(); + + a_model.do_imitate(); + + + while(1) begin + repeat(2) @(posedge wif.csn); + @(posedge wif.clk); + a_model.dout.pop_back(); + if(a_scb.compare( + a_model.dout , + w_monitor.act_trans.data , + a_model.awgout , + a_monitor.act_trans + )) + error++; + a_model.dout.delete(); + a_model.awgout.delete(); + a_monitor.act_trans.delete(); + end + + + join + + $display("SCOREBOARD:"); + $display("\tError_awg:\t%0d",error); + + +endtask + diff --git a/tb/awgreg_tb/awgreg_if.sv b/tb/awgreg_tb/awgreg_if.sv new file mode 100644 index 0000000..657a14f --- /dev/null +++ b/tb/awgreg_tb/awgreg_if.sv @@ -0,0 +1,40 @@ + + +interface awgreg_if(input clk,input rstn); + + //input port + logic [1 :0] fb_st_i ; + logic [31 :0] run_time ; + logic [31 :0] instr_num ; + logic bais_i_ov ; + logic bais_q_ov ; + logic awg_ctrl_fsm_st ; + logic [31 :0] mcu_result0 ; // MCU result 0 + logic [31 :0] mcu_result1 ; // MCU result 1 + logic [31 :0] mcu_result2 ; // MCU result 2 + logic [31 :0] mcu_result3 ; // MCU result 3 + + + + //output port + logic [31 :0] mcu_param0 ; // MCU parameter 0 + logic [31 :0] mcu_param1 ; // MCU parameter 1 + logic [31 :0] mcu_param2 ; // MCU parameter 2 + logic [31 :0] mcu_param3 ; // MCU parameter 3 + logic [1 :0] fb_st_o ; + logic mod_sel_sideband ; //1'b0:Upper sideband;1'b1:Lower sideband; + logic qam_nco_clr ; + logic qam_nco_sclr_en ; + logic [47 :0] qam_fcw ; + logic [15 :0] qam_pha ; + logic [1 :0] qam_mod ; //2'b00:bypass;2'b01:mix;2'b10:cos;2'b11:sin; + logic qam_sel_sideband ; //1'b0:Upper sideband;1'b1:Lower sideband; + logic [2 :0] intp_mode ; //3'b000:x1;3'b001:x2;3'b010:x4;3'b011:x8;3'b100:x16; + logic [1 :0] role_sel ; //2'b00:HBF;2'b01:Nearest-neighbor interpolator;2'b10:Median interpolator;2'b00:reserve; + logic [1 :0] dac_mode_sel ; //2'b00:NRZ mode;2'b01:MIX mode;2'b10:2xNRZ mode;2'b00:reserve; + logic dout_sel ; //1'b0:bypass;1'b1:enable; + +endinterface : awgreg_if + + + diff --git a/tb/awgreg_tb/awgreg_monitor.sv b/tb/awgreg_tb/awgreg_monitor.sv new file mode 100644 index 0000000..c5920f0 --- /dev/null +++ b/tb/awgreg_tb/awgreg_monitor.sv @@ -0,0 +1,56 @@ +class awgreg_monitor; + + + virtual awgreg_if aif; + virtual sram_if#(25,32) xif; + + //collect + awgreg_trans act_trans[$]; + + + function new(); + endfunction + extern task collect(); + extern task do_mon(); + +endclass : awgreg_monitor + + +task awgreg_monitor::do_mon(); + + while(1) begin + @(negedge xif.wren); + collect(); + end + +endtask: do_mon + + + + +task awgreg_monitor::collect(); + awgreg_trans tr_temp; + + @(posedge xif.clk); + @(negedge xif.clk); + + tr_temp = new(); + tr_temp.mcu_param0 = aif.mcu_param0 ; + tr_temp.mcu_param1 = aif.mcu_param1 ; + tr_temp.mcu_param2 = aif.mcu_param2 ; + tr_temp.mcu_param3 = aif.mcu_param3 ; + tr_temp.fb_st_o = aif.fb_st_o ; + tr_temp.mod_sel_sideband = aif.mod_sel_sideband; + tr_temp.qam_nco_clr = aif.qam_nco_clr ; + tr_temp.qam_nco_sclr_en = aif.qam_nco_sclr_en ; + tr_temp.qam_fcw = aif.qam_fcw ; + tr_temp.qam_pha = aif.qam_pha ; + tr_temp.qam_mod = aif.qam_mod ; + tr_temp.qam_sel_sideband = aif.qam_sel_sideband; + tr_temp.intp_mode = aif.intp_mode ; + tr_temp.role_sel = aif.role_sel ; + tr_temp.dac_mode_sel = aif.dac_mode_sel ; + tr_temp.dout_sel = aif.dout_sel ; + act_trans.push_back(tr_temp); + +endtask: collect diff --git a/tb/awgreg_tb/awgreg_scb.sv b/tb/awgreg_tb/awgreg_scb.sv new file mode 100644 index 0000000..620b12b --- /dev/null +++ b/tb/awgreg_tb/awgreg_scb.sv @@ -0,0 +1,89 @@ +class awgreg_scoreboard; + + integer fid; + + function new(); + endfunction; + + //extern task do_check(); + + extern function bit compare( + bit[31:0] spi_exp[$], + bit[31:0] spi_act[$], + awgreg_trans awg_exp[$], + awgreg_trans awg_act[$] + ); + +endclass + +function bit awgreg_scoreboard::compare( + bit[31:0] spi_exp[$], + bit[31:0] spi_act[$], + awgreg_trans awg_exp[$], + awgreg_trans awg_act[$] +); + + bit result=1'b1; + int i=0; + +//$display(dout); + + if(spi_exp.size() != spi_act.size()) begin + result = 1'b0; + //$display("ScoreBoard(ERROR): write & read datanum ARNT'T equal!"); + //$display("Exp spi_data size:%0d",spi_exp.size()); + //$display("Act spi_data size:%0d",spi_act.size()); + $fwrite(fid,"ScoreBoard(ERROR): write & read datanum ARNT'T equal!\n"); + $fwrite(fid,"Exp spi_data size:%0d\n",spi_exp.size()); + $fwrite(fid,"Act spi_data size:%0d\n",spi_act.size()); + end + + else if(awg_exp.size() != awg_act.size()) begin + result = 1'b0; + //$display("ScoreBoard(ERROR): regmdl & read datanum ARNT'T equal!"); + //$display("Exp awg_trs size:%0d",awg_exp.size()); + //$display("Act awg_trs size:%0d",awg_act.size()); + $fwrite(fid,"ScoreBoard(ERROR): regmdl & read datanum ARNT'T equal!\n"); + $fwrite(fid,"Exp awg_trs size:%0d\n",awg_exp.size()); + $fwrite(fid,"Act awg_trs size:%0d\n",awg_act.size()); + end + + + else + for(i=0;i= 0 ; + run_time_time >= 0 ; + instr_num_time >= 0 ; + bais_i_ov_time >= 0 ; + bais_q_ov_time >= 0 ; + awg_ctrl_fsm_st_time >= 0 ; + mcu_result0_time >= 0 ; + mcu_result1_time >= 0 ; + mcu_result2_time >= 0 ; + mcu_result3_time >= 0 ; + fb_st_i_time <= 2000 ; + run_time_time <= 2000 ; + instr_num_time <= 2000 ; + bais_i_ov_time <= 2000 ; + bais_q_ov_time <= 2000 ; + awg_ctrl_fsm_st_time <= 2000 ; + mcu_result0_time <= 2000 ; + mcu_result1_time <= 2000 ; + mcu_result2_time <= 2000 ; + mcu_result3_time <= 2000 ; +} + + function new(); + endfunction + + function bit[38:0] compare(awgreg_trans tr); + bit[38:0] result=39'b0; + if(tr.mcu_param0 != mcu_param0 ) result[ 0]=1'b1; + if(tr.mcu_param1 != mcu_param1 ) result[ 1]=1'b1; + if(tr.mcu_param2 != mcu_param2 ) result[ 2]=1'b1; + if(tr.mcu_param3 != mcu_param3 ) result[ 3]=1'b1; + if(tr.fb_st_o != fb_st_o ) result[ 4]=1'b1; + if(tr.mod_sel_sideband != mod_sel_sideband ) result[ 5]=1'b1; + if(tr.qam_nco_clr != qam_nco_clr ) result[ 6]=1'b1; + if(tr.qam_nco_sclr_en != qam_nco_sclr_en ) result[ 7]=1'b1; + if(tr.qam_fcw != qam_fcw ) result[ 8]=1'b1; + if(tr.qam_pha != qam_pha ) result[ 9]=1'b1; + if(tr.qam_mod != qam_mod ) result[10]=1'b1; + if(tr.qam_sel_sideband != qam_sel_sideband ) result[11]=1'b1; + if(tr.intp_mode != intp_mode ) result[12]=1'b1; + if(tr.role_sel != role_sel ) result[13]=1'b1; + if(tr.dac_mode_sel != dac_mode_sel ) result[14]=1'b1; + if(tr.dout_sel != dout_sel ) result[15]=1'b1; + return result; + endfunction + + function print(bit[38:0] ctrl,integer fid); + if(ctrl[ 0]) $fwrite(fid,"mcu_param0 =%h\n",mcu_param0 ); + if(ctrl[ 1]) $fwrite(fid,"mcu_param1 =%h\n",mcu_param1 ); + if(ctrl[ 2]) $fwrite(fid,"mcu_param2 =%h\n",mcu_param2 ); + if(ctrl[ 3]) $fwrite(fid,"mcu_param3 =%h\n",mcu_param3 ); + if(ctrl[ 4]) $fwrite(fid,"fb_st_o =%h\n",fb_st_o ); + if(ctrl[ 5]) $fwrite(fid,"mod_sel_sideband =%h\n",mod_sel_sideband ); + if(ctrl[ 6]) $fwrite(fid,"qam_nco_clr =%h\n",qam_nco_clr ); + if(ctrl[ 7]) $fwrite(fid,"qam_nco_sclr_en =%h\n",qam_nco_sclr_en ); + if(ctrl[ 8]) $fwrite(fid,"qam_fcw =%h\n",qam_fcw ); + if(ctrl[ 9]) $fwrite(fid,"qam_pha =%h\n",qam_pha ); + if(ctrl[10]) $fwrite(fid,"qam_mod =%h\n",qam_mod ); + if(ctrl[11]) $fwrite(fid,"qam_sel_sideband =%h\n",qam_sel_sideband ); + if(ctrl[12]) $fwrite(fid,"intp_mode =%h\n",intp_mode ); + if(ctrl[13]) $fwrite(fid,"role_sel =%h\n",role_sel ); + if(ctrl[14]) $fwrite(fid,"dac_mode_sel =%h\n",dac_mode_sel ); + if(ctrl[15]) $fwrite(fid,"dout_sel =%h\n",dout_sel ); +endfunction + +endclass : awgreg_trans + + + + + + + + + + + + diff --git a/tb/chip_top/DW01_addsub.v b/tb/chip_top/DW01_addsub.v new file mode 100644 index 0000000..a369ca3 --- /dev/null +++ b/tb/chip_top/DW01_addsub.v @@ -0,0 +1,92 @@ +//////////////////////////////////////////////////////////////////////////////// +// +// This confidential and proprietary software may be used only +// as authorized by a licensing agreement from Synopsys Inc. +// In the event of publication, the following notice is applicable: +// +// (C) COPYRIGHT 1992 - 2018 SYNOPSYS INC. +// ALL RIGHTS RESERVED +// +// The entire notice above must be reproduced on all authorized +// copies. +// +// AUTHOR: PS Nov. 8, 1992 +// +// VERSION: Simulation Architecture +// +// DesignWare_version: 22a5618c +// DesignWare_release: O-2018.06-DWBB_201806.3 +// +//////////////////////////////////////////////////////////////////////////////// +//----------------------------------------------------------------------------------- +// +// ABSTRACT: Adder-Subtractor +// ADD_SUB= '1' : SUM <= A - B - CI +// ADD_SUB= '0' : SUM <= A + B + CI +// Carry-in and Carry-out is active high with both addition +// and subtraction. +// MODIFIED: Sheela May 11, 1995 +// Converted to verilog from vhdl +// GN +// changed dw01 to DW01 star 33068 +// +// Bob Tong: 12/02/98 +// STAR 59142 +// +// Bob Tong: 03/03/2000 +// STAR 99907 +// +// RPH 07/17/2002 +// Rewrote to comply with the new guidelines +// +//--------------------------------------------------------------------- + +module DW01_addsub (A,B,CI,ADD_SUB,SUM,CO); + + parameter integer width = 4; + + // port list declaration in order + input [width-1 : 0] A, B; + input CI, ADD_SUB; + + output [width-1 : 0] SUM; + output CO; + + // synopsys translate_off + wire [width : 0] tmp_out; + //------------------------------------------------------------------------- + // Parameter legality check + //------------------------------------------------------------------------- + + + + initial begin : parameter_check + integer param_err_flg; + + param_err_flg = 0; + + + if (width < 1) begin + param_err_flg = 1; + $display( + "ERROR: %m :\n Invalid value (%d) for parameter width (lower bound: 1)", + width ); + end + + if ( param_err_flg == 1) begin + $display( + "%m :\n Simulation aborted due to invalid parameter value(s)"); + $finish; + end + + end // parameter_check + + + assign tmp_out = ((^(A ^ A) !== 1'b0) || (^(B ^ B) !== 1'b0) || (^(ADD_SUB ^ ADD_SUB) !== 1'b0)) ? {width+1{1'bx}} + : ADD_SUB ? A-B-CI : A+B+CI; + assign CO = tmp_out[width]; + assign SUM = tmp_out[width-1 : 0]; + + // synopsys translate_on + +endmodule diff --git a/tb/chip_top/DW02_mult.v b/tb/chip_top/DW02_mult.v new file mode 100644 index 0000000..bdcb182 --- /dev/null +++ b/tb/chip_top/DW02_mult.v @@ -0,0 +1,101 @@ +//////////////////////////////////////////////////////////////////////////////// +// +// This confidential and proprietary software may be used only +// as authorized by a licensing agreement from Synopsys Inc. +// In the event of publication, the following notice is applicable: +// +// (C) COPYRIGHT 1994 - 2018 SYNOPSYS INC. +// ALL RIGHTS RESERVED +// +// The entire notice above must be reproduced on all authorized +// copies. +// +// AUTHOR: KB WSFDB June 30, 1994 +// +// VERSION: Simulation Architecture +// +// DesignWare_version: 714fe7a9 +// DesignWare_release: O-2018.06-DWBB_201806.3 +// +//////////////////////////////////////////////////////////////////////////////// +//----------------------------------------------------------------------------------- +// +// ABSTRACT: Multiplier +// A_width-Bits * B_width-Bits => A_width+B_width Bits +// Operands A and B can be either both signed (two's complement) or +// both unsigned numbers. TC determines the coding of the input operands. +// ie. TC = '1' => signed multiplication +// TC = '0' => unsigned multiplication +// +// FIXED: by replacement with A tested working version +// that not only doesn't multiplies right it does it +// two times faster! +// RPH 07/17/2002 +// Rewrote to comply with the new guidelines +//------------------------------------------------------------------------------ + +module DW02_mult(A,B,TC,PRODUCT); +parameter integer A_width = 8; +parameter integer B_width = 8; + +input [A_width-1:0] A; +input [B_width-1:0] B; +input TC; +output [A_width+B_width-1:0] PRODUCT; + +wire [A_width+B_width-1:0] PRODUCT; + +wire [A_width-1:0] temp_a; +wire [B_width-1:0] temp_b; +wire [A_width+B_width-2:0] long_temp1,long_temp2; + + // synopsys translate_off + //------------------------------------------------------------------------- + // Parameter legality check + //------------------------------------------------------------------------- + + + + initial begin : parameter_check + integer param_err_flg; + + param_err_flg = 0; + + + if (A_width < 1) begin + param_err_flg = 1; + $display( + "ERROR: %m :\n Invalid value (%d) for parameter A_width (lower bound: 1)", + A_width ); + end + + if (B_width < 1) begin + param_err_flg = 1; + $display( + "ERROR: %m :\n Invalid value (%d) for parameter B_width (lower bound: 1)", + B_width ); + end + + if ( param_err_flg == 1) begin + $display( + "%m :\n Simulation aborted due to invalid parameter value(s)"); + $finish; + end + + end // parameter_check + + +assign temp_a = (A[A_width-1])? (~A + 1'b1) : A; +assign temp_b = (B[B_width-1])? (~B + 1'b1) : B; + +assign long_temp1 = temp_a * temp_b; +assign long_temp2 = ~(long_temp1 - 1'b1); + +assign PRODUCT = ((^(A ^ A) !== 1'b0) || (^(B ^ B) !== 1'b0) || (^(TC ^ TC) !== 1'b0) ) ? {A_width+B_width{1'bX}} : + (TC)? (((A[A_width-1] ^ B[B_width-1]) && (|long_temp1))? + {1'b1,long_temp2} : {1'b0,long_temp1}) + : A * B; + // synopsys translate_on +endmodule + + diff --git a/tb/chip_top/DW_mult_pipe.v b/tb/chip_top/DW_mult_pipe.v new file mode 100644 index 0000000..a99a7b9 --- /dev/null +++ b/tb/chip_top/DW_mult_pipe.v @@ -0,0 +1,357 @@ +//////////////////////////////////////////////////////////////////////////////// +// +// This confidential and proprietary software may be used only +// as authorized by a licensing agreement from Synopsys Inc. +// In the event of publication, the following notice is applicable: +// +// (C) COPYRIGHT 2002 - 2018 SYNOPSYS INC. +// ALL RIGHTS RESERVED +// +// The entire notice above must be reproduced on all authorized +// copies. +// +// AUTHOR: Rajeev Huralikoppi Feb 15, 2002 +// +// VERSION: Verilog Simulation Architecture +// +// DesignWare_version: 4e25d03d +// DesignWare_release: O-2018.06-DWBB_201806.3 +// +//////////////////////////////////////////////////////////////////////////////// +//----------------------------------------------------------------------------- +// ABSTRACT: An n stage pipelined multipler simulation model +// +// Parameters Valid Values Description +// ========== ========= =========== +// a_width >= 1 default: none +// Word length of a +// +// b_width >= 1 default: none +// Word length of b +// +// num_stages >= 2 default: 2 +// Number of pipelined stages +// +// stall_mode 0 or 1 default: 1 +// Stall mode +// 0 => non-stallable +// 1 => stallable +// +// rst_mode 0 to 2 default: 1 +// Reset mode +// 0 => no reset +// 1 => asynchronous reset +// 2 => synchronous reset +// +// op_iso_mode 0 to 4 default: 0 +// Type of operand isolation +// If 'stall_mode' is '0', this parameter is ignored and no isolation is applied +// 0 => Follow intent defined by Power Compiler user setting +// 1 => no operand isolation +// 2 => 'and' gate operand isolaton +// 3 => 'or' gate operand isolation +// 4 => preferred isolation style: 'and' +// +// +// Input Ports Size Description +// =========== ==== ============ +// clk 1 Clock +// rst_n 1 Reset, active low +// en 1 Register enable, active high +// tc 1 2's complement control +// a a_width Multiplier +// b b_width Multiplicand +// +// product a_width+b_width Product (a*b) +// +// MODIFIED: +// RJK 05/14/15 Updated model to work with less propagated 'X's +// so as to be more friendly with VCS-NLP +// +// RJK 05/28/13 Updated documentation in comments to properly +// describe the "en" input (STAR 9000627580) +// +// DLL 02/01/08 Enhanced abstract and added "op_iso_mode" parameter +// and related code. +// +// DLL 11/14/05 Changed legality checking of 'num_stages' +// parameter along with its abstract "Valid Values" +// +// +//----------------------------------------------------------------------------- + +module DW_mult_pipe (clk,rst_n,en,tc,a,b,product); + + parameter integer a_width = 2; + parameter integer b_width = 2; + parameter integer num_stages = 2; + parameter integer stall_mode = 1; + parameter integer rst_mode = 1; + parameter integer op_iso_mode = 0; + + + input clk; + input rst_n; + input [a_width-1 : 0] a; + input [b_width-1 : 0] b; + input tc; + input en; + + output [a_width+b_width-1: 0] product; + + reg [a_width-1 : 0] a_reg [0 : num_stages-2]; + reg [b_width-1 : 0] b_reg [0 : num_stages-2]; + reg tc_reg [0 : num_stages-2]; + + // synopsys translate_off + //--------------------------------------------------------------------------- + // Behavioral model + //--------------------------------------------------------------------------- + +generate + if (rst_mode == 0) begin : GEN_RSM_EQ_0 + + if (stall_mode == 0) begin : GEN_RM0_SM0 + always @(posedge clk) begin: rm0_sm0_pipe_reg_PROC + integer i; + + for(i= 0; i < num_stages-1; i=i+1) begin + if (i == 0) begin + a_reg[0] <= a; + b_reg[0] <= b; + tc_reg[0] <= tc; + end else begin + a_reg[i] <= a_reg[i-1]; + b_reg[i] <= b_reg[i-1]; + tc_reg[i] <= tc_reg[i-1]; + end + end // for (i= 0; i < num_stages-1; i++) + end // block: rm0_pipe_reg_PROC + end else begin : GEN_RM0_SM1 + always @(posedge clk) begin: rm0_sm1_pipe_reg_PROC + integer i; + + for(i= 0; i < num_stages-1; i=i+1) begin + if (i == 0) begin + a_reg[0] <= (en == 1'b0)? a_reg[0] : ((en == 1'b1)? a : {a_width{1'bx}}); + b_reg[0] <= (en == 1'b0)? b_reg[0] : ((en == 1'b1)? b : {b_width{1'bx}}); + tc_reg[0] <= (en == 1'b0)? tc_reg[0]: ((en == 1'b1)? tc: 1'bx); + end else begin + a_reg[i] <= (en == 1'b0)? a_reg[i] : ((en == 1'b1)? a_reg[i-1] : {a_width{1'bx}}); + b_reg[i] <= (en == 1'b0)? b_reg[i] : ((en == 1'b1)? b_reg[i-1] : {b_width{1'bx}}); + tc_reg[i] <= (en == 1'b0)? tc_reg[i]: ((en == 1'b1)? tc_reg[i-1]: 1'bx); + end + end + end + end + + end else if (rst_mode == 1) begin : GEN_RM_EQ_1 + + if (stall_mode == 0) begin : GEN_RM1_SM0 + always @(posedge clk or negedge rst_n) begin: rm1_pipe_reg_PROC + integer i; + + if (rst_n == 1'b0) begin + for (i= 0; i < num_stages-1; i=i+1) begin + a_reg[i] <= {a_width{1'b0}}; + b_reg[i] <= {b_width{1'b0}}; + tc_reg[i] <= 1'b0; + end // for (i= 0; i < num_stages-1; i++) + end else if (rst_n == 1'b1) begin + for(i= 0; i < num_stages-1; i=i+1) begin + if (i == 0) begin + a_reg[0] <= a; + b_reg[0] <= b; + tc_reg[0] <= tc; + end else begin + a_reg[i] <= a_reg[i-1]; + b_reg[i] <= b_reg[i-1]; + tc_reg[i] <= tc_reg[i-1]; + end + end // for (i= 0; i < num_stages-1; i++) + end else begin // rst_n not 1'b0 and not 1'b1 + for (i= 0; i < num_stages-1; i=i+1) begin + a_reg[i] <= {a_width{1'bx}}; + b_reg[i] <= {b_width{1'bx}}; + tc_reg[i] <= 1'bx; + end // for (i= 0; i < num_stages-1; i++) + end + end // block: rm1_pipe_reg_PROC + end else begin : GEN_RM1_SM1 + always @(posedge clk or negedge rst_n) begin: rm1_pipe_reg_PROC + integer i; + + if (rst_n == 1'b0) begin + for (i= 0; i < num_stages-1; i=i+1) begin + a_reg[i] <= {a_width{1'b0}}; + b_reg[i] <= {b_width{1'b0}}; + tc_reg[i] <= 1'b0; + end // for (i= 0; i < num_stages-1; i++) + end else if (rst_n == 1'b1) begin + for(i= 0; i < num_stages-1; i=i+1) begin + if (i == 0) begin + a_reg[0] <= (en == 1'b0)? a_reg[0] : ((en == 1'b1)? a : {a_width{1'bx}}); + b_reg[0] <= (en == 1'b0)? b_reg[0] : ((en == 1'b1)? b : {b_width{1'bx}}); + tc_reg[0] <= (en == 1'b0)? tc_reg[0]: ((en == 1'b1)? tc: 1'bx); + end else begin + a_reg[i] <= (en == 1'b0)? a_reg[i] : ((en == 1'b1)? a_reg[i-1] : {a_width{1'bx}}); + b_reg[i] <= (en == 1'b0)? b_reg[i] : ((en == 1'b1)? b_reg[i-1] : {b_width{1'bx}}); + tc_reg[i] <= (en == 1'b0)? tc_reg[i]: ((en == 1'b1)? tc_reg[i-1]: 1'bx); + end + end // for (i= 0; i < num_stages-1; i++) + end else begin // rst_n not 1'b0 and not 1'b1 + for (i= 0; i < num_stages-1; i=i+1) begin + a_reg[i] <= {a_width{1'bx}}; + b_reg[i] <= {b_width{1'bx}}; + tc_reg[i] <= 1'bx; + end // for (i= 0; i < num_stages-1; i++) + end + end // block: rm1_pipe_reg_PROC + end + + end else begin : GEN_RM_GT_1 + + if (stall_mode == 0) begin : GEN_RM2_SM0 + always @(posedge clk) begin: rm2_pipe_reg_PROC + integer i; + + if (rst_n == 1'b0) begin + for (i= 0; i < num_stages-1; i=i+1) begin + a_reg[i] <= {a_width{1'b0}}; + b_reg[i] <= {b_width{1'b0}}; + tc_reg[i] <= 1'b0; + end // for (i= 0; i < num_stages-1; i++) + end else if (rst_n == 1'b1) begin + for(i= 0; i < num_stages-1; i=i+1) begin + if (i == 0) begin + a_reg[0] <= a; + b_reg[0] <= b; + tc_reg[0] <= tc; + end else begin + a_reg[i] <= a_reg[i-1]; + b_reg[i] <= b_reg[i-1]; + tc_reg[i] <= tc_reg[i-1]; + end + end // for (i= 0; i < num_stages-1; i++) + end else begin // rst_n not 1'b0 and not 1'b1 + for (i= 0; i < num_stages-1; i=i+1) begin + a_reg[i] <= {a_width{1'bx}}; + b_reg[i] <= {b_width{1'bx}}; + tc_reg[i] <= 1'bx; + end // for (i= 0; i < num_stages-1; i++) + end + end // block: rm2_pipe_reg_PROC + end else begin : GEN_RM2_SM1 + always @(posedge clk) begin: rm2_pipe_reg_PROC + integer i; + + if (rst_n == 1'b0) begin + for (i= 0; i < num_stages-1; i=i+1) begin + a_reg[i] <= {a_width{1'b0}}; + b_reg[i] <= {b_width{1'b0}}; + tc_reg[i] <= 1'b0; + end // for (i= 0; i < num_stages-1; i++) + end else if (rst_n == 1'b1) begin + for(i= 0; i < num_stages-1; i=i+1) begin + if (i == 0) begin + a_reg[0] <= (en == 1'b0)? a_reg[0] : ((en == 1'b1)? a : {a_width{1'bx}}); + b_reg[0] <= (en == 1'b0)? b_reg[0] : ((en == 1'b1)? b : {b_width{1'bx}}); + tc_reg[0] <= (en == 1'b0)? tc_reg[0]: ((en == 1'b1)? tc: 1'bx); + end else begin + a_reg[i] <= (en == 1'b0)? a_reg[i] : ((en == 1'b1)? a_reg[i-1] : {a_width{1'bx}}); + b_reg[i] <= (en == 1'b0)? b_reg[i] : ((en == 1'b1)? b_reg[i-1] : {b_width{1'bx}}); + tc_reg[i] <= (en == 1'b0)? tc_reg[i]: ((en == 1'b1)? tc_reg[i-1]: 1'bx); + end + end // for (i= 0; i < num_stages-1; i++) + end else begin // rst_n not 1'b0 and not 1'b1 + for (i= 0; i < num_stages-1; i=i+1) begin + a_reg[i] <= {a_width{1'bx}}; + b_reg[i] <= {b_width{1'bx}}; + tc_reg[i] <= 1'bx; + end // for (i= 0; i < num_stages-1; i++) + end + end // block: rm2_pipe_reg_PROC + end + + end +endgenerate + + DW02_mult #(a_width, b_width) + U1 (.A(a_reg[num_stages-2]), + .B(b_reg[num_stages-2]), + .TC(tc_reg[num_stages-2]), + .PRODUCT(product)); + //--------------------------------------------------------------------------- + // Parameter legality check and initializations + //--------------------------------------------------------------------------- + + + initial begin : parameter_check + integer param_err_flg; + + param_err_flg = 0; + + + if (a_width < 1) begin + param_err_flg = 1; + $display( + "ERROR: %m :\n Invalid value (%d) for parameter a_width (lower bound: 1)", + a_width ); + end + + if (b_width < 1) begin + param_err_flg = 1; + $display( + "ERROR: %m :\n Invalid value (%d) for parameter b_width (lower bound: 1)", + b_width ); + end + + if (num_stages < 2) begin + param_err_flg = 1; + $display( + "ERROR: %m :\n Invalid value (%d) for parameter num_stages (lower bound: 2)", + num_stages ); + end + + if ( (stall_mode < 0) || (stall_mode > 1) ) begin + param_err_flg = 1; + $display( + "ERROR: %m :\n Invalid value (%d) for parameter stall_mode (legal range: 0 to 1)", + stall_mode ); + end + + if ( (rst_mode < 0) || (rst_mode > 2) ) begin + param_err_flg = 1; + $display( + "ERROR: %m :\n Invalid value (%d) for parameter rst_mode (legal range: 0 to 2)", + rst_mode ); + end + + if ( (op_iso_mode < 0) || (op_iso_mode > 4) ) begin + param_err_flg = 1; + $display( + "ERROR: %m :\n Invalid value (%d) for parameter op_iso_mode (legal range: 0 to 4)", + op_iso_mode ); + end + + if ( param_err_flg == 1) begin + $display( + "%m :\n Simulation aborted due to invalid parameter value(s)"); + $finish; + end + + end // parameter_check + + + //--------------------------------------------------------------------------- + // Report unknown clock inputs + //--------------------------------------------------------------------------- + + always @ (clk) begin : clk_monitor + if ( (clk !== 1'b0) && (clk !== 1'b1) && ($time > 0) ) + $display( "WARNING: %m :\n at time = %t, detected unknown value, %b, on clk input.", + $time, clk ); + end // clk_monitor + + // synopsys translate_on +endmodule // diff --git a/tb/chip_top/Makefile b/tb/chip_top/Makefile new file mode 100644 index 0000000..6c048e4 --- /dev/null +++ b/tb/chip_top/Makefile @@ -0,0 +1,17 @@ +VCS = vcs -full64 -sverilog +lint=TFIPC-L +v2k -debug_access+all +define+DUMP_FSDB -lca -q -timescale=1ns/1ps +nospecify -P /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/pli.a -l compile.log + +SIMV = ./simv -l sim.log + +all:comp run + +comp: + ${VCS} -f files.f + +run: + ${SIMV} + +dbg: + verdi -sverilog -f files.f -top TB -nologo & + +clean: + rm -rf DVE* simv* *log ucli.key verdiLog urgReport csrc novas.* *.fsdb *.dat *.daidir *.vdb *~ diff --git a/tb/chip_top/TB.sv b/tb/chip_top/TB.sv new file mode 100644 index 0000000..e69f2b5 --- /dev/null +++ b/tb/chip_top/TB.sv @@ -0,0 +1,1459 @@ + + +`include "chip_define.v" + +`timescale 1ps/10fs + +//-----------AWG out NCO data------------------ +//1'b0:normal data; 1'b1: NCO data +`define AWG_OUT 1'b0 +//-------Configure chip role------------------- +//2'b00:XY's Chiop at AC Mode +//2'b11:Z's Chiop at DC Mode +`define ROLE 2'b00 + +//-------Interpolation------------------------- +//Set the interpolation factor +//3'b000:x1;3'b001:x2;3'b010:x4; +//3'b011:x8;3'b100:x16; +`define INTP_MODE 3'b100 + +//-----------QAM mode-------------------------- +//Set the mixer output to the mixed signal +//2'b00:bypass;2'b01:mix; +//2'b10:cos;2'b11:sin; +`define QAM_MODE 2'b01 + +//-----------sideband select------------------- +//Set the mixer to upper sideband modulation +//1'b1:Upper sideband;1'b0:Lower sideband; +`define MIX_SIDEBAND 1'b1 + +//-----------DAC data format-------------------- +//Set the DAC data format to normal mode +//2'b00:NRZ mode;2'b01:MIX mode; +//2'b10:2xNRZ mode;2'b11:reserve; +`define DAC_FORMAT 2'b11 + +//-----------CH0 FeedBack-------------------- +//Set the DAC data format to normal mode +//2'b00:0 state;2'b01:1 state; +//2'b10:2 state;2'b11:reserve; +`define CH0_FB 2'b10 + +//-----------DSP Always on-------------------- +//1'b0 --> dsp output data vaild depend on awg vaild; +//1'b1 --> dsp output data always vaild; +`define DSPAO 1'b0 + + + +//define Instr and Envelope ID and envelope data +//Instr mem +//`define MCU_INSTR_FILE "../../cfgdata/instrmem/awg_inst.txt" +//`define MCU_INSTR_FILE "../../cfgdata/instrmem/LongFlattop_bin.txt" +//`define MCU_INSTR_FILE "../../cfgdata/instrmem/LongFlattopAmpAdj_bin.txt" +//`define MCU_INSTR_FILE "../../cfgdata/instrmem/LongRectangle_bin.txt" +//`define MCU_INSTR_FILE "../../cfgdata/instrmem/LongRectangle50us_bin.txt" +//`define MCU_INSTR_FILE "../../cfgdata/instrmem/SingleWaveACCZ_bin.txt" +//`define MCU_INSTR_FILE "../../cfgdata/instrmem/SingleWaveCombine_bin.txt" +//`define MCU_INSTR_FILE "../../cfgdata/instrmem/SingleWaveCosine_bin.txt" +//`define MCU_INSTR_FILE "../../cfgdata/instrmem/SingleWaveFlattop_bin.txt" +//`define MCU_INSTR_FILE "../../cfgdata/instrmem/SingleWaveRectangle_bin.txt" +//`define MCU_INSTR_FILE "../../cfgdata/instrmem/WaveHold_bin.txt" +//`define MCU_INSTR_FILE "../../cfgdata/instrmem/Condition_bin.txt" +//`define MCU_INSTR_FILE "../../cfgdata/instrmem/RabiFreqAmp_bin.txt" +//`define MCU_INSTR_FILE "../../cfgdata/instrmem/WaveHoldSingle_bin.txt" +`define MCU_INSTR_FILE "../../cfgdata/instrmem/Cosine9_bin.txt" + +//data mem +//`define MCU_DATA_FILE "../../cfgdata/datamem/awg_data.txt" +//`define MCU_DATA_FILE "../../cfgdata/datamem/Condition_data_bin.txt" +//`define MCU_DATA_FILE "../../cfgdata/datamem/RabiFreqAmp_data_bin.txt" +`define MCU_DATA_FILE "../../cfgdata/datamem/Cosine9_data_bin.txt" + +//Envelope ID mem +`define ENVE_ID_FILE "../../cfgdata/enveindex/wave_index_13.txt" + +//Envelope mem +`define ENVE_DATA_FILE "../../cfgdata/envemem/wave_bin_13.txt" + +//read data +`define READ_FILE "../../cfgdata/envemem/rwave_bin_12.txt" + +`define CHIIPID 5'b0_0000 +`define SYSREG_BASEADDR 25'h000_0000 +`define CH0_ITCM_BASEADDR 25'h010_0000 +`define CH0_DTCM_BASEADDR 25'h020_0000 +`define CH0_CTRLREG_BASEADDR 25'h030_0000 +`define CH0_ENVEID_BASEADDR 25'h040_0000 +`define CH0_ENVEMEM_BASEADDR 25'h050_0000 +`define CH0_DACREG_BASEADDR 25'h060_0000 +`define PLL_BASEADDR 25'h1F0_0000 + +`define SYS_PERIOD 83.33 +`define MAIN_PERIOD `SYS_PERIOD * 16 +`define SCLK_PERIOD 3 * `MAIN_PERIOD +`define CSN2SCLK_TIME 3ns +class BinaryDataReader; + + // 定义一个ä½é˜Ÿåˆ—æ¥å­˜å‚¨ä»ŽTXT文件中读å–çš„32ä½äºŒè¿›åˆ¶æ•°æ®çš„æ¯ä¸€ä½ + bit spi_data_queue[$]; + + // 定义一个方法，用于读å–TXT文件并将32ä½äºŒè¿›åˆ¶æ•°æ®æŒ‰æ¯”特存储到队列中 + function void read_txt_file(input string filename); + int file_id; + string line; + bit [31:0] binary_value; + int i; + + // æ‰“å¼€æ–‡ä»¶ä»¥è¿›è¡Œè¯»å– + file_id = $fopen(filename, "r"); + if (file_id == 0) begin + $display("Error: Failed to open file %s", filename); + return; + end + + // 读å–文件的æ¯ä¸€è¡Œï¼Œå¹¶å°†å…¶ä½œä¸º32ä½äºŒè¿›åˆ¶æ•°æ®æ·»åŠ åˆ°é˜Ÿåˆ—中 + while (!$feof(file_id)) begin + //if ($fgets(line, file_id)) begin + $fscanf(file_id,"%b\n",binary_value); + for (i = 31; i >= 0; i--) begin + spi_data_queue.push_back(binary_value[i]); + end + //end + end + + // 关闭文件 + $fclose(file_id); + endfunction + + function void get_data_queue(ref bit data_queue[$]); + data_queue = spi_data_queue; + spi_data_queue.delete(); + endfunction + +endclass + +class spi_data_send; + virtual spi_if spi_intf; + task send_item(bit data_queue[], virtual spi_if spi_intf); + + //ToDo + //wait(spi_intf.rstn); + #(`SCLK_PERIOD/3); + spi_intf.csn <= 1'b1; + spi_intf.sclk <= 1'b1; + #(`SCLK_PERIOD/3); + spi_intf.csn <= 1'b0; + #(`SCLK_PERIOD/3); + foreach(data_queue[i]) begin + spi_intf.mosi <= data_queue[i]; + spi_intf.sclk <= ~spi_intf.sclk; + #(`SCLK_PERIOD/2); + spi_intf.sclk <= ~spi_intf.sclk; + #(`SCLK_PERIOD/2); + end + spi_intf.sclk <= 1'b1; + #(`SCLK_PERIOD/3); + spi_intf.csn <= 1'b1; + #(`SCLK_PERIOD/3); + endtask : send_item + +endclass + + +class spi_reg; + virtual spi_if spi_intf; + bit spi_reg_queue[$]; + bit [63:0] write_item; + int i; + task write_reg(bit cmd, bit[24:0] addr, bit[4:0] chipid, bit[31:0] data, virtual spi_if spi_intf); + write_item = {cmd,addr,chipid,1'b0,data}; + $display("write_item %b", write_item); + for (i = 63; i >= 0; i--) begin + spi_reg_queue.push_back(write_item[i]); + $display("write_item %0d: %b", i, write_item[i]); + end + foreach (spi_reg_queue[i]) begin + $display("reg %0d: %b", i, spi_reg_queue[i]); + end + //ToDo + //wait(spi_intf.rstn); + #(`SCLK_PERIOD/3); + spi_intf.csn <= 1'b1; + spi_intf.sclk <= 1'b1; + #(`SCLK_PERIOD/3); + spi_intf.csn <= 1'b0; + #(`SCLK_PERIOD/3); + foreach(spi_reg_queue[i]) begin + spi_intf.mosi <= spi_reg_queue[i]; + spi_intf.sclk <= ~spi_intf.sclk; + #(`SCLK_PERIOD/2); + spi_intf.sclk <= ~spi_intf.sclk; + #(`SCLK_PERIOD/2); + end + //spi_intf.sclk <= ~spi_intf.sclk; + // #(`SCLK_PERIOD/2); + spi_intf.sclk <= 1'b1; + #(`SCLK_PERIOD/3); + spi_intf.csn <= 1'b1; + #100ns; + spi_reg_queue.delete(); + endtask : write_reg + +endclass + + +module TB; + +parameter WRITE = 1'b0 , + READ = 1'b1 ; + + virtual spi_if vif; + + // 实例化TextFileReaderç±» + BinaryDataReader data_reader = new(); + spi_data_send spi_send = new(); + spi_reg reg_wr = new(); + + +//====================================================================== +initial begin + $fsdbAutoSwitchDumpfile(500, "./verdplus.fsdb", 1000000); + $fsdbDumpvars(); +end +//====================================================================== +//clock & reset & bootsel +//====================================================================== +logic clk ; +logic rstn ; +logic clk_rstn ; +logic qbmcu_i_start ; +bit data[$]; +//parameter SYS_PERIOD = 2; +//sys_clk --> 50M, 0 phase +initial begin + clk =0; + forever # (`SYS_PERIOD/2) clk = ~clk; +end + + +//hresetn +initial begin + clk_rstn = 0; + rstn = 0; + #1000; + clk_rstn = 0; + #1000; + clk_rstn = 1; + #1000; + rstn = 1; + // $display("m%"); +end + +spi_if aif(.*); + + + +initial begin + aif.sclk = 1'b1; + aif.mosi = 1'b0; + aif.csn = 1'b1; + vif = aif; +end +initial begin + qbmcu_i_start = 1'b0; + + wait (rstn); + +//////////////////////////////////////////////////////////// +//reg cfg +//////////////////////////////////////////////////////////// + +//-----------------debug------------------------------ +//DBGCFGR 16'h34 +// dbg_enable = dbgcfgr[0]; 1'b0 -> disable; 1'b1 -> enable; +// dbg_data_sel = dbgcfgr[1]; 1'b0-->mod;1'b1-->dsp +// dbg_ch_sel = dbgcfgr[5:2]; //4'b0001-->ch0;4'b0010-->ch1; + //4'b0100-->ch2;4'b1000-->ch3; +//6'b0001_0_1 + +reg_wr.write_reg(WRITE,`SYSREG_BASEADDR+32'h34,`CHIIPID,32'h00000007,vif); + +#100; + +reg_wr.write_reg(READ,`SYSREG_BASEADDR+32'h0,`CHIIPID,32'h00000007,vif); + + + + + +//[0]-> 1'b1:Synchronous clear enable for the clock divider +//[1]-> 1'b1:Enable synchronous signal output +reg_wr.write_reg(WRITE,`PLL_BASEADDR+32'h4c,`CHIIPID,{16'h3,16'h0},vif); +#100; +reg_wr.write_reg(WRITE,`PLL_BASEADDR+32'h30,`CHIIPID,{16'h8008,16'h0},vif); +#100; +reg_wr.write_reg(READ ,`PLL_BASEADDR+32'h4c,`CHIIPID,{16'h3,16'h0},vif); +#100; +reg_wr.write_reg(READ ,`PLL_BASEADDR+32'h30,`CHIIPID,{16'h3,16'h0},vif); + +reg_wr.write_reg(WRITE,`PLL_BASEADDR+32'h4c,`CHIIPID,{16'h2,16'h0},vif); + +reg_wr.write_reg(WRITE,`PLL_BASEADDR+32'h50,`CHIIPID,{16'h0,16'h0},vif); +//Set the chip role to XY + +reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h128,`CHIIPID,`ROLE,vif); + +//dsp always on off +reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h138,`CHIIPID,`DSPAO,vif); + + + +//Set the chip role to Z & DC mode +//reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h128,`CHIIPID,32'h0000_0003,vif); + + +//---------------------------INTP---------------------------------------------- + +//Set the interpolation factor +//3'b000:x1;3'b001:x2;3'b010:x4; +//3'b011:x8;3'b100:x16; + +reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h104,`CHIIPID,`INTP_MODE,vif); + +//---------------------------INTP---------------------------------------------- + +//Enable synchronous clearing for the mixing NCO +reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h12C,`CHIIPID,32'h0000_0001,vif); + +//Set the output data type of the modulator +//1'b0 --> mod modem data; 1'b1 --> mod nco data for XY DAC +//1'b0 --> Z dsp data; 1'b1 --> XY dsp data for Z DAC +reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h130,`CHIIPID,`AWG_OUT,vif); + +//Set the carrier frequency of the mixing NCO (5GHz) +reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h10c,`CHIIPID,32'h6888_8888,vif); +reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h110,`CHIIPID,32'h8889_0000,vif); + +//Set the mixer to upper sideband modulation +//1'b0:Upper sideband;1'b1:Lower sideband; +reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h118,`CHIIPID,`MIX_SIDEBAND,vif); + +//Set the mixer output to the mixed signal +//2'b00:bypass;2'b01:mix; +//2'b10:cos;2'b11:sin; +reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h11c,`CHIIPID,`QAM_MODE,vif); + +//Set the DAC data format to normal mode +reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h120,`CHIIPID,`DAC_FORMAT,vif); +//2'b00:NRZ mode;2'b01:MIX mode; +//2'b10:2xNRZ mode;2'b00:reserve; + + // 调用read_txt_file方法读å–TXT文件 + data_reader.read_txt_file(`MCU_INSTR_FILE); + + // 获å–æ•°æ®é˜Ÿåˆ—并打å°å…¶å†…容 + //bit data[$]; + data_reader.get_data_queue(data); + + foreach (data[i]) begin + $display("Line %0d: %b", i, data[i]); + end + $display("Send MCU_INSTR_FILE"); + spi_send.send_item(data,vif); + data.delete(); + #100; + + // 调用read_txt_file方法读å–TXT文件 + data_reader.read_txt_file(`MCU_DATA_FILE); + + // 获å–æ•°æ®é˜Ÿåˆ—并打å°å…¶å†…容 + //bit data[$]; + data_reader.get_data_queue(data); + + foreach (data[i]) begin + $display("Line %0d: %b", i, data[i]); + end + $display("Send MCU_INSTR_FILE"); + spi_send.send_item(data,vif); + data.delete(); + #100; + + + data_reader.read_txt_file(`ENVE_ID_FILE); + data_reader.get_data_queue(data); + foreach (data[i]) begin + $display("Line %0d: %b", i, data[i]); + end + $display("Send ENVE_ID_FILE"); + spi_send.send_item(data,vif); + data.delete(); + #100; + + data_reader.read_txt_file(`ENVE_DATA_FILE); + data_reader.get_data_queue(data); + foreach (data[i]) begin + $display("Line %0d: %b", i, data[i]); + end + $display("Send ENVE_DATA1_FILE"); + spi_send.send_item(data,vif); + data.delete(); + + #100; + + + + #100; + qbmcu_i_start = 1'b1; + #500000; + qbmcu_i_start = 1'b0; + + #100000; + + data_reader.read_txt_file(`READ_FILE); + data_reader.get_data_queue(data); + + #1000000; +reg_wr.write_reg(WRITE,`SYSREG_BASEADDR+32'h34,`CHIIPID,32'h00000000,vif); + foreach (data[i]) begin + $display("Line %0d: %b", i, data[i]); + end + $display("Send READ_FILE"); + spi_send.send_item(data,vif); + data.delete(); +end + + + +/////////////////////////////////////////////////////////////////////////////////////////// +//clk gen +/////////////////////////////////////////////////////////////////////////////////////////// +wire clk_div16_0; +wire clk_div16_1; +wire clk_div16_2; +wire clk_div16_3; +wire clk_div16_4; +wire clk_div16_5; +wire clk_div16_6; +wire clk_div16_7; +wire clk_div16_8; +wire clk_div16_9; +wire clk_div16_a; +wire clk_div16_b; +wire clk_div16_c; +wire clk_div16_d; +wire clk_div16_e; +wire clk_div16_f; + + +clk_gen inst_clk_gen( + .rstn (clk_rstn ) + ,.clk (clk ) + ,.clk_div16_0 (clk_div16_0 ) + ,.clk_div16_1 (clk_div16_1 ) + ,.clk_div16_2 (clk_div16_2 ) + ,.clk_div16_3 (clk_div16_3 ) + ,.clk_div16_4 (clk_div16_4 ) + ,.clk_div16_5 (clk_div16_5 ) + ,.clk_div16_6 (clk_div16_6 ) + ,.clk_div16_7 (clk_div16_7 ) + ,.clk_div16_8 (clk_div16_8 ) + ,.clk_div16_9 (clk_div16_9 ) + ,.clk_div16_a (clk_div16_a ) + ,.clk_div16_b (clk_div16_b ) + ,.clk_div16_c (clk_div16_c ) + ,.clk_div16_d (clk_div16_d ) + ,.clk_div16_e (clk_div16_e ) + ,.clk_div16_f (clk_div16_f ) + ,.clk_h (clk_h ) + ,.clk_l (clk_l ) + ); + + + +//////////////////////////////////////////////////////////////////////////////////////// +//DUT +//////////////////////////////////////////////////////////////////////////////////////// +wire async_rstn = rstn; +wire por_rstn = 1'b1; +logic sync_out ; +logic [1 :0] ch0_feedback = `CH0_FB; +wire [4 :0] cfgid = 5'b00000; +logic irq; + +//------------------------------PLL cfg pin---------------------------------------------------- +logic ref_sel ; // Clock source selection for a frequency divider; + // 1'b0:External clock source + // 1'b1:internal phase-locked loop clock source +logic ref_en ; // Input reference clock enable + // 1'b0:enable,1'b1:disable +logic ref_s2d_en ; // Referenced clock differential to single-ended conversion enable + // 1'b0:enable,1'b1:disable +logic [6 :0] p_cnt ; // P counter +logic pfd_delay ; // PFD Dead Zone +logic pfd_dff_Set ; // Setting the PFD register,active high +logic pfd_dff_4and ; // PFD output polarity +logic [3 :0] spd_div ; // SPD Frequency Divider +logic spd_pulse_width ; // Pulse Width of SPD +logic spd_pulse_sw ; // Pulse sw of SPD +logic cpc_sel ; // current source selection +logic [1 :0] swcp_i ; // PTAT current switch +logic [3 :0] sw_ptat_r ; // PTAT current adjustment +logic [1 :0] sw_fll_cpi ; // Phase-locked loop charge pump current +logic sw_fll_delay ; // PLL Dead Zone +logic pfd_sel ; // PFD Loop selection +logic spd_sel ; // SPD Loop selection +logic fll_sel ; // FLL Loop selection +logic vco_tc ; // VCO temperature compensation +logic vco_tcr ; // VCO temperature compensation resistor +logic vco_gain_adj ; // VCO gain adjustment +logic vco_gain_adj_r ; // VCO gain adjustment resistor +logic [2 :0] vco_cur_adj ; // VCO current adjustment +logic vco_buff_en ; // VCO buff enable,active high +logic vco_en ; // VCO enable,active high +logic [2 :0] pll_dpwr_adj ; // PLL frequency division output power adjustment +logic [6 :0] vco_fb_adj ; // VCO frequency band adjustment +logic afc_en ; // AFC enable +logic afc_shutdown ; // AFC module shutdown signal +logic [0 :0] afc_det_speed ; // AFC detection speed +logic [0 :0] flag_out_sel ; // Read and choose the signs +logic afc_reset ; // AFC reset +logic [10 :0] afc_cnt ; // AFC frequency band adjustment function counter + // counting time adjustment +logic [10 :0] afc_ld_cnt ; // Adjust the counting time of the AFC lock detection + // feature counter +logic [3 :0] afc_pres ; // Adjusting the resolution of the AFC comparator +logic [14 :0] afc_ld_tcc ; // AFC Lock Detection Function Target Cycle Count +logic [14 :0] afc_fb_tcc ; // Target number of cycles for AFC frequency band + // adjustment function +logic sync_clr ; // PLL div sync clr,low active +logic pll_rstn ; // PLL reset,active low +logic [0 :0] div_rstn_sel ; // div rstn select, 1'b0: ext clear, 1'b1:inter pll lock +logic [1 :0] test_clk_sel ; // test clk select, 2'b00:DIV1 clk, 2'b01:DIV2 clk, 2'b10:DIV4 clk, 2'b11:DIV8 clk +logic [0 :0] test_clk_oen ; // test clk output enable, 1'b0:disenable, 1'b1:enable +logic [7 :0] dig_clk_sel ; // digital main clk select, one hot code,bit[0]-->0 degree phase,bit[1]-->45 degree phase.....bit[7]-->315degree phae +logic clkrx_pdn ; +logic pll_lock = 1'b1 ; // PLL LOCK + +//DAC cfg +logic [2 :0] ch0_dac_addr ; +logic [2 :0] ch0_dac_dw ; +logic [8 :0] ch0_dac_ref ; +logic [16 :0] ch0_dac_Prbs_rst0 ; +logic [16 :0] ch0_dac_Prbs_set0 ; +logic [16 :0] ch0_dac_Prbs_rst1 ; +logic [16 :0] ch0_dac_Prbs_set1 ; +logic ch0_dac_Cal_sig ; +logic ch0_dac_Cal_rstn ; +logic ch1_dac_Cal_div_rstn; +logic ch0_dac_Cal_end = 1'b1 ; + +//DSP output +//`ifdef CHANNEL_XY_ON +logic [15 :0] ch0_xy_dsp_dout0 ; +logic [15 :0] ch0_xy_dsp_dout1 ; +logic [15 :0] ch0_xy_dsp_dout2 ; +logic [15 :0] ch0_xy_dsp_dout3 ; +logic [15 :0] ch0_xy_dsp_dout4 ; +logic [15 :0] ch0_xy_dsp_dout5 ; +logic [15 :0] ch0_xy_dsp_dout6 ; +logic [15 :0] ch0_xy_dsp_dout7 ; +logic [15 :0] ch0_xy_dsp_dout8 ; +logic [15 :0] ch0_xy_dsp_dout9 ; +logic [15 :0] ch0_xy_dsp_dout10 ; +logic [15 :0] ch0_xy_dsp_dout11 ; +logic [15 :0] ch0_xy_dsp_dout12 ; +logic [15 :0] ch0_xy_dsp_dout13 ; +logic [15 :0] ch0_xy_dsp_dout14 ; +logic [15 :0] ch0_xy_dsp_dout15 ; +//`endif +//`ifdef CHANNEL_Z_ON +logic [15 :0] ch0_z_dsp_dout0 ; +logic [15 :0] ch0_z_dsp_dout1 ; +logic [15 :0] ch0_z_dsp_dout2 ; +logic [15 :0] ch0_z_dsp_dout3 ; +//`endif + `ifdef CHANNEL_XY_ON +logic [14:0] ch0_xy_A_DEM_MSB_OUT0 ; +logic [14:0] ch0_xy_A_DEM_MSB_OUT1 ; +logic [14:0] ch0_xy_A_DEM_MSB_OUT2 ; +logic [14:0] ch0_xy_A_DEM_MSB_OUT3 ; +logic [14:0] ch0_xy_A_DEM_MSB_OUT4 ; +logic [14:0] ch0_xy_A_DEM_MSB_OUT5 ; +logic [14:0] ch0_xy_A_DEM_MSB_OUT6 ; +logic [14:0] ch0_xy_A_DEM_MSB_OUT7 ; +logic [14:0] ch0_xy_B_DEM_MSB_OUT0 ; +logic [14:0] ch0_xy_B_DEM_MSB_OUT1 ; +logic [14:0] ch0_xy_B_DEM_MSB_OUT2 ; +logic [14:0] ch0_xy_B_DEM_MSB_OUT3 ; +logic [14:0] ch0_xy_B_DEM_MSB_OUT4 ; +logic [14:0] ch0_xy_B_DEM_MSB_OUT5 ; +logic [14:0] ch0_xy_B_DEM_MSB_OUT6 ; +logic [14:0] ch0_xy_B_DEM_MSB_OUT7 ; +logic [6 :0] ch0_xy_A_DEM_ISB_OUT0 ; +logic [6 :0] ch0_xy_A_DEM_ISB_OUT1 ; +logic [6 :0] ch0_xy_A_DEM_ISB_OUT2 ; +logic [6 :0] ch0_xy_A_DEM_ISB_OUT3 ; +logic [6 :0] ch0_xy_A_DEM_ISB_OUT4 ; +logic [6 :0] ch0_xy_A_DEM_ISB_OUT5 ; +logic [6 :0] ch0_xy_A_DEM_ISB_OUT6 ; +logic [6 :0] ch0_xy_A_DEM_ISB_OUT7 ; +logic [6 :0] ch0_xy_B_DEM_ISB_OUT0 ; +logic [6 :0] ch0_xy_B_DEM_ISB_OUT1 ; +logic [6 :0] ch0_xy_B_DEM_ISB_OUT2 ; +logic [6 :0] ch0_xy_B_DEM_ISB_OUT3 ; +logic [6 :0] ch0_xy_B_DEM_ISB_OUT4 ; +logic [6 :0] ch0_xy_B_DEM_ISB_OUT5 ; +logic [6 :0] ch0_xy_B_DEM_ISB_OUT6 ; +logic [6 :0] ch0_xy_B_DEM_ISB_OUT7 ; +logic [8 :0] ch0_xy_A_DEM_LSB_OUT0 ; +logic [8 :0] ch0_xy_A_DEM_LSB_OUT1 ; +logic [8 :0] ch0_xy_A_DEM_LSB_OUT2 ; +logic [8 :0] ch0_xy_A_DEM_LSB_OUT3 ; +logic [8 :0] ch0_xy_A_DEM_LSB_OUT4 ; +logic [8 :0] ch0_xy_A_DEM_LSB_OUT5 ; +logic [8 :0] ch0_xy_A_DEM_LSB_OUT6 ; +logic [8 :0] ch0_xy_A_DEM_LSB_OUT7 ; +logic [8 :0] ch0_xy_B_DEM_LSB_OUT0 ; +logic [8 :0] ch0_xy_B_DEM_LSB_OUT1 ; +logic [8 :0] ch0_xy_B_DEM_LSB_OUT2 ; +logic [8 :0] ch0_xy_B_DEM_LSB_OUT3 ; +logic [8 :0] ch0_xy_B_DEM_LSB_OUT4 ; +logic [8 :0] ch0_xy_B_DEM_LSB_OUT5 ; +logic [8 :0] ch0_xy_B_DEM_LSB_OUT6 ; +logic [8 :0] ch0_xy_B_DEM_LSB_OUT7 ; +`endif +`ifdef CHANNEL_Z_ON +logic [14 :0] ch0_z_DEM_MSB_OUT0 ; +logic [14 :0] ch0_z_DEM_MSB_OUT1 ; +logic [14 :0] ch0_z_DEM_MSB_OUT2 ; +logic [14 :0] ch0_z_DEM_MSB_OUT3 ; +logic [6 :0] ch0_z_DEM_ISB_OUT0 ; +logic [6 :0] ch0_z_DEM_ISB_OUT1 ; +logic [6 :0] ch0_z_DEM_ISB_OUT2 ; +logic [6 :0] ch0_z_DEM_ISB_OUT3 ; +logic [8 :0] ch0_z_DEM_LSB_OUT0 ; +logic [8 :0] ch0_z_DEM_LSB_OUT1 ; +logic [8 :0] ch0_z_DEM_LSB_OUT2 ; +logic [8 :0] ch0_z_DEM_LSB_OUT3 ; +`endif + + + + + + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +xyz_chip_top U_xyz_chip_top ( + .clk ( clk_div16_0 ) + ,.por_rstn ( por_rstn ) + ,.PI_async_rstn ( async_rstn ) + ,.PI_sync_in ( qbmcu_i_start ) + ,.PO_sync_out ( sync_out ) + ,.PI_ch0_feedback ( ch0_feedback ) + `ifdef CHANNEL_IS_FOUR + ,.PI_ch1_feedback ( ch1_feedback ) + ,.PI_ch2_feedback ( ch2_feedback ) + ,.PI_ch3_feedback ( ch3_feedback ) + `endif + ,.PI_cfgid ( cfgid ) + ,.PI_sclk ( aif.sclk ) + ,.PI_csn ( aif.csn ) + ,.PI_mosi ( aif.mosi ) + ,.PO_miso ( aif.miso ) + ,.PO_irq ( irq ) + ,.ref_sel ( ref_sel ) + ,.ref_en ( ref_en ) + ,.ref_s2d_en ( ref_s2d_en ) + ,.p_cnt ( p_cnt ) + ,.pfd_delay ( pfd_delay ) + ,.pfd_dff_Set ( pfd_dff_Set ) + ,.pfd_dff_4and ( pfd_dff_4and ) + ,.spd_div ( spd_div ) + ,.spd_pulse_width ( spd_pulse_width ) + ,.spd_pulse_sw ( spd_pulse_sw ) + ,.cpc_sel ( cpc_sel ) + ,.swcp_i ( swcp_i ) + ,.sw_ptat_r ( sw_ptat_r ) + ,.sw_fll_cpi ( sw_fll_cpi ) + ,.sw_fll_delay ( sw_fll_delay ) + ,.pfd_sel ( pfd_sel ) + ,.spd_sel ( spd_sel ) + ,.fll_sel ( fll_sel ) + ,.vco_tc ( vco_tc ) + ,.vco_tcr ( vco_tcr ) + ,.vco_gain_adj ( vco_gain_adj ) + ,.vco_gain_adj_r ( vco_gain_adj_r ) + ,.vco_cur_adj ( vco_cur_adj ) + ,.vco_buff_en ( vco_buff_en ) + ,.vco_en ( vco_en ) + ,.pll_dpwr_adj ( pll_dpwr_adj ) + ,.vco_fb_adj ( vco_fb_adj ) + ,.afc_en ( afc_en ) + ,.afc_shutdown ( afc_shutdown ) + ,.afc_det_speed ( afc_det_speed ) + ,.flag_out_sel ( flag_out_sel ) + ,.afc_reset ( afc_reset ) + ,.afc_cnt ( afc_cnt ) + ,.afc_ld_cnt ( afc_ld_cnt ) + ,.afc_pres ( afc_pres ) + ,.afc_ld_tcc ( afc_ld_tcc ) + ,.afc_fb_tcc ( afc_fb_tcc ) + ,.sync_clr ( sync_clr ) + ,.pll_rstn ( pll_rstn ) + ,.div_rstn_sel ( div_rstn_sel ) + ,.test_clk_sel ( test_clk_sel ) + ,.test_clk_oen ( test_clk_oen ) + ,.dig_clk_sel ( dig_clk_sel ) + ,.clkrx_pdn ( clkrx_pdn ) + ,.pll_lock ( pll_lock ) + ,.ch0_dac_addr ( ch0_dac_addr ) + ,.ch0_dac_dw ( ch0_dac_dw ) + ,.ch0_dac_ref ( ch0_dac_ref ) + ,.ch0_dac_Prbs_rst0 ( ch0_dac_Prbs_rst0 ) + ,.ch0_dac_Prbs_set0 ( ch0_dac_Prbs_set0 ) + ,.ch0_dac_Prbs_rst1 ( ch0_dac_Prbs_rst1 ) + ,.ch0_dac_Prbs_set1 ( ch0_dac_Prbs_set1 ) + ,.ch0_dac_Cal_sig ( ch0_dac_Cal_sig ) + ,.ch0_dac_Cal_rstn ( ch0_dac_Cal_rstn ) + ,.ch0_dac_Cal_div_rstn ( ch0_dac_Cal_div_rstn ) + ,.ch0_dac_Cal_end ( ch0_dac_Cal_end ) + `ifdef CHANNEL_IS_FOUR + ,.ch1_dac_addr ( ch1_dac_addr ) + ,.ch1_dac_dw ( ch1_dac_dw ) + ,.ch1_dac_ref ( ch1_dac_ref ) + ,.ch1_dac_Prbs_rst0 ( ch1_dac_Prbs_rst0 ) + ,.ch1_dac_Prbs_set0 ( ch1_dac_Prbs_set0 ) + ,.ch1_dac_Prbs_rst1 ( ch1_dac_Prbs_rst1 ) + ,.ch1_dac_Prbs_set1 ( ch1_dac_Prbs_set1 ) + ,.ch1_dac_Cal_sig ( ch1_dac_Cal_sig ) + ,.ch1_dac_Cal_rstn ( ch1_dac_Cal_rstn ) + ,.ch1_dac_Cal_div_rstn ( ch1_dac_Cal_div_rstn ) + ,.ch1_dac_Cal_end ( ch1_dac_Cal_end ) + ,.ch2_dac_addr ( ch2_dac_addr ) + ,.ch2_dac_dw ( ch2_dac_dw ) + ,.ch2_dac_ref ( ch2_dac_ref ) + ,.ch2_dac_Prbs_rst0 ( ch2_dac_Prbs_rst0 ) + ,.ch2_dac_Prbs_set0 ( ch2_dac_Prbs_set0 ) + ,.ch2_dac_Prbs_rst1 ( ch2_dac_Prbs_rst1 ) + ,.ch2_dac_Prbs_set1 ( ch2_dac_Prbs_set1 ) + ,.ch2_dac_Cal_sig ( ch2_dac_Cal_sig ) + ,.ch2_dac_Cal_rstn ( ch2_dac_Cal_rstn ) + ,.ch2_dac_Cal_div_rstn ( ch2_dac_Cal_div_rstn ) + ,.ch2_dac_Cal_end ( ch2_dac_Cal_end ) + ,.ch3_dac_dw ( ch3_dac_dw ) + ,.ch3_dac_ref ( ch3_dac_ref ) + ,.ch3_dac_Prbs_rst0 ( ch3_dac_Prbs_rst0 ) + ,.ch3_dac_Prbs_set0 ( ch3_dac_Prbs_set0 ) + ,.ch3_dac_Prbs_rst1 ( ch3_dac_Prbs_rst1 ) + ,.ch3_dac_Prbs_set1 ( ch3_dac_Prbs_set1 ) + ,.ch3_dac_Cal_sig ( ch3_dac_Cal_sig ) + ,.ch3_dac_Cal_rstn ( ch3_dac_Cal_rstn ) + ,.ch0_dac_Cal_div_rstn ( ch3_dac_Cal_div_rstn ) + ,.ch3_dac_Cal_end ( ch3_dac_Cal_end ) + `endif + //------------------------------Ch0 DSP data out---------------------------------------------------- + `ifdef CHANNEL_XY_ON + ,.ch0_xy_A_DEM_MSB_OUT0 ( ch0_xy_A_DEM_MSB_OUT0 ) + ,.ch0_xy_A_DEM_MSB_OUT1 ( ch0_xy_A_DEM_MSB_OUT1 ) + ,.ch0_xy_A_DEM_MSB_OUT2 ( ch0_xy_A_DEM_MSB_OUT2 ) + ,.ch0_xy_A_DEM_MSB_OUT3 ( ch0_xy_A_DEM_MSB_OUT3 ) + ,.ch0_xy_A_DEM_MSB_OUT4 ( ch0_xy_A_DEM_MSB_OUT4 ) + ,.ch0_xy_A_DEM_MSB_OUT5 ( ch0_xy_A_DEM_MSB_OUT5 ) + ,.ch0_xy_A_DEM_MSB_OUT6 ( ch0_xy_A_DEM_MSB_OUT6 ) + ,.ch0_xy_A_DEM_MSB_OUT7 ( ch0_xy_A_DEM_MSB_OUT7 ) + ,.ch0_xy_B_DEM_MSB_OUT0 ( ch0_xy_B_DEM_MSB_OUT0 ) + ,.ch0_xy_B_DEM_MSB_OUT1 ( ch0_xy_B_DEM_MSB_OUT1 ) + ,.ch0_xy_B_DEM_MSB_OUT2 ( ch0_xy_B_DEM_MSB_OUT2 ) + ,.ch0_xy_B_DEM_MSB_OUT3 ( ch0_xy_B_DEM_MSB_OUT3 ) + ,.ch0_xy_B_DEM_MSB_OUT4 ( ch0_xy_B_DEM_MSB_OUT4 ) + ,.ch0_xy_B_DEM_MSB_OUT5 ( ch0_xy_B_DEM_MSB_OUT5 ) + ,.ch0_xy_B_DEM_MSB_OUT6 ( ch0_xy_B_DEM_MSB_OUT6 ) + ,.ch0_xy_B_DEM_MSB_OUT7 ( ch0_xy_B_DEM_MSB_OUT7 ) + ,.ch0_xy_A_DEM_ISB_OUT0 ( ch0_xy_A_DEM_ISB_OUT0 ) + ,.ch0_xy_A_DEM_ISB_OUT1 ( ch0_xy_A_DEM_ISB_OUT1 ) + ,.ch0_xy_A_DEM_ISB_OUT2 ( ch0_xy_A_DEM_ISB_OUT2 ) + ,.ch0_xy_A_DEM_ISB_OUT3 ( ch0_xy_A_DEM_ISB_OUT3 ) + ,.ch0_xy_A_DEM_ISB_OUT4 ( ch0_xy_A_DEM_ISB_OUT4 ) + ,.ch0_xy_A_DEM_ISB_OUT5 ( ch0_xy_A_DEM_ISB_OUT5 ) + ,.ch0_xy_A_DEM_ISB_OUT6 ( ch0_xy_A_DEM_ISB_OUT6 ) + ,.ch0_xy_A_DEM_ISB_OUT7 ( ch0_xy_A_DEM_ISB_OUT7 ) + ,.ch0_xy_B_DEM_ISB_OUT0 ( ch0_xy_B_DEM_ISB_OUT0 ) + ,.ch0_xy_B_DEM_ISB_OUT1 ( ch0_xy_B_DEM_ISB_OUT1 ) + ,.ch0_xy_B_DEM_ISB_OUT2 ( ch0_xy_B_DEM_ISB_OUT2 ) + ,.ch0_xy_B_DEM_ISB_OUT3 ( ch0_xy_B_DEM_ISB_OUT3 ) + ,.ch0_xy_B_DEM_ISB_OUT4 ( ch0_xy_B_DEM_ISB_OUT4 ) + ,.ch0_xy_B_DEM_ISB_OUT5 ( ch0_xy_B_DEM_ISB_OUT5 ) + ,.ch0_xy_B_DEM_ISB_OUT6 ( ch0_xy_B_DEM_ISB_OUT6 ) + ,.ch0_xy_B_DEM_ISB_OUT7 ( ch0_xy_B_DEM_ISB_OUT7 ) + ,.ch0_xy_A_DEM_LSB_OUT0 ( ch0_xy_A_DEM_LSB_OUT0 ) + ,.ch0_xy_A_DEM_LSB_OUT1 ( ch0_xy_A_DEM_LSB_OUT1 ) + ,.ch0_xy_A_DEM_LSB_OUT2 ( ch0_xy_A_DEM_LSB_OUT2 ) + ,.ch0_xy_A_DEM_LSB_OUT3 ( ch0_xy_A_DEM_LSB_OUT3 ) + ,.ch0_xy_A_DEM_LSB_OUT4 ( ch0_xy_A_DEM_LSB_OUT4 ) + ,.ch0_xy_A_DEM_LSB_OUT5 ( ch0_xy_A_DEM_LSB_OUT5 ) + ,.ch0_xy_A_DEM_LSB_OUT6 ( ch0_xy_A_DEM_LSB_OUT6 ) + ,.ch0_xy_A_DEM_LSB_OUT7 ( ch0_xy_A_DEM_LSB_OUT7 ) + ,.ch0_xy_B_DEM_LSB_OUT0 ( ch0_xy_B_DEM_LSB_OUT0 ) + ,.ch0_xy_B_DEM_LSB_OUT1 ( ch0_xy_B_DEM_LSB_OUT1 ) + ,.ch0_xy_B_DEM_LSB_OUT2 ( ch0_xy_B_DEM_LSB_OUT2 ) + ,.ch0_xy_B_DEM_LSB_OUT3 ( ch0_xy_B_DEM_LSB_OUT3 ) + ,.ch0_xy_B_DEM_LSB_OUT4 ( ch0_xy_B_DEM_LSB_OUT4 ) + ,.ch0_xy_B_DEM_LSB_OUT5 ( ch0_xy_B_DEM_LSB_OUT5 ) + ,.ch0_xy_B_DEM_LSB_OUT6 ( ch0_xy_B_DEM_LSB_OUT6 ) + ,.ch0_xy_B_DEM_LSB_OUT7 ( ch0_xy_B_DEM_LSB_OUT7 ) + `endif + `ifdef CHANNEL_Z_ON + ,.ch0_z_DEM_MSB_OUT0 ( ch0_z_DEM_MSB_OUT0 ) + ,.ch0_z_DEM_MSB_OUT1 ( ch0_z_DEM_MSB_OUT1 ) + ,.ch0_z_DEM_MSB_OUT2 ( ch0_z_DEM_MSB_OUT2 ) + ,.ch0_z_DEM_MSB_OUT3 ( ch0_z_DEM_MSB_OUT3 ) + ,.ch0_z_DEM_ISB_OUT0 ( ch0_z_DEM_ISB_OUT0 ) + ,.ch0_z_DEM_ISB_OUT1 ( ch0_z_DEM_ISB_OUT1 ) + ,.ch0_z_DEM_ISB_OUT2 ( ch0_z_DEM_ISB_OUT2 ) + ,.ch0_z_DEM_ISB_OUT3 ( ch0_z_DEM_ISB_OUT3 ) + ,.ch0_z_DEM_LSB_OUT0 ( ch0_z_DEM_LSB_OUT0 ) + ,.ch0_z_DEM_LSB_OUT1 ( ch0_z_DEM_LSB_OUT1 ) + ,.ch0_z_DEM_LSB_OUT2 ( ch0_z_DEM_LSB_OUT2 ) + ,.ch0_z_DEM_LSB_OUT3 ( ch0_z_DEM_LSB_OUT3 ) + `endif + `ifdef CHANNEL_IS_FOUR + //------------------------------Ch1 DSP data out---------------------------------------------------- + `ifdef CHANNEL_XY_ON + ,.ch1_xy_A_DEM_MSB_OUT0 ( ch1_xy_A_DEM_MSB_OUT0 ) + ,.ch1_xy_A_DEM_MSB_OUT1 ( ch1_xy_A_DEM_MSB_OUT1 ) + ,.ch1_xy_A_DEM_MSB_OUT2 ( ch1_xy_A_DEM_MSB_OUT2 ) + ,.ch1_xy_A_DEM_MSB_OUT3 ( ch1_xy_A_DEM_MSB_OUT3 ) + ,.ch1_xy_A_DEM_MSB_OUT4 ( ch1_xy_A_DEM_MSB_OUT4 ) + ,.ch1_xy_A_DEM_MSB_OUT5 ( ch1_xy_A_DEM_MSB_OUT5 ) + ,.ch1_xy_A_DEM_MSB_OUT6 ( ch1_xy_A_DEM_MSB_OUT6 ) + ,.ch1_xy_A_DEM_MSB_OUT7 ( ch1_xy_A_DEM_MSB_OUT7 ) + ,.ch1_xy_B_DEM_MSB_OUT0 ( ch1_xy_B_DEM_MSB_OUT0 ) + ,.ch1_xy_B_DEM_MSB_OUT1 ( ch1_xy_B_DEM_MSB_OUT1 ) + ,.ch1_xy_B_DEM_MSB_OUT2 ( ch1_xy_B_DEM_MSB_OUT2 ) + ,.ch1_xy_B_DEM_MSB_OUT3 ( ch1_xy_B_DEM_MSB_OUT3 ) + ,.ch1_xy_B_DEM_MSB_OUT4 ( ch1_xy_B_DEM_MSB_OUT4 ) + ,.ch1_xy_B_DEM_MSB_OUT5 ( ch1_xy_B_DEM_MSB_OUT5 ) + ,.ch1_xy_B_DEM_MSB_OUT6 ( ch1_xy_B_DEM_MSB_OUT6 ) + ,.ch1_xy_B_DEM_MSB_OUT7 ( ch1_xy_B_DEM_MSB_OUT7 ) + ,.ch1_xy_A_DEM_ISB_OUT0 ( ch1_xy_A_DEM_ISB_OUT0 ) + ,.ch1_xy_A_DEM_ISB_OUT1 ( ch1_xy_A_DEM_ISB_OUT1 ) + ,.ch1_xy_A_DEM_ISB_OUT2 ( ch1_xy_A_DEM_ISB_OUT2 ) + ,.ch1_xy_A_DEM_ISB_OUT3 ( ch1_xy_A_DEM_ISB_OUT3 ) + ,.ch1_xy_A_DEM_ISB_OUT4 ( ch1_xy_A_DEM_ISB_OUT4 ) + ,.ch1_xy_A_DEM_ISB_OUT5 ( ch1_xy_A_DEM_ISB_OUT5 ) + ,.ch1_xy_A_DEM_ISB_OUT6 ( ch1_xy_A_DEM_ISB_OUT6 ) + ,.ch1_xy_A_DEM_ISB_OUT7 ( ch1_xy_A_DEM_ISB_OUT7 ) + ,.ch1_xy_B_DEM_ISB_OUT0 ( ch1_xy_B_DEM_ISB_OUT0 ) + ,.ch1_xy_B_DEM_ISB_OUT1 ( ch1_xy_B_DEM_ISB_OUT1 ) + ,.ch1_xy_B_DEM_ISB_OUT2 ( ch1_xy_B_DEM_ISB_OUT2 ) + ,.ch1_xy_B_DEM_ISB_OUT3 ( ch1_xy_B_DEM_ISB_OUT3 ) + ,.ch1_xy_B_DEM_ISB_OUT4 ( ch1_xy_B_DEM_ISB_OUT4 ) + ,.ch1_xy_B_DEM_ISB_OUT5 ( ch1_xy_B_DEM_ISB_OUT5 ) + ,.ch1_xy_B_DEM_ISB_OUT6 ( ch1_xy_B_DEM_ISB_OUT6 ) + ,.ch1_xy_B_DEM_ISB_OUT7 ( ch1_xy_B_DEM_ISB_OUT7 ) + ,.ch1_xy_A_DEM_LSB_OUT0 ( ch1_xy_A_DEM_LSB_OUT0 ) + ,.ch1_xy_A_DEM_LSB_OUT1 ( ch1_xy_A_DEM_LSB_OUT1 ) + ,.ch1_xy_A_DEM_LSB_OUT2 ( ch1_xy_A_DEM_LSB_OUT2 ) + ,.ch1_xy_A_DEM_LSB_OUT3 ( ch1_xy_A_DEM_LSB_OUT3 ) + ,.ch1_xy_A_DEM_LSB_OUT4 ( ch1_xy_A_DEM_LSB_OUT4 ) + ,.ch1_xy_A_DEM_LSB_OUT5 ( ch1_xy_A_DEM_LSB_OUT5 ) + ,.ch1_xy_A_DEM_LSB_OUT6 ( ch1_xy_A_DEM_LSB_OUT6 ) + ,.ch1_xy_A_DEM_LSB_OUT7 ( ch1_xy_A_DEM_LSB_OUT7 ) + ,.ch1_xy_B_DEM_LSB_OUT0 ( ch1_xy_B_DEM_LSB_OUT0 ) + ,.ch1_xy_B_DEM_LSB_OUT1 ( ch1_xy_B_DEM_LSB_OUT1 ) + ,.ch1_xy_B_DEM_LSB_OUT2 ( ch1_xy_B_DEM_LSB_OUT2 ) + ,.ch1_xy_B_DEM_LSB_OUT3 ( ch1_xy_B_DEM_LSB_OUT3 ) + ,.ch1_xy_B_DEM_LSB_OUT4 ( ch1_xy_B_DEM_LSB_OUT4 ) + ,.ch1_xy_B_DEM_LSB_OUT5 ( ch1_xy_B_DEM_LSB_OUT5 ) + ,.ch1_xy_B_DEM_LSB_OUT6 ( ch1_xy_B_DEM_LSB_OUT6 ) + ,.ch1_xy_B_DEM_LSB_OUT7 ( ch1_xy_B_DEM_LSB_OUT7 ) + `endif + `ifdef CHANNEL_Z_ON + ,.ch1_z_DEM_MSB_OUT0 ( ch1_z_DEM_MSB_OUT0 ) + ,.ch1_z_DEM_MSB_OUT1 ( ch1_z_DEM_MSB_OUT1 ) + ,.ch1_z_DEM_MSB_OUT2 ( ch1_z_DEM_MSB_OUT2 ) + ,.ch1_z_DEM_MSB_OUT3 ( ch1_z_DEM_MSB_OUT3 ) + ,.ch1_z_DEM_ISB_OUT0 ( ch1_z_DEM_ISB_OUT0 ) + ,.ch1_z_DEM_ISB_OUT1 ( ch1_z_DEM_ISB_OUT1 ) + ,.ch1_z_DEM_ISB_OUT2 ( ch1_z_DEM_ISB_OUT2 ) + ,.ch1_z_DEM_ISB_OUT3 ( ch1_z_DEM_ISB_OUT3 ) + ,.ch1_z_DEM_LSB_OUT0 ( ch1_z_DEM_LSB_OUT0 ) + ,.ch1_z_DEM_LSB_OUT1 ( ch1_z_DEM_LSB_OUT1 ) + ,.ch1_z_DEM_LSB_OUT2 ( ch1_z_DEM_LSB_OUT2 ) + ,.ch1_z_DEM_LSB_OUT3 ( ch1_z_DEM_LSB_OUT3 ) + `endif + //------------------------------Ch2 DSP data out---------------------------------------------------- + `ifdef CHANNEL_XY_ON + ,.ch2_xy_A_DEM_MSB_OUT0 ( ch2_xy_A_DEM_MSB_OUT0 ) + ,.ch2_xy_A_DEM_MSB_OUT1 ( ch2_xy_A_DEM_MSB_OUT1 ) + ,.ch2_xy_A_DEM_MSB_OUT2 ( ch2_xy_A_DEM_MSB_OUT2 ) + ,.ch2_xy_A_DEM_MSB_OUT3 ( ch2_xy_A_DEM_MSB_OUT3 ) + ,.ch2_xy_A_DEM_MSB_OUT4 ( ch2_xy_A_DEM_MSB_OUT4 ) + ,.ch2_xy_A_DEM_MSB_OUT5 ( ch2_xy_A_DEM_MSB_OUT5 ) + ,.ch2_xy_A_DEM_MSB_OUT6 ( ch2_xy_A_DEM_MSB_OUT6 ) + ,.ch2_xy_A_DEM_MSB_OUT7 ( ch2_xy_A_DEM_MSB_OUT7 ) + ,.ch2_xy_B_DEM_MSB_OUT0 ( ch2_xy_B_DEM_MSB_OUT0 ) + ,.ch2_xy_B_DEM_MSB_OUT1 ( ch2_xy_B_DEM_MSB_OUT1 ) + ,.ch2_xy_B_DEM_MSB_OUT2 ( ch2_xy_B_DEM_MSB_OUT2 ) + ,.ch2_xy_B_DEM_MSB_OUT3 ( ch2_xy_B_DEM_MSB_OUT3 ) + ,.ch2_xy_B_DEM_MSB_OUT4 ( ch2_xy_B_DEM_MSB_OUT4 ) + ,.ch2_xy_B_DEM_MSB_OUT5 ( ch2_xy_B_DEM_MSB_OUT5 ) + ,.ch2_xy_B_DEM_MSB_OUT6 ( ch2_xy_B_DEM_MSB_OUT6 ) + ,.ch2_xy_B_DEM_MSB_OUT7 ( ch2_xy_B_DEM_MSB_OUT7 ) + ,.ch2_xy_A_DEM_ISB_OUT0 ( ch2_xy_A_DEM_ISB_OUT0 ) + ,.ch2_xy_A_DEM_ISB_OUT1 ( ch2_xy_A_DEM_ISB_OUT1 ) + ,.ch2_xy_A_DEM_ISB_OUT2 ( ch2_xy_A_DEM_ISB_OUT2 ) + ,.ch2_xy_A_DEM_ISB_OUT3 ( ch2_xy_A_DEM_ISB_OUT3 ) + ,.ch2_xy_A_DEM_ISB_OUT4 ( ch2_xy_A_DEM_ISB_OUT4 ) + ,.ch2_xy_A_DEM_ISB_OUT5 ( ch2_xy_A_DEM_ISB_OUT5 ) + ,.ch2_xy_A_DEM_ISB_OUT6 ( ch2_xy_A_DEM_ISB_OUT6 ) + ,.ch2_xy_A_DEM_ISB_OUT7 ( ch2_xy_A_DEM_ISB_OUT7 ) + ,.ch2_xy_B_DEM_ISB_OUT0 ( ch2_xy_B_DEM_ISB_OUT0 ) + ,.ch2_xy_B_DEM_ISB_OUT1 ( ch2_xy_B_DEM_ISB_OUT1 ) + ,.ch2_xy_B_DEM_ISB_OUT2 ( ch2_xy_B_DEM_ISB_OUT2 ) + ,.ch2_xy_B_DEM_ISB_OUT3 ( ch2_xy_B_DEM_ISB_OUT3 ) + ,.ch2_xy_B_DEM_ISB_OUT4 ( ch2_xy_B_DEM_ISB_OUT4 ) + ,.ch2_xy_B_DEM_ISB_OUT5 ( ch2_xy_B_DEM_ISB_OUT5 ) + ,.ch2_xy_B_DEM_ISB_OUT6 ( ch2_xy_B_DEM_ISB_OUT6 ) + ,.ch2_xy_B_DEM_ISB_OUT7 ( ch2_xy_B_DEM_ISB_OUT7 ) + ,.ch2_xy_A_DEM_LSB_OUT0 ( ch2_xy_A_DEM_LSB_OUT0 ) + ,.ch2_xy_A_DEM_LSB_OUT1 ( ch2_xy_A_DEM_LSB_OUT1 ) + ,.ch2_xy_A_DEM_LSB_OUT2 ( ch2_xy_A_DEM_LSB_OUT2 ) + ,.ch2_xy_A_DEM_LSB_OUT3 ( ch2_xy_A_DEM_LSB_OUT3 ) + ,.ch2_xy_A_DEM_LSB_OUT4 ( ch2_xy_A_DEM_LSB_OUT4 ) + ,.ch2_xy_A_DEM_LSB_OUT5 ( ch2_xy_A_DEM_LSB_OUT5 ) + ,.ch2_xy_A_DEM_LSB_OUT6 ( ch2_xy_A_DEM_LSB_OUT6 ) + ,.ch2_xy_A_DEM_LSB_OUT7 ( ch2_xy_A_DEM_LSB_OUT7 ) + ,.ch2_xy_B_DEM_LSB_OUT0 ( ch2_xy_B_DEM_LSB_OUT0 ) + ,.ch2_xy_B_DEM_LSB_OUT1 ( ch2_xy_B_DEM_LSB_OUT1 ) + ,.ch2_xy_B_DEM_LSB_OUT2 ( ch2_xy_B_DEM_LSB_OUT2 ) + ,.ch2_xy_B_DEM_LSB_OUT3 ( ch2_xy_B_DEM_LSB_OUT3 ) + ,.ch2_xy_B_DEM_LSB_OUT4 ( ch2_xy_B_DEM_LSB_OUT4 ) + ,.ch2_xy_B_DEM_LSB_OUT5 ( ch2_xy_B_DEM_LSB_OUT5 ) + ,.ch2_xy_B_DEM_LSB_OUT6 ( ch2_xy_B_DEM_LSB_OUT6 ) + ,.ch2_xy_B_DEM_LSB_OUT7 ( ch2_xy_B_DEM_LSB_OUT7 ) + `endif + `ifdef CHANNEL_Z_ON + ,.ch2_z_DEM_MSB_OUT0 ( ch2_z_DEM_MSB_OUT0 ) + ,.ch2_z_DEM_MSB_OUT1 ( ch2_z_DEM_MSB_OUT1 ) + ,.ch2_z_DEM_MSB_OUT2 ( ch2_z_DEM_MSB_OUT2 ) + ,.ch2_z_DEM_MSB_OUT3 ( ch2_z_DEM_MSB_OUT3 ) + ,.ch2_z_DEM_ISB_OUT0 ( ch2_z_DEM_ISB_OUT0 ) + ,.ch2_z_DEM_ISB_OUT1 ( ch2_z_DEM_ISB_OUT1 ) + ,.ch2_z_DEM_ISB_OUT2 ( ch2_z_DEM_ISB_OUT2 ) + ,.ch2_z_DEM_ISB_OUT3 ( ch2_z_DEM_ISB_OUT3 ) + ,.ch2_z_DEM_LSB_OUT0 ( ch2_z_DEM_LSB_OUT0 ) + ,.ch2_z_DEM_LSB_OUT1 ( ch2_z_DEM_LSB_OUT1 ) + ,.ch2_z_DEM_LSB_OUT2 ( ch2_z_DEM_LSB_OUT2 ) + ,.ch2_z_DEM_LSB_OUT3 ( ch2_z_DEM_LSB_OUT3 ) + `endif + //------------------------------Ch3 DSP data out---------------------------------------------------- + `ifdef CHANNEL_XY_ON + ,.ch3_xy_A_DEM_MSB_OUT0 ( ch3_xy_A_DEM_MSB_OUT0 ) + ,.ch3_xy_A_DEM_MSB_OUT1 ( ch3_xy_A_DEM_MSB_OUT1 ) + ,.ch3_xy_A_DEM_MSB_OUT2 ( ch3_xy_A_DEM_MSB_OUT2 ) + ,.ch3_xy_A_DEM_MSB_OUT3 ( ch3_xy_A_DEM_MSB_OUT3 ) + ,.ch3_xy_A_DEM_MSB_OUT4 ( ch3_xy_A_DEM_MSB_OUT4 ) + ,.ch3_xy_A_DEM_MSB_OUT5 ( ch3_xy_A_DEM_MSB_OUT5 ) + ,.ch3_xy_A_DEM_MSB_OUT6 ( ch3_xy_A_DEM_MSB_OUT6 ) + ,.ch3_xy_A_DEM_MSB_OUT7 ( ch3_xy_A_DEM_MSB_OUT7 ) + ,.ch3_xy_B_DEM_MSB_OUT0 ( ch3_xy_B_DEM_MSB_OUT0 ) + ,.ch3_xy_B_DEM_MSB_OUT1 ( ch3_xy_B_DEM_MSB_OUT1 ) + ,.ch3_xy_B_DEM_MSB_OUT2 ( ch3_xy_B_DEM_MSB_OUT2 ) + ,.ch3_xy_B_DEM_MSB_OUT3 ( ch3_xy_B_DEM_MSB_OUT3 ) + ,.ch3_xy_B_DEM_MSB_OUT4 ( ch3_xy_B_DEM_MSB_OUT4 ) + ,.ch3_xy_B_DEM_MSB_OUT5 ( ch3_xy_B_DEM_MSB_OUT5 ) + ,.ch3_xy_B_DEM_MSB_OUT6 ( ch3_xy_B_DEM_MSB_OUT6 ) + ,.ch3_xy_B_DEM_MSB_OUT7 ( ch3_xy_B_DEM_MSB_OUT7 ) + ,.ch3_xy_A_DEM_ISB_OUT0 ( ch3_xy_A_DEM_ISB_OUT0 ) + ,.ch3_xy_A_DEM_ISB_OUT1 ( ch3_xy_A_DEM_ISB_OUT1 ) + ,.ch3_xy_A_DEM_ISB_OUT2 ( ch3_xy_A_DEM_ISB_OUT2 ) + ,.ch3_xy_A_DEM_ISB_OUT3 ( ch3_xy_A_DEM_ISB_OUT3 ) + ,.ch3_xy_A_DEM_ISB_OUT4 ( ch3_xy_A_DEM_ISB_OUT4 ) + ,.ch3_xy_A_DEM_ISB_OUT5 ( ch3_xy_A_DEM_ISB_OUT5 ) + ,.ch3_xy_A_DEM_ISB_OUT6 ( ch3_xy_A_DEM_ISB_OUT6 ) + ,.ch3_xy_A_DEM_ISB_OUT7 ( ch3_xy_A_DEM_ISB_OUT7 ) + ,.ch3_xy_B_DEM_ISB_OUT0 ( ch3_xy_B_DEM_ISB_OUT0 ) + ,.ch3_xy_B_DEM_ISB_OUT1 ( ch3_xy_B_DEM_ISB_OUT1 ) + ,.ch3_xy_B_DEM_ISB_OUT2 ( ch3_xy_B_DEM_ISB_OUT2 ) + ,.ch3_xy_B_DEM_ISB_OUT3 ( ch3_xy_B_DEM_ISB_OUT3 ) + ,.ch3_xy_B_DEM_ISB_OUT4 ( ch3_xy_B_DEM_ISB_OUT4 ) + ,.ch3_xy_B_DEM_ISB_OUT5 ( ch3_xy_B_DEM_ISB_OUT5 ) + ,.ch3_xy_B_DEM_ISB_OUT6 ( ch3_xy_B_DEM_ISB_OUT6 ) + ,.ch3_xy_B_DEM_ISB_OUT7 ( ch3_xy_B_DEM_ISB_OUT7 ) + ,.ch3_xy_A_DEM_LSB_OUT0 ( ch3_xy_A_DEM_LSB_OUT0 ) + ,.ch3_xy_A_DEM_LSB_OUT1 ( ch3_xy_A_DEM_LSB_OUT1 ) + ,.ch3_xy_A_DEM_LSB_OUT2 ( ch3_xy_A_DEM_LSB_OUT2 ) + ,.ch3_xy_A_DEM_LSB_OUT3 ( ch3_xy_A_DEM_LSB_OUT3 ) + ,.ch3_xy_A_DEM_LSB_OUT4 ( ch3_xy_A_DEM_LSB_OUT4 ) + ,.ch3_xy_A_DEM_LSB_OUT5 ( ch3_xy_A_DEM_LSB_OUT5 ) + ,.ch3_xy_A_DEM_LSB_OUT6 ( ch3_xy_A_DEM_LSB_OUT6 ) + ,.ch3_xy_A_DEM_LSB_OUT7 ( ch3_xy_A_DEM_LSB_OUT7 ) + ,.ch3_xy_B_DEM_LSB_OUT0 ( ch3_xy_B_DEM_LSB_OUT0 ) + ,.ch3_xy_B_DEM_LSB_OUT1 ( ch3_xy_B_DEM_LSB_OUT1 ) + ,.ch3_xy_B_DEM_LSB_OUT2 ( ch3_xy_B_DEM_LSB_OUT2 ) + ,.ch3_xy_B_DEM_LSB_OUT3 ( ch3_xy_B_DEM_LSB_OUT3 ) + ,.ch3_xy_B_DEM_LSB_OUT4 ( ch3_xy_B_DEM_LSB_OUT4 ) + ,.ch3_xy_B_DEM_LSB_OUT5 ( ch3_xy_B_DEM_LSB_OUT5 ) + ,.ch3_xy_B_DEM_LSB_OUT6 ( ch3_xy_B_DEM_LSB_OUT6 ) + ,.ch3_xy_B_DEM_LSB_OUT7 ( ch3_xy_B_DEM_LSB_OUT7 ) + `endif + `ifdef CHANNEL_Z_ON + ,.ch3_z_DEM_MSB_OUT0 ( ch3_z_DEM_MSB_OUT0 ) + ,.ch3_z_DEM_MSB_OUT1 ( ch3_z_DEM_MSB_OUT1 ) + ,.ch3_z_DEM_MSB_OUT2 ( ch3_z_DEM_MSB_OUT2 ) + ,.ch3_z_DEM_MSB_OUT3 ( ch3_z_DEM_MSB_OUT3 ) + ,.ch3_z_DEM_ISB_OUT0 ( ch3_z_DEM_ISB_OUT0 ) + ,.ch3_z_DEM_ISB_OUT1 ( ch3_z_DEM_ISB_OUT1 ) + ,.ch3_z_DEM_ISB_OUT2 ( ch3_z_DEM_ISB_OUT2 ) + ,.ch3_z_DEM_ISB_OUT3 ( ch3_z_DEM_ISB_OUT3 ) + ,.ch3_z_DEM_LSB_OUT0 ( ch3_z_DEM_LSB_OUT0 ) + ,.ch3_z_DEM_LSB_OUT1 ( ch3_z_DEM_LSB_OUT1 ) + ,.ch3_z_DEM_LSB_OUT2 ( ch3_z_DEM_LSB_OUT2 ) + ,.ch3_z_DEM_LSB_OUT3 ( ch3_z_DEM_LSB_OUT3 ) + `endif + `endif +); + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +thermo2binary_top U0_thermo2binary_top ( + .DEM_MSB_IN ( ch0_xy_A_DEM_MSB_OUT0 ) + ,.DEM_ISB_IN ( ch0_xy_A_DEM_ISB_OUT0 ) + ,.DEM_LSB_IN ( ch0_xy_A_DEM_LSB_OUT0 ) + ,.DOUT ( ch0_xy_dsp_dout0 ) +); + +thermo2binary_top U1_thermo2binary_top ( + .DEM_MSB_IN ( ch0_xy_A_DEM_MSB_OUT1 ) + ,.DEM_ISB_IN ( ch0_xy_A_DEM_ISB_OUT1 ) + ,.DEM_LSB_IN ( ch0_xy_A_DEM_LSB_OUT1 ) + ,.DOUT ( ch0_xy_dsp_dout1 ) +); + +thermo2binary_top U2_thermo2binary_top ( + .DEM_MSB_IN ( ch0_xy_A_DEM_MSB_OUT2 ) + ,.DEM_ISB_IN ( ch0_xy_A_DEM_ISB_OUT2 ) + ,.DEM_LSB_IN ( ch0_xy_A_DEM_LSB_OUT2 ) + ,.DOUT ( ch0_xy_dsp_dout2 ) +); + +thermo2binary_top U3_thermo2binary_top ( + .DEM_MSB_IN ( ch0_xy_A_DEM_MSB_OUT3 ) + ,.DEM_ISB_IN ( ch0_xy_A_DEM_ISB_OUT3 ) + ,.DEM_LSB_IN ( ch0_xy_A_DEM_LSB_OUT3 ) + ,.DOUT ( ch0_xy_dsp_dout3 ) +); + +thermo2binary_top U4_thermo2binary_top ( + .DEM_MSB_IN ( ch0_xy_A_DEM_MSB_OUT4 ) + ,.DEM_ISB_IN ( ch0_xy_A_DEM_ISB_OUT4 ) + ,.DEM_LSB_IN ( ch0_xy_A_DEM_LSB_OUT4 ) + ,.DOUT ( ch0_xy_dsp_dout4 ) +); + +thermo2binary_top U5_thermo2binary_top ( + .DEM_MSB_IN ( ch0_xy_A_DEM_MSB_OUT5 ) + ,.DEM_ISB_IN ( ch0_xy_A_DEM_ISB_OUT5 ) + ,.DEM_LSB_IN ( ch0_xy_A_DEM_LSB_OUT5 ) + ,.DOUT ( ch0_xy_dsp_dout5 ) +); + +thermo2binary_top U6_thermo2binary_top ( + .DEM_MSB_IN ( ch0_xy_A_DEM_MSB_OUT6 ) + ,.DEM_ISB_IN ( ch0_xy_A_DEM_ISB_OUT6 ) + ,.DEM_LSB_IN ( ch0_xy_A_DEM_LSB_OUT6 ) + ,.DOUT ( ch0_xy_dsp_dout6 ) +); + +thermo2binary_top U7_thermo2binary_top ( + .DEM_MSB_IN ( ch0_xy_A_DEM_MSB_OUT7 ) + ,.DEM_ISB_IN ( ch0_xy_A_DEM_ISB_OUT7 ) + ,.DEM_LSB_IN ( ch0_xy_A_DEM_LSB_OUT7 ) + ,.DOUT ( ch0_xy_dsp_dout7 ) +); + +thermo2binary_top U8_thermo2binary_top ( + .DEM_MSB_IN ( ch0_xy_B_DEM_MSB_OUT0 ) + ,.DEM_ISB_IN ( ch0_xy_B_DEM_ISB_OUT0 ) + ,.DEM_LSB_IN ( ch0_xy_B_DEM_LSB_OUT0 ) + ,.DOUT ( ch0_xy_dsp_dout8 ) +); + +thermo2binary_top U9_thermo2binary_top ( + .DEM_MSB_IN ( ch0_xy_B_DEM_MSB_OUT1 ) + ,.DEM_ISB_IN ( ch0_xy_B_DEM_ISB_OUT1 ) + ,.DEM_LSB_IN ( ch0_xy_B_DEM_LSB_OUT1 ) + ,.DOUT ( ch0_xy_dsp_dout9 ) +); + +thermo2binary_top U10_thermo2binary_top ( + .DEM_MSB_IN ( ch0_xy_B_DEM_MSB_OUT2 ) + ,.DEM_ISB_IN ( ch0_xy_B_DEM_ISB_OUT2 ) + ,.DEM_LSB_IN ( ch0_xy_B_DEM_LSB_OUT2 ) + ,.DOUT ( ch0_xy_dsp_dout10 ) +); + +thermo2binary_top U11_thermo2binary_top ( + .DEM_MSB_IN ( ch0_xy_B_DEM_MSB_OUT3 ) + ,.DEM_ISB_IN ( ch0_xy_B_DEM_ISB_OUT3 ) + ,.DEM_LSB_IN ( ch0_xy_B_DEM_LSB_OUT3 ) + ,.DOUT ( ch0_xy_dsp_dout11 ) +); + +thermo2binary_top U12_thermo2binary_top ( + .DEM_MSB_IN ( ch0_xy_B_DEM_MSB_OUT4 ) + ,.DEM_ISB_IN ( ch0_xy_B_DEM_ISB_OUT4 ) + ,.DEM_LSB_IN ( ch0_xy_B_DEM_LSB_OUT4 ) + ,.DOUT ( ch0_xy_dsp_dout12 ) +); + +thermo2binary_top U13_thermo2binary_top ( + .DEM_MSB_IN ( ch0_xy_B_DEM_MSB_OUT5 ) + ,.DEM_ISB_IN ( ch0_xy_B_DEM_ISB_OUT5 ) + ,.DEM_LSB_IN ( ch0_xy_B_DEM_LSB_OUT5 ) + ,.DOUT ( ch0_xy_dsp_dout13 ) +); + + +thermo2binary_top U14_thermo2binary_top ( + .DEM_MSB_IN ( ch0_xy_B_DEM_MSB_OUT6 ) + ,.DEM_ISB_IN ( ch0_xy_B_DEM_ISB_OUT6 ) + ,.DEM_LSB_IN ( ch0_xy_B_DEM_LSB_OUT6 ) + ,.DOUT ( ch0_xy_dsp_dout14 ) +); + +thermo2binary_top U15_thermo2binary_top ( + .DEM_MSB_IN ( ch0_xy_B_DEM_MSB_OUT7 ) + ,.DEM_ISB_IN ( ch0_xy_B_DEM_ISB_OUT7 ) + ,.DEM_LSB_IN ( ch0_xy_B_DEM_LSB_OUT7 ) + ,.DOUT ( ch0_xy_dsp_dout15 ) +); + + +//////////////////////////////////////////////////////////////////////////////////////////////////// + + +logic [31:0] cnt_c; + +wire add_cnt = 'b1; + +wire end_cnt = 1'b0; + +wire [31:0] cnt_n = end_cnt ? 32'h0 : + add_cnt ? cnt_c + 1'b1 : + cnt_c ; + + +sirv_gnrl_dffr #(32) cnt_c_dffr (cnt_n, cnt_c, clk_div16_0, async_rstn); + +initial begin + wait(cnt_c == 32'd100000); + $finish(0); +end + + +/////////////////////////////////////////////////////////////////////// +//XY DEM output data save +/////////////////////////////////////////////////////////////////////// + +logic [15:0] cs_wave; +wire [15:0] i_cs_0 = ch0_xy_dsp_dout0 ; +wire [15:0] i_cs_1 = ch0_xy_dsp_dout1 ; +wire [15:0] i_cs_2 = ch0_xy_dsp_dout2 ; +wire [15:0] i_cs_3 = ch0_xy_dsp_dout3 ; +wire [15:0] i_cs_4 = ch0_xy_dsp_dout4 ; +wire [15:0] i_cs_5 = ch0_xy_dsp_dout5 ; +wire [15:0] i_cs_6 = ch0_xy_dsp_dout6 ; +wire [15:0] i_cs_7 = ch0_xy_dsp_dout7 ; +wire [15:0] i_cs_8 = ch0_xy_dsp_dout8 ; +wire [15:0] i_cs_9 = ch0_xy_dsp_dout9 ; +wire [15:0] i_cs_a = ch0_xy_dsp_dout10; +wire [15:0] i_cs_b = ch0_xy_dsp_dout11; +wire [15:0] i_cs_c = ch0_xy_dsp_dout12; +wire [15:0] i_cs_d = ch0_xy_dsp_dout13; +wire [15:0] i_cs_e = ch0_xy_dsp_dout14; +wire [15:0] i_cs_f = ch0_xy_dsp_dout15; + +wire [2:0] intp_mode = U_xyz_chip_top.U_digital_top.U0_channel_top.intp_mode; + +always@(*) + fork + case (intp_mode) + 3'b000 : begin + @(posedge clk_div16_f) + cs_wave = i_cs_0; + end + 3'b001 : begin + @(posedge clk_div16_f) + cs_wave = i_cs_0; + @(posedge clk_div16_7) + cs_wave = i_cs_1; + end + 3'b010 : begin + @(posedge clk_div16_f) + cs_wave = i_cs_0; + @(posedge clk_div16_b) + cs_wave = i_cs_1; + @(posedge clk_div16_7) + cs_wave = i_cs_2; + @(posedge clk_div16_3) + cs_wave = i_cs_3; + end + 3'b011 : begin + @(posedge clk_div16_f) + cs_wave = i_cs_0; + @(posedge clk_div16_d) + cs_wave = i_cs_1; + @(posedge clk_div16_b) + cs_wave = i_cs_2; + @(posedge clk_div16_9) + cs_wave = i_cs_3; + @(posedge clk_div16_7) + cs_wave = i_cs_4; + @(posedge clk_div16_5) + cs_wave = i_cs_5; + @(posedge clk_div16_3) + cs_wave = i_cs_6; + @(posedge clk_div16_1) + cs_wave = i_cs_7; + end + 3'b100 : begin + @(posedge clk_div16_f) + cs_wave = i_cs_0; + @(posedge clk_div16_e) + cs_wave = i_cs_1; + @(posedge clk_div16_d) + cs_wave = i_cs_2; + @(posedge clk_div16_c) + cs_wave = i_cs_3; + @(posedge clk_div16_b) + cs_wave = i_cs_4; + @(posedge clk_div16_a) + cs_wave = i_cs_5; + @(posedge clk_div16_9) + cs_wave = i_cs_6; + @(posedge clk_div16_8) + cs_wave = i_cs_7; + @(posedge clk_div16_7) + cs_wave = i_cs_8; + @(posedge clk_div16_6) + cs_wave = i_cs_9; + @(posedge clk_div16_5) + cs_wave = i_cs_a; + @(posedge clk_div16_4) + cs_wave = i_cs_b; + @(posedge clk_div16_3) + cs_wave = i_cs_c; + @(posedge clk_div16_2) + cs_wave = i_cs_d; + @(posedge clk_div16_1) + cs_wave = i_cs_e; + @(posedge clk_div16_0) + cs_wave = i_cs_f; + end + endcase +join + +integer XY_fid; +initial begin + #0; + XY_fid = $fopen("./xy_data.dat"); +end +always@(posedge clk) + if(U_xyz_chip_top.U_digital_top.ch0_xy_dsp_dout_vld) + $fwrite(XY_fid,"%d\n",cs_wave); + + + +/////////////////////////////////////////////////////////////////////// +//XY DSP output data save +/////////////////////////////////////////////////////////////////////// + +logic [15:0] dsp_cs_wave; +wire [15:0] dsp_cs_0 = U_xyz_chip_top.ch0_xy_dsp_dout0 ; +wire [15:0] dsp_cs_1 = U_xyz_chip_top.ch0_xy_dsp_dout1 ; +wire [15:0] dsp_cs_2 = U_xyz_chip_top.ch0_xy_dsp_dout2 ; +wire [15:0] dsp_cs_3 = U_xyz_chip_top.ch0_xy_dsp_dout3 ; +wire [15:0] dsp_cs_4 = U_xyz_chip_top.ch0_xy_dsp_dout4 ; +wire [15:0] dsp_cs_5 = U_xyz_chip_top.ch0_xy_dsp_dout5 ; +wire [15:0] dsp_cs_6 = U_xyz_chip_top.ch0_xy_dsp_dout6 ; +wire [15:0] dsp_cs_7 = U_xyz_chip_top.ch0_xy_dsp_dout7 ; +wire [15:0] dsp_cs_8 = U_xyz_chip_top.ch0_xy_dsp_dout8 ; +wire [15:0] dsp_cs_9 = U_xyz_chip_top.ch0_xy_dsp_dout9 ; +wire [15:0] dsp_cs_a = U_xyz_chip_top.ch0_xy_dsp_dout10; +wire [15:0] dsp_cs_b = U_xyz_chip_top.ch0_xy_dsp_dout11; +wire [15:0] dsp_cs_c = U_xyz_chip_top.ch0_xy_dsp_dout12; +wire [15:0] dsp_cs_d = U_xyz_chip_top.ch0_xy_dsp_dout13; +wire [15:0] dsp_cs_e = U_xyz_chip_top.ch0_xy_dsp_dout14; +wire [15:0] dsp_cs_f = U_xyz_chip_top.ch0_xy_dsp_dout15; + +//wire [2:0] intp_mode = U_xyz_chip_top.U_digital_top.U0_channel_top.intp_mode; + +always@(*) + fork + case (intp_mode) + 3'b000 : begin + @(posedge clk_div16_f) + dsp_cs_wave = dsp_cs_0; + end + 3'b001 : begin + @(posedge clk_div16_f) + dsp_cs_wave = dsp_cs_0; + @(posedge clk_div16_7) + dsp_cs_wave = dsp_cs_1; + end + 3'b010 : begin + @(posedge clk_div16_f) + dsp_cs_wave = dsp_cs_0; + @(posedge clk_div16_b) + dsp_cs_wave = dsp_cs_1; + @(posedge clk_div16_7) + dsp_cs_wave = dsp_cs_2; + @(posedge clk_div16_3) + dsp_cs_wave = dsp_cs_3; + end + 3'b011 : begin + @(posedge clk_div16_f) + dsp_cs_wave = dsp_cs_0; + @(posedge clk_div16_d) + dsp_cs_wave = dsp_cs_1; + @(posedge clk_div16_b) + dsp_cs_wave = dsp_cs_2; + @(posedge clk_div16_9) + dsp_cs_wave = dsp_cs_3; + @(posedge clk_div16_7) + dsp_cs_wave = dsp_cs_4; + @(posedge clk_div16_5) + dsp_cs_wave = dsp_cs_5; + @(posedge clk_div16_3) + dsp_cs_wave = dsp_cs_6; + @(posedge clk_div16_1) + dsp_cs_wave = dsp_cs_7; + end + 3'b100 : begin + @(posedge clk_div16_f) + dsp_cs_wave = dsp_cs_0; + @(posedge clk_div16_e) + dsp_cs_wave = dsp_cs_1; + @(posedge clk_div16_d) + dsp_cs_wave = dsp_cs_2; + @(posedge clk_div16_c) + dsp_cs_wave = dsp_cs_3; + @(posedge clk_div16_b) + dsp_cs_wave = dsp_cs_4; + @(posedge clk_div16_a) + dsp_cs_wave = dsp_cs_5; + @(posedge clk_div16_9) + dsp_cs_wave = dsp_cs_6; + @(posedge clk_div16_8) + dsp_cs_wave = dsp_cs_7; + @(posedge clk_div16_7) + dsp_cs_wave = dsp_cs_8; + @(posedge clk_div16_6) + dsp_cs_wave = dsp_cs_9; + @(posedge clk_div16_5) + dsp_cs_wave = dsp_cs_a; + @(posedge clk_div16_4) + dsp_cs_wave = dsp_cs_b; + @(posedge clk_div16_3) + dsp_cs_wave = dsp_cs_c; + @(posedge clk_div16_2) + dsp_cs_wave = dsp_cs_d; + @(posedge clk_div16_1) + dsp_cs_wave = dsp_cs_e; + @(posedge clk_div16_0) + dsp_cs_wave = dsp_cs_f; + end + endcase +join + +integer XY_dsp_fid; + +always@(posedge clk) + if(U_xyz_chip_top.U_digital_top.ch0_xy_dsp_dout_vld) + $fwrite(XY_dsp_fid,"%d\n",dsp_cs_wave); + +/////////////////////////////////////////////////////////////////////// +//Z DSP output data save +/////////////////////////////////////////////////////////////////////// + +logic [15:0] z_wave; +wire [15:0] z_cs_0 = ch0_z_dsp_dout0 ; +wire [15:0] z_cs_1 = ch0_z_dsp_dout1 ; +wire [15:0] z_cs_2 = ch0_z_dsp_dout2 ; +wire [15:0] z_cs_3 = ch0_z_dsp_dout3 ; + + +//wire [2:0] intp_mode = U_xyz_chip_top.U_digital_top.U0_channel_top.intp_mode; + +always@(*) + fork + case (intp_mode) + 3'b000 : begin + @(posedge clk_div16_f) + z_wave = z_cs_0; + end + 3'b001 : begin + @(posedge clk_div16_f) + z_wave = z_cs_0; + @(posedge clk_div16_7) + z_wave = z_cs_1; + end + 3'b010 : begin + @(posedge clk_div16_f) + z_wave = z_cs_0; + @(posedge clk_div16_b) + z_wave = z_cs_1; + @(posedge clk_div16_7) + z_wave = z_cs_2; + @(posedge clk_div16_3) + z_wave = z_cs_3; + end + endcase +join + +integer Z_fid; + +always@(posedge clk) + if(cnt_c > 22'd4096) + $fwrite(Z_fid,"%d\n",z_wave); + +wire [15 :0] ch0_mod_data_i = U_xyz_chip_top.U_digital_top.U_debug_top.U_debug_sampling.ch0_mod_data_i ; +wire [15 :0] ch0_mod_data_q = U_xyz_chip_top.U_digital_top.U_debug_top.U_debug_sampling.ch0_mod_data_q ; +wire ch0_mod_vld = U_xyz_chip_top.U_digital_top.U_debug_top.U_debug_sampling.ch0_mod_vld ; + +integer dbg_mod_fid; + +initial begin + #0; + dbg_mod_fid = $fopen("./dbg_mod_data.dat"); +end + +always@(posedge clk_div16_0) + if(ch0_mod_vld) + $fwrite(dbg_mod_fid,"%h\n",{ch0_mod_data_i,ch0_mod_data_q}); + +wire [511:0] mod_data_c = U_xyz_chip_top.U_digital_top.U_debug_top.U_debug_sampling.mod_data_c ; +wire mod_cen = U_xyz_chip_top.U_digital_top.U_debug_top.U_debug_sampling.mod_cen ; + +integer dbg_mod_data_c_fid; + +initial begin + #0; + dbg_mod_data_c_fid = $fopen("./dbg_mod_data_c.dat"); +end + +always@(posedge clk_div16_0) + if(~mod_cen) + $fwrite(dbg_mod_data_c_fid,"%h\n",mod_data_c); + + +endmodule + +`include "chip_undefine.v" + diff --git a/tb/chip_top/XY_DAC_TB.sv b/tb/chip_top/XY_DAC_TB.sv new file mode 100644 index 0000000..53d3adc --- /dev/null +++ b/tb/chip_top/XY_DAC_TB.sv @@ -0,0 +1,1911 @@ +`include "/home/ic6103/DIGITAL/SWB/EZQ-XYZ-M1-V1.0_20240527/EZQ-XYZ-M1-V1.0/EZQ-XYZ-M1/rtl/define/chip_define.v" + + + +//-----------AWG out NCO data------------------ +//1'b0:normal data; 1'b1: NCO data +`define AWG_OUT 1'b1 +//-------Configure chip role------------------- +//2'b00:XY's Chiop at AC Mode +//2'b11:Z's Chiop at DC Mode +`define ROLE 2'b00 + +//-------Interpolation------------------------- +//Set the interpolation factor +//3'b000:x1;3'b001:x2;3'b010:x4; +//3'b011:x8;3'b100:x16; +`define INTP_MODE 3'b100 + +//-----------QAM mode-------------------------- +//Set the mixer output to the mixed signal +//2'b00:bypass;2'b01:mix; +//2'b10:cos;2'b11:sin; +`define QAM_MODE 2'b00 + +//-----------sideband select------------------- +//Set the mixer to upper sideband modulation +//1'b0:Upper sideband;1'b1:Lower sideband; +`define MIX_SIDEBAND 1'b0 + +//-----------DAC data format-------------------- +//Set the DAC data format to normal mode +//2'b00:NRZ mode;2'b01:MIX mode; +//2'b10:2xNRZ mode;2'b11:reserve; +`define DAC_FORMAT 2'b11 + + +//define Instr and Envelope ID and envelope data +//`define MCU_INSTR_FILE "../../cfgdata/instrmem/SingleWaveCosine_bin.txt" +`define MCU_INSTR_FILE "/home/ic6103/DIGITAL/SWB/EZQ-XYZ-M1-V1.0_20240527/EZQ-XYZ-M1-V1.0/EZQ-XYZ-M1/cfgdata/instrmem/SingleWaveCombine_bin.txt" +//`define MCU_INSTR_FILE "../../cfgdata/instrmem/SingleWaveFlattop_bin.txt" +//`define MCU_INSTR_FILE "../../cfgdata/instrmem/awg_inst.txt" +//`define MCU_INSTR_FILE "../../cfgdata/instrmem/SingleWaveRectangle_bin.txt" +`define MCU_DATA_FILE "/home/ic6103/DIGITAL/SWB/EZQ-XYZ-M1-V1.0_20240527/EZQ-XYZ-M1-V1.0/EZQ-XYZ-M1/cfgdata/datamem/awg_data.txt" +`define ENVE_ID_FILE "/home/ic6103/DIGITAL/SWB/EZQ-XYZ-M1-V1.0_20240527/EZQ-XYZ-M1-V1.0/EZQ-XYZ-M1/cfgdata/enveindex/wave_index_12.txt" +`define ENVE_DATA_FILE "/home/ic6103/DIGITAL/SWB/EZQ-XYZ-M1-V1.0_20240527/EZQ-XYZ-M1-V1.0/EZQ-XYZ-M1/cfgdata/envemem/wave_bin_12.txt" +`define READ_FILE "/home/ic6103/DIGITAL/SWB/EZQ-XYZ-M1-V1.0_20240527/EZQ-XYZ-M1-V1.0/EZQ-XYZ-M1/cfgdata/envemem/rwave_bin_12.txt" + +`define CHIIPID 5'b0_0000 +`define SYSREG_BASEADDR 25'h000_0000 +`define CH0_ITCM_BASEADDR 25'h010_0000 +`define CH0_DTCM_BASEADDR 25'h020_0000 +`define CH0_CTRLREG_BASEADDR 25'h030_0000 +`define CH0_ENVEID_BASEADDR 25'h040_0000 +`define CH0_ENVEMEM_BASEADDR 25'h050_0000 +`define CH0_DACREG_BASEADDR 25'h060_0000 +`define PLL_BASEADDR 25'h1F0_0000 + +`define SCLK_PERIOD 10ns +`define CSN2SCLK_TIME 3ns + +class BinaryDataReader; + + + bit spi_data_queue[$]; + + + function void read_txt_file(input string filename); + int file_id; + string line; + bit [31:0] binary_value; + int i; + + + file_id = $fopen(filename, "r"); + if (file_id == 0) begin + $display("Error: Failed to open file %s", filename); + return; + end + + + while (!$feof(file_id)) begin + //if ($fgets(line, file_id)) begin + $fscanf(file_id,"%b\n",binary_value); + for (i = 31; i >= 0; i--) begin + spi_data_queue.push_back(binary_value[i]); + end + //end + end + + // 关闭文件 + $fclose(file_id); + endfunction + + function void get_data_queue(ref bit data_queue[$]); + data_queue = spi_data_queue; + spi_data_queue.delete(); + endfunction + +endclass + +class spi_data_send; + virtual spi_if spi_intf; + task send_item(bit data_queue[], virtual spi_if spi_intf); + + //ToDo + //wait(spi_intf.rstn); + #(`SCLK_PERIOD/3); + spi_intf.csn <= 1'b1; + spi_intf.sclk <= 1'b1; + #(`SCLK_PERIOD/3); + spi_intf.csn <= 1'b0; + #(`SCLK_PERIOD/3); + foreach(data_queue[i]) begin + spi_intf.mosi <= data_queue[i]; + spi_intf.sclk <= ~spi_intf.sclk; + #(`SCLK_PERIOD/2); + spi_intf.sclk <= ~spi_intf.sclk; + #(`SCLK_PERIOD/2); + end + spi_intf.sclk <= 1'b1; + #(`SCLK_PERIOD/3); + spi_intf.csn <= 1'b1; + #(`SCLK_PERIOD/3); + endtask : send_item + +endclass + + +class spi_reg; + virtual spi_if spi_intf; + bit spi_reg_queue[$]; + bit [63:0] write_item; + int i; + task write_reg(bit cmd, bit[24:0] addr, bit[4:0] chipid, bit[31:0] data, virtual spi_if spi_intf); + write_item = {cmd,addr,chipid,1'b0,data}; + $display("write_item %b", write_item); + for (i = 63; i >= 0; i--) begin + spi_reg_queue.push_back(write_item[i]); + $display("write_item %0d: %b", i, write_item[i]); + end + foreach (spi_reg_queue[i]) begin + $display("reg %0d: %b", i, spi_reg_queue[i]); + end + //ToDo + //wait(spi_intf.rstn); + #(`SCLK_PERIOD/3); + spi_intf.csn <= 1'b1; + spi_intf.sclk <= 1'b1; + #(`SCLK_PERIOD/3); + spi_intf.csn <= 1'b0; + #(`SCLK_PERIOD/3); + foreach(spi_reg_queue[i]) begin + spi_intf.mosi <= spi_reg_queue[i]; + spi_intf.sclk <= ~spi_intf.sclk; + #(`SCLK_PERIOD/2); + spi_intf.sclk <= ~spi_intf.sclk; + #(`SCLK_PERIOD/2); + end + spi_intf.sclk <= ~spi_intf.sclk; + #(`SCLK_PERIOD/2); + spi_intf.sclk <= 1'b1; + #(`SCLK_PERIOD/3); + spi_intf.csn <= 1'b1; + #100ns; + spi_reg_queue.delete(); + endtask : write_reg + +endclass + + +module XY_DAC_TB( + //-------------------------clcok pin from pll------------------------------------------------- + input clk // System Main Clock + //-------------------------Power on reset pin from por---------------------------------------- + //,input por_rstn // Power on reset, active low + //------------------------------digital IO---------------------------------------------------- + + ,input rstn // hardware Reset, active low + //sync + //,input sync_in // Chip synchronization signal input, high pulse valid + ,output sync_out // Chip synchronization signal output, high pulse valid + //Feedback signal + //,input [1 :0] ch0_feedback // Ch0 Feedback signals from the readout chip + `ifdef CHANNEL_IS_FOUR + ,input [1 :0] ch1_feedback // Ch1 Feedback signals from the readout chip + ,input [1 :0] ch2_feedback // Ch2 Feedback signals from the readout chip + ,input [1 :0] ch3_feedback // Ch3 Feedback signals from the readout chip + `endif + //config chip id + //,input [4 :0] cfgid // During power-on initialization, the IO configuration + // values are read as the chip ID number + //spi port + //,input sclk // Spi Clock + //,input csn // Spi Chip Select active low + //,input mosi // Spi Mosi + ,output miso // Spi Miso + ,output oen // Spi Miso output enable + //irq + ,output irq // Interrupt signal in the chip, high level active + //------------------------------PLL cfg pin---------------------------------------------------- + ,output ref_sel // Clock source selection for a frequency divider; + // 1'b0:External clock source + // 1'b1:internal phase-locked loop clock source + ,output ref_en // Input reference clock enable + // 1'b0:enable,1'b1:disable + ,output ref_s2d_en // Referenced clock differential to single-ended conversion enable + // 1'b0:enable,1'b1:disable + ,output [6 :0] p_cnt // P counter + ,output pfd_delay // PFD Dead Zone + ,output pfd_dff_Set // Setting the PFD register,active high + ,output pfd_dff_4and // PFD output polarity + ,output [3 :0] spd_div // SPD Frequency Divider + ,output spd_pulse_width // Pulse Width of SPD + ,output spd_pulse_sw // Pulse sw of SPD + ,output cpc_sel // current source selection + ,output [1 :0] swcp_i // PTAT current switch + ,output [3 :0] sw_ptat_r // PTAT current adjustment + ,output [1 :0] sw_fll_cpi // Phase-locked loop charge pump current + ,output sw_fll_delay // PLL Dead Zone + ,output pfd_sel // PFD Loop selection + ,output spd_sel // SPD Loop selection + ,output fll_sel // FLL Loop selection + ,output vco_tc // VCO temperature compensation + ,output vco_tcr // VCO temperature compensation resistor + ,output vco_gain_adj // VCO gain adjustment + ,output vco_gain_adj_r // VCO gain adjustment resistor + ,output [2 :0] vco_cur_adj // VCO current adjustment + ,output vco_buff_en // VCO buff enable,active high + ,output vco_en // VCO enable,active high + ,output [2 :0] pll_dpwr_adj // PLL frequency division output power adjustment + ,output [6 :0] vco_fb_adj // VCO frequency band adjustment + ,output afc_en // AFC enable + ,output afc_shutdown // AFC module shutdown signal + ,output [0 :0] afc_det_speed // AFC detection speed + ,output [0 :0] flag_out_sel // Read and choose the signs + ,output afc_reset // AFC reset + ,output [10 :0] afc_cnt // AFC frequency band adjustment function counter + // counting time adjustment + ,output [10 :0] afc_ld_cnt // Adjust the counting time of the AFC lock detection + // feature counter + ,output [3 :0] afc_pres // Adjusting the resolution of the AFC comparator + ,output [14 :0] afc_ld_tcc // AFC Lock Detection Function Target Cycle Count + ,output [14 :0] afc_fb_tcc // Target number of cycles for AFC frequency band + // adjustment function + ,output sync_clr // PLL div sync clr,low active + ,output pll_rstn // PLL reset,active low + ,output [0 :0] div_rstn_sel // div rstn select, 1'b0: ext clear, 1'b1:inter pll lock + ,output [1 :0] test_clk_sel // test clk select, 2'b00:DIV1 clk, 2'b01:DIV2 clk, 2'b10:DIV4 clk, 2'b11:DIV8 clk + ,output [0 :0] test_clk_oen // test clk output enable, 1'b0:disenable, 1'b1:enable + ,output [7 :0] dig_clk_sel // digital main clk select, one hot code,bit[0]-->0 degree phase,bit[1]-->45 degree phase.....bit[7]-->315degree phae + ,output clkrx_pdn // CLock Rx Power Down + ,input pll_lock // PLL LOCK + //------------------------------Ch0 DAC cfg pin---------------------------------------------------- + ,output [2 :0] ch0_dac_addr + ,output [2 :0] ch0_dac_dw + ,output [8 :0] ch0_dac_ref + ,output [16 :0] ch0_dac_Prbs_rst0 + ,output [16 :0] ch0_dac_Prbs_set0 + ,output [16 :0] ch0_dac_Prbs_rst1 + ,output [16 :0] ch0_dac_Prbs_set1 + ,output ch0_dac_Cal_sig + ,output ch0_dac_Cal_rstn + ,output ch0_dac_Cal_div_rstn + ,input ch0_dac_Cal_end + `ifdef CHANNEL_IS_FOUR + //------------------------------Ch1 DAC cfg pin---------------------------------------------------- + ,output [2 :0] ch1_dac_addr + ,output [2 :0] ch1_dac_dw + ,output [8 :0] ch1_dac_ref + ,output [16 :0] ch1_dac_Prbs_rst0 + ,output [16 :0] ch1_dac_Prbs_set0 + ,output [16 :0] ch1_dac_Prbs_rst1 + ,output [16 :0] ch1_dac_Prbs_set1 + ,output ch1_dac_Cal_sig + ,output ch1_dac_Cal_rstn + ,output ch1_dac_Cal_div_rstn + ,output ch1_dac_Digitalclk + ,input ch1_dac_Cal_end + //------------------------------Ch2 DAC cfg pin---------------------------------------------------- + ,output [2 :0] ch2_dac_addr + ,output [2 :0] ch2_dac_dw + ,output [8 :0] ch2_dac_ref + ,output [16 :0] ch2_dac_Prbs_rst0 + ,output [16 :0] ch2_dac_Prbs_set0 + ,output [16 :0] ch2_dac_Prbs_rst1 + ,output [16 :0] ch2_dac_Prbs_set1 + ,output ch2_dac_Cal_sig + ,output ch2_dac_Cal_rstn + ,output ch2_dac_Cal_div_rstn + ,output ch2_dac_Digitalclk + ,input ch2_dac_Cal_end + //------------------------------Ch3 DAC cfg pin---------------------------------------------------- + ,output [2 :0] ch3_dac_addr + ,output [2 :0] ch3_dac_dw + ,output [8 :0] ch3_dac_ref + ,output [16 :0] ch3_dac_Prbs_rst0 + ,output [16 :0] ch3_dac_Prbs_set0 + ,output [16 :0] ch3_dac_Prbs_rst1 + ,output [16 :0] ch3_dac_Prbs_set1 + ,output ch3_dac_Cal_sig + ,output ch3_dac_Cal_rstn + ,output ch3_dac_Cal_div_rstn + ,output ch3_dac_Digitalclk + ,input ch3_dac_Cal_end + `endif + //------------------------------Ch0 DSP data out---------------------------------------------------- + `ifdef CHANNEL_XY_ON + ,output [14:0] ch0_xy_A_DEM_MSB_OUT0 + ,output [14:0] ch0_xy_A_DEM_MSB_OUT1 + ,output [14:0] ch0_xy_A_DEM_MSB_OUT2 + ,output [14:0] ch0_xy_A_DEM_MSB_OUT3 + ,output [14:0] ch0_xy_A_DEM_MSB_OUT4 + ,output [14:0] ch0_xy_A_DEM_MSB_OUT5 + ,output [14:0] ch0_xy_A_DEM_MSB_OUT6 + ,output [14:0] ch0_xy_A_DEM_MSB_OUT7 + ,output [14:0] ch0_xy_B_DEM_MSB_OUT0 + ,output [14:0] ch0_xy_B_DEM_MSB_OUT1 + ,output [14:0] ch0_xy_B_DEM_MSB_OUT2 + ,output [14:0] ch0_xy_B_DEM_MSB_OUT3 + ,output [14:0] ch0_xy_B_DEM_MSB_OUT4 + ,output [14:0] ch0_xy_B_DEM_MSB_OUT5 + ,output [14:0] ch0_xy_B_DEM_MSB_OUT6 + ,output [14:0] ch0_xy_B_DEM_MSB_OUT7 + ,output [6 :0] ch0_xy_A_DEM_ISB_OUT0 + ,output [6 :0] ch0_xy_A_DEM_ISB_OUT1 + ,output [6 :0] ch0_xy_A_DEM_ISB_OUT2 + ,output [6 :0] ch0_xy_A_DEM_ISB_OUT3 + ,output [6 :0] ch0_xy_A_DEM_ISB_OUT4 + ,output [6 :0] ch0_xy_A_DEM_ISB_OUT5 + ,output [6 :0] ch0_xy_A_DEM_ISB_OUT6 + ,output [6 :0] ch0_xy_A_DEM_ISB_OUT7 + ,output [6 :0] ch0_xy_B_DEM_ISB_OUT0 + ,output [6 :0] ch0_xy_B_DEM_ISB_OUT1 + ,output [6 :0] ch0_xy_B_DEM_ISB_OUT2 + ,output [6 :0] ch0_xy_B_DEM_ISB_OUT3 + ,output [6 :0] ch0_xy_B_DEM_ISB_OUT4 + ,output [6 :0] ch0_xy_B_DEM_ISB_OUT5 + ,output [6 :0] ch0_xy_B_DEM_ISB_OUT6 + ,output [6 :0] ch0_xy_B_DEM_ISB_OUT7 + ,output [8 :0] ch0_xy_A_DEM_LSB_OUT0 + ,output [8 :0] ch0_xy_A_DEM_LSB_OUT1 + ,output [8 :0] ch0_xy_A_DEM_LSB_OUT2 + ,output [8 :0] ch0_xy_A_DEM_LSB_OUT3 + ,output [8 :0] ch0_xy_A_DEM_LSB_OUT4 + ,output [8 :0] ch0_xy_A_DEM_LSB_OUT5 + ,output [8 :0] ch0_xy_A_DEM_LSB_OUT6 + ,output [8 :0] ch0_xy_A_DEM_LSB_OUT7 + ,output [8 :0] ch0_xy_B_DEM_LSB_OUT0 + ,output [8 :0] ch0_xy_B_DEM_LSB_OUT1 + ,output [8 :0] ch0_xy_B_DEM_LSB_OUT2 + ,output [8 :0] ch0_xy_B_DEM_LSB_OUT3 + ,output [8 :0] ch0_xy_B_DEM_LSB_OUT4 + ,output [8 :0] ch0_xy_B_DEM_LSB_OUT5 + ,output [8 :0] ch0_xy_B_DEM_LSB_OUT6 + ,output [8 :0] ch0_xy_B_DEM_LSB_OUT7 + `endif + `ifdef CHANNEL_Z_ON + ,output [14 :0] ch0_z_DEM_MSB_OUT0 + ,output [14 :0] ch0_z_DEM_MSB_OUT1 + ,output [14 :0] ch0_z_DEM_MSB_OUT2 + ,output [14 :0] ch0_z_DEM_MSB_OUT3 + ,output [6 :0] ch0_z_DEM_ISB_OUT0 + ,output [6 :0] ch0_z_DEM_ISB_OUT1 + ,output [6 :0] ch0_z_DEM_ISB_OUT2 + ,output [6 :0] ch0_z_DEM_ISB_OUT3 + ,output [8 :0] ch0_z_DEM_LSB_OUT0 + ,output [8 :0] ch0_z_DEM_LSB_OUT1 + ,output [8 :0] ch0_z_DEM_LSB_OUT2 + ,output [8 :0] ch0_z_DEM_LSB_OUT3 + `endif + `ifdef CHANNEL_IS_FOUR + //------------------------------Ch1 DSP data out---------------------------------------------------- + `ifdef CHANNEL_XY_ON + ,output [14:0] ch1_xy_A_DEM_MSB_OUT0 + ,output [14:0] ch1_xy_A_DEM_MSB_OUT1 + ,output [14:0] ch1_xy_A_DEM_MSB_OUT2 + ,output [14:0] ch1_xy_A_DEM_MSB_OUT3 + ,output [14:0] ch1_xy_A_DEM_MSB_OUT4 + ,output [14:0] ch1_xy_A_DEM_MSB_OUT5 + ,output [14:0] ch1_xy_A_DEM_MSB_OUT6 + ,output [14:0] ch1_xy_A_DEM_MSB_OUT7 + ,output [14:0] ch1_xy_B_DEM_MSB_OUT0 + ,output [14:0] ch1_xy_B_DEM_MSB_OUT1 + ,output [14:0] ch1_xy_B_DEM_MSB_OUT2 + ,output [14:0] ch1_xy_B_DEM_MSB_OUT3 + ,output [14:0] ch1_xy_B_DEM_MSB_OUT4 + ,output [14:0] ch1_xy_B_DEM_MSB_OUT5 + ,output [14:0] ch1_xy_B_DEM_MSB_OUT6 + ,output [14:0] ch1_xy_B_DEM_MSB_OUT7 + ,output [6 :0] ch1_xy_A_DEM_ISB_OUT0 + ,output [6 :0] ch1_xy_A_DEM_ISB_OUT1 + ,output [6 :0] ch1_xy_A_DEM_ISB_OUT2 + ,output [6 :0] ch1_xy_A_DEM_ISB_OUT3 + ,output [6 :0] ch1_xy_A_DEM_ISB_OUT4 + ,output [6 :0] ch1_xy_A_DEM_ISB_OUT5 + ,output [6 :0] ch1_xy_A_DEM_ISB_OUT6 + ,output [6 :0] ch1_xy_A_DEM_ISB_OUT7 + ,output [6 :0] ch1_xy_B_DEM_ISB_OUT0 + ,output [6 :0] ch1_xy_B_DEM_ISB_OUT1 + ,output [6 :0] ch1_xy_B_DEM_ISB_OUT2 + ,output [6 :0] ch1_xy_B_DEM_ISB_OUT3 + ,output [6 :0] ch1_xy_B_DEM_ISB_OUT4 + ,output [6 :0] ch1_xy_B_DEM_ISB_OUT5 + ,output [6 :0] ch1_xy_B_DEM_ISB_OUT6 + ,output [6 :0] ch1_xy_B_DEM_ISB_OUT7 + ,output [8 :0] ch1_xy_A_DEM_LSB_OUT0 + ,output [8 :0] ch1_xy_A_DEM_LSB_OUT1 + ,output [8 :0] ch1_xy_A_DEM_LSB_OUT2 + ,output [8 :0] ch1_xy_A_DEM_LSB_OUT3 + ,output [8 :0] ch1_xy_A_DEM_LSB_OUT4 + ,output [8 :0] ch1_xy_A_DEM_LSB_OUT5 + ,output [8 :0] ch1_xy_A_DEM_LSB_OUT6 + ,output [8 :0] ch1_xy_A_DEM_LSB_OUT7 + ,output [8 :0] ch1_xy_B_DEM_LSB_OUT0 + ,output [8 :0] ch1_xy_B_DEM_LSB_OUT1 + ,output [8 :0] ch1_xy_B_DEM_LSB_OUT2 + ,output [8 :0] ch1_xy_B_DEM_LSB_OUT3 + ,output [8 :0] ch1_xy_B_DEM_LSB_OUT4 + ,output [8 :0] ch1_xy_B_DEM_LSB_OUT5 + ,output [8 :0] ch1_xy_B_DEM_LSB_OUT6 + ,output [8 :0] ch1_xy_B_DEM_LSB_OUT7 + `endif + `ifdef CHANNEL_Z_ON + ,output [14 :0] ch1_z_DEM_MSB_OUT0 + ,output [14 :0] ch1_z_DEM_MSB_OUT1 + ,output [14 :0] ch1_z_DEM_MSB_OUT2 + ,output [14 :0] ch1_z_DEM_MSB_OUT3 + ,output [6 :0] ch1_z_DEM_ISB_OUT0 + ,output [6 :0] ch1_z_DEM_ISB_OUT1 + ,output [6 :0] ch1_z_DEM_ISB_OUT2 + ,output [6 :0] ch1_z_DEM_ISB_OUT3 + ,output [8 :0] ch1_z_DEM_LSB_OUT0 + ,output [8 :0] ch1_z_DEM_LSB_OUT1 + ,output [8 :0] ch1_z_DEM_LSB_OUT2 + ,output [8 :0] ch1_z_DEM_LSB_OUT3 + `endif + //------------------------------Ch2 DSP data out---------------------------------------------------- + `ifdef CHANNEL_XY_ON + ,output [14:0] ch2_xy_A_DEM_MSB_OUT0 + ,output [14:0] ch2_xy_A_DEM_MSB_OUT1 + ,output [14:0] ch2_xy_A_DEM_MSB_OUT2 + ,output [14:0] ch2_xy_A_DEM_MSB_OUT3 + ,output [14:0] ch2_xy_A_DEM_MSB_OUT4 + ,output [14:0] ch2_xy_A_DEM_MSB_OUT5 + ,output [14:0] ch2_xy_A_DEM_MSB_OUT6 + ,output [14:0] ch2_xy_A_DEM_MSB_OUT7 + ,output [14:0] ch2_xy_B_DEM_MSB_OUT0 + ,output [14:0] ch2_xy_B_DEM_MSB_OUT1 + ,output [14:0] ch2_xy_B_DEM_MSB_OUT2 + ,output [14:0] ch2_xy_B_DEM_MSB_OUT3 + ,output [14:0] ch2_xy_B_DEM_MSB_OUT4 + ,output [14:0] ch2_xy_B_DEM_MSB_OUT5 + ,output [14:0] ch2_xy_B_DEM_MSB_OUT6 + ,output [14:0] ch2_xy_B_DEM_MSB_OUT7 + ,output [6 :0] ch2_xy_A_DEM_ISB_OUT0 + ,output [6 :0] ch2_xy_A_DEM_ISB_OUT1 + ,output [6 :0] ch2_xy_A_DEM_ISB_OUT2 + ,output [6 :0] ch2_xy_A_DEM_ISB_OUT3 + ,output [6 :0] ch2_xy_A_DEM_ISB_OUT4 + ,output [6 :0] ch2_xy_A_DEM_ISB_OUT5 + ,output [6 :0] ch2_xy_A_DEM_ISB_OUT6 + ,output [6 :0] ch2_xy_A_DEM_ISB_OUT7 + ,output [6 :0] ch2_xy_B_DEM_ISB_OUT0 + ,output [6 :0] ch2_xy_B_DEM_ISB_OUT1 + ,output [6 :0] ch2_xy_B_DEM_ISB_OUT2 + ,output [6 :0] ch2_xy_B_DEM_ISB_OUT3 + ,output [6 :0] ch2_xy_B_DEM_ISB_OUT4 + ,output [6 :0] ch2_xy_B_DEM_ISB_OUT5 + ,output [6 :0] ch2_xy_B_DEM_ISB_OUT6 + ,output [6 :0] ch2_xy_B_DEM_ISB_OUT7 + ,output [8 :0] ch2_xy_A_DEM_LSB_OUT0 + ,output [8 :0] ch2_xy_A_DEM_LSB_OUT1 + ,output [8 :0] ch2_xy_A_DEM_LSB_OUT2 + ,output [8 :0] ch2_xy_A_DEM_LSB_OUT3 + ,output [8 :0] ch2_xy_A_DEM_LSB_OUT4 + ,output [8 :0] ch2_xy_A_DEM_LSB_OUT5 + ,output [8 :0] ch2_xy_A_DEM_LSB_OUT6 + ,output [8 :0] ch2_xy_A_DEM_LSB_OUT7 + ,output [8 :0] ch2_xy_B_DEM_LSB_OUT0 + ,output [8 :0] ch2_xy_B_DEM_LSB_OUT1 + ,output [8 :0] ch2_xy_B_DEM_LSB_OUT2 + ,output [8 :0] ch2_xy_B_DEM_LSB_OUT3 + ,output [8 :0] ch2_xy_B_DEM_LSB_OUT4 + ,output [8 :0] ch2_xy_B_DEM_LSB_OUT5 + ,output [8 :0] ch2_xy_B_DEM_LSB_OUT6 + ,output [8 :0] ch2_xy_B_DEM_LSB_OUT7 + `endif + `ifdef CHANNEL_Z_ON + ,output [14 :0] ch2_z_DEM_MSB_OUT0 + ,output [14 :0] ch2_z_DEM_MSB_OUT1 + ,output [14 :0] ch2_z_DEM_MSB_OUT2 + ,output [14 :0] ch2_z_DEM_MSB_OUT3 + ,output [6 :0] ch2_z_DEM_ISB_OUT0 + ,output [6 :0] ch2_z_DEM_ISB_OUT1 + ,output [6 :0] ch2_z_DEM_ISB_OUT2 + ,output [6 :0] ch2_z_DEM_ISB_OUT3 + ,output [8 :0] ch2_z_DEM_LSB_OUT0 + ,output [8 :0] ch2_z_DEM_LSB_OUT1 + ,output [8 :0] ch2_z_DEM_LSB_OUT2 + ,output [8 :0] ch2_z_DEM_LSB_OUT3 + `endif + //------------------------------Ch3 DSP data out---------------------------------------------------- + `ifdef CHANNEL_XY_ON + ,output [14:0] ch3_xy_A_DEM_MSB_OUT0 + ,output [14:0] ch3_xy_A_DEM_MSB_OUT1 + ,output [14:0] ch3_xy_A_DEM_MSB_OUT2 + ,output [14:0] ch3_xy_A_DEM_MSB_OUT3 + ,output [14:0] ch3_xy_A_DEM_MSB_OUT4 + ,output [14:0] ch3_xy_A_DEM_MSB_OUT5 + ,output [14:0] ch3_xy_A_DEM_MSB_OUT6 + ,output [14:0] ch3_xy_A_DEM_MSB_OUT7 + ,output [14:0] ch3_xy_B_DEM_MSB_OUT0 + ,output [14:0] ch3_xy_B_DEM_MSB_OUT1 + ,output [14:0] ch3_xy_B_DEM_MSB_OUT2 + ,output [14:0] ch3_xy_B_DEM_MSB_OUT3 + ,output [14:0] ch3_xy_B_DEM_MSB_OUT4 + ,output [14:0] ch3_xy_B_DEM_MSB_OUT5 + ,output [14:0] ch3_xy_B_DEM_MSB_OUT6 + ,output [14:0] ch3_xy_B_DEM_MSB_OUT7 + ,output [6 :0] ch3_xy_A_DEM_ISB_OUT0 + ,output [6 :0] ch3_xy_A_DEM_ISB_OUT1 + ,output [6 :0] ch3_xy_A_DEM_ISB_OUT2 + ,output [6 :0] ch3_xy_A_DEM_ISB_OUT3 + ,output [6 :0] ch3_xy_A_DEM_ISB_OUT4 + ,output [6 :0] ch3_xy_A_DEM_ISB_OUT5 + ,output [6 :0] ch3_xy_A_DEM_ISB_OUT6 + ,output [6 :0] ch3_xy_A_DEM_ISB_OUT7 + ,output [6 :0] ch3_xy_B_DEM_ISB_OUT0 + ,output [6 :0] ch3_xy_B_DEM_ISB_OUT1 + ,output [6 :0] ch3_xy_B_DEM_ISB_OUT2 + ,output [6 :0] ch3_xy_B_DEM_ISB_OUT3 + ,output [6 :0] ch3_xy_B_DEM_ISB_OUT4 + ,output [6 :0] ch3_xy_B_DEM_ISB_OUT5 + ,output [6 :0] ch3_xy_B_DEM_ISB_OUT6 + ,output [6 :0] ch3_xy_B_DEM_ISB_OUT7 + ,output [8 :0] ch3_xy_A_DEM_LSB_OUT0 + ,output [8 :0] ch3_xy_A_DEM_LSB_OUT1 + ,output [8 :0] ch3_xy_A_DEM_LSB_OUT2 + ,output [8 :0] ch3_xy_A_DEM_LSB_OUT3 + ,output [8 :0] ch3_xy_A_DEM_LSB_OUT4 + ,output [8 :0] ch3_xy_A_DEM_LSB_OUT5 + ,output [8 :0] ch3_xy_A_DEM_LSB_OUT6 + ,output [8 :0] ch3_xy_A_DEM_LSB_OUT7 + ,output [8 :0] ch3_xy_B_DEM_LSB_OUT0 + ,output [8 :0] ch3_xy_B_DEM_LSB_OUT1 + ,output [8 :0] ch3_xy_B_DEM_LSB_OUT2 + ,output [8 :0] ch3_xy_B_DEM_LSB_OUT3 + ,output [8 :0] ch3_xy_B_DEM_LSB_OUT4 + ,output [8 :0] ch3_xy_B_DEM_LSB_OUT5 + ,output [8 :0] ch3_xy_B_DEM_LSB_OUT6 + ,output [8 :0] ch3_xy_B_DEM_LSB_OUT7 + `endif + `ifdef CHANNEL_Z_ON + ,output [14 :0] ch3_z_DEM_MSB_OUT0 + ,output [14 :0] ch3_z_DEM_MSB_OUT1 + ,output [14 :0] ch3_z_DEM_MSB_OUT2 + ,output [14 :0] ch3_z_DEM_MSB_OUT3 + ,output [6 :0] ch3_z_DEM_ISB_OUT0 + ,output [6 :0] ch3_z_DEM_ISB_OUT1 + ,output [6 :0] ch3_z_DEM_ISB_OUT2 + ,output [6 :0] ch3_z_DEM_ISB_OUT3 + ,output [8 :0] ch3_z_DEM_LSB_OUT0 + ,output [8 :0] ch3_z_DEM_LSB_OUT1 + ,output [8 :0] ch3_z_DEM_LSB_OUT2 + ,output [8 :0] ch3_z_DEM_LSB_OUT3 + `endif + `endif +); + +parameter WRITE = 1'b0 , + READ = 1'b1 ; + + virtual spi_if vif; + + + BinaryDataReader data_reader = new(); + spi_data_send spi_send = new(); + spi_reg reg_wr = new(); + + +//====================================================================== +/*initial begin + $fsdbAutoSwitchDumpfile(500, "./verdplus.fsdb", 1000000); + $fsdbDumpvars(); +end */ +//====================================================================== +//clock & reset & bootsel +//====================================================================== +//logic clk ; +//logic rstn ; +//logic clk_rstn ; +logic qbmcu_i_start ; +bit data[$]; + +//parameter SYS_PERIOD = 2; +//sys_clk --> 50M, 0 phase +//initial begin +// clk =0; +//forever # (SYS_PERIOD/2) clk = ~clk; +//end + + +//hresetn +/* +initial begin + clk_rstn = 0; + rstn = 0; + #1000; + clk_rstn = 0; + #1000; + clk_rstn = 1; + #1000; + rstn = 1; + // $display("m%"); +end +*/ +spi_if aif(.*); + + + +initial begin + aif.sclk = 1'b1; + aif.mosi = 1'b0; + aif.csn = 1'b1; + vif = aif; +end +initial begin + qbmcu_i_start = 1'b0; + + wait (rstn); + +//////////////////////////////////////////////////////////// +//reg cfg +//////////////////////////////////////////////////////////// + +//-----------------debug------------------------------ +//DBGCFGR 16'h34 +// dbg_enable = dbgcfgr[0]; 1'b0 -> disable; 1'b1 -> enable; +// dbg_data_sel = dbgcfgr[1]; 1'b0-->mod;1'b1-->dsp +// dbg_ch_sel = dbgcfgr[5:2]; //4'b0001-->ch0;4'b0010-->ch1; + //4'b0100-->ch2;4'b1000-->ch3; +//6'b0001_0_1 + +reg_wr.write_reg(WRITE,`SYSREG_BASEADDR+32'h34,`CHIIPID,32'h00000007,vif); + + + + +//-----------------TC paraneter start------------------------------ +//a_re: +//tcparr0:'00000000E96476E1' +//TCPARHR0 16'h130 -> 32'h00000000 +//TCPARLR0 16'h134 -> 32'hE96476E1 +reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h130,`CHIIPID,32'h00000000,vif); +reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h134,`CHIIPID,32'hE96476E1,vif); +//tcparr1:'FFFFFFFF7AC0925C' +//TCPARHR1 16'h138 -> 32'hFFFFFFFF +//TCPARLR1 16'h13C -> 32'h7AC0925C +reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h138,`CHIIPID,32'hFFFFFFFF,vif); +reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h13C,`CHIIPID,32'h7AC0925C,vif); +//tcparr2:'000000016673A91C' +//TCPARHR2 16'h140 -> 32'h00000001 +//TCPARLR2 16'h144 -> 32'h6673A91C +reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h140,`CHIIPID,32'h00000001,vif); +reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h144,`CHIIPID,32'h6673A91C,vif); +//tcparr3:'0000000013C11A0B' +//TCPARHR3 16'h148 -> 32'h00000000 +//TCPARLR3 16'h14C -> 32'h13C11A0B +reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h148,`CHIIPID,32'h00000000,vif); +reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h14C,`CHIIPID,32'h13C11A0B,vif); +//tcparr4:'0000000000000000' +//TCPARHR4 16'h150 -> 32'h00000000 +//TCPARLR4 16'h154 -> 32'h00000000 +reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h150,`CHIIPID,32'h00000000,vif); +reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h154,`CHIIPID,32'h00000000,vif); +//tcparr5:'0000000000000000' +//TCPARHR5 16'h158 -> 32'h00000000 +//TCPARLR5 16'h15C -> 32'h00000000 +reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h158,`CHIIPID,32'h00000000,vif); +reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h15C,`CHIIPID,32'h00000000,vif); +//a_im: +//tcpair0:'0000000000000000' +//TCPAIHR0 16'h160 -> 32'h00000000 +//TCPAILR0 16'h164 -> 32'h00000000 +reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h160,`CHIIPID,32'h00000000,vif); +reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h164,`CHIIPID,32'h00000000,vif); +//tcpair1:'FFFFFFFF6405CFFB' +//TCPAIHR1 16'h168 -> 32'hFFFFFFFF +//TCPAILR1 16'h16C -> 32'h6405CFFB +reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h168,`CHIIPID,32'hFFFFFFFF,vif); +reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h16C,`CHIIPID,32'h6405CFFB,vif); +//tcpair2:'FFFFFFFEFEF5F1FF' +//TCPAIHR2 16'h170 -> 32'hFFFFFFFE +//TCPAILR2 16'h174 -> 32'hFEF5F1FF +reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h170,`CHIIPID,32'hFFFFFFFE,vif); +reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h174,`CHIIPID,32'hFEF5F1FF,vif); +//tcpair3:'0000000000000000' +//TCPAIHR3 16'h178 -> 32'h00000000 +//TCPAILR3 16'h17C -> 32'h00000000 +reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h178,`CHIIPID,32'h00000000,vif); +reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h17C,`CHIIPID,32'h00000000,vif); +//tcpair4:'0000000000000000' +//TCPAIHR4 16'h180 -> 32'h00000000 +//TCPAILR4 16'h184 -> 32'h00000000 +reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h180,`CHIIPID,32'h00000000,vif); +reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h184,`CHIIPID,32'h00000000,vif); +//tcpair5:'0000000000000000' +//TCPAIHR5 16'h188 -> 32'h00000000 +//TCPAILR5 16'h18C -> 32'h00000000 +reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h188,`CHIIPID,32'h00000000,vif); +reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h18C,`CHIIPID,32'h00000000,vif); + +//b_re: +//tcpbrr0:'FFF00E4D' +//TCPBRR0 16'h190 -> 32'hFFF00E4D +reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h190,`CHIIPID,32'hFFF00E4D,vif); +//tcpbrr1:'FFF02C39' +//TCPBRR1 16'h194 -> 32'hFFF02C39 +reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h194,`CHIIPID,32'hFFF02C39,vif); +//tcpbrr2:'FFF028F5' +//TCPBRR2 16'h198 -> 32'hFFF028F5 +reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h198,`CHIIPID,32'hFFF028F5,vif); +//tcpbrr3:'FFF0008C' +//TCPBRR3 16'h19C -> 32'hFFF0008C +reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h19C,`CHIIPID,32'hFFF0008C,vif); +//tcpbrr4:'FFF00000' +//TCPBRR4 16'h1A0 -> 32'hFFF00000 +reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h1A0,`CHIIPID,32'hFFF00000,vif); +//tcpbrr5:'FFF00000' +//TCPBRR5 16'h1A4 -> 32'hFFF00000 +reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h1A4,`CHIIPID,32'hFFF00000,vif); +//b_im: +//tcpbir0:'000000' +//TCPBIR0 16'h1A8 -> 32'h000000 +reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h1A8,`CHIIPID,32'h000000,vif); +//tcpbir1:'0028DC' +//TCPBIR1 16'h1AC -> 32'h0028DC +reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h1AC,`CHIIPID,32'h0028DC,vif); +//tcpbir2:'001140' +//TCPBIR2 16'h1B0 -> 32'h001140 +reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h1B0,`CHIIPID,32'h001140,vif); +//tcpbir3:'000000' +//TCPBIR3 16'h1B4 -> 32'h000000 +reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h1B4,`CHIIPID,32'h000000,vif); +//tcpbir4:'000000' +//TCPBIR4 16'h1B8 -> 32'h000000 +reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h1B8,`CHIIPID,32'h000000,vif); +//tcpbir5:'000000' +//TCPBIR5 16'h1BC -> 32'h000000 +reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h1BC,`CHIIPID,32'h000000,vif); +//-----------------TC paraneter end------------------------------ + + +//[0]-> 1'b1:Synchronous clear enable for the clock divider +//[1]-> 1'b1:Enable synchronous signal output +reg_wr.write_reg(WRITE,`PLL_BASEADDR+32'h4c,`CHIIPID,32'h3,vif); + + +//Set the chip role to XY +reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h128,`CHIIPID,`ROLE,vif); + + + +//Set the chip role to Z & DC mode +//reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h128,`CHIIPID,32'h0000_0003,vif); + + +//---------------------------INTP---------------------------------------------- + +//Set the interpolation factor +//3'b000:x1;3'b001:x2;3'b010:x4; +//3'b011:x8;3'b100:x16; + +reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h104,`CHIIPID,`INTP_MODE,vif); + +//---------------------------INTP---------------------------------------------- + +//Enable synchronous clearing for the mixing NCO +reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h190,`CHIIPID,32'h0000_0001,vif); + +//Set the output data type of the modulator +//1'b0 --> mod modem data; 1'b1 --> mod nco data for XY DAC +//1'b0 --> Z dsp data; 1'b1 --> XY dsp data for Z DAC +reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h1c4,`CHIIPID,`AWG_OUT,vif); + +//Set the carrier frequency of the mixing NCO (2GHz) +reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h10c,`CHIIPID,32'h2AAA_AAAA,vif); +reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h110,`CHIIPID,32'h2AAA_0000,vif); + +//Set the mixer to upper sideband modulation +//1'b0:Upper sideband;1'b1:Lower sideband; +reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h118,`CHIIPID,`MIX_SIDEBAND,vif); + +//Set the mixer output to the mixed signal +//2'b00:bypass;2'b01:mix; +//2'b10:cos;2'b11:sin; +reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h11c,`CHIIPID,`QAM_MODE,vif); + +//Set the DAC data format to normal mode +reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h120,`CHIIPID,`DAC_FORMAT,vif); +//2'b00:NRZ mode;2'b01:MIX mode; +//2'b10:2xNRZ mode;2'b00:reserve; + + + data_reader.read_txt_file(`MCU_INSTR_FILE); + + + //bit data[$]; + data_reader.get_data_queue(data); + + foreach (data[i]) begin + $display("Line %0d: %b", i, data[i]); + end + $display("Send MCU_INSTR_FILE"); + spi_send.send_item(data,vif); + data.delete(); + #100; + + + data_reader.read_txt_file(`MCU_DATA_FILE); + + + //bit data[$]; + data_reader.get_data_queue(data); + + foreach (data[i]) begin + $display("Line %0d: %b", i, data[i]); + end + $display("Send MCU_INSTR_FILE"); + spi_send.send_item(data,vif); + data.delete(); + #100; + + + data_reader.read_txt_file(`ENVE_ID_FILE); + data_reader.get_data_queue(data); + foreach (data[i]) begin + $display("Line %0d: %b", i, data[i]); + end + $display("Send ENVE_ID_FILE"); + spi_send.send_item(data,vif); + data.delete(); + #100; + + data_reader.read_txt_file(`ENVE_DATA_FILE); + data_reader.get_data_queue(data); + foreach (data[i]) begin + $display("Line %0d: %b", i, data[i]); + end + $display("Send ENVE_DATA1_FILE"); + spi_send.send_item(data,vif); + data.delete(); + + #100; + + + + #100; + qbmcu_i_start = 1'b1; + #500; + qbmcu_i_start = 1'b0; + + #100000; + + data_reader.read_txt_file(`READ_FILE); + data_reader.get_data_queue(data); + + #1000000; +reg_wr.write_reg(WRITE,`SYSREG_BASEADDR+32'h34,`CHIIPID,32'h00000000,vif); + foreach (data[i]) begin + $display("Line %0d: %b", i, data[i]); + end + $display("Send READ_FILE"); + spi_send.send_item(data,vif); + data.delete(); +end + + + +/////////////////////////////////////////////////////////////////////////////////////////// +//clk gen +/////////////////////////////////////////////////////////////////////////////////////////// +/* +wire clk_div16_0; +wire clk_div16_1; +wire clk_div16_2; +wire clk_div16_3; +wire clk_div16_4; +wire clk_div16_5; +wire clk_div16_6; +wire clk_div16_7; +wire clk_div16_8; +wire clk_div16_9; +wire clk_div16_a; +wire clk_div16_b; +wire clk_div16_c; +wire clk_div16_d; +wire clk_div16_e; +wire clk_div16_f; + + +clk_gen inst_clk_gen( + .rstn (clk_rstn ) + ,.clk (clk ) + ,.clk_div16_0 (clk_div16_0 ) + ,.clk_div16_1 (clk_div16_1 ) + ,.clk_div16_2 (clk_div16_2 ) + ,.clk_div16_3 (clk_div16_3 ) + ,.clk_div16_4 (clk_div16_4 ) + ,.clk_div16_5 (clk_div16_5 ) + ,.clk_div16_6 (clk_div16_6 ) + ,.clk_div16_7 (clk_div16_7 ) + ,.clk_div16_8 (clk_div16_8 ) + ,.clk_div16_9 (clk_div16_9 ) + ,.clk_div16_a (clk_div16_a ) + ,.clk_div16_b (clk_div16_b ) + ,.clk_div16_c (clk_div16_c ) + ,.clk_div16_d (clk_div16_d ) + ,.clk_div16_e (clk_div16_e ) + ,.clk_div16_f (clk_div16_f ) + ,.clk_h (clk_h ) + ,.clk_l (clk_l ) + ); + */ + + + +//////////////////////////////////////////////////////////////////////////////////////// +//DUT +//////////////////////////////////////////////////////////////////////////////////////// +wire async_rstn = rstn; +wire por_rstn = 1'b1; +logic sync_out ; +logic [1 :0] ch0_feedback = 2'b00; +wire [4 :0] cfgid = 5'b00000; +/* +logic irq; + +//------------------------------PLL cfg pin---------------------------------------------------- +logic ref_sel ; // Clock source selection for a frequency divider; + // 1'b0:External clock source + // 1'b1:internal phase-locked loop clock source +logic ref_en ; // Input reference clock enable + // 1'b0:enable,1'b1:disable +logic ref_s2d_en ; // Referenced clock differential to single-ended conversion enable + // 1'b0:enable,1'b1:disable +logic [6 :0] p_cnt ; // P counter +logic pfd_delay ; // PFD Dead Zone +logic pfd_dff_Set ; // Setting the PFD register,active high +logic pfd_dff_4and ; // PFD output polarity +logic [3 :0] spd_div ; // SPD Frequency Divider +logic spd_pulse_width ; // Pulse Width of SPD +logic spd_pulse_sw ; // Pulse sw of SPD +logic cpc_sel ; // current source selection +logic [1 :0] swcp_i ; // PTAT current switch +logic [3 :0] sw_ptat_r ; // PTAT current adjustment +logic [1 :0] sw_fll_cpi ; // Phase-locked loop charge pump current +logic sw_fll_delay ; // PLL Dead Zone +logic pfd_sel ; // PFD Loop selection +logic spd_sel ; // SPD Loop selection +logic fll_sel ; // FLL Loop selection +logic vco_tc ; // VCO temperature compensation +logic vco_tcr ; // VCO temperature compensation resistor +logic vco_gain_adj ; // VCO gain adjustment +logic vco_gain_adj_r ; // VCO gain adjustment resistor +logic [2 :0] vco_cur_adj ; // VCO current adjustment +logic vco_buff_en ; // VCO buff enable,active high +logic vco_en ; // VCO enable,active high +logic [2 :0] pll_dpwr_adj ; // PLL frequency division output power adjustment +logic [6 :0] vco_fb_adj ; // VCO frequency band adjustment +logic afc_en ; // AFC enable +logic afc_shutdown ; // AFC module shutdown signal +logic [0 :0] afc_det_speed ; // AFC detection speed +logic [0 :0] flag_out_sel ; // Read and choose the signs +logic afc_reset ; // AFC reset +logic [10 :0] afc_cnt ; // AFC frequency band adjustment function counter + // counting time adjustment +logic [10 :0] afc_ld_cnt ; // Adjust the counting time of the AFC lock detection + // feature counter +logic [3 :0] afc_pres ; // Adjusting the resolution of the AFC comparator +logic [14 :0] afc_ld_tcc ; // AFC Lock Detection Function Target Cycle Count +logic [14 :0] afc_fb_tcc ; // Target number of cycles for AFC frequency band + // adjustment function +logic sync_clr ; // PLL div sync clr,low active +logic pll_rstn ; // PLL reset,active low +logic [0 :0] div_rstn_sel ; // div rstn select, 1'b0: ext clear, 1'b1:inter pll lock +logic [1 :0] test_clk_sel ; // test clk select, 2'b00:DIV1 clk, 2'b01:DIV2 clk, 2'b10:DIV4 clk, 2'b11:DIV8 clk +logic [0 :0] test_clk_oen ; // test clk output enable, 1'b0:disenable, 1'b1:enable +logic [7 :0] dig_clk_sel ; // digital main clk select, one hot code,bit[0]-->0 degree phase,bit[1]-->45 degree phase.....bit[7]-->315degree phae +logic clkrx_pdn ; +logic pll_lock = 1'b1 ; // PLL LOCK + +//DAC cfg +logic [2 :0] ch0_dac_addr ; +logic [2 :0] ch0_dac_dw ; +logic [8 :0] ch0_dac_ref ; +logic [16 :0] ch0_dac_Prbs_rst0 ; +logic [16 :0] ch0_dac_Prbs_set0 ; +logic [16 :0] ch0_dac_Prbs_rst1 ; +logic [16 :0] ch0_dac_Prbs_set1 ; +logic ch0_dac_Cal_sig ; +logic ch0_dac_Cal_rstn ; +logic ch1_dac_Cal_div_rstn; +logic ch0_dac_Cal_end = 1'b1 ; + +//DSP output +//`ifdef CHANNEL_XY_ON +logic [15 :0] ch0_xy_dsp_dout0 ; +logic [15 :0] ch0_xy_dsp_dout1 ; +logic [15 :0] ch0_xy_dsp_dout2 ; +logic [15 :0] ch0_xy_dsp_dout3 ; +logic [15 :0] ch0_xy_dsp_dout4 ; +logic [15 :0] ch0_xy_dsp_dout5 ; +logic [15 :0] ch0_xy_dsp_dout6 ; +logic [15 :0] ch0_xy_dsp_dout7 ; +logic [15 :0] ch0_xy_dsp_dout8 ; +logic [15 :0] ch0_xy_dsp_dout9 ; +logic [15 :0] ch0_xy_dsp_dout10 ; +logic [15 :0] ch0_xy_dsp_dout11 ; +logic [15 :0] ch0_xy_dsp_dout12 ; +logic [15 :0] ch0_xy_dsp_dout13 ; +logic [15 :0] ch0_xy_dsp_dout14 ; +logic [15 :0] ch0_xy_dsp_dout15 ; +//`endif +//`ifdef CHANNEL_Z_ON +logic [15 :0] ch0_z_dsp_dout0 ; +logic [15 :0] ch0_z_dsp_dout1 ; +logic [15 :0] ch0_z_dsp_dout2 ; +logic [15 :0] ch0_z_dsp_dout3 ; +//`endif + `ifdef CHANNEL_XY_ON +logic [14:0] ch0_xy_A_DEM_MSB_OUT0 ; +logic [14:0] ch0_xy_A_DEM_MSB_OUT1 ; +logic [14:0] ch0_xy_A_DEM_MSB_OUT2 ; +logic [14:0] ch0_xy_A_DEM_MSB_OUT3 ; +logic [14:0] ch0_xy_A_DEM_MSB_OUT4 ; +logic [14:0] ch0_xy_A_DEM_MSB_OUT5 ; +logic [14:0] ch0_xy_A_DEM_MSB_OUT6 ; +logic [14:0] ch0_xy_A_DEM_MSB_OUT7 ; +logic [14:0] ch0_xy_B_DEM_MSB_OUT0 ; +logic [14:0] ch0_xy_B_DEM_MSB_OUT1 ; +logic [14:0] ch0_xy_B_DEM_MSB_OUT2 ; +logic [14:0] ch0_xy_B_DEM_MSB_OUT3 ; +logic [14:0] ch0_xy_B_DEM_MSB_OUT4 ; +logic [14:0] ch0_xy_B_DEM_MSB_OUT5 ; +logic [14:0] ch0_xy_B_DEM_MSB_OUT6 ; +logic [14:0] ch0_xy_B_DEM_MSB_OUT7 ; +logic [6 :0] ch0_xy_A_DEM_ISB_OUT0 ; +logic [6 :0] ch0_xy_A_DEM_ISB_OUT1 ; +logic [6 :0] ch0_xy_A_DEM_ISB_OUT2 ; +logic [6 :0] ch0_xy_A_DEM_ISB_OUT3 ; +logic [6 :0] ch0_xy_A_DEM_ISB_OUT4 ; +logic [6 :0] ch0_xy_A_DEM_ISB_OUT5 ; +logic [6 :0] ch0_xy_A_DEM_ISB_OUT6 ; +logic [6 :0] ch0_xy_A_DEM_ISB_OUT7 ; +logic [6 :0] ch0_xy_B_DEM_ISB_OUT0 ; +logic [6 :0] ch0_xy_B_DEM_ISB_OUT1 ; +logic [6 :0] ch0_xy_B_DEM_ISB_OUT2 ; +logic [6 :0] ch0_xy_B_DEM_ISB_OUT3 ; +logic [6 :0] ch0_xy_B_DEM_ISB_OUT4 ; +logic [6 :0] ch0_xy_B_DEM_ISB_OUT5 ; +logic [6 :0] ch0_xy_B_DEM_ISB_OUT6 ; +logic [6 :0] ch0_xy_B_DEM_ISB_OUT7 ; +logic [8 :0] ch0_xy_A_DEM_LSB_OUT0 ; +logic [8 :0] ch0_xy_A_DEM_LSB_OUT1 ; +logic [8 :0] ch0_xy_A_DEM_LSB_OUT2 ; +logic [8 :0] ch0_xy_A_DEM_LSB_OUT3 ; +logic [8 :0] ch0_xy_A_DEM_LSB_OUT4 ; +logic [8 :0] ch0_xy_A_DEM_LSB_OUT5 ; +logic [8 :0] ch0_xy_A_DEM_LSB_OUT6 ; +logic [8 :0] ch0_xy_A_DEM_LSB_OUT7 ; +logic [8 :0] ch0_xy_B_DEM_LSB_OUT0 ; +logic [8 :0] ch0_xy_B_DEM_LSB_OUT1 ; +logic [8 :0] ch0_xy_B_DEM_LSB_OUT2 ; +logic [8 :0] ch0_xy_B_DEM_LSB_OUT3 ; +logic [8 :0] ch0_xy_B_DEM_LSB_OUT4 ; +logic [8 :0] ch0_xy_B_DEM_LSB_OUT5 ; +logic [8 :0] ch0_xy_B_DEM_LSB_OUT6 ; +logic [8 :0] ch0_xy_B_DEM_LSB_OUT7 ; +`endif +`ifdef CHANNEL_Z_ON +logic [14 :0] ch0_z_DEM_MSB_OUT0 ; +logic [14 :0] ch0_z_DEM_MSB_OUT1 ; +logic [14 :0] ch0_z_DEM_MSB_OUT2 ; +logic [14 :0] ch0_z_DEM_MSB_OUT3 ; +logic [6 :0] ch0_z_DEM_ISB_OUT0 ; +logic [6 :0] ch0_z_DEM_ISB_OUT1 ; +logic [6 :0] ch0_z_DEM_ISB_OUT2 ; +logic [6 :0] ch0_z_DEM_ISB_OUT3 ; +logic [8 :0] ch0_z_DEM_LSB_OUT0 ; +logic [8 :0] ch0_z_DEM_LSB_OUT1 ; +logic [8 :0] ch0_z_DEM_LSB_OUT2 ; +logic [8 :0] ch0_z_DEM_LSB_OUT3 ; +`endif +*/ + + + + + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +xyz_chip_top U_xyz_chip_top ( + .clk ( clk ) + ,.por_rstn ( por_rstn ) + ,.async_rstn ( async_rstn ) + ,.sync_in ( qbmcu_i_start ) + ,.sync_out ( sync_out ) + ,.ch0_feedback ( ch0_feedback ) + `ifdef CHANNEL_IS_FOUR + ,.ch1_feedback ( ch1_feedback ) + ,.ch2_feedback ( ch2_feedback ) + ,.ch3_feedback ( ch3_feedback ) + `endif + ,.cfgid ( cfgid ) + ,.sclk ( aif.sclk ) + ,.csn ( aif.csn ) + ,.mosi ( aif.mosi ) + ,.miso ( miso ) + ,.oen ( oen ) + ,.irq ( irq ) + ,.ref_sel ( ref_sel ) + ,.ref_en ( ref_en ) + ,.ref_s2d_en ( ref_s2d_en ) + ,.p_cnt ( p_cnt ) + ,.pfd_delay ( pfd_delay ) + ,.pfd_dff_Set ( pfd_dff_Set ) + ,.pfd_dff_4and ( pfd_dff_4and ) + ,.spd_div ( spd_div ) + ,.spd_pulse_width ( spd_pulse_width ) + ,.spd_pulse_sw ( spd_pulse_sw ) + ,.cpc_sel ( cpc_sel ) + ,.swcp_i ( swcp_i ) + ,.sw_ptat_r ( sw_ptat_r ) + ,.sw_fll_cpi ( sw_fll_cpi ) + ,.sw_fll_delay ( sw_fll_delay ) + ,.pfd_sel ( pfd_sel ) + ,.spd_sel ( spd_sel ) + ,.fll_sel ( fll_sel ) + ,.vco_tc ( vco_tc ) + ,.vco_tcr ( vco_tcr ) + ,.vco_gain_adj ( vco_gain_adj ) + ,.vco_gain_adj_r ( vco_gain_adj_r ) + ,.vco_cur_adj ( vco_cur_adj ) + ,.vco_buff_en ( vco_buff_en ) + ,.vco_en ( vco_en ) + ,.pll_dpwr_adj ( pll_dpwr_adj ) + ,.vco_fb_adj ( vco_fb_adj ) + ,.afc_en ( afc_en ) + ,.afc_shutdown ( afc_shutdown ) + ,.afc_det_speed ( afc_det_speed ) + ,.flag_out_sel ( flag_out_sel ) + ,.afc_reset ( afc_reset ) + ,.afc_cnt ( afc_cnt ) + ,.afc_ld_cnt ( afc_ld_cnt ) + ,.afc_pres ( afc_pres ) + ,.afc_ld_tcc ( afc_ld_tcc ) + ,.afc_fb_tcc ( afc_fb_tcc ) + ,.sync_clr ( sync_clr ) + ,.pll_rstn ( pll_rstn ) + ,.div_rstn_sel ( div_rstn_sel ) + ,.test_clk_sel ( test_clk_sel ) + ,.test_clk_oen ( test_clk_oen ) + ,.dig_clk_sel ( dig_clk_sel ) + ,.clkrx_pdn ( clkrx_pdn ) + ,.pll_lock ( pll_lock ) + ,.ch0_dac_addr ( ch0_dac_addr ) + ,.ch0_dac_dw ( ch0_dac_dw ) + ,.ch0_dac_ref ( ch0_dac_ref ) + ,.ch0_dac_Prbs_rst0 ( ch0_dac_Prbs_rst0 ) + ,.ch0_dac_Prbs_set0 ( ch0_dac_Prbs_set0 ) + ,.ch0_dac_Prbs_rst1 ( ch0_dac_Prbs_rst1 ) + ,.ch0_dac_Prbs_set1 ( ch0_dac_Prbs_set1 ) + ,.ch0_dac_Cal_sig ( ch0_dac_Cal_sig ) + ,.ch0_dac_Cal_rstn ( ch0_dac_Cal_rstn ) + ,.ch0_dac_Cal_div_rstn ( ch0_dac_Cal_div_rstn ) + ,.ch0_dac_Cal_end ( ch0_dac_Cal_end ) + `ifdef CHANNEL_IS_FOUR + ,.ch1_dac_addr ( ch1_dac_addr ) + ,.ch1_dac_dw ( ch1_dac_dw ) + ,.ch1_dac_ref ( ch1_dac_ref ) + ,.ch1_dac_Prbs_rst0 ( ch1_dac_Prbs_rst0 ) + ,.ch1_dac_Prbs_set0 ( ch1_dac_Prbs_set0 ) + ,.ch1_dac_Prbs_rst1 ( ch1_dac_Prbs_rst1 ) + ,.ch1_dac_Prbs_set1 ( ch1_dac_Prbs_set1 ) + ,.ch1_dac_Cal_sig ( ch1_dac_Cal_sig ) + ,.ch1_dac_Cal_rstn ( ch1_dac_Cal_rstn ) + ,.ch1_dac_Cal_div_rstn ( ch1_dac_Cal_div_rstn ) + ,.ch1_dac_Cal_end ( ch1_dac_Cal_end ) + ,.ch2_dac_addr ( ch2_dac_addr ) + ,.ch2_dac_dw ( ch2_dac_dw ) + ,.ch2_dac_ref ( ch2_dac_ref ) + ,.ch2_dac_Prbs_rst0 ( ch2_dac_Prbs_rst0 ) + ,.ch2_dac_Prbs_set0 ( ch2_dac_Prbs_set0 ) + ,.ch2_dac_Prbs_rst1 ( ch2_dac_Prbs_rst1 ) + ,.ch2_dac_Prbs_set1 ( ch2_dac_Prbs_set1 ) + ,.ch2_dac_Cal_sig ( ch2_dac_Cal_sig ) + ,.ch2_dac_Cal_rstn ( ch2_dac_Cal_rstn ) + ,.ch2_dac_Cal_div_rstn ( ch2_dac_Cal_div_rstn ) + ,.ch2_dac_Cal_end ( ch2_dac_Cal_end ) + ,.ch3_dac_dw ( ch3_dac_dw ) + ,.ch3_dac_ref ( ch3_dac_ref ) + ,.ch3_dac_Prbs_rst0 ( ch3_dac_Prbs_rst0 ) + ,.ch3_dac_Prbs_set0 ( ch3_dac_Prbs_set0 ) + ,.ch3_dac_Prbs_rst1 ( ch3_dac_Prbs_rst1 ) + ,.ch3_dac_Prbs_set1 ( ch3_dac_Prbs_set1 ) + ,.ch3_dac_Cal_sig ( ch3_dac_Cal_sig ) + ,.ch3_dac_Cal_rstn ( ch3_dac_Cal_rstn ) + ,.ch0_dac_Cal_div_rstn ( ch3_dac_Cal_div_rstn ) + ,.ch3_dac_Cal_end ( ch3_dac_Cal_end ) + `endif + //------------------------------Ch0 DSP data out---------------------------------------------------- + `ifdef CHANNEL_XY_ON + ,.ch0_xy_A_DEM_MSB_OUT0 ( ch0_xy_A_DEM_MSB_OUT0 ) + ,.ch0_xy_A_DEM_MSB_OUT1 ( ch0_xy_A_DEM_MSB_OUT1 ) + ,.ch0_xy_A_DEM_MSB_OUT2 ( ch0_xy_A_DEM_MSB_OUT2 ) + ,.ch0_xy_A_DEM_MSB_OUT3 ( ch0_xy_A_DEM_MSB_OUT3 ) + ,.ch0_xy_A_DEM_MSB_OUT4 ( ch0_xy_A_DEM_MSB_OUT4 ) + ,.ch0_xy_A_DEM_MSB_OUT5 ( ch0_xy_A_DEM_MSB_OUT5 ) + ,.ch0_xy_A_DEM_MSB_OUT6 ( ch0_xy_A_DEM_MSB_OUT6 ) + ,.ch0_xy_A_DEM_MSB_OUT7 ( ch0_xy_A_DEM_MSB_OUT7 ) + ,.ch0_xy_B_DEM_MSB_OUT0 ( ch0_xy_B_DEM_MSB_OUT0 ) + ,.ch0_xy_B_DEM_MSB_OUT1 ( ch0_xy_B_DEM_MSB_OUT1 ) + ,.ch0_xy_B_DEM_MSB_OUT2 ( ch0_xy_B_DEM_MSB_OUT2 ) + ,.ch0_xy_B_DEM_MSB_OUT3 ( ch0_xy_B_DEM_MSB_OUT3 ) + ,.ch0_xy_B_DEM_MSB_OUT4 ( ch0_xy_B_DEM_MSB_OUT4 ) + ,.ch0_xy_B_DEM_MSB_OUT5 ( ch0_xy_B_DEM_MSB_OUT5 ) + ,.ch0_xy_B_DEM_MSB_OUT6 ( ch0_xy_B_DEM_MSB_OUT6 ) + ,.ch0_xy_B_DEM_MSB_OUT7 ( ch0_xy_B_DEM_MSB_OUT7 ) + ,.ch0_xy_A_DEM_ISB_OUT0 ( ch0_xy_A_DEM_ISB_OUT0 ) + ,.ch0_xy_A_DEM_ISB_OUT1 ( ch0_xy_A_DEM_ISB_OUT1 ) + ,.ch0_xy_A_DEM_ISB_OUT2 ( ch0_xy_A_DEM_ISB_OUT2 ) + ,.ch0_xy_A_DEM_ISB_OUT3 ( ch0_xy_A_DEM_ISB_OUT3 ) + ,.ch0_xy_A_DEM_ISB_OUT4 ( ch0_xy_A_DEM_ISB_OUT4 ) + ,.ch0_xy_A_DEM_ISB_OUT5 ( ch0_xy_A_DEM_ISB_OUT5 ) + ,.ch0_xy_A_DEM_ISB_OUT6 ( ch0_xy_A_DEM_ISB_OUT6 ) + ,.ch0_xy_A_DEM_ISB_OUT7 ( ch0_xy_A_DEM_ISB_OUT7 ) + ,.ch0_xy_B_DEM_ISB_OUT0 ( ch0_xy_B_DEM_ISB_OUT0 ) + ,.ch0_xy_B_DEM_ISB_OUT1 ( ch0_xy_B_DEM_ISB_OUT1 ) + ,.ch0_xy_B_DEM_ISB_OUT2 ( ch0_xy_B_DEM_ISB_OUT2 ) + ,.ch0_xy_B_DEM_ISB_OUT3 ( ch0_xy_B_DEM_ISB_OUT3 ) + ,.ch0_xy_B_DEM_ISB_OUT4 ( ch0_xy_B_DEM_ISB_OUT4 ) + ,.ch0_xy_B_DEM_ISB_OUT5 ( ch0_xy_B_DEM_ISB_OUT5 ) + ,.ch0_xy_B_DEM_ISB_OUT6 ( ch0_xy_B_DEM_ISB_OUT6 ) + ,.ch0_xy_B_DEM_ISB_OUT7 ( ch0_xy_B_DEM_ISB_OUT7 ) + ,.ch0_xy_A_DEM_LSB_OUT0 ( ch0_xy_A_DEM_LSB_OUT0 ) + ,.ch0_xy_A_DEM_LSB_OUT1 ( ch0_xy_A_DEM_LSB_OUT1 ) + ,.ch0_xy_A_DEM_LSB_OUT2 ( ch0_xy_A_DEM_LSB_OUT2 ) + ,.ch0_xy_A_DEM_LSB_OUT3 ( ch0_xy_A_DEM_LSB_OUT3 ) + ,.ch0_xy_A_DEM_LSB_OUT4 ( ch0_xy_A_DEM_LSB_OUT4 ) + ,.ch0_xy_A_DEM_LSB_OUT5 ( ch0_xy_A_DEM_LSB_OUT5 ) + ,.ch0_xy_A_DEM_LSB_OUT6 ( ch0_xy_A_DEM_LSB_OUT6 ) + ,.ch0_xy_A_DEM_LSB_OUT7 ( ch0_xy_A_DEM_LSB_OUT7 ) + ,.ch0_xy_B_DEM_LSB_OUT0 ( ch0_xy_B_DEM_LSB_OUT0 ) + ,.ch0_xy_B_DEM_LSB_OUT1 ( ch0_xy_B_DEM_LSB_OUT1 ) + ,.ch0_xy_B_DEM_LSB_OUT2 ( ch0_xy_B_DEM_LSB_OUT2 ) + ,.ch0_xy_B_DEM_LSB_OUT3 ( ch0_xy_B_DEM_LSB_OUT3 ) + ,.ch0_xy_B_DEM_LSB_OUT4 ( ch0_xy_B_DEM_LSB_OUT4 ) + ,.ch0_xy_B_DEM_LSB_OUT5 ( ch0_xy_B_DEM_LSB_OUT5 ) + ,.ch0_xy_B_DEM_LSB_OUT6 ( ch0_xy_B_DEM_LSB_OUT6 ) + ,.ch0_xy_B_DEM_LSB_OUT7 ( ch0_xy_B_DEM_LSB_OUT7 ) + `endif + `ifdef CHANNEL_Z_ON + ,.ch0_z_DEM_MSB_OUT0 ( ch0_z_DEM_MSB_OUT0 ) + ,.ch0_z_DEM_MSB_OUT1 ( ch0_z_DEM_MSB_OUT1 ) + ,.ch0_z_DEM_MSB_OUT2 ( ch0_z_DEM_MSB_OUT2 ) + ,.ch0_z_DEM_MSB_OUT3 ( ch0_z_DEM_MSB_OUT3 ) + ,.ch0_z_DEM_ISB_OUT0 ( ch0_z_DEM_ISB_OUT0 ) + ,.ch0_z_DEM_ISB_OUT1 ( ch0_z_DEM_ISB_OUT1 ) + ,.ch0_z_DEM_ISB_OUT2 ( ch0_z_DEM_ISB_OUT2 ) + ,.ch0_z_DEM_ISB_OUT3 ( ch0_z_DEM_ISB_OUT3 ) + ,.ch0_z_DEM_LSB_OUT0 ( ch0_z_DEM_LSB_OUT0 ) + ,.ch0_z_DEM_LSB_OUT1 ( ch0_z_DEM_LSB_OUT1 ) + ,.ch0_z_DEM_LSB_OUT2 ( ch0_z_DEM_LSB_OUT2 ) + ,.ch0_z_DEM_LSB_OUT3 ( ch0_z_DEM_LSB_OUT3 ) + `endif + `ifdef CHANNEL_IS_FOUR + //------------------------------Ch1 DSP data out---------------------------------------------------- + `ifdef CHANNEL_XY_ON + ,.ch1_xy_A_DEM_MSB_OUT0 ( ch1_xy_A_DEM_MSB_OUT0 ) + ,.ch1_xy_A_DEM_MSB_OUT1 ( ch1_xy_A_DEM_MSB_OUT1 ) + ,.ch1_xy_A_DEM_MSB_OUT2 ( ch1_xy_A_DEM_MSB_OUT2 ) + ,.ch1_xy_A_DEM_MSB_OUT3 ( ch1_xy_A_DEM_MSB_OUT3 ) + ,.ch1_xy_A_DEM_MSB_OUT4 ( ch1_xy_A_DEM_MSB_OUT4 ) + ,.ch1_xy_A_DEM_MSB_OUT5 ( ch1_xy_A_DEM_MSB_OUT5 ) + ,.ch1_xy_A_DEM_MSB_OUT6 ( ch1_xy_A_DEM_MSB_OUT6 ) + ,.ch1_xy_A_DEM_MSB_OUT7 ( ch1_xy_A_DEM_MSB_OUT7 ) + ,.ch1_xy_B_DEM_MSB_OUT0 ( ch1_xy_B_DEM_MSB_OUT0 ) + ,.ch1_xy_B_DEM_MSB_OUT1 ( ch1_xy_B_DEM_MSB_OUT1 ) + ,.ch1_xy_B_DEM_MSB_OUT2 ( ch1_xy_B_DEM_MSB_OUT2 ) + ,.ch1_xy_B_DEM_MSB_OUT3 ( ch1_xy_B_DEM_MSB_OUT3 ) + ,.ch1_xy_B_DEM_MSB_OUT4 ( ch1_xy_B_DEM_MSB_OUT4 ) + ,.ch1_xy_B_DEM_MSB_OUT5 ( ch1_xy_B_DEM_MSB_OUT5 ) + ,.ch1_xy_B_DEM_MSB_OUT6 ( ch1_xy_B_DEM_MSB_OUT6 ) + ,.ch1_xy_B_DEM_MSB_OUT7 ( ch1_xy_B_DEM_MSB_OUT7 ) + ,.ch1_xy_A_DEM_ISB_OUT0 ( ch1_xy_A_DEM_ISB_OUT0 ) + ,.ch1_xy_A_DEM_ISB_OUT1 ( ch1_xy_A_DEM_ISB_OUT1 ) + ,.ch1_xy_A_DEM_ISB_OUT2 ( ch1_xy_A_DEM_ISB_OUT2 ) + ,.ch1_xy_A_DEM_ISB_OUT3 ( ch1_xy_A_DEM_ISB_OUT3 ) + ,.ch1_xy_A_DEM_ISB_OUT4 ( ch1_xy_A_DEM_ISB_OUT4 ) + ,.ch1_xy_A_DEM_ISB_OUT5 ( ch1_xy_A_DEM_ISB_OUT5 ) + ,.ch1_xy_A_DEM_ISB_OUT6 ( ch1_xy_A_DEM_ISB_OUT6 ) + ,.ch1_xy_A_DEM_ISB_OUT7 ( ch1_xy_A_DEM_ISB_OUT7 ) + ,.ch1_xy_B_DEM_ISB_OUT0 ( ch1_xy_B_DEM_ISB_OUT0 ) + ,.ch1_xy_B_DEM_ISB_OUT1 ( ch1_xy_B_DEM_ISB_OUT1 ) + ,.ch1_xy_B_DEM_ISB_OUT2 ( ch1_xy_B_DEM_ISB_OUT2 ) + ,.ch1_xy_B_DEM_ISB_OUT3 ( ch1_xy_B_DEM_ISB_OUT3 ) + ,.ch1_xy_B_DEM_ISB_OUT4 ( ch1_xy_B_DEM_ISB_OUT4 ) + ,.ch1_xy_B_DEM_ISB_OUT5 ( ch1_xy_B_DEM_ISB_OUT5 ) + ,.ch1_xy_B_DEM_ISB_OUT6 ( ch1_xy_B_DEM_ISB_OUT6 ) + ,.ch1_xy_B_DEM_ISB_OUT7 ( ch1_xy_B_DEM_ISB_OUT7 ) + ,.ch1_xy_A_DEM_LSB_OUT0 ( ch1_xy_A_DEM_LSB_OUT0 ) + ,.ch1_xy_A_DEM_LSB_OUT1 ( ch1_xy_A_DEM_LSB_OUT1 ) + ,.ch1_xy_A_DEM_LSB_OUT2 ( ch1_xy_A_DEM_LSB_OUT2 ) + ,.ch1_xy_A_DEM_LSB_OUT3 ( ch1_xy_A_DEM_LSB_OUT3 ) + ,.ch1_xy_A_DEM_LSB_OUT4 ( ch1_xy_A_DEM_LSB_OUT4 ) + ,.ch1_xy_A_DEM_LSB_OUT5 ( ch1_xy_A_DEM_LSB_OUT5 ) + ,.ch1_xy_A_DEM_LSB_OUT6 ( ch1_xy_A_DEM_LSB_OUT6 ) + ,.ch1_xy_A_DEM_LSB_OUT7 ( ch1_xy_A_DEM_LSB_OUT7 ) + ,.ch1_xy_B_DEM_LSB_OUT0 ( ch1_xy_B_DEM_LSB_OUT0 ) + ,.ch1_xy_B_DEM_LSB_OUT1 ( ch1_xy_B_DEM_LSB_OUT1 ) + ,.ch1_xy_B_DEM_LSB_OUT2 ( ch1_xy_B_DEM_LSB_OUT2 ) + ,.ch1_xy_B_DEM_LSB_OUT3 ( ch1_xy_B_DEM_LSB_OUT3 ) + ,.ch1_xy_B_DEM_LSB_OUT4 ( ch1_xy_B_DEM_LSB_OUT4 ) + ,.ch1_xy_B_DEM_LSB_OUT5 ( ch1_xy_B_DEM_LSB_OUT5 ) + ,.ch1_xy_B_DEM_LSB_OUT6 ( ch1_xy_B_DEM_LSB_OUT6 ) + ,.ch1_xy_B_DEM_LSB_OUT7 ( ch1_xy_B_DEM_LSB_OUT7 ) + `endif + `ifdef CHANNEL_Z_ON + ,.ch1_z_DEM_MSB_OUT0 ( ch1_z_DEM_MSB_OUT0 ) + ,.ch1_z_DEM_MSB_OUT1 ( ch1_z_DEM_MSB_OUT1 ) + ,.ch1_z_DEM_MSB_OUT2 ( ch1_z_DEM_MSB_OUT2 ) + ,.ch1_z_DEM_MSB_OUT3 ( ch1_z_DEM_MSB_OUT3 ) + ,.ch1_z_DEM_ISB_OUT0 ( ch1_z_DEM_ISB_OUT0 ) + ,.ch1_z_DEM_ISB_OUT1 ( ch1_z_DEM_ISB_OUT1 ) + ,.ch1_z_DEM_ISB_OUT2 ( ch1_z_DEM_ISB_OUT2 ) + ,.ch1_z_DEM_ISB_OUT3 ( ch1_z_DEM_ISB_OUT3 ) + ,.ch1_z_DEM_LSB_OUT0 ( ch1_z_DEM_LSB_OUT0 ) + ,.ch1_z_DEM_LSB_OUT1 ( ch1_z_DEM_LSB_OUT1 ) + ,.ch1_z_DEM_LSB_OUT2 ( ch1_z_DEM_LSB_OUT2 ) + ,.ch1_z_DEM_LSB_OUT3 ( ch1_z_DEM_LSB_OUT3 ) + `endif + //------------------------------Ch2 DSP data out---------------------------------------------------- + `ifdef CHANNEL_XY_ON + ,.ch2_xy_A_DEM_MSB_OUT0 ( ch2_xy_A_DEM_MSB_OUT0 ) + ,.ch2_xy_A_DEM_MSB_OUT1 ( ch2_xy_A_DEM_MSB_OUT1 ) + ,.ch2_xy_A_DEM_MSB_OUT2 ( ch2_xy_A_DEM_MSB_OUT2 ) + ,.ch2_xy_A_DEM_MSB_OUT3 ( ch2_xy_A_DEM_MSB_OUT3 ) + ,.ch2_xy_A_DEM_MSB_OUT4 ( ch2_xy_A_DEM_MSB_OUT4 ) + ,.ch2_xy_A_DEM_MSB_OUT5 ( ch2_xy_A_DEM_MSB_OUT5 ) + ,.ch2_xy_A_DEM_MSB_OUT6 ( ch2_xy_A_DEM_MSB_OUT6 ) + ,.ch2_xy_A_DEM_MSB_OUT7 ( ch2_xy_A_DEM_MSB_OUT7 ) + ,.ch2_xy_B_DEM_MSB_OUT0 ( ch2_xy_B_DEM_MSB_OUT0 ) + ,.ch2_xy_B_DEM_MSB_OUT1 ( ch2_xy_B_DEM_MSB_OUT1 ) + ,.ch2_xy_B_DEM_MSB_OUT2 ( ch2_xy_B_DEM_MSB_OUT2 ) + ,.ch2_xy_B_DEM_MSB_OUT3 ( ch2_xy_B_DEM_MSB_OUT3 ) + ,.ch2_xy_B_DEM_MSB_OUT4 ( ch2_xy_B_DEM_MSB_OUT4 ) + ,.ch2_xy_B_DEM_MSB_OUT5 ( ch2_xy_B_DEM_MSB_OUT5 ) + ,.ch2_xy_B_DEM_MSB_OUT6 ( ch2_xy_B_DEM_MSB_OUT6 ) + ,.ch2_xy_B_DEM_MSB_OUT7 ( ch2_xy_B_DEM_MSB_OUT7 ) + ,.ch2_xy_A_DEM_ISB_OUT0 ( ch2_xy_A_DEM_ISB_OUT0 ) + ,.ch2_xy_A_DEM_ISB_OUT1 ( ch2_xy_A_DEM_ISB_OUT1 ) + ,.ch2_xy_A_DEM_ISB_OUT2 ( ch2_xy_A_DEM_ISB_OUT2 ) + ,.ch2_xy_A_DEM_ISB_OUT3 ( ch2_xy_A_DEM_ISB_OUT3 ) + ,.ch2_xy_A_DEM_ISB_OUT4 ( ch2_xy_A_DEM_ISB_OUT4 ) + ,.ch2_xy_A_DEM_ISB_OUT5 ( ch2_xy_A_DEM_ISB_OUT5 ) + ,.ch2_xy_A_DEM_ISB_OUT6 ( ch2_xy_A_DEM_ISB_OUT6 ) + ,.ch2_xy_A_DEM_ISB_OUT7 ( ch2_xy_A_DEM_ISB_OUT7 ) + ,.ch2_xy_B_DEM_ISB_OUT0 ( ch2_xy_B_DEM_ISB_OUT0 ) + ,.ch2_xy_B_DEM_ISB_OUT1 ( ch2_xy_B_DEM_ISB_OUT1 ) + ,.ch2_xy_B_DEM_ISB_OUT2 ( ch2_xy_B_DEM_ISB_OUT2 ) + ,.ch2_xy_B_DEM_ISB_OUT3 ( ch2_xy_B_DEM_ISB_OUT3 ) + ,.ch2_xy_B_DEM_ISB_OUT4 ( ch2_xy_B_DEM_ISB_OUT4 ) + ,.ch2_xy_B_DEM_ISB_OUT5 ( ch2_xy_B_DEM_ISB_OUT5 ) + ,.ch2_xy_B_DEM_ISB_OUT6 ( ch2_xy_B_DEM_ISB_OUT6 ) + ,.ch2_xy_B_DEM_ISB_OUT7 ( ch2_xy_B_DEM_ISB_OUT7 ) + ,.ch2_xy_A_DEM_LSB_OUT0 ( ch2_xy_A_DEM_LSB_OUT0 ) + ,.ch2_xy_A_DEM_LSB_OUT1 ( ch2_xy_A_DEM_LSB_OUT1 ) + ,.ch2_xy_A_DEM_LSB_OUT2 ( ch2_xy_A_DEM_LSB_OUT2 ) + ,.ch2_xy_A_DEM_LSB_OUT3 ( ch2_xy_A_DEM_LSB_OUT3 ) + ,.ch2_xy_A_DEM_LSB_OUT4 ( ch2_xy_A_DEM_LSB_OUT4 ) + ,.ch2_xy_A_DEM_LSB_OUT5 ( ch2_xy_A_DEM_LSB_OUT5 ) + ,.ch2_xy_A_DEM_LSB_OUT6 ( ch2_xy_A_DEM_LSB_OUT6 ) + ,.ch2_xy_A_DEM_LSB_OUT7 ( ch2_xy_A_DEM_LSB_OUT7 ) + ,.ch2_xy_B_DEM_LSB_OUT0 ( ch2_xy_B_DEM_LSB_OUT0 ) + ,.ch2_xy_B_DEM_LSB_OUT1 ( ch2_xy_B_DEM_LSB_OUT1 ) + ,.ch2_xy_B_DEM_LSB_OUT2 ( ch2_xy_B_DEM_LSB_OUT2 ) + ,.ch2_xy_B_DEM_LSB_OUT3 ( ch2_xy_B_DEM_LSB_OUT3 ) + ,.ch2_xy_B_DEM_LSB_OUT4 ( ch2_xy_B_DEM_LSB_OUT4 ) + ,.ch2_xy_B_DEM_LSB_OUT5 ( ch2_xy_B_DEM_LSB_OUT5 ) + ,.ch2_xy_B_DEM_LSB_OUT6 ( ch2_xy_B_DEM_LSB_OUT6 ) + ,.ch2_xy_B_DEM_LSB_OUT7 ( ch2_xy_B_DEM_LSB_OUT7 ) + `endif + `ifdef CHANNEL_Z_ON + ,.ch2_z_DEM_MSB_OUT0 ( ch2_z_DEM_MSB_OUT0 ) + ,.ch2_z_DEM_MSB_OUT1 ( ch2_z_DEM_MSB_OUT1 ) + ,.ch2_z_DEM_MSB_OUT2 ( ch2_z_DEM_MSB_OUT2 ) + ,.ch2_z_DEM_MSB_OUT3 ( ch2_z_DEM_MSB_OUT3 ) + ,.ch2_z_DEM_ISB_OUT0 ( ch2_z_DEM_ISB_OUT0 ) + ,.ch2_z_DEM_ISB_OUT1 ( ch2_z_DEM_ISB_OUT1 ) + ,.ch2_z_DEM_ISB_OUT2 ( ch2_z_DEM_ISB_OUT2 ) + ,.ch2_z_DEM_ISB_OUT3 ( ch2_z_DEM_ISB_OUT3 ) + ,.ch2_z_DEM_LSB_OUT0 ( ch2_z_DEM_LSB_OUT0 ) + ,.ch2_z_DEM_LSB_OUT1 ( ch2_z_DEM_LSB_OUT1 ) + ,.ch2_z_DEM_LSB_OUT2 ( ch2_z_DEM_LSB_OUT2 ) + ,.ch2_z_DEM_LSB_OUT3 ( ch2_z_DEM_LSB_OUT3 ) + `endif + //------------------------------Ch3 DSP data out---------------------------------------------------- + `ifdef CHANNEL_XY_ON + ,.ch3_xy_A_DEM_MSB_OUT0 ( ch3_xy_A_DEM_MSB_OUT0 ) + ,.ch3_xy_A_DEM_MSB_OUT1 ( ch3_xy_A_DEM_MSB_OUT1 ) + ,.ch3_xy_A_DEM_MSB_OUT2 ( ch3_xy_A_DEM_MSB_OUT2 ) + ,.ch3_xy_A_DEM_MSB_OUT3 ( ch3_xy_A_DEM_MSB_OUT3 ) + ,.ch3_xy_A_DEM_MSB_OUT4 ( ch3_xy_A_DEM_MSB_OUT4 ) + ,.ch3_xy_A_DEM_MSB_OUT5 ( ch3_xy_A_DEM_MSB_OUT5 ) + ,.ch3_xy_A_DEM_MSB_OUT6 ( ch3_xy_A_DEM_MSB_OUT6 ) + ,.ch3_xy_A_DEM_MSB_OUT7 ( ch3_xy_A_DEM_MSB_OUT7 ) + ,.ch3_xy_B_DEM_MSB_OUT0 ( ch3_xy_B_DEM_MSB_OUT0 ) + ,.ch3_xy_B_DEM_MSB_OUT1 ( ch3_xy_B_DEM_MSB_OUT1 ) + ,.ch3_xy_B_DEM_MSB_OUT2 ( ch3_xy_B_DEM_MSB_OUT2 ) + ,.ch3_xy_B_DEM_MSB_OUT3 ( ch3_xy_B_DEM_MSB_OUT3 ) + ,.ch3_xy_B_DEM_MSB_OUT4 ( ch3_xy_B_DEM_MSB_OUT4 ) + ,.ch3_xy_B_DEM_MSB_OUT5 ( ch3_xy_B_DEM_MSB_OUT5 ) + ,.ch3_xy_B_DEM_MSB_OUT6 ( ch3_xy_B_DEM_MSB_OUT6 ) + ,.ch3_xy_B_DEM_MSB_OUT7 ( ch3_xy_B_DEM_MSB_OUT7 ) + ,.ch3_xy_A_DEM_ISB_OUT0 ( ch3_xy_A_DEM_ISB_OUT0 ) + ,.ch3_xy_A_DEM_ISB_OUT1 ( ch3_xy_A_DEM_ISB_OUT1 ) + ,.ch3_xy_A_DEM_ISB_OUT2 ( ch3_xy_A_DEM_ISB_OUT2 ) + ,.ch3_xy_A_DEM_ISB_OUT3 ( ch3_xy_A_DEM_ISB_OUT3 ) + ,.ch3_xy_A_DEM_ISB_OUT4 ( ch3_xy_A_DEM_ISB_OUT4 ) + ,.ch3_xy_A_DEM_ISB_OUT5 ( ch3_xy_A_DEM_ISB_OUT5 ) + ,.ch3_xy_A_DEM_ISB_OUT6 ( ch3_xy_A_DEM_ISB_OUT6 ) + ,.ch3_xy_A_DEM_ISB_OUT7 ( ch3_xy_A_DEM_ISB_OUT7 ) + ,.ch3_xy_B_DEM_ISB_OUT0 ( ch3_xy_B_DEM_ISB_OUT0 ) + ,.ch3_xy_B_DEM_ISB_OUT1 ( ch3_xy_B_DEM_ISB_OUT1 ) + ,.ch3_xy_B_DEM_ISB_OUT2 ( ch3_xy_B_DEM_ISB_OUT2 ) + ,.ch3_xy_B_DEM_ISB_OUT3 ( ch3_xy_B_DEM_ISB_OUT3 ) + ,.ch3_xy_B_DEM_ISB_OUT4 ( ch3_xy_B_DEM_ISB_OUT4 ) + ,.ch3_xy_B_DEM_ISB_OUT5 ( ch3_xy_B_DEM_ISB_OUT5 ) + ,.ch3_xy_B_DEM_ISB_OUT6 ( ch3_xy_B_DEM_ISB_OUT6 ) + ,.ch3_xy_B_DEM_ISB_OUT7 ( ch3_xy_B_DEM_ISB_OUT7 ) + ,.ch3_xy_A_DEM_LSB_OUT0 ( ch3_xy_A_DEM_LSB_OUT0 ) + ,.ch3_xy_A_DEM_LSB_OUT1 ( ch3_xy_A_DEM_LSB_OUT1 ) + ,.ch3_xy_A_DEM_LSB_OUT2 ( ch3_xy_A_DEM_LSB_OUT2 ) + ,.ch3_xy_A_DEM_LSB_OUT3 ( ch3_xy_A_DEM_LSB_OUT3 ) + ,.ch3_xy_A_DEM_LSB_OUT4 ( ch3_xy_A_DEM_LSB_OUT4 ) + ,.ch3_xy_A_DEM_LSB_OUT5 ( ch3_xy_A_DEM_LSB_OUT5 ) + ,.ch3_xy_A_DEM_LSB_OUT6 ( ch3_xy_A_DEM_LSB_OUT6 ) + ,.ch3_xy_A_DEM_LSB_OUT7 ( ch3_xy_A_DEM_LSB_OUT7 ) + ,.ch3_xy_B_DEM_LSB_OUT0 ( ch3_xy_B_DEM_LSB_OUT0 ) + ,.ch3_xy_B_DEM_LSB_OUT1 ( ch3_xy_B_DEM_LSB_OUT1 ) + ,.ch3_xy_B_DEM_LSB_OUT2 ( ch3_xy_B_DEM_LSB_OUT2 ) + ,.ch3_xy_B_DEM_LSB_OUT3 ( ch3_xy_B_DEM_LSB_OUT3 ) + ,.ch3_xy_B_DEM_LSB_OUT4 ( ch3_xy_B_DEM_LSB_OUT4 ) + ,.ch3_xy_B_DEM_LSB_OUT5 ( ch3_xy_B_DEM_LSB_OUT5 ) + ,.ch3_xy_B_DEM_LSB_OUT6 ( ch3_xy_B_DEM_LSB_OUT6 ) + ,.ch3_xy_B_DEM_LSB_OUT7 ( ch3_xy_B_DEM_LSB_OUT7 ) + `endif + `ifdef CHANNEL_Z_ON + ,.ch3_z_DEM_MSB_OUT0 ( ch3_z_DEM_MSB_OUT0 ) + ,.ch3_z_DEM_MSB_OUT1 ( ch3_z_DEM_MSB_OUT1 ) + ,.ch3_z_DEM_MSB_OUT2 ( ch3_z_DEM_MSB_OUT2 ) + ,.ch3_z_DEM_MSB_OUT3 ( ch3_z_DEM_MSB_OUT3 ) + ,.ch3_z_DEM_ISB_OUT0 ( ch3_z_DEM_ISB_OUT0 ) + ,.ch3_z_DEM_ISB_OUT1 ( ch3_z_DEM_ISB_OUT1 ) + ,.ch3_z_DEM_ISB_OUT2 ( ch3_z_DEM_ISB_OUT2 ) + ,.ch3_z_DEM_ISB_OUT3 ( ch3_z_DEM_ISB_OUT3 ) + ,.ch3_z_DEM_LSB_OUT0 ( ch3_z_DEM_LSB_OUT0 ) + ,.ch3_z_DEM_LSB_OUT1 ( ch3_z_DEM_LSB_OUT1 ) + ,.ch3_z_DEM_LSB_OUT2 ( ch3_z_DEM_LSB_OUT2 ) + ,.ch3_z_DEM_LSB_OUT3 ( ch3_z_DEM_LSB_OUT3 ) + `endif + `endif +); + +//////////////////////////////////////////////////////////////////////////////////////////////////// +/* +thermo2binary_top U0_thermo2binary_top ( + .DEM_MSB_IN ( ch0_xy_A_DEM_MSB_OUT0 ) + ,.DEM_ISB_IN ( ch0_xy_A_DEM_ISB_OUT0 ) + ,.DEM_LSB_IN ( ch0_xy_A_DEM_LSB_OUT0 ) + ,.DOUT ( ch0_xy_dsp_dout0 ) +); + +thermo2binary_top U1_thermo2binary_top ( + .DEM_MSB_IN ( ch0_xy_A_DEM_MSB_OUT1 ) + ,.DEM_ISB_IN ( ch0_xy_A_DEM_ISB_OUT1 ) + ,.DEM_LSB_IN ( ch0_xy_A_DEM_LSB_OUT1 ) + ,.DOUT ( ch0_xy_dsp_dout1 ) +); + +thermo2binary_top U2_thermo2binary_top ( + .DEM_MSB_IN ( ch0_xy_A_DEM_MSB_OUT2 ) + ,.DEM_ISB_IN ( ch0_xy_A_DEM_ISB_OUT2 ) + ,.DEM_LSB_IN ( ch0_xy_A_DEM_LSB_OUT2 ) + ,.DOUT ( ch0_xy_dsp_dout2 ) +); + +thermo2binary_top U3_thermo2binary_top ( + .DEM_MSB_IN ( ch0_xy_A_DEM_MSB_OUT3 ) + ,.DEM_ISB_IN ( ch0_xy_A_DEM_ISB_OUT3 ) + ,.DEM_LSB_IN ( ch0_xy_A_DEM_LSB_OUT3 ) + ,.DOUT ( ch0_xy_dsp_dout3 ) +); + +thermo2binary_top U4_thermo2binary_top ( + .DEM_MSB_IN ( ch0_xy_A_DEM_MSB_OUT4 ) + ,.DEM_ISB_IN ( ch0_xy_A_DEM_ISB_OUT4 ) + ,.DEM_LSB_IN ( ch0_xy_A_DEM_LSB_OUT4 ) + ,.DOUT ( ch0_xy_dsp_dout4 ) +); + +thermo2binary_top U5_thermo2binary_top ( + .DEM_MSB_IN ( ch0_xy_A_DEM_MSB_OUT5 ) + ,.DEM_ISB_IN ( ch0_xy_A_DEM_ISB_OUT5 ) + ,.DEM_LSB_IN ( ch0_xy_A_DEM_LSB_OUT5 ) + ,.DOUT ( ch0_xy_dsp_dout5 ) +); + +thermo2binary_top U6_thermo2binary_top ( + .DEM_MSB_IN ( ch0_xy_A_DEM_MSB_OUT6 ) + ,.DEM_ISB_IN ( ch0_xy_A_DEM_ISB_OUT6 ) + ,.DEM_LSB_IN ( ch0_xy_A_DEM_LSB_OUT6 ) + ,.DOUT ( ch0_xy_dsp_dout6 ) +); + +thermo2binary_top U7_thermo2binary_top ( + .DEM_MSB_IN ( ch0_xy_A_DEM_MSB_OUT7 ) + ,.DEM_ISB_IN ( ch0_xy_A_DEM_ISB_OUT7 ) + ,.DEM_LSB_IN ( ch0_xy_A_DEM_LSB_OUT7 ) + ,.DOUT ( ch0_xy_dsp_dout7 ) +); + +thermo2binary_top U8_thermo2binary_top ( + .DEM_MSB_IN ( ch0_xy_B_DEM_MSB_OUT0 ) + ,.DEM_ISB_IN ( ch0_xy_B_DEM_ISB_OUT0 ) + ,.DEM_LSB_IN ( ch0_xy_B_DEM_LSB_OUT0 ) + ,.DOUT ( ch0_xy_dsp_dout8 ) +); + +thermo2binary_top U9_thermo2binary_top ( + .DEM_MSB_IN ( ch0_xy_B_DEM_MSB_OUT1 ) + ,.DEM_ISB_IN ( ch0_xy_B_DEM_ISB_OUT1 ) + ,.DEM_LSB_IN ( ch0_xy_B_DEM_LSB_OUT1 ) + ,.DOUT ( ch0_xy_dsp_dout9 ) +); + +thermo2binary_top U10_thermo2binary_top ( + .DEM_MSB_IN ( ch0_xy_B_DEM_MSB_OUT2 ) + ,.DEM_ISB_IN ( ch0_xy_B_DEM_ISB_OUT2 ) + ,.DEM_LSB_IN ( ch0_xy_B_DEM_LSB_OUT2 ) + ,.DOUT ( ch0_xy_dsp_dout10 ) +); + +thermo2binary_top U11_thermo2binary_top ( + .DEM_MSB_IN ( ch0_xy_B_DEM_MSB_OUT3 ) + ,.DEM_ISB_IN ( ch0_xy_B_DEM_ISB_OUT3 ) + ,.DEM_LSB_IN ( ch0_xy_B_DEM_LSB_OUT3 ) + ,.DOUT ( ch0_xy_dsp_dout11 ) +); + +thermo2binary_top U12_thermo2binary_top ( + .DEM_MSB_IN ( ch0_xy_B_DEM_MSB_OUT4 ) + ,.DEM_ISB_IN ( ch0_xy_B_DEM_ISB_OUT4 ) + ,.DEM_LSB_IN ( ch0_xy_B_DEM_LSB_OUT4 ) + ,.DOUT ( ch0_xy_dsp_dout12 ) +); + +thermo2binary_top U13_thermo2binary_top ( + .DEM_MSB_IN ( ch0_xy_B_DEM_MSB_OUT5 ) + ,.DEM_ISB_IN ( ch0_xy_B_DEM_ISB_OUT5 ) + ,.DEM_LSB_IN ( ch0_xy_B_DEM_LSB_OUT5 ) + ,.DOUT ( ch0_xy_dsp_dout13 ) +); + + +thermo2binary_top U14_thermo2binary_top ( + .DEM_MSB_IN ( ch0_xy_B_DEM_MSB_OUT6 ) + ,.DEM_ISB_IN ( ch0_xy_B_DEM_ISB_OUT6 ) + ,.DEM_LSB_IN ( ch0_xy_B_DEM_LSB_OUT6 ) + ,.DOUT ( ch0_xy_dsp_dout14 ) +); + +thermo2binary_top U15_thermo2binary_top ( + .DEM_MSB_IN ( ch0_xy_B_DEM_MSB_OUT7 ) + ,.DEM_ISB_IN ( ch0_xy_B_DEM_ISB_OUT7 ) + ,.DEM_LSB_IN ( ch0_xy_B_DEM_LSB_OUT7 ) + ,.DOUT ( ch0_xy_dsp_dout15 ) +); +*/ + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +/* +logic [31:0] cnt_c; + +wire add_cnt = 'b1; + +wire end_cnt = 1'b0; + +wire [31:0] cnt_n = end_cnt ? 32'h0 : + add_cnt ? cnt_c + 1'b1 : + cnt_c ; + + +sirv_gnrl_dffr #(32) cnt_c_dffr (cnt_n, cnt_c, clk, async_rstn); + +initial begin + wait(cnt_c == 32'd100000); + $finish(0); +end +*/ + +/////////////////////////////////////////////////////////////////////// +//XY DEM output data save +/////////////////////////////////////////////////////////////////////// +/* +logic [15:0] cs_wave; +wire [15:0] i_cs_0 = ch0_xy_dsp_dout0 ; +wire [15:0] i_cs_1 = ch0_xy_dsp_dout1 ; +wire [15:0] i_cs_2 = ch0_xy_dsp_dout2 ; +wire [15:0] i_cs_3 = ch0_xy_dsp_dout3 ; +wire [15:0] i_cs_4 = ch0_xy_dsp_dout4 ; +wire [15:0] i_cs_5 = ch0_xy_dsp_dout5 ; +wire [15:0] i_cs_6 = ch0_xy_dsp_dout6 ; +wire [15:0] i_cs_7 = ch0_xy_dsp_dout7 ; +wire [15:0] i_cs_8 = ch0_xy_dsp_dout8 ; +wire [15:0] i_cs_9 = ch0_xy_dsp_dout9 ; +wire [15:0] i_cs_a = ch0_xy_dsp_dout10; +wire [15:0] i_cs_b = ch0_xy_dsp_dout11; +wire [15:0] i_cs_c = ch0_xy_dsp_dout12; +wire [15:0] i_cs_d = ch0_xy_dsp_dout13; +wire [15:0] i_cs_e = ch0_xy_dsp_dout14; +wire [15:0] i_cs_f = ch0_xy_dsp_dout15; + +wire [2:0] intp_mode = U_xyz_chip_top.U_digital_top.U0_channel_top.intp_mode; + +always@(*) + fork + case (intp_mode) + 3'b000 : begin + @(posedge clk_div16_f) + cs_wave = i_cs_0; + end + 3'b001 : begin + @(posedge clk_div16_f) + cs_wave = i_cs_0; + @(posedge clk_div16_7) + cs_wave = i_cs_1; + end + 3'b010 : begin + @(posedge clk_div16_f) + cs_wave = i_cs_0; + @(posedge clk_div16_b) + cs_wave = i_cs_1; + @(posedge clk_div16_7) + cs_wave = i_cs_2; + @(posedge clk_div16_3) + cs_wave = i_cs_3; + end + 3'b011 : begin + @(posedge clk_div16_f) + cs_wave = i_cs_0; + @(posedge clk_div16_d) + cs_wave = i_cs_1; + @(posedge clk_div16_b) + cs_wave = i_cs_2; + @(posedge clk_div16_9) + cs_wave = i_cs_3; + @(posedge clk_div16_7) + cs_wave = i_cs_4; + @(posedge clk_div16_5) + cs_wave = i_cs_5; + @(posedge clk_div16_3) + cs_wave = i_cs_6; + @(posedge clk_div16_1) + cs_wave = i_cs_7; + end + 3'b100 : begin + @(posedge clk_div16_f) + cs_wave = i_cs_0; + @(posedge clk_div16_e) + cs_wave = i_cs_1; + @(posedge clk_div16_d) + cs_wave = i_cs_2; + @(posedge clk_div16_c) + cs_wave = i_cs_3; + @(posedge clk_div16_b) + cs_wave = i_cs_4; + @(posedge clk_div16_a) + cs_wave = i_cs_5; + @(posedge clk_div16_9) + cs_wave = i_cs_6; + @(posedge clk_div16_8) + cs_wave = i_cs_7; + @(posedge clk_div16_7) + cs_wave = i_cs_8; + @(posedge clk_div16_6) + cs_wave = i_cs_9; + @(posedge clk_div16_5) + cs_wave = i_cs_a; + @(posedge clk_div16_4) + cs_wave = i_cs_b; + @(posedge clk_div16_3) + cs_wave = i_cs_c; + @(posedge clk_div16_2) + cs_wave = i_cs_d; + @(posedge clk_div16_1) + cs_wave = i_cs_e; + @(posedge clk_div16_0) + cs_wave = i_cs_f; + end + endcase +join + +integer XY_fid; + +always@(posedge clk) + if(U_xyz_chip_top.U_digital_top.ch0_xy_dsp_dout_vld) + $fwrite(XY_fid,"%d\n",cs_wave); + + + +/////////////////////////////////////////////////////////////////////// +//XY DSP output data save +/////////////////////////////////////////////////////////////////////// + +logic [15:0] dsp_cs_wave; +wire [15:0] dsp_cs_0 = U_xyz_chip_top.ch0_xy_dsp_dout0 ; +wire [15:0] dsp_cs_1 = U_xyz_chip_top.ch0_xy_dsp_dout1 ; +wire [15:0] dsp_cs_2 = U_xyz_chip_top.ch0_xy_dsp_dout2 ; +wire [15:0] dsp_cs_3 = U_xyz_chip_top.ch0_xy_dsp_dout3 ; +wire [15:0] dsp_cs_4 = U_xyz_chip_top.ch0_xy_dsp_dout4 ; +wire [15:0] dsp_cs_5 = U_xyz_chip_top.ch0_xy_dsp_dout5 ; +wire [15:0] dsp_cs_6 = U_xyz_chip_top.ch0_xy_dsp_dout6 ; +wire [15:0] dsp_cs_7 = U_xyz_chip_top.ch0_xy_dsp_dout7 ; +wire [15:0] dsp_cs_8 = U_xyz_chip_top.ch0_xy_dsp_dout8 ; +wire [15:0] dsp_cs_9 = U_xyz_chip_top.ch0_xy_dsp_dout9 ; +wire [15:0] dsp_cs_a = U_xyz_chip_top.ch0_xy_dsp_dout10; +wire [15:0] dsp_cs_b = U_xyz_chip_top.ch0_xy_dsp_dout11; +wire [15:0] dsp_cs_c = U_xyz_chip_top.ch0_xy_dsp_dout12; +wire [15:0] dsp_cs_d = U_xyz_chip_top.ch0_xy_dsp_dout13; +wire [15:0] dsp_cs_e = U_xyz_chip_top.ch0_xy_dsp_dout14; +wire [15:0] dsp_cs_f = U_xyz_chip_top.ch0_xy_dsp_dout15; + +//wire [2:0] intp_mode = U_xyz_chip_top.U_digital_top.U0_channel_top.intp_mode; + +always@(*) + fork + case (intp_mode) + 3'b000 : begin + @(posedge clk_div16_f) + dsp_cs_wave = dsp_cs_0; + end + 3'b001 : begin + @(posedge clk_div16_f) + dsp_cs_wave = dsp_cs_0; + @(posedge clk_div16_7) + dsp_cs_wave = dsp_cs_1; + end + 3'b010 : begin + @(posedge clk_div16_f) + dsp_cs_wave = dsp_cs_0; + @(posedge clk_div16_b) + dsp_cs_wave = dsp_cs_1; + @(posedge clk_div16_7) + dsp_cs_wave = dsp_cs_2; + @(posedge clk_div16_3) + dsp_cs_wave = dsp_cs_3; + end + 3'b011 : begin + @(posedge clk_div16_f) + dsp_cs_wave = dsp_cs_0; + @(posedge clk_div16_d) + dsp_cs_wave = dsp_cs_1; + @(posedge clk_div16_b) + dsp_cs_wave = dsp_cs_2; + @(posedge clk_div16_9) + dsp_cs_wave = dsp_cs_3; + @(posedge clk_div16_7) + dsp_cs_wave = dsp_cs_4; + @(posedge clk_div16_5) + dsp_cs_wave = dsp_cs_5; + @(posedge clk_div16_3) + dsp_cs_wave = dsp_cs_6; + @(posedge clk_div16_1) + dsp_cs_wave = dsp_cs_7; + end + 3'b100 : begin + @(posedge clk_div16_f) + dsp_cs_wave = dsp_cs_0; + @(posedge clk_div16_e) + dsp_cs_wave = dsp_cs_1; + @(posedge clk_div16_d) + dsp_cs_wave = dsp_cs_2; + @(posedge clk_div16_c) + dsp_cs_wave = dsp_cs_3; + @(posedge clk_div16_b) + dsp_cs_wave = dsp_cs_4; + @(posedge clk_div16_a) + dsp_cs_wave = dsp_cs_5; + @(posedge clk_div16_9) + dsp_cs_wave = dsp_cs_6; + @(posedge clk_div16_8) + dsp_cs_wave = dsp_cs_7; + @(posedge clk_div16_7) + dsp_cs_wave = dsp_cs_8; + @(posedge clk_div16_6) + dsp_cs_wave = dsp_cs_9; + @(posedge clk_div16_5) + dsp_cs_wave = dsp_cs_a; + @(posedge clk_div16_4) + dsp_cs_wave = dsp_cs_b; + @(posedge clk_div16_3) + dsp_cs_wave = dsp_cs_c; + @(posedge clk_div16_2) + dsp_cs_wave = dsp_cs_d; + @(posedge clk_div16_1) + dsp_cs_wave = dsp_cs_e; + @(posedge clk_div16_0) + dsp_cs_wave = dsp_cs_f; + end + endcase +join + +integer XY_dsp_fid; + +always@(posedge clk) + if(U_xyz_chip_top.U_digital_top.ch0_xy_dsp_dout_vld) + $fwrite(XY_dsp_fid,"%d\n",dsp_cs_wave); + +/////////////////////////////////////////////////////////////////////// +//Z DSP output data save +/////////////////////////////////////////////////////////////////////// + +logic [15:0] z_wave; +wire [15:0] z_cs_0 = ch0_z_dsp_dout0 ; +wire [15:0] z_cs_1 = ch0_z_dsp_dout1 ; +wire [15:0] z_cs_2 = ch0_z_dsp_dout2 ; +wire [15:0] z_cs_3 = ch0_z_dsp_dout3 ; + + +//wire [2:0] intp_mode = U_xyz_chip_top.U_digital_top.U0_channel_top.intp_mode; + +always@(*) + fork + case (intp_mode) + 3'b000 : begin + @(posedge clk_div16_f) + z_wave = z_cs_0; + end + 3'b001 : begin + @(posedge clk_div16_f) + z_wave = z_cs_0; + @(posedge clk_div16_7) + z_wave = z_cs_1; + end + 3'b010 : begin + @(posedge clk_div16_f) + z_wave = z_cs_0; + @(posedge clk_div16_b) + z_wave = z_cs_1; + @(posedge clk_div16_7) + z_wave = z_cs_2; + @(posedge clk_div16_3) + z_wave = z_cs_3; + end + endcase +join + +integer Z_fid; + +always@(posedge clk) + if(cnt_c > 22'd4096) + $fwrite(Z_fid,"%d\n",z_wave); +*/ +/* +wire [15 :0] ch0_mod_data_i = U_xyz_chip_top.U_digital_top. U_debug_top.U_debug_sampling.ch0_mod_data_i ; +wire [15 :0] ch0_mod_data_q = U_xyz_chip_top.U_digital_top. U_debug_top.U_debug_sampling.ch0_mod_data_q ; +wire ch0_mod_vld = U_xyz_chip_top.U_digital_top. U_debug_top.U_debug_sampling.ch0_mod_vld ; + +integer dbg_mod_fid; + +initial begin + #0; + dbg_mod_fid = $fopen("./dbg_mod_data.dat"); +end + +always@(posedge clk_div16_0) + if(ch0_mod_vld) + $fwrite(dbg_mod_fid,"%h\n",{ch0_mod_data_i,ch0_mod_data_q}); + +wire [511:0] mod_data_c = U_xyz_chip_top.U_digital_top.U_debug_top.U_debug_sampling.mod_data_c ; +wire mod_cen = U_xyz_chip_top.U_digital_top.U_debug_top.U_debug_sampling.mod_cen ; + +integer dbg_mod_data_c_fid; + +initial begin + #0; + dbg_mod_data_c_fid = $fopen("./dbg_mod_data_c.dat"); +end + +always@(posedge clk_div16_0) + if(~mod_cen) + $fwrite(dbg_mod_data_c_fid,"%h\n",mod_data_c); + +*/ +endmodule + +`include "/home/ic6103/DIGITAL/SWB/EZQ-XYZ-M1-V1.0_20240527/EZQ-XYZ-M1-V1.0/EZQ-XYZ-M1/rtl/define/chip_undefine.v" + diff --git a/tb/chip_top/chip_define.v b/tb/chip_top/chip_define.v new file mode 100644 index 0000000..5d16c3f --- /dev/null +++ b/tb/chip_top/chip_define.v @@ -0,0 +1,23 @@ + +//Defining Memory Types + +//`define BEHAVIOR_SIM +//`define XINLINX_FPGA +`define TSMC_IC +//Is the chip a 4-channel one? +//`define CHANNEL_IS_FOUR 1 + + +//Whether to instantiate the XY-channel +`define CHANNEL_XY_ON 1 +//Whether to instantiate the Z-channel +`define CHANNEL_Z_ON 1 + +//Setting the Number of SPI Slave Devices +`define SLVNUM 26 +//Whether SPI Bus Commands Are Buffered +`define SPIBUS_CMD_REG 1 +//Whether SPI Bus Readout Are Buffered +`define SPIBUS_OUT_REG 0 +//Whether Mod mux dout Are Buffered +//`define MODDOUT_MUX_REG diff --git a/tb/chip_top/chip_undefine.v b/tb/chip_top/chip_undefine.v new file mode 100644 index 0000000..b093466 --- /dev/null +++ b/tb/chip_top/chip_undefine.v @@ -0,0 +1,19 @@ + +//Is the chip a 4-channel one? +//`undef CHANNEL_IS_FOUR + + +//Whether to instantiate the XY-channel +`undef CHANNEL_XY_ON +//Whether to instantiate the Z-channel +`undef CHANNEL_Z_ON + +//Setting the Number of SPI Slave Devices +`undef SLVNUM +//Whether SPI Bus Commands Are Buffered +`undef SPIBUS_CMD_REG +//Whether SPI Bus Readout Are Buffered +`undef SPIBUS_OUT_REG + +//Whether Mod mux dout Are Buffered +//`undef MODDOUT_MUX_REG \ No newline at end of file diff --git a/tb/chip_top/clk_gen.v b/tb/chip_top/clk_gen.v new file mode 100644 index 0000000..a9b1e7b --- /dev/null +++ b/tb/chip_top/clk_gen.v @@ -0,0 +1,141 @@ +module clk_gen( + input rstn, + input clk, + output clk_div16_0, + output clk_div16_1, + output clk_div16_2, + output clk_div16_3, + output clk_div16_4, + output clk_div16_5, + output clk_div16_6, + output clk_div16_7, + output clk_div16_8, + output clk_div16_9, + output clk_div16_a, + output clk_div16_b, + output clk_div16_c, + output clk_div16_d, + output clk_div16_e, + output clk_div16_f, + + output clk_h, + output clk_l + ); + +reg [3:0] cnt_ini; +always@(posedge clk or negedge rstn) + if(!rstn) + cnt_ini <= 4'd0; + else if(cnt_ini <= 4'd7) + cnt_ini <= cnt_ini + 4'd1; + else + cnt_ini <= cnt_ini; +wire div_en; +assign div_en = (cnt_ini ==4'd8)? 1'b1:1'b0; + +reg [3:0] cnt_0; +reg [3:0] cnt_1; +reg [3:0] cnt_2; +reg [3:0] cnt_3; +reg [3:0] cnt_4; +reg [3:0] cnt_5; +reg [3:0] cnt_6; +reg [3:0] cnt_7; +reg [3:0] cnt_8; +reg [3:0] cnt_9; +reg [3:0] cnt_a; +reg [3:0] cnt_b; +reg [3:0] cnt_c; +reg [3:0] cnt_d; +reg [3:0] cnt_e; +reg [3:0] cnt_f; + +always@(posedge clk or negedge rstn) + if(!rstn) begin + cnt_0 <= 4'h0; + cnt_1 <= 4'h1; + cnt_2 <= 4'h2; + cnt_3 <= 4'h3; + cnt_4 <= 4'h4; + cnt_5 <= 4'h5; + cnt_6 <= 4'h6; + cnt_7 <= 4'h7; + cnt_8 <= 4'h8; + cnt_9 <= 4'h9; + cnt_a <= 4'ha; + cnt_b <= 4'hb; + cnt_c <= 4'hc; + cnt_d <= 4'hd; + cnt_e <= 4'he; + cnt_f <= 4'hf; + end + else if(div_en) begin + cnt_0 <= cnt_0 + 4'd1; + cnt_1 <= cnt_1 + 4'd1; + cnt_2 <= cnt_2 + 4'd1; + cnt_3 <= cnt_3 + 4'd1; + cnt_4 <= cnt_4 + 4'd1; + cnt_5 <= cnt_5 + 4'd1; + cnt_6 <= cnt_6 + 4'd1; + cnt_7 <= cnt_7 + 4'd1; + cnt_8 <= cnt_8 + 4'd1; + cnt_9 <= cnt_9 + 4'd1; + cnt_a <= cnt_a + 4'd1; + cnt_b <= cnt_b + 4'd1; + cnt_c <= cnt_c + 4'd1; + cnt_d <= cnt_d + 4'd1; + cnt_e <= cnt_e + 4'd1; + cnt_f <= cnt_f + 4'd1; + end + else begin + cnt_0 <= cnt_0; + cnt_1 <= cnt_1; + cnt_2 <= cnt_2; + cnt_3 <= cnt_3; + cnt_4 <= cnt_4; + cnt_5 <= cnt_5; + cnt_6 <= cnt_6; + cnt_7 <= cnt_7; + cnt_8 <= cnt_8; + cnt_9 <= cnt_9; + cnt_a <= cnt_a; + cnt_b <= cnt_b; + cnt_c <= cnt_c; + cnt_d <= cnt_d; + cnt_e <= cnt_e; + cnt_f <= cnt_f; + + end + +assign clk_div16_0 = cnt_0[3]; +assign clk_div16_1 = cnt_1[3]; +assign clk_div16_2 = cnt_2[3]; +assign clk_div16_3 = cnt_3[3]; +assign clk_div16_4 = cnt_4[3]; +assign clk_div16_5 = cnt_5[3]; +assign clk_div16_6 = cnt_6[3]; +assign clk_div16_7 = cnt_7[3]; +assign clk_div16_8 = cnt_8[3]; +assign clk_div16_9 = cnt_9[3]; +assign clk_div16_a = cnt_a[3]; +assign clk_div16_b = cnt_b[3]; +assign clk_div16_c = cnt_c[3]; +assign clk_div16_d = cnt_d[3]; +assign clk_div16_e = cnt_e[3]; +assign clk_div16_f = cnt_f[3]; + + +reg [3:0] cnt_div16; +always@(posedge clk_div16_0 or negedge rstn) + if(!rstn) + cnt_div16 <= 4'd0; + else if(div_en) + cnt_div16 <= cnt_div16 + 4'd1; + else + cnt_div16 <= cnt_div16; + + +assign clk_h = clk_div16_0; +assign clk_l = cnt_div16[0]; + +endmodule diff --git a/tb/chip_top/compile.log b/tb/chip_top/compile.log new file mode 100644 index 0000000..5a23f16 --- /dev/null +++ b/tb/chip_top/compile.log @@ -0,0 +1,34 @@ +Command: vcs -full64 -sverilog +lint=TFIPC-L +v2k -debug_access+all +define+DUMP_FSDB \ +-lca -q -timescale=1ns/1ps +nospecify -P /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab \ +/home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/pli.a -l compile.log \ +-f files.f + +Warning-[LCA_FEATURES_ENABLED] Usage warning + LCA features enabled by '-lca' argument on the command line. For more + information regarding list of LCA features please refer to Chapter "LCA + features" in the VCS/VCS-MX Release Notes + + +Warning-[TMR] Text macro redefined +../../sim/chip_top/TB.sv, 59 + Text macro (MCU_INSTR_FILE) is redefined. The last definition will override + previous ones. + Location of previous definition: ../../sim/chip_top/TB.sv, 58. + Previous value: "../../cfgdata/instrmem/RabiFreqAmp_bin.txt" + + +Warning-[RVOSFD] Return value discarded +../../sim/chip_top/TB.sv, 111 + System function '$fscanf' is invoked as task, its return value is discarded. + "../../sim/chip_top/TB.sv", 111 + Source info: $fscanf(file_id,"%b\n",binary_value); + +Notice: Ports coerced to inout, use -notice for details +38 modules and 0 UDP read. +make[1]: Entering directory '/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/chip_top/csrc' \ + +ld -shared -Bsymbolic -o .//../simv.daidir//_csrc0.so objs/amcQw_d.o +rm -f _csrc0.so +../simv up to date +make[1]: Leaving directory '/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/chip_top/csrc' \ + diff --git a/tb/chip_top/csrc/Makefile b/tb/chip_top/csrc/Makefile new file mode 100644 index 0000000..ef00a4f --- /dev/null +++ b/tb/chip_top/csrc/Makefile @@ -0,0 +1,116 @@ +# Makefile generated by VCS to build your model +# This file may be modified; VCS will not overwrite it unless -Mupdate is used + +# define default verilog source directory +VSRC=.. + +# Override TARGET_ARCH +TARGET_ARCH= + +# Choose name of executable +PRODUCTBASE=$(VSRC)/simv + +PRODUCT=$(PRODUCTBASE) + +# Product timestamp file. If product is newer than this one, +# we will also re-link the product. +PRODUCT_TIMESTAMP=product_timestamp + +# Path to runtime library +DEPLIBS= +VCSUCLI=-lvcsucli +RUNTIME=-lvcsnew -lsimprofile -luclinative /home/synopsys/vcs/O-2018.09-SP2/linux64/lib/vcs_tls.o $(DEPLIBS) + +VCS_SAVE_RESTORE_OBJ=/home/synopsys/vcs/O-2018.09-SP2/linux64/lib/vcs_save_restore_new.o + +# Select your favorite compiler + +# Linux: +VCS_CC=gcc + +# Internal CC for gen_c flow: +CC_CG=gcc +# User overrode default CC: +VCS_CC=gcc +# Loader +LD=g++ + +# Strip Flags for target product +STRIPFLAGS= + +PRE_LDFLAGS= # Loader Flags +LDFLAGS= -rdynamic -Wl,-rpath=/home/synopsys/vcs/O-2018.09-SP2/linux64/lib -L/home/synopsys/vcs/O-2018.09-SP2/linux64/lib +# Picarchive Flags +PICLDFLAGS=-Wl,-rpath-link=./ -Wl,-rpath='$$ORIGIN'/simv.daidir/ -Wl,-rpath=./simv.daidir/ -Wl,-rpath='$$ORIGIN'/simv.daidir//scsim.db.dir + +# C run time startup +CRT0= +# C run time startup +CRTN= +# Machine specific libraries +SYSLIBS=/home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/pli.a -ldl -lm -lc -lpthread -ldl + +# Default defines +SHELL=/bin/sh + +VCSTMPSPECARG= +VCSTMPSPECENV= +# NOTE: if you have little space in $TMPDIR, but plenty in /foo, +#and you are using gcc, uncomment the next line +#VCSTMPSPECENV=SNPS_VCS_TMPDIR=/foo + +TMPSPECARG=$(VCSTMPSPECARG) +TMPSPECENV=$(VCSTMPSPECENV) +CC=$(TMPSPECENV) $(VCS_CC) $(TMPSPECARG) + +# C flags for compilation +CFLAGS=-w -pipe -fPIC -O -I/home/synopsys/vcs/O-2018.09-SP2/include + +CFLAGS_O0=-w -pipe -fPIC -I/home/synopsys/vcs/O-2018.09-SP2/include -O0 -fno-strict-aliasing + +CFLAGS_CG=-w -pipe -fPIC -I/home/synopsys/vcs/O-2018.09-SP2/include -O -fno-strict-aliasing + +LD_PARTIAL_LOADER=ld +# Partial linking +LD_PARTIAL=$(LD_PARTIAL_LOADER) -r -o +ASFLAGS= +LIBS=-lzerosoft_rt_stubs -lvirsim -lerrorinf -lsnpsmalloc -lvfs /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/pli.a +# Note: if make gives you errors about include, either get gmake, or +# replace the following line with the contents of the file filelist, +# EACH TIME IT CHANGES +# included file defines OBJS, and is automatically generated by vcs +include filelist + +OBJS=$(VLOG_OBJS) $(SYSC_OBJS) $(VHDL_OBJS) + +product : $(PRODUCT_TIMESTAMP) + @echo $(PRODUCT) up to date + +objects : $(OBJS) $(DPI_STUB_OBJS) $(PLI_STUB_OBJS) + +clean : + rm -f $(VCS_OBJS) $(CU_OBJS) + +clobber : clean + rm -f $(PRODUCT) $(PRODUCT_TIMESTAMP) + +picclean : + @rm -f _csrc*.so pre_vcsobj_*.so share_vcsobj_*.so + @rm -f $(PRODUCT).daidir/_[0-9]*_archive_*.so 2>/dev/null + +product_clean_order : + @$(MAKE) -f Makefile --no-print-directory picclean + @$(MAKE) -f Makefile --no-print-directory product_order + +product_order : $(PRODUCT) + +$(PRODUCT_TIMESTAMP) : product_clean_order + @-if [ -x $(PRODUCT) ]; then chmod -x $(PRODUCT); fi + @$(LD) $(CRT0) -o $(PRODUCT) $(PRE_LDFLAGS) $(STRIPFLAGS) $(PCLDFLAGS) $(PICLDFLAGS) $(LDFLAGS) $(OBJS) $(LIBS) $(RUNTIME) -Wl,-whole-archive $(VCSUCLI) -Wl,-no-whole-archive $(LINK_TB) $(DPI_STUB_OBJS) $(PLI_STUB_OBJS) $(VCS_SAVE_RESTORE_OBJ) $(SYSLIBS) $(CRTN) + @rm -f csrc[0-9]*.o + @touch $(PRODUCT_TIMESTAMP) + @-if [ -d ./objs ]; then find ./objs -type d -empty -delete; fi + +$(PRODUCT) : $(LD_VERSION_CHECK) $(OBJS) $(DOTLIBS) $(DPI_STUB_OBJS) $(PLI_STUB_OBJS) $(CMODLIB) /home/synopsys/vcs/O-2018.09-SP2/linux64/lib/libvcsnew.so /home/synopsys/vcs/O-2018.09-SP2/linux64/lib/libsimprofile.so /home/synopsys/vcs/O-2018.09-SP2/linux64/lib/libuclinative.so /home/synopsys/vcs/O-2018.09-SP2/linux64/lib/vcs_tls.o /home/synopsys/vcs/O-2018.09-SP2/linux64/lib/libvcsucli.so $(VCS_SAVE_RESTORE_OBJ) + @touch $(PRODUCT) + diff --git a/tb/chip_top/csrc/Makefile.hsopt b/tb/chip_top/csrc/Makefile.hsopt new file mode 100644 index 0000000..6d6350b --- /dev/null +++ b/tb/chip_top/csrc/Makefile.hsopt @@ -0,0 +1,47 @@ +# Makefile generated by VCS to build rmapats.so for your model +VSRC=.. + +# Override TARGET_ARCH +TARGET_ARCH= + +# Select your favorite compiler + +# Linux: +VCS_CC=gcc + +# Internal CC for gen_c flow: +CC_CG=gcc + +# User overrode default CC: +VCS_CC=gcc +# Loader +LD=g++ +# Loader Flags +LDFLAGS= + +# Default defines +SHELL=/bin/sh + +VCSTMPSPECARG= +VCSTMPSPECENV= +# NOTE: if you have little space in $TMPDIR, but plenty in /foo, +#and you are using gcc, uncomment the next line +#VCSTMPSPECENV=SNPS_VCS_TMPDIR=/foo + +TMPSPECARG=$(VCSTMPSPECARG) +TMPSPECENV=$(VCSTMPSPECENV) +CC=$(TMPSPECENV) $(VCS_CC) $(TMPSPECARG) + +# C flags for compilation +CFLAGS=-w -pipe -fPIC -O -I/home/synopsys/vcs/O-2018.09-SP2/include + +CFLAGS_CG=-w -pipe -fPIC -I/home/synopsys/vcs/O-2018.09-SP2/include -O -fno-strict-aliasing + +ASFLAGS= +LIBS= + +include filelist.hsopt + + +rmapats.so: $(HSOPT_OBJS) + @$(VCS_CC) $(LDFLAGS) $(LIBS) -shared -o ./../simv.daidir/rmapats.so $(HSOPT_OBJS) diff --git a/tb/chip_top/csrc/SIM_l.o b/tb/chip_top/csrc/SIM_l.o new file mode 100644 index 0000000..8fd683e Binary files /dev/null and b/tb/chip_top/csrc/SIM_l.o differ diff --git a/tb/chip_top/csrc/_100465_archive_1.so b/tb/chip_top/csrc/_100465_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_10107_archive_1.so b/tb/chip_top/csrc/_10107_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_101457_archive_1.so b/tb/chip_top/csrc/_101457_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_10168_archive_1.so b/tb/chip_top/csrc/_10168_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_103000_archive_1.so b/tb/chip_top/csrc/_103000_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_104123_archive_1.so b/tb/chip_top/csrc/_104123_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_104304_archive_1.so b/tb/chip_top/csrc/_104304_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_105845_archive_1.so b/tb/chip_top/csrc/_105845_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_10628_archive_1.so b/tb/chip_top/csrc/_10628_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_106345_archive_1.so b/tb/chip_top/csrc/_106345_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_106838_archive_1.so b/tb/chip_top/csrc/_106838_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_107019_archive_1.so b/tb/chip_top/csrc/_107019_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_107734_archive_1.so b/tb/chip_top/csrc/_107734_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_108461_archive_1.so b/tb/chip_top/csrc/_108461_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_108724_archive_1.so b/tb/chip_top/csrc/_108724_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_109401_archive_1.so b/tb/chip_top/csrc/_109401_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_110289_archive_1.so b/tb/chip_top/csrc/_110289_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_110299_archive_1.so b/tb/chip_top/csrc/_110299_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_110792_archive_1.so b/tb/chip_top/csrc/_110792_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_11097_archive_1.so b/tb/chip_top/csrc/_11097_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_111001_archive_1.so b/tb/chip_top/csrc/_111001_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_111620_archive_1.so b/tb/chip_top/csrc/_111620_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_111703_archive_1.so b/tb/chip_top/csrc/_111703_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_111941_archive_1.so b/tb/chip_top/csrc/_111941_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_111974_archive_1.so b/tb/chip_top/csrc/_111974_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_112463_archive_1.so b/tb/chip_top/csrc/_112463_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_113252_archive_1.so b/tb/chip_top/csrc/_113252_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_113679_archive_1.so b/tb/chip_top/csrc/_113679_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_113694_archive_1.so b/tb/chip_top/csrc/_113694_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_114074_archive_1.so b/tb/chip_top/csrc/_114074_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_115137_archive_1.so b/tb/chip_top/csrc/_115137_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_115978_archive_1.so b/tb/chip_top/csrc/_115978_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_11628_archive_1.so b/tb/chip_top/csrc/_11628_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_116446_archive_1.so b/tb/chip_top/csrc/_116446_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_116511_archive_1.so b/tb/chip_top/csrc/_116511_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_116685_archive_1.so b/tb/chip_top/csrc/_116685_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_117252_archive_1.so b/tb/chip_top/csrc/_117252_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_117661_archive_1.so b/tb/chip_top/csrc/_117661_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_118384_archive_1.so b/tb/chip_top/csrc/_118384_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_118420_archive_1.so b/tb/chip_top/csrc/_118420_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_11863_archive_1.so b/tb/chip_top/csrc/_11863_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_120277_archive_1.so b/tb/chip_top/csrc/_120277_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_121354_archive_1.so b/tb/chip_top/csrc/_121354_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_121770_archive_1.so b/tb/chip_top/csrc/_121770_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_12224_archive_1.so b/tb/chip_top/csrc/_12224_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_122576_archive_1.so b/tb/chip_top/csrc/_122576_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_122637_archive_1.so b/tb/chip_top/csrc/_122637_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_123963_archive_1.so b/tb/chip_top/csrc/_123963_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_125013_archive_1.so b/tb/chip_top/csrc/_125013_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_125231_archive_1.so b/tb/chip_top/csrc/_125231_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_125905_archive_1.so b/tb/chip_top/csrc/_125905_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_12599_archive_1.so b/tb/chip_top/csrc/_12599_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_126055_archive_1.so b/tb/chip_top/csrc/_126055_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_126124_archive_1.so b/tb/chip_top/csrc/_126124_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_127235_archive_1.so b/tb/chip_top/csrc/_127235_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_127242_archive_1.so b/tb/chip_top/csrc/_127242_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_127852_archive_1.so b/tb/chip_top/csrc/_127852_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_128035_archive_1.so b/tb/chip_top/csrc/_128035_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_128512_archive_1.so b/tb/chip_top/csrc/_128512_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_12886_archive_1.so b/tb/chip_top/csrc/_12886_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_128934_archive_1.so b/tb/chip_top/csrc/_128934_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_129545_archive_1.so b/tb/chip_top/csrc/_129545_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_130246_archive_1.so b/tb/chip_top/csrc/_130246_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_130443_archive_1.so b/tb/chip_top/csrc/_130443_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_130911_archive_1.so b/tb/chip_top/csrc/_130911_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_13194_archive_1.so b/tb/chip_top/csrc/_13194_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_1376_archive_1.so b/tb/chip_top/csrc/_1376_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_13895_archive_1.so b/tb/chip_top/csrc/_13895_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_14056_archive_1.so b/tb/chip_top/csrc/_14056_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_15160_archive_1.so b/tb/chip_top/csrc/_15160_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_15358_archive_1.so b/tb/chip_top/csrc/_15358_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_16216_archive_1.so b/tb/chip_top/csrc/_16216_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_17413_archive_1.so b/tb/chip_top/csrc/_17413_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_17954_archive_1.so b/tb/chip_top/csrc/_17954_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_19122_archive_1.so b/tb/chip_top/csrc/_19122_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_19228_archive_1.so b/tb/chip_top/csrc/_19228_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_20415_archive_1.so b/tb/chip_top/csrc/_20415_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_20450_archive_1.so b/tb/chip_top/csrc/_20450_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_21557_archive_1.so b/tb/chip_top/csrc/_21557_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_21590_archive_1.so b/tb/chip_top/csrc/_21590_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_22700_archive_1.so b/tb/chip_top/csrc/_22700_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_23008_archive_1.so b/tb/chip_top/csrc/_23008_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_23112_archive_1.so b/tb/chip_top/csrc/_23112_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_23612_archive_1.so b/tb/chip_top/csrc/_23612_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_25781_archive_1.so b/tb/chip_top/csrc/_25781_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_25832_archive_1.so b/tb/chip_top/csrc/_25832_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_27589_archive_1.so b/tb/chip_top/csrc/_27589_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_2769_archive_1.so b/tb/chip_top/csrc/_2769_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_29046_archive_1.so b/tb/chip_top/csrc/_29046_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_3127_archive_1.so b/tb/chip_top/csrc/_3127_archive_1.so new file mode 100644 index 0000000..124ddb2 Binary files /dev/null and b/tb/chip_top/csrc/_3127_archive_1.so differ diff --git a/tb/chip_top/csrc/_31328_archive_1.so b/tb/chip_top/csrc/_31328_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_32266_archive_1.so b/tb/chip_top/csrc/_32266_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_32494_archive_1.so b/tb/chip_top/csrc/_32494_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_33358_archive_1.so b/tb/chip_top/csrc/_33358_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_33454_archive_1.so b/tb/chip_top/csrc/_33454_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_33711_archive_1.so b/tb/chip_top/csrc/_33711_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_34450_archive_1.so b/tb/chip_top/csrc/_34450_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_35049_archive_1.so b/tb/chip_top/csrc/_35049_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_35129_archive_1.so b/tb/chip_top/csrc/_35129_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_3531_archive_1.so b/tb/chip_top/csrc/_3531_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_35452_archive_1.so b/tb/chip_top/csrc/_35452_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_35599_archive_1.so b/tb/chip_top/csrc/_35599_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_36082_archive_1.so b/tb/chip_top/csrc/_36082_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_36208_archive_1.so b/tb/chip_top/csrc/_36208_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_36310_archive_1.so b/tb/chip_top/csrc/_36310_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_36378_archive_1.so b/tb/chip_top/csrc/_36378_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_367_archive_1.so b/tb/chip_top/csrc/_367_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_37047_archive_1.so b/tb/chip_top/csrc/_37047_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_37342_archive_1.so b/tb/chip_top/csrc/_37342_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_3744_archive_1.so b/tb/chip_top/csrc/_3744_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_37480_archive_1.so b/tb/chip_top/csrc/_37480_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_37595_archive_1.so b/tb/chip_top/csrc/_37595_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_37839_archive_1.so b/tb/chip_top/csrc/_37839_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_38265_archive_1.so b/tb/chip_top/csrc/_38265_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_39113_archive_1.so b/tb/chip_top/csrc/_39113_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_39709_archive_1.so b/tb/chip_top/csrc/_39709_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_40881_archive_1.so b/tb/chip_top/csrc/_40881_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_41038_archive_1.so b/tb/chip_top/csrc/_41038_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_41391_archive_1.so b/tb/chip_top/csrc/_41391_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_42151_archive_1.so b/tb/chip_top/csrc/_42151_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_42645_archive_1.so b/tb/chip_top/csrc/_42645_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_43072_archive_1.so b/tb/chip_top/csrc/_43072_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_43357_archive_1.so b/tb/chip_top/csrc/_43357_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_43398_archive_1.so b/tb/chip_top/csrc/_43398_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_44208_archive_1.so b/tb/chip_top/csrc/_44208_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_44771_archive_1.so b/tb/chip_top/csrc/_44771_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_46616_archive_1.so b/tb/chip_top/csrc/_46616_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_47050_archive_1.so b/tb/chip_top/csrc/_47050_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_48135_archive_1.so b/tb/chip_top/csrc/_48135_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_51488_archive_1.so b/tb/chip_top/csrc/_51488_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_5192_archive_1.so b/tb/chip_top/csrc/_5192_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_52818_archive_1.so b/tb/chip_top/csrc/_52818_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_53768_archive_1.so b/tb/chip_top/csrc/_53768_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_55152_archive_1.so b/tb/chip_top/csrc/_55152_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_58486_archive_1.so b/tb/chip_top/csrc/_58486_archive_1.so new file mode 100644 index 0000000..e456c6a Binary files /dev/null and b/tb/chip_top/csrc/_58486_archive_1.so differ diff --git a/tb/chip_top/csrc/_5931_archive_1.so b/tb/chip_top/csrc/_5931_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_60878_archive_1.so b/tb/chip_top/csrc/_60878_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_62150_archive_1.so b/tb/chip_top/csrc/_62150_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_62238_archive_1.so b/tb/chip_top/csrc/_62238_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_63588_archive_1.so b/tb/chip_top/csrc/_63588_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_63835_archive_1.so b/tb/chip_top/csrc/_63835_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_63855_archive_1.so b/tb/chip_top/csrc/_63855_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_64586_archive_1.so b/tb/chip_top/csrc/_64586_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_64715_archive_1.so b/tb/chip_top/csrc/_64715_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_66400_archive_1.so b/tb/chip_top/csrc/_66400_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_66851_archive_1.so b/tb/chip_top/csrc/_66851_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_68264_archive_1.so b/tb/chip_top/csrc/_68264_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_6831_archive_1.so b/tb/chip_top/csrc/_6831_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_69660_archive_1.so b/tb/chip_top/csrc/_69660_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_72002_archive_1.so b/tb/chip_top/csrc/_72002_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_72058_archive_1.so b/tb/chip_top/csrc/_72058_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_73324_archive_1.so b/tb/chip_top/csrc/_73324_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_75989_archive_1.so b/tb/chip_top/csrc/_75989_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_76123_archive_1.so b/tb/chip_top/csrc/_76123_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_76582_archive_1.so b/tb/chip_top/csrc/_76582_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_76857_archive_1.so b/tb/chip_top/csrc/_76857_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_77744_archive_1.so b/tb/chip_top/csrc/_77744_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_7785_archive_1.so b/tb/chip_top/csrc/_7785_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_78691_archive_1.so b/tb/chip_top/csrc/_78691_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_81914_archive_1.so b/tb/chip_top/csrc/_81914_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_82804_archive_1.so b/tb/chip_top/csrc/_82804_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_84034_archive_1.so b/tb/chip_top/csrc/_84034_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_84928_archive_1.so b/tb/chip_top/csrc/_84928_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_85369_archive_1.so b/tb/chip_top/csrc/_85369_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_85683_archive_1.so b/tb/chip_top/csrc/_85683_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_86438_archive_1.so b/tb/chip_top/csrc/_86438_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_86888_archive_1.so b/tb/chip_top/csrc/_86888_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_86959_archive_1.so b/tb/chip_top/csrc/_86959_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_87361_archive_1.so b/tb/chip_top/csrc/_87361_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_8759_archive_1.so b/tb/chip_top/csrc/_8759_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_88261_archive_1.so b/tb/chip_top/csrc/_88261_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_90723_archive_1.so b/tb/chip_top/csrc/_90723_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_90868_archive_1.so b/tb/chip_top/csrc/_90868_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_91006_archive_1.so b/tb/chip_top/csrc/_91006_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_91888_archive_1.so b/tb/chip_top/csrc/_91888_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_92476_archive_1.so b/tb/chip_top/csrc/_92476_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_93005_archive_1.so b/tb/chip_top/csrc/_93005_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_93061_archive_1.so b/tb/chip_top/csrc/_93061_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_93648_archive_1.so b/tb/chip_top/csrc/_93648_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_93651_archive_1.so b/tb/chip_top/csrc/_93651_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_93769_archive_1.so b/tb/chip_top/csrc/_93769_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_93943_archive_1.so b/tb/chip_top/csrc/_93943_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_94027_archive_1.so b/tb/chip_top/csrc/_94027_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_94639_archive_1.so b/tb/chip_top/csrc/_94639_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_94921_archive_1.so b/tb/chip_top/csrc/_94921_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_96081_archive_1.so b/tb/chip_top/csrc/_96081_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_96620_archive_1.so b/tb/chip_top/csrc/_96620_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_96958_archive_1.so b/tb/chip_top/csrc/_96958_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_97429_archive_1.so b/tb/chip_top/csrc/_97429_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_97436_archive_1.so b/tb/chip_top/csrc/_97436_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_99070_archive_1.so b/tb/chip_top/csrc/_99070_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_99277_archive_1.so b/tb/chip_top/csrc/_99277_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/_csrc0.so b/tb/chip_top/csrc/_csrc0.so new file mode 100644 index 0000000..22e0c5d Binary files /dev/null and b/tb/chip_top/csrc/_csrc0.so differ diff --git a/tb/chip_top/csrc/_prev_archive_1.so b/tb/chip_top/csrc/_prev_archive_1.so new file mode 100644 index 0000000..d35d1cb Binary files /dev/null and b/tb/chip_top/csrc/_prev_archive_1.so differ diff --git a/tb/chip_top/csrc/_prev_cginfo.json b/tb/chip_top/csrc/_prev_cginfo.json new file mode 100644 index 0000000..5054d45 --- /dev/null +++ b/tb/chip_top/csrc/_prev_cginfo.json @@ -0,0 +1,1058 @@ +{ + "cycles_program_begin": 7462872446170635, + "perf": [ + { + "stat": [ + "main", + "entry", + 0.010977029800415039, + 0.016655, + 0.01145, + 219296, + 219296, + 0.0, + 0.0, + 1717241854.044472, + 7462872446354541 + ], + "sub": [ + { + "stat": [ + "doParsingAndDesignResolution", + "entry", + 0.017261028289794922, + 0.018183999999999999, + 0.014975, + 275204, + 276004, + 0.0, + 0.0, + 1717241854.050756, + 7462872467879500 + ], + "sub": [] + }, + { + "stat": [ + "doParsingAndDesignResolution", + "exit", + 0.10923504829406738, + 0.103889, + 0.021388999999999998, + 284344, + 284992, + 0.0, + 0.0, + 1717241854.14273, + 7462872782893139 + ], + "sub": [] + }, + { + "stat": [ + "doPostDesignResolutionToVir2Vcs", + "entry", + 0.11282110214233398, + 0.106542, + 0.022322999999999999, + 284344, + 284992, + 0.0, + 0.0, + 1717241854.1463161, + 7462872795064430 + ], + "sub": [ + { + "stat": [ + "doUptoVir2VcsNoSepCleanup", + "entry", + 0.18264198303222656, + 0.173569, + 0.025241, + 289052, + 289056, + 0.0, + 0.0, + 1717241854.2161369, + 7462873034195204 + ], + "sub": [] + }, + { + "stat": [ + "doUptoVir2VcsNoSepCleanup", + "exit", + 0.5529780387878418, + 0.52385800000000005, + 0.036197, + 311972, + 311996, + 0.003277, + 0.006097, + 1717241854.586473, + 7462874302305312 + ], + "sub": [] + }, + { + "stat": [ + "doRadify_vir2vcsAll", + "entry", + 0.55304098129272461, + 0.52391799999999999, + 0.036200999999999997, + 311972, + 311996, + 0.003277, + 0.006097, + 1717241854.5865359, + 7462874302432380 + ], + "sub": [] + }, + { + "stat": [ + "doRadify_vir2vcsAll", + "exit", + 0.58184409141540527, + 0.55177500000000002, + 0.037186999999999998, + 311972, + 311996, + 0.003277, + 0.006097, + 1717241854.615339, + 7462874401123807 + ], + "sub": [] + } + ] + }, + { + "stat": [ + "doPostDesignResolutionToVir2Vcs", + "exit", + 0.58188009262084961, + 0.55181000000000002, + 0.037189, + 311972, + 311996, + 0.003277, + 0.006097, + 1717241854.615375, + 7462874401179875 + ], + "sub": [] + }, + { + "stat": [ + "doGAToPass2", + "entry", + 0.58189511299133301, + 0.55182299999999995, + 0.037190000000000001, + 311972, + 311996, + 0.003277, + 0.006097, + 1717241854.6153901, + 7462874401224182 + ], + "sub": [ + { + "stat": [ + "DoPass2", + "entry", + 0.59759902954101562, + 0.55469100000000005, + 0.038184999999999997, + 309768, + 311996, + 0.011494000000000001, + 0.010125, + 1717241854.631094, + 7462874455058996 + ], + "sub": [] + }, + { + "stat": [ + "DoPass2", + "exit", + 0.9338691234588623, + 0.87801399999999996, + 0.050229000000000003, + 311744, + 311996, + 0.011494000000000001, + 0.011682, + 1717241854.9673641, + 7462875606484477 + ], + "sub": [] + } + ] + }, + { + "stat": [ + "doGAToPass2", + "exit", + 0.93595004081726074, + 0.87913799999999998, + 0.051181999999999998, + 311744, + 311996, + 0.011494000000000001, + 0.011682, + 1717241854.969445, + 7462875613645140 + ], + "sub": [] + } + ] + }, + { + "stat": [ + "main", + "exit", + 0.93638396263122559, + 0.87954900000000003, + 0.051206000000000002, + 311736, + 311996, + 0.011494000000000001, + 0.011682, + 1717241854.9698789, + 7462875615080279 + ], + "sub": [] + } + ], + "stat": { + "cpu_cycles_end": 7462875615151155, + "ru_childs_cgstart": { + "ru_utime_sec": 0.011494000000000001, + "ru_stime_sec": 0.010125, + "ru_maxrss_kb": 44300, + "ru_minflt": 10104, + "ru_majflt": 0, + "ru_nvcsw": 25, + "ru_nivcsw": 22 + }, + "ru_self_cgstart": { + "ru_utime_sec": 0.55474999999999997, + "ru_stime_sec": 0.038189000000000001, + "ru_maxrss_kb": 101456, + "ru_minflt": 33437, + "ru_majflt": 0, + "ru_nvcsw": 31, + "ru_nivcsw": 19 + }, + "nQuads": 130654, + "Frontend(%)": 63.546237461759624, + "cpu_cycles_cgstart": 7462874455202015, + "nMops": 397956, + "mop/quad": 3.0458768962297365, + "totalObjSize": 424888, + "ru_self_end": { + "ru_utime_sec": 0.87958000000000003, + "ru_stime_sec": 0.051207999999999997, + "ru_maxrss_kb": 111512, + "ru_minflt": 40556, + "ru_majflt": 0, + "ru_nvcsw": 32, + "ru_nivcsw": 22 + }, + "CodeGen(%)": 36.453762538240376, + "ru_childs_end": { + "ru_utime_sec": 0.011494000000000001, + "ru_stime_sec": 0.011682, + "ru_maxrss_kb": 44684, + "ru_minflt": 10699, + "ru_majflt": 0, + "ru_nvcsw": 26, + "ru_nivcsw": 24 + }, + "outputSizePerQuad": 3.2520091233333845, + "quadSpeed": 402222.70110519341, + "cpu_cycles_total": 3168980520, + "mopSpeed": 1225120.8324354275, + "peak_mem_kb": 311996, + "realTime": 0.93643307685852051 + }, + "PrevCompiledModules": { + "qbmcu_datalatch": { + "MsCBG_d": { + "bytes": 12266, + "archive": "archive.27/_prev_archive_1.a", + "mod": "qbmcu_datalatch", + "mode": 4, + "checksum": 0, + "out": "MsCBG_d.o" + } + }, + "DUC4": { + "cwtAY_d": { + "bytes": 302374, + "archive": "archive.27/_prev_archive_1.a", + "mod": "DUC4", + "mode": 4, + "checksum": 0, + "out": "cwtAY_d.o" + } + }, + "tsdn28hpcpuhdb128x128m4mw_170a_Int_Array": { + "eFLuy_d": { + "bytes": 66736, + "archive": "archive.27/_prev_archive_1.a", + "mod": "tsdn28hpcpuhdb128x128m4mw_170a_Int_Array", + "mode": 4, + "checksum": 0, + "out": "eFLuy_d.o" + } + }, + "mcu_regfile": { + "HWLgR_d": { + "bytes": 221744, + "archive": "archive.27/_prev_archive_1.a", + "mod": "mcu_regfile", + "mode": 4, + "checksum": 0, + "out": "HWLgR_d.o" + } + }, + "...MASTER...": { + "amcQw_d": { + "bytes": 8962, + "mod": "...MASTER...", + "mode": 4, + "checksum": 0, + "out": "objs/amcQw_d.o" + } + }, + "tsdn28hpcpuhdb128x128m4mw_170a": { + "rShyv_d": { + "bytes": 297858, + "archive": "archive.27/_prev_archive_1.a", + "mod": "tsdn28hpcpuhdb128x128m4mw_170a", + "mode": 4, + "checksum": 0, + "out": "rShyv_d.o" + } + }, + "sram_if": { + "NABmh_d": { + "bytes": 8496, + "archive": "archive.27/_prev_archive_1.a", + "mod": "sram_if", + "mode": 4, + "checksum": 0, + "out": "NABmh_d.o" + } + }, + "channel_top": { + "xFWdC_d": { + "bytes": 466884, + "archive": "archive.27/_prev_archive_1.a", + "mod": "channel_top", + "mode": 4, + "checksum": 0, + "out": "xFWdC_d.o" + } + }, + "sirv_gnrl_dffl": { + "BM4bj_d": { + "bytes": 9566, + "archive": "archive.27/_prev_archive_1.a", + "mod": "sirv_gnrl_dffl", + "mode": 4, + "checksum": 0, + "out": "BM4bj_d.o" + } + }, + "DAC_DEM_4": { + "WqW9L_d": { + "bytes": 7116, + "archive": "archive.27/_prev_archive_1.a", + "mod": "DAC_DEM_4", + "mode": 4, + "checksum": 0, + "out": "WqW9L_d.o" + } + }, + "ctrl_regfile": { + "mLA3J_d": { + "bytes": 103968, + "archive": "archive.27/_prev_archive_1.a", + "mod": "ctrl_regfile", + "mode": 4, + "checksum": 0, + "out": "mLA3J_d.o" + } + }, + "DW01_addsub": { + "KysYq_d": { + "bytes": 18348, + "archive": "archive.27/_prev_archive_1.a", + "mod": "DW01_addsub", + "mode": 4, + "checksum": 0, + "out": "KysYq_d.o" + } + }, + "DAC_DEM": { + "brTVz_d": { + "bytes": 47090, + "archive": "archive.27/_prev_archive_1.a", + "mod": "DAC_DEM", + "mode": 4, + "checksum": 0, + "out": "brTVz_d.o" + } + }, + "spi_if": { + "IHYdB_d": { + "bytes": 11638, + "archive": "archive.27/_prev_archive_1.a", + "mod": "spi_if", + "mode": 4, + "checksum": 0, + "out": "IHYdB_d.o" + } + }, + "DW_mult_pipe_0000_0002": { + "SiiVi_d": { + "bytes": 37404, + "archive": "archive.27/_prev_archive_1.a", + "mod": "DW_mult_pipe_0000_0002", + "mode": 4, + "checksum": 0, + "out": "SiiVi_d.o" + } + }, + "modout_mux": { + "jEu9i_d": { + "bytes": 10566, + "archive": "archive.27/_prev_archive_1.a", + "mod": "modout_mux", + "mode": 4, + "checksum": 0, + "out": "jEu9i_d.o" + } + }, + "DUC_HB3": { + "Rdd8k_d": { + "bytes": 44058, + "archive": "archive.27/_prev_archive_1.a", + "mod": "DUC_HB3", + "mode": 4, + "checksum": 0, + "out": "Rdd8k_d.o" + } + }, + "DW_mult_pipe_0000_0000": { + "HNRiG_d": { + "bytes": 38412, + "archive": "archive.27/_prev_archive_1.a", + "mod": "DW_mult_pipe_0000_0000", + "mode": 4, + "checksum": 0, + "out": "HNRiG_d.o" + } + }, + "qbmcu_regfile_0000": { + "Hit7c_d": { + "bytes": 92428, + "archive": "archive.27/_prev_archive_1.a", + "mod": "qbmcu_regfile_0000", + "mode": 4, + "checksum": 0, + "out": "Hit7c_d.o" + } + }, + "DUC_HB2": { + "ksFw4_d": { + "bytes": 60820, + "archive": "archive.27/_prev_archive_1.a", + "mod": "DUC_HB2", + "mode": 4, + "checksum": 0, + "out": "ksFw4_d.o" + } + }, + "DUC_HB4": { + "zwWSN_d": { + "bytes": 39014, + "archive": "archive.27/_prev_archive_1.a", + "mod": "DUC_HB4", + "mode": 4, + "checksum": 0, + "out": "zwWSN_d.o" + } + }, + "sirv_gnrl_ltch": { + "UTi0b_d": { + "bytes": 9700, + "archive": "archive.27/_prev_archive_1.a", + "mod": "sirv_gnrl_ltch", + "mode": 4, + "checksum": 0, + "out": "UTi0b_d.o" + } + }, + "param_lut_0002": { + "nJN5E_d": { + "bytes": 19394, + "archive": "archive.27/_prev_archive_1.a", + "mod": "param_lut_0002", + "mode": 4, + "checksum": 0, + "out": "nJN5E_d.o" + } + }, + "qbmcu_busdecoder": { + "jAiwN_d": { + "bytes": 16692, + "archive": "archive.27/_prev_archive_1.a", + "mod": "qbmcu_busdecoder", + "mode": 4, + "checksum": 0, + "out": "jAiwN_d.o" + } + }, + "qbmcu": { + "xnbfb_d": { + "bytes": 365212, + "archive": "archive.27/_prev_archive_1.a", + "mod": "qbmcu", + "mode": 4, + "checksum": 0, + "out": "xnbfb_d.o" + } + }, + "system_regfile": { + "W3x1b_d": { + "bytes": 140240, + "archive": "archive.27/_prev_archive_1.a", + "mod": "system_regfile", + "mode": 4, + "checksum": 0, + "out": "W3x1b_d.o" + } + }, + "debug_top": { + "gNaPt_d": { + "bytes": 102354, + "archive": "archive.27/_prev_archive_1.a", + "mod": "debug_top", + "mode": 4, + "checksum": 0, + "out": "gNaPt_d.o" + } + }, + "std": { + "reYIK_d": { + "bytes": 43042, + "archive": "archive.27/_prev_archive_1.a", + "mod": "std", + "mode": 4, + "checksum": 0, + "out": "reYIK_d.o" + } + }, + "TB": { + "sH4Fc_d": { + "bytes": 266644, + "archive": "archive.27/_55152_archive_1.a", + "mod": "TB", + "out": "sH4Fc_d.o", + "mode": 4, + "checksum": 0 + } + }, + "thermo2binary_top": { + "N7Gsb_d": { + "bytes": 44956, + "archive": "archive.27/_prev_archive_1.a", + "mod": "thermo2binary_top", + "mode": 4, + "checksum": 0, + "out": "N7Gsb_d.o" + } + }, + "tsdn28hpcpuhdb4096x32m4mw_170a": { + "d6TPd_d": { + "bytes": 110112, + "archive": "archive.27/_prev_archive_1.a", + "mod": "tsdn28hpcpuhdb4096x32m4mw_170a", + "mode": 4, + "checksum": 0, + "out": "d6TPd_d.o" + } + }, + "tsdn28hpcpuhdb4096x32m4mw_170a_Int_Array": { + "ay4xz_d": { + "bytes": 66252, + "archive": "archive.27/_prev_archive_1.a", + "mod": "tsdn28hpcpuhdb4096x32m4mw_170a_Int_Array", + "mode": 4, + "checksum": 0, + "out": "ay4xz_d.o" + } + }, + "dac_regfile": { + "LR0zI_d": { + "bytes": 108876, + "archive": "archive.27/_prev_archive_1.a", + "mod": "dac_regfile", + "mode": 4, + "checksum": 0, + "out": "LR0zI_d.o" + } + }, + "sram_if_0000": { + "nJgqZ_d": { + "bytes": 8690, + "archive": "archive.27/_prev_archive_1.a", + "mod": "sram_if_0000", + "mode": 4, + "checksum": 0, + "out": "nJgqZ_d.o" + } + }, + "xyz_chip_top": { + "VHUBa_d": { + "bytes": 655492, + "archive": "archive.27/_prev_archive_1.a", + "mod": "xyz_chip_top", + "mode": 4, + "checksum": 0, + "out": "VHUBa_d.o" + } + }, + "DAC_DEM_16": { + "gcyA4_d": { + "bytes": 8402, + "archive": "archive.27/_prev_archive_1.a", + "mod": "DAC_DEM_16", + "mode": 4, + "checksum": 0, + "out": "gcyA4_d.o" + } + }, + "PH2AMP": { + "iYIEc_d": { + "bytes": 157906, + "archive": "archive.27/_prev_archive_1.a", + "mod": "PH2AMP", + "mode": 4, + "checksum": 0, + "out": "iYIEc_d.o" + } + }, + "dacif": { + "SMgga_d": { + "bytes": 62042, + "archive": "archive.27/_prev_archive_1.a", + "mod": "dacif", + "mode": 4, + "checksum": 0, + "out": "SMgga_d.o" + } + }, + "tsdn28hpcpuhdb64x32m4mw_170a_Int_Array": { + "JweIx_d": { + "bytes": 65620, + "archive": "archive.27/_prev_archive_1.a", + "mod": "tsdn28hpcpuhdb64x32m4mw_170a_Int_Array", + "mode": 4, + "checksum": 0, + "out": "JweIx_d.o" + } + }, + "xy_dsp": { + "U33JQ_d": { + "bytes": 380142, + "archive": "archive.27/_prev_archive_1.a", + "mod": "xy_dsp", + "mode": 4, + "checksum": 0, + "out": "U33JQ_d.o" + } + }, + "rst_gen_unit": { + "anuMN_d": { + "bytes": 21774, + "archive": "archive.27/_prev_archive_1.a", + "mod": "rst_gen_unit", + "mode": 4, + "checksum": 0, + "out": "anuMN_d.o" + } + }, + "_vcs_unit__3598111382": { + "QyjH7_d": { + "bytes": 86582, + "archive": "archive.27/_prev_archive_1.a", + "mod": "_vcs_unit__3598111382", + "mode": 4, + "checksum": 0, + "out": "QyjH7_d.o" + } + }, + "spi_slave": { + "eAsJz_d": { + "bytes": 308508, + "archive": "archive.27/_prev_archive_1.a", + "mod": "spi_slave", + "mode": 4, + "checksum": 0, + "out": "eAsJz_d.o" + } + } + }, + "LVLData": [ + "SIM" + ], + "MlibObjs": {}, + "NameTable": { + "_vcs_unit__3598111382": [ + "_vcs_unit__3598111382", + "QyjH7", + "module", + 1 + ], + "DW01_addsub": [ + "DW01_addsub", + "KysYq", + "module", + 41 + ], + "DAC_DEM": [ + "DAC_DEM", + "brTVz", + "module", + 34 + ], + "ctrl_regfile": [ + "ctrl_regfile", + "mLA3J", + "module", + 5 + ], + "sram_if_0000": [ + "sram_if_0000", + "nJgqZ", + "module", + 4 + ], + "system_regfile": [ + "system_regfile", + "W3x1b", + "module", + 25 + ], + "debug_top": [ + "debug_top", + "gNaPt", + "module", + 11 + ], + "std": [ + "std", + "reYIK", + "module", + 2 + ], + "sram_if": [ + "sram_if", + "NABmh", + "module", + 3 + ], + "channel_top": [ + "channel_top", + "xFWdC", + "module", + 26 + ], + "DAC_DEM_4": [ + "DAC_DEM_4", + "WqW9L", + "module", + 36 + ], + "sirv_gnrl_dffl": [ + "sirv_gnrl_dffl", + "BM4bj", + "module", + 8 + ], + "modout_mux": [ + "modout_mux", + "jEu9i", + "module", + 7 + ], + "param_lut_0002": [ + "param_lut_0002", + "nJN5E", + "module", + 6 + ], + "sirv_gnrl_ltch": [ + "sirv_gnrl_ltch", + "UTi0b", + "module", + 9 + ], + "DUC_HB4": [ + "DUC_HB4", + "zwWSN", + "module", + 32 + ], + "rst_gen_unit": [ + "rst_gen_unit", + "anuMN", + "module", + 23 + ], + "dac_regfile": [ + "dac_regfile", + "LR0zI", + "module", + 10 + ], + "mcu_regfile": [ + "mcu_regfile", + "HWLgR", + "module", + 18 + ], + "...MASTER...": [ + "SIM", + "amcQw", + "module", + 44 + ], + "tsdn28hpcpuhdb128x128m4mw_170a": [ + "tsdn28hpcpuhdb128x128m4mw_170a", + "rShyv", + "module", + 12 + ], + "DUC4": [ + "DUC4", + "cwtAY", + "module", + 33 + ], + "tsdn28hpcpuhdb128x128m4mw_170a_Int_Array": [ + "tsdn28hpcpuhdb128x128m4mw_170a_Int_Array", + "eFLuy", + "module", + 13 + ], + "tsdn28hpcpuhdb4096x32m4mw_170a_Int_Array": [ + "tsdn28hpcpuhdb4096x32m4mw_170a_Int_Array", + "ay4xz", + "module", + 15 + ], + "tsdn28hpcpuhdb4096x32m4mw_170a": [ + "tsdn28hpcpuhdb4096x32m4mw_170a", + "d6TPd", + "module", + 14 + ], + "tsdn28hpcpuhdb64x32m4mw_170a_Int_Array": [ + "tsdn28hpcpuhdb64x32m4mw_170a_Int_Array", + "JweIx", + "module", + 16 + ], + "xy_dsp": [ + "xy_dsp", + "U33JQ", + "module", + 29 + ], + "PH2AMP": [ + "PH2AMP", + "iYIEc", + "module", + 17 + ], + "qbmcu_busdecoder": [ + "qbmcu_busdecoder", + "jAiwN", + "module", + 19 + ], + "qbmcu": [ + "qbmcu", + "xnbfb", + "module", + 20 + ], + "qbmcu_datalatch": [ + "qbmcu_datalatch", + "MsCBG", + "module", + 21 + ], + "DUC_HB2": [ + "DUC_HB2", + "ksFw4", + "module", + 30 + ], + "qbmcu_regfile_0000": [ + "qbmcu_regfile_0000", + "Hit7c", + "module", + 22 + ], + "spi_slave": [ + "spi_slave", + "eAsJz", + "module", + 24 + ], + "xyz_chip_top": [ + "xyz_chip_top", + "VHUBa", + "module", + 27 + ], + "dacif": [ + "dacif", + "SMgga", + "module", + 28 + ], + "DW_mult_pipe_0000_0000": [ + "DW_mult_pipe_0000_0000", + "HNRiG", + "module", + 38 + ], + "DUC_HB3": [ + "DUC_HB3", + "Rdd8k", + "module", + 31 + ], + "DAC_DEM_16": [ + "DAC_DEM_16", + "gcyA4", + "module", + 35 + ], + "TB": [ + "TB", + "sH4Fc", + "module", + 37 + ], + "DW_mult_pipe_0000_0002": [ + "DW_mult_pipe_0000_0002", + "SiiVi", + "module", + 39 + ], + "spi_if": [ + "spi_if", + "IHYdB", + "module", + 42 + ], + "thermo2binary_top": [ + "thermo2binary_top", + "N7Gsb", + "module", + 43 + ] + }, + "PEModules": [], + "CompileStrategy": "fullobj", + "Misc": { + "master_pid": 55152, + "vcs_version": "O-2018.09-SP2_Full64", + "vcs_build_date": "Build Date = Feb 28 2019 22:34:30", + "csrc": "csrc", + "csrc_abs": "/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/chip_top/csrc", + "VCS_HOME": "/home/synopsys/vcs/O-2018.09-SP2", + "hostname": "IC_EDA", + "cwd": "/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/chip_top", + "daidir": "simv.daidir", + "archive_dir": "archive.27", + "daidir_abs": "/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/chip_top/simv.daidir", + "default_output_dir": "csrc" + }, + "SIMBData": { + "out": "amcQwB.o", + "bytes": 158244, + "text": 0, + "archive": "archive.27/_55152_archive_1.a" + }, + "cpu_cycles_pass2_start": 7462874455078675, + "CurCompileUdps": {}, + "incremental": "on", + "CurCompileModules": [ + "...MASTER...", + "_vcs_unit__3598111382", + "std", + "sram_if", + "sram_if_0000", + "ctrl_regfile", + "param_lut_0002", + "modout_mux", + "sirv_gnrl_dffl", + "sirv_gnrl_ltch", + "dac_regfile", + "debug_top", + "tsdn28hpcpuhdb128x128m4mw_170a", + "tsdn28hpcpuhdb128x128m4mw_170a_Int_Array", + "tsdn28hpcpuhdb4096x32m4mw_170a", + "tsdn28hpcpuhdb4096x32m4mw_170a_Int_Array", + "tsdn28hpcpuhdb64x32m4mw_170a_Int_Array", + "PH2AMP", + "mcu_regfile", + "qbmcu_busdecoder", + "qbmcu", + "qbmcu_datalatch", + "qbmcu_regfile_0000", + "rst_gen_unit", + "spi_slave", + "system_regfile", + "channel_top", + "xyz_chip_top", + "dacif", + "xy_dsp", + "DUC_HB2", + "DUC_HB3", + "DUC_HB4", + "DUC4", + "DAC_DEM", + "DAC_DEM_16", + "DAC_DEM_4", + "TB", + "TB", + "DW_mult_pipe_0000_0000", + "DW_mult_pipe_0000_0002", + "DW01_addsub", + "spi_if", + "thermo2binary_top" + ], + "CompileProcesses": [ + "cgproc.55152.json" + ], + "rlimit": { + "data": -1, + "stack": -1 + }, + "CompileStatus": "Successful" +} \ No newline at end of file diff --git a/tb/chip_top/csrc/_vcs_pli_stub_.c b/tb/chip_top/csrc/_vcs_pli_stub_.c new file mode 100644 index 0000000..e4d8eaa --- /dev/null +++ b/tb/chip_top/csrc/_vcs_pli_stub_.c @@ -0,0 +1,964 @@ +#ifndef _GNU_SOURCE +#define _GNU_SOURCE +#endif +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +extern void* VCS_dlsymLookup(const char *); +extern void vcsMsgReportNoSource1(const char *, const char*); + +/* PLI routine: $fsdbDumpvars:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbDumpvars +#define __VCS_PLI_STUB_novas_call_fsdbDumpvars +extern void novas_call_fsdbDumpvars(int data, int reason); +#pragma weak novas_call_fsdbDumpvars +void novas_call_fsdbDumpvars(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbDumpvars"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbDumpvars"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbDumpvars"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbDumpvars)(int data, int reason) = novas_call_fsdbDumpvars; +#endif /* __VCS_PLI_STUB_novas_call_fsdbDumpvars */ + +/* PLI routine: $fsdbDumpvars:misc */ +#ifndef __VCS_PLI_STUB_novas_misc +#define __VCS_PLI_STUB_novas_misc +extern void novas_misc(int data, int reason, int iparam ); +#pragma weak novas_misc +void novas_misc(int data, int reason, int iparam ) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason, int iparam ) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason, int iparam )) dlsym(RTLD_NEXT, "novas_misc"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason, int iparam )) VCS_dlsymLookup("novas_misc"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason, iparam ); + } +} +void (*__vcs_pli_dummy_reference_novas_misc)(int data, int reason, int iparam ) = novas_misc; +#endif /* __VCS_PLI_STUB_novas_misc */ + +/* PLI routine: $fsdbDumpvarsByFile:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbDumpvarsByFile +#define __VCS_PLI_STUB_novas_call_fsdbDumpvarsByFile +extern void novas_call_fsdbDumpvarsByFile(int data, int reason); +#pragma weak novas_call_fsdbDumpvarsByFile +void novas_call_fsdbDumpvarsByFile(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbDumpvarsByFile"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbDumpvarsByFile"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbDumpvarsByFile"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbDumpvarsByFile)(int data, int reason) = novas_call_fsdbDumpvarsByFile; +#endif /* __VCS_PLI_STUB_novas_call_fsdbDumpvarsByFile */ + +/* PLI routine: $fsdbAddRuntimeSignal:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbAddRuntimeSignal +#define __VCS_PLI_STUB_novas_call_fsdbAddRuntimeSignal +extern void novas_call_fsdbAddRuntimeSignal(int data, int reason); +#pragma weak novas_call_fsdbAddRuntimeSignal +void novas_call_fsdbAddRuntimeSignal(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbAddRuntimeSignal"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbAddRuntimeSignal"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbAddRuntimeSignal"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbAddRuntimeSignal)(int data, int reason) = novas_call_fsdbAddRuntimeSignal; +#endif /* __VCS_PLI_STUB_novas_call_fsdbAddRuntimeSignal */ + +/* PLI routine: $sps_create_transaction_stream:call */ +#ifndef __VCS_PLI_STUB_novas_call_sps_create_transaction_stream +#define __VCS_PLI_STUB_novas_call_sps_create_transaction_stream +extern void novas_call_sps_create_transaction_stream(int data, int reason); +#pragma weak novas_call_sps_create_transaction_stream +void novas_call_sps_create_transaction_stream(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_create_transaction_stream"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_create_transaction_stream"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_create_transaction_stream"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_sps_create_transaction_stream)(int data, int reason) = novas_call_sps_create_transaction_stream; +#endif /* __VCS_PLI_STUB_novas_call_sps_create_transaction_stream */ + +/* PLI routine: $sps_begin_transaction:call */ +#ifndef __VCS_PLI_STUB_novas_call_sps_begin_transaction +#define __VCS_PLI_STUB_novas_call_sps_begin_transaction +extern void novas_call_sps_begin_transaction(int data, int reason); +#pragma weak novas_call_sps_begin_transaction +void novas_call_sps_begin_transaction(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_begin_transaction"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_begin_transaction"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_begin_transaction"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_sps_begin_transaction)(int data, int reason) = novas_call_sps_begin_transaction; +#endif /* __VCS_PLI_STUB_novas_call_sps_begin_transaction */ + +/* PLI routine: $sps_end_transaction:call */ +#ifndef __VCS_PLI_STUB_novas_call_sps_end_transaction +#define __VCS_PLI_STUB_novas_call_sps_end_transaction +extern void novas_call_sps_end_transaction(int data, int reason); +#pragma weak novas_call_sps_end_transaction +void novas_call_sps_end_transaction(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_end_transaction"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_end_transaction"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_end_transaction"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_sps_end_transaction)(int data, int reason) = novas_call_sps_end_transaction; +#endif /* __VCS_PLI_STUB_novas_call_sps_end_transaction */ + +/* PLI routine: $sps_free_transaction:call */ +#ifndef __VCS_PLI_STUB_novas_call_sps_free_transaction +#define __VCS_PLI_STUB_novas_call_sps_free_transaction +extern void novas_call_sps_free_transaction(int data, int reason); +#pragma weak novas_call_sps_free_transaction +void novas_call_sps_free_transaction(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_free_transaction"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_free_transaction"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_free_transaction"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_sps_free_transaction)(int data, int reason) = novas_call_sps_free_transaction; +#endif /* __VCS_PLI_STUB_novas_call_sps_free_transaction */ + +/* PLI routine: $sps_add_attribute:call */ +#ifndef __VCS_PLI_STUB_novas_call_sps_add_attribute +#define __VCS_PLI_STUB_novas_call_sps_add_attribute +extern void novas_call_sps_add_attribute(int data, int reason); +#pragma weak novas_call_sps_add_attribute +void novas_call_sps_add_attribute(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_add_attribute"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_add_attribute"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_add_attribute"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_sps_add_attribute)(int data, int reason) = novas_call_sps_add_attribute; +#endif /* __VCS_PLI_STUB_novas_call_sps_add_attribute */ + +/* PLI routine: $sps_update_label:call */ +#ifndef __VCS_PLI_STUB_novas_call_sps_update_label +#define __VCS_PLI_STUB_novas_call_sps_update_label +extern void novas_call_sps_update_label(int data, int reason); +#pragma weak novas_call_sps_update_label +void novas_call_sps_update_label(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_update_label"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_update_label"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_update_label"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_sps_update_label)(int data, int reason) = novas_call_sps_update_label; +#endif /* __VCS_PLI_STUB_novas_call_sps_update_label */ + +/* PLI routine: $sps_add_relation:call */ +#ifndef __VCS_PLI_STUB_novas_call_sps_add_relation +#define __VCS_PLI_STUB_novas_call_sps_add_relation +extern void novas_call_sps_add_relation(int data, int reason); +#pragma weak novas_call_sps_add_relation +void novas_call_sps_add_relation(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_add_relation"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_add_relation"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_add_relation"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_sps_add_relation)(int data, int reason) = novas_call_sps_add_relation; +#endif /* __VCS_PLI_STUB_novas_call_sps_add_relation */ + +/* PLI routine: $fsdbWhatif:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbWhatif +#define __VCS_PLI_STUB_novas_call_fsdbWhatif +extern void novas_call_fsdbWhatif(int data, int reason); +#pragma weak novas_call_fsdbWhatif +void novas_call_fsdbWhatif(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbWhatif"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbWhatif"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbWhatif"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbWhatif)(int data, int reason) = novas_call_fsdbWhatif; +#endif /* __VCS_PLI_STUB_novas_call_fsdbWhatif */ + +/* PLI routine: $paa_init:call */ +#ifndef __VCS_PLI_STUB_novas_call_paa_init +#define __VCS_PLI_STUB_novas_call_paa_init +extern void novas_call_paa_init(int data, int reason); +#pragma weak novas_call_paa_init +void novas_call_paa_init(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_paa_init"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_paa_init"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_paa_init"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_paa_init)(int data, int reason) = novas_call_paa_init; +#endif /* __VCS_PLI_STUB_novas_call_paa_init */ + +/* PLI routine: $paa_sync:call */ +#ifndef __VCS_PLI_STUB_novas_call_paa_sync +#define __VCS_PLI_STUB_novas_call_paa_sync +extern void novas_call_paa_sync(int data, int reason); +#pragma weak novas_call_paa_sync +void novas_call_paa_sync(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_paa_sync"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_paa_sync"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_paa_sync"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_paa_sync)(int data, int reason) = novas_call_paa_sync; +#endif /* __VCS_PLI_STUB_novas_call_paa_sync */ + +/* PLI routine: $fsdbDumpClassMethod:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbDumpClassMethod +#define __VCS_PLI_STUB_novas_call_fsdbDumpClassMethod +extern void novas_call_fsdbDumpClassMethod(int data, int reason); +#pragma weak novas_call_fsdbDumpClassMethod +void novas_call_fsdbDumpClassMethod(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbDumpClassMethod"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbDumpClassMethod"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbDumpClassMethod"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbDumpClassMethod)(int data, int reason) = novas_call_fsdbDumpClassMethod; +#endif /* __VCS_PLI_STUB_novas_call_fsdbDumpClassMethod */ + +/* PLI routine: $fsdbSuppressClassMethod:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbSuppressClassMethod +#define __VCS_PLI_STUB_novas_call_fsdbSuppressClassMethod +extern void novas_call_fsdbSuppressClassMethod(int data, int reason); +#pragma weak novas_call_fsdbSuppressClassMethod +void novas_call_fsdbSuppressClassMethod(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbSuppressClassMethod"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbSuppressClassMethod"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbSuppressClassMethod"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbSuppressClassMethod)(int data, int reason) = novas_call_fsdbSuppressClassMethod; +#endif /* __VCS_PLI_STUB_novas_call_fsdbSuppressClassMethod */ + +/* PLI routine: $fsdbSuppressClassProp:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbSuppressClassProp +#define __VCS_PLI_STUB_novas_call_fsdbSuppressClassProp +extern void novas_call_fsdbSuppressClassProp(int data, int reason); +#pragma weak novas_call_fsdbSuppressClassProp +void novas_call_fsdbSuppressClassProp(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbSuppressClassProp"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbSuppressClassProp"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbSuppressClassProp"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbSuppressClassProp)(int data, int reason) = novas_call_fsdbSuppressClassProp; +#endif /* __VCS_PLI_STUB_novas_call_fsdbSuppressClassProp */ + +/* PLI routine: $fsdbDumpMDAByFile:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbDumpMDAByFile +#define __VCS_PLI_STUB_novas_call_fsdbDumpMDAByFile +extern void novas_call_fsdbDumpMDAByFile(int data, int reason); +#pragma weak novas_call_fsdbDumpMDAByFile +void novas_call_fsdbDumpMDAByFile(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbDumpMDAByFile"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbDumpMDAByFile"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbDumpMDAByFile"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbDumpMDAByFile)(int data, int reason) = novas_call_fsdbDumpMDAByFile; +#endif /* __VCS_PLI_STUB_novas_call_fsdbDumpMDAByFile */ + +/* PLI routine: $fsdbTrans_create_stream_begin:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_create_stream_begin +#define __VCS_PLI_STUB_novas_call_fsdbEvent_create_stream_begin +extern void novas_call_fsdbEvent_create_stream_begin(int data, int reason); +#pragma weak novas_call_fsdbEvent_create_stream_begin +void novas_call_fsdbEvent_create_stream_begin(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_create_stream_begin"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_create_stream_begin"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_create_stream_begin"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_create_stream_begin)(int data, int reason) = novas_call_fsdbEvent_create_stream_begin; +#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_create_stream_begin */ + +/* PLI routine: $fsdbTrans_define_attribute:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_add_stream_attribute +#define __VCS_PLI_STUB_novas_call_fsdbEvent_add_stream_attribute +extern void novas_call_fsdbEvent_add_stream_attribute(int data, int reason); +#pragma weak novas_call_fsdbEvent_add_stream_attribute +void novas_call_fsdbEvent_add_stream_attribute(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_add_stream_attribute"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_add_stream_attribute"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_add_stream_attribute"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_add_stream_attribute)(int data, int reason) = novas_call_fsdbEvent_add_stream_attribute; +#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_add_stream_attribute */ + +/* PLI routine: $fsdbTrans_create_stream_end:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_create_stream_end +#define __VCS_PLI_STUB_novas_call_fsdbEvent_create_stream_end +extern void novas_call_fsdbEvent_create_stream_end(int data, int reason); +#pragma weak novas_call_fsdbEvent_create_stream_end +void novas_call_fsdbEvent_create_stream_end(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_create_stream_end"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_create_stream_end"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_create_stream_end"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_create_stream_end)(int data, int reason) = novas_call_fsdbEvent_create_stream_end; +#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_create_stream_end */ + +/* PLI routine: $fsdbTrans_begin:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_begin +#define __VCS_PLI_STUB_novas_call_fsdbEvent_begin +extern void novas_call_fsdbEvent_begin(int data, int reason); +#pragma weak novas_call_fsdbEvent_begin +void novas_call_fsdbEvent_begin(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_begin"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_begin"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_begin"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_begin)(int data, int reason) = novas_call_fsdbEvent_begin; +#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_begin */ + +/* PLI routine: $fsdbTrans_set_label:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_set_label +#define __VCS_PLI_STUB_novas_call_fsdbEvent_set_label +extern void novas_call_fsdbEvent_set_label(int data, int reason); +#pragma weak novas_call_fsdbEvent_set_label +void novas_call_fsdbEvent_set_label(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_set_label"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_set_label"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_set_label"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_set_label)(int data, int reason) = novas_call_fsdbEvent_set_label; +#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_set_label */ + +/* PLI routine: $fsdbTrans_add_attribute:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_add_attribute +#define __VCS_PLI_STUB_novas_call_fsdbEvent_add_attribute +extern void novas_call_fsdbEvent_add_attribute(int data, int reason); +#pragma weak novas_call_fsdbEvent_add_attribute +void novas_call_fsdbEvent_add_attribute(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_add_attribute"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_add_attribute"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_add_attribute"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_add_attribute)(int data, int reason) = novas_call_fsdbEvent_add_attribute; +#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_add_attribute */ + +/* PLI routine: $fsdbTrans_add_tag:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_add_tag +#define __VCS_PLI_STUB_novas_call_fsdbEvent_add_tag +extern void novas_call_fsdbEvent_add_tag(int data, int reason); +#pragma weak novas_call_fsdbEvent_add_tag +void novas_call_fsdbEvent_add_tag(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_add_tag"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_add_tag"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_add_tag"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_add_tag)(int data, int reason) = novas_call_fsdbEvent_add_tag; +#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_add_tag */ + +/* PLI routine: $fsdbTrans_end:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_end +#define __VCS_PLI_STUB_novas_call_fsdbEvent_end +extern void novas_call_fsdbEvent_end(int data, int reason); +#pragma weak novas_call_fsdbEvent_end +void novas_call_fsdbEvent_end(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_end"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_end"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_end"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_end)(int data, int reason) = novas_call_fsdbEvent_end; +#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_end */ + +/* PLI routine: $fsdbTrans_add_relation:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_add_relation +#define __VCS_PLI_STUB_novas_call_fsdbEvent_add_relation +extern void novas_call_fsdbEvent_add_relation(int data, int reason); +#pragma weak novas_call_fsdbEvent_add_relation +void novas_call_fsdbEvent_add_relation(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_add_relation"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_add_relation"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_add_relation"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_add_relation)(int data, int reason) = novas_call_fsdbEvent_add_relation; +#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_add_relation */ + +/* PLI routine: $fsdbTrans_get_error_code:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_get_error_code +#define __VCS_PLI_STUB_novas_call_fsdbEvent_get_error_code +extern void novas_call_fsdbEvent_get_error_code(int data, int reason); +#pragma weak novas_call_fsdbEvent_get_error_code +void novas_call_fsdbEvent_get_error_code(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_get_error_code"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_get_error_code"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_get_error_code"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_get_error_code)(int data, int reason) = novas_call_fsdbEvent_get_error_code; +#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_get_error_code */ + +/* PLI routine: $fsdbTrans_add_stream_attribute:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbTrans_add_stream_attribute +#define __VCS_PLI_STUB_novas_call_fsdbTrans_add_stream_attribute +extern void novas_call_fsdbTrans_add_stream_attribute(int data, int reason); +#pragma weak novas_call_fsdbTrans_add_stream_attribute +void novas_call_fsdbTrans_add_stream_attribute(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbTrans_add_stream_attribute"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbTrans_add_stream_attribute"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbTrans_add_stream_attribute"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbTrans_add_stream_attribute)(int data, int reason) = novas_call_fsdbTrans_add_stream_attribute; +#endif /* __VCS_PLI_STUB_novas_call_fsdbTrans_add_stream_attribute */ + +/* PLI routine: $fsdbTrans_add_scope_attribute:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbTrans_add_scope_attribute +#define __VCS_PLI_STUB_novas_call_fsdbTrans_add_scope_attribute +extern void novas_call_fsdbTrans_add_scope_attribute(int data, int reason); +#pragma weak novas_call_fsdbTrans_add_scope_attribute +void novas_call_fsdbTrans_add_scope_attribute(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbTrans_add_scope_attribute"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbTrans_add_scope_attribute"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbTrans_add_scope_attribute"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbTrans_add_scope_attribute)(int data, int reason) = novas_call_fsdbTrans_add_scope_attribute; +#endif /* __VCS_PLI_STUB_novas_call_fsdbTrans_add_scope_attribute */ + +/* PLI routine: $sps_interactive:call */ +#ifndef __VCS_PLI_STUB_novas_call_sps_interactive +#define __VCS_PLI_STUB_novas_call_sps_interactive +extern void novas_call_sps_interactive(int data, int reason); +#pragma weak novas_call_sps_interactive +void novas_call_sps_interactive(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_interactive"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_interactive"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_interactive"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_sps_interactive)(int data, int reason) = novas_call_sps_interactive; +#endif /* __VCS_PLI_STUB_novas_call_sps_interactive */ + +/* PLI routine: $sps_test:call */ +#ifndef __VCS_PLI_STUB_novas_call_sps_test +#define __VCS_PLI_STUB_novas_call_sps_test +extern void novas_call_sps_test(int data, int reason); +#pragma weak novas_call_sps_test +void novas_call_sps_test(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_test"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_test"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_test"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_sps_test)(int data, int reason) = novas_call_sps_test; +#endif /* __VCS_PLI_STUB_novas_call_sps_test */ + +/* PLI routine: $fsdbDumpClassObject:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbDumpClassObject +#define __VCS_PLI_STUB_novas_call_fsdbDumpClassObject +extern void novas_call_fsdbDumpClassObject(int data, int reason); +#pragma weak novas_call_fsdbDumpClassObject +void novas_call_fsdbDumpClassObject(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbDumpClassObject"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbDumpClassObject"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbDumpClassObject"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbDumpClassObject)(int data, int reason) = novas_call_fsdbDumpClassObject; +#endif /* __VCS_PLI_STUB_novas_call_fsdbDumpClassObject */ + +/* PLI routine: $fsdbDumpClassObjectByFile:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbDumpClassObjectByFile +#define __VCS_PLI_STUB_novas_call_fsdbDumpClassObjectByFile +extern void novas_call_fsdbDumpClassObjectByFile(int data, int reason); +#pragma weak novas_call_fsdbDumpClassObjectByFile +void novas_call_fsdbDumpClassObjectByFile(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbDumpClassObjectByFile"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbDumpClassObjectByFile"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbDumpClassObjectByFile"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbDumpClassObjectByFile)(int data, int reason) = novas_call_fsdbDumpClassObjectByFile; +#endif /* __VCS_PLI_STUB_novas_call_fsdbDumpClassObjectByFile */ + +/* PLI routine: $ridbDump:call */ +#ifndef __VCS_PLI_STUB_novas_call_ridbDump +#define __VCS_PLI_STUB_novas_call_ridbDump +extern void novas_call_ridbDump(int data, int reason); +#pragma weak novas_call_ridbDump +void novas_call_ridbDump(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_ridbDump"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_ridbDump"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_ridbDump"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_ridbDump)(int data, int reason) = novas_call_ridbDump; +#endif /* __VCS_PLI_STUB_novas_call_ridbDump */ + +/* PLI routine: $sps_flush_file:call */ +#ifndef __VCS_PLI_STUB_novas_call_sps_flush_file +#define __VCS_PLI_STUB_novas_call_sps_flush_file +extern void novas_call_sps_flush_file(int data, int reason); +#pragma weak novas_call_sps_flush_file +void novas_call_sps_flush_file(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_flush_file"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_flush_file"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_flush_file"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_sps_flush_file)(int data, int reason) = novas_call_sps_flush_file; +#endif /* __VCS_PLI_STUB_novas_call_sps_flush_file */ + +/* PLI routine: $fsdbDumpSingle:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbDumpSingle +#define __VCS_PLI_STUB_novas_call_fsdbDumpSingle +extern void novas_call_fsdbDumpSingle(int data, int reason); +#pragma weak novas_call_fsdbDumpSingle +void novas_call_fsdbDumpSingle(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbDumpSingle"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbDumpSingle"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbDumpSingle"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbDumpSingle)(int data, int reason) = novas_call_fsdbDumpSingle; +#endif /* __VCS_PLI_STUB_novas_call_fsdbDumpSingle */ + +/* PLI routine: $fsdbDumpIO:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbDumpIO +#define __VCS_PLI_STUB_novas_call_fsdbDumpIO +extern void novas_call_fsdbDumpIO(int data, int reason); +#pragma weak novas_call_fsdbDumpIO +void novas_call_fsdbDumpIO(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbDumpIO"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbDumpIO"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbDumpIO"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbDumpIO)(int data, int reason) = novas_call_fsdbDumpIO; +#endif /* __VCS_PLI_STUB_novas_call_fsdbDumpIO */ + +#ifdef __cplusplus +} +#endif diff --git a/tb/chip_top/csrc/_vcs_pli_stub_.o b/tb/chip_top/csrc/_vcs_pli_stub_.o new file mode 100644 index 0000000..7927935 Binary files /dev/null and b/tb/chip_top/csrc/_vcs_pli_stub_.o differ diff --git a/tb/chip_top/csrc/archive.162/_3127_archive_1.a b/tb/chip_top/csrc/archive.162/_3127_archive_1.a new file mode 100644 index 0000000..f69d634 Binary files /dev/null and b/tb/chip_top/csrc/archive.162/_3127_archive_1.a differ diff --git a/tb/chip_top/csrc/archive.162/_3127_archive_1.a.info b/tb/chip_top/csrc/archive.162/_3127_archive_1.a.info new file mode 100644 index 0000000..81f9480 --- /dev/null +++ b/tb/chip_top/csrc/archive.162/_3127_archive_1.a.info @@ -0,0 +1,42 @@ +D1hM1_d.o +nJgqZ_d.o +nJN5E_d.o +BM4bj_d.o +UTi0b_d.o +LR0zI_d.o +gNaPt_d.o +rShyv_d.o +eFLuy_d.o +d6TPd_d.o +ay4xz_d.o +Sg3ri_d.o +e36VC_d.o +JweIx_d.o +iYIEc_d.o +HWLgR_d.o +jAiwN_d.o +xnbfb_d.o +MsCBG_d.o +Hit7c_d.o +anuMN_d.o +eAsJz_d.o +W3x1b_d.o +xFWdC_d.o +rTmJG_d.o +SMgga_d.o +U33JQ_d.o +ksFw4_d.o +Rdd8k_d.o +zwWSN_d.o +cwtAY_d.o +rLaFI_d.o +zpIk1_d.o +sH4Fc_d.o +HNRiG_d.o +SiiVi_d.o +ZpmS6_d.o +KysYq_d.o +hwIug_d.o +UIt6b_d.o +IHYdB_d.o +amcQwB.o diff --git a/tb/chip_top/csrc/archive.162/_prev_archive_1.a b/tb/chip_top/csrc/archive.162/_prev_archive_1.a new file mode 100644 index 0000000..e1bc451 Binary files /dev/null and b/tb/chip_top/csrc/archive.162/_prev_archive_1.a differ diff --git a/tb/chip_top/csrc/archive.162/_prev_archive_1.a.info b/tb/chip_top/csrc/archive.162/_prev_archive_1.a.info new file mode 100644 index 0000000..ae9799a --- /dev/null +++ b/tb/chip_top/csrc/archive.162/_prev_archive_1.a.info @@ -0,0 +1,4 @@ +jEu9i_d.o +NABmh_d.o +reYIK_d.o +mLA3J_d.o diff --git a/tb/chip_top/csrc/archive.28/_58486_archive_1.a b/tb/chip_top/csrc/archive.28/_58486_archive_1.a new file mode 100644 index 0000000..43cd7db Binary files /dev/null and b/tb/chip_top/csrc/archive.28/_58486_archive_1.a differ diff --git a/tb/chip_top/csrc/archive.28/_58486_archive_1.a.info b/tb/chip_top/csrc/archive.28/_58486_archive_1.a.info new file mode 100644 index 0000000..d229ed4 --- /dev/null +++ b/tb/chip_top/csrc/archive.28/_58486_archive_1.a.info @@ -0,0 +1,15 @@ +QyjH7_d.o +eAsJz_d.o +xFWdC_d.o +VHUBa_d.o +SMgga_d.o +U33JQ_d.o +ksFw4_d.o +Rdd8k_d.o +zwWSN_d.o +cwtAY_d.o +brTVz_d.o +gcyA4_d.o +WqW9L_d.o +sH4Fc_d.o +amcQwB.o diff --git a/tb/chip_top/csrc/archive.28/_prev_archive_1.a b/tb/chip_top/csrc/archive.28/_prev_archive_1.a new file mode 100644 index 0000000..e47e75c Binary files /dev/null and b/tb/chip_top/csrc/archive.28/_prev_archive_1.a differ diff --git a/tb/chip_top/csrc/archive.28/_prev_archive_1.a.info b/tb/chip_top/csrc/archive.28/_prev_archive_1.a.info new file mode 100644 index 0000000..cff0973 --- /dev/null +++ b/tb/chip_top/csrc/archive.28/_prev_archive_1.a.info @@ -0,0 +1,28 @@ +IHYdB_d.o +MsCBG_d.o +jEu9i_d.o +mLA3J_d.o +rShyv_d.o +HNRiG_d.o +NABmh_d.o +SiiVi_d.o +jAiwN_d.o +N7Gsb_d.o +nJN5E_d.o +KysYq_d.o +gNaPt_d.o +reYIK_d.o +iYIEc_d.o +UTi0b_d.o +Hit7c_d.o +HWLgR_d.o +W3x1b_d.o +d6TPd_d.o +eFLuy_d.o +ay4xz_d.o +LR0zI_d.o +nJgqZ_d.o +xnbfb_d.o +BM4bj_d.o +JweIx_d.o +anuMN_d.o diff --git a/tb/chip_top/csrc/cgincr.sdb b/tb/chip_top/csrc/cgincr.sdb new file mode 100644 index 0000000..aa5b53b Binary files /dev/null and b/tb/chip_top/csrc/cgincr.sdb differ diff --git a/tb/chip_top/csrc/cginfo.json b/tb/chip_top/csrc/cginfo.json new file mode 100644 index 0000000..9759752 --- /dev/null +++ b/tb/chip_top/csrc/cginfo.json @@ -0,0 +1,1071 @@ +{ + "PEModules": [], + "CompileProcesses": [ + "cgproc.58486.json" + ], + "CompileStrategy": "fullobj", + "SIMBData": { + "out": "amcQwB.o", + "bytes": 159704, + "text": 0, + "archive": "archive.28/_58486_archive_1.a" + }, + "cycles_program_begin": 7945477152822173, + "perf": [ + { + "stat": [ + "main", + "entry", + 0.016614913940429688, + 0.023085000000000001, + 0.017062999999999998, + 219296, + 219296, + 0.0, + 0.0, + 1717383081.0146279, + 7945477153086489 + ], + "sub": [ + { + "stat": [ + "doParsingAndDesignResolution", + "entry", + 0.02528691291809082, + 0.025464000000000001, + 0.021389999999999999, + 275204, + 276004, + 0.0, + 0.0, + 1717383081.0232999, + 7945477182525211 + ], + "sub": [] + }, + { + "stat": [ + "doParsingAndDesignResolution", + "exit", + 0.13479804992675781, + 0.108998, + 0.045998999999999998, + 284344, + 284992, + 0.0, + 0.0, + 1717383081.1328111, + 7945477555672517 + ], + "sub": [] + }, + { + "stat": [ + "doPostDesignResolutionToVir2Vcs", + "entry", + 0.13848996162414551, + 0.11176899999999999, + 0.046903, + 284344, + 284992, + 0.0, + 0.0, + 1717383081.136503, + 7945477568228898 + ], + "sub": [ + { + "stat": [ + "doUptoVir2VcsNoSepCleanup", + "entry", + 0.21096086502075195, + 0.179864, + 0.051045, + 289052, + 289056, + 0.0, + 0.0, + 1717383081.2089739, + 7945477815131856 + ], + "sub": [] + }, + { + "stat": [ + "doUptoVir2VcsNoSepCleanup", + "exit", + 0.59868288040161133, + 0.52772300000000005, + 0.078809000000000004, + 311976, + 312000, + 0.0022070000000000002, + 0.0081989999999999997, + 1717383081.5966959, + 7945479135982948 + ], + "sub": [] + }, + { + "stat": [ + "doRadify_vir2vcsAll", + "entry", + 0.59874391555786133, + 0.52777600000000002, + 0.078816999999999998, + 311976, + 312000, + 0.0022070000000000002, + 0.0081989999999999997, + 1717383081.5967569, + 7945479136109550 + ], + "sub": [] + }, + { + "stat": [ + "doRadify_vir2vcsAll", + "exit", + 0.62996006011962891, + 0.55187200000000003, + 0.085823999999999998, + 311976, + 312000, + 0.0022070000000000002, + 0.0081989999999999997, + 1717383081.6279731, + 7945479242535609 + ], + "sub": [] + } + ] + }, + { + "stat": [ + "doPostDesignResolutionToVir2Vcs", + "exit", + 0.63000202178955078, + 0.55190899999999998, + 0.085830000000000004, + 311976, + 312000, + 0.0022070000000000002, + 0.0081989999999999997, + 1717383081.628015, + 7945479242595904 + ], + "sub": [] + }, + { + "stat": [ + "doGAToPass2", + "entry", + 0.63001704216003418, + 0.55192200000000002, + 0.085832000000000006, + 311976, + 312000, + 0.0022070000000000002, + 0.0081989999999999997, + 1717383081.6280301, + 7945479242639807 + ], + "sub": [ + { + "stat": [ + "DoPass2", + "entry", + 0.64835190773010254, + 0.55519300000000005, + 0.086873000000000006, + 309772, + 312000, + 0.0060819999999999997, + 0.018713, + 1717383081.6463649, + 7945479305168851 + ], + "sub": [] + }, + { + "stat": [ + "DoPass2", + "exit", + 1.2781100273132324, + 1.1562319999999999, + 0.111786, + 311748, + 312000, + 0.0060819999999999997, + 0.020500000000000001, + 1717383082.276123, + 7945481450539865 + ], + "sub": [] + } + ] + }, + { + "stat": [ + "doGAToPass2", + "exit", + 1.2804079055786133, + 1.157543, + 0.11276, + 311748, + 312000, + 0.0060819999999999997, + 0.020500000000000001, + 1717383082.2784209, + 7945481458427090 + ], + "sub": [] + } + ] + }, + { + "stat": [ + "main", + "exit", + 1.2809219360351562, + 1.157543, + 0.113272, + 311740, + 312000, + 0.0060819999999999997, + 0.020500000000000001, + 1717383082.278935, + 7945481460109426 + ], + "sub": [] + } + ], + "MlibObjs": {}, + "PrevCompiledModules": { + "spi_if": { + "IHYdB_d": { + "bytes": 11638, + "out": "IHYdB_d.o", + "mod": "spi_if", + "mode": 4, + "checksum": 0, + "archive": "archive.28/_prev_archive_1.a" + } + }, + "qbmcu_datalatch": { + "MsCBG_d": { + "bytes": 12266, + "out": "MsCBG_d.o", + "mod": "qbmcu_datalatch", + "mode": 4, + "checksum": 0, + "archive": "archive.28/_prev_archive_1.a" + } + }, + "modout_mux": { + "jEu9i_d": { + "bytes": 10566, + "out": "jEu9i_d.o", + "mod": "modout_mux", + "mode": 4, + "checksum": 0, + "archive": "archive.28/_prev_archive_1.a" + } + }, + "DUC_HB3": { + "Rdd8k_d": { + "bytes": 44058, + "out": "Rdd8k_d.o", + "mod": "DUC_HB3", + "mode": 4, + "checksum": 0, + "archive": "archive.28/_58486_archive_1.a" + } + }, + "channel_top": { + "xFWdC_d": { + "bytes": 466884, + "out": "xFWdC_d.o", + "mod": "channel_top", + "mode": 4, + "checksum": 0, + "archive": "archive.28/_58486_archive_1.a" + } + }, + "DUC4": { + "cwtAY_d": { + "bytes": 302374, + "out": "cwtAY_d.o", + "mod": "DUC4", + "mode": 4, + "checksum": 0, + "archive": "archive.28/_58486_archive_1.a" + } + }, + "DAC_DEM_16": { + "gcyA4_d": { + "bytes": 8402, + "out": "gcyA4_d.o", + "mod": "DAC_DEM_16", + "mode": 4, + "checksum": 0, + "archive": "archive.28/_58486_archive_1.a" + } + }, + "ctrl_regfile": { + "mLA3J_d": { + "bytes": 103968, + "out": "mLA3J_d.o", + "mod": "ctrl_regfile", + "mode": 4, + "checksum": 0, + "archive": "archive.28/_prev_archive_1.a" + } + }, + "tsdn28hpcpuhdb128x128m4mw_170a": { + "rShyv_d": { + "bytes": 297858, + "out": "rShyv_d.o", + "mod": "tsdn28hpcpuhdb128x128m4mw_170a", + "mode": 4, + "checksum": 0, + "archive": "archive.28/_prev_archive_1.a" + } + }, + "DAC_DEM_4": { + "WqW9L_d": { + "bytes": 7116, + "out": "WqW9L_d.o", + "mod": "DAC_DEM_4", + "mode": 4, + "checksum": 0, + "archive": "archive.28/_58486_archive_1.a" + } + }, + "xyz_chip_top": { + "VHUBa_d": { + "bytes": 655492, + "out": "VHUBa_d.o", + "mod": "xyz_chip_top", + "mode": 4, + "checksum": 0, + "archive": "archive.28/_58486_archive_1.a" + } + }, + "DAC_DEM": { + "brTVz_d": { + "bytes": 47090, + "out": "brTVz_d.o", + "mod": "DAC_DEM", + "mode": 4, + "checksum": 0, + "archive": "archive.28/_58486_archive_1.a" + } + }, + "DW_mult_pipe_0000_0000": { + "HNRiG_d": { + "bytes": 38412, + "out": "HNRiG_d.o", + "mod": "DW_mult_pipe_0000_0000", + "mode": 4, + "checksum": 0, + "archive": "archive.28/_prev_archive_1.a" + } + }, + "sram_if": { + "NABmh_d": { + "bytes": 8496, + "out": "NABmh_d.o", + "mod": "sram_if", + "mode": 4, + "checksum": 0, + "archive": "archive.28/_prev_archive_1.a" + } + }, + "DUC_HB2": { + "ksFw4_d": { + "bytes": 60820, + "out": "ksFw4_d.o", + "mod": "DUC_HB2", + "mode": 4, + "checksum": 0, + "archive": "archive.28/_58486_archive_1.a" + } + }, + "DW_mult_pipe_0000_0002": { + "SiiVi_d": { + "bytes": 37404, + "out": "SiiVi_d.o", + "mod": "DW_mult_pipe_0000_0002", + "mode": 4, + "checksum": 0, + "archive": "archive.28/_prev_archive_1.a" + } + }, + "qbmcu_busdecoder": { + "jAiwN_d": { + "bytes": 16692, + "out": "jAiwN_d.o", + "mod": "qbmcu_busdecoder", + "mode": 4, + "checksum": 0, + "archive": "archive.28/_prev_archive_1.a" + } + }, + "thermo2binary_top": { + "N7Gsb_d": { + "bytes": 44956, + "out": "N7Gsb_d.o", + "mod": "thermo2binary_top", + "mode": 4, + "checksum": 0, + "archive": "archive.28/_prev_archive_1.a" + } + }, + "DUC_HB4": { + "zwWSN_d": { + "bytes": 39014, + "out": "zwWSN_d.o", + "mod": "DUC_HB4", + "mode": 4, + "checksum": 0, + "archive": "archive.28/_58486_archive_1.a" + } + }, + "TB": { + "sH4Fc_d": { + "bytes": 266644, + "out": "sH4Fc_d.o", + "mod": "TB", + "mode": 4, + "checksum": 0, + "archive": "archive.28/_58486_archive_1.a" + } + }, + "param_lut_0002": { + "nJN5E_d": { + "bytes": 19394, + "out": "nJN5E_d.o", + "mod": "param_lut_0002", + "mode": 4, + "checksum": 0, + "archive": "archive.28/_prev_archive_1.a" + } + }, + "DW01_addsub": { + "KysYq_d": { + "bytes": 18348, + "out": "KysYq_d.o", + "mod": "DW01_addsub", + "mode": 4, + "checksum": 0, + "archive": "archive.28/_prev_archive_1.a" + } + }, + "debug_top": { + "gNaPt_d": { + "bytes": 102354, + "out": "gNaPt_d.o", + "mod": "debug_top", + "mode": 4, + "checksum": 0, + "archive": "archive.28/_prev_archive_1.a" + } + }, + "std": { + "reYIK_d": { + "bytes": 43042, + "out": "reYIK_d.o", + "mod": "std", + "mode": 4, + "checksum": 0, + "archive": "archive.28/_prev_archive_1.a" + } + }, + "dacif": { + "SMgga_d": { + "bytes": 62042, + "out": "SMgga_d.o", + "mod": "dacif", + "mode": 4, + "checksum": 0, + "archive": "archive.28/_58486_archive_1.a" + } + }, + "PH2AMP": { + "iYIEc_d": { + "bytes": 157906, + "out": "iYIEc_d.o", + "mod": "PH2AMP", + "mode": 4, + "checksum": 0, + "archive": "archive.28/_prev_archive_1.a" + } + }, + "sirv_gnrl_ltch": { + "UTi0b_d": { + "bytes": 9700, + "out": "UTi0b_d.o", + "mod": "sirv_gnrl_ltch", + "mode": 4, + "checksum": 0, + "archive": "archive.28/_prev_archive_1.a" + } + }, + "qbmcu_regfile_0000": { + "Hit7c_d": { + "bytes": 92428, + "out": "Hit7c_d.o", + "mod": "qbmcu_regfile_0000", + "mode": 4, + "checksum": 0, + "archive": "archive.28/_prev_archive_1.a" + } + }, + "mcu_regfile": { + "HWLgR_d": { + "bytes": 221744, + "out": "HWLgR_d.o", + "mod": "mcu_regfile", + "mode": 4, + "checksum": 0, + "archive": "archive.28/_prev_archive_1.a" + } + }, + "system_regfile": { + "W3x1b_d": { + "bytes": 140240, + "out": "W3x1b_d.o", + "mod": "system_regfile", + "mode": 4, + "checksum": 0, + "archive": "archive.28/_prev_archive_1.a" + } + }, + "_vcs_unit__3598111382": { + "QyjH7_d": { + "bytes": 86582, + "out": "QyjH7_d.o", + "mod": "_vcs_unit__3598111382", + "mode": 4, + "checksum": 0, + "archive": "archive.28/_58486_archive_1.a" + } + }, + "tsdn28hpcpuhdb4096x32m4mw_170a": { + "d6TPd_d": { + "bytes": 110112, + "out": "d6TPd_d.o", + "mod": "tsdn28hpcpuhdb4096x32m4mw_170a", + "mode": 4, + "checksum": 0, + "archive": "archive.28/_prev_archive_1.a" + } + }, + "tsdn28hpcpuhdb128x128m4mw_170a_Int_Array": { + "eFLuy_d": { + "bytes": 66736, + "out": "eFLuy_d.o", + "mod": "tsdn28hpcpuhdb128x128m4mw_170a_Int_Array", + "mode": 4, + "checksum": 0, + "archive": "archive.28/_prev_archive_1.a" + } + }, + "tsdn28hpcpuhdb4096x32m4mw_170a_Int_Array": { + "ay4xz_d": { + "bytes": 66252, + "out": "ay4xz_d.o", + "mod": "tsdn28hpcpuhdb4096x32m4mw_170a_Int_Array", + "mode": 4, + "checksum": 0, + "archive": "archive.28/_prev_archive_1.a" + } + }, + "dac_regfile": { + "LR0zI_d": { + "bytes": 108876, + "out": "LR0zI_d.o", + "mod": "dac_regfile", + "mode": 4, + "checksum": 0, + "archive": "archive.28/_prev_archive_1.a" + } + }, + "sram_if_0000": { + "nJgqZ_d": { + "bytes": 8690, + "out": "nJgqZ_d.o", + "mod": "sram_if_0000", + "mode": 4, + "checksum": 0, + "archive": "archive.28/_prev_archive_1.a" + } + }, + "qbmcu": { + "xnbfb_d": { + "bytes": 365212, + "out": "xnbfb_d.o", + "mod": "qbmcu", + "mode": 4, + "checksum": 0, + "archive": "archive.28/_prev_archive_1.a" + } + }, + "sirv_gnrl_dffl": { + "BM4bj_d": { + "bytes": 9566, + "out": "BM4bj_d.o", + "mod": "sirv_gnrl_dffl", + "mode": 4, + "checksum": 0, + "archive": "archive.28/_prev_archive_1.a" + } + }, + "tsdn28hpcpuhdb64x32m4mw_170a_Int_Array": { + "JweIx_d": { + "bytes": 65620, + "out": "JweIx_d.o", + "mod": "tsdn28hpcpuhdb64x32m4mw_170a_Int_Array", + "mode": 4, + "checksum": 0, + "archive": "archive.28/_prev_archive_1.a" + } + }, + "...MASTER...": { + "amcQw_d": { + "bytes": 8962, + "out": "objs/amcQw_d.o", + "mod": "...MASTER...", + "mode": 4, + "checksum": 0 + } + }, + "xy_dsp": { + "U33JQ_d": { + "bytes": 380142, + "out": "U33JQ_d.o", + "mod": "xy_dsp", + "mode": 4, + "checksum": 0, + "archive": "archive.28/_58486_archive_1.a" + } + }, + "rst_gen_unit": { + "anuMN_d": { + "bytes": 21774, + "out": "anuMN_d.o", + "mod": "rst_gen_unit", + "mode": 4, + "checksum": 0, + "archive": "archive.28/_prev_archive_1.a" + } + }, + "spi_slave": { + "eAsJz_d": { + "bytes": 308508, + "out": "eAsJz_d.o", + "mod": "spi_slave", + "mode": 4, + "checksum": 0, + "archive": "archive.28/_58486_archive_1.a" + } + } + }, + "cpu_cycles_pass2_start": 7945479305189390, + "stat": { + "ru_self_cgstart": { + "ru_utime_sec": 0.55524700000000005, + "ru_stime_sec": 0.086882000000000001, + "ru_majflt": 0, + "ru_maxrss_kb": 97268, + "ru_minflt": 36643, + "ru_nvcsw": 30, + "ru_nivcsw": 23 + }, + "peak_mem_kb": 312000, + "ru_childs_cgstart": { + "ru_utime_sec": 0.0060819999999999997, + "ru_stime_sec": 0.018713, + "ru_majflt": 0, + "ru_maxrss_kb": 40128, + "ru_minflt": 10104, + "ru_nvcsw": 25, + "ru_nivcsw": 22 + }, + "CodeGen(%)": 51.760317971855187, + "ru_childs_end": { + "ru_utime_sec": 0.0060819999999999997, + "ru_stime_sec": 0.020500000000000001, + "ru_majflt": 0, + "ru_maxrss_kb": 40548, + "ru_minflt": 10699, + "ru_nvcsw": 26, + "ru_nivcsw": 24 + }, + "totalObjSize": 2894608, + "cpu_cycles_cgstart": 7945479305314010, + "ru_self_end": { + "ru_utime_sec": 1.157543, + "ru_stime_sec": 0.11330999999999999, + "ru_majflt": 0, + "ru_maxrss_kb": 109924, + "ru_minflt": 45276, + "ru_nvcsw": 31, + "ru_nivcsw": 27 + }, + "mop/quad": 3.0603915662650603, + "realTime": 1.2809770107269287, + "nMops": 568988, + "nQuads": 185920, + "cpu_cycles_end": 7945481460192227, + "cpu_cycles_total": 4307370054, + "mopSpeed": 944698.28788502689, + "quadSpeed": 308685.43041959446, + "outputSizePerQuad": 15.569104991394148, + "Frontend(%)": 48.239682028144813 + }, + "NameTable": { + "tsdn28hpcpuhdb4096x32m4mw_170a": [ + "tsdn28hpcpuhdb4096x32m4mw_170a", + "d6TPd", + "module", + 14 + ], + "tsdn28hpcpuhdb128x128m4mw_170a_Int_Array": [ + "tsdn28hpcpuhdb128x128m4mw_170a_Int_Array", + "eFLuy", + "module", + 13 + ], + "_vcs_unit__3598111382": [ + "_vcs_unit__3598111382", + "QyjH7", + "module", + 1 + ], + "std": [ + "std", + "reYIK", + "module", + 2 + ], + "tsdn28hpcpuhdb64x32m4mw_170a_Int_Array": [ + "tsdn28hpcpuhdb64x32m4mw_170a_Int_Array", + "JweIx", + "module", + 16 + ], + "tsdn28hpcpuhdb4096x32m4mw_170a_Int_Array": [ + "tsdn28hpcpuhdb4096x32m4mw_170a_Int_Array", + "ay4xz", + "module", + 15 + ], + "sram_if": [ + "sram_if", + "NABmh", + "module", + 3 + ], + "DUC_HB2": [ + "DUC_HB2", + "ksFw4", + "module", + 30 + ], + "modout_mux": [ + "modout_mux", + "jEu9i", + "module", + 7 + ], + "spi_if": [ + "spi_if", + "IHYdB", + "module", + 42 + ], + "qbmcu_datalatch": [ + "qbmcu_datalatch", + "MsCBG", + "module", + 21 + ], + "sirv_gnrl_dffl": [ + "sirv_gnrl_dffl", + "BM4bj", + "module", + 8 + ], + "sram_if_0000": [ + "sram_if_0000", + "nJgqZ", + "module", + 4 + ], + "DAC_DEM_4": [ + "DAC_DEM_4", + "WqW9L", + "module", + 36 + ], + "tsdn28hpcpuhdb128x128m4mw_170a": [ + "tsdn28hpcpuhdb128x128m4mw_170a", + "rShyv", + "module", + 12 + ], + "ctrl_regfile": [ + "ctrl_regfile", + "mLA3J", + "module", + 5 + ], + "xyz_chip_top": [ + "xyz_chip_top", + "VHUBa", + "module", + 27 + ], + "param_lut_0002": [ + "param_lut_0002", + "nJN5E", + "module", + 6 + ], + "sirv_gnrl_ltch": [ + "sirv_gnrl_ltch", + "UTi0b", + "module", + 9 + ], + "PH2AMP": [ + "PH2AMP", + "iYIEc", + "module", + 17 + ], + "dacif": [ + "dacif", + "SMgga", + "module", + 28 + ], + "qbmcu_regfile_0000": [ + "qbmcu_regfile_0000", + "Hit7c", + "module", + 22 + ], + "dac_regfile": [ + "dac_regfile", + "LR0zI", + "module", + 10 + ], + "debug_top": [ + "debug_top", + "gNaPt", + "module", + 11 + ], + "mcu_regfile": [ + "mcu_regfile", + "HWLgR", + "module", + 18 + ], + "TB": [ + "TB", + "sH4Fc", + "module", + 37 + ], + "DUC_HB4": [ + "DUC_HB4", + "zwWSN", + "module", + 32 + ], + "thermo2binary_top": [ + "thermo2binary_top", + "N7Gsb", + "module", + 43 + ], + "qbmcu_busdecoder": [ + "qbmcu_busdecoder", + "jAiwN", + "module", + 19 + ], + "xy_dsp": [ + "xy_dsp", + "U33JQ", + "module", + 29 + ], + "qbmcu": [ + "qbmcu", + "xnbfb", + "module", + 20 + ], + "rst_gen_unit": [ + "rst_gen_unit", + "anuMN", + "module", + 23 + ], + "spi_slave": [ + "spi_slave", + "eAsJz", + "module", + 24 + ], + "system_regfile": [ + "system_regfile", + "W3x1b", + "module", + 25 + ], + "channel_top": [ + "channel_top", + "xFWdC", + "module", + 26 + ], + "DUC_HB3": [ + "DUC_HB3", + "Rdd8k", + "module", + 31 + ], + "DUC4": [ + "DUC4", + "cwtAY", + "module", + 33 + ], + "DAC_DEM": [ + "DAC_DEM", + "brTVz", + "module", + 34 + ], + "DAC_DEM_16": [ + "DAC_DEM_16", + "gcyA4", + "module", + 35 + ], + "DW_mult_pipe_0000_0000": [ + "DW_mult_pipe_0000_0000", + "HNRiG", + "module", + 38 + ], + "DW_mult_pipe_0000_0002": [ + "DW_mult_pipe_0000_0002", + "SiiVi", + "module", + 39 + ], + "DW01_addsub": [ + "DW01_addsub", + "KysYq", + "module", + 41 + ], + "...MASTER...": [ + "SIM", + "amcQw", + "module", + 44 + ] + }, + "incremental": "on", + "LVLData": [ + "SIM" + ], + "Misc": { + "archive_dir": "archive.28", + "vcs_version": "O-2018.09-SP2_Full64", + "master_pid": 58486, + "vcs_build_date": "Build Date = Feb 28 2019 22:34:30", + "VCS_HOME": "/home/synopsys/vcs/O-2018.09-SP2", + "default_output_dir": "csrc", + "csrc_abs": "/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/chip_top/csrc", + "hostname": "IC_EDA", + "cwd": "/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/chip_top", + "csrc": "csrc", + "daidir": "simv.daidir", + "daidir_abs": "/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/chip_top/simv.daidir" + }, + "CurCompileUdps": {}, + "CurCompileModules": [ + "...MASTER...", + "_vcs_unit__3598111382", + "_vcs_unit__3598111382", + "std", + "sram_if", + "sram_if_0000", + "ctrl_regfile", + "param_lut_0002", + "modout_mux", + "sirv_gnrl_dffl", + "sirv_gnrl_ltch", + "dac_regfile", + "debug_top", + "tsdn28hpcpuhdb128x128m4mw_170a", + "tsdn28hpcpuhdb128x128m4mw_170a_Int_Array", + "tsdn28hpcpuhdb4096x32m4mw_170a", + "tsdn28hpcpuhdb4096x32m4mw_170a_Int_Array", + "tsdn28hpcpuhdb64x32m4mw_170a_Int_Array", + "PH2AMP", + "mcu_regfile", + "qbmcu_busdecoder", + "qbmcu", + "qbmcu_datalatch", + "qbmcu_regfile_0000", + "rst_gen_unit", + "spi_slave", + "spi_slave", + "system_regfile", + "channel_top", + "channel_top", + "xyz_chip_top", + "xyz_chip_top", + "dacif", + "dacif", + "xy_dsp", + "xy_dsp", + "DUC_HB2", + "DUC_HB2", + "DUC_HB3", + "DUC_HB3", + "DUC_HB4", + "DUC_HB4", + "DUC4", + "DUC4", + "DAC_DEM", + "DAC_DEM", + "DAC_DEM_16", + "DAC_DEM_16", + "DAC_DEM_4", + "DAC_DEM_4", + "TB", + "TB", + "DW_mult_pipe_0000_0000", + "DW_mult_pipe_0000_0002", + "DW01_addsub", + "spi_if", + "thermo2binary_top" + ], + "rlimit": { + "data": -1, + "stack": -1 + }, + "CompileStatus": "Successful" +} \ No newline at end of file diff --git a/tb/chip_top/csrc/cgproc.3127.json b/tb/chip_top/csrc/cgproc.3127.json new file mode 100644 index 0000000..1fec2d8 --- /dev/null +++ b/tb/chip_top/csrc/cgproc.3127.json @@ -0,0 +1,1999 @@ +{ + "Modules": { + "PH2AMP": { + "start_perf": [ + 0.90703201293945312, + 0.82548100000000002, + 0.071779999999999997, + 312516, + 313024, + 1716628561.086571, + 5366956876836506 + ], + "child_modules": { + "DW_mult_pipe_0000_0000": 2 + }, + "Compiled": "Yes", + "nRouts": 435, + "nMops": 22628, + "nQuads": 8772, + "Compiled Times": 163, + "end_perf": [ + 0.93802213668823242, + 0.85540799999999995, + 0.072778999999999996, + 312516, + 313024, + 5366956982605397, + 184683593729, + 0 + ] + }, + "DUC_HB3": { + "start_perf": [ + 1.3760230541229248, + 1.2775129999999999, + 0.087760000000000005, + 312516, + 313024, + 1716628561.555562, + 5366958476397445 + ], + "child_modules": {}, + "Compiled": "Yes", + "nRouts": 107, + "nMops": 7360, + "nQuads": 1886, + "Compiled Times": 163, + "end_perf": [ + 1.3855690956115723, + 1.287039, + 0.087760000000000005, + 312516, + 313024, + 5366958508993029, + 339302416385, + 0 + ] + }, + "param_lut_0002": { + "start_perf": [ + 0.69298505783081055, + 0.61887300000000001, + 0.064777000000000001, + 312516, + 313024, + 1716628560.872524, + 5366956146798401 + ], + "child_modules": {}, + "Compiled": "Yes", + "nRouts": 46, + "nMops": 2028, + "nQuads": 530, + "Compiled Times": 163, + "end_perf": [ + 0.69748711585998535, + 0.62331700000000001, + 0.064824000000000007, + 312516, + 313024, + 5366956162201501, + 34359738369, + 0 + ] + }, + "DUC4": { + "start_perf": [ + 1.3940439224243164, + 1.2944979999999999, + 0.088759000000000005, + 312516, + 313024, + 1716628561.5735829, + 5366958537862536 + ], + "child_modules": { + "DUC_HB2": 2, + "DUC_HB3": 4, + "DUC_HB4": 8 + }, + "Compiled": "Yes", + "nRouts": 1018, + "nMops": 55264, + "nQuads": 18936, + "Compiled Times": 163, + "end_perf": [ + 1.4506981372833252, + 1.351035, + 0.088759000000000005, + 312516, + 313024, + 5366958731132881, + 356482285569, + 0 + ] + }, + "...MASTER...": { + "start_perf": [ + 0.65459203720092773, + 0.59146500000000002, + 0.055485, + 310536, + 313024, + 1716628560.834131, + 5366956015863029 + ], + "child_modules": { + "DW01_addsub": 1, + "_vcs_unit__504089786": 1, + "std": 1, + "TB": 1, + "tsdn28hpcpuhdb4096x32m4mw_170a": 1, + "sirv_gnrl_ltch": 1, + "sirv_gnrl_dffl": 1 + }, + "end_perf": [ + 0.6593470573425293, + 0.59146500000000002, + 0.058626999999999999, + 311532, + 313024, + 5366956032101465, + 0, + 0 + ], + "nRouts": 8, + "nMops": 14, + "nQuads": 8 + }, + "spi_slave": { + "start_perf": [ + 1.0679941177368164, + 0.97912699999999997, + 0.078768000000000005, + 312516, + 313024, + 1716628561.2475331, + 5366957425818309 + ], + "child_modules": {}, + "Compiled": "Yes", + "nRouts": 986, + "nMops": 25923, + "nQuads": 9699, + "Compiled Times": 163, + "end_perf": [ + 1.1163139343261719, + 1.027323, + 0.078794000000000003, + 312516, + 313024, + 5366957590662374, + 287762808833, + 0 + ] + }, + "dac_regfile": { + "start_perf": [ + 0.70262694358825684, + 0.62743599999999999, + 0.065835000000000005, + 312516, + 313024, + 1716628560.8821659, + 5366956179680442 + ], + "child_modules": {}, + "Compiled": "Yes", + "nRouts": 381, + "nMops": 18486, + "nQuads": 6198, + "Compiled Times": 163, + "end_perf": [ + 0.7235100269317627, + 0.64738200000000001, + 0.066729999999999998, + 312516, + 313024, + 5366956250987475, + 77309411329, + 0 + ] + }, + "modout_mux": { + "start_perf": [ + 0.69752097129821777, + 0.62334800000000001, + 0.064827999999999997, + 312516, + 313024, + 1716628560.8770599, + 5366956162268336 + ], + "child_modules": {}, + "Compiled": "Yes", + "nRouts": 23, + "nMops": 314, + "nQuads": 93, + "Compiled Times": 80, + "end_perf": [ + 0.69831013679504395, + 0.62334800000000001, + 0.065615000000000007, + 312516, + 313024, + 5366956164998383, + 38654705665, + 0 + ] + }, + "tsdn28hpcpuhdb128x128m4mw_170a_Int_Array": { + "start_perf": [ + 0.80225300788879395, + 0.72389499999999996, + 0.0688, + 312516, + 313024, + 1716628560.981792, + 5366956519469571 + ], + "significant_routs": [ + [ + 23, + "R_VCSgd_eFLuy_17", + 12801016, + 15741, + 1919 + ] + ], + "child_modules": {}, + "Compiled": "Yes", + "Compiled Times": 49, + "nQuads": 2502, + "nMops": 8246, + "end_perf": [ + 0.8163909912109375, + 0.73799199999999998, + 0.068811999999999998, + 312516, + 313024, + 5366956567732453, + 107374182401, + 0 + ], + "nRouts": 61 + }, + "_vcs_unit__504089786": { + "start_perf": [ + 0.65942001342773438, + 0.59146500000000002, + 0.058701000000000003, + 311532, + 313024, + 1716628560.838959, + 5366956032321372 + ], + "child_modules": {}, + "Compiled": "Yes", + "Compiled Times": 76, + "nQuads": 429, + "nMops": 1692, + "end_perf": [ + 0.66795897483825684, + 0.598885, + 0.059788000000000001, + 312516, + 313024, + 5366956061477408, + 4294967297, + 0 + ], + "svclass": [ + "BinaryDataReader", + 2977, + 297, + 4, + 4, + 4294978061, + "spi_data_send", + 4400, + 447, + 20, + 3, + 4294978101, + "spi_reg", + 7139, + 901, + 22, + 3, + 4294978129 + ], + "nRouts": 51 + }, + "std": { + "start_perf": [ + 0.66798996925354004, + 0.59891399999999995, + 0.059790999999999997, + 312516, + 313024, + 1716628560.8475289, + 5366956061549437 + ], + "child_modules": {}, + "Compiled": "Yes", + "Compiled Times": 163, + "nQuads": 218, + "nMops": 528, + "end_perf": [ + 0.66906595230102539, + 0.59898399999999996, + 0.060795000000000002, + 312516, + 313024, + 5366956065242891, + 8589934594, + 0 + ], + "svclass": [ + "$vcs_nba_dyn_obj", + 0, + 35, + 2, + 2, + 0, + "sigprop$$", + 0, + 35, + 2, + 2, + 0, + "process", + 0, + 200, + 8, + 8, + 0, + "event", + 0, + 34, + 2, + 2, + 0, + "mailbox", + 0, + 140, + 9, + 9, + 0, + "semaphore", + 0, + 84, + 5, + 5, + 0 + ], + "nRouts": 33 + }, + "tsdn28hpcpuhdb4096x32m4mw_170a": { + "start_perf": [ + 0.8164210319519043, + 0.73802000000000001, + 0.068815000000000001, + 312516, + 313024, + 1716628560.99596, + 5366956567842948 + ], + "child_modules": { + "tsdn28hpcpuhdb4096x32m4mw_170a_Int_Array": 1 + }, + "Compiled": "Yes", + "nRouts": 375, + "nMops": 20438, + "nQuads": 8228, + "Compiled Times": 163, + "end_perf": [ + 0.83657312393188477, + 0.75620699999999996, + 0.070737999999999995, + 312516, + 313024, + 5366956636564580, + 111669149697, + 0 + ] + }, + "debug_top": { + "start_perf": [ + 0.72355794906616211, + 0.64742599999999995, + 0.066734000000000002, + 312516, + 313024, + 1716628560.9030969, + 5366956251075196 + ], + "child_modules": { + "tsdn28hpcpuhdb128x128m4mw_170a": 2, + "sram_if_0000": 1 + }, + "Compiled": "Yes", + "nRouts": 294, + "nMops": 17892, + "nQuads": 4840, + "Compiled Times": 163, + "end_perf": [ + 0.74973201751708984, + 0.67252999999999996, + 0.067751000000000006, + 312516, + 313024, + 5366956340416991, + 85899345921, + 0 + ] + }, + "sram_if": { + "start_perf": [ + 0.66909193992614746, + 0.59900699999999996, + 0.060796999999999997, + 312516, + 313024, + 1716628560.8486309, + 5366956065305842 + ], + "child_modules": {}, + "Compiled": "Yes", + "nRouts": 33, + "nMops": 401, + "nQuads": 154, + "Compiled Times": 163, + "end_perf": [ + 0.67546796798706055, + 0.60433800000000004, + 0.061830000000000003, + 312516, + 313024, + 5366956087079789, + 12884901889, + 0 + ] + }, + "spi_if": { + "start_perf": [ + 1.5540800094604492, + 1.4512080000000001, + 0.091759999999999994, + 312516, + 313024, + 1716628561.733619, + 5366959083688698 + ], + "child_modules": {}, + "Compiled": "Yes", + "Compiled Times": 163, + "nQuads": 0, + "nMops": 0, + "end_perf": [ + 1.5548319816589355, + 1.4519580000000001, + 0.091759999999999994, + 312516, + 313024, + 5366959086275052, + 438086664193, + 0 + ], + "svclass": [ + "spi_if_vcs_virt_intf_C", + 0, + 0, + 0, + 0, + 0 + ], + "nRouts": 6 + }, + "sram_if_0000": { + "start_perf": [ + 0.6754920482635498, + 0.60436100000000004, + 0.061831999999999998, + 312516, + 313024, + 1716628560.855031, + 5366956087135507 + ], + "child_modules": {}, + "Compiled": "Yes", + "nRouts": 33, + "nMops": 716, + "nQuads": 308, + "Compiled Times": 163, + "end_perf": [ + 0.67845606803894043, + 0.60542099999999999, + 0.063728000000000007, + 312516, + 313024, + 5366956097282401, + 12884901889, + 0 + ] + }, + "rst_gen_unit": { + "start_perf": [ + 1.0638151168823242, + 0.97684499999999996, + 0.076881000000000005, + 312516, + 313024, + 1716628561.2433541, + 5366957411570560 + ], + "child_modules": {}, + "Compiled": "Yes", + "nRouts": 89, + "nMops": 2002, + "nQuads": 968, + "Compiled Times": 163, + "end_perf": [ + 1.0679669380187988, + 0.97910200000000003, + 0.078766000000000003, + 312516, + 313024, + 5366957425754971, + 270582939649, + 0 + ] + }, + "xy_dsp": { + "start_perf": [ + 1.3085570335388184, + 1.2122120000000001, + 0.085732000000000003, + 312516, + 313024, + 1716628561.488096, + 5366958246293633 + ], + "child_modules": { + "PH2AMP": 16, + "DUC4": 2, + "DW_mult_pipe_0000_0003": 32, + "dacif": 1 + }, + "Compiled": "Yes", + "nRouts": 1450, + "nMops": 66952, + "nQuads": 18346, + "Compiled Times": 96, + "end_perf": [ + 1.3630459308624268, + 1.265558, + 0.086763999999999994, + 312516, + 313024, + 5366958432180564, + 317827579905, + 0 + ] + }, + "ctrl_regfile": { + "start_perf": [ + 0.67848491668701172, + 0.60544799999999999, + 0.063730999999999996, + 312516, + 313024, + 1716628560.8580239, + 5366956097343423 + ], + "child_modules": {}, + "Compiled": "Yes", + "nRouts": 943, + "nMops": 18959, + "nQuads": 6921, + "Compiled Times": 163, + "end_perf": [ + 0.6929471492767334, + 0.618838, + 0.064772999999999997, + 312516, + 313024, + 5366956146735195, + 30064771073, + 0 + ] + }, + "mcu_regfile": { + "start_perf": [ + 0.93806600570678711, + 0.85544900000000001, + 0.072781999999999999, + 312516, + 313024, + 1716628561.117605, + 5366956982679726 + ], + "child_modules": {}, + "Compiled": "Yes", + "nRouts": 778, + "nMops": 20554, + "nQuads": 6080, + "Compiled Times": 163, + "end_perf": [ + 0.96821093559265137, + 0.88452200000000003, + 0.073792999999999997, + 312516, + 313024, + 5366957085584526, + 206158430209, + 0 + ] + }, + "sirv_gnrl_dffl": { + "start_perf": [ + 0.69833803176879883, + 0.62334800000000001, + 0.065643000000000007, + 312516, + 313024, + 1716628560.877877, + 5366956165054168 + ], + "child_modules": {}, + "Compiled": "Yes", + "nRouts": 20, + "nMops": 288, + "nQuads": 168, + "Compiled Times": 163, + "end_perf": [ + 0.70040011405944824, + 0.62533000000000005, + 0.065719, + 312516, + 313024, + 5366956172136670, + 60129542145, + 0 + ] + }, + "DW_mult_pipe_0000_0000": { + "start_perf": [ + 1.5087640285491943, + 1.4079709999999999, + 0.089773000000000006, + 312516, + 313024, + 1716628561.688303, + 5366958929132376 + ], + "child_modules": {}, + "Compiled": "Yes", + "nRouts": 55, + "nMops": 5465, + "nQuads": 1422, + "Compiled Times": 163, + "end_perf": [ + 1.5173630714416504, + 1.416544, + 0.089779999999999999, + 312516, + 313024, + 5366958958488597, + 420906795009, + 0 + ] + }, + "sirv_gnrl_ltch": { + "start_perf": [ + 0.70043396949768066, + 0.62536099999999994, + 0.065722000000000003, + 312516, + 313024, + 1716628560.8799729, + 5366956172205900 + ], + "child_modules": {}, + "Compiled": "Yes", + "nRouts": 18, + "nMops": 280, + "nQuads": 140, + "Compiled Times": 163, + "end_perf": [ + 0.70259809494018555, + 0.62740899999999999, + 0.065833000000000003, + 312516, + 313024, + 5366956179621172, + 73014444033, + 0 + ] + }, + "digital_top": { + "start_perf": [ + 1.2184789180755615, + 1.1283099999999999, + 0.079739000000000004, + 312516, + 313024, + 1716628561.3980179, + 5366957939079242 + ], + "child_modules": { + "system_regfile": 1, + "debug_top": 1, + "sram_if": 27, + "channel_top": 1, + "rst_gen_unit": 1, + "spi_slave": 1 + }, + "Compiled": "Yes", + "nRouts": 2464, + "nMops": 49975, + "nQuads": 17980, + "Compiled Times": 158, + "end_perf": [ + 1.2976291179656982, + 1.2042930000000001, + 0.082744999999999999, + 312516, + 313024, + 5366958209090474, + 309237645313, + 0 + ] + }, + "tsdn28hpcpuhdb128x128m4mw_170a": { + "start_perf": [ + 0.74977803230285645, + 0.67257199999999995, + 0.067754999999999996, + 312516, + 313024, + 1716628560.929317, + 5366956340499914 + ], + "significant_routs": [ + [ + 1126, + "R_VCSgd_rShyv_466", + 12339878, + 24637, + 3595 + ] + ], + "child_modules": { + "tsdn28hpcpuhdb128x128m4mw_170a_Int_Array": 1 + }, + "Compiled": "Yes", + "Compiled Times": 49, + "nQuads": 23808, + "nMops": 69686, + "end_perf": [ + 0.80220913887023926, + 0.72385500000000003, + 0.068795999999999996, + 312516, + 313024, + 5366956519386761, + 103079215105, + 0 + ], + "nRouts": 1133 + }, + "DW02_mult_0005": { + "start_perf": [ + 1.5473310947418213, + 1.4454469999999999, + 0.090785000000000005, + 312516, + 313024, + 1716628561.7268701, + 5366959060671203 + ], + "child_modules": {}, + "Compiled": "Yes", + "nRouts": 25, + "nMops": 7058, + "nQuads": 606, + "Compiled Times": 163, + "end_perf": [ + 1.55405592918396, + 1.4511849999999999, + 0.091758000000000006, + 312516, + 313024, + 5366959083630476, + 429496729601, + 0 + ] + }, + "tsdn28hpcpuhdb4096x32m4mw_170a_Int_Array": { + "start_perf": [ + 0.83660507202148438, + 0.75623600000000002, + 0.070740999999999998, + 312516, + 313024, + 1716628561.016144, + 5366956636632851 + ], + "significant_routs": [ + [ + 23, + "R_VCSgd_ay4xz_17", + 12447404, + 15692, + 1863 + ] + ], + "child_modules": {}, + "Compiled": "Yes", + "Compiled Times": 163, + "nQuads": 2502, + "nMops": 8076, + "end_perf": [ + 0.84995412826538086, + 0.76853000000000005, + 0.071768999999999999, + 312516, + 313024, + 5366956682194718, + 115964116993, + 0 + ], + "nRouts": 61 + }, + "qbmcu": { + "start_perf": [ + 0.97199201583862305, + 0.88731599999999999, + 0.074773000000000006, + 312516, + 313024, + 1716628561.151531, + 5366957098391864 + ], + "child_modules": { + "qbmcu_datalatch": 4, + "qbmcu_regfile_0000": 1 + }, + "Compiled": "Yes", + "nRouts": 1212, + "nMops": 34064, + "nQuads": 9974, + "Compiled Times": 163, + "end_perf": [ + 1.0496289730072021, + 0.96274800000000005, + 0.076819999999999999, + 312516, + 313024, + 5366957363257242, + 214748364801, + 0 + ] + }, + "TSDN28HPCPUHDB4096X32M4MWR_Int_Array": { + "start_perf": [ + 0.87191295623779297, + 0.79044199999999998, + 0.071771000000000001, + 312516, + 313024, + 1716628561.0514519, + 5366956757057519 + ], + "child_modules": {}, + "Compiled": "Yes", + "nRouts": 86, + "nMops": 14181, + "nQuads": 4214, + "Compiled Times": 96, + "end_perf": [ + 0.89372014999389648, + 0.81220400000000004, + 0.071771000000000001, + 312516, + 313024, + 5366956831467502, + 124554051585, + 0 + ] + }, + "TSDN28HPCPUHDB4096X32M4MWR": { + "start_perf": [ + 0.84998106956481934, + 0.76855499999999999, + 0.071771000000000001, + 312516, + 313024, + 1716628561.02952, + 5366956682254714 + ], + "child_modules": { + "TSDN28HPCPUHDB4096X32M4MWR_Int_Array": 1 + }, + "Compiled": "Yes", + "nRouts": 394, + "nMops": 22078, + "nQuads": 8894, + "Compiled Times": 96, + "end_perf": [ + 0.87188506126403809, + 0.79041300000000003, + 0.071771000000000001, + 312516, + 313024, + 5366956756991535, + 120259084289, + 0 + ] + }, + "tsdn28hpcpuhdb64x32m4mw_170a_Int_Array": { + "start_perf": [ + 0.89374995231628418, + 0.81223500000000004, + 0.071771000000000001, + 312516, + 313024, + 1716628561.0732889, + 5366956831534123 + ], + "significant_routs": [ + [ + 23, + "R_VCSgd_JweIx_17", + 12596654, + 15647, + 1863 + ] + ], + "child_modules": {}, + "Compiled": "Yes", + "Compiled Times": 96, + "nQuads": 2502, + "nMops": 8076, + "end_perf": [ + 0.90700507164001465, + 0.82545500000000005, + 0.071777999999999995, + 312516, + 313024, + 5366956876775830, + 133143986177, + 0 + ], + "nRouts": 61 + }, + "qbmcu_busdecoder": { + "start_perf": [ + 0.96825695037841797, + 0.88456500000000005, + 0.073796, + 312516, + 313024, + 1716628561.1477959, + 5366957085651696 + ], + "child_modules": {}, + "Compiled": "Yes", + "nRouts": 35, + "nMops": 2058, + "nQuads": 480, + "Compiled Times": 163, + "end_perf": [ + 0.97196507453918457, + 0.88729100000000005, + 0.074771000000000004, + 312516, + 313024, + 5366957098329975, + 210453397505, + 0 + ] + }, + "qbmcu_datalatch": { + "start_perf": [ + 1.0496721267700195, + 0.96278799999999998, + 0.076823000000000002, + 312516, + 313024, + 1716628561.2292111, + 5366957363332681 + ], + "child_modules": {}, + "Compiled": "Yes", + "nRouts": 25, + "nMops": 1002, + "nQuads": 248, + "Compiled Times": 163, + "end_perf": [ + 1.0521340370178223, + 0.96524500000000002, + 0.076823000000000002, + 312516, + 313024, + 5366957371766410, + 219043332097, + 0 + ] + }, + "qbmcu_regfile_0000": { + "start_perf": [ + 1.0521619319915771, + 0.96527300000000005, + 0.076823000000000002, + 312516, + 313024, + 1716628561.2317009, + 5366957371823231 + ], + "child_modules": {}, + "Compiled": "Yes", + "nRouts": 369, + "nMops": 6589, + "nQuads": 2686, + "Compiled Times": 163, + "end_perf": [ + 1.0637650489807129, + 0.97684499999999996, + 0.076829999999999996, + 312516, + 313024, + 5366957411483621, + 261993005057, + 0 + ] + }, + "dacif": { + "start_perf": [ + 1.2976751327514648, + 1.2043360000000001, + 0.082748000000000002, + 312516, + 313024, + 1716628561.4772141, + 5366958209188908 + ], + "child_modules": {}, + "Compiled": "Yes", + "nRouts": 206, + "nMops": 10166, + "nQuads": 3586, + "Compiled Times": 163, + "end_perf": [ + 1.3085250854492188, + 1.2121820000000001, + 0.085730000000000001, + 312516, + 313024, + 5366958246232678, + 313532612609, + 0 + ] + }, + "system_regfile": { + "start_perf": [ + 1.1163489818572998, + 1.027355, + 0.078797000000000006, + 312516, + 313024, + 1716628561.2958879, + 5366957590744484 + ], + "child_modules": {}, + "Compiled": "Yes", + "nRouts": 515, + "nMops": 10566, + "nQuads": 4066, + "Compiled Times": 163, + "end_perf": [ + 1.1386620998382568, + 1.049623, + 0.078797000000000006, + 312516, + 313024, + 5366957666879908, + 300647710721, + 0 + ] + }, + "channel_top": { + "start_perf": [ + 1.13869309425354, + 1.0496540000000001, + 0.078797000000000006, + 312516, + 313024, + 1716628561.3182321, + 5366957666953647 + ], + "child_modules": { + "z_dsp": 1, + "modout_mux": 1, + "dac_regfile": 1, + "qbmcu_busdecoder": 1, + "DW_mult_pipe_0000_0002": 2, + "DW_mult_pipe_0000_0003": 4, + "PH2AMP": 1, + "param_lut_0002": 2, + "mcu_regfile": 1, + "TSDN28HPCPUHDB4096X32M4MWR": 6, + "qbmcu": 1, + "tsdn28hpcpuhdb64x32m4mw_170a_Int_Array": 1, + "xy_dsp": 1, + "ctrl_regfile": 1 + }, + "Compiled": "Yes", + "nRouts": 1500, + "nMops": 38963, + "nQuads": 12591, + "Compiled Times": 163, + "end_perf": [ + 1.2184369564056396, + 1.1282700000000001, + 0.079736000000000001, + 312516, + 313024, + 5366957938991886, + 304942678017, + 0 + ] + }, + "DUC_HB2": { + "start_perf": [ + 1.3630831241607666, + 1.265593, + 0.086765999999999996, + 312516, + 313024, + 1716628561.5426221, + 5366958432264040 + ], + "child_modules": {}, + "Compiled": "Yes", + "nRouts": 146, + "nMops": 11462, + "nQuads": 2754, + "Compiled Times": 163, + "end_perf": [ + 1.3759889602661133, + 1.2774799999999999, + 0.087758000000000003, + 312516, + 313024, + 5366958476320509, + 330712481793, + 0 + ] + }, + "DUC_HB4": { + "start_perf": [ + 1.3855969905853271, + 1.287067, + 0.087760000000000005, + 312516, + 313024, + 1716628561.565136, + 5366958509053363 + ], + "child_modules": {}, + "Compiled": "Yes", + "nRouts": 91, + "nMops": 6164, + "nQuads": 1606, + "Compiled Times": 163, + "end_perf": [ + 1.3940169811248779, + 1.2944720000000001, + 0.088758000000000004, + 312516, + 313024, + 5366958537796609, + 347892350977, + 0 + ] + }, + "IIR_Filter": { + "start_perf": [ + 1.4507350921630859, + 1.351073, + 0.088759000000000005, + 312516, + 313024, + 1716628561.6302741, + 5366958731214779 + ], + "child_modules": { + "DW02_mult_0004": 4, + "DW02_mult_0005": 4 + }, + "Compiled": "Yes", + "nRouts": 148, + "nMops": 7688, + "nQuads": 2036, + "Compiled Times": 163, + "end_perf": [ + 1.4612259864807129, + 1.3605309999999999, + 0.089771000000000004, + 312516, + 313024, + 5366958767029305, + 373662154753, + 0 + ] + }, + "z_dsp": { + "start_perf": [ + 1.4612569808959961, + 1.3605610000000001, + 0.089773000000000006, + 312516, + 313024, + 1716628561.6407959, + 5366958767100241 + ], + "child_modules": { + "IIR_Filter": 6 + }, + "Compiled": "Yes", + "nRouts": 313, + "nMops": 13876, + "nQuads": 4236, + "Compiled Times": 163, + "end_perf": [ + 1.4775979518890381, + 1.376868, + 0.089773000000000006, + 312516, + 313024, + 5366958822868478, + 412316860417, + 0 + ] + }, + "TB": { + "start_perf": [ + 1.4776279926300049, + 1.3768989999999999, + 0.089773000000000006, + 312516, + 313024, + 1716628561.657167, + 5366958822938527 + ], + "child_modules": { + "spi_if": 1, + "digital_top": 1 + }, + "Compiled": "Yes", + "nRouts": 544, + "nMops": 23558, + "nQuads": 8884, + "Compiled Times": 156, + "end_perf": [ + 1.5087361335754395, + 1.4079429999999999, + 0.089773000000000006, + 312516, + 313024, + 5366958929069591, + 416611827713, + 0 + ] + }, + "DW_mult_pipe_0000_0002": { + "start_perf": [ + 1.5173890590667725, + 1.416569, + 0.089782000000000001, + 312516, + 313024, + 1716628561.696928, + 5366958958547843 + ], + "child_modules": {}, + "Compiled": "Yes", + "nRouts": 55, + "nMops": 8229, + "nQuads": 1422, + "Compiled Times": 163, + "end_perf": [ + 1.5274889469146729, + 1.4266480000000001, + 0.089782000000000001, + 312516, + 313024, + 5366958993058884, + 420906795009, + 0 + ] + }, + "DW_mult_pipe_0000_0003": { + "start_perf": [ + 1.5275270938873291, + 1.426687, + 0.089782000000000001, + 312516, + 313024, + 1716628561.7070661, + 5366958993126586 + ], + "child_modules": {}, + "Compiled": "Yes", + "nRouts": 55, + "nMops": 5191, + "nQuads": 1422, + "Compiled Times": 30, + "end_perf": [ + 1.5363321304321289, + 1.4344790000000001, + 0.090776999999999997, + 312516, + 313024, + 5366959023190991, + 420906795009, + 0 + ] + }, + "DW01_addsub": { + "start_perf": [ + 1.5363619327545166, + 1.434507, + 0.090777999999999998, + 312516, + 313024, + 1716628561.7159009, + 5366959023259593 + ], + "child_modules": {}, + "Compiled": "Yes", + "nRouts": 23, + "nMops": 2376, + "nQuads": 430, + "Compiled Times": 163, + "end_perf": [ + 1.5404379367828369, + 1.4385699999999999, + 0.090783000000000003, + 312516, + 313024, + 5366959037190185, + 425201762305, + 0 + ] + }, + "DW02_mult_0004": { + "start_perf": [ + 1.540463924407959, + 1.4385950000000001, + 0.090785000000000005, + 312516, + 313024, + 1716628561.7200029, + 5366959037296967 + ], + "child_modules": {}, + "Compiled": "Yes", + "nRouts": 25, + "nMops": 7046, + "nQuads": 606, + "Compiled Times": 163, + "end_perf": [ + 1.5473051071166992, + 1.4454210000000001, + 0.090785000000000005, + 312516, + 313024, + 5366959060609613, + 429496729601, + 0 + ] + } + }, + "CompUnits": { + "IHYdB_d": { + "mod": "spi_if", + "out": "IHYdB_d.o", + "mode": 4, + "bytes": 11636, + "archive": "archive.162/_3127_archive_1.a", + "text": 213, + "checksum": 0 + }, + "amcQw_d": { + "mod": "...MASTER...", + "out": "objs/amcQw_d.o", + "mode": 4, + "bytes": 9160, + "text": 653, + "checksum": 0 + }, + "UTi0b_d": { + "mod": "sirv_gnrl_ltch", + "out": "UTi0b_d.o", + "mode": 4, + "bytes": 9700, + "archive": "archive.162/_3127_archive_1.a", + "text": 1507, + "checksum": 0 + }, + "HNRiG_d": { + "mod": "DW_mult_pipe_0000_0000", + "out": "HNRiG_d.o", + "mode": 4, + "bytes": 38420, + "archive": "archive.162/_3127_archive_1.a", + "text": 21600, + "checksum": 0 + }, + "iYIEc_d": { + "mod": "PH2AMP", + "out": "iYIEc_d.o", + "mode": 4, + "bytes": 158200, + "archive": "archive.162/_3127_archive_1.a", + "text": 98836, + "checksum": 0 + }, + "D1hM1_d": { + "mod": "_vcs_unit__504089786", + "out": "D1hM1_d.o", + "mode": 4, + "bytes": 88126, + "archive": "archive.162/_3127_archive_1.a", + "text": 14843, + "cls": 14516, + "checksum": 0 + }, + "xFWdC_d": { + "mod": "channel_top", + "out": "xFWdC_d.o", + "mode": 4, + "bytes": 468752, + "archive": "archive.162/_3127_archive_1.a", + "text": 301887, + "checksum": 0 + }, + "rTmJG_d": { + "mod": "digital_top", + "out": "rTmJG_d.o", + "mode": 4, + "bytes": 644250, + "archive": "archive.162/_3127_archive_1.a", + "text": 386152, + "checksum": 0 + }, + "nJgqZ_d": { + "mod": "sram_if_0000", + "out": "nJgqZ_d.o", + "mode": 4, + "bytes": 16568, + "archive": "archive.162/_3127_archive_1.a", + "text": 3711, + "checksum": 0 + }, + "nJN5E_d": { + "mod": "param_lut_0002", + "out": "nJN5E_d.o", + "mode": 4, + "bytes": 19394, + "archive": "archive.162/_3127_archive_1.a", + "text": 7703, + "checksum": 0 + }, + "BM4bj_d": { + "mod": "sirv_gnrl_dffl", + "out": "BM4bj_d.o", + "mode": 4, + "bytes": 9566, + "archive": "archive.162/_3127_archive_1.a", + "text": 1374, + "checksum": 0 + }, + "e36VC_d": { + "mod": "TSDN28HPCPUHDB4096X32M4MWR_Int_Array", + "out": "e36VC_d.o", + "mode": 4, + "bytes": 106790, + "archive": "archive.162/_3127_archive_1.a", + "text": 60950, + "checksum": 0 + }, + "Sg3ri_d": { + "mod": "TSDN28HPCPUHDB4096X32M4MWR", + "out": "Sg3ri_d.o", + "mode": 4, + "bytes": 122964, + "archive": "archive.162/_3127_archive_1.a", + "text": 68656, + "checksum": 0 + }, + "LR0zI_d": { + "mod": "dac_regfile", + "out": "LR0zI_d.o", + "mode": 4, + "bytes": 118956, + "archive": "archive.162/_3127_archive_1.a", + "text": 73359, + "checksum": 0 + }, + "SMgga_d": { + "mod": "dacif", + "out": "SMgga_d.o", + "mode": 4, + "bytes": 62530, + "archive": "archive.162/_3127_archive_1.a", + "text": 42611, + "checksum": 0 + }, + "rLaFI_d": { + "mod": "IIR_Filter", + "out": "rLaFI_d.o", + "mode": 4, + "bytes": 55838, + "archive": "archive.162/_3127_archive_1.a", + "text": 31475, + "checksum": 0 + }, + "rShyv_d": { + "mod": "tsdn28hpcpuhdb128x128m4mw_170a", + "out": "rShyv_d.o", + "mode": 4, + "bytes": 297858, + "archive": "archive.162/_3127_archive_1.a", + "text": 199889, + "checksum": 0 + }, + "HWLgR_d": { + "mod": "mcu_regfile", + "out": "HWLgR_d.o", + "mode": 4, + "bytes": 226690, + "archive": "archive.162/_3127_archive_1.a", + "text": 144659, + "checksum": 0 + }, + "gNaPt_d": { + "mod": "debug_top", + "out": "gNaPt_d.o", + "mode": 4, + "bytes": 108122, + "archive": "archive.162/_3127_archive_1.a", + "text": 66239, + "checksum": 0 + }, + "W3x1b_d": { + "mod": "system_regfile", + "out": "W3x1b_d.o", + "mode": 4, + "bytes": 141826, + "archive": "archive.162/_3127_archive_1.a", + "text": 80143, + "checksum": 0 + }, + "hwIug_d": { + "mod": "DW02_mult_0004", + "out": "hwIug_d.o", + "mode": 4, + "bytes": 29288, + "archive": "archive.162/_3127_archive_1.a", + "text": 17912, + "checksum": 0 + }, + "eFLuy_d": { + "mod": "tsdn28hpcpuhdb128x128m4mw_170a_Int_Array", + "out": "eFLuy_d.o", + "mode": 4, + "bytes": 66736, + "archive": "archive.162/_3127_archive_1.a", + "text": 35490, + "checksum": 0 + }, + "d6TPd_d": { + "mod": "tsdn28hpcpuhdb4096x32m4mw_170a", + "out": "d6TPd_d.o", + "mode": 4, + "bytes": 109700, + "archive": "archive.162/_3127_archive_1.a", + "text": 63696, + "checksum": 0 + }, + "ay4xz_d": { + "mod": "tsdn28hpcpuhdb4096x32m4mw_170a_Int_Array", + "out": "ay4xz_d.o", + "mode": 4, + "bytes": 66252, + "archive": "archive.162/_3127_archive_1.a", + "text": 35222, + "checksum": 0 + }, + "jAiwN_d": { + "mod": "qbmcu_busdecoder", + "out": "jAiwN_d.o", + "mode": 4, + "bytes": 16690, + "archive": "archive.162/_3127_archive_1.a", + "text": 7155, + "checksum": 0 + }, + "JweIx_d": { + "mod": "tsdn28hpcpuhdb64x32m4mw_170a_Int_Array", + "out": "JweIx_d.o", + "mode": 4, + "bytes": 65620, + "archive": "archive.162/_3127_archive_1.a", + "text": 34994, + "checksum": 0 + }, + "xnbfb_d": { + "mod": "qbmcu", + "out": "xnbfb_d.o", + "mode": 4, + "bytes": 388698, + "archive": "archive.162/_3127_archive_1.a", + "text": 249459, + "checksum": 0 + }, + "eAsJz_d": { + "mod": "spi_slave", + "out": "eAsJz_d.o", + "mode": 4, + "bytes": 308970, + "archive": "archive.162/_3127_archive_1.a", + "text": 188711, + "checksum": 0 + }, + "MsCBG_d": { + "mod": "qbmcu_datalatch", + "out": "MsCBG_d.o", + "mode": 4, + "bytes": 12266, + "archive": "archive.162/_3127_archive_1.a", + "text": 3672, + "checksum": 0 + }, + "Hit7c_d": { + "mod": "qbmcu_regfile_0000", + "out": "Hit7c_d.o", + "mode": 4, + "bytes": 92426, + "archive": "archive.162/_3127_archive_1.a", + "text": 49819, + "checksum": 0 + }, + "zpIk1_d": { + "mod": "z_dsp", + "out": "zpIk1_d.o", + "mode": 4, + "bytes": 88692, + "archive": "archive.162/_3127_archive_1.a", + "text": 53911, + "checksum": 0 + }, + "anuMN_d": { + "mod": "rst_gen_unit", + "out": "anuMN_d.o", + "mode": 4, + "bytes": 21774, + "archive": "archive.162/_3127_archive_1.a", + "text": 8383, + "checksum": 0 + }, + "U33JQ_d": { + "mod": "xy_dsp", + "out": "U33JQ_d.o", + "mode": 4, + "bytes": 380142, + "archive": "archive.162/_3127_archive_1.a", + "text": 244551, + "checksum": 0 + }, + "KysYq_d": { + "mod": "DW01_addsub", + "out": "KysYq_d.o", + "mode": 4, + "bytes": 18370, + "archive": "archive.162/_3127_archive_1.a", + "text": 8432, + "checksum": 0 + }, + "ksFw4_d": { + "mod": "DUC_HB2", + "out": "ksFw4_d.o", + "mode": 4, + "bytes": 60820, + "archive": "archive.162/_3127_archive_1.a", + "text": 41471, + "checksum": 0 + }, + "SiiVi_d": { + "mod": "DW_mult_pipe_0000_0002", + "out": "SiiVi_d.o", + "mode": 4, + "bytes": 41994, + "archive": "archive.162/_3127_archive_1.a", + "text": 24592, + "checksum": 0 + }, + "Rdd8k_d": { + "mod": "DUC_HB3", + "out": "Rdd8k_d.o", + "mode": 4, + "bytes": 44056, + "archive": "archive.162/_3127_archive_1.a", + "text": 27407, + "checksum": 0 + }, + "cwtAY_d": { + "mod": "DUC4", + "out": "cwtAY_d.o", + "mode": 4, + "bytes": 302476, + "archive": "archive.162/_3127_archive_1.a", + "text": 216676, + "checksum": 0 + }, + "zwWSN_d": { + "mod": "DUC_HB4", + "out": "zwWSN_d.o", + "mode": 4, + "bytes": 39014, + "archive": "archive.162/_3127_archive_1.a", + "text": 23235, + "checksum": 0 + }, + "sH4Fc_d": { + "mod": "TB", + "out": "sH4Fc_d.o", + "mode": 4, + "bytes": 216624, + "archive": "archive.162/_3127_archive_1.a", + "text": 110871, + "checksum": 0 + }, + "ZpmS6_d": { + "mod": "DW_mult_pipe_0000_0003", + "out": "ZpmS6_d.o", + "mode": 4, + "bytes": 37410, + "archive": "archive.162/_3127_archive_1.a", + "text": 20756, + "checksum": 0 + }, + "UIt6b_d": { + "mod": "DW02_mult_0005", + "out": "UIt6b_d.o", + "mode": 4, + "bytes": 29268, + "archive": "archive.162/_3127_archive_1.a", + "text": 17892, + "checksum": 0 + } + }, + "reusePaths": { + "reYIK_d": { + "icPath": "csrc" + }, + "jEu9i_d": { + "icPath": "csrc" + }, + "NABmh_d": { + "icPath": "csrc" + }, + "mLA3J_d": { + "icPath": "csrc" + } + }, + "ObjArchives": [ + { + "archive": "archive.162/_3127_archive_1.a", + "objects": [ + [ + "D1hM1_d.o", + 88126 + ], + [ + "nJgqZ_d.o", + 16568 + ], + [ + "nJN5E_d.o", + 19394 + ], + [ + "BM4bj_d.o", + 9566 + ], + [ + "UTi0b_d.o", + 9700 + ], + [ + "LR0zI_d.o", + 118956 + ], + [ + "gNaPt_d.o", + 108122 + ], + [ + "rShyv_d.o", + 297858 + ], + [ + "eFLuy_d.o", + 66736 + ], + [ + "d6TPd_d.o", + 109700 + ], + [ + "ay4xz_d.o", + 66252 + ], + [ + "Sg3ri_d.o", + 122964 + ], + [ + "e36VC_d.o", + 106790 + ], + [ + "JweIx_d.o", + 65620 + ], + [ + "iYIEc_d.o", + 158200 + ], + [ + "HWLgR_d.o", + 226690 + ], + [ + "jAiwN_d.o", + 16690 + ], + [ + "xnbfb_d.o", + 388698 + ], + [ + "MsCBG_d.o", + 12266 + ], + [ + "Hit7c_d.o", + 92426 + ], + [ + "anuMN_d.o", + 21774 + ], + [ + "eAsJz_d.o", + 308970 + ], + [ + "W3x1b_d.o", + 141826 + ], + [ + "xFWdC_d.o", + 468752 + ], + [ + "rTmJG_d.o", + 644250 + ], + [ + "SMgga_d.o", + 62530 + ], + [ + "U33JQ_d.o", + 380142 + ], + [ + "ksFw4_d.o", + 60820 + ], + [ + "Rdd8k_d.o", + 44056 + ], + [ + "zwWSN_d.o", + 39014 + ], + [ + "cwtAY_d.o", + 302476 + ], + [ + "rLaFI_d.o", + 55838 + ], + [ + "zpIk1_d.o", + 88692 + ], + [ + "sH4Fc_d.o", + 216624 + ], + [ + "HNRiG_d.o", + 38420 + ], + [ + "SiiVi_d.o", + 41994 + ], + [ + "ZpmS6_d.o", + 37410 + ], + [ + "KysYq_d.o", + 18370 + ], + [ + "hwIug_d.o", + 29288 + ], + [ + "UIt6b_d.o", + 29268 + ], + [ + "IHYdB_d.o", + 11636 + ], + [ + "amcQwB.o", + 169714 + ] + ], + "size": 5313186 + } + ], + "stat": { + "ru_self_end": { + "ru_utime_sec": 1.452623, + "ru_minflt": 43105, + "ru_stime_sec": 0.094714000000000007, + "ru_maxrss_kb": 113780, + "ru_majflt": 0, + "ru_nvcsw": 32, + "ru_nivcsw": 14 + }, + "cpu_cycles_end": 5366959098587723, + "ru_childs_end": { + "ru_utime_sec": 0.0090399999999999994, + "ru_minflt": 10699, + "ru_stime_sec": 0.015606999999999999, + "ru_maxrss_kb": 46032, + "ru_majflt": 0, + "ru_nvcsw": 25, + "ru_nivcsw": 24 + }, + "peak_mem_kb": 313024 + } +} \ No newline at end of file diff --git a/tb/chip_top/csrc/cgproc.58486.json b/tb/chip_top/csrc/cgproc.58486.json new file mode 100644 index 0000000..5e968f0 --- /dev/null +++ b/tb/chip_top/csrc/cgproc.58486.json @@ -0,0 +1,1595 @@ +{ + "Modules": { + "tsdn28hpcpuhdb4096x32m4mw_170a": { + "end_perf": [ + 0.74352788925170898, + 0.64621799999999996, + 0.088932999999999998, + 311752, + 312000, + 7945479629370579, + 111669149697, + 0 + ], + "start_perf": [ + 0.73480486869812012, + 0.63752299999999995, + 0.088932999999999998, + 311752, + 312000, + 1717383081.7328179, + 7945479599625325 + ], + "child_modules": { + "tsdn28hpcpuhdb4096x32m4mw_170a_Int_Array": 1 + }, + "nMops": 10255, + "Compiled": "Yes", + "Compiled Times": 29, + "nQuads": 4126, + "nRouts": 375 + }, + "tsdn28hpcpuhdb128x128m4mw_170a_Int_Array": { + "end_perf": [ + 0.73477697372436523, + 0.63749900000000004, + 0.088929999999999995, + 311752, + 312000, + 7945479599566674, + 107374182401, + 0 + ], + "start_perf": [ + 0.73076391220092773, + 0.63351400000000002, + 0.088914000000000007, + 311752, + 312000, + 1717383081.7287769, + 7945479585861552 + ], + "child_modules": {}, + "nMops": 4123, + "Compiled": "Yes", + "Compiled Times": 29, + "nQuads": 1251, + "nRouts": 61 + }, + "_vcs_unit__3598111382": { + "start_perf": [ + 0.65259099006652832, + 0.55748399999999998, + 0.087032999999999999, + 309784, + 312000, + 1717383081.650604, + 7945479319558049 + ], + "end_perf": [ + 0.66164088249206543, + 0.56572299999999998, + 0.087801000000000004, + 311752, + 312000, + 7945479350420521, + 4294967297, + 0 + ], + "svclass": [ + "BinaryDataReader", + 2977, + 297, + 4, + 4, + 4294977643, + "spi_data_send", + 4400, + 447, + 20, + 3, + 4294977683, + "spi_reg", + 6750, + 854, + 20, + 3, + 4294977711 + ], + "child_modules": {}, + "Compiled": "Yes", + "nMops": 1645, + "Compiled Times": 29, + "nQuads": 421, + "nRouts": 49 + }, + "...MASTER...": { + "end_perf": [ + 0.65247797966003418, + 0.55748399999999998, + 0.086918999999999996, + 309784, + 312000, + 7945479319202767, + 0, + 0 + ], + "start_perf": [ + 0.64849495887756348, + 0.55532700000000002, + 0.086882000000000001, + 309772, + 312000, + 1717383081.646508, + 7945479305603456 + ], + "child_modules": { + "DW01_addsub": 1, + "std": 1, + "TB": 1, + "sirv_gnrl_ltch": 1, + "sirv_gnrl_dffl": 1, + "_vcs_unit__3598111382": 1 + }, + "nQuads": 4, + "nMops": 7, + "nRouts": 8 + }, + "tsdn28hpcpuhdb64x32m4mw_170a_Int_Array": { + "end_perf": [ + 0.75065207481384277, + 0.65331899999999998, + 0.088932999999999998, + 311752, + 312000, + 7945479653643337, + 124554051585, + 0 + ], + "start_perf": [ + 0.74709486961364746, + 0.64977399999999996, + 0.088932999999999998, + 311752, + 312000, + 1717383081.7451079, + 7945479641496216 + ], + "child_modules": {}, + "nMops": 4038, + "Compiled": "Yes", + "Compiled Times": 29, + "nQuads": 1251, + "nRouts": 61 + }, + "std": { + "start_perf": [ + 0.66167497634887695, + 0.56575299999999995, + 0.087805999999999995, + 311752, + 312000, + 1717383081.659688, + 7945479350494338 + ], + "end_perf": [ + 0.66280007362365723, + 0.56672299999999998, + 0.087956999999999994, + 311752, + 312000, + 7945479354351145, + 8589934594, + 0 + ], + "svclass": [ + "$vcs_nba_dyn_obj", + 0, + 35, + 2, + 2, + 0, + "sigprop$$", + 0, + 35, + 2, + 2, + 0, + "process", + 0, + 200, + 8, + 8, + 0, + "event", + 0, + 34, + 2, + 2, + 0, + "mailbox", + 0, + 140, + 9, + 9, + 0, + "semaphore", + 0, + 84, + 5, + 5, + 0 + ], + "child_modules": {}, + "Compiled": "Yes", + "nMops": 528, + "Compiled Times": 29, + "nQuads": 218, + "nRouts": 33 + }, + "tsdn28hpcpuhdb4096x32m4mw_170a_Int_Array": { + "end_perf": [ + 0.7470700740814209, + 0.64974900000000002, + 0.088932999999999998, + 311752, + 312000, + 7945479641437337, + 115964116993, + 0 + ], + "start_perf": [ + 0.74355506896972656, + 0.64624499999999996, + 0.088932999999999998, + 311752, + 312000, + 1717383081.7415681, + 7945479629434857 + ], + "child_modules": {}, + "nMops": 4038, + "Compiled": "Yes", + "Compiled Times": 29, + "nQuads": 1251, + "nRouts": 61 + }, + "sram_if": { + "end_perf": [ + 0.66335105895996094, + 0.56726900000000002, + 0.087959999999999997, + 311752, + 312000, + 7945479356227910, + 12884901889, + 0 + ], + "start_perf": [ + 0.6628270149230957, + 0.566747, + 0.087959999999999997, + 311752, + 312000, + 1717383081.66084, + 7945479354417484 + ], + "child_modules": {}, + "nMops": 68, + "Compiled": "Yes", + "Compiled Times": 29, + "nQuads": 24, + "nRouts": 10 + }, + "DUC_HB2": { + "end_perf": [ + 1.1421449184417725, + 1.030675, + 0.101822, + 311752, + 312000, + 7945480987428240, + 326417514497, + 0 + ], + "start_perf": [ + 1.1286568641662598, + 1.0172300000000001, + 0.101822, + 311752, + 312000, + 1717383082.1266699, + 7945480941389052 + ], + "child_modules": {}, + "nMops": 11462, + "Compiled": "Yes", + "Compiled Times": 29, + "nQuads": 2754, + "nRouts": 146 + }, + "spi_if": { + "start_perf": [ + 1.273853063583374, + 1.152061, + 0.11171499999999999, + 311752, + 312000, + 1717383082.2718661, + 7945481436101611 + ], + "end_perf": [ + 1.2742519378662109, + 1.152423, + 0.11175, + 311752, + 312000, + 7945481437394711, + 403726925825, + 0 + ], + "svclass": [ + "spi_if_vcs_virt_intf_C", + 0, + 0, + 0, + 0, + 0 + ], + "child_modules": {}, + "Compiled": "Yes", + "nMops": 0, + "Compiled Times": 29, + "nQuads": 0, + "nRouts": 6 + }, + "qbmcu_datalatch": { + "end_perf": [ + 0.79878401756286621, + 0.69732300000000003, + 0.092909000000000005, + 311752, + 312000, + 7945479817622835, + 210453397505, + 0 + ], + "start_perf": [ + 0.79788088798522949, + 0.69652800000000004, + 0.092802999999999997, + 311752, + 312000, + 1717383081.7958939, + 7945479814510835 + ], + "child_modules": {}, + "nMops": 501, + "Compiled": "Yes", + "Compiled Times": 29, + "nQuads": 124, + "nRouts": 25 + }, + "sirv_gnrl_dffl": { + "end_perf": [ + 0.67894196510314941, + 0.58209500000000003, + 0.088676000000000005, + 311752, + 312000, + 7945479409341227, + 60129542145, + 0 + ], + "start_perf": [ + 0.67822408676147461, + 0.58209500000000003, + 0.087959999999999997, + 311752, + 312000, + 1717383081.6762371, + 7945479406870729 + ], + "child_modules": {}, + "nMops": 144, + "Compiled": "Yes", + "Compiled Times": 29, + "nQuads": 84, + "nRouts": 20 + }, + "modout_mux": { + "end_perf": [ + 0.67820000648498535, + 0.58207100000000001, + 0.087959999999999997, + 311752, + 312000, + 7945479406815589, + 38654705665, + 0 + ], + "start_perf": [ + 0.67749905586242676, + 0.58137300000000003, + 0.087959999999999997, + 311752, + 312000, + 1717383081.6755121, + 7945479404403036 + ], + "child_modules": {}, + "nMops": 289, + "Compiled": "Yes", + "Compiled Times": 29, + "nQuads": 90, + "nRouts": 24 + }, + "sram_if_0000": { + "end_perf": [ + 0.6638028621673584, + 0.56772, + 0.087959999999999997, + 311752, + 312000, + 7945479357765719, + 12884901889, + 0 + ], + "start_perf": [ + 0.66337490081787109, + 0.56729300000000005, + 0.087959999999999997, + 311752, + 312000, + 1717383081.6613879, + 7945479356284767 + ], + "child_modules": {}, + "nMops": 48, + "Compiled": "Yes", + "Compiled Times": 29, + "nQuads": 24, + "nRouts": 10 + }, + "DAC_DEM_4": { + "end_perf": [ + 1.23124098777771, + 1.1128439999999999, + 0.10846600000000001, + 311752, + 312000, + 7945481290872613, + 377957122049, + 0 + ], + "start_perf": [ + 1.2305629253387451, + 1.1128439999999999, + 0.107791, + 311752, + 312000, + 1717383082.2285759, + 7945481288538327 + ], + "child_modules": { + "DAC_DEM": 4 + }, + "nMops": 0, + "Compiled": "Yes", + "Compiled Times": 29, + "nQuads": 0, + "nRouts": 5 + }, + "tsdn28hpcpuhdb128x128m4mw_170a": { + "end_perf": [ + 0.73071789741516113, + 0.63346800000000003, + 0.088914000000000007, + 311752, + 312000, + 7945479585783806, + 103079215105, + 0 + ], + "start_perf": [ + 0.69356107711791992, + 0.59642899999999999, + 0.088914000000000007, + 311752, + 312000, + 1717383081.6915741, + 7945479459120475 + ], + "child_modules": { + "tsdn28hpcpuhdb128x128m4mw_170a_Int_Array": 1 + }, + "nMops": 34843, + "Compiled": "Yes", + "Compiled Times": 29, + "nQuads": 11904, + "nRouts": 1133 + }, + "ctrl_regfile": { + "end_perf": [ + 0.6705329418182373, + 0.57442800000000005, + 0.087959999999999997, + 311752, + 312000, + 7945479380709620, + 30064771073, + 0 + ], + "start_perf": [ + 0.66382598876953125, + 0.567743, + 0.087959999999999997, + 311752, + 312000, + 1717383081.661839, + 7945479357821312 + ], + "child_modules": {}, + "nMops": 7265, + "Compiled": "Yes", + "Compiled Times": 29, + "nQuads": 2767, + "nRouts": 397 + }, + "xyz_chip_top": { + "end_perf": [ + 1.0602869987487793, + 0.950102, + 0.100798, + 311752, + 312000, + 7945480708532366, + 304942678017, + 0 + ], + "start_perf": [ + 0.96214604377746582, + 0.854271, + 0.098799999999999999, + 311752, + 312000, + 1717383081.9601591, + 7945480374126068 + ], + "child_modules": { + "DAC_DEM_16": 1, + "system_regfile": 1, + "DAC_DEM_4": 1, + "sram_if": 27, + "channel_top": 1, + "debug_top": 1, + "spi_slave": 1, + "rst_gen_unit": 1 + }, + "nMops": 100116, + "Compiled": "Yes", + "Compiled Times": 29, + "nQuads": 36004, + "nRouts": 2575 + }, + "param_lut_0002": { + "end_perf": [ + 0.67746996879577637, + 0.58134300000000005, + 0.087959999999999997, + 311752, + 312000, + 7945479404340637, + 34359738369, + 0 + ], + "start_perf": [ + 0.6705629825592041, + 0.57445900000000005, + 0.087959999999999997, + 311752, + 312000, + 1717383081.668576, + 7945479380773989 + ], + "child_modules": {}, + "nMops": 1014, + "Compiled": "Yes", + "Compiled Times": 29, + "nQuads": 265, + "nRouts": 46 + }, + "sirv_gnrl_ltch": { + "end_perf": [ + 0.67983698844909668, + 0.58284000000000002, + 0.088822999999999999, + 311752, + 312000, + 7945479412392495, + 73014444033, + 0 + ], + "start_perf": [ + 0.67896604537963867, + 0.58209500000000003, + 0.088700000000000001, + 311752, + 312000, + 1717383081.6769791, + 7945479409399198 + ], + "child_modules": {}, + "nMops": 140, + "Compiled": "Yes", + "Compiled Times": 29, + "nQuads": 70, + "nRouts": 18 + }, + "PH2AMP": { + "end_perf": [ + 0.75978302955627441, + 0.66143300000000005, + 0.089922000000000002, + 311752, + 312000, + 7945479684765023, + 176093659137, + 0 + ], + "start_perf": [ + 0.75067901611328125, + 0.65334700000000001, + 0.088932999999999998, + 311752, + 312000, + 1717383081.748692, + 7945479653758600 + ], + "child_modules": { + "DW_mult_pipe_0000_0000": 2 + }, + "nMops": 11266, + "Compiled": "Yes", + "Compiled Times": 29, + "nQuads": 4383, + "nRouts": 436 + }, + "dacif": { + "end_perf": [ + 1.0716049671173096, + 0.96137799999999995, + 0.100803, + 311752, + 312000, + 7945480747065901, + 309237645313, + 0 + ], + "start_perf": [ + 1.0603389739990234, + 0.95014900000000002, + 0.100803, + 311752, + 312000, + 1717383082.058352, + 7945480708660828 + ], + "child_modules": {}, + "nMops": 9778, + "Compiled": "Yes", + "Compiled Times": 29, + "nQuads": 3562, + "nRouts": 207 + }, + "qbmcu_regfile_0000": { + "end_perf": [ + 0.80420207977294922, + 0.70272000000000001, + 0.092912999999999996, + 311752, + 312000, + 7945479836072707, + 253403070465, + 0 + ], + "start_perf": [ + 0.79881191253662109, + 0.69734700000000005, + 0.092912999999999996, + 311752, + 312000, + 1717383081.7968249, + 7945479817680535 + ], + "child_modules": {}, + "nMops": 6121, + "Compiled": "Yes", + "Compiled Times": 29, + "nQuads": 2496, + "nRouts": 369 + }, + "dac_regfile": { + "end_perf": [ + 0.68638300895690918, + 0.58929500000000001, + 0.088893, + 311752, + 312000, + 7945479434696006, + 77309411329, + 0 + ], + "start_perf": [ + 0.67986202239990234, + 0.58286199999999999, + 0.088826000000000002, + 311752, + 312000, + 1717383081.677875, + 7945479412448775 + ], + "child_modules": {}, + "nMops": 8460, + "Compiled": "Yes", + "Compiled Times": 29, + "nQuads": 2943, + "nRouts": 367 + }, + "debug_top": { + "end_perf": [ + 0.69351601600646973, + 0.59638999999999998, + 0.088909000000000002, + 311752, + 312000, + 7945479459056231, + 85899345921, + 0 + ], + "start_perf": [ + 0.68640899658203125, + 0.58931800000000001, + 0.088897000000000004, + 311752, + 312000, + 1717383081.684422, + 7945479434755956 + ], + "child_modules": { + "tsdn28hpcpuhdb128x128m4mw_170a": 2, + "sram_if_0000": 1 + }, + "nMops": 8140, + "Compiled": "Yes", + "Compiled Times": 29, + "nQuads": 2296, + "nRouts": 305 + }, + "mcu_regfile": { + "end_perf": [ + 0.77332592010498047, + 0.67399100000000001, + 0.090864, + 311752, + 312000, + 7945479730933024, + 197568495617, + 0 + ], + "start_perf": [ + 0.75981402397155762, + 0.66145900000000002, + 0.089926000000000006, + 311752, + 312000, + 1717383081.757827, + 7945479684825458 + ], + "child_modules": {}, + "nMops": 20092, + "Compiled": "Yes", + "Compiled Times": 29, + "nQuads": 5930, + "nRouts": 759 + }, + "thermo2binary_top": { + "end_perf": [ + 1.2766680717468262, + 1.154795, + 0.111786, + 311752, + 312000, + 7945481445636066, + 416611827713, + 0 + ], + "start_perf": [ + 1.2742760181427002, + 1.1524449999999999, + 0.111752, + 311752, + 312000, + 1717383082.272289, + 7945481437456821 + ], + "child_modules": {}, + "nMops": 5005, + "Compiled": "Yes", + "Compiled Times": 29, + "nQuads": 702, + "nRouts": 48 + }, + "qbmcu_busdecoder": { + "end_perf": [ + 0.77458000183105469, + 0.67421299999999995, + 0.091892000000000001, + 311752, + 312000, + 7945479735162765, + 201863462913, + 0 + ], + "start_perf": [ + 0.77336692810058594, + 0.67402799999999996, + 0.090868000000000004, + 311752, + 312000, + 1717383081.7713799, + 7945479730998182 + ], + "child_modules": {}, + "nMops": 1029, + "Compiled": "Yes", + "Compiled Times": 29, + "nQuads": 240, + "nRouts": 35 + }, + "xy_dsp": { + "end_perf": [ + 1.1286110877990723, + 1.0171870000000001, + 0.10181800000000001, + 311752, + 312000, + 7945480941281105, + 313532612609, + 0 + ], + "start_perf": [ + 1.0716419219970703, + 0.96141600000000005, + 0.100803, + 311752, + 312000, + 1717383082.0696549, + 7945480747139171 + ], + "child_modules": { + "DUC4": 2, + "DW_mult_pipe_0000_0002": 32, + "dacif": 1, + "PH2AMP": 16 + }, + "nMops": 66952, + "Compiled": "Yes", + "Compiled Times": 29, + "nQuads": 18346, + "nRouts": 1450 + }, + "qbmcu": { + "end_perf": [ + 0.79783487319946289, + 0.696488, + 0.092798000000000005, + 311752, + 312000, + 7945479814434100, + 206158430209, + 0 + ], + "start_perf": [ + 0.77460694313049316, + 0.67423599999999995, + 0.091895000000000004, + 311752, + 312000, + 1717383081.77262, + 7945479735220209 + ], + "child_modules": { + "qbmcu_datalatch": 4, + "qbmcu_regfile_0000": 1 + }, + "nMops": 32265, + "Compiled": "Yes", + "Compiled Times": 29, + "nQuads": 9292, + "nRouts": 1118 + }, + "rst_gen_unit": { + "end_perf": [ + 0.80569601058959961, + 0.70420799999999995, + 0.092912999999999996, + 311752, + 312000, + 7945479841158397, + 261993005057, + 0 + ], + "start_perf": [ + 0.80423092842102051, + 0.70274899999999996, + 0.092912999999999996, + 311752, + 312000, + 1717383081.8022439, + 7945479836145707 + ], + "child_modules": {}, + "nMops": 1001, + "Compiled": "Yes", + "Compiled Times": 29, + "nQuads": 484, + "nRouts": 89 + }, + "spi_slave": { + "end_perf": [ + 0.85709190368652344, + 0.75353800000000004, + 0.094815999999999998, + 311752, + 312000, + 7945480016296216, + 279172874241, + 0 + ], + "start_perf": [ + 0.80572009086608887, + 0.704233, + 0.092912999999999996, + 311752, + 312000, + 1717383081.8037331, + 7945479841215461 + ], + "child_modules": {}, + "nMops": 25852, + "Compiled": "Yes", + "Compiled Times": 29, + "nQuads": 9670, + "nRouts": 984 + }, + "system_regfile": { + "end_perf": [ + 0.86609888076782227, + 0.76251100000000005, + 0.094821000000000003, + 311752, + 312000, + 7945480046948320, + 292057776129, + 0 + ], + "start_perf": [ + 0.85714101791381836, + 0.75358199999999997, + 0.094821000000000003, + 311752, + 312000, + 1717383081.855154, + 7945480016394642 + ], + "child_modules": {}, + "nMops": 10379, + "Compiled": "Yes", + "Compiled Times": 29, + "nQuads": 3984, + "nRouts": 508 + }, + "channel_top": { + "end_perf": [ + 0.96209406852722168, + 0.85422500000000001, + 0.098794000000000007, + 311752, + 312000, + 7945480374013926, + 296352743425, + 0 + ], + "start_perf": [ + 0.86612892150878906, + 0.76254100000000002, + 0.094821000000000003, + 311752, + 312000, + 1717383081.8641419, + 7945480047017792 + ], + "child_modules": { + "modout_mux": 1, + "tsdn28hpcpuhdb4096x32m4mw_170a": 6, + "DW_mult_pipe_0000_0002": 6, + "xy_dsp": 1, + "param_lut_0002": 2, + "qbmcu": 1, + "qbmcu_busdecoder": 1, + "mcu_regfile": 1, + "dac_regfile": 1, + "PH2AMP": 1, + "tsdn28hpcpuhdb64x32m4mw_170a_Int_Array": 1, + "ctrl_regfile": 1 + }, + "nMops": 77460, + "Compiled": "Yes", + "Compiled Times": 29, + "nQuads": 24992, + "nRouts": 1481 + }, + "DUC_HB3": { + "end_perf": [ + 1.1522030830383301, + 1.0387489999999999, + 0.10377500000000001, + 311752, + 312000, + 7945481021625011, + 335007449089, + 0 + ], + "start_perf": [ + 1.1421949863433838, + 1.0307249999999999, + 0.101822, + 311752, + 312000, + 1717383082.140208, + 7945480987494670 + ], + "child_modules": {}, + "nMops": 7360, + "Compiled": "Yes", + "Compiled Times": 29, + "nQuads": 1886, + "nRouts": 107 + }, + "TB": { + "end_perf": [ + 1.2668659687042236, + 1.1480859999999999, + 0.108724, + 311752, + 312000, + 7945481412275128, + 382252089345, + 0 + ], + "start_perf": [ + 1.2312650680541992, + 1.1128439999999999, + 0.10849, + 311752, + 312000, + 1717383082.2292781, + 7945481290930002 + ], + "child_modules": { + "spi_if": 1, + "thermo2binary_top": 16, + "xyz_chip_top": 1 + }, + "nMops": 21941, + "Compiled": "Yes", + "Compiled Times": 29, + "nQuads": 7467, + "nRouts": 706 + }, + "DUC_HB4": { + "end_perf": [ + 1.1608960628509521, + 1.046354, + 0.104835, + 311752, + 312000, + 7945481051236719, + 343597383681, + 0 + ], + "start_perf": [ + 1.1522378921508789, + 1.038781, + 0.103778, + 311752, + 312000, + 1717383082.1502509, + 7945481021708724 + ], + "child_modules": {}, + "nMops": 6164, + "Compiled": "Yes", + "Compiled Times": 29, + "nQuads": 1606, + "nRouts": 91 + }, + "DUC4": { + "end_perf": [ + 1.2197639942169189, + 1.103145, + 0.106723, + 311752, + 312000, + 7945481251815979, + 352187318273, + 0 + ], + "start_perf": [ + 1.1609289646148682, + 1.046384, + 0.104838, + 311752, + 312000, + 1717383082.158942, + 7945481051315112 + ], + "child_modules": { + "DUC_HB4": 8, + "DUC_HB2": 2, + "DUC_HB3": 4 + }, + "nMops": 55084, + "Compiled": "Yes", + "Compiled Times": 29, + "nQuads": 18928, + "nRouts": 1019 + }, + "DAC_DEM": { + "end_perf": [ + 1.2297320365905762, + 1.112088, + 0.10771699999999999, + 311752, + 312000, + 7945481285757427, + 369367187457, + 0 + ], + "start_perf": [ + 1.2198069095611572, + 1.1031850000000001, + 0.106727, + 311752, + 312000, + 1717383082.2178199, + 7945481251895771 + ], + "child_modules": {}, + "nMops": 7624, + "Compiled": "Yes", + "Compiled Times": 29, + "nQuads": 2444, + "nRouts": 62 + }, + "DAC_DEM_16": { + "end_perf": [ + 1.2305400371551514, + 1.112822, + 0.107789, + 311752, + 312000, + 7945481288483720, + 373662154753, + 0 + ], + "start_perf": [ + 1.2297649383544922, + 1.1121190000000001, + 0.10772, + 311752, + 312000, + 1717383082.227778, + 7945481285825623 + ], + "child_modules": { + "DAC_DEM": 16 + }, + "nMops": 0, + "Compiled": "Yes", + "Compiled Times": 29, + "nQuads": 0, + "nRouts": 5 + }, + "DW_mult_pipe_0000_0000": { + "end_perf": [ + 1.2695400714874268, + 1.1496960000000001, + 0.10978, + 311752, + 312000, + 7945481421354645, + 386547056641, + 0 + ], + "start_perf": [ + 1.2669050693511963, + 1.1481220000000001, + 0.108727, + 311752, + 312000, + 1717383082.2649181, + 7945481412370561 + ], + "child_modules": {}, + "nMops": 2733, + "Compiled": "Yes", + "Compiled Times": 29, + "nQuads": 711, + "nRouts": 55 + }, + "DW_mult_pipe_0000_0002": { + "end_perf": [ + 1.2725610733032227, + 1.151707, + 0.110779, + 311752, + 312000, + 7945481431650277, + 386547056641, + 0 + ], + "start_perf": [ + 1.2695660591125488, + 1.1497200000000001, + 0.109782, + 311752, + 312000, + 1717383082.2675791, + 7945481421411980 + ], + "child_modules": {}, + "nMops": 2596, + "Compiled": "Yes", + "Compiled Times": 29, + "nQuads": 711, + "nRouts": 55 + }, + "DW01_addsub": { + "end_perf": [ + 1.273827075958252, + 1.152037, + 0.11171200000000001, + 311752, + 312000, + 7945481435955488, + 390842023937, + 0 + ], + "start_perf": [ + 1.2725899219512939, + 1.151735, + 0.11078200000000001, + 311752, + 312000, + 1717383082.2706029, + 7945481431714557 + ], + "child_modules": {}, + "nMops": 1162, + "Compiled": "Yes", + "Compiled Times": 29, + "nQuads": 215, + "nRouts": 25 + } + }, + "ObjArchives": [ + { + "archive": "archive.28/_58486_archive_1.a", + "objects": [ + [ + "QyjH7_d.o", + 86582 + ], + [ + "eAsJz_d.o", + 308244 + ], + [ + "xFWdC_d.o", + 466884 + ], + [ + "VHUBa_d.o", + 655492 + ], + [ + "SMgga_d.o", + 62042 + ], + [ + "U33JQ_d.o", + 380142 + ], + [ + "ksFw4_d.o", + 60820 + ], + [ + "Rdd8k_d.o", + 44058 + ], + [ + "zwWSN_d.o", + 39014 + ], + [ + "cwtAY_d.o", + 302374 + ], + [ + "brTVz_d.o", + 47090 + ], + [ + "gcyA4_d.o", + 8402 + ], + [ + "WqW9L_d.o", + 7116 + ], + [ + "sH4Fc_d.o", + 266644 + ], + [ + "amcQwB.o", + 159704 + ] + ], + "size": 2894608 + } + ], + "reusePaths": { + "KysYq_d": { + "icPath": "csrc" + }, + "amcQw_d": { + "icPath": "csrc" + }, + "reYIK_d": { + "icPath": "csrc" + }, + "gNaPt_d": { + "icPath": "csrc" + }, + "d6TPd_d": { + "icPath": "csrc" + }, + "NABmh_d": { + "icPath": "csrc" + }, + "HWLgR_d": { + "icPath": "csrc" + }, + "nJgqZ_d": { + "icPath": "csrc" + }, + "eFLuy_d": { + "icPath": "csrc" + }, + "mLA3J_d": { + "icPath": "csrc" + }, + "JweIx_d": { + "icPath": "csrc" + }, + "jEu9i_d": { + "icPath": "csrc" + }, + "nJN5E_d": { + "icPath": "csrc" + }, + "Hit7c_d": { + "icPath": "csrc" + }, + "BM4bj_d": { + "icPath": "csrc" + }, + "LR0zI_d": { + "icPath": "csrc" + }, + "MsCBG_d": { + "icPath": "csrc" + }, + "UTi0b_d": { + "icPath": "csrc" + }, + "rShyv_d": { + "icPath": "csrc" + }, + "ay4xz_d": { + "icPath": "csrc" + }, + "iYIEc_d": { + "icPath": "csrc" + }, + "jAiwN_d": { + "icPath": "csrc" + }, + "xnbfb_d": { + "icPath": "csrc" + }, + "anuMN_d": { + "icPath": "csrc" + }, + "W3x1b_d": { + "icPath": "csrc" + }, + "HNRiG_d": { + "icPath": "csrc" + }, + "SiiVi_d": { + "icPath": "csrc" + }, + "N7Gsb_d": { + "icPath": "csrc" + }, + "IHYdB_d": { + "icPath": "csrc" + } + }, + "CompUnits": { + "QyjH7_d": { + "out": "QyjH7_d.o", + "mod": "_vcs_unit__3598111382", + "bytes": 86582, + "checksum": 0, + "text": 14451, + "cls": 14127, + "mode": 4, + "archive": "archive.28/_58486_archive_1.a" + }, + "brTVz_d": { + "out": "brTVz_d.o", + "mod": "DAC_DEM", + "bytes": 47090, + "checksum": 0, + "text": 32587, + "mode": 4, + "archive": "archive.28/_58486_archive_1.a" + }, + "eAsJz_d": { + "out": "eAsJz_d.o", + "mod": "spi_slave", + "bytes": 308244, + "checksum": 0, + "text": 188255, + "mode": 4, + "archive": "archive.28/_58486_archive_1.a" + }, + "xFWdC_d": { + "out": "xFWdC_d.o", + "mod": "channel_top", + "bytes": 466884, + "checksum": 0, + "text": 301591, + "mode": 4, + "archive": "archive.28/_58486_archive_1.a" + }, + "SMgga_d": { + "out": "SMgga_d.o", + "mod": "dacif", + "bytes": 62042, + "checksum": 0, + "text": 42091, + "mode": 4, + "archive": "archive.28/_58486_archive_1.a" + }, + "VHUBa_d": { + "out": "VHUBa_d.o", + "mod": "xyz_chip_top", + "bytes": 655492, + "checksum": 0, + "text": 386632, + "mode": 4, + "archive": "archive.28/_58486_archive_1.a" + }, + "U33JQ_d": { + "out": "U33JQ_d.o", + "mod": "xy_dsp", + "bytes": 380142, + "checksum": 0, + "text": 244551, + "mode": 4, + "archive": "archive.28/_58486_archive_1.a" + }, + "WqW9L_d": { + "out": "WqW9L_d.o", + "mod": "DAC_DEM_4", + "bytes": 7116, + "checksum": 0, + "text": 305, + "mode": 4, + "archive": "archive.28/_58486_archive_1.a" + }, + "ksFw4_d": { + "out": "ksFw4_d.o", + "mod": "DUC_HB2", + "bytes": 60820, + "checksum": 0, + "text": 41471, + "mode": 4, + "archive": "archive.28/_58486_archive_1.a" + }, + "Rdd8k_d": { + "out": "Rdd8k_d.o", + "mod": "DUC_HB3", + "bytes": 44058, + "checksum": 0, + "text": 27407, + "mode": 4, + "archive": "archive.28/_58486_archive_1.a" + }, + "zwWSN_d": { + "out": "zwWSN_d.o", + "mod": "DUC_HB4", + "bytes": 39014, + "checksum": 0, + "text": 23235, + "mode": 4, + "archive": "archive.28/_58486_archive_1.a" + }, + "cwtAY_d": { + "out": "cwtAY_d.o", + "mod": "DUC4", + "bytes": 302374, + "checksum": 0, + "text": 216540, + "mode": 4, + "archive": "archive.28/_58486_archive_1.a" + }, + "gcyA4_d": { + "out": "gcyA4_d.o", + "mod": "DAC_DEM_16", + "bytes": 8402, + "checksum": 0, + "text": 221, + "mode": 4, + "archive": "archive.28/_58486_archive_1.a" + }, + "sH4Fc_d": { + "out": "sH4Fc_d.o", + "mod": "TB", + "bytes": 266644, + "checksum": 0, + "text": 138647, + "mode": 4, + "archive": "archive.28/_58486_archive_1.a" + } + }, + "stat": { + "ru_self_end": { + "ru_utime_sec": 1.157543, + "ru_stime_sec": 0.112828, + "ru_majflt": 0, + "ru_maxrss_kb": 109924, + "ru_minflt": 45272, + "ru_nvcsw": 31, + "ru_nivcsw": 27 + }, + "ru_childs_end": { + "ru_utime_sec": 0.0060819999999999997, + "ru_stime_sec": 0.020500000000000001, + "ru_majflt": 0, + "ru_maxrss_kb": 40548, + "ru_minflt": 10699, + "ru_nvcsw": 26, + "ru_nivcsw": 24 + }, + "cpu_cycles_end": 7945481458547003, + "peak_mem_kb": 312000 + } +} \ No newline at end of file diff --git a/tb/chip_top/csrc/filelist b/tb/chip_top/csrc/filelist new file mode 100644 index 0000000..988c130 --- /dev/null +++ b/tb/chip_top/csrc/filelist @@ -0,0 +1,31 @@ + + +AR=ar +DOTLIBS=/home/synopsys/vcs/O-2018.09-SP2/linux64/lib/libzerosoft_rt_stubs.so /home/synopsys/vcs/O-2018.09-SP2/linux64/lib/libvirsim.so /home/synopsys/vcs/O-2018.09-SP2/linux64/lib/liberrorinf.so /home/synopsys/vcs/O-2018.09-SP2/linux64/lib/libsnpsmalloc.so /home/synopsys/vcs/O-2018.09-SP2/linux64/lib/libvfs.so /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/pli.a + +# This file is automatically generated by VCS. Any changes you make to it +# will be overwritten the next time VCS is run +VCS_LIBEXT= +XTRN_OBJS= + +DPI_WRAPPER_OBJS = +DPI_STUB_OBJS = +# filelist.dpi will populate DPI_WRAPPER_OBJS and DPI_STUB_OBJS +include filelist.dpi +PLI_STUB_OBJS = +include filelist.pli + +include filelist.hsopt + +include filelist.cu + +VCS_INCR_OBJS= + + +AUGDIR= +AUG_LDFLAGS= +SHARED_OBJ_SO= + + + +VLOG_OBJS= $(VCS_OBJS) $(CU_OBJS) $(VCS_ARC0) $(XTRN_OBJS) $(DPI_WRAPPER_OBJS) $(VCS_INCR_OBJS) $(SHARED_OBJ_SO) $(HSOPT_OBJS) diff --git a/tb/chip_top/csrc/filelist.cu b/tb/chip_top/csrc/filelist.cu new file mode 100644 index 0000000..ccd191e --- /dev/null +++ b/tb/chip_top/csrc/filelist.cu @@ -0,0 +1,50 @@ +PIC_LD=ld + +ARCHIVE_OBJS= +ARCHIVE_OBJS += _58486_archive_1.so +_58486_archive_1.so : archive.28/_58486_archive_1.a + @$(AR) -s $< + @$(PIC_LD) -shared -Bsymbolic -o .//../simv.daidir//_58486_archive_1.so --whole-archive $< --no-whole-archive + @rm -f $@ + @ln -sf .//../simv.daidir//_58486_archive_1.so $@ + + +ARCHIVE_OBJS += _prev_archive_1.so +_prev_archive_1.so : archive.28/_prev_archive_1.a + @$(AR) -s $< + @$(PIC_LD) -shared -Bsymbolic -o .//../simv.daidir//_prev_archive_1.so --whole-archive $< --no-whole-archive + @rm -f $@ + @ln -sf .//../simv.daidir//_prev_archive_1.so $@ + + + +VCS_ARC0 =_csrc0.so + +VCS_OBJS0 =objs/amcQw_d.o + + +O0_OBJS = + +$(O0_OBJS) : %.o: %.c + $(CC_CG) $(CFLAGS_O0) -c -o $@ $< + + +%.o: %.c + $(CC_CG) $(CFLAGS_CG) -c -o $@ $< + +$(VCS_ARC0) : $(VCS_OBJS0) + $(PIC_LD) -shared -Bsymbolic -o .//../simv.daidir//$(VCS_ARC0) $(VCS_OBJS0) + rm -f $(VCS_ARC0) + @ln -sf .//../simv.daidir//$(VCS_ARC0) $(VCS_ARC0) + +CU_UDP_OBJS = \ + + +CU_LVL_OBJS = \ +SIM_l.o + +MAIN_OBJS = \ + + +CU_OBJS = $(MAIN_OBJS) $(ARCHIVE_OBJS) $(VCS_ARC0) $(CU_UDP_OBJS) $(CU_LVL_OBJS) + diff --git a/tb/chip_top/csrc/filelist.dpi b/tb/chip_top/csrc/filelist.dpi new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/filelist.hsopt b/tb/chip_top/csrc/filelist.hsopt new file mode 100644 index 0000000..9287244 --- /dev/null +++ b/tb/chip_top/csrc/filelist.hsopt @@ -0,0 +1,13 @@ +rmapats_mop.o: rmapats.m + @/home/synopsys/vcs/O-2018.09-SP2/linux64/bin/cgmop1 -tls_initexe -pic -gen_obj rmapats.m rmapats_mop.o; rm -f rmapats.m; touch rmapats.m; touch rmapats_mop.o + +rmapats.o: rmapats.c + @$(CC_CG) $(CFLAGS_CG) -c -fPIC -x c -o rmapats.o rmapats.c +rmapats%.o: rmapats%.c + @$(CC_CG) $(CFLAGS_CG) -c -fPIC -x c -o $@ $< +rmar.o: rmar.c + @$(CC_CG) $(CFLAGS_CG) -c -fPIC -x c -o rmar.o rmar.c +rmar%.o: rmar%.c + @$(CC_CG) $(CFLAGS_CG) -c -fPIC -x c -o $@ $< + +include filelist.hsopt.objs diff --git a/tb/chip_top/csrc/filelist.hsopt.llvm2_0.objs b/tb/chip_top/csrc/filelist.hsopt.llvm2_0.objs new file mode 100644 index 0000000..4c31419 --- /dev/null +++ b/tb/chip_top/csrc/filelist.hsopt.llvm2_0.objs @@ -0,0 +1 @@ +LLVM_OBJS += rmar_llvm_0_1.o rmar_llvm_0_0.o diff --git a/tb/chip_top/csrc/filelist.hsopt.objs b/tb/chip_top/csrc/filelist.hsopt.objs new file mode 100644 index 0000000..f40e57c --- /dev/null +++ b/tb/chip_top/csrc/filelist.hsopt.objs @@ -0,0 +1,7 @@ +HSOPT_OBJS +=rmapats_mop.o \ + rmapats.o \ + rmar.o rmar_nd.o + +include filelist.hsopt.llvm2_0.objs +HSOPT_OBJS += $(LLVM_OBJS) + diff --git a/tb/chip_top/csrc/filelist.pli b/tb/chip_top/csrc/filelist.pli new file mode 100644 index 0000000..e3714f3 --- /dev/null +++ b/tb/chip_top/csrc/filelist.pli @@ -0,0 +1,4 @@ +PLI_STUB_OBJS += _vcs_pli_stub_.o +_vcs_pli_stub_.o: _vcs_pli_stub_.c + @$(CC) -I/home/synopsys/vcs/O-2018.09-SP2/include -pipe -fPIC -I/home/synopsys/vcs/O-2018.09-SP2/include -fPIC -c -o _vcs_pli_stub_.o _vcs_pli_stub_.c + @strip -g _vcs_pli_stub_.o diff --git a/tb/chip_top/csrc/hsim/hsim.sdb b/tb/chip_top/csrc/hsim/hsim.sdb new file mode 100644 index 0000000..a8223a0 Binary files /dev/null and b/tb/chip_top/csrc/hsim/hsim.sdb differ diff --git a/tb/chip_top/csrc/import_dpic.h b/tb/chip_top/csrc/import_dpic.h new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/objs/amcQw_d.o b/tb/chip_top/csrc/objs/amcQw_d.o new file mode 100644 index 0000000..e62dc35 Binary files /dev/null and b/tb/chip_top/csrc/objs/amcQw_d.o differ diff --git a/tb/chip_top/csrc/pre.cgincr.sdb b/tb/chip_top/csrc/pre.cgincr.sdb new file mode 100644 index 0000000..2b3f825 Binary files /dev/null and b/tb/chip_top/csrc/pre.cgincr.sdb differ diff --git a/tb/chip_top/csrc/product_timestamp b/tb/chip_top/csrc/product_timestamp new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/rmapats.c b/tb/chip_top/csrc/rmapats.c new file mode 100644 index 0000000..0c43907 --- /dev/null +++ b/tb/chip_top/csrc/rmapats.c @@ -0,0 +1,43 @@ +// file = 0; split type = patterns; threshold = 100000; total count = 0. +#include +#include +#include +#include "rmapats.h" + +void hsG_0__0 (struct dummyq_struct * I1289, EBLK * I1283, U I685); +void hsG_0__0 (struct dummyq_struct * I1289, EBLK * I1283, U I685) +{ + U I1547; + U I1548; + U I1549; + struct futq * I1550; + struct dummyq_struct * pQ = I1289; + I1547 = ((U )vcs_clocks) + I685; + I1549 = I1547 & ((1 << fHashTableSize) - 1); + I1283->I727 = (EBLK *)(-1); + I1283->I731 = I1547; + if (I1547 < (U )vcs_clocks) { + I1548 = ((U *)&vcs_clocks)[1]; + sched_millenium(pQ, I1283, I1548 + 1, I1547); + } + else if ((peblkFutQ1Head != ((void *)0)) && (I685 == 1)) { + I1283->I733 = (struct eblk *)peblkFutQ1Tail; + peblkFutQ1Tail->I727 = I1283; + peblkFutQ1Tail = I1283; + } + else if ((I1550 = pQ->I1190[I1549].I745)) { + I1283->I733 = (struct eblk *)I1550->I744; + I1550->I744->I727 = (RP )I1283; + I1550->I744 = (RmaEblk *)I1283; + } + else { + sched_hsopt(pQ, I1283, I1547); + } +} +#ifdef __cplusplus +extern "C" { +#endif +void SinitHsimPats(void); +#ifdef __cplusplus +} +#endif diff --git a/tb/chip_top/csrc/rmapats.h b/tb/chip_top/csrc/rmapats.h new file mode 100644 index 0000000..4a142a0 --- /dev/null +++ b/tb/chip_top/csrc/rmapats.h @@ -0,0 +1,2702 @@ +#ifndef __DO_RMAHDR_ +#define __DO_RMAHDR_ + +#ifdef __cplusplus + extern "C" { +#endif + +#define VCS_RTLIB_TLS_MODEL __attribute__((tls_model("initial-exec"))) + +typedef unsigned long UP; +typedef unsigned U; +typedef unsigned char UB; +typedef unsigned char scalar; +typedef struct vec32 vec32; +typedef unsigned short US; +typedef unsigned char SVAL; +typedef unsigned char TYPEB; +typedef struct qird QIRD; +typedef unsigned char UST_e; +typedef unsigned uscope_t; +typedef U NumLibs_t; +struct vec32 { + U I1; + U I2; +}; +typedef unsigned long RP; +typedef unsigned long RO; +typedef unsigned long long ULL; +typedef U GateCount; +typedef U NodeCount; +typedef unsigned short HsimEdge; +typedef unsigned char HsimExprChar; +typedef struct { + U I706; + RP I707; +} RmaReceiveClock1; +typedef NodeCount FlatNodeNum; +typedef U InstNum; +typedef unsigned ProcessNum; +typedef unsigned long long TimeStamp64; +typedef unsigned long long TimeStamp; +typedef enum { + PD_SING = 0, + PD_RF = 1, + PD_PLSE = 2, + PD_PLSE_RF = 3, + PD_NULL = 4 +} PD_e; +typedef TimeStamp RmaTimeStamp; +typedef TimeStamp64 RmaTimeStamp64; +typedef struct { + int * I708; + int * I709; + int I710; + union { + long long enumDesc; + long long classId; + } I711; +} TypeData; +struct etype { + U I586 :8; + U I587; + U I588; + U I589 :1; + U I590 :1; + U I591 :1; + U I592 :1; + U I593 :1; + U I594 :1; + U I595 :1; + U I596 :1; + U I597 :1; + U I598 :4; + U I599 :1; + U I600 :1; + U I601 :1; + U I602 :1; + U I603 :1; + U I604 :1; + U I605 :1; + U I606 :1; + U I607 :2; + U I608 :1; + U I609 :2; + U I610 :1; + U I611 :1; + U I612 :1; + U I613 :1; + U I614 :1; + U I615 :1; + TypeData * I616; + U I617; + U I618; + U I619 :1; + U I620 :1; + U I621 :1; + U I622 :1; + U I623 :2; + U I624 :2; + U I625 :1; + U I626 :1; + U I627 :1; + U I628 :1; + U I629 :1; + U I630 :1; + U I631 :1; + U I632 :1; + U I633 :1; + U I634 :1; + U I635 :1; + U I636 :13; +}; +typedef union { + double I718; + unsigned long long I719; + unsigned I720[2]; +} rma_clock_struct; +typedef struct eblk EBLK; +typedef int (* E_fn)(void); +typedef struct eblk { + struct eblk * I727; + E_fn I728; + struct iptmpl * I729; + unsigned I731; + unsigned I732; + struct eblk * I733; +} eblk_struct; +typedef struct { + RP I727; + RP I728; + RP I729; + unsigned I731; + unsigned I732; + RP I733; +} RmaEblk; +typedef struct { + RP I727; + RP I728; + RP I729; + unsigned I731; + unsigned I732; + RP I733; + unsigned val; +} RmaEblklq; +typedef union { + double I718; + unsigned long long I719; + unsigned I720[2]; +} clock_struct; +typedef clock_struct RmaClockStruct; +typedef struct RmaRetain_t RmaRetain; +struct RmaRetain_t { + RP I769; + RmaEblk I726; + U I771; + US I772 :1; + US I773 :4; + US I181 :2; + US state :2; + US I775 :1; + US I776 :2; + US I777 :2; + US fHsim :1; + US I569 :1; + scalar newval; + scalar I780; + RP I781; +}; +struct retain_t { + struct retain_t * I769; + EBLK I726; + U I771; + US I772 :1; + US I773 :4; + US I181 :2; + US state :2; + US I775 :1; + US I776 :2; + US I777 :2; + US fHsim :1; + US I778 :1; + scalar newval; + scalar I780; + void * I781; +}; +typedef struct MPSched MPS; +typedef struct RmaMPSched RmaMps; +struct MPSched { + MPS * I760; + scalar I761; + scalar I762; + scalar I763; + scalar fHsim :1; + scalar I181 :6; + U I765; + EBLK I766; + void * I767; + UP I768[1]; +}; +struct RmaMPSched { + RP I760; + scalar I761; + scalar I762; + scalar I763; + scalar fHsim :1; + scalar I181 :6; + U I765; + RmaEblk I766; + RP I767; + RP I768[1]; +}; +typedef struct RmaMPSchedPulse RmaMpsp; +struct RmaMPSchedPulse { + RP I760; + scalar I761; + scalar I762; + scalar I763; + scalar I181; + U I765; + RmaEblk I766; + scalar I777; + scalar I786; + scalar I787; + scalar I788; + U I789; + RmaClockStruct I790; + RmaClockStruct I791; + U state; + U I792; + RP I729; + RP I793; + RP I794; + RP I768[1]; +}; +typedef struct MPItem MPI; +struct MPItem { + U * I796; + void * I797; +}; +typedef struct { + RmaEblk I726; + RP I798; + scalar I799; + scalar I777; + scalar I800; +} RmaTransEventHdr; +typedef struct RmaMPSchedPulseNewCsdf RmaMpspNewCsdf; +struct RmaMPSchedPulseNewCsdf { + RP I760; + scalar I761; + scalar I762; + scalar I763; + scalar fHsim :1; + scalar I181 :6; + U I765; + RmaEblk I766; + scalar I777; + scalar I786; + scalar I787; + scalar I788; + U state :4; + U I802 :28; + RmaClockStruct I790; + RmaClockStruct I791; + RP I803; + RP I729; + RP I804; + RP I768[1]; +}; +typedef struct red_t { + U I805; + U I806; + U I685; +} RED; +typedef struct predd { + PD_e I181; + RED I807[0]; +} PREDD; +union rhs_value { + vec32 I808; + scalar I799; + vec32 * I777; + double I809; + U I810; +}; +typedef struct nbs_t { + struct nbs_t * I811; + struct nbs_t * I813; + void (* I814)(struct nbs_t * I781); + U I815 :1; + U I816 :1; + U I817 :1; + U I818 :1; + U I819 :1; + U I820 :1; + U I821 :26; + U I822; + void * I823; + union rhs_value I824; + vec32 I718; + union { + struct nbs_t * first; + struct nbs_t * last; + } I826; +} NBS; +typedef struct { + RP I827; + RP I793; + RP I729; + RP I794; + RmaEblk I726; + RmaEblk I828; + RP I829; + scalar I799; + scalar I777; + char state; + uscope_t I830; + U I831; + RP I832; + scalar I786; + scalar I787; + scalar I788; + RmaClockStruct I790; + RmaClockStruct I791; + RP I767; +} RmaPulse; +typedef enum { + QIRDModuleC = 1, + QIRDSVPackageC = 2, + QIRDSpiceModuleC = 3 +} QIRDModuleType; +typedef struct { + U I836 :1; + U I837 :1; + U I838 :1; + U I839 :1; + U I840 :1; + U I841 :1; + U I842 :1; + U I843 :1; + U I844 :1; + U I845 :1; + U I846 :1; + U I847 :1; + U I848 :1; + U I849 :1; + U I850 :1; + U I851 :1; + U I852 :1; + U I853 :1; + QIRDModuleType I854 :2; + U I855 :1; + U I856 :1; + U I857 :1; + U I858 :1; + U I859 :1; + U I860 :1; + U I861 :1; + U I862 :1; + U I863 :1; + U I864 :1; + U I865 :1; + U I866 :1; + U I867 :1; + U I868 :1; + U I869 :1; + U I870 :1; + U I871 :1; + U I872 :1; + U I873 :1; + U I874 :1; +} BitFlags; +struct qird { + US I4; + US I5; + U I6; + U I7; + char * I8; + char * I9; + U * I10; + char * I11; + char * I12; + U I13; + U I14; + struct vcd_rt * I15; + U I17; + struct _vcdOffset_rt * I18; + U I20; + U I21; + U * I22; + U * I23; + void * I24; + void * I25; + U I26; + int I27; + UP I28; + U I29; + U I30; + U I31; + UP I32; + U * I33; + UP I34; + U I35; + BitFlags I36; + U I37; + U I38; + U I39; + U I40; + U I41; + U * I42; + U I43; + U * I44; + U I45; + U I46; + U I47; + U I48; + U I49; + U I50; + U I51; + U * I52; + U * I53; + U I54; + U I55; + U * I56; + U I57; + U * I58; + U I59; + U I60; + U I61; + U I62; + U * I63; + U I64; + U * I65; + U I66; + U I67; + U I68; + U I69; + U I70; + U I71; + U * I72; + char * I73; + U I74; + U I75; + U I76; + U I77; + U I78; + U * I79; + U I80; + U I81; + U I82; + UP * I83; + U I84; + U I85; + U I86; + U I87; + U I88; + U I89; + U * I90; + U I91; + U I92; + U * I93; + U * I94; + U * I95; + U * I96; + U * I97; + U I98; + U I99; + struct taskInfo * I100; + U I102; + U I103; + U I104; + int * I105; + U * I106; + UP * I107; + U * I108; + U I109; + U I110; + U I111; + U I112; + U I113; + struct qrefer * I114; + U * I116; + unsigned * I117; + void * I118; + U I119; + U I120; + struct classStaticReferData * I121; + U I123; + U * I124; + U I125; + U * I126; + U I127; + struct wakeupInfoStruct * I128; + U I130; + U I131; + U I132; + U * I133; + U I134; + U * I135; + U I136; + U I137; + U I138; + U * I139; + U I140; + U * I141; + U I142; + U I143; + U * I144; + U I145; + U I146; + U * I147; + U * I148; + U * I149; + U I150; + U I151; + U I152; + U I153; + U I154; + struct qrefee * I155; + U * I157; + U I158; + struct qdefrefee * I159; + U * I161; + int (* I162)(void); + char * I163; + U I164; + U I165; + void * I166; + void * I167; + NumLibs_t I168; + char * I169; + U * I170; + U I171; + U I172; + U I173; + U I174; + U I175; + U * I176; + U * I177; + int I178; + struct clock_load * I179; + int I194; + struct clock_data * I195; + int I211; + struct clock_hiconn * I212; + U I216; + U I217; + U I218; + U I219; + U * I220; + U * I221; + U I222; + void * I223; + U I224; + U I225; + UP * I226; + void * I227; + U I228; + UP * I229; + U * I230; + int (* I231)(void); + U * I232; + UP * I233; + U * I234; + U I235 :1; + U I236 :31; + U I237; + U I238; + UP * I239; + U * I240; + U I241 :1; + U I242 :1; + U I243 :1; + U I244 :1; + U I245 :28; + U I246; + U I247; + U I248; + U I249 :31; + U I250 :1; + UP * I251; + UP * I252; + U * I253; + U * I254; + U * I255; + U * I256; + UP * I257; + UP * I258; + UP * I259; + U * I260; + UP * I261; + UP * I262; + UP * I263; + UP * I264; + char * I265; + U I266; + U I267; + U I268; + UP * I269; + U I270; + UP * I271; + UP * I272; + UP * I273; + UP * I274; + UP * I275; + UP * I276; + UP * I277; + UP * I278; + UP * I279; + UP * I280; + UP * I281; + UP * I282; + UP * I283; + UP * I284; + U * I285; + U * I286; + UP * I287; + U I288; + U I289; + U I290; + U I291; + U I292; + U I293; + U I294; + U I295; + char * I296; + U * I297; + U I298; + U I299; + U I300; + U I301; + U I302; + UP * I303; + UP * I304; + UP * I305; + UP * I306; + struct daidirInfo * I307; + struct vcs_tftable * I309; + U I311; + UP * I312; + UP * I313; + U I314; + U I315; + U I316; + UP * I317; + U * I318; + UP * I319; + UP * I320; + struct qird_hil_data * I321; + UP (* I323)(void); + UP (* I324)(void); + UP (* I325)(void); + UP (* I326)(void); + UP (* I327)(void); + int * I328; + int (* I329)(void); + char * I330; + UP * I331; + UP * I332; + UP (* I333)(void); + int (* I334)(void); + int * I335; + int (* I336)(void); + int * I337; + char * I338; + U * I339; + U * I340; + U * I341; + U * I342; + void * I343; + U I344; + void * I345; + U I346; + U I347; + U I348; + U I349; + U I350; + U I351; + char * I352; + UP * I353; + U * I354; + U * I355; + U I356 :15; + U I357 :14; + U I358 :1; + U I359 :1; + U I360 :1; + U I361 :3; + U I362 :1; + U I363 :1; + U I364 :17; + U I365 :3; + U I366 :5; + U I367 :1; + U I368 :1; + U I369; + U I370; + struct scope * I371; + U I373; + U I374; + U I375; + U * I376; + U * I377; + U * I378; + U I379; + U I380; + U I381; + struct pcbt * I382; + U I392; + U I393; + U I394; + U I395; + void * I396; + void * I397; + void * I398; + int I399; + U * I400; + U I401; + U I402; + U I403; + U I404; + U I405; + U I406; + U I407; + void * I408; + UP * I409; + U I410; + U I411; + void * I412; + U I413; + void * I414; + U I415; + void * I416; + U I417; + int (* I418)(void); + int (* I419)(void); + void * I420; + void * I421; + void * I422; + U I423; + U I424; + U I425; + U I426; + U I427; + U I428; + char * I429; + U I430; + U * I431; + U I432; + U * I433; + U I434; + U I435; + U I436; + U I437; + U I438; + U I439; + U * I440; + U I441; + U I442; + U * I443; + U I444; + U I445; + U I446; + U * I447; + char * I448; + U I449; + U I450; + U I451; + U I452; + U * I453; + U * I454; + U I455; + U * I456; + U * I457; + U I458; + U I459; + U I460; + UP * I461; + U I462; + U I463; + U I464; + struct cosim_info * I465; + U I467; + U * I468; + U I469; + void * I470; + U I471; + U * I472; + U I473; + struct hybridSimReferrerData * I474; + U I476; + U * I477; + U I478; + U I479; + U * I480; + U I481; + U * I482; + U I483; + U * I484; + U I485; + U I486; + U I487; + U I488; + U I489; + U I490; + U I491; + U I492; + U I493; + U * I494; + U * I495; + void (* I496)(void); + U * I497; + UP * I498; + struct mhdl_outInfo * I499; + UP * I501; + U I502; + UP * I503; + U I504; + void * I505; + U * I506; + void * I507; + char * I508; + int (* I509)(void); + U * I510; + char * I511; + char * I512; + U I513; + U * I514; + char * I515; + U I516; + struct regInitInfo * I517; + UP * I519; + U * I520; + char * I521; + U I522; + U I523; + U I524; + U I525; + U I526; + U I527; + U I528; + U I529; + UP * I530; + U I531; + U I532; + U I533; + U I534; + UP * I535; + U I536; + UP * I537; + U I538; + U I539; + U I540; + U * I541; + U I542; + U I543; + U I544; + U * I545; + U * I546; + UP * I547; + UP * I548; + void * I549; + UP I550; + void * I551; + void * I552; + void * I553; + void * I554; + void * I555; + UP I556; + U * I557; + U * I558; + void * I559; + U I560 :1; + U I561 :31; + U I562; + U I563; + U I564; + int I565; + U I566 :1; + U I567 :1; + U I568 :1; + U I569 :29; + void * I570; + void * I571; + void * I572; + void * I573; + void * I574; + UP * I575; + U * I576; + U I577; + char * I578; + U * I579; + U * I580; + char * I581; + int * I582; + UP * I583; + struct etype * I584; + U I637; + U I638; + U * I639; + struct etype * I640; + U I641; + U I642; + U I643; + U * I644; + void * I645; + U I646; + U I647; + void * I648; + U I649; + U I650; + U * I651; + U * I652; + char * I653; + U I654; + struct covreg_rt * I655; + U I657; + U I658; + U * I659; + U I660; + U * I661; + U I662; + U I663; + U * I664; +}; +typedef struct pcbt { + U * I384; + UP I385; + U I386; + U I387; + U I388; + U I389; + U I390; + U I391; +} PCBT; +struct iptmpl { + QIRD * I734; + struct vcs_globals_t * I735; + void * I737; + UP I738; + UP I739; + struct iptmpl * I729[2]; +}; +typedef unsigned long long FileOffset; +typedef struct _RmaMultiInputTable { + U I881 :1; + U I882 :1; + U I672 :2; + U I673 :4; + U I674 :5; + U I883 :1; + U I884 :1; + U I885 :1; + U I886 :1; + U I887 :1; + U I888 :1; + U I889; + U I890; + U I203; + U I891; + U I892 :1; + U I893 :31; + union { + U utable; + U edgeInputNum; + } I699; + U I894 :4; + U I895 :4; + U I896 :4; + U I897 :4; + U I898 :4; + U I899 :4; + U I900 :1; + U I901 :1; + U I902 :1; + U I903 :1; + U I904 :5; + HsimExprChar * I905; + UB * I906; + UB * I907; + struct _RmaMultiInputTable * I880; + struct _RmaMultiInputTable * I909; +} RmaMultiInputTable; +typedef struct _HsCgPeriod { + U I955; + U I956; +} HsCgPeriod; +typedef struct { + U I957[2]; + U I958 :1; + U I959 :1; + U I960 :8; + U I961 :8; + U I962 :8; + U I963 :4; + U I964 :1; + U I965 :1; + unsigned long long I966; + unsigned long long I967; + unsigned long long I968; + unsigned long long I969; + unsigned long long I956; + U I955; + U I970; + U I971; + U I972; + U I973; + U I974; + HsCgPeriod * I975[10]; +} HsimSignalMonitor; +typedef struct { + FlatNodeNum I976; + InstNum I977; + U I915; + scalar I978; + UB I979; + UB I980; + UB I981; + UB I982; + UB I983; + UB I984; + U I985; + U I986; + U I987; + U I988; + U I989; + U I990; + U I991; + U I992; + U I993; + HsimSignalMonitor * I994; + RP I995; + RmaTimeStamp64 I996; + U I997; + RmaTimeStamp64 I998; + U I999; + UB I1000; +} HsimNodeRecord; +typedef RP RCICODE; +typedef struct { + RP I1005; + RP I729; +} RmaIbfIp; +typedef struct { + RP I1005; + RP pcode; +} RmaIbfPcode; +typedef struct { + RmaEblk I726; +} RmaEvTriggeredOrSyncLoadCg; +typedef struct { + RO I877; + RP pcode; +} SchedGateFanout; +typedef struct { + RO I877; + RP pcode; + U I936[4]; +} SchedSelectGateFanout; +typedef struct { + RP pcode; + RmaEblklq I726; +} SchedGateEblk; +typedef struct { + RP pcode; + RmaEblklq I726; + UB * I1006; +} SchedSelectGateEblk; +typedef struct { + RP I1007; + RP pfn; + RP pcode; +} RmaSeqPrimOutputEblkData; +typedef struct { + RmaEblk I726; + RP I1008; +} RmaAnySchedSampleSCg; +typedef struct { + RmaEblk I726; + RP I1006; + RP I1008; + vec32 I1009; +} RmaAnySchedVCg; +typedef struct { + RmaEblk I726; + RP I1006; + RP I1008; + vec32 I776[1]; +} RmaAnySchedWCg; +typedef struct { + RmaEblk I726; + RP I1006; + RP I1008; + scalar I1010[1]; +} RmaAnySchedECg; +typedef struct { + U I1011; + U I714; + U I915; + U I1012; + RmaIbfIp * I1013; + EBLK I726; + void * val; +} RmaThreadSchedCompiledLoads; +typedef struct { + U I714; + U I722; + RmaThreadSchedCompiledLoads * I1014; +} RmaSchedCompileLoadsCg; +typedef struct { + RP I1015; +} RmaRootCbkCg; +typedef struct { + RP I1016; +} RmaRootForceCbkCg; +typedef struct { + RmaEblk I726; + RP I1017; +} RmaForceCbkJmpCg; +typedef struct { + U I5; + U I722 :31; + U I1018 :1; + vec32 I808; + U I1019; + RP I1020; + RP I1021; +} RmaForceSelectorV; +typedef struct { + U I5; + RmaIbfPcode I1027; +} RmaNetTypeDriverGate; +typedef struct { + U I5; + U I668; + RmaIbfPcode I1027[1]; +} RmaNetTypeScatterGate; +typedef struct { + U I5; + RmaIbfPcode I1027; +} RmaNetTypeGatherGate; +typedef struct { + RmaIbfPcode I1028; + U I1029 :3; + U I1030 :1; + U I1031 :1; + U I890 :16; +} RmaNbaGateOfn; +typedef struct { + U I5; + NBS I1032; + RmaIbfPcode I1028; +} RmaNbaGate1; +typedef struct { + RP ptable; + RP pfn; + RP pcode; +} Rma1InputGateFaninCgS; +typedef struct RmaSeqPrimOutputS_ RmaSeqPrimOutputOnClkS; +struct RmaSeqPrimOutputS_ { + RP pfn; + RP I1035; + U state; + U I1036; + RP I1037; + U I706; + scalar val; +}; +typedef struct { + U I5; + U iinput; + UB I1039; + RP I1040; +} RmaCondOptLoad; +typedef struct { + U I5; + U iinput; + UB I1039; + RP I1040; +} RmaMacroStateUpdate; +typedef struct { + U I5; + U state; + U I1041; + UB I1039; + U * I1042; +} RmaMacroState; +typedef struct { + U iinput; + RP I1043; +} RmaMultiInputLogicGateCg; +typedef struct { + U iinput; + RP ptable; + RP I1043; +} RmaSeqPrimEdgeInputCg; +typedef struct { + RmaEblk I726; + RP pcode; +} RmaSched0GateCg; +typedef struct { + RmaEblk I726; + RP pcode; + RP pfn; +} RmaUdpDeltaGateCg; +typedef struct { + RmaEblk I726; + RP pcode; + RP pfn; + scalar I1044; +} RmaSchedDeltaGateCg; +typedef struct { + UB I1045; + RP I1046; + RP I1047; +} RmaPropNodeSeqLhsSCg; +typedef struct { + RmaEblk I726; + RP pcode; + U I915; + U I715[1]; +} RmaBitEdgeEblk; +typedef struct { + U I5; + RP I807; + RmaEblk I726; + RmaIbfPcode I1028; +} RmaGateDelay; +typedef struct { + U I5; + RP I807; + RmaEblk I726; + RmaIbfPcode I1028; +} RmaGateBehavioralDelay; +typedef struct { + U I5; + union { + RP I1290; + RP I1578; + RP I1592; + } I781; + RmaIbfPcode I1028; +} RmaMPDelay; +typedef struct { + U I5; + RmaPulse I1048; + RmaIbfPcode I1028; +} RmaMPPulseHybridDelay; +typedef struct { + U I5; + RmaIbfPcode I1028; + RmaMps I1049; +} RmaMPHybridDelay; +typedef struct { + U I5; + U I1050; + RmaIbfPcode I1028; + RmaEblk I766; +} RmaMPHybridDelayPacked; +typedef struct { + U I5; + RmaIbfPcode I1028; + RmaMpspNewCsdf I1051; +} RmaMPPulseDelay; +typedef struct { + U I5; + RmaMpsp I1051; + RmaIbfPcode I1028; +} RmaMPPulseOptHybridDelay; +typedef struct _RmaBehavioralTransportDelay { + U I5; + RP I685; + RmaTransEventHdr I921; + RP I804; + RmaIbfPcode I1028; +} RmaBehavioralTransportDelayS; +typedef struct { + U I5; + U I685; + RmaTransEventHdr I921; + RP I804; + RmaIbfPcode I1028; +} RmaNtcTransDelay; +typedef struct { + U I5; + U I685; + RmaEblk I726; + RmaIbfPcode I1028; +} RmaNtcTransMpwOptDelay; +typedef struct { + U I5; + RmaEblk I726; + RmaIbfPcode I1028; +} RmaNtcTransZeroDelay; +typedef struct { + U I5; + U I1052; + U I1053; + RmaTransEventHdr I921; + RP I804; + RmaIbfPcode I1028; +} RmaNtcTransDelayRF; +typedef struct { + U I5; + U I1052; + U I1053; + RmaEblk I726; + RmaIbfPcode I1028; +} RmaNtcTransMpwOptDelayRF; +typedef struct { + U I5; + RP I1054; + RmaTransEventHdr I921; + RP I804; + RmaIbfPcode I1028; +} RmaICTransDelay; +typedef struct { + U I5; + RP I1054; + RmaEblk I726; + RmaIbfPcode I1028; +} RmaICTransMpwOptDelay; +typedef struct { + U I5; + RmaEblk I726; + RmaIbfPcode I1028; +} RmaICTransZeroDelay; +typedef struct { + U I5; + RP I807; + RmaEblk I726; + RmaIbfPcode I1028; +} RmaICSimpleDelay; +typedef struct { + U I5; + union { + RP psimple; + RP I1578; + RP I1592; + } I781; + RmaIbfPcode I1028; +} RmaICDelay; +typedef struct { + U I5; + RP I807; + RmaEblk I726; + RmaIbfPcode I1028; +} RmaPortDelay; +typedef struct { + U I890; + RP I1058; +} RmaRtlXEdgesLoad; +typedef struct { + U I5; + RmaRtlXEdgesLoad I1058[(5)]; +} RmaRtlXEdgesHdr; +typedef struct { + U I5; + US I1059; + US I1060 :1; + US I904 :15; + RP I1061; + RP I1062; + RP I1063; +} RmaRtlEdgeBlockHdr; +typedef struct { + RP I1064; + RP I1065; +} RemoteDbsedLoad; +typedef struct { + RmaEblk I726; + RP I1066; + RP I1067; + U I1068 :16; + U I1069 :2; + U I1070 :2; + U I1071 :1; + U I1072 :8; + U I904 :3; + U I471; + RP I1073; + RP I811[(5)]; + RP I813[(5)]; + US I1074; + US I1075; + RemoteDbsedLoad I1076[1]; +} RmaRtlEdgeBlock; +typedef struct TableAssign_ { + struct TableAssign_ * I880; + struct TableAssign_ * I798; + U I5; + U I1078 :1; + U I1079 :1; + U I1080 :2; + U I1081 :1; + U I706 :8; + U I1082 :1; + U I1083 :1; + U I1084 :1; + U I1085 :1; + U I1086 :1; + U I1087 :1; + U I904 :13; + RP ptable; + RP I1043; +} TableAssign; +typedef struct TableAssignLayoutOnClk_ { + struct TableAssignLayoutOnClk_ * I880; + struct TableAssignLayoutOnClk_ * I798; + U I5; + U I1078 :1; + U I1079 :1; + U I1080 :2; + U I1081 :1; + U I706 :8; + U I1082 :1; + U I1083 :1; + U I1084 :1; + U I1085 :1; + U I1086 :1; + U I1087 :1; + U I904 :13; + RP ptable; + RmaSeqPrimOutputOnClkS I1089; + RmaEblk I726; +} TableAssignLayoutOnClk; +typedef struct { + U state; + U I1090; +} RmaSeqPrimOutputOnClkOpt; +typedef struct TableAssignLayoutOnClkOpt_ { + struct TableAssignLayoutOnClkOpt_ * I880; + struct TableAssignLayoutOnClkOpt_ * I798; + U I1092; + U I1078 :1; + U I1079 :1; + U I1080 :2; + U I1081 :1; + U I706 :8; + U I1082 :1; + U I1083 :1; + U I1084 :1; + U I1085 :1; + U I1086 :1; + U I1087 :1; + U I904 :13; + RmaSeqPrimOutputOnClkOpt I1089; + RmaSeqPrimOutputEblkData I1093; +} TableAssignLayoutOnClkOpt; +typedef struct { + U I5; + RP I798; + RP I1094; +} RmaTableAssignList; +typedef struct { + U I5; + RP I798; + RP I1094; + RP I1095; + RP I1037; + US I706; + UB I978; + UB I1096; + UB I1097; + UB I772; + RP I1098[0]; +} RmaThreadTableAssignList; +typedef struct { + RP I1095; + RP I1037; + US I706; + UB I978; + UB I1096; + UB I1097; + UB I772; +} RmaThreadTableHeader; +typedef struct { + RP I1064; +} RmaWakeupListCg; +typedef struct { + RP I1064; +} RmaWakeupArrayCg; +typedef struct { + RP I1064; + RP I1099; +} RmaPreCheckWakeupListCg; +typedef struct { + RP I1064; + RP I1099; +} RmaPreCheckWakeupArrayCg; +typedef struct { + U I1100; + U I706; + RmaTimeStamp I1101[1]; +} RmaTsArray; +typedef struct { + U iinput; + RP I1102; +} RmaConditionsMdb; +typedef struct { + RP I1103; + RP I1104; + U I1105; +} RmaTcListHeader; +typedef struct { + RP I880; + RP I1106; + RP I1107; + RP I721; + U I1108; + scalar I890; + scalar I1109; + US I1110 :1; + US I1111 :1; + US I1112 :1; + US I1113 :1; + US I1114 :1; + US I1115 :1; + US I1116 :5; +} RmaTcCoreSimple; +typedef struct { + RP I880; + RP I1106; + RP I1107; + RP I721; + U I1108; + scalar I890; + scalar I1109; + US I1110 :1; + US I1111 :1; + US I1112 :1; + US I1113 :1; + US I1114 :1; + US I1115 :1; + US I1116 :5; + RP I1117; +} RmaTcCoreConditional; +typedef struct { + RP I880; + RP I1106; + RP I1107; + RP I721; + U I1108; + scalar I890; + scalar I1109; + US I1110 :1; + US I1111 :1; + US I1112 :1; + US I1113 :1; + US I1114 :1; + US I1115 :1; + US I1116 :5; + RP I1117; + RP I1118; +} RmaTcCoreConditionalOpt; +typedef struct { + RP I880; + RP I1106; + RP I1107; + RP I721; + U I1108; + scalar I890; + scalar I1109; + US I1110 :1; + US I1111 :1; + US I1112 :1; + US I1113 :1; + US I1114 :1; + US I1115 :1; + US I1116 :5; + RP I1118; + RP I1119; + U I1120; + RmaConditionsMdb arr[1]; +} RmaTcCoreConditionalMtc; +typedef struct { + RP I1107; + RP I721; + U I1108; + scalar I890; + scalar I1109; + US I1110 :1; + US I1111 :1; + US I1112 :1; + US I1113 :1; + US I1114 :1; + US I1115 :1; + US I1116 :5; +} RmaTcCoreSimpleNoList; +typedef struct { + RP I1107; + RP I721; + U I1108; + scalar I890; + scalar I1109; + US I1110 :1; + US I1111 :1; + US I1112 :1; + US I1113 :1; + US I1114 :1; + US I1115 :1; + US I1116 :5; + RP I1035; +} RmaTcCoreSimpleNoListMdb; +typedef struct { + RP I1107; + RP I721; + U I1108; + scalar I890; + scalar I1109; + US I1110 :1; + US I1111 :1; + US I1112 :1; + US I1113 :1; + US I1114 :1; + US I1115 :1; + US I1116 :5; + RP I1117; +} RmaTcCoreConditionalNoList; +typedef struct { + RP I1107; + RP I721; + U I1108; + scalar I890; + scalar I1109; + US I1110 :1; + US I1111 :1; + US I1112 :1; + US I1113 :1; + US I1114 :1; + US I1115 :1; + US I1116 :5; + RP I1117; + RP I1118; +} RmaTcCoreConditionalOptNoList; +typedef struct { + RP I1107; + RP I721; + U I1108; + scalar I890; + scalar I1109; + US I1110 :1; + US I1111 :1; + US I1112 :1; + US I1113 :1; + US I1114 :1; + US I1115 :1; + US I1116 :5; + RP I1118; + RP I1119; + U I1120; + RmaConditionsMdb arr[1]; +} RmaTcCoreConditionalMtcNoList; +typedef struct { + RP I1107; + RP I721; + U I1108; + scalar I890; + scalar I1109; + US I1110 :1; + US I1111 :1; + US I1112 :1; + US I1113 :1; + US I1114 :1; + US I1115 :1; + US I1116 :5; + RP I1118; + RP I1119; + RP I1035; + U I1120; + RmaConditionsMdb arr[1]; +} RmaTcCoreConditionalMtcNoListMdb; +typedef struct { + RP I1107; + RP I721; + U I1108; + scalar I890; + scalar I1109; + US I1110 :1; + US I1111 :1; + US I1112 :1; + US I1113 :1; + US I1114 :1; + US I1115 :1; + US I1116 :5; + RP I1117; + RP I1035; +} RmaTcCoreConditionalNoListMdb; +typedef struct { + RP I1107; + RP I721; + U I1108; + scalar I890; + scalar I1109; + US I1110 :1; + US I1111 :1; + US I1112 :1; + US I1113 :1; + US I1114 :1; + US I1115 :1; + US I1116 :5; + U I1122; + RP I1123; + RP I1124; + RP I1117; + RP I1125; + RP I1126; + RmaTimeStamp I1127; +} RmaTcCoreNochange; +typedef struct { + RP I1128; + RP I880; +} RmaTcCoreNochangeList; +typedef struct { + RP I1102; + RmaTimeStamp I1129; + scalar I1130; +} RmaConditionalTSLoadNoList; +typedef struct { + RP I880; + RP I1102; + RmaTimeStamp I1129; + scalar I1130; +} RmaConditionalTSLoad; +typedef struct { + RmaTimeStamp I1129; + scalar I1130; + US I890; + RP I1118; +} RmaConditionalTSLoadOptNoList; +typedef struct { + RP I880; + RmaTimeStamp I1129; + scalar I1130; + US I890; + RP I1118; +} RmaConditionalTSLoadOpt; +typedef struct { + RP I1118; + RP I1131; + U I1120; + RmaConditionsMdb arr[1]; +} RmaConditionalTSLoadMtcNoList; +typedef struct { + RP I1035; + RP I1118; + RP I1131; + U I1120; + RmaConditionsMdb arr[1]; +} RmaConditionalTSLoadMtcNoListMdb; +typedef struct { + RP I880; + RP I1118; + RP I1131; + U I1120; + RmaConditionsMdb arr[1]; +} RmaConditionalTSLoadMtc; +typedef struct { + U I1132; + U I1133; + FlatNodeNum I1004; + U I915; + U I1134; + U I1135; + RmaIbfPcode I1028; + union { + scalar I1136; + vec32 I1137; + scalar * I1138; + vec32 * I1139; + } val; +} RmaScanSwitchData; +typedef struct { + RP I880; + RP I798; + RP I1140; +} RmaDoublyLinkedListElem; +typedef struct { + RP I1141; + U I1142 :1; + U I1143 :1; + U I1144 :1; + U I1145 :4; + U I904 :25; + U I1146; +} RmaSwitchGateInCbkListInfo; +typedef struct { + union { + RmaDoublyLinkedListElem I1640; + RmaSwitchGateInCbkListInfo I2; + } I699; + RmaIbfPcode I1028; +} RmaSwitchGate; +typedef struct RmaNonEdgeLoadData1_ { + US I1147; + scalar val; + scalar I1148 :1; + scalar I1149 :1; + scalar I1150 :1; + scalar I1151 :1; + scalar I1152 :1; + U I1153; + RP I811; + RP I1154; + RP I1004; + RP I1155; + RP I1156; +} RmaNonEdgeLoadData1; +typedef struct RmaNonEdgeLoadHdr1_ { + UB I1148; + UB I1157; + UB I978; + RmaNonEdgeLoadData1 * I1058; + RmaNonEdgeLoadData1 * I798; + void * I1158; +} RmaNonEdgeLoadHdr1; +typedef struct RmaNonEdgeLoadHdrPrl1_ { + U I1159; + RP I721; +} RmaNonEdgeLoadHdrPrl1; +typedef struct RmaChildClockProp_ { + RP I811; + RP I1160; + RP I1004; + RP pcode; + scalar val; +} RmaChildClockProp; +typedef struct RmaChildClockPropList1_ { + RmaChildClockProp * I1058; + RmaChildClockProp * I798; +} RmaChildClockPropList1; +typedef struct { + U I5; + U I1161; +} RmaHDLCosimDUTGate; +typedef struct { + UB I1162; + UB I1163 :1; + UB I1164 :1; + UB I1165 :1; + UB I1166 :1; + UB I904 :4; + US cedges; +} RmaMasterXpropLoadHdr; +typedef struct { + UB I1167; + UB I1168; + UB I1169; + UB I1170; + U cedges :30; + U I1164 :1; + U I1171 :1; + U I1172; + U I1173; + RP I1174; + RP I1175; + RmaRtlEdgeBlockHdr * I1176; +} RmaChildXpropLoadHdr; +struct clock_load { + U I181 :5; + U I182 :12; + U I183 :1; + U I184 :2; + U I185 :1; + U I186 :1; + U I187 :1; + U I188 :9; + U I189; + U I190; + void (* pfn)(void * I192, char val); +}; +typedef struct clock_data { + U I197 :1; + U I198 :1; + U I199 :1; + U I200 :1; + U I181 :5; + U I182 :12; + U I201 :6; + U I202 :1; + U I184 :2; + U I185 :1; + U I188 :1; + U I203; + U I204; + U I205; + U I189; + U I206; + U I207; + U I208; + U I209; + U I210; +} HdbsClockData; +struct clock_hiconn { + U I214; + U I215; + U I189; + U I184; +}; +typedef struct _RmaDaiCg { + RP I1177; + RP I1178; + U I1179; +} RmaDaiCg; +typedef union _RmaCbkMemOptUnion { + RP I1177; + RP I1180; + RP I1181; +} RmaCbkMemOptUnion; +typedef struct _RmaDaiOptCg { + RmaCbkMemOptUnion I1182; +} RmaDaiOptCg; +struct futq_slot2 { + U I758; + U I759[32]; +}; +struct futq_slot1 { + U I755; + struct futq_slot2 I756[32]; +}; +struct futq_info { + scalar * I750; + U I751; + U I752; + struct futq_slot1 I753[32]; +}; +struct futq { + struct futq * I740; + struct futq * I742; + RmaEblk * I743; + RmaEblk * I744; + U I731; + U I1; +}; +struct sched_table { + struct futq * I745; + struct futq I746; + struct hash_bucket * I747; + struct hash_bucket * I749; +}; +struct dummyq_struct { + clock_struct I1183; + EBLK * I1184; + EBLK * I1185; + EBLK * I1186; + struct futq * I1187; + struct futq * I1188; + struct futq * I1189; + struct sched_table * I1190; + struct futq_info * I1192; + struct futq_info * I1194; + U I1195; + U I1196; + U I1197; + U I1198; + U I1199; + U I1200; + U I1201; + struct millenium * I1202; + EBLK * I1204; + EBLK * I1205; + EBLK * I1206; + EBLK * I1207; + EBLK * I1208; + EBLK * I1209; + EBLK * I1210; + EBLK * I1211; + EBLK * I1212; + EBLK * I1213; + EBLK * I1214; + EBLK * I1215; + EBLK * I1216; + EBLK * I1217; + EBLK * I1218; + EBLK * I1219; + EBLK * I1220; + EBLK * I1221; + MPS * I1222; + struct retain_t * I1223; + EBLK * I1224; + EBLK * I1225; + EBLK * I1226; + EBLK * I1227; + EBLK * I1228; + EBLK * I1229; + EBLK * I1230; + EBLK * I1231; + EBLK * I1232; + EBLK * I1233; + EBLK * I1234; + EBLK * I1235; + EBLK * I1236; + EBLK * I1237; + EBLK * I1238; + EBLK * I1239; + EBLK * I1240; + EBLK * I1241; + EBLK * I1242; + EBLK * I1243; + EBLK * I1244; + EBLK * I1245; + EBLK * I1246; + EBLK * I1247; + EBLK * I1248; + EBLK * I1249; + EBLK I1250; + EBLK * I1251; + EBLK * I1252; + EBLK * I1253; + EBLK * I1254; + int I1255; + int I1256; + struct vcs_globals_t * I1257; + clock_struct I1258; + unsigned long long I1259; + EBLK * I1260; + EBLK * I1261; + void * I1262; +}; +typedef void (* FP)(void * , scalar ); +typedef void (* FP1)(void * ); +typedef void (* FPRAP)(void * , vec32 * , U ); +typedef U (* FPU1)(void * ); +typedef void (* FPV)(void * , UB * ); +typedef void (* FPVU)(void * , UB * , U ); +typedef void (* FPLSEL)(void * , scalar , U ); +typedef void (* FPLSELV)(void * , vec32 * , U , U ); +typedef void (* FPFPV)(UB * , UB * , U , U , U , U , U , UB * , U ); +typedef void (* FPFA)(UB * , UB * , U , U , U , U , U , U , UB * , U ); +typedef void (* FPRPV)(UB * , U , U , U ); +typedef void (* FPEVCDLSEL)(void * , scalar , U , UB * ); +typedef void (* FPEVCDLSELV)(void * , vec32 * , U , U , UB * ); +typedef void (* FPNTYPE_L)(void * , void * , U , U , UB * , UB * , UB * , UB * , UB * , UB * , UB * , U ); +typedef void (* FPNTYPE_H)(void * , void * , U , U , UB * , UB * , UB * , UB * , U ); +typedef void (* FPNTYPE_LPAP)(void * , void * , void * , U , U , UB * , UB * , U ); +typedef void (* FPNTYPE_HPAP)(void * , void * , void * , U , U , UB * , UB * , UB * , UB * , U ); +typedef struct _lqueue { + EBLK * I727; + EBLK * I1263; + int I1264; + struct _lqueue * I769; +} Queue; +typedef struct { + void * I1266; + void * I1267; + void * I1268[2]; + void * I1269; +} ClkLevel; +typedef struct { + unsigned long long I1270; + EBLK I1171; + U I1271; + U I1272; + union { + void * pHeap; + Queue * pList; + } I699; + unsigned long long I1273; + ClkLevel I1274; + Queue I1275[1]; +} Qhdr; +extern UB Xvalchg[]; +extern UB X4val[]; +extern UB X3val[]; +extern UB X2val[]; +extern UB XcvtstrTR[]; +extern UB Xcvtstr[]; +extern UB Xbuf[]; +extern UB Xbitnot[]; +extern UB Xwor[]; +extern UB Xwand[]; +extern U Xbitnot4val[]; +extern UB globalTable1Input[]; +extern __thread unsigned long long vcs_clocks; +extern UB Xunion[]; +extern U fRTFrcRelCbk; +extern FP txpFnPtr; +extern FP rmaFunctionArray[]; +extern UP rmaFunctionRtlArray[]; +extern FP rmaFunctionLRArray[]; +extern U rmaFunctionCount; +extern U rmaFunctionLRCount; +extern U rmaFunctionLRDummyCount; +extern UP rmaFunctionDummyEndPtr; +extern FP rmaFunctionFanoutArray[]; +extern __thread UB dummyScalar; +extern __thread UB fScalarIsForced; +extern __thread UB fScalarIsReleased; +extern U fNotimingchecks; +extern U fFsdbDumpOn; +extern RP * iparr; +extern FP1 * rmaPostAnySchedFnPtr; +extern FP1 * rmaPostAnySchedFnSamplePtr; +extern FP1 * rmaPostAnySchedVFnPtr; +extern FP1 * rmaPostAnySchedWFnPtr; +extern FP1 * rmaPostAnySchedEFnPtr; +extern FP1 * rmaPostSchedUpdateClockStatusFnPtr; +extern FP1 * rmaPostSchedUpdateClockStatusNonCongruentFnPtr; +extern FP1 * rmaPostSchedUpdateEvTrigFnPtr; +extern FP1 * rmaSched0UpdateEvTrigFnPtr; +extern FP1 * rmaPostSchedRecoveryResetDbsFnPtr; +extern U fGblDataOrTime0Prop; +extern UB rmaEdgeStatusValArr[]; +extern FP1 * propForceCbkSPostSchedCgFnPtr; +extern FP1 * propForceCbkMemoptSPostSchedCgFnPtr; +extern UB * ptableGbl; +extern U * vcs_ptableOffsetsGbl; +extern UB * expandedClkValues; +extern __thread Qhdr * lvlQueue; +extern __thread unsigned threadIndex; +extern int cPeblkThreads; +extern US xedges[]; +extern U mhdl_delta_count; +extern U ignoreSchedForScanOpt; +extern U fignoreSchedForDeadComboCloud; +extern int fZeroUser; +extern U fEveBusPullVal; +extern U fEveBusPullFlag; +extern U fFutEventPRL; +extern U fParallelEBLK; +extern U fBufferingEvent; +extern __thread UB fNettypeIsForced; +extern __thread UB fNettypeIsReleased; +extern EBLK * peblkFutQ1Head; +extern EBLK * peblkFutQ1Tail; +extern US * edgeActionT; +extern unsigned long long * derivedClk; +extern U fHashTableSize; +extern U fSkipStrChangeOnDelay; +extern U fHsimTcheckOpt; +extern scalar edgeChangeLookUp[4][4]; +extern U fDoingTime0Prop; +extern U fLoopDetectMode; +extern int gFLoopDectCodeEna; +extern U fLoopReportRT; + + +extern void *mempcpy(void* s1, void* s2, unsigned n); +extern UB* rmaEvalDelays(UB* pcode, scalar val); +extern UB* rmaEvalDelaysV(UB* pcode, vec32* pval); +extern void rmaPopTransEvent(UB* pcode); +extern void rmaSetupFuncArray(UP* ra, U c, U w); +extern void rmaSetupRTLoopReportPtrs(UP* funcs, UP* rtlFuncs, U cnt, U cntDummy, UP end); +extern void SinitHsimPats(void); +extern void VVrpDaicb(void* ip, U nIndex); +extern int SDaicb(void *ip, U nIndex); +extern void SDaicbForHsimNoFlagScalar(void* pDaiCb, unsigned char value); +extern void SDaicbForHsimNoFlagStrengthScalar(void* pDaiCb, unsigned char value); +extern void SDaicbForHsimNoFlag(void* pRmaDaiCg, unsigned char value); +extern void SDaicbForHsimNoFlag2(void* pRmaDaiCg, unsigned char value); +extern void SDaicbForHsimWithFlag(void* pRmaDaiCg, unsigned char value); +extern void SDaicbForHsimNoFlagFrcRel(void* pRmaDaiCg, unsigned char reason, int msb, int lsb, int ndx); +extern void SDaicbForHsimNoFlagFrcRel2(void* pRmaDaiCg, unsigned char reason, int msb, int lsb, int ndx); +extern void VcsHsimValueChangeCB(void* pRmaDaiCg, void* pValue, unsigned int valueFormat); +extern U isNonDesignNodeCallbackList(void* pRmaDaiCg); +extern void SDaicbForHsimCbkMemOptNoFlagScalar(void* pDaiCb, unsigned char value, unsigned char isStrength); +extern void SDaicbForHsimCbkMemOptWithFlagScalar(void* pDaiCb, unsigned char value, unsigned char isStrength); +extern void SDaicbForHsimCbkMemOptNoFlagScalar(void* pDaiCb, unsigned char value, unsigned char isStrength); +extern void SDaicbForHsimCbkMemOptWithFlagScalar(void* pDaiCb, unsigned char value, unsigned char isStrength); +extern void VVrpNonEventNonRegdScalarForHsimOptCbkMemopt(void* ip, U nIndex); +extern void SDaicbForHsimCbkMemOptNoFlagDynElabScalar(U* mem, unsigned char value, unsigned char isStrength); +extern void SDaicbForHsimCbkMemOptWithFlagDynElabScalar(U* mem, unsigned char value, unsigned char isStrength); +extern void SDaicbForHsimCbkMemOptNoFlagDynElabFrcRel(U* mem, unsigned char reason, int msb, int lsb, int ndx); +extern void SDaicbForHsimCbkMemOptNoFlagFrcRel(void* pDaiCb, unsigned char reason, int msb, int lsb, int ndx); +extern void hsimDispatchCbkMemOptForVcd(RP p, U val); +extern void* hsimGetCbkMemOptCallback(RP p); +extern void hsimDispatchCbkMemOptNoDynElabS(RP* p, U val, U isStrength); +extern void* hsimGetCbkPtrNoDynElab(RP p); +extern void hsimDispatchCbkMemOptDynElabS(U** pvcdarr, U** pcbkarr, U val, U isScalForced, U isScalReleased, U isStrength); +extern void hsimDispatchCbkMemOptNoDynElabVector(RP* /*RmaDaiOptCg* */p, void* pval, U /*RmaValueType*/ vt, U cbits); +extern void copyAndPropRootCbkCgS(RmaRootCbkCg* pRootCbk, scalar val); +extern void copyAndPropRootCbkCgV(RmaRootCbkCg* rootCbk, vec32* pval); +extern void copyAndPropRootCbkCgW(RmaRootCbkCg* rootCbk, vec32* pval); +extern void copyAndPropRootCbkCgE(RmaRootCbkCg* rootCbk, scalar* pval); +extern void Wsvvar_callback_non_dynamic1(RP* ptr, int); +extern void rmaExecEvSyncList(RP plist); +extern void Wsvvar_callback_virt_intf(RP* ptr); +extern void Wsvvar_callback_hsim_var(RP* ptr); +extern void checkAndConvertVec32To2State(vec32* value, vec32* svalue, U cbits, U* pforcedBits); +extern unsigned int fGblDataOrTime0Prop; +extern void SchedSemiLerMP1(UB* pmps, U partId); +extern void SchedSemiLerMPO(UB* pmpso, U partId); +extern void rmaDummyPropagate(void); +extern RP rmaTestCg(RP pcode, U vt, UB* value); +extern void hsUpdateModpathTimeStamp(UB* pmps); +extern void doMpd32One(UB* pmps); +extern void doMpdCommon(MPS* pmps); +extern TimeStamp GET_DIFF_DELAY_FUNC(TimeStamp ts); +extern void SchedSemiLerMP(UB* ppulse, U partId); +extern EBLK *peblkFutQ1Head; +extern EBLK *peblkFutQ1Tail; +extern void scheduleuna(UB *e, U t); +extern void scheduleuna_mp(EBLK *e, unsigned t); +extern void schedule(UB *e, U t); +extern void sched_hsopt(struct dummyq_struct * pQ, EBLK *e, U t); +extern void sched_millenium(struct dummyq_struct * pQ, void *e, U thigh, U t); +extern void schedule_1(EBLK *e); +extern void sched0(UB *e); +extern void sched0Raptor(UB *e); +extern void sched0lq(EBLK *e); +extern void sched0lqnc(EBLK *e); +extern void sched0una(UB *e); +extern void sched0una_th(struct dummyq_struct *pq, UB *e); +extern void hsopt_sched0u_th(struct dummyq_struct *pq, UB *e); +extern void scheduleuna_mp_th(struct dummyq_struct *pq, EBLK *e, unsigned t); +extern void schedal(UB *e); +extern void sched0_th(struct dummyq_struct * pQ, EBLK *e); +extern void sched0u(UB *e); +extern void sched0u_th(struct dummyq_struct *pq, UB *e); +extern void sched0_hsim_front_th(struct dummyq_struct * pQ, UB *e); +extern void sched0_hsim_frontlq_th(struct dummyq_struct * pQ, UB *e); +extern void sched0lq_th(struct dummyq_struct * pQ, UB *e); +extern void schedal_th(struct dummyq_struct * pQ, UB *e); +extern void scheduleuna_th(struct dummyq_struct * pQ, void *e, U t); +extern void schedule_th(struct dummyq_struct * pQ, UB *e, U t); +extern void schedule_1_th(struct dummyq_struct * pQ, EBLK *peblk); +extern void SetupLER_th(struct dummyq_struct * pQ, EBLK *e); +extern void FsdbReportClkGlitch(UB*,U); +extern void AddToClkGLitchArray(EBLK*); +extern void SchedSemiLer_th(struct dummyq_struct * pQ, EBLK *e); +extern void SchedSemiLerTXP_th(struct dummyq_struct * pQ, EBLK *e); +extern void SchedSemiLerTXPFreeVar_th(struct dummyq_struct * pQ, EBLK *e); +extern U getVcdFlags(UB *ip); +extern void VVrpNonEventNonRegdScalarForHsimOpt(void* ip, U nIndex); +extern void VVrpNonEventNonRegdScalarForHsimOpt2(void* ip, U nIndex); +extern void SchedSemiLerTBReactiveRegion(struct eblk* peblk); +extern void SchedSemiLerTBReactiveRegion_th(struct eblk* peblk, U partId); +extern void SchedSemiLerTr(UB* peblk, U partId); +extern void SchedSemiLerNBA(UB* peblk, U partId); +extern void NBA_Semiler(void *ip, void *pNBS); +extern void sched0sd_hsim(UB* peblk); +extern void vcs_sched0sd_hsim_udpclk(UB* peblk); +extern void vcs_sched0sd_hsim_udpclkopt(UB* peblk); +extern void sched0sd_hsim_PRL(UB* peblk); +extern void sched0lq_parallel_clk(EBLK* peblk); +extern U isRtlClockScheduled(EBLK* peblk); +extern void doFgpRaceCheck(UB* pcode, UB* p, U flag); +extern void doSanityLvlCheck(); +extern void sched0lq_parallel_ova(EBLK* peblk); +extern void sched0lq_parallel_ova_precheck(EBLK* peblk); +extern void rmaDlpEvalSeqPrim(UB* peblk, UB val, UB preval); +extern void appendNtcEvent(UB* phdr, scalar s, U schedDelta); +extern void appendTransEventS(RmaTransEventHdr* phdr, scalar s, U schedDelta); +extern void schedRetainHsim(MPS* pMPS, scalar sv, scalar pv); +extern void updateRetainHsim(MPS* pMPS,scalar sv, scalar pv); +extern void hsimCountXEdges(void* record, scalar s); +extern void hsimRegisterEdge(void* sm, scalar s); +extern U pvcsGetPartId(); +extern void HsimPVCSPartIdCheck(U instNo); +extern void debug_func(U partId, struct dummyq_struct* pQ, EBLK* EblkLastEventx); +extern struct dummyq_struct* pvcsGetQ(U thid); +extern EBLK* pvcsGetLastEventEblk(U thid); +extern void insertTransEvent(RmaTransEventHdr* phdr, scalar s, scalar pv, scalar resval, U schedDelta, int re, UB* predd, U fpdd); +extern void insertNtcEventRF(RmaTransEventHdr* phdr, scalar s, scalar pv, scalar resval, U schedDelta, U* delays); +extern U doTimingViolation(RmaTimeStamp ts,RP* pdata, U fskew, U limit, U floaded, U fcondopt, RmaTimeStamp tsNochange); +extern void sched_gate_hsim(EBLK* peblk, unsigned t, RP* offset, U gd_info, U encodeInPcode, void* propValue); +extern int getCurSchedRegion(); +extern FP getRoutPtr(RP, U); +extern U rmaChangeCheckAndUpdateE(scalar* pvalDst, scalar* pvalSrc, U cbits); +extern void rmaUpdateE(scalar* pvalDst, scalar* pvalSrc, U cbits); +extern U rmaChangeCheckAndUpdateEFromW(scalar* pvalDst, vec32* pvalSrc, U cbits); +extern void rmaLhsPartSelUpdateE(scalar* pvalDst, scalar* pvalSrc, U index, U width); +extern void rmaUpdateWithForceSelectorE(scalar* pvalDst, scalar* pvalSrc, U cbits, U* pforceSelector); +extern void rmaUpdateWFromE(vec32* pvalDst, scalar* pvalSrc, U cbits); +extern U rmaLhsPartSelWithChangeCheckE(scalar* pvalDst, scalar* pvalSrc, U index, U width); +extern void rmaLhsPartSelWFromE(vec32* pvalDst, scalar* pvalSrc, U index,U width); +extern U rmaChangeCheckAndUpdateW(vec32* pvalDst, vec32* pvalSrc, U cbits); +extern void rmaUpdateW(vec32* pvalDst, vec32* pvalSrc, U cbits); +extern void rmaUpdateEFromW(scalar* pvalDst, vec32* pvalSrc, U cbits); +extern void *VCSCalloc(size_t size, size_t count); +extern void *VCSMalloc(size_t size); +extern void VCSFree(void *ptr); +extern U rmaLhsPartSelWithChangeCheckW(vec32* pvalDst, vec32* pvalSrc, U index,U width); +extern void rmaLhsPartSelEFromW(scalar* pvalDst, vec32* pvalSrc, U index,U width); +extern U rmaLhsPartSelWithChangeCheckEFromW(scalar* pvalDst, vec32* pvalSrc, U index,U width); +extern void rmaLhsPartSelUpdateW(vec32* pvalDst, vec32* pvalSrc, U index, U width); +extern void rmaEvalWunionW(vec32* dst, vec32* src, U cbits, U count); +extern void rmaEvalWorW(vec32* dst, vec32* src, U cbits, U count); +extern void rmaEvalWandW(vec32* dst, vec32* src, U cbits, U count); +extern void rmaEvalUnionE(scalar* dst, scalar* src, U cbits, U count, RP ptable); +typedef U RmaCgFunctionType; +extern RmaIbfPcode* rmaEvalPartSelectsW(vec32* pvec32, U startIndex, U onWidth, U offWidth, U count, RmaIbfPcode* pibfPcode, U fnonRootForce, UB* pevcdStatus); +extern RmaIbfPcode* rmaEvalPartSelectsWLe32(vec32* pvec32, U startIndex, U onWidth, U offWidth, U count, RmaIbfPcode* pibfPcode, U fnonRootForce, UB* pevcdStatus); +extern RmaIbfPcode* rmaEvalPartSelectsWToE(vec32* pvec32, U startIndex, U onWidth, U offWidth, U count, RmaIbfPcode* pibfPcode, U fnonRootForce); +extern RmaIbfPcode* rmaEvalPartSelectsEToE(scalar* pv, U startIndex, U onWidth, U offWidth, U count, RmaIbfPcode* pibfPcode, U fnonRootForce, UB* pevcdStatus); +extern RmaIbfPcode* rmaEvalPartSelectsEToW(scalar* pv, U startIndex, U onWidth, U offWidth, U count, RmaIbfPcode* pibfPcode, U fnonRootForce); +extern U rmaEvalBitPosEdgeW(vec32* pvalCurr, vec32* pvalPrev, U cbits, U* pedges); +extern U rmaEvalBitNegEdgeW(vec32* pvalCurr, vec32* pvalPrev, U cbits, U* pedges); +extern U rmaEvalBitChangeW(vec32* pvalCurr, vec32* pvalPrev, U cbits, U* pedges); +extern U VcsForceVecVCg(UB* pcode, UB* pval, UB* pvDst, UB* pvCur, U fullcbits, U ibeginSrc, U ibeginDst, U width, U/*RmaValueConvType*/ convtype, U/*RmaForceType*/ frcType, UB* prhs, UB* prhsDst, U frhs, U* pforcedbits, U fisRoot); +extern U VcsReleaseVecVCg(UB* pcode, UB* pvDst, U fullcbits, U ibeginDst, U width, UB* prhsDst, U frhs, U* pforcedbits, U fisRoot); +extern U VcsForceVecWCg(UB* pcode, UB* pval, UB* pvDst, UB* pvCur, U fullcbits, U ibeginSrc, U ibeginDst, U width, U/*RmaValueConvType*/ convtype, U /*RmaForceType*/ frcType, UB* prhs, UB* prhsDst, U frhs, U* pforcedbits, U fisRoot); +extern U VcsReleaseVecWCg(UB* pcode, UB* pvDst, U fullcbits, U ibeginDst, U width, UB* prhsDst, U frhs, U* pforcedbits, U fisRoot); +extern U VcsForceVecECg(UB* pcode, UB* pval, UB* pvDst, UB* pvCur, U fullcbits, U ibeginSrc, U ibeginDst, U width, U /*RmaValueConvType*/ convtype, U /*RmaForceType*/ frcType,UB* prhs, UB* prhsDst, U frhs, U* pforcedbits, U fisRoot); +extern U VcsForceVecACg(UB* pcode, UB* pval, UB* pvDst, UB* pvCur, U fullcbits, U ibeginSrc, U ibeginDst, U width, U /*RmaValueConvType*/ convtype, U /*RmaForceType*/ frcType,UB* prhs, UB* prhsDst, U frhs, U* pforcedbits, U fisRoot); +extern U VcsReleaseVecCg(UB* pcode, UB* pvDst, U ibeginDst, U width, U /*RmaValueType*/ type,U fisRoot, UB* prhsDst, U frhs, U* pforcedbits); +extern U VcsDriveBitsAndDoChangeCheckV(vec32* pvSel, vec32* pvCur, U fullcbits, U* pforcedbits, U isRoot); +extern U VcsDriveBitsAndDoChangeCheckW(vec32* pvSel, vec32* pvCur, U fullcbits, U* pforcedbits, U isRoot); +extern U VcsDriveBitsAndDoChangeCheckE(scalar* pvSel, scalar* pvCur, U fullcbits, U* pforcedbits, U isRoot); +extern void cgvecDebug_Eblk(UB* pcode); +extern U rmaCmpW(vec32* pvalDst, vec32* pvalSrc, U index, U width); +extern void copyVec32ArrMask(vec32* pv1, vec32* pv2, U len, U* mask); +extern void* memcpy(void*, const void*, size_t); +extern int memcmp(const void*, const void*, size_t); +extern void propagateScanOptPathVal(EBLK *peblk); +extern UB* rmaProcessScanSwitches(UB* pcode, scalar val); +extern UB* rmaProcessScanSwitchesV(UB* pcode, vec32 *pval); +extern UB* rmaProcessScanoptDump(UB* pcode, scalar val); +extern UB* rmaProcessScanoptDumpV(UB* pcode, vec32 *pval); +extern UB* rmaProcessScanChainOptSeqPrims(UB* pcode, scalar val); +extern void rmaProcessPvcsCcn(UB* pcode, scalar val); +extern void rmaProcessPvcsCcnE(UB* pcode, scalar* val); +extern void rmaProcessPvcsCcnW(UB* pcode, vec32* val); +extern void rmaProcessPvcsCcnV(UB* pcode, vec32* val); +extern void rmaProcessPvcsCcnCompiledS(UB* pcode, U offset, scalar ibnval); +extern void rmaProcessPvcsCcnCompiledV(UB* pcode, U offset, vec32* pval); +extern void schedResetRecoveryDbs(U cedges, EBLK* peblkFirst); +extern UB* rmaEvalUnaryOpV(UB* pcode, vec32* pval); +extern UB* rmaEvalBinaryOpV(UB* pcode, vec32* pval); +extern UB* rmaEvalBinaryOpVOneFanoutCount(UB* pcode, vec32* pval); +extern UB* rmaEvalBinaryOpVLargeFanoutCount(UB* pcode, vec32* pval); +extern UB* rmaEvalAndOpVOneFanoutCount(UB* pcode, vec32* value); +extern UB* rmaEvalAndOpVLargeFanoutCount(UB* pcode, vec32* value); +extern UB* rmaEvalAndOpV(UB* pcode, vec32* value); +extern UB* rmaEvalOrOpVOneFanoutCount(UB* pcode, vec32* value); +extern UB* rmaEvalOrOpVLargeFanoutCount(UB* pcode, vec32* value); +extern UB* rmaEvalOrOpV(UB* pcode, vec32* value); +extern UB* rmaEvalTernaryOpV(UB* pcode, vec32* pval); +extern UB* rmaEvalUnaryOpW(UB* pcode, vec32* pval); +extern UB* rmaEvalBinaryOpW(UB* pcode, vec32* pval); +extern UB* rmaEvalTernaryOpW(UB* pcode, vec32* pval); +extern UB* rmaEvalUnaryOpE(UB* pcode, scalar* pv); +extern UB* rmaEvalBinaryOpE(UB* pcode, scalar* pv); +extern UB* rmaEvalTernaryOpE(UB* pcode, scalar* pv); +extern UB* rmaEvalTernaryOpS(UB* pcode, scalar val); +extern scalar rmaGetScalarFromWCg(vec32* pval, U index); +extern void rmaSetScalarInWCg(vec32* pval, U index, scalar s); +extern void rmaSetWInW(vec32* dst, vec32* src, U index, U indexSrc, U width); +extern void rmaCountRaptorBits(void* pval, void* pvalPrev, U cbits, U vt); +extern void setHsimFunc(void* ip); +extern void unsetHsimFunc(void* ip); +extern UB* getEvcdStatusByFlagsE(scalar* pscalar, UB* pevcdTBDriverFlags, U cdrivers, UB* table, U cbits); +extern UB* getEvcdStatusByFlagsV(vec32* pvec32, UB* pevcdTBDriverFlags, U cdrivers, UB* table, U cbits); +extern UB* getEvcdStatusByFlagsW(vec32* pvec32, UB* pevcdTBDriverFlags, U cdrivers, UB* table, U cbits); +extern UB* getEvcdStatusByFlagsS(scalar* pscalar, UB* pevcdTBDriverFlags, U cdrivers, UB* table); +extern UB* getSingleDrvEvcdStatusS(UB value, U fTBDriver); +extern UB* getSingleDrvEvcdStatusE(scalar* pscalars, U fTBDriver, U cbits); +extern UB* getSingleDrvEvcdStatusV(scalar* pscalars, U fTBDriver, U cbits); +extern UB* getSingleDrvEvcdStatusW(scalar* pscalars, U fTBDriver, U cbits); +extern UB* getEvcdStatusByDrvEvcdStatus(UB* pdrvevcdStatus, U cdrivers, UB* table, U cbits); +extern void evcdCallback(UP pcode, U cbits); +extern UB* getSavedEvcdStatus(void); +extern void saveEvcdStatus(UB*); +extern void mhdlMarkExport(void*, U); +extern void levelInsertQueue(int); +extern void VcsRciRtl(RP pcode); +extern U fLoopDetectMode; +extern int gFLoopDectCodeEna; +extern U fLoopReportRT; +extern void rtSched0LoopDectDumpProcess(void* e, void* rtn, void* PQ); +extern void pushHsimRtnCtxt(void* pcode); +extern void popHsimRtnCtxt(); +extern EBLK* loopReportInlinedSched0Wrapper(EBLK *peblk); +extern void loopReportSched0Wrapper(EBLK *peblk, unsigned int sfType, unsigned int fTH, struct dummyq_struct* pq); +extern void loopReportSchedSemiLerWrapper(EBLK *peblk, int sfType); +extern void CallGraphPushNodeAndAddToGraph(UP flatNode, UP instNum, U dummy); +extern void CallGraphPopNode(void); +extern RP elabGetIpTpl(U in); +extern U rmaEvalBitBothEdgeW(vec32* pvalCurr, vec32* pvalPrev, U cbits, U* pedges); +extern U rmaEvalBitEdgeQ1W(vec32* pvalCurr, vec32* pvalPrev, U cbits, U* pedges); +extern U rmaEvalBitEdgeQXW(vec32* pvalCurr, vec32* pvalPrev, U cbits, U* pedges); +extern U rmaEvalBitEdgeQ0W(vec32* pvalCurr, vec32* pvalPrev, U cbits, U* pedges); +extern U rmaEval01EdgeW(vec32* pvalCurr, vec32* pvalPrev, U cbits, U* pedges); +extern U rmaEval0XEdgeW(vec32* pvalCurr, vec32* pvalPrev, U cbits, U* pedges); +extern U rmaEval10EdgeW(vec32* pvalCurr, vec32* pvalPrev, U cbits, U* pedges); +extern U rmaEval1XEdgeW(vec32* pvalCurr, vec32* pvalPrev, U cbits, U* pedges); +extern U rmaEvalX1EdgeW(vec32* pvalCurr, vec32* pvalPrev, U cbits, U* pedges); +extern U rmaEvalX0EdgeW(vec32* pvalCurr, vec32* pvalPrev, U cbits, U* pedges); +extern U rmaEvalBitPosEdgeE(scalar* pvalCurr, scalar* pvalPrev, U cbits, U* pedges); +extern U rmaEvalBitNegEdgeE(scalar* pvalCurr, scalar* pvalPrev, U cbits, U* pedges); +extern U rmaEvalBitBothEdgeE(scalar* pvalCurr, scalar* pvalPrev, U cbits, U* pedges); +extern U rmaEvalBitEdgeQ1E(scalar* pvalCurr, scalar* pvalPrev, U cbits, U* pedges); +extern U rmaEvalBitEdgeQ0E(scalar* pvalCurr, scalar* pvalPrev, U cbits, U* pedges); +extern U rmaEvalBitChangeE(scalar* pvalCurr, scalar* pvalPrev, U cbits, U* pedges); +extern void rmaScheduleNbaGate(RP pcode, scalar val); +extern void rmaEvalRtlEdgeLoads(RmaRtlEdgeBlockHdr *phdr, US clkEdge, scalar clkVal, scalar prevClkVal, scalar val4, scalar prevval4, scalar master4val); +extern void rmaEvaluateDynamicGateLoadsCg(RP p, scalar s); +extern void rmaEvaluateFusedWithDynamicGateLoadsCg(RP p, scalar s); +extern void rmaScheduleGatedClockEdgeLoadNew(UB* p, US* ea, U flags, UB* plist, UB* pprevlist, scalar v); +extern void rmaScheduleGatedClockEdgeLoad(UB* p, US* ea, U flags, UB* plist, UB* pprevlist, scalar v); +extern void rmaRemoveNonEdgeLoads(UB* pcode); +extern void rmaRecordEvents(HsimNodeRecord *pnr); +extern void handlePCBs(UB* p, U i); +extern void markMasterClkOvaLists(U fdbs, RP p); +extern void rmaChildClockPropAfterWrite(UB* p); +extern void rmaSchedChildClockPropAfterWrite(UB* p, UB* pmasterList, UB val); +extern void HDLCosimProcessDUTInputChange(U inputId, void* val); +extern void rmaChangeListForMovedGates(UB clkVal, UB f10Edge, UB* subMasterVal, UB* plist, RP* p, U count); +extern void rmaEvalSeqPrimLoadsByteArray(UB* pcode, UB val, UB prevval4); +extern void rmaEvalSeqPrimLoadsByteArrayX(UB* pcode, UB val, UB prevval4); +extern void vcsRmaEvalSeqPrimLoadsByteArraySCT(UB* pcode, UB val, UB prevval4, U c); +extern void vcsAbortForBadEBlk(void); +extern scalar edgeChangeLookUp[4][4]; +extern void Wsvvar_sched_virt_intf_eval(RP* ptr); +extern void vcs_hwcosim_drive_dut_scalar(uint id, char val); +extern void vcs_hwcosim_drive_dut_vector_4state(uint id, vec32* val); +extern U vcs_rmaGetClkValForSeqUdpLayoutOnClkOpt(UB* poutput); +extern U rmaIsS2State(scalar s); +extern U rmaIsV2State(vec32* pval, U cbits); +extern U rmaIsW2State(vec32* pval, U cbits); +extern U rmaIsE2State(scalar* pval, U cbits); +extern void rmaUpdateRecordFor2State(HsimNodeRecord* record, U f2state); +typedef void (*FuncPtr)(); +static inline U asm_bsf (U in) +{ +#if defined(linux) + U out; +#if !defined(__aarch64__) + asm ("movl %1, %%eax; bsf %%eax, %%eax; movl %%eax, %0;" + :"=r"(out) + :"r"(in) + :"%eax" + ); +#else + out = ffs(in) - 1; +#endif + return out; +#else + return 0; +#endif +} + + +#ifdef __cplusplus +extern "C" { +#endif +void hs_0_M_6_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_6_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_6_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_9_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_9_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_9_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_9_2__simv_daidir (UB * pcode); +void hs_0_M_9_5__simv_daidir (UB * pcode, UB val); +void hs_0_M_9_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_10_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_10_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_10_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_10_2__simv_daidir (UB * pcode); +void hs_0_M_10_5__simv_daidir (UB * pcode, UB val); +void hs_0_M_10_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_15_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_15_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_15_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_15_2__simv_daidir (UB * pcode); +void hs_0_M_15_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_26_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_26_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_26_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_26_2__simv_daidir (UB * pcode); +void hs_0_M_26_5__simv_daidir (UB * pcode, UB val); +void hs_0_M_26_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_27_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_27_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_27_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_27_2__simv_daidir (UB * pcode); +void hs_0_M_27_5__simv_daidir (UB * pcode, UB val); +void hs_0_M_27_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_28_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_28_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_28_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_28_2__simv_daidir (UB * pcode); +void hs_0_M_28_5__simv_daidir (UB * pcode, UB val); +void hs_0_M_28_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_31_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_31_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_31_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_31_2__simv_daidir (UB * pcode); +void hs_0_M_31_5__simv_daidir (UB * pcode, UB val); +void hs_0_M_31_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_32_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_32_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_32_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_32_2__simv_daidir (UB * pcode); +void hs_0_M_32_5__simv_daidir (UB * pcode, UB val); +void hs_0_M_32_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_33_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_33_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_33_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_33_2__simv_daidir (UB * pcode); +void hs_0_M_33_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_34_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_34_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_34_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_34_2__simv_daidir (UB * pcode); +void hs_0_M_34_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_35_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_35_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_35_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_35_2__simv_daidir (UB * pcode); +void hs_0_M_35_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_36_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_36_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_36_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_36_2__simv_daidir (UB * pcode); +void hs_0_M_36_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_37_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_37_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_37_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_37_2__simv_daidir (UB * pcode); +void hs_0_M_37_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_38_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_38_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_38_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_38_2__simv_daidir (UB * pcode); +void hs_0_M_38_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_39_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_39_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_39_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_39_2__simv_daidir (UB * pcode); +void hs_0_M_39_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_40_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_40_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_40_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_40_2__simv_daidir (UB * pcode); +void hs_0_M_40_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_41_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_41_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_41_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_41_2__simv_daidir (UB * pcode); +void hs_0_M_41_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_56_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_57_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_57_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_57_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_57_2__simv_daidir (UB * pcode); +void hs_0_M_57_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_58_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_59_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_59_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_59_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_59_2__simv_daidir (UB * pcode); +void hs_0_M_59_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_60_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_60_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_60_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_60_2__simv_daidir (UB * pcode); +void hs_0_M_60_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_61_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_61_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_61_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_61_2__simv_daidir (UB * pcode); +void hs_0_M_61_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_62_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_62_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_62_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_62_2__simv_daidir (UB * pcode); +void hs_0_M_62_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_63_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_63_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_63_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_63_2__simv_daidir (UB * pcode); +void hs_0_M_63_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_64_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_64_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_64_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_64_2__simv_daidir (UB * pcode); +void hs_0_M_64_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_65_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_66_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_66_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_66_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_66_2__simv_daidir (UB * pcode); +void hs_0_M_66_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_68_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_68_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_68_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_68_2__simv_daidir (UB * pcode); +void hs_0_M_68_5__simv_daidir (UB * pcode, UB val); +void hs_0_M_68_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_70_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_70_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_70_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_71_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_71_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_71_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_71_2__simv_daidir (UB * pcode); +void hs_0_M_71_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_72_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_72_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_72_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_72_2__simv_daidir (UB * pcode); +void hs_0_M_72_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_74_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_74_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_74_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_74_2__simv_daidir (UB * pcode); +void hs_0_M_74_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_75_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_75_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_75_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_75_2__simv_daidir (UB * pcode); +void hs_0_M_75_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_76_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_76_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_76_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_76_2__simv_daidir (UB * pcode); +void hs_0_M_76_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_77_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_77_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_77_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_77_2__simv_daidir (UB * pcode); +void hs_0_M_77_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_78_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_78_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_78_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_78_2__simv_daidir (UB * pcode); +void hs_0_M_78_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_80_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_80_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_80_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_80_2__simv_daidir (UB * pcode); +void hs_0_M_80_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_86_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_86_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_86_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_87_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_87_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_87_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_87_2__simv_daidir (UB * pcode); +void hs_0_M_87_5__simv_daidir (UB * pcode, UB val); +void hs_0_M_87_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_91_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_92_0__simv_daidir (UB * pcode, vec32 * I1006, U I915); +void hs_0_M_93_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_96_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_96_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_96_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_96_2__simv_daidir (UB * pcode); +void hs_0_M_96_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_100_0__simv_daidir (UB * pcode, vec32 * I1006, U I915); +void hs_0_M_101_21__simv_daidir (UB * pcode, vec32 * I1006, U I915); +void hs_0_M_101_0__simv_daidir (UB * pcode, vec32 * I1006, U I915); +void hs_0_M_101_5__simv_daidir (UB * pcode, U I915); +void hs_0_M_102_21__simv_daidir (UB * pcode, vec32 * I1006, U I915); +void hs_0_M_102_0__simv_daidir (UB * pcode, vec32 * I1006, U I915); +void hs_0_M_102_5__simv_daidir (UB * pcode, U I915); +void hs_0_M_103_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_103_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_103_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_103_2__simv_daidir (UB * pcode); +void hs_0_M_103_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_104_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_104_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_104_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_104_2__simv_daidir (UB * pcode); +void hs_0_M_104_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_105_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_105_5__simv_daidir (UB * pcode, UB val); +void hs_0_M_106_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_106_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_106_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_106_2__simv_daidir (UB * pcode); +void hs_0_M_106_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_107_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_111_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_111_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_111_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_115_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_115_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_115_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_115_2__simv_daidir (UB * pcode); +void hs_0_M_115_5__simv_daidir (UB * pcode, UB val); +void hs_0_M_115_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_116_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_117_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_118_21__simv_daidir (UB * pcode, vec32 * I1006, U I915); +void hs_0_M_118_0__simv_daidir (UB * pcode, vec32 * I1006, U I915); +void hs_0_M_118_6__simv_daidir (UB * pcode, scalar val, U I890); +void hs_0_M_118_7__simv_daidir (UB * pcode, vec32 * I1363, U I890, U I1373); +void hs_0_M_118_10__simv_daidir (UB * pcode, vec32 * I1006); +void hs_0_M_119_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_120_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_120_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_120_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_120_2__simv_daidir (UB * pcode); +void hs_0_M_120_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_121_21__simv_daidir (UB * pcode, vec32 * I1006, U I915); +void hs_0_M_121_0__simv_daidir (UB * pcode, vec32 * I1006, U I915); +void hs_0_M_121_6__simv_daidir (UB * pcode, scalar val, U I890); +void hs_0_M_121_7__simv_daidir (UB * pcode, vec32 * I1363, U I890, U I1373); +void hs_0_M_121_10__simv_daidir (UB * pcode, vec32 * I1006); +void hsG_0__0 (struct dummyq_struct * I1289, EBLK * I1283, U I685); +#ifdef __cplusplus +} +#endif + +#ifdef __cplusplus + } +#endif +#endif /*__DO_RMAHDR_*/ + diff --git a/tb/chip_top/csrc/rmapats.m b/tb/chip_top/csrc/rmapats.m new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/csrc/rmapats.o b/tb/chip_top/csrc/rmapats.o new file mode 100644 index 0000000..f7e34a8 Binary files /dev/null and b/tb/chip_top/csrc/rmapats.o differ diff --git a/tb/chip_top/csrc/rmapats_mop.o b/tb/chip_top/csrc/rmapats_mop.o new file mode 100644 index 0000000..a99134d Binary files /dev/null and b/tb/chip_top/csrc/rmapats_mop.o differ diff --git a/tb/chip_top/csrc/rmar.c b/tb/chip_top/csrc/rmar.c new file mode 100644 index 0000000..21b81fa --- /dev/null +++ b/tb/chip_top/csrc/rmar.c @@ -0,0 +1,13 @@ +#include +#include +#include "rmar0.h" + +// stubs for Hil functions +#ifdef __cplusplus +extern "C" { +#endif +void __Hil__Static_Init_Func__(void) {} +#ifdef __cplusplus +} +#endif + diff --git a/tb/chip_top/csrc/rmar.h b/tb/chip_top/csrc/rmar.h new file mode 100644 index 0000000..77865aa --- /dev/null +++ b/tb/chip_top/csrc/rmar.h @@ -0,0 +1,18 @@ +#ifndef _RMAR1_H_ +#define _RMAR1_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef __DO_RMAHDR_ +#include "rmar0.h" +#endif /*__DO_RMAHDR_*/ + +extern UP rmaFunctionRtlArray[]; + +#ifdef __cplusplus +} +#endif +#endif + diff --git a/tb/chip_top/csrc/rmar.o b/tb/chip_top/csrc/rmar.o new file mode 100644 index 0000000..1989370 Binary files /dev/null and b/tb/chip_top/csrc/rmar.o differ diff --git a/tb/chip_top/csrc/rmar0.h b/tb/chip_top/csrc/rmar0.h new file mode 100644 index 0000000..48e8516 --- /dev/null +++ b/tb/chip_top/csrc/rmar0.h @@ -0,0 +1,13 @@ +#ifndef _RMAR0_H_ +#define _RMAR0_H_ + +#ifdef __cplusplus +extern "C" { +#endif + + +#ifdef __cplusplus +} +#endif +#endif + diff --git a/tb/chip_top/csrc/rmar_llvm_0_0.o b/tb/chip_top/csrc/rmar_llvm_0_0.o new file mode 100644 index 0000000..3663b36 Binary files /dev/null and b/tb/chip_top/csrc/rmar_llvm_0_0.o differ diff --git a/tb/chip_top/csrc/rmar_llvm_0_1.o b/tb/chip_top/csrc/rmar_llvm_0_1.o new file mode 100644 index 0000000..0119f49 Binary files /dev/null and b/tb/chip_top/csrc/rmar_llvm_0_1.o differ diff --git a/tb/chip_top/csrc/rmar_nd.o b/tb/chip_top/csrc/rmar_nd.o new file mode 100644 index 0000000..99927ba Binary files /dev/null and b/tb/chip_top/csrc/rmar_nd.o differ diff --git a/tb/chip_top/dbg_mod_data.dat b/tb/chip_top/dbg_mod_data.dat new file mode 100644 index 0000000..b8c49b0 --- /dev/null +++ b/tb/chip_top/dbg_mod_data.dat @@ -0,0 +1,4260 @@ +00000000 +03c4fc20 +f3e8ff9d +0c2f1097 +09dee31e +d81609d0 +2450243d +0f24c5df +bfd7116d +312631ab +1324bccc +bf610fa2 +29452ba5 +0e5ccec0 +d84c0aa2 +168f148f +02afeb98 +f596062b +052a0195 +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 +00000000 +fded04fc +0b63fbe9 +ee91f50f +01761e7c +2180e82f +d0e6ebac +07523ba0 +353dd82e +c004e3e9 +06f14588 +3654d9ad +c98fe69d +04c73313 +2101e780 +e375f530 +050413f6 +0769f66f +fa9e006e +00000000 diff --git a/tb/chip_top/dbg_mod_data_c.dat b/tb/chip_top/dbg_mod_data_c.dat new file mode 100644 index 0000000..7c76ada --- /dev/null +++ b/tb/chip_top/dbg_mod_data_c.dat @@ -0,0 +1,16 @@ +000000000000000000000000000000000000000000000000000000000000000015bcbd2315b842dec720d6ab464e0002c71d295215bcbd2315b842dec720d6ab +0000000000000000000000000000000000000000000000000000000000000000c720d6ab464e0002c71d295215bcbd2315b842dfc720d6ab464e0002c71d2952 +0000000000000000000000000000000000000000000000000000000000000000c71d295115bdbd2315b742dfc720d6ab464e0003c71d295215bcbd2315b742df +000000000000000000000000000000000000000000000000000000000000000015b742dfc720d6aa464e0003c71d295115bdbd2315b742dfc720d6aa464e0003 +0000000000000000000000000000000000000000000000000000000000000000464e0003c71c295015bdbd2315b742dfc720d6aa464e0003c71c295115bdbd23 +000000000000000000000000000000000000000000000000000000000000000015bdbd2315b642dfc721d6a9464e0004c71c295015bdbd2315b742dfc721d6a9 +0000000000000000000000000000000000000000000000000000000000000000c721d6a9464e0004c71c295015bebd2315b642e0c721d6a9464e0004c71c2950 +0000000000000000000000000000000000000000000000000000000000000000c71c295015bebd2315b642e0c721d6a9464e0004c71c295015bebd2315b642e0 +000000000000000000000000000000000000000000000000000000000000000015b542e0c721d6a8464e0005c71c294f15bebd2315b642e0c721d6a9464e0004 +0000000000000000000000000000000000000000000000000000000000000000464e0005c71b294f15bfbd2415b542e0c721d6a8464e0005c71c294f15bebd24 +000000000000000000000000000000000000000000000000000000000000000015bfbd2415b542e0c722d6a8464e0005c71b294f15bfbd2415b542e0c722d6a8 +0000000000000000000000000000000000000000000000000000000000000000c722d6a8464e0006c71b294f15c0bd2415b542e0c722d6a8464e0005c71b294f +0000000000000000000000000000000000000000000000000000000000000000c71b294e15c0bd2415b442e0c722d6a7464e0006c71b294f15c0bd2415b442e0 +000000000000000000000000000000000000000000000000000000000000000015b342e0c722d6a7464e0007c71b294e15c0bd2415b442e0c722d6a7464e0006 +0000000000000000000000000000000000000000000000000000000000000000464e0007c71a294e15c1bd2415b342e0c722d6a7464e0007c71b294e15c0bd24 +000000000000000000000000000000000000000000000000000000000000000015c1bd2415b342e0c723d6a7464e0007c71a294e15c1bd2415b342e0c722d6a7 diff --git a/tb/chip_top/files.f b/tb/chip_top/files.f new file mode 100644 index 0000000..41a20c7 --- /dev/null +++ b/tb/chip_top/files.f @@ -0,0 +1,94 @@ +../../rtl/memory/sram_if.sv +../../rtl/awg/awg_ctrl.v +../../rtl/awg/awg_top.sv +../../rtl/awg/codeword_decode.v +../../rtl/awg/ctrl_regfile.v +../../rtl/awg/param_lut.sv +../../rtl/awg/modout_mux.v +../../rtl/clk/intpll_regfile.v +../../rtl/comm/syncer.v +../../rtl/comm/sirv_gnrl_dffs.v +../../rtl/comm/sirv_gnrl_xchecker.v +../../rtl/dac_regfile/dac_regfile.v +../../rtl/debug/debug_sample.sv +../../rtl/debug/debug_top.sv +../../rtl/define/chip_define.v +../../rtl/define/chip_undefine.v +../../rtl/memory/dpram.v +../../rtl/memory/dpram_model.v +../../rtl/memory/sram_dmux.sv +../../rtl/memory/tsdn28hpcpuhdb128x128m4mw_170a_ffg0p99v0c.v +../../rtl/memory/tsdn28hpcpuhdb4096x32m4mw_170a_ffg0p99v0c.v +../../rtl/memory/tsdn28hpcpuhdb64x32m4mw_170a_ffg0p99v0c.v +../../rtl/memory/tsmc_dpram.v +../../rtl/io/tphn28hpcpgv18.v +../../rtl/io/iopad.v +../../rtl/modem/ampmod.v +../../rtl/modem/baisset.v +../../rtl/modem/freqmod.v +../../rtl/nco/coef_c.v +../../rtl/nco/coef_s.v +../../rtl/nco/cos_op.v +../../rtl/nco/nco.v +../../rtl/nco/nco_ch1.v +../../rtl/nco/p_nco.v +../../rtl/nco/p_nco_ch1.v +../../rtl/nco/ph2amp.v +../../rtl/nco/pipe_acc_48bit.v +../../rtl/nco/pipe_add_48bit.v +../../rtl/nco/sin_op.v +../../rtl/perips/DW03_updn_ctr.v +../../rtl/perips/mcu_regfile.sv +../../rtl/perips/qbmcu_busdecoder.v +../../rtl/qubitmcu/qbmcu.v +../../rtl/qubitmcu/qbmcu_datalock.v +../../rtl/qubitmcu/qbmcu_decode.v +../../rtl/qubitmcu/qbmcu_defines.v +../../rtl/qubitmcu/qbmcu_exu.v +../../rtl/qubitmcu/qbmcu_exu_alu.v +../../rtl/qubitmcu/qbmcu_exu_bjp.v +../../rtl/qubitmcu/qbmcu_exu_dpath.v +../../rtl/qubitmcu/qbmcu_exu_ext.v +../../rtl/qubitmcu/qbmcu_exu_lsuagu.v +../../rtl/qubitmcu/qbmcu_fsm.v +../../rtl/qubitmcu/qbmcu_ifu.v +../../rtl/qubitmcu/qbmcu_regfile.v +../../rtl/qubitmcu/qbmcu_undefines.v +../../rtl/qubitmcu/qbmcu_wbck.v +../../rtl/rstgen/rst_gen_unit.v +../../rtl/rstgen/rst_sync.v +../../rtl/spi/spi_bus_decoder.sv +../../rtl/spi/spi_pll.v +../../rtl/spi/spi_slave.v +../../rtl/spi/spi_sys.v +../../rtl/sync/sync_buf.sv +../../rtl/system_regfile/system_regfile.v +../../rtl/top/channel_top.sv +../../rtl/top/digital_top.sv +../../rtl/top/xyz_chip_top.v +../../rtl/xy_dsp/dacif/dacif.v +../../rtl/xy_dsp/dsp_top/xy_dsp.v +../../rtl/xy_dsp/duc/duc_hb1_pipe_shift.v +../../rtl/xy_dsp/duc/duc_hb1_top.v +../../rtl/xy_dsp/duc/duc_hb2_pipe_shift.v +../../rtl/xy_dsp/duc/duc_hb2_top_s.v +../../rtl/xy_dsp/duc/duc_hb3_pipe_shift.v +../../rtl/xy_dsp/duc/duc_hb3_top_s2.v +../../rtl/xy_dsp/duc/duc_hb4_pipe_shift.v +../../rtl/xy_dsp/duc/duc_hb4_top_s3.v +../../rtl/xy_dsp/duc/duc4.v +../../rtl/xy_dsp/qam/qam_top.v +../../rtl/xy_dsp/qam/ssb.v +../../rtl/top/z_data_mux.v +../../rtl/dem/DAC_DEM.v +../../rtl/dem/DAC_DEM_16.v +../../rtl/dem/DAC_DEM_4.v +../../sim/chip_top/TB.sv +../../sim/chip_top/DW_mult_pipe.v +../../sim/chip_top/DW01_addsub.v +../../sim/chip_top/DW02_mult.v +../../sim/chip_top/clk_gen.v +../../sim/chip_top/spi_if.sv +../../sim/chip_top/thermo15_binary4.v +../../sim/chip_top/thermo7_binary3.v +../../sim/chip_top/thermo2binary_top.v diff --git a/tb/chip_top/novas.conf b/tb/chip_top/novas.conf new file mode 100644 index 0000000..e7d6c82 --- /dev/null +++ b/tb/chip_top/novas.conf @@ -0,0 +1,131 @@ +[QwMainWindow] +window\Verdi_1\layout="@ByteArray(\0\0\0\xff\0\x3\x14Q\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x2\x13\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x3H\0\0\0\x89\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\xe9\0\0\0\xc6\0\0\0k\0\0\0k\xfc\0\0\x3N\0\0\x6\xb2\0\0\0\xbf\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x4\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\x1\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x33\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x34\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x35\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\0\0\0\x3\0\0\n\0\0\0\x2\xd2\xfc\x1\0\0\0\x1\xfc\0\0\0\0\0\0\n\0\0\0\x2,\0\xff\xff\xff\xfa\0\0\0\x2\x1\0\0\0\x3\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\x1\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\x1[\0\xff\xff\xff\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x3\x16\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +window\Verdi_1\geometry=@ByteArray(\x1\xd9\xd0\xcb\0\x1\0\0\xff\xff\xff\xff\0\0\0\x1b\0\0\n\0\0\0\x5z\0\0\0\0\0\0\0\0\xff\xff\xff\xfe\xff\xff\xff\xfe\0\0\0\0\x2\0) +window\Verdi_1\menubar=true +window\Verdi_1\splitters\tbvConstrDbgSplitter\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x2\xff\xff\xff\xff\xff\xff\xff\xff\x1\0\0\0\x6\x1\0\0\0\x1) +window\Verdi_1\splitters\tbvConstrRerandSplitter\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x2\xff\xff\xff\xff\xff\xff\xff\xff\x1\0\0\0\x6\x1\0\0\0\x2) +window\Verdi_1\splitters\tbvConstrOriginSplitter\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x2\xff\xff\xff\xff\xff\xff\xff\xff\x1\0\0\0\x6\x1\0\0\0\x2) +window\Verdi_1\splitters\ThreadPane\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x2\xff\xff\xff\xff\xff\xff\xff\xff\x1\0\0\0\x6\x1\0\0\0\x2) +window\Verdi_1\splitters\tbvInteractiveSplitter\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x2\xff\xff\xff\xff\xff\xff\xff\xff\x1\0\0\0\x6\x1\0\0\0\x2) +window\Verdi_1\splitters\tbvVSimSplitter\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x2\xff\xff\xff\xff\xff\xff\xff\xff\x1\0\0\0\x6\x1\0\0\0\x2) +window\Verdi_1\splitters\tbvTBHSplitter\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x2\xff\xff\xff\xff\xff\xff\xff\xff\x1\0\0\0\x6\x1\0\0\0\x2) +window\nSchema_3\layout=@ByteArray(\0\0\0\xff\0\x3\x14Q\xfd\0\0\0\0\0\0\x6\xb2\0\0\x2\r\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x4\0\0\0\x2\0\0\0\v\0\0\0\x10\0S\0\x43\0H\0_\0V\0I\0\x45\0W\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x10\0S\0\x43\0H\0_\0\x45\0\x44\0I\0T\0\0\0\0\xab\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x10\0S\0\x43\0H\0_\0H\0I\0\x45\0R\x1\0\0\0\xab\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x12\0S\0\x43\0H\0_\0T\0R\0\x41\0\x43\0\x45\x1\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\f\0S\0\x43\0H\0_\0\x42\0\x41\x1\0\0\x2\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0S\0\x43\0H\0_\0P\0O\0W\0\x45\0R\0_\0S\0T\0\x41\0T\0U\0S\0_\0I\0N\0\x46\0O\0\0\0\x3\x66\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0S\0\x43\0H\0_\0P\0O\0W\0\x45\0R\0_\0\x44\0O\0M\0\x41\0I\0N\0_\0I\0N\0\x46\0O\0\0\0\x3\xce\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x34\0S\0\x43\0H\0_\0P\0O\0W\0\x45\0R\0_\0S\0I\0G\0N\0\x41\0L\0_\0T\0Y\0P\0\x45\0_\0I\0N\0\x46\0O\0\0\0\x4\x43\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0S\0\x43\0H\0_\0P\0O\0W\0\x45\0R\0_\0\x43\0\x45\0L\0L\0_\0T\0Y\0P\0\x45\0_\0I\0N\0\x46\0O\0\0\0\x4`\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x34\0S\0\x43\0H\0_\0S\0P\0I\0\x43\0\x45\0_\0S\0I\0G\0N\0\x41\0L\0_\0T\0Y\0P\0\x45\0_\0I\0N\0\x46\0O\0\0\0\x4\xc4\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1a\0S\0\x43\0H\0_\0\x43\0L\0O\0\x43\0K\0_\0M\0\x41\0P\0\0\0\x5\x19\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0.\0S\0\x43\0H\0_\0Q\0U\0I\0\x43\0K\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x32\0_\0P\0O\0I\0N\0T\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x32\0S\0\x45\0L\0\x45\0\x43\0T\0I\0O\0N\0_\0M\0\x45\0S\0S\0\x41\0G\0\x45\0_\0T\0O\0O\0L\0\x42\0\x41\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x38\0P\0R\0\x45\0S\0\x45\0L\0\x45\0\x43\0T\0I\0O\0N\0_\0M\0\x45\0S\0S\0\x41\0G\0\x45\0_\0T\0O\0O\0L\0\x42\0\x41\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0) +window\nSchema_3\geometry=@ByteArray(\x1\xd9\xd0\xcb\0\x1\0\0\0\0\0\0\0\0\0\x1b\0\0\x6\xb1\0\0\x2Y\0\0\0\0\0\0\0\x1b\0\0\x6\xb1\0\0\x2Y\0\0\0\0\0\0) +window\nSchema_3\menubar=true +window\nSchema_3\splitters\splitDrawAndProperty\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x3\xff\xff\xff\xff\0\0\0\0\xff\xff\xff\xff\x1\0\0\0\x6\x1\0\0\0\x1) +window\nSchema_3\splitters\splitPropertyAndRightDock\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x2\xff\xff\xff\xff\xff\xff\xff\xff\x1\0\0\0\x6\x1\0\0\0\x2) +window\nSchema_3\splitters\splitDrawAndMinimap\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x3\0\0\0\x1e\xff\xff\xff\xff\xff\xff\xff\xff\x1\0\0\0\x6\x1\0\0\0\x2) +window\nSchema_3\splitters\splitPropertyAndBottomDock\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x2\xff\xff\xff\xff\xff\xff\xff\xff\x1\0\0\0\x6\x1\0\0\0\x1) +window\nSchema_4\layout=@ByteArray(\0\0\0\xff\0\x3\x14Q\xfd\0\0\0\0\0\0\x6\xb2\0\0\x3\xd3\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x4\0\0\0\x2\0\0\0\v\0\0\0\x10\0S\0\x43\0H\0_\0V\0I\0\x45\0W\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x10\0S\0\x43\0H\0_\0\x45\0\x44\0I\0T\0\0\0\0\xab\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x10\0S\0\x43\0H\0_\0H\0I\0\x45\0R\x1\0\0\0\xab\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x12\0S\0\x43\0H\0_\0T\0R\0\x41\0\x43\0\x45\x1\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\f\0S\0\x43\0H\0_\0\x42\0\x41\x1\0\0\x2\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0S\0\x43\0H\0_\0P\0O\0W\0\x45\0R\0_\0S\0T\0\x41\0T\0U\0S\0_\0I\0N\0\x46\0O\0\0\0\x3\x66\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0S\0\x43\0H\0_\0P\0O\0W\0\x45\0R\0_\0\x44\0O\0M\0\x41\0I\0N\0_\0I\0N\0\x46\0O\0\0\0\x3\xce\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x34\0S\0\x43\0H\0_\0P\0O\0W\0\x45\0R\0_\0S\0I\0G\0N\0\x41\0L\0_\0T\0Y\0P\0\x45\0_\0I\0N\0\x46\0O\0\0\0\x4\x43\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0S\0\x43\0H\0_\0P\0O\0W\0\x45\0R\0_\0\x43\0\x45\0L\0L\0_\0T\0Y\0P\0\x45\0_\0I\0N\0\x46\0O\0\0\0\x4`\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x34\0S\0\x43\0H\0_\0S\0P\0I\0\x43\0\x45\0_\0S\0I\0G\0N\0\x41\0L\0_\0T\0Y\0P\0\x45\0_\0I\0N\0\x46\0O\0\0\0\x4\xc4\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1a\0S\0\x43\0H\0_\0\x43\0L\0O\0\x43\0K\0_\0M\0\x41\0P\0\0\0\x5\x19\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0.\0S\0\x43\0H\0_\0Q\0U\0I\0\x43\0K\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x32\0_\0P\0O\0I\0N\0T\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x32\0S\0\x45\0L\0\x45\0\x43\0T\0I\0O\0N\0_\0M\0\x45\0S\0S\0\x41\0G\0\x45\0_\0T\0O\0O\0L\0\x42\0\x41\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x38\0P\0R\0\x45\0S\0\x45\0L\0\x45\0\x43\0T\0I\0O\0N\0_\0M\0\x45\0S\0S\0\x41\0G\0\x45\0_\0T\0O\0O\0L\0\x42\0\x41\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0) +window\nSchema_4\geometry=@ByteArray(\x1\xd9\xd0\xcb\0\x1\0\0\0\0\0\0\0\0\0\x1b\0\0\x6\xb1\0\0\x4\x1f\0\0\0\0\0\0\0\x1b\0\0\x6\xb1\0\0\x4\x1f\0\0\0\0\0\0) +window\nSchema_4\menubar=true +window\nSchema_4\splitters\splitDrawAndProperty\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x3\xff\xff\xff\xff\0\0\0\0\xff\xff\xff\xff\x1\0\0\0\x6\x1\0\0\0\x1) +window\nSchema_4\splitters\splitPropertyAndRightDock\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x2\xff\xff\xff\xff\xff\xff\xff\xff\x1\0\0\0\x6\x1\0\0\0\x2) +window\nSchema_4\splitters\splitDrawAndMinimap\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x3\0\0\0\x1e\xff\xff\xff\xff\xff\xff\xff\xff\x1\0\0\0\x6\x1\0\0\0\x2) +window\nSchema_4\splitters\splitPropertyAndBottomDock\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x2\xff\xff\xff\xff\xff\xff\xff\xff\x1\0\0\0\x6\x1\0\0\0\x1) +window\nSchema_5\layout=@ByteArray(\0\0\0\xff\0\x3\x14Q\xfd\0\0\0\0\0\0\x6\xb2\0\0\x2\f\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x4\0\0\0\x2\0\0\0\v\0\0\0\x10\0S\0\x43\0H\0_\0V\0I\0\x45\0W\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x10\0S\0\x43\0H\0_\0\x45\0\x44\0I\0T\0\0\0\0\xab\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x10\0S\0\x43\0H\0_\0H\0I\0\x45\0R\x1\0\0\0\xab\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x12\0S\0\x43\0H\0_\0T\0R\0\x41\0\x43\0\x45\x1\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\f\0S\0\x43\0H\0_\0\x42\0\x41\x1\0\0\x2\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0S\0\x43\0H\0_\0P\0O\0W\0\x45\0R\0_\0S\0T\0\x41\0T\0U\0S\0_\0I\0N\0\x46\0O\0\0\0\x3\x66\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0S\0\x43\0H\0_\0P\0O\0W\0\x45\0R\0_\0\x44\0O\0M\0\x41\0I\0N\0_\0I\0N\0\x46\0O\0\0\0\x3\xce\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x34\0S\0\x43\0H\0_\0P\0O\0W\0\x45\0R\0_\0S\0I\0G\0N\0\x41\0L\0_\0T\0Y\0P\0\x45\0_\0I\0N\0\x46\0O\0\0\0\x4\x43\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0S\0\x43\0H\0_\0P\0O\0W\0\x45\0R\0_\0\x43\0\x45\0L\0L\0_\0T\0Y\0P\0\x45\0_\0I\0N\0\x46\0O\0\0\0\x4`\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x34\0S\0\x43\0H\0_\0S\0P\0I\0\x43\0\x45\0_\0S\0I\0G\0N\0\x41\0L\0_\0T\0Y\0P\0\x45\0_\0I\0N\0\x46\0O\0\0\0\x4\xc4\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1a\0S\0\x43\0H\0_\0\x43\0L\0O\0\x43\0K\0_\0M\0\x41\0P\0\0\0\x5\x19\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0.\0S\0\x43\0H\0_\0Q\0U\0I\0\x43\0K\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x32\0_\0P\0O\0I\0N\0T\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x32\0S\0\x45\0L\0\x45\0\x43\0T\0I\0O\0N\0_\0M\0\x45\0S\0S\0\x41\0G\0\x45\0_\0T\0O\0O\0L\0\x42\0\x41\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x38\0P\0R\0\x45\0S\0\x45\0L\0\x45\0\x43\0T\0I\0O\0N\0_\0M\0\x45\0S\0S\0\x41\0G\0\x45\0_\0T\0O\0O\0L\0\x42\0\x41\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0) +window\nSchema_5\geometry=@ByteArray(\x1\xd9\xd0\xcb\0\x1\0\0\0\0\0\0\0\0\0\x1b\0\0\x6\xb1\0\0\x2X\0\0\0\0\0\0\0\x1b\0\0\x6\xb1\0\0\x2X\0\0\0\0\0\0) +window\nSchema_5\menubar=true +window\nSchema_5\splitters\splitDrawAndProperty\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x3\xff\xff\xff\xff\0\0\0\0\xff\xff\xff\xff\x1\0\0\0\x6\x1\0\0\0\x1) +window\nSchema_5\splitters\splitPropertyAndRightDock\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x2\xff\xff\xff\xff\xff\xff\xff\xff\x1\0\0\0\x6\x1\0\0\0\x2) +window\nSchema_5\splitters\splitDrawAndMinimap\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x3\0\0\0\x1e\xff\xff\xff\xff\xff\xff\xff\xff\x1\0\0\0\x6\x1\0\0\0\x2) +window\nSchema_5\splitters\splitPropertyAndBottomDock\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x2\xff\xff\xff\xff\xff\xff\xff\xff\x1\0\0\0\x6\x1\0\0\0\x1) +window\nWave_2\layout="@ByteArray(\0\0\0\xff\0\x3\x14Q\xfd\0\0\0\0\0\0\n\0\0\0\x2j\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x2\0\0\0\x2\0\0\0\f\0\0\0\x12\0W\0\x41\0V\0\x45\0_\0O\0P\0\x45\0N\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x12\0W\0\x41\0V\0\x45\0_\0\x45\0\x44\0I\0T\x1\0\0\0?\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x16\0W\0\x41\0V\0\x45\0_\0\x43\0U\0R\0S\0O\0R\x1\0\0\0\xb4\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x12\0W\0\x41\0V\0\x45\0_\0V\0I\0\x45\0W\x1\0\0\x2\x46\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\"\0W\0\x41\0V\0\x45\0_\0S\0\x45\0\x41\0R\0\x43\0H\0_\0\x45\0V\0\x45\0N\0T\x1\0\0\x2\xa0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0W\0\x41\0V\0\x45\0_\0R\0\x45\0P\0L\0\x41\0Y\0_\0S\0I\0M\0\0\0\x2\xcb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x12\0W\0\x41\0V\0\x45\0_\0G\0O\0T\0O\x1\0\0\x3<\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0W\0\x41\0V\0\x45\0_\0G\0O\0T\0O\0_\0N\0\x41\0M\0\x45\0\x44\0_\0M\0\x41\0R\0K\0\x45\0R\x1\0\0\x3\xba\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0W\0\x41\0V\0\x45\0_\0T\0R\0\x41\0N\0S\0\x41\0\x43\0T\0I\0O\0N\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0W\0\x41\0V\0\x45\0_\0\x45\0X\0P\0L\0O\0R\0\x45\0_\0P\0R\0O\0P\0\x45\0R\0T\0Y\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0W\0\x41\0V\0\x45\0_\0\x46\0I\0N\0\x44\0_\0S\0I\0G\0N\0\x41\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x18\0W\0\x41\0V\0\x45\0_\0P\0R\0I\0M\0\x41\0R\0Y\0\0\0\x3`\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x32\0S\0\x45\0L\0\x45\0\x43\0T\0I\0O\0N\0_\0M\0\x45\0S\0S\0\x41\0G\0\x45\0_\0T\0O\0O\0L\0\x42\0\x41\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +window\nWave_2\geometry=@ByteArray(\x1\xd9\xd0\xcb\0\x1\0\0\0\0\0\0\0\0\0\x1b\0\0\t\xff\0\0\x2\xb6\0\0\0\0\0\0\0\x1b\0\0\t\xff\0\0\x2\xb6\0\0\0\0\0\0) +window\nWave_2\menubar=true +window\nWave_2\splitters\splitter_5\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\x2j\x1\0\0\0\x1\0\0\0\0\x2) +window\nWave_2\splitters\splitter_2\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x2\0\0\x1\x34\0\0\b\xcc\x1\0\0\0\x1\0\0\0\0\x1) +window\nWave_2\splitters\splitter\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x3\0\0\0\x41\0\0\0\x1\0\0\b\x88\x1\0\0\0\x1\0\0\0\0\x1) +window\nWave_2\splitters\Pane_Upper\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x2\0\0\x1\x34\0\0\b\xc9\x1\0\0\0\x1\0\0\0\0\x1) +window\nWave_2\splitters\splitter_3\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x2\xff\xff\xff\xff\xff\xff\xff\xff\x1\0\0\0\x1\0\0\0\0\x1) +window\nWave_2\splitters\wholeSplitter\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x3\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\x1\0\0\0\x6\x1\0\0\0\x1) +window\nWave_2\splitters\middleSplitter\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x2\xff\xff\xff\xff\xff\xff\xff\xff\x1\0\0\0\x6\x1\0\0\0\x2) + +[qBaseWindowStateGroup] +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qDockerWindow_qDockContentType\Verdi=1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qDockerWindow_qDockContentType\nWave=1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qDockerWindow_qDockContentType\nSchema=3 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qDockerWindow_qDockContentType\hdlHier=1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qDockerWindow_qDockContentType\hdlSrc=1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qDockerWindow_qDockContentType\messageWindow=1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qDockerWindow_qDockContentType\svtbHier=1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qDockerWindow_qDockContentType\OneSearch=1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qDockerWindowMgr_saveDockerChildList\Verdi_1=10 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qDockerWindowMgr_saveDockerChildList\Verdi_1_0=widgetDock_hdlHier_1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qDockerWindowMgr_saveDockerChildList\Verdi_1_1=widgetDock_messageWindow_1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qDockerWindowMgr_saveDockerChildList\Verdi_1_2=widgetDock_hdlSrc_1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qDockerWindowMgr_saveDockerChildList\Verdi_1_3=widgetDock_signalList_1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qDockerWindowMgr_saveDockerChildList\Verdi_1_4=widgetDock_svtbHier_1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qDockerWindowMgr_saveDockerChildList\Verdi_1_5=windowDock_OneSearch_1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qDockerWindowMgr_saveDockerChildList\Verdi_1_6=windowDock_nWave_1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qDockerWindowMgr_saveDockerChildList\Verdi_1_7=windowDock_nSchema_1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qDockerWindowMgr_saveDockerChildList\Verdi_1_8=windowDock_nSchema_2 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qDockerWindowMgr_saveDockerChildList\Verdi_1_9=windowDock_nSchema_3 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\widgetDock_hdlHier_1\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\widgetDock_hdlHier_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\widgetDock_hdlHier_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\widgetDock_hdlHier_1\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\widgetDock_messageWindow_1\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\widgetDock_messageWindow_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\widgetDock_messageWindow_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\widgetDock_messageWindow_1\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\widgetDock_hdlSrc_1\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\widgetDock_hdlSrc_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\widgetDock_hdlSrc_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\widgetDock_hdlSrc_1\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\widgetDock_signalList_1\isVisible=false +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\widgetDock_svtbHier_1\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\widgetDock_svtbHier_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\widgetDock_svtbHier_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\widgetDock_svtbHier_1\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\windowDock_OneSearch_1\isNestedWindow=1 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\windowDock_OneSearch_1\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\windowDock_OneSearch_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\windowDock_OneSearch_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\windowDock_OneSearch_1\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\windowDock_nWave_1\isNestedWindow=1 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\windowDock_nWave_1\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\windowDock_nWave_1\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\windowDock_nWave_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\windowDock_nWave_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\windowDock_nWave_1\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\windowDock_nSchema_1\isNestedWindow=1 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\windowDock_nSchema_1\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\windowDock_nSchema_1\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\windowDock_nSchema_1\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\windowDock_nSchema_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\windowDock_nSchema_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\windowDock_nSchema_1\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\windowDock_nSchema_2\isNestedWindow=1 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\windowDock_nSchema_2\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\windowDock_nSchema_2\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\windowDock_nSchema_2\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\windowDock_nSchema_2\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\windowDock_nSchema_2\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\windowDock_nSchema_2\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\windowDock_nSchema_3\isNestedWindow=1 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\windowDock_nSchema_3\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\windowDock_nSchema_3\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\windowDock_nSchema_3\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\windowDock_nSchema_3\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\windowDock_nSchema_3\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\windowDock_nSchema_3\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\ProductVersion=201809 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\Layout="@ByteArray(\0\0\0\xff\0\0\0\0\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x2\x13\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x3H\0\0\0\x89\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x2\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0h\0\x64\0l\0H\0i\0\x65\0r\0_\0\x31\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0*\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0s\0v\0t\0\x62\0H\0i\0\x65\0r\0_\0\x31\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0s\0i\0g\0n\0\x61\0l\0L\0i\0s\0t\0_\0\x31\0\0\0\0\xe9\0\0\0\xc6\0\0\0k\0\0\0k\xfc\0\0\x3N\0\0\x6\xb2\0\0\0\xbf\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x4\xfb\0\0\0&\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0h\0\x64\0l\0S\0r\0\x63\0_\0\x31\x1\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x31\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x33\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\0\0\0\x3\0\0\n\0\0\0\x2\xd2\xfc\x1\0\0\0\x1\xfc\0\0\0\0\0\0\n\0\0\0\x2,\0\xff\xff\xff\xfa\0\0\0\x2\x1\0\0\0\x3\xfb\0\0\0\x34\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0m\0\x65\0s\0s\0\x61\0g\0\x65\0W\0i\0n\0\x64\0o\0w\0_\0\x31\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0,\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\0_\0\x31\x1\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x31\x1\0\0\0\0\xff\xff\xff\xff\0\0\x1[\0\xff\xff\xff\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x3\x16\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\isNestedWindow=0 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\size=@Size(2560 1337) +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\geometry_x=-1 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\geometry_y=27 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\geometry_width=2560 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\geometry_height=1337 + +[qBaseWindow_saveRestoreSession_group] +10=/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/chip_top/verdiLog/novas_autosave.ses + +[qDockerWindow_C] +Verdi_1\position.x=-1 +Verdi_1\position.y=27 +Verdi_1\width=2560 +Verdi_1\height=1337 diff --git a/tb/chip_top/novas.rc b/tb/chip_top/novas.rc new file mode 100644 index 0000000..b8afaf9 --- /dev/null +++ b/tb/chip_top/novas.rc @@ -0,0 +1,1315 @@ +@verdi rc file Version 1.0 +[Library] +work = ./work +[Annotation] +3D_Active_Annotation = FALSE +[CommandSyntax.finsim] +InvokeCommand = +FullFileName = TRUE +Separator = . +SimPromptSign = ">" +HierNameLevel = 1 +RunContinue = "continue" +Finish = "quit" +UseAbsTime = FALSE +NextTime = "run 1" +NextNTime = "run ${SimBPTime}" +NextEvent = "run 1" +Reset = +ObjPosBreak = "break posedge ${SimBPObj}" +ObjNegBreak = "break negedge ${SimBPObj}" +ObjAnyBreak = "break change ${SimBPObj}" +ObjLevelBreak = +LineBreak = "breakline ${SimBPFile} ${SimBPLine}" +AbsTimeBreak = "break abstimeaf ${SimBPTime}" +RelTimeBreak = "break reltimeaf ${SimBPTime}" +EnableBP = "breakon ${SimBPId}" +DisableBP = "breakoff ${SimBPId}" +DeleteBP = "breakclr ${SimBPId}" +DeleteAllBP = "breakclr" +SimSetScope = "cd ${SimDmpObj}" +[CommandSyntax.ikos] +InvokeCommand = "setvar debussy true;elaborate -p ${SimTop} -s ${SimArch}; run until 0;fsdbInteractive; " +FullFileName = TRUE +NeedTimeUnit = TRUE +NormalizeTimeUnit = TRUE +Separator = / +HierNameLevel = 2 +RunContinue = "run" +Finish = "exit" +NextTime = "run ${SimBPTime} ${SimTimeUnit}" +NextNTime = "run for ${SimBPTime} ${SimTimeUnit}" +NextEvent = "step 1" +Reset = "reset" +ObjPosBreak = "stop if ${SimBPObj} = \"'1'\"" +ObjNegBreak = "stop if ${SimBPObj} = \"'0'\"" +ObjAnyBreak = +ObjLevelBreak = "stop if ${SimBPObj} = ${SimBPValue}" +LineBreak = "stop at ${SimBPFile}:${SimBPLine}" +AbsTimeBreak = +RelTimeBreak = +EnableBP = "enable ${SimBPId}" +DisableBP = "disable ${SimBPId}" +DeleteBP = "delete ${SimBPId}" +DeleteAllBP = "delete *" +[CommandSyntax.verisity] +InvokeCommand = +FullFileName = FALSE +Separator = . +SimPromptSign = "> " +HierNameLevel = 1 +RunContinue = "." +Finish = "$finish;" +NextTime = "$db_steptime(1);" +NextNTime = "$db_steptime(${SimBPTime});" +NextEvent = "$db_step;" +SimSetScope = "$scope(${SimDmpObj});" +Reset = "$reset;" +ObjPosBreak = "$db_breakonposedge(${SimBPObj});" +ObjNegBreak = "$db_breakonnegedge(${SimBPObj});" +ObjAnyBreak = "$db_breakwhen(${SimBPObj});" +ObjLevelBreak = "$db_breakwhen(${SimBPObj}, ${SimBPValue});" +LineBreak = "$db_breakatline(${SimBPLine}, ${SimBPScope}, \"${SimBPFile}\");" +AbsTimeBreak = "$db_breakbeforetime(${SimBPTime});" +RelTimeBreak = "$db_breakbeforetime(${SimBPTime});" +EnableBP = "$db_enablebreak(${SimBPId});" +DisableBP = "$db_disablebreak(${SimBPId});" +DeleteBP = "$db_deletebreak(${SimBPId});" +DeleteAllBP = "$db_deletebreak;" +FSDBInit = "$novasInteractive;" +FSDBDumpvars = "$novasDumpvars(0, ${SimDmpObj});" +FSDBDumpsingle = "$novasDumpsingle(${SimDmpObj});" +FSDBDumpvarsInFile = "$novasDumpvarsToFile(\"${SimDmpFile}\");" +FSDBDumpMem = "$novasDumpMemNow(${SimDmpObj}, ${SimDmpBegin}, ${SimDmpSize});" +[CoverageDetail] +cross_filter_limit = 1000 +branch_limit_vector_display = 50 +showgrid = TRUE +reuseFirst = TRUE +justify = TRUE +scrollbar_mode = per pane +test_combo_left_truncate = TRUE +instance_combo_left_truncate = TRUE +loop_navigation = TRUE +condSubExpr = 20 +tglMda = 1000 +linecoverable = 100000 +lineuncovered = 50000 +tglcoverable = 30000 +tgluncovered = 30000 +pendingMax = 1000 +show_full_more = FALSE +[CoverageHier] +showgrid = FALSE +[CoverageWeight] +Assert = 1 +Covergroup = 1 +Line = 1 +Condition = 1 +Toggle = 1 +FSM = 1 +Branch = 1 +[DesignTree] +IfShowModule = {TRUE, FALSE} +[DisabledMessages] +version = Verdi_O-2018.09-SP2 +[Editor] +editorName = TurboEditor +[Emacs] +EmacsFont = "Clean 14" +EmacsBG = white +EmacsFG = black +[Exclusion] +enableAsDefault = TRUE +saveAsDefault = TRUE +saveManually = TRUE +illegalBehavior = FALSE +DisplayExcludedItem = FALSE +adaptiveExclusion = TRUE +warningExcludeInstance = TRUE +favorite_exclude_annotation = "" +[FSM] +viewport = 65 336 387 479 +WndBk-FillColor = Gray3 +Background-FillColor = gray5 +prefKey_Link-FillColor = yellow4 +prefKey_Link-TextColor = black +Trap = red3 +Hilight = blue4 +Window = Gray3 +Selected = white +Trans. = green2 +State = black +Init. = black +SmartTips = TRUE +VectorFont = FALSE +StopAskBkgndColor = FALSE +ShowStateAction = FALSE +ShowTransAction = FALSE +ShowTransCond = FALSE +StateLable = NAME +StateValueRadix = ORIG +State-LineColor = ID_BLACK +State-LineWidth = 1 +State-FillColor = ID_BLUE2 +State-TextColor = ID_WHITE +Init_State-LineColor = ID_BLACK +Init_State-LineWidth = 2 +Init_State-FillColor = ID_YELLOW2 +Init_State-TextColor = ID_BLACK +Reset_State-LineColor = ID_BLACK +Reset_State-LineWidth = 2 +Reset_State-FillColor = ID_YELLOW7 +Reset_State-TextColor = ID_BLACK +Trap_State-LineColor = ID_RED2 +Trap_State-LineWidth = 2 +Trap_State-FillColor = ID_CYAN5 +Trap_State-TextColor = ID_RED2 +State_Action-LineColor = ID_BLACK +State_Action-LineWidth = 1 +State_Action-FillColor = ID_WHITE +State_Action-TextColor = ID_BLACK +Junction-LineColor = ID_BLACK +Junction-LineWidth = 1 +Junction-FillColor = ID_GREEN2 +Junction-TextColor = ID_BLACK +Connection-LineColor = ID_BLACK +Connection-LineWidth = 1 +Connection-FillColor = ID_GRAY5 +Connection-TextColor = ID_BLACK +prefKey_Port-LineColor = ID_BLACK +prefKey_Port-LineWidth = 1 +prefKey_Port-FillColor = ID_ORANGE6 +prefKey_Port-TextColor = ID_YELLOW2 +Transition-LineColor = ID_BLACK +Transition-LineWidth = 1 +Transition-FillColor = ID_WHITE +Transition-TextColor = ID_BLACK +Trans_Condition-LineColor = ID_BLACK +Trans_Condition-LineWidth = 1 +Trans_Condition-FillColor = ID_WHITE +Trans_Condition-TextColor = ID_ORANGE2 +Trans_Action-LineColor = ID_BLACK +Trans_Action-LineWidth = 1 +Trans_Action-FillColor = ID_WHITE +Trans_Action-TextColor = ID_GREEN2 +SelectedSet-LineColor = ID_RED2 +SelectedSet-LineWidth = 1 +SelectedSet-FillColor = ID_RED2 +SelectedSet-TextColor = ID_WHITE +StickSet-LineColor = ID_ORANGE5 +StickSet-LineWidth = 1 +StickSet-FillColor = ID_PURPLE6 +StickSet-TextColor = ID_BLACK +HilightSet-LineColor = ID_RED5 +HilightSet-LineWidth = 1 +HilightSet-FillColor = ID_RED7 +HilightSet-TextColor = ID_BLUE5 +ControlPoint-LineColor = ID_BLACK +ControlPoint-LineWidth = 1 +ControlPoint-FillColor = ID_WHITE +Bundle-LineColor = ID_BLACK +Bundle-LineWidth = 1 +Bundle-FillColor = ID_WHITE +Bundle-TextColor = ID_BLUE4 +QtBackground-FillColor = ID_GRAY6 +prefKey_Link-LineColor = ID_ORANGE2 +prefKey_Link-LineWidth = 1 +Selection-LineColor = ID_BLUE2 +Selection-LineWidth = 1 +[FSM_Dlg-Print] +Orientation = Landscape +[FileBrowser] +nWaveOpenFsdbDirHistory = "\"/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/chip_top/verdplus_000.fsdb\"" +[Form] +version = Verdi_O-2018.09-SP2 +wave/sigCPL.fm = 100,100,243,333 +[General] +autoSaveSession = FALSE +TclAutoSource = +cmd_enter_form = FALSE +SyncBrowserDir = TRUE +version = Verdi_O-2018.09-SP2 +SignalCaseInSensitive = FALSE +ShowWndCtntDuringResizing = FALSE +[GlobalProp] +ErrWindow_Font = Helvetica_M_R_12 +[Globals] +app_default_font = Bitstream Vera Sans,10,-1,5,50,0,0,0,0,0 +app_fixed_width_font = Courier,10,-1,5,50,0,0,0,0,0 +text_encoding = Unicode(utf8) +smart_resize = TRUE +smart_resize_child_limit = 2000 +tooltip_max_width = 200 +tooltip_max_height = 20 +tooltip_viewer_key = F3 +tooltip_display_time = 1000 +bookmark_name_length_limit = 12 +disable_tooltip = FALSE +auto_load_source = TRUE +max_array_size = 4096 +filter_when_typing = TRUE +filter_keep_children = TRUE +filter_syntax = Wildcards +filter_keystroke_interval = 800 +filter_case_sensitive = FALSE +filter_full_path = FALSE +load_detail_for_funcov = FALSE +sort_limit = 100000 +ignoreDBVersionChecking = FALSE +[HB] +ViewSchematic = FALSE +windowLayout = 0 0 804 500 182 214 804 148 +import_filter = *.v; *.vc; *.f +designTreeFont = *-adobe-courier-medium-r-*-*-12-*-*-*-*-*-iso8859-* +import_filter_vhdl = *.vhd; *.vhdl; *.f +import_default_language = Verilog +import_filter_verilog = *.v; *.vc; *.f +simulation_file_type = *.fsdb;*.fsdb.gz;*.fsdb.bz2;*.ff;*.dump +PrefetchViewableAnnot = TRUE +[Hier] +filterTimeout = 1500 +[ImportLiberty] +SearchPriority = .lib++ +bSkipStateCell = False +bImportPowerInfo = False +bSkipFFCell = False +bScpecifyCellNameCase = False +bSpecifyPinNameCase = False +CellNameToCase = +PinNameToCase = +[Language] +EditWindow_Font = COURIER12 +Background = ID_WHITE +Comment = ID_GRAY4 +Keyword = ID_BLUE5 +UserKeyword = ID_GREEN2 +Text = ID_BLACK +SelText = ID_WHITE +SelBackground = ID_BLUE2 +[Library.Ikos] +pack = ./work.lib++ +vital = ./work.lib++ +work = ./work.lib++ +std = ${dls_std}.lib++ +ieee = ${dls_ieee}.lib++ +synopsys = ${dls_synopsys}.lib++ +silc = ${dls_silc}.lib++ +ikos = ${dls_ikos}.lib++ +novas = ${VOYAGER_LIB_VHDL}/${VOYAGER_MACHINE}/novas.lib++ +[MDT] +ART_RF_SP = spr[0-9]*bx[0-9]* +ART_RF_2P = dpr[0-9]*bx[0-9]* +ART_SRAM_SP = spm[0-9]*bx[0-9]* +ART_SRAM_DP = dpm[0-9]*bx[0-9]* +VIR_SRAM_SP = hdsd1_[0-9]*x[0-9]*cm4sw1 +VIR_SRAM_DP = hdsd2_[0-9]*x[0-9]*cm4sw1 +VIR_RF_SP = rfsd1_[0-9]*x[0-9]*cm2sw0 +VIR_RF_DP = rfsd2_[0-9]*x[0-9]*cm2sw1 +VIR_STAR_SRAM_SP = shsd1_[0-9]*x[0-9]*cm4sw0 +[NPExpanding] +functiongroups = FALSE +modules = FALSE +[NPFilter] +showAssertion = TRUE +showCoverGroup = TRUE +showProperty = TRUE +showSequence = TRUE +showDollarUnit = TRUE +[OldFontRC] +Wave_legend_window_font = -f COURIER12 -c ID_CYAN5 +Wave_value_window_font = -f COURIER12 -c ID_CYAN5 +Wave_curve_window_font = -f COURIER12 -c ID_CYAN5 +Wave_group_name_font = -f COURIER12 -c ID_GREEN5 +Wave_ruler_value_font = -f COURIER12 -c ID_CYAN5 +Wave_analog_ruler_value_font = -f COURIER12 -c ID_CYAN5 +Wave_comment_string_font = -f COURIER12 -c ID_RED5 +HB_designTreeFont = *-adobe-courier-medium-r-*-*-12-*-*-*-*-*-iso8859-* +Text_font = COURIER12 +nMemory_font = Fixed 14 +[OtherEditor] +cmd1 = "xterm -font 9x15 -fg black -bg gray -e" +name = "vi" +options = "+${CurLine} ${CurFullFileName}" +[Power] +PowerDownInstance = ID_GRAY1 +RetentionSignal = ID_YELLOW2 +IsolationSignal = ID_RED6 +LevelShiftedSignal = ID_GREEN6 +PowerSwitchObject = ID_ORANGE5 +AlwaysOnObject = ID_GREEN5 +PowerNet = ID_RED2 +GroundNet = ID_RED2 +SimulationOnly = ID_CYAN3 +SRSN/SPA = ID_CYAN3 +CNSSignal = ID_CYAN3 +RPTRSignal = ID_CYAN3 +AcknowledgeSignal = ID_CYAN3 +BoundaryPort = ID_CYAN3 +DisplayInstrumentedCell = TRUE +ShowCmdByFile = FALSE +ShowPstAnnot = FALSE +ShowIsoSymbol = TRUE +ExtractIsoSameNets = FALSE +AnnotateSignal = TRUE +HighlightPowerObject = TRUE +HighlightPowerDomain = TRUE +TraceThroughInstruLowPower = FALSE +BrightenPowerColorInSchematicWindow = FALSE +ShowAlias = FALSE +ShowVoltage = TRUE +MatchTreeNodesCaseInsensitive = FALSE +SearchHBNodeDynamically = FALSE +ContinueTracingSupplyOrLogicNet = FALSE +[Print] +PrinterName = lp +FileName = test.ps +PaperSize = A4 - 210x297 (mm) +ColorPrint = FALSE +[PropertyTools] +saveWaveformStat = TRUE +savePropStat = FALSE +savePropDtl = TRUE +[QtDialog] +QwInfoMsgDlg = 895,624,750,250 +openFileDlg = 969,507,602,483 +QwWarnMsgDlg = 979,700,600,250 +ActiveFileDialog = 1041,586,458,279 +SetWindowTimeUnitDialog = 1053,682,433,86 +QwUserAskDlg = 1118,667,324,134 +[Relationship] +hideRecursiceNode = FALSE +[Session Cache] +2 = string (session file name) +3 = string (session file name) +4 = string (session file name) +5 = string (session file name) +1 = /home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/chip_top/verdiLog/novas_autosave.ses +[Simulation] +scsPath = scsim +scsOption = +xlPath = verilog +xlOption = +ncPath = ncsim +ncOption = -f ncsim.args +osciPath = gdb +osciOption = +vcsPath = simv +vcsOption = +mtiPath = vsim +mtiOption = +vhncPath = ncsim +vhncOption = -log debussy.nc.log +mixncPath = ncsim +mixncOption = -log debussy.mixnc.log +speedsimPath = +speedsimOption = +mti_vlogPath = vsim +mti_vlogOption = novas_vlog +vcs_mixPath = simv +vcs_mixOption = -vhdlrun "-vhpi debussy:FSDBDumpCmd" +scs_mixPath = scsim +scs_mixOption = -vhpi debussy:FSDBDumpCmd +interactiveDebugging = {True, False} +KeepBreakPoints = False +ScsDebugAll = False +simType = {vcssv, xl, nc, vcs, mti, mti_vlog, vhnc, scs, mixnc} +thirdpartyIdx = -1 +iscCmdSep = FALSE +NoAppendOption = False +[SimulationPlus] +xlPath = verilog +xlOption = +ncPath = ncsim +ncOption = -f ncsim.args +vcsPath = simv +vcsOption = +mti_vlogPath = vsim +mti_vlogOption = novas_vlog +mtiPath = vsim +mtiOption = +vhncPath = ncsim +vhncOption = -log debussy.nc.log +speedsimPath = verilog +speedsimOption = +mixncPath = ncsim +mixncOption = -log debussy.mixnc.log +scsPath = scsim +scsOption = +vcs_mixPath = simv +vcs_mixOption = -vhdlrun "-vhpi debussy:FSDBDumpCmd" +scs_mixPath = scsim +scs_mixOption = -vhpi debussy:FSDBDumpCmd +vcs_svPath = simv +vcs_svOption = +simType = vcssv +thirdpartyIdx = -1 +interactiveDebugging = FALSE +KeepBreakPoints = FALSE +iscCmdSep = FALSE +ScsDebugAll = FALSE +NoAppendOption = FALSE +invokeSimPath = work +[SimulationPlus2] +eventDumpUnfinish = FALSE +[Source] +wordWrapOn = TRUE +viewReuse = TRUE +lineNumberOn = TRUE +warnOutdatedDlg = TRUE +showEncrypt = FALSE +loadInclude = FALSE +showColorForActive = FALSE +tabWidth = 8 +editor = vi +reload = Never +sync_active_to_source = TRUE +navigateAsColored = FALSE +navigateCovered = FALSE +navigateUncovered = TRUE +navigateExcluded = FALSE +not_ask_for_source_path = FALSE +expandMacroOn = TRUE +expandMacroInstancesThreshold = 10000 +[SourceVHDL] +vhSimType = ModelSim +ohSimType = VerilogXL +[TclShell] +nLineSize = 1024 +[Test] +verbose_progress = FALSE +[TestBenchBrowser] +-showUVMDynamicHierTreeWin = FALSE +[Text] +hdlTypeName = blue4 +hdlLibrary = blue4 +viewport = 396 392 445 487 +hdlOther = ID_BLACK +hdlComment = ID_GRAY1 +hdlKeyword = ID_BLUE5 +hdlEntity = ID_BLACK +hdlEntityInst = ID_BLACK +hdlSignal = ID_RED2 +hdlInSignal = ID_RED2 +hdlOutSignal = ID_RED2 +hdlInOutSignal = ID_RED2 +hdlOperator = ID_BLACK +hdlMinus = ID_BLACK +hdlSymbol = ID_BLACK +hdlString = ID_BLACK +hdlNumberBase = ID_BLACK +hdlNumber = ID_BLACK +hdlLiteral = ID_BLACK +hdlIdentifier = ID_BLACK +hdlSystemTask = ID_BLACK +hdlParameter = ID_BLACK +hdlIncFile = ID_BLACK +hdlDataFile = ID_BLACK +hdlCDSkipIf = ID_GRAY1 +hdlMacro = ID_BLACK +hdlMacroValue = ID_BLACK +hdlPlainText = ID_BLACK +hdlOvaId = ID_PURPLE2 +hdlPslId = ID_PURPLE2 +HvlEId = ID_BLACK +HvlVERAId = ID_BLACK +hdlEscSignal = ID_BLACK +hdlEscInSignal = ID_BLACK +hdlEscOutSignal = ID_BLACK +hdlEscInOutSignal = ID_BLACK +textBackgroundColor = ID_GRAY6 +textHiliteBK = ID_BLUE5 +textHiliteText = ID_WHITE +textTracedMark = ID_GREEN2 +textLineNo = ID_BLACK +textFoldedLineNo = ID_RED5 +textUserKeyword = ID_GREEN2 +textParaAnnotText = ID_BLACK +textFuncAnnotText = ID_BLUE2 +textAnnotText = ID_BLACK +textUserDefAnnotText = ID_BLACK +ComputedSignal = ID_PURPLE5 +textAnnotTextShadow = ID_WHITE +parenthesisBGColor = ID_YELLOW5 +codeInParenthesis = ID_CYAN5 +text3DLight = ID_WHITE +text3DShadow = ID_BLACK +textHvlDriver = ID_GREEN3 +textHvlLoad = ID_YELLOW3 +textHvlDriverLoad = ID_BLUE3 +irOutline = ID_RED2 +irDriver = ID_YELLOW5 +irLoad = ID_BLACK +irBookMark = ID_YELLOW2 +irIndicator = ID_WHITE +irBreakpoint = ID_GREEN5 +irCurLine = ID_BLUE5 +hdlVhEntity = ID_BLACK +hdlArchitecture = ID_BLACK +hdlPackage = ID_BLUE5 +hdlRefPackage = ID_BLUE5 +hdlAlias = ID_BLACK +hdlGeneric = ID_BLUE5 +specialAnnotShadow = ID_BLUE1 +hdlZeroInHead = ID_GREEN2 +hdlZeroInComment = ID_GREEN2 +hdlPslHead = ID_GRAY1 +hdlPslComment = ID_GRAY1 +hdlSynopsysHead = ID_GREEN2 +hdlSynopsysComment = ID_GREEN2 +pdmlIdentifier = ID_BLACK +pdmlCommand = ID_BLACK +pdmlMacro = ID_BLACK +font = COURIER12 +annotFont = Helvetica_M_R_10 +[Text.1] +viewport = -1 27 2560 1337 45 +[TextPrinter] +Orientation = Landscape +Indicator = FALSE +LineNum = TRUE +FontSize = 7 +Column = 2 +Annotation = TRUE +[Texteditor] +TexteditorFont = "Clean 14" +TexteditorBG = white +TexteditorFG = black +[ThirdParty] +ThirdPartySimTool = verisity surefire ikos finsim +[TurboEditor] +autoBackup = TRUE +[UserButton.mixnc] +Button1 = "Dump All Signals" "call fsdbDumpvars\n" +Button2 = "Next 1000 Time" "run 1000 -relative\n" +Button3 = "Next ? Time" "run ${Arg:Next Time} -relative\n" +Button4 = "Run Next" "run -next\n" +Button5 = "Run Step" "run -step\n" +Button6 = "Run Return" "run -return\n" +Button7 = "Show Variables" "value {${NCSelVars}}\n" +Button8 = "FSDB Ver" "call fsdbVersion" +Button9 = "Dump On" "call fsdbDumpon" +Button10 = "Dump Off" "call fsdbDumpoff" +Button11 = "All Tasks" "call" +Button12 = "Dump Selected Instance" "call fsdbDumpvars 1 ${SelInst}" +[UserButton.mti] +Button1 = "Dump All Signals" "fsdbDumpvars\n" +Button2 = "Next 1000 Time" "run 1000\n" +Button3 = "Next ? Time" "run ${Arg:Next Time}\n" +Button4 = "Show Variables" "exa ${SelVars}\n" +Button5 = "Force Variable" "force -freeze ${SelVar} ${Arg:New Value} 0\n" +Button6 = "Release Variable" "noforce ${SelVar}\n" +Button7 = "Deposit Variable" "force -deposit ${SelVar} ${Arg:New Value} 0\n" +[UserButton.mti_vlog] +Button1 = "Dump All Signals" "fsdbDumpvars\n" +Button2 = "Next 1000 Time" "run 1000\n" +Button3 = "Next ? Time" "run ${Arg:Next Time}\n" +Button4 = "Show Variables" "exa ${SelVars}\n" +Button5 = "Force Variable" "force -freeze ${SelVar} ${Arg:New Value} 0\n" +Button6 = "Release Variable" "noforce ${SelVar}\n" +Button7 = "Deposit Variable" "force -deposit ${SelVar} ${Arg:New Value} 0\n" +[UserButton.nc] +Button1 = "Dump All Signals" "call fsdbDumpvars\n" +Button2 = "Next 1000 Time" "run 1000 -relative\n" +Button3 = "Next ? Time" "run ${Arg:Next Time} -relative\n" +Button4 = "Run Next" "run -next\n" +Button5 = "Run Step" "run -step\n" +Button6 = "Run Return" "run -return\n" +Button7 = "Show Variables" "value {${NCSelVars}}\n" +[UserButton.scs] +Button1 = "Dump All Signals" "call fsdbDumpvars(0, \"${TopScope}\");\n" +Button2 = "Next 1000 Time" "run 1000 \n" +Button3 = "Next ? Time" "run ${Arg:Next Time} \n" +Button4 = "Run Step" "step\n" +Button5 = "Show Variables" "ls -v {${SelVars}}\n" +[UserButton.vhnc] +Button1 = "Dump All Signals" "call fsdbDumpvars\n" +Button2 = "Next 1000 Time" "run 1000 -relative\n" +Button3 = "Next ? Time" "run ${Arg:Next Time} -relative\n" +Button4 = "Run Next" "run -next\n" +Button5 = "Run Step" "run -step\n" +Button6 = "Run Return" "run -return\n" +Button7 = "Show Variables" "value {${NCSelVars}}\n" +[UserButton.xl] +Button13 = "Dump Off" "$fsdbDumpoff;\n" +Button12 = "Dump On" "$fsdbDumpon;\n" +Button11 = "Delete Focus" "$db_deletefocus(${treeSelScope});\n" +Button10 = "Set Focus" "$db_setfocus(${treeSelScope});\n" +Button9 = "Deposit Variable" "$deposit(${SelVar},${Arg:New Value});\n" +Button8 = "Release Variable" "release ${SelVar};\n" +Button7 = "Force Variable" "force ${SelVar} = ${Arg:New Value};\n" +Button6 = "Show Variables" "$showvars(${SelVars});\n" +Button5 = "Next ? Event" "$db_step(${Arg:Next Event});\n" +Button4 = "Next Event" "$db_step(1);\n" +Button3 = "Next ? Time" "#${Arg:Next Time} $stop;.\n" +Button2 = "Next 1000 Time" "#1000 $stop;.\n" +Button1 = "Dump All Signals" "$fsdbDumpvars;\n" +[VIA] +viaLogViewerDefaultRuleOneSearchForm = "share/VIA/Apps/PredefinedRules/Misc/Onesearch_rule.rc" +[VIA.oneSearch.preference] +DefaultDisplayTimeUnit = "1.000000ns" +DefaultLogTimeUnit = "1.000000ns" +[VIA.oneSearch.preference.vgifColumnSettingRC] +[VIA.oneSearch.preference.vgifColumnSettingRC.setting0] +parRuleSets = "" +[VIA.oneSearch.preference.vgifColumnSettingRC.setting0.column0] +name = Time +width = 60 +visualIndex = 0 +isHidden = TRUE +isUserChangeColumnVisible = FALSE +[VIA.oneSearch.preference.vgifColumnSettingRC.setting0.column1] +name = Code +width = 60 +visualIndex = 2 +isHidden = TRUE +isUserChangeColumnVisible = FALSE +[VIA.oneSearch.preference.vgifColumnSettingRC.setting0.column2] +name = Type +width = 60 +visualIndex = 3 +isHidden = TRUE +isUserChangeColumnVisible = FALSE +[VIA.oneSearch.preference.vgifColumnSettingRC.setting0.column3] +name = Message +width = 2000 +visualIndex = 4 +isHidden = FALSE +isUserChangeColumnVisible = FALSE +[VIA.oneSearch.preference.vgifColumnSettingRC.setting0.column4] +name = Severity +width = 60 +visualIndex = 1 +isHidden = TRUE +isUserChangeColumnVisible = FALSE +[Vi] +ViFont = "Clean 14" +ViBG = white +ViFG = black +[Wave] +ovaEventSuccessColor = -c ID_CYAN5 +ovaEventFailureColor = -c ID_RED5 +ovaBooleanSuccessColor = -c ID_CYAN5 +ovaBooleanFailureColor = -c ID_RED5 +ovaAssertSuccessColor = -c ID_GREEN5 +ovaAssertFailureColor = -c ID_RED5 +ovaForbidSuccessColor = -c ID_GREEN5 +SigGroupRuleFile = +DisplayFileName = FALSE +waveform_vertical_scroll_bar = TRUE +getSignalForm = 0 0 800 479 100 30 100 30 +viewPort = 0 27 2560 668 308 65 +signalSpacing = 5 +digitalSignalHeight = 15 +analogSignalHeight = 98 +commentSignalHeight = 98 +transactionSignalHeight = 98 +messageSignalHeight = 98 +minCompErrWidth = 4 +DragZoomTolerance = 4 +maxTransExpandedLayer = 10 +WaveMaxPoint = 512 +legendBackground = -c ID_BLACK +valueBackground = -c ID_BLACK +curveBackground = -c ID_BLACK +getSignalSignalList_BackgroundColor = -c ID_GRAY6 +glitchColor = -c ID_RED5 +cursor = -c ID_YELLOW5 -lw 1 -ls long_dashed +marker = -c ID_WHITE -lw 1 -ls dash_dot_l +usermarker = -c ID_GREEN5 -lw 1 -ls long_dashed +trace = -c ID_GRAY5 -lw 1 -ls long_dashed +grid = -c ID_WHITE -lw 1 -ls short_dashed +rulerBackground = -c ID_GRAY3 +rulerForeground = -c ID_YELLOW5 +busTextColor = -c ID_ORANGE8 +legendForeground = -c ID_CYAN5 +valueForeground = -c ID_CYAN5 +curveForeground = -c ID_CYAN5 +groupNameColor = -c ID_GREEN5 +commentStringColor = -c ID_RED5 +region(Active)Background = -c ID_YELLOW1 +region(NBA)Background = -c ID_RED1 +region(Re-Active)Background = -c ID_YELLOW3 +region(Re-NBA)Background = -c ID_RED3 +region(VHDL-Delta)Background = -c ID_ORANGE3 +region(Dump-Off)Background = -c ID_GRAY4 +High_Light = -c ID_GRAY2 +Input_Signal = -c ID_RED5 +Output_Signal = -c ID_GREEN5 +InOut_Signal = -c ID_BLUE5 +Net_Signal = -c ID_YELLOW5 +Register_Signal = -c ID_PURPLE5 +Verilog_Signal = -c ID_CYAN5 +VHDL_Signal = -c ID_ORANGE5 +SystemC_Signal = -c ID_BLUE7 +Dump_Off_Color = -c ID_BLUE2 +Compress_Bar_Color = -c ID_YELLOW4 +Vector_Dense_Block_Color = -c ID_ORANGE8 +Scalar_Dense_Block_Color = -c ID_GREEN6 +Analog_Dense_Block_Color = -c ID_PURPLE2 +Composite_Dense_Block_Color = -c ID_ORANGE5 +RPTR_Power_Off_Layer = -c ID_CYAN3 -stipple dots +DB_Power_Off_Layer = -c ID_BLUE4 -stipple dots +SPA_Driver_Power_Off_Layer = -c ID_ORANGE4 -stipple dots +SPA_Receiver_Power_Off_Layer = -c ID_GREEN5 -stipple dots +SRSN_Power_Off_Layer = -c ID_GREEN4 -stipple dots +Isolation_Power_Off_Layer = -c ID_RED4 -stipple dots +PD_Power_Off_Layer = -c ID_GRAY4 -stipple dots +Isolation_Layer = -c ID_RED4 -stipple vLine +Retention_Level_Trigger_Layer = -c ID_ORANGE1 -stipple fill_solid +Retention_Edge_Trigger_Layer = -c ID_YELLOW6 -stipple fill_solid +Driving_Power_Off_Layer = -c ID_YELLOW2 -stipple x +Toggle_Layer = -c ID_YELLOW4 -stipple slash +analogRealStyle = pwl +analogVoltageStyle = pwl +analogCurrentStyle = pwl +analogOthersStyle = pwl +busSignalLayer = -c ID_ORANGE8 +busXLayer = -c ID_RED5 +busZLayer = -c ID_ORANGE6 +busMixedLayer = -c ID_GREEN5 +busNotComputedLayer = -c ID_GRAY1 +busNoValueLayer = -c ID_BLUE2 +signalGridLayer = -c ID_WHITE +analogGridLayer = -c ID_GRAY6 +analogRulerLayer = -c ID_GRAY6 +keywordLayer = -c ID_RED5 +loadedLayer = -c ID_BLUE5 +loadingLayer = -c ID_BLACK +qdsCurMarkerLayer = -c ID_BLUE5 +qdsBrkMarkerLayer = -c ID_GREEN5 +qdsTrgMarkerLayer = -c ID_RED5 +arrowDefaultColor = -c ID_ORANGE6 +startNodeArrowColor = -c ID_WHITE +endNodeArrowColor = -c ID_YELLOW5 +propertyEventMatchColor = -c ID_GREEN5 +propertyEventNoMatchColor = -c ID_RED5 +propertyVacuousSuccessMatchColor = -c ID_YELLOW2 +propertyStatusBoundaryColor = -c ID_WHITE +propertyBooleanSuccessColor = -c ID_CYAN5 +propertyBooleanFailureColor = -c ID_RED5 +propertyAssertSuccessColor = -c ID_GREEN5 +propertyAssertFailureColor = -c ID_RED5 +propertyForbidSuccessColor = -c ID_GREEN5 +transactionForegroundColor = -c ID_YELLOW8 +transactionBackgroundColor = -c ID_BLACK +transactionHighLightColor = -c ID_CYAN6 +transactionRelationshipColor = -c ID_PURPLE6 +transactionErrorTypeColor = -c ID_RED5 +coverageFullyCoveredColor = -c ID_GREEN5 +coverageNoCoverageColor = -c ID_RED5 +coveragePartialCoverageColor = -c ID_YELLOW5 +coverageReferenceLineColor = -c ID_GRAY4 +messageForegroundColor = -c ID_YELLOW4 +messageBackgroundColor = -c ID_PURPLE1 +messageHighLightColor = -c ID_CYAN6 +messageInformationColor = -c ID_RED5 +ComputedAnnotColor = -c ID_PURPLE5 +fsvSecurityDataColor = -c ID_PURPLE3 +qdsAutoBusGroup = TRUE +qdsTimeStampMode = FALSE +qdsVbfBusOrderAscending = FALSE +openDumpFilter = *.fsdb;*.vf;*.jf +DumpFileFilter = *.vcd +RestoreSignalFilter = *.rc +SaveSignalFilter = *.rc +AddAliasFilter = *.alias;*.adb +CompareSignalFilter = *.err +ConvertFFFilter = *.vcd;*.out;*.tr0;*.xp;*.raw;*.wfm +Scroll_Ratio = 100 +Zoom_Ratio = 10 +EventSequence_SyncCursorTime = TRUE +EventSequence_Sorting = FALSE +EventSequence_RemoveGrid = FALSE +EventSequence_IsGridMode = FALSE +SetDefaultRadix_global = FALSE +DefaultRadix = Hex +SigSearchSignalMatchCase = FALSE +SigSearchSignalScopeOption = FALSE +SigSearchSignalSamenetInterface = FALSE +SigSearchSignalFullScope = FALSE +SigSearchSignalWithRegExp = FALSE +SigSearchDynamically = FALSE +SigDisplayBySelectionOrder = FALSE +SigDisplayRowMajor = FALSE +SigDragSelFollowColumn = FALSE +SigDisplayHierarchyBox = TRUE +SigDisplaySubscopeBox = TRUE +SigDisplayEmptyScope = TRUE +SigDisplaySignalNavigationBox = FALSE +SigDisplayFormBus = TRUE +SigShowSubProgram = TRUE +SigSearchScopeDynamically = TRUE +SigCollapseSubtreeNodes = FALSE +activeFileApplyToAnnotation = FALSE +GrpSelMode = TRUE +dispGridCount = FALSE +hierarchyName = FALSE +partial_level_name = FALSE +partial_level_head = 1 +partial_level_tail = 1 +displayMessageLabelOnly = TRUE +autoInsertDumpoffs = TRUE +displayMessageCallStack = FALSE +displayCallStackWithFullSections = TRUE +displayCallStackWithLastSection = FALSE +limitMessageMaxWidth = FALSE +messageMaxWidth = 50 +displayTransBySpecificColor = FALSE +fittedTransHeight = FALSE +snap = TRUE +gravitySnap = FALSE +displayLeadingZero = FALSE +displayGlitchs = FALSE +allfileTimeRange = FALSE +fixDelta = FALSE +displayCursorMarker = FALSE +autoUpdate = FALSE +restoreFromActiveFile = TRUE +restoreToEnd = FALSE +dispCompErr = TRUE +showMsgDes = TRUE +anaAutoFit = FALSE +anaAutoPattn = FALSE +anaAuto100VertFit = FALSE +displayDeltaY = FALSE +centerCursor = FALSE +denseBlockDrawing = TRUE +relativeFreqPrecision = 3 +showMarkerAbsolute = FALSE +showMarkerAdjacent = FALSE +showMarkerRelative = FALSE +showMarkerFrequency = FALSE +stickCursorMarkerOnWaveform = TRUE +keepMarkerAtEndTimeOfTransaction = FALSE +doubleClickToExpandTransaction = TRUE +expandTransactionAssociatedSignals = TRUE +expandTransactionAttributeSignals = FALSE +WaveExtendLastTick = TRUE +InOutSignal = FALSE +NetRegisterSignal = FALSE +VerilogVHDLSignal = FALSE +LabelMarker = TRUE +ResolveSymbolicLink = TRUE +signal_rc_abspath = TRUE +signal_rc_no_natural_bus_range = FALSE +save_scope_with_macro = FALSE +scope_to_save_with_macro +TipInSignalWin = FALSE +DisplayPackedSiganlInBitwiseManner = FALSE +DisplaySignalTypeAheadOfSignalName = TRUE ICON +TipInCurveWin = FALSE +MouseGesturesInCurveWin = TRUE +DisplayLSBsFirst = FALSE +PaintSpecificColorPattern = TRUE +ModuleName = TRUE +form_all_memory_signal = FALSE +formBusSignalFromPartSelects = FALSE +read_value_change_on_demand_for_drawing = FALSE +load_scopes_on_demand = on 5 +TransitionMode = TRUE +DisplayRadix = FALSE +SchemaX = FALSE +Hilight = TRUE +UseBeforeValue = FALSE +DisplayFileNameAheadOfSignalName = FALSE +DisplayFileNumberAheadOfSignalName = FALSE +DisplayValueSpace = TRUE +FitAnaByBusSize = FALSE +displayTransactionAttributeName = FALSE +expandOverlappedTrans = FALSE +dispSamplePointForAttrSig = TRUE +dispClassName = TRUE +ReloadActiveFileOnly = FALSE +NormalizeEVCD = FALSE +OverwriteAliasWithRC = TRUE +overlay_added_analog_signals = FALSE +case_insensitive = FALSE +vhdlVariableCalculate = TRUE +showError = TRUE +signal_vertical_scroll_bar = TRUE +showPortNameForDroppedInstance = FALSE +truncateFilePathInTitleBar = TRUE +filterPropVacuousSuccess = FALSE +includeLocalSignals = FALSE +encloseSignalsByGroup = TRUE +resaveSignals = TRUE +adjustBusPrefix = adjustBus_ +adjustBusBits = 1 +adjustBusSettings = 69889 +maskPowerOff = TRUE +maskIsolation = TRUE +maskRetention = TRUE +maskDrivingPowerOff = TRUE +maskToggle = TRUE +autoBackupSignals = off 5 "\"/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/chip_top/verdiLog\"" "\"novas_autosave_sig\"" +signal_rc_attribute = 65535 +signal_rc_alias_attribute = 0 +ConvertAttr1 = -inc FALSE +ConvertAttr2 = -hier FALSE +ConvertAttr3 = -ucase FALSE +ConvertAttr4 = -lcase FALSE +ConvertAttr5 = -org FALSE +ConvertAttr6 = -mem 24 +ConvertAttr7 = -deli . +ConvertAttr8 = -hier_scope FALSE +ConvertAttr9 = -inst_array FALSE +ConvertAttr10 = -vhdlnaming FALSE +ConvertAttr11 = -orgScope FALSE +analogFmtPrecision = Automatic 2 +confirmOverwrite = TRUE +confirmExit = TRUE +confirmGetAll = TRUE +printTimeRange = TRUE 0.000000 0.000000 0.000000 +printPageRange = TRUE 1 1 +printOption = 0 +printBasic = 1 0 0 FALSE FALSE +printDest = -printer {} +printSignature = {%f %h %t} {} +curveWindow_Drag&Drop_Mode = TRUE +hspiceIncOpenMode = TRUE +pcSelectMode = TRUE +hierarchyDelimiter = / +RecentFile1 = "\"/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/chip_top/verdplus_000.fsdb\"" +open_file_time_range = FALSE +open_file_dir +open_rc_file_dir +value_window_aligment = Right +signal_window_alignment = Auto +ShowDeltaTime = TRUE +legend_window_font = -f COURIER12 -c ID_CYAN5 +value_window_font = -f COURIER12 -c ID_CYAN5 +curve_window_font = -f COURIER12 -c ID_CYAN5 +group_name_font = -f COURIER12 -c ID_GREEN5 +ruler_value_font = -f COURIER12 -c ID_CYAN5 +analog_ruler_value_font = -f COURIER12 -c ID_CYAN5 +comment_string_font = -f COURIER12 -c ID_RED5 +getsignal_form_font = -f COURIER12 +SigsCheckNum = on 1000 +filter_synthesized_net = off n +filterOutNet = on +filter_synthesized_instance = off +filterOutInstance = on +showGroupTree = TRUE +hierGroupDelim = / +MsgSeverityColor = {y \"Severity\"==\"1\" ID_RED5} {y \"Severity\"==\"2\" ID_RED6} {y \"Severity\"==\"3\" ID_RED7} {y \"Severity\"==\"4\" ID_RED8} {y \"Severity\"==\"5\" ID_ORANGE5} {y \"Severity\"==\"6\" ID_ORANGE6} {y \"Severity\"==\"7\" ID_ORANGE7} {y \"Severity\"==\"8\" \ +ID_GREEN7} {y \"Severity\"==\"9\" ID_GREEN6} {y \"Severity\"==\"10\" ID_GREEN5} +AutoApplySeverityColor = TRUE +AutoAdjustMsgWidthByLabel = off +verilogStrengthDispType = type1 +waveDblClkActiveTrace = on +autoConnectTBrowser = FALSE +connectTBrowserInContainer = TRUE +SEQShowComparisonIcon = TRUE +SEQAddDriverLoadInSameGroup = TRUE +autoSyncCursorMarker = FALSE +autoSyncHorizontalRange = FALSE +autoSyncVerticalScroll = FALSE +[cov_hier_name_column] +justify = TRUE +[coverageColors] +sou_uncov = TRUE +sou_pc = TRUE +sou_cov = TRUE +sou_exuncov = TRUE +sou_excov = TRUE +sou_unreach = TRUE +sou_unreachcon = TRUE +sou_fillColor_uncov = red +sou_fillColor_pc = yellow +sou_fillColor_cov = green3 +sou_fillColor_exuncov = grey +sou_fillColor_excov = #3C9371 +sou_fillColor_unreach = grey +sou_fillColor_unreachcon = orange +numberOfBins = 6 +rangeMin_0 = 0 +rangeMax_0 = 20 +fillColor_0 = #FF6464 +rangeMin_1 = 20 +rangeMax_1 = 40 +fillColor_1 = #FF9999 +rangeMin_2 = 40 +rangeMax_2 = 60 +fillColor_2 = #FF8040 +rangeMin_3 = 60 +rangeMax_3 = 80 +fillColor_3 = #FFFF99 +rangeMin_4 = 80 +rangeMax_4 = 100 +fillColor_4 = #99FF99 +rangeMin_5 = 100 +rangeMax_5 = 100 +fillColor_5 = #64FF64 +[coveragesetting] +assertTopoMode = FALSE +urgAppendOptions = +group_instance_new_format_name = TRUE +showvalue = FALSE +computeGroupsScoreByRatio = FALSE +computeGroupsScoreByInst = FALSE +showConditionId = FALSE +showfullhier = FALSE +nameLeftAlignment = TRUE +showAllInfoInTooltips = FALSE +copyItemHvpName = TRUE +ignoreGroupWeight = FALSE +absTestName = FALSE +HvpMergeTool = +ShowMergeMenuItem = FALSE +fsmScoreMode = transition +[eco] +IsFreezeSilicon = FALSE +cellQuantityManagement = FALSE +ManageMode = INSTANCE_NAME +SpareCellsPinsManagement = TRUE +LogCommitReport = FALSE +InputPinStatus = 1 +OutputPinStatus = 2 +NameRule = +RevisedComponentColor = ID_BLUE5 +SpareCellColor = ID_RED5 +UserName = ICer +CommentFormat = Novas ECO updated by ${UserName} ${Date} ${Time} +PrefixN = eco_n +PrefixP = eco_p +PrefixI = eco_i +DefaultTieUpNet = 1'b1 +DefaultTieDownNet = 1'b0 +MultipleInstantiations = TRUE +KeepClockPinConnection = FALSE +KeepAsyncResetPinConnection = FALSE +ScriptFileModeType = 1 +MagmaScriptPower = VDD +MagmaScriptGround = GND +ShowModeMsg = TRUE +AstroScriptPower = VDD +AstroScriptGround = VSS +ClearFloatingPorts = FALSE +[eco_connection] +Port/NetIsUnique = TRUE +SerialNet = 0 +SerialPort = 0 +SerialInst = 0 +[finsim] +TPLanguage = Verilog +TPName = Super-FinSim +TPPath = TOP.sim +TPOption = +AddImportArgument = FALSE +LineBreakWithScope = FALSE +StopAfterCompileOption = -i +[hvpsetting] +importExcelXMLOptions = +use_test_loca_as_source = FALSE +autoTurnOffHideMeetGoalInit = FALSE +autoTurnOffHideMeetGoal = TRUE +autoTurnOffModifierInit = FALSE +autoTurnOffModifier = TRUE +enableNumbering = TRUE +autoSaveCheck = TRUE +autoSaveTime = 5 +ShowMissingScore = TRUE +enableFeatureId = FALSE +enable_HVP_FEAT_ID = FALSE +enableMeasureConcealment = FALSE +HvpCloneHierShowMsgAgain = 1 +HvpCloneHierType = tree +HvpCloneHierMetrics = Line,Cond,FSM,Toggle,Branch,Assert +autoRecalPlanAfterLoadingCovDBUserDataPlan = false +warnMeAutoRecalPlanAfterLoadingCovDBUserDataPlan = true +autoRecalExclWithPlan = false +warnMeAutoRecalExclWithPlan = true +autoRecalPlanWithExcl = false +warnMeAutoRecalPlanWithExcl = true +warnPopupWarnWhenMultiFilters = true +warnPopupWarnIfHvpReadOnly = true +unmappedObjsReportLevel = def_var_inst +unmappedObjsReportInst = true +unmappedObjsNumOfObjs = High +[ikos] +TPLanguage = VHDL +TPName = Voyager +TPPath = vsh +TPOption = -X +AddImportArgument = FALSE +LineBreakWithScope = FALSE +StopAfterCompileOption = -i +[imp] +options = NULL +libPath = NULL +libDir = NULL +[nCompare] +ErrorViewport = 80 180 800 550 +EditorViewport = 409 287 676 475 +EditorHeightWidth = 802 380 +WaveCommand = "novas" +WaveArgs = "-nWave" +[nCompare.Wnd0] +ViewByHier = FALSE +[nMemory] +dispMode = ADDR_HINT +addrColWidth = 120 +valueColWidth = 100 +showCellBitRangeWithAddr = TRUE +wordsShownInOneRow = 8 +syncCursorTime = FALSE +fixCellColumnWidth = FALSE +font = Courier 12 +[planColors] +plan_fillColor_inactive = lightGray +plan_fillColor_warning = orange +plan_fillColor_error = red +plan_fillColor_invalid = #F0DCDB +plan_fillColor_subplan = lightGray +[schematics] +schBackgroundColor = black lineSolid +schBackgroundColor_qt = #000000 qt_solidLine 1 +schBodyColor = orange6 lineSolid +schBodyColor_qt = #ffb973 qt_solidLine 1 +schAsmBodyColor = blue7 lineSolid +schAsmBodyColor_qt = #a5a5ff qt_solidLine 1 +schPortColor = orange6 lineSolid +schPortColor_qt = #ffb973 qt_solidLine 1 +schCellNameColor = Gray6 lineSolid +schCellNameColor_qt = #e0e0e0 qt_solidLine 1 +schCLKNetColor = red6 lineSolid +schCLKNetColor_qt = #ff7373 qt_solidLine 1 +schPWRNetColor = red4 lineSolid +schPWRNetColor_qt = #ff0101 qt_solidLine 1 +schGNDNetColor = cyan4 lineSolid +schGNDNetColor_qt = #01ffff qt_solidLine 1 +schSIGNetColor = green8 lineSolid +schSIGNetColor_qt = #cdffcd qt_solidLine 1 +schTraceColor = yellow4 lineSolid +schTraceColor_qt = #ffff01 qt_solidLine 2 +schBackAnnotateColor = white lineSolid +schBackAnnotateColor_qt = #ffffff qt_solidLine 1 +schValue0 = yellow4 lineSolid +schValue0_qt = #ffff01 qt_solidLine 1 +schValue1 = green3 lineSolid +schValue1_qt = #008000 qt_solidLine 1 +schValueX = red4 lineSolid +schValueX_qt = #ff0101 qt_solidLine 1 +schValueZ = purple7 lineSolid +schValueZ_qt = #ffcdff qt_solidLine 1 +dimColor = cyan2 lineSolid +dimColor_qt = #008080 qt_solidLine 1 +schPreSelColor = green4 lineDash +schPreSelColor_qt = #01ff01 qt_dashLine 2 +schSIGBusNetColor = green8 lineSolid +schSIGBusNetColor_qt = #cdffcd qt_solidLine +schGNDBusNetColor = cyan4 lineSolid +schGNDBusNetColor_qt = #01ffff qt_solidLine +schPWRBusNetColor = red4 lineSolid +schPWRBusNetColor_qt = #ff0101 qt_solidLine +schCLKBusNetColor = red6 lineSolid +schCLKBusNetColor_qt = #ff7373 qt_solidLine +schEdgeSensitiveColor = orange6 lineSolid +schEdgeSensitiveColor_qt = #ffb973 qt_solidLine +schAnnotColor = cyan4 lineSolid +schAnnotColor_qt = #01ffff qt_solidLine +schInstNameColor = orange6 lineSolid +schInstNameColor_qt = #ffb973 qt_solidLine +schPortNameColor = cyan4 lineSolid +schPortNameColor_qt = #01ffff qt_solidLine +schAsmLatchColor = cyan4 lineSolid +schAsmLatchColor_qt = #01ffff qt_solidLine +schAsmRegColor = cyan4 lineSolid +schAsmRegColor_qt = #01ffff qt_solidLine +schAsmTriColor = cyan4 lineSolid +schAsmTriColor_qt = #01ffff qt_solidLine +pre_select = True +ShowPassThroughNet = False +ComputedAnnotColor = ID_PURPLE5 +viewport = 0 27 1714 574 +[schematics_print] +Signature = FALSE +DesignName = PCU +DesignerName = bai +SignatureLocation = LowerRight +MultiPage = TRUE +AutoSliver = FALSE +[sourceColors] +BackgroundActive = gray88 +BackgroundInactive = lightgray +InactiveCode = dimgray +Selection = darkblue +Standard = black +Keyword = blue +Comment = gray25 +Number = black +String = black +Identifier = darkred +Inline = green +colorIdentifier = green +Value = darkgreen +MacroBackground = white +Missing = #400040 +[specColors] +top_plan_linked = #ADFFA6 +top_plan_ignore = #D3D3D3 +top_plan_todo = #EECBAD +sub_plan_ignore = #919191 +sub_plan_todo = #EFAFAF +sub_plan_linked = darkorange +[spec_link_setting] +use_spline = true +goto_section = false +exclude_ignore = true +truncate_abstract = false +abstract_length = 999 +compare_strategy = 2 +auto_apply_margin = FALSE +margin_top = 0.80 +margin_bottom = 0.80 +margin_left = 0.50 +margin_right = 0.50 +margin_unit = inches +[spiceDebug] +ThroughNet = ID_YELLOW5 +InstrumentSig = ID_GREEN5 +InterfaceElement = ID_GREEN5 +Run-timeInterfaceElement = ID_BLUE5 +HighlightThroughNet = TRUE +HighlightInterfaceElement = TRUE +HighlightRuntimeInterfaceElement = TRUE +HighlightSameNet = TRUE +[surefire] +TPLanguage = Verilog +TPName = SureFire +TPPath = verilog +TPOption = +AddImportArgument = TRUE +LineBreakWithScope = TRUE +StopAfterCompileOption = -tcl +[turboSchema_Printer_Options] +Orientation = Landscape +[turbo_library] +bdb_load_scope = +[vdCovFilteringSearchesStrings] +keepLastUsedFiltersMaxNum = 10 +[verisity] +TPLanguage = Verilog +TPName = "Verisity SpeXsim" +TPPath = vlg +TPOption = +AddImportArgument = FALSE +LineBreakWithScope = TRUE +StopAfterCompileOption = -s +[wave.0] +viewPort = 0 27 2560 668 308 65 +[wave.1] +viewPort = 127 219 960 332 100 65 +[wave.2] +viewPort = 38 314 686 205 100 65 +[wave.3] +viewPort = 63 63 700 400 65 41 +[wave.4] +viewPort = 84 84 700 400 65 41 +[wave.5] +viewPort = 92 105 700 400 65 41 +[wave.6] +viewPort = 0 0 700 400 65 41 +[wave.7] +viewPort = 21 21 700 400 65 41 diff --git a/tb/chip_top/novas_dump.log b/tb/chip_top/novas_dump.log new file mode 100644 index 0000000..a79fe7b --- /dev/null +++ b/tb/chip_top/novas_dump.log @@ -0,0 +1,327 @@ +####################################################################################### +# log primitive debug message of FSDB dumping # +# This is for R&D to analyze when there are issues happening when FSDB dump # +####################################################################################### +ANF: vcsd_get_serial_mode_status('./simv: undefined symbol: vcsd_get_serial_mode_status') +ANF: vcsd_enable_sva_success_callback('./simv: undefined symbol: vcsd_enable_sva_success_callback') +ANF: vcsd_disable_sva_success_callback('./simv: undefined symbol: vcsd_disable_sva_success_callback') +ANF: vcsd_get_power_scope_name('./simv: undefined symbol: vcsd_get_power_scope_name') +ANF: vcsd_begin_no_value_var_info('./simv: undefined symbol: vcsd_begin_no_value_var_info') +ANF: vcsd_end_no_value_var_info('./simv: undefined symbol: vcsd_end_no_value_var_info') +ANF: vcsd_remove_xprop_merge_mode_callback('./simv: undefined symbol: vcsd_remove_xprop_merge_mode_callback') +ANF: vhpi_get_cb_info('./simv: undefined symbol: vhpi_get_cb_info') +ANF: vhpi_free_handle('./simv: undefined symbol: vhpi_free_handle') +ANF: vhpi_fetch_vcsd_handle('./simv: undefined symbol: vhpi_fetch_vcsd_handle') +ANF: vhpi_fetch_vpi_handle('./simv: undefined symbol: vhpi_fetch_vpi_handle') +ANF: vhpi_has_verilog_parent('./simv: undefined symbol: vhpi_has_verilog_parent') +ANF: vhpi_is_verilog_scope('./simv: undefined symbol: vhpi_is_verilog_scope') +ANF: scsd_xprop_is_enabled('./simv: undefined symbol: scsd_xprop_is_enabled') +ANF: scsd_xprop_sig_is_promoted('./simv: undefined symbol: scsd_xprop_sig_is_promoted') +ANF: scsd_xprop_int_xvalue('./simv: undefined symbol: scsd_xprop_int_xvalue') +ANF: scsd_xprop_bool_xvalue('./simv: undefined symbol: scsd_xprop_bool_xvalue') +ANF: scsd_xprop_enum_xvalue('./simv: undefined symbol: scsd_xprop_enum_xvalue') +ANF: scsd_xprop_register_merge_mode_cb('./simv: undefined symbol: scsd_xprop_register_merge_mode_cb') +ANF: scsd_xprop_delete_merge_mode_cb('./simv: undefined symbol: scsd_xprop_delete_merge_mode_cb') +ANF: scsd_xprop_get_merge_mode('./simv: undefined symbol: scsd_xprop_get_merge_mode') +ANF: scsd_thread_get_info('./simv: undefined symbol: scsd_thread_get_info') +ANF: scsd_thread_vc_init('./simv: undefined symbol: scsd_thread_vc_init') +ANF: scsd_master_set_delta_sync_cbk('./simv: undefined symbol: scsd_master_set_delta_sync_cbk') +ANF: scsd_fgp_get_fsdb_cores('./simv: undefined symbol: scsd_fgp_get_fsdb_cores') +ANF: msvEnableDumpingMode('./simv: undefined symbol: msvEnableDumpingMode') +ANF: msvGetVersion('./simv: undefined symbol: msvGetVersion') +ANF: msvGetInstProp('./simv: undefined symbol: msvGetInstProp') +ANF: msvIsSpiceEngineReady('./simv: undefined symbol: msvIsSpiceEngineReady') +ANF: msvSetAddProbeCallback('./simv: undefined symbol: msvSetAddProbeCallback') +ANF: msvGetInstHandle('./simv: undefined symbol: msvGetInstHandle') +ANF: msvGetProbeByInst('./simv: undefined symbol: msvGetProbeByInst') +ANF: msvGetSigHandle('./simv: undefined symbol: msvGetSigHandle') +ANF: msvGetProbeBySig('./simv: undefined symbol: msvGetProbeBySig') +ANF: msvGetProbeInfo('./simv: undefined symbol: msvGetProbeInfo') +ANF: msvRelease('./simv: undefined symbol: msvRelease') +ANF: msvSetVcCallbackFunc('./simv: undefined symbol: msvSetVcCallbackFunc') +ANF: msvCheckVcCallback('./simv: undefined symbol: msvCheckVcCallback') +ANF: msvAddVcCallback('./simv: undefined symbol: msvAddVcCallback') +ANF: msvRemoveVcCallback('./simv: undefined symbol: msvRemoveVcCallback') +ANF: msvGetLatestValue('./simv: undefined symbol: msvGetLatestValue') +ANF: msvSetEndofSimCallback('./simv: undefined symbol: msvSetEndofSimCallback') +ANF: msvIgnoredProbe('./simv: undefined symbol: msvIgnoredProbe') +ANF: msvGetThruNetInfo('./simv: undefined symbol: msvGetThruNetInfo') +ANF: msvFreeThruNetInfo('./simv: undefined symbol: msvFreeThruNetInfo') +ANF: PI_ace_get_output_time_unit('./simv: undefined symbol: PI_ace_get_output_time_unit') +ANF: PI_ace_sim_sync('./simv: undefined symbol: PI_ace_sim_sync') +ANF: msvGetRereadInitFile('./simv: undefined symbol: msvGetRereadInitFile') +ANF: msvSetBeforeRereadCallback('./simv: undefined symbol: msvSetBeforeRereadCallback') +ANF: msvSetAfterRereadCallback('./simv: undefined symbol: msvSetAfterRereadCallback') +ANF: msvSetForceCallback('./simv: undefined symbol: msvSetForceCallback') +ANF: msvSetReleaseCallback('./simv: undefined symbol: msvSetReleaseCallback') +ANF: msvGetForceStatus('./simv: undefined symbol: msvGetForceStatus') +ANF: vhdi_dt_get_type('./simv: undefined symbol: vhdi_dt_get_type') +ANF: vhdi_dt_get_key('./simv: undefined symbol: vhdi_dt_get_key') +ANF: vhdi_dt_get_vhdl_enum_info('./simv: undefined symbol: vhdi_dt_get_vhdl_enum_info') +ANF: vhdi_dt_get_vhdl_physical_info('./simv: undefined symbol: vhdi_dt_get_vhdl_physical_info') +ANF: vhdi_dt_get_vhdl_array_info('./simv: undefined symbol: vhdi_dt_get_vhdl_array_info') +ANF: vhdi_dt_get_vhdl_record_info('./simv: undefined symbol: vhdi_dt_get_vhdl_record_info') +ANF: vhdi_def_traverse_module('./simv: undefined symbol: vhdi_def_traverse_module') +ANF: vhdi_def_traverse_scope('./simv: undefined symbol: vhdi_def_traverse_scope') +ANF: vhdi_def_traverse_variable('./simv: undefined symbol: vhdi_def_traverse_variable') +ANF: vhdi_def_get_module_id_by_vhpi('./simv: undefined symbol: vhdi_def_get_module_id_by_vhpi') +ANF: vhdi_def_get_handle_by_module_id('./simv: undefined symbol: vhdi_def_get_handle_by_module_id') +ANF: vhdi_def_get_variable_info_by_vhpi('./simv: undefined symbol: vhdi_def_get_variable_info_by_vhpi') +ANF: vhdi_def_free('./simv: undefined symbol: vhdi_def_free') +ANF: vhdi_ist_traverse_scope('./simv: undefined symbol: vhdi_ist_traverse_scope') +ANF: vhdi_ist_traverse_variable('./simv: undefined symbol: vhdi_ist_traverse_variable') +ANF: vhdi_ist_convert_by_vhpi('./simv: undefined symbol: vhdi_ist_convert_by_vhpi') +ANF: vhdi_ist_clone('./simv: undefined symbol: vhdi_ist_clone') +ANF: vhdi_ist_free('./simv: undefined symbol: vhdi_ist_free') +ANF: vhdi_ist_hash_key('./simv: undefined symbol: vhdi_ist_hash_key') +ANF: vhdi_ist_compare('./simv: undefined symbol: vhdi_ist_compare') +ANF: vhdi_ist_get_value_addr('./simv: undefined symbol: vhdi_ist_get_value_addr') +ANF: vhdi_set_scsd_callback('./simv: undefined symbol: vhdi_set_scsd_callback') +ANF: vhdi_cbk_set_force_callback('./simv: undefined symbol: vhdi_cbk_set_force_callback') +ANF: vhdi_trigger_init_force('./simv: undefined symbol: vhdi_trigger_init_force') +ANF: vhdi_ist_check_scsd_callback('./simv: undefined symbol: vhdi_ist_check_scsd_callback') +ANF: vhdi_ist_add_scsd_callback('./simv: undefined symbol: vhdi_ist_add_scsd_callback') +ANF: vhdi_ist_remove_scsd_callback('./simv: undefined symbol: vhdi_ist_remove_scsd_callback') +ANF: vhdi_ist_get_scsd_user_data('./simv: undefined symbol: vhdi_ist_get_scsd_user_data') +ANF: vhdi_add_time_change_callback('./simv: undefined symbol: vhdi_add_time_change_callback') +ANF: vhdi_get_real_value_by_value_addr('./simv: undefined symbol: vhdi_get_real_value_by_value_addr') +ANF: vhdi_get_64_value_by_value_addr('./simv: undefined symbol: vhdi_get_64_value_by_value_addr') +ANF: vhdi_xprop_inst_is_promoted('./simv: undefined symbol: vhdi_xprop_inst_is_promoted') +ANF: vdi_ist_convert_by_vhdi('./simv: undefined symbol: vdi_ist_convert_by_vhdi') +ANF: vhdi_ist_get_module_id('./simv: undefined symbol: vhdi_ist_get_module_id') +ANF: vhdi_refine_foreign_scope_type('./simv: undefined symbol: vhdi_refine_foreign_scope_type') +ANF: vhdi_flush_callback('./simv: undefined symbol: vhdi_flush_callback') +ANF: vhdi_set_orig_name('./simv: undefined symbol: vhdi_set_orig_name') +ANF: vhdi_set_dump_pt('./simv: undefined symbol: vhdi_set_dump_pt') +ANF: vhdi_get_fsdb_option('./simv: undefined symbol: vhdi_get_fsdb_option') +ANF: vhdi_fgp_get_mode('./simv: undefined symbol: vhdi_fgp_get_mode') +ANF: vhdi_node_register_composite_var('./simv: undefined symbol: vhdi_node_register_composite_var') +ANF: vhdi_node_analysis('./simv: undefined symbol: vhdi_node_analysis') +ANF: vhdi_node_id('./simv: undefined symbol: vhdi_node_id') +ANF: vhdi_node_ist_check_scsd_callback('./simv: undefined symbol: vhdi_node_ist_check_scsd_callback') +ANF: vhdi_node_ist_add_scsd_callback('./simv: undefined symbol: vhdi_node_ist_add_scsd_callback') +ANF: vhdi_node_ist_get_value_addr('./simv: undefined symbol: vhdi_node_ist_get_value_addr') +VCS compile option: + option[0]: ./simv + option[1]: -l + option[2]: sim.log + option[3]: /home/synopsys/vcs/O-2018.09-SP2/linux64/bin/vcs1 + option[4]: -Mcc=gcc + option[5]: -Mcplusplus=g++ + option[6]: -Masflags= + option[7]: -Mcfl= -pipe -fPIC -O -I/home/synopsys/vcs/O-2018.09-SP2/include + option[8]: -Mxcflags= -pipe -fPIC -I/home/synopsys/vcs/O-2018.09-SP2/include + option[9]: -Mldflags= -rdynamic + option[10]: -Mout=simv + option[11]: -Mamsrun= + option[12]: -Mvcsaceobjs= + option[13]: -Mobjects= /home/synopsys/vcs/O-2018.09-SP2/linux64/lib/libvirsim.so /home/synopsys/vcs/O-2018.09-SP2/linux64/lib/liberrorinf.so /home/synopsys/vcs/O-2018.09-SP2/linux64/lib/libsnpsmalloc.so /home/synopsys/vcs/O-2018.09-SP2/linux64/lib/libvfs.so /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/pli.a + option[14]: -Mexternalobj= + option[15]: -Msaverestoreobj=/home/synopsys/vcs/O-2018.09-SP2/linux64/lib/vcs_save_restore_new.o + option[16]: -Mcrt0= + option[17]: -Mcrtn= + option[18]: -Mcsrc= + option[19]: -Msyslibs=/home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/pli.a -ldl -lm + option[20]: -l + option[21]: compile.log + option[22]: -full64 + option[23]: +lint=TFIPC-L + option[24]: +v2k + option[25]: -debug_access+all + option[26]: +vpi + option[27]: +vcsd1 + option[28]: +itf+/home/synopsys/vcs/O-2018.09-SP2/linux64/lib/vcsdp_lite.tab + option[29]: +define+DUMP_FSDB + option[30]: -lca + option[31]: -q + option[32]: -timescale=1ns/1ps + option[33]: +nospecify + option[34]: -P + option[35]: /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab + option[36]: -picarchive + option[37]: -P + option[38]: /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab + option[39]: -fsdb + option[40]: -sverilog + option[41]: -gen_obj + option[42]: -f + option[43]: files.f + option[44]: -load + option[45]: /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/libnovas.so:FSDBDumpCmd + option[46]: timescale=1ns/1ps +Chronologic Simulation VCS Release O-2018.09-SP2_Full64 +Linux 3.10.0-1160.53.1.el7.x86_64 #1 SMP Fri Jan 14 13:59:45 UTC 2022 x86_64 +CPU cores: 8 +Limit information: +====================================== +cputime unlimited +filesize unlimited +datasize unlimited +stacksize 8192 kbytes +coredumpsize 0 kbytes +memoryuse unlimited +vmemoryuse unlimited +descriptors 4096 +memorylocked 64 kbytes +maxproc 4096 +====================================== +(Special)Runtime environment variables: + +Runtime environment variables: +DESKTOP_SESSION=gnome-classic +XDG_SESSION_TYPE=x11 +XAUTHORITY=/run/gdm/auth-for-ICer-FQtMgs/database +GDMSESSION=gnome-classic +XMODIFIERS=@im=ibus +SHELL=/bin/bash +GDM_LANG=zh_CN.UTF-8 +VTE_VERSION=5204 +_=/usr/local/bin/make +HISTCONTROL=ignoredups +SNPSLMD_LICENSE_FILE=27000@IC_EDA +USERNAME=ICer +DVE_HOME=/home/synopsys/vcs/O-2018.09-SP2 +XDG_DATA_DIRS=/home/ICer/.local/share/flatpak/exports/share/:/var/lib/flatpak/exports/share/:/usr/local/share/:/usr/share/ +QT_PLUGIN_PATH=/usr/lib64/kde4/plugins:/usr/lib/kde4/plugins +LESSOPEN=||/usr/bin/lesspipe.sh %s +QUESTASIM_HOME=/home/mentor/questasim +PATH=/usr/lib/qt-3.3/bin:/usr/local/bin:/usr/local/sbin:/usr/bin:/usr/sbin:/bin:/sbin:/home/synopsys/pts/O-2018.06-SP1/bin:/home/synopsys/syn/O-2018.06-SP1/bin:/home/synopsys/lc/O-2018.06-SP1/bin:/home/synopsys/SpyGlass-L2016.06/SPYGLASS_HOME//bin:/home/synopsys/vcs/O-2018.09-SP2/gui/dve/bin:/home/synopsys/vcs/O-2018.09-SP2/bin:/home/synopsys/verdi/Verdi_O-2018.09-SP2/bin:/home/synopsys/verdi/Verdi_O-2018.09-SP2/platform/LINUX/bin:/home/synopsys/scl/2018.06/linux64/bin::/home/mentor/questasim/linux_x86_64:/home/Riscv_Tools/bin:/home/Riscv_Tools/riscv-gnu-toolchain/qemu-6.0.0/build/riscv32-linux-user +PT_HOME=/home/synopsys/pts/O-2018.06-SP1 +QT_GRAPHICSSYSTEM_CHECKED=1 +SESSION_MANAGER=local/unix:@/tmp/.ICE-unix/10289,unix/unix:/tmp/.ICE-unix/10289 +XDG_RUNTIME_DIR=/run/user/1000 +XDG_MENU_PREFIX=gnome- +LC_NUMERIC=zh_CN.UTF-8 +LS_COLORS=rs=0:di=38;5;27:ln=38;5;51:mh=44;38;5;15:pi=40;38;5;11:so=38;5;13:do=38;5;5:bd=48;5;232;38;5;11:cd=48;5;232;38;5;3:or=48;5;232;38;5;9:mi=05;48;5;232;38;5;15:su=48;5;196;38;5;15:sg=48;5;11;38;5;16:ca=48;5;196;38;5;226:tw=48;5;10;38;5;16:ow=48;5;10;38;5;21:st=48;5;21;38;5;15:ex=38;5;34:*.tar=38;5;9:*.tgz=38;5;9:*.arc=38;5;9:*.arj=38;5;9:*.taz=38;5;9:*.lha=38;5;9:*.lz4=38;5;9:*.lzh=38;5;9:*.lzma=38;5;9:*.tlz=38;5;9:*.txz=38;5;9:*.tzo=38;5;9:*.t7z=38;5;9:*.zip=38;5;9:*.z=38;5;9:*.Z=38;5;9:*.dz=38;5;9:*.gz=38;5;9:*.lrz=38;5;9:*.lz=38;5;9:*.lzo=38;5;9:*.xz=38;5;9:*.bz2=38;5;9:*.bz=38;5;9:*.tbz=38;5;9:*.tbz2=38;5;9:*.tz=38;5;9:*.deb=38;5;9:*.rpm=38;5;9:*.jar=38;5;9:*.war=38;5;9:*.ear=38;5;9:*.sar=38;5;9:*.rar=38;5;9:*.alz=38;5;9:*.ace=38;5;9:*.zoo=38;5;9:*.cpio=38;5;9:*.7z=38;5;9:*.rz=38;5;9:*.cab=38;5;9:*.jpg=38;5;13:*.jpeg=38;5;13:*.gif=38;5;13:*.bmp=38;5;13:*.pbm=38;5;13:*.pgm=38;5;13:*.ppm=38;5;13:*.tga=38;5;13:*.xbm=38;5;13:*.xpm=38;5;13:*.tif=38;5;13:*.tiff=38;5;13:*.png=38;5;13:*.svg=38;5;13:*.svgz=38;5;13:*.mng=38;5;13:*.pcx=38;5;13:*.mov=38;5;13:*.mpg=38;5;13:*.mpeg=38;5;13:*.m2v=38;5;13:*.mkv=38;5;13:*.webm=38;5;13:*.ogm=38;5;13:*.mp4=38;5;13:*.m4v=38;5;13:*.mp4v=38;5;13:*.vob=38;5;13:*.qt=38;5;13:*.nuv=38;5;13:*.wmv=38;5;13:*.asf=38;5;13:*.rm=38;5;13:*.rmvb=38;5;13:*.flc=38;5;13:*.avi=38;5;13:*.fli=38;5;13:*.flv=38;5;13:*.gl=38;5;13:*.dl=38;5;13:*.xcf=38;5;13:*.xwd=38;5;13:*.yuv=38;5;13:*.cgm=38;5;13:*.emf=38;5;13:*.axv=38;5;13:*.anx=38;5;13:*.ogv=38;5;13:*.ogx=38;5;13:*.aac=38;5;45:*.au=38;5;45:*.flac=38;5;45:*.mid=38;5;45:*.midi=38;5;45:*.mka=38;5;45:*.mp3=38;5;45:*.mpc=38;5;45:*.ogg=38;5;45:*.ra=38;5;45:*.wav=38;5;45:*.axa=38;5;45:*.oga=38;5;45:*.spx=38;5;45:*.xspf=38;5;45: +XDG_SESSION_DESKTOP=gnome-classic +SSH_AUTH_SOCK=/run/user/1000/keyring/ssh +KDEDIRS=/usr +DISPLAY=:0 +IMSETTINGS_INTEGRATE_DESKTOP=yes +HOME=/home/ICer +VCS_HOME=/home/synopsys/vcs/O-2018.09-SP2 +PWD=/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/chip_top +XDG_SEAT=seat0 +SSH_AGENT_PID=10423 +VERDI_HOME=/home/synopsys/verdi/Verdi_O-2018.09-SP2 +MGLS_LICENSE_FILE=/home/mentor/questasim/mentor.dat +DBUS_SESSION_BUS_ADDRESS=unix:abstract=/tmp/dbus-DIYqQioq7q,guid=a50f166bc97a0937429a75936639b5b6 +LD_LIBRARY_PATH=:/home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/lib/LINUX64:/home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/IUS/LINUX64/boot +RISCV=/home/Riscv_Tools +LOGNAME=ICer +GNOME_DESKTOP_SESSION_ID=this-is-deprecated +HOSTNAME=IC_EDA +XDG_VTNR=1 +COLORTERM=truecolor +QT_IM_MODULE=ibus +VCS_ARCH_OVERRIDE=linux +SHLVL=2 +GNOME_SHELL_SESSION_MODE=classic +XDG_SESSION_ID=1 +USER=ICer +LC_MONETARY=zh_CN.UTF-8 +QTLIB=/usr/lib/qt-3.3/lib +XDG_CURRENT_DESKTOP=GNOME-Classic:GNOME +IMSETTINGS_MODULE=none +MAKEFLAGS= +MFLAGS= +MAIL=/var/spool/mail/ICer +SPYGLASS_HOME=/home/synopsys/SpyGlass-L2016.06/SPYGLASS_HOME/ +MAKE_TERMOUT=/dev/pts/2 +DC_HOME=/home/synopsys/syn/O-2018.06-SP1 +LC_PAPER=zh_CN.UTF-8 +LC_HOME=/home/synopsys/lc/O-2018.06-SP1 +PS1=[\u@\h `pwd`]\$ +LC_MEASUREMENT=zh_CN.UTF-8 +DBUS_STARTER_BUS_TYPE=session +SCL_HOME=/home/synopsys/scl/2018.06 +GNOME_TERMINAL_SCREEN=/org/gnome/Terminal/screen/ebae3589_b60a_4793_b5e9_6b90fc529827 +GNOME_TERMINAL_SERVICE=:1.108 +HISTSIZE=1000 +QEMU_HOME=/home/Riscv_Tools/riscv-gnu-toolchain/qemu-6.0.0 +WINDOWPATH=1 +LC_TIME=zh_CN.UTF-8 +QTINC=/usr/lib/qt-3.3/include +QTDIR=/usr/lib/qt-3.3 +MAKE_TERMERR=/dev/pts/2 +LANG=zh_CN.UTF-8 +TERM=xterm-256color +DBUS_STARTER_ADDRESS=unix:abstract=/tmp/dbus-DIYqQioq7q,guid=a50f166bc97a0937429a75936639b5b6 +MAKELEVEL=1 +VCS_HEAP_EXEC=true +VCS_PATHMAP_PRELOAD_DONE=1 +VCS_STACK_EXEC=true +VCS_EXEC_DONE=1 +LC_ALL=C +DVE=/home/synopsys/vcs/O-2018.09-SP2/gui/dve +SPECMAN_OUTPUT_TO_TTY=1 +Runtime command line arguments: +argv[0]=./simv +argv[1]=-l +argv[2]=sim.log +261 profile - 100 + CPU/Mem usage: 0.040 sys, 0.080 user, 251.81M mem +262 Mon Jun 3 10:51:22 2024 +263 pliAppInit +264 FSDB_GATE is set. +265 FSDB_RTL is set. +266 Enable Parallel Dumping. +267 pliAppMiscSet: New Sim Round +268 pliEntryInit +269 LIBSSCORE=found /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/lib/LINUXAMD64/libsscore_vcs201809.so through $NOVAS_HOME setting. +270 FSDB Dumper for VCS, Release Verdi_O-2018.09-SP2, Linux x86_64/64bit, 02/21/2019 +271 (C) 1996 - 2019 by Synopsys, Inc. +272 FSDB_VCS_ENABLE_FAST_VC is enable +273 sps_call_fsdbAutoSwitchDumpfile_main_vd at 0 : ../../sim/chip_top/TB.sv(214) +274 sps_call_fsdbAutoSwitchDumpfile at 0 : ../../sim/chip_top/TB.sv(214) +275 argv[0]: (500) +276 argv[1]: (./verdplus.fsdb) +277 argv[2]: (1000000) +278 *Verdi* FSDB WARNING: The FSDB file already exists. Overwriting the FSDB file may crash the programs that are using this file. +279 *Verdi* FSDB: The switch FSDB file size might not match the input size (500MB) because of performance concerns. +280 *Verdi* FSDB: To have the FSDB file size match the input size (500MB), set the FSDB_ENV_PRECISE_AUTOSWITCH environment, though the dumping performance might decrease. +281 *Verdi* : Enable automatic switching of the FSDB file. +282 *Verdi* : (Filename='./verdplus', Limit Size=500MB, File Amount=1000000). +283 *Verdi* : Create FSDB file './verdplus_000.fsdb' +284 compile option from '/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/chip_top/simv.daidir/vcs_rebuild'. +285 "vcs '-full64' '-sverilog' '+lint=TFIPC-L' '+v2k' '-debug_access+all' '+define+DUMP_FSDB' '-lca' '-q' '-timescale=1ns/1ps' '+nospecify' '-P' '/home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab' '/home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/pli.a' '-l' 'compile.log' '-f' 'files.f' 2>&1" +286 *Verdi* : Create the file './verdplus.log' to log the time range of each FSDB file. +287 *Verdi* : Create virtual FSDB file './verdplus.vf' to log each FSDB file. +288 sps_call_fsdbDumpvars_vd_main at 0 : ../../sim/chip_top/TB.sv(215) +289 [spi_vcs_vd_ppi_create_root]: no upf option +290 FSDB dumper cannot dump UPF related power signal ($power_tree): no ppiPowerNetwork. +291 *Verdi* : Begin traversing the scopes, layer (0). +292 *Verdi* : End of traversing. +293 pliAppHDL_DumpVarComplete traverse var: profile - + CPU/Mem usage: 0.050 sys, 0.120 user, 365.64M mem + incr: 0.010 sys, 0.030 user, 26.30M mem + accu: 0.010 sys, 0.030 user, 26.30M mem + accu incr: 0.010 sys, 0.030 user, 26.30M mem + + Count usage: 12893 var, 8412 idcode, 3467 callback + incr: 12893 var, 8412 idcode, 3467 callback + accu: 12893 var, 8412 idcode, 3467 callback + accu incr: 12893 var, 8412 idcode, 3467 callback +294 Mon Jun 3 10:51:22 2024 +295 pliAppHDL_DumpVarComplete: profile - + CPU/Mem usage: 0.050 sys, 0.120 user, 366.83M mem + incr: 0.000 sys, 0.000 user, 1.19M mem + accu: 0.010 sys, 0.030 user, 27.49M mem + accu incr: 0.000 sys, 0.000 user, 1.19M mem + + Count usage: 12893 var, 8412 idcode, 3467 callback + incr: 0 var, 0 idcode, 0 callback + accu: 12893 var, 8412 idcode, 3467 callback + accu incr: 0 var, 0 idcode, 0 callback +296 Mon Jun 3 10:51:22 2024 +297 End of simulation at 3202992000 +298 Mon Jun 3 10:51:29 2024 +299 Begin FSDB profile info: +300 FSDB Writer : bc1(3262850) bcn(74166047) mtf/stf(0/15) +FSDB Writer elapsed time : flush(4.479019) io wait(0.000000) theadpool wait(0.000000) target functin(0.000000) +FSDB Writer cpu time : MT Compression : 0 +301 End FSDB profile info +302 Parallel profile - Flush:3 Expand:1 ProduceWait:0 ConsumerWait:110 BlockUsed:651 +303 ProduceTime:6.661204627 ConsumerTime:5.602404763 Buffer:96MB +304 SimExit +305 Sim process exit diff --git a/tb/chip_top/qbmcu_defines.v b/tb/chip_top/qbmcu_defines.v new file mode 100644 index 0000000..590fe2b --- /dev/null +++ b/tb/chip_top/qbmcu_defines.v @@ -0,0 +1,223 @@ + //+FHDR-------------------------------------------------------------------------------------------------------- +// Company: +//----------------------------------------------------------------------------------------------------------------- +// File Name : qbmcu.v +// Department : +// Author : PWY +// Author's Tel : +//----------------------------------------------------------------------------------------------------------------- +// Relese History +// Version Date Author Description +// 0.1 2024-03-13 PWY The files to include all the macro defines +//----------------------------------------------------------------------------------------------------------------- +// Keywords : +// +//----------------------------------------------------------------------------------------------------------------- +// Parameter +// +//----------------------------------------------------------------------------------------------------------------- +// Purpose : +// +//----------------------------------------------------------------------------------------------------------------- +// Target Device: +// Tool versions: +//----------------------------------------------------------------------------------------------------------------- +// Reuse Issues +// Reset Strategy: +// Clock Domains: +// Critical Timing: +// Asynchronous I/F: +// Synthesizable (y/n): +// Other: +//-FHDR-------------------------------------------------------------------------------------------------------- + + + +///////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////// +/////// ISA relevant macro +// +//system address width +`define QBMCU_ADDR_SIZE 32 + +//PC width +`define QBMCU_PC_SIZE 32 + +//system data width +`define QBMCU_XLEN 32 +//system instruction width +`define QBMCU_INSTR_SIZE 32 + +//register array index bit width +`define QBMCU_RFIDX_WIDTH 5 +//number of register arrays +`define QBMCU_RFREG_NUM 32 + +//base address of instruction memory +//initial value of the program counter (PC) -> 0x0000_0000 +`define QBMCU_ITCM_ADDR_BASE 32'h0000_0000 +//base address of data memory +`define QBMCU_DTCM_ADDR_BASE 32'h0010_0000 + +//data memory address width +`define QBMCU_DTCM_ADDR_SIZE 15 + +//instruction memory address width +`define QBMCU_ITCM_ADDR_SIZE 15 + +//BUS memory address width +`define QBMCU_BUS_ADDR_SIZE 25 + +///////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////// +/////// ALU relevant macro +// + +`define QBMCU_ALU_ADDER_WIDTH (`QBMCU_XLEN+1) + + +///////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////// +/////// Decode relevant macro +// + `define QBMCU_DECINFO_GRP_WIDTH 3 + `define QBMCU_DECINFO_GRP_ALU `QBMCU_DECINFO_GRP_WIDTH'd0 + `define QBMCU_DECINFO_GRP_AGU `QBMCU_DECINFO_GRP_WIDTH'd1 + `define QBMCU_DECINFO_GRP_BJP `QBMCU_DECINFO_GRP_WIDTH'd2 + `define QBMCU_DECINFO_GRP_EXT `QBMCU_DECINFO_GRP_WIDTH'd3 + + + `define QBMCU_DECINFO_GRP_LSB 0 + `define QBMCU_DECINFO_GRP_MSB (`QBMCU_DECINFO_GRP_LSB+`QBMCU_DECINFO_GRP_WIDTH-1) + `define QBMCU_DECINFO_GRP `QBMCU_DECINFO_GRP_MSB:`QBMCU_DECINFO_GRP_LSB + `define QBMCU_DECINFO_RV32_LSB (`QBMCU_DECINFO_GRP_MSB+1) + `define QBMCU_DECINFO_RV32_MSB (`QBMCU_DECINFO_RV32_LSB+1-1) + `define QBMCU_DECINFO_RV32 `QBMCU_DECINFO_RV32_MSB:`QBMCU_DECINFO_RV32_LSB + + `define QBMCU_DECINFO_SUBDECINFO_LSB (`QBMCU_DECINFO_RV32_MSB+1) + + // ALU group + `define QBMCU_DECINFO_ALU_ADD_LSB `QBMCU_DECINFO_SUBDECINFO_LSB + `define QBMCU_DECINFO_ALU_ADD_MSB (`QBMCU_DECINFO_ALU_ADD_LSB+1-1) + `define QBMCU_DECINFO_ALU_ADD `QBMCU_DECINFO_ALU_ADD_MSB :`QBMCU_DECINFO_ALU_ADD_LSB + `define QBMCU_DECINFO_ALU_SUB_LSB (`QBMCU_DECINFO_ALU_ADD_MSB+1) + `define QBMCU_DECINFO_ALU_SUB_MSB (`QBMCU_DECINFO_ALU_SUB_LSB+1-1) + `define QBMCU_DECINFO_ALU_SUB `QBMCU_DECINFO_ALU_SUB_MSB :`QBMCU_DECINFO_ALU_SUB_LSB + `define QBMCU_DECINFO_ALU_XOR_LSB (`QBMCU_DECINFO_ALU_SUB_MSB+1) + `define QBMCU_DECINFO_ALU_XOR_MSB (`QBMCU_DECINFO_ALU_XOR_LSB+1-1) + `define QBMCU_DECINFO_ALU_XOR `QBMCU_DECINFO_ALU_XOR_MSB :`QBMCU_DECINFO_ALU_XOR_LSB + `define QBMCU_DECINFO_ALU_SLL_LSB (`QBMCU_DECINFO_ALU_XOR_MSB+1) + `define QBMCU_DECINFO_ALU_SLL_MSB (`QBMCU_DECINFO_ALU_SLL_LSB+1-1) + `define QBMCU_DECINFO_ALU_SLL `QBMCU_DECINFO_ALU_SLL_MSB :`QBMCU_DECINFO_ALU_SLL_LSB + `define QBMCU_DECINFO_ALU_SRL_LSB (`QBMCU_DECINFO_ALU_SLL_MSB+1) + `define QBMCU_DECINFO_ALU_SRL_MSB (`QBMCU_DECINFO_ALU_SRL_LSB+1-1) + `define QBMCU_DECINFO_ALU_SRL `QBMCU_DECINFO_ALU_SRL_MSB :`QBMCU_DECINFO_ALU_SRL_LSB + `define QBMCU_DECINFO_ALU_SRA_LSB (`QBMCU_DECINFO_ALU_SRL_MSB+1) + `define QBMCU_DECINFO_ALU_SRA_MSB (`QBMCU_DECINFO_ALU_SRA_LSB+1-1) + `define QBMCU_DECINFO_ALU_SRA `QBMCU_DECINFO_ALU_SRA_MSB :`QBMCU_DECINFO_ALU_SRA_LSB + `define QBMCU_DECINFO_ALU_OR_LSB (`QBMCU_DECINFO_ALU_SRA_MSB+1) + `define QBMCU_DECINFO_ALU_OR_MSB (`QBMCU_DECINFO_ALU_OR_LSB+1-1) + `define QBMCU_DECINFO_ALU_OR `QBMCU_DECINFO_ALU_OR_MSB :`QBMCU_DECINFO_ALU_OR_LSB + `define QBMCU_DECINFO_ALU_AND_LSB (`QBMCU_DECINFO_ALU_OR_MSB+1) + `define QBMCU_DECINFO_ALU_AND_MSB (`QBMCU_DECINFO_ALU_AND_LSB+1-1) + `define QBMCU_DECINFO_ALU_AND `QBMCU_DECINFO_ALU_AND_MSB :`QBMCU_DECINFO_ALU_AND_LSB + `define QBMCU_DECINFO_ALU_SLT_LSB (`QBMCU_DECINFO_ALU_AND_MSB+1) + `define QBMCU_DECINFO_ALU_SLT_MSB (`QBMCU_DECINFO_ALU_SLT_LSB+1-1) + `define QBMCU_DECINFO_ALU_SLT `QBMCU_DECINFO_ALU_SLT_MSB :`QBMCU_DECINFO_ALU_SLT_LSB + `define QBMCU_DECINFO_ALU_SLTU_LSB (`QBMCU_DECINFO_ALU_SLT_MSB+1) + `define QBMCU_DECINFO_ALU_SLTU_MSB (`QBMCU_DECINFO_ALU_SLTU_LSB+1-1) + `define QBMCU_DECINFO_ALU_SLTU `QBMCU_DECINFO_ALU_SLTU_MSB:`QBMCU_DECINFO_ALU_SLTU_LSB + `define QBMCU_DECINFO_ALU_LUI_LSB (`QBMCU_DECINFO_ALU_SLTU_MSB+1) + `define QBMCU_DECINFO_ALU_LUI_MSB (`QBMCU_DECINFO_ALU_LUI_LSB+1-1) + `define QBMCU_DECINFO_ALU_LUI `QBMCU_DECINFO_ALU_LUI_MSB :`QBMCU_DECINFO_ALU_LUI_LSB + `define QBMCU_DECINFO_ALU_OP2IMM_LSB (`QBMCU_DECINFO_ALU_LUI_MSB+1) + `define QBMCU_DECINFO_ALU_OP2IMM_MSB (`QBMCU_DECINFO_ALU_OP2IMM_LSB+1-1) + `define QBMCU_DECINFO_ALU_OP2IMM `QBMCU_DECINFO_ALU_OP2IMM_MSB :`QBMCU_DECINFO_ALU_OP2IMM_LSB + `define QBMCU_DECINFO_ALU_OP1PC_LSB (`QBMCU_DECINFO_ALU_OP2IMM_MSB+1) + `define QBMCU_DECINFO_ALU_OP1PC_MSB (`QBMCU_DECINFO_ALU_OP1PC_LSB+1-1) + `define QBMCU_DECINFO_ALU_OP1PC `QBMCU_DECINFO_ALU_OP1PC_MSB :`QBMCU_DECINFO_ALU_OP1PC_LSB + `define QBMCU_DECINFO_ALU_NOP_LSB (`QBMCU_DECINFO_ALU_OP1PC_MSB+1) + `define QBMCU_DECINFO_ALU_NOP_MSB (`QBMCU_DECINFO_ALU_NOP_LSB+1-1) + `define QBMCU_DECINFO_ALU_NOP `QBMCU_DECINFO_ALU_NOP_MSB :`QBMCU_DECINFO_ALU_NOP_LSB + + `define QBMCU_DECINFO_ALU_WIDTH (`QBMCU_DECINFO_ALU_NOP_MSB+1) + + //AGU group + `define QBMCU_DECINFO_AGU_LOAD_LSB `QBMCU_DECINFO_SUBDECINFO_LSB + `define QBMCU_DECINFO_AGU_LOAD_MSB (`QBMCU_DECINFO_AGU_LOAD_LSB+1-1) + `define QBMCU_DECINFO_AGU_LOAD `QBMCU_DECINFO_AGU_LOAD_MSB :`QBMCU_DECINFO_AGU_LOAD_LSB + `define QBMCU_DECINFO_AGU_STORE_LSB (`QBMCU_DECINFO_AGU_LOAD_MSB+1) + `define QBMCU_DECINFO_AGU_STORE_MSB (`QBMCU_DECINFO_AGU_STORE_LSB+1-1) + `define QBMCU_DECINFO_AGU_STORE `QBMCU_DECINFO_AGU_STORE_MSB :`QBMCU_DECINFO_AGU_STORE_LSB + `define QBMCU_DECINFO_AGU_SIZE_LSB (`QBMCU_DECINFO_AGU_STORE_MSB+1) + `define QBMCU_DECINFO_AGU_SIZE_MSB (`QBMCU_DECINFO_AGU_SIZE_LSB+2-1) + `define QBMCU_DECINFO_AGU_SIZE `QBMCU_DECINFO_AGU_SIZE_MSB :`QBMCU_DECINFO_AGU_SIZE_LSB + `define QBMCU_DECINFO_AGU_USIGN_LSB (`QBMCU_DECINFO_AGU_SIZE_MSB+1) + `define QBMCU_DECINFO_AGU_USIGN_MSB (`QBMCU_DECINFO_AGU_USIGN_LSB+1-1) + `define QBMCU_DECINFO_AGU_USIGN `QBMCU_DECINFO_AGU_USIGN_MSB :`QBMCU_DECINFO_AGU_USIGN_LSB + `define QBMCU_DECINFO_AGU_OP2IMM_LSB (`QBMCU_DECINFO_AGU_USIGN_MSB+1) + `define QBMCU_DECINFO_AGU_OP2IMM_MSB (`QBMCU_DECINFO_AGU_OP2IMM_LSB+1-1) + `define QBMCU_DECINFO_AGU_OP2IMM `QBMCU_DECINFO_AGU_OP2IMM_MSB:`QBMCU_DECINFO_AGU_OP2IMM_LSB + + `define QBMCU_DECINFO_AGU_WIDTH (`QBMCU_DECINFO_AGU_OP2IMM_MSB+1) + + // Bxx group + `define QBMCU_DECINFO_BJP_JUMP_LSB `QBMCU_DECINFO_SUBDECINFO_LSB + `define QBMCU_DECINFO_BJP_JUMP_MSB (`QBMCU_DECINFO_BJP_JUMP_LSB+1-1) + `define QBMCU_DECINFO_BJP_JUMP `QBMCU_DECINFO_BJP_JUMP_MSB :`QBMCU_DECINFO_BJP_JUMP_LSB + `define QBMCU_DECINFO_BJP_BPRDT_LSB (`QBMCU_DECINFO_BJP_JUMP_MSB+1) + `define QBMCU_DECINFO_BJP_BPRDT_MSB (`QBMCU_DECINFO_BJP_BPRDT_LSB+1-1) + `define QBMCU_DECINFO_BJP_JALR `QBMCU_DECINFO_BJP_BPRDT_MSB:`QBMCU_DECINFO_BJP_BPRDT_LSB + `define QBMCU_DECINFO_BJP_BEQ_LSB (`QBMCU_DECINFO_BJP_BPRDT_MSB+1) + `define QBMCU_DECINFO_BJP_BEQ_MSB (`QBMCU_DECINFO_BJP_BEQ_LSB+1-1) + `define QBMCU_DECINFO_BJP_BEQ `QBMCU_DECINFO_BJP_BEQ_MSB :`QBMCU_DECINFO_BJP_BEQ_LSB + `define QBMCU_DECINFO_BJP_BNE_LSB (`QBMCU_DECINFO_BJP_BEQ_MSB+1) + `define QBMCU_DECINFO_BJP_BNE_MSB (`QBMCU_DECINFO_BJP_BNE_LSB+1-1) + `define QBMCU_DECINFO_BJP_BNE `QBMCU_DECINFO_BJP_BNE_MSB :`QBMCU_DECINFO_BJP_BNE_LSB + `define QBMCU_DECINFO_BJP_BLT_LSB (`QBMCU_DECINFO_BJP_BNE_MSB+1) + `define QBMCU_DECINFO_BJP_BLT_MSB (`QBMCU_DECINFO_BJP_BLT_LSB+1-1) + `define QBMCU_DECINFO_BJP_BLT `QBMCU_DECINFO_BJP_BLT_MSB :`QBMCU_DECINFO_BJP_BLT_LSB + `define QBMCU_DECINFO_BJP_BGT_LSB (`QBMCU_DECINFO_BJP_BLT_MSB+1) + `define QBMCU_DECINFO_BJP_BGT_MSB (`QBMCU_DECINFO_BJP_BGT_LSB+1-1) + `define QBMCU_DECINFO_BJP_BGT `QBMCU_DECINFO_BJP_BGT_MSB :`QBMCU_DECINFO_BJP_BGT_LSB + `define QBMCU_DECINFO_BJP_BLTU_LSB (`QBMCU_DECINFO_BJP_BGT_MSB+1) + `define QBMCU_DECINFO_BJP_BLTU_MSB (`QBMCU_DECINFO_BJP_BLTU_LSB+1-1) + `define QBMCU_DECINFO_BJP_BLTU `QBMCU_DECINFO_BJP_BLTU_MSB :`QBMCU_DECINFO_BJP_BLTU_LSB + `define QBMCU_DECINFO_BJP_BGTU_LSB (`QBMCU_DECINFO_BJP_BLTU_MSB+1) + `define QBMCU_DECINFO_BJP_BGTU_MSB (`QBMCU_DECINFO_BJP_BGTU_LSB+1-1) + `define QBMCU_DECINFO_BJP_BGTU `QBMCU_DECINFO_BJP_BGTU_MSB :`QBMCU_DECINFO_BJP_BGTU_LSB + `define QBMCU_DECINFO_BJP_BXX_LSB (`QBMCU_DECINFO_BJP_BGTU_MSB+1) + `define QBMCU_DECINFO_BJP_BXX_MSB (`QBMCU_DECINFO_BJP_BXX_LSB+1-1) + `define QBMCU_DECINFO_BJP_BXX `QBMCU_DECINFO_BJP_BXX_MSB :`QBMCU_DECINFO_BJP_BXX_LSB + +`define QBMCU_DECINFO_BJP_WIDTH (`QBMCU_DECINFO_BJP_BXX_MSB+1) + + + // EXT group + `define QBMCU_DECINFO_EXT_WAIT_LSB `QBMCU_DECINFO_SUBDECINFO_LSB + `define QBMCU_DECINFO_EXT_WAIT_MSB (`QBMCU_DECINFO_EXT_WAIT_LSB+1-1) + `define QBMCU_DECINFO_EXT_WAIT `QBMCU_DECINFO_EXT_WAIT_MSB:`QBMCU_DECINFO_EXT_WAIT_LSB + `define QBMCU_DECINFO_EXT_SEND_LSB (`QBMCU_DECINFO_EXT_WAIT_MSB+1) + `define QBMCU_DECINFO_EXT_SEND_MSB (`QBMCU_DECINFO_EXT_SEND_LSB+1-1) + `define QBMCU_DECINFO_EXT_SEND `QBMCU_DECINFO_EXT_SEND_MSB:`QBMCU_DECINFO_EXT_SEND_LSB + `define QBMCU_DECINFO_EXT_SENDC_LSB (`QBMCU_DECINFO_EXT_SEND_MSB+1) + `define QBMCU_DECINFO_EXT_SENDC_MSB (`QBMCU_DECINFO_EXT_SENDC_LSB+1-1) + `define QBMCU_DECINFO_EXT_SENDC `QBMCU_DECINFO_EXT_SENDC_MSB:`QBMCU_DECINFO_EXT_SENDC_LSB + `define QBMCU_DECINFO_EXT_EXIT_LSB (`QBMCU_DECINFO_EXT_SENDC_MSB+1) + `define QBMCU_DECINFO_EXT_EXIT_MSB (`QBMCU_DECINFO_EXT_EXIT_LSB+1-1) + `define QBMCU_DECINFO_EXT_EXIT `QBMCU_DECINFO_EXT_EXIT_MSB:`QBMCU_DECINFO_EXT_EXIT_LSB + `define QBMCU_DECINFO_EXT_EXITI_LSB (`QBMCU_DECINFO_EXT_EXIT_MSB+1) + `define QBMCU_DECINFO_EXT_EXITI_MSB (`QBMCU_DECINFO_EXT_EXITI_LSB+1-1) + `define QBMCU_DECINFO_EXT_EXITI `QBMCU_DECINFO_EXT_EXITI_MSB:`QBMCU_DECINFO_EXT_EXITI_LSB + `define QBMCU_DECINFO_EXT_OP2IMM_LSB (`QBMCU_DECINFO_EXT_EXITI_MSB+1) + `define QBMCU_DECINFO_EXT_OP2IMM_MSB (`QBMCU_DECINFO_EXT_OP2IMM_LSB+1-1) + `define QBMCU_DECINFO_EXT_OP2IMM `QBMCU_DECINFO_EXT_OP2IMM_MSB:`QBMCU_DECINFO_EXT_OP2IMM_LSB + +`define QBMCU_DECINFO_EXT_WIDTH (`QBMCU_DECINFO_EXT_OP2IMM_MSB+1) + +// Choose the longest group as the final DEC info width +`define QBMCU_DECINFO_WIDTH (`QBMCU_DECINFO_ALU_WIDTH+1) + diff --git a/tb/chip_top/qbmcu_undefines.v b/tb/chip_top/qbmcu_undefines.v new file mode 100644 index 0000000..2650f70 --- /dev/null +++ b/tb/chip_top/qbmcu_undefines.v @@ -0,0 +1,219 @@ + //+FHDR-------------------------------------------------------------------------------------------------------- +// Company: +//----------------------------------------------------------------------------------------------------------------- +// File Name : qbmcu.v +// Department : +// Author : PWY +// Author's Tel : +//----------------------------------------------------------------------------------------------------------------- +// Relese History +// Version Date Author Description +// 0.1 2024-03-13 PWY The files to include all the macro undefs +//----------------------------------------------------------------------------------------------------------------- +// Keywords : +// +//----------------------------------------------------------------------------------------------------------------- +// Parameter +// +//----------------------------------------------------------------------------------------------------------------- +// Purpose : +// +//----------------------------------------------------------------------------------------------------------------- +// Target Device: +// Tool versions: +//----------------------------------------------------------------------------------------------------------------- +// Reuse Issues +// Reset Strategy: +// Clock Domains: +// Critical Timing: +// Asynchronous I/F: +// Synthesizable (y/n): +// Other: +//-FHDR-------------------------------------------------------------------------------------------------------- + + + +///////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////// +/////// ISA relevant macro +// +//system address width +`undef QBMCU_ADDR_SIZE + +//PC width +`undef QBMCU_PC_SIZE + +//system data width +`undef QBMCU_XLEN +//system instruction width +`undef QBMCU_INSTR_SIZE + +//register array index bit width +`undef QBMCU_RFIDX_WIDTH +//number of register arrays +`undef QBMCU_RFREG_NUM + +//base address of instruction memory +//initial value of the program counter (PC) -> 0x0000_0000 +`undef QBMCU_DTCM_ADDR_BASE +//base address of data memory +`undef QBMCU_ITCM_ADDR_BASE + +//data memory address width +`undef QBMCU_DTCM_ADDR_SIZE + +//instruction memory address width +`undef QBMCU_ITCM_ADDR_SIZE + +//BUS memory address width +`undef QBMCU_BUS_ADDR_SIZE + +///////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////// +/////// ALU relevant macro +// + +`undef QBMCU_ALU_ADDER_WIDTH + + +///////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////// +/////// Decode relevant macro +// +`undef QBMCU_DECINFO_GRP_WIDTH +`undef QBMCU_DECINFO_GRP_ALU +`undef QBMCU_DECINFO_GRP_AGU +`undef QBMCU_DECINFO_GRP_BJP +`undef QBMCU_DECINFO_GRP_EXT + + +`undef QBMCU_DECINFO_GRP_LSB +`undef QBMCU_DECINFO_GRP_MSB +`undef QBMCU_DECINFO_GRP +`undef QBMCU_DECINFO_RV32_LSB +`undef QBMCU_DECINFO_RV32_MSB +`undef QBMCU_DECINFO_RV32 + +`undef QBMCU_DECINFO_SUBDECINFO_LSB + +// ALU group +`undef QBMCU_DECINFO_ALU_ADD_LSB +`undef QBMCU_DECINFO_ALU_ADD_MSB +`undef QBMCU_DECINFO_ALU_ADD +`undef QBMCU_DECINFO_ALU_SUB_LSB +`undef QBMCU_DECINFO_ALU_SUB_MSB +`undef QBMCU_DECINFO_ALU_SUB +`undef QBMCU_DECINFO_ALU_XOR_LSB +`undef QBMCU_DECINFO_ALU_XOR_MSB +`undef QBMCU_DECINFO_ALU_XOR +`undef QBMCU_DECINFO_ALU_SLL_LSB +`undef QBMCU_DECINFO_ALU_SLL_MSB +`undef QBMCU_DECINFO_ALU_SLL +`undef QBMCU_DECINFO_ALU_SRL_LSB +`undef QBMCU_DECINFO_ALU_SRL_MSB +`undef QBMCU_DECINFO_ALU_SRL +`undef QBMCU_DECINFO_ALU_SRA_LSB +`undef QBMCU_DECINFO_ALU_SRA_MSB +`undef QBMCU_DECINFO_ALU_SRA +`undef QBMCU_DECINFO_ALU_OR_LSB +`undef QBMCU_DECINFO_ALU_OR_MSB +`undef QBMCU_DECINFO_ALU_OR +`undef QBMCU_DECINFO_ALU_AND_LSB +`undef QBMCU_DECINFO_ALU_AND_MSB +`undef QBMCU_DECINFO_ALU_AND +`undef QBMCU_DECINFO_ALU_SLT_LSB +`undef QBMCU_DECINFO_ALU_SLT_MSB +`undef QBMCU_DECINFO_ALU_SLT +`undef QBMCU_DECINFO_ALU_SLTU_LSB +`undef QBMCU_DECINFO_ALU_SLTU_MSB +`undef QBMCU_DECINFO_ALU_SLTU +`undef QBMCU_DECINFO_ALU_LUI_LSB +`undef QBMCU_DECINFO_ALU_LUI_MSB +`undef QBMCU_DECINFO_ALU_LUI +`undef QBMCU_DECINFO_ALU_OP2IMM_LSB +`undef QBMCU_DECINFO_ALU_OP2IMM_MSB +`undef QBMCU_DECINFO_ALU_OP2IMM +`undef QBMCU_DECINFO_ALU_OP1PC_LSB +`undef QBMCU_DECINFO_ALU_OP1PC_MSB +`undef QBMCU_DECINFO_ALU_OP1PC +`undef QBMCU_DECINFO_ALU_NOP_LSB +`undef QBMCU_DECINFO_ALU_NOP_MSB +`undef QBMCU_DECINFO_ALU_NOP +`undef QBMCU_DECINFO_ALU_WIDTH + +//AGU group +`undef QBMCU_DECINFO_AGU_LOAD_LSB +`undef QBMCU_DECINFO_AGU_LOAD_MSB +`undef QBMCU_DECINFO_AGU_LOAD +`undef QBMCU_DECINFO_AGU_STORE_LSB +`undef QBMCU_DECINFO_AGU_STORE_MSB +`undef QBMCU_DECINFO_AGU_STORE +`undef QBMCU_DECINFO_AGU_SIZE_LSB +`undef QBMCU_DECINFO_AGU_SIZE_MSB +`undef QBMCU_DECINFO_AGU_SIZE +`undef QBMCU_DECINFO_AGU_USIGN_LSB +`undef QBMCU_DECINFO_AGU_USIGN_MSB +`undef QBMCU_DECINFO_AGU_USIGN +`undef QBMCU_DECINFO_AGU_OP2IMM_LSB +`undef QBMCU_DECINFO_AGU_OP2IMM_MSB +`undef QBMCU_DECINFO_AGU_OP2IMM +`undef QBMCU_DECINFO_AGU_WIDTH + +// Bxx group +`undef QBMCU_DECINFO_BJP_JUMP_LSB +`undef QBMCU_DECINFO_BJP_JUMP_MSB +`undef QBMCU_DECINFO_BJP_JUMP +`undef QBMCU_DECINFO_BJP_BPRDT_LSB +`undef QBMCU_DECINFO_BJP_BPRDT_MSB +`undef QBMCU_DECINFO_BJP_JALR +`undef QBMCU_DECINFO_BJP_BEQ_LSB +`undef QBMCU_DECINFO_BJP_BEQ_MSB +`undef QBMCU_DECINFO_BJP_BEQ +`undef QBMCU_DECINFO_BJP_BNE_LSB +`undef QBMCU_DECINFO_BJP_BNE_MSB +`undef QBMCU_DECINFO_BJP_BNE +`undef QBMCU_DECINFO_BJP_BLT_LSB +`undef QBMCU_DECINFO_BJP_BLT_MSB +`undef QBMCU_DECINFO_BJP_BLT +`undef QBMCU_DECINFO_BJP_BGT_LSB +`undef QBMCU_DECINFO_BJP_BGT_MSB +`undef QBMCU_DECINFO_BJP_BGT +`undef QBMCU_DECINFO_BJP_BLTU_LSB +`undef QBMCU_DECINFO_BJP_BLTU_MSB +`undef QBMCU_DECINFO_BJP_BLTU +`undef QBMCU_DECINFO_BJP_BGTU_LSB +`undef QBMCU_DECINFO_BJP_BGTU_MSB +`undef QBMCU_DECINFO_BJP_BGTU +`undef QBMCU_DECINFO_BJP_BXX_LSB +`undef QBMCU_DECINFO_BJP_BXX_MSB +`undef QBMCU_DECINFO_BJP_BXX +`undef QBMCU_DECINFO_BJP_WIDTH + + +// EXT group +`undef QBMCU_DECINFO_EXT_WAIT_LSB +`undef QBMCU_DECINFO_EXT_WAIT_MSB +`undef QBMCU_DECINFO_EXT_WAIT +`undef QBMCU_DECINFO_EXT_SEND_LSB +`undef QBMCU_DECINFO_EXT_SEND_MSB +`undef QBMCU_DECINFO_EXT_SEND +`undef QBMCU_DECINFO_EXT_SENDC_LSB +`undef QBMCU_DECINFO_EXT_SENDC_MSB +`undef QBMCU_DECINFO_EXT_SENDC +`undef QBMCU_DECINFO_EXT_EXIT_LSB +`undef QBMCU_DECINFO_EXT_EXIT_MSB +`undef QBMCU_DECINFO_EXT_EXIT +`undef QBMCU_DECINFO_EXT_EXITI_LSB +`undef QBMCU_DECINFO_EXT_EXITI_MSB +`undef QBMCU_DECINFO_EXT_EXITI +`undef QBMCU_DECINFO_EXT_OP2IMM_LSB +`undef QBMCU_DECINFO_EXT_OP2IMM_MSB +`undef QBMCU_DECINFO_EXT_OP2IMM +`undef QBMCU_DECINFO_EXT_WIDTH + +// Choose the longest group as the final DEC info width +`undef QBMCU_DECINFO_WIDTH + diff --git a/tb/chip_top/sim.log b/tb/chip_top/sim.log new file mode 100644 index 0000000..d1f65e7 --- /dev/null +++ b/tb/chip_top/sim.log @@ -0,0 +1,29411 @@ +Command: /home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/chip_top/./simv -l sim.log +Chronologic VCS simulator copyright 1991-2018 +Contains Synopsys proprietary information. +Compiler version O-2018.09-SP2_Full64; Runtime version O-2018.09-SP2_Full64; Jun 3 10:51 2024 +*Verdi* Loading libsscore_vcs201809.so +FSDB Dumper for VCS, Release Verdi_O-2018.09-SP2, Linux x86_64/64bit, 02/21/2019 +(C) 1996 - 2019 by Synopsys, Inc. +*Verdi* FSDB WARNING: The FSDB file already exists. Overwriting the FSDB file may crash the programs that are using this file. +*Verdi* FSDB: The switch FSDB file size might not match the input size (500MB) because of performance concerns. +*Verdi* FSDB: To have the FSDB file size match the input size (500MB), set the FSDB_ENV_PRECISE_AUTOSWITCH environment, though the dumping performance might decrease. +*Verdi* : Enable automatic switching of the FSDB file. +*Verdi* : (Filename='./verdplus', Limit Size=500MB, File Amount=1000000). +*Verdi* : Create FSDB file './verdplus_000.fsdb' +*Verdi* : Create the file './verdplus.log' to log the time range of each FSDB file. +*Verdi* : Create virtual FSDB file './verdplus.vf' to log each FSDB file. +*Verdi* : Begin traversing the scopes, layer (0). +*Verdi* : End of traversing. +write_item 0000000000000000000011010000000000000000000000000000000000000111 +write_item 63: 0 +write_item 62: 0 +write_item 61: 0 +write_item 60: 0 +write_item 59: 0 +write_item 58: 0 +write_item 57: 0 +write_item 56: 0 +write_item 55: 0 +write_item 54: 0 +write_item 53: 0 +write_item 52: 0 +write_item 51: 0 +write_item 50: 0 +write_item 49: 0 +write_item 48: 0 +write_item 47: 0 +write_item 46: 0 +write_item 45: 0 +write_item 44: 0 +write_item 43: 1 +write_item 42: 1 +write_item 41: 0 +write_item 40: 1 +write_item 39: 0 +write_item 38: 0 +write_item 37: 0 +write_item 36: 0 +write_item 35: 0 +write_item 34: 0 +write_item 33: 0 +write_item 32: 0 +write_item 31: 0 +write_item 30: 0 +write_item 29: 0 +write_item 28: 0 +write_item 27: 0 +write_item 26: 0 +write_item 25: 0 +write_item 24: 0 +write_item 23: 0 +write_item 22: 0 +write_item 21: 0 +write_item 20: 0 +write_item 19: 0 +write_item 18: 0 +write_item 17: 0 +write_item 16: 0 +write_item 15: 0 +write_item 14: 0 +write_item 13: 0 +write_item 12: 0 +write_item 11: 0 +write_item 10: 0 +write_item 9: 0 +write_item 8: 0 +write_item 7: 0 +write_item 6: 0 +write_item 5: 0 +write_item 4: 0 +write_item 3: 0 +write_item 2: 1 +write_item 1: 1 +write_item 0: 1 +reg 0: 0 +reg 1: 0 +reg 2: 0 +reg 3: 0 +reg 4: 0 +reg 5: 0 +reg 6: 0 +reg 7: 0 +reg 8: 0 +reg 9: 0 +reg 10: 0 +reg 11: 0 +reg 12: 0 +reg 13: 0 +reg 14: 0 +reg 15: 0 +reg 16: 0 +reg 17: 0 +reg 18: 0 +reg 19: 0 +reg 20: 1 +reg 21: 1 +reg 22: 0 +reg 23: 1 +reg 24: 0 +reg 25: 0 +reg 26: 0 +reg 27: 0 +reg 28: 0 +reg 29: 0 +reg 30: 0 +reg 31: 0 +reg 32: 0 +reg 33: 0 +reg 34: 0 +reg 35: 0 +reg 36: 0 +reg 37: 0 +reg 38: 0 +reg 39: 0 +reg 40: 0 +reg 41: 0 +reg 42: 0 +reg 43: 0 +reg 44: 0 +reg 45: 0 +reg 46: 0 +reg 47: 0 +reg 48: 0 +reg 49: 0 +reg 50: 0 +reg 51: 0 +reg 52: 0 +reg 53: 0 +reg 54: 0 +reg 55: 0 +reg 56: 0 +reg 57: 0 +reg 58: 0 +reg 59: 0 +reg 60: 0 +reg 61: 1 +reg 62: 1 +reg 63: 1 +write_item 0000110000000000010010100000000000000000000000000000000000000000 +write_item 63: 0 +write_item 62: 0 +write_item 61: 0 +write_item 60: 0 +write_item 59: 1 +write_item 58: 1 +write_item 57: 0 +write_item 56: 0 +write_item 55: 0 +write_item 54: 0 +write_item 53: 0 +write_item 52: 0 +write_item 51: 0 +write_item 50: 0 +write_item 49: 0 +write_item 48: 0 +write_item 47: 0 +write_item 46: 1 +write_item 45: 0 +write_item 44: 0 +write_item 43: 1 +write_item 42: 0 +write_item 41: 1 +write_item 40: 0 +write_item 39: 0 +write_item 38: 0 +write_item 37: 0 +write_item 36: 0 +write_item 35: 0 +write_item 34: 0 +write_item 33: 0 +write_item 32: 0 +write_item 31: 0 +write_item 30: 0 +write_item 29: 0 +write_item 28: 0 +write_item 27: 0 +write_item 26: 0 +write_item 25: 0 +write_item 24: 0 +write_item 23: 0 +write_item 22: 0 +write_item 21: 0 +write_item 20: 0 +write_item 19: 0 +write_item 18: 0 +write_item 17: 0 +write_item 16: 0 +write_item 15: 0 +write_item 14: 0 +write_item 13: 0 +write_item 12: 0 +write_item 11: 0 +write_item 10: 0 +write_item 9: 0 +write_item 8: 0 +write_item 7: 0 +write_item 6: 0 +write_item 5: 0 +write_item 4: 0 +write_item 3: 0 +write_item 2: 0 +write_item 1: 0 +write_item 0: 0 +reg 0: 0 +reg 1: 0 +reg 2: 0 +reg 3: 0 +reg 4: 1 +reg 5: 1 +reg 6: 0 +reg 7: 0 +reg 8: 0 +reg 9: 0 +reg 10: 0 +reg 11: 0 +reg 12: 0 +reg 13: 0 +reg 14: 0 +reg 15: 0 +reg 16: 0 +reg 17: 1 +reg 18: 0 +reg 19: 0 +reg 20: 1 +reg 21: 0 +reg 22: 1 +reg 23: 0 +reg 24: 0 +reg 25: 0 +reg 26: 0 +reg 27: 0 +reg 28: 0 +reg 29: 0 +reg 30: 0 +reg 31: 0 +reg 32: 0 +reg 33: 0 +reg 34: 0 +reg 35: 0 +reg 36: 0 +reg 37: 0 +reg 38: 0 +reg 39: 0 +reg 40: 0 +reg 41: 0 +reg 42: 0 +reg 43: 0 +reg 44: 0 +reg 45: 0 +reg 46: 0 +reg 47: 0 +reg 48: 0 +reg 49: 0 +reg 50: 0 +reg 51: 0 +reg 52: 0 +reg 53: 0 +reg 54: 0 +reg 55: 0 +reg 56: 0 +reg 57: 0 +reg 58: 0 +reg 59: 0 +reg 60: 0 +reg 61: 0 +reg 62: 0 +reg 63: 0 +write_item 0000110000000000010000010000000000000000000000000000000000000100 +write_item 63: 0 +write_item 62: 0 +write_item 61: 0 +write_item 60: 0 +write_item 59: 1 +write_item 58: 1 +write_item 57: 0 +write_item 56: 0 +write_item 55: 0 +write_item 54: 0 +write_item 53: 0 +write_item 52: 0 +write_item 51: 0 +write_item 50: 0 +write_item 49: 0 +write_item 48: 0 +write_item 47: 0 +write_item 46: 1 +write_item 45: 0 +write_item 44: 0 +write_item 43: 0 +write_item 42: 0 +write_item 41: 0 +write_item 40: 1 +write_item 39: 0 +write_item 38: 0 +write_item 37: 0 +write_item 36: 0 +write_item 35: 0 +write_item 34: 0 +write_item 33: 0 +write_item 32: 0 +write_item 31: 0 +write_item 30: 0 +write_item 29: 0 +write_item 28: 0 +write_item 27: 0 +write_item 26: 0 +write_item 25: 0 +write_item 24: 0 +write_item 23: 0 +write_item 22: 0 +write_item 21: 0 +write_item 20: 0 +write_item 19: 0 +write_item 18: 0 +write_item 17: 0 +write_item 16: 0 +write_item 15: 0 +write_item 14: 0 +write_item 13: 0 +write_item 12: 0 +write_item 11: 0 +write_item 10: 0 +write_item 9: 0 +write_item 8: 0 +write_item 7: 0 +write_item 6: 0 +write_item 5: 0 +write_item 4: 0 +write_item 3: 0 +write_item 2: 1 +write_item 1: 0 +write_item 0: 0 +reg 0: 0 +reg 1: 0 +reg 2: 0 +reg 3: 0 +reg 4: 1 +reg 5: 1 +reg 6: 0 +reg 7: 0 +reg 8: 0 +reg 9: 0 +reg 10: 0 +reg 11: 0 +reg 12: 0 +reg 13: 0 +reg 14: 0 +reg 15: 0 +reg 16: 0 +reg 17: 1 +reg 18: 0 +reg 19: 0 +reg 20: 0 +reg 21: 0 +reg 22: 0 +reg 23: 1 +reg 24: 0 +reg 25: 0 +reg 26: 0 +reg 27: 0 +reg 28: 0 +reg 29: 0 +reg 30: 0 +reg 31: 0 +reg 32: 0 +reg 33: 0 +reg 34: 0 +reg 35: 0 +reg 36: 0 +reg 37: 0 +reg 38: 0 +reg 39: 0 +reg 40: 0 +reg 41: 0 +reg 42: 0 +reg 43: 0 +reg 44: 0 +reg 45: 0 +reg 46: 0 +reg 47: 0 +reg 48: 0 +reg 49: 0 +reg 50: 0 +reg 51: 0 +reg 52: 0 +reg 53: 0 +reg 54: 0 +reg 55: 0 +reg 56: 0 +reg 57: 0 +reg 58: 0 +reg 59: 0 +reg 60: 0 +reg 61: 1 +reg 62: 0 +reg 63: 0 +write_item 0000110000000000010010110000000000000000000000000000000000000001 +write_item 63: 0 +write_item 62: 0 +write_item 61: 0 +write_item 60: 0 +write_item 59: 1 +write_item 58: 1 +write_item 57: 0 +write_item 56: 0 +write_item 55: 0 +write_item 54: 0 +write_item 53: 0 +write_item 52: 0 +write_item 51: 0 +write_item 50: 0 +write_item 49: 0 +write_item 48: 0 +write_item 47: 0 +write_item 46: 1 +write_item 45: 0 +write_item 44: 0 +write_item 43: 1 +write_item 42: 0 +write_item 41: 1 +write_item 40: 1 +write_item 39: 0 +write_item 38: 0 +write_item 37: 0 +write_item 36: 0 +write_item 35: 0 +write_item 34: 0 +write_item 33: 0 +write_item 32: 0 +write_item 31: 0 +write_item 30: 0 +write_item 29: 0 +write_item 28: 0 +write_item 27: 0 +write_item 26: 0 +write_item 25: 0 +write_item 24: 0 +write_item 23: 0 +write_item 22: 0 +write_item 21: 0 +write_item 20: 0 +write_item 19: 0 +write_item 18: 0 +write_item 17: 0 +write_item 16: 0 +write_item 15: 0 +write_item 14: 0 +write_item 13: 0 +write_item 12: 0 +write_item 11: 0 +write_item 10: 0 +write_item 9: 0 +write_item 8: 0 +write_item 7: 0 +write_item 6: 0 +write_item 5: 0 +write_item 4: 0 +write_item 3: 0 +write_item 2: 0 +write_item 1: 0 +write_item 0: 1 +reg 0: 0 +reg 1: 0 +reg 2: 0 +reg 3: 0 +reg 4: 1 +reg 5: 1 +reg 6: 0 +reg 7: 0 +reg 8: 0 +reg 9: 0 +reg 10: 0 +reg 11: 0 +reg 12: 0 +reg 13: 0 +reg 14: 0 +reg 15: 0 +reg 16: 0 +reg 17: 1 +reg 18: 0 +reg 19: 0 +reg 20: 1 +reg 21: 0 +reg 22: 1 +reg 23: 1 +reg 24: 0 +reg 25: 0 +reg 26: 0 +reg 27: 0 +reg 28: 0 +reg 29: 0 +reg 30: 0 +reg 31: 0 +reg 32: 0 +reg 33: 0 +reg 34: 0 +reg 35: 0 +reg 36: 0 +reg 37: 0 +reg 38: 0 +reg 39: 0 +reg 40: 0 +reg 41: 0 +reg 42: 0 +reg 43: 0 +reg 44: 0 +reg 45: 0 +reg 46: 0 +reg 47: 0 +reg 48: 0 +reg 49: 0 +reg 50: 0 +reg 51: 0 +reg 52: 0 +reg 53: 0 +reg 54: 0 +reg 55: 0 +reg 56: 0 +reg 57: 0 +reg 58: 0 +reg 59: 0 +reg 60: 0 +reg 61: 0 +reg 62: 0 +reg 63: 1 +write_item 0000110000000000010011000000000000000000000000000000000000000000 +write_item 63: 0 +write_item 62: 0 +write_item 61: 0 +write_item 60: 0 +write_item 59: 1 +write_item 58: 1 +write_item 57: 0 +write_item 56: 0 +write_item 55: 0 +write_item 54: 0 +write_item 53: 0 +write_item 52: 0 +write_item 51: 0 +write_item 50: 0 +write_item 49: 0 +write_item 48: 0 +write_item 47: 0 +write_item 46: 1 +write_item 45: 0 +write_item 44: 0 +write_item 43: 1 +write_item 42: 1 +write_item 41: 0 +write_item 40: 0 +write_item 39: 0 +write_item 38: 0 +write_item 37: 0 +write_item 36: 0 +write_item 35: 0 +write_item 34: 0 +write_item 33: 0 +write_item 32: 0 +write_item 31: 0 +write_item 30: 0 +write_item 29: 0 +write_item 28: 0 +write_item 27: 0 +write_item 26: 0 +write_item 25: 0 +write_item 24: 0 +write_item 23: 0 +write_item 22: 0 +write_item 21: 0 +write_item 20: 0 +write_item 19: 0 +write_item 18: 0 +write_item 17: 0 +write_item 16: 0 +write_item 15: 0 +write_item 14: 0 +write_item 13: 0 +write_item 12: 0 +write_item 11: 0 +write_item 10: 0 +write_item 9: 0 +write_item 8: 0 +write_item 7: 0 +write_item 6: 0 +write_item 5: 0 +write_item 4: 0 +write_item 3: 0 +write_item 2: 0 +write_item 1: 0 +write_item 0: 0 +reg 0: 0 +reg 1: 0 +reg 2: 0 +reg 3: 0 +reg 4: 1 +reg 5: 1 +reg 6: 0 +reg 7: 0 +reg 8: 0 +reg 9: 0 +reg 10: 0 +reg 11: 0 +reg 12: 0 +reg 13: 0 +reg 14: 0 +reg 15: 0 +reg 16: 0 +reg 17: 1 +reg 18: 0 +reg 19: 0 +reg 20: 1 +reg 21: 1 +reg 22: 0 +reg 23: 0 +reg 24: 0 +reg 25: 0 +reg 26: 0 +reg 27: 0 +reg 28: 0 +reg 29: 0 +reg 30: 0 +reg 31: 0 +reg 32: 0 +reg 33: 0 +reg 34: 0 +reg 35: 0 +reg 36: 0 +reg 37: 0 +reg 38: 0 +reg 39: 0 +reg 40: 0 +reg 41: 0 +reg 42: 0 +reg 43: 0 +reg 44: 0 +reg 45: 0 +reg 46: 0 +reg 47: 0 +reg 48: 0 +reg 49: 0 +reg 50: 0 +reg 51: 0 +reg 52: 0 +reg 53: 0 +reg 54: 0 +reg 55: 0 +reg 56: 0 +reg 57: 0 +reg 58: 0 +reg 59: 0 +reg 60: 0 +reg 61: 0 +reg 62: 0 +reg 63: 0 +write_item 0000110000000000010000110000000001101010101010101010101010101010 +write_item 63: 0 +write_item 62: 0 +write_item 61: 0 +write_item 60: 0 +write_item 59: 1 +write_item 58: 1 +write_item 57: 0 +write_item 56: 0 +write_item 55: 0 +write_item 54: 0 +write_item 53: 0 +write_item 52: 0 +write_item 51: 0 +write_item 50: 0 +write_item 49: 0 +write_item 48: 0 +write_item 47: 0 +write_item 46: 1 +write_item 45: 0 +write_item 44: 0 +write_item 43: 0 +write_item 42: 0 +write_item 41: 1 +write_item 40: 1 +write_item 39: 0 +write_item 38: 0 +write_item 37: 0 +write_item 36: 0 +write_item 35: 0 +write_item 34: 0 +write_item 33: 0 +write_item 32: 0 +write_item 31: 0 +write_item 30: 1 +write_item 29: 1 +write_item 28: 0 +write_item 27: 1 +write_item 26: 0 +write_item 25: 1 +write_item 24: 0 +write_item 23: 1 +write_item 22: 0 +write_item 21: 1 +write_item 20: 0 +write_item 19: 1 +write_item 18: 0 +write_item 17: 1 +write_item 16: 0 +write_item 15: 1 +write_item 14: 0 +write_item 13: 1 +write_item 12: 0 +write_item 11: 1 +write_item 10: 0 +write_item 9: 1 +write_item 8: 0 +write_item 7: 1 +write_item 6: 0 +write_item 5: 1 +write_item 4: 0 +write_item 3: 1 +write_item 2: 0 +write_item 1: 1 +write_item 0: 0 +reg 0: 0 +reg 1: 0 +reg 2: 0 +reg 3: 0 +reg 4: 1 +reg 5: 1 +reg 6: 0 +reg 7: 0 +reg 8: 0 +reg 9: 0 +reg 10: 0 +reg 11: 0 +reg 12: 0 +reg 13: 0 +reg 14: 0 +reg 15: 0 +reg 16: 0 +reg 17: 1 +reg 18: 0 +reg 19: 0 +reg 20: 0 +reg 21: 0 +reg 22: 1 +reg 23: 1 +reg 24: 0 +reg 25: 0 +reg 26: 0 +reg 27: 0 +reg 28: 0 +reg 29: 0 +reg 30: 0 +reg 31: 0 +reg 32: 0 +reg 33: 1 +reg 34: 1 +reg 35: 0 +reg 36: 1 +reg 37: 0 +reg 38: 1 +reg 39: 0 +reg 40: 1 +reg 41: 0 +reg 42: 1 +reg 43: 0 +reg 44: 1 +reg 45: 0 +reg 46: 1 +reg 47: 0 +reg 48: 1 +reg 49: 0 +reg 50: 1 +reg 51: 0 +reg 52: 1 +reg 53: 0 +reg 54: 1 +reg 55: 0 +reg 56: 1 +reg 57: 0 +reg 58: 1 +reg 59: 0 +reg 60: 1 +reg 61: 0 +reg 62: 1 +reg 63: 0 +write_item 0000110000000000010001000000000010101010101010100000000000000000 +write_item 63: 0 +write_item 62: 0 +write_item 61: 0 +write_item 60: 0 +write_item 59: 1 +write_item 58: 1 +write_item 57: 0 +write_item 56: 0 +write_item 55: 0 +write_item 54: 0 +write_item 53: 0 +write_item 52: 0 +write_item 51: 0 +write_item 50: 0 +write_item 49: 0 +write_item 48: 0 +write_item 47: 0 +write_item 46: 1 +write_item 45: 0 +write_item 44: 0 +write_item 43: 0 +write_item 42: 1 +write_item 41: 0 +write_item 40: 0 +write_item 39: 0 +write_item 38: 0 +write_item 37: 0 +write_item 36: 0 +write_item 35: 0 +write_item 34: 0 +write_item 33: 0 +write_item 32: 0 +write_item 31: 1 +write_item 30: 0 +write_item 29: 1 +write_item 28: 0 +write_item 27: 1 +write_item 26: 0 +write_item 25: 1 +write_item 24: 0 +write_item 23: 1 +write_item 22: 0 +write_item 21: 1 +write_item 20: 0 +write_item 19: 1 +write_item 18: 0 +write_item 17: 1 +write_item 16: 0 +write_item 15: 0 +write_item 14: 0 +write_item 13: 0 +write_item 12: 0 +write_item 11: 0 +write_item 10: 0 +write_item 9: 0 +write_item 8: 0 +write_item 7: 0 +write_item 6: 0 +write_item 5: 0 +write_item 4: 0 +write_item 3: 0 +write_item 2: 0 +write_item 1: 0 +write_item 0: 0 +reg 0: 0 +reg 1: 0 +reg 2: 0 +reg 3: 0 +reg 4: 1 +reg 5: 1 +reg 6: 0 +reg 7: 0 +reg 8: 0 +reg 9: 0 +reg 10: 0 +reg 11: 0 +reg 12: 0 +reg 13: 0 +reg 14: 0 +reg 15: 0 +reg 16: 0 +reg 17: 1 +reg 18: 0 +reg 19: 0 +reg 20: 0 +reg 21: 1 +reg 22: 0 +reg 23: 0 +reg 24: 0 +reg 25: 0 +reg 26: 0 +reg 27: 0 +reg 28: 0 +reg 29: 0 +reg 30: 0 +reg 31: 0 +reg 32: 1 +reg 33: 0 +reg 34: 1 +reg 35: 0 +reg 36: 1 +reg 37: 0 +reg 38: 1 +reg 39: 0 +reg 40: 1 +reg 41: 0 +reg 42: 1 +reg 43: 0 +reg 44: 1 +reg 45: 0 +reg 46: 1 +reg 47: 0 +reg 48: 0 +reg 49: 0 +reg 50: 0 +reg 51: 0 +reg 52: 0 +reg 53: 0 +reg 54: 0 +reg 55: 0 +reg 56: 0 +reg 57: 0 +reg 58: 0 +reg 59: 0 +reg 60: 0 +reg 61: 0 +reg 62: 0 +reg 63: 0 +write_item 0000110000000000010001100000000000000000000000000000000000000000 +write_item 63: 0 +write_item 62: 0 +write_item 61: 0 +write_item 60: 0 +write_item 59: 1 +write_item 58: 1 +write_item 57: 0 +write_item 56: 0 +write_item 55: 0 +write_item 54: 0 +write_item 53: 0 +write_item 52: 0 +write_item 51: 0 +write_item 50: 0 +write_item 49: 0 +write_item 48: 0 +write_item 47: 0 +write_item 46: 1 +write_item 45: 0 +write_item 44: 0 +write_item 43: 0 +write_item 42: 1 +write_item 41: 1 +write_item 40: 0 +write_item 39: 0 +write_item 38: 0 +write_item 37: 0 +write_item 36: 0 +write_item 35: 0 +write_item 34: 0 +write_item 33: 0 +write_item 32: 0 +write_item 31: 0 +write_item 30: 0 +write_item 29: 0 +write_item 28: 0 +write_item 27: 0 +write_item 26: 0 +write_item 25: 0 +write_item 24: 0 +write_item 23: 0 +write_item 22: 0 +write_item 21: 0 +write_item 20: 0 +write_item 19: 0 +write_item 18: 0 +write_item 17: 0 +write_item 16: 0 +write_item 15: 0 +write_item 14: 0 +write_item 13: 0 +write_item 12: 0 +write_item 11: 0 +write_item 10: 0 +write_item 9: 0 +write_item 8: 0 +write_item 7: 0 +write_item 6: 0 +write_item 5: 0 +write_item 4: 0 +write_item 3: 0 +write_item 2: 0 +write_item 1: 0 +write_item 0: 0 +reg 0: 0 +reg 1: 0 +reg 2: 0 +reg 3: 0 +reg 4: 1 +reg 5: 1 +reg 6: 0 +reg 7: 0 +reg 8: 0 +reg 9: 0 +reg 10: 0 +reg 11: 0 +reg 12: 0 +reg 13: 0 +reg 14: 0 +reg 15: 0 +reg 16: 0 +reg 17: 1 +reg 18: 0 +reg 19: 0 +reg 20: 0 +reg 21: 1 +reg 22: 1 +reg 23: 0 +reg 24: 0 +reg 25: 0 +reg 26: 0 +reg 27: 0 +reg 28: 0 +reg 29: 0 +reg 30: 0 +reg 31: 0 +reg 32: 0 +reg 33: 0 +reg 34: 0 +reg 35: 0 +reg 36: 0 +reg 37: 0 +reg 38: 0 +reg 39: 0 +reg 40: 0 +reg 41: 0 +reg 42: 0 +reg 43: 0 +reg 44: 0 +reg 45: 0 +reg 46: 0 +reg 47: 0 +reg 48: 0 +reg 49: 0 +reg 50: 0 +reg 51: 0 +reg 52: 0 +reg 53: 0 +reg 54: 0 +reg 55: 0 +reg 56: 0 +reg 57: 0 +reg 58: 0 +reg 59: 0 +reg 60: 0 +reg 61: 0 +reg 62: 0 +reg 63: 0 +write_item 0000110000000000010001110000000000000000000000000000000000000001 +write_item 63: 0 +write_item 62: 0 +write_item 61: 0 +write_item 60: 0 +write_item 59: 1 +write_item 58: 1 +write_item 57: 0 +write_item 56: 0 +write_item 55: 0 +write_item 54: 0 +write_item 53: 0 +write_item 52: 0 +write_item 51: 0 +write_item 50: 0 +write_item 49: 0 +write_item 48: 0 +write_item 47: 0 +write_item 46: 1 +write_item 45: 0 +write_item 44: 0 +write_item 43: 0 +write_item 42: 1 +write_item 41: 1 +write_item 40: 1 +write_item 39: 0 +write_item 38: 0 +write_item 37: 0 +write_item 36: 0 +write_item 35: 0 +write_item 34: 0 +write_item 33: 0 +write_item 32: 0 +write_item 31: 0 +write_item 30: 0 +write_item 29: 0 +write_item 28: 0 +write_item 27: 0 +write_item 26: 0 +write_item 25: 0 +write_item 24: 0 +write_item 23: 0 +write_item 22: 0 +write_item 21: 0 +write_item 20: 0 +write_item 19: 0 +write_item 18: 0 +write_item 17: 0 +write_item 16: 0 +write_item 15: 0 +write_item 14: 0 +write_item 13: 0 +write_item 12: 0 +write_item 11: 0 +write_item 10: 0 +write_item 9: 0 +write_item 8: 0 +write_item 7: 0 +write_item 6: 0 +write_item 5: 0 +write_item 4: 0 +write_item 3: 0 +write_item 2: 0 +write_item 1: 0 +write_item 0: 1 +reg 0: 0 +reg 1: 0 +reg 2: 0 +reg 3: 0 +reg 4: 1 +reg 5: 1 +reg 6: 0 +reg 7: 0 +reg 8: 0 +reg 9: 0 +reg 10: 0 +reg 11: 0 +reg 12: 0 +reg 13: 0 +reg 14: 0 +reg 15: 0 +reg 16: 0 +reg 17: 1 +reg 18: 0 +reg 19: 0 +reg 20: 0 +reg 21: 1 +reg 22: 1 +reg 23: 1 +reg 24: 0 +reg 25: 0 +reg 26: 0 +reg 27: 0 +reg 28: 0 +reg 29: 0 +reg 30: 0 +reg 31: 0 +reg 32: 0 +reg 33: 0 +reg 34: 0 +reg 35: 0 +reg 36: 0 +reg 37: 0 +reg 38: 0 +reg 39: 0 +reg 40: 0 +reg 41: 0 +reg 42: 0 +reg 43: 0 +reg 44: 0 +reg 45: 0 +reg 46: 0 +reg 47: 0 +reg 48: 0 +reg 49: 0 +reg 50: 0 +reg 51: 0 +reg 52: 0 +reg 53: 0 +reg 54: 0 +reg 55: 0 +reg 56: 0 +reg 57: 0 +reg 58: 0 +reg 59: 0 +reg 60: 0 +reg 61: 0 +reg 62: 0 +reg 63: 1 +write_item 0000110000000000010010000000000000000000000000000000000000000011 +write_item 63: 0 +write_item 62: 0 +write_item 61: 0 +write_item 60: 0 +write_item 59: 1 +write_item 58: 1 +write_item 57: 0 +write_item 56: 0 +write_item 55: 0 +write_item 54: 0 +write_item 53: 0 +write_item 52: 0 +write_item 51: 0 +write_item 50: 0 +write_item 49: 0 +write_item 48: 0 +write_item 47: 0 +write_item 46: 1 +write_item 45: 0 +write_item 44: 0 +write_item 43: 1 +write_item 42: 0 +write_item 41: 0 +write_item 40: 0 +write_item 39: 0 +write_item 38: 0 +write_item 37: 0 +write_item 36: 0 +write_item 35: 0 +write_item 34: 0 +write_item 33: 0 +write_item 32: 0 +write_item 31: 0 +write_item 30: 0 +write_item 29: 0 +write_item 28: 0 +write_item 27: 0 +write_item 26: 0 +write_item 25: 0 +write_item 24: 0 +write_item 23: 0 +write_item 22: 0 +write_item 21: 0 +write_item 20: 0 +write_item 19: 0 +write_item 18: 0 +write_item 17: 0 +write_item 16: 0 +write_item 15: 0 +write_item 14: 0 +write_item 13: 0 +write_item 12: 0 +write_item 11: 0 +write_item 10: 0 +write_item 9: 0 +write_item 8: 0 +write_item 7: 0 +write_item 6: 0 +write_item 5: 0 +write_item 4: 0 +write_item 3: 0 +write_item 2: 0 +write_item 1: 1 +write_item 0: 1 +reg 0: 0 +reg 1: 0 +reg 2: 0 +reg 3: 0 +reg 4: 1 +reg 5: 1 +reg 6: 0 +reg 7: 0 +reg 8: 0 +reg 9: 0 +reg 10: 0 +reg 11: 0 +reg 12: 0 +reg 13: 0 +reg 14: 0 +reg 15: 0 +reg 16: 0 +reg 17: 1 +reg 18: 0 +reg 19: 0 +reg 20: 1 +reg 21: 0 +reg 22: 0 +reg 23: 0 +reg 24: 0 +reg 25: 0 +reg 26: 0 +reg 27: 0 +reg 28: 0 +reg 29: 0 +reg 30: 0 +reg 31: 0 +reg 32: 0 +reg 33: 0 +reg 34: 0 +reg 35: 0 +reg 36: 0 +reg 37: 0 +reg 38: 0 +reg 39: 0 +reg 40: 0 +reg 41: 0 +reg 42: 0 +reg 43: 0 +reg 44: 0 +reg 45: 0 +reg 46: 0 +reg 47: 0 +reg 48: 0 +reg 49: 0 +reg 50: 0 +reg 51: 0 +reg 52: 0 +reg 53: 0 +reg 54: 0 +reg 55: 0 +reg 56: 0 +reg 57: 0 +reg 58: 0 +reg 59: 0 +reg 60: 0 +reg 61: 0 +reg 62: 1 +reg 63: 1 +Line 0: 0 +Line 1: 0 +Line 2: 0 +Line 3: 0 +Line 4: 0 +Line 5: 1 +Line 6: 0 +Line 7: 0 +Line 8: 0 +Line 9: 0 +Line 10: 0 +Line 11: 0 +Line 12: 0 +Line 13: 0 +Line 14: 0 +Line 15: 0 +Line 16: 0 +Line 17: 0 +Line 18: 0 +Line 19: 0 +Line 20: 0 +Line 21: 0 +Line 22: 0 +Line 23: 0 +Line 24: 0 +Line 25: 0 +Line 26: 0 +Line 27: 0 +Line 28: 0 +Line 29: 0 +Line 30: 0 +Line 31: 0 +Line 32: 0 +Line 33: 0 +Line 34: 0 +Line 35: 0 +Line 36: 0 +Line 37: 0 +Line 38: 0 +Line 39: 0 +Line 40: 0 +Line 41: 0 +Line 42: 1 +Line 43: 0 +Line 44: 0 +Line 45: 0 +Line 46: 0 +Line 47: 0 +Line 48: 0 +Line 49: 0 +Line 50: 0 +Line 51: 0 +Line 52: 0 +Line 53: 0 +Line 54: 0 +Line 55: 1 +Line 56: 1 +Line 57: 0 +Line 58: 1 +Line 59: 1 +Line 60: 0 +Line 61: 1 +Line 62: 1 +Line 63: 1 +Line 64: 0 +Line 65: 1 +Line 66: 1 +Line 67: 0 +Line 68: 0 +Line 69: 1 +Line 70: 1 +Line 71: 0 +Line 72: 0 +Line 73: 1 +Line 74: 1 +Line 75: 0 +Line 76: 0 +Line 77: 1 +Line 78: 1 +Line 79: 0 +Line 80: 0 +Line 81: 1 +Line 82: 1 +Line 83: 0 +Line 84: 0 +Line 85: 1 +Line 86: 0 +Line 87: 0 +Line 88: 0 +Line 89: 0 +Line 90: 1 +Line 91: 1 +Line 92: 0 +Line 93: 1 +Line 94: 1 +Line 95: 1 +Line 96: 0 +Line 97: 0 +Line 98: 0 +Line 99: 0 +Line 100: 0 +Line 101: 1 +Line 102: 0 +Line 103: 0 +Line 104: 1 +Line 105: 0 +Line 106: 0 +Line 107: 0 +Line 108: 0 +Line 109: 0 +Line 110: 0 +Line 111: 1 +Line 112: 1 +Line 113: 0 +Line 114: 1 +Line 115: 0 +Line 116: 0 +Line 117: 0 +Line 118: 0 +Line 119: 0 +Line 120: 0 +Line 121: 0 +Line 122: 1 +Line 123: 0 +Line 124: 0 +Line 125: 0 +Line 126: 1 +Line 127: 1 +Line 128: 0 +Line 129: 0 +Line 130: 0 +Line 131: 0 +Line 132: 0 +Line 133: 1 +Line 134: 0 +Line 135: 0 +Line 136: 0 +Line 137: 0 +Line 138: 0 +Line 139: 0 +Line 140: 0 +Line 141: 0 +Line 142: 0 +Line 143: 1 +Line 144: 1 +Line 145: 0 +Line 146: 1 +Line 147: 0 +Line 148: 1 +Line 149: 0 +Line 150: 1 +Line 151: 0 +Line 152: 0 +Line 153: 0 +Line 154: 1 +Line 155: 0 +Line 156: 0 +Line 157: 0 +Line 158: 1 +Line 159: 1 +Line 160: 0 +Line 161: 1 +Line 162: 1 +Line 163: 1 +Line 164: 1 +Line 165: 1 +Line 166: 1 +Line 167: 1 +Line 168: 1 +Line 169: 1 +Line 170: 1 +Line 171: 1 +Line 172: 1 +Line 173: 1 +Line 174: 1 +Line 175: 1 +Line 176: 0 +Line 177: 0 +Line 178: 0 +Line 179: 0 +Line 180: 0 +Line 181: 1 +Line 182: 0 +Line 183: 1 +Line 184: 0 +Line 185: 0 +Line 186: 1 +Line 187: 1 +Line 188: 0 +Line 189: 1 +Line 190: 1 +Line 191: 1 +Line 192: 0 +Line 193: 0 +Line 194: 0 +Line 195: 0 +Line 196: 0 +Line 197: 1 +Line 198: 1 +Line 199: 0 +Line 200: 1 +Line 201: 0 +Line 202: 1 +Line 203: 0 +Line 204: 0 +Line 205: 0 +Line 206: 0 +Line 207: 1 +Line 208: 1 +Line 209: 0 +Line 210: 1 +Line 211: 0 +Line 212: 1 +Line 213: 1 +Line 214: 0 +Line 215: 0 +Line 216: 0 +Line 217: 0 +Line 218: 1 +Line 219: 0 +Line 220: 0 +Line 221: 0 +Line 222: 1 +Line 223: 1 +Line 224: 0 +Line 225: 0 +Line 226: 1 +Line 227: 1 +Line 228: 1 +Line 229: 1 +Line 230: 1 +Line 231: 1 +Line 232: 1 +Line 233: 1 +Line 234: 1 +Line 235: 1 +Line 236: 1 +Line 237: 1 +Line 238: 1 +Line 239: 1 +Line 240: 0 +Line 241: 0 +Line 242: 0 +Line 243: 0 +Line 244: 0 +Line 245: 1 +Line 246: 0 +Line 247: 1 +Line 248: 0 +Line 249: 0 +Line 250: 1 +Line 251: 1 +Line 252: 0 +Line 253: 1 +Line 254: 1 +Line 255: 1 +Line 256: 0 +Line 257: 0 +Line 258: 0 +Line 259: 0 +Line 260: 0 +Line 261: 1 +Line 262: 1 +Line 263: 0 +Line 264: 1 +Line 265: 0 +Line 266: 1 +Line 267: 0 +Line 268: 0 +Line 269: 0 +Line 270: 0 +Line 271: 1 +Line 272: 1 +Line 273: 0 +Line 274: 1 +Line 275: 0 +Line 276: 1 +Line 277: 1 +Line 278: 1 +Line 279: 0 +Line 280: 0 +Line 281: 0 +Line 282: 1 +Line 283: 0 +Line 284: 0 +Line 285: 0 +Line 286: 1 +Line 287: 1 +Line 288: 0 +Line 289: 0 +Line 290: 0 +Line 291: 0 +Line 292: 0 +Line 293: 0 +Line 294: 0 +Line 295: 1 +Line 296: 0 +Line 297: 1 +Line 298: 1 +Line 299: 1 +Line 300: 0 +Line 301: 0 +Line 302: 0 +Line 303: 0 +Line 304: 0 +Line 305: 0 +Line 306: 0 +Line 307: 0 +Line 308: 0 +Line 309: 0 +Line 310: 0 +Line 311: 0 +Line 312: 0 +Line 313: 0 +Line 314: 0 +Line 315: 0 +Line 316: 1 +Line 317: 0 +Line 318: 1 +Line 319: 1 +Line 320: 0 +Line 321: 0 +Line 322: 0 +Line 323: 0 +Line 324: 0 +Line 325: 1 +Line 326: 1 +Line 327: 0 +Line 328: 0 +Line 329: 0 +Line 330: 0 +Line 331: 0 +Line 332: 0 +Line 333: 0 +Line 334: 0 +Line 335: 1 +Line 336: 1 +Line 337: 0 +Line 338: 1 +Line 339: 0 +Line 340: 1 +Line 341: 0 +Line 342: 1 +Line 343: 0 +Line 344: 0 +Line 345: 0 +Line 346: 1 +Line 347: 0 +Line 348: 0 +Line 349: 0 +Line 350: 1 +Line 351: 1 +Line 352: 0 +Line 353: 0 +Line 354: 0 +Line 355: 0 +Line 356: 0 +Line 357: 0 +Line 358: 0 +Line 359: 0 +Line 360: 0 +Line 361: 0 +Line 362: 0 +Line 363: 1 +Line 364: 0 +Line 365: 0 +Line 366: 0 +Line 367: 0 +Line 368: 0 +Line 369: 0 +Line 370: 0 +Line 371: 0 +Line 372: 0 +Line 373: 0 +Line 374: 1 +Line 375: 0 +Line 376: 0 +Line 377: 0 +Line 378: 0 +Line 379: 1 +Line 380: 0 +Line 381: 0 +Line 382: 1 +Line 383: 1 +Line 384: 0 +Line 385: 0 +Line 386: 0 +Line 387: 0 +Line 388: 0 +Line 389: 1 +Line 390: 0 +Line 391: 0 +Line 392: 0 +Line 393: 1 +Line 394: 0 +Line 395: 0 +Line 396: 0 +Line 397: 0 +Line 398: 0 +Line 399: 1 +Line 400: 1 +Line 401: 0 +Line 402: 1 +Line 403: 0 +Line 404: 1 +Line 405: 0 +Line 406: 0 +Line 407: 0 +Line 408: 0 +Line 409: 0 +Line 410: 1 +Line 411: 0 +Line 412: 0 +Line 413: 0 +Line 414: 1 +Line 415: 1 +Line 416: 0 +Line 417: 0 +Line 418: 0 +Line 419: 0 +Line 420: 0 +Line 421: 0 +Line 422: 0 +Line 423: 0 +Line 424: 0 +Line 425: 0 +Line 426: 0 +Line 427: 0 +Line 428: 1 +Line 429: 0 +Line 430: 0 +Line 431: 0 +Line 432: 0 +Line 433: 0 +Line 434: 1 +Line 435: 0 +Line 436: 0 +Line 437: 1 +Line 438: 0 +Line 439: 0 +Line 440: 1 +Line 441: 0 +Line 442: 1 +Line 443: 1 +Line 444: 0 +Line 445: 1 +Line 446: 1 +Line 447: 1 +Line 448: 0 +Line 449: 0 +Line 450: 0 +Line 451: 0 +Line 452: 0 +Line 453: 0 +Line 454: 0 +Line 455: 0 +Line 456: 0 +Line 457: 1 +Line 458: 0 +Line 459: 1 +Line 460: 0 +Line 461: 0 +Line 462: 0 +Line 463: 0 +Line 464: 0 +Line 465: 0 +Line 466: 0 +Line 467: 0 +Line 468: 0 +Line 469: 0 +Line 470: 0 +Line 471: 0 +Line 472: 0 +Line 473: 0 +Line 474: 0 +Line 475: 0 +Line 476: 1 +Line 477: 0 +Line 478: 1 +Line 479: 1 +Line 480: 0 +Line 481: 0 +Line 482: 0 +Line 483: 0 +Line 484: 0 +Line 485: 0 +Line 486: 0 +Line 487: 0 +Line 488: 0 +Line 489: 0 +Line 490: 0 +Line 491: 0 +Line 492: 0 +Line 493: 0 +Line 494: 0 +Line 495: 0 +Line 496: 0 +Line 497: 0 +Line 498: 0 +Line 499: 0 +Line 500: 0 +Line 501: 0 +Line 502: 0 +Line 503: 0 +Line 504: 0 +Line 505: 0 +Line 506: 0 +Line 507: 1 +Line 508: 0 +Line 509: 0 +Line 510: 1 +Line 511: 1 +Line 512: 0 +Line 513: 0 +Line 514: 0 +Line 515: 0 +Line 516: 0 +Line 517: 0 +Line 518: 0 +Line 519: 0 +Line 520: 0 +Line 521: 0 +Line 522: 0 +Line 523: 0 +Line 524: 1 +Line 525: 0 +Line 526: 0 +Line 527: 0 +Line 528: 0 +Line 529: 0 +Line 530: 0 +Line 531: 0 +Line 532: 0 +Line 533: 1 +Line 534: 0 +Line 535: 0 +Line 536: 1 +Line 537: 0 +Line 538: 1 +Line 539: 1 +Line 540: 0 +Line 541: 1 +Line 542: 1 +Line 543: 1 +Line 544: 0 +Line 545: 0 +Line 546: 0 +Line 547: 0 +Line 548: 0 +Line 549: 1 +Line 550: 0 +Line 551: 1 +Line 552: 1 +Line 553: 0 +Line 554: 1 +Line 555: 1 +Line 556: 0 +Line 557: 0 +Line 558: 0 +Line 559: 0 +Line 560: 0 +Line 561: 0 +Line 562: 0 +Line 563: 0 +Line 564: 0 +Line 565: 0 +Line 566: 0 +Line 567: 0 +Line 568: 0 +Line 569: 0 +Line 570: 0 +Line 571: 0 +Line 572: 1 +Line 573: 0 +Line 574: 1 +Line 575: 1 +Line 576: 0 +Line 577: 0 +Line 578: 0 +Line 579: 0 +Line 580: 0 +Line 581: 0 +Line 582: 0 +Line 583: 0 +Line 584: 0 +Line 585: 1 +Line 586: 1 +Line 587: 0 +Line 588: 0 +Line 589: 1 +Line 590: 0 +Line 591: 0 +Line 592: 1 +Line 593: 0 +Line 594: 1 +Line 595: 0 +Line 596: 0 +Line 597: 0 +Line 598: 0 +Line 599: 0 +Line 600: 0 +Line 601: 0 +Line 602: 0 +Line 603: 0 +Line 604: 1 +Line 605: 0 +Line 606: 1 +Line 607: 1 +Line 608: 0 +Line 609: 0 +Line 610: 0 +Line 611: 0 +Line 612: 0 +Line 613: 1 +Line 614: 1 +Line 615: 0 +Line 616: 0 +Line 617: 1 +Line 618: 0 +Line 619: 0 +Line 620: 0 +Line 621: 0 +Line 622: 0 +Line 623: 0 +Line 624: 0 +Line 625: 0 +Line 626: 0 +Line 627: 0 +Line 628: 0 +Line 629: 1 +Line 630: 0 +Line 631: 0 +Line 632: 0 +Line 633: 0 +Line 634: 0 +Line 635: 1 +Line 636: 0 +Line 637: 0 +Line 638: 1 +Line 639: 1 +Line 640: 1 +Line 641: 1 +Line 642: 1 +Line 643: 1 +Line 644: 1 +Line 645: 0 +Line 646: 1 +Line 647: 0 +Line 648: 0 +Line 649: 1 +Line 650: 1 +Line 651: 1 +Line 652: 0 +Line 653: 1 +Line 654: 0 +Line 655: 0 +Line 656: 0 +Line 657: 0 +Line 658: 0 +Line 659: 0 +Line 660: 0 +Line 661: 0 +Line 662: 1 +Line 663: 1 +Line 664: 1 +Line 665: 0 +Line 666: 0 +Line 667: 0 +Line 668: 1 +Line 669: 0 +Line 670: 1 +Line 671: 1 +Line 672: 0 +Line 673: 0 +Line 674: 0 +Line 675: 0 +Line 676: 0 +Line 677: 0 +Line 678: 0 +Line 679: 0 +Line 680: 0 +Line 681: 0 +Line 682: 0 +Line 683: 0 +Line 684: 0 +Line 685: 0 +Line 686: 0 +Line 687: 0 +Line 688: 0 +Line 689: 0 +Line 690: 0 +Line 691: 0 +Line 692: 0 +Line 693: 0 +Line 694: 0 +Line 695: 0 +Line 696: 0 +Line 697: 0 +Line 698: 1 +Line 699: 0 +Line 700: 1 +Line 701: 0 +Line 702: 1 +Line 703: 1 +Send MCU_INSTR_FILE +Line 0: 0 +Line 1: 0 +Line 2: 0 +Line 3: 0 +Line 4: 1 +Line 5: 0 +Line 6: 0 +Line 7: 0 +Line 8: 0 +Line 9: 0 +Line 10: 0 +Line 11: 0 +Line 12: 0 +Line 13: 0 +Line 14: 0 +Line 15: 0 +Line 16: 0 +Line 17: 0 +Line 18: 0 +Line 19: 0 +Line 20: 0 +Line 21: 0 +Line 22: 0 +Line 23: 0 +Line 24: 0 +Line 25: 0 +Line 26: 0 +Line 27: 0 +Line 28: 0 +Line 29: 0 +Line 30: 0 +Line 31: 0 +Line 32: 0 +Line 33: 0 +Line 34: 0 +Line 35: 0 +Line 36: 0 +Line 37: 0 +Line 38: 0 +Line 39: 0 +Line 40: 0 +Line 41: 0 +Line 42: 0 +Line 43: 0 +Line 44: 0 +Line 45: 0 +Line 46: 0 +Line 47: 0 +Line 48: 0 +Line 49: 0 +Line 50: 0 +Line 51: 0 +Line 52: 0 +Line 53: 0 +Line 54: 0 +Line 55: 0 +Line 56: 0 +Line 57: 0 +Line 58: 0 +Line 59: 0 +Line 60: 0 +Line 61: 0 +Line 62: 1 +Line 63: 0 +Line 64: 0 +Line 65: 0 +Line 66: 0 +Line 67: 1 +Line 68: 0 +Line 69: 1 +Line 70: 0 +Line 71: 0 +Line 72: 0 +Line 73: 1 +Line 74: 1 +Line 75: 1 +Line 76: 1 +Line 77: 0 +Line 78: 1 +Line 79: 0 +Line 80: 1 +Line 81: 1 +Line 82: 1 +Line 83: 0 +Line 84: 0 +Line 85: 0 +Line 86: 0 +Line 87: 1 +Line 88: 0 +Line 89: 1 +Line 90: 0 +Line 91: 0 +Line 92: 0 +Line 93: 1 +Line 94: 1 +Line 95: 1 +Line 96: 0 +Line 97: 0 +Line 98: 0 +Line 99: 0 +Line 100: 1 +Line 101: 0 +Line 102: 1 +Line 103: 0 +Line 104: 0 +Line 105: 0 +Line 106: 1 +Line 107: 1 +Line 108: 1 +Line 109: 1 +Line 110: 0 +Line 111: 1 +Line 112: 0 +Line 113: 1 +Line 114: 1 +Line 115: 1 +Line 116: 0 +Line 117: 0 +Line 118: 0 +Line 119: 0 +Line 120: 1 +Line 121: 0 +Line 122: 1 +Line 123: 0 +Line 124: 0 +Line 125: 0 +Line 126: 1 +Line 127: 1 +Line 128: 0 +Line 129: 0 +Line 130: 0 +Line 131: 0 +Line 132: 0 +Line 133: 0 +Line 134: 0 +Line 135: 0 +Line 136: 0 +Line 137: 0 +Line 138: 0 +Line 139: 0 +Line 140: 0 +Line 141: 0 +Line 142: 0 +Line 143: 0 +Line 144: 0 +Line 145: 0 +Line 146: 0 +Line 147: 0 +Line 148: 0 +Line 149: 0 +Line 150: 0 +Line 151: 0 +Line 152: 0 +Line 153: 0 +Line 154: 0 +Line 155: 0 +Line 156: 1 +Line 157: 0 +Line 158: 0 +Line 159: 1 +Line 160: 0 +Line 161: 0 +Line 162: 0 +Line 163: 1 +Line 164: 1 +Line 165: 0 +Line 166: 0 +Line 167: 1 +Line 168: 1 +Line 169: 0 +Line 170: 0 +Line 171: 1 +Line 172: 1 +Line 173: 0 +Line 174: 0 +Line 175: 1 +Line 176: 0 +Line 177: 0 +Line 178: 0 +Line 179: 0 +Line 180: 0 +Line 181: 0 +Line 182: 0 +Line 183: 0 +Line 184: 0 +Line 185: 0 +Line 186: 0 +Line 187: 0 +Line 188: 0 +Line 189: 0 +Line 190: 0 +Line 191: 0 +Line 192: 0 +Line 193: 0 +Line 194: 0 +Line 195: 0 +Line 196: 1 +Line 197: 1 +Line 198: 0 +Line 199: 0 +Line 200: 1 +Line 201: 1 +Line 202: 0 +Line 203: 0 +Line 204: 1 +Line 205: 1 +Line 206: 0 +Line 207: 0 +Line 208: 0 +Line 209: 0 +Line 210: 0 +Line 211: 0 +Line 212: 0 +Line 213: 0 +Line 214: 0 +Line 215: 0 +Line 216: 0 +Line 217: 0 +Line 218: 0 +Line 219: 0 +Line 220: 0 +Line 221: 0 +Line 222: 0 +Line 223: 0 +Line 224: 0 +Line 225: 0 +Line 226: 0 +Line 227: 0 +Line 228: 0 +Line 229: 0 +Line 230: 0 +Line 231: 0 +Line 232: 0 +Line 233: 0 +Line 234: 0 +Line 235: 0 +Line 236: 0 +Line 237: 0 +Line 238: 0 +Line 239: 0 +Line 240: 0 +Line 241: 0 +Line 242: 0 +Line 243: 0 +Line 244: 0 +Line 245: 0 +Line 246: 0 +Line 247: 0 +Line 248: 0 +Line 249: 0 +Line 250: 0 +Line 251: 0 +Line 252: 1 +Line 253: 0 +Line 254: 0 +Line 255: 1 +Line 256: 0 +Line 257: 0 +Line 258: 0 +Line 259: 0 +Line 260: 0 +Line 261: 0 +Line 262: 0 +Line 263: 0 +Line 264: 0 +Line 265: 0 +Line 266: 0 +Line 267: 0 +Line 268: 0 +Line 269: 0 +Line 270: 0 +Line 271: 0 +Line 272: 0 +Line 273: 0 +Line 274: 0 +Line 275: 0 +Line 276: 0 +Line 277: 0 +Line 278: 0 +Line 279: 0 +Line 280: 0 +Line 281: 0 +Line 282: 0 +Line 283: 0 +Line 284: 0 +Line 285: 0 +Line 286: 0 +Line 287: 0 +Line 288: 0 +Line 289: 0 +Line 290: 0 +Line 291: 0 +Line 292: 0 +Line 293: 0 +Line 294: 0 +Line 295: 0 +Line 296: 0 +Line 297: 0 +Line 298: 0 +Line 299: 0 +Line 300: 0 +Line 301: 0 +Line 302: 0 +Line 303: 0 +Line 304: 0 +Line 305: 0 +Line 306: 0 +Line 307: 0 +Line 308: 0 +Line 309: 0 +Line 310: 0 +Line 311: 0 +Line 312: 0 +Line 313: 0 +Line 314: 0 +Line 315: 0 +Line 316: 0 +Line 317: 0 +Line 318: 0 +Line 319: 1 +Line 320: 0 +Line 321: 0 +Line 322: 0 +Line 323: 0 +Line 324: 0 +Line 325: 0 +Line 326: 0 +Line 327: 0 +Line 328: 0 +Line 329: 0 +Line 330: 0 +Line 331: 0 +Line 332: 0 +Line 333: 0 +Line 334: 0 +Line 335: 0 +Line 336: 0 +Line 337: 0 +Line 338: 0 +Line 339: 0 +Line 340: 0 +Line 341: 0 +Line 342: 0 +Line 343: 0 +Line 344: 0 +Line 345: 1 +Line 346: 1 +Line 347: 0 +Line 348: 0 +Line 349: 1 +Line 350: 0 +Line 351: 0 +Send MCU_INSTR_FILE +Line 0: 0 +Line 1: 0 +Line 2: 0 +Line 3: 1 +Line 4: 0 +Line 5: 0 +Line 6: 0 +Line 7: 0 +Line 8: 0 +Line 9: 0 +Line 10: 0 +Line 11: 0 +Line 12: 0 +Line 13: 0 +Line 14: 0 +Line 15: 0 +Line 16: 0 +Line 17: 0 +Line 18: 0 +Line 19: 0 +Line 20: 0 +Line 21: 0 +Line 22: 0 +Line 23: 0 +Line 24: 0 +Line 25: 0 +Line 26: 0 +Line 27: 0 +Line 28: 0 +Line 29: 0 +Line 30: 0 +Line 31: 0 +Line 32: 0 +Line 33: 0 +Line 34: 0 +Line 35: 0 +Line 36: 0 +Line 37: 0 +Line 38: 0 +Line 39: 0 +Line 40: 0 +Line 41: 0 +Line 42: 0 +Line 43: 0 +Line 44: 0 +Line 45: 0 +Line 46: 0 +Line 47: 0 +Line 48: 0 +Line 49: 0 +Line 50: 0 +Line 51: 0 +Line 52: 0 +Line 53: 0 +Line 54: 0 +Line 55: 0 +Line 56: 0 +Line 57: 0 +Line 58: 0 +Line 59: 1 +Line 60: 0 +Line 61: 1 +Line 62: 0 +Line 63: 0 +Line 64: 0 +Line 65: 0 +Line 66: 0 +Line 67: 0 +Line 68: 0 +Line 69: 0 +Line 70: 0 +Line 71: 0 +Line 72: 0 +Line 73: 1 +Line 74: 0 +Line 75: 1 +Line 76: 0 +Line 77: 0 +Line 78: 0 +Line 79: 0 +Line 80: 0 +Line 81: 0 +Line 82: 0 +Line 83: 0 +Line 84: 0 +Line 85: 0 +Line 86: 0 +Line 87: 0 +Line 88: 0 +Line 89: 0 +Line 90: 0 +Line 91: 1 +Line 92: 1 +Line 93: 0 +Line 94: 0 +Line 95: 1 +Line 96: 0 +Line 97: 0 +Line 98: 0 +Line 99: 0 +Line 100: 0 +Line 101: 0 +Line 102: 0 +Line 103: 0 +Line 104: 1 +Line 105: 0 +Line 106: 1 +Line 107: 1 +Line 108: 0 +Line 109: 1 +Line 110: 0 +Line 111: 0 +Line 112: 0 +Line 113: 0 +Line 114: 0 +Line 115: 0 +Line 116: 0 +Line 117: 0 +Line 118: 0 +Line 119: 0 +Line 120: 0 +Line 121: 0 +Line 122: 1 +Line 123: 1 +Line 124: 0 +Line 125: 0 +Line 126: 1 +Line 127: 0 +Line 128: 0 +Line 129: 0 +Line 130: 0 +Line 131: 0 +Line 132: 0 +Line 133: 0 +Line 134: 0 +Line 135: 1 +Line 136: 0 +Line 137: 1 +Line 138: 1 +Line 139: 1 +Line 140: 1 +Line 141: 1 +Line 142: 0 +Line 143: 0 +Line 144: 0 +Line 145: 0 +Line 146: 0 +Line 147: 0 +Line 148: 0 +Line 149: 0 +Line 150: 0 +Line 151: 0 +Line 152: 0 +Line 153: 0 +Line 154: 1 +Line 155: 1 +Line 156: 0 +Line 157: 0 +Line 158: 1 +Line 159: 0 +Line 160: 0 +Line 161: 0 +Line 162: 0 +Line 163: 0 +Line 164: 0 +Line 165: 0 +Line 166: 1 +Line 167: 0 +Line 168: 0 +Line 169: 1 +Line 170: 0 +Line 171: 0 +Line 172: 0 +Line 173: 1 +Line 174: 0 +Line 175: 0 +Line 176: 0 +Line 177: 0 +Line 178: 0 +Line 179: 0 +Line 180: 0 +Line 181: 0 +Line 182: 0 +Line 183: 0 +Line 184: 0 +Line 185: 0 +Line 186: 0 +Line 187: 1 +Line 188: 1 +Line 189: 0 +Line 190: 0 +Line 191: 1 +Line 192: 0 +Line 193: 0 +Line 194: 0 +Line 195: 0 +Line 196: 0 +Line 197: 0 +Line 198: 1 +Line 199: 0 +Line 200: 1 +Line 201: 0 +Line 202: 1 +Line 203: 0 +Line 204: 1 +Line 205: 0 +Line 206: 0 +Line 207: 0 +Line 208: 0 +Line 209: 0 +Line 210: 0 +Line 211: 0 +Line 212: 0 +Line 213: 0 +Line 214: 0 +Line 215: 0 +Line 216: 1 +Line 217: 0 +Line 218: 1 +Line 219: 0 +Line 220: 1 +Line 221: 1 +Line 222: 1 +Line 223: 1 +Line 224: 0 +Line 225: 0 +Line 226: 0 +Line 227: 0 +Line 228: 0 +Line 229: 1 +Line 230: 0 +Line 231: 1 +Line 232: 0 +Line 233: 1 +Line 234: 1 +Line 235: 0 +Line 236: 0 +Line 237: 1 +Line 238: 0 +Line 239: 0 +Line 240: 0 +Line 241: 0 +Line 242: 0 +Line 243: 0 +Line 244: 0 +Line 245: 0 +Line 246: 0 +Line 247: 0 +Line 248: 0 +Line 249: 0 +Line 250: 0 +Line 251: 0 +Line 252: 0 +Line 253: 0 +Line 254: 0 +Line 255: 1 +Line 256: 0 +Line 257: 0 +Line 258: 0 +Line 259: 0 +Line 260: 0 +Line 261: 1 +Line 262: 0 +Line 263: 1 +Line 264: 0 +Line 265: 1 +Line 266: 1 +Line 267: 0 +Line 268: 1 +Line 269: 0 +Line 270: 0 +Line 271: 0 +Line 272: 0 +Line 273: 0 +Line 274: 0 +Line 275: 0 +Line 276: 0 +Line 277: 0 +Line 278: 0 +Line 279: 0 +Line 280: 0 +Line 281: 0 +Line 282: 0 +Line 283: 0 +Line 284: 0 +Line 285: 0 +Line 286: 0 +Line 287: 1 +Line 288: 0 +Line 289: 0 +Line 290: 0 +Line 291: 0 +Line 292: 0 +Line 293: 1 +Line 294: 0 +Line 295: 1 +Line 296: 0 +Line 297: 1 +Line 298: 1 +Line 299: 0 +Line 300: 1 +Line 301: 1 +Line 302: 0 +Line 303: 0 +Line 304: 0 +Line 305: 0 +Line 306: 0 +Line 307: 0 +Line 308: 0 +Line 309: 0 +Line 310: 0 +Line 311: 0 +Line 312: 0 +Line 313: 0 +Line 314: 1 +Line 315: 0 +Line 316: 1 +Line 317: 0 +Line 318: 0 +Line 319: 0 +Line 320: 0 +Line 321: 0 +Line 322: 0 +Line 323: 0 +Line 324: 0 +Line 325: 1 +Line 326: 1 +Line 327: 0 +Line 328: 0 +Line 329: 0 +Line 330: 0 +Line 331: 0 +Line 332: 1 +Line 333: 1 +Line 334: 0 +Line 335: 0 +Line 336: 0 +Line 337: 0 +Line 338: 0 +Line 339: 0 +Line 340: 0 +Line 341: 0 +Line 342: 0 +Line 343: 0 +Line 344: 0 +Line 345: 0 +Line 346: 0 +Line 347: 0 +Line 348: 1 +Line 349: 0 +Line 350: 1 +Line 351: 0 +Line 352: 0 +Line 353: 0 +Line 354: 0 +Line 355: 0 +Line 356: 0 +Line 357: 1 +Line 358: 1 +Line 359: 0 +Line 360: 0 +Line 361: 0 +Line 362: 1 +Line 363: 1 +Line 364: 0 +Line 365: 1 +Line 366: 0 +Line 367: 0 +Line 368: 0 +Line 369: 0 +Line 370: 0 +Line 371: 0 +Line 372: 0 +Line 373: 0 +Line 374: 0 +Line 375: 0 +Line 376: 0 +Line 377: 0 +Line 378: 0 +Line 379: 0 +Line 380: 1 +Line 381: 0 +Line 382: 0 +Line 383: 0 +Line 384: 0 +Line 385: 0 +Line 386: 0 +Line 387: 0 +Line 388: 0 +Line 389: 1 +Line 390: 1 +Line 391: 0 +Line 392: 0 +Line 393: 1 +Line 394: 0 +Line 395: 1 +Line 396: 0 +Line 397: 1 +Line 398: 0 +Line 399: 0 +Line 400: 0 +Line 401: 0 +Line 402: 0 +Line 403: 0 +Line 404: 0 +Line 405: 0 +Line 406: 0 +Line 407: 0 +Line 408: 0 +Line 409: 0 +Line 410: 0 +Line 411: 0 +Line 412: 1 +Line 413: 0 +Line 414: 0 +Line 415: 0 +Send ENVE_ID_FILE +Line 0: 0 +Line 1: 0 +Line 2: 0 +Line 3: 1 +Line 4: 0 +Line 5: 1 +Line 6: 0 +Line 7: 0 +Line 8: 0 +Line 9: 0 +Line 10: 0 +Line 11: 0 +Line 12: 0 +Line 13: 0 +Line 14: 0 +Line 15: 0 +Line 16: 0 +Line 17: 0 +Line 18: 0 +Line 19: 0 +Line 20: 0 +Line 21: 0 +Line 22: 0 +Line 23: 0 +Line 24: 0 +Line 25: 0 +Line 26: 0 +Line 27: 0 +Line 28: 0 +Line 29: 0 +Line 30: 0 +Line 31: 0 +Line 32: 0 +Line 33: 0 +Line 34: 0 +Line 35: 0 +Line 36: 0 +Line 37: 0 +Line 38: 0 +Line 39: 0 +Line 40: 0 +Line 41: 0 +Line 42: 0 +Line 43: 0 +Line 44: 0 +Line 45: 0 +Line 46: 0 +Line 47: 0 +Line 48: 0 +Line 49: 0 +Line 50: 0 +Line 51: 0 +Line 52: 0 +Line 53: 0 +Line 54: 0 +Line 55: 0 +Line 56: 0 +Line 57: 0 +Line 58: 0 +Line 59: 0 +Line 60: 0 +Line 61: 0 +Line 62: 0 +Line 63: 0 +Line 64: 0 +Line 65: 0 +Line 66: 0 +Line 67: 0 +Line 68: 0 +Line 69: 0 +Line 70: 0 +Line 71: 1 +Line 72: 1 +Line 73: 1 +Line 74: 1 +Line 75: 0 +Line 76: 0 +Line 77: 1 +Line 78: 1 +Line 79: 1 +Line 80: 0 +Line 81: 0 +Line 82: 0 +Line 83: 0 +Line 84: 0 +Line 85: 1 +Line 86: 0 +Line 87: 1 +Line 88: 0 +Line 89: 0 +Line 90: 0 +Line 91: 0 +Line 92: 1 +Line 93: 1 +Line 94: 1 +Line 95: 0 +Line 96: 0 +Line 97: 0 +Line 98: 0 +Line 99: 0 +Line 100: 0 +Line 101: 1 +Line 102: 1 +Line 103: 1 +Line 104: 0 +Line 105: 1 +Line 106: 1 +Line 107: 0 +Line 108: 1 +Line 109: 0 +Line 110: 0 +Line 111: 1 +Line 112: 0 +Line 113: 0 +Line 114: 0 +Line 115: 0 +Line 116: 1 +Line 117: 0 +Line 118: 0 +Line 119: 1 +Line 120: 1 +Line 121: 0 +Line 122: 0 +Line 123: 1 +Line 124: 0 +Line 125: 0 +Line 126: 0 +Line 127: 1 +Line 128: 0 +Line 129: 0 +Line 130: 0 +Line 131: 0 +Line 132: 1 +Line 133: 1 +Line 134: 1 +Line 135: 1 +Line 136: 1 +Line 137: 1 +Line 138: 1 +Line 139: 0 +Line 140: 1 +Line 141: 1 +Line 142: 0 +Line 143: 1 +Line 144: 0 +Line 145: 0 +Line 146: 0 +Line 147: 0 +Line 148: 1 +Line 149: 1 +Line 150: 0 +Line 151: 1 +Line 152: 0 +Line 153: 0 +Line 154: 0 +Line 155: 0 +Line 156: 1 +Line 157: 0 +Line 158: 1 +Line 159: 0 +Line 160: 0 +Line 161: 0 +Line 162: 0 +Line 163: 1 +Line 164: 1 +Line 165: 0 +Line 166: 1 +Line 167: 0 +Line 168: 1 +Line 169: 0 +Line 170: 0 +Line 171: 0 +Line 172: 0 +Line 173: 1 +Line 174: 1 +Line 175: 0 +Line 176: 0 +Line 177: 0 +Line 178: 0 +Line 179: 0 +Line 180: 1 +Line 181: 1 +Line 182: 1 +Line 183: 1 +Line 184: 0 +Line 185: 0 +Line 186: 0 +Line 187: 1 +Line 188: 1 +Line 189: 0 +Line 190: 1 +Line 191: 0 +Line 192: 0 +Line 193: 0 +Line 194: 1 +Line 195: 0 +Line 196: 0 +Line 197: 1 +Line 198: 1 +Line 199: 0 +Line 200: 0 +Line 201: 0 +Line 202: 0 +Line 203: 0 +Line 204: 1 +Line 205: 1 +Line 206: 1 +Line 207: 1 +Line 208: 0 +Line 209: 0 +Line 210: 0 +Line 211: 0 +Line 212: 1 +Line 213: 1 +Line 214: 1 +Line 215: 1 +Line 216: 1 +Line 217: 0 +Line 218: 0 +Line 219: 0 +Line 220: 0 +Line 221: 1 +Line 222: 1 +Line 223: 0 +Line 224: 0 +Line 225: 0 +Line 226: 1 +Line 227: 1 +Line 228: 0 +Line 229: 0 +Line 230: 0 +Line 231: 1 +Line 232: 0 +Line 233: 1 +Line 234: 0 +Line 235: 0 +Line 236: 0 +Line 237: 1 +Line 238: 1 +Line 239: 1 +Line 240: 0 +Line 241: 0 +Line 242: 0 +Line 243: 0 +Line 244: 1 +Line 245: 1 +Line 246: 1 +Line 247: 0 +Line 248: 0 +Line 249: 1 +Line 250: 0 +Line 251: 0 +Line 252: 0 +Line 253: 1 +Line 254: 0 +Line 255: 0 +Line 256: 0 +Line 257: 0 +Line 258: 1 +Line 259: 1 +Line 260: 1 +Line 261: 0 +Line 262: 1 +Line 263: 0 +Line 264: 1 +Line 265: 1 +Line 266: 1 +Line 267: 1 +Line 268: 0 +Line 269: 1 +Line 270: 1 +Line 271: 1 +Line 272: 0 +Line 273: 0 +Line 274: 0 +Line 275: 0 +Line 276: 1 +Line 277: 0 +Line 278: 1 +Line 279: 1 +Line 280: 0 +Line 281: 1 +Line 282: 1 +Line 283: 1 +Line 284: 0 +Line 285: 1 +Line 286: 1 +Line 287: 0 +Line 288: 0 +Line 289: 1 +Line 290: 0 +Line 291: 0 +Line 292: 0 +Line 293: 0 +Line 294: 1 +Line 295: 0 +Line 296: 0 +Line 297: 0 +Line 298: 0 +Line 299: 1 +Line 300: 0 +Line 301: 0 +Line 302: 1 +Line 303: 1 +Line 304: 0 +Line 305: 0 +Line 306: 0 +Line 307: 0 +Line 308: 0 +Line 309: 1 +Line 310: 1 +Line 311: 1 +Line 312: 0 +Line 313: 1 +Line 314: 1 +Line 315: 0 +Line 316: 1 +Line 317: 0 +Line 318: 1 +Line 319: 0 +Line 320: 0 +Line 321: 1 +Line 322: 0 +Line 323: 0 +Line 324: 0 +Line 325: 1 +Line 326: 0 +Line 327: 1 +Line 328: 1 +Line 329: 1 +Line 330: 0 +Line 331: 1 +Line 332: 0 +Line 333: 1 +Line 334: 0 +Line 335: 1 +Line 336: 0 +Line 337: 0 +Line 338: 0 +Line 339: 0 +Line 340: 0 +Line 341: 0 +Line 342: 1 +Line 343: 0 +Line 344: 1 +Line 345: 0 +Line 346: 0 +Line 347: 1 +Line 348: 0 +Line 349: 0 +Line 350: 0 +Line 351: 0 +Line 352: 0 +Line 353: 1 +Line 354: 0 +Line 355: 0 +Line 356: 0 +Line 357: 1 +Line 358: 0 +Line 359: 1 +Line 360: 1 +Line 361: 1 +Line 362: 0 +Line 363: 1 +Line 364: 0 +Line 365: 1 +Line 366: 0 +Line 367: 1 +Line 368: 1 +Line 369: 1 +Line 370: 1 +Line 371: 1 +Line 372: 1 +Line 373: 1 +Line 374: 0 +Line 375: 1 +Line 376: 0 +Line 377: 1 +Line 378: 1 +Line 379: 1 +Line 380: 0 +Line 381: 0 +Line 382: 0 +Line 383: 0 +Line 384: 0 +Line 385: 1 +Line 386: 0 +Line 387: 0 +Line 388: 0 +Line 389: 0 +Line 390: 1 +Line 391: 0 +Line 392: 0 +Line 393: 0 +Line 394: 0 +Line 395: 1 +Line 396: 0 +Line 397: 0 +Line 398: 1 +Line 399: 1 +Line 400: 1 +Line 401: 1 +Line 402: 1 +Line 403: 1 +Line 404: 1 +Line 405: 0 +Line 406: 0 +Line 407: 0 +Line 408: 1 +Line 409: 0 +Line 410: 0 +Line 411: 1 +Line 412: 0 +Line 413: 1 +Line 414: 1 +Line 415: 0 +Line 416: 0 +Line 417: 0 +Line 418: 1 +Line 419: 1 +Line 420: 1 +Line 421: 0 +Line 422: 1 +Line 423: 0 +Line 424: 1 +Line 425: 1 +Line 426: 1 +Line 427: 1 +Line 428: 0 +Line 429: 1 +Line 430: 1 +Line 431: 1 +Line 432: 1 +Line 433: 1 +Line 434: 1 +Line 435: 1 +Line 436: 0 +Line 437: 1 +Line 438: 0 +Line 439: 0 +Line 440: 1 +Line 441: 0 +Line 442: 0 +Line 443: 0 +Line 444: 1 +Line 445: 0 +Line 446: 1 +Line 447: 0 +Line 448: 0 +Line 449: 0 +Line 450: 1 +Line 451: 1 +Line 452: 0 +Line 453: 0 +Line 454: 0 +Line 455: 1 +Line 456: 0 +Line 457: 1 +Line 458: 0 +Line 459: 0 +Line 460: 0 +Line 461: 1 +Line 462: 1 +Line 463: 1 +Line 464: 1 +Line 465: 1 +Line 466: 1 +Line 467: 1 +Line 468: 0 +Line 469: 0 +Line 470: 0 +Line 471: 1 +Line 472: 1 +Line 473: 0 +Line 474: 1 +Line 475: 1 +Line 476: 1 +Line 477: 1 +Line 478: 0 +Line 479: 0 +Line 480: 0 +Line 481: 0 +Line 482: 1 +Line 483: 0 +Line 484: 0 +Line 485: 1 +Line 486: 1 +Line 487: 0 +Line 488: 0 +Line 489: 0 +Line 490: 0 +Line 491: 0 +Line 492: 1 +Line 493: 1 +Line 494: 1 +Line 495: 1 +Line 496: 1 +Line 497: 1 +Line 498: 1 +Line 499: 1 +Line 500: 0 +Line 501: 0 +Line 502: 0 +Line 503: 0 +Line 504: 0 +Line 505: 1 +Line 506: 1 +Line 507: 1 +Line 508: 1 +Line 509: 0 +Line 510: 1 +Line 511: 0 +Line 512: 0 +Line 513: 0 +Line 514: 0 +Line 515: 1 +Line 516: 1 +Line 517: 0 +Line 518: 1 +Line 519: 0 +Line 520: 1 +Line 521: 0 +Line 522: 0 +Line 523: 0 +Line 524: 0 +Line 525: 1 +Line 526: 1 +Line 527: 0 +Line 528: 1 +Line 529: 1 +Line 530: 1 +Line 531: 1 +Line 532: 0 +Line 533: 0 +Line 534: 0 +Line 535: 0 +Line 536: 1 +Line 537: 1 +Line 538: 1 +Line 539: 0 +Line 540: 0 +Line 541: 1 +Line 542: 1 +Line 543: 0 +Line 544: 0 +Line 545: 0 +Line 546: 0 +Line 547: 0 +Line 548: 1 +Line 549: 1 +Line 550: 1 +Line 551: 1 +Line 552: 1 +Line 553: 1 +Line 554: 1 +Line 555: 0 +Line 556: 1 +Line 557: 1 +Line 558: 0 +Line 559: 1 +Line 560: 1 +Line 561: 1 +Line 562: 1 +Line 563: 1 +Line 564: 0 +Line 565: 0 +Line 566: 1 +Line 567: 0 +Line 568: 1 +Line 569: 1 +Line 570: 1 +Line 571: 1 +Line 572: 0 +Line 573: 1 +Line 574: 1 +Line 575: 0 +Line 576: 0 +Line 577: 0 +Line 578: 0 +Line 579: 0 +Line 580: 0 +Line 581: 1 +Line 582: 1 +Line 583: 1 +Line 584: 0 +Line 585: 1 +Line 586: 1 +Line 587: 0 +Line 588: 1 +Line 589: 0 +Line 590: 0 +Line 591: 1 +Line 592: 1 +Line 593: 1 +Line 594: 1 +Line 595: 1 +Line 596: 0 +Line 597: 1 +Line 598: 1 +Line 599: 0 +Line 600: 0 +Line 601: 1 +Line 602: 1 +Line 603: 0 +Line 604: 1 +Line 605: 1 +Line 606: 1 +Line 607: 1 +Line 608: 0 +Line 609: 0 +Line 610: 0 +Line 611: 0 +Line 612: 0 +Line 613: 0 +Line 614: 0 +Line 615: 1 +Line 616: 1 +Line 617: 1 +Line 618: 1 +Line 619: 0 +Line 620: 0 +Line 621: 1 +Line 622: 1 +Line 623: 1 +Line 624: 1 +Line 625: 1 +Line 626: 1 +Line 627: 1 +Line 628: 1 +Line 629: 0 +Line 630: 1 +Line 631: 0 +Line 632: 1 +Line 633: 1 +Line 634: 1 +Line 635: 1 +Line 636: 0 +Line 637: 0 +Line 638: 1 +Line 639: 0 +Line 640: 0 +Line 641: 0 +Line 642: 0 +Line 643: 0 +Line 644: 0 +Line 645: 0 +Line 646: 0 +Line 647: 0 +Line 648: 0 +Line 649: 0 +Line 650: 0 +Line 651: 0 +Line 652: 0 +Line 653: 0 +Line 654: 0 +Line 655: 0 +Line 656: 0 +Line 657: 0 +Line 658: 0 +Line 659: 0 +Line 660: 0 +Line 661: 0 +Line 662: 0 +Line 663: 0 +Line 664: 0 +Line 665: 0 +Line 666: 0 +Line 667: 0 +Line 668: 0 +Line 669: 0 +Line 670: 0 +Line 671: 0 +Line 672: 0 +Line 673: 1 +Line 674: 0 +Line 675: 0 +Line 676: 0 +Line 677: 1 +Line 678: 1 +Line 679: 0 +Line 680: 0 +Line 681: 1 +Line 682: 0 +Line 683: 1 +Line 684: 0 +Line 685: 0 +Line 686: 0 +Line 687: 0 +Line 688: 0 +Line 689: 0 +Line 690: 0 +Line 691: 0 +Line 692: 0 +Line 693: 0 +Line 694: 0 +Line 695: 0 +Line 696: 0 +Line 697: 0 +Line 698: 0 +Line 699: 0 +Line 700: 0 +Line 701: 0 +Line 702: 0 +Line 703: 0 +Line 704: 0 +Line 705: 1 +Line 706: 0 +Line 707: 0 +Line 708: 0 +Line 709: 1 +Line 710: 1 +Line 711: 0 +Line 712: 0 +Line 713: 1 +Line 714: 0 +Line 715: 1 +Line 716: 0 +Line 717: 0 +Line 718: 0 +Line 719: 0 +Line 720: 0 +Line 721: 0 +Line 722: 0 +Line 723: 0 +Line 724: 0 +Line 725: 0 +Line 726: 0 +Line 727: 0 +Line 728: 0 +Line 729: 0 +Line 730: 0 +Line 731: 0 +Line 732: 0 +Line 733: 0 +Line 734: 0 +Line 735: 0 +Line 736: 0 +Line 737: 1 +Line 738: 0 +Line 739: 0 +Line 740: 0 +Line 741: 1 +Line 742: 1 +Line 743: 0 +Line 744: 0 +Line 745: 1 +Line 746: 0 +Line 747: 1 +Line 748: 0 +Line 749: 0 +Line 750: 0 +Line 751: 0 +Line 752: 0 +Line 753: 0 +Line 754: 0 +Line 755: 0 +Line 756: 0 +Line 757: 0 +Line 758: 0 +Line 759: 0 +Line 760: 0 +Line 761: 0 +Line 762: 0 +Line 763: 0 +Line 764: 0 +Line 765: 0 +Line 766: 0 +Line 767: 0 +Line 768: 0 +Line 769: 1 +Line 770: 0 +Line 771: 0 +Line 772: 0 +Line 773: 1 +Line 774: 1 +Line 775: 0 +Line 776: 0 +Line 777: 1 +Line 778: 0 +Line 779: 1 +Line 780: 0 +Line 781: 0 +Line 782: 0 +Line 783: 0 +Line 784: 0 +Line 785: 0 +Line 786: 0 +Line 787: 0 +Line 788: 0 +Line 789: 0 +Line 790: 0 +Line 791: 0 +Line 792: 0 +Line 793: 0 +Line 794: 0 +Line 795: 0 +Line 796: 0 +Line 797: 0 +Line 798: 0 +Line 799: 0 +Line 800: 0 +Line 801: 1 +Line 802: 0 +Line 803: 0 +Line 804: 0 +Line 805: 1 +Line 806: 1 +Line 807: 0 +Line 808: 0 +Line 809: 1 +Line 810: 0 +Line 811: 1 +Line 812: 0 +Line 813: 0 +Line 814: 0 +Line 815: 0 +Line 816: 0 +Line 817: 0 +Line 818: 0 +Line 819: 0 +Line 820: 0 +Line 821: 0 +Line 822: 0 +Line 823: 0 +Line 824: 0 +Line 825: 0 +Line 826: 0 +Line 827: 0 +Line 828: 0 +Line 829: 0 +Line 830: 0 +Line 831: 0 +Line 832: 0 +Line 833: 1 +Line 834: 0 +Line 835: 0 +Line 836: 0 +Line 837: 1 +Line 838: 1 +Line 839: 0 +Line 840: 0 +Line 841: 1 +Line 842: 0 +Line 843: 1 +Line 844: 0 +Line 845: 0 +Line 846: 0 +Line 847: 0 +Line 848: 0 +Line 849: 0 +Line 850: 0 +Line 851: 0 +Line 852: 0 +Line 853: 0 +Line 854: 0 +Line 855: 0 +Line 856: 0 +Line 857: 0 +Line 858: 0 +Line 859: 0 +Line 860: 0 +Line 861: 0 +Line 862: 0 +Line 863: 0 +Line 864: 0 +Line 865: 1 +Line 866: 0 +Line 867: 0 +Line 868: 0 +Line 869: 1 +Line 870: 1 +Line 871: 0 +Line 872: 0 +Line 873: 1 +Line 874: 0 +Line 875: 1 +Line 876: 0 +Line 877: 0 +Line 878: 0 +Line 879: 0 +Line 880: 0 +Line 881: 0 +Line 882: 0 +Line 883: 0 +Line 884: 0 +Line 885: 0 +Line 886: 0 +Line 887: 0 +Line 888: 0 +Line 889: 0 +Line 890: 0 +Line 891: 0 +Line 892: 0 +Line 893: 0 +Line 894: 0 +Line 895: 0 +Line 896: 0 +Line 897: 1 +Line 898: 0 +Line 899: 0 +Line 900: 0 +Line 901: 1 +Line 902: 1 +Line 903: 0 +Line 904: 0 +Line 905: 1 +Line 906: 0 +Line 907: 1 +Line 908: 0 +Line 909: 0 +Line 910: 0 +Line 911: 0 +Line 912: 0 +Line 913: 0 +Line 914: 0 +Line 915: 0 +Line 916: 0 +Line 917: 0 +Line 918: 0 +Line 919: 0 +Line 920: 0 +Line 921: 0 +Line 922: 0 +Line 923: 0 +Line 924: 0 +Line 925: 0 +Line 926: 0 +Line 927: 0 +Line 928: 0 +Line 929: 1 +Line 930: 0 +Line 931: 0 +Line 932: 0 +Line 933: 1 +Line 934: 1 +Line 935: 0 +Line 936: 0 +Line 937: 1 +Line 938: 0 +Line 939: 1 +Line 940: 0 +Line 941: 0 +Line 942: 0 +Line 943: 0 +Line 944: 0 +Line 945: 0 +Line 946: 0 +Line 947: 0 +Line 948: 0 +Line 949: 0 +Line 950: 0 +Line 951: 0 +Line 952: 0 +Line 953: 0 +Line 954: 0 +Line 955: 0 +Line 956: 0 +Line 957: 0 +Line 958: 0 +Line 959: 0 +Line 960: 0 +Line 961: 1 +Line 962: 0 +Line 963: 0 +Line 964: 0 +Line 965: 1 +Line 966: 1 +Line 967: 0 +Line 968: 0 +Line 969: 1 +Line 970: 0 +Line 971: 1 +Line 972: 0 +Line 973: 0 +Line 974: 0 +Line 975: 0 +Line 976: 0 +Line 977: 0 +Line 978: 0 +Line 979: 0 +Line 980: 0 +Line 981: 0 +Line 982: 0 +Line 983: 0 +Line 984: 0 +Line 985: 0 +Line 986: 0 +Line 987: 0 +Line 988: 0 +Line 989: 0 +Line 990: 0 +Line 991: 0 +Line 992: 0 +Line 993: 1 +Line 994: 0 +Line 995: 0 +Line 996: 0 +Line 997: 1 +Line 998: 1 +Line 999: 0 +Line 1000: 0 +Line 1001: 1 +Line 1002: 0 +Line 1003: 1 +Line 1004: 0 +Line 1005: 0 +Line 1006: 0 +Line 1007: 0 +Line 1008: 0 +Line 1009: 0 +Line 1010: 0 +Line 1011: 0 +Line 1012: 0 +Line 1013: 0 +Line 1014: 0 +Line 1015: 0 +Line 1016: 0 +Line 1017: 0 +Line 1018: 0 +Line 1019: 0 +Line 1020: 0 +Line 1021: 0 +Line 1022: 0 +Line 1023: 0 +Line 1024: 0 +Line 1025: 1 +Line 1026: 0 +Line 1027: 0 +Line 1028: 0 +Line 1029: 1 +Line 1030: 1 +Line 1031: 0 +Line 1032: 0 +Line 1033: 1 +Line 1034: 0 +Line 1035: 1 +Line 1036: 0 +Line 1037: 0 +Line 1038: 0 +Line 1039: 0 +Line 1040: 0 +Line 1041: 0 +Line 1042: 0 +Line 1043: 0 +Line 1044: 0 +Line 1045: 0 +Line 1046: 0 +Line 1047: 0 +Line 1048: 0 +Line 1049: 0 +Line 1050: 0 +Line 1051: 0 +Line 1052: 0 +Line 1053: 0 +Line 1054: 0 +Line 1055: 0 +Line 1056: 0 +Line 1057: 1 +Line 1058: 0 +Line 1059: 0 +Line 1060: 0 +Line 1061: 1 +Line 1062: 1 +Line 1063: 0 +Line 1064: 0 +Line 1065: 1 +Line 1066: 0 +Line 1067: 1 +Line 1068: 0 +Line 1069: 0 +Line 1070: 0 +Line 1071: 0 +Line 1072: 0 +Line 1073: 0 +Line 1074: 0 +Line 1075: 0 +Line 1076: 0 +Line 1077: 0 +Line 1078: 0 +Line 1079: 0 +Line 1080: 0 +Line 1081: 0 +Line 1082: 0 +Line 1083: 0 +Line 1084: 0 +Line 1085: 0 +Line 1086: 0 +Line 1087: 0 +Line 1088: 0 +Line 1089: 1 +Line 1090: 0 +Line 1091: 0 +Line 1092: 0 +Line 1093: 1 +Line 1094: 1 +Line 1095: 0 +Line 1096: 0 +Line 1097: 1 +Line 1098: 0 +Line 1099: 1 +Line 1100: 0 +Line 1101: 0 +Line 1102: 0 +Line 1103: 0 +Line 1104: 0 +Line 1105: 0 +Line 1106: 0 +Line 1107: 0 +Line 1108: 0 +Line 1109: 0 +Line 1110: 0 +Line 1111: 0 +Line 1112: 0 +Line 1113: 0 +Line 1114: 0 +Line 1115: 0 +Line 1116: 0 +Line 1117: 0 +Line 1118: 0 +Line 1119: 0 +Line 1120: 0 +Line 1121: 1 +Line 1122: 0 +Line 1123: 0 +Line 1124: 0 +Line 1125: 1 +Line 1126: 1 +Line 1127: 0 +Line 1128: 0 +Line 1129: 1 +Line 1130: 0 +Line 1131: 1 +Line 1132: 0 +Line 1133: 0 +Line 1134: 0 +Line 1135: 0 +Line 1136: 0 +Line 1137: 0 +Line 1138: 0 +Line 1139: 0 +Line 1140: 0 +Line 1141: 0 +Line 1142: 0 +Line 1143: 0 +Line 1144: 0 +Line 1145: 0 +Line 1146: 0 +Line 1147: 0 +Line 1148: 0 +Line 1149: 0 +Line 1150: 0 +Line 1151: 0 +Line 1152: 0 +Line 1153: 1 +Line 1154: 0 +Line 1155: 0 +Line 1156: 0 +Line 1157: 1 +Line 1158: 1 +Line 1159: 0 +Line 1160: 0 +Line 1161: 1 +Line 1162: 0 +Line 1163: 1 +Line 1164: 0 +Line 1165: 0 +Line 1166: 0 +Line 1167: 0 +Line 1168: 0 +Line 1169: 0 +Line 1170: 0 +Line 1171: 0 +Line 1172: 0 +Line 1173: 0 +Line 1174: 0 +Line 1175: 0 +Line 1176: 0 +Line 1177: 0 +Line 1178: 0 +Line 1179: 0 +Line 1180: 0 +Line 1181: 0 +Line 1182: 0 +Line 1183: 0 +Line 1184: 0 +Line 1185: 1 +Line 1186: 0 +Line 1187: 0 +Line 1188: 0 +Line 1189: 1 +Line 1190: 1 +Line 1191: 0 +Line 1192: 0 +Line 1193: 1 +Line 1194: 0 +Line 1195: 1 +Line 1196: 0 +Line 1197: 0 +Line 1198: 0 +Line 1199: 0 +Line 1200: 0 +Line 1201: 0 +Line 1202: 0 +Line 1203: 0 +Line 1204: 0 +Line 1205: 0 +Line 1206: 0 +Line 1207: 0 +Line 1208: 0 +Line 1209: 0 +Line 1210: 0 +Line 1211: 0 +Line 1212: 0 +Line 1213: 0 +Line 1214: 0 +Line 1215: 0 +Line 1216: 0 +Line 1217: 1 +Line 1218: 0 +Line 1219: 0 +Line 1220: 0 +Line 1221: 1 +Line 1222: 1 +Line 1223: 0 +Line 1224: 0 +Line 1225: 1 +Line 1226: 0 +Line 1227: 1 +Line 1228: 0 +Line 1229: 0 +Line 1230: 0 +Line 1231: 0 +Line 1232: 0 +Line 1233: 0 +Line 1234: 0 +Line 1235: 0 +Line 1236: 0 +Line 1237: 0 +Line 1238: 0 +Line 1239: 0 +Line 1240: 0 +Line 1241: 0 +Line 1242: 0 +Line 1243: 0 +Line 1244: 0 +Line 1245: 0 +Line 1246: 0 +Line 1247: 0 +Line 1248: 0 +Line 1249: 1 +Line 1250: 0 +Line 1251: 0 +Line 1252: 0 +Line 1253: 1 +Line 1254: 1 +Line 1255: 0 +Line 1256: 0 +Line 1257: 1 +Line 1258: 0 +Line 1259: 1 +Line 1260: 0 +Line 1261: 0 +Line 1262: 0 +Line 1263: 0 +Line 1264: 0 +Line 1265: 0 +Line 1266: 0 +Line 1267: 0 +Line 1268: 0 +Line 1269: 0 +Line 1270: 0 +Line 1271: 0 +Line 1272: 0 +Line 1273: 0 +Line 1274: 0 +Line 1275: 0 +Line 1276: 0 +Line 1277: 0 +Line 1278: 0 +Line 1279: 0 +Line 1280: 0 +Line 1281: 1 +Line 1282: 0 +Line 1283: 0 +Line 1284: 0 +Line 1285: 1 +Line 1286: 1 +Line 1287: 0 +Line 1288: 0 +Line 1289: 1 +Line 1290: 0 +Line 1291: 1 +Line 1292: 0 +Line 1293: 0 +Line 1294: 0 +Line 1295: 0 +Line 1296: 0 +Line 1297: 0 +Line 1298: 0 +Line 1299: 0 +Line 1300: 0 +Line 1301: 0 +Line 1302: 0 +Line 1303: 0 +Line 1304: 0 +Line 1305: 0 +Line 1306: 0 +Line 1307: 0 +Line 1308: 0 +Line 1309: 0 +Line 1310: 0 +Line 1311: 0 +Line 1312: 0 +Line 1313: 1 +Line 1314: 0 +Line 1315: 0 +Line 1316: 0 +Line 1317: 1 +Line 1318: 1 +Line 1319: 0 +Line 1320: 0 +Line 1321: 1 +Line 1322: 0 +Line 1323: 1 +Line 1324: 0 +Line 1325: 0 +Line 1326: 0 +Line 1327: 0 +Line 1328: 0 +Line 1329: 0 +Line 1330: 0 +Line 1331: 0 +Line 1332: 0 +Line 1333: 0 +Line 1334: 0 +Line 1335: 0 +Line 1336: 0 +Line 1337: 0 +Line 1338: 0 +Line 1339: 0 +Line 1340: 0 +Line 1341: 0 +Line 1342: 0 +Line 1343: 0 +Line 1344: 0 +Line 1345: 1 +Line 1346: 0 +Line 1347: 0 +Line 1348: 0 +Line 1349: 1 +Line 1350: 1 +Line 1351: 0 +Line 1352: 0 +Line 1353: 1 +Line 1354: 0 +Line 1355: 1 +Line 1356: 0 +Line 1357: 0 +Line 1358: 0 +Line 1359: 0 +Line 1360: 0 +Line 1361: 0 +Line 1362: 0 +Line 1363: 0 +Line 1364: 0 +Line 1365: 0 +Line 1366: 0 +Line 1367: 0 +Line 1368: 0 +Line 1369: 0 +Line 1370: 0 +Line 1371: 0 +Line 1372: 0 +Line 1373: 0 +Line 1374: 0 +Line 1375: 0 +Line 1376: 0 +Line 1377: 1 +Line 1378: 0 +Line 1379: 0 +Line 1380: 0 +Line 1381: 1 +Line 1382: 1 +Line 1383: 0 +Line 1384: 0 +Line 1385: 1 +Line 1386: 0 +Line 1387: 1 +Line 1388: 0 +Line 1389: 0 +Line 1390: 0 +Line 1391: 0 +Line 1392: 0 +Line 1393: 0 +Line 1394: 0 +Line 1395: 0 +Line 1396: 0 +Line 1397: 0 +Line 1398: 0 +Line 1399: 0 +Line 1400: 0 +Line 1401: 0 +Line 1402: 0 +Line 1403: 0 +Line 1404: 0 +Line 1405: 0 +Line 1406: 0 +Line 1407: 0 +Line 1408: 0 +Line 1409: 1 +Line 1410: 0 +Line 1411: 0 +Line 1412: 0 +Line 1413: 1 +Line 1414: 1 +Line 1415: 0 +Line 1416: 0 +Line 1417: 1 +Line 1418: 0 +Line 1419: 1 +Line 1420: 0 +Line 1421: 0 +Line 1422: 0 +Line 1423: 0 +Line 1424: 0 +Line 1425: 0 +Line 1426: 0 +Line 1427: 0 +Line 1428: 0 +Line 1429: 0 +Line 1430: 0 +Line 1431: 0 +Line 1432: 0 +Line 1433: 0 +Line 1434: 0 +Line 1435: 0 +Line 1436: 0 +Line 1437: 0 +Line 1438: 0 +Line 1439: 0 +Line 1440: 0 +Line 1441: 1 +Line 1442: 0 +Line 1443: 0 +Line 1444: 0 +Line 1445: 1 +Line 1446: 1 +Line 1447: 0 +Line 1448: 0 +Line 1449: 1 +Line 1450: 0 +Line 1451: 1 +Line 1452: 0 +Line 1453: 0 +Line 1454: 0 +Line 1455: 0 +Line 1456: 0 +Line 1457: 0 +Line 1458: 0 +Line 1459: 0 +Line 1460: 0 +Line 1461: 0 +Line 1462: 0 +Line 1463: 0 +Line 1464: 0 +Line 1465: 0 +Line 1466: 0 +Line 1467: 0 +Line 1468: 0 +Line 1469: 0 +Line 1470: 0 +Line 1471: 0 +Line 1472: 0 +Line 1473: 0 +Line 1474: 0 +Line 1475: 1 +Line 1476: 0 +Line 1477: 1 +Line 1478: 0 +Line 1479: 0 +Line 1480: 0 +Line 1481: 0 +Line 1482: 1 +Line 1483: 0 +Line 1484: 1 +Line 1485: 0 +Line 1486: 1 +Line 1487: 1 +Line 1488: 0 +Line 1489: 0 +Line 1490: 0 +Line 1491: 0 +Line 1492: 0 +Line 1493: 0 +Line 1494: 0 +Line 1495: 0 +Line 1496: 0 +Line 1497: 0 +Line 1498: 0 +Line 1499: 0 +Line 1500: 0 +Line 1501: 0 +Line 1502: 0 +Line 1503: 0 +Line 1504: 0 +Line 1505: 0 +Line 1506: 0 +Line 1507: 1 +Line 1508: 0 +Line 1509: 1 +Line 1510: 0 +Line 1511: 1 +Line 1512: 0 +Line 1513: 0 +Line 1514: 1 +Line 1515: 0 +Line 1516: 1 +Line 1517: 1 +Line 1518: 1 +Line 1519: 0 +Line 1520: 0 +Line 1521: 0 +Line 1522: 0 +Line 1523: 0 +Line 1524: 0 +Line 1525: 0 +Line 1526: 0 +Line 1527: 0 +Line 1528: 0 +Line 1529: 0 +Line 1530: 0 +Line 1531: 0 +Line 1532: 0 +Line 1533: 0 +Line 1534: 0 +Line 1535: 0 +Line 1536: 0 +Line 1537: 0 +Line 1538: 0 +Line 1539: 1 +Line 1540: 0 +Line 1541: 1 +Line 1542: 1 +Line 1543: 0 +Line 1544: 0 +Line 1545: 0 +Line 1546: 1 +Line 1547: 1 +Line 1548: 0 +Line 1549: 1 +Line 1550: 1 +Line 1551: 0 +Line 1552: 0 +Line 1553: 0 +Line 1554: 0 +Line 1555: 0 +Line 1556: 0 +Line 1557: 0 +Line 1558: 0 +Line 1559: 0 +Line 1560: 0 +Line 1561: 0 +Line 1562: 0 +Line 1563: 0 +Line 1564: 0 +Line 1565: 0 +Line 1566: 0 +Line 1567: 0 +Line 1568: 0 +Line 1569: 0 +Line 1570: 0 +Line 1571: 1 +Line 1572: 0 +Line 1573: 1 +Line 1574: 1 +Line 1575: 1 +Line 1576: 0 +Line 1577: 1 +Line 1578: 0 +Line 1579: 0 +Line 1580: 0 +Line 1581: 0 +Line 1582: 1 +Line 1583: 1 +Line 1584: 0 +Line 1585: 0 +Line 1586: 0 +Line 1587: 0 +Line 1588: 0 +Line 1589: 0 +Line 1590: 0 +Line 1591: 0 +Line 1592: 0 +Line 1593: 0 +Line 1594: 0 +Line 1595: 0 +Line 1596: 0 +Line 1597: 0 +Line 1598: 0 +Line 1599: 0 +Line 1600: 0 +Line 1601: 0 +Line 1602: 0 +Line 1603: 1 +Line 1604: 1 +Line 1605: 0 +Line 1606: 0 +Line 1607: 0 +Line 1608: 0 +Line 1609: 1 +Line 1610: 0 +Line 1611: 1 +Line 1612: 0 +Line 1613: 1 +Line 1614: 1 +Line 1615: 0 +Line 1616: 0 +Line 1617: 0 +Line 1618: 0 +Line 1619: 0 +Line 1620: 0 +Line 1621: 0 +Line 1622: 0 +Line 1623: 0 +Line 1624: 0 +Line 1625: 0 +Line 1626: 0 +Line 1627: 0 +Line 1628: 0 +Line 1629: 0 +Line 1630: 0 +Line 1631: 0 +Line 1632: 0 +Line 1633: 0 +Line 1634: 0 +Line 1635: 1 +Line 1636: 1 +Line 1637: 0 +Line 1638: 0 +Line 1639: 1 +Line 1640: 0 +Line 1641: 1 +Line 1642: 1 +Line 1643: 0 +Line 1644: 1 +Line 1645: 1 +Line 1646: 0 +Line 1647: 0 +Line 1648: 0 +Line 1649: 0 +Line 1650: 0 +Line 1651: 0 +Line 1652: 0 +Line 1653: 0 +Line 1654: 0 +Line 1655: 0 +Line 1656: 0 +Line 1657: 0 +Line 1658: 0 +Line 1659: 0 +Line 1660: 0 +Line 1661: 0 +Line 1662: 0 +Line 1663: 0 +Line 1664: 0 +Line 1665: 0 +Line 1666: 0 +Line 1667: 1 +Line 1668: 1 +Line 1669: 0 +Line 1670: 1 +Line 1671: 0 +Line 1672: 1 +Line 1673: 0 +Line 1674: 0 +Line 1675: 0 +Line 1676: 0 +Line 1677: 1 +Line 1678: 1 +Line 1679: 1 +Line 1680: 0 +Line 1681: 0 +Line 1682: 0 +Line 1683: 0 +Line 1684: 0 +Line 1685: 0 +Line 1686: 0 +Line 1687: 0 +Line 1688: 0 +Line 1689: 0 +Line 1690: 0 +Line 1691: 0 +Line 1692: 0 +Line 1693: 0 +Line 1694: 0 +Line 1695: 0 +Line 1696: 0 +Line 1697: 0 +Line 1698: 0 +Line 1699: 1 +Line 1700: 1 +Line 1701: 0 +Line 1702: 1 +Line 1703: 1 +Line 1704: 1 +Line 1705: 0 +Line 1706: 1 +Line 1707: 0 +Line 1708: 0 +Line 1709: 1 +Line 1710: 1 +Line 1711: 0 +Line 1712: 0 +Line 1713: 0 +Line 1714: 0 +Line 1715: 0 +Line 1716: 0 +Line 1717: 0 +Line 1718: 0 +Line 1719: 0 +Line 1720: 0 +Line 1721: 0 +Line 1722: 0 +Line 1723: 0 +Line 1724: 0 +Line 1725: 0 +Line 1726: 0 +Line 1727: 0 +Line 1728: 0 +Line 1729: 0 +Line 1730: 0 +Line 1731: 1 +Line 1732: 1 +Line 1733: 1 +Line 1734: 0 +Line 1735: 0 +Line 1736: 1 +Line 1737: 1 +Line 1738: 0 +Line 1739: 0 +Line 1740: 1 +Line 1741: 0 +Line 1742: 0 +Line 1743: 0 +Line 1744: 0 +Line 1745: 0 +Line 1746: 0 +Line 1747: 0 +Line 1748: 0 +Line 1749: 0 +Line 1750: 0 +Line 1751: 0 +Line 1752: 0 +Line 1753: 0 +Line 1754: 0 +Line 1755: 0 +Line 1756: 0 +Line 1757: 0 +Line 1758: 0 +Line 1759: 0 +Line 1760: 0 +Line 1761: 0 +Line 1762: 0 +Line 1763: 1 +Line 1764: 1 +Line 1765: 1 +Line 1766: 0 +Line 1767: 1 +Line 1768: 1 +Line 1769: 1 +Line 1770: 1 +Line 1771: 0 +Line 1772: 1 +Line 1773: 1 +Line 1774: 0 +Line 1775: 1 +Line 1776: 0 +Line 1777: 0 +Line 1778: 0 +Line 1779: 0 +Line 1780: 0 +Line 1781: 0 +Line 1782: 0 +Line 1783: 0 +Line 1784: 0 +Line 1785: 0 +Line 1786: 0 +Line 1787: 0 +Line 1788: 0 +Line 1789: 0 +Line 1790: 0 +Line 1791: 0 +Line 1792: 0 +Line 1793: 0 +Line 1794: 0 +Line 1795: 1 +Line 1796: 1 +Line 1797: 1 +Line 1798: 1 +Line 1799: 1 +Line 1800: 0 +Line 1801: 0 +Line 1802: 0 +Line 1803: 1 +Line 1804: 0 +Line 1805: 1 +Line 1806: 0 +Line 1807: 0 +Line 1808: 0 +Line 1809: 0 +Line 1810: 0 +Line 1811: 0 +Line 1812: 0 +Line 1813: 0 +Line 1814: 0 +Line 1815: 0 +Line 1816: 0 +Line 1817: 0 +Line 1818: 0 +Line 1819: 0 +Line 1820: 0 +Line 1821: 0 +Line 1822: 0 +Line 1823: 0 +Line 1824: 0 +Line 1825: 0 +Line 1826: 1 +Line 1827: 0 +Line 1828: 0 +Line 1829: 0 +Line 1830: 0 +Line 1831: 0 +Line 1832: 0 +Line 1833: 0 +Line 1834: 1 +Line 1835: 1 +Line 1836: 1 +Line 1837: 1 +Line 1838: 0 +Line 1839: 1 +Line 1840: 0 +Line 1841: 0 +Line 1842: 0 +Line 1843: 0 +Line 1844: 0 +Line 1845: 0 +Line 1846: 0 +Line 1847: 0 +Line 1848: 0 +Line 1849: 0 +Line 1850: 0 +Line 1851: 0 +Line 1852: 0 +Line 1853: 0 +Line 1854: 0 +Line 1855: 0 +Line 1856: 0 +Line 1857: 0 +Line 1858: 1 +Line 1859: 0 +Line 1860: 0 +Line 1861: 0 +Line 1862: 0 +Line 1863: 1 +Line 1864: 0 +Line 1865: 1 +Line 1866: 1 +Line 1867: 0 +Line 1868: 0 +Line 1869: 1 +Line 1870: 1 +Line 1871: 1 +Line 1872: 0 +Line 1873: 0 +Line 1874: 0 +Line 1875: 0 +Line 1876: 0 +Line 1877: 0 +Line 1878: 0 +Line 1879: 0 +Line 1880: 0 +Line 1881: 0 +Line 1882: 0 +Line 1883: 0 +Line 1884: 0 +Line 1885: 0 +Line 1886: 0 +Line 1887: 0 +Line 1888: 0 +Line 1889: 0 +Line 1890: 1 +Line 1891: 0 +Line 1892: 0 +Line 1893: 0 +Line 1894: 1 +Line 1895: 0 +Line 1896: 1 +Line 1897: 0 +Line 1898: 0 +Line 1899: 1 +Line 1900: 0 +Line 1901: 0 +Line 1902: 1 +Line 1903: 0 +Line 1904: 0 +Line 1905: 0 +Line 1906: 0 +Line 1907: 0 +Line 1908: 0 +Line 1909: 0 +Line 1910: 0 +Line 1911: 0 +Line 1912: 0 +Line 1913: 0 +Line 1914: 0 +Line 1915: 0 +Line 1916: 0 +Line 1917: 0 +Line 1918: 0 +Line 1919: 0 +Line 1920: 0 +Line 1921: 0 +Line 1922: 1 +Line 1923: 0 +Line 1924: 0 +Line 1925: 0 +Line 1926: 1 +Line 1927: 1 +Line 1928: 1 +Line 1929: 0 +Line 1930: 1 +Line 1931: 1 +Line 1932: 1 +Line 1933: 1 +Line 1934: 0 +Line 1935: 1 +Line 1936: 0 +Line 1937: 0 +Line 1938: 0 +Line 1939: 0 +Line 1940: 0 +Line 1941: 0 +Line 1942: 0 +Line 1943: 0 +Line 1944: 0 +Line 1945: 0 +Line 1946: 0 +Line 1947: 0 +Line 1948: 0 +Line 1949: 0 +Line 1950: 0 +Line 1951: 0 +Line 1952: 0 +Line 1953: 0 +Line 1954: 1 +Line 1955: 0 +Line 1956: 0 +Line 1957: 1 +Line 1958: 0 +Line 1959: 0 +Line 1960: 1 +Line 1961: 1 +Line 1962: 1 +Line 1963: 0 +Line 1964: 1 +Line 1965: 0 +Line 1966: 0 +Line 1967: 0 +Line 1968: 0 +Line 1969: 0 +Line 1970: 0 +Line 1971: 0 +Line 1972: 0 +Line 1973: 0 +Line 1974: 0 +Line 1975: 0 +Line 1976: 0 +Line 1977: 0 +Line 1978: 0 +Line 1979: 0 +Line 1980: 0 +Line 1981: 0 +Line 1982: 0 +Line 1983: 0 +Line 1984: 0 +Line 1985: 0 +Line 1986: 1 +Line 1987: 0 +Line 1988: 0 +Line 1989: 1 +Line 1990: 1 +Line 1991: 0 +Line 1992: 0 +Line 1993: 0 +Line 1994: 0 +Line 1995: 1 +Line 1996: 0 +Line 1997: 0 +Line 1998: 1 +Line 1999: 0 +Line 2000: 0 +Line 2001: 0 +Line 2002: 0 +Line 2003: 0 +Line 2004: 0 +Line 2005: 0 +Line 2006: 0 +Line 2007: 0 +Line 2008: 0 +Line 2009: 0 +Line 2010: 0 +Line 2011: 0 +Line 2012: 0 +Line 2013: 0 +Line 2014: 0 +Line 2015: 0 +Line 2016: 0 +Line 2017: 0 +Line 2018: 1 +Line 2019: 0 +Line 2020: 0 +Line 2021: 1 +Line 2022: 1 +Line 2023: 1 +Line 2024: 0 +Line 2025: 0 +Line 2026: 1 +Line 2027: 1 +Line 2028: 1 +Line 2029: 0 +Line 2030: 1 +Line 2031: 1 +Line 2032: 0 +Line 2033: 0 +Line 2034: 0 +Line 2035: 0 +Line 2036: 0 +Line 2037: 0 +Line 2038: 0 +Line 2039: 0 +Line 2040: 0 +Line 2041: 0 +Line 2042: 0 +Line 2043: 0 +Line 2044: 0 +Line 2045: 0 +Line 2046: 0 +Line 2047: 0 +Line 2048: 0 +Line 2049: 0 +Line 2050: 1 +Line 2051: 0 +Line 2052: 1 +Line 2053: 0 +Line 2054: 0 +Line 2055: 0 +Line 2056: 0 +Line 2057: 1 +Line 2058: 1 +Line 2059: 0 +Line 2060: 0 +Line 2061: 0 +Line 2062: 1 +Line 2063: 0 +Line 2064: 0 +Line 2065: 0 +Line 2066: 0 +Line 2067: 0 +Line 2068: 0 +Line 2069: 0 +Line 2070: 0 +Line 2071: 0 +Line 2072: 0 +Line 2073: 0 +Line 2074: 0 +Line 2075: 0 +Line 2076: 0 +Line 2077: 0 +Line 2078: 0 +Line 2079: 0 +Line 2080: 0 +Line 2081: 0 +Line 2082: 1 +Line 2083: 0 +Line 2084: 1 +Line 2085: 0 +Line 2086: 0 +Line 2087: 1 +Line 2088: 1 +Line 2089: 0 +Line 2090: 0 +Line 2091: 0 +Line 2092: 0 +Line 2093: 1 +Line 2094: 1 +Line 2095: 1 +Line 2096: 0 +Line 2097: 0 +Line 2098: 0 +Line 2099: 0 +Line 2100: 0 +Line 2101: 0 +Line 2102: 0 +Line 2103: 0 +Line 2104: 0 +Line 2105: 0 +Line 2106: 0 +Line 2107: 0 +Line 2108: 0 +Line 2109: 0 +Line 2110: 0 +Line 2111: 0 +Line 2112: 0 +Line 2113: 0 +Line 2114: 1 +Line 2115: 0 +Line 2116: 1 +Line 2117: 0 +Line 2118: 1 +Line 2119: 0 +Line 2120: 1 +Line 2121: 0 +Line 2122: 1 +Line 2123: 0 +Line 2124: 1 +Line 2125: 0 +Line 2126: 0 +Line 2127: 1 +Line 2128: 0 +Line 2129: 0 +Line 2130: 0 +Line 2131: 0 +Line 2132: 0 +Line 2133: 0 +Line 2134: 0 +Line 2135: 0 +Line 2136: 0 +Line 2137: 0 +Line 2138: 0 +Line 2139: 0 +Line 2140: 0 +Line 2141: 0 +Line 2142: 0 +Line 2143: 0 +Line 2144: 0 +Line 2145: 0 +Line 2146: 1 +Line 2147: 0 +Line 2148: 1 +Line 2149: 0 +Line 2150: 1 +Line 2151: 1 +Line 2152: 1 +Line 2153: 1 +Line 2154: 0 +Line 2155: 0 +Line 2156: 1 +Line 2157: 0 +Line 2158: 0 +Line 2159: 0 +Line 2160: 0 +Line 2161: 0 +Line 2162: 0 +Line 2163: 0 +Line 2164: 0 +Line 2165: 0 +Line 2166: 0 +Line 2167: 0 +Line 2168: 0 +Line 2169: 0 +Line 2170: 0 +Line 2171: 0 +Line 2172: 0 +Line 2173: 0 +Line 2174: 0 +Line 2175: 0 +Line 2176: 0 +Line 2177: 0 +Line 2178: 1 +Line 2179: 0 +Line 2180: 1 +Line 2181: 1 +Line 2182: 0 +Line 2183: 0 +Line 2184: 1 +Line 2185: 1 +Line 2186: 1 +Line 2187: 0 +Line 2188: 0 +Line 2189: 0 +Line 2190: 1 +Line 2191: 1 +Line 2192: 0 +Line 2193: 0 +Line 2194: 0 +Line 2195: 0 +Line 2196: 0 +Line 2197: 0 +Line 2198: 0 +Line 2199: 0 +Line 2200: 0 +Line 2201: 0 +Line 2202: 0 +Line 2203: 0 +Line 2204: 0 +Line 2205: 0 +Line 2206: 0 +Line 2207: 0 +Line 2208: 0 +Line 2209: 0 +Line 2210: 1 +Line 2211: 0 +Line 2212: 1 +Line 2213: 1 +Line 2214: 0 +Line 2215: 1 +Line 2216: 1 +Line 2217: 1 +Line 2218: 1 +Line 2219: 1 +Line 2220: 1 +Line 2221: 0 +Line 2222: 0 +Line 2223: 1 +Line 2224: 0 +Line 2225: 0 +Line 2226: 0 +Line 2227: 0 +Line 2228: 0 +Line 2229: 0 +Line 2230: 0 +Line 2231: 0 +Line 2232: 0 +Line 2233: 0 +Line 2234: 0 +Line 2235: 0 +Line 2236: 0 +Line 2237: 0 +Line 2238: 0 +Line 2239: 0 +Line 2240: 0 +Line 2241: 0 +Line 2242: 1 +Line 2243: 0 +Line 2244: 1 +Line 2245: 1 +Line 2246: 1 +Line 2247: 1 +Line 2248: 0 +Line 2249: 0 +Line 2250: 0 +Line 2251: 0 +Line 2252: 1 +Line 2253: 1 +Line 2254: 0 +Line 2255: 0 +Line 2256: 0 +Line 2257: 0 +Line 2258: 0 +Line 2259: 0 +Line 2260: 0 +Line 2261: 0 +Line 2262: 0 +Line 2263: 0 +Line 2264: 0 +Line 2265: 0 +Line 2266: 0 +Line 2267: 0 +Line 2268: 0 +Line 2269: 0 +Line 2270: 0 +Line 2271: 0 +Line 2272: 0 +Line 2273: 0 +Line 2274: 1 +Line 2275: 1 +Line 2276: 0 +Line 2277: 0 +Line 2278: 0 +Line 2279: 0 +Line 2280: 0 +Line 2281: 0 +Line 2282: 0 +Line 2283: 1 +Line 2284: 1 +Line 2285: 0 +Line 2286: 0 +Line 2287: 1 +Line 2288: 0 +Line 2289: 0 +Line 2290: 0 +Line 2291: 0 +Line 2292: 0 +Line 2293: 0 +Line 2294: 0 +Line 2295: 0 +Line 2296: 0 +Line 2297: 0 +Line 2298: 0 +Line 2299: 0 +Line 2300: 0 +Line 2301: 0 +Line 2302: 0 +Line 2303: 0 +Line 2304: 0 +Line 2305: 0 +Line 2306: 1 +Line 2307: 1 +Line 2308: 0 +Line 2309: 0 +Line 2310: 0 +Line 2311: 1 +Line 2312: 0 +Line 2313: 0 +Line 2314: 1 +Line 2315: 0 +Line 2316: 0 +Line 2317: 0 +Line 2318: 0 +Line 2319: 1 +Line 2320: 0 +Line 2321: 0 +Line 2322: 0 +Line 2323: 0 +Line 2324: 0 +Line 2325: 0 +Line 2326: 0 +Line 2327: 0 +Line 2328: 0 +Line 2329: 0 +Line 2330: 0 +Line 2331: 0 +Line 2332: 0 +Line 2333: 0 +Line 2334: 0 +Line 2335: 0 +Line 2336: 0 +Line 2337: 0 +Line 2338: 1 +Line 2339: 1 +Line 2340: 0 +Line 2341: 0 +Line 2342: 1 +Line 2343: 0 +Line 2344: 0 +Line 2345: 0 +Line 2346: 1 +Line 2347: 0 +Line 2348: 0 +Line 2349: 1 +Line 2350: 0 +Line 2351: 0 +Line 2352: 0 +Line 2353: 0 +Line 2354: 0 +Line 2355: 0 +Line 2356: 0 +Line 2357: 0 +Line 2358: 0 +Line 2359: 0 +Line 2360: 0 +Line 2361: 0 +Line 2362: 0 +Line 2363: 0 +Line 2364: 0 +Line 2365: 0 +Line 2366: 0 +Line 2367: 0 +Line 2368: 0 +Line 2369: 0 +Line 2370: 1 +Line 2371: 1 +Line 2372: 0 +Line 2373: 0 +Line 2374: 1 +Line 2375: 1 +Line 2376: 0 +Line 2377: 0 +Line 2378: 1 +Line 2379: 0 +Line 2380: 0 +Line 2381: 0 +Line 2382: 0 +Line 2383: 0 +Line 2384: 0 +Line 2385: 0 +Line 2386: 0 +Line 2387: 0 +Line 2388: 0 +Line 2389: 0 +Line 2390: 0 +Line 2391: 0 +Line 2392: 0 +Line 2393: 0 +Line 2394: 0 +Line 2395: 0 +Line 2396: 0 +Line 2397: 0 +Line 2398: 0 +Line 2399: 0 +Line 2400: 0 +Line 2401: 0 +Line 2402: 1 +Line 2403: 1 +Line 2404: 0 +Line 2405: 1 +Line 2406: 0 +Line 2407: 0 +Line 2408: 0 +Line 2409: 0 +Line 2410: 0 +Line 2411: 1 +Line 2412: 0 +Line 2413: 1 +Line 2414: 1 +Line 2415: 0 +Line 2416: 0 +Line 2417: 0 +Line 2418: 0 +Line 2419: 0 +Line 2420: 0 +Line 2421: 0 +Line 2422: 0 +Line 2423: 0 +Line 2424: 0 +Line 2425: 0 +Line 2426: 0 +Line 2427: 0 +Line 2428: 0 +Line 2429: 0 +Line 2430: 0 +Line 2431: 0 +Line 2432: 0 +Line 2433: 0 +Line 2434: 1 +Line 2435: 1 +Line 2436: 0 +Line 2437: 1 +Line 2438: 0 +Line 2439: 1 +Line 2440: 0 +Line 2441: 0 +Line 2442: 0 +Line 2443: 0 +Line 2444: 0 +Line 2445: 1 +Line 2446: 1 +Line 2447: 0 +Line 2448: 0 +Line 2449: 0 +Line 2450: 0 +Line 2451: 0 +Line 2452: 0 +Line 2453: 0 +Line 2454: 0 +Line 2455: 0 +Line 2456: 0 +Line 2457: 0 +Line 2458: 0 +Line 2459: 0 +Line 2460: 0 +Line 2461: 0 +Line 2462: 0 +Line 2463: 0 +Line 2464: 0 +Line 2465: 0 +Line 2466: 1 +Line 2467: 1 +Line 2468: 0 +Line 2469: 1 +Line 2470: 0 +Line 2471: 1 +Line 2472: 1 +Line 2473: 1 +Line 2474: 1 +Line 2475: 0 +Line 2476: 1 +Line 2477: 1 +Line 2478: 1 +Line 2479: 0 +Line 2480: 0 +Line 2481: 0 +Line 2482: 0 +Line 2483: 0 +Line 2484: 0 +Line 2485: 0 +Line 2486: 0 +Line 2487: 0 +Line 2488: 0 +Line 2489: 0 +Line 2490: 0 +Line 2491: 0 +Line 2492: 0 +Line 2493: 0 +Line 2494: 0 +Line 2495: 0 +Line 2496: 0 +Line 2497: 0 +Line 2498: 1 +Line 2499: 1 +Line 2500: 0 +Line 2501: 1 +Line 2502: 1 +Line 2503: 0 +Line 2504: 1 +Line 2505: 1 +Line 2506: 0 +Line 2507: 1 +Line 2508: 0 +Line 2509: 0 +Line 2510: 0 +Line 2511: 0 +Line 2512: 0 +Line 2513: 0 +Line 2514: 0 +Line 2515: 0 +Line 2516: 0 +Line 2517: 0 +Line 2518: 0 +Line 2519: 0 +Line 2520: 0 +Line 2521: 0 +Line 2522: 0 +Line 2523: 0 +Line 2524: 0 +Line 2525: 0 +Line 2526: 0 +Line 2527: 0 +Line 2528: 0 +Line 2529: 0 +Line 2530: 1 +Line 2531: 1 +Line 2532: 0 +Line 2533: 1 +Line 2534: 1 +Line 2535: 1 +Line 2536: 1 +Line 2537: 0 +Line 2538: 1 +Line 2539: 0 +Line 2540: 1 +Line 2541: 0 +Line 2542: 1 +Line 2543: 1 +Line 2544: 0 +Line 2545: 0 +Line 2546: 0 +Line 2547: 0 +Line 2548: 0 +Line 2549: 0 +Line 2550: 0 +Line 2551: 0 +Line 2552: 0 +Line 2553: 0 +Line 2554: 0 +Line 2555: 0 +Line 2556: 0 +Line 2557: 0 +Line 2558: 0 +Line 2559: 0 +Line 2560: 0 +Line 2561: 0 +Line 2562: 1 +Line 2563: 1 +Line 2564: 1 +Line 2565: 0 +Line 2566: 0 +Line 2567: 0 +Line 2568: 0 +Line 2569: 1 +Line 2570: 1 +Line 2571: 1 +Line 2572: 1 +Line 2573: 1 +Line 2574: 1 +Line 2575: 0 +Line 2576: 0 +Line 2577: 0 +Line 2578: 0 +Line 2579: 0 +Line 2580: 0 +Line 2581: 0 +Line 2582: 0 +Line 2583: 0 +Line 2584: 0 +Line 2585: 0 +Line 2586: 0 +Line 2587: 0 +Line 2588: 0 +Line 2589: 0 +Line 2590: 0 +Line 2591: 0 +Line 2592: 0 +Line 2593: 0 +Line 2594: 1 +Line 2595: 1 +Line 2596: 1 +Line 2597: 0 +Line 2598: 0 +Line 2599: 1 +Line 2600: 0 +Line 2601: 1 +Line 2602: 0 +Line 2603: 0 +Line 2604: 1 +Line 2605: 0 +Line 2606: 1 +Line 2607: 0 +Line 2608: 0 +Line 2609: 0 +Line 2610: 0 +Line 2611: 0 +Line 2612: 0 +Line 2613: 0 +Line 2614: 0 +Line 2615: 0 +Line 2616: 0 +Line 2617: 0 +Line 2618: 0 +Line 2619: 0 +Line 2620: 0 +Line 2621: 0 +Line 2622: 0 +Line 2623: 0 +Line 2624: 0 +Line 2625: 0 +Line 2626: 1 +Line 2627: 1 +Line 2628: 1 +Line 2629: 0 +Line 2630: 1 +Line 2631: 0 +Line 2632: 0 +Line 2633: 0 +Line 2634: 0 +Line 2635: 0 +Line 2636: 1 +Line 2637: 1 +Line 2638: 1 +Line 2639: 1 +Line 2640: 0 +Line 2641: 0 +Line 2642: 0 +Line 2643: 0 +Line 2644: 0 +Line 2645: 0 +Line 2646: 0 +Line 2647: 0 +Line 2648: 0 +Line 2649: 0 +Line 2650: 0 +Line 2651: 0 +Line 2652: 0 +Line 2653: 0 +Line 2654: 0 +Line 2655: 0 +Line 2656: 0 +Line 2657: 0 +Line 2658: 1 +Line 2659: 1 +Line 2660: 1 +Line 2661: 0 +Line 2662: 1 +Line 2663: 0 +Line 2664: 1 +Line 2665: 1 +Line 2666: 0 +Line 2667: 0 +Line 2668: 1 +Line 2669: 1 +Line 2670: 0 +Line 2671: 0 +Line 2672: 0 +Line 2673: 0 +Line 2674: 0 +Line 2675: 0 +Line 2676: 0 +Line 2677: 0 +Line 2678: 0 +Line 2679: 0 +Line 2680: 0 +Line 2681: 0 +Line 2682: 0 +Line 2683: 0 +Line 2684: 0 +Line 2685: 0 +Line 2686: 0 +Line 2687: 0 +Line 2688: 0 +Line 2689: 0 +Line 2690: 1 +Line 2691: 1 +Line 2692: 1 +Line 2693: 0 +Line 2694: 1 +Line 2695: 1 +Line 2696: 1 +Line 2697: 0 +Line 2698: 0 +Line 2699: 0 +Line 2700: 0 +Line 2701: 0 +Line 2702: 0 +Line 2703: 1 +Line 2704: 0 +Line 2705: 0 +Line 2706: 0 +Line 2707: 0 +Line 2708: 0 +Line 2709: 0 +Line 2710: 0 +Line 2711: 0 +Line 2712: 0 +Line 2713: 0 +Line 2714: 0 +Line 2715: 0 +Line 2716: 0 +Line 2717: 0 +Line 2718: 0 +Line 2719: 0 +Line 2720: 0 +Line 2721: 0 +Line 2722: 1 +Line 2723: 1 +Line 2724: 1 +Line 2725: 1 +Line 2726: 0 +Line 2727: 0 +Line 2728: 0 +Line 2729: 0 +Line 2730: 1 +Line 2731: 0 +Line 2732: 1 +Line 2733: 1 +Line 2734: 1 +Line 2735: 1 +Line 2736: 0 +Line 2737: 0 +Line 2738: 0 +Line 2739: 0 +Line 2740: 0 +Line 2741: 0 +Line 2742: 0 +Line 2743: 0 +Line 2744: 0 +Line 2745: 0 +Line 2746: 0 +Line 2747: 0 +Line 2748: 0 +Line 2749: 0 +Line 2750: 0 +Line 2751: 0 +Line 2752: 0 +Line 2753: 0 +Line 2754: 1 +Line 2755: 1 +Line 2756: 1 +Line 2757: 1 +Line 2758: 0 +Line 2759: 0 +Line 2760: 1 +Line 2761: 1 +Line 2762: 0 +Line 2763: 1 +Line 2764: 0 +Line 2765: 1 +Line 2766: 1 +Line 2767: 0 +Line 2768: 0 +Line 2769: 0 +Line 2770: 0 +Line 2771: 0 +Line 2772: 0 +Line 2773: 0 +Line 2774: 0 +Line 2775: 0 +Line 2776: 0 +Line 2777: 0 +Line 2778: 0 +Line 2779: 0 +Line 2780: 0 +Line 2781: 0 +Line 2782: 0 +Line 2783: 0 +Line 2784: 0 +Line 2785: 0 +Line 2786: 1 +Line 2787: 1 +Line 2788: 1 +Line 2789: 1 +Line 2790: 0 +Line 2791: 1 +Line 2792: 0 +Line 2793: 1 +Line 2794: 1 +Line 2795: 1 +Line 2796: 0 +Line 2797: 1 +Line 2798: 0 +Line 2799: 1 +Line 2800: 0 +Line 2801: 0 +Line 2802: 0 +Line 2803: 0 +Line 2804: 0 +Line 2805: 0 +Line 2806: 0 +Line 2807: 0 +Line 2808: 0 +Line 2809: 0 +Line 2810: 0 +Line 2811: 0 +Line 2812: 0 +Line 2813: 0 +Line 2814: 0 +Line 2815: 0 +Line 2816: 0 +Line 2817: 0 +Line 2818: 1 +Line 2819: 1 +Line 2820: 1 +Line 2821: 1 +Line 2822: 1 +Line 2823: 0 +Line 2824: 0 +Line 2825: 0 +Line 2826: 0 +Line 2827: 0 +Line 2828: 1 +Line 2829: 1 +Line 2830: 0 +Line 2831: 0 +Line 2832: 0 +Line 2833: 0 +Line 2834: 0 +Line 2835: 0 +Line 2836: 0 +Line 2837: 0 +Line 2838: 0 +Line 2839: 0 +Line 2840: 0 +Line 2841: 0 +Line 2842: 0 +Line 2843: 0 +Line 2844: 0 +Line 2845: 0 +Line 2846: 0 +Line 2847: 0 +Line 2848: 0 +Line 2849: 0 +Line 2850: 1 +Line 2851: 1 +Line 2852: 1 +Line 2853: 1 +Line 2854: 1 +Line 2855: 0 +Line 2856: 1 +Line 2857: 0 +Line 2858: 0 +Line 2859: 1 +Line 2860: 1 +Line 2861: 1 +Line 2862: 0 +Line 2863: 0 +Line 2864: 0 +Line 2865: 0 +Line 2866: 0 +Line 2867: 0 +Line 2868: 0 +Line 2869: 0 +Line 2870: 0 +Line 2871: 0 +Line 2872: 0 +Line 2873: 0 +Line 2874: 0 +Line 2875: 0 +Line 2876: 0 +Line 2877: 0 +Line 2878: 0 +Line 2879: 0 +Line 2880: 0 +Line 2881: 0 +Line 2882: 1 +Line 2883: 1 +Line 2884: 1 +Line 2885: 1 +Line 2886: 1 +Line 2887: 1 +Line 2888: 0 +Line 2889: 0 +Line 2890: 1 +Line 2891: 0 +Line 2892: 0 +Line 2893: 1 +Line 2894: 0 +Line 2895: 1 +Line 2896: 0 +Line 2897: 0 +Line 2898: 0 +Line 2899: 0 +Line 2900: 0 +Line 2901: 0 +Line 2902: 0 +Line 2903: 0 +Line 2904: 0 +Line 2905: 0 +Line 2906: 0 +Line 2907: 0 +Line 2908: 0 +Line 2909: 0 +Line 2910: 0 +Line 2911: 0 +Line 2912: 0 +Line 2913: 0 +Line 2914: 1 +Line 2915: 1 +Line 2916: 1 +Line 2917: 1 +Line 2918: 1 +Line 2919: 1 +Line 2920: 1 +Line 2921: 0 +Line 2922: 1 +Line 2923: 0 +Line 2924: 0 +Line 2925: 1 +Line 2926: 1 +Line 2927: 1 +Line 2928: 0 +Line 2929: 0 +Line 2930: 0 +Line 2931: 0 +Line 2932: 0 +Line 2933: 0 +Line 2934: 0 +Line 2935: 0 +Line 2936: 0 +Line 2937: 0 +Line 2938: 0 +Line 2939: 0 +Line 2940: 0 +Line 2941: 0 +Line 2942: 0 +Line 2943: 0 +Line 2944: 0 +Line 2945: 1 +Line 2946: 0 +Line 2947: 0 +Line 2948: 0 +Line 2949: 0 +Line 2950: 0 +Line 2951: 0 +Line 2952: 0 +Line 2953: 0 +Line 2954: 1 +Line 2955: 0 +Line 2956: 0 +Line 2957: 0 +Line 2958: 1 +Line 2959: 0 +Line 2960: 0 +Line 2961: 0 +Line 2962: 0 +Line 2963: 0 +Line 2964: 0 +Line 2965: 0 +Line 2966: 0 +Line 2967: 0 +Line 2968: 0 +Line 2969: 0 +Line 2970: 0 +Line 2971: 0 +Line 2972: 0 +Line 2973: 0 +Line 2974: 0 +Line 2975: 0 +Line 2976: 0 +Line 2977: 1 +Line 2978: 0 +Line 2979: 0 +Line 2980: 0 +Line 2981: 0 +Line 2982: 0 +Line 2983: 0 +Line 2984: 1 +Line 2985: 0 +Line 2986: 0 +Line 2987: 1 +Line 2988: 0 +Line 2989: 1 +Line 2990: 1 +Line 2991: 1 +Line 2992: 0 +Line 2993: 0 +Line 2994: 0 +Line 2995: 0 +Line 2996: 0 +Line 2997: 0 +Line 2998: 0 +Line 2999: 0 +Line 3000: 0 +Line 3001: 0 +Line 3002: 0 +Line 3003: 0 +Line 3004: 0 +Line 3005: 0 +Line 3006: 0 +Line 3007: 0 +Line 3008: 0 +Line 3009: 1 +Line 3010: 0 +Line 3011: 0 +Line 3012: 0 +Line 3013: 0 +Line 3014: 0 +Line 3015: 1 +Line 3016: 0 +Line 3017: 0 +Line 3018: 0 +Line 3019: 0 +Line 3020: 0 +Line 3021: 1 +Line 3022: 0 +Line 3023: 0 +Line 3024: 0 +Line 3025: 0 +Line 3026: 0 +Line 3027: 0 +Line 3028: 0 +Line 3029: 0 +Line 3030: 0 +Line 3031: 0 +Line 3032: 0 +Line 3033: 0 +Line 3034: 0 +Line 3035: 0 +Line 3036: 0 +Line 3037: 0 +Line 3038: 0 +Line 3039: 0 +Line 3040: 0 +Line 3041: 1 +Line 3042: 0 +Line 3043: 0 +Line 3044: 0 +Line 3045: 0 +Line 3046: 0 +Line 3047: 1 +Line 3048: 0 +Line 3049: 1 +Line 3050: 1 +Line 3051: 0 +Line 3052: 1 +Line 3053: 1 +Line 3054: 0 +Line 3055: 0 +Line 3056: 0 +Line 3057: 0 +Line 3058: 0 +Line 3059: 0 +Line 3060: 0 +Line 3061: 0 +Line 3062: 0 +Line 3063: 0 +Line 3064: 0 +Line 3065: 0 +Line 3066: 0 +Line 3067: 0 +Line 3068: 0 +Line 3069: 0 +Line 3070: 0 +Line 3071: 0 +Line 3072: 0 +Line 3073: 1 +Line 3074: 0 +Line 3075: 0 +Line 3076: 0 +Line 3077: 0 +Line 3078: 0 +Line 3079: 1 +Line 3080: 0 +Line 3081: 1 +Line 3082: 1 +Line 3083: 0 +Line 3084: 1 +Line 3085: 1 +Line 3086: 0 +Line 3087: 0 +Line 3088: 0 +Line 3089: 0 +Line 3090: 0 +Line 3091: 0 +Line 3092: 0 +Line 3093: 0 +Line 3094: 0 +Line 3095: 0 +Line 3096: 0 +Line 3097: 0 +Line 3098: 0 +Line 3099: 0 +Line 3100: 0 +Line 3101: 0 +Line 3102: 0 +Line 3103: 0 +Line 3104: 0 +Line 3105: 1 +Line 3106: 0 +Line 3107: 0 +Line 3108: 0 +Line 3109: 0 +Line 3110: 0 +Line 3111: 1 +Line 3112: 0 +Line 3113: 0 +Line 3114: 0 +Line 3115: 0 +Line 3116: 0 +Line 3117: 1 +Line 3118: 0 +Line 3119: 0 +Line 3120: 0 +Line 3121: 0 +Line 3122: 0 +Line 3123: 0 +Line 3124: 0 +Line 3125: 0 +Line 3126: 0 +Line 3127: 0 +Line 3128: 0 +Line 3129: 0 +Line 3130: 0 +Line 3131: 0 +Line 3132: 0 +Line 3133: 0 +Line 3134: 0 +Line 3135: 0 +Line 3136: 0 +Line 3137: 1 +Line 3138: 0 +Line 3139: 0 +Line 3140: 0 +Line 3141: 0 +Line 3142: 0 +Line 3143: 0 +Line 3144: 1 +Line 3145: 0 +Line 3146: 0 +Line 3147: 1 +Line 3148: 0 +Line 3149: 1 +Line 3150: 1 +Line 3151: 1 +Line 3152: 0 +Line 3153: 0 +Line 3154: 0 +Line 3155: 0 +Line 3156: 0 +Line 3157: 0 +Line 3158: 0 +Line 3159: 0 +Line 3160: 0 +Line 3161: 0 +Line 3162: 0 +Line 3163: 0 +Line 3164: 0 +Line 3165: 0 +Line 3166: 0 +Line 3167: 0 +Line 3168: 0 +Line 3169: 1 +Line 3170: 0 +Line 3171: 0 +Line 3172: 0 +Line 3173: 0 +Line 3174: 0 +Line 3175: 0 +Line 3176: 0 +Line 3177: 0 +Line 3178: 1 +Line 3179: 0 +Line 3180: 0 +Line 3181: 0 +Line 3182: 1 +Line 3183: 0 +Line 3184: 0 +Line 3185: 0 +Line 3186: 0 +Line 3187: 0 +Line 3188: 0 +Line 3189: 0 +Line 3190: 0 +Line 3191: 0 +Line 3192: 0 +Line 3193: 0 +Line 3194: 0 +Line 3195: 0 +Line 3196: 0 +Line 3197: 0 +Line 3198: 0 +Line 3199: 0 +Line 3200: 0 +Line 3201: 0 +Line 3202: 1 +Line 3203: 1 +Line 3204: 1 +Line 3205: 1 +Line 3206: 1 +Line 3207: 1 +Line 3208: 1 +Line 3209: 0 +Line 3210: 1 +Line 3211: 0 +Line 3212: 0 +Line 3213: 1 +Line 3214: 1 +Line 3215: 1 +Line 3216: 0 +Line 3217: 0 +Line 3218: 0 +Line 3219: 0 +Line 3220: 0 +Line 3221: 0 +Line 3222: 0 +Line 3223: 0 +Line 3224: 0 +Line 3225: 0 +Line 3226: 0 +Line 3227: 0 +Line 3228: 0 +Line 3229: 0 +Line 3230: 0 +Line 3231: 0 +Line 3232: 0 +Line 3233: 0 +Line 3234: 1 +Line 3235: 1 +Line 3236: 1 +Line 3237: 1 +Line 3238: 1 +Line 3239: 1 +Line 3240: 0 +Line 3241: 0 +Line 3242: 1 +Line 3243: 0 +Line 3244: 0 +Line 3245: 1 +Line 3246: 0 +Line 3247: 1 +Line 3248: 0 +Line 3249: 0 +Line 3250: 0 +Line 3251: 0 +Line 3252: 0 +Line 3253: 0 +Line 3254: 0 +Line 3255: 0 +Line 3256: 0 +Line 3257: 0 +Line 3258: 0 +Line 3259: 0 +Line 3260: 0 +Line 3261: 0 +Line 3262: 0 +Line 3263: 0 +Line 3264: 0 +Line 3265: 0 +Line 3266: 1 +Line 3267: 1 +Line 3268: 1 +Line 3269: 1 +Line 3270: 1 +Line 3271: 0 +Line 3272: 1 +Line 3273: 0 +Line 3274: 0 +Line 3275: 1 +Line 3276: 1 +Line 3277: 1 +Line 3278: 0 +Line 3279: 0 +Line 3280: 0 +Line 3281: 0 +Line 3282: 0 +Line 3283: 0 +Line 3284: 0 +Line 3285: 0 +Line 3286: 0 +Line 3287: 0 +Line 3288: 0 +Line 3289: 0 +Line 3290: 0 +Line 3291: 0 +Line 3292: 0 +Line 3293: 0 +Line 3294: 0 +Line 3295: 0 +Line 3296: 0 +Line 3297: 0 +Line 3298: 1 +Line 3299: 1 +Line 3300: 1 +Line 3301: 1 +Line 3302: 1 +Line 3303: 0 +Line 3304: 0 +Line 3305: 0 +Line 3306: 0 +Line 3307: 0 +Line 3308: 1 +Line 3309: 1 +Line 3310: 0 +Line 3311: 0 +Line 3312: 0 +Line 3313: 0 +Line 3314: 0 +Line 3315: 0 +Line 3316: 0 +Line 3317: 0 +Line 3318: 0 +Line 3319: 0 +Line 3320: 0 +Line 3321: 0 +Line 3322: 0 +Line 3323: 0 +Line 3324: 0 +Line 3325: 0 +Line 3326: 0 +Line 3327: 0 +Line 3328: 0 +Line 3329: 0 +Line 3330: 1 +Line 3331: 1 +Line 3332: 1 +Line 3333: 1 +Line 3334: 0 +Line 3335: 1 +Line 3336: 0 +Line 3337: 1 +Line 3338: 1 +Line 3339: 1 +Line 3340: 0 +Line 3341: 1 +Line 3342: 0 +Line 3343: 1 +Line 3344: 0 +Line 3345: 0 +Line 3346: 0 +Line 3347: 0 +Line 3348: 0 +Line 3349: 0 +Line 3350: 0 +Line 3351: 0 +Line 3352: 0 +Line 3353: 0 +Line 3354: 0 +Line 3355: 0 +Line 3356: 0 +Line 3357: 0 +Line 3358: 0 +Line 3359: 0 +Line 3360: 0 +Line 3361: 0 +Line 3362: 1 +Line 3363: 1 +Line 3364: 1 +Line 3365: 1 +Line 3366: 0 +Line 3367: 0 +Line 3368: 1 +Line 3369: 1 +Line 3370: 0 +Line 3371: 1 +Line 3372: 0 +Line 3373: 1 +Line 3374: 1 +Line 3375: 0 +Line 3376: 0 +Line 3377: 0 +Line 3378: 0 +Line 3379: 0 +Line 3380: 0 +Line 3381: 0 +Line 3382: 0 +Line 3383: 0 +Line 3384: 0 +Line 3385: 0 +Line 3386: 0 +Line 3387: 0 +Line 3388: 0 +Line 3389: 0 +Line 3390: 0 +Line 3391: 0 +Line 3392: 0 +Line 3393: 0 +Line 3394: 1 +Line 3395: 1 +Line 3396: 1 +Line 3397: 1 +Line 3398: 0 +Line 3399: 0 +Line 3400: 0 +Line 3401: 0 +Line 3402: 1 +Line 3403: 0 +Line 3404: 1 +Line 3405: 1 +Line 3406: 1 +Line 3407: 1 +Line 3408: 0 +Line 3409: 0 +Line 3410: 0 +Line 3411: 0 +Line 3412: 0 +Line 3413: 0 +Line 3414: 0 +Line 3415: 0 +Line 3416: 0 +Line 3417: 0 +Line 3418: 0 +Line 3419: 0 +Line 3420: 0 +Line 3421: 0 +Line 3422: 0 +Line 3423: 0 +Line 3424: 0 +Line 3425: 0 +Line 3426: 1 +Line 3427: 1 +Line 3428: 1 +Line 3429: 0 +Line 3430: 1 +Line 3431: 1 +Line 3432: 1 +Line 3433: 0 +Line 3434: 0 +Line 3435: 0 +Line 3436: 0 +Line 3437: 0 +Line 3438: 0 +Line 3439: 1 +Line 3440: 0 +Line 3441: 0 +Line 3442: 0 +Line 3443: 0 +Line 3444: 0 +Line 3445: 0 +Line 3446: 0 +Line 3447: 0 +Line 3448: 0 +Line 3449: 0 +Line 3450: 0 +Line 3451: 0 +Line 3452: 0 +Line 3453: 0 +Line 3454: 0 +Line 3455: 0 +Line 3456: 0 +Line 3457: 0 +Line 3458: 1 +Line 3459: 1 +Line 3460: 1 +Line 3461: 0 +Line 3462: 1 +Line 3463: 0 +Line 3464: 1 +Line 3465: 1 +Line 3466: 0 +Line 3467: 0 +Line 3468: 1 +Line 3469: 1 +Line 3470: 0 +Line 3471: 0 +Line 3472: 0 +Line 3473: 0 +Line 3474: 0 +Line 3475: 0 +Line 3476: 0 +Line 3477: 0 +Line 3478: 0 +Line 3479: 0 +Line 3480: 0 +Line 3481: 0 +Line 3482: 0 +Line 3483: 0 +Line 3484: 0 +Line 3485: 0 +Line 3486: 0 +Line 3487: 0 +Line 3488: 0 +Line 3489: 0 +Line 3490: 1 +Line 3491: 1 +Line 3492: 1 +Line 3493: 0 +Line 3494: 1 +Line 3495: 0 +Line 3496: 0 +Line 3497: 0 +Line 3498: 0 +Line 3499: 0 +Line 3500: 1 +Line 3501: 1 +Line 3502: 1 +Line 3503: 1 +Line 3504: 0 +Line 3505: 0 +Line 3506: 0 +Line 3507: 0 +Line 3508: 0 +Line 3509: 0 +Line 3510: 0 +Line 3511: 0 +Line 3512: 0 +Line 3513: 0 +Line 3514: 0 +Line 3515: 0 +Line 3516: 0 +Line 3517: 0 +Line 3518: 0 +Line 3519: 0 +Line 3520: 0 +Line 3521: 0 +Line 3522: 1 +Line 3523: 1 +Line 3524: 1 +Line 3525: 0 +Line 3526: 0 +Line 3527: 1 +Line 3528: 0 +Line 3529: 1 +Line 3530: 0 +Line 3531: 0 +Line 3532: 1 +Line 3533: 0 +Line 3534: 1 +Line 3535: 0 +Line 3536: 0 +Line 3537: 0 +Line 3538: 0 +Line 3539: 0 +Line 3540: 0 +Line 3541: 0 +Line 3542: 0 +Line 3543: 0 +Line 3544: 0 +Line 3545: 0 +Line 3546: 0 +Line 3547: 0 +Line 3548: 0 +Line 3549: 0 +Line 3550: 0 +Line 3551: 0 +Line 3552: 0 +Line 3553: 0 +Line 3554: 1 +Line 3555: 1 +Line 3556: 1 +Line 3557: 0 +Line 3558: 0 +Line 3559: 0 +Line 3560: 0 +Line 3561: 1 +Line 3562: 1 +Line 3563: 1 +Line 3564: 1 +Line 3565: 1 +Line 3566: 1 +Line 3567: 0 +Line 3568: 0 +Line 3569: 0 +Line 3570: 0 +Line 3571: 0 +Line 3572: 0 +Line 3573: 0 +Line 3574: 0 +Line 3575: 0 +Line 3576: 0 +Line 3577: 0 +Line 3578: 0 +Line 3579: 0 +Line 3580: 0 +Line 3581: 0 +Line 3582: 0 +Line 3583: 0 +Line 3584: 0 +Line 3585: 0 +Line 3586: 1 +Line 3587: 1 +Line 3588: 0 +Line 3589: 1 +Line 3590: 1 +Line 3591: 1 +Line 3592: 1 +Line 3593: 0 +Line 3594: 1 +Line 3595: 0 +Line 3596: 1 +Line 3597: 0 +Line 3598: 1 +Line 3599: 1 +Line 3600: 0 +Line 3601: 0 +Line 3602: 0 +Line 3603: 0 +Line 3604: 0 +Line 3605: 0 +Line 3606: 0 +Line 3607: 0 +Line 3608: 0 +Line 3609: 0 +Line 3610: 0 +Line 3611: 0 +Line 3612: 0 +Line 3613: 0 +Line 3614: 0 +Line 3615: 0 +Line 3616: 0 +Line 3617: 0 +Line 3618: 1 +Line 3619: 1 +Line 3620: 0 +Line 3621: 1 +Line 3622: 1 +Line 3623: 0 +Line 3624: 1 +Line 3625: 1 +Line 3626: 0 +Line 3627: 1 +Line 3628: 0 +Line 3629: 0 +Line 3630: 0 +Line 3631: 0 +Line 3632: 0 +Line 3633: 0 +Line 3634: 0 +Line 3635: 0 +Line 3636: 0 +Line 3637: 0 +Line 3638: 0 +Line 3639: 0 +Line 3640: 0 +Line 3641: 0 +Line 3642: 0 +Line 3643: 0 +Line 3644: 0 +Line 3645: 0 +Line 3646: 0 +Line 3647: 0 +Line 3648: 0 +Line 3649: 0 +Line 3650: 1 +Line 3651: 1 +Line 3652: 0 +Line 3653: 1 +Line 3654: 0 +Line 3655: 1 +Line 3656: 1 +Line 3657: 1 +Line 3658: 1 +Line 3659: 0 +Line 3660: 1 +Line 3661: 1 +Line 3662: 1 +Line 3663: 0 +Line 3664: 0 +Line 3665: 0 +Line 3666: 0 +Line 3667: 0 +Line 3668: 0 +Line 3669: 0 +Line 3670: 0 +Line 3671: 0 +Line 3672: 0 +Line 3673: 0 +Line 3674: 0 +Line 3675: 0 +Line 3676: 0 +Line 3677: 0 +Line 3678: 0 +Line 3679: 0 +Line 3680: 0 +Line 3681: 0 +Line 3682: 1 +Line 3683: 1 +Line 3684: 0 +Line 3685: 1 +Line 3686: 0 +Line 3687: 1 +Line 3688: 0 +Line 3689: 0 +Line 3690: 0 +Line 3691: 0 +Line 3692: 0 +Line 3693: 1 +Line 3694: 1 +Line 3695: 0 +Line 3696: 0 +Line 3697: 0 +Line 3698: 0 +Line 3699: 0 +Line 3700: 0 +Line 3701: 0 +Line 3702: 0 +Line 3703: 0 +Line 3704: 0 +Line 3705: 0 +Line 3706: 0 +Line 3707: 0 +Line 3708: 0 +Line 3709: 0 +Line 3710: 0 +Line 3711: 0 +Line 3712: 0 +Line 3713: 0 +Line 3714: 1 +Line 3715: 1 +Line 3716: 0 +Line 3717: 1 +Line 3718: 0 +Line 3719: 0 +Line 3720: 0 +Line 3721: 0 +Line 3722: 0 +Line 3723: 1 +Line 3724: 0 +Line 3725: 1 +Line 3726: 1 +Line 3727: 0 +Line 3728: 0 +Line 3729: 0 +Line 3730: 0 +Line 3731: 0 +Line 3732: 0 +Line 3733: 0 +Line 3734: 0 +Line 3735: 0 +Line 3736: 0 +Line 3737: 0 +Line 3738: 0 +Line 3739: 0 +Line 3740: 0 +Line 3741: 0 +Line 3742: 0 +Line 3743: 0 +Line 3744: 0 +Line 3745: 0 +Line 3746: 1 +Line 3747: 1 +Line 3748: 0 +Line 3749: 0 +Line 3750: 1 +Line 3751: 1 +Line 3752: 0 +Line 3753: 0 +Line 3754: 1 +Line 3755: 0 +Line 3756: 0 +Line 3757: 0 +Line 3758: 0 +Line 3759: 0 +Line 3760: 0 +Line 3761: 0 +Line 3762: 0 +Line 3763: 0 +Line 3764: 0 +Line 3765: 0 +Line 3766: 0 +Line 3767: 0 +Line 3768: 0 +Line 3769: 0 +Line 3770: 0 +Line 3771: 0 +Line 3772: 0 +Line 3773: 0 +Line 3774: 0 +Line 3775: 0 +Line 3776: 0 +Line 3777: 0 +Line 3778: 1 +Line 3779: 1 +Line 3780: 0 +Line 3781: 0 +Line 3782: 1 +Line 3783: 0 +Line 3784: 0 +Line 3785: 0 +Line 3786: 1 +Line 3787: 0 +Line 3788: 0 +Line 3789: 1 +Line 3790: 0 +Line 3791: 0 +Line 3792: 0 +Line 3793: 0 +Line 3794: 0 +Line 3795: 0 +Line 3796: 0 +Line 3797: 0 +Line 3798: 0 +Line 3799: 0 +Line 3800: 0 +Line 3801: 0 +Line 3802: 0 +Line 3803: 0 +Line 3804: 0 +Line 3805: 0 +Line 3806: 0 +Line 3807: 0 +Line 3808: 0 +Line 3809: 0 +Line 3810: 1 +Line 3811: 1 +Line 3812: 0 +Line 3813: 0 +Line 3814: 0 +Line 3815: 1 +Line 3816: 0 +Line 3817: 0 +Line 3818: 1 +Line 3819: 0 +Line 3820: 0 +Line 3821: 0 +Line 3822: 0 +Line 3823: 1 +Line 3824: 0 +Line 3825: 0 +Line 3826: 0 +Line 3827: 0 +Line 3828: 0 +Line 3829: 0 +Line 3830: 0 +Line 3831: 0 +Line 3832: 0 +Line 3833: 0 +Line 3834: 0 +Line 3835: 0 +Line 3836: 0 +Line 3837: 0 +Line 3838: 0 +Line 3839: 0 +Line 3840: 0 +Line 3841: 0 +Line 3842: 1 +Line 3843: 1 +Line 3844: 0 +Line 3845: 0 +Line 3846: 0 +Line 3847: 0 +Line 3848: 0 +Line 3849: 0 +Line 3850: 0 +Line 3851: 1 +Line 3852: 1 +Line 3853: 0 +Line 3854: 0 +Line 3855: 1 +Line 3856: 0 +Line 3857: 0 +Line 3858: 0 +Line 3859: 0 +Line 3860: 0 +Line 3861: 0 +Line 3862: 0 +Line 3863: 0 +Line 3864: 0 +Line 3865: 0 +Line 3866: 0 +Line 3867: 0 +Line 3868: 0 +Line 3869: 0 +Line 3870: 0 +Line 3871: 0 +Line 3872: 0 +Line 3873: 0 +Line 3874: 1 +Line 3875: 0 +Line 3876: 1 +Line 3877: 1 +Line 3878: 1 +Line 3879: 1 +Line 3880: 0 +Line 3881: 0 +Line 3882: 0 +Line 3883: 0 +Line 3884: 1 +Line 3885: 1 +Line 3886: 0 +Line 3887: 0 +Line 3888: 0 +Line 3889: 0 +Line 3890: 0 +Line 3891: 0 +Line 3892: 0 +Line 3893: 0 +Line 3894: 0 +Line 3895: 0 +Line 3896: 0 +Line 3897: 0 +Line 3898: 0 +Line 3899: 0 +Line 3900: 0 +Line 3901: 0 +Line 3902: 0 +Line 3903: 0 +Line 3904: 0 +Line 3905: 0 +Line 3906: 1 +Line 3907: 0 +Line 3908: 1 +Line 3909: 1 +Line 3910: 0 +Line 3911: 1 +Line 3912: 1 +Line 3913: 1 +Line 3914: 1 +Line 3915: 1 +Line 3916: 1 +Line 3917: 0 +Line 3918: 0 +Line 3919: 1 +Line 3920: 0 +Line 3921: 0 +Line 3922: 0 +Line 3923: 0 +Line 3924: 0 +Line 3925: 0 +Line 3926: 0 +Line 3927: 0 +Line 3928: 0 +Line 3929: 0 +Line 3930: 0 +Line 3931: 0 +Line 3932: 0 +Line 3933: 0 +Line 3934: 0 +Line 3935: 0 +Line 3936: 0 +Line 3937: 0 +Line 3938: 1 +Line 3939: 0 +Line 3940: 1 +Line 3941: 1 +Line 3942: 0 +Line 3943: 0 +Line 3944: 1 +Line 3945: 1 +Line 3946: 1 +Line 3947: 0 +Line 3948: 0 +Line 3949: 0 +Line 3950: 1 +Line 3951: 1 +Line 3952: 0 +Line 3953: 0 +Line 3954: 0 +Line 3955: 0 +Line 3956: 0 +Line 3957: 0 +Line 3958: 0 +Line 3959: 0 +Line 3960: 0 +Line 3961: 0 +Line 3962: 0 +Line 3963: 0 +Line 3964: 0 +Line 3965: 0 +Line 3966: 0 +Line 3967: 0 +Line 3968: 0 +Line 3969: 0 +Line 3970: 1 +Line 3971: 0 +Line 3972: 1 +Line 3973: 0 +Line 3974: 1 +Line 3975: 1 +Line 3976: 1 +Line 3977: 1 +Line 3978: 0 +Line 3979: 0 +Line 3980: 1 +Line 3981: 0 +Line 3982: 0 +Line 3983: 0 +Line 3984: 0 +Line 3985: 0 +Line 3986: 0 +Line 3987: 0 +Line 3988: 0 +Line 3989: 0 +Line 3990: 0 +Line 3991: 0 +Line 3992: 0 +Line 3993: 0 +Line 3994: 0 +Line 3995: 0 +Line 3996: 0 +Line 3997: 0 +Line 3998: 0 +Line 3999: 0 +Line 4000: 0 +Line 4001: 0 +Line 4002: 1 +Line 4003: 0 +Line 4004: 1 +Line 4005: 0 +Line 4006: 1 +Line 4007: 0 +Line 4008: 1 +Line 4009: 0 +Line 4010: 1 +Line 4011: 0 +Line 4012: 1 +Line 4013: 0 +Line 4014: 0 +Line 4015: 1 +Line 4016: 0 +Line 4017: 0 +Line 4018: 0 +Line 4019: 0 +Line 4020: 0 +Line 4021: 0 +Line 4022: 0 +Line 4023: 0 +Line 4024: 0 +Line 4025: 0 +Line 4026: 0 +Line 4027: 0 +Line 4028: 0 +Line 4029: 0 +Line 4030: 0 +Line 4031: 0 +Line 4032: 0 +Line 4033: 0 +Line 4034: 1 +Line 4035: 0 +Line 4036: 1 +Line 4037: 0 +Line 4038: 0 +Line 4039: 1 +Line 4040: 1 +Line 4041: 0 +Line 4042: 0 +Line 4043: 0 +Line 4044: 0 +Line 4045: 1 +Line 4046: 1 +Line 4047: 1 +Line 4048: 0 +Line 4049: 0 +Line 4050: 0 +Line 4051: 0 +Line 4052: 0 +Line 4053: 0 +Line 4054: 0 +Line 4055: 0 +Line 4056: 0 +Line 4057: 0 +Line 4058: 0 +Line 4059: 0 +Line 4060: 0 +Line 4061: 0 +Line 4062: 0 +Line 4063: 0 +Line 4064: 0 +Line 4065: 0 +Line 4066: 1 +Line 4067: 0 +Line 4068: 1 +Line 4069: 0 +Line 4070: 0 +Line 4071: 0 +Line 4072: 0 +Line 4073: 1 +Line 4074: 1 +Line 4075: 0 +Line 4076: 0 +Line 4077: 0 +Line 4078: 1 +Line 4079: 0 +Line 4080: 0 +Line 4081: 0 +Line 4082: 0 +Line 4083: 0 +Line 4084: 0 +Line 4085: 0 +Line 4086: 0 +Line 4087: 0 +Line 4088: 0 +Line 4089: 0 +Line 4090: 0 +Line 4091: 0 +Line 4092: 0 +Line 4093: 0 +Line 4094: 0 +Line 4095: 0 +Line 4096: 0 +Line 4097: 0 +Line 4098: 1 +Line 4099: 0 +Line 4100: 0 +Line 4101: 1 +Line 4102: 1 +Line 4103: 1 +Line 4104: 0 +Line 4105: 0 +Line 4106: 1 +Line 4107: 1 +Line 4108: 1 +Line 4109: 0 +Line 4110: 1 +Line 4111: 1 +Line 4112: 0 +Line 4113: 0 +Line 4114: 0 +Line 4115: 0 +Line 4116: 0 +Line 4117: 0 +Line 4118: 0 +Line 4119: 0 +Line 4120: 0 +Line 4121: 0 +Line 4122: 0 +Line 4123: 0 +Line 4124: 0 +Line 4125: 0 +Line 4126: 0 +Line 4127: 0 +Line 4128: 0 +Line 4129: 0 +Line 4130: 1 +Line 4131: 0 +Line 4132: 0 +Line 4133: 1 +Line 4134: 1 +Line 4135: 0 +Line 4136: 0 +Line 4137: 0 +Line 4138: 0 +Line 4139: 1 +Line 4140: 0 +Line 4141: 0 +Line 4142: 1 +Line 4143: 0 +Line 4144: 0 +Line 4145: 0 +Line 4146: 0 +Line 4147: 0 +Line 4148: 0 +Line 4149: 0 +Line 4150: 0 +Line 4151: 0 +Line 4152: 0 +Line 4153: 0 +Line 4154: 0 +Line 4155: 0 +Line 4156: 0 +Line 4157: 0 +Line 4158: 0 +Line 4159: 0 +Line 4160: 0 +Line 4161: 0 +Line 4162: 1 +Line 4163: 0 +Line 4164: 0 +Line 4165: 1 +Line 4166: 0 +Line 4167: 0 +Line 4168: 1 +Line 4169: 1 +Line 4170: 1 +Line 4171: 0 +Line 4172: 1 +Line 4173: 0 +Line 4174: 0 +Line 4175: 0 +Line 4176: 0 +Line 4177: 0 +Line 4178: 0 +Line 4179: 0 +Line 4180: 0 +Line 4181: 0 +Line 4182: 0 +Line 4183: 0 +Line 4184: 0 +Line 4185: 0 +Line 4186: 0 +Line 4187: 0 +Line 4188: 0 +Line 4189: 0 +Line 4190: 0 +Line 4191: 0 +Line 4192: 0 +Line 4193: 0 +Line 4194: 1 +Line 4195: 0 +Line 4196: 0 +Line 4197: 0 +Line 4198: 1 +Line 4199: 1 +Line 4200: 1 +Line 4201: 0 +Line 4202: 1 +Line 4203: 1 +Line 4204: 1 +Line 4205: 1 +Line 4206: 0 +Line 4207: 1 +Line 4208: 0 +Line 4209: 0 +Line 4210: 0 +Line 4211: 0 +Line 4212: 0 +Line 4213: 0 +Line 4214: 0 +Line 4215: 0 +Line 4216: 0 +Line 4217: 0 +Line 4218: 0 +Line 4219: 0 +Line 4220: 0 +Line 4221: 0 +Line 4222: 0 +Line 4223: 0 +Line 4224: 0 +Line 4225: 0 +Line 4226: 1 +Line 4227: 0 +Line 4228: 0 +Line 4229: 0 +Line 4230: 1 +Line 4231: 0 +Line 4232: 1 +Line 4233: 0 +Line 4234: 0 +Line 4235: 1 +Line 4236: 0 +Line 4237: 0 +Line 4238: 1 +Line 4239: 0 +Line 4240: 0 +Line 4241: 0 +Line 4242: 0 +Line 4243: 0 +Line 4244: 0 +Line 4245: 0 +Line 4246: 0 +Line 4247: 0 +Line 4248: 0 +Line 4249: 0 +Line 4250: 0 +Line 4251: 0 +Line 4252: 0 +Line 4253: 0 +Line 4254: 0 +Line 4255: 0 +Line 4256: 0 +Line 4257: 0 +Line 4258: 1 +Line 4259: 0 +Line 4260: 0 +Line 4261: 0 +Line 4262: 0 +Line 4263: 1 +Line 4264: 0 +Line 4265: 1 +Line 4266: 1 +Line 4267: 0 +Line 4268: 0 +Line 4269: 1 +Line 4270: 1 +Line 4271: 1 +Line 4272: 0 +Line 4273: 0 +Line 4274: 0 +Line 4275: 0 +Line 4276: 0 +Line 4277: 0 +Line 4278: 0 +Line 4279: 0 +Line 4280: 0 +Line 4281: 0 +Line 4282: 0 +Line 4283: 0 +Line 4284: 0 +Line 4285: 0 +Line 4286: 0 +Line 4287: 0 +Line 4288: 0 +Line 4289: 0 +Line 4290: 1 +Line 4291: 0 +Line 4292: 0 +Line 4293: 0 +Line 4294: 0 +Line 4295: 0 +Line 4296: 0 +Line 4297: 0 +Line 4298: 1 +Line 4299: 1 +Line 4300: 1 +Line 4301: 1 +Line 4302: 0 +Line 4303: 1 +Line 4304: 0 +Line 4305: 0 +Line 4306: 0 +Line 4307: 0 +Line 4308: 0 +Line 4309: 0 +Line 4310: 0 +Line 4311: 0 +Line 4312: 0 +Line 4313: 0 +Line 4314: 0 +Line 4315: 0 +Line 4316: 0 +Line 4317: 0 +Line 4318: 0 +Line 4319: 0 +Line 4320: 0 +Line 4321: 0 +Line 4322: 0 +Line 4323: 1 +Line 4324: 1 +Line 4325: 1 +Line 4326: 1 +Line 4327: 1 +Line 4328: 0 +Line 4329: 0 +Line 4330: 0 +Line 4331: 1 +Line 4332: 0 +Line 4333: 1 +Line 4334: 0 +Line 4335: 0 +Line 4336: 0 +Line 4337: 0 +Line 4338: 0 +Line 4339: 0 +Line 4340: 0 +Line 4341: 0 +Line 4342: 0 +Line 4343: 0 +Line 4344: 0 +Line 4345: 0 +Line 4346: 0 +Line 4347: 0 +Line 4348: 0 +Line 4349: 0 +Line 4350: 0 +Line 4351: 0 +Line 4352: 0 +Line 4353: 0 +Line 4354: 0 +Line 4355: 1 +Line 4356: 1 +Line 4357: 1 +Line 4358: 0 +Line 4359: 1 +Line 4360: 1 +Line 4361: 1 +Line 4362: 1 +Line 4363: 0 +Line 4364: 1 +Line 4365: 1 +Line 4366: 0 +Line 4367: 1 +Line 4368: 0 +Line 4369: 0 +Line 4370: 0 +Line 4371: 0 +Line 4372: 0 +Line 4373: 0 +Line 4374: 0 +Line 4375: 0 +Line 4376: 0 +Line 4377: 0 +Line 4378: 0 +Line 4379: 0 +Line 4380: 0 +Line 4381: 0 +Line 4382: 0 +Line 4383: 0 +Line 4384: 0 +Line 4385: 0 +Line 4386: 0 +Line 4387: 1 +Line 4388: 1 +Line 4389: 1 +Line 4390: 0 +Line 4391: 0 +Line 4392: 1 +Line 4393: 1 +Line 4394: 0 +Line 4395: 0 +Line 4396: 1 +Line 4397: 0 +Line 4398: 0 +Line 4399: 0 +Line 4400: 0 +Line 4401: 0 +Line 4402: 0 +Line 4403: 0 +Line 4404: 0 +Line 4405: 0 +Line 4406: 0 +Line 4407: 0 +Line 4408: 0 +Line 4409: 0 +Line 4410: 0 +Line 4411: 0 +Line 4412: 0 +Line 4413: 0 +Line 4414: 0 +Line 4415: 0 +Line 4416: 0 +Line 4417: 0 +Line 4418: 0 +Line 4419: 1 +Line 4420: 1 +Line 4421: 0 +Line 4422: 1 +Line 4423: 1 +Line 4424: 1 +Line 4425: 0 +Line 4426: 1 +Line 4427: 0 +Line 4428: 0 +Line 4429: 1 +Line 4430: 1 +Line 4431: 0 +Line 4432: 0 +Line 4433: 0 +Line 4434: 0 +Line 4435: 0 +Line 4436: 0 +Line 4437: 0 +Line 4438: 0 +Line 4439: 0 +Line 4440: 0 +Line 4441: 0 +Line 4442: 0 +Line 4443: 0 +Line 4444: 0 +Line 4445: 0 +Line 4446: 0 +Line 4447: 0 +Line 4448: 0 +Line 4449: 0 +Line 4450: 0 +Line 4451: 1 +Line 4452: 1 +Line 4453: 0 +Line 4454: 1 +Line 4455: 0 +Line 4456: 1 +Line 4457: 0 +Line 4458: 0 +Line 4459: 0 +Line 4460: 0 +Line 4461: 1 +Line 4462: 1 +Line 4463: 1 +Line 4464: 0 +Line 4465: 0 +Line 4466: 0 +Line 4467: 0 +Line 4468: 0 +Line 4469: 0 +Line 4470: 0 +Line 4471: 0 +Line 4472: 0 +Line 4473: 0 +Line 4474: 0 +Line 4475: 0 +Line 4476: 0 +Line 4477: 0 +Line 4478: 0 +Line 4479: 0 +Line 4480: 0 +Line 4481: 0 +Line 4482: 0 +Line 4483: 1 +Line 4484: 1 +Line 4485: 0 +Line 4486: 0 +Line 4487: 1 +Line 4488: 0 +Line 4489: 1 +Line 4490: 1 +Line 4491: 0 +Line 4492: 1 +Line 4493: 1 +Line 4494: 0 +Line 4495: 0 +Line 4496: 0 +Line 4497: 0 +Line 4498: 0 +Line 4499: 0 +Line 4500: 0 +Line 4501: 0 +Line 4502: 0 +Line 4503: 0 +Line 4504: 0 +Line 4505: 0 +Line 4506: 0 +Line 4507: 0 +Line 4508: 0 +Line 4509: 0 +Line 4510: 0 +Line 4511: 0 +Line 4512: 0 +Line 4513: 0 +Line 4514: 0 +Line 4515: 1 +Line 4516: 1 +Line 4517: 0 +Line 4518: 0 +Line 4519: 0 +Line 4520: 0 +Line 4521: 1 +Line 4522: 0 +Line 4523: 1 +Line 4524: 0 +Line 4525: 1 +Line 4526: 1 +Line 4527: 0 +Line 4528: 0 +Line 4529: 0 +Line 4530: 0 +Line 4531: 0 +Line 4532: 0 +Line 4533: 0 +Line 4534: 0 +Line 4535: 0 +Line 4536: 0 +Line 4537: 0 +Line 4538: 0 +Line 4539: 0 +Line 4540: 0 +Line 4541: 0 +Line 4542: 0 +Line 4543: 0 +Line 4544: 0 +Line 4545: 0 +Line 4546: 0 +Line 4547: 1 +Line 4548: 0 +Line 4549: 1 +Line 4550: 1 +Line 4551: 1 +Line 4552: 0 +Line 4553: 1 +Line 4554: 0 +Line 4555: 0 +Line 4556: 0 +Line 4557: 0 +Line 4558: 1 +Line 4559: 1 +Line 4560: 0 +Line 4561: 0 +Line 4562: 0 +Line 4563: 0 +Line 4564: 0 +Line 4565: 0 +Line 4566: 0 +Line 4567: 0 +Line 4568: 0 +Line 4569: 0 +Line 4570: 0 +Line 4571: 0 +Line 4572: 0 +Line 4573: 0 +Line 4574: 0 +Line 4575: 0 +Line 4576: 0 +Line 4577: 0 +Line 4578: 0 +Line 4579: 1 +Line 4580: 0 +Line 4581: 1 +Line 4582: 1 +Line 4583: 0 +Line 4584: 0 +Line 4585: 0 +Line 4586: 1 +Line 4587: 1 +Line 4588: 0 +Line 4589: 1 +Line 4590: 1 +Line 4591: 0 +Line 4592: 0 +Line 4593: 0 +Line 4594: 0 +Line 4595: 0 +Line 4596: 0 +Line 4597: 0 +Line 4598: 0 +Line 4599: 0 +Line 4600: 0 +Line 4601: 0 +Line 4602: 0 +Line 4603: 0 +Line 4604: 0 +Line 4605: 0 +Line 4606: 0 +Line 4607: 0 +Line 4608: 0 +Line 4609: 0 +Line 4610: 0 +Line 4611: 1 +Line 4612: 0 +Line 4613: 1 +Line 4614: 0 +Line 4615: 1 +Line 4616: 0 +Line 4617: 0 +Line 4618: 1 +Line 4619: 0 +Line 4620: 1 +Line 4621: 1 +Line 4622: 1 +Line 4623: 0 +Line 4624: 0 +Line 4625: 0 +Line 4626: 0 +Line 4627: 0 +Line 4628: 0 +Line 4629: 0 +Line 4630: 0 +Line 4631: 0 +Line 4632: 0 +Line 4633: 0 +Line 4634: 0 +Line 4635: 0 +Line 4636: 0 +Line 4637: 0 +Line 4638: 0 +Line 4639: 0 +Line 4640: 0 +Line 4641: 0 +Line 4642: 0 +Line 4643: 1 +Line 4644: 0 +Line 4645: 1 +Line 4646: 0 +Line 4647: 0 +Line 4648: 0 +Line 4649: 0 +Line 4650: 1 +Line 4651: 0 +Line 4652: 1 +Line 4653: 0 +Line 4654: 1 +Line 4655: 1 +Line 4656: 0 +Line 4657: 0 +Line 4658: 0 +Line 4659: 0 +Line 4660: 0 +Line 4661: 0 +Line 4662: 0 +Line 4663: 0 +Line 4664: 0 +Line 4665: 0 +Line 4666: 0 +Line 4667: 0 +Line 4668: 0 +Line 4669: 0 +Line 4670: 0 +Line 4671: 0 +Line 4672: 1 +Line 4673: 1 +Line 4674: 1 +Line 4675: 1 +Line 4676: 1 +Line 4677: 1 +Line 4678: 1 +Line 4679: 0 +Line 4680: 0 +Line 4681: 1 +Line 4682: 1 +Line 4683: 0 +Line 4684: 0 +Line 4685: 1 +Line 4686: 1 +Line 4687: 1 +Line 4688: 0 +Line 4689: 0 +Line 4690: 0 +Line 4691: 0 +Line 4692: 0 +Line 4693: 0 +Line 4694: 0 +Line 4695: 0 +Line 4696: 0 +Line 4697: 0 +Line 4698: 0 +Line 4699: 0 +Line 4700: 0 +Line 4701: 0 +Line 4702: 0 +Line 4703: 0 +Line 4704: 1 +Line 4705: 1 +Line 4706: 1 +Line 4707: 1 +Line 4708: 0 +Line 4709: 1 +Line 4710: 0 +Line 4711: 0 +Line 4712: 1 +Line 4713: 1 +Line 4714: 0 +Line 4715: 1 +Line 4716: 1 +Line 4717: 0 +Line 4718: 0 +Line 4719: 1 +Line 4720: 0 +Line 4721: 0 +Line 4722: 0 +Line 4723: 0 +Line 4724: 0 +Line 4725: 0 +Line 4726: 0 +Line 4727: 0 +Line 4728: 0 +Line 4729: 0 +Line 4730: 0 +Line 4731: 0 +Line 4732: 0 +Line 4733: 0 +Line 4734: 0 +Line 4735: 0 +Line 4736: 1 +Line 4737: 1 +Line 4738: 0 +Line 4739: 1 +Line 4740: 1 +Line 4741: 1 +Line 4742: 0 +Line 4743: 0 +Line 4744: 1 +Line 4745: 1 +Line 4746: 0 +Line 4747: 1 +Line 4748: 1 +Line 4749: 0 +Line 4750: 0 +Line 4751: 0 +Line 4752: 0 +Line 4753: 0 +Line 4754: 0 +Line 4755: 0 +Line 4756: 0 +Line 4757: 0 +Line 4758: 0 +Line 4759: 0 +Line 4760: 0 +Line 4761: 0 +Line 4762: 0 +Line 4763: 0 +Line 4764: 0 +Line 4765: 0 +Line 4766: 0 +Line 4767: 0 +Line 4768: 1 +Line 4769: 1 +Line 4770: 0 +Line 4771: 0 +Line 4772: 0 +Line 4773: 1 +Line 4774: 0 +Line 4775: 0 +Line 4776: 1 +Line 4777: 1 +Line 4778: 0 +Line 4779: 1 +Line 4780: 1 +Line 4781: 0 +Line 4782: 0 +Line 4783: 0 +Line 4784: 0 +Line 4785: 0 +Line 4786: 0 +Line 4787: 0 +Line 4788: 0 +Line 4789: 0 +Line 4790: 0 +Line 4791: 0 +Line 4792: 0 +Line 4793: 0 +Line 4794: 0 +Line 4795: 0 +Line 4796: 0 +Line 4797: 0 +Line 4798: 0 +Line 4799: 0 +Line 4800: 1 +Line 4801: 0 +Line 4802: 1 +Line 4803: 1 +Line 4804: 1 +Line 4805: 0 +Line 4806: 1 +Line 4807: 1 +Line 4808: 0 +Line 4809: 1 +Line 4810: 0 +Line 4811: 0 +Line 4812: 1 +Line 4813: 0 +Line 4814: 1 +Line 4815: 0 +Line 4816: 0 +Line 4817: 0 +Line 4818: 0 +Line 4819: 0 +Line 4820: 0 +Line 4821: 0 +Line 4822: 0 +Line 4823: 0 +Line 4824: 0 +Line 4825: 0 +Line 4826: 0 +Line 4827: 0 +Line 4828: 0 +Line 4829: 0 +Line 4830: 0 +Line 4831: 0 +Line 4832: 1 +Line 4833: 0 +Line 4834: 1 +Line 4835: 1 +Line 4836: 1 +Line 4837: 0 +Line 4838: 0 +Line 4839: 1 +Line 4840: 1 +Line 4841: 1 +Line 4842: 0 +Line 4843: 0 +Line 4844: 1 +Line 4845: 0 +Line 4846: 0 +Line 4847: 1 +Line 4848: 0 +Line 4849: 0 +Line 4850: 0 +Line 4851: 0 +Line 4852: 0 +Line 4853: 0 +Line 4854: 0 +Line 4855: 0 +Line 4856: 0 +Line 4857: 0 +Line 4858: 0 +Line 4859: 0 +Line 4860: 0 +Line 4861: 0 +Line 4862: 0 +Line 4863: 0 +Line 4864: 1 +Line 4865: 0 +Line 4866: 1 +Line 4867: 1 +Line 4868: 1 +Line 4869: 0 +Line 4870: 0 +Line 4871: 1 +Line 4872: 1 +Line 4873: 0 +Line 4874: 1 +Line 4875: 1 +Line 4876: 0 +Line 4877: 0 +Line 4878: 0 +Line 4879: 1 +Line 4880: 0 +Line 4881: 0 +Line 4882: 0 +Line 4883: 0 +Line 4884: 0 +Line 4885: 0 +Line 4886: 0 +Line 4887: 0 +Line 4888: 0 +Line 4889: 0 +Line 4890: 0 +Line 4891: 0 +Line 4892: 0 +Line 4893: 0 +Line 4894: 0 +Line 4895: 0 +Line 4896: 1 +Line 4897: 0 +Line 4898: 1 +Line 4899: 1 +Line 4900: 1 +Line 4901: 0 +Line 4902: 0 +Line 4903: 1 +Line 4904: 1 +Line 4905: 0 +Line 4906: 1 +Line 4907: 1 +Line 4908: 0 +Line 4909: 0 +Line 4910: 0 +Line 4911: 1 +Line 4912: 0 +Line 4913: 0 +Line 4914: 0 +Line 4915: 0 +Line 4916: 0 +Line 4917: 0 +Line 4918: 0 +Line 4919: 0 +Line 4920: 0 +Line 4921: 0 +Line 4922: 0 +Line 4923: 0 +Line 4924: 0 +Line 4925: 0 +Line 4926: 0 +Line 4927: 0 +Line 4928: 1 +Line 4929: 0 +Line 4930: 1 +Line 4931: 1 +Line 4932: 1 +Line 4933: 0 +Line 4934: 0 +Line 4935: 1 +Line 4936: 1 +Line 4937: 0 +Line 4938: 1 +Line 4939: 1 +Line 4940: 0 +Line 4941: 0 +Line 4942: 0 +Line 4943: 1 +Line 4944: 0 +Line 4945: 0 +Line 4946: 0 +Line 4947: 0 +Line 4948: 0 +Line 4949: 0 +Line 4950: 0 +Line 4951: 0 +Line 4952: 0 +Line 4953: 0 +Line 4954: 0 +Line 4955: 0 +Line 4956: 0 +Line 4957: 0 +Line 4958: 0 +Line 4959: 0 +Line 4960: 1 +Line 4961: 0 +Line 4962: 1 +Line 4963: 1 +Line 4964: 1 +Line 4965: 0 +Line 4966: 0 +Line 4967: 1 +Line 4968: 1 +Line 4969: 0 +Line 4970: 1 +Line 4971: 1 +Line 4972: 0 +Line 4973: 0 +Line 4974: 0 +Line 4975: 1 +Line 4976: 0 +Line 4977: 0 +Line 4978: 0 +Line 4979: 0 +Line 4980: 0 +Line 4981: 0 +Line 4982: 0 +Line 4983: 0 +Line 4984: 0 +Line 4985: 0 +Line 4986: 0 +Line 4987: 0 +Line 4988: 0 +Line 4989: 0 +Line 4990: 0 +Line 4991: 0 +Line 4992: 1 +Line 4993: 0 +Line 4994: 1 +Line 4995: 1 +Line 4996: 1 +Line 4997: 0 +Line 4998: 0 +Line 4999: 1 +Line 5000: 1 +Line 5001: 0 +Line 5002: 1 +Line 5003: 1 +Line 5004: 0 +Line 5005: 0 +Line 5006: 0 +Line 5007: 1 +Line 5008: 0 +Line 5009: 0 +Line 5010: 0 +Line 5011: 0 +Line 5012: 0 +Line 5013: 0 +Line 5014: 0 +Line 5015: 0 +Line 5016: 0 +Line 5017: 0 +Line 5018: 0 +Line 5019: 0 +Line 5020: 0 +Line 5021: 0 +Line 5022: 0 +Line 5023: 0 +Line 5024: 1 +Line 5025: 0 +Line 5026: 1 +Line 5027: 1 +Line 5028: 1 +Line 5029: 0 +Line 5030: 0 +Line 5031: 1 +Line 5032: 1 +Line 5033: 0 +Line 5034: 1 +Line 5035: 1 +Line 5036: 0 +Line 5037: 0 +Line 5038: 0 +Line 5039: 0 +Line 5040: 0 +Line 5041: 0 +Line 5042: 0 +Line 5043: 0 +Line 5044: 0 +Line 5045: 0 +Line 5046: 0 +Line 5047: 0 +Line 5048: 0 +Line 5049: 0 +Line 5050: 0 +Line 5051: 0 +Line 5052: 0 +Line 5053: 0 +Line 5054: 0 +Line 5055: 0 +Line 5056: 1 +Line 5057: 0 +Line 5058: 1 +Line 5059: 1 +Line 5060: 1 +Line 5061: 0 +Line 5062: 0 +Line 5063: 1 +Line 5064: 1 +Line 5065: 0 +Line 5066: 1 +Line 5067: 1 +Line 5068: 0 +Line 5069: 0 +Line 5070: 0 +Line 5071: 0 +Line 5072: 0 +Line 5073: 0 +Line 5074: 0 +Line 5075: 0 +Line 5076: 0 +Line 5077: 0 +Line 5078: 0 +Line 5079: 0 +Line 5080: 0 +Line 5081: 0 +Line 5082: 0 +Line 5083: 0 +Line 5084: 0 +Line 5085: 0 +Line 5086: 0 +Line 5087: 0 +Line 5088: 1 +Line 5089: 0 +Line 5090: 1 +Line 5091: 1 +Line 5092: 1 +Line 5093: 0 +Line 5094: 0 +Line 5095: 1 +Line 5096: 1 +Line 5097: 0 +Line 5098: 1 +Line 5099: 1 +Line 5100: 0 +Line 5101: 0 +Line 5102: 0 +Line 5103: 0 +Line 5104: 0 +Line 5105: 0 +Line 5106: 0 +Line 5107: 0 +Line 5108: 0 +Line 5109: 0 +Line 5110: 0 +Line 5111: 0 +Line 5112: 0 +Line 5113: 0 +Line 5114: 0 +Line 5115: 0 +Line 5116: 0 +Line 5117: 0 +Line 5118: 0 +Line 5119: 0 +Line 5120: 1 +Line 5121: 0 +Line 5122: 1 +Line 5123: 1 +Line 5124: 1 +Line 5125: 0 +Line 5126: 0 +Line 5127: 1 +Line 5128: 1 +Line 5129: 0 +Line 5130: 1 +Line 5131: 1 +Line 5132: 0 +Line 5133: 0 +Line 5134: 0 +Line 5135: 1 +Line 5136: 0 +Line 5137: 0 +Line 5138: 0 +Line 5139: 0 +Line 5140: 0 +Line 5141: 0 +Line 5142: 0 +Line 5143: 0 +Line 5144: 0 +Line 5145: 0 +Line 5146: 0 +Line 5147: 0 +Line 5148: 0 +Line 5149: 0 +Line 5150: 0 +Line 5151: 0 +Line 5152: 1 +Line 5153: 0 +Line 5154: 1 +Line 5155: 1 +Line 5156: 1 +Line 5157: 0 +Line 5158: 0 +Line 5159: 1 +Line 5160: 1 +Line 5161: 0 +Line 5162: 1 +Line 5163: 1 +Line 5164: 0 +Line 5165: 0 +Line 5166: 0 +Line 5167: 1 +Line 5168: 0 +Line 5169: 0 +Line 5170: 0 +Line 5171: 0 +Line 5172: 0 +Line 5173: 0 +Line 5174: 0 +Line 5175: 0 +Line 5176: 0 +Line 5177: 0 +Line 5178: 0 +Line 5179: 0 +Line 5180: 0 +Line 5181: 0 +Line 5182: 0 +Line 5183: 0 +Line 5184: 1 +Line 5185: 0 +Line 5186: 1 +Line 5187: 1 +Line 5188: 1 +Line 5189: 0 +Line 5190: 0 +Line 5191: 1 +Line 5192: 1 +Line 5193: 0 +Line 5194: 1 +Line 5195: 1 +Line 5196: 0 +Line 5197: 0 +Line 5198: 0 +Line 5199: 1 +Line 5200: 0 +Line 5201: 0 +Line 5202: 0 +Line 5203: 0 +Line 5204: 0 +Line 5205: 0 +Line 5206: 0 +Line 5207: 0 +Line 5208: 0 +Line 5209: 0 +Line 5210: 0 +Line 5211: 0 +Line 5212: 0 +Line 5213: 0 +Line 5214: 0 +Line 5215: 0 +Line 5216: 1 +Line 5217: 0 +Line 5218: 1 +Line 5219: 1 +Line 5220: 1 +Line 5221: 0 +Line 5222: 0 +Line 5223: 1 +Line 5224: 1 +Line 5225: 0 +Line 5226: 1 +Line 5227: 1 +Line 5228: 0 +Line 5229: 0 +Line 5230: 0 +Line 5231: 1 +Line 5232: 0 +Line 5233: 0 +Line 5234: 0 +Line 5235: 0 +Line 5236: 0 +Line 5237: 0 +Line 5238: 0 +Line 5239: 0 +Line 5240: 0 +Line 5241: 0 +Line 5242: 0 +Line 5243: 0 +Line 5244: 0 +Line 5245: 0 +Line 5246: 0 +Line 5247: 0 +Line 5248: 1 +Line 5249: 0 +Line 5250: 1 +Line 5251: 1 +Line 5252: 1 +Line 5253: 0 +Line 5254: 0 +Line 5255: 1 +Line 5256: 1 +Line 5257: 0 +Line 5258: 1 +Line 5259: 1 +Line 5260: 0 +Line 5261: 0 +Line 5262: 0 +Line 5263: 1 +Line 5264: 0 +Line 5265: 0 +Line 5266: 0 +Line 5267: 0 +Line 5268: 0 +Line 5269: 0 +Line 5270: 0 +Line 5271: 0 +Line 5272: 0 +Line 5273: 0 +Line 5274: 0 +Line 5275: 0 +Line 5276: 0 +Line 5277: 0 +Line 5278: 0 +Line 5279: 0 +Line 5280: 1 +Line 5281: 0 +Line 5282: 1 +Line 5283: 1 +Line 5284: 1 +Line 5285: 0 +Line 5286: 0 +Line 5287: 1 +Line 5288: 1 +Line 5289: 1 +Line 5290: 0 +Line 5291: 0 +Line 5292: 1 +Line 5293: 0 +Line 5294: 0 +Line 5295: 1 +Line 5296: 0 +Line 5297: 0 +Line 5298: 0 +Line 5299: 0 +Line 5300: 0 +Line 5301: 0 +Line 5302: 0 +Line 5303: 0 +Line 5304: 0 +Line 5305: 0 +Line 5306: 0 +Line 5307: 0 +Line 5308: 0 +Line 5309: 0 +Line 5310: 0 +Line 5311: 0 +Line 5312: 1 +Line 5313: 0 +Line 5314: 1 +Line 5315: 1 +Line 5316: 1 +Line 5317: 0 +Line 5318: 1 +Line 5319: 1 +Line 5320: 0 +Line 5321: 1 +Line 5322: 0 +Line 5323: 0 +Line 5324: 1 +Line 5325: 0 +Line 5326: 1 +Line 5327: 0 +Line 5328: 0 +Line 5329: 0 +Line 5330: 0 +Line 5331: 0 +Line 5332: 0 +Line 5333: 0 +Line 5334: 0 +Line 5335: 0 +Line 5336: 0 +Line 5337: 0 +Line 5338: 0 +Line 5339: 0 +Line 5340: 0 +Line 5341: 0 +Line 5342: 0 +Line 5343: 0 +Line 5344: 1 +Line 5345: 1 +Line 5346: 0 +Line 5347: 0 +Line 5348: 0 +Line 5349: 1 +Line 5350: 0 +Line 5351: 0 +Line 5352: 1 +Line 5353: 1 +Line 5354: 0 +Line 5355: 1 +Line 5356: 1 +Line 5357: 0 +Line 5358: 0 +Line 5359: 0 +Line 5360: 0 +Line 5361: 0 +Line 5362: 0 +Line 5363: 0 +Line 5364: 0 +Line 5365: 0 +Line 5366: 0 +Line 5367: 0 +Line 5368: 0 +Line 5369: 0 +Line 5370: 0 +Line 5371: 0 +Line 5372: 0 +Line 5373: 0 +Line 5374: 0 +Line 5375: 0 +Line 5376: 1 +Line 5377: 1 +Line 5378: 0 +Line 5379: 1 +Line 5380: 1 +Line 5381: 1 +Line 5382: 0 +Line 5383: 0 +Line 5384: 1 +Line 5385: 1 +Line 5386: 0 +Line 5387: 1 +Line 5388: 1 +Line 5389: 0 +Line 5390: 0 +Line 5391: 0 +Line 5392: 0 +Line 5393: 0 +Line 5394: 0 +Line 5395: 0 +Line 5396: 0 +Line 5397: 0 +Line 5398: 0 +Line 5399: 0 +Line 5400: 0 +Line 5401: 0 +Line 5402: 0 +Line 5403: 0 +Line 5404: 0 +Line 5405: 0 +Line 5406: 0 +Line 5407: 0 +Line 5408: 1 +Line 5409: 1 +Line 5410: 1 +Line 5411: 1 +Line 5412: 0 +Line 5413: 1 +Line 5414: 0 +Line 5415: 0 +Line 5416: 1 +Line 5417: 1 +Line 5418: 0 +Line 5419: 1 +Line 5420: 1 +Line 5421: 0 +Line 5422: 0 +Line 5423: 1 +Line 5424: 0 +Line 5425: 0 +Line 5426: 0 +Line 5427: 0 +Line 5428: 0 +Line 5429: 0 +Line 5430: 0 +Line 5431: 0 +Line 5432: 0 +Line 5433: 0 +Line 5434: 0 +Line 5435: 0 +Line 5436: 0 +Line 5437: 0 +Line 5438: 0 +Line 5439: 0 +Line 5440: 1 +Line 5441: 1 +Line 5442: 1 +Line 5443: 1 +Line 5444: 1 +Line 5445: 1 +Line 5446: 1 +Line 5447: 0 +Line 5448: 0 +Line 5449: 1 +Line 5450: 1 +Line 5451: 0 +Line 5452: 0 +Line 5453: 1 +Line 5454: 1 +Line 5455: 1 +Line 5456: 0 +Line 5457: 0 +Line 5458: 0 +Line 5459: 0 +Line 5460: 0 +Line 5461: 0 +Line 5462: 0 +Line 5463: 0 +Line 5464: 0 +Line 5465: 0 +Line 5466: 0 +Line 5467: 0 +Line 5468: 0 +Line 5469: 0 +Line 5470: 0 +Line 5471: 0 +Line 5472: 0 +Line 5473: 0 +Line 5474: 0 +Line 5475: 0 +Line 5476: 0 +Line 5477: 0 +Line 5478: 0 +Line 5479: 0 +Line 5480: 0 +Line 5481: 0 +Line 5482: 0 +Line 5483: 0 +Line 5484: 0 +Line 5485: 0 +Line 5486: 0 +Line 5487: 0 +Line 5488: 0 +Line 5489: 0 +Line 5490: 0 +Line 5491: 0 +Line 5492: 0 +Line 5493: 0 +Line 5494: 0 +Line 5495: 0 +Line 5496: 0 +Line 5497: 0 +Line 5498: 0 +Line 5499: 0 +Line 5500: 0 +Line 5501: 0 +Line 5502: 0 +Line 5503: 0 +Line 5504: 0 +Line 5505: 0 +Line 5506: 0 +Line 5507: 0 +Line 5508: 0 +Line 5509: 0 +Line 5510: 0 +Line 5511: 0 +Line 5512: 0 +Line 5513: 0 +Line 5514: 0 +Line 5515: 0 +Line 5516: 0 +Line 5517: 1 +Line 5518: 0 +Line 5519: 1 +Line 5520: 1 +Line 5521: 1 +Line 5522: 1 +Line 5523: 1 +Line 5524: 1 +Line 5525: 1 +Line 5526: 1 +Line 5527: 1 +Line 5528: 1 +Line 5529: 1 +Line 5530: 1 +Line 5531: 1 +Line 5532: 0 +Line 5533: 0 +Line 5534: 0 +Line 5535: 1 +Line 5536: 0 +Line 5537: 0 +Line 5538: 0 +Line 5539: 0 +Line 5540: 0 +Line 5541: 0 +Line 5542: 0 +Line 5543: 0 +Line 5544: 0 +Line 5545: 0 +Line 5546: 0 +Line 5547: 1 +Line 5548: 0 +Line 5549: 1 +Line 5550: 1 +Line 5551: 1 +Line 5552: 1 +Line 5553: 1 +Line 5554: 1 +Line 5555: 1 +Line 5556: 1 +Line 5557: 1 +Line 5558: 1 +Line 5559: 1 +Line 5560: 1 +Line 5561: 1 +Line 5562: 1 +Line 5563: 0 +Line 5564: 0 +Line 5565: 0 +Line 5566: 0 +Line 5567: 1 +Line 5568: 0 +Line 5569: 0 +Line 5570: 0 +Line 5571: 0 +Line 5572: 0 +Line 5573: 0 +Line 5574: 0 +Line 5575: 0 +Line 5576: 0 +Line 5577: 0 +Line 5578: 1 +Line 5579: 1 +Line 5580: 0 +Line 5581: 1 +Line 5582: 0 +Line 5583: 0 +Line 5584: 1 +Line 5585: 1 +Line 5586: 1 +Line 5587: 1 +Line 5588: 1 +Line 5589: 1 +Line 5590: 1 +Line 5591: 1 +Line 5592: 1 +Line 5593: 1 +Line 5594: 0 +Line 5595: 1 +Line 5596: 0 +Line 5597: 0 +Line 5598: 0 +Line 5599: 1 +Line 5600: 0 +Line 5601: 0 +Line 5602: 0 +Line 5603: 0 +Line 5604: 0 +Line 5605: 0 +Line 5606: 0 +Line 5607: 0 +Line 5608: 0 +Line 5609: 1 +Line 5610: 0 +Line 5611: 1 +Line 5612: 1 +Line 5613: 1 +Line 5614: 0 +Line 5615: 1 +Line 5616: 1 +Line 5617: 1 +Line 5618: 1 +Line 5619: 1 +Line 5620: 1 +Line 5621: 1 +Line 5622: 1 +Line 5623: 1 +Line 5624: 1 +Line 5625: 1 +Line 5626: 0 +Line 5627: 0 +Line 5628: 0 +Line 5629: 0 +Line 5630: 1 +Line 5631: 0 +Line 5632: 0 +Line 5633: 0 +Line 5634: 0 +Line 5635: 0 +Line 5636: 0 +Line 5637: 0 +Line 5638: 0 +Line 5639: 0 +Line 5640: 1 +Line 5641: 0 +Line 5642: 0 +Line 5643: 1 +Line 5644: 0 +Line 5645: 0 +Line 5646: 1 +Line 5647: 0 +Line 5648: 1 +Line 5649: 1 +Line 5650: 1 +Line 5651: 1 +Line 5652: 1 +Line 5653: 1 +Line 5654: 1 +Line 5655: 1 +Line 5656: 1 +Line 5657: 0 +Line 5658: 1 +Line 5659: 1 +Line 5660: 0 +Line 5661: 0 +Line 5662: 1 +Line 5663: 0 +Line 5664: 0 +Line 5665: 0 +Line 5666: 0 +Line 5667: 0 +Line 5668: 0 +Line 5669: 0 +Line 5670: 0 +Line 5671: 0 +Line 5672: 1 +Line 5673: 1 +Line 5674: 0 +Line 5675: 1 +Line 5676: 0 +Line 5677: 0 +Line 5678: 1 +Line 5679: 0 +Line 5680: 1 +Line 5681: 1 +Line 5682: 1 +Line 5683: 1 +Line 5684: 1 +Line 5685: 1 +Line 5686: 1 +Line 5687: 1 +Line 5688: 1 +Line 5689: 0 +Line 5690: 1 +Line 5691: 0 +Line 5692: 0 +Line 5693: 0 +Line 5694: 1 +Line 5695: 1 +Line 5696: 0 +Line 5697: 0 +Line 5698: 0 +Line 5699: 0 +Line 5700: 0 +Line 5701: 0 +Line 5702: 0 +Line 5703: 1 +Line 5704: 0 +Line 5705: 0 +Line 5706: 0 +Line 5707: 1 +Line 5708: 1 +Line 5709: 1 +Line 5710: 0 +Line 5711: 1 +Line 5712: 1 +Line 5713: 1 +Line 5714: 1 +Line 5715: 1 +Line 5716: 1 +Line 5717: 1 +Line 5718: 1 +Line 5719: 1 +Line 5720: 1 +Line 5721: 0 +Line 5722: 0 +Line 5723: 1 +Line 5724: 0 +Line 5725: 1 +Line 5726: 0 +Line 5727: 0 +Line 5728: 0 +Line 5729: 0 +Line 5730: 0 +Line 5731: 0 +Line 5732: 0 +Line 5733: 0 +Line 5734: 0 +Line 5735: 1 +Line 5736: 0 +Line 5737: 1 +Line 5738: 1 +Line 5739: 1 +Line 5740: 0 +Line 5741: 1 +Line 5742: 0 +Line 5743: 0 +Line 5744: 1 +Line 5745: 1 +Line 5746: 1 +Line 5747: 1 +Line 5748: 1 +Line 5749: 1 +Line 5750: 1 +Line 5751: 1 +Line 5752: 1 +Line 5753: 0 +Line 5754: 0 +Line 5755: 0 +Line 5756: 0 +Line 5757: 1 +Line 5758: 0 +Line 5759: 0 +Line 5760: 0 +Line 5761: 0 +Line 5762: 0 +Line 5763: 0 +Line 5764: 0 +Line 5765: 0 +Line 5766: 0 +Line 5767: 1 +Line 5768: 1 +Line 5769: 1 +Line 5770: 0 +Line 5771: 1 +Line 5772: 0 +Line 5773: 1 +Line 5774: 1 +Line 5775: 1 +Line 5776: 1 +Line 5777: 1 +Line 5778: 1 +Line 5779: 1 +Line 5780: 1 +Line 5781: 1 +Line 5782: 1 +Line 5783: 1 +Line 5784: 0 +Line 5785: 1 +Line 5786: 1 +Line 5787: 1 +Line 5788: 0 +Line 5789: 1 +Line 5790: 0 +Line 5791: 1 +Line 5792: 0 +Line 5793: 0 +Line 5794: 0 +Line 5795: 0 +Line 5796: 0 +Line 5797: 0 +Line 5798: 1 +Line 5799: 0 +Line 5800: 0 +Line 5801: 1 +Line 5802: 0 +Line 5803: 0 +Line 5804: 0 +Line 5805: 1 +Line 5806: 0 +Line 5807: 0 +Line 5808: 1 +Line 5809: 1 +Line 5810: 1 +Line 5811: 1 +Line 5812: 1 +Line 5813: 1 +Line 5814: 1 +Line 5815: 1 +Line 5816: 0 +Line 5817: 1 +Line 5818: 1 +Line 5819: 0 +Line 5820: 0 +Line 5821: 1 +Line 5822: 1 +Line 5823: 1 +Line 5824: 0 +Line 5825: 0 +Line 5826: 0 +Line 5827: 0 +Line 5828: 0 +Line 5829: 0 +Line 5830: 1 +Line 5831: 0 +Line 5832: 1 +Line 5833: 0 +Line 5834: 1 +Line 5835: 1 +Line 5836: 1 +Line 5837: 1 +Line 5838: 0 +Line 5839: 0 +Line 5840: 1 +Line 5841: 1 +Line 5842: 1 +Line 5843: 1 +Line 5844: 1 +Line 5845: 1 +Line 5846: 1 +Line 5847: 1 +Line 5848: 0 +Line 5849: 1 +Line 5850: 0 +Line 5851: 1 +Line 5852: 1 +Line 5853: 0 +Line 5854: 0 +Line 5855: 0 +Line 5856: 0 +Line 5857: 0 +Line 5858: 0 +Line 5859: 0 +Line 5860: 0 +Line 5861: 0 +Line 5862: 1 +Line 5863: 1 +Line 5864: 0 +Line 5865: 0 +Line 5866: 1 +Line 5867: 1 +Line 5868: 1 +Line 5869: 1 +Line 5870: 1 +Line 5871: 1 +Line 5872: 1 +Line 5873: 1 +Line 5874: 1 +Line 5875: 1 +Line 5876: 1 +Line 5877: 1 +Line 5878: 1 +Line 5879: 1 +Line 5880: 0 +Line 5881: 1 +Line 5882: 0 +Line 5883: 0 +Line 5884: 1 +Line 5885: 0 +Line 5886: 1 +Line 5887: 0 +Line 5888: 0 +Line 5889: 0 +Line 5890: 0 +Line 5891: 0 +Line 5892: 0 +Line 5893: 0 +Line 5894: 1 +Line 5895: 1 +Line 5896: 1 +Line 5897: 1 +Line 5898: 0 +Line 5899: 0 +Line 5900: 1 +Line 5901: 1 +Line 5902: 0 +Line 5903: 1 +Line 5904: 1 +Line 5905: 1 +Line 5906: 1 +Line 5907: 1 +Line 5908: 1 +Line 5909: 1 +Line 5910: 1 +Line 5911: 1 +Line 5912: 0 +Line 5913: 0 +Line 5914: 1 +Line 5915: 1 +Line 5916: 1 +Line 5917: 0 +Line 5918: 1 +Line 5919: 1 +Line 5920: 0 +Line 5921: 0 +Line 5922: 0 +Line 5923: 0 +Line 5924: 0 +Line 5925: 1 +Line 5926: 0 +Line 5927: 0 +Line 5928: 0 +Line 5929: 1 +Line 5930: 1 +Line 5931: 0 +Line 5932: 0 +Line 5933: 1 +Line 5934: 0 +Line 5935: 1 +Line 5936: 1 +Line 5937: 1 +Line 5938: 1 +Line 5939: 1 +Line 5940: 1 +Line 5941: 1 +Line 5942: 1 +Line 5943: 1 +Line 5944: 0 +Line 5945: 0 +Line 5946: 1 +Line 5947: 0 +Line 5948: 1 +Line 5949: 1 +Line 5950: 1 +Line 5951: 0 +Line 5952: 0 +Line 5953: 0 +Line 5954: 0 +Line 5955: 0 +Line 5956: 0 +Line 5957: 1 +Line 5958: 0 +Line 5959: 1 +Line 5960: 0 +Line 5961: 0 +Line 5962: 0 +Line 5963: 0 +Line 5964: 1 +Line 5965: 0 +Line 5966: 0 +Line 5967: 0 +Line 5968: 1 +Line 5969: 1 +Line 5970: 1 +Line 5971: 1 +Line 5972: 1 +Line 5973: 1 +Line 5974: 1 +Line 5975: 1 +Line 5976: 0 +Line 5977: 0 +Line 5978: 1 +Line 5979: 0 +Line 5980: 0 +Line 5981: 0 +Line 5982: 0 +Line 5983: 0 +Line 5984: 0 +Line 5985: 0 +Line 5986: 0 +Line 5987: 0 +Line 5988: 0 +Line 5989: 1 +Line 5990: 0 +Line 5991: 1 +Line 5992: 1 +Line 5993: 0 +Line 5994: 1 +Line 5995: 1 +Line 5996: 0 +Line 5997: 1 +Line 5998: 0 +Line 5999: 0 +Line 6000: 1 +Line 6001: 1 +Line 6002: 1 +Line 6003: 1 +Line 6004: 1 +Line 6005: 1 +Line 6006: 1 +Line 6007: 1 +Line 6008: 0 +Line 6009: 0 +Line 6010: 0 +Line 6011: 1 +Line 6012: 0 +Line 6013: 0 +Line 6014: 1 +Line 6015: 1 +Line 6016: 0 +Line 6017: 0 +Line 6018: 0 +Line 6019: 0 +Line 6020: 0 +Line 6021: 1 +Line 6022: 1 +Line 6023: 0 +Line 6024: 0 +Line 6025: 1 +Line 6026: 1 +Line 6027: 0 +Line 6028: 1 +Line 6029: 0 +Line 6030: 1 +Line 6031: 1 +Line 6032: 1 +Line 6033: 1 +Line 6034: 1 +Line 6035: 1 +Line 6036: 1 +Line 6037: 1 +Line 6038: 1 +Line 6039: 1 +Line 6040: 0 +Line 6041: 0 +Line 6042: 0 +Line 6043: 0 +Line 6044: 0 +Line 6045: 1 +Line 6046: 1 +Line 6047: 0 +Line 6048: 0 +Line 6049: 0 +Line 6050: 0 +Line 6051: 0 +Line 6052: 0 +Line 6053: 1 +Line 6054: 1 +Line 6055: 1 +Line 6056: 0 +Line 6057: 0 +Line 6058: 1 +Line 6059: 0 +Line 6060: 1 +Line 6061: 0 +Line 6062: 1 +Line 6063: 1 +Line 6064: 1 +Line 6065: 1 +Line 6066: 1 +Line 6067: 1 +Line 6068: 1 +Line 6069: 1 +Line 6070: 1 +Line 6071: 0 +Line 6072: 1 +Line 6073: 1 +Line 6074: 1 +Line 6075: 1 +Line 6076: 1 +Line 6077: 0 +Line 6078: 0 +Line 6079: 1 +Line 6080: 0 +Line 6081: 0 +Line 6082: 0 +Line 6083: 0 +Line 6084: 0 +Line 6085: 1 +Line 6086: 1 +Line 6087: 1 +Line 6088: 1 +Line 6089: 1 +Line 6090: 1 +Line 6091: 1 +Line 6092: 0 +Line 6093: 1 +Line 6094: 0 +Line 6095: 0 +Line 6096: 1 +Line 6097: 1 +Line 6098: 1 +Line 6099: 1 +Line 6100: 1 +Line 6101: 1 +Line 6102: 1 +Line 6103: 0 +Line 6104: 1 +Line 6105: 1 +Line 6106: 1 +Line 6107: 0 +Line 6108: 1 +Line 6109: 1 +Line 6110: 0 +Line 6111: 1 +Line 6112: 0 +Line 6113: 0 +Line 6114: 0 +Line 6115: 0 +Line 6116: 1 +Line 6117: 0 +Line 6118: 0 +Line 6119: 0 +Line 6120: 1 +Line 6121: 1 +Line 6122: 0 +Line 6123: 0 +Line 6124: 0 +Line 6125: 1 +Line 6126: 1 +Line 6127: 0 +Line 6128: 1 +Line 6129: 1 +Line 6130: 1 +Line 6131: 1 +Line 6132: 1 +Line 6133: 1 +Line 6134: 1 +Line 6135: 0 +Line 6136: 1 +Line 6137: 1 +Line 6138: 1 +Line 6139: 0 +Line 6140: 0 +Line 6141: 0 +Line 6142: 0 +Line 6143: 1 +Line 6144: 0 +Line 6145: 0 +Line 6146: 0 +Line 6147: 0 +Line 6148: 1 +Line 6149: 0 +Line 6150: 0 +Line 6151: 1 +Line 6152: 1 +Line 6153: 0 +Line 6154: 1 +Line 6155: 0 +Line 6156: 0 +Line 6157: 0 +Line 6158: 1 +Line 6159: 0 +Line 6160: 1 +Line 6161: 1 +Line 6162: 1 +Line 6163: 1 +Line 6164: 1 +Line 6165: 1 +Line 6166: 1 +Line 6167: 0 +Line 6168: 1 +Line 6169: 1 +Line 6170: 0 +Line 6171: 1 +Line 6172: 0 +Line 6173: 1 +Line 6174: 0 +Line 6175: 1 +Line 6176: 0 +Line 6177: 0 +Line 6178: 0 +Line 6179: 0 +Line 6180: 1 +Line 6181: 0 +Line 6182: 1 +Line 6183: 0 +Line 6184: 1 +Line 6185: 0 +Line 6186: 0 +Line 6187: 0 +Line 6188: 0 +Line 6189: 1 +Line 6190: 0 +Line 6191: 1 +Line 6192: 1 +Line 6193: 1 +Line 6194: 1 +Line 6195: 1 +Line 6196: 1 +Line 6197: 1 +Line 6198: 1 +Line 6199: 0 +Line 6200: 1 +Line 6201: 1 +Line 6202: 0 +Line 6203: 0 +Line 6204: 1 +Line 6205: 0 +Line 6206: 1 +Line 6207: 0 +Line 6208: 0 +Line 6209: 0 +Line 6210: 0 +Line 6211: 0 +Line 6212: 1 +Line 6213: 0 +Line 6214: 1 +Line 6215: 1 +Line 6216: 0 +Line 6217: 1 +Line 6218: 1 +Line 6219: 1 +Line 6220: 0 +Line 6221: 0 +Line 6222: 0 +Line 6223: 1 +Line 6224: 1 +Line 6225: 1 +Line 6226: 1 +Line 6227: 1 +Line 6228: 1 +Line 6229: 1 +Line 6230: 1 +Line 6231: 0 +Line 6232: 1 +Line 6233: 0 +Line 6234: 1 +Line 6235: 1 +Line 6236: 1 +Line 6237: 1 +Line 6238: 1 +Line 6239: 1 +Line 6240: 0 +Line 6241: 0 +Line 6242: 0 +Line 6243: 0 +Line 6244: 1 +Line 6245: 1 +Line 6246: 0 +Line 6247: 0 +Line 6248: 0 +Line 6249: 1 +Line 6250: 1 +Line 6251: 0 +Line 6252: 0 +Line 6253: 1 +Line 6254: 0 +Line 6255: 1 +Line 6256: 1 +Line 6257: 1 +Line 6258: 1 +Line 6259: 1 +Line 6260: 1 +Line 6261: 1 +Line 6262: 1 +Line 6263: 0 +Line 6264: 1 +Line 6265: 0 +Line 6266: 1 +Line 6267: 1 +Line 6268: 0 +Line 6269: 1 +Line 6270: 0 +Line 6271: 1 +Line 6272: 0 +Line 6273: 0 +Line 6274: 0 +Line 6275: 0 +Line 6276: 1 +Line 6277: 1 +Line 6278: 0 +Line 6279: 1 +Line 6280: 0 +Line 6281: 1 +Line 6282: 1 +Line 6283: 0 +Line 6284: 0 +Line 6285: 0 +Line 6286: 0 +Line 6287: 0 +Line 6288: 1 +Line 6289: 1 +Line 6290: 1 +Line 6291: 1 +Line 6292: 1 +Line 6293: 1 +Line 6294: 1 +Line 6295: 0 +Line 6296: 1 +Line 6297: 0 +Line 6298: 1 +Line 6299: 0 +Line 6300: 1 +Line 6301: 0 +Line 6302: 1 +Line 6303: 1 +Line 6304: 0 +Line 6305: 0 +Line 6306: 0 +Line 6307: 0 +Line 6308: 1 +Line 6309: 1 +Line 6310: 1 +Line 6311: 0 +Line 6312: 0 +Line 6313: 1 +Line 6314: 1 +Line 6315: 0 +Line 6316: 0 +Line 6317: 0 +Line 6318: 1 +Line 6319: 1 +Line 6320: 1 +Line 6321: 1 +Line 6322: 1 +Line 6323: 1 +Line 6324: 1 +Line 6325: 1 +Line 6326: 1 +Line 6327: 0 +Line 6328: 1 +Line 6329: 0 +Line 6330: 1 +Line 6331: 0 +Line 6332: 0 +Line 6333: 0 +Line 6334: 0 +Line 6335: 1 +Line 6336: 0 +Line 6337: 0 +Line 6338: 0 +Line 6339: 0 +Line 6340: 1 +Line 6341: 1 +Line 6342: 1 +Line 6343: 1 +Line 6344: 0 +Line 6345: 1 +Line 6346: 1 +Line 6347: 0 +Line 6348: 1 +Line 6349: 1 +Line 6350: 0 +Line 6351: 1 +Line 6352: 1 +Line 6353: 1 +Line 6354: 1 +Line 6355: 1 +Line 6356: 1 +Line 6357: 1 +Line 6358: 1 +Line 6359: 0 +Line 6360: 1 +Line 6361: 0 +Line 6362: 0 +Line 6363: 1 +Line 6364: 1 +Line 6365: 0 +Line 6366: 0 +Line 6367: 0 +Line 6368: 0 +Line 6369: 0 +Line 6370: 0 +Line 6371: 1 +Line 6372: 0 +Line 6373: 0 +Line 6374: 0 +Line 6375: 0 +Line 6376: 0 +Line 6377: 1 +Line 6378: 1 +Line 6379: 1 +Line 6380: 1 +Line 6381: 1 +Line 6382: 0 +Line 6383: 1 +Line 6384: 1 +Line 6385: 1 +Line 6386: 1 +Line 6387: 1 +Line 6388: 1 +Line 6389: 1 +Line 6390: 1 +Line 6391: 0 +Line 6392: 1 +Line 6393: 0 +Line 6394: 0 +Line 6395: 0 +Line 6396: 1 +Line 6397: 1 +Line 6398: 1 +Line 6399: 1 +Line 6400: 0 +Line 6401: 0 +Line 6402: 0 +Line 6403: 1 +Line 6404: 0 +Line 6405: 0 +Line 6406: 0 +Line 6407: 1 +Line 6408: 1 +Line 6409: 0 +Line 6410: 0 +Line 6411: 1 +Line 6412: 0 +Line 6413: 1 +Line 6414: 0 +Line 6415: 0 +Line 6416: 1 +Line 6417: 1 +Line 6418: 1 +Line 6419: 1 +Line 6420: 1 +Line 6421: 1 +Line 6422: 1 +Line 6423: 0 +Line 6424: 1 +Line 6425: 0 +Line 6426: 0 +Line 6427: 0 +Line 6428: 0 +Line 6429: 1 +Line 6430: 1 +Line 6431: 1 +Line 6432: 0 +Line 6433: 0 +Line 6434: 0 +Line 6435: 1 +Line 6436: 0 +Line 6437: 0 +Line 6438: 1 +Line 6439: 0 +Line 6440: 1 +Line 6441: 0 +Line 6442: 1 +Line 6443: 1 +Line 6444: 0 +Line 6445: 0 +Line 6446: 0 +Line 6447: 0 +Line 6448: 1 +Line 6449: 1 +Line 6450: 1 +Line 6451: 1 +Line 6452: 1 +Line 6453: 1 +Line 6454: 1 +Line 6455: 0 +Line 6456: 1 +Line 6457: 0 +Line 6458: 0 +Line 6459: 0 +Line 6460: 0 +Line 6461: 0 +Line 6462: 0 +Line 6463: 0 +Line 6464: 0 +Line 6465: 0 +Line 6466: 0 +Line 6467: 1 +Line 6468: 0 +Line 6469: 0 +Line 6470: 1 +Line 6471: 1 +Line 6472: 1 +Line 6473: 1 +Line 6474: 0 +Line 6475: 1 +Line 6476: 0 +Line 6477: 0 +Line 6478: 1 +Line 6479: 0 +Line 6480: 1 +Line 6481: 1 +Line 6482: 1 +Line 6483: 1 +Line 6484: 1 +Line 6485: 1 +Line 6486: 1 +Line 6487: 0 +Line 6488: 0 +Line 6489: 1 +Line 6490: 1 +Line 6491: 1 +Line 6492: 1 +Line 6493: 0 +Line 6494: 0 +Line 6495: 1 +Line 6496: 0 +Line 6497: 0 +Line 6498: 0 +Line 6499: 1 +Line 6500: 0 +Line 6501: 1 +Line 6502: 0 +Line 6503: 0 +Line 6504: 1 +Line 6505: 1 +Line 6506: 1 +Line 6507: 1 +Line 6508: 1 +Line 6509: 0 +Line 6510: 0 +Line 6511: 1 +Line 6512: 1 +Line 6513: 1 +Line 6514: 1 +Line 6515: 1 +Line 6516: 1 +Line 6517: 1 +Line 6518: 1 +Line 6519: 0 +Line 6520: 0 +Line 6521: 1 +Line 6522: 1 +Line 6523: 1 +Line 6524: 0 +Line 6525: 0 +Line 6526: 1 +Line 6527: 0 +Line 6528: 0 +Line 6529: 0 +Line 6530: 0 +Line 6531: 1 +Line 6532: 0 +Line 6533: 1 +Line 6534: 1 +Line 6535: 0 +Line 6536: 0 +Line 6537: 0 +Line 6538: 1 +Line 6539: 0 +Line 6540: 0 +Line 6541: 1 +Line 6542: 0 +Line 6543: 0 +Line 6544: 1 +Line 6545: 1 +Line 6546: 1 +Line 6547: 1 +Line 6548: 1 +Line 6549: 1 +Line 6550: 1 +Line 6551: 0 +Line 6552: 0 +Line 6553: 1 +Line 6554: 1 +Line 6555: 0 +Line 6556: 1 +Line 6557: 1 +Line 6558: 0 +Line 6559: 0 +Line 6560: 0 +Line 6561: 0 +Line 6562: 0 +Line 6563: 1 +Line 6564: 0 +Line 6565: 1 +Line 6566: 1 +Line 6567: 1 +Line 6568: 0 +Line 6569: 1 +Line 6570: 0 +Line 6571: 1 +Line 6572: 0 +Line 6573: 1 +Line 6574: 0 +Line 6575: 0 +Line 6576: 1 +Line 6577: 1 +Line 6578: 1 +Line 6579: 1 +Line 6580: 1 +Line 6581: 1 +Line 6582: 1 +Line 6583: 0 +Line 6584: 0 +Line 6585: 1 +Line 6586: 1 +Line 6587: 0 +Line 6588: 0 +Line 6589: 1 +Line 6590: 1 +Line 6591: 0 +Line 6592: 0 +Line 6593: 0 +Line 6594: 0 +Line 6595: 1 +Line 6596: 1 +Line 6597: 0 +Line 6598: 0 +Line 6599: 0 +Line 6600: 1 +Line 6601: 0 +Line 6602: 0 +Line 6603: 0 +Line 6604: 1 +Line 6605: 0 +Line 6606: 0 +Line 6607: 0 +Line 6608: 1 +Line 6609: 1 +Line 6610: 1 +Line 6611: 1 +Line 6612: 1 +Line 6613: 1 +Line 6614: 1 +Line 6615: 0 +Line 6616: 0 +Line 6617: 1 +Line 6618: 1 +Line 6619: 0 +Line 6620: 0 +Line 6621: 0 +Line 6622: 0 +Line 6623: 1 +Line 6624: 0 +Line 6625: 0 +Line 6626: 0 +Line 6627: 1 +Line 6628: 1 +Line 6629: 0 +Line 6630: 0 +Line 6631: 1 +Line 6632: 1 +Line 6633: 1 +Line 6634: 0 +Line 6635: 0 +Line 6636: 0 +Line 6637: 0 +Line 6638: 0 +Line 6639: 0 +Line 6640: 1 +Line 6641: 1 +Line 6642: 1 +Line 6643: 1 +Line 6644: 1 +Line 6645: 1 +Line 6646: 1 +Line 6647: 0 +Line 6648: 0 +Line 6649: 1 +Line 6650: 0 +Line 6651: 1 +Line 6652: 1 +Line 6653: 1 +Line 6654: 0 +Line 6655: 1 +Line 6656: 0 +Line 6657: 0 +Line 6658: 0 +Line 6659: 1 +Line 6660: 1 +Line 6661: 0 +Line 6662: 1 +Line 6663: 0 +Line 6664: 1 +Line 6665: 1 +Line 6666: 1 +Line 6667: 1 +Line 6668: 1 +Line 6669: 0 +Line 6670: 1 +Line 6671: 0 +Line 6672: 1 +Line 6673: 1 +Line 6674: 1 +Line 6675: 1 +Line 6676: 1 +Line 6677: 1 +Line 6678: 1 +Line 6679: 0 +Line 6680: 0 +Line 6681: 1 +Line 6682: 0 +Line 6683: 1 +Line 6684: 1 +Line 6685: 0 +Line 6686: 0 +Line 6687: 1 +Line 6688: 0 +Line 6689: 0 +Line 6690: 0 +Line 6691: 1 +Line 6692: 1 +Line 6693: 1 +Line 6694: 0 +Line 6695: 0 +Line 6696: 0 +Line 6697: 0 +Line 6698: 1 +Line 6699: 1 +Line 6700: 1 +Line 6701: 0 +Line 6702: 0 +Line 6703: 0 +Line 6704: 1 +Line 6705: 1 +Line 6706: 1 +Line 6707: 1 +Line 6708: 1 +Line 6709: 1 +Line 6710: 1 +Line 6711: 0 +Line 6712: 0 +Line 6713: 1 +Line 6714: 0 +Line 6715: 1 +Line 6716: 0 +Line 6717: 1 +Line 6718: 1 +Line 6719: 0 +Line 6720: 0 +Line 6721: 0 +Line 6722: 0 +Line 6723: 1 +Line 6724: 1 +Line 6725: 1 +Line 6726: 0 +Line 6727: 1 +Line 6728: 0 +Line 6729: 1 +Line 6730: 1 +Line 6731: 1 +Line 6732: 0 +Line 6733: 1 +Line 6734: 1 +Line 6735: 1 +Line 6736: 1 +Line 6737: 1 +Line 6738: 1 +Line 6739: 1 +Line 6740: 1 +Line 6741: 1 +Line 6742: 1 +Line 6743: 0 +Line 6744: 0 +Line 6745: 1 +Line 6746: 0 +Line 6747: 1 +Line 6748: 0 +Line 6749: 0 +Line 6750: 1 +Line 6751: 1 +Line 6752: 0 +Line 6753: 0 +Line 6754: 0 +Line 6755: 1 +Line 6756: 1 +Line 6757: 1 +Line 6758: 1 +Line 6759: 0 +Line 6760: 1 +Line 6761: 0 +Line 6762: 1 +Line 6763: 1 +Line 6764: 1 +Line 6765: 0 +Line 6766: 0 +Line 6767: 1 +Line 6768: 1 +Line 6769: 1 +Line 6770: 1 +Line 6771: 1 +Line 6772: 1 +Line 6773: 1 +Line 6774: 1 +Line 6775: 0 +Line 6776: 0 +Line 6777: 1 +Line 6778: 0 +Line 6779: 1 +Line 6780: 0 +Line 6781: 0 +Line 6782: 0 +Line 6783: 0 +Line 6784: 0 +Line 6785: 0 +Line 6786: 0 +Line 6787: 1 +Line 6788: 1 +Line 6789: 1 +Line 6790: 1 +Line 6791: 1 +Line 6792: 1 +Line 6793: 1 +Line 6794: 1 +Line 6795: 1 +Line 6796: 1 +Line 6797: 1 +Line 6798: 0 +Line 6799: 0 +Line 6800: 1 +Line 6801: 1 +Line 6802: 1 +Line 6803: 1 +Line 6804: 1 +Line 6805: 1 +Line 6806: 1 +Line 6807: 0 +Line 6808: 0 +Line 6809: 1 +Line 6810: 0 +Line 6811: 0 +Line 6812: 1 +Line 6813: 1 +Line 6814: 1 +Line 6815: 1 +Line 6816: 0 +Line 6817: 0 +Line 6818: 1 +Line 6819: 0 +Line 6820: 0 +Line 6821: 0 +Line 6822: 0 +Line 6823: 1 +Line 6824: 0 +Line 6825: 1 +Line 6826: 0 +Line 6827: 0 +Line 6828: 0 +Line 6829: 0 +Line 6830: 0 +Line 6831: 0 +Line 6832: 1 +Line 6833: 1 +Line 6834: 1 +Line 6835: 1 +Line 6836: 1 +Line 6837: 1 +Line 6838: 1 +Line 6839: 0 +Line 6840: 0 +Line 6841: 1 +Line 6842: 0 +Line 6843: 0 +Line 6844: 1 +Line 6845: 1 +Line 6846: 1 +Line 6847: 0 +Line 6848: 0 +Line 6849: 0 +Line 6850: 1 +Line 6851: 0 +Line 6852: 0 +Line 6853: 0 +Line 6854: 1 +Line 6855: 0 +Line 6856: 1 +Line 6857: 0 +Line 6858: 0 +Line 6859: 0 +Line 6860: 0 +Line 6861: 1 +Line 6862: 0 +Line 6863: 1 +Line 6864: 1 +Line 6865: 1 +Line 6866: 1 +Line 6867: 1 +Line 6868: 1 +Line 6869: 1 +Line 6870: 1 +Line 6871: 0 +Line 6872: 0 +Line 6873: 1 +Line 6874: 0 +Line 6875: 0 +Line 6876: 1 +Line 6877: 1 +Line 6878: 0 +Line 6879: 1 +Line 6880: 0 +Line 6881: 0 +Line 6882: 1 +Line 6883: 0 +Line 6884: 0 +Line 6885: 0 +Line 6886: 1 +Line 6887: 1 +Line 6888: 1 +Line 6889: 1 +Line 6890: 0 +Line 6891: 0 +Line 6892: 1 +Line 6893: 0 +Line 6894: 1 +Line 6895: 0 +Line 6896: 1 +Line 6897: 1 +Line 6898: 1 +Line 6899: 1 +Line 6900: 1 +Line 6901: 1 +Line 6902: 1 +Line 6903: 0 +Line 6904: 0 +Line 6905: 1 +Line 6906: 0 +Line 6907: 0 +Line 6908: 1 +Line 6909: 1 +Line 6910: 0 +Line 6911: 1 +Line 6912: 0 +Line 6913: 0 +Line 6914: 1 +Line 6915: 0 +Line 6916: 0 +Line 6917: 1 +Line 6918: 0 +Line 6919: 1 +Line 6920: 0 +Line 6921: 0 +Line 6922: 0 +Line 6923: 0 +Line 6924: 1 +Line 6925: 1 +Line 6926: 1 +Line 6927: 1 +Line 6928: 1 +Line 6929: 1 +Line 6930: 1 +Line 6931: 1 +Line 6932: 1 +Line 6933: 1 +Line 6934: 1 +Line 6935: 0 +Line 6936: 0 +Line 6937: 1 +Line 6938: 0 +Line 6939: 0 +Line 6940: 1 +Line 6941: 1 +Line 6942: 1 +Line 6943: 0 +Line 6944: 0 +Line 6945: 0 +Line 6946: 1 +Line 6947: 0 +Line 6948: 0 +Line 6949: 1 +Line 6950: 1 +Line 6951: 0 +Line 6952: 0 +Line 6953: 1 +Line 6954: 0 +Line 6955: 1 +Line 6956: 0 +Line 6957: 0 +Line 6958: 1 +Line 6959: 1 +Line 6960: 1 +Line 6961: 1 +Line 6962: 1 +Line 6963: 1 +Line 6964: 1 +Line 6965: 1 +Line 6966: 1 +Line 6967: 0 +Line 6968: 0 +Line 6969: 1 +Line 6970: 0 +Line 6971: 0 +Line 6972: 1 +Line 6973: 1 +Line 6974: 1 +Line 6975: 1 +Line 6976: 0 +Line 6977: 0 +Line 6978: 1 +Line 6979: 0 +Line 6980: 0 +Line 6981: 1 +Line 6982: 1 +Line 6983: 1 +Line 6984: 1 +Line 6985: 0 +Line 6986: 0 +Line 6987: 1 +Line 6988: 0 +Line 6989: 1 +Line 6990: 1 +Line 6991: 0 +Line 6992: 1 +Line 6993: 1 +Line 6994: 1 +Line 6995: 1 +Line 6996: 1 +Line 6997: 1 +Line 6998: 1 +Line 6999: 0 +Line 7000: 0 +Line 7001: 1 +Line 7002: 0 +Line 7003: 1 +Line 7004: 0 +Line 7005: 0 +Line 7006: 0 +Line 7007: 0 +Line 7008: 0 +Line 7009: 0 +Line 7010: 1 +Line 7011: 0 +Line 7012: 1 +Line 7013: 0 +Line 7014: 0 +Line 7015: 0 +Line 7016: 1 +Line 7017: 1 +Line 7018: 0 +Line 7019: 1 +Line 7020: 1 +Line 7021: 0 +Line 7022: 0 +Line 7023: 0 +Line 7024: 1 +Line 7025: 1 +Line 7026: 1 +Line 7027: 1 +Line 7028: 1 +Line 7029: 1 +Line 7030: 1 +Line 7031: 0 +Line 7032: 0 +Line 7033: 1 +Line 7034: 0 +Line 7035: 1 +Line 7036: 0 +Line 7037: 0 +Line 7038: 1 +Line 7039: 1 +Line 7040: 0 +Line 7041: 0 +Line 7042: 1 +Line 7043: 0 +Line 7044: 1 +Line 7045: 0 +Line 7046: 1 +Line 7047: 0 +Line 7048: 0 +Line 7049: 0 +Line 7050: 0 +Line 7051: 1 +Line 7052: 0 +Line 7053: 1 +Line 7054: 1 +Line 7055: 1 +Line 7056: 1 +Line 7057: 1 +Line 7058: 1 +Line 7059: 1 +Line 7060: 1 +Line 7061: 1 +Line 7062: 1 +Line 7063: 0 +Line 7064: 0 +Line 7065: 1 +Line 7066: 0 +Line 7067: 1 +Line 7068: 0 +Line 7069: 1 +Line 7070: 1 +Line 7071: 0 +Line 7072: 0 +Line 7073: 0 +Line 7074: 1 +Line 7075: 0 +Line 7076: 1 +Line 7077: 0 +Line 7078: 1 +Line 7079: 1 +Line 7080: 0 +Line 7081: 1 +Line 7082: 0 +Line 7083: 1 +Line 7084: 0 +Line 7085: 1 +Line 7086: 0 +Line 7087: 1 +Line 7088: 1 +Line 7089: 1 +Line 7090: 1 +Line 7091: 1 +Line 7092: 1 +Line 7093: 1 +Line 7094: 1 +Line 7095: 0 +Line 7096: 0 +Line 7097: 1 +Line 7098: 0 +Line 7099: 1 +Line 7100: 1 +Line 7101: 0 +Line 7102: 0 +Line 7103: 1 +Line 7104: 0 +Line 7105: 0 +Line 7106: 1 +Line 7107: 0 +Line 7108: 1 +Line 7109: 1 +Line 7110: 0 +Line 7111: 0 +Line 7112: 1 +Line 7113: 0 +Line 7114: 0 +Line 7115: 0 +Line 7116: 1 +Line 7117: 1 +Line 7118: 1 +Line 7119: 1 +Line 7120: 1 +Line 7121: 1 +Line 7122: 1 +Line 7123: 1 +Line 7124: 1 +Line 7125: 1 +Line 7126: 1 +Line 7127: 0 +Line 7128: 0 +Line 7129: 1 +Line 7130: 0 +Line 7131: 1 +Line 7132: 1 +Line 7133: 1 +Line 7134: 0 +Line 7135: 1 +Line 7136: 0 +Line 7137: 0 +Line 7138: 1 +Line 7139: 0 +Line 7140: 1 +Line 7141: 1 +Line 7142: 0 +Line 7143: 1 +Line 7144: 1 +Line 7145: 1 +Line 7146: 0 +Line 7147: 0 +Line 7148: 0 +Line 7149: 1 +Line 7150: 1 +Line 7151: 1 +Line 7152: 1 +Line 7153: 1 +Line 7154: 1 +Line 7155: 1 +Line 7156: 1 +Line 7157: 1 +Line 7158: 1 +Line 7159: 0 +Line 7160: 0 +Line 7161: 1 +Line 7162: 1 +Line 7163: 0 +Line 7164: 0 +Line 7165: 0 +Line 7166: 0 +Line 7167: 1 +Line 7168: 0 +Line 7169: 0 +Line 7170: 1 +Line 7171: 0 +Line 7172: 1 +Line 7173: 1 +Line 7174: 1 +Line 7175: 0 +Line 7176: 1 +Line 7177: 1 +Line 7178: 1 +Line 7179: 1 +Line 7180: 1 +Line 7181: 0 +Line 7182: 1 +Line 7183: 1 +Line 7184: 1 +Line 7185: 1 +Line 7186: 1 +Line 7187: 1 +Line 7188: 1 +Line 7189: 1 +Line 7190: 1 +Line 7191: 0 +Line 7192: 0 +Line 7193: 1 +Line 7194: 1 +Line 7195: 0 +Line 7196: 0 +Line 7197: 1 +Line 7198: 1 +Line 7199: 0 +Line 7200: 0 +Line 7201: 0 +Line 7202: 1 +Line 7203: 1 +Line 7204: 0 +Line 7205: 0 +Line 7206: 0 +Line 7207: 0 +Line 7208: 0 +Line 7209: 0 +Line 7210: 1 +Line 7211: 0 +Line 7212: 1 +Line 7213: 0 +Line 7214: 1 +Line 7215: 1 +Line 7216: 1 +Line 7217: 1 +Line 7218: 1 +Line 7219: 1 +Line 7220: 1 +Line 7221: 1 +Line 7222: 1 +Line 7223: 0 +Line 7224: 0 +Line 7225: 1 +Line 7226: 1 +Line 7227: 0 +Line 7228: 1 +Line 7229: 1 +Line 7230: 0 +Line 7231: 0 +Line 7232: 0 +Line 7233: 0 +Line 7234: 1 +Line 7235: 1 +Line 7236: 0 +Line 7237: 0 +Line 7238: 0 +Line 7239: 1 +Line 7240: 0 +Line 7241: 1 +Line 7242: 0 +Line 7243: 1 +Line 7244: 0 +Line 7245: 1 +Line 7246: 1 +Line 7247: 0 +Line 7248: 1 +Line 7249: 1 +Line 7250: 1 +Line 7251: 1 +Line 7252: 1 +Line 7253: 1 +Line 7254: 1 +Line 7255: 0 +Line 7256: 0 +Line 7257: 1 +Line 7258: 1 +Line 7259: 1 +Line 7260: 0 +Line 7261: 0 +Line 7262: 1 +Line 7263: 0 +Line 7264: 0 +Line 7265: 0 +Line 7266: 1 +Line 7267: 1 +Line 7268: 0 +Line 7269: 0 +Line 7270: 1 +Line 7271: 0 +Line 7272: 0 +Line 7273: 1 +Line 7274: 1 +Line 7275: 1 +Line 7276: 1 +Line 7277: 1 +Line 7278: 0 +Line 7279: 1 +Line 7280: 1 +Line 7281: 1 +Line 7282: 1 +Line 7283: 1 +Line 7284: 1 +Line 7285: 1 +Line 7286: 1 +Line 7287: 0 +Line 7288: 0 +Line 7289: 1 +Line 7290: 1 +Line 7291: 1 +Line 7292: 1 +Line 7293: 0 +Line 7294: 0 +Line 7295: 1 +Line 7296: 0 +Line 7297: 0 +Line 7298: 1 +Line 7299: 1 +Line 7300: 0 +Line 7301: 0 +Line 7302: 1 +Line 7303: 1 +Line 7304: 1 +Line 7305: 0 +Line 7306: 0 +Line 7307: 1 +Line 7308: 1 +Line 7309: 1 +Line 7310: 1 +Line 7311: 1 +Line 7312: 1 +Line 7313: 1 +Line 7314: 1 +Line 7315: 1 +Line 7316: 1 +Line 7317: 1 +Line 7318: 1 +Line 7319: 0 +Line 7320: 1 +Line 7321: 0 +Line 7322: 0 +Line 7323: 0 +Line 7324: 0 +Line 7325: 0 +Line 7326: 0 +Line 7327: 0 +Line 7328: 0 +Line 7329: 0 +Line 7330: 1 +Line 7331: 1 +Line 7332: 0 +Line 7333: 1 +Line 7334: 0 +Line 7335: 0 +Line 7336: 1 +Line 7337: 0 +Line 7338: 1 +Line 7339: 1 +Line 7340: 1 +Line 7341: 1 +Line 7342: 0 +Line 7343: 0 +Line 7344: 1 +Line 7345: 1 +Line 7346: 1 +Line 7347: 1 +Line 7348: 1 +Line 7349: 1 +Line 7350: 1 +Line 7351: 0 +Line 7352: 1 +Line 7353: 0 +Line 7354: 0 +Line 7355: 0 +Line 7356: 0 +Line 7357: 1 +Line 7358: 1 +Line 7359: 1 +Line 7360: 0 +Line 7361: 0 +Line 7362: 1 +Line 7363: 1 +Line 7364: 0 +Line 7365: 1 +Line 7366: 0 +Line 7367: 1 +Line 7368: 1 +Line 7369: 1 +Line 7370: 0 +Line 7371: 1 +Line 7372: 0 +Line 7373: 0 +Line 7374: 1 +Line 7375: 0 +Line 7376: 1 +Line 7377: 1 +Line 7378: 1 +Line 7379: 1 +Line 7380: 1 +Line 7381: 1 +Line 7382: 1 +Line 7383: 0 +Line 7384: 1 +Line 7385: 0 +Line 7386: 0 +Line 7387: 0 +Line 7388: 1 +Line 7389: 1 +Line 7390: 1 +Line 7391: 1 +Line 7392: 0 +Line 7393: 0 +Line 7394: 1 +Line 7395: 1 +Line 7396: 0 +Line 7397: 1 +Line 7398: 1 +Line 7399: 0 +Line 7400: 1 +Line 7401: 1 +Line 7402: 1 +Line 7403: 0 +Line 7404: 0 +Line 7405: 0 +Line 7406: 1 +Line 7407: 0 +Line 7408: 1 +Line 7409: 1 +Line 7410: 1 +Line 7411: 1 +Line 7412: 1 +Line 7413: 1 +Line 7414: 1 +Line 7415: 0 +Line 7416: 1 +Line 7417: 0 +Line 7418: 0 +Line 7419: 1 +Line 7420: 1 +Line 7421: 0 +Line 7422: 0 +Line 7423: 0 +Line 7424: 0 +Line 7425: 0 +Line 7426: 1 +Line 7427: 1 +Line 7428: 0 +Line 7429: 1 +Line 7430: 1 +Line 7431: 1 +Line 7432: 1 +Line 7433: 1 +Line 7434: 1 +Line 7435: 0 +Line 7436: 1 +Line 7437: 1 +Line 7438: 0 +Line 7439: 0 +Line 7440: 1 +Line 7441: 1 +Line 7442: 1 +Line 7443: 1 +Line 7444: 1 +Line 7445: 1 +Line 7446: 1 +Line 7447: 0 +Line 7448: 1 +Line 7449: 0 +Line 7450: 1 +Line 7451: 0 +Line 7452: 0 +Line 7453: 0 +Line 7454: 0 +Line 7455: 1 +Line 7456: 0 +Line 7457: 0 +Line 7458: 1 +Line 7459: 1 +Line 7460: 1 +Line 7461: 0 +Line 7462: 0 +Line 7463: 0 +Line 7464: 1 +Line 7465: 1 +Line 7466: 1 +Line 7467: 0 +Line 7468: 1 +Line 7469: 1 +Line 7470: 1 +Line 7471: 1 +Line 7472: 1 +Line 7473: 1 +Line 7474: 1 +Line 7475: 1 +Line 7476: 1 +Line 7477: 1 +Line 7478: 1 +Line 7479: 0 +Line 7480: 1 +Line 7481: 0 +Line 7482: 1 +Line 7483: 0 +Line 7484: 1 +Line 7485: 0 +Line 7486: 1 +Line 7487: 1 +Line 7488: 0 +Line 7489: 0 +Line 7490: 1 +Line 7491: 1 +Line 7492: 1 +Line 7493: 0 +Line 7494: 0 +Line 7495: 1 +Line 7496: 1 +Line 7497: 1 +Line 7498: 1 +Line 7499: 0 +Line 7500: 1 +Line 7501: 0 +Line 7502: 1 +Line 7503: 0 +Line 7504: 1 +Line 7505: 1 +Line 7506: 1 +Line 7507: 1 +Line 7508: 1 +Line 7509: 1 +Line 7510: 1 +Line 7511: 0 +Line 7512: 1 +Line 7513: 0 +Line 7514: 1 +Line 7515: 1 +Line 7516: 0 +Line 7517: 1 +Line 7518: 0 +Line 7519: 1 +Line 7520: 0 +Line 7521: 0 +Line 7522: 1 +Line 7523: 1 +Line 7524: 1 +Line 7525: 0 +Line 7526: 1 +Line 7527: 0 +Line 7528: 1 +Line 7529: 1 +Line 7530: 0 +Line 7531: 1 +Line 7532: 1 +Line 7533: 1 +Line 7534: 1 +Line 7535: 0 +Line 7536: 1 +Line 7537: 1 +Line 7538: 1 +Line 7539: 1 +Line 7540: 1 +Line 7541: 1 +Line 7542: 1 +Line 7543: 0 +Line 7544: 1 +Line 7545: 0 +Line 7546: 1 +Line 7547: 1 +Line 7548: 1 +Line 7549: 1 +Line 7550: 1 +Line 7551: 1 +Line 7552: 0 +Line 7553: 0 +Line 7554: 1 +Line 7555: 1 +Line 7556: 1 +Line 7557: 0 +Line 7558: 1 +Line 7559: 1 +Line 7560: 1 +Line 7561: 1 +Line 7562: 0 +Line 7563: 0 +Line 7564: 1 +Line 7565: 0 +Line 7566: 1 +Line 7567: 0 +Line 7568: 1 +Line 7569: 1 +Line 7570: 1 +Line 7571: 1 +Line 7572: 1 +Line 7573: 1 +Line 7574: 1 +Line 7575: 0 +Line 7576: 1 +Line 7577: 1 +Line 7578: 0 +Line 7579: 0 +Line 7580: 1 +Line 7581: 0 +Line 7582: 1 +Line 7583: 0 +Line 7584: 0 +Line 7585: 0 +Line 7586: 1 +Line 7587: 1 +Line 7588: 1 +Line 7589: 1 +Line 7590: 0 +Line 7591: 0 +Line 7592: 1 +Line 7593: 0 +Line 7594: 1 +Line 7595: 0 +Line 7596: 1 +Line 7597: 1 +Line 7598: 0 +Line 7599: 1 +Line 7600: 1 +Line 7601: 1 +Line 7602: 1 +Line 7603: 1 +Line 7604: 1 +Line 7605: 1 +Line 7606: 1 +Line 7607: 0 +Line 7608: 1 +Line 7609: 1 +Line 7610: 0 +Line 7611: 1 +Line 7612: 0 +Line 7613: 1 +Line 7614: 0 +Line 7615: 1 +Line 7616: 0 +Line 7617: 0 +Line 7618: 1 +Line 7619: 1 +Line 7620: 1 +Line 7621: 1 +Line 7622: 0 +Line 7623: 1 +Line 7624: 1 +Line 7625: 0 +Line 7626: 0 +Line 7627: 0 +Line 7628: 1 +Line 7629: 0 +Line 7630: 0 +Line 7631: 1 +Line 7632: 1 +Line 7633: 1 +Line 7634: 1 +Line 7635: 1 +Line 7636: 1 +Line 7637: 1 +Line 7638: 1 +Line 7639: 0 +Line 7640: 1 +Line 7641: 1 +Line 7642: 1 +Line 7643: 0 +Line 7644: 0 +Line 7645: 0 +Line 7646: 0 +Line 7647: 1 +Line 7648: 0 +Line 7649: 0 +Line 7650: 1 +Line 7651: 1 +Line 7652: 1 +Line 7653: 1 +Line 7654: 1 +Line 7655: 0 +Line 7656: 0 +Line 7657: 1 +Line 7658: 0 +Line 7659: 1 +Line 7660: 1 +Line 7661: 0 +Line 7662: 1 +Line 7663: 1 +Line 7664: 1 +Line 7665: 1 +Line 7666: 1 +Line 7667: 1 +Line 7668: 1 +Line 7669: 1 +Line 7670: 1 +Line 7671: 0 +Line 7672: 1 +Line 7673: 1 +Line 7674: 1 +Line 7675: 0 +Line 7676: 1 +Line 7677: 1 +Line 7678: 0 +Line 7679: 1 +Line 7680: 0 +Line 7681: 0 +Line 7682: 1 +Line 7683: 1 +Line 7684: 1 +Line 7685: 1 +Line 7686: 1 +Line 7687: 1 +Line 7688: 0 +Line 7689: 0 +Line 7690: 1 +Line 7691: 0 +Line 7692: 0 +Line 7693: 1 +Line 7694: 0 +Line 7695: 0 +Line 7696: 1 +Line 7697: 1 +Line 7698: 1 +Line 7699: 1 +Line 7700: 1 +Line 7701: 1 +Line 7702: 1 +Line 7703: 0 +Line 7704: 1 +Line 7705: 1 +Line 7706: 1 +Line 7707: 1 +Line 7708: 1 +Line 7709: 0 +Line 7710: 0 +Line 7711: 1 +Line 7712: 0 +Line 7713: 0 +Line 7714: 1 +Line 7715: 1 +Line 7716: 1 +Line 7717: 1 +Line 7718: 1 +Line 7719: 1 +Line 7720: 1 +Line 7721: 1 +Line 7722: 1 +Line 7723: 0 +Line 7724: 0 +Line 7725: 1 +Line 7726: 0 +Line 7727: 0 +Line 7728: 1 +Line 7729: 1 +Line 7730: 1 +Line 7731: 1 +Line 7732: 1 +Line 7733: 1 +Line 7734: 1 +Line 7735: 1 +Line 7736: 0 +Line 7737: 0 +Line 7738: 0 +Line 7739: 0 +Line 7740: 0 +Line 7741: 1 +Line 7742: 1 +Line 7743: 0 +Line 7744: 0 +Line 7745: 1 +Line 7746: 0 +Line 7747: 0 +Line 7748: 0 +Line 7749: 0 +Line 7750: 0 +Line 7751: 0 +Line 7752: 1 +Line 7753: 0 +Line 7754: 0 +Line 7755: 1 +Line 7756: 1 +Line 7757: 0 +Line 7758: 1 +Line 7759: 1 +Line 7760: 1 +Line 7761: 1 +Line 7762: 1 +Line 7763: 1 +Line 7764: 1 +Line 7765: 1 +Line 7766: 1 +Line 7767: 1 +Line 7768: 0 +Line 7769: 0 +Line 7770: 0 +Line 7771: 1 +Line 7772: 0 +Line 7773: 0 +Line 7774: 1 +Line 7775: 1 +Line 7776: 0 +Line 7777: 1 +Line 7778: 0 +Line 7779: 0 +Line 7780: 0 +Line 7781: 0 +Line 7782: 0 +Line 7783: 1 +Line 7784: 0 +Line 7785: 1 +Line 7786: 0 +Line 7787: 0 +Line 7788: 0 +Line 7789: 1 +Line 7790: 1 +Line 7791: 1 +Line 7792: 1 +Line 7793: 1 +Line 7794: 1 +Line 7795: 1 +Line 7796: 1 +Line 7797: 1 +Line 7798: 1 +Line 7799: 1 +Line 7800: 0 +Line 7801: 0 +Line 7802: 1 +Line 7803: 0 +Line 7804: 0 +Line 7805: 0 +Line 7806: 0 +Line 7807: 0 +Line 7808: 0 +Line 7809: 1 +Line 7810: 0 +Line 7811: 0 +Line 7812: 0 +Line 7813: 0 +Line 7814: 0 +Line 7815: 1 +Line 7816: 1 +Line 7817: 1 +Line 7818: 1 +Line 7819: 0 +Line 7820: 1 +Line 7821: 0 +Line 7822: 1 +Line 7823: 0 +Line 7824: 1 +Line 7825: 1 +Line 7826: 1 +Line 7827: 1 +Line 7828: 1 +Line 7829: 1 +Line 7830: 1 +Line 7831: 1 +Line 7832: 0 +Line 7833: 0 +Line 7834: 1 +Line 7835: 0 +Line 7836: 1 +Line 7837: 1 +Line 7838: 1 +Line 7839: 0 +Line 7840: 0 +Line 7841: 1 +Line 7842: 0 +Line 7843: 0 +Line 7844: 0 +Line 7845: 0 +Line 7846: 1 +Line 7847: 0 +Line 7848: 1 +Line 7849: 0 +Line 7850: 0 +Line 7851: 0 +Line 7852: 0 +Line 7853: 0 +Line 7854: 1 +Line 7855: 0 +Line 7856: 1 +Line 7857: 1 +Line 7858: 1 +Line 7859: 1 +Line 7860: 1 +Line 7861: 1 +Line 7862: 1 +Line 7863: 1 +Line 7864: 0 +Line 7865: 0 +Line 7866: 1 +Line 7867: 1 +Line 7868: 1 +Line 7869: 0 +Line 7870: 1 +Line 7871: 1 +Line 7872: 0 +Line 7873: 1 +Line 7874: 0 +Line 7875: 0 +Line 7876: 0 +Line 7877: 0 +Line 7878: 1 +Line 7879: 1 +Line 7880: 0 +Line 7881: 0 +Line 7882: 0 +Line 7883: 1 +Line 7884: 0 +Line 7885: 0 +Line 7886: 0 +Line 7887: 0 +Line 7888: 1 +Line 7889: 1 +Line 7890: 1 +Line 7891: 1 +Line 7892: 1 +Line 7893: 1 +Line 7894: 1 +Line 7895: 1 +Line 7896: 0 +Line 7897: 1 +Line 7898: 0 +Line 7899: 0 +Line 7900: 1 +Line 7901: 0 +Line 7902: 1 +Line 7903: 0 +Line 7904: 0 +Line 7905: 1 +Line 7906: 0 +Line 7907: 0 +Line 7908: 0 +Line 7909: 0 +Line 7910: 1 +Line 7911: 1 +Line 7912: 1 +Line 7913: 0 +Line 7914: 0 +Line 7915: 1 +Line 7916: 0 +Line 7917: 0 +Line 7918: 1 +Line 7919: 1 +Line 7920: 1 +Line 7921: 1 +Line 7922: 1 +Line 7923: 1 +Line 7924: 1 +Line 7925: 1 +Line 7926: 1 +Line 7927: 1 +Line 7928: 0 +Line 7929: 1 +Line 7930: 0 +Line 7931: 1 +Line 7932: 1 +Line 7933: 0 +Line 7934: 0 +Line 7935: 0 +Line 7936: 0 +Line 7937: 1 +Line 7938: 0 +Line 7939: 0 +Line 7940: 0 +Line 7941: 1 +Line 7942: 0 +Line 7943: 0 +Line 7944: 0 +Line 7945: 0 +Line 7946: 0 +Line 7947: 0 +Line 7948: 1 +Line 7949: 0 +Line 7950: 1 +Line 7951: 1 +Line 7952: 1 +Line 7953: 1 +Line 7954: 1 +Line 7955: 1 +Line 7956: 1 +Line 7957: 1 +Line 7958: 1 +Line 7959: 1 +Line 7960: 0 +Line 7961: 1 +Line 7962: 1 +Line 7963: 0 +Line 7964: 0 +Line 7965: 1 +Line 7966: 1 +Line 7967: 1 +Line 7968: 0 +Line 7969: 1 +Line 7970: 0 +Line 7971: 0 +Line 7972: 0 +Line 7973: 1 +Line 7974: 0 +Line 7975: 0 +Line 7976: 0 +Line 7977: 1 +Line 7978: 1 +Line 7979: 1 +Line 7980: 1 +Line 7981: 0 +Line 7982: 0 +Line 7983: 0 +Line 7984: 1 +Line 7985: 1 +Line 7986: 1 +Line 7987: 1 +Line 7988: 1 +Line 7989: 1 +Line 7990: 1 +Line 7991: 1 +Line 7992: 0 +Line 7993: 1 +Line 7994: 1 +Line 7995: 1 +Line 7996: 0 +Line 7997: 1 +Line 7998: 0 +Line 7999: 1 +Line 8000: 0 +Line 8001: 1 +Line 8002: 0 +Line 8003: 0 +Line 8004: 0 +Line 8005: 1 +Line 8006: 0 +Line 8007: 0 +Line 8008: 1 +Line 8009: 1 +Line 8010: 0 +Line 8011: 1 +Line 8012: 1 +Line 8013: 0 +Line 8014: 1 +Line 8015: 1 +Line 8016: 1 +Line 8017: 1 +Line 8018: 1 +Line 8019: 1 +Line 8020: 1 +Line 8021: 1 +Line 8022: 1 +Line 8023: 1 +Line 8024: 1 +Line 8025: 0 +Line 8026: 0 +Line 8027: 0 +Line 8028: 0 +Line 8029: 1 +Line 8030: 0 +Line 8031: 0 +Line 8032: 0 +Line 8033: 1 +Line 8034: 0 +Line 8035: 0 +Line 8036: 0 +Line 8037: 1 +Line 8038: 0 +Line 8039: 1 +Line 8040: 0 +Line 8041: 0 +Line 8042: 1 +Line 8043: 1 +Line 8044: 0 +Line 8045: 0 +Line 8046: 1 +Line 8047: 0 +Line 8048: 1 +Line 8049: 1 +Line 8050: 1 +Line 8051: 1 +Line 8052: 1 +Line 8053: 1 +Line 8054: 1 +Line 8055: 1 +Line 8056: 1 +Line 8057: 0 +Line 8058: 0 +Line 8059: 1 +Line 8060: 0 +Line 8061: 1 +Line 8062: 0 +Line 8063: 0 +Line 8064: 0 +Line 8065: 1 +Line 8066: 0 +Line 8067: 0 +Line 8068: 0 +Line 8069: 1 +Line 8070: 0 +Line 8071: 1 +Line 8072: 0 +Line 8073: 1 +Line 8074: 1 +Line 8075: 1 +Line 8076: 1 +Line 8077: 1 +Line 8078: 0 +Line 8079: 1 +Line 8080: 1 +Line 8081: 1 +Line 8082: 1 +Line 8083: 1 +Line 8084: 1 +Line 8085: 1 +Line 8086: 1 +Line 8087: 1 +Line 8088: 1 +Line 8089: 0 +Line 8090: 1 +Line 8091: 0 +Line 8092: 0 +Line 8093: 0 +Line 8094: 1 +Line 8095: 1 +Line 8096: 0 +Line 8097: 1 +Line 8098: 0 +Line 8099: 0 +Line 8100: 0 +Line 8101: 1 +Line 8102: 0 +Line 8103: 1 +Line 8104: 1 +Line 8105: 0 +Line 8106: 1 +Line 8107: 1 +Line 8108: 1 +Line 8109: 1 +Line 8110: 0 +Line 8111: 1 +Line 8112: 1 +Line 8113: 1 +Line 8114: 1 +Line 8115: 1 +Line 8116: 1 +Line 8117: 1 +Line 8118: 1 +Line 8119: 1 +Line 8120: 1 +Line 8121: 0 +Line 8122: 1 +Line 8123: 1 +Line 8124: 0 +Line 8125: 0 +Line 8126: 1 +Line 8127: 0 +Line 8128: 0 +Line 8129: 1 +Line 8130: 0 +Line 8131: 0 +Line 8132: 0 +Line 8133: 1 +Line 8134: 0 +Line 8135: 1 +Line 8136: 1 +Line 8137: 1 +Line 8138: 1 +Line 8139: 1 +Line 8140: 0 +Line 8141: 0 +Line 8142: 1 +Line 8143: 0 +Line 8144: 1 +Line 8145: 1 +Line 8146: 1 +Line 8147: 1 +Line 8148: 1 +Line 8149: 1 +Line 8150: 1 +Line 8151: 1 +Line 8152: 1 +Line 8153: 1 +Line 8154: 0 +Line 8155: 0 +Line 8156: 0 +Line 8157: 0 +Line 8158: 1 +Line 8159: 0 +Line 8160: 0 +Line 8161: 1 +Line 8162: 0 +Line 8163: 0 +Line 8164: 0 +Line 8165: 1 +Line 8166: 1 +Line 8167: 0 +Line 8168: 0 +Line 8169: 0 +Line 8170: 0 +Line 8171: 1 +Line 8172: 1 +Line 8173: 0 +Line 8174: 1 +Line 8175: 1 +Line 8176: 1 +Line 8177: 1 +Line 8178: 1 +Line 8179: 1 +Line 8180: 1 +Line 8181: 1 +Line 8182: 1 +Line 8183: 1 +Line 8184: 1 +Line 8185: 1 +Line 8186: 0 +Line 8187: 1 +Line 8188: 0 +Line 8189: 0 +Line 8190: 0 +Line 8191: 1 +Line 8192: 0 +Line 8193: 1 +Line 8194: 0 +Line 8195: 0 +Line 8196: 0 +Line 8197: 1 +Line 8198: 1 +Line 8199: 0 +Line 8200: 0 +Line 8201: 0 +Line 8202: 1 +Line 8203: 1 +Line 8204: 1 +Line 8205: 0 +Line 8206: 0 +Line 8207: 0 +Line 8208: 1 +Line 8209: 1 +Line 8210: 1 +Line 8211: 1 +Line 8212: 1 +Line 8213: 1 +Line 8214: 1 +Line 8215: 1 +Line 8216: 1 +Line 8217: 1 +Line 8218: 1 +Line 8219: 0 +Line 8220: 0 +Line 8221: 0 +Line 8222: 0 +Line 8223: 1 +Line 8224: 0 +Line 8225: 1 +Line 8226: 0 +Line 8227: 0 +Line 8228: 0 +Line 8229: 1 +Line 8230: 1 +Line 8231: 0 +Line 8232: 0 +Line 8233: 1 +Line 8234: 0 +Line 8235: 0 +Line 8236: 1 +Line 8237: 0 +Line 8238: 1 +Line 8239: 0 +Line 8240: 1 +Line 8241: 1 +Line 8242: 1 +Line 8243: 1 +Line 8244: 1 +Line 8245: 1 +Line 8246: 1 +Line 8247: 1 +Line 8248: 1 +Line 8249: 1 +Line 8250: 1 +Line 8251: 1 +Line 8252: 0 +Line 8253: 0 +Line 8254: 0 +Line 8255: 1 +Line 8256: 0 +Line 8257: 1 +Line 8258: 0 +Line 8259: 0 +Line 8260: 0 +Line 8261: 1 +Line 8262: 1 +Line 8263: 0 +Line 8264: 0 +Line 8265: 1 +Line 8266: 0 +Line 8267: 1 +Line 8268: 0 +Line 8269: 0 +Line 8270: 0 +Line 8271: 0 +Line 8272: 0 +Line 8273: 0 +Line 8274: 0 +Line 8275: 0 +Line 8276: 0 +Line 8277: 0 +Line 8278: 0 +Line 8279: 0 +Line 8280: 0 +Line 8281: 0 +Line 8282: 0 +Line 8283: 0 +Line 8284: 0 +Line 8285: 0 +Line 8286: 0 +Line 8287: 0 +Line 8288: 0 +Line 8289: 1 +Line 8290: 0 +Line 8291: 0 +Line 8292: 0 +Line 8293: 1 +Line 8294: 1 +Line 8295: 0 +Line 8296: 0 +Line 8297: 1 +Line 8298: 0 +Line 8299: 0 +Line 8300: 1 +Line 8301: 0 +Line 8302: 1 +Line 8303: 0 +Line 8304: 0 +Line 8305: 0 +Line 8306: 0 +Line 8307: 0 +Line 8308: 0 +Line 8309: 0 +Line 8310: 0 +Line 8311: 0 +Line 8312: 0 +Line 8313: 0 +Line 8314: 0 +Line 8315: 0 +Line 8316: 1 +Line 8317: 1 +Line 8318: 1 +Line 8319: 1 +Line 8320: 0 +Line 8321: 1 +Line 8322: 0 +Line 8323: 0 +Line 8324: 0 +Line 8325: 1 +Line 8326: 1 +Line 8327: 0 +Line 8328: 0 +Line 8329: 0 +Line 8330: 1 +Line 8331: 1 +Line 8332: 1 +Line 8333: 0 +Line 8334: 0 +Line 8335: 0 +Line 8336: 0 +Line 8337: 0 +Line 8338: 0 +Line 8339: 0 +Line 8340: 0 +Line 8341: 0 +Line 8342: 0 +Line 8343: 0 +Line 8344: 0 +Line 8345: 0 +Line 8346: 0 +Line 8347: 1 +Line 8348: 1 +Line 8349: 1 +Line 8350: 1 +Line 8351: 1 +Line 8352: 0 +Line 8353: 1 +Line 8354: 0 +Line 8355: 0 +Line 8356: 0 +Line 8357: 1 +Line 8358: 1 +Line 8359: 0 +Line 8360: 0 +Line 8361: 0 +Line 8362: 0 +Line 8363: 1 +Line 8364: 1 +Line 8365: 0 +Line 8366: 1 +Line 8367: 1 +Line 8368: 0 +Line 8369: 0 +Line 8370: 0 +Line 8371: 0 +Line 8372: 0 +Line 8373: 0 +Line 8374: 0 +Line 8375: 0 +Line 8376: 0 +Line 8377: 0 +Line 8378: 1 +Line 8379: 0 +Line 8380: 1 +Line 8381: 1 +Line 8382: 1 +Line 8383: 1 +Line 8384: 0 +Line 8385: 1 +Line 8386: 0 +Line 8387: 0 +Line 8388: 0 +Line 8389: 1 +Line 8390: 0 +Line 8391: 1 +Line 8392: 1 +Line 8393: 1 +Line 8394: 1 +Line 8395: 1 +Line 8396: 0 +Line 8397: 0 +Line 8398: 1 +Line 8399: 0 +Line 8400: 0 +Line 8401: 0 +Line 8402: 0 +Line 8403: 0 +Line 8404: 0 +Line 8405: 0 +Line 8406: 0 +Line 8407: 0 +Line 8408: 0 +Line 8409: 0 +Line 8410: 1 +Line 8411: 1 +Line 8412: 1 +Line 8413: 1 +Line 8414: 1 +Line 8415: 0 +Line 8416: 0 +Line 8417: 1 +Line 8418: 0 +Line 8419: 0 +Line 8420: 0 +Line 8421: 1 +Line 8422: 0 +Line 8423: 1 +Line 8424: 1 +Line 8425: 0 +Line 8426: 1 +Line 8427: 1 +Line 8428: 1 +Line 8429: 1 +Line 8430: 0 +Line 8431: 1 +Line 8432: 0 +Line 8433: 0 +Line 8434: 0 +Line 8435: 0 +Line 8436: 0 +Line 8437: 0 +Line 8438: 0 +Line 8439: 0 +Line 8440: 0 +Line 8441: 1 +Line 8442: 0 +Line 8443: 0 +Line 8444: 1 +Line 8445: 1 +Line 8446: 1 +Line 8447: 0 +Line 8448: 0 +Line 8449: 1 +Line 8450: 0 +Line 8451: 0 +Line 8452: 0 +Line 8453: 1 +Line 8454: 0 +Line 8455: 1 +Line 8456: 0 +Line 8457: 1 +Line 8458: 1 +Line 8459: 1 +Line 8460: 1 +Line 8461: 1 +Line 8462: 0 +Line 8463: 1 +Line 8464: 0 +Line 8465: 0 +Line 8466: 0 +Line 8467: 0 +Line 8468: 0 +Line 8469: 0 +Line 8470: 0 +Line 8471: 0 +Line 8472: 0 +Line 8473: 1 +Line 8474: 0 +Line 8475: 1 +Line 8476: 1 +Line 8477: 1 +Line 8478: 0 +Line 8479: 1 +Line 8480: 0 +Line 8481: 1 +Line 8482: 0 +Line 8483: 0 +Line 8484: 0 +Line 8485: 1 +Line 8486: 0 +Line 8487: 1 +Line 8488: 0 +Line 8489: 0 +Line 8490: 1 +Line 8491: 1 +Line 8492: 0 +Line 8493: 0 +Line 8494: 1 +Line 8495: 0 +Line 8496: 0 +Line 8497: 0 +Line 8498: 0 +Line 8499: 0 +Line 8500: 0 +Line 8501: 0 +Line 8502: 0 +Line 8503: 0 +Line 8504: 0 +Line 8505: 1 +Line 8506: 1 +Line 8507: 0 +Line 8508: 1 +Line 8509: 1 +Line 8510: 0 +Line 8511: 0 +Line 8512: 0 +Line 8513: 1 +Line 8514: 0 +Line 8515: 0 +Line 8516: 0 +Line 8517: 1 +Line 8518: 0 +Line 8519: 0 +Line 8520: 1 +Line 8521: 1 +Line 8522: 0 +Line 8523: 1 +Line 8524: 1 +Line 8525: 0 +Line 8526: 1 +Line 8527: 1 +Line 8528: 0 +Line 8529: 0 +Line 8530: 0 +Line 8531: 0 +Line 8532: 0 +Line 8533: 0 +Line 8534: 0 +Line 8535: 0 +Line 8536: 0 +Line 8537: 1 +Line 8538: 1 +Line 8539: 1 +Line 8540: 1 +Line 8541: 1 +Line 8542: 0 +Line 8543: 0 +Line 8544: 0 +Line 8545: 1 +Line 8546: 0 +Line 8547: 0 +Line 8548: 0 +Line 8549: 1 +Line 8550: 0 +Line 8551: 0 +Line 8552: 0 +Line 8553: 1 +Line 8554: 1 +Line 8555: 1 +Line 8556: 1 +Line 8557: 0 +Line 8558: 0 +Line 8559: 0 +Line 8560: 0 +Line 8561: 0 +Line 8562: 0 +Line 8563: 0 +Line 8564: 0 +Line 8565: 0 +Line 8566: 0 +Line 8567: 0 +Line 8568: 1 +Line 8569: 0 +Line 8570: 0 +Line 8571: 0 +Line 8572: 1 +Line 8573: 0 +Line 8574: 1 +Line 8575: 1 +Line 8576: 0 +Line 8577: 1 +Line 8578: 0 +Line 8579: 0 +Line 8580: 0 +Line 8581: 1 +Line 8582: 0 +Line 8583: 0 +Line 8584: 0 +Line 8585: 0 +Line 8586: 0 +Line 8587: 0 +Line 8588: 1 +Line 8589: 0 +Line 8590: 1 +Line 8591: 1 +Line 8592: 0 +Line 8593: 0 +Line 8594: 0 +Line 8595: 0 +Line 8596: 0 +Line 8597: 0 +Line 8598: 0 +Line 8599: 0 +Line 8600: 1 +Line 8601: 0 +Line 8602: 0 +Line 8603: 1 +Line 8604: 1 +Line 8605: 0 +Line 8606: 0 +Line 8607: 1 +Line 8608: 0 +Line 8609: 1 +Line 8610: 0 +Line 8611: 0 +Line 8612: 0 +Line 8613: 0 +Line 8614: 1 +Line 8615: 1 +Line 8616: 1 +Line 8617: 0 +Line 8618: 0 +Line 8619: 1 +Line 8620: 0 +Line 8621: 0 +Line 8622: 1 +Line 8623: 1 +Line 8624: 0 +Line 8625: 0 +Line 8626: 0 +Line 8627: 0 +Line 8628: 0 +Line 8629: 0 +Line 8630: 0 +Line 8631: 0 +Line 8632: 1 +Line 8633: 0 +Line 8634: 1 +Line 8635: 0 +Line 8636: 1 +Line 8637: 0 +Line 8638: 0 +Line 8639: 0 +Line 8640: 0 +Line 8641: 1 +Line 8642: 0 +Line 8643: 0 +Line 8644: 0 +Line 8645: 0 +Line 8646: 1 +Line 8647: 1 +Line 8648: 0 +Line 8649: 0 +Line 8650: 0 +Line 8651: 1 +Line 8652: 0 +Line 8653: 0 +Line 8654: 0 +Line 8655: 0 +Line 8656: 0 +Line 8657: 0 +Line 8658: 0 +Line 8659: 0 +Line 8660: 0 +Line 8661: 0 +Line 8662: 0 +Line 8663: 0 +Line 8664: 1 +Line 8665: 0 +Line 8666: 1 +Line 8667: 1 +Line 8668: 0 +Line 8669: 1 +Line 8670: 1 +Line 8671: 0 +Line 8672: 0 +Line 8673: 1 +Line 8674: 0 +Line 8675: 0 +Line 8676: 0 +Line 8677: 0 +Line 8678: 1 +Line 8679: 0 +Line 8680: 1 +Line 8681: 0 +Line 8682: 0 +Line 8683: 0 +Line 8684: 0 +Line 8685: 0 +Line 8686: 1 +Line 8687: 0 +Line 8688: 0 +Line 8689: 0 +Line 8690: 0 +Line 8691: 0 +Line 8692: 0 +Line 8693: 0 +Line 8694: 0 +Line 8695: 0 +Line 8696: 1 +Line 8697: 1 +Line 8698: 0 +Line 8699: 0 +Line 8700: 0 +Line 8701: 1 +Line 8702: 0 +Line 8703: 1 +Line 8704: 0 +Line 8705: 1 +Line 8706: 0 +Line 8707: 0 +Line 8708: 0 +Line 8709: 0 +Line 8710: 0 +Line 8711: 1 +Line 8712: 1 +Line 8713: 1 +Line 8714: 1 +Line 8715: 0 +Line 8716: 1 +Line 8717: 0 +Line 8718: 1 +Line 8719: 0 +Line 8720: 0 +Line 8721: 0 +Line 8722: 0 +Line 8723: 0 +Line 8724: 0 +Line 8725: 0 +Line 8726: 0 +Line 8727: 0 +Line 8728: 1 +Line 8729: 1 +Line 8730: 0 +Line 8731: 1 +Line 8732: 0 +Line 8733: 0 +Line 8734: 1 +Line 8735: 0 +Line 8736: 0 +Line 8737: 1 +Line 8738: 0 +Line 8739: 0 +Line 8740: 0 +Line 8741: 0 +Line 8742: 0 +Line 8743: 1 +Line 8744: 0 +Line 8745: 1 +Line 8746: 0 +Line 8747: 0 +Line 8748: 0 +Line 8749: 1 +Line 8750: 1 +Line 8751: 1 +Line 8752: 0 +Line 8753: 0 +Line 8754: 0 +Line 8755: 0 +Line 8756: 0 +Line 8757: 0 +Line 8758: 0 +Line 8759: 0 +Line 8760: 1 +Line 8761: 1 +Line 8762: 1 +Line 8763: 0 +Line 8764: 0 +Line 8765: 0 +Line 8766: 0 +Line 8767: 0 +Line 8768: 0 +Line 8769: 1 +Line 8770: 0 +Line 8771: 0 +Line 8772: 0 +Line 8773: 0 +Line 8774: 0 +Line 8775: 0 +Line 8776: 1 +Line 8777: 0 +Line 8778: 0 +Line 8779: 1 +Line 8780: 1 +Line 8781: 0 +Line 8782: 1 +Line 8783: 1 +Line 8784: 0 +Line 8785: 0 +Line 8786: 0 +Line 8787: 0 +Line 8788: 0 +Line 8789: 0 +Line 8790: 0 +Line 8791: 0 +Line 8792: 1 +Line 8793: 1 +Line 8794: 1 +Line 8795: 0 +Line 8796: 1 +Line 8797: 1 +Line 8798: 0 +Line 8799: 1 +Line 8800: 0 +Line 8801: 0 +Line 8802: 1 +Line 8803: 1 +Line 8804: 1 +Line 8805: 1 +Line 8806: 1 +Line 8807: 1 +Line 8808: 1 +Line 8809: 1 +Line 8810: 1 +Line 8811: 0 +Line 8812: 0 +Line 8813: 1 +Line 8814: 0 +Line 8815: 0 +Line 8816: 0 +Line 8817: 0 +Line 8818: 0 +Line 8819: 0 +Line 8820: 0 +Line 8821: 0 +Line 8822: 0 +Line 8823: 0 +Line 8824: 1 +Line 8825: 1 +Line 8826: 1 +Line 8827: 1 +Line 8828: 1 +Line 8829: 0 +Line 8830: 1 +Line 8831: 0 +Line 8832: 0 +Line 8833: 0 +Line 8834: 1 +Line 8835: 1 +Line 8836: 1 +Line 8837: 1 +Line 8838: 1 +Line 8839: 1 +Line 8840: 0 +Line 8841: 0 +Line 8842: 1 +Line 8843: 0 +Line 8844: 0 +Line 8845: 1 +Line 8846: 0 +Line 8847: 0 +Line 8848: 0 +Line 8849: 0 +Line 8850: 0 +Line 8851: 0 +Line 8852: 0 +Line 8853: 0 +Line 8854: 0 +Line 8855: 1 +Line 8856: 0 +Line 8857: 0 +Line 8858: 0 +Line 8859: 0 +Line 8860: 0 +Line 8861: 1 +Line 8862: 1 +Line 8863: 1 +Line 8864: 0 +Line 8865: 0 +Line 8866: 1 +Line 8867: 1 +Line 8868: 1 +Line 8869: 1 +Line 8870: 1 +Line 8871: 0 +Line 8872: 0 +Line 8873: 1 +Line 8874: 0 +Line 8875: 1 +Line 8876: 1 +Line 8877: 0 +Line 8878: 1 +Line 8879: 1 +Line 8880: 0 +Line 8881: 0 +Line 8882: 0 +Line 8883: 0 +Line 8884: 0 +Line 8885: 0 +Line 8886: 0 +Line 8887: 1 +Line 8888: 0 +Line 8889: 0 +Line 8890: 0 +Line 8891: 1 +Line 8892: 0 +Line 8893: 0 +Line 8894: 1 +Line 8895: 1 +Line 8896: 0 +Line 8897: 0 +Line 8898: 1 +Line 8899: 1 +Line 8900: 1 +Line 8901: 1 +Line 8902: 0 +Line 8903: 1 +Line 8904: 1 +Line 8905: 0 +Line 8906: 0 +Line 8907: 0 +Line 8908: 1 +Line 8909: 0 +Line 8910: 0 +Line 8911: 1 +Line 8912: 0 +Line 8913: 0 +Line 8914: 0 +Line 8915: 0 +Line 8916: 0 +Line 8917: 0 +Line 8918: 0 +Line 8919: 1 +Line 8920: 0 +Line 8921: 0 +Line 8922: 0 +Line 8923: 1 +Line 8924: 1 +Line 8925: 1 +Line 8926: 1 +Line 8927: 1 +Line 8928: 0 +Line 8929: 0 +Line 8930: 1 +Line 8931: 1 +Line 8932: 1 +Line 8933: 1 +Line 8934: 0 +Line 8935: 0 +Line 8936: 1 +Line 8937: 0 +Line 8938: 1 +Line 8939: 0 +Line 8940: 1 +Line 8941: 1 +Line 8942: 0 +Line 8943: 1 +Line 8944: 0 +Line 8945: 0 +Line 8946: 0 +Line 8947: 0 +Line 8948: 0 +Line 8949: 0 +Line 8950: 0 +Line 8951: 1 +Line 8952: 0 +Line 8953: 0 +Line 8954: 1 +Line 8955: 0 +Line 8956: 1 +Line 8957: 0 +Line 8958: 1 +Line 8959: 1 +Line 8960: 0 +Line 8961: 0 +Line 8962: 1 +Line 8963: 1 +Line 8964: 1 +Line 8965: 0 +Line 8966: 1 +Line 8967: 1 +Line 8968: 1 +Line 8969: 1 +Line 8970: 0 +Line 8971: 0 +Line 8972: 1 +Line 8973: 0 +Line 8974: 1 +Line 8975: 0 +Line 8976: 0 +Line 8977: 0 +Line 8978: 0 +Line 8979: 0 +Line 8980: 0 +Line 8981: 0 +Line 8982: 0 +Line 8983: 1 +Line 8984: 0 +Line 8985: 0 +Line 8986: 1 +Line 8987: 1 +Line 8988: 0 +Line 8989: 1 +Line 8990: 1 +Line 8991: 0 +Line 8992: 0 +Line 8993: 0 +Line 8994: 1 +Line 8995: 1 +Line 8996: 1 +Line 8997: 0 +Line 8998: 1 +Line 8999: 0 +Line 9000: 1 +Line 9001: 1 +Line 9002: 0 +Line 9003: 1 +Line 9004: 1 +Line 9005: 1 +Line 9006: 1 +Line 9007: 0 +Line 9008: 0 +Line 9009: 0 +Line 9010: 0 +Line 9011: 0 +Line 9012: 0 +Line 9013: 0 +Line 9014: 0 +Line 9015: 1 +Line 9016: 0 +Line 9017: 1 +Line 9018: 0 +Line 9019: 0 +Line 9020: 0 +Line 9021: 0 +Line 9022: 0 +Line 9023: 1 +Line 9024: 0 +Line 9025: 0 +Line 9026: 1 +Line 9027: 1 +Line 9028: 1 +Line 9029: 0 +Line 9030: 0 +Line 9031: 1 +Line 9032: 1 +Line 9033: 1 +Line 9034: 1 +Line 9035: 0 +Line 9036: 1 +Line 9037: 0 +Line 9038: 1 +Line 9039: 0 +Line 9040: 0 +Line 9041: 0 +Line 9042: 0 +Line 9043: 0 +Line 9044: 0 +Line 9045: 0 +Line 9046: 0 +Line 9047: 1 +Line 9048: 0 +Line 9049: 1 +Line 9050: 0 +Line 9051: 0 +Line 9052: 1 +Line 9053: 0 +Line 9054: 1 +Line 9055: 1 +Line 9056: 0 +Line 9057: 0 +Line 9058: 1 +Line 9059: 1 +Line 9060: 1 +Line 9061: 0 +Line 9062: 0 +Line 9063: 0 +Line 9064: 1 +Line 9065: 1 +Line 9066: 1 +Line 9067: 0 +Line 9068: 1 +Line 9069: 1 +Line 9070: 1 +Line 9071: 1 +Line 9072: 0 +Line 9073: 0 +Line 9074: 0 +Line 9075: 0 +Line 9076: 0 +Line 9077: 0 +Line 9078: 0 +Line 9079: 1 +Line 9080: 0 +Line 9081: 1 +Line 9082: 0 +Line 9083: 1 +Line 9084: 0 +Line 9085: 1 +Line 9086: 0 +Line 9087: 1 +Line 9088: 0 +Line 9089: 0 +Line 9090: 1 +Line 9091: 1 +Line 9092: 0 +Line 9093: 1 +Line 9094: 1 +Line 9095: 1 +Line 9096: 1 +Line 9097: 1 +Line 9098: 1 +Line 9099: 0 +Line 9100: 1 +Line 9101: 1 +Line 9102: 0 +Line 9103: 0 +Line 9104: 0 +Line 9105: 0 +Line 9106: 0 +Line 9107: 0 +Line 9108: 0 +Line 9109: 0 +Line 9110: 0 +Line 9111: 1 +Line 9112: 0 +Line 9113: 1 +Line 9114: 0 +Line 9115: 1 +Line 9116: 1 +Line 9117: 1 +Line 9118: 1 +Line 9119: 1 +Line 9120: 0 +Line 9121: 0 +Line 9122: 1 +Line 9123: 1 +Line 9124: 0 +Line 9125: 1 +Line 9126: 1 +Line 9127: 0 +Line 9128: 1 +Line 9129: 1 +Line 9130: 1 +Line 9131: 0 +Line 9132: 0 +Line 9133: 0 +Line 9134: 1 +Line 9135: 0 +Line 9136: 0 +Line 9137: 0 +Line 9138: 0 +Line 9139: 0 +Line 9140: 0 +Line 9141: 0 +Line 9142: 0 +Line 9143: 1 +Line 9144: 0 +Line 9145: 1 +Line 9146: 1 +Line 9147: 0 +Line 9148: 1 +Line 9149: 0 +Line 9150: 0 +Line 9151: 0 +Line 9152: 0 +Line 9153: 0 +Line 9154: 1 +Line 9155: 1 +Line 9156: 0 +Line 9157: 1 +Line 9158: 0 +Line 9159: 1 +Line 9160: 1 +Line 9161: 1 +Line 9162: 0 +Line 9163: 1 +Line 9164: 0 +Line 9165: 0 +Line 9166: 1 +Line 9167: 0 +Line 9168: 0 +Line 9169: 0 +Line 9170: 0 +Line 9171: 0 +Line 9172: 0 +Line 9173: 0 +Line 9174: 0 +Line 9175: 1 +Line 9176: 0 +Line 9177: 1 +Line 9178: 1 +Line 9179: 1 +Line 9180: 0 +Line 9181: 0 +Line 9182: 0 +Line 9183: 1 +Line 9184: 0 +Line 9185: 0 +Line 9186: 1 +Line 9187: 1 +Line 9188: 0 +Line 9189: 1 +Line 9190: 0 +Line 9191: 0 +Line 9192: 1 +Line 9193: 0 +Line 9194: 1 +Line 9195: 1 +Line 9196: 1 +Line 9197: 0 +Line 9198: 1 +Line 9199: 1 +Line 9200: 0 +Line 9201: 0 +Line 9202: 0 +Line 9203: 0 +Line 9204: 0 +Line 9205: 0 +Line 9206: 0 +Line 9207: 1 +Line 9208: 0 +Line 9209: 1 +Line 9210: 1 +Line 9211: 1 +Line 9212: 1 +Line 9213: 0 +Line 9214: 0 +Line 9215: 1 +Line 9216: 0 +Line 9217: 0 +Line 9218: 1 +Line 9219: 1 +Line 9220: 0 +Line 9221: 0 +Line 9222: 1 +Line 9223: 1 +Line 9224: 1 +Line 9225: 0 +Line 9226: 0 +Line 9227: 1 +Line 9228: 1 +Line 9229: 1 +Line 9230: 1 +Line 9231: 1 +Line 9232: 0 +Line 9233: 0 +Line 9234: 0 +Line 9235: 0 +Line 9236: 0 +Line 9237: 0 +Line 9238: 0 +Line 9239: 1 +Line 9240: 1 +Line 9241: 0 +Line 9242: 0 +Line 9243: 0 +Line 9244: 0 +Line 9245: 0 +Line 9246: 0 +Line 9247: 0 +Line 9248: 0 +Line 9249: 0 +Line 9250: 1 +Line 9251: 1 +Line 9252: 0 +Line 9253: 0 +Line 9254: 1 +Line 9255: 0 +Line 9256: 0 +Line 9257: 1 +Line 9258: 1 +Line 9259: 1 +Line 9260: 1 +Line 9261: 1 +Line 9262: 0 +Line 9263: 1 +Line 9264: 0 +Line 9265: 0 +Line 9266: 0 +Line 9267: 0 +Line 9268: 0 +Line 9269: 0 +Line 9270: 0 +Line 9271: 1 +Line 9272: 1 +Line 9273: 0 +Line 9274: 0 +Line 9275: 0 +Line 9276: 0 +Line 9277: 1 +Line 9278: 1 +Line 9279: 1 +Line 9280: 0 +Line 9281: 0 +Line 9282: 1 +Line 9283: 1 +Line 9284: 0 +Line 9285: 0 +Line 9286: 0 +Line 9287: 1 +Line 9288: 0 +Line 9289: 1 +Line 9290: 0 +Line 9291: 1 +Line 9292: 0 +Line 9293: 1 +Line 9294: 1 +Line 9295: 0 +Line 9296: 0 +Line 9297: 0 +Line 9298: 0 +Line 9299: 0 +Line 9300: 0 +Line 9301: 0 +Line 9302: 0 +Line 9303: 1 +Line 9304: 1 +Line 9305: 0 +Line 9306: 0 +Line 9307: 0 +Line 9308: 1 +Line 9309: 1 +Line 9310: 1 +Line 9311: 0 +Line 9312: 0 +Line 9313: 0 +Line 9314: 1 +Line 9315: 1 +Line 9316: 0 +Line 9317: 0 +Line 9318: 0 +Line 9319: 0 +Line 9320: 0 +Line 9321: 0 +Line 9322: 1 +Line 9323: 0 +Line 9324: 1 +Line 9325: 0 +Line 9326: 1 +Line 9327: 1 +Line 9328: 0 +Line 9329: 0 +Line 9330: 0 +Line 9331: 0 +Line 9332: 0 +Line 9333: 0 +Line 9334: 0 +Line 9335: 1 +Line 9336: 1 +Line 9337: 0 +Line 9338: 0 +Line 9339: 1 +Line 9340: 0 +Line 9341: 1 +Line 9342: 0 +Line 9343: 0 +Line 9344: 0 +Line 9345: 0 +Line 9346: 1 +Line 9347: 0 +Line 9348: 1 +Line 9349: 1 +Line 9350: 1 +Line 9351: 0 +Line 9352: 1 +Line 9353: 1 +Line 9354: 1 +Line 9355: 1 +Line 9356: 1 +Line 9357: 0 +Line 9358: 1 +Line 9359: 1 +Line 9360: 0 +Line 9361: 0 +Line 9362: 0 +Line 9363: 0 +Line 9364: 0 +Line 9365: 0 +Line 9366: 0 +Line 9367: 1 +Line 9368: 1 +Line 9369: 0 +Line 9370: 0 +Line 9371: 1 +Line 9372: 1 +Line 9373: 0 +Line 9374: 1 +Line 9375: 0 +Line 9376: 0 +Line 9377: 0 +Line 9378: 1 +Line 9379: 0 +Line 9380: 1 +Line 9381: 1 +Line 9382: 0 +Line 9383: 1 +Line 9384: 1 +Line 9385: 1 +Line 9386: 0 +Line 9387: 0 +Line 9388: 0 +Line 9389: 1 +Line 9390: 1 +Line 9391: 1 +Line 9392: 0 +Line 9393: 0 +Line 9394: 0 +Line 9395: 0 +Line 9396: 0 +Line 9397: 0 +Line 9398: 0 +Line 9399: 1 +Line 9400: 1 +Line 9401: 0 +Line 9402: 0 +Line 9403: 1 +Line 9404: 1 +Line 9405: 1 +Line 9406: 1 +Line 9407: 1 +Line 9408: 0 +Line 9409: 0 +Line 9410: 1 +Line 9411: 0 +Line 9412: 1 +Line 9413: 1 +Line 9414: 0 +Line 9415: 0 +Line 9416: 1 +Line 9417: 0 +Line 9418: 0 +Line 9419: 0 +Line 9420: 1 +Line 9421: 1 +Line 9422: 1 +Line 9423: 1 +Line 9424: 0 +Line 9425: 0 +Line 9426: 0 +Line 9427: 0 +Line 9428: 0 +Line 9429: 0 +Line 9430: 0 +Line 9431: 1 +Line 9432: 1 +Line 9433: 0 +Line 9434: 1 +Line 9435: 0 +Line 9436: 0 +Line 9437: 0 +Line 9438: 1 +Line 9439: 1 +Line 9440: 0 +Line 9441: 0 +Line 9442: 1 +Line 9443: 0 +Line 9444: 1 +Line 9445: 0 +Line 9446: 1 +Line 9447: 1 +Line 9448: 0 +Line 9449: 1 +Line 9450: 0 +Line 9451: 1 +Line 9452: 0 +Line 9453: 1 +Line 9454: 0 +Line 9455: 1 +Line 9456: 0 +Line 9457: 0 +Line 9458: 0 +Line 9459: 0 +Line 9460: 0 +Line 9461: 0 +Line 9462: 0 +Line 9463: 1 +Line 9464: 1 +Line 9465: 0 +Line 9466: 1 +Line 9467: 0 +Line 9468: 0 +Line 9469: 1 +Line 9470: 1 +Line 9471: 1 +Line 9472: 0 +Line 9473: 0 +Line 9474: 1 +Line 9475: 0 +Line 9476: 1 +Line 9477: 0 +Line 9478: 1 +Line 9479: 0 +Line 9480: 0 +Line 9481: 0 +Line 9482: 0 +Line 9483: 1 +Line 9484: 0 +Line 9485: 1 +Line 9486: 1 +Line 9487: 1 +Line 9488: 0 +Line 9489: 0 +Line 9490: 0 +Line 9491: 0 +Line 9492: 0 +Line 9493: 0 +Line 9494: 0 +Line 9495: 1 +Line 9496: 1 +Line 9497: 0 +Line 9498: 1 +Line 9499: 0 +Line 9500: 1 +Line 9501: 0 +Line 9502: 1 +Line 9503: 0 +Line 9504: 0 +Line 9505: 0 +Line 9506: 1 +Line 9507: 0 +Line 9508: 1 +Line 9509: 0 +Line 9510: 0 +Line 9511: 0 +Line 9512: 1 +Line 9513: 1 +Line 9514: 0 +Line 9515: 1 +Line 9516: 1 +Line 9517: 0 +Line 9518: 0 +Line 9519: 0 +Line 9520: 0 +Line 9521: 0 +Line 9522: 0 +Line 9523: 0 +Line 9524: 0 +Line 9525: 0 +Line 9526: 0 +Line 9527: 1 +Line 9528: 1 +Line 9529: 0 +Line 9530: 1 +Line 9531: 0 +Line 9532: 1 +Line 9533: 1 +Line 9534: 0 +Line 9535: 1 +Line 9536: 0 +Line 9537: 0 +Line 9538: 1 +Line 9539: 0 +Line 9540: 0 +Line 9541: 1 +Line 9542: 1 +Line 9543: 1 +Line 9544: 1 +Line 9545: 0 +Line 9546: 0 +Line 9547: 1 +Line 9548: 0 +Line 9549: 1 +Line 9550: 1 +Line 9551: 0 +Line 9552: 0 +Line 9553: 0 +Line 9554: 0 +Line 9555: 0 +Line 9556: 0 +Line 9557: 0 +Line 9558: 0 +Line 9559: 1 +Line 9560: 1 +Line 9561: 0 +Line 9562: 1 +Line 9563: 1 +Line 9564: 0 +Line 9565: 0 +Line 9566: 0 +Line 9567: 0 +Line 9568: 0 +Line 9569: 0 +Line 9570: 1 +Line 9571: 0 +Line 9572: 0 +Line 9573: 1 +Line 9574: 1 +Line 9575: 0 +Line 9576: 0 +Line 9577: 1 +Line 9578: 0 +Line 9579: 1 +Line 9580: 0 +Line 9581: 0 +Line 9582: 1 +Line 9583: 1 +Line 9584: 0 +Line 9585: 0 +Line 9586: 0 +Line 9587: 0 +Line 9588: 0 +Line 9589: 0 +Line 9590: 0 +Line 9591: 1 +Line 9592: 1 +Line 9593: 0 +Line 9594: 1 +Line 9595: 1 +Line 9596: 0 +Line 9597: 0 +Line 9598: 0 +Line 9599: 1 +Line 9600: 0 +Line 9601: 0 +Line 9602: 1 +Line 9603: 0 +Line 9604: 0 +Line 9605: 1 +Line 9606: 0 +Line 9607: 1 +Line 9608: 0 +Line 9609: 0 +Line 9610: 0 +Line 9611: 0 +Line 9612: 1 +Line 9613: 1 +Line 9614: 1 +Line 9615: 1 +Line 9616: 0 +Line 9617: 0 +Line 9618: 0 +Line 9619: 0 +Line 9620: 0 +Line 9621: 0 +Line 9622: 0 +Line 9623: 1 +Line 9624: 1 +Line 9625: 0 +Line 9626: 1 +Line 9627: 1 +Line 9628: 0 +Line 9629: 0 +Line 9630: 1 +Line 9631: 0 +Line 9632: 0 +Line 9633: 0 +Line 9634: 1 +Line 9635: 0 +Line 9636: 0 +Line 9637: 0 +Line 9638: 1 +Line 9639: 1 +Line 9640: 1 +Line 9641: 1 +Line 9642: 0 +Line 9643: 0 +Line 9644: 1 +Line 9645: 0 +Line 9646: 1 +Line 9647: 0 +Line 9648: 0 +Line 9649: 0 +Line 9650: 0 +Line 9651: 0 +Line 9652: 0 +Line 9653: 0 +Line 9654: 0 +Line 9655: 1 +Line 9656: 1 +Line 9657: 0 +Line 9658: 1 +Line 9659: 1 +Line 9660: 0 +Line 9661: 0 +Line 9662: 1 +Line 9663: 1 +Line 9664: 0 +Line 9665: 0 +Line 9666: 1 +Line 9667: 0 +Line 9668: 0 +Line 9669: 0 +Line 9670: 1 +Line 9671: 0 +Line 9672: 1 +Line 9673: 0 +Line 9674: 0 +Line 9675: 0 +Line 9676: 0 +Line 9677: 1 +Line 9678: 0 +Line 9679: 1 +Line 9680: 0 +Line 9681: 0 +Line 9682: 0 +Line 9683: 0 +Line 9684: 0 +Line 9685: 0 +Line 9686: 0 +Line 9687: 1 +Line 9688: 1 +Line 9689: 0 +Line 9690: 1 +Line 9691: 1 +Line 9692: 0 +Line 9693: 0 +Line 9694: 1 +Line 9695: 1 +Line 9696: 0 +Line 9697: 0 +Line 9698: 1 +Line 9699: 0 +Line 9700: 0 +Line 9701: 0 +Line 9702: 0 +Line 9703: 1 +Line 9704: 0 +Line 9705: 1 +Line 9706: 0 +Line 9707: 0 +Line 9708: 0 +Line 9709: 0 +Line 9710: 0 +Line 9711: 0 +Line 9712: 0 +Line 9713: 0 +Line 9714: 0 +Line 9715: 0 +Line 9716: 0 +Line 9717: 0 +Line 9718: 0 +Line 9719: 1 +Line 9720: 1 +Line 9721: 0 +Line 9722: 1 +Line 9723: 1 +Line 9724: 0 +Line 9725: 0 +Line 9726: 1 +Line 9727: 0 +Line 9728: 0 +Line 9729: 0 +Line 9730: 0 +Line 9731: 1 +Line 9732: 1 +Line 9733: 1 +Line 9734: 1 +Line 9735: 1 +Line 9736: 1 +Line 9737: 1 +Line 9738: 1 +Line 9739: 1 +Line 9740: 1 +Line 9741: 1 +Line 9742: 0 +Line 9743: 0 +Line 9744: 0 +Line 9745: 0 +Line 9746: 0 +Line 9747: 0 +Line 9748: 0 +Line 9749: 0 +Line 9750: 0 +Line 9751: 1 +Line 9752: 1 +Line 9753: 0 +Line 9754: 1 +Line 9755: 1 +Line 9756: 0 +Line 9757: 0 +Line 9758: 0 +Line 9759: 1 +Line 9760: 0 +Line 9761: 0 +Line 9762: 0 +Line 9763: 1 +Line 9764: 1 +Line 9765: 1 +Line 9766: 1 +Line 9767: 0 +Line 9768: 1 +Line 9769: 0 +Line 9770: 1 +Line 9771: 1 +Line 9772: 1 +Line 9773: 0 +Line 9774: 0 +Line 9775: 1 +Line 9776: 0 +Line 9777: 0 +Line 9778: 0 +Line 9779: 0 +Line 9780: 0 +Line 9781: 0 +Line 9782: 0 +Line 9783: 1 +Line 9784: 1 +Line 9785: 0 +Line 9786: 1 +Line 9787: 1 +Line 9788: 0 +Line 9789: 0 +Line 9790: 0 +Line 9791: 0 +Line 9792: 0 +Line 9793: 0 +Line 9794: 0 +Line 9795: 1 +Line 9796: 1 +Line 9797: 1 +Line 9798: 0 +Line 9799: 1 +Line 9800: 0 +Line 9801: 1 +Line 9802: 1 +Line 9803: 1 +Line 9804: 0 +Line 9805: 1 +Line 9806: 1 +Line 9807: 1 +Line 9808: 0 +Line 9809: 0 +Line 9810: 0 +Line 9811: 0 +Line 9812: 0 +Line 9813: 0 +Line 9814: 0 +Line 9815: 1 +Line 9816: 1 +Line 9817: 0 +Line 9818: 1 +Line 9819: 0 +Line 9820: 1 +Line 9821: 1 +Line 9822: 0 +Line 9823: 1 +Line 9824: 0 +Line 9825: 0 +Line 9826: 0 +Line 9827: 1 +Line 9828: 1 +Line 9829: 1 +Line 9830: 0 +Line 9831: 0 +Line 9832: 0 +Line 9833: 0 +Line 9834: 1 +Line 9835: 1 +Line 9836: 1 +Line 9837: 0 +Line 9838: 0 +Line 9839: 0 +Line 9840: 0 +Line 9841: 0 +Line 9842: 0 +Line 9843: 0 +Line 9844: 0 +Line 9845: 0 +Line 9846: 0 +Line 9847: 1 +Line 9848: 1 +Line 9849: 0 +Line 9850: 1 +Line 9851: 0 +Line 9852: 1 +Line 9853: 0 +Line 9854: 1 +Line 9855: 0 +Line 9856: 0 +Line 9857: 0 +Line 9858: 0 +Line 9859: 1 +Line 9860: 1 +Line 9861: 0 +Line 9862: 1 +Line 9863: 0 +Line 9864: 1 +Line 9865: 1 +Line 9866: 1 +Line 9867: 1 +Line 9868: 1 +Line 9869: 0 +Line 9870: 1 +Line 9871: 0 +Line 9872: 0 +Line 9873: 0 +Line 9874: 0 +Line 9875: 0 +Line 9876: 0 +Line 9877: 0 +Line 9878: 0 +Line 9879: 1 +Line 9880: 1 +Line 9881: 0 +Line 9882: 1 +Line 9883: 0 +Line 9884: 0 +Line 9885: 1 +Line 9886: 1 +Line 9887: 1 +Line 9888: 0 +Line 9889: 0 +Line 9890: 0 +Line 9891: 1 +Line 9892: 1 +Line 9893: 0 +Line 9894: 0 +Line 9895: 1 +Line 9896: 1 +Line 9897: 1 +Line 9898: 0 +Line 9899: 0 +Line 9900: 0 +Line 9901: 0 +Line 9902: 0 +Line 9903: 0 +Line 9904: 0 +Line 9905: 0 +Line 9906: 0 +Line 9907: 0 +Line 9908: 0 +Line 9909: 0 +Line 9910: 0 +Line 9911: 1 +Line 9912: 1 +Line 9913: 0 +Line 9914: 1 +Line 9915: 0 +Line 9916: 0 +Line 9917: 0 +Line 9918: 1 +Line 9919: 1 +Line 9920: 0 +Line 9921: 0 +Line 9922: 0 +Line 9923: 1 +Line 9924: 1 +Line 9925: 0 +Line 9926: 0 +Line 9927: 0 +Line 9928: 1 +Line 9929: 0 +Line 9930: 0 +Line 9931: 0 +Line 9932: 1 +Line 9933: 0 +Line 9934: 0 +Line 9935: 0 +Line 9936: 0 +Line 9937: 0 +Line 9938: 0 +Line 9939: 0 +Line 9940: 0 +Line 9941: 0 +Line 9942: 0 +Line 9943: 1 +Line 9944: 1 +Line 9945: 0 +Line 9946: 0 +Line 9947: 1 +Line 9948: 1 +Line 9949: 1 +Line 9950: 1 +Line 9951: 1 +Line 9952: 0 +Line 9953: 0 +Line 9954: 0 +Line 9955: 1 +Line 9956: 0 +Line 9957: 1 +Line 9958: 1 +Line 9959: 1 +Line 9960: 0 +Line 9961: 1 +Line 9962: 0 +Line 9963: 1 +Line 9964: 0 +Line 9965: 1 +Line 9966: 0 +Line 9967: 0 +Line 9968: 0 +Line 9969: 0 +Line 9970: 0 +Line 9971: 0 +Line 9972: 0 +Line 9973: 0 +Line 9974: 0 +Line 9975: 1 +Line 9976: 1 +Line 9977: 0 +Line 9978: 0 +Line 9979: 1 +Line 9980: 1 +Line 9981: 0 +Line 9982: 1 +Line 9983: 0 +Line 9984: 0 +Line 9985: 0 +Line 9986: 0 +Line 9987: 1 +Line 9988: 0 +Line 9989: 1 +Line 9990: 1 +Line 9991: 0 +Line 9992: 0 +Line 9993: 0 +Line 9994: 1 +Line 9995: 0 +Line 9996: 0 +Line 9997: 1 +Line 9998: 0 +Line 9999: 0 +Line 10000: 0 +Line 10001: 0 +Line 10002: 0 +Line 10003: 0 +Line 10004: 0 +Line 10005: 0 +Line 10006: 0 +Line 10007: 1 +Line 10008: 1 +Line 10009: 0 +Line 10010: 0 +Line 10011: 1 +Line 10012: 0 +Line 10013: 1 +Line 10014: 0 +Line 10015: 0 +Line 10016: 0 +Line 10017: 0 +Line 10018: 0 +Line 10019: 1 +Line 10020: 0 +Line 10021: 1 +Line 10022: 0 +Line 10023: 0 +Line 10024: 1 +Line 10025: 1 +Line 10026: 1 +Line 10027: 1 +Line 10028: 1 +Line 10029: 0 +Line 10030: 0 +Line 10031: 1 +Line 10032: 0 +Line 10033: 0 +Line 10034: 0 +Line 10035: 0 +Line 10036: 0 +Line 10037: 0 +Line 10038: 0 +Line 10039: 1 +Line 10040: 1 +Line 10041: 0 +Line 10042: 0 +Line 10043: 0 +Line 10044: 1 +Line 10045: 1 +Line 10046: 1 +Line 10047: 0 +Line 10048: 0 +Line 10049: 0 +Line 10050: 0 +Line 10051: 1 +Line 10052: 0 +Line 10053: 0 +Line 10054: 1 +Line 10055: 1 +Line 10056: 1 +Line 10057: 1 +Line 10058: 0 +Line 10059: 1 +Line 10060: 0 +Line 10061: 0 +Line 10062: 1 +Line 10063: 0 +Line 10064: 0 +Line 10065: 0 +Line 10066: 0 +Line 10067: 0 +Line 10068: 0 +Line 10069: 0 +Line 10070: 0 +Line 10071: 1 +Line 10072: 1 +Line 10073: 0 +Line 10074: 0 +Line 10075: 0 +Line 10076: 0 +Line 10077: 1 +Line 10078: 1 +Line 10079: 1 +Line 10080: 0 +Line 10081: 0 +Line 10082: 0 +Line 10083: 1 +Line 10084: 0 +Line 10085: 0 +Line 10086: 1 +Line 10087: 0 +Line 10088: 1 +Line 10089: 0 +Line 10090: 1 +Line 10091: 1 +Line 10092: 0 +Line 10093: 0 +Line 10094: 0 +Line 10095: 0 +Line 10096: 0 +Line 10097: 0 +Line 10098: 0 +Line 10099: 0 +Line 10100: 0 +Line 10101: 0 +Line 10102: 0 +Line 10103: 1 +Line 10104: 1 +Line 10105: 0 +Line 10106: 0 +Line 10107: 0 +Line 10108: 0 +Line 10109: 0 +Line 10110: 0 +Line 10111: 0 +Line 10112: 0 +Line 10113: 0 +Line 10114: 0 +Line 10115: 1 +Line 10116: 0 +Line 10117: 0 +Line 10118: 0 +Line 10119: 1 +Line 10120: 1 +Line 10121: 0 +Line 10122: 0 +Line 10123: 1 +Line 10124: 0 +Line 10125: 0 +Line 10126: 1 +Line 10127: 1 +Line 10128: 0 +Line 10129: 0 +Line 10130: 0 +Line 10131: 0 +Line 10132: 0 +Line 10133: 0 +Line 10134: 0 +Line 10135: 1 +Line 10136: 0 +Line 10137: 1 +Line 10138: 1 +Line 10139: 1 +Line 10140: 1 +Line 10141: 0 +Line 10142: 0 +Line 10143: 1 +Line 10144: 0 +Line 10145: 0 +Line 10146: 0 +Line 10147: 1 +Line 10148: 0 +Line 10149: 0 +Line 10150: 0 +Line 10151: 0 +Line 10152: 0 +Line 10153: 1 +Line 10154: 1 +Line 10155: 1 +Line 10156: 1 +Line 10157: 1 +Line 10158: 0 +Line 10159: 1 +Line 10160: 0 +Line 10161: 0 +Line 10162: 0 +Line 10163: 0 +Line 10164: 0 +Line 10165: 0 +Line 10166: 0 +Line 10167: 1 +Line 10168: 0 +Line 10169: 1 +Line 10170: 1 +Line 10171: 1 +Line 10172: 0 +Line 10173: 0 +Line 10174: 0 +Line 10175: 1 +Line 10176: 0 +Line 10177: 0 +Line 10178: 0 +Line 10179: 0 +Line 10180: 1 +Line 10181: 1 +Line 10182: 1 +Line 10183: 1 +Line 10184: 0 +Line 10185: 1 +Line 10186: 1 +Line 10187: 0 +Line 10188: 1 +Line 10189: 1 +Line 10190: 0 +Line 10191: 1 +Line 10192: 0 +Line 10193: 0 +Line 10194: 0 +Line 10195: 0 +Line 10196: 0 +Line 10197: 0 +Line 10198: 0 +Line 10199: 1 +Line 10200: 0 +Line 10201: 1 +Line 10202: 1 +Line 10203: 0 +Line 10204: 1 +Line 10205: 0 +Line 10206: 0 +Line 10207: 0 +Line 10208: 0 +Line 10209: 0 +Line 10210: 0 +Line 10211: 0 +Line 10212: 1 +Line 10213: 1 +Line 10214: 1 +Line 10215: 0 +Line 10216: 0 +Line 10217: 1 +Line 10218: 1 +Line 10219: 0 +Line 10220: 0 +Line 10221: 0 +Line 10222: 1 +Line 10223: 1 +Line 10224: 0 +Line 10225: 0 +Line 10226: 0 +Line 10227: 0 +Line 10228: 0 +Line 10229: 0 +Line 10230: 0 +Line 10231: 1 +Line 10232: 0 +Line 10233: 1 +Line 10234: 0 +Line 10235: 1 +Line 10236: 1 +Line 10237: 1 +Line 10238: 1 +Line 10239: 1 +Line 10240: 0 +Line 10241: 0 +Line 10242: 0 +Line 10243: 0 +Line 10244: 1 +Line 10245: 1 +Line 10246: 0 +Line 10247: 1 +Line 10248: 0 +Line 10249: 1 +Line 10250: 1 +Line 10251: 0 +Line 10252: 0 +Line 10253: 0 +Line 10254: 0 +Line 10255: 0 +Line 10256: 0 +Line 10257: 0 +Line 10258: 0 +Line 10259: 0 +Line 10260: 0 +Line 10261: 0 +Line 10262: 0 +Line 10263: 1 +Line 10264: 0 +Line 10265: 1 +Line 10266: 0 +Line 10267: 1 +Line 10268: 0 +Line 10269: 1 +Line 10270: 0 +Line 10271: 1 +Line 10272: 0 +Line 10273: 0 +Line 10274: 0 +Line 10275: 0 +Line 10276: 1 +Line 10277: 1 +Line 10278: 0 +Line 10279: 0 +Line 10280: 0 +Line 10281: 1 +Line 10282: 1 +Line 10283: 0 +Line 10284: 0 +Line 10285: 1 +Line 10286: 0 +Line 10287: 1 +Line 10288: 0 +Line 10289: 0 +Line 10290: 0 +Line 10291: 0 +Line 10292: 0 +Line 10293: 0 +Line 10294: 0 +Line 10295: 1 +Line 10296: 0 +Line 10297: 1 +Line 10298: 0 +Line 10299: 0 +Line 10300: 1 +Line 10301: 0 +Line 10302: 1 +Line 10303: 1 +Line 10304: 0 +Line 10305: 0 +Line 10306: 0 +Line 10307: 0 +Line 10308: 1 +Line 10309: 0 +Line 10310: 1 +Line 10311: 1 +Line 10312: 0 +Line 10313: 1 +Line 10314: 1 +Line 10315: 1 +Line 10316: 0 +Line 10317: 0 +Line 10318: 0 +Line 10319: 1 +Line 10320: 0 +Line 10321: 0 +Line 10322: 0 +Line 10323: 0 +Line 10324: 0 +Line 10325: 0 +Line 10326: 0 +Line 10327: 1 +Line 10328: 0 +Line 10329: 1 +Line 10330: 0 +Line 10331: 0 +Line 10332: 0 +Line 10333: 0 +Line 10334: 0 +Line 10335: 1 +Line 10336: 0 +Line 10337: 0 +Line 10338: 0 +Line 10339: 0 +Line 10340: 1 +Line 10341: 0 +Line 10342: 1 +Line 10343: 0 +Line 10344: 1 +Line 10345: 0 +Line 10346: 0 +Line 10347: 0 +Line 10348: 0 +Line 10349: 1 +Line 10350: 0 +Line 10351: 1 +Line 10352: 0 +Line 10353: 0 +Line 10354: 0 +Line 10355: 0 +Line 10356: 0 +Line 10357: 0 +Line 10358: 0 +Line 10359: 1 +Line 10360: 0 +Line 10361: 0 +Line 10362: 1 +Line 10363: 1 +Line 10364: 0 +Line 10365: 1 +Line 10366: 1 +Line 10367: 0 +Line 10368: 0 +Line 10369: 0 +Line 10370: 0 +Line 10371: 0 +Line 10372: 1 +Line 10373: 0 +Line 10374: 0 +Line 10375: 1 +Line 10376: 1 +Line 10377: 0 +Line 10378: 1 +Line 10379: 0 +Line 10380: 0 +Line 10381: 0 +Line 10382: 1 +Line 10383: 0 +Line 10384: 0 +Line 10385: 0 +Line 10386: 0 +Line 10387: 0 +Line 10388: 0 +Line 10389: 0 +Line 10390: 0 +Line 10391: 1 +Line 10392: 0 +Line 10393: 0 +Line 10394: 1 +Line 10395: 0 +Line 10396: 1 +Line 10397: 0 +Line 10398: 1 +Line 10399: 1 +Line 10400: 0 +Line 10401: 0 +Line 10402: 0 +Line 10403: 0 +Line 10404: 1 +Line 10405: 0 +Line 10406: 0 +Line 10407: 0 +Line 10408: 1 +Line 10409: 1 +Line 10410: 0 +Line 10411: 0 +Line 10412: 0 +Line 10413: 1 +Line 10414: 1 +Line 10415: 0 +Line 10416: 0 +Line 10417: 0 +Line 10418: 0 +Line 10419: 0 +Line 10420: 0 +Line 10421: 0 +Line 10422: 0 +Line 10423: 1 +Line 10424: 0 +Line 10425: 0 +Line 10426: 0 +Line 10427: 1 +Line 10428: 1 +Line 10429: 1 +Line 10430: 1 +Line 10431: 1 +Line 10432: 0 +Line 10433: 0 +Line 10434: 0 +Line 10435: 0 +Line 10436: 0 +Line 10437: 1 +Line 10438: 1 +Line 10439: 1 +Line 10440: 1 +Line 10441: 1 +Line 10442: 1 +Line 10443: 1 +Line 10444: 0 +Line 10445: 1 +Line 10446: 0 +Line 10447: 0 +Line 10448: 0 +Line 10449: 0 +Line 10450: 0 +Line 10451: 0 +Line 10452: 0 +Line 10453: 0 +Line 10454: 0 +Line 10455: 1 +Line 10456: 0 +Line 10457: 0 +Line 10458: 0 +Line 10459: 1 +Line 10460: 0 +Line 10461: 0 +Line 10462: 1 +Line 10463: 1 +Line 10464: 0 +Line 10465: 0 +Line 10466: 0 +Line 10467: 0 +Line 10468: 0 +Line 10469: 1 +Line 10470: 1 +Line 10471: 1 +Line 10472: 0 +Line 10473: 0 +Line 10474: 1 +Line 10475: 0 +Line 10476: 1 +Line 10477: 0 +Line 10478: 1 +Line 10479: 1 +Line 10480: 0 +Line 10481: 0 +Line 10482: 0 +Line 10483: 0 +Line 10484: 0 +Line 10485: 0 +Line 10486: 0 +Line 10487: 1 +Line 10488: 0 +Line 10489: 0 +Line 10490: 0 +Line 10491: 0 +Line 10492: 0 +Line 10493: 1 +Line 10494: 1 +Line 10495: 1 +Line 10496: 0 +Line 10497: 0 +Line 10498: 0 +Line 10499: 0 +Line 10500: 0 +Line 10501: 1 +Line 10502: 1 +Line 10503: 0 +Line 10504: 0 +Line 10505: 1 +Line 10506: 1 +Line 10507: 0 +Line 10508: 1 +Line 10509: 0 +Line 10510: 1 +Line 10511: 1 +Line 10512: 0 +Line 10513: 0 +Line 10514: 0 +Line 10515: 0 +Line 10516: 0 +Line 10517: 0 +Line 10518: 0 +Line 10519: 0 +Line 10520: 1 +Line 10521: 1 +Line 10522: 1 +Line 10523: 1 +Line 10524: 1 +Line 10525: 0 +Line 10526: 1 +Line 10527: 0 +Line 10528: 0 +Line 10529: 0 +Line 10530: 0 +Line 10531: 0 +Line 10532: 0 +Line 10533: 1 +Line 10534: 0 +Line 10535: 1 +Line 10536: 1 +Line 10537: 0 +Line 10538: 1 +Line 10539: 1 +Line 10540: 0 +Line 10541: 1 +Line 10542: 0 +Line 10543: 0 +Line 10544: 0 +Line 10545: 0 +Line 10546: 0 +Line 10547: 0 +Line 10548: 0 +Line 10549: 0 +Line 10550: 0 +Line 10551: 0 +Line 10552: 1 +Line 10553: 1 +Line 10554: 1 +Line 10555: 0 +Line 10556: 1 +Line 10557: 1 +Line 10558: 0 +Line 10559: 1 +Line 10560: 0 +Line 10561: 0 +Line 10562: 0 +Line 10563: 0 +Line 10564: 0 +Line 10565: 1 +Line 10566: 0 +Line 10567: 1 +Line 10568: 0 +Line 10569: 0 +Line 10570: 0 +Line 10571: 0 +Line 10572: 1 +Line 10573: 0 +Line 10574: 0 +Line 10575: 0 +Line 10576: 0 +Line 10577: 0 +Line 10578: 0 +Line 10579: 0 +Line 10580: 0 +Line 10581: 0 +Line 10582: 0 +Line 10583: 0 +Line 10584: 1 +Line 10585: 1 +Line 10586: 1 +Line 10587: 0 +Line 10588: 0 +Line 10589: 0 +Line 10590: 0 +Line 10591: 0 +Line 10592: 0 +Line 10593: 0 +Line 10594: 0 +Line 10595: 0 +Line 10596: 0 +Line 10597: 1 +Line 10598: 0 +Line 10599: 0 +Line 10600: 0 +Line 10601: 1 +Line 10602: 1 +Line 10603: 0 +Line 10604: 0 +Line 10605: 1 +Line 10606: 0 +Line 10607: 1 +Line 10608: 0 +Line 10609: 0 +Line 10610: 0 +Line 10611: 0 +Line 10612: 0 +Line 10613: 0 +Line 10614: 0 +Line 10615: 0 +Line 10616: 1 +Line 10617: 1 +Line 10618: 0 +Line 10619: 1 +Line 10620: 0 +Line 10621: 0 +Line 10622: 1 +Line 10623: 0 +Line 10624: 0 +Line 10625: 0 +Line 10626: 0 +Line 10627: 0 +Line 10628: 0 +Line 10629: 0 +Line 10630: 1 +Line 10631: 1 +Line 10632: 1 +Line 10633: 1 +Line 10634: 0 +Line 10635: 0 +Line 10636: 1 +Line 10637: 1 +Line 10638: 0 +Line 10639: 1 +Line 10640: 0 +Line 10641: 0 +Line 10642: 0 +Line 10643: 0 +Line 10644: 0 +Line 10645: 0 +Line 10646: 0 +Line 10647: 0 +Line 10648: 1 +Line 10649: 1 +Line 10650: 0 +Line 10651: 0 +Line 10652: 0 +Line 10653: 1 +Line 10654: 0 +Line 10655: 1 +Line 10656: 0 +Line 10657: 0 +Line 10658: 0 +Line 10659: 0 +Line 10660: 0 +Line 10661: 0 +Line 10662: 1 +Line 10663: 1 +Line 10664: 0 +Line 10665: 0 +Line 10666: 1 +Line 10667: 1 +Line 10668: 1 +Line 10669: 1 +Line 10670: 1 +Line 10671: 1 +Line 10672: 0 +Line 10673: 0 +Line 10674: 0 +Line 10675: 0 +Line 10676: 0 +Line 10677: 0 +Line 10678: 0 +Line 10679: 0 +Line 10680: 1 +Line 10681: 0 +Line 10682: 1 +Line 10683: 1 +Line 10684: 0 +Line 10685: 1 +Line 10686: 1 +Line 10687: 0 +Line 10688: 0 +Line 10689: 0 +Line 10690: 0 +Line 10691: 0 +Line 10692: 0 +Line 10693: 0 +Line 10694: 1 +Line 10695: 0 +Line 10696: 1 +Line 10697: 0 +Line 10698: 1 +Line 10699: 1 +Line 10700: 1 +Line 10701: 1 +Line 10702: 0 +Line 10703: 0 +Line 10704: 0 +Line 10705: 0 +Line 10706: 0 +Line 10707: 0 +Line 10708: 0 +Line 10709: 0 +Line 10710: 0 +Line 10711: 0 +Line 10712: 1 +Line 10713: 0 +Line 10714: 1 +Line 10715: 0 +Line 10716: 1 +Line 10717: 0 +Line 10718: 0 +Line 10719: 0 +Line 10720: 0 +Line 10721: 0 +Line 10722: 0 +Line 10723: 0 +Line 10724: 0 +Line 10725: 0 +Line 10726: 1 +Line 10727: 0 +Line 10728: 0 +Line 10729: 1 +Line 10730: 0 +Line 10731: 0 +Line 10732: 0 +Line 10733: 1 +Line 10734: 0 +Line 10735: 0 +Line 10736: 0 +Line 10737: 0 +Line 10738: 0 +Line 10739: 0 +Line 10740: 0 +Line 10741: 0 +Line 10742: 0 +Line 10743: 0 +Line 10744: 1 +Line 10745: 0 +Line 10746: 0 +Line 10747: 1 +Line 10748: 1 +Line 10749: 0 +Line 10750: 0 +Line 10751: 1 +Line 10752: 0 +Line 10753: 0 +Line 10754: 0 +Line 10755: 0 +Line 10756: 0 +Line 10757: 0 +Line 10758: 0 +Line 10759: 1 +Line 10760: 1 +Line 10761: 1 +Line 10762: 0 +Line 10763: 1 +Line 10764: 0 +Line 10765: 1 +Line 10766: 1 +Line 10767: 1 +Line 10768: 0 +Line 10769: 0 +Line 10770: 0 +Line 10771: 0 +Line 10772: 0 +Line 10773: 0 +Line 10774: 0 +Line 10775: 0 +Line 10776: 1 +Line 10777: 0 +Line 10778: 0 +Line 10779: 0 +Line 10780: 1 +Line 10781: 0 +Line 10782: 1 +Line 10783: 1 +Line 10784: 0 +Line 10785: 0 +Line 10786: 0 +Line 10787: 0 +Line 10788: 0 +Line 10789: 0 +Line 10790: 0 +Line 10791: 1 +Line 10792: 0 +Line 10793: 1 +Line 10794: 1 +Line 10795: 1 +Line 10796: 0 +Line 10797: 1 +Line 10798: 0 +Line 10799: 0 +Line 10800: 0 +Line 10801: 0 +Line 10802: 0 +Line 10803: 0 +Line 10804: 0 +Line 10805: 0 +Line 10806: 0 +Line 10807: 0 +Line 10808: 0 +Line 10809: 1 +Line 10810: 1 +Line 10811: 1 +Line 10812: 1 +Line 10813: 1 +Line 10814: 0 +Line 10815: 0 +Line 10816: 0 +Line 10817: 0 +Line 10818: 0 +Line 10819: 0 +Line 10820: 0 +Line 10821: 0 +Line 10822: 0 +Line 10823: 1 +Line 10824: 0 +Line 10825: 0 +Line 10826: 0 +Line 10827: 1 +Line 10828: 1 +Line 10829: 1 +Line 10830: 0 +Line 10831: 1 +Line 10832: 0 +Line 10833: 0 +Line 10834: 0 +Line 10835: 0 +Line 10836: 0 +Line 10837: 0 +Line 10838: 0 +Line 10839: 0 +Line 10840: 0 +Line 10841: 1 +Line 10842: 1 +Line 10843: 0 +Line 10844: 1 +Line 10845: 1 +Line 10846: 0 +Line 10847: 0 +Line 10848: 0 +Line 10849: 0 +Line 10850: 0 +Line 10851: 0 +Line 10852: 0 +Line 10853: 0 +Line 10854: 0 +Line 10855: 0 +Line 10856: 1 +Line 10857: 1 +Line 10858: 0 +Line 10859: 1 +Line 10860: 0 +Line 10861: 0 +Line 10862: 1 +Line 10863: 0 +Line 10864: 0 +Line 10865: 0 +Line 10866: 0 +Line 10867: 0 +Line 10868: 0 +Line 10869: 0 +Line 10870: 0 +Line 10871: 0 +Line 10872: 0 +Line 10873: 1 +Line 10874: 0 +Line 10875: 1 +Line 10876: 1 +Line 10877: 1 +Line 10878: 0 +Line 10879: 1 +Line 10880: 0 +Line 10881: 0 +Line 10882: 0 +Line 10883: 0 +Line 10884: 0 +Line 10885: 0 +Line 10886: 0 +Line 10887: 0 +Line 10888: 1 +Line 10889: 0 +Line 10890: 0 +Line 10891: 1 +Line 10892: 0 +Line 10893: 0 +Line 10894: 1 +Line 10895: 0 +Line 10896: 0 +Line 10897: 0 +Line 10898: 0 +Line 10899: 0 +Line 10900: 0 +Line 10901: 0 +Line 10902: 0 +Line 10903: 0 +Line 10904: 0 +Line 10905: 1 +Line 10906: 0 +Line 10907: 0 +Line 10908: 1 +Line 10909: 1 +Line 10910: 1 +Line 10911: 0 +Line 10912: 0 +Line 10913: 0 +Line 10914: 0 +Line 10915: 0 +Line 10916: 0 +Line 10917: 0 +Line 10918: 0 +Line 10919: 0 +Line 10920: 0 +Line 10921: 1 +Line 10922: 0 +Line 10923: 1 +Line 10924: 1 +Line 10925: 1 +Line 10926: 0 +Line 10927: 1 +Line 10928: 0 +Line 10929: 0 +Line 10930: 0 +Line 10931: 0 +Line 10932: 0 +Line 10933: 0 +Line 10934: 0 +Line 10935: 0 +Line 10936: 0 +Line 10937: 0 +Line 10938: 1 +Line 10939: 1 +Line 10940: 1 +Line 10941: 1 +Line 10942: 1 +Line 10943: 0 +Line 10944: 0 +Line 10945: 0 +Line 10946: 0 +Line 10947: 0 +Line 10948: 0 +Line 10949: 0 +Line 10950: 0 +Line 10951: 0 +Line 10952: 0 +Line 10953: 0 +Line 10954: 1 +Line 10955: 1 +Line 10956: 0 +Line 10957: 1 +Line 10958: 0 +Line 10959: 0 +Line 10960: 0 +Line 10961: 0 +Line 10962: 0 +Line 10963: 0 +Line 10964: 0 +Line 10965: 0 +Line 10966: 0 +Line 10967: 0 +Line 10968: 0 +Line 10969: 0 +Line 10970: 1 +Line 10971: 0 +Line 10972: 1 +Line 10973: 1 +Line 10974: 1 +Line 10975: 1 +Line 10976: 0 +Line 10977: 0 +Line 10978: 0 +Line 10979: 0 +Line 10980: 0 +Line 10981: 0 +Line 10982: 0 +Line 10983: 0 +Line 10984: 0 +Line 10985: 0 +Line 10986: 0 +Line 10987: 1 +Line 10988: 0 +Line 10989: 1 +Line 10990: 1 +Line 10991: 1 +Line 10992: 0 +Line 10993: 0 +Line 10994: 0 +Line 10995: 0 +Line 10996: 0 +Line 10997: 0 +Line 10998: 0 +Line 10999: 0 +Line 11000: 0 +Line 11001: 0 +Line 11002: 0 +Line 11003: 1 +Line 11004: 1 +Line 11005: 1 +Line 11006: 1 +Line 11007: 1 +Line 11008: 0 +Line 11009: 0 +Line 11010: 0 +Line 11011: 0 +Line 11012: 0 +Line 11013: 0 +Line 11014: 0 +Line 11015: 0 +Line 11016: 0 +Line 11017: 0 +Line 11018: 0 +Line 11019: 0 +Line 11020: 0 +Line 11021: 1 +Line 11022: 0 +Line 11023: 1 +Line 11024: 0 +Line 11025: 0 +Line 11026: 0 +Line 11027: 0 +Line 11028: 0 +Line 11029: 0 +Line 11030: 0 +Line 11031: 0 +Line 11032: 0 +Line 11033: 0 +Line 11034: 0 +Line 11035: 0 +Line 11036: 1 +Line 11037: 1 +Line 11038: 1 +Line 11039: 1 +Line 11040: 0 +Line 11041: 0 +Line 11042: 0 +Line 11043: 0 +Line 11044: 0 +Line 11045: 0 +Line 11046: 0 +Line 11047: 0 +Line 11048: 0 +Line 11049: 0 +Line 11050: 0 +Line 11051: 0 +Line 11052: 0 +Line 11053: 0 +Line 11054: 0 +Line 11055: 0 +Line 11056: 0 +Line 11057: 0 +Line 11058: 0 +Line 11059: 0 +Line 11060: 0 +Line 11061: 0 +Line 11062: 0 +Line 11063: 0 +Line 11064: 0 +Line 11065: 0 +Line 11066: 0 +Line 11067: 0 +Line 11068: 0 +Line 11069: 0 +Line 11070: 0 +Line 11071: 0 +Line 11072: 0 +Line 11073: 1 +Line 11074: 0 +Line 11075: 0 +Line 11076: 0 +Line 11077: 1 +Line 11078: 1 +Line 11079: 0 +Line 11080: 0 +Line 11081: 1 +Line 11082: 0 +Line 11083: 1 +Line 11084: 0 +Line 11085: 0 +Line 11086: 0 +Line 11087: 0 +Line 11088: 0 +Line 11089: 0 +Line 11090: 0 +Line 11091: 0 +Line 11092: 0 +Line 11093: 0 +Line 11094: 0 +Line 11095: 0 +Line 11096: 0 +Line 11097: 0 +Line 11098: 0 +Line 11099: 0 +Line 11100: 0 +Line 11101: 0 +Line 11102: 0 +Line 11103: 0 +Line 11104: 0 +Line 11105: 0 +Line 11106: 0 +Line 11107: 0 +Line 11108: 0 +Line 11109: 0 +Line 11110: 0 +Line 11111: 0 +Line 11112: 0 +Line 11113: 0 +Line 11114: 0 +Line 11115: 0 +Line 11116: 0 +Line 11117: 0 +Line 11118: 0 +Line 11119: 0 +Line 11120: 0 +Line 11121: 0 +Line 11122: 0 +Line 11123: 0 +Line 11124: 0 +Line 11125: 0 +Line 11126: 0 +Line 11127: 0 +Line 11128: 0 +Line 11129: 0 +Line 11130: 0 +Line 11131: 0 +Line 11132: 0 +Line 11133: 0 +Line 11134: 0 +Line 11135: 0 +Line 11136: 0 +Line 11137: 0 +Line 11138: 0 +Line 11139: 0 +Line 11140: 0 +Line 11141: 0 +Line 11142: 0 +Line 11143: 0 +Line 11144: 0 +Line 11145: 0 +Line 11146: 0 +Line 11147: 0 +Line 11148: 0 +Line 11149: 0 +Line 11150: 0 +Line 11151: 0 +Line 11152: 0 +Line 11153: 0 +Line 11154: 0 +Line 11155: 0 +Line 11156: 0 +Line 11157: 0 +Line 11158: 0 +Line 11159: 0 +Line 11160: 0 +Line 11161: 0 +Line 11162: 0 +Line 11163: 0 +Line 11164: 0 +Line 11165: 0 +Line 11166: 0 +Line 11167: 0 +Line 11168: 0 +Line 11169: 0 +Line 11170: 0 +Line 11171: 0 +Line 11172: 1 +Line 11173: 0 +Line 11174: 0 +Line 11175: 0 +Line 11176: 0 +Line 11177: 0 +Line 11178: 0 +Line 11179: 0 +Line 11180: 1 +Line 11181: 0 +Line 11182: 1 +Line 11183: 0 +Line 11184: 0 +Line 11185: 0 +Line 11186: 0 +Line 11187: 0 +Line 11188: 0 +Line 11189: 0 +Line 11190: 0 +Line 11191: 0 +Line 11192: 0 +Line 11193: 0 +Line 11194: 0 +Line 11195: 0 +Line 11196: 0 +Line 11197: 0 +Line 11198: 0 +Line 11199: 0 +Line 11200: 0 +Line 11201: 0 +Line 11202: 0 +Line 11203: 0 +Line 11204: 1 +Line 11205: 1 +Line 11206: 1 +Line 11207: 1 +Line 11208: 1 +Line 11209: 1 +Line 11210: 1 +Line 11211: 0 +Line 11212: 0 +Line 11213: 1 +Line 11214: 1 +Line 11215: 1 +Line 11216: 0 +Line 11217: 0 +Line 11218: 0 +Line 11219: 0 +Line 11220: 0 +Line 11221: 0 +Line 11222: 0 +Line 11223: 0 +Line 11224: 0 +Line 11225: 0 +Line 11226: 0 +Line 11227: 0 +Line 11228: 0 +Line 11229: 0 +Line 11230: 0 +Line 11231: 0 +Line 11232: 0 +Line 11233: 0 +Line 11234: 0 +Line 11235: 1 +Line 11236: 0 +Line 11237: 1 +Line 11238: 1 +Line 11239: 1 +Line 11240: 0 +Line 11241: 1 +Line 11242: 1 +Line 11243: 0 +Line 11244: 1 +Line 11245: 1 +Line 11246: 0 +Line 11247: 0 +Line 11248: 0 +Line 11249: 0 +Line 11250: 0 +Line 11251: 0 +Line 11252: 0 +Line 11253: 0 +Line 11254: 0 +Line 11255: 0 +Line 11256: 0 +Line 11257: 0 +Line 11258: 0 +Line 11259: 0 +Line 11260: 0 +Line 11261: 0 +Line 11262: 0 +Line 11263: 0 +Line 11264: 0 +Line 11265: 0 +Line 11266: 0 +Line 11267: 1 +Line 11268: 1 +Line 11269: 1 +Line 11270: 1 +Line 11271: 0 +Line 11272: 0 +Line 11273: 1 +Line 11274: 1 +Line 11275: 1 +Line 11276: 0 +Line 11277: 0 +Line 11278: 0 +Line 11279: 1 +Line 11280: 0 +Line 11281: 0 +Line 11282: 0 +Line 11283: 0 +Line 11284: 0 +Line 11285: 0 +Line 11286: 0 +Line 11287: 0 +Line 11288: 0 +Line 11289: 0 +Line 11290: 0 +Line 11291: 0 +Line 11292: 0 +Line 11293: 0 +Line 11294: 0 +Line 11295: 0 +Line 11296: 0 +Line 11297: 0 +Line 11298: 1 +Line 11299: 0 +Line 11300: 0 +Line 11301: 1 +Line 11302: 0 +Line 11303: 0 +Line 11304: 1 +Line 11305: 1 +Line 11306: 0 +Line 11307: 1 +Line 11308: 0 +Line 11309: 1 +Line 11310: 0 +Line 11311: 1 +Line 11312: 0 +Line 11313: 0 +Line 11314: 0 +Line 11315: 0 +Line 11316: 0 +Line 11317: 0 +Line 11318: 0 +Line 11319: 0 +Line 11320: 0 +Line 11321: 0 +Line 11322: 0 +Line 11323: 0 +Line 11324: 0 +Line 11325: 0 +Line 11326: 0 +Line 11327: 0 +Line 11328: 0 +Line 11329: 0 +Line 11330: 1 +Line 11331: 0 +Line 11332: 1 +Line 11333: 0 +Line 11334: 1 +Line 11335: 0 +Line 11336: 0 +Line 11337: 1 +Line 11338: 1 +Line 11339: 1 +Line 11340: 1 +Line 11341: 1 +Line 11342: 1 +Line 11343: 0 +Line 11344: 0 +Line 11345: 0 +Line 11346: 0 +Line 11347: 0 +Line 11348: 0 +Line 11349: 0 +Line 11350: 0 +Line 11351: 0 +Line 11352: 0 +Line 11353: 0 +Line 11354: 0 +Line 11355: 0 +Line 11356: 0 +Line 11357: 0 +Line 11358: 0 +Line 11359: 0 +Line 11360: 0 +Line 11361: 0 +Line 11362: 1 +Line 11363: 0 +Line 11364: 1 +Line 11365: 1 +Line 11366: 1 +Line 11367: 1 +Line 11368: 0 +Line 11369: 1 +Line 11370: 0 +Line 11371: 1 +Line 11372: 1 +Line 11373: 0 +Line 11374: 0 +Line 11375: 1 +Line 11376: 0 +Line 11377: 0 +Line 11378: 0 +Line 11379: 0 +Line 11380: 0 +Line 11381: 0 +Line 11382: 0 +Line 11383: 0 +Line 11384: 0 +Line 11385: 0 +Line 11386: 0 +Line 11387: 0 +Line 11388: 0 +Line 11389: 0 +Line 11390: 0 +Line 11391: 0 +Line 11392: 0 +Line 11393: 0 +Line 11394: 1 +Line 11395: 1 +Line 11396: 0 +Line 11397: 0 +Line 11398: 1 +Line 11399: 1 +Line 11400: 0 +Line 11401: 1 +Line 11402: 0 +Line 11403: 1 +Line 11404: 1 +Line 11405: 1 +Line 11406: 1 +Line 11407: 1 +Line 11408: 0 +Line 11409: 0 +Line 11410: 0 +Line 11411: 0 +Line 11412: 0 +Line 11413: 0 +Line 11414: 0 +Line 11415: 0 +Line 11416: 0 +Line 11417: 0 +Line 11418: 0 +Line 11419: 0 +Line 11420: 0 +Line 11421: 0 +Line 11422: 0 +Line 11423: 0 +Line 11424: 0 +Line 11425: 0 +Line 11426: 1 +Line 11427: 1 +Line 11428: 0 +Line 11429: 1 +Line 11430: 1 +Line 11431: 0 +Line 11432: 1 +Line 11433: 0 +Line 11434: 0 +Line 11435: 1 +Line 11436: 0 +Line 11437: 0 +Line 11438: 0 +Line 11439: 0 +Line 11440: 0 +Line 11441: 0 +Line 11442: 0 +Line 11443: 0 +Line 11444: 0 +Line 11445: 0 +Line 11446: 0 +Line 11447: 0 +Line 11448: 0 +Line 11449: 0 +Line 11450: 0 +Line 11451: 0 +Line 11452: 0 +Line 11453: 0 +Line 11454: 0 +Line 11455: 0 +Line 11456: 0 +Line 11457: 0 +Line 11458: 1 +Line 11459: 1 +Line 11460: 1 +Line 11461: 0 +Line 11462: 0 +Line 11463: 0 +Line 11464: 1 +Line 11465: 1 +Line 11466: 1 +Line 11467: 1 +Line 11468: 0 +Line 11469: 0 +Line 11470: 1 +Line 11471: 0 +Line 11472: 0 +Line 11473: 0 +Line 11474: 0 +Line 11475: 0 +Line 11476: 0 +Line 11477: 0 +Line 11478: 0 +Line 11479: 0 +Line 11480: 0 +Line 11481: 0 +Line 11482: 0 +Line 11483: 0 +Line 11484: 0 +Line 11485: 0 +Line 11486: 0 +Line 11487: 0 +Line 11488: 0 +Line 11489: 0 +Line 11490: 1 +Line 11491: 1 +Line 11492: 1 +Line 11493: 0 +Line 11494: 1 +Line 11495: 0 +Line 11496: 1 +Line 11497: 0 +Line 11498: 0 +Line 11499: 1 +Line 11500: 1 +Line 11501: 0 +Line 11502: 0 +Line 11503: 1 +Line 11504: 0 +Line 11505: 0 +Line 11506: 0 +Line 11507: 0 +Line 11508: 0 +Line 11509: 0 +Line 11510: 0 +Line 11511: 0 +Line 11512: 0 +Line 11513: 0 +Line 11514: 0 +Line 11515: 0 +Line 11516: 0 +Line 11517: 0 +Line 11518: 0 +Line 11519: 0 +Line 11520: 0 +Line 11521: 0 +Line 11522: 1 +Line 11523: 1 +Line 11524: 1 +Line 11525: 0 +Line 11526: 1 +Line 11527: 1 +Line 11528: 1 +Line 11529: 0 +Line 11530: 0 +Line 11531: 1 +Line 11532: 1 +Line 11533: 0 +Line 11534: 1 +Line 11535: 0 +Line 11536: 0 +Line 11537: 0 +Line 11538: 0 +Line 11539: 0 +Line 11540: 0 +Line 11541: 0 +Line 11542: 0 +Line 11543: 0 +Line 11544: 0 +Line 11545: 0 +Line 11546: 0 +Line 11547: 0 +Line 11548: 0 +Line 11549: 0 +Line 11550: 0 +Line 11551: 0 +Line 11552: 0 +Line 11553: 0 +Line 11554: 1 +Line 11555: 1 +Line 11556: 1 +Line 11557: 1 +Line 11558: 0 +Line 11559: 0 +Line 11560: 0 +Line 11561: 0 +Line 11562: 0 +Line 11563: 1 +Line 11564: 0 +Line 11565: 0 +Line 11566: 0 +Line 11567: 1 +Line 11568: 0 +Line 11569: 0 +Line 11570: 0 +Line 11571: 0 +Line 11572: 0 +Line 11573: 0 +Line 11574: 0 +Line 11575: 0 +Line 11576: 0 +Line 11577: 0 +Line 11578: 0 +Line 11579: 0 +Line 11580: 0 +Line 11581: 0 +Line 11582: 0 +Line 11583: 0 +Line 11584: 0 +Line 11585: 0 +Line 11586: 1 +Line 11587: 1 +Line 11588: 1 +Line 11589: 1 +Line 11590: 0 +Line 11591: 0 +Line 11592: 0 +Line 11593: 0 +Line 11594: 0 +Line 11595: 1 +Line 11596: 1 +Line 11597: 1 +Line 11598: 1 +Line 11599: 1 +Line 11600: 0 +Line 11601: 0 +Line 11602: 0 +Line 11603: 0 +Line 11604: 0 +Line 11605: 0 +Line 11606: 0 +Line 11607: 0 +Line 11608: 0 +Line 11609: 0 +Line 11610: 0 +Line 11611: 0 +Line 11612: 0 +Line 11613: 0 +Line 11614: 0 +Line 11615: 0 +Line 11616: 0 +Line 11617: 0 +Line 11618: 1 +Line 11619: 1 +Line 11620: 1 +Line 11621: 0 +Line 11622: 1 +Line 11623: 1 +Line 11624: 1 +Line 11625: 1 +Line 11626: 1 +Line 11627: 0 +Line 11628: 0 +Line 11629: 1 +Line 11630: 0 +Line 11631: 0 +Line 11632: 0 +Line 11633: 0 +Line 11634: 0 +Line 11635: 0 +Line 11636: 0 +Line 11637: 0 +Line 11638: 0 +Line 11639: 0 +Line 11640: 0 +Line 11641: 0 +Line 11642: 0 +Line 11643: 0 +Line 11644: 0 +Line 11645: 0 +Line 11646: 0 +Line 11647: 0 +Line 11648: 0 +Line 11649: 0 +Line 11650: 1 +Line 11651: 1 +Line 11652: 1 +Line 11653: 0 +Line 11654: 1 +Line 11655: 1 +Line 11656: 1 +Line 11657: 0 +Line 11658: 0 +Line 11659: 0 +Line 11660: 0 +Line 11661: 0 +Line 11662: 0 +Line 11663: 0 +Line 11664: 0 +Line 11665: 0 +Line 11666: 0 +Line 11667: 0 +Line 11668: 0 +Line 11669: 0 +Line 11670: 0 +Line 11671: 0 +Line 11672: 0 +Line 11673: 0 +Line 11674: 0 +Line 11675: 0 +Line 11676: 0 +Line 11677: 0 +Line 11678: 0 +Line 11679: 0 +Line 11680: 0 +Line 11681: 0 +Line 11682: 1 +Line 11683: 1 +Line 11684: 1 +Line 11685: 0 +Line 11686: 1 +Line 11687: 1 +Line 11688: 0 +Line 11689: 0 +Line 11690: 0 +Line 11691: 1 +Line 11692: 0 +Line 11693: 0 +Line 11694: 0 +Line 11695: 0 +Line 11696: 0 +Line 11697: 0 +Line 11698: 0 +Line 11699: 0 +Line 11700: 0 +Line 11701: 0 +Line 11702: 0 +Line 11703: 0 +Line 11704: 0 +Line 11705: 0 +Line 11706: 0 +Line 11707: 0 +Line 11708: 0 +Line 11709: 0 +Line 11710: 0 +Line 11711: 0 +Line 11712: 0 +Line 11713: 0 +Line 11714: 1 +Line 11715: 1 +Line 11716: 1 +Line 11717: 0 +Line 11718: 1 +Line 11719: 0 +Line 11720: 1 +Line 11721: 0 +Line 11722: 1 +Line 11723: 0 +Line 11724: 1 +Line 11725: 1 +Line 11726: 0 +Line 11727: 1 +Line 11728: 0 +Line 11729: 0 +Line 11730: 0 +Line 11731: 0 +Line 11732: 0 +Line 11733: 0 +Line 11734: 0 +Line 11735: 0 +Line 11736: 0 +Line 11737: 0 +Line 11738: 0 +Line 11739: 0 +Line 11740: 0 +Line 11741: 0 +Line 11742: 0 +Line 11743: 0 +Line 11744: 0 +Line 11745: 0 +Line 11746: 1 +Line 11747: 1 +Line 11748: 1 +Line 11749: 0 +Line 11750: 1 +Line 11751: 0 +Line 11752: 0 +Line 11753: 1 +Line 11754: 1 +Line 11755: 0 +Line 11756: 1 +Line 11757: 0 +Line 11758: 0 +Line 11759: 1 +Line 11760: 0 +Line 11761: 0 +Line 11762: 0 +Line 11763: 0 +Line 11764: 0 +Line 11765: 0 +Line 11766: 0 +Line 11767: 0 +Line 11768: 0 +Line 11769: 0 +Line 11770: 0 +Line 11771: 0 +Line 11772: 0 +Line 11773: 0 +Line 11774: 0 +Line 11775: 0 +Line 11776: 0 +Line 11777: 0 +Line 11778: 1 +Line 11779: 1 +Line 11780: 1 +Line 11781: 0 +Line 11782: 1 +Line 11783: 0 +Line 11784: 0 +Line 11785: 1 +Line 11786: 0 +Line 11787: 1 +Line 11788: 0 +Line 11789: 0 +Line 11790: 1 +Line 11791: 0 +Line 11792: 0 +Line 11793: 0 +Line 11794: 0 +Line 11795: 0 +Line 11796: 0 +Line 11797: 0 +Line 11798: 0 +Line 11799: 0 +Line 11800: 0 +Line 11801: 0 +Line 11802: 0 +Line 11803: 0 +Line 11804: 0 +Line 11805: 0 +Line 11806: 0 +Line 11807: 0 +Line 11808: 0 +Line 11809: 0 +Line 11810: 1 +Line 11811: 1 +Line 11812: 1 +Line 11813: 0 +Line 11814: 1 +Line 11815: 0 +Line 11816: 0 +Line 11817: 1 +Line 11818: 1 +Line 11819: 0 +Line 11820: 1 +Line 11821: 0 +Line 11822: 0 +Line 11823: 1 +Line 11824: 0 +Line 11825: 0 +Line 11826: 0 +Line 11827: 0 +Line 11828: 0 +Line 11829: 0 +Line 11830: 0 +Line 11831: 0 +Line 11832: 0 +Line 11833: 0 +Line 11834: 0 +Line 11835: 0 +Line 11836: 0 +Line 11837: 0 +Line 11838: 0 +Line 11839: 0 +Line 11840: 0 +Line 11841: 0 +Line 11842: 1 +Line 11843: 1 +Line 11844: 1 +Line 11845: 0 +Line 11846: 1 +Line 11847: 0 +Line 11848: 1 +Line 11849: 0 +Line 11850: 1 +Line 11851: 0 +Line 11852: 1 +Line 11853: 1 +Line 11854: 0 +Line 11855: 1 +Line 11856: 0 +Line 11857: 0 +Line 11858: 0 +Line 11859: 0 +Line 11860: 0 +Line 11861: 0 +Line 11862: 0 +Line 11863: 0 +Line 11864: 0 +Line 11865: 0 +Line 11866: 0 +Line 11867: 0 +Line 11868: 0 +Line 11869: 0 +Line 11870: 0 +Line 11871: 0 +Line 11872: 0 +Line 11873: 0 +Line 11874: 1 +Line 11875: 1 +Line 11876: 1 +Line 11877: 0 +Line 11878: 1 +Line 11879: 1 +Line 11880: 0 +Line 11881: 0 +Line 11882: 0 +Line 11883: 1 +Line 11884: 0 +Line 11885: 0 +Line 11886: 0 +Line 11887: 0 +Line 11888: 0 +Line 11889: 0 +Line 11890: 0 +Line 11891: 0 +Line 11892: 0 +Line 11893: 0 +Line 11894: 0 +Line 11895: 0 +Line 11896: 0 +Line 11897: 0 +Line 11898: 0 +Line 11899: 0 +Line 11900: 0 +Line 11901: 0 +Line 11902: 0 +Line 11903: 0 +Line 11904: 0 +Line 11905: 0 +Line 11906: 1 +Line 11907: 1 +Line 11908: 1 +Line 11909: 0 +Line 11910: 1 +Line 11911: 1 +Line 11912: 1 +Line 11913: 0 +Line 11914: 0 +Line 11915: 0 +Line 11916: 0 +Line 11917: 0 +Line 11918: 0 +Line 11919: 0 +Line 11920: 0 +Line 11921: 0 +Line 11922: 0 +Line 11923: 0 +Line 11924: 0 +Line 11925: 0 +Line 11926: 0 +Line 11927: 0 +Line 11928: 0 +Line 11929: 0 +Line 11930: 0 +Line 11931: 0 +Line 11932: 0 +Line 11933: 0 +Line 11934: 0 +Line 11935: 0 +Line 11936: 0 +Line 11937: 0 +Line 11938: 1 +Line 11939: 1 +Line 11940: 1 +Line 11941: 0 +Line 11942: 1 +Line 11943: 1 +Line 11944: 1 +Line 11945: 1 +Line 11946: 1 +Line 11947: 0 +Line 11948: 0 +Line 11949: 1 +Line 11950: 0 +Line 11951: 0 +Line 11952: 0 +Line 11953: 0 +Line 11954: 0 +Line 11955: 0 +Line 11956: 0 +Line 11957: 0 +Line 11958: 0 +Line 11959: 0 +Line 11960: 0 +Line 11961: 0 +Line 11962: 0 +Line 11963: 0 +Line 11964: 0 +Line 11965: 0 +Line 11966: 0 +Line 11967: 0 +Line 11968: 0 +Line 11969: 0 +Line 11970: 1 +Line 11971: 1 +Line 11972: 1 +Line 11973: 1 +Line 11974: 0 +Line 11975: 0 +Line 11976: 0 +Line 11977: 0 +Line 11978: 0 +Line 11979: 1 +Line 11980: 1 +Line 11981: 1 +Line 11982: 1 +Line 11983: 1 +Line 11984: 0 +Line 11985: 0 +Line 11986: 0 +Line 11987: 0 +Line 11988: 0 +Line 11989: 0 +Line 11990: 0 +Line 11991: 0 +Line 11992: 0 +Line 11993: 0 +Line 11994: 0 +Line 11995: 0 +Line 11996: 0 +Line 11997: 0 +Line 11998: 0 +Line 11999: 0 +Line 12000: 0 +Line 12001: 0 +Line 12002: 1 +Line 12003: 1 +Line 12004: 1 +Line 12005: 1 +Line 12006: 0 +Line 12007: 0 +Line 12008: 0 +Line 12009: 0 +Line 12010: 0 +Line 12011: 1 +Line 12012: 0 +Line 12013: 0 +Line 12014: 0 +Line 12015: 1 +Line 12016: 0 +Line 12017: 0 +Line 12018: 0 +Line 12019: 0 +Line 12020: 0 +Line 12021: 0 +Line 12022: 0 +Line 12023: 0 +Line 12024: 0 +Line 12025: 0 +Line 12026: 0 +Line 12027: 0 +Line 12028: 0 +Line 12029: 0 +Line 12030: 0 +Line 12031: 0 +Line 12032: 0 +Line 12033: 0 +Line 12034: 1 +Line 12035: 1 +Line 12036: 1 +Line 12037: 0 +Line 12038: 1 +Line 12039: 1 +Line 12040: 1 +Line 12041: 0 +Line 12042: 0 +Line 12043: 1 +Line 12044: 1 +Line 12045: 0 +Line 12046: 1 +Line 12047: 0 +Line 12048: 0 +Line 12049: 0 +Line 12050: 0 +Line 12051: 0 +Line 12052: 0 +Line 12053: 0 +Line 12054: 0 +Line 12055: 0 +Line 12056: 0 +Line 12057: 0 +Line 12058: 0 +Line 12059: 0 +Line 12060: 0 +Line 12061: 0 +Line 12062: 0 +Line 12063: 0 +Line 12064: 0 +Line 12065: 0 +Line 12066: 1 +Line 12067: 1 +Line 12068: 1 +Line 12069: 0 +Line 12070: 1 +Line 12071: 0 +Line 12072: 1 +Line 12073: 0 +Line 12074: 0 +Line 12075: 1 +Line 12076: 1 +Line 12077: 0 +Line 12078: 0 +Line 12079: 1 +Line 12080: 0 +Line 12081: 0 +Line 12082: 0 +Line 12083: 0 +Line 12084: 0 +Line 12085: 0 +Line 12086: 0 +Line 12087: 0 +Line 12088: 0 +Line 12089: 0 +Line 12090: 0 +Line 12091: 0 +Line 12092: 0 +Line 12093: 0 +Line 12094: 0 +Line 12095: 0 +Line 12096: 0 +Line 12097: 0 +Line 12098: 1 +Line 12099: 1 +Line 12100: 1 +Line 12101: 0 +Line 12102: 0 +Line 12103: 0 +Line 12104: 1 +Line 12105: 1 +Line 12106: 1 +Line 12107: 1 +Line 12108: 0 +Line 12109: 0 +Line 12110: 1 +Line 12111: 0 +Line 12112: 0 +Line 12113: 0 +Line 12114: 0 +Line 12115: 0 +Line 12116: 0 +Line 12117: 0 +Line 12118: 0 +Line 12119: 0 +Line 12120: 0 +Line 12121: 0 +Line 12122: 0 +Line 12123: 0 +Line 12124: 0 +Line 12125: 0 +Line 12126: 0 +Line 12127: 0 +Line 12128: 0 +Line 12129: 0 +Line 12130: 1 +Line 12131: 1 +Line 12132: 0 +Line 12133: 1 +Line 12134: 1 +Line 12135: 0 +Line 12136: 1 +Line 12137: 0 +Line 12138: 0 +Line 12139: 1 +Line 12140: 0 +Line 12141: 0 +Line 12142: 0 +Line 12143: 0 +Line 12144: 0 +Line 12145: 0 +Line 12146: 0 +Line 12147: 0 +Line 12148: 0 +Line 12149: 0 +Line 12150: 0 +Line 12151: 0 +Line 12152: 0 +Line 12153: 0 +Line 12154: 0 +Line 12155: 0 +Line 12156: 0 +Line 12157: 0 +Line 12158: 0 +Line 12159: 0 +Line 12160: 0 +Line 12161: 0 +Line 12162: 1 +Line 12163: 1 +Line 12164: 0 +Line 12165: 0 +Line 12166: 1 +Line 12167: 1 +Line 12168: 0 +Line 12169: 1 +Line 12170: 0 +Line 12171: 1 +Line 12172: 1 +Line 12173: 1 +Line 12174: 1 +Line 12175: 1 +Line 12176: 0 +Line 12177: 0 +Line 12178: 0 +Line 12179: 0 +Line 12180: 0 +Line 12181: 0 +Line 12182: 0 +Line 12183: 0 +Line 12184: 0 +Line 12185: 0 +Line 12186: 0 +Line 12187: 0 +Line 12188: 0 +Line 12189: 0 +Line 12190: 0 +Line 12191: 0 +Line 12192: 0 +Line 12193: 0 +Line 12194: 1 +Line 12195: 0 +Line 12196: 1 +Line 12197: 1 +Line 12198: 1 +Line 12199: 1 +Line 12200: 0 +Line 12201: 1 +Line 12202: 0 +Line 12203: 1 +Line 12204: 1 +Line 12205: 0 +Line 12206: 0 +Line 12207: 1 +Line 12208: 0 +Line 12209: 0 +Line 12210: 0 +Line 12211: 0 +Line 12212: 0 +Line 12213: 0 +Line 12214: 0 +Line 12215: 0 +Line 12216: 0 +Line 12217: 0 +Line 12218: 0 +Line 12219: 0 +Line 12220: 0 +Line 12221: 0 +Line 12222: 0 +Line 12223: 0 +Line 12224: 0 +Line 12225: 0 +Line 12226: 1 +Line 12227: 0 +Line 12228: 1 +Line 12229: 0 +Line 12230: 1 +Line 12231: 0 +Line 12232: 0 +Line 12233: 1 +Line 12234: 1 +Line 12235: 1 +Line 12236: 1 +Line 12237: 1 +Line 12238: 1 +Line 12239: 0 +Line 12240: 0 +Line 12241: 0 +Line 12242: 0 +Line 12243: 0 +Line 12244: 0 +Line 12245: 0 +Line 12246: 0 +Line 12247: 0 +Line 12248: 0 +Line 12249: 0 +Line 12250: 0 +Line 12251: 0 +Line 12252: 0 +Line 12253: 0 +Line 12254: 0 +Line 12255: 0 +Line 12256: 0 +Line 12257: 0 +Line 12258: 1 +Line 12259: 0 +Line 12260: 0 +Line 12261: 1 +Line 12262: 0 +Line 12263: 0 +Line 12264: 1 +Line 12265: 1 +Line 12266: 0 +Line 12267: 1 +Line 12268: 0 +Line 12269: 1 +Line 12270: 0 +Line 12271: 1 +Line 12272: 0 +Line 12273: 0 +Line 12274: 0 +Line 12275: 0 +Line 12276: 0 +Line 12277: 0 +Line 12278: 0 +Line 12279: 0 +Line 12280: 0 +Line 12281: 0 +Line 12282: 0 +Line 12283: 0 +Line 12284: 0 +Line 12285: 0 +Line 12286: 0 +Line 12287: 0 +Line 12288: 0 +Line 12289: 0 +Line 12290: 0 +Line 12291: 1 +Line 12292: 1 +Line 12293: 1 +Line 12294: 1 +Line 12295: 0 +Line 12296: 0 +Line 12297: 1 +Line 12298: 1 +Line 12299: 1 +Line 12300: 0 +Line 12301: 0 +Line 12302: 0 +Line 12303: 1 +Line 12304: 0 +Line 12305: 0 +Line 12306: 0 +Line 12307: 0 +Line 12308: 0 +Line 12309: 0 +Line 12310: 0 +Line 12311: 0 +Line 12312: 0 +Line 12313: 0 +Line 12314: 0 +Line 12315: 0 +Line 12316: 0 +Line 12317: 0 +Line 12318: 0 +Line 12319: 0 +Line 12320: 0 +Line 12321: 0 +Line 12322: 0 +Line 12323: 1 +Line 12324: 0 +Line 12325: 1 +Line 12326: 1 +Line 12327: 1 +Line 12328: 0 +Line 12329: 1 +Line 12330: 1 +Line 12331: 0 +Line 12332: 1 +Line 12333: 1 +Line 12334: 0 +Line 12335: 0 +Line 12336: 0 +Line 12337: 0 +Line 12338: 0 +Line 12339: 0 +Line 12340: 0 +Line 12341: 0 +Line 12342: 0 +Line 12343: 0 +Line 12344: 0 +Line 12345: 0 +Line 12346: 0 +Line 12347: 0 +Line 12348: 0 +Line 12349: 0 +Line 12350: 0 +Line 12351: 0 +Line 12352: 0 +Line 12353: 0 +Line 12354: 0 +Line 12355: 0 +Line 12356: 1 +Line 12357: 1 +Line 12358: 1 +Line 12359: 1 +Line 12360: 1 +Line 12361: 1 +Line 12362: 1 +Line 12363: 0 +Line 12364: 0 +Line 12365: 1 +Line 12366: 1 +Line 12367: 1 +Line 12368: 0 +Line 12369: 0 +Line 12370: 0 +Line 12371: 0 +Line 12372: 0 +Line 12373: 0 +Line 12374: 0 +Line 12375: 0 +Line 12376: 0 +Line 12377: 0 +Line 12378: 0 +Line 12379: 0 +Line 12380: 0 +Line 12381: 0 +Line 12382: 0 +Line 12383: 0 +Line 12384: 0 +Line 12385: 0 +Line 12386: 0 +Line 12387: 0 +Line 12388: 1 +Line 12389: 0 +Line 12390: 0 +Line 12391: 0 +Line 12392: 0 +Line 12393: 0 +Line 12394: 0 +Line 12395: 0 +Line 12396: 1 +Line 12397: 0 +Line 12398: 1 +Line 12399: 0 +Line 12400: 0 +Line 12401: 0 +Line 12402: 0 +Line 12403: 0 +Line 12404: 0 +Line 12405: 0 +Line 12406: 0 +Line 12407: 0 +Line 12408: 0 +Line 12409: 0 +Line 12410: 0 +Line 12411: 0 +Line 12412: 0 +Line 12413: 0 +Line 12414: 0 +Line 12415: 0 +Line 12416: 0 +Line 12417: 0 +Line 12418: 0 +Line 12419: 0 +Line 12420: 0 +Line 12421: 0 +Line 12422: 0 +Line 12423: 0 +Line 12424: 0 +Line 12425: 0 +Line 12426: 0 +Line 12427: 0 +Line 12428: 0 +Line 12429: 0 +Line 12430: 0 +Line 12431: 0 +Line 12432: 0 +Line 12433: 0 +Line 12434: 0 +Line 12435: 0 +Line 12436: 0 +Line 12437: 0 +Line 12438: 0 +Line 12439: 0 +Line 12440: 0 +Line 12441: 0 +Line 12442: 0 +Line 12443: 0 +Line 12444: 0 +Line 12445: 0 +Line 12446: 0 +Line 12447: 0 +Line 12448: 0 +Line 12449: 0 +Line 12450: 0 +Line 12451: 0 +Line 12452: 1 +Line 12453: 0 +Line 12454: 0 +Line 12455: 0 +Line 12456: 0 +Line 12457: 0 +Line 12458: 1 +Line 12459: 1 +Line 12460: 1 +Line 12461: 0 +Line 12462: 0 +Line 12463: 1 +Line 12464: 0 +Line 12465: 0 +Line 12466: 1 +Line 12467: 0 +Line 12468: 0 +Line 12469: 0 +Line 12470: 0 +Line 12471: 1 +Line 12472: 0 +Line 12473: 0 +Line 12474: 1 +Line 12475: 0 +Line 12476: 0 +Line 12477: 0 +Line 12478: 0 +Line 12479: 1 +Line 12480: 0 +Line 12481: 0 +Line 12482: 0 +Line 12483: 1 +Line 12484: 1 +Line 12485: 1 +Line 12486: 0 +Line 12487: 1 +Line 12488: 0 +Line 12489: 0 +Line 12490: 0 +Line 12491: 0 +Line 12492: 1 +Line 12493: 1 +Line 12494: 0 +Line 12495: 1 +Line 12496: 0 +Line 12497: 0 +Line 12498: 1 +Line 12499: 1 +Line 12500: 0 +Line 12501: 0 +Line 12502: 1 +Line 12503: 0 +Line 12504: 1 +Line 12505: 1 +Line 12506: 0 +Line 12507: 0 +Line 12508: 0 +Line 12509: 0 +Line 12510: 1 +Line 12511: 0 +Line 12512: 0 +Line 12513: 0 +Line 12514: 1 +Line 12515: 1 +Line 12516: 0 +Line 12517: 1 +Line 12518: 0 +Line 12519: 0 +Line 12520: 1 +Line 12521: 0 +Line 12522: 1 +Line 12523: 1 +Line 12524: 1 +Line 12525: 0 +Line 12526: 1 +Line 12527: 1 +Line 12528: 0 +Line 12529: 0 +Line 12530: 1 +Line 12531: 0 +Line 12532: 1 +Line 12533: 1 +Line 12534: 0 +Line 12535: 0 +Line 12536: 1 +Line 12537: 0 +Line 12538: 1 +Line 12539: 0 +Line 12540: 0 +Line 12541: 0 +Line 12542: 1 +Line 12543: 0 +Line 12544: 0 +Line 12545: 1 +Line 12546: 0 +Line 12547: 0 +Line 12548: 0 +Line 12549: 1 +Line 12550: 0 +Line 12551: 0 +Line 12552: 0 +Line 12553: 0 +Line 12554: 1 +Line 12555: 1 +Line 12556: 0 +Line 12557: 0 +Line 12558: 0 +Line 12559: 1 +Line 12560: 0 +Line 12561: 0 +Line 12562: 0 +Line 12563: 1 +Line 12564: 0 +Line 12565: 0 +Line 12566: 0 +Line 12567: 1 +Line 12568: 1 +Line 12569: 0 +Line 12570: 1 +Line 12571: 0 +Line 12572: 0 +Line 12573: 0 +Line 12574: 0 +Line 12575: 0 +Line 12576: 0 +Line 12577: 1 +Line 12578: 0 +Line 12579: 0 +Line 12580: 0 +Line 12581: 1 +Line 12582: 0 +Line 12583: 0 +Line 12584: 0 +Line 12585: 0 +Line 12586: 1 +Line 12587: 1 +Line 12588: 0 +Line 12589: 0 +Line 12590: 0 +Line 12591: 1 +Line 12592: 1 +Line 12593: 1 +Line 12594: 1 +Line 12595: 0 +Line 12596: 1 +Line 12597: 1 +Line 12598: 1 +Line 12599: 0 +Line 12600: 0 +Line 12601: 1 +Line 12602: 1 +Line 12603: 0 +Line 12604: 0 +Line 12605: 0 +Line 12606: 0 +Line 12607: 0 +Line 12608: 0 +Line 12609: 0 +Line 12610: 1 +Line 12611: 1 +Line 12612: 0 +Line 12613: 1 +Line 12614: 0 +Line 12615: 0 +Line 12616: 1 +Line 12617: 0 +Line 12618: 1 +Line 12619: 1 +Line 12620: 1 +Line 12621: 1 +Line 12622: 0 +Line 12623: 0 +Line 12624: 1 +Line 12625: 1 +Line 12626: 0 +Line 12627: 1 +Line 12628: 0 +Line 12629: 0 +Line 12630: 1 +Line 12631: 1 +Line 12632: 0 +Line 12633: 1 +Line 12634: 0 +Line 12635: 1 +Line 12636: 1 +Line 12637: 1 +Line 12638: 1 +Line 12639: 0 +Line 12640: 0 +Line 12641: 0 +Line 12642: 0 +Line 12643: 1 +Line 12644: 1 +Line 12645: 1 +Line 12646: 0 +Line 12647: 1 +Line 12648: 0 +Line 12649: 0 +Line 12650: 0 +Line 12651: 0 +Line 12652: 1 +Line 12653: 1 +Line 12654: 0 +Line 12655: 1 +Line 12656: 1 +Line 12657: 1 +Line 12658: 0 +Line 12659: 0 +Line 12660: 1 +Line 12661: 1 +Line 12662: 0 +Line 12663: 1 +Line 12664: 0 +Line 12665: 0 +Line 12666: 1 +Line 12667: 1 +Line 12668: 1 +Line 12669: 1 +Line 12670: 1 +Line 12671: 0 +Line 12672: 0 +Line 12673: 0 +Line 12674: 0 +Line 12675: 0 +Line 12676: 1 +Line 12677: 0 +Line 12678: 0 +Line 12679: 0 +Line 12680: 0 +Line 12681: 0 +Line 12682: 1 +Line 12683: 1 +Line 12684: 1 +Line 12685: 0 +Line 12686: 0 +Line 12687: 1 +Line 12688: 1 +Line 12689: 1 +Line 12690: 0 +Line 12691: 1 +Line 12692: 1 +Line 12693: 1 +Line 12694: 1 +Line 12695: 0 +Line 12696: 1 +Line 12697: 1 +Line 12698: 0 +Line 12699: 1 +Line 12700: 1 +Line 12701: 1 +Line 12702: 1 +Line 12703: 1 +Line 12704: 0 +Line 12705: 0 +Line 12706: 0 +Line 12707: 0 +Line 12708: 0 +Line 12709: 0 +Line 12710: 0 +Line 12711: 0 +Line 12712: 0 +Line 12713: 0 +Line 12714: 0 +Line 12715: 0 +Line 12716: 0 +Line 12717: 0 +Line 12718: 0 +Line 12719: 0 +Line 12720: 0 +Line 12721: 0 +Line 12722: 0 +Line 12723: 0 +Line 12724: 0 +Line 12725: 0 +Line 12726: 0 +Line 12727: 0 +Line 12728: 0 +Line 12729: 0 +Line 12730: 0 +Line 12731: 0 +Line 12732: 0 +Line 12733: 0 +Line 12734: 0 +Line 12735: 0 +Line 12736: 0 +Line 12737: 0 +Line 12738: 0 +Line 12739: 0 +Line 12740: 0 +Line 12741: 0 +Line 12742: 0 +Line 12743: 1 +Line 12744: 1 +Line 12745: 0 +Line 12746: 0 +Line 12747: 1 +Line 12748: 1 +Line 12749: 0 +Line 12750: 0 +Line 12751: 1 +Line 12752: 0 +Line 12753: 0 +Line 12754: 0 +Line 12755: 0 +Line 12756: 0 +Line 12757: 0 +Line 12758: 0 +Line 12759: 0 +Line 12760: 0 +Line 12761: 0 +Line 12762: 0 +Line 12763: 0 +Line 12764: 0 +Line 12765: 0 +Line 12766: 0 +Line 12767: 0 +Line 12768: 0 +Line 12769: 0 +Line 12770: 0 +Line 12771: 0 +Line 12772: 1 +Line 12773: 0 +Line 12774: 1 +Line 12775: 1 +Line 12776: 0 +Line 12777: 0 +Line 12778: 1 +Line 12779: 0 +Line 12780: 0 +Line 12781: 1 +Line 12782: 1 +Line 12783: 1 +Line 12784: 0 +Line 12785: 0 +Line 12786: 0 +Line 12787: 0 +Line 12788: 0 +Line 12789: 0 +Line 12790: 0 +Line 12791: 0 +Line 12792: 0 +Line 12793: 0 +Line 12794: 0 +Line 12795: 0 +Line 12796: 0 +Line 12797: 0 +Line 12798: 0 +Line 12799: 0 +Line 12800: 0 +Line 12801: 0 +Line 12802: 1 +Line 12803: 0 +Line 12804: 0 +Line 12805: 0 +Line 12806: 1 +Line 12807: 1 +Line 12808: 0 +Line 12809: 0 +Line 12810: 1 +Line 12811: 0 +Line 12812: 1 +Line 12813: 0 +Line 12814: 0 +Line 12815: 0 +Line 12816: 0 +Line 12817: 0 +Line 12818: 0 +Line 12819: 0 +Line 12820: 0 +Line 12821: 0 +Line 12822: 0 +Line 12823: 0 +Line 12824: 0 +Line 12825: 0 +Line 12826: 0 +Line 12827: 0 +Line 12828: 0 +Line 12829: 0 +Line 12830: 0 +Line 12831: 0 +Line 12832: 0 +Line 12833: 0 +Line 12834: 1 +Line 12835: 1 +Line 12836: 1 +Line 12837: 0 +Line 12838: 1 +Line 12839: 1 +Line 12840: 0 +Line 12841: 0 +Line 12842: 1 +Line 12843: 0 +Line 12844: 1 +Line 12845: 0 +Line 12846: 0 +Line 12847: 0 +Line 12848: 0 +Line 12849: 0 +Line 12850: 0 +Line 12851: 0 +Line 12852: 0 +Line 12853: 0 +Line 12854: 0 +Line 12855: 0 +Line 12856: 0 +Line 12857: 0 +Line 12858: 0 +Line 12859: 0 +Line 12860: 0 +Line 12861: 0 +Line 12862: 0 +Line 12863: 0 +Line 12864: 0 +Line 12865: 1 +Line 12866: 0 +Line 12867: 0 +Line 12868: 0 +Line 12869: 1 +Line 12870: 0 +Line 12871: 0 +Line 12872: 1 +Line 12873: 0 +Line 12874: 1 +Line 12875: 1 +Line 12876: 0 +Line 12877: 1 +Line 12878: 1 +Line 12879: 0 +Line 12880: 0 +Line 12881: 0 +Line 12882: 0 +Line 12883: 0 +Line 12884: 0 +Line 12885: 0 +Line 12886: 0 +Line 12887: 0 +Line 12888: 0 +Line 12889: 0 +Line 12890: 0 +Line 12891: 0 +Line 12892: 0 +Line 12893: 0 +Line 12894: 0 +Line 12895: 0 +Line 12896: 0 +Line 12897: 1 +Line 12898: 0 +Line 12899: 0 +Line 12900: 0 +Line 12901: 1 +Line 12902: 1 +Line 12903: 0 +Line 12904: 0 +Line 12905: 0 +Line 12906: 1 +Line 12907: 1 +Line 12908: 0 +Line 12909: 1 +Line 12910: 1 +Line 12911: 1 +Line 12912: 0 +Line 12913: 0 +Line 12914: 0 +Line 12915: 0 +Line 12916: 0 +Line 12917: 0 +Line 12918: 0 +Line 12919: 0 +Line 12920: 0 +Line 12921: 0 +Line 12922: 0 +Line 12923: 0 +Line 12924: 0 +Line 12925: 0 +Line 12926: 0 +Line 12927: 0 +Line 12928: 0 +Line 12929: 1 +Line 12930: 0 +Line 12931: 0 +Line 12932: 0 +Line 12933: 1 +Line 12934: 1 +Line 12935: 0 +Line 12936: 0 +Line 12937: 1 +Line 12938: 0 +Line 12939: 0 +Line 12940: 1 +Line 12941: 1 +Line 12942: 1 +Line 12943: 1 +Line 12944: 0 +Line 12945: 0 +Line 12946: 0 +Line 12947: 0 +Line 12948: 0 +Line 12949: 0 +Line 12950: 0 +Line 12951: 0 +Line 12952: 0 +Line 12953: 0 +Line 12954: 0 +Line 12955: 0 +Line 12956: 0 +Line 12957: 0 +Line 12958: 0 +Line 12959: 0 +Line 12960: 0 +Line 12961: 1 +Line 12962: 0 +Line 12963: 0 +Line 12964: 0 +Line 12965: 1 +Line 12966: 1 +Line 12967: 0 +Line 12968: 0 +Line 12969: 1 +Line 12970: 0 +Line 12971: 0 +Line 12972: 1 +Line 12973: 1 +Line 12974: 1 +Line 12975: 1 +Line 12976: 0 +Line 12977: 0 +Line 12978: 0 +Line 12979: 0 +Line 12980: 0 +Line 12981: 0 +Line 12982: 0 +Line 12983: 0 +Line 12984: 0 +Line 12985: 0 +Line 12986: 0 +Line 12987: 0 +Line 12988: 0 +Line 12989: 0 +Line 12990: 0 +Line 12991: 0 +Line 12992: 0 +Line 12993: 1 +Line 12994: 0 +Line 12995: 0 +Line 12996: 0 +Line 12997: 1 +Line 12998: 1 +Line 12999: 0 +Line 13000: 0 +Line 13001: 1 +Line 13002: 0 +Line 13003: 0 +Line 13004: 1 +Line 13005: 1 +Line 13006: 1 +Line 13007: 1 +Line 13008: 0 +Line 13009: 0 +Line 13010: 0 +Line 13011: 0 +Line 13012: 0 +Line 13013: 0 +Line 13014: 0 +Line 13015: 0 +Line 13016: 0 +Line 13017: 0 +Line 13018: 0 +Line 13019: 0 +Line 13020: 0 +Line 13021: 0 +Line 13022: 0 +Line 13023: 0 +Line 13024: 0 +Line 13025: 1 +Line 13026: 0 +Line 13027: 0 +Line 13028: 0 +Line 13029: 1 +Line 13030: 1 +Line 13031: 0 +Line 13032: 0 +Line 13033: 1 +Line 13034: 0 +Line 13035: 0 +Line 13036: 1 +Line 13037: 1 +Line 13038: 1 +Line 13039: 1 +Line 13040: 0 +Line 13041: 0 +Line 13042: 0 +Line 13043: 0 +Line 13044: 0 +Line 13045: 0 +Line 13046: 0 +Line 13047: 0 +Line 13048: 0 +Line 13049: 0 +Line 13050: 0 +Line 13051: 0 +Line 13052: 0 +Line 13053: 0 +Line 13054: 0 +Line 13055: 0 +Line 13056: 0 +Line 13057: 1 +Line 13058: 0 +Line 13059: 0 +Line 13060: 0 +Line 13061: 1 +Line 13062: 1 +Line 13063: 0 +Line 13064: 0 +Line 13065: 0 +Line 13066: 1 +Line 13067: 1 +Line 13068: 0 +Line 13069: 1 +Line 13070: 1 +Line 13071: 1 +Line 13072: 0 +Line 13073: 0 +Line 13074: 0 +Line 13075: 0 +Line 13076: 0 +Line 13077: 0 +Line 13078: 0 +Line 13079: 0 +Line 13080: 0 +Line 13081: 0 +Line 13082: 0 +Line 13083: 0 +Line 13084: 0 +Line 13085: 0 +Line 13086: 0 +Line 13087: 0 +Line 13088: 0 +Line 13089: 1 +Line 13090: 0 +Line 13091: 0 +Line 13092: 0 +Line 13093: 1 +Line 13094: 0 +Line 13095: 0 +Line 13096: 1 +Line 13097: 0 +Line 13098: 1 +Line 13099: 1 +Line 13100: 0 +Line 13101: 1 +Line 13102: 1 +Line 13103: 0 +Line 13104: 0 +Line 13105: 0 +Line 13106: 0 +Line 13107: 0 +Line 13108: 0 +Line 13109: 0 +Line 13110: 0 +Line 13111: 0 +Line 13112: 0 +Line 13113: 0 +Line 13114: 0 +Line 13115: 0 +Line 13116: 0 +Line 13117: 0 +Line 13118: 0 +Line 13119: 0 +Line 13120: 0 +Line 13121: 0 +Line 13122: 1 +Line 13123: 1 +Line 13124: 1 +Line 13125: 0 +Line 13126: 1 +Line 13127: 1 +Line 13128: 0 +Line 13129: 0 +Line 13130: 1 +Line 13131: 0 +Line 13132: 1 +Line 13133: 0 +Line 13134: 0 +Line 13135: 0 +Line 13136: 0 +Line 13137: 0 +Line 13138: 0 +Line 13139: 0 +Line 13140: 0 +Line 13141: 0 +Line 13142: 0 +Line 13143: 0 +Line 13144: 0 +Line 13145: 0 +Line 13146: 0 +Line 13147: 0 +Line 13148: 0 +Line 13149: 0 +Line 13150: 0 +Line 13151: 0 +Line 13152: 0 +Line 13153: 0 +Line 13154: 1 +Line 13155: 0 +Line 13156: 0 +Line 13157: 0 +Line 13158: 1 +Line 13159: 1 +Line 13160: 0 +Line 13161: 0 +Line 13162: 1 +Line 13163: 0 +Line 13164: 1 +Line 13165: 0 +Line 13166: 0 +Line 13167: 0 +Line 13168: 0 +Line 13169: 0 +Line 13170: 0 +Line 13171: 0 +Line 13172: 0 +Line 13173: 0 +Line 13174: 0 +Line 13175: 0 +Line 13176: 0 +Line 13177: 0 +Line 13178: 0 +Line 13179: 0 +Line 13180: 0 +Line 13181: 0 +Line 13182: 0 +Line 13183: 0 +Line 13184: 0 +Line 13185: 0 +Line 13186: 0 +Line 13187: 0 +Line 13188: 1 +Line 13189: 0 +Line 13190: 1 +Line 13191: 1 +Line 13192: 0 +Line 13193: 0 +Line 13194: 1 +Line 13195: 0 +Line 13196: 0 +Line 13197: 1 +Line 13198: 1 +Line 13199: 1 +Line 13200: 0 +Line 13201: 0 +Line 13202: 0 +Line 13203: 0 +Line 13204: 0 +Line 13205: 0 +Line 13206: 0 +Line 13207: 0 +Line 13208: 0 +Line 13209: 0 +Line 13210: 0 +Line 13211: 0 +Line 13212: 0 +Line 13213: 0 +Line 13214: 0 +Line 13215: 0 +Line 13216: 0 +Line 13217: 0 +Line 13218: 0 +Line 13219: 0 +Line 13220: 0 +Line 13221: 0 +Line 13222: 0 +Line 13223: 1 +Line 13224: 1 +Line 13225: 0 +Line 13226: 0 +Line 13227: 1 +Line 13228: 1 +Line 13229: 0 +Line 13230: 0 +Line 13231: 1 +Line 13232: 0 +Line 13233: 0 +Line 13234: 0 +Line 13235: 0 +Line 13236: 0 +Line 13237: 0 +Line 13238: 0 +Line 13239: 0 +Line 13240: 0 +Line 13241: 0 +Line 13242: 0 +Line 13243: 0 +Line 13244: 0 +Line 13245: 0 +Line 13246: 0 +Line 13247: 0 +Send ENVE_DATA1_FILE +write_item 0000000000000000000011010000000000000000000000000000000000000000 +write_item 63: 0 +write_item 62: 0 +write_item 61: 0 +write_item 60: 0 +write_item 59: 0 +write_item 58: 0 +write_item 57: 0 +write_item 56: 0 +write_item 55: 0 +write_item 54: 0 +write_item 53: 0 +write_item 52: 0 +write_item 51: 0 +write_item 50: 0 +write_item 49: 0 +write_item 48: 0 +write_item 47: 0 +write_item 46: 0 +write_item 45: 0 +write_item 44: 0 +write_item 43: 1 +write_item 42: 1 +write_item 41: 0 +write_item 40: 1 +write_item 39: 0 +write_item 38: 0 +write_item 37: 0 +write_item 36: 0 +write_item 35: 0 +write_item 34: 0 +write_item 33: 0 +write_item 32: 0 +write_item 31: 0 +write_item 30: 0 +write_item 29: 0 +write_item 28: 0 +write_item 27: 0 +write_item 26: 0 +write_item 25: 0 +write_item 24: 0 +write_item 23: 0 +write_item 22: 0 +write_item 21: 0 +write_item 20: 0 +write_item 19: 0 +write_item 18: 0 +write_item 17: 0 +write_item 16: 0 +write_item 15: 0 +write_item 14: 0 +write_item 13: 0 +write_item 12: 0 +write_item 11: 0 +write_item 10: 0 +write_item 9: 0 +write_item 8: 0 +write_item 7: 0 +write_item 6: 0 +write_item 5: 0 +write_item 4: 0 +write_item 3: 0 +write_item 2: 0 +write_item 1: 0 +write_item 0: 0 +reg 0: 0 +reg 1: 0 +reg 2: 0 +reg 3: 0 +reg 4: 0 +reg 5: 0 +reg 6: 0 +reg 7: 0 +reg 8: 0 +reg 9: 0 +reg 10: 0 +reg 11: 0 +reg 12: 0 +reg 13: 0 +reg 14: 0 +reg 15: 0 +reg 16: 0 +reg 17: 0 +reg 18: 0 +reg 19: 0 +reg 20: 1 +reg 21: 1 +reg 22: 0 +reg 23: 1 +reg 24: 0 +reg 25: 0 +reg 26: 0 +reg 27: 0 +reg 28: 0 +reg 29: 0 +reg 30: 0 +reg 31: 0 +reg 32: 0 +reg 33: 0 +reg 34: 0 +reg 35: 0 +reg 36: 0 +reg 37: 0 +reg 38: 0 +reg 39: 0 +reg 40: 0 +reg 41: 0 +reg 42: 0 +reg 43: 0 +reg 44: 0 +reg 45: 0 +reg 46: 0 +reg 47: 0 +reg 48: 0 +reg 49: 0 +reg 50: 0 +reg 51: 0 +reg 52: 0 +reg 53: 0 +reg 54: 0 +reg 55: 0 +reg 56: 0 +reg 57: 0 +reg 58: 0 +reg 59: 0 +reg 60: 0 +reg 61: 0 +reg 62: 0 +reg 63: 0 +Line 0: 1 +Line 1: 1 +Line 2: 1 +Line 3: 0 +Line 4: 0 +Line 5: 1 +Line 6: 0 +Line 7: 0 +Line 8: 0 +Line 9: 0 +Line 10: 0 +Line 11: 0 +Line 12: 0 +Line 13: 0 +Line 14: 0 +Line 15: 0 +Line 16: 0 +Line 17: 0 +Line 18: 0 +Line 19: 0 +Line 20: 0 +Line 21: 0 +Line 22: 0 +Line 23: 0 +Line 24: 0 +Line 25: 0 +Line 26: 0 +Line 27: 0 +Line 28: 0 +Line 29: 0 +Line 30: 0 +Line 31: 0 +Line 32: 0 +Line 33: 0 +Line 34: 0 +Line 35: 0 +Line 36: 0 +Line 37: 0 +Line 38: 0 +Line 39: 0 +Line 40: 0 +Line 41: 0 +Line 42: 0 +Line 43: 0 +Line 44: 0 +Line 45: 0 +Line 46: 0 +Line 47: 0 +Line 48: 0 +Line 49: 0 +Line 50: 0 +Line 51: 0 +Line 52: 0 +Line 53: 0 +Line 54: 0 +Line 55: 0 +Line 56: 0 +Line 57: 0 +Line 58: 0 +Line 59: 0 +Line 60: 0 +Line 61: 0 +Line 62: 0 +Line 63: 0 +Line 64: 0 +Line 65: 0 +Line 66: 0 +Line 67: 0 +Line 68: 0 +Line 69: 0 +Line 70: 0 +Line 71: 1 +Line 72: 1 +Line 73: 1 +Line 74: 1 +Line 75: 0 +Line 76: 0 +Line 77: 1 +Line 78: 1 +Line 79: 1 +Line 80: 0 +Line 81: 0 +Line 82: 0 +Line 83: 0 +Line 84: 0 +Line 85: 1 +Line 86: 0 +Line 87: 1 +Line 88: 0 +Line 89: 0 +Line 90: 0 +Line 91: 0 +Line 92: 1 +Line 93: 1 +Line 94: 1 +Line 95: 0 +Line 96: 0 +Line 97: 0 +Line 98: 0 +Line 99: 0 +Line 100: 0 +Line 101: 1 +Line 102: 1 +Line 103: 1 +Line 104: 0 +Line 105: 1 +Line 106: 1 +Line 107: 0 +Line 108: 1 +Line 109: 0 +Line 110: 0 +Line 111: 1 +Line 112: 0 +Line 113: 0 +Line 114: 0 +Line 115: 0 +Line 116: 1 +Line 117: 0 +Line 118: 0 +Line 119: 1 +Line 120: 1 +Line 121: 0 +Line 122: 0 +Line 123: 1 +Line 124: 0 +Line 125: 0 +Line 126: 0 +Line 127: 1 +Line 128: 0 +Line 129: 0 +Line 130: 0 +Line 131: 0 +Line 132: 1 +Line 133: 1 +Line 134: 1 +Line 135: 1 +Line 136: 1 +Line 137: 1 +Line 138: 1 +Line 139: 0 +Line 140: 1 +Line 141: 1 +Line 142: 0 +Line 143: 1 +Line 144: 0 +Line 145: 0 +Line 146: 0 +Line 147: 0 +Line 148: 1 +Line 149: 1 +Line 150: 0 +Line 151: 1 +Line 152: 0 +Line 153: 0 +Line 154: 0 +Line 155: 0 +Line 156: 1 +Line 157: 0 +Line 158: 1 +Line 159: 0 +Line 160: 0 +Line 161: 0 +Line 162: 0 +Line 163: 1 +Line 164: 1 +Line 165: 0 +Line 166: 1 +Line 167: 0 +Line 168: 1 +Line 169: 0 +Line 170: 0 +Line 171: 0 +Line 172: 0 +Line 173: 1 +Line 174: 1 +Line 175: 0 +Line 176: 0 +Line 177: 0 +Line 178: 0 +Line 179: 0 +Line 180: 1 +Line 181: 1 +Line 182: 1 +Line 183: 1 +Line 184: 0 +Line 185: 0 +Line 186: 0 +Line 187: 1 +Line 188: 1 +Line 189: 0 +Line 190: 1 +Line 191: 0 +Line 192: 0 +Line 193: 0 +Line 194: 1 +Line 195: 0 +Line 196: 0 +Line 197: 1 +Line 198: 1 +Line 199: 0 +Line 200: 0 +Line 201: 0 +Line 202: 0 +Line 203: 0 +Line 204: 1 +Line 205: 1 +Line 206: 1 +Line 207: 1 +Line 208: 0 +Line 209: 0 +Line 210: 0 +Line 211: 0 +Line 212: 1 +Line 213: 1 +Line 214: 1 +Line 215: 1 +Line 216: 1 +Line 217: 0 +Line 218: 0 +Line 219: 0 +Line 220: 0 +Line 221: 1 +Line 222: 1 +Line 223: 0 +Line 224: 0 +Line 225: 0 +Line 226: 1 +Line 227: 1 +Line 228: 0 +Line 229: 0 +Line 230: 0 +Line 231: 1 +Line 232: 0 +Line 233: 1 +Line 234: 0 +Line 235: 0 +Line 236: 0 +Line 237: 1 +Line 238: 1 +Line 239: 1 +Line 240: 0 +Line 241: 0 +Line 242: 0 +Line 243: 0 +Line 244: 1 +Line 245: 1 +Line 246: 1 +Line 247: 0 +Line 248: 0 +Line 249: 1 +Line 250: 0 +Line 251: 0 +Line 252: 0 +Line 253: 1 +Line 254: 0 +Line 255: 0 +Line 256: 0 +Line 257: 0 +Line 258: 1 +Line 259: 1 +Line 260: 1 +Line 261: 0 +Line 262: 1 +Line 263: 0 +Line 264: 1 +Line 265: 1 +Line 266: 1 +Line 267: 1 +Line 268: 0 +Line 269: 1 +Line 270: 1 +Line 271: 1 +Line 272: 0 +Line 273: 0 +Line 274: 0 +Line 275: 0 +Line 276: 1 +Line 277: 0 +Line 278: 1 +Line 279: 1 +Line 280: 0 +Line 281: 1 +Line 282: 1 +Line 283: 1 +Line 284: 0 +Line 285: 1 +Line 286: 1 +Line 287: 0 +Line 288: 0 +Line 289: 1 +Line 290: 0 +Line 291: 0 +Line 292: 0 +Line 293: 0 +Line 294: 1 +Line 295: 0 +Line 296: 0 +Line 297: 0 +Line 298: 0 +Line 299: 1 +Line 300: 0 +Line 301: 0 +Line 302: 1 +Line 303: 1 +Line 304: 0 +Line 305: 0 +Line 306: 0 +Line 307: 0 +Line 308: 0 +Line 309: 1 +Line 310: 1 +Line 311: 1 +Line 312: 0 +Line 313: 1 +Line 314: 1 +Line 315: 0 +Line 316: 1 +Line 317: 0 +Line 318: 1 +Line 319: 0 +Line 320: 0 +Line 321: 1 +Line 322: 0 +Line 323: 0 +Line 324: 0 +Line 325: 1 +Line 326: 0 +Line 327: 1 +Line 328: 1 +Line 329: 1 +Line 330: 0 +Line 331: 1 +Line 332: 0 +Line 333: 1 +Line 334: 0 +Line 335: 1 +Line 336: 0 +Line 337: 0 +Line 338: 0 +Line 339: 0 +Line 340: 0 +Line 341: 0 +Line 342: 1 +Line 343: 0 +Line 344: 1 +Line 345: 0 +Line 346: 0 +Line 347: 1 +Line 348: 0 +Line 349: 0 +Line 350: 0 +Line 351: 0 +Line 352: 0 +Line 353: 1 +Line 354: 0 +Line 355: 0 +Line 356: 0 +Line 357: 1 +Line 358: 0 +Line 359: 1 +Line 360: 1 +Line 361: 1 +Line 362: 0 +Line 363: 1 +Line 364: 0 +Line 365: 1 +Line 366: 0 +Line 367: 1 +Line 368: 1 +Line 369: 1 +Line 370: 1 +Line 371: 1 +Line 372: 1 +Line 373: 1 +Line 374: 0 +Line 375: 1 +Line 376: 0 +Line 377: 1 +Line 378: 1 +Line 379: 1 +Line 380: 0 +Line 381: 0 +Line 382: 0 +Line 383: 0 +Line 384: 0 +Line 385: 1 +Line 386: 0 +Line 387: 0 +Line 388: 0 +Line 389: 0 +Line 390: 1 +Line 391: 0 +Line 392: 0 +Line 393: 0 +Line 394: 0 +Line 395: 1 +Line 396: 0 +Line 397: 0 +Line 398: 1 +Line 399: 1 +Line 400: 1 +Line 401: 1 +Line 402: 1 +Line 403: 1 +Line 404: 1 +Line 405: 0 +Line 406: 0 +Line 407: 0 +Line 408: 1 +Line 409: 0 +Line 410: 0 +Line 411: 1 +Line 412: 0 +Line 413: 1 +Line 414: 1 +Line 415: 0 +Line 416: 0 +Line 417: 0 +Line 418: 1 +Line 419: 1 +Line 420: 1 +Line 421: 0 +Line 422: 1 +Line 423: 0 +Line 424: 1 +Line 425: 1 +Line 426: 1 +Line 427: 1 +Line 428: 0 +Line 429: 1 +Line 430: 1 +Line 431: 1 +Line 432: 1 +Line 433: 1 +Line 434: 1 +Line 435: 1 +Line 436: 0 +Line 437: 1 +Line 438: 0 +Line 439: 0 +Line 440: 1 +Line 441: 0 +Line 442: 0 +Line 443: 0 +Line 444: 1 +Line 445: 0 +Line 446: 1 +Line 447: 0 +Line 448: 0 +Line 449: 0 +Line 450: 1 +Line 451: 1 +Line 452: 0 +Line 453: 0 +Line 454: 0 +Line 455: 1 +Line 456: 0 +Line 457: 1 +Line 458: 0 +Line 459: 0 +Line 460: 0 +Line 461: 1 +Line 462: 1 +Line 463: 1 +Line 464: 1 +Line 465: 1 +Line 466: 1 +Line 467: 1 +Line 468: 0 +Line 469: 0 +Line 470: 0 +Line 471: 1 +Line 472: 1 +Line 473: 0 +Line 474: 1 +Line 475: 1 +Line 476: 1 +Line 477: 1 +Line 478: 0 +Line 479: 0 +Line 480: 0 +Line 481: 0 +Line 482: 1 +Line 483: 0 +Line 484: 0 +Line 485: 1 +Line 486: 1 +Line 487: 0 +Line 488: 0 +Line 489: 0 +Line 490: 0 +Line 491: 0 +Line 492: 1 +Line 493: 1 +Line 494: 1 +Line 495: 1 +Line 496: 1 +Line 497: 1 +Line 498: 1 +Line 499: 1 +Line 500: 0 +Line 501: 0 +Line 502: 0 +Line 503: 0 +Line 504: 0 +Line 505: 1 +Line 506: 1 +Line 507: 1 +Line 508: 1 +Line 509: 0 +Line 510: 1 +Line 511: 0 +Line 512: 0 +Line 513: 0 +Line 514: 0 +Line 515: 1 +Line 516: 1 +Line 517: 0 +Line 518: 1 +Line 519: 0 +Line 520: 1 +Line 521: 0 +Line 522: 0 +Line 523: 0 +Line 524: 0 +Line 525: 1 +Line 526: 1 +Line 527: 0 +Line 528: 1 +Line 529: 1 +Line 530: 1 +Line 531: 1 +Line 532: 0 +Line 533: 0 +Line 534: 0 +Line 535: 0 +Line 536: 1 +Line 537: 1 +Line 538: 1 +Line 539: 0 +Line 540: 0 +Line 541: 1 +Line 542: 1 +Line 543: 0 +Line 544: 0 +Line 545: 0 +Line 546: 0 +Line 547: 0 +Line 548: 1 +Line 549: 1 +Line 550: 1 +Line 551: 1 +Line 552: 1 +Line 553: 1 +Line 554: 1 +Line 555: 0 +Line 556: 1 +Line 557: 1 +Line 558: 0 +Line 559: 1 +Line 560: 1 +Line 561: 1 +Line 562: 1 +Line 563: 1 +Line 564: 0 +Line 565: 0 +Line 566: 1 +Line 567: 0 +Line 568: 1 +Line 569: 1 +Line 570: 1 +Line 571: 1 +Line 572: 0 +Line 573: 1 +Line 574: 1 +Line 575: 0 +Line 576: 0 +Line 577: 0 +Line 578: 0 +Line 579: 0 +Line 580: 0 +Line 581: 1 +Line 582: 1 +Line 583: 1 +Line 584: 0 +Line 585: 1 +Line 586: 1 +Line 587: 0 +Line 588: 1 +Line 589: 0 +Line 590: 0 +Line 591: 1 +Line 592: 1 +Line 593: 1 +Line 594: 1 +Line 595: 1 +Line 596: 0 +Line 597: 1 +Line 598: 1 +Line 599: 0 +Line 600: 0 +Line 601: 1 +Line 602: 1 +Line 603: 0 +Line 604: 1 +Line 605: 1 +Line 606: 1 +Line 607: 1 +Line 608: 0 +Line 609: 0 +Line 610: 0 +Line 611: 0 +Line 612: 0 +Line 613: 0 +Line 614: 0 +Line 615: 1 +Line 616: 1 +Line 617: 1 +Line 618: 1 +Line 619: 0 +Line 620: 0 +Line 621: 1 +Line 622: 1 +Line 623: 1 +Line 624: 1 +Line 625: 1 +Line 626: 1 +Line 627: 1 +Line 628: 1 +Line 629: 0 +Line 630: 1 +Line 631: 0 +Line 632: 1 +Line 633: 1 +Line 634: 1 +Line 635: 1 +Line 636: 0 +Line 637: 0 +Line 638: 1 +Line 639: 0 +Line 640: 0 +Line 641: 0 +Line 642: 0 +Line 643: 0 +Line 644: 0 +Line 645: 0 +Line 646: 0 +Line 647: 0 +Line 648: 0 +Line 649: 0 +Line 650: 0 +Line 651: 0 +Line 652: 0 +Line 653: 0 +Line 654: 0 +Line 655: 0 +Line 656: 0 +Line 657: 0 +Line 658: 0 +Line 659: 0 +Line 660: 0 +Line 661: 0 +Line 662: 0 +Line 663: 0 +Line 664: 0 +Line 665: 0 +Line 666: 0 +Line 667: 0 +Line 668: 0 +Line 669: 0 +Line 670: 0 +Line 671: 0 +Line 672: 0 +Line 673: 1 +Line 674: 0 +Line 675: 0 +Line 676: 0 +Line 677: 1 +Line 678: 1 +Line 679: 0 +Line 680: 0 +Line 681: 1 +Line 682: 0 +Line 683: 1 +Line 684: 0 +Line 685: 0 +Line 686: 0 +Line 687: 0 +Line 688: 0 +Line 689: 0 +Line 690: 0 +Line 691: 0 +Line 692: 0 +Line 693: 0 +Line 694: 0 +Line 695: 0 +Line 696: 0 +Line 697: 0 +Line 698: 0 +Line 699: 0 +Line 700: 0 +Line 701: 0 +Line 702: 0 +Line 703: 0 +Line 704: 0 +Line 705: 1 +Line 706: 0 +Line 707: 0 +Line 708: 0 +Line 709: 1 +Line 710: 1 +Line 711: 0 +Line 712: 0 +Line 713: 1 +Line 714: 0 +Line 715: 1 +Line 716: 0 +Line 717: 0 +Line 718: 0 +Line 719: 0 +Line 720: 0 +Line 721: 0 +Line 722: 0 +Line 723: 0 +Line 724: 0 +Line 725: 0 +Line 726: 0 +Line 727: 0 +Line 728: 0 +Line 729: 0 +Line 730: 0 +Line 731: 0 +Line 732: 0 +Line 733: 0 +Line 734: 0 +Line 735: 0 +Line 736: 0 +Line 737: 1 +Line 738: 0 +Line 739: 0 +Line 740: 0 +Line 741: 1 +Line 742: 1 +Line 743: 0 +Line 744: 0 +Line 745: 1 +Line 746: 0 +Line 747: 1 +Line 748: 0 +Line 749: 0 +Line 750: 0 +Line 751: 0 +Line 752: 0 +Line 753: 0 +Line 754: 0 +Line 755: 0 +Line 756: 0 +Line 757: 0 +Line 758: 0 +Line 759: 0 +Line 760: 0 +Line 761: 0 +Line 762: 0 +Line 763: 0 +Line 764: 0 +Line 765: 0 +Line 766: 0 +Line 767: 0 +Line 768: 0 +Line 769: 1 +Line 770: 0 +Line 771: 0 +Line 772: 0 +Line 773: 1 +Line 774: 1 +Line 775: 0 +Line 776: 0 +Line 777: 1 +Line 778: 0 +Line 779: 1 +Line 780: 0 +Line 781: 0 +Line 782: 0 +Line 783: 0 +Line 784: 0 +Line 785: 0 +Line 786: 0 +Line 787: 0 +Line 788: 0 +Line 789: 0 +Line 790: 0 +Line 791: 0 +Line 792: 0 +Line 793: 0 +Line 794: 0 +Line 795: 0 +Line 796: 0 +Line 797: 0 +Line 798: 0 +Line 799: 0 +Line 800: 0 +Line 801: 1 +Line 802: 0 +Line 803: 0 +Line 804: 0 +Line 805: 1 +Line 806: 1 +Line 807: 0 +Line 808: 0 +Line 809: 1 +Line 810: 0 +Line 811: 1 +Line 812: 0 +Line 813: 0 +Line 814: 0 +Line 815: 0 +Line 816: 0 +Line 817: 0 +Line 818: 0 +Line 819: 0 +Line 820: 0 +Line 821: 0 +Line 822: 0 +Line 823: 0 +Line 824: 0 +Line 825: 0 +Line 826: 0 +Line 827: 0 +Line 828: 0 +Line 829: 0 +Line 830: 0 +Line 831: 0 +Line 832: 0 +Line 833: 1 +Line 834: 0 +Line 835: 0 +Line 836: 0 +Line 837: 1 +Line 838: 1 +Line 839: 0 +Line 840: 0 +Line 841: 1 +Line 842: 0 +Line 843: 1 +Line 844: 0 +Line 845: 0 +Line 846: 0 +Line 847: 0 +Line 848: 0 +Line 849: 0 +Line 850: 0 +Line 851: 0 +Line 852: 0 +Line 853: 0 +Line 854: 0 +Line 855: 0 +Line 856: 0 +Line 857: 0 +Line 858: 0 +Line 859: 0 +Line 860: 0 +Line 861: 0 +Line 862: 0 +Line 863: 0 +Line 864: 0 +Line 865: 1 +Line 866: 0 +Line 867: 0 +Line 868: 0 +Line 869: 1 +Line 870: 1 +Line 871: 0 +Line 872: 0 +Line 873: 1 +Line 874: 0 +Line 875: 1 +Line 876: 0 +Line 877: 0 +Line 878: 0 +Line 879: 0 +Line 880: 0 +Line 881: 0 +Line 882: 0 +Line 883: 0 +Line 884: 0 +Line 885: 0 +Line 886: 0 +Line 887: 0 +Line 888: 0 +Line 889: 0 +Line 890: 0 +Line 891: 0 +Line 892: 0 +Line 893: 0 +Line 894: 0 +Line 895: 0 +Line 896: 0 +Line 897: 1 +Line 898: 0 +Line 899: 0 +Line 900: 0 +Line 901: 1 +Line 902: 1 +Line 903: 0 +Line 904: 0 +Line 905: 1 +Line 906: 0 +Line 907: 1 +Line 908: 0 +Line 909: 0 +Line 910: 0 +Line 911: 0 +Line 912: 0 +Line 913: 0 +Line 914: 0 +Line 915: 0 +Line 916: 0 +Line 917: 0 +Line 918: 0 +Line 919: 0 +Line 920: 0 +Line 921: 0 +Line 922: 0 +Line 923: 0 +Line 924: 0 +Line 925: 0 +Line 926: 0 +Line 927: 0 +Line 928: 0 +Line 929: 1 +Line 930: 0 +Line 931: 0 +Line 932: 0 +Line 933: 1 +Line 934: 1 +Line 935: 0 +Line 936: 0 +Line 937: 1 +Line 938: 0 +Line 939: 1 +Line 940: 0 +Line 941: 0 +Line 942: 0 +Line 943: 0 +Line 944: 0 +Line 945: 0 +Line 946: 0 +Line 947: 0 +Line 948: 0 +Line 949: 0 +Line 950: 0 +Line 951: 0 +Line 952: 0 +Line 953: 0 +Line 954: 0 +Line 955: 0 +Line 956: 0 +Line 957: 0 +Line 958: 0 +Line 959: 0 +Line 960: 0 +Line 961: 1 +Line 962: 0 +Line 963: 0 +Line 964: 0 +Line 965: 1 +Line 966: 1 +Line 967: 0 +Line 968: 0 +Line 969: 1 +Line 970: 0 +Line 971: 1 +Line 972: 0 +Line 973: 0 +Line 974: 0 +Line 975: 0 +Line 976: 0 +Line 977: 0 +Line 978: 0 +Line 979: 0 +Line 980: 0 +Line 981: 0 +Line 982: 0 +Line 983: 0 +Line 984: 0 +Line 985: 0 +Line 986: 0 +Line 987: 0 +Line 988: 0 +Line 989: 0 +Line 990: 0 +Line 991: 0 +Line 992: 0 +Line 993: 1 +Line 994: 0 +Line 995: 0 +Line 996: 0 +Line 997: 1 +Line 998: 1 +Line 999: 0 +Line 1000: 0 +Line 1001: 1 +Line 1002: 0 +Line 1003: 1 +Line 1004: 0 +Line 1005: 0 +Line 1006: 0 +Line 1007: 0 +Line 1008: 0 +Line 1009: 0 +Line 1010: 0 +Line 1011: 0 +Line 1012: 0 +Line 1013: 0 +Line 1014: 0 +Line 1015: 0 +Line 1016: 0 +Line 1017: 0 +Line 1018: 0 +Line 1019: 0 +Line 1020: 0 +Line 1021: 0 +Line 1022: 0 +Line 1023: 0 +Line 1024: 0 +Line 1025: 1 +Line 1026: 0 +Line 1027: 0 +Line 1028: 0 +Line 1029: 1 +Line 1030: 1 +Line 1031: 0 +Line 1032: 0 +Line 1033: 1 +Line 1034: 0 +Line 1035: 1 +Line 1036: 0 +Line 1037: 0 +Line 1038: 0 +Line 1039: 0 +Line 1040: 0 +Line 1041: 0 +Line 1042: 0 +Line 1043: 0 +Line 1044: 0 +Line 1045: 0 +Line 1046: 0 +Line 1047: 0 +Line 1048: 0 +Line 1049: 0 +Line 1050: 0 +Line 1051: 0 +Line 1052: 0 +Line 1053: 0 +Line 1054: 0 +Line 1055: 0 +Line 1056: 0 +Line 1057: 1 +Line 1058: 0 +Line 1059: 0 +Line 1060: 0 +Line 1061: 1 +Line 1062: 1 +Line 1063: 0 +Line 1064: 0 +Line 1065: 1 +Line 1066: 0 +Line 1067: 1 +Line 1068: 0 +Line 1069: 0 +Line 1070: 0 +Line 1071: 0 +Line 1072: 0 +Line 1073: 0 +Line 1074: 0 +Line 1075: 0 +Line 1076: 0 +Line 1077: 0 +Line 1078: 0 +Line 1079: 0 +Line 1080: 0 +Line 1081: 0 +Line 1082: 0 +Line 1083: 0 +Line 1084: 0 +Line 1085: 0 +Line 1086: 0 +Line 1087: 0 +Line 1088: 0 +Line 1089: 1 +Line 1090: 0 +Line 1091: 0 +Line 1092: 0 +Line 1093: 1 +Line 1094: 1 +Line 1095: 0 +Line 1096: 0 +Line 1097: 1 +Line 1098: 0 +Line 1099: 1 +Line 1100: 0 +Line 1101: 0 +Line 1102: 0 +Line 1103: 0 +Line 1104: 0 +Line 1105: 0 +Line 1106: 0 +Line 1107: 0 +Line 1108: 0 +Line 1109: 0 +Line 1110: 0 +Line 1111: 0 +Line 1112: 0 +Line 1113: 0 +Line 1114: 0 +Line 1115: 0 +Line 1116: 0 +Line 1117: 0 +Line 1118: 0 +Line 1119: 0 +Line 1120: 0 +Line 1121: 1 +Line 1122: 0 +Line 1123: 0 +Line 1124: 0 +Line 1125: 1 +Line 1126: 1 +Line 1127: 0 +Line 1128: 0 +Line 1129: 1 +Line 1130: 0 +Line 1131: 1 +Line 1132: 0 +Line 1133: 0 +Line 1134: 0 +Line 1135: 0 +Line 1136: 0 +Line 1137: 0 +Line 1138: 0 +Line 1139: 0 +Line 1140: 0 +Line 1141: 0 +Line 1142: 0 +Line 1143: 0 +Line 1144: 0 +Line 1145: 0 +Line 1146: 0 +Line 1147: 0 +Line 1148: 0 +Line 1149: 0 +Line 1150: 0 +Line 1151: 0 +Line 1152: 0 +Line 1153: 1 +Line 1154: 0 +Line 1155: 0 +Line 1156: 0 +Line 1157: 1 +Line 1158: 1 +Line 1159: 0 +Line 1160: 0 +Line 1161: 1 +Line 1162: 0 +Line 1163: 1 +Line 1164: 0 +Line 1165: 0 +Line 1166: 0 +Line 1167: 0 +Line 1168: 0 +Line 1169: 0 +Line 1170: 0 +Line 1171: 0 +Line 1172: 0 +Line 1173: 0 +Line 1174: 0 +Line 1175: 0 +Line 1176: 0 +Line 1177: 0 +Line 1178: 0 +Line 1179: 0 +Line 1180: 0 +Line 1181: 0 +Line 1182: 0 +Line 1183: 0 +Line 1184: 0 +Line 1185: 1 +Line 1186: 0 +Line 1187: 0 +Line 1188: 0 +Line 1189: 1 +Line 1190: 1 +Line 1191: 0 +Line 1192: 0 +Line 1193: 1 +Line 1194: 0 +Line 1195: 1 +Line 1196: 0 +Line 1197: 0 +Line 1198: 0 +Line 1199: 0 +Line 1200: 0 +Line 1201: 0 +Line 1202: 0 +Line 1203: 0 +Line 1204: 0 +Line 1205: 0 +Line 1206: 0 +Line 1207: 0 +Line 1208: 0 +Line 1209: 0 +Line 1210: 0 +Line 1211: 0 +Line 1212: 0 +Line 1213: 0 +Line 1214: 0 +Line 1215: 0 +Line 1216: 0 +Line 1217: 1 +Line 1218: 0 +Line 1219: 0 +Line 1220: 0 +Line 1221: 1 +Line 1222: 1 +Line 1223: 0 +Line 1224: 0 +Line 1225: 1 +Line 1226: 0 +Line 1227: 1 +Line 1228: 0 +Line 1229: 0 +Line 1230: 0 +Line 1231: 0 +Line 1232: 0 +Line 1233: 0 +Line 1234: 0 +Line 1235: 0 +Line 1236: 0 +Line 1237: 0 +Line 1238: 0 +Line 1239: 0 +Line 1240: 0 +Line 1241: 0 +Line 1242: 0 +Line 1243: 0 +Line 1244: 0 +Line 1245: 0 +Line 1246: 0 +Line 1247: 0 +Line 1248: 0 +Line 1249: 1 +Line 1250: 0 +Line 1251: 0 +Line 1252: 0 +Line 1253: 1 +Line 1254: 1 +Line 1255: 0 +Line 1256: 0 +Line 1257: 1 +Line 1258: 0 +Line 1259: 1 +Line 1260: 0 +Line 1261: 0 +Line 1262: 0 +Line 1263: 0 +Line 1264: 0 +Line 1265: 0 +Line 1266: 0 +Line 1267: 0 +Line 1268: 0 +Line 1269: 0 +Line 1270: 0 +Line 1271: 0 +Line 1272: 0 +Line 1273: 0 +Line 1274: 0 +Line 1275: 0 +Line 1276: 0 +Line 1277: 0 +Line 1278: 0 +Line 1279: 0 +Line 1280: 0 +Line 1281: 1 +Line 1282: 0 +Line 1283: 0 +Line 1284: 0 +Line 1285: 1 +Line 1286: 1 +Line 1287: 0 +Line 1288: 0 +Line 1289: 1 +Line 1290: 0 +Line 1291: 1 +Line 1292: 0 +Line 1293: 0 +Line 1294: 0 +Line 1295: 0 +Line 1296: 0 +Line 1297: 0 +Line 1298: 0 +Line 1299: 0 +Line 1300: 0 +Line 1301: 0 +Line 1302: 0 +Line 1303: 0 +Line 1304: 0 +Line 1305: 0 +Line 1306: 0 +Line 1307: 0 +Line 1308: 0 +Line 1309: 0 +Line 1310: 0 +Line 1311: 0 +Line 1312: 0 +Line 1313: 1 +Line 1314: 0 +Line 1315: 0 +Line 1316: 0 +Line 1317: 1 +Line 1318: 1 +Line 1319: 0 +Line 1320: 0 +Line 1321: 1 +Line 1322: 0 +Line 1323: 1 +Line 1324: 0 +Line 1325: 0 +Line 1326: 0 +Line 1327: 0 +Line 1328: 0 +Line 1329: 0 +Line 1330: 0 +Line 1331: 0 +Line 1332: 0 +Line 1333: 0 +Line 1334: 0 +Line 1335: 0 +Line 1336: 0 +Line 1337: 0 +Line 1338: 0 +Line 1339: 0 +Line 1340: 0 +Line 1341: 0 +Line 1342: 0 +Line 1343: 0 +Line 1344: 0 +Line 1345: 1 +Line 1346: 0 +Line 1347: 0 +Line 1348: 0 +Line 1349: 1 +Line 1350: 1 +Line 1351: 0 +Line 1352: 0 +Line 1353: 1 +Line 1354: 0 +Line 1355: 1 +Line 1356: 0 +Line 1357: 0 +Line 1358: 0 +Line 1359: 0 +Line 1360: 0 +Line 1361: 0 +Line 1362: 0 +Line 1363: 0 +Line 1364: 0 +Line 1365: 0 +Line 1366: 0 +Line 1367: 0 +Line 1368: 0 +Line 1369: 0 +Line 1370: 0 +Line 1371: 0 +Line 1372: 0 +Line 1373: 0 +Line 1374: 0 +Line 1375: 0 +Line 1376: 0 +Line 1377: 1 +Line 1378: 0 +Line 1379: 0 +Line 1380: 0 +Line 1381: 1 +Line 1382: 1 +Line 1383: 0 +Line 1384: 0 +Line 1385: 1 +Line 1386: 0 +Line 1387: 1 +Line 1388: 0 +Line 1389: 0 +Line 1390: 0 +Line 1391: 0 +Line 1392: 0 +Line 1393: 0 +Line 1394: 0 +Line 1395: 0 +Line 1396: 0 +Line 1397: 0 +Line 1398: 0 +Line 1399: 0 +Line 1400: 0 +Line 1401: 0 +Line 1402: 0 +Line 1403: 0 +Line 1404: 0 +Line 1405: 0 +Line 1406: 0 +Line 1407: 0 +Line 1408: 0 +Line 1409: 1 +Line 1410: 0 +Line 1411: 0 +Line 1412: 0 +Line 1413: 1 +Line 1414: 1 +Line 1415: 0 +Line 1416: 0 +Line 1417: 1 +Line 1418: 0 +Line 1419: 1 +Line 1420: 0 +Line 1421: 0 +Line 1422: 0 +Line 1423: 0 +Line 1424: 0 +Line 1425: 0 +Line 1426: 0 +Line 1427: 0 +Line 1428: 0 +Line 1429: 0 +Line 1430: 0 +Line 1431: 0 +Line 1432: 0 +Line 1433: 0 +Line 1434: 0 +Line 1435: 0 +Line 1436: 0 +Line 1437: 0 +Line 1438: 0 +Line 1439: 0 +Line 1440: 0 +Line 1441: 1 +Line 1442: 0 +Line 1443: 0 +Line 1444: 0 +Line 1445: 1 +Line 1446: 1 +Line 1447: 0 +Line 1448: 0 +Line 1449: 1 +Line 1450: 0 +Line 1451: 1 +Line 1452: 0 +Line 1453: 0 +Line 1454: 0 +Line 1455: 0 +Line 1456: 0 +Line 1457: 0 +Line 1458: 0 +Line 1459: 0 +Line 1460: 0 +Line 1461: 0 +Line 1462: 0 +Line 1463: 0 +Line 1464: 0 +Line 1465: 0 +Line 1466: 0 +Line 1467: 0 +Line 1468: 0 +Line 1469: 0 +Line 1470: 0 +Line 1471: 0 +Line 1472: 0 +Line 1473: 0 +Line 1474: 0 +Line 1475: 1 +Line 1476: 0 +Line 1477: 1 +Line 1478: 0 +Line 1479: 0 +Line 1480: 0 +Line 1481: 0 +Line 1482: 1 +Line 1483: 0 +Line 1484: 1 +Line 1485: 0 +Line 1486: 1 +Line 1487: 1 +Line 1488: 0 +Line 1489: 0 +Line 1490: 0 +Line 1491: 0 +Line 1492: 0 +Line 1493: 0 +Line 1494: 0 +Line 1495: 0 +Line 1496: 0 +Line 1497: 0 +Line 1498: 0 +Line 1499: 0 +Line 1500: 0 +Line 1501: 0 +Line 1502: 0 +Line 1503: 0 +Line 1504: 0 +Line 1505: 0 +Line 1506: 0 +Line 1507: 1 +Line 1508: 0 +Line 1509: 1 +Line 1510: 0 +Line 1511: 1 +Line 1512: 0 +Line 1513: 0 +Line 1514: 1 +Line 1515: 0 +Line 1516: 1 +Line 1517: 1 +Line 1518: 1 +Line 1519: 0 +Line 1520: 0 +Line 1521: 0 +Line 1522: 0 +Line 1523: 0 +Line 1524: 0 +Line 1525: 0 +Line 1526: 0 +Line 1527: 0 +Line 1528: 0 +Line 1529: 0 +Line 1530: 0 +Line 1531: 0 +Line 1532: 0 +Line 1533: 0 +Line 1534: 0 +Line 1535: 0 +Line 1536: 0 +Line 1537: 0 +Line 1538: 0 +Line 1539: 1 +Line 1540: 0 +Line 1541: 1 +Line 1542: 1 +Line 1543: 0 +Line 1544: 0 +Line 1545: 0 +Line 1546: 1 +Line 1547: 1 +Line 1548: 0 +Line 1549: 1 +Line 1550: 1 +Line 1551: 0 +Line 1552: 0 +Line 1553: 0 +Line 1554: 0 +Line 1555: 0 +Line 1556: 0 +Line 1557: 0 +Line 1558: 0 +Line 1559: 0 +Line 1560: 0 +Line 1561: 0 +Line 1562: 0 +Line 1563: 0 +Line 1564: 0 +Line 1565: 0 +Line 1566: 0 +Line 1567: 0 +Line 1568: 0 +Line 1569: 0 +Line 1570: 0 +Line 1571: 1 +Line 1572: 0 +Line 1573: 1 +Line 1574: 1 +Line 1575: 1 +Line 1576: 0 +Line 1577: 1 +Line 1578: 0 +Line 1579: 0 +Line 1580: 0 +Line 1581: 0 +Line 1582: 1 +Line 1583: 1 +Line 1584: 0 +Line 1585: 0 +Line 1586: 0 +Line 1587: 0 +Line 1588: 0 +Line 1589: 0 +Line 1590: 0 +Line 1591: 0 +Line 1592: 0 +Line 1593: 0 +Line 1594: 0 +Line 1595: 0 +Line 1596: 0 +Line 1597: 0 +Line 1598: 0 +Line 1599: 0 +Line 1600: 0 +Line 1601: 0 +Line 1602: 0 +Line 1603: 1 +Line 1604: 1 +Line 1605: 0 +Line 1606: 0 +Line 1607: 0 +Line 1608: 0 +Line 1609: 1 +Line 1610: 0 +Line 1611: 1 +Line 1612: 0 +Line 1613: 1 +Line 1614: 1 +Line 1615: 0 +Line 1616: 0 +Line 1617: 0 +Line 1618: 0 +Line 1619: 0 +Line 1620: 0 +Line 1621: 0 +Line 1622: 0 +Line 1623: 0 +Line 1624: 0 +Line 1625: 0 +Line 1626: 0 +Line 1627: 0 +Line 1628: 0 +Line 1629: 0 +Line 1630: 0 +Line 1631: 0 +Line 1632: 0 +Line 1633: 0 +Line 1634: 0 +Line 1635: 1 +Line 1636: 1 +Line 1637: 0 +Line 1638: 0 +Line 1639: 1 +Line 1640: 0 +Line 1641: 1 +Line 1642: 1 +Line 1643: 0 +Line 1644: 1 +Line 1645: 1 +Line 1646: 0 +Line 1647: 0 +Line 1648: 0 +Line 1649: 0 +Line 1650: 0 +Line 1651: 0 +Line 1652: 0 +Line 1653: 0 +Line 1654: 0 +Line 1655: 0 +Line 1656: 0 +Line 1657: 0 +Line 1658: 0 +Line 1659: 0 +Line 1660: 0 +Line 1661: 0 +Line 1662: 0 +Line 1663: 0 +Line 1664: 0 +Line 1665: 0 +Line 1666: 0 +Line 1667: 1 +Line 1668: 1 +Line 1669: 0 +Line 1670: 1 +Line 1671: 0 +Line 1672: 1 +Line 1673: 0 +Line 1674: 0 +Line 1675: 0 +Line 1676: 0 +Line 1677: 1 +Line 1678: 1 +Line 1679: 1 +Line 1680: 0 +Line 1681: 0 +Line 1682: 0 +Line 1683: 0 +Line 1684: 0 +Line 1685: 0 +Line 1686: 0 +Line 1687: 0 +Line 1688: 0 +Line 1689: 0 +Line 1690: 0 +Line 1691: 0 +Line 1692: 0 +Line 1693: 0 +Line 1694: 0 +Line 1695: 0 +Line 1696: 0 +Line 1697: 0 +Line 1698: 0 +Line 1699: 1 +Line 1700: 1 +Line 1701: 0 +Line 1702: 1 +Line 1703: 1 +Line 1704: 1 +Line 1705: 0 +Line 1706: 1 +Line 1707: 0 +Line 1708: 0 +Line 1709: 1 +Line 1710: 1 +Line 1711: 0 +Line 1712: 0 +Line 1713: 0 +Line 1714: 0 +Line 1715: 0 +Line 1716: 0 +Line 1717: 0 +Line 1718: 0 +Line 1719: 0 +Line 1720: 0 +Line 1721: 0 +Line 1722: 0 +Line 1723: 0 +Line 1724: 0 +Line 1725: 0 +Line 1726: 0 +Line 1727: 0 +Line 1728: 0 +Line 1729: 0 +Line 1730: 0 +Line 1731: 1 +Line 1732: 1 +Line 1733: 1 +Line 1734: 0 +Line 1735: 0 +Line 1736: 1 +Line 1737: 1 +Line 1738: 0 +Line 1739: 0 +Line 1740: 1 +Line 1741: 0 +Line 1742: 0 +Line 1743: 0 +Line 1744: 0 +Line 1745: 0 +Line 1746: 0 +Line 1747: 0 +Line 1748: 0 +Line 1749: 0 +Line 1750: 0 +Line 1751: 0 +Line 1752: 0 +Line 1753: 0 +Line 1754: 0 +Line 1755: 0 +Line 1756: 0 +Line 1757: 0 +Line 1758: 0 +Line 1759: 0 +Line 1760: 0 +Line 1761: 0 +Line 1762: 0 +Line 1763: 1 +Line 1764: 1 +Line 1765: 1 +Line 1766: 0 +Line 1767: 1 +Line 1768: 1 +Line 1769: 1 +Line 1770: 1 +Line 1771: 0 +Line 1772: 1 +Line 1773: 1 +Line 1774: 0 +Line 1775: 1 +Line 1776: 0 +Line 1777: 0 +Line 1778: 0 +Line 1779: 0 +Line 1780: 0 +Line 1781: 0 +Line 1782: 0 +Line 1783: 0 +Line 1784: 0 +Line 1785: 0 +Line 1786: 0 +Line 1787: 0 +Line 1788: 0 +Line 1789: 0 +Line 1790: 0 +Line 1791: 0 +Line 1792: 0 +Line 1793: 0 +Line 1794: 0 +Line 1795: 1 +Line 1796: 1 +Line 1797: 1 +Line 1798: 1 +Line 1799: 1 +Line 1800: 0 +Line 1801: 0 +Line 1802: 0 +Line 1803: 1 +Line 1804: 0 +Line 1805: 1 +Line 1806: 0 +Line 1807: 0 +Line 1808: 0 +Line 1809: 0 +Line 1810: 0 +Line 1811: 0 +Line 1812: 0 +Line 1813: 0 +Line 1814: 0 +Line 1815: 0 +Line 1816: 0 +Line 1817: 0 +Line 1818: 0 +Line 1819: 0 +Line 1820: 0 +Line 1821: 0 +Line 1822: 0 +Line 1823: 0 +Line 1824: 0 +Line 1825: 0 +Line 1826: 1 +Line 1827: 0 +Line 1828: 0 +Line 1829: 0 +Line 1830: 0 +Line 1831: 0 +Line 1832: 0 +Line 1833: 0 +Line 1834: 1 +Line 1835: 1 +Line 1836: 1 +Line 1837: 1 +Line 1838: 0 +Line 1839: 1 +Line 1840: 0 +Line 1841: 0 +Line 1842: 0 +Line 1843: 0 +Line 1844: 0 +Line 1845: 0 +Line 1846: 0 +Line 1847: 0 +Line 1848: 0 +Line 1849: 0 +Line 1850: 0 +Line 1851: 0 +Line 1852: 0 +Line 1853: 0 +Line 1854: 0 +Line 1855: 0 +Line 1856: 0 +Line 1857: 0 +Line 1858: 1 +Line 1859: 0 +Line 1860: 0 +Line 1861: 0 +Line 1862: 0 +Line 1863: 1 +Line 1864: 0 +Line 1865: 1 +Line 1866: 1 +Line 1867: 0 +Line 1868: 0 +Line 1869: 1 +Line 1870: 1 +Line 1871: 1 +Line 1872: 0 +Line 1873: 0 +Line 1874: 0 +Line 1875: 0 +Line 1876: 0 +Line 1877: 0 +Line 1878: 0 +Line 1879: 0 +Line 1880: 0 +Line 1881: 0 +Line 1882: 0 +Line 1883: 0 +Line 1884: 0 +Line 1885: 0 +Line 1886: 0 +Line 1887: 0 +Line 1888: 0 +Line 1889: 0 +Line 1890: 1 +Line 1891: 0 +Line 1892: 0 +Line 1893: 0 +Line 1894: 1 +Line 1895: 0 +Line 1896: 1 +Line 1897: 0 +Line 1898: 0 +Line 1899: 1 +Line 1900: 0 +Line 1901: 0 +Line 1902: 1 +Line 1903: 0 +Line 1904: 0 +Line 1905: 0 +Line 1906: 0 +Line 1907: 0 +Line 1908: 0 +Line 1909: 0 +Line 1910: 0 +Line 1911: 0 +Line 1912: 0 +Line 1913: 0 +Line 1914: 0 +Line 1915: 0 +Line 1916: 0 +Line 1917: 0 +Line 1918: 0 +Line 1919: 0 +Line 1920: 0 +Line 1921: 0 +Line 1922: 1 +Line 1923: 0 +Line 1924: 0 +Line 1925: 0 +Line 1926: 1 +Line 1927: 1 +Line 1928: 1 +Line 1929: 0 +Line 1930: 1 +Line 1931: 1 +Line 1932: 1 +Line 1933: 1 +Line 1934: 0 +Line 1935: 1 +Line 1936: 0 +Line 1937: 0 +Line 1938: 0 +Line 1939: 0 +Line 1940: 0 +Line 1941: 0 +Line 1942: 0 +Line 1943: 0 +Line 1944: 0 +Line 1945: 0 +Line 1946: 0 +Line 1947: 0 +Line 1948: 0 +Line 1949: 0 +Line 1950: 0 +Line 1951: 0 +Line 1952: 0 +Line 1953: 0 +Line 1954: 1 +Line 1955: 0 +Line 1956: 0 +Line 1957: 1 +Line 1958: 0 +Line 1959: 0 +Line 1960: 1 +Line 1961: 1 +Line 1962: 1 +Line 1963: 0 +Line 1964: 1 +Line 1965: 0 +Line 1966: 0 +Line 1967: 0 +Line 1968: 0 +Line 1969: 0 +Line 1970: 0 +Line 1971: 0 +Line 1972: 0 +Line 1973: 0 +Line 1974: 0 +Line 1975: 0 +Line 1976: 0 +Line 1977: 0 +Line 1978: 0 +Line 1979: 0 +Line 1980: 0 +Line 1981: 0 +Line 1982: 0 +Line 1983: 0 +Line 1984: 0 +Line 1985: 0 +Line 1986: 1 +Line 1987: 0 +Line 1988: 0 +Line 1989: 1 +Line 1990: 1 +Line 1991: 0 +Line 1992: 0 +Line 1993: 0 +Line 1994: 0 +Line 1995: 1 +Line 1996: 0 +Line 1997: 0 +Line 1998: 1 +Line 1999: 0 +Line 2000: 0 +Line 2001: 0 +Line 2002: 0 +Line 2003: 0 +Line 2004: 0 +Line 2005: 0 +Line 2006: 0 +Line 2007: 0 +Line 2008: 0 +Line 2009: 0 +Line 2010: 0 +Line 2011: 0 +Line 2012: 0 +Line 2013: 0 +Line 2014: 0 +Line 2015: 0 +Line 2016: 0 +Line 2017: 0 +Line 2018: 1 +Line 2019: 0 +Line 2020: 0 +Line 2021: 1 +Line 2022: 1 +Line 2023: 1 +Line 2024: 0 +Line 2025: 0 +Line 2026: 1 +Line 2027: 1 +Line 2028: 1 +Line 2029: 0 +Line 2030: 1 +Line 2031: 1 +Line 2032: 0 +Line 2033: 0 +Line 2034: 0 +Line 2035: 0 +Line 2036: 0 +Line 2037: 0 +Line 2038: 0 +Line 2039: 0 +Line 2040: 0 +Line 2041: 0 +Line 2042: 0 +Line 2043: 0 +Line 2044: 0 +Line 2045: 0 +Line 2046: 0 +Line 2047: 0 +Line 2048: 0 +Line 2049: 0 +Line 2050: 1 +Line 2051: 0 +Line 2052: 1 +Line 2053: 0 +Line 2054: 0 +Line 2055: 0 +Line 2056: 0 +Line 2057: 1 +Line 2058: 1 +Line 2059: 0 +Line 2060: 0 +Line 2061: 0 +Line 2062: 1 +Line 2063: 0 +Line 2064: 0 +Line 2065: 0 +Line 2066: 0 +Line 2067: 0 +Line 2068: 0 +Line 2069: 0 +Line 2070: 0 +Line 2071: 0 +Line 2072: 0 +Line 2073: 0 +Line 2074: 0 +Line 2075: 0 +Line 2076: 0 +Line 2077: 0 +Line 2078: 0 +Line 2079: 0 +Line 2080: 0 +Line 2081: 0 +Line 2082: 1 +Line 2083: 0 +Line 2084: 1 +Line 2085: 0 +Line 2086: 0 +Line 2087: 1 +Line 2088: 1 +Line 2089: 0 +Line 2090: 0 +Line 2091: 0 +Line 2092: 0 +Line 2093: 1 +Line 2094: 1 +Line 2095: 1 +Line 2096: 0 +Line 2097: 0 +Line 2098: 0 +Line 2099: 0 +Line 2100: 0 +Line 2101: 0 +Line 2102: 0 +Line 2103: 0 +Line 2104: 0 +Line 2105: 0 +Line 2106: 0 +Line 2107: 0 +Line 2108: 0 +Line 2109: 0 +Line 2110: 0 +Line 2111: 0 +Line 2112: 0 +Line 2113: 0 +Line 2114: 1 +Line 2115: 0 +Line 2116: 1 +Line 2117: 0 +Line 2118: 1 +Line 2119: 0 +Line 2120: 1 +Line 2121: 0 +Line 2122: 1 +Line 2123: 0 +Line 2124: 1 +Line 2125: 0 +Line 2126: 0 +Line 2127: 1 +Line 2128: 0 +Line 2129: 0 +Line 2130: 0 +Line 2131: 0 +Line 2132: 0 +Line 2133: 0 +Line 2134: 0 +Line 2135: 0 +Line 2136: 0 +Line 2137: 0 +Line 2138: 0 +Line 2139: 0 +Line 2140: 0 +Line 2141: 0 +Line 2142: 0 +Line 2143: 0 +Line 2144: 0 +Line 2145: 0 +Line 2146: 1 +Line 2147: 0 +Line 2148: 1 +Line 2149: 0 +Line 2150: 1 +Line 2151: 1 +Line 2152: 1 +Line 2153: 1 +Line 2154: 0 +Line 2155: 0 +Line 2156: 1 +Line 2157: 0 +Line 2158: 0 +Line 2159: 0 +Line 2160: 0 +Line 2161: 0 +Line 2162: 0 +Line 2163: 0 +Line 2164: 0 +Line 2165: 0 +Line 2166: 0 +Line 2167: 0 +Line 2168: 0 +Line 2169: 0 +Line 2170: 0 +Line 2171: 0 +Line 2172: 0 +Line 2173: 0 +Line 2174: 0 +Line 2175: 0 +Line 2176: 0 +Line 2177: 0 +Line 2178: 1 +Line 2179: 0 +Line 2180: 1 +Line 2181: 1 +Line 2182: 0 +Line 2183: 0 +Line 2184: 1 +Line 2185: 1 +Line 2186: 1 +Line 2187: 0 +Line 2188: 0 +Line 2189: 0 +Line 2190: 1 +Line 2191: 1 +Line 2192: 0 +Line 2193: 0 +Line 2194: 0 +Line 2195: 0 +Line 2196: 0 +Line 2197: 0 +Line 2198: 0 +Line 2199: 0 +Line 2200: 0 +Line 2201: 0 +Line 2202: 0 +Line 2203: 0 +Line 2204: 0 +Line 2205: 0 +Line 2206: 0 +Line 2207: 0 +Line 2208: 0 +Line 2209: 0 +Line 2210: 1 +Line 2211: 0 +Line 2212: 1 +Line 2213: 1 +Line 2214: 0 +Line 2215: 1 +Line 2216: 1 +Line 2217: 1 +Line 2218: 1 +Line 2219: 1 +Line 2220: 1 +Line 2221: 0 +Line 2222: 0 +Line 2223: 1 +Line 2224: 0 +Line 2225: 0 +Line 2226: 0 +Line 2227: 0 +Line 2228: 0 +Line 2229: 0 +Line 2230: 0 +Line 2231: 0 +Line 2232: 0 +Line 2233: 0 +Line 2234: 0 +Line 2235: 0 +Line 2236: 0 +Line 2237: 0 +Line 2238: 0 +Line 2239: 0 +Line 2240: 0 +Line 2241: 0 +Line 2242: 1 +Line 2243: 0 +Line 2244: 1 +Line 2245: 1 +Line 2246: 1 +Line 2247: 1 +Line 2248: 0 +Line 2249: 0 +Line 2250: 0 +Line 2251: 0 +Line 2252: 1 +Line 2253: 1 +Line 2254: 0 +Line 2255: 0 +Line 2256: 0 +Line 2257: 0 +Line 2258: 0 +Line 2259: 0 +Line 2260: 0 +Line 2261: 0 +Line 2262: 0 +Line 2263: 0 +Line 2264: 0 +Line 2265: 0 +Line 2266: 0 +Line 2267: 0 +Line 2268: 0 +Line 2269: 0 +Line 2270: 0 +Line 2271: 0 +Line 2272: 0 +Line 2273: 0 +Line 2274: 1 +Line 2275: 1 +Line 2276: 0 +Line 2277: 0 +Line 2278: 0 +Line 2279: 0 +Line 2280: 0 +Line 2281: 0 +Line 2282: 0 +Line 2283: 1 +Line 2284: 1 +Line 2285: 0 +Line 2286: 0 +Line 2287: 1 +Line 2288: 0 +Line 2289: 0 +Line 2290: 0 +Line 2291: 0 +Line 2292: 0 +Line 2293: 0 +Line 2294: 0 +Line 2295: 0 +Line 2296: 0 +Line 2297: 0 +Line 2298: 0 +Line 2299: 0 +Line 2300: 0 +Line 2301: 0 +Line 2302: 0 +Line 2303: 0 +Line 2304: 0 +Line 2305: 0 +Line 2306: 1 +Line 2307: 1 +Line 2308: 0 +Line 2309: 0 +Line 2310: 0 +Line 2311: 1 +Line 2312: 0 +Line 2313: 0 +Line 2314: 1 +Line 2315: 0 +Line 2316: 0 +Line 2317: 0 +Line 2318: 0 +Line 2319: 1 +Line 2320: 0 +Line 2321: 0 +Line 2322: 0 +Line 2323: 0 +Line 2324: 0 +Line 2325: 0 +Line 2326: 0 +Line 2327: 0 +Line 2328: 0 +Line 2329: 0 +Line 2330: 0 +Line 2331: 0 +Line 2332: 0 +Line 2333: 0 +Line 2334: 0 +Line 2335: 0 +Line 2336: 0 +Line 2337: 0 +Line 2338: 1 +Line 2339: 1 +Line 2340: 0 +Line 2341: 0 +Line 2342: 1 +Line 2343: 0 +Line 2344: 0 +Line 2345: 0 +Line 2346: 1 +Line 2347: 0 +Line 2348: 0 +Line 2349: 1 +Line 2350: 0 +Line 2351: 0 +Line 2352: 0 +Line 2353: 0 +Line 2354: 0 +Line 2355: 0 +Line 2356: 0 +Line 2357: 0 +Line 2358: 0 +Line 2359: 0 +Line 2360: 0 +Line 2361: 0 +Line 2362: 0 +Line 2363: 0 +Line 2364: 0 +Line 2365: 0 +Line 2366: 0 +Line 2367: 0 +Line 2368: 0 +Line 2369: 0 +Line 2370: 1 +Line 2371: 1 +Line 2372: 0 +Line 2373: 0 +Line 2374: 1 +Line 2375: 1 +Line 2376: 0 +Line 2377: 0 +Line 2378: 1 +Line 2379: 0 +Line 2380: 0 +Line 2381: 0 +Line 2382: 0 +Line 2383: 0 +Line 2384: 0 +Line 2385: 0 +Line 2386: 0 +Line 2387: 0 +Line 2388: 0 +Line 2389: 0 +Line 2390: 0 +Line 2391: 0 +Line 2392: 0 +Line 2393: 0 +Line 2394: 0 +Line 2395: 0 +Line 2396: 0 +Line 2397: 0 +Line 2398: 0 +Line 2399: 0 +Line 2400: 0 +Line 2401: 0 +Line 2402: 1 +Line 2403: 1 +Line 2404: 0 +Line 2405: 1 +Line 2406: 0 +Line 2407: 0 +Line 2408: 0 +Line 2409: 0 +Line 2410: 0 +Line 2411: 1 +Line 2412: 0 +Line 2413: 1 +Line 2414: 1 +Line 2415: 0 +Line 2416: 0 +Line 2417: 0 +Line 2418: 0 +Line 2419: 0 +Line 2420: 0 +Line 2421: 0 +Line 2422: 0 +Line 2423: 0 +Line 2424: 0 +Line 2425: 0 +Line 2426: 0 +Line 2427: 0 +Line 2428: 0 +Line 2429: 0 +Line 2430: 0 +Line 2431: 0 +Line 2432: 0 +Line 2433: 0 +Line 2434: 1 +Line 2435: 1 +Line 2436: 0 +Line 2437: 1 +Line 2438: 0 +Line 2439: 1 +Line 2440: 0 +Line 2441: 0 +Line 2442: 0 +Line 2443: 0 +Line 2444: 0 +Line 2445: 1 +Line 2446: 1 +Line 2447: 0 +Line 2448: 0 +Line 2449: 0 +Line 2450: 0 +Line 2451: 0 +Line 2452: 0 +Line 2453: 0 +Line 2454: 0 +Line 2455: 0 +Line 2456: 0 +Line 2457: 0 +Line 2458: 0 +Line 2459: 0 +Line 2460: 0 +Line 2461: 0 +Line 2462: 0 +Line 2463: 0 +Line 2464: 0 +Line 2465: 0 +Line 2466: 1 +Line 2467: 1 +Line 2468: 0 +Line 2469: 1 +Line 2470: 0 +Line 2471: 1 +Line 2472: 1 +Line 2473: 1 +Line 2474: 1 +Line 2475: 0 +Line 2476: 1 +Line 2477: 1 +Line 2478: 1 +Line 2479: 0 +Line 2480: 0 +Line 2481: 0 +Line 2482: 0 +Line 2483: 0 +Line 2484: 0 +Line 2485: 0 +Line 2486: 0 +Line 2487: 0 +Line 2488: 0 +Line 2489: 0 +Line 2490: 0 +Line 2491: 0 +Line 2492: 0 +Line 2493: 0 +Line 2494: 0 +Line 2495: 0 +Line 2496: 0 +Line 2497: 0 +Line 2498: 1 +Line 2499: 1 +Line 2500: 0 +Line 2501: 1 +Line 2502: 1 +Line 2503: 0 +Line 2504: 1 +Line 2505: 1 +Line 2506: 0 +Line 2507: 1 +Line 2508: 0 +Line 2509: 0 +Line 2510: 0 +Line 2511: 0 +Line 2512: 0 +Line 2513: 0 +Line 2514: 0 +Line 2515: 0 +Line 2516: 0 +Line 2517: 0 +Line 2518: 0 +Line 2519: 0 +Line 2520: 0 +Line 2521: 0 +Line 2522: 0 +Line 2523: 0 +Line 2524: 0 +Line 2525: 0 +Line 2526: 0 +Line 2527: 0 +Line 2528: 0 +Line 2529: 0 +Line 2530: 1 +Line 2531: 1 +Line 2532: 0 +Line 2533: 1 +Line 2534: 1 +Line 2535: 1 +Line 2536: 1 +Line 2537: 0 +Line 2538: 1 +Line 2539: 0 +Line 2540: 1 +Line 2541: 0 +Line 2542: 1 +Line 2543: 1 +Line 2544: 0 +Line 2545: 0 +Line 2546: 0 +Line 2547: 0 +Line 2548: 0 +Line 2549: 0 +Line 2550: 0 +Line 2551: 0 +Line 2552: 0 +Line 2553: 0 +Line 2554: 0 +Line 2555: 0 +Line 2556: 0 +Line 2557: 0 +Line 2558: 0 +Line 2559: 0 +Line 2560: 0 +Line 2561: 0 +Line 2562: 1 +Line 2563: 1 +Line 2564: 1 +Line 2565: 0 +Line 2566: 0 +Line 2567: 0 +Line 2568: 0 +Line 2569: 1 +Line 2570: 1 +Line 2571: 1 +Line 2572: 1 +Line 2573: 1 +Line 2574: 1 +Line 2575: 0 +Line 2576: 0 +Line 2577: 0 +Line 2578: 0 +Line 2579: 0 +Line 2580: 0 +Line 2581: 0 +Line 2582: 0 +Line 2583: 0 +Line 2584: 0 +Line 2585: 0 +Line 2586: 0 +Line 2587: 0 +Line 2588: 0 +Line 2589: 0 +Line 2590: 0 +Line 2591: 0 +Line 2592: 0 +Line 2593: 0 +Line 2594: 1 +Line 2595: 1 +Line 2596: 1 +Line 2597: 0 +Line 2598: 0 +Line 2599: 1 +Line 2600: 0 +Line 2601: 1 +Line 2602: 0 +Line 2603: 0 +Line 2604: 1 +Line 2605: 0 +Line 2606: 1 +Line 2607: 0 +Line 2608: 0 +Line 2609: 0 +Line 2610: 0 +Line 2611: 0 +Line 2612: 0 +Line 2613: 0 +Line 2614: 0 +Line 2615: 0 +Line 2616: 0 +Line 2617: 0 +Line 2618: 0 +Line 2619: 0 +Line 2620: 0 +Line 2621: 0 +Line 2622: 0 +Line 2623: 0 +Line 2624: 0 +Line 2625: 0 +Line 2626: 1 +Line 2627: 1 +Line 2628: 1 +Line 2629: 0 +Line 2630: 1 +Line 2631: 0 +Line 2632: 0 +Line 2633: 0 +Line 2634: 0 +Line 2635: 0 +Line 2636: 1 +Line 2637: 1 +Line 2638: 1 +Line 2639: 1 +Line 2640: 0 +Line 2641: 0 +Line 2642: 0 +Line 2643: 0 +Line 2644: 0 +Line 2645: 0 +Line 2646: 0 +Line 2647: 0 +Line 2648: 0 +Line 2649: 0 +Line 2650: 0 +Line 2651: 0 +Line 2652: 0 +Line 2653: 0 +Line 2654: 0 +Line 2655: 0 +Line 2656: 0 +Line 2657: 0 +Line 2658: 1 +Line 2659: 1 +Line 2660: 1 +Line 2661: 0 +Line 2662: 1 +Line 2663: 0 +Line 2664: 1 +Line 2665: 1 +Line 2666: 0 +Line 2667: 0 +Line 2668: 1 +Line 2669: 1 +Line 2670: 0 +Line 2671: 0 +Line 2672: 0 +Line 2673: 0 +Line 2674: 0 +Line 2675: 0 +Line 2676: 0 +Line 2677: 0 +Line 2678: 0 +Line 2679: 0 +Line 2680: 0 +Line 2681: 0 +Line 2682: 0 +Line 2683: 0 +Line 2684: 0 +Line 2685: 0 +Line 2686: 0 +Line 2687: 0 +Line 2688: 0 +Line 2689: 0 +Line 2690: 1 +Line 2691: 1 +Line 2692: 1 +Line 2693: 0 +Line 2694: 1 +Line 2695: 1 +Line 2696: 1 +Line 2697: 0 +Line 2698: 0 +Line 2699: 0 +Line 2700: 0 +Line 2701: 0 +Line 2702: 0 +Line 2703: 1 +Line 2704: 0 +Line 2705: 0 +Line 2706: 0 +Line 2707: 0 +Line 2708: 0 +Line 2709: 0 +Line 2710: 0 +Line 2711: 0 +Line 2712: 0 +Line 2713: 0 +Line 2714: 0 +Line 2715: 0 +Line 2716: 0 +Line 2717: 0 +Line 2718: 0 +Line 2719: 0 +Line 2720: 0 +Line 2721: 0 +Line 2722: 1 +Line 2723: 1 +Line 2724: 1 +Line 2725: 1 +Line 2726: 0 +Line 2727: 0 +Line 2728: 0 +Line 2729: 0 +Line 2730: 1 +Line 2731: 0 +Line 2732: 1 +Line 2733: 1 +Line 2734: 1 +Line 2735: 1 +Line 2736: 0 +Line 2737: 0 +Line 2738: 0 +Line 2739: 0 +Line 2740: 0 +Line 2741: 0 +Line 2742: 0 +Line 2743: 0 +Line 2744: 0 +Line 2745: 0 +Line 2746: 0 +Line 2747: 0 +Line 2748: 0 +Line 2749: 0 +Line 2750: 0 +Line 2751: 0 +Line 2752: 0 +Line 2753: 0 +Line 2754: 1 +Line 2755: 1 +Line 2756: 1 +Line 2757: 1 +Line 2758: 0 +Line 2759: 0 +Line 2760: 1 +Line 2761: 1 +Line 2762: 0 +Line 2763: 1 +Line 2764: 0 +Line 2765: 1 +Line 2766: 1 +Line 2767: 0 +Line 2768: 0 +Line 2769: 0 +Line 2770: 0 +Line 2771: 0 +Line 2772: 0 +Line 2773: 0 +Line 2774: 0 +Line 2775: 0 +Line 2776: 0 +Line 2777: 0 +Line 2778: 0 +Line 2779: 0 +Line 2780: 0 +Line 2781: 0 +Line 2782: 0 +Line 2783: 0 +Line 2784: 0 +Line 2785: 0 +Line 2786: 1 +Line 2787: 1 +Line 2788: 1 +Line 2789: 1 +Line 2790: 0 +Line 2791: 1 +Line 2792: 0 +Line 2793: 1 +Line 2794: 1 +Line 2795: 1 +Line 2796: 0 +Line 2797: 1 +Line 2798: 0 +Line 2799: 1 +Line 2800: 0 +Line 2801: 0 +Line 2802: 0 +Line 2803: 0 +Line 2804: 0 +Line 2805: 0 +Line 2806: 0 +Line 2807: 0 +Line 2808: 0 +Line 2809: 0 +Line 2810: 0 +Line 2811: 0 +Line 2812: 0 +Line 2813: 0 +Line 2814: 0 +Line 2815: 0 +Line 2816: 0 +Line 2817: 0 +Line 2818: 1 +Line 2819: 1 +Line 2820: 1 +Line 2821: 1 +Line 2822: 1 +Line 2823: 0 +Line 2824: 0 +Line 2825: 0 +Line 2826: 0 +Line 2827: 0 +Line 2828: 1 +Line 2829: 1 +Line 2830: 0 +Line 2831: 0 +Line 2832: 0 +Line 2833: 0 +Line 2834: 0 +Line 2835: 0 +Line 2836: 0 +Line 2837: 0 +Line 2838: 0 +Line 2839: 0 +Line 2840: 0 +Line 2841: 0 +Line 2842: 0 +Line 2843: 0 +Line 2844: 0 +Line 2845: 0 +Line 2846: 0 +Line 2847: 0 +Line 2848: 0 +Line 2849: 0 +Line 2850: 1 +Line 2851: 1 +Line 2852: 1 +Line 2853: 1 +Line 2854: 1 +Line 2855: 0 +Line 2856: 1 +Line 2857: 0 +Line 2858: 0 +Line 2859: 1 +Line 2860: 1 +Line 2861: 1 +Line 2862: 0 +Line 2863: 0 +Line 2864: 0 +Line 2865: 0 +Line 2866: 0 +Line 2867: 0 +Line 2868: 0 +Line 2869: 0 +Line 2870: 0 +Line 2871: 0 +Line 2872: 0 +Line 2873: 0 +Line 2874: 0 +Line 2875: 0 +Line 2876: 0 +Line 2877: 0 +Line 2878: 0 +Line 2879: 0 +Line 2880: 0 +Line 2881: 0 +Line 2882: 1 +Line 2883: 1 +Line 2884: 1 +Line 2885: 1 +Line 2886: 1 +Line 2887: 1 +Line 2888: 0 +Line 2889: 0 +Line 2890: 1 +Line 2891: 0 +Line 2892: 0 +Line 2893: 1 +Line 2894: 0 +Line 2895: 1 +Line 2896: 0 +Line 2897: 0 +Line 2898: 0 +Line 2899: 0 +Line 2900: 0 +Line 2901: 0 +Line 2902: 0 +Line 2903: 0 +Line 2904: 0 +Line 2905: 0 +Line 2906: 0 +Line 2907: 0 +Line 2908: 0 +Line 2909: 0 +Line 2910: 0 +Line 2911: 0 +Line 2912: 0 +Line 2913: 0 +Line 2914: 1 +Line 2915: 1 +Line 2916: 1 +Line 2917: 1 +Line 2918: 1 +Line 2919: 1 +Line 2920: 1 +Line 2921: 0 +Line 2922: 1 +Line 2923: 0 +Line 2924: 0 +Line 2925: 1 +Line 2926: 1 +Line 2927: 1 +Line 2928: 0 +Line 2929: 0 +Line 2930: 0 +Line 2931: 0 +Line 2932: 0 +Line 2933: 0 +Line 2934: 0 +Line 2935: 0 +Line 2936: 0 +Line 2937: 0 +Line 2938: 0 +Line 2939: 0 +Line 2940: 0 +Line 2941: 0 +Line 2942: 0 +Line 2943: 0 +Line 2944: 0 +Line 2945: 1 +Line 2946: 0 +Line 2947: 0 +Line 2948: 0 +Line 2949: 0 +Line 2950: 0 +Line 2951: 0 +Line 2952: 0 +Line 2953: 0 +Line 2954: 1 +Line 2955: 0 +Line 2956: 0 +Line 2957: 0 +Line 2958: 1 +Line 2959: 0 +Line 2960: 0 +Line 2961: 0 +Line 2962: 0 +Line 2963: 0 +Line 2964: 0 +Line 2965: 0 +Line 2966: 0 +Line 2967: 0 +Line 2968: 0 +Line 2969: 0 +Line 2970: 0 +Line 2971: 0 +Line 2972: 0 +Line 2973: 0 +Line 2974: 0 +Line 2975: 0 +Line 2976: 0 +Line 2977: 1 +Line 2978: 0 +Line 2979: 0 +Line 2980: 0 +Line 2981: 0 +Line 2982: 0 +Line 2983: 0 +Line 2984: 1 +Line 2985: 0 +Line 2986: 0 +Line 2987: 1 +Line 2988: 0 +Line 2989: 1 +Line 2990: 1 +Line 2991: 1 +Line 2992: 0 +Line 2993: 0 +Line 2994: 0 +Line 2995: 0 +Line 2996: 0 +Line 2997: 0 +Line 2998: 0 +Line 2999: 0 +Line 3000: 0 +Line 3001: 0 +Line 3002: 0 +Line 3003: 0 +Line 3004: 0 +Line 3005: 0 +Line 3006: 0 +Line 3007: 0 +Line 3008: 0 +Line 3009: 1 +Line 3010: 0 +Line 3011: 0 +Line 3012: 0 +Line 3013: 0 +Line 3014: 0 +Line 3015: 1 +Line 3016: 0 +Line 3017: 0 +Line 3018: 0 +Line 3019: 0 +Line 3020: 0 +Line 3021: 1 +Line 3022: 0 +Line 3023: 0 +Line 3024: 0 +Line 3025: 0 +Line 3026: 0 +Line 3027: 0 +Line 3028: 0 +Line 3029: 0 +Line 3030: 0 +Line 3031: 0 +Line 3032: 0 +Line 3033: 0 +Line 3034: 0 +Line 3035: 0 +Line 3036: 0 +Line 3037: 0 +Line 3038: 0 +Line 3039: 0 +Line 3040: 0 +Line 3041: 1 +Line 3042: 0 +Line 3043: 0 +Line 3044: 0 +Line 3045: 0 +Line 3046: 0 +Line 3047: 1 +Line 3048: 0 +Line 3049: 1 +Line 3050: 1 +Line 3051: 0 +Line 3052: 1 +Line 3053: 1 +Line 3054: 0 +Line 3055: 0 +Line 3056: 0 +Line 3057: 0 +Line 3058: 0 +Line 3059: 0 +Line 3060: 0 +Line 3061: 0 +Line 3062: 0 +Line 3063: 0 +Line 3064: 0 +Line 3065: 0 +Line 3066: 0 +Line 3067: 0 +Line 3068: 0 +Line 3069: 0 +Line 3070: 0 +Line 3071: 0 +Line 3072: 0 +Line 3073: 1 +Line 3074: 0 +Line 3075: 0 +Line 3076: 0 +Line 3077: 0 +Line 3078: 0 +Line 3079: 1 +Line 3080: 0 +Line 3081: 1 +Line 3082: 1 +Line 3083: 0 +Line 3084: 1 +Line 3085: 1 +Line 3086: 0 +Line 3087: 0 +Line 3088: 0 +Line 3089: 0 +Line 3090: 0 +Line 3091: 0 +Line 3092: 0 +Line 3093: 0 +Line 3094: 0 +Line 3095: 0 +Line 3096: 0 +Line 3097: 0 +Line 3098: 0 +Line 3099: 0 +Line 3100: 0 +Line 3101: 0 +Line 3102: 0 +Line 3103: 0 +Line 3104: 0 +Line 3105: 1 +Line 3106: 0 +Line 3107: 0 +Line 3108: 0 +Line 3109: 0 +Line 3110: 0 +Line 3111: 1 +Line 3112: 0 +Line 3113: 0 +Line 3114: 0 +Line 3115: 0 +Line 3116: 0 +Line 3117: 1 +Line 3118: 0 +Line 3119: 0 +Line 3120: 0 +Line 3121: 0 +Line 3122: 0 +Line 3123: 0 +Line 3124: 0 +Line 3125: 0 +Line 3126: 0 +Line 3127: 0 +Line 3128: 0 +Line 3129: 0 +Line 3130: 0 +Line 3131: 0 +Line 3132: 0 +Line 3133: 0 +Line 3134: 0 +Line 3135: 0 +Line 3136: 0 +Line 3137: 1 +Line 3138: 0 +Line 3139: 0 +Line 3140: 0 +Line 3141: 0 +Line 3142: 0 +Line 3143: 0 +Line 3144: 1 +Line 3145: 0 +Line 3146: 0 +Line 3147: 1 +Line 3148: 0 +Line 3149: 1 +Line 3150: 1 +Line 3151: 1 +Line 3152: 0 +Line 3153: 0 +Line 3154: 0 +Line 3155: 0 +Line 3156: 0 +Line 3157: 0 +Line 3158: 0 +Line 3159: 0 +Line 3160: 0 +Line 3161: 0 +Line 3162: 0 +Line 3163: 0 +Line 3164: 0 +Line 3165: 0 +Line 3166: 0 +Line 3167: 0 +Line 3168: 0 +Line 3169: 1 +Line 3170: 0 +Line 3171: 0 +Line 3172: 0 +Line 3173: 0 +Line 3174: 0 +Line 3175: 0 +Line 3176: 0 +Line 3177: 0 +Line 3178: 1 +Line 3179: 0 +Line 3180: 0 +Line 3181: 0 +Line 3182: 1 +Line 3183: 0 +Line 3184: 0 +Line 3185: 0 +Line 3186: 0 +Line 3187: 0 +Line 3188: 0 +Line 3189: 0 +Line 3190: 0 +Line 3191: 0 +Line 3192: 0 +Line 3193: 0 +Line 3194: 0 +Line 3195: 0 +Line 3196: 0 +Line 3197: 0 +Line 3198: 0 +Line 3199: 0 +Line 3200: 0 +Line 3201: 0 +Line 3202: 1 +Line 3203: 1 +Line 3204: 1 +Line 3205: 1 +Line 3206: 1 +Line 3207: 1 +Line 3208: 1 +Line 3209: 0 +Line 3210: 1 +Line 3211: 0 +Line 3212: 0 +Line 3213: 1 +Line 3214: 1 +Line 3215: 1 +Line 3216: 0 +Line 3217: 0 +Line 3218: 0 +Line 3219: 0 +Line 3220: 0 +Line 3221: 0 +Line 3222: 0 +Line 3223: 0 +Line 3224: 0 +Line 3225: 0 +Line 3226: 0 +Line 3227: 0 +Line 3228: 0 +Line 3229: 0 +Line 3230: 0 +Line 3231: 0 +Line 3232: 0 +Line 3233: 0 +Line 3234: 1 +Line 3235: 1 +Line 3236: 1 +Line 3237: 1 +Line 3238: 1 +Line 3239: 1 +Line 3240: 0 +Line 3241: 0 +Line 3242: 1 +Line 3243: 0 +Line 3244: 0 +Line 3245: 1 +Line 3246: 0 +Line 3247: 1 +Line 3248: 0 +Line 3249: 0 +Line 3250: 0 +Line 3251: 0 +Line 3252: 0 +Line 3253: 0 +Line 3254: 0 +Line 3255: 0 +Line 3256: 0 +Line 3257: 0 +Line 3258: 0 +Line 3259: 0 +Line 3260: 0 +Line 3261: 0 +Line 3262: 0 +Line 3263: 0 +Line 3264: 0 +Line 3265: 0 +Line 3266: 1 +Line 3267: 1 +Line 3268: 1 +Line 3269: 1 +Line 3270: 1 +Line 3271: 0 +Line 3272: 1 +Line 3273: 0 +Line 3274: 0 +Line 3275: 1 +Line 3276: 1 +Line 3277: 1 +Line 3278: 0 +Line 3279: 0 +Line 3280: 0 +Line 3281: 0 +Line 3282: 0 +Line 3283: 0 +Line 3284: 0 +Line 3285: 0 +Line 3286: 0 +Line 3287: 0 +Line 3288: 0 +Line 3289: 0 +Line 3290: 0 +Line 3291: 0 +Line 3292: 0 +Line 3293: 0 +Line 3294: 0 +Line 3295: 0 +Line 3296: 0 +Line 3297: 0 +Line 3298: 1 +Line 3299: 1 +Line 3300: 1 +Line 3301: 1 +Line 3302: 1 +Line 3303: 0 +Line 3304: 0 +Line 3305: 0 +Line 3306: 0 +Line 3307: 0 +Line 3308: 1 +Line 3309: 1 +Line 3310: 0 +Line 3311: 0 +Line 3312: 0 +Line 3313: 0 +Line 3314: 0 +Line 3315: 0 +Line 3316: 0 +Line 3317: 0 +Line 3318: 0 +Line 3319: 0 +Line 3320: 0 +Line 3321: 0 +Line 3322: 0 +Line 3323: 0 +Line 3324: 0 +Line 3325: 0 +Line 3326: 0 +Line 3327: 0 +Line 3328: 0 +Line 3329: 0 +Line 3330: 1 +Line 3331: 1 +Line 3332: 1 +Line 3333: 1 +Line 3334: 0 +Line 3335: 1 +Line 3336: 0 +Line 3337: 1 +Line 3338: 1 +Line 3339: 1 +Line 3340: 0 +Line 3341: 1 +Line 3342: 0 +Line 3343: 1 +Line 3344: 0 +Line 3345: 0 +Line 3346: 0 +Line 3347: 0 +Line 3348: 0 +Line 3349: 0 +Line 3350: 0 +Line 3351: 0 +Line 3352: 0 +Line 3353: 0 +Line 3354: 0 +Line 3355: 0 +Line 3356: 0 +Line 3357: 0 +Line 3358: 0 +Line 3359: 0 +Line 3360: 0 +Line 3361: 0 +Line 3362: 1 +Line 3363: 1 +Line 3364: 1 +Line 3365: 1 +Line 3366: 0 +Line 3367: 0 +Line 3368: 1 +Line 3369: 1 +Line 3370: 0 +Line 3371: 1 +Line 3372: 0 +Line 3373: 1 +Line 3374: 1 +Line 3375: 0 +Line 3376: 0 +Line 3377: 0 +Line 3378: 0 +Line 3379: 0 +Line 3380: 0 +Line 3381: 0 +Line 3382: 0 +Line 3383: 0 +Line 3384: 0 +Line 3385: 0 +Line 3386: 0 +Line 3387: 0 +Line 3388: 0 +Line 3389: 0 +Line 3390: 0 +Line 3391: 0 +Line 3392: 0 +Line 3393: 0 +Line 3394: 1 +Line 3395: 1 +Line 3396: 1 +Line 3397: 1 +Line 3398: 0 +Line 3399: 0 +Line 3400: 0 +Line 3401: 0 +Line 3402: 1 +Line 3403: 0 +Line 3404: 1 +Line 3405: 1 +Line 3406: 1 +Line 3407: 1 +Line 3408: 0 +Line 3409: 0 +Line 3410: 0 +Line 3411: 0 +Line 3412: 0 +Line 3413: 0 +Line 3414: 0 +Line 3415: 0 +Line 3416: 0 +Line 3417: 0 +Line 3418: 0 +Line 3419: 0 +Line 3420: 0 +Line 3421: 0 +Line 3422: 0 +Line 3423: 0 +Line 3424: 0 +Line 3425: 0 +Line 3426: 1 +Line 3427: 1 +Line 3428: 1 +Line 3429: 0 +Line 3430: 1 +Line 3431: 1 +Line 3432: 1 +Line 3433: 0 +Line 3434: 0 +Line 3435: 0 +Line 3436: 0 +Line 3437: 0 +Line 3438: 0 +Line 3439: 1 +Line 3440: 0 +Line 3441: 0 +Line 3442: 0 +Line 3443: 0 +Line 3444: 0 +Line 3445: 0 +Line 3446: 0 +Line 3447: 0 +Line 3448: 0 +Line 3449: 0 +Line 3450: 0 +Line 3451: 0 +Line 3452: 0 +Line 3453: 0 +Line 3454: 0 +Line 3455: 0 +Line 3456: 0 +Line 3457: 0 +Line 3458: 1 +Line 3459: 1 +Line 3460: 1 +Line 3461: 0 +Line 3462: 1 +Line 3463: 0 +Line 3464: 1 +Line 3465: 1 +Line 3466: 0 +Line 3467: 0 +Line 3468: 1 +Line 3469: 1 +Line 3470: 0 +Line 3471: 0 +Line 3472: 0 +Line 3473: 0 +Line 3474: 0 +Line 3475: 0 +Line 3476: 0 +Line 3477: 0 +Line 3478: 0 +Line 3479: 0 +Line 3480: 0 +Line 3481: 0 +Line 3482: 0 +Line 3483: 0 +Line 3484: 0 +Line 3485: 0 +Line 3486: 0 +Line 3487: 0 +Line 3488: 0 +Line 3489: 0 +Line 3490: 1 +Line 3491: 1 +Line 3492: 1 +Line 3493: 0 +Line 3494: 1 +Line 3495: 0 +Line 3496: 0 +Line 3497: 0 +Line 3498: 0 +Line 3499: 0 +Line 3500: 1 +Line 3501: 1 +Line 3502: 1 +Line 3503: 1 +Line 3504: 0 +Line 3505: 0 +Line 3506: 0 +Line 3507: 0 +Line 3508: 0 +Line 3509: 0 +Line 3510: 0 +Line 3511: 0 +Line 3512: 0 +Line 3513: 0 +Line 3514: 0 +Line 3515: 0 +Line 3516: 0 +Line 3517: 0 +Line 3518: 0 +Line 3519: 0 +Line 3520: 0 +Line 3521: 0 +Line 3522: 1 +Line 3523: 1 +Line 3524: 1 +Line 3525: 0 +Line 3526: 0 +Line 3527: 1 +Line 3528: 0 +Line 3529: 1 +Line 3530: 0 +Line 3531: 0 +Line 3532: 1 +Line 3533: 0 +Line 3534: 1 +Line 3535: 0 +Line 3536: 0 +Line 3537: 0 +Line 3538: 0 +Line 3539: 0 +Line 3540: 0 +Line 3541: 0 +Line 3542: 0 +Line 3543: 0 +Line 3544: 0 +Line 3545: 0 +Line 3546: 0 +Line 3547: 0 +Line 3548: 0 +Line 3549: 0 +Line 3550: 0 +Line 3551: 0 +Line 3552: 0 +Line 3553: 0 +Line 3554: 1 +Line 3555: 1 +Line 3556: 1 +Line 3557: 0 +Line 3558: 0 +Line 3559: 0 +Line 3560: 0 +Line 3561: 1 +Line 3562: 1 +Line 3563: 1 +Line 3564: 1 +Line 3565: 1 +Line 3566: 1 +Line 3567: 0 +Line 3568: 0 +Line 3569: 0 +Line 3570: 0 +Line 3571: 0 +Line 3572: 0 +Line 3573: 0 +Line 3574: 0 +Line 3575: 0 +Line 3576: 0 +Line 3577: 0 +Line 3578: 0 +Line 3579: 0 +Line 3580: 0 +Line 3581: 0 +Line 3582: 0 +Line 3583: 0 +Line 3584: 0 +Line 3585: 0 +Line 3586: 1 +Line 3587: 1 +Line 3588: 0 +Line 3589: 1 +Line 3590: 1 +Line 3591: 1 +Line 3592: 1 +Line 3593: 0 +Line 3594: 1 +Line 3595: 0 +Line 3596: 1 +Line 3597: 0 +Line 3598: 1 +Line 3599: 1 +Line 3600: 0 +Line 3601: 0 +Line 3602: 0 +Line 3603: 0 +Line 3604: 0 +Line 3605: 0 +Line 3606: 0 +Line 3607: 0 +Line 3608: 0 +Line 3609: 0 +Line 3610: 0 +Line 3611: 0 +Line 3612: 0 +Line 3613: 0 +Line 3614: 0 +Line 3615: 0 +Line 3616: 0 +Line 3617: 0 +Line 3618: 1 +Line 3619: 1 +Line 3620: 0 +Line 3621: 1 +Line 3622: 1 +Line 3623: 0 +Line 3624: 1 +Line 3625: 1 +Line 3626: 0 +Line 3627: 1 +Line 3628: 0 +Line 3629: 0 +Line 3630: 0 +Line 3631: 0 +Line 3632: 0 +Line 3633: 0 +Line 3634: 0 +Line 3635: 0 +Line 3636: 0 +Line 3637: 0 +Line 3638: 0 +Line 3639: 0 +Line 3640: 0 +Line 3641: 0 +Line 3642: 0 +Line 3643: 0 +Line 3644: 0 +Line 3645: 0 +Line 3646: 0 +Line 3647: 0 +Line 3648: 0 +Line 3649: 0 +Line 3650: 1 +Line 3651: 1 +Line 3652: 0 +Line 3653: 1 +Line 3654: 0 +Line 3655: 1 +Line 3656: 1 +Line 3657: 1 +Line 3658: 1 +Line 3659: 0 +Line 3660: 1 +Line 3661: 1 +Line 3662: 1 +Line 3663: 0 +Line 3664: 0 +Line 3665: 0 +Line 3666: 0 +Line 3667: 0 +Line 3668: 0 +Line 3669: 0 +Line 3670: 0 +Line 3671: 0 +Line 3672: 0 +Line 3673: 0 +Line 3674: 0 +Line 3675: 0 +Line 3676: 0 +Line 3677: 0 +Line 3678: 0 +Line 3679: 0 +Line 3680: 0 +Line 3681: 0 +Line 3682: 1 +Line 3683: 1 +Line 3684: 0 +Line 3685: 1 +Line 3686: 0 +Line 3687: 1 +Line 3688: 0 +Line 3689: 0 +Line 3690: 0 +Line 3691: 0 +Line 3692: 0 +Line 3693: 1 +Line 3694: 1 +Line 3695: 0 +Line 3696: 0 +Line 3697: 0 +Line 3698: 0 +Line 3699: 0 +Line 3700: 0 +Line 3701: 0 +Line 3702: 0 +Line 3703: 0 +Line 3704: 0 +Line 3705: 0 +Line 3706: 0 +Line 3707: 0 +Line 3708: 0 +Line 3709: 0 +Line 3710: 0 +Line 3711: 0 +Line 3712: 0 +Line 3713: 0 +Line 3714: 1 +Line 3715: 1 +Line 3716: 0 +Line 3717: 1 +Line 3718: 0 +Line 3719: 0 +Line 3720: 0 +Line 3721: 0 +Line 3722: 0 +Line 3723: 1 +Line 3724: 0 +Line 3725: 1 +Line 3726: 1 +Line 3727: 0 +Line 3728: 0 +Line 3729: 0 +Line 3730: 0 +Line 3731: 0 +Line 3732: 0 +Line 3733: 0 +Line 3734: 0 +Line 3735: 0 +Line 3736: 0 +Line 3737: 0 +Line 3738: 0 +Line 3739: 0 +Line 3740: 0 +Line 3741: 0 +Line 3742: 0 +Line 3743: 0 +Line 3744: 0 +Line 3745: 0 +Line 3746: 1 +Line 3747: 1 +Line 3748: 0 +Line 3749: 0 +Line 3750: 1 +Line 3751: 1 +Line 3752: 0 +Line 3753: 0 +Line 3754: 1 +Line 3755: 0 +Line 3756: 0 +Line 3757: 0 +Line 3758: 0 +Line 3759: 0 +Line 3760: 0 +Line 3761: 0 +Line 3762: 0 +Line 3763: 0 +Line 3764: 0 +Line 3765: 0 +Line 3766: 0 +Line 3767: 0 +Line 3768: 0 +Line 3769: 0 +Line 3770: 0 +Line 3771: 0 +Line 3772: 0 +Line 3773: 0 +Line 3774: 0 +Line 3775: 0 +Line 3776: 0 +Line 3777: 0 +Line 3778: 1 +Line 3779: 1 +Line 3780: 0 +Line 3781: 0 +Line 3782: 1 +Line 3783: 0 +Line 3784: 0 +Line 3785: 0 +Line 3786: 1 +Line 3787: 0 +Line 3788: 0 +Line 3789: 1 +Line 3790: 0 +Line 3791: 0 +Line 3792: 0 +Line 3793: 0 +Line 3794: 0 +Line 3795: 0 +Line 3796: 0 +Line 3797: 0 +Line 3798: 0 +Line 3799: 0 +Line 3800: 0 +Line 3801: 0 +Line 3802: 0 +Line 3803: 0 +Line 3804: 0 +Line 3805: 0 +Line 3806: 0 +Line 3807: 0 +Line 3808: 0 +Line 3809: 0 +Line 3810: 1 +Line 3811: 1 +Line 3812: 0 +Line 3813: 0 +Line 3814: 0 +Line 3815: 1 +Line 3816: 0 +Line 3817: 0 +Line 3818: 1 +Line 3819: 0 +Line 3820: 0 +Line 3821: 0 +Line 3822: 0 +Line 3823: 1 +Line 3824: 0 +Line 3825: 0 +Line 3826: 0 +Line 3827: 0 +Line 3828: 0 +Line 3829: 0 +Line 3830: 0 +Line 3831: 0 +Line 3832: 0 +Line 3833: 0 +Line 3834: 0 +Line 3835: 0 +Line 3836: 0 +Line 3837: 0 +Line 3838: 0 +Line 3839: 0 +Line 3840: 0 +Line 3841: 0 +Line 3842: 1 +Line 3843: 1 +Line 3844: 0 +Line 3845: 0 +Line 3846: 0 +Line 3847: 0 +Line 3848: 0 +Line 3849: 0 +Line 3850: 0 +Line 3851: 1 +Line 3852: 1 +Line 3853: 0 +Line 3854: 0 +Line 3855: 1 +Line 3856: 0 +Line 3857: 0 +Line 3858: 0 +Line 3859: 0 +Line 3860: 0 +Line 3861: 0 +Line 3862: 0 +Line 3863: 0 +Line 3864: 0 +Line 3865: 0 +Line 3866: 0 +Line 3867: 0 +Line 3868: 0 +Line 3869: 0 +Line 3870: 0 +Line 3871: 0 +Line 3872: 0 +Line 3873: 0 +Line 3874: 1 +Line 3875: 0 +Line 3876: 1 +Line 3877: 1 +Line 3878: 1 +Line 3879: 1 +Line 3880: 0 +Line 3881: 0 +Line 3882: 0 +Line 3883: 0 +Line 3884: 1 +Line 3885: 1 +Line 3886: 0 +Line 3887: 0 +Line 3888: 0 +Line 3889: 0 +Line 3890: 0 +Line 3891: 0 +Line 3892: 0 +Line 3893: 0 +Line 3894: 0 +Line 3895: 0 +Line 3896: 0 +Line 3897: 0 +Line 3898: 0 +Line 3899: 0 +Line 3900: 0 +Line 3901: 0 +Line 3902: 0 +Line 3903: 0 +Line 3904: 0 +Line 3905: 0 +Line 3906: 1 +Line 3907: 0 +Line 3908: 1 +Line 3909: 1 +Line 3910: 0 +Line 3911: 1 +Line 3912: 1 +Line 3913: 1 +Line 3914: 1 +Line 3915: 1 +Line 3916: 1 +Line 3917: 0 +Line 3918: 0 +Line 3919: 1 +Line 3920: 0 +Line 3921: 0 +Line 3922: 0 +Line 3923: 0 +Line 3924: 0 +Line 3925: 0 +Line 3926: 0 +Line 3927: 0 +Line 3928: 0 +Line 3929: 0 +Line 3930: 0 +Line 3931: 0 +Line 3932: 0 +Line 3933: 0 +Line 3934: 0 +Line 3935: 0 +Line 3936: 0 +Line 3937: 0 +Line 3938: 1 +Line 3939: 0 +Line 3940: 1 +Line 3941: 1 +Line 3942: 0 +Line 3943: 0 +Line 3944: 1 +Line 3945: 1 +Line 3946: 1 +Line 3947: 0 +Line 3948: 0 +Line 3949: 0 +Line 3950: 1 +Line 3951: 1 +Line 3952: 0 +Line 3953: 0 +Line 3954: 0 +Line 3955: 0 +Line 3956: 0 +Line 3957: 0 +Line 3958: 0 +Line 3959: 0 +Line 3960: 0 +Line 3961: 0 +Line 3962: 0 +Line 3963: 0 +Line 3964: 0 +Line 3965: 0 +Line 3966: 0 +Line 3967: 0 +Line 3968: 0 +Line 3969: 0 +Line 3970: 1 +Line 3971: 0 +Line 3972: 1 +Line 3973: 0 +Line 3974: 1 +Line 3975: 1 +Line 3976: 1 +Line 3977: 1 +Line 3978: 0 +Line 3979: 0 +Line 3980: 1 +Line 3981: 0 +Line 3982: 0 +Line 3983: 0 +Line 3984: 0 +Line 3985: 0 +Line 3986: 0 +Line 3987: 0 +Line 3988: 0 +Line 3989: 0 +Line 3990: 0 +Line 3991: 0 +Line 3992: 0 +Line 3993: 0 +Line 3994: 0 +Line 3995: 0 +Line 3996: 0 +Line 3997: 0 +Line 3998: 0 +Line 3999: 0 +Line 4000: 0 +Line 4001: 0 +Line 4002: 1 +Line 4003: 0 +Line 4004: 1 +Line 4005: 0 +Line 4006: 1 +Line 4007: 0 +Line 4008: 1 +Line 4009: 0 +Line 4010: 1 +Line 4011: 0 +Line 4012: 1 +Line 4013: 0 +Line 4014: 0 +Line 4015: 1 +Line 4016: 0 +Line 4017: 0 +Line 4018: 0 +Line 4019: 0 +Line 4020: 0 +Line 4021: 0 +Line 4022: 0 +Line 4023: 0 +Line 4024: 0 +Line 4025: 0 +Line 4026: 0 +Line 4027: 0 +Line 4028: 0 +Line 4029: 0 +Line 4030: 0 +Line 4031: 0 +Line 4032: 0 +Line 4033: 0 +Line 4034: 1 +Line 4035: 0 +Line 4036: 1 +Line 4037: 0 +Line 4038: 0 +Line 4039: 1 +Line 4040: 1 +Line 4041: 0 +Line 4042: 0 +Line 4043: 0 +Line 4044: 0 +Line 4045: 1 +Line 4046: 1 +Line 4047: 1 +Line 4048: 0 +Line 4049: 0 +Line 4050: 0 +Line 4051: 0 +Line 4052: 0 +Line 4053: 0 +Line 4054: 0 +Line 4055: 0 +Line 4056: 0 +Line 4057: 0 +Line 4058: 0 +Line 4059: 0 +Line 4060: 0 +Line 4061: 0 +Line 4062: 0 +Line 4063: 0 +Line 4064: 0 +Line 4065: 0 +Line 4066: 1 +Line 4067: 0 +Line 4068: 1 +Line 4069: 0 +Line 4070: 0 +Line 4071: 0 +Line 4072: 0 +Line 4073: 1 +Line 4074: 1 +Line 4075: 0 +Line 4076: 0 +Line 4077: 0 +Line 4078: 1 +Line 4079: 0 +Line 4080: 0 +Line 4081: 0 +Line 4082: 0 +Line 4083: 0 +Line 4084: 0 +Line 4085: 0 +Line 4086: 0 +Line 4087: 0 +Line 4088: 0 +Line 4089: 0 +Line 4090: 0 +Line 4091: 0 +Line 4092: 0 +Line 4093: 0 +Line 4094: 0 +Line 4095: 0 +Line 4096: 0 +Line 4097: 0 +Line 4098: 1 +Line 4099: 0 +Line 4100: 0 +Line 4101: 1 +Line 4102: 1 +Line 4103: 1 +Line 4104: 0 +Line 4105: 0 +Line 4106: 1 +Line 4107: 1 +Line 4108: 1 +Line 4109: 0 +Line 4110: 1 +Line 4111: 1 +Line 4112: 0 +Line 4113: 0 +Line 4114: 0 +Line 4115: 0 +Line 4116: 0 +Line 4117: 0 +Line 4118: 0 +Line 4119: 0 +Line 4120: 0 +Line 4121: 0 +Line 4122: 0 +Line 4123: 0 +Line 4124: 0 +Line 4125: 0 +Line 4126: 0 +Line 4127: 0 +Line 4128: 0 +Line 4129: 0 +Line 4130: 1 +Line 4131: 0 +Line 4132: 0 +Line 4133: 1 +Line 4134: 1 +Line 4135: 0 +Line 4136: 0 +Line 4137: 0 +Line 4138: 0 +Line 4139: 1 +Line 4140: 0 +Line 4141: 0 +Line 4142: 1 +Line 4143: 0 +Line 4144: 0 +Line 4145: 0 +Line 4146: 0 +Line 4147: 0 +Line 4148: 0 +Line 4149: 0 +Line 4150: 0 +Line 4151: 0 +Line 4152: 0 +Line 4153: 0 +Line 4154: 0 +Line 4155: 0 +Line 4156: 0 +Line 4157: 0 +Line 4158: 0 +Line 4159: 0 +Line 4160: 0 +Line 4161: 0 +Line 4162: 1 +Line 4163: 0 +Line 4164: 0 +Line 4165: 1 +Line 4166: 0 +Line 4167: 0 +Line 4168: 1 +Line 4169: 1 +Line 4170: 1 +Line 4171: 0 +Line 4172: 1 +Line 4173: 0 +Line 4174: 0 +Line 4175: 0 +Line 4176: 0 +Line 4177: 0 +Line 4178: 0 +Line 4179: 0 +Line 4180: 0 +Line 4181: 0 +Line 4182: 0 +Line 4183: 0 +Line 4184: 0 +Line 4185: 0 +Line 4186: 0 +Line 4187: 0 +Line 4188: 0 +Line 4189: 0 +Line 4190: 0 +Line 4191: 0 +Line 4192: 0 +Line 4193: 0 +Line 4194: 1 +Line 4195: 0 +Line 4196: 0 +Line 4197: 0 +Line 4198: 1 +Line 4199: 1 +Line 4200: 1 +Line 4201: 0 +Line 4202: 1 +Line 4203: 1 +Line 4204: 1 +Line 4205: 1 +Line 4206: 0 +Line 4207: 1 +Line 4208: 0 +Line 4209: 0 +Line 4210: 0 +Line 4211: 0 +Line 4212: 0 +Line 4213: 0 +Line 4214: 0 +Line 4215: 0 +Line 4216: 0 +Line 4217: 0 +Line 4218: 0 +Line 4219: 0 +Line 4220: 0 +Line 4221: 0 +Line 4222: 0 +Line 4223: 0 +Line 4224: 0 +Line 4225: 0 +Line 4226: 1 +Line 4227: 0 +Line 4228: 0 +Line 4229: 0 +Line 4230: 1 +Line 4231: 0 +Line 4232: 1 +Line 4233: 0 +Line 4234: 0 +Line 4235: 1 +Line 4236: 0 +Line 4237: 0 +Line 4238: 1 +Line 4239: 0 +Line 4240: 0 +Line 4241: 0 +Line 4242: 0 +Line 4243: 0 +Line 4244: 0 +Line 4245: 0 +Line 4246: 0 +Line 4247: 0 +Line 4248: 0 +Line 4249: 0 +Line 4250: 0 +Line 4251: 0 +Line 4252: 0 +Line 4253: 0 +Line 4254: 0 +Line 4255: 0 +Line 4256: 0 +Line 4257: 0 +Line 4258: 1 +Line 4259: 0 +Line 4260: 0 +Line 4261: 0 +Line 4262: 0 +Line 4263: 1 +Line 4264: 0 +Line 4265: 1 +Line 4266: 1 +Line 4267: 0 +Line 4268: 0 +Line 4269: 1 +Line 4270: 1 +Line 4271: 1 +Line 4272: 0 +Line 4273: 0 +Line 4274: 0 +Line 4275: 0 +Line 4276: 0 +Line 4277: 0 +Line 4278: 0 +Line 4279: 0 +Line 4280: 0 +Line 4281: 0 +Line 4282: 0 +Line 4283: 0 +Line 4284: 0 +Line 4285: 0 +Line 4286: 0 +Line 4287: 0 +Line 4288: 0 +Line 4289: 0 +Line 4290: 1 +Line 4291: 0 +Line 4292: 0 +Line 4293: 0 +Line 4294: 0 +Line 4295: 0 +Line 4296: 0 +Line 4297: 0 +Line 4298: 1 +Line 4299: 1 +Line 4300: 1 +Line 4301: 1 +Line 4302: 0 +Line 4303: 1 +Line 4304: 0 +Line 4305: 0 +Line 4306: 0 +Line 4307: 0 +Line 4308: 0 +Line 4309: 0 +Line 4310: 0 +Line 4311: 0 +Line 4312: 0 +Line 4313: 0 +Line 4314: 0 +Line 4315: 0 +Line 4316: 0 +Line 4317: 0 +Line 4318: 0 +Line 4319: 0 +Line 4320: 0 +Line 4321: 0 +Line 4322: 0 +Line 4323: 1 +Line 4324: 1 +Line 4325: 1 +Line 4326: 1 +Line 4327: 1 +Line 4328: 0 +Line 4329: 0 +Line 4330: 0 +Line 4331: 1 +Line 4332: 0 +Line 4333: 1 +Line 4334: 0 +Line 4335: 0 +Line 4336: 0 +Line 4337: 0 +Line 4338: 0 +Line 4339: 0 +Line 4340: 0 +Line 4341: 0 +Line 4342: 0 +Line 4343: 0 +Line 4344: 0 +Line 4345: 0 +Line 4346: 0 +Line 4347: 0 +Line 4348: 0 +Line 4349: 0 +Line 4350: 0 +Line 4351: 0 +Line 4352: 0 +Line 4353: 0 +Line 4354: 0 +Line 4355: 1 +Line 4356: 1 +Line 4357: 1 +Line 4358: 0 +Line 4359: 1 +Line 4360: 1 +Line 4361: 1 +Line 4362: 1 +Line 4363: 0 +Line 4364: 1 +Line 4365: 1 +Line 4366: 0 +Line 4367: 1 +Line 4368: 0 +Line 4369: 0 +Line 4370: 0 +Line 4371: 0 +Line 4372: 0 +Line 4373: 0 +Line 4374: 0 +Line 4375: 0 +Line 4376: 0 +Line 4377: 0 +Line 4378: 0 +Line 4379: 0 +Line 4380: 0 +Line 4381: 0 +Line 4382: 0 +Line 4383: 0 +Line 4384: 0 +Line 4385: 0 +Line 4386: 0 +Line 4387: 1 +Line 4388: 1 +Line 4389: 1 +Line 4390: 0 +Line 4391: 0 +Line 4392: 1 +Line 4393: 1 +Line 4394: 0 +Line 4395: 0 +Line 4396: 1 +Line 4397: 0 +Line 4398: 0 +Line 4399: 0 +Line 4400: 0 +Line 4401: 0 +Line 4402: 0 +Line 4403: 0 +Line 4404: 0 +Line 4405: 0 +Line 4406: 0 +Line 4407: 0 +Line 4408: 0 +Line 4409: 0 +Line 4410: 0 +Line 4411: 0 +Line 4412: 0 +Line 4413: 0 +Line 4414: 0 +Line 4415: 0 +Line 4416: 0 +Line 4417: 0 +Line 4418: 0 +Line 4419: 1 +Line 4420: 1 +Line 4421: 0 +Line 4422: 1 +Line 4423: 1 +Line 4424: 1 +Line 4425: 0 +Line 4426: 1 +Line 4427: 0 +Line 4428: 0 +Line 4429: 1 +Line 4430: 1 +Line 4431: 0 +Line 4432: 0 +Line 4433: 0 +Line 4434: 0 +Line 4435: 0 +Line 4436: 0 +Line 4437: 0 +Line 4438: 0 +Line 4439: 0 +Line 4440: 0 +Line 4441: 0 +Line 4442: 0 +Line 4443: 0 +Line 4444: 0 +Line 4445: 0 +Line 4446: 0 +Line 4447: 0 +Line 4448: 0 +Line 4449: 0 +Line 4450: 0 +Line 4451: 1 +Line 4452: 1 +Line 4453: 0 +Line 4454: 1 +Line 4455: 0 +Line 4456: 1 +Line 4457: 0 +Line 4458: 0 +Line 4459: 0 +Line 4460: 0 +Line 4461: 1 +Line 4462: 1 +Line 4463: 1 +Line 4464: 0 +Line 4465: 0 +Line 4466: 0 +Line 4467: 0 +Line 4468: 0 +Line 4469: 0 +Line 4470: 0 +Line 4471: 0 +Line 4472: 0 +Line 4473: 0 +Line 4474: 0 +Line 4475: 0 +Line 4476: 0 +Line 4477: 0 +Line 4478: 0 +Line 4479: 0 +Line 4480: 0 +Line 4481: 0 +Line 4482: 0 +Line 4483: 1 +Line 4484: 1 +Line 4485: 0 +Line 4486: 0 +Line 4487: 1 +Line 4488: 0 +Line 4489: 1 +Line 4490: 1 +Line 4491: 0 +Line 4492: 1 +Line 4493: 1 +Line 4494: 0 +Line 4495: 0 +Line 4496: 0 +Line 4497: 0 +Line 4498: 0 +Line 4499: 0 +Line 4500: 0 +Line 4501: 0 +Line 4502: 0 +Line 4503: 0 +Line 4504: 0 +Line 4505: 0 +Line 4506: 0 +Line 4507: 0 +Line 4508: 0 +Line 4509: 0 +Line 4510: 0 +Line 4511: 0 +Line 4512: 0 +Line 4513: 0 +Line 4514: 0 +Line 4515: 1 +Line 4516: 1 +Line 4517: 0 +Line 4518: 0 +Line 4519: 0 +Line 4520: 0 +Line 4521: 1 +Line 4522: 0 +Line 4523: 1 +Line 4524: 0 +Line 4525: 1 +Line 4526: 1 +Line 4527: 0 +Line 4528: 0 +Line 4529: 0 +Line 4530: 0 +Line 4531: 0 +Line 4532: 0 +Line 4533: 0 +Line 4534: 0 +Line 4535: 0 +Line 4536: 0 +Line 4537: 0 +Line 4538: 0 +Line 4539: 0 +Line 4540: 0 +Line 4541: 0 +Line 4542: 0 +Line 4543: 0 +Line 4544: 0 +Line 4545: 0 +Line 4546: 0 +Line 4547: 1 +Line 4548: 0 +Line 4549: 1 +Line 4550: 1 +Line 4551: 1 +Line 4552: 0 +Line 4553: 1 +Line 4554: 0 +Line 4555: 0 +Line 4556: 0 +Line 4557: 0 +Line 4558: 1 +Line 4559: 1 +Line 4560: 0 +Line 4561: 0 +Line 4562: 0 +Line 4563: 0 +Line 4564: 0 +Line 4565: 0 +Line 4566: 0 +Line 4567: 0 +Line 4568: 0 +Line 4569: 0 +Line 4570: 0 +Line 4571: 0 +Line 4572: 0 +Line 4573: 0 +Line 4574: 0 +Line 4575: 0 +Line 4576: 0 +Line 4577: 0 +Line 4578: 0 +Line 4579: 1 +Line 4580: 0 +Line 4581: 1 +Line 4582: 1 +Line 4583: 0 +Line 4584: 0 +Line 4585: 0 +Line 4586: 1 +Line 4587: 1 +Line 4588: 0 +Line 4589: 1 +Line 4590: 1 +Line 4591: 0 +Line 4592: 0 +Line 4593: 0 +Line 4594: 0 +Line 4595: 0 +Line 4596: 0 +Line 4597: 0 +Line 4598: 0 +Line 4599: 0 +Line 4600: 0 +Line 4601: 0 +Line 4602: 0 +Line 4603: 0 +Line 4604: 0 +Line 4605: 0 +Line 4606: 0 +Line 4607: 0 +Line 4608: 0 +Line 4609: 0 +Line 4610: 0 +Line 4611: 1 +Line 4612: 0 +Line 4613: 1 +Line 4614: 0 +Line 4615: 1 +Line 4616: 0 +Line 4617: 0 +Line 4618: 1 +Line 4619: 0 +Line 4620: 1 +Line 4621: 1 +Line 4622: 1 +Line 4623: 0 +Line 4624: 0 +Line 4625: 0 +Line 4626: 0 +Line 4627: 0 +Line 4628: 0 +Line 4629: 0 +Line 4630: 0 +Line 4631: 0 +Line 4632: 0 +Line 4633: 0 +Line 4634: 0 +Line 4635: 0 +Line 4636: 0 +Line 4637: 0 +Line 4638: 0 +Line 4639: 0 +Line 4640: 0 +Line 4641: 0 +Line 4642: 0 +Line 4643: 1 +Line 4644: 0 +Line 4645: 1 +Line 4646: 0 +Line 4647: 0 +Line 4648: 0 +Line 4649: 0 +Line 4650: 1 +Line 4651: 0 +Line 4652: 1 +Line 4653: 0 +Line 4654: 1 +Line 4655: 1 +Line 4656: 0 +Line 4657: 0 +Line 4658: 0 +Line 4659: 0 +Line 4660: 0 +Line 4661: 0 +Line 4662: 0 +Line 4663: 0 +Line 4664: 0 +Line 4665: 0 +Line 4666: 0 +Line 4667: 0 +Line 4668: 0 +Line 4669: 0 +Line 4670: 0 +Line 4671: 0 +Line 4672: 1 +Line 4673: 1 +Line 4674: 1 +Line 4675: 1 +Line 4676: 1 +Line 4677: 1 +Line 4678: 1 +Line 4679: 0 +Line 4680: 0 +Line 4681: 1 +Line 4682: 1 +Line 4683: 0 +Line 4684: 0 +Line 4685: 1 +Line 4686: 1 +Line 4687: 1 +Line 4688: 0 +Line 4689: 0 +Line 4690: 0 +Line 4691: 0 +Line 4692: 0 +Line 4693: 0 +Line 4694: 0 +Line 4695: 0 +Line 4696: 0 +Line 4697: 0 +Line 4698: 0 +Line 4699: 0 +Line 4700: 0 +Line 4701: 0 +Line 4702: 0 +Line 4703: 0 +Line 4704: 1 +Line 4705: 1 +Line 4706: 1 +Line 4707: 1 +Line 4708: 0 +Line 4709: 1 +Line 4710: 0 +Line 4711: 0 +Line 4712: 1 +Line 4713: 1 +Line 4714: 0 +Line 4715: 1 +Line 4716: 1 +Line 4717: 0 +Line 4718: 0 +Line 4719: 1 +Line 4720: 0 +Line 4721: 0 +Line 4722: 0 +Line 4723: 0 +Line 4724: 0 +Line 4725: 0 +Line 4726: 0 +Line 4727: 0 +Line 4728: 0 +Line 4729: 0 +Line 4730: 0 +Line 4731: 0 +Line 4732: 0 +Line 4733: 0 +Line 4734: 0 +Line 4735: 0 +Line 4736: 1 +Line 4737: 1 +Line 4738: 0 +Line 4739: 1 +Line 4740: 1 +Line 4741: 1 +Line 4742: 0 +Line 4743: 0 +Line 4744: 1 +Line 4745: 1 +Line 4746: 0 +Line 4747: 1 +Line 4748: 1 +Line 4749: 0 +Line 4750: 0 +Line 4751: 0 +Line 4752: 0 +Line 4753: 0 +Line 4754: 0 +Line 4755: 0 +Line 4756: 0 +Line 4757: 0 +Line 4758: 0 +Line 4759: 0 +Line 4760: 0 +Line 4761: 0 +Line 4762: 0 +Line 4763: 0 +Line 4764: 0 +Line 4765: 0 +Line 4766: 0 +Line 4767: 0 +Line 4768: 1 +Line 4769: 1 +Line 4770: 0 +Line 4771: 0 +Line 4772: 0 +Line 4773: 1 +Line 4774: 0 +Line 4775: 0 +Line 4776: 1 +Line 4777: 1 +Line 4778: 0 +Line 4779: 1 +Line 4780: 1 +Line 4781: 0 +Line 4782: 0 +Line 4783: 0 +Line 4784: 0 +Line 4785: 0 +Line 4786: 0 +Line 4787: 0 +Line 4788: 0 +Line 4789: 0 +Line 4790: 0 +Line 4791: 0 +Line 4792: 0 +Line 4793: 0 +Line 4794: 0 +Line 4795: 0 +Line 4796: 0 +Line 4797: 0 +Line 4798: 0 +Line 4799: 0 +Line 4800: 1 +Line 4801: 0 +Line 4802: 1 +Line 4803: 1 +Line 4804: 1 +Line 4805: 0 +Line 4806: 1 +Line 4807: 1 +Line 4808: 0 +Line 4809: 1 +Line 4810: 0 +Line 4811: 0 +Line 4812: 1 +Line 4813: 0 +Line 4814: 1 +Line 4815: 0 +Line 4816: 0 +Line 4817: 0 +Line 4818: 0 +Line 4819: 0 +Line 4820: 0 +Line 4821: 0 +Line 4822: 0 +Line 4823: 0 +Line 4824: 0 +Line 4825: 0 +Line 4826: 0 +Line 4827: 0 +Line 4828: 0 +Line 4829: 0 +Line 4830: 0 +Line 4831: 0 +Line 4832: 1 +Line 4833: 0 +Line 4834: 1 +Line 4835: 1 +Line 4836: 1 +Line 4837: 0 +Line 4838: 0 +Line 4839: 1 +Line 4840: 1 +Line 4841: 1 +Line 4842: 0 +Line 4843: 0 +Line 4844: 1 +Line 4845: 0 +Line 4846: 0 +Line 4847: 1 +Line 4848: 0 +Line 4849: 0 +Line 4850: 0 +Line 4851: 0 +Line 4852: 0 +Line 4853: 0 +Line 4854: 0 +Line 4855: 0 +Line 4856: 0 +Line 4857: 0 +Line 4858: 0 +Line 4859: 0 +Line 4860: 0 +Line 4861: 0 +Line 4862: 0 +Line 4863: 0 +Line 4864: 1 +Line 4865: 0 +Line 4866: 1 +Line 4867: 1 +Line 4868: 1 +Line 4869: 0 +Line 4870: 0 +Line 4871: 1 +Line 4872: 1 +Line 4873: 0 +Line 4874: 1 +Line 4875: 1 +Line 4876: 0 +Line 4877: 0 +Line 4878: 0 +Line 4879: 1 +Line 4880: 0 +Line 4881: 0 +Line 4882: 0 +Line 4883: 0 +Line 4884: 0 +Line 4885: 0 +Line 4886: 0 +Line 4887: 0 +Line 4888: 0 +Line 4889: 0 +Line 4890: 0 +Line 4891: 0 +Line 4892: 0 +Line 4893: 0 +Line 4894: 0 +Line 4895: 0 +Line 4896: 1 +Line 4897: 0 +Line 4898: 1 +Line 4899: 1 +Line 4900: 1 +Line 4901: 0 +Line 4902: 0 +Line 4903: 1 +Line 4904: 1 +Line 4905: 0 +Line 4906: 1 +Line 4907: 1 +Line 4908: 0 +Line 4909: 0 +Line 4910: 0 +Line 4911: 1 +Line 4912: 0 +Line 4913: 0 +Line 4914: 0 +Line 4915: 0 +Line 4916: 0 +Line 4917: 0 +Line 4918: 0 +Line 4919: 0 +Line 4920: 0 +Line 4921: 0 +Line 4922: 0 +Line 4923: 0 +Line 4924: 0 +Line 4925: 0 +Line 4926: 0 +Line 4927: 0 +Line 4928: 1 +Line 4929: 0 +Line 4930: 1 +Line 4931: 1 +Line 4932: 1 +Line 4933: 0 +Line 4934: 0 +Line 4935: 1 +Line 4936: 1 +Line 4937: 0 +Line 4938: 1 +Line 4939: 1 +Line 4940: 0 +Line 4941: 0 +Line 4942: 0 +Line 4943: 1 +Line 4944: 0 +Line 4945: 0 +Line 4946: 0 +Line 4947: 0 +Line 4948: 0 +Line 4949: 0 +Line 4950: 0 +Line 4951: 0 +Line 4952: 0 +Line 4953: 0 +Line 4954: 0 +Line 4955: 0 +Line 4956: 0 +Line 4957: 0 +Line 4958: 0 +Line 4959: 0 +Line 4960: 1 +Line 4961: 0 +Line 4962: 1 +Line 4963: 1 +Line 4964: 1 +Line 4965: 0 +Line 4966: 0 +Line 4967: 1 +Line 4968: 1 +Line 4969: 0 +Line 4970: 1 +Line 4971: 1 +Line 4972: 0 +Line 4973: 0 +Line 4974: 0 +Line 4975: 1 +Line 4976: 0 +Line 4977: 0 +Line 4978: 0 +Line 4979: 0 +Line 4980: 0 +Line 4981: 0 +Line 4982: 0 +Line 4983: 0 +Line 4984: 0 +Line 4985: 0 +Line 4986: 0 +Line 4987: 0 +Line 4988: 0 +Line 4989: 0 +Line 4990: 0 +Line 4991: 0 +Line 4992: 1 +Line 4993: 0 +Line 4994: 1 +Line 4995: 1 +Line 4996: 1 +Line 4997: 0 +Line 4998: 0 +Line 4999: 1 +Line 5000: 1 +Line 5001: 0 +Line 5002: 1 +Line 5003: 1 +Line 5004: 0 +Line 5005: 0 +Line 5006: 0 +Line 5007: 1 +Line 5008: 0 +Line 5009: 0 +Line 5010: 0 +Line 5011: 0 +Line 5012: 0 +Line 5013: 0 +Line 5014: 0 +Line 5015: 0 +Line 5016: 0 +Line 5017: 0 +Line 5018: 0 +Line 5019: 0 +Line 5020: 0 +Line 5021: 0 +Line 5022: 0 +Line 5023: 0 +Line 5024: 1 +Line 5025: 0 +Line 5026: 1 +Line 5027: 1 +Line 5028: 1 +Line 5029: 0 +Line 5030: 0 +Line 5031: 1 +Line 5032: 1 +Line 5033: 0 +Line 5034: 1 +Line 5035: 1 +Line 5036: 0 +Line 5037: 0 +Line 5038: 0 +Line 5039: 0 +Line 5040: 0 +Line 5041: 0 +Line 5042: 0 +Line 5043: 0 +Line 5044: 0 +Line 5045: 0 +Line 5046: 0 +Line 5047: 0 +Line 5048: 0 +Line 5049: 0 +Line 5050: 0 +Line 5051: 0 +Line 5052: 0 +Line 5053: 0 +Line 5054: 0 +Line 5055: 0 +Line 5056: 1 +Line 5057: 0 +Line 5058: 1 +Line 5059: 1 +Line 5060: 1 +Line 5061: 0 +Line 5062: 0 +Line 5063: 1 +Line 5064: 1 +Line 5065: 0 +Line 5066: 1 +Line 5067: 1 +Line 5068: 0 +Line 5069: 0 +Line 5070: 0 +Line 5071: 0 +Line 5072: 0 +Line 5073: 0 +Line 5074: 0 +Line 5075: 0 +Line 5076: 0 +Line 5077: 0 +Line 5078: 0 +Line 5079: 0 +Line 5080: 0 +Line 5081: 0 +Line 5082: 0 +Line 5083: 0 +Line 5084: 0 +Line 5085: 0 +Line 5086: 0 +Line 5087: 0 +Line 5088: 1 +Line 5089: 0 +Line 5090: 1 +Line 5091: 1 +Line 5092: 1 +Line 5093: 0 +Line 5094: 0 +Line 5095: 1 +Line 5096: 1 +Line 5097: 0 +Line 5098: 1 +Line 5099: 1 +Line 5100: 0 +Line 5101: 0 +Line 5102: 0 +Line 5103: 0 +Line 5104: 0 +Line 5105: 0 +Line 5106: 0 +Line 5107: 0 +Line 5108: 0 +Line 5109: 0 +Line 5110: 0 +Line 5111: 0 +Line 5112: 0 +Line 5113: 0 +Line 5114: 0 +Line 5115: 0 +Line 5116: 0 +Line 5117: 0 +Line 5118: 0 +Line 5119: 0 +Line 5120: 1 +Line 5121: 0 +Line 5122: 1 +Line 5123: 1 +Line 5124: 1 +Line 5125: 0 +Line 5126: 0 +Line 5127: 1 +Line 5128: 1 +Line 5129: 0 +Line 5130: 1 +Line 5131: 1 +Line 5132: 0 +Line 5133: 0 +Line 5134: 0 +Line 5135: 1 +Line 5136: 0 +Line 5137: 0 +Line 5138: 0 +Line 5139: 0 +Line 5140: 0 +Line 5141: 0 +Line 5142: 0 +Line 5143: 0 +Line 5144: 0 +Line 5145: 0 +Line 5146: 0 +Line 5147: 0 +Line 5148: 0 +Line 5149: 0 +Line 5150: 0 +Line 5151: 0 +Line 5152: 1 +Line 5153: 0 +Line 5154: 1 +Line 5155: 1 +Line 5156: 1 +Line 5157: 0 +Line 5158: 0 +Line 5159: 1 +Line 5160: 1 +Line 5161: 0 +Line 5162: 1 +Line 5163: 1 +Line 5164: 0 +Line 5165: 0 +Line 5166: 0 +Line 5167: 1 +Line 5168: 0 +Line 5169: 0 +Line 5170: 0 +Line 5171: 0 +Line 5172: 0 +Line 5173: 0 +Line 5174: 0 +Line 5175: 0 +Line 5176: 0 +Line 5177: 0 +Line 5178: 0 +Line 5179: 0 +Line 5180: 0 +Line 5181: 0 +Line 5182: 0 +Line 5183: 0 +Line 5184: 1 +Line 5185: 0 +Line 5186: 1 +Line 5187: 1 +Line 5188: 1 +Line 5189: 0 +Line 5190: 0 +Line 5191: 1 +Line 5192: 1 +Line 5193: 0 +Line 5194: 1 +Line 5195: 1 +Line 5196: 0 +Line 5197: 0 +Line 5198: 0 +Line 5199: 1 +Line 5200: 0 +Line 5201: 0 +Line 5202: 0 +Line 5203: 0 +Line 5204: 0 +Line 5205: 0 +Line 5206: 0 +Line 5207: 0 +Line 5208: 0 +Line 5209: 0 +Line 5210: 0 +Line 5211: 0 +Line 5212: 0 +Line 5213: 0 +Line 5214: 0 +Line 5215: 0 +Line 5216: 1 +Line 5217: 0 +Line 5218: 1 +Line 5219: 1 +Line 5220: 1 +Line 5221: 0 +Line 5222: 0 +Line 5223: 1 +Line 5224: 1 +Line 5225: 0 +Line 5226: 1 +Line 5227: 1 +Line 5228: 0 +Line 5229: 0 +Line 5230: 0 +Line 5231: 1 +Line 5232: 0 +Line 5233: 0 +Line 5234: 0 +Line 5235: 0 +Line 5236: 0 +Line 5237: 0 +Line 5238: 0 +Line 5239: 0 +Line 5240: 0 +Line 5241: 0 +Line 5242: 0 +Line 5243: 0 +Line 5244: 0 +Line 5245: 0 +Line 5246: 0 +Line 5247: 0 +Line 5248: 1 +Line 5249: 0 +Line 5250: 1 +Line 5251: 1 +Line 5252: 1 +Line 5253: 0 +Line 5254: 0 +Line 5255: 1 +Line 5256: 1 +Line 5257: 0 +Line 5258: 1 +Line 5259: 1 +Line 5260: 0 +Line 5261: 0 +Line 5262: 0 +Line 5263: 1 +Line 5264: 0 +Line 5265: 0 +Line 5266: 0 +Line 5267: 0 +Line 5268: 0 +Line 5269: 0 +Line 5270: 0 +Line 5271: 0 +Line 5272: 0 +Line 5273: 0 +Line 5274: 0 +Line 5275: 0 +Line 5276: 0 +Line 5277: 0 +Line 5278: 0 +Line 5279: 0 +Line 5280: 1 +Line 5281: 0 +Line 5282: 1 +Line 5283: 1 +Line 5284: 1 +Line 5285: 0 +Line 5286: 0 +Line 5287: 1 +Line 5288: 1 +Line 5289: 1 +Line 5290: 0 +Line 5291: 0 +Line 5292: 1 +Line 5293: 0 +Line 5294: 0 +Line 5295: 1 +Line 5296: 0 +Line 5297: 0 +Line 5298: 0 +Line 5299: 0 +Line 5300: 0 +Line 5301: 0 +Line 5302: 0 +Line 5303: 0 +Line 5304: 0 +Line 5305: 0 +Line 5306: 0 +Line 5307: 0 +Line 5308: 0 +Line 5309: 0 +Line 5310: 0 +Line 5311: 0 +Line 5312: 1 +Line 5313: 0 +Line 5314: 1 +Line 5315: 1 +Line 5316: 1 +Line 5317: 0 +Line 5318: 1 +Line 5319: 1 +Line 5320: 0 +Line 5321: 1 +Line 5322: 0 +Line 5323: 0 +Line 5324: 1 +Line 5325: 0 +Line 5326: 1 +Line 5327: 0 +Line 5328: 0 +Line 5329: 0 +Line 5330: 0 +Line 5331: 0 +Line 5332: 0 +Line 5333: 0 +Line 5334: 0 +Line 5335: 0 +Line 5336: 0 +Line 5337: 0 +Line 5338: 0 +Line 5339: 0 +Line 5340: 0 +Line 5341: 0 +Line 5342: 0 +Line 5343: 0 +Line 5344: 1 +Line 5345: 1 +Line 5346: 0 +Line 5347: 0 +Line 5348: 0 +Line 5349: 1 +Line 5350: 0 +Line 5351: 0 +Line 5352: 1 +Line 5353: 1 +Line 5354: 0 +Line 5355: 1 +Line 5356: 1 +Line 5357: 0 +Line 5358: 0 +Line 5359: 0 +Line 5360: 0 +Line 5361: 0 +Line 5362: 0 +Line 5363: 0 +Line 5364: 0 +Line 5365: 0 +Line 5366: 0 +Line 5367: 0 +Line 5368: 0 +Line 5369: 0 +Line 5370: 0 +Line 5371: 0 +Line 5372: 0 +Line 5373: 0 +Line 5374: 0 +Line 5375: 0 +Line 5376: 1 +Line 5377: 1 +Line 5378: 0 +Line 5379: 1 +Line 5380: 1 +Line 5381: 1 +Line 5382: 0 +Line 5383: 0 +Line 5384: 1 +Line 5385: 1 +Line 5386: 0 +Line 5387: 1 +Line 5388: 1 +Line 5389: 0 +Line 5390: 0 +Line 5391: 0 +Line 5392: 0 +Line 5393: 0 +Line 5394: 0 +Line 5395: 0 +Line 5396: 0 +Line 5397: 0 +Line 5398: 0 +Line 5399: 0 +Line 5400: 0 +Line 5401: 0 +Line 5402: 0 +Line 5403: 0 +Line 5404: 0 +Line 5405: 0 +Line 5406: 0 +Line 5407: 0 +Line 5408: 1 +Line 5409: 1 +Line 5410: 1 +Line 5411: 1 +Line 5412: 0 +Line 5413: 1 +Line 5414: 0 +Line 5415: 0 +Line 5416: 1 +Line 5417: 1 +Line 5418: 0 +Line 5419: 1 +Line 5420: 1 +Line 5421: 0 +Line 5422: 0 +Line 5423: 1 +Line 5424: 0 +Line 5425: 0 +Line 5426: 0 +Line 5427: 0 +Line 5428: 0 +Line 5429: 0 +Line 5430: 0 +Line 5431: 0 +Line 5432: 0 +Line 5433: 0 +Line 5434: 0 +Line 5435: 0 +Line 5436: 0 +Line 5437: 0 +Line 5438: 0 +Line 5439: 0 +Line 5440: 1 +Line 5441: 1 +Line 5442: 1 +Line 5443: 1 +Line 5444: 1 +Line 5445: 1 +Line 5446: 1 +Line 5447: 0 +Line 5448: 0 +Line 5449: 1 +Line 5450: 1 +Line 5451: 0 +Line 5452: 0 +Line 5453: 1 +Line 5454: 1 +Line 5455: 1 +Line 5456: 0 +Line 5457: 0 +Line 5458: 0 +Line 5459: 0 +Line 5460: 0 +Line 5461: 0 +Line 5462: 0 +Line 5463: 0 +Line 5464: 0 +Line 5465: 0 +Line 5466: 0 +Line 5467: 0 +Line 5468: 0 +Line 5469: 0 +Line 5470: 0 +Line 5471: 0 +Line 5472: 0 +Line 5473: 0 +Line 5474: 0 +Line 5475: 0 +Line 5476: 0 +Line 5477: 0 +Line 5478: 0 +Line 5479: 0 +Line 5480: 0 +Line 5481: 0 +Line 5482: 0 +Line 5483: 0 +Line 5484: 0 +Line 5485: 0 +Line 5486: 0 +Line 5487: 0 +Line 5488: 0 +Line 5489: 0 +Line 5490: 0 +Line 5491: 0 +Line 5492: 0 +Line 5493: 0 +Line 5494: 0 +Line 5495: 0 +Line 5496: 0 +Line 5497: 0 +Line 5498: 0 +Line 5499: 0 +Line 5500: 0 +Line 5501: 0 +Line 5502: 0 +Line 5503: 0 +Line 5504: 0 +Line 5505: 0 +Line 5506: 0 +Line 5507: 0 +Line 5508: 0 +Line 5509: 0 +Line 5510: 0 +Line 5511: 0 +Line 5512: 0 +Line 5513: 0 +Line 5514: 0 +Line 5515: 0 +Line 5516: 0 +Line 5517: 1 +Line 5518: 0 +Line 5519: 1 +Line 5520: 1 +Line 5521: 1 +Line 5522: 1 +Line 5523: 1 +Line 5524: 1 +Line 5525: 1 +Line 5526: 1 +Line 5527: 1 +Line 5528: 1 +Line 5529: 1 +Line 5530: 1 +Line 5531: 1 +Line 5532: 0 +Line 5533: 0 +Line 5534: 0 +Line 5535: 1 +Line 5536: 0 +Line 5537: 0 +Line 5538: 0 +Line 5539: 0 +Line 5540: 0 +Line 5541: 0 +Line 5542: 0 +Line 5543: 0 +Line 5544: 0 +Line 5545: 0 +Line 5546: 0 +Line 5547: 1 +Line 5548: 0 +Line 5549: 1 +Line 5550: 1 +Line 5551: 1 +Line 5552: 1 +Line 5553: 1 +Line 5554: 1 +Line 5555: 1 +Line 5556: 1 +Line 5557: 1 +Line 5558: 1 +Line 5559: 1 +Line 5560: 1 +Line 5561: 1 +Line 5562: 1 +Line 5563: 0 +Line 5564: 0 +Line 5565: 0 +Line 5566: 0 +Line 5567: 1 +Line 5568: 0 +Line 5569: 0 +Line 5570: 0 +Line 5571: 0 +Line 5572: 0 +Line 5573: 0 +Line 5574: 0 +Line 5575: 0 +Line 5576: 0 +Line 5577: 0 +Line 5578: 1 +Line 5579: 1 +Line 5580: 0 +Line 5581: 1 +Line 5582: 0 +Line 5583: 0 +Line 5584: 1 +Line 5585: 1 +Line 5586: 1 +Line 5587: 1 +Line 5588: 1 +Line 5589: 1 +Line 5590: 1 +Line 5591: 1 +Line 5592: 1 +Line 5593: 1 +Line 5594: 0 +Line 5595: 1 +Line 5596: 0 +Line 5597: 0 +Line 5598: 0 +Line 5599: 1 +Line 5600: 0 +Line 5601: 0 +Line 5602: 0 +Line 5603: 0 +Line 5604: 0 +Line 5605: 0 +Line 5606: 0 +Line 5607: 0 +Line 5608: 0 +Line 5609: 1 +Line 5610: 0 +Line 5611: 1 +Line 5612: 1 +Line 5613: 1 +Line 5614: 0 +Line 5615: 1 +Line 5616: 1 +Line 5617: 1 +Line 5618: 1 +Line 5619: 1 +Line 5620: 1 +Line 5621: 1 +Line 5622: 1 +Line 5623: 1 +Line 5624: 1 +Line 5625: 1 +Line 5626: 0 +Line 5627: 0 +Line 5628: 0 +Line 5629: 0 +Line 5630: 1 +Line 5631: 0 +Line 5632: 0 +Line 5633: 0 +Line 5634: 0 +Line 5635: 0 +Line 5636: 0 +Line 5637: 0 +Line 5638: 0 +Line 5639: 0 +Line 5640: 1 +Line 5641: 0 +Line 5642: 0 +Line 5643: 1 +Line 5644: 0 +Line 5645: 0 +Line 5646: 1 +Line 5647: 0 +Line 5648: 1 +Line 5649: 1 +Line 5650: 1 +Line 5651: 1 +Line 5652: 1 +Line 5653: 1 +Line 5654: 1 +Line 5655: 1 +Line 5656: 1 +Line 5657: 0 +Line 5658: 1 +Line 5659: 1 +Line 5660: 0 +Line 5661: 0 +Line 5662: 1 +Line 5663: 0 +Line 5664: 0 +Line 5665: 0 +Line 5666: 0 +Line 5667: 0 +Line 5668: 0 +Line 5669: 0 +Line 5670: 0 +Line 5671: 0 +Line 5672: 1 +Line 5673: 1 +Line 5674: 0 +Line 5675: 1 +Line 5676: 0 +Line 5677: 0 +Line 5678: 1 +Line 5679: 0 +Line 5680: 1 +Line 5681: 1 +Line 5682: 1 +Line 5683: 1 +Line 5684: 1 +Line 5685: 1 +Line 5686: 1 +Line 5687: 1 +Line 5688: 1 +Line 5689: 0 +Line 5690: 1 +Line 5691: 0 +Line 5692: 0 +Line 5693: 0 +Line 5694: 1 +Line 5695: 1 +Line 5696: 0 +Line 5697: 0 +Line 5698: 0 +Line 5699: 0 +Line 5700: 0 +Line 5701: 0 +Line 5702: 0 +Line 5703: 1 +Line 5704: 0 +Line 5705: 0 +Line 5706: 0 +Line 5707: 1 +Line 5708: 1 +Line 5709: 1 +Line 5710: 0 +Line 5711: 1 +Line 5712: 1 +Line 5713: 1 +Line 5714: 1 +Line 5715: 1 +Line 5716: 1 +Line 5717: 1 +Line 5718: 1 +Line 5719: 1 +Line 5720: 1 +Line 5721: 0 +Line 5722: 0 +Line 5723: 1 +Line 5724: 0 +Line 5725: 1 +Line 5726: 0 +Line 5727: 0 +Line 5728: 0 +Line 5729: 0 +Line 5730: 0 +Line 5731: 0 +Line 5732: 0 +Line 5733: 0 +Line 5734: 0 +Line 5735: 1 +Line 5736: 0 +Line 5737: 1 +Line 5738: 1 +Line 5739: 1 +Line 5740: 0 +Line 5741: 1 +Line 5742: 0 +Line 5743: 0 +Line 5744: 1 +Line 5745: 1 +Line 5746: 1 +Line 5747: 1 +Line 5748: 1 +Line 5749: 1 +Line 5750: 1 +Line 5751: 1 +Line 5752: 1 +Line 5753: 0 +Line 5754: 0 +Line 5755: 0 +Line 5756: 0 +Line 5757: 1 +Line 5758: 0 +Line 5759: 0 +Line 5760: 0 +Line 5761: 0 +Line 5762: 0 +Line 5763: 0 +Line 5764: 0 +Line 5765: 0 +Line 5766: 0 +Line 5767: 1 +Line 5768: 1 +Line 5769: 1 +Line 5770: 0 +Line 5771: 1 +Line 5772: 0 +Line 5773: 1 +Line 5774: 1 +Line 5775: 1 +Line 5776: 1 +Line 5777: 1 +Line 5778: 1 +Line 5779: 1 +Line 5780: 1 +Line 5781: 1 +Line 5782: 1 +Line 5783: 1 +Line 5784: 0 +Line 5785: 1 +Line 5786: 1 +Line 5787: 1 +Line 5788: 0 +Line 5789: 1 +Line 5790: 0 +Line 5791: 1 +Line 5792: 0 +Line 5793: 0 +Line 5794: 0 +Line 5795: 0 +Line 5796: 0 +Line 5797: 0 +Line 5798: 1 +Line 5799: 0 +Line 5800: 0 +Line 5801: 1 +Line 5802: 0 +Line 5803: 0 +Line 5804: 0 +Line 5805: 1 +Line 5806: 0 +Line 5807: 0 +Line 5808: 1 +Line 5809: 1 +Line 5810: 1 +Line 5811: 1 +Line 5812: 1 +Line 5813: 1 +Line 5814: 1 +Line 5815: 1 +Line 5816: 0 +Line 5817: 1 +Line 5818: 1 +Line 5819: 0 +Line 5820: 0 +Line 5821: 1 +Line 5822: 1 +Line 5823: 1 +Line 5824: 0 +Line 5825: 0 +Line 5826: 0 +Line 5827: 0 +Line 5828: 0 +Line 5829: 0 +Line 5830: 1 +Line 5831: 0 +Line 5832: 1 +Line 5833: 0 +Line 5834: 1 +Line 5835: 1 +Line 5836: 1 +Line 5837: 1 +Line 5838: 0 +Line 5839: 0 +Line 5840: 1 +Line 5841: 1 +Line 5842: 1 +Line 5843: 1 +Line 5844: 1 +Line 5845: 1 +Line 5846: 1 +Line 5847: 1 +Line 5848: 0 +Line 5849: 1 +Line 5850: 0 +Line 5851: 1 +Line 5852: 1 +Line 5853: 0 +Line 5854: 0 +Line 5855: 0 +Line 5856: 0 +Line 5857: 0 +Line 5858: 0 +Line 5859: 0 +Line 5860: 0 +Line 5861: 0 +Line 5862: 1 +Line 5863: 1 +Line 5864: 0 +Line 5865: 0 +Line 5866: 1 +Line 5867: 1 +Line 5868: 1 +Line 5869: 1 +Line 5870: 1 +Line 5871: 1 +Line 5872: 1 +Line 5873: 1 +Line 5874: 1 +Line 5875: 1 +Line 5876: 1 +Line 5877: 1 +Line 5878: 1 +Line 5879: 1 +Line 5880: 0 +Line 5881: 1 +Line 5882: 0 +Line 5883: 0 +Line 5884: 1 +Line 5885: 0 +Line 5886: 1 +Line 5887: 0 +Line 5888: 0 +Line 5889: 0 +Line 5890: 0 +Line 5891: 0 +Line 5892: 0 +Line 5893: 0 +Line 5894: 1 +Line 5895: 1 +Line 5896: 1 +Line 5897: 1 +Line 5898: 0 +Line 5899: 0 +Line 5900: 1 +Line 5901: 1 +Line 5902: 0 +Line 5903: 1 +Line 5904: 1 +Line 5905: 1 +Line 5906: 1 +Line 5907: 1 +Line 5908: 1 +Line 5909: 1 +Line 5910: 1 +Line 5911: 1 +Line 5912: 0 +Line 5913: 0 +Line 5914: 1 +Line 5915: 1 +Line 5916: 1 +Line 5917: 0 +Line 5918: 1 +Line 5919: 1 +Line 5920: 0 +Line 5921: 0 +Line 5922: 0 +Line 5923: 0 +Line 5924: 0 +Line 5925: 1 +Line 5926: 0 +Line 5927: 0 +Line 5928: 0 +Line 5929: 1 +Line 5930: 1 +Line 5931: 0 +Line 5932: 0 +Line 5933: 1 +Line 5934: 0 +Line 5935: 1 +Line 5936: 1 +Line 5937: 1 +Line 5938: 1 +Line 5939: 1 +Line 5940: 1 +Line 5941: 1 +Line 5942: 1 +Line 5943: 1 +Line 5944: 0 +Line 5945: 0 +Line 5946: 1 +Line 5947: 0 +Line 5948: 1 +Line 5949: 1 +Line 5950: 1 +Line 5951: 0 +Line 5952: 0 +Line 5953: 0 +Line 5954: 0 +Line 5955: 0 +Line 5956: 0 +Line 5957: 1 +Line 5958: 0 +Line 5959: 1 +Line 5960: 0 +Line 5961: 0 +Line 5962: 0 +Line 5963: 0 +Line 5964: 1 +Line 5965: 0 +Line 5966: 0 +Line 5967: 0 +Line 5968: 1 +Line 5969: 1 +Line 5970: 1 +Line 5971: 1 +Line 5972: 1 +Line 5973: 1 +Line 5974: 1 +Line 5975: 1 +Line 5976: 0 +Line 5977: 0 +Line 5978: 1 +Line 5979: 0 +Line 5980: 0 +Line 5981: 0 +Line 5982: 0 +Line 5983: 0 +Line 5984: 0 +Line 5985: 0 +Line 5986: 0 +Line 5987: 0 +Line 5988: 0 +Line 5989: 1 +Line 5990: 0 +Line 5991: 1 +Line 5992: 1 +Line 5993: 0 +Line 5994: 1 +Line 5995: 1 +Line 5996: 0 +Line 5997: 1 +Line 5998: 0 +Line 5999: 0 +Line 6000: 1 +Line 6001: 1 +Line 6002: 1 +Line 6003: 1 +Line 6004: 1 +Line 6005: 1 +Line 6006: 1 +Line 6007: 1 +Line 6008: 0 +Line 6009: 0 +Line 6010: 0 +Line 6011: 1 +Line 6012: 0 +Line 6013: 0 +Line 6014: 1 +Line 6015: 1 +Line 6016: 0 +Line 6017: 0 +Line 6018: 0 +Line 6019: 0 +Line 6020: 0 +Line 6021: 1 +Line 6022: 1 +Line 6023: 0 +Line 6024: 0 +Line 6025: 1 +Line 6026: 1 +Line 6027: 0 +Line 6028: 1 +Line 6029: 0 +Line 6030: 1 +Line 6031: 1 +Line 6032: 1 +Line 6033: 1 +Line 6034: 1 +Line 6035: 1 +Line 6036: 1 +Line 6037: 1 +Line 6038: 1 +Line 6039: 1 +Line 6040: 0 +Line 6041: 0 +Line 6042: 0 +Line 6043: 0 +Line 6044: 0 +Line 6045: 1 +Line 6046: 1 +Line 6047: 0 +Line 6048: 0 +Line 6049: 0 +Line 6050: 0 +Line 6051: 0 +Line 6052: 0 +Line 6053: 1 +Line 6054: 1 +Line 6055: 1 +Line 6056: 0 +Line 6057: 0 +Line 6058: 1 +Line 6059: 0 +Line 6060: 1 +Line 6061: 0 +Line 6062: 1 +Line 6063: 1 +Line 6064: 1 +Line 6065: 1 +Line 6066: 1 +Line 6067: 1 +Line 6068: 1 +Line 6069: 1 +Line 6070: 1 +Line 6071: 0 +Line 6072: 1 +Line 6073: 1 +Line 6074: 1 +Line 6075: 1 +Line 6076: 1 +Line 6077: 0 +Line 6078: 0 +Line 6079: 1 +Line 6080: 0 +Line 6081: 0 +Line 6082: 0 +Line 6083: 0 +Line 6084: 0 +Line 6085: 1 +Line 6086: 1 +Line 6087: 1 +Line 6088: 1 +Line 6089: 1 +Line 6090: 1 +Line 6091: 1 +Line 6092: 0 +Line 6093: 1 +Line 6094: 0 +Line 6095: 0 +Line 6096: 1 +Line 6097: 1 +Line 6098: 1 +Line 6099: 1 +Line 6100: 1 +Line 6101: 1 +Line 6102: 1 +Line 6103: 0 +Line 6104: 1 +Line 6105: 1 +Line 6106: 1 +Line 6107: 0 +Line 6108: 1 +Line 6109: 1 +Line 6110: 0 +Line 6111: 1 +Line 6112: 0 +Line 6113: 0 +Line 6114: 0 +Line 6115: 0 +Line 6116: 1 +Line 6117: 0 +Line 6118: 0 +Line 6119: 0 +Line 6120: 1 +Line 6121: 1 +Line 6122: 0 +Line 6123: 0 +Line 6124: 0 +Line 6125: 1 +Line 6126: 1 +Line 6127: 0 +Line 6128: 1 +Line 6129: 1 +Line 6130: 1 +Line 6131: 1 +Line 6132: 1 +Line 6133: 1 +Line 6134: 1 +Line 6135: 0 +Line 6136: 1 +Line 6137: 1 +Line 6138: 1 +Line 6139: 0 +Line 6140: 0 +Line 6141: 0 +Line 6142: 0 +Line 6143: 1 +Line 6144: 0 +Line 6145: 0 +Line 6146: 0 +Line 6147: 0 +Line 6148: 1 +Line 6149: 0 +Line 6150: 0 +Line 6151: 1 +Line 6152: 1 +Line 6153: 0 +Line 6154: 1 +Line 6155: 0 +Line 6156: 0 +Line 6157: 0 +Line 6158: 1 +Line 6159: 0 +Line 6160: 1 +Line 6161: 1 +Line 6162: 1 +Line 6163: 1 +Line 6164: 1 +Line 6165: 1 +Line 6166: 1 +Line 6167: 0 +Line 6168: 1 +Line 6169: 1 +Line 6170: 0 +Line 6171: 1 +Line 6172: 0 +Line 6173: 1 +Line 6174: 0 +Line 6175: 1 +Line 6176: 0 +Line 6177: 0 +Line 6178: 0 +Line 6179: 0 +Line 6180: 1 +Line 6181: 0 +Line 6182: 1 +Line 6183: 0 +Line 6184: 1 +Line 6185: 0 +Line 6186: 0 +Line 6187: 0 +Line 6188: 0 +Line 6189: 1 +Line 6190: 0 +Line 6191: 1 +Line 6192: 1 +Line 6193: 1 +Line 6194: 1 +Line 6195: 1 +Line 6196: 1 +Line 6197: 1 +Line 6198: 1 +Line 6199: 0 +Line 6200: 1 +Line 6201: 1 +Line 6202: 0 +Line 6203: 0 +Line 6204: 1 +Line 6205: 0 +Line 6206: 1 +Line 6207: 0 +Line 6208: 0 +Line 6209: 0 +Line 6210: 0 +Line 6211: 0 +Line 6212: 1 +Line 6213: 0 +Line 6214: 1 +Line 6215: 1 +Line 6216: 0 +Line 6217: 1 +Line 6218: 1 +Line 6219: 1 +Line 6220: 0 +Line 6221: 0 +Line 6222: 0 +Line 6223: 1 +Line 6224: 1 +Line 6225: 1 +Line 6226: 1 +Line 6227: 1 +Line 6228: 1 +Line 6229: 1 +Line 6230: 1 +Line 6231: 0 +Line 6232: 1 +Line 6233: 0 +Line 6234: 1 +Line 6235: 1 +Line 6236: 1 +Line 6237: 1 +Line 6238: 1 +Line 6239: 1 +Line 6240: 0 +Line 6241: 0 +Line 6242: 0 +Line 6243: 0 +Line 6244: 1 +Line 6245: 1 +Line 6246: 0 +Line 6247: 0 +Line 6248: 0 +Line 6249: 1 +Line 6250: 1 +Line 6251: 0 +Line 6252: 0 +Line 6253: 1 +Line 6254: 0 +Line 6255: 1 +Line 6256: 1 +Line 6257: 1 +Line 6258: 1 +Line 6259: 1 +Line 6260: 1 +Line 6261: 1 +Line 6262: 1 +Line 6263: 0 +Line 6264: 1 +Line 6265: 0 +Line 6266: 1 +Line 6267: 1 +Line 6268: 0 +Line 6269: 1 +Line 6270: 0 +Line 6271: 1 +Line 6272: 0 +Line 6273: 0 +Line 6274: 0 +Line 6275: 0 +Line 6276: 1 +Line 6277: 1 +Line 6278: 0 +Line 6279: 1 +Line 6280: 0 +Line 6281: 1 +Line 6282: 1 +Line 6283: 0 +Line 6284: 0 +Line 6285: 0 +Line 6286: 0 +Line 6287: 0 +Line 6288: 1 +Line 6289: 1 +Line 6290: 1 +Line 6291: 1 +Line 6292: 1 +Line 6293: 1 +Line 6294: 1 +Line 6295: 0 +Line 6296: 1 +Line 6297: 0 +Line 6298: 1 +Line 6299: 0 +Line 6300: 1 +Line 6301: 0 +Line 6302: 1 +Line 6303: 1 +Line 6304: 0 +Line 6305: 0 +Line 6306: 0 +Line 6307: 0 +Line 6308: 1 +Line 6309: 1 +Line 6310: 1 +Line 6311: 0 +Line 6312: 0 +Line 6313: 1 +Line 6314: 1 +Line 6315: 0 +Line 6316: 0 +Line 6317: 0 +Line 6318: 1 +Line 6319: 1 +Line 6320: 1 +Line 6321: 1 +Line 6322: 1 +Line 6323: 1 +Line 6324: 1 +Line 6325: 1 +Line 6326: 1 +Line 6327: 0 +Line 6328: 1 +Line 6329: 0 +Line 6330: 1 +Line 6331: 0 +Line 6332: 0 +Line 6333: 0 +Line 6334: 0 +Line 6335: 1 +Line 6336: 0 +Line 6337: 0 +Line 6338: 0 +Line 6339: 0 +Line 6340: 1 +Line 6341: 1 +Line 6342: 1 +Line 6343: 1 +Line 6344: 0 +Line 6345: 1 +Line 6346: 1 +Line 6347: 0 +Line 6348: 1 +Line 6349: 1 +Line 6350: 0 +Line 6351: 1 +Line 6352: 1 +Line 6353: 1 +Line 6354: 1 +Line 6355: 1 +Line 6356: 1 +Line 6357: 1 +Line 6358: 1 +Line 6359: 0 +Line 6360: 1 +Line 6361: 0 +Line 6362: 0 +Line 6363: 1 +Line 6364: 1 +Line 6365: 0 +Line 6366: 0 +Line 6367: 0 +Line 6368: 0 +Line 6369: 0 +Line 6370: 0 +Line 6371: 1 +Line 6372: 0 +Line 6373: 0 +Line 6374: 0 +Line 6375: 0 +Line 6376: 0 +Line 6377: 1 +Line 6378: 1 +Line 6379: 1 +Line 6380: 1 +Line 6381: 1 +Line 6382: 0 +Line 6383: 1 +Line 6384: 1 +Line 6385: 1 +Line 6386: 1 +Line 6387: 1 +Line 6388: 1 +Line 6389: 1 +Line 6390: 1 +Line 6391: 0 +Line 6392: 1 +Line 6393: 0 +Line 6394: 0 +Line 6395: 0 +Line 6396: 1 +Line 6397: 1 +Line 6398: 1 +Line 6399: 1 +Line 6400: 0 +Line 6401: 0 +Line 6402: 0 +Line 6403: 1 +Line 6404: 0 +Line 6405: 0 +Line 6406: 0 +Line 6407: 1 +Line 6408: 1 +Line 6409: 0 +Line 6410: 0 +Line 6411: 1 +Line 6412: 0 +Line 6413: 1 +Line 6414: 0 +Line 6415: 0 +Line 6416: 1 +Line 6417: 1 +Line 6418: 1 +Line 6419: 1 +Line 6420: 1 +Line 6421: 1 +Line 6422: 1 +Line 6423: 0 +Line 6424: 1 +Line 6425: 0 +Line 6426: 0 +Line 6427: 0 +Line 6428: 0 +Line 6429: 1 +Line 6430: 1 +Line 6431: 1 +Line 6432: 0 +Line 6433: 0 +Line 6434: 0 +Line 6435: 1 +Line 6436: 0 +Line 6437: 0 +Line 6438: 1 +Line 6439: 0 +Line 6440: 1 +Line 6441: 0 +Line 6442: 1 +Line 6443: 1 +Line 6444: 0 +Line 6445: 0 +Line 6446: 0 +Line 6447: 0 +Line 6448: 1 +Line 6449: 1 +Line 6450: 1 +Line 6451: 1 +Line 6452: 1 +Line 6453: 1 +Line 6454: 1 +Line 6455: 0 +Line 6456: 1 +Line 6457: 0 +Line 6458: 0 +Line 6459: 0 +Line 6460: 0 +Line 6461: 0 +Line 6462: 0 +Line 6463: 0 +Line 6464: 0 +Line 6465: 0 +Line 6466: 0 +Line 6467: 1 +Line 6468: 0 +Line 6469: 0 +Line 6470: 1 +Line 6471: 1 +Line 6472: 1 +Line 6473: 1 +Line 6474: 0 +Line 6475: 1 +Line 6476: 0 +Line 6477: 0 +Line 6478: 1 +Line 6479: 0 +Line 6480: 1 +Line 6481: 1 +Line 6482: 1 +Line 6483: 1 +Line 6484: 1 +Line 6485: 1 +Line 6486: 1 +Line 6487: 0 +Line 6488: 0 +Line 6489: 1 +Line 6490: 1 +Line 6491: 1 +Line 6492: 1 +Line 6493: 0 +Line 6494: 0 +Line 6495: 1 +Line 6496: 0 +Line 6497: 0 +Line 6498: 0 +Line 6499: 1 +Line 6500: 0 +Line 6501: 1 +Line 6502: 0 +Line 6503: 0 +Line 6504: 1 +Line 6505: 1 +Line 6506: 1 +Line 6507: 1 +Line 6508: 1 +Line 6509: 0 +Line 6510: 0 +Line 6511: 1 +Line 6512: 1 +Line 6513: 1 +Line 6514: 1 +Line 6515: 1 +Line 6516: 1 +Line 6517: 1 +Line 6518: 1 +Line 6519: 0 +Line 6520: 0 +Line 6521: 1 +Line 6522: 1 +Line 6523: 1 +Line 6524: 0 +Line 6525: 0 +Line 6526: 1 +Line 6527: 0 +Line 6528: 0 +Line 6529: 0 +Line 6530: 0 +Line 6531: 1 +Line 6532: 0 +Line 6533: 1 +Line 6534: 1 +Line 6535: 0 +Line 6536: 0 +Line 6537: 0 +Line 6538: 1 +Line 6539: 0 +Line 6540: 0 +Line 6541: 1 +Line 6542: 0 +Line 6543: 0 +Line 6544: 1 +Line 6545: 1 +Line 6546: 1 +Line 6547: 1 +Line 6548: 1 +Line 6549: 1 +Line 6550: 1 +Line 6551: 0 +Line 6552: 0 +Line 6553: 1 +Line 6554: 1 +Line 6555: 0 +Line 6556: 1 +Line 6557: 1 +Line 6558: 0 +Line 6559: 0 +Line 6560: 0 +Line 6561: 0 +Line 6562: 0 +Line 6563: 1 +Line 6564: 0 +Line 6565: 1 +Line 6566: 1 +Line 6567: 1 +Line 6568: 0 +Line 6569: 1 +Line 6570: 0 +Line 6571: 1 +Line 6572: 0 +Line 6573: 1 +Line 6574: 0 +Line 6575: 0 +Line 6576: 1 +Line 6577: 1 +Line 6578: 1 +Line 6579: 1 +Line 6580: 1 +Line 6581: 1 +Line 6582: 1 +Line 6583: 0 +Line 6584: 0 +Line 6585: 1 +Line 6586: 1 +Line 6587: 0 +Line 6588: 0 +Line 6589: 1 +Line 6590: 1 +Line 6591: 0 +Line 6592: 0 +Line 6593: 0 +Line 6594: 0 +Line 6595: 1 +Line 6596: 1 +Line 6597: 0 +Line 6598: 0 +Line 6599: 0 +Line 6600: 1 +Line 6601: 0 +Line 6602: 0 +Line 6603: 0 +Line 6604: 1 +Line 6605: 0 +Line 6606: 0 +Line 6607: 0 +Line 6608: 1 +Line 6609: 1 +Line 6610: 1 +Line 6611: 1 +Line 6612: 1 +Line 6613: 1 +Line 6614: 1 +Line 6615: 0 +Line 6616: 0 +Line 6617: 1 +Line 6618: 1 +Line 6619: 0 +Line 6620: 0 +Line 6621: 0 +Line 6622: 0 +Line 6623: 1 +Line 6624: 0 +Line 6625: 0 +Line 6626: 0 +Line 6627: 1 +Line 6628: 1 +Line 6629: 0 +Line 6630: 0 +Line 6631: 1 +Line 6632: 1 +Line 6633: 1 +Line 6634: 0 +Line 6635: 0 +Line 6636: 0 +Line 6637: 0 +Line 6638: 0 +Line 6639: 0 +Line 6640: 1 +Line 6641: 1 +Line 6642: 1 +Line 6643: 1 +Line 6644: 1 +Line 6645: 1 +Line 6646: 1 +Line 6647: 0 +Line 6648: 0 +Line 6649: 1 +Line 6650: 0 +Line 6651: 1 +Line 6652: 1 +Line 6653: 1 +Line 6654: 0 +Line 6655: 1 +Line 6656: 0 +Line 6657: 0 +Line 6658: 0 +Line 6659: 1 +Line 6660: 1 +Line 6661: 0 +Line 6662: 1 +Line 6663: 0 +Line 6664: 1 +Line 6665: 1 +Line 6666: 1 +Line 6667: 1 +Line 6668: 1 +Line 6669: 0 +Line 6670: 1 +Line 6671: 0 +Line 6672: 1 +Line 6673: 1 +Line 6674: 1 +Line 6675: 1 +Line 6676: 1 +Line 6677: 1 +Line 6678: 1 +Line 6679: 0 +Line 6680: 0 +Line 6681: 1 +Line 6682: 0 +Line 6683: 1 +Line 6684: 1 +Line 6685: 0 +Line 6686: 0 +Line 6687: 1 +Line 6688: 0 +Line 6689: 0 +Line 6690: 0 +Line 6691: 1 +Line 6692: 1 +Line 6693: 1 +Line 6694: 0 +Line 6695: 0 +Line 6696: 0 +Line 6697: 0 +Line 6698: 1 +Line 6699: 1 +Line 6700: 1 +Line 6701: 0 +Line 6702: 0 +Line 6703: 0 +Line 6704: 1 +Line 6705: 1 +Line 6706: 1 +Line 6707: 1 +Line 6708: 1 +Line 6709: 1 +Line 6710: 1 +Line 6711: 0 +Line 6712: 0 +Line 6713: 1 +Line 6714: 0 +Line 6715: 1 +Line 6716: 0 +Line 6717: 1 +Line 6718: 1 +Line 6719: 0 +Line 6720: 0 +Line 6721: 0 +Line 6722: 0 +Line 6723: 1 +Line 6724: 1 +Line 6725: 1 +Line 6726: 0 +Line 6727: 1 +Line 6728: 0 +Line 6729: 1 +Line 6730: 1 +Line 6731: 1 +Line 6732: 0 +Line 6733: 1 +Line 6734: 1 +Line 6735: 1 +Line 6736: 1 +Line 6737: 1 +Line 6738: 1 +Line 6739: 1 +Line 6740: 1 +Line 6741: 1 +Line 6742: 1 +Line 6743: 0 +Line 6744: 0 +Line 6745: 1 +Line 6746: 0 +Line 6747: 1 +Line 6748: 0 +Line 6749: 0 +Line 6750: 1 +Line 6751: 1 +Line 6752: 0 +Line 6753: 0 +Line 6754: 0 +Line 6755: 1 +Line 6756: 1 +Line 6757: 1 +Line 6758: 1 +Line 6759: 0 +Line 6760: 1 +Line 6761: 0 +Line 6762: 1 +Line 6763: 1 +Line 6764: 1 +Line 6765: 0 +Line 6766: 0 +Line 6767: 1 +Line 6768: 1 +Line 6769: 1 +Line 6770: 1 +Line 6771: 1 +Line 6772: 1 +Line 6773: 1 +Line 6774: 1 +Line 6775: 0 +Line 6776: 0 +Line 6777: 1 +Line 6778: 0 +Line 6779: 1 +Line 6780: 0 +Line 6781: 0 +Line 6782: 0 +Line 6783: 0 +Line 6784: 0 +Line 6785: 0 +Line 6786: 0 +Line 6787: 1 +Line 6788: 1 +Line 6789: 1 +Line 6790: 1 +Line 6791: 1 +Line 6792: 1 +Line 6793: 1 +Line 6794: 1 +Line 6795: 1 +Line 6796: 1 +Line 6797: 1 +Line 6798: 0 +Line 6799: 0 +Line 6800: 1 +Line 6801: 1 +Line 6802: 1 +Line 6803: 1 +Line 6804: 1 +Line 6805: 1 +Line 6806: 1 +Line 6807: 0 +Line 6808: 0 +Line 6809: 1 +Line 6810: 0 +Line 6811: 0 +Line 6812: 1 +Line 6813: 1 +Line 6814: 1 +Line 6815: 1 +Line 6816: 0 +Line 6817: 0 +Line 6818: 1 +Line 6819: 0 +Line 6820: 0 +Line 6821: 0 +Line 6822: 0 +Line 6823: 1 +Line 6824: 0 +Line 6825: 1 +Line 6826: 0 +Line 6827: 0 +Line 6828: 0 +Line 6829: 0 +Line 6830: 0 +Line 6831: 0 +Line 6832: 1 +Line 6833: 1 +Line 6834: 1 +Line 6835: 1 +Line 6836: 1 +Line 6837: 1 +Line 6838: 1 +Line 6839: 0 +Line 6840: 0 +Line 6841: 1 +Line 6842: 0 +Line 6843: 0 +Line 6844: 1 +Line 6845: 1 +Line 6846: 1 +Line 6847: 0 +Line 6848: 0 +Line 6849: 0 +Line 6850: 1 +Line 6851: 0 +Line 6852: 0 +Line 6853: 0 +Line 6854: 1 +Line 6855: 0 +Line 6856: 1 +Line 6857: 0 +Line 6858: 0 +Line 6859: 0 +Line 6860: 0 +Line 6861: 1 +Line 6862: 0 +Line 6863: 1 +Line 6864: 1 +Line 6865: 1 +Line 6866: 1 +Line 6867: 1 +Line 6868: 1 +Line 6869: 1 +Line 6870: 1 +Line 6871: 0 +Line 6872: 0 +Line 6873: 1 +Line 6874: 0 +Line 6875: 0 +Line 6876: 1 +Line 6877: 1 +Line 6878: 0 +Line 6879: 1 +Line 6880: 0 +Line 6881: 0 +Line 6882: 1 +Line 6883: 0 +Line 6884: 0 +Line 6885: 0 +Line 6886: 1 +Line 6887: 1 +Line 6888: 1 +Line 6889: 1 +Line 6890: 0 +Line 6891: 0 +Line 6892: 1 +Line 6893: 0 +Line 6894: 1 +Line 6895: 0 +Line 6896: 1 +Line 6897: 1 +Line 6898: 1 +Line 6899: 1 +Line 6900: 1 +Line 6901: 1 +Line 6902: 1 +Line 6903: 0 +Line 6904: 0 +Line 6905: 1 +Line 6906: 0 +Line 6907: 0 +Line 6908: 1 +Line 6909: 1 +Line 6910: 0 +Line 6911: 1 +Line 6912: 0 +Line 6913: 0 +Line 6914: 1 +Line 6915: 0 +Line 6916: 0 +Line 6917: 1 +Line 6918: 0 +Line 6919: 1 +Line 6920: 0 +Line 6921: 0 +Line 6922: 0 +Line 6923: 0 +Line 6924: 1 +Line 6925: 1 +Line 6926: 1 +Line 6927: 1 +Line 6928: 1 +Line 6929: 1 +Line 6930: 1 +Line 6931: 1 +Line 6932: 1 +Line 6933: 1 +Line 6934: 1 +Line 6935: 0 +Line 6936: 0 +Line 6937: 1 +Line 6938: 0 +Line 6939: 0 +Line 6940: 1 +Line 6941: 1 +Line 6942: 1 +Line 6943: 0 +Line 6944: 0 +Line 6945: 0 +Line 6946: 1 +Line 6947: 0 +Line 6948: 0 +Line 6949: 1 +Line 6950: 1 +Line 6951: 0 +Line 6952: 0 +Line 6953: 1 +Line 6954: 0 +Line 6955: 1 +Line 6956: 0 +Line 6957: 0 +Line 6958: 1 +Line 6959: 1 +Line 6960: 1 +Line 6961: 1 +Line 6962: 1 +Line 6963: 1 +Line 6964: 1 +Line 6965: 1 +Line 6966: 1 +Line 6967: 0 +Line 6968: 0 +Line 6969: 1 +Line 6970: 0 +Line 6971: 0 +Line 6972: 1 +Line 6973: 1 +Line 6974: 1 +Line 6975: 1 +Line 6976: 0 +Line 6977: 0 +Line 6978: 1 +Line 6979: 0 +Line 6980: 0 +Line 6981: 1 +Line 6982: 1 +Line 6983: 1 +Line 6984: 1 +Line 6985: 0 +Line 6986: 0 +Line 6987: 1 +Line 6988: 0 +Line 6989: 1 +Line 6990: 1 +Line 6991: 0 +Line 6992: 1 +Line 6993: 1 +Line 6994: 1 +Line 6995: 1 +Line 6996: 1 +Line 6997: 1 +Line 6998: 1 +Line 6999: 0 +Line 7000: 0 +Line 7001: 1 +Line 7002: 0 +Line 7003: 1 +Line 7004: 0 +Line 7005: 0 +Line 7006: 0 +Line 7007: 0 +Line 7008: 0 +Line 7009: 0 +Line 7010: 1 +Line 7011: 0 +Line 7012: 1 +Line 7013: 0 +Line 7014: 0 +Line 7015: 0 +Line 7016: 1 +Line 7017: 1 +Line 7018: 0 +Line 7019: 1 +Line 7020: 1 +Line 7021: 0 +Line 7022: 0 +Line 7023: 0 +Line 7024: 1 +Line 7025: 1 +Line 7026: 1 +Line 7027: 1 +Line 7028: 1 +Line 7029: 1 +Line 7030: 1 +Line 7031: 0 +Line 7032: 0 +Line 7033: 1 +Line 7034: 0 +Line 7035: 1 +Line 7036: 0 +Line 7037: 0 +Line 7038: 1 +Line 7039: 1 +Line 7040: 0 +Line 7041: 0 +Line 7042: 1 +Line 7043: 0 +Line 7044: 1 +Line 7045: 0 +Line 7046: 1 +Line 7047: 0 +Line 7048: 0 +Line 7049: 0 +Line 7050: 0 +Line 7051: 1 +Line 7052: 0 +Line 7053: 1 +Line 7054: 1 +Line 7055: 1 +Line 7056: 1 +Line 7057: 1 +Line 7058: 1 +Line 7059: 1 +Line 7060: 1 +Line 7061: 1 +Line 7062: 1 +Line 7063: 0 +Line 7064: 0 +Line 7065: 1 +Line 7066: 0 +Line 7067: 1 +Line 7068: 0 +Line 7069: 1 +Line 7070: 1 +Line 7071: 0 +Line 7072: 0 +Line 7073: 0 +Line 7074: 1 +Line 7075: 0 +Line 7076: 1 +Line 7077: 0 +Line 7078: 1 +Line 7079: 1 +Line 7080: 0 +Line 7081: 1 +Line 7082: 0 +Line 7083: 1 +Line 7084: 0 +Line 7085: 1 +Line 7086: 0 +Line 7087: 1 +Line 7088: 1 +Line 7089: 1 +Line 7090: 1 +Line 7091: 1 +Line 7092: 1 +Line 7093: 1 +Line 7094: 1 +Line 7095: 0 +Line 7096: 0 +Line 7097: 1 +Line 7098: 0 +Line 7099: 1 +Line 7100: 1 +Line 7101: 0 +Line 7102: 0 +Line 7103: 1 +Line 7104: 0 +Line 7105: 0 +Line 7106: 1 +Line 7107: 0 +Line 7108: 1 +Line 7109: 1 +Line 7110: 0 +Line 7111: 0 +Line 7112: 1 +Line 7113: 0 +Line 7114: 0 +Line 7115: 0 +Line 7116: 1 +Line 7117: 1 +Line 7118: 1 +Line 7119: 1 +Line 7120: 1 +Line 7121: 1 +Line 7122: 1 +Line 7123: 1 +Line 7124: 1 +Line 7125: 1 +Line 7126: 1 +Line 7127: 0 +Line 7128: 0 +Line 7129: 1 +Line 7130: 0 +Line 7131: 1 +Line 7132: 1 +Line 7133: 1 +Line 7134: 0 +Line 7135: 1 +Line 7136: 0 +Line 7137: 0 +Line 7138: 1 +Line 7139: 0 +Line 7140: 1 +Line 7141: 1 +Line 7142: 0 +Line 7143: 1 +Line 7144: 1 +Line 7145: 1 +Line 7146: 0 +Line 7147: 0 +Line 7148: 0 +Line 7149: 1 +Line 7150: 1 +Line 7151: 1 +Line 7152: 1 +Line 7153: 1 +Line 7154: 1 +Line 7155: 1 +Line 7156: 1 +Line 7157: 1 +Line 7158: 1 +Line 7159: 0 +Line 7160: 0 +Line 7161: 1 +Line 7162: 1 +Line 7163: 0 +Line 7164: 0 +Line 7165: 0 +Line 7166: 0 +Line 7167: 1 +Line 7168: 0 +Line 7169: 0 +Line 7170: 1 +Line 7171: 0 +Line 7172: 1 +Line 7173: 1 +Line 7174: 1 +Line 7175: 0 +Line 7176: 1 +Line 7177: 1 +Line 7178: 1 +Line 7179: 1 +Line 7180: 1 +Line 7181: 0 +Line 7182: 1 +Line 7183: 1 +Line 7184: 1 +Line 7185: 1 +Line 7186: 1 +Line 7187: 1 +Line 7188: 1 +Line 7189: 1 +Line 7190: 1 +Line 7191: 0 +Line 7192: 0 +Line 7193: 1 +Line 7194: 1 +Line 7195: 0 +Line 7196: 0 +Line 7197: 1 +Line 7198: 1 +Line 7199: 0 +Line 7200: 0 +Line 7201: 0 +Line 7202: 1 +Line 7203: 1 +Line 7204: 0 +Line 7205: 0 +Line 7206: 0 +Line 7207: 0 +Line 7208: 0 +Line 7209: 0 +Line 7210: 1 +Line 7211: 0 +Line 7212: 1 +Line 7213: 0 +Line 7214: 1 +Line 7215: 1 +Line 7216: 1 +Line 7217: 1 +Line 7218: 1 +Line 7219: 1 +Line 7220: 1 +Line 7221: 1 +Line 7222: 1 +Line 7223: 0 +Line 7224: 0 +Line 7225: 1 +Line 7226: 1 +Line 7227: 0 +Line 7228: 1 +Line 7229: 1 +Line 7230: 0 +Line 7231: 0 +Line 7232: 0 +Line 7233: 0 +Line 7234: 1 +Line 7235: 1 +Line 7236: 0 +Line 7237: 0 +Line 7238: 0 +Line 7239: 1 +Line 7240: 0 +Line 7241: 1 +Line 7242: 0 +Line 7243: 1 +Line 7244: 0 +Line 7245: 1 +Line 7246: 1 +Line 7247: 0 +Line 7248: 1 +Line 7249: 1 +Line 7250: 1 +Line 7251: 1 +Line 7252: 1 +Line 7253: 1 +Line 7254: 1 +Line 7255: 0 +Line 7256: 0 +Line 7257: 1 +Line 7258: 1 +Line 7259: 1 +Line 7260: 0 +Line 7261: 0 +Line 7262: 1 +Line 7263: 0 +Line 7264: 0 +Line 7265: 0 +Line 7266: 1 +Line 7267: 1 +Line 7268: 0 +Line 7269: 0 +Line 7270: 1 +Line 7271: 0 +Line 7272: 0 +Line 7273: 1 +Line 7274: 1 +Line 7275: 1 +Line 7276: 1 +Line 7277: 1 +Line 7278: 0 +Line 7279: 1 +Line 7280: 1 +Line 7281: 1 +Line 7282: 1 +Line 7283: 1 +Line 7284: 1 +Line 7285: 1 +Line 7286: 1 +Line 7287: 0 +Line 7288: 0 +Line 7289: 1 +Line 7290: 1 +Line 7291: 1 +Line 7292: 1 +Line 7293: 0 +Line 7294: 0 +Line 7295: 1 +Line 7296: 0 +Line 7297: 0 +Line 7298: 1 +Line 7299: 1 +Line 7300: 0 +Line 7301: 0 +Line 7302: 1 +Line 7303: 1 +Line 7304: 1 +Line 7305: 0 +Line 7306: 0 +Line 7307: 1 +Line 7308: 1 +Line 7309: 1 +Line 7310: 1 +Line 7311: 1 +Line 7312: 1 +Line 7313: 1 +Line 7314: 1 +Line 7315: 1 +Line 7316: 1 +Line 7317: 1 +Line 7318: 1 +Line 7319: 0 +Line 7320: 1 +Line 7321: 0 +Line 7322: 0 +Line 7323: 0 +Line 7324: 0 +Line 7325: 0 +Line 7326: 0 +Line 7327: 0 +Line 7328: 0 +Line 7329: 0 +Line 7330: 1 +Line 7331: 1 +Line 7332: 0 +Line 7333: 1 +Line 7334: 0 +Line 7335: 0 +Line 7336: 1 +Line 7337: 0 +Line 7338: 1 +Line 7339: 1 +Line 7340: 1 +Line 7341: 1 +Line 7342: 0 +Line 7343: 0 +Line 7344: 1 +Line 7345: 1 +Line 7346: 1 +Line 7347: 1 +Line 7348: 1 +Line 7349: 1 +Line 7350: 1 +Line 7351: 0 +Line 7352: 1 +Line 7353: 0 +Line 7354: 0 +Line 7355: 0 +Line 7356: 0 +Line 7357: 1 +Line 7358: 1 +Line 7359: 1 +Line 7360: 0 +Line 7361: 0 +Line 7362: 1 +Line 7363: 1 +Line 7364: 0 +Line 7365: 1 +Line 7366: 0 +Line 7367: 1 +Line 7368: 1 +Line 7369: 1 +Line 7370: 0 +Line 7371: 1 +Line 7372: 0 +Line 7373: 0 +Line 7374: 1 +Line 7375: 0 +Line 7376: 1 +Line 7377: 1 +Line 7378: 1 +Line 7379: 1 +Line 7380: 1 +Line 7381: 1 +Line 7382: 1 +Line 7383: 0 +Line 7384: 1 +Line 7385: 0 +Line 7386: 0 +Line 7387: 0 +Line 7388: 1 +Line 7389: 1 +Line 7390: 1 +Line 7391: 1 +Line 7392: 0 +Line 7393: 0 +Line 7394: 1 +Line 7395: 1 +Line 7396: 0 +Line 7397: 1 +Line 7398: 1 +Line 7399: 0 +Line 7400: 1 +Line 7401: 1 +Line 7402: 1 +Line 7403: 0 +Line 7404: 0 +Line 7405: 0 +Line 7406: 1 +Line 7407: 0 +Line 7408: 1 +Line 7409: 1 +Line 7410: 1 +Line 7411: 1 +Line 7412: 1 +Line 7413: 1 +Line 7414: 1 +Line 7415: 0 +Line 7416: 1 +Line 7417: 0 +Line 7418: 0 +Line 7419: 1 +Line 7420: 1 +Line 7421: 0 +Line 7422: 0 +Line 7423: 0 +Line 7424: 0 +Line 7425: 0 +Line 7426: 1 +Line 7427: 1 +Line 7428: 0 +Line 7429: 1 +Line 7430: 1 +Line 7431: 1 +Line 7432: 1 +Line 7433: 1 +Line 7434: 1 +Line 7435: 0 +Line 7436: 1 +Line 7437: 1 +Line 7438: 0 +Line 7439: 0 +Line 7440: 1 +Line 7441: 1 +Line 7442: 1 +Line 7443: 1 +Line 7444: 1 +Line 7445: 1 +Line 7446: 1 +Line 7447: 0 +Line 7448: 1 +Line 7449: 0 +Line 7450: 1 +Line 7451: 0 +Line 7452: 0 +Line 7453: 0 +Line 7454: 0 +Line 7455: 1 +Line 7456: 0 +Line 7457: 0 +Line 7458: 1 +Line 7459: 1 +Line 7460: 1 +Line 7461: 0 +Line 7462: 0 +Line 7463: 0 +Line 7464: 1 +Line 7465: 1 +Line 7466: 1 +Line 7467: 0 +Line 7468: 1 +Line 7469: 1 +Line 7470: 1 +Line 7471: 1 +Line 7472: 1 +Line 7473: 1 +Line 7474: 1 +Line 7475: 1 +Line 7476: 1 +Line 7477: 1 +Line 7478: 1 +Line 7479: 0 +Line 7480: 1 +Line 7481: 0 +Line 7482: 1 +Line 7483: 0 +Line 7484: 1 +Line 7485: 0 +Line 7486: 1 +Line 7487: 1 +Line 7488: 0 +Line 7489: 0 +Line 7490: 1 +Line 7491: 1 +Line 7492: 1 +Line 7493: 0 +Line 7494: 0 +Line 7495: 1 +Line 7496: 1 +Line 7497: 1 +Line 7498: 1 +Line 7499: 0 +Line 7500: 1 +Line 7501: 0 +Line 7502: 1 +Line 7503: 0 +Line 7504: 1 +Line 7505: 1 +Line 7506: 1 +Line 7507: 1 +Line 7508: 1 +Line 7509: 1 +Line 7510: 1 +Line 7511: 0 +Line 7512: 1 +Line 7513: 0 +Line 7514: 1 +Line 7515: 1 +Line 7516: 0 +Line 7517: 1 +Line 7518: 0 +Line 7519: 1 +Line 7520: 0 +Line 7521: 0 +Line 7522: 1 +Line 7523: 1 +Line 7524: 1 +Line 7525: 0 +Line 7526: 1 +Line 7527: 0 +Line 7528: 1 +Line 7529: 1 +Line 7530: 0 +Line 7531: 1 +Line 7532: 1 +Line 7533: 1 +Line 7534: 1 +Line 7535: 0 +Line 7536: 1 +Line 7537: 1 +Line 7538: 1 +Line 7539: 1 +Line 7540: 1 +Line 7541: 1 +Line 7542: 1 +Line 7543: 0 +Line 7544: 1 +Line 7545: 0 +Line 7546: 1 +Line 7547: 1 +Line 7548: 1 +Line 7549: 1 +Line 7550: 1 +Line 7551: 1 +Line 7552: 0 +Line 7553: 0 +Line 7554: 1 +Line 7555: 1 +Line 7556: 1 +Line 7557: 0 +Line 7558: 1 +Line 7559: 1 +Line 7560: 1 +Line 7561: 1 +Line 7562: 0 +Line 7563: 0 +Line 7564: 1 +Line 7565: 0 +Line 7566: 1 +Line 7567: 0 +Line 7568: 1 +Line 7569: 1 +Line 7570: 1 +Line 7571: 1 +Line 7572: 1 +Line 7573: 1 +Line 7574: 1 +Line 7575: 0 +Line 7576: 1 +Line 7577: 1 +Line 7578: 0 +Line 7579: 0 +Line 7580: 1 +Line 7581: 0 +Line 7582: 1 +Line 7583: 0 +Line 7584: 0 +Line 7585: 0 +Line 7586: 1 +Line 7587: 1 +Line 7588: 1 +Line 7589: 1 +Line 7590: 0 +Line 7591: 0 +Line 7592: 1 +Line 7593: 0 +Line 7594: 1 +Line 7595: 0 +Line 7596: 1 +Line 7597: 1 +Line 7598: 0 +Line 7599: 1 +Line 7600: 1 +Line 7601: 1 +Line 7602: 1 +Line 7603: 1 +Line 7604: 1 +Line 7605: 1 +Line 7606: 1 +Line 7607: 0 +Line 7608: 1 +Line 7609: 1 +Line 7610: 0 +Line 7611: 1 +Line 7612: 0 +Line 7613: 1 +Line 7614: 0 +Line 7615: 1 +Line 7616: 0 +Line 7617: 0 +Line 7618: 1 +Line 7619: 1 +Line 7620: 1 +Line 7621: 1 +Line 7622: 0 +Line 7623: 1 +Line 7624: 1 +Line 7625: 0 +Line 7626: 0 +Line 7627: 0 +Line 7628: 1 +Line 7629: 0 +Line 7630: 0 +Line 7631: 1 +Line 7632: 1 +Line 7633: 1 +Line 7634: 1 +Line 7635: 1 +Line 7636: 1 +Line 7637: 1 +Line 7638: 1 +Line 7639: 0 +Line 7640: 1 +Line 7641: 1 +Line 7642: 1 +Line 7643: 0 +Line 7644: 0 +Line 7645: 0 +Line 7646: 0 +Line 7647: 1 +Line 7648: 0 +Line 7649: 0 +Line 7650: 1 +Line 7651: 1 +Line 7652: 1 +Line 7653: 1 +Line 7654: 1 +Line 7655: 0 +Line 7656: 0 +Line 7657: 1 +Line 7658: 0 +Line 7659: 1 +Line 7660: 1 +Line 7661: 0 +Line 7662: 1 +Line 7663: 1 +Line 7664: 1 +Line 7665: 1 +Line 7666: 1 +Line 7667: 1 +Line 7668: 1 +Line 7669: 1 +Line 7670: 1 +Line 7671: 0 +Line 7672: 1 +Line 7673: 1 +Line 7674: 1 +Line 7675: 0 +Line 7676: 1 +Line 7677: 1 +Line 7678: 0 +Line 7679: 1 +Line 7680: 0 +Line 7681: 0 +Line 7682: 1 +Line 7683: 1 +Line 7684: 1 +Line 7685: 1 +Line 7686: 1 +Line 7687: 1 +Line 7688: 0 +Line 7689: 0 +Line 7690: 1 +Line 7691: 0 +Line 7692: 0 +Line 7693: 1 +Line 7694: 0 +Line 7695: 0 +Line 7696: 1 +Line 7697: 1 +Line 7698: 1 +Line 7699: 1 +Line 7700: 1 +Line 7701: 1 +Line 7702: 1 +Line 7703: 0 +Line 7704: 1 +Line 7705: 1 +Line 7706: 1 +Line 7707: 1 +Line 7708: 1 +Line 7709: 0 +Line 7710: 0 +Line 7711: 1 +Line 7712: 0 +Line 7713: 0 +Line 7714: 1 +Line 7715: 1 +Line 7716: 1 +Line 7717: 1 +Line 7718: 1 +Line 7719: 1 +Line 7720: 1 +Line 7721: 1 +Line 7722: 1 +Line 7723: 0 +Line 7724: 0 +Line 7725: 1 +Line 7726: 0 +Line 7727: 0 +Line 7728: 1 +Line 7729: 1 +Line 7730: 1 +Line 7731: 1 +Line 7732: 1 +Line 7733: 1 +Line 7734: 1 +Line 7735: 1 +Line 7736: 0 +Line 7737: 0 +Line 7738: 0 +Line 7739: 0 +Line 7740: 0 +Line 7741: 1 +Line 7742: 1 +Line 7743: 0 +Line 7744: 0 +Line 7745: 1 +Line 7746: 0 +Line 7747: 0 +Line 7748: 0 +Line 7749: 0 +Line 7750: 0 +Line 7751: 0 +Line 7752: 1 +Line 7753: 0 +Line 7754: 0 +Line 7755: 1 +Line 7756: 1 +Line 7757: 0 +Line 7758: 1 +Line 7759: 1 +Line 7760: 1 +Line 7761: 1 +Line 7762: 1 +Line 7763: 1 +Line 7764: 1 +Line 7765: 1 +Line 7766: 1 +Line 7767: 1 +Line 7768: 0 +Line 7769: 0 +Line 7770: 0 +Line 7771: 1 +Line 7772: 0 +Line 7773: 0 +Line 7774: 1 +Line 7775: 1 +Line 7776: 0 +Line 7777: 1 +Line 7778: 0 +Line 7779: 0 +Line 7780: 0 +Line 7781: 0 +Line 7782: 0 +Line 7783: 1 +Line 7784: 0 +Line 7785: 1 +Line 7786: 0 +Line 7787: 0 +Line 7788: 0 +Line 7789: 1 +Line 7790: 1 +Line 7791: 1 +Line 7792: 1 +Line 7793: 1 +Line 7794: 1 +Line 7795: 1 +Line 7796: 1 +Line 7797: 1 +Line 7798: 1 +Line 7799: 1 +Line 7800: 0 +Line 7801: 0 +Line 7802: 1 +Line 7803: 0 +Line 7804: 0 +Line 7805: 0 +Line 7806: 0 +Line 7807: 0 +Line 7808: 0 +Line 7809: 1 +Line 7810: 0 +Line 7811: 0 +Line 7812: 0 +Line 7813: 0 +Line 7814: 0 +Line 7815: 1 +Line 7816: 1 +Line 7817: 1 +Line 7818: 1 +Line 7819: 0 +Line 7820: 1 +Line 7821: 0 +Line 7822: 1 +Line 7823: 0 +Line 7824: 1 +Line 7825: 1 +Line 7826: 1 +Line 7827: 1 +Line 7828: 1 +Line 7829: 1 +Line 7830: 1 +Line 7831: 1 +Line 7832: 0 +Line 7833: 0 +Line 7834: 1 +Line 7835: 0 +Line 7836: 1 +Line 7837: 1 +Line 7838: 1 +Line 7839: 0 +Line 7840: 0 +Line 7841: 1 +Line 7842: 0 +Line 7843: 0 +Line 7844: 0 +Line 7845: 0 +Line 7846: 1 +Line 7847: 0 +Line 7848: 1 +Line 7849: 0 +Line 7850: 0 +Line 7851: 0 +Line 7852: 0 +Line 7853: 0 +Line 7854: 1 +Line 7855: 0 +Line 7856: 1 +Line 7857: 1 +Line 7858: 1 +Line 7859: 1 +Line 7860: 1 +Line 7861: 1 +Line 7862: 1 +Line 7863: 1 +Line 7864: 0 +Line 7865: 0 +Line 7866: 1 +Line 7867: 1 +Line 7868: 1 +Line 7869: 0 +Line 7870: 1 +Line 7871: 1 +Line 7872: 0 +Line 7873: 1 +Line 7874: 0 +Line 7875: 0 +Line 7876: 0 +Line 7877: 0 +Line 7878: 1 +Line 7879: 1 +Line 7880: 0 +Line 7881: 0 +Line 7882: 0 +Line 7883: 1 +Line 7884: 0 +Line 7885: 0 +Line 7886: 0 +Line 7887: 0 +Line 7888: 1 +Line 7889: 1 +Line 7890: 1 +Line 7891: 1 +Line 7892: 1 +Line 7893: 1 +Line 7894: 1 +Line 7895: 1 +Line 7896: 0 +Line 7897: 1 +Line 7898: 0 +Line 7899: 0 +Line 7900: 1 +Line 7901: 0 +Line 7902: 1 +Line 7903: 0 +Line 7904: 0 +Line 7905: 1 +Line 7906: 0 +Line 7907: 0 +Line 7908: 0 +Line 7909: 0 +Line 7910: 1 +Line 7911: 1 +Line 7912: 1 +Line 7913: 0 +Line 7914: 0 +Line 7915: 1 +Line 7916: 0 +Line 7917: 0 +Line 7918: 1 +Line 7919: 1 +Line 7920: 1 +Line 7921: 1 +Line 7922: 1 +Line 7923: 1 +Line 7924: 1 +Line 7925: 1 +Line 7926: 1 +Line 7927: 1 +Line 7928: 0 +Line 7929: 1 +Line 7930: 0 +Line 7931: 1 +Line 7932: 1 +Line 7933: 0 +Line 7934: 0 +Line 7935: 0 +Line 7936: 0 +Line 7937: 1 +Line 7938: 0 +Line 7939: 0 +Line 7940: 0 +Line 7941: 1 +Line 7942: 0 +Line 7943: 0 +Line 7944: 0 +Line 7945: 0 +Line 7946: 0 +Line 7947: 0 +Line 7948: 1 +Line 7949: 0 +Line 7950: 1 +Line 7951: 1 +Line 7952: 1 +Line 7953: 1 +Line 7954: 1 +Line 7955: 1 +Line 7956: 1 +Line 7957: 1 +Line 7958: 1 +Line 7959: 1 +Line 7960: 0 +Line 7961: 1 +Line 7962: 1 +Line 7963: 0 +Line 7964: 0 +Line 7965: 1 +Line 7966: 1 +Line 7967: 1 +Line 7968: 0 +Line 7969: 1 +Line 7970: 0 +Line 7971: 0 +Line 7972: 0 +Line 7973: 1 +Line 7974: 0 +Line 7975: 0 +Line 7976: 0 +Line 7977: 1 +Line 7978: 1 +Line 7979: 1 +Line 7980: 1 +Line 7981: 0 +Line 7982: 0 +Line 7983: 0 +Line 7984: 1 +Line 7985: 1 +Line 7986: 1 +Line 7987: 1 +Line 7988: 1 +Line 7989: 1 +Line 7990: 1 +Line 7991: 1 +Line 7992: 0 +Line 7993: 1 +Line 7994: 1 +Line 7995: 1 +Line 7996: 0 +Line 7997: 1 +Line 7998: 0 +Line 7999: 1 +Line 8000: 0 +Line 8001: 1 +Line 8002: 0 +Line 8003: 0 +Line 8004: 0 +Line 8005: 1 +Line 8006: 0 +Line 8007: 0 +Line 8008: 1 +Line 8009: 1 +Line 8010: 0 +Line 8011: 1 +Line 8012: 1 +Line 8013: 0 +Line 8014: 1 +Line 8015: 1 +Line 8016: 1 +Line 8017: 1 +Line 8018: 1 +Line 8019: 1 +Line 8020: 1 +Line 8021: 1 +Line 8022: 1 +Line 8023: 1 +Line 8024: 1 +Line 8025: 0 +Line 8026: 0 +Line 8027: 0 +Line 8028: 0 +Line 8029: 1 +Line 8030: 0 +Line 8031: 0 +Line 8032: 0 +Line 8033: 1 +Line 8034: 0 +Line 8035: 0 +Line 8036: 0 +Line 8037: 1 +Line 8038: 0 +Line 8039: 1 +Line 8040: 0 +Line 8041: 0 +Line 8042: 1 +Line 8043: 1 +Line 8044: 0 +Line 8045: 0 +Line 8046: 1 +Line 8047: 0 +Line 8048: 1 +Line 8049: 1 +Line 8050: 1 +Line 8051: 1 +Line 8052: 1 +Line 8053: 1 +Line 8054: 1 +Line 8055: 1 +Line 8056: 1 +Line 8057: 0 +Line 8058: 0 +Line 8059: 1 +Line 8060: 0 +Line 8061: 1 +Line 8062: 0 +Line 8063: 0 +Line 8064: 0 +Line 8065: 1 +Line 8066: 0 +Line 8067: 0 +Line 8068: 0 +Line 8069: 1 +Line 8070: 0 +Line 8071: 1 +Line 8072: 0 +Line 8073: 1 +Line 8074: 1 +Line 8075: 1 +Line 8076: 1 +Line 8077: 1 +Line 8078: 0 +Line 8079: 1 +Line 8080: 1 +Line 8081: 1 +Line 8082: 1 +Line 8083: 1 +Line 8084: 1 +Line 8085: 1 +Line 8086: 1 +Line 8087: 1 +Line 8088: 1 +Line 8089: 0 +Line 8090: 1 +Line 8091: 0 +Line 8092: 0 +Line 8093: 0 +Line 8094: 1 +Line 8095: 1 +Line 8096: 0 +Line 8097: 1 +Line 8098: 0 +Line 8099: 0 +Line 8100: 0 +Line 8101: 1 +Line 8102: 0 +Line 8103: 1 +Line 8104: 1 +Line 8105: 0 +Line 8106: 1 +Line 8107: 1 +Line 8108: 1 +Line 8109: 1 +Line 8110: 0 +Line 8111: 1 +Line 8112: 1 +Line 8113: 1 +Line 8114: 1 +Line 8115: 1 +Line 8116: 1 +Line 8117: 1 +Line 8118: 1 +Line 8119: 1 +Line 8120: 1 +Line 8121: 0 +Line 8122: 1 +Line 8123: 1 +Line 8124: 0 +Line 8125: 0 +Line 8126: 1 +Line 8127: 0 +Line 8128: 0 +Line 8129: 1 +Line 8130: 0 +Line 8131: 0 +Line 8132: 0 +Line 8133: 1 +Line 8134: 0 +Line 8135: 1 +Line 8136: 1 +Line 8137: 1 +Line 8138: 1 +Line 8139: 1 +Line 8140: 0 +Line 8141: 0 +Line 8142: 1 +Line 8143: 0 +Line 8144: 1 +Line 8145: 1 +Line 8146: 1 +Line 8147: 1 +Line 8148: 1 +Line 8149: 1 +Line 8150: 1 +Line 8151: 1 +Line 8152: 1 +Line 8153: 1 +Line 8154: 0 +Line 8155: 0 +Line 8156: 0 +Line 8157: 0 +Line 8158: 1 +Line 8159: 0 +Line 8160: 0 +Line 8161: 1 +Line 8162: 0 +Line 8163: 0 +Line 8164: 0 +Line 8165: 1 +Line 8166: 1 +Line 8167: 0 +Line 8168: 0 +Line 8169: 0 +Line 8170: 0 +Line 8171: 1 +Line 8172: 1 +Line 8173: 0 +Line 8174: 1 +Line 8175: 1 +Line 8176: 1 +Line 8177: 1 +Line 8178: 1 +Line 8179: 1 +Line 8180: 1 +Line 8181: 1 +Line 8182: 1 +Line 8183: 1 +Line 8184: 1 +Line 8185: 1 +Line 8186: 0 +Line 8187: 1 +Line 8188: 0 +Line 8189: 0 +Line 8190: 0 +Line 8191: 1 +Line 8192: 0 +Line 8193: 1 +Line 8194: 0 +Line 8195: 0 +Line 8196: 0 +Line 8197: 1 +Line 8198: 1 +Line 8199: 0 +Line 8200: 0 +Line 8201: 0 +Line 8202: 1 +Line 8203: 1 +Line 8204: 1 +Line 8205: 0 +Line 8206: 0 +Line 8207: 0 +Line 8208: 1 +Line 8209: 1 +Line 8210: 1 +Line 8211: 1 +Line 8212: 1 +Line 8213: 1 +Line 8214: 1 +Line 8215: 1 +Line 8216: 1 +Line 8217: 1 +Line 8218: 1 +Line 8219: 0 +Line 8220: 0 +Line 8221: 0 +Line 8222: 0 +Line 8223: 1 +Line 8224: 0 +Line 8225: 1 +Line 8226: 0 +Line 8227: 0 +Line 8228: 0 +Line 8229: 1 +Line 8230: 1 +Line 8231: 0 +Line 8232: 0 +Line 8233: 1 +Line 8234: 0 +Line 8235: 0 +Line 8236: 1 +Line 8237: 0 +Line 8238: 1 +Line 8239: 0 +Line 8240: 1 +Line 8241: 1 +Line 8242: 1 +Line 8243: 1 +Line 8244: 1 +Line 8245: 1 +Line 8246: 1 +Line 8247: 1 +Line 8248: 1 +Line 8249: 1 +Line 8250: 1 +Line 8251: 1 +Line 8252: 0 +Line 8253: 0 +Line 8254: 0 +Line 8255: 1 +Line 8256: 0 +Line 8257: 1 +Line 8258: 0 +Line 8259: 0 +Line 8260: 0 +Line 8261: 1 +Line 8262: 1 +Line 8263: 0 +Line 8264: 0 +Line 8265: 1 +Line 8266: 0 +Line 8267: 1 +Line 8268: 0 +Line 8269: 0 +Line 8270: 0 +Line 8271: 0 +Line 8272: 0 +Line 8273: 0 +Line 8274: 0 +Line 8275: 0 +Line 8276: 0 +Line 8277: 0 +Line 8278: 0 +Line 8279: 0 +Line 8280: 0 +Line 8281: 0 +Line 8282: 0 +Line 8283: 0 +Line 8284: 0 +Line 8285: 0 +Line 8286: 0 +Line 8287: 0 +Line 8288: 0 +Line 8289: 1 +Line 8290: 0 +Line 8291: 0 +Line 8292: 0 +Line 8293: 1 +Line 8294: 1 +Line 8295: 0 +Line 8296: 0 +Line 8297: 1 +Line 8298: 0 +Line 8299: 0 +Line 8300: 1 +Line 8301: 0 +Line 8302: 1 +Line 8303: 0 +Line 8304: 0 +Line 8305: 0 +Line 8306: 0 +Line 8307: 0 +Line 8308: 0 +Line 8309: 0 +Line 8310: 0 +Line 8311: 0 +Line 8312: 0 +Line 8313: 0 +Line 8314: 0 +Line 8315: 0 +Line 8316: 1 +Line 8317: 1 +Line 8318: 1 +Line 8319: 1 +Line 8320: 0 +Line 8321: 1 +Line 8322: 0 +Line 8323: 0 +Line 8324: 0 +Line 8325: 1 +Line 8326: 1 +Line 8327: 0 +Line 8328: 0 +Line 8329: 0 +Line 8330: 1 +Line 8331: 1 +Line 8332: 1 +Line 8333: 0 +Line 8334: 0 +Line 8335: 0 +Line 8336: 0 +Line 8337: 0 +Line 8338: 0 +Line 8339: 0 +Line 8340: 0 +Line 8341: 0 +Line 8342: 0 +Line 8343: 0 +Line 8344: 0 +Line 8345: 0 +Line 8346: 0 +Line 8347: 1 +Line 8348: 1 +Line 8349: 1 +Line 8350: 1 +Line 8351: 1 +Line 8352: 0 +Line 8353: 1 +Line 8354: 0 +Line 8355: 0 +Line 8356: 0 +Line 8357: 1 +Line 8358: 1 +Line 8359: 0 +Line 8360: 0 +Line 8361: 0 +Line 8362: 0 +Line 8363: 1 +Line 8364: 1 +Line 8365: 0 +Line 8366: 1 +Line 8367: 1 +Line 8368: 0 +Line 8369: 0 +Line 8370: 0 +Line 8371: 0 +Line 8372: 0 +Line 8373: 0 +Line 8374: 0 +Line 8375: 0 +Line 8376: 0 +Line 8377: 0 +Line 8378: 1 +Line 8379: 0 +Line 8380: 1 +Line 8381: 1 +Line 8382: 1 +Line 8383: 1 +Line 8384: 0 +Line 8385: 1 +Line 8386: 0 +Line 8387: 0 +Line 8388: 0 +Line 8389: 1 +Line 8390: 0 +Line 8391: 1 +Line 8392: 1 +Line 8393: 1 +Line 8394: 1 +Line 8395: 1 +Line 8396: 0 +Line 8397: 0 +Line 8398: 1 +Line 8399: 0 +Line 8400: 0 +Line 8401: 0 +Line 8402: 0 +Line 8403: 0 +Line 8404: 0 +Line 8405: 0 +Line 8406: 0 +Line 8407: 0 +Line 8408: 0 +Line 8409: 0 +Line 8410: 1 +Line 8411: 1 +Line 8412: 1 +Line 8413: 1 +Line 8414: 1 +Line 8415: 0 +Line 8416: 0 +Line 8417: 1 +Line 8418: 0 +Line 8419: 0 +Line 8420: 0 +Line 8421: 1 +Line 8422: 0 +Line 8423: 1 +Line 8424: 1 +Line 8425: 0 +Line 8426: 1 +Line 8427: 1 +Line 8428: 1 +Line 8429: 1 +Line 8430: 0 +Line 8431: 1 +Line 8432: 0 +Line 8433: 0 +Line 8434: 0 +Line 8435: 0 +Line 8436: 0 +Line 8437: 0 +Line 8438: 0 +Line 8439: 0 +Line 8440: 0 +Line 8441: 1 +Line 8442: 0 +Line 8443: 0 +Line 8444: 1 +Line 8445: 1 +Line 8446: 1 +Line 8447: 0 +Line 8448: 0 +Line 8449: 1 +Line 8450: 0 +Line 8451: 0 +Line 8452: 0 +Line 8453: 1 +Line 8454: 0 +Line 8455: 1 +Line 8456: 0 +Line 8457: 1 +Line 8458: 1 +Line 8459: 1 +Line 8460: 1 +Line 8461: 1 +Line 8462: 0 +Line 8463: 1 +Line 8464: 0 +Line 8465: 0 +Line 8466: 0 +Line 8467: 0 +Line 8468: 0 +Line 8469: 0 +Line 8470: 0 +Line 8471: 0 +Line 8472: 0 +Line 8473: 1 +Line 8474: 0 +Line 8475: 1 +Line 8476: 1 +Line 8477: 1 +Line 8478: 0 +Line 8479: 1 +Line 8480: 0 +Line 8481: 1 +Line 8482: 0 +Line 8483: 0 +Line 8484: 0 +Line 8485: 1 +Line 8486: 0 +Line 8487: 1 +Line 8488: 0 +Line 8489: 0 +Line 8490: 1 +Line 8491: 1 +Line 8492: 0 +Line 8493: 0 +Line 8494: 1 +Line 8495: 0 +Line 8496: 0 +Line 8497: 0 +Line 8498: 0 +Line 8499: 0 +Line 8500: 0 +Line 8501: 0 +Line 8502: 0 +Line 8503: 0 +Line 8504: 0 +Line 8505: 1 +Line 8506: 1 +Line 8507: 0 +Line 8508: 1 +Line 8509: 1 +Line 8510: 0 +Line 8511: 0 +Line 8512: 0 +Line 8513: 1 +Line 8514: 0 +Line 8515: 0 +Line 8516: 0 +Line 8517: 1 +Line 8518: 0 +Line 8519: 0 +Line 8520: 1 +Line 8521: 1 +Line 8522: 0 +Line 8523: 1 +Line 8524: 1 +Line 8525: 0 +Line 8526: 1 +Line 8527: 1 +Line 8528: 0 +Line 8529: 0 +Line 8530: 0 +Line 8531: 0 +Line 8532: 0 +Line 8533: 0 +Line 8534: 0 +Line 8535: 0 +Line 8536: 0 +Line 8537: 1 +Line 8538: 1 +Line 8539: 1 +Line 8540: 1 +Line 8541: 1 +Line 8542: 0 +Line 8543: 0 +Line 8544: 0 +Line 8545: 1 +Line 8546: 0 +Line 8547: 0 +Line 8548: 0 +Line 8549: 1 +Line 8550: 0 +Line 8551: 0 +Line 8552: 0 +Line 8553: 1 +Line 8554: 1 +Line 8555: 1 +Line 8556: 1 +Line 8557: 0 +Line 8558: 0 +Line 8559: 0 +Line 8560: 0 +Line 8561: 0 +Line 8562: 0 +Line 8563: 0 +Line 8564: 0 +Line 8565: 0 +Line 8566: 0 +Line 8567: 0 +Line 8568: 1 +Line 8569: 0 +Line 8570: 0 +Line 8571: 0 +Line 8572: 1 +Line 8573: 0 +Line 8574: 1 +Line 8575: 1 +Line 8576: 0 +Line 8577: 1 +Line 8578: 0 +Line 8579: 0 +Line 8580: 0 +Line 8581: 1 +Line 8582: 0 +Line 8583: 0 +Line 8584: 0 +Line 8585: 0 +Line 8586: 0 +Line 8587: 0 +Line 8588: 1 +Line 8589: 0 +Line 8590: 1 +Line 8591: 1 +Line 8592: 0 +Line 8593: 0 +Line 8594: 0 +Line 8595: 0 +Line 8596: 0 +Line 8597: 0 +Line 8598: 0 +Line 8599: 0 +Line 8600: 1 +Line 8601: 0 +Line 8602: 0 +Line 8603: 1 +Line 8604: 1 +Line 8605: 0 +Line 8606: 0 +Line 8607: 1 +Line 8608: 0 +Line 8609: 1 +Line 8610: 0 +Line 8611: 0 +Line 8612: 0 +Line 8613: 0 +Line 8614: 1 +Line 8615: 1 +Line 8616: 1 +Line 8617: 0 +Line 8618: 0 +Line 8619: 1 +Line 8620: 0 +Line 8621: 0 +Line 8622: 1 +Line 8623: 1 +Line 8624: 0 +Line 8625: 0 +Line 8626: 0 +Line 8627: 0 +Line 8628: 0 +Line 8629: 0 +Line 8630: 0 +Line 8631: 0 +Line 8632: 1 +Line 8633: 0 +Line 8634: 1 +Line 8635: 0 +Line 8636: 1 +Line 8637: 0 +Line 8638: 0 +Line 8639: 0 +Line 8640: 0 +Line 8641: 1 +Line 8642: 0 +Line 8643: 0 +Line 8644: 0 +Line 8645: 0 +Line 8646: 1 +Line 8647: 1 +Line 8648: 0 +Line 8649: 0 +Line 8650: 0 +Line 8651: 1 +Line 8652: 0 +Line 8653: 0 +Line 8654: 0 +Line 8655: 0 +Line 8656: 0 +Line 8657: 0 +Line 8658: 0 +Line 8659: 0 +Line 8660: 0 +Line 8661: 0 +Line 8662: 0 +Line 8663: 0 +Line 8664: 1 +Line 8665: 0 +Line 8666: 1 +Line 8667: 1 +Line 8668: 0 +Line 8669: 1 +Line 8670: 1 +Line 8671: 0 +Line 8672: 0 +Line 8673: 1 +Line 8674: 0 +Line 8675: 0 +Line 8676: 0 +Line 8677: 0 +Line 8678: 1 +Line 8679: 0 +Line 8680: 1 +Line 8681: 0 +Line 8682: 0 +Line 8683: 0 +Line 8684: 0 +Line 8685: 0 +Line 8686: 1 +Line 8687: 0 +Line 8688: 0 +Line 8689: 0 +Line 8690: 0 +Line 8691: 0 +Line 8692: 0 +Line 8693: 0 +Line 8694: 0 +Line 8695: 0 +Line 8696: 1 +Line 8697: 1 +Line 8698: 0 +Line 8699: 0 +Line 8700: 0 +Line 8701: 1 +Line 8702: 0 +Line 8703: 1 +Line 8704: 0 +Line 8705: 1 +Line 8706: 0 +Line 8707: 0 +Line 8708: 0 +Line 8709: 0 +Line 8710: 0 +Line 8711: 1 +Line 8712: 1 +Line 8713: 1 +Line 8714: 1 +Line 8715: 0 +Line 8716: 1 +Line 8717: 0 +Line 8718: 1 +Line 8719: 0 +Line 8720: 0 +Line 8721: 0 +Line 8722: 0 +Line 8723: 0 +Line 8724: 0 +Line 8725: 0 +Line 8726: 0 +Line 8727: 0 +Line 8728: 1 +Line 8729: 1 +Line 8730: 0 +Line 8731: 1 +Line 8732: 0 +Line 8733: 0 +Line 8734: 1 +Line 8735: 0 +Line 8736: 0 +Line 8737: 1 +Line 8738: 0 +Line 8739: 0 +Line 8740: 0 +Line 8741: 0 +Line 8742: 0 +Line 8743: 1 +Line 8744: 0 +Line 8745: 1 +Line 8746: 0 +Line 8747: 0 +Line 8748: 0 +Line 8749: 1 +Line 8750: 1 +Line 8751: 1 +Line 8752: 0 +Line 8753: 0 +Line 8754: 0 +Line 8755: 0 +Line 8756: 0 +Line 8757: 0 +Line 8758: 0 +Line 8759: 0 +Line 8760: 1 +Line 8761: 1 +Line 8762: 1 +Line 8763: 0 +Line 8764: 0 +Line 8765: 0 +Line 8766: 0 +Line 8767: 0 +Line 8768: 0 +Line 8769: 1 +Line 8770: 0 +Line 8771: 0 +Line 8772: 0 +Line 8773: 0 +Line 8774: 0 +Line 8775: 0 +Line 8776: 1 +Line 8777: 0 +Line 8778: 0 +Line 8779: 1 +Line 8780: 1 +Line 8781: 0 +Line 8782: 1 +Line 8783: 1 +Line 8784: 0 +Line 8785: 0 +Line 8786: 0 +Line 8787: 0 +Line 8788: 0 +Line 8789: 0 +Line 8790: 0 +Line 8791: 0 +Line 8792: 1 +Line 8793: 1 +Line 8794: 1 +Line 8795: 0 +Line 8796: 1 +Line 8797: 1 +Line 8798: 0 +Line 8799: 1 +Line 8800: 0 +Line 8801: 0 +Line 8802: 1 +Line 8803: 1 +Line 8804: 1 +Line 8805: 1 +Line 8806: 1 +Line 8807: 1 +Line 8808: 1 +Line 8809: 1 +Line 8810: 1 +Line 8811: 0 +Line 8812: 0 +Line 8813: 1 +Line 8814: 0 +Line 8815: 0 +Line 8816: 0 +Line 8817: 0 +Line 8818: 0 +Line 8819: 0 +Line 8820: 0 +Line 8821: 0 +Line 8822: 0 +Line 8823: 0 +Line 8824: 1 +Line 8825: 1 +Line 8826: 1 +Line 8827: 1 +Line 8828: 1 +Line 8829: 0 +Line 8830: 1 +Line 8831: 0 +Line 8832: 0 +Line 8833: 0 +Line 8834: 1 +Line 8835: 1 +Line 8836: 1 +Line 8837: 1 +Line 8838: 1 +Line 8839: 1 +Line 8840: 0 +Line 8841: 0 +Line 8842: 1 +Line 8843: 0 +Line 8844: 0 +Line 8845: 1 +Line 8846: 0 +Line 8847: 0 +Line 8848: 0 +Line 8849: 0 +Line 8850: 0 +Line 8851: 0 +Line 8852: 0 +Line 8853: 0 +Line 8854: 0 +Line 8855: 1 +Line 8856: 0 +Line 8857: 0 +Line 8858: 0 +Line 8859: 0 +Line 8860: 0 +Line 8861: 1 +Line 8862: 1 +Line 8863: 1 +Line 8864: 0 +Line 8865: 0 +Line 8866: 1 +Line 8867: 1 +Line 8868: 1 +Line 8869: 1 +Line 8870: 1 +Line 8871: 0 +Line 8872: 0 +Line 8873: 1 +Line 8874: 0 +Line 8875: 1 +Line 8876: 1 +Line 8877: 0 +Line 8878: 1 +Line 8879: 1 +Line 8880: 0 +Line 8881: 0 +Line 8882: 0 +Line 8883: 0 +Line 8884: 0 +Line 8885: 0 +Line 8886: 0 +Line 8887: 1 +Line 8888: 0 +Line 8889: 0 +Line 8890: 0 +Line 8891: 1 +Line 8892: 0 +Line 8893: 0 +Line 8894: 1 +Line 8895: 1 +Line 8896: 0 +Line 8897: 0 +Line 8898: 1 +Line 8899: 1 +Line 8900: 1 +Line 8901: 1 +Line 8902: 0 +Line 8903: 1 +Line 8904: 1 +Line 8905: 0 +Line 8906: 0 +Line 8907: 0 +Line 8908: 1 +Line 8909: 0 +Line 8910: 0 +Line 8911: 1 +Line 8912: 0 +Line 8913: 0 +Line 8914: 0 +Line 8915: 0 +Line 8916: 0 +Line 8917: 0 +Line 8918: 0 +Line 8919: 1 +Line 8920: 0 +Line 8921: 0 +Line 8922: 0 +Line 8923: 1 +Line 8924: 1 +Line 8925: 1 +Line 8926: 1 +Line 8927: 1 +Line 8928: 0 +Line 8929: 0 +Line 8930: 1 +Line 8931: 1 +Line 8932: 1 +Line 8933: 1 +Line 8934: 0 +Line 8935: 0 +Line 8936: 1 +Line 8937: 0 +Line 8938: 1 +Line 8939: 0 +Line 8940: 1 +Line 8941: 1 +Line 8942: 0 +Line 8943: 1 +Line 8944: 0 +Line 8945: 0 +Line 8946: 0 +Line 8947: 0 +Line 8948: 0 +Line 8949: 0 +Line 8950: 0 +Line 8951: 1 +Line 8952: 0 +Line 8953: 0 +Line 8954: 1 +Line 8955: 0 +Line 8956: 1 +Line 8957: 0 +Line 8958: 1 +Line 8959: 1 +Line 8960: 0 +Line 8961: 0 +Line 8962: 1 +Line 8963: 1 +Line 8964: 1 +Line 8965: 0 +Line 8966: 1 +Line 8967: 1 +Line 8968: 1 +Line 8969: 1 +Line 8970: 0 +Line 8971: 0 +Line 8972: 1 +Line 8973: 0 +Line 8974: 1 +Line 8975: 0 +Line 8976: 0 +Line 8977: 0 +Line 8978: 0 +Line 8979: 0 +Line 8980: 0 +Line 8981: 0 +Line 8982: 0 +Line 8983: 1 +Line 8984: 0 +Line 8985: 0 +Line 8986: 1 +Line 8987: 1 +Line 8988: 0 +Line 8989: 1 +Line 8990: 1 +Line 8991: 0 +Line 8992: 0 +Line 8993: 0 +Line 8994: 1 +Line 8995: 1 +Line 8996: 1 +Line 8997: 0 +Line 8998: 1 +Line 8999: 0 +Line 9000: 1 +Line 9001: 1 +Line 9002: 0 +Line 9003: 1 +Line 9004: 1 +Line 9005: 1 +Line 9006: 1 +Line 9007: 0 +Line 9008: 0 +Line 9009: 0 +Line 9010: 0 +Line 9011: 0 +Line 9012: 0 +Line 9013: 0 +Line 9014: 0 +Line 9015: 1 +Line 9016: 0 +Line 9017: 1 +Line 9018: 0 +Line 9019: 0 +Line 9020: 0 +Line 9021: 0 +Line 9022: 0 +Line 9023: 1 +Line 9024: 0 +Line 9025: 0 +Line 9026: 1 +Line 9027: 1 +Line 9028: 1 +Line 9029: 0 +Line 9030: 0 +Line 9031: 1 +Line 9032: 1 +Line 9033: 1 +Line 9034: 1 +Line 9035: 0 +Line 9036: 1 +Line 9037: 0 +Line 9038: 1 +Line 9039: 0 +Line 9040: 0 +Line 9041: 0 +Line 9042: 0 +Line 9043: 0 +Line 9044: 0 +Line 9045: 0 +Line 9046: 0 +Line 9047: 1 +Line 9048: 0 +Line 9049: 1 +Line 9050: 0 +Line 9051: 0 +Line 9052: 1 +Line 9053: 0 +Line 9054: 1 +Line 9055: 1 +Line 9056: 0 +Line 9057: 0 +Line 9058: 1 +Line 9059: 1 +Line 9060: 1 +Line 9061: 0 +Line 9062: 0 +Line 9063: 0 +Line 9064: 1 +Line 9065: 1 +Line 9066: 1 +Line 9067: 0 +Line 9068: 1 +Line 9069: 1 +Line 9070: 1 +Line 9071: 1 +Line 9072: 0 +Line 9073: 0 +Line 9074: 0 +Line 9075: 0 +Line 9076: 0 +Line 9077: 0 +Line 9078: 0 +Line 9079: 1 +Line 9080: 0 +Line 9081: 1 +Line 9082: 0 +Line 9083: 1 +Line 9084: 0 +Line 9085: 1 +Line 9086: 0 +Line 9087: 1 +Line 9088: 0 +Line 9089: 0 +Line 9090: 1 +Line 9091: 1 +Line 9092: 0 +Line 9093: 1 +Line 9094: 1 +Line 9095: 1 +Line 9096: 1 +Line 9097: 1 +Line 9098: 1 +Line 9099: 0 +Line 9100: 1 +Line 9101: 1 +Line 9102: 0 +Line 9103: 0 +Line 9104: 0 +Line 9105: 0 +Line 9106: 0 +Line 9107: 0 +Line 9108: 0 +Line 9109: 0 +Line 9110: 0 +Line 9111: 1 +Line 9112: 0 +Line 9113: 1 +Line 9114: 0 +Line 9115: 1 +Line 9116: 1 +Line 9117: 1 +Line 9118: 1 +Line 9119: 1 +Line 9120: 0 +Line 9121: 0 +Line 9122: 1 +Line 9123: 1 +Line 9124: 0 +Line 9125: 1 +Line 9126: 1 +Line 9127: 0 +Line 9128: 1 +Line 9129: 1 +Line 9130: 1 +Line 9131: 0 +Line 9132: 0 +Line 9133: 0 +Line 9134: 1 +Line 9135: 0 +Line 9136: 0 +Line 9137: 0 +Line 9138: 0 +Line 9139: 0 +Line 9140: 0 +Line 9141: 0 +Line 9142: 0 +Line 9143: 1 +Line 9144: 0 +Line 9145: 1 +Line 9146: 1 +Line 9147: 0 +Line 9148: 1 +Line 9149: 0 +Line 9150: 0 +Line 9151: 0 +Line 9152: 0 +Line 9153: 0 +Line 9154: 1 +Line 9155: 1 +Line 9156: 0 +Line 9157: 1 +Line 9158: 0 +Line 9159: 1 +Line 9160: 1 +Line 9161: 1 +Line 9162: 0 +Line 9163: 1 +Line 9164: 0 +Line 9165: 0 +Line 9166: 1 +Line 9167: 0 +Line 9168: 0 +Line 9169: 0 +Line 9170: 0 +Line 9171: 0 +Line 9172: 0 +Line 9173: 0 +Line 9174: 0 +Line 9175: 1 +Line 9176: 0 +Line 9177: 1 +Line 9178: 1 +Line 9179: 1 +Line 9180: 0 +Line 9181: 0 +Line 9182: 0 +Line 9183: 1 +Line 9184: 0 +Line 9185: 0 +Line 9186: 1 +Line 9187: 1 +Line 9188: 0 +Line 9189: 1 +Line 9190: 0 +Line 9191: 0 +Line 9192: 1 +Line 9193: 0 +Line 9194: 1 +Line 9195: 1 +Line 9196: 1 +Line 9197: 0 +Line 9198: 1 +Line 9199: 1 +Line 9200: 0 +Line 9201: 0 +Line 9202: 0 +Line 9203: 0 +Line 9204: 0 +Line 9205: 0 +Line 9206: 0 +Line 9207: 1 +Line 9208: 0 +Line 9209: 1 +Line 9210: 1 +Line 9211: 1 +Line 9212: 1 +Line 9213: 0 +Line 9214: 0 +Line 9215: 1 +Line 9216: 0 +Line 9217: 0 +Line 9218: 1 +Line 9219: 1 +Line 9220: 0 +Line 9221: 0 +Line 9222: 1 +Line 9223: 1 +Line 9224: 1 +Line 9225: 0 +Line 9226: 0 +Line 9227: 1 +Line 9228: 1 +Line 9229: 1 +Line 9230: 1 +Line 9231: 1 +Line 9232: 0 +Line 9233: 0 +Line 9234: 0 +Line 9235: 0 +Line 9236: 0 +Line 9237: 0 +Line 9238: 0 +Line 9239: 1 +Line 9240: 1 +Line 9241: 0 +Line 9242: 0 +Line 9243: 0 +Line 9244: 0 +Line 9245: 0 +Line 9246: 0 +Line 9247: 0 +Line 9248: 0 +Line 9249: 0 +Line 9250: 1 +Line 9251: 1 +Line 9252: 0 +Line 9253: 0 +Line 9254: 1 +Line 9255: 0 +Line 9256: 0 +Line 9257: 1 +Line 9258: 1 +Line 9259: 1 +Line 9260: 1 +Line 9261: 1 +Line 9262: 0 +Line 9263: 1 +Line 9264: 0 +Line 9265: 0 +Line 9266: 0 +Line 9267: 0 +Line 9268: 0 +Line 9269: 0 +Line 9270: 0 +Line 9271: 1 +Line 9272: 1 +Line 9273: 0 +Line 9274: 0 +Line 9275: 0 +Line 9276: 0 +Line 9277: 1 +Line 9278: 1 +Line 9279: 1 +Line 9280: 0 +Line 9281: 0 +Line 9282: 1 +Line 9283: 1 +Line 9284: 0 +Line 9285: 0 +Line 9286: 0 +Line 9287: 1 +Line 9288: 0 +Line 9289: 1 +Line 9290: 0 +Line 9291: 1 +Line 9292: 0 +Line 9293: 1 +Line 9294: 1 +Line 9295: 0 +Line 9296: 0 +Line 9297: 0 +Line 9298: 0 +Line 9299: 0 +Line 9300: 0 +Line 9301: 0 +Line 9302: 0 +Line 9303: 1 +Line 9304: 1 +Line 9305: 0 +Line 9306: 0 +Line 9307: 0 +Line 9308: 1 +Line 9309: 1 +Line 9310: 1 +Line 9311: 0 +Line 9312: 0 +Line 9313: 0 +Line 9314: 1 +Line 9315: 1 +Line 9316: 0 +Line 9317: 0 +Line 9318: 0 +Line 9319: 0 +Line 9320: 0 +Line 9321: 0 +Line 9322: 1 +Line 9323: 0 +Line 9324: 1 +Line 9325: 0 +Line 9326: 1 +Line 9327: 1 +Line 9328: 0 +Line 9329: 0 +Line 9330: 0 +Line 9331: 0 +Line 9332: 0 +Line 9333: 0 +Line 9334: 0 +Line 9335: 1 +Line 9336: 1 +Line 9337: 0 +Line 9338: 0 +Line 9339: 1 +Line 9340: 0 +Line 9341: 1 +Line 9342: 0 +Line 9343: 0 +Line 9344: 0 +Line 9345: 0 +Line 9346: 1 +Line 9347: 0 +Line 9348: 1 +Line 9349: 1 +Line 9350: 1 +Line 9351: 0 +Line 9352: 1 +Line 9353: 1 +Line 9354: 1 +Line 9355: 1 +Line 9356: 1 +Line 9357: 0 +Line 9358: 1 +Line 9359: 1 +Line 9360: 0 +Line 9361: 0 +Line 9362: 0 +Line 9363: 0 +Line 9364: 0 +Line 9365: 0 +Line 9366: 0 +Line 9367: 1 +Line 9368: 1 +Line 9369: 0 +Line 9370: 0 +Line 9371: 1 +Line 9372: 1 +Line 9373: 0 +Line 9374: 1 +Line 9375: 0 +Line 9376: 0 +Line 9377: 0 +Line 9378: 1 +Line 9379: 0 +Line 9380: 1 +Line 9381: 1 +Line 9382: 0 +Line 9383: 1 +Line 9384: 1 +Line 9385: 1 +Line 9386: 0 +Line 9387: 0 +Line 9388: 0 +Line 9389: 1 +Line 9390: 1 +Line 9391: 1 +Line 9392: 0 +Line 9393: 0 +Line 9394: 0 +Line 9395: 0 +Line 9396: 0 +Line 9397: 0 +Line 9398: 0 +Line 9399: 1 +Line 9400: 1 +Line 9401: 0 +Line 9402: 0 +Line 9403: 1 +Line 9404: 1 +Line 9405: 1 +Line 9406: 1 +Line 9407: 1 +Line 9408: 0 +Line 9409: 0 +Line 9410: 1 +Line 9411: 0 +Line 9412: 1 +Line 9413: 1 +Line 9414: 0 +Line 9415: 0 +Line 9416: 1 +Line 9417: 0 +Line 9418: 0 +Line 9419: 0 +Line 9420: 1 +Line 9421: 1 +Line 9422: 1 +Line 9423: 1 +Line 9424: 0 +Line 9425: 0 +Line 9426: 0 +Line 9427: 0 +Line 9428: 0 +Line 9429: 0 +Line 9430: 0 +Line 9431: 1 +Line 9432: 1 +Line 9433: 0 +Line 9434: 1 +Line 9435: 0 +Line 9436: 0 +Line 9437: 0 +Line 9438: 1 +Line 9439: 1 +Line 9440: 0 +Line 9441: 0 +Line 9442: 1 +Line 9443: 0 +Line 9444: 1 +Line 9445: 0 +Line 9446: 1 +Line 9447: 1 +Line 9448: 0 +Line 9449: 1 +Line 9450: 0 +Line 9451: 1 +Line 9452: 0 +Line 9453: 1 +Line 9454: 0 +Line 9455: 1 +Line 9456: 0 +Line 9457: 0 +Line 9458: 0 +Line 9459: 0 +Line 9460: 0 +Line 9461: 0 +Line 9462: 0 +Line 9463: 1 +Line 9464: 1 +Line 9465: 0 +Line 9466: 1 +Line 9467: 0 +Line 9468: 0 +Line 9469: 1 +Line 9470: 1 +Line 9471: 1 +Line 9472: 0 +Line 9473: 0 +Line 9474: 1 +Line 9475: 0 +Line 9476: 1 +Line 9477: 0 +Line 9478: 1 +Line 9479: 0 +Line 9480: 0 +Line 9481: 0 +Line 9482: 0 +Line 9483: 1 +Line 9484: 0 +Line 9485: 1 +Line 9486: 1 +Line 9487: 1 +Line 9488: 0 +Line 9489: 0 +Line 9490: 0 +Line 9491: 0 +Line 9492: 0 +Line 9493: 0 +Line 9494: 0 +Line 9495: 1 +Line 9496: 1 +Line 9497: 0 +Line 9498: 1 +Line 9499: 0 +Line 9500: 1 +Line 9501: 0 +Line 9502: 1 +Line 9503: 0 +Line 9504: 0 +Line 9505: 0 +Line 9506: 1 +Line 9507: 0 +Line 9508: 1 +Line 9509: 0 +Line 9510: 0 +Line 9511: 0 +Line 9512: 1 +Line 9513: 1 +Line 9514: 0 +Line 9515: 1 +Line 9516: 1 +Line 9517: 0 +Line 9518: 0 +Line 9519: 0 +Line 9520: 0 +Line 9521: 0 +Line 9522: 0 +Line 9523: 0 +Line 9524: 0 +Line 9525: 0 +Line 9526: 0 +Line 9527: 1 +Line 9528: 1 +Line 9529: 0 +Line 9530: 1 +Line 9531: 0 +Line 9532: 1 +Line 9533: 1 +Line 9534: 0 +Line 9535: 1 +Line 9536: 0 +Line 9537: 0 +Line 9538: 1 +Line 9539: 0 +Line 9540: 0 +Line 9541: 1 +Line 9542: 1 +Line 9543: 1 +Line 9544: 1 +Line 9545: 0 +Line 9546: 0 +Line 9547: 1 +Line 9548: 0 +Line 9549: 1 +Line 9550: 1 +Line 9551: 0 +Line 9552: 0 +Line 9553: 0 +Line 9554: 0 +Line 9555: 0 +Line 9556: 0 +Line 9557: 0 +Line 9558: 0 +Line 9559: 1 +Line 9560: 1 +Line 9561: 0 +Line 9562: 1 +Line 9563: 1 +Line 9564: 0 +Line 9565: 0 +Line 9566: 0 +Line 9567: 0 +Line 9568: 0 +Line 9569: 0 +Line 9570: 1 +Line 9571: 0 +Line 9572: 0 +Line 9573: 1 +Line 9574: 1 +Line 9575: 0 +Line 9576: 0 +Line 9577: 1 +Line 9578: 0 +Line 9579: 1 +Line 9580: 0 +Line 9581: 0 +Line 9582: 1 +Line 9583: 1 +Line 9584: 0 +Line 9585: 0 +Line 9586: 0 +Line 9587: 0 +Line 9588: 0 +Line 9589: 0 +Line 9590: 0 +Line 9591: 1 +Line 9592: 1 +Line 9593: 0 +Line 9594: 1 +Line 9595: 1 +Line 9596: 0 +Line 9597: 0 +Line 9598: 0 +Line 9599: 1 +Line 9600: 0 +Line 9601: 0 +Line 9602: 1 +Line 9603: 0 +Line 9604: 0 +Line 9605: 1 +Line 9606: 0 +Line 9607: 1 +Line 9608: 0 +Line 9609: 0 +Line 9610: 0 +Line 9611: 0 +Line 9612: 1 +Line 9613: 1 +Line 9614: 1 +Line 9615: 1 +Line 9616: 0 +Line 9617: 0 +Line 9618: 0 +Line 9619: 0 +Line 9620: 0 +Line 9621: 0 +Line 9622: 0 +Line 9623: 1 +Line 9624: 1 +Line 9625: 0 +Line 9626: 1 +Line 9627: 1 +Line 9628: 0 +Line 9629: 0 +Line 9630: 1 +Line 9631: 0 +Line 9632: 0 +Line 9633: 0 +Line 9634: 1 +Line 9635: 0 +Line 9636: 0 +Line 9637: 0 +Line 9638: 1 +Line 9639: 1 +Line 9640: 1 +Line 9641: 1 +Line 9642: 0 +Line 9643: 0 +Line 9644: 1 +Line 9645: 0 +Line 9646: 1 +Line 9647: 0 +Line 9648: 0 +Line 9649: 0 +Line 9650: 0 +Line 9651: 0 +Line 9652: 0 +Line 9653: 0 +Line 9654: 0 +Line 9655: 1 +Line 9656: 1 +Line 9657: 0 +Line 9658: 1 +Line 9659: 1 +Line 9660: 0 +Line 9661: 0 +Line 9662: 1 +Line 9663: 1 +Line 9664: 0 +Line 9665: 0 +Line 9666: 1 +Line 9667: 0 +Line 9668: 0 +Line 9669: 0 +Line 9670: 1 +Line 9671: 0 +Line 9672: 1 +Line 9673: 0 +Line 9674: 0 +Line 9675: 0 +Line 9676: 0 +Line 9677: 1 +Line 9678: 0 +Line 9679: 1 +Line 9680: 0 +Line 9681: 0 +Line 9682: 0 +Line 9683: 0 +Line 9684: 0 +Line 9685: 0 +Line 9686: 0 +Line 9687: 1 +Line 9688: 1 +Line 9689: 0 +Line 9690: 1 +Line 9691: 1 +Line 9692: 0 +Line 9693: 0 +Line 9694: 1 +Line 9695: 1 +Line 9696: 0 +Line 9697: 0 +Line 9698: 1 +Line 9699: 0 +Line 9700: 0 +Line 9701: 0 +Line 9702: 0 +Line 9703: 1 +Line 9704: 0 +Line 9705: 1 +Line 9706: 0 +Line 9707: 0 +Line 9708: 0 +Line 9709: 0 +Line 9710: 0 +Line 9711: 0 +Line 9712: 0 +Line 9713: 0 +Line 9714: 0 +Line 9715: 0 +Line 9716: 0 +Line 9717: 0 +Line 9718: 0 +Line 9719: 1 +Line 9720: 1 +Line 9721: 0 +Line 9722: 1 +Line 9723: 1 +Line 9724: 0 +Line 9725: 0 +Line 9726: 1 +Line 9727: 0 +Line 9728: 0 +Line 9729: 0 +Line 9730: 0 +Line 9731: 1 +Line 9732: 1 +Line 9733: 1 +Line 9734: 1 +Line 9735: 1 +Line 9736: 1 +Line 9737: 1 +Line 9738: 1 +Line 9739: 1 +Line 9740: 1 +Line 9741: 1 +Line 9742: 0 +Line 9743: 0 +Line 9744: 0 +Line 9745: 0 +Line 9746: 0 +Line 9747: 0 +Line 9748: 0 +Line 9749: 0 +Line 9750: 0 +Line 9751: 1 +Line 9752: 1 +Line 9753: 0 +Line 9754: 1 +Line 9755: 1 +Line 9756: 0 +Line 9757: 0 +Line 9758: 0 +Line 9759: 1 +Line 9760: 0 +Line 9761: 0 +Line 9762: 0 +Line 9763: 1 +Line 9764: 1 +Line 9765: 1 +Line 9766: 1 +Line 9767: 0 +Line 9768: 1 +Line 9769: 0 +Line 9770: 1 +Line 9771: 1 +Line 9772: 1 +Line 9773: 0 +Line 9774: 0 +Line 9775: 1 +Line 9776: 0 +Line 9777: 0 +Line 9778: 0 +Line 9779: 0 +Line 9780: 0 +Line 9781: 0 +Line 9782: 0 +Line 9783: 1 +Line 9784: 1 +Line 9785: 0 +Line 9786: 1 +Line 9787: 1 +Line 9788: 0 +Line 9789: 0 +Line 9790: 0 +Line 9791: 0 +Line 9792: 0 +Line 9793: 0 +Line 9794: 0 +Line 9795: 1 +Line 9796: 1 +Line 9797: 1 +Line 9798: 0 +Line 9799: 1 +Line 9800: 0 +Line 9801: 1 +Line 9802: 1 +Line 9803: 1 +Line 9804: 0 +Line 9805: 1 +Line 9806: 1 +Line 9807: 1 +Line 9808: 0 +Line 9809: 0 +Line 9810: 0 +Line 9811: 0 +Line 9812: 0 +Line 9813: 0 +Line 9814: 0 +Line 9815: 1 +Line 9816: 1 +Line 9817: 0 +Line 9818: 1 +Line 9819: 0 +Line 9820: 1 +Line 9821: 1 +Line 9822: 0 +Line 9823: 1 +Line 9824: 0 +Line 9825: 0 +Line 9826: 0 +Line 9827: 1 +Line 9828: 1 +Line 9829: 1 +Line 9830: 0 +Line 9831: 0 +Line 9832: 0 +Line 9833: 0 +Line 9834: 1 +Line 9835: 1 +Line 9836: 1 +Line 9837: 0 +Line 9838: 0 +Line 9839: 0 +Line 9840: 0 +Line 9841: 0 +Line 9842: 0 +Line 9843: 0 +Line 9844: 0 +Line 9845: 0 +Line 9846: 0 +Line 9847: 1 +Line 9848: 1 +Line 9849: 0 +Line 9850: 1 +Line 9851: 0 +Line 9852: 1 +Line 9853: 0 +Line 9854: 1 +Line 9855: 0 +Line 9856: 0 +Line 9857: 0 +Line 9858: 0 +Line 9859: 1 +Line 9860: 1 +Line 9861: 0 +Line 9862: 1 +Line 9863: 0 +Line 9864: 1 +Line 9865: 1 +Line 9866: 1 +Line 9867: 1 +Line 9868: 1 +Line 9869: 0 +Line 9870: 1 +Line 9871: 0 +Line 9872: 0 +Line 9873: 0 +Line 9874: 0 +Line 9875: 0 +Line 9876: 0 +Line 9877: 0 +Line 9878: 0 +Line 9879: 1 +Line 9880: 1 +Line 9881: 0 +Line 9882: 1 +Line 9883: 0 +Line 9884: 0 +Line 9885: 1 +Line 9886: 1 +Line 9887: 1 +Line 9888: 0 +Line 9889: 0 +Line 9890: 0 +Line 9891: 1 +Line 9892: 1 +Line 9893: 0 +Line 9894: 0 +Line 9895: 1 +Line 9896: 1 +Line 9897: 1 +Line 9898: 0 +Line 9899: 0 +Line 9900: 0 +Line 9901: 0 +Line 9902: 0 +Line 9903: 0 +Line 9904: 0 +Line 9905: 0 +Line 9906: 0 +Line 9907: 0 +Line 9908: 0 +Line 9909: 0 +Line 9910: 0 +Line 9911: 1 +Line 9912: 1 +Line 9913: 0 +Line 9914: 1 +Line 9915: 0 +Line 9916: 0 +Line 9917: 0 +Line 9918: 1 +Line 9919: 1 +Line 9920: 0 +Line 9921: 0 +Line 9922: 0 +Line 9923: 1 +Line 9924: 1 +Line 9925: 0 +Line 9926: 0 +Line 9927: 0 +Line 9928: 1 +Line 9929: 0 +Line 9930: 0 +Line 9931: 0 +Line 9932: 1 +Line 9933: 0 +Line 9934: 0 +Line 9935: 0 +Line 9936: 0 +Line 9937: 0 +Line 9938: 0 +Line 9939: 0 +Line 9940: 0 +Line 9941: 0 +Line 9942: 0 +Line 9943: 1 +Line 9944: 1 +Line 9945: 0 +Line 9946: 0 +Line 9947: 1 +Line 9948: 1 +Line 9949: 1 +Line 9950: 1 +Line 9951: 1 +Line 9952: 0 +Line 9953: 0 +Line 9954: 0 +Line 9955: 1 +Line 9956: 0 +Line 9957: 1 +Line 9958: 1 +Line 9959: 1 +Line 9960: 0 +Line 9961: 1 +Line 9962: 0 +Line 9963: 1 +Line 9964: 0 +Line 9965: 1 +Line 9966: 0 +Line 9967: 0 +Line 9968: 0 +Line 9969: 0 +Line 9970: 0 +Line 9971: 0 +Line 9972: 0 +Line 9973: 0 +Line 9974: 0 +Line 9975: 1 +Line 9976: 1 +Line 9977: 0 +Line 9978: 0 +Line 9979: 1 +Line 9980: 1 +Line 9981: 0 +Line 9982: 1 +Line 9983: 0 +Line 9984: 0 +Line 9985: 0 +Line 9986: 0 +Line 9987: 1 +Line 9988: 0 +Line 9989: 1 +Line 9990: 1 +Line 9991: 0 +Line 9992: 0 +Line 9993: 0 +Line 9994: 1 +Line 9995: 0 +Line 9996: 0 +Line 9997: 1 +Line 9998: 0 +Line 9999: 0 +Line 10000: 0 +Line 10001: 0 +Line 10002: 0 +Line 10003: 0 +Line 10004: 0 +Line 10005: 0 +Line 10006: 0 +Line 10007: 1 +Line 10008: 1 +Line 10009: 0 +Line 10010: 0 +Line 10011: 1 +Line 10012: 0 +Line 10013: 1 +Line 10014: 0 +Line 10015: 0 +Line 10016: 0 +Line 10017: 0 +Line 10018: 0 +Line 10019: 1 +Line 10020: 0 +Line 10021: 1 +Line 10022: 0 +Line 10023: 0 +Line 10024: 1 +Line 10025: 1 +Line 10026: 1 +Line 10027: 1 +Line 10028: 1 +Line 10029: 0 +Line 10030: 0 +Line 10031: 1 +Line 10032: 0 +Line 10033: 0 +Line 10034: 0 +Line 10035: 0 +Line 10036: 0 +Line 10037: 0 +Line 10038: 0 +Line 10039: 1 +Line 10040: 1 +Line 10041: 0 +Line 10042: 0 +Line 10043: 0 +Line 10044: 1 +Line 10045: 1 +Line 10046: 1 +Line 10047: 0 +Line 10048: 0 +Line 10049: 0 +Line 10050: 0 +Line 10051: 1 +Line 10052: 0 +Line 10053: 0 +Line 10054: 1 +Line 10055: 1 +Line 10056: 1 +Line 10057: 1 +Line 10058: 0 +Line 10059: 1 +Line 10060: 0 +Line 10061: 0 +Line 10062: 1 +Line 10063: 0 +Line 10064: 0 +Line 10065: 0 +Line 10066: 0 +Line 10067: 0 +Line 10068: 0 +Line 10069: 0 +Line 10070: 0 +Line 10071: 1 +Line 10072: 1 +Line 10073: 0 +Line 10074: 0 +Line 10075: 0 +Line 10076: 0 +Line 10077: 1 +Line 10078: 1 +Line 10079: 1 +Line 10080: 0 +Line 10081: 0 +Line 10082: 0 +Line 10083: 1 +Line 10084: 0 +Line 10085: 0 +Line 10086: 1 +Line 10087: 0 +Line 10088: 1 +Line 10089: 0 +Line 10090: 1 +Line 10091: 1 +Line 10092: 0 +Line 10093: 0 +Line 10094: 0 +Line 10095: 0 +Line 10096: 0 +Line 10097: 0 +Line 10098: 0 +Line 10099: 0 +Line 10100: 0 +Line 10101: 0 +Line 10102: 0 +Line 10103: 1 +Line 10104: 1 +Line 10105: 0 +Line 10106: 0 +Line 10107: 0 +Line 10108: 0 +Line 10109: 0 +Line 10110: 0 +Line 10111: 0 +Line 10112: 0 +Line 10113: 0 +Line 10114: 0 +Line 10115: 1 +Line 10116: 0 +Line 10117: 0 +Line 10118: 0 +Line 10119: 1 +Line 10120: 1 +Line 10121: 0 +Line 10122: 0 +Line 10123: 1 +Line 10124: 0 +Line 10125: 0 +Line 10126: 1 +Line 10127: 1 +Line 10128: 0 +Line 10129: 0 +Line 10130: 0 +Line 10131: 0 +Line 10132: 0 +Line 10133: 0 +Line 10134: 0 +Line 10135: 1 +Line 10136: 0 +Line 10137: 1 +Line 10138: 1 +Line 10139: 1 +Line 10140: 1 +Line 10141: 0 +Line 10142: 0 +Line 10143: 1 +Line 10144: 0 +Line 10145: 0 +Line 10146: 0 +Line 10147: 1 +Line 10148: 0 +Line 10149: 0 +Line 10150: 0 +Line 10151: 0 +Line 10152: 0 +Line 10153: 1 +Line 10154: 1 +Line 10155: 1 +Line 10156: 1 +Line 10157: 1 +Line 10158: 0 +Line 10159: 1 +Line 10160: 0 +Line 10161: 0 +Line 10162: 0 +Line 10163: 0 +Line 10164: 0 +Line 10165: 0 +Line 10166: 0 +Line 10167: 1 +Line 10168: 0 +Line 10169: 1 +Line 10170: 1 +Line 10171: 1 +Line 10172: 0 +Line 10173: 0 +Line 10174: 0 +Line 10175: 1 +Line 10176: 0 +Line 10177: 0 +Line 10178: 0 +Line 10179: 0 +Line 10180: 1 +Line 10181: 1 +Line 10182: 1 +Line 10183: 1 +Line 10184: 0 +Line 10185: 1 +Line 10186: 1 +Line 10187: 0 +Line 10188: 1 +Line 10189: 1 +Line 10190: 0 +Line 10191: 1 +Line 10192: 0 +Line 10193: 0 +Line 10194: 0 +Line 10195: 0 +Line 10196: 0 +Line 10197: 0 +Line 10198: 0 +Line 10199: 1 +Line 10200: 0 +Line 10201: 1 +Line 10202: 1 +Line 10203: 0 +Line 10204: 1 +Line 10205: 0 +Line 10206: 0 +Line 10207: 0 +Line 10208: 0 +Line 10209: 0 +Line 10210: 0 +Line 10211: 0 +Line 10212: 1 +Line 10213: 1 +Line 10214: 1 +Line 10215: 0 +Line 10216: 0 +Line 10217: 1 +Line 10218: 1 +Line 10219: 0 +Line 10220: 0 +Line 10221: 0 +Line 10222: 1 +Line 10223: 1 +Line 10224: 0 +Line 10225: 0 +Line 10226: 0 +Line 10227: 0 +Line 10228: 0 +Line 10229: 0 +Line 10230: 0 +Line 10231: 1 +Line 10232: 0 +Line 10233: 1 +Line 10234: 0 +Line 10235: 1 +Line 10236: 1 +Line 10237: 1 +Line 10238: 1 +Line 10239: 1 +Line 10240: 0 +Line 10241: 0 +Line 10242: 0 +Line 10243: 0 +Line 10244: 1 +Line 10245: 1 +Line 10246: 0 +Line 10247: 1 +Line 10248: 0 +Line 10249: 1 +Line 10250: 1 +Line 10251: 0 +Line 10252: 0 +Line 10253: 0 +Line 10254: 0 +Line 10255: 0 +Line 10256: 0 +Line 10257: 0 +Line 10258: 0 +Line 10259: 0 +Line 10260: 0 +Line 10261: 0 +Line 10262: 0 +Line 10263: 1 +Line 10264: 0 +Line 10265: 1 +Line 10266: 0 +Line 10267: 1 +Line 10268: 0 +Line 10269: 1 +Line 10270: 0 +Line 10271: 1 +Line 10272: 0 +Line 10273: 0 +Line 10274: 0 +Line 10275: 0 +Line 10276: 1 +Line 10277: 1 +Line 10278: 0 +Line 10279: 0 +Line 10280: 0 +Line 10281: 1 +Line 10282: 1 +Line 10283: 0 +Line 10284: 0 +Line 10285: 1 +Line 10286: 0 +Line 10287: 1 +Line 10288: 0 +Line 10289: 0 +Line 10290: 0 +Line 10291: 0 +Line 10292: 0 +Line 10293: 0 +Line 10294: 0 +Line 10295: 1 +Line 10296: 0 +Line 10297: 1 +Line 10298: 0 +Line 10299: 0 +Line 10300: 1 +Line 10301: 0 +Line 10302: 1 +Line 10303: 1 +Line 10304: 0 +Line 10305: 0 +Line 10306: 0 +Line 10307: 0 +Line 10308: 1 +Line 10309: 0 +Line 10310: 1 +Line 10311: 1 +Line 10312: 0 +Line 10313: 1 +Line 10314: 1 +Line 10315: 1 +Line 10316: 0 +Line 10317: 0 +Line 10318: 0 +Line 10319: 1 +Line 10320: 0 +Line 10321: 0 +Line 10322: 0 +Line 10323: 0 +Line 10324: 0 +Line 10325: 0 +Line 10326: 0 +Line 10327: 1 +Line 10328: 0 +Line 10329: 1 +Line 10330: 0 +Line 10331: 0 +Line 10332: 0 +Line 10333: 0 +Line 10334: 0 +Line 10335: 1 +Line 10336: 0 +Line 10337: 0 +Line 10338: 0 +Line 10339: 0 +Line 10340: 1 +Line 10341: 0 +Line 10342: 1 +Line 10343: 0 +Line 10344: 1 +Line 10345: 0 +Line 10346: 0 +Line 10347: 0 +Line 10348: 0 +Line 10349: 1 +Line 10350: 0 +Line 10351: 1 +Line 10352: 0 +Line 10353: 0 +Line 10354: 0 +Line 10355: 0 +Line 10356: 0 +Line 10357: 0 +Line 10358: 0 +Line 10359: 1 +Line 10360: 0 +Line 10361: 0 +Line 10362: 1 +Line 10363: 1 +Line 10364: 0 +Line 10365: 1 +Line 10366: 1 +Line 10367: 0 +Line 10368: 0 +Line 10369: 0 +Line 10370: 0 +Line 10371: 0 +Line 10372: 1 +Line 10373: 0 +Line 10374: 0 +Line 10375: 1 +Line 10376: 1 +Line 10377: 0 +Line 10378: 1 +Line 10379: 0 +Line 10380: 0 +Line 10381: 0 +Line 10382: 1 +Line 10383: 0 +Line 10384: 0 +Line 10385: 0 +Line 10386: 0 +Line 10387: 0 +Line 10388: 0 +Line 10389: 0 +Line 10390: 0 +Line 10391: 1 +Line 10392: 0 +Line 10393: 0 +Line 10394: 1 +Line 10395: 0 +Line 10396: 1 +Line 10397: 0 +Line 10398: 1 +Line 10399: 1 +Line 10400: 0 +Line 10401: 0 +Line 10402: 0 +Line 10403: 0 +Line 10404: 1 +Line 10405: 0 +Line 10406: 0 +Line 10407: 0 +Line 10408: 1 +Line 10409: 1 +Line 10410: 0 +Line 10411: 0 +Line 10412: 0 +Line 10413: 1 +Line 10414: 1 +Line 10415: 0 +Line 10416: 0 +Line 10417: 0 +Line 10418: 0 +Line 10419: 0 +Line 10420: 0 +Line 10421: 0 +Line 10422: 0 +Line 10423: 1 +Line 10424: 0 +Line 10425: 0 +Line 10426: 0 +Line 10427: 1 +Line 10428: 1 +Line 10429: 1 +Line 10430: 1 +Line 10431: 1 +Line 10432: 0 +Line 10433: 0 +Line 10434: 0 +Line 10435: 0 +Line 10436: 0 +Line 10437: 1 +Line 10438: 1 +Line 10439: 1 +Line 10440: 1 +Line 10441: 1 +Line 10442: 1 +Line 10443: 1 +Line 10444: 0 +Line 10445: 1 +Line 10446: 0 +Line 10447: 0 +Line 10448: 0 +Line 10449: 0 +Line 10450: 0 +Line 10451: 0 +Line 10452: 0 +Line 10453: 0 +Line 10454: 0 +Line 10455: 1 +Line 10456: 0 +Line 10457: 0 +Line 10458: 0 +Line 10459: 1 +Line 10460: 0 +Line 10461: 0 +Line 10462: 1 +Line 10463: 1 +Line 10464: 0 +Line 10465: 0 +Line 10466: 0 +Line 10467: 0 +Line 10468: 0 +Line 10469: 1 +Line 10470: 1 +Line 10471: 1 +Line 10472: 0 +Line 10473: 0 +Line 10474: 1 +Line 10475: 0 +Line 10476: 1 +Line 10477: 0 +Line 10478: 1 +Line 10479: 1 +Line 10480: 0 +Line 10481: 0 +Line 10482: 0 +Line 10483: 0 +Line 10484: 0 +Line 10485: 0 +Line 10486: 0 +Line 10487: 1 +Line 10488: 0 +Line 10489: 0 +Line 10490: 0 +Line 10491: 0 +Line 10492: 0 +Line 10493: 1 +Line 10494: 1 +Line 10495: 1 +Line 10496: 0 +Line 10497: 0 +Line 10498: 0 +Line 10499: 0 +Line 10500: 0 +Line 10501: 1 +Line 10502: 1 +Line 10503: 0 +Line 10504: 0 +Line 10505: 1 +Line 10506: 1 +Line 10507: 0 +Line 10508: 1 +Line 10509: 0 +Line 10510: 1 +Line 10511: 1 +Line 10512: 0 +Line 10513: 0 +Line 10514: 0 +Line 10515: 0 +Line 10516: 0 +Line 10517: 0 +Line 10518: 0 +Line 10519: 0 +Line 10520: 1 +Line 10521: 1 +Line 10522: 1 +Line 10523: 1 +Line 10524: 1 +Line 10525: 0 +Line 10526: 1 +Line 10527: 0 +Line 10528: 0 +Line 10529: 0 +Line 10530: 0 +Line 10531: 0 +Line 10532: 0 +Line 10533: 1 +Line 10534: 0 +Line 10535: 1 +Line 10536: 1 +Line 10537: 0 +Line 10538: 1 +Line 10539: 1 +Line 10540: 0 +Line 10541: 1 +Line 10542: 0 +Line 10543: 0 +Line 10544: 0 +Line 10545: 0 +Line 10546: 0 +Line 10547: 0 +Line 10548: 0 +Line 10549: 0 +Line 10550: 0 +Line 10551: 0 +Line 10552: 1 +Line 10553: 1 +Line 10554: 1 +Line 10555: 0 +Line 10556: 1 +Line 10557: 1 +Line 10558: 0 +Line 10559: 1 +Line 10560: 0 +Line 10561: 0 +Line 10562: 0 +Line 10563: 0 +Line 10564: 0 +Line 10565: 1 +Line 10566: 0 +Line 10567: 1 +Line 10568: 0 +Line 10569: 0 +Line 10570: 0 +Line 10571: 0 +Line 10572: 1 +Line 10573: 0 +Line 10574: 0 +Line 10575: 0 +Line 10576: 0 +Line 10577: 0 +Line 10578: 0 +Line 10579: 0 +Line 10580: 0 +Line 10581: 0 +Line 10582: 0 +Line 10583: 0 +Line 10584: 1 +Line 10585: 1 +Line 10586: 1 +Line 10587: 0 +Line 10588: 0 +Line 10589: 0 +Line 10590: 0 +Line 10591: 0 +Line 10592: 0 +Line 10593: 0 +Line 10594: 0 +Line 10595: 0 +Line 10596: 0 +Line 10597: 1 +Line 10598: 0 +Line 10599: 0 +Line 10600: 0 +Line 10601: 1 +Line 10602: 1 +Line 10603: 0 +Line 10604: 0 +Line 10605: 1 +Line 10606: 0 +Line 10607: 1 +Line 10608: 0 +Line 10609: 0 +Line 10610: 0 +Line 10611: 0 +Line 10612: 0 +Line 10613: 0 +Line 10614: 0 +Line 10615: 0 +Line 10616: 1 +Line 10617: 1 +Line 10618: 0 +Line 10619: 1 +Line 10620: 0 +Line 10621: 0 +Line 10622: 1 +Line 10623: 0 +Line 10624: 0 +Line 10625: 0 +Line 10626: 0 +Line 10627: 0 +Line 10628: 0 +Line 10629: 0 +Line 10630: 1 +Line 10631: 1 +Line 10632: 1 +Line 10633: 1 +Line 10634: 0 +Line 10635: 0 +Line 10636: 1 +Line 10637: 1 +Line 10638: 0 +Line 10639: 1 +Line 10640: 0 +Line 10641: 0 +Line 10642: 0 +Line 10643: 0 +Line 10644: 0 +Line 10645: 0 +Line 10646: 0 +Line 10647: 0 +Line 10648: 1 +Line 10649: 1 +Line 10650: 0 +Line 10651: 0 +Line 10652: 0 +Line 10653: 1 +Line 10654: 0 +Line 10655: 1 +Line 10656: 0 +Line 10657: 0 +Line 10658: 0 +Line 10659: 0 +Line 10660: 0 +Line 10661: 0 +Line 10662: 1 +Line 10663: 1 +Line 10664: 0 +Line 10665: 0 +Line 10666: 1 +Line 10667: 1 +Line 10668: 1 +Line 10669: 1 +Line 10670: 1 +Line 10671: 1 +Line 10672: 0 +Line 10673: 0 +Line 10674: 0 +Line 10675: 0 +Line 10676: 0 +Line 10677: 0 +Line 10678: 0 +Line 10679: 0 +Line 10680: 1 +Line 10681: 0 +Line 10682: 1 +Line 10683: 1 +Line 10684: 0 +Line 10685: 1 +Line 10686: 1 +Line 10687: 0 +Line 10688: 0 +Line 10689: 0 +Line 10690: 0 +Line 10691: 0 +Line 10692: 0 +Line 10693: 0 +Line 10694: 1 +Line 10695: 0 +Line 10696: 1 +Line 10697: 0 +Line 10698: 1 +Line 10699: 1 +Line 10700: 1 +Line 10701: 1 +Line 10702: 0 +Line 10703: 0 +Line 10704: 0 +Line 10705: 0 +Line 10706: 0 +Line 10707: 0 +Line 10708: 0 +Line 10709: 0 +Line 10710: 0 +Line 10711: 0 +Line 10712: 1 +Line 10713: 0 +Line 10714: 1 +Line 10715: 0 +Line 10716: 1 +Line 10717: 0 +Line 10718: 0 +Line 10719: 0 +Line 10720: 0 +Line 10721: 0 +Line 10722: 0 +Line 10723: 0 +Line 10724: 0 +Line 10725: 0 +Line 10726: 1 +Line 10727: 0 +Line 10728: 0 +Line 10729: 1 +Line 10730: 0 +Line 10731: 0 +Line 10732: 0 +Line 10733: 1 +Line 10734: 0 +Line 10735: 0 +Line 10736: 0 +Line 10737: 0 +Line 10738: 0 +Line 10739: 0 +Line 10740: 0 +Line 10741: 0 +Line 10742: 0 +Line 10743: 0 +Line 10744: 1 +Line 10745: 0 +Line 10746: 0 +Line 10747: 1 +Line 10748: 1 +Line 10749: 0 +Line 10750: 0 +Line 10751: 1 +Line 10752: 0 +Line 10753: 0 +Line 10754: 0 +Line 10755: 0 +Line 10756: 0 +Line 10757: 0 +Line 10758: 0 +Line 10759: 1 +Line 10760: 1 +Line 10761: 1 +Line 10762: 0 +Line 10763: 1 +Line 10764: 0 +Line 10765: 1 +Line 10766: 1 +Line 10767: 1 +Line 10768: 0 +Line 10769: 0 +Line 10770: 0 +Line 10771: 0 +Line 10772: 0 +Line 10773: 0 +Line 10774: 0 +Line 10775: 0 +Line 10776: 1 +Line 10777: 0 +Line 10778: 0 +Line 10779: 0 +Line 10780: 1 +Line 10781: 0 +Line 10782: 1 +Line 10783: 1 +Line 10784: 0 +Line 10785: 0 +Line 10786: 0 +Line 10787: 0 +Line 10788: 0 +Line 10789: 0 +Line 10790: 0 +Line 10791: 1 +Line 10792: 0 +Line 10793: 1 +Line 10794: 1 +Line 10795: 1 +Line 10796: 0 +Line 10797: 1 +Line 10798: 0 +Line 10799: 0 +Line 10800: 0 +Line 10801: 0 +Line 10802: 0 +Line 10803: 0 +Line 10804: 0 +Line 10805: 0 +Line 10806: 0 +Line 10807: 0 +Line 10808: 0 +Line 10809: 1 +Line 10810: 1 +Line 10811: 1 +Line 10812: 1 +Line 10813: 1 +Line 10814: 0 +Line 10815: 0 +Line 10816: 0 +Line 10817: 0 +Line 10818: 0 +Line 10819: 0 +Line 10820: 0 +Line 10821: 0 +Line 10822: 0 +Line 10823: 1 +Line 10824: 0 +Line 10825: 0 +Line 10826: 0 +Line 10827: 1 +Line 10828: 1 +Line 10829: 1 +Line 10830: 0 +Line 10831: 1 +Line 10832: 0 +Line 10833: 0 +Line 10834: 0 +Line 10835: 0 +Line 10836: 0 +Line 10837: 0 +Line 10838: 0 +Line 10839: 0 +Line 10840: 0 +Line 10841: 1 +Line 10842: 1 +Line 10843: 0 +Line 10844: 1 +Line 10845: 1 +Line 10846: 0 +Line 10847: 0 +Line 10848: 0 +Line 10849: 0 +Line 10850: 0 +Line 10851: 0 +Line 10852: 0 +Line 10853: 0 +Line 10854: 0 +Line 10855: 0 +Line 10856: 1 +Line 10857: 1 +Line 10858: 0 +Line 10859: 1 +Line 10860: 0 +Line 10861: 0 +Line 10862: 1 +Line 10863: 0 +Line 10864: 0 +Line 10865: 0 +Line 10866: 0 +Line 10867: 0 +Line 10868: 0 +Line 10869: 0 +Line 10870: 0 +Line 10871: 0 +Line 10872: 0 +Line 10873: 1 +Line 10874: 0 +Line 10875: 1 +Line 10876: 1 +Line 10877: 1 +Line 10878: 0 +Line 10879: 1 +Line 10880: 0 +Line 10881: 0 +Line 10882: 0 +Line 10883: 0 +Line 10884: 0 +Line 10885: 0 +Line 10886: 0 +Line 10887: 0 +Line 10888: 1 +Line 10889: 0 +Line 10890: 0 +Line 10891: 1 +Line 10892: 0 +Line 10893: 0 +Line 10894: 1 +Line 10895: 0 +Line 10896: 0 +Line 10897: 0 +Line 10898: 0 +Line 10899: 0 +Line 10900: 0 +Line 10901: 0 +Line 10902: 0 +Line 10903: 0 +Line 10904: 0 +Line 10905: 1 +Line 10906: 0 +Line 10907: 0 +Line 10908: 1 +Line 10909: 1 +Line 10910: 1 +Line 10911: 0 +Line 10912: 0 +Line 10913: 0 +Line 10914: 0 +Line 10915: 0 +Line 10916: 0 +Line 10917: 0 +Line 10918: 0 +Line 10919: 0 +Line 10920: 0 +Line 10921: 1 +Line 10922: 0 +Line 10923: 1 +Line 10924: 1 +Line 10925: 1 +Line 10926: 0 +Line 10927: 1 +Line 10928: 0 +Line 10929: 0 +Line 10930: 0 +Line 10931: 0 +Line 10932: 0 +Line 10933: 0 +Line 10934: 0 +Line 10935: 0 +Line 10936: 0 +Line 10937: 0 +Line 10938: 1 +Line 10939: 1 +Line 10940: 1 +Line 10941: 1 +Line 10942: 1 +Line 10943: 0 +Line 10944: 0 +Line 10945: 0 +Line 10946: 0 +Line 10947: 0 +Line 10948: 0 +Line 10949: 0 +Line 10950: 0 +Line 10951: 0 +Line 10952: 0 +Line 10953: 0 +Line 10954: 1 +Line 10955: 1 +Line 10956: 0 +Line 10957: 1 +Line 10958: 0 +Line 10959: 0 +Line 10960: 0 +Line 10961: 0 +Line 10962: 0 +Line 10963: 0 +Line 10964: 0 +Line 10965: 0 +Line 10966: 0 +Line 10967: 0 +Line 10968: 0 +Line 10969: 0 +Line 10970: 1 +Line 10971: 0 +Line 10972: 1 +Line 10973: 1 +Line 10974: 1 +Line 10975: 1 +Line 10976: 0 +Line 10977: 0 +Line 10978: 0 +Line 10979: 0 +Line 10980: 0 +Line 10981: 0 +Line 10982: 0 +Line 10983: 0 +Line 10984: 0 +Line 10985: 0 +Line 10986: 0 +Line 10987: 1 +Line 10988: 0 +Line 10989: 1 +Line 10990: 1 +Line 10991: 1 +Line 10992: 0 +Line 10993: 0 +Line 10994: 0 +Line 10995: 0 +Line 10996: 0 +Line 10997: 0 +Line 10998: 0 +Line 10999: 0 +Line 11000: 0 +Line 11001: 0 +Line 11002: 0 +Line 11003: 1 +Line 11004: 1 +Line 11005: 1 +Line 11006: 1 +Line 11007: 1 +Line 11008: 0 +Line 11009: 0 +Line 11010: 0 +Line 11011: 0 +Line 11012: 0 +Line 11013: 0 +Line 11014: 0 +Line 11015: 0 +Line 11016: 0 +Line 11017: 0 +Line 11018: 0 +Line 11019: 0 +Line 11020: 0 +Line 11021: 1 +Line 11022: 0 +Line 11023: 1 +Line 11024: 0 +Line 11025: 0 +Line 11026: 0 +Line 11027: 0 +Line 11028: 0 +Line 11029: 0 +Line 11030: 0 +Line 11031: 0 +Line 11032: 0 +Line 11033: 0 +Line 11034: 0 +Line 11035: 0 +Line 11036: 1 +Line 11037: 1 +Line 11038: 1 +Line 11039: 1 +Line 11040: 0 +Line 11041: 0 +Line 11042: 0 +Line 11043: 0 +Line 11044: 0 +Line 11045: 0 +Line 11046: 0 +Line 11047: 0 +Line 11048: 0 +Line 11049: 0 +Line 11050: 0 +Line 11051: 0 +Line 11052: 0 +Line 11053: 0 +Line 11054: 0 +Line 11055: 0 +Line 11056: 0 +Line 11057: 0 +Line 11058: 0 +Line 11059: 0 +Line 11060: 0 +Line 11061: 0 +Line 11062: 0 +Line 11063: 0 +Line 11064: 0 +Line 11065: 0 +Line 11066: 0 +Line 11067: 0 +Line 11068: 0 +Line 11069: 0 +Line 11070: 0 +Line 11071: 0 +Line 11072: 0 +Line 11073: 1 +Line 11074: 0 +Line 11075: 0 +Line 11076: 0 +Line 11077: 1 +Line 11078: 1 +Line 11079: 0 +Line 11080: 0 +Line 11081: 1 +Line 11082: 0 +Line 11083: 1 +Line 11084: 0 +Line 11085: 0 +Line 11086: 0 +Line 11087: 0 +Line 11088: 0 +Line 11089: 0 +Line 11090: 0 +Line 11091: 0 +Line 11092: 0 +Line 11093: 0 +Line 11094: 0 +Line 11095: 0 +Line 11096: 0 +Line 11097: 0 +Line 11098: 0 +Line 11099: 0 +Line 11100: 0 +Line 11101: 0 +Line 11102: 0 +Line 11103: 0 +Line 11104: 0 +Line 11105: 0 +Line 11106: 0 +Line 11107: 0 +Line 11108: 0 +Line 11109: 0 +Line 11110: 0 +Line 11111: 0 +Line 11112: 0 +Line 11113: 0 +Line 11114: 0 +Line 11115: 0 +Line 11116: 0 +Line 11117: 0 +Line 11118: 0 +Line 11119: 0 +Line 11120: 0 +Line 11121: 0 +Line 11122: 0 +Line 11123: 0 +Line 11124: 0 +Line 11125: 0 +Line 11126: 0 +Line 11127: 0 +Line 11128: 0 +Line 11129: 0 +Line 11130: 0 +Line 11131: 0 +Line 11132: 0 +Line 11133: 0 +Line 11134: 0 +Line 11135: 0 +Line 11136: 0 +Line 11137: 0 +Line 11138: 0 +Line 11139: 0 +Line 11140: 0 +Line 11141: 0 +Line 11142: 0 +Line 11143: 0 +Line 11144: 0 +Line 11145: 0 +Line 11146: 0 +Line 11147: 0 +Line 11148: 0 +Line 11149: 0 +Line 11150: 0 +Line 11151: 0 +Line 11152: 0 +Line 11153: 0 +Line 11154: 0 +Line 11155: 0 +Line 11156: 0 +Line 11157: 0 +Line 11158: 0 +Line 11159: 0 +Line 11160: 0 +Line 11161: 0 +Line 11162: 0 +Line 11163: 0 +Line 11164: 0 +Line 11165: 0 +Line 11166: 0 +Line 11167: 0 +Line 11168: 0 +Line 11169: 0 +Line 11170: 0 +Line 11171: 0 +Line 11172: 1 +Line 11173: 0 +Line 11174: 0 +Line 11175: 0 +Line 11176: 0 +Line 11177: 0 +Line 11178: 0 +Line 11179: 0 +Line 11180: 1 +Line 11181: 0 +Line 11182: 1 +Line 11183: 0 +Line 11184: 0 +Line 11185: 0 +Line 11186: 0 +Line 11187: 0 +Line 11188: 0 +Line 11189: 0 +Line 11190: 0 +Line 11191: 0 +Line 11192: 0 +Line 11193: 0 +Line 11194: 0 +Line 11195: 0 +Line 11196: 0 +Line 11197: 0 +Line 11198: 0 +Line 11199: 0 +Line 11200: 0 +Line 11201: 0 +Line 11202: 0 +Line 11203: 0 +Line 11204: 1 +Line 11205: 1 +Line 11206: 1 +Line 11207: 1 +Line 11208: 1 +Line 11209: 1 +Line 11210: 1 +Line 11211: 0 +Line 11212: 0 +Line 11213: 1 +Line 11214: 1 +Line 11215: 1 +Line 11216: 0 +Line 11217: 0 +Line 11218: 0 +Line 11219: 0 +Line 11220: 0 +Line 11221: 0 +Line 11222: 0 +Line 11223: 0 +Line 11224: 0 +Line 11225: 0 +Line 11226: 0 +Line 11227: 0 +Line 11228: 0 +Line 11229: 0 +Line 11230: 0 +Line 11231: 0 +Line 11232: 0 +Line 11233: 0 +Line 11234: 0 +Line 11235: 1 +Line 11236: 0 +Line 11237: 1 +Line 11238: 1 +Line 11239: 1 +Line 11240: 0 +Line 11241: 1 +Line 11242: 1 +Line 11243: 0 +Line 11244: 1 +Line 11245: 1 +Line 11246: 0 +Line 11247: 0 +Line 11248: 0 +Line 11249: 0 +Line 11250: 0 +Line 11251: 0 +Line 11252: 0 +Line 11253: 0 +Line 11254: 0 +Line 11255: 0 +Line 11256: 0 +Line 11257: 0 +Line 11258: 0 +Line 11259: 0 +Line 11260: 0 +Line 11261: 0 +Line 11262: 0 +Line 11263: 0 +Line 11264: 0 +Line 11265: 0 +Line 11266: 0 +Line 11267: 1 +Line 11268: 1 +Line 11269: 1 +Line 11270: 1 +Line 11271: 0 +Line 11272: 0 +Line 11273: 1 +Line 11274: 1 +Line 11275: 1 +Line 11276: 0 +Line 11277: 0 +Line 11278: 0 +Line 11279: 1 +Line 11280: 0 +Line 11281: 0 +Line 11282: 0 +Line 11283: 0 +Line 11284: 0 +Line 11285: 0 +Line 11286: 0 +Line 11287: 0 +Line 11288: 0 +Line 11289: 0 +Line 11290: 0 +Line 11291: 0 +Line 11292: 0 +Line 11293: 0 +Line 11294: 0 +Line 11295: 0 +Line 11296: 0 +Line 11297: 0 +Line 11298: 1 +Line 11299: 0 +Line 11300: 0 +Line 11301: 1 +Line 11302: 0 +Line 11303: 0 +Line 11304: 1 +Line 11305: 1 +Line 11306: 0 +Line 11307: 1 +Line 11308: 0 +Line 11309: 1 +Line 11310: 0 +Line 11311: 1 +Line 11312: 0 +Line 11313: 0 +Line 11314: 0 +Line 11315: 0 +Line 11316: 0 +Line 11317: 0 +Line 11318: 0 +Line 11319: 0 +Line 11320: 0 +Line 11321: 0 +Line 11322: 0 +Line 11323: 0 +Line 11324: 0 +Line 11325: 0 +Line 11326: 0 +Line 11327: 0 +Line 11328: 0 +Line 11329: 0 +Line 11330: 1 +Line 11331: 0 +Line 11332: 1 +Line 11333: 0 +Line 11334: 1 +Line 11335: 0 +Line 11336: 0 +Line 11337: 1 +Line 11338: 1 +Line 11339: 1 +Line 11340: 1 +Line 11341: 1 +Line 11342: 1 +Line 11343: 0 +Line 11344: 0 +Line 11345: 0 +Line 11346: 0 +Line 11347: 0 +Line 11348: 0 +Line 11349: 0 +Line 11350: 0 +Line 11351: 0 +Line 11352: 0 +Line 11353: 0 +Line 11354: 0 +Line 11355: 0 +Line 11356: 0 +Line 11357: 0 +Line 11358: 0 +Line 11359: 0 +Line 11360: 0 +Line 11361: 0 +Line 11362: 1 +Line 11363: 0 +Line 11364: 1 +Line 11365: 1 +Line 11366: 1 +Line 11367: 1 +Line 11368: 0 +Line 11369: 1 +Line 11370: 0 +Line 11371: 1 +Line 11372: 1 +Line 11373: 0 +Line 11374: 0 +Line 11375: 1 +Line 11376: 0 +Line 11377: 0 +Line 11378: 0 +Line 11379: 0 +Line 11380: 0 +Line 11381: 0 +Line 11382: 0 +Line 11383: 0 +Line 11384: 0 +Line 11385: 0 +Line 11386: 0 +Line 11387: 0 +Line 11388: 0 +Line 11389: 0 +Line 11390: 0 +Line 11391: 0 +Line 11392: 0 +Line 11393: 0 +Line 11394: 1 +Line 11395: 1 +Line 11396: 0 +Line 11397: 0 +Line 11398: 1 +Line 11399: 1 +Line 11400: 0 +Line 11401: 1 +Line 11402: 0 +Line 11403: 1 +Line 11404: 1 +Line 11405: 1 +Line 11406: 1 +Line 11407: 1 +Line 11408: 0 +Line 11409: 0 +Line 11410: 0 +Line 11411: 0 +Line 11412: 0 +Line 11413: 0 +Line 11414: 0 +Line 11415: 0 +Line 11416: 0 +Line 11417: 0 +Line 11418: 0 +Line 11419: 0 +Line 11420: 0 +Line 11421: 0 +Line 11422: 0 +Line 11423: 0 +Line 11424: 0 +Line 11425: 0 +Line 11426: 1 +Line 11427: 1 +Line 11428: 0 +Line 11429: 1 +Line 11430: 1 +Line 11431: 0 +Line 11432: 1 +Line 11433: 0 +Line 11434: 0 +Line 11435: 1 +Line 11436: 0 +Line 11437: 0 +Line 11438: 0 +Line 11439: 0 +Line 11440: 0 +Line 11441: 0 +Line 11442: 0 +Line 11443: 0 +Line 11444: 0 +Line 11445: 0 +Line 11446: 0 +Line 11447: 0 +Line 11448: 0 +Line 11449: 0 +Line 11450: 0 +Line 11451: 0 +Line 11452: 0 +Line 11453: 0 +Line 11454: 0 +Line 11455: 0 +Line 11456: 0 +Line 11457: 0 +Line 11458: 1 +Line 11459: 1 +Line 11460: 1 +Line 11461: 0 +Line 11462: 0 +Line 11463: 0 +Line 11464: 1 +Line 11465: 1 +Line 11466: 1 +Line 11467: 1 +Line 11468: 0 +Line 11469: 0 +Line 11470: 1 +Line 11471: 0 +Line 11472: 0 +Line 11473: 0 +Line 11474: 0 +Line 11475: 0 +Line 11476: 0 +Line 11477: 0 +Line 11478: 0 +Line 11479: 0 +Line 11480: 0 +Line 11481: 0 +Line 11482: 0 +Line 11483: 0 +Line 11484: 0 +Line 11485: 0 +Line 11486: 0 +Line 11487: 0 +Line 11488: 0 +Line 11489: 0 +Line 11490: 1 +Line 11491: 1 +Line 11492: 1 +Line 11493: 0 +Line 11494: 1 +Line 11495: 0 +Line 11496: 1 +Line 11497: 0 +Line 11498: 0 +Line 11499: 1 +Line 11500: 1 +Line 11501: 0 +Line 11502: 0 +Line 11503: 1 +Line 11504: 0 +Line 11505: 0 +Line 11506: 0 +Line 11507: 0 +Line 11508: 0 +Line 11509: 0 +Line 11510: 0 +Line 11511: 0 +Line 11512: 0 +Line 11513: 0 +Line 11514: 0 +Line 11515: 0 +Line 11516: 0 +Line 11517: 0 +Line 11518: 0 +Line 11519: 0 +Line 11520: 0 +Line 11521: 0 +Line 11522: 1 +Line 11523: 1 +Line 11524: 1 +Line 11525: 0 +Line 11526: 1 +Line 11527: 1 +Line 11528: 1 +Line 11529: 0 +Line 11530: 0 +Line 11531: 1 +Line 11532: 1 +Line 11533: 0 +Line 11534: 1 +Line 11535: 0 +Line 11536: 0 +Line 11537: 0 +Line 11538: 0 +Line 11539: 0 +Line 11540: 0 +Line 11541: 0 +Line 11542: 0 +Line 11543: 0 +Line 11544: 0 +Line 11545: 0 +Line 11546: 0 +Line 11547: 0 +Line 11548: 0 +Line 11549: 0 +Line 11550: 0 +Line 11551: 0 +Line 11552: 0 +Line 11553: 0 +Line 11554: 1 +Line 11555: 1 +Line 11556: 1 +Line 11557: 1 +Line 11558: 0 +Line 11559: 0 +Line 11560: 0 +Line 11561: 0 +Line 11562: 0 +Line 11563: 1 +Line 11564: 0 +Line 11565: 0 +Line 11566: 0 +Line 11567: 1 +Line 11568: 0 +Line 11569: 0 +Line 11570: 0 +Line 11571: 0 +Line 11572: 0 +Line 11573: 0 +Line 11574: 0 +Line 11575: 0 +Line 11576: 0 +Line 11577: 0 +Line 11578: 0 +Line 11579: 0 +Line 11580: 0 +Line 11581: 0 +Line 11582: 0 +Line 11583: 0 +Line 11584: 0 +Line 11585: 0 +Line 11586: 1 +Line 11587: 1 +Line 11588: 1 +Line 11589: 1 +Line 11590: 0 +Line 11591: 0 +Line 11592: 0 +Line 11593: 0 +Line 11594: 0 +Line 11595: 1 +Line 11596: 1 +Line 11597: 1 +Line 11598: 1 +Line 11599: 1 +Line 11600: 0 +Line 11601: 0 +Line 11602: 0 +Line 11603: 0 +Line 11604: 0 +Line 11605: 0 +Line 11606: 0 +Line 11607: 0 +Line 11608: 0 +Line 11609: 0 +Line 11610: 0 +Line 11611: 0 +Line 11612: 0 +Line 11613: 0 +Line 11614: 0 +Line 11615: 0 +Line 11616: 0 +Line 11617: 0 +Line 11618: 1 +Line 11619: 1 +Line 11620: 1 +Line 11621: 0 +Line 11622: 1 +Line 11623: 1 +Line 11624: 1 +Line 11625: 1 +Line 11626: 1 +Line 11627: 0 +Line 11628: 0 +Line 11629: 1 +Line 11630: 0 +Line 11631: 0 +Line 11632: 0 +Line 11633: 0 +Line 11634: 0 +Line 11635: 0 +Line 11636: 0 +Line 11637: 0 +Line 11638: 0 +Line 11639: 0 +Line 11640: 0 +Line 11641: 0 +Line 11642: 0 +Line 11643: 0 +Line 11644: 0 +Line 11645: 0 +Line 11646: 0 +Line 11647: 0 +Line 11648: 0 +Line 11649: 0 +Line 11650: 1 +Line 11651: 1 +Line 11652: 1 +Line 11653: 0 +Line 11654: 1 +Line 11655: 1 +Line 11656: 1 +Line 11657: 0 +Line 11658: 0 +Line 11659: 0 +Line 11660: 0 +Line 11661: 0 +Line 11662: 0 +Line 11663: 0 +Line 11664: 0 +Line 11665: 0 +Line 11666: 0 +Line 11667: 0 +Line 11668: 0 +Line 11669: 0 +Line 11670: 0 +Line 11671: 0 +Line 11672: 0 +Line 11673: 0 +Line 11674: 0 +Line 11675: 0 +Line 11676: 0 +Line 11677: 0 +Line 11678: 0 +Line 11679: 0 +Line 11680: 0 +Line 11681: 0 +Line 11682: 1 +Line 11683: 1 +Line 11684: 1 +Line 11685: 0 +Line 11686: 1 +Line 11687: 1 +Line 11688: 0 +Line 11689: 0 +Line 11690: 0 +Line 11691: 1 +Line 11692: 0 +Line 11693: 0 +Line 11694: 0 +Line 11695: 0 +Line 11696: 0 +Line 11697: 0 +Line 11698: 0 +Line 11699: 0 +Line 11700: 0 +Line 11701: 0 +Line 11702: 0 +Line 11703: 0 +Line 11704: 0 +Line 11705: 0 +Line 11706: 0 +Line 11707: 0 +Line 11708: 0 +Line 11709: 0 +Line 11710: 0 +Line 11711: 0 +Line 11712: 0 +Line 11713: 0 +Line 11714: 1 +Line 11715: 1 +Line 11716: 1 +Line 11717: 0 +Line 11718: 1 +Line 11719: 0 +Line 11720: 1 +Line 11721: 0 +Line 11722: 1 +Line 11723: 0 +Line 11724: 1 +Line 11725: 1 +Line 11726: 0 +Line 11727: 1 +Line 11728: 0 +Line 11729: 0 +Line 11730: 0 +Line 11731: 0 +Line 11732: 0 +Line 11733: 0 +Line 11734: 0 +Line 11735: 0 +Line 11736: 0 +Line 11737: 0 +Line 11738: 0 +Line 11739: 0 +Line 11740: 0 +Line 11741: 0 +Line 11742: 0 +Line 11743: 0 +Line 11744: 0 +Line 11745: 0 +Line 11746: 1 +Line 11747: 1 +Line 11748: 1 +Line 11749: 0 +Line 11750: 1 +Line 11751: 0 +Line 11752: 0 +Line 11753: 1 +Line 11754: 1 +Line 11755: 0 +Line 11756: 1 +Line 11757: 0 +Line 11758: 0 +Line 11759: 1 +Line 11760: 0 +Line 11761: 0 +Line 11762: 0 +Line 11763: 0 +Line 11764: 0 +Line 11765: 0 +Line 11766: 0 +Line 11767: 0 +Line 11768: 0 +Line 11769: 0 +Line 11770: 0 +Line 11771: 0 +Line 11772: 0 +Line 11773: 0 +Line 11774: 0 +Line 11775: 0 +Line 11776: 0 +Line 11777: 0 +Line 11778: 1 +Line 11779: 1 +Line 11780: 1 +Line 11781: 0 +Line 11782: 1 +Line 11783: 0 +Line 11784: 0 +Line 11785: 1 +Line 11786: 0 +Line 11787: 1 +Line 11788: 0 +Line 11789: 0 +Line 11790: 1 +Line 11791: 0 +Line 11792: 0 +Line 11793: 0 +Line 11794: 0 +Line 11795: 0 +Line 11796: 0 +Line 11797: 0 +Line 11798: 0 +Line 11799: 0 +Line 11800: 0 +Line 11801: 0 +Line 11802: 0 +Line 11803: 0 +Line 11804: 0 +Line 11805: 0 +Line 11806: 0 +Line 11807: 0 +Line 11808: 0 +Line 11809: 0 +Line 11810: 1 +Line 11811: 1 +Line 11812: 1 +Line 11813: 0 +Line 11814: 1 +Line 11815: 0 +Line 11816: 0 +Line 11817: 1 +Line 11818: 1 +Line 11819: 0 +Line 11820: 1 +Line 11821: 0 +Line 11822: 0 +Line 11823: 1 +Line 11824: 0 +Line 11825: 0 +Line 11826: 0 +Line 11827: 0 +Line 11828: 0 +Line 11829: 0 +Line 11830: 0 +Line 11831: 0 +Line 11832: 0 +Line 11833: 0 +Line 11834: 0 +Line 11835: 0 +Line 11836: 0 +Line 11837: 0 +Line 11838: 0 +Line 11839: 0 +Line 11840: 0 +Line 11841: 0 +Line 11842: 1 +Line 11843: 1 +Line 11844: 1 +Line 11845: 0 +Line 11846: 1 +Line 11847: 0 +Line 11848: 1 +Line 11849: 0 +Line 11850: 1 +Line 11851: 0 +Line 11852: 1 +Line 11853: 1 +Line 11854: 0 +Line 11855: 1 +Line 11856: 0 +Line 11857: 0 +Line 11858: 0 +Line 11859: 0 +Line 11860: 0 +Line 11861: 0 +Line 11862: 0 +Line 11863: 0 +Line 11864: 0 +Line 11865: 0 +Line 11866: 0 +Line 11867: 0 +Line 11868: 0 +Line 11869: 0 +Line 11870: 0 +Line 11871: 0 +Line 11872: 0 +Line 11873: 0 +Line 11874: 1 +Line 11875: 1 +Line 11876: 1 +Line 11877: 0 +Line 11878: 1 +Line 11879: 1 +Line 11880: 0 +Line 11881: 0 +Line 11882: 0 +Line 11883: 1 +Line 11884: 0 +Line 11885: 0 +Line 11886: 0 +Line 11887: 0 +Line 11888: 0 +Line 11889: 0 +Line 11890: 0 +Line 11891: 0 +Line 11892: 0 +Line 11893: 0 +Line 11894: 0 +Line 11895: 0 +Line 11896: 0 +Line 11897: 0 +Line 11898: 0 +Line 11899: 0 +Line 11900: 0 +Line 11901: 0 +Line 11902: 0 +Line 11903: 0 +Line 11904: 0 +Line 11905: 0 +Line 11906: 1 +Line 11907: 1 +Line 11908: 1 +Line 11909: 0 +Line 11910: 1 +Line 11911: 1 +Line 11912: 1 +Line 11913: 0 +Line 11914: 0 +Line 11915: 0 +Line 11916: 0 +Line 11917: 0 +Line 11918: 0 +Line 11919: 0 +Line 11920: 0 +Line 11921: 0 +Line 11922: 0 +Line 11923: 0 +Line 11924: 0 +Line 11925: 0 +Line 11926: 0 +Line 11927: 0 +Line 11928: 0 +Line 11929: 0 +Line 11930: 0 +Line 11931: 0 +Line 11932: 0 +Line 11933: 0 +Line 11934: 0 +Line 11935: 0 +Line 11936: 0 +Line 11937: 0 +Line 11938: 1 +Line 11939: 1 +Line 11940: 1 +Line 11941: 0 +Line 11942: 1 +Line 11943: 1 +Line 11944: 1 +Line 11945: 1 +Line 11946: 1 +Line 11947: 0 +Line 11948: 0 +Line 11949: 1 +Line 11950: 0 +Line 11951: 0 +Line 11952: 0 +Line 11953: 0 +Line 11954: 0 +Line 11955: 0 +Line 11956: 0 +Line 11957: 0 +Line 11958: 0 +Line 11959: 0 +Line 11960: 0 +Line 11961: 0 +Line 11962: 0 +Line 11963: 0 +Line 11964: 0 +Line 11965: 0 +Line 11966: 0 +Line 11967: 0 +Line 11968: 0 +Line 11969: 0 +Line 11970: 1 +Line 11971: 1 +Line 11972: 1 +Line 11973: 1 +Line 11974: 0 +Line 11975: 0 +Line 11976: 0 +Line 11977: 0 +Line 11978: 0 +Line 11979: 1 +Line 11980: 1 +Line 11981: 1 +Line 11982: 1 +Line 11983: 1 +Line 11984: 0 +Line 11985: 0 +Line 11986: 0 +Line 11987: 0 +Line 11988: 0 +Line 11989: 0 +Line 11990: 0 +Line 11991: 0 +Line 11992: 0 +Line 11993: 0 +Line 11994: 0 +Line 11995: 0 +Line 11996: 0 +Line 11997: 0 +Line 11998: 0 +Line 11999: 0 +Line 12000: 0 +Line 12001: 0 +Line 12002: 1 +Line 12003: 1 +Line 12004: 1 +Line 12005: 1 +Line 12006: 0 +Line 12007: 0 +Line 12008: 0 +Line 12009: 0 +Line 12010: 0 +Line 12011: 1 +Line 12012: 0 +Line 12013: 0 +Line 12014: 0 +Line 12015: 1 +Line 12016: 0 +Line 12017: 0 +Line 12018: 0 +Line 12019: 0 +Line 12020: 0 +Line 12021: 0 +Line 12022: 0 +Line 12023: 0 +Line 12024: 0 +Line 12025: 0 +Line 12026: 0 +Line 12027: 0 +Line 12028: 0 +Line 12029: 0 +Line 12030: 0 +Line 12031: 0 +Line 12032: 0 +Line 12033: 0 +Line 12034: 1 +Line 12035: 1 +Line 12036: 1 +Line 12037: 0 +Line 12038: 1 +Line 12039: 1 +Line 12040: 1 +Line 12041: 0 +Line 12042: 0 +Line 12043: 1 +Line 12044: 1 +Line 12045: 0 +Line 12046: 1 +Line 12047: 0 +Line 12048: 0 +Line 12049: 0 +Line 12050: 0 +Line 12051: 0 +Line 12052: 0 +Line 12053: 0 +Line 12054: 0 +Line 12055: 0 +Line 12056: 0 +Line 12057: 0 +Line 12058: 0 +Line 12059: 0 +Line 12060: 0 +Line 12061: 0 +Line 12062: 0 +Line 12063: 0 +Line 12064: 0 +Line 12065: 0 +Line 12066: 1 +Line 12067: 1 +Line 12068: 1 +Line 12069: 0 +Line 12070: 1 +Line 12071: 0 +Line 12072: 1 +Line 12073: 0 +Line 12074: 0 +Line 12075: 1 +Line 12076: 1 +Line 12077: 0 +Line 12078: 0 +Line 12079: 1 +Line 12080: 0 +Line 12081: 0 +Line 12082: 0 +Line 12083: 0 +Line 12084: 0 +Line 12085: 0 +Line 12086: 0 +Line 12087: 0 +Line 12088: 0 +Line 12089: 0 +Line 12090: 0 +Line 12091: 0 +Line 12092: 0 +Line 12093: 0 +Line 12094: 0 +Line 12095: 0 +Line 12096: 0 +Line 12097: 0 +Line 12098: 1 +Line 12099: 1 +Line 12100: 1 +Line 12101: 0 +Line 12102: 0 +Line 12103: 0 +Line 12104: 1 +Line 12105: 1 +Line 12106: 1 +Line 12107: 1 +Line 12108: 0 +Line 12109: 0 +Line 12110: 1 +Line 12111: 0 +Line 12112: 0 +Line 12113: 0 +Line 12114: 0 +Line 12115: 0 +Line 12116: 0 +Line 12117: 0 +Line 12118: 0 +Line 12119: 0 +Line 12120: 0 +Line 12121: 0 +Line 12122: 0 +Line 12123: 0 +Line 12124: 0 +Line 12125: 0 +Line 12126: 0 +Line 12127: 0 +Line 12128: 0 +Line 12129: 0 +Line 12130: 1 +Line 12131: 1 +Line 12132: 0 +Line 12133: 1 +Line 12134: 1 +Line 12135: 0 +Line 12136: 1 +Line 12137: 0 +Line 12138: 0 +Line 12139: 1 +Line 12140: 0 +Line 12141: 0 +Line 12142: 0 +Line 12143: 0 +Line 12144: 0 +Line 12145: 0 +Line 12146: 0 +Line 12147: 0 +Line 12148: 0 +Line 12149: 0 +Line 12150: 0 +Line 12151: 0 +Line 12152: 0 +Line 12153: 0 +Line 12154: 0 +Line 12155: 0 +Line 12156: 0 +Line 12157: 0 +Line 12158: 0 +Line 12159: 0 +Line 12160: 0 +Line 12161: 0 +Line 12162: 1 +Line 12163: 1 +Line 12164: 0 +Line 12165: 0 +Line 12166: 1 +Line 12167: 1 +Line 12168: 0 +Line 12169: 1 +Line 12170: 0 +Line 12171: 1 +Line 12172: 1 +Line 12173: 1 +Line 12174: 1 +Line 12175: 1 +Line 12176: 0 +Line 12177: 0 +Line 12178: 0 +Line 12179: 0 +Line 12180: 0 +Line 12181: 0 +Line 12182: 0 +Line 12183: 0 +Line 12184: 0 +Line 12185: 0 +Line 12186: 0 +Line 12187: 0 +Line 12188: 0 +Line 12189: 0 +Line 12190: 0 +Line 12191: 0 +Line 12192: 0 +Line 12193: 0 +Line 12194: 1 +Line 12195: 0 +Line 12196: 1 +Line 12197: 1 +Line 12198: 1 +Line 12199: 1 +Line 12200: 0 +Line 12201: 1 +Line 12202: 0 +Line 12203: 1 +Line 12204: 1 +Line 12205: 0 +Line 12206: 0 +Line 12207: 1 +Line 12208: 0 +Line 12209: 0 +Line 12210: 0 +Line 12211: 0 +Line 12212: 0 +Line 12213: 0 +Line 12214: 0 +Line 12215: 0 +Line 12216: 0 +Line 12217: 0 +Line 12218: 0 +Line 12219: 0 +Line 12220: 0 +Line 12221: 0 +Line 12222: 0 +Line 12223: 0 +Line 12224: 0 +Line 12225: 0 +Line 12226: 1 +Line 12227: 0 +Line 12228: 1 +Line 12229: 0 +Line 12230: 1 +Line 12231: 0 +Line 12232: 0 +Line 12233: 1 +Line 12234: 1 +Line 12235: 1 +Line 12236: 1 +Line 12237: 1 +Line 12238: 1 +Line 12239: 0 +Line 12240: 0 +Line 12241: 0 +Line 12242: 0 +Line 12243: 0 +Line 12244: 0 +Line 12245: 0 +Line 12246: 0 +Line 12247: 0 +Line 12248: 0 +Line 12249: 0 +Line 12250: 0 +Line 12251: 0 +Line 12252: 0 +Line 12253: 0 +Line 12254: 0 +Line 12255: 0 +Line 12256: 0 +Line 12257: 0 +Line 12258: 1 +Line 12259: 0 +Line 12260: 0 +Line 12261: 1 +Line 12262: 0 +Line 12263: 0 +Line 12264: 1 +Line 12265: 1 +Line 12266: 0 +Line 12267: 1 +Line 12268: 0 +Line 12269: 1 +Line 12270: 0 +Line 12271: 1 +Line 12272: 0 +Line 12273: 0 +Line 12274: 0 +Line 12275: 0 +Line 12276: 0 +Line 12277: 0 +Line 12278: 0 +Line 12279: 0 +Line 12280: 0 +Line 12281: 0 +Line 12282: 0 +Line 12283: 0 +Line 12284: 0 +Line 12285: 0 +Line 12286: 0 +Line 12287: 0 +Line 12288: 0 +Line 12289: 0 +Line 12290: 0 +Line 12291: 1 +Line 12292: 1 +Line 12293: 1 +Line 12294: 1 +Line 12295: 0 +Line 12296: 0 +Line 12297: 1 +Line 12298: 1 +Line 12299: 1 +Line 12300: 0 +Line 12301: 0 +Line 12302: 0 +Line 12303: 1 +Line 12304: 0 +Line 12305: 0 +Line 12306: 0 +Line 12307: 0 +Line 12308: 0 +Line 12309: 0 +Line 12310: 0 +Line 12311: 0 +Line 12312: 0 +Line 12313: 0 +Line 12314: 0 +Line 12315: 0 +Line 12316: 0 +Line 12317: 0 +Line 12318: 0 +Line 12319: 0 +Line 12320: 0 +Line 12321: 0 +Line 12322: 0 +Line 12323: 1 +Line 12324: 0 +Line 12325: 1 +Line 12326: 1 +Line 12327: 1 +Line 12328: 0 +Line 12329: 1 +Line 12330: 1 +Line 12331: 0 +Line 12332: 1 +Line 12333: 1 +Line 12334: 0 +Line 12335: 0 +Line 12336: 0 +Line 12337: 0 +Line 12338: 0 +Line 12339: 0 +Line 12340: 0 +Line 12341: 0 +Line 12342: 0 +Line 12343: 0 +Line 12344: 0 +Line 12345: 0 +Line 12346: 0 +Line 12347: 0 +Line 12348: 0 +Line 12349: 0 +Line 12350: 0 +Line 12351: 0 +Line 12352: 0 +Line 12353: 0 +Line 12354: 0 +Line 12355: 0 +Line 12356: 1 +Line 12357: 1 +Line 12358: 1 +Line 12359: 1 +Line 12360: 1 +Line 12361: 1 +Line 12362: 1 +Line 12363: 0 +Line 12364: 0 +Line 12365: 1 +Line 12366: 1 +Line 12367: 1 +Line 12368: 0 +Line 12369: 0 +Line 12370: 0 +Line 12371: 0 +Line 12372: 0 +Line 12373: 0 +Line 12374: 0 +Line 12375: 0 +Line 12376: 0 +Line 12377: 0 +Line 12378: 0 +Line 12379: 0 +Line 12380: 0 +Line 12381: 0 +Line 12382: 0 +Line 12383: 0 +Line 12384: 0 +Line 12385: 0 +Line 12386: 0 +Line 12387: 0 +Line 12388: 1 +Line 12389: 0 +Line 12390: 0 +Line 12391: 0 +Line 12392: 0 +Line 12393: 0 +Line 12394: 0 +Line 12395: 0 +Line 12396: 1 +Line 12397: 0 +Line 12398: 1 +Line 12399: 0 +Line 12400: 0 +Line 12401: 0 +Line 12402: 0 +Line 12403: 0 +Line 12404: 0 +Line 12405: 0 +Line 12406: 0 +Line 12407: 0 +Line 12408: 0 +Line 12409: 0 +Line 12410: 0 +Line 12411: 0 +Line 12412: 0 +Line 12413: 0 +Line 12414: 0 +Line 12415: 0 +Line 12416: 0 +Line 12417: 0 +Line 12418: 0 +Line 12419: 0 +Line 12420: 0 +Line 12421: 0 +Line 12422: 0 +Line 12423: 0 +Line 12424: 0 +Line 12425: 0 +Line 12426: 0 +Line 12427: 0 +Line 12428: 0 +Line 12429: 0 +Line 12430: 0 +Line 12431: 0 +Line 12432: 0 +Line 12433: 0 +Line 12434: 0 +Line 12435: 0 +Line 12436: 0 +Line 12437: 0 +Line 12438: 0 +Line 12439: 0 +Line 12440: 0 +Line 12441: 0 +Line 12442: 0 +Line 12443: 0 +Line 12444: 0 +Line 12445: 0 +Line 12446: 0 +Line 12447: 0 +Line 12448: 0 +Line 12449: 0 +Line 12450: 0 +Line 12451: 0 +Line 12452: 1 +Line 12453: 0 +Line 12454: 0 +Line 12455: 0 +Line 12456: 0 +Line 12457: 0 +Line 12458: 1 +Line 12459: 1 +Line 12460: 1 +Line 12461: 0 +Line 12462: 0 +Line 12463: 1 +Line 12464: 0 +Line 12465: 0 +Line 12466: 1 +Line 12467: 0 +Line 12468: 0 +Line 12469: 0 +Line 12470: 0 +Line 12471: 1 +Line 12472: 0 +Line 12473: 0 +Line 12474: 1 +Line 12475: 0 +Line 12476: 0 +Line 12477: 0 +Line 12478: 0 +Line 12479: 1 +Line 12480: 0 +Line 12481: 0 +Line 12482: 0 +Line 12483: 1 +Line 12484: 1 +Line 12485: 1 +Line 12486: 0 +Line 12487: 1 +Line 12488: 0 +Line 12489: 0 +Line 12490: 0 +Line 12491: 0 +Line 12492: 1 +Line 12493: 1 +Line 12494: 0 +Line 12495: 1 +Line 12496: 0 +Line 12497: 0 +Line 12498: 1 +Line 12499: 1 +Line 12500: 0 +Line 12501: 0 +Line 12502: 1 +Line 12503: 0 +Line 12504: 1 +Line 12505: 1 +Line 12506: 0 +Line 12507: 0 +Line 12508: 0 +Line 12509: 0 +Line 12510: 1 +Line 12511: 0 +Line 12512: 0 +Line 12513: 0 +Line 12514: 1 +Line 12515: 1 +Line 12516: 0 +Line 12517: 1 +Line 12518: 0 +Line 12519: 0 +Line 12520: 1 +Line 12521: 0 +Line 12522: 1 +Line 12523: 1 +Line 12524: 1 +Line 12525: 0 +Line 12526: 1 +Line 12527: 1 +Line 12528: 0 +Line 12529: 0 +Line 12530: 1 +Line 12531: 0 +Line 12532: 1 +Line 12533: 1 +Line 12534: 0 +Line 12535: 0 +Line 12536: 1 +Line 12537: 0 +Line 12538: 1 +Line 12539: 0 +Line 12540: 0 +Line 12541: 0 +Line 12542: 1 +Line 12543: 0 +Line 12544: 0 +Line 12545: 1 +Line 12546: 0 +Line 12547: 0 +Line 12548: 0 +Line 12549: 1 +Line 12550: 0 +Line 12551: 0 +Line 12552: 0 +Line 12553: 0 +Line 12554: 1 +Line 12555: 1 +Line 12556: 0 +Line 12557: 0 +Line 12558: 0 +Line 12559: 1 +Line 12560: 0 +Line 12561: 0 +Line 12562: 0 +Line 12563: 1 +Line 12564: 0 +Line 12565: 0 +Line 12566: 0 +Line 12567: 1 +Line 12568: 1 +Line 12569: 0 +Line 12570: 1 +Line 12571: 0 +Line 12572: 0 +Line 12573: 0 +Line 12574: 0 +Line 12575: 0 +Line 12576: 0 +Line 12577: 1 +Line 12578: 0 +Line 12579: 0 +Line 12580: 0 +Line 12581: 1 +Line 12582: 0 +Line 12583: 0 +Line 12584: 0 +Line 12585: 0 +Line 12586: 1 +Line 12587: 1 +Line 12588: 0 +Line 12589: 0 +Line 12590: 0 +Line 12591: 1 +Line 12592: 1 +Line 12593: 1 +Line 12594: 1 +Line 12595: 0 +Line 12596: 1 +Line 12597: 1 +Line 12598: 1 +Line 12599: 0 +Line 12600: 0 +Line 12601: 1 +Line 12602: 1 +Line 12603: 0 +Line 12604: 0 +Line 12605: 0 +Line 12606: 0 +Line 12607: 0 +Line 12608: 0 +Line 12609: 0 +Line 12610: 1 +Line 12611: 1 +Line 12612: 0 +Line 12613: 1 +Line 12614: 0 +Line 12615: 0 +Line 12616: 1 +Line 12617: 0 +Line 12618: 1 +Line 12619: 1 +Line 12620: 1 +Line 12621: 1 +Line 12622: 0 +Line 12623: 0 +Line 12624: 1 +Line 12625: 1 +Line 12626: 0 +Line 12627: 1 +Line 12628: 0 +Line 12629: 0 +Line 12630: 1 +Line 12631: 1 +Line 12632: 0 +Line 12633: 1 +Line 12634: 0 +Line 12635: 1 +Line 12636: 1 +Line 12637: 1 +Line 12638: 1 +Line 12639: 0 +Line 12640: 0 +Line 12641: 0 +Line 12642: 0 +Line 12643: 1 +Line 12644: 1 +Line 12645: 1 +Line 12646: 0 +Line 12647: 1 +Line 12648: 0 +Line 12649: 0 +Line 12650: 0 +Line 12651: 0 +Line 12652: 1 +Line 12653: 1 +Line 12654: 0 +Line 12655: 1 +Line 12656: 1 +Line 12657: 1 +Line 12658: 0 +Line 12659: 0 +Line 12660: 1 +Line 12661: 1 +Line 12662: 0 +Line 12663: 1 +Line 12664: 0 +Line 12665: 0 +Line 12666: 1 +Line 12667: 1 +Line 12668: 1 +Line 12669: 1 +Line 12670: 1 +Line 12671: 0 +Line 12672: 0 +Line 12673: 0 +Line 12674: 0 +Line 12675: 0 +Line 12676: 1 +Line 12677: 0 +Line 12678: 0 +Line 12679: 0 +Line 12680: 0 +Line 12681: 0 +Line 12682: 1 +Line 12683: 1 +Line 12684: 1 +Line 12685: 0 +Line 12686: 0 +Line 12687: 1 +Line 12688: 1 +Line 12689: 1 +Line 12690: 0 +Line 12691: 1 +Line 12692: 1 +Line 12693: 1 +Line 12694: 1 +Line 12695: 0 +Line 12696: 1 +Line 12697: 1 +Line 12698: 0 +Line 12699: 1 +Line 12700: 1 +Line 12701: 1 +Line 12702: 1 +Line 12703: 1 +Line 12704: 0 +Line 12705: 0 +Line 12706: 0 +Line 12707: 0 +Line 12708: 0 +Line 12709: 0 +Line 12710: 0 +Line 12711: 0 +Line 12712: 0 +Line 12713: 0 +Line 12714: 0 +Line 12715: 0 +Line 12716: 0 +Line 12717: 0 +Line 12718: 0 +Line 12719: 0 +Line 12720: 0 +Line 12721: 0 +Line 12722: 0 +Line 12723: 0 +Line 12724: 0 +Line 12725: 0 +Line 12726: 0 +Line 12727: 0 +Line 12728: 0 +Line 12729: 0 +Line 12730: 0 +Line 12731: 0 +Line 12732: 0 +Line 12733: 0 +Line 12734: 0 +Line 12735: 0 +Line 12736: 0 +Line 12737: 0 +Line 12738: 0 +Line 12739: 0 +Line 12740: 0 +Line 12741: 0 +Line 12742: 0 +Line 12743: 1 +Line 12744: 1 +Line 12745: 0 +Line 12746: 0 +Line 12747: 1 +Line 12748: 1 +Line 12749: 0 +Line 12750: 0 +Line 12751: 1 +Line 12752: 0 +Line 12753: 0 +Line 12754: 0 +Line 12755: 0 +Line 12756: 0 +Line 12757: 0 +Line 12758: 0 +Line 12759: 0 +Line 12760: 0 +Line 12761: 0 +Line 12762: 0 +Line 12763: 0 +Line 12764: 0 +Line 12765: 0 +Line 12766: 0 +Line 12767: 0 +Line 12768: 0 +Line 12769: 0 +Line 12770: 0 +Line 12771: 0 +Line 12772: 1 +Line 12773: 0 +Line 12774: 1 +Line 12775: 1 +Line 12776: 0 +Line 12777: 0 +Line 12778: 1 +Line 12779: 0 +Line 12780: 0 +Line 12781: 1 +Line 12782: 1 +Line 12783: 1 +Line 12784: 0 +Line 12785: 0 +Line 12786: 0 +Line 12787: 0 +Line 12788: 0 +Line 12789: 0 +Line 12790: 0 +Line 12791: 0 +Line 12792: 0 +Line 12793: 0 +Line 12794: 0 +Line 12795: 0 +Line 12796: 0 +Line 12797: 0 +Line 12798: 0 +Line 12799: 0 +Line 12800: 0 +Line 12801: 0 +Line 12802: 1 +Line 12803: 0 +Line 12804: 0 +Line 12805: 0 +Line 12806: 1 +Line 12807: 1 +Line 12808: 0 +Line 12809: 0 +Line 12810: 1 +Line 12811: 0 +Line 12812: 1 +Line 12813: 0 +Line 12814: 0 +Line 12815: 0 +Line 12816: 0 +Line 12817: 0 +Line 12818: 0 +Line 12819: 0 +Line 12820: 0 +Line 12821: 0 +Line 12822: 0 +Line 12823: 0 +Line 12824: 0 +Line 12825: 0 +Line 12826: 0 +Line 12827: 0 +Line 12828: 0 +Line 12829: 0 +Line 12830: 0 +Line 12831: 0 +Line 12832: 0 +Line 12833: 0 +Line 12834: 1 +Line 12835: 1 +Line 12836: 1 +Line 12837: 0 +Line 12838: 1 +Line 12839: 1 +Line 12840: 0 +Line 12841: 0 +Line 12842: 1 +Line 12843: 0 +Line 12844: 1 +Line 12845: 0 +Line 12846: 0 +Line 12847: 0 +Line 12848: 0 +Line 12849: 0 +Line 12850: 0 +Line 12851: 0 +Line 12852: 0 +Line 12853: 0 +Line 12854: 0 +Line 12855: 0 +Line 12856: 0 +Line 12857: 0 +Line 12858: 0 +Line 12859: 0 +Line 12860: 0 +Line 12861: 0 +Line 12862: 0 +Line 12863: 0 +Line 12864: 0 +Line 12865: 1 +Line 12866: 0 +Line 12867: 0 +Line 12868: 0 +Line 12869: 1 +Line 12870: 0 +Line 12871: 0 +Line 12872: 1 +Line 12873: 0 +Line 12874: 1 +Line 12875: 1 +Line 12876: 0 +Line 12877: 1 +Line 12878: 1 +Line 12879: 0 +Line 12880: 0 +Line 12881: 0 +Line 12882: 0 +Line 12883: 0 +Line 12884: 0 +Line 12885: 0 +Line 12886: 0 +Line 12887: 0 +Line 12888: 0 +Line 12889: 0 +Line 12890: 0 +Line 12891: 0 +Line 12892: 0 +Line 12893: 0 +Line 12894: 0 +Line 12895: 0 +Line 12896: 0 +Line 12897: 1 +Line 12898: 0 +Line 12899: 0 +Line 12900: 0 +Line 12901: 1 +Line 12902: 1 +Line 12903: 0 +Line 12904: 0 +Line 12905: 0 +Line 12906: 1 +Line 12907: 1 +Line 12908: 0 +Line 12909: 1 +Line 12910: 1 +Line 12911: 1 +Line 12912: 0 +Line 12913: 0 +Line 12914: 0 +Line 12915: 0 +Line 12916: 0 +Line 12917: 0 +Line 12918: 0 +Line 12919: 0 +Line 12920: 0 +Line 12921: 0 +Line 12922: 0 +Line 12923: 0 +Line 12924: 0 +Line 12925: 0 +Line 12926: 0 +Line 12927: 0 +Line 12928: 0 +Line 12929: 1 +Line 12930: 0 +Line 12931: 0 +Line 12932: 0 +Line 12933: 1 +Line 12934: 1 +Line 12935: 0 +Line 12936: 0 +Line 12937: 1 +Line 12938: 0 +Line 12939: 0 +Line 12940: 1 +Line 12941: 1 +Line 12942: 1 +Line 12943: 1 +Line 12944: 0 +Line 12945: 0 +Line 12946: 0 +Line 12947: 0 +Line 12948: 0 +Line 12949: 0 +Line 12950: 0 +Line 12951: 0 +Line 12952: 0 +Line 12953: 0 +Line 12954: 0 +Line 12955: 0 +Line 12956: 0 +Line 12957: 0 +Line 12958: 0 +Line 12959: 0 +Line 12960: 0 +Line 12961: 1 +Line 12962: 0 +Line 12963: 0 +Line 12964: 0 +Line 12965: 1 +Line 12966: 1 +Line 12967: 0 +Line 12968: 0 +Line 12969: 1 +Line 12970: 0 +Line 12971: 0 +Line 12972: 1 +Line 12973: 1 +Line 12974: 1 +Line 12975: 1 +Line 12976: 0 +Line 12977: 0 +Line 12978: 0 +Line 12979: 0 +Line 12980: 0 +Line 12981: 0 +Line 12982: 0 +Line 12983: 0 +Line 12984: 0 +Line 12985: 0 +Line 12986: 0 +Line 12987: 0 +Line 12988: 0 +Line 12989: 0 +Line 12990: 0 +Line 12991: 0 +Line 12992: 0 +Line 12993: 1 +Line 12994: 0 +Line 12995: 0 +Line 12996: 0 +Line 12997: 1 +Line 12998: 1 +Line 12999: 0 +Line 13000: 0 +Line 13001: 1 +Line 13002: 0 +Line 13003: 0 +Line 13004: 1 +Line 13005: 1 +Line 13006: 1 +Line 13007: 1 +Line 13008: 0 +Line 13009: 0 +Line 13010: 0 +Line 13011: 0 +Line 13012: 0 +Line 13013: 0 +Line 13014: 0 +Line 13015: 0 +Line 13016: 0 +Line 13017: 0 +Line 13018: 0 +Line 13019: 0 +Line 13020: 0 +Line 13021: 0 +Line 13022: 0 +Line 13023: 0 +Line 13024: 0 +Line 13025: 1 +Line 13026: 0 +Line 13027: 0 +Line 13028: 0 +Line 13029: 1 +Line 13030: 1 +Line 13031: 0 +Line 13032: 0 +Line 13033: 1 +Line 13034: 0 +Line 13035: 0 +Line 13036: 1 +Line 13037: 1 +Line 13038: 1 +Line 13039: 1 +Line 13040: 0 +Line 13041: 0 +Line 13042: 0 +Line 13043: 0 +Line 13044: 0 +Line 13045: 0 +Line 13046: 0 +Line 13047: 0 +Line 13048: 0 +Line 13049: 0 +Line 13050: 0 +Line 13051: 0 +Line 13052: 0 +Line 13053: 0 +Line 13054: 0 +Line 13055: 0 +Line 13056: 0 +Line 13057: 1 +Line 13058: 0 +Line 13059: 0 +Line 13060: 0 +Line 13061: 1 +Line 13062: 1 +Line 13063: 0 +Line 13064: 0 +Line 13065: 0 +Line 13066: 1 +Line 13067: 1 +Line 13068: 0 +Line 13069: 1 +Line 13070: 1 +Line 13071: 1 +Line 13072: 0 +Line 13073: 0 +Line 13074: 0 +Line 13075: 0 +Line 13076: 0 +Line 13077: 0 +Line 13078: 0 +Line 13079: 0 +Line 13080: 0 +Line 13081: 0 +Line 13082: 0 +Line 13083: 0 +Line 13084: 0 +Line 13085: 0 +Line 13086: 0 +Line 13087: 0 +Line 13088: 0 +Line 13089: 1 +Line 13090: 0 +Line 13091: 0 +Line 13092: 0 +Line 13093: 1 +Line 13094: 0 +Line 13095: 0 +Line 13096: 1 +Line 13097: 0 +Line 13098: 1 +Line 13099: 1 +Line 13100: 0 +Line 13101: 1 +Line 13102: 1 +Line 13103: 0 +Line 13104: 0 +Line 13105: 0 +Line 13106: 0 +Line 13107: 0 +Line 13108: 0 +Line 13109: 0 +Line 13110: 0 +Line 13111: 0 +Line 13112: 0 +Line 13113: 0 +Line 13114: 0 +Line 13115: 0 +Line 13116: 0 +Line 13117: 0 +Line 13118: 0 +Line 13119: 0 +Line 13120: 0 +Line 13121: 0 +Line 13122: 1 +Line 13123: 1 +Line 13124: 1 +Line 13125: 0 +Line 13126: 1 +Line 13127: 1 +Line 13128: 0 +Line 13129: 0 +Line 13130: 1 +Line 13131: 0 +Line 13132: 1 +Line 13133: 0 +Line 13134: 0 +Line 13135: 0 +Line 13136: 0 +Line 13137: 0 +Line 13138: 0 +Line 13139: 0 +Line 13140: 0 +Line 13141: 0 +Line 13142: 0 +Line 13143: 0 +Line 13144: 0 +Line 13145: 0 +Line 13146: 0 +Line 13147: 0 +Line 13148: 0 +Line 13149: 0 +Line 13150: 0 +Line 13151: 0 +Line 13152: 0 +Line 13153: 0 +Line 13154: 1 +Line 13155: 0 +Line 13156: 0 +Line 13157: 0 +Line 13158: 1 +Line 13159: 1 +Line 13160: 0 +Line 13161: 0 +Line 13162: 1 +Line 13163: 0 +Line 13164: 1 +Line 13165: 0 +Line 13166: 0 +Line 13167: 0 +Line 13168: 0 +Line 13169: 0 +Line 13170: 0 +Line 13171: 0 +Line 13172: 0 +Line 13173: 0 +Line 13174: 0 +Line 13175: 0 +Line 13176: 0 +Line 13177: 0 +Line 13178: 0 +Line 13179: 0 +Line 13180: 0 +Line 13181: 0 +Line 13182: 0 +Line 13183: 0 +Line 13184: 0 +Line 13185: 0 +Line 13186: 0 +Line 13187: 0 +Line 13188: 1 +Line 13189: 0 +Line 13190: 1 +Line 13191: 1 +Line 13192: 0 +Line 13193: 0 +Line 13194: 1 +Line 13195: 0 +Line 13196: 0 +Line 13197: 1 +Line 13198: 1 +Line 13199: 1 +Line 13200: 0 +Line 13201: 0 +Line 13202: 0 +Line 13203: 0 +Line 13204: 0 +Line 13205: 0 +Line 13206: 0 +Line 13207: 0 +Line 13208: 0 +Line 13209: 0 +Line 13210: 0 +Line 13211: 0 +Line 13212: 0 +Line 13213: 0 +Line 13214: 0 +Line 13215: 0 +Line 13216: 0 +Line 13217: 0 +Line 13218: 0 +Line 13219: 0 +Line 13220: 0 +Line 13221: 0 +Line 13222: 0 +Line 13223: 1 +Line 13224: 1 +Line 13225: 0 +Line 13226: 0 +Line 13227: 1 +Line 13228: 1 +Line 13229: 0 +Line 13230: 0 +Line 13231: 1 +Line 13232: 0 +Line 13233: 0 +Line 13234: 0 +Line 13235: 0 +Line 13236: 0 +Line 13237: 0 +Line 13238: 0 +Line 13239: 0 +Line 13240: 0 +Line 13241: 0 +Line 13242: 0 +Line 13243: 0 +Line 13244: 0 +Line 13245: 0 +Line 13246: 0 +Line 13247: 0 +Send READ_FILE + V C S S i m u l a t i o n R e p o r t +Time: 3202992000 ps diff --git a/tb/chip_top/simv b/tb/chip_top/simv new file mode 100644 index 0000000..3a23156 Binary files /dev/null and b/tb/chip_top/simv differ diff --git a/tb/chip_top/simv.daidir/.daidir_complete b/tb/chip_top/simv.daidir/.daidir_complete new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/simv.daidir/.normal_done b/tb/chip_top/simv.daidir/.normal_done new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/simv.daidir/.vcs.timestamp b/tb/chip_top/simv.daidir/.vcs.timestamp new file mode 100644 index 0000000..629e540 --- /dev/null +++ b/tb/chip_top/simv.daidir/.vcs.timestamp @@ -0,0 +1,232 @@ +0 +40 ++define+DUMP_FSDB ++itf+/home/synopsys/vcs/O-2018.09-SP2/linux64/lib/vcsdp_lite.tab ++lint=TFIPC-L ++nospecify ++v2k ++vcsd1 ++vpi +-Mamsrun= +-Masflags= +-Mcc=gcc +-Mcfl= -pipe -fPIC -O -I/home/synopsys/vcs/O-2018.09-SP2/include +-Mcplusplus=g++ +-Mcrt0= +-Mcrtn= +-Mcsrc= +-Mexternalobj= +-Mldflags= -rdynamic +-Mobjects= /home/synopsys/vcs/O-2018.09-SP2/linux64/lib/libvirsim.so /home/synopsys/vcs/O-2018.09-SP2/linux64/lib/liberrorinf.so /home/synopsys/vcs/O-2018.09-SP2/linux64/lib/libsnpsmalloc.so /home/synopsys/vcs/O-2018.09-SP2/linux64/lib/libvfs.so /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/pli.a +-Mout=simv +-Msaverestoreobj=/home/synopsys/vcs/O-2018.09-SP2/linux64/lib/vcs_save_restore_new.o +-Msyslibs=/home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/pli.a -ldl -lm +-Mvcsaceobjs= +-Mxcflags= -pipe -fPIC -I/home/synopsys/vcs/O-2018.09-SP2/include +-P +-P +-debug_access+all +-f files.f +-fsdb +-full64 +-gen_obj +-l +-lca +-picarchive +-q +-sverilog +-timescale=1ns/1ps +/home/synopsys/vcs/O-2018.09-SP2/linux64/bin/vcs1 +/home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +/home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +compile.log +76 +sysc_uni_pwd=/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/chip_top +XMODIFIERS=@im=ibus +XDG_VTNR=1 +XDG_SESSION_TYPE=x11 +XDG_SESSION_ID=1 +XDG_SESSION_DESKTOP=gnome-classic +XDG_SEAT=seat0 +XDG_RUNTIME_DIR=/run/user/1000 +XDG_MENU_PREFIX=gnome- +XDG_DATA_DIRS=/home/ICer/.local/share/flatpak/exports/share/:/var/lib/flatpak/exports/share/:/usr/local/share/:/usr/share/ +XDG_CURRENT_DESKTOP=GNOME-Classic:GNOME +XAUTHORITY=/run/gdm/auth-for-ICer-FQtMgs/database +WINDOWPATH=1 +VTE_VERSION=5204 +VMR_MODE_FLAG=64 +VERDI_HOME=/home/synopsys/verdi/Verdi_O-2018.09-SP2 +VCS_MODE_FLAG=64 +VCS_LOG_FILE=compile.log +VCS_LCAMSG_PRINT_OFF=1 +VCS_HOME=/home/synopsys/vcs/O-2018.09-SP2 +VCS_DEPTH=0 +VCS_ARG_ADDED_FOR_TMP=1 +VCS_ARCH_OVERRIDE=linux +VCS_ARCH=linux64 +USERNAME=ICer +UNAME=/bin/uname +TOOL_HOME=/home/synopsys/vcs/O-2018.09-SP2/linux64 +SSH_AUTH_SOCK=/run/user/1000/keyring/ssh +SSH_AGENT_PID=10423 +SPYGLASS_HOME=/home/synopsys/SpyGlass-L2016.06/SPYGLASS_HOME/ +SESSION_MANAGER=local/unix:@/tmp/.ICE-unix/10289,unix/unix:/tmp/.ICE-unix/10289 +SCRNAME=vcs +SCRIPT_NAME=vcs +SCL_HOME=/home/synopsys/scl/2018.06 +RISCV=/home/Riscv_Tools +QUESTASIM_HOME=/home/mentor/questasim +QT_PLUGIN_PATH=/usr/lib64/kde4/plugins:/usr/lib/kde4/plugins +QT_IM_MODULE=ibus +QT_GRAPHICSSYSTEM_CHECKED=1 +QTLIB=/usr/lib/qt-3.3/lib +QTINC=/usr/lib/qt-3.3/include +QTDIR=/usr/lib/qt-3.3 +QEMU_HOME=/home/Riscv_Tools/riscv-gnu-toolchain/qemu-6.0.0 +PT_HOME=/home/synopsys/pts/O-2018.06-SP1 +OVA_UUM=0 +MGLS_LICENSE_FILE=/home/mentor/questasim/mentor.dat +MFLAGS= +MAKE_TERMOUT=/dev/pts/2 +MAKE_TERMERR=/dev/pts/2 +MAKELEVEL=1 +MAKEFLAGS= +LESSOPEN=||/usr/bin/lesspipe.sh %s +LC_TIME=zh_CN.UTF-8 +LC_PAPER=zh_CN.UTF-8 +LC_NUMERIC=zh_CN.UTF-8 +LC_MONETARY=zh_CN.UTF-8 +LC_MEASUREMENT=zh_CN.UTF-8 +LC_HOME=/home/synopsys/lc/O-2018.06-SP1 +LC_ALL=C +KDEDIRS=/usr +IMSETTINGS_MODULE=none +IMSETTINGS_INTEGRATE_DESKTOP=yes +HISTCONTROL=ignoredups +GNOME_TERMINAL_SERVICE=:1.108 +GNOME_TERMINAL_SCREEN=/org/gnome/Terminal/screen/ebae3589_b60a_4793_b5e9_6b90fc529827 +GNOME_SHELL_SESSION_MODE=classic +GNOME_DESKTOP_SESSION_ID=this-is-deprecated +GDM_LANG=zh_CN.UTF-8 +GDMSESSION=gnome-classic +DVE_HOME=/home/synopsys/vcs/O-2018.09-SP2 +DESKTOP_SESSION=gnome-classic +DC_HOME=/home/synopsys/syn/O-2018.06-SP1 +DBUS_STARTER_BUS_TYPE=session +DBUS_STARTER_ADDRESS=unix:abstract=/tmp/dbus-DIYqQioq7q,guid=a50f166bc97a0937429a75936639b5b6 +DBUS_SESSION_BUS_ADDRESS=unix:abstract=/tmp/dbus-DIYqQioq7q,guid=a50f166bc97a0937429a75936639b5b6 +COLORTERM=truecolor +0 +103 +1715825058 chip_undefine.v +1716628557 chip_define.v +1715587843 qbmcu_undefines.v +1715564372 qbmcu_defines.v +1715587843 ../qubitmcu/qbmcu_undefines.v +1715564372 ../qubitmcu/qbmcu_defines.v +1715825058 ../define/chip_undefine.v +1716628557 ../define/chip_define.v +1716778389 ../../sim/chip_top/thermo2binary_top.v +1716778343 ../../sim/chip_top/thermo7_binary3.v +1716778341 ../../sim/chip_top/thermo15_binary4.v +1715584846 ../../sim/chip_top/spi_if.sv +1692987349 ../../sim/chip_top/clk_gen.v +1699539018 ../../sim/chip_top/DW02_mult.v +1692987348 ../../sim/chip_top/DW01_addsub.v +1699539018 ../../sim/chip_top/DW_mult_pipe.v +1717383044 ../../sim/chip_top/TB.sv +1716518818 ../../rtl/dem/DAC_DEM_4.v +1716454941 ../../rtl/dem/DAC_DEM_16.v +1716454941 ../../rtl/dem/DAC_DEM.v +1715832037 ../../rtl/top/z_data_mux.v +1715479955 ../../rtl/xy_dsp/qam/ssb.v +1715776566 ../../rtl/xy_dsp/qam/qam_top.v +1716260096 ../../rtl/xy_dsp/duc/duc4.v +1715336081 ../../rtl/xy_dsp/duc/duc_hb4_top_s3.v +1716371502 ../../rtl/xy_dsp/duc/duc_hb4_pipe_shift.v +1715336081 ../../rtl/xy_dsp/duc/duc_hb3_top_s2.v +1716371468 ../../rtl/xy_dsp/duc/duc_hb3_pipe_shift.v +1715336084 ../../rtl/xy_dsp/duc/duc_hb2_top_s.v +1716371436 ../../rtl/xy_dsp/duc/duc_hb2_pipe_shift.v +1715336084 ../../rtl/xy_dsp/duc/duc_hb1_top.v +1716371402 ../../rtl/xy_dsp/duc/duc_hb1_pipe_shift.v +1715488548 ../../rtl/xy_dsp/dsp_top/xy_dsp.v +1716976038 ../../rtl/xy_dsp/dacif/dacif.v +1716813328 ../../rtl/top/xyz_chip_top.v +1717066391 ../../rtl/top/digital_top.sv +1717061360 ../../rtl/top/channel_top.sv +1717057441 ../../rtl/system_regfile/system_regfile.v +1717068239 ../../rtl/sync/sync_buf.sv +1717226926 ../../rtl/spi/spi_sys.v +1714632519 ../../rtl/spi/spi_slave.v +1716012606 ../../rtl/spi/spi_pll.v +1717066214 ../../rtl/spi/spi_bus_decoder.sv +1714632519 ../../rtl/rstgen/rst_sync.v +1715837885 ../../rtl/rstgen/rst_gen_unit.v +1716362658 ../../rtl/qubitmcu/qbmcu_wbck.v +1715587843 ../../rtl/qubitmcu/qbmcu_undefines.v +1715565068 ../../rtl/qubitmcu/qbmcu_regfile.v +1717057557 ../../rtl/qubitmcu/qbmcu_ifu.v +1716365241 ../../rtl/qubitmcu/qbmcu_fsm.v +1717067603 ../../rtl/qubitmcu/qbmcu_exu_lsuagu.v +1716378800 ../../rtl/qubitmcu/qbmcu_exu_ext.v +1716388041 ../../rtl/qubitmcu/qbmcu_exu_dpath.v +1717058038 ../../rtl/qubitmcu/qbmcu_exu_bjp.v +1715863407 ../../rtl/qubitmcu/qbmcu_exu_alu.v +1716388078 ../../rtl/qubitmcu/qbmcu_exu.v +1715564372 ../../rtl/qubitmcu/qbmcu_defines.v +1717066615 ../../rtl/qubitmcu/qbmcu_decode.v +1715564955 ../../rtl/qubitmcu/qbmcu_datalock.v +1717059339 ../../rtl/qubitmcu/qbmcu.v +1716514718 ../../rtl/perips/qbmcu_busdecoder.v +1716900419 ../../rtl/perips/mcu_regfile.sv +1714632519 ../../rtl/perips/DW03_updn_ctr.v +1714632519 ../../rtl/nco/sin_op.v +1714632519 ../../rtl/nco/pipe_add_48bit.v +1714632519 ../../rtl/nco/pipe_acc_48bit.v +1714632519 ../../rtl/nco/ph2amp.v +1715858907 ../../rtl/nco/p_nco_ch1.v +1714632519 ../../rtl/nco/p_nco.v +1714632519 ../../rtl/nco/nco_ch1.v +1715850409 ../../rtl/nco/nco.v +1714632519 ../../rtl/nco/cos_op.v +1714632519 ../../rtl/nco/coef_s.v +1714632519 ../../rtl/nco/coef_c.v +1716468135 ../../rtl/modem/freqmod.v +1716271781 ../../rtl/modem/baisset.v +1717227147 ../../rtl/modem/ampmod.v +1716468532 ../../rtl/memory/tsmc_dpram.v +1712728963 ../../rtl/memory/tsdn28hpcpuhdb64x32m4mw_170a_ffg0p99v0c.v +1714632519 ../../rtl/memory/tsdn28hpcpuhdb4096x32m4mw_170a_ffg0p99v0c.v +1714632519 ../../rtl/memory/tsdn28hpcpuhdb128x128m4mw_170a_ffg0p99v0c.v +1715856272 ../../rtl/memory/sram_dmux.sv +1715687309 ../../rtl/memory/dpram_model.v +1717068688 ../../rtl/memory/dpram.v +1715825058 ../../rtl/define/chip_undefine.v +1716628532 ../../rtl/define/chip_define.v +1715908982 ../../rtl/debug/debug_top.sv +1715920037 ../../rtl/debug/debug_sample.sv +1717062750 ../../rtl/dac_regfile/dac_regfile.v +1714632519 ../../rtl/comm/sirv_gnrl_xchecker.v +1715740226 ../../rtl/comm/sirv_gnrl_dffs.v +1716898895 ../../rtl/clk/intpll_regfile.v +1715827745 ../../rtl/awg/modout_mux.v +1715653014 ../../rtl/awg/param_lut.sv +1717056803 ../../rtl/awg/ctrl_regfile.v +1717145659 ../../rtl/awg/codeword_decode.v +1717227098 ../../rtl/awg/awg_top.sv +1717144003 ../../rtl/awg/awg_ctrl.v +1716882724 ../../rtl/memory/sram_if.sv +1717125615 files.f +1550753332 /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +1550753332 /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +1551421246 /home/synopsys/vcs/O-2018.09-SP2/linux64/lib/vcsdp_lite.tab +5 +1551422344 /home/synopsys/vcs/O-2018.09-SP2/linux64/lib/libvirsim.so +1551421792 /home/synopsys/vcs/O-2018.09-SP2/linux64/lib/liberrorinf.so +1551421768 /home/synopsys/vcs/O-2018.09-SP2/linux64/lib/libsnpsmalloc.so +1551421789 /home/synopsys/vcs/O-2018.09-SP2/linux64/lib/libvfs.so +1550752033 /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/pli.a +1717383082 simv.daidir +-1 partitionlib diff --git a/tb/chip_top/simv.daidir/_3127_archive_1.so b/tb/chip_top/simv.daidir/_3127_archive_1.so new file mode 100644 index 0000000..124ddb2 Binary files /dev/null and b/tb/chip_top/simv.daidir/_3127_archive_1.so differ diff --git a/tb/chip_top/simv.daidir/_58486_archive_1.so b/tb/chip_top/simv.daidir/_58486_archive_1.so new file mode 100644 index 0000000..e456c6a Binary files /dev/null and b/tb/chip_top/simv.daidir/_58486_archive_1.so differ diff --git a/tb/chip_top/simv.daidir/_csrc0.so b/tb/chip_top/simv.daidir/_csrc0.so new file mode 100644 index 0000000..22e0c5d Binary files /dev/null and b/tb/chip_top/simv.daidir/_csrc0.so differ diff --git a/tb/chip_top/simv.daidir/_prev_archive_1.so b/tb/chip_top/simv.daidir/_prev_archive_1.so new file mode 100644 index 0000000..d35d1cb Binary files /dev/null and b/tb/chip_top/simv.daidir/_prev_archive_1.so differ diff --git a/tb/chip_top/simv.daidir/binmap.sdb b/tb/chip_top/simv.daidir/binmap.sdb new file mode 100644 index 0000000..a512656 Binary files /dev/null and b/tb/chip_top/simv.daidir/binmap.sdb differ diff --git a/tb/chip_top/simv.daidir/build_db b/tb/chip_top/simv.daidir/build_db new file mode 100644 index 0000000..f0a2b99 --- /dev/null +++ b/tb/chip_top/simv.daidir/build_db @@ -0,0 +1,4 @@ +#!/bin/sh -e +# This file is automatically generated by VCS. Any changes you make +# to it will be overwritten the next time VCS is run. +vcs '-full64' '-sverilog' '+lint=TFIPC-L' '+v2k' '-debug_access+all' '+define+DUMP_FSDB' '-lca' '-q' '-timescale=1ns/1ps' '+nospecify' '-P' '/home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab' '/home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/pli.a' '-l' 'compile.log' '-f' 'files.f' -static_dbgen_only -daidir=$1 2>&1 diff --git a/tb/chip_top/simv.daidir/cc/cc_bcode.db b/tb/chip_top/simv.daidir/cc/cc_bcode.db new file mode 100644 index 0000000..807c675 --- /dev/null +++ b/tb/chip_top/simv.daidir/cc/cc_bcode.db @@ -0,0 +1,918 @@ +sid spi_slave +bcid 0 0 WIDTH,1 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 RET +bcid 1 1 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,5 CALL_ARG_VAL,3,0 OPT_CONST,31 WIDTH,1 M_EQU AND RET +bcid 2 2 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,5 OPT_CONST,0 WIDTH,1 CALL_ARG_VAL,3,0 WIDTH,5 CALL_ARG_VAL,4,0 OPT_CONST,1 ADD CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 3 3 WIDTH,1 CALL_ARG_VAL,2,0 NOT CALL_ARG_VAL,3,0 WIDTH,5 CALL_ARG_VAL,4,0 OPT_CONST,26 WIDTH,1 M_EQU AND AND RET +bcid 4 4 WIDTH,1 CALL_ARG_VAL,2,0 NOT CALL_ARG_VAL,3,0 WIDTH,5 CALL_ARG_VAL,4,0 OPT_CONST,31 WIDTH,1 M_EQU AND AND RET +bcid 5 5 WIDTH,5 CALL_ARG_VAL,2,0 OPT_CONST,31 WIDTH,1 M_EQU WIDTH,5 CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 WIDTH,1 M_EQU AND RET +bcid 6 6 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,5 CALL_ARG_VAL,3,0 OPT_CONST,0 WIDTH,1 M_EQU AND RET +bcid 7 7 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,5 CALL_ARG_VAL,3,0 OPT_CONST,30 WIDTH,1 M_EQU CALL_ARG_VAL,4,0 AND AND RET +bcid 8 8 WIDTH,1 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 AND CALL_ARG_VAL,4,0 OR CALL_ARG_VAL,5,0 WIDTH,5 CALL_ARG_VAL,6,0 OPT_CONST,27 WIDTH,1 M_EQU AND AND RET +bcid 9 9 WIDTH,1 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 WIDTH,8 CALL_ARG_VAL,4,0 OPT_CONST,4 ADD CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 CALL_ARG_VAL,5,0 MITECONDNOINSTR,4 RET +bcid 10 10 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,0 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,31 WIDTH,1 SLICE,1 OPT_CONST,0 MITECONDNOINSTR,4 RET +bcid 11 11 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,1 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,30 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,0 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 12 12 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,2 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,29 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,1 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 13 13 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,3 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,28 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,2 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 14 14 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,4 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,27 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,3 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 15 15 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,5 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,26 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,4 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 16 16 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,6 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,25 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,5 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 17 17 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,7 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,24 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,6 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 18 18 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,8 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,23 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,7 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 19 19 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,9 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,22 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,8 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 20 20 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,10 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,21 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,9 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 21 21 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,11 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,20 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,10 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 22 22 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,12 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,19 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,11 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 23 23 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,13 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,18 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,12 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 24 24 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,14 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,17 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,13 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 25 25 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,15 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,16 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,14 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 26 26 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,16 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,15 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,15 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 27 27 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,17 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,14 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,16 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 28 28 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,18 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,13 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,17 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 29 29 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,19 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,12 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,18 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 30 30 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,20 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,11 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,19 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 31 31 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,21 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,10 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,20 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 32 32 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,22 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,9 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,21 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 33 33 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,23 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,8 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,22 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 34 34 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,24 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,7 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,23 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 35 35 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,25 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,6 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,24 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 36 36 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,26 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,5 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,25 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 37 37 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,27 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,4 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,26 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 38 38 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,28 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,3 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,27 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 39 39 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,29 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,2 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,28 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 40 40 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,30 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,1 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,29 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 41 41 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,31 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,0 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,30 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 42 42 WIDTH,2 CALL_ARG_VAL,2,0 OPT_CONST,1 WIDTH,1 M_EQU RET +bcid 43 43 WIDTH,2 CALL_ARG_VAL,2,0 OPT_CONST,2 WIDTH,1 M_EQU RET +bcid 44 44 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,5 CALL_ARG_VAL,3,0 OPT_CONST,31 WIDTH,1 M_EQU AND CALL_ARG_VAL,4,0 OR RET +bcid 45 45 WIDTH,2 CALL_ARG_VAL,2,0 OPT_CONST,1 WIDTH,1 M_EQU CALL_ARG_VAL,3,0 AND WIDTH,5 CALL_ARG_VAL,4,0 OPT_CONST,26 WIDTH,1 M_EQU AND RET +bcid 46 46 WIDTH,2 CALL_ARG_VAL,2,0 OPT_CONST,1 WIDTH,1 M_EQU CALL_ARG_VAL,3,0 WIDTH,5 CALL_ARG_VAL,4,0 OPT_CONST,30 WIDTH,1 M_EQU AND AND RET +bcid 47 47 WIDTH,5 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 WIDTH,1 M_EQU RET +bcid 48 48 WIDTH,5 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 WIDTH,1 M_NEQU RET +bcid 49 49 WIDTH,2 CALL_ARG_VAL,2,0 OPT_CONST,0 WIDTH,1 M_EQU CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 AND AND RET +bcid 50 50 WIDTH,2 CALL_ARG_VAL,2,0 OPT_CONST,1 WIDTH,1 M_EQU CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 AND AND RET +bcid 51 51 WIDTH,2 CALL_ARG_VAL,2,0 OPT_CONST,1 WIDTH,1 M_EQU CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 NOT CALL_ARG_VAL,5,0 AND AND AND RET +bcid 52 52 WIDTH,2 CALL_ARG_VAL,2,0 OPT_CONST,1 WIDTH,1 M_EQU CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 CALL_ARG_VAL,5,0 AND AND AND RET +bcid 53 53 WIDTH,2 CALL_ARG_VAL,2,0 OPT_CONST,2 WIDTH,1 M_EQU CALL_ARG_VAL,3,0 AND RET +bcid 54 54 WIDTH,2 CALL_ARG_VAL,2,0 OPT_CONST,3 WIDTH,1 M_EQU CALL_ARG_VAL,3,0 AND RET +bcid 55 55 WIDTH,2 CALL_ARG_VAL,2,0 OPT_CONST,0 WIDTH,1 M_EQU CALL_ARG_VAL,3,0 AND WIDTH,2 OPT_CONST,1 CALL_ARG_VAL,2,0 OPT_CONST,1 WIDTH,1 M_EQU CALL_ARG_VAL,4,0 AND WIDTH,2 OPT_CONST,0 CALL_ARG_VAL,2,0 OPT_CONST,1 WIDTH,1 M_EQU CALL_ARG_VAL,5,0 AND WIDTH,2 OPT_CONST,2 CALL_ARG_VAL,2,0 OPT_CONST,1 WIDTH,1 M_EQU CALL_ARG_VAL,6,0 AND WIDTH,2 OPT_CONST,3 CALL_ARG_VAL,2,0 OPT_CONST,2 WIDTH,1 M_EQU CALL_ARG_VAL,7,0 AND WIDTH,2 OPT_CONST,0 CALL_ARG_VAL,2,0 OPT_CONST,3 WIDTH,1 M_EQU CALL_ARG_VAL,8,0 AND WIDTH,2 OPT_CONST,0 CALL_ARG_VAL,2,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 56 56 WIDTH,2 CALL_ARG_VAL,2,0 OPT_CONST,3 WIDTH,1 M_EQU WIDTH,2 CALL_ARG_VAL,2,0 OPT_CONST,2 WIDTH,1 M_EQU CALL_ARG_VAL,3,0 AND OR CALL_ARG_VAL,4,0 WIDTH,5 CALL_ARG_VAL,5,0 OPT_CONST,27 WIDTH,1 M_EQU AND AND RET +bcid 57 57 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,25 OPT_CONST,0 WIDTH,1 CALL_ARG_VAL,3,0 WIDTH,25 CALL_ARG_VAL,4,0 WIDTH,1 CALL_ARG_VAL,5,0 WIDTH,25 CALL_ARG_VAL,6,0 OPT_CONST,4 ADD CALL_ARG_VAL,6,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 58 58 WIDTH,2 CALL_ARG_VAL,2,0 OPT_CONST,2 WIDTH,1 M_EQU CALL_ARG_VAL,3,0 WIDTH,5 CALL_ARG_VAL,4,0 OPT_CONST,31 WIDTH,1 M_EQU AND AND RET +bcid 59 59 WIDTH,1 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 WIDTH,5 CALL_ARG_VAL,4,0 OPT_CONST,28 WIDTH,1 M_EQU AND AND RET +bcid 60 60 WIDTH,1 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 WIDTH,5 CALL_ARG_VAL,4,0 OPT_CONST,30 WIDTH,1 M_EQU AND AND RET +bcid 61 61 WIDTH,1 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 WIDTH,5 CALL_ARG_VAL,4,0 OPT_CONST,31 WIDTH,1 M_EQU AND AND RET +bcid 62 62 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,32 CALL_ARG_VAL,3,0 WIDTH,2 CALL_ARG_VAL,4,0 OPT_CONST,3 WIDTH,1 M_EQU CALL_ARG_VAL,5,0 AND WIDTH,32 CALL_ARG_VAL,6,0 OPT_CONST,0 WIDTH,31 SLICE,1 WIDTH,1 OPT_CONST,0 WIDTH,32 CONCATENATE,2 CALL_ARG_VAL,6,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 63 63 WIDTH,2 CALL_ARG_VAL,2,0 OPT_CONST,3 WIDTH,1 M_EQU RET +sid system_regfile +bcid 64 0 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,6 WIDTH,26 SLICE,1 WIDTH,1 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,5,0 OPT_CONST,6 WIDTH,26 SLICE,1 WIDTH,1 CALL_ARG_VAL,6,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,7,0 OPT_CONST,6 WIDTH,26 SLICE,1 WIDTH,1 CALL_ARG_VAL,8,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,9,0 OPT_CONST,6 WIDTH,26 SLICE,1 WIDTH,1 CALL_ARG_VAL,10,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,11,0 OPT_CONST,6 WIDTH,26 SLICE,1 WIDTH,1 CALL_ARG_VAL,12,0 OPT_CONST,1 EQU WIDTH,26 OPT_CONST,0 WIDTH,1 CALL_ARG_VAL,13,0 OPT_CONST,1 EQU WIDTH,26 OPT_CONST,8423456 WIDTH,1 CALL_ARG_VAL,14,0 OPT_CONST,1 EQU WIDTH,26 OPT_CONST,22367569 WIDTH,1 CALL_ARG_VAL,15,0 OPT_CONST,1 EQU WIDTH,26 OPT_CONST,17128733 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 65 1 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 EQU WIDTH,6 CALL_ARG_VAL,3,0 WIDTH,1 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,5,0 OPT_CONST,0 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,6,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,7,0 OPT_CONST,0 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,8,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,9,0 OPT_CONST,0 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,10,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,11,0 OPT_CONST,0 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,12,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,13,0 OPT_CONST,0 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,14,0 OPT_CONST,1 EQU WIDTH,6 OPT_CONST,1 WIDTH,1 CALL_ARG_VAL,15,0 OPT_CONST,1 EQU WIDTH,6 OPT_CONST,49 WIDTH,1 CALL_ARG_VAL,16,0 OPT_CONST,1 EQU WIDTH,6 OPT_CONST,3 WIDTH,1 CALL_ARG_VAL,17,0 OPT_CONST,1 EQU WIDTH,6 OPT_CONST,3 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 66 2 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,0 WIDTH,1 M_EQU RET +bcid 67 3 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,1 WIDTH,1 M_EQU RET +bcid 68 4 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,2 WIDTH,1 M_EQU RET +bcid 69 5 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,3 WIDTH,1 M_EQU RET +bcid 70 6 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,4 WIDTH,1 M_EQU RET +bcid 71 7 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,5 WIDTH,1 M_EQU RET +bcid 72 8 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,6 WIDTH,1 M_EQU RET +bcid 73 9 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,16 WIDTH,1 M_EQU RET +bcid 74 10 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,7 WIDTH,1 M_EQU RET +bcid 75 11 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,8 WIDTH,1 M_EQU RET +bcid 76 12 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,9 WIDTH,1 M_EQU RET +bcid 77 13 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,10 WIDTH,1 M_EQU RET +bcid 78 14 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,11 WIDTH,1 M_EQU RET +bcid 79 15 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,12 WIDTH,1 M_EQU RET +bcid 80 16 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,13 WIDTH,1 M_EQU RET +bcid 81 17 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,32 CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 OPT_CONST,1 SUBTRACT WIDTH,1 M_EQU AND RET +bcid 82 18 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,0 WIDTH,1 CALL_ARG_VAL,3,0 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,1 ADD CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 83 19 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,0 WIDTH,1 M_NEQU RET +sid qbmcu_datalatch +bcid 84 0 WIDTH,1 CALL_ARG_VAL,2,0 NOT WIDTH,3 CALL_ARG_VAL,3,0 PARAMETER,4 WIDTH,1 M_EQU AND RET +bcid 85 1 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,32 MULTI_CONCATENATE,1,32 CALL_ARG_VAL,3,0 AND RET +bcid 86 2 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,19 MULTI_CONCATENATE,1,19 CALL_ARG_VAL,3,0 AND RET +sid qbmcu +bcid 87 0 WIDTH,32 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 ADD RET +bcid 88 1 WIDTH,5 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,2 WIDTH,2 SLICE,1 OPT_CONST,0 WIDTH,1 M_EQU RET +bcid 89 2 WIDTH,5 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,2 WIDTH,2 SLICE,1 OPT_CONST,1 WIDTH,1 M_EQU RET +bcid 90 3 WIDTH,5 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,2 WIDTH,2 SLICE,1 OPT_CONST,2 WIDTH,1 M_EQU RET +bcid 91 4 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,0 WIDTH,1 SLICE,1 AND CALL_ARG_VAL,4,0 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,0 WIDTH,2 SLICE,1 OPT_CONST,0 WIDTH,1 M_NEQU AND OR RET +bcid 92 5 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,32 MULTI_CONCATENATE,1,32 WIDTH,8 CALL_ARG_VAL,3,0 WIDTH,32 MULTI_CONCATENATE,1,4 AND WIDTH,1 CALL_ARG_VAL,4,0 WIDTH,32 MULTI_CONCATENATE,1,32 WIDTH,16 CALL_ARG_VAL,5,0 WIDTH,32 MULTI_CONCATENATE,1,2 AND WIDTH,1 CALL_ARG_VAL,6,0 WIDTH,32 MULTI_CONCATENATE,1,32 CALL_ARG_VAL,7,0 AND OR OR RET +bcid 93 6 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,4 MULTI_CONCATENATE,1,4 OPT_CONST,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,0 WIDTH,2 SLICE,1 WIDTH,4 SHIFT_L AND WIDTH,1 CALL_ARG_VAL,4,0 WIDTH,4 MULTI_CONCATENATE,1,4 OPT_CONST,3 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,1 WIDTH,1 SLICE,1 OPT_CONST,0 WIDTH,2 CONCATENATE,2 WIDTH,4 SHIFT_L AND WIDTH,1 CALL_ARG_VAL,5,0 WIDTH,4 MULTI_CONCATENATE,1,4 OR OR RET +bcid 94 7 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,5 MULTI_CONCATENATE,1,5 CALL_ARG_VAL,3,0 AND RET +bcid 95 8 WIDTH,5 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,3 WIDTH,2 SLICE,1 OPT_CONST,0 WIDTH,1 M_NEQU RET +bcid 96 9 WIDTH,13 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,11 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 RET +bcid 97 10 WIDTH,13 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,10 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 RET +bcid 98 11 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,13 MULTI_CONCATENATE,1,13 CALL_ARG_VAL,3,0 AND RET +bcid 99 12 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,32 CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 RET +bcid 100 13 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,4 CALL_ARG_VAL,3,0 MITECONDNOINSTR,4 RET +bcid 101 14 WIDTH,9 CALL_ARG_VAL,2,0 OPT_CONST,257 AND OPT_CONST,0 WIDTH,1 M_NEQU RET +bcid 102 15 WIDTH,9 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 OPT_CONST,1 CALL_ARG_VAL,3,0 MITECONDNOINSTR,4 RET +bcid 103 16 WIDTH,9 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 RET +bcid 104 17 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,9 MULTI_CONCATENATE,1,9 CALL_ARG_VAL,3,0 AND RET +bcid 105 18 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,32 MULTI_CONCATENATE,1,32 WIDTH,10 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,4 WIDTH,1 SLICE,1 WIDTH,10 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,3 WIDTH,1 SLICE,1 OR WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,0 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,1 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,2 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,3 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,4 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,5 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,6 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,7 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,8 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,9 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,10 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,11 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,12 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,13 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,14 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,15 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,16 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,17 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,18 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,19 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,20 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,21 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,22 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,23 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,24 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,25 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,26 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,27 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,28 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,29 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,30 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,31 WIDTH,1 SLICE,1 WIDTH,32 CONCATENATE,32 CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 AND RET +bcid 106 19 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,5 MULTI_CONCATENATE,1,5 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,0 WIDTH,5 SLICE,1 AND RET +bcid 107 20 WIDTH,32 CALL_ARG_VAL,2,0 WIDTH,5 CALL_ARG_VAL,3,0 WIDTH,32 SHIFT_L RET +bcid 108 21 WIDTH,32 OPT_CONST,-1 WIDTH,5 CALL_ARG_VAL,2,0 WIDTH,32 SHIFT_R RET +bcid 109 22 WIDTH,32 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 AND CALL_ARG_VAL,4,0 OPT_CONST,31 WIDTH,1 SLICE,1 WIDTH,32 MULTI_CONCATENATE,1,32 CALL_ARG_VAL,3,0 NOT AND OR RET +bcid 110 23 WIDTH,1 CALL_ARG_VAL,2,0 NOT WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,31 WIDTH,1 SLICE,1 AND WIDTH,32 CALL_ARG_VAL,3,0 WIDTH,33 CONCATENATE,2 RET +bcid 111 24 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,33 MULTI_CONCATENATE,1,33 CALL_ARG_VAL,3,0 AND RET +bcid 112 25 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,33 MULTI_CONCATENATE,1,33 WIDTH,1 CALL_ARG_VAL,3,0 WIDTH,33 CALL_ARG_VAL,4,0 NOT CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 AND RET +bcid 113 26 WIDTH,33 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 WIDTH,1 CALL_ARG_VAL,4,0 WIDTH,33 PAD ADD ADD RET +bcid 114 27 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,32 MULTI_CONCATENATE,1,32 CALL_ARG_VAL,3,0 AND RET +bcid 115 28 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,0 WIDTH,1 M_NEQU RET +bcid 116 29 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,32 MULTI_CONCATENATE,1,32 OPT_CONST,1 AND RET +bcid 117 30 WIDTH,10 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,5 WIDTH,1 SLICE,1 WIDTH,32 MULTI_CONCATENATE,1,32 CALL_ARG_VAL,3,0 AND WIDTH,10 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,6 WIDTH,1 SLICE,1 WIDTH,32 MULTI_CONCATENATE,1,32 CALL_ARG_VAL,4,0 AND OR WIDTH,10 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 WIDTH,32 MULTI_CONCATENATE,1,32 CALL_ARG_VAL,5,0 AND WIDTH,1 CALL_ARG_VAL,6,0 WIDTH,32 MULTI_CONCATENATE,1,32 WIDTH,33 CALL_ARG_VAL,7,0 WIDTH,32 OPT_CONST,0 SLICE,1 AND OR OR WIDTH,10 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,3 WIDTH,1 SLICE,1 WIDTH,32 MULTI_CONCATENATE,1,32 CALL_ARG_VAL,8,0 AND WIDTH,10 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,2 WIDTH,1 SLICE,1 WIDTH,32 MULTI_CONCATENATE,1,32 CALL_ARG_VAL,9,0 AND OR WIDTH,10 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,4 WIDTH,1 SLICE,1 WIDTH,32 MULTI_CONCATENATE,1,32 CALL_ARG_VAL,10,0 AND WIDTH,10 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,9 WIDTH,1 SLICE,1 WIDTH,32 MULTI_CONCATENATE,1,32 CALL_ARG_VAL,11,0 AND WIDTH,1 CALL_ARG_VAL,12,0 WIDTH,32 MULTI_CONCATENATE,1,32 CALL_ARG_VAL,13,0 AND OR OR OR OR RET +bcid 118 31 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,32 MULTI_CONCATENATE,1,32 CALL_ARG_VAL,3,0 AND WIDTH,1 CALL_ARG_VAL,4,0 WIDTH,32 MULTI_CONCATENATE,1,32 CALL_ARG_VAL,5,0 AND OR RET +bcid 119 32 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,32 MULTI_CONCATENATE,1,32 CALL_ARG_VAL,3,0 AND WIDTH,1 CALL_ARG_VAL,4,0 WIDTH,32 MULTI_CONCATENATE,1,32 CALL_ARG_VAL,5,0 AND OR WIDTH,1 CALL_ARG_VAL,6,0 WIDTH,32 MULTI_CONCATENATE,1,32 CALL_ARG_VAL,7,0 AND WIDTH,1 CALL_ARG_VAL,8,0 WIDTH,32 MULTI_CONCATENATE,1,32 CALL_ARG_VAL,9,0 AND OR OR RET +bcid 120 33 WIDTH,3 CALL_ARG_VAL,2,0 OPT_CONST,0 WIDTH,1 M_EQU CALL_ARG_VAL,3,0 AND WIDTH,3 OPT_CONST,1 CALL_ARG_VAL,2,0 OPT_CONST,1 WIDTH,1 M_EQU CALL_ARG_VAL,4,0 AND WIDTH,3 OPT_CONST,2 CALL_ARG_VAL,2,0 OPT_CONST,2 WIDTH,1 M_EQU CALL_ARG_VAL,5,0 AND WIDTH,3 OPT_CONST,3 CALL_ARG_VAL,2,0 OPT_CONST,3 WIDTH,1 M_EQU CALL_ARG_VAL,6,0 AND WIDTH,3 OPT_CONST,0 CALL_ARG_VAL,2,0 OPT_CONST,3 WIDTH,1 M_EQU CALL_ARG_VAL,7,0 AND WIDTH,3 OPT_CONST,1 CALL_ARG_VAL,2,0 OPT_CONST,3 WIDTH,1 M_EQU CALL_ARG_VAL,8,0 AND WIDTH,3 OPT_CONST,4 CALL_ARG_VAL,2,0 OPT_CONST,4 WIDTH,1 M_EQU CALL_ARG_VAL,9,0 AND WIDTH,3 OPT_CONST,1 CALL_ARG_VAL,2,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 121 34 WIDTH,3 CALL_ARG_VAL,2,0 OPT_CONST,0 WIDTH,1 M_EQU CALL_ARG_VAL,3,0 AND RET +bcid 122 35 WIDTH,3 CALL_ARG_VAL,2,0 OPT_CONST,1 WIDTH,1 M_EQU RET +bcid 123 36 WIDTH,3 CALL_ARG_VAL,2,0 OPT_CONST,2 WIDTH,1 M_EQU RET +bcid 124 37 WIDTH,3 CALL_ARG_VAL,2,0 OPT_CONST,3 WIDTH,1 M_EQU CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 CALL_ARG_VAL,5,0 OR CALL_ARG_VAL,6,0 OR OR NOT AND RET +bcid 125 38 WIDTH,3 CALL_ARG_VAL,2,0 OPT_CONST,3 WIDTH,1 M_EQU CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 CALL_ARG_VAL,5,0 OR CALL_ARG_VAL,6,0 OR NOT AND AND RET +bcid 126 39 WIDTH,3 CALL_ARG_VAL,2,0 OPT_CONST,3 WIDTH,1 M_EQU CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 CALL_ARG_VAL,5,0 OR OR AND RET +bcid 127 40 WIDTH,3 CALL_ARG_VAL,2,0 OPT_CONST,4 WIDTH,1 M_EQU CALL_ARG_VAL,3,0 AND RET +bcid 128 41 WIDTH,1 CALL_ARG_VAL,2,0 NOT CALL_ARG_VAL,3,0 OR WIDTH,32 CALL_ARG_VAL,4,0 CALL_ARG_VAL,5,0 MITECONDNOINSTR,4 RET +bcid 129 42 WIDTH,1 CALL_ARG_VAL,2,0 NOT CALL_ARG_VAL,3,0 OR WIDTH,32 MULTI_CONCATENATE,1,32 NOT OPT_CONST,4 AND RET +bcid 130 43 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,1 WIDTH,31 SLICE,1 WIDTH,1 OPT_CONST,0 WIDTH,32 CONCATENATE,2 CALL_ARG_VAL,4,0 OPT_CONST,1 WIDTH,31 SLICE,1 WIDTH,1 OPT_CONST,0 WIDTH,32 CONCATENATE,2 MITECONDNOINSTR,4 RET +bcid 131 44 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,0 WIDTH,2 SLICE,1 OPT_CONST,3 WIDTH,1 M_EQU RET +bcid 132 45 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,2 WIDTH,3 SLICE,1 OPT_CONST,7 WIDTH,1 M_NEQU CALL_ARG_VAL,3,0 AND RET +bcid 133 46 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,2 WIDTH,3 SLICE,1 OPT_CONST,0 WIDTH,1 M_EQU RET +bcid 134 47 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,2 WIDTH,3 SLICE,1 OPT_CONST,1 WIDTH,1 M_EQU RET +bcid 135 48 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,2 WIDTH,3 SLICE,1 OPT_CONST,2 WIDTH,1 M_EQU RET +bcid 136 49 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,2 WIDTH,3 SLICE,1 OPT_CONST,3 WIDTH,1 M_EQU RET +bcid 137 50 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,2 WIDTH,3 SLICE,1 OPT_CONST,4 WIDTH,1 M_EQU RET +bcid 138 51 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,2 WIDTH,3 SLICE,1 OPT_CONST,5 WIDTH,1 M_EQU RET +bcid 139 52 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,2 WIDTH,3 SLICE,1 OPT_CONST,7 WIDTH,1 M_EQU RET +bcid 140 53 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,5 WIDTH,2 SLICE,1 OPT_CONST,0 WIDTH,1 M_EQU RET +bcid 141 54 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,5 WIDTH,2 SLICE,1 OPT_CONST,1 WIDTH,1 M_EQU RET +bcid 142 55 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,5 WIDTH,2 SLICE,1 OPT_CONST,3 WIDTH,1 M_EQU RET +bcid 143 56 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,25 WIDTH,7 SLICE,1 OPT_CONST,0 WIDTH,1 M_EQU RET +bcid 144 57 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,25 WIDTH,7 SLICE,1 OPT_CONST,32 WIDTH,1 M_EQU RET +bcid 145 58 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,25 WIDTH,7 SLICE,1 OPT_CONST,127 WIDTH,1 M_EQU RET +bcid 146 59 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,15 WIDTH,5 SLICE,1 OPT_CONST,0 WIDTH,1 M_EQU RET +bcid 147 60 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,20 WIDTH,5 SLICE,1 OPT_CONST,0 WIDTH,1 M_EQU RET +bcid 148 61 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,7 WIDTH,5 SLICE,1 OPT_CONST,0 WIDTH,1 M_EQU RET +bcid 149 62 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,15 WIDTH,5 SLICE,1 OPT_CONST,31 WIDTH,1 M_EQU RET +bcid 150 63 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,20 WIDTH,5 SLICE,1 OPT_CONST,31 WIDTH,1 M_EQU RET +bcid 151 64 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,7 WIDTH,5 SLICE,1 OPT_CONST,31 WIDTH,1 M_EQU RET +bcid 152 65 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,8 CALL_ARG_VAL,3,0 OPT_CONST,129 AND OPT_CONST,0 WIDTH,1 M_NEQU OR RET +bcid 153 66 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,4 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,26 WIDTH,6 SLICE,1 OPT_CONST,0 WIDTH,1 M_EQU AND AND RET +bcid 154 67 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,4 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,3 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,26 WIDTH,6 SLICE,1 OPT_CONST,0 WIDTH,1 M_EQU AND AND RET +bcid 155 68 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,4 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,3 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,26 WIDTH,6 SLICE,1 OPT_CONST,16 WIDTH,1 M_EQU AND AND RET +bcid 156 69 WIDTH,8 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,1 WIDTH,3 SLICE,1 OPT_CONST,0 WIDTH,1 M_NEQU CALL_ARG_VAL,3,0 NOT AND RET +bcid 157 70 WIDTH,1 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 AND CALL_ARG_VAL,4,0 WIDTH,32 CALL_ARG_VAL,5,0 OPT_CONST,20 WIDTH,12 SLICE,1 OPT_CONST,0 WIDTH,1 M_EQU AND AND RET +bcid 158 71 WIDTH,1 CALL_ARG_VAL,2,0 NOT CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 OR WIDTH,4 CALL_ARG_VAL,5,0 OPT_CONST,13 AND OPT_CONST,0 WIDTH,1 M_NEQU OR AND RET +bcid 159 72 WIDTH,6 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 OPT_CONST,0 WIDTH,1 M_NEQU RET +bcid 160 73 WIDTH,1 CALL_ARG_VAL,2,0 NOT WIDTH,5 CALL_ARG_VAL,3,0 OPT_CONST,0 WIDTH,1 M_NEQU AND RET +bcid 161 74 WIDTH,1 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 AND CALL_ARG_VAL,4,0 WIDTH,4 CALL_ARG_VAL,5,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 AND AND CALL_ARG_VAL,6,0 CALL_ARG_VAL,7,0 AND CALL_ARG_VAL,8,0 WIDTH,32 CALL_ARG_VAL,9,0 OPT_CONST,0 WIDTH,2 SLICE,1 OPT_CONST,0 WIDTH,1 M_EQU AND AND AND RET +bcid 162 75 WIDTH,1 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 AND CALL_ARG_VAL,4,0 WIDTH,4 CALL_ARG_VAL,5,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 AND AND CALL_ARG_VAL,6,0 CALL_ARG_VAL,7,0 AND CALL_ARG_VAL,8,0 WIDTH,32 CALL_ARG_VAL,9,0 OPT_CONST,0 WIDTH,2 SLICE,1 OPT_CONST,3 WIDTH,1 M_EQU AND AND AND RET +bcid 163 76 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,31 WIDTH,1 SLICE,1 WIDTH,20 MULTI_CONCATENATE,1,20 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,20 WIDTH,12 SLICE,1 WIDTH,32 CONCATENATE,2 RET +bcid 164 77 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,31 WIDTH,1 SLICE,1 WIDTH,20 MULTI_CONCATENATE,1,20 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,25 WIDTH,7 SLICE,1 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,7 WIDTH,5 SLICE,1 WIDTH,32 CONCATENATE,3 RET +bcid 165 78 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,31 WIDTH,1 SLICE,1 WIDTH,20 MULTI_CONCATENATE,1,20 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,7 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,25 WIDTH,6 SLICE,1 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,8 WIDTH,4 SLICE,1 WIDTH,1 OPT_CONST,0 WIDTH,32 CONCATENATE,5 RET +bcid 166 79 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,31 WIDTH,1 SLICE,1 WIDTH,12 MULTI_CONCATENATE,1,12 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,12 WIDTH,8 SLICE,1 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,20 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,21 WIDTH,10 SLICE,1 WIDTH,1 OPT_CONST,0 WIDTH,32 CONCATENATE,5 RET +bcid 167 80 WIDTH,4 CALL_ARG_VAL,2,0 OPT_CONST,5 AND OPT_CONST,0 WIDTH,1 M_NEQU RET +bcid 168 81 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,32 MULTI_CONCATENATE,1,32 CALL_ARG_VAL,3,0 AND WIDTH,1 CALL_ARG_VAL,4,0 WIDTH,32 MULTI_CONCATENATE,1,32 CALL_ARG_VAL,5,0 AND WIDTH,1 CALL_ARG_VAL,6,0 WIDTH,32 MULTI_CONCATENATE,1,32 CALL_ARG_VAL,7,0 AND OR OR WIDTH,1 CALL_ARG_VAL,8,0 WIDTH,32 MULTI_CONCATENATE,1,32 CALL_ARG_VAL,9,0 AND WIDTH,1 CALL_ARG_VAL,10,0 WIDTH,32 MULTI_CONCATENATE,1,32 CALL_ARG_VAL,11,0 AND WIDTH,1 CALL_ARG_VAL,12,0 WIDTH,32 MULTI_CONCATENATE,1,32 CALL_ARG_VAL,13,0 AND OR OR OR RET +bcid 169 82 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,19 MULTI_CONCATENATE,1,19 WIDTH,1 OPT_CONST,0 WIDTH,18 CALL_ARG_VAL,3,0 WIDTH,19 CONCATENATE,2 AND WIDTH,1 CALL_ARG_VAL,4,0 WIDTH,19 MULTI_CONCATENATE,1,19 WIDTH,9 OPT_CONST,0 WIDTH,10 CALL_ARG_VAL,5,0 WIDTH,19 CONCATENATE,2 AND OR WIDTH,1 CALL_ARG_VAL,6,0 WIDTH,19 MULTI_CONCATENATE,1,19 WIDTH,6 OPT_CONST,0 WIDTH,13 CALL_ARG_VAL,7,0 WIDTH,19 CONCATENATE,2 AND WIDTH,1 CALL_ARG_VAL,8,0 WIDTH,19 MULTI_CONCATENATE,1,19 WIDTH,9 OPT_CONST,0 WIDTH,10 CALL_ARG_VAL,9,0 WIDTH,19 CONCATENATE,2 AND OR OR RET +bcid 170 83 WIDTH,1 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 AND WIDTH,4 MULTI_CONCATENATE,1,4 CALL_ARG_VAL,4,0 AND RET +bcid 171 84 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,4 MULTI_CONCATENATE,1,4 CALL_ARG_VAL,3,0 AND RET +bcid 172 85 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,2 MULTI_CONCATENATE,1,2 WIDTH,4 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,0 WIDTH,2 SLICE,1 AND RET +bcid 173 86 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,4 MULTI_CONCATENATE,1,4 CALL_ARG_VAL,3,0 AND RET +bcid 174 87 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,2 MULTI_CONCATENATE,1,2 WIDTH,4 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,0 WIDTH,2 SLICE,1 AND RET +bcid 175 88 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,2 MULTI_CONCATENATE,1,2 WIDTH,4 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,2 WIDTH,2 SLICE,1 AND RET +bcid 176 89 WIDTH,1 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 WIDTH,32 CALL_ARG_VAL,5,0 OPT_CONST,-1 SUBTRACT CALL_ARG_VAL,5,0 OPT_CONST,-1 ADD MITECONDNOINSTR,4 CALL_ARG_VAL,5,0 MITECONDNOINSTR,4 CALL_ARG_VAL,6,0 NOT NOT MITECONDNOINSTR,4 RET +bcid 177 90 WIDTH,32 CALL_ARG_VAL,2,0 WIDTH,1 CALL_ARG_VAL,3,0 WIDTH,32 MULTI_CONCATENATE,1,32 WIDTH,1 M_EQU RET +bcid 178 91 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,1 SUBTRACT RET +bcid 179 92 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,10 MULTI_CONCATENATE,1,10 CALL_ARG_VAL,3,0 AND RET +bcid 180 93 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,6 MULTI_CONCATENATE,1,6 CALL_ARG_VAL,3,0 AND RET +sid qbmcu_busdecoder +bcid 181 0 WIDTH,16 CALL_ARG_VAL,2,0 OPT_CONST,16 WIDTH,1 M_EQU RET +bcid 182 1 WIDTH,16 CALL_ARG_VAL,2,0 OPT_CONST,32 WIDTH,1 M_EQU RET +bcid 183 2 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,4 MULTI_CONCATENATE,1,4 CALL_ARG_VAL,3,0 AND RET +bcid 184 3 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,32 MULTI_CONCATENATE,1,32 CALL_ARG_VAL,3,0 AND RET +bcid 185 4 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,32 MULTI_CONCATENATE,1,32 CALL_ARG_VAL,3,0 AND WIDTH,1 CALL_ARG_VAL,4,0 WIDTH,32 MULTI_CONCATENATE,1,32 CALL_ARG_VAL,5,0 AND OR RET +sid mcu_regfile +bcid 186 0 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,4,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,5,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,6,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,7,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,8,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,9,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,10,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,11,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,12,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,13,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,14,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,15,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,16,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,17,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,18,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,19,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,20,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,21,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,22,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,23,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,24,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,25,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,26,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU CALL_ARG_VAL,27,0 CALL_ARG_VAL,28,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,29,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,30,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,31,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,32,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,33,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,34,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,35,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,36,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,37,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,38,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,39,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,40,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,41,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,42,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,43,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,44,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,45,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,46,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,47,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,48,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,49,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,50,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,51,0 OPT_CONST,0 WIDTH,1 SLICE,1 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 187 1 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,2 WIDTH,14 SLICE,1 WIDTH,1 CALL_ARG_VAL,4,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,5,0 WIDTH,32 OPT_CONST,2 WIDTH,14 SLICE,1 WIDTH,1 CALL_ARG_VAL,6,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,7,0 WIDTH,32 OPT_CONST,2 WIDTH,14 SLICE,1 WIDTH,1 CALL_ARG_VAL,8,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,9,0 WIDTH,32 OPT_CONST,2 WIDTH,14 SLICE,1 WIDTH,1 CALL_ARG_VAL,10,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,11,0 WIDTH,32 OPT_CONST,2 WIDTH,14 SLICE,1 WIDTH,1 CALL_ARG_VAL,12,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,13,0 WIDTH,32 OPT_CONST,2 WIDTH,14 SLICE,1 WIDTH,1 CALL_ARG_VAL,14,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,15,0 WIDTH,32 OPT_CONST,2 WIDTH,14 SLICE,1 WIDTH,1 CALL_ARG_VAL,16,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,17,0 WIDTH,32 OPT_CONST,2 WIDTH,14 SLICE,1 WIDTH,1 CALL_ARG_VAL,18,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,19,0 WIDTH,32 OPT_CONST,2 WIDTH,14 SLICE,1 WIDTH,1 CALL_ARG_VAL,20,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,21,0 WIDTH,32 OPT_CONST,2 WIDTH,14 SLICE,1 WIDTH,1 CALL_ARG_VAL,22,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,23,0 WIDTH,32 OPT_CONST,2 WIDTH,14 SLICE,1 WIDTH,1 CALL_ARG_VAL,24,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,25,0 WIDTH,32 OPT_CONST,2 WIDTH,14 SLICE,1 WIDTH,1 CALL_ARG_VAL,26,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,27,0 WIDTH,32 OPT_CONST,2 WIDTH,14 SLICE,1 WIDTH,1 CALL_ARG_VAL,28,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,29,0 OPT_CONST,2 WIDTH,14 SLICE,1 WIDTH,1 CALL_ARG_VAL,30,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,31,0 OPT_CONST,2 WIDTH,14 SLICE,1 WIDTH,1 CALL_ARG_VAL,32,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,33,0 OPT_CONST,2 WIDTH,14 SLICE,1 WIDTH,1 CALL_ARG_VAL,34,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,35,0 OPT_CONST,2 WIDTH,14 SLICE,1 WIDTH,1 CALL_ARG_VAL,36,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,37,0 OPT_CONST,2 WIDTH,14 SLICE,1 WIDTH,1 CALL_ARG_VAL,38,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,39,0 OPT_CONST,2 WIDTH,14 SLICE,1 WIDTH,1 CALL_ARG_VAL,40,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,41,0 OPT_CONST,2 WIDTH,14 SLICE,1 WIDTH,1 CALL_ARG_VAL,42,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,43,0 OPT_CONST,2 WIDTH,14 SLICE,1 WIDTH,1 CALL_ARG_VAL,44,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,45,0 OPT_CONST,2 WIDTH,14 SLICE,1 WIDTH,1 CALL_ARG_VAL,46,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,47,0 OPT_CONST,2 WIDTH,14 SLICE,1 WIDTH,1 CALL_ARG_VAL,48,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,49,0 OPT_CONST,2 WIDTH,14 SLICE,1 WIDTH,1 CALL_ARG_VAL,50,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,51,0 OPT_CONST,2 WIDTH,14 SLICE,1 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 188 2 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,4,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,5,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,6,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,7,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,8,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,9,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,10,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,11,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,12,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,13,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,14,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,15,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,16,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,17,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,18,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,19,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,20,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,21,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,22,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,23,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,24,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,25,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,26,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,27,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,28,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,29,0 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,30,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,31,0 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,32,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,33,0 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,34,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,35,0 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,36,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,37,0 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,38,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,39,0 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,40,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,41,0 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,42,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,43,0 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,44,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,45,0 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,46,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,47,0 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,48,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,49,0 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,50,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,51,0 OPT_CONST,1 WIDTH,1 SLICE,1 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 189 3 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,16 WIDTH,16 SLICE,1 WIDTH,1 CALL_ARG_VAL,4,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,5,0 OPT_CONST,16 WIDTH,16 SLICE,1 WIDTH,1 CALL_ARG_VAL,6,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,7,0 OPT_CONST,16 WIDTH,16 SLICE,1 WIDTH,1 CALL_ARG_VAL,8,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,9,0 OPT_CONST,16 WIDTH,16 SLICE,1 WIDTH,1 CALL_ARG_VAL,10,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,11,0 OPT_CONST,16 WIDTH,16 SLICE,1 WIDTH,1 CALL_ARG_VAL,12,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,13,0 OPT_CONST,16 WIDTH,16 SLICE,1 WIDTH,1 CALL_ARG_VAL,14,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,15,0 OPT_CONST,16 WIDTH,16 SLICE,1 WIDTH,1 CALL_ARG_VAL,16,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,17,0 OPT_CONST,16 WIDTH,16 SLICE,1 WIDTH,1 CALL_ARG_VAL,18,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,19,0 OPT_CONST,16 WIDTH,16 SLICE,1 WIDTH,1 CALL_ARG_VAL,20,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,21,0 OPT_CONST,16 WIDTH,16 SLICE,1 WIDTH,1 CALL_ARG_VAL,22,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,23,0 OPT_CONST,16 WIDTH,16 SLICE,1 WIDTH,1 CALL_ARG_VAL,24,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,25,0 OPT_CONST,16 WIDTH,16 SLICE,1 WIDTH,1 CALL_ARG_VAL,26,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,27,0 OPT_CONST,16 WIDTH,16 SLICE,1 WIDTH,1 CALL_ARG_VAL,28,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,29,0 OPT_CONST,16 WIDTH,16 SLICE,1 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 190 4 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,2 WIDTH,14 SLICE,1 WIDTH,1 CALL_ARG_VAL,4,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,5,0 OPT_CONST,2 WIDTH,14 SLICE,1 WIDTH,1 CALL_ARG_VAL,6,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,7,0 WIDTH,32 OPT_CONST,2 WIDTH,14 SLICE,1 WIDTH,1 CALL_ARG_VAL,8,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,9,0 WIDTH,32 OPT_CONST,2 WIDTH,14 SLICE,1 WIDTH,1 CALL_ARG_VAL,10,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,11,0 WIDTH,32 OPT_CONST,2 WIDTH,14 SLICE,1 WIDTH,1 CALL_ARG_VAL,12,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,13,0 WIDTH,32 OPT_CONST,2 WIDTH,14 SLICE,1 CALL_ARG_VAL,14,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 191 5 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,2 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,4,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,5,0 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,6,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,7,0 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,8,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,9,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,10,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,11,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,12,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,13,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,14,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,15,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,16,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 192 6 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,2 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,4,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,5,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,6,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,7,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,8,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,9,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,10,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,11,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,12,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,13,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,14,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,15,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,16,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,17,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,18,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 193 7 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,0 WIDTH,1 M_EQU RET +bcid 194 8 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,1 WIDTH,1 M_EQU RET +bcid 195 9 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,2 WIDTH,1 M_EQU RET +bcid 196 10 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,3 WIDTH,1 M_EQU RET +bcid 197 11 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,4 WIDTH,1 M_EQU RET +bcid 198 12 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,5 WIDTH,1 M_EQU RET +bcid 199 13 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,6 WIDTH,1 M_EQU RET +bcid 200 14 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,7 WIDTH,1 M_EQU RET +bcid 201 15 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,16 WIDTH,1 M_EQU RET +bcid 202 16 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,17 WIDTH,1 M_EQU RET +bcid 203 17 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,18 WIDTH,1 M_EQU RET +bcid 204 18 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,19 WIDTH,1 M_EQU RET +bcid 205 19 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,20 WIDTH,1 M_EQU RET +bcid 206 20 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,21 WIDTH,1 M_EQU RET +bcid 207 21 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,22 WIDTH,1 M_EQU RET +bcid 208 22 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,23 WIDTH,1 M_EQU RET +bcid 209 23 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,24 WIDTH,1 M_EQU RET +bcid 210 24 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,25 WIDTH,1 M_EQU RET +bcid 211 25 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,26 WIDTH,1 M_EQU RET +bcid 212 26 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,27 WIDTH,1 M_EQU RET +bcid 213 27 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,28 WIDTH,1 M_EQU RET +bcid 214 28 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,29 WIDTH,1 M_EQU RET +bcid 215 29 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,30 WIDTH,1 M_EQU RET +bcid 216 30 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,31 WIDTH,1 M_EQU RET +bcid 217 31 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,32 WIDTH,1 M_EQU RET +bcid 218 32 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,33 WIDTH,1 M_EQU RET +bcid 219 33 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,34 WIDTH,1 M_EQU RET +bcid 220 34 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,35 WIDTH,1 M_EQU RET +bcid 221 35 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,36 WIDTH,1 M_EQU RET +bcid 222 36 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,37 WIDTH,1 M_EQU RET +bcid 223 37 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,38 WIDTH,1 M_EQU RET +bcid 224 38 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,39 WIDTH,1 M_EQU RET +bcid 225 39 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,40 WIDTH,1 M_EQU RET +bcid 226 40 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,8 CALL_ARG_VAL,3,0 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,24 WIDTH,8 SLICE,1 MITECONDNOINSTR,4 RET +bcid 227 41 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,8 CALL_ARG_VAL,3,0 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,16 WIDTH,8 SLICE,1 MITECONDNOINSTR,4 RET +bcid 228 42 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,8 CALL_ARG_VAL,3,0 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,8 WIDTH,8 SLICE,1 MITECONDNOINSTR,4 RET +bcid 229 43 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,8 CALL_ARG_VAL,3,0 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,0 WIDTH,8 SLICE,1 MITECONDNOINSTR,4 RET +bcid 230 44 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,8 CALL_ARG_VAL,3,0 WIDTH,16 CALL_ARG_VAL,4,0 WIDTH,32 OPT_CONST,8 WIDTH,8 SLICE,1 MITECONDNOINSTR,4 RET +bcid 231 45 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,8 CALL_ARG_VAL,3,0 WIDTH,16 CALL_ARG_VAL,4,0 WIDTH,32 OPT_CONST,0 WIDTH,8 SLICE,1 MITECONDNOINSTR,4 RET +sid ctrl_regfile +bcid 232 0 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,16 WIDTH,16 SLICE,1 WIDTH,1 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,5,0 OPT_CONST,16 WIDTH,16 SLICE,1 WIDTH,1 CALL_ARG_VAL,6,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,7,0 OPT_CONST,16 WIDTH,16 SLICE,1 WIDTH,1 CALL_ARG_VAL,8,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,9,0 OPT_CONST,16 WIDTH,16 SLICE,1 WIDTH,1 CALL_ARG_VAL,10,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,11,0 OPT_CONST,16 WIDTH,16 SLICE,1 WIDTH,1 CALL_ARG_VAL,12,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,13,0 OPT_CONST,16 WIDTH,16 SLICE,1 WIDTH,1 CALL_ARG_VAL,14,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,15,0 OPT_CONST,16 WIDTH,16 SLICE,1 WIDTH,1 CALL_ARG_VAL,16,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,17,0 OPT_CONST,16 WIDTH,16 SLICE,1 WIDTH,1 CALL_ARG_VAL,18,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,19,0 OPT_CONST,16 WIDTH,16 SLICE,1 WIDTH,1 CALL_ARG_VAL,20,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,21,0 OPT_CONST,16 WIDTH,16 SLICE,1 WIDTH,1 CALL_ARG_VAL,22,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,23,0 OPT_CONST,16 WIDTH,16 SLICE,1 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 233 1 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,3 WIDTH,13 SLICE,1 WIDTH,1 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,5,0 WIDTH,32 OPT_CONST,3 WIDTH,13 SLICE,1 WIDTH,1 CALL_ARG_VAL,6,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,7,0 OPT_CONST,3 WIDTH,13 SLICE,1 WIDTH,1 CALL_ARG_VAL,8,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,9,0 OPT_CONST,3 WIDTH,13 SLICE,1 WIDTH,1 CALL_ARG_VAL,10,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,11,0 OPT_CONST,3 WIDTH,13 SLICE,1 WIDTH,1 CALL_ARG_VAL,12,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,13,0 OPT_CONST,3 WIDTH,13 SLICE,1 WIDTH,1 CALL_ARG_VAL,14,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,15,0 OPT_CONST,3 WIDTH,13 SLICE,1 WIDTH,1 CALL_ARG_VAL,16,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,17,0 OPT_CONST,3 WIDTH,13 SLICE,1 WIDTH,1 CALL_ARG_VAL,18,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,19,0 OPT_CONST,3 WIDTH,13 SLICE,1 WIDTH,1 CALL_ARG_VAL,20,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,21,0 OPT_CONST,3 WIDTH,13 SLICE,1 WIDTH,1 CALL_ARG_VAL,22,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,23,0 OPT_CONST,3 WIDTH,13 SLICE,1 WIDTH,1 CALL_ARG_VAL,24,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,25,0 OPT_CONST,3 WIDTH,13 SLICE,1 WIDTH,1 CALL_ARG_VAL,26,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,27,0 OPT_CONST,3 WIDTH,13 SLICE,1 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 234 2 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 EQU CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,5,0 WIDTH,32 OPT_CONST,2 WIDTH,1 SLICE,1 CALL_ARG_VAL,6,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,7,0 WIDTH,32 OPT_CONST,2 WIDTH,1 SLICE,1 CALL_ARG_VAL,8,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,9,0 OPT_CONST,2 WIDTH,1 SLICE,1 CALL_ARG_VAL,10,0 OPT_CONST,1 EQU WIDTH,3 CALL_ARG_VAL,11,0 WIDTH,32 OPT_CONST,2 WIDTH,1 SLICE,1 CALL_ARG_VAL,12,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,13,0 OPT_CONST,2 WIDTH,1 SLICE,1 CALL_ARG_VAL,14,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,15,0 OPT_CONST,2 WIDTH,1 SLICE,1 CALL_ARG_VAL,16,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,17,0 OPT_CONST,2 WIDTH,1 SLICE,1 CALL_ARG_VAL,18,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,19,0 OPT_CONST,2 WIDTH,1 SLICE,1 CALL_ARG_VAL,20,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,21,0 OPT_CONST,2 WIDTH,1 SLICE,1 CALL_ARG_VAL,22,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,23,0 OPT_CONST,2 WIDTH,1 SLICE,1 CALL_ARG_VAL,24,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,25,0 OPT_CONST,2 WIDTH,1 SLICE,1 CALL_ARG_VAL,26,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,27,0 OPT_CONST,2 WIDTH,1 SLICE,1 CALL_ARG_VAL,28,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,29,0 OPT_CONST,2 WIDTH,1 SLICE,1 CALL_ARG_VAL,30,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,31,0 OPT_CONST,2 WIDTH,1 SLICE,1 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 235 3 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 EQU CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU WIDTH,2 CALL_ARG_VAL,5,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,6,0 OPT_CONST,1 EQU WIDTH,2 CALL_ARG_VAL,7,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,8,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,9,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,10,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,11,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,12,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,13,0 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,14,0 OPT_CONST,1 EQU WIDTH,2 CALL_ARG_VAL,15,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,16,0 OPT_CONST,1 EQU WIDTH,3 CALL_ARG_VAL,17,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,18,0 OPT_CONST,1 EQU WIDTH,2 CALL_ARG_VAL,19,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,20,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,21,0 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,22,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,23,0 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,24,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,25,0 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,26,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,27,0 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,28,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,29,0 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,30,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,31,0 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,32,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,33,0 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,34,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,35,0 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,36,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,37,0 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,38,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,39,0 OPT_CONST,1 WIDTH,1 SLICE,1 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 236 4 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 EQU CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU CALL_ARG_VAL,5,0 CALL_ARG_VAL,6,0 OPT_CONST,1 EQU CALL_ARG_VAL,7,0 CALL_ARG_VAL,8,0 OPT_CONST,1 EQU WIDTH,2 CALL_ARG_VAL,9,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,10,0 OPT_CONST,1 EQU WIDTH,2 CALL_ARG_VAL,11,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,12,0 OPT_CONST,1 EQU CALL_ARG_VAL,13,0 CALL_ARG_VAL,14,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,15,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,16,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,17,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,18,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,19,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,20,0 OPT_CONST,1 EQU CALL_ARG_VAL,21,0 CALL_ARG_VAL,22,0 OPT_CONST,1 EQU WIDTH,2 CALL_ARG_VAL,23,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,24,0 OPT_CONST,1 EQU WIDTH,3 CALL_ARG_VAL,25,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,26,0 OPT_CONST,1 EQU CALL_ARG_VAL,27,0 CALL_ARG_VAL,28,0 OPT_CONST,1 EQU WIDTH,2 CALL_ARG_VAL,29,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,30,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,31,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,32,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,33,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,34,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,35,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,36,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,37,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,38,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,39,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,40,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,41,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,42,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,43,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,44,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,45,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,46,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,47,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,48,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,49,0 OPT_CONST,0 WIDTH,1 SLICE,1 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 237 5 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,0 WIDTH,1 M_EQU RET +bcid 238 6 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,1 WIDTH,1 M_EQU RET +bcid 239 7 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,2 WIDTH,1 M_EQU RET +bcid 240 8 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,3 WIDTH,1 M_EQU RET +bcid 241 9 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,4 WIDTH,1 M_EQU RET +bcid 242 10 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,5 WIDTH,1 M_EQU RET +bcid 243 11 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,6 WIDTH,1 M_EQU RET +bcid 244 12 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,7 WIDTH,1 M_EQU RET +bcid 245 13 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,38 WIDTH,1 M_EQU RET +bcid 246 14 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,39 WIDTH,1 M_EQU RET +bcid 247 15 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,40 WIDTH,1 M_EQU RET +bcid 248 16 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,64 WIDTH,1 M_EQU RET +bcid 249 17 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,65 WIDTH,1 M_EQU RET +bcid 250 18 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,66 WIDTH,1 M_EQU RET +bcid 251 19 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,67 WIDTH,1 M_EQU RET +bcid 252 20 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,68 WIDTH,1 M_EQU RET +bcid 253 21 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,69 WIDTH,1 M_EQU RET +bcid 254 22 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,70 WIDTH,1 M_EQU RET +bcid 255 23 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,71 WIDTH,1 M_EQU RET +bcid 256 24 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,72 WIDTH,1 M_EQU RET +bcid 257 25 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,74 WIDTH,1 M_EQU RET +bcid 258 26 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,75 WIDTH,1 M_EQU RET +bcid 259 27 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,77 WIDTH,1 M_EQU RET +bcid 260 28 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,76 WIDTH,1 M_EQU RET +bcid 261 29 WIDTH,2 CALL_ARG_VAL,2,0 OPT_CONST,3 WIDTH,1 M_EQU RET +sid DUC_HB2 +bcid 262 0 WIDTH,33 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,15 WIDTH,18 SLICE,1 WIDTH,33 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,14 WIDTH,1 SLICE,1 WIDTH,18 PAD ADD RET +sid DUC_HB3 +bcid 263 0 WIDTH,33 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,15 WIDTH,18 SLICE,1 WIDTH,33 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,14 WIDTH,1 SLICE,1 WIDTH,18 PAD ADD RET +sid DUC_HB4 +bcid 264 0 WIDTH,33 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,15 WIDTH,18 SLICE,1 WIDTH,33 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,14 WIDTH,1 SLICE,1 WIDTH,18 PAD ADD RET +sid DUC4 +bcid 265 0 WIDTH,34 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,15 WIDTH,19 SLICE,1 WIDTH,20 PAD WIDTH,34 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,14 WIDTH,1 SLICE,1 WIDTH,20 PAD ADD RET +sid DW_mult_pipe_0000_0000 +bcid 266 0 WIDTH,11 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,10 WIDTH,1 SLICE,1 WIDTH,11 CALL_ARG_VAL,2,0 NOT OPT_CONST,1 ADD CALL_ARG_VAL,2,0 MITECONDNOINSTR,4 RET +bcid 267 1 WIDTH,12 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,11 WIDTH,1 SLICE,1 WIDTH,12 CALL_ARG_VAL,2,0 NOT OPT_CONST,1 ADD CALL_ARG_VAL,2,0 MITECONDNOINSTR,4 RET +bcid 268 2 WIDTH,11 CALL_ARG_VAL,2,0 WIDTH,22 PAD WIDTH,12 CALL_ARG_VAL,3,0 WIDTH,22 PAD MULTIPLY RET +bcid 269 3 WIDTH,22 CALL_ARG_VAL,2,0 OPT_CONST,1 SUBTRACT NOT RET +bcid 270 4 WIDTH,11 CALL_ARG_VAL,2,0 CALL_ARG_VAL,2,0 XOR WIDTH,1 XOR_REDUCE OPT_CONST,0 NEQU WIDTH,12 CALL_ARG_VAL,3,0 CALL_ARG_VAL,3,0 XOR WIDTH,1 XOR_REDUCE OPT_CONST,0 NEQU CALL_ARG_VAL,4,0 CALL_ARG_VAL,4,0 XOR XOR_REDUCE OPT_CONST,0 NEQU OR OR WIDTH,23 OPT_CONST_4ST,8388607,8388607 WIDTH,1 CALL_ARG_VAL,4,0 WIDTH,11 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,10 WIDTH,1 SLICE,1 WIDTH,12 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,11 WIDTH,1 SLICE,1 XOR WIDTH,22 CALL_ARG_VAL,5,0 OPT_CONST,0 WIDTH,1 M_NEQU AND OPT_CONST,1 WIDTH,22 CALL_ARG_VAL,6,0 WIDTH,23 CONCATENATE,2 WIDTH,1 OPT_CONST,0 WIDTH,22 CALL_ARG_VAL,5,0 WIDTH,23 CONCATENATE,2 MITECONDNOINSTR,4 WIDTH,11 CALL_ARG_VAL,2,0 WIDTH,23 PAD WIDTH,12 CALL_ARG_VAL,3,0 WIDTH,23 PAD MULTIPLY MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +sid PH2AMP +bcid 271 0 WIDTH,16 CALL_ARG_VAL,2,0 OPT_CONST,0 WIDTH,1 M_NEQU WIDTH,16 MULTI_CONCATENATE,1,16 CALL_ARG_VAL,2,0 NOT OPT_CONST,1 ADD AND RET +bcid 272 1 WIDTH,19 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,16 WIDTH,1 SLICE,1 WIDTH,19 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,0 WIDTH,16 SLICE,1 NOT WIDTH,19 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,0 WIDTH,16 SLICE,1 MITECONDNOINSTR,4 RET +bcid 273 2 WIDTH,16 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,10 WIDTH,1 SLICE,1 WIDTH,16 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,11 WIDTH,5 SLICE,1 OPT_CONST,1 ADD WIDTH,16 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,11 WIDTH,5 SLICE,1 MITECONDNOINSTR,4 RET +bcid 274 3 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,13 CALL_ARG_VAL,3,0 OPT_CONST,1 ADD CALL_ARG_VAL,3,0 MITECONDNOINSTR,4 RET +bcid 275 4 WIDTH,18 CALL_ARG_VAL,2,0 WIDTH,13 CALL_ARG_VAL,3,0 WIDTH,18 PAD ADD RET +bcid 276 5 WIDTH,18 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,2 WIDTH,1 SLICE,1 WIDTH,18 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,3 WIDTH,15 SLICE,1 OPT_CONST,1 ADD WIDTH,18 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,3 WIDTH,15 SLICE,1 MITECONDNOINSTR,4 RET +bcid 277 6 WIDTH,11 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,10 WIDTH,1 SLICE,1 WIDTH,11 CALL_ARG_VAL,2,0 NOT OPT_CONST,1 ADD CALL_ARG_VAL,2,0 MITECONDNOINSTR,4 RET +bcid 278 7 WIDTH,5 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,4 WIDTH,1 SLICE,1 WIDTH,5 CALL_ARG_VAL,2,0 NOT OPT_CONST,1 ADD CALL_ARG_VAL,2,0 MITECONDNOINSTR,4 RET +bcid 279 8 WIDTH,11 CALL_ARG_VAL,2,0 WIDTH,15 PAD WIDTH,5 CALL_ARG_VAL,3,0 WIDTH,15 PAD MULTIPLY RET +bcid 280 9 WIDTH,15 CALL_ARG_VAL,2,0 OPT_CONST,1 SUBTRACT NOT RET +bcid 281 10 WIDTH,11 CALL_ARG_VAL,2,0 CALL_ARG_VAL,2,0 XOR WIDTH,1 XOR_REDUCE OPT_CONST,0 NEQU WIDTH,5 CALL_ARG_VAL,3,0 CALL_ARG_VAL,3,0 XOR WIDTH,1 XOR_REDUCE OPT_CONST,0 NEQU CALL_ARG_VAL,4,0 CALL_ARG_VAL,4,0 XOR XOR_REDUCE OPT_CONST,0 NEQU OR OR WIDTH,16 OPT_CONST_4ST,65535,65535 WIDTH,1 CALL_ARG_VAL,4,0 WIDTH,11 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,10 WIDTH,1 SLICE,1 WIDTH,5 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,4 WIDTH,1 SLICE,1 XOR WIDTH,15 CALL_ARG_VAL,5,0 OPT_CONST,0 WIDTH,1 M_NEQU AND OPT_CONST,1 WIDTH,15 CALL_ARG_VAL,6,0 WIDTH,16 CONCATENATE,2 WIDTH,1 OPT_CONST,0 WIDTH,15 CALL_ARG_VAL,5,0 WIDTH,16 CONCATENATE,2 MITECONDNOINSTR,4 WIDTH,11 CALL_ARG_VAL,2,0 WIDTH,16 PAD WIDTH,5 CALL_ARG_VAL,3,0 WIDTH,16 PAD MULTIPLY MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 282 11 WIDTH,17 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,10 WIDTH,1 SLICE,1 WIDTH,17 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,11 WIDTH,6 SLICE,1 OPT_CONST,1 ADD WIDTH,17 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,11 WIDTH,6 SLICE,1 MITECONDNOINSTR,4 RET +bcid 283 12 WIDTH,18 CALL_ARG_VAL,2,0 WIDTH,13 CALL_ARG_VAL,3,0 WIDTH,18 PAD SUBTRACT RET +bcid 284 13 WIDTH,18 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,2 WIDTH,1 SLICE,1 OPT_CONST,0 WIDTH,18 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,3 WIDTH,15 SLICE,1 WIDTH,16 CONCATENATE,2 OPT_CONST,1 ADD WIDTH,1 OPT_CONST,0 WIDTH,18 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,3 WIDTH,15 SLICE,1 WIDTH,16 CONCATENATE,2 MITECONDNOINSTR,4 RET +bcid 285 14 WIDTH,16 CALL_ARG_VAL,2,0 OPT_CONST,32766 WIDTH,1 M_GT WIDTH,15 OPT_CONST,32767 WIDTH,16 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,0 WIDTH,15 SLICE,1 MITECONDNOINSTR,4 RET +bcid 286 15 WIDTH,6 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,5 WIDTH,1 SLICE,1 WIDTH,6 CALL_ARG_VAL,2,0 NOT OPT_CONST,1 ADD CALL_ARG_VAL,2,0 MITECONDNOINSTR,4 RET +bcid 287 16 WIDTH,11 CALL_ARG_VAL,2,0 WIDTH,16 PAD WIDTH,6 CALL_ARG_VAL,3,0 WIDTH,16 PAD MULTIPLY RET +bcid 288 17 WIDTH,16 CALL_ARG_VAL,2,0 OPT_CONST,1 SUBTRACT NOT RET +bcid 289 18 WIDTH,11 CALL_ARG_VAL,2,0 CALL_ARG_VAL,2,0 XOR WIDTH,1 XOR_REDUCE OPT_CONST,0 NEQU WIDTH,6 CALL_ARG_VAL,3,0 CALL_ARG_VAL,3,0 XOR WIDTH,1 XOR_REDUCE OPT_CONST,0 NEQU CALL_ARG_VAL,4,0 CALL_ARG_VAL,4,0 XOR XOR_REDUCE OPT_CONST,0 NEQU OR OR WIDTH,17 OPT_CONST_4ST,131071,131071 WIDTH,1 CALL_ARG_VAL,4,0 WIDTH,11 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,10 WIDTH,1 SLICE,1 WIDTH,6 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,5 WIDTH,1 SLICE,1 XOR WIDTH,16 CALL_ARG_VAL,5,0 OPT_CONST,0 WIDTH,1 M_NEQU AND OPT_CONST,1 WIDTH,16 CALL_ARG_VAL,6,0 WIDTH,17 CONCATENATE,2 WIDTH,1 OPT_CONST,0 WIDTH,16 CALL_ARG_VAL,5,0 WIDTH,17 CONCATENATE,2 MITECONDNOINSTR,4 WIDTH,11 CALL_ARG_VAL,2,0 WIDTH,17 PAD WIDTH,6 CALL_ARG_VAL,3,0 WIDTH,17 PAD MULTIPLY MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +sid DW_mult_pipe_0000_0002 +bcid 290 0 WIDTH,16 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,15 WIDTH,1 SLICE,1 WIDTH,16 CALL_ARG_VAL,2,0 NOT OPT_CONST,1 ADD CALL_ARG_VAL,2,0 MITECONDNOINSTR,4 RET +bcid 291 1 WIDTH,16 CALL_ARG_VAL,2,0 WIDTH,31 PAD WIDTH,16 CALL_ARG_VAL,3,0 WIDTH,31 PAD MULTIPLY RET +bcid 292 2 WIDTH,31 CALL_ARG_VAL,2,0 OPT_CONST,1 SUBTRACT NOT RET +bcid 293 3 WIDTH,16 CALL_ARG_VAL,2,0 CALL_ARG_VAL,2,0 XOR WIDTH,1 XOR_REDUCE OPT_CONST,0 NEQU WIDTH,16 CALL_ARG_VAL,3,0 CALL_ARG_VAL,3,0 XOR WIDTH,1 XOR_REDUCE OPT_CONST,0 NEQU CALL_ARG_VAL,4,0 CALL_ARG_VAL,4,0 XOR XOR_REDUCE OPT_CONST,0 NEQU OR OR WIDTH,32 OPT_CONST_4ST,-1,-1 WIDTH,1 CALL_ARG_VAL,4,0 WIDTH,16 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,15 WIDTH,1 SLICE,1 WIDTH,16 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,15 WIDTH,1 SLICE,1 XOR WIDTH,31 CALL_ARG_VAL,5,0 OPT_CONST,0 WIDTH,1 M_NEQU AND OPT_CONST,1 WIDTH,31 CALL_ARG_VAL,6,0 WIDTH,32 CONCATENATE,2 WIDTH,1 OPT_CONST,0 WIDTH,31 CALL_ARG_VAL,5,0 WIDTH,32 CONCATENATE,2 MITECONDNOINSTR,4 WIDTH,16 CALL_ARG_VAL,2,0 WIDTH,32 PAD WIDTH,16 CALL_ARG_VAL,3,0 WIDTH,32 PAD MULTIPLY MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +sid xy_dsp +bcid 294 0 WIDTH,48 CALL_ARG_VAL,2,0 WIDTH,3 OPT_CONST,1 WIDTH,48 SHIFT_L RET +bcid 295 1 WIDTH,48 CALL_ARG_VAL,2,0 WIDTH,3 OPT_CONST,2 WIDTH,48 SHIFT_L RET +bcid 296 2 WIDTH,48 CALL_ARG_VAL,2,0 WIDTH,3 OPT_CONST,3 WIDTH,48 SHIFT_L RET +bcid 297 3 WIDTH,48 CALL_ARG_VAL,2,0 WIDTH,3 OPT_CONST,4 WIDTH,48 SHIFT_L RET +bcid 298 4 WIDTH,1 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 WIDTH,15 CALL_ARG_VAL,4,0 WIDTH,16 CONCATENATE,2 OPT_CONST,1 ADD WIDTH,1 CALL_ARG_VAL,3,0 WIDTH,15 CALL_ARG_VAL,4,0 WIDTH,16 CONCATENATE,2 MITECONDNOINSTR,4 RET +bcid 299 5 WIDTH,17 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,15 WIDTH,2 SLICE,1 OPT_CONST,1 WIDTH,1 M_EQU WIDTH,16 OPT_CONST,32767 WIDTH,17 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,15 WIDTH,2 SLICE,1 OPT_CONST,2 WIDTH,1 M_EQU WIDTH,16 OPT_CONST,32768 WIDTH,17 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,16 WIDTH,1 SLICE,1 WIDTH,17 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,0 WIDTH,15 SLICE,1 WIDTH,16 CONCATENATE,2 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +sid dac_regfile +bcid 300 0 WIDTH,15 OPT_CONST,0 RET +bcid 301 1 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 EQU WIDTH,17 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,15 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU WIDTH,17 CALL_ARG_VAL,5,0 WIDTH,32 OPT_CONST,15 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,6,0 OPT_CONST,1 EQU WIDTH,17 CALL_ARG_VAL,7,0 WIDTH,32 OPT_CONST,15 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,8,0 OPT_CONST,1 EQU WIDTH,17 CALL_ARG_VAL,9,0 WIDTH,32 OPT_CONST,15 WIDTH,2 SLICE,1 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 302 2 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 EQU WIDTH,17 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,9 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU WIDTH,17 CALL_ARG_VAL,5,0 WIDTH,32 OPT_CONST,9 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,6,0 OPT_CONST,1 EQU WIDTH,17 CALL_ARG_VAL,7,0 WIDTH,32 OPT_CONST,9 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,8,0 OPT_CONST,1 EQU WIDTH,17 CALL_ARG_VAL,9,0 WIDTH,32 OPT_CONST,9 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,10,0 OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,11,0 WIDTH,32 OPT_CONST,9 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,12,0 OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,13,0 WIDTH,32 OPT_CONST,9 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,14,0 OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,15,0 WIDTH,32 OPT_CONST,9 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,16,0 OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,17,0 WIDTH,32 OPT_CONST,9 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,18,0 OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,19,0 WIDTH,32 OPT_CONST,9 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,20,0 OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,21,0 WIDTH,32 OPT_CONST,9 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,22,0 OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,23,0 WIDTH,32 OPT_CONST,9 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,24,0 OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,25,0 WIDTH,32 OPT_CONST,9 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,26,0 OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,27,0 WIDTH,32 OPT_CONST,9 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,28,0 OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,29,0 WIDTH,32 OPT_CONST,9 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,30,0 OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,31,0 WIDTH,32 OPT_CONST,9 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,32,0 OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,33,0 WIDTH,32 OPT_CONST,9 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,34,0 OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,35,0 WIDTH,32 OPT_CONST,9 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,36,0 OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,37,0 WIDTH,32 OPT_CONST,9 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,38,0 OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,39,0 WIDTH,32 OPT_CONST,9 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,40,0 OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,41,0 WIDTH,32 OPT_CONST,9 WIDTH,6 SLICE,1 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 303 3 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 EQU WIDTH,17 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,3 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU WIDTH,17 CALL_ARG_VAL,5,0 WIDTH,32 OPT_CONST,3 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,6,0 OPT_CONST,1 EQU WIDTH,17 CALL_ARG_VAL,7,0 WIDTH,32 OPT_CONST,3 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,8,0 OPT_CONST,1 EQU WIDTH,17 CALL_ARG_VAL,9,0 WIDTH,32 OPT_CONST,3 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,10,0 OPT_CONST,1 EQU WIDTH,9 CALL_ARG_VAL,11,0 WIDTH,32 OPT_CONST,3 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,12,0 OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,13,0 WIDTH,32 OPT_CONST,3 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,14,0 OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,15,0 WIDTH,32 OPT_CONST,3 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,16,0 OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,17,0 WIDTH,32 OPT_CONST,3 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,18,0 OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,19,0 WIDTH,32 OPT_CONST,3 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,20,0 OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,21,0 WIDTH,32 OPT_CONST,3 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,22,0 OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,23,0 WIDTH,32 OPT_CONST,3 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,24,0 OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,25,0 WIDTH,32 OPT_CONST,3 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,26,0 OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,27,0 WIDTH,32 OPT_CONST,3 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,28,0 OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,29,0 WIDTH,32 OPT_CONST,3 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,30,0 OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,31,0 WIDTH,32 OPT_CONST,3 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,32,0 OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,33,0 WIDTH,32 OPT_CONST,3 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,34,0 OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,35,0 WIDTH,32 OPT_CONST,3 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,36,0 OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,37,0 WIDTH,32 OPT_CONST,3 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,38,0 OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,39,0 WIDTH,32 OPT_CONST,3 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,40,0 OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,41,0 WIDTH,32 OPT_CONST,3 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,42,0 OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,43,0 WIDTH,32 OPT_CONST,3 WIDTH,6 SLICE,1 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 304 4 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 EQU WIDTH,17 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU WIDTH,17 CALL_ARG_VAL,5,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,6,0 OPT_CONST,1 EQU WIDTH,17 CALL_ARG_VAL,7,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,8,0 OPT_CONST,1 EQU WIDTH,17 CALL_ARG_VAL,9,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,10,0 OPT_CONST,1 EQU WIDTH,9 CALL_ARG_VAL,11,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,12,0 OPT_CONST,1 EQU WIDTH,3 CALL_ARG_VAL,13,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,14,0 OPT_CONST,1 EQU WIDTH,3 CALL_ARG_VAL,15,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,16,0 OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,17,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,18,0 OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,19,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,20,0 OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,21,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,22,0 OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,23,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,24,0 OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,25,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,26,0 OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,27,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,28,0 OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,29,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,30,0 OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,31,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,32,0 OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,33,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,34,0 OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,35,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,36,0 OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,37,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,38,0 OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,39,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,40,0 OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,41,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,42,0 OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,43,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,44,0 OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,45,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,46,0 OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,47,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 305 5 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 EQU CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU WIDTH,17 CALL_ARG_VAL,5,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,6,0 OPT_CONST,1 EQU WIDTH,17 CALL_ARG_VAL,7,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,8,0 OPT_CONST,1 EQU WIDTH,17 CALL_ARG_VAL,9,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,10,0 OPT_CONST,1 EQU WIDTH,17 CALL_ARG_VAL,11,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,12,0 OPT_CONST,1 EQU WIDTH,9 CALL_ARG_VAL,13,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,14,0 OPT_CONST,1 EQU WIDTH,3 CALL_ARG_VAL,15,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,16,0 OPT_CONST,1 EQU WIDTH,3 CALL_ARG_VAL,17,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,18,0 OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,19,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,20,0 OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,21,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,22,0 OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,23,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,24,0 OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,25,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,26,0 OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,27,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,28,0 OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,29,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,30,0 OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,31,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,32,0 OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,33,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,34,0 OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,35,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,36,0 OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,37,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,38,0 OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,39,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,40,0 OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,41,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,42,0 OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,43,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,44,0 OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,45,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,46,0 OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,47,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,48,0 OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,49,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,50,0 OPT_CONST,1 EQU CALL_ARG_VAL,51,0 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 306 6 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 EQU CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU CALL_ARG_VAL,5,0 CALL_ARG_VAL,6,0 OPT_CONST,1 EQU CALL_ARG_VAL,7,0 CALL_ARG_VAL,8,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 307 7 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,0 WIDTH,1 M_EQU RET +bcid 308 8 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,1 WIDTH,1 M_EQU RET +bcid 309 9 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,2 WIDTH,1 M_EQU RET +bcid 310 10 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,3 WIDTH,1 M_EQU RET +bcid 311 11 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,4 WIDTH,1 M_EQU RET +bcid 312 12 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,5 WIDTH,1 M_EQU RET +bcid 313 13 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,6 WIDTH,1 M_EQU RET +bcid 314 14 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,7 WIDTH,1 M_EQU RET +bcid 315 15 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,8 WIDTH,1 M_EQU RET +bcid 316 16 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,9 WIDTH,1 M_EQU RET +bcid 317 17 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,10 WIDTH,1 M_EQU RET +bcid 318 18 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,11 WIDTH,1 M_EQU RET +bcid 319 19 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,12 WIDTH,1 M_EQU RET +bcid 320 20 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,13 WIDTH,1 M_EQU RET +bcid 321 21 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,14 WIDTH,1 M_EQU RET +bcid 322 22 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,15 WIDTH,1 M_EQU RET +bcid 323 23 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,16 WIDTH,1 M_EQU RET +bcid 324 24 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,17 WIDTH,1 M_EQU RET +bcid 325 25 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,18 WIDTH,1 M_EQU RET +bcid 326 26 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,19 WIDTH,1 M_EQU RET +bcid 327 27 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,20 WIDTH,1 M_EQU RET +bcid 328 28 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,21 WIDTH,1 M_EQU RET +bcid 329 29 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,22 WIDTH,1 M_EQU RET +bcid 330 30 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,23 WIDTH,1 M_EQU RET +bcid 331 31 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,24 WIDTH,1 M_EQU RET +bcid 332 32 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,25 WIDTH,1 M_EQU RET +bcid 333 33 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,26 WIDTH,1 M_EQU RET +bcid 334 34 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,27 WIDTH,1 M_EQU RET +bcid 335 35 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,28 WIDTH,1 M_EQU RET +sid param_lut_0002 +bcid 336 0 WIDTH,4 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 WIDTH,16 CALL_ARG_VAL,3,0 OPT_CONST,0 MITECONDNOINSTR,4 RET +bcid 337 1 WIDTH,4 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 WIDTH,16 CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 RET +bcid 338 2 WIDTH,4 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,2 WIDTH,1 SLICE,1 WIDTH,16 CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 RET +bcid 339 3 WIDTH,4 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,3 WIDTH,1 SLICE,1 WIDTH,16 CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 RET +sid tsdn28hpcpuhdb4096x32m4mw_170a +bcid 340 0 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 341 1 WIDTH,1 OPT_CONST,0 RET +bcid 342 2 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 343 3 WIDTH,1 OPT_CONST,0 RET +bcid 344 4 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 345 5 WIDTH,1 OPT_CONST,0 RET +bcid 346 6 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 347 7 WIDTH,1 OPT_CONST,0 RET +bcid 348 8 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 349 9 WIDTH,1 OPT_CONST,0 RET +bcid 350 10 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 351 11 WIDTH,1 OPT_CONST,0 RET +bcid 352 12 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 353 13 WIDTH,1 OPT_CONST,0 RET +bcid 354 14 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 355 15 WIDTH,1 OPT_CONST,0 RET +bcid 356 16 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 357 17 WIDTH,1 OPT_CONST,0 RET +bcid 358 18 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 359 19 WIDTH,1 OPT_CONST,0 RET +bcid 360 20 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 361 21 WIDTH,1 OPT_CONST,0 RET +bcid 362 22 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 363 23 WIDTH,1 OPT_CONST,0 RET +bcid 364 24 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 365 25 WIDTH,1 OPT_CONST,0 RET +bcid 366 26 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 367 27 WIDTH,1 OPT_CONST,0 RET +bcid 368 28 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 369 29 WIDTH,1 OPT_CONST,0 RET +bcid 370 30 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 371 31 WIDTH,1 OPT_CONST,0 RET +bcid 372 32 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 373 33 WIDTH,1 OPT_CONST,0 RET +bcid 374 34 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 375 35 WIDTH,1 OPT_CONST,0 RET +bcid 376 36 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 377 37 WIDTH,1 OPT_CONST,0 RET +bcid 378 38 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 379 39 WIDTH,1 OPT_CONST,0 RET +bcid 380 40 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 381 41 WIDTH,1 OPT_CONST,0 RET +bcid 382 42 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 383 43 WIDTH,1 OPT_CONST,0 RET +bcid 384 44 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 385 45 WIDTH,1 OPT_CONST,0 RET +bcid 386 46 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 387 47 WIDTH,1 OPT_CONST,0 RET +bcid 388 48 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 389 49 WIDTH,1 OPT_CONST,0 RET +bcid 390 50 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 391 51 WIDTH,1 OPT_CONST,0 RET +bcid 392 52 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 393 53 WIDTH,1 OPT_CONST,0 RET +bcid 394 54 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 395 55 WIDTH,1 OPT_CONST,0 RET +bcid 396 56 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 397 57 WIDTH,1 OPT_CONST,0 RET +bcid 398 58 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 399 59 WIDTH,1 OPT_CONST,0 RET +bcid 400 60 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 401 61 WIDTH,1 OPT_CONST,0 RET +bcid 402 62 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 403 63 WIDTH,1 OPT_CONST,0 RET +sid modout_mux +bcid 404 0 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,16 CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 RET +bcid 405 1 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 CALL_ARG_VAL,3,0 MITECONDNOINSTR,4 RET +sid channel_top +bcid 406 0 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 407 1 WIDTH,1 OPT_CONST,0 RET +bcid 408 2 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 409 3 WIDTH,1 OPT_CONST,0 RET +bcid 410 4 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 411 5 WIDTH,1 OPT_CONST,0 RET +bcid 412 6 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 413 7 WIDTH,1 OPT_CONST,0 RET +bcid 414 8 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 415 9 WIDTH,1 OPT_CONST,0 RET +bcid 416 10 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 417 11 WIDTH,1 OPT_CONST,0 RET +bcid 418 12 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 419 13 WIDTH,1 OPT_CONST,0 RET +bcid 420 14 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 421 15 WIDTH,1 OPT_CONST,0 RET +bcid 422 16 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 423 17 WIDTH,1 OPT_CONST,0 RET +bcid 424 18 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 425 19 WIDTH,1 OPT_CONST,0 RET +bcid 426 20 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 427 21 WIDTH,1 OPT_CONST,0 RET +bcid 428 22 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 429 23 WIDTH,1 OPT_CONST,0 RET +bcid 430 24 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 431 25 WIDTH,1 OPT_CONST,0 RET +bcid 432 26 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 433 27 WIDTH,1 OPT_CONST,0 RET +bcid 434 28 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 435 29 WIDTH,1 OPT_CONST,0 RET +bcid 436 30 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 437 31 WIDTH,1 OPT_CONST,0 RET +bcid 438 32 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 439 33 WIDTH,1 OPT_CONST,0 RET +bcid 440 34 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 441 35 WIDTH,1 OPT_CONST,0 RET +bcid 442 36 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 443 37 WIDTH,1 OPT_CONST,0 RET +bcid 444 38 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 445 39 WIDTH,1 OPT_CONST,0 RET +bcid 446 40 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 447 41 WIDTH,1 OPT_CONST,0 RET +bcid 448 42 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 449 43 WIDTH,1 OPT_CONST,0 RET +bcid 450 44 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 451 45 WIDTH,1 OPT_CONST,0 RET +bcid 452 46 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 453 47 WIDTH,1 OPT_CONST,0 RET +bcid 454 48 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 455 49 WIDTH,1 OPT_CONST,0 RET +bcid 456 50 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 457 51 WIDTH,1 OPT_CONST,0 RET +bcid 458 52 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 459 53 WIDTH,1 OPT_CONST,0 RET +bcid 460 54 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 461 55 WIDTH,1 OPT_CONST,0 RET +bcid 462 56 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 463 57 WIDTH,1 OPT_CONST,0 RET +bcid 464 58 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 465 59 WIDTH,1 OPT_CONST,0 RET +bcid 466 60 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 467 61 WIDTH,1 OPT_CONST,0 RET +bcid 468 62 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 469 63 WIDTH,1 OPT_CONST,0 RET +bcid 470 64 WIDTH,8 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,2 WIDTH,8 SHIFT_L RET +bcid 471 65 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,16 MULTI_CONCATENATE,1,16 CALL_ARG_VAL,3,0 AND RET +bcid 472 66 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,16 CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 RET +bcid 473 67 WIDTH,1 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 RET +bcid 474 68 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,8 CALL_ARG_VAL,3,0 WIDTH,2 CALL_ARG_VAL,4,0 WIDTH,8 PAD ADD CALL_ARG_VAL,3,0 MITECONDNOINSTR,4 RET +bcid 475 69 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,16 CALL_ARG_VAL,3,0 WIDTH,32 PAD WIDTH,16 CALL_ARG_VAL,4,0 WIDTH,32 PAD OPT_CONST,1 SUBTRACT WIDTH,1 M_EQU AND RET +bcid 476 70 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,16 OPT_CONST,0 WIDTH,1 CALL_ARG_VAL,3,0 WIDTH,16 CALL_ARG_VAL,4,0 OPT_CONST,1 ADD CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 477 71 WIDTH,1 CALL_ARG_VAL,2,0 NOT CALL_ARG_VAL,3,0 AND OPT_CONST,1 CALL_ARG_VAL,2,0 CALL_ARG_VAL,4,0 AND OPT_CONST,0 CALL_ARG_VAL,2,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 478 72 WIDTH,16 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,2 WIDTH,16 SHIFT_L ADD RET +bcid 479 73 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,32 CALL_ARG_VAL,3,0 WIDTH,1 CALL_ARG_VAL,4,0 WIDTH,32 CALL_ARG_VAL,5,0 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 480 74 WIDTH,16 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 ADD RET +bcid 481 75 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,16 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,15 WIDTH,1 SLICE,1 WIDTH,2 MULTI_CONCATENATE,1,2 WIDTH,16 CALL_ARG_VAL,3,0 WIDTH,18 CONCATENATE,2 WIDTH,16 CALL_ARG_VAL,4,0 WIDTH,32 OPT_CONST,15 WIDTH,1 SLICE,1 WIDTH,2 MULTI_CONCATENATE,1,2 WIDTH,16 CALL_ARG_VAL,4,0 WIDTH,18 CONCATENATE,2 ADD WIDTH,16 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,15 WIDTH,1 SLICE,1 WIDTH,2 MULTI_CONCATENATE,1,2 WIDTH,16 CALL_ARG_VAL,3,0 WIDTH,18 CONCATENATE,2 MITECONDNOINSTR,4 RET +bcid 482 76 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,15 CALL_ARG_VAL,3,0 WIDTH,16 CONCATENATE,2 WIDTH,1 CALL_ARG_VAL,4,0 WIDTH,16 PAD ADD RET +bcid 483 77 WIDTH,4 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,0 MITECONDNOINSTR,4 RET +bcid 484 78 WIDTH,4 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 RET +bcid 485 79 WIDTH,4 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,2 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 RET +bcid 486 80 WIDTH,4 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,3 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 RET +bcid 487 81 WIDTH,8 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 WIDTH,16 CALL_ARG_VAL,3,0 OPT_CONST,0 MITECONDNOINSTR,4 RET +bcid 488 82 WIDTH,8 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 WIDTH,16 CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 RET +bcid 489 83 WIDTH,8 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,2 WIDTH,1 SLICE,1 WIDTH,16 CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 RET +bcid 490 84 WIDTH,8 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,3 WIDTH,1 SLICE,1 WIDTH,16 CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 RET +bcid 491 85 WIDTH,8 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,4 WIDTH,1 SLICE,1 WIDTH,16 CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 RET +bcid 492 86 WIDTH,8 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,5 WIDTH,1 SLICE,1 WIDTH,16 CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 RET +bcid 493 87 WIDTH,8 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,6 WIDTH,1 SLICE,1 WIDTH,16 CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 RET +bcid 494 88 WIDTH,8 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,7 WIDTH,1 SLICE,1 WIDTH,16 CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 RET +bcid 495 89 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,16 CALL_ARG_VAL,3,0 OPT_CONST,0 MITECONDNOINSTR,4 RET +bcid 496 90 WIDTH,4 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,3 WIDTH,1 SLICE,1 WIDTH,8 MULTI_CONCATENATE,1,8 WIDTH,4 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,2 WIDTH,1 SLICE,1 WIDTH,8 MULTI_CONCATENATE,1,8 WIDTH,4 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 WIDTH,8 MULTI_CONCATENATE,1,8 WIDTH,4 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 WIDTH,8 MULTI_CONCATENATE,1,8 WIDTH,32 CONCATENATE,4 RET +bcid 497 91 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,32 MULTI_CONCATENATE,1,32 NOT CALL_ARG_VAL,3,0 AND WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,32 MULTI_CONCATENATE,1,32 CALL_ARG_VAL,4,0 AND OR RET +bcid 498 92 WIDTH,1 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 WIDTH,32 CALL_ARG_VAL,5,0 OPT_CONST,-1 SUBTRACT CALL_ARG_VAL,5,0 OPT_CONST,-1 ADD MITECONDNOINSTR,4 CALL_ARG_VAL,5,0 MITECONDNOINSTR,4 CALL_ARG_VAL,6,0 NOT NOT MITECONDNOINSTR,4 RET +bcid 499 93 WIDTH,32 CALL_ARG_VAL,2,0 WIDTH,1 CALL_ARG_VAL,3,0 WIDTH,32 MULTI_CONCATENATE,1,32 WIDTH,1 M_EQU RET +bcid 500 94 WIDTH,3 CALL_ARG_VAL,2,0 OPT_CONST,0 WIDTH,1 M_NEQU RET +bcid 501 95 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,8 MULTI_CONCATENATE,1,8 WIDTH,1 CALL_ARG_VAL,3,0 WIDTH,8 MULTI_CONCATENATE,1,8 WIDTH,1 CALL_ARG_VAL,4,0 WIDTH,8 MULTI_CONCATENATE,1,8 WIDTH,1 CALL_ARG_VAL,5,0 WIDTH,8 MULTI_CONCATENATE,1,8 WIDTH,32 CONCATENATE,4 RET +sid tsdn28hpcpuhdb128x128m4mw_170a +bcid 502 0 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 503 1 WIDTH,1 OPT_CONST,0 RET +bcid 504 2 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 505 3 WIDTH,1 OPT_CONST,0 RET +bcid 506 4 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 507 5 WIDTH,1 OPT_CONST,0 RET +bcid 508 6 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 509 7 WIDTH,1 OPT_CONST,0 RET +bcid 510 8 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 511 9 WIDTH,1 OPT_CONST,0 RET +bcid 512 10 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 513 11 WIDTH,1 OPT_CONST,0 RET +bcid 514 12 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 515 13 WIDTH,1 OPT_CONST,0 RET +bcid 516 14 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 517 15 WIDTH,1 OPT_CONST,0 RET +bcid 518 16 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 519 17 WIDTH,1 OPT_CONST,0 RET +bcid 520 18 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 521 19 WIDTH,1 OPT_CONST,0 RET +bcid 522 20 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 523 21 WIDTH,1 OPT_CONST,0 RET +bcid 524 22 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 525 23 WIDTH,1 OPT_CONST,0 RET +bcid 526 24 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 527 25 WIDTH,1 OPT_CONST,0 RET +bcid 528 26 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 529 27 WIDTH,1 OPT_CONST,0 RET +bcid 530 28 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 531 29 WIDTH,1 OPT_CONST,0 RET +bcid 532 30 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 533 31 WIDTH,1 OPT_CONST,0 RET +bcid 534 32 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 535 33 WIDTH,1 OPT_CONST,0 RET +bcid 536 34 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 537 35 WIDTH,1 OPT_CONST,0 RET +bcid 538 36 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 539 37 WIDTH,1 OPT_CONST,0 RET +bcid 540 38 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 541 39 WIDTH,1 OPT_CONST,0 RET +bcid 542 40 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 543 41 WIDTH,1 OPT_CONST,0 RET +bcid 544 42 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 545 43 WIDTH,1 OPT_CONST,0 RET +bcid 546 44 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 547 45 WIDTH,1 OPT_CONST,0 RET +bcid 548 46 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 549 47 WIDTH,1 OPT_CONST,0 RET +bcid 550 48 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 551 49 WIDTH,1 OPT_CONST,0 RET +bcid 552 50 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 553 51 WIDTH,1 OPT_CONST,0 RET +bcid 554 52 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 555 53 WIDTH,1 OPT_CONST,0 RET +bcid 556 54 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 557 55 WIDTH,1 OPT_CONST,0 RET +bcid 558 56 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 559 57 WIDTH,1 OPT_CONST,0 RET +bcid 560 58 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 561 59 WIDTH,1 OPT_CONST,0 RET +bcid 562 60 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 563 61 WIDTH,1 OPT_CONST,0 RET +bcid 564 62 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 565 63 WIDTH,1 OPT_CONST,0 RET +bcid 566 64 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 567 65 WIDTH,1 OPT_CONST,0 RET +bcid 568 66 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 569 67 WIDTH,1 OPT_CONST,0 RET +bcid 570 68 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 571 69 WIDTH,1 OPT_CONST,0 RET +bcid 572 70 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 573 71 WIDTH,1 OPT_CONST,0 RET +bcid 574 72 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 575 73 WIDTH,1 OPT_CONST,0 RET +bcid 576 74 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 577 75 WIDTH,1 OPT_CONST,0 RET +bcid 578 76 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 579 77 WIDTH,1 OPT_CONST,0 RET +bcid 580 78 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 581 79 WIDTH,1 OPT_CONST,0 RET +bcid 582 80 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 583 81 WIDTH,1 OPT_CONST,0 RET +bcid 584 82 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 585 83 WIDTH,1 OPT_CONST,0 RET +bcid 586 84 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 587 85 WIDTH,1 OPT_CONST,0 RET +bcid 588 86 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 589 87 WIDTH,1 OPT_CONST,0 RET +bcid 590 88 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 591 89 WIDTH,1 OPT_CONST,0 RET +bcid 592 90 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 593 91 WIDTH,1 OPT_CONST,0 RET +bcid 594 92 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 595 93 WIDTH,1 OPT_CONST,0 RET +bcid 596 94 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 597 95 WIDTH,1 OPT_CONST,0 RET +bcid 598 96 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 599 97 WIDTH,1 OPT_CONST,0 RET +bcid 600 98 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 601 99 WIDTH,1 OPT_CONST,0 RET +bcid 602 100 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 603 101 WIDTH,1 OPT_CONST,0 RET +bcid 604 102 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 605 103 WIDTH,1 OPT_CONST,0 RET +bcid 606 104 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 607 105 WIDTH,1 OPT_CONST,0 RET +bcid 608 106 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 609 107 WIDTH,1 OPT_CONST,0 RET +bcid 610 108 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 611 109 WIDTH,1 OPT_CONST,0 RET +bcid 612 110 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 613 111 WIDTH,1 OPT_CONST,0 RET +bcid 614 112 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 615 113 WIDTH,1 OPT_CONST,0 RET +bcid 616 114 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 617 115 WIDTH,1 OPT_CONST,0 RET +bcid 618 116 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 619 117 WIDTH,1 OPT_CONST,0 RET +bcid 620 118 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 621 119 WIDTH,1 OPT_CONST,0 RET +bcid 622 120 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 623 121 WIDTH,1 OPT_CONST,0 RET +bcid 624 122 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 625 123 WIDTH,1 OPT_CONST,0 RET +bcid 626 124 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 627 125 WIDTH,1 OPT_CONST,0 RET +bcid 628 126 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 629 127 WIDTH,1 OPT_CONST,0 RET +bcid 630 128 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 631 129 WIDTH,1 OPT_CONST,0 RET +bcid 632 130 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 633 131 WIDTH,1 OPT_CONST,0 RET +bcid 634 132 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 635 133 WIDTH,1 OPT_CONST,0 RET +bcid 636 134 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 637 135 WIDTH,1 OPT_CONST,0 RET +bcid 638 136 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 639 137 WIDTH,1 OPT_CONST,0 RET +bcid 640 138 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 641 139 WIDTH,1 OPT_CONST,0 RET +bcid 642 140 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 643 141 WIDTH,1 OPT_CONST,0 RET +bcid 644 142 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 645 143 WIDTH,1 OPT_CONST,0 RET +bcid 646 144 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 647 145 WIDTH,1 OPT_CONST,0 RET +bcid 648 146 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 649 147 WIDTH,1 OPT_CONST,0 RET +bcid 650 148 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 651 149 WIDTH,1 OPT_CONST,0 RET +bcid 652 150 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 653 151 WIDTH,1 OPT_CONST,0 RET +bcid 654 152 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 655 153 WIDTH,1 OPT_CONST,0 RET +bcid 656 154 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 657 155 WIDTH,1 OPT_CONST,0 RET +bcid 658 156 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 659 157 WIDTH,1 OPT_CONST,0 RET +bcid 660 158 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 661 159 WIDTH,1 OPT_CONST,0 RET +bcid 662 160 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 663 161 WIDTH,1 OPT_CONST,0 RET +bcid 664 162 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 665 163 WIDTH,1 OPT_CONST,0 RET +bcid 666 164 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 667 165 WIDTH,1 OPT_CONST,0 RET +bcid 668 166 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 669 167 WIDTH,1 OPT_CONST,0 RET +bcid 670 168 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 671 169 WIDTH,1 OPT_CONST,0 RET +bcid 672 170 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 673 171 WIDTH,1 OPT_CONST,0 RET +bcid 674 172 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 675 173 WIDTH,1 OPT_CONST,0 RET +bcid 676 174 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 677 175 WIDTH,1 OPT_CONST,0 RET +bcid 678 176 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 679 177 WIDTH,1 OPT_CONST,0 RET +bcid 680 178 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 681 179 WIDTH,1 OPT_CONST,0 RET +bcid 682 180 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 683 181 WIDTH,1 OPT_CONST,0 RET +bcid 684 182 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 685 183 WIDTH,1 OPT_CONST,0 RET +bcid 686 184 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 687 185 WIDTH,1 OPT_CONST,0 RET +bcid 688 186 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 689 187 WIDTH,1 OPT_CONST,0 RET +bcid 690 188 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 691 189 WIDTH,1 OPT_CONST,0 RET +bcid 692 190 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 693 191 WIDTH,1 OPT_CONST,0 RET +bcid 694 192 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 695 193 WIDTH,1 OPT_CONST,0 RET +bcid 696 194 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 697 195 WIDTH,1 OPT_CONST,0 RET +bcid 698 196 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 699 197 WIDTH,1 OPT_CONST,0 RET +bcid 700 198 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 701 199 WIDTH,1 OPT_CONST,0 RET +bcid 702 200 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 703 201 WIDTH,1 OPT_CONST,0 RET +bcid 704 202 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 705 203 WIDTH,1 OPT_CONST,0 RET +bcid 706 204 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 707 205 WIDTH,1 OPT_CONST,0 RET +bcid 708 206 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 709 207 WIDTH,1 OPT_CONST,0 RET +bcid 710 208 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 711 209 WIDTH,1 OPT_CONST,0 RET +bcid 712 210 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 713 211 WIDTH,1 OPT_CONST,0 RET +bcid 714 212 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 715 213 WIDTH,1 OPT_CONST,0 RET +bcid 716 214 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 717 215 WIDTH,1 OPT_CONST,0 RET +bcid 718 216 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 719 217 WIDTH,1 OPT_CONST,0 RET +bcid 720 218 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 721 219 WIDTH,1 OPT_CONST,0 RET +bcid 722 220 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 723 221 WIDTH,1 OPT_CONST,0 RET +bcid 724 222 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 725 223 WIDTH,1 OPT_CONST,0 RET +bcid 726 224 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 727 225 WIDTH,1 OPT_CONST,0 RET +bcid 728 226 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 729 227 WIDTH,1 OPT_CONST,0 RET +bcid 730 228 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 731 229 WIDTH,1 OPT_CONST,0 RET +bcid 732 230 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 733 231 WIDTH,1 OPT_CONST,0 RET +bcid 734 232 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 735 233 WIDTH,1 OPT_CONST,0 RET +bcid 736 234 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 737 235 WIDTH,1 OPT_CONST,0 RET +bcid 738 236 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 739 237 WIDTH,1 OPT_CONST,0 RET +bcid 740 238 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 741 239 WIDTH,1 OPT_CONST,0 RET +bcid 742 240 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 743 241 WIDTH,1 OPT_CONST,0 RET +bcid 744 242 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 745 243 WIDTH,1 OPT_CONST,0 RET +bcid 746 244 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 747 245 WIDTH,1 OPT_CONST,0 RET +bcid 748 246 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 749 247 WIDTH,1 OPT_CONST,0 RET +bcid 750 248 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 751 249 WIDTH,1 OPT_CONST,0 RET +bcid 752 250 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 753 251 WIDTH,1 OPT_CONST,0 RET +bcid 754 252 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 755 253 WIDTH,1 OPT_CONST,0 RET +bcid 756 254 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 757 255 WIDTH,1 OPT_CONST,0 RET +sid debug_top +bcid 758 0 WIDTH,1 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 NOT WIDTH,10 CALL_ARG_VAL,4,0 OPT_CONST,1023 WIDTH,1 M_EQU AND CALL_ARG_VAL,3,0 WIDTH,10 CALL_ARG_VAL,4,0 OPT_CONST,127 WIDTH,1 M_EQU AND OR AND RET +bcid 759 1 WIDTH,1 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 WIDTH,10 CALL_ARG_VAL,4,0 WIDTH,1 CALL_ARG_VAL,5,0 WIDTH,10 CALL_ARG_VAL,4,0 OPT_CONST,1 ADD CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 OPT_CONST,0 MITECONDNOINSTR,4 RET +bcid 760 2 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,32 MULTI_CONCATENATE,1,32 WIDTH,16 CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 WIDTH,32 CONCATENATE,2 AND WIDTH,1 CALL_ARG_VAL,5,0 WIDTH,32 MULTI_CONCATENATE,1,32 WIDTH,16 CALL_ARG_VAL,6,0 CALL_ARG_VAL,7,0 WIDTH,32 CONCATENATE,2 AND OR WIDTH,1 CALL_ARG_VAL,8,0 WIDTH,32 MULTI_CONCATENATE,1,32 WIDTH,16 CALL_ARG_VAL,9,0 CALL_ARG_VAL,10,0 WIDTH,32 CONCATENATE,2 AND WIDTH,1 CALL_ARG_VAL,11,0 WIDTH,32 MULTI_CONCATENATE,1,32 WIDTH,16 CALL_ARG_VAL,12,0 CALL_ARG_VAL,13,0 WIDTH,32 CONCATENATE,2 AND OR OR RET +bcid 761 3 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,32 CALL_ARG_VAL,3,0 WIDTH,256 CALL_ARG_VAL,4,0 WIDTH,32 OPT_CONST,32 WIDTH,224 SLICE,1 WIDTH,256 CONCATENATE,2 CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 RET +bcid 762 4 WIDTH,3 CALL_ARG_VAL,2,0 OPT_CONST,7 WIDTH,1 M_EQU CALL_ARG_VAL,3,0 AND NOT RET +bcid 763 5 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,256 CALL_ARG_VAL,3,0 WIDTH,1 CALL_ARG_VAL,4,0 WIDTH,256 CALL_ARG_VAL,5,0 WIDTH,1 CALL_ARG_VAL,6,0 WIDTH,256 CALL_ARG_VAL,7,0 WIDTH,1 CALL_ARG_VAL,8,0 WIDTH,256 CALL_ARG_VAL,9,0 CONST,0,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 764 6 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,12 CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 RET +bcid 765 7 WIDTH,1 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 RET +bcid 766 8 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,256 CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 RET +bcid 767 9 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,0 WIDTH,1 SLICE,1 WIDTH,8 MULTI_CONCATENATE,1,8 RET +bcid 768 10 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,1 WIDTH,1 SLICE,1 WIDTH,8 MULTI_CONCATENATE,1,8 RET +bcid 769 11 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,2 WIDTH,1 SLICE,1 WIDTH,8 MULTI_CONCATENATE,1,8 RET +bcid 770 12 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,3 WIDTH,1 SLICE,1 WIDTH,8 MULTI_CONCATENATE,1,8 RET +bcid 771 13 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,4 WIDTH,1 SLICE,1 WIDTH,8 MULTI_CONCATENATE,1,8 RET +bcid 772 14 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,5 WIDTH,1 SLICE,1 WIDTH,8 MULTI_CONCATENATE,1,8 RET +bcid 773 15 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,6 WIDTH,1 SLICE,1 WIDTH,8 MULTI_CONCATENATE,1,8 RET +bcid 774 16 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,7 WIDTH,1 SLICE,1 WIDTH,8 MULTI_CONCATENATE,1,8 RET +bcid 775 17 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,8 WIDTH,1 SLICE,1 WIDTH,8 MULTI_CONCATENATE,1,8 RET +bcid 776 18 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,9 WIDTH,1 SLICE,1 WIDTH,8 MULTI_CONCATENATE,1,8 RET +bcid 777 19 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,10 WIDTH,1 SLICE,1 WIDTH,8 MULTI_CONCATENATE,1,8 RET +bcid 778 20 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,11 WIDTH,1 SLICE,1 WIDTH,8 MULTI_CONCATENATE,1,8 RET +bcid 779 21 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,12 WIDTH,1 SLICE,1 WIDTH,8 MULTI_CONCATENATE,1,8 RET +bcid 780 22 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,13 WIDTH,1 SLICE,1 WIDTH,8 MULTI_CONCATENATE,1,8 RET +bcid 781 23 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,14 WIDTH,1 SLICE,1 WIDTH,8 MULTI_CONCATENATE,1,8 RET +bcid 782 24 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,15 WIDTH,1 SLICE,1 WIDTH,8 MULTI_CONCATENATE,1,8 RET +bcid 783 25 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,16 WIDTH,1 SLICE,1 WIDTH,8 MULTI_CONCATENATE,1,8 RET +bcid 784 26 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,17 WIDTH,1 SLICE,1 WIDTH,8 MULTI_CONCATENATE,1,8 RET +bcid 785 27 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,18 WIDTH,1 SLICE,1 WIDTH,8 MULTI_CONCATENATE,1,8 RET +bcid 786 28 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,19 WIDTH,1 SLICE,1 WIDTH,8 MULTI_CONCATENATE,1,8 RET +bcid 787 29 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,20 WIDTH,1 SLICE,1 WIDTH,8 MULTI_CONCATENATE,1,8 RET +bcid 788 30 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,21 WIDTH,1 SLICE,1 WIDTH,8 MULTI_CONCATENATE,1,8 RET +bcid 789 31 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,22 WIDTH,1 SLICE,1 WIDTH,8 MULTI_CONCATENATE,1,8 RET +bcid 790 32 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,23 WIDTH,1 SLICE,1 WIDTH,8 MULTI_CONCATENATE,1,8 RET +bcid 791 33 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,24 WIDTH,1 SLICE,1 WIDTH,8 MULTI_CONCATENATE,1,8 RET +bcid 792 34 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,25 WIDTH,1 SLICE,1 WIDTH,8 MULTI_CONCATENATE,1,8 RET +bcid 793 35 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,26 WIDTH,1 SLICE,1 WIDTH,8 MULTI_CONCATENATE,1,8 RET +bcid 794 36 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,27 WIDTH,1 SLICE,1 WIDTH,8 MULTI_CONCATENATE,1,8 RET +bcid 795 37 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,28 WIDTH,1 SLICE,1 WIDTH,8 MULTI_CONCATENATE,1,8 RET +bcid 796 38 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,29 WIDTH,1 SLICE,1 WIDTH,8 MULTI_CONCATENATE,1,8 RET +bcid 797 39 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,30 WIDTH,1 SLICE,1 WIDTH,8 MULTI_CONCATENATE,1,8 RET +bcid 798 40 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,31 WIDTH,1 SLICE,1 WIDTH,8 MULTI_CONCATENATE,1,8 RET +sid xyz_chip_top +bcid 799 0 WIDTH,17 OPT_CONST,0 RET +bcid 800 1 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,12 WIDTH,3 SLICE,1 WIDTH,1 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,5,0 WIDTH,32 OPT_CONST,12 WIDTH,3 SLICE,1 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 801 2 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,11 WIDTH,1 SLICE,1 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,5,0 WIDTH,32 OPT_CONST,11 WIDTH,1 SLICE,1 CALL_ARG_VAL,6,0 OPT_CONST,1 EQU WIDTH,12 CALL_ARG_VAL,7,0 WIDTH,32 OPT_CONST,11 WIDTH,1 SLICE,1 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 802 3 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,8 WIDTH,3 SLICE,1 WIDTH,1 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,5,0 WIDTH,32 OPT_CONST,8 WIDTH,3 SLICE,1 WIDTH,1 CALL_ARG_VAL,6,0 OPT_CONST,1 EQU WIDTH,11 CALL_ARG_VAL,7,0 WIDTH,32 OPT_CONST,8 WIDTH,3 SLICE,1 WIDTH,1 CALL_ARG_VAL,8,0 OPT_CONST,1 EQU WIDTH,11 CALL_ARG_VAL,9,0 WIDTH,32 OPT_CONST,8 WIDTH,3 SLICE,1 WIDTH,1 CALL_ARG_VAL,10,0 OPT_CONST,1 EQU WIDTH,12 CALL_ARG_VAL,11,0 WIDTH,32 OPT_CONST,8 WIDTH,3 SLICE,1 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 803 4 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 EQU WIDTH,8 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,7 WIDTH,1 SLICE,1 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,5,0 WIDTH,32 OPT_CONST,7 WIDTH,1 SLICE,1 CALL_ARG_VAL,6,0 OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,7,0 WIDTH,32 OPT_CONST,7 WIDTH,1 SLICE,1 CALL_ARG_VAL,8,0 OPT_CONST,1 EQU WIDTH,11 CALL_ARG_VAL,9,0 WIDTH,32 OPT_CONST,7 WIDTH,1 SLICE,1 CALL_ARG_VAL,10,0 OPT_CONST,1 EQU WIDTH,11 CALL_ARG_VAL,11,0 WIDTH,32 OPT_CONST,7 WIDTH,1 SLICE,1 CALL_ARG_VAL,12,0 OPT_CONST,1 EQU WIDTH,12 CALL_ARG_VAL,13,0 WIDTH,32 OPT_CONST,7 WIDTH,1 SLICE,1 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 804 5 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 EQU WIDTH,8 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,6 WIDTH,1 SLICE,1 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,5,0 WIDTH,32 OPT_CONST,6 WIDTH,1 SLICE,1 CALL_ARG_VAL,6,0 OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,7,0 WIDTH,32 OPT_CONST,6 WIDTH,1 SLICE,1 CALL_ARG_VAL,8,0 OPT_CONST,1 EQU WIDTH,11 CALL_ARG_VAL,9,0 WIDTH,32 OPT_CONST,6 WIDTH,1 SLICE,1 CALL_ARG_VAL,10,0 OPT_CONST,1 EQU WIDTH,11 CALL_ARG_VAL,11,0 WIDTH,32 OPT_CONST,6 WIDTH,1 SLICE,1 CALL_ARG_VAL,12,0 OPT_CONST,1 EQU WIDTH,7 CALL_ARG_VAL,13,0 WIDTH,32 OPT_CONST,6 WIDTH,1 SLICE,1 CALL_ARG_VAL,14,0 OPT_CONST,1 EQU WIDTH,12 CALL_ARG_VAL,15,0 WIDTH,32 OPT_CONST,6 WIDTH,1 SLICE,1 CALL_ARG_VAL,16,0 OPT_CONST,1 EQU WIDTH,7 CALL_ARG_VAL,17,0 WIDTH,32 OPT_CONST,6 WIDTH,1 SLICE,1 CALL_ARG_VAL,18,0 OPT_CONST,1 EQU WIDTH,7 CALL_ARG_VAL,19,0 WIDTH,32 OPT_CONST,6 WIDTH,1 SLICE,1 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 805 6 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 EQU WIDTH,8 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,5 WIDTH,1 SLICE,1 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,5,0 WIDTH,32 OPT_CONST,5 WIDTH,1 SLICE,1 CALL_ARG_VAL,6,0 OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,7,0 WIDTH,32 OPT_CONST,5 WIDTH,1 SLICE,1 CALL_ARG_VAL,8,0 OPT_CONST,1 EQU WIDTH,11 CALL_ARG_VAL,9,0 WIDTH,32 OPT_CONST,5 WIDTH,1 SLICE,1 CALL_ARG_VAL,10,0 OPT_CONST,1 EQU WIDTH,11 CALL_ARG_VAL,11,0 WIDTH,32 OPT_CONST,5 WIDTH,1 SLICE,1 CALL_ARG_VAL,12,0 OPT_CONST,1 EQU WIDTH,7 CALL_ARG_VAL,13,0 WIDTH,32 OPT_CONST,5 WIDTH,1 SLICE,1 CALL_ARG_VAL,14,0 OPT_CONST,1 EQU WIDTH,12 CALL_ARG_VAL,15,0 WIDTH,32 OPT_CONST,5 WIDTH,1 SLICE,1 CALL_ARG_VAL,16,0 OPT_CONST,1 EQU WIDTH,7 CALL_ARG_VAL,17,0 WIDTH,32 OPT_CONST,5 WIDTH,1 SLICE,1 CALL_ARG_VAL,18,0 OPT_CONST,1 EQU WIDTH,6 CALL_ARG_VAL,19,0 WIDTH,32 OPT_CONST,5 WIDTH,1 SLICE,1 CALL_ARG_VAL,20,0 OPT_CONST,1 EQU WIDTH,7 CALL_ARG_VAL,21,0 WIDTH,32 OPT_CONST,5 WIDTH,1 SLICE,1 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 806 7 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 EQU WIDTH,8 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,4 WIDTH,1 SLICE,1 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,5,0 WIDTH,32 OPT_CONST,4 WIDTH,1 SLICE,1 CALL_ARG_VAL,6,0 OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,7,0 WIDTH,32 OPT_CONST,4 WIDTH,1 SLICE,1 CALL_ARG_VAL,8,0 OPT_CONST,1 EQU WIDTH,11 CALL_ARG_VAL,9,0 WIDTH,32 OPT_CONST,4 WIDTH,1 SLICE,1 CALL_ARG_VAL,10,0 OPT_CONST,1 EQU WIDTH,11 CALL_ARG_VAL,11,0 WIDTH,32 OPT_CONST,4 WIDTH,1 SLICE,1 CALL_ARG_VAL,12,0 OPT_CONST,1 EQU WIDTH,5 CALL_ARG_VAL,13,0 WIDTH,32 OPT_CONST,4 WIDTH,1 SLICE,1 CALL_ARG_VAL,14,0 OPT_CONST,1 EQU WIDTH,7 CALL_ARG_VAL,15,0 WIDTH,32 OPT_CONST,4 WIDTH,1 SLICE,1 CALL_ARG_VAL,16,0 OPT_CONST,1 EQU WIDTH,12 CALL_ARG_VAL,17,0 WIDTH,32 OPT_CONST,4 WIDTH,1 SLICE,1 CALL_ARG_VAL,18,0 OPT_CONST,1 EQU WIDTH,7 CALL_ARG_VAL,19,0 WIDTH,32 OPT_CONST,4 WIDTH,1 SLICE,1 CALL_ARG_VAL,20,0 OPT_CONST,1 EQU WIDTH,6 CALL_ARG_VAL,21,0 WIDTH,32 OPT_CONST,4 WIDTH,1 SLICE,1 CALL_ARG_VAL,22,0 OPT_CONST,1 EQU WIDTH,7 CALL_ARG_VAL,23,0 WIDTH,32 OPT_CONST,4 WIDTH,1 SLICE,1 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 807 8 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 EQU WIDTH,8 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,5,0 WIDTH,32 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,6,0 OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,7,0 WIDTH,32 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,8,0 OPT_CONST,1 EQU WIDTH,4 CALL_ARG_VAL,9,0 WIDTH,32 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,10,0 OPT_CONST,1 EQU WIDTH,11 CALL_ARG_VAL,11,0 WIDTH,32 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,12,0 OPT_CONST,1 EQU WIDTH,11 CALL_ARG_VAL,13,0 WIDTH,32 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,14,0 OPT_CONST,1 EQU WIDTH,5 CALL_ARG_VAL,15,0 WIDTH,32 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,16,0 OPT_CONST,1 EQU WIDTH,7 CALL_ARG_VAL,17,0 WIDTH,32 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,18,0 OPT_CONST,1 EQU WIDTH,12 CALL_ARG_VAL,19,0 WIDTH,32 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,20,0 OPT_CONST,1 EQU WIDTH,7 CALL_ARG_VAL,21,0 WIDTH,32 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,22,0 OPT_CONST,1 EQU WIDTH,6 CALL_ARG_VAL,23,0 WIDTH,32 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,24,0 OPT_CONST,1 EQU WIDTH,7 CALL_ARG_VAL,25,0 WIDTH,32 OPT_CONST,3 WIDTH,1 SLICE,1 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 808 9 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 EQU WIDTH,8 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,2 WIDTH,1 SLICE,1 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU WIDTH,3 CALL_ARG_VAL,5,0 WIDTH,32 OPT_CONST,2 WIDTH,1 SLICE,1 CALL_ARG_VAL,6,0 OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,7,0 WIDTH,32 OPT_CONST,2 WIDTH,1 SLICE,1 CALL_ARG_VAL,8,0 OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,9,0 WIDTH,32 OPT_CONST,2 WIDTH,1 SLICE,1 CALL_ARG_VAL,10,0 OPT_CONST,1 EQU WIDTH,4 CALL_ARG_VAL,11,0 WIDTH,32 OPT_CONST,2 WIDTH,1 SLICE,1 CALL_ARG_VAL,12,0 OPT_CONST,1 EQU WIDTH,11 CALL_ARG_VAL,13,0 WIDTH,32 OPT_CONST,2 WIDTH,1 SLICE,1 CALL_ARG_VAL,14,0 OPT_CONST,1 EQU WIDTH,11 CALL_ARG_VAL,15,0 WIDTH,32 OPT_CONST,2 WIDTH,1 SLICE,1 CALL_ARG_VAL,16,0 OPT_CONST,1 EQU WIDTH,5 CALL_ARG_VAL,17,0 WIDTH,32 OPT_CONST,2 WIDTH,1 SLICE,1 CALL_ARG_VAL,18,0 OPT_CONST,1 EQU WIDTH,7 CALL_ARG_VAL,19,0 WIDTH,32 OPT_CONST,2 WIDTH,1 SLICE,1 CALL_ARG_VAL,20,0 OPT_CONST,1 EQU WIDTH,12 CALL_ARG_VAL,21,0 WIDTH,32 OPT_CONST,2 WIDTH,1 SLICE,1 CALL_ARG_VAL,22,0 OPT_CONST,1 EQU WIDTH,3 CALL_ARG_VAL,23,0 WIDTH,32 OPT_CONST,2 WIDTH,1 SLICE,1 CALL_ARG_VAL,24,0 OPT_CONST,1 EQU WIDTH,3 CALL_ARG_VAL,25,0 WIDTH,32 OPT_CONST,2 WIDTH,1 SLICE,1 CALL_ARG_VAL,26,0 OPT_CONST,1 EQU WIDTH,7 CALL_ARG_VAL,27,0 WIDTH,32 OPT_CONST,2 WIDTH,1 SLICE,1 CALL_ARG_VAL,28,0 OPT_CONST,1 EQU WIDTH,6 CALL_ARG_VAL,29,0 WIDTH,32 OPT_CONST,2 WIDTH,1 SLICE,1 CALL_ARG_VAL,30,0 OPT_CONST,1 EQU WIDTH,3 CALL_ARG_VAL,31,0 WIDTH,32 OPT_CONST,2 WIDTH,1 SLICE,1 CALL_ARG_VAL,32,0 OPT_CONST,1 EQU WIDTH,7 CALL_ARG_VAL,33,0 WIDTH,32 OPT_CONST,2 WIDTH,1 SLICE,1 CALL_ARG_VAL,34,0 OPT_CONST,1 EQU WIDTH,3 CALL_ARG_VAL,35,0 WIDTH,32 OPT_CONST,2 WIDTH,1 SLICE,1 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 809 10 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 EQU WIDTH,2 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU WIDTH,2 CALL_ARG_VAL,5,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,6,0 OPT_CONST,1 EQU WIDTH,8 CALL_ARG_VAL,7,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,8,0 OPT_CONST,1 EQU WIDTH,3 CALL_ARG_VAL,9,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,10,0 OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,11,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,12,0 OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,13,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,14,0 OPT_CONST,1 EQU WIDTH,4 CALL_ARG_VAL,15,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,16,0 OPT_CONST,1 EQU WIDTH,11 CALL_ARG_VAL,17,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,18,0 OPT_CONST,1 EQU WIDTH,11 CALL_ARG_VAL,19,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,20,0 OPT_CONST,1 EQU WIDTH,5 CALL_ARG_VAL,21,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,22,0 OPT_CONST,1 EQU WIDTH,7 CALL_ARG_VAL,23,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,24,0 OPT_CONST,1 EQU WIDTH,12 CALL_ARG_VAL,25,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,26,0 OPT_CONST,1 EQU WIDTH,3 CALL_ARG_VAL,27,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,28,0 OPT_CONST,1 EQU WIDTH,3 CALL_ARG_VAL,29,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,30,0 OPT_CONST,1 EQU WIDTH,7 CALL_ARG_VAL,31,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,32,0 OPT_CONST,1 EQU WIDTH,6 CALL_ARG_VAL,33,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,34,0 OPT_CONST,1 EQU WIDTH,3 CALL_ARG_VAL,35,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,36,0 OPT_CONST,1 EQU WIDTH,7 CALL_ARG_VAL,37,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,38,0 OPT_CONST,1 EQU WIDTH,3 CALL_ARG_VAL,39,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 810 11 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 EQU WIDTH,2 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU WIDTH,2 CALL_ARG_VAL,5,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,6,0 OPT_CONST,1 EQU CALL_ARG_VAL,7,0 CALL_ARG_VAL,8,0 OPT_CONST,1 EQU WIDTH,8 CALL_ARG_VAL,9,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,10,0 OPT_CONST,1 EQU WIDTH,3 CALL_ARG_VAL,11,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,12,0 OPT_CONST,1 EQU CALL_ARG_VAL,13,0 CALL_ARG_VAL,14,0 OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,15,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,16,0 OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,17,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,18,0 OPT_CONST,1 EQU WIDTH,4 CALL_ARG_VAL,19,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,20,0 OPT_CONST,1 EQU WIDTH,11 CALL_ARG_VAL,21,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,22,0 OPT_CONST,1 EQU WIDTH,11 CALL_ARG_VAL,23,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,24,0 OPT_CONST,1 EQU WIDTH,5 CALL_ARG_VAL,25,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,26,0 OPT_CONST,1 EQU WIDTH,7 CALL_ARG_VAL,27,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,28,0 OPT_CONST,1 EQU WIDTH,12 CALL_ARG_VAL,29,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,30,0 OPT_CONST,1 EQU WIDTH,3 CALL_ARG_VAL,31,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,32,0 OPT_CONST,1 EQU WIDTH,3 CALL_ARG_VAL,33,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,34,0 OPT_CONST,1 EQU WIDTH,7 CALL_ARG_VAL,35,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,36,0 OPT_CONST,1 EQU WIDTH,6 CALL_ARG_VAL,37,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,38,0 OPT_CONST,1 EQU WIDTH,3 CALL_ARG_VAL,39,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,40,0 OPT_CONST,1 EQU WIDTH,7 CALL_ARG_VAL,41,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,42,0 OPT_CONST,1 EQU WIDTH,3 CALL_ARG_VAL,43,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 811 12 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,2 PAD RET +bcid 812 13 WIDTH,6 CALL_ARG_VAL,2,0 OPT_CONST,0 WIDTH,1 M_EQU RET +bcid 813 14 WIDTH,6 CALL_ARG_VAL,2,0 OPT_CONST,1 WIDTH,1 M_EQU RET +bcid 814 15 WIDTH,6 CALL_ARG_VAL,2,0 OPT_CONST,2 WIDTH,1 M_EQU RET +bcid 815 16 WIDTH,6 CALL_ARG_VAL,2,0 OPT_CONST,3 WIDTH,1 M_EQU RET +bcid 816 17 WIDTH,6 CALL_ARG_VAL,2,0 OPT_CONST,4 WIDTH,1 M_EQU RET +bcid 817 18 WIDTH,6 CALL_ARG_VAL,2,0 OPT_CONST,5 WIDTH,1 M_EQU RET +bcid 818 19 WIDTH,6 CALL_ARG_VAL,2,0 OPT_CONST,6 WIDTH,1 M_EQU RET +bcid 819 20 WIDTH,6 CALL_ARG_VAL,2,0 OPT_CONST,7 WIDTH,1 M_EQU RET +bcid 820 21 WIDTH,6 CALL_ARG_VAL,2,0 OPT_CONST,8 WIDTH,1 M_EQU RET +bcid 821 22 WIDTH,6 CALL_ARG_VAL,2,0 OPT_CONST,9 WIDTH,1 M_EQU RET +bcid 822 23 WIDTH,6 CALL_ARG_VAL,2,0 OPT_CONST,10 WIDTH,1 M_EQU RET +bcid 823 24 WIDTH,6 CALL_ARG_VAL,2,0 OPT_CONST,11 WIDTH,1 M_EQU RET +bcid 824 25 WIDTH,6 CALL_ARG_VAL,2,0 OPT_CONST,12 WIDTH,1 M_EQU RET +bcid 825 26 WIDTH,6 CALL_ARG_VAL,2,0 OPT_CONST,13 WIDTH,1 M_EQU RET +bcid 826 27 WIDTH,6 CALL_ARG_VAL,2,0 OPT_CONST,14 WIDTH,1 M_EQU RET +bcid 827 28 WIDTH,6 CALL_ARG_VAL,2,0 OPT_CONST,15 WIDTH,1 M_EQU RET +bcid 828 29 WIDTH,6 CALL_ARG_VAL,2,0 OPT_CONST,16 WIDTH,1 M_EQU RET +bcid 829 30 WIDTH,6 CALL_ARG_VAL,2,0 OPT_CONST,17 WIDTH,1 M_EQU RET +bcid 830 31 WIDTH,6 CALL_ARG_VAL,2,0 OPT_CONST,18 WIDTH,1 M_EQU RET +bcid 831 32 WIDTH,6 CALL_ARG_VAL,2,0 OPT_CONST,19 WIDTH,1 M_EQU RET +bcid 832 33 WIDTH,6 CALL_ARG_VAL,2,0 OPT_CONST,20 WIDTH,1 M_EQU RET +bcid 833 34 WIDTH,6 CALL_ARG_VAL,2,0 OPT_CONST,21 WIDTH,1 M_EQU RET +bcid 834 35 WIDTH,26 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 WIDTH,25 MULTI_CONCATENATE,1,25 WIDTH,5 OPT_CONST,0 WIDTH,25 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,0 WIDTH,20 SLICE,1 WIDTH,25 CONCATENATE,2 AND RET +bcid 835 36 WIDTH,26 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 WIDTH,25 MULTI_CONCATENATE,1,25 WIDTH,5 OPT_CONST,0 WIDTH,25 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,0 WIDTH,20 SLICE,1 WIDTH,25 CONCATENATE,2 AND RET +bcid 836 37 WIDTH,26 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,2 WIDTH,1 SLICE,1 WIDTH,25 MULTI_CONCATENATE,1,25 WIDTH,5 OPT_CONST,0 WIDTH,25 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,0 WIDTH,20 SLICE,1 WIDTH,25 CONCATENATE,2 AND RET +bcid 837 38 WIDTH,26 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,3 WIDTH,1 SLICE,1 WIDTH,25 MULTI_CONCATENATE,1,25 WIDTH,5 OPT_CONST,0 WIDTH,25 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,0 WIDTH,20 SLICE,1 WIDTH,25 CONCATENATE,2 AND RET +bcid 838 39 WIDTH,26 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,4 WIDTH,1 SLICE,1 WIDTH,25 MULTI_CONCATENATE,1,25 WIDTH,5 OPT_CONST,0 WIDTH,25 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,0 WIDTH,20 SLICE,1 WIDTH,25 CONCATENATE,2 AND RET +bcid 839 40 WIDTH,26 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,5 WIDTH,1 SLICE,1 WIDTH,25 MULTI_CONCATENATE,1,25 WIDTH,5 OPT_CONST,0 WIDTH,25 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,0 WIDTH,20 SLICE,1 WIDTH,25 CONCATENATE,2 AND RET +bcid 840 41 WIDTH,26 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,6 WIDTH,1 SLICE,1 WIDTH,25 MULTI_CONCATENATE,1,25 WIDTH,5 OPT_CONST,0 WIDTH,25 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,0 WIDTH,20 SLICE,1 WIDTH,25 CONCATENATE,2 AND RET +bcid 841 42 WIDTH,26 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,7 WIDTH,1 SLICE,1 WIDTH,25 MULTI_CONCATENATE,1,25 WIDTH,5 OPT_CONST,0 WIDTH,25 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,0 WIDTH,20 SLICE,1 WIDTH,25 CONCATENATE,2 AND RET +bcid 842 43 WIDTH,26 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,8 WIDTH,1 SLICE,1 WIDTH,25 MULTI_CONCATENATE,1,25 WIDTH,5 OPT_CONST,0 WIDTH,25 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,0 WIDTH,20 SLICE,1 WIDTH,25 CONCATENATE,2 AND RET +bcid 843 44 WIDTH,26 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,9 WIDTH,1 SLICE,1 WIDTH,25 MULTI_CONCATENATE,1,25 WIDTH,5 OPT_CONST,0 WIDTH,25 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,0 WIDTH,20 SLICE,1 WIDTH,25 CONCATENATE,2 AND RET +bcid 844 45 WIDTH,26 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,10 WIDTH,1 SLICE,1 WIDTH,25 MULTI_CONCATENATE,1,25 WIDTH,5 OPT_CONST,0 WIDTH,25 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,0 WIDTH,20 SLICE,1 WIDTH,25 CONCATENATE,2 AND RET +bcid 845 46 WIDTH,26 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,11 WIDTH,1 SLICE,1 WIDTH,25 MULTI_CONCATENATE,1,25 WIDTH,5 OPT_CONST,0 WIDTH,25 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,0 WIDTH,20 SLICE,1 WIDTH,25 CONCATENATE,2 AND RET +bcid 846 47 WIDTH,26 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,12 WIDTH,1 SLICE,1 WIDTH,25 MULTI_CONCATENATE,1,25 WIDTH,5 OPT_CONST,0 WIDTH,25 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,0 WIDTH,20 SLICE,1 WIDTH,25 CONCATENATE,2 AND RET +bcid 847 48 WIDTH,26 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,13 WIDTH,1 SLICE,1 WIDTH,25 MULTI_CONCATENATE,1,25 WIDTH,5 OPT_CONST,0 WIDTH,25 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,0 WIDTH,20 SLICE,1 WIDTH,25 CONCATENATE,2 AND RET +bcid 848 49 WIDTH,26 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,14 WIDTH,1 SLICE,1 WIDTH,25 MULTI_CONCATENATE,1,25 WIDTH,5 OPT_CONST,0 WIDTH,25 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,0 WIDTH,20 SLICE,1 WIDTH,25 CONCATENATE,2 AND RET +bcid 849 50 WIDTH,26 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,15 WIDTH,1 SLICE,1 WIDTH,25 MULTI_CONCATENATE,1,25 WIDTH,5 OPT_CONST,0 WIDTH,25 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,0 WIDTH,20 SLICE,1 WIDTH,25 CONCATENATE,2 AND RET +bcid 850 51 WIDTH,26 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,16 WIDTH,1 SLICE,1 WIDTH,25 MULTI_CONCATENATE,1,25 WIDTH,5 OPT_CONST,0 WIDTH,25 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,0 WIDTH,20 SLICE,1 WIDTH,25 CONCATENATE,2 AND RET +bcid 851 52 WIDTH,26 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,17 WIDTH,1 SLICE,1 WIDTH,25 MULTI_CONCATENATE,1,25 WIDTH,5 OPT_CONST,0 WIDTH,25 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,0 WIDTH,20 SLICE,1 WIDTH,25 CONCATENATE,2 AND RET +bcid 852 53 WIDTH,26 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,18 WIDTH,1 SLICE,1 WIDTH,25 MULTI_CONCATENATE,1,25 WIDTH,5 OPT_CONST,0 WIDTH,25 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,0 WIDTH,20 SLICE,1 WIDTH,25 CONCATENATE,2 AND RET +bcid 853 54 WIDTH,26 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,19 WIDTH,1 SLICE,1 WIDTH,25 MULTI_CONCATENATE,1,25 WIDTH,5 OPT_CONST,0 WIDTH,25 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,0 WIDTH,20 SLICE,1 WIDTH,25 CONCATENATE,2 AND RET +bcid 854 55 WIDTH,26 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,20 WIDTH,1 SLICE,1 WIDTH,25 MULTI_CONCATENATE,1,25 WIDTH,5 OPT_CONST,0 WIDTH,25 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,0 WIDTH,20 SLICE,1 WIDTH,25 CONCATENATE,2 AND RET +bcid 855 56 WIDTH,26 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,21 WIDTH,1 SLICE,1 WIDTH,25 MULTI_CONCATENATE,1,25 WIDTH,5 OPT_CONST,0 WIDTH,25 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,0 WIDTH,20 SLICE,1 WIDTH,25 CONCATENATE,2 AND RET +bcid 856 57 WIDTH,26 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,22 WIDTH,1 SLICE,1 WIDTH,25 MULTI_CONCATENATE,1,25 WIDTH,5 OPT_CONST,0 WIDTH,25 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,0 WIDTH,20 SLICE,1 WIDTH,25 CONCATENATE,2 AND RET +bcid 857 58 WIDTH,26 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,23 WIDTH,1 SLICE,1 WIDTH,25 MULTI_CONCATENATE,1,25 WIDTH,5 OPT_CONST,0 WIDTH,25 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,0 WIDTH,20 SLICE,1 WIDTH,25 CONCATENATE,2 AND RET +bcid 858 59 WIDTH,26 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,24 WIDTH,1 SLICE,1 WIDTH,25 MULTI_CONCATENATE,1,25 WIDTH,5 OPT_CONST,0 WIDTH,25 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,0 WIDTH,20 SLICE,1 WIDTH,25 CONCATENATE,2 AND RET +bcid 859 60 WIDTH,26 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,25 WIDTH,1 SLICE,1 WIDTH,25 MULTI_CONCATENATE,1,25 WIDTH,5 OPT_CONST,0 WIDTH,25 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,0 WIDTH,20 SLICE,1 WIDTH,25 CONCATENATE,2 AND RET +bcid 860 61 WIDTH,26 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 WIDTH,32 MULTI_CONCATENATE,1,32 CALL_ARG_VAL,3,0 AND RET +bcid 861 62 WIDTH,26 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 WIDTH,32 MULTI_CONCATENATE,1,32 CALL_ARG_VAL,3,0 AND RET +bcid 862 63 WIDTH,26 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,2 WIDTH,1 SLICE,1 WIDTH,32 MULTI_CONCATENATE,1,32 CALL_ARG_VAL,3,0 AND RET +bcid 863 64 WIDTH,26 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,3 WIDTH,1 SLICE,1 WIDTH,32 MULTI_CONCATENATE,1,32 CALL_ARG_VAL,3,0 AND RET +bcid 864 65 WIDTH,26 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,4 WIDTH,1 SLICE,1 WIDTH,32 MULTI_CONCATENATE,1,32 CALL_ARG_VAL,3,0 AND RET +bcid 865 66 WIDTH,26 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,5 WIDTH,1 SLICE,1 WIDTH,32 MULTI_CONCATENATE,1,32 CALL_ARG_VAL,3,0 AND RET +bcid 866 67 WIDTH,26 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,6 WIDTH,1 SLICE,1 WIDTH,32 MULTI_CONCATENATE,1,32 CALL_ARG_VAL,3,0 AND RET +bcid 867 68 WIDTH,26 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,7 WIDTH,1 SLICE,1 WIDTH,32 MULTI_CONCATENATE,1,32 CALL_ARG_VAL,3,0 AND RET +bcid 868 69 WIDTH,26 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,8 WIDTH,1 SLICE,1 WIDTH,32 MULTI_CONCATENATE,1,32 CALL_ARG_VAL,3,0 AND RET +bcid 869 70 WIDTH,26 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,9 WIDTH,1 SLICE,1 WIDTH,32 MULTI_CONCATENATE,1,32 CALL_ARG_VAL,3,0 AND RET +bcid 870 71 WIDTH,26 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,10 WIDTH,1 SLICE,1 WIDTH,32 MULTI_CONCATENATE,1,32 CALL_ARG_VAL,3,0 AND RET +bcid 871 72 WIDTH,26 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,11 WIDTH,1 SLICE,1 WIDTH,32 MULTI_CONCATENATE,1,32 CALL_ARG_VAL,3,0 AND RET +bcid 872 73 WIDTH,26 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,12 WIDTH,1 SLICE,1 WIDTH,32 MULTI_CONCATENATE,1,32 CALL_ARG_VAL,3,0 AND RET +bcid 873 74 WIDTH,26 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,13 WIDTH,1 SLICE,1 WIDTH,32 MULTI_CONCATENATE,1,32 CALL_ARG_VAL,3,0 AND RET +bcid 874 75 WIDTH,26 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,14 WIDTH,1 SLICE,1 WIDTH,32 MULTI_CONCATENATE,1,32 CALL_ARG_VAL,3,0 AND RET +bcid 875 76 WIDTH,26 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,15 WIDTH,1 SLICE,1 WIDTH,32 MULTI_CONCATENATE,1,32 CALL_ARG_VAL,3,0 AND RET +bcid 876 77 WIDTH,26 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,16 WIDTH,1 SLICE,1 WIDTH,32 MULTI_CONCATENATE,1,32 CALL_ARG_VAL,3,0 AND RET +bcid 877 78 WIDTH,26 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,17 WIDTH,1 SLICE,1 WIDTH,32 MULTI_CONCATENATE,1,32 CALL_ARG_VAL,3,0 AND RET +bcid 878 79 WIDTH,26 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,18 WIDTH,1 SLICE,1 WIDTH,32 MULTI_CONCATENATE,1,32 CALL_ARG_VAL,3,0 AND RET +bcid 879 80 WIDTH,26 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,19 WIDTH,1 SLICE,1 WIDTH,32 MULTI_CONCATENATE,1,32 CALL_ARG_VAL,3,0 AND RET +bcid 880 81 WIDTH,26 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,20 WIDTH,1 SLICE,1 WIDTH,32 MULTI_CONCATENATE,1,32 CALL_ARG_VAL,3,0 AND RET +bcid 881 82 WIDTH,26 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,21 WIDTH,1 SLICE,1 WIDTH,32 MULTI_CONCATENATE,1,32 CALL_ARG_VAL,3,0 AND RET +bcid 882 83 WIDTH,26 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,22 WIDTH,1 SLICE,1 WIDTH,32 MULTI_CONCATENATE,1,32 CALL_ARG_VAL,3,0 AND RET +bcid 883 84 WIDTH,26 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,23 WIDTH,1 SLICE,1 WIDTH,32 MULTI_CONCATENATE,1,32 CALL_ARG_VAL,3,0 AND RET +bcid 884 85 WIDTH,26 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,24 WIDTH,1 SLICE,1 WIDTH,32 MULTI_CONCATENATE,1,32 CALL_ARG_VAL,3,0 AND RET +bcid 885 86 WIDTH,26 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,25 WIDTH,1 SLICE,1 WIDTH,32 MULTI_CONCATENATE,1,32 CALL_ARG_VAL,3,0 AND RET +bcid 886 87 WIDTH,26 CALL_ARG_VAL,2,0 WIDTH,1 CALL_ARG_VAL,3,0 WIDTH,26 MULTI_CONCATENATE,1,26 AND RET +sid thermo2binary_top +bcid 887 0 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,4 PAD WIDTH,1 CALL_ARG_VAL,3,0 WIDTH,4 PAD WIDTH,1 CALL_ARG_VAL,4,0 WIDTH,4 PAD ADD ADD WIDTH,1 CALL_ARG_VAL,5,0 WIDTH,4 PAD WIDTH,1 CALL_ARG_VAL,6,0 WIDTH,4 PAD ADD WIDTH,1 CALL_ARG_VAL,7,0 WIDTH,4 PAD WIDTH,1 CALL_ARG_VAL,8,0 WIDTH,4 PAD ADD ADD ADD WIDTH,1 CALL_ARG_VAL,9,0 WIDTH,4 PAD WIDTH,1 CALL_ARG_VAL,10,0 WIDTH,4 PAD ADD WIDTH,1 CALL_ARG_VAL,11,0 WIDTH,4 PAD WIDTH,1 CALL_ARG_VAL,12,0 WIDTH,4 PAD ADD ADD WIDTH,1 CALL_ARG_VAL,13,0 WIDTH,4 PAD WIDTH,1 CALL_ARG_VAL,14,0 WIDTH,4 PAD ADD WIDTH,1 CALL_ARG_VAL,15,0 WIDTH,4 PAD WIDTH,1 CALL_ARG_VAL,16,0 WIDTH,4 PAD ADD ADD ADD ADD RET +bcid 888 1 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,3 PAD WIDTH,1 CALL_ARG_VAL,3,0 WIDTH,3 PAD WIDTH,1 CALL_ARG_VAL,4,0 WIDTH,3 PAD ADD ADD WIDTH,1 CALL_ARG_VAL,5,0 WIDTH,3 PAD WIDTH,1 CALL_ARG_VAL,6,0 WIDTH,3 PAD ADD WIDTH,1 CALL_ARG_VAL,7,0 WIDTH,3 PAD WIDTH,1 CALL_ARG_VAL,8,0 WIDTH,3 PAD ADD ADD ADD RET +sid TB +bcid 889 0 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,0 WIDTH,1 CALL_ARG_VAL,3,0 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,1 ADD CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 890 1 WIDTH,4 CALL_ARG_VAL,2,0 OPT_CONST,8 WIDTH,1 M_EQU RET +sid DW01_addsub +bcid 891 0 WIDTH,4 CALL_ARG_VAL,2,0 CALL_ARG_VAL,2,0 XOR WIDTH,1 XOR_REDUCE OPT_CONST,0 NEQU WIDTH,4 CALL_ARG_VAL,3,0 CALL_ARG_VAL,3,0 XOR WIDTH,1 XOR_REDUCE OPT_CONST,0 NEQU CALL_ARG_VAL,4,0 CALL_ARG_VAL,4,0 XOR XOR_REDUCE OPT_CONST,0 NEQU OR OR WIDTH,5 OPT_CONST_4ST,31,31 WIDTH,1 CALL_ARG_VAL,4,0 WIDTH,4 CALL_ARG_VAL,2,0 WIDTH,5 PAD WIDTH,4 CALL_ARG_VAL,3,0 WIDTH,5 PAD SUBTRACT WIDTH,1 CALL_ARG_VAL,5,0 WIDTH,5 PAD SUBTRACT WIDTH,4 CALL_ARG_VAL,2,0 WIDTH,5 PAD WIDTH,4 CALL_ARG_VAL,3,0 WIDTH,5 PAD WIDTH,1 CALL_ARG_VAL,5,0 WIDTH,5 PAD ADD ADD MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET diff --git a/tb/chip_top/simv.daidir/cc/cc_dummy_file b/tb/chip_top/simv.daidir/cc/cc_dummy_file new file mode 100644 index 0000000..9ec9235 --- /dev/null +++ b/tb/chip_top/simv.daidir/cc/cc_dummy_file @@ -0,0 +1,2 @@ +Dummy_file +Missing line/file info diff --git a/tb/chip_top/simv.daidir/cgname.json b/tb/chip_top/simv.daidir/cgname.json new file mode 100644 index 0000000..41c21a1 --- /dev/null +++ b/tb/chip_top/simv.daidir/cgname.json @@ -0,0 +1,260 @@ +{ + "tsdn28hpcpuhdb4096x32m4mw_170a": [ + "tsdn28hpcpuhdb4096x32m4mw_170a", + "d6TPd", + "module", + 14 + ], + "tsdn28hpcpuhdb128x128m4mw_170a_Int_Array": [ + "tsdn28hpcpuhdb128x128m4mw_170a_Int_Array", + "eFLuy", + "module", + 13 + ], + "_vcs_unit__3598111382": [ + "_vcs_unit__3598111382", + "QyjH7", + "module", + 1 + ], + "std": [ + "std", + "reYIK", + "module", + 2 + ], + "tsdn28hpcpuhdb64x32m4mw_170a_Int_Array": [ + "tsdn28hpcpuhdb64x32m4mw_170a_Int_Array", + "JweIx", + "module", + 16 + ], + "tsdn28hpcpuhdb4096x32m4mw_170a_Int_Array": [ + "tsdn28hpcpuhdb4096x32m4mw_170a_Int_Array", + "ay4xz", + "module", + 15 + ], + "sram_if": [ + "sram_if", + "NABmh", + "module", + 3 + ], + "DUC_HB2": [ + "DUC_HB2", + "ksFw4", + "module", + 30 + ], + "modout_mux": [ + "modout_mux", + "jEu9i", + "module", + 7 + ], + "spi_if": [ + "spi_if", + "IHYdB", + "module", + 42 + ], + "qbmcu_datalatch": [ + "qbmcu_datalatch", + "MsCBG", + "module", + 21 + ], + "sirv_gnrl_dffl": [ + "sirv_gnrl_dffl", + "BM4bj", + "module", + 8 + ], + "sram_if_0000": [ + "sram_if_0000", + "nJgqZ", + "module", + 4 + ], + "DAC_DEM_4": [ + "DAC_DEM_4", + "WqW9L", + "module", + 36 + ], + "tsdn28hpcpuhdb128x128m4mw_170a": [ + "tsdn28hpcpuhdb128x128m4mw_170a", + "rShyv", + "module", + 12 + ], + "ctrl_regfile": [ + "ctrl_regfile", + "mLA3J", + "module", + 5 + ], + "xyz_chip_top": [ + "xyz_chip_top", + "VHUBa", + "module", + 27 + ], + "param_lut_0002": [ + "param_lut_0002", + "nJN5E", + "module", + 6 + ], + "sirv_gnrl_ltch": [ + "sirv_gnrl_ltch", + "UTi0b", + "module", + 9 + ], + "PH2AMP": [ + "PH2AMP", + "iYIEc", + "module", + 17 + ], + "dacif": [ + "dacif", + "SMgga", + "module", + 28 + ], + "qbmcu_regfile_0000": [ + "qbmcu_regfile_0000", + "Hit7c", + "module", + 22 + ], + "dac_regfile": [ + "dac_regfile", + "LR0zI", + "module", + 10 + ], + "debug_top": [ + "debug_top", + "gNaPt", + "module", + 11 + ], + "mcu_regfile": [ + "mcu_regfile", + "HWLgR", + "module", + 18 + ], + "TB": [ + "TB", + "sH4Fc", + "module", + 37 + ], + "DUC_HB4": [ + "DUC_HB4", + "zwWSN", + "module", + 32 + ], + "thermo2binary_top": [ + "thermo2binary_top", + "N7Gsb", + "module", + 43 + ], + "qbmcu_busdecoder": [ + "qbmcu_busdecoder", + "jAiwN", + "module", + 19 + ], + "xy_dsp": [ + "xy_dsp", + "U33JQ", + "module", + 29 + ], + "qbmcu": [ + "qbmcu", + "xnbfb", + "module", + 20 + ], + "rst_gen_unit": [ + "rst_gen_unit", + "anuMN", + "module", + 23 + ], + "spi_slave": [ + "spi_slave", + "eAsJz", + "module", + 24 + ], + "system_regfile": [ + "system_regfile", + "W3x1b", + "module", + 25 + ], + "channel_top": [ + "channel_top", + "xFWdC", + "module", + 26 + ], + "DUC_HB3": [ + "DUC_HB3", + "Rdd8k", + "module", + 31 + ], + "DUC4": [ + "DUC4", + "cwtAY", + "module", + 33 + ], + "DAC_DEM": [ + "DAC_DEM", + "brTVz", + "module", + 34 + ], + "DAC_DEM_16": [ + "DAC_DEM_16", + "gcyA4", + "module", + 35 + ], + "DW_mult_pipe_0000_0000": [ + "DW_mult_pipe_0000_0000", + "HNRiG", + "module", + 38 + ], + "DW_mult_pipe_0000_0002": [ + "DW_mult_pipe_0000_0002", + "SiiVi", + "module", + 39 + ], + "DW01_addsub": [ + "DW01_addsub", + "KysYq", + "module", + 41 + ], + "...MASTER...": [ + "SIM", + "amcQw", + "module", + 44 + ] +} \ No newline at end of file diff --git a/tb/chip_top/simv.daidir/covg_defs b/tb/chip_top/simv.daidir/covg_defs new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/simv.daidir/debug_dump/.version b/tb/chip_top/simv.daidir/debug_dump/.version new file mode 100644 index 0000000..bb52d22 --- /dev/null +++ b/tb/chip_top/simv.daidir/debug_dump/.version @@ -0,0 +1,4 @@ +O-2018.09-SP2_Full64 +Build Date = Feb 28 2019 22:34:30 +RedHat +Compile Location: /home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/chip_top diff --git a/tb/chip_top/simv.daidir/debug_dump/AllModulesSkeletons.sdb b/tb/chip_top/simv.daidir/debug_dump/AllModulesSkeletons.sdb new file mode 100644 index 0000000..6eaaf69 Binary files /dev/null and b/tb/chip_top/simv.daidir/debug_dump/AllModulesSkeletons.sdb differ diff --git a/tb/chip_top/simv.daidir/debug_dump/HsimSigOptDb.sdb b/tb/chip_top/simv.daidir/debug_dump/HsimSigOptDb.sdb new file mode 100644 index 0000000..4509d26 Binary files /dev/null and b/tb/chip_top/simv.daidir/debug_dump/HsimSigOptDb.sdb differ diff --git a/tb/chip_top/simv.daidir/debug_dump/dumpcheck.db b/tb/chip_top/simv.daidir/debug_dump/dumpcheck.db new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/simv.daidir/debug_dump/dve_debug.db.gz b/tb/chip_top/simv.daidir/debug_dump/dve_debug.db.gz new file mode 100644 index 0000000..903bcf7 Binary files /dev/null and b/tb/chip_top/simv.daidir/debug_dump/dve_debug.db.gz differ diff --git a/tb/chip_top/simv.daidir/debug_dump/fsearch/.create_fsearch_db b/tb/chip_top/simv.daidir/debug_dump/fsearch/.create_fsearch_db new file mode 100644 index 0000000..06b7639 --- /dev/null +++ b/tb/chip_top/simv.daidir/debug_dump/fsearch/.create_fsearch_db @@ -0,0 +1,9 @@ +#!/bin/sh -h +PYTHONHOME=/home/synopsys/vcs/O-2018.09-SP2/etc/search/pyh +export PYTHONHOME +PYTHONPATH=/home/synopsys/vcs/O-2018.09-SP2/linux64/lib/pylib27 +export PYTHONPATH +LD_LIBRARY_PATH=/home/synopsys/vcs/O-2018.09-SP2/linux64/lib:/home/synopsys/vcs/O-2018.09-SP2/linux64/lib/pylib27 +export LD_LIBRARY_PATH +/home/synopsys/vcs/O-2018.09-SP2/linux64/bin/vcsfind_create_index.exe -z "/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/chip_top/simv.daidir/debug_dump/fsearch/./idents_ObLR71.xml.gz" "/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/chip_top/simv.daidir/debug_dump/fsearch/./idents_tapi.xml.gz" -o "/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/chip_top/simv.daidir/debug_dump/fsearch/fsearch.db_tmp" +\mv "/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/chip_top/simv.daidir/debug_dump/fsearch/fsearch.db_tmp" "/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/chip_top/simv.daidir/debug_dump/fsearch/fsearch.db" diff --git a/tb/chip_top/simv.daidir/debug_dump/fsearch/check_fsearch_db b/tb/chip_top/simv.daidir/debug_dump/fsearch/check_fsearch_db new file mode 100644 index 0000000..b273978 --- /dev/null +++ b/tb/chip_top/simv.daidir/debug_dump/fsearch/check_fsearch_db @@ -0,0 +1,57 @@ +#!/bin/sh -h + +FILE_PATH="/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/chip_top/simv.daidir/debug_dump/fsearch" +lockfile="${FILE_PATH}"/lock + +FSearch_lock_release() { + echo "" > /dev/null +} +create_fsearch_db_ctrl() { + if [ -s "${FILE_PATH}"/fsearch.stat ]; then + if [ -s "${FILE_PATH}"/fsearch.log ]; then + echo "ERROR building identifier database failed. Check ${FILE_PATH}/fsearch.log" + else + cat "${FILE_PATH}"/fsearch.stat + fi + return + fi + nohup "$1" > "${FILE_PATH}"/fsearch.log 2>&1 193>/dev/null & + MY_PID=`echo $!` + BUILDER="pid ${MY_PID} ${USER}@${hostname}" + echo "INFO Started building database for Identifiers, please wait ($BUILDER). Use VCS elab option '-debug_access+idents_db' to build the database earlier." + echo "INFO Still building database for Identifiers, please wait ($BUILDER). Use VCS elab option '-debug_access+idents_db' to build the database earlier." > "${FILE_PATH}"/fsearch.stat + return +} + +dir_name=`/bin/dirname "$0"` +if [ "${dir_name}" = "." ]; then + cd $dir_name + dir_name=`/bin/pwd` +fi +if [ -d "$dir_name"/../../../../../../../../../.. ]; then + cd "$dir_name"/../../../../../../../../../.. +fi + +if [ -f "/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/chip_top/simv.daidir/debug_dump/fsearch/.create_fsearch_db" ]; then + if [ ! -f "/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/chip_top/simv.daidir/debug_dump/fsearch/fsearch.db" ]; then + if [ "$#" -eq 1 ] && [ "x$1" == "x-background" ]; then + trap FSearch_lock_release EXIT + ( + flock 193 + create_fsearch_db_ctrl "/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/chip_top/simv.daidir/debug_dump/fsearch/.create_fsearch_db" + exit 193 + ) 193> "$lockfile" + rstat=$? + if [ "${rstat}"x != "193x" ]; then + exit $rstat + fi + else + "/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/chip_top/simv.daidir/debug_dump/fsearch/.create_fsearch_db" + if [ -f "/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/chip_top/simv.daidir/debug_dump/fsearch/fsearch.stat" ]; then + rm -f "/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/chip_top/simv.daidir/debug_dump/fsearch/fsearch.stat" + fi + fi + elif [ -f "/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/chip_top/simv.daidir/debug_dump/fsearch/fsearch.stat" ]; then + rm -f "/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/chip_top/simv.daidir/debug_dump/fsearch/fsearch.stat" + fi +fi diff --git a/tb/chip_top/simv.daidir/debug_dump/fsearch/fsearch.stat b/tb/chip_top/simv.daidir/debug_dump/fsearch/fsearch.stat new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/simv.daidir/debug_dump/fsearch/idents_ObLR71.xml.gz b/tb/chip_top/simv.daidir/debug_dump/fsearch/idents_ObLR71.xml.gz new file mode 100644 index 0000000..b084b06 Binary files /dev/null and b/tb/chip_top/simv.daidir/debug_dump/fsearch/idents_ObLR71.xml.gz differ diff --git a/tb/chip_top/simv.daidir/debug_dump/fsearch/idents_tapi.xml.gz b/tb/chip_top/simv.daidir/debug_dump/fsearch/idents_tapi.xml.gz new file mode 100644 index 0000000..cc12c1d Binary files /dev/null and b/tb/chip_top/simv.daidir/debug_dump/fsearch/idents_tapi.xml.gz differ diff --git a/tb/chip_top/simv.daidir/debug_dump/fsearch/idents_uXI5BR.xml.gz b/tb/chip_top/simv.daidir/debug_dump/fsearch/idents_uXI5BR.xml.gz new file mode 100644 index 0000000..3072986 Binary files /dev/null and b/tb/chip_top/simv.daidir/debug_dump/fsearch/idents_uXI5BR.xml.gz differ diff --git a/tb/chip_top/simv.daidir/debug_dump/src_files_verilog b/tb/chip_top/simv.daidir/debug_dump/src_files_verilog new file mode 100644 index 0000000..2944196 --- /dev/null +++ b/tb/chip_top/simv.daidir/debug_dump/src_files_verilog @@ -0,0 +1,99 @@ +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/awg/awg_ctrl.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/awg/awg_top.sv +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/awg/codeword_decode.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/awg/ctrl_regfile.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/awg/modout_mux.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/awg/param_lut.sv +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/clk/intpll_regfile.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/comm/sirv_gnrl_dffs.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/comm/sirv_gnrl_xchecker.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/dac_regfile/dac_regfile.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/debug/debug_sample.sv +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/debug/debug_top.sv +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/define/chip_define.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/define/chip_undefine.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/dem/DAC_DEM.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/dem/DAC_DEM_16.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/dem/DAC_DEM_4.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/memory/dpram.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/memory/dpram_model.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/memory/sram_dmux.sv +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/memory/sram_if.sv +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/memory/tsdn28hpcpuhdb128x128m4mw_170a_ffg0p99v0c.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/memory/tsdn28hpcpuhdb4096x32m4mw_170a_ffg0p99v0c.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/memory/tsdn28hpcpuhdb64x32m4mw_170a_ffg0p99v0c.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/memory/tsmc_dpram.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/modem/ampmod.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/modem/baisset.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/modem/freqmod.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/nco/coef_c.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/nco/coef_s.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/nco/cos_op.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/nco/nco.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/nco/nco_ch1.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/nco/p_nco.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/nco/p_nco_ch1.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/nco/ph2amp.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/nco/pipe_acc_48bit.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/nco/pipe_add_48bit.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/nco/sin_op.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/perips/DW03_updn_ctr.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/perips/mcu_regfile.sv +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/perips/qbmcu_busdecoder.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/qubitmcu/qbmcu.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/qubitmcu/qbmcu_datalock.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/qubitmcu/qbmcu_decode.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/qubitmcu/qbmcu_defines.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/qubitmcu/qbmcu_exu.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/qubitmcu/qbmcu_exu_alu.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/qubitmcu/qbmcu_exu_bjp.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/qubitmcu/qbmcu_exu_dpath.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/qubitmcu/qbmcu_exu_ext.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/qubitmcu/qbmcu_exu_lsuagu.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/qubitmcu/qbmcu_fsm.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/qubitmcu/qbmcu_ifu.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/qubitmcu/qbmcu_regfile.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/qubitmcu/qbmcu_undefines.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/qubitmcu/qbmcu_wbck.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/rstgen/rst_gen_unit.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/rstgen/rst_sync.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/spi/spi_bus_decoder.sv +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/spi/spi_pll.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/spi/spi_slave.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/spi/spi_sys.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/sync/sync_buf.sv +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/system_regfile/system_regfile.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/top/channel_top.sv +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/top/digital_top.sv +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/top/xyz_chip_top.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/top/z_data_mux.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/xy_dsp/dacif/dacif.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/xy_dsp/dsp_top/xy_dsp.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/xy_dsp/duc/duc4.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/xy_dsp/duc/duc_hb1_pipe_shift.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/xy_dsp/duc/duc_hb1_top.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/xy_dsp/duc/duc_hb2_pipe_shift.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/xy_dsp/duc/duc_hb2_top_s.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/xy_dsp/duc/duc_hb3_pipe_shift.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/xy_dsp/duc/duc_hb3_top_s2.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/xy_dsp/duc/duc_hb4_pipe_shift.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/xy_dsp/duc/duc_hb4_top_s3.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/xy_dsp/qam/qam_top.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/xy_dsp/qam/ssb.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/chip_top/DW01_addsub.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/chip_top/DW02_mult.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/chip_top/DW_mult_pipe.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/chip_top/TB.sv +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/chip_top/chip_define.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/chip_top/chip_undefine.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/chip_top/clk_gen.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/chip_top/qbmcu_defines.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/chip_top/qbmcu_undefines.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/chip_top/spi_if.sv +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/chip_top/thermo15_binary4.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/chip_top/thermo2binary_top.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/chip_top/thermo7_binary3.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/define/chip_define.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/define/chip_undefine.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/qubitmcu/qbmcu_defines.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/qubitmcu/qbmcu_undefines.v diff --git a/tb/chip_top/simv.daidir/debug_dump/topmodules b/tb/chip_top/simv.daidir/debug_dump/topmodules new file mode 100644 index 0000000..c9df38d --- /dev/null +++ b/tb/chip_top/simv.daidir/debug_dump/topmodules @@ -0,0 +1 @@ +®=›7²ZœMn°@ \ No newline at end of file diff --git a/tb/chip_top/simv.daidir/debug_dump/vir.sdb b/tb/chip_top/simv.daidir/debug_dump/vir.sdb new file mode 100644 index 0000000..cce7ee1 Binary files /dev/null and b/tb/chip_top/simv.daidir/debug_dump/vir.sdb differ diff --git a/tb/chip_top/simv.daidir/eblklvl.db b/tb/chip_top/simv.daidir/eblklvl.db new file mode 100644 index 0000000..23a8a8e Binary files /dev/null and b/tb/chip_top/simv.daidir/eblklvl.db differ diff --git a/tb/chip_top/simv.daidir/elabmoddb.sdb b/tb/chip_top/simv.daidir/elabmoddb.sdb new file mode 100644 index 0000000..71b572f Binary files /dev/null and b/tb/chip_top/simv.daidir/elabmoddb.sdb differ diff --git a/tb/chip_top/simv.daidir/external_functions b/tb/chip_top/simv.daidir/external_functions new file mode 100644 index 0000000..9dbd31f --- /dev/null +++ b/tb/chip_top/simv.daidir/external_functions @@ -0,0 +1,129 @@ +pli $fsdbDumpvars novas_call_fsdbDumpvars - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbDumpvarsES novas_call_fsdbDumpvarsES - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbDumpMDA novas_call_fsdbDumpMDA - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbDumpSVA novas_call_fsdbDumpSVA - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbDumpvarsByFile novas_call_fsdbDumpvarsByFile - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbSuppress novas_call_fsdbSuppress - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbDumpon novas_call_fsdbDumpon - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbDumpoff novas_call_fsdbDumpoff - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbSwitchDumpfile novas_call_fsdbSwitchDumpfile - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbDumpfile novas_call_fsdbDumpfile - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbAutoSwitchDumpfile novas_call_fsdbAutoSwitchDumpfile - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbDumpFinish novas_call_fsdbDumpFinish - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbDumpflush novas_call_fsdbDumpflush - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbLog novas_call_fsdbLog - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbAddRuntimeSignal novas_call_fsdbAddRuntimeSignal - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbDumpSC novas_call_fsdbDumpSC - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbDumpvarsToFile novas_call_fsdbDumpvarsToFile - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $sps_create_transaction_stream novas_call_sps_create_transaction_stream - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $sps_begin_transaction novas_call_sps_begin_transaction - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $sps_end_transaction novas_call_sps_end_transaction - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $sps_free_transaction novas_call_sps_free_transaction - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $sps_add_attribute novas_call_sps_add_attribute - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $sps_update_label novas_call_sps_update_label - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $sps_add_relation novas_call_sps_add_relation - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbWhatif novas_call_fsdbWhatif - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $paa_init novas_call_paa_init - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $paa_sync novas_call_paa_sync - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbDumpClassMethod novas_call_fsdbDumpClassMethod - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbSuppressClassMethod novas_call_fsdbSuppressClassMethod - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbSuppressClassProp novas_call_fsdbSuppressClassProp - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbDumpMDAByFile novas_call_fsdbDumpMDAByFile - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbTrans_create_stream_begin novas_call_fsdbEvent_create_stream_begin - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbTrans_define_attribute novas_call_fsdbEvent_add_stream_attribute - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbTrans_create_stream_end novas_call_fsdbEvent_create_stream_end - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbTrans_begin novas_call_fsdbEvent_begin - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbTrans_set_label novas_call_fsdbEvent_set_label - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbTrans_add_attribute novas_call_fsdbEvent_add_attribute - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbTrans_add_tag novas_call_fsdbEvent_add_tag - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbTrans_end novas_call_fsdbEvent_end - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbTrans_add_relation novas_call_fsdbEvent_add_relation - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbTrans_get_error_code novas_call_fsdbEvent_get_error_code - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbTrans_add_stream_attribute novas_call_fsdbTrans_add_stream_attribute - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbTrans_add_scope_attribute novas_call_fsdbTrans_add_scope_attribute - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $sps_interactive novas_call_sps_interactive - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $sps_test novas_call_sps_test - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbDumpClassObject novas_call_fsdbDumpClassObject - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbDumpClassObjectByFile novas_call_fsdbDumpClassObjectByFile - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $ridbDump novas_call_ridbDump - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $sps_flush_file novas_call_sps_flush_file - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbDumpPSL novas_call_fsdbDumpPSL - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbDumplimit novas_call_fsdbDumplimit - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbDumpvars novas_call_fsdbDumpvars - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpvarsES novas_call_fsdbDumpvarsES - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpMDA novas_call_fsdbDumpMDA - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpSVA novas_call_fsdbDumpSVA - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpvarsByFile novas_call_fsdbDumpvarsByFile - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbSuppress novas_call_fsdbSuppress - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpon novas_call_fsdbDumpon - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpoff novas_call_fsdbDumpoff - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbSwitchDumpfile novas_call_fsdbSwitchDumpfile - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpfile novas_call_fsdbDumpfile - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbAutoSwitchDumpfile novas_call_fsdbAutoSwitchDumpfile - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpFinish novas_call_fsdbDumpFinish - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpflush novas_call_fsdbDumpflush - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbLog novas_call_fsdbLog - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbAddRuntimeSignal novas_call_fsdbAddRuntimeSignal - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpSC novas_call_fsdbDumpSC - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpvarsToFile novas_call_fsdbDumpvarsToFile - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $sps_create_transaction_stream novas_call_sps_create_transaction_stream - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $sps_begin_transaction novas_call_sps_begin_transaction - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $sps_end_transaction novas_call_sps_end_transaction - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $sps_free_transaction novas_call_sps_free_transaction - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $sps_add_attribute novas_call_sps_add_attribute - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $sps_update_label novas_call_sps_update_label - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $sps_add_relation novas_call_sps_add_relation - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbWhatif novas_call_fsdbWhatif - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $paa_init novas_call_paa_init - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $paa_sync novas_call_paa_sync - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpClassMethod novas_call_fsdbDumpClassMethod - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbSuppressClassMethod novas_call_fsdbSuppressClassMethod - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbSuppressClassProp novas_call_fsdbSuppressClassProp - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpMDAByFile novas_call_fsdbDumpMDAByFile - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbTrans_create_stream_begin novas_call_fsdbEvent_create_stream_begin - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbTrans_define_attribute novas_call_fsdbEvent_add_stream_attribute - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbTrans_create_stream_end novas_call_fsdbEvent_create_stream_end - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbTrans_begin novas_call_fsdbEvent_begin - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbTrans_set_label novas_call_fsdbEvent_set_label - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbTrans_add_attribute novas_call_fsdbEvent_add_attribute - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbTrans_add_tag novas_call_fsdbEvent_add_tag - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbTrans_end novas_call_fsdbEvent_end - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbTrans_add_relation novas_call_fsdbEvent_add_relation - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbTrans_get_error_code novas_call_fsdbEvent_get_error_code - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbTrans_add_stream_attribute novas_call_fsdbTrans_add_stream_attribute - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbTrans_add_scope_attribute novas_call_fsdbTrans_add_scope_attribute - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $sps_interactive novas_call_sps_interactive - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $sps_test novas_call_sps_test - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpClassObject novas_call_fsdbDumpClassObject - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpClassObjectByFile novas_call_fsdbDumpClassObjectByFile - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $ridbDump novas_call_ridbDump - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $sps_flush_file novas_call_sps_flush_file - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpPSL novas_call_fsdbDumpPSL - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDisplay novas_call_fsdbDisplay - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumplimit novas_call_fsdbDumplimit - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpMem novas_call_fsdbDumpMem - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpMemNow novas_call_fsdbDumpMemNow - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpMemInScope novas_call_fsdbDumpMemInScope - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpMDANow novas_call_fsdbDumpMDANow - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpMDAOnChange novas_call_fsdbDumpMDAOnChange - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpMDAInScope novas_call_fsdbDumpMDAInScope - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpMemInFile novas_call_fsdbDumpMemInFile - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpPSLon novas_call_fsdbDumpPSLon - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpPSLoff novas_call_fsdbDumpPSLoff - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpSVAon novas_call_fsdbDumpSVAon - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpSVAoff novas_call_fsdbDumpSVAoff - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpStrength novas_call_fsdbDumpStrength - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpSingle novas_call_fsdbDumpSingle - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpIO novas_call_fsdbDumpIO - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpPattern novas_call_fsdbDumpPattern - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbSubstituteHier novas_call_fsdbSubstituteHier - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $dumpports DumpPortsIeeeCALL - DumpPortsMISC +pli $lsi_dumpports DumpPortsLsiCALL - DumpPortsMISC +pli $dumpportson DumpPortsOnCALL - DumpPortsMISC +pli $dumpportsoff DumpPortsOffCALL - DumpPortsMISC +pli $dumpportsflush DumpPortsFlushCALL - DumpPortsMISC +pli $simlearn simLearnCall simLearnCheck simLearnMisc +pli $dumpportsall DumpPortsAllCALL - DumpPortsMISC +pli $dumpportslimit DumpPortsLimitCALL - DumpPortsMISC +pli $countdrivers CountDriversCALL - - +pli $vcsmemprof DMMemProfCALL DMMemProfCheck DMMemProfMISC diff --git a/tb/chip_top/simv.daidir/hslevel_callgraph.sdb b/tb/chip_top/simv.daidir/hslevel_callgraph.sdb new file mode 100644 index 0000000..eec6423 Binary files /dev/null and b/tb/chip_top/simv.daidir/hslevel_callgraph.sdb differ diff --git a/tb/chip_top/simv.daidir/hslevel_level.sdb b/tb/chip_top/simv.daidir/hslevel_level.sdb new file mode 100644 index 0000000..b9d6712 Binary files /dev/null and b/tb/chip_top/simv.daidir/hslevel_level.sdb differ diff --git a/tb/chip_top/simv.daidir/hslevel_rtime_level.sdb b/tb/chip_top/simv.daidir/hslevel_rtime_level.sdb new file mode 100644 index 0000000..c329a02 Binary files /dev/null and b/tb/chip_top/simv.daidir/hslevel_rtime_level.sdb differ diff --git a/tb/chip_top/simv.daidir/hsscan_cfg.dat b/tb/chip_top/simv.daidir/hsscan_cfg.dat new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/simv.daidir/nsparam.dat b/tb/chip_top/simv.daidir/nsparam.dat new file mode 100644 index 0000000..a974554 Binary files /dev/null and b/tb/chip_top/simv.daidir/nsparam.dat differ diff --git a/tb/chip_top/simv.daidir/pcc.sdb b/tb/chip_top/simv.daidir/pcc.sdb new file mode 100644 index 0000000..9a0c55d Binary files /dev/null and b/tb/chip_top/simv.daidir/pcc.sdb differ diff --git a/tb/chip_top/simv.daidir/pcxpxmr.dat b/tb/chip_top/simv.daidir/pcxpxmr.dat new file mode 100644 index 0000000..ed00730 Binary files /dev/null and b/tb/chip_top/simv.daidir/pcxpxmr.dat differ diff --git a/tb/chip_top/simv.daidir/prof.sdb b/tb/chip_top/simv.daidir/prof.sdb new file mode 100644 index 0000000..f2fc418 Binary files /dev/null and b/tb/chip_top/simv.daidir/prof.sdb differ diff --git a/tb/chip_top/simv.daidir/rmapats.dat b/tb/chip_top/simv.daidir/rmapats.dat new file mode 100644 index 0000000..51dd887 Binary files /dev/null and b/tb/chip_top/simv.daidir/rmapats.dat differ diff --git a/tb/chip_top/simv.daidir/rmapats.so b/tb/chip_top/simv.daidir/rmapats.so new file mode 100644 index 0000000..ceb7356 Binary files /dev/null and b/tb/chip_top/simv.daidir/rmapats.so differ diff --git a/tb/chip_top/simv.daidir/saifNetInfo.db b/tb/chip_top/simv.daidir/saifNetInfo.db new file mode 100644 index 0000000..f0d367b --- /dev/null +++ b/tb/chip_top/simv.daidir/saifNetInfo.db @@ -0,0 +1,43 @@ +14 +tsmc_dpram +dpram_32X4096_generation®BWEBA +All +tsmc_dpram +dpram_32X4096_generation®BWEBB +All +tsmc_dpram +dpram_32X4096_generation®U0_CEBA +Scal +tsmc_dpram +dpram_32X4096_generation®U0_CEBB +Scal +tsmc_dpram +dpram_32X4096_generation®U0_QA +All +tsmc_dpram +dpram_32X4096_generation®U0_QB +All +tsmc_dpram +dpram_32X4096_generation®U1_CEBA +Scal +tsmc_dpram +dpram_32X4096_generation®U1_CEBB +Scal +tsmc_dpram +dpram_32X4096_generation®U1_QA +All +tsmc_dpram +dpram_32X4096_generation®U1_QB +All +tsmc_dpram +spram_32X64_generation®BWEBA +All +tsmc_dpram +spram_32X64_generation®BWEBB +All +tsmc_dpram +spram_512X128_generation®BWEBA +All +tsmc_dpram +spram_512X128_generation®BWEBB +All diff --git a/tb/chip_top/simv.daidir/simv.kdb b/tb/chip_top/simv.daidir/simv.kdb new file mode 100644 index 0000000..819493f --- /dev/null +++ b/tb/chip_top/simv.daidir/simv.kdb @@ -0,0 +1,16 @@ +rc file Version 1.0 + +[Design] +COMPILE_PATH=/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/chip_top +SystemC=FALSE +UUM=FALSE +KDB=FALSE +USE_NOVAS_HOME=FALSE +COSIM=FALSE +TOP=sirv_gnrl_dffl sirv_gnrl_ltch TB DW01_addsub +OPTION=-ssv -ssy +ELAB_OPTION=-ssv -ssy + +[Value] +WREALX=ffff534e50535f58 +WREALZ=ffff534e50535f5a diff --git a/tb/chip_top/simv.daidir/stitch_nsparam.dat b/tb/chip_top/simv.daidir/stitch_nsparam.dat new file mode 100644 index 0000000..0357d47 Binary files /dev/null and b/tb/chip_top/simv.daidir/stitch_nsparam.dat differ diff --git a/tb/chip_top/simv.daidir/tt.sdb b/tb/chip_top/simv.daidir/tt.sdb new file mode 100644 index 0000000..dada3b6 Binary files /dev/null and b/tb/chip_top/simv.daidir/tt.sdb differ diff --git a/tb/chip_top/simv.daidir/vcs_rebuild b/tb/chip_top/simv.daidir/vcs_rebuild new file mode 100644 index 0000000..68cf71e --- /dev/null +++ b/tb/chip_top/simv.daidir/vcs_rebuild @@ -0,0 +1,4 @@ +#!/bin/sh -e +# This file is automatically generated by VCS. Any changes you make +# to it will be overwritten the next time VCS is run. +vcs '-full64' '-sverilog' '+lint=TFIPC-L' '+v2k' '-debug_access+all' '+define+DUMP_FSDB' '-lca' '-q' '-timescale=1ns/1ps' '+nospecify' '-P' '/home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab' '/home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/pli.a' '-l' 'compile.log' '-f' 'files.f' 2>&1 diff --git a/tb/chip_top/simv.daidir/vcselab_master_hsim_elabout.db b/tb/chip_top/simv.daidir/vcselab_master_hsim_elabout.db new file mode 100644 index 0000000..b59ee40 --- /dev/null +++ b/tb/chip_top/simv.daidir/vcselab_master_hsim_elabout.db @@ -0,0 +1,691 @@ +hsDirType 1 +fHsimDesignHasDebugNodes 63 +fNSParam 1024 +fLargeSizeSdfTest 0 +fHsimDelayGateMbme 0 +fNoMergeDelays 0 +fHsimAllMtmPat 0 +fHsimCertRaptMode 0 +fSharedMasterElab 0 +hsimLevelizeDone 1 +fHsimCompressDiag 1 +fHsimPowerOpt 0 +fLoopReportElab 0 +fHsimRtl 0 +fHsimCbkOptVec 1 +fHsimDynamicCcnHeur 1 +fHsimPvcs 0 +fHsimPvcsCcn 0 +fHsimOldLdr 0 +fHsimSingleDB 1 +uVfsGcLimit 50 +fHsimCompatSched 0 +fHsimCompatOrder 0 +fHsimTransUsingdoMpd32 0 +fHsimDynamicElabForGates 1 +fHsimDynamicElabForVectors 0 +fHsimDynamicElabForVectorsAlways 0 +fHsimDynamicElabForVectorsMinputs 0 +fHsimDeferForceSelTillReElab 0 +fHsimModByModElab 1 +fSvNettRealResType 0 +fHsimExprID 1 +fHsimSequdpon 0 +fHsimDatapinOpt 0 +fHsimExprPrune 0 +fHsimMimoGate 0 +fHsimNewChangeCheckFrankch 1 +fHsimNoSched0Front 0 +fHsimNoSched0FrontForMd 1 +fHsimScalReg 0 +fHsimNtbVl 0 +fHsimICTimeStamp 0 +fHsimICDiag 0 +fHsimNewCSDF 1 +vcselabIncrMode 2 +fHsimMPPackDelay 0 +fHsimMultDriver 0 +fHsimPart 0 +fHsimPrlComp 0 +fHsimPartTest 0 +fHsimTestChangeCheck 0 +fHsimTestFlatNodeOrder 0 +fHsimTestNState 0 +fHsimPartDebug 0 +fHsimPartFlags 0 +fHsimOdeSched0 0 +fHsimNewRootSig 1 +fHsimDisableRootSigModeOpt 0 +fHsimTestRootSigModeOpt 0 +fHsimIncrWriteOnce 0 +fHsimUnifInterfaceFlow 1 +fHsimUnifInterfaceFlowDiag 0 +fHsimUnifInterfaceFlowXmrDiag 0 +fHsimUnifInterfaceMultiDrvChk 1 +fHsimXVirForGenerateScope 0 +fHsimCongruencyIntTestI 0 +fHsimCongruencySVA 0 +fHsimCongruencySVADbg 0 +fHsimCongruencyLatchEdgeFix 0 +fHsimCongruencyFlopEdgeFix 0 +fHsimCongruencyXprop 0 +fHsimCongruencyXpropFix 0 +fHsimCongruencyXpropDbsEdge 0 +fHsimCongruencyResetRecoveryDbs 0 +fHsimCongruencyClockControlDiag 0 +fHsimCongruencySampleUpdate 0 +fHsimCongruencyFFDbsFix 0 +fHsimCongruency 0 +fHsimCongruencySlave 0 +fHsimCongruencyCombinedLoads 0 +fHsimCongruencyFGP 0 +fHsimDeraceClockDataUdp 0 +fHsimDeraceClockDataLERUpdate 0 +fHsimCongruencyPC 0 +fHsimCongruencyPCInl 0 +fHsimCongruencyPCDbg 0 +fHsimCongruencyPCNoReuse 0 +fHsimCongruencyDumpHier 0 +fHsimCongruencyResolution 0 +fHsimCongruencyEveBus 0 +fHsimHcExpr 0 +fHsCgOptModOpt 0 +fHsCgOptSlowProp 0 +fHsimCcnOpt 1 +fHsimCcnOpt2 1 +fHsimCcnOpt3 0 +fHsimSmdMap 0 +fHsimSmdDiag 0 +fHsimSmdSimProf 0 +fHsimSgdDiag 0 +fHsimRtDiagLite 0 +fHsimRtDiagLiteCevent 100 +fHsimRtDiag 0 +fHsimSkRtDiag 0 +fHsimDDBSRtdiag 0 +fHsimDbg 0 +fHsimCompWithGates 0 +fHsimMdbDebugOpt 0 +fHsimMdbDebugOptP1 0 +fHsimMdbDebugOptP2 0 +fHsimMdbPruneOpt 1 +fHsimMdbMemOpt 0 +hsimRandValue 0 +fHsimSimMemProfile 0 +fHsimSimTimeProfile 0 +fHsimElabMemProfile 0 +fHsimElabTimeProfile 0 +fHsimElabMemNodesProfile 0 +fHsimElabMemAllNodesProfile 0 +fHsimDisableVpdGatesProfile 0 +fHsimFileProfile 0 +fHsimCountProfile 0 +fHsimXmrDefault 1 +fHsimFuseWireAndReg 0 +fHsimFuseSelfDrvLogic 0 +fHsimFuseProcess 0 +fHsimNoStitchDump 0 +fHsimAllExtXmrs 0 +fHsimAllXmrs 1 +fHsimMvsimDb 0 +fHsimTaskFuncXmrs 0 +fHsimTaskFuncXmrsDbg 0 +fHsimAllTaskFuncXmrs 0 +fHsimPageArray 16383 +fHsimPageControls 16383 +hsDfsNodePageElems 0 +hsNodePageElems 0 +hsFlatNodePageElems 0 +hsGateMapPageElems 0 +hsGateOffsetPageElems 0 +hsGateInputOffsetPageElems 0 +hsDbsOffsetPageElems 0 +hsMinPulseWidthPageElems 0 +hsNodeUpPatternPageElems 0 +hsNodeDownPatternPageElems 0 +hsNodeUpOffsetPageElems 0 +hsNodeEblkOffsetPageElems 0 +hsNodeDownOffsetPageElems 0 +hsNodeUpdateOffsetPageElems 0 +hsSdfOffsetPageElems 0 +fHsimPageAllLevelData 0 +fHsimAggrCg 0 +fHsimViWire 1 +fHsimPcCbOpt 1 +fHsimAmsTunneling 0 +fHsimAmsTunnelingDiag 0 +fHsimScUpwardXmrNoSplit 1 +fHsimOrigNdbViewOnly 0 +fHsimVcsInterface 1 +fHsimVcsInterfaceAlias 1 +fHsimSVTypesIntf 1 +fUnifiedAssertCtrlDiag 0 +fHsimEnable2StateScal 0 +fHsimDisable2StateScalIbn 0 +fHsimVcsInterfaceAliasDbg 0 +fHsimVcsInterfaceDbg 0 +fHsimVcsVirtIntfDbg 0 +fHsimVcsAllIntfVarMem 0 +fHsimCheckVIDynLoadOffsets 0 +fHsimModInline 1 +fHsimModInlineDbg 0 +fHsimPCDrvLoadDbg 0 +fHsimDrvChk 1 +fHsimRtlProcessingNeeded 0 +fHsimGrpByGrpElab 0 +fHsimGrpByGrpElabMaster 0 +fHsimNoParentSplitPC 0 +fHsimNusymMode 0 +fHsimOneIntfPart 0 +fHsimCompressInSingleDb 2 +fHsimCompressFlatDb 0 +fHsimNoTime0Sched 1 +fHsimMdbVectorizeInstances 0 +fHsimMdbSplitGates 0 +fHsimDeleteInstances 0 +fHsimUserDeleteInstances 0 +fHsimDeleteGdb 0 +fHsimDeleteInstancesMdb 0 +fHsimShortInstMap 0 +fHsimMdbVectorizationDump 0 +fHsimScanVectorize 0 +fHsimParallelScanVectorize 0 +noInstsInVectorization 0 +cHsimNonReplicatedInstances 0 +fHsimScanRaptor 0 +fHsimConfigFileCount 0 +fHsimVectorConstProp 0 +fHsimPromoteParam 0 +fHsimNoVecInRaptor 0 +fRaptorDumpVal 0 +fRaptorVecNodes 0 +fRaptorVecNodes2 0 +fRaptorNonVecNodes 0 +fRaptorBdrNodes 0 +fRaptorVecGates 0 +fRaptorNonVecGates 0 +fRaptorTotalNodesBeforeVect 0 +fRaptorTotalGatesBeforeVect 0 +fHsimCountRaptorBits 0 +fHsimNewEvcd 1 +fHsimNewEvcdMX 0 +fHsimNewEvcdVecRoot 1 +fHsimNewEvcdForce 1 +fHsimNewEvcdTest 0 +fHsimNewEvcdObnDrv 1 +fHsimNewEvcdW 1 +fHsimNewEvcdWTest 0 +fHsimEvcdDbgFlags 0 +fHsimNewEvcdMultiDrvFmt 1 +fHsimDumpOffsetData 1 +fFlopGlitchDetect 0 +fHsimClkGlitch 0 +fHsimGlitchDumpOnce 0 +fHsimDynamicElab 1 +fHsimCgVectors2Debug 0 +fHsimOdeDynElab 0 +fHsimOdeDynElabDiag 0 +fHsimOdeSeqUdp 0 +fHsimOdeSeqUdpXEdge 0 +fHsimOdeSeqUdpDbg 0 +fHsimOdeRmvSched0 0 +fHsimAllLevelSame 0 +fHsimRtlDbsList 0 +fHsimPePort 0 +fHsimPeXmr 0 +fHsimPePortDiag 0 +fHsimUdpDbs 0 +fHsimRemoveDbgCaps 0 +fFsdbGateOnepassTraverse 0 +fHsimAllowVecGateInVpd 1 +fHsimAllowAllVecGateInVpd 0 +fHsimAllowUdpInVpd 1 +fHsimAllowAlwaysCombInVpd 1 +fHsimAllowAlwaysCombCmpDvcSimv 0 +fHsimAllowAlwaysCombDbg 0 +fHsimMakeAllP2SPrimary 0 +fHsimMakeAllSeqPrimary 0 +fHsimNoCcnDump 0 +fHsimFsdbProfDiag 0 +fVpdSeqGate 0 +fVpdUseMaxBCode 0 +fVpdHsIntVecGate 0 +fVpdHsCmplxVecGate 0 +fVpdHsVecGateDiags 0 +fSeqGateCodePatch 0 +fVpdLongFaninOpt 0 +fVpdSeqLongFaninOpt 0 +fVpdNoLoopDetect 0 +fVpdNoSeqLoopDetect 0 +fVpdOptAllowConstDriver 0 +fVpdAllowCellReconstruction 0 +fVpdRtlForSharedLib 0 +fHsimVpdOptGate 1 +fHsimVpdOptDelay 0 +fHsimVpdOptMPDelay 0 +fHsimCbkOptDiag 0 +fHsimSK 0 +fHsimSharedKernel 1 +fHsimOnepass 0 +fHsimStitchNew 0 +fHsimParallelLevelize 0 +fHsimParallelLevelizeDbg 0 +fHsimSeqUdpDbsByteArray 0 +fHsimCoLocate 0 +fHsimSeqUdpEblkOpt 0 +fHsimSeqUdpEblkOptDiag 0 +fHsimGateInputAndDbsOffsetsOpt 1 +fHsimUdpDynElab 0 +fHsimCompressData 4 +fHsimIgnoreZForDfuse 1 +fHsimIgnoreDifferentCaps 0 +fHandleGlitchQC 1 +fGlitchDetectForAllRtlLoads 0 +fHsimFuseConstDriversOpt 1 +fHsimMdSchedTr 0 +fHsimIgnoreReElab 0 +fHsimFuseMultiDrivers 0 +fHsimNoSched0Reg 0 +fHsimAmsFusionEnabled 0 +fHsimRtlDbs 0 +fHsimWakeupId 0 +fHsimPassiveIbn 0 +fHsimBcOpt 1 +fHsimCertitude 0 +fHsimCertRapAutoTest 0 +fHsimRaceDetect 0 +fCheckTcCond 0 +fHsimScanOptRelaxDbg 0 +fHsimScanOptRelaxDbgDynamic 0 +fHsimScanOptRelaxDbgDynamicPli 0 +fHsimScanOptRelaxDbgDiag 0 +fHsimScanOptRelaxDbgDiagHi 0 +fHsimScanOptNoErrorOnPliAccess 0 +fHsimScanOptTiming 0 +fRelaxIbnSchedCheck 0 +fHsimScanOptNoDumpCombo 0 +fHsimScanOptPrintSwitchState 0 +fHsimScanOptSelectiveSwitchOn 0 +fHsimScanOptSingleSEPliOpt 1 +fHsimScanOptDesignHasDebugAccessOnly 0 +fHsimScanOptPrintPcode 0 +fHsimScanDbgPerf 0 +fHsimNoStitchMap 0 +fHsimUnifiedModName 0 +fHsimCbkMemOptDebug 0 +fHsimMasterModuleOnly 0 +fHsimMdbOptimizeSelects 0 +fHsimMdbScalarizePorts 0 +fHsimMdbOptimizeSelectsHeuristic 1 +fHsimMdb1006Partition 0 +fHsimVectorPgate 0 +fHsimNoHs 0 +fHsimXmrPartition 0 +fHsimNewPartition 0 +fHsimElabPart 0 +fHsimElabPartThreshHoldDesign 1 +fHsimPMdb 0 +fHsimParitionCellInstNum 1000 +fHsimParitionCellNodeNum 1000 +fHsimParitionCellXMRNum 1000 +fHsimNewPartCutSingleInstLimit 268435455 +fHsimElabModDistNum 0 +fHsimElabPartThreshHoldModule 3000000 +fHsimPCPortPartition 0 +fHsimPortPartition 0 +fHsimDumpMdb 0 +fHsimElabDiag 0 +fHsimSimpCollect 0 +fHsimPcodeDiag 0 +fHsimFastelab 0 +fHsimMacroOpt 0 +fHsimSkipOpt 0 +fHsimSkipOptFanoutlimit 0 +fHsimSkipOptRootlimit 0 +fHsimFuseDelayChains 0 +fFusempchainsFanoutlimit 0 +fFusempchainsDiagCount 0 +fHsimCgVectorGates 0 +fHsimCgVectorGates1 0 +fHsimCgVectorGates2 0 +fHsimCgVectorGatesNoReElab 0 +fHsimCgScalarGates 0 +fHsimCgScalarGatesExpr 0 +fHsimCgScalarGatesLut 0 +fHsimCgRtl 1 +fHsimCgRtlFilter 0 +fHsimCgRtlDebug 0 +fHsimCgRtlSize 15 +fHsimNewCgRt 0 +fHsimNewCgMPRt 0 +fHsimNewCgMPRetain 0 +fHsimCgRtlInfra 1 +fHsimGlueOpt 0 +fHsimPGatePatchOpt 0 +fHsimCgNoPic 0 +fHsimElabModCg 0 +fPossibleNullChecks 0 +fHsimProcessNoSplit 1 +fHsimMdbOptInSchedDelta 0 +fScaleTimeValue 0 +fDebugTimeScale 0 +fPartCompSDF 0 +fHsimNbaGate 1 +fDumpDtviInfoInSC 0 +fDumpSDFBasedMod 1 +fHsimSdfIC 0 +fOptimisticNtcSolver 0 +fHsimAllMtm 0 +fHsimAllMtmPat 0 +fHsimSdgOptEnable 0 +fHsimSVTypesRefPorts 0 +fHsimGrpByGrpElabIncr 0 +fHsimMarkRefereeInVcsElab 0 +fHsimStreamOpFix 1 +fHsimInterface 0 +fHsimMxWrapOpt 0 +fHsimMxTopBdryOpt 0 +fHsimClasses 0 +fHsimAggressiveDce 0 +fHsimDceDebug 1 +fHsimDceDebugUseHeuristics 1 +fHsimMdbNewDebugOpt 0 +fHsimMdbNewDebugOptExitOnError 1 +fHsimNewDebugOptMemDiag 0 +hsGlobalVerboseLevel 0 +fHsimMdbVectorConstProp 1 +fHsimEnableSeqUdpWrite 1 +fHsimDumpMDBOnlyForSeqUdp 0 +fHsimInitRegRandom 0 +fHsimInitRegRandomVcs 1 +fEnableNewFinalStrHash 0 +fEnableNewAssert 1 +fRunDbgDmma 0 +fAssrtCtrlSigChk 1 +fCheckSigValidity 0 +fUniqPriToAstRewrite 0 +fUniqPriToAstCtrl 0 +fAssertcontrolUniqPriNewImpl 0 +fRTLoopDectEna 0 +fCmplLoopDectEna 0 +fHsimMopFlow 1 +fUCaseLabelCtrl 0 +fUniSolRtSvaEna 1 +fUniSolSvaEna 1 +fXpropRtCtrlCallerOnly 0 +fHsimRaptorPart 0 +fHsimEnableDbsMemOpt 1 +fHsimDebugDbsMemOpt 0 +fHsimRenPart 0 +fHsimShortElabInsts 0 +fHsimXmrAllWires 0 +fHsimXmrDiag 0 +fHsimXmrPort 0 +fHsimFalcon 1 +fHsimGenForProfile 0 +fCompressSDF 0 +fDlpSvtbExclElab 0 +fHsimGates1209 0 +fHsimCgRtlNoShareSmd 0 +fHsimGenForErSum 0 +fVpdOpt 1 +fHsimMdbCell 0 +fHsimCellDebug 0 +fHsimNoPeekInMdbCell 0 +igetOpcodeSmdPtrLayoutId -1 +igetFieldSmdPtr -1 +fDebugDump 1 +fHsimOrigNodeNames 0 +fHsimCgVectors2VOnly 0 +fHsimMdbDeltaGate 0 +fHsimMdbDeltaGateAggr 0 +fHsimMdbVecDeltaGate 1 +fHsimVpdOptVfsDB 1 +fHsimMdbPruneVpdGates 1 +fHsimPcPe 0 +fHsimVpdGateOnlyFlag 1 +fHsimMxConnFrc 0 +fHsimNewForceCbkVec 0 +fHsimNewForceCbkVecDiag 0 +fHsimMdbReplaceVpdHighConn 1 +fHsimVpdOptSVTypes 1 +fHsHasPeUpXmr 0 +fHsimCompactVpdFn 1 +fHsimPIP 0 +fHsimRTLoopDectOrgName 0 +fHsimVpdOptPC 0 +fHsimFusePeXmrFo 0 +fHsimXmrSched 0 +fHsimNoMdg 0 +fHsimVectorGates 0 +fHsimRtlLite 0 +fHsimMdbcgLut 0 +fHsimMdbcgSelective 0 +fHsimVcselabGates 0 +fHsimMdbcgLevelize 0 +fHsimParGateEvalMode 0 +fHsimDFuseVectors 0 +fHsimDFuseZero 0 +fHsimDFuseOpt 1 +fHsimPruneOpt 0 +fHsimSeqUdpPruneWithConstInputs 0 +fHsimSafeDFuse 0 +fHsimVpdOptExpVec 0 +fHsimVpdOptSelGate 1 +fHsimVpdOptSkipFuncPorts 0 +fHsimVpdOptAlways 1 +fHsimVpdOptMdbCell 0 +fHsimVpdOptPartialMdb 1 +fHsimVpdOptPartitionGate 1 +fHsimVpdOptXmr 1 +fHsimVpdOptMoreLevels 1 +fHsimVpdHilRtl 0 +fHsimSWave 0 +fHsimNoSched0InCell 1 +fHsimPartialMdb 0 +hsimPdbLargeOffsetThreshold 1048576 +fHsimFlatCell 0 +fHsimFlatCellLimit 0 +fHsimRegBank 0 +fHsimHmetisMaxPartSize 0 +fHsimHmetisGateWt 0 +fHsimHmetisUbFactor 0 +fHsimHmetis 0 +fHsimHmetisDiag 0 +fHsimRenumGatesForMdbCell 0 +fHsimHmetisMinPart 0 +fHsim2stCell 0 +fHsim2stCellMinSize 0 +fHsimMdbcgDebug 0 +fHsimMdbcgDebugLite 0 +fHsimMdbcgDistrib 0 +fHsimMdbcgSepmem 1 +fHsimMdbcgObjDiag 0 +fHsimMdbcg2stDiag 0 +fHsimMdbcgRttrace 0 +fHsimMdbVectorGateGroup 1 +fHsimMdbProcDfuse 1 +fHsimMdbHilPrune 0 +fHsCgOpt 1 +fHsCgOptUdp 1 +fHsCgOptRtl 1 +fHsCgOptDiag 0 +fHsCgOptAggr 0 +fHsCgOptNoZCheck 0 +fHsCgOptEnableZSupport 0 +fHsCgOpt4StateInfra 0 +fHsCgOptDce 0 +fHsCgOptUdpChkDataForWakeup 1 +fHsCgOptXprop 0 +fHsimMdbcgDiag 0 +fHsCgMaxInputs 6 +fHsCgOptFwdPass 1 +fHsimHpnodes 0 +fLightDump 0 +fHDLCosim 0 +fHDLCosimDebug 0 +fHDLCosimTimeCoupled 0 +fHDLCosimTimeCoupledPorts 0 +HDLCosimMaxDataPerDpi 1 +HDLCosimMaxCallsPerDpi 2147483647 +fHDLCosimCompileDUT 0 +fHDLCosimCustomCompile 0 +fHDLCosimBoundaryAnalysis 0 +fVpdBeforeScan 1 +fHsCgOptMiSched0 0 +fgcAddSched0 0 +fParamClassOptRtDiag 0 +fHsRegress 0 +fHsBenchmark 0 +fHsimCgScalarVerilogForce 1 +fVcsElabToRoot 1 +fHilIbnObnCallByName 0 +fHsimMdbcgCellPartition 0 +fHsimCompressVpdSig 0 +fHsimLowPowerOpt 0 +fHsimUdpOpt 1 +fHsVecOneld 0 +fNativeVpdDebug 0 +fNewDtviFuse 0 +fHsimVcsGenTLS 1 +fAssertSuccDebugLevelDump 0 +fHsimMinputsChangeCheck 0 +fHsimClkLayout 0 +fHsimIslandLayout 0 +fHsimConfigSched0 0 +fHsimSelectFuseAfterDfuse 0 +fHsimFoldedCell 0 +fHsimSWaveEmul 0 +fHsimSWaveDumpMDB 0 +fHsimSWaveDumpFlatData 0 +fHsimRenumberAlias 0 +fHsimAliasRenumbered 0 +fHilCgMode 115 +fHsimUnionOpt 0 +fHsimFuseSGDBoundaryNodes 0 +fHsimRemoveCapsVec 0 +fHsimCertRaptScal 0 +fHsimCertRaptMdbClock 0 +fHsCgOptMux 0 +fHsCgOptFrc 0 +fHsCgOpt30 0 +fHsLpNoCapsOpt 0 +fHsCgOpt4State 1 +fSkipStrChangeOnDelay 1 +fHsimTcheckOpt 0 +fHsCgOptMuxMClk 0 +fHsCgOptMuxFrc 0 +fHsCgOptNoPcb 0 +fHsCgOptMin1 0 +fHsCgOptUdpChk 0 +fHsChkXForSlowSigProp 1 +fHsimVcsParallelDbg 0 +fHsimVcsParallelStrategy 0 +fHsimVcsParallelOpt 0 +fHsimVcsParallelSubLevel 4 +fHsimParallelEblk 0 +fHsimByteCodeParts 1 +fFgpNovlInComp 0 +fFutEventPRL 0 +fFgpNbaDelay 0 +fHsimDbsFlagsByteArray 0 +fHsimDbsFlagsByteArrayTC 0 +fHsimDbsFlagsThreadArray 0 +fHsimGateEdgeEventSched 0 +fHsimEgschedDynelab 0 +fHsimUdpClkDynelab 0 +fUdpLayoutOnClk 0 +fHsimDiagClk 1 +fDbsPreCheck 0 +fHsimSched0Analysis 0 +fHsimMultiDriverSched0 0 +fHsimLargeIbnSched 0 +fFgpHierarchical 0 +fFgpHierAllElabModAsRoot 0 +fFgpHierPCElabModAsRoot 0 +fFgpAdjustDataLevelOfLatch 1 +fHsimUdpXedgeEval 0 +fFgpRaceCheck 0 +fFgpUnifyClk 0 +fFgpSmallClkTree 0 +fFgpSmallRtlClkTree 4 +fFgpNoRtlUnlink 0 +fFgpNoRtlAuxLevel 0 +fFgpNumPartitions 8 +fFgpMultiSocketCompile 0 +fFgpDataDepOn 0 +fFgpDDIgnore 0 +fFgpTbCbOn 0 +fFgpTbEvOn 1 +fFgpTbNoVSA 0 +fFgpTbEvXmr 0 +fFgpTbEvCgCall 1 +fFgpDisabledLevel 512 +fFgpSched0User 0 +fFgpNoSdDelayedNbas 1 +fFgpTimingFlags 0 +fFgpSched0Level 0 +fHsimFgpMultiClock 0 +fFgpScanOptFix 0 +fFgpSched0UdpData 0 +fFgpLoadBalance0CompileTime 1 +fFgpDepositDiag 0 +fFgpEvtDiag.diagOn 0 +fFgpEvtDiag.printAllNodes 0 +fFgpMangleDiagLog 0 +fFgpMultiExclDiag 0 +fFgpSingleExclReason 0 +fHsDoFaninFanoutSanity 0 +fHsFgpNonDbsOva 1 +fFgpParallelTask 1 +fFgpIbnSched 0 +fFgpIbnSchedOpt 0 +fFgpIbnSchedThreshold 0 +fFgpIbnSchedDyn 0 +fFgpMpStateByte 0 +fFgpTcStateByte 0 +fHsimVirtIntfDynLoadSched 0 +fFgpNoRtimeFgp 0 +fHsFgpGlSched0 0 +fFgpExclReason 0 +fHsimIslandByIslandElab 0 +fHsimIslandByIslandFlat 151652416 +fHsimIslandByIslandFlat1 4 +fHsimVpdIBIF 0 +fHsimXmrIBIF 0 +fHsimReportTime 0 +fHsimElabJ 0 +hf_fHsimElabJ 0 +fHsimElabJOpt 0 +fHsimSchedMinput 0 +fHsimSchedSeqPrim 0 +fHsimSchedSelectFanout 0 +fHsimSchedSelectFanoutDebug 0 +fSpecifyInDesign 0 +fFgpDynamicReadOn 0 +fHsCgOptAllUc 0 +fHsimXmrRepl 0 +fZoix 0 +fHsimDfuseNewOpt 0 +fHsimBfuseNewOpt 0 +fFgpXmrSched 0 +fHsimClearClkCaps 0 +fHsimDiagClkConfig 0 +fHsimDiagClkConfigDebug 0 +fHsimDiagClkConfigDumpAll 0 +fHsDiagClkConfigPara 0 +fHsimDiagClkConfigAn 0 +fHsimCanDumpClkConfig 0 +fFgpInitRout 0 +fFgpIgnoreExclSD 0 +fHsCgOptNoClockFusing 0 +fHsClkWheelLimit 50000 +fHsimPCSharedLibSpecified 0 +fHsFgpSchedCgUcLoads 1 +fHsCgOptNewSelCheck 1 +fFgpReportUnsafeFuncs 0 +fHsCgOptUncPrlThreshold 4 +fHsSVNettypePerfOpt 0 +fHsimLowPowerRetAnalysisInChild 0 +fRetainWithDelayedSig 0 +fHsimChargeDecay 0 diff --git a/tb/chip_top/simv.daidir/vcselab_master_hsim_virtintf_info.dat b/tb/chip_top/simv.daidir/vcselab_master_hsim_virtintf_info.dat new file mode 100644 index 0000000..d6baec1 Binary files /dev/null and b/tb/chip_top/simv.daidir/vcselab_master_hsim_virtintf_info.dat differ diff --git a/tb/chip_top/simv.daidir/vcselab_misc_hil_stmts.db b/tb/chip_top/simv.daidir/vcselab_misc_hil_stmts.db new file mode 100644 index 0000000..4e9ac7b Binary files /dev/null and b/tb/chip_top/simv.daidir/vcselab_misc_hil_stmts.db differ diff --git a/tb/chip_top/simv.daidir/vcselab_misc_hsdef.db b/tb/chip_top/simv.daidir/vcselab_misc_hsdef.db new file mode 100644 index 0000000..aba38dc Binary files /dev/null and b/tb/chip_top/simv.daidir/vcselab_misc_hsdef.db differ diff --git a/tb/chip_top/simv.daidir/vcselab_misc_hsim_elab.db b/tb/chip_top/simv.daidir/vcselab_misc_hsim_elab.db new file mode 100644 index 0000000..8357400 --- /dev/null +++ b/tb/chip_top/simv.daidir/vcselab_misc_hsim_elab.db @@ -0,0 +1,1217 @@ +psSimBaseName simv +psLogFileName compile.log +pDaiDir /home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/chip_top/simv.daidir +destPath csrc/ +fSharedMaster 0 +fHsimPCSharedLibSpecified 0 +hsMainFileCount 0 +hsMainFileName dummy +hsAuxFileName dummy +hsimDlpPartitionFilename 0 +partitionName 6 MASTER +hsimInitRegValue 3 +fNSParam 1024 +hsim_noschedinl 0 +hsim_hdbs 4096 +eval_order_seq 0 +simorder_light 0 +partialelab 0 +hsim_csdf -2147483648 +fHsimRuntimeElabSdf 0 +fNtcNewSolver 0 +fHsimSdfFileOpt 0 +fHsimTransUsingdoMpd32 0 +hsDirType 1 +fHsimClasses 0 +fHsimPulseMPDelay 1 +fHsimMvsimDb 0 +fHsimMvsimDebug 0 +fHsimAllXmrs 1 +fHsimTaskFuncXmrs 0 +fHsimTaskFuncXmrsDbg 0 +fHsimAllTaskFuncXmrs 0 +fHsimDoXmrProcessing 1 +fNoMergeDelays 0 +uGlblTimeUnit 4 +fHsimAllMtm 0 +fSimprofileNew 0 +fHsimVhVlOpt 0 +fHsimMdbVhVlInputFuseOpt 0 +fHsimMdbVhVlInoutFuseOpt 0 +fHsimMdbVhVlCcnOpt 0 +fHsimVlVhOpt 0 +fHsimVlVhVlOpt 0 +fHsimVlVhBfuseOpt 0 +xpropMergeMode 0 +xpropUnifiedInferenceMode 0 +xpropOverride 0 +isXpropConfigEnabled 0 +fHsimVectorConst 0 +fHsimAllMtmPat 0 +fHsimCertRaptMode 0 +fNewCBSemantics 1 +fSchedAtEnd 0 +fSpecifyInDesign 0 +fHsimDumpFlatData 1 +fHsimCompressDiag 1 +fHsimPowerOpt 0 +fLoopReportElab 0 +fHsimRtl 0 +fHsimCbkOptVec 1 +fHsimDynamicCcnHeur 1 +fHsimPvcs 0 +fHsimPvcsCcn 0 +fHsimOldLdr 0 +fHsimSingleDB 1 +uVfsGcLimit 50 +fHsimCompatSched 0 +fHsimCompatOrder 0 +fHsimDynamicElabForGates 1 +fHsimDynamicElabForVectors 0 +fHsimDynamicElabForVectorsAlways 0 +fHsimDynamicElabForVectorsMinputs 0 +fHsimDeferForceSelTillReElab 0 +fHsimModByModElab 1 +fSvNettRealResType 0 +fHsimExprID 1 +fHsimSequdpon 0 +fHsimDatapinOpt 0 +fHsimExprPrune 0 +fHsimMimoGate 0 +fHsimNewChangeCheckFrankch 1 +fHsimNoSched0Front 0 +fHsimNoSched0FrontForMd 1 +fHsimScalReg 0 +fHsimNtbVl 0 +fHsimICTimeStamp 0 +fHsimICDiag 0 +fHsimNewCSDF 1 +vcselabIncrMode 2 +fHsimMPPackDelay 0 +fHsimMultDriver 0 +fHsimPart 0 +fHsimPrlComp 0 +fHsimPartTest 0 +fHsimTestChangeCheck 0 +fHsimTestFlatNodeOrder 0 +fHsimTestNState 0 +fHsimPartDebug 0 +fHsimPartFlags 0 +fHsimOdeSched0 0 +fHsimNewRootSig 1 +fHsimDisableRootSigModeOpt 0 +fHsimTestRootSigModeOpt 0 +fHsimIncrWriteOnce 0 +fHsimUnifInterfaceStrId 1 +fHsimUnifInterfaceFlow 1 +fHsimUnifInterfaceFlowDiag 0 +fHsimUnifInterfaceFlowXmrDiag 0 +fHsimUnifInterfaceMultiDrvChk 1 +fHsimXVirForGenerateScope 0 +fHsimCongruencyIntTestI 0 +fHsimCongruencySVA 0 +fHsimCongruencySVADbg 0 +fHsimCongruencyLatchEdgeFix 0 +fHsimCongruencyFlopEdgeFix 0 +fHsimCongruencyXprop 0 +fHsimCongruencyXpropFix 0 +fHsimCongruencyXpropDbsEdge 0 +fHsimCongruencyResetRecoveryDbs 0 +fHsimCongruencyClockControlDiag 0 +fHsimCongruencySampleUpdate 0 +fHsimCongruencyFFDbsFix 0 +fHsimCongruency 0 +fHsimCongruencySlave 0 +fHsimCongruencyCombinedLoads 0 +fHsimCongruencyFGP 0 +fHsimDeraceClockDataUdp 0 +fHsimDeraceClockDataLERUpdate 0 +fHsimCongruencyPC 0 +fHsimCongruencyPCInl 0 +fHsimCongruencyPCDbg 0 +fHsimCongruencyPCNoReuse 0 +fHsimCongruencyDumpHier 0 +fHsimCongruencyResolution 0 +fHsimCongruencyEveBus 0 +fHsimHcExpr 0 +fHsCgOptModOpt 0 +fHsCgOptSlowProp 0 +fHsimCcnOpt 1 +fHsimCcnOpt2 1 +fHsimCcnOpt3 0 +fHsimSmdMap 0 +fHsimSmdDiag 0 +fHsimSmdSimProf 0 +fHsimSgdDiag 0 +fHsimRtDiagLite 0 +fHsimRtDiagLiteCevent 100 +fHsimRtDiag 0 +fHsimSkRtDiag 0 +fHsimDDBSRtdiag 0 +fHsimDbg 0 +fHsimCompWithGates 0 +fHsimMdbDebugOpt 0 +fHsimMdbDebugOptP1 0 +fHsimMdbDebugOptP2 0 +fHsimMdbPruneOpt 1 +fHsimMdbMemOpt 0 +hsimRandValue 0 +fHsimSimMemProfile 0 +fHsimSimTimeProfile 0 +fHsimElabMemProfile 0 +fHsimElabTimeProfile 0 +fHsimElabMemNodesProfile 0 +fHsimElabMemAllNodesProfile 0 +fHsimDisableVpdGatesProfile 0 +fHsimFileProfile 0 +fHsimCountProfile 0 +fHsimXmrDefault 1 +fHsimFuseWireAndReg 0 +fHsimFuseSelfDrvLogic 0 +fHsimFuseProcess 0 +fHsimNoStitchDump 0 +fHsimAllExtXmrs 0 +fHsimAllExtXmrsDiag 0 +fHsimAllExtXmrsAllowClkFusing 0 +fHsimPageArray 16383 +fHsimPageControls 16383 +hsDfsNodePageElems 0 +hsNodePageElems 0 +hsFlatNodePageElems 0 +hsGateMapPageElems 0 +hsGateOffsetPageElems 0 +hsGateInputOffsetPageElems 0 +hsDbsOffsetPageElems 0 +hsMinPulseWidthPageElems 0 +hsNodeUpPatternPageElems 0 +hsNodeDownPatternPageElems 0 +hsNodeUpOffsetPageElems 0 +hsNodeEblkOffsetPageElems 0 +hsNodeDownOffsetPageElems 0 +hsNodeUpdateOffsetPageElems 0 +hsSdfOffsetPageElems 0 +fHsimPageAllLevelData 0 +fHsimAggrCg 0 +fHsimViWire 1 +fHsimPcCbOpt 1 +fHsimAmsTunneling 0 +fHsimAmsTunnelingDiag 0 +fHsimAmsNewDrs 0 +fHsimScUpwardXmrNoSplit 1 +fHsimOrigNdbViewOnly 0 +fHsimVcsInterface 1 +fHsimVcsInterfaceAlias 1 +fHsimSVTypesIntf 1 +fUnifiedAssertCtrlDiag 0 +fHsimEnable2StateScal 0 +fHsimDisable2StateScalIbn 0 +fHsimVcsInterfaceAliasDbg 0 +fHsimVcsInterfaceDbg 0 +fHsimVcsVirtIntfDbg 0 +fHsimVcsAllIntfVarMem 0 +fHsimCheckVIDynLoadOffsets 0 +fHsimModInline 1 +fHsimModInlineDbg 0 +fHsimPCDrvLoadDbg 0 +fHsimDrvChk 1 +fHsimRtlProcessingNeeded 0 +fHsimGrpByGrpElab 0 +fHsimGrpByGrpElabMaster 0 +fHsimNoParentSplitPC 0 +fHsimNusymMode 0 +fHsimOneIntfPart 0 +fHsimCompressInSingleDb 2 +fHsimCompressFlatDb 0 +fHsimNoTime0Sched 1 +fHsimMdbVectorizeInstances 0 +fHsimMdbSplitGates 0 +fHsimDeleteInstances 0 +fHsimUserDeleteInstances 0 +fHsimDeleteGdb 0 +fHsimDeleteInstancesMdb 0 +fHsimShortInstMap 0 +fHsimMdbVectorizationDump 0 +fHsimScanVectorize 0 +fHsimParallelScanVectorize 0 +noInstsInVectorization 0 +cHsimNonReplicatedInstances 0 +fHsimScanRaptor 0 +fHsimConfigFileCount 0 +fHsimVectorConstProp 0 +fHsimPromoteParam 0 +fHsimNoVecInRaptor 0 +fRaptorDumpVal 0 +fRaptorVecNodes 0 +fRaptorVecNodes2 0 +fRaptorNonVecNodes 0 +fRaptorBdrNodes 0 +fRaptorVecGates 0 +fRaptorNonVecGates 0 +fRaptorTotalNodesBeforeVect 0 +fRaptorTotalGatesBeforeVect 0 +fHsimCountRaptorBits 0 +fHsimNewEvcd 1 +fHsimNewEvcdMX 0 +fHsimNewEvcdVecRoot 1 +fHsimNewEvcdForce 1 +fHsimNewEvcdTest 0 +fHsimNewEvcdObnDrv 1 +fHsimNewEvcdW 1 +fHsimNewEvcdWTest 0 +fHsimEvcdDbgFlags 0 +fHsimNewEvcdMultiDrvFmt 1 +fHsimDumpElabData 1 +fHsimNoDeposit 0 +fHsimDumpOffsetData 1 +fNoOfsOpt 0 +fFlopGlitchDetect 0 +fHsimClkGlitch 0 +fHsimGlitchDumpOnce 0 +fHsimDynamicElab 1 +fHsimDynamicElabDiag 0 +fHsimPrintPats 1 +fHsimInterpreted 0 +fHsimAggressiveCodegenForDelays 1 +fHsimAggressiveCgNtcDelays 1 +fHsimCgDelaysDiag 0 +fHsimCodegenForVectors 1 +fHsimCgVectors2E 1 +fHsimCgVectors2W 1 +fHsimCgVectors2Cbk 1 +fHsimCgVectors2Force 0 +fHsimCgVectors2Debug 0 +fHsimCgVectors2Diag 0 +fHsimHdlForceInfoDiag 0 +fHsimHdlForceInfo 0 +fHsimCodegenForTcheck 1 +fHsimUdpsched 0 +fHsimUdpTetramax 0 +fHsimUdpDelta 0 +fHsimMasterNodesOpt 0 +fHsimTransOpt 1 +fHsimNoPortOBN 0 +fHsimGateGroup 0 +fHsimOldXmr 0 +fHsimConst 1 +fHsimOptimizeSeqUdp 1 +fHsimOptimizeNotifier 0 +fHsimPrintUdpTable 0 +fHsimConstDelay 0 +fHsimConstForce 0 +fHsimCcnOpt4 0 +fHsimCcnOptDiag 0 +fHsimCcn 1 +fHsimDynamicCcn 0 +fHsimTestBoundaryConditions1 0 +fHsimTestBoundaryConditions2 0 +fHsimTestBoundaryConditions3 0 +fHsimTestElabNodeLimit 0 +fHsimInsertSched0ForLhsSelects 1 +fHsimVectors 1 +fHsimOde 0 +fHsimOdeDynElab 0 +fHsimOdeDynElabDiag 0 +fHsimOdeUdp 0 +fHsimOdeSeqUdp 0 +fHsimOdeSeqUdpXEdge 0 +fHsimOdeSeqUdpDbg 0 +fHsimOdeRmvSched0 0 +fHsimOde4State 0 +fHsimOdeDiag 0 +fHsimOdeWithVecNew 0 +fHsimOdeAcceptDeadGates 0 +fHsimOdeAcceptValue4Loads 0 +fHsimOdeAmdSRLatch 0 +fHsimRmvSched0OnDataOfFlop 0 +fHsimRmvSched0OnMpd 0 +fHsimAllLevelSame 0 +fHsimDbsList 0 +fHsimRtlDbsList 0 +fHsimPePort 0 +fHsimPeXmr 0 +fHsimPePortDiag 0 +fHsimUdpDbs 0 +fHsimCodeShare 0 +fHsimRemoveDbgCaps 0 +fFsdbGateOnepassTraverse 0 +fHsimAllowVecGateInVpd 1 +fHsimAllowAllVecGateInVpd 0 +fHsimAllowUdpInVpd 1 +fHsimAllowAlwaysCombInVpd 1 +fHsimAllowAlwaysCombCmpDvcSimv 0 +fHsimAllowAlwaysCombDbg 0 +fHsimMakeAllP2SPrimary 0 +fHsimMakeAllSeqPrimary 0 +fHsimNoCcnDump 0 +fHsimFsdbProfDiag 0 +fVpdSeqGate 0 +fVpdUseMaxBCode 0 +fVpdHsIntVecGate 0 +fVpdHsCmplxVecGate 0 +fVpdHsVecGateDiags 0 +fSeqGateCodePatch 0 +fVpdLongFaninOpt 0 +fVpdSeqLongFaninOpt 0 +fVpdNoLoopDetect 0 +fVpdNoSeqLoopDetect 0 +fVpdOptAllowConstDriver 0 +fVpdAllowCellReconstruction 0 +fVpdRtlForSharedLib 0 +fRaptorProf 0 +fHsimVpdOptGateMustDisable 0 +fHsimVpdOptGate 1 +fHsimVpdOptDelay 0 +fHsimVpdOptMPDelay 0 +fHsimVpdOptDiag 0 +fHsimVpdOptRtlIncrFix 0 +fHsimVpdOptDiagV 0 +fHsimCbkOptVecWithVcsd 0 +fHsimCbkOptDiag 0 +fHsimByRefIBN 1 +fHsimWireMda 1 +fHsimUniqifyElabDiag 0 +fHsimForceCbkVec 1 +fHsimSplitForceCbkVec 1 +fHsimLowPower 0 +fHsimLowPowerDumpOnly 0 +fHsimLowPowerDiag 0 +fHsimXpropFix 1 +fHsimXpropConfigTrace 0 +fHsimNameBasedInterface 1 +fHsimVcsInterfaceHierDiag 0 +fHsimCbSchedFix 0 +fHsimIncrDebug 0 +fHsimSK 0 +fHsimSharedKernel 1 +fHsimSKIncr 0 +fElabModTimeProfCount 0 +fHsimChangeSharedLib 0 +fHsimNewIncr 1 +fHsimIncrSkip 0 +fHsimSecondCheckMdb 0 +fHsimIntraXmrNotMaster 0 +fHsimExtNodeDiag 0 +fHsimExtIntfXmrDebug 0 +fHsimExtXmrNodeDiag 0 +fPartTopElabModName 0 +fHsimPreResolveXmr 1 +fHsimNoIntfXmrNonMaster 1 +fHsimXmrPropDebug 0 +fHsimXmrElabDebug 0 +fHsimXmrNoMaster 1 +fHsimXmrNoMasterIBIF 1 +fHsimIncrMaster 0 +fHsimEffTest 0 +fHsimIncrTest 0 +fHsimIncrTesting 0 +fHsimOnepass 0 +fHsimPartModSplit 0 +fHsimNoIncrMatch 0 +fHsimMergeOnly 0 +fHsimStitchNew 0 +fHsimCbkOpt 1 +fFrcRelCbk 1 +fPulserrWarn 1 +hsMtmSpec 0 +fprofile 0 +fPreserveDaidir 1 +fHsimLevelize 1 +fHsimSelectLevelize 0 +fHsimSelectEdgeData 0 +fHsimSelectEdgeDataDbg 0 +fHsimSelectEdgeDataSched0 0 +fHsimSelectEdgeDataSanity 0 +fHsimLevelizeFlatNodeLimit 22 +fHsimLevelizeNoSizeLimit 1 +fHsimLevelizeForce 0 +fHsimParallelLevelize 0 +fHsimParallelLevelizeDbg 0 +fHsimLevelizeNoCgDump 0 +fHsimReuseVcs1Sem 0 +semLevelizeVar -1 +fHsimLevelizeDbg 0 +fHsimMinputsPostEval 0 +fHsimSeqUdpDbsByteArray 0 +fHsimHilRtlAny 0 +fHsimHilRtlAll 0 +fHsimCoLocate 0 +fHsimNoinlSched0lq 0 +fHsimUdpOutputOpt 0 +fHsimSeqUdpEblkOpt 0 +fHsimSeqUdpEblkOptDiag 0 +fHsimGateInputAndDbsOffsetsOpt 1 +fHsimRelaxSched0 0 +fHsimLocalVar 0 +fHsimUdpDynElab 0 +fHsimCbDynElab 0 +fHsimCompressData 4 +fHsimIgnoreCaps 0 +fHsimMdbIgnoreCaps 0 +fHsimIgnoreZForDfuse 1 +fHsimIgnoreDifferentCaps 0 +fHsimIgnoreDifferentNStates 0 +fHandleGlitchQC 1 +fGlitchDetectForAllRtlLoads 0 +fHsimAllowFuseOnRegWithMultDrivers 0 +fHsimFuseConstDriversOpt 1 +fHsimMdSchedTr 0 +fHsimIgnoreReElab 0 +fHsimFuseMultiDrivers 0 +fHsimSched0 0 +fHsimPulseFilter 0 +fHsimNoSched0Reg 0 +fHsimAddSched0 0 +fHsimLargeBc 0 +fHsimLargePdbModule 0 +fHsimMMDebug 0 +fHsimMMLimit 0 +hsimMMLimit 0 +fHsimAmsFusionEnabled 0 +fHsimAmsWrealMdrEnabled 0 +fHsimAmsWrealInitValZero 1 +fWrealForce 0 +fHsimCgMarkers 0 +fHsimSplitRmaCode 1 +rmapatsPattCountThreshold 1000 +fHsimElab64 0 +fHsimTestFnn64 0 +fHsimTestDgn64 0 +fHsimRtlDbs 0 +fHsimWakeupId 0 +fHsimPassiveIbn 0 +fHsimInitialConst 0 +fHsimForceRtlDbs 0 +fHsimBcOpt 1 +fHsimBcOptDebug 0 +fHsimBfuseFast 1 +fHsimParallelElab 0 +fHsimParallelElabVcs1 0 +fpicArchive 1 +fCsrcInTmpDir 0 +fHsimInterconFE 1 +fHsimMxOpt 1 +fHsimModpathFE 1 +fHsimPathOnCCN 0 +fHsimOptMPDelayLoad 0 +fHsimTransMPDelay 1 +fLargeSizeSdfTest 0 +fAllMtm 0 +fHsimDelayGateMbme 0 +fHsimDelayGateMbmeOld 0 +fHsimNdb 1 +fHsimNdbDebug 0 +fHsimNdbTest 0 +fHsimGrpByGrpElabIncrTest 0 +fHsimGrpByGrpElabIncrTest2 0 +fHsimTestAggrCg 0 +fHsimOneInputGateAggrCg 0 +fHsimCertitude 0 +fHsimCertRapAutoTest 0 +fHsimRaceDetect 0 +fCheckTcCond 0 +fHsimSimlearnDdce 0 +fHsimSimlearnDdce_diag 0 +fHsimScanOpt 0 +fHsimScanOptPartComp 0 +fHsimHsoptNoScanOpt 0 +fHsimNoScanOptDeadLogic 1 +fHsimScanOptFixForDInSIPath 1 +fHsimNoScanOptForNonScanLoad 0 +fHsimScanOptLoopFix 1 +fHsimScanOptLoopFix2 0 +fHsimScanOptRelaxDbg 0 +fHsimScanOptRelaxDbgDynamic 0 +fHsimScanOptRelaxDbgDynamicPli 0 +fHsimScanOptRelaxDbgDiag 0 +fHsimScanOptRelaxDbgDiagHi 0 +fHsimScanOptNoErrorOnPliAccess 0 +fHsimScanOptTiming 0 +fRelaxIbnSchedCheck 0 +fHsimScanOptNoDumpCombo 0 +fHsimScanOptPrintSwitchState 0 +fHsimScanOptSelectiveSwitchOn 0 +fHsimScanOptSingleSEPliOpt 1 +fHsimScanOptDesignHasDebugAccessOnly 0 +fHsimScanOptPrintPcode 0 +fHsimNettypeOneDrvPerfOpt 0 +fHsimOldNettypeResFnOffset 0 +fHsimScanoptDump 0 +fHsimScanDbgFunc 0 +fHsimScanDbgPerf 0 +fHsimAutoScanSuppWarn 0 +fHsimScanOptAggr 0 +fHsimScanOptFuse 1 +fHsimScanMemOpt 1 +fHsimScanChainOpt 0 +fHsimForceChangeCheck 0 +fHsimFuseConsts 0 +fHsimMemBusOpt 0 +fHsimDefLevelElab 0 +fHsimOneInstElabMods 0 +fHsimOneInstElabModsHeur 1 +fHsimOneInstElabModsAllowDbg 0 +fHsimTopElabMods 0 +fHsimPVCS 0 +fHsimNoStitchMap 0 +fHsimUnifiedModName 0 +fHsimVIIntegrityCheck 0 +fHsimOrigViewType 0 +fHsimXmrDumpFullDR 0 +fHsimXmrDumpDebug 0 +fHsimRTLoopDectEna 0 +fHsimAssertInActive 0 +dGblTeE 1.000000 +dGblTeR 1.000000 +dGblPeE 1.000000 +dGblPeR 1.000000 +fNewdaidirpath 0 +fHsimDelayMbmeCheck 4 +fHsimMdbPartInputLimit 1 +fHsimSdfData 0 +fHsimDesignHasSdfAnnotation 0 +fHsimDesignUsesParallelVcs 0 +fHsimCMEnabled 0 +fGblMSah 0 +fGblMSTe 0 +fGblIntPe 0 +fGblTe 0 +fGblPe 0 +iPulseR 100 +iPulseE 100 +iTransR 100 +iTransE 100 +fPulseOpt 0 +fGblPulseOnD 0 +fGblPulseOnE 0 +fVCSiFlow 0 +fSystemVCSEnabled 1 +fHsimForcedPort 0 +fpicOption 1 +fModelSave 0 +fHsimGenObj 1 +fHsimCbkMemOpt 1 +fHsimCbkMemOptDebug 0 +fHsimMasterModuleOnly 0 +fHsimDumpOriginalFlatNodeNumsMap 0 +fHsimRecordPli 0 +fHsimPlaybackPli 0 +fHsimModByModElabForGates 0 +fHsimMdbOpts 0 +fHsimMdbInlineNew 0 +fHsimMdbSelUdp2Rtl 0 +fHsimMdbUdp2Rtl 0 +fHsimZeroDelayDelta 1 +fHsimMdbUdp2Rtl_3state 0 +fHsimMdbUdp2Rtl_noxedge 0 +fHsimMdbUdp2Rtl_dfsr 0 +fHsimMdbInsertComplexSelect 0 +fHsimMdbNoComplexSelect 0 +fHsimMdbScalarization 0 +fHsimCmplxOperScalarization 0 +fHsimMdbVectorizeInstances2 0 +fHsimMdbVectorizeInstancesCfg 0 +fHsimMdbVectorizeInstDiag 0 +fHsimMdbVectorizeInstances3 0 +fHsimMdbOptimizeSeqUdp 0 +fHsimMdbB2BLatch 0 +fHsimMdbAggr 0 +fHsimMdbGateGroupNew 0 +fHsimMdbUdpGroup 0 +fHsimMdbOptimizeConstants 0 +fHsimMdbDfuse 0 +fHsimMdbBfuse 0 +fHsimMdbDce 0 +fHsimMdbMpopt 0 +fHsimMdbCondMpOpt 0 +fHsimMdbSimplifyMpCond 0 +fHsimDceIgnorecaps 0 +fHsimCondModPathDbs 0 +fHsimCondModPathCompact 0 +fHsimMdbCondMpMerge 0 +fHsimModPathCg 0 +fHsimNoCondModPathCg 0 +fHsimCompactCode 0 +fHsimCondTC 0 +fHsimMacroTC 0 +fHsimCondMPConst 0 +fHsimCondTCConst 0 +fHsimMergeDelay 0 +fHsimDelayOpt 0 +fRemoveDelonTrans 1 +fHsimModPathLoadOpt 1 +fHsimMdbTranOpt 0 +fHsimMdbTranMerge 0 +fHsimRmapatsCsh 0 +fHsimLrmSupply 0 +fHsimNewMbmeFlow 0 +fHsimBackEndInteg 0 +fHsimBackEndIntegCapsOk 0 +fHsimBackEndIntegDiag 0 +fHsimBackEndIntegMaxIbns 1024 +fHsimBackEndIntegDeadObns 0 +fHsimTran2MosDriver 1 +fHsimDumpCcn 0 +fHsimMdbNStateAnalysis 0 +fHsimMdbAdjustWidth 0 +fHsimMdbOptimizeSelects 0 +fHsimMdbScalarizePorts 0 +fHsimMdbOptimizeSelectsHeuristic 1 +fHsimMdbPart 0 +fHsimMdb1006Partition 0 +fHsimVectorPgate 0 +fHsimNoHs 0 +fHsimXmrPartition 0 +fHsimNewPartition 0 +fHsimElabPart 0 +fHsimElabPartThreshHoldDesign 1 +fHsimPMdb 0 +fHsimParitionCellInstNum 1000 +fHsimParitionCellNodeNum 1000 +fHsimParitionCellXMRNum 1000 +fHsimNewPartCutSingleInstLimit 268435455 +fHsimElabModDistNum 0 +fHsimElabPartThreshHoldModule 3000000 +fHsimPCPortPartition 0 +fHsimPortPartition 0 +fHsimMdbHdbsBehavior 0 +fHsimMdbHdbsBehaviorTC 0 +fHsimMdbIbnObnPartition 0 +fHsimMdbDebugOpt0 0 +fHsimMdbClockAnalysis 0 +fHsimMdbMimo 0 +fHsimMdbMimoLite 0 +fHsimMdbMimoAggr 0 +fHsimDumpMdb 0 +fHsimDumpMdbVpd 0 +fHsimElabDiag 0 +fHsimElabMasterDiag 0 +fHsimElabDiagSummary 0 +fHsimElabDiagMn 0 +fHsimElabDiagMnCount 0 +fHsimElabDiagLite 0 +fHsimSimpCollect 0 +fHsimPcodeDiag 0 +fHsimDbsAlwaysBlocks 1 +fHsimPrintNodeMap 0 +fHsimSvAggr 0 +fHsimDynamicFlatNode 0 +fHsimSeqPrimCg 1 +fHsimDiagPats 0 +fHsimDdPats 0 +fHsimPatOpt 3 +fHsimPatInline 0 +fHsimPatOutline 0 +fHsimFastelab 0 +fHsimMacroOpt 0 +fHsimSkipOpt 0 +fHsimSkipOptFanoutlimit 0 +fHsimSkipOptRootlimit 0 +fHsimFuseDelayChains 0 +fFusempchainsFanoutlimit 0 +fFusempchainsDiagCount 0 +fHsimCloadOpt 0 +fHsimNoICDelayPropPwEqDelay 0 +fHsimPrintMopComment 0 +fNewRace 0 +fHsimCgVectorGates 0 +fHsimCgVectorGates1 0 +fHsimCgVectorGates2 0 +fHsimCgVectorGatesNoReElab 0 +fHsimCgScalarGates 0 +fHsimCgScalarGatesExpr 0 +fHsimCgScalarGatesLut 0 +fHsimCgRtl 1 +fHsimCgRtlFilter 0 +fHsimCgRtlDebug 0 +fHsimCgRtlSize 15 +fHsimNewCg 0 +fHsimNewCgRt 0 +fHsimNewCgFg 0 +fHsimNewCgMinput 0 +fHsimNewCgUpdate 0 +fHsimNewCgMP 0 +fHsimNewCgMPRt 0 +fHsimNewCgMPRetain 0 +fHsimNewCgTC 0 +fHsimCgRtlInfra 1 +fHsimGlueOpt 0 +fHsimPGatePatchOpt 0 +fHsimCgNoPic 0 +fHsimElabModCg 0 +fPossibleNullChecks 0 +fHsimProcessNoSplit 1 +fHsimMdbInstDiag 0 +fHsimMdbOptInSchedDelta 0 +fScaleTimeValue 0 +fDebugTimeScale 0 +fPartCompSDF 0 +fHsimNbaGate 1 +fDumpDtviInfoInSC 0 +fDumpSDFBasedMod 1 +fHsimSdfIC 0 +fHsimSdfICOverlap 0 +fHsimSdfICDiag 0 +fHsimSdfICOpt 0 +fHsimMsvSdfInout 0 +fOptimisticNtcSolver 0 +fHsimAllMtm 0 +fHsimAllMtmPat 0 +fHsimSdgOptEnable 0 +fHsimSVTypesRefPorts 0 +fHsimGrpByGrpElabIncr 0 +fHsimGrpByGrpElabIncrDiag 0 +fHsimEvcdTranSeen 0 +fHsimMarkRefereeInVcsElab 0 +fHsimStreamOpFix 1 +fHsimInterface 0 +fHsimNoPruning 0 +fHsimNoVarBidirs 0 +fHsimMxWrapOpt 0 +fHsimMxTopBdryOpt 0 +fHsimAggressiveDce 0 +fHsimDceDebug 1 +fHsimDceDebugUseHeuristics 1 +fHsimMdbUnidirSelects 0 +fHsimMdbNewDebugOpt 0 +fHsimMdbNewDebugOptExitOnError 1 +fHsimNewDebugOptMemDiag 0 +hsGlobalVerboseLevel 0 +fHsimMdbVectorConstProp 1 +fHsimEnableSeqUdpWrite 1 +fHsimDumpMDBOnlyForSeqUdp 0 +fHsimInitRegRandom 0 +fHsimInitRegRandomVcs 1 +fEnableNewFinalStrHash 0 +fEnableNewAssert 1 +fRunDbgDmma 0 +fAssrtCtrlSigChk 1 +fCheckSigValidity 0 +fUniqPriToAstRewrite 0 +fUniqPriToAstCtrl 0 +fAssertcontrolUniqPriNewImpl 0 +fRTLoopDectEna 0 +fCmplLoopDectEna 0 +fHsimMopFlow 1 +fUCaseLabelCtrl 0 +fUniSolRtSvaEna 1 +fUniSolSvaEna 1 +fXpropRtCtrlCallerOnly 0 +fHsimRaptorPart 0 +fHsimEnableDbsMemOpt 1 +fHsimDebugDbsMemOpt 0 +fHsimRenPart 0 +fHsimShortElabInsts 0 +fHsimNoTcSched 0 +fHsimSchedOpt 0 +fHsimXmrAllWires 0 +fHsimXmrDiag 0 +fHsimXmrPort 0 +fHsimFalcon 1 +fHsimGenForProfile 0 +fHsimDumpMdbAll 0 +fHsimDumpMdbRaptor 0 +fHsimDumpMdbGates 0 +fHsimDumpMdbPrune 0 +fHsimDumpMdbInline 0 +fHsimDumpMdbCondTC 0 +fHsimDumpMdbNState 0 +fHsimDumpMdbVhVlInputFuseOpt 0 +fHsimDumpMdbVhVlInoutFuseOpt 0 +fHsimDumpMdbVhVlCcnOpt 0 +fCompressSDF 0 +fHsimDumpMdbSchedDelta 0 +fHsimDumpMdbNoVarBidirs 0 +fHsimDumpMdbScalarize 0 +fHsimDumpMdbVecInst 0 +fHsimDumpMdbVecInst2 0 +fHsimDumpMdbDce 0 +fHsimDumpMdbScanopt 0 +fHsimDumpMdbSelects 0 +fHsimDumpMdbAggr 0 +fHsimDumpMdbOptConst 0 +fHsimDumpMdbVcsInterface 0 +fHsimDumpMdbDfuse 0 +fHsimDumpMdbBfuse 0 +fHsimDumpMdbTranOpt 0 +fHsimDumpMdbOptLoops 0 +fHsimDumpMdbSeqUdp 0 +fHsimDumpMdbMpOpt 0 +fHsimDumpMdbGG 0 +fHsimDumpMdbUdpGG 0 +fHsimDumpMdbMimo 0 +fHsimDumpMdbUdp2rtl 0 +fHsimDumpMdbUdpDelta 0 +fHsimDumpMdbDebugOpt 0 +fHsimDumpMdbSplitGates 0 +fHsimDumpMdb1006Part 0 +fHsimDumpMdbPart 0 +fHsimDumpMdbSimplifyMpCond 0 +fDlpSvtbExclElab 0 +fHsimDumpMdbCondMpMerge 0 +fHsimDumpMdbCondMp 0 +fHsimDumpMdbCondModPathDbs 0 +fHsimSdfAltRetain 0 +fHsimDumpMdbCompress 1 +fHsimDumpMdbSummary 0 +fHsimBfuseOn 1 +fHsimBfuseHeur 0 +fHsimBfuseHash 1 +fHsimSelectCell 0 +fHsimBfuseNoRedundantFanout 1 +fHsimBFuseVectorMinputGates 0 +fHsimBFuseVectorAlways 0 +fHsimDfuseOn 1 +fHsimDumpMdbPruneVpdGates 0 +fHsimGates1209 0 +fHsimCgRtlNoShareSmd 0 +fHsimGenForErSum 0 +fVpdOpt 1 +fHsimMdbCell 0 +fHsimCellDebug 0 +fHsimMdbCellComplexity 1.500000 +fHsimMdbCellHeur 1 +fHsimNoPeekInMdbCell 0 +fDebugDump 1 +fHsimOrigNodeNames 0 +hsimSrcList filelist +fHsimCgVectors2VOnly 0 +fHsimPortCoerce 0 +fHsimBidirOpt 0 +fHsimCheckLoop 1 +fHsimCheckLoopDiag 0 +fHsimCheckLoopMore 0 +fHsimLoop 1 +fHsimMdbDeltaGate 0 +fHsimMdbDeltaGateAggr 0 +fHsimMdbVecDeltaGate 1 +fHsimVpdOptVfsDB 1 +fHsimMdbPruneVpdGates 1 +fHsimPcPe 0 +fHsimVpdGateOnlyFlag 1 +fHsimMxConnFrc 0 +fHsimNewForceCbkVec 0 +fHsimNewForceCbkVecDiag 0 +fHsimMdbReplaceVpdHighConn 1 +fHsimVpdHighConnReplaced 1 +fHsimVpdOptSVTypes 1 +fHsimDlyInitFrc 0 +fHsimCompactVpdFn 1 +fHsimPIP 0 +fHsimRTLoopDectOrgName 0 +fHsimVpdOptPC 0 +fHsimFusePeXmrFo 0 +fHsimXmrSched 0 +fHsimNoMdg 0 +fHsimUseBidirSelectsInVectorGates 0 +fHsimGates2 0 +fHsimVectorGates 0 +fHsimHilCg 0 +fHsimHilVecAndRtl 0 +fHsimRtlLite 0 +fHsimMdbcgLut 0 +fHsimMdbcgSelective 0 +fHsimVcselabGates 0 +fHsimMdbcgUnidirSel 0 +fHsimMdbcgLhsConcat 0 +fHsimMdbcgSelectSplit 0 +fHsimMdbcgProcessSelSplit 0 +fHsimMdbcgEdgeop 0 +fHsimMdbcgMultiDelayControl 1 +fHsimParGateEvalMode 0 +fHsimDFuseVectors 0 +fHsimDFuseVecIgnoreFrc 0 +fHsimDFuseZero 0 +fHsimDFuseOpt 1 +fHsimAllPortsDiag 0 +fHsimPruneOpt 0 +fHsimSeqUdpPruneWithConstInputs 0 +fHsimSafeDFuse 0 +fHsimVpdOptExpVec 0 +fHsimVpdOptSelGate 1 +fHsimVpdOptSkipFuncPorts 0 +fHsimVpdOptAlways 1 +fHsimVpdOptMdbCell 0 +fHsimVpdOptPartialMdb 1 +fHsimVpdOptPartitionGate 1 +fHsimVpdOptXmr 1 +fHsimVpdOptConst 1 +fHsimVpdOptMoreLevels 1 +fHsimVpdHilRtl 0 +fHsimSWave 0 +fHsimNoSched0InCell 1 +fHsimPartialMdb 0 +hsimPdbLargeOffsetThreshold 1048576 +fHsimFlatCell 0 +fHsimFlatCellLimit 0 +fHsimRegBank 0 +fHsimHmetisMaxPartSize 0 +fHsimHmetisGateWt 0 +fHsimHmetisUbFactor 0 +fHsimHmetis 0 +fHsimHmetisDiag 0 +fHsimRenumGatesForMdbCell 0 +fHsimHmetisMinPart 0 +fHsim2stCell 0 +fHsim2stCellMinSize 0 +fHsimMdbcgDebug 0 +fHsimMdbcgDebugLite 0 +fHsimMdbcgDistrib 0 +fHsimMdbcgSepmem 0 +fHsimMdbcgObjDiag 0 +fHsimMdbcg2stDiag 0 +fHsimMdbcgRttrace 0 +fHsimMdbVectorGateGroup 1 +fHsimMdbProcDfuse 1 +fHsimMdbHilPrune 0 +fHsimNewConstProp 0 +fHsimSignedOp 0 +fHsimVarIndex 0 +fHsimNewMdbNstate 0 +fHsimProcessNstate 0 +fHsimMdbModpathNstate 0 +fHsimPgateConst 0 +fHsCgOpt 1 +fHsCgOptUdp 1 +fHsCgOptRtl 1 +fHsCgOptDiag 0 +fHsCgOptAggr 0 +fHsCgOptNoZCheck 0 +fHsCgOptEnableZSupport 0 +fHsCgOpt4StateInfra 0 +fHsCgOptDce 0 +fHsCgOptUdpChkDataForWakeup 1 +fHsNBACgOpt 1 +fHsCgOptXprop 0 +fHsimMdbcgDiag 0 +fHsCgMaxInputs 6 +fHsimMemory 0 +fHsCgOptFwdPass 1 +fHsimHpnodes 0 +fLightDump 0 +fRtdbgAccess 0 +fRtdbgOption 0 +fHDLCosim 0 +fHDLCosimDebug 0 +fHDLCosimTimeCoupled 0 +fHDLCosimTimeCoupledPorts 0 +HDLCosimMaxDataPerDpi 1 +HDLCosimMaxCallsPerDpi 2147483647 +fHDLCosimCompileDUT 0 +fHDLCosimCustomCompile 0 +fHDLCosimBoundaryAnalysis 0 +fVpdBeforeScan 1 +fHsCgOptMiSched0 0 +fgcAddSched0 0 +fParamClassOptRtDiag 0 +fHsRegress 0 +fHsBenchmark 0 +fHsimCgScalarVerilogForce 1 +fVcsElabToRoot 1 +fHilIbnObnCallByName 0 +fHsimMdbcgCellPartition 0 +fHsimCompressVpdSig 0 +fHsimLowPowerOpt 0 +fHsimUdpOpt 1 +fHsVecOneld 0 +fNativeVpdDebug 0 +fNewDtviFuse 0 +fHsimVcsGenTLS 1 +fAssertSuccDebugLevelDump 0 +fHsimMinputsChangeCheck 0 +fHsimClkLayout 0 +fHsimIslandLayout 0 +fHsimConfigSched0 0 +fHsimSelectFuseAfterDfuse 0 +vcsNettypeDbgOpt 4 +fHsimFoldedCell 0 +fHsimSimon2Mdb 0 +fHsimSWaveEmul 0 +fHsimSWaveDumpMDB 0 +fHsimSWaveDumpFlatData 0 +fHsimRenumberAlias 0 +fHsimAliasRenumbered 0 +fHilCgMode 115 +fHsimUnionOpt 0 +fHsimFuseSGDBoundaryNodes 0 +fHsimRemoveCapsVec 0 +fHsimSlowNfsRmapats 0 +fHsimCertRaptScal 0 +fHsimCertRaptMdbClock 0 +fHsCgOptMux 0 +fHsCgOptFrc 0 +fHsCgOpt30 0 +fHsLpNoCapsOpt 0 +fHsCgOpt4State 1 +fHashTableSize 12 +fSkipStrChangeOnDelay 1 +fHsimTcheckOpt 0 +fHsCgOptMuxMClk 0 +fHsCgOptMuxFrc 0 +fHsCgOptNoPcb 0 +fHsCgOptMin1 0 +fHsCgOptUdpChk 0 +fHsChkXForSlowSigProp 1 +fHsimVcsParallelDbg 0 +fHsimVcsParallelStrategy 0 +fHsimVcsParallelOpt 0 +fHsimVcsParallelSubLevel 4 +fHsimParallelEblk 0 +fHsimByteCodeParts 1 +fHsimByteCodePartTesting 0 +fHsimByteCodePartAssert 0 +fFgpNovlInComp 0 +fFutEventPRL 0 +fFgpNbaDelay 0 +fHsimDbsFlagsByteArray 0 +fHsimDbsFlagsByteArrayTC 0 +fHsimDbsFlagsThreadArray 0 +fHsimLevelCompaction 0 +fHsimLevelCompactionThreshold 0 +fHsimGateEdgeEventSched 0 +fHsimGateEdgeEventSchedThreshold 0 +fHsimGateEdgeEventSchedSanity 0 +fHsimSelectEdgeEventSched 0 +fHsimSelectEdgeEventSchedNoTempReuse 0 +fHsimSelectEdgeEventSchedThreshold 0 +fHsimMaxComboLevels 0 +fHsimEgschedDynelab 0 +fHsimUdpClkDynelab 0 +fUdpLayoutOnClk 0 +fHsimDiagClk 1 +fDbsPreCheck 0 +fHsimSched0Analysis 0 +fHsimMultiDriverSched0 0 +fHsimLargeIbnSched 0 +fFgpHierarchical 0 +fFgpHierAllElabModAsRoot 0 +fFgpHierPCElabModAsRoot 0 +fFgpAdjustDataLevelOfLatch 1 +fHsimUdpXedgeEval 0 +fFgpRaceCheck 0 +fFgpUnifyClk 0 +fFgpSmallClkTree 0 +fFgpSmallRtlClkTree 4 +fFgpNoRtlUnlink 0 +fFgpNoRtlAuxLevel 0 +fFgpNumPartitions 8 +fFgpMultiSocketCompile 0 +fFgpMultiSocketAfterGrping 0 +fFgpMultiSocketNCuts 1 +fFgpMultiSocketDiag 0 +fFgpMultiSocketRecomputePart 1 +fFgpDataDepOn 0 +fFgpDDIgnore 0 +fFgpXmrDepOn 0 +fFgpTbCbOn 0 +fFgpTbEvOn 1 +fFgpTbNoVSA 0 +fFgpTbEvXmr 0 +fFgpTbEvCgCall 1 +fFgpDisabledLevel 512 +fFgpSched0User 0 +fFgpNoSdDelayedNbas 1 +fFgpTimingFlags 0 +fFgpTcLoadThreshold 0 +fFgpSched0Level 0 +fHsimFgpMultiClock 0 +fFgpScanOptFix 0 +fFgpSched0UdpData 0 +fFgpSanityTest 0 +fFgpSanityTest_Eng 1 +fFgpAlternativeLevelization 0 +fFgpHighFanoutThreshold 1024 +fFgpSplitGroupLevels 1 +fFgpSplitGroupIbn 1 +fFgpSplitGroupGateEdge 1 +fFgpSplitGroupEval 3 +fFgpGroupingPerfDiag 0 +fFgpSplitGroupDiag 0 +fFgpStricDepModDiag 0 +fFgpIPProtect 0 +fFgpIPProtectStrict 0 +fFgpNoVirtualThreads 0 +fFgpLoadBalance0DiagComp 0 +fFgpLoadBalance0CompileTime 1 +fFgpDepositDiag 0 +fFgpEvtDiag.diagOn 0 +fFgpEvtDiag.printAllNodes 0 +fFgpMangleDiagLog 0 +fFgpMultiExclDiag 0 +fFgpSingleExclReason 0 +fHsDoFaninFanoutSanity 0 +fHsFgpNonDbsOva 1 +fFgpParallelTask 1 +fFgpIbnSched 0 +fFgpIbnSchedOpt 0 +fFgpIbnSchedNoLevel 0 +fFgpIbnSchedThreshold 0 +fFgpIbnSchedDyn 0 +fFgpObnSched 0 +fFgpMpStateByte 0 +fFgpTcStateByte 0 +fHsimVirtIntfDynLoadSched 0 +fHsimNetXmrDrvChk 0 +fFgpNoRtimeFgp 0 +fHsFgpGlSched0 0 +fFgpExclReason 0 +fHsimIslandByIslandElab 0 +fHsimIslandByIslandFlat 0 +fHsimIslandByIslandFlat1 0 +fHsimVpdIBIF 0 +fHsimXmrIBIF 0 +fHsimReportTime 0 +fHsimElabJ 0 +fHsimElabJ4SDF 0 +cElabProcs 0 +hf_fHsimElabJ 0 +fHsimElabJOpt 0 +fHsimElabJMMFactor 0 +fHsimOneInstCap 0 +fHsimSchedMinput 0 +fHsimSchedSeqPrim 0 +fHsimSchedRandom 0 +fHsimSchedAll 0 +fHsimSchedSelectFanout 0 +fHsimSchedSelectFanoutDebug 0 +fHsimSchedSelectFanoutRandom 0 +fFgpDynamicReadOn 0 +fHsCgOptAllUc 0 +fHsimNoReconvergenceSched0 0 +fHsimXmrRepl 0 +fZoix 0 +fHsimDfuseNewOpt 0 +fHsimBfuseNewOpt 0 +fFgpMbme 0 +fFgpXmrSched 0 +fHsimClearClkCaps 0 +fFgpHideXmrNodes 0 +fHsimDiagClkConfig 0 +fHsimDiagClkConfigDebug 0 +fHsimDiagClkConfigDumpAll 0 +fHsDiagClkConfigPara 0 +fHsimDiagClkConfigAn 0 +fHsimCanDumpClkConfig 0 +fFgpInitRout 0 +fFgpIgnoreExclSD 0 +fHsimAggrTCOpt 0 +fFgpNewAggrXmrIterFlow 0 +fFgpNoLocalReferer 0 +fHsCgOptNoClockFusing 0 +fHsClkWheelLimit 50000 +fHsFgpSchedCgUcLoads 1 +fHsimAdvanceUdpInfer 0 +fFgpIbnSchedIntf 0 +fHsCgOptNewSelCheck 1 +fFgpReportUnsafeFuncs 0 +fHsCgOptUncPrlThreshold 4 +fHsimCosimGatesProp 0 +fHsSVNettypePerfOpt 0 +fHsCgOptHashFixMap 1 +fHsimLowPowerRetAnalysisInChild 0 +fRetainWithDelayedSig 0 +fHsimChargeDecay 0 +fHsimCongruencyConfigFile 0 +fHsimCongruencyLogFile 0 +fHsimCoverageEnabled 0 +fHsimCoverageOptions 0 +fHsimCoverageDir NULL diff --git a/tb/chip_top/simv.daidir/vcselab_misc_hsim_fegate.db b/tb/chip_top/simv.daidir/vcselab_misc_hsim_fegate.db new file mode 100644 index 0000000..ef0f4be Binary files /dev/null and b/tb/chip_top/simv.daidir/vcselab_misc_hsim_fegate.db differ diff --git a/tb/chip_top/simv.daidir/vcselab_misc_hsim_lvl.db b/tb/chip_top/simv.daidir/vcselab_misc_hsim_lvl.db new file mode 100644 index 0000000..50e5cb2 Binary files /dev/null and b/tb/chip_top/simv.daidir/vcselab_misc_hsim_lvl.db differ diff --git a/tb/chip_top/simv.daidir/vcselab_misc_hsim_merge.db b/tb/chip_top/simv.daidir/vcselab_misc_hsim_merge.db new file mode 100644 index 0000000..4aae68d Binary files /dev/null and b/tb/chip_top/simv.daidir/vcselab_misc_hsim_merge.db differ diff --git a/tb/chip_top/simv.daidir/vcselab_misc_hsim_name.db b/tb/chip_top/simv.daidir/vcselab_misc_hsim_name.db new file mode 100644 index 0000000..76221e0 Binary files /dev/null and b/tb/chip_top/simv.daidir/vcselab_misc_hsim_name.db differ diff --git a/tb/chip_top/simv.daidir/vcselab_misc_hsim_uds.db b/tb/chip_top/simv.daidir/vcselab_misc_hsim_uds.db new file mode 100644 index 0000000..e15e8df --- /dev/null +++ b/tb/chip_top/simv.daidir/vcselab_misc_hsim_uds.db @@ -0,0 +1,145 @@ +vcselab_misc_midd.db 39889 +vcselab_misc_mnmn.db 832 +vcselab_misc_hsim_name.db 9821 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 1061116 +vcselab_misc_midd.db 39889 +vcselab_misc_mnmn.db 832 +vcselab_misc_hsim_name.db 9821 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 1061116 +vcselab_misc_midd.db 39889 +vcselab_misc_mnmn.db 832 +vcselab_misc_hsim_name.db 9821 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 1061116 +vcselab_misc_midd.db 39889 +vcselab_misc_mnmn.db 832 +vcselab_misc_hsim_name.db 9821 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 1061116 +vcselab_misc_midd.db 39889 +vcselab_misc_mnmn.db 832 +vcselab_misc_hsim_name.db 9821 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 1061116 +vcselab_misc_midd.db 39889 +vcselab_misc_mnmn.db 832 +vcselab_misc_hsim_name.db 9821 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 1061116 +vcselab_misc_midd.db 39889 +vcselab_misc_mnmn.db 832 +vcselab_misc_hsim_name.db 9821 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 1061116 +vcselab_misc_midd.db 39889 +vcselab_misc_mnmn.db 832 +vcselab_misc_hsim_name.db 9821 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 1061116 +vcselab_misc_midd.db 39889 +vcselab_misc_mnmn.db 832 +vcselab_misc_hsim_name.db 9821 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 1061116 +vcselab_misc_midd.db 39889 +vcselab_misc_mnmn.db 832 +vcselab_misc_hsim_name.db 9821 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 1061116 +vcselab_misc_midd.db 39889 +vcselab_misc_mnmn.db 832 +vcselab_misc_hsim_name.db 9821 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 1061116 +vcselab_misc_midd.db 39665 +vcselab_misc_mnmn.db 805 +vcselab_misc_hsim_name.db 9725 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 1058500 +vcselab_misc_midd.db 39665 +vcselab_misc_mnmn.db 805 +vcselab_misc_hsim_name.db 9725 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 1058500 +vcselab_misc_midd.db 39665 +vcselab_misc_mnmn.db 805 +vcselab_misc_hsim_name.db 9725 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 1058512 +vcselab_misc_midd.db 39665 +vcselab_misc_mnmn.db 805 +vcselab_misc_hsim_name.db 9725 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 1058512 +vcselab_misc_midd.db 39665 +vcselab_misc_mnmn.db 805 +vcselab_misc_hsim_name.db 9725 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 1058512 +vcselab_misc_midd.db 39665 +vcselab_misc_mnmn.db 805 +vcselab_misc_hsim_name.db 9725 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 1058512 +vcselab_misc_midd.db 39665 +vcselab_misc_mnmn.db 805 +vcselab_misc_hsim_name.db 9725 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 1058512 +vcselab_misc_midd.db 39665 +vcselab_misc_mnmn.db 805 +vcselab_misc_hsim_name.db 9725 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 1058512 +vcselab_misc_midd.db 39665 +vcselab_misc_mnmn.db 805 +vcselab_misc_hsim_name.db 9725 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 1058512 +vcselab_misc_midd.db 39665 +vcselab_misc_mnmn.db 805 +vcselab_misc_hsim_name.db 9725 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 1058512 +vcselab_misc_midd.db 39665 +vcselab_misc_mnmn.db 805 +vcselab_misc_hsim_name.db 9725 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 1058512 +vcselab_misc_midd.db 39665 +vcselab_misc_mnmn.db 805 +vcselab_misc_hsim_name.db 9725 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 1058512 +vcselab_misc_midd.db 39665 +vcselab_misc_mnmn.db 805 +vcselab_misc_hsim_name.db 9725 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 1058512 +vcselab_misc_midd.db 39665 +vcselab_misc_mnmn.db 805 +vcselab_misc_hsim_name.db 9725 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 1058512 +vcselab_misc_midd.db 39665 +vcselab_misc_mnmn.db 805 +vcselab_misc_hsim_name.db 9725 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 1058512 +vcselab_misc_midd.db 39665 +vcselab_misc_mnmn.db 805 +vcselab_misc_hsim_name.db 9725 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 1058512 +vcselab_misc_midd.db 39665 +vcselab_misc_mnmn.db 805 +vcselab_misc_hsim_name.db 9725 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 1058512 +vcselab_misc_midd.db 39665 +vcselab_misc_mnmn.db 805 +vcselab_misc_hsim_name.db 9725 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 1058500 diff --git a/tb/chip_top/simv.daidir/vcselab_misc_midd.db b/tb/chip_top/simv.daidir/vcselab_misc_midd.db new file mode 100644 index 0000000..7659da8 Binary files /dev/null and b/tb/chip_top/simv.daidir/vcselab_misc_midd.db differ diff --git a/tb/chip_top/simv.daidir/vcselab_misc_mnmn.db b/tb/chip_top/simv.daidir/vcselab_misc_mnmn.db new file mode 100644 index 0000000..9fe06a6 Binary files /dev/null and b/tb/chip_top/simv.daidir/vcselab_misc_mnmn.db differ diff --git a/tb/chip_top/simv.daidir/vcselab_misc_partition.db b/tb/chip_top/simv.daidir/vcselab_misc_partition.db new file mode 100644 index 0000000..fc455a1 Binary files /dev/null and b/tb/chip_top/simv.daidir/vcselab_misc_partition.db differ diff --git a/tb/chip_top/simv.daidir/vcselab_misc_partitionDbg.db b/tb/chip_top/simv.daidir/vcselab_misc_partitionDbg.db new file mode 100644 index 0000000..d0219f5 Binary files /dev/null and b/tb/chip_top/simv.daidir/vcselab_misc_partitionDbg.db differ diff --git a/tb/chip_top/simv.daidir/vcselab_misc_tCEYNb b/tb/chip_top/simv.daidir/vcselab_misc_tCEYNb new file mode 100644 index 0000000..20c4d8b Binary files /dev/null and b/tb/chip_top/simv.daidir/vcselab_misc_tCEYNb differ diff --git a/tb/chip_top/simv.daidir/vcselab_misc_vcselabref.db b/tb/chip_top/simv.daidir/vcselab_misc_vcselabref.db new file mode 100644 index 0000000..f76dd23 Binary files /dev/null and b/tb/chip_top/simv.daidir/vcselab_misc_vcselabref.db differ diff --git a/tb/chip_top/simv.daidir/vcselab_misc_vpdnodenums b/tb/chip_top/simv.daidir/vcselab_misc_vpdnodenums new file mode 100644 index 0000000..742d36f Binary files /dev/null and b/tb/chip_top/simv.daidir/vcselab_misc_vpdnodenums differ diff --git a/tb/chip_top/spi_if.sv b/tb/chip_top/spi_if.sv new file mode 100644 index 0000000..d143592 --- /dev/null +++ b/tb/chip_top/spi_if.sv @@ -0,0 +1,17 @@ + + +interface spi_if(input clk,input rstn); + + //timeunit 1ns; + //timeprecision 1ps; + logic sclk; + logic csn; + logic mosi; + logic miso; + + + +endinterface : spi_if + + + diff --git a/tb/chip_top/thermo15_binary4.v b/tb/chip_top/thermo15_binary4.v new file mode 100644 index 0000000..86297d3 --- /dev/null +++ b/tb/chip_top/thermo15_binary4.v @@ -0,0 +1,30 @@ +module thermo15_binary4( + input [14:0] thermo_code + ,output reg [3 :0] binary_code + ); + +wire [3:0]sum; +assign sum=thermo_code[0]+thermo_code[1]+thermo_code[2]+thermo_code[3]+thermo_code[4]+thermo_code[5]+thermo_code[6]+thermo_code[7]+thermo_code[8]+thermo_code[9]+thermo_code[10]+thermo_code[11]+thermo_code[12]+thermo_code[13]+thermo_code[14]; + +always @(*) begin + +case(sum) + 4'd0 : binary_code<=4'b0000; + 4'd1 : binary_code<=4'b0001; + 4'd2 : binary_code<=4'b0010; + 4'd3 : binary_code<=4'b0011; + 4'd4 : binary_code<=4'b0100; + 4'd5 : binary_code<=4'b0101; + 4'd6 : binary_code<=4'b0110; + 4'd7 : binary_code<=4'b0111; + 4'd8 : binary_code<=4'b1000; + 4'd9 : binary_code<=4'b1001; + 4'd10: binary_code<=4'b1010; + 4'd11: binary_code<=4'b1011; + 4'd12: binary_code<=4'b1100; + 4'd13: binary_code<=4'b1101; + 4'd14: binary_code<=4'b1110; + 4'd15: binary_code<=4'b1111; +endcase +end +endmodule \ No newline at end of file diff --git a/tb/chip_top/thermo2binary_top.v b/tb/chip_top/thermo2binary_top.v new file mode 100644 index 0000000..776e27b --- /dev/null +++ b/tb/chip_top/thermo2binary_top.v @@ -0,0 +1,30 @@ + + + + + +module thermo2binary_top ( + + input [14:0] DEM_MSB_IN + ,input [6 :0] DEM_ISB_IN + ,input [8 :0] DEM_LSB_IN + + ,output [15:0] DOUT +); + +wire [3:0] temp_data15_12; +thermo15_binary4 U_thermo15_binary4 ( + .thermo_code ( DEM_MSB_IN ) + ,.binary_code ( temp_data15_12 ) + ); + +wire [2:0] temp_data11_9; +thermo7_binary3 thermo7_binary3 ( + .thermo_code ( DEM_ISB_IN ) + ,.binary_code ( temp_data11_9 ) + ); + + +assign DOUT = {temp_data15_12[3:0],temp_data11_9[2:0],DEM_LSB_IN[8:0]}; + +endmodule \ No newline at end of file diff --git a/tb/chip_top/thermo7_binary3.v b/tb/chip_top/thermo7_binary3.v new file mode 100644 index 0000000..ce1f1e4 --- /dev/null +++ b/tb/chip_top/thermo7_binary3.v @@ -0,0 +1,22 @@ +module thermo7_binary3( + input [6:0] thermo_code + ,output reg [2 :0] binary_code +); + +wire [2:0]sum; +assign sum=thermo_code[0]+thermo_code[1]+thermo_code[2]+thermo_code[3]+thermo_code[4]+thermo_code[5]+thermo_code[6]; + +always @(*) begin + +case(sum) + 3'd0 : binary_code<=3'b000; + 3'd1 : binary_code<=3'b001; + 3'd2 : binary_code<=3'b010; + 3'd3 : binary_code<=3'b011; + 3'd4 : binary_code<=3'b100; + 3'd5 : binary_code<=3'b101; + 3'd6 : binary_code<=3'b110; + 3'd7 : binary_code<=3'b111; +endcase +end +endmodule \ No newline at end of file diff --git a/tb/chip_top/ucli.key b/tb/chip_top/ucli.key new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/verdiLog/.111237IC_EDA.conf b/tb/chip_top/verdiLog/.111237IC_EDA.conf new file mode 100644 index 0000000..3648493 --- /dev/null +++ b/tb/chip_top/verdiLog/.111237IC_EDA.conf @@ -0,0 +1,507 @@ +[QwMainWindow] +window\Verdi_1\layout="@ByteArray(\0\0\0\xff\0\x3\x14Q\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x2\x13\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x3H\0\0\0\x89\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\xe9\0\0\0\xc6\0\0\0k\0\0\0k\xfc\0\0\x3N\0\0\x6\xb2\0\0\0\xbf\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x4\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\x1\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x33\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x34\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x35\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\0\0\0\x3\0\0\n\0\0\0\x2\xd2\xfc\x1\0\0\0\x1\xfc\0\0\0\0\0\0\n\0\0\0\x2,\0\xff\xff\xff\xfa\0\0\0\x2\x1\0\0\0\x3\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\x1\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\x1[\0\xff\xff\xff\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x3\x16\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +window\Verdi_1\geometry=@ByteArray(\x1\xd9\xd0\xcb\0\x1\0\0\xff\xff\xff\xff\0\0\0\x1b\0\0\n\0\0\0\x5z\0\0\0\0\0\0\0\0\xff\xff\xff\xfe\xff\xff\xff\xfe\0\0\0\0\x2\0) +window\Verdi_1\menubar=true +window\Verdi_1\splitters\tbvConstrDbgSplitter\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x2\xff\xff\xff\xff\xff\xff\xff\xff\x1\0\0\0\x6\x1\0\0\0\x1) +window\Verdi_1\splitters\tbvConstrRerandSplitter\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x2\xff\xff\xff\xff\xff\xff\xff\xff\x1\0\0\0\x6\x1\0\0\0\x2) +window\Verdi_1\splitters\tbvConstrOriginSplitter\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x2\xff\xff\xff\xff\xff\xff\xff\xff\x1\0\0\0\x6\x1\0\0\0\x2) +window\Verdi_1\splitters\ThreadPane\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x2\xff\xff\xff\xff\xff\xff\xff\xff\x1\0\0\0\x6\x1\0\0\0\x2) +window\Verdi_1\splitters\tbvInteractiveSplitter\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x2\xff\xff\xff\xff\xff\xff\xff\xff\x1\0\0\0\x6\x1\0\0\0\x2) +window\Verdi_1\splitters\tbvVSimSplitter\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x2\xff\xff\xff\xff\xff\xff\xff\xff\x1\0\0\0\x6\x1\0\0\0\x2) +window\Verdi_1\splitters\tbvTBHSplitter\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x2\xff\xff\xff\xff\xff\xff\xff\xff\x1\0\0\0\x6\x1\0\0\0\x2) +window\nSchema_3\layout=@ByteArray(\0\0\0\xff\0\x3\x14Q\xfd\0\0\0\0\0\0\x6\xb2\0\0\x2\r\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x4\0\0\0\x2\0\0\0\v\0\0\0\x10\0S\0\x43\0H\0_\0V\0I\0\x45\0W\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x10\0S\0\x43\0H\0_\0\x45\0\x44\0I\0T\0\0\0\0\xab\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x10\0S\0\x43\0H\0_\0H\0I\0\x45\0R\x1\0\0\0\xab\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x12\0S\0\x43\0H\0_\0T\0R\0\x41\0\x43\0\x45\x1\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\f\0S\0\x43\0H\0_\0\x42\0\x41\x1\0\0\x2\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0S\0\x43\0H\0_\0P\0O\0W\0\x45\0R\0_\0S\0T\0\x41\0T\0U\0S\0_\0I\0N\0\x46\0O\0\0\0\x3\x66\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0S\0\x43\0H\0_\0P\0O\0W\0\x45\0R\0_\0\x44\0O\0M\0\x41\0I\0N\0_\0I\0N\0\x46\0O\0\0\0\x3\xce\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x34\0S\0\x43\0H\0_\0P\0O\0W\0\x45\0R\0_\0S\0I\0G\0N\0\x41\0L\0_\0T\0Y\0P\0\x45\0_\0I\0N\0\x46\0O\0\0\0\x4\x43\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0S\0\x43\0H\0_\0P\0O\0W\0\x45\0R\0_\0\x43\0\x45\0L\0L\0_\0T\0Y\0P\0\x45\0_\0I\0N\0\x46\0O\0\0\0\x4`\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x34\0S\0\x43\0H\0_\0S\0P\0I\0\x43\0\x45\0_\0S\0I\0G\0N\0\x41\0L\0_\0T\0Y\0P\0\x45\0_\0I\0N\0\x46\0O\0\0\0\x4\xc4\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1a\0S\0\x43\0H\0_\0\x43\0L\0O\0\x43\0K\0_\0M\0\x41\0P\0\0\0\x5\x19\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0.\0S\0\x43\0H\0_\0Q\0U\0I\0\x43\0K\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x32\0_\0P\0O\0I\0N\0T\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x32\0S\0\x45\0L\0\x45\0\x43\0T\0I\0O\0N\0_\0M\0\x45\0S\0S\0\x41\0G\0\x45\0_\0T\0O\0O\0L\0\x42\0\x41\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x38\0P\0R\0\x45\0S\0\x45\0L\0\x45\0\x43\0T\0I\0O\0N\0_\0M\0\x45\0S\0S\0\x41\0G\0\x45\0_\0T\0O\0O\0L\0\x42\0\x41\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0) +window\nSchema_3\geometry=@ByteArray(\x1\xd9\xd0\xcb\0\x1\0\0\0\0\0\0\0\0\0\x1b\0\0\x6\xb1\0\0\x2Y\0\0\0\0\0\0\0\x1b\0\0\x6\xb1\0\0\x2Y\0\0\0\0\0\0) +window\nSchema_3\menubar=true +window\nSchema_3\splitters\splitDrawAndProperty\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x3\xff\xff\xff\xff\0\0\0\0\xff\xff\xff\xff\x1\0\0\0\x6\x1\0\0\0\x1) +window\nSchema_3\splitters\splitPropertyAndRightDock\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x2\xff\xff\xff\xff\xff\xff\xff\xff\x1\0\0\0\x6\x1\0\0\0\x2) +window\nSchema_3\splitters\splitDrawAndMinimap\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x3\0\0\0\x1e\xff\xff\xff\xff\xff\xff\xff\xff\x1\0\0\0\x6\x1\0\0\0\x2) +window\nSchema_3\splitters\splitPropertyAndBottomDock\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x2\xff\xff\xff\xff\xff\xff\xff\xff\x1\0\0\0\x6\x1\0\0\0\x1) +window\nSchema_4\layout=@ByteArray(\0\0\0\xff\0\x3\x14Q\xfd\0\0\0\0\0\0\x6\xb2\0\0\x3\xd3\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x4\0\0\0\x2\0\0\0\v\0\0\0\x10\0S\0\x43\0H\0_\0V\0I\0\x45\0W\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x10\0S\0\x43\0H\0_\0\x45\0\x44\0I\0T\0\0\0\0\xab\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x10\0S\0\x43\0H\0_\0H\0I\0\x45\0R\x1\0\0\0\xab\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x12\0S\0\x43\0H\0_\0T\0R\0\x41\0\x43\0\x45\x1\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\f\0S\0\x43\0H\0_\0\x42\0\x41\x1\0\0\x2\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0S\0\x43\0H\0_\0P\0O\0W\0\x45\0R\0_\0S\0T\0\x41\0T\0U\0S\0_\0I\0N\0\x46\0O\0\0\0\x3\x66\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0S\0\x43\0H\0_\0P\0O\0W\0\x45\0R\0_\0\x44\0O\0M\0\x41\0I\0N\0_\0I\0N\0\x46\0O\0\0\0\x3\xce\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x34\0S\0\x43\0H\0_\0P\0O\0W\0\x45\0R\0_\0S\0I\0G\0N\0\x41\0L\0_\0T\0Y\0P\0\x45\0_\0I\0N\0\x46\0O\0\0\0\x4\x43\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0S\0\x43\0H\0_\0P\0O\0W\0\x45\0R\0_\0\x43\0\x45\0L\0L\0_\0T\0Y\0P\0\x45\0_\0I\0N\0\x46\0O\0\0\0\x4`\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x34\0S\0\x43\0H\0_\0S\0P\0I\0\x43\0\x45\0_\0S\0I\0G\0N\0\x41\0L\0_\0T\0Y\0P\0\x45\0_\0I\0N\0\x46\0O\0\0\0\x4\xc4\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1a\0S\0\x43\0H\0_\0\x43\0L\0O\0\x43\0K\0_\0M\0\x41\0P\0\0\0\x5\x19\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0.\0S\0\x43\0H\0_\0Q\0U\0I\0\x43\0K\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x32\0_\0P\0O\0I\0N\0T\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x32\0S\0\x45\0L\0\x45\0\x43\0T\0I\0O\0N\0_\0M\0\x45\0S\0S\0\x41\0G\0\x45\0_\0T\0O\0O\0L\0\x42\0\x41\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x38\0P\0R\0\x45\0S\0\x45\0L\0\x45\0\x43\0T\0I\0O\0N\0_\0M\0\x45\0S\0S\0\x41\0G\0\x45\0_\0T\0O\0O\0L\0\x42\0\x41\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0) +window\nSchema_4\geometry=@ByteArray(\x1\xd9\xd0\xcb\0\x1\0\0\0\0\0\0\0\0\0\x1b\0\0\x6\xb1\0\0\x4\x1f\0\0\0\0\0\0\0\x1b\0\0\x6\xb1\0\0\x4\x1f\0\0\0\0\0\0) +window\nSchema_4\menubar=true +window\nSchema_4\splitters\splitDrawAndProperty\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x3\xff\xff\xff\xff\0\0\0\0\xff\xff\xff\xff\x1\0\0\0\x6\x1\0\0\0\x1) +window\nSchema_4\splitters\splitPropertyAndRightDock\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x2\xff\xff\xff\xff\xff\xff\xff\xff\x1\0\0\0\x6\x1\0\0\0\x2) +window\nSchema_4\splitters\splitDrawAndMinimap\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x3\0\0\0\x1e\xff\xff\xff\xff\xff\xff\xff\xff\x1\0\0\0\x6\x1\0\0\0\x2) +window\nSchema_4\splitters\splitPropertyAndBottomDock\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x2\xff\xff\xff\xff\xff\xff\xff\xff\x1\0\0\0\x6\x1\0\0\0\x1) +window\nSchema_5\layout=@ByteArray(\0\0\0\xff\0\x3\x14Q\xfd\0\0\0\0\0\0\x6\xb2\0\0\x2\f\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x4\0\0\0\x2\0\0\0\v\0\0\0\x10\0S\0\x43\0H\0_\0V\0I\0\x45\0W\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x10\0S\0\x43\0H\0_\0\x45\0\x44\0I\0T\0\0\0\0\xab\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x10\0S\0\x43\0H\0_\0H\0I\0\x45\0R\x1\0\0\0\xab\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x12\0S\0\x43\0H\0_\0T\0R\0\x41\0\x43\0\x45\x1\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\f\0S\0\x43\0H\0_\0\x42\0\x41\x1\0\0\x2\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0S\0\x43\0H\0_\0P\0O\0W\0\x45\0R\0_\0S\0T\0\x41\0T\0U\0S\0_\0I\0N\0\x46\0O\0\0\0\x3\x66\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0S\0\x43\0H\0_\0P\0O\0W\0\x45\0R\0_\0\x44\0O\0M\0\x41\0I\0N\0_\0I\0N\0\x46\0O\0\0\0\x3\xce\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x34\0S\0\x43\0H\0_\0P\0O\0W\0\x45\0R\0_\0S\0I\0G\0N\0\x41\0L\0_\0T\0Y\0P\0\x45\0_\0I\0N\0\x46\0O\0\0\0\x4\x43\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0S\0\x43\0H\0_\0P\0O\0W\0\x45\0R\0_\0\x43\0\x45\0L\0L\0_\0T\0Y\0P\0\x45\0_\0I\0N\0\x46\0O\0\0\0\x4`\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x34\0S\0\x43\0H\0_\0S\0P\0I\0\x43\0\x45\0_\0S\0I\0G\0N\0\x41\0L\0_\0T\0Y\0P\0\x45\0_\0I\0N\0\x46\0O\0\0\0\x4\xc4\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1a\0S\0\x43\0H\0_\0\x43\0L\0O\0\x43\0K\0_\0M\0\x41\0P\0\0\0\x5\x19\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0.\0S\0\x43\0H\0_\0Q\0U\0I\0\x43\0K\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x32\0_\0P\0O\0I\0N\0T\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x32\0S\0\x45\0L\0\x45\0\x43\0T\0I\0O\0N\0_\0M\0\x45\0S\0S\0\x41\0G\0\x45\0_\0T\0O\0O\0L\0\x42\0\x41\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x38\0P\0R\0\x45\0S\0\x45\0L\0\x45\0\x43\0T\0I\0O\0N\0_\0M\0\x45\0S\0S\0\x41\0G\0\x45\0_\0T\0O\0O\0L\0\x42\0\x41\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0) +window\nSchema_5\geometry=@ByteArray(\x1\xd9\xd0\xcb\0\x1\0\0\0\0\0\0\0\0\0\x1b\0\0\x6\xb1\0\0\x2X\0\0\0\0\0\0\0\x1b\0\0\x6\xb1\0\0\x2X\0\0\0\0\0\0) +window\nSchema_5\menubar=true +window\nSchema_5\splitters\splitDrawAndProperty\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x3\xff\xff\xff\xff\0\0\0\0\xff\xff\xff\xff\x1\0\0\0\x6\x1\0\0\0\x1) +window\nSchema_5\splitters\splitPropertyAndRightDock\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x2\xff\xff\xff\xff\xff\xff\xff\xff\x1\0\0\0\x6\x1\0\0\0\x2) +window\nSchema_5\splitters\splitDrawAndMinimap\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x3\0\0\0\x1e\xff\xff\xff\xff\xff\xff\xff\xff\x1\0\0\0\x6\x1\0\0\0\x2) +window\nSchema_5\splitters\splitPropertyAndBottomDock\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x2\xff\xff\xff\xff\xff\xff\xff\xff\x1\0\0\0\x6\x1\0\0\0\x1) +window\nWave_2\layout="@ByteArray(\0\0\0\xff\0\x3\x14Q\xfd\0\0\0\0\0\0\n\0\0\0\x2j\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x2\0\0\0\x2\0\0\0\f\0\0\0\x12\0W\0\x41\0V\0\x45\0_\0O\0P\0\x45\0N\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x12\0W\0\x41\0V\0\x45\0_\0\x45\0\x44\0I\0T\x1\0\0\0?\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x16\0W\0\x41\0V\0\x45\0_\0\x43\0U\0R\0S\0O\0R\x1\0\0\0\xb4\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x12\0W\0\x41\0V\0\x45\0_\0V\0I\0\x45\0W\x1\0\0\x2\x46\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\"\0W\0\x41\0V\0\x45\0_\0S\0\x45\0\x41\0R\0\x43\0H\0_\0\x45\0V\0\x45\0N\0T\x1\0\0\x2\xa0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0W\0\x41\0V\0\x45\0_\0R\0\x45\0P\0L\0\x41\0Y\0_\0S\0I\0M\0\0\0\x2\xcb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x12\0W\0\x41\0V\0\x45\0_\0G\0O\0T\0O\x1\0\0\x3<\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0W\0\x41\0V\0\x45\0_\0G\0O\0T\0O\0_\0N\0\x41\0M\0\x45\0\x44\0_\0M\0\x41\0R\0K\0\x45\0R\x1\0\0\x3\xba\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0W\0\x41\0V\0\x45\0_\0T\0R\0\x41\0N\0S\0\x41\0\x43\0T\0I\0O\0N\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0W\0\x41\0V\0\x45\0_\0\x45\0X\0P\0L\0O\0R\0\x45\0_\0P\0R\0O\0P\0\x45\0R\0T\0Y\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0W\0\x41\0V\0\x45\0_\0\x46\0I\0N\0\x44\0_\0S\0I\0G\0N\0\x41\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x18\0W\0\x41\0V\0\x45\0_\0P\0R\0I\0M\0\x41\0R\0Y\0\0\0\x3`\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x32\0S\0\x45\0L\0\x45\0\x43\0T\0I\0O\0N\0_\0M\0\x45\0S\0S\0\x41\0G\0\x45\0_\0T\0O\0O\0L\0\x42\0\x41\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +window\nWave_2\geometry=@ByteArray(\x1\xd9\xd0\xcb\0\x1\0\0\0\0\0\0\0\0\0\x1b\0\0\t\xff\0\0\x2\xb6\0\0\0\0\0\0\0\x1b\0\0\t\xff\0\0\x2\xb6\0\0\0\0\0\0) +window\nWave_2\menubar=true +window\nWave_2\splitters\splitter_5\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\x2j\x1\0\0\0\x1\0\0\0\0\x2) +window\nWave_2\splitters\splitter_2\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x2\0\0\x1\x34\0\0\b\xcc\x1\0\0\0\x1\0\0\0\0\x1) +window\nWave_2\splitters\splitter\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x3\0\0\0\x41\0\0\0\x1\0\0\b\x88\x1\0\0\0\x1\0\0\0\0\x1) +window\nWave_2\splitters\Pane_Upper\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x2\0\0\x1\x34\0\0\b\xc9\x1\0\0\0\x1\0\0\0\0\x1) +window\nWave_2\splitters\splitter_3\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x2\xff\xff\xff\xff\xff\xff\xff\xff\x1\0\0\0\x1\0\0\0\0\x1) +window\nWave_2\splitters\wholeSplitter\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x3\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\x1\0\0\0\x6\x1\0\0\0\x1) +window\nWave_2\splitters\middleSplitter\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x2\xff\xff\xff\xff\xff\xff\xff\xff\x1\0\0\0\x6\x1\0\0\0\x2) + +[qBaseWindowStateGroup] +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qDockerWindow_qDockContentType\Verdi=1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qDockerWindow_qDockContentType\nWave=1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qDockerWindow_qDockContentType\nSchema=3 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qDockerWindow_qDockContentType\hdlHier=1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qDockerWindow_qDockContentType\hdlSrc=1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qDockerWindow_qDockContentType\messageWindow=1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qDockerWindow_qDockContentType\svtbHier=1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qDockerWindow_qDockContentType\OneSearch=1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qDockerWindowMgr_saveDockerChildList\Verdi_1=10 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qDockerWindowMgr_saveDockerChildList\Verdi_1_0=widgetDock_hdlHier_1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qDockerWindowMgr_saveDockerChildList\Verdi_1_1=widgetDock_messageWindow_1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qDockerWindowMgr_saveDockerChildList\Verdi_1_2=widgetDock_hdlSrc_1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qDockerWindowMgr_saveDockerChildList\Verdi_1_3=widgetDock_signalList_1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qDockerWindowMgr_saveDockerChildList\Verdi_1_4=widgetDock_svtbHier_1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qDockerWindowMgr_saveDockerChildList\Verdi_1_5=windowDock_OneSearch_1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qDockerWindowMgr_saveDockerChildList\Verdi_1_6=windowDock_nWave_1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qDockerWindowMgr_saveDockerChildList\Verdi_1_7=windowDock_nSchema_1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qDockerWindowMgr_saveDockerChildList\Verdi_1_8=windowDock_nSchema_2 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qDockerWindowMgr_saveDockerChildList\Verdi_1_9=windowDock_nSchema_3 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\widgetDock_hdlHier_1\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\widgetDock_hdlHier_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\widgetDock_hdlHier_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\widgetDock_hdlHier_1\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\widgetDock_messageWindow_1\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\widgetDock_messageWindow_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\widgetDock_messageWindow_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\widgetDock_messageWindow_1\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\widgetDock_hdlSrc_1\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\widgetDock_hdlSrc_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\widgetDock_hdlSrc_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\widgetDock_hdlSrc_1\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\widgetDock_signalList_1\isVisible=false +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\widgetDock_svtbHier_1\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\widgetDock_svtbHier_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\widgetDock_svtbHier_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\widgetDock_svtbHier_1\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\windowDock_OneSearch_1\isNestedWindow=1 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\windowDock_OneSearch_1\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\windowDock_OneSearch_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\windowDock_OneSearch_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\windowDock_OneSearch_1\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\windowDock_nWave_1\isNestedWindow=1 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\windowDock_nWave_1\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\windowDock_nWave_1\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\windowDock_nWave_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\windowDock_nWave_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\windowDock_nWave_1\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\windowDock_nSchema_1\isNestedWindow=1 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\windowDock_nSchema_1\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\windowDock_nSchema_1\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\windowDock_nSchema_1\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\windowDock_nSchema_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\windowDock_nSchema_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\windowDock_nSchema_1\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\windowDock_nSchema_2\isNestedWindow=1 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\windowDock_nSchema_2\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\windowDock_nSchema_2\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\windowDock_nSchema_2\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\windowDock_nSchema_2\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\windowDock_nSchema_2\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\windowDock_nSchema_2\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\windowDock_nSchema_3\isNestedWindow=1 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\windowDock_nSchema_3\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\windowDock_nSchema_3\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\windowDock_nSchema_3\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\windowDock_nSchema_3\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\windowDock_nSchema_3\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\windowDock_nSchema_3\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\ProductVersion=201809 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\Layout="@ByteArray(\0\0\0\xff\0\0\0\0\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x2\x13\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x3H\0\0\0\x89\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x2\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0h\0\x64\0l\0H\0i\0\x65\0r\0_\0\x31\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0*\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0s\0v\0t\0\x62\0H\0i\0\x65\0r\0_\0\x31\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0s\0i\0g\0n\0\x61\0l\0L\0i\0s\0t\0_\0\x31\0\0\0\0\xe9\0\0\0\xc6\0\0\0k\0\0\0k\xfc\0\0\x3N\0\0\x6\xb2\0\0\0\xbf\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x4\xfb\0\0\0&\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0h\0\x64\0l\0S\0r\0\x63\0_\0\x31\x1\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x31\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x33\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\0\0\0\x3\0\0\n\0\0\0\x2\xd2\xfc\x1\0\0\0\x1\xfc\0\0\0\0\0\0\n\0\0\0\x2,\0\xff\xff\xff\xfa\0\0\0\x2\x1\0\0\0\x3\xfb\0\0\0\x34\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0m\0\x65\0s\0s\0\x61\0g\0\x65\0W\0i\0n\0\x64\0o\0w\0_\0\x31\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0,\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\0_\0\x31\x1\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x31\x1\0\0\0\0\xff\xff\xff\xff\0\0\x1[\0\xff\xff\xff\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x3\x16\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\isNestedWindow=0 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\size=@Size(2560 1337) +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\geometry_x=-1 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\geometry_y=27 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\geometry_width=2560 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\geometry_height=1337 +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\ProductVersion=201809 +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\Layout="@ByteArray(\0\0\0\xff\0\0\0\0\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x2\xf2\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x3P\0\0\0\x89\0\xff\xff\xff\xfa\0\0\0\x1\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\x2\xc7\0\0\x1\xa8\0\0\0k\0\0\0k\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\x1\0\0\x3V\0\0\x6\xaa\0\0\0k\0\xff\xff\xff\0\0\0\x3\0\0\n\0\0\0\x1\xd8\xfc\x1\0\0\0\x1\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\x1\0\0\0\0\0\0\n\0\0\0\0\xa0\0\xff\xff\xff\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x3\x16\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x3\x1e\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\x1f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x43\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3g\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\isNestedWindow=0 +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\size=@Size(2560 1337) +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\geometry_x=-1 +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\geometry_y=27 +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\geometry_width=2560 +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\geometry_height=1337 +Verdi_1\qBaseWindowNextStateGroup\0\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\0\ProductVersion=201809 +Verdi_1\qBaseWindowNextStateGroup\0\Layout="@ByteArray(\0\0\0\xff\0\0\0\0\xfd\0\0\0\x2\0\0\0\x2\0\0\x3U\0\0\0\x94\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x1\x17\0\0\0\x89\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\xe9\0\0\0\xc6\0\0\0k\0\0\0k\xfc\0\0\x1\x1d\0\0\x2\x38\0\0\0k\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x4\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\x1\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x33\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x34\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x35\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x3\0\0\x3U\0\0\x1T\xfc\x1\0\0\0\x1\xfc\0\0\0\0\0\0\x3U\0\0\0\xa0\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x3\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\x3U\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowNextStateGroup\0\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\0\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\0\size=@Size(853 572) +Verdi_1\qBaseWindowNextStateGroup\0\geometry_x=-1 +Verdi_1\qBaseWindowNextStateGroup\0\geometry_y=27 +Verdi_1\qBaseWindowNextStateGroup\0\geometry_width=853 +Verdi_1\qBaseWindowNextStateGroup\0\geometry_height=572 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\ProductVersion=201809 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\Layout="@ByteArray(\0\0\0\xff\0\0\0\0\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x1\xfa\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x2\x1d\0\0\0\x89\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\xe9\0\0\0\xc6\0\0\0k\0\0\0k\xfc\0\0\x2#\0\0\a\xdd\0\0\0k\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x4\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\x1\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x33\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x34\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x35\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x3\0\0\n\0\0\0\x2\xeb\xfc\x1\0\0\0\x1\xfc\0\0\0\0\0\0\n\0\0\0\x2,\0\xff\xff\xff\xfa\0\0\0\x2\x1\0\0\0\x3\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\x1\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\x1[\0\xff\xff\xff\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\isNestedWindow=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\size=@Size(2560 1337) +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\geometry_x=-1 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\geometry_y=27 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\geometry_width=2560 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\geometry_height=1337 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_OneSearch\isNestedWindow=1 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_OneSearch\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_OneSearch\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\1\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_OneSearch\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_OneSearch\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_OneSearch\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\1\ProductVersion=201809 +Verdi_1\qBaseWindowNextStateGroup\1\Layout="@ByteArray(\0\0\0\xff\0\0\0\x1\xfd\0\0\0\x2\0\0\0\x2\0\0\x3U\0\0\0{\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x1\x17\0\0\0\x89\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\xe9\0\0\0\xc6\0\0\0k\0\0\0k\xfc\0\0\x1\x1d\0\0\x2\x38\0\0\0k\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x4\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\x1\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x33\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x34\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x35\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x3\0\0\x3U\0\0\x1m\xfc\x1\0\0\0\x1\xfc\0\0\0\0\0\0\x3U\0\0\x2,\0\xff\xff\xff\xfa\0\0\0\x2\x1\0\0\0\x3\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\x1\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\0\0\x3U\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowNextStateGroup\1\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\1\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\1\size=@Size(853 572) +Verdi_1\qBaseWindowNextStateGroup\1\geometry_x=-1 +Verdi_1\qBaseWindowNextStateGroup\1\geometry_y=27 +Verdi_1\qBaseWindowNextStateGroup\1\geometry_width=853 +Verdi_1\qBaseWindowNextStateGroup\1\geometry_height=572 +Verdi_1\qBaseWindowNextStateGroup\2\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\windowDock_OneSearch\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\windowDock_OneSearch\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\2\ProductVersion=201809 +Verdi_1\qBaseWindowNextStateGroup\2\Layout="@ByteArray(\0\0\0\xff\0\0\0\x2\xfd\0\0\0\x2\0\0\0\x2\0\0\x3U\0\0\0{\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x1\x17\0\0\0\x89\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\xe9\0\0\0\xc6\0\0\0k\0\0\0k\xfc\0\0\x1\x1d\0\0\x2\x38\0\0\0k\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x4\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\x1\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x33\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x34\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x35\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x3\0\0\x3U\0\0\x1m\xfc\x1\0\0\0\x1\xfc\0\0\0\0\0\0\x3U\0\0\0\xa0\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x3\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\0\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\0\0k\0\0\x3U\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowNextStateGroup\2\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\2\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\2\size=@Size(853 572) +Verdi_1\qBaseWindowNextStateGroup\2\geometry_x=-1 +Verdi_1\qBaseWindowNextStateGroup\2\geometry_y=27 +Verdi_1\qBaseWindowNextStateGroup\2\geometry_width=853 +Verdi_1\qBaseWindowNextStateGroup\2\geometry_height=572 +Verdi_1\qBaseWindowNextStateGroup\3\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\windowDock_OneSearch\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\windowDock_OneSearch\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\windowDock_OneSearch\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\3\ProductVersion=201809 +Verdi_1\qBaseWindowNextStateGroup\3\Layout="@ByteArray(\0\0\0\xff\0\0\0\x3\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x3x\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x3I\0\0\0\x89\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\xe9\0\0\0\xc6\0\0\0k\0\0\0k\xfc\0\0\x3O\0\0\x6\xb1\0\0\0k\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x4\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\x1\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x33\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x34\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x35\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x3\0\0\n\0\0\0\x1m\xfc\x1\0\0\0\x1\xfc\0\0\0\0\0\0\n\0\0\0\x2,\0\xff\xff\xff\xfa\0\0\0\x2\x1\0\0\0\x3\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\x1\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowNextStateGroup\3\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\3\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\3\size=@Size(2560 1337) +Verdi_1\qBaseWindowNextStateGroup\3\geometry_x=-1 +Verdi_1\qBaseWindowNextStateGroup\3\geometry_y=27 +Verdi_1\qBaseWindowNextStateGroup\3\geometry_width=2560 +Verdi_1\qBaseWindowNextStateGroup\3\geometry_height=1337 +Verdi_1\qBaseWindowNextStateGroup\4\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\windowDock_OneSearch\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\windowDock_OneSearch\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\windowDock_OneSearch\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\4\ProductVersion=201809 +Verdi_1\qBaseWindowNextStateGroup\4\Layout="@ByteArray(\0\0\0\xff\0\0\0\x4\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x3x\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x3I\0\0\0\x89\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\xe9\0\0\0\xc6\0\0\0k\0\0\0k\xfc\0\0\x3O\0\0\x6\xb1\0\0\0k\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x4\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\x1\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x33\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x34\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x35\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x3\0\0\n\0\0\0\x1m\xfc\x1\0\0\0\x1\xfc\0\0\0\0\0\0\n\0\0\0\x2,\0\xff\xff\xff\xfa\0\0\0\x2\x1\0\0\0\x3\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\x1\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowNextStateGroup\4\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\4\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\4\size=@Size(2560 1337) +Verdi_1\qBaseWindowNextStateGroup\4\geometry_x=-1 +Verdi_1\qBaseWindowNextStateGroup\4\geometry_y=27 +Verdi_1\qBaseWindowNextStateGroup\4\geometry_width=2560 +Verdi_1\qBaseWindowNextStateGroup\4\geometry_height=1337 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nWave_2\isNestedWindow=1 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nWave_2\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nWave_2\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nWave_2\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\5\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nWave_2\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_OneSearch\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_OneSearch\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_OneSearch\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nWave_2\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nWave_2\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nWave_2\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nWave_2\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nWave_2\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\5\ProductVersion=201809 +Verdi_1\qBaseWindowNextStateGroup\5\Layout="@ByteArray(\0\0\0\xff\0\0\0\x5\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x3x\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x3I\0\0\0\x89\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\xe9\0\0\0\xc6\0\0\0k\0\0\0k\xfc\0\0\x3O\0\0\x6\xb1\0\0\0k\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x4\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\x1\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x33\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x34\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x35\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x3\0\0\n\0\0\0\x1m\xfc\x1\0\0\0\x1\xfc\0\0\0\0\0\0\n\0\0\0\x2,\0\xff\xff\xff\xfa\0\0\0\x2\x1\0\0\0\x3\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\x1\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\x1\xd5\0\xff\xff\xff\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowNextStateGroup\5\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\5\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\5\size=@Size(2560 1337) +Verdi_1\qBaseWindowNextStateGroup\5\geometry_x=-1 +Verdi_1\qBaseWindowNextStateGroup\5\geometry_y=27 +Verdi_1\qBaseWindowNextStateGroup\5\geometry_width=2560 +Verdi_1\qBaseWindowNextStateGroup\5\geometry_height=1337 +Verdi_1\qBaseWindowNextStateGroup\6\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\windowDock_OneSearch\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\windowDock_OneSearch\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\windowDock_nWave_2\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\windowDock_nWave_2\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\windowDock_nWave_2\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\windowDock_nWave_2\qBaseWindowBeMax=1 +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\windowDock_nWave_2\qBaseWindowBeFix=1 +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\windowDock_nWave_2\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\6\ProductVersion=201809 +Verdi_1\qBaseWindowNextStateGroup\6\Layout="@ByteArray(\0\0\0\xff\0\0\0\x6\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x3x\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x3I\0\0\0\0\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\xe9\0\0\0\xc6\0\0\0k\0\0\0k\xfc\0\0\x3O\0\0\x6\xb1\0\0\0\0\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x4\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\0\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x33\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x34\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x35\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x3\0\0\n\0\0\0\x1m\xfc\x1\0\0\0\x1\xfc\0\0\0\0\0\0\n\0\0\0\x1-\0\xff\xff\xff\xfa\0\0\0\x2\x1\0\0\0\x3\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\0\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\x1-\0\xff\xff\xff\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowNextStateGroup\6\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\6\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\6\size=@Size(2560 1337) +Verdi_1\qBaseWindowNextStateGroup\6\geometry_x=-1 +Verdi_1\qBaseWindowNextStateGroup\6\geometry_y=27 +Verdi_1\qBaseWindowNextStateGroup\6\geometry_width=2560 +Verdi_1\qBaseWindowNextStateGroup\6\geometry_height=1337 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nWave_2\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\7\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_OneSearch\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_OneSearch\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_OneSearch\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_nWave_2\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_nWave_2\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_nWave_2\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_nWave_2\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_nWave_2\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_nWave_2\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\7\ProductVersion=201809 +Verdi_1\qBaseWindowNextStateGroup\7\Layout="@ByteArray(\0\0\0\xff\0\0\0\a\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x3x\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x3I\0\0\0\x89\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\xe9\0\0\0\xc6\0\0\0k\0\0\0k\xfc\0\0\x3O\0\0\x6\xb1\0\0\0k\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x4\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\x1\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x33\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x34\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x35\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x3\0\0\n\0\0\0\x1m\xfc\x1\0\0\0\x1\xfc\0\0\0\0\0\0\n\0\0\0\x2,\0\xff\xff\xff\xfa\0\0\0\x2\x1\0\0\0\x3\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\x1\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\x1-\0\xff\xff\xff\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowNextStateGroup\7\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\7\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\7\size=@Size(2560 1337) +Verdi_1\qBaseWindowNextStateGroup\7\geometry_x=-1 +Verdi_1\qBaseWindowNextStateGroup\7\geometry_y=27 +Verdi_1\qBaseWindowNextStateGroup\7\geometry_width=2560 +Verdi_1\qBaseWindowNextStateGroup\7\geometry_height=1337 +Verdi_1\qBaseWindowNextStateGroup\8\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\windowDock_OneSearch\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\windowDock_OneSearch\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\windowDock_nWave_2\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\windowDock_nWave_2\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\windowDock_nWave_2\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\windowDock_nWave_2\qBaseWindowBeMax=1 +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\windowDock_nWave_2\qBaseWindowBeFix=1 +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\windowDock_nWave_2\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\8\ProductVersion=201809 +Verdi_1\qBaseWindowNextStateGroup\8\Layout="@ByteArray(\0\0\0\xff\0\0\0\b\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x1\xfa\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x2\x1d\0\0\0\0\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\xe9\0\0\0\xc6\0\0\0k\0\0\0k\xfc\0\0\x2#\0\0\a\xdd\0\0\0\0\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x4\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\0\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x33\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x34\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x35\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x3\0\0\n\0\0\0\x2\xeb\xfc\x1\0\0\0\x1\xfc\0\0\0\0\0\0\n\0\0\0\x1[\0\xff\xff\xff\xfa\0\0\0\x2\x1\0\0\0\x3\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\0\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\x1[\0\xff\xff\xff\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowNextStateGroup\8\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\8\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\8\size=@Size(2560 1337) +Verdi_1\qBaseWindowNextStateGroup\8\geometry_x=-1 +Verdi_1\qBaseWindowNextStateGroup\8\geometry_y=27 +Verdi_1\qBaseWindowNextStateGroup\8\geometry_width=2560 +Verdi_1\qBaseWindowNextStateGroup\8\geometry_height=1337 +Verdi_1\qBaseWindowNextStateGroup\9\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\windowDock_OneSearch\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\windowDock_OneSearch\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\windowDock_OneSearch\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\windowDock_nWave_2\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\windowDock_nWave_2\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\windowDock_nWave_2\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\windowDock_nWave_2\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\windowDock_nWave_2\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\windowDock_nWave_2\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\9\ProductVersion=201809 +Verdi_1\qBaseWindowNextStateGroup\9\Layout="@ByteArray(\0\0\0\xff\0\0\0\t\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x1\xfa\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x2\x1d\0\0\0\x89\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\xe9\0\0\0\xc6\0\0\0k\0\0\0k\xfc\0\0\x2#\0\0\a\xdd\0\0\0k\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x4\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\x1\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x33\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x34\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x35\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x3\0\0\n\0\0\0\x2\xeb\xfc\x1\0\0\0\x1\xfc\0\0\0\0\0\0\n\0\0\0\x2,\0\xff\xff\xff\xfa\0\0\0\x2\x1\0\0\0\x3\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\x1\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\x1[\0\xff\xff\xff\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowNextStateGroup\9\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\9\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\9\size=@Size(2560 1337) +Verdi_1\qBaseWindowNextStateGroup\9\geometry_x=-1 +Verdi_1\qBaseWindowNextStateGroup\9\geometry_y=27 +Verdi_1\qBaseWindowNextStateGroup\9\geometry_width=2560 +Verdi_1\qBaseWindowNextStateGroup\9\geometry_height=1337 + +[qBaseWindow_saveRestoreSession_group] +10=/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/chip_top/verdiLog/novas_autosave.ses + +[qDockerWindow_C] +Verdi_1\position.x=-1 +Verdi_1\position.y=27 +Verdi_1\width=2560 +Verdi_1\height=1337 diff --git a/tb/chip_top/verdiLog/.74196IC_EDA.conf b/tb/chip_top/verdiLog/.74196IC_EDA.conf new file mode 100644 index 0000000..d755d45 --- /dev/null +++ b/tb/chip_top/verdiLog/.74196IC_EDA.conf @@ -0,0 +1,2261 @@ +[qBaseWindowStateGroup] +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\ProductVersion=201809 +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\Layout="@ByteArray(\0\0\0\xff\0\0\0\0\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x2\xf2\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x3P\0\0\0\x89\0\xff\xff\xff\xfa\0\0\0\x1\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\x2\xc7\0\0\x1\xa8\0\0\0k\0\0\0k\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\x1\0\0\x3V\0\0\x6\xaa\0\0\0k\0\xff\xff\xff\0\0\0\x3\0\0\n\0\0\0\x1\xd8\xfc\x1\0\0\0\x1\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\x1\0\0\0\0\0\0\n\0\0\0\0\xa0\0\xff\xff\xff\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x3\x16\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x3\x1e\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\x1f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x43\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3g\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\isNestedWindow=0 +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\size=@Size(2560 1337) +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\geometry_x=-1 +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\geometry_y=27 +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\geometry_width=2560 +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\geometry_height=1337 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=false +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=false +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=false +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=false +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\ProductVersion=201809 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\Layout="@ByteArray(\0\0\0\xff\0\0\0\0\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x4\xeb\xfc\x1\0\0\0\x4\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x33\0\0\0\0\0\0\0\n\0\0\0\0\x80\0\xff\xff\xff\xfc\0\0\0\0\0\0\x2\\\0\0\0\0\0\xff\xff\xff\xfa\xff\xff\xff\xff\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfc\0\0\x2\x62\0\0\0\xb7\0\0\0\0\0\xff\xff\xff\xfa\xff\xff\xff\xff\x1\0\0\0\x2\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\0\0k\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0h\0\x65\0r\0i\0t\0\x61\0n\0\x63\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xae\0\xff\xff\xff\xfc\0\0\x3\x1f\0\0\x6\xe1\0\0\0\0\0\xff\xff\xff\xfa\0\0\0\x5\x1\0\0\0\b\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\0\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x34\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x35\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x36\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x37\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x32\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x38\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x39\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\0\0\0\x3\0\0\n\0\0\0\x4\xeb\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\n\0\0\0\0\0\0\xff\xff\xff\xfa\0\0\0\x2\x1\0\0\0\x3\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\0\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x33\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x34\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\isNestedWindow=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\size=@Size(2560 1337) +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\geometry_x=-1 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\geometry_y=27 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\geometry_width=2560 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\geometry_height=1337 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_OneSearch\isNestedWindow=1 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_OneSearch\isVisible=false +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_OneSearch\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nWave_2\isNestedWindow=1 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nWave_2\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nWave_2\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nWave_2\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nWave_2\dockIsFloating=false +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qDockerWindow_qDockContentType\Verdi=1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qDockerWindow_qDockContentType\hdlHier=1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qDockerWindow_qDockContentType\hdlSrc=1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qDockerWindow_qDockContentType\messageWindow=1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qDockerWindow_qDockContentType\svtbHier=1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qDockerWindow_qDockContentType\OneSearch=1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qDockerWindowMgr_saveDockerChildList\Verdi_1=7 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qDockerWindowMgr_saveDockerChildList\Verdi_1_0=widgetDock_hdlHier_1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qDockerWindowMgr_saveDockerChildList\Verdi_1_1=widgetDock_messageWindow_1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qDockerWindowMgr_saveDockerChildList\Verdi_1_2=widgetDock_hdlSrc_1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qDockerWindowMgr_saveDockerChildList\Verdi_1_3=widgetDock_signalList_1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qDockerWindowMgr_saveDockerChildList\Verdi_1_4=widgetDock_svtbHier_1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qDockerWindowMgr_saveDockerChildList\Verdi_1_5=windowDock_OneSearch_1 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\widgetDock_hdlHier_1\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\widgetDock_hdlHier_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\widgetDock_hdlHier_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\widgetDock_hdlHier_1\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\widgetDock_messageWindow_1\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\widgetDock_messageWindow_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\widgetDock_messageWindow_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\widgetDock_messageWindow_1\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\widgetDock_hdlSrc_1\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\widgetDock_hdlSrc_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\widgetDock_hdlSrc_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\widgetDock_hdlSrc_1\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\widgetDock_signalList_1\isVisible=false +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\widgetDock_svtbHier_1\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\widgetDock_svtbHier_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\widgetDock_svtbHier_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\widgetDock_svtbHier_1\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\windowDock_OneSearch_1\isNestedWindow=1 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\windowDock_OneSearch_1\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\windowDock_OneSearch_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\windowDock_OneSearch_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\windowDock_OneSearch_1\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\windowDock_nWave_1\isNestedWindow=1 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\windowDock_nWave_1\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\windowDock_nWave_1\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\windowDock_nWave_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\windowDock_nWave_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\windowDock_nWave_1\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\ProductVersion=201809 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\Layout="@ByteArray(\0\0\0\xff\0\0\0\0\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x2\xcb\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x2\x8d\0\0\0\x89\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x2\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0h\0\x64\0l\0H\0i\0\x65\0r\0_\0\x31\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0*\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0s\0v\0t\0\x62\0H\0i\0\x65\0r\0_\0\x31\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0s\0i\0g\0n\0\x61\0l\0L\0i\0s\0t\0_\0\x31\0\0\0\0\xe9\0\0\0\xc6\0\0\0k\0\0\0k\xfb\0\0\0&\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0h\0\x64\0l\0S\0r\0\x63\0_\0\x31\x1\0\0\x2\x93\0\0\am\0\0\0k\0\xff\xff\xff\0\0\0\x3\0\0\n\0\0\0\x2\x1a\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\n\0\0\0\x2,\0\xff\xff\xff\xfa\0\0\0\x2\x1\0\0\0\x3\xfb\0\0\0\x34\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0m\0\x65\0s\0s\0\x61\0g\0\x65\0W\0i\0n\0\x64\0o\0w\0_\0\x31\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0,\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\0_\0\x31\x1\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x31\x1\0\0\0\0\xff\xff\xff\xff\0\0\x1-\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x33\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x34\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\isNestedWindow=0 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\size=@Size(2560 1337) +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\geometry_x=-1 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\geometry_y=27 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\geometry_width=2560 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\geometry_height=1337 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nWave_2\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nMemory_3\isNestedWindow=1 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nMemory_3\isVisible=false +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nMemory_3\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nMemory_3\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nMemory_3\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nMemory_4\isNestedWindow=1 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nMemory_4\isVisible=false +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nMemory_4\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nMemory_4\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nMemory_4\dockIsFloating=false +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qDockerWindow_qDockContentType\nWave=1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qDockerWindowMgr_saveDockerChildList\Verdi_1_6=windowDock_nWave_1 +Verdi_1\qBaseWindowNextStateGroup\0\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\0\ProductVersion=201809 +Verdi_1\qBaseWindowNextStateGroup\0\Layout="@ByteArray(\0\0\0\xff\0\0\0\x1e\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x3\xb3\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x2\\\0\0\0\0\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfc\0\0\x2\x62\0\0\0\xb7\0\0\0\0\0\xff\xff\xff\xfa\0\0\0\x1\x1\0\0\0\x2\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\0\0k\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0h\0\x65\0r\0i\0t\0\x61\0n\0\x63\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xae\0\xff\xff\xff\xfc\0\0\x3\x1f\0\0\x6\xe1\0\0\0\0\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\b\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\0\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x34\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x35\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x36\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x37\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x32\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x38\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x39\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\0\0\0\x3\0\0\n\0\0\0\x1\x32\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\n\0\0\0\x1[\0\xff\xff\xff\xfa\0\0\0\x3\x1\0\0\0\x4\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\0\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x33\x1\0\0\0\0\xff\xff\xff\xff\0\0\x1[\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x33\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x34\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowNextStateGroup\0\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\0\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\0\size=@Size(2560 1337) +Verdi_1\qBaseWindowNextStateGroup\0\geometry_x=-1 +Verdi_1\qBaseWindowNextStateGroup\0\geometry_y=27 +Verdi_1\qBaseWindowNextStateGroup\0\geometry_width=2560 +Verdi_1\qBaseWindowNextStateGroup\0\geometry_height=1337 +Verdi_1\qBaseWindowNextStateGroup\1\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_OneSearch\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_OneSearch\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_OneSearch\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\1\ProductVersion=201809 +Verdi_1\qBaseWindowNextStateGroup\1\Layout="@ByteArray(\0\0\0\xff\0\0\0\x1f\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x3\xb3\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x2\\\0\0\0\x89\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfc\0\0\x2\x62\0\0\0\xb7\0\0\0\xae\0\xff\xff\xff\xfa\0\0\0\x1\x1\0\0\0\x2\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\0\0k\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0h\0\x65\0r\0i\0t\0\x61\0n\0\x63\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xae\0\xff\xff\xff\xfc\0\0\x3\x1f\0\0\x6\xe1\0\0\0\xbf\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\b\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\x1\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x34\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x35\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x36\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x37\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x32\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x38\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x39\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\0\0\0\x3\0\0\n\0\0\0\x1\x32\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\n\0\0\0\x2,\0\xff\xff\xff\xfa\0\0\0\x3\x1\0\0\0\x4\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\x1\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x33\x1\0\0\0\0\xff\xff\xff\xff\0\0\x1[\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x33\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x34\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowNextStateGroup\1\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\1\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\1\size=@Size(2560 1337) +Verdi_1\qBaseWindowNextStateGroup\1\geometry_x=-1 +Verdi_1\qBaseWindowNextStateGroup\1\geometry_y=27 +Verdi_1\qBaseWindowNextStateGroup\1\geometry_width=2560 +Verdi_1\qBaseWindowNextStateGroup\1\geometry_height=1337 +Verdi_1\qBaseWindowNextStateGroup\2\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\windowDock_OneSearch\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\windowDock_OneSearch\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\2\ProductVersion=201809 +Verdi_1\qBaseWindowNextStateGroup\2\Layout="@ByteArray(\0\0\0\xff\0\0\0 \xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x3\xb3\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x2\\\0\0\0\0\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfc\0\0\x2\x62\0\0\0\xb7\0\0\0\0\0\xff\xff\xff\xfa\0\0\0\x1\x1\0\0\0\x2\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\0\0k\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0h\0\x65\0r\0i\0t\0\x61\0n\0\x63\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xae\0\xff\xff\xff\xfc\0\0\x3\x1f\0\0\x6\xe1\0\0\0\0\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\b\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\0\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x34\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x35\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x36\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x37\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x32\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x38\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x39\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\0\0\0\x3\0\0\n\0\0\0\x1\x32\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\n\0\0\0\x1[\0\xff\xff\xff\xfa\0\0\0\x3\x1\0\0\0\x4\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\0\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x33\x1\0\0\0\0\xff\xff\xff\xff\0\0\x1[\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x33\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x34\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowNextStateGroup\2\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\2\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\2\size=@Size(2560 1337) +Verdi_1\qBaseWindowNextStateGroup\2\geometry_x=-1 +Verdi_1\qBaseWindowNextStateGroup\2\geometry_y=27 +Verdi_1\qBaseWindowNextStateGroup\2\geometry_width=2560 +Verdi_1\qBaseWindowNextStateGroup\2\geometry_height=1337 +Verdi_1\qBaseWindowNextStateGroup\3\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeMax=1 +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\windowDock_OneSearch\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\windowDock_OneSearch\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\windowDock_OneSearch\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\3\ProductVersion=201809 +Verdi_1\qBaseWindowNextStateGroup\3\Layout="@ByteArray(\0\0\0\xff\0\0\0!\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x3\xb3\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x2\\\0\0\0\0\0\xff\xff\xff\xfa\xff\xff\xff\xff\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfc\0\0\x2\x62\0\0\0\xb7\0\0\0\0\0\xff\xff\xff\xfa\xff\xff\xff\xff\x1\0\0\0\x2\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\0\0k\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0h\0\x65\0r\0i\0t\0\x61\0n\0\x63\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xae\0\xff\xff\xff\xfc\0\0\x3\x1f\0\0\x6\xe1\0\0\0\0\0\xff\xff\xff\xfa\0\0\0\x5\x1\0\0\0\b\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\0\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x34\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x35\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x36\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x37\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x32\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x38\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x39\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\0\0\0\x3\0\0\n\0\0\0\x4\xeb\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\n\0\0\0\x1[\0\xff\xff\xff\xfa\0\0\0\x3\x1\0\0\0\x4\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\0\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x33\x1\0\0\0\0\xff\xff\xff\xff\0\0\x1[\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x33\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x34\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowNextStateGroup\3\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\3\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\3\size=@Size(2560 1337) +Verdi_1\qBaseWindowNextStateGroup\3\geometry_x=-1 +Verdi_1\qBaseWindowNextStateGroup\3\geometry_y=27 +Verdi_1\qBaseWindowNextStateGroup\3\geometry_width=2560 +Verdi_1\qBaseWindowNextStateGroup\3\geometry_height=1337 +Verdi_1\qBaseWindowNextStateGroup\4\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeMax=1 +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\windowDock_OneSearch\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\windowDock_OneSearch\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\windowDock_OneSearch\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\4\ProductVersion=201809 +Verdi_1\qBaseWindowNextStateGroup\4\Layout="@ByteArray(\0\0\0\xff\0\0\0\"\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x3\xb3\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x2\\\0\0\0\0\0\xff\xff\xff\xfa\xff\xff\xff\xff\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfc\0\0\x2\x62\0\0\0\xb7\0\0\0\0\0\xff\xff\xff\xfa\xff\xff\xff\xff\x1\0\0\0\x2\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\0\0k\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0h\0\x65\0r\0i\0t\0\x61\0n\0\x63\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xae\0\xff\xff\xff\xfc\0\0\x3\x1f\0\0\x6\xe1\0\0\0\0\0\xff\xff\xff\xfa\0\0\0\x4\x1\0\0\0\a\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x34\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x35\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x36\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x37\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x32\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x38\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x39\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\0\0\0\x3\0\0\n\0\0\0\x4\xeb\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\n\0\0\0\x1[\0\xff\xff\xff\xfa\0\0\0\x3\x1\0\0\0\x5\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\0\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x33\x1\0\0\0\0\xff\xff\xff\xff\0\0\x1[\0\xff\xff\xff\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\0\0\0\0\0\xff\xff\xff\xff\0\0\x6\xe1\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x33\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x34\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowNextStateGroup\4\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\4\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\4\size=@Size(2560 1337) +Verdi_1\qBaseWindowNextStateGroup\4\geometry_x=-1 +Verdi_1\qBaseWindowNextStateGroup\4\geometry_y=27 +Verdi_1\qBaseWindowNextStateGroup\4\geometry_width=2560 +Verdi_1\qBaseWindowNextStateGroup\4\geometry_height=1337 +Verdi_1\qBaseWindowNextStateGroup\5\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_OneSearch\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_OneSearch\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_OneSearch\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nWave_2\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nWave_2\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nWave_2\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nWave_2\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nWave_2\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\5\ProductVersion=201809 +Verdi_1\qBaseWindowNextStateGroup\5\Layout="@ByteArray(\0\0\0\xff\0\0\0#\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x3\xb3\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x2\\\0\0\0\x89\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfc\0\0\x2\x62\0\0\0\xb7\0\0\0\xae\0\xff\xff\xff\xfa\0\0\0\x1\x1\0\0\0\x2\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\0\0k\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0h\0\x65\0r\0i\0t\0\x61\0n\0\x63\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xae\0\xff\xff\xff\xfc\0\0\x3\x1f\0\0\x6\xe1\0\0\0\xbf\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\b\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\x1\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x34\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x35\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x36\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x37\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x32\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x38\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x39\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\0\0\0\x3\0\0\n\0\0\0\x1\x32\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\n\0\0\0\x2,\0\xff\xff\xff\xfa\0\0\0\x3\x1\0\0\0\x4\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\x1\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x33\x1\0\0\0\0\xff\xff\xff\xff\0\0\x1[\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x33\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x34\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowNextStateGroup\5\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\5\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\5\size=@Size(2560 1337) +Verdi_1\qBaseWindowNextStateGroup\5\geometry_x=-1 +Verdi_1\qBaseWindowNextStateGroup\5\geometry_y=27 +Verdi_1\qBaseWindowNextStateGroup\5\geometry_width=2560 +Verdi_1\qBaseWindowNextStateGroup\5\geometry_height=1337 +Verdi_1\qBaseWindowNextStateGroup\6\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\windowDock_OneSearch\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\windowDock_OneSearch\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\windowDock_nWave_2\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\windowDock_nWave_2\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\windowDock_nWave_2\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\windowDock_nWave_2\qBaseWindowBeMax=1 +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\windowDock_nWave_2\qBaseWindowBeFix=1 +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\windowDock_nWave_2\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\6\ProductVersion=201809 +Verdi_1\qBaseWindowNextStateGroup\6\Layout="@ByteArray(\0\0\0\xff\0\0\0$\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x3\xb3\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x2\\\0\0\0\0\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfc\0\0\x2\x62\0\0\0\xb7\0\0\0\0\0\xff\xff\xff\xfa\0\0\0\x1\x1\0\0\0\x2\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\0\0k\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0h\0\x65\0r\0i\0t\0\x61\0n\0\x63\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xae\0\xff\xff\xff\xfc\0\0\x3\x1f\0\0\x6\xe1\0\0\0\0\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\b\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\0\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x34\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x35\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x36\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x37\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x32\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x38\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x39\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\0\0\0\x3\0\0\n\0\0\0\x1\x32\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\n\0\0\0\x1[\0\xff\xff\xff\xfa\0\0\0\x3\x1\0\0\0\x4\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\0\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x33\x1\0\0\0\0\xff\xff\xff\xff\0\0\x1[\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x33\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x34\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowNextStateGroup\6\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\6\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\6\size=@Size(2560 1337) +Verdi_1\qBaseWindowNextStateGroup\6\geometry_x=-1 +Verdi_1\qBaseWindowNextStateGroup\6\geometry_y=27 +Verdi_1\qBaseWindowNextStateGroup\6\geometry_width=2560 +Verdi_1\qBaseWindowNextStateGroup\6\geometry_height=1337 +Verdi_1\qBaseWindowNextStateGroup\7\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_OneSearch\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_OneSearch\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_OneSearch\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\7\ProductVersion=201809 +Verdi_1\qBaseWindowNextStateGroup\7\Layout="@ByteArray(\0\0\0\xff\0\0\0%\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x3\xb3\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x2\\\0\0\0\x89\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfc\0\0\x2\x62\0\0\0\xb7\0\0\0\xae\0\xff\xff\xff\xfa\0\0\0\x1\x1\0\0\0\x2\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\0\0k\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0h\0\x65\0r\0i\0t\0\x61\0n\0\x63\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xae\0\xff\xff\xff\xfc\0\0\x3\x1f\0\0\x6\xe1\0\0\0\xbf\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\b\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\x1\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x34\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x35\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x36\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x37\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x32\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x38\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x39\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\0\0\0\x3\0\0\n\0\0\0\x1\x32\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\n\0\0\0\x2,\0\xff\xff\xff\xfa\0\0\0\x3\x1\0\0\0\x4\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\x1\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x33\x1\0\0\0\0\xff\xff\xff\xff\0\0\x1[\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x33\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x34\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowNextStateGroup\7\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\7\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\7\size=@Size(2560 1337) +Verdi_1\qBaseWindowNextStateGroup\7\geometry_x=-1 +Verdi_1\qBaseWindowNextStateGroup\7\geometry_y=27 +Verdi_1\qBaseWindowNextStateGroup\7\geometry_width=2560 +Verdi_1\qBaseWindowNextStateGroup\7\geometry_height=1337 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nWave_3\isNestedWindow=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nWave_3\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nWave_3\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\8\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\windowDock_OneSearch\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\windowDock_OneSearch\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\windowDock_OneSearch\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\windowDock_nWave_3\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\windowDock_nWave_3\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeMax=1 +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeFix=1 +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\windowDock_nWave_3\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\8\ProductVersion=201809 +Verdi_1\qBaseWindowNextStateGroup\8\Layout="@ByteArray(\0\0\0\xff\0\0\0&\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x3\xb3\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x2\\\0\0\0\0\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfc\0\0\x2\x62\0\0\0\xb7\0\0\0\0\0\xff\xff\xff\xfa\0\0\0\x1\x1\0\0\0\x2\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\0\0k\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0h\0\x65\0r\0i\0t\0\x61\0n\0\x63\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xae\0\xff\xff\xff\xfc\0\0\x3\x1f\0\0\x6\xe1\0\0\0\0\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\b\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\0\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x34\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x35\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x36\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x37\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x32\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x38\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x39\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\0\0\0\x3\0\0\n\0\0\0\x1\x32\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\n\0\0\0\x1[\0\xff\xff\xff\xfa\0\0\0\x3\x1\0\0\0\x4\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\0\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x33\x1\0\0\0\0\xff\xff\xff\xff\0\0\x1[\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x33\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x34\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowNextStateGroup\8\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\8\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\8\size=@Size(2560 1337) +Verdi_1\qBaseWindowNextStateGroup\8\geometry_x=-1 +Verdi_1\qBaseWindowNextStateGroup\8\geometry_y=27 +Verdi_1\qBaseWindowNextStateGroup\8\geometry_width=2560 +Verdi_1\qBaseWindowNextStateGroup\8\geometry_height=1337 +Verdi_1\qBaseWindowNextStateGroup\9\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\windowDock_OneSearch\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\windowDock_OneSearch\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\windowDock_nWave_3\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\windowDock_nWave_3\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\windowDock_nWave_3\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeMax=1 +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeFix=1 +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\windowDock_nWave_3\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\9\ProductVersion=201809 +Verdi_1\qBaseWindowNextStateGroup\9\Layout="@ByteArray(\0\0\0\xff\0\0\0'\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x3\xb3\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x2\\\0\0\0\0\0\xff\xff\xff\xfa\xff\xff\xff\xff\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfc\0\0\x2\x62\0\0\0\xb7\0\0\0\0\0\xff\xff\xff\xfa\xff\xff\xff\xff\x1\0\0\0\x2\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\0\0k\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0h\0\x65\0r\0i\0t\0\x61\0n\0\x63\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xae\0\xff\xff\xff\xfc\0\0\x3\x1f\0\0\x6\xe1\0\0\0\0\0\xff\xff\xff\xfa\0\0\0\x5\x1\0\0\0\b\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\0\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x34\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x35\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x36\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x37\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x32\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x38\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x39\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\0\0\0\x3\0\0\n\0\0\0\x4\xeb\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\n\0\0\0\x1[\0\xff\xff\xff\xfa\0\0\0\x3\x1\0\0\0\x4\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\0\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x33\x1\0\0\0\0\xff\xff\xff\xff\0\0\x1[\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x33\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x34\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowNextStateGroup\9\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\9\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\9\size=@Size(2560 1337) +Verdi_1\qBaseWindowNextStateGroup\9\geometry_x=-1 +Verdi_1\qBaseWindowNextStateGroup\9\geometry_y=27 +Verdi_1\qBaseWindowNextStateGroup\9\geometry_width=2560 +Verdi_1\qBaseWindowNextStateGroup\9\geometry_height=1337 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nWave_3\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\10\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeMax=1 +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\windowDock_OneSearch\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\windowDock_OneSearch\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\windowDock_OneSearch\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\windowDock_nWave_3\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\windowDock_nWave_3\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\windowDock_nWave_3\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeMax=1 +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeFix=1 +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\windowDock_nWave_3\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\10\ProductVersion=201809 +Verdi_1\qBaseWindowNextStateGroup\10\Layout="@ByteArray(\0\0\0\xff\0\0\0(\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x3\xb3\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x2\\\0\0\0\0\0\xff\xff\xff\xfa\xff\xff\xff\xff\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfc\0\0\x2\x62\0\0\0\xb7\0\0\0\0\0\xff\xff\xff\xfa\xff\xff\xff\xff\x1\0\0\0\x2\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\0\0k\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0h\0\x65\0r\0i\0t\0\x61\0n\0\x63\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xae\0\xff\xff\xff\xfc\0\0\x3\x1f\0\0\x6\xe1\0\0\0\0\0\xff\xff\xff\xfa\0\0\0\x4\x1\0\0\0\a\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x34\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x35\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x36\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x37\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x32\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x38\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x39\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\0\0\0\x3\0\0\n\0\0\0\x4\xeb\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\n\0\0\0\x1[\0\xff\xff\xff\xfa\0\0\0\x3\x1\0\0\0\x5\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\0\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x33\x1\0\0\0\0\xff\xff\xff\xff\0\0\x1[\0\xff\xff\xff\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\0\0\0\0\0\xff\xff\xff\xff\0\0\x6\xe1\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x33\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x34\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowNextStateGroup\10\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\10\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\10\size=@Size(2560 1337) +Verdi_1\qBaseWindowNextStateGroup\10\geometry_x=-1 +Verdi_1\qBaseWindowNextStateGroup\10\geometry_y=27 +Verdi_1\qBaseWindowNextStateGroup\10\geometry_width=2560 +Verdi_1\qBaseWindowNextStateGroup\10\geometry_height=1337 +Verdi_1\qBaseWindowNextStateGroup\11\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_OneSearch\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_OneSearch\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_nWave_3\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_nWave_3\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_nWave_3\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_nWave_3\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\11\ProductVersion=201809 +Verdi_1\qBaseWindowNextStateGroup\11\Layout="@ByteArray(\0\0\0\xff\0\0\0)\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x3\xb3\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x2\\\0\0\0\x89\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfc\0\0\x2\x62\0\0\0\xb7\0\0\0\xae\0\xff\xff\xff\xfa\0\0\0\x1\x1\0\0\0\x2\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\0\0k\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0h\0\x65\0r\0i\0t\0\x61\0n\0\x63\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xae\0\xff\xff\xff\xfc\0\0\x3\x1f\0\0\x6\xe1\0\0\0\xbf\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\b\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\x1\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x34\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x35\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x36\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x37\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x32\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x38\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x39\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\0\0\0\x3\0\0\n\0\0\0\x1\x32\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\n\0\0\0\x2,\0\xff\xff\xff\xfa\0\0\0\x3\x1\0\0\0\x4\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\x1\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x33\x1\0\0\0\0\xff\xff\xff\xff\0\0\x1[\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x33\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x34\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowNextStateGroup\11\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\11\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\11\size=@Size(2560 1337) +Verdi_1\qBaseWindowNextStateGroup\11\geometry_x=-1 +Verdi_1\qBaseWindowNextStateGroup\11\geometry_y=27 +Verdi_1\qBaseWindowNextStateGroup\11\geometry_width=2560 +Verdi_1\qBaseWindowNextStateGroup\11\geometry_height=1337 +Verdi_1\qBaseWindowNextStateGroup\12\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\windowDock_OneSearch\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\windowDock_OneSearch\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\windowDock_OneSearch\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\windowDock_nWave_3\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\windowDock_nWave_3\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\windowDock_nWave_3\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeMax=1 +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeFix=1 +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\windowDock_nWave_3\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\12\ProductVersion=201809 +Verdi_1\qBaseWindowNextStateGroup\12\Layout="@ByteArray(\0\0\0\xff\0\0\0*\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x3\xb3\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x2\\\0\0\0\0\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfc\0\0\x2\x62\0\0\0\xb7\0\0\0\0\0\xff\xff\xff\xfa\0\0\0\x1\x1\0\0\0\x2\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\0\0k\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0h\0\x65\0r\0i\0t\0\x61\0n\0\x63\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xae\0\xff\xff\xff\xfc\0\0\x3\x1f\0\0\x6\xe1\0\0\0\0\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\b\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\0\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x34\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x35\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x36\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x37\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x32\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x38\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x39\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\0\0\0\x3\0\0\n\0\0\0\x1\x32\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\n\0\0\0\x1[\0\xff\xff\xff\xfa\0\0\0\x3\x1\0\0\0\x4\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\0\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x33\x1\0\0\0\0\xff\xff\xff\xff\0\0\x1[\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x33\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x34\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowNextStateGroup\12\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\12\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\12\size=@Size(2560 1337) +Verdi_1\qBaseWindowNextStateGroup\12\geometry_x=-1 +Verdi_1\qBaseWindowNextStateGroup\12\geometry_y=27 +Verdi_1\qBaseWindowNextStateGroup\12\geometry_width=2560 +Verdi_1\qBaseWindowNextStateGroup\12\geometry_height=1337 +Verdi_1\qBaseWindowNextStateGroup\13\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_OneSearch\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_OneSearch\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_nWave_3\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_nWave_3\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_nWave_3\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_nWave_3\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\13\ProductVersion=201809 +Verdi_1\qBaseWindowNextStateGroup\13\Layout="@ByteArray(\0\0\0\xff\0\0\0+\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x3\xb3\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x2\\\0\0\0\x89\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfc\0\0\x2\x62\0\0\0\xb7\0\0\0\xae\0\xff\xff\xff\xfa\0\0\0\x1\x1\0\0\0\x2\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\0\0k\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0h\0\x65\0r\0i\0t\0\x61\0n\0\x63\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xae\0\xff\xff\xff\xfc\0\0\x3\x1f\0\0\x6\xe1\0\0\0\xbf\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\b\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\x1\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x34\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x35\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x36\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x37\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x32\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x38\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x39\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\0\0\0\x3\0\0\n\0\0\0\x1\x32\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\n\0\0\0\x2,\0\xff\xff\xff\xfa\0\0\0\x3\x1\0\0\0\x4\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\x1\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x33\x1\0\0\0\0\xff\xff\xff\xff\0\0\x1[\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x33\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x34\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowNextStateGroup\13\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\13\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\13\size=@Size(2560 1337) +Verdi_1\qBaseWindowNextStateGroup\13\geometry_x=-1 +Verdi_1\qBaseWindowNextStateGroup\13\geometry_y=27 +Verdi_1\qBaseWindowNextStateGroup\13\geometry_width=2560 +Verdi_1\qBaseWindowNextStateGroup\13\geometry_height=1337 +Verdi_1\qBaseWindowNextStateGroup\14\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowNextStateGroup\14\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\14\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\14\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\14\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\14\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\14\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\14\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\14\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\14\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\14\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\14\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\14\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\14\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\14\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\14\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\14\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\14\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\14\qBaseDockWidgetGroup\windowDock_OneSearch\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\14\qBaseDockWidgetGroup\windowDock_OneSearch\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\14\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\14\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\14\qBaseDockWidgetGroup\windowDock_OneSearch\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\14\qBaseDockWidgetGroup\windowDock_nWave_3\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\14\qBaseDockWidgetGroup\windowDock_nWave_3\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\14\qBaseDockWidgetGroup\windowDock_nWave_3\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\14\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeMax=1 +Verdi_1\qBaseWindowNextStateGroup\14\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeFix=1 +Verdi_1\qBaseWindowNextStateGroup\14\qBaseDockWidgetGroup\windowDock_nWave_3\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\14\ProductVersion=201809 +Verdi_1\qBaseWindowNextStateGroup\14\Layout="@ByteArray(\0\0\0\xff\0\0\0,\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x3\xb3\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x2\\\0\0\0\0\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfc\0\0\x2\x62\0\0\0\xb7\0\0\0\0\0\xff\xff\xff\xfa\0\0\0\x1\x1\0\0\0\x2\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\0\0k\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0h\0\x65\0r\0i\0t\0\x61\0n\0\x63\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xae\0\xff\xff\xff\xfc\0\0\x3\x1f\0\0\x6\xe1\0\0\0\0\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\b\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\0\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x34\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x35\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x36\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x37\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x32\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x38\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x39\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\0\0\0\x3\0\0\n\0\0\0\x1\x32\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\n\0\0\0\x1[\0\xff\xff\xff\xfa\0\0\0\x3\x1\0\0\0\x4\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\0\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x33\x1\0\0\0\0\xff\xff\xff\xff\0\0\x1[\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x33\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x34\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowNextStateGroup\14\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\14\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\14\size=@Size(2560 1337) +Verdi_1\qBaseWindowNextStateGroup\14\geometry_x=-1 +Verdi_1\qBaseWindowNextStateGroup\14\geometry_y=27 +Verdi_1\qBaseWindowNextStateGroup\14\geometry_width=2560 +Verdi_1\qBaseWindowNextStateGroup\14\geometry_height=1337 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_4\isNestedWindow=1 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_4\isVisible=false +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_4\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_4\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_4\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_4\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_4\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\15\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowNextStateGroup\15\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\15\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\15\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\15\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\15\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\15\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\15\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\15\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\15\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\15\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\15\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\15\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\15\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\15\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\15\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\15\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\15\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\15\qBaseDockWidgetGroup\windowDock_OneSearch\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\15\qBaseDockWidgetGroup\windowDock_OneSearch\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\15\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\15\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\15\qBaseDockWidgetGroup\windowDock_OneSearch\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\15\qBaseDockWidgetGroup\windowDock_nWave_3\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\15\qBaseDockWidgetGroup\windowDock_nWave_3\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\15\qBaseDockWidgetGroup\windowDock_nWave_3\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\15\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\15\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\15\qBaseDockWidgetGroup\windowDock_nWave_3\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\15\qBaseDockWidgetGroup\windowDock_nSchema_4\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\15\qBaseDockWidgetGroup\windowDock_nSchema_4\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\15\qBaseDockWidgetGroup\windowDock_nSchema_4\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\15\qBaseDockWidgetGroup\windowDock_nSchema_4\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\15\qBaseDockWidgetGroup\windowDock_nSchema_4\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\15\qBaseDockWidgetGroup\windowDock_nSchema_4\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\15\qBaseDockWidgetGroup\windowDock_nSchema_4\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\15\ProductVersion=201809 +Verdi_1\qBaseWindowNextStateGroup\15\Layout="@ByteArray(\0\0\0\xff\0\0\0-\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x4\xeb\xfc\x1\0\0\0\x4\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x33\x2\xff\xff\xff\x8a\0\0\0v\0\0\n\0\0\0\x4\xec\xfc\0\0\0\0\0\0\x2\\\0\0\0\0\0\xff\xff\xff\xfa\xff\xff\xff\xff\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfc\0\0\x2\x62\0\0\0\xb7\0\0\0\0\0\xff\xff\xff\xfa\xff\xff\xff\xff\x1\0\0\0\x2\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\0\0k\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0h\0\x65\0r\0i\0t\0\x61\0n\0\x63\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xae\0\xff\xff\xff\xfc\0\0\x3\x1f\0\0\x6\xe1\0\0\0\0\0\xff\xff\xff\xfa\0\0\0\x5\x1\0\0\0\b\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\0\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x34\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x35\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x36\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x37\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x32\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x38\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x39\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\0\0\0\x3\0\0\n\0\0\0\x4\xeb\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\n\0\0\0\0\0\0\xff\xff\xff\xfa\0\0\0\x2\x1\0\0\0\x3\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\0\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x33\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x34\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowNextStateGroup\15\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\15\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\15\size=@Size(2560 1337) +Verdi_1\qBaseWindowNextStateGroup\15\geometry_x=-1 +Verdi_1\qBaseWindowNextStateGroup\15\geometry_y=27 +Verdi_1\qBaseWindowNextStateGroup\15\geometry_width=2560 +Verdi_1\qBaseWindowNextStateGroup\15\geometry_height=1337 +Verdi_1\qBaseWindowNextStateGroup\16\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowNextStateGroup\16\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\16\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\16\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\16\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\16\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\16\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\16\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\16\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\16\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\16\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\16\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\16\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\16\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\16\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\16\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\16\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\16\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\16\qBaseDockWidgetGroup\windowDock_OneSearch\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\16\qBaseDockWidgetGroup\windowDock_OneSearch\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\16\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\16\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\16\qBaseDockWidgetGroup\windowDock_OneSearch\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\16\qBaseDockWidgetGroup\windowDock_nWave_3\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\16\qBaseDockWidgetGroup\windowDock_nWave_3\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\16\qBaseDockWidgetGroup\windowDock_nWave_3\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\16\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\16\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\16\qBaseDockWidgetGroup\windowDock_nWave_3\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\16\qBaseDockWidgetGroup\windowDock_nSchema_4\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\16\qBaseDockWidgetGroup\windowDock_nSchema_4\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\16\qBaseDockWidgetGroup\windowDock_nSchema_4\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\16\qBaseDockWidgetGroup\windowDock_nSchema_4\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\16\qBaseDockWidgetGroup\windowDock_nSchema_4\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\16\qBaseDockWidgetGroup\windowDock_nSchema_4\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\16\qBaseDockWidgetGroup\windowDock_nSchema_4\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\16\ProductVersion=201809 +Verdi_1\qBaseWindowNextStateGroup\16\Layout="@ByteArray(\0\0\0\xff\0\0\0.\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x4\xeb\xfc\x1\0\0\0\x4\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x33\0\0\0\0\0\0\0\n\0\0\0\0\x80\0\xff\xff\xff\xfc\0\0\0\0\0\0\x2\\\0\0\0\0\0\xff\xff\xff\xfa\xff\xff\xff\xff\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfc\0\0\x2\x62\0\0\0\xb7\0\0\0\0\0\xff\xff\xff\xfa\xff\xff\xff\xff\x1\0\0\0\x2\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\0\0k\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0h\0\x65\0r\0i\0t\0\x61\0n\0\x63\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xae\0\xff\xff\xff\xfc\0\0\x3\x1f\0\0\x6\xe1\0\0\0\0\0\xff\xff\xff\xfa\0\0\0\x5\x1\0\0\0\b\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\0\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x34\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x35\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x36\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x37\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x32\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x38\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x39\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\0\0\0\x3\0\0\n\0\0\0\x4\xeb\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\n\0\0\0\0\0\0\xff\xff\xff\xfa\0\0\0\x2\x1\0\0\0\x3\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\0\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x33\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x34\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowNextStateGroup\16\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\16\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\16\size=@Size(2560 1337) +Verdi_1\qBaseWindowNextStateGroup\16\geometry_x=-1 +Verdi_1\qBaseWindowNextStateGroup\16\geometry_y=27 +Verdi_1\qBaseWindowNextStateGroup\16\geometry_width=2560 +Verdi_1\qBaseWindowNextStateGroup\16\geometry_height=1337 +Verdi_1\qBaseWindowNextStateGroup\17\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowNextStateGroup\17\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\17\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\17\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\17\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\17\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\17\qBaseDockWidgetGroup\windowDock_OneSearch\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\17\qBaseDockWidgetGroup\windowDock_OneSearch\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\17\qBaseDockWidgetGroup\windowDock_nWave_3\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\17\qBaseDockWidgetGroup\windowDock_nWave_3\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\17\qBaseDockWidgetGroup\windowDock_nWave_3\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\17\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeMax=1 +Verdi_1\qBaseWindowNextStateGroup\17\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeFix=1 +Verdi_1\qBaseWindowNextStateGroup\17\qBaseDockWidgetGroup\windowDock_nWave_3\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\17\qBaseDockWidgetGroup\windowDock_nSchema_4\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\17\qBaseDockWidgetGroup\windowDock_nSchema_4\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\17\qBaseDockWidgetGroup\windowDock_nSchema_4\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\17\qBaseDockWidgetGroup\windowDock_nSchema_4\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\17\ProductVersion=201809 +Verdi_1\qBaseWindowNextStateGroup\17\Layout="@ByteArray(\0\0\0\xff\0\0\0/\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x4\xeb\xfc\x1\0\0\0\x4\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x33\0\0\0\0\0\0\0\n\0\0\0\0\x80\0\xff\xff\xff\xfc\0\0\0\0\0\0\x2\\\0\0\0\0\0\xff\xff\xff\xfa\xff\xff\xff\xff\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfc\0\0\x2\x62\0\0\0\xb7\0\0\0\0\0\xff\xff\xff\xfa\xff\xff\xff\xff\x1\0\0\0\x2\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\0\0k\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0h\0\x65\0r\0i\0t\0\x61\0n\0\x63\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xae\0\xff\xff\xff\xfc\0\0\x3\x1f\0\0\x6\xe1\0\0\0\0\0\xff\xff\xff\xfa\0\0\0\x5\x1\0\0\0\b\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\0\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x34\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x35\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x36\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x37\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x32\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x38\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x39\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\0\0\0\x3\0\0\n\0\0\0\x4\xeb\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\n\0\0\0\n\0\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x3\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\n\0\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\0\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x33\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x34\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowNextStateGroup\17\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\17\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\17\size=@Size(2560 1337) +Verdi_1\qBaseWindowNextStateGroup\17\geometry_x=-1 +Verdi_1\qBaseWindowNextStateGroup\17\geometry_y=27 +Verdi_1\qBaseWindowNextStateGroup\17\geometry_width=2560 +Verdi_1\qBaseWindowNextStateGroup\17\geometry_height=1337 +Verdi_1\qBaseWindowNextStateGroup\18\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowNextStateGroup\18\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\18\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\18\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\18\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\18\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\18\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeMax=1 +Verdi_1\qBaseWindowNextStateGroup\18\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\18\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\18\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\18\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\18\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\18\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\18\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\18\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\18\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\18\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\18\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\18\qBaseDockWidgetGroup\windowDock_OneSearch\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\18\qBaseDockWidgetGroup\windowDock_OneSearch\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\18\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\18\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\18\qBaseDockWidgetGroup\windowDock_OneSearch\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\18\qBaseDockWidgetGroup\windowDock_nWave_3\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\18\qBaseDockWidgetGroup\windowDock_nWave_3\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\18\qBaseDockWidgetGroup\windowDock_nWave_3\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\18\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\18\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\18\qBaseDockWidgetGroup\windowDock_nWave_3\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\18\qBaseDockWidgetGroup\windowDock_nSchema_4\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\18\qBaseDockWidgetGroup\windowDock_nSchema_4\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\18\qBaseDockWidgetGroup\windowDock_nSchema_4\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\18\qBaseDockWidgetGroup\windowDock_nSchema_4\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\18\qBaseDockWidgetGroup\windowDock_nSchema_4\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\18\qBaseDockWidgetGroup\windowDock_nSchema_4\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\18\qBaseDockWidgetGroup\windowDock_nSchema_4\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\18\ProductVersion=201809 +Verdi_1\qBaseWindowNextStateGroup\18\Layout="@ByteArray(\0\0\0\xff\0\0\0\x30\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x4\xeb\xfc\x1\0\0\0\x4\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x33\0\0\0\0\0\0\0\n\0\0\0\0\x80\0\xff\xff\xff\xfc\0\0\0\0\0\0\x2\\\0\0\0\0\0\xff\xff\xff\xfa\xff\xff\xff\xff\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfc\0\0\x2\x62\0\0\0\xb7\0\0\0\0\0\xff\xff\xff\xfa\xff\xff\xff\xff\x1\0\0\0\x2\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\0\0k\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0h\0\x65\0r\0i\0t\0\x61\0n\0\x63\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xae\0\xff\xff\xff\xfc\0\0\x3\x1f\0\0\x6\xe1\0\0\0\0\0\xff\xff\xff\xfa\0\0\0\x4\x1\0\0\0\a\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x34\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x35\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x36\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x37\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x32\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x38\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x39\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\0\0\0\x3\0\0\n\0\0\0\x4\xeb\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\n\0\0\0\n\0\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x4\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\n\0\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\0\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\0\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x33\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x34\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowNextStateGroup\18\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\18\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\18\size=@Size(2560 1337) +Verdi_1\qBaseWindowNextStateGroup\18\geometry_x=-1 +Verdi_1\qBaseWindowNextStateGroup\18\geometry_y=27 +Verdi_1\qBaseWindowNextStateGroup\18\geometry_width=2560 +Verdi_1\qBaseWindowNextStateGroup\18\geometry_height=1337 +Verdi_1\qBaseWindowNextStateGroup\19\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowNextStateGroup\19\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\19\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\19\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\19\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\19\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\19\qBaseDockWidgetGroup\windowDock_OneSearch\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\19\qBaseDockWidgetGroup\windowDock_OneSearch\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\19\qBaseDockWidgetGroup\windowDock_nWave_3\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\19\qBaseDockWidgetGroup\windowDock_nWave_3\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\19\qBaseDockWidgetGroup\windowDock_nWave_3\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\19\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeMax=1 +Verdi_1\qBaseWindowNextStateGroup\19\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeFix=1 +Verdi_1\qBaseWindowNextStateGroup\19\qBaseDockWidgetGroup\windowDock_nWave_3\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\19\qBaseDockWidgetGroup\windowDock_nSchema_4\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\19\qBaseDockWidgetGroup\windowDock_nSchema_4\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\19\qBaseDockWidgetGroup\windowDock_nSchema_4\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\19\qBaseDockWidgetGroup\windowDock_nSchema_4\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\19\ProductVersion=201809 +Verdi_1\qBaseWindowNextStateGroup\19\Layout="@ByteArray(\0\0\0\xff\0\0\0\x31\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x4\xeb\xfc\x1\0\0\0\x4\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x33\0\0\0\0\0\0\0\n\0\0\0\0\x80\0\xff\xff\xff\xfc\0\0\0\0\0\0\x2\\\0\0\0\0\0\xff\xff\xff\xfa\xff\xff\xff\xff\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfc\0\0\x2\x62\0\0\0\xb7\0\0\0\0\0\xff\xff\xff\xfa\xff\xff\xff\xff\x1\0\0\0\x2\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\0\0k\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0h\0\x65\0r\0i\0t\0\x61\0n\0\x63\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xae\0\xff\xff\xff\xfc\0\0\x3\x1f\0\0\x6\xe1\0\0\0\0\0\xff\xff\xff\xfa\0\0\0\x4\x1\0\0\0\a\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x34\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x35\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x36\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x37\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x32\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x38\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x39\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\0\0\0\x3\0\0\n\0\0\0\x4\xeb\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\n\0\0\0\x2\xc6\0\xff\xff\xff\xfa\0\0\0\x4\x1\0\0\0\x5\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\0\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\x1\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\xff\xff\xff\xfb\0\0\0*\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x31\0\x30\x1\0\0\0\0\xff\xff\xff\xff\0\0\x2\xc6\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x33\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x34\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowNextStateGroup\19\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\19\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\19\size=@Size(2560 1337) +Verdi_1\qBaseWindowNextStateGroup\19\geometry_x=-1 +Verdi_1\qBaseWindowNextStateGroup\19\geometry_y=27 +Verdi_1\qBaseWindowNextStateGroup\19\geometry_width=2560 +Verdi_1\qBaseWindowNextStateGroup\19\geometry_height=1337 +Verdi_1\qBaseWindowNextStateGroup\20\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeMax=1 +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeMax=1 +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\windowDock_OneSearch\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\windowDock_OneSearch\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeMax=1 +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\windowDock_OneSearch\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\windowDock_nWave_3\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\windowDock_nWave_3\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\windowDock_nWave_3\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\windowDock_nWave_3\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\windowDock_nSchema_4\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\windowDock_nSchema_4\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\windowDock_nSchema_4\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\windowDock_nSchema_4\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\windowDock_nSchema_4\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\windowDock_nSchema_4\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\windowDock_nSchema_4\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\20\ProductVersion=201809 +Verdi_1\qBaseWindowNextStateGroup\20\Layout="@ByteArray(\0\0\0\xff\0\0\0\x32\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x4\xeb\xfc\x1\0\0\0\x4\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x33\0\0\0\0\0\0\0\n\0\0\0\0\x80\0\xff\xff\xff\xfc\0\0\0\0\0\0\x2\\\0\0\0\0\0\xff\xff\xff\xfa\xff\xff\xff\xff\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfc\0\0\x2\x62\0\0\0\xb7\0\0\0\0\0\xff\xff\xff\xfa\xff\xff\xff\xff\x1\0\0\0\x2\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\0\0k\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0h\0\x65\0r\0i\0t\0\x61\0n\0\x63\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xae\0\xff\xff\xff\xfc\0\0\x3\x1f\0\0\x6\xe1\0\0\0\0\0\xff\xff\xff\xfa\0\0\0\x4\x1\0\0\0\a\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x34\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x35\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x36\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x37\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x32\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x38\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x39\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\0\0\0\x3\0\0\n\0\0\0\x4\xeb\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\n\0\0\0\x2,\0\xff\xff\xff\xfa\0\0\0\x3\x1\0\0\0\x5\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\x1\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\x1\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\xff\xff\xff\xfb\0\0\0*\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x31\0\x30\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x33\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x34\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowNextStateGroup\20\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\20\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\20\size=@Size(2560 1337) +Verdi_1\qBaseWindowNextStateGroup\20\geometry_x=-1 +Verdi_1\qBaseWindowNextStateGroup\20\geometry_y=27 +Verdi_1\qBaseWindowNextStateGroup\20\geometry_width=2560 +Verdi_1\qBaseWindowNextStateGroup\20\geometry_height=1337 +Verdi_1\qBaseWindowNextStateGroup\21\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\windowDock_OneSearch\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\windowDock_OneSearch\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\windowDock_nWave_3\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\windowDock_nWave_3\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\windowDock_nWave_3\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeMax=1 +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeFix=1 +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\windowDock_nWave_3\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\windowDock_nSchema_4\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\windowDock_nSchema_4\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\windowDock_nSchema_4\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\windowDock_nSchema_4\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\21\ProductVersion=201809 +Verdi_1\qBaseWindowNextStateGroup\21\Layout="@ByteArray(\0\0\0\xff\0\0\0\x33\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x4\xeb\xfc\x1\0\0\0\x4\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x33\0\0\0\0\0\0\0\n\0\0\0\0\x80\0\xff\xff\xff\xfc\0\0\0\0\0\0\x2\\\0\0\0\0\0\xff\xff\xff\xfa\xff\xff\xff\xff\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfc\0\0\x2\x62\0\0\0\xb7\0\0\0\0\0\xff\xff\xff\xfa\xff\xff\xff\xff\x1\0\0\0\x2\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\0\0k\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0h\0\x65\0r\0i\0t\0\x61\0n\0\x63\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xae\0\xff\xff\xff\xfc\0\0\x3\x1f\0\0\x6\xe1\0\0\0\0\0\xff\xff\xff\xfa\0\0\0\x4\x1\0\0\0\a\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x34\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x35\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x36\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x37\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x32\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x38\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x39\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\0\0\0\x3\0\0\n\0\0\0\x4\xeb\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\n\0\0\0\x2\xc6\0\xff\xff\xff\xfa\0\0\0\x5\x1\0\0\0\x6\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\x1\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\x1\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\xff\xff\xff\xfb\0\0\0*\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x31\0\x30\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0*\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x31\0\x31\x1\0\0\0\0\xff\xff\xff\xff\0\0\x2\xc6\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x33\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x34\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowNextStateGroup\21\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\21\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\21\size=@Size(2560 1337) +Verdi_1\qBaseWindowNextStateGroup\21\geometry_x=-1 +Verdi_1\qBaseWindowNextStateGroup\21\geometry_y=27 +Verdi_1\qBaseWindowNextStateGroup\21\geometry_width=2560 +Verdi_1\qBaseWindowNextStateGroup\21\geometry_height=1337 +Verdi_1\qBaseWindowNextStateGroup\22\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowNextStateGroup\22\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\22\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\22\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\22\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\22\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\22\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\22\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\22\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\22\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\22\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\22\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\22\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\22\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\22\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\22\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\22\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\22\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\22\qBaseDockWidgetGroup\windowDock_OneSearch\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\22\qBaseDockWidgetGroup\windowDock_OneSearch\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\22\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\22\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\22\qBaseDockWidgetGroup\windowDock_OneSearch\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\22\qBaseDockWidgetGroup\windowDock_nWave_3\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\22\qBaseDockWidgetGroup\windowDock_nWave_3\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\22\qBaseDockWidgetGroup\windowDock_nWave_3\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\22\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\22\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\22\qBaseDockWidgetGroup\windowDock_nWave_3\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\22\qBaseDockWidgetGroup\windowDock_nSchema_4\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\22\qBaseDockWidgetGroup\windowDock_nSchema_4\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\22\qBaseDockWidgetGroup\windowDock_nSchema_4\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\22\qBaseDockWidgetGroup\windowDock_nSchema_4\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\22\qBaseDockWidgetGroup\windowDock_nSchema_4\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\22\qBaseDockWidgetGroup\windowDock_nSchema_4\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\22\qBaseDockWidgetGroup\windowDock_nSchema_4\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\22\ProductVersion=201809 +Verdi_1\qBaseWindowNextStateGroup\22\Layout="@ByteArray(\0\0\0\xff\0\0\0\x16\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x2s\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x1\xba\0\0\0\x89\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\xe9\0\0\0\xc6\0\0\0k\0\0\0k\xfc\0\0\x1\xc0\0\0\b@\0\0\0\xbf\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x2\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\x1\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x34\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\0\0\0\x3\0\0\n\0\0\0\x2r\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\n\0\0\0\x2,\0\xff\xff\xff\xfa\0\0\0\x3\x1\0\0\0\x4\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\x1\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x33\x1\0\0\0\0\xff\xff\xff\xff\0\0\x1[\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x33\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x34\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowNextStateGroup\22\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\22\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\22\size=@Size(2560 1337) +Verdi_1\qBaseWindowNextStateGroup\22\geometry_x=-1 +Verdi_1\qBaseWindowNextStateGroup\22\geometry_y=27 +Verdi_1\qBaseWindowNextStateGroup\22\geometry_width=2560 +Verdi_1\qBaseWindowNextStateGroup\22\geometry_height=1337 +Verdi_1\qBaseWindowNextStateGroup\23\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowNextStateGroup\23\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\23\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\23\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\23\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\23\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\23\qBaseDockWidgetGroup\windowDock_OneSearch\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\23\qBaseDockWidgetGroup\windowDock_OneSearch\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\23\qBaseDockWidgetGroup\windowDock_nWave_3\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\23\qBaseDockWidgetGroup\windowDock_nWave_3\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\23\qBaseDockWidgetGroup\windowDock_nWave_3\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\23\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeMax=1 +Verdi_1\qBaseWindowNextStateGroup\23\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeFix=1 +Verdi_1\qBaseWindowNextStateGroup\23\qBaseDockWidgetGroup\windowDock_nWave_3\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\23\qBaseDockWidgetGroup\windowDock_nSchema_4\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\23\qBaseDockWidgetGroup\windowDock_nSchema_4\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\23\qBaseDockWidgetGroup\windowDock_nSchema_4\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\23\qBaseDockWidgetGroup\windowDock_nSchema_4\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\23\ProductVersion=201809 +Verdi_1\qBaseWindowNextStateGroup\23\Layout="@ByteArray(\0\0\0\xff\0\0\0\x17\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x3\x6\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x2\x8c\0\0\0\0\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\xe9\0\0\0\xc6\0\0\0k\0\0\0k\xfc\0\0\x2\x92\0\0\an\0\0\0\0\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x2\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\0\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x34\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\0\0\0\x3\0\0\n\0\0\0\x1\xdf\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\n\0\0\0\x1[\0\xff\xff\xff\xfa\0\0\0\x3\x1\0\0\0\x4\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\0\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x33\x1\0\0\0\0\xff\xff\xff\xff\0\0\x1[\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x33\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x34\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowNextStateGroup\23\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\23\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\23\size=@Size(2560 1337) +Verdi_1\qBaseWindowNextStateGroup\23\geometry_x=-1 +Verdi_1\qBaseWindowNextStateGroup\23\geometry_y=27 +Verdi_1\qBaseWindowNextStateGroup\23\geometry_width=2560 +Verdi_1\qBaseWindowNextStateGroup\23\geometry_height=1337 +Verdi_1\qBaseWindowNextStateGroup\24\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowNextStateGroup\24\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\24\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\24\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\24\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\24\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\24\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\24\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\24\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\24\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\24\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\24\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\24\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\24\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\24\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\24\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\24\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\24\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\24\qBaseDockWidgetGroup\windowDock_OneSearch\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\24\qBaseDockWidgetGroup\windowDock_OneSearch\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\24\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\24\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\24\qBaseDockWidgetGroup\windowDock_OneSearch\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\24\qBaseDockWidgetGroup\windowDock_nWave_3\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\24\qBaseDockWidgetGroup\windowDock_nWave_3\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\24\qBaseDockWidgetGroup\windowDock_nWave_3\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\24\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\24\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\24\qBaseDockWidgetGroup\windowDock_nWave_3\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\24\qBaseDockWidgetGroup\windowDock_nSchema_4\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\24\qBaseDockWidgetGroup\windowDock_nSchema_4\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\24\qBaseDockWidgetGroup\windowDock_nSchema_4\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\24\qBaseDockWidgetGroup\windowDock_nSchema_4\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\24\qBaseDockWidgetGroup\windowDock_nSchema_4\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\24\qBaseDockWidgetGroup\windowDock_nSchema_4\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\24\qBaseDockWidgetGroup\windowDock_nSchema_4\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\24\ProductVersion=201809 +Verdi_1\qBaseWindowNextStateGroup\24\Layout="@ByteArray(\0\0\0\xff\0\0\0\x18\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x3\x6\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x2\x8c\0\0\0\x89\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\xe9\0\0\0\xc6\0\0\0k\0\0\0k\xfc\0\0\x2\x92\0\0\an\0\0\0\xbf\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x2\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\x1\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x34\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\0\0\0\x3\0\0\n\0\0\0\x1\xdf\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\n\0\0\0\x2,\0\xff\xff\xff\xfa\0\0\0\x3\x1\0\0\0\x4\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\x1\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x33\x1\0\0\0\0\xff\xff\xff\xff\0\0\x1[\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x33\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x34\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowNextStateGroup\24\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\24\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\24\size=@Size(2560 1337) +Verdi_1\qBaseWindowNextStateGroup\24\geometry_x=-1 +Verdi_1\qBaseWindowNextStateGroup\24\geometry_y=27 +Verdi_1\qBaseWindowNextStateGroup\24\geometry_width=2560 +Verdi_1\qBaseWindowNextStateGroup\24\geometry_height=1337 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_5\isNestedWindow=1 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_5\isVisible=false +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_5\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_5\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_5\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_5\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_5\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\25\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowNextStateGroup\25\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\25\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\25\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\25\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\25\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\25\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\25\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\25\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\25\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\25\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\25\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\25\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\25\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\25\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\25\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\25\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\25\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\25\qBaseDockWidgetGroup\windowDock_OneSearch\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\25\qBaseDockWidgetGroup\windowDock_OneSearch\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\25\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\25\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\25\qBaseDockWidgetGroup\windowDock_OneSearch\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\25\qBaseDockWidgetGroup\windowDock_nWave_3\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\25\qBaseDockWidgetGroup\windowDock_nWave_3\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\25\qBaseDockWidgetGroup\windowDock_nWave_3\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\25\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\25\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\25\qBaseDockWidgetGroup\windowDock_nWave_3\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\25\qBaseDockWidgetGroup\windowDock_nSchema_4\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\25\qBaseDockWidgetGroup\windowDock_nSchema_4\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\25\qBaseDockWidgetGroup\windowDock_nSchema_4\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\25\qBaseDockWidgetGroup\windowDock_nSchema_4\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\25\qBaseDockWidgetGroup\windowDock_nSchema_4\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\25\qBaseDockWidgetGroup\windowDock_nSchema_4\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\25\qBaseDockWidgetGroup\windowDock_nSchema_4\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\25\qBaseDockWidgetGroup\windowDock_nSchema_5\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\25\qBaseDockWidgetGroup\windowDock_nSchema_5\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\25\qBaseDockWidgetGroup\windowDock_nSchema_5\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\25\qBaseDockWidgetGroup\windowDock_nSchema_5\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\25\qBaseDockWidgetGroup\windowDock_nSchema_5\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\25\qBaseDockWidgetGroup\windowDock_nSchema_5\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\25\qBaseDockWidgetGroup\windowDock_nSchema_5\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\25\ProductVersion=201809 +Verdi_1\qBaseWindowNextStateGroup\25\Layout="@ByteArray(\0\0\0\xff\0\0\0\x19\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x3\x6\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x2\x8c\0\0\0\x89\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\xe9\0\0\0\xc6\0\0\0k\0\0\0k\xfc\0\0\x2\x92\0\0\an\0\0\x2\xc6\0\0\bC\xfa\0\0\0\x2\x1\0\0\0\x3\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\x1\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x34\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x35\x1\0\0\0\0\xff\xff\xff\xff\0\0\x2\xc6\0\0\bC\0\0\0\x3\0\0\n\0\0\0\x1\xdf\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\n\0\0\0\x2,\0\xff\xff\xff\xfa\0\0\0\x3\x1\0\0\0\x4\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\x1\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x33\x1\0\0\0\0\xff\xff\xff\xff\0\0\x1[\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x33\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x34\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowNextStateGroup\25\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\25\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\25\size=@Size(2560 1337) +Verdi_1\qBaseWindowNextStateGroup\25\geometry_x=-1 +Verdi_1\qBaseWindowNextStateGroup\25\geometry_y=27 +Verdi_1\qBaseWindowNextStateGroup\25\geometry_width=2560 +Verdi_1\qBaseWindowNextStateGroup\25\geometry_height=1337 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\isVisible=false +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_6\isNestedWindow=1 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_6\isVisible=false +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_6\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_6\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_6\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_6\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_6\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\26\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowNextStateGroup\26\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\26\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\26\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\26\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\26\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\26\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\26\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\26\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\26\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\26\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\26\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\26\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\26\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\26\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\26\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\26\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\26\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\26\qBaseDockWidgetGroup\windowDock_OneSearch\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\26\qBaseDockWidgetGroup\windowDock_OneSearch\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\26\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\26\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\26\qBaseDockWidgetGroup\windowDock_OneSearch\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\26\qBaseDockWidgetGroup\windowDock_nWave_3\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\26\qBaseDockWidgetGroup\windowDock_nWave_3\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\26\qBaseDockWidgetGroup\windowDock_nWave_3\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\26\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\26\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\26\qBaseDockWidgetGroup\windowDock_nWave_3\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\26\qBaseDockWidgetGroup\windowDock_nSchema_4\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\26\qBaseDockWidgetGroup\windowDock_nSchema_4\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\26\qBaseDockWidgetGroup\windowDock_nSchema_4\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\26\qBaseDockWidgetGroup\windowDock_nSchema_4\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\26\qBaseDockWidgetGroup\windowDock_nSchema_4\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\26\qBaseDockWidgetGroup\windowDock_nSchema_4\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\26\qBaseDockWidgetGroup\windowDock_nSchema_4\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\26\qBaseDockWidgetGroup\windowDock_nSchema_5\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\26\qBaseDockWidgetGroup\windowDock_nSchema_5\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\26\qBaseDockWidgetGroup\windowDock_nSchema_5\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\26\qBaseDockWidgetGroup\windowDock_nSchema_5\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\26\qBaseDockWidgetGroup\windowDock_nSchema_5\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\26\qBaseDockWidgetGroup\windowDock_nSchema_5\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\26\qBaseDockWidgetGroup\windowDock_nSchema_5\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\26\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\26\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\26\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\26\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\26\qBaseDockWidgetGroup\windowDock_nSchema_6\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\26\qBaseDockWidgetGroup\windowDock_nSchema_6\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\26\qBaseDockWidgetGroup\windowDock_nSchema_6\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\26\qBaseDockWidgetGroup\windowDock_nSchema_6\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\26\qBaseDockWidgetGroup\windowDock_nSchema_6\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\26\qBaseDockWidgetGroup\windowDock_nSchema_6\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\26\qBaseDockWidgetGroup\windowDock_nSchema_6\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\26\ProductVersion=201809 +Verdi_1\qBaseWindowNextStateGroup\26\Layout="@ByteArray(\0\0\0\xff\0\0\0\x1a\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x3\x6\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x2\\\0\0\0\x89\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfc\0\0\x2\x62\0\0\0\xb7\0\0\0\xae\0\xff\xff\xff\xfa\0\0\0\x1\x1\0\0\0\x2\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\0\0k\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0h\0\x65\0r\0i\0t\0\x61\0n\0\x63\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xae\0\xff\xff\xff\xfc\0\0\x3\x1f\0\0\x6\xe1\0\0\x2\xc6\0\0\x6\xe1\xfa\0\0\0\x3\x1\0\0\0\x4\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\x1\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x34\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x35\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x36\x1\0\0\0\0\xff\xff\xff\xff\0\0\x2\xc6\0\0\x6\xe1\0\0\0\x3\0\0\n\0\0\0\x1\xdf\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\n\0\0\0\x2,\0\xff\xff\xff\xfa\0\0\0\x3\x1\0\0\0\x4\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\x1\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x33\x1\0\0\0\0\xff\xff\xff\xff\0\0\x1[\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x33\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x34\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowNextStateGroup\26\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\26\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\26\size=@Size(2560 1337) +Verdi_1\qBaseWindowNextStateGroup\26\geometry_x=-1 +Verdi_1\qBaseWindowNextStateGroup\26\geometry_y=27 +Verdi_1\qBaseWindowNextStateGroup\26\geometry_width=2560 +Verdi_1\qBaseWindowNextStateGroup\26\geometry_height=1337 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_7\isNestedWindow=1 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_7\isVisible=false +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_7\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_7\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_7\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_7\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_7\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\27\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowNextStateGroup\27\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\27\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\27\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\27\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\27\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\27\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\27\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\27\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\27\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\27\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\27\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\27\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\27\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\27\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\27\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\27\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\27\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\27\qBaseDockWidgetGroup\windowDock_OneSearch\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\27\qBaseDockWidgetGroup\windowDock_OneSearch\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\27\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\27\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\27\qBaseDockWidgetGroup\windowDock_OneSearch\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\27\qBaseDockWidgetGroup\windowDock_nWave_3\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\27\qBaseDockWidgetGroup\windowDock_nWave_3\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\27\qBaseDockWidgetGroup\windowDock_nWave_3\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\27\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\27\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\27\qBaseDockWidgetGroup\windowDock_nWave_3\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\27\qBaseDockWidgetGroup\windowDock_nSchema_4\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\27\qBaseDockWidgetGroup\windowDock_nSchema_4\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\27\qBaseDockWidgetGroup\windowDock_nSchema_4\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\27\qBaseDockWidgetGroup\windowDock_nSchema_4\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\27\qBaseDockWidgetGroup\windowDock_nSchema_4\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\27\qBaseDockWidgetGroup\windowDock_nSchema_4\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\27\qBaseDockWidgetGroup\windowDock_nSchema_4\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\27\qBaseDockWidgetGroup\windowDock_nSchema_5\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\27\qBaseDockWidgetGroup\windowDock_nSchema_5\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\27\qBaseDockWidgetGroup\windowDock_nSchema_5\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\27\qBaseDockWidgetGroup\windowDock_nSchema_5\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\27\qBaseDockWidgetGroup\windowDock_nSchema_5\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\27\qBaseDockWidgetGroup\windowDock_nSchema_5\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\27\qBaseDockWidgetGroup\windowDock_nSchema_5\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\27\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\27\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\27\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\27\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\27\qBaseDockWidgetGroup\windowDock_nSchema_6\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\27\qBaseDockWidgetGroup\windowDock_nSchema_6\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\27\qBaseDockWidgetGroup\windowDock_nSchema_6\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\27\qBaseDockWidgetGroup\windowDock_nSchema_6\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\27\qBaseDockWidgetGroup\windowDock_nSchema_6\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\27\qBaseDockWidgetGroup\windowDock_nSchema_6\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\27\qBaseDockWidgetGroup\windowDock_nSchema_6\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\27\qBaseDockWidgetGroup\windowDock_nSchema_7\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\27\qBaseDockWidgetGroup\windowDock_nSchema_7\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\27\qBaseDockWidgetGroup\windowDock_nSchema_7\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\27\qBaseDockWidgetGroup\windowDock_nSchema_7\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\27\qBaseDockWidgetGroup\windowDock_nSchema_7\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\27\qBaseDockWidgetGroup\windowDock_nSchema_7\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\27\qBaseDockWidgetGroup\windowDock_nSchema_7\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\27\ProductVersion=201809 +Verdi_1\qBaseWindowNextStateGroup\27\Layout="@ByteArray(\0\0\0\xff\0\0\0\x1b\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x3\x6\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x2\\\0\0\0\x89\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfc\0\0\x2\x62\0\0\0\xb7\0\0\0\xae\0\xff\xff\xff\xfa\0\0\0\x1\x1\0\0\0\x2\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\0\0k\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0h\0\x65\0r\0i\0t\0\x61\0n\0\x63\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xae\0\xff\xff\xff\xfc\0\0\x3\x1f\0\0\x6\xe1\0\0\x2\xc6\0\0\x6\xe1\xfa\0\0\0\x4\x1\0\0\0\x5\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\x1\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x34\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x35\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x36\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x37\x1\0\0\0\0\xff\xff\xff\xff\0\0\x2\xc6\0\0\x6\xe1\0\0\0\x3\0\0\n\0\0\0\x1\xdf\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\n\0\0\0\x2,\0\xff\xff\xff\xfa\0\0\0\x3\x1\0\0\0\x4\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\x1\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x33\x1\0\0\0\0\xff\xff\xff\xff\0\0\x1[\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x33\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x34\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowNextStateGroup\27\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\27\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\27\size=@Size(2560 1337) +Verdi_1\qBaseWindowNextStateGroup\27\geometry_x=-1 +Verdi_1\qBaseWindowNextStateGroup\27\geometry_y=27 +Verdi_1\qBaseWindowNextStateGroup\27\geometry_width=2560 +Verdi_1\qBaseWindowNextStateGroup\27\geometry_height=1337 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_8\isNestedWindow=1 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_8\isVisible=false +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_8\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_8\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_8\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_8\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_8\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\28\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\windowDock_OneSearch\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\windowDock_OneSearch\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\windowDock_OneSearch\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\windowDock_nWave_3\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\windowDock_nWave_3\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\windowDock_nWave_3\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\windowDock_nWave_3\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\windowDock_nSchema_4\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\windowDock_nSchema_4\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\windowDock_nSchema_4\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\windowDock_nSchema_4\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\windowDock_nSchema_4\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\windowDock_nSchema_4\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\windowDock_nSchema_4\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\windowDock_nSchema_5\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\windowDock_nSchema_5\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\windowDock_nSchema_5\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\windowDock_nSchema_5\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\windowDock_nSchema_5\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\windowDock_nSchema_5\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\windowDock_nSchema_5\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\windowDock_nSchema_6\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\windowDock_nSchema_6\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\windowDock_nSchema_6\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\windowDock_nSchema_6\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\windowDock_nSchema_6\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\windowDock_nSchema_6\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\windowDock_nSchema_6\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\windowDock_nSchema_7\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\windowDock_nSchema_7\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\windowDock_nSchema_7\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\windowDock_nSchema_7\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\windowDock_nSchema_7\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\windowDock_nSchema_7\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\windowDock_nSchema_7\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\windowDock_nSchema_8\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\windowDock_nSchema_8\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\windowDock_nSchema_8\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\windowDock_nSchema_8\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\windowDock_nSchema_8\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\windowDock_nSchema_8\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\windowDock_nSchema_8\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\28\ProductVersion=201809 +Verdi_1\qBaseWindowNextStateGroup\28\Layout="@ByteArray(\0\0\0\xff\0\0\0\x1c\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x3\xb3\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x2\\\0\0\0\x89\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfc\0\0\x2\x62\0\0\0\xb7\0\0\0\xae\0\xff\xff\xff\xfa\0\0\0\x1\x1\0\0\0\x2\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\0\0k\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0h\0\x65\0r\0i\0t\0\x61\0n\0\x63\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xae\0\xff\xff\xff\xfc\0\0\x3\x1f\0\0\x6\xe1\0\0\x2\xc6\0\0\x6\xe1\xfa\0\0\0\x6\x1\0\0\0\a\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\x1\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x34\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x35\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x36\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x37\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x32\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x38\x1\0\0\0\0\xff\xff\xff\xff\0\0\x2\xc6\0\0\x6\xe1\0\0\0\x3\0\0\n\0\0\0\x1\x32\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\n\0\0\0\x2,\0\xff\xff\xff\xfa\0\0\0\x3\x1\0\0\0\x4\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\x1\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x33\x1\0\0\0\0\xff\xff\xff\xff\0\0\x1[\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x33\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x34\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowNextStateGroup\28\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\28\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\28\size=@Size(2560 1337) +Verdi_1\qBaseWindowNextStateGroup\28\geometry_x=-1 +Verdi_1\qBaseWindowNextStateGroup\28\geometry_y=27 +Verdi_1\qBaseWindowNextStateGroup\28\geometry_width=2560 +Verdi_1\qBaseWindowNextStateGroup\28\geometry_height=1337 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_9\isNestedWindow=1 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_9\isVisible=false +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_9\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_9\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_9\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_9\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_9\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\29\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\windowDock_OneSearch\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\windowDock_OneSearch\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\windowDock_OneSearch\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\windowDock_nWave_3\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\windowDock_nWave_3\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\windowDock_nWave_3\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\windowDock_nWave_3\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\windowDock_nSchema_4\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\windowDock_nSchema_4\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\windowDock_nSchema_4\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\windowDock_nSchema_4\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\windowDock_nSchema_4\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\windowDock_nSchema_4\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\windowDock_nSchema_4\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\windowDock_nSchema_5\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\windowDock_nSchema_5\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\windowDock_nSchema_5\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\windowDock_nSchema_5\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\windowDock_nSchema_5\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\windowDock_nSchema_5\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\windowDock_nSchema_5\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\windowDock_nSchema_6\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\windowDock_nSchema_6\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\windowDock_nSchema_6\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\windowDock_nSchema_6\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\windowDock_nSchema_6\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\windowDock_nSchema_6\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\windowDock_nSchema_6\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\windowDock_nSchema_7\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\windowDock_nSchema_7\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\windowDock_nSchema_7\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\windowDock_nSchema_7\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\windowDock_nSchema_7\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\windowDock_nSchema_7\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\windowDock_nSchema_7\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\windowDock_nSchema_8\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\windowDock_nSchema_8\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\windowDock_nSchema_8\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\windowDock_nSchema_8\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\windowDock_nSchema_8\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\windowDock_nSchema_8\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\windowDock_nSchema_8\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\windowDock_nSchema_9\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\windowDock_nSchema_9\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\windowDock_nSchema_9\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\windowDock_nSchema_9\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\windowDock_nSchema_9\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\windowDock_nSchema_9\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\windowDock_nSchema_9\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\29\ProductVersion=201809 +Verdi_1\qBaseWindowNextStateGroup\29\Layout="@ByteArray(\0\0\0\xff\0\0\0\x1d\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x3\xb3\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x2\\\0\0\0\x89\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfc\0\0\x2\x62\0\0\0\xb7\0\0\0\xae\0\xff\xff\xff\xfa\0\0\0\x1\x1\0\0\0\x2\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\0\0k\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0h\0\x65\0r\0i\0t\0\x61\0n\0\x63\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xae\0\xff\xff\xff\xfc\0\0\x3\x1f\0\0\x6\xe1\0\0\x2\xc6\0\0\x6\xe1\xfa\0\0\0\a\x1\0\0\0\b\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\x1\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x34\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x35\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x36\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x37\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x32\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x38\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x39\x1\0\0\0\0\xff\xff\xff\xff\0\0\x2\xc6\0\0\x6\xe1\0\0\0\x3\0\0\n\0\0\0\x1\x32\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\n\0\0\0\x2,\0\xff\xff\xff\xfa\0\0\0\x3\x1\0\0\0\x4\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\x1\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x33\x1\0\0\0\0\xff\xff\xff\xff\0\0\x1[\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x33\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x34\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowNextStateGroup\29\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\29\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\29\size=@Size(2560 1337) +Verdi_1\qBaseWindowNextStateGroup\29\geometry_x=-1 +Verdi_1\qBaseWindowNextStateGroup\29\geometry_y=27 +Verdi_1\qBaseWindowNextStateGroup\29\geometry_width=2560 +Verdi_1\qBaseWindowNextStateGroup\29\geometry_height=1337 +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\windowDock_OneSearch\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\windowDock_OneSearch\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\windowDock_nWave_3\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\windowDock_nWave_3\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\windowDock_nWave_3\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeMax=1 +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeFix=1 +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\windowDock_nWave_3\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\windowDock_nSchema_4\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\windowDock_nSchema_4\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\windowDock_nSchema_4\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\windowDock_nSchema_4\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\windowDock_nSchema_5\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\windowDock_nSchema_5\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\windowDock_nSchema_5\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\windowDock_nSchema_5\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\windowDock_nSchema_6\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\windowDock_nSchema_6\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\windowDock_nSchema_6\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\windowDock_nSchema_6\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\windowDock_nSchema_7\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\windowDock_nSchema_7\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\windowDock_nSchema_7\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\windowDock_nSchema_7\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\windowDock_nSchema_8\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\windowDock_nSchema_8\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\windowDock_nSchema_8\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\windowDock_nSchema_8\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\windowDock_nSchema_9\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\windowDock_nSchema_9\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\windowDock_nSchema_9\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\windowDock_nSchema_9\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_nWave_3\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_nWave_3\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_nWave_3\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_nWave_3\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_nSchema_4\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_nSchema_4\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_nSchema_4\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_nSchema_4\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_nSchema_4\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_nSchema_4\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_nSchema_4\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_nSchema_5\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_nSchema_5\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_nSchema_5\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_nSchema_5\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_nSchema_5\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_nSchema_5\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_nSchema_5\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_nSchema_6\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_nSchema_6\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_nSchema_6\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_nSchema_6\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_nSchema_6\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_nSchema_6\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_nSchema_6\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_nSchema_7\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_nSchema_7\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_nSchema_7\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_nSchema_7\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_nSchema_7\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_nSchema_7\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_nSchema_7\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_nSchema_8\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_nSchema_8\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_nSchema_8\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_nSchema_8\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_nSchema_8\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_nSchema_8\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_nSchema_8\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_nSchema_9\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_nSchema_9\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_nSchema_9\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_nSchema_9\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_nSchema_9\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_nSchema_9\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_nSchema_9\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\windowDock_nWave_3\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\windowDock_nWave_3\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\windowDock_nWave_3\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeMax=1 +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeFix=1 +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\windowDock_nWave_3\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\windowDock_nSchema_4\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\windowDock_nSchema_4\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\windowDock_nSchema_4\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\windowDock_nSchema_4\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\windowDock_nSchema_5\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\windowDock_nSchema_5\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\windowDock_nSchema_5\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\windowDock_nSchema_5\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\windowDock_nSchema_6\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\windowDock_nSchema_6\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\windowDock_nSchema_6\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\windowDock_nSchema_6\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\windowDock_nSchema_7\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\windowDock_nSchema_7\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\windowDock_nSchema_7\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\windowDock_nSchema_7\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\windowDock_nSchema_8\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\windowDock_nSchema_8\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\windowDock_nSchema_8\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\windowDock_nSchema_8\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\windowDock_nSchema_9\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\windowDock_nSchema_9\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\windowDock_nSchema_9\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\windowDock_nSchema_9\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\windowDock_nWave_3\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\windowDock_nWave_3\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\windowDock_nWave_3\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeMax=1 +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeFix=1 +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\windowDock_nWave_3\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\windowDock_nSchema_4\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\windowDock_nSchema_4\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\windowDock_nSchema_4\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\windowDock_nSchema_4\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\windowDock_nSchema_5\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\windowDock_nSchema_5\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\windowDock_nSchema_5\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\windowDock_nSchema_5\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\windowDock_nSchema_6\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\windowDock_nSchema_6\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\windowDock_nSchema_6\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\windowDock_nSchema_6\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\windowDock_nSchema_7\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\windowDock_nSchema_7\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\windowDock_nSchema_7\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\windowDock_nSchema_7\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\windowDock_nSchema_8\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\windowDock_nSchema_8\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\windowDock_nSchema_8\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\windowDock_nSchema_8\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\windowDock_nSchema_9\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\windowDock_nSchema_9\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\windowDock_nSchema_9\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\windowDock_nSchema_9\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\windowDock_nWave_3\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\windowDock_nWave_3\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\windowDock_nWave_3\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeMax=1 +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeFix=1 +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\windowDock_nWave_3\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\windowDock_nSchema_4\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\windowDock_nSchema_4\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\windowDock_nSchema_4\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\windowDock_nSchema_4\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\windowDock_nSchema_5\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\windowDock_nSchema_5\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\windowDock_nSchema_5\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\windowDock_nSchema_5\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\windowDock_nSchema_6\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\windowDock_nSchema_6\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\windowDock_nSchema_6\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\windowDock_nSchema_6\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\windowDock_nSchema_7\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\windowDock_nSchema_7\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\windowDock_nSchema_7\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\windowDock_nSchema_7\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\windowDock_nSchema_8\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\windowDock_nSchema_8\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\windowDock_nSchema_8\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\windowDock_nSchema_8\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\windowDock_nSchema_9\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\windowDock_nSchema_9\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\windowDock_nSchema_9\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\windowDock_nSchema_9\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nWave_3\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nWave_3\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nWave_3\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nWave_3\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nSchema_4\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nSchema_4\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nSchema_4\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nSchema_4\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nSchema_4\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nSchema_4\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nSchema_4\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nSchema_5\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nSchema_5\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nSchema_5\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nSchema_5\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nSchema_5\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nSchema_5\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nSchema_5\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nSchema_6\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nSchema_6\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nSchema_6\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nSchema_6\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nSchema_6\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nSchema_6\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nSchema_6\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nSchema_7\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nSchema_7\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nSchema_7\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nSchema_7\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nSchema_7\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nSchema_7\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nSchema_7\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nSchema_8\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nSchema_8\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nSchema_8\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nSchema_8\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nSchema_8\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nSchema_8\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nSchema_8\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nSchema_9\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nSchema_9\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nSchema_9\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nSchema_9\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nSchema_9\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nSchema_9\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nSchema_9\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\windowDock_nWave_3\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\windowDock_nWave_3\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\windowDock_nWave_3\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeMax=1 +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeFix=1 +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\windowDock_nWave_3\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\windowDock_nSchema_4\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\windowDock_nSchema_4\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\windowDock_nSchema_4\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\windowDock_nSchema_4\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\windowDock_nSchema_5\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\windowDock_nSchema_5\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\windowDock_nSchema_5\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\windowDock_nSchema_5\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\windowDock_nSchema_6\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\windowDock_nSchema_6\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\windowDock_nSchema_6\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\windowDock_nSchema_6\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\windowDock_nSchema_7\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\windowDock_nSchema_7\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\windowDock_nSchema_7\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\windowDock_nSchema_7\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\windowDock_nSchema_8\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\windowDock_nSchema_8\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\windowDock_nSchema_8\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\windowDock_nSchema_8\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\windowDock_nSchema_9\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\windowDock_nSchema_9\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\windowDock_nSchema_9\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\windowDock_nSchema_9\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_nWave_3\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_nWave_3\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_nWave_3\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_nWave_3\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_nSchema_4\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_nSchema_4\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_nSchema_4\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_nSchema_4\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_nSchema_4\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_nSchema_4\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_nSchema_4\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_nSchema_5\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_nSchema_5\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_nSchema_5\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_nSchema_5\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_nSchema_5\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_nSchema_5\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_nSchema_5\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_nSchema_6\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_nSchema_6\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_nSchema_6\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_nSchema_6\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_nSchema_6\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_nSchema_6\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_nSchema_6\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_nSchema_7\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_nSchema_7\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_nSchema_7\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_nSchema_7\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_nSchema_7\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_nSchema_7\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_nSchema_7\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_nSchema_8\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_nSchema_8\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_nSchema_8\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_nSchema_8\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_nSchema_8\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_nSchema_8\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_nSchema_8\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_nSchema_9\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_nSchema_9\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_nSchema_9\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_nSchema_9\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_nSchema_9\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_nSchema_9\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_nSchema_9\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\windowDock_nWave_3\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\windowDock_nSchema_4\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\windowDock_nSchema_4\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\windowDock_nSchema_4\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\windowDock_nSchema_4\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\windowDock_nSchema_5\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\windowDock_nSchema_5\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\windowDock_nSchema_5\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\windowDock_nSchema_5\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\windowDock_nSchema_6\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\windowDock_nSchema_6\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\windowDock_nSchema_6\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\windowDock_nSchema_6\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\windowDock_nSchema_7\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\windowDock_nSchema_7\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\windowDock_nSchema_7\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\windowDock_nSchema_7\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\windowDock_nSchema_8\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\windowDock_nSchema_8\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\windowDock_nSchema_8\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\windowDock_nSchema_8\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\windowDock_nSchema_9\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\windowDock_nSchema_9\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\windowDock_nSchema_9\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\windowDock_nSchema_9\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeMax=1 +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\windowDock_nSchema_4\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\windowDock_nSchema_4\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\windowDock_nSchema_4\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\windowDock_nSchema_4\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\windowDock_nSchema_5\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\windowDock_nSchema_5\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\windowDock_nSchema_5\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\windowDock_nSchema_5\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\windowDock_nSchema_6\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\windowDock_nSchema_6\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\windowDock_nSchema_6\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\windowDock_nSchema_6\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\windowDock_nSchema_7\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\windowDock_nSchema_7\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\windowDock_nSchema_7\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\windowDock_nSchema_7\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\windowDock_nSchema_8\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\windowDock_nSchema_8\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\windowDock_nSchema_8\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\windowDock_nSchema_8\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\windowDock_nSchema_9\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\windowDock_nSchema_9\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\windowDock_nSchema_9\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\windowDock_nSchema_9\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\windowDock_nSchema_4\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\windowDock_nSchema_4\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\windowDock_nSchema_4\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\windowDock_nSchema_4\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\windowDock_nSchema_5\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\windowDock_nSchema_5\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\windowDock_nSchema_5\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\windowDock_nSchema_5\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\windowDock_nSchema_6\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\windowDock_nSchema_6\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\windowDock_nSchema_6\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\windowDock_nSchema_6\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\windowDock_nSchema_7\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\windowDock_nSchema_7\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\windowDock_nSchema_7\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\windowDock_nSchema_7\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\windowDock_nSchema_8\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\windowDock_nSchema_8\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\windowDock_nSchema_8\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\windowDock_nSchema_8\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\windowDock_nSchema_9\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\windowDock_nSchema_9\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\windowDock_nSchema_9\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\windowDock_nSchema_9\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_OneSearch\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_nSchema_4\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_nSchema_4\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_nSchema_4\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_nSchema_4\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_nSchema_4\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_nSchema_4\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_nSchema_4\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_nSchema_5\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_nSchema_5\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_nSchema_5\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_nSchema_5\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_nSchema_5\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_nSchema_5\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_nSchema_5\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_nSchema_6\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_nSchema_6\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_nSchema_6\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_nSchema_6\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_nSchema_6\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_nSchema_6\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_nSchema_6\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_nSchema_7\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_nSchema_7\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_nSchema_7\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_nSchema_7\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_nSchema_7\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_nSchema_7\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_nSchema_7\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_nSchema_8\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_nSchema_8\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_nSchema_8\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_nSchema_8\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_nSchema_8\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_nSchema_8\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_nSchema_8\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_nSchema_9\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_nSchema_9\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_nSchema_9\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_nSchema_9\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_nSchema_9\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_nSchema_9\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_nSchema_9\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\windowDock_nSchema_4\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\windowDock_nSchema_4\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\windowDock_nSchema_4\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\windowDock_nSchema_4\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\windowDock_nSchema_5\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\windowDock_nSchema_5\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\windowDock_nSchema_5\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\windowDock_nSchema_5\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\windowDock_nSchema_6\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\windowDock_nSchema_6\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\windowDock_nSchema_6\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\windowDock_nSchema_6\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\windowDock_nSchema_7\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\windowDock_nSchema_7\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\windowDock_nSchema_7\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\windowDock_nSchema_7\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\windowDock_nSchema_8\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\windowDock_nSchema_8\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\windowDock_nSchema_8\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\windowDock_nSchema_8\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\windowDock_nSchema_9\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\windowDock_nSchema_9\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\windowDock_nSchema_9\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\windowDock_nSchema_9\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_OneSearch\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_nSchema_4\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_nSchema_4\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_nSchema_4\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_nSchema_4\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_nSchema_4\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_nSchema_4\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_nSchema_4\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_nSchema_5\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_nSchema_5\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_nSchema_5\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_nSchema_5\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_nSchema_5\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_nSchema_5\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_nSchema_5\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_nSchema_6\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_nSchema_6\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_nSchema_6\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_nSchema_6\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_nSchema_6\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_nSchema_6\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_nSchema_6\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_nSchema_7\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_nSchema_7\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_nSchema_7\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_nSchema_7\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_nSchema_7\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_nSchema_7\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_nSchema_7\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_nSchema_8\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_nSchema_8\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_nSchema_8\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_nSchema_8\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_nSchema_8\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_nSchema_8\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_nSchema_8\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_nSchema_9\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_nSchema_9\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_nSchema_9\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_nSchema_9\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_nSchema_9\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_nSchema_9\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_nSchema_9\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\windowDock_OneSearch\isNestedWindow=1 +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\windowDock_OneSearch\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\windowDock_OneSearch\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\windowDock_nWave_3\isNestedWindow=1 +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\windowDock_nWave_3\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\windowDock_nWave_3\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\windowDock_nWave_3\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_4\isNestedWindow=1 +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_4\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_4\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_4\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_4\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_4\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_4\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_5\isNestedWindow=1 +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_5\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_5\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_5\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_5\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_5\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_5\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_6\isNestedWindow=1 +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_6\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_6\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_6\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_6\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_6\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_6\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_7\isNestedWindow=1 +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_7\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_7\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_7\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_7\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_7\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_7\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_8\isNestedWindow=1 +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_8\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_8\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_8\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_8\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_8\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_8\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_9\isNestedWindow=1 +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_9\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_9\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_9\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_9\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_9\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_9\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\ProductVersion=201809 +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\Layout="@ByteArray(\0\0\0\xff\0\0\0\0\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x3\xb3\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x2\\\0\0\0\x89\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfc\0\0\x2\x62\0\0\0\xb7\0\0\0\xae\0\xff\xff\xff\xfa\0\0\0\x1\x1\0\0\0\x2\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\0\0k\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0h\0\x65\0r\0i\0t\0\x61\0n\0\x63\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xae\0\xff\xff\xff\xfc\0\0\x3\x1f\0\0\x6\xe1\0\0\0\xbf\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\b\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\x1\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x34\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x35\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x36\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x37\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x32\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x38\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x39\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\0\0\0\x3\0\0\n\0\0\0\x1\x32\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\n\0\0\0\x2,\0\xff\xff\xff\xfa\0\0\0\x3\x1\0\0\0\x4\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\x1\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x33\x1\0\0\0\0\xff\xff\xff\xff\0\0\x1[\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x33\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x34\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\isNestedWindow=0 +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\size=@Size(2560 1337) +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\geometry_x=-1 +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\geometry_y=27 +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\geometry_width=2560 +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\geometry_height=1337 +Verdi_1\qBaseWindowNextStateGroup\14\qBaseDockWidgetGroup\windowDock_nSchema_4\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\14\qBaseDockWidgetGroup\windowDock_nSchema_4\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\14\qBaseDockWidgetGroup\windowDock_nSchema_4\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\14\qBaseDockWidgetGroup\windowDock_nSchema_4\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\14\qBaseDockWidgetGroup\windowDock_nSchema_5\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\14\qBaseDockWidgetGroup\windowDock_nSchema_5\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\14\qBaseDockWidgetGroup\windowDock_nSchema_5\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\14\qBaseDockWidgetGroup\windowDock_nSchema_5\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\14\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\14\qBaseDockWidgetGroup\windowDock_nSchema_6\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\14\qBaseDockWidgetGroup\windowDock_nSchema_6\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\14\qBaseDockWidgetGroup\windowDock_nSchema_6\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\14\qBaseDockWidgetGroup\windowDock_nSchema_6\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\14\qBaseDockWidgetGroup\windowDock_nSchema_7\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\14\qBaseDockWidgetGroup\windowDock_nSchema_7\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\14\qBaseDockWidgetGroup\windowDock_nSchema_7\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\14\qBaseDockWidgetGroup\windowDock_nSchema_7\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\14\qBaseDockWidgetGroup\windowDock_nSchema_8\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\14\qBaseDockWidgetGroup\windowDock_nSchema_8\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\14\qBaseDockWidgetGroup\windowDock_nSchema_8\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\14\qBaseDockWidgetGroup\windowDock_nSchema_8\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\14\qBaseDockWidgetGroup\windowDock_nSchema_9\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\14\qBaseDockWidgetGroup\windowDock_nSchema_9\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\14\qBaseDockWidgetGroup\windowDock_nSchema_9\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\14\qBaseDockWidgetGroup\windowDock_nSchema_9\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nWave_3\geometry=@ByteArray(\x1\xd9\xd0\xcb\0\x1\0\0\xff\xff\xff\x8a\0\0\0v\0\0\t\x89\0\0\x5\x61\xff\xff\xff\x8a\0\0\0v\0\0\t\x89\0\0\x5\x61\0\0\0\0\0\0) +Verdi_1\qBaseWindowNextStateGroup\15\qBaseDockWidgetGroup\windowDock_nWave_3\geometry=@ByteArray(\x1\xd9\xd0\xcb\0\x1\0\0\xff\xff\xff\x8a\0\0\0v\0\0\t\x89\0\0\x5\x61\xff\xff\xff\x8a\0\0\0v\0\0\t\x89\0\0\x5\x61\0\0\0\0\0\0) +Verdi_1\qBaseWindowNextStateGroup\15\qBaseDockWidgetGroup\windowDock_nSchema_5\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\15\qBaseDockWidgetGroup\windowDock_nSchema_5\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\15\qBaseDockWidgetGroup\windowDock_nSchema_5\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\15\qBaseDockWidgetGroup\windowDock_nSchema_5\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\15\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\15\qBaseDockWidgetGroup\windowDock_nSchema_6\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\15\qBaseDockWidgetGroup\windowDock_nSchema_6\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\15\qBaseDockWidgetGroup\windowDock_nSchema_6\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\15\qBaseDockWidgetGroup\windowDock_nSchema_6\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\15\qBaseDockWidgetGroup\windowDock_nSchema_7\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\15\qBaseDockWidgetGroup\windowDock_nSchema_7\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\15\qBaseDockWidgetGroup\windowDock_nSchema_7\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\15\qBaseDockWidgetGroup\windowDock_nSchema_7\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\15\qBaseDockWidgetGroup\windowDock_nSchema_8\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\15\qBaseDockWidgetGroup\windowDock_nSchema_8\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\15\qBaseDockWidgetGroup\windowDock_nSchema_8\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\15\qBaseDockWidgetGroup\windowDock_nSchema_8\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\15\qBaseDockWidgetGroup\windowDock_nSchema_9\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\15\qBaseDockWidgetGroup\windowDock_nSchema_9\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\15\qBaseDockWidgetGroup\windowDock_nSchema_9\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\15\qBaseDockWidgetGroup\windowDock_nSchema_9\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\16\qBaseDockWidgetGroup\windowDock_nWave_3\geometry=@ByteArray(\x1\xd9\xd0\xcb\0\x1\0\0\xff\xff\xff\x8a\0\0\0v\0\0\t\x89\0\0\x5\x61\xff\xff\xff\x8a\0\0\0v\0\0\t\x89\0\0\x5\x61\0\0\0\0\0\0) +Verdi_1\qBaseWindowNextStateGroup\16\qBaseDockWidgetGroup\windowDock_nSchema_5\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\16\qBaseDockWidgetGroup\windowDock_nSchema_5\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\16\qBaseDockWidgetGroup\windowDock_nSchema_5\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\16\qBaseDockWidgetGroup\windowDock_nSchema_5\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\16\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\16\qBaseDockWidgetGroup\windowDock_nSchema_6\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\16\qBaseDockWidgetGroup\windowDock_nSchema_6\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\16\qBaseDockWidgetGroup\windowDock_nSchema_6\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\16\qBaseDockWidgetGroup\windowDock_nSchema_6\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\16\qBaseDockWidgetGroup\windowDock_nSchema_7\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\16\qBaseDockWidgetGroup\windowDock_nSchema_7\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\16\qBaseDockWidgetGroup\windowDock_nSchema_7\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\16\qBaseDockWidgetGroup\windowDock_nSchema_7\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\16\qBaseDockWidgetGroup\windowDock_nSchema_8\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\16\qBaseDockWidgetGroup\windowDock_nSchema_8\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\16\qBaseDockWidgetGroup\windowDock_nSchema_8\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\16\qBaseDockWidgetGroup\windowDock_nSchema_8\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\16\qBaseDockWidgetGroup\windowDock_nSchema_9\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\16\qBaseDockWidgetGroup\windowDock_nSchema_9\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\16\qBaseDockWidgetGroup\windowDock_nSchema_9\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\16\qBaseDockWidgetGroup\windowDock_nSchema_9\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\17\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeMax=1 +Verdi_1\qBaseWindowNextStateGroup\17\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\17\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\17\qBaseDockWidgetGroup\windowDock_nWave_3\geometry=@ByteArray(\x1\xd9\xd0\xcb\0\x1\0\0\xff\xff\xff\xf6\0\0\0Z\0\0\n\t\0\0\x5|\0\0\0\0\0\0\0\x87\0\0\t\xff\0\0\x5r\0\0\0\0\0\0) +Verdi_1\qBaseWindowNextStateGroup\17\qBaseDockWidgetGroup\windowDock_nSchema_5\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\17\qBaseDockWidgetGroup\windowDock_nSchema_5\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\17\qBaseDockWidgetGroup\windowDock_nSchema_5\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\17\qBaseDockWidgetGroup\windowDock_nSchema_5\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\17\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\17\qBaseDockWidgetGroup\windowDock_nSchema_6\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\17\qBaseDockWidgetGroup\windowDock_nSchema_6\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\17\qBaseDockWidgetGroup\windowDock_nSchema_6\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\17\qBaseDockWidgetGroup\windowDock_nSchema_6\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\17\qBaseDockWidgetGroup\windowDock_nSchema_7\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\17\qBaseDockWidgetGroup\windowDock_nSchema_7\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\17\qBaseDockWidgetGroup\windowDock_nSchema_7\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\17\qBaseDockWidgetGroup\windowDock_nSchema_7\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\17\qBaseDockWidgetGroup\windowDock_nSchema_8\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\17\qBaseDockWidgetGroup\windowDock_nSchema_8\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\17\qBaseDockWidgetGroup\windowDock_nSchema_8\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\17\qBaseDockWidgetGroup\windowDock_nSchema_8\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\17\qBaseDockWidgetGroup\windowDock_nSchema_9\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\17\qBaseDockWidgetGroup\windowDock_nSchema_9\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\17\qBaseDockWidgetGroup\windowDock_nSchema_9\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\17\qBaseDockWidgetGroup\windowDock_nSchema_9\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\18\qBaseDockWidgetGroup\windowDock_nWave_3\geometry=@ByteArray(\x1\xd9\xd0\xcb\0\x1\0\0\xff\xff\xff\xf6\0\0\0Z\0\0\n\t\0\0\x5|\0\0\0\0\0\0\0\x87\0\0\t\xff\0\0\x5r\0\0\0\0\0\0) +Verdi_1\qBaseWindowNextStateGroup\18\qBaseDockWidgetGroup\windowDock_nSchema_5\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\18\qBaseDockWidgetGroup\windowDock_nSchema_5\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\18\qBaseDockWidgetGroup\windowDock_nSchema_5\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\18\qBaseDockWidgetGroup\windowDock_nSchema_5\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\18\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\18\qBaseDockWidgetGroup\windowDock_nSchema_6\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\18\qBaseDockWidgetGroup\windowDock_nSchema_6\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\18\qBaseDockWidgetGroup\windowDock_nSchema_6\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\18\qBaseDockWidgetGroup\windowDock_nSchema_6\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\18\qBaseDockWidgetGroup\windowDock_nSchema_7\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\18\qBaseDockWidgetGroup\windowDock_nSchema_7\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\18\qBaseDockWidgetGroup\windowDock_nSchema_7\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\18\qBaseDockWidgetGroup\windowDock_nSchema_7\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\18\qBaseDockWidgetGroup\windowDock_nSchema_8\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\18\qBaseDockWidgetGroup\windowDock_nSchema_8\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\18\qBaseDockWidgetGroup\windowDock_nSchema_8\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\18\qBaseDockWidgetGroup\windowDock_nSchema_8\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\18\qBaseDockWidgetGroup\windowDock_nSchema_9\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\18\qBaseDockWidgetGroup\windowDock_nSchema_9\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\18\qBaseDockWidgetGroup\windowDock_nSchema_9\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\18\qBaseDockWidgetGroup\windowDock_nSchema_9\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\19\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeMax=1 +Verdi_1\qBaseWindowNextStateGroup\19\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\19\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\19\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeMax=1 +Verdi_1\qBaseWindowNextStateGroup\19\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\19\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\19\qBaseDockWidgetGroup\windowDock_nWave_3\geometry=@ByteArray(\x1\xd9\xd0\xcb\0\x1\0\0\xff\xff\xff\xf6\0\0\0Z\0\0\n\t\0\0\x5|\0\0\0\0\0\0\0\x87\0\0\t\xff\0\0\x5r\0\0\0\0\0\0) +Verdi_1\qBaseWindowNextStateGroup\19\qBaseDockWidgetGroup\windowDock_nSchema_5\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\19\qBaseDockWidgetGroup\windowDock_nSchema_5\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\19\qBaseDockWidgetGroup\windowDock_nSchema_5\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\19\qBaseDockWidgetGroup\windowDock_nSchema_5\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\19\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\19\qBaseDockWidgetGroup\windowDock_nSchema_6\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\19\qBaseDockWidgetGroup\windowDock_nSchema_6\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\19\qBaseDockWidgetGroup\windowDock_nSchema_6\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\19\qBaseDockWidgetGroup\windowDock_nSchema_6\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\19\qBaseDockWidgetGroup\windowDock_nSchema_7\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\19\qBaseDockWidgetGroup\windowDock_nSchema_7\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\19\qBaseDockWidgetGroup\windowDock_nSchema_7\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\19\qBaseDockWidgetGroup\windowDock_nSchema_7\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\19\qBaseDockWidgetGroup\windowDock_nSchema_8\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\19\qBaseDockWidgetGroup\windowDock_nSchema_8\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\19\qBaseDockWidgetGroup\windowDock_nSchema_8\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\19\qBaseDockWidgetGroup\windowDock_nSchema_8\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\19\qBaseDockWidgetGroup\windowDock_nSchema_9\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\19\qBaseDockWidgetGroup\windowDock_nSchema_9\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\19\qBaseDockWidgetGroup\windowDock_nSchema_9\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\19\qBaseDockWidgetGroup\windowDock_nSchema_9\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\19\qBaseDockWidgetGroup\windowDock_nSchema_10\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\19\qBaseDockWidgetGroup\windowDock_nSchema_10\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\19\qBaseDockWidgetGroup\windowDock_nSchema_10\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\19\qBaseDockWidgetGroup\windowDock_nSchema_10\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\19\qBaseDockWidgetGroup\windowDock_nSchema_10\qBaseWindowBeMax=1 +Verdi_1\qBaseWindowNextStateGroup\19\qBaseDockWidgetGroup\windowDock_nSchema_10\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\19\qBaseDockWidgetGroup\windowDock_nSchema_10\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\windowDock_nWave_3\geometry=@ByteArray(\x1\xd9\xd0\xcb\0\x1\0\0\xff\xff\xff\xf6\0\0\0Z\0\0\n\t\0\0\x5|\0\0\0\0\0\0\0\x87\0\0\t\xff\0\0\x5r\0\0\0\0\0\0) +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\windowDock_nSchema_5\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\windowDock_nSchema_5\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\windowDock_nSchema_5\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\windowDock_nSchema_5\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\windowDock_nSchema_6\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\windowDock_nSchema_6\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\windowDock_nSchema_6\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\windowDock_nSchema_6\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\windowDock_nSchema_7\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\windowDock_nSchema_7\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\windowDock_nSchema_7\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\windowDock_nSchema_7\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\windowDock_nSchema_8\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\windowDock_nSchema_8\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\windowDock_nSchema_8\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\windowDock_nSchema_8\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\windowDock_nSchema_9\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\windowDock_nSchema_9\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\windowDock_nSchema_9\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\windowDock_nSchema_9\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\windowDock_nSchema_10\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\windowDock_nSchema_10\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\windowDock_nSchema_10\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\windowDock_nSchema_10\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\windowDock_nSchema_10\qBaseWindowBeMax=1 +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\windowDock_nSchema_10\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\windowDock_nSchema_10\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeMax=1 +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeMax=1 +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeMax=1 +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\windowDock_OneSearch\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\windowDock_nWave_3\geometry=@ByteArray(\x1\xd9\xd0\xcb\0\x1\0\0\xff\xff\xff\xf6\0\0\0Z\0\0\n\t\0\0\x5|\0\0\0\0\0\0\0\x87\0\0\t\xff\0\0\x5r\0\0\0\0\0\0) +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\windowDock_nSchema_5\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\windowDock_nSchema_5\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\windowDock_nSchema_5\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\windowDock_nSchema_5\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\windowDock_nSchema_6\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\windowDock_nSchema_6\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\windowDock_nSchema_6\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\windowDock_nSchema_6\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\windowDock_nSchema_7\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\windowDock_nSchema_7\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\windowDock_nSchema_7\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\windowDock_nSchema_7\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\windowDock_nSchema_8\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\windowDock_nSchema_8\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\windowDock_nSchema_8\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\windowDock_nSchema_8\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\windowDock_nSchema_9\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\windowDock_nSchema_9\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\windowDock_nSchema_9\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\windowDock_nSchema_9\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\windowDock_nSchema_10\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\windowDock_nSchema_10\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\windowDock_nSchema_10\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\windowDock_nSchema_10\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\windowDock_nSchema_10\qBaseWindowBeMax=1 +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\windowDock_nSchema_10\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\windowDock_nSchema_10\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\windowDock_nSchema_11\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\windowDock_nSchema_11\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\windowDock_nSchema_11\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\windowDock_nSchema_11\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\windowDock_nSchema_11\qBaseWindowBeMax=1 +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\windowDock_nSchema_11\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\windowDock_nSchema_11\dockIsFloating=false + +[QwMainWindow] +window\Verdi_1\layout="@ByteArray(\0\0\0\xff\0\x3\x14Q\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x2\xcb\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x2\x8d\0\0\0\x89\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\xe9\0\0\0\xc6\0\0\0k\0\0\0k\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\x1\0\0\x2\x93\0\0\am\0\0\0k\0\xff\xff\xff\0\0\0\x3\0\0\n\0\0\0\x2\x1a\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\n\0\0\0\x2,\0\xff\xff\xff\xfa\0\0\0\x2\x1\0\0\0\x3\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\x1\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\x1-\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x33\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x34\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +window\Verdi_1\geometry=@ByteArray(\x1\xd9\xd0\xcb\0\x1\0\0\xff\xff\xff\xff\0\0\0\x1b\0\0\n\0\0\0\x5z\0\0\0\0\0\0\0\0\xff\xff\xff\xfe\xff\xff\xff\xfe\0\0\0\0\x2\0) +window\Verdi_1\menubar=true +window\Verdi_1\splitters\tbvConstrDbgSplitter\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x2\0\0\0\x8d\0\0\0\x8d\x1\0\0\0\x6\x1\0\0\0\x1) +window\Verdi_1\splitters\tbvConstrRerandSplitter\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x2\0\0\0G\0\0\0\x4\x1\0\0\0\x6\x1\0\0\0\x2) +window\Verdi_1\splitters\tbvConstrOriginSplitter\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x2\0\0\0!\0\0\0\x4\x1\0\0\0\x6\x1\0\0\0\x2) +window\Verdi_1\splitters\ThreadPane\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x2\0\0\0\x37\0\0\0\x37\x1\0\0\0\x6\x1\0\0\0\x2) +window\Verdi_1\splitters\tbvInteractiveSplitter\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x2\0\0\0\x1f\0\0\0\x1f\x1\0\0\0\x6\x1\0\0\0\x2) +window\Verdi_1\splitters\tbvVSimSplitter\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x2\0\0\0\x1f\0\0\0\x1f\x1\0\0\0\x6\x1\0\0\0\x2) +window\Verdi_1\splitters\tbvTBHSplitter\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x2\0\0\0-\0\0\0?\x1\0\0\0\x6\x1\0\0\0\x2) +window\nWave_2\layout="@ByteArray(\0\0\0\xff\0\x3\x14Q\xfd\0\0\0\0\0\0\n\0\0\0\x4\x9e\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x2\0\0\0\x2\0\0\0\f\0\0\0\x12\0W\0\x41\0V\0\x45\0_\0O\0P\0\x45\0N\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x12\0W\0\x41\0V\0\x45\0_\0\x45\0\x44\0I\0T\x1\0\0\0?\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x16\0W\0\x41\0V\0\x45\0_\0\x43\0U\0R\0S\0O\0R\x1\0\0\0\xb4\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x12\0W\0\x41\0V\0\x45\0_\0V\0I\0\x45\0W\x1\0\0\x2%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\"\0W\0\x41\0V\0\x45\0_\0S\0\x45\0\x41\0R\0\x43\0H\0_\0\x45\0V\0\x45\0N\0T\x1\0\0\x2\x7f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0W\0\x41\0V\0\x45\0_\0R\0\x45\0P\0L\0\x41\0Y\0_\0S\0I\0M\0\0\0\x5K\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x12\0W\0\x41\0V\0\x45\0_\0G\0O\0T\0O\x1\0\0\x3\x1b\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0W\0\x41\0V\0\x45\0_\0G\0O\0T\0O\0_\0N\0\x41\0M\0\x45\0\x44\0_\0M\0\x41\0R\0K\0\x45\0R\0\0\0\x5\xed\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0W\0\x41\0V\0\x45\0_\0T\0R\0\x41\0N\0S\0\x41\0\x43\0T\0I\0O\0N\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0W\0\x41\0V\0\x45\0_\0\x45\0X\0P\0L\0O\0R\0\x45\0_\0P\0R\0O\0P\0\x45\0R\0T\0Y\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0W\0\x41\0V\0\x45\0_\0\x46\0I\0N\0\x44\0_\0S\0I\0G\0N\0\x41\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x18\0W\0\x41\0V\0\x45\0_\0P\0R\0I\0M\0\x41\0R\0Y\0\0\0\x6\x1b\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x32\0S\0\x45\0L\0\x45\0\x43\0T\0I\0O\0N\0_\0M\0\x45\0S\0S\0\x41\0G\0\x45\0_\0T\0O\0O\0L\0\x42\0\x41\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +window\nWave_2\geometry=@ByteArray(\x1\xd9\xd0\xcb\0\x1\0\0\0\0\0\0\0\0\0\x1b\0\0\t\xff\0\0\x4\xea\0\0\0\0\0\0\0\x1b\0\0\t\xff\0\0\x4\xea\0\0\0\0\0\0) +window\nWave_2\menubar=true +window\nWave_2\splitters\splitter_5\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x83\x1\0\0\0\x1\0\0\0\0\x2) +window\nWave_2\splitters\splitter_2\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x2\0\0\0\xd8\0\0\t(\x1\0\0\0\x1\0\0\0\0\x1) +window\nWave_2\splitters\splitter\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x3\0\0\0?\0\0\0\x1\0\0\b\xe6\x1\0\0\0\x1\0\0\0\0\x1) +window\nWave_2\splitters\Pane_Upper\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x2\0\0\0\xd8\0\0\t%\x1\0\0\0\x1\0\0\0\0\x1) +window\nWave_2\splitters\splitter_3\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x2\0\0\0?\0\0\tW\x1\0\0\0\x1\0\0\0\0\x1) +window\nWave_2\splitters\wholeSplitter\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x3\0\0\0O\0\0\0\xa3\0\0\0\x4\x1\0\0\0\x6\x1\0\0\0\x1) +window\nWave_2\splitters\middleSplitter\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0\x4\x1\0\0\0\x6\x1\0\0\0\x2) +window\nMemory_3\layout=@ByteArray(\0\0\0\xff\0\x3\x14Q\xfd\0\0\0\0\0\0\x4\xfd\0\0\x1\xda\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x2\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0M\0\x45\0M\0_\0T\0O\0O\0L\0\x42\0\x41\0R\0_\0U\0P\0P\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x34\0N\0M\0\x45\0M\0_\0T\0O\0O\0L\0\x42\0\x41\0R\0_\0U\0P\0P\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0_\0\x32\x1\0\0\0?\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x34\0N\0M\0\x45\0M\0_\0T\0O\0O\0L\0\x42\0\x41\0R\0_\0U\0P\0P\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0_\0\x33\x1\0\0\x1\xd3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x34\0N\0M\0\x45\0M\0_\0T\0O\0O\0L\0\x42\0\x41\0R\0_\0L\0O\0W\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0_\0\x31\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0) +window\nMemory_3\geometry=@ByteArray(\x1\xd9\xd0\xcb\0\x1\0\0\0\0\0\0\0\0\0\x1b\0\0\x4\xfc\0\0\x2@\0\0\0\0\0\0\0\x1b\0\0\x4\xfc\0\0\x2@\0\0\0\0\0\0) +window\nMemory_3\menubar=true +window\nMemory_4\layout=@ByteArray(\0\0\0\xff\0\x3\x14Q\xfd\0\0\0\0\0\0\x4\xfd\0\0\x1\xda\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x2\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0M\0\x45\0M\0_\0T\0O\0O\0L\0\x42\0\x41\0R\0_\0U\0P\0P\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x34\0N\0M\0\x45\0M\0_\0T\0O\0O\0L\0\x42\0\x41\0R\0_\0U\0P\0P\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0_\0\x32\x1\0\0\0?\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x34\0N\0M\0\x45\0M\0_\0T\0O\0O\0L\0\x42\0\x41\0R\0_\0U\0P\0P\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0_\0\x33\x1\0\0\x1\xd3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x34\0N\0M\0\x45\0M\0_\0T\0O\0O\0L\0\x42\0\x41\0R\0_\0L\0O\0W\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0_\0\x31\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0) +window\nMemory_4\geometry=@ByteArray(\x1\xd9\xd0\xcb\0\x1\0\0\0\0\0\0\0\0\0\x1b\0\0\x4\xfc\0\0\x2@\0\0\0\0\0\0\0\x1b\0\0\x4\xfc\0\0\x2@\0\0\0\0\0\0) +window\nMemory_4\menubar=true + +[qBaseWindow_saveRestoreSession_group] +10=/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/digital_top/verdiLog/novas_autosave.ses + +[qDockerWindow_C] +Verdi_1\position.x=-1 +Verdi_1\position.y=27 +Verdi_1\width=2560 +Verdi_1\height=1337 + +[nWave_3_qBaseWindow_Be_Window_Group] +geometry_x=-118 +geometry_y=118 +geometry_width=2560 +geometry_height=1260 diff --git a/tb/chip_top/verdiLog/.diagnose.oneSearch b/tb/chip_top/verdiLog/.diagnose.oneSearch new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/verdiLog/.tbvBP.tmp b/tb/chip_top/verdiLog/.tbvBP.tmp new file mode 100644 index 0000000..edc3ac0 --- /dev/null +++ b/tb/chip_top/verdiLog/.tbvBP.tmp @@ -0,0 +1 @@ +stop -line 132 -file /home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/top/channel_top.sv diff --git a/tb/chip_top/verdiLog/ToNetlist.log b/tb/chip_top/verdiLog/ToNetlist.log new file mode 100644 index 0000000..e709d4f --- /dev/null +++ b/tb/chip_top/verdiLog/ToNetlist.log @@ -0,0 +1 @@ +Compiling Netlist: Failed to create net (slv[25].slave[0:95]) - Create operation net failed: bit range not inside declaration net diff --git a/tb/chip_top/verdiLog/compiler.log b/tb/chip_top/verdiLog/compiler.log new file mode 100644 index 0000000..aa2cccc --- /dev/null +++ b/tb/chip_top/verdiLog/compiler.log @@ -0,0 +1,109 @@ +*design* DebussyLib (btIdent Verdi_O-2018.09-SP2) +Command arguments: + +define+verilog + -sverilog + -f files.f + ../../rtl/memory/sram_if.sv + ../../rtl/awg/awg_ctrl.v + ../../rtl/awg/awg_top.sv + ../../rtl/awg/codeword_decode.v + ../../rtl/awg/ctrl_regfile.v + ../../rtl/awg/param_lut.sv + ../../rtl/awg/modout_mux.v + ../../rtl/clk/intpll_regfile.v + ../../rtl/comm/sirv_gnrl_dffs.v + ../../rtl/comm/sirv_gnrl_xchecker.v + ../../rtl/dac_regfile/dac_regfile.v + ../../rtl/debug/debug_sample.sv + ../../rtl/debug/debug_top.sv + ../../rtl/define/chip_define.v + ../../rtl/define/chip_undefine.v + ../../rtl/memory/dpram.v + ../../rtl/memory/dpram_model.v + ../../rtl/memory/sram_dmux.sv + ../../rtl/memory/tsdn28hpcpuhdb128x128m4mw_170a_ffg0p99v0c.v + ../../rtl/memory/tsdn28hpcpuhdb4096x32m4mw_170a_ffg0p99v0c.v + ../../rtl/memory/tsdn28hpcpuhdb64x32m4mw_170a_ffg0p99v0c.v + ../../rtl/memory/tsmc_dpram.v + ../../rtl/modem/ampmod.v + ../../rtl/modem/baisset.v + ../../rtl/modem/freqmod.v + ../../rtl/nco/coef_c.v + ../../rtl/nco/coef_s.v + ../../rtl/nco/cos_op.v + ../../rtl/nco/nco.v + ../../rtl/nco/nco_ch1.v + ../../rtl/nco/p_nco.v + ../../rtl/nco/p_nco_ch1.v + ../../rtl/nco/ph2amp.v + ../../rtl/nco/pipe_acc_48bit.v + ../../rtl/nco/pipe_add_48bit.v + ../../rtl/nco/sin_op.v + ../../rtl/perips/DW03_updn_ctr.v + ../../rtl/perips/mcu_regfile.sv + ../../rtl/perips/qbmcu_busdecoder.v + ../../rtl/qubitmcu/qbmcu.v + ../../rtl/qubitmcu/qbmcu_datalock.v + ../../rtl/qubitmcu/qbmcu_decode.v + ../../rtl/qubitmcu/qbmcu_defines.v + ../../rtl/qubitmcu/qbmcu_exu.v + ../../rtl/qubitmcu/qbmcu_exu_alu.v + ../../rtl/qubitmcu/qbmcu_exu_bjp.v + ../../rtl/qubitmcu/qbmcu_exu_dpath.v + ../../rtl/qubitmcu/qbmcu_exu_ext.v + ../../rtl/qubitmcu/qbmcu_exu_lsuagu.v + ../../rtl/qubitmcu/qbmcu_fsm.v + ../../rtl/qubitmcu/qbmcu_ifu.v + ../../rtl/qubitmcu/qbmcu_regfile.v + ../../rtl/qubitmcu/qbmcu_undefines.v + ../../rtl/qubitmcu/qbmcu_wbck.v + ../../rtl/rstgen/rst_gen_unit.v + ../../rtl/rstgen/rst_sync.v + ../../rtl/spi/spi_bus_decoder.sv + ../../rtl/spi/spi_pll.v + ../../rtl/spi/spi_slave.v + ../../rtl/spi/spi_sys.v + ../../rtl/sync/sync_buf.sv + ../../rtl/system_regfile/system_regfile.v + ../../rtl/top/channel_top.sv + ../../rtl/top/digital_top.sv + ../../rtl/top/xyz_chip_top.v + ../../rtl/xy_dsp/dacif/dacif.v + ../../rtl/xy_dsp/dsp_top/xy_dsp.v + ../../rtl/xy_dsp/duc/duc_hb1_pipe_shift.v + ../../rtl/xy_dsp/duc/duc_hb1_top.v + ../../rtl/xy_dsp/duc/duc_hb2_pipe_shift.v + ../../rtl/xy_dsp/duc/duc_hb2_top_s.v + ../../rtl/xy_dsp/duc/duc_hb3_pipe_shift.v + ../../rtl/xy_dsp/duc/duc_hb3_top_s2.v + ../../rtl/xy_dsp/duc/duc_hb4_pipe_shift.v + ../../rtl/xy_dsp/duc/duc_hb4_top_s3.v + ../../rtl/xy_dsp/duc/duc4.v + ../../rtl/xy_dsp/qam/qam_top.v + ../../rtl/xy_dsp/qam/ssb.v + ../../rtl/top/z_data_mux.v + ../../rtl/dem/DAC_DEM.v + ../../rtl/dem/DAC_DEM_16.v + ../../rtl/dem/DAC_DEM_4.v + ../../sim/chip_top/TB.sv + ../../sim/chip_top/DW_mult_pipe.v + ../../sim/chip_top/DW01_addsub.v + ../../sim/chip_top/DW02_mult.v + ../../sim/chip_top/clk_gen.v + ../../sim/chip_top/spi_if.sv + ../../sim/chip_top/thermo15_binary4.v + ../../sim/chip_top/thermo7_binary3.v + ../../sim/chip_top/thermo2binary_top.v + -top + TB + + +*Warning* macro MCU_INSTR_FILE redefined from ("../../cfgdata/instrmem/RabiFreqAmp_bin.txt") to ("../../cfgdata/instrmem/WaveHoldSingle_bin.txt") +"../../sim/chip_top/TB.sv", 59: +Highest level modules: +sirv_gnrl_dffl +sirv_gnrl_ltch +TB +DW01_addsub + +Total 0 error(s), 1 warning(s) diff --git a/tb/chip_top/verdiLog/coredump b/tb/chip_top/verdiLog/coredump new file mode 100644 index 0000000..1616df7 --- /dev/null +++ b/tb/chip_top/verdiLog/coredump @@ -0,0 +1,443 @@ +91158: /home/synopsys/verdi/Verdi_O-2018.09-SP2/platform/LINUXAMD64/bin/Novas -sverilog -f files.f -top TB -nologo +0000000000400000 182584K r-x-- novas +000000000b84d000 444K r-x-- novas +000000000b8bc000 12544K rwx-- novas +000000000c4fc000 81756K rwx-- [ anon ] +0000000011ebc000 215860K rwx-- [ anon ] +00007fc4e0000000 8988K rwx-- [ anon ] +00007fc4e08c7000 56548K ----- [ anon ] +00007fc4e4000000 13896K rwx-- [ anon ] +00007fc4e4d92000 51640K ----- [ anon ] +00007fc4e8000000 65200K rwx-- [ anon ] +00007fc4ebfac000 336K ----- [ anon ] +00007fc4ec000000 5560K rwx-- [ anon ] +00007fc4ec56e000 59976K ----- [ anon ] +00007fc4f0000000 6384K rwx-- [ anon ] +00007fc4f063c000 59152K ----- [ anon ] +00007fc4f4ff8000 4K ----- [ anon ] +00007fc4f4ff9000 6144K rwx-- [ anon ] +00007fc4f55f9000 4K ----- [ anon ] +00007fc4f55fa000 6144K rwx-- [ anon ] +00007fc4f5bfa000 4K ----- [ anon ] +00007fc4f5bfb000 6144K rwx-- [ anon ] +00007fc4f61fb000 4K ----- [ anon ] +00007fc4f61fc000 6144K rwx-- [ anon ] +00007fc4f67fc000 4K ----- [ anon ] +00007fc4f67fd000 6144K rwx-- [ anon ] +00007fc4f6dfd000 4K ----- [ anon ] +00007fc4f6dfe000 6144K rwx-- [ anon ] +00007fc4f73fe000 4K ----- [ anon ] +00007fc4f73ff000 6144K rwx-- [ anon ] +00007fc4f79ff000 4K ----- [ anon ] +00007fc4f7a00000 6144K rwx-- [ anon ] +00007fc4f8000000 132K rwx-- [ anon ] +00007fc4f8021000 65404K ----- [ anon ] +00007fc4fc000000 132K rwx-- [ anon ] +00007fc4fc021000 65404K ----- [ anon ] +00007fc500000000 292K rwx-- [ anon ] +00007fc500049000 65244K ----- [ anon ] +00007fc50440f000 4K ----- [ anon ] +00007fc504410000 6144K rwx-- [ anon ] +00007fc504a10000 4K ----- [ anon ] +00007fc504a11000 8192K rwx-- [ anon ] +00007fc505211000 4K ----- [ anon ] +00007fc505212000 8192K rwx-- [ anon ] +00007fc505a12000 4K ----- [ anon ] +00007fc505a13000 8192K rwx-- [ anon ] +00007fc506413000 4K ----- [ anon ] +00007fc506414000 6144K rwx-- [ anon ] +00007fc506a14000 4K ----- [ anon ] +00007fc506a15000 8192K rwx-- [ anon ] +00007fc507215000 396K r-x-- libtiff.so.3.9.4 +00007fc507278000 2044K ----- libtiff.so.3.9.4 +00007fc507477000 8K r-x-- libtiff.so.3.9.4 +00007fc507479000 4K rwx-- libtiff.so.3.9.4 +00007fc50747a000 24K r-x-- libqtiff.so +00007fc507480000 2048K ----- libqtiff.so +00007fc507680000 4K rwx-- libqtiff.so +00007fc507681000 16K r-x-- libqtga.so +00007fc507685000 2048K ----- libqtga.so +00007fc507885000 4K rwx-- libqtga.so +00007fc507886000 340K r-x-- libQtSvg.so.4.8.7 +00007fc5078db000 2048K ----- libQtSvg.so.4.8.7 +00007fc507adb000 8K r-x-- libQtSvg.so.4.8.7 +00007fc507add000 4K rwx-- libQtSvg.so.4.8.7 +00007fc507ade000 20K r-x-- libqsvg.so +00007fc507ae3000 2044K ----- libqsvg.so +00007fc507ce2000 4K rwx-- libqsvg.so +00007fc507ce3000 436K r-x-- libmng.so.1.0.0 +00007fc507d50000 2048K ----- libmng.so.1.0.0 +00007fc507f50000 12K r-x-- libmng.so.1.0.0 +00007fc507f53000 8K rwx-- libmng.so.1.0.0 +00007fc507f55000 20K r-x-- libqmng.so +00007fc507f5a000 2048K ----- libqmng.so +00007fc50815a000 4K rwx-- libqmng.so +00007fc50815b000 132K r-x-- libjpeg.so.62.0.0 +00007fc50817c000 2048K ----- libjpeg.so.62.0.0 +00007fc50837c000 4K rwx-- libjpeg.so.62.0.0 +00007fc50837d000 28K r-x-- libqjpeg.so +00007fc508384000 2044K ----- libqjpeg.so +00007fc508583000 4K rwx-- libqjpeg.so +00007fc508584000 24K r-x-- libqico.so +00007fc50858a000 2048K ----- libqico.so +00007fc50878a000 4K rwx-- libqico.so +00007fc50878b000 24K r-x-- libqgif.so +00007fc508791000 2048K ----- libqgif.so +00007fc508991000 4K rwx-- libqgif.so +00007fc508992000 92K r-x-- libelf-0.176.so +00007fc5089a9000 2044K ----- libelf-0.176.so +00007fc508ba8000 4K r-x-- libelf-0.176.so +00007fc508ba9000 4K rwx-- libelf-0.176.so +00007fc508baa000 16K r-x-- libattr.so.1.1.0 +00007fc508bae000 2044K ----- libattr.so.1.1.0 +00007fc508dad000 4K r-x-- libattr.so.1.1.0 +00007fc508dae000 4K rwx-- libattr.so.1.1.0 +00007fc508daf000 240K r-x-- libblkid.so.1.1.0 +00007fc508deb000 2044K ----- libblkid.so.1.1.0 +00007fc508fea000 12K r-x-- libblkid.so.1.1.0 +00007fc508fed000 4K rwx-- libblkid.so.1.1.0 +00007fc508fee000 4K rwx-- [ anon ] +00007fc508fef000 312K r-x-- libdw-0.176.so +00007fc50903d000 2048K ----- libdw-0.176.so +00007fc50923d000 8K r-x-- libdw-0.176.so +00007fc50923f000 4K rwx-- libdw-0.176.so +00007fc509240000 16K r-x-- libgpg-error.so.0.10.0 +00007fc509244000 2044K ----- libgpg-error.so.0.10.0 +00007fc509443000 4K r-x-- libgpg-error.so.0.10.0 +00007fc509444000 4K rwx-- libgpg-error.so.0.10.0 +00007fc509445000 500K r-x-- libgcrypt.so.11.8.2 +00007fc5094c2000 2044K ----- libgcrypt.so.11.8.2 +00007fc5096c1000 4K r-x-- libgcrypt.so.11.8.2 +00007fc5096c2000 12K rwx-- libgcrypt.so.11.8.2 +00007fc5096c5000 4K rwx-- [ anon ] +00007fc5096c6000 56K r-x-- liblz4.so.1.8.3 +00007fc5096d4000 2044K ----- liblz4.so.1.8.3 +00007fc5098d3000 4K r-x-- liblz4.so.1.8.3 +00007fc5098d4000 4K rwx-- liblz4.so.1.8.3 +00007fc5098d5000 148K r-x-- liblzma.so.5.2.2 +00007fc5098fa000 2044K ----- liblzma.so.5.2.2 +00007fc509af9000 4K r-x-- liblzma.so.5.2.2 +00007fc509afa000 4K rwx-- liblzma.so.5.2.2 +00007fc509afb000 16K r-x-- libcap.so.2.22 +00007fc509aff000 2044K ----- libcap.so.2.22 +00007fc509cfe000 4K r-x-- libcap.so.2.22 +00007fc509cff000 4K rwx-- libcap.so.2.22 +00007fc509d00000 256K r-x-- libmount.so.1.1.0 +00007fc509d40000 2048K ----- libmount.so.1.1.0 +00007fc509f40000 4K r-x-- libmount.so.1.1.0 +00007fc509f41000 4K rwx-- libmount.so.1.1.0 +00007fc509f42000 4K rwx-- [ anon ] +00007fc509f43000 88K r-x-- libresolv-2.17.so +00007fc509f59000 2048K ----- libresolv-2.17.so +00007fc50a159000 4K r-x-- libresolv-2.17.so +00007fc50a15a000 4K rwx-- libresolv-2.17.so +00007fc50a15b000 8K rwx-- [ anon ] +00007fc50a15d000 144K r-x-- libselinux.so.1 +00007fc50a181000 2044K ----- libselinux.so.1 +00007fc50a380000 4K r-x-- libselinux.so.1 +00007fc50a381000 4K rwx-- libselinux.so.1 +00007fc50a382000 8K rwx-- [ anon ] +00007fc50a384000 384K r-x-- libpcre.so.1.2.0 +00007fc50a3e4000 2048K ----- libpcre.so.1.2.0 +00007fc50a5e4000 4K r-x-- libpcre.so.1.2.0 +00007fc50a5e5000 4K rwx-- libpcre.so.1.2.0 +00007fc50a5e6000 12K r-x-- libgmodule-2.0.so.0.5600.1 +00007fc50a5e9000 2044K ----- libgmodule-2.0.so.0.5600.1 +00007fc50a7e8000 4K r-x-- libgmodule-2.0.so.0.5600.1 +00007fc50a7e9000 4K rwx-- libgmodule-2.0.so.0.5600.1 +00007fc50a7ea000 28K r-x-- libffi.so.6.0.1 +00007fc50a7f1000 2044K ----- libffi.so.6.0.1 +00007fc50a9f0000 4K r-x-- libffi.so.6.0.1 +00007fc50a9f1000 4K rwx-- libffi.so.6.0.1 +00007fc50a9f2000 188K r-x-- libsystemd.so.0.6.0 +00007fc50aa21000 2048K ----- libsystemd.so.0.6.0 +00007fc50ac21000 4K r-x-- libsystemd.so.0.6.0 +00007fc50ac22000 4K rwx-- libsystemd.so.0.6.0 +00007fc50ac23000 1104K r-x-- libglib-2.0.so.0.5600.1 +00007fc50ad37000 2044K ----- libglib-2.0.so.0.5600.1 +00007fc50af36000 4K r-x-- libglib-2.0.so.0.5600.1 +00007fc50af37000 4K rwx-- libglib-2.0.so.0.5600.1 +00007fc50af38000 4K rwx-- [ anon ] +00007fc50af39000 316K r-x-- libgobject-2.0.so.0.5600.1 +00007fc50af88000 2048K ----- libgobject-2.0.so.0.5600.1 +00007fc50b188000 4K r-x-- libgobject-2.0.so.0.5600.1 +00007fc50b189000 4K rwx-- libgobject-2.0.so.0.5600.1 +00007fc50b18a000 1624K r-x-- libgio-2.0.so.0.5600.1 +00007fc50b320000 2048K ----- libgio-2.0.so.0.5600.1 +00007fc50b520000 20K r-x-- libgio-2.0.so.0.5600.1 +00007fc50b525000 12K rwx-- libgio-2.0.so.0.5600.1 +00007fc50b528000 8K rwx-- [ anon ] +00007fc50b52a000 312K r-x-- libdbus-1.so.3.14.14 +00007fc50b578000 2044K ----- libdbus-1.so.3.14.14 +00007fc50b777000 4K r-x-- libdbus-1.so.3.14.14 +00007fc50b778000 4K rwx-- libdbus-1.so.3.14.14 +00007fc50b779000 4K rwx-- [ anon ] +00007fc50b77a000 152K r-x-- libdbus-glib-1.so.2.2.2 +00007fc50b7a0000 2048K ----- libdbus-glib-1.so.2.2.2 +00007fc50b9a0000 4K r-x-- libdbus-glib-1.so.2.2.2 +00007fc50b9a1000 4K rwx-- libdbus-glib-1.so.2.2.2 +00007fc50b9a2000 6520K r-x-- novas.rcc +00007fc50c000000 284K rwx-- [ anon ] +00007fc50c047000 65252K ----- [ anon ] +00007fc5101ba000 108K r-x-- LiberationMono-Regular.ttf +00007fc5101d5000 268K rwx-- [ anon ] +00007fc510226000 24K rwx-- [ anon ] +00007fc51022c000 140K r-x-- LiberationSans-Regular.ttf +00007fc51024f000 60K r-x-- VeraBd.ttf +00007fc51025e000 8K r-x-- libXinerama.so.1.0.0 +00007fc510260000 2044K ----- libXinerama.so.1.0.0 +00007fc51045f000 4K r-x-- libXinerama.so.1.0.0 +00007fc510460000 4K rwx-- libXinerama.so.1.0.0 +00007fc510461000 40K r-x-- libXrandr.so.2.2.0 +00007fc51046b000 2044K ----- libXrandr.so.2.2.0 +00007fc51066a000 4K r-x-- libXrandr.so.2.2.0 +00007fc51066b000 4K rwx-- libXrandr.so.2.2.0 +00007fc51066c000 16K rwx-- [ anon ] +00007fc510670000 40K r-x-- c0419bt_.pfb +00007fc51067a000 68K r-x-- Vera.ttf +00007fc51068b000 8K r-x-- UTF-16.so +00007fc51068d000 2048K ----- UTF-16.so +00007fc51088d000 4K r-x-- UTF-16.so +00007fc51088e000 4K rwx-- UTF-16.so +00007fc51088f000 4K ----- [ anon ] +00007fc510890000 8192K rwx-- [ anon ] +00007fc511090000 20K r-x-- libXfixes.so.3.1.0 +00007fc511095000 2044K ----- libXfixes.so.3.1.0 +00007fc511294000 4K r-x-- libXfixes.so.3.1.0 +00007fc511295000 4K rwx-- libXfixes.so.3.1.0 +00007fc511296000 36K r-x-- libXcursor.so.1.0.2 +00007fc51129f000 2048K ----- libXcursor.so.1.0.2 +00007fc51149f000 4K r-x-- libXcursor.so.1.0.2 +00007fc5114a0000 4K rwx-- libXcursor.so.1.0.2 +00007fc5114a1000 4K ----- [ anon ] +00007fc5114a2000 8192K rwx-- [ anon ] +00007fc511ca2000 4K ----- [ anon ] +00007fc511ca3000 8192K rwx-- [ anon ] +00007fc5124a3000 48K r-x-- libnss_files-2.17.so +00007fc5124af000 2044K ----- libnss_files-2.17.so +00007fc5126ae000 4K r-x-- libnss_files-2.17.so +00007fc5126af000 4K rwx-- libnss_files-2.17.so +00007fc5126b0000 1052K rwx-- [ anon ] +00007fc5127b7000 8K r-x-- libXau.so.6.0.0 +00007fc5127b9000 2048K ----- libXau.so.6.0.0 +00007fc5129b9000 4K r-x-- libXau.so.6.0.0 +00007fc5129ba000 4K rwx-- libXau.so.6.0.0 +00007fc5129bb000 16K r-x-- libuuid.so.1.3.0 +00007fc5129bf000 2044K ----- libuuid.so.1.3.0 +00007fc512bbe000 4K r-x-- libuuid.so.1.3.0 +00007fc512bbf000 4K rwx-- libuuid.so.1.3.0 +00007fc512bc0000 156K r-x-- libexpat.so.1.6.0 +00007fc512be7000 2048K ----- libexpat.so.1.6.0 +00007fc512de7000 8K r-x-- libexpat.so.1.6.0 +00007fc512de9000 4K rwx-- libexpat.so.1.6.0 +00007fc512dea000 156K r-x-- libxcb.so.1.1.0 +00007fc512e11000 2044K ----- libxcb.so.1.1.0 +00007fc513010000 4K r-x-- libxcb.so.1.1.0 +00007fc513011000 4K rwx-- libxcb.so.1.1.0 +00007fc513012000 36K r-x-- libXrender.so.1.3.0 +00007fc51301b000 2048K ----- libXrender.so.1.3.0 +00007fc51321b000 4K r-x-- libXrender.so.1.3.0 +00007fc51321c000 4K rwx-- libXrender.so.1.3.0 +00007fc51321d000 84K r-x-- libgcc_s.so.1 +00007fc513232000 2048K ----- libgcc_s.so.1 +00007fc513432000 4K rwx-- libgcc_s.so.1 +00007fc513433000 92K r-x-- libICE.so.6.3.0 +00007fc51344a000 2044K ----- libICE.so.6.3.0 +00007fc513649000 4K r-x-- libICE.so.6.3.0 +00007fc51364a000 4K rwx-- libICE.so.6.3.0 +00007fc51364b000 16K rwx-- [ anon ] +00007fc51364f000 28K r-x-- libSM.so.6.0.1 +00007fc513656000 2044K ----- libSM.so.6.0.1 +00007fc513855000 4K r-x-- libSM.so.6.0.1 +00007fc513856000 4K rwx-- libSM.so.6.0.1 +00007fc513857000 164K r-x-- libpng15.so.15.13.0 +00007fc513880000 2048K ----- libpng15.so.15.13.0 +00007fc513a80000 4K r-x-- libpng15.so.15.13.0 +00007fc513a81000 4K rwx-- libpng15.so.15.13.0 +00007fc513a82000 60K r-x-- libbz2.so.1.0.6 +00007fc513a91000 2044K ----- libbz2.so.1.0.6 +00007fc513c90000 4K r-x-- libbz2.so.1.0.6 +00007fc513c91000 4K rwx-- libbz2.so.1.0.6 +00007fc513c92000 84K r-x-- libz.so.1.2.7 +00007fc513ca7000 2044K ----- libz.so.1.2.7 +00007fc513ea6000 4K r-x-- libz.so.1.2.7 +00007fc513ea7000 4K rwx-- libz.so.1.2.7 +00007fc513ea8000 1808K r-x-- libc-2.17.so +00007fc51406c000 2044K ----- libc-2.17.so +00007fc51426b000 16K r-x-- libc-2.17.so +00007fc51426f000 8K rwx-- libc-2.17.so +00007fc514271000 20K rwx-- [ anon ] +00007fc514276000 1028K r-x-- libm-2.17.so +00007fc514377000 2044K ----- libm-2.17.so +00007fc514576000 4K r-x-- libm-2.17.so +00007fc514577000 4K rwx-- libm-2.17.so +00007fc514578000 152K r-x-- libpng12.so.0.50.0 +00007fc51459e000 2044K ----- libpng12.so.0.50.0 +00007fc51479d000 4K r-x-- libpng12.so.0.50.0 +00007fc51479e000 4K rwx-- libpng12.so.0.50.0 +00007fc51479f000 28K r-x-- librt-2.17.so +00007fc5147a6000 2044K ----- librt-2.17.so +00007fc5149a5000 4K r-x-- librt-2.17.so +00007fc5149a6000 4K rwx-- librt-2.17.so +00007fc5149a7000 92K r-x-- libpthread-2.17.so +00007fc5149be000 2044K ----- libpthread-2.17.so +00007fc514bbd000 4K r-x-- libpthread-2.17.so +00007fc514bbe000 4K rwx-- libpthread-2.17.so +00007fc514bbf000 16K rwx-- [ anon ] +00007fc514bc3000 40K r-x-- libnuma.so.1.0.0 +00007fc514bcd000 2048K ----- libnuma.so.1.0.0 +00007fc514dcd000 4K r-x-- libnuma.so.1.0.0 +00007fc514dce000 4K rwx-- libnuma.so.1.0.0 +00007fc514dcf000 92K r-x-- libnsl-2.17.so +00007fc514de6000 2044K ----- libnsl-2.17.so +00007fc514fe5000 4K r-x-- libnsl-2.17.so +00007fc514fe6000 4K rwx-- libnsl-2.17.so +00007fc514fe7000 8K rwx-- [ anon ] +00007fc514fe9000 256K r-x-- libfontconfig.so.1.11.1 +00007fc515029000 2044K ----- libfontconfig.so.1.11.1 +00007fc515228000 8K r-x-- libfontconfig.so.1.11.1 +00007fc51522a000 4K rwx-- libfontconfig.so.1.11.1 +00007fc51522b000 68K r-x-- libXext.so.6.4.0 +00007fc51523c000 2044K ----- libXext.so.6.4.0 +00007fc51543b000 4K r-x-- libXext.so.6.4.0 +00007fc51543c000 4K rwx-- libXext.so.6.4.0 +00007fc51543d000 1248K r-x-- libX11.so.6.3.0 +00007fc515575000 2048K ----- libX11.so.6.3.0 +00007fc515775000 4K r-x-- libX11.so.6.3.0 +00007fc515776000 20K rwx-- libX11.so.6.3.0 +00007fc51577b000 96K r-x-- libXmu.so.6.2.0 +00007fc515793000 2048K ----- libXmu.so.6.2.0 +00007fc515993000 4K r-x-- libXmu.so.6.2.0 +00007fc515994000 4K rwx-- libXmu.so.6.2.0 +00007fc515995000 4K rwx-- [ anon ] +00007fc515996000 388K r-x-- libXt.so.6.0.0 +00007fc5159f7000 2044K ----- libXt.so.6.0.0 +00007fc515bf6000 4K r-x-- libXt.so.6.0.0 +00007fc515bf7000 20K rwx-- libXt.so.6.0.0 +00007fc515bfc000 4K rwx-- [ anon ] +00007fc515bfd000 84K r-x-- libXft.so.2.3.2 +00007fc515c12000 2044K ----- libXft.so.2.3.2 +00007fc515e11000 4K r-x-- libXft.so.2.3.2 +00007fc515e12000 4K rwx-- libXft.so.2.3.2 +00007fc515e13000 8K r-x-- libXss.so.1.0.0 +00007fc515e15000 2048K ----- libXss.so.1.0.0 +00007fc516015000 4K r-x-- libXss.so.1.0.0 +00007fc516016000 4K rwx-- libXss.so.1.0.0 +00007fc516017000 1476K r-x-- libstdc++.so.6 +00007fc516188000 2048K ----- libstdc++.so.6 +00007fc516388000 40K r-x-- libstdc++.so.6 +00007fc516392000 8K rwx-- libstdc++.so.6 +00007fc516394000 16K rwx-- [ anon ] +00007fc516398000 1688K r-x-- libsimprofile_verdi.so +00007fc51653e000 2044K ----- libsimprofile_verdi.so +00007fc51673d000 52K r-x-- libsimprofile_verdi.so +00007fc51674a000 4K rwx-- libsimprofile_verdi.so +00007fc51674b000 20K rwx-- [ anon ] +00007fc516750000 208K r-x-- libQtSql.so.4.8.5 +00007fc516784000 2044K ----- libQtSql.so.4.8.5 +00007fc516983000 12K rwx-- libQtSql.so.4.8.5 +00007fc516986000 2564K r-x-- libQt3Support.so.4.8.5 +00007fc516c07000 2048K ----- libQt3Support.so.4.8.5 +00007fc516e07000 124K rwx-- libQt3Support.so.4.8.5 +00007fc516e26000 1048K r-x-- libQtNetwork.so.4.8.5 +00007fc516f2c000 2044K ----- libQtNetwork.so.4.8.5 +00007fc51712b000 36K rwx-- libQtNetwork.so.4.8.5 +00007fc517134000 21820K r-x-- libQtWebKit.so.4.9.4 +00007fc518683000 2048K ----- libQtWebKit.so.4.9.4 +00007fc518883000 1632K rwx-- libQtWebKit.so.4.9.4 +00007fc518a1b000 168K rwx-- [ anon ] +00007fc518a45000 224K r-x-- libQtXml.so.4.8.5 +00007fc518a7d000 2044K ----- libQtXml.so.4.8.5 +00007fc518c7c000 12K rwx-- libQtXml.so.4.8.5 +00007fc518c7f000 2600K r-x-- libQtCore.so.4.8.5 +00007fc518f09000 2044K ----- libQtCore.so.4.8.5 +00007fc519108000 60K rwx-- libQtCore.so.4.8.5 +00007fc519117000 4K rwx-- [ anon ] +00007fc519118000 9524K r-x-- libQtGui.so.4.8.5 +00007fc519a65000 2044K ----- libQtGui.so.4.8.5 +00007fc519c64000 340K rwx-- libQtGui.so.4.8.5 +00007fc519cb9000 12K rwx-- [ anon ] +00007fc519cbc000 84K r-x-- libQtSolutions_MotifExtension-2.7.so.1.0.0 +00007fc519cd1000 2044K ----- libQtSolutions_MotifExtension-2.7.so.1.0.0 +00007fc519ed0000 8K rwx-- libQtSolutions_MotifExtension-2.7.so.1.0.0 +00007fc519ed2000 732K r-x-- libfreetype.so.6.14.0 +00007fc519f89000 2048K ----- libfreetype.so.6.14.0 +00007fc51a189000 28K r-x-- libfreetype.so.6.14.0 +00007fc51a190000 4K rwx-- libfreetype.so.6.14.0 +00007fc51a191000 1028K r-x-- libvfs.so +00007fc51a292000 2044K ----- libvfs.so +00007fc51a491000 28K r-x-- libvfs.so +00007fc51a498000 4K rwx-- libvfs.so +00007fc51a499000 20K rwx-- [ anon ] +00007fc51a49e000 8K r-x-- libdl-2.17.so +00007fc51a4a0000 2048K ----- libdl-2.17.so +00007fc51a6a0000 4K r-x-- libdl-2.17.so +00007fc51a6a1000 4K rwx-- libdl-2.17.so +00007fc51a6a2000 136K r-x-- ld-2.17.so +00007fc51a6c4000 48K rwx-- [ anon ] +00007fc51a6d0000 20K r-x-- access.rcc +00007fc51a6d5000 12K r-xs- 25052d8b-0a4d-4120-b7c0-49c39777638f-le64.cache-7 +00007fc51a6d8000 8K r-xs- b9d6a7e6-d9c6-447f-9d5c-078d24e10a55-le64.cache-7 +00007fc51a6da000 8K r-xs- b4ff5cf7-9766-47f8-9078-1b2fb59dfdc4-le64.cache-7 +00007fc51a6dc000 96K r-xs- 507eb2c7-aa72-4556-a723-82b3d0e61db2-le64.cache-7 +00007fc51a6f4000 44K r-xs- 955347f6-7d91-4f8c-879e-e31b12a49edb-le64.cache-7 +00007fc51a6ff000 8K r-xs- edf143a7-6212-4f3c-baa3-93dff078c158-le64.cache-7 +00007fc51a701000 12K r-xs- 4bf7f7d7-7d6d-46b5-ba19-b338022a553f-le64.cache-7 +00007fc51a704000 4K r-xs- 0f81de0c-45f3-457e-9a1a-20656baf05b3-le64.cache-7 +00007fc51a705000 4K r-xs- 84d76674-e845-4fdb-84e5-08f7fa5bfa20-le64.cache-7 +00007fc51a706000 4K r-xs- 73b2c246-8ec2-4cec-a9f7-8b69a879c11f-le64.cache-7 +00007fc51a707000 4K r-xs- 6d7fd616-c632-433b-b2a1-1a439844cb4c-le64.cache-7 +00007fc51a708000 12K r-xs- 94515895-7b91-4b92-a153-6168de8eb31f-le64.cache-7 +00007fc51a70b000 4K r-xs- bf59a3ff-18f7-458a-9f3c-45f045bfd41d-le64.cache-7 +00007fc51a70c000 16K r-xs- 3c4a99bc-95e1-4a81-b6e2-4093e7436024-le64.cache-7 +00007fc51a710000 16K r-xs- 231c47af-f39e-45c2-be83-f2cf926f3d24-le64.cache-7 +00007fc51a714000 12K r-xs- 9b1ada64-557e-4486-9164-e350371d5977-le64.cache-7 +00007fc51a717000 4K r-xs- 2bef893d-53ce-4d50-85aa-6dfea1db2c09-le64.cache-7 +00007fc51a718000 4K r-xs- ba6f3da1-6f47-4f77-97f7-2c3ca34b7945-le64.cache-7 +00007fc51a719000 4K r-xs- 8c1ea774-9391-418c-b3b1-907b6f0fa42f-le64.cache-7 +00007fc51a71a000 4K r-xs- a9656883-81b3-4353-8422-374f190304ff-le64.cache-7 +00007fc51a71b000 4K r-xs- 72111187-2413-48dd-8bad-f3ae4733a141-le64.cache-7 +00007fc51a71c000 4K r-xs- 178aeec4-0594-4743-a0c3-4e00175af393-le64.cache-7 +00007fc51a71d000 4K r-xs- 52a9c7f4-4118-482e-9b5f-3609406ef52f-le64.cache-7 +00007fc51a71e000 4K r-xs- 464ac9c6-b340-4ebc-887d-bd9fb6a54740-le64.cache-7 +00007fc51a71f000 4K r-xs- e04247dc-5989-4dd8-b993-085ab6fdf38c-le64.cache-7 +00007fc51a720000 4K r-xs- d1cbab9e-6c73-4eeb-8d4c-bd2c3ee72d9f-le64.cache-7 +00007fc51a721000 4K r-xs- 4d2f7af5-90a7-407d-8f91-27b43fa4eaf0-le64.cache-7 +00007fc51a722000 4K r-xs- 2f0faddf-403a-4776-952b-d1c2ca48367a-le64.cache-7 +00007fc51a723000 4K r-xs- 4b6e2fa7-8d67-46ee-8e1d-072b4048d149-le64.cache-7 +00007fc51a724000 4K r-xs- 3a57024f-d45a-4a94-aab6-457a97da8cb4-le64.cache-7 +00007fc51a725000 20K r-xs- 6f90bf98-dc57-4b19-9ea2-609bab43e579-le64.cache-7 +00007fc51a72a000 8K r-xs- d9966c19-a1c8-4a84-8e8b-67b9a5359c30-le64.cache-7 +00007fc51a72c000 4K r-xs- 1aedb7a2-5540-4639-b125-3803affd7c69-le64.cache-7 +00007fc51a72d000 32K r-xs- 27cca8a0-9a0b-41eb-ab8b-bc11685292d5-le64.cache-7 +00007fc51a735000 44K r-xs- 26b986c5-881b-4ee7-afce-080eb5c1aa62-le64.cache-7 +00007fc51a740000 72K rwx-- [ anon ] +00007fc51a752000 276K r-x-- libtbb.so.2 +00007fc51a797000 1024K ----- libtbb.so.2 +00007fc51a897000 20K rwx-- libtbb.so.2 +00007fc51a89c000 28K rwx-- [ anon ] +00007fc51a8a3000 8K r-xs- 6d459492-a742-40a3-b56b-31b84086b270-le64.cache-7 +00007fc51a8a5000 8K r-xs- 0d14775e-ba0b-409e-985d-aea8000857bd-le64.cache-7 +00007fc51a8a7000 8K r-xs- 586711aa-7365-4876-9dad-3549bfb47790-le64.cache-7 +00007fc51a8a9000 32K r-xs- 98268496-283c-48cd-8915-f21958b2b549-le64.cache-7 +00007fc51a8b1000 8K r-xs- 08dbea36-fd86-40ff-bb03-7fdcc9589253-le64.cache-7 +00007fc51a8b3000 4K r-xs- ca77f4a9-cc46-46b4-90f1-e56998c495b1-le64.cache-7 +00007fc51a8b4000 20K r-xs- c74708f5-7f19-4d87-8b35-3252086ba113-le64.cache-7 +00007fc51a8b9000 28K r-xs- gconv-modules.cache +00007fc51a8c0000 12K rwx-- [ anon ] +00007fc51a8c3000 4K r-x-- ld-2.17.so +00007fc51a8c4000 4K rwx-- ld-2.17.so +00007fc51a8c5000 4K rwx-- [ anon ] +00007ffdca0fd000 852K rwx-- [ stack ] +00007ffdca1dd000 8K r-x-- [ anon ] +ffffffffff600000 4K r-x-- [ anon ] + total 1428928K +--------------- +branchName=Verdi_O-2018.09-SP2 cnlDate=-- Thu Feb 21 04:40:56 PDT 2019 cnlEnv=Linux.0/64bit +uname(Linux IC_EDA 3.10.0-1160.53.1.el7.x86_64 #1 SMP Fri Jan 14 13:59:45 UTC 2022 x86_64) +--------------- +Process Size: 1463218176 bytes +verdi detected abnormal termination. +Log information written to +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/digital_top/verdiLog/sysinfo_May15_1728.tar. +Please send this file to customer support. diff --git a/tb/chip_top/verdiLog/da_debug.log b/tb/chip_top/verdiLog/da_debug.log new file mode 100644 index 0000000..94d3d9c --- /dev/null +++ b/tb/chip_top/verdiLog/da_debug.log @@ -0,0 +1,5 @@ +##################################################################################################### +# da_debug.log : log primitive debug message of Data Agent (Verdi internal layer to access FSDB). # +# This is for R&D to analyze when there are issues happening when Verdi reading FSDB # +##################################################################################################### +[DA][EVDP][XML]: start update xml in interactive mode at init[DA][EVDP][XML]: start update xml file in interactive mode diff --git a/tb/chip_top/verdiLog/exe.log b/tb/chip_top/verdiLog/exe.log new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/verdiLog/novas.conf b/tb/chip_top/verdiLog/novas.conf new file mode 100644 index 0000000..9f6292b --- /dev/null +++ b/tb/chip_top/verdiLog/novas.conf @@ -0,0 +1,590 @@ +[qBaseWindowStateGroup] +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\ProductVersion=201809 +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\Layout="@ByteArray(\0\0\0\xff\0\0\0\0\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x2\xf2\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x3P\0\0\0\x89\0\xff\xff\xff\xfa\0\0\0\x1\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\x2\xc7\0\0\x1\xa8\0\0\0k\0\0\0k\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\x1\0\0\x3V\0\0\x6\xaa\0\0\0k\0\xff\xff\xff\0\0\0\x3\0\0\n\0\0\0\x1\xd8\xfc\x1\0\0\0\x1\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\x1\0\0\0\0\0\0\n\0\0\0\0\xa0\0\xff\xff\xff\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x3\x16\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x3\x1e\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\x1f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x43\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3g\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\isNestedWindow=0 +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\size=@Size(2560 1337) +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\geometry_x=-1 +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\geometry_y=27 +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\geometry_width=2560 +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\geometry_height=1337 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\ProductVersion=201809 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\Layout="@ByteArray(\0\0\0\xff\0\0\0\0\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x3<\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x2\x8e\0\0\0\x89\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\xe9\0\0\0\xc6\0\0\0k\0\0\0k\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\x1\0\0\x2\x94\0\0\al\0\0\0k\0\xff\xff\xff\0\0\0\x3\0\0\n\0\0\0\x1\xa9\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\n\0\0\0\x2,\0\xff\xff\xff\xfa\0\0\0\x2\x1\0\0\0\x3\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\x1\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\x1-\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x33\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x34\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\isNestedWindow=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\size=@Size(2560 1337) +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\geometry_x=-1 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\geometry_y=27 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\geometry_width=2560 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\geometry_height=1337 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_OneSearch\isNestedWindow=1 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_OneSearch\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_OneSearch\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nWave_2\isNestedWindow=1 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nWave_2\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nWave_2\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nWave_2\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nWave_2\dockIsFloating=false +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qDockerWindow_qDockContentType\Verdi=1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qDockerWindow_qDockContentType\hdlHier=1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qDockerWindow_qDockContentType\hdlSrc=1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qDockerWindow_qDockContentType\messageWindow=1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qDockerWindow_qDockContentType\svtbHier=1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qDockerWindow_qDockContentType\OneSearch=1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qDockerWindowMgr_saveDockerChildList\Verdi_1=7 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qDockerWindowMgr_saveDockerChildList\Verdi_1_0=widgetDock_hdlHier_1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qDockerWindowMgr_saveDockerChildList\Verdi_1_1=widgetDock_messageWindow_1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qDockerWindowMgr_saveDockerChildList\Verdi_1_2=widgetDock_hdlSrc_1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qDockerWindowMgr_saveDockerChildList\Verdi_1_3=widgetDock_signalList_1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qDockerWindowMgr_saveDockerChildList\Verdi_1_4=widgetDock_svtbHier_1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qDockerWindowMgr_saveDockerChildList\Verdi_1_5=windowDock_OneSearch_1 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\widgetDock_hdlHier_1\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\widgetDock_hdlHier_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\widgetDock_hdlHier_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\widgetDock_hdlHier_1\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\widgetDock_messageWindow_1\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\widgetDock_messageWindow_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\widgetDock_messageWindow_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\widgetDock_messageWindow_1\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\widgetDock_hdlSrc_1\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\widgetDock_hdlSrc_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\widgetDock_hdlSrc_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\widgetDock_hdlSrc_1\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\widgetDock_signalList_1\isVisible=false +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\widgetDock_svtbHier_1\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\widgetDock_svtbHier_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\widgetDock_svtbHier_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\widgetDock_svtbHier_1\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\windowDock_OneSearch_1\isNestedWindow=1 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\windowDock_OneSearch_1\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\windowDock_OneSearch_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\windowDock_OneSearch_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\windowDock_OneSearch_1\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\windowDock_nWave_1\isNestedWindow=1 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\windowDock_nWave_1\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\windowDock_nWave_1\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\windowDock_nWave_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\windowDock_nWave_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\windowDock_nWave_1\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\ProductVersion=201809 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\Layout="@ByteArray(\0\0\0\xff\0\0\0\0\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x2\xcb\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x2\x8d\0\0\0\x89\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x2\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0h\0\x64\0l\0H\0i\0\x65\0r\0_\0\x31\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0*\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0s\0v\0t\0\x62\0H\0i\0\x65\0r\0_\0\x31\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0s\0i\0g\0n\0\x61\0l\0L\0i\0s\0t\0_\0\x31\0\0\0\0\xe9\0\0\0\xc6\0\0\0k\0\0\0k\xfb\0\0\0&\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0h\0\x64\0l\0S\0r\0\x63\0_\0\x31\x1\0\0\x2\x93\0\0\am\0\0\0k\0\xff\xff\xff\0\0\0\x3\0\0\n\0\0\0\x2\x1a\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\n\0\0\0\x2,\0\xff\xff\xff\xfa\0\0\0\x2\x1\0\0\0\x3\xfb\0\0\0\x34\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0m\0\x65\0s\0s\0\x61\0g\0\x65\0W\0i\0n\0\x64\0o\0w\0_\0\x31\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0,\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\0_\0\x31\x1\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x31\x1\0\0\0\0\xff\xff\xff\xff\0\0\x1-\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x33\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x34\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\isNestedWindow=0 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\size=@Size(2560 1337) +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\geometry_x=-1 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\geometry_y=27 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\geometry_width=2560 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\geometry_height=1337 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nWave_2\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nMemory_3\isNestedWindow=1 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nMemory_3\isVisible=false +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nMemory_3\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nMemory_3\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nMemory_3\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nMemory_4\isNestedWindow=1 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nMemory_4\isVisible=false +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nMemory_4\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nMemory_4\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nMemory_4\dockIsFloating=false +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qDockerWindow_qDockContentType\nWave=1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qDockerWindowMgr_saveDockerChildList\Verdi_1_6=windowDock_nWave_1 +Verdi_1\qBaseWindowNextStateGroup\0\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\0\ProductVersion=201809 +Verdi_1\qBaseWindowNextStateGroup\0\Layout="@ByteArray(\0\0\0\xff\0\0\0\0\xfd\0\0\0\x2\0\0\0\x2\0\0\x3U\0\0\x1L\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\0\xd9\0\0\0\x89\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\xe9\0\0\0\xc6\0\0\0k\0\0\0k\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\x1\0\0\0\xdf\0\0\x2v\0\0\0k\0\xff\xff\xff\0\0\0\x3\0\0\x3U\0\0\0\x9c\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x3U\0\0\0\xa0\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x3\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x33\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x34\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\0\0\x3U\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowNextStateGroup\0\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\0\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\0\size=@Size(853 572) +Verdi_1\qBaseWindowNextStateGroup\0\geometry_x=-1 +Verdi_1\qBaseWindowNextStateGroup\0\geometry_y=27 +Verdi_1\qBaseWindowNextStateGroup\0\geometry_width=853 +Verdi_1\qBaseWindowNextStateGroup\0\geometry_height=572 +Verdi_1\qBaseWindowNextStateGroup\1\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_OneSearch\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_OneSearch\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_OneSearch\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\1\ProductVersion=201809 +Verdi_1\qBaseWindowNextStateGroup\1\Layout="@ByteArray(\0\0\0\xff\0\0\0\x1\xfd\0\0\0\x2\0\0\0\x2\0\0\x3U\0\0\x1\x33\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\0\xd9\0\0\0\x89\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\xe9\0\0\0\xc6\0\0\0k\0\0\0k\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\x1\0\0\0\xdf\0\0\x2v\0\0\0k\0\xff\xff\xff\0\0\0\x3\0\0\x3U\0\0\0\xb5\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x3U\0\0\x2,\0\xff\xff\xff\xfa\0\0\0\x2\x1\0\0\0\x3\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\x1\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x33\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x34\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\0\0\x3U\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowNextStateGroup\1\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\1\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\1\size=@Size(853 572) +Verdi_1\qBaseWindowNextStateGroup\1\geometry_x=-1 +Verdi_1\qBaseWindowNextStateGroup\1\geometry_y=27 +Verdi_1\qBaseWindowNextStateGroup\1\geometry_width=853 +Verdi_1\qBaseWindowNextStateGroup\1\geometry_height=572 +Verdi_1\qBaseWindowNextStateGroup\2\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\windowDock_OneSearch\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\windowDock_OneSearch\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\2\ProductVersion=201809 +Verdi_1\qBaseWindowNextStateGroup\2\Layout="@ByteArray(\0\0\0\xff\0\0\0\x2\xfd\0\0\0\x2\0\0\0\x2\0\0\x3U\0\0\x1\x33\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\0\xd9\0\0\0\x89\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\xe9\0\0\0\xc6\0\0\0k\0\0\0k\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\x1\0\0\0\xdf\0\0\x2v\0\0\0k\0\xff\xff\xff\0\0\0\x3\0\0\x3U\0\0\0\xb5\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x3U\0\0\0\xa0\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x3\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\0\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\0\0k\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x33\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x34\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\0\0\x3U\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowNextStateGroup\2\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\2\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\2\size=@Size(853 572) +Verdi_1\qBaseWindowNextStateGroup\2\geometry_x=-1 +Verdi_1\qBaseWindowNextStateGroup\2\geometry_y=27 +Verdi_1\qBaseWindowNextStateGroup\2\geometry_width=853 +Verdi_1\qBaseWindowNextStateGroup\2\geometry_height=572 +Verdi_1\qBaseWindowNextStateGroup\3\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\windowDock_OneSearch\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\windowDock_OneSearch\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\windowDock_OneSearch\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\3\ProductVersion=201809 +Verdi_1\qBaseWindowNextStateGroup\3\Layout="@ByteArray(\0\0\0\xff\0\0\0\x3\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x4\x30\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x2\x8e\0\0\0\x89\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\xe9\0\0\0\xc6\0\0\0k\0\0\0k\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\x1\0\0\x2\x94\0\0\al\0\0\0k\0\xff\xff\xff\0\0\0\x3\0\0\n\0\0\0\0\xb5\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\n\0\0\0\x2,\0\xff\xff\xff\xfa\0\0\0\x2\x1\0\0\0\x3\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\x1\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x33\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x34\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowNextStateGroup\3\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\3\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\3\size=@Size(2560 1337) +Verdi_1\qBaseWindowNextStateGroup\3\geometry_x=-1 +Verdi_1\qBaseWindowNextStateGroup\3\geometry_y=27 +Verdi_1\qBaseWindowNextStateGroup\3\geometry_width=2560 +Verdi_1\qBaseWindowNextStateGroup\3\geometry_height=1337 +Verdi_1\qBaseWindowNextStateGroup\4\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\windowDock_OneSearch\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\windowDock_OneSearch\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\windowDock_OneSearch\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\4\ProductVersion=201809 +Verdi_1\qBaseWindowNextStateGroup\4\Layout="@ByteArray(\0\0\0\xff\0\0\0\x4\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x4\x30\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x2\x8e\0\0\0\x89\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\xe9\0\0\0\xc6\0\0\0k\0\0\0k\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\x1\0\0\x2\x94\0\0\al\0\0\0k\0\xff\xff\xff\0\0\0\x3\0\0\n\0\0\0\0\xb5\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\n\0\0\0\x2,\0\xff\xff\xff\xfa\0\0\0\x2\x1\0\0\0\x3\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\x1\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x33\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x34\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowNextStateGroup\4\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\4\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\4\size=@Size(2560 1337) +Verdi_1\qBaseWindowNextStateGroup\4\geometry_x=-1 +Verdi_1\qBaseWindowNextStateGroup\4\geometry_y=27 +Verdi_1\qBaseWindowNextStateGroup\4\geometry_width=2560 +Verdi_1\qBaseWindowNextStateGroup\4\geometry_height=1337 +Verdi_1\qBaseWindowNextStateGroup\5\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_OneSearch\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_OneSearch\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_OneSearch\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nWave_2\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nWave_2\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nWave_2\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nWave_2\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nWave_2\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\5\ProductVersion=201809 +Verdi_1\qBaseWindowNextStateGroup\5\Layout="@ByteArray(\0\0\0\xff\0\0\0\x5\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x4/\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x2\x8e\0\0\0\x89\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\xe9\0\0\0\xc6\0\0\0k\0\0\0k\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\x1\0\0\x2\x94\0\0\al\0\0\0k\0\xff\xff\xff\0\0\0\x3\0\0\n\0\0\0\0\xb6\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\n\0\0\0\x2,\0\xff\xff\xff\xfa\0\0\0\x2\x1\0\0\0\x3\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\x1\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\x1\xd5\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x33\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x34\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowNextStateGroup\5\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\5\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\5\size=@Size(2560 1337) +Verdi_1\qBaseWindowNextStateGroup\5\geometry_x=-1 +Verdi_1\qBaseWindowNextStateGroup\5\geometry_y=27 +Verdi_1\qBaseWindowNextStateGroup\5\geometry_width=2560 +Verdi_1\qBaseWindowNextStateGroup\5\geometry_height=1337 +Verdi_1\qBaseWindowNextStateGroup\6\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\windowDock_OneSearch\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\windowDock_OneSearch\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\windowDock_nWave_2\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\windowDock_nWave_2\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\windowDock_nWave_2\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\windowDock_nWave_2\qBaseWindowBeMax=1 +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\windowDock_nWave_2\qBaseWindowBeFix=1 +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\windowDock_nWave_2\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\6\ProductVersion=201809 +Verdi_1\qBaseWindowNextStateGroup\6\Layout="@ByteArray(\0\0\0\xff\0\0\0\x6\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x3<\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x2\x8e\0\0\0\0\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\xe9\0\0\0\xc6\0\0\0k\0\0\0k\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\0\0\0\x2\x94\0\0\al\0\0\0k\0\xff\xff\xff\0\0\0\x3\0\0\n\0\0\0\x1\xa9\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\n\0\0\0\x1-\0\xff\xff\xff\xfa\0\0\0\x2\x1\0\0\0\x3\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\0\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\x1-\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x33\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x34\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowNextStateGroup\6\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\6\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\6\size=@Size(2560 1337) +Verdi_1\qBaseWindowNextStateGroup\6\geometry_x=-1 +Verdi_1\qBaseWindowNextStateGroup\6\geometry_y=27 +Verdi_1\qBaseWindowNextStateGroup\6\geometry_width=2560 +Verdi_1\qBaseWindowNextStateGroup\6\geometry_height=1337 +Verdi_1\qBaseWindowNextStateGroup\7\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_OneSearch\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_OneSearch\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_OneSearch\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_nWave_2\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_nWave_2\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_nWave_2\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_nWave_2\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_nWave_2\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_nWave_2\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\7\ProductVersion=201809 +Verdi_1\qBaseWindowNextStateGroup\7\Layout="@ByteArray(\0\0\0\xff\0\0\0\a\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x3<\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x2\x8e\0\0\0\x89\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\xe9\0\0\0\xc6\0\0\0k\0\0\0k\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\x1\0\0\x2\x94\0\0\al\0\0\0k\0\xff\xff\xff\0\0\0\x3\0\0\n\0\0\0\x1\xa9\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\n\0\0\0\x2,\0\xff\xff\xff\xfa\0\0\0\x2\x1\0\0\0\x3\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\x1\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\x1-\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x33\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x34\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowNextStateGroup\7\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\7\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\7\size=@Size(2560 1337) +Verdi_1\qBaseWindowNextStateGroup\7\geometry_x=-1 +Verdi_1\qBaseWindowNextStateGroup\7\geometry_y=27 +Verdi_1\qBaseWindowNextStateGroup\7\geometry_width=2560 +Verdi_1\qBaseWindowNextStateGroup\7\geometry_height=1337 +Verdi_1\qBaseWindowNextStateGroup\8\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\windowDock_OneSearch\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\windowDock_OneSearch\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\windowDock_nWave_2\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\windowDock_nWave_2\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\windowDock_nWave_2\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\windowDock_nWave_2\qBaseWindowBeMax=1 +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\windowDock_nWave_2\qBaseWindowBeFix=1 +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\windowDock_nWave_2\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\8\ProductVersion=201809 +Verdi_1\qBaseWindowNextStateGroup\8\Layout="@ByteArray(\0\0\0\xff\0\0\0\b\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x3<\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x2\x8e\0\0\0\0\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\xe9\0\0\0\xc6\0\0\0k\0\0\0k\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\0\0\0\x2\x94\0\0\al\0\0\0k\0\xff\xff\xff\0\0\0\x3\0\0\n\0\0\0\x1\xa9\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\n\0\0\0\x1-\0\xff\xff\xff\xfa\0\0\0\x2\x1\0\0\0\x3\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\0\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\x1-\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x33\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x34\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowNextStateGroup\8\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\8\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\8\size=@Size(2560 1337) +Verdi_1\qBaseWindowNextStateGroup\8\geometry_x=-1 +Verdi_1\qBaseWindowNextStateGroup\8\geometry_y=27 +Verdi_1\qBaseWindowNextStateGroup\8\geometry_width=2560 +Verdi_1\qBaseWindowNextStateGroup\8\geometry_height=1337 +Verdi_1\qBaseWindowNextStateGroup\9\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\windowDock_OneSearch\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\windowDock_OneSearch\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\windowDock_OneSearch\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\windowDock_nWave_2\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\windowDock_nWave_2\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\windowDock_nWave_2\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\windowDock_nWave_2\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\windowDock_nWave_2\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\windowDock_nWave_2\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\9\ProductVersion=201809 +Verdi_1\qBaseWindowNextStateGroup\9\Layout="@ByteArray(\0\0\0\xff\0\0\0\t\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x3<\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x2\x8e\0\0\0\x89\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\xe9\0\0\0\xc6\0\0\0k\0\0\0k\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\x1\0\0\x2\x94\0\0\al\0\0\0k\0\xff\xff\xff\0\0\0\x3\0\0\n\0\0\0\x1\xa9\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\n\0\0\0\x2,\0\xff\xff\xff\xfa\0\0\0\x2\x1\0\0\0\x3\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\x1\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\x1-\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x33\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x34\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowNextStateGroup\9\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\9\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\9\size=@Size(2560 1337) +Verdi_1\qBaseWindowNextStateGroup\9\geometry_x=-1 +Verdi_1\qBaseWindowNextStateGroup\9\geometry_y=27 +Verdi_1\qBaseWindowNextStateGroup\9\geometry_width=2560 +Verdi_1\qBaseWindowNextStateGroup\9\geometry_height=1337 +Verdi_1\qBaseWindowNextStateGroup\10\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\windowDock_OneSearch\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\windowDock_OneSearch\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\windowDock_nWave_2\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\windowDock_nWave_2\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\windowDock_nWave_2\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\windowDock_nWave_2\qBaseWindowBeMax=1 +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\windowDock_nWave_2\qBaseWindowBeFix=1 +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\windowDock_nWave_2\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\10\ProductVersion=201809 +Verdi_1\qBaseWindowNextStateGroup\10\Layout="@ByteArray(\0\0\0\xff\0\0\0\n\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x3<\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x2\x8e\0\0\0\0\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\xe9\0\0\0\xc6\0\0\0k\0\0\0k\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\0\0\0\x2\x94\0\0\al\0\0\0k\0\xff\xff\xff\0\0\0\x3\0\0\n\0\0\0\x1\xa9\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\n\0\0\0\x1-\0\xff\xff\xff\xfa\0\0\0\x2\x1\0\0\0\x3\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\0\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\x1-\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x33\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x34\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowNextStateGroup\10\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\10\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\10\size=@Size(2560 1337) +Verdi_1\qBaseWindowNextStateGroup\10\geometry_x=-1 +Verdi_1\qBaseWindowNextStateGroup\10\geometry_y=27 +Verdi_1\qBaseWindowNextStateGroup\10\geometry_width=2560 +Verdi_1\qBaseWindowNextStateGroup\10\geometry_height=1337 +Verdi_1\qBaseWindowNextStateGroup\11\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeMax=1 +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_OneSearch\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_OneSearch\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_nWave_2\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_nWave_2\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_nWave_2\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_nWave_2\qBaseWindowBeMax=1 +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_nWave_2\qBaseWindowBeFix=1 +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_nWave_2\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\11\ProductVersion=201809 +Verdi_1\qBaseWindowNextStateGroup\11\Layout="@ByteArray(\0\0\0\xff\0\0\0\v\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x3<\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x2\x8e\0\0\0\0\0\xff\xff\xff\xfa\xff\xff\xff\xff\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\xe9\0\0\0\xc6\0\0\0k\0\0\0k\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\0\0\0\x2\x94\0\0\al\0\0\0k\0\xff\xff\xff\0\0\0\x3\0\0\n\0\0\0\x4\xeb\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\n\0\0\0\x1-\0\xff\xff\xff\xfa\0\0\0\x2\x1\0\0\0\x3\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\0\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\x1-\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x33\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x34\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowNextStateGroup\11\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\11\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\11\size=@Size(2560 1337) +Verdi_1\qBaseWindowNextStateGroup\11\geometry_x=-1 +Verdi_1\qBaseWindowNextStateGroup\11\geometry_y=27 +Verdi_1\qBaseWindowNextStateGroup\11\geometry_width=2560 +Verdi_1\qBaseWindowNextStateGroup\11\geometry_height=1337 +Verdi_1\qBaseWindowNextStateGroup\12\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeMax=1 +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\windowDock_OneSearch\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\windowDock_OneSearch\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\windowDock_nWave_2\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\windowDock_nWave_2\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\windowDock_nWave_2\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\windowDock_nWave_2\qBaseWindowBeMax=1 +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\windowDock_nWave_2\qBaseWindowBeFix=1 +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\windowDock_nWave_2\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\12\ProductVersion=201809 +Verdi_1\qBaseWindowNextStateGroup\12\Layout="@ByteArray(\0\0\0\xff\0\0\0\f\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x3<\xfc\x1\0\0\0\x2\xfc\0\0\0\0\0\0\x2\x8e\0\0\0\0\0\xff\xff\xff\xfa\xff\xff\xff\xff\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\xe9\0\0\0\xc6\0\0\0k\0\0\0k\0\0\0\x3\0\0\n\0\0\0\x4\xeb\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\n\0\0\0\x1-\0\xff\xff\xff\xfa\0\0\0\x2\x1\0\0\0\x4\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\0\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\x1-\0\xff\xff\xff\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\0\0\0\0\0\xff\xff\xff\xff\0\0\al\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x33\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x34\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowNextStateGroup\12\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\12\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\12\size=@Size(2560 1337) +Verdi_1\qBaseWindowNextStateGroup\12\geometry_x=-1 +Verdi_1\qBaseWindowNextStateGroup\12\geometry_y=27 +Verdi_1\qBaseWindowNextStateGroup\12\geometry_width=2560 +Verdi_1\qBaseWindowNextStateGroup\12\geometry_height=1337 +Verdi_1\qBaseWindowNextStateGroup\13\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_OneSearch\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_OneSearch\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_OneSearch\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_nWave_2\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_nWave_2\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_nWave_2\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_nWave_2\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_nWave_2\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_nWave_2\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\13\ProductVersion=201809 +Verdi_1\qBaseWindowNextStateGroup\13\Layout="@ByteArray(\0\0\0\xff\0\0\0\r\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x3<\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x2\x8e\0\0\0\x89\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\xe9\0\0\0\xc6\0\0\0k\0\0\0k\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\x1\0\0\x2\x94\0\0\al\0\0\0k\0\xff\xff\xff\0\0\0\x3\0\0\n\0\0\0\x1\xa9\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\n\0\0\0\x2,\0\xff\xff\xff\xfa\0\0\0\x2\x1\0\0\0\x3\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\x1\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\x1-\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x33\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x34\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowNextStateGroup\13\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\13\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\13\size=@Size(2560 1337) +Verdi_1\qBaseWindowNextStateGroup\13\geometry_x=-1 +Verdi_1\qBaseWindowNextStateGroup\13\geometry_y=27 +Verdi_1\qBaseWindowNextStateGroup\13\geometry_width=2560 +Verdi_1\qBaseWindowNextStateGroup\13\geometry_height=1337 + +[QwMainWindow] +window\Verdi_1\layout="@ByteArray(\0\0\0\xff\0\x3\x14Q\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x2\xcb\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x2\x8d\0\0\0\x89\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\xe9\0\0\0\xc6\0\0\0k\0\0\0k\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\x1\0\0\x2\x93\0\0\am\0\0\0k\0\xff\xff\xff\0\0\0\x3\0\0\n\0\0\0\x2\x1a\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\n\0\0\0\x2,\0\xff\xff\xff\xfa\0\0\0\x2\x1\0\0\0\x3\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\x1\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\x1-\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x33\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x34\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +window\Verdi_1\geometry=@ByteArray(\x1\xd9\xd0\xcb\0\x1\0\0\xff\xff\xff\xff\0\0\0\x1b\0\0\n\0\0\0\x5z\0\0\0\0\0\0\0\0\xff\xff\xff\xfe\xff\xff\xff\xfe\0\0\0\0\x2\0) +window\Verdi_1\menubar=true +window\Verdi_1\splitters\tbvConstrDbgSplitter\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x2\0\0\0\x8d\0\0\0\x8d\x1\0\0\0\x6\x1\0\0\0\x1) +window\Verdi_1\splitters\tbvConstrRerandSplitter\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x2\0\0\0G\0\0\0\x4\x1\0\0\0\x6\x1\0\0\0\x2) +window\Verdi_1\splitters\tbvConstrOriginSplitter\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x2\0\0\0!\0\0\0\x4\x1\0\0\0\x6\x1\0\0\0\x2) +window\Verdi_1\splitters\ThreadPane\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x2\0\0\0\x37\0\0\0\x37\x1\0\0\0\x6\x1\0\0\0\x2) +window\Verdi_1\splitters\tbvInteractiveSplitter\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x2\0\0\0\x1f\0\0\0\x1f\x1\0\0\0\x6\x1\0\0\0\x2) +window\Verdi_1\splitters\tbvVSimSplitter\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x2\0\0\0\x1f\0\0\0\x1f\x1\0\0\0\x6\x1\0\0\0\x2) +window\Verdi_1\splitters\tbvTBHSplitter\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x2\0\0\0-\0\0\0?\x1\0\0\0\x6\x1\0\0\0\x2) +window\nWave_2\layout="@ByteArray(\0\0\0\xff\0\x3\x14Q\xfd\0\0\0\0\0\0\n\0\0\0\x1\xb2\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x2\0\0\0\x2\0\0\0\f\0\0\0\x12\0W\0\x41\0V\0\x45\0_\0O\0P\0\x45\0N\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x12\0W\0\x41\0V\0\x45\0_\0\x45\0\x44\0I\0T\x1\0\0\0?\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x16\0W\0\x41\0V\0\x45\0_\0\x43\0U\0R\0S\0O\0R\x1\0\0\0\xb4\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x12\0W\0\x41\0V\0\x45\0_\0V\0I\0\x45\0W\x1\0\0\x2R\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\"\0W\0\x41\0V\0\x45\0_\0S\0\x45\0\x41\0R\0\x43\0H\0_\0\x45\0V\0\x45\0N\0T\x1\0\0\x2\xac\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0W\0\x41\0V\0\x45\0_\0R\0\x45\0P\0L\0\x41\0Y\0_\0S\0I\0M\0\0\0\x5K\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x12\0W\0\x41\0V\0\x45\0_\0G\0O\0T\0O\x1\0\0\x3H\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0W\0\x41\0V\0\x45\0_\0G\0O\0T\0O\0_\0N\0\x41\0M\0\x45\0\x44\0_\0M\0\x41\0R\0K\0\x45\0R\0\0\0\x5\xed\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0W\0\x41\0V\0\x45\0_\0T\0R\0\x41\0N\0S\0\x41\0\x43\0T\0I\0O\0N\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0W\0\x41\0V\0\x45\0_\0\x45\0X\0P\0L\0O\0R\0\x45\0_\0P\0R\0O\0P\0\x45\0R\0T\0Y\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0W\0\x41\0V\0\x45\0_\0\x46\0I\0N\0\x44\0_\0S\0I\0G\0N\0\x41\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x18\0W\0\x41\0V\0\x45\0_\0P\0R\0I\0M\0\x41\0R\0Y\0\0\0\x6\x1b\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x32\0S\0\x45\0L\0\x45\0\x43\0T\0I\0O\0N\0_\0M\0\x45\0S\0S\0\x41\0G\0\x45\0_\0T\0O\0O\0L\0\x42\0\x41\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +window\nWave_2\geometry=@ByteArray(\x1\xd9\xd0\xcb\0\x1\0\0\0\0\0\0\0\0\0\x1b\0\0\t\xff\0\0\x1\xfe\0\0\0\0\0\0\0\x1b\0\0\t\xff\0\0\x1\xfe\0\0\0\0\0\0) +window\nWave_2\menubar=true +window\nWave_2\splitters\splitter_5\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\x1\xb2\x1\0\0\0\x1\0\0\0\0\x2) +window\nWave_2\splitters\splitter_2\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x2\0\0\0\xd8\0\0\t(\x1\0\0\0\x1\0\0\0\0\x1) +window\nWave_2\splitters\splitter\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x3\0\0\0?\0\0\0\x1\0\0\b\xe6\x1\0\0\0\x1\0\0\0\0\x1) +window\nWave_2\splitters\Pane_Upper\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x2\0\0\0\xd8\0\0\t%\x1\0\0\0\x1\0\0\0\0\x1) +window\nWave_2\splitters\splitter_3\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x2\0\0\0?\0\0\tW\x1\0\0\0\x1\0\0\0\0\x1) +window\nWave_2\splitters\wholeSplitter\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x3\0\0\0O\0\0\0\xa3\0\0\0\x4\x1\0\0\0\x6\x1\0\0\0\x1) +window\nWave_2\splitters\middleSplitter\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0\x4\x1\0\0\0\x6\x1\0\0\0\x2) +window\nMemory_3\layout=@ByteArray(\0\0\0\xff\0\x3\x14Q\xfd\0\0\0\0\0\0\x4\xfd\0\0\x1\xda\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x2\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0M\0\x45\0M\0_\0T\0O\0O\0L\0\x42\0\x41\0R\0_\0U\0P\0P\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x34\0N\0M\0\x45\0M\0_\0T\0O\0O\0L\0\x42\0\x41\0R\0_\0U\0P\0P\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0_\0\x32\x1\0\0\0?\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x34\0N\0M\0\x45\0M\0_\0T\0O\0O\0L\0\x42\0\x41\0R\0_\0U\0P\0P\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0_\0\x33\x1\0\0\x1\xd3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x34\0N\0M\0\x45\0M\0_\0T\0O\0O\0L\0\x42\0\x41\0R\0_\0L\0O\0W\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0_\0\x31\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0) +window\nMemory_3\geometry=@ByteArray(\x1\xd9\xd0\xcb\0\x1\0\0\0\0\0\0\0\0\0\x1b\0\0\x4\xfc\0\0\x2@\0\0\0\0\0\0\0\x1b\0\0\x4\xfc\0\0\x2@\0\0\0\0\0\0) +window\nMemory_3\menubar=true +window\nMemory_4\layout=@ByteArray(\0\0\0\xff\0\x3\x14Q\xfd\0\0\0\0\0\0\x4\xfd\0\0\x1\xda\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x2\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0M\0\x45\0M\0_\0T\0O\0O\0L\0\x42\0\x41\0R\0_\0U\0P\0P\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x34\0N\0M\0\x45\0M\0_\0T\0O\0O\0L\0\x42\0\x41\0R\0_\0U\0P\0P\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0_\0\x32\x1\0\0\0?\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x34\0N\0M\0\x45\0M\0_\0T\0O\0O\0L\0\x42\0\x41\0R\0_\0U\0P\0P\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0_\0\x33\x1\0\0\x1\xd3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x34\0N\0M\0\x45\0M\0_\0T\0O\0O\0L\0\x42\0\x41\0R\0_\0L\0O\0W\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0_\0\x31\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0) +window\nMemory_4\geometry=@ByteArray(\x1\xd9\xd0\xcb\0\x1\0\0\0\0\0\0\0\0\0\x1b\0\0\x4\xfc\0\0\x2@\0\0\0\0\0\0\0\x1b\0\0\x4\xfc\0\0\x2@\0\0\0\0\0\0) +window\nMemory_4\menubar=true + +[qBaseWindow_saveRestoreSession_group] +10=/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/digital_top/verdiLog/novas_autosave.ses + +[qDockerWindow_C] +Verdi_1\position.x=-1 +Verdi_1\position.y=27 +Verdi_1\width=2560 +Verdi_1\height=1337 diff --git a/tb/chip_top/verdiLog/novas.log b/tb/chip_top/verdiLog/novas.log new file mode 100644 index 0000000..157ce72 --- /dev/null +++ b/tb/chip_top/verdiLog/novas.log @@ -0,0 +1,10 @@ +Verdi (R) + +Release Verdi_O-2018.09-SP2 for (RH Linux x86_64/64bit) -- Thu Feb 21 04:40:56 PDT 2019 + +Copyright (c) 1999 - 2019 Synopsys, Inc. +This software and the associated documentation are proprietary to Synopsys, Inc. +This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. +All other use, reproduction, or distribution of this software is strictly prohibited. + + diff --git a/tb/chip_top/verdiLog/novas.rc b/tb/chip_top/verdiLog/novas.rc new file mode 100644 index 0000000..b8afaf9 --- /dev/null +++ b/tb/chip_top/verdiLog/novas.rc @@ -0,0 +1,1315 @@ +@verdi rc file Version 1.0 +[Library] +work = ./work +[Annotation] +3D_Active_Annotation = FALSE +[CommandSyntax.finsim] +InvokeCommand = +FullFileName = TRUE +Separator = . +SimPromptSign = ">" +HierNameLevel = 1 +RunContinue = "continue" +Finish = "quit" +UseAbsTime = FALSE +NextTime = "run 1" +NextNTime = "run ${SimBPTime}" +NextEvent = "run 1" +Reset = +ObjPosBreak = "break posedge ${SimBPObj}" +ObjNegBreak = "break negedge ${SimBPObj}" +ObjAnyBreak = "break change ${SimBPObj}" +ObjLevelBreak = +LineBreak = "breakline ${SimBPFile} ${SimBPLine}" +AbsTimeBreak = "break abstimeaf ${SimBPTime}" +RelTimeBreak = "break reltimeaf ${SimBPTime}" +EnableBP = "breakon ${SimBPId}" +DisableBP = "breakoff ${SimBPId}" +DeleteBP = "breakclr ${SimBPId}" +DeleteAllBP = "breakclr" +SimSetScope = "cd ${SimDmpObj}" +[CommandSyntax.ikos] +InvokeCommand = "setvar debussy true;elaborate -p ${SimTop} -s ${SimArch}; run until 0;fsdbInteractive; " +FullFileName = TRUE +NeedTimeUnit = TRUE +NormalizeTimeUnit = TRUE +Separator = / +HierNameLevel = 2 +RunContinue = "run" +Finish = "exit" +NextTime = "run ${SimBPTime} ${SimTimeUnit}" +NextNTime = "run for ${SimBPTime} ${SimTimeUnit}" +NextEvent = "step 1" +Reset = "reset" +ObjPosBreak = "stop if ${SimBPObj} = \"'1'\"" +ObjNegBreak = "stop if ${SimBPObj} = \"'0'\"" +ObjAnyBreak = +ObjLevelBreak = "stop if ${SimBPObj} = ${SimBPValue}" +LineBreak = "stop at ${SimBPFile}:${SimBPLine}" +AbsTimeBreak = +RelTimeBreak = +EnableBP = "enable ${SimBPId}" +DisableBP = "disable ${SimBPId}" +DeleteBP = "delete ${SimBPId}" +DeleteAllBP = "delete *" +[CommandSyntax.verisity] +InvokeCommand = +FullFileName = FALSE +Separator = . +SimPromptSign = "> " +HierNameLevel = 1 +RunContinue = "." +Finish = "$finish;" +NextTime = "$db_steptime(1);" +NextNTime = "$db_steptime(${SimBPTime});" +NextEvent = "$db_step;" +SimSetScope = "$scope(${SimDmpObj});" +Reset = "$reset;" +ObjPosBreak = "$db_breakonposedge(${SimBPObj});" +ObjNegBreak = "$db_breakonnegedge(${SimBPObj});" +ObjAnyBreak = "$db_breakwhen(${SimBPObj});" +ObjLevelBreak = "$db_breakwhen(${SimBPObj}, ${SimBPValue});" +LineBreak = "$db_breakatline(${SimBPLine}, ${SimBPScope}, \"${SimBPFile}\");" +AbsTimeBreak = "$db_breakbeforetime(${SimBPTime});" +RelTimeBreak = "$db_breakbeforetime(${SimBPTime});" +EnableBP = "$db_enablebreak(${SimBPId});" +DisableBP = "$db_disablebreak(${SimBPId});" +DeleteBP = "$db_deletebreak(${SimBPId});" +DeleteAllBP = "$db_deletebreak;" +FSDBInit = "$novasInteractive;" +FSDBDumpvars = "$novasDumpvars(0, ${SimDmpObj});" +FSDBDumpsingle = "$novasDumpsingle(${SimDmpObj});" +FSDBDumpvarsInFile = "$novasDumpvarsToFile(\"${SimDmpFile}\");" +FSDBDumpMem = "$novasDumpMemNow(${SimDmpObj}, ${SimDmpBegin}, ${SimDmpSize});" +[CoverageDetail] +cross_filter_limit = 1000 +branch_limit_vector_display = 50 +showgrid = TRUE +reuseFirst = TRUE +justify = TRUE +scrollbar_mode = per pane +test_combo_left_truncate = TRUE +instance_combo_left_truncate = TRUE +loop_navigation = TRUE +condSubExpr = 20 +tglMda = 1000 +linecoverable = 100000 +lineuncovered = 50000 +tglcoverable = 30000 +tgluncovered = 30000 +pendingMax = 1000 +show_full_more = FALSE +[CoverageHier] +showgrid = FALSE +[CoverageWeight] +Assert = 1 +Covergroup = 1 +Line = 1 +Condition = 1 +Toggle = 1 +FSM = 1 +Branch = 1 +[DesignTree] +IfShowModule = {TRUE, FALSE} +[DisabledMessages] +version = Verdi_O-2018.09-SP2 +[Editor] +editorName = TurboEditor +[Emacs] +EmacsFont = "Clean 14" +EmacsBG = white +EmacsFG = black +[Exclusion] +enableAsDefault = TRUE +saveAsDefault = TRUE +saveManually = TRUE +illegalBehavior = FALSE +DisplayExcludedItem = FALSE +adaptiveExclusion = TRUE +warningExcludeInstance = TRUE +favorite_exclude_annotation = "" +[FSM] +viewport = 65 336 387 479 +WndBk-FillColor = Gray3 +Background-FillColor = gray5 +prefKey_Link-FillColor = yellow4 +prefKey_Link-TextColor = black +Trap = red3 +Hilight = blue4 +Window = Gray3 +Selected = white +Trans. = green2 +State = black +Init. = black +SmartTips = TRUE +VectorFont = FALSE +StopAskBkgndColor = FALSE +ShowStateAction = FALSE +ShowTransAction = FALSE +ShowTransCond = FALSE +StateLable = NAME +StateValueRadix = ORIG +State-LineColor = ID_BLACK +State-LineWidth = 1 +State-FillColor = ID_BLUE2 +State-TextColor = ID_WHITE +Init_State-LineColor = ID_BLACK +Init_State-LineWidth = 2 +Init_State-FillColor = ID_YELLOW2 +Init_State-TextColor = ID_BLACK +Reset_State-LineColor = ID_BLACK +Reset_State-LineWidth = 2 +Reset_State-FillColor = ID_YELLOW7 +Reset_State-TextColor = ID_BLACK +Trap_State-LineColor = ID_RED2 +Trap_State-LineWidth = 2 +Trap_State-FillColor = ID_CYAN5 +Trap_State-TextColor = ID_RED2 +State_Action-LineColor = ID_BLACK +State_Action-LineWidth = 1 +State_Action-FillColor = ID_WHITE +State_Action-TextColor = ID_BLACK +Junction-LineColor = ID_BLACK +Junction-LineWidth = 1 +Junction-FillColor = ID_GREEN2 +Junction-TextColor = ID_BLACK +Connection-LineColor = ID_BLACK +Connection-LineWidth = 1 +Connection-FillColor = ID_GRAY5 +Connection-TextColor = ID_BLACK +prefKey_Port-LineColor = ID_BLACK +prefKey_Port-LineWidth = 1 +prefKey_Port-FillColor = ID_ORANGE6 +prefKey_Port-TextColor = ID_YELLOW2 +Transition-LineColor = ID_BLACK +Transition-LineWidth = 1 +Transition-FillColor = ID_WHITE +Transition-TextColor = ID_BLACK +Trans_Condition-LineColor = ID_BLACK +Trans_Condition-LineWidth = 1 +Trans_Condition-FillColor = ID_WHITE +Trans_Condition-TextColor = ID_ORANGE2 +Trans_Action-LineColor = ID_BLACK +Trans_Action-LineWidth = 1 +Trans_Action-FillColor = ID_WHITE +Trans_Action-TextColor = ID_GREEN2 +SelectedSet-LineColor = ID_RED2 +SelectedSet-LineWidth = 1 +SelectedSet-FillColor = ID_RED2 +SelectedSet-TextColor = ID_WHITE +StickSet-LineColor = ID_ORANGE5 +StickSet-LineWidth = 1 +StickSet-FillColor = ID_PURPLE6 +StickSet-TextColor = ID_BLACK +HilightSet-LineColor = ID_RED5 +HilightSet-LineWidth = 1 +HilightSet-FillColor = ID_RED7 +HilightSet-TextColor = ID_BLUE5 +ControlPoint-LineColor = ID_BLACK +ControlPoint-LineWidth = 1 +ControlPoint-FillColor = ID_WHITE +Bundle-LineColor = ID_BLACK +Bundle-LineWidth = 1 +Bundle-FillColor = ID_WHITE +Bundle-TextColor = ID_BLUE4 +QtBackground-FillColor = ID_GRAY6 +prefKey_Link-LineColor = ID_ORANGE2 +prefKey_Link-LineWidth = 1 +Selection-LineColor = ID_BLUE2 +Selection-LineWidth = 1 +[FSM_Dlg-Print] +Orientation = Landscape +[FileBrowser] +nWaveOpenFsdbDirHistory = "\"/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/chip_top/verdplus_000.fsdb\"" +[Form] +version = Verdi_O-2018.09-SP2 +wave/sigCPL.fm = 100,100,243,333 +[General] +autoSaveSession = FALSE +TclAutoSource = +cmd_enter_form = FALSE +SyncBrowserDir = TRUE +version = Verdi_O-2018.09-SP2 +SignalCaseInSensitive = FALSE +ShowWndCtntDuringResizing = FALSE +[GlobalProp] +ErrWindow_Font = Helvetica_M_R_12 +[Globals] +app_default_font = Bitstream Vera Sans,10,-1,5,50,0,0,0,0,0 +app_fixed_width_font = Courier,10,-1,5,50,0,0,0,0,0 +text_encoding = Unicode(utf8) +smart_resize = TRUE +smart_resize_child_limit = 2000 +tooltip_max_width = 200 +tooltip_max_height = 20 +tooltip_viewer_key = F3 +tooltip_display_time = 1000 +bookmark_name_length_limit = 12 +disable_tooltip = FALSE +auto_load_source = TRUE +max_array_size = 4096 +filter_when_typing = TRUE +filter_keep_children = TRUE +filter_syntax = Wildcards +filter_keystroke_interval = 800 +filter_case_sensitive = FALSE +filter_full_path = FALSE +load_detail_for_funcov = FALSE +sort_limit = 100000 +ignoreDBVersionChecking = FALSE +[HB] +ViewSchematic = FALSE +windowLayout = 0 0 804 500 182 214 804 148 +import_filter = *.v; *.vc; *.f +designTreeFont = *-adobe-courier-medium-r-*-*-12-*-*-*-*-*-iso8859-* +import_filter_vhdl = *.vhd; *.vhdl; *.f +import_default_language = Verilog +import_filter_verilog = *.v; *.vc; *.f +simulation_file_type = *.fsdb;*.fsdb.gz;*.fsdb.bz2;*.ff;*.dump +PrefetchViewableAnnot = TRUE +[Hier] +filterTimeout = 1500 +[ImportLiberty] +SearchPriority = .lib++ +bSkipStateCell = False +bImportPowerInfo = False +bSkipFFCell = False +bScpecifyCellNameCase = False +bSpecifyPinNameCase = False +CellNameToCase = +PinNameToCase = +[Language] +EditWindow_Font = COURIER12 +Background = ID_WHITE +Comment = ID_GRAY4 +Keyword = ID_BLUE5 +UserKeyword = ID_GREEN2 +Text = ID_BLACK +SelText = ID_WHITE +SelBackground = ID_BLUE2 +[Library.Ikos] +pack = ./work.lib++ +vital = ./work.lib++ +work = ./work.lib++ +std = ${dls_std}.lib++ +ieee = ${dls_ieee}.lib++ +synopsys = ${dls_synopsys}.lib++ +silc = ${dls_silc}.lib++ +ikos = ${dls_ikos}.lib++ +novas = ${VOYAGER_LIB_VHDL}/${VOYAGER_MACHINE}/novas.lib++ +[MDT] +ART_RF_SP = spr[0-9]*bx[0-9]* +ART_RF_2P = dpr[0-9]*bx[0-9]* +ART_SRAM_SP = spm[0-9]*bx[0-9]* +ART_SRAM_DP = dpm[0-9]*bx[0-9]* +VIR_SRAM_SP = hdsd1_[0-9]*x[0-9]*cm4sw1 +VIR_SRAM_DP = hdsd2_[0-9]*x[0-9]*cm4sw1 +VIR_RF_SP = rfsd1_[0-9]*x[0-9]*cm2sw0 +VIR_RF_DP = rfsd2_[0-9]*x[0-9]*cm2sw1 +VIR_STAR_SRAM_SP = shsd1_[0-9]*x[0-9]*cm4sw0 +[NPExpanding] +functiongroups = FALSE +modules = FALSE +[NPFilter] +showAssertion = TRUE +showCoverGroup = TRUE +showProperty = TRUE +showSequence = TRUE +showDollarUnit = TRUE +[OldFontRC] +Wave_legend_window_font = -f COURIER12 -c ID_CYAN5 +Wave_value_window_font = -f COURIER12 -c ID_CYAN5 +Wave_curve_window_font = -f COURIER12 -c ID_CYAN5 +Wave_group_name_font = -f COURIER12 -c ID_GREEN5 +Wave_ruler_value_font = -f COURIER12 -c ID_CYAN5 +Wave_analog_ruler_value_font = -f COURIER12 -c ID_CYAN5 +Wave_comment_string_font = -f COURIER12 -c ID_RED5 +HB_designTreeFont = *-adobe-courier-medium-r-*-*-12-*-*-*-*-*-iso8859-* +Text_font = COURIER12 +nMemory_font = Fixed 14 +[OtherEditor] +cmd1 = "xterm -font 9x15 -fg black -bg gray -e" +name = "vi" +options = "+${CurLine} ${CurFullFileName}" +[Power] +PowerDownInstance = ID_GRAY1 +RetentionSignal = ID_YELLOW2 +IsolationSignal = ID_RED6 +LevelShiftedSignal = ID_GREEN6 +PowerSwitchObject = ID_ORANGE5 +AlwaysOnObject = ID_GREEN5 +PowerNet = ID_RED2 +GroundNet = ID_RED2 +SimulationOnly = ID_CYAN3 +SRSN/SPA = ID_CYAN3 +CNSSignal = ID_CYAN3 +RPTRSignal = ID_CYAN3 +AcknowledgeSignal = ID_CYAN3 +BoundaryPort = ID_CYAN3 +DisplayInstrumentedCell = TRUE +ShowCmdByFile = FALSE +ShowPstAnnot = FALSE +ShowIsoSymbol = TRUE +ExtractIsoSameNets = FALSE +AnnotateSignal = TRUE +HighlightPowerObject = TRUE +HighlightPowerDomain = TRUE +TraceThroughInstruLowPower = FALSE +BrightenPowerColorInSchematicWindow = FALSE +ShowAlias = FALSE +ShowVoltage = TRUE +MatchTreeNodesCaseInsensitive = FALSE +SearchHBNodeDynamically = FALSE +ContinueTracingSupplyOrLogicNet = FALSE +[Print] +PrinterName = lp +FileName = test.ps +PaperSize = A4 - 210x297 (mm) +ColorPrint = FALSE +[PropertyTools] +saveWaveformStat = TRUE +savePropStat = FALSE +savePropDtl = TRUE +[QtDialog] +QwInfoMsgDlg = 895,624,750,250 +openFileDlg = 969,507,602,483 +QwWarnMsgDlg = 979,700,600,250 +ActiveFileDialog = 1041,586,458,279 +SetWindowTimeUnitDialog = 1053,682,433,86 +QwUserAskDlg = 1118,667,324,134 +[Relationship] +hideRecursiceNode = FALSE +[Session Cache] +2 = string (session file name) +3 = string (session file name) +4 = string (session file name) +5 = string (session file name) +1 = /home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/chip_top/verdiLog/novas_autosave.ses +[Simulation] +scsPath = scsim +scsOption = +xlPath = verilog +xlOption = +ncPath = ncsim +ncOption = -f ncsim.args +osciPath = gdb +osciOption = +vcsPath = simv +vcsOption = +mtiPath = vsim +mtiOption = +vhncPath = ncsim +vhncOption = -log debussy.nc.log +mixncPath = ncsim +mixncOption = -log debussy.mixnc.log +speedsimPath = +speedsimOption = +mti_vlogPath = vsim +mti_vlogOption = novas_vlog +vcs_mixPath = simv +vcs_mixOption = -vhdlrun "-vhpi debussy:FSDBDumpCmd" +scs_mixPath = scsim +scs_mixOption = -vhpi debussy:FSDBDumpCmd +interactiveDebugging = {True, False} +KeepBreakPoints = False +ScsDebugAll = False +simType = {vcssv, xl, nc, vcs, mti, mti_vlog, vhnc, scs, mixnc} +thirdpartyIdx = -1 +iscCmdSep = FALSE +NoAppendOption = False +[SimulationPlus] +xlPath = verilog +xlOption = +ncPath = ncsim +ncOption = -f ncsim.args +vcsPath = simv +vcsOption = +mti_vlogPath = vsim +mti_vlogOption = novas_vlog +mtiPath = vsim +mtiOption = +vhncPath = ncsim +vhncOption = -log debussy.nc.log +speedsimPath = verilog +speedsimOption = +mixncPath = ncsim +mixncOption = -log debussy.mixnc.log +scsPath = scsim +scsOption = +vcs_mixPath = simv +vcs_mixOption = -vhdlrun "-vhpi debussy:FSDBDumpCmd" +scs_mixPath = scsim +scs_mixOption = -vhpi debussy:FSDBDumpCmd +vcs_svPath = simv +vcs_svOption = +simType = vcssv +thirdpartyIdx = -1 +interactiveDebugging = FALSE +KeepBreakPoints = FALSE +iscCmdSep = FALSE +ScsDebugAll = FALSE +NoAppendOption = FALSE +invokeSimPath = work +[SimulationPlus2] +eventDumpUnfinish = FALSE +[Source] +wordWrapOn = TRUE +viewReuse = TRUE +lineNumberOn = TRUE +warnOutdatedDlg = TRUE +showEncrypt = FALSE +loadInclude = FALSE +showColorForActive = FALSE +tabWidth = 8 +editor = vi +reload = Never +sync_active_to_source = TRUE +navigateAsColored = FALSE +navigateCovered = FALSE +navigateUncovered = TRUE +navigateExcluded = FALSE +not_ask_for_source_path = FALSE +expandMacroOn = TRUE +expandMacroInstancesThreshold = 10000 +[SourceVHDL] +vhSimType = ModelSim +ohSimType = VerilogXL +[TclShell] +nLineSize = 1024 +[Test] +verbose_progress = FALSE +[TestBenchBrowser] +-showUVMDynamicHierTreeWin = FALSE +[Text] +hdlTypeName = blue4 +hdlLibrary = blue4 +viewport = 396 392 445 487 +hdlOther = ID_BLACK +hdlComment = ID_GRAY1 +hdlKeyword = ID_BLUE5 +hdlEntity = ID_BLACK +hdlEntityInst = ID_BLACK +hdlSignal = ID_RED2 +hdlInSignal = ID_RED2 +hdlOutSignal = ID_RED2 +hdlInOutSignal = ID_RED2 +hdlOperator = ID_BLACK +hdlMinus = ID_BLACK +hdlSymbol = ID_BLACK +hdlString = ID_BLACK +hdlNumberBase = ID_BLACK +hdlNumber = ID_BLACK +hdlLiteral = ID_BLACK +hdlIdentifier = ID_BLACK +hdlSystemTask = ID_BLACK +hdlParameter = ID_BLACK +hdlIncFile = ID_BLACK +hdlDataFile = ID_BLACK +hdlCDSkipIf = ID_GRAY1 +hdlMacro = ID_BLACK +hdlMacroValue = ID_BLACK +hdlPlainText = ID_BLACK +hdlOvaId = ID_PURPLE2 +hdlPslId = ID_PURPLE2 +HvlEId = ID_BLACK +HvlVERAId = ID_BLACK +hdlEscSignal = ID_BLACK +hdlEscInSignal = ID_BLACK +hdlEscOutSignal = ID_BLACK +hdlEscInOutSignal = ID_BLACK +textBackgroundColor = ID_GRAY6 +textHiliteBK = ID_BLUE5 +textHiliteText = ID_WHITE +textTracedMark = ID_GREEN2 +textLineNo = ID_BLACK +textFoldedLineNo = ID_RED5 +textUserKeyword = ID_GREEN2 +textParaAnnotText = ID_BLACK +textFuncAnnotText = ID_BLUE2 +textAnnotText = ID_BLACK +textUserDefAnnotText = ID_BLACK +ComputedSignal = ID_PURPLE5 +textAnnotTextShadow = ID_WHITE +parenthesisBGColor = ID_YELLOW5 +codeInParenthesis = ID_CYAN5 +text3DLight = ID_WHITE +text3DShadow = ID_BLACK +textHvlDriver = ID_GREEN3 +textHvlLoad = ID_YELLOW3 +textHvlDriverLoad = ID_BLUE3 +irOutline = ID_RED2 +irDriver = ID_YELLOW5 +irLoad = ID_BLACK +irBookMark = ID_YELLOW2 +irIndicator = ID_WHITE +irBreakpoint = ID_GREEN5 +irCurLine = ID_BLUE5 +hdlVhEntity = ID_BLACK +hdlArchitecture = ID_BLACK +hdlPackage = ID_BLUE5 +hdlRefPackage = ID_BLUE5 +hdlAlias = ID_BLACK +hdlGeneric = ID_BLUE5 +specialAnnotShadow = ID_BLUE1 +hdlZeroInHead = ID_GREEN2 +hdlZeroInComment = ID_GREEN2 +hdlPslHead = ID_GRAY1 +hdlPslComment = ID_GRAY1 +hdlSynopsysHead = ID_GREEN2 +hdlSynopsysComment = ID_GREEN2 +pdmlIdentifier = ID_BLACK +pdmlCommand = ID_BLACK +pdmlMacro = ID_BLACK +font = COURIER12 +annotFont = Helvetica_M_R_10 +[Text.1] +viewport = -1 27 2560 1337 45 +[TextPrinter] +Orientation = Landscape +Indicator = FALSE +LineNum = TRUE +FontSize = 7 +Column = 2 +Annotation = TRUE +[Texteditor] +TexteditorFont = "Clean 14" +TexteditorBG = white +TexteditorFG = black +[ThirdParty] +ThirdPartySimTool = verisity surefire ikos finsim +[TurboEditor] +autoBackup = TRUE +[UserButton.mixnc] +Button1 = "Dump All Signals" "call fsdbDumpvars\n" +Button2 = "Next 1000 Time" "run 1000 -relative\n" +Button3 = "Next ? Time" "run ${Arg:Next Time} -relative\n" +Button4 = "Run Next" "run -next\n" +Button5 = "Run Step" "run -step\n" +Button6 = "Run Return" "run -return\n" +Button7 = "Show Variables" "value {${NCSelVars}}\n" +Button8 = "FSDB Ver" "call fsdbVersion" +Button9 = "Dump On" "call fsdbDumpon" +Button10 = "Dump Off" "call fsdbDumpoff" +Button11 = "All Tasks" "call" +Button12 = "Dump Selected Instance" "call fsdbDumpvars 1 ${SelInst}" +[UserButton.mti] +Button1 = "Dump All Signals" "fsdbDumpvars\n" +Button2 = "Next 1000 Time" "run 1000\n" +Button3 = "Next ? Time" "run ${Arg:Next Time}\n" +Button4 = "Show Variables" "exa ${SelVars}\n" +Button5 = "Force Variable" "force -freeze ${SelVar} ${Arg:New Value} 0\n" +Button6 = "Release Variable" "noforce ${SelVar}\n" +Button7 = "Deposit Variable" "force -deposit ${SelVar} ${Arg:New Value} 0\n" +[UserButton.mti_vlog] +Button1 = "Dump All Signals" "fsdbDumpvars\n" +Button2 = "Next 1000 Time" "run 1000\n" +Button3 = "Next ? Time" "run ${Arg:Next Time}\n" +Button4 = "Show Variables" "exa ${SelVars}\n" +Button5 = "Force Variable" "force -freeze ${SelVar} ${Arg:New Value} 0\n" +Button6 = "Release Variable" "noforce ${SelVar}\n" +Button7 = "Deposit Variable" "force -deposit ${SelVar} ${Arg:New Value} 0\n" +[UserButton.nc] +Button1 = "Dump All Signals" "call fsdbDumpvars\n" +Button2 = "Next 1000 Time" "run 1000 -relative\n" +Button3 = "Next ? Time" "run ${Arg:Next Time} -relative\n" +Button4 = "Run Next" "run -next\n" +Button5 = "Run Step" "run -step\n" +Button6 = "Run Return" "run -return\n" +Button7 = "Show Variables" "value {${NCSelVars}}\n" +[UserButton.scs] +Button1 = "Dump All Signals" "call fsdbDumpvars(0, \"${TopScope}\");\n" +Button2 = "Next 1000 Time" "run 1000 \n" +Button3 = "Next ? Time" "run ${Arg:Next Time} \n" +Button4 = "Run Step" "step\n" +Button5 = "Show Variables" "ls -v {${SelVars}}\n" +[UserButton.vhnc] +Button1 = "Dump All Signals" "call fsdbDumpvars\n" +Button2 = "Next 1000 Time" "run 1000 -relative\n" +Button3 = "Next ? Time" "run ${Arg:Next Time} -relative\n" +Button4 = "Run Next" "run -next\n" +Button5 = "Run Step" "run -step\n" +Button6 = "Run Return" "run -return\n" +Button7 = "Show Variables" "value {${NCSelVars}}\n" +[UserButton.xl] +Button13 = "Dump Off" "$fsdbDumpoff;\n" +Button12 = "Dump On" "$fsdbDumpon;\n" +Button11 = "Delete Focus" "$db_deletefocus(${treeSelScope});\n" +Button10 = "Set Focus" "$db_setfocus(${treeSelScope});\n" +Button9 = "Deposit Variable" "$deposit(${SelVar},${Arg:New Value});\n" +Button8 = "Release Variable" "release ${SelVar};\n" +Button7 = "Force Variable" "force ${SelVar} = ${Arg:New Value};\n" +Button6 = "Show Variables" "$showvars(${SelVars});\n" +Button5 = "Next ? Event" "$db_step(${Arg:Next Event});\n" +Button4 = "Next Event" "$db_step(1);\n" +Button3 = "Next ? Time" "#${Arg:Next Time} $stop;.\n" +Button2 = "Next 1000 Time" "#1000 $stop;.\n" +Button1 = "Dump All Signals" "$fsdbDumpvars;\n" +[VIA] +viaLogViewerDefaultRuleOneSearchForm = "share/VIA/Apps/PredefinedRules/Misc/Onesearch_rule.rc" +[VIA.oneSearch.preference] +DefaultDisplayTimeUnit = "1.000000ns" +DefaultLogTimeUnit = "1.000000ns" +[VIA.oneSearch.preference.vgifColumnSettingRC] +[VIA.oneSearch.preference.vgifColumnSettingRC.setting0] +parRuleSets = "" +[VIA.oneSearch.preference.vgifColumnSettingRC.setting0.column0] +name = Time +width = 60 +visualIndex = 0 +isHidden = TRUE +isUserChangeColumnVisible = FALSE +[VIA.oneSearch.preference.vgifColumnSettingRC.setting0.column1] +name = Code +width = 60 +visualIndex = 2 +isHidden = TRUE +isUserChangeColumnVisible = FALSE +[VIA.oneSearch.preference.vgifColumnSettingRC.setting0.column2] +name = Type +width = 60 +visualIndex = 3 +isHidden = TRUE +isUserChangeColumnVisible = FALSE +[VIA.oneSearch.preference.vgifColumnSettingRC.setting0.column3] +name = Message +width = 2000 +visualIndex = 4 +isHidden = FALSE +isUserChangeColumnVisible = FALSE +[VIA.oneSearch.preference.vgifColumnSettingRC.setting0.column4] +name = Severity +width = 60 +visualIndex = 1 +isHidden = TRUE +isUserChangeColumnVisible = FALSE +[Vi] +ViFont = "Clean 14" +ViBG = white +ViFG = black +[Wave] +ovaEventSuccessColor = -c ID_CYAN5 +ovaEventFailureColor = -c ID_RED5 +ovaBooleanSuccessColor = -c ID_CYAN5 +ovaBooleanFailureColor = -c ID_RED5 +ovaAssertSuccessColor = -c ID_GREEN5 +ovaAssertFailureColor = -c ID_RED5 +ovaForbidSuccessColor = -c ID_GREEN5 +SigGroupRuleFile = +DisplayFileName = FALSE +waveform_vertical_scroll_bar = TRUE +getSignalForm = 0 0 800 479 100 30 100 30 +viewPort = 0 27 2560 668 308 65 +signalSpacing = 5 +digitalSignalHeight = 15 +analogSignalHeight = 98 +commentSignalHeight = 98 +transactionSignalHeight = 98 +messageSignalHeight = 98 +minCompErrWidth = 4 +DragZoomTolerance = 4 +maxTransExpandedLayer = 10 +WaveMaxPoint = 512 +legendBackground = -c ID_BLACK +valueBackground = -c ID_BLACK +curveBackground = -c ID_BLACK +getSignalSignalList_BackgroundColor = -c ID_GRAY6 +glitchColor = -c ID_RED5 +cursor = -c ID_YELLOW5 -lw 1 -ls long_dashed +marker = -c ID_WHITE -lw 1 -ls dash_dot_l +usermarker = -c ID_GREEN5 -lw 1 -ls long_dashed +trace = -c ID_GRAY5 -lw 1 -ls long_dashed +grid = -c ID_WHITE -lw 1 -ls short_dashed +rulerBackground = -c ID_GRAY3 +rulerForeground = -c ID_YELLOW5 +busTextColor = -c ID_ORANGE8 +legendForeground = -c ID_CYAN5 +valueForeground = -c ID_CYAN5 +curveForeground = -c ID_CYAN5 +groupNameColor = -c ID_GREEN5 +commentStringColor = -c ID_RED5 +region(Active)Background = -c ID_YELLOW1 +region(NBA)Background = -c ID_RED1 +region(Re-Active)Background = -c ID_YELLOW3 +region(Re-NBA)Background = -c ID_RED3 +region(VHDL-Delta)Background = -c ID_ORANGE3 +region(Dump-Off)Background = -c ID_GRAY4 +High_Light = -c ID_GRAY2 +Input_Signal = -c ID_RED5 +Output_Signal = -c ID_GREEN5 +InOut_Signal = -c ID_BLUE5 +Net_Signal = -c ID_YELLOW5 +Register_Signal = -c ID_PURPLE5 +Verilog_Signal = -c ID_CYAN5 +VHDL_Signal = -c ID_ORANGE5 +SystemC_Signal = -c ID_BLUE7 +Dump_Off_Color = -c ID_BLUE2 +Compress_Bar_Color = -c ID_YELLOW4 +Vector_Dense_Block_Color = -c ID_ORANGE8 +Scalar_Dense_Block_Color = -c ID_GREEN6 +Analog_Dense_Block_Color = -c ID_PURPLE2 +Composite_Dense_Block_Color = -c ID_ORANGE5 +RPTR_Power_Off_Layer = -c ID_CYAN3 -stipple dots +DB_Power_Off_Layer = -c ID_BLUE4 -stipple dots +SPA_Driver_Power_Off_Layer = -c ID_ORANGE4 -stipple dots +SPA_Receiver_Power_Off_Layer = -c ID_GREEN5 -stipple dots +SRSN_Power_Off_Layer = -c ID_GREEN4 -stipple dots +Isolation_Power_Off_Layer = -c ID_RED4 -stipple dots +PD_Power_Off_Layer = -c ID_GRAY4 -stipple dots +Isolation_Layer = -c ID_RED4 -stipple vLine +Retention_Level_Trigger_Layer = -c ID_ORANGE1 -stipple fill_solid +Retention_Edge_Trigger_Layer = -c ID_YELLOW6 -stipple fill_solid +Driving_Power_Off_Layer = -c ID_YELLOW2 -stipple x +Toggle_Layer = -c ID_YELLOW4 -stipple slash +analogRealStyle = pwl +analogVoltageStyle = pwl +analogCurrentStyle = pwl +analogOthersStyle = pwl +busSignalLayer = -c ID_ORANGE8 +busXLayer = -c ID_RED5 +busZLayer = -c ID_ORANGE6 +busMixedLayer = -c ID_GREEN5 +busNotComputedLayer = -c ID_GRAY1 +busNoValueLayer = -c ID_BLUE2 +signalGridLayer = -c ID_WHITE +analogGridLayer = -c ID_GRAY6 +analogRulerLayer = -c ID_GRAY6 +keywordLayer = -c ID_RED5 +loadedLayer = -c ID_BLUE5 +loadingLayer = -c ID_BLACK +qdsCurMarkerLayer = -c ID_BLUE5 +qdsBrkMarkerLayer = -c ID_GREEN5 +qdsTrgMarkerLayer = -c ID_RED5 +arrowDefaultColor = -c ID_ORANGE6 +startNodeArrowColor = -c ID_WHITE +endNodeArrowColor = -c ID_YELLOW5 +propertyEventMatchColor = -c ID_GREEN5 +propertyEventNoMatchColor = -c ID_RED5 +propertyVacuousSuccessMatchColor = -c ID_YELLOW2 +propertyStatusBoundaryColor = -c ID_WHITE +propertyBooleanSuccessColor = -c ID_CYAN5 +propertyBooleanFailureColor = -c ID_RED5 +propertyAssertSuccessColor = -c ID_GREEN5 +propertyAssertFailureColor = -c ID_RED5 +propertyForbidSuccessColor = -c ID_GREEN5 +transactionForegroundColor = -c ID_YELLOW8 +transactionBackgroundColor = -c ID_BLACK +transactionHighLightColor = -c ID_CYAN6 +transactionRelationshipColor = -c ID_PURPLE6 +transactionErrorTypeColor = -c ID_RED5 +coverageFullyCoveredColor = -c ID_GREEN5 +coverageNoCoverageColor = -c ID_RED5 +coveragePartialCoverageColor = -c ID_YELLOW5 +coverageReferenceLineColor = -c ID_GRAY4 +messageForegroundColor = -c ID_YELLOW4 +messageBackgroundColor = -c ID_PURPLE1 +messageHighLightColor = -c ID_CYAN6 +messageInformationColor = -c ID_RED5 +ComputedAnnotColor = -c ID_PURPLE5 +fsvSecurityDataColor = -c ID_PURPLE3 +qdsAutoBusGroup = TRUE +qdsTimeStampMode = FALSE +qdsVbfBusOrderAscending = FALSE +openDumpFilter = *.fsdb;*.vf;*.jf +DumpFileFilter = *.vcd +RestoreSignalFilter = *.rc +SaveSignalFilter = *.rc +AddAliasFilter = *.alias;*.adb +CompareSignalFilter = *.err +ConvertFFFilter = *.vcd;*.out;*.tr0;*.xp;*.raw;*.wfm +Scroll_Ratio = 100 +Zoom_Ratio = 10 +EventSequence_SyncCursorTime = TRUE +EventSequence_Sorting = FALSE +EventSequence_RemoveGrid = FALSE +EventSequence_IsGridMode = FALSE +SetDefaultRadix_global = FALSE +DefaultRadix = Hex +SigSearchSignalMatchCase = FALSE +SigSearchSignalScopeOption = FALSE +SigSearchSignalSamenetInterface = FALSE +SigSearchSignalFullScope = FALSE +SigSearchSignalWithRegExp = FALSE +SigSearchDynamically = FALSE +SigDisplayBySelectionOrder = FALSE +SigDisplayRowMajor = FALSE +SigDragSelFollowColumn = FALSE +SigDisplayHierarchyBox = TRUE +SigDisplaySubscopeBox = TRUE +SigDisplayEmptyScope = TRUE +SigDisplaySignalNavigationBox = FALSE +SigDisplayFormBus = TRUE +SigShowSubProgram = TRUE +SigSearchScopeDynamically = TRUE +SigCollapseSubtreeNodes = FALSE +activeFileApplyToAnnotation = FALSE +GrpSelMode = TRUE +dispGridCount = FALSE +hierarchyName = FALSE +partial_level_name = FALSE +partial_level_head = 1 +partial_level_tail = 1 +displayMessageLabelOnly = TRUE +autoInsertDumpoffs = TRUE +displayMessageCallStack = FALSE +displayCallStackWithFullSections = TRUE +displayCallStackWithLastSection = FALSE +limitMessageMaxWidth = FALSE +messageMaxWidth = 50 +displayTransBySpecificColor = FALSE +fittedTransHeight = FALSE +snap = TRUE +gravitySnap = FALSE +displayLeadingZero = FALSE +displayGlitchs = FALSE +allfileTimeRange = FALSE +fixDelta = FALSE +displayCursorMarker = FALSE +autoUpdate = FALSE +restoreFromActiveFile = TRUE +restoreToEnd = FALSE +dispCompErr = TRUE +showMsgDes = TRUE +anaAutoFit = FALSE +anaAutoPattn = FALSE +anaAuto100VertFit = FALSE +displayDeltaY = FALSE +centerCursor = FALSE +denseBlockDrawing = TRUE +relativeFreqPrecision = 3 +showMarkerAbsolute = FALSE +showMarkerAdjacent = FALSE +showMarkerRelative = FALSE +showMarkerFrequency = FALSE +stickCursorMarkerOnWaveform = TRUE +keepMarkerAtEndTimeOfTransaction = FALSE +doubleClickToExpandTransaction = TRUE +expandTransactionAssociatedSignals = TRUE +expandTransactionAttributeSignals = FALSE +WaveExtendLastTick = TRUE +InOutSignal = FALSE +NetRegisterSignal = FALSE +VerilogVHDLSignal = FALSE +LabelMarker = TRUE +ResolveSymbolicLink = TRUE +signal_rc_abspath = TRUE +signal_rc_no_natural_bus_range = FALSE +save_scope_with_macro = FALSE +scope_to_save_with_macro +TipInSignalWin = FALSE +DisplayPackedSiganlInBitwiseManner = FALSE +DisplaySignalTypeAheadOfSignalName = TRUE ICON +TipInCurveWin = FALSE +MouseGesturesInCurveWin = TRUE +DisplayLSBsFirst = FALSE +PaintSpecificColorPattern = TRUE +ModuleName = TRUE +form_all_memory_signal = FALSE +formBusSignalFromPartSelects = FALSE +read_value_change_on_demand_for_drawing = FALSE +load_scopes_on_demand = on 5 +TransitionMode = TRUE +DisplayRadix = FALSE +SchemaX = FALSE +Hilight = TRUE +UseBeforeValue = FALSE +DisplayFileNameAheadOfSignalName = FALSE +DisplayFileNumberAheadOfSignalName = FALSE +DisplayValueSpace = TRUE +FitAnaByBusSize = FALSE +displayTransactionAttributeName = FALSE +expandOverlappedTrans = FALSE +dispSamplePointForAttrSig = TRUE +dispClassName = TRUE +ReloadActiveFileOnly = FALSE +NormalizeEVCD = FALSE +OverwriteAliasWithRC = TRUE +overlay_added_analog_signals = FALSE +case_insensitive = FALSE +vhdlVariableCalculate = TRUE +showError = TRUE +signal_vertical_scroll_bar = TRUE +showPortNameForDroppedInstance = FALSE +truncateFilePathInTitleBar = TRUE +filterPropVacuousSuccess = FALSE +includeLocalSignals = FALSE +encloseSignalsByGroup = TRUE +resaveSignals = TRUE +adjustBusPrefix = adjustBus_ +adjustBusBits = 1 +adjustBusSettings = 69889 +maskPowerOff = TRUE +maskIsolation = TRUE +maskRetention = TRUE +maskDrivingPowerOff = TRUE +maskToggle = TRUE +autoBackupSignals = off 5 "\"/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/chip_top/verdiLog\"" "\"novas_autosave_sig\"" +signal_rc_attribute = 65535 +signal_rc_alias_attribute = 0 +ConvertAttr1 = -inc FALSE +ConvertAttr2 = -hier FALSE +ConvertAttr3 = -ucase FALSE +ConvertAttr4 = -lcase FALSE +ConvertAttr5 = -org FALSE +ConvertAttr6 = -mem 24 +ConvertAttr7 = -deli . +ConvertAttr8 = -hier_scope FALSE +ConvertAttr9 = -inst_array FALSE +ConvertAttr10 = -vhdlnaming FALSE +ConvertAttr11 = -orgScope FALSE +analogFmtPrecision = Automatic 2 +confirmOverwrite = TRUE +confirmExit = TRUE +confirmGetAll = TRUE +printTimeRange = TRUE 0.000000 0.000000 0.000000 +printPageRange = TRUE 1 1 +printOption = 0 +printBasic = 1 0 0 FALSE FALSE +printDest = -printer {} +printSignature = {%f %h %t} {} +curveWindow_Drag&Drop_Mode = TRUE +hspiceIncOpenMode = TRUE +pcSelectMode = TRUE +hierarchyDelimiter = / +RecentFile1 = "\"/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/chip_top/verdplus_000.fsdb\"" +open_file_time_range = FALSE +open_file_dir +open_rc_file_dir +value_window_aligment = Right +signal_window_alignment = Auto +ShowDeltaTime = TRUE +legend_window_font = -f COURIER12 -c ID_CYAN5 +value_window_font = -f COURIER12 -c ID_CYAN5 +curve_window_font = -f COURIER12 -c ID_CYAN5 +group_name_font = -f COURIER12 -c ID_GREEN5 +ruler_value_font = -f COURIER12 -c ID_CYAN5 +analog_ruler_value_font = -f COURIER12 -c ID_CYAN5 +comment_string_font = -f COURIER12 -c ID_RED5 +getsignal_form_font = -f COURIER12 +SigsCheckNum = on 1000 +filter_synthesized_net = off n +filterOutNet = on +filter_synthesized_instance = off +filterOutInstance = on +showGroupTree = TRUE +hierGroupDelim = / +MsgSeverityColor = {y \"Severity\"==\"1\" ID_RED5} {y \"Severity\"==\"2\" ID_RED6} {y \"Severity\"==\"3\" ID_RED7} {y \"Severity\"==\"4\" ID_RED8} {y \"Severity\"==\"5\" ID_ORANGE5} {y \"Severity\"==\"6\" ID_ORANGE6} {y \"Severity\"==\"7\" ID_ORANGE7} {y \"Severity\"==\"8\" \ +ID_GREEN7} {y \"Severity\"==\"9\" ID_GREEN6} {y \"Severity\"==\"10\" ID_GREEN5} +AutoApplySeverityColor = TRUE +AutoAdjustMsgWidthByLabel = off +verilogStrengthDispType = type1 +waveDblClkActiveTrace = on +autoConnectTBrowser = FALSE +connectTBrowserInContainer = TRUE +SEQShowComparisonIcon = TRUE +SEQAddDriverLoadInSameGroup = TRUE +autoSyncCursorMarker = FALSE +autoSyncHorizontalRange = FALSE +autoSyncVerticalScroll = FALSE +[cov_hier_name_column] +justify = TRUE +[coverageColors] +sou_uncov = TRUE +sou_pc = TRUE +sou_cov = TRUE +sou_exuncov = TRUE +sou_excov = TRUE +sou_unreach = TRUE +sou_unreachcon = TRUE +sou_fillColor_uncov = red +sou_fillColor_pc = yellow +sou_fillColor_cov = green3 +sou_fillColor_exuncov = grey +sou_fillColor_excov = #3C9371 +sou_fillColor_unreach = grey +sou_fillColor_unreachcon = orange +numberOfBins = 6 +rangeMin_0 = 0 +rangeMax_0 = 20 +fillColor_0 = #FF6464 +rangeMin_1 = 20 +rangeMax_1 = 40 +fillColor_1 = #FF9999 +rangeMin_2 = 40 +rangeMax_2 = 60 +fillColor_2 = #FF8040 +rangeMin_3 = 60 +rangeMax_3 = 80 +fillColor_3 = #FFFF99 +rangeMin_4 = 80 +rangeMax_4 = 100 +fillColor_4 = #99FF99 +rangeMin_5 = 100 +rangeMax_5 = 100 +fillColor_5 = #64FF64 +[coveragesetting] +assertTopoMode = FALSE +urgAppendOptions = +group_instance_new_format_name = TRUE +showvalue = FALSE +computeGroupsScoreByRatio = FALSE +computeGroupsScoreByInst = FALSE +showConditionId = FALSE +showfullhier = FALSE +nameLeftAlignment = TRUE +showAllInfoInTooltips = FALSE +copyItemHvpName = TRUE +ignoreGroupWeight = FALSE +absTestName = FALSE +HvpMergeTool = +ShowMergeMenuItem = FALSE +fsmScoreMode = transition +[eco] +IsFreezeSilicon = FALSE +cellQuantityManagement = FALSE +ManageMode = INSTANCE_NAME +SpareCellsPinsManagement = TRUE +LogCommitReport = FALSE +InputPinStatus = 1 +OutputPinStatus = 2 +NameRule = +RevisedComponentColor = ID_BLUE5 +SpareCellColor = ID_RED5 +UserName = ICer +CommentFormat = Novas ECO updated by ${UserName} ${Date} ${Time} +PrefixN = eco_n +PrefixP = eco_p +PrefixI = eco_i +DefaultTieUpNet = 1'b1 +DefaultTieDownNet = 1'b0 +MultipleInstantiations = TRUE +KeepClockPinConnection = FALSE +KeepAsyncResetPinConnection = FALSE +ScriptFileModeType = 1 +MagmaScriptPower = VDD +MagmaScriptGround = GND +ShowModeMsg = TRUE +AstroScriptPower = VDD +AstroScriptGround = VSS +ClearFloatingPorts = FALSE +[eco_connection] +Port/NetIsUnique = TRUE +SerialNet = 0 +SerialPort = 0 +SerialInst = 0 +[finsim] +TPLanguage = Verilog +TPName = Super-FinSim +TPPath = TOP.sim +TPOption = +AddImportArgument = FALSE +LineBreakWithScope = FALSE +StopAfterCompileOption = -i +[hvpsetting] +importExcelXMLOptions = +use_test_loca_as_source = FALSE +autoTurnOffHideMeetGoalInit = FALSE +autoTurnOffHideMeetGoal = TRUE +autoTurnOffModifierInit = FALSE +autoTurnOffModifier = TRUE +enableNumbering = TRUE +autoSaveCheck = TRUE +autoSaveTime = 5 +ShowMissingScore = TRUE +enableFeatureId = FALSE +enable_HVP_FEAT_ID = FALSE +enableMeasureConcealment = FALSE +HvpCloneHierShowMsgAgain = 1 +HvpCloneHierType = tree +HvpCloneHierMetrics = Line,Cond,FSM,Toggle,Branch,Assert +autoRecalPlanAfterLoadingCovDBUserDataPlan = false +warnMeAutoRecalPlanAfterLoadingCovDBUserDataPlan = true +autoRecalExclWithPlan = false +warnMeAutoRecalExclWithPlan = true +autoRecalPlanWithExcl = false +warnMeAutoRecalPlanWithExcl = true +warnPopupWarnWhenMultiFilters = true +warnPopupWarnIfHvpReadOnly = true +unmappedObjsReportLevel = def_var_inst +unmappedObjsReportInst = true +unmappedObjsNumOfObjs = High +[ikos] +TPLanguage = VHDL +TPName = Voyager +TPPath = vsh +TPOption = -X +AddImportArgument = FALSE +LineBreakWithScope = FALSE +StopAfterCompileOption = -i +[imp] +options = NULL +libPath = NULL +libDir = NULL +[nCompare] +ErrorViewport = 80 180 800 550 +EditorViewport = 409 287 676 475 +EditorHeightWidth = 802 380 +WaveCommand = "novas" +WaveArgs = "-nWave" +[nCompare.Wnd0] +ViewByHier = FALSE +[nMemory] +dispMode = ADDR_HINT +addrColWidth = 120 +valueColWidth = 100 +showCellBitRangeWithAddr = TRUE +wordsShownInOneRow = 8 +syncCursorTime = FALSE +fixCellColumnWidth = FALSE +font = Courier 12 +[planColors] +plan_fillColor_inactive = lightGray +plan_fillColor_warning = orange +plan_fillColor_error = red +plan_fillColor_invalid = #F0DCDB +plan_fillColor_subplan = lightGray +[schematics] +schBackgroundColor = black lineSolid +schBackgroundColor_qt = #000000 qt_solidLine 1 +schBodyColor = orange6 lineSolid +schBodyColor_qt = #ffb973 qt_solidLine 1 +schAsmBodyColor = blue7 lineSolid +schAsmBodyColor_qt = #a5a5ff qt_solidLine 1 +schPortColor = orange6 lineSolid +schPortColor_qt = #ffb973 qt_solidLine 1 +schCellNameColor = Gray6 lineSolid +schCellNameColor_qt = #e0e0e0 qt_solidLine 1 +schCLKNetColor = red6 lineSolid +schCLKNetColor_qt = #ff7373 qt_solidLine 1 +schPWRNetColor = red4 lineSolid +schPWRNetColor_qt = #ff0101 qt_solidLine 1 +schGNDNetColor = cyan4 lineSolid +schGNDNetColor_qt = #01ffff qt_solidLine 1 +schSIGNetColor = green8 lineSolid +schSIGNetColor_qt = #cdffcd qt_solidLine 1 +schTraceColor = yellow4 lineSolid +schTraceColor_qt = #ffff01 qt_solidLine 2 +schBackAnnotateColor = white lineSolid +schBackAnnotateColor_qt = #ffffff qt_solidLine 1 +schValue0 = yellow4 lineSolid +schValue0_qt = #ffff01 qt_solidLine 1 +schValue1 = green3 lineSolid +schValue1_qt = #008000 qt_solidLine 1 +schValueX = red4 lineSolid +schValueX_qt = #ff0101 qt_solidLine 1 +schValueZ = purple7 lineSolid +schValueZ_qt = #ffcdff qt_solidLine 1 +dimColor = cyan2 lineSolid +dimColor_qt = #008080 qt_solidLine 1 +schPreSelColor = green4 lineDash +schPreSelColor_qt = #01ff01 qt_dashLine 2 +schSIGBusNetColor = green8 lineSolid +schSIGBusNetColor_qt = #cdffcd qt_solidLine +schGNDBusNetColor = cyan4 lineSolid +schGNDBusNetColor_qt = #01ffff qt_solidLine +schPWRBusNetColor = red4 lineSolid +schPWRBusNetColor_qt = #ff0101 qt_solidLine +schCLKBusNetColor = red6 lineSolid +schCLKBusNetColor_qt = #ff7373 qt_solidLine +schEdgeSensitiveColor = orange6 lineSolid +schEdgeSensitiveColor_qt = #ffb973 qt_solidLine +schAnnotColor = cyan4 lineSolid +schAnnotColor_qt = #01ffff qt_solidLine +schInstNameColor = orange6 lineSolid +schInstNameColor_qt = #ffb973 qt_solidLine +schPortNameColor = cyan4 lineSolid +schPortNameColor_qt = #01ffff qt_solidLine +schAsmLatchColor = cyan4 lineSolid +schAsmLatchColor_qt = #01ffff qt_solidLine +schAsmRegColor = cyan4 lineSolid +schAsmRegColor_qt = #01ffff qt_solidLine +schAsmTriColor = cyan4 lineSolid +schAsmTriColor_qt = #01ffff qt_solidLine +pre_select = True +ShowPassThroughNet = False +ComputedAnnotColor = ID_PURPLE5 +viewport = 0 27 1714 574 +[schematics_print] +Signature = FALSE +DesignName = PCU +DesignerName = bai +SignatureLocation = LowerRight +MultiPage = TRUE +AutoSliver = FALSE +[sourceColors] +BackgroundActive = gray88 +BackgroundInactive = lightgray +InactiveCode = dimgray +Selection = darkblue +Standard = black +Keyword = blue +Comment = gray25 +Number = black +String = black +Identifier = darkred +Inline = green +colorIdentifier = green +Value = darkgreen +MacroBackground = white +Missing = #400040 +[specColors] +top_plan_linked = #ADFFA6 +top_plan_ignore = #D3D3D3 +top_plan_todo = #EECBAD +sub_plan_ignore = #919191 +sub_plan_todo = #EFAFAF +sub_plan_linked = darkorange +[spec_link_setting] +use_spline = true +goto_section = false +exclude_ignore = true +truncate_abstract = false +abstract_length = 999 +compare_strategy = 2 +auto_apply_margin = FALSE +margin_top = 0.80 +margin_bottom = 0.80 +margin_left = 0.50 +margin_right = 0.50 +margin_unit = inches +[spiceDebug] +ThroughNet = ID_YELLOW5 +InstrumentSig = ID_GREEN5 +InterfaceElement = ID_GREEN5 +Run-timeInterfaceElement = ID_BLUE5 +HighlightThroughNet = TRUE +HighlightInterfaceElement = TRUE +HighlightRuntimeInterfaceElement = TRUE +HighlightSameNet = TRUE +[surefire] +TPLanguage = Verilog +TPName = SureFire +TPPath = verilog +TPOption = +AddImportArgument = TRUE +LineBreakWithScope = TRUE +StopAfterCompileOption = -tcl +[turboSchema_Printer_Options] +Orientation = Landscape +[turbo_library] +bdb_load_scope = +[vdCovFilteringSearchesStrings] +keepLastUsedFiltersMaxNum = 10 +[verisity] +TPLanguage = Verilog +TPName = "Verisity SpeXsim" +TPPath = vlg +TPOption = +AddImportArgument = FALSE +LineBreakWithScope = TRUE +StopAfterCompileOption = -s +[wave.0] +viewPort = 0 27 2560 668 308 65 +[wave.1] +viewPort = 127 219 960 332 100 65 +[wave.2] +viewPort = 38 314 686 205 100 65 +[wave.3] +viewPort = 63 63 700 400 65 41 +[wave.4] +viewPort = 84 84 700 400 65 41 +[wave.5] +viewPort = 92 105 700 400 65 41 +[wave.6] +viewPort = 0 0 700 400 65 41 +[wave.7] +viewPort = 21 21 700 400 65 41 diff --git a/tb/chip_top/verdiLog/novas_autosave.ses b/tb/chip_top/verdiLog/novas_autosave.ses new file mode 100644 index 0000000..d101963 --- /dev/null +++ b/tb/chip_top/verdiLog/novas_autosave.ses @@ -0,0 +1,247 @@ +@verdi rc file Version 1.0 +[General] +saveDB = TRUE +relativePath = FALSE +saveSingleView = FALSE +saveNWaveWinId = +VerdiVersion = Verdi_O-2018.09-SP2 +[KeyNote] +Line1 = Automatic Backup 0 +Line2 = Save Open Database Information: Yes +Line3 = Path Option: Absolute Paths +Line4 = Windows Option: All Windows +[TestBench] +ConstrViewShow = 0 +InherViewShow = 0 +FSDBMsgShow = 0 +AnnotationShow = 0 +Console = FALSE +powerDumped = 0 +[hb] +postSimFile = /home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/chip_top/verdplus_000.fsdb +syncTime = 1570449 +viewport = 0 27 2560 1337 0 0 228 898 +interactiveMode = False +viewType = Source +simulatorMode = False +sourceBeginLine = 0 +baMode = False +srcLineNum = True +AutoWrap = True +IdentifyFalseLogic = False +syncSignal = False +traceMode = Hierarchical +showTraceInSchema = True +paMode = False +funcMode = False +powerAwareAnnot = True +amsAnnot = True +traceCrossHier = True +DnDtraceCrossHierOnly = True +traceIncTopPort = False +leadingZero = False +signalPane = False +sdfCheckUndef = FALSE +simFlow = FALSE +[nMemoryManager] +WaveformFile = /home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/chip_top/verdplus_000.fsdb +UserActionNum = 0 +nMemWindowNum = 0 +[schematics.0] +viewport = 0 27 1714 575 +viewbbox = -232577 -21300 388577 164900 +design = . "TB.U_xyz_chip_top.U_digital_top.U_spi_slave.U_spi_sys" DebussyLib +schmaticId = 3 +partial = False +partialHier = False +annotData = AnnotData.0 +locatorSession = Locator.0 +display_port_name = False +display_pin_name = False +display_instance_name = False +display_local_net_name = False +display_complete_name = False +display_entity_name = True +display_arch_name = True +display_module_name = True +display_high_contrast = False +display_back_annotation = False +display_back_annotation_in_Line = False +display_param_list = False +auto_fit_select_set = False +pre_select = True +show_full_name = False +display_short_name = True +display_preselect_tip = False +append_view_obj = True +cmdToolbar = True +msgToolbar = True +syncTime = 1570449 +traceMode = Hierarchical +originate_from = from_import_scope +full_hier_partial_dis = False +detail_rtl = False +hide_extraneous_bus = True +hierFlatten = False +instrument_cell = False +gcc_level = False +PG_pin = True +power_signal = True +power_domain = True +brighten_power_color = False +sdc_annot = False +hier_flatten_view = False +auto_collapse_paths = True +group_paths = False +locator = True +align_locator_right = False +all_hier_ports = False +VCST_path_type = 0 +verdi_type_wnd = False +line_up_registers = False +through_net = True +interface_element = True +run-time_interface_element = True +magnifier = False +highlight_incomplete_net = False +quick_trace_2_point = False +show_pass_through_net = False +[schematics.1] +viewport = 0 27 1714 1029 +viewbbox = -26374 -15754 108490 60732 +design = . "TB.U_xyz_chip_top.U_digital_top.U0_channel_top" DebussyLib +schmaticId = 4 +partial = False +partialHier = False +annotData = AnnotData.1 +locatorSession = Locator.1 +display_port_name = True +display_pin_name = True +display_instance_name = False +display_local_net_name = False +display_complete_name = False +display_entity_name = True +display_arch_name = True +display_module_name = True +display_high_contrast = False +display_back_annotation = False +display_back_annotation_in_Line = False +display_param_list = False +auto_fit_select_set = False +pre_select = True +show_full_name = False +display_short_name = True +display_preselect_tip = False +append_view_obj = True +cmdToolbar = True +msgToolbar = True +syncTime = 1570449 +traceMode = Hierarchical +originate_from = from_import_scope +full_hier_partial_dis = False +detail_rtl = False +hide_extraneous_bus = True +hierFlatten = False +instrument_cell = False +gcc_level = False +PG_pin = True +power_signal = True +power_domain = True +brighten_power_color = False +sdc_annot = False +hier_flatten_view = False +auto_collapse_paths = True +group_paths = False +locator = True +align_locator_right = False +all_hier_ports = False +VCST_path_type = 0 +verdi_type_wnd = False +line_up_registers = False +through_net = True +interface_element = True +run-time_interface_element = True +magnifier = False +highlight_incomplete_net = False +quick_trace_2_point = False +show_pass_through_net = False +[schematics.2] +viewport = 0 27 1714 574 +viewbbox = 182556 745 201378 6375 +design = . "TB.U_xyz_chip_top.U_digital_top" DebussyLib +schmaticId = 5 +partial = False +partialHier = False +annotData = AnnotData.2 +locatorSession = Locator.2 +display_port_name = True +display_pin_name = True +display_instance_name = False +display_local_net_name = False +display_complete_name = False +display_entity_name = True +display_arch_name = True +display_module_name = True +display_high_contrast = False +display_back_annotation = False +display_back_annotation_in_Line = False +display_param_list = False +auto_fit_select_set = False +pre_select = True +show_full_name = False +display_short_name = True +display_preselect_tip = False +append_view_obj = True +cmdToolbar = True +msgToolbar = True +syncTime = 1570449 +traceMode = Hierarchical +originate_from = from_import_scope +full_hier_partial_dis = False +detail_rtl = False +hide_extraneous_bus = True +hierFlatten = False +instrument_cell = False +gcc_level = False +PG_pin = True +power_signal = True +power_domain = True +brighten_power_color = False +sdc_annot = False +hier_flatten_view = False +auto_collapse_paths = True +group_paths = False +locator = True +align_locator_right = False +all_hier_ports = False +VCST_path_type = 0 +verdi_type_wnd = False +line_up_registers = False +through_net = True +interface_element = True +run-time_interface_element = True +magnifier = False +highlight_incomplete_net = False +quick_trace_2_point = False +show_pass_through_net = False +[wave.0] +viewPort = 0 27 2560 668 308 65 +primaryWindow = TRUE +SessionFile = /home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/chip_top/verdiLog/novas_autosave.ses.wave.0 +displayGrid = FALSE +hierarchicalName = FALSE +snap = TRUE +displayLeadingZeros = FALSE +fixDelta = FALSE +displayCursorMarker = FALSE +autoUpdate = FALSE +highlightGlitchs = FALSE +waveformSyncCursorMarker = FALSE +waveformSyncHorizontalRange = FALSE +waveformSyncVerticalscroll = FALSE +displayErrors = TRUE +displayMsgSymbols = TRUE +showMsgDescriptions = TRUE +autoFit = FALSE +displayDeltaY = FALSE +centerCursor = FALSE diff --git a/tb/chip_top/verdiLog/novas_autosave.ses.config b/tb/chip_top/verdiLog/novas_autosave.ses.config new file mode 100644 index 0000000..2b20e16 --- /dev/null +++ b/tb/chip_top/verdiLog/novas_autosave.ses.config @@ -0,0 +1,80 @@ +[qBaseWindowStateGroup] +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qDockerWindow_qDockContentType\Verdi=1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qDockerWindow_qDockContentType\nWave=1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qDockerWindow_qDockContentType\nSchema=3 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qDockerWindow_qDockContentType\hdlHier=1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qDockerWindow_qDockContentType\hdlSrc=1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qDockerWindow_qDockContentType\messageWindow=1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qDockerWindow_qDockContentType\svtbHier=1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qDockerWindow_qDockContentType\OneSearch=1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qDockerWindowMgr_saveDockerChildList\Verdi_1=10 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qDockerWindowMgr_saveDockerChildList\Verdi_1_0=widgetDock_hdlHier_1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qDockerWindowMgr_saveDockerChildList\Verdi_1_1=widgetDock_messageWindow_1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qDockerWindowMgr_saveDockerChildList\Verdi_1_2=widgetDock_hdlSrc_1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qDockerWindowMgr_saveDockerChildList\Verdi_1_3=widgetDock_signalList_1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qDockerWindowMgr_saveDockerChildList\Verdi_1_4=widgetDock_svtbHier_1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qDockerWindowMgr_saveDockerChildList\Verdi_1_5=windowDock_OneSearch_1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qDockerWindowMgr_saveDockerChildList\Verdi_1_6=windowDock_nWave_1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qDockerWindowMgr_saveDockerChildList\Verdi_1_7=windowDock_nSchema_1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qDockerWindowMgr_saveDockerChildList\Verdi_1_8=windowDock_nSchema_2 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qDockerWindowMgr_saveDockerChildList\Verdi_1_9=windowDock_nSchema_3 +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qDockerWindow_encode_to_relative_window_id_name=true +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\widgetDock_hdlHier_1\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\widgetDock_hdlHier_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\widgetDock_hdlHier_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\widgetDock_hdlHier_1\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\widgetDock_messageWindow_1\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\widgetDock_messageWindow_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\widgetDock_messageWindow_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\widgetDock_messageWindow_1\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\widgetDock_hdlSrc_1\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\widgetDock_hdlSrc_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\widgetDock_hdlSrc_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\widgetDock_hdlSrc_1\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\widgetDock_signalList_1\isVisible=false +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\widgetDock_svtbHier_1\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\widgetDock_svtbHier_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\widgetDock_svtbHier_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\widgetDock_svtbHier_1\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\windowDock_OneSearch_1\isNestedWindow=1 +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\windowDock_OneSearch_1\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\windowDock_OneSearch_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\windowDock_OneSearch_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\windowDock_OneSearch_1\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\windowDock_nWave_1\isNestedWindow=1 +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\windowDock_nWave_1\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\windowDock_nWave_1\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\windowDock_nWave_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\windowDock_nWave_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\windowDock_nWave_1\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\windowDock_nSchema_1\isNestedWindow=1 +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\windowDock_nSchema_1\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\windowDock_nSchema_1\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\windowDock_nSchema_1\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\windowDock_nSchema_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\windowDock_nSchema_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\windowDock_nSchema_1\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\windowDock_nSchema_2\isNestedWindow=1 +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\windowDock_nSchema_2\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\windowDock_nSchema_2\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\windowDock_nSchema_2\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\windowDock_nSchema_2\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\windowDock_nSchema_2\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\windowDock_nSchema_2\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\windowDock_nSchema_3\isNestedWindow=1 +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\windowDock_nSchema_3\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\windowDock_nSchema_3\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\windowDock_nSchema_3\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\windowDock_nSchema_3\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\windowDock_nSchema_3\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\windowDock_nSchema_3\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\ProductVersion=201809 +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\Layout="@ByteArray(\0\0\0\xff\0\0\0\0\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x2\x13\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x3H\0\0\0\x89\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x2\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0h\0\x64\0l\0H\0i\0\x65\0r\0_\0\x31\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0*\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0s\0v\0t\0\x62\0H\0i\0\x65\0r\0_\0\x31\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0s\0i\0g\0n\0\x61\0l\0L\0i\0s\0t\0_\0\x31\0\0\0\0\xe9\0\0\0\xc6\0\0\0k\0\0\0k\xfc\0\0\x3N\0\0\x6\xb2\0\0\0\xbf\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x4\xfb\0\0\0&\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0h\0\x64\0l\0S\0r\0\x63\0_\0\x31\x1\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x31\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x33\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\0\0\0\x3\0\0\n\0\0\0\x2\xd2\xfc\x1\0\0\0\x1\xfc\0\0\0\0\0\0\n\0\0\0\x2,\0\xff\xff\xff\xfa\0\0\0\x2\x1\0\0\0\x3\xfb\0\0\0\x34\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0m\0\x65\0s\0s\0\x61\0g\0\x65\0W\0i\0n\0\x64\0o\0w\0_\0\x31\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0,\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\0_\0\x31\x1\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x31\x1\0\0\0\0\xff\xff\xff\xff\0\0\x1[\0\xff\xff\xff\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x3\x16\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\isNestedWindow=0 +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\size=@Size(2560 1337) +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\geometry_x=-1 +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\geometry_y=27 +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\geometry_width=2560 +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\geometry_height=1337 diff --git a/tb/chip_top/verdiLog/novas_autosave.ses.png b/tb/chip_top/verdiLog/novas_autosave.ses.png new file mode 100644 index 0000000..3548427 Binary files /dev/null and b/tb/chip_top/verdiLog/novas_autosave.ses.png differ diff --git a/tb/chip_top/verdiLog/novas_autosave.ses.wave.0 b/tb/chip_top/verdiLog/novas_autosave.ses.wave.0 new file mode 100644 index 0000000..63ee29d --- /dev/null +++ b/tb/chip_top/verdiLog/novas_autosave.ses.wave.0 @@ -0,0 +1,69 @@ +Magic 271485 +Revision Verdi_O-2018.09-SP2 + +; Window Layout +viewPort 0 27 2560 668 308 65 + +; File list: +; openDirFile [-d delimiter] [-s time_offset] [-rf auto_bus_rule_file] path_name file_name +openDirFile -d / "" "/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/chip_top/verdplus_000.fsdb" + +; file time scale: +; fileTimeScale ### s|ms|us|ns|ps + +; signal spacing: +signalSpacing 5 + +; windowTimeUnit is used for zoom, cursor & marker +windowTimeUnit 1ns + +; waveform viewport range +zoom 0.000000 0.010000 1n +cursor 1570449.000000 +marker 0.000000 + +; user define markers +; userMarker time_pos marker_name color linestyle +userMarker 1570449.755061 M3 ID_GREEN5 long_dashed +userMarker 1530449.110245 M2 ID_GREEN5 long_dashed +userMarker 6120.490729 M1 ID_GREEN5 long_dashed + +; show marker information +; showMarkerValue [absolute|adjacent|relative|frequency] +showMarkerValue absolute +showMarkerValue adjacent + +; visible top row signal index +top 0 +; marker line index +markerPos 3 + +; event list +; addEvent event_name event_expression +; curEvent event_name + + + +COMPLEX_EVENT_BEGIN + + +COMPLEX_EVENT_END + + + +; toolbar current search type +; curSTATUS search_type +curSTATUS ByChange + + +addGroup "G1" +addGroup "G2" +activeDirFile "" "/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/chip_top/verdplus_000.fsdb" +addSignal -w analog -ds pwc -h 98 -2COMP -HEX /TB/U_xyz_chip_top/U_digital_top/U0_channel_top/U_awg_top/U_awg_ctrl/enve_idata_o[15:0] +addSignal -w analog -ds pwc -c ID_PURPLE8 -ls solid -lw 1 -h 98 -UNSIGNED -HEX /TB/cs_wave[15:0] +addGroup "G3" +addGroup "G4" + +; getSignalForm Scope Hierarchy Status +; active file of getSignalForm + diff --git a/tb/chip_top/verdiLog/novas_ones_IC_EDA_111237.log.result b/tb/chip_top/verdiLog/novas_ones_IC_EDA_111237.log.result new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/verdiLog/novas_ones_IC_EDA_74196.log.result b/tb/chip_top/verdiLog/novas_ones_IC_EDA_74196.log.result new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/verdiLog/pes.bat b/tb/chip_top/verdiLog/pes.bat new file mode 100644 index 0000000..7c6e4ac --- /dev/null +++ b/tb/chip_top/verdiLog/pes.bat @@ -0,0 +1,3 @@ +where +detach +quit diff --git a/tb/chip_top/verdiLog/sysinfo.log b/tb/chip_top/verdiLog/sysinfo.log new file mode 100644 index 0000000..01a43bd --- /dev/null +++ b/tb/chip_top/verdiLog/sysinfo.log @@ -0,0 +1,2229 @@ +========== uname -a ========== +Linux IC_EDA 3.10.0-1160.53.1.el7.x86_64 #1 SMP Fri Jan 14 13:59:45 UTC 2022 x86_64 x86_64 x86_64 GNU/Linux +------------- end(uname -a) ------------- + +========== limit ========== +cputime unlimited +filesize unlimited +datasize unlimited +stacksize 8192 kbytes +coredumpsize 0 kbytes +memoryuse unlimited +vmemoryuse unlimited +descriptors 4096 +memorylocked 64 kbytes +maxproc 4096 +maxlocks unlimited +maxsignal 39142 +maxmessage 819200 +maxnice 0 +maxrtprio 0 +maxrttime unlimited +------------- end(limit) ------------- +========== xdpyinfo ========== +name of display: :0 +version number: 11.0 +vendor string: The X.Org Foundation +vendor release number: 12004000 +X.Org version: 1.20.4 +maximum request size: 16777212 bytes +motion buffer size: 256 +bitmap unit, bit order, padding: 32, LSBFirst, 32 +image byte order: LSBFirst +number of supported pixmap formats: 7 +supported pixmap formats: + depth 1, bits_per_pixel 1, scanline_pad 32 + depth 4, bits_per_pixel 8, scanline_pad 32 + depth 8, bits_per_pixel 8, scanline_pad 32 + depth 15, bits_per_pixel 16, scanline_pad 32 + depth 16, bits_per_pixel 16, scanline_pad 32 + depth 24, bits_per_pixel 32, scanline_pad 32 + depth 32, bits_per_pixel 32, scanline_pad 32 +keycode range: minimum 8, maximum 255 +focus: window 0x2e006f9, revert to Parent +number of extensions: 28 + BIG-REQUESTS + Composite + DAMAGE + DOUBLE-BUFFER + DPMS + DRI2 + GLX + Generic Event Extension + MIT-SCREEN-SAVER + MIT-SHM + Present + RANDR + RECORD + RENDER + SECURITY + SHAPE + SYNC + VMWARE_CTRL + X-Resource + XC-MISC + XFIXES + XFree86-DGA + XFree86-VidModeExtension + XINERAMA + XInputExtension + XKEYBOARD + XTEST + XVideo +default screen number: 0 +number of screens: 1 + +screen #0: + dimensions: 2560x1440 pixels (677x381 millimeters) + resolution: 96x96 dots per inch + depths (7): 24, 1, 4, 8, 15, 16, 32 + root window id: 0x3ad + depth of root window: 24 planes + number of colormaps: minimum 1, maximum 1 + default colormap: 0x20 + default number of colormap cells: 256 + preallocated pixels: black 0, white 16777215 + options: backing-store WHEN MAPPED, save-unders NO + largest cursor: 64x64 + current input event mask: 0xda4033 + KeyPressMask KeyReleaseMask EnterWindowMask + LeaveWindowMask KeymapStateMask StructureNotifyMask + SubstructureNotifyMask SubstructureRedirectMask PropertyChangeMask + ColormapChangeMask + number of visuals: 270 + default visual id: 0x21 + visual: + visual id: 0x21 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x22 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2a1 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2a2 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2a3 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2a4 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2a5 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2a6 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2a7 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2a8 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2a9 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2aa + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2ab + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2ac + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2ad + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2ae + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2af + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2b0 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2b1 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2b2 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2b3 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2b4 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2b5 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2b6 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2b7 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2b8 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2b9 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2ba + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2bb + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2bc + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2bd + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2be + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2bf + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2c0 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2c1 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2c2 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2c3 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2c4 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2c5 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2c6 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2c7 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2c8 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2c9 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2ca + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2cb + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2cc + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2cd + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2ce + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2cf + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2d0 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2d1 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2d2 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2d3 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2d4 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2d5 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2d6 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2d7 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2d8 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2d9 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2da + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2db + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2dc + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2dd + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2de + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2df + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2e0 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2e1 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2e2 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2e3 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2e4 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2e5 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2e6 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2e7 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2e8 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2e9 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2ea + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2eb + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2ec + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2ed + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2ee + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2ef + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2f0 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2f1 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2f2 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2f3 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2f4 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2f5 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2f6 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2f7 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2f8 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2f9 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2fa + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2fb + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2fc + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2fd + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2fe + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2ff + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x300 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x301 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x302 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x303 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x304 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x305 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x306 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x307 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x308 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x309 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x30a + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x30b + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x30c + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x30d + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x30e + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x30f + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x310 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x311 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x312 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x313 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x314 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x315 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x316 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x317 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x318 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x319 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x31a + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x31b + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x31c + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x31d + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x31e + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x31f + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x320 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x321 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x322 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x323 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x324 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x325 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x326 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x327 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x328 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x329 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x32a + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x32b + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x32c + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x32d + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x32e + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x32f + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x330 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x331 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x332 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x333 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x334 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x335 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x336 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x337 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x338 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x339 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x33a + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x33b + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x33c + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x33d + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x33e + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x33f + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x340 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x341 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x342 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x343 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x344 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x345 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x346 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x347 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x348 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x349 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x34a + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x34b + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x34c + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x34d + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x34e + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x34f + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x350 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x351 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x352 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x353 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x354 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x355 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x356 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x357 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x358 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x359 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x35a + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x35b + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x35c + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x35d + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x35e + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x35f + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x360 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x361 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x362 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x363 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x364 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x365 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x366 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x367 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x368 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x369 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x36a + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x36b + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x36c + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x36d + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x36e + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x36f + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x370 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x371 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x372 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x373 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x374 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x375 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x376 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x377 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x378 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x379 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x37a + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x37b + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x37c + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x37d + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x37e + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x37f + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x380 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x381 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x382 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x383 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x384 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x385 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x386 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x387 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x388 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x389 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x38a + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x38b + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x38c + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x38d + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x38e + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x66 + class: TrueColor + depth: 32 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x38f + class: TrueColor + depth: 32 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x390 + class: TrueColor + depth: 32 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x391 + class: TrueColor + depth: 32 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x392 + class: TrueColor + depth: 32 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x393 + class: TrueColor + depth: 32 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x394 + class: TrueColor + depth: 32 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x395 + class: TrueColor + depth: 32 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x396 + class: TrueColor + depth: 32 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x397 + class: TrueColor + depth: 32 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x398 + class: TrueColor + depth: 32 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x399 + class: TrueColor + depth: 32 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x39a + class: TrueColor + depth: 32 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x39b + class: TrueColor + depth: 32 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x39c + class: TrueColor + depth: 32 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x39d + class: TrueColor + depth: 32 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x39e + class: TrueColor + depth: 32 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x39f + class: TrueColor + depth: 32 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x3a0 + class: TrueColor + depth: 32 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x3a1 + class: TrueColor + depth: 32 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x3a2 + class: TrueColor + depth: 32 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x3a3 + class: TrueColor + depth: 32 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x3a4 + class: TrueColor + depth: 32 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x3a5 + class: TrueColor + depth: 32 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x3a6 + class: TrueColor + depth: 32 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x3a7 + class: TrueColor + depth: 32 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x3a8 + class: TrueColor + depth: 32 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x3a9 + class: TrueColor + depth: 32 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x3aa + class: TrueColor + depth: 32 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x3ab + class: TrueColor + depth: 32 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits +------------- end(xdpyinfo) ------------- +========== Environment Variables ========== +LC_PAPER=zh_CN.UTF-8 +XDG_VTNR=1 +DISABLE_LIBRARY_MAP_CHECK=1 +XDG_SESSION_ID=1 +SSH_AGENT_PID=10423 +XLOCALEDIR=/home/synopsys/verdi/Verdi_O-2018.09-SP2/etc/access/locale +DBUS_STARTER_ADDRESS=unix:abstract=/tmp/dbus-DIYqQioq7q,guid=a50f166bc97a0937429a75936639b5b6 +LC_MONETARY=zh_CN.UTF-8 +HOSTNAME=IC_EDA +XKEYSYMDB=/home/synopsys/verdi/Verdi_O-2018.09-SP2/etc/access/XKeysymDB2.1 +SIGNAL_BASE_EXTRACTION=1 +IMSETTINGS_INTEGRATE_DESKTOP=yes +NOVAS_SYNC_MOTIF_DISP= +TERM=xterm-256color +XDG_MENU_PREFIX=gnome- +VTE_VERSION=5204 +SHELL=/bin/bash +HISTSIZE=1000 +MAKEFLAGS= +NOVAS_VERDI_SVTB_ALPHA=1 +NOVAS_WAVE_REDRAW_ALLVC=1 +GNOME_TERMINAL_SCREEN=/org/gnome/Terminal/screen/b3faae4f_07ba_4ce6_b83c_c942094b753b +QUESTASIM_HOME=/home/mentor/questasim +SPS_FONT_PATH=/home/synopsys/verdi/Verdi_O-2018.09-SP2/font +LC_NUMERIC=zh_CN.UTF-8 +QTDIR=/usr/lib/qt-3.3 +SPS_XFONT_PATH=/home/synopsys/verdi/Verdi_O-2018.09-SP2/XFont +QTINC=/usr/lib/qt-3.3/include +LC_ALL=C +IMSETTINGS_MODULE=none +QT_GRAPHICSSYSTEM_CHECKED=1 +USER=ICer +WAVE_REDRAW_ALLVC=1 +PS_HWPC=OFF +LD_LIBRARY_PATH=/home/synopsys/verdi/Verdi_O-2018.09-SP2/platform/LINUXAMD64/bin:/home/synopsys/verdi/Verdi_O-2018.09-SP2/platform/LINUXAMD64/lib/Qt:/home/synopsys/verdi/Verdi_O-2018.09-SP2/platform/LINUXAMD64/lib/tbb:/home/synopsys/verdi/Verdi_O-2018.09-SP2/etc/lib/libstdc++/LINUXAMD64:/home/synopsys/verdi/Verdi_O-2018.09-SP2/share/NPI/lib/LINUXAMD64::/home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/lib/LINUX64:/home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/IUS/LINUX64/boot +LS_COLORS=rs=0:di=38;5;27:ln=38;5;51:mh=44;38;5;15:pi=40;38;5;11:so=38;5;13:do=38;5;5:bd=48;5;232;38;5;11:cd=48;5;232;38;5;3:or=48;5;232;38;5;9:mi=05;48;5;232;38;5;15:su=48;5;196;38;5;15:sg=48;5;11;38;5;16:ca=48;5;196;38;5;226:tw=48;5;10;38;5;16:ow=48;5;10;38;5;21:st=48;5;21;38;5;15:ex=38;5;34:*.tar=38;5;9:*.tgz=38;5;9:*.arc=38;5;9:*.arj=38;5;9:*.taz=38;5;9:*.lha=38;5;9:*.lz4=38;5;9:*.lzh=38;5;9:*.lzma=38;5;9:*.tlz=38;5;9:*.txz=38;5;9:*.tzo=38;5;9:*.t7z=38;5;9:*.zip=38;5;9:*.z=38;5;9:*.Z=38;5;9:*.dz=38;5;9:*.gz=38;5;9:*.lrz=38;5;9:*.lz=38;5;9:*.lzo=38;5;9:*.xz=38;5;9:*.bz2=38;5;9:*.bz=38;5;9:*.tbz=38;5;9:*.tbz2=38;5;9:*.tz=38;5;9:*.deb=38;5;9:*.rpm=38;5;9:*.jar=38;5;9:*.war=38;5;9:*.ear=38;5;9:*.sar=38;5;9:*.rar=38;5;9:*.alz=38;5;9:*.ace=38;5;9:*.zoo=38;5;9:*.cpio=38;5;9:*.7z=38;5;9:*.rz=38;5;9:*.cab=38;5;9:*.jpg=38;5;13:*.jpeg=38;5;13:*.gif=38;5;13:*.bmp=38;5;13:*.pbm=38;5;13:*.pgm=38;5;13:*.ppm=38;5;13:*.tga=38;5;13:*.xbm=38;5;13:*.xpm=38;5;13:*.tif=38;5;13:*.tiff=38;5;13:*.png=38;5;13:*.svg=38;5;13:*.svgz=38;5;13:*.mng=38;5;13:*.pcx=38;5;13:*.mov=38;5;13:*.mpg=38;5;13:*.mpeg=38;5;13:*.m2v=38;5;13:*.mkv=38;5;13:*.webm=38;5;13:*.ogm=38;5;13:*.mp4=38;5;13:*.m4v=38;5;13:*.mp4v=38;5;13:*.vob=38;5;13:*.qt=38;5;13:*.nuv=38;5;13:*.wmv=38;5;13:*.asf=38;5;13:*.rm=38;5;13:*.rmvb=38;5;13:*.flc=38;5;13:*.avi=38;5;13:*.fli=38;5;13:*.flv=38;5;13:*.gl=38;5;13:*.dl=38;5;13:*.xcf=38;5;13:*.xwd=38;5;13:*.yuv=38;5;13:*.cgm=38;5;13:*.emf=38;5;13:*.axv=38;5;13:*.anx=38;5;13:*.ogv=38;5;13:*.ogx=38;5;13:*.aac=38;5;45:*.au=38;5;45:*.flac=38;5;45:*.mid=38;5;45:*.midi=38;5;45:*.mka=38;5;45:*.mp3=38;5;45:*.mpc=38;5;45:*.ogg=38;5;45:*.ra=38;5;45:*.wav=38;5;45:*.axa=38;5;45:*.oga=38;5;45:*.spx=38;5;45:*.xspf=38;5;45: +GNOME_TERMINAL_SERVICE=:1.108 +SIGNAL_BASED_BA=0 +XNLSPATH=/home/synopsys/verdi/Verdi_O-2018.09-SP2/etc/access/nls +TCL_LIBRARY=/home/synopsys/verdi/Verdi_O-2018.09-SP2/etc/access/tcl86_library +MAKE_TERMOUT=/dev/pts/3 +SSH_AUTH_SOCK=/run/user/1000/keyring/ssh +DVE_HOME=/home/synopsys/vcs/O-2018.09-SP2 +MAKELEVEL=1 +SESSION_MANAGER=local/unix:@/tmp/.ICE-unix/10289,unix/unix:/tmp/.ICE-unix/10289 +USERNAME=ICer +SNPSLMD_LICENSE_FILE=27000@IC_EDA +MFLAGS= +NOVAS_SIGNAL_BASED_BA=0 +GNOME_SHELL_SESSION_MODE=classic +NOVAS_TCL_LIBRARY=/home/synopsys/verdi/Verdi_O-2018.09-SP2/etc/access/tcl86_library +NOVAS_VERDI_SVTB_BETA=1 +MAIL=/var/spool/mail/ICer +PATH=/bin:/usr/lib/qt-3.3/bin:/usr/local/bin:/usr/local/sbin:/usr/bin:/usr/sbin:/bin:/sbin:/home/synopsys/pts/O-2018.06-SP1/bin:/home/synopsys/syn/O-2018.06-SP1/bin:/home/synopsys/lc/O-2018.06-SP1/bin:/home/synopsys/SpyGlass-L2016.06/SPYGLASS_HOME//bin:/home/synopsys/vcs/O-2018.09-SP2/gui/dve/bin:/home/synopsys/vcs/O-2018.09-SP2/bin:/home/synopsys/verdi/Verdi_O-2018.09-SP2/bin:/home/synopsys/verdi/Verdi_O-2018.09-SP2/platform/LINUX/bin:/home/synopsys/scl/2018.06/linux64/bin::/home/mentor/questasim/linux_x86_64:/home/Riscv_Tools/bin:/home/Riscv_Tools/riscv-gnu-toolchain/qemu-6.0.0/build/riscv32-linux-user +DESKTOP_SESSION=gnome-classic +PT_HOME=/home/synopsys/pts/O-2018.06-SP1 +QT_IM_MODULE=ibus +VERDI_HOME=/home/synopsys/verdi/Verdi_O-2018.09-SP2 +PWD=/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/digital_top +XDG_SESSION_TYPE=x11 +VCS_HOME=/home/synopsys/vcs/O-2018.09-SP2 +XMODIFIERS=@im=none +LANG=C +SYS_PROG_NAME=verdi +GDM_LANG=zh_CN.UTF-8 +SYNOPSYS_SIM=/home/synopsys/vcs/O-2018.09-SP2 +VERDI_TB_HT=1 +LC_MEASUREMENT=zh_CN.UTF-8 +VCS_ARCH_OVERRIDE=linux +KDEDIRS=/usr +QEMU_HOME=/home/Riscv_Tools/riscv-gnu-toolchain/qemu-6.0.0 +GDMSESSION=gnome-classic +SYS_INST_DIR=/home/synopsys/verdi/Verdi_O-2018.09-SP2 +HISTCONTROL=ignoredups +DBUS_STARTER_BUS_TYPE=session +SHLVL=5 +RISCV=/home/Riscv_Tools +XDG_SEAT=seat0 +HOME=/home/ICer +GNOME_DESKTOP_SESSION_ID=this-is-deprecated +VERDI_ORIGNAL_LD_LIBRARY_PATH=:/home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/lib/LINUX64:/home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/IUS/LINUX64/boot +VERDI_SVTB_ALPHA=1 +DC_HOME=/home/synopsys/syn/O-2018.06-SP1 +LOGNAME=ICer +XDG_SESSION_DESKTOP=gnome-classic +MAKE_TERMERR=/dev/pts/3 +SPYGLASS_HOME=/home/synopsys/SpyGlass-L2016.06/SPYGLASS_HOME/ +QTLIB=/usr/lib/qt-3.3/lib +MGLS_LICENSE_FILE=/home/mentor/questasim/mentor.dat +VERDI_SVTB_BETA=1 +DBUS_SESSION_BUS_ADDRESS=unix:abstract=/tmp/dbus-DIYqQioq7q,guid=a50f166bc97a0937429a75936639b5b6 +XDG_DATA_DIRS=/home/ICer/.local/share/flatpak/exports/share/:/var/lib/flatpak/exports/share/:/usr/local/share/:/usr/share/ +SPS_RGB_PATH=/home/synopsys/verdi/Verdi_O-2018.09-SP2/etc/rgb +NOVASHLPPATH=/home/synopsys/verdi/Verdi_O-2018.09-SP2/doc +NOVAS_LC_ALL=C +LESSOPEN=||/usr/bin/lesspipe.sh %s +SCL_HOME=/home/synopsys/scl/2018.06 +WINDOWPATH=1 +DISPLAY=:0 +XDG_RUNTIME_DIR=/run/user/1000 +LD_NOVERSION=1 +LC_HOME=/home/synopsys/lc/O-2018.06-SP1 +QT_PLUGIN_PATH=/home/synopsys/verdi/Verdi_O-2018.09-SP2/platform/LINUXAMD64/lib/Qt/plugins +NOVAS_SIGNAL_BASE_EXTRACTION=1 +XDG_CURRENT_DESKTOP=GNOME-Classic:GNOME +LC_TIME=zh_CN.UTF-8 +NOVAS_VERDI_TB_HT=1 +COLORTERM=truecolor +XAUTHORITY=/run/gdm/auth-for-ICer-FQtMgs/database +_=/home/synopsys/verdi/Verdi_O-2018.09-SP2/etc/access/sysinfo.sh +HOSTTYPE=x86_64-linux +VENDOR=unknown +OSTYPE=linux +MACHTYPE=x86_64 +GROUP=ICer +HOST=IC_EDA +------------- end(env) ------------- +========== ps ========== + PID TTY TIME CMD + 22848 pts/3 00:00:00 bash + 74015 pts/3 00:00:00 sysinfo.sh + 74029 pts/3 00:00:00 ps + 86437 pts/3 00:00:00 make + 87088 pts/3 00:02:10 simv + 91158 pts/3 00:04:37 Novas +------------- end(ps) ------------- +========== cat /proc/meminfo ========== +MemTotal: 10054436 kB +MemFree: 2888288 kB +MemAvailable: 6919124 kB +Buffers: 2152 kB +Cached: 4349736 kB +SwapCached: 0 kB +Active: 4558976 kB +Inactive: 1730636 kB +Active(anon): 1939208 kB +Inactive(anon): 262608 kB +Active(file): 2619768 kB +Inactive(file): 1468028 kB +Unevictable: 0 kB +Mlocked: 0 kB +SwapTotal: 10481660 kB +SwapFree: 10481660 kB +Dirty: 12 kB +Writeback: 0 kB +AnonPages: 1938352 kB +Mapped: 529440 kB +Shmem: 263904 kB +Slab: 390328 kB +SReclaimable: 256964 kB +SUnreclaim: 133364 kB +KernelStack: 12016 kB +PageTables: 45816 kB +NFS_Unstable: 0 kB +Bounce: 0 kB +WritebackTmp: 0 kB +CommitLimit: 15508876 kB +Committed_AS: 6368600 kB +VmallocTotal: 34359738367 kB +VmallocUsed: 243676 kB +VmallocChunk: 34359277564 kB +Percpu: 56320 kB +HardwareCorrupted: 0 kB +AnonHugePages: 1312768 kB +CmaTotal: 0 kB +CmaFree: 0 kB +HugePages_Total: 0 +HugePages_Free: 0 +HugePages_Rsvd: 0 +HugePages_Surp: 0 +Hugepagesize: 2048 kB +DirectMap4k: 159552 kB +DirectMap2M: 6131712 kB +DirectMap1G: 6291456 kB +------------- end(cat /proc/meminfo) ------------- +========== show OS patch level ========== +\S +Kernel \r on an \m + +------------- end(show OS patch level) ------------- +========= uptime ========== + 17:28:00 up 8 days, 30 min, 4 users, load average: 1.00, 1.01, 0.96 +------------ end(uptime) ------------- +========= locale ========== +LANG=C +LC_CTYPE="C" +LC_NUMERIC="C" +LC_TIME="C" +LC_COLLATE="C" +LC_MONETARY="C" +LC_MESSAGES="C" +LC_PAPER="C" +LC_NAME="C" +LC_ADDRESS="C" +LC_TELEPHONE="C" +LC_MEASUREMENT="C" +LC_IDENTIFICATION="C" +LC_ALL=C +------------ end(locale) ------------- +========== ldd ========== +ldd /home/synopsys/verdi/Verdi_O-2018.09-SP2/platform/LINUXAMD64/bin/Novas + linux-vdso.so.1 => (0x00007fff2b1d9000) + libdl.so.2 => /lib64/libdl.so.2 (0x00007f95c5319000) + libvfs.so => /home/synopsys/verdi/Verdi_O-2018.09-SP2/platform/LINUXAMD64/bin/libvfs.so (0x00007f95c500c000) + libfreetype.so.6 => /lib64/libfreetype.so.6 (0x00007f95c4d4d000) + libQtSolutions_MotifExtension-2.7.so.1 => /home/synopsys/verdi/Verdi_O-2018.09-SP2/platform/LINUXAMD64/lib/Qt/libQtSolutions_MotifExtension-2.7.so.1 (0x00007f95c4b37000) + libQtGui.so.4 => /home/synopsys/verdi/Verdi_O-2018.09-SP2/platform/LINUXAMD64/lib/Qt/libQtGui.so.4 (0x00007f95c3f93000) + libQtCore.so.4 => /home/synopsys/verdi/Verdi_O-2018.09-SP2/platform/LINUXAMD64/lib/Qt/libQtCore.so.4 (0x00007f95c3afa000) + libQtXml.so.4 => /home/synopsys/verdi/Verdi_O-2018.09-SP2/platform/LINUXAMD64/lib/Qt/libQtXml.so.4 (0x00007f95c38c0000) + libQtWebKit.so.4 => /home/synopsys/verdi/Verdi_O-2018.09-SP2/platform/LINUXAMD64/lib/Qt/libQtWebKit.so.4 (0x00007f95c1faf000) + libQtNetwork.so.4 => /home/synopsys/verdi/Verdi_O-2018.09-SP2/platform/LINUXAMD64/lib/Qt/libQtNetwork.so.4 (0x00007f95c1ca1000) + libQt3Support.so.4 => /home/synopsys/verdi/Verdi_O-2018.09-SP2/platform/LINUXAMD64/lib/Qt/libQt3Support.so.4 (0x00007f95c1801000) + libQtSql.so.4 => /home/synopsys/verdi/Verdi_O-2018.09-SP2/platform/LINUXAMD64/lib/Qt/libQtSql.so.4 (0x00007f95c15cb000) + libsimprofile_verdi.so => /home/synopsys/verdi/Verdi_O-2018.09-SP2/platform/LINUXAMD64/bin/libsimprofile_verdi.so (0x00007f95c1213000) + libstdc++.so.6 => /home/synopsys/verdi/Verdi_O-2018.09-SP2/etc/lib/libstdc++/LINUXAMD64/libstdc++.so.6 (0x00007f95c0e92000) + libtbb.so.2 => /home/synopsys/verdi/Verdi_O-2018.09-SP2/platform/LINUXAMD64/bin/libtbb.so.2 (0x00007f95c55cd000) + libXss.so.1 => /lib64/libXss.so.1 (0x00007f95c0c8e000) + libXft.so.2 => /lib64/libXft.so.2 (0x00007f95c0a78000) + libXt.so.6 => /lib64/libXt.so.6 (0x00007f95c0811000) + libXmu.so.6 => /lib64/libXmu.so.6 (0x00007f95c05f6000) + libX11.so.6 => /lib64/libX11.so.6 (0x00007f95c02b8000) + libXext.so.6 => /lib64/libXext.so.6 (0x00007f95c00a6000) + libfontconfig.so.1 => /lib64/libfontconfig.so.1 (0x00007f95bfe64000) + libnsl.so.1 => /lib64/libnsl.so.1 (0x00007f95bfc4a000) + libnuma.so.1 => /lib64/libnuma.so.1 (0x00007f95bfa3e000) + libpthread.so.0 => /lib64/libpthread.so.0 (0x00007f95bf822000) + librt.so.1 => /lib64/librt.so.1 (0x00007f95bf61a000) + libpng12.so.0 => /lib64/libpng12.so.0 (0x00007f95bf3f3000) + libm.so.6 => /lib64/libm.so.6 (0x00007f95bf0f1000) + libc.so.6 => /lib64/libc.so.6 (0x00007f95bed23000) + /lib64/ld-linux-x86-64.so.2 (0x00007f95c551d000) + libz.so.1 => /lib64/libz.so.1 (0x00007f95beb0d000) + libbz2.so.1 => /lib64/libbz2.so.1 (0x00007f95be8fd000) + libpng15.so.15 => /lib64/libpng15.so.15 (0x00007f95be6d2000) + libSM.so.6 => /lib64/libSM.so.6 (0x00007f95be4ca000) + libICE.so.6 => /lib64/libICE.so.6 (0x00007f95be2ae000) + libgcc_s.so.1 => /home/synopsys/verdi/Verdi_O-2018.09-SP2/etc/lib/libstdc++/LINUXAMD64/libgcc_s.so.1 (0x00007f95be098000) + libXrender.so.1 => /lib64/libXrender.so.1 (0x00007f95bde8d000) + libxcb.so.1 => /lib64/libxcb.so.1 (0x00007f95bdc65000) + libexpat.so.1 => /lib64/libexpat.so.1 (0x00007f95bda3b000) + libuuid.so.1 => /lib64/libuuid.so.1 (0x00007f95bd836000) + libXau.so.6 => /lib64/libXau.so.6 (0x00007f95bd632000) +------------- end(ldd) ------------- diff --git a/tb/chip_top/verdiLog/sysinfo_May15_1728.tar b/tb/chip_top/verdiLog/sysinfo_May15_1728.tar new file mode 100644 index 0000000..cb47e80 Binary files /dev/null and b/tb/chip_top/verdiLog/sysinfo_May15_1728.tar differ diff --git a/tb/chip_top/verdiLog/tdc.list.oneSearch b/tb/chip_top/verdiLog/tdc.list.oneSearch new file mode 100644 index 0000000..59b8f12 --- /dev/null +++ b/tb/chip_top/verdiLog/tdc.list.oneSearch @@ -0,0 +1,130 @@ +../../rtl/memory/tsmc_dpram.v +../../rtl/top/z_data_mux.v +../../rtl/xy_dsp/duc/duc_hb1_top.v +qbmcu_undefines.v +qbmcu_defines.v +qbmcu_defines.v +../../rtl/top/xyz_chip_top.v +chip_define.v +../../rtl/modem/ampmod.v +../../rtl/xy_dsp/duc/duc_hb3_pipe_shift.v +qbmcu_undefines.v +../../rtl/nco/pipe_acc_48bit.v +../../rtl/rstgen/rst_sync.v +../../rtl/rstgen/rst_gen_unit.v +qbmcu_defines.v +../../sim/chip_top/clk_gen.v +../../rtl/spi/spi_bus_decoder.sv +../define/chip_define.v +../define/chip_undefine.v +../../rtl/define/chip_undefine.v +../../rtl/clk/intpll_regfile.v +../../rtl/qubitmcu/qbmcu_undefines.v +../../rtl/dac_regfile/dac_regfile.v +../../rtl/spi/spi_pll.v +../../rtl/xy_dsp/duc/duc_hb4_top_s3.v +../../rtl/perips/DW03_updn_ctr.v +../../rtl/modem/baisset.v +../../sim/chip_top/spi_if.sv +../../rtl/xy_dsp/qam/qam_top.v +../../rtl/xy_dsp/duc/duc_hb2_pipe_shift.v +../../rtl/memory/tsdn28hpcpuhdb128x128m4mw_170a_ffg0p99v0c.v +../../rtl/qubitmcu/qbmcu_ifu.v +../../rtl/nco/sin_op.v +../../rtl/awg/ctrl_regfile.v +../define/chip_define.v +../../rtl/xy_dsp/duc/duc_hb3_top_s2.v +../../rtl/system_regfile/system_regfile.v +../../rtl/qubitmcu/qbmcu_regfile.v +../../rtl/qubitmcu/qbmcu_fsm.v +qbmcu_defines.v +../qubitmcu/qbmcu_undefines.v +../../rtl/dem/DAC_DEM.v +../../rtl/nco/nco_ch1.v +../../rtl/top/channel_top.sv +../../rtl/memory/tsdn28hpcpuhdb4096x32m4mw_170a_ffg0p99v0c.v +../../rtl/dem/DAC_DEM_16.v +../../rtl/xy_dsp/dacif/dacif.v +../../rtl/qubitmcu/qbmcu_exu_alu.v +qbmcu_defines.v +../../rtl/qubitmcu/qbmcu_decode.v +../../rtl/modem/freqmod.v +../define/chip_undefine.v +../../rtl/nco/p_nco.v +../../rtl/qubitmcu/qbmcu_exu_ext.v +../define/chip_define.v +../../rtl/spi/spi_slave.v +qbmcu_defines.v +../../rtl/qubitmcu/qbmcu_exu.v +qbmcu_defines.v +../../rtl/qubitmcu/qbmcu.v +../define/chip_define.v +../define/chip_undefine.v +../../rtl/memory/dpram.v +../../sim/chip_top/DW02_mult.v +../../rtl/xy_dsp/duc/duc_hb1_pipe_shift.v +../../rtl/nco/p_nco_ch1.v +../../sim/chip_top/DW01_addsub.v +qbmcu_defines.v +../../rtl/memory/dpram_model.v +../../sim/chip_top/DW_mult_pipe.v +../../rtl/top/digital_top.sv +../../rtl/spi/spi_sys.v +../../rtl/debug/debug_top.sv +../../rtl/awg/awg_top.sv +../../rtl/xy_dsp/duc/duc4.v +../../rtl/xy_dsp/duc/duc_hb2_top_s.v +qbmcu_defines.v +../qubitmcu/qbmcu_defines.v +qbmcu_undefines.v +../../rtl/nco/pipe_add_48bit.v +../../rtl/awg/param_lut.sv +../../rtl/awg/codeword_decode.v +../../rtl/xy_dsp/qam/ssb.v +../../rtl/perips/mcu_regfile.sv +../../rtl/comm/sirv_gnrl_dffs.v +../../rtl/debug/debug_sample.sv +../../rtl/xy_dsp/dsp_top/xy_dsp.v +../../rtl/qubitmcu/qbmcu_exu_bjp.v +../../rtl/nco/ph2amp.v +../../sim/chip_top/thermo2binary_top.v +../../rtl/awg/awg_ctrl.v +../qubitmcu/qbmcu_defines.v +qbmcu_undefines.v +qbmcu_undefines.v +../../rtl/dem/DAC_DEM_4.v +../../rtl/memory/sram_dmux.sv +../qubitmcu/qbmcu_undefines.v +../../rtl/qubitmcu/qbmcu_wbck.v +../../rtl/memory/sram_if.sv +qbmcu_undefines.v +qbmcu_undefines.v +../../rtl/comm/sirv_gnrl_xchecker.v +qbmcu_defines.v +../../rtl/nco/coef_s.v +../../rtl/define/chip_define.v +../../rtl/qubitmcu/qbmcu_datalock.v +qbmcu_undefines.v +qbmcu_undefines.v +qbmcu_defines.v +../../rtl/awg/modout_mux.v +../../rtl/xy_dsp/duc/duc_hb4_pipe_shift.v +../../rtl/perips/qbmcu_busdecoder.v +../../rtl/nco/coef_c.v +chip_undefine.v +qbmcu_undefines.v +../../rtl/qubitmcu/qbmcu_exu_dpath.v +qbmcu_undefines.v +../../sim/chip_top/thermo15_binary4.v +qbmcu_defines.v +../../rtl/nco/cos_op.v +../../sim/chip_top/thermo7_binary3.v +../../sim/chip_top/TB.sv +../../rtl/qubitmcu/qbmcu_defines.v +../../rtl/nco/nco.v +../../rtl/memory/tsdn28hpcpuhdb64x32m4mw_170a_ffg0p99v0c.v +qbmcu_undefines.v +../../rtl/qubitmcu/qbmcu_exu_lsuagu.v +qbmcu_defines.v +../../rtl/sync/sync_buf.sv +qbmcu_undefines.v diff --git a/tb/chip_top/verdiLog/turbo.log b/tb/chip_top/verdiLog/turbo.log new file mode 100644 index 0000000..96a4d3e --- /dev/null +++ b/tb/chip_top/verdiLog/turbo.log @@ -0,0 +1,2 @@ +Command Line: /home/synopsys/verdi/Verdi_O-2018.09-SP2/platform/LINUXAMD64/bin/Novas -sverilog -f files.f -top TB -nologo +uname(Linux IC_EDA 3.10.0-1160.53.1.el7.x86_64 #1 SMP Fri Jan 14 13:59:45 UTC 2022 x86_64) diff --git a/tb/chip_top/verdiLog/verdi.cmd b/tb/chip_top/verdiLog/verdi.cmd new file mode 100644 index 0000000..a5b264a --- /dev/null +++ b/tb/chip_top/verdiLog/verdi.cmd @@ -0,0 +1,1622 @@ +sidCmdLineBehaviorAnalysisOpt -incr -clockSkew 0 -loopUnroll 0 -bboxEmptyModule 0 -cellModel 0 -bboxIgnoreProtected 0 +debImport "-sverilog" "-f" "files.f" "-top" "TB" +wvCreateWindow +wvSetPosition -win $_nWave2 {("G1" 0)} +wvOpenFile -win $_nWave2 \ + {/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/chip_top/verdplus_000.fsdb} +srcDeselectAll -win $_nTrace1 +srcSelect -signal "cs_wave" -line 1238 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvBusWaveform -win $_nWave2 -analog +wvSetPosition -win $_nWave2 {("G1" 1)} +wvZoom -win $_nWave2 1447601201.591856 1699097584.081444 +wvZoom -win $_nWave2 1520222091.305717 1612161999.758644 +wvZoom -win $_nWave2 1529284192.415816 1576807041.903053 +wvSetCursor -win $_nWave2 1530405740.459354 -snap {("G1" 1)} +wvSetWindowTimeUnit -win $_nWave2 1.000000 us +wvSetCursor -win $_nWave2 1570.473594 -snap {("G1" 1)} +wvSetCursor -win $_nWave2 1530.449723 -snap {("G1" 1)} +wvSetCursor -win $_nWave2 1570.473594 -snap {("G1" 1)} +wvSetCursor -win $_nWave2 1530.449723 -snap {("G1" 1)} +wvSetCursor -win $_nWave2 1570.451603 -snap {("G1" 1)} +wvSetCursor -win $_nWave2 1530.427732 -snap {("G1" 1)} +wvSetCursor -win $_nWave2 1570.429612 -snap {("G1" 1)} +wvSetCursor -win $_nWave2 1530.361758 -snap {("G1" 1)} +wvSetWindowTimeUnit -win $_nWave2 32.000000 ns +wvSetCursor -win $_nWave2 47826.553836 -snap {("G1" 1)} +wvSetCursor -win $_nWave2 49077.987039 -snap {("G1" 1)} +wvSetCursor -win $_nWave2 47825.179389 -snap {("G1" 1)} +verdiDockWidgetMaximize -dock windowDock_nWave_2 +verdiDockWidgetRestore -dock windowDock_nWave_2 +srcHBSelect "TB.U_xyz_chip_top.U0_DAC_DEM_16" -win $_nTrace1 +srcHBSelect "TB.U_xyz_chip_top.U_digital_top" -win $_nTrace1 +srcHBSelect "TB.U_xyz_chip_top.U_digital_top.U0_channel_top.U_awg_top" -win \ + $_nTrace1 +srcHBSelect "TB.U_xyz_chip_top.U_digital_top.U0_channel_top.U_awg_top.U_awg_ctrl" \ + -win $_nTrace1 +srcSetScope -win $_nTrace1 \ + "TB.U_xyz_chip_top.U_digital_top.U0_channel_top.U_awg_top.U_awg_ctrl" \ + -delim "." +srcHBSelect "TB.U_xyz_chip_top.U_digital_top.U0_channel_top.U_awg_top.U_awg_ctrl" \ + -win $_nTrace1 +srcSelect -signal "enve_vld_o" -line 99 -pos 1 -win $_nTrace1 +srcSelect -signal "enve_qdata_o" -line 98 -pos 1 -win $_nTrace1 +srcSelect -signal "enve_idata_o" -line 97 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 0 +wvSelectSignal -win $_nWave2 {( "G1" 4 )} +wvSelectSignal -win $_nWave2 {( "G1" 3 )} +wvCut -win $_nWave2 +wvSetPosition -win $_nWave2 {("G2" 0)} +wvSetPosition -win $_nWave2 {("G1" 3)} +wvSelectSignal -win $_nWave2 {( "G1" 3 )} +wvBusWaveform -win $_nWave2 -analog +wvSetPosition -win $_nWave2 {("G1" 3)} +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 0 +wvZoomOut -win $_nWave2 +wvScrollUp -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvSetRadix -win $_nWave2 -2Com +wvSetCursor -win $_nWave2 48012.447675 -snap {("G1" 3)} +wvSetCursor -win $_nWave2 47765.047371 -snap {("G1" 3)} +wvSetCursor -win $_nWave2 49015.793352 -snap {("G1" 3)} +wvSetCursor -win $_nWave2 47767.796263 -snap {("G1" 2)} +wvSetCursor -win $_nWave2 49015.793352 -snap {("G1" 2)} +wvSetCursor -win $_nWave2 47767.796263 -snap {("G1" 3)} +srcDeselectAll -win $_nTrace1 +srcSelect -signal "clk" -line 85 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +wvZoom -win $_nWave2 47657.840573 47875.003062 +wvZoom -win $_nWave2 47701.152480 47713.311972 +wvSetCursor -win $_nWave2 47703.470718 -snap {("G1" 4)} +wvSetCursor -win $_nWave2 47704.472286 -snap {("G1" 4)} +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "enve_len_i" -line 90 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "enve_index_vld_i" -line 88 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +wvSelectSignal -win $_nWave2 {( "G1" 5 )} +wvSelectSignal -win $_nWave2 {( "G1" 5 6 )} +wvSelectSignal -win $_nWave2 {( "G1" 6 )} +wvCut -win $_nWave2 +wvSetPosition -win $_nWave2 {("G2" 0)} +wvSetPosition -win $_nWave2 {("G1" 5)} +wvSelectSignal -win $_nWave2 {( "G1" 5 )} +wvCut -win $_nWave2 +wvSetPosition -win $_nWave2 {("G2" 0)} +wvSetPosition -win $_nWave2 {("G1" 4)} +wvSetCursor -win $_nWave2 47927.622307 -snap {("G1" 1)} +wvSetCursor -win $_nWave2 47783.576502 -snap {("G1" 1)} +wvSetCursor -win $_nWave2 47812.385663 -snap {("G1" 3)} +wvSetCursor -win $_nWave2 44891.136755 -snap {("G1" 3)} +wvSelectSignal -win $_nWave2 {( "G1" 1 )} +wvSelectSignal -win $_nWave2 {( "G1" 2 )} +wvZoom -win $_nWave2 47792.219251 47996.764293 +wvZoom -win $_nWave2 47824.779868 47841.154830 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomIn -win $_nWave2 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "muc_mod_nco_rz_pha_i" -line 108 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 48091.198140 57400.681048 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "muc_mod_nco_rz_pha_i" -line 108 -pos 1 -win $_nTrace1 +srcAction -pos 107 10 9 -win $_nTrace1 -name "muc_mod_nco_rz_pha_i" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -signal "lcpr" -line 781 -pos 1 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "lcpr" -line 781 -pos 1 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "lcpr" -line 781 -pos 1 -win $_nTrace1 +srcAction -pos 780 6 1 -win $_nTrace1 -name "lcpr" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -signal "dnxt" -line 107 -pos 1 -win $_nTrace1 +srcAction -pos 106 12 1 -win $_nTrace1 -name "dnxt" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -signal "lcprwe" -line 557 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +wvSetCursor -win $_nWave2 49258.652961 -snap {("G1" 4)} +wvZoom -win $_nWave2 49107.874663 49267.268863 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 49032.971928 49184.031309 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "wrdata\[23:16\]" -line 556 -pos 1 -win $_nTrace1 +debReload +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 47666.831709 49221.464117 +wvZoomOut -win $_nWave2 +wvSetWindowTimeUnit -win $_nWave2 8.000000 ns +wvSetCursor -win $_nWave2 191074.509596 -snap {("G1" 2)} +wvSetCursor -win $_nWave2 196064.296908 -snap {("G1" 2)} +wvSelectSignal -win $_nWave2 {( "G1" 4 )} +wvCut -win $_nWave2 +wvSetPosition -win $_nWave2 {("G2" 0)} +wvSetPosition -win $_nWave2 {("G1" 5)} +wvSelectSignal -win $_nWave2 {( "G1" 4 )} +wvCut -win $_nWave2 +wvSetPosition -win $_nWave2 {("G2" 0)} +wvSetPosition -win $_nWave2 {("G1" 4)} +wvSelectSignal -win $_nWave2 {( "G1" 4 )} +wvCut -win $_nWave2 +wvSetPosition -win $_nWave2 {("G2" 0)} +wvSetPosition -win $_nWave2 {("G1" 3)} +wvSetCursor -win $_nWave2 191080.264830 -snap {("G1" 2)} +wvSelectSignal -win $_nWave2 {( "G1" 2 )} +wvSetMarker -win $_nWave2 -keepViewRange -name "M1" 191068.754363 +wvSetMarker -win $_nWave2 -keepViewRange -name "M1" 191068.754363 +wvSetCursor -win $_nWave2 196058.541675 -snap {("G1" 3)} +wvSelectSignal -win $_nWave2 {( "G1" 3 )} +wvSetMarker -win $_nWave2 -keepViewRange -name "M2" 196070.052142 +wvSetMarker -win $_nWave2 -keepViewRange -name "M2" 196070.052142 +wvSelectGroup -win $_nWave2 {G2} +wvSetCursor -win $_nWave2 191062.999130 -snap {("G2" 0)} +wvSetCursor -win $_nWave2 191091.775297 -snap {("G1" 3)} +wvSetCursor -win $_nWave2 191057.243896 -snap {("G1" 3)} +wvSetMarkerOption -win $_nWave2 -refmarker "M1" +wvSelectSignal -win $_nWave2 {( "G1" 3 )} +wvSelectGroup -win $_nWave2 {G2} +wvSetMarkerOption -win $_nWave2 -frequency on +wvSelectSignal -win $_nWave2 {( "G1" 3 )} +wvSelectGroup -win $_nWave2 {G2} +wvSetMarkerOption -win $_nWave2 -relative on +wvSetMarkerOption -win $_nWave2 -frequency off +wvSetMarkerOption -win $_nWave2 -adjacent on +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 190706.174662 191477.375931 +wvZoom -win $_nWave2 191047.701554 191124.429122 +wvSelectUserMarker -win $_nWave2 -name "M1" +wvSetMarker -win $_nWave2 -keepViewRange -name "M1" 191069.928050 +wvZoomIn -win $_nWave2 +wvZoom -win $_nWave2 191068.854006 191072.120520 +wvSelectUserMarker -win $_nWave2 -name "M1" +wvSetMarker -win $_nWave2 -keepViewRange -name "M1" 191069.996757 +wvSelectUserMarker -win $_nWave2 -name "M1" +wvSelectUserMarker -win $_nWave2 -name "M1" +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 191069.958589 191070.117305 +wvZoom -win $_nWave2 191069.988849 191070.019402 +wvSelectUserMarker -win $_nWave2 -name "M1" +wvSetMarker -win $_nWave2 -keepViewRange -name "M1" 191069.999976 +wvZoom -win $_nWave2 191069.998732 191070.001460 +wvSelectUserMarker -win $_nWave2 -name "M1" +wvSetMarker -win $_nWave2 -keepViewRange -name "M1" 191069.999999 +wvZoom -win $_nWave2 191069.999903 191070.000191 +wvZoom -win $_nWave2 191069.999989 191070.000028 +wvSelectUserMarker -win $_nWave2 -name "M1" +wvSetMarker -win $_nWave2 -keepViewRange -name "M1" 191070.000000 +wvSelectUserMarker -win $_nWave2 -name "M1" +wvSelectUserMarker -win $_nWave2 -name "M1" +wvZoom -win $_nWave2 191069.999995 191070.000007 +wvZoom -win $_nWave2 191069.999998 191070.000007 +wvZoom -win $_nWave2 191069.999998 191070.000023 +wvSelectUserMarker -win $_nWave2 -name "M1" +wvSelectUserMarker -win $_nWave2 -name "M1" +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 194951.817470 200044.761912 +wvZoom -win $_nWave2 195974.648515 196311.664274 +wvZoom -win $_nWave2 196057.303930 196093.485168 +wvZoom -win $_nWave2 196068.036079 196073.192868 +wvZoom -win $_nWave2 196069.749441 196070.672938 +wvSelectUserMarker -win $_nWave2 -name "M2" +wvSetMarker -win $_nWave2 -keepViewRange -name "M2" 196069.999011 +wvSelectUserMarker -win $_nWave2 -name "M2" +wvSetMarker -win $_nWave2 -keepViewRange -name "M2" 196069.999011 +wvSelectUserMarker -win $_nWave2 -name "M2" +wvSelectUserMarker -win $_nWave2 -name "M2" +wvSelectUserMarker -win $_nWave2 -name "M2" +wvSetMarker -win $_nWave2 -keepViewRange -name "M2" 196070.001148 +wvSelectUserMarker -win $_nWave2 -name "M2" +wvSelectUserMarker -win $_nWave2 -name "M2" +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 196068.330434 196072.706469 +wvZoom -win $_nWave2 196069.853238 196070.152938 +wvSetCursor -win $_nWave2 196070.001354 -snap {("G1" 1)} +wvSetCursor -win $_nWave2 196070.000938 -snap {("G1" 1)} +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvSetCursor -win $_nWave2 196070.123190 -snap {("G1" 1)} +wvSetCursor -win $_nWave2 196070.000037 -snap {("G1" 1)} +wvSearchPrev -win $_nWave2 +wvSearchPrev -win $_nWave2 +wvSearchNext -win $_nWave2 +wvSelectSignal -win $_nWave2 {( "G1" 3 )} +wvSetMarker -win $_nWave2 -keepViewRange -name "M2" 196070.000037 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 190007.685128 197169.763917 +wvZoom -win $_nWave2 190919.101910 191475.894708 +wvZoom -win $_nWave2 191037.623283 191132.955692 +wvZoom -win $_nWave2 191065.018668 191076.135635 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 191069.604867 191070.952690 +wvZoom -win $_nWave2 191069.924203 191070.160586 +wvSetCursor -win $_nWave2 191069.999789 -snap {("G1" 3)} +wvSetMarker -win $_nWave2 -keepViewRange -name "M1" 191070.000000 ID_GREEN5 \ + long_dashed +wvSetMarker -win $_nWave2 -keepViewRange -name "M1" 191070.000000 ID_GREEN5 \ + long_dashed +wvJumpUserMarker -win $_nWave2 -name "M1" +wvSetMarker -win $_nWave2 -keepViewRange -name "M1" 191070.000000 ID_GREEN5 \ + long_dashed +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 187270.570930 205163.731228 +wvZoom -win $_nWave2 195931.489797 197032.734739 +wvZoom -win $_nWave2 196055.832122 196135.839275 +wvZoom -win $_nWave2 196068.420013 196074.491819 +wvZoom -win $_nWave2 196069.684387 196070.353101 +wvZoom -win $_nWave2 196069.992286 196070.022303 +wvZoom -win $_nWave2 196069.999592 196070.001690 +wvZoom -win $_nWave2 196069.999932 196070.000221 +wvSelectUserMarker -win $_nWave2 -name "M2" +wvSetMarker -win $_nWave2 -keepViewRange -name "M2" 196070.000035 +wvSelectUserMarker -win $_nWave2 -name "M2" +wvSetMarker -win $_nWave2 -keepViewRange -name "M2" 196070.000027 +wvSelectUserMarker -win $_nWave2 -name "M2" +wvSetMarker -win $_nWave2 -keepViewRange -name "M2" 196070.000000 +wvSelectUserMarker -win $_nWave2 -name "M2" +wvSelectUserMarker -win $_nWave2 -name "M2" +wvSelectUserMarker -win $_nWave2 -name "M2" +wvSelectUserMarker -win $_nWave2 -name "M2" +wvSelectUserMarker -win $_nWave2 -name "M2" +wvSelectUserMarker -win $_nWave2 -name "M2" +wvSelectUserMarker -win $_nWave2 -name "M2" +wvSelectUserMarker -win $_nWave2 -name "M2" +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvSetCursor -win $_nWave2 191296.145965 -snap {("G1" 1)} +srcHBSelect "TB.U_xyz_chip_top.U_digital_top.U0_channel_top" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_xyz_chip_top.U_digital_top.U0_channel_top" \ + -delim "." +srcHBSelect "TB.U_xyz_chip_top.U_digital_top.U0_channel_top" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "xy_dsp_dout_vld" -line 139 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +wvSelectSignal -win $_nWave2 {( "G1" 2 )} +wvSetPosition -win $_nWave2 {("G1" 2)} +wvSetPosition -win $_nWave2 {("G1" 3)} +wvMoveSelected -win $_nWave2 +wvSetPosition -win $_nWave2 {("G1" 3)} +wvZoom -win $_nWave2 190326.105995 193290.117015 +wvZoom -win $_nWave2 190913.147511 191634.605076 +wvUnselectUserMarker -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 195557.885300 197502.248490 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 190300.186873 198779.445875 +wvSetCursor -win $_nWave2 191069.245070 -snap {("G1" 2)} +wvSearchNext -win $_nWave2 +wvSetCursor -win $_nWave2 196044.580755 -snap {("G1" 2)} +wvSearchNext -win $_nWave2 +wvSearchNext -win $_nWave2 +wvSearchPrev -win $_nWave2 +wvSetCursor -win $_nWave2 190978.998445 -snap {("G1" 2)} +wvSearchNext -win $_nWave2 +wvSearchPrev -win $_nWave2 +wvSearchPrev -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 165418.751578 258420.018019 +wvZoom -win $_nWave2 189475.997270 199202.182469 +wvJumpToolbarUserMarker -win $_nWave2 -name "M2" +wvJumpToolbarUserMarker -win $_nWave2 -name "M1" +wvSelectSignal -win $_nWave2 {( "G1" 1 )} +wvDeleteMarker -win $_nWave2 "M2" +wvSelectSignal -win $_nWave2 {( "G1" 2 )} +wvDeleteMarker -win $_nWave2 "M1" +wvGoToGroup -win $_nWave2 "G2" +wvSearchNext -win $_nWave2 +wvSearchNext -win $_nWave2 +wvSearchNext -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvSearchNext -win $_nWave2 +wvSearchNext -win $_nWave2 +wvSearchNext -win $_nWave2 +wvSearchNext -win $_nWave2 +wvSetCursor -win $_nWave2 191438.661355 -snap {("G1" 3)} +wvSetCursor -win $_nWave2 190199.651116 -snap {("G1" 3)} +wvSelectSignal -win $_nWave2 {( "G1" 3 )} +wvSearchNext -win $_nWave2 +wvSetCursor -win $_nWave2 193465.079969 -snap {("G1" 2)} +wvSearchPrev -win $_nWave2 +wvGoToGroup -win $_nWave2 "G1" +wvSearchNext -win $_nWave2 +wvSearchPrev -win $_nWave2 +wvSetMarkerOption -win $_nWave2 -stickMarker off +wvZoom -win $_nWave2 195549.396258 197158.951614 +wvZoom -win $_nWave2 196049.170271 196091.624994 +wvZoom -win $_nWave2 196067.519513 196071.409395 +wvSearchNext -win $_nWave2 +wvSetCursor -win $_nWave2 196068.532934 -snap {("G1" 1)} +wvSearchNext -win $_nWave2 +wvSearchPrev -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 193976.694902 198724.878225 +wvZoom -win $_nWave2 195919.033661 196228.841087 +wvSelectSignal -win $_nWave2 {( "G1" 2 )} +wvSelectSignal -win $_nWave2 {( "G1" 3 )} +wvRemoveGrid -win $_nWave2 +wvGridSetStartNum -win $_nWave2 1 +wvDisplayGridCount -win $_nWave2 -off +wvGridSetLockCount -win $_nWave2 -off +wvGridBothEdge -win $_nWave2 +wvRemoveGrid -win $_nWave2 +wvGridSetStartNum -win $_nWave2 1 +wvDisplayGridCount -win $_nWave2 -off +wvGridSetLockCount -win $_nWave2 -off +wvGridBothEdge -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 190444.932843 198831.094442 +wvZoom -win $_nWave2 190825.240032 196487.160335 +wvSelectSignal -win $_nWave2 {( "G1" 2 )} +wvSelectSignal -win $_nWave2 {( "G1" 3 )} +wvRemoveGrid -win $_nWave2 +wvGridSetStartNum -win $_nWave2 1 +wvDisplayGridCount -win $_nWave2 -off +wvGridSetLockCount -win $_nWave2 -off +wvZoomOut -win $_nWave2 +wvSetCursor -win $_nWave2 192338.316837 -snap {("G2" 0)} +wvSelectGroup -win $_nWave2 {G2} +wvSelectSignal -win $_nWave2 {( "G1" 4 )} +wvSelectSignal -win $_nWave2 {( "G1" 3 )} +wvSelectSignal -win $_nWave2 {( "G1" 3 )} +wvRemoveGrid -win $_nWave2 +wvGridSetStartNum -win $_nWave2 1 +wvDisplayGridCount -win $_nWave2 -off +wvGridSetLockCount -win $_nWave2 -off +wvGridBothEdge -win $_nWave2 +wvZoom -win $_nWave2 190892.051216 197049.160291 +wvZoomOut -win $_nWave2 +wvSetCursor -win $_nWave2 191067.276671 -snap {("G2" 0)} +wvZoom -win $_nWave2 195785.542579 196600.412174 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomIn -win $_nWave2 +wvSetCursor -win $_nWave2 191070.000000 +wvSelectSignal -win $_nWave2 {( "G1" 2 )} +wvSelectSignal -win $_nWave2 {( "G1" 3 )} +wvSelectSignal -win $_nWave2 {( "G1" 2 )} +tfgNWNodeAddSpreadSheet "TB.U_xyz_chip_top.U_digital_top.U0_channel_top.U_awg_top.U_awg_ctrl.enve_idata_o\[15:0\]#191070" +srcSelect -win $_nTrace1 -range {132 132 1 13 1 1} +srcTBAddBrkPnt -win $_nTrace1 -line 132 -file \ + /home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/top/channel_top.sv +srcSelect -win $_nTrace1 -range {132 132 1 3 1 5} +wvSetCursor -win $_nWave2 191049.909638 -snap {("G2" 0)} +wvZoom -win $_nWave2 190627.580185 198307.942941 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 190640.019459 199539.431000 +wvSelectSignal -win $_nWave2 {( "G1" 1 )} +wvSetCursor -win $_nWave2 191290.693694 -snap {("G1" 1)} +wvSetCursor -win $_nWave2 196302.532587 -snap {("G1" 1)} +wvSetCursor -win $_nWave2 196306.650778 -snap {("G1" 1)} +wvSetCursor -win $_nWave2 193032.688642 -snap {("G2" 0)} +wvSelectSignal -win $_nWave2 {( "G1" 1 )} +wvChangeDisplayAttr -win $_nWave2 -c ID_ORANGE5 -lw 1 -ls solid +wvChangeDisplayAttr -win $_nWave2 -c ID_PURPLE5 -lw 1 -ls solid +wvChangeDisplayAttr -win $_nWave2 -c ID_PURPLE8 -lw 1 -ls solid +wvChangeDisplayAttr -win $_nWave2 -c ID_PURPLE7 -lw 1 -ls solid +wvChangeDisplayAttr -win $_nWave2 -c ID_CYAN8 -lw 1 -ls solid +wvChangeDisplayAttr -win $_nWave2 -c ID_CYAN7 -lw 1 -ls solid +wvChangeDisplayAttr -win $_nWave2 -c ID_CYAN4 -lw 1 -ls solid +wvChangeDisplayAttr -win $_nWave2 -c ID_CYAN3 -lw 1 -ls solid +wvChangeDisplayAttr -win $_nWave2 -c ID_CYAN3 -lw 1 -ls solid +wvChangeDisplayAttr -win $_nWave2 -c ID_GREEN8 -lw 1 -ls solid +wvChangeDisplayAttr -win $_nWave2 -c ID_GREEN7 -lw 1 -ls solid +wvChangeDisplayAttr -win $_nWave2 -c ID_GREEN6 -lw 1 -ls solid +wvChangeDisplayAttr -win $_nWave2 -c ID_ORANGE4 -lw 1 -ls solid +wvChangeDisplayAttr -win $_nWave2 -c ID_RED8 -lw 1 -ls solid +wvChangeDisplayAttr -win $_nWave2 -c ID_ORANGE7 -lw 1 -ls solid +wvChangeDisplayAttr -win $_nWave2 -c ID_YELLOW8 -lw 1 -ls solid +wvChangeDisplayAttr -win $_nWave2 -c ID_GREEN8 -lw 1 -ls solid +wvChangeDisplayAttr -win $_nWave2 -c ID_GREEN7 -lw 1 -ls solid +wvRemoveGrid -win $_nWave2 +wvGridSetStartNum -win $_nWave2 1 +wvDisplayGridCount -win $_nWave2 -off +wvGridSetLockCount -win $_nWave2 -off +wvRemoveGrid -win $_nWave2 +wvGridSetStartNum -win $_nWave2 1 +wvDisplayGridCount -win $_nWave2 -off +wvGridSetLockCount -win $_nWave2 -off +wvSetMarker -win $_nWave2 -keepViewRange -name "M1" 196306.000000 ID_GREEN5 \ + long_dashed +wvSetMarker -win $_nWave2 -keepViewRange -name "M2" 191306.000000 ID_GREEN5 \ + long_dashed +wvSelectSignal -win $_nWave2 {( "G1" 2 )} +wvSelectGroup -win $_nWave2 {G2} +wvDeleteMarker -win $_nWave2 "M1" +wvDeleteMarker -win $_nWave2 "M2" +wvSetCursor -win $_nWave2 196298.414395 -snap {("G1" 0)} +wvSetMarker -win $_nWave2 -keepViewRange -name "m1" 196306.000000 ID_GREEN5 \ + long_dashed +wvSetMarker -win $_nWave2 -keepViewRange -name "m2" 191306.000000 ID_GREEN5 \ + long_dashed +wvZoom -win $_nWave2 196331.359926 196607.278748 +wvSetCursor -win $_nWave2 196345.915570 -snap {("G1" 1)} +wvSetMarker -win $_nWave2 -keepViewRange -name "m3" 196346.000000 ID_GREEN5 \ + long_dashed +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 196276.520901 196366.919108 +wvSelectSignal -win $_nWave2 {( "G1" 1 )} +wvSetMarkerOption -win $_nWave2 -refmarker "m1" +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoom -win $_nWave2 196436.840719 196865.196870 +wvSetCursor -win $_nWave2 196546.060636 -snap {("G1" 1)} +wvSelectGroup -win $_nWave2 {G2} +wvSetMarker -win $_nWave2 -keepViewRange -name "m4" 196546.000000 ID_GREEN5 \ + long_dashed +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 190678.585348 197925.246139 +wvZoom -win $_nWave2 196157.462105 196561.795687 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvSelectSignal -win $_nWave2 {( "G1" 1 )} +wvSetMarkerOption -win $_nWave2 -refmarker "m2" +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 190684.967964 197870.633286 +wvZoom -win $_nWave2 196217.184345 196916.481360 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +srcHBSelect "TB.U_xyz_chip_top.U_digital_top.U0_channel_top.U_awg_top" -win \ + $_nTrace1 +srcHBSelect "TB.U_xyz_chip_top.U_digital_top.U0_channel_top.U_awg_top.U_awg_ctrl" \ + -win $_nTrace1 +srcSetScope -win $_nTrace1 \ + "TB.U_xyz_chip_top.U_digital_top.U0_channel_top.U_awg_top.U_awg_ctrl" \ + -delim "." +srcHBSelect "TB.U_xyz_chip_top.U_digital_top.U0_channel_top.U_awg_top.U_awg_ctrl" \ + -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "muc_z_bais_i" -line 116 -pos 1 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "mod_amp_o" -line 117 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +wvSelectSignal -win $_nWave2 {( "G1" 2 )} +wvSetCursor -win $_nWave2 195090.808012 -snap {("G1" 2)} +wvSetCursor -win $_nWave2 196189.357647 -snap {("G1" 2)} +srcHBSelect "TB.U_xyz_chip_top.U_digital_top.U0_channel_top.U_awg_top" -win \ + $_nTrace1 +srcHBSelect "TB.U_xyz_chip_top.U_digital_top.U0_channel_top.U_awg_top" -win \ + $_nTrace1 +srcSetScope -win $_nTrace1 \ + "TB.U_xyz_chip_top.U_digital_top.U0_channel_top.U_awg_top" -delim \ + "." +srcHBSelect "TB.U_xyz_chip_top.U_digital_top.U0_channel_top.U_awg_top" -win \ + $_nTrace1 +srcHBSelect "TB.U_xyz_chip_top.U_digital_top.U0_channel_top.U_awg_top" -win \ + $_nTrace1 +srcSetScope -win $_nTrace1 \ + "TB.U_xyz_chip_top.U_digital_top.U0_channel_top.U_awg_top" -delim \ + "." +srcHBSelect "TB.U_xyz_chip_top.U_digital_top.U0_channel_top.U_awg_top" -win \ + $_nTrace1 +srcHBSelect "TB.U_xyz_chip_top.U_digital_top.U0_channel_top.U_awg_top" -win \ + $_nTrace1 +srcSetScope -win $_nTrace1 \ + "TB.U_xyz_chip_top.U_digital_top.U0_channel_top.U_awg_top" -delim \ + "." +srcHBSelect "TB.U_xyz_chip_top.U_digital_top.U0_channel_top.U_awg_top" -win \ + $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -win $_nTrace1 -range {343 343 8 13 1 1} +srcDeselectAll -win $_nTrace1 +srcSelect -inst "U_ampmod" -line 337 -pos 1 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -inst "U_ampmod" -line 337 -pos 1 -win $_nTrace1 +srcAction -pos 336 2 5 -win $_nTrace1 -name "U_ampmod" -ctrlKey off +wvZoom -win $_nWave2 195913.510382 196702.336772 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +srcHBSelect "TB.U_xyz_chip_top.U_digital_top.U_spi_slave.U_spi_sys" -win \ + $_nTrace1 +srcHBSelect "TB.U_xyz_chip_top.U_digital_top.U_spi_slave.U_spi_sys" -win \ + $_nTrace1 +srcSetScope -win $_nTrace1 \ + "TB.U_xyz_chip_top.U_digital_top.U_spi_slave.U_spi_sys" -delim "." +srcHBSelect "TB.U_xyz_chip_top.U_digital_top.U_spi_slave.U_spi_sys" -win \ + $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "csn_p" -line 102 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "csn_n" -line 105 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "csn_reg" -line 97 -pos 1 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "csn" -line 97 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +wvZoom -win $_nWave2 190483.164005 190925.343504 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 349.807734 19939.040813 +wvZoom -win $_nWave2 392.171992 1222.511456 +wvZoom -win $_nWave2 316.405306 435.281761 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "csn_p" -line 102 -pos 1 -win $_nTrace1 +srcSearchString "csn_p" -win $_nTrace1 -next -case +srcSearchString "csn_p" -win $_nTrace1 -next -case +srcSearchString "csn_p" -win $_nTrace1 -next -case +srcSearchString "csn_p" -win $_nTrace1 -next -case +srcDeselectAll -win $_nTrace1 +debReload +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 192569.157327 216880.794810 +wvZoom -win $_nWave2 195713.266154 196922.538779 +wvZoom -win $_nWave2 196126.469170 196334.116762 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +srcDeselectAll -win $_nTrace1 +debReload +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +srcDeselectAll -win $_nTrace1 +debReload +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 0.000000 7520.866272 +wvZoom -win $_nWave2 234.213829 618.064270 +wvSelectSignal -win $_nWave2 {( "G1" 5 )} +wvSetCursor -win $_nWave2 381.976325 -snap {("G1" 5)} +srcDeselectAll -win $_nTrace1 +srcSelect -signal "cnt_c" -line 157 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "csn_p" -line 197 -pos 1 -win $_nTrace1 +srcSelect -signal "csn_p" -line 198 -pos 1 -win $_nTrace1 +wvSetCursor -win $_nWave2 390.609640 -snap {("G1" 6)} +srcDeselectAll -win $_nTrace1 +srcSelect -signal "sclk_reg\[2:1\]" -line 86 -pos 1 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "csn_reg\[2:1\]" -line 102 -pos 1 -win $_nTrace1 +wvSetCursor -win $_nWave2 382.972477 -snap {("G1" 7)} +srcDeselectAll -win $_nTrace1 +srcSelect -signal "clk" -line 97 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +wvSetCursor -win $_nWave2 386.126957 -snap {("G1" 9)} +wvSetCursor -win $_nWave2 390.277589 -snap {("G1" 9)} +srcDeselectAll -win $_nTrace1 +debReload +wvSetCursor -win $_nWave2 385.628882 -snap {("G1" 9)} +wvSetCursor -win $_nWave2 389.779514 -snap {("G1" 9)} +wvSelectSignal -win $_nWave2 {( "G1" 6 )} +wvSetCursor -win $_nWave2 385.794907 -snap {("G1" 9)} +wvSetCursor -win $_nWave2 390.111564 -snap {("G1" 9)} +wvSetCursor -win $_nWave2 385.462857 -snap {("G1" 9)} +wvSetCursor -win $_nWave2 390.277590 -snap {("G1" 9)} +wvSetCursor -win $_nWave2 385.794907 -snap {("G1" 9)} +wvSetCursor -win $_nWave2 390.277590 -snap {("G1" 9)} +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 1097.095032 1498.212102 +wvSetCursor -win $_nWave2 1165.971968 -snap {("G1" 5)} +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 274.813771 727.284929 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 1119.435565 1272.868691 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 183474.156254 221953.006946 +wvZoom -win $_nWave2 194025.882612 199950.826750 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 174.903867 23262.214282 +wvZoom -win $_nWave2 234.819032 1453.094063 +wvZoom -win $_nWave2 363.918246 425.042772 +wvZoomOut -win $_nWave2 +wvSetCursor -win $_nWave2 385.861739 -snap {("G1" 9)} +wvSetCursor -win $_nWave2 389.933183 -snap {("G1" 9)} +wvSetCursor -win $_nWave2 385.914615 -snap {("G1" 9)} +wvSetCursor -win $_nWave2 389.774555 -snap {("G1" 9)} +wvSetCursor -win $_nWave2 385.808863 -snap {("G1" 9)} +wvSetCursor -win $_nWave2 389.774555 -snap {("G1" 9)} +srcDeselectAll -win $_nTrace1 +debReload +wvSetCursor -win $_nWave2 386.020367 -snap {("G1" 9)} +wvSetCursor -win $_nWave2 389.986059 -snap {("G1" 9)} +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +srcDeselectAll -win $_nTrace1 +debReload +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 7742.721965 16676.631924 +wvSetCursor -win $_nWave2 8264.381932 -snap {("G1" 6)} +wvZoom -win $_nWave2 8979.249295 9547.279037 +wvSetCursor -win $_nWave2 9165.480499 -snap {("G1" 5)} +wvZoomOut -win $_nWave2 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "add_cnt" -line 122 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "end_cnt" -line 124 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 330.204141 1823.984778 +wvZoom -win $_nWave2 726.908860 818.654903 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 1908.571654 2053.333576 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +srcDeselectAll -win $_nTrace1 +debReload +wvZoom -win $_nWave2 186272.618123 232447.238953 +wvZoom -win $_nWave2 193781.985524 199733.558624 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 194863.153648 197890.424394 +wvZoom -win $_nWave2 195578.071393 195733.886799 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 195440.317635 198627.794038 +wvZoom -win $_nWave2 195831.858854 197768.884955 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 189186.317747 208757.654138 +wvZoom -win $_nWave2 194553.198055 201858.588758 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 195463.212122 198521.870513 +wvZoomOut -win $_nWave2 +srcHBSelect "TB" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB" -delim "." +srcHBSelect "TB" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -win $_nTrace1 -range {45 47 1 1 3 1} -backward +srcDeselectAll -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -win $_nTrace1 -range {47 58 1 1 1 1} -backward +srcHBSelect "TB.U_xyz_chip_top.U_digital_top.U_spi_slave.U_spi_pll" -win \ + $_nTrace1 +srcSetScope -win $_nTrace1 \ + "TB.U_xyz_chip_top.U_digital_top.U_spi_slave.U_spi_pll" -delim "." +srcHBSelect "TB.U_xyz_chip_top.U_digital_top.U_spi_slave.U_spi_pll" -win \ + $_nTrace1 +srcHBSelect "TB.U_xyz_chip_top.U_digital_top.U_intpll_regfile" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_xyz_chip_top.U_digital_top.U_intpll_regfile" \ + -delim "." +srcHBSelect "TB.U_xyz_chip_top.U_digital_top.U_intpll_regfile" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "div_sync_en" -line 109 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +wvSetPosition -win $_nWave2 {("G1" 13)} +wvSetPosition -win $_nWave2 {("G2" 0)} +wvMoveSelected -win $_nWave2 +wvSetPosition -win $_nWave2 {("G2" 1)} +wvSetPosition -win $_nWave2 {("G2" 1)} +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +srcHBSelect "TB.U_xyz_chip_top.U_digital_top.U_sync_buf" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_xyz_chip_top.U_digital_top.U_sync_buf" -delim \ + "." +srcHBSelect "TB.U_xyz_chip_top.U_digital_top.U_sync_buf" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "clr_ena" -line 5 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "sync_clr" -line 18 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "sync_int" -line 15 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +srcDeselectAll -win $_nTrace1 +debReload +srcDeselectAll -win $_nTrace1 +srcSelect -signal "sync_int" -line 15 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +wvZoom -win $_nWave2 183474.156254 214607.044542 +wvZoom -win $_nWave2 194933.536848 196562.896486 +wvZoom -win $_nWave2 195492.395928 195751.740368 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +srcHBSelect "TB.U_xyz_chip_top.U_digital_top.U_intpll_regfile" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_xyz_chip_top.U_digital_top.U_intpll_regfile" \ + -delim "." +srcHBSelect "TB.U_xyz_chip_top.U_digital_top.U_intpll_regfile" -win $_nTrace1 +wvSelectSignal -win $_nWave2 {( "G2" 2 )} +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvSetCursor -win $_nWave2 184873.387189 -snap {("G2" 2)} +srcDeselectAll -win $_nTrace1 +srcSelect -signal "sync_oe" -line 110 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 0 +wvZoom -win $_nWave2 1049.423201 18889.617612 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "sync_oe" -line 110 -pos 1 -win $_nTrace1 +srcAction -pos 109 4 4 -win $_nTrace1 -name "sync_oe" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -signal "sync_r\[1\]" -line 667 -pos 1 -win $_nTrace1 +srcAction -pos 666 6 3 -win $_nTrace1 -name "sync_r\[1\]" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -signal "dnxt" -line 155 -pos 1 -win $_nTrace1 +srcAction -pos 154 12 3 -win $_nTrace1 -name "dnxt" -ctrlKey off +srcBackwardHistory -win $_nTrace1 +srcHBSelect "TB.U_xyz_chip_top.U_digital_top.U_spi_slave.U_spi_pll" -win \ + $_nTrace1 +srcHBSelect "TB.U_xyz_chip_top.U_digital_top.U_intpll_regfile.sync_dfflrd" -win \ + $_nTrace1 +srcBackwardHistory -win $_nTrace1 +srcHBSelect "TB.U_xyz_chip_top.U_digital_top.U_intpll_regfile.sync_dfflrd" -win \ + $_nTrace1 +srcHBSelect "TB.U_xyz_chip_top.U_digital_top.U_intpll_regfile" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "synccfgwe" -line 574 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +wvZoom -win $_nWave2 1782.476172 2376.634896 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "wrdata\[1:0\]" -line 574 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "sync_r" -line 574 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "clk" -line 574 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +srcDeselectAll -win $_nTrace1 +debReload +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 0 +wvZoom -win $_nWave2 1749.038668 40927.504827 +wvZoom -win $_nWave2 1799.875778 3308.043377 +wvZoom -win $_nWave2 1904.899560 1991.006014 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 1844.882930 2178.582685 +wvSetCursor -win $_nWave2 1934.081221 -snap {("G2" 8)} +wvSetCursor -win $_nWave2 1946.205261 -snap {("G2" 10)} +srcDeselectAll -win $_nTrace1 +debReload +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 188721.272258 210584.255606 +wvZoom -win $_nWave2 192390.319636 195851.328246 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollDown -win $_nWave2 0 +srcDeselectAll -win $_nTrace1 +debReload +srcDeselectAll -win $_nTrace1 +debReload +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvSelectSignal -win $_nWave2 {( "G1" 3 )} +wvSelectSignal -win $_nWave2 {( "G1" 4 )} +wvSelectSignal -win $_nWave2 {( "G1" 4 5 6 7 8 9 10 11 12 )} {( "G2" 1 2 3 4 5 \ + )} +wvCut -win $_nWave2 +wvSetPosition -win $_nWave2 {("G2" 5)} +wvSelectSignal -win $_nWave2 {( "G2" 1 )} +wvSelectSignal -win $_nWave2 {( "G2" 1 2 3 4 5 )} +wvCut -win $_nWave2 +wvSetPosition -win $_nWave2 {("G2" 0)} +wvSelectSignal -win $_nWave2 {( "G1" 1 )} +wvChangeDisplayAttr -win $_nWave2 -c ID_RED8 -lw 1 -ls solid +wvZoom -win $_nWave2 180325.886652 223352.237881 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +verdiDockWidgetMaximize -dock windowDock_nWave_2 +verdiDockWidgetRestore -dock windowDock_nWave_2 +wvZoomIn -win $_nWave2 +wvZoom -win $_nWave2 186428.985312 193091.370147 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 177702.328651 298211.092863 +wvZoom -win $_nWave2 214709.777868 238321.572932 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 211278.305921 230273.954199 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 310279.459671 383039.468253 +wvZoom -win $_nWave2 333158.580017 346281.816858 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 232097.431220 303108.401133 +wvZoom -win $_nWave2 252184.444335 267480.059827 +wvZoom -win $_nWave2 254791.050090 259838.867832 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 249411.368897 256555.166325 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 239214.772222 245579.920450 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 182049.574218 297194.885398 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 168607.327578 314127.344740 +wvZoom -win $_nWave2 184153.800000 203602.625823 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 186139.060767 200153.655845 +wvZoom -win $_nWave2 186799.783459 194916.367719 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 182432.555595 202653.803580 +wvZoom -win $_nWave2 186062.234624 194773.464292 +wvZoom -win $_nWave2 187004.192849 192757.673689 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 186859.858122 192991.595488 +wvSetCursor -win $_nWave2 187331.938248 -snap {("G1" 1)} +wvSetCursor -win $_nWave2 192344.474417 -snap {("G1" 1)} +wvSetCursor -win $_nWave2 187331.938248 -snap {("G1" 1)} +wvSetCursor -win $_nWave2 192339.170145 -snap {("G1" 1)} +srcDeselectAll -win $_nTrace1 +debReload +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvSetCursor -win $_nWave2 185353.445136 -snap {("G1" 1)} +wvSetCursor -win $_nWave2 195378.517473 -snap {("G1" 1)} +wvSetCursor -win $_nWave2 190328.851407 -snap {("G1" 2)} +wvZoomIn -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 121383.283547 289640.803391 +wvZoom -win $_nWave2 176037.867199 221304.379890 +wvZoom -win $_nWave2 183458.286018 201098.912287 +srcDeselectAll -win $_nTrace1 +debReload +wvZoom -win $_nWave2 184160.248655 187692.951926 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 182879.796518 187540.153342 +srcDeselectAll -win $_nTrace1 +debReload +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 177527.424784 215481.563875 +wvZoom -win $_nWave2 190052.947330 197111.891884 +wvZoom -win $_nWave2 191866.534296 193066.432743 +wvZoomOut -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 193189.744106 193342.326348 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvSetCursor -win $_nWave2 193250.196240 -snap {("G1" 1)} +wvSetCursor -win $_nWave2 193289.793707 -snap {("G1" 1)} +srcHBSelect "TB.U_xyz_chip_top.U_digital_top.U0_channel_top" -win $_nTrace1 +srcHBSelect "TB.U_xyz_chip_top.U_digital_top.U0_channel_top.U_awg_top.U_awg_ctrl" \ + -win $_nTrace1 +srcSetScope -win $_nTrace1 \ + "TB.U_xyz_chip_top.U_digital_top.U0_channel_top.U_awg_top.U_awg_ctrl" \ + -delim "." +srcHBSelect "TB.U_xyz_chip_top.U_digital_top.U0_channel_top.U_awg_top.U_awg_ctrl" \ + -win $_nTrace1 +srcSelect -signal "enve_len_i" -line 90 -pos 1 -win $_nTrace1 +srcSelect -signal "enve_start_addr_i" -line 89 -pos 1 -win $_nTrace1 +srcSelect -signal "enve_index_vld_i" -line 88 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +wvSelectSignal -win $_nWave2 {( "G2" 1 )} +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 191846.122834 192583.163698 +wvZoom -win $_nWave2 192005.836274 192207.629901 +wvZoomOut -win $_nWave2 +wvSelectSignal -win $_nWave2 {( "G2" 1 )} +wvSetRadix -win $_nWave2 -format UDec +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "wave_hold_i" -line 91 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 191220.516921 194203.431721 +wvZoom -win $_nWave2 191775.297787 192902.922154 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "wave_hold_i" -line 91 -pos 1 -win $_nTrace1 +srcAction -pos 90 4 3 -win $_nTrace1 -name "wave_hold_i" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -signal "dnxt" -line 107 -pos 1 -win $_nTrace1 +srcAction -pos 106 12 1 -win $_nTrace1 -name "dnxt" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -signal "codeword_i\[19\]" -line 65 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +srcDeselectAll -win $_nTrace1 +debReload +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 180883.382837 198597.620298 +wvZoom -win $_nWave2 185710.359308 191020.033426 +wvZoom -win $_nWave2 187354.704753 188937.042757 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 187313.640617 188980.844501 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 187160.765521 189531.771736 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 187236.654128 188920.560791 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 187322.597461 188415.097459 +wvZoomOut -win $_nWave2 +srcDeselectAll -win $_nTrace1 +debReload +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 186358.626875 188802.575832 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 186331.143019 188419.916004 +srcDeselectAll -win $_nTrace1 +debReload +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 185973.377404 188311.502181 +srcDeselectAll -win $_nTrace1 +debReload +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 183129.602805 187029.174232 +wvZoom -win $_nWave2 184359.182204 185759.114853 +wvZoomOut -win $_nWave2 +srcDeselectAll -win $_nTrace1 +debReload +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 187384.296182 235902.377211 +wvZoom -win $_nWave2 191455.450040 200793.921518 +wvZoom -win $_nWave2 192053.241466 195942.924872 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 192716.102739 195878.994089 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 192858.378128 195687.469526 +srcDeselectAll -win $_nTrace1 +debReload +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 192941.586699 196715.340103 +srcDeselectAll -win $_nTrace1 +debReload +srcDeselectAll -win $_nTrace1 +debReload +wvZoom -win $_nWave2 193798.189548 194049.555475 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 193071.489781 193374.172628 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +srcDeselectAll -win $_nTrace1 +debReload +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 183838.615602 195769.975440 +wvZoom -win $_nWave2 187296.232856 188478.015470 +wvZoom -win $_nWave2 187625.925670 187765.981222 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 diff --git a/tb/chip_top/verdiLog/verdi.cmd.bak b/tb/chip_top/verdiLog/verdi.cmd.bak new file mode 100644 index 0000000..dc2c3f1 --- /dev/null +++ b/tb/chip_top/verdiLog/verdi.cmd.bak @@ -0,0 +1,1139 @@ +sidCmdLineBehaviorAnalysisOpt -incr -clockSkew 0 -loopUnroll 0 -bboxEmptyModule 0 -cellModel 0 -bboxIgnoreProtected 0 +debImport "-sverilog" "-f" "files.f" "-top" "TB" +wvCreateWindow +wvSetPosition -win $_nWave2 {("G1" 0)} +wvOpenFile -win $_nWave2 \ + {/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/digital_top/verdplus_000.fsdb} +srcDeselectAll -win $_nTrace1 +srcSelect -signal "clk" -line 151 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +srcHBSelect "TB.U_digital_top" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top" -delim "." +srcHBSelect "TB.U_digital_top" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "sclk" -line 58 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +wvZoom -win $_nWave2 183894753.436807 259270219.235033 +wvZoom -win $_nWave2 196897439.111084 202111883.751671 +wvZoom -win $_nWave2 197903329.762288 198386619.753367 +wvZoom -win $_nWave2 197998916.163983 198078428.619278 +wvZoomOut -win $_nWave2 +srcHBSelect "TB.U_digital_top.U_debug_top" -win $_nTrace1 +srcHBSelect "TB.U_digital_top.U0_channel_top" -win $_nTrace1 +srcHBSelect "TB.U_digital_top.U0_channel_top.U_ITCM" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U0_channel_top.U_ITCM" -delim "." +srcHBSelect "TB.U_digital_top.U0_channel_top.U_ITCM" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -inst "U_tsmc_dpram" -line 70 -pos 1 -win $_nTrace1 +srcAction -pos 69 3 5 -win $_nTrace1 -name "U_tsmc_dpram" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -signal "U0_CEBB" -line 96 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 60081656.330637 274989119.359453 +wvZoom -win $_nWave2 66276328.213944 73709934.473921 +wvZoom -win $_nWave2 67917984.940090 68244338.385650 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "PortBWriteEnable" -line 97 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "PortBDataIn" -line 100 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 67851918.266964 68236306.183330 +wvSetCursor -win $_nWave2 68016241.970453 -snap {("G1" 3)} +srcDeselectAll -win $_nTrace1 +srcSelect -signal "PortClk" -line 89 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +wvZoom -win $_nWave2 68041470.090907 68058857.038787 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvSetCursor -win $_nWave2 68047110.247164 -snap {("G1" 6)} +wvSetCursor -win $_nWave2 68014849.941208 -snap {("G1" 6)} +srcDeselectAll -win $_nTrace1 +debReload +wvSelectSignal -win $_nWave2 {( "G1" 3 )} +wvSetCursor -win $_nWave2 68047295.296720 -snap {("G1" 6)} +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvSetCursor -win $_nWave2 68013400.386351 -snap {("G1" 6)} +wvSelectSignal -win $_nWave2 {( "G1" 4 )} +wvSelectSignal -win $_nWave2 {( "G1" 4 5 )} +wvSelectSignal -win $_nWave2 {( "G1" 3 4 5 )} +wvCut -win $_nWave2 +wvSetPosition -win $_nWave2 {("G1" 3)} +wvSelectGroup -win $_nWave2 {G2} +srcDeselectAll -win $_nTrace1 +srcSelect -signal "U0_CEBB" -line 96 -pos 1 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "U0_CEBA" -line 90 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "U0_CEBA" -line 90 -pos 1 -win $_nTrace1 +srcAction -pos 89 7 5 -win $_nTrace1 -name "U0_CEBA" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -signal "PortAChipEnable" -line 48 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "PortAChipEnable" -line 48 -pos 1 -win $_nTrace1 +srcAction -pos 47 11 11 -win $_nTrace1 -name "PortAChipEnable" -ctrlKey off +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "ifu_o_req" -line 342 -pos 1 -win $_nTrace1 +srcAction -pos 341 8 6 -win $_nTrace1 -name "ifu_o_req" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -signal "ifu_req_w" -line 112 -pos 1 -win $_nTrace1 +srcAction -pos 111 6 5 -win $_nTrace1 -name "ifu_req_w" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -signal "ifu_active" -line 65 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "ifu_active" -line 65 -pos 1 -win $_nTrace1 +srcAction -pos 64 6 6 -win $_nTrace1 -name "ifu_active" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -signal "dnxt" -line 263 -pos 1 -win $_nTrace1 +srcAction -pos 262 11 1 -win $_nTrace1 -name "dnxt" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -signal "clk" -line 37 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "start" -line 39 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +wvZoom -win $_nWave2 281730289.068736 361465276.541020 +wvZoom -win $_nWave2 302167904.482882 304254097.059762 +wvSetCursor -win $_nWave2 302816428.206256 -snap {("G2" 0)} +wvDisplayGridCount -win $_nWave2 -off +wvGetSignalClose -win $_nWave2 +wvReloadFile -win $_nWave2 +wvSetCursor -win $_nWave2 302703561.024713 -snap {("G2" 0)} +wvSetCursor -win $_nWave2 302673031.377246 -snap {("G2" 0)} +wvSetCursor -win $_nWave2 302600870.392325 -snap {("G1" 9)} +wvZoom -win $_nWave2 302576816.730685 302747967.784664 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "start" -line 39 -pos 1 -win $_nTrace1 +srcAction -pos 38 4 1 -win $_nTrace1 -name "start" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -signal "sync_in" -line 6 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "sync_int" -line 7 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "sync_int" -line 15 -pos 2 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "sync_r\[1\]" -line 15 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "sync_r\[1:0\]" -line 14 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "sync_r\[1\]" -line 15 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "sync_r\[1\]" -line 16 -pos 1 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +wvSetCursor -win $_nWave2 302310830.536111 -snap {("G1" 11)} +wvDisplayGridCount -win $_nWave2 -off +wvGetSignalClose -win $_nWave2 +wvReloadFile -win $_nWave2 +wvSetCursor -win $_nWave2 303060100.250027 -snap {("G1" 12)} +srcBackwardHistory -win $_nTrace1 +srcHBSelect "TB.U_digital_top.U_sync_buf" -win $_nTrace1 +srcHBSelect "TB.U_digital_top.U0_channel_top.U_qbmcu.U_qbmcu_fsm" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "state_c" -line 59 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 792751.463415 11362770.975610 +wvZoom -win $_nWave2 1880221.320102 2405206.768157 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "rst_n" -line 38 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 1691128.290323 2488268.057127 +wvSelectSignal -win $_nWave2 {( "G1" 8 )} +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +srcHBSelect \ + "TB.U_digital_top.U0_channel_top.U_ITCM.U_tsmc_dpram.dpram_32X4096_generation" \ + -win $_nTrace1 +srcHBSelect "TB.inst_clk_gen" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.inst_clk_gen" -delim "." +srcHBSelect "TB.inst_clk_gen" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "clk" -line 3 -pos 1 -win $_nTrace1 +wvSelectSignal -win $_nWave2 {( "G1" 8 )} +wvSelectSignal -win $_nWave2 {( "G1" 13 )} +wvSelectAll -win $_nWave2 +wvCut -win $_nWave2 +wvSetPosition -win $_nWave2 {("G1" 0)} +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "clk_div16_0" -line 4 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +wvZoom -win $_nWave2 622157.866774 3744259.161857 +wvZoom -win $_nWave2 1875151.956375 2183900.776243 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "clk_l" -line 22 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +wvZoom -win $_nWave2 1824835.596988 2381268.059935 +wvZoom -win $_nWave2 1999044.607560 2113538.914792 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "rstn" -line 2 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +srcHBSelect "TB" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB" -delim "." +srcHBSelect "TB" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "rstn" -line 152 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +srcHBSelect "TB.inst_clk_gen" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.inst_clk_gen" -delim "." +srcHBSelect "TB.inst_clk_gen" -win $_nTrace1 +wvSetCursor -win $_nWave2 2041542.051087 -snap {("G1" 4)} +wvSetCursor -win $_nWave2 2031184.251231 -snap {("G1" 3)} +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvSetWindowTimeUnit -win $_nWave2 1.000000 ns +wvSetCursor -win $_nWave2 1999.222315 -snap {("G1" 4)} +wvSetCursor -win $_nWave2 2030.904997 -snap {("G1" 3)} +wvSetCursor -win $_nWave2 1999.222315 -snap {("G1" 4)} +srcDeselectAll -win $_nTrace1 +debReload +srcHBSelect "TB.U_digital_top" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top" -delim "." +srcHBSelect "TB.U_digital_top" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "por_rstn" -line 40 -pos 1 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "async_rstn" -line 43 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvSelectSignal -win $_nWave2 {( "G1" 3 )} +wvSelectAll -win $_nWave2 +wvCut -win $_nWave2 +wvSetPosition -win $_nWave2 {("G1" 0)} +srcDeselectAll -win $_nTrace1 +srcSelect -signal "ch0_xy_dsp_dout0" -line 239 -pos 1 -win $_nTrace1 +srcSelect -win $_nTrace1 -range {239 254 12 12 10 12} +srcDeselectAll -win $_nTrace1 +srcSelect -signal "ch0_xy_dsp_dout15" -line 254 -pos 1 -win $_nTrace1 +srcHBSelect "TB" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB" -delim "." +srcHBSelect "TB" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "cs_wave" -line 836 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "i_cs_f" -line 836 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "ch0_xy_dsp_dout0" -line 744 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "ch0_xy_dsp_dout0" -line 744 -pos 1 -win $_nTrace1 +srcAction -pos 743 12 10 -win $_nTrace1 -name "ch0_xy_dsp_dout0" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -signal "ch0_xy_dsp_dout0" -line 744 -pos 1 -win $_nTrace1 +srcAction -pos 743 12 10 -win $_nTrace1 -name "ch0_xy_dsp_dout0" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -signal "ch0_xy_dsp_dout0" -line 744 -pos 1 -win $_nTrace1 +srcAction -pos 743 12 10 -win $_nTrace1 -name "ch0_xy_dsp_dout0" -ctrlKey off +srcHBSelect "TB" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB" -delim "." +srcHBSelect "TB" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +debReload +wvSelectSignal -win $_nWave2 {( "G1" 1 )} +wvSelectSignal -win $_nWave2 {( "G1" 1 2 )} +wvCut -win $_nWave2 +wvSetPosition -win $_nWave2 {("G1" 1)} +wvZoom -win $_nWave2 594458.977237 792611.969650 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "ch0_xy_dsp_dout13" -line 633 -pos 2 -win $_nTrace1 +srcSearchString "ch0_xy_dsp_dout13" -win $_nTrace1 -next -case +srcDeselectAll -win $_nTrace1 +srcSelect -signal "i_cs_d" -line 757 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "ch0_xy_dsp_dout9" -line 753 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "i_cs_a" -line 754 -pos 1 -win $_nTrace1 +srcSearchString "i_cs_a" -win $_nTrace1 -next -case +srcSearchString "i_cs_a" -win $_nTrace1 -next -case +srcDeselectAll -win $_nTrace1 +srcSelect -signal "i_cs_8" -line 752 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "i_cs_8" -line 752 -pos 1 -win $_nTrace1 +srcAction -pos 751 8 3 -win $_nTrace1 -name "i_cs_8" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -signal "i_cs_8" -line 752 -pos 1 -win $_nTrace1 +srcAction -pos 751 8 3 -win $_nTrace1 -name "i_cs_8" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -signal "i_cs_8" -line 752 -pos 1 -win $_nTrace1 +srcAction -pos 751 8 3 -win $_nTrace1 -name "i_cs_8" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -signal "i_cs_8" -line 752 -pos 1 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +debReload +wvSelectSignal -win $_nWave2 {( "G1" 3 )} +srcDeselectAll -win $_nTrace1 +srcSelect -signal "cs_wave" -line 743 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +wvSelectSignal -win $_nWave2 {( "G1" 4 )} +wvSelectSignal -win $_nWave2 {( "G1" 5 )} +wvBusWaveform -win $_nWave2 -analog +wvSetPosition -win $_nWave2 {("G1" 5)} +wvZoomIn -win $_nWave2 +wvZoom -win $_nWave2 661220.279226 667722.860795 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 1868528.810754 2059533.978075 +wvZoom -win $_nWave2 1994143.295515 2004646.462144 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvSelectSignal -win $_nWave2 {( "G1" 3 )} +wvSetCursor -win $_nWave2 161345.979849 -snap {("G1" 3)} +srcActiveTrace "TB.ch0_xy_dsp_dout9\[15:0\]" -win $_nTrace1 -TraceByDConWave \ + -TraceTime 22863000 -TraceValue 1000000000000000 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "dout9_r" -line 361 -pos 1 -win $_nTrace1 +srcAction -pos 360 6 2 -win $_nTrace1 -name "dout9_r" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -signal "rstn" -line 237 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +wvZoom -win $_nWave2 0.000000 39150.127463 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 298895.163818 370563.335068 +wvZoom -win $_nWave2 308397.950161 312307.123139 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomIn -win $_nWave2 +verdiDockWidgetMaximize -dock windowDock_nWave_2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 357671.732033 362664.378673 +wvZoomOut -win $_nWave2 +wvSetCursor -win $_nWave2 359213.806704 -snap {("G1" 5)} +wvZoom -win $_nWave2 359036.683985 359652.185434 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 366244.601723 371380.422234 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 375198.694113 378223.248276 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 375776.108999 376540.630450 +wvZoomOut -win $_nWave2 +wvSelectSignal -win $_nWave2 {( "G1" 5 )} +wvAddSignal -win $_nWave2 "/TB/cs_wave\[15:0\]" +wvSetPosition -win $_nWave2 {("G1" 6)} +wvSetPosition -win $_nWave2 {("G1" 7)} +wvSetCursor -win $_nWave2 375865.105398 -snap {("G1" 7)} +wvSetCursor -win $_nWave2 375901.721060 -snap {("G1" 7)} +wvSelectSignal -win $_nWave2 {( "G1" 1 )} +wvSelectSignal -win $_nWave2 {( "G1" 1 2 3 4 )} +wvCut -win $_nWave2 +wvSetPosition -win $_nWave2 {("G1" 3)} +verdiDockWidgetRestore -dock windowDock_nWave_2 +srcHBSelect "TB" -win $_nTrace1 +srcHBSelect "TB.U_digital_top" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top" -delim "." +srcHBSelect "TB.U_digital_top" -win $_nTrace1 +verdiDockWidgetMaximize -dock windowDock_nWave_2 +verdiDockWidgetRestore -dock windowDock_nWave_2 +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U0_channel_top.U_awg_top" -delim "." +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top" -win $_nTrace1 +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.U_awg_ctrl" -win $_nTrace1 +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.U_awg_ctrl" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U0_channel_top.U_awg_top.U_awg_ctrl" \ + -delim "." +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.U_awg_ctrl" -win $_nTrace1 +srcSelect -signal "enve_vld_o" -line 100 -pos 1 -win $_nTrace1 +srcSelect -signal "enve_qdata_o" -line 99 -pos 1 -win $_nTrace1 +srcSelect -signal "enve_idata_o" -line 98 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +wvZoomOut -win $_nWave2 +wvSelectSignal -win $_nWave2 {( "G1" 5 )} +wvSelectSignal -win $_nWave2 {( "G1" 6 )} +wvSetRadix -win $_nWave2 -2Com +wvBusWaveform -win $_nWave2 -analog +wvSetPosition -win $_nWave2 {("G1" 6)} +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 0 +verdiDockWidgetMaximize -dock windowDock_nWave_2 +wvZoomIn -win $_nWave2 +wvSetCursor -win $_nWave2 367506.224517 -snap {("G1" 6)} +wvSetCursor -win $_nWave2 365401.502046 -snap {("G1" 6)} +wvSetCursor -win $_nWave2 367506.224517 -snap {("G1" 6)} +wvSetCursor -win $_nWave2 373842.090098 -snap {("G1" 6)} +wvSetCursor -win $_nWave2 376001.057993 -snap {("G1" 6)} +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomOut -win $_nWave2 +wvSetCursor -win $_nWave2 373877.349624 -snap {("G1" 6)} +wvSetCursor -win $_nWave2 374452.351124 -snap {("G1" 6)} +wvSetCursor -win $_nWave2 375314.853373 -snap {("G1" 6)} +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 363725.318429 369193.257219 +wvZoomOut -win $_nWave2 +wvSetCursor -win $_nWave2 365554.834978 -snap {("G1" 6)} +wvSelectSignal -win $_nWave2 {( "G1" 5 )} +wvSetRadix -win $_nWave2 -2Com +wvBusWaveform -win $_nWave2 -analog +wvSetPosition -win $_nWave2 {("G1" 6)} +wvSetCursor -win $_nWave2 361718.791002 -snap {("G1" 5)} +srcActiveTrace \ + "TB.U_digital_top.U0_channel_top.U_awg_top.U_awg_ctrl.enve_qdata_o\[15:0\]" \ + -win $_nTrace1 -TraceByDConWave -TraceTime 358480000 -TraceValue \ + 0110001001000111 +wvSetCursor -win $_nWave2 359488.827971 -snap {("G1" 5)} +srcActiveTrace \ + "TB.U_digital_top.U0_channel_top.U_awg_top.U_awg_ctrl.enve_qdata_o\[15:0\]" \ + -win $_nTrace1 -TraceByDConWave -TraceTime 359056000 -TraceValue \ + 0000000000000000 +verdiDockWidgetRestore -dock windowDock_nWave_2 +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.U_awg_ctrl" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U0_channel_top.U_awg_top.U_awg_ctrl" \ + -delim "." +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.U_awg_ctrl" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "enve_idata_o" -line 98 -pos 1 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "enve_idata_o" -line 98 -pos 1 -win $_nTrace1 +srcAction -pos 97 11 7 -win $_nTrace1 -name "enve_idata_o" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -signal "dnxt" -line 277 -pos 1 -win $_nTrace1 +srcAction -pos 276 12 3 -win $_nTrace1 -name "dnxt" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -signal "enve_idata_o" -line 98 -pos 1 -win $_nTrace1 +srcSearchString "enve_idata_o" -win $_nTrace1 -next -case +srcDeselectAll -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +debReload +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 379796.582900 386159.275310 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 405573.246542 411803.324077 +wvZoomOut -win $_nWave2 +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.U_awg_ctrl.cnt_c_dffr" \ + -win $_nTrace1 +srcHBSelect "TB" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB" -delim "." +srcHBSelect "TB" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "cs_wave" -line 812 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 0 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 409605.529541 412279.904288 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "clk_div16_b" -line 813 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "intp_mode" -line 765 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U0_channel_top.U_awg_top" -delim "." +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +debReload +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvSelectSignal -win $_nWave2 {( "G1" 7 )} +wvSetRadix -win $_nWave2 -2Com +wvSetRadix -win $_nWave2 -Unsigned +wvBusWaveform -win $_nWave2 -analog +wvSetPosition -win $_nWave2 {("G1" 9)} +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 409670.165206 410275.012709 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 408985.520747 413071.124817 +wvZoomOut -win $_nWave2 +wvScrollUp -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 402251.974173 404339.165254 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvZoom -win $_nWave2 402358.879082 403713.933513 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvSelectSignal -win $_nWave2 {( "G1" 6 )} +wvScrollUp -win $_nWave2 1 +wvSelectSignal -win $_nWave2 {( "G1" 5 )} +wvSelectSignal -win $_nWave2 {( "G1" 6 )} +wvScrollDown -win $_nWave2 1 +wvSelectSignal -win $_nWave2 {( "G1" 6 )} +wvSelectSignal -win $_nWave2 {( "G1" 7 )} +wvSelectSignal -win $_nWave2 {( "G1" 6 )} +wvAddSignal -win $_nWave2 \ + "/TB/U_digital_top/U0_channel_top/U_awg_top/U_awg_ctrl/enve_idata_o\[15:0\]" +wvSetPosition -win $_nWave2 {("G1" 9)} +wvSetPosition -win $_nWave2 {("G1" 10)} +wvSetCursor -win $_nWave2 401279.342370 -snap {("G1" 10)} +wvZoom -win $_nWave2 400534.212660 401663.925445 +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.U_awg_ctrl" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U0_channel_top.U_awg_top.U_awg_ctrl" \ + -delim "." +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.U_awg_ctrl" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "enve_vld_o" -line 100 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +wvSetCursor -win $_nWave2 400658.956999 -snap {("G1" 11)} +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvSetCursor -win $_nWave2 399173.297014 -snap {("G1" 11)} +wvSetCursor -win $_nWave2 400680.248703 -snap {("G1" 11)} +wvSetCursor -win $_nWave2 401313.489040 -snap {("G1" 11)} +srcHBSelect "TB.U_digital_top" -win $_nTrace1 +srcHBSelect "TB.U_digital_top.U0_channel_top" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U0_channel_top" -delim "." +srcHBSelect "TB.U_digital_top.U0_channel_top" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "xy_dsp_dout_vld" -line 588 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +wvSetCursor -win $_nWave2 403341.461260 -snap {("G1" 7)} +wvSetCursor -win $_nWave2 402668.142420 -snap {("G1" 7)} +wvSetCursor -win $_nWave2 403329.437709 -snap {("G1" 7)} +wvSetCursor -win $_nWave2 402672.150271 -snap {("G1" 7)} +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.U_awg_ctrl" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U0_channel_top.U_awg_top.U_awg_ctrl" \ + -delim "." +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.U_awg_ctrl" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "enve_rden_o" -line 94 -pos 1 -win $_nTrace1 +srcSelect -signal "enve_rdaddr_o" -line 95 -pos 1 -win $_nTrace1 +srcSelect -signal "enve_rddata_i" -line 96 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +wvSelectSignal -win $_nWave2 {( "G1" 15 )} +wvSelectSignal -win $_nWave2 {( "G1" 14 )} +wvCut -win $_nWave2 +wvSetPosition -win $_nWave2 {("G2" 0)} +wvSetPosition -win $_nWave2 {("G1" 14)} +wvZoom -win $_nWave2 400535.966094 401309.481190 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvSelectSignal -win $_nWave2 {( "G1" 6 )} +wvSetPosition -win $_nWave2 {("G1" 6)} +wvSetPosition -win $_nWave2 {("G1" 7)} +wvSetPosition -win $_nWave2 {("G1" 10)} +wvSetPosition -win $_nWave2 {("G2" 0)} +wvMoveSelected -win $_nWave2 +wvSetPosition -win $_nWave2 {("G2" 1)} +wvSetPosition -win $_nWave2 {("G2" 1)} +wvZoom -win $_nWave2 400526.189961 401442.745321 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "enve_rden_o" -line 94 -pos 1 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "enve_rdaddr_o" -line 95 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +wvSetCursor -win $_nWave2 400595.084034 -snap {("G1" 12)} +wvSetPosition -win $_nWave2 {("G2" 1)} +wvSetPosition -win $_nWave2 {("G1" 12)} +wvMoveSelected -win $_nWave2 +wvSetPosition -win $_nWave2 {("G1" 12)} +wvSetPosition -win $_nWave2 {("G1" 13)} +srcDeselectAll -win $_nTrace1 +srcSelect -signal "enve_start_addr_i" -line 89 -pos 1 -win $_nTrace1 +srcSelect -signal "enve_index_vld_i" -line 88 -pos 1 -win $_nTrace1 +srcSelect -signal "enve_len_i" -line 90 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.enve_dpram" -win $_nTrace1 +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.enve_dpram" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U0_channel_top.U_awg_top.enve_dpram" \ + -delim "." +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.enve_dpram" -win $_nTrace1 +srcSelect -signal "PortBAddr" -line 78 -pos 2 -win $_nTrace1 +srcSelect -signal "PortADataOut" -line 77 -pos 2 -win $_nTrace1 +srcSelect -toggle -signal "PortADataOut" -line 77 -pos 2 -win $_nTrace1 +srcSelect -signal "PortBDataIn" -line 79 -pos 2 -win $_nTrace1 +srcSelect -signal "PortBWriteEnable" -line 80 -pos 2 -win $_nTrace1 +srcSelect -signal "PortBChipEnable" -line 81 -pos 2 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 230580.128255 326308.340346 +wvScrollDown -win $_nWave2 1 +wvZoom -win $_nWave2 241490.172826 243867.458802 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +srcDeselectAll -win $_nTrace1 +debReload +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomOut -win $_nWave2 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollDown -win $_nWave2 0 +wvZoomIn -win $_nWave2 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvSelectSignal -win $_nWave2 {( "G1" 6 )} +wvSetCursor -win $_nWave2 9736100.393815 -snap {("G1" 6)} +wvZoom -win $_nWave2 9736007.621680 9737449.806698 +wvZoomOut -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomOut -win $_nWave2 +wvSetCursor -win $_nWave2 9728286.655546 -snap {("G1" 6)} +wvSelectSignal -win $_nWave2 {( "G1" 5 )} +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 0 +wvSelectSignal -win $_nWave2 {( "G1" 21 )} +wvCut -win $_nWave2 +wvSetPosition -win $_nWave2 {("G1" 20)} +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 0 +wvZoom -win $_nWave2 9725298.678426 9726485.683035 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 9726919.689819 9732983.677889 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 9727687.436424 9733151.748512 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 9717654.184007 9724012.656254 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 9710067.722994 9714421.373172 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 9774396.524365 9799356.164939 +wvZoomOut -win $_nWave2 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 0 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 0 +wvZoomIn -win $_nWave2 +wvZoom -win $_nWave2 9786483.410177 9787988.736615 +wvZoom -win $_nWave2 9786971.389611 9787466.712102 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +srcDeselectAll -win $_nTrace1 +debReload +srcHBSelect "TB.U_digital_top.U0_channel_top" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U0_channel_top" -delim "." +srcHBSelect "TB.U_digital_top.U0_channel_top" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +debReload +srcDeselectAll -win $_nTrace1 +debReload +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 9751286.973534 9756572.756427 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 9760263.428340 9764342.036869 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 9785482.975135 9792138.974863 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 9794354.197833 9798037.873070 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 9811002.612991 9816177.727471 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 9827671.989499 9834611.921289 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 9845655.799440 9849447.371930 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 9854203.231260 9857202.861115 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 9862572.265066 9865200.765550 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoom -win $_nWave2 9856025.492128 9856790.146814 +wvSetCursor -win $_nWave2 9856274.725473 -snap {("G1" 1)} +wvSetCursor -win $_nWave2 9856285.237355 -snap {("G1" 1)} +wvSetCursor -win $_nWave2 9856295.749238 -snap {("G1" 1)} +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvSelectSignal -win $_nWave2 {( "G1" 1 )} +wvChangeDisplayAttr -win $_nWave2 -c ID_YELLOW6 -lw 1 -ls solid +wvChangeDisplayAttr -win $_nWave2 -c ID_ORANGE5 -lw 1 -ls solid +wvChangeDisplayAttr -win $_nWave2 -c ID_RED5 -lw 1 -ls solid +wvChangeDisplayAttr -win $_nWave2 -c ID_RED8 -lw 1 -ls solid +wvChangeDisplayAttr -win $_nWave2 -c ID_GREEN4 -lw 1 -ls solid +wvChangeDisplayAttr -win $_nWave2 -c ID_YELLOW4 -lw 1 -ls solid +wvChangeDisplayAttr -win $_nWave2 -c ID_ORANGE5 -lw 1 -ls solid +wvChangeDisplayAttr -win $_nWave2 -c ID_RED3 -lw 1 -ls solid +wvSetCursor -win $_nWave2 9841596.237782 -snap {("G1" 3)} +wvSetCursor -win $_nWave2 9839556.254370 -snap {("G1" 5)} +wvSelectSignal -win $_nWave2 {( "G1" 1 )} +wvSetCursor -win $_nWave2 9840185.610955 -snap {("G1" 1)} +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomIn -win $_nWave2 +wvSetCursor -win $_nWave2 9843788.134853 -snap {("G1" 5)} +wvSelectSignal -win $_nWave2 {( "G1" 3 )} +wvSetCursor -win $_nWave2 9839209.023151 -snap {("G1" 5)} +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomOut -win $_nWave2 +srcHBSelect "TB.U_digital_top.U0_channel_top.U_DTCM" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +debReload diff --git a/tb/chip_top/verdiLog/verdi_perf_err.log b/tb/chip_top/verdiLog/verdi_perf_err.log new file mode 100644 index 0000000..e69de29 diff --git a/tb/chip_top/verdplus.log b/tb/chip_top/verdplus.log new file mode 100644 index 0000000..258a6e6 --- /dev/null +++ b/tb/chip_top/verdplus.log @@ -0,0 +1,2 @@ +File Name Time +./verdplus_000.fsdb 0 to 3,202,992,000 diff --git a/tb/chip_top/verdplus.vf b/tb/chip_top/verdplus.vf new file mode 100644 index 0000000..1ef6a51 --- /dev/null +++ b/tb/chip_top/verdplus.vf @@ -0,0 +1,7 @@ +@FSDB rc file Version 1.0 +[VRTL_FILE_HEADER] +# !! DON'T EDIT [VRTL_FILE_HEADER] SESSION !! +Version = 1 +[VRTL_FILE_SOURCE] +FileType = switch +File1 = ./verdplus_000.fsdb diff --git a/tb/chip_top/verdplus_000.fsdb b/tb/chip_top/verdplus_000.fsdb new file mode 100644 index 0000000..4943830 Binary files /dev/null and b/tb/chip_top/verdplus_000.fsdb differ diff --git a/tb/chip_top/verdplus_001.fsdb b/tb/chip_top/verdplus_001.fsdb new file mode 100644 index 0000000..d76bb51 Binary files /dev/null and b/tb/chip_top/verdplus_001.fsdb differ diff --git a/tb/chip_top/xy_data.dat b/tb/chip_top/xy_data.dat new file mode 100644 index 0000000..38c33ad --- /dev/null +++ b/tb/chip_top/xy_data.dat @@ -0,0 +1,68160 @@ +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32813 +32795 +32618 +33041 +32428 +33075 +32594 +32749 +32973 +32450 +33092 +32533 +32874 +32758 +32768 +32873 +32614 +32852 +32885 +32366 +33447 +31928 +33575 +32212 +32897 +33146 +31920 +33951 +31446 +34018 +31776 +33588 +31552 +34258 +31162 +34296 +31542 +33460 +32809 +31885 +34473 +30423 +35424 +30225 +34757 +31707 +32669 +29594 +35916 +30123 +34494 +32262 +31909 +34961 +29461 +36790 +28571 +36516 +30088 +33874 +33535 +30114 +37015 +36527 +30728 +32682 +35069 +28505 +38430 +26501 +38726 +28028 +35523 +32513 +30352 +37632 +26065 +40380 +25374 +34322 +28242 +39697 +24411 +41313 +25352 +37871 +30843 +31114 +37869 +24881 +42339 +22909 +41427 +26671 +35280 +22805 +43655 +22602 +40619 +28522 +32639 +37382 +24256 +43969 +20537 +44174 +23958 +37571 +32800 +27792 +42045 +43332 +25998 +34615 +36245 +24375 +44898 +18688 +46669 +21198 +40178 +30741 +29007 +41836 +19703 +47885 +17887 +34677 +25070 +45164 +17504 +48604 +18781 +42731 +28416 +30762 +40909 +19670 +48866 +16118 +47415 +22398 +37229 +16997 +49929 +16839 +45017 +26101 +32794 +39437 +20380 +49018 +15122 +49113 +20240 +39536 +32828 +25863 +45483 +46910 +23913 +34971 +37562 +21706 +48413 +14932 +50074 +18634 +41573 +30635 +27906 +43877 +17118 +50558 +15565 +35394 +23584 +47080 +15541 +50266 +17671 +43178 +28600 +30104 +41813 +18764 +49570 +15745 +47424 +22691 +36770 +16955 +49629 +17439 +44246 +26848 +32296 +39482 +20914 +47894 +16708 +47319 +21904 +38359 +33217 +26436 +43941 +44613 +25560 +34319 +37019 +23455 +45647 +18341 +46529 +21741 +39454 +31337 +28848 +41327 +20961 +45980 +20160 +34721 +26150 +42956 +20615 +45022 +22253 +40007 +29811 +31111 +38664 +23642 +43657 +21803 +42170 +26276 +35490 +23226 +42932 +23498 +39814 +28906 +32984 +36113 +26472 +40987 +23911 +40922 +26509 +36272 +32428 +30032 +38031 +39041 +28707 +34141 +34145 +28981 +38304 +26360 +39093 +27427 +36399 +31300 +31950 +35653 +28339 +38008 +27544 +32759 +30894 +36120 +28537 +37200 +28783 +35784 +31063 +33028 +33891 +30502 +35805 +29420 +35941 +30220 +34347 +30407 +35559 +30011 +35065 +31246 +33363 +33080 +31715 +34312 +31013 +34480 +31299 +33852 +32155 +32868 +33173 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32768 +32684 +32811 +32836 +32557 +33097 +32403 +33060 +32639 +32700 +32997 +32469 +33032 +32611 +32815 +32768 +32656 +32974 +32564 +32831 +32974 +32236 +33577 +31835 +33608 +32239 +32832 +33222 +31855 +33996 +31418 +34044 +32433 +33595 +31518 +34329 +31060 +34410 +31448 +33504 +32831 +31796 +34605 +30281 +35545 +30146 +34787 +31721 +35600 +29502 +35997 +30055 +34541 +32247 +31878 +35045 +29330 +36951 +28412 +36637 +30031 +33853 +33630 +29967 +27835 +36573 +30746 +32608 +35185 +28364 +38581 +26356 +38848 +27948 +35541 +32568 +30227 +37813 +25860 +40572 +34212 +34466 +28048 +39906 +24224 +41450 +25284 +37863 +30923 +30973 +38051 +24681 +42529 +22757 +41512 +26671 +40589 +22582 +43833 +22503 +40620 +28621 +32459 +37611 +24018 +44178 +20388 +44241 +23982 +37462 +32982 +27564 +19979 +43339 +26090 +34435 +36487 +24112 +45137 +18514 +46746 +21230 +40040 +30957 +28747 +42098 +19483 +48032 +36653 +34929 +24803 +45404 +17329 +48685 +18811 +42593 +28644 +30481 +41194 +19428 +49022 +16071 +47343 +22574 +45007 +16829 +49993 +16886 +44867 +26333 +32515 +39718 +20140 +49177 +15071 +49044 +20419 +39276 +33126 +25577 +15573 +46741 +24164 +34680 +37846 +21473 +48556 +14897 +49995 +18816 +41316 +30927 +27626 +44100 +16991 +50567 +36830 +35683 +23351 +47218 +15519 +50170 +17868 +42914 +28887 +29838 +42016 +18654 +49568 +15855 +47221 +22957 +45228 +16932 +49536 +17634 +43982 +27136 +32032 +39677 +20820 +47877 +16832 +47113 +22159 +38095 +33449 +26269 +18212 +44374 +25825 +34072 +37208 +23355 +45636 +18460 +46324 +21996 +39193 +31559 +28700 +41379 +21009 +45843 +35675 +34876 +26076 +42940 +20719 +44846 +22478 +39770 +30022 +30962 +38723 +23684 +43522 +22005 +41938 +26496 +40173 +23343 +42758 +23699 +39616 +29075 +32866 +36164 +26495 +40890 +24072 +40722 +26716 +36093 +32545 +30000 +25339 +38839 +28871 +34040 +34170 +29028 +38200 +26499 +38940 +27576 +36269 +31397 +31900 +35645 +28411 +37878 +34656 +32827 +30904 +36034 +28680 +37032 +28940 +35667 +31127 +33018 +33857 +30565 +35725 +29510 +35844 +30319 +34282 +30457 +35463 +30141 +34925 +31365 +33296 +33079 +31779 +34205 +31130 +34382 +31360 +33829 +32154 +32878 diff --git a/tb/dacreg_tb/dac_refmodel.sv b/tb/dacreg_tb/dac_refmodel.sv new file mode 100644 index 0000000..6699c9a --- /dev/null +++ b/tb/dacreg_tb/dac_refmodel.sv @@ -0,0 +1,252 @@ +//For dac_regfile +class dac_refmodel; + + virtual dacreg_if dif; + virtual spi_if wif; + virtual sram_if#(25,32) xif; + + //poor-quality register model + bit[31:0] rm[29]; + bit[31:0] update_rm[29]; + + //members to be sent to scoreboard + int rst_error[5]; + bit[31:0] dout[$]; + dacreg_trans dacout[$]; + + + + function new(); + endfunction + extern task do_imitate(); + extern task RWreg_write (bit[24:0] addr,bit[32:0] din ); + extern task ROreg_update (bit[24:0] addr ); + extern task reg_read (bit[24:0] addr ); + extern task rst_check (bit[31:0] rst_time,int i ); + extern task output_trace (bit[24:0] addr ); + +endclass : dac_refmodel + +task dac_refmodel::do_imitate(); + + int i=0,j=0; + + rm[ 0] = 32'h0; //PRBSCR 16'h0000 + rm[ 1] = 32'h0000413E; //SET0CR 16'h0004 + rm[ 2] = 32'h00003910; //SET1CR 16'h0008 + rm[ 3] = 32'h0000780F; //SET2CR 16'h000C + rm[ 4] = 32'h00000AD4; //SET3CR 16'h0010 + rm[ 5] = 32'h00000569; //SET4CR 16'h0014 + rm[ 6] = 32'h00006F31; //SET5CR 16'h0018 + rm[ 7] = 32'h00005A38; //SET6CR 16'h001C + rm[ 8] = 32'h00005660; //SET7CR 16'h0020 + rm[ 9] = 32'h00004F83; //SET8CR 16'h0024 + rm[10] = 32'h00002E95; //SET9CR 16'h0028 + rm[11] = 32'h00005417; //SET10CR 16'h002C + rm[12] = 32'h000016DE; //SET11CR 16'h0030 + rm[13] = 32'h00000EE9; //SET12CR 16'h0034 + rm[14] = 32'h0000169C; //SET13CR 16'h0038 + rm[15] = 32'h00001135; //SET14CR 16'h003C + rm[16] = 32'h00005DD1; //SET15CR 16'h0040 + rm[17] = 32'h0; //DACADDR 16'h0044 + rm[18] = 32'h0; //DACDW 16'h0048 + rm[19] = 32'h00000088; //DACREF 16'h004C + rm[20] = 32'h000001FF; //PRBSRST0 16'h0050 + rm[21] = 32'h0001FE00; //PRBSSET0 16'h0054 + rm[22] = 32'h000000FF; //PRBSRST1 16'h0058 + rm[23] = 32'h0001FF00; //PRBSSET1 16'h005C + rm[24] = 32'h0; //PRBSREV 16'h0060 + rm[25] = 32'h0; //CALSIG 16'h0064 + rm[26] = 32'h0; //CALEND 16'h0068 + rm[27] = 32'h0; //CALRSTN 16'h006C + rm[28] = 32'h00000001; //CALDIVRSTN 16'h0070 + + + + fork + + + while(1) begin: write_reg_RW + + @(negedge xif.wren); + + RWreg_write(xif.addr,xif.din); + + end: write_reg_RW + + + + while(1) begin: update_reg_RO + + ROreg_update(xif.addr); + + end: update_reg_RO + + + while(1) begin: read_reg + + @(negedge xif.rden); + repeat(3) @(posedge xif.clk); + + reg_read(xif.addr); + + end: read_reg + + + while(1) begin: dbg_port + + @(negedge xif.wren); + + output_trace(xif.addr); + + end: dbg_port + + + join + +endtask: do_imitate + + + +task dac_refmodel::RWreg_write(bit[24:0] addr,bit[32:0] din); + + //delay caused by decoder + @(posedge wif.clk); + + case(addr[24: 2]) + 23'h180000: rm[ 0] = {rm[ 0][31: 1],din[0 : 0]}; //PRBSCR 16'h0000 + 23'h180001: rm[ 1] = {rm[ 1][31:15],din[14: 0]}; //SET0CR 16'h0004 + 23'h180002: rm[ 2] = {rm[ 2][31:15],din[14: 0]}; //SET1CR 16'h0008 + 23'h180003: rm[ 3] = {rm[ 3][31:15],din[14: 0]}; //SET2CR 16'h000C + 23'h180004: rm[ 4] = {rm[ 4][31:15],din[14: 0]}; //SET3CR 16'h0010 + 23'h180005: rm[ 5] = {rm[ 5][31:15],din[14: 0]}; //SET4CR 16'h0014 + 23'h180006: rm[ 6] = {rm[ 6][31:15],din[14: 0]}; //SET5CR 16'h0018 + 23'h180007: rm[ 7] = {rm[ 7][31:15],din[14: 0]}; //SET6CR 16'h001C + 23'h180008: rm[ 8] = {rm[ 8][31:15],din[14: 0]}; //SET7CR 16'h0020 + 23'h180009: rm[ 9] = {rm[ 9][31:15],din[14: 0]}; //SET8CR 16'h0024 + 23'h18000a: rm[10] = {rm[10][31:15],din[14: 0]}; //SET9CR 16'h0028 + 23'h18000b: rm[11] = {rm[11][31:15],din[14: 0]}; //SET10CR 16'h002C + 23'h18000c: rm[12] = {rm[12][31:15],din[14: 0]}; //SET11CR 16'h0030 + 23'h18000d: rm[13] = {rm[13][31:15],din[14: 0]}; //SET12CR 16'h0034 + 23'h18000e: rm[14] = {rm[14][31:15],din[14: 0]}; //SET13CR 16'h0038 + 23'h18000f: rm[15] = {rm[15][31:15],din[14: 0]}; //SET14CR 16'h003C + 23'h180010: rm[16] = {rm[16][31:15],din[14: 0]}; //SET15CR 16'h0040 + 23'h180011: rm[17] = {rm[17][31: 3],din[ 2: 0]}; //DACADDR 16'h0044 + 23'h180012: rm[18] = {rm[18][31: 3],din[ 2: 0]}; //DACDW 16'h0048 + 23'h180013: rm[19] = {rm[19][31: 9],din[ 8: 0]}; //DACREF 16'h004C + 23'h180014: rm[20] = {rm[20][31:17],din[16: 0]}; //PRBSRST0 16'h0050 + 23'h180015: rm[21] = {rm[21][31:17],din[16: 0]}; //PRBSSET0 16'h0054 + 23'h180016: rm[22] = {rm[22][31:17],din[16: 0]}; //PRBSRST1 16'h0058 + 23'h180017: rm[23] = {rm[23][31:17],din[16: 0]}; //PRBSSET1 16'h005C + 23'h180018:begin //PRBSREV 16'h0060 + rm[20] = 0; //PRBSRST0 16'h0050 + rm[21] = 0; //PRBSSET0 16'h0054 + rm[22] = 0; //PRBSRST1 16'h0058 + rm[23] = 0; //PRBSSET1 16'h005C + end + 23'h180019: rm[25] = {rm[25][31: 1],din[ 0: 0]}; //CALSIG 16'h0064 + 23'h18001b: rm[27] = {rm[27][31: 1],din[ 0: 0]}; //CALRSTN 16'h006C + 23'h18001c: rm[28] = {rm[28][31: 1],din[ 0: 0]}; //CALDIVRSTN 16'h0070 + + endcase +// $display("addr:%0h",addr); +// $display("rm:%h",rm[addr[15: 2]]); +// $display("din:%h",din); + +endtask: RWreg_write + + + +task dac_refmodel::ROreg_update(bit[24:0] addr); + + @(posedge wif.clk); + update_rm[26] = dif.Cal_end; //CALEND 16'h0068 +endtask: ROreg_update + + +task dac_refmodel::reg_read(bit[24:0] addr); + + @(posedge wif.clk); + case(addr[24: 2]) + 23'h180000: dout.push_back(rm[ 0]); //PRBSCR 16'h0000 + 23'h180001: dout.push_back(rm[ 1]); //SET0CR 16'h0004 + 23'h180002: dout.push_back(rm[ 2]); //SET1CR 16'h0008 + 23'h180003: dout.push_back(rm[ 3]); //SET2CR 16'h000C + 23'h180004: dout.push_back(rm[ 4]); //SET3CR 16'h0010 + 23'h180005: dout.push_back(rm[ 5]); //SET4CR 16'h0014 + 23'h180006: dout.push_back(rm[ 6]); //SET5CR 16'h0018 + 23'h180007: dout.push_back(rm[ 7]); //SET6CR 16'h001C + 23'h180008: dout.push_back(rm[ 8]); //SET7CR 16'h0020 + 23'h180009: dout.push_back(rm[ 9]); //SET8CR 16'h0024 + 23'h18000a: dout.push_back(rm[10]); //SET9CR 16'h0028 + 23'h18000b: dout.push_back(rm[11]); //SET10CR 16'h002C + 23'h18000c: dout.push_back(rm[12]); //SET11CR 16'h0030 + 23'h18000d: dout.push_back(rm[13]); //SET12CR 16'h0034 + 23'h18000e: dout.push_back(rm[14]); //SET13CR 16'h0038 + 23'h18000f: dout.push_back(rm[15]); //SET14CR 16'h003C + 23'h180010: dout.push_back(rm[16]); //SET15CR 16'h0040 + 23'h180011: dout.push_back(rm[17]); //DACADDR 16'h0044 + 23'h180012: dout.push_back(rm[18]); //DACDW 16'h0048 + 23'h180013: dout.push_back(rm[19]); //DACREF 16'h004C + 23'h180014: dout.push_back(rm[20]); //PRBSRST0 16'h0050 + 23'h180015: dout.push_back(rm[21]); //PRBSSET0 16'h0054 + 23'h180016: dout.push_back(rm[22]); //PRBSRST1 16'h0058 + 23'h180017: dout.push_back(rm[23]); //PRBSSET1 16'h005C + 23'h180018: dout.push_back(rm[24]); //PRBSREV 16'h0060 + 23'h180019: dout.push_back(rm[25]); //CALSIG 16'h0064 + 23'h18001a: dout.push_back(update_rm[26]); //CALEND 16'h0068 + 23'h18001b: dout.push_back(rm[27]); //CALRSTN 16'h006C + 23'h18001c: dout.push_back(rm[28]); //CALDIVRSTN 16'h0070 + 23'h18001d: dout.push_back(0); + endcase +// $display("dout:%h",dout[$]); + +endtask: reg_read + + +task dac_refmodel::output_trace(bit[24:0] addr); + +dacreg_trans tr_temp; + + //delay caused by decoder + @(posedge wif.clk); + @(negedge wif.clk); +// @(negedge wif.clk); + tr_temp = new(); + if(addr[24:20] == 5'h6) + begin + tr_temp.Prbs = rm[ 0][0 : 0]; //PRBSCR 16'h0000 + tr_temp.Set0 = rm[ 1][14: 0]; //SET0CR 16'h0004 + tr_temp.Set1 = rm[ 2][14: 0]; //SET1CR 16'h0008 + tr_temp.Set2 = rm[ 3][14: 0]; //SET2CR 16'h000C + tr_temp.Set3 = rm[ 4][14: 0]; //SET3CR 16'h0010 + tr_temp.Set4 = rm[ 5][14: 0]; //SET4CR 16'h0014 + tr_temp.Set5 = rm[ 6][14: 0]; //SET5CR 16'h0018 + tr_temp.Set6 = rm[ 7][14: 0]; //SET6CR 16'h001C + tr_temp.Set7 = rm[ 8][14: 0]; //SET7CR 16'h0020 + tr_temp.Set8 = rm[ 9][14: 0]; //SET8CR 16'h0024 + tr_temp.Set9 = rm[10][14: 0]; //SET9CR 16'h0028 + tr_temp.Set10 = rm[11][14: 0]; //SET10CR 16'h002C + tr_temp.Set11 = rm[12][14: 0]; //SET11CR 16'h0030 + tr_temp.Set12 = rm[13][14: 0]; //SET12CR 16'h0034 + tr_temp.Set13 = rm[14][14: 0]; //SET13CR 16'h0038 + tr_temp.Set14 = rm[15][14: 0]; //SET14CR 16'h003C + tr_temp.Set15 = rm[16][14: 0]; //SET15CR 16'h0040 + tr_temp.Dac_addr = rm[17][ 2: 0]; //DACADDR 16'h0044 + tr_temp.Dac_dw = rm[18][ 2: 0]; //DACDW 16'h0048 + tr_temp.Dac_ref = rm[19][ 8: 0]; //DACREF 16'h004C + tr_temp.Prbs_rst0 = rm[20][16: 0]; //PRBSRST0 16'h0050 + tr_temp.Prbs_set0 = rm[21][16: 0]; //PRBSSET0 16'h0054 + tr_temp.Prbs_rst1 = rm[22][16: 0]; //PRBSRST1 16'h0058 + tr_temp.Prbs_set1 = rm[23][16: 0]; //PRBSSET1 16'h005C + tr_temp.Cal_sig = rm[25][14: 0]; //CALSIG 16'h0060 + tr_temp.Cal_rstn = rm[27][14: 0]; //CALRSTN 16'h006C + tr_temp.Cal_div_rstn = rm[28][14: 0]; //CALDIVRSTN 16'h0070 + + dacout.push_back(tr_temp); + end + //$display("addr:%0h",addr); + //$display("rm[%0h]:%0h",addr[15:2],rm[addr[15:2]]); + //$display("din:%h",din); + +endtask: output_trace diff --git a/tb/dacreg_tb/dacreg_driver.sv b/tb/dacreg_tb/dacreg_driver.sv new file mode 100644 index 0000000..e84f52a --- /dev/null +++ b/tb/dacreg_tb/dacreg_driver.sv @@ -0,0 +1,53 @@ +class dacreg_driver; + + + dacreg_trans tr; + + //interface + virtual dacreg_if dif; + virtual spi_if wif; + + + function new(); + endfunction + extern task do_drive(); + extern task make_pkt(); + +endclass : dacreg_driver + +task dacreg_driver::do_drive(); + + fork + + while(1) begin + make_pkt(); + end + + join + +endtask + +task dacreg_driver::make_pkt(); + int cnt=0; + + + cnt = 0; + + + tr = new(); + if(!tr.randomize()) + $fatal(0,"Randomize Failed"); + + + while(cnt<3000) begin + @(posedge wif.clk); + + cnt = cnt + 1; + + case(cnt) + tr.Cal_end: dif.Cal_end <=tr.Cal_end; + endcase + + end + +endtask : make_pkt diff --git a/tb/dacreg_tb/dacreg_env.sv b/tb/dacreg_tb/dacreg_env.sv new file mode 100644 index 0000000..d1ac3e1 --- /dev/null +++ b/tb/dacreg_tb/dacreg_env.sv @@ -0,0 +1,107 @@ +class sysreg_env; + + + static int pktnum; + + //Interface: + virtual dacreg_if dif; + virtual spi_if wif; + virtual sram_if#(25,32) xif; + + //Component: + spi_driver w_driver; + dac_driver d_driver; + spi_monitor w_monitor; + dac_refmodel d_model; + dacreg_monitor d_monitor; + dacreg_scoreboard d_scb; + + + function new(); + endfunction; + + extern function build(); + + extern task run(); + +endclass + +function dacreg_env::build(); + + w_driver = new(); + if(!w_driver.randomize() with { + error_time < 0; + }) + $fatal(0,"Randomize Failed"); + w_driver.pktnum = pktnum; + w_driver.vif = wif; + w_driver.autarchy = 1'b1; + w_driver.half_sclk = 4; + + w_monitor = new(); + w_monitor.wif = wif; + w_monitor.xif = xif; + + d_driver = new(); + d_driver.dif = dif; + d_driver.wif = wif; + + d_monitor = new(); + d_monitor.dif = dif; + d_monitor.xif = xif; + + d_model = new(); + d_model.dif = dif; + d_model.wif = wif; + d_model.xif = xif; + + s_scb = new(); + +endfunction + + +task sysreg_env::run(); + int error=0; + + fork + + w_driver.do_drive(); + + d_driver.do_drive(); + + w_monitor.do_mon(); + + d_monitor.do_mon(); + + d_model.do_imitate(); + + + while(1) begin + repeat(2) @(posedge wif.csn); + @(posedge wif.clk); + s_model.dout.pop_back(); + if(s_scb.compare( + d_model.dout , + w_monitor.act_trans.data , + d_model.dacout , + d_monitor.act_trans + )) + error++; + d_model.dout.delete(); + d_model.dacout.delete(); + d_monitor.act_trans.delete(); + end + + + join + + $display("SCOREBOARD:"); + $display("\tError_isr:\t%0d",error); + $display("\tError_sysrst:\t%0d",s_model.rst_error[0]); + $display("\tError_ch0rst:\t%0d",s_model.rst_error[1]); + $display("\tError_ch1rst:\t%0d",s_model.rst_error[2]); + $display("\tError_ch2rst:\t%0d",s_model.rst_error[3]); + $display("\tError_ch3rst:\t%0d",s_model.rst_error[4]); + +endtask + diff --git a/tb/dacreg_tb/dacreg_if.sv b/tb/dacreg_tb/dacreg_if.sv new file mode 100644 index 0000000..f508504 --- /dev/null +++ b/tb/dacreg_tb/dacreg_if.sv @@ -0,0 +1,38 @@ + + +interface dacreg_if(input clk,input rstn); +//input port + logic Cal_end ; +//output port + logic Prbs ; + logic [14 :0] Set0 ; + logic [14 :0] Set1 ; + logic [14 :0] Set2 ; + logic [14 :0] Set3 ; + logic [14 :0] Set4 ; + logic [14 :0] Set5 ; + logic [14 :0] Set6 ; + logic [14 :0] Set7 ; + logic [14 :0] Set8 ; + logic [14 :0] Set9 ; + logic [14 :0] Set10 ; + logic [14 :0] Set11 ; + logic [14 :0] Set12 ; + logic [14 :0] Set13 ; + logic [14 :0] Set14 ; + logic [14 :0] Set15 ; + logic [2 :0] Dac_addr ; + logic [2 :0] Dac_dw ; + logic [8 :0] Dac_ref ; + logic [16 :0] Prbs_rst0 ; + logic [16 :0] Prbs_set0 ; + logic [16 :0] Prbs_rst1 ; + logic [16 :0] Prbs_set1 ; + logic Cal_sig ; + logic Cal_rstn ; + logic Cal_div_rstn; + +endinterface : dacreg_if + + + diff --git a/tb/dacreg_tb/dacreg_monitor.sv b/tb/dacreg_tb/dacreg_monitor.sv new file mode 100644 index 0000000..8aba502 --- /dev/null +++ b/tb/dacreg_tb/dacreg_monitor.sv @@ -0,0 +1,69 @@ +class dacreg_monitor; + + + virtual dacreg_if dif; + virtual spi_if wif; + virtual sram_if#(25,32) xif; + + //collect + dacreg_trans act_trans[$]; + + + function new(); + endfunction + extern task collect(); + extern task do_mon(); + +endclass : dacreg_monitor + + +task dacreg_monitor::do_mon(); + + while(1) begin + @(negedge xif.wren); + collect(); + end + +endtask: do_mon + + + + +task dacreg_monitor::collect(); + dacreg_trans tr_temp; + + @(posedge xif.clk); + @(negedge xif.clk); + + tr_temp = new(); + tr_temp.Prbs = dif.Prbs ; + tr_temp.Set0 = dif.Set0 ; + tr_temp.Set1 = dif.Set1 ; + tr_temp.Set2 = dif.Set2 ; + tr_temp.Set3 = dif.Set3 ; + tr_temp.Set4 = dif.Set4 ; + tr_temp.Set5 = dif.Set5 ; + tr_temp.Set6 = dif.Set6 ; + tr_temp.Set7 = dif.Set7 ; + tr_temp.Set8 = dif.Set8 ; + tr_temp.Set9 = dif.Set9 ; + tr_temp.Set10 = dif.Set10 ; + tr_temp.Set11 = dif.Set11 ; + tr_temp.Set12 = dif.Set12 ; + tr_temp.Set13 = dif.Set13 ; + tr_temp.Set14 = dif.Set14 ; + tr_temp.Set15 = dif.Set15 ; + tr_temp.Dac_addr = dif.Dac_addr ; + tr_temp.Dac_dw = dif.Dac_dw ; + tr_temp.Dac_ref = dif.Dac_ref ; + tr_temp.Prbs_rst0 = dif.Prbs_rst0 ; + tr_temp.Prbs_set0 = dif.Prbs_set0 ; + tr_temp.Prbs_rst1 = dif.Prbs_rst1 ; + tr_temp.Prbs_set1 = dif.Prbs_set1 ; + tr_temp.Cal_sig = dif.Cal_sig ; + tr_temp.Cal_rstn = dif.Cal_rstn ; + tr_temp.Cal_div_rstn = dif.Cal_div_rstn; + + act_trans.push_back(tr_temp); + +endtask: collect diff --git a/tb/dacreg_tb/dacreg_scb.sv b/tb/dacreg_tb/dacreg_scb.sv new file mode 100644 index 0000000..137a310 --- /dev/null +++ b/tb/dacreg_tb/dacreg_scb.sv @@ -0,0 +1,93 @@ +class dacreg_scoreboard; + + //Vars in intr_check + integer fid; + + function new(); + endfunction; + + //extern task do_check(); + + extern function bit compare( + bit[31:0] spi_exp[$], + bit[31:0] spi_act[$], + dacreg_trans dac_exp[$], + dacreg_trans dac_act[$] + ); + +endclass + +function bit dacreg_scoreboard::compare( + bit[31:0] spi_exp[$], + bit[31:0] spi_act[$], + dacreg_trans dac_exp[$], + dacreg_trans dac_act[$] +); + + bit result=1'b1; + int i=0; + +//$display(dout); + + if(spi_exp.size() != spi_act.size()) begin + result = 1'b0; + //$display("ScoreBoard(ERROR): write & read datanum ARNT'T equal!"); + //$display("Exp spi_data size:%0d",spi_exp.size()); + //$display("Act spi_data size:%0d",spi_act.size()); + $fwrite(fid,"ScoreBoard(ERROR): write & read datanum ARNT'T equal!\t@%t\n",$realtime); + $fwrite(fid,"Exp spi_data size:%0d\n",spi_exp.size()); + $fwrite(fid,"Act spi_data size:%0d\n",spi_act.size()); + end + + else if(dac_exp.size() != dac_act.size()) begin + result = 1'b0; + //$display("ScoreBoard(ERROR): regmdl & read datanum ARNT'T equal!"); + //$display("Exp dac_trs size:%0d",dac_exp.size()); + //$display("Act dac_trs size:%0d",dac_act.size()); + $fwrite(fid,"ScoreBoard(ERROR): regmdl & read datanum ARNT'T equal!\t@%t\n",$realtime); + $fwrite(fid,"Exp dac_trs size:%0d\n",dac_exp.size()); + $fwrite(fid,"Act dac_trs size:%0d\n",dac_act.size()); + end + + + else + for(i=0;i= 0 ; + Cal_end <= 5000 ; + +} + + function new(); + + endfunction + + function bit[26:0] compare(dacreg_trans tr); + + bit[26:0] result = 27'b0; + + if(tr.Prbs != Prbs ) result[ 0]=1'b1; + if(tr.Set0 != Set0 ) result[ 1]=1'b1; + if(tr.Set1 != Set1 ) result[ 2]=1'b1; + if(tr.Set2 != Set2 ) result[ 3]=1'b1; + if(tr.Set3 != Set3 ) result[ 4]=1'b1; + if(tr.Set4 != Set4 ) result[ 5]=1'b1; + if(tr.Set5 != Set5 ) result[ 6]=1'b1; + if(tr.Set6 != Set6 ) result[ 7]=1'b1; + if(tr.Set7 != Set7 ) result[ 8]=1'b1; + if(tr.Set8 != Set8 ) result[ 9]=1'b1; + if(tr.Set9 != Set9 ) result[10]=1'b1; + if(tr.Set10 != Set10 ) result[11]=1'b1; + if(tr.Set11 != Set11 ) result[12]=1'b1; + if(tr.Set12 != Set12 ) result[13]=1'b1; + if(tr.Set13 != Set13 ) result[14]=1'b1; + if(tr.Set14 != Set14 ) result[15]=1'b1; + if(tr.Set15 != Set15 ) result[16]=1'b1; + if(tr.Dac_addr != Dac_addr ) result[17]=1'b1; + if(tr.Dac_dw != Dac_dw ) result[18]=1'b1; + if(tr.Dac_ref != Dac_ref ) result[19]=1'b1; + if(tr.Prbs_rst0 != Prbs_rst0 ) result[20]=1'b1; + if(tr.Prbs_set0 != Prbs_set0 ) result[21]=1'b1; + if(tr.Prbs_rst1 != Prbs_rst1 ) result[22]=1'b1; + if(tr.Prbs_set1 != Prbs_set1 ) result[23]=1'b1; + if(tr.Cal_sig != Cal_sig ) result[24]=1'b1; + if(tr.Cal_rstn != Cal_rstn ) result[25]=1'b1; + if(tr.Cal_div_rstn != Cal_div_rstn) result[26]=1'b1; + + return result; + endfunction + + function print(bit[26:0] ctrl,integer fid); + + if(ctrl[ 0]) $fwrite(fid,"Prbs :\t%h\n", Prbs ); + if(ctrl[ 1]) $fwrite(fid,"Set0 :\t%h\n", Set0 ); + if(ctrl[ 2]) $fwrite(fid,"Set1 :\t%h\n", Set1 ); + if(ctrl[ 3]) $fwrite(fid,"Set2 :\t%h\n", Set2 ); + if(ctrl[ 4]) $fwrite(fid,"Set3 :\t%h\n", Set3 ); + if(ctrl[ 5]) $fwrite(fid,"Set4 :\t%h\n", Set4 ); + if(ctrl[ 6]) $fwrite(fid,"Set5 :\t%h\n", Set5 ); + if(ctrl[ 7]) $fwrite(fid,"Set6 :\t%h\n", Set6 ); + if(ctrl[ 8]) $fwrite(fid,"Set7 :\t%h\n", Set7 ); + if(ctrl[ 9]) $fwrite(fid,"Set8 :\t%h\n", Set8 ); + if(ctrl[10]) $fwrite(fid,"Set9 :\t%h\n", Set9 ); + if(ctrl[11]) $fwrite(fid,"Set10 :\t%h\n", Set10 ); + if(ctrl[12]) $fwrite(fid,"Set11 :\t%h\n", Set11 ); + if(ctrl[13]) $fwrite(fid,"Set12 :\t%h\n", Set12 ); + if(ctrl[14]) $fwrite(fid,"Set13 :\t%h\n", Set13 ); + if(ctrl[15]) $fwrite(fid,"Set14 :\t%h\n", Set14 ); + if(ctrl[16]) $fwrite(fid,"Set15 :\t%h\n", Set15 ); + if(ctrl[17]) $fwrite(fid,"Dac_addr :\t%h\n", Dac_addr ); + if(ctrl[18]) $fwrite(fid,"Dac_dw :\t%h\n", Dac_dw ); + if(ctrl[19]) $fwrite(fid,"Dac_ref :\t%h\n", Dac_ref ); + if(ctrl[20]) $fwrite(fid,"Prbs_rst0 :\t%h\n", Prbs_rst0 ); + if(ctrl[21]) $fwrite(fid,"Prbs_set0 :\t%h\n", Prbs_set0 ); + if(ctrl[22]) $fwrite(fid,"Prbs_rst1 :\t%h\n", Prbs_rst1 ); + if(ctrl[23]) $fwrite(fid,"Prbs_set1 :\t%h\n", Prbs_set1 ); + if(ctrl[24]) $fwrite(fid,"Cal_sig :\t%h\n", Cal_sig ); + if(ctrl[25]) $fwrite(fid,"Cal_rstn :\t%h\n", Cal_rstn ); + if(ctrl[26]) $fwrite(fid,"Cal_div_rstn:\t%h\n", Cal_div_rstn); + + endfunction + +endclass : dacreg_trans + diff --git a/tb/digital_top/DW01_addsub.v b/tb/digital_top/DW01_addsub.v new file mode 100644 index 0000000..a369ca3 --- /dev/null +++ b/tb/digital_top/DW01_addsub.v @@ -0,0 +1,92 @@ +//////////////////////////////////////////////////////////////////////////////// +// +// This confidential and proprietary software may be used only +// as authorized by a licensing agreement from Synopsys Inc. +// In the event of publication, the following notice is applicable: +// +// (C) COPYRIGHT 1992 - 2018 SYNOPSYS INC. +// ALL RIGHTS RESERVED +// +// The entire notice above must be reproduced on all authorized +// copies. +// +// AUTHOR: PS Nov. 8, 1992 +// +// VERSION: Simulation Architecture +// +// DesignWare_version: 22a5618c +// DesignWare_release: O-2018.06-DWBB_201806.3 +// +//////////////////////////////////////////////////////////////////////////////// +//----------------------------------------------------------------------------------- +// +// ABSTRACT: Adder-Subtractor +// ADD_SUB= '1' : SUM <= A - B - CI +// ADD_SUB= '0' : SUM <= A + B + CI +// Carry-in and Carry-out is active high with both addition +// and subtraction. +// MODIFIED: Sheela May 11, 1995 +// Converted to verilog from vhdl +// GN +// changed dw01 to DW01 star 33068 +// +// Bob Tong: 12/02/98 +// STAR 59142 +// +// Bob Tong: 03/03/2000 +// STAR 99907 +// +// RPH 07/17/2002 +// Rewrote to comply with the new guidelines +// +//--------------------------------------------------------------------- + +module DW01_addsub (A,B,CI,ADD_SUB,SUM,CO); + + parameter integer width = 4; + + // port list declaration in order + input [width-1 : 0] A, B; + input CI, ADD_SUB; + + output [width-1 : 0] SUM; + output CO; + + // synopsys translate_off + wire [width : 0] tmp_out; + //------------------------------------------------------------------------- + // Parameter legality check + //------------------------------------------------------------------------- + + + + initial begin : parameter_check + integer param_err_flg; + + param_err_flg = 0; + + + if (width < 1) begin + param_err_flg = 1; + $display( + "ERROR: %m :\n Invalid value (%d) for parameter width (lower bound: 1)", + width ); + end + + if ( param_err_flg == 1) begin + $display( + "%m :\n Simulation aborted due to invalid parameter value(s)"); + $finish; + end + + end // parameter_check + + + assign tmp_out = ((^(A ^ A) !== 1'b0) || (^(B ^ B) !== 1'b0) || (^(ADD_SUB ^ ADD_SUB) !== 1'b0)) ? {width+1{1'bx}} + : ADD_SUB ? A-B-CI : A+B+CI; + assign CO = tmp_out[width]; + assign SUM = tmp_out[width-1 : 0]; + + // synopsys translate_on + +endmodule diff --git a/tb/digital_top/DW02_mult.v b/tb/digital_top/DW02_mult.v new file mode 100644 index 0000000..bdcb182 --- /dev/null +++ b/tb/digital_top/DW02_mult.v @@ -0,0 +1,101 @@ +//////////////////////////////////////////////////////////////////////////////// +// +// This confidential and proprietary software may be used only +// as authorized by a licensing agreement from Synopsys Inc. +// In the event of publication, the following notice is applicable: +// +// (C) COPYRIGHT 1994 - 2018 SYNOPSYS INC. +// ALL RIGHTS RESERVED +// +// The entire notice above must be reproduced on all authorized +// copies. +// +// AUTHOR: KB WSFDB June 30, 1994 +// +// VERSION: Simulation Architecture +// +// DesignWare_version: 714fe7a9 +// DesignWare_release: O-2018.06-DWBB_201806.3 +// +//////////////////////////////////////////////////////////////////////////////// +//----------------------------------------------------------------------------------- +// +// ABSTRACT: Multiplier +// A_width-Bits * B_width-Bits => A_width+B_width Bits +// Operands A and B can be either both signed (two's complement) or +// both unsigned numbers. TC determines the coding of the input operands. +// ie. TC = '1' => signed multiplication +// TC = '0' => unsigned multiplication +// +// FIXED: by replacement with A tested working version +// that not only doesn't multiplies right it does it +// two times faster! +// RPH 07/17/2002 +// Rewrote to comply with the new guidelines +//------------------------------------------------------------------------------ + +module DW02_mult(A,B,TC,PRODUCT); +parameter integer A_width = 8; +parameter integer B_width = 8; + +input [A_width-1:0] A; +input [B_width-1:0] B; +input TC; +output [A_width+B_width-1:0] PRODUCT; + +wire [A_width+B_width-1:0] PRODUCT; + +wire [A_width-1:0] temp_a; +wire [B_width-1:0] temp_b; +wire [A_width+B_width-2:0] long_temp1,long_temp2; + + // synopsys translate_off + //------------------------------------------------------------------------- + // Parameter legality check + //------------------------------------------------------------------------- + + + + initial begin : parameter_check + integer param_err_flg; + + param_err_flg = 0; + + + if (A_width < 1) begin + param_err_flg = 1; + $display( + "ERROR: %m :\n Invalid value (%d) for parameter A_width (lower bound: 1)", + A_width ); + end + + if (B_width < 1) begin + param_err_flg = 1; + $display( + "ERROR: %m :\n Invalid value (%d) for parameter B_width (lower bound: 1)", + B_width ); + end + + if ( param_err_flg == 1) begin + $display( + "%m :\n Simulation aborted due to invalid parameter value(s)"); + $finish; + end + + end // parameter_check + + +assign temp_a = (A[A_width-1])? (~A + 1'b1) : A; +assign temp_b = (B[B_width-1])? (~B + 1'b1) : B; + +assign long_temp1 = temp_a * temp_b; +assign long_temp2 = ~(long_temp1 - 1'b1); + +assign PRODUCT = ((^(A ^ A) !== 1'b0) || (^(B ^ B) !== 1'b0) || (^(TC ^ TC) !== 1'b0) ) ? {A_width+B_width{1'bX}} : + (TC)? (((A[A_width-1] ^ B[B_width-1]) && (|long_temp1))? + {1'b1,long_temp2} : {1'b0,long_temp1}) + : A * B; + // synopsys translate_on +endmodule + + diff --git a/tb/digital_top/DW_mult_pipe.v b/tb/digital_top/DW_mult_pipe.v new file mode 100644 index 0000000..a99a7b9 --- /dev/null +++ b/tb/digital_top/DW_mult_pipe.v @@ -0,0 +1,357 @@ +//////////////////////////////////////////////////////////////////////////////// +// +// This confidential and proprietary software may be used only +// as authorized by a licensing agreement from Synopsys Inc. +// In the event of publication, the following notice is applicable: +// +// (C) COPYRIGHT 2002 - 2018 SYNOPSYS INC. +// ALL RIGHTS RESERVED +// +// The entire notice above must be reproduced on all authorized +// copies. +// +// AUTHOR: Rajeev Huralikoppi Feb 15, 2002 +// +// VERSION: Verilog Simulation Architecture +// +// DesignWare_version: 4e25d03d +// DesignWare_release: O-2018.06-DWBB_201806.3 +// +//////////////////////////////////////////////////////////////////////////////// +//----------------------------------------------------------------------------- +// ABSTRACT: An n stage pipelined multipler simulation model +// +// Parameters Valid Values Description +// ========== ========= =========== +// a_width >= 1 default: none +// Word length of a +// +// b_width >= 1 default: none +// Word length of b +// +// num_stages >= 2 default: 2 +// Number of pipelined stages +// +// stall_mode 0 or 1 default: 1 +// Stall mode +// 0 => non-stallable +// 1 => stallable +// +// rst_mode 0 to 2 default: 1 +// Reset mode +// 0 => no reset +// 1 => asynchronous reset +// 2 => synchronous reset +// +// op_iso_mode 0 to 4 default: 0 +// Type of operand isolation +// If 'stall_mode' is '0', this parameter is ignored and no isolation is applied +// 0 => Follow intent defined by Power Compiler user setting +// 1 => no operand isolation +// 2 => 'and' gate operand isolaton +// 3 => 'or' gate operand isolation +// 4 => preferred isolation style: 'and' +// +// +// Input Ports Size Description +// =========== ==== ============ +// clk 1 Clock +// rst_n 1 Reset, active low +// en 1 Register enable, active high +// tc 1 2's complement control +// a a_width Multiplier +// b b_width Multiplicand +// +// product a_width+b_width Product (a*b) +// +// MODIFIED: +// RJK 05/14/15 Updated model to work with less propagated 'X's +// so as to be more friendly with VCS-NLP +// +// RJK 05/28/13 Updated documentation in comments to properly +// describe the "en" input (STAR 9000627580) +// +// DLL 02/01/08 Enhanced abstract and added "op_iso_mode" parameter +// and related code. +// +// DLL 11/14/05 Changed legality checking of 'num_stages' +// parameter along with its abstract "Valid Values" +// +// +//----------------------------------------------------------------------------- + +module DW_mult_pipe (clk,rst_n,en,tc,a,b,product); + + parameter integer a_width = 2; + parameter integer b_width = 2; + parameter integer num_stages = 2; + parameter integer stall_mode = 1; + parameter integer rst_mode = 1; + parameter integer op_iso_mode = 0; + + + input clk; + input rst_n; + input [a_width-1 : 0] a; + input [b_width-1 : 0] b; + input tc; + input en; + + output [a_width+b_width-1: 0] product; + + reg [a_width-1 : 0] a_reg [0 : num_stages-2]; + reg [b_width-1 : 0] b_reg [0 : num_stages-2]; + reg tc_reg [0 : num_stages-2]; + + // synopsys translate_off + //--------------------------------------------------------------------------- + // Behavioral model + //--------------------------------------------------------------------------- + +generate + if (rst_mode == 0) begin : GEN_RSM_EQ_0 + + if (stall_mode == 0) begin : GEN_RM0_SM0 + always @(posedge clk) begin: rm0_sm0_pipe_reg_PROC + integer i; + + for(i= 0; i < num_stages-1; i=i+1) begin + if (i == 0) begin + a_reg[0] <= a; + b_reg[0] <= b; + tc_reg[0] <= tc; + end else begin + a_reg[i] <= a_reg[i-1]; + b_reg[i] <= b_reg[i-1]; + tc_reg[i] <= tc_reg[i-1]; + end + end // for (i= 0; i < num_stages-1; i++) + end // block: rm0_pipe_reg_PROC + end else begin : GEN_RM0_SM1 + always @(posedge clk) begin: rm0_sm1_pipe_reg_PROC + integer i; + + for(i= 0; i < num_stages-1; i=i+1) begin + if (i == 0) begin + a_reg[0] <= (en == 1'b0)? a_reg[0] : ((en == 1'b1)? a : {a_width{1'bx}}); + b_reg[0] <= (en == 1'b0)? b_reg[0] : ((en == 1'b1)? b : {b_width{1'bx}}); + tc_reg[0] <= (en == 1'b0)? tc_reg[0]: ((en == 1'b1)? tc: 1'bx); + end else begin + a_reg[i] <= (en == 1'b0)? a_reg[i] : ((en == 1'b1)? a_reg[i-1] : {a_width{1'bx}}); + b_reg[i] <= (en == 1'b0)? b_reg[i] : ((en == 1'b1)? b_reg[i-1] : {b_width{1'bx}}); + tc_reg[i] <= (en == 1'b0)? tc_reg[i]: ((en == 1'b1)? tc_reg[i-1]: 1'bx); + end + end + end + end + + end else if (rst_mode == 1) begin : GEN_RM_EQ_1 + + if (stall_mode == 0) begin : GEN_RM1_SM0 + always @(posedge clk or negedge rst_n) begin: rm1_pipe_reg_PROC + integer i; + + if (rst_n == 1'b0) begin + for (i= 0; i < num_stages-1; i=i+1) begin + a_reg[i] <= {a_width{1'b0}}; + b_reg[i] <= {b_width{1'b0}}; + tc_reg[i] <= 1'b0; + end // for (i= 0; i < num_stages-1; i++) + end else if (rst_n == 1'b1) begin + for(i= 0; i < num_stages-1; i=i+1) begin + if (i == 0) begin + a_reg[0] <= a; + b_reg[0] <= b; + tc_reg[0] <= tc; + end else begin + a_reg[i] <= a_reg[i-1]; + b_reg[i] <= b_reg[i-1]; + tc_reg[i] <= tc_reg[i-1]; + end + end // for (i= 0; i < num_stages-1; i++) + end else begin // rst_n not 1'b0 and not 1'b1 + for (i= 0; i < num_stages-1; i=i+1) begin + a_reg[i] <= {a_width{1'bx}}; + b_reg[i] <= {b_width{1'bx}}; + tc_reg[i] <= 1'bx; + end // for (i= 0; i < num_stages-1; i++) + end + end // block: rm1_pipe_reg_PROC + end else begin : GEN_RM1_SM1 + always @(posedge clk or negedge rst_n) begin: rm1_pipe_reg_PROC + integer i; + + if (rst_n == 1'b0) begin + for (i= 0; i < num_stages-1; i=i+1) begin + a_reg[i] <= {a_width{1'b0}}; + b_reg[i] <= {b_width{1'b0}}; + tc_reg[i] <= 1'b0; + end // for (i= 0; i < num_stages-1; i++) + end else if (rst_n == 1'b1) begin + for(i= 0; i < num_stages-1; i=i+1) begin + if (i == 0) begin + a_reg[0] <= (en == 1'b0)? a_reg[0] : ((en == 1'b1)? a : {a_width{1'bx}}); + b_reg[0] <= (en == 1'b0)? b_reg[0] : ((en == 1'b1)? b : {b_width{1'bx}}); + tc_reg[0] <= (en == 1'b0)? tc_reg[0]: ((en == 1'b1)? tc: 1'bx); + end else begin + a_reg[i] <= (en == 1'b0)? a_reg[i] : ((en == 1'b1)? a_reg[i-1] : {a_width{1'bx}}); + b_reg[i] <= (en == 1'b0)? b_reg[i] : ((en == 1'b1)? b_reg[i-1] : {b_width{1'bx}}); + tc_reg[i] <= (en == 1'b0)? tc_reg[i]: ((en == 1'b1)? tc_reg[i-1]: 1'bx); + end + end // for (i= 0; i < num_stages-1; i++) + end else begin // rst_n not 1'b0 and not 1'b1 + for (i= 0; i < num_stages-1; i=i+1) begin + a_reg[i] <= {a_width{1'bx}}; + b_reg[i] <= {b_width{1'bx}}; + tc_reg[i] <= 1'bx; + end // for (i= 0; i < num_stages-1; i++) + end + end // block: rm1_pipe_reg_PROC + end + + end else begin : GEN_RM_GT_1 + + if (stall_mode == 0) begin : GEN_RM2_SM0 + always @(posedge clk) begin: rm2_pipe_reg_PROC + integer i; + + if (rst_n == 1'b0) begin + for (i= 0; i < num_stages-1; i=i+1) begin + a_reg[i] <= {a_width{1'b0}}; + b_reg[i] <= {b_width{1'b0}}; + tc_reg[i] <= 1'b0; + end // for (i= 0; i < num_stages-1; i++) + end else if (rst_n == 1'b1) begin + for(i= 0; i < num_stages-1; i=i+1) begin + if (i == 0) begin + a_reg[0] <= a; + b_reg[0] <= b; + tc_reg[0] <= tc; + end else begin + a_reg[i] <= a_reg[i-1]; + b_reg[i] <= b_reg[i-1]; + tc_reg[i] <= tc_reg[i-1]; + end + end // for (i= 0; i < num_stages-1; i++) + end else begin // rst_n not 1'b0 and not 1'b1 + for (i= 0; i < num_stages-1; i=i+1) begin + a_reg[i] <= {a_width{1'bx}}; + b_reg[i] <= {b_width{1'bx}}; + tc_reg[i] <= 1'bx; + end // for (i= 0; i < num_stages-1; i++) + end + end // block: rm2_pipe_reg_PROC + end else begin : GEN_RM2_SM1 + always @(posedge clk) begin: rm2_pipe_reg_PROC + integer i; + + if (rst_n == 1'b0) begin + for (i= 0; i < num_stages-1; i=i+1) begin + a_reg[i] <= {a_width{1'b0}}; + b_reg[i] <= {b_width{1'b0}}; + tc_reg[i] <= 1'b0; + end // for (i= 0; i < num_stages-1; i++) + end else if (rst_n == 1'b1) begin + for(i= 0; i < num_stages-1; i=i+1) begin + if (i == 0) begin + a_reg[0] <= (en == 1'b0)? a_reg[0] : ((en == 1'b1)? a : {a_width{1'bx}}); + b_reg[0] <= (en == 1'b0)? b_reg[0] : ((en == 1'b1)? b : {b_width{1'bx}}); + tc_reg[0] <= (en == 1'b0)? tc_reg[0]: ((en == 1'b1)? tc: 1'bx); + end else begin + a_reg[i] <= (en == 1'b0)? a_reg[i] : ((en == 1'b1)? a_reg[i-1] : {a_width{1'bx}}); + b_reg[i] <= (en == 1'b0)? b_reg[i] : ((en == 1'b1)? b_reg[i-1] : {b_width{1'bx}}); + tc_reg[i] <= (en == 1'b0)? tc_reg[i]: ((en == 1'b1)? tc_reg[i-1]: 1'bx); + end + end // for (i= 0; i < num_stages-1; i++) + end else begin // rst_n not 1'b0 and not 1'b1 + for (i= 0; i < num_stages-1; i=i+1) begin + a_reg[i] <= {a_width{1'bx}}; + b_reg[i] <= {b_width{1'bx}}; + tc_reg[i] <= 1'bx; + end // for (i= 0; i < num_stages-1; i++) + end + end // block: rm2_pipe_reg_PROC + end + + end +endgenerate + + DW02_mult #(a_width, b_width) + U1 (.A(a_reg[num_stages-2]), + .B(b_reg[num_stages-2]), + .TC(tc_reg[num_stages-2]), + .PRODUCT(product)); + //--------------------------------------------------------------------------- + // Parameter legality check and initializations + //--------------------------------------------------------------------------- + + + initial begin : parameter_check + integer param_err_flg; + + param_err_flg = 0; + + + if (a_width < 1) begin + param_err_flg = 1; + $display( + "ERROR: %m :\n Invalid value (%d) for parameter a_width (lower bound: 1)", + a_width ); + end + + if (b_width < 1) begin + param_err_flg = 1; + $display( + "ERROR: %m :\n Invalid value (%d) for parameter b_width (lower bound: 1)", + b_width ); + end + + if (num_stages < 2) begin + param_err_flg = 1; + $display( + "ERROR: %m :\n Invalid value (%d) for parameter num_stages (lower bound: 2)", + num_stages ); + end + + if ( (stall_mode < 0) || (stall_mode > 1) ) begin + param_err_flg = 1; + $display( + "ERROR: %m :\n Invalid value (%d) for parameter stall_mode (legal range: 0 to 1)", + stall_mode ); + end + + if ( (rst_mode < 0) || (rst_mode > 2) ) begin + param_err_flg = 1; + $display( + "ERROR: %m :\n Invalid value (%d) for parameter rst_mode (legal range: 0 to 2)", + rst_mode ); + end + + if ( (op_iso_mode < 0) || (op_iso_mode > 4) ) begin + param_err_flg = 1; + $display( + "ERROR: %m :\n Invalid value (%d) for parameter op_iso_mode (legal range: 0 to 4)", + op_iso_mode ); + end + + if ( param_err_flg == 1) begin + $display( + "%m :\n Simulation aborted due to invalid parameter value(s)"); + $finish; + end + + end // parameter_check + + + //--------------------------------------------------------------------------- + // Report unknown clock inputs + //--------------------------------------------------------------------------- + + always @ (clk) begin : clk_monitor + if ( (clk !== 1'b0) && (clk !== 1'b1) && ($time > 0) ) + $display( "WARNING: %m :\n at time = %t, detected unknown value, %b, on clk input.", + $time, clk ); + end // clk_monitor + + // synopsys translate_on +endmodule // diff --git a/tb/digital_top/Makefile b/tb/digital_top/Makefile new file mode 100644 index 0000000..6c048e4 --- /dev/null +++ b/tb/digital_top/Makefile @@ -0,0 +1,17 @@ +VCS = vcs -full64 -sverilog +lint=TFIPC-L +v2k -debug_access+all +define+DUMP_FSDB -lca -q -timescale=1ns/1ps +nospecify -P /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/pli.a -l compile.log + +SIMV = ./simv -l sim.log + +all:comp run + +comp: + ${VCS} -f files.f + +run: + ${SIMV} + +dbg: + verdi -sverilog -f files.f -top TB -nologo & + +clean: + rm -rf DVE* simv* *log ucli.key verdiLog urgReport csrc novas.* *.fsdb *.dat *.daidir *.vdb *~ diff --git a/tb/digital_top/TB.sv b/tb/digital_top/TB.sv new file mode 100644 index 0000000..d8497e0 --- /dev/null +++ b/tb/digital_top/TB.sv @@ -0,0 +1,1131 @@ +`include "chip_define.v" + + + +//-----------AWG out NCO data------------------ +//1'b0:normal data; 1'b1: NCO data +`define AWG_OUT 1'b0 +//-------Configure chip role------------------- +//2'b00:XY's Chiop at AC Mode +//2'b11:Z's Chiop at DC Mode +`define ROLE 2'b00 + +//-------Interpolation------------------------- +//Set the interpolation factor +//3'b000:x1;3'b001:x2;3'b010:x4; +//3'b011:x8;3'b100:x16; +`define INTP_MODE 3'b000 + +//-----------QAM mode-------------------------- +//Set the mixer output to the mixed signal +//2'b00:bypass;2'b01:mix; +//2'b10:cos;2'b11:sin; +`define QAM_MODE 2'b01 + +//-----------sideband select------------------- +//Set the mixer to upper sideband modulation +//1'b0:Upper sideband;1'b1:Lower sideband; +`define MIX_SIDEBAND 1'b0 + +//-----------DAC data format-------------------- +//Set the DAC data format to normal mode +//2'b00:NRZ mode;2'b01:MIX mode; +//2'b10:2xNRZ mode;2'b00:reserve; +`define DAC_FORMAT 2'b00 + + +//define Instr and Envelope ID and envelope data +//`define MCU_INSTR_FILE "../../cfgdata/instrmem/SingleWaveCosine_bin.txt" +`define MCU_INSTR_FILE "../../cfgdata/instrmem/SingleWaveCombine_bin.txt" +//`define MCU_INSTR_FILE "../../cfgdata/instrmem/SingleWaveFlattop_bin.txt" +//`define MCU_INSTR_FILE "../../cfgdata/instrmem/awg_inst.txt" +//`define MCU_INSTR_FILE "../../cfgdata/instrmem/SingleWaveRectangle_bin.txt" +`define MCU_DATA_FILE "../../cfgdata/datamem/awg_data.txt" +`define ENVE_ID_FILE "../../cfgdata/enveindex/wave_index_12.txt" +`define ENVE_DATA_FILE "../../cfgdata/envemem/wave_bin_12.txt" +`define READ_FILE "../../cfgdata/envemem/rwave_bin_12.txt" + +`define CHIIPID 5'b0_0000 +`define SYSREG_BASEADDR 25'h000_0000 +`define CH0_ITCM_BASEADDR 25'h010_0000 +`define CH0_DTCM_BASEADDR 25'h020_0000 +`define CH0_CTRLREG_BASEADDR 25'h030_0000 +`define CH0_ENVEID_BASEADDR 25'h040_0000 +`define CH0_ENVEMEM_BASEADDR 25'h050_0000 +`define CH0_DACREG_BASEADDR 25'h060_0000 +`define PLL_BASEADDR 25'h1F0_0000 + +class BinaryDataReader; + + // 定义一个ä½é˜Ÿåˆ—æ¥å­˜å‚¨ä»ŽTXT文件中读å–çš„32ä½äºŒè¿›åˆ¶æ•°æ®çš„æ¯ä¸€ä½ + bit spi_data_queue[$]; + + // 定义一个方法，用于读å–TXT文件并将32ä½äºŒè¿›åˆ¶æ•°æ®æŒ‰æ¯”特存储到队列中 + function void read_txt_file(input string filename); + int file_id; + string line; + bit [31:0] binary_value; + int i; + + // æ‰“å¼€æ–‡ä»¶ä»¥è¿›è¡Œè¯»å– + file_id = $fopen(filename, "r"); + if (file_id == 0) begin + $display("Error: Failed to open file %s", filename); + return; + end + + // 读å–文件的æ¯ä¸€è¡Œï¼Œå¹¶å°†å…¶ä½œä¸º32ä½äºŒè¿›åˆ¶æ•°æ®æ·»åŠ åˆ°é˜Ÿåˆ—中 + while (!$feof(file_id)) begin + //if ($fgets(line, file_id)) begin + $fscanf(file_id,"%b\n",binary_value); + for (i = 31; i >= 0; i--) begin + spi_data_queue.push_back(binary_value[i]); + end + //end + end + + // 关闭文件 + $fclose(file_id); + endfunction + + function void get_data_queue(ref bit data_queue[$]); + data_queue = spi_data_queue; + spi_data_queue.delete(); + endfunction + +endclass + +class spi_data_send; + virtual spi_if spi_intf; + task send_item(bit data_queue[], virtual spi_if spi_intf); + + //ToDo + //wait(spi_intf.rstn); + #15ns; + spi_intf.csn <= 1'b1; + spi_intf.sclk <= 1'b1; + #15ns; + spi_intf.csn <= 1'b0; + #15ns; + foreach(data_queue[i]) begin + spi_intf.mosi <= data_queue[i]; + spi_intf.sclk <= ~spi_intf.sclk; + #50ns; + spi_intf.sclk <= ~spi_intf.sclk; + #50ns; + end + spi_intf.sclk <= 1'b1; + #15ns; + spi_intf.csn <= 1'b1; + #100ns; + endtask : send_item + +endclass + + +class spi_reg; + virtual spi_if spi_intf; + bit spi_reg_queue[$]; + bit [63:0] write_item; + int i; + task write_reg(bit cmd, bit[24:0] addr, bit[4:0] chipid, bit[31:0] data, virtual spi_if spi_intf); + write_item = {cmd,addr,chipid,1'b0,data}; + $display("write_item %b", write_item); + for (i = 63; i >= 0; i--) begin + spi_reg_queue.push_back(write_item[i]); + $display("write_item %0d: %b", i, write_item[i]); + end + foreach (spi_reg_queue[i]) begin + $display("reg %0d: %b", i, spi_reg_queue[i]); + end + //ToDo + //wait(spi_intf.rstn); + #15ns; + spi_intf.csn <= 1'b1; + spi_intf.sclk <= 1'b1; + #15ns; + spi_intf.csn <= 1'b0; + #15ns; + foreach(spi_reg_queue[i]) begin + spi_intf.mosi <= spi_reg_queue[i]; + spi_intf.sclk <= ~spi_intf.sclk; + #50ns; + spi_intf.sclk <= ~spi_intf.sclk; + #50ns; + end + spi_intf.sclk <= ~spi_intf.sclk; + #50ns; + spi_intf.sclk <= 1'b1; + #15ns; + spi_intf.csn <= 1'b1; + #100ns; + spi_reg_queue.delete(); + endtask : write_reg + +endclass + + +module TB; + +parameter WRITE = 1'b0 , + READ = 1'b1 ; + + virtual spi_if vif; + + // 实例化TextFileReaderç±» + BinaryDataReader data_reader = new(); + spi_data_send spi_send = new(); + spi_reg reg_wr = new(); + + +//====================================================================== +initial begin + $fsdbAutoSwitchDumpfile(500, "./verdplus.fsdb", 1000000); + $fsdbDumpvars(); +end +//====================================================================== +//clock & reset & bootsel +//====================================================================== +logic clk ; +logic rstn ; +logic clk_rstn ; +logic qbmcu_i_start ; +bit data[$]; +parameter SYS_PERIOD = 2; +//sys_clk --> 50M, 0 phase +initial begin + clk =0; + forever # (SYS_PERIOD/2) clk = ~clk; +end + + +//hresetn +initial begin + clk_rstn = 0; + rstn = 0; + #1000; + clk_rstn = 0; + #1000; + clk_rstn = 1; + #1000; + rstn = 1; + // $display("m%"); +end + +spi_if aif(.*); + + + +initial begin + aif.sclk = 1'b1; + aif.mosi = 1'b0; + aif.csn = 1'b1; + vif = aif; +end +initial begin + qbmcu_i_start = 1'b0; + + wait (rstn); + +//////////////////////////////////////////////////////////// +//reg cfg +//////////////////////////////////////////////////////////// + +//-----------------debug------------------------------ +//DBGCFGR 16'h34 +// dbg_enable = dbgcfgr[0]; 1'b0 -> disable; 1'b1 -> enable; +// dbg_data_sel = dbgcfgr[1]; 1'b0-->mod;1'b1-->dsp +// dbg_ch_sel = dbgcfgr[5:2]; //4'b0001-->ch0;4'b0010-->ch1; + //4'b0100-->ch2;4'b1000-->ch3; +//6'b0001_0_1 + +reg_wr.write_reg(WRITE,`SYSREG_BASEADDR+32'h34,`CHIIPID,32'h00000007,vif); + + + + +//-----------------TC paraneter start------------------------------ +//a_re: +//tcparr0:'00000000E96476E1' +//TCPARHR0 16'h130 -> 32'h00000000 +//TCPARLR0 16'h134 -> 32'hE96476E1 +reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h130,`CHIIPID,32'h00000000,vif); +reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h134,`CHIIPID,32'hE96476E1,vif); +//tcparr1:'FFFFFFFF7AC0925C' +//TCPARHR1 16'h138 -> 32'hFFFFFFFF +//TCPARLR1 16'h13C -> 32'h7AC0925C +reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h138,`CHIIPID,32'hFFFFFFFF,vif); +reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h13C,`CHIIPID,32'h7AC0925C,vif); +//tcparr2:'000000016673A91C' +//TCPARHR2 16'h140 -> 32'h00000001 +//TCPARLR2 16'h144 -> 32'h6673A91C +reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h140,`CHIIPID,32'h00000001,vif); +reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h144,`CHIIPID,32'h6673A91C,vif); +//tcparr3:'0000000013C11A0B' +//TCPARHR3 16'h148 -> 32'h00000000 +//TCPARLR3 16'h14C -> 32'h13C11A0B +reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h148,`CHIIPID,32'h00000000,vif); +reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h14C,`CHIIPID,32'h13C11A0B,vif); +//tcparr4:'0000000000000000' +//TCPARHR4 16'h150 -> 32'h00000000 +//TCPARLR4 16'h154 -> 32'h00000000 +reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h150,`CHIIPID,32'h00000000,vif); +reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h154,`CHIIPID,32'h00000000,vif); +//tcparr5:'0000000000000000' +//TCPARHR5 16'h158 -> 32'h00000000 +//TCPARLR5 16'h15C -> 32'h00000000 +reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h158,`CHIIPID,32'h00000000,vif); +reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h15C,`CHIIPID,32'h00000000,vif); +//a_im: +//tcpair0:'0000000000000000' +//TCPAIHR0 16'h160 -> 32'h00000000 +//TCPAILR0 16'h164 -> 32'h00000000 +reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h160,`CHIIPID,32'h00000000,vif); +reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h164,`CHIIPID,32'h00000000,vif); +//tcpair1:'FFFFFFFF6405CFFB' +//TCPAIHR1 16'h168 -> 32'hFFFFFFFF +//TCPAILR1 16'h16C -> 32'h6405CFFB +reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h168,`CHIIPID,32'hFFFFFFFF,vif); +reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h16C,`CHIIPID,32'h6405CFFB,vif); +//tcpair2:'FFFFFFFEFEF5F1FF' +//TCPAIHR2 16'h170 -> 32'hFFFFFFFE +//TCPAILR2 16'h174 -> 32'hFEF5F1FF +reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h170,`CHIIPID,32'hFFFFFFFE,vif); +reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h174,`CHIIPID,32'hFEF5F1FF,vif); +//tcpair3:'0000000000000000' +//TCPAIHR3 16'h178 -> 32'h00000000 +//TCPAILR3 16'h17C -> 32'h00000000 +reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h178,`CHIIPID,32'h00000000,vif); +reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h17C,`CHIIPID,32'h00000000,vif); +//tcpair4:'0000000000000000' +//TCPAIHR4 16'h180 -> 32'h00000000 +//TCPAILR4 16'h184 -> 32'h00000000 +reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h180,`CHIIPID,32'h00000000,vif); +reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h184,`CHIIPID,32'h00000000,vif); +//tcpair5:'0000000000000000' +//TCPAIHR5 16'h188 -> 32'h00000000 +//TCPAILR5 16'h18C -> 32'h00000000 +reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h188,`CHIIPID,32'h00000000,vif); +reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h18C,`CHIIPID,32'h00000000,vif); + +//b_re: +//tcpbrr0:'FFF00E4D' +//TCPBRR0 16'h190 -> 32'hFFF00E4D +reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h190,`CHIIPID,32'hFFF00E4D,vif); +//tcpbrr1:'FFF02C39' +//TCPBRR1 16'h194 -> 32'hFFF02C39 +reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h194,`CHIIPID,32'hFFF02C39,vif); +//tcpbrr2:'FFF028F5' +//TCPBRR2 16'h198 -> 32'hFFF028F5 +reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h198,`CHIIPID,32'hFFF028F5,vif); +//tcpbrr3:'FFF0008C' +//TCPBRR3 16'h19C -> 32'hFFF0008C +reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h19C,`CHIIPID,32'hFFF0008C,vif); +//tcpbrr4:'FFF00000' +//TCPBRR4 16'h1A0 -> 32'hFFF00000 +reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h1A0,`CHIIPID,32'hFFF00000,vif); +//tcpbrr5:'FFF00000' +//TCPBRR5 16'h1A4 -> 32'hFFF00000 +reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h1A4,`CHIIPID,32'hFFF00000,vif); +//b_im: +//tcpbir0:'000000' +//TCPBIR0 16'h1A8 -> 32'h000000 +reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h1A8,`CHIIPID,32'h000000,vif); +//tcpbir1:'0028DC' +//TCPBIR1 16'h1AC -> 32'h0028DC +reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h1AC,`CHIIPID,32'h0028DC,vif); +//tcpbir2:'001140' +//TCPBIR2 16'h1B0 -> 32'h001140 +reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h1B0,`CHIIPID,32'h001140,vif); +//tcpbir3:'000000' +//TCPBIR3 16'h1B4 -> 32'h000000 +reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h1B4,`CHIIPID,32'h000000,vif); +//tcpbir4:'000000' +//TCPBIR4 16'h1B8 -> 32'h000000 +reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h1B8,`CHIIPID,32'h000000,vif); +//tcpbir5:'000000' +//TCPBIR5 16'h1BC -> 32'h000000 +reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h1BC,`CHIIPID,32'h000000,vif); +//-----------------TC paraneter end------------------------------ + + +//[0]-> 1'b1:Synchronous clear enable for the clock divider +//[1]-> 1'b1:Enable synchronous signal output +reg_wr.write_reg(WRITE,`PLL_BASEADDR+32'h4c,`CHIIPID,32'h3,vif); + + +//Set the chip role to XY +reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h128,`CHIIPID,`ROLE,vif); + + + +//Set the chip role to Z & DC mode +//reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h128,`CHIIPID,32'h0000_0003,vif); + + +//---------------------------INTP---------------------------------------------- + +//Set the interpolation factor +//3'b000:x1;3'b001:x2;3'b010:x4; +//3'b011:x8;3'b100:x16; + +reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h104,`CHIIPID,`INTP_MODE,vif); + +//---------------------------INTP---------------------------------------------- + +//Enable synchronous clearing for the mixing NCO +reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h190,`CHIIPID,32'h0000_0001,vif); + +//Set the output data type of the modulator +//1'b0 --> mod modem data; 1'b1 --> mod nco data for XY DAC +//1'b0 --> Z dsp data; 1'b1 --> XY dsp data for Z DAC +reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h1c4,`CHIIPID,`AWG_OUT,vif); + +//Set the carrier frequency of the mixing NCO (2GHz) +reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h10c,`CHIIPID,32'h2AAA_AAAA,vif); +reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h110,`CHIIPID,32'h2AAA_0000,vif); + +//Set the mixer to upper sideband modulation +//1'b0:Upper sideband;1'b1:Lower sideband; +reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h118,`CHIIPID,`MIX_SIDEBAND,vif); + +//Set the mixer output to the mixed signal +//2'b00:bypass;2'b01:mix; +//2'b10:cos;2'b11:sin; +reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h11c,`CHIIPID,`QAM_MODE,vif); + +//Set the DAC data format to normal mode +reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h120,`CHIIPID,`DAC_FORMAT,vif); +//2'b00:NRZ mode;2'b01:MIX mode; +//2'b10:2xNRZ mode;2'b00:reserve; + + // 调用read_txt_file方法读å–TXT文件 + data_reader.read_txt_file(`MCU_INSTR_FILE); + + // 获å–æ•°æ®é˜Ÿåˆ—并打å°å…¶å†…容 + //bit data[$]; + data_reader.get_data_queue(data); + + foreach (data[i]) begin + $display("Line %0d: %b", i, data[i]); + end + $display("Send MCU_INSTR_FILE"); + spi_send.send_item(data,vif); + data.delete(); + #100; + + // 调用read_txt_file方法读å–TXT文件 + data_reader.read_txt_file(`MCU_DATA_FILE); + + // 获å–æ•°æ®é˜Ÿåˆ—并打å°å…¶å†…容 + //bit data[$]; + data_reader.get_data_queue(data); + + foreach (data[i]) begin + $display("Line %0d: %b", i, data[i]); + end + $display("Send MCU_INSTR_FILE"); + spi_send.send_item(data,vif); + data.delete(); + #100; + + + data_reader.read_txt_file(`ENVE_ID_FILE); + data_reader.get_data_queue(data); + foreach (data[i]) begin + $display("Line %0d: %b", i, data[i]); + end + $display("Send ENVE_ID_FILE"); + spi_send.send_item(data,vif); + data.delete(); + #100; + + data_reader.read_txt_file(`ENVE_DATA_FILE); + data_reader.get_data_queue(data); + foreach (data[i]) begin + $display("Line %0d: %b", i, data[i]); + end + $display("Send ENVE_DATA1_FILE"); + spi_send.send_item(data,vif); + data.delete(); + + #100; + + + + #100; + qbmcu_i_start = 1'b1; + #500; + qbmcu_i_start = 1'b0; + + #100000; + + data_reader.read_txt_file(`READ_FILE); + data_reader.get_data_queue(data); + + #1000000; +reg_wr.write_reg(WRITE,`SYSREG_BASEADDR+32'h34,`CHIIPID,32'h00000000,vif); + foreach (data[i]) begin + $display("Line %0d: %b", i, data[i]); + end + $display("Send READ_FILE"); + spi_send.send_item(data,vif); + data.delete(); +end + + + +/////////////////////////////////////////////////////////////////////////////////////////// +//clk gen +/////////////////////////////////////////////////////////////////////////////////////////// +wire clk_div16_0; +wire clk_div16_1; +wire clk_div16_2; +wire clk_div16_3; +wire clk_div16_4; +wire clk_div16_5; +wire clk_div16_6; +wire clk_div16_7; +wire clk_div16_8; +wire clk_div16_9; +wire clk_div16_a; +wire clk_div16_b; +wire clk_div16_c; +wire clk_div16_d; +wire clk_div16_e; +wire clk_div16_f; + + +clk_gen inst_clk_gen( + .rstn (clk_rstn ) + ,.clk (clk ) + ,.clk_div16_0 (clk_div16_0 ) + ,.clk_div16_1 (clk_div16_1 ) + ,.clk_div16_2 (clk_div16_2 ) + ,.clk_div16_3 (clk_div16_3 ) + ,.clk_div16_4 (clk_div16_4 ) + ,.clk_div16_5 (clk_div16_5 ) + ,.clk_div16_6 (clk_div16_6 ) + ,.clk_div16_7 (clk_div16_7 ) + ,.clk_div16_8 (clk_div16_8 ) + ,.clk_div16_9 (clk_div16_9 ) + ,.clk_div16_a (clk_div16_a ) + ,.clk_div16_b (clk_div16_b ) + ,.clk_div16_c (clk_div16_c ) + ,.clk_div16_d (clk_div16_d ) + ,.clk_div16_e (clk_div16_e ) + ,.clk_div16_f (clk_div16_f ) + ,.clk_h (clk_h ) + ,.clk_l (clk_l ) + ); + + + +//////////////////////////////////////////////////////////////////////////////////////// +//DUT +//////////////////////////////////////////////////////////////////////////////////////// +wire async_rstn = rstn; +wire por_rstn = 1'b1; +logic sync_out ; +logic [1 :0] ch0_feedback = 2'b00; +wire [4 :0] cfgid = 5'b00000; +logic irq; + +//------------------------------PLL cfg pin---------------------------------------------------- +logic ref_sel ; // Clock source selection for a frequency divider; + // 1'b0:External clock source + // 1'b1:internal phase-locked loop clock source +logic ref_en ; // Input reference clock enable + // 1'b0:enable,1'b1:disable +logic ref_s2d_en ; // Referenced clock differential to single-ended conversion enable + // 1'b0:enable,1'b1:disable +logic [6 :0] p_cnt ; // P counter +logic pfd_delay ; // PFD Dead Zone +logic pfd_dff_Set ; // Setting the PFD register,active high +logic pfd_dff_4and ; // PFD output polarity +logic [3 :0] spd_div ; // SPD Frequency Divider +logic spd_pulse_width ; // Pulse Width of SPD +logic spd_pulse_sw ; // Pulse sw of SPD +logic cpc_sel ; // current source selection +logic [1 :0] swcp_i ; // PTAT current switch +logic [3 :0] sw_ptat_r ; // PTAT current adjustment +logic [1 :0] sw_fll_cpi ; // Phase-locked loop charge pump current +logic sw_fll_delay ; // PLL Dead Zone +logic pfd_sel ; // PFD Loop selection +logic spd_sel ; // SPD Loop selection +logic fll_sel ; // FLL Loop selection +logic vco_tc ; // VCO temperature compensation +logic vco_tcr ; // VCO temperature compensation resistor +logic vco_gain_adj ; // VCO gain adjustment +logic vco_gain_adj_r ; // VCO gain adjustment resistor +logic [2 :0] vco_cur_adj ; // VCO current adjustment +logic vco_buff_en ; // VCO buff enable,active high +logic vco_en ; // VCO enable,active high +logic [2 :0] pll_dpwr_adj ; // PLL frequency division output power adjustment +logic [6 :0] vco_fb_adj ; // VCO frequency band adjustment +logic afc_en ; // AFC enable +logic afc_shutdown ; // AFC module shutdown signal +logic [0 :0] afc_det_speed ; // AFC detection speed +logic [0 :0] flag_out_sel ; // Read and choose the signs +logic afc_reset ; // AFC reset +logic [10 :0] afc_cnt ; // AFC frequency band adjustment function counter + // counting time adjustment +logic [10 :0] afc_ld_cnt ; // Adjust the counting time of the AFC lock detection + // feature counter +logic [3 :0] afc_pres ; // Adjusting the resolution of the AFC comparator +logic [14 :0] afc_ld_tcc ; // AFC Lock Detection Function Target Cycle Count +logic [14 :0] afc_fb_tcc ; // Target number of cycles for AFC frequency band + // adjustment function +logic sync_clr ; // PLL div sync clr,low active +logic pll_rstn ; // PLL reset,active low +logic [0 :0] div_rstn_sel ; // div rstn select, 1'b0: ext clear, 1'b1:inter pll lock +logic [1 :0] test_clk_sel ; // test clk select, 2'b00:DIV1 clk, 2'b01:DIV2 clk, 2'b10:DIV4 clk, 2'b11:DIV8 clk +logic [0 :0] test_clk_oen ; // test clk output enable, 1'b0:disenable, 1'b1:enable +logic [7 :0] dig_clk_sel ; // digital main clk select, one hot code,bit[0]-->0 degree phase,bit[1]-->45 degree phase.....bit[7]-->315degree phae +logic clkrx_pdn ; +logic pll_lock = 1'b1 ; // PLL LOCK + +//DAC cfg +logic ch0_dac_Prbs ; +logic [14 :0] ch0_dac_Set0 ; +logic [14 :0] ch0_dac_Set1 ; +logic [14 :0] ch0_dac_Set2 ; +logic [14 :0] ch0_dac_Set3 ; +logic [14 :0] ch0_dac_Set4 ; +logic [14 :0] ch0_dac_Set5 ; +logic [14 :0] ch0_dac_Set6 ; +logic [14 :0] ch0_dac_Set7 ; +logic [14 :0] ch0_dac_Set8 ; +logic [14 :0] ch0_dac_Set9 ; +logic [14 :0] ch0_dac_Set10 ; +logic [14 :0] ch0_dac_Set11 ; +logic [14 :0] ch0_dac_Set12 ; +logic [14 :0] ch0_dac_Set13 ; +logic [14 :0] ch0_dac_Set14 ; +logic [14 :0] ch0_dac_Set15 ; +logic [2 :0] ch0_dac_addr ; +logic [2 :0] ch0_dac_dw ; +logic [8 :0] ch0_dac_ref ; +logic [16 :0] ch0_dac_Prbs_rst0 ; +logic [16 :0] ch0_dac_Prbs_set0 ; +logic [16 :0] ch0_dac_Prbs_rst1 ; +logic [16 :0] ch0_dac_Prbs_set1 ; +logic ch0_dac_Cal_sig ; +logic ch0_dac_Cal_rstn ; +logic ch0_dac_Cal_end = 1'b1 ; + +//DSP output +//`ifdef CHANNEL_XY_ON +logic [15 :0] ch0_xy_dsp_dout0 ; +logic [15 :0] ch0_xy_dsp_dout1 ; +logic [15 :0] ch0_xy_dsp_dout2 ; +logic [15 :0] ch0_xy_dsp_dout3 ; +logic [15 :0] ch0_xy_dsp_dout4 ; +logic [15 :0] ch0_xy_dsp_dout5 ; +logic [15 :0] ch0_xy_dsp_dout6 ; +logic [15 :0] ch0_xy_dsp_dout7 ; +logic [15 :0] ch0_xy_dsp_dout8 ; +logic [15 :0] ch0_xy_dsp_dout9 ; +logic [15 :0] ch0_xy_dsp_dout10 ; +logic [15 :0] ch0_xy_dsp_dout11 ; +logic [15 :0] ch0_xy_dsp_dout12 ; +logic [15 :0] ch0_xy_dsp_dout13 ; +logic [15 :0] ch0_xy_dsp_dout14 ; +logic [15 :0] ch0_xy_dsp_dout15 ; +//`endif +//`ifdef CHANNEL_Z_ON +logic [15 :0] ch0_z_dsp_dout0 ; +logic [15 :0] ch0_z_dsp_dout1 ; +logic [15 :0] ch0_z_dsp_dout2 ; +logic [15 :0] ch0_z_dsp_dout3 ; +//`endif + + + +digital_top U_digital_top ( + .clk ( clk_div16_0 ) + ,.por_rstn ( por_rstn ) + ,.async_rstn ( async_rstn ) + ,.sync_in ( qbmcu_i_start ) + ,.sync_out ( sync_out ) + ,.ch0_feedback ( ch0_feedback ) + `ifdef CHANNEL_IS_FOUR + ,.ch1_feedback ( ch1_feedback ) + ,.ch2_feedback ( ch2_feedback ) + ,.ch3_feedback ( ch3_feedback ) + `endif + ,.cfgid ( cfgid ) + ,.sclk ( aif.sclk ) + ,.csn ( aif.csn ) + ,.mosi ( aif.mosi ) + ,.miso ( aif.miso ) + ,.oen ( oen ) + ,.irq ( irq ) + ,.ref_sel ( ref_sel ) + ,.ref_en ( ref_en ) + ,.ref_s2d_en ( ref_s2d_en ) + ,.p_cnt ( p_cnt ) + ,.pfd_delay ( pfd_delay ) + ,.pfd_dff_Set ( pfd_dff_Set ) + ,.pfd_dff_4and ( pfd_dff_4and ) + ,.spd_div ( spd_div ) + ,.spd_pulse_width ( spd_pulse_width ) + ,.spd_pulse_sw ( spd_pulse_sw ) + ,.cpc_sel ( cpc_sel ) + ,.swcp_i ( swcp_i ) + ,.sw_ptat_r ( sw_ptat_r ) + ,.sw_fll_cpi ( sw_fll_cpi ) + ,.sw_fll_delay ( sw_fll_delay ) + ,.pfd_sel ( pfd_sel ) + ,.spd_sel ( spd_sel ) + ,.fll_sel ( fll_sel ) + ,.vco_tc ( vco_tc ) + ,.vco_tcr ( vco_tcr ) + ,.vco_gain_adj ( vco_gain_adj ) + ,.vco_gain_adj_r ( vco_gain_adj_r ) + ,.vco_cur_adj ( vco_cur_adj ) + ,.vco_buff_en ( vco_buff_en ) + ,.vco_en ( vco_en ) + ,.pll_dpwr_adj ( pll_dpwr_adj ) + ,.vco_fb_adj ( vco_fb_adj ) + ,.afc_en ( afc_en ) + ,.afc_shutdown ( afc_shutdown ) + ,.afc_det_speed ( afc_det_speed ) + ,.flag_out_sel ( flag_out_sel ) + ,.afc_reset ( afc_reset ) + ,.afc_cnt ( afc_cnt ) + ,.afc_ld_cnt ( afc_ld_cnt ) + ,.afc_pres ( afc_pres ) + ,.afc_ld_tcc ( afc_ld_tcc ) + ,.afc_fb_tcc ( afc_fb_tcc ) + ,.sync_clr ( sync_clr ) + ,.pll_rstn ( pll_rstn ) + ,.div_rstn_sel ( div_rstn_sel ) + ,.test_clk_sel ( test_clk_sel ) + ,.test_clk_oen ( test_clk_oen ) + ,.dig_clk_sel ( dig_clk_sel ) + ,.clkrx_pdn ( clkrx_pdn ) + ,.pll_lock ( pll_lock ) + ,.ch0_dac_Prbs ( ch0_dac_Prbs ) + ,.ch0_dac_Set0 ( ch0_dac_Set0 ) + ,.ch0_dac_Set1 ( ch0_dac_Set1 ) + ,.ch0_dac_Set2 ( ch0_dac_Set2 ) + ,.ch0_dac_Set3 ( ch0_dac_Set3 ) + ,.ch0_dac_Set4 ( ch0_dac_Set4 ) + ,.ch0_dac_Set5 ( ch0_dac_Set5 ) + ,.ch0_dac_Set6 ( ch0_dac_Set6 ) + ,.ch0_dac_Set7 ( ch0_dac_Set7 ) + ,.ch0_dac_Set8 ( ch0_dac_Set8 ) + ,.ch0_dac_Set9 ( ch0_dac_Set9 ) + ,.ch0_dac_Set10 ( ch0_dac_Set10 ) + ,.ch0_dac_Set11 ( ch0_dac_Set11 ) + ,.ch0_dac_Set12 ( ch0_dac_Set12 ) + ,.ch0_dac_Set13 ( ch0_dac_Set13 ) + ,.ch0_dac_Set14 ( ch0_dac_Set14 ) + ,.ch0_dac_Set15 ( ch0_dac_Set15 ) + ,.ch0_dac_addr ( ch0_dac_addr ) + ,.ch0_dac_dw ( ch0_dac_dw ) + ,.ch0_dac_ref ( ch0_dac_ref ) + ,.ch0_dac_Prbs_rst0 ( ch0_dac_Prbs_rst0 ) + ,.ch0_dac_Prbs_set0 ( ch0_dac_Prbs_set0 ) + ,.ch0_dac_Prbs_rst1 ( ch0_dac_Prbs_rst1 ) + ,.ch0_dac_Prbs_set1 ( ch0_dac_Prbs_set1 ) + ,.ch0_dac_Cal_sig ( ch0_dac_Cal_sig ) + ,.ch0_dac_Cal_rstn ( ch0_dac_Cal_rstn ) + ,.ch0_dac_Cal_end ( ch0_dac_Cal_end ) + `ifdef CHANNEL_IS_FOUR + ,.ch1_dac_Prbs ( ch1_dac_Prbs ) + ,.ch1_dac_Set0 ( ch1_dac_Set0 ) + ,.ch1_dac_Set1 ( ch1_dac_Set1 ) + ,.ch1_dac_Set2 ( ch1_dac_Set2 ) + ,.ch1_dac_Set3 ( ch1_dac_Set3 ) + ,.ch1_dac_Set4 ( ch1_dac_Set4 ) + ,.ch1_dac_Set5 ( ch1_dac_Set5 ) + ,.ch1_dac_Set6 ( ch1_dac_Set6 ) + ,.ch1_dac_Set7 ( ch1_dac_Set7 ) + ,.ch1_dac_Set8 ( ch1_dac_Set8 ) + ,.ch1_dac_Set9 ( ch1_dac_Set9 ) + ,.ch1_dac_Set10 ( ch1_dac_Set10 ) + ,.ch1_dac_Set11 ( ch1_dac_Set11 ) + ,.ch1_dac_Set12 ( ch1_dac_Set12 ) + ,.ch1_dac_Set13 ( ch1_dac_Set13 ) + ,.ch1_dac_Set14 ( ch1_dac_Set14 ) + ,.ch1_dac_Set15 ( ch1_dac_Set15 ) + ,.ch1_dac_addr ( ch1_dac_addr ) + ,.ch1_dac_dw ( ch1_dac_dw ) + ,.ch1_dac_ref ( ch1_dac_ref ) + ,.ch1_dac_Prbs_rst0 ( ch1_dac_Prbs_rst0 ) + ,.ch1_dac_Prbs_set0 ( ch1_dac_Prbs_set0 ) + ,.ch1_dac_Prbs_rst1 ( ch1_dac_Prbs_rst1 ) + ,.ch1_dac_Prbs_set1 ( ch1_dac_Prbs_set1 ) + ,.ch1_dac_Cal_sig ( ch1_dac_Cal_sig ) + ,.ch1_dac_Cal_rstn ( ch1_dac_Cal_rstn ) + ,.ch1_dac_Reset ( ch1_dac_Reset ) + ,.ch1_dac_Digitalclk ( ch1_dac_Digitalclk ) + ,.ch1_dac_Cal_end ( ch1_dac_Cal_end ) + ,.ch2_dac_Prbs ( ch2_dac_Prbs ) + ,.ch2_dac_Set0 ( ch2_dac_Set0 ) + ,.ch2_dac_Set1 ( ch2_dac_Set1 ) + ,.ch2_dac_Set2 ( ch2_dac_Set2 ) + ,.ch2_dac_Set3 ( ch2_dac_Set3 ) + ,.ch2_dac_Set4 ( ch2_dac_Set4 ) + ,.ch2_dac_Set5 ( ch2_dac_Set5 ) + ,.ch2_dac_Set6 ( ch2_dac_Set6 ) + ,.ch2_dac_Set7 ( ch2_dac_Set7 ) + ,.ch2_dac_Set8 ( ch2_dac_Set8 ) + ,.ch2_dac_Set9 ( ch2_dac_Set9 ) + ,.ch2_dac_Set10 ( ch2_dac_Set10 ) + ,.ch2_dac_Set11 ( ch2_dac_Set11 ) + ,.ch2_dac_Set12 ( ch2_dac_Set12 ) + ,.ch2_dac_Set13 ( ch2_dac_Set13 ) + ,.ch2_dac_Set14 ( ch2_dac_Set14 ) + ,.ch2_dac_Set15 ( ch2_dac_Set15 ) + ,.ch2_dac_addr ( ch2_dac_addr ) + ,.ch2_dac_dw ( ch2_dac_dw ) + ,.ch2_dac_ref ( ch2_dac_ref ) + ,.ch2_dac_Prbs_rst0 ( ch2_dac_Prbs_rst0 ) + ,.ch2_dac_Prbs_set0 ( ch2_dac_Prbs_set0 ) + ,.ch2_dac_Prbs_rst1 ( ch2_dac_Prbs_rst1 ) + ,.ch2_dac_Prbs_set1 ( ch2_dac_Prbs_set1 ) + ,.ch2_dac_Cal_sig ( ch2_dac_Cal_sig ) + ,.ch2_dac_Cal_rstn ( ch2_dac_Cal_rstn ) + ,.ch2_dac_Reset ( ch2_dac_Reset ) + ,.ch2_dac_Digitalclk ( ch2_dac_Digitalclk ) + ,.ch2_dac_Cal_end ( ch2_dac_Cal_end ) + ,.ch3_dac_Prbs ( ch3_dac_Prbs ) + ,.ch3_dac_Set0 ( ch3_dac_Set0 ) + ,.ch3_dac_Set1 ( ch3_dac_Set1 ) + ,.ch3_dac_Set2 ( ch3_dac_Set2 ) + ,.ch3_dac_Set3 ( ch3_dac_Set3 ) + ,.ch3_dac_Set4 ( ch3_dac_Set4 ) + ,.ch3_dac_Set5 ( ch3_dac_Set5 ) + ,.ch3_dac_Set6 ( ch3_dac_Set6 ) + ,.ch3_dac_Set7 ( ch3_dac_Set7 ) + ,.ch3_dac_Set8 ( ch3_dac_Set8 ) + ,.ch3_dac_Set9 ( ch3_dac_Set9 ) + ,.ch3_dac_Set10 ( ch3_dac_Set10 ) + ,.ch3_dac_Set11 ( ch3_dac_Set11 ) + ,.ch3_dac_Set12 ( ch3_dac_Set12 ) + ,.ch3_dac_Set13 ( ch3_dac_Set13 ) + ,.ch3_dac_Set14 ( ch3_dac_Set14 ) + ,.ch3_dac_Set15 ( ch3_dac_Set15 ) + ,.ch3_dac_addr ( ch3_dac_addr ) + ,.ch3_dac_dw ( ch3_dac_dw ) + ,.ch3_dac_ref ( ch3_dac_ref ) + ,.ch3_dac_Prbs_rst0 ( ch3_dac_Prbs_rst0 ) + ,.ch3_dac_Prbs_set0 ( ch3_dac_Prbs_set0 ) + ,.ch3_dac_Prbs_rst1 ( ch3_dac_Prbs_rst1 ) + ,.ch3_dac_Prbs_set1 ( ch3_dac_Prbs_set1 ) + ,.ch3_dac_Cal_sig ( ch3_dac_Cal_sig ) + ,.ch3_dac_Cal_rstn ( ch3_dac_Cal_rstn ) + ,.ch3_dac_Reset ( ch3_dac_Reset ) + ,.ch3_dac_Digitalclk ( ch3_dac_Digitalclk ) + ,.ch3_dac_Cal_end ( ch3_dac_Cal_end ) + `endif + `ifdef CHANNEL_XY_ON + ,.ch0_xy_dsp_dout0 ( ch0_xy_dsp_dout0 ) + ,.ch0_xy_dsp_dout1 ( ch0_xy_dsp_dout1 ) + ,.ch0_xy_dsp_dout2 ( ch0_xy_dsp_dout2 ) + ,.ch0_xy_dsp_dout3 ( ch0_xy_dsp_dout3 ) + ,.ch0_xy_dsp_dout4 ( ch0_xy_dsp_dout4 ) + ,.ch0_xy_dsp_dout5 ( ch0_xy_dsp_dout5 ) + ,.ch0_xy_dsp_dout6 ( ch0_xy_dsp_dout6 ) + ,.ch0_xy_dsp_dout7 ( ch0_xy_dsp_dout7 ) + ,.ch0_xy_dsp_dout8 ( ch0_xy_dsp_dout8 ) + ,.ch0_xy_dsp_dout9 ( ch0_xy_dsp_dout9 ) + ,.ch0_xy_dsp_dout10 ( ch0_xy_dsp_dout10 ) + ,.ch0_xy_dsp_dout11 ( ch0_xy_dsp_dout11 ) + ,.ch0_xy_dsp_dout12 ( ch0_xy_dsp_dout12 ) + ,.ch0_xy_dsp_dout13 ( ch0_xy_dsp_dout13 ) + ,.ch0_xy_dsp_dout14 ( ch0_xy_dsp_dout14 ) + ,.ch0_xy_dsp_dout15 ( ch0_xy_dsp_dout15 ) + `endif + `ifdef CHANNEL_Z_ON + ,.ch0_z_dsp_dout0 ( ch0_z_dsp_dout0 ) + ,.ch0_z_dsp_dout1 ( ch0_z_dsp_dout1 ) + ,.ch0_z_dsp_dout2 ( ch0_z_dsp_dout2 ) + ,.ch0_z_dsp_dout3 ( ch0_z_dsp_dout3 ) + `endif + `ifdef CHANNEL_IS_FOUR + `ifdef CHANNEL_XY_ON + ,.ch1_xy_dsp_dout0 ( ch1_xy_dsp_dout0 ) + ,.ch1_xy_dsp_dout1 ( ch1_xy_dsp_dout1 ) + ,.ch1_xy_dsp_dout2 ( ch1_xy_dsp_dout2 ) + ,.ch1_xy_dsp_dout3 ( ch1_xy_dsp_dout3 ) + ,.ch1_xy_dsp_dout4 ( ch1_xy_dsp_dout4 ) + ,.ch1_xy_dsp_dout5 ( ch1_xy_dsp_dout5 ) + ,.ch1_xy_dsp_dout6 ( ch1_xy_dsp_dout6 ) + ,.ch1_xy_dsp_dout7 ( ch1_xy_dsp_dout7 ) + ,.ch1_xy_dsp_dout8 ( ch1_xy_dsp_dout8 ) + ,.ch1_xy_dsp_dout9 ( ch1_xy_dsp_dout9 ) + ,.ch1_xy_dsp_dout10 ( ch1_xy_dsp_dout10 ) + ,.ch1_xy_dsp_dout11 ( ch1_xy_dsp_dout11 ) + ,.ch1_xy_dsp_dout12 ( ch1_xy_dsp_dout12 ) + ,.ch1_xy_dsp_dout13 ( ch1_xy_dsp_dout13 ) + ,.ch1_xy_dsp_dout14 ( ch1_xy_dsp_dout14 ) + ,.ch1_xy_dsp_dout15 ( ch1_xy_dsp_dout15 ) + `endif + `ifdef CHANNEL_Z_ON + ,.ch1_z_dsp_dout0 ( ch1_z_dsp_dout0 ) + ,.ch1_z_dsp_dout1 ( ch1_z_dsp_dout1 ) + ,.ch1_z_dsp_dout2 ( ch1_z_dsp_dout2 ) + ,.ch1_z_dsp_dout3 ( ch1_z_dsp_dout3 ) + `endif + `ifdef CHANNEL_XY_ON + ,.ch2_xy_dsp_dout0 ( ch2_xy_dsp_dout0 ) + ,.ch2_xy_dsp_dout1 ( ch2_xy_dsp_dout1 ) + ,.ch2_xy_dsp_dout2 ( ch2_xy_dsp_dout2 ) + ,.ch2_xy_dsp_dout3 ( ch2_xy_dsp_dout3 ) + ,.ch2_xy_dsp_dout4 ( ch2_xy_dsp_dout4 ) + ,.ch2_xy_dsp_dout5 ( ch2_xy_dsp_dout5 ) + ,.ch2_xy_dsp_dout6 ( ch2_xy_dsp_dout6 ) + ,.ch2_xy_dsp_dout7 ( ch2_xy_dsp_dout7 ) + ,.ch2_xy_dsp_dout8 ( ch2_xy_dsp_dout8 ) + ,.ch2_xy_dsp_dout9 ( ch2_xy_dsp_dout9 ) + ,.ch2_xy_dsp_dout10 ( ch2_xy_dsp_dout10 ) + ,.ch2_xy_dsp_dout11 ( ch2_xy_dsp_dout11 ) + ,.ch2_xy_dsp_dout12 ( ch2_xy_dsp_dout12 ) + ,.ch2_xy_dsp_dout13 ( ch2_xy_dsp_dout13 ) + ,.ch2_xy_dsp_dout14 ( ch2_xy_dsp_dout14 ) + ,.ch2_xy_dsp_dout15 ( ch2_xy_dsp_dout15 ) + `endif + `ifdef CHANNEL_Z_ON + ,.ch2_z_dsp_dout0 ( ch2_z_dsp_dout0 ) + ,.ch2_z_dsp_dout1 ( ch2_z_dsp_dout1 ) + ,.ch2_z_dsp_dout2 ( ch2_z_dsp_dout2 ) + ,.ch2_z_dsp_dout3 ( ch2_z_dsp_dout3 ) + `endif + `ifdef CHANNEL_XY_ON + ,.ch3_xy_dsp_dout0 ( ch3_xy_dsp_dout0 ) + ,.ch3_xy_dsp_dout1 ( ch3_xy_dsp_dout1 ) + ,.ch3_xy_dsp_dout2 ( ch3_xy_dsp_dout2 ) + ,.ch3_xy_dsp_dout3 ( ch3_xy_dsp_dout3 ) + ,.ch3_xy_dsp_dout4 ( ch3_xy_dsp_dout4 ) + ,.ch3_xy_dsp_dout5 ( ch3_xy_dsp_dout5 ) + ,.ch3_xy_dsp_dout6 ( ch3_xy_dsp_dout6 ) + ,.ch3_xy_dsp_dout7 ( ch3_xy_dsp_dout7 ) + ,.ch3_xy_dsp_dout8 ( ch3_xy_dsp_dout8 ) + ,.ch3_xy_dsp_dout9 ( ch3_xy_dsp_dout9 ) + ,.ch3_xy_dsp_dout10 ( ch3_xy_dsp_dout10 ) + ,.ch3_xy_dsp_dout11 ( ch3_xy_dsp_dout11 ) + ,.ch3_xy_dsp_dout12 ( ch3_xy_dsp_dout12 ) + ,.ch3_xy_dsp_dout13 ( ch3_xy_dsp_dout13 ) + ,.ch3_xy_dsp_dout14 ( ch3_xy_dsp_dout14 ) + ,.ch3_xy_dsp_dout15 ( ch3_xy_dsp_dout15 ) + `endif + `ifdef CHANNEL_Z_ON + ,.ch3_z_dsp_dout0 ( ch3_z_dsp_dout0 ) + ,.ch3_z_dsp_dout1 ( ch3_z_dsp_dout1 ) + ,.ch3_z_dsp_dout2 ( ch3_z_dsp_dout2 ) + ,.ch3_z_dsp_dout3 ( ch3_z_dsp_dout3 ) + `endif + `endif +); + + +logic [31:0] cnt_c; + +wire add_cnt = 'b1; + +wire end_cnt = 1'b0; + +wire [31:0] cnt_n = end_cnt ? 32'h0 : + add_cnt ? cnt_c + 1'b1 : + cnt_c ; + + +sirv_gnrl_dffr #(32) cnt_c_dffr (cnt_n, cnt_c, clk_div16_0, async_rstn); + +initial begin + wait(cnt_c == 32'd100000); + $finish(0); +end + + +/////////////////////////////////////////////////////////////////////// +//XY DSP output data save +/////////////////////////////////////////////////////////////////////// + +logic [15:0] cs_wave; +wire [15:0] i_cs_0 = ch0_xy_dsp_dout0 ; +wire [15:0] i_cs_1 = ch0_xy_dsp_dout1 ; +wire [15:0] i_cs_2 = ch0_xy_dsp_dout2 ; +wire [15:0] i_cs_3 = ch0_xy_dsp_dout3 ; +wire [15:0] i_cs_4 = ch0_xy_dsp_dout4 ; +wire [15:0] i_cs_5 = ch0_xy_dsp_dout5 ; +wire [15:0] i_cs_6 = ch0_xy_dsp_dout6 ; +wire [15:0] i_cs_7 = ch0_xy_dsp_dout7 ; +wire [15:0] i_cs_8 = ch0_xy_dsp_dout8 ; +wire [15:0] i_cs_9 = ch0_xy_dsp_dout9 ; +wire [15:0] i_cs_a = ch0_xy_dsp_dout10; +wire [15:0] i_cs_b = ch0_xy_dsp_dout11; +wire [15:0] i_cs_c = ch0_xy_dsp_dout12; +wire [15:0] i_cs_d = ch0_xy_dsp_dout13; +wire [15:0] i_cs_e = ch0_xy_dsp_dout14; +wire [15:0] i_cs_f = ch0_xy_dsp_dout15; + +wire [2:0] intp_mode = U_digital_top.U0_channel_top.intp_mode; + +always@(*) + fork + case (intp_mode) + 3'b000 : begin + @(posedge clk_div16_f) + cs_wave = i_cs_0; + end + 3'b001 : begin + @(posedge clk_div16_f) + cs_wave = i_cs_0; + @(posedge clk_div16_7) + cs_wave = i_cs_1; + end + 3'b010 : begin + @(posedge clk_div16_f) + cs_wave = i_cs_0; + @(posedge clk_div16_b) + cs_wave = i_cs_1; + @(posedge clk_div16_7) + cs_wave = i_cs_2; + @(posedge clk_div16_3) + cs_wave = i_cs_3; + end + 3'b011 : begin + @(posedge clk_div16_f) + cs_wave = i_cs_0; + @(posedge clk_div16_d) + cs_wave = i_cs_1; + @(posedge clk_div16_b) + cs_wave = i_cs_2; + @(posedge clk_div16_9) + cs_wave = i_cs_3; + @(posedge clk_div16_7) + cs_wave = i_cs_4; + @(posedge clk_div16_5) + cs_wave = i_cs_5; + @(posedge clk_div16_3) + cs_wave = i_cs_6; + @(posedge clk_div16_1) + cs_wave = i_cs_7; + end + 3'b100 : begin + @(posedge clk_div16_f) + cs_wave = i_cs_0; + @(posedge clk_div16_e) + cs_wave = i_cs_1; + @(posedge clk_div16_d) + cs_wave = i_cs_2; + @(posedge clk_div16_c) + cs_wave = i_cs_3; + @(posedge clk_div16_b) + cs_wave = i_cs_4; + @(posedge clk_div16_a) + cs_wave = i_cs_5; + @(posedge clk_div16_9) + cs_wave = i_cs_6; + @(posedge clk_div16_8) + cs_wave = i_cs_7; + @(posedge clk_div16_7) + cs_wave = i_cs_8; + @(posedge clk_div16_6) + cs_wave = i_cs_9; + @(posedge clk_div16_5) + cs_wave = i_cs_a; + @(posedge clk_div16_4) + cs_wave = i_cs_b; + @(posedge clk_div16_3) + cs_wave = i_cs_c; + @(posedge clk_div16_2) + cs_wave = i_cs_d; + @(posedge clk_div16_1) + cs_wave = i_cs_e; + @(posedge clk_div16_0) + cs_wave = i_cs_f; + end + endcase +join + +integer XY_fid; + +always@(posedge clk) + if(U_digital_top.ch0_xy_dsp_dout_vld) + $fwrite(XY_fid,"%d\n",cs_wave); + +/////////////////////////////////////////////////////////////////////// +//Z DSP output data save +/////////////////////////////////////////////////////////////////////// + +logic [15:0] z_wave; +wire [15:0] z_cs_0 = ch0_z_dsp_dout0 ; +wire [15:0] z_cs_1 = ch0_z_dsp_dout1 ; +wire [15:0] z_cs_2 = ch0_z_dsp_dout2 ; +wire [15:0] z_cs_3 = ch0_z_dsp_dout3 ; + + +//wire [2:0] intp_mode = U_digital_top.U0_channel_top.intp_mode; + +always@(*) + fork + case (intp_mode) + 3'b000 : begin + @(posedge clk_div16_f) + z_wave = z_cs_0; + end + 3'b001 : begin + @(posedge clk_div16_f) + z_wave = z_cs_0; + @(posedge clk_div16_7) + z_wave = z_cs_1; + end + 3'b010 : begin + @(posedge clk_div16_f) + z_wave = z_cs_0; + @(posedge clk_div16_b) + z_wave = z_cs_1; + @(posedge clk_div16_7) + z_wave = z_cs_2; + @(posedge clk_div16_3) + z_wave = z_cs_3; + end + endcase +join + +integer Z_fid; + +always@(posedge clk) + if(cnt_c > 22'd4096) + $fwrite(Z_fid,"%d\n",z_wave); + +wire [15 :0] ch0_mod_data_i = U_digital_top. U_debug_top.U_debug_sampling.ch0_mod_data_i ; +wire [15 :0] ch0_mod_data_q = U_digital_top. U_debug_top.U_debug_sampling.ch0_mod_data_q ; +wire ch0_mod_vld = U_digital_top. U_debug_top.U_debug_sampling.ch0_mod_vld ; + +integer dbg_mod_fid; + +initial begin + #0; + dbg_mod_fid = $fopen("./dbg_mod_data.dat"); +end + +always@(posedge clk_div16_0) + if(ch0_mod_vld) + $fwrite(dbg_mod_fid,"%h\n",{ch0_mod_data_i,ch0_mod_data_q}); + +wire [511:0] mod_data_c = U_digital_top.U_debug_top.U_debug_sampling.mod_data_c ; +wire mod_cen = U_digital_top.U_debug_top.U_debug_sampling.mod_cen ; + +integer dbg_mod_data_c_fid; + +initial begin + #0; + dbg_mod_data_c_fid = $fopen("./dbg_mod_data_c.dat"); +end + +always@(posedge clk_div16_0) + if(~mod_cen) + $fwrite(dbg_mod_data_c_fid,"%h\n",mod_data_c); + + +endmodule + +`include "chip_undefine.v" + diff --git a/tb/digital_top/chip_define.v b/tb/digital_top/chip_define.v new file mode 100644 index 0000000..5d16c3f --- /dev/null +++ b/tb/digital_top/chip_define.v @@ -0,0 +1,23 @@ + +//Defining Memory Types + +//`define BEHAVIOR_SIM +//`define XINLINX_FPGA +`define TSMC_IC +//Is the chip a 4-channel one? +//`define CHANNEL_IS_FOUR 1 + + +//Whether to instantiate the XY-channel +`define CHANNEL_XY_ON 1 +//Whether to instantiate the Z-channel +`define CHANNEL_Z_ON 1 + +//Setting the Number of SPI Slave Devices +`define SLVNUM 26 +//Whether SPI Bus Commands Are Buffered +`define SPIBUS_CMD_REG 1 +//Whether SPI Bus Readout Are Buffered +`define SPIBUS_OUT_REG 0 +//Whether Mod mux dout Are Buffered +//`define MODDOUT_MUX_REG diff --git a/tb/digital_top/chip_undefine.v b/tb/digital_top/chip_undefine.v new file mode 100644 index 0000000..b093466 --- /dev/null +++ b/tb/digital_top/chip_undefine.v @@ -0,0 +1,19 @@ + +//Is the chip a 4-channel one? +//`undef CHANNEL_IS_FOUR + + +//Whether to instantiate the XY-channel +`undef CHANNEL_XY_ON +//Whether to instantiate the Z-channel +`undef CHANNEL_Z_ON + +//Setting the Number of SPI Slave Devices +`undef SLVNUM +//Whether SPI Bus Commands Are Buffered +`undef SPIBUS_CMD_REG +//Whether SPI Bus Readout Are Buffered +`undef SPIBUS_OUT_REG + +//Whether Mod mux dout Are Buffered +//`undef MODDOUT_MUX_REG \ No newline at end of file diff --git a/tb/digital_top/clk_gen.v b/tb/digital_top/clk_gen.v new file mode 100644 index 0000000..a9b1e7b --- /dev/null +++ b/tb/digital_top/clk_gen.v @@ -0,0 +1,141 @@ +module clk_gen( + input rstn, + input clk, + output clk_div16_0, + output clk_div16_1, + output clk_div16_2, + output clk_div16_3, + output clk_div16_4, + output clk_div16_5, + output clk_div16_6, + output clk_div16_7, + output clk_div16_8, + output clk_div16_9, + output clk_div16_a, + output clk_div16_b, + output clk_div16_c, + output clk_div16_d, + output clk_div16_e, + output clk_div16_f, + + output clk_h, + output clk_l + ); + +reg [3:0] cnt_ini; +always@(posedge clk or negedge rstn) + if(!rstn) + cnt_ini <= 4'd0; + else if(cnt_ini <= 4'd7) + cnt_ini <= cnt_ini + 4'd1; + else + cnt_ini <= cnt_ini; +wire div_en; +assign div_en = (cnt_ini ==4'd8)? 1'b1:1'b0; + +reg [3:0] cnt_0; +reg [3:0] cnt_1; +reg [3:0] cnt_2; +reg [3:0] cnt_3; +reg [3:0] cnt_4; +reg [3:0] cnt_5; +reg [3:0] cnt_6; +reg [3:0] cnt_7; +reg [3:0] cnt_8; +reg [3:0] cnt_9; +reg [3:0] cnt_a; +reg [3:0] cnt_b; +reg [3:0] cnt_c; +reg [3:0] cnt_d; +reg [3:0] cnt_e; +reg [3:0] cnt_f; + +always@(posedge clk or negedge rstn) + if(!rstn) begin + cnt_0 <= 4'h0; + cnt_1 <= 4'h1; + cnt_2 <= 4'h2; + cnt_3 <= 4'h3; + cnt_4 <= 4'h4; + cnt_5 <= 4'h5; + cnt_6 <= 4'h6; + cnt_7 <= 4'h7; + cnt_8 <= 4'h8; + cnt_9 <= 4'h9; + cnt_a <= 4'ha; + cnt_b <= 4'hb; + cnt_c <= 4'hc; + cnt_d <= 4'hd; + cnt_e <= 4'he; + cnt_f <= 4'hf; + end + else if(div_en) begin + cnt_0 <= cnt_0 + 4'd1; + cnt_1 <= cnt_1 + 4'd1; + cnt_2 <= cnt_2 + 4'd1; + cnt_3 <= cnt_3 + 4'd1; + cnt_4 <= cnt_4 + 4'd1; + cnt_5 <= cnt_5 + 4'd1; + cnt_6 <= cnt_6 + 4'd1; + cnt_7 <= cnt_7 + 4'd1; + cnt_8 <= cnt_8 + 4'd1; + cnt_9 <= cnt_9 + 4'd1; + cnt_a <= cnt_a + 4'd1; + cnt_b <= cnt_b + 4'd1; + cnt_c <= cnt_c + 4'd1; + cnt_d <= cnt_d + 4'd1; + cnt_e <= cnt_e + 4'd1; + cnt_f <= cnt_f + 4'd1; + end + else begin + cnt_0 <= cnt_0; + cnt_1 <= cnt_1; + cnt_2 <= cnt_2; + cnt_3 <= cnt_3; + cnt_4 <= cnt_4; + cnt_5 <= cnt_5; + cnt_6 <= cnt_6; + cnt_7 <= cnt_7; + cnt_8 <= cnt_8; + cnt_9 <= cnt_9; + cnt_a <= cnt_a; + cnt_b <= cnt_b; + cnt_c <= cnt_c; + cnt_d <= cnt_d; + cnt_e <= cnt_e; + cnt_f <= cnt_f; + + end + +assign clk_div16_0 = cnt_0[3]; +assign clk_div16_1 = cnt_1[3]; +assign clk_div16_2 = cnt_2[3]; +assign clk_div16_3 = cnt_3[3]; +assign clk_div16_4 = cnt_4[3]; +assign clk_div16_5 = cnt_5[3]; +assign clk_div16_6 = cnt_6[3]; +assign clk_div16_7 = cnt_7[3]; +assign clk_div16_8 = cnt_8[3]; +assign clk_div16_9 = cnt_9[3]; +assign clk_div16_a = cnt_a[3]; +assign clk_div16_b = cnt_b[3]; +assign clk_div16_c = cnt_c[3]; +assign clk_div16_d = cnt_d[3]; +assign clk_div16_e = cnt_e[3]; +assign clk_div16_f = cnt_f[3]; + + +reg [3:0] cnt_div16; +always@(posedge clk_div16_0 or negedge rstn) + if(!rstn) + cnt_div16 <= 4'd0; + else if(div_en) + cnt_div16 <= cnt_div16 + 4'd1; + else + cnt_div16 <= cnt_div16; + + +assign clk_h = clk_div16_0; +assign clk_l = cnt_div16[0]; + +endmodule diff --git a/tb/digital_top/compile.log b/tb/digital_top/compile.log new file mode 100644 index 0000000..f00d8e6 --- /dev/null +++ b/tb/digital_top/compile.log @@ -0,0 +1,14 @@ +Command: vcs -full64 -sverilog +lint=TFIPC-L +v2k -debug_access+all +define+DUMP_FSDB \ +-lca -q -timescale=1ns/1ps +nospecify -P /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab \ +/home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/pli.a -l compile.log \ +-f files.f + +Warning-[LCA_FEATURES_ENABLED] Usage warning + LCA features enabled by '-lca' argument on the command line. For more + information regarding list of LCA features please refer to Chapter "LCA + features" in the VCS/VCS-MX Release Notes + +The design hasn't changed and need not be recompiled. +If you really want to, delete file simv.daidir/.vcs.timestamp and +run VCS again. + diff --git a/tb/digital_top/csrc/Makefile b/tb/digital_top/csrc/Makefile new file mode 100644 index 0000000..ef00a4f --- /dev/null +++ b/tb/digital_top/csrc/Makefile @@ -0,0 +1,116 @@ +# Makefile generated by VCS to build your model +# This file may be modified; VCS will not overwrite it unless -Mupdate is used + +# define default verilog source directory +VSRC=.. + +# Override TARGET_ARCH +TARGET_ARCH= + +# Choose name of executable +PRODUCTBASE=$(VSRC)/simv + +PRODUCT=$(PRODUCTBASE) + +# Product timestamp file. If product is newer than this one, +# we will also re-link the product. +PRODUCT_TIMESTAMP=product_timestamp + +# Path to runtime library +DEPLIBS= +VCSUCLI=-lvcsucli +RUNTIME=-lvcsnew -lsimprofile -luclinative /home/synopsys/vcs/O-2018.09-SP2/linux64/lib/vcs_tls.o $(DEPLIBS) + +VCS_SAVE_RESTORE_OBJ=/home/synopsys/vcs/O-2018.09-SP2/linux64/lib/vcs_save_restore_new.o + +# Select your favorite compiler + +# Linux: +VCS_CC=gcc + +# Internal CC for gen_c flow: +CC_CG=gcc +# User overrode default CC: +VCS_CC=gcc +# Loader +LD=g++ + +# Strip Flags for target product +STRIPFLAGS= + +PRE_LDFLAGS= # Loader Flags +LDFLAGS= -rdynamic -Wl,-rpath=/home/synopsys/vcs/O-2018.09-SP2/linux64/lib -L/home/synopsys/vcs/O-2018.09-SP2/linux64/lib +# Picarchive Flags +PICLDFLAGS=-Wl,-rpath-link=./ -Wl,-rpath='$$ORIGIN'/simv.daidir/ -Wl,-rpath=./simv.daidir/ -Wl,-rpath='$$ORIGIN'/simv.daidir//scsim.db.dir + +# C run time startup +CRT0= +# C run time startup +CRTN= +# Machine specific libraries +SYSLIBS=/home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/pli.a -ldl -lm -lc -lpthread -ldl + +# Default defines +SHELL=/bin/sh + +VCSTMPSPECARG= +VCSTMPSPECENV= +# NOTE: if you have little space in $TMPDIR, but plenty in /foo, +#and you are using gcc, uncomment the next line +#VCSTMPSPECENV=SNPS_VCS_TMPDIR=/foo + +TMPSPECARG=$(VCSTMPSPECARG) +TMPSPECENV=$(VCSTMPSPECENV) +CC=$(TMPSPECENV) $(VCS_CC) $(TMPSPECARG) + +# C flags for compilation +CFLAGS=-w -pipe -fPIC -O -I/home/synopsys/vcs/O-2018.09-SP2/include + +CFLAGS_O0=-w -pipe -fPIC -I/home/synopsys/vcs/O-2018.09-SP2/include -O0 -fno-strict-aliasing + +CFLAGS_CG=-w -pipe -fPIC -I/home/synopsys/vcs/O-2018.09-SP2/include -O -fno-strict-aliasing + +LD_PARTIAL_LOADER=ld +# Partial linking +LD_PARTIAL=$(LD_PARTIAL_LOADER) -r -o +ASFLAGS= +LIBS=-lzerosoft_rt_stubs -lvirsim -lerrorinf -lsnpsmalloc -lvfs /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/pli.a +# Note: if make gives you errors about include, either get gmake, or +# replace the following line with the contents of the file filelist, +# EACH TIME IT CHANGES +# included file defines OBJS, and is automatically generated by vcs +include filelist + +OBJS=$(VLOG_OBJS) $(SYSC_OBJS) $(VHDL_OBJS) + +product : $(PRODUCT_TIMESTAMP) + @echo $(PRODUCT) up to date + +objects : $(OBJS) $(DPI_STUB_OBJS) $(PLI_STUB_OBJS) + +clean : + rm -f $(VCS_OBJS) $(CU_OBJS) + +clobber : clean + rm -f $(PRODUCT) $(PRODUCT_TIMESTAMP) + +picclean : + @rm -f _csrc*.so pre_vcsobj_*.so share_vcsobj_*.so + @rm -f $(PRODUCT).daidir/_[0-9]*_archive_*.so 2>/dev/null + +product_clean_order : + @$(MAKE) -f Makefile --no-print-directory picclean + @$(MAKE) -f Makefile --no-print-directory product_order + +product_order : $(PRODUCT) + +$(PRODUCT_TIMESTAMP) : product_clean_order + @-if [ -x $(PRODUCT) ]; then chmod -x $(PRODUCT); fi + @$(LD) $(CRT0) -o $(PRODUCT) $(PRE_LDFLAGS) $(STRIPFLAGS) $(PCLDFLAGS) $(PICLDFLAGS) $(LDFLAGS) $(OBJS) $(LIBS) $(RUNTIME) -Wl,-whole-archive $(VCSUCLI) -Wl,-no-whole-archive $(LINK_TB) $(DPI_STUB_OBJS) $(PLI_STUB_OBJS) $(VCS_SAVE_RESTORE_OBJ) $(SYSLIBS) $(CRTN) + @rm -f csrc[0-9]*.o + @touch $(PRODUCT_TIMESTAMP) + @-if [ -d ./objs ]; then find ./objs -type d -empty -delete; fi + +$(PRODUCT) : $(LD_VERSION_CHECK) $(OBJS) $(DOTLIBS) $(DPI_STUB_OBJS) $(PLI_STUB_OBJS) $(CMODLIB) /home/synopsys/vcs/O-2018.09-SP2/linux64/lib/libvcsnew.so /home/synopsys/vcs/O-2018.09-SP2/linux64/lib/libsimprofile.so /home/synopsys/vcs/O-2018.09-SP2/linux64/lib/libuclinative.so /home/synopsys/vcs/O-2018.09-SP2/linux64/lib/vcs_tls.o /home/synopsys/vcs/O-2018.09-SP2/linux64/lib/libvcsucli.so $(VCS_SAVE_RESTORE_OBJ) + @touch $(PRODUCT) + diff --git a/tb/digital_top/csrc/Makefile.hsopt b/tb/digital_top/csrc/Makefile.hsopt new file mode 100644 index 0000000..6d6350b --- /dev/null +++ b/tb/digital_top/csrc/Makefile.hsopt @@ -0,0 +1,47 @@ +# Makefile generated by VCS to build rmapats.so for your model +VSRC=.. + +# Override TARGET_ARCH +TARGET_ARCH= + +# Select your favorite compiler + +# Linux: +VCS_CC=gcc + +# Internal CC for gen_c flow: +CC_CG=gcc + +# User overrode default CC: +VCS_CC=gcc +# Loader +LD=g++ +# Loader Flags +LDFLAGS= + +# Default defines +SHELL=/bin/sh + +VCSTMPSPECARG= +VCSTMPSPECENV= +# NOTE: if you have little space in $TMPDIR, but plenty in /foo, +#and you are using gcc, uncomment the next line +#VCSTMPSPECENV=SNPS_VCS_TMPDIR=/foo + +TMPSPECARG=$(VCSTMPSPECARG) +TMPSPECENV=$(VCSTMPSPECENV) +CC=$(TMPSPECENV) $(VCS_CC) $(TMPSPECARG) + +# C flags for compilation +CFLAGS=-w -pipe -fPIC -O -I/home/synopsys/vcs/O-2018.09-SP2/include + +CFLAGS_CG=-w -pipe -fPIC -I/home/synopsys/vcs/O-2018.09-SP2/include -O -fno-strict-aliasing + +ASFLAGS= +LIBS= + +include filelist.hsopt + + +rmapats.so: $(HSOPT_OBJS) + @$(VCS_CC) $(LDFLAGS) $(LIBS) -shared -o ./../simv.daidir/rmapats.so $(HSOPT_OBJS) diff --git a/tb/digital_top/csrc/SIM_l.o b/tb/digital_top/csrc/SIM_l.o new file mode 100644 index 0000000..8fd683e Binary files /dev/null and b/tb/digital_top/csrc/SIM_l.o differ diff --git a/tb/digital_top/csrc/_100465_archive_1.so b/tb/digital_top/csrc/_100465_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_10107_archive_1.so b/tb/digital_top/csrc/_10107_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_101457_archive_1.so b/tb/digital_top/csrc/_101457_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_103000_archive_1.so b/tb/digital_top/csrc/_103000_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_104123_archive_1.so b/tb/digital_top/csrc/_104123_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_104304_archive_1.so b/tb/digital_top/csrc/_104304_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_105845_archive_1.so b/tb/digital_top/csrc/_105845_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_10628_archive_1.so b/tb/digital_top/csrc/_10628_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_106838_archive_1.so b/tb/digital_top/csrc/_106838_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_107734_archive_1.so b/tb/digital_top/csrc/_107734_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_108724_archive_1.so b/tb/digital_top/csrc/_108724_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_109401_archive_1.so b/tb/digital_top/csrc/_109401_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_110299_archive_1.so b/tb/digital_top/csrc/_110299_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_110792_archive_1.so b/tb/digital_top/csrc/_110792_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_11097_archive_1.so b/tb/digital_top/csrc/_11097_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_111620_archive_1.so b/tb/digital_top/csrc/_111620_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_111941_archive_1.so b/tb/digital_top/csrc/_111941_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_111974_archive_1.so b/tb/digital_top/csrc/_111974_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_113252_archive_1.so b/tb/digital_top/csrc/_113252_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_113679_archive_1.so b/tb/digital_top/csrc/_113679_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_113694_archive_1.so b/tb/digital_top/csrc/_113694_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_116446_archive_1.so b/tb/digital_top/csrc/_116446_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_116511_archive_1.so b/tb/digital_top/csrc/_116511_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_116685_archive_1.so b/tb/digital_top/csrc/_116685_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_117252_archive_1.so b/tb/digital_top/csrc/_117252_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_118384_archive_1.so b/tb/digital_top/csrc/_118384_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_118420_archive_1.so b/tb/digital_top/csrc/_118420_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_11863_archive_1.so b/tb/digital_top/csrc/_11863_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_120277_archive_1.so b/tb/digital_top/csrc/_120277_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_121354_archive_1.so b/tb/digital_top/csrc/_121354_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_121770_archive_1.so b/tb/digital_top/csrc/_121770_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_12224_archive_1.so b/tb/digital_top/csrc/_12224_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_122576_archive_1.so b/tb/digital_top/csrc/_122576_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_122637_archive_1.so b/tb/digital_top/csrc/_122637_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_123963_archive_1.so b/tb/digital_top/csrc/_123963_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_125013_archive_1.so b/tb/digital_top/csrc/_125013_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_125231_archive_1.so b/tb/digital_top/csrc/_125231_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_125905_archive_1.so b/tb/digital_top/csrc/_125905_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_12599_archive_1.so b/tb/digital_top/csrc/_12599_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_126055_archive_1.so b/tb/digital_top/csrc/_126055_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_126124_archive_1.so b/tb/digital_top/csrc/_126124_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_127235_archive_1.so b/tb/digital_top/csrc/_127235_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_127242_archive_1.so b/tb/digital_top/csrc/_127242_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_127852_archive_1.so b/tb/digital_top/csrc/_127852_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_128035_archive_1.so b/tb/digital_top/csrc/_128035_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_128512_archive_1.so b/tb/digital_top/csrc/_128512_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_12886_archive_1.so b/tb/digital_top/csrc/_12886_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_128934_archive_1.so b/tb/digital_top/csrc/_128934_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_129545_archive_1.so b/tb/digital_top/csrc/_129545_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_130246_archive_1.so b/tb/digital_top/csrc/_130246_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_130443_archive_1.so b/tb/digital_top/csrc/_130443_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_130911_archive_1.so b/tb/digital_top/csrc/_130911_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_13194_archive_1.so b/tb/digital_top/csrc/_13194_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_1376_archive_1.so b/tb/digital_top/csrc/_1376_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_13895_archive_1.so b/tb/digital_top/csrc/_13895_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_14056_archive_1.so b/tb/digital_top/csrc/_14056_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_15358_archive_1.so b/tb/digital_top/csrc/_15358_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_17413_archive_1.so b/tb/digital_top/csrc/_17413_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_17954_archive_1.so b/tb/digital_top/csrc/_17954_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_19122_archive_1.so b/tb/digital_top/csrc/_19122_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_19228_archive_1.so b/tb/digital_top/csrc/_19228_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_20415_archive_1.so b/tb/digital_top/csrc/_20415_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_20450_archive_1.so b/tb/digital_top/csrc/_20450_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_21557_archive_1.so b/tb/digital_top/csrc/_21557_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_21590_archive_1.so b/tb/digital_top/csrc/_21590_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_22700_archive_1.so b/tb/digital_top/csrc/_22700_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_23008_archive_1.so b/tb/digital_top/csrc/_23008_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_23612_archive_1.so b/tb/digital_top/csrc/_23612_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_25781_archive_1.so b/tb/digital_top/csrc/_25781_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_25832_archive_1.so b/tb/digital_top/csrc/_25832_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_27589_archive_1.so b/tb/digital_top/csrc/_27589_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_2769_archive_1.so b/tb/digital_top/csrc/_2769_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_29046_archive_1.so b/tb/digital_top/csrc/_29046_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_3127_archive_1.so b/tb/digital_top/csrc/_3127_archive_1.so new file mode 100644 index 0000000..124ddb2 Binary files /dev/null and b/tb/digital_top/csrc/_3127_archive_1.so differ diff --git a/tb/digital_top/csrc/_31328_archive_1.so b/tb/digital_top/csrc/_31328_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_32266_archive_1.so b/tb/digital_top/csrc/_32266_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_32494_archive_1.so b/tb/digital_top/csrc/_32494_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_33358_archive_1.so b/tb/digital_top/csrc/_33358_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_33454_archive_1.so b/tb/digital_top/csrc/_33454_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_33711_archive_1.so b/tb/digital_top/csrc/_33711_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_34450_archive_1.so b/tb/digital_top/csrc/_34450_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_35049_archive_1.so b/tb/digital_top/csrc/_35049_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_35129_archive_1.so b/tb/digital_top/csrc/_35129_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_3531_archive_1.so b/tb/digital_top/csrc/_3531_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_35452_archive_1.so b/tb/digital_top/csrc/_35452_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_35599_archive_1.so b/tb/digital_top/csrc/_35599_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_36208_archive_1.so b/tb/digital_top/csrc/_36208_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_36310_archive_1.so b/tb/digital_top/csrc/_36310_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_36378_archive_1.so b/tb/digital_top/csrc/_36378_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_367_archive_1.so b/tb/digital_top/csrc/_367_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_37047_archive_1.so b/tb/digital_top/csrc/_37047_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_37342_archive_1.so b/tb/digital_top/csrc/_37342_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_3744_archive_1.so b/tb/digital_top/csrc/_3744_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_37480_archive_1.so b/tb/digital_top/csrc/_37480_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_37595_archive_1.so b/tb/digital_top/csrc/_37595_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_39113_archive_1.so b/tb/digital_top/csrc/_39113_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_39709_archive_1.so b/tb/digital_top/csrc/_39709_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_40881_archive_1.so b/tb/digital_top/csrc/_40881_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_41038_archive_1.so b/tb/digital_top/csrc/_41038_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_41391_archive_1.so b/tb/digital_top/csrc/_41391_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_42151_archive_1.so b/tb/digital_top/csrc/_42151_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_42645_archive_1.so b/tb/digital_top/csrc/_42645_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_43357_archive_1.so b/tb/digital_top/csrc/_43357_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_43398_archive_1.so b/tb/digital_top/csrc/_43398_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_44208_archive_1.so b/tb/digital_top/csrc/_44208_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_47050_archive_1.so b/tb/digital_top/csrc/_47050_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_5192_archive_1.so b/tb/digital_top/csrc/_5192_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_5931_archive_1.so b/tb/digital_top/csrc/_5931_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_60878_archive_1.so b/tb/digital_top/csrc/_60878_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_62150_archive_1.so b/tb/digital_top/csrc/_62150_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_62238_archive_1.so b/tb/digital_top/csrc/_62238_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_63588_archive_1.so b/tb/digital_top/csrc/_63588_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_63835_archive_1.so b/tb/digital_top/csrc/_63835_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_63855_archive_1.so b/tb/digital_top/csrc/_63855_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_64586_archive_1.so b/tb/digital_top/csrc/_64586_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_64715_archive_1.so b/tb/digital_top/csrc/_64715_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_66400_archive_1.so b/tb/digital_top/csrc/_66400_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_66851_archive_1.so b/tb/digital_top/csrc/_66851_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_68264_archive_1.so b/tb/digital_top/csrc/_68264_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_6831_archive_1.so b/tb/digital_top/csrc/_6831_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_69660_archive_1.so b/tb/digital_top/csrc/_69660_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_72002_archive_1.so b/tb/digital_top/csrc/_72002_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_72058_archive_1.so b/tb/digital_top/csrc/_72058_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_73324_archive_1.so b/tb/digital_top/csrc/_73324_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_75989_archive_1.so b/tb/digital_top/csrc/_75989_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_76123_archive_1.so b/tb/digital_top/csrc/_76123_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_76582_archive_1.so b/tb/digital_top/csrc/_76582_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_76857_archive_1.so b/tb/digital_top/csrc/_76857_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_77744_archive_1.so b/tb/digital_top/csrc/_77744_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_7785_archive_1.so b/tb/digital_top/csrc/_7785_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_78691_archive_1.so b/tb/digital_top/csrc/_78691_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_81914_archive_1.so b/tb/digital_top/csrc/_81914_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_82804_archive_1.so b/tb/digital_top/csrc/_82804_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_84034_archive_1.so b/tb/digital_top/csrc/_84034_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_84928_archive_1.so b/tb/digital_top/csrc/_84928_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_85369_archive_1.so b/tb/digital_top/csrc/_85369_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_85683_archive_1.so b/tb/digital_top/csrc/_85683_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_86438_archive_1.so b/tb/digital_top/csrc/_86438_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_86888_archive_1.so b/tb/digital_top/csrc/_86888_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_86959_archive_1.so b/tb/digital_top/csrc/_86959_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_87361_archive_1.so b/tb/digital_top/csrc/_87361_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_88261_archive_1.so b/tb/digital_top/csrc/_88261_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_90723_archive_1.so b/tb/digital_top/csrc/_90723_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_90868_archive_1.so b/tb/digital_top/csrc/_90868_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_91006_archive_1.so b/tb/digital_top/csrc/_91006_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_91888_archive_1.so b/tb/digital_top/csrc/_91888_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_92476_archive_1.so b/tb/digital_top/csrc/_92476_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_93005_archive_1.so b/tb/digital_top/csrc/_93005_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_93061_archive_1.so b/tb/digital_top/csrc/_93061_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_93648_archive_1.so b/tb/digital_top/csrc/_93648_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_93651_archive_1.so b/tb/digital_top/csrc/_93651_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_93769_archive_1.so b/tb/digital_top/csrc/_93769_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_93943_archive_1.so b/tb/digital_top/csrc/_93943_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_94027_archive_1.so b/tb/digital_top/csrc/_94027_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_94639_archive_1.so b/tb/digital_top/csrc/_94639_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_94921_archive_1.so b/tb/digital_top/csrc/_94921_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_96081_archive_1.so b/tb/digital_top/csrc/_96081_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_96620_archive_1.so b/tb/digital_top/csrc/_96620_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_96958_archive_1.so b/tb/digital_top/csrc/_96958_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_97429_archive_1.so b/tb/digital_top/csrc/_97429_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_97436_archive_1.so b/tb/digital_top/csrc/_97436_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_99070_archive_1.so b/tb/digital_top/csrc/_99070_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_99277_archive_1.so b/tb/digital_top/csrc/_99277_archive_1.so new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/_prev_archive_1.so b/tb/digital_top/csrc/_prev_archive_1.so new file mode 100644 index 0000000..13e42bb Binary files /dev/null and b/tb/digital_top/csrc/_prev_archive_1.so differ diff --git a/tb/digital_top/csrc/_prev_cginfo.json b/tb/digital_top/csrc/_prev_cginfo.json new file mode 100644 index 0000000..02b44b1 --- /dev/null +++ b/tb/digital_top/csrc/_prev_cginfo.json @@ -0,0 +1,1126 @@ +{ + "cycles_program_begin": 5365254023434733, + "perf": [ + { + "stat": [ + "main", + "entry", + 0.010998010635375977, + 0.020944000000000001, + 0.0062830000000000004, + 219296, + 219296, + 0.0, + 0.0, + 1716628062.7482431, + 5365254023618961 + ], + "sub": [ + { + "stat": [ + "doParsingAndDesignResolution", + "entry", + 0.017252922058105469, + 0.023444, + 0.0086379999999999998, + 275204, + 276004, + 0.0, + 0.0, + 1716628062.754498, + 5365254044985144 + ], + "sub": [] + }, + { + "stat": [ + "doParsingAndDesignResolution", + "exit", + 0.12197184562683105, + 0.116482, + 0.020434999999999998, + 285272, + 285920, + 0.0, + 0.0, + 1716628062.8592169, + 5365254403409389 + ], + "sub": [] + }, + { + "stat": [ + "doPostDesignResolutionToVir2Vcs", + "entry", + 0.12591981887817383, + 0.12042899999999999, + 0.020434999999999998, + 285272, + 285920, + 0.0, + 0.0, + 1716628062.8631649, + 5365254416923102 + ], + "sub": [ + { + "stat": [ + "doUptoVir2VcsNoSepCleanup", + "entry", + 0.20213890075683594, + 0.19484199999999999, + 0.022325000000000001, + 289884, + 289888, + 0.0, + 0.0, + 1716628062.939384, + 5365254677743294 + ], + "sub": [] + }, + { + "stat": [ + "doUptoVir2VcsNoSepCleanup", + "exit", + 0.60333895683288574, + 0.574604, + 0.034273999999999999, + 312380, + 312404, + 0.001024, + 0.0086, + 1716628063.340584, + 5365256050658233 + ], + "sub": [] + }, + { + "stat": [ + "doRadify_vir2vcsAll", + "entry", + 0.60339879989624023, + 0.57466200000000001, + 0.034278000000000003, + 312380, + 312404, + 0.001024, + 0.0086, + 1716628063.3406439, + 5365256050786688 + ], + "sub": [] + }, + { + "stat": [ + "doRadify_vir2vcsAll", + "exit", + 0.63610982894897461, + 0.60338400000000003, + 0.038278, + 312380, + 312404, + 0.001024, + 0.0086, + 1716628063.3733549, + 5365256162797812 + ], + "sub": [] + } + ] + }, + { + "stat": [ + "doPostDesignResolutionToVir2Vcs", + "exit", + 0.63614892959594727, + 0.60342099999999999, + 0.038280000000000002, + 312380, + 312404, + 0.001024, + 0.0086, + 1716628063.373394, + 5365256162854232 + ], + "sub": [] + }, + { + "stat": [ + "doGAToPass2", + "entry", + 0.63616394996643066, + 0.60343500000000005, + 0.038281000000000003, + 312380, + 312404, + 0.001024, + 0.0086, + 1716628063.373409, + 5365256162899292 + ], + "sub": [ + { + "stat": [ + "DoPass2", + "entry", + 0.65217900276184082, + 0.60570999999999997, + 0.040245999999999997, + 309916, + 312404, + 0.0055579999999999996, + 0.016175999999999999, + 1716628063.3894241, + 5365256217764708 + ], + "sub": [] + }, + { + "stat": [ + "DoPass2", + "exit", + 1.0193369388580322, + 0.954677, + 0.057279999999999998, + 311892, + 312404, + 0.0063839999999999999, + 0.017002, + 1716628063.756582, + 5365257474162224 + ], + "sub": [] + } + ] + }, + { + "stat": [ + "doGAToPass2", + "exit", + 1.0213918685913086, + 0.95672599999999997, + 0.057282, + 311892, + 312404, + 0.0063839999999999999, + 0.017002, + 1716628063.758637, + 5365257481222923 + ], + "sub": [] + } + ] + }, + { + "stat": [ + "main", + "exit", + 1.0218160152435303, + 0.95712699999999995, + 0.057306999999999997, + 311884, + 312404, + 0.0063839999999999999, + 0.017002, + 1716628063.7590611, + 5365257482633053 + ], + "sub": [] + } + ], + "Misc": { + "vcs_version": "O-2018.09-SP2_Full64", + "csrc": "csrc", + "archive_dir": "archive.161", + "vcs_build_date": "Build Date = Feb 28 2019 22:34:30", + "VCS_HOME": "/home/synopsys/vcs/O-2018.09-SP2", + "master_pid": 367, + "default_output_dir": "csrc", + "csrc_abs": "/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/digital_top/csrc", + "hostname": "IC_EDA", + "daidir": "simv.daidir", + "cwd": "/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/digital_top", + "daidir_abs": "/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/digital_top/simv.daidir" + }, + "CompileProcesses": [ + "cgproc.367.json" + ], + "MlibObjs": {}, + "stat": { + "ru_self_end": { + "ru_minflt": 42150, + "ru_stime_sec": 0.057307999999999998, + "ru_utime_sec": 0.95716000000000001, + "ru_maxrss_kb": 111716, + "ru_majflt": 0, + "ru_nvcsw": 33, + "ru_nivcsw": 18 + }, + "ru_self_cgstart": { + "ru_minflt": 34742, + "ru_stime_sec": 0.040250000000000001, + "ru_utime_sec": 0.605765, + "ru_maxrss_kb": 102464, + "ru_majflt": 0, + "ru_nvcsw": 32, + "ru_nivcsw": 16 + }, + "ru_childs_cgstart": { + "ru_minflt": 10104, + "ru_stime_sec": 0.016175999999999999, + "ru_utime_sec": 0.0055579999999999996, + "ru_maxrss_kb": 45132, + "ru_majflt": 0, + "ru_nvcsw": 26, + "ru_nivcsw": 22 + }, + "cpu_cycles_cgstart": 5365256217897550, + "mop/quad": 3.0596252726979385, + "nMops": 436171, + "cpu_cycles_end": 5365257482707844, + "totalObjSize": 619628, + "nQuads": 142557, + "ru_childs_end": { + "ru_minflt": 10699, + "ru_stime_sec": 0.017002, + "ru_utime_sec": 0.0063839999999999999, + "ru_maxrss_kb": 45516, + "ru_majflt": 0, + "ru_nvcsw": 27, + "ru_nivcsw": 24 + }, + "CodeGen(%)": 36.554739586360355, + "cpu_cycles_total": 3459273111, + "quadSpeed": 404737.36659654026, + "mopSpeed": 1238344.6756439849, + "outputSizePerQuad": 4.3465280554444892, + "Frontend(%)": 63.445260413639645, + "peak_mem_kb": 312404, + "realTime": 1.0218667984008789 + }, + "PrevCompiledModules": { + "z_dsp": { + "zpIk1_d": { + "bytes": 88692, + "mod": "z_dsp", + "mode": 4, + "checksum": 0, + "out": "zpIk1_d.o", + "archive": "archive.161/_prev_archive_1.a" + } + }, + "tsdn28hpcpuhdb128x128m4mw_170a": { + "rShyv_d": { + "bytes": 297858, + "mod": "tsdn28hpcpuhdb128x128m4mw_170a", + "mode": 4, + "checksum": 0, + "out": "rShyv_d.o", + "archive": "archive.161/_prev_archive_1.a" + } + }, + "qbmcu_datalatch": { + "MsCBG_d": { + "bytes": 12266, + "mod": "qbmcu_datalatch", + "mode": 4, + "checksum": 0, + "out": "MsCBG_d.o", + "archive": "archive.161/_prev_archive_1.a" + } + }, + "std": { + "reYIK_d": { + "bytes": 43000, + "mod": "std", + "mode": 4, + "checksum": 0, + "out": "reYIK_d.o", + "archive": "archive.161/_prev_archive_1.a" + } + }, + "sram_if": { + "NABmh_d": { + "bytes": 16326, + "mod": "sram_if", + "mode": 4, + "checksum": 0, + "out": "NABmh_d.o", + "archive": "archive.161/_prev_archive_1.a" + } + }, + "DUC_HB2": { + "ksFw4_d": { + "bytes": 60820, + "mod": "DUC_HB2", + "mode": 4, + "checksum": 0, + "out": "ksFw4_d.o", + "archive": "archive.161/_prev_archive_1.a" + } + }, + "sirv_gnrl_ltch": { + "UTi0b_d": { + "bytes": 9700, + "mod": "sirv_gnrl_ltch", + "mode": 4, + "checksum": 0, + "out": "UTi0b_d.o", + "archive": "archive.161/_prev_archive_1.a" + } + }, + "channel_top": { + "xFWdC_d": { + "bytes": 468752, + "mod": "channel_top", + "mode": 4, + "checksum": 0, + "out": "xFWdC_d.o", + "archive": "archive.161/_prev_archive_1.a" + } + }, + "DUC4": { + "cwtAY_d": { + "bytes": 302476, + "mod": "DUC4", + "mode": 4, + "checksum": 0, + "out": "cwtAY_d.o", + "archive": "archive.161/_prev_archive_1.a" + } + }, + "modout_mux": { + "jEu9i_d": { + "bytes": 10794, + "mod": "modout_mux", + "mode": 4, + "checksum": 0, + "out": "jEu9i_d.o", + "archive": "archive.161/_prev_archive_1.a" + } + }, + "DW_mult_pipe_0000_0002": { + "SiiVi_d": { + "bytes": 41994, + "mod": "DW_mult_pipe_0000_0002", + "mode": 4, + "checksum": 0, + "out": "SiiVi_d.o", + "archive": "archive.161/_prev_archive_1.a" + } + }, + "DW_mult_pipe_0000_0000": { + "HNRiG_d": { + "bytes": 38420, + "mod": "DW_mult_pipe_0000_0000", + "mode": 4, + "checksum": 0, + "out": "HNRiG_d.o", + "archive": "archive.161/_prev_archive_1.a" + } + }, + "qbmcu_busdecoder": { + "jAiwN_d": { + "bytes": 16690, + "mod": "qbmcu_busdecoder", + "mode": 4, + "checksum": 0, + "out": "jAiwN_d.o", + "archive": "archive.161/_prev_archive_1.a" + } + }, + "rst_gen_unit": { + "anuMN_d": { + "bytes": 21774, + "mod": "rst_gen_unit", + "mode": 4, + "checksum": 0, + "out": "anuMN_d.o", + "archive": "archive.161/_prev_archive_1.a" + } + }, + "intpll_regfile": { + "Gw2LN_d": { + "bytes": 188388, + "mod": "intpll_regfile", + "mode": 4, + "checksum": 0, + "out": "Gw2LN_d.o", + "archive": "archive.161/_prev_archive_1.a" + } + }, + "TB": { + "sH4Fc_d": { + "bytes": 216624, + "mod": "TB", + "mode": 4, + "checksum": 0, + "out": "sH4Fc_d.o", + "archive": "archive.161/_prev_archive_1.a" + } + }, + "DUC_HB3": { + "Rdd8k_d": { + "bytes": 44056, + "mod": "DUC_HB3", + "mode": 4, + "checksum": 0, + "out": "Rdd8k_d.o", + "archive": "archive.161/_prev_archive_1.a" + } + }, + "dac_regfile": { + "LR0zI_d": { + "bytes": 118956, + "mod": "dac_regfile", + "mode": 4, + "checksum": 0, + "out": "LR0zI_d.o", + "archive": "archive.161/_prev_archive_1.a" + } + }, + "DW02_mult_0004": { + "hwIug_d": { + "bytes": 29288, + "mod": "DW02_mult_0004", + "mode": 4, + "checksum": 0, + "out": "hwIug_d.o", + "archive": "archive.161/_prev_archive_1.a" + } + }, + "DW_mult_pipe_0000_0003": { + "ZpmS6_d": { + "bytes": 37410, + "mod": "DW_mult_pipe_0000_0003", + "mode": 4, + "checksum": 0, + "out": "ZpmS6_d.o", + "archive": "archive.161/_prev_archive_1.a" + } + }, + "DUC_HB4": { + "zwWSN_d": { + "bytes": 39014, + "mod": "DUC_HB4", + "mode": 4, + "checksum": 0, + "out": "zwWSN_d.o", + "archive": "archive.161/_prev_archive_1.a" + } + }, + "debug_top": { + "gNaPt_d": { + "bytes": 108122, + "mod": "debug_top", + "mode": 4, + "checksum": 0, + "out": "gNaPt_d.o", + "archive": "archive.161/_prev_archive_1.a" + } + }, + "ctrl_regfile": { + "mLA3J_d": { + "bytes": 251072, + "mod": "ctrl_regfile", + "mode": 4, + "checksum": 0, + "out": "mLA3J_d.o", + "archive": "archive.161/_prev_archive_1.a" + } + }, + "DW01_addsub": { + "KysYq_d": { + "bytes": 18370, + "mod": "DW01_addsub", + "mode": 4, + "checksum": 0, + "out": "KysYq_d.o", + "archive": "archive.161/_prev_archive_1.a" + } + }, + "spi_if": { + "IHYdB_d": { + "bytes": 11636, + "mod": "spi_if", + "mode": 4, + "checksum": 0, + "out": "IHYdB_d.o", + "archive": "archive.161/_prev_archive_1.a" + } + }, + "digital_top": { + "rTmJG_d": { + "bytes": 455898, + "mod": "digital_top", + "archive": "archive.161/_367_archive_1.a", + "out": "rTmJG_d.o", + "mode": 4, + "checksum": 0 + } + }, + "param_lut_0002": { + "nJN5E_d": { + "bytes": 19394, + "mod": "param_lut_0002", + "mode": 4, + "checksum": 0, + "out": "nJN5E_d.o", + "archive": "archive.161/_prev_archive_1.a" + } + }, + "DW02_mult_0005": { + "UIt6b_d": { + "bytes": 29268, + "mod": "DW02_mult_0005", + "mode": 4, + "checksum": 0, + "out": "UIt6b_d.o", + "archive": "archive.161/_prev_archive_1.a" + } + }, + "qbmcu_regfile_0000": { + "Hit7c_d": { + "bytes": 92426, + "mod": "qbmcu_regfile_0000", + "archive": "archive.161/_prev_archive_1.a", + "out": "Hit7c_d.o", + "mode": 4, + "checksum": 0 + } + }, + "mcu_regfile": { + "HWLgR_d": { + "bytes": 226690, + "mod": "mcu_regfile", + "mode": 4, + "checksum": 0, + "out": "HWLgR_d.o", + "archive": "archive.161/_prev_archive_1.a" + } + }, + "system_regfile": { + "W3x1b_d": { + "bytes": 141826, + "mod": "system_regfile", + "mode": 4, + "checksum": 0, + "out": "W3x1b_d.o", + "archive": "archive.161/_prev_archive_1.a" + } + }, + "TSDN28HPCPUHDB4096X32M4MWR_Int_Array": { + "e36VC_d": { + "bytes": 106790, + "mod": "TSDN28HPCPUHDB4096X32M4MWR_Int_Array", + "mode": 4, + "checksum": 0, + "out": "e36VC_d.o", + "archive": "archive.161/_prev_archive_1.a" + } + }, + "tsdn28hpcpuhdb128x128m4mw_170a_Int_Array": { + "eFLuy_d": { + "bytes": 66736, + "mod": "tsdn28hpcpuhdb128x128m4mw_170a_Int_Array", + "mode": 4, + "checksum": 0, + "out": "eFLuy_d.o", + "archive": "archive.161/_prev_archive_1.a" + } + }, + "tsdn28hpcpuhdb4096x32m4mw_170a_Int_Array": { + "ay4xz_d": { + "bytes": 66252, + "mod": "tsdn28hpcpuhdb4096x32m4mw_170a_Int_Array", + "mode": 4, + "checksum": 0, + "out": "ay4xz_d.o", + "archive": "archive.161/_prev_archive_1.a" + } + }, + "TSDN28HPCPUHDB4096X32M4MWR": { + "Sg3ri_d": { + "bytes": 122964, + "mod": "TSDN28HPCPUHDB4096X32M4MWR", + "mode": 4, + "checksum": 0, + "out": "Sg3ri_d.o", + "archive": "archive.161/_prev_archive_1.a" + } + }, + "sram_if_0000": { + "nJgqZ_d": { + "bytes": 16568, + "mod": "sram_if_0000", + "mode": 4, + "checksum": 0, + "out": "nJgqZ_d.o", + "archive": "archive.161/_prev_archive_1.a" + } + }, + "qbmcu": { + "xnbfb_d": { + "bytes": 388698, + "mod": "qbmcu", + "mode": 4, + "checksum": 0, + "out": "xnbfb_d.o", + "archive": "archive.161/_prev_archive_1.a" + } + }, + "sirv_gnrl_dffl": { + "BM4bj_d": { + "bytes": 9566, + "mod": "sirv_gnrl_dffl", + "mode": 4, + "checksum": 0, + "out": "BM4bj_d.o", + "archive": "archive.161/_prev_archive_1.a" + } + }, + "PH2AMP": { + "iYIEc_d": { + "bytes": 158200, + "mod": "PH2AMP", + "mode": 4, + "checksum": 0, + "out": "iYIEc_d.o", + "archive": "archive.161/_prev_archive_1.a" + } + }, + "dacif": { + "SMgga_d": { + "bytes": 62530, + "mod": "dacif", + "mode": 4, + "checksum": 0, + "out": "SMgga_d.o", + "archive": "archive.161/_prev_archive_1.a" + } + }, + "_vcs_unit__504089786": { + "D1hM1_d": { + "bytes": 88168, + "mod": "_vcs_unit__504089786", + "mode": 4, + "checksum": 0, + "out": "D1hM1_d.o", + "archive": "archive.161/_prev_archive_1.a" + } + }, + "tsdn28hpcpuhdb64x32m4mw_170a_Int_Array": { + "JweIx_d": { + "bytes": 65620, + "mod": "tsdn28hpcpuhdb64x32m4mw_170a_Int_Array", + "mode": 4, + "checksum": 0, + "out": "JweIx_d.o", + "archive": "archive.161/_prev_archive_1.a" + } + }, + "...MASTER...": { + "amcQw_d": { + "bytes": 9160, + "mod": "...MASTER...", + "mode": 4, + "checksum": 0, + "out": "objs/amcQw_d.o" + } + }, + "IIR_Filter": { + "rLaFI_d": { + "bytes": 55838, + "mod": "IIR_Filter", + "mode": 4, + "checksum": 0, + "out": "rLaFI_d.o", + "archive": "archive.161/_prev_archive_1.a" + } + }, + "tsdn28hpcpuhdb4096x32m4mw_170a": { + "d6TPd_d": { + "bytes": 109700, + "mod": "tsdn28hpcpuhdb4096x32m4mw_170a", + "mode": 4, + "checksum": 0, + "out": "d6TPd_d.o", + "archive": "archive.161/_prev_archive_1.a" + } + }, + "xy_dsp": { + "U33JQ_d": { + "bytes": 380142, + "mod": "xy_dsp", + "mode": 4, + "checksum": 0, + "out": "U33JQ_d.o", + "archive": "archive.161/_prev_archive_1.a" + } + }, + "spi_slave": { + "eAsJz_d": { + "bytes": 308970, + "mod": "spi_slave", + "mode": 4, + "checksum": 0, + "out": "eAsJz_d.o", + "archive": "archive.161/_prev_archive_1.a" + } + } + }, + "NameTable": { + "TSDN28HPCPUHDB4096X32M4MWR_Int_Array": [ + "TSDN28HPCPUHDB4096X32M4MWR_Int_Array", + "e36VC", + "module", + 29 + ], + "sirv_gnrl_dffl": [ + "sirv_gnrl_dffl", + "BM4bj", + "module", + 8 + ], + "_vcs_unit__504089786": [ + "_vcs_unit__504089786", + "D1hM1", + "module", + 2 + ], + "dacif": [ + "dacif", + "SMgga", + "module", + 28 + ], + "std": [ + "std", + "reYIK", + "module", + 3 + ], + "qbmcu_datalatch": [ + "qbmcu_datalatch", + "MsCBG", + "module", + 22 + ], + "sram_if": [ + "sram_if", + "NABmh", + "module", + 4 + ], + "sram_if_0000": [ + "sram_if_0000", + "nJgqZ", + "module", + 5 + ], + "DW01_addsub": [ + "DW01_addsub", + "KysYq", + "module", + 40 + ], + "ctrl_regfile": [ + "ctrl_regfile", + "mLA3J", + "module", + 6 + ], + "DUC_HB2": [ + "DUC_HB2", + "ksFw4", + "module", + 30 + ], + "sirv_gnrl_ltch": [ + "sirv_gnrl_ltch", + "UTi0b", + "module", + 10 + ], + "channel_top": [ + "channel_top", + "xFWdC", + "module", + 27 + ], + "DUC4": [ + "DUC4", + "cwtAY", + "module", + 33 + ], + "modout_mux": [ + "modout_mux", + "jEu9i", + "module", + 15 + ], + "tsdn28hpcpuhdb4096x32m4mw_170a": [ + "tsdn28hpcpuhdb4096x32m4mw_170a", + "d6TPd", + "module", + 13 + ], + "xy_dsp": [ + "xy_dsp", + "U33JQ", + "module", + 16 + ], + "param_lut_0002": [ + "param_lut_0002", + "nJN5E", + "module", + 7 + ], + "TB": [ + "TB", + "sH4Fc", + "module", + 47 + ], + "intpll_regfile": [ + "intpll_regfile", + "Gw2LN", + "module", + 1 + ], + "rst_gen_unit": [ + "rst_gen_unit", + "anuMN", + "module", + 24 + ], + "DUC_HB3": [ + "DUC_HB3", + "Rdd8k", + "module", + 31 + ], + "dac_regfile": [ + "dac_regfile", + "LR0zI", + "module", + 11 + ], + "DUC_HB4": [ + "DUC_HB4", + "zwWSN", + "module", + 32 + ], + "debug_top": [ + "debug_top", + "gNaPt", + "module", + 12 + ], + "tsdn28hpcpuhdb4096x32m4mw_170a_Int_Array": [ + "tsdn28hpcpuhdb4096x32m4mw_170a_Int_Array", + "ay4xz", + "module", + 14 + ], + "tsdn28hpcpuhdb128x128m4mw_170a": [ + "tsdn28hpcpuhdb128x128m4mw_170a", + "rShyv", + "module", + 43 + ], + "tsdn28hpcpuhdb128x128m4mw_170a_Int_Array": [ + "tsdn28hpcpuhdb128x128m4mw_170a_Int_Array", + "eFLuy", + "module", + 9 + ], + "system_regfile": [ + "system_regfile", + "W3x1b", + "module", + 26 + ], + "TSDN28HPCPUHDB4096X32M4MWR": [ + "TSDN28HPCPUHDB4096X32M4MWR", + "Sg3ri", + "module", + 36 + ], + "tsdn28hpcpuhdb64x32m4mw_170a_Int_Array": [ + "tsdn28hpcpuhdb64x32m4mw_170a_Int_Array", + "JweIx", + "module", + 17 + ], + "PH2AMP": [ + "PH2AMP", + "iYIEc", + "module", + 18 + ], + "mcu_regfile": [ + "mcu_regfile", + "HWLgR", + "module", + 19 + ], + "DW_mult_pipe_0000_0002": [ + "DW_mult_pipe_0000_0002", + "SiiVi", + "module", + 38 + ], + "DW_mult_pipe_0000_0000": [ + "DW_mult_pipe_0000_0000", + "HNRiG", + "module", + 37 + ], + "qbmcu_busdecoder": [ + "qbmcu_busdecoder", + "jAiwN", + "module", + 21 + ], + "qbmcu": [ + "qbmcu", + "xnbfb", + "module", + 20 + ], + "qbmcu_regfile_0000": [ + "qbmcu_regfile_0000", + "Hit7c", + "module", + 23 + ], + "spi_slave": [ + "spi_slave", + "eAsJz", + "module", + 25 + ], + "digital_top": [ + "digital_top", + "rTmJG", + "module", + 46 + ], + "IIR_Filter": [ + "IIR_Filter", + "rLaFI", + "module", + 34 + ], + "z_dsp": [ + "z_dsp", + "zpIk1", + "module", + 35 + ], + "DW_mult_pipe_0000_0003": [ + "DW_mult_pipe_0000_0003", + "ZpmS6", + "module", + 39 + ], + "DW02_mult_0004": [ + "DW02_mult_0004", + "hwIug", + "module", + 41 + ], + "DW02_mult_0005": [ + "DW02_mult_0005", + "UIt6b", + "module", + 42 + ], + "spi_if": [ + "spi_if", + "IHYdB", + "module", + 44 + ], + "...MASTER...": [ + "SIM", + "amcQw", + "module", + 45 + ] + }, + "cpu_cycles_pass2_start": 5365256217784336, + "SIMBData": { + "archive": "archive.161/_367_archive_1.a", + "out": "amcQwB.o", + "bytes": 163906, + "text": 0 + }, + "PEModules": [], + "CurCompileUdps": {}, + "CompileStrategy": "fullobj", + "incremental": "on", + "CurCompileModules": [ + "...MASTER...", + "_vcs_unit__504089786", + "std", + "sram_if", + "sram_if_0000", + "ctrl_regfile", + "param_lut_0002", + "modout_mux", + "intpll_regfile", + "sirv_gnrl_dffl", + "sirv_gnrl_ltch", + "dac_regfile", + "debug_top", + "tsdn28hpcpuhdb128x128m4mw_170a", + "tsdn28hpcpuhdb128x128m4mw_170a_Int_Array", + "tsdn28hpcpuhdb4096x32m4mw_170a", + "tsdn28hpcpuhdb4096x32m4mw_170a_Int_Array", + "TSDN28HPCPUHDB4096X32M4MWR", + "TSDN28HPCPUHDB4096X32M4MWR_Int_Array", + "tsdn28hpcpuhdb64x32m4mw_170a_Int_Array", + "PH2AMP", + "mcu_regfile", + "qbmcu_busdecoder", + "qbmcu", + "qbmcu_datalatch", + "qbmcu_regfile_0000", + "rst_gen_unit", + "spi_slave", + "system_regfile", + "channel_top", + "digital_top", + "digital_top", + "dacif", + "xy_dsp", + "DUC_HB2", + "DUC_HB3", + "DUC_HB4", + "DUC4", + "IIR_Filter", + "z_dsp", + "TB", + "DW_mult_pipe_0000_0000", + "DW_mult_pipe_0000_0002", + "DW_mult_pipe_0000_0003", + "DW01_addsub", + "DW02_mult_0004", + "DW02_mult_0005", + "spi_if" + ], + "LVLData": [ + "SIM" + ], + "rlimit": { + "data": -1, + "stack": -1 + }, + "CompileStatus": "Successful" +} \ No newline at end of file diff --git a/tb/digital_top/csrc/_vcs_pli_stub_.c b/tb/digital_top/csrc/_vcs_pli_stub_.c new file mode 100644 index 0000000..e4d8eaa --- /dev/null +++ b/tb/digital_top/csrc/_vcs_pli_stub_.c @@ -0,0 +1,964 @@ +#ifndef _GNU_SOURCE +#define _GNU_SOURCE +#endif +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +extern void* VCS_dlsymLookup(const char *); +extern void vcsMsgReportNoSource1(const char *, const char*); + +/* PLI routine: $fsdbDumpvars:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbDumpvars +#define __VCS_PLI_STUB_novas_call_fsdbDumpvars +extern void novas_call_fsdbDumpvars(int data, int reason); +#pragma weak novas_call_fsdbDumpvars +void novas_call_fsdbDumpvars(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbDumpvars"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbDumpvars"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbDumpvars"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbDumpvars)(int data, int reason) = novas_call_fsdbDumpvars; +#endif /* __VCS_PLI_STUB_novas_call_fsdbDumpvars */ + +/* PLI routine: $fsdbDumpvars:misc */ +#ifndef __VCS_PLI_STUB_novas_misc +#define __VCS_PLI_STUB_novas_misc +extern void novas_misc(int data, int reason, int iparam ); +#pragma weak novas_misc +void novas_misc(int data, int reason, int iparam ) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason, int iparam ) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason, int iparam )) dlsym(RTLD_NEXT, "novas_misc"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason, int iparam )) VCS_dlsymLookup("novas_misc"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason, iparam ); + } +} +void (*__vcs_pli_dummy_reference_novas_misc)(int data, int reason, int iparam ) = novas_misc; +#endif /* __VCS_PLI_STUB_novas_misc */ + +/* PLI routine: $fsdbDumpvarsByFile:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbDumpvarsByFile +#define __VCS_PLI_STUB_novas_call_fsdbDumpvarsByFile +extern void novas_call_fsdbDumpvarsByFile(int data, int reason); +#pragma weak novas_call_fsdbDumpvarsByFile +void novas_call_fsdbDumpvarsByFile(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbDumpvarsByFile"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbDumpvarsByFile"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbDumpvarsByFile"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbDumpvarsByFile)(int data, int reason) = novas_call_fsdbDumpvarsByFile; +#endif /* __VCS_PLI_STUB_novas_call_fsdbDumpvarsByFile */ + +/* PLI routine: $fsdbAddRuntimeSignal:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbAddRuntimeSignal +#define __VCS_PLI_STUB_novas_call_fsdbAddRuntimeSignal +extern void novas_call_fsdbAddRuntimeSignal(int data, int reason); +#pragma weak novas_call_fsdbAddRuntimeSignal +void novas_call_fsdbAddRuntimeSignal(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbAddRuntimeSignal"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbAddRuntimeSignal"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbAddRuntimeSignal"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbAddRuntimeSignal)(int data, int reason) = novas_call_fsdbAddRuntimeSignal; +#endif /* __VCS_PLI_STUB_novas_call_fsdbAddRuntimeSignal */ + +/* PLI routine: $sps_create_transaction_stream:call */ +#ifndef __VCS_PLI_STUB_novas_call_sps_create_transaction_stream +#define __VCS_PLI_STUB_novas_call_sps_create_transaction_stream +extern void novas_call_sps_create_transaction_stream(int data, int reason); +#pragma weak novas_call_sps_create_transaction_stream +void novas_call_sps_create_transaction_stream(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_create_transaction_stream"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_create_transaction_stream"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_create_transaction_stream"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_sps_create_transaction_stream)(int data, int reason) = novas_call_sps_create_transaction_stream; +#endif /* __VCS_PLI_STUB_novas_call_sps_create_transaction_stream */ + +/* PLI routine: $sps_begin_transaction:call */ +#ifndef __VCS_PLI_STUB_novas_call_sps_begin_transaction +#define __VCS_PLI_STUB_novas_call_sps_begin_transaction +extern void novas_call_sps_begin_transaction(int data, int reason); +#pragma weak novas_call_sps_begin_transaction +void novas_call_sps_begin_transaction(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_begin_transaction"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_begin_transaction"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_begin_transaction"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_sps_begin_transaction)(int data, int reason) = novas_call_sps_begin_transaction; +#endif /* __VCS_PLI_STUB_novas_call_sps_begin_transaction */ + +/* PLI routine: $sps_end_transaction:call */ +#ifndef __VCS_PLI_STUB_novas_call_sps_end_transaction +#define __VCS_PLI_STUB_novas_call_sps_end_transaction +extern void novas_call_sps_end_transaction(int data, int reason); +#pragma weak novas_call_sps_end_transaction +void novas_call_sps_end_transaction(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_end_transaction"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_end_transaction"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_end_transaction"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_sps_end_transaction)(int data, int reason) = novas_call_sps_end_transaction; +#endif /* __VCS_PLI_STUB_novas_call_sps_end_transaction */ + +/* PLI routine: $sps_free_transaction:call */ +#ifndef __VCS_PLI_STUB_novas_call_sps_free_transaction +#define __VCS_PLI_STUB_novas_call_sps_free_transaction +extern void novas_call_sps_free_transaction(int data, int reason); +#pragma weak novas_call_sps_free_transaction +void novas_call_sps_free_transaction(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_free_transaction"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_free_transaction"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_free_transaction"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_sps_free_transaction)(int data, int reason) = novas_call_sps_free_transaction; +#endif /* __VCS_PLI_STUB_novas_call_sps_free_transaction */ + +/* PLI routine: $sps_add_attribute:call */ +#ifndef __VCS_PLI_STUB_novas_call_sps_add_attribute +#define __VCS_PLI_STUB_novas_call_sps_add_attribute +extern void novas_call_sps_add_attribute(int data, int reason); +#pragma weak novas_call_sps_add_attribute +void novas_call_sps_add_attribute(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_add_attribute"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_add_attribute"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_add_attribute"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_sps_add_attribute)(int data, int reason) = novas_call_sps_add_attribute; +#endif /* __VCS_PLI_STUB_novas_call_sps_add_attribute */ + +/* PLI routine: $sps_update_label:call */ +#ifndef __VCS_PLI_STUB_novas_call_sps_update_label +#define __VCS_PLI_STUB_novas_call_sps_update_label +extern void novas_call_sps_update_label(int data, int reason); +#pragma weak novas_call_sps_update_label +void novas_call_sps_update_label(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_update_label"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_update_label"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_update_label"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_sps_update_label)(int data, int reason) = novas_call_sps_update_label; +#endif /* __VCS_PLI_STUB_novas_call_sps_update_label */ + +/* PLI routine: $sps_add_relation:call */ +#ifndef __VCS_PLI_STUB_novas_call_sps_add_relation +#define __VCS_PLI_STUB_novas_call_sps_add_relation +extern void novas_call_sps_add_relation(int data, int reason); +#pragma weak novas_call_sps_add_relation +void novas_call_sps_add_relation(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_add_relation"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_add_relation"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_add_relation"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_sps_add_relation)(int data, int reason) = novas_call_sps_add_relation; +#endif /* __VCS_PLI_STUB_novas_call_sps_add_relation */ + +/* PLI routine: $fsdbWhatif:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbWhatif +#define __VCS_PLI_STUB_novas_call_fsdbWhatif +extern void novas_call_fsdbWhatif(int data, int reason); +#pragma weak novas_call_fsdbWhatif +void novas_call_fsdbWhatif(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbWhatif"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbWhatif"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbWhatif"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbWhatif)(int data, int reason) = novas_call_fsdbWhatif; +#endif /* __VCS_PLI_STUB_novas_call_fsdbWhatif */ + +/* PLI routine: $paa_init:call */ +#ifndef __VCS_PLI_STUB_novas_call_paa_init +#define __VCS_PLI_STUB_novas_call_paa_init +extern void novas_call_paa_init(int data, int reason); +#pragma weak novas_call_paa_init +void novas_call_paa_init(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_paa_init"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_paa_init"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_paa_init"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_paa_init)(int data, int reason) = novas_call_paa_init; +#endif /* __VCS_PLI_STUB_novas_call_paa_init */ + +/* PLI routine: $paa_sync:call */ +#ifndef __VCS_PLI_STUB_novas_call_paa_sync +#define __VCS_PLI_STUB_novas_call_paa_sync +extern void novas_call_paa_sync(int data, int reason); +#pragma weak novas_call_paa_sync +void novas_call_paa_sync(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_paa_sync"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_paa_sync"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_paa_sync"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_paa_sync)(int data, int reason) = novas_call_paa_sync; +#endif /* __VCS_PLI_STUB_novas_call_paa_sync */ + +/* PLI routine: $fsdbDumpClassMethod:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbDumpClassMethod +#define __VCS_PLI_STUB_novas_call_fsdbDumpClassMethod +extern void novas_call_fsdbDumpClassMethod(int data, int reason); +#pragma weak novas_call_fsdbDumpClassMethod +void novas_call_fsdbDumpClassMethod(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbDumpClassMethod"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbDumpClassMethod"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbDumpClassMethod"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbDumpClassMethod)(int data, int reason) = novas_call_fsdbDumpClassMethod; +#endif /* __VCS_PLI_STUB_novas_call_fsdbDumpClassMethod */ + +/* PLI routine: $fsdbSuppressClassMethod:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbSuppressClassMethod +#define __VCS_PLI_STUB_novas_call_fsdbSuppressClassMethod +extern void novas_call_fsdbSuppressClassMethod(int data, int reason); +#pragma weak novas_call_fsdbSuppressClassMethod +void novas_call_fsdbSuppressClassMethod(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbSuppressClassMethod"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbSuppressClassMethod"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbSuppressClassMethod"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbSuppressClassMethod)(int data, int reason) = novas_call_fsdbSuppressClassMethod; +#endif /* __VCS_PLI_STUB_novas_call_fsdbSuppressClassMethod */ + +/* PLI routine: $fsdbSuppressClassProp:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbSuppressClassProp +#define __VCS_PLI_STUB_novas_call_fsdbSuppressClassProp +extern void novas_call_fsdbSuppressClassProp(int data, int reason); +#pragma weak novas_call_fsdbSuppressClassProp +void novas_call_fsdbSuppressClassProp(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbSuppressClassProp"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbSuppressClassProp"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbSuppressClassProp"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbSuppressClassProp)(int data, int reason) = novas_call_fsdbSuppressClassProp; +#endif /* __VCS_PLI_STUB_novas_call_fsdbSuppressClassProp */ + +/* PLI routine: $fsdbDumpMDAByFile:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbDumpMDAByFile +#define __VCS_PLI_STUB_novas_call_fsdbDumpMDAByFile +extern void novas_call_fsdbDumpMDAByFile(int data, int reason); +#pragma weak novas_call_fsdbDumpMDAByFile +void novas_call_fsdbDumpMDAByFile(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbDumpMDAByFile"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbDumpMDAByFile"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbDumpMDAByFile"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbDumpMDAByFile)(int data, int reason) = novas_call_fsdbDumpMDAByFile; +#endif /* __VCS_PLI_STUB_novas_call_fsdbDumpMDAByFile */ + +/* PLI routine: $fsdbTrans_create_stream_begin:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_create_stream_begin +#define __VCS_PLI_STUB_novas_call_fsdbEvent_create_stream_begin +extern void novas_call_fsdbEvent_create_stream_begin(int data, int reason); +#pragma weak novas_call_fsdbEvent_create_stream_begin +void novas_call_fsdbEvent_create_stream_begin(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_create_stream_begin"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_create_stream_begin"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_create_stream_begin"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_create_stream_begin)(int data, int reason) = novas_call_fsdbEvent_create_stream_begin; +#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_create_stream_begin */ + +/* PLI routine: $fsdbTrans_define_attribute:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_add_stream_attribute +#define __VCS_PLI_STUB_novas_call_fsdbEvent_add_stream_attribute +extern void novas_call_fsdbEvent_add_stream_attribute(int data, int reason); +#pragma weak novas_call_fsdbEvent_add_stream_attribute +void novas_call_fsdbEvent_add_stream_attribute(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_add_stream_attribute"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_add_stream_attribute"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_add_stream_attribute"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_add_stream_attribute)(int data, int reason) = novas_call_fsdbEvent_add_stream_attribute; +#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_add_stream_attribute */ + +/* PLI routine: $fsdbTrans_create_stream_end:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_create_stream_end +#define __VCS_PLI_STUB_novas_call_fsdbEvent_create_stream_end +extern void novas_call_fsdbEvent_create_stream_end(int data, int reason); +#pragma weak novas_call_fsdbEvent_create_stream_end +void novas_call_fsdbEvent_create_stream_end(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_create_stream_end"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_create_stream_end"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_create_stream_end"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_create_stream_end)(int data, int reason) = novas_call_fsdbEvent_create_stream_end; +#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_create_stream_end */ + +/* PLI routine: $fsdbTrans_begin:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_begin +#define __VCS_PLI_STUB_novas_call_fsdbEvent_begin +extern void novas_call_fsdbEvent_begin(int data, int reason); +#pragma weak novas_call_fsdbEvent_begin +void novas_call_fsdbEvent_begin(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_begin"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_begin"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_begin"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_begin)(int data, int reason) = novas_call_fsdbEvent_begin; +#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_begin */ + +/* PLI routine: $fsdbTrans_set_label:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_set_label +#define __VCS_PLI_STUB_novas_call_fsdbEvent_set_label +extern void novas_call_fsdbEvent_set_label(int data, int reason); +#pragma weak novas_call_fsdbEvent_set_label +void novas_call_fsdbEvent_set_label(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_set_label"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_set_label"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_set_label"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_set_label)(int data, int reason) = novas_call_fsdbEvent_set_label; +#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_set_label */ + +/* PLI routine: $fsdbTrans_add_attribute:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_add_attribute +#define __VCS_PLI_STUB_novas_call_fsdbEvent_add_attribute +extern void novas_call_fsdbEvent_add_attribute(int data, int reason); +#pragma weak novas_call_fsdbEvent_add_attribute +void novas_call_fsdbEvent_add_attribute(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_add_attribute"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_add_attribute"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_add_attribute"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_add_attribute)(int data, int reason) = novas_call_fsdbEvent_add_attribute; +#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_add_attribute */ + +/* PLI routine: $fsdbTrans_add_tag:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_add_tag +#define __VCS_PLI_STUB_novas_call_fsdbEvent_add_tag +extern void novas_call_fsdbEvent_add_tag(int data, int reason); +#pragma weak novas_call_fsdbEvent_add_tag +void novas_call_fsdbEvent_add_tag(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_add_tag"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_add_tag"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_add_tag"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_add_tag)(int data, int reason) = novas_call_fsdbEvent_add_tag; +#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_add_tag */ + +/* PLI routine: $fsdbTrans_end:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_end +#define __VCS_PLI_STUB_novas_call_fsdbEvent_end +extern void novas_call_fsdbEvent_end(int data, int reason); +#pragma weak novas_call_fsdbEvent_end +void novas_call_fsdbEvent_end(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_end"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_end"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_end"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_end)(int data, int reason) = novas_call_fsdbEvent_end; +#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_end */ + +/* PLI routine: $fsdbTrans_add_relation:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_add_relation +#define __VCS_PLI_STUB_novas_call_fsdbEvent_add_relation +extern void novas_call_fsdbEvent_add_relation(int data, int reason); +#pragma weak novas_call_fsdbEvent_add_relation +void novas_call_fsdbEvent_add_relation(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_add_relation"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_add_relation"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_add_relation"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_add_relation)(int data, int reason) = novas_call_fsdbEvent_add_relation; +#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_add_relation */ + +/* PLI routine: $fsdbTrans_get_error_code:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_get_error_code +#define __VCS_PLI_STUB_novas_call_fsdbEvent_get_error_code +extern void novas_call_fsdbEvent_get_error_code(int data, int reason); +#pragma weak novas_call_fsdbEvent_get_error_code +void novas_call_fsdbEvent_get_error_code(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_get_error_code"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_get_error_code"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_get_error_code"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_get_error_code)(int data, int reason) = novas_call_fsdbEvent_get_error_code; +#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_get_error_code */ + +/* PLI routine: $fsdbTrans_add_stream_attribute:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbTrans_add_stream_attribute +#define __VCS_PLI_STUB_novas_call_fsdbTrans_add_stream_attribute +extern void novas_call_fsdbTrans_add_stream_attribute(int data, int reason); +#pragma weak novas_call_fsdbTrans_add_stream_attribute +void novas_call_fsdbTrans_add_stream_attribute(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbTrans_add_stream_attribute"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbTrans_add_stream_attribute"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbTrans_add_stream_attribute"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbTrans_add_stream_attribute)(int data, int reason) = novas_call_fsdbTrans_add_stream_attribute; +#endif /* __VCS_PLI_STUB_novas_call_fsdbTrans_add_stream_attribute */ + +/* PLI routine: $fsdbTrans_add_scope_attribute:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbTrans_add_scope_attribute +#define __VCS_PLI_STUB_novas_call_fsdbTrans_add_scope_attribute +extern void novas_call_fsdbTrans_add_scope_attribute(int data, int reason); +#pragma weak novas_call_fsdbTrans_add_scope_attribute +void novas_call_fsdbTrans_add_scope_attribute(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbTrans_add_scope_attribute"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbTrans_add_scope_attribute"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbTrans_add_scope_attribute"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbTrans_add_scope_attribute)(int data, int reason) = novas_call_fsdbTrans_add_scope_attribute; +#endif /* __VCS_PLI_STUB_novas_call_fsdbTrans_add_scope_attribute */ + +/* PLI routine: $sps_interactive:call */ +#ifndef __VCS_PLI_STUB_novas_call_sps_interactive +#define __VCS_PLI_STUB_novas_call_sps_interactive +extern void novas_call_sps_interactive(int data, int reason); +#pragma weak novas_call_sps_interactive +void novas_call_sps_interactive(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_interactive"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_interactive"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_interactive"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_sps_interactive)(int data, int reason) = novas_call_sps_interactive; +#endif /* __VCS_PLI_STUB_novas_call_sps_interactive */ + +/* PLI routine: $sps_test:call */ +#ifndef __VCS_PLI_STUB_novas_call_sps_test +#define __VCS_PLI_STUB_novas_call_sps_test +extern void novas_call_sps_test(int data, int reason); +#pragma weak novas_call_sps_test +void novas_call_sps_test(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_test"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_test"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_test"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_sps_test)(int data, int reason) = novas_call_sps_test; +#endif /* __VCS_PLI_STUB_novas_call_sps_test */ + +/* PLI routine: $fsdbDumpClassObject:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbDumpClassObject +#define __VCS_PLI_STUB_novas_call_fsdbDumpClassObject +extern void novas_call_fsdbDumpClassObject(int data, int reason); +#pragma weak novas_call_fsdbDumpClassObject +void novas_call_fsdbDumpClassObject(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbDumpClassObject"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbDumpClassObject"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbDumpClassObject"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbDumpClassObject)(int data, int reason) = novas_call_fsdbDumpClassObject; +#endif /* __VCS_PLI_STUB_novas_call_fsdbDumpClassObject */ + +/* PLI routine: $fsdbDumpClassObjectByFile:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbDumpClassObjectByFile +#define __VCS_PLI_STUB_novas_call_fsdbDumpClassObjectByFile +extern void novas_call_fsdbDumpClassObjectByFile(int data, int reason); +#pragma weak novas_call_fsdbDumpClassObjectByFile +void novas_call_fsdbDumpClassObjectByFile(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbDumpClassObjectByFile"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbDumpClassObjectByFile"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbDumpClassObjectByFile"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbDumpClassObjectByFile)(int data, int reason) = novas_call_fsdbDumpClassObjectByFile; +#endif /* __VCS_PLI_STUB_novas_call_fsdbDumpClassObjectByFile */ + +/* PLI routine: $ridbDump:call */ +#ifndef __VCS_PLI_STUB_novas_call_ridbDump +#define __VCS_PLI_STUB_novas_call_ridbDump +extern void novas_call_ridbDump(int data, int reason); +#pragma weak novas_call_ridbDump +void novas_call_ridbDump(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_ridbDump"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_ridbDump"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_ridbDump"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_ridbDump)(int data, int reason) = novas_call_ridbDump; +#endif /* __VCS_PLI_STUB_novas_call_ridbDump */ + +/* PLI routine: $sps_flush_file:call */ +#ifndef __VCS_PLI_STUB_novas_call_sps_flush_file +#define __VCS_PLI_STUB_novas_call_sps_flush_file +extern void novas_call_sps_flush_file(int data, int reason); +#pragma weak novas_call_sps_flush_file +void novas_call_sps_flush_file(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_flush_file"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_flush_file"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_flush_file"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_sps_flush_file)(int data, int reason) = novas_call_sps_flush_file; +#endif /* __VCS_PLI_STUB_novas_call_sps_flush_file */ + +/* PLI routine: $fsdbDumpSingle:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbDumpSingle +#define __VCS_PLI_STUB_novas_call_fsdbDumpSingle +extern void novas_call_fsdbDumpSingle(int data, int reason); +#pragma weak novas_call_fsdbDumpSingle +void novas_call_fsdbDumpSingle(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbDumpSingle"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbDumpSingle"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbDumpSingle"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbDumpSingle)(int data, int reason) = novas_call_fsdbDumpSingle; +#endif /* __VCS_PLI_STUB_novas_call_fsdbDumpSingle */ + +/* PLI routine: $fsdbDumpIO:call */ +#ifndef __VCS_PLI_STUB_novas_call_fsdbDumpIO +#define __VCS_PLI_STUB_novas_call_fsdbDumpIO +extern void novas_call_fsdbDumpIO(int data, int reason); +#pragma weak novas_call_fsdbDumpIO +void novas_call_fsdbDumpIO(int data, int reason) +{ + static int _vcs_pli_stub_initialized_ = 0; + static void (*_vcs_pli_fp_)(int data, int reason) = NULL; + if (!_vcs_pli_stub_initialized_) { + _vcs_pli_stub_initialized_ = 1; + _vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbDumpIO"); + if (_vcs_pli_fp_ == NULL) { + _vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbDumpIO"); + } + } + if (_vcs_pli_fp_) { + _vcs_pli_fp_(data, reason); + } else { + vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbDumpIO"); + } +} +void (*__vcs_pli_dummy_reference_novas_call_fsdbDumpIO)(int data, int reason) = novas_call_fsdbDumpIO; +#endif /* __VCS_PLI_STUB_novas_call_fsdbDumpIO */ + +#ifdef __cplusplus +} +#endif diff --git a/tb/digital_top/csrc/_vcs_pli_stub_.o b/tb/digital_top/csrc/_vcs_pli_stub_.o new file mode 100644 index 0000000..7927935 Binary files /dev/null and b/tb/digital_top/csrc/_vcs_pli_stub_.o differ diff --git a/tb/digital_top/csrc/archive.162/_3127_archive_1.a b/tb/digital_top/csrc/archive.162/_3127_archive_1.a new file mode 100644 index 0000000..f69d634 Binary files /dev/null and b/tb/digital_top/csrc/archive.162/_3127_archive_1.a differ diff --git a/tb/digital_top/csrc/archive.162/_3127_archive_1.a.info b/tb/digital_top/csrc/archive.162/_3127_archive_1.a.info new file mode 100644 index 0000000..81f9480 --- /dev/null +++ b/tb/digital_top/csrc/archive.162/_3127_archive_1.a.info @@ -0,0 +1,42 @@ +D1hM1_d.o +nJgqZ_d.o +nJN5E_d.o +BM4bj_d.o +UTi0b_d.o +LR0zI_d.o +gNaPt_d.o +rShyv_d.o +eFLuy_d.o +d6TPd_d.o +ay4xz_d.o +Sg3ri_d.o +e36VC_d.o +JweIx_d.o +iYIEc_d.o +HWLgR_d.o +jAiwN_d.o +xnbfb_d.o +MsCBG_d.o +Hit7c_d.o +anuMN_d.o +eAsJz_d.o +W3x1b_d.o +xFWdC_d.o +rTmJG_d.o +SMgga_d.o +U33JQ_d.o +ksFw4_d.o +Rdd8k_d.o +zwWSN_d.o +cwtAY_d.o +rLaFI_d.o +zpIk1_d.o +sH4Fc_d.o +HNRiG_d.o +SiiVi_d.o +ZpmS6_d.o +KysYq_d.o +hwIug_d.o +UIt6b_d.o +IHYdB_d.o +amcQwB.o diff --git a/tb/digital_top/csrc/archive.162/_prev_archive_1.a b/tb/digital_top/csrc/archive.162/_prev_archive_1.a new file mode 100644 index 0000000..e1bc451 Binary files /dev/null and b/tb/digital_top/csrc/archive.162/_prev_archive_1.a differ diff --git a/tb/digital_top/csrc/archive.162/_prev_archive_1.a.info b/tb/digital_top/csrc/archive.162/_prev_archive_1.a.info new file mode 100644 index 0000000..ae9799a --- /dev/null +++ b/tb/digital_top/csrc/archive.162/_prev_archive_1.a.info @@ -0,0 +1,4 @@ +jEu9i_d.o +NABmh_d.o +reYIK_d.o +mLA3J_d.o diff --git a/tb/digital_top/csrc/cgincr.sdb b/tb/digital_top/csrc/cgincr.sdb new file mode 100644 index 0000000..1d3ec5d Binary files /dev/null and b/tb/digital_top/csrc/cgincr.sdb differ diff --git a/tb/digital_top/csrc/cginfo.json b/tb/digital_top/csrc/cginfo.json new file mode 100644 index 0000000..f7b084b --- /dev/null +++ b/tb/digital_top/csrc/cginfo.json @@ -0,0 +1,1150 @@ +{ + "cycles_program_begin": 5366953823361191, + "cpu_cycles_pass2_start": 5366956015568938, + "NameTable": { + "dac_regfile": [ + "dac_regfile", + "LR0zI", + "module", + 11 + ], + "modout_mux": [ + "modout_mux", + "jEu9i", + "module", + 15 + ], + "tsdn28hpcpuhdb128x128m4mw_170a_Int_Array": [ + "tsdn28hpcpuhdb128x128m4mw_170a_Int_Array", + "eFLuy", + "module", + 9 + ], + "_vcs_unit__504089786": [ + "_vcs_unit__504089786", + "D1hM1", + "module", + 2 + ], + "std": [ + "std", + "reYIK", + "module", + 3 + ], + "tsdn28hpcpuhdb4096x32m4mw_170a": [ + "tsdn28hpcpuhdb4096x32m4mw_170a", + "d6TPd", + "module", + 13 + ], + "debug_top": [ + "debug_top", + "gNaPt", + "module", + 12 + ], + "sram_if": [ + "sram_if", + "NABmh", + "module", + 4 + ], + "spi_if": [ + "spi_if", + "IHYdB", + "module", + 44 + ], + "sram_if_0000": [ + "sram_if_0000", + "nJgqZ", + "module", + 5 + ], + "rst_gen_unit": [ + "rst_gen_unit", + "anuMN", + "module", + 24 + ], + "xy_dsp": [ + "xy_dsp", + "U33JQ", + "module", + 16 + ], + "ctrl_regfile": [ + "ctrl_regfile", + "mLA3J", + "module", + 6 + ], + "PH2AMP": [ + "PH2AMP", + "iYIEc", + "module", + 18 + ], + "DUC_HB3": [ + "DUC_HB3", + "Rdd8k", + "module", + 31 + ], + "param_lut_0002": [ + "param_lut_0002", + "nJN5E", + "module", + 7 + ], + "mcu_regfile": [ + "mcu_regfile", + "HWLgR", + "module", + 19 + ], + "sirv_gnrl_dffl": [ + "sirv_gnrl_dffl", + "BM4bj", + "module", + 8 + ], + "DW_mult_pipe_0000_0000": [ + "DW_mult_pipe_0000_0000", + "HNRiG", + "module", + 37 + ], + "sirv_gnrl_ltch": [ + "sirv_gnrl_ltch", + "UTi0b", + "module", + 10 + ], + "digital_top": [ + "digital_top", + "rTmJG", + "module", + 46 + ], + "tsdn28hpcpuhdb128x128m4mw_170a": [ + "tsdn28hpcpuhdb128x128m4mw_170a", + "rShyv", + "module", + 43 + ], + "DW02_mult_0005": [ + "DW02_mult_0005", + "UIt6b", + "module", + 42 + ], + "tsdn28hpcpuhdb4096x32m4mw_170a_Int_Array": [ + "tsdn28hpcpuhdb4096x32m4mw_170a_Int_Array", + "ay4xz", + "module", + 14 + ], + "qbmcu": [ + "qbmcu", + "xnbfb", + "module", + 20 + ], + "TSDN28HPCPUHDB4096X32M4MWR_Int_Array": [ + "TSDN28HPCPUHDB4096X32M4MWR_Int_Array", + "e36VC", + "module", + 29 + ], + "TSDN28HPCPUHDB4096X32M4MWR": [ + "TSDN28HPCPUHDB4096X32M4MWR", + "Sg3ri", + "module", + 36 + ], + "tsdn28hpcpuhdb64x32m4mw_170a_Int_Array": [ + "tsdn28hpcpuhdb64x32m4mw_170a_Int_Array", + "JweIx", + "module", + 17 + ], + "qbmcu_busdecoder": [ + "qbmcu_busdecoder", + "jAiwN", + "module", + 21 + ], + "qbmcu_datalatch": [ + "qbmcu_datalatch", + "MsCBG", + "module", + 22 + ], + "qbmcu_regfile_0000": [ + "qbmcu_regfile_0000", + "Hit7c", + "module", + 23 + ], + "dacif": [ + "dacif", + "SMgga", + "module", + 28 + ], + "...MASTER...": [ + "SIM", + "amcQw", + "module", + 45 + ], + "DUC4": [ + "DUC4", + "cwtAY", + "module", + 33 + ], + "spi_slave": [ + "spi_slave", + "eAsJz", + "module", + 25 + ], + "system_regfile": [ + "system_regfile", + "W3x1b", + "module", + 26 + ], + "channel_top": [ + "channel_top", + "xFWdC", + "module", + 27 + ], + "DUC_HB2": [ + "DUC_HB2", + "ksFw4", + "module", + 30 + ], + "DUC_HB4": [ + "DUC_HB4", + "zwWSN", + "module", + 32 + ], + "IIR_Filter": [ + "IIR_Filter", + "rLaFI", + "module", + 34 + ], + "z_dsp": [ + "z_dsp", + "zpIk1", + "module", + 35 + ], + "TB": [ + "TB", + "sH4Fc", + "module", + 47 + ], + "DW_mult_pipe_0000_0002": [ + "DW_mult_pipe_0000_0002", + "SiiVi", + "module", + 38 + ], + "DW_mult_pipe_0000_0003": [ + "DW_mult_pipe_0000_0003", + "ZpmS6", + "module", + 39 + ], + "DW01_addsub": [ + "DW01_addsub", + "KysYq", + "module", + 40 + ], + "DW02_mult_0004": [ + "DW02_mult_0004", + "hwIug", + "module", + 41 + ] + }, + "CompileStrategy": "fullobj", + "CurCompileUdps": {}, + "perf": [ + { + "stat": [ + "main", + "entry", + 0.011790990829467773, + 0.020036999999999999, + 0.01102, + 219296, + 219296, + 0.0, + 0.0, + 1716628560.19133, + 5366953823561524 + ], + "sub": [ + { + "stat": [ + "doParsingAndDesignResolution", + "entry", + 0.02102208137512207, + 0.021423999999999999, + 0.016274, + 275204, + 276004, + 0.0, + 0.0, + 1716628560.200561, + 5366953855018275 + ], + "sub": [] + }, + { + "stat": [ + "doParsingAndDesignResolution", + "exit", + 0.12056803703308105, + 0.109793, + 0.027196000000000001, + 285272, + 285920, + 0.0, + 0.0, + 1716628560.300107, + 5366954194667324 + ], + "sub": [] + }, + { + "stat": [ + "doPostDesignResolutionToVir2Vcs", + "entry", + 0.1245110034942627, + 0.112939, + 0.027984999999999999, + 285272, + 285920, + 0.0, + 0.0, + 1716628560.30405, + 5366954208021092 + ], + "sub": [ + { + "stat": [ + "doUptoVir2VcsNoSepCleanup", + "entry", + 0.1997830867767334, + 0.18601500000000001, + 0.030009000000000001, + 289884, + 289888, + 0.0, + 0.0, + 1716628560.3793221, + 5366954464712519 + ], + "sub": [] + }, + { + "stat": [ + "doUptoVir2VcsNoSepCleanup", + "exit", + 0.60324406623840332, + 0.55808999999999997, + 0.049917999999999997, + 313000, + 313024, + 0.0031089999999999998, + 0.0072459999999999998, + 1716628560.782783, + 5366955840802810 + ], + "sub": [] + }, + { + "stat": [ + "doRadify_vir2vcsAll", + "entry", + 0.60330414772033691, + 0.558145, + 0.049923000000000002, + 313000, + 313024, + 0.0031089999999999998, + 0.0072459999999999998, + 1716628560.7828431, + 5366955840937071 + ], + "sub": [] + }, + { + "stat": [ + "doRadify_vir2vcsAll", + "exit", + 0.63725709915161133, + 0.59003700000000003, + 0.051915000000000003, + 313000, + 313024, + 0.0031089999999999998, + 0.0072459999999999998, + 1716628560.8167961, + 5366955956827620 + ], + "sub": [] + } + ] + }, + { + "stat": [ + "doPostDesignResolutionToVir2Vcs", + "exit", + 0.63730311393737793, + 0.59007900000000002, + 0.051919, + 313000, + 313024, + 0.0031089999999999998, + 0.0072459999999999998, + 1716628560.8168421, + 5366955956888083 + ], + "sub": [] + }, + { + "stat": [ + "doGAToPass2", + "entry", + 0.63731694221496582, + 0.59009299999999998, + 0.051920000000000001, + 313000, + 313024, + 0.0031089999999999998, + 0.0072459999999999998, + 1716628560.8168559, + 5366955956932901 + ], + "sub": [ + { + "stat": [ + "DoPass2", + "entry", + 0.65396404266357422, + 0.59146500000000002, + 0.054857000000000003, + 310536, + 313024, + 0.0074060000000000003, + 0.015606999999999999, + 1716628560.833503, + 5366956015539767 + ], + "sub": [] + }, + { + "stat": [ + "DoPass2", + "exit", + 1.5563111305236816, + 1.4524219999999999, + 0.092771000000000006, + 312512, + 313024, + 0.0090399999999999994, + 0.015606999999999999, + 1716628561.7358501, + 5366959091315070 + ], + "sub": [] + } + ] + }, + { + "stat": [ + "doGAToPass2", + "exit", + 1.558398962020874, + 1.4525669999999999, + 0.094711000000000004, + 312512, + 313024, + 0.0090399999999999994, + 0.015606999999999999, + 1716628561.7379379, + 5366959098443430 + ], + "sub": [] + } + ] + }, + { + "stat": [ + "main", + "exit", + 1.5589349269866943, + 1.4530699999999999, + 0.094742999999999994, + 312504, + 313024, + 0.0090399999999999994, + 0.015606999999999999, + 1716628561.7384739, + 5366959100258927 + ], + "sub": [] + } + ], + "PEModules": [], + "MlibObjs": {}, + "CurCompileModules": [ + "...MASTER...", + "...MASTER...", + "_vcs_unit__504089786", + "_vcs_unit__504089786", + "std", + "sram_if", + "sram_if_0000", + "sram_if_0000", + "ctrl_regfile", + "param_lut_0002", + "param_lut_0002", + "modout_mux", + "sirv_gnrl_dffl", + "sirv_gnrl_dffl", + "sirv_gnrl_ltch", + "sirv_gnrl_ltch", + "dac_regfile", + "dac_regfile", + "debug_top", + "debug_top", + "tsdn28hpcpuhdb128x128m4mw_170a", + "tsdn28hpcpuhdb128x128m4mw_170a", + "tsdn28hpcpuhdb128x128m4mw_170a_Int_Array", + "tsdn28hpcpuhdb128x128m4mw_170a_Int_Array", + "tsdn28hpcpuhdb4096x32m4mw_170a", + "tsdn28hpcpuhdb4096x32m4mw_170a", + "tsdn28hpcpuhdb4096x32m4mw_170a_Int_Array", + "tsdn28hpcpuhdb4096x32m4mw_170a_Int_Array", + "TSDN28HPCPUHDB4096X32M4MWR", + "TSDN28HPCPUHDB4096X32M4MWR", + "TSDN28HPCPUHDB4096X32M4MWR_Int_Array", + "TSDN28HPCPUHDB4096X32M4MWR_Int_Array", + "tsdn28hpcpuhdb64x32m4mw_170a_Int_Array", + "tsdn28hpcpuhdb64x32m4mw_170a_Int_Array", + "PH2AMP", + "PH2AMP", + "mcu_regfile", + "mcu_regfile", + "qbmcu_busdecoder", + "qbmcu_busdecoder", + "qbmcu", + "qbmcu", + "qbmcu_datalatch", + "qbmcu_datalatch", + "qbmcu_regfile_0000", + "qbmcu_regfile_0000", + "rst_gen_unit", + "rst_gen_unit", + "spi_slave", + "spi_slave", + "system_regfile", + "system_regfile", + "channel_top", + "channel_top", + "digital_top", + "digital_top", + "dacif", + "dacif", + "xy_dsp", + "xy_dsp", + "DUC_HB2", + "DUC_HB2", + "DUC_HB3", + "DUC_HB3", + "DUC_HB4", + "DUC_HB4", + "DUC4", + "DUC4", + "IIR_Filter", + "IIR_Filter", + "z_dsp", + "z_dsp", + "TB", + "TB", + "DW_mult_pipe_0000_0000", + "DW_mult_pipe_0000_0000", + "DW_mult_pipe_0000_0002", + "DW_mult_pipe_0000_0002", + "DW_mult_pipe_0000_0003", + "DW_mult_pipe_0000_0003", + "DW01_addsub", + "DW01_addsub", + "DW02_mult_0004", + "DW02_mult_0004", + "DW02_mult_0005", + "DW02_mult_0005", + "spi_if", + "spi_if" + ], + "PrevCompiledModules": { + "DW02_mult_0004": { + "hwIug_d": { + "mode": 4, + "bytes": 29288, + "mod": "DW02_mult_0004", + "checksum": 0, + "archive": "archive.162/_3127_archive_1.a", + "out": "hwIug_d.o" + } + }, + "DW_mult_pipe_0000_0002": { + "SiiVi_d": { + "mode": 4, + "bytes": 41994, + "mod": "DW_mult_pipe_0000_0002", + "checksum": 0, + "archive": "archive.162/_3127_archive_1.a", + "out": "SiiVi_d.o" + } + }, + "tsdn28hpcpuhdb128x128m4mw_170a": { + "rShyv_d": { + "mode": 4, + "bytes": 297858, + "mod": "tsdn28hpcpuhdb128x128m4mw_170a", + "checksum": 0, + "archive": "archive.162/_3127_archive_1.a", + "out": "rShyv_d.o" + } + }, + "digital_top": { + "rTmJG_d": { + "mode": 4, + "bytes": 455722, + "mod": "digital_top", + "out": "rTmJG_d.o", + "checksum": 0, + "archive": "archive.162/_3127_archive_1.a" + } + }, + "qbmcu_datalatch": { + "MsCBG_d": { + "mode": 4, + "bytes": 12266, + "mod": "qbmcu_datalatch", + "checksum": 0, + "archive": "archive.162/_3127_archive_1.a", + "out": "MsCBG_d.o" + } + }, + "qbmcu_busdecoder": { + "jAiwN_d": { + "mode": 4, + "bytes": 16690, + "mod": "qbmcu_busdecoder", + "checksum": 0, + "archive": "archive.162/_3127_archive_1.a", + "out": "jAiwN_d.o" + } + }, + "DW01_addsub": { + "KysYq_d": { + "mode": 4, + "bytes": 18370, + "mod": "DW01_addsub", + "checksum": 0, + "archive": "archive.162/_3127_archive_1.a", + "out": "KysYq_d.o" + } + }, + "spi_slave": { + "eAsJz_d": { + "mode": 4, + "bytes": 308970, + "mod": "spi_slave", + "checksum": 0, + "archive": "archive.162/_3127_archive_1.a", + "out": "eAsJz_d.o" + } + }, + "...MASTER...": { + "amcQw_d": { + "mode": 4, + "bytes": 9160, + "mod": "...MASTER...", + "checksum": 0, + "out": "objs/amcQw_d.o" + } + }, + "DUC4": { + "cwtAY_d": { + "mode": 4, + "bytes": 302476, + "mod": "DUC4", + "checksum": 0, + "archive": "archive.162/_3127_archive_1.a", + "out": "cwtAY_d.o" + } + }, + "z_dsp": { + "zpIk1_d": { + "mode": 4, + "bytes": 88692, + "mod": "z_dsp", + "checksum": 0, + "archive": "archive.162/_3127_archive_1.a", + "out": "zpIk1_d.o" + } + }, + "modout_mux": { + "jEu9i_d": { + "mode": 4, + "bytes": 10794, + "mod": "modout_mux", + "checksum": 0, + "archive": "archive.162/_prev_archive_1.a", + "out": "jEu9i_d.o" + } + }, + "DW_mult_pipe_0000_0000": { + "HNRiG_d": { + "mode": 4, + "bytes": 38420, + "mod": "DW_mult_pipe_0000_0000", + "checksum": 0, + "archive": "archive.162/_3127_archive_1.a", + "out": "HNRiG_d.o" + } + }, + "sirv_gnrl_ltch": { + "UTi0b_d": { + "mode": 4, + "bytes": 9700, + "mod": "sirv_gnrl_ltch", + "checksum": 0, + "archive": "archive.162/_3127_archive_1.a", + "out": "UTi0b_d.o" + } + }, + "DW_mult_pipe_0000_0003": { + "ZpmS6_d": { + "mode": 4, + "bytes": 37410, + "mod": "DW_mult_pipe_0000_0003", + "checksum": 0, + "archive": "archive.162/_3127_archive_1.a", + "out": "ZpmS6_d.o" + } + }, + "DUC_HB2": { + "ksFw4_d": { + "mode": 4, + "bytes": 60820, + "mod": "DUC_HB2", + "checksum": 0, + "archive": "archive.162/_3127_archive_1.a", + "out": "ksFw4_d.o" + } + }, + "param_lut_0002": { + "nJN5E_d": { + "mode": 4, + "bytes": 19394, + "mod": "param_lut_0002", + "checksum": 0, + "archive": "archive.162/_3127_archive_1.a", + "out": "nJN5E_d.o" + } + }, + "DUC_HB3": { + "Rdd8k_d": { + "mode": 4, + "bytes": 44056, + "mod": "DUC_HB3", + "checksum": 0, + "archive": "archive.162/_3127_archive_1.a", + "out": "Rdd8k_d.o" + } + }, + "channel_top": { + "xFWdC_d": { + "mode": 4, + "bytes": 468752, + "mod": "channel_top", + "checksum": 0, + "archive": "archive.162/_3127_archive_1.a", + "out": "xFWdC_d.o" + } + }, + "DUC_HB4": { + "zwWSN_d": { + "mode": 4, + "bytes": 39014, + "mod": "DUC_HB4", + "checksum": 0, + "archive": "archive.162/_3127_archive_1.a", + "out": "zwWSN_d.o" + } + }, + "rst_gen_unit": { + "anuMN_d": { + "mode": 4, + "bytes": 21774, + "mod": "rst_gen_unit", + "checksum": 0, + "archive": "archive.162/_3127_archive_1.a", + "out": "anuMN_d.o" + } + }, + "sram_if_0000": { + "nJgqZ_d": { + "mode": 4, + "bytes": 16568, + "mod": "sram_if_0000", + "checksum": 0, + "archive": "archive.162/_3127_archive_1.a", + "out": "nJgqZ_d.o" + } + }, + "spi_if": { + "IHYdB_d": { + "mode": 4, + "bytes": 11636, + "mod": "spi_if", + "checksum": 0, + "archive": "archive.162/_3127_archive_1.a", + "out": "IHYdB_d.o" + } + }, + "tsdn28hpcpuhdb4096x32m4mw_170a": { + "d6TPd_d": { + "mode": 4, + "bytes": 109700, + "mod": "tsdn28hpcpuhdb4096x32m4mw_170a", + "checksum": 0, + "archive": "archive.162/_3127_archive_1.a", + "out": "d6TPd_d.o" + } + }, + "sram_if": { + "NABmh_d": { + "mode": 4, + "bytes": 16326, + "mod": "sram_if", + "checksum": 0, + "archive": "archive.162/_prev_archive_1.a", + "out": "NABmh_d.o" + } + }, + "debug_top": { + "gNaPt_d": { + "mode": 4, + "bytes": 108122, + "mod": "debug_top", + "checksum": 0, + "archive": "archive.162/_3127_archive_1.a", + "out": "gNaPt_d.o" + } + }, + "std": { + "reYIK_d": { + "mode": 4, + "bytes": 43000, + "mod": "std", + "checksum": 0, + "archive": "archive.162/_prev_archive_1.a", + "out": "reYIK_d.o" + } + }, + "qbmcu": { + "xnbfb_d": { + "mode": 4, + "bytes": 388698, + "mod": "qbmcu", + "checksum": 0, + "archive": "archive.162/_3127_archive_1.a", + "out": "xnbfb_d.o" + } + }, + "DW02_mult_0005": { + "UIt6b_d": { + "mode": 4, + "bytes": 29268, + "mod": "DW02_mult_0005", + "checksum": 0, + "archive": "archive.162/_3127_archive_1.a", + "out": "UIt6b_d.o" + } + }, + "tsdn28hpcpuhdb4096x32m4mw_170a_Int_Array": { + "ay4xz_d": { + "mode": 4, + "bytes": 66252, + "mod": "tsdn28hpcpuhdb4096x32m4mw_170a_Int_Array", + "checksum": 0, + "archive": "archive.162/_3127_archive_1.a", + "out": "ay4xz_d.o" + } + }, + "dacif": { + "SMgga_d": { + "mode": 4, + "bytes": 62530, + "mod": "dacif", + "checksum": 0, + "archive": "archive.162/_3127_archive_1.a", + "out": "SMgga_d.o" + } + }, + "qbmcu_regfile_0000": { + "Hit7c_d": { + "mode": 4, + "bytes": 92426, + "mod": "qbmcu_regfile_0000", + "checksum": 0, + "archive": "archive.162/_3127_archive_1.a", + "out": "Hit7c_d.o" + } + }, + "mcu_regfile": { + "HWLgR_d": { + "mode": 4, + "bytes": 226690, + "mod": "mcu_regfile", + "checksum": 0, + "archive": "archive.162/_3127_archive_1.a", + "out": "HWLgR_d.o" + } + }, + "system_regfile": { + "W3x1b_d": { + "mode": 4, + "bytes": 141826, + "mod": "system_regfile", + "checksum": 0, + "archive": "archive.162/_3127_archive_1.a", + "out": "W3x1b_d.o" + } + }, + "TSDN28HPCPUHDB4096X32M4MWR": { + "Sg3ri_d": { + "mode": 4, + "bytes": 122964, + "mod": "TSDN28HPCPUHDB4096X32M4MWR", + "checksum": 0, + "archive": "archive.162/_3127_archive_1.a", + "out": "Sg3ri_d.o" + } + }, + "TSDN28HPCPUHDB4096X32M4MWR_Int_Array": { + "e36VC_d": { + "mode": 4, + "bytes": 106790, + "mod": "TSDN28HPCPUHDB4096X32M4MWR_Int_Array", + "checksum": 0, + "archive": "archive.162/_3127_archive_1.a", + "out": "e36VC_d.o" + } + }, + "TB": { + "sH4Fc_d": { + "mode": 4, + "bytes": 216624, + "mod": "TB", + "checksum": 0, + "archive": "archive.162/_3127_archive_1.a", + "out": "sH4Fc_d.o" + } + }, + "_vcs_unit__504089786": { + "D1hM1_d": { + "mode": 4, + "bytes": 88168, + "mod": "_vcs_unit__504089786", + "checksum": 0, + "archive": "archive.162/_3127_archive_1.a", + "out": "D1hM1_d.o" + } + }, + "tsdn28hpcpuhdb128x128m4mw_170a_Int_Array": { + "eFLuy_d": { + "mode": 4, + "bytes": 66736, + "mod": "tsdn28hpcpuhdb128x128m4mw_170a_Int_Array", + "checksum": 0, + "archive": "archive.162/_3127_archive_1.a", + "out": "eFLuy_d.o" + } + }, + "dac_regfile": { + "LR0zI_d": { + "mode": 4, + "bytes": 118956, + "mod": "dac_regfile", + "checksum": 0, + "archive": "archive.162/_3127_archive_1.a", + "out": "LR0zI_d.o" + } + }, + "sirv_gnrl_dffl": { + "BM4bj_d": { + "mode": 4, + "bytes": 9566, + "mod": "sirv_gnrl_dffl", + "checksum": 0, + "archive": "archive.162/_3127_archive_1.a", + "out": "BM4bj_d.o" + } + }, + "PH2AMP": { + "iYIEc_d": { + "mode": 4, + "bytes": 158200, + "mod": "PH2AMP", + "checksum": 0, + "archive": "archive.162/_3127_archive_1.a", + "out": "iYIEc_d.o" + } + }, + "tsdn28hpcpuhdb64x32m4mw_170a_Int_Array": { + "JweIx_d": { + "mode": 4, + "bytes": 65620, + "mod": "tsdn28hpcpuhdb64x32m4mw_170a_Int_Array", + "checksum": 0, + "archive": "archive.162/_3127_archive_1.a", + "out": "JweIx_d.o" + } + }, + "IIR_Filter": { + "rLaFI_d": { + "mode": 4, + "bytes": 55838, + "mod": "IIR_Filter", + "checksum": 0, + "archive": "archive.162/_3127_archive_1.a", + "out": "rLaFI_d.o" + } + }, + "ctrl_regfile": { + "mLA3J_d": { + "mode": 4, + "bytes": 251072, + "mod": "ctrl_regfile", + "checksum": 0, + "archive": "archive.162/_prev_archive_1.a", + "out": "mLA3J_d.o" + } + }, + "xy_dsp": { + "U33JQ_d": { + "mode": 4, + "bytes": 380142, + "mod": "xy_dsp", + "checksum": 0, + "archive": "archive.162/_3127_archive_1.a", + "out": "U33JQ_d.o" + } + } + }, + "stat": { + "ru_childs_cgstart": { + "ru_utime_sec": 0.0074060000000000003, + "ru_minflt": 10104, + "ru_stime_sec": 0.015606999999999999, + "ru_maxrss_kb": 45648, + "ru_majflt": 0, + "ru_nvcsw": 24, + "ru_nivcsw": 22 + }, + "ru_self_cgstart": { + "ru_utime_sec": 0.59146500000000002, + "ru_minflt": 34701, + "ru_stime_sec": 0.055444, + "ru_maxrss_kb": 103136, + "ru_majflt": 0, + "ru_nvcsw": 31, + "ru_nivcsw": 12 + }, + "cpu_cycles_total": 5276996392, + "nQuads": 214379, + "nMops": 664558, + "cpu_cycles_cgstart": 5366956015713561, + "totalObjSize": 5322346, + "realTime": 1.5589950084686279, + "ru_childs_end": { + "ru_utime_sec": 0.0090399999999999994, + "ru_minflt": 10699, + "ru_stime_sec": 0.015606999999999999, + "ru_maxrss_kb": 46032, + "ru_majflt": 0, + "ru_nvcsw": 25, + "ru_nivcsw": 24 + }, + "mopSpeed": 769806.74845559779, + "ru_self_end": { + "ru_utime_sec": 1.4531100000000001, + "ru_minflt": 43109, + "ru_stime_sec": 0.094745999999999997, + "ru_maxrss_kb": 113780, + "ru_majflt": 0, + "ru_nvcsw": 32, + "ru_nivcsw": 14 + }, + "cpu_cycles_end": 5366959100357583, + "quadSpeed": 248331.0725732932, + "Frontend(%)": 40.958246417946178, + "CodeGen(%)": 59.041753582053822, + "mop/quad": 3.0999211676516825, + "outputSizePerQuad": 24.826806730136813, + "peak_mem_kb": 313024 + }, + "SIMBData": { + "out": "amcQwB.o", + "bytes": 169714, + "archive": "archive.162/_3127_archive_1.a", + "text": 0 + }, + "LVLData": [ + "SIM" + ], + "incremental": "on", + "CompileProcesses": [ + "cgproc.3127.json" + ], + "Misc": { + "cwd": "/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/digital_top", + "default_output_dir": "csrc", + "vcs_version": "O-2018.09-SP2_Full64", + "vcs_build_date": "Build Date = Feb 28 2019 22:34:30", + "hostname": "IC_EDA", + "csrc_abs": "/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/digital_top/csrc", + "master_pid": 3127, + "VCS_HOME": "/home/synopsys/vcs/O-2018.09-SP2", + "csrc": "csrc", + "daidir": "simv.daidir", + "daidir_abs": "/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/digital_top/simv.daidir", + "archive_dir": "archive.162" + }, + "rlimit": { + "stack": -1, + "data": -1 + }, + "CompileStatus": "Successful" +} \ No newline at end of file diff --git a/tb/digital_top/csrc/cgproc.3127.json b/tb/digital_top/csrc/cgproc.3127.json new file mode 100644 index 0000000..1fec2d8 --- /dev/null +++ b/tb/digital_top/csrc/cgproc.3127.json @@ -0,0 +1,1999 @@ +{ + "Modules": { + "PH2AMP": { + "start_perf": [ + 0.90703201293945312, + 0.82548100000000002, + 0.071779999999999997, + 312516, + 313024, + 1716628561.086571, + 5366956876836506 + ], + "child_modules": { + "DW_mult_pipe_0000_0000": 2 + }, + "Compiled": "Yes", + "nRouts": 435, + "nMops": 22628, + "nQuads": 8772, + "Compiled Times": 163, + "end_perf": [ + 0.93802213668823242, + 0.85540799999999995, + 0.072778999999999996, + 312516, + 313024, + 5366956982605397, + 184683593729, + 0 + ] + }, + "DUC_HB3": { + "start_perf": [ + 1.3760230541229248, + 1.2775129999999999, + 0.087760000000000005, + 312516, + 313024, + 1716628561.555562, + 5366958476397445 + ], + "child_modules": {}, + "Compiled": "Yes", + "nRouts": 107, + "nMops": 7360, + "nQuads": 1886, + "Compiled Times": 163, + "end_perf": [ + 1.3855690956115723, + 1.287039, + 0.087760000000000005, + 312516, + 313024, + 5366958508993029, + 339302416385, + 0 + ] + }, + "param_lut_0002": { + "start_perf": [ + 0.69298505783081055, + 0.61887300000000001, + 0.064777000000000001, + 312516, + 313024, + 1716628560.872524, + 5366956146798401 + ], + "child_modules": {}, + "Compiled": "Yes", + "nRouts": 46, + "nMops": 2028, + "nQuads": 530, + "Compiled Times": 163, + "end_perf": [ + 0.69748711585998535, + 0.62331700000000001, + 0.064824000000000007, + 312516, + 313024, + 5366956162201501, + 34359738369, + 0 + ] + }, + "DUC4": { + "start_perf": [ + 1.3940439224243164, + 1.2944979999999999, + 0.088759000000000005, + 312516, + 313024, + 1716628561.5735829, + 5366958537862536 + ], + "child_modules": { + "DUC_HB2": 2, + "DUC_HB3": 4, + "DUC_HB4": 8 + }, + "Compiled": "Yes", + "nRouts": 1018, + "nMops": 55264, + "nQuads": 18936, + "Compiled Times": 163, + "end_perf": [ + 1.4506981372833252, + 1.351035, + 0.088759000000000005, + 312516, + 313024, + 5366958731132881, + 356482285569, + 0 + ] + }, + "...MASTER...": { + "start_perf": [ + 0.65459203720092773, + 0.59146500000000002, + 0.055485, + 310536, + 313024, + 1716628560.834131, + 5366956015863029 + ], + "child_modules": { + "DW01_addsub": 1, + "_vcs_unit__504089786": 1, + "std": 1, + "TB": 1, + "tsdn28hpcpuhdb4096x32m4mw_170a": 1, + "sirv_gnrl_ltch": 1, + "sirv_gnrl_dffl": 1 + }, + "end_perf": [ + 0.6593470573425293, + 0.59146500000000002, + 0.058626999999999999, + 311532, + 313024, + 5366956032101465, + 0, + 0 + ], + "nRouts": 8, + "nMops": 14, + "nQuads": 8 + }, + "spi_slave": { + "start_perf": [ + 1.0679941177368164, + 0.97912699999999997, + 0.078768000000000005, + 312516, + 313024, + 1716628561.2475331, + 5366957425818309 + ], + "child_modules": {}, + "Compiled": "Yes", + "nRouts": 986, + "nMops": 25923, + "nQuads": 9699, + "Compiled Times": 163, + "end_perf": [ + 1.1163139343261719, + 1.027323, + 0.078794000000000003, + 312516, + 313024, + 5366957590662374, + 287762808833, + 0 + ] + }, + "dac_regfile": { + "start_perf": [ + 0.70262694358825684, + 0.62743599999999999, + 0.065835000000000005, + 312516, + 313024, + 1716628560.8821659, + 5366956179680442 + ], + "child_modules": {}, + "Compiled": "Yes", + "nRouts": 381, + "nMops": 18486, + "nQuads": 6198, + "Compiled Times": 163, + "end_perf": [ + 0.7235100269317627, + 0.64738200000000001, + 0.066729999999999998, + 312516, + 313024, + 5366956250987475, + 77309411329, + 0 + ] + }, + "modout_mux": { + "start_perf": [ + 0.69752097129821777, + 0.62334800000000001, + 0.064827999999999997, + 312516, + 313024, + 1716628560.8770599, + 5366956162268336 + ], + "child_modules": {}, + "Compiled": "Yes", + "nRouts": 23, + "nMops": 314, + "nQuads": 93, + "Compiled Times": 80, + "end_perf": [ + 0.69831013679504395, + 0.62334800000000001, + 0.065615000000000007, + 312516, + 313024, + 5366956164998383, + 38654705665, + 0 + ] + }, + "tsdn28hpcpuhdb128x128m4mw_170a_Int_Array": { + "start_perf": [ + 0.80225300788879395, + 0.72389499999999996, + 0.0688, + 312516, + 313024, + 1716628560.981792, + 5366956519469571 + ], + "significant_routs": [ + [ + 23, + "R_VCSgd_eFLuy_17", + 12801016, + 15741, + 1919 + ] + ], + "child_modules": {}, + "Compiled": "Yes", + "Compiled Times": 49, + "nQuads": 2502, + "nMops": 8246, + "end_perf": [ + 0.8163909912109375, + 0.73799199999999998, + 0.068811999999999998, + 312516, + 313024, + 5366956567732453, + 107374182401, + 0 + ], + "nRouts": 61 + }, + "_vcs_unit__504089786": { + "start_perf": [ + 0.65942001342773438, + 0.59146500000000002, + 0.058701000000000003, + 311532, + 313024, + 1716628560.838959, + 5366956032321372 + ], + "child_modules": {}, + "Compiled": "Yes", + "Compiled Times": 76, + "nQuads": 429, + "nMops": 1692, + "end_perf": [ + 0.66795897483825684, + 0.598885, + 0.059788000000000001, + 312516, + 313024, + 5366956061477408, + 4294967297, + 0 + ], + "svclass": [ + "BinaryDataReader", + 2977, + 297, + 4, + 4, + 4294978061, + "spi_data_send", + 4400, + 447, + 20, + 3, + 4294978101, + "spi_reg", + 7139, + 901, + 22, + 3, + 4294978129 + ], + "nRouts": 51 + }, + "std": { + "start_perf": [ + 0.66798996925354004, + 0.59891399999999995, + 0.059790999999999997, + 312516, + 313024, + 1716628560.8475289, + 5366956061549437 + ], + "child_modules": {}, + "Compiled": "Yes", + "Compiled Times": 163, + "nQuads": 218, + "nMops": 528, + "end_perf": [ + 0.66906595230102539, + 0.59898399999999996, + 0.060795000000000002, + 312516, + 313024, + 5366956065242891, + 8589934594, + 0 + ], + "svclass": [ + "$vcs_nba_dyn_obj", + 0, + 35, + 2, + 2, + 0, + "sigprop$$", + 0, + 35, + 2, + 2, + 0, + "process", + 0, + 200, + 8, + 8, + 0, + "event", + 0, + 34, + 2, + 2, + 0, + "mailbox", + 0, + 140, + 9, + 9, + 0, + "semaphore", + 0, + 84, + 5, + 5, + 0 + ], + "nRouts": 33 + }, + "tsdn28hpcpuhdb4096x32m4mw_170a": { + "start_perf": [ + 0.8164210319519043, + 0.73802000000000001, + 0.068815000000000001, + 312516, + 313024, + 1716628560.99596, + 5366956567842948 + ], + "child_modules": { + "tsdn28hpcpuhdb4096x32m4mw_170a_Int_Array": 1 + }, + "Compiled": "Yes", + "nRouts": 375, + "nMops": 20438, + "nQuads": 8228, + "Compiled Times": 163, + "end_perf": [ + 0.83657312393188477, + 0.75620699999999996, + 0.070737999999999995, + 312516, + 313024, + 5366956636564580, + 111669149697, + 0 + ] + }, + "debug_top": { + "start_perf": [ + 0.72355794906616211, + 0.64742599999999995, + 0.066734000000000002, + 312516, + 313024, + 1716628560.9030969, + 5366956251075196 + ], + "child_modules": { + "tsdn28hpcpuhdb128x128m4mw_170a": 2, + "sram_if_0000": 1 + }, + "Compiled": "Yes", + "nRouts": 294, + "nMops": 17892, + "nQuads": 4840, + "Compiled Times": 163, + "end_perf": [ + 0.74973201751708984, + 0.67252999999999996, + 0.067751000000000006, + 312516, + 313024, + 5366956340416991, + 85899345921, + 0 + ] + }, + "sram_if": { + "start_perf": [ + 0.66909193992614746, + 0.59900699999999996, + 0.060796999999999997, + 312516, + 313024, + 1716628560.8486309, + 5366956065305842 + ], + "child_modules": {}, + "Compiled": "Yes", + "nRouts": 33, + "nMops": 401, + "nQuads": 154, + "Compiled Times": 163, + "end_perf": [ + 0.67546796798706055, + 0.60433800000000004, + 0.061830000000000003, + 312516, + 313024, + 5366956087079789, + 12884901889, + 0 + ] + }, + "spi_if": { + "start_perf": [ + 1.5540800094604492, + 1.4512080000000001, + 0.091759999999999994, + 312516, + 313024, + 1716628561.733619, + 5366959083688698 + ], + "child_modules": {}, + "Compiled": "Yes", + "Compiled Times": 163, + "nQuads": 0, + "nMops": 0, + "end_perf": [ + 1.5548319816589355, + 1.4519580000000001, + 0.091759999999999994, + 312516, + 313024, + 5366959086275052, + 438086664193, + 0 + ], + "svclass": [ + "spi_if_vcs_virt_intf_C", + 0, + 0, + 0, + 0, + 0 + ], + "nRouts": 6 + }, + "sram_if_0000": { + "start_perf": [ + 0.6754920482635498, + 0.60436100000000004, + 0.061831999999999998, + 312516, + 313024, + 1716628560.855031, + 5366956087135507 + ], + "child_modules": {}, + "Compiled": "Yes", + "nRouts": 33, + "nMops": 716, + "nQuads": 308, + "Compiled Times": 163, + "end_perf": [ + 0.67845606803894043, + 0.60542099999999999, + 0.063728000000000007, + 312516, + 313024, + 5366956097282401, + 12884901889, + 0 + ] + }, + "rst_gen_unit": { + "start_perf": [ + 1.0638151168823242, + 0.97684499999999996, + 0.076881000000000005, + 312516, + 313024, + 1716628561.2433541, + 5366957411570560 + ], + "child_modules": {}, + "Compiled": "Yes", + "nRouts": 89, + "nMops": 2002, + "nQuads": 968, + "Compiled Times": 163, + "end_perf": [ + 1.0679669380187988, + 0.97910200000000003, + 0.078766000000000003, + 312516, + 313024, + 5366957425754971, + 270582939649, + 0 + ] + }, + "xy_dsp": { + "start_perf": [ + 1.3085570335388184, + 1.2122120000000001, + 0.085732000000000003, + 312516, + 313024, + 1716628561.488096, + 5366958246293633 + ], + "child_modules": { + "PH2AMP": 16, + "DUC4": 2, + "DW_mult_pipe_0000_0003": 32, + "dacif": 1 + }, + "Compiled": "Yes", + "nRouts": 1450, + "nMops": 66952, + "nQuads": 18346, + "Compiled Times": 96, + "end_perf": [ + 1.3630459308624268, + 1.265558, + 0.086763999999999994, + 312516, + 313024, + 5366958432180564, + 317827579905, + 0 + ] + }, + "ctrl_regfile": { + "start_perf": [ + 0.67848491668701172, + 0.60544799999999999, + 0.063730999999999996, + 312516, + 313024, + 1716628560.8580239, + 5366956097343423 + ], + "child_modules": {}, + "Compiled": "Yes", + "nRouts": 943, + "nMops": 18959, + "nQuads": 6921, + "Compiled Times": 163, + "end_perf": [ + 0.6929471492767334, + 0.618838, + 0.064772999999999997, + 312516, + 313024, + 5366956146735195, + 30064771073, + 0 + ] + }, + "mcu_regfile": { + "start_perf": [ + 0.93806600570678711, + 0.85544900000000001, + 0.072781999999999999, + 312516, + 313024, + 1716628561.117605, + 5366956982679726 + ], + "child_modules": {}, + "Compiled": "Yes", + "nRouts": 778, + "nMops": 20554, + "nQuads": 6080, + "Compiled Times": 163, + "end_perf": [ + 0.96821093559265137, + 0.88452200000000003, + 0.073792999999999997, + 312516, + 313024, + 5366957085584526, + 206158430209, + 0 + ] + }, + "sirv_gnrl_dffl": { + "start_perf": [ + 0.69833803176879883, + 0.62334800000000001, + 0.065643000000000007, + 312516, + 313024, + 1716628560.877877, + 5366956165054168 + ], + "child_modules": {}, + "Compiled": "Yes", + "nRouts": 20, + "nMops": 288, + "nQuads": 168, + "Compiled Times": 163, + "end_perf": [ + 0.70040011405944824, + 0.62533000000000005, + 0.065719, + 312516, + 313024, + 5366956172136670, + 60129542145, + 0 + ] + }, + "DW_mult_pipe_0000_0000": { + "start_perf": [ + 1.5087640285491943, + 1.4079709999999999, + 0.089773000000000006, + 312516, + 313024, + 1716628561.688303, + 5366958929132376 + ], + "child_modules": {}, + "Compiled": "Yes", + "nRouts": 55, + "nMops": 5465, + "nQuads": 1422, + "Compiled Times": 163, + "end_perf": [ + 1.5173630714416504, + 1.416544, + 0.089779999999999999, + 312516, + 313024, + 5366958958488597, + 420906795009, + 0 + ] + }, + "sirv_gnrl_ltch": { + "start_perf": [ + 0.70043396949768066, + 0.62536099999999994, + 0.065722000000000003, + 312516, + 313024, + 1716628560.8799729, + 5366956172205900 + ], + "child_modules": {}, + "Compiled": "Yes", + "nRouts": 18, + "nMops": 280, + "nQuads": 140, + "Compiled Times": 163, + "end_perf": [ + 0.70259809494018555, + 0.62740899999999999, + 0.065833000000000003, + 312516, + 313024, + 5366956179621172, + 73014444033, + 0 + ] + }, + "digital_top": { + "start_perf": [ + 1.2184789180755615, + 1.1283099999999999, + 0.079739000000000004, + 312516, + 313024, + 1716628561.3980179, + 5366957939079242 + ], + "child_modules": { + "system_regfile": 1, + "debug_top": 1, + "sram_if": 27, + "channel_top": 1, + "rst_gen_unit": 1, + "spi_slave": 1 + }, + "Compiled": "Yes", + "nRouts": 2464, + "nMops": 49975, + "nQuads": 17980, + "Compiled Times": 158, + "end_perf": [ + 1.2976291179656982, + 1.2042930000000001, + 0.082744999999999999, + 312516, + 313024, + 5366958209090474, + 309237645313, + 0 + ] + }, + "tsdn28hpcpuhdb128x128m4mw_170a": { + "start_perf": [ + 0.74977803230285645, + 0.67257199999999995, + 0.067754999999999996, + 312516, + 313024, + 1716628560.929317, + 5366956340499914 + ], + "significant_routs": [ + [ + 1126, + "R_VCSgd_rShyv_466", + 12339878, + 24637, + 3595 + ] + ], + "child_modules": { + "tsdn28hpcpuhdb128x128m4mw_170a_Int_Array": 1 + }, + "Compiled": "Yes", + "Compiled Times": 49, + "nQuads": 23808, + "nMops": 69686, + "end_perf": [ + 0.80220913887023926, + 0.72385500000000003, + 0.068795999999999996, + 312516, + 313024, + 5366956519386761, + 103079215105, + 0 + ], + "nRouts": 1133 + }, + "DW02_mult_0005": { + "start_perf": [ + 1.5473310947418213, + 1.4454469999999999, + 0.090785000000000005, + 312516, + 313024, + 1716628561.7268701, + 5366959060671203 + ], + "child_modules": {}, + "Compiled": "Yes", + "nRouts": 25, + "nMops": 7058, + "nQuads": 606, + "Compiled Times": 163, + "end_perf": [ + 1.55405592918396, + 1.4511849999999999, + 0.091758000000000006, + 312516, + 313024, + 5366959083630476, + 429496729601, + 0 + ] + }, + "tsdn28hpcpuhdb4096x32m4mw_170a_Int_Array": { + "start_perf": [ + 0.83660507202148438, + 0.75623600000000002, + 0.070740999999999998, + 312516, + 313024, + 1716628561.016144, + 5366956636632851 + ], + "significant_routs": [ + [ + 23, + "R_VCSgd_ay4xz_17", + 12447404, + 15692, + 1863 + ] + ], + "child_modules": {}, + "Compiled": "Yes", + "Compiled Times": 163, + "nQuads": 2502, + "nMops": 8076, + "end_perf": [ + 0.84995412826538086, + 0.76853000000000005, + 0.071768999999999999, + 312516, + 313024, + 5366956682194718, + 115964116993, + 0 + ], + "nRouts": 61 + }, + "qbmcu": { + "start_perf": [ + 0.97199201583862305, + 0.88731599999999999, + 0.074773000000000006, + 312516, + 313024, + 1716628561.151531, + 5366957098391864 + ], + "child_modules": { + "qbmcu_datalatch": 4, + "qbmcu_regfile_0000": 1 + }, + "Compiled": "Yes", + "nRouts": 1212, + "nMops": 34064, + "nQuads": 9974, + "Compiled Times": 163, + "end_perf": [ + 1.0496289730072021, + 0.96274800000000005, + 0.076819999999999999, + 312516, + 313024, + 5366957363257242, + 214748364801, + 0 + ] + }, + "TSDN28HPCPUHDB4096X32M4MWR_Int_Array": { + "start_perf": [ + 0.87191295623779297, + 0.79044199999999998, + 0.071771000000000001, + 312516, + 313024, + 1716628561.0514519, + 5366956757057519 + ], + "child_modules": {}, + "Compiled": "Yes", + "nRouts": 86, + "nMops": 14181, + "nQuads": 4214, + "Compiled Times": 96, + "end_perf": [ + 0.89372014999389648, + 0.81220400000000004, + 0.071771000000000001, + 312516, + 313024, + 5366956831467502, + 124554051585, + 0 + ] + }, + "TSDN28HPCPUHDB4096X32M4MWR": { + "start_perf": [ + 0.84998106956481934, + 0.76855499999999999, + 0.071771000000000001, + 312516, + 313024, + 1716628561.02952, + 5366956682254714 + ], + "child_modules": { + "TSDN28HPCPUHDB4096X32M4MWR_Int_Array": 1 + }, + "Compiled": "Yes", + "nRouts": 394, + "nMops": 22078, + "nQuads": 8894, + "Compiled Times": 96, + "end_perf": [ + 0.87188506126403809, + 0.79041300000000003, + 0.071771000000000001, + 312516, + 313024, + 5366956756991535, + 120259084289, + 0 + ] + }, + "tsdn28hpcpuhdb64x32m4mw_170a_Int_Array": { + "start_perf": [ + 0.89374995231628418, + 0.81223500000000004, + 0.071771000000000001, + 312516, + 313024, + 1716628561.0732889, + 5366956831534123 + ], + "significant_routs": [ + [ + 23, + "R_VCSgd_JweIx_17", + 12596654, + 15647, + 1863 + ] + ], + "child_modules": {}, + "Compiled": "Yes", + "Compiled Times": 96, + "nQuads": 2502, + "nMops": 8076, + "end_perf": [ + 0.90700507164001465, + 0.82545500000000005, + 0.071777999999999995, + 312516, + 313024, + 5366956876775830, + 133143986177, + 0 + ], + "nRouts": 61 + }, + "qbmcu_busdecoder": { + "start_perf": [ + 0.96825695037841797, + 0.88456500000000005, + 0.073796, + 312516, + 313024, + 1716628561.1477959, + 5366957085651696 + ], + "child_modules": {}, + "Compiled": "Yes", + "nRouts": 35, + "nMops": 2058, + "nQuads": 480, + "Compiled Times": 163, + "end_perf": [ + 0.97196507453918457, + 0.88729100000000005, + 0.074771000000000004, + 312516, + 313024, + 5366957098329975, + 210453397505, + 0 + ] + }, + "qbmcu_datalatch": { + "start_perf": [ + 1.0496721267700195, + 0.96278799999999998, + 0.076823000000000002, + 312516, + 313024, + 1716628561.2292111, + 5366957363332681 + ], + "child_modules": {}, + "Compiled": "Yes", + "nRouts": 25, + "nMops": 1002, + "nQuads": 248, + "Compiled Times": 163, + "end_perf": [ + 1.0521340370178223, + 0.96524500000000002, + 0.076823000000000002, + 312516, + 313024, + 5366957371766410, + 219043332097, + 0 + ] + }, + "qbmcu_regfile_0000": { + "start_perf": [ + 1.0521619319915771, + 0.96527300000000005, + 0.076823000000000002, + 312516, + 313024, + 1716628561.2317009, + 5366957371823231 + ], + "child_modules": {}, + "Compiled": "Yes", + "nRouts": 369, + "nMops": 6589, + "nQuads": 2686, + "Compiled Times": 163, + "end_perf": [ + 1.0637650489807129, + 0.97684499999999996, + 0.076829999999999996, + 312516, + 313024, + 5366957411483621, + 261993005057, + 0 + ] + }, + "dacif": { + "start_perf": [ + 1.2976751327514648, + 1.2043360000000001, + 0.082748000000000002, + 312516, + 313024, + 1716628561.4772141, + 5366958209188908 + ], + "child_modules": {}, + "Compiled": "Yes", + "nRouts": 206, + "nMops": 10166, + "nQuads": 3586, + "Compiled Times": 163, + "end_perf": [ + 1.3085250854492188, + 1.2121820000000001, + 0.085730000000000001, + 312516, + 313024, + 5366958246232678, + 313532612609, + 0 + ] + }, + "system_regfile": { + "start_perf": [ + 1.1163489818572998, + 1.027355, + 0.078797000000000006, + 312516, + 313024, + 1716628561.2958879, + 5366957590744484 + ], + "child_modules": {}, + "Compiled": "Yes", + "nRouts": 515, + "nMops": 10566, + "nQuads": 4066, + "Compiled Times": 163, + "end_perf": [ + 1.1386620998382568, + 1.049623, + 0.078797000000000006, + 312516, + 313024, + 5366957666879908, + 300647710721, + 0 + ] + }, + "channel_top": { + "start_perf": [ + 1.13869309425354, + 1.0496540000000001, + 0.078797000000000006, + 312516, + 313024, + 1716628561.3182321, + 5366957666953647 + ], + "child_modules": { + "z_dsp": 1, + "modout_mux": 1, + "dac_regfile": 1, + "qbmcu_busdecoder": 1, + "DW_mult_pipe_0000_0002": 2, + "DW_mult_pipe_0000_0003": 4, + "PH2AMP": 1, + "param_lut_0002": 2, + "mcu_regfile": 1, + "TSDN28HPCPUHDB4096X32M4MWR": 6, + "qbmcu": 1, + "tsdn28hpcpuhdb64x32m4mw_170a_Int_Array": 1, + "xy_dsp": 1, + "ctrl_regfile": 1 + }, + "Compiled": "Yes", + "nRouts": 1500, + "nMops": 38963, + "nQuads": 12591, + "Compiled Times": 163, + "end_perf": [ + 1.2184369564056396, + 1.1282700000000001, + 0.079736000000000001, + 312516, + 313024, + 5366957938991886, + 304942678017, + 0 + ] + }, + "DUC_HB2": { + "start_perf": [ + 1.3630831241607666, + 1.265593, + 0.086765999999999996, + 312516, + 313024, + 1716628561.5426221, + 5366958432264040 + ], + "child_modules": {}, + "Compiled": "Yes", + "nRouts": 146, + "nMops": 11462, + "nQuads": 2754, + "Compiled Times": 163, + "end_perf": [ + 1.3759889602661133, + 1.2774799999999999, + 0.087758000000000003, + 312516, + 313024, + 5366958476320509, + 330712481793, + 0 + ] + }, + "DUC_HB4": { + "start_perf": [ + 1.3855969905853271, + 1.287067, + 0.087760000000000005, + 312516, + 313024, + 1716628561.565136, + 5366958509053363 + ], + "child_modules": {}, + "Compiled": "Yes", + "nRouts": 91, + "nMops": 6164, + "nQuads": 1606, + "Compiled Times": 163, + "end_perf": [ + 1.3940169811248779, + 1.2944720000000001, + 0.088758000000000004, + 312516, + 313024, + 5366958537796609, + 347892350977, + 0 + ] + }, + "IIR_Filter": { + "start_perf": [ + 1.4507350921630859, + 1.351073, + 0.088759000000000005, + 312516, + 313024, + 1716628561.6302741, + 5366958731214779 + ], + "child_modules": { + "DW02_mult_0004": 4, + "DW02_mult_0005": 4 + }, + "Compiled": "Yes", + "nRouts": 148, + "nMops": 7688, + "nQuads": 2036, + "Compiled Times": 163, + "end_perf": [ + 1.4612259864807129, + 1.3605309999999999, + 0.089771000000000004, + 312516, + 313024, + 5366958767029305, + 373662154753, + 0 + ] + }, + "z_dsp": { + "start_perf": [ + 1.4612569808959961, + 1.3605610000000001, + 0.089773000000000006, + 312516, + 313024, + 1716628561.6407959, + 5366958767100241 + ], + "child_modules": { + "IIR_Filter": 6 + }, + "Compiled": "Yes", + "nRouts": 313, + "nMops": 13876, + "nQuads": 4236, + "Compiled Times": 163, + "end_perf": [ + 1.4775979518890381, + 1.376868, + 0.089773000000000006, + 312516, + 313024, + 5366958822868478, + 412316860417, + 0 + ] + }, + "TB": { + "start_perf": [ + 1.4776279926300049, + 1.3768989999999999, + 0.089773000000000006, + 312516, + 313024, + 1716628561.657167, + 5366958822938527 + ], + "child_modules": { + "spi_if": 1, + "digital_top": 1 + }, + "Compiled": "Yes", + "nRouts": 544, + "nMops": 23558, + "nQuads": 8884, + "Compiled Times": 156, + "end_perf": [ + 1.5087361335754395, + 1.4079429999999999, + 0.089773000000000006, + 312516, + 313024, + 5366958929069591, + 416611827713, + 0 + ] + }, + "DW_mult_pipe_0000_0002": { + "start_perf": [ + 1.5173890590667725, + 1.416569, + 0.089782000000000001, + 312516, + 313024, + 1716628561.696928, + 5366958958547843 + ], + "child_modules": {}, + "Compiled": "Yes", + "nRouts": 55, + "nMops": 8229, + "nQuads": 1422, + "Compiled Times": 163, + "end_perf": [ + 1.5274889469146729, + 1.4266480000000001, + 0.089782000000000001, + 312516, + 313024, + 5366958993058884, + 420906795009, + 0 + ] + }, + "DW_mult_pipe_0000_0003": { + "start_perf": [ + 1.5275270938873291, + 1.426687, + 0.089782000000000001, + 312516, + 313024, + 1716628561.7070661, + 5366958993126586 + ], + "child_modules": {}, + "Compiled": "Yes", + "nRouts": 55, + "nMops": 5191, + "nQuads": 1422, + "Compiled Times": 30, + "end_perf": [ + 1.5363321304321289, + 1.4344790000000001, + 0.090776999999999997, + 312516, + 313024, + 5366959023190991, + 420906795009, + 0 + ] + }, + "DW01_addsub": { + "start_perf": [ + 1.5363619327545166, + 1.434507, + 0.090777999999999998, + 312516, + 313024, + 1716628561.7159009, + 5366959023259593 + ], + "child_modules": {}, + "Compiled": "Yes", + "nRouts": 23, + "nMops": 2376, + "nQuads": 430, + "Compiled Times": 163, + "end_perf": [ + 1.5404379367828369, + 1.4385699999999999, + 0.090783000000000003, + 312516, + 313024, + 5366959037190185, + 425201762305, + 0 + ] + }, + "DW02_mult_0004": { + "start_perf": [ + 1.540463924407959, + 1.4385950000000001, + 0.090785000000000005, + 312516, + 313024, + 1716628561.7200029, + 5366959037296967 + ], + "child_modules": {}, + "Compiled": "Yes", + "nRouts": 25, + "nMops": 7046, + "nQuads": 606, + "Compiled Times": 163, + "end_perf": [ + 1.5473051071166992, + 1.4454210000000001, + 0.090785000000000005, + 312516, + 313024, + 5366959060609613, + 429496729601, + 0 + ] + } + }, + "CompUnits": { + "IHYdB_d": { + "mod": "spi_if", + "out": "IHYdB_d.o", + "mode": 4, + "bytes": 11636, + "archive": "archive.162/_3127_archive_1.a", + "text": 213, + "checksum": 0 + }, + "amcQw_d": { + "mod": "...MASTER...", + "out": "objs/amcQw_d.o", + "mode": 4, + "bytes": 9160, + "text": 653, + "checksum": 0 + }, + "UTi0b_d": { + "mod": "sirv_gnrl_ltch", + "out": "UTi0b_d.o", + "mode": 4, + "bytes": 9700, + "archive": "archive.162/_3127_archive_1.a", + "text": 1507, + "checksum": 0 + }, + "HNRiG_d": { + "mod": "DW_mult_pipe_0000_0000", + "out": "HNRiG_d.o", + "mode": 4, + "bytes": 38420, + "archive": "archive.162/_3127_archive_1.a", + "text": 21600, + "checksum": 0 + }, + "iYIEc_d": { + "mod": "PH2AMP", + "out": "iYIEc_d.o", + "mode": 4, + "bytes": 158200, + "archive": "archive.162/_3127_archive_1.a", + "text": 98836, + "checksum": 0 + }, + "D1hM1_d": { + "mod": "_vcs_unit__504089786", + "out": "D1hM1_d.o", + "mode": 4, + "bytes": 88126, + "archive": "archive.162/_3127_archive_1.a", + "text": 14843, + "cls": 14516, + "checksum": 0 + }, + "xFWdC_d": { + "mod": "channel_top", + "out": "xFWdC_d.o", + "mode": 4, + "bytes": 468752, + "archive": "archive.162/_3127_archive_1.a", + "text": 301887, + "checksum": 0 + }, + "rTmJG_d": { + "mod": "digital_top", + "out": "rTmJG_d.o", + "mode": 4, + "bytes": 644250, + "archive": "archive.162/_3127_archive_1.a", + "text": 386152, + "checksum": 0 + }, + "nJgqZ_d": { + "mod": "sram_if_0000", + "out": "nJgqZ_d.o", + "mode": 4, + "bytes": 16568, + "archive": "archive.162/_3127_archive_1.a", + "text": 3711, + "checksum": 0 + }, + "nJN5E_d": { + "mod": "param_lut_0002", + "out": "nJN5E_d.o", + "mode": 4, + "bytes": 19394, + "archive": "archive.162/_3127_archive_1.a", + "text": 7703, + "checksum": 0 + }, + "BM4bj_d": { + "mod": "sirv_gnrl_dffl", + "out": "BM4bj_d.o", + "mode": 4, + "bytes": 9566, + "archive": "archive.162/_3127_archive_1.a", + "text": 1374, + "checksum": 0 + }, + "e36VC_d": { + "mod": "TSDN28HPCPUHDB4096X32M4MWR_Int_Array", + "out": "e36VC_d.o", + "mode": 4, + "bytes": 106790, + "archive": "archive.162/_3127_archive_1.a", + "text": 60950, + "checksum": 0 + }, + "Sg3ri_d": { + "mod": "TSDN28HPCPUHDB4096X32M4MWR", + "out": "Sg3ri_d.o", + "mode": 4, + "bytes": 122964, + "archive": "archive.162/_3127_archive_1.a", + "text": 68656, + "checksum": 0 + }, + "LR0zI_d": { + "mod": "dac_regfile", + "out": "LR0zI_d.o", + "mode": 4, + "bytes": 118956, + "archive": "archive.162/_3127_archive_1.a", + "text": 73359, + "checksum": 0 + }, + "SMgga_d": { + "mod": "dacif", + "out": "SMgga_d.o", + "mode": 4, + "bytes": 62530, + "archive": "archive.162/_3127_archive_1.a", + "text": 42611, + "checksum": 0 + }, + "rLaFI_d": { + "mod": "IIR_Filter", + "out": "rLaFI_d.o", + "mode": 4, + "bytes": 55838, + "archive": "archive.162/_3127_archive_1.a", + "text": 31475, + "checksum": 0 + }, + "rShyv_d": { + "mod": "tsdn28hpcpuhdb128x128m4mw_170a", + "out": "rShyv_d.o", + "mode": 4, + "bytes": 297858, + "archive": "archive.162/_3127_archive_1.a", + "text": 199889, + "checksum": 0 + }, + "HWLgR_d": { + "mod": "mcu_regfile", + "out": "HWLgR_d.o", + "mode": 4, + "bytes": 226690, + "archive": "archive.162/_3127_archive_1.a", + "text": 144659, + "checksum": 0 + }, + "gNaPt_d": { + "mod": "debug_top", + "out": "gNaPt_d.o", + "mode": 4, + "bytes": 108122, + "archive": "archive.162/_3127_archive_1.a", + "text": 66239, + "checksum": 0 + }, + "W3x1b_d": { + "mod": "system_regfile", + "out": "W3x1b_d.o", + "mode": 4, + "bytes": 141826, + "archive": "archive.162/_3127_archive_1.a", + "text": 80143, + "checksum": 0 + }, + "hwIug_d": { + "mod": "DW02_mult_0004", + "out": "hwIug_d.o", + "mode": 4, + "bytes": 29288, + "archive": "archive.162/_3127_archive_1.a", + "text": 17912, + "checksum": 0 + }, + "eFLuy_d": { + "mod": "tsdn28hpcpuhdb128x128m4mw_170a_Int_Array", + "out": "eFLuy_d.o", + "mode": 4, + "bytes": 66736, + "archive": "archive.162/_3127_archive_1.a", + "text": 35490, + "checksum": 0 + }, + "d6TPd_d": { + "mod": "tsdn28hpcpuhdb4096x32m4mw_170a", + "out": "d6TPd_d.o", + "mode": 4, + "bytes": 109700, + "archive": "archive.162/_3127_archive_1.a", + "text": 63696, + "checksum": 0 + }, + "ay4xz_d": { + "mod": "tsdn28hpcpuhdb4096x32m4mw_170a_Int_Array", + "out": "ay4xz_d.o", + "mode": 4, + "bytes": 66252, + "archive": "archive.162/_3127_archive_1.a", + "text": 35222, + "checksum": 0 + }, + "jAiwN_d": { + "mod": "qbmcu_busdecoder", + "out": "jAiwN_d.o", + "mode": 4, + "bytes": 16690, + "archive": "archive.162/_3127_archive_1.a", + "text": 7155, + "checksum": 0 + }, + "JweIx_d": { + "mod": "tsdn28hpcpuhdb64x32m4mw_170a_Int_Array", + "out": "JweIx_d.o", + "mode": 4, + "bytes": 65620, + "archive": "archive.162/_3127_archive_1.a", + "text": 34994, + "checksum": 0 + }, + "xnbfb_d": { + "mod": "qbmcu", + "out": "xnbfb_d.o", + "mode": 4, + "bytes": 388698, + "archive": "archive.162/_3127_archive_1.a", + "text": 249459, + "checksum": 0 + }, + "eAsJz_d": { + "mod": "spi_slave", + "out": "eAsJz_d.o", + "mode": 4, + "bytes": 308970, + "archive": "archive.162/_3127_archive_1.a", + "text": 188711, + "checksum": 0 + }, + "MsCBG_d": { + "mod": "qbmcu_datalatch", + "out": "MsCBG_d.o", + "mode": 4, + "bytes": 12266, + "archive": "archive.162/_3127_archive_1.a", + "text": 3672, + "checksum": 0 + }, + "Hit7c_d": { + "mod": "qbmcu_regfile_0000", + "out": "Hit7c_d.o", + "mode": 4, + "bytes": 92426, + "archive": "archive.162/_3127_archive_1.a", + "text": 49819, + "checksum": 0 + }, + "zpIk1_d": { + "mod": "z_dsp", + "out": "zpIk1_d.o", + "mode": 4, + "bytes": 88692, + "archive": "archive.162/_3127_archive_1.a", + "text": 53911, + "checksum": 0 + }, + "anuMN_d": { + "mod": "rst_gen_unit", + "out": "anuMN_d.o", + "mode": 4, + "bytes": 21774, + "archive": "archive.162/_3127_archive_1.a", + "text": 8383, + "checksum": 0 + }, + "U33JQ_d": { + "mod": "xy_dsp", + "out": "U33JQ_d.o", + "mode": 4, + "bytes": 380142, + "archive": "archive.162/_3127_archive_1.a", + "text": 244551, + "checksum": 0 + }, + "KysYq_d": { + "mod": "DW01_addsub", + "out": "KysYq_d.o", + "mode": 4, + "bytes": 18370, + "archive": "archive.162/_3127_archive_1.a", + "text": 8432, + "checksum": 0 + }, + "ksFw4_d": { + "mod": "DUC_HB2", + "out": "ksFw4_d.o", + "mode": 4, + "bytes": 60820, + "archive": "archive.162/_3127_archive_1.a", + "text": 41471, + "checksum": 0 + }, + "SiiVi_d": { + "mod": "DW_mult_pipe_0000_0002", + "out": "SiiVi_d.o", + "mode": 4, + "bytes": 41994, + "archive": "archive.162/_3127_archive_1.a", + "text": 24592, + "checksum": 0 + }, + "Rdd8k_d": { + "mod": "DUC_HB3", + "out": "Rdd8k_d.o", + "mode": 4, + "bytes": 44056, + "archive": "archive.162/_3127_archive_1.a", + "text": 27407, + "checksum": 0 + }, + "cwtAY_d": { + "mod": "DUC4", + "out": "cwtAY_d.o", + "mode": 4, + "bytes": 302476, + "archive": "archive.162/_3127_archive_1.a", + "text": 216676, + "checksum": 0 + }, + "zwWSN_d": { + "mod": "DUC_HB4", + "out": "zwWSN_d.o", + "mode": 4, + "bytes": 39014, + "archive": "archive.162/_3127_archive_1.a", + "text": 23235, + "checksum": 0 + }, + "sH4Fc_d": { + "mod": "TB", + "out": "sH4Fc_d.o", + "mode": 4, + "bytes": 216624, + "archive": "archive.162/_3127_archive_1.a", + "text": 110871, + "checksum": 0 + }, + "ZpmS6_d": { + "mod": "DW_mult_pipe_0000_0003", + "out": "ZpmS6_d.o", + "mode": 4, + "bytes": 37410, + "archive": "archive.162/_3127_archive_1.a", + "text": 20756, + "checksum": 0 + }, + "UIt6b_d": { + "mod": "DW02_mult_0005", + "out": "UIt6b_d.o", + "mode": 4, + "bytes": 29268, + "archive": "archive.162/_3127_archive_1.a", + "text": 17892, + "checksum": 0 + } + }, + "reusePaths": { + "reYIK_d": { + "icPath": "csrc" + }, + "jEu9i_d": { + "icPath": "csrc" + }, + "NABmh_d": { + "icPath": "csrc" + }, + "mLA3J_d": { + "icPath": "csrc" + } + }, + "ObjArchives": [ + { + "archive": "archive.162/_3127_archive_1.a", + "objects": [ + [ + "D1hM1_d.o", + 88126 + ], + [ + "nJgqZ_d.o", + 16568 + ], + [ + "nJN5E_d.o", + 19394 + ], + [ + "BM4bj_d.o", + 9566 + ], + [ + "UTi0b_d.o", + 9700 + ], + [ + "LR0zI_d.o", + 118956 + ], + [ + "gNaPt_d.o", + 108122 + ], + [ + "rShyv_d.o", + 297858 + ], + [ + "eFLuy_d.o", + 66736 + ], + [ + "d6TPd_d.o", + 109700 + ], + [ + "ay4xz_d.o", + 66252 + ], + [ + "Sg3ri_d.o", + 122964 + ], + [ + "e36VC_d.o", + 106790 + ], + [ + "JweIx_d.o", + 65620 + ], + [ + "iYIEc_d.o", + 158200 + ], + [ + "HWLgR_d.o", + 226690 + ], + [ + "jAiwN_d.o", + 16690 + ], + [ + "xnbfb_d.o", + 388698 + ], + [ + "MsCBG_d.o", + 12266 + ], + [ + "Hit7c_d.o", + 92426 + ], + [ + "anuMN_d.o", + 21774 + ], + [ + "eAsJz_d.o", + 308970 + ], + [ + "W3x1b_d.o", + 141826 + ], + [ + "xFWdC_d.o", + 468752 + ], + [ + "rTmJG_d.o", + 644250 + ], + [ + "SMgga_d.o", + 62530 + ], + [ + "U33JQ_d.o", + 380142 + ], + [ + "ksFw4_d.o", + 60820 + ], + [ + "Rdd8k_d.o", + 44056 + ], + [ + "zwWSN_d.o", + 39014 + ], + [ + "cwtAY_d.o", + 302476 + ], + [ + "rLaFI_d.o", + 55838 + ], + [ + "zpIk1_d.o", + 88692 + ], + [ + "sH4Fc_d.o", + 216624 + ], + [ + "HNRiG_d.o", + 38420 + ], + [ + "SiiVi_d.o", + 41994 + ], + [ + "ZpmS6_d.o", + 37410 + ], + [ + "KysYq_d.o", + 18370 + ], + [ + "hwIug_d.o", + 29288 + ], + [ + "UIt6b_d.o", + 29268 + ], + [ + "IHYdB_d.o", + 11636 + ], + [ + "amcQwB.o", + 169714 + ] + ], + "size": 5313186 + } + ], + "stat": { + "ru_self_end": { + "ru_utime_sec": 1.452623, + "ru_minflt": 43105, + "ru_stime_sec": 0.094714000000000007, + "ru_maxrss_kb": 113780, + "ru_majflt": 0, + "ru_nvcsw": 32, + "ru_nivcsw": 14 + }, + "cpu_cycles_end": 5366959098587723, + "ru_childs_end": { + "ru_utime_sec": 0.0090399999999999994, + "ru_minflt": 10699, + "ru_stime_sec": 0.015606999999999999, + "ru_maxrss_kb": 46032, + "ru_majflt": 0, + "ru_nvcsw": 25, + "ru_nivcsw": 24 + }, + "peak_mem_kb": 313024 + } +} \ No newline at end of file diff --git a/tb/digital_top/csrc/filelist b/tb/digital_top/csrc/filelist new file mode 100644 index 0000000..988c130 --- /dev/null +++ b/tb/digital_top/csrc/filelist @@ -0,0 +1,31 @@ + + +AR=ar +DOTLIBS=/home/synopsys/vcs/O-2018.09-SP2/linux64/lib/libzerosoft_rt_stubs.so /home/synopsys/vcs/O-2018.09-SP2/linux64/lib/libvirsim.so /home/synopsys/vcs/O-2018.09-SP2/linux64/lib/liberrorinf.so /home/synopsys/vcs/O-2018.09-SP2/linux64/lib/libsnpsmalloc.so /home/synopsys/vcs/O-2018.09-SP2/linux64/lib/libvfs.so /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/pli.a + +# This file is automatically generated by VCS. Any changes you make to it +# will be overwritten the next time VCS is run +VCS_LIBEXT= +XTRN_OBJS= + +DPI_WRAPPER_OBJS = +DPI_STUB_OBJS = +# filelist.dpi will populate DPI_WRAPPER_OBJS and DPI_STUB_OBJS +include filelist.dpi +PLI_STUB_OBJS = +include filelist.pli + +include filelist.hsopt + +include filelist.cu + +VCS_INCR_OBJS= + + +AUGDIR= +AUG_LDFLAGS= +SHARED_OBJ_SO= + + + +VLOG_OBJS= $(VCS_OBJS) $(CU_OBJS) $(VCS_ARC0) $(XTRN_OBJS) $(DPI_WRAPPER_OBJS) $(VCS_INCR_OBJS) $(SHARED_OBJ_SO) $(HSOPT_OBJS) diff --git a/tb/digital_top/csrc/filelist.cu b/tb/digital_top/csrc/filelist.cu new file mode 100644 index 0000000..a72fe20 --- /dev/null +++ b/tb/digital_top/csrc/filelist.cu @@ -0,0 +1,41 @@ +PIC_LD=ld + +ARCHIVE_OBJS= +ARCHIVE_OBJS += _3127_archive_1.so +_3127_archive_1.so : archive.162/_3127_archive_1.a + @$(AR) -s $< + @$(PIC_LD) -shared -Bsymbolic -o .//../simv.daidir//_3127_archive_1.so --whole-archive $< --no-whole-archive + @rm -f $@ + @ln -sf .//../simv.daidir//_3127_archive_1.so $@ + + +ARCHIVE_OBJS += _prev_archive_1.so +_prev_archive_1.so : archive.162/_prev_archive_1.a + @$(AR) -s $< + @$(PIC_LD) -shared -Bsymbolic -o .//../simv.daidir//_prev_archive_1.so --whole-archive $< --no-whole-archive + @rm -f $@ + @ln -sf .//../simv.daidir//_prev_archive_1.so $@ + + + + + +O0_OBJS = + +$(O0_OBJS) : %.o: %.c + $(CC_CG) $(CFLAGS_O0) -c -o $@ $< + + +%.o: %.c + $(CC_CG) $(CFLAGS_CG) -c -o $@ $< +CU_UDP_OBJS = \ + + +CU_LVL_OBJS = \ +SIM_l.o + +MAIN_OBJS = \ +objs/amcQw_d.o + +CU_OBJS = $(MAIN_OBJS) $(ARCHIVE_OBJS) $(CU_UDP_OBJS) $(CU_LVL_OBJS) + diff --git a/tb/digital_top/csrc/filelist.dpi b/tb/digital_top/csrc/filelist.dpi new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/filelist.hsopt b/tb/digital_top/csrc/filelist.hsopt new file mode 100644 index 0000000..9287244 --- /dev/null +++ b/tb/digital_top/csrc/filelist.hsopt @@ -0,0 +1,13 @@ +rmapats_mop.o: rmapats.m + @/home/synopsys/vcs/O-2018.09-SP2/linux64/bin/cgmop1 -tls_initexe -pic -gen_obj rmapats.m rmapats_mop.o; rm -f rmapats.m; touch rmapats.m; touch rmapats_mop.o + +rmapats.o: rmapats.c + @$(CC_CG) $(CFLAGS_CG) -c -fPIC -x c -o rmapats.o rmapats.c +rmapats%.o: rmapats%.c + @$(CC_CG) $(CFLAGS_CG) -c -fPIC -x c -o $@ $< +rmar.o: rmar.c + @$(CC_CG) $(CFLAGS_CG) -c -fPIC -x c -o rmar.o rmar.c +rmar%.o: rmar%.c + @$(CC_CG) $(CFLAGS_CG) -c -fPIC -x c -o $@ $< + +include filelist.hsopt.objs diff --git a/tb/digital_top/csrc/filelist.hsopt.llvm2_0.objs b/tb/digital_top/csrc/filelist.hsopt.llvm2_0.objs new file mode 100644 index 0000000..4c31419 --- /dev/null +++ b/tb/digital_top/csrc/filelist.hsopt.llvm2_0.objs @@ -0,0 +1 @@ +LLVM_OBJS += rmar_llvm_0_1.o rmar_llvm_0_0.o diff --git a/tb/digital_top/csrc/filelist.hsopt.objs b/tb/digital_top/csrc/filelist.hsopt.objs new file mode 100644 index 0000000..f40e57c --- /dev/null +++ b/tb/digital_top/csrc/filelist.hsopt.objs @@ -0,0 +1,7 @@ +HSOPT_OBJS +=rmapats_mop.o \ + rmapats.o \ + rmar.o rmar_nd.o + +include filelist.hsopt.llvm2_0.objs +HSOPT_OBJS += $(LLVM_OBJS) + diff --git a/tb/digital_top/csrc/filelist.pli b/tb/digital_top/csrc/filelist.pli new file mode 100644 index 0000000..e3714f3 --- /dev/null +++ b/tb/digital_top/csrc/filelist.pli @@ -0,0 +1,4 @@ +PLI_STUB_OBJS += _vcs_pli_stub_.o +_vcs_pli_stub_.o: _vcs_pli_stub_.c + @$(CC) -I/home/synopsys/vcs/O-2018.09-SP2/include -pipe -fPIC -I/home/synopsys/vcs/O-2018.09-SP2/include -fPIC -c -o _vcs_pli_stub_.o _vcs_pli_stub_.c + @strip -g _vcs_pli_stub_.o diff --git a/tb/digital_top/csrc/hsim/hsim.sdb b/tb/digital_top/csrc/hsim/hsim.sdb new file mode 100644 index 0000000..b1c23c8 Binary files /dev/null and b/tb/digital_top/csrc/hsim/hsim.sdb differ diff --git a/tb/digital_top/csrc/import_dpic.h b/tb/digital_top/csrc/import_dpic.h new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/objs/amcQw_d.o b/tb/digital_top/csrc/objs/amcQw_d.o new file mode 100644 index 0000000..fb2281f Binary files /dev/null and b/tb/digital_top/csrc/objs/amcQw_d.o differ diff --git a/tb/digital_top/csrc/pre.cgincr.sdb b/tb/digital_top/csrc/pre.cgincr.sdb new file mode 100644 index 0000000..f8a3b19 Binary files /dev/null and b/tb/digital_top/csrc/pre.cgincr.sdb differ diff --git a/tb/digital_top/csrc/product_timestamp b/tb/digital_top/csrc/product_timestamp new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/rmapats.c b/tb/digital_top/csrc/rmapats.c new file mode 100644 index 0000000..0c43907 --- /dev/null +++ b/tb/digital_top/csrc/rmapats.c @@ -0,0 +1,43 @@ +// file = 0; split type = patterns; threshold = 100000; total count = 0. +#include +#include +#include +#include "rmapats.h" + +void hsG_0__0 (struct dummyq_struct * I1289, EBLK * I1283, U I685); +void hsG_0__0 (struct dummyq_struct * I1289, EBLK * I1283, U I685) +{ + U I1547; + U I1548; + U I1549; + struct futq * I1550; + struct dummyq_struct * pQ = I1289; + I1547 = ((U )vcs_clocks) + I685; + I1549 = I1547 & ((1 << fHashTableSize) - 1); + I1283->I727 = (EBLK *)(-1); + I1283->I731 = I1547; + if (I1547 < (U )vcs_clocks) { + I1548 = ((U *)&vcs_clocks)[1]; + sched_millenium(pQ, I1283, I1548 + 1, I1547); + } + else if ((peblkFutQ1Head != ((void *)0)) && (I685 == 1)) { + I1283->I733 = (struct eblk *)peblkFutQ1Tail; + peblkFutQ1Tail->I727 = I1283; + peblkFutQ1Tail = I1283; + } + else if ((I1550 = pQ->I1190[I1549].I745)) { + I1283->I733 = (struct eblk *)I1550->I744; + I1550->I744->I727 = (RP )I1283; + I1550->I744 = (RmaEblk *)I1283; + } + else { + sched_hsopt(pQ, I1283, I1547); + } +} +#ifdef __cplusplus +extern "C" { +#endif +void SinitHsimPats(void); +#ifdef __cplusplus +} +#endif diff --git a/tb/digital_top/csrc/rmapats.h b/tb/digital_top/csrc/rmapats.h new file mode 100644 index 0000000..e3cdd81 --- /dev/null +++ b/tb/digital_top/csrc/rmapats.h @@ -0,0 +1,2724 @@ +#ifndef __DO_RMAHDR_ +#define __DO_RMAHDR_ + +#ifdef __cplusplus + extern "C" { +#endif + +#define VCS_RTLIB_TLS_MODEL __attribute__((tls_model("initial-exec"))) + +typedef unsigned long UP; +typedef unsigned U; +typedef unsigned char UB; +typedef unsigned char scalar; +typedef struct vec32 vec32; +typedef unsigned short US; +typedef unsigned char SVAL; +typedef unsigned char TYPEB; +typedef struct qird QIRD; +typedef unsigned char UST_e; +typedef unsigned uscope_t; +typedef U NumLibs_t; +struct vec32 { + U I1; + U I2; +}; +typedef unsigned long RP; +typedef unsigned long RO; +typedef unsigned long long ULL; +typedef U GateCount; +typedef U NodeCount; +typedef unsigned short HsimEdge; +typedef unsigned char HsimExprChar; +typedef struct { + U I706; + RP I707; +} RmaReceiveClock1; +typedef NodeCount FlatNodeNum; +typedef U InstNum; +typedef unsigned ProcessNum; +typedef unsigned long long TimeStamp64; +typedef unsigned long long TimeStamp; +typedef enum { + PD_SING = 0, + PD_RF = 1, + PD_PLSE = 2, + PD_PLSE_RF = 3, + PD_NULL = 4 +} PD_e; +typedef TimeStamp RmaTimeStamp; +typedef TimeStamp64 RmaTimeStamp64; +typedef struct { + int * I708; + int * I709; + int I710; + union { + long long enumDesc; + long long classId; + } I711; +} TypeData; +struct etype { + U I586 :8; + U I587; + U I588; + U I589 :1; + U I590 :1; + U I591 :1; + U I592 :1; + U I593 :1; + U I594 :1; + U I595 :1; + U I596 :1; + U I597 :1; + U I598 :4; + U I599 :1; + U I600 :1; + U I601 :1; + U I602 :1; + U I603 :1; + U I604 :1; + U I605 :1; + U I606 :1; + U I607 :2; + U I608 :1; + U I609 :2; + U I610 :1; + U I611 :1; + U I612 :1; + U I613 :1; + U I614 :1; + U I615 :1; + TypeData * I616; + U I617; + U I618; + U I619 :1; + U I620 :1; + U I621 :1; + U I622 :1; + U I623 :2; + U I624 :2; + U I625 :1; + U I626 :1; + U I627 :1; + U I628 :1; + U I629 :1; + U I630 :1; + U I631 :1; + U I632 :1; + U I633 :1; + U I634 :1; + U I635 :1; + U I636 :13; +}; +typedef union { + double I718; + unsigned long long I719; + unsigned I720[2]; +} rma_clock_struct; +typedef struct eblk EBLK; +typedef int (* E_fn)(void); +typedef struct eblk { + struct eblk * I727; + E_fn I728; + struct iptmpl * I729; + unsigned I731; + unsigned I732; + struct eblk * I733; +} eblk_struct; +typedef struct { + RP I727; + RP I728; + RP I729; + unsigned I731; + unsigned I732; + RP I733; +} RmaEblk; +typedef struct { + RP I727; + RP I728; + RP I729; + unsigned I731; + unsigned I732; + RP I733; + unsigned val; +} RmaEblklq; +typedef union { + double I718; + unsigned long long I719; + unsigned I720[2]; +} clock_struct; +typedef clock_struct RmaClockStruct; +typedef struct RmaRetain_t RmaRetain; +struct RmaRetain_t { + RP I769; + RmaEblk I726; + U I771; + US I772 :1; + US I773 :4; + US I181 :2; + US state :2; + US I775 :1; + US I776 :2; + US I777 :2; + US fHsim :1; + US I569 :1; + scalar newval; + scalar I780; + RP I781; +}; +struct retain_t { + struct retain_t * I769; + EBLK I726; + U I771; + US I772 :1; + US I773 :4; + US I181 :2; + US state :2; + US I775 :1; + US I776 :2; + US I777 :2; + US fHsim :1; + US I778 :1; + scalar newval; + scalar I780; + void * I781; +}; +typedef struct MPSched MPS; +typedef struct RmaMPSched RmaMps; +struct MPSched { + MPS * I760; + scalar I761; + scalar I762; + scalar I763; + scalar fHsim :1; + scalar I181 :6; + U I765; + EBLK I766; + void * I767; + UP I768[1]; +}; +struct RmaMPSched { + RP I760; + scalar I761; + scalar I762; + scalar I763; + scalar fHsim :1; + scalar I181 :6; + U I765; + RmaEblk I766; + RP I767; + RP I768[1]; +}; +typedef struct RmaMPSchedPulse RmaMpsp; +struct RmaMPSchedPulse { + RP I760; + scalar I761; + scalar I762; + scalar I763; + scalar I181; + U I765; + RmaEblk I766; + scalar I777; + scalar I786; + scalar I787; + scalar I788; + U I789; + RmaClockStruct I790; + RmaClockStruct I791; + U state; + U I792; + RP I729; + RP I793; + RP I794; + RP I768[1]; +}; +typedef struct MPItem MPI; +struct MPItem { + U * I796; + void * I797; +}; +typedef struct { + RmaEblk I726; + RP I798; + scalar I799; + scalar I777; + scalar I800; +} RmaTransEventHdr; +typedef struct RmaMPSchedPulseNewCsdf RmaMpspNewCsdf; +struct RmaMPSchedPulseNewCsdf { + RP I760; + scalar I761; + scalar I762; + scalar I763; + scalar fHsim :1; + scalar I181 :6; + U I765; + RmaEblk I766; + scalar I777; + scalar I786; + scalar I787; + scalar I788; + U state :4; + U I802 :28; + RmaClockStruct I790; + RmaClockStruct I791; + RP I803; + RP I729; + RP I804; + RP I768[1]; +}; +typedef struct red_t { + U I805; + U I806; + U I685; +} RED; +typedef struct predd { + PD_e I181; + RED I807[0]; +} PREDD; +union rhs_value { + vec32 I808; + scalar I799; + vec32 * I777; + double I809; + U I810; +}; +typedef struct nbs_t { + struct nbs_t * I811; + struct nbs_t * I813; + void (* I814)(struct nbs_t * I781); + U I815 :1; + U I816 :1; + U I817 :1; + U I818 :1; + U I819 :1; + U I820 :1; + U I821 :26; + U I822; + void * I823; + union rhs_value I824; + vec32 I718; + union { + struct nbs_t * first; + struct nbs_t * last; + } I826; +} NBS; +typedef struct { + RP I827; + RP I793; + RP I729; + RP I794; + RmaEblk I726; + RmaEblk I828; + RP I829; + scalar I799; + scalar I777; + char state; + uscope_t I830; + U I831; + RP I832; + scalar I786; + scalar I787; + scalar I788; + RmaClockStruct I790; + RmaClockStruct I791; + RP I767; +} RmaPulse; +typedef enum { + QIRDModuleC = 1, + QIRDSVPackageC = 2, + QIRDSpiceModuleC = 3 +} QIRDModuleType; +typedef struct { + U I836 :1; + U I837 :1; + U I838 :1; + U I839 :1; + U I840 :1; + U I841 :1; + U I842 :1; + U I843 :1; + U I844 :1; + U I845 :1; + U I846 :1; + U I847 :1; + U I848 :1; + U I849 :1; + U I850 :1; + U I851 :1; + U I852 :1; + U I853 :1; + QIRDModuleType I854 :2; + U I855 :1; + U I856 :1; + U I857 :1; + U I858 :1; + U I859 :1; + U I860 :1; + U I861 :1; + U I862 :1; + U I863 :1; + U I864 :1; + U I865 :1; + U I866 :1; + U I867 :1; + U I868 :1; + U I869 :1; + U I870 :1; + U I871 :1; + U I872 :1; + U I873 :1; + U I874 :1; +} BitFlags; +struct qird { + US I4; + US I5; + U I6; + U I7; + char * I8; + char * I9; + U * I10; + char * I11; + char * I12; + U I13; + U I14; + struct vcd_rt * I15; + U I17; + struct _vcdOffset_rt * I18; + U I20; + U I21; + U * I22; + U * I23; + void * I24; + void * I25; + U I26; + int I27; + UP I28; + U I29; + U I30; + U I31; + UP I32; + U * I33; + UP I34; + U I35; + BitFlags I36; + U I37; + U I38; + U I39; + U I40; + U I41; + U * I42; + U I43; + U * I44; + U I45; + U I46; + U I47; + U I48; + U I49; + U I50; + U I51; + U * I52; + U * I53; + U I54; + U I55; + U * I56; + U I57; + U * I58; + U I59; + U I60; + U I61; + U I62; + U * I63; + U I64; + U * I65; + U I66; + U I67; + U I68; + U I69; + U I70; + U I71; + U * I72; + char * I73; + U I74; + U I75; + U I76; + U I77; + U I78; + U * I79; + U I80; + U I81; + U I82; + UP * I83; + U I84; + U I85; + U I86; + U I87; + U I88; + U I89; + U * I90; + U I91; + U I92; + U * I93; + U * I94; + U * I95; + U * I96; + U * I97; + U I98; + U I99; + struct taskInfo * I100; + U I102; + U I103; + U I104; + int * I105; + U * I106; + UP * I107; + U * I108; + U I109; + U I110; + U I111; + U I112; + U I113; + struct qrefer * I114; + U * I116; + unsigned * I117; + void * I118; + U I119; + U I120; + struct classStaticReferData * I121; + U I123; + U * I124; + U I125; + U * I126; + U I127; + struct wakeupInfoStruct * I128; + U I130; + U I131; + U I132; + U * I133; + U I134; + U * I135; + U I136; + U I137; + U I138; + U * I139; + U I140; + U * I141; + U I142; + U I143; + U * I144; + U I145; + U I146; + U * I147; + U * I148; + U * I149; + U I150; + U I151; + U I152; + U I153; + U I154; + struct qrefee * I155; + U * I157; + U I158; + struct qdefrefee * I159; + U * I161; + int (* I162)(void); + char * I163; + U I164; + U I165; + void * I166; + void * I167; + NumLibs_t I168; + char * I169; + U * I170; + U I171; + U I172; + U I173; + U I174; + U I175; + U * I176; + U * I177; + int I178; + struct clock_load * I179; + int I194; + struct clock_data * I195; + int I211; + struct clock_hiconn * I212; + U I216; + U I217; + U I218; + U I219; + U * I220; + U * I221; + U I222; + void * I223; + U I224; + U I225; + UP * I226; + void * I227; + U I228; + UP * I229; + U * I230; + int (* I231)(void); + U * I232; + UP * I233; + U * I234; + U I235 :1; + U I236 :31; + U I237; + U I238; + UP * I239; + U * I240; + U I241 :1; + U I242 :1; + U I243 :1; + U I244 :1; + U I245 :28; + U I246; + U I247; + U I248; + U I249 :31; + U I250 :1; + UP * I251; + UP * I252; + U * I253; + U * I254; + U * I255; + U * I256; + UP * I257; + UP * I258; + UP * I259; + U * I260; + UP * I261; + UP * I262; + UP * I263; + UP * I264; + char * I265; + U I266; + U I267; + U I268; + UP * I269; + U I270; + UP * I271; + UP * I272; + UP * I273; + UP * I274; + UP * I275; + UP * I276; + UP * I277; + UP * I278; + UP * I279; + UP * I280; + UP * I281; + UP * I282; + UP * I283; + UP * I284; + U * I285; + U * I286; + UP * I287; + U I288; + U I289; + U I290; + U I291; + U I292; + U I293; + U I294; + U I295; + char * I296; + U * I297; + U I298; + U I299; + U I300; + U I301; + U I302; + UP * I303; + UP * I304; + UP * I305; + UP * I306; + struct daidirInfo * I307; + struct vcs_tftable * I309; + U I311; + UP * I312; + UP * I313; + U I314; + U I315; + U I316; + UP * I317; + U * I318; + UP * I319; + UP * I320; + struct qird_hil_data * I321; + UP (* I323)(void); + UP (* I324)(void); + UP (* I325)(void); + UP (* I326)(void); + UP (* I327)(void); + int * I328; + int (* I329)(void); + char * I330; + UP * I331; + UP * I332; + UP (* I333)(void); + int (* I334)(void); + int * I335; + int (* I336)(void); + int * I337; + char * I338; + U * I339; + U * I340; + U * I341; + U * I342; + void * I343; + U I344; + void * I345; + U I346; + U I347; + U I348; + U I349; + U I350; + U I351; + char * I352; + UP * I353; + U * I354; + U * I355; + U I356 :15; + U I357 :14; + U I358 :1; + U I359 :1; + U I360 :1; + U I361 :3; + U I362 :1; + U I363 :1; + U I364 :17; + U I365 :3; + U I366 :5; + U I367 :1; + U I368 :1; + U I369; + U I370; + struct scope * I371; + U I373; + U I374; + U I375; + U * I376; + U * I377; + U * I378; + U I379; + U I380; + U I381; + struct pcbt * I382; + U I392; + U I393; + U I394; + U I395; + void * I396; + void * I397; + void * I398; + int I399; + U * I400; + U I401; + U I402; + U I403; + U I404; + U I405; + U I406; + U I407; + void * I408; + UP * I409; + U I410; + U I411; + void * I412; + U I413; + void * I414; + U I415; + void * I416; + U I417; + int (* I418)(void); + int (* I419)(void); + void * I420; + void * I421; + void * I422; + U I423; + U I424; + U I425; + U I426; + U I427; + U I428; + char * I429; + U I430; + U * I431; + U I432; + U * I433; + U I434; + U I435; + U I436; + U I437; + U I438; + U I439; + U * I440; + U I441; + U I442; + U * I443; + U I444; + U I445; + U I446; + U * I447; + char * I448; + U I449; + U I450; + U I451; + U I452; + U * I453; + U * I454; + U I455; + U * I456; + U * I457; + U I458; + U I459; + U I460; + UP * I461; + U I462; + U I463; + U I464; + struct cosim_info * I465; + U I467; + U * I468; + U I469; + void * I470; + U I471; + U * I472; + U I473; + struct hybridSimReferrerData * I474; + U I476; + U * I477; + U I478; + U I479; + U * I480; + U I481; + U * I482; + U I483; + U * I484; + U I485; + U I486; + U I487; + U I488; + U I489; + U I490; + U I491; + U I492; + U I493; + U * I494; + U * I495; + void (* I496)(void); + U * I497; + UP * I498; + struct mhdl_outInfo * I499; + UP * I501; + U I502; + UP * I503; + U I504; + void * I505; + U * I506; + void * I507; + char * I508; + int (* I509)(void); + U * I510; + char * I511; + char * I512; + U I513; + U * I514; + char * I515; + U I516; + struct regInitInfo * I517; + UP * I519; + U * I520; + char * I521; + U I522; + U I523; + U I524; + U I525; + U I526; + U I527; + U I528; + U I529; + UP * I530; + U I531; + U I532; + U I533; + U I534; + UP * I535; + U I536; + UP * I537; + U I538; + U I539; + U I540; + U * I541; + U I542; + U I543; + U I544; + U * I545; + U * I546; + UP * I547; + UP * I548; + void * I549; + UP I550; + void * I551; + void * I552; + void * I553; + void * I554; + void * I555; + UP I556; + U * I557; + U * I558; + void * I559; + U I560 :1; + U I561 :31; + U I562; + U I563; + U I564; + int I565; + U I566 :1; + U I567 :1; + U I568 :1; + U I569 :29; + void * I570; + void * I571; + void * I572; + void * I573; + void * I574; + UP * I575; + U * I576; + U I577; + char * I578; + U * I579; + U * I580; + char * I581; + int * I582; + UP * I583; + struct etype * I584; + U I637; + U I638; + U * I639; + struct etype * I640; + U I641; + U I642; + U I643; + U * I644; + void * I645; + U I646; + U I647; + void * I648; + U I649; + U I650; + U * I651; + U * I652; + char * I653; + U I654; + struct covreg_rt * I655; + U I657; + U I658; + U * I659; + U I660; + U * I661; + U I662; + U I663; + U * I664; +}; +typedef struct pcbt { + U * I384; + UP I385; + U I386; + U I387; + U I388; + U I389; + U I390; + U I391; +} PCBT; +struct iptmpl { + QIRD * I734; + struct vcs_globals_t * I735; + void * I737; + UP I738; + UP I739; + struct iptmpl * I729[2]; +}; +typedef unsigned long long FileOffset; +typedef struct _RmaMultiInputTable { + U I881 :1; + U I882 :1; + U I672 :2; + U I673 :4; + U I674 :5; + U I883 :1; + U I884 :1; + U I885 :1; + U I886 :1; + U I887 :1; + U I888 :1; + U I889; + U I890; + U I203; + U I891; + U I892 :1; + U I893 :31; + union { + U utable; + U edgeInputNum; + } I699; + U I894 :4; + U I895 :4; + U I896 :4; + U I897 :4; + U I898 :4; + U I899 :4; + U I900 :1; + U I901 :1; + U I902 :1; + U I903 :1; + U I904 :5; + HsimExprChar * I905; + UB * I906; + UB * I907; + struct _RmaMultiInputTable * I880; + struct _RmaMultiInputTable * I909; +} RmaMultiInputTable; +typedef struct _HsCgPeriod { + U I955; + U I956; +} HsCgPeriod; +typedef struct { + U I957[2]; + U I958 :1; + U I959 :1; + U I960 :8; + U I961 :8; + U I962 :8; + U I963 :4; + U I964 :1; + U I965 :1; + unsigned long long I966; + unsigned long long I967; + unsigned long long I968; + unsigned long long I969; + unsigned long long I956; + U I955; + U I970; + U I971; + U I972; + U I973; + U I974; + HsCgPeriod * I975[10]; +} HsimSignalMonitor; +typedef struct { + FlatNodeNum I976; + InstNum I977; + U I915; + scalar I978; + UB I979; + UB I980; + UB I981; + UB I982; + UB I983; + UB I984; + U I985; + U I986; + U I987; + U I988; + U I989; + U I990; + U I991; + U I992; + U I993; + HsimSignalMonitor * I994; + RP I995; + RmaTimeStamp64 I996; + U I997; + RmaTimeStamp64 I998; + U I999; + UB I1000; +} HsimNodeRecord; +typedef RP RCICODE; +typedef struct { + RP I1005; + RP I729; +} RmaIbfIp; +typedef struct { + RP I1005; + RP pcode; +} RmaIbfPcode; +typedef struct { + RmaEblk I726; +} RmaEvTriggeredOrSyncLoadCg; +typedef struct { + RO I877; + RP pcode; +} SchedGateFanout; +typedef struct { + RO I877; + RP pcode; + U I936[4]; +} SchedSelectGateFanout; +typedef struct { + RP pcode; + RmaEblklq I726; +} SchedGateEblk; +typedef struct { + RP pcode; + RmaEblklq I726; + UB * I1006; +} SchedSelectGateEblk; +typedef struct { + RP I1007; + RP pfn; + RP pcode; +} RmaSeqPrimOutputEblkData; +typedef struct { + RmaEblk I726; + RP I1008; +} RmaAnySchedSampleSCg; +typedef struct { + RmaEblk I726; + RP I1006; + RP I1008; + vec32 I1009; +} RmaAnySchedVCg; +typedef struct { + RmaEblk I726; + RP I1006; + RP I1008; + vec32 I776[1]; +} RmaAnySchedWCg; +typedef struct { + RmaEblk I726; + RP I1006; + RP I1008; + scalar I1010[1]; +} RmaAnySchedECg; +typedef struct { + U I1011; + U I714; + U I915; + U I1012; + RmaIbfIp * I1013; + EBLK I726; + void * val; +} RmaThreadSchedCompiledLoads; +typedef struct { + U I714; + U I722; + RmaThreadSchedCompiledLoads * I1014; +} RmaSchedCompileLoadsCg; +typedef struct { + RP I1015; +} RmaRootCbkCg; +typedef struct { + RP I1016; +} RmaRootForceCbkCg; +typedef struct { + RmaEblk I726; + RP I1017; +} RmaForceCbkJmpCg; +typedef struct { + U I5; + U I722 :31; + U I1018 :1; + vec32 I808; + U I1019; + RP I1020; + RP I1021; +} RmaForceSelectorV; +typedef struct { + U I5; + RmaIbfPcode I1027; +} RmaNetTypeDriverGate; +typedef struct { + U I5; + U I668; + RmaIbfPcode I1027[1]; +} RmaNetTypeScatterGate; +typedef struct { + U I5; + RmaIbfPcode I1027; +} RmaNetTypeGatherGate; +typedef struct { + RmaIbfPcode I1028; + U I1029 :3; + U I1030 :1; + U I1031 :1; + U I890 :16; +} RmaNbaGateOfn; +typedef struct { + U I5; + NBS I1032; + RmaIbfPcode I1028; +} RmaNbaGate1; +typedef struct { + RP ptable; + RP pfn; + RP pcode; +} Rma1InputGateFaninCgS; +typedef struct RmaSeqPrimOutputS_ RmaSeqPrimOutputOnClkS; +struct RmaSeqPrimOutputS_ { + RP pfn; + RP I1035; + U state; + U I1036; + RP I1037; + U I706; + scalar val; +}; +typedef struct { + U I5; + U iinput; + UB I1039; + RP I1040; +} RmaCondOptLoad; +typedef struct { + U I5; + U iinput; + UB I1039; + RP I1040; +} RmaMacroStateUpdate; +typedef struct { + U I5; + U state; + U I1041; + UB I1039; + U * I1042; +} RmaMacroState; +typedef struct { + U iinput; + RP I1043; +} RmaMultiInputLogicGateCg; +typedef struct { + U iinput; + RP ptable; + RP I1043; +} RmaSeqPrimEdgeInputCg; +typedef struct { + RmaEblk I726; + RP pcode; +} RmaSched0GateCg; +typedef struct { + RmaEblk I726; + RP pcode; + RP pfn; +} RmaUdpDeltaGateCg; +typedef struct { + RmaEblk I726; + RP pcode; + RP pfn; + scalar I1044; +} RmaSchedDeltaGateCg; +typedef struct { + UB I1045; + RP I1046; + RP I1047; +} RmaPropNodeSeqLhsSCg; +typedef struct { + RmaEblk I726; + RP pcode; + U I915; + U I715[1]; +} RmaBitEdgeEblk; +typedef struct { + U I5; + RP I807; + RmaEblk I726; + RmaIbfPcode I1028; +} RmaGateDelay; +typedef struct { + U I5; + RP I807; + RmaEblk I726; + RmaIbfPcode I1028; +} RmaGateBehavioralDelay; +typedef struct { + U I5; + union { + RP I1290; + RP I1578; + RP I1592; + } I781; + RmaIbfPcode I1028; +} RmaMPDelay; +typedef struct { + U I5; + RmaPulse I1048; + RmaIbfPcode I1028; +} RmaMPPulseHybridDelay; +typedef struct { + U I5; + RmaIbfPcode I1028; + RmaMps I1049; +} RmaMPHybridDelay; +typedef struct { + U I5; + U I1050; + RmaIbfPcode I1028; + RmaEblk I766; +} RmaMPHybridDelayPacked; +typedef struct { + U I5; + RmaIbfPcode I1028; + RmaMpspNewCsdf I1051; +} RmaMPPulseDelay; +typedef struct { + U I5; + RmaMpsp I1051; + RmaIbfPcode I1028; +} RmaMPPulseOptHybridDelay; +typedef struct _RmaBehavioralTransportDelay { + U I5; + RP I685; + RmaTransEventHdr I921; + RP I804; + RmaIbfPcode I1028; +} RmaBehavioralTransportDelayS; +typedef struct { + U I5; + U I685; + RmaTransEventHdr I921; + RP I804; + RmaIbfPcode I1028; +} RmaNtcTransDelay; +typedef struct { + U I5; + U I685; + RmaEblk I726; + RmaIbfPcode I1028; +} RmaNtcTransMpwOptDelay; +typedef struct { + U I5; + RmaEblk I726; + RmaIbfPcode I1028; +} RmaNtcTransZeroDelay; +typedef struct { + U I5; + U I1052; + U I1053; + RmaTransEventHdr I921; + RP I804; + RmaIbfPcode I1028; +} RmaNtcTransDelayRF; +typedef struct { + U I5; + U I1052; + U I1053; + RmaEblk I726; + RmaIbfPcode I1028; +} RmaNtcTransMpwOptDelayRF; +typedef struct { + U I5; + RP I1054; + RmaTransEventHdr I921; + RP I804; + RmaIbfPcode I1028; +} RmaICTransDelay; +typedef struct { + U I5; + RP I1054; + RmaEblk I726; + RmaIbfPcode I1028; +} RmaICTransMpwOptDelay; +typedef struct { + U I5; + RmaEblk I726; + RmaIbfPcode I1028; +} RmaICTransZeroDelay; +typedef struct { + U I5; + RP I807; + RmaEblk I726; + RmaIbfPcode I1028; +} RmaICSimpleDelay; +typedef struct { + U I5; + union { + RP psimple; + RP I1578; + RP I1592; + } I781; + RmaIbfPcode I1028; +} RmaICDelay; +typedef struct { + U I5; + RP I807; + RmaEblk I726; + RmaIbfPcode I1028; +} RmaPortDelay; +typedef struct { + U I890; + RP I1058; +} RmaRtlXEdgesLoad; +typedef struct { + U I5; + RmaRtlXEdgesLoad I1058[(5)]; +} RmaRtlXEdgesHdr; +typedef struct { + U I5; + US I1059; + US I1060 :1; + US I904 :15; + RP I1061; + RP I1062; + RP I1063; +} RmaRtlEdgeBlockHdr; +typedef struct { + RP I1064; + RP I1065; +} RemoteDbsedLoad; +typedef struct { + RmaEblk I726; + RP I1066; + RP I1067; + U I1068 :16; + U I1069 :2; + U I1070 :2; + U I1071 :1; + U I1072 :8; + U I904 :3; + U I471; + RP I1073; + RP I811[(5)]; + RP I813[(5)]; + US I1074; + US I1075; + RemoteDbsedLoad I1076[1]; +} RmaRtlEdgeBlock; +typedef struct TableAssign_ { + struct TableAssign_ * I880; + struct TableAssign_ * I798; + U I5; + U I1078 :1; + U I1079 :1; + U I1080 :2; + U I1081 :1; + U I706 :8; + U I1082 :1; + U I1083 :1; + U I1084 :1; + U I1085 :1; + U I1086 :1; + U I1087 :1; + U I904 :13; + RP ptable; + RP I1043; +} TableAssign; +typedef struct TableAssignLayoutOnClk_ { + struct TableAssignLayoutOnClk_ * I880; + struct TableAssignLayoutOnClk_ * I798; + U I5; + U I1078 :1; + U I1079 :1; + U I1080 :2; + U I1081 :1; + U I706 :8; + U I1082 :1; + U I1083 :1; + U I1084 :1; + U I1085 :1; + U I1086 :1; + U I1087 :1; + U I904 :13; + RP ptable; + RmaSeqPrimOutputOnClkS I1089; + RmaEblk I726; +} TableAssignLayoutOnClk; +typedef struct { + U state; + U I1090; +} RmaSeqPrimOutputOnClkOpt; +typedef struct TableAssignLayoutOnClkOpt_ { + struct TableAssignLayoutOnClkOpt_ * I880; + struct TableAssignLayoutOnClkOpt_ * I798; + U I1092; + U I1078 :1; + U I1079 :1; + U I1080 :2; + U I1081 :1; + U I706 :8; + U I1082 :1; + U I1083 :1; + U I1084 :1; + U I1085 :1; + U I1086 :1; + U I1087 :1; + U I904 :13; + RmaSeqPrimOutputOnClkOpt I1089; + RmaSeqPrimOutputEblkData I1093; +} TableAssignLayoutOnClkOpt; +typedef struct { + U I5; + RP I798; + RP I1094; +} RmaTableAssignList; +typedef struct { + U I5; + RP I798; + RP I1094; + RP I1095; + RP I1037; + US I706; + UB I978; + UB I1096; + UB I1097; + UB I772; + RP I1098[0]; +} RmaThreadTableAssignList; +typedef struct { + RP I1095; + RP I1037; + US I706; + UB I978; + UB I1096; + UB I1097; + UB I772; +} RmaThreadTableHeader; +typedef struct { + RP I1064; +} RmaWakeupListCg; +typedef struct { + RP I1064; +} RmaWakeupArrayCg; +typedef struct { + RP I1064; + RP I1099; +} RmaPreCheckWakeupListCg; +typedef struct { + RP I1064; + RP I1099; +} RmaPreCheckWakeupArrayCg; +typedef struct { + U I1100; + U I706; + RmaTimeStamp I1101[1]; +} RmaTsArray; +typedef struct { + U iinput; + RP I1102; +} RmaConditionsMdb; +typedef struct { + RP I1103; + RP I1104; + U I1105; +} RmaTcListHeader; +typedef struct { + RP I880; + RP I1106; + RP I1107; + RP I721; + U I1108; + scalar I890; + scalar I1109; + US I1110 :1; + US I1111 :1; + US I1112 :1; + US I1113 :1; + US I1114 :1; + US I1115 :1; + US I1116 :5; +} RmaTcCoreSimple; +typedef struct { + RP I880; + RP I1106; + RP I1107; + RP I721; + U I1108; + scalar I890; + scalar I1109; + US I1110 :1; + US I1111 :1; + US I1112 :1; + US I1113 :1; + US I1114 :1; + US I1115 :1; + US I1116 :5; + RP I1117; +} RmaTcCoreConditional; +typedef struct { + RP I880; + RP I1106; + RP I1107; + RP I721; + U I1108; + scalar I890; + scalar I1109; + US I1110 :1; + US I1111 :1; + US I1112 :1; + US I1113 :1; + US I1114 :1; + US I1115 :1; + US I1116 :5; + RP I1117; + RP I1118; +} RmaTcCoreConditionalOpt; +typedef struct { + RP I880; + RP I1106; + RP I1107; + RP I721; + U I1108; + scalar I890; + scalar I1109; + US I1110 :1; + US I1111 :1; + US I1112 :1; + US I1113 :1; + US I1114 :1; + US I1115 :1; + US I1116 :5; + RP I1118; + RP I1119; + U I1120; + RmaConditionsMdb arr[1]; +} RmaTcCoreConditionalMtc; +typedef struct { + RP I1107; + RP I721; + U I1108; + scalar I890; + scalar I1109; + US I1110 :1; + US I1111 :1; + US I1112 :1; + US I1113 :1; + US I1114 :1; + US I1115 :1; + US I1116 :5; +} RmaTcCoreSimpleNoList; +typedef struct { + RP I1107; + RP I721; + U I1108; + scalar I890; + scalar I1109; + US I1110 :1; + US I1111 :1; + US I1112 :1; + US I1113 :1; + US I1114 :1; + US I1115 :1; + US I1116 :5; + RP I1035; +} RmaTcCoreSimpleNoListMdb; +typedef struct { + RP I1107; + RP I721; + U I1108; + scalar I890; + scalar I1109; + US I1110 :1; + US I1111 :1; + US I1112 :1; + US I1113 :1; + US I1114 :1; + US I1115 :1; + US I1116 :5; + RP I1117; +} RmaTcCoreConditionalNoList; +typedef struct { + RP I1107; + RP I721; + U I1108; + scalar I890; + scalar I1109; + US I1110 :1; + US I1111 :1; + US I1112 :1; + US I1113 :1; + US I1114 :1; + US I1115 :1; + US I1116 :5; + RP I1117; + RP I1118; +} RmaTcCoreConditionalOptNoList; +typedef struct { + RP I1107; + RP I721; + U I1108; + scalar I890; + scalar I1109; + US I1110 :1; + US I1111 :1; + US I1112 :1; + US I1113 :1; + US I1114 :1; + US I1115 :1; + US I1116 :5; + RP I1118; + RP I1119; + U I1120; + RmaConditionsMdb arr[1]; +} RmaTcCoreConditionalMtcNoList; +typedef struct { + RP I1107; + RP I721; + U I1108; + scalar I890; + scalar I1109; + US I1110 :1; + US I1111 :1; + US I1112 :1; + US I1113 :1; + US I1114 :1; + US I1115 :1; + US I1116 :5; + RP I1118; + RP I1119; + RP I1035; + U I1120; + RmaConditionsMdb arr[1]; +} RmaTcCoreConditionalMtcNoListMdb; +typedef struct { + RP I1107; + RP I721; + U I1108; + scalar I890; + scalar I1109; + US I1110 :1; + US I1111 :1; + US I1112 :1; + US I1113 :1; + US I1114 :1; + US I1115 :1; + US I1116 :5; + RP I1117; + RP I1035; +} RmaTcCoreConditionalNoListMdb; +typedef struct { + RP I1107; + RP I721; + U I1108; + scalar I890; + scalar I1109; + US I1110 :1; + US I1111 :1; + US I1112 :1; + US I1113 :1; + US I1114 :1; + US I1115 :1; + US I1116 :5; + U I1122; + RP I1123; + RP I1124; + RP I1117; + RP I1125; + RP I1126; + RmaTimeStamp I1127; +} RmaTcCoreNochange; +typedef struct { + RP I1128; + RP I880; +} RmaTcCoreNochangeList; +typedef struct { + RP I1102; + RmaTimeStamp I1129; + scalar I1130; +} RmaConditionalTSLoadNoList; +typedef struct { + RP I880; + RP I1102; + RmaTimeStamp I1129; + scalar I1130; +} RmaConditionalTSLoad; +typedef struct { + RmaTimeStamp I1129; + scalar I1130; + US I890; + RP I1118; +} RmaConditionalTSLoadOptNoList; +typedef struct { + RP I880; + RmaTimeStamp I1129; + scalar I1130; + US I890; + RP I1118; +} RmaConditionalTSLoadOpt; +typedef struct { + RP I1118; + RP I1131; + U I1120; + RmaConditionsMdb arr[1]; +} RmaConditionalTSLoadMtcNoList; +typedef struct { + RP I1035; + RP I1118; + RP I1131; + U I1120; + RmaConditionsMdb arr[1]; +} RmaConditionalTSLoadMtcNoListMdb; +typedef struct { + RP I880; + RP I1118; + RP I1131; + U I1120; + RmaConditionsMdb arr[1]; +} RmaConditionalTSLoadMtc; +typedef struct { + U I1132; + U I1133; + FlatNodeNum I1004; + U I915; + U I1134; + U I1135; + RmaIbfPcode I1028; + union { + scalar I1136; + vec32 I1137; + scalar * I1138; + vec32 * I1139; + } val; +} RmaScanSwitchData; +typedef struct { + RP I880; + RP I798; + RP I1140; +} RmaDoublyLinkedListElem; +typedef struct { + RP I1141; + U I1142 :1; + U I1143 :1; + U I1144 :1; + U I1145 :4; + U I904 :25; + U I1146; +} RmaSwitchGateInCbkListInfo; +typedef struct { + union { + RmaDoublyLinkedListElem I1640; + RmaSwitchGateInCbkListInfo I2; + } I699; + RmaIbfPcode I1028; +} RmaSwitchGate; +typedef struct RmaNonEdgeLoadData1_ { + US I1147; + scalar val; + scalar I1148 :1; + scalar I1149 :1; + scalar I1150 :1; + scalar I1151 :1; + scalar I1152 :1; + U I1153; + RP I811; + RP I1154; + RP I1004; + RP I1155; + RP I1156; +} RmaNonEdgeLoadData1; +typedef struct RmaNonEdgeLoadHdr1_ { + UB I1148; + UB I1157; + UB I978; + RmaNonEdgeLoadData1 * I1058; + RmaNonEdgeLoadData1 * I798; + void * I1158; +} RmaNonEdgeLoadHdr1; +typedef struct RmaNonEdgeLoadHdrPrl1_ { + U I1159; + RP I721; +} RmaNonEdgeLoadHdrPrl1; +typedef struct RmaChildClockProp_ { + RP I811; + RP I1160; + RP I1004; + RP pcode; + scalar val; +} RmaChildClockProp; +typedef struct RmaChildClockPropList1_ { + RmaChildClockProp * I1058; + RmaChildClockProp * I798; +} RmaChildClockPropList1; +typedef struct { + U I5; + U I1161; +} RmaHDLCosimDUTGate; +typedef struct { + UB I1162; + UB I1163 :1; + UB I1164 :1; + UB I1165 :1; + UB I1166 :1; + UB I904 :4; + US cedges; +} RmaMasterXpropLoadHdr; +typedef struct { + UB I1167; + UB I1168; + UB I1169; + UB I1170; + U cedges :30; + U I1164 :1; + U I1171 :1; + U I1172; + U I1173; + RP I1174; + RP I1175; + RmaRtlEdgeBlockHdr * I1176; +} RmaChildXpropLoadHdr; +struct clock_load { + U I181 :5; + U I182 :12; + U I183 :1; + U I184 :2; + U I185 :1; + U I186 :1; + U I187 :1; + U I188 :9; + U I189; + U I190; + void (* pfn)(void * I192, char val); +}; +typedef struct clock_data { + U I197 :1; + U I198 :1; + U I199 :1; + U I200 :1; + U I181 :5; + U I182 :12; + U I201 :6; + U I202 :1; + U I184 :2; + U I185 :1; + U I188 :1; + U I203; + U I204; + U I205; + U I189; + U I206; + U I207; + U I208; + U I209; + U I210; +} HdbsClockData; +struct clock_hiconn { + U I214; + U I215; + U I189; + U I184; +}; +typedef struct _RmaDaiCg { + RP I1177; + RP I1178; + U I1179; +} RmaDaiCg; +typedef union _RmaCbkMemOptUnion { + RP I1177; + RP I1180; + RP I1181; +} RmaCbkMemOptUnion; +typedef struct _RmaDaiOptCg { + RmaCbkMemOptUnion I1182; +} RmaDaiOptCg; +struct futq_slot2 { + U I758; + U I759[32]; +}; +struct futq_slot1 { + U I755; + struct futq_slot2 I756[32]; +}; +struct futq_info { + scalar * I750; + U I751; + U I752; + struct futq_slot1 I753[32]; +}; +struct futq { + struct futq * I740; + struct futq * I742; + RmaEblk * I743; + RmaEblk * I744; + U I731; + U I1; +}; +struct sched_table { + struct futq * I745; + struct futq I746; + struct hash_bucket * I747; + struct hash_bucket * I749; +}; +struct dummyq_struct { + clock_struct I1183; + EBLK * I1184; + EBLK * I1185; + EBLK * I1186; + struct futq * I1187; + struct futq * I1188; + struct futq * I1189; + struct sched_table * I1190; + struct futq_info * I1192; + struct futq_info * I1194; + U I1195; + U I1196; + U I1197; + U I1198; + U I1199; + U I1200; + U I1201; + struct millenium * I1202; + EBLK * I1204; + EBLK * I1205; + EBLK * I1206; + EBLK * I1207; + EBLK * I1208; + EBLK * I1209; + EBLK * I1210; + EBLK * I1211; + EBLK * I1212; + EBLK * I1213; + EBLK * I1214; + EBLK * I1215; + EBLK * I1216; + EBLK * I1217; + EBLK * I1218; + EBLK * I1219; + EBLK * I1220; + EBLK * I1221; + MPS * I1222; + struct retain_t * I1223; + EBLK * I1224; + EBLK * I1225; + EBLK * I1226; + EBLK * I1227; + EBLK * I1228; + EBLK * I1229; + EBLK * I1230; + EBLK * I1231; + EBLK * I1232; + EBLK * I1233; + EBLK * I1234; + EBLK * I1235; + EBLK * I1236; + EBLK * I1237; + EBLK * I1238; + EBLK * I1239; + EBLK * I1240; + EBLK * I1241; + EBLK * I1242; + EBLK * I1243; + EBLK * I1244; + EBLK * I1245; + EBLK * I1246; + EBLK * I1247; + EBLK * I1248; + EBLK * I1249; + EBLK I1250; + EBLK * I1251; + EBLK * I1252; + EBLK * I1253; + EBLK * I1254; + int I1255; + int I1256; + struct vcs_globals_t * I1257; + clock_struct I1258; + unsigned long long I1259; + EBLK * I1260; + EBLK * I1261; + void * I1262; +}; +typedef void (* FP)(void * , scalar ); +typedef void (* FP1)(void * ); +typedef void (* FPRAP)(void * , vec32 * , U ); +typedef U (* FPU1)(void * ); +typedef void (* FPV)(void * , UB * ); +typedef void (* FPVU)(void * , UB * , U ); +typedef void (* FPLSEL)(void * , scalar , U ); +typedef void (* FPLSELV)(void * , vec32 * , U , U ); +typedef void (* FPFPV)(UB * , UB * , U , U , U , U , U , UB * , U ); +typedef void (* FPFA)(UB * , UB * , U , U , U , U , U , U , UB * , U ); +typedef void (* FPRPV)(UB * , U , U , U ); +typedef void (* FPEVCDLSEL)(void * , scalar , U , UB * ); +typedef void (* FPEVCDLSELV)(void * , vec32 * , U , U , UB * ); +typedef void (* FPNTYPE_L)(void * , void * , U , U , UB * , UB * , UB * , UB * , UB * , UB * , UB * , U ); +typedef void (* FPNTYPE_H)(void * , void * , U , U , UB * , UB * , UB * , UB * , U ); +typedef void (* FPNTYPE_LPAP)(void * , void * , void * , U , U , UB * , UB * , U ); +typedef void (* FPNTYPE_HPAP)(void * , void * , void * , U , U , UB * , UB * , UB * , UB * , U ); +typedef struct _lqueue { + EBLK * I727; + EBLK * I1263; + int I1264; + struct _lqueue * I769; +} Queue; +typedef struct { + void * I1266; + void * I1267; + void * I1268[2]; + void * I1269; +} ClkLevel; +typedef struct { + unsigned long long I1270; + EBLK I1171; + U I1271; + U I1272; + union { + void * pHeap; + Queue * pList; + } I699; + unsigned long long I1273; + ClkLevel I1274; + Queue I1275[1]; +} Qhdr; +extern UB Xvalchg[]; +extern UB X4val[]; +extern UB X3val[]; +extern UB X2val[]; +extern UB XcvtstrTR[]; +extern UB Xcvtstr[]; +extern UB Xbuf[]; +extern UB Xbitnot[]; +extern UB Xwor[]; +extern UB Xwand[]; +extern U Xbitnot4val[]; +extern UB globalTable1Input[]; +extern __thread unsigned long long vcs_clocks; +extern UB Xunion[]; +extern U fRTFrcRelCbk; +extern FP txpFnPtr; +extern FP rmaFunctionArray[]; +extern UP rmaFunctionRtlArray[]; +extern FP rmaFunctionLRArray[]; +extern U rmaFunctionCount; +extern U rmaFunctionLRCount; +extern U rmaFunctionLRDummyCount; +extern UP rmaFunctionDummyEndPtr; +extern FP rmaFunctionFanoutArray[]; +extern __thread UB dummyScalar; +extern __thread UB fScalarIsForced; +extern __thread UB fScalarIsReleased; +extern U fNotimingchecks; +extern U fFsdbDumpOn; +extern RP * iparr; +extern FP1 * rmaPostAnySchedFnPtr; +extern FP1 * rmaPostAnySchedFnSamplePtr; +extern FP1 * rmaPostAnySchedVFnPtr; +extern FP1 * rmaPostAnySchedWFnPtr; +extern FP1 * rmaPostAnySchedEFnPtr; +extern FP1 * rmaPostSchedUpdateClockStatusFnPtr; +extern FP1 * rmaPostSchedUpdateClockStatusNonCongruentFnPtr; +extern FP1 * rmaPostSchedUpdateEvTrigFnPtr; +extern FP1 * rmaSched0UpdateEvTrigFnPtr; +extern FP1 * rmaPostSchedRecoveryResetDbsFnPtr; +extern U fGblDataOrTime0Prop; +extern UB rmaEdgeStatusValArr[]; +extern FP1 * propForceCbkSPostSchedCgFnPtr; +extern FP1 * propForceCbkMemoptSPostSchedCgFnPtr; +extern UB * ptableGbl; +extern U * vcs_ptableOffsetsGbl; +extern UB * expandedClkValues; +extern __thread Qhdr * lvlQueue; +extern __thread unsigned threadIndex; +extern int cPeblkThreads; +extern US xedges[]; +extern U mhdl_delta_count; +extern U ignoreSchedForScanOpt; +extern U fignoreSchedForDeadComboCloud; +extern int fZeroUser; +extern U fEveBusPullVal; +extern U fEveBusPullFlag; +extern U fFutEventPRL; +extern U fParallelEBLK; +extern U fBufferingEvent; +extern __thread UB fNettypeIsForced; +extern __thread UB fNettypeIsReleased; +extern EBLK * peblkFutQ1Head; +extern EBLK * peblkFutQ1Tail; +extern US * edgeActionT; +extern unsigned long long * derivedClk; +extern U fHashTableSize; +extern U fSkipStrChangeOnDelay; +extern U fHsimTcheckOpt; +extern scalar edgeChangeLookUp[4][4]; +extern U fDoingTime0Prop; +extern U fLoopDetectMode; +extern int gFLoopDectCodeEna; +extern U fLoopReportRT; + + +extern void *mempcpy(void* s1, void* s2, unsigned n); +extern UB* rmaEvalDelays(UB* pcode, scalar val); +extern UB* rmaEvalDelaysV(UB* pcode, vec32* pval); +extern void rmaPopTransEvent(UB* pcode); +extern void rmaSetupFuncArray(UP* ra, U c, U w); +extern void rmaSetupRTLoopReportPtrs(UP* funcs, UP* rtlFuncs, U cnt, U cntDummy, UP end); +extern void SinitHsimPats(void); +extern void VVrpDaicb(void* ip, U nIndex); +extern int SDaicb(void *ip, U nIndex); +extern void SDaicbForHsimNoFlagScalar(void* pDaiCb, unsigned char value); +extern void SDaicbForHsimNoFlagStrengthScalar(void* pDaiCb, unsigned char value); +extern void SDaicbForHsimNoFlag(void* pRmaDaiCg, unsigned char value); +extern void SDaicbForHsimNoFlag2(void* pRmaDaiCg, unsigned char value); +extern void SDaicbForHsimWithFlag(void* pRmaDaiCg, unsigned char value); +extern void SDaicbForHsimNoFlagFrcRel(void* pRmaDaiCg, unsigned char reason, int msb, int lsb, int ndx); +extern void SDaicbForHsimNoFlagFrcRel2(void* pRmaDaiCg, unsigned char reason, int msb, int lsb, int ndx); +extern void VcsHsimValueChangeCB(void* pRmaDaiCg, void* pValue, unsigned int valueFormat); +extern U isNonDesignNodeCallbackList(void* pRmaDaiCg); +extern void SDaicbForHsimCbkMemOptNoFlagScalar(void* pDaiCb, unsigned char value, unsigned char isStrength); +extern void SDaicbForHsimCbkMemOptWithFlagScalar(void* pDaiCb, unsigned char value, unsigned char isStrength); +extern void SDaicbForHsimCbkMemOptNoFlagScalar(void* pDaiCb, unsigned char value, unsigned char isStrength); +extern void SDaicbForHsimCbkMemOptWithFlagScalar(void* pDaiCb, unsigned char value, unsigned char isStrength); +extern void VVrpNonEventNonRegdScalarForHsimOptCbkMemopt(void* ip, U nIndex); +extern void SDaicbForHsimCbkMemOptNoFlagDynElabScalar(U* mem, unsigned char value, unsigned char isStrength); +extern void SDaicbForHsimCbkMemOptWithFlagDynElabScalar(U* mem, unsigned char value, unsigned char isStrength); +extern void SDaicbForHsimCbkMemOptNoFlagDynElabFrcRel(U* mem, unsigned char reason, int msb, int lsb, int ndx); +extern void SDaicbForHsimCbkMemOptNoFlagFrcRel(void* pDaiCb, unsigned char reason, int msb, int lsb, int ndx); +extern void hsimDispatchCbkMemOptForVcd(RP p, U val); +extern void* hsimGetCbkMemOptCallback(RP p); +extern void hsimDispatchCbkMemOptNoDynElabS(RP* p, U val, U isStrength); +extern void* hsimGetCbkPtrNoDynElab(RP p); +extern void hsimDispatchCbkMemOptDynElabS(U** pvcdarr, U** pcbkarr, U val, U isScalForced, U isScalReleased, U isStrength); +extern void hsimDispatchCbkMemOptNoDynElabVector(RP* /*RmaDaiOptCg* */p, void* pval, U /*RmaValueType*/ vt, U cbits); +extern void copyAndPropRootCbkCgS(RmaRootCbkCg* pRootCbk, scalar val); +extern void copyAndPropRootCbkCgV(RmaRootCbkCg* rootCbk, vec32* pval); +extern void copyAndPropRootCbkCgW(RmaRootCbkCg* rootCbk, vec32* pval); +extern void copyAndPropRootCbkCgE(RmaRootCbkCg* rootCbk, scalar* pval); +extern void Wsvvar_callback_non_dynamic1(RP* ptr, int); +extern void rmaExecEvSyncList(RP plist); +extern void Wsvvar_callback_virt_intf(RP* ptr); +extern void Wsvvar_callback_hsim_var(RP* ptr); +extern void checkAndConvertVec32To2State(vec32* value, vec32* svalue, U cbits, U* pforcedBits); +extern unsigned int fGblDataOrTime0Prop; +extern void SchedSemiLerMP1(UB* pmps, U partId); +extern void SchedSemiLerMPO(UB* pmpso, U partId); +extern void rmaDummyPropagate(void); +extern RP rmaTestCg(RP pcode, U vt, UB* value); +extern void hsUpdateModpathTimeStamp(UB* pmps); +extern void doMpd32One(UB* pmps); +extern void doMpdCommon(MPS* pmps); +extern TimeStamp GET_DIFF_DELAY_FUNC(TimeStamp ts); +extern void SchedSemiLerMP(UB* ppulse, U partId); +extern EBLK *peblkFutQ1Head; +extern EBLK *peblkFutQ1Tail; +extern void scheduleuna(UB *e, U t); +extern void scheduleuna_mp(EBLK *e, unsigned t); +extern void schedule(UB *e, U t); +extern void sched_hsopt(struct dummyq_struct * pQ, EBLK *e, U t); +extern void sched_millenium(struct dummyq_struct * pQ, void *e, U thigh, U t); +extern void schedule_1(EBLK *e); +extern void sched0(UB *e); +extern void sched0Raptor(UB *e); +extern void sched0lq(EBLK *e); +extern void sched0lqnc(EBLK *e); +extern void sched0una(UB *e); +extern void sched0una_th(struct dummyq_struct *pq, UB *e); +extern void hsopt_sched0u_th(struct dummyq_struct *pq, UB *e); +extern void scheduleuna_mp_th(struct dummyq_struct *pq, EBLK *e, unsigned t); +extern void schedal(UB *e); +extern void sched0_th(struct dummyq_struct * pQ, EBLK *e); +extern void sched0u(UB *e); +extern void sched0u_th(struct dummyq_struct *pq, UB *e); +extern void sched0_hsim_front_th(struct dummyq_struct * pQ, UB *e); +extern void sched0_hsim_frontlq_th(struct dummyq_struct * pQ, UB *e); +extern void sched0lq_th(struct dummyq_struct * pQ, UB *e); +extern void schedal_th(struct dummyq_struct * pQ, UB *e); +extern void scheduleuna_th(struct dummyq_struct * pQ, void *e, U t); +extern void schedule_th(struct dummyq_struct * pQ, UB *e, U t); +extern void schedule_1_th(struct dummyq_struct * pQ, EBLK *peblk); +extern void SetupLER_th(struct dummyq_struct * pQ, EBLK *e); +extern void FsdbReportClkGlitch(UB*,U); +extern void AddToClkGLitchArray(EBLK*); +extern void SchedSemiLer_th(struct dummyq_struct * pQ, EBLK *e); +extern void SchedSemiLerTXP_th(struct dummyq_struct * pQ, EBLK *e); +extern void SchedSemiLerTXPFreeVar_th(struct dummyq_struct * pQ, EBLK *e); +extern U getVcdFlags(UB *ip); +extern void VVrpNonEventNonRegdScalarForHsimOpt(void* ip, U nIndex); +extern void VVrpNonEventNonRegdScalarForHsimOpt2(void* ip, U nIndex); +extern void SchedSemiLerTBReactiveRegion(struct eblk* peblk); +extern void SchedSemiLerTBReactiveRegion_th(struct eblk* peblk, U partId); +extern void SchedSemiLerTr(UB* peblk, U partId); +extern void SchedSemiLerNBA(UB* peblk, U partId); +extern void NBA_Semiler(void *ip, void *pNBS); +extern void sched0sd_hsim(UB* peblk); +extern void vcs_sched0sd_hsim_udpclk(UB* peblk); +extern void vcs_sched0sd_hsim_udpclkopt(UB* peblk); +extern void sched0sd_hsim_PRL(UB* peblk); +extern void sched0lq_parallel_clk(EBLK* peblk); +extern U isRtlClockScheduled(EBLK* peblk); +extern void doFgpRaceCheck(UB* pcode, UB* p, U flag); +extern void doSanityLvlCheck(); +extern void sched0lq_parallel_ova(EBLK* peblk); +extern void sched0lq_parallel_ova_precheck(EBLK* peblk); +extern void rmaDlpEvalSeqPrim(UB* peblk, UB val, UB preval); +extern void appendNtcEvent(UB* phdr, scalar s, U schedDelta); +extern void appendTransEventS(RmaTransEventHdr* phdr, scalar s, U schedDelta); +extern void schedRetainHsim(MPS* pMPS, scalar sv, scalar pv); +extern void updateRetainHsim(MPS* pMPS,scalar sv, scalar pv); +extern void hsimCountXEdges(void* record, scalar s); +extern void hsimRegisterEdge(void* sm, scalar s); +extern U pvcsGetPartId(); +extern void HsimPVCSPartIdCheck(U instNo); +extern void debug_func(U partId, struct dummyq_struct* pQ, EBLK* EblkLastEventx); +extern struct dummyq_struct* pvcsGetQ(U thid); +extern EBLK* pvcsGetLastEventEblk(U thid); +extern void insertTransEvent(RmaTransEventHdr* phdr, scalar s, scalar pv, scalar resval, U schedDelta, int re, UB* predd, U fpdd); +extern void insertNtcEventRF(RmaTransEventHdr* phdr, scalar s, scalar pv, scalar resval, U schedDelta, U* delays); +extern U doTimingViolation(RmaTimeStamp ts,RP* pdata, U fskew, U limit, U floaded, U fcondopt, RmaTimeStamp tsNochange); +extern void sched_gate_hsim(EBLK* peblk, unsigned t, RP* offset, U gd_info, U encodeInPcode, void* propValue); +extern int getCurSchedRegion(); +extern FP getRoutPtr(RP, U); +extern U rmaChangeCheckAndUpdateE(scalar* pvalDst, scalar* pvalSrc, U cbits); +extern void rmaUpdateE(scalar* pvalDst, scalar* pvalSrc, U cbits); +extern U rmaChangeCheckAndUpdateEFromW(scalar* pvalDst, vec32* pvalSrc, U cbits); +extern void rmaLhsPartSelUpdateE(scalar* pvalDst, scalar* pvalSrc, U index, U width); +extern void rmaUpdateWithForceSelectorE(scalar* pvalDst, scalar* pvalSrc, U cbits, U* pforceSelector); +extern void rmaUpdateWFromE(vec32* pvalDst, scalar* pvalSrc, U cbits); +extern U rmaLhsPartSelWithChangeCheckE(scalar* pvalDst, scalar* pvalSrc, U index, U width); +extern void rmaLhsPartSelWFromE(vec32* pvalDst, scalar* pvalSrc, U index,U width); +extern U rmaChangeCheckAndUpdateW(vec32* pvalDst, vec32* pvalSrc, U cbits); +extern void rmaUpdateW(vec32* pvalDst, vec32* pvalSrc, U cbits); +extern void rmaUpdateEFromW(scalar* pvalDst, vec32* pvalSrc, U cbits); +extern void *VCSCalloc(size_t size, size_t count); +extern void *VCSMalloc(size_t size); +extern void VCSFree(void *ptr); +extern U rmaLhsPartSelWithChangeCheckW(vec32* pvalDst, vec32* pvalSrc, U index,U width); +extern void rmaLhsPartSelEFromW(scalar* pvalDst, vec32* pvalSrc, U index,U width); +extern U rmaLhsPartSelWithChangeCheckEFromW(scalar* pvalDst, vec32* pvalSrc, U index,U width); +extern void rmaLhsPartSelUpdateW(vec32* pvalDst, vec32* pvalSrc, U index, U width); +extern void rmaEvalWunionW(vec32* dst, vec32* src, U cbits, U count); +extern void rmaEvalWorW(vec32* dst, vec32* src, U cbits, U count); +extern void rmaEvalWandW(vec32* dst, vec32* src, U cbits, U count); +extern void rmaEvalUnionE(scalar* dst, scalar* src, U cbits, U count, RP ptable); +typedef U RmaCgFunctionType; +extern RmaIbfPcode* rmaEvalPartSelectsW(vec32* pvec32, U startIndex, U onWidth, U offWidth, U count, RmaIbfPcode* pibfPcode, U fnonRootForce, UB* pevcdStatus); +extern RmaIbfPcode* rmaEvalPartSelectsWLe32(vec32* pvec32, U startIndex, U onWidth, U offWidth, U count, RmaIbfPcode* pibfPcode, U fnonRootForce, UB* pevcdStatus); +extern RmaIbfPcode* rmaEvalPartSelectsWToE(vec32* pvec32, U startIndex, U onWidth, U offWidth, U count, RmaIbfPcode* pibfPcode, U fnonRootForce); +extern RmaIbfPcode* rmaEvalPartSelectsEToE(scalar* pv, U startIndex, U onWidth, U offWidth, U count, RmaIbfPcode* pibfPcode, U fnonRootForce, UB* pevcdStatus); +extern RmaIbfPcode* rmaEvalPartSelectsEToW(scalar* pv, U startIndex, U onWidth, U offWidth, U count, RmaIbfPcode* pibfPcode, U fnonRootForce); +extern U rmaEvalBitPosEdgeW(vec32* pvalCurr, vec32* pvalPrev, U cbits, U* pedges); +extern U rmaEvalBitNegEdgeW(vec32* pvalCurr, vec32* pvalPrev, U cbits, U* pedges); +extern U rmaEvalBitChangeW(vec32* pvalCurr, vec32* pvalPrev, U cbits, U* pedges); +extern U VcsForceVecVCg(UB* pcode, UB* pval, UB* pvDst, UB* pvCur, U fullcbits, U ibeginSrc, U ibeginDst, U width, U/*RmaValueConvType*/ convtype, U/*RmaForceType*/ frcType, UB* prhs, UB* prhsDst, U frhs, U* pforcedbits, U fisRoot); +extern U VcsReleaseVecVCg(UB* pcode, UB* pvDst, U fullcbits, U ibeginDst, U width, UB* prhsDst, U frhs, U* pforcedbits, U fisRoot); +extern U VcsForceVecWCg(UB* pcode, UB* pval, UB* pvDst, UB* pvCur, U fullcbits, U ibeginSrc, U ibeginDst, U width, U/*RmaValueConvType*/ convtype, U /*RmaForceType*/ frcType, UB* prhs, UB* prhsDst, U frhs, U* pforcedbits, U fisRoot); +extern U VcsReleaseVecWCg(UB* pcode, UB* pvDst, U fullcbits, U ibeginDst, U width, UB* prhsDst, U frhs, U* pforcedbits, U fisRoot); +extern U VcsForceVecECg(UB* pcode, UB* pval, UB* pvDst, UB* pvCur, U fullcbits, U ibeginSrc, U ibeginDst, U width, U /*RmaValueConvType*/ convtype, U /*RmaForceType*/ frcType,UB* prhs, UB* prhsDst, U frhs, U* pforcedbits, U fisRoot); +extern U VcsForceVecACg(UB* pcode, UB* pval, UB* pvDst, UB* pvCur, U fullcbits, U ibeginSrc, U ibeginDst, U width, U /*RmaValueConvType*/ convtype, U /*RmaForceType*/ frcType,UB* prhs, UB* prhsDst, U frhs, U* pforcedbits, U fisRoot); +extern U VcsReleaseVecCg(UB* pcode, UB* pvDst, U ibeginDst, U width, U /*RmaValueType*/ type,U fisRoot, UB* prhsDst, U frhs, U* pforcedbits); +extern U VcsDriveBitsAndDoChangeCheckV(vec32* pvSel, vec32* pvCur, U fullcbits, U* pforcedbits, U isRoot); +extern U VcsDriveBitsAndDoChangeCheckW(vec32* pvSel, vec32* pvCur, U fullcbits, U* pforcedbits, U isRoot); +extern U VcsDriveBitsAndDoChangeCheckE(scalar* pvSel, scalar* pvCur, U fullcbits, U* pforcedbits, U isRoot); +extern void cgvecDebug_Eblk(UB* pcode); +extern U rmaCmpW(vec32* pvalDst, vec32* pvalSrc, U index, U width); +extern void copyVec32ArrMask(vec32* pv1, vec32* pv2, U len, U* mask); +extern void* memcpy(void*, const void*, size_t); +extern int memcmp(const void*, const void*, size_t); +extern void propagateScanOptPathVal(EBLK *peblk); +extern UB* rmaProcessScanSwitches(UB* pcode, scalar val); +extern UB* rmaProcessScanSwitchesV(UB* pcode, vec32 *pval); +extern UB* rmaProcessScanoptDump(UB* pcode, scalar val); +extern UB* rmaProcessScanoptDumpV(UB* pcode, vec32 *pval); +extern UB* rmaProcessScanChainOptSeqPrims(UB* pcode, scalar val); +extern void rmaProcessPvcsCcn(UB* pcode, scalar val); +extern void rmaProcessPvcsCcnE(UB* pcode, scalar* val); +extern void rmaProcessPvcsCcnW(UB* pcode, vec32* val); +extern void rmaProcessPvcsCcnV(UB* pcode, vec32* val); +extern void rmaProcessPvcsCcnCompiledS(UB* pcode, U offset, scalar ibnval); +extern void rmaProcessPvcsCcnCompiledV(UB* pcode, U offset, vec32* pval); +extern void schedResetRecoveryDbs(U cedges, EBLK* peblkFirst); +extern UB* rmaEvalUnaryOpV(UB* pcode, vec32* pval); +extern UB* rmaEvalBinaryOpV(UB* pcode, vec32* pval); +extern UB* rmaEvalBinaryOpVOneFanoutCount(UB* pcode, vec32* pval); +extern UB* rmaEvalBinaryOpVLargeFanoutCount(UB* pcode, vec32* pval); +extern UB* rmaEvalAndOpVOneFanoutCount(UB* pcode, vec32* value); +extern UB* rmaEvalAndOpVLargeFanoutCount(UB* pcode, vec32* value); +extern UB* rmaEvalAndOpV(UB* pcode, vec32* value); +extern UB* rmaEvalOrOpVOneFanoutCount(UB* pcode, vec32* value); +extern UB* rmaEvalOrOpVLargeFanoutCount(UB* pcode, vec32* value); +extern UB* rmaEvalOrOpV(UB* pcode, vec32* value); +extern UB* rmaEvalTernaryOpV(UB* pcode, vec32* pval); +extern UB* rmaEvalUnaryOpW(UB* pcode, vec32* pval); +extern UB* rmaEvalBinaryOpW(UB* pcode, vec32* pval); +extern UB* rmaEvalTernaryOpW(UB* pcode, vec32* pval); +extern UB* rmaEvalUnaryOpE(UB* pcode, scalar* pv); +extern UB* rmaEvalBinaryOpE(UB* pcode, scalar* pv); +extern UB* rmaEvalTernaryOpE(UB* pcode, scalar* pv); +extern UB* rmaEvalTernaryOpS(UB* pcode, scalar val); +extern scalar rmaGetScalarFromWCg(vec32* pval, U index); +extern void rmaSetScalarInWCg(vec32* pval, U index, scalar s); +extern void rmaSetWInW(vec32* dst, vec32* src, U index, U indexSrc, U width); +extern void rmaCountRaptorBits(void* pval, void* pvalPrev, U cbits, U vt); +extern void setHsimFunc(void* ip); +extern void unsetHsimFunc(void* ip); +extern UB* getEvcdStatusByFlagsE(scalar* pscalar, UB* pevcdTBDriverFlags, U cdrivers, UB* table, U cbits); +extern UB* getEvcdStatusByFlagsV(vec32* pvec32, UB* pevcdTBDriverFlags, U cdrivers, UB* table, U cbits); +extern UB* getEvcdStatusByFlagsW(vec32* pvec32, UB* pevcdTBDriverFlags, U cdrivers, UB* table, U cbits); +extern UB* getEvcdStatusByFlagsS(scalar* pscalar, UB* pevcdTBDriverFlags, U cdrivers, UB* table); +extern UB* getSingleDrvEvcdStatusS(UB value, U fTBDriver); +extern UB* getSingleDrvEvcdStatusE(scalar* pscalars, U fTBDriver, U cbits); +extern UB* getSingleDrvEvcdStatusV(scalar* pscalars, U fTBDriver, U cbits); +extern UB* getSingleDrvEvcdStatusW(scalar* pscalars, U fTBDriver, U cbits); +extern UB* getEvcdStatusByDrvEvcdStatus(UB* pdrvevcdStatus, U cdrivers, UB* table, U cbits); +extern void evcdCallback(UP pcode, U cbits); +extern UB* getSavedEvcdStatus(void); +extern void saveEvcdStatus(UB*); +extern void mhdlMarkExport(void*, U); +extern void levelInsertQueue(int); +extern void VcsRciRtl(RP pcode); +extern U fLoopDetectMode; +extern int gFLoopDectCodeEna; +extern U fLoopReportRT; +extern void rtSched0LoopDectDumpProcess(void* e, void* rtn, void* PQ); +extern void pushHsimRtnCtxt(void* pcode); +extern void popHsimRtnCtxt(); +extern EBLK* loopReportInlinedSched0Wrapper(EBLK *peblk); +extern void loopReportSched0Wrapper(EBLK *peblk, unsigned int sfType, unsigned int fTH, struct dummyq_struct* pq); +extern void loopReportSchedSemiLerWrapper(EBLK *peblk, int sfType); +extern void CallGraphPushNodeAndAddToGraph(UP flatNode, UP instNum, U dummy); +extern void CallGraphPopNode(void); +extern RP elabGetIpTpl(U in); +extern U rmaEvalBitBothEdgeW(vec32* pvalCurr, vec32* pvalPrev, U cbits, U* pedges); +extern U rmaEvalBitEdgeQ1W(vec32* pvalCurr, vec32* pvalPrev, U cbits, U* pedges); +extern U rmaEvalBitEdgeQXW(vec32* pvalCurr, vec32* pvalPrev, U cbits, U* pedges); +extern U rmaEvalBitEdgeQ0W(vec32* pvalCurr, vec32* pvalPrev, U cbits, U* pedges); +extern U rmaEval01EdgeW(vec32* pvalCurr, vec32* pvalPrev, U cbits, U* pedges); +extern U rmaEval0XEdgeW(vec32* pvalCurr, vec32* pvalPrev, U cbits, U* pedges); +extern U rmaEval10EdgeW(vec32* pvalCurr, vec32* pvalPrev, U cbits, U* pedges); +extern U rmaEval1XEdgeW(vec32* pvalCurr, vec32* pvalPrev, U cbits, U* pedges); +extern U rmaEvalX1EdgeW(vec32* pvalCurr, vec32* pvalPrev, U cbits, U* pedges); +extern U rmaEvalX0EdgeW(vec32* pvalCurr, vec32* pvalPrev, U cbits, U* pedges); +extern U rmaEvalBitPosEdgeE(scalar* pvalCurr, scalar* pvalPrev, U cbits, U* pedges); +extern U rmaEvalBitNegEdgeE(scalar* pvalCurr, scalar* pvalPrev, U cbits, U* pedges); +extern U rmaEvalBitBothEdgeE(scalar* pvalCurr, scalar* pvalPrev, U cbits, U* pedges); +extern U rmaEvalBitEdgeQ1E(scalar* pvalCurr, scalar* pvalPrev, U cbits, U* pedges); +extern U rmaEvalBitEdgeQ0E(scalar* pvalCurr, scalar* pvalPrev, U cbits, U* pedges); +extern U rmaEvalBitChangeE(scalar* pvalCurr, scalar* pvalPrev, U cbits, U* pedges); +extern void rmaScheduleNbaGate(RP pcode, scalar val); +extern void rmaEvalRtlEdgeLoads(RmaRtlEdgeBlockHdr *phdr, US clkEdge, scalar clkVal, scalar prevClkVal, scalar val4, scalar prevval4, scalar master4val); +extern void rmaEvaluateDynamicGateLoadsCg(RP p, scalar s); +extern void rmaEvaluateFusedWithDynamicGateLoadsCg(RP p, scalar s); +extern void rmaScheduleGatedClockEdgeLoadNew(UB* p, US* ea, U flags, UB* plist, UB* pprevlist, scalar v); +extern void rmaScheduleGatedClockEdgeLoad(UB* p, US* ea, U flags, UB* plist, UB* pprevlist, scalar v); +extern void rmaRemoveNonEdgeLoads(UB* pcode); +extern void rmaRecordEvents(HsimNodeRecord *pnr); +extern void handlePCBs(UB* p, U i); +extern void markMasterClkOvaLists(U fdbs, RP p); +extern void rmaChildClockPropAfterWrite(UB* p); +extern void rmaSchedChildClockPropAfterWrite(UB* p, UB* pmasterList, UB val); +extern void HDLCosimProcessDUTInputChange(U inputId, void* val); +extern void rmaChangeListForMovedGates(UB clkVal, UB f10Edge, UB* subMasterVal, UB* plist, RP* p, U count); +extern void rmaEvalSeqPrimLoadsByteArray(UB* pcode, UB val, UB prevval4); +extern void rmaEvalSeqPrimLoadsByteArrayX(UB* pcode, UB val, UB prevval4); +extern void vcsRmaEvalSeqPrimLoadsByteArraySCT(UB* pcode, UB val, UB prevval4, U c); +extern void vcsAbortForBadEBlk(void); +extern scalar edgeChangeLookUp[4][4]; +extern void Wsvvar_sched_virt_intf_eval(RP* ptr); +extern void vcs_hwcosim_drive_dut_scalar(uint id, char val); +extern void vcs_hwcosim_drive_dut_vector_4state(uint id, vec32* val); +extern U vcs_rmaGetClkValForSeqUdpLayoutOnClkOpt(UB* poutput); +extern U rmaIsS2State(scalar s); +extern U rmaIsV2State(vec32* pval, U cbits); +extern U rmaIsW2State(vec32* pval, U cbits); +extern U rmaIsE2State(scalar* pval, U cbits); +extern void rmaUpdateRecordFor2State(HsimNodeRecord* record, U f2state); +typedef void (*FuncPtr)(); +static inline U asm_bsf (U in) +{ +#if defined(linux) + U out; +#if !defined(__aarch64__) + asm ("movl %1, %%eax; bsf %%eax, %%eax; movl %%eax, %0;" + :"=r"(out) + :"r"(in) + :"%eax" + ); +#else + out = ffs(in) - 1; +#endif + return out; +#else + return 0; +#endif +} + + +#ifdef __cplusplus +extern "C" { +#endif +void hs_0_M_6_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_6_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_6_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_9_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_9_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_9_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_9_2__simv_daidir (UB * pcode); +void hs_0_M_9_5__simv_daidir (UB * pcode, UB val); +void hs_0_M_9_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_10_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_10_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_10_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_10_2__simv_daidir (UB * pcode); +void hs_0_M_10_5__simv_daidir (UB * pcode, UB val); +void hs_0_M_10_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_15_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_15_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_15_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_15_2__simv_daidir (UB * pcode); +void hs_0_M_15_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_16_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_16_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_16_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_29_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_29_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_29_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_29_2__simv_daidir (UB * pcode); +void hs_0_M_29_5__simv_daidir (UB * pcode, UB val); +void hs_0_M_29_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_30_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_30_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_30_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_30_2__simv_daidir (UB * pcode); +void hs_0_M_30_5__simv_daidir (UB * pcode, UB val); +void hs_0_M_30_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_31_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_31_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_31_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_31_2__simv_daidir (UB * pcode); +void hs_0_M_31_5__simv_daidir (UB * pcode, UB val); +void hs_0_M_31_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_34_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_34_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_34_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_34_2__simv_daidir (UB * pcode); +void hs_0_M_34_5__simv_daidir (UB * pcode, UB val); +void hs_0_M_34_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_35_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_35_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_35_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_35_2__simv_daidir (UB * pcode); +void hs_0_M_35_5__simv_daidir (UB * pcode, UB val); +void hs_0_M_35_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_36_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_37_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_38_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_38_5__simv_daidir (UB * pcode, UB val); +void hs_0_M_39_21__simv_daidir (UB * pcode, vec32 * I1006, U I915); +void hs_0_M_39_0__simv_daidir (UB * pcode, vec32 * I1006, U I915); +void hs_0_M_39_5__simv_daidir (UB * pcode, U I915); +void hs_0_M_40_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_41_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_41_5__simv_daidir (UB * pcode, UB val); +void hs_0_M_42_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_42_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_42_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_42_2__simv_daidir (UB * pcode); +void hs_0_M_42_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_43_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_43_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_43_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_43_2__simv_daidir (UB * pcode); +void hs_0_M_43_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_44_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_44_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_44_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_44_2__simv_daidir (UB * pcode); +void hs_0_M_44_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_45_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_45_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_45_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_45_2__simv_daidir (UB * pcode); +void hs_0_M_45_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_46_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_46_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_46_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_46_2__simv_daidir (UB * pcode); +void hs_0_M_46_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_47_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_47_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_47_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_47_2__simv_daidir (UB * pcode); +void hs_0_M_47_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_48_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_48_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_48_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_48_2__simv_daidir (UB * pcode); +void hs_0_M_48_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_49_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_49_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_49_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_49_2__simv_daidir (UB * pcode); +void hs_0_M_49_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_50_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_50_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_50_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_50_2__simv_daidir (UB * pcode); +void hs_0_M_50_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_65_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_66_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_66_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_66_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_66_2__simv_daidir (UB * pcode); +void hs_0_M_66_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_67_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_68_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_68_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_68_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_68_2__simv_daidir (UB * pcode); +void hs_0_M_68_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_69_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_69_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_69_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_69_2__simv_daidir (UB * pcode); +void hs_0_M_69_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_70_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_70_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_70_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_70_2__simv_daidir (UB * pcode); +void hs_0_M_70_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_71_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_71_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_71_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_71_2__simv_daidir (UB * pcode); +void hs_0_M_71_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_72_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_72_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_72_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_72_2__simv_daidir (UB * pcode); +void hs_0_M_72_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_73_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_73_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_73_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_73_2__simv_daidir (UB * pcode); +void hs_0_M_73_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_74_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_75_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_75_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_75_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_75_2__simv_daidir (UB * pcode); +void hs_0_M_75_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_77_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_77_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_77_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_77_2__simv_daidir (UB * pcode); +void hs_0_M_77_5__simv_daidir (UB * pcode, UB val); +void hs_0_M_77_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_78_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_78_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_78_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_78_2__simv_daidir (UB * pcode); +void hs_0_M_78_5__simv_daidir (UB * pcode, UB val); +void hs_0_M_78_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_80_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_80_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_80_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_80_2__simv_daidir (UB * pcode); +void hs_0_M_80_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_81_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_81_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_81_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_81_2__simv_daidir (UB * pcode); +void hs_0_M_81_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_83_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_83_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_83_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_83_2__simv_daidir (UB * pcode); +void hs_0_M_83_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_84_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_84_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_84_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_84_2__simv_daidir (UB * pcode); +void hs_0_M_84_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_85_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_85_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_85_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_85_2__simv_daidir (UB * pcode); +void hs_0_M_85_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_86_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_86_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_86_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_86_2__simv_daidir (UB * pcode); +void hs_0_M_86_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_87_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_87_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_87_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_87_2__simv_daidir (UB * pcode); +void hs_0_M_87_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_91_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_91_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_91_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_91_2__simv_daidir (UB * pcode); +void hs_0_M_91_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_100_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_100_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_100_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_101_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_101_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_101_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_101_2__simv_daidir (UB * pcode); +void hs_0_M_101_5__simv_daidir (UB * pcode, UB val); +void hs_0_M_101_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_104_0__simv_daidir (UB * pcode, vec32 * I1006, U I915); +void hs_0_M_105_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_106_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_109_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_109_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_109_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_109_2__simv_daidir (UB * pcode); +void hs_0_M_109_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_110_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_110_5__simv_daidir (UB * pcode, UB val); +void hs_0_M_111_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_111_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_111_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_111_2__simv_daidir (UB * pcode); +void hs_0_M_111_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_115_0__simv_daidir (UB * pcode, vec32 * I1006, U I915); +void hs_0_M_116_21__simv_daidir (UB * pcode, vec32 * I1006, U I915); +void hs_0_M_116_0__simv_daidir (UB * pcode, vec32 * I1006, U I915); +void hs_0_M_116_5__simv_daidir (UB * pcode, U I915); +void hs_0_M_117_21__simv_daidir (UB * pcode, vec32 * I1006, U I915); +void hs_0_M_117_0__simv_daidir (UB * pcode, vec32 * I1006, U I915); +void hs_0_M_117_5__simv_daidir (UB * pcode, U I915); +void hs_0_M_119_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_119_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_119_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_120_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_120_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_120_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_120_2__simv_daidir (UB * pcode); +void hs_0_M_120_5__simv_daidir (UB * pcode, UB val); +void hs_0_M_120_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_121_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_121_5__simv_daidir (UB * pcode, UB val); +void hs_0_M_122_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_122_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_122_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_122_2__simv_daidir (UB * pcode); +void hs_0_M_122_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_123_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_127_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_127_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_127_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_131_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_131_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_131_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_131_2__simv_daidir (UB * pcode); +void hs_0_M_131_5__simv_daidir (UB * pcode, UB val); +void hs_0_M_131_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_132_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_133_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_134_21__simv_daidir (UB * pcode, vec32 * I1006, U I915); +void hs_0_M_134_0__simv_daidir (UB * pcode, vec32 * I1006, U I915); +void hs_0_M_134_6__simv_daidir (UB * pcode, scalar val, U I890); +void hs_0_M_134_7__simv_daidir (UB * pcode, vec32 * I1363, U I890, U I1373); +void hs_0_M_134_10__simv_daidir (UB * pcode, vec32 * I1006); +void hs_0_M_135_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_136_21__simv_daidir (UB * pcode, scalar val); +void hs_0_M_136_0__simv_daidir (UB * pcode, scalar val); +void hs_0_M_136_1__simv_daidir (UB * pcode, scalar val, U I677, scalar * I1303, U did); +void hs_0_M_136_2__simv_daidir (UB * pcode); +void hs_0_M_136_11__simv_daidir (UB * pcode, scalar val); +void hs_0_M_137_21__simv_daidir (UB * pcode, vec32 * I1006, U I915); +void hs_0_M_137_0__simv_daidir (UB * pcode, vec32 * I1006, U I915); +void hs_0_M_137_6__simv_daidir (UB * pcode, scalar val, U I890); +void hs_0_M_137_7__simv_daidir (UB * pcode, vec32 * I1363, U I890, U I1373); +void hs_0_M_137_10__simv_daidir (UB * pcode, vec32 * I1006); +void hsG_0__0 (struct dummyq_struct * I1289, EBLK * I1283, U I685); +#ifdef __cplusplus +} +#endif + +#ifdef __cplusplus + } +#endif +#endif /*__DO_RMAHDR_*/ + diff --git a/tb/digital_top/csrc/rmapats.m b/tb/digital_top/csrc/rmapats.m new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/csrc/rmapats.o b/tb/digital_top/csrc/rmapats.o new file mode 100644 index 0000000..f7e34a8 Binary files /dev/null and b/tb/digital_top/csrc/rmapats.o differ diff --git a/tb/digital_top/csrc/rmapats_mop.o b/tb/digital_top/csrc/rmapats_mop.o new file mode 100644 index 0000000..db2f52c Binary files /dev/null and b/tb/digital_top/csrc/rmapats_mop.o differ diff --git a/tb/digital_top/csrc/rmar.c b/tb/digital_top/csrc/rmar.c new file mode 100644 index 0000000..21b81fa --- /dev/null +++ b/tb/digital_top/csrc/rmar.c @@ -0,0 +1,13 @@ +#include +#include +#include "rmar0.h" + +// stubs for Hil functions +#ifdef __cplusplus +extern "C" { +#endif +void __Hil__Static_Init_Func__(void) {} +#ifdef __cplusplus +} +#endif + diff --git a/tb/digital_top/csrc/rmar.h b/tb/digital_top/csrc/rmar.h new file mode 100644 index 0000000..77865aa --- /dev/null +++ b/tb/digital_top/csrc/rmar.h @@ -0,0 +1,18 @@ +#ifndef _RMAR1_H_ +#define _RMAR1_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef __DO_RMAHDR_ +#include "rmar0.h" +#endif /*__DO_RMAHDR_*/ + +extern UP rmaFunctionRtlArray[]; + +#ifdef __cplusplus +} +#endif +#endif + diff --git a/tb/digital_top/csrc/rmar.o b/tb/digital_top/csrc/rmar.o new file mode 100644 index 0000000..1989370 Binary files /dev/null and b/tb/digital_top/csrc/rmar.o differ diff --git a/tb/digital_top/csrc/rmar0.h b/tb/digital_top/csrc/rmar0.h new file mode 100644 index 0000000..48e8516 --- /dev/null +++ b/tb/digital_top/csrc/rmar0.h @@ -0,0 +1,13 @@ +#ifndef _RMAR0_H_ +#define _RMAR0_H_ + +#ifdef __cplusplus +extern "C" { +#endif + + +#ifdef __cplusplus +} +#endif +#endif + diff --git a/tb/digital_top/csrc/rmar_llvm_0_0.o b/tb/digital_top/csrc/rmar_llvm_0_0.o new file mode 100644 index 0000000..3663b36 Binary files /dev/null and b/tb/digital_top/csrc/rmar_llvm_0_0.o differ diff --git a/tb/digital_top/csrc/rmar_llvm_0_1.o b/tb/digital_top/csrc/rmar_llvm_0_1.o new file mode 100644 index 0000000..0119f49 Binary files /dev/null and b/tb/digital_top/csrc/rmar_llvm_0_1.o differ diff --git a/tb/digital_top/csrc/rmar_nd.o b/tb/digital_top/csrc/rmar_nd.o new file mode 100644 index 0000000..99927ba Binary files /dev/null and b/tb/digital_top/csrc/rmar_nd.o differ diff --git a/tb/digital_top/dbg_mod_data.dat b/tb/digital_top/dbg_mod_data.dat new file mode 100644 index 0000000..a203474 --- /dev/null +++ b/tb/digital_top/dbg_mod_data.dat @@ -0,0 +1,36435 @@ +00000000 +f030f996 +15a713a6 +edd4e2a1 +0ce920c4 +f731dde8 +028e2272 +05f9e361 +f6f90e7b +00000000 +ef48fa91 +0e380a56 +0e39f5ab +fa92ef48 +ee6cffff +fa9110b8 +0e380a56 +0e39f5ab +fa92ef48 +ee6cffff +fa9110b8 +0e380a56 +0e39f5ab +fa92ef48 +ee6cffff +fa9110b8 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b8 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +00000000 +01a0012e +fec6fc38 +fe310592 +0628fb87 +f6cbffff +0897063f +fc58f4be +fc070c37 +0b0af7fc +f1c4ffff +0bd9089d +fb66f1d4 +fb5b0e48 +0c2af72b +f107ffff +0c0808bf +fb71f1f5 +fb770df3 +0bd1f76c +f16cffff +0bd00896 +fb79f20c +fb6f0e0b +0c09f742 +f107ffff +0c2908d7 +fb5df1b8 +fb640e2b +0bdaf765 +f1c4ffff +0b090805 +fc09f3c9 +fc570b41 +0898f9c2 +f6cbffff +06280479 +fe31fa6e +fec503c8 +01a0fed2 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +00000000 +fdfe0000 +03370257 +fe31fa6e +fda6073d +0773fa97 +f561ffff +099306f6 +fc09f3c9 +fbc80cf9 +0b85f7a3 +f15affff +0c0d08c3 +fb5df1b8 +fb5a0e4b +0c1ef734 +f120ffff +0bf208af +fb79f20c +fb7c0de3 +0bccf76f +f166ffff +0bdd08a0 +fb71f1f5 +fb660e25 +0c1ef734 +f0f8ffff +0c2508d4 +fb66f1d4 +fb780dee +0b85f7a3 +f25cffff +0a63078d +fc59f4be +fcb70a1a +0773fa97 +f864ffff +04bc0371 +fec6fc38 +ff6101e9 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +1090fbe5 +e2eefcd4 +1ff80d15 +e24ded15 +1b2a1668 +e9b0e5a1 +0bfe1aac +fecbeefa +00000000 +10b8fa92 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac +fa92ef48 +ee6cffff +fa9110b7 +0e380a56 +0e39f5ac diff --git a/tb/digital_top/dbg_mod_data_c.dat b/tb/digital_top/dbg_mod_data_c.dat new file mode 100644 index 0000000..3cefb58 --- /dev/null +++ b/tb/digital_top/dbg_mod_data_c.dat @@ -0,0 +1,16 @@ +000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f6f90e7b +0000000000000000000000000000000000000000000000000000000000000000fa92ef480e39f5ab0e380a56fa9110b8ee6cfffffa92ef480000000000000000 +00000000000000000000000000000000000000000000000000000000000000000e380a56fa9110b8ee6cfffffa92ef480e39f5ac0e380a56fa9110b8ee6cffff +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ee6cfffffa92ef480e39f5ac +0000000000000000000000000000000000000000000000000000000000000000fb66f1d40bd9089df1c4ffff0b0af7fcfc070c37000000000000000000000000 +0000000000000000000000000000000000000000000000000000000000000000f16cffff0bd1f76cfb770df3fb71f1f50c0808bff107ffff0c2af72bfb5b0e48 +0000000000000000000000000000000000000000000000000000000000000000fb640e2bfb5df1b80c2908d7f107ffff0c09f742fb6f0e0bfb79f20c0bd00896 +000000000000000000000000000000000000000000000000000000000000000006280479f6cbffff0898f9c2fc570b41fc09f3c90b090805f1c4ffff0bdaf765 +0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001a0fed2fec503c8fe31fa6e +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 diff --git a/tb/digital_top/files.f b/tb/digital_top/files.f new file mode 100644 index 0000000..bf2c552 --- /dev/null +++ b/tb/digital_top/files.f @@ -0,0 +1,95 @@ +../../rtl/memory/sram_if.sv +../../rtl/awg/awg_ctrl.v +../../rtl/awg/awg_top.sv +../../rtl/awg/codeword_decode.v +../../rtl/awg/ctrl_regfile.v +../../rtl/awg/param_lut.sv +../../rtl/awg/modout_mux.v +../../rtl/clk/intpll_regfile.v +../../rtl/comm/sirv_gnrl_dffs.v +../../rtl/comm/sirv_gnrl_xchecker.v +../../rtl/dac_regfile/dac_regfile.v +../../rtl/debug/debug_sample.sv +../../rtl/debug/debug_top.sv +../../rtl/define/chip_define.v +../../rtl/define/chip_undefine.v +../../rtl/memory/dpram.v +../../rtl/memory/dpram_model.v +../../rtl/memory/sram_dmux.sv +../../rtl/memory/tsdn28hpcpuhdb128x128m4mw_170a_ffg0p99v0c.v +../../rtl/memory/tsdn28hpcpuhdb4096x32m4mw_170a_ffg0p99v0c.v +../../rtl/memory/tsdn28hpcpuhdb4096x32m4mwr_170a_ffg0p99v0c.v +../../rtl/memory/tsdn28hpcpuhdb64x32m4mw_170a_ffg0p99v0c.v +../../rtl/memory/tsmc_dpram.v +../../rtl/modem/ampmod.v +../../rtl/modem/baisset.v +../../rtl/modem/freqmod.v +../../rtl/nco/coef_c.v +../../rtl/nco/coef_s.v +../../rtl/nco/cos_op.v +../../rtl/nco/nco.v +../../rtl/nco/nco_ch1.v +../../rtl/nco/p_nco.v +../../rtl/nco/p_nco_ch1.v +../../rtl/nco/ph2amp.v +../../rtl/nco/pipe_acc_48bit.v +../../rtl/nco/pipe_add_48bit.v +../../rtl/nco/sin_op.v +../../rtl/perips/DW03_updn_ctr.v +../../rtl/perips/mcu_regfile.sv +../../rtl/perips/qbmcu_busdecoder.v +../../rtl/qubitmcu/qbmcu.v +../../rtl/qubitmcu/qbmcu_datalock.v +../../rtl/qubitmcu/qbmcu_decode.v +../../rtl/qubitmcu/qbmcu_defines.v +../../rtl/qubitmcu/qbmcu_exu.v +../../rtl/qubitmcu/qbmcu_exu_alu.v +../../rtl/qubitmcu/qbmcu_exu_bjp.v +../../rtl/qubitmcu/qbmcu_exu_dpath.v +../../rtl/qubitmcu/qbmcu_exu_ext.v +../../rtl/qubitmcu/qbmcu_exu_lsuagu.v +../../rtl/qubitmcu/qbmcu_fsm.v +../../rtl/qubitmcu/qbmcu_ifu.v +../../rtl/qubitmcu/qbmcu_regfile.v +../../rtl/qubitmcu/qbmcu_undefines.v +../../rtl/qubitmcu/qbmcu_wbck.v +../../rtl/rstgen/rst_gen_unit.v +../../rtl/rstgen/rst_sync.v +../../rtl/spi/spi_bus_decoder.sv +../../rtl/spi/spi_pll.v +../../rtl/spi/spi_slave.v +../../rtl/spi/spi_sys.v +../../rtl/sync/sync_buf.sv +../../rtl/system_regfile/system_regfile.v +../../rtl/top/channel_top.sv +../../rtl/top/digital_top.sv +../../rtl/xy_dsp/dacif/dacif.v +../../rtl/xy_dsp/dsp_top/xy_dsp.v +../../rtl/xy_dsp/duc/duc_hb1_pipe_shift.v +../../rtl/xy_dsp/duc/duc_hb1_top.v +../../rtl/xy_dsp/duc/duc_hb2_pipe_shift.v +../../rtl/xy_dsp/duc/duc_hb2_top_s.v +../../rtl/xy_dsp/duc/duc_hb3_pipe_shift.v +../../rtl/xy_dsp/duc/duc_hb3_top_s2.v +../../rtl/xy_dsp/duc/duc_hb4_pipe_shift.v +../../rtl/xy_dsp/duc/duc_hb4_top_s3.v +../../rtl/xy_dsp/duc/duc4.v +../../rtl/xy_dsp/qam/qam_top.v +../../rtl/xy_dsp/qam/ssb.v +../../rtl/z_dsp/diff.v +../../rtl/z_dsp/IIR_Filter.v +../../rtl/z_dsp/lsdacif.v +../../rtl/z_dsp/MeanIntp.v +../../rtl/z_dsp/MeanIntp_s1.v +../../rtl/z_dsp/MeanIntp2.v +../../rtl/z_dsp/MeanIntp4_top.v +../../rtl/z_dsp/mult_C.v +../../rtl/z_dsp/TailCorr_top.v +../../rtl/z_dsp/z_data_mux.v +../../rtl/z_dsp/z_dsp.v +../../sim/digital_top/TB.sv +../../sim/digital_top/DW_mult_pipe.v +../../sim/digital_top/DW01_addsub.v +../../sim/digital_top/DW02_mult.v +../../sim/digital_top/clk_gen.v +../../sim/digital_top/spi_if.sv diff --git a/tb/digital_top/novas.conf b/tb/digital_top/novas.conf new file mode 100644 index 0000000..9f6292b --- /dev/null +++ b/tb/digital_top/novas.conf @@ -0,0 +1,590 @@ +[qBaseWindowStateGroup] +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\ProductVersion=201809 +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\Layout="@ByteArray(\0\0\0\xff\0\0\0\0\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x2\xf2\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x3P\0\0\0\x89\0\xff\xff\xff\xfa\0\0\0\x1\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\x2\xc7\0\0\x1\xa8\0\0\0k\0\0\0k\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\x1\0\0\x3V\0\0\x6\xaa\0\0\0k\0\xff\xff\xff\0\0\0\x3\0\0\n\0\0\0\x1\xd8\xfc\x1\0\0\0\x1\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\x1\0\0\0\0\0\0\n\0\0\0\0\xa0\0\xff\xff\xff\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x3\x16\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x3\x1e\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\x1f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x43\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3g\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\isNestedWindow=0 +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\size=@Size(2560 1337) +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\geometry_x=-1 +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\geometry_y=27 +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\geometry_width=2560 +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\geometry_height=1337 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\ProductVersion=201809 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\Layout="@ByteArray(\0\0\0\xff\0\0\0\0\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x3<\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x2\x8e\0\0\0\x89\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\xe9\0\0\0\xc6\0\0\0k\0\0\0k\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\x1\0\0\x2\x94\0\0\al\0\0\0k\0\xff\xff\xff\0\0\0\x3\0\0\n\0\0\0\x1\xa9\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\n\0\0\0\x2,\0\xff\xff\xff\xfa\0\0\0\x2\x1\0\0\0\x3\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\x1\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\x1-\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x33\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x34\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\isNestedWindow=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\size=@Size(2560 1337) +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\geometry_x=-1 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\geometry_y=27 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\geometry_width=2560 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\geometry_height=1337 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_OneSearch\isNestedWindow=1 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_OneSearch\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_OneSearch\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nWave_2\isNestedWindow=1 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nWave_2\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nWave_2\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nWave_2\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nWave_2\dockIsFloating=false +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qDockerWindow_qDockContentType\Verdi=1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qDockerWindow_qDockContentType\hdlHier=1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qDockerWindow_qDockContentType\hdlSrc=1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qDockerWindow_qDockContentType\messageWindow=1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qDockerWindow_qDockContentType\svtbHier=1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qDockerWindow_qDockContentType\OneSearch=1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qDockerWindowMgr_saveDockerChildList\Verdi_1=7 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qDockerWindowMgr_saveDockerChildList\Verdi_1_0=widgetDock_hdlHier_1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qDockerWindowMgr_saveDockerChildList\Verdi_1_1=widgetDock_messageWindow_1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qDockerWindowMgr_saveDockerChildList\Verdi_1_2=widgetDock_hdlSrc_1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qDockerWindowMgr_saveDockerChildList\Verdi_1_3=widgetDock_signalList_1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qDockerWindowMgr_saveDockerChildList\Verdi_1_4=widgetDock_svtbHier_1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qDockerWindowMgr_saveDockerChildList\Verdi_1_5=windowDock_OneSearch_1 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\widgetDock_hdlHier_1\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\widgetDock_hdlHier_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\widgetDock_hdlHier_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\widgetDock_hdlHier_1\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\widgetDock_messageWindow_1\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\widgetDock_messageWindow_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\widgetDock_messageWindow_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\widgetDock_messageWindow_1\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\widgetDock_hdlSrc_1\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\widgetDock_hdlSrc_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\widgetDock_hdlSrc_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\widgetDock_hdlSrc_1\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\widgetDock_signalList_1\isVisible=false +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\widgetDock_svtbHier_1\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\widgetDock_svtbHier_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\widgetDock_svtbHier_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\widgetDock_svtbHier_1\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\windowDock_OneSearch_1\isNestedWindow=1 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\windowDock_OneSearch_1\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\windowDock_OneSearch_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\windowDock_OneSearch_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\windowDock_OneSearch_1\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\windowDock_nWave_1\isNestedWindow=1 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\windowDock_nWave_1\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\windowDock_nWave_1\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\windowDock_nWave_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\windowDock_nWave_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\windowDock_nWave_1\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\ProductVersion=201809 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\Layout="@ByteArray(\0\0\0\xff\0\0\0\0\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x2\xcb\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x2\x8d\0\0\0\x89\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x2\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0h\0\x64\0l\0H\0i\0\x65\0r\0_\0\x31\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0*\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0s\0v\0t\0\x62\0H\0i\0\x65\0r\0_\0\x31\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0s\0i\0g\0n\0\x61\0l\0L\0i\0s\0t\0_\0\x31\0\0\0\0\xe9\0\0\0\xc6\0\0\0k\0\0\0k\xfb\0\0\0&\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0h\0\x64\0l\0S\0r\0\x63\0_\0\x31\x1\0\0\x2\x93\0\0\am\0\0\0k\0\xff\xff\xff\0\0\0\x3\0\0\n\0\0\0\x2\x1a\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\n\0\0\0\x2,\0\xff\xff\xff\xfa\0\0\0\x2\x1\0\0\0\x3\xfb\0\0\0\x34\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0m\0\x65\0s\0s\0\x61\0g\0\x65\0W\0i\0n\0\x64\0o\0w\0_\0\x31\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0,\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\0_\0\x31\x1\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x31\x1\0\0\0\0\xff\xff\xff\xff\0\0\x1-\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x33\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x34\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\isNestedWindow=0 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\size=@Size(2560 1337) +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\geometry_x=-1 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\geometry_y=27 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\geometry_width=2560 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\geometry_height=1337 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nWave_2\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nMemory_3\isNestedWindow=1 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nMemory_3\isVisible=false +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nMemory_3\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nMemory_3\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nMemory_3\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nMemory_4\isNestedWindow=1 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nMemory_4\isVisible=false +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nMemory_4\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nMemory_4\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nMemory_4\dockIsFloating=false +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qDockerWindow_qDockContentType\nWave=1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qDockerWindowMgr_saveDockerChildList\Verdi_1_6=windowDock_nWave_1 +Verdi_1\qBaseWindowNextStateGroup\0\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\0\ProductVersion=201809 +Verdi_1\qBaseWindowNextStateGroup\0\Layout="@ByteArray(\0\0\0\xff\0\0\0\0\xfd\0\0\0\x2\0\0\0\x2\0\0\x3U\0\0\x1L\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\0\xd9\0\0\0\x89\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\xe9\0\0\0\xc6\0\0\0k\0\0\0k\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\x1\0\0\0\xdf\0\0\x2v\0\0\0k\0\xff\xff\xff\0\0\0\x3\0\0\x3U\0\0\0\x9c\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x3U\0\0\0\xa0\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x3\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x33\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x34\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\0\0\x3U\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowNextStateGroup\0\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\0\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\0\size=@Size(853 572) +Verdi_1\qBaseWindowNextStateGroup\0\geometry_x=-1 +Verdi_1\qBaseWindowNextStateGroup\0\geometry_y=27 +Verdi_1\qBaseWindowNextStateGroup\0\geometry_width=853 +Verdi_1\qBaseWindowNextStateGroup\0\geometry_height=572 +Verdi_1\qBaseWindowNextStateGroup\1\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_OneSearch\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_OneSearch\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_OneSearch\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\1\ProductVersion=201809 +Verdi_1\qBaseWindowNextStateGroup\1\Layout="@ByteArray(\0\0\0\xff\0\0\0\x1\xfd\0\0\0\x2\0\0\0\x2\0\0\x3U\0\0\x1\x33\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\0\xd9\0\0\0\x89\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\xe9\0\0\0\xc6\0\0\0k\0\0\0k\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\x1\0\0\0\xdf\0\0\x2v\0\0\0k\0\xff\xff\xff\0\0\0\x3\0\0\x3U\0\0\0\xb5\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x3U\0\0\x2,\0\xff\xff\xff\xfa\0\0\0\x2\x1\0\0\0\x3\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\x1\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x33\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x34\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\0\0\x3U\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowNextStateGroup\1\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\1\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\1\size=@Size(853 572) +Verdi_1\qBaseWindowNextStateGroup\1\geometry_x=-1 +Verdi_1\qBaseWindowNextStateGroup\1\geometry_y=27 +Verdi_1\qBaseWindowNextStateGroup\1\geometry_width=853 +Verdi_1\qBaseWindowNextStateGroup\1\geometry_height=572 +Verdi_1\qBaseWindowNextStateGroup\2\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\windowDock_OneSearch\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\windowDock_OneSearch\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\2\ProductVersion=201809 +Verdi_1\qBaseWindowNextStateGroup\2\Layout="@ByteArray(\0\0\0\xff\0\0\0\x2\xfd\0\0\0\x2\0\0\0\x2\0\0\x3U\0\0\x1\x33\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\0\xd9\0\0\0\x89\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\xe9\0\0\0\xc6\0\0\0k\0\0\0k\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\x1\0\0\0\xdf\0\0\x2v\0\0\0k\0\xff\xff\xff\0\0\0\x3\0\0\x3U\0\0\0\xb5\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x3U\0\0\0\xa0\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x3\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\0\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\0\0k\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x33\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x34\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\0\0\x3U\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowNextStateGroup\2\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\2\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\2\size=@Size(853 572) +Verdi_1\qBaseWindowNextStateGroup\2\geometry_x=-1 +Verdi_1\qBaseWindowNextStateGroup\2\geometry_y=27 +Verdi_1\qBaseWindowNextStateGroup\2\geometry_width=853 +Verdi_1\qBaseWindowNextStateGroup\2\geometry_height=572 +Verdi_1\qBaseWindowNextStateGroup\3\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\windowDock_OneSearch\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\windowDock_OneSearch\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\windowDock_OneSearch\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\3\ProductVersion=201809 +Verdi_1\qBaseWindowNextStateGroup\3\Layout="@ByteArray(\0\0\0\xff\0\0\0\x3\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x4\x30\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x2\x8e\0\0\0\x89\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\xe9\0\0\0\xc6\0\0\0k\0\0\0k\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\x1\0\0\x2\x94\0\0\al\0\0\0k\0\xff\xff\xff\0\0\0\x3\0\0\n\0\0\0\0\xb5\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\n\0\0\0\x2,\0\xff\xff\xff\xfa\0\0\0\x2\x1\0\0\0\x3\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\x1\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x33\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x34\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowNextStateGroup\3\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\3\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\3\size=@Size(2560 1337) +Verdi_1\qBaseWindowNextStateGroup\3\geometry_x=-1 +Verdi_1\qBaseWindowNextStateGroup\3\geometry_y=27 +Verdi_1\qBaseWindowNextStateGroup\3\geometry_width=2560 +Verdi_1\qBaseWindowNextStateGroup\3\geometry_height=1337 +Verdi_1\qBaseWindowNextStateGroup\4\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\windowDock_OneSearch\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\windowDock_OneSearch\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\windowDock_OneSearch\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\4\ProductVersion=201809 +Verdi_1\qBaseWindowNextStateGroup\4\Layout="@ByteArray(\0\0\0\xff\0\0\0\x4\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x4\x30\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x2\x8e\0\0\0\x89\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\xe9\0\0\0\xc6\0\0\0k\0\0\0k\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\x1\0\0\x2\x94\0\0\al\0\0\0k\0\xff\xff\xff\0\0\0\x3\0\0\n\0\0\0\0\xb5\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\n\0\0\0\x2,\0\xff\xff\xff\xfa\0\0\0\x2\x1\0\0\0\x3\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\x1\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x33\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x34\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowNextStateGroup\4\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\4\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\4\size=@Size(2560 1337) +Verdi_1\qBaseWindowNextStateGroup\4\geometry_x=-1 +Verdi_1\qBaseWindowNextStateGroup\4\geometry_y=27 +Verdi_1\qBaseWindowNextStateGroup\4\geometry_width=2560 +Verdi_1\qBaseWindowNextStateGroup\4\geometry_height=1337 +Verdi_1\qBaseWindowNextStateGroup\5\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_OneSearch\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_OneSearch\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_OneSearch\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nWave_2\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nWave_2\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nWave_2\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nWave_2\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nWave_2\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\5\ProductVersion=201809 +Verdi_1\qBaseWindowNextStateGroup\5\Layout="@ByteArray(\0\0\0\xff\0\0\0\x5\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x4/\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x2\x8e\0\0\0\x89\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\xe9\0\0\0\xc6\0\0\0k\0\0\0k\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\x1\0\0\x2\x94\0\0\al\0\0\0k\0\xff\xff\xff\0\0\0\x3\0\0\n\0\0\0\0\xb6\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\n\0\0\0\x2,\0\xff\xff\xff\xfa\0\0\0\x2\x1\0\0\0\x3\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\x1\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\x1\xd5\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x33\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x34\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowNextStateGroup\5\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\5\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\5\size=@Size(2560 1337) +Verdi_1\qBaseWindowNextStateGroup\5\geometry_x=-1 +Verdi_1\qBaseWindowNextStateGroup\5\geometry_y=27 +Verdi_1\qBaseWindowNextStateGroup\5\geometry_width=2560 +Verdi_1\qBaseWindowNextStateGroup\5\geometry_height=1337 +Verdi_1\qBaseWindowNextStateGroup\6\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\windowDock_OneSearch\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\windowDock_OneSearch\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\windowDock_nWave_2\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\windowDock_nWave_2\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\windowDock_nWave_2\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\windowDock_nWave_2\qBaseWindowBeMax=1 +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\windowDock_nWave_2\qBaseWindowBeFix=1 +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\windowDock_nWave_2\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\6\ProductVersion=201809 +Verdi_1\qBaseWindowNextStateGroup\6\Layout="@ByteArray(\0\0\0\xff\0\0\0\x6\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x3<\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x2\x8e\0\0\0\0\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\xe9\0\0\0\xc6\0\0\0k\0\0\0k\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\0\0\0\x2\x94\0\0\al\0\0\0k\0\xff\xff\xff\0\0\0\x3\0\0\n\0\0\0\x1\xa9\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\n\0\0\0\x1-\0\xff\xff\xff\xfa\0\0\0\x2\x1\0\0\0\x3\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\0\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\x1-\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x33\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x34\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowNextStateGroup\6\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\6\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\6\size=@Size(2560 1337) +Verdi_1\qBaseWindowNextStateGroup\6\geometry_x=-1 +Verdi_1\qBaseWindowNextStateGroup\6\geometry_y=27 +Verdi_1\qBaseWindowNextStateGroup\6\geometry_width=2560 +Verdi_1\qBaseWindowNextStateGroup\6\geometry_height=1337 +Verdi_1\qBaseWindowNextStateGroup\7\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_OneSearch\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_OneSearch\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_OneSearch\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_nWave_2\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_nWave_2\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_nWave_2\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_nWave_2\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_nWave_2\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_nWave_2\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\7\ProductVersion=201809 +Verdi_1\qBaseWindowNextStateGroup\7\Layout="@ByteArray(\0\0\0\xff\0\0\0\a\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x3<\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x2\x8e\0\0\0\x89\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\xe9\0\0\0\xc6\0\0\0k\0\0\0k\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\x1\0\0\x2\x94\0\0\al\0\0\0k\0\xff\xff\xff\0\0\0\x3\0\0\n\0\0\0\x1\xa9\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\n\0\0\0\x2,\0\xff\xff\xff\xfa\0\0\0\x2\x1\0\0\0\x3\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\x1\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\x1-\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x33\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x34\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowNextStateGroup\7\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\7\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\7\size=@Size(2560 1337) +Verdi_1\qBaseWindowNextStateGroup\7\geometry_x=-1 +Verdi_1\qBaseWindowNextStateGroup\7\geometry_y=27 +Verdi_1\qBaseWindowNextStateGroup\7\geometry_width=2560 +Verdi_1\qBaseWindowNextStateGroup\7\geometry_height=1337 +Verdi_1\qBaseWindowNextStateGroup\8\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\windowDock_OneSearch\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\windowDock_OneSearch\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\windowDock_nWave_2\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\windowDock_nWave_2\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\windowDock_nWave_2\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\windowDock_nWave_2\qBaseWindowBeMax=1 +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\windowDock_nWave_2\qBaseWindowBeFix=1 +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\windowDock_nWave_2\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\8\ProductVersion=201809 +Verdi_1\qBaseWindowNextStateGroup\8\Layout="@ByteArray(\0\0\0\xff\0\0\0\b\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x3<\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x2\x8e\0\0\0\0\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\xe9\0\0\0\xc6\0\0\0k\0\0\0k\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\0\0\0\x2\x94\0\0\al\0\0\0k\0\xff\xff\xff\0\0\0\x3\0\0\n\0\0\0\x1\xa9\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\n\0\0\0\x1-\0\xff\xff\xff\xfa\0\0\0\x2\x1\0\0\0\x3\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\0\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\x1-\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x33\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x34\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowNextStateGroup\8\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\8\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\8\size=@Size(2560 1337) +Verdi_1\qBaseWindowNextStateGroup\8\geometry_x=-1 +Verdi_1\qBaseWindowNextStateGroup\8\geometry_y=27 +Verdi_1\qBaseWindowNextStateGroup\8\geometry_width=2560 +Verdi_1\qBaseWindowNextStateGroup\8\geometry_height=1337 +Verdi_1\qBaseWindowNextStateGroup\9\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\windowDock_OneSearch\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\windowDock_OneSearch\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\windowDock_OneSearch\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\windowDock_nWave_2\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\windowDock_nWave_2\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\windowDock_nWave_2\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\windowDock_nWave_2\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\windowDock_nWave_2\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\windowDock_nWave_2\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\9\ProductVersion=201809 +Verdi_1\qBaseWindowNextStateGroup\9\Layout="@ByteArray(\0\0\0\xff\0\0\0\t\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x3<\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x2\x8e\0\0\0\x89\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\xe9\0\0\0\xc6\0\0\0k\0\0\0k\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\x1\0\0\x2\x94\0\0\al\0\0\0k\0\xff\xff\xff\0\0\0\x3\0\0\n\0\0\0\x1\xa9\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\n\0\0\0\x2,\0\xff\xff\xff\xfa\0\0\0\x2\x1\0\0\0\x3\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\x1\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\x1-\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x33\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x34\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowNextStateGroup\9\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\9\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\9\size=@Size(2560 1337) +Verdi_1\qBaseWindowNextStateGroup\9\geometry_x=-1 +Verdi_1\qBaseWindowNextStateGroup\9\geometry_y=27 +Verdi_1\qBaseWindowNextStateGroup\9\geometry_width=2560 +Verdi_1\qBaseWindowNextStateGroup\9\geometry_height=1337 +Verdi_1\qBaseWindowNextStateGroup\10\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\windowDock_OneSearch\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\windowDock_OneSearch\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\windowDock_nWave_2\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\windowDock_nWave_2\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\windowDock_nWave_2\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\windowDock_nWave_2\qBaseWindowBeMax=1 +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\windowDock_nWave_2\qBaseWindowBeFix=1 +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\windowDock_nWave_2\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\10\ProductVersion=201809 +Verdi_1\qBaseWindowNextStateGroup\10\Layout="@ByteArray(\0\0\0\xff\0\0\0\n\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x3<\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x2\x8e\0\0\0\0\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\xe9\0\0\0\xc6\0\0\0k\0\0\0k\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\0\0\0\x2\x94\0\0\al\0\0\0k\0\xff\xff\xff\0\0\0\x3\0\0\n\0\0\0\x1\xa9\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\n\0\0\0\x1-\0\xff\xff\xff\xfa\0\0\0\x2\x1\0\0\0\x3\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\0\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\x1-\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x33\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x34\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowNextStateGroup\10\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\10\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\10\size=@Size(2560 1337) +Verdi_1\qBaseWindowNextStateGroup\10\geometry_x=-1 +Verdi_1\qBaseWindowNextStateGroup\10\geometry_y=27 +Verdi_1\qBaseWindowNextStateGroup\10\geometry_width=2560 +Verdi_1\qBaseWindowNextStateGroup\10\geometry_height=1337 +Verdi_1\qBaseWindowNextStateGroup\11\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeMax=1 +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_OneSearch\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_OneSearch\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_nWave_2\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_nWave_2\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_nWave_2\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_nWave_2\qBaseWindowBeMax=1 +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_nWave_2\qBaseWindowBeFix=1 +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_nWave_2\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\11\ProductVersion=201809 +Verdi_1\qBaseWindowNextStateGroup\11\Layout="@ByteArray(\0\0\0\xff\0\0\0\v\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x3<\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x2\x8e\0\0\0\0\0\xff\xff\xff\xfa\xff\xff\xff\xff\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\xe9\0\0\0\xc6\0\0\0k\0\0\0k\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\0\0\0\x2\x94\0\0\al\0\0\0k\0\xff\xff\xff\0\0\0\x3\0\0\n\0\0\0\x4\xeb\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\n\0\0\0\x1-\0\xff\xff\xff\xfa\0\0\0\x2\x1\0\0\0\x3\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\0\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\x1-\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x33\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x34\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowNextStateGroup\11\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\11\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\11\size=@Size(2560 1337) +Verdi_1\qBaseWindowNextStateGroup\11\geometry_x=-1 +Verdi_1\qBaseWindowNextStateGroup\11\geometry_y=27 +Verdi_1\qBaseWindowNextStateGroup\11\geometry_width=2560 +Verdi_1\qBaseWindowNextStateGroup\11\geometry_height=1337 +Verdi_1\qBaseWindowNextStateGroup\12\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeMax=1 +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\windowDock_OneSearch\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\windowDock_OneSearch\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\windowDock_nWave_2\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\windowDock_nWave_2\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\windowDock_nWave_2\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\windowDock_nWave_2\qBaseWindowBeMax=1 +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\windowDock_nWave_2\qBaseWindowBeFix=1 +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\windowDock_nWave_2\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\12\ProductVersion=201809 +Verdi_1\qBaseWindowNextStateGroup\12\Layout="@ByteArray(\0\0\0\xff\0\0\0\f\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x3<\xfc\x1\0\0\0\x2\xfc\0\0\0\0\0\0\x2\x8e\0\0\0\0\0\xff\xff\xff\xfa\xff\xff\xff\xff\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\xe9\0\0\0\xc6\0\0\0k\0\0\0k\0\0\0\x3\0\0\n\0\0\0\x4\xeb\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\n\0\0\0\x1-\0\xff\xff\xff\xfa\0\0\0\x2\x1\0\0\0\x4\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\0\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\x1-\0\xff\xff\xff\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\0\0\0\0\0\xff\xff\xff\xff\0\0\al\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x33\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x34\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowNextStateGroup\12\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\12\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\12\size=@Size(2560 1337) +Verdi_1\qBaseWindowNextStateGroup\12\geometry_x=-1 +Verdi_1\qBaseWindowNextStateGroup\12\geometry_y=27 +Verdi_1\qBaseWindowNextStateGroup\12\geometry_width=2560 +Verdi_1\qBaseWindowNextStateGroup\12\geometry_height=1337 +Verdi_1\qBaseWindowNextStateGroup\13\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_OneSearch\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_OneSearch\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_OneSearch\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_nWave_2\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_nWave_2\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_nWave_2\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_nWave_2\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_nWave_2\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_nWave_2\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\13\ProductVersion=201809 +Verdi_1\qBaseWindowNextStateGroup\13\Layout="@ByteArray(\0\0\0\xff\0\0\0\r\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x3<\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x2\x8e\0\0\0\x89\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\xe9\0\0\0\xc6\0\0\0k\0\0\0k\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\x1\0\0\x2\x94\0\0\al\0\0\0k\0\xff\xff\xff\0\0\0\x3\0\0\n\0\0\0\x1\xa9\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\n\0\0\0\x2,\0\xff\xff\xff\xfa\0\0\0\x2\x1\0\0\0\x3\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\x1\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\x1-\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x33\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x34\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowNextStateGroup\13\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\13\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\13\size=@Size(2560 1337) +Verdi_1\qBaseWindowNextStateGroup\13\geometry_x=-1 +Verdi_1\qBaseWindowNextStateGroup\13\geometry_y=27 +Verdi_1\qBaseWindowNextStateGroup\13\geometry_width=2560 +Verdi_1\qBaseWindowNextStateGroup\13\geometry_height=1337 + +[QwMainWindow] +window\Verdi_1\layout="@ByteArray(\0\0\0\xff\0\x3\x14Q\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x2\xcb\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x2\x8d\0\0\0\x89\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\xe9\0\0\0\xc6\0\0\0k\0\0\0k\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\x1\0\0\x2\x93\0\0\am\0\0\0k\0\xff\xff\xff\0\0\0\x3\0\0\n\0\0\0\x2\x1a\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\n\0\0\0\x2,\0\xff\xff\xff\xfa\0\0\0\x2\x1\0\0\0\x3\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\x1\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\x1-\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x33\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x34\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +window\Verdi_1\geometry=@ByteArray(\x1\xd9\xd0\xcb\0\x1\0\0\xff\xff\xff\xff\0\0\0\x1b\0\0\n\0\0\0\x5z\0\0\0\0\0\0\0\0\xff\xff\xff\xfe\xff\xff\xff\xfe\0\0\0\0\x2\0) +window\Verdi_1\menubar=true +window\Verdi_1\splitters\tbvConstrDbgSplitter\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x2\0\0\0\x8d\0\0\0\x8d\x1\0\0\0\x6\x1\0\0\0\x1) +window\Verdi_1\splitters\tbvConstrRerandSplitter\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x2\0\0\0G\0\0\0\x4\x1\0\0\0\x6\x1\0\0\0\x2) +window\Verdi_1\splitters\tbvConstrOriginSplitter\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x2\0\0\0!\0\0\0\x4\x1\0\0\0\x6\x1\0\0\0\x2) +window\Verdi_1\splitters\ThreadPane\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x2\0\0\0\x37\0\0\0\x37\x1\0\0\0\x6\x1\0\0\0\x2) +window\Verdi_1\splitters\tbvInteractiveSplitter\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x2\0\0\0\x1f\0\0\0\x1f\x1\0\0\0\x6\x1\0\0\0\x2) +window\Verdi_1\splitters\tbvVSimSplitter\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x2\0\0\0\x1f\0\0\0\x1f\x1\0\0\0\x6\x1\0\0\0\x2) +window\Verdi_1\splitters\tbvTBHSplitter\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x2\0\0\0-\0\0\0?\x1\0\0\0\x6\x1\0\0\0\x2) +window\nWave_2\layout="@ByteArray(\0\0\0\xff\0\x3\x14Q\xfd\0\0\0\0\0\0\n\0\0\0\x1\xb2\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x2\0\0\0\x2\0\0\0\f\0\0\0\x12\0W\0\x41\0V\0\x45\0_\0O\0P\0\x45\0N\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x12\0W\0\x41\0V\0\x45\0_\0\x45\0\x44\0I\0T\x1\0\0\0?\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x16\0W\0\x41\0V\0\x45\0_\0\x43\0U\0R\0S\0O\0R\x1\0\0\0\xb4\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x12\0W\0\x41\0V\0\x45\0_\0V\0I\0\x45\0W\x1\0\0\x2R\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\"\0W\0\x41\0V\0\x45\0_\0S\0\x45\0\x41\0R\0\x43\0H\0_\0\x45\0V\0\x45\0N\0T\x1\0\0\x2\xac\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0W\0\x41\0V\0\x45\0_\0R\0\x45\0P\0L\0\x41\0Y\0_\0S\0I\0M\0\0\0\x5K\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x12\0W\0\x41\0V\0\x45\0_\0G\0O\0T\0O\x1\0\0\x3H\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0W\0\x41\0V\0\x45\0_\0G\0O\0T\0O\0_\0N\0\x41\0M\0\x45\0\x44\0_\0M\0\x41\0R\0K\0\x45\0R\0\0\0\x5\xed\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0W\0\x41\0V\0\x45\0_\0T\0R\0\x41\0N\0S\0\x41\0\x43\0T\0I\0O\0N\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0W\0\x41\0V\0\x45\0_\0\x45\0X\0P\0L\0O\0R\0\x45\0_\0P\0R\0O\0P\0\x45\0R\0T\0Y\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0W\0\x41\0V\0\x45\0_\0\x46\0I\0N\0\x44\0_\0S\0I\0G\0N\0\x41\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x18\0W\0\x41\0V\0\x45\0_\0P\0R\0I\0M\0\x41\0R\0Y\0\0\0\x6\x1b\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x32\0S\0\x45\0L\0\x45\0\x43\0T\0I\0O\0N\0_\0M\0\x45\0S\0S\0\x41\0G\0\x45\0_\0T\0O\0O\0L\0\x42\0\x41\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +window\nWave_2\geometry=@ByteArray(\x1\xd9\xd0\xcb\0\x1\0\0\0\0\0\0\0\0\0\x1b\0\0\t\xff\0\0\x1\xfe\0\0\0\0\0\0\0\x1b\0\0\t\xff\0\0\x1\xfe\0\0\0\0\0\0) +window\nWave_2\menubar=true +window\nWave_2\splitters\splitter_5\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\x1\xb2\x1\0\0\0\x1\0\0\0\0\x2) +window\nWave_2\splitters\splitter_2\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x2\0\0\0\xd8\0\0\t(\x1\0\0\0\x1\0\0\0\0\x1) +window\nWave_2\splitters\splitter\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x3\0\0\0?\0\0\0\x1\0\0\b\xe6\x1\0\0\0\x1\0\0\0\0\x1) +window\nWave_2\splitters\Pane_Upper\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x2\0\0\0\xd8\0\0\t%\x1\0\0\0\x1\0\0\0\0\x1) +window\nWave_2\splitters\splitter_3\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x2\0\0\0?\0\0\tW\x1\0\0\0\x1\0\0\0\0\x1) +window\nWave_2\splitters\wholeSplitter\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x3\0\0\0O\0\0\0\xa3\0\0\0\x4\x1\0\0\0\x6\x1\0\0\0\x1) +window\nWave_2\splitters\middleSplitter\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0\x4\x1\0\0\0\x6\x1\0\0\0\x2) +window\nMemory_3\layout=@ByteArray(\0\0\0\xff\0\x3\x14Q\xfd\0\0\0\0\0\0\x4\xfd\0\0\x1\xda\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x2\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0M\0\x45\0M\0_\0T\0O\0O\0L\0\x42\0\x41\0R\0_\0U\0P\0P\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x34\0N\0M\0\x45\0M\0_\0T\0O\0O\0L\0\x42\0\x41\0R\0_\0U\0P\0P\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0_\0\x32\x1\0\0\0?\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x34\0N\0M\0\x45\0M\0_\0T\0O\0O\0L\0\x42\0\x41\0R\0_\0U\0P\0P\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0_\0\x33\x1\0\0\x1\xd3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x34\0N\0M\0\x45\0M\0_\0T\0O\0O\0L\0\x42\0\x41\0R\0_\0L\0O\0W\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0_\0\x31\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0) +window\nMemory_3\geometry=@ByteArray(\x1\xd9\xd0\xcb\0\x1\0\0\0\0\0\0\0\0\0\x1b\0\0\x4\xfc\0\0\x2@\0\0\0\0\0\0\0\x1b\0\0\x4\xfc\0\0\x2@\0\0\0\0\0\0) +window\nMemory_3\menubar=true +window\nMemory_4\layout=@ByteArray(\0\0\0\xff\0\x3\x14Q\xfd\0\0\0\0\0\0\x4\xfd\0\0\x1\xda\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x2\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0M\0\x45\0M\0_\0T\0O\0O\0L\0\x42\0\x41\0R\0_\0U\0P\0P\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x34\0N\0M\0\x45\0M\0_\0T\0O\0O\0L\0\x42\0\x41\0R\0_\0U\0P\0P\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0_\0\x32\x1\0\0\0?\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x34\0N\0M\0\x45\0M\0_\0T\0O\0O\0L\0\x42\0\x41\0R\0_\0U\0P\0P\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0_\0\x33\x1\0\0\x1\xd3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x34\0N\0M\0\x45\0M\0_\0T\0O\0O\0L\0\x42\0\x41\0R\0_\0L\0O\0W\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0_\0\x31\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0) +window\nMemory_4\geometry=@ByteArray(\x1\xd9\xd0\xcb\0\x1\0\0\0\0\0\0\0\0\0\x1b\0\0\x4\xfc\0\0\x2@\0\0\0\0\0\0\0\x1b\0\0\x4\xfc\0\0\x2@\0\0\0\0\0\0) +window\nMemory_4\menubar=true + +[qBaseWindow_saveRestoreSession_group] +10=/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/digital_top/verdiLog/novas_autosave.ses + +[qDockerWindow_C] +Verdi_1\position.x=-1 +Verdi_1\position.y=27 +Verdi_1\width=2560 +Verdi_1\height=1337 diff --git a/tb/digital_top/novas.rc b/tb/digital_top/novas.rc new file mode 100644 index 0000000..66543f4 --- /dev/null +++ b/tb/digital_top/novas.rc @@ -0,0 +1,1319 @@ +@verdi rc file Version 1.0 +[Library] +work = ./work +[Annotation] +3D_Active_Annotation = FALSE +[CommandSyntax.finsim] +InvokeCommand = +FullFileName = TRUE +Separator = . +SimPromptSign = ">" +HierNameLevel = 1 +RunContinue = "continue" +Finish = "quit" +UseAbsTime = FALSE +NextTime = "run 1" +NextNTime = "run ${SimBPTime}" +NextEvent = "run 1" +Reset = +ObjPosBreak = "break posedge ${SimBPObj}" +ObjNegBreak = "break negedge ${SimBPObj}" +ObjAnyBreak = "break change ${SimBPObj}" +ObjLevelBreak = +LineBreak = "breakline ${SimBPFile} ${SimBPLine}" +AbsTimeBreak = "break abstimeaf ${SimBPTime}" +RelTimeBreak = "break reltimeaf ${SimBPTime}" +EnableBP = "breakon ${SimBPId}" +DisableBP = "breakoff ${SimBPId}" +DeleteBP = "breakclr ${SimBPId}" +DeleteAllBP = "breakclr" +SimSetScope = "cd ${SimDmpObj}" +[CommandSyntax.ikos] +InvokeCommand = "setvar debussy true;elaborate -p ${SimTop} -s ${SimArch}; run until 0;fsdbInteractive; " +FullFileName = TRUE +NeedTimeUnit = TRUE +NormalizeTimeUnit = TRUE +Separator = / +HierNameLevel = 2 +RunContinue = "run" +Finish = "exit" +NextTime = "run ${SimBPTime} ${SimTimeUnit}" +NextNTime = "run for ${SimBPTime} ${SimTimeUnit}" +NextEvent = "step 1" +Reset = "reset" +ObjPosBreak = "stop if ${SimBPObj} = \"'1'\"" +ObjNegBreak = "stop if ${SimBPObj} = \"'0'\"" +ObjAnyBreak = +ObjLevelBreak = "stop if ${SimBPObj} = ${SimBPValue}" +LineBreak = "stop at ${SimBPFile}:${SimBPLine}" +AbsTimeBreak = +RelTimeBreak = +EnableBP = "enable ${SimBPId}" +DisableBP = "disable ${SimBPId}" +DeleteBP = "delete ${SimBPId}" +DeleteAllBP = "delete *" +[CommandSyntax.verisity] +InvokeCommand = +FullFileName = FALSE +Separator = . +SimPromptSign = "> " +HierNameLevel = 1 +RunContinue = "." +Finish = "$finish;" +NextTime = "$db_steptime(1);" +NextNTime = "$db_steptime(${SimBPTime});" +NextEvent = "$db_step;" +SimSetScope = "$scope(${SimDmpObj});" +Reset = "$reset;" +ObjPosBreak = "$db_breakonposedge(${SimBPObj});" +ObjNegBreak = "$db_breakonnegedge(${SimBPObj});" +ObjAnyBreak = "$db_breakwhen(${SimBPObj});" +ObjLevelBreak = "$db_breakwhen(${SimBPObj}, ${SimBPValue});" +LineBreak = "$db_breakatline(${SimBPLine}, ${SimBPScope}, \"${SimBPFile}\");" +AbsTimeBreak = "$db_breakbeforetime(${SimBPTime});" +RelTimeBreak = "$db_breakbeforetime(${SimBPTime});" +EnableBP = "$db_enablebreak(${SimBPId});" +DisableBP = "$db_disablebreak(${SimBPId});" +DeleteBP = "$db_deletebreak(${SimBPId});" +DeleteAllBP = "$db_deletebreak;" +FSDBInit = "$novasInteractive;" +FSDBDumpvars = "$novasDumpvars(0, ${SimDmpObj});" +FSDBDumpsingle = "$novasDumpsingle(${SimDmpObj});" +FSDBDumpvarsInFile = "$novasDumpvarsToFile(\"${SimDmpFile}\");" +FSDBDumpMem = "$novasDumpMemNow(${SimDmpObj}, ${SimDmpBegin}, ${SimDmpSize});" +[CoverageDetail] +cross_filter_limit = 1000 +branch_limit_vector_display = 50 +showgrid = TRUE +reuseFirst = TRUE +justify = TRUE +scrollbar_mode = per pane +test_combo_left_truncate = TRUE +instance_combo_left_truncate = TRUE +loop_navigation = TRUE +condSubExpr = 20 +tglMda = 1000 +linecoverable = 100000 +lineuncovered = 50000 +tglcoverable = 30000 +tgluncovered = 30000 +pendingMax = 1000 +show_full_more = FALSE +[CoverageHier] +showgrid = FALSE +[CoverageWeight] +Assert = 1 +Covergroup = 1 +Line = 1 +Condition = 1 +Toggle = 1 +FSM = 1 +Branch = 1 +[DesignTree] +IfShowModule = {TRUE, FALSE} +[DisabledMessages] +version = Verdi_O-2018.09-SP2 +[Editor] +editorName = TurboEditor +[Emacs] +EmacsFont = "Clean 14" +EmacsBG = white +EmacsFG = black +[Exclusion] +enableAsDefault = TRUE +saveAsDefault = TRUE +saveManually = TRUE +illegalBehavior = FALSE +DisplayExcludedItem = FALSE +adaptiveExclusion = TRUE +warningExcludeInstance = TRUE +favorite_exclude_annotation = "" +[FSM] +viewport = 65 336 387 479 +WndBk-FillColor = Gray3 +Background-FillColor = gray5 +prefKey_Link-FillColor = yellow4 +prefKey_Link-TextColor = black +Trap = red3 +Hilight = blue4 +Window = Gray3 +Selected = white +Trans. = green2 +State = black +Init. = black +SmartTips = TRUE +VectorFont = FALSE +StopAskBkgndColor = FALSE +ShowStateAction = FALSE +ShowTransAction = FALSE +ShowTransCond = FALSE +StateLable = NAME +StateValueRadix = ORIG +State-LineColor = ID_BLACK +State-LineWidth = 1 +State-FillColor = ID_BLUE2 +State-TextColor = ID_WHITE +Init_State-LineColor = ID_BLACK +Init_State-LineWidth = 2 +Init_State-FillColor = ID_YELLOW2 +Init_State-TextColor = ID_BLACK +Reset_State-LineColor = ID_BLACK +Reset_State-LineWidth = 2 +Reset_State-FillColor = ID_YELLOW7 +Reset_State-TextColor = ID_BLACK +Trap_State-LineColor = ID_RED2 +Trap_State-LineWidth = 2 +Trap_State-FillColor = ID_CYAN5 +Trap_State-TextColor = ID_RED2 +State_Action-LineColor = ID_BLACK +State_Action-LineWidth = 1 +State_Action-FillColor = ID_WHITE +State_Action-TextColor = ID_BLACK +Junction-LineColor = ID_BLACK +Junction-LineWidth = 1 +Junction-FillColor = ID_GREEN2 +Junction-TextColor = ID_BLACK +Connection-LineColor = ID_BLACK +Connection-LineWidth = 1 +Connection-FillColor = ID_GRAY5 +Connection-TextColor = ID_BLACK +prefKey_Port-LineColor = ID_BLACK +prefKey_Port-LineWidth = 1 +prefKey_Port-FillColor = ID_ORANGE6 +prefKey_Port-TextColor = ID_YELLOW2 +Transition-LineColor = ID_BLACK +Transition-LineWidth = 1 +Transition-FillColor = ID_WHITE +Transition-TextColor = ID_BLACK +Trans_Condition-LineColor = ID_BLACK +Trans_Condition-LineWidth = 1 +Trans_Condition-FillColor = ID_WHITE +Trans_Condition-TextColor = ID_ORANGE2 +Trans_Action-LineColor = ID_BLACK +Trans_Action-LineWidth = 1 +Trans_Action-FillColor = ID_WHITE +Trans_Action-TextColor = ID_GREEN2 +SelectedSet-LineColor = ID_RED2 +SelectedSet-LineWidth = 1 +SelectedSet-FillColor = ID_RED2 +SelectedSet-TextColor = ID_WHITE +StickSet-LineColor = ID_ORANGE5 +StickSet-LineWidth = 1 +StickSet-FillColor = ID_PURPLE6 +StickSet-TextColor = ID_BLACK +HilightSet-LineColor = ID_RED5 +HilightSet-LineWidth = 1 +HilightSet-FillColor = ID_RED7 +HilightSet-TextColor = ID_BLUE5 +ControlPoint-LineColor = ID_BLACK +ControlPoint-LineWidth = 1 +ControlPoint-FillColor = ID_WHITE +Bundle-LineColor = ID_BLACK +Bundle-LineWidth = 1 +Bundle-FillColor = ID_WHITE +Bundle-TextColor = ID_BLUE4 +QtBackground-FillColor = ID_GRAY6 +prefKey_Link-LineColor = ID_ORANGE2 +prefKey_Link-LineWidth = 1 +Selection-LineColor = ID_BLUE2 +Selection-LineWidth = 1 +[FSM_Dlg-Print] +Orientation = Landscape +[FileBrowser] +nWaveOpenFsdbDirHistory = "\"/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/digital_top/verdplus_000.fsdb\"" +[Form] +version = Verdi_O-2018.09-SP2 +nMemory/nMemGetVariable.fm = 347,480,638,472 +wave/unknownSave.fm = 100,100,520,275 +wave/sigCPL.fm = 100,100,243,333 +[General] +autoSaveSession = FALSE +TclAutoSource = +cmd_enter_form = FALSE +SyncBrowserDir = TRUE +SignalCaseInSensitive = FALSE +ShowWndCtntDuringResizing = FALSE +version = Verdi_O-2018.09-SP2 +[GlobalProp] +ErrWindow_Font = Helvetica_M_R_12 +[Globals] +app_default_font = Bitstream Vera Sans,10,-1,5,50,0,0,0,0,0 +app_fixed_width_font = Courier,10,-1,5,50,0,0,0,0,0 +text_encoding = Unicode(utf8) +smart_resize = TRUE +smart_resize_child_limit = 2000 +tooltip_max_width = 200 +tooltip_max_height = 20 +tooltip_viewer_key = F3 +tooltip_display_time = 1000 +bookmark_name_length_limit = 12 +disable_tooltip = FALSE +auto_load_source = TRUE +max_array_size = 4096 +filter_when_typing = TRUE +filter_keep_children = TRUE +filter_syntax = Wildcards +filter_keystroke_interval = 800 +filter_case_sensitive = FALSE +filter_full_path = FALSE +load_detail_for_funcov = FALSE +sort_limit = 100000 +ignoreDBVersionChecking = FALSE +[HB] +ViewSchematic = FALSE +windowLayout = 0 0 804 500 182 214 804 148 +import_filter = *.v; *.vc; *.f +designTreeFont = *-adobe-courier-medium-r-*-*-12-*-*-*-*-*-iso8859-* +import_filter_vhdl = *.vhd; *.vhdl; *.f +import_default_language = Verilog +import_filter_verilog = *.v; *.vc; *.f +simulation_file_type = *.fsdb;*.fsdb.gz;*.fsdb.bz2;*.ff;*.dump +PrefetchViewableAnnot = TRUE +[Hier] +filterTimeout = 1500 +[ImportLiberty] +SearchPriority = .lib++ +bSkipStateCell = False +bImportPowerInfo = False +bSkipFFCell = False +bScpecifyCellNameCase = False +bSpecifyPinNameCase = False +CellNameToCase = +PinNameToCase = +[Language] +EditWindow_Font = COURIER12 +Background = ID_WHITE +Comment = ID_GRAY4 +Keyword = ID_BLUE5 +UserKeyword = ID_GREEN2 +Text = ID_BLACK +SelText = ID_WHITE +SelBackground = ID_BLUE2 +[Library.Ikos] +pack = ./work.lib++ +vital = ./work.lib++ +work = ./work.lib++ +std = ${dls_std}.lib++ +ieee = ${dls_ieee}.lib++ +synopsys = ${dls_synopsys}.lib++ +silc = ${dls_silc}.lib++ +ikos = ${dls_ikos}.lib++ +novas = ${VOYAGER_LIB_VHDL}/${VOYAGER_MACHINE}/novas.lib++ +[MDT] +ART_RF_SP = spr[0-9]*bx[0-9]* +ART_RF_2P = dpr[0-9]*bx[0-9]* +ART_SRAM_SP = spm[0-9]*bx[0-9]* +ART_SRAM_DP = dpm[0-9]*bx[0-9]* +VIR_SRAM_SP = hdsd1_[0-9]*x[0-9]*cm4sw1 +VIR_SRAM_DP = hdsd2_[0-9]*x[0-9]*cm4sw1 +VIR_RF_SP = rfsd1_[0-9]*x[0-9]*cm2sw0 +VIR_RF_DP = rfsd2_[0-9]*x[0-9]*cm2sw1 +VIR_STAR_SRAM_SP = shsd1_[0-9]*x[0-9]*cm4sw0 +[NPExpanding] +functiongroups = FALSE +modules = FALSE +[NPFilter] +showAssertion = TRUE +showCoverGroup = TRUE +showProperty = TRUE +showSequence = TRUE +showDollarUnit = TRUE +[OldFontRC] +Wave_legend_window_font = -f COURIER12 -c ID_CYAN5 +Wave_value_window_font = -f COURIER12 -c ID_CYAN5 +Wave_curve_window_font = -f COURIER12 -c ID_CYAN5 +Wave_group_name_font = -f COURIER12 -c ID_GREEN5 +Wave_ruler_value_font = -f COURIER12 -c ID_CYAN5 +Wave_analog_ruler_value_font = -f COURIER12 -c ID_CYAN5 +Wave_comment_string_font = -f COURIER12 -c ID_RED5 +HB_designTreeFont = *-adobe-courier-medium-r-*-*-12-*-*-*-*-*-iso8859-* +Text_font = COURIER12 +nMemory_font = Fixed 14 +Wave_getsignal_form_font = -f COURIER12 +Text_annotFont = Helvetica_M_R_10 +[OtherEditor] +cmd1 = "xterm -font 9x15 -fg black -bg gray -e" +name = "vi" +options = "+${CurLine} ${CurFullFileName}" +[Power] +PowerDownInstance = ID_GRAY1 +RetentionSignal = ID_YELLOW2 +IsolationSignal = ID_RED6 +LevelShiftedSignal = ID_GREEN6 +PowerSwitchObject = ID_ORANGE5 +AlwaysOnObject = ID_GREEN5 +PowerNet = ID_RED2 +GroundNet = ID_RED2 +SimulationOnly = ID_CYAN3 +SRSN/SPA = ID_CYAN3 +CNSSignal = ID_CYAN3 +RPTRSignal = ID_CYAN3 +AcknowledgeSignal = ID_CYAN3 +BoundaryPort = ID_CYAN3 +DisplayInstrumentedCell = TRUE +ShowCmdByFile = FALSE +ShowPstAnnot = FALSE +ShowIsoSymbol = TRUE +ExtractIsoSameNets = FALSE +AnnotateSignal = TRUE +HighlightPowerObject = TRUE +HighlightPowerDomain = TRUE +TraceThroughInstruLowPower = FALSE +BrightenPowerColorInSchematicWindow = FALSE +ShowAlias = FALSE +ShowVoltage = TRUE +MatchTreeNodesCaseInsensitive = FALSE +SearchHBNodeDynamically = FALSE +ContinueTracingSupplyOrLogicNet = FALSE +[Print] +PrinterName = lp +FileName = test.ps +PaperSize = A4 - 210x297 (mm) +ColorPrint = FALSE +[PropertyTools] +saveWaveformStat = TRUE +savePropStat = FALSE +savePropDtl = TRUE +[QtDialog] +ExpressionDialog_AppendLogicalExpression = 984,563,590,340 +ExpressionDialog = 890,486,778,493 +QwWarnMsgDlg = 979,811,600,250 +QwUserAskDlg = 1118,679,324,110 +openFileDlg = 978,491,602,483 +SetWindowTimeUnitDialog = 1062,689,433,86 +[Relationship] +hideRecursiceNode = FALSE +[Session Cache] +2 = string (session file name) +3 = string (session file name) +4 = string (session file name) +5 = string (session file name) +1 = /home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/digital_top/verdiLog/novas_autosave.ses +[Simulation] +scsPath = scsim +scsOption = +xlPath = verilog +xlOption = +ncPath = ncsim +ncOption = -f ncsim.args +osciPath = gdb +osciOption = +vcsPath = simv +vcsOption = +mtiPath = vsim +mtiOption = +vhncPath = ncsim +vhncOption = -log debussy.nc.log +mixncPath = ncsim +mixncOption = -log debussy.mixnc.log +speedsimPath = +speedsimOption = +mti_vlogPath = vsim +mti_vlogOption = novas_vlog +vcs_mixPath = simv +vcs_mixOption = -vhdlrun "-vhpi debussy:FSDBDumpCmd" +scs_mixPath = scsim +scs_mixOption = -vhpi debussy:FSDBDumpCmd +interactiveDebugging = {True, False} +KeepBreakPoints = False +ScsDebugAll = False +simType = {vcssv, xl, nc, vcs, mti, mti_vlog, vhnc, scs, mixnc} +thirdpartyIdx = -1 +iscCmdSep = FALSE +NoAppendOption = False +[SimulationPlus] +xlPath = verilog +xlOption = +ncPath = ncsim +ncOption = -f ncsim.args +vcsPath = simv +vcsOption = +mti_vlogPath = vsim +mti_vlogOption = novas_vlog +mtiPath = vsim +mtiOption = +vhncPath = ncsim +vhncOption = -log debussy.nc.log +speedsimPath = verilog +speedsimOption = +mixncPath = ncsim +mixncOption = -log debussy.mixnc.log +scsPath = scsim +scsOption = +vcs_mixPath = simv +vcs_mixOption = -vhdlrun "-vhpi debussy:FSDBDumpCmd" +scs_mixPath = scsim +scs_mixOption = -vhpi debussy:FSDBDumpCmd +vcs_svPath = simv +vcs_svOption = +simType = vcssv +thirdpartyIdx = -1 +interactiveDebugging = FALSE +KeepBreakPoints = FALSE +iscCmdSep = FALSE +ScsDebugAll = FALSE +NoAppendOption = FALSE +invokeSimPath = work +[SimulationPlus2] +eventDumpUnfinish = FALSE +[Source] +wordWrapOn = TRUE +viewReuse = TRUE +lineNumberOn = TRUE +warnOutdatedDlg = TRUE +showEncrypt = FALSE +loadInclude = FALSE +showColorForActive = FALSE +tabWidth = 8 +editor = vi +reload = Never +sync_active_to_source = TRUE +navigateAsColored = FALSE +navigateCovered = FALSE +navigateUncovered = TRUE +navigateExcluded = FALSE +not_ask_for_source_path = FALSE +expandMacroOn = TRUE +expandMacroInstancesThreshold = 10000 +[SourceVHDL] +vhSimType = ModelSim +ohSimType = VerilogXL +[TclShell] +nLineSize = 1024 +[Test] +verbose_progress = FALSE +[TestBenchBrowser] +-showUVMDynamicHierTreeWin = FALSE +[Text] +hdlTypeName = blue4 +hdlLibrary = blue4 +viewport = 396 392 445 487 +hdlOther = ID_BLACK +hdlComment = ID_GRAY1 +hdlKeyword = ID_BLUE5 +hdlEntity = ID_BLACK +hdlEntityInst = ID_BLACK +hdlSignal = ID_RED2 +hdlInSignal = ID_RED2 +hdlOutSignal = ID_RED2 +hdlInOutSignal = ID_RED2 +hdlOperator = ID_BLACK +hdlMinus = ID_BLACK +hdlSymbol = ID_BLACK +hdlString = ID_BLACK +hdlNumberBase = ID_BLACK +hdlNumber = ID_BLACK +hdlLiteral = ID_BLACK +hdlIdentifier = ID_BLACK +hdlSystemTask = ID_BLACK +hdlParameter = ID_BLACK +hdlIncFile = ID_BLACK +hdlDataFile = ID_BLACK +hdlCDSkipIf = ID_GRAY1 +hdlMacro = ID_BLACK +hdlMacroValue = ID_BLACK +hdlPlainText = ID_BLACK +hdlOvaId = ID_PURPLE2 +hdlPslId = ID_PURPLE2 +HvlEId = ID_BLACK +HvlVERAId = ID_BLACK +hdlEscSignal = ID_BLACK +hdlEscInSignal = ID_BLACK +hdlEscOutSignal = ID_BLACK +hdlEscInOutSignal = ID_BLACK +textBackgroundColor = ID_GRAY6 +textHiliteBK = ID_BLUE5 +textHiliteText = ID_WHITE +textTracedMark = ID_GREEN2 +textLineNo = ID_BLACK +textFoldedLineNo = ID_RED5 +textUserKeyword = ID_GREEN2 +textParaAnnotText = ID_BLACK +textFuncAnnotText = ID_BLUE2 +textAnnotText = ID_BLACK +textUserDefAnnotText = ID_BLACK +ComputedSignal = ID_PURPLE5 +textAnnotTextShadow = ID_WHITE +parenthesisBGColor = ID_YELLOW5 +codeInParenthesis = ID_CYAN5 +text3DLight = ID_WHITE +text3DShadow = ID_BLACK +textHvlDriver = ID_GREEN3 +textHvlLoad = ID_YELLOW3 +textHvlDriverLoad = ID_BLUE3 +irOutline = ID_RED2 +irDriver = ID_YELLOW5 +irLoad = ID_BLACK +irBookMark = ID_YELLOW2 +irIndicator = ID_WHITE +irBreakpoint = ID_GREEN5 +irCurLine = ID_BLUE5 +hdlVhEntity = ID_BLACK +hdlArchitecture = ID_BLACK +hdlPackage = ID_BLUE5 +hdlRefPackage = ID_BLUE5 +hdlAlias = ID_BLACK +hdlGeneric = ID_BLUE5 +specialAnnotShadow = ID_BLUE1 +hdlZeroInHead = ID_GREEN2 +hdlZeroInComment = ID_GREEN2 +hdlPslHead = ID_BLACK +hdlPslComment = ID_BLACK +hdlSynopsysHead = ID_GREEN2 +hdlSynopsysComment = ID_GREEN2 +pdmlIdentifier = ID_BLACK +pdmlCommand = ID_BLACK +pdmlMacro = ID_BLACK +font = COURIER12 +annotFont = Helvetica_M_R_10 +[Text.1] +viewport = -1 27 2560 1337 45 +[TextPrinter] +Orientation = Landscape +Indicator = FALSE +LineNum = TRUE +FontSize = 7 +Column = 2 +Annotation = TRUE +[Texteditor] +TexteditorFont = "Clean 14" +TexteditorBG = white +TexteditorFG = black +[ThirdParty] +ThirdPartySimTool = verisity surefire ikos finsim +[TurboEditor] +autoBackup = TRUE +[UserButton.mixnc] +Button1 = "Dump All Signals" "call fsdbDumpvars\n" +Button2 = "Next 1000 Time" "run 1000 -relative\n" +Button3 = "Next ? Time" "run ${Arg:Next Time} -relative\n" +Button4 = "Run Next" "run -next\n" +Button5 = "Run Step" "run -step\n" +Button6 = "Run Return" "run -return\n" +Button7 = "Show Variables" "value {${NCSelVars}}\n" +Button8 = "FSDB Ver" "call fsdbVersion" +Button9 = "Dump On" "call fsdbDumpon" +Button10 = "Dump Off" "call fsdbDumpoff" +Button11 = "All Tasks" "call" +Button12 = "Dump Selected Instance" "call fsdbDumpvars 1 ${SelInst}" +[UserButton.mti] +Button1 = "Dump All Signals" "fsdbDumpvars\n" +Button2 = "Next 1000 Time" "run 1000\n" +Button3 = "Next ? Time" "run ${Arg:Next Time}\n" +Button4 = "Show Variables" "exa ${SelVars}\n" +Button5 = "Force Variable" "force -freeze ${SelVar} ${Arg:New Value} 0\n" +Button6 = "Release Variable" "noforce ${SelVar}\n" +Button7 = "Deposit Variable" "force -deposit ${SelVar} ${Arg:New Value} 0\n" +[UserButton.mti_vlog] +Button1 = "Dump All Signals" "fsdbDumpvars\n" +Button2 = "Next 1000 Time" "run 1000\n" +Button3 = "Next ? Time" "run ${Arg:Next Time}\n" +Button4 = "Show Variables" "exa ${SelVars}\n" +Button5 = "Force Variable" "force -freeze ${SelVar} ${Arg:New Value} 0\n" +Button6 = "Release Variable" "noforce ${SelVar}\n" +Button7 = "Deposit Variable" "force -deposit ${SelVar} ${Arg:New Value} 0\n" +[UserButton.nc] +Button1 = "Dump All Signals" "call fsdbDumpvars\n" +Button2 = "Next 1000 Time" "run 1000 -relative\n" +Button3 = "Next ? Time" "run ${Arg:Next Time} -relative\n" +Button4 = "Run Next" "run -next\n" +Button5 = "Run Step" "run -step\n" +Button6 = "Run Return" "run -return\n" +Button7 = "Show Variables" "value {${NCSelVars}}\n" +[UserButton.scs] +Button1 = "Dump All Signals" "call fsdbDumpvars(0, \"${TopScope}\");\n" +Button2 = "Next 1000 Time" "run 1000 \n" +Button3 = "Next ? Time" "run ${Arg:Next Time} \n" +Button4 = "Run Step" "step\n" +Button5 = "Show Variables" "ls -v {${SelVars}}\n" +[UserButton.vhnc] +Button1 = "Dump All Signals" "call fsdbDumpvars\n" +Button2 = "Next 1000 Time" "run 1000 -relative\n" +Button3 = "Next ? Time" "run ${Arg:Next Time} -relative\n" +Button4 = "Run Next" "run -next\n" +Button5 = "Run Step" "run -step\n" +Button6 = "Run Return" "run -return\n" +Button7 = "Show Variables" "value {${NCSelVars}}\n" +[UserButton.xl] +Button13 = "Dump Off" "$fsdbDumpoff;\n" +Button12 = "Dump On" "$fsdbDumpon;\n" +Button11 = "Delete Focus" "$db_deletefocus(${treeSelScope});\n" +Button10 = "Set Focus" "$db_setfocus(${treeSelScope});\n" +Button9 = "Deposit Variable" "$deposit(${SelVar},${Arg:New Value});\n" +Button8 = "Release Variable" "release ${SelVar};\n" +Button7 = "Force Variable" "force ${SelVar} = ${Arg:New Value};\n" +Button6 = "Show Variables" "$showvars(${SelVars});\n" +Button5 = "Next ? Event" "$db_step(${Arg:Next Event});\n" +Button4 = "Next Event" "$db_step(1);\n" +Button3 = "Next ? Time" "#${Arg:Next Time} $stop;.\n" +Button2 = "Next 1000 Time" "#1000 $stop;.\n" +Button1 = "Dump All Signals" "$fsdbDumpvars;\n" +[VIA] +viaLogViewerDefaultRuleOneSearchForm = "share/VIA/Apps/PredefinedRules/Misc/Onesearch_rule.rc" +[VIA.oneSearch.preference] +DefaultDisplayTimeUnit = "1.000000ns" +DefaultLogTimeUnit = "1.000000ns" +[VIA.oneSearch.preference.vgifColumnSettingRC] +[VIA.oneSearch.preference.vgifColumnSettingRC.setting0] +parRuleSets = "" +[VIA.oneSearch.preference.vgifColumnSettingRC.setting0.column0] +name = Code +width = 60 +visualIndex = 2 +isHidden = TRUE +isUserChangeColumnVisible = FALSE +[VIA.oneSearch.preference.vgifColumnSettingRC.setting0.column1] +name = Type +width = 60 +visualIndex = 3 +isHidden = TRUE +isUserChangeColumnVisible = FALSE +[VIA.oneSearch.preference.vgifColumnSettingRC.setting0.column2] +name = Severity +width = 60 +visualIndex = 1 +isHidden = TRUE +isUserChangeColumnVisible = FALSE +[VIA.oneSearch.preference.vgifColumnSettingRC.setting0.column3] +name = Message +width = 2000 +visualIndex = 4 +isHidden = FALSE +isUserChangeColumnVisible = FALSE +[VIA.oneSearch.preference.vgifColumnSettingRC.setting0.column4] +name = Time +width = 60 +visualIndex = 0 +isHidden = TRUE +isUserChangeColumnVisible = FALSE +[Vi] +ViFont = "Clean 14" +ViBG = white +ViFG = black +[Wave] +ovaEventSuccessColor = -c ID_CYAN5 +ovaEventFailureColor = -c ID_RED5 +ovaBooleanSuccessColor = -c ID_CYAN5 +ovaBooleanFailureColor = -c ID_RED5 +ovaAssertSuccessColor = -c ID_GREEN5 +ovaAssertFailureColor = -c ID_RED5 +ovaForbidSuccessColor = -c ID_GREEN5 +SigGroupRuleFile = +DisplayFileName = FALSE +waveform_vertical_scroll_bar = TRUE +scope_to_save_with_macro +open_file_dir +open_rc_file_dir +viewPort = 0 27 2560 484 216 63 +signalSpacing = 5 +digitalSignalHeight = 15 +analogSignalHeight = 98 +commentSignalHeight = 98 +transactionSignalHeight = 98 +messageSignalHeight = 98 +minCompErrWidth = 4 +DragZoomTolerance = 4 +maxTransExpandedLayer = 10 +WaveMaxPoint = 512 +legendBackground = -c ID_BLACK +valueBackground = -c ID_BLACK +curveBackground = -c ID_BLACK +getSignalSignalList_BackgroundColor = -c ID_GRAY6 +glitchColor = -c ID_RED5 +cursor = -c ID_YELLOW5 -lw 1 -ls long_dashed +marker = -c ID_WHITE -lw 1 -ls dash_dot_l +usermarker = -c ID_GREEN5 -lw 1 -ls long_dashed +trace = -c ID_GRAY5 -lw 1 -ls long_dashed +grid = -c ID_WHITE -lw 1 -ls short_dashed +rulerBackground = -c ID_GRAY3 +rulerForeground = -c ID_YELLOW5 +busTextColor = -c ID_ORANGE8 +legendForeground = -c ID_CYAN5 +valueForeground = -c ID_CYAN5 +curveForeground = -c ID_CYAN5 +groupNameColor = -c ID_GREEN5 +commentStringColor = -c ID_RED5 +region(Active)Background = -c ID_YELLOW1 +region(NBA)Background = -c ID_RED1 +region(Re-Active)Background = -c ID_YELLOW3 +region(Re-NBA)Background = -c ID_RED3 +region(VHDL-Delta)Background = -c ID_ORANGE3 +region(Dump-Off)Background = -c ID_GRAY4 +High_Light = -c ID_GRAY2 +Input_Signal = -c ID_RED5 +Output_Signal = -c ID_GREEN5 +InOut_Signal = -c ID_BLUE5 +Net_Signal = -c ID_YELLOW5 +Register_Signal = -c ID_PURPLE5 +Verilog_Signal = -c ID_CYAN5 +VHDL_Signal = -c ID_ORANGE5 +SystemC_Signal = -c ID_BLUE7 +Dump_Off_Color = -c ID_BLUE2 +Compress_Bar_Color = -c ID_YELLOW4 +Vector_Dense_Block_Color = -c ID_ORANGE8 +Scalar_Dense_Block_Color = -c ID_GREEN6 +Analog_Dense_Block_Color = -c ID_PURPLE2 +Composite_Dense_Block_Color = -c ID_ORANGE5 +RPTR_Power_Off_Layer = -c ID_CYAN3 -stipple dots +DB_Power_Off_Layer = -c ID_BLUE4 -stipple dots +SPA_Driver_Power_Off_Layer = -c ID_ORANGE4 -stipple dots +SPA_Receiver_Power_Off_Layer = -c ID_GREEN5 -stipple dots +SRSN_Power_Off_Layer = -c ID_GREEN4 -stipple dots +Isolation_Power_Off_Layer = -c ID_RED4 -stipple dots +PD_Power_Off_Layer = -c ID_GRAY4 -stipple dots +Isolation_Layer = -c ID_RED4 -stipple vLine +Retention_Level_Trigger_Layer = -c ID_ORANGE1 -stipple fill_solid +Retention_Edge_Trigger_Layer = -c ID_YELLOW6 -stipple fill_solid +Driving_Power_Off_Layer = -c ID_YELLOW2 -stipple x +Toggle_Layer = -c ID_YELLOW4 -stipple slash +analogRealStyle = pwl +analogVoltageStyle = pwl +analogCurrentStyle = pwl +analogOthersStyle = pwl +busSignalLayer = -c ID_ORANGE8 +busXLayer = -c ID_RED5 +busZLayer = -c ID_ORANGE6 +busMixedLayer = -c ID_GREEN5 +busNotComputedLayer = -c ID_GRAY1 +busNoValueLayer = -c ID_BLUE2 +signalGridLayer = -c ID_WHITE +analogGridLayer = -c ID_GRAY6 +analogRulerLayer = -c ID_GRAY6 +keywordLayer = -c ID_RED5 +loadedLayer = -c ID_BLUE5 +loadingLayer = -c ID_BLACK +qdsCurMarkerLayer = -c ID_BLUE5 +qdsBrkMarkerLayer = -c ID_GREEN5 +qdsTrgMarkerLayer = -c ID_RED5 +arrowDefaultColor = -c ID_ORANGE6 +startNodeArrowColor = -c ID_WHITE +endNodeArrowColor = -c ID_YELLOW5 +propertyEventMatchColor = -c ID_GREEN5 +propertyEventNoMatchColor = -c ID_RED5 +propertyVacuousSuccessMatchColor = -c ID_YELLOW2 +propertyStatusBoundaryColor = -c ID_WHITE +propertyBooleanSuccessColor = -c ID_CYAN5 +propertyBooleanFailureColor = -c ID_RED5 +propertyAssertSuccessColor = -c ID_GREEN5 +propertyAssertFailureColor = -c ID_RED5 +propertyForbidSuccessColor = -c ID_GREEN5 +transactionForegroundColor = -c ID_YELLOW8 +transactionBackgroundColor = -c ID_BLACK +transactionHighLightColor = -c ID_CYAN6 +transactionRelationshipColor = -c ID_PURPLE6 +transactionErrorTypeColor = -c ID_RED5 +coverageFullyCoveredColor = -c ID_GREEN5 +coverageNoCoverageColor = -c ID_RED5 +coveragePartialCoverageColor = -c ID_YELLOW5 +coverageReferenceLineColor = -c ID_GRAY4 +messageForegroundColor = -c ID_YELLOW4 +messageBackgroundColor = -c ID_PURPLE1 +messageHighLightColor = -c ID_CYAN6 +messageInformationColor = -c ID_RED5 +ComputedAnnotColor = -c ID_PURPLE5 +fsvSecurityDataColor = -c ID_PURPLE3 +qdsAutoBusGroup = TRUE +qdsTimeStampMode = FALSE +qdsVbfBusOrderAscending = FALSE +openDumpFilter = *.fsdb;*.vf;*.jf +DumpFileFilter = *.vcd +RestoreSignalFilter = *.rc +SaveSignalFilter = *.rc +AddAliasFilter = *.alias;*.adb +CompareSignalFilter = *.err +ConvertFFFilter = *.vcd;*.out;*.tr0;*.xp;*.raw;*.wfm +Scroll_Ratio = 100 +Zoom_Ratio = 10 +EventSequence_SyncCursorTime = TRUE +EventSequence_Sorting = FALSE +EventSequence_RemoveGrid = FALSE +EventSequence_IsGridMode = FALSE +SetDefaultRadix_global = FALSE +DefaultRadix = Hex +SigSearchSignalMatchCase = FALSE +SigSearchSignalScopeOption = FALSE +SigSearchSignalSamenetInterface = FALSE +SigSearchSignalFullScope = FALSE +SigSearchSignalWithRegExp = FALSE +SigSearchDynamically = FALSE +SigDisplayBySelectionOrder = FALSE +SigDisplayRowMajor = FALSE +SigDragSelFollowColumn = FALSE +SigDisplayHierarchyBox = TRUE +SigDisplaySubscopeBox = TRUE +SigDisplayEmptyScope = TRUE +SigDisplaySignalNavigationBox = FALSE +SigDisplayFormBus = TRUE +SigShowSubProgram = TRUE +SigSearchScopeDynamically = TRUE +SigCollapseSubtreeNodes = FALSE +activeFileApplyToAnnotation = FALSE +GrpSelMode = TRUE +dispGridCount = FALSE +hierarchyName = FALSE +partial_level_name = FALSE +partial_level_head = 1 +partial_level_tail = 1 +displayMessageLabelOnly = TRUE +autoInsertDumpoffs = TRUE +displayMessageCallStack = FALSE +displayCallStackWithFullSections = TRUE +displayCallStackWithLastSection = FALSE +limitMessageMaxWidth = FALSE +messageMaxWidth = 50 +displayTransBySpecificColor = FALSE +fittedTransHeight = FALSE +snap = TRUE +gravitySnap = FALSE +displayLeadingZero = FALSE +displayGlitchs = FALSE +allfileTimeRange = FALSE +fixDelta = FALSE +displayCursorMarker = FALSE +autoUpdate = FALSE +restoreFromActiveFile = TRUE +restoreToEnd = FALSE +dispCompErr = TRUE +showMsgDes = TRUE +anaAutoFit = FALSE +anaAutoPattn = FALSE +anaAuto100VertFit = FALSE +displayDeltaY = FALSE +centerCursor = FALSE +denseBlockDrawing = TRUE +relativeFreqPrecision = 3 +showMarkerAbsolute = FALSE +showMarkerAdjacent = FALSE +showMarkerRelative = FALSE +showMarkerFrequency = FALSE +stickCursorMarkerOnWaveform = TRUE +keepMarkerAtEndTimeOfTransaction = FALSE +doubleClickToExpandTransaction = TRUE +expandTransactionAssociatedSignals = TRUE +expandTransactionAttributeSignals = FALSE +WaveExtendLastTick = TRUE +InOutSignal = FALSE +NetRegisterSignal = FALSE +VerilogVHDLSignal = FALSE +LabelMarker = TRUE +ResolveSymbolicLink = TRUE +signal_rc_abspath = TRUE +signal_rc_no_natural_bus_range = FALSE +save_scope_with_macro = FALSE +TipInSignalWin = FALSE +DisplayPackedSiganlInBitwiseManner = FALSE +DisplaySignalTypeAheadOfSignalName = TRUE ICON +TipInCurveWin = FALSE +MouseGesturesInCurveWin = TRUE +DisplayLSBsFirst = FALSE +PaintSpecificColorPattern = TRUE +ModuleName = TRUE +form_all_memory_signal = FALSE +formBusSignalFromPartSelects = FALSE +read_value_change_on_demand_for_drawing = FALSE +load_scopes_on_demand = on 5 +TransitionMode = TRUE +DisplayRadix = FALSE +SchemaX = FALSE +Hilight = TRUE +UseBeforeValue = FALSE +DisplayFileNameAheadOfSignalName = FALSE +DisplayFileNumberAheadOfSignalName = FALSE +DisplayValueSpace = TRUE +FitAnaByBusSize = FALSE +displayTransactionAttributeName = FALSE +expandOverlappedTrans = FALSE +dispSamplePointForAttrSig = TRUE +dispClassName = TRUE +ReloadActiveFileOnly = FALSE +NormalizeEVCD = FALSE +OverwriteAliasWithRC = TRUE +overlay_added_analog_signals = FALSE +case_insensitive = FALSE +vhdlVariableCalculate = TRUE +showError = TRUE +signal_vertical_scroll_bar = TRUE +showPortNameForDroppedInstance = FALSE +truncateFilePathInTitleBar = TRUE +filterPropVacuousSuccess = FALSE +includeLocalSignals = FALSE +encloseSignalsByGroup = TRUE +resaveSignals = TRUE +adjustBusPrefix = adjustBus_ +adjustBusBits = 1 +adjustBusSettings = 69889 +maskPowerOff = TRUE +maskIsolation = TRUE +maskRetention = TRUE +maskDrivingPowerOff = TRUE +maskToggle = TRUE +autoBackupSignals = off 5 "\"/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/digital_top/verdiLog\"" "\"novas_autosave_sig\"" +signal_rc_attribute = 65535 +signal_rc_alias_attribute = 0 +ConvertAttr1 = -inc FALSE +ConvertAttr2 = -hier FALSE +ConvertAttr3 = -ucase FALSE +ConvertAttr4 = -lcase FALSE +ConvertAttr5 = -org FALSE +ConvertAttr6 = -mem 24 +ConvertAttr7 = -deli . +ConvertAttr8 = -hier_scope FALSE +ConvertAttr9 = -inst_array FALSE +ConvertAttr10 = -vhdlnaming FALSE +ConvertAttr11 = -orgScope FALSE +analogFmtPrecision = Automatic 2 +confirmOverwrite = TRUE +confirmExit = TRUE +confirmGetAll = TRUE +printTimeRange = TRUE 0.000000 0.000000 0.000000 +printPageRange = TRUE 1 1 +printOption = 0 +printBasic = 1 0 0 FALSE FALSE +printDest = -printer {} +printSignature = {%f %h %t} {} +curveWindow_Drag&Drop_Mode = TRUE +hspiceIncOpenMode = TRUE +pcSelectMode = TRUE +hierarchyDelimiter = / +RecentFile1 = "\"/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/digital_top/verdplus_000.fsdb\"" +open_file_time_range = FALSE +value_window_aligment = Right +signal_window_alignment = Auto +ShowDeltaTime = TRUE +legend_window_font = -f COURIER12 -c ID_CYAN5 +value_window_font = -f COURIER12 -c ID_CYAN5 +curve_window_font = -f COURIER12 -c ID_CYAN5 +group_name_font = -f COURIER12 -c ID_GREEN5 +ruler_value_font = -f COURIER12 -c ID_CYAN5 +analog_ruler_value_font = -f COURIER12 -c ID_CYAN5 +comment_string_font = -f COURIER12 -c ID_RED5 +getsignal_form_font = -f COURIER12 +SigsCheckNum = on 1000 +filter_synthesized_net = off n +filterOutNet = on +filter_synthesized_instance = off +filterOutInstance = on +showGroupTree = TRUE +hierGroupDelim = / +MsgSeverityColor = {y \"Severity\"==\"1\" ID_RED5} {y \"Severity\"==\"2\" ID_RED6} {y \"Severity\"==\"3\" ID_RED7} {y \"Severity\"==\"4\" ID_RED8} {y \"Severity\"==\"5\" ID_ORANGE5} {y \"Severity\"==\"6\" ID_ORANGE6} {y \"Severity\"==\"7\" ID_ORANGE7} {y \"Severity\"==\"8\" \ +ID_GREEN7} {y \"Severity\"==\"9\" ID_GREEN6} {y \"Severity\"==\"10\" ID_GREEN5} +AutoApplySeverityColor = TRUE +AutoAdjustMsgWidthByLabel = off +verilogStrengthDispType = type1 +waveDblClkActiveTrace = on +autoConnectTBrowser = FALSE +connectTBrowserInContainer = TRUE +SEQShowComparisonIcon = TRUE +SEQAddDriverLoadInSameGroup = TRUE +autoSyncCursorMarker = FALSE +autoSyncHorizontalRange = FALSE +autoSyncVerticalScroll = FALSE +getSignalForm = 0 0 800 479 100 30 100 30 +[cov_hier_name_column] +justify = TRUE +[coverageColors] +sou_uncov = TRUE +sou_pc = TRUE +sou_cov = TRUE +sou_exuncov = TRUE +sou_excov = TRUE +sou_unreach = TRUE +sou_unreachcon = TRUE +sou_fillColor_uncov = red +sou_fillColor_pc = yellow +sou_fillColor_cov = green3 +sou_fillColor_exuncov = grey +sou_fillColor_excov = #3C9371 +sou_fillColor_unreach = grey +sou_fillColor_unreachcon = orange +numberOfBins = 6 +rangeMin_0 = 0 +rangeMax_0 = 20 +fillColor_0 = #FF6464 +rangeMin_1 = 20 +rangeMax_1 = 40 +fillColor_1 = #FF9999 +rangeMin_2 = 40 +rangeMax_2 = 60 +fillColor_2 = #FF8040 +rangeMin_3 = 60 +rangeMax_3 = 80 +fillColor_3 = #FFFF99 +rangeMin_4 = 80 +rangeMax_4 = 100 +fillColor_4 = #99FF99 +rangeMin_5 = 100 +rangeMax_5 = 100 +fillColor_5 = #64FF64 +[coveragesetting] +assertTopoMode = FALSE +urgAppendOptions = +group_instance_new_format_name = TRUE +showvalue = FALSE +computeGroupsScoreByRatio = FALSE +computeGroupsScoreByInst = FALSE +showConditionId = FALSE +showfullhier = FALSE +nameLeftAlignment = TRUE +showAllInfoInTooltips = FALSE +copyItemHvpName = TRUE +ignoreGroupWeight = FALSE +absTestName = FALSE +HvpMergeTool = +ShowMergeMenuItem = FALSE +fsmScoreMode = transition +[eco] +NameRule = +IsFreezeSilicon = FALSE +cellQuantityManagement = FALSE +ManageMode = INSTANCE_NAME +SpareCellsPinsManagement = TRUE +LogCommitReport = FALSE +InputPinStatus = 1 +OutputPinStatus = 2 +RevisedComponentColor = ID_BLUE5 +SpareCellColor = ID_RED5 +UserName = ICer +CommentFormat = Novas ECO updated by ${UserName} ${Date} ${Time} +PrefixN = eco_n +PrefixP = eco_p +PrefixI = eco_i +DefaultTieUpNet = 1'b1 +DefaultTieDownNet = 1'b0 +MultipleInstantiations = TRUE +KeepClockPinConnection = FALSE +KeepAsyncResetPinConnection = FALSE +ScriptFileModeType = 1 +MagmaScriptPower = VDD +MagmaScriptGround = GND +ShowModeMsg = TRUE +AstroScriptPower = VDD +AstroScriptGround = VSS +ClearFloatingPorts = FALSE +[eco_connection] +Port/NetIsUnique = TRUE +SerialNet = 0 +SerialPort = 0 +SerialInst = 0 +[finsim] +TPLanguage = Verilog +TPName = Super-FinSim +TPPath = TOP.sim +TPOption = +AddImportArgument = FALSE +LineBreakWithScope = FALSE +StopAfterCompileOption = -i +[hvpsetting] +importExcelXMLOptions = +use_test_loca_as_source = FALSE +autoTurnOffHideMeetGoalInit = FALSE +autoTurnOffHideMeetGoal = TRUE +autoTurnOffModifierInit = FALSE +autoTurnOffModifier = TRUE +enableNumbering = TRUE +autoSaveCheck = TRUE +autoSaveTime = 5 +ShowMissingScore = TRUE +enableFeatureId = FALSE +enable_HVP_FEAT_ID = FALSE +enableMeasureConcealment = FALSE +HvpCloneHierShowMsgAgain = 1 +HvpCloneHierType = tree +HvpCloneHierMetrics = Line,Cond,FSM,Toggle,Branch,Assert +autoRecalPlanAfterLoadingCovDBUserDataPlan = false +warnMeAutoRecalPlanAfterLoadingCovDBUserDataPlan = true +autoRecalExclWithPlan = false +warnMeAutoRecalExclWithPlan = true +autoRecalPlanWithExcl = false +warnMeAutoRecalPlanWithExcl = true +warnPopupWarnWhenMultiFilters = true +warnPopupWarnIfHvpReadOnly = true +unmappedObjsReportLevel = def_var_inst +unmappedObjsReportInst = true +unmappedObjsNumOfObjs = High +[ikos] +TPLanguage = VHDL +TPName = Voyager +TPPath = vsh +TPOption = -X +AddImportArgument = FALSE +LineBreakWithScope = FALSE +StopAfterCompileOption = -i +[imp] +options = NULL +libPath = NULL +libDir = NULL +[nCompare] +ErrorViewport = 80 180 800 550 +EditorViewport = 409 287 676 475 +EditorHeightWidth = 802 380 +WaveCommand = "novas" +WaveArgs = "-nWave" +[nCompare.Wnd0] +ViewByHier = FALSE +[nMemory] +dispMode = ADDR_HINT +addrColWidth = 120 +valueColWidth = 100 +showCellBitRangeWithAddr = TRUE +wordsShownInOneRow = 8 +syncCursorTime = FALSE +fixCellColumnWidth = FALSE +font = Courier 12 +[planColors] +plan_fillColor_inactive = lightGray +plan_fillColor_warning = orange +plan_fillColor_error = red +plan_fillColor_invalid = #F0DCDB +plan_fillColor_subplan = lightGray +[schematics] +viewport = 178 262 638 516 +schBackgroundColor = black lineSolid +schBackgroundColor_qt = #000000 qt_solidLine 1 +schBodyColor = orange6 lineSolid +schBodyColor_qt = #ffb973 qt_solidLine 1 +schAsmBodyColor = blue7 lineSolid +schAsmBodyColor_qt = #a5a5ff qt_solidLine 1 +schPortColor = orange6 lineSolid +schPortColor_qt = #ffb973 qt_solidLine 1 +schCellNameColor = Gray6 lineSolid +schCellNameColor_qt = #e0e0e0 qt_solidLine 1 +schCLKNetColor = red6 lineSolid +schCLKNetColor_qt = #ff7373 qt_solidLine 1 +schPWRNetColor = red4 lineSolid +schPWRNetColor_qt = #ff0101 qt_solidLine 1 +schGNDNetColor = cyan4 lineSolid +schGNDNetColor_qt = #01ffff qt_solidLine 1 +schSIGNetColor = green8 lineSolid +schSIGNetColor_qt = #cdffcd qt_solidLine 1 +schTraceColor = yellow4 lineSolid +schTraceColor_qt = #ffff01 qt_solidLine 2 +schBackAnnotateColor = white lineSolid +schBackAnnotateColor_qt = #ffffff qt_solidLine 1 +schValue0 = yellow4 lineSolid +schValue0_qt = #ffff01 qt_solidLine 1 +schValue1 = green3 lineSolid +schValue1_qt = #008000 qt_solidLine 1 +schValueX = red4 lineSolid +schValueX_qt = #ff0101 qt_solidLine 1 +schValueZ = purple7 lineSolid +schValueZ_qt = #ffcdff qt_solidLine 1 +dimColor = cyan2 lineSolid +dimColor_qt = #008080 qt_solidLine 1 +schPreSelColor = green4 lineDash +schPreSelColor_qt = #01ff01 qt_dashLine 2 +schSIGBusNetColor = green8 lineSolid +schSIGBusNetColor_qt = #cdffcd qt_solidLine +schGNDBusNetColor = cyan4 lineSolid +schGNDBusNetColor_qt = #01ffff qt_solidLine +schPWRBusNetColor = red4 lineSolid +schPWRBusNetColor_qt = #ff0101 qt_solidLine +schCLKBusNetColor = red6 lineSolid +schCLKBusNetColor_qt = #ff7373 qt_solidLine +schEdgeSensitiveColor = orange6 lineSolid +schEdgeSensitiveColor_qt = #ffb973 qt_solidLine +schAnnotColor = cyan4 lineSolid +schAnnotColor_qt = #01ffff qt_solidLine +schInstNameColor = orange6 lineSolid +schInstNameColor_qt = #ffb973 qt_solidLine +schPortNameColor = cyan4 lineSolid +schPortNameColor_qt = #01ffff qt_solidLine +schAsmLatchColor = cyan4 lineSolid +schAsmLatchColor_qt = #01ffff qt_solidLine +schAsmRegColor = cyan4 lineSolid +schAsmRegColor_qt = #01ffff qt_solidLine +schAsmTriColor = cyan4 lineSolid +schAsmTriColor_qt = #01ffff qt_solidLine +pre_select = True +ShowPassThroughNet = False +ComputedAnnotColor = ID_PURPLE5 +[schematics_print] +Signature = FALSE +DesignName = PCU +DesignerName = bai +SignatureLocation = LowerRight +MultiPage = TRUE +AutoSliver = FALSE +[sourceColors] +BackgroundActive = gray88 +BackgroundInactive = lightgray +InactiveCode = dimgray +Selection = darkblue +Standard = black +Keyword = blue +Comment = gray25 +Number = black +String = black +Identifier = darkred +Inline = green +colorIdentifier = green +Value = darkgreen +MacroBackground = white +Missing = #400040 +[specColors] +top_plan_linked = #ADFFA6 +top_plan_ignore = #D3D3D3 +top_plan_todo = #EECBAD +sub_plan_ignore = #919191 +sub_plan_todo = #EFAFAF +sub_plan_linked = darkorange +[spec_link_setting] +use_spline = true +goto_section = false +exclude_ignore = true +truncate_abstract = false +abstract_length = 999 +compare_strategy = 2 +auto_apply_margin = FALSE +margin_top = 0.80 +margin_bottom = 0.80 +margin_left = 0.50 +margin_right = 0.50 +margin_unit = inches +[spiceDebug] +ThroughNet = ID_YELLOW5 +InstrumentSig = ID_GREEN5 +InterfaceElement = ID_GREEN5 +Run-timeInterfaceElement = ID_BLUE5 +HighlightThroughNet = TRUE +HighlightInterfaceElement = TRUE +HighlightRuntimeInterfaceElement = TRUE +HighlightSameNet = TRUE +[surefire] +TPLanguage = Verilog +TPName = SureFire +TPPath = verilog +TPOption = +AddImportArgument = TRUE +LineBreakWithScope = TRUE +StopAfterCompileOption = -tcl +[turboSchema_Printer_Options] +Orientation = Landscape +[turbo_library] +bdb_load_scope = +[vdCovFilteringSearchesStrings] +keepLastUsedFiltersMaxNum = 10 +[verisity] +TPLanguage = Verilog +TPName = "Verisity SpeXsim" +TPPath = vlg +TPOption = +AddImportArgument = FALSE +LineBreakWithScope = TRUE +StopAfterCompileOption = -s +[wave.0] +viewPort = 0 27 2560 484 216 63 +[wave.1] +viewPort = 127 219 960 332 100 65 +[wave.2] +viewPort = 38 314 686 205 100 65 +[wave.3] +viewPort = 63 63 700 400 65 41 +[wave.4] +viewPort = 84 84 700 400 65 41 +[wave.5] +viewPort = 92 105 700 400 65 41 +[wave.6] +viewPort = 0 0 700 400 65 41 +[wave.7] +viewPort = 21 21 700 400 65 41 diff --git a/tb/digital_top/novas_dump.log b/tb/digital_top/novas_dump.log new file mode 100644 index 0000000..a439c14 --- /dev/null +++ b/tb/digital_top/novas_dump.log @@ -0,0 +1,327 @@ +####################################################################################### +# log primitive debug message of FSDB dumping # +# This is for R&D to analyze when there are issues happening when FSDB dump # +####################################################################################### +ANF: vcsd_get_serial_mode_status('./simv: undefined symbol: vcsd_get_serial_mode_status') +ANF: vcsd_enable_sva_success_callback('./simv: undefined symbol: vcsd_enable_sva_success_callback') +ANF: vcsd_disable_sva_success_callback('./simv: undefined symbol: vcsd_disable_sva_success_callback') +ANF: vcsd_get_power_scope_name('./simv: undefined symbol: vcsd_get_power_scope_name') +ANF: vcsd_begin_no_value_var_info('./simv: undefined symbol: vcsd_begin_no_value_var_info') +ANF: vcsd_end_no_value_var_info('./simv: undefined symbol: vcsd_end_no_value_var_info') +ANF: vcsd_remove_xprop_merge_mode_callback('./simv: undefined symbol: vcsd_remove_xprop_merge_mode_callback') +ANF: vhpi_get_cb_info('./simv: undefined symbol: vhpi_get_cb_info') +ANF: vhpi_free_handle('./simv: undefined symbol: vhpi_free_handle') +ANF: vhpi_fetch_vcsd_handle('./simv: undefined symbol: vhpi_fetch_vcsd_handle') +ANF: vhpi_fetch_vpi_handle('./simv: undefined symbol: vhpi_fetch_vpi_handle') +ANF: vhpi_has_verilog_parent('./simv: undefined symbol: vhpi_has_verilog_parent') +ANF: vhpi_is_verilog_scope('./simv: undefined symbol: vhpi_is_verilog_scope') +ANF: scsd_xprop_is_enabled('./simv: undefined symbol: scsd_xprop_is_enabled') +ANF: scsd_xprop_sig_is_promoted('./simv: undefined symbol: scsd_xprop_sig_is_promoted') +ANF: scsd_xprop_int_xvalue('./simv: undefined symbol: scsd_xprop_int_xvalue') +ANF: scsd_xprop_bool_xvalue('./simv: undefined symbol: scsd_xprop_bool_xvalue') +ANF: scsd_xprop_enum_xvalue('./simv: undefined symbol: scsd_xprop_enum_xvalue') +ANF: scsd_xprop_register_merge_mode_cb('./simv: undefined symbol: scsd_xprop_register_merge_mode_cb') +ANF: scsd_xprop_delete_merge_mode_cb('./simv: undefined symbol: scsd_xprop_delete_merge_mode_cb') +ANF: scsd_xprop_get_merge_mode('./simv: undefined symbol: scsd_xprop_get_merge_mode') +ANF: scsd_thread_get_info('./simv: undefined symbol: scsd_thread_get_info') +ANF: scsd_thread_vc_init('./simv: undefined symbol: scsd_thread_vc_init') +ANF: scsd_master_set_delta_sync_cbk('./simv: undefined symbol: scsd_master_set_delta_sync_cbk') +ANF: scsd_fgp_get_fsdb_cores('./simv: undefined symbol: scsd_fgp_get_fsdb_cores') +ANF: msvEnableDumpingMode('./simv: undefined symbol: msvEnableDumpingMode') +ANF: msvGetVersion('./simv: undefined symbol: msvGetVersion') +ANF: msvGetInstProp('./simv: undefined symbol: msvGetInstProp') +ANF: msvIsSpiceEngineReady('./simv: undefined symbol: msvIsSpiceEngineReady') +ANF: msvSetAddProbeCallback('./simv: undefined symbol: msvSetAddProbeCallback') +ANF: msvGetInstHandle('./simv: undefined symbol: msvGetInstHandle') +ANF: msvGetProbeByInst('./simv: undefined symbol: msvGetProbeByInst') +ANF: msvGetSigHandle('./simv: undefined symbol: msvGetSigHandle') +ANF: msvGetProbeBySig('./simv: undefined symbol: msvGetProbeBySig') +ANF: msvGetProbeInfo('./simv: undefined symbol: msvGetProbeInfo') +ANF: msvRelease('./simv: undefined symbol: msvRelease') +ANF: msvSetVcCallbackFunc('./simv: undefined symbol: msvSetVcCallbackFunc') +ANF: msvCheckVcCallback('./simv: undefined symbol: msvCheckVcCallback') +ANF: msvAddVcCallback('./simv: undefined symbol: msvAddVcCallback') +ANF: msvRemoveVcCallback('./simv: undefined symbol: msvRemoveVcCallback') +ANF: msvGetLatestValue('./simv: undefined symbol: msvGetLatestValue') +ANF: msvSetEndofSimCallback('./simv: undefined symbol: msvSetEndofSimCallback') +ANF: msvIgnoredProbe('./simv: undefined symbol: msvIgnoredProbe') +ANF: msvGetThruNetInfo('./simv: undefined symbol: msvGetThruNetInfo') +ANF: msvFreeThruNetInfo('./simv: undefined symbol: msvFreeThruNetInfo') +ANF: PI_ace_get_output_time_unit('./simv: undefined symbol: PI_ace_get_output_time_unit') +ANF: PI_ace_sim_sync('./simv: undefined symbol: PI_ace_sim_sync') +ANF: msvGetRereadInitFile('./simv: undefined symbol: msvGetRereadInitFile') +ANF: msvSetBeforeRereadCallback('./simv: undefined symbol: msvSetBeforeRereadCallback') +ANF: msvSetAfterRereadCallback('./simv: undefined symbol: msvSetAfterRereadCallback') +ANF: msvSetForceCallback('./simv: undefined symbol: msvSetForceCallback') +ANF: msvSetReleaseCallback('./simv: undefined symbol: msvSetReleaseCallback') +ANF: msvGetForceStatus('./simv: undefined symbol: msvGetForceStatus') +ANF: vhdi_dt_get_type('./simv: undefined symbol: vhdi_dt_get_type') +ANF: vhdi_dt_get_key('./simv: undefined symbol: vhdi_dt_get_key') +ANF: vhdi_dt_get_vhdl_enum_info('./simv: undefined symbol: vhdi_dt_get_vhdl_enum_info') +ANF: vhdi_dt_get_vhdl_physical_info('./simv: undefined symbol: vhdi_dt_get_vhdl_physical_info') +ANF: vhdi_dt_get_vhdl_array_info('./simv: undefined symbol: vhdi_dt_get_vhdl_array_info') +ANF: vhdi_dt_get_vhdl_record_info('./simv: undefined symbol: vhdi_dt_get_vhdl_record_info') +ANF: vhdi_def_traverse_module('./simv: undefined symbol: vhdi_def_traverse_module') +ANF: vhdi_def_traverse_scope('./simv: undefined symbol: vhdi_def_traverse_scope') +ANF: vhdi_def_traverse_variable('./simv: undefined symbol: vhdi_def_traverse_variable') +ANF: vhdi_def_get_module_id_by_vhpi('./simv: undefined symbol: vhdi_def_get_module_id_by_vhpi') +ANF: vhdi_def_get_handle_by_module_id('./simv: undefined symbol: vhdi_def_get_handle_by_module_id') +ANF: vhdi_def_get_variable_info_by_vhpi('./simv: undefined symbol: vhdi_def_get_variable_info_by_vhpi') +ANF: vhdi_def_free('./simv: undefined symbol: vhdi_def_free') +ANF: vhdi_ist_traverse_scope('./simv: undefined symbol: vhdi_ist_traverse_scope') +ANF: vhdi_ist_traverse_variable('./simv: undefined symbol: vhdi_ist_traverse_variable') +ANF: vhdi_ist_convert_by_vhpi('./simv: undefined symbol: vhdi_ist_convert_by_vhpi') +ANF: vhdi_ist_clone('./simv: undefined symbol: vhdi_ist_clone') +ANF: vhdi_ist_free('./simv: undefined symbol: vhdi_ist_free') +ANF: vhdi_ist_hash_key('./simv: undefined symbol: vhdi_ist_hash_key') +ANF: vhdi_ist_compare('./simv: undefined symbol: vhdi_ist_compare') +ANF: vhdi_ist_get_value_addr('./simv: undefined symbol: vhdi_ist_get_value_addr') +ANF: vhdi_set_scsd_callback('./simv: undefined symbol: vhdi_set_scsd_callback') +ANF: vhdi_cbk_set_force_callback('./simv: undefined symbol: vhdi_cbk_set_force_callback') +ANF: vhdi_trigger_init_force('./simv: undefined symbol: vhdi_trigger_init_force') +ANF: vhdi_ist_check_scsd_callback('./simv: undefined symbol: vhdi_ist_check_scsd_callback') +ANF: vhdi_ist_add_scsd_callback('./simv: undefined symbol: vhdi_ist_add_scsd_callback') +ANF: vhdi_ist_remove_scsd_callback('./simv: undefined symbol: vhdi_ist_remove_scsd_callback') +ANF: vhdi_ist_get_scsd_user_data('./simv: undefined symbol: vhdi_ist_get_scsd_user_data') +ANF: vhdi_add_time_change_callback('./simv: undefined symbol: vhdi_add_time_change_callback') +ANF: vhdi_get_real_value_by_value_addr('./simv: undefined symbol: vhdi_get_real_value_by_value_addr') +ANF: vhdi_get_64_value_by_value_addr('./simv: undefined symbol: vhdi_get_64_value_by_value_addr') +ANF: vhdi_xprop_inst_is_promoted('./simv: undefined symbol: vhdi_xprop_inst_is_promoted') +ANF: vdi_ist_convert_by_vhdi('./simv: undefined symbol: vdi_ist_convert_by_vhdi') +ANF: vhdi_ist_get_module_id('./simv: undefined symbol: vhdi_ist_get_module_id') +ANF: vhdi_refine_foreign_scope_type('./simv: undefined symbol: vhdi_refine_foreign_scope_type') +ANF: vhdi_flush_callback('./simv: undefined symbol: vhdi_flush_callback') +ANF: vhdi_set_orig_name('./simv: undefined symbol: vhdi_set_orig_name') +ANF: vhdi_set_dump_pt('./simv: undefined symbol: vhdi_set_dump_pt') +ANF: vhdi_get_fsdb_option('./simv: undefined symbol: vhdi_get_fsdb_option') +ANF: vhdi_fgp_get_mode('./simv: undefined symbol: vhdi_fgp_get_mode') +ANF: vhdi_node_register_composite_var('./simv: undefined symbol: vhdi_node_register_composite_var') +ANF: vhdi_node_analysis('./simv: undefined symbol: vhdi_node_analysis') +ANF: vhdi_node_id('./simv: undefined symbol: vhdi_node_id') +ANF: vhdi_node_ist_check_scsd_callback('./simv: undefined symbol: vhdi_node_ist_check_scsd_callback') +ANF: vhdi_node_ist_add_scsd_callback('./simv: undefined symbol: vhdi_node_ist_add_scsd_callback') +ANF: vhdi_node_ist_get_value_addr('./simv: undefined symbol: vhdi_node_ist_get_value_addr') +VCS compile option: + option[0]: ./simv + option[1]: -l + option[2]: sim.log + option[3]: /home/synopsys/vcs/O-2018.09-SP2/linux64/bin/vcs1 + option[4]: -Mcc=gcc + option[5]: -Mcplusplus=g++ + option[6]: -Masflags= + option[7]: -Mcfl= -pipe -fPIC -O -I/home/synopsys/vcs/O-2018.09-SP2/include + option[8]: -Mxcflags= -pipe -fPIC -I/home/synopsys/vcs/O-2018.09-SP2/include + option[9]: -Mldflags= -rdynamic + option[10]: -Mout=simv + option[11]: -Mamsrun= + option[12]: -Mvcsaceobjs= + option[13]: -Mobjects= /home/synopsys/vcs/O-2018.09-SP2/linux64/lib/libvirsim.so /home/synopsys/vcs/O-2018.09-SP2/linux64/lib/liberrorinf.so /home/synopsys/vcs/O-2018.09-SP2/linux64/lib/libsnpsmalloc.so /home/synopsys/vcs/O-2018.09-SP2/linux64/lib/libvfs.so /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/pli.a + option[14]: -Mexternalobj= + option[15]: -Msaverestoreobj=/home/synopsys/vcs/O-2018.09-SP2/linux64/lib/vcs_save_restore_new.o + option[16]: -Mcrt0= + option[17]: -Mcrtn= + option[18]: -Mcsrc= + option[19]: -Msyslibs=/home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/pli.a -ldl -lm + option[20]: -l + option[21]: compile.log + option[22]: -full64 + option[23]: +lint=TFIPC-L + option[24]: +v2k + option[25]: -debug_access+all + option[26]: +vpi + option[27]: +vcsd1 + option[28]: +itf+/home/synopsys/vcs/O-2018.09-SP2/linux64/lib/vcsdp_lite.tab + option[29]: +define+DUMP_FSDB + option[30]: -lca + option[31]: -q + option[32]: -timescale=1ns/1ps + option[33]: +nospecify + option[34]: -P + option[35]: /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab + option[36]: -picarchive + option[37]: -P + option[38]: /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab + option[39]: -fsdb + option[40]: -sverilog + option[41]: -gen_obj + option[42]: -f + option[43]: files.f + option[44]: -load + option[45]: /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/libnovas.so:FSDBDumpCmd + option[46]: timescale=1ns/1ps +Chronologic Simulation VCS Release O-2018.09-SP2_Full64 +Linux 3.10.0-1160.53.1.el7.x86_64 #1 SMP Fri Jan 14 13:59:45 UTC 2022 x86_64 +CPU cores: 8 +Limit information: +====================================== +cputime unlimited +filesize unlimited +datasize unlimited +stacksize 8192 kbytes +coredumpsize 0 kbytes +memoryuse unlimited +vmemoryuse unlimited +descriptors 4096 +memorylocked 64 kbytes +maxproc 4096 +====================================== +(Special)Runtime environment variables: + +Runtime environment variables: +DESKTOP_SESSION=gnome-classic +XDG_SESSION_TYPE=x11 +XAUTHORITY=/run/gdm/auth-for-ICer-FQtMgs/database +GDMSESSION=gnome-classic +XMODIFIERS=@im=ibus +SHELL=/bin/bash +GDM_LANG=zh_CN.UTF-8 +VTE_VERSION=5204 +_=/usr/local/bin/make +HISTCONTROL=ignoredups +SNPSLMD_LICENSE_FILE=27000@IC_EDA +USERNAME=ICer +DVE_HOME=/home/synopsys/vcs/O-2018.09-SP2 +XDG_DATA_DIRS=/home/ICer/.local/share/flatpak/exports/share/:/var/lib/flatpak/exports/share/:/usr/local/share/:/usr/share/ +QT_PLUGIN_PATH=/usr/lib64/kde4/plugins:/usr/lib/kde4/plugins +LESSOPEN=||/usr/bin/lesspipe.sh %s +QUESTASIM_HOME=/home/mentor/questasim +PATH=/usr/lib/qt-3.3/bin:/usr/local/bin:/usr/local/sbin:/usr/bin:/usr/sbin:/bin:/sbin:/home/synopsys/pts/O-2018.06-SP1/bin:/home/synopsys/syn/O-2018.06-SP1/bin:/home/synopsys/lc/O-2018.06-SP1/bin:/home/synopsys/SpyGlass-L2016.06/SPYGLASS_HOME//bin:/home/synopsys/vcs/O-2018.09-SP2/gui/dve/bin:/home/synopsys/vcs/O-2018.09-SP2/bin:/home/synopsys/verdi/Verdi_O-2018.09-SP2/bin:/home/synopsys/verdi/Verdi_O-2018.09-SP2/platform/LINUX/bin:/home/synopsys/scl/2018.06/linux64/bin::/home/mentor/questasim/linux_x86_64:/home/Riscv_Tools/bin:/home/Riscv_Tools/riscv-gnu-toolchain/qemu-6.0.0/build/riscv32-linux-user +PT_HOME=/home/synopsys/pts/O-2018.06-SP1 +QT_GRAPHICSSYSTEM_CHECKED=1 +SESSION_MANAGER=local/unix:@/tmp/.ICE-unix/10289,unix/unix:/tmp/.ICE-unix/10289 +XDG_RUNTIME_DIR=/run/user/1000 +XDG_MENU_PREFIX=gnome- +LC_NUMERIC=zh_CN.UTF-8 +LS_COLORS=rs=0:di=38;5;27:ln=38;5;51:mh=44;38;5;15:pi=40;38;5;11:so=38;5;13:do=38;5;5:bd=48;5;232;38;5;11:cd=48;5;232;38;5;3:or=48;5;232;38;5;9:mi=05;48;5;232;38;5;15:su=48;5;196;38;5;15:sg=48;5;11;38;5;16:ca=48;5;196;38;5;226:tw=48;5;10;38;5;16:ow=48;5;10;38;5;21:st=48;5;21;38;5;15:ex=38;5;34:*.tar=38;5;9:*.tgz=38;5;9:*.arc=38;5;9:*.arj=38;5;9:*.taz=38;5;9:*.lha=38;5;9:*.lz4=38;5;9:*.lzh=38;5;9:*.lzma=38;5;9:*.tlz=38;5;9:*.txz=38;5;9:*.tzo=38;5;9:*.t7z=38;5;9:*.zip=38;5;9:*.z=38;5;9:*.Z=38;5;9:*.dz=38;5;9:*.gz=38;5;9:*.lrz=38;5;9:*.lz=38;5;9:*.lzo=38;5;9:*.xz=38;5;9:*.bz2=38;5;9:*.bz=38;5;9:*.tbz=38;5;9:*.tbz2=38;5;9:*.tz=38;5;9:*.deb=38;5;9:*.rpm=38;5;9:*.jar=38;5;9:*.war=38;5;9:*.ear=38;5;9:*.sar=38;5;9:*.rar=38;5;9:*.alz=38;5;9:*.ace=38;5;9:*.zoo=38;5;9:*.cpio=38;5;9:*.7z=38;5;9:*.rz=38;5;9:*.cab=38;5;9:*.jpg=38;5;13:*.jpeg=38;5;13:*.gif=38;5;13:*.bmp=38;5;13:*.pbm=38;5;13:*.pgm=38;5;13:*.ppm=38;5;13:*.tga=38;5;13:*.xbm=38;5;13:*.xpm=38;5;13:*.tif=38;5;13:*.tiff=38;5;13:*.png=38;5;13:*.svg=38;5;13:*.svgz=38;5;13:*.mng=38;5;13:*.pcx=38;5;13:*.mov=38;5;13:*.mpg=38;5;13:*.mpeg=38;5;13:*.m2v=38;5;13:*.mkv=38;5;13:*.webm=38;5;13:*.ogm=38;5;13:*.mp4=38;5;13:*.m4v=38;5;13:*.mp4v=38;5;13:*.vob=38;5;13:*.qt=38;5;13:*.nuv=38;5;13:*.wmv=38;5;13:*.asf=38;5;13:*.rm=38;5;13:*.rmvb=38;5;13:*.flc=38;5;13:*.avi=38;5;13:*.fli=38;5;13:*.flv=38;5;13:*.gl=38;5;13:*.dl=38;5;13:*.xcf=38;5;13:*.xwd=38;5;13:*.yuv=38;5;13:*.cgm=38;5;13:*.emf=38;5;13:*.axv=38;5;13:*.anx=38;5;13:*.ogv=38;5;13:*.ogx=38;5;13:*.aac=38;5;45:*.au=38;5;45:*.flac=38;5;45:*.mid=38;5;45:*.midi=38;5;45:*.mka=38;5;45:*.mp3=38;5;45:*.mpc=38;5;45:*.ogg=38;5;45:*.ra=38;5;45:*.wav=38;5;45:*.axa=38;5;45:*.oga=38;5;45:*.spx=38;5;45:*.xspf=38;5;45: +XDG_SESSION_DESKTOP=gnome-classic +SSH_AUTH_SOCK=/run/user/1000/keyring/ssh +KDEDIRS=/usr +DISPLAY=:0 +IMSETTINGS_INTEGRATE_DESKTOP=yes +HOME=/home/ICer +VCS_HOME=/home/synopsys/vcs/O-2018.09-SP2 +PWD=/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/digital_top +XDG_SEAT=seat0 +SSH_AGENT_PID=10423 +VERDI_HOME=/home/synopsys/verdi/Verdi_O-2018.09-SP2 +MGLS_LICENSE_FILE=/home/mentor/questasim/mentor.dat +DBUS_SESSION_BUS_ADDRESS=unix:abstract=/tmp/dbus-DIYqQioq7q,guid=a50f166bc97a0937429a75936639b5b6 +LD_LIBRARY_PATH=:/home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/lib/LINUX64:/home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/IUS/LINUX64/boot +RISCV=/home/Riscv_Tools +LOGNAME=ICer +GNOME_DESKTOP_SESSION_ID=this-is-deprecated +HOSTNAME=IC_EDA +XDG_VTNR=1 +COLORTERM=truecolor +QT_IM_MODULE=ibus +VCS_ARCH_OVERRIDE=linux +SHLVL=2 +GNOME_SHELL_SESSION_MODE=classic +XDG_SESSION_ID=1 +USER=ICer +LC_MONETARY=zh_CN.UTF-8 +QTLIB=/usr/lib/qt-3.3/lib +XDG_CURRENT_DESKTOP=GNOME-Classic:GNOME +IMSETTINGS_MODULE=none +MAKEFLAGS= +MFLAGS= +MAIL=/var/spool/mail/ICer +SPYGLASS_HOME=/home/synopsys/SpyGlass-L2016.06/SPYGLASS_HOME/ +MAKE_TERMOUT=/dev/pts/3 +DC_HOME=/home/synopsys/syn/O-2018.06-SP1 +LC_PAPER=zh_CN.UTF-8 +LC_HOME=/home/synopsys/lc/O-2018.06-SP1 +PS1=[\u@\h `pwd`]\$ +LC_MEASUREMENT=zh_CN.UTF-8 +DBUS_STARTER_BUS_TYPE=session +SCL_HOME=/home/synopsys/scl/2018.06 +GNOME_TERMINAL_SCREEN=/org/gnome/Terminal/screen/b3faae4f_07ba_4ce6_b83c_c942094b753b +GNOME_TERMINAL_SERVICE=:1.108 +HISTSIZE=1000 +QEMU_HOME=/home/Riscv_Tools/riscv-gnu-toolchain/qemu-6.0.0 +WINDOWPATH=1 +LC_TIME=zh_CN.UTF-8 +QTINC=/usr/lib/qt-3.3/include +QTDIR=/usr/lib/qt-3.3 +MAKE_TERMERR=/dev/pts/3 +LANG=zh_CN.UTF-8 +TERM=xterm-256color +DBUS_STARTER_ADDRESS=unix:abstract=/tmp/dbus-DIYqQioq7q,guid=a50f166bc97a0937429a75936639b5b6 +MAKELEVEL=1 +VCS_HEAP_EXEC=true +VCS_PATHMAP_PRELOAD_DONE=1 +VCS_STACK_EXEC=true +VCS_EXEC_DONE=1 +LC_ALL=C +DVE=/home/synopsys/vcs/O-2018.09-SP2/gui/dve +SPECMAN_OUTPUT_TO_TTY=1 +Runtime command line arguments: +argv[0]=./simv +argv[1]=-l +argv[2]=sim.log +261 profile - 100 + CPU/Mem usage: 0.010 sys, 0.100 user, 252.26M mem +262 Mon May 27 20:31:48 2024 +263 pliAppInit +264 FSDB_GATE is set. +265 FSDB_RTL is set. +266 Enable Parallel Dumping. +267 pliAppMiscSet: New Sim Round +268 pliEntryInit +269 LIBSSCORE=found /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/lib/LINUXAMD64/libsscore_vcs201809.so through $NOVAS_HOME setting. +270 FSDB Dumper for VCS, Release Verdi_O-2018.09-SP2, Linux x86_64/64bit, 02/21/2019 +271 (C) 1996 - 2019 by Synopsys, Inc. +272 FSDB_VCS_ENABLE_FAST_VC is enable +273 sps_call_fsdbAutoSwitchDumpfile_main_vd at 0 : ../../sim/digital_top/TB.sv(183) +274 sps_call_fsdbAutoSwitchDumpfile at 0 : ../../sim/digital_top/TB.sv(183) +275 argv[0]: (500) +276 argv[1]: (./verdplus.fsdb) +277 argv[2]: (1000000) +278 *Verdi* FSDB WARNING: The FSDB file already exists. Overwriting the FSDB file may crash the programs that are using this file. +279 *Verdi* FSDB: The switch FSDB file size might not match the input size (500MB) because of performance concerns. +280 *Verdi* FSDB: To have the FSDB file size match the input size (500MB), set the FSDB_ENV_PRECISE_AUTOSWITCH environment, though the dumping performance might decrease. +281 *Verdi* : Enable automatic switching of the FSDB file. +282 *Verdi* : (Filename='./verdplus', Limit Size=500MB, File Amount=1000000). +283 *Verdi* : Create FSDB file './verdplus_000.fsdb' +284 compile option from '/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/digital_top/simv.daidir/vcs_rebuild'. +285 "vcs '-full64' '-sverilog' '+lint=TFIPC-L' '+v2k' '-debug_access+all' '+define+DUMP_FSDB' '-lca' '-q' '-timescale=1ns/1ps' '+nospecify' '-P' '/home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab' '/home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/pli.a' '-l' 'compile.log' '-f' 'files.f' 2>&1" +286 *Verdi* : Create the file './verdplus.log' to log the time range of each FSDB file. +287 *Verdi* : Create virtual FSDB file './verdplus.vf' to log each FSDB file. +288 sps_call_fsdbDumpvars_vd_main at 0 : ../../sim/digital_top/TB.sv(184) +289 [spi_vcs_vd_ppi_create_root]: no upf option +290 FSDB dumper cannot dump UPF related power signal ($power_tree): no ppiPowerNetwork. +291 *Verdi* : Begin traversing the scopes, layer (0). +292 *Verdi* : End of traversing. +293 pliAppHDL_DumpVarComplete traverse var: profile - + CPU/Mem usage: 0.040 sys, 0.160 user, 366.14M mem + incr: 0.010 sys, 0.050 user, 26.34M mem + accu: 0.010 sys, 0.050 user, 26.34M mem + accu incr: 0.010 sys, 0.050 user, 26.34M mem + + Count usage: 13558 var, 8803 idcode, 3713 callback + incr: 13558 var, 8803 idcode, 3713 callback + accu: 13558 var, 8803 idcode, 3713 callback + accu incr: 13558 var, 8803 idcode, 3713 callback +294 Mon May 27 20:31:48 2024 +295 pliAppHDL_DumpVarComplete: profile - + CPU/Mem usage: 0.040 sys, 0.160 user, 367.33M mem + incr: 0.000 sys, 0.000 user, 1.19M mem + accu: 0.010 sys, 0.050 user, 27.53M mem + accu incr: 0.000 sys, 0.000 user, 1.19M mem + + Count usage: 13558 var, 8803 idcode, 3713 callback + incr: 0 var, 0 idcode, 0 callback + accu: 13558 var, 8803 idcode, 3713 callback + accu incr: 0 var, 0 idcode, 0 callback +296 Mon May 27 20:31:48 2024 +297 End of simulation at 3202992000 +298 Mon May 27 20:31:55 2024 +299 Begin FSDB profile info: +300 FSDB Writer : bc1(3369894) bcn(116706814) mtf/stf(0/24) +FSDB Writer elapsed time : flush(4.630404) io wait(0.000000) theadpool wait(0.000000) target functin(0.000000) +FSDB Writer cpu time : MT Compression : 0 +301 End FSDB profile info +302 Parallel profile - Flush:3 Expand:1 ProduceWait:0 ConsumerWait:137 BlockUsed:998 +303 ProduceTime:7.757765918 ConsumerTime:6.782707184 Buffer:96MB +304 SimExit +305 Sim process exit diff --git a/tb/digital_top/qbmcu_defines.v b/tb/digital_top/qbmcu_defines.v new file mode 100644 index 0000000..590fe2b --- /dev/null +++ b/tb/digital_top/qbmcu_defines.v @@ -0,0 +1,223 @@ + //+FHDR-------------------------------------------------------------------------------------------------------- +// Company: +//----------------------------------------------------------------------------------------------------------------- +// File Name : qbmcu.v +// Department : +// Author : PWY +// Author's Tel : +//----------------------------------------------------------------------------------------------------------------- +// Relese History +// Version Date Author Description +// 0.1 2024-03-13 PWY The files to include all the macro defines +//----------------------------------------------------------------------------------------------------------------- +// Keywords : +// +//----------------------------------------------------------------------------------------------------------------- +// Parameter +// +//----------------------------------------------------------------------------------------------------------------- +// Purpose : +// +//----------------------------------------------------------------------------------------------------------------- +// Target Device: +// Tool versions: +//----------------------------------------------------------------------------------------------------------------- +// Reuse Issues +// Reset Strategy: +// Clock Domains: +// Critical Timing: +// Asynchronous I/F: +// Synthesizable (y/n): +// Other: +//-FHDR-------------------------------------------------------------------------------------------------------- + + + +///////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////// +/////// ISA relevant macro +// +//system address width +`define QBMCU_ADDR_SIZE 32 + +//PC width +`define QBMCU_PC_SIZE 32 + +//system data width +`define QBMCU_XLEN 32 +//system instruction width +`define QBMCU_INSTR_SIZE 32 + +//register array index bit width +`define QBMCU_RFIDX_WIDTH 5 +//number of register arrays +`define QBMCU_RFREG_NUM 32 + +//base address of instruction memory +//initial value of the program counter (PC) -> 0x0000_0000 +`define QBMCU_ITCM_ADDR_BASE 32'h0000_0000 +//base address of data memory +`define QBMCU_DTCM_ADDR_BASE 32'h0010_0000 + +//data memory address width +`define QBMCU_DTCM_ADDR_SIZE 15 + +//instruction memory address width +`define QBMCU_ITCM_ADDR_SIZE 15 + +//BUS memory address width +`define QBMCU_BUS_ADDR_SIZE 25 + +///////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////// +/////// ALU relevant macro +// + +`define QBMCU_ALU_ADDER_WIDTH (`QBMCU_XLEN+1) + + +///////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////// +/////// Decode relevant macro +// + `define QBMCU_DECINFO_GRP_WIDTH 3 + `define QBMCU_DECINFO_GRP_ALU `QBMCU_DECINFO_GRP_WIDTH'd0 + `define QBMCU_DECINFO_GRP_AGU `QBMCU_DECINFO_GRP_WIDTH'd1 + `define QBMCU_DECINFO_GRP_BJP `QBMCU_DECINFO_GRP_WIDTH'd2 + `define QBMCU_DECINFO_GRP_EXT `QBMCU_DECINFO_GRP_WIDTH'd3 + + + `define QBMCU_DECINFO_GRP_LSB 0 + `define QBMCU_DECINFO_GRP_MSB (`QBMCU_DECINFO_GRP_LSB+`QBMCU_DECINFO_GRP_WIDTH-1) + `define QBMCU_DECINFO_GRP `QBMCU_DECINFO_GRP_MSB:`QBMCU_DECINFO_GRP_LSB + `define QBMCU_DECINFO_RV32_LSB (`QBMCU_DECINFO_GRP_MSB+1) + `define QBMCU_DECINFO_RV32_MSB (`QBMCU_DECINFO_RV32_LSB+1-1) + `define QBMCU_DECINFO_RV32 `QBMCU_DECINFO_RV32_MSB:`QBMCU_DECINFO_RV32_LSB + + `define QBMCU_DECINFO_SUBDECINFO_LSB (`QBMCU_DECINFO_RV32_MSB+1) + + // ALU group + `define QBMCU_DECINFO_ALU_ADD_LSB `QBMCU_DECINFO_SUBDECINFO_LSB + `define QBMCU_DECINFO_ALU_ADD_MSB (`QBMCU_DECINFO_ALU_ADD_LSB+1-1) + `define QBMCU_DECINFO_ALU_ADD `QBMCU_DECINFO_ALU_ADD_MSB :`QBMCU_DECINFO_ALU_ADD_LSB + `define QBMCU_DECINFO_ALU_SUB_LSB (`QBMCU_DECINFO_ALU_ADD_MSB+1) + `define QBMCU_DECINFO_ALU_SUB_MSB (`QBMCU_DECINFO_ALU_SUB_LSB+1-1) + `define QBMCU_DECINFO_ALU_SUB `QBMCU_DECINFO_ALU_SUB_MSB :`QBMCU_DECINFO_ALU_SUB_LSB + `define QBMCU_DECINFO_ALU_XOR_LSB (`QBMCU_DECINFO_ALU_SUB_MSB+1) + `define QBMCU_DECINFO_ALU_XOR_MSB (`QBMCU_DECINFO_ALU_XOR_LSB+1-1) + `define QBMCU_DECINFO_ALU_XOR `QBMCU_DECINFO_ALU_XOR_MSB :`QBMCU_DECINFO_ALU_XOR_LSB + `define QBMCU_DECINFO_ALU_SLL_LSB (`QBMCU_DECINFO_ALU_XOR_MSB+1) + `define QBMCU_DECINFO_ALU_SLL_MSB (`QBMCU_DECINFO_ALU_SLL_LSB+1-1) + `define QBMCU_DECINFO_ALU_SLL `QBMCU_DECINFO_ALU_SLL_MSB :`QBMCU_DECINFO_ALU_SLL_LSB + `define QBMCU_DECINFO_ALU_SRL_LSB (`QBMCU_DECINFO_ALU_SLL_MSB+1) + `define QBMCU_DECINFO_ALU_SRL_MSB (`QBMCU_DECINFO_ALU_SRL_LSB+1-1) + `define QBMCU_DECINFO_ALU_SRL `QBMCU_DECINFO_ALU_SRL_MSB :`QBMCU_DECINFO_ALU_SRL_LSB + `define QBMCU_DECINFO_ALU_SRA_LSB (`QBMCU_DECINFO_ALU_SRL_MSB+1) + `define QBMCU_DECINFO_ALU_SRA_MSB (`QBMCU_DECINFO_ALU_SRA_LSB+1-1) + `define QBMCU_DECINFO_ALU_SRA `QBMCU_DECINFO_ALU_SRA_MSB :`QBMCU_DECINFO_ALU_SRA_LSB + `define QBMCU_DECINFO_ALU_OR_LSB (`QBMCU_DECINFO_ALU_SRA_MSB+1) + `define QBMCU_DECINFO_ALU_OR_MSB (`QBMCU_DECINFO_ALU_OR_LSB+1-1) + `define QBMCU_DECINFO_ALU_OR `QBMCU_DECINFO_ALU_OR_MSB :`QBMCU_DECINFO_ALU_OR_LSB + `define QBMCU_DECINFO_ALU_AND_LSB (`QBMCU_DECINFO_ALU_OR_MSB+1) + `define QBMCU_DECINFO_ALU_AND_MSB (`QBMCU_DECINFO_ALU_AND_LSB+1-1) + `define QBMCU_DECINFO_ALU_AND `QBMCU_DECINFO_ALU_AND_MSB :`QBMCU_DECINFO_ALU_AND_LSB + `define QBMCU_DECINFO_ALU_SLT_LSB (`QBMCU_DECINFO_ALU_AND_MSB+1) + `define QBMCU_DECINFO_ALU_SLT_MSB (`QBMCU_DECINFO_ALU_SLT_LSB+1-1) + `define QBMCU_DECINFO_ALU_SLT `QBMCU_DECINFO_ALU_SLT_MSB :`QBMCU_DECINFO_ALU_SLT_LSB + `define QBMCU_DECINFO_ALU_SLTU_LSB (`QBMCU_DECINFO_ALU_SLT_MSB+1) + `define QBMCU_DECINFO_ALU_SLTU_MSB (`QBMCU_DECINFO_ALU_SLTU_LSB+1-1) + `define QBMCU_DECINFO_ALU_SLTU `QBMCU_DECINFO_ALU_SLTU_MSB:`QBMCU_DECINFO_ALU_SLTU_LSB + `define QBMCU_DECINFO_ALU_LUI_LSB (`QBMCU_DECINFO_ALU_SLTU_MSB+1) + `define QBMCU_DECINFO_ALU_LUI_MSB (`QBMCU_DECINFO_ALU_LUI_LSB+1-1) + `define QBMCU_DECINFO_ALU_LUI `QBMCU_DECINFO_ALU_LUI_MSB :`QBMCU_DECINFO_ALU_LUI_LSB + `define QBMCU_DECINFO_ALU_OP2IMM_LSB (`QBMCU_DECINFO_ALU_LUI_MSB+1) + `define QBMCU_DECINFO_ALU_OP2IMM_MSB (`QBMCU_DECINFO_ALU_OP2IMM_LSB+1-1) + `define QBMCU_DECINFO_ALU_OP2IMM `QBMCU_DECINFO_ALU_OP2IMM_MSB :`QBMCU_DECINFO_ALU_OP2IMM_LSB + `define QBMCU_DECINFO_ALU_OP1PC_LSB (`QBMCU_DECINFO_ALU_OP2IMM_MSB+1) + `define QBMCU_DECINFO_ALU_OP1PC_MSB (`QBMCU_DECINFO_ALU_OP1PC_LSB+1-1) + `define QBMCU_DECINFO_ALU_OP1PC `QBMCU_DECINFO_ALU_OP1PC_MSB :`QBMCU_DECINFO_ALU_OP1PC_LSB + `define QBMCU_DECINFO_ALU_NOP_LSB (`QBMCU_DECINFO_ALU_OP1PC_MSB+1) + `define QBMCU_DECINFO_ALU_NOP_MSB (`QBMCU_DECINFO_ALU_NOP_LSB+1-1) + `define QBMCU_DECINFO_ALU_NOP `QBMCU_DECINFO_ALU_NOP_MSB :`QBMCU_DECINFO_ALU_NOP_LSB + + `define QBMCU_DECINFO_ALU_WIDTH (`QBMCU_DECINFO_ALU_NOP_MSB+1) + + //AGU group + `define QBMCU_DECINFO_AGU_LOAD_LSB `QBMCU_DECINFO_SUBDECINFO_LSB + `define QBMCU_DECINFO_AGU_LOAD_MSB (`QBMCU_DECINFO_AGU_LOAD_LSB+1-1) + `define QBMCU_DECINFO_AGU_LOAD `QBMCU_DECINFO_AGU_LOAD_MSB :`QBMCU_DECINFO_AGU_LOAD_LSB + `define QBMCU_DECINFO_AGU_STORE_LSB (`QBMCU_DECINFO_AGU_LOAD_MSB+1) + `define QBMCU_DECINFO_AGU_STORE_MSB (`QBMCU_DECINFO_AGU_STORE_LSB+1-1) + `define QBMCU_DECINFO_AGU_STORE `QBMCU_DECINFO_AGU_STORE_MSB :`QBMCU_DECINFO_AGU_STORE_LSB + `define QBMCU_DECINFO_AGU_SIZE_LSB (`QBMCU_DECINFO_AGU_STORE_MSB+1) + `define QBMCU_DECINFO_AGU_SIZE_MSB (`QBMCU_DECINFO_AGU_SIZE_LSB+2-1) + `define QBMCU_DECINFO_AGU_SIZE `QBMCU_DECINFO_AGU_SIZE_MSB :`QBMCU_DECINFO_AGU_SIZE_LSB + `define QBMCU_DECINFO_AGU_USIGN_LSB (`QBMCU_DECINFO_AGU_SIZE_MSB+1) + `define QBMCU_DECINFO_AGU_USIGN_MSB (`QBMCU_DECINFO_AGU_USIGN_LSB+1-1) + `define QBMCU_DECINFO_AGU_USIGN `QBMCU_DECINFO_AGU_USIGN_MSB :`QBMCU_DECINFO_AGU_USIGN_LSB + `define QBMCU_DECINFO_AGU_OP2IMM_LSB (`QBMCU_DECINFO_AGU_USIGN_MSB+1) + `define QBMCU_DECINFO_AGU_OP2IMM_MSB (`QBMCU_DECINFO_AGU_OP2IMM_LSB+1-1) + `define QBMCU_DECINFO_AGU_OP2IMM `QBMCU_DECINFO_AGU_OP2IMM_MSB:`QBMCU_DECINFO_AGU_OP2IMM_LSB + + `define QBMCU_DECINFO_AGU_WIDTH (`QBMCU_DECINFO_AGU_OP2IMM_MSB+1) + + // Bxx group + `define QBMCU_DECINFO_BJP_JUMP_LSB `QBMCU_DECINFO_SUBDECINFO_LSB + `define QBMCU_DECINFO_BJP_JUMP_MSB (`QBMCU_DECINFO_BJP_JUMP_LSB+1-1) + `define QBMCU_DECINFO_BJP_JUMP `QBMCU_DECINFO_BJP_JUMP_MSB :`QBMCU_DECINFO_BJP_JUMP_LSB + `define QBMCU_DECINFO_BJP_BPRDT_LSB (`QBMCU_DECINFO_BJP_JUMP_MSB+1) + `define QBMCU_DECINFO_BJP_BPRDT_MSB (`QBMCU_DECINFO_BJP_BPRDT_LSB+1-1) + `define QBMCU_DECINFO_BJP_JALR `QBMCU_DECINFO_BJP_BPRDT_MSB:`QBMCU_DECINFO_BJP_BPRDT_LSB + `define QBMCU_DECINFO_BJP_BEQ_LSB (`QBMCU_DECINFO_BJP_BPRDT_MSB+1) + `define QBMCU_DECINFO_BJP_BEQ_MSB (`QBMCU_DECINFO_BJP_BEQ_LSB+1-1) + `define QBMCU_DECINFO_BJP_BEQ `QBMCU_DECINFO_BJP_BEQ_MSB :`QBMCU_DECINFO_BJP_BEQ_LSB + `define QBMCU_DECINFO_BJP_BNE_LSB (`QBMCU_DECINFO_BJP_BEQ_MSB+1) + `define QBMCU_DECINFO_BJP_BNE_MSB (`QBMCU_DECINFO_BJP_BNE_LSB+1-1) + `define QBMCU_DECINFO_BJP_BNE `QBMCU_DECINFO_BJP_BNE_MSB :`QBMCU_DECINFO_BJP_BNE_LSB + `define QBMCU_DECINFO_BJP_BLT_LSB (`QBMCU_DECINFO_BJP_BNE_MSB+1) + `define QBMCU_DECINFO_BJP_BLT_MSB (`QBMCU_DECINFO_BJP_BLT_LSB+1-1) + `define QBMCU_DECINFO_BJP_BLT `QBMCU_DECINFO_BJP_BLT_MSB :`QBMCU_DECINFO_BJP_BLT_LSB + `define QBMCU_DECINFO_BJP_BGT_LSB (`QBMCU_DECINFO_BJP_BLT_MSB+1) + `define QBMCU_DECINFO_BJP_BGT_MSB (`QBMCU_DECINFO_BJP_BGT_LSB+1-1) + `define QBMCU_DECINFO_BJP_BGT `QBMCU_DECINFO_BJP_BGT_MSB :`QBMCU_DECINFO_BJP_BGT_LSB + `define QBMCU_DECINFO_BJP_BLTU_LSB (`QBMCU_DECINFO_BJP_BGT_MSB+1) + `define QBMCU_DECINFO_BJP_BLTU_MSB (`QBMCU_DECINFO_BJP_BLTU_LSB+1-1) + `define QBMCU_DECINFO_BJP_BLTU `QBMCU_DECINFO_BJP_BLTU_MSB :`QBMCU_DECINFO_BJP_BLTU_LSB + `define QBMCU_DECINFO_BJP_BGTU_LSB (`QBMCU_DECINFO_BJP_BLTU_MSB+1) + `define QBMCU_DECINFO_BJP_BGTU_MSB (`QBMCU_DECINFO_BJP_BGTU_LSB+1-1) + `define QBMCU_DECINFO_BJP_BGTU `QBMCU_DECINFO_BJP_BGTU_MSB :`QBMCU_DECINFO_BJP_BGTU_LSB + `define QBMCU_DECINFO_BJP_BXX_LSB (`QBMCU_DECINFO_BJP_BGTU_MSB+1) + `define QBMCU_DECINFO_BJP_BXX_MSB (`QBMCU_DECINFO_BJP_BXX_LSB+1-1) + `define QBMCU_DECINFO_BJP_BXX `QBMCU_DECINFO_BJP_BXX_MSB :`QBMCU_DECINFO_BJP_BXX_LSB + +`define QBMCU_DECINFO_BJP_WIDTH (`QBMCU_DECINFO_BJP_BXX_MSB+1) + + + // EXT group + `define QBMCU_DECINFO_EXT_WAIT_LSB `QBMCU_DECINFO_SUBDECINFO_LSB + `define QBMCU_DECINFO_EXT_WAIT_MSB (`QBMCU_DECINFO_EXT_WAIT_LSB+1-1) + `define QBMCU_DECINFO_EXT_WAIT `QBMCU_DECINFO_EXT_WAIT_MSB:`QBMCU_DECINFO_EXT_WAIT_LSB + `define QBMCU_DECINFO_EXT_SEND_LSB (`QBMCU_DECINFO_EXT_WAIT_MSB+1) + `define QBMCU_DECINFO_EXT_SEND_MSB (`QBMCU_DECINFO_EXT_SEND_LSB+1-1) + `define QBMCU_DECINFO_EXT_SEND `QBMCU_DECINFO_EXT_SEND_MSB:`QBMCU_DECINFO_EXT_SEND_LSB + `define QBMCU_DECINFO_EXT_SENDC_LSB (`QBMCU_DECINFO_EXT_SEND_MSB+1) + `define QBMCU_DECINFO_EXT_SENDC_MSB (`QBMCU_DECINFO_EXT_SENDC_LSB+1-1) + `define QBMCU_DECINFO_EXT_SENDC `QBMCU_DECINFO_EXT_SENDC_MSB:`QBMCU_DECINFO_EXT_SENDC_LSB + `define QBMCU_DECINFO_EXT_EXIT_LSB (`QBMCU_DECINFO_EXT_SENDC_MSB+1) + `define QBMCU_DECINFO_EXT_EXIT_MSB (`QBMCU_DECINFO_EXT_EXIT_LSB+1-1) + `define QBMCU_DECINFO_EXT_EXIT `QBMCU_DECINFO_EXT_EXIT_MSB:`QBMCU_DECINFO_EXT_EXIT_LSB + `define QBMCU_DECINFO_EXT_EXITI_LSB (`QBMCU_DECINFO_EXT_EXIT_MSB+1) + `define QBMCU_DECINFO_EXT_EXITI_MSB (`QBMCU_DECINFO_EXT_EXITI_LSB+1-1) + `define QBMCU_DECINFO_EXT_EXITI `QBMCU_DECINFO_EXT_EXITI_MSB:`QBMCU_DECINFO_EXT_EXITI_LSB + `define QBMCU_DECINFO_EXT_OP2IMM_LSB (`QBMCU_DECINFO_EXT_EXITI_MSB+1) + `define QBMCU_DECINFO_EXT_OP2IMM_MSB (`QBMCU_DECINFO_EXT_OP2IMM_LSB+1-1) + `define QBMCU_DECINFO_EXT_OP2IMM `QBMCU_DECINFO_EXT_OP2IMM_MSB:`QBMCU_DECINFO_EXT_OP2IMM_LSB + +`define QBMCU_DECINFO_EXT_WIDTH (`QBMCU_DECINFO_EXT_OP2IMM_MSB+1) + +// Choose the longest group as the final DEC info width +`define QBMCU_DECINFO_WIDTH (`QBMCU_DECINFO_ALU_WIDTH+1) + diff --git a/tb/digital_top/qbmcu_undefines.v b/tb/digital_top/qbmcu_undefines.v new file mode 100644 index 0000000..2650f70 --- /dev/null +++ b/tb/digital_top/qbmcu_undefines.v @@ -0,0 +1,219 @@ + //+FHDR-------------------------------------------------------------------------------------------------------- +// Company: +//----------------------------------------------------------------------------------------------------------------- +// File Name : qbmcu.v +// Department : +// Author : PWY +// Author's Tel : +//----------------------------------------------------------------------------------------------------------------- +// Relese History +// Version Date Author Description +// 0.1 2024-03-13 PWY The files to include all the macro undefs +//----------------------------------------------------------------------------------------------------------------- +// Keywords : +// +//----------------------------------------------------------------------------------------------------------------- +// Parameter +// +//----------------------------------------------------------------------------------------------------------------- +// Purpose : +// +//----------------------------------------------------------------------------------------------------------------- +// Target Device: +// Tool versions: +//----------------------------------------------------------------------------------------------------------------- +// Reuse Issues +// Reset Strategy: +// Clock Domains: +// Critical Timing: +// Asynchronous I/F: +// Synthesizable (y/n): +// Other: +//-FHDR-------------------------------------------------------------------------------------------------------- + + + +///////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////// +/////// ISA relevant macro +// +//system address width +`undef QBMCU_ADDR_SIZE + +//PC width +`undef QBMCU_PC_SIZE + +//system data width +`undef QBMCU_XLEN +//system instruction width +`undef QBMCU_INSTR_SIZE + +//register array index bit width +`undef QBMCU_RFIDX_WIDTH +//number of register arrays +`undef QBMCU_RFREG_NUM + +//base address of instruction memory +//initial value of the program counter (PC) -> 0x0000_0000 +`undef QBMCU_DTCM_ADDR_BASE +//base address of data memory +`undef QBMCU_ITCM_ADDR_BASE + +//data memory address width +`undef QBMCU_DTCM_ADDR_SIZE + +//instruction memory address width +`undef QBMCU_ITCM_ADDR_SIZE + +//BUS memory address width +`undef QBMCU_BUS_ADDR_SIZE + +///////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////// +/////// ALU relevant macro +// + +`undef QBMCU_ALU_ADDER_WIDTH + + +///////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////// +/////// Decode relevant macro +// +`undef QBMCU_DECINFO_GRP_WIDTH +`undef QBMCU_DECINFO_GRP_ALU +`undef QBMCU_DECINFO_GRP_AGU +`undef QBMCU_DECINFO_GRP_BJP +`undef QBMCU_DECINFO_GRP_EXT + + +`undef QBMCU_DECINFO_GRP_LSB +`undef QBMCU_DECINFO_GRP_MSB +`undef QBMCU_DECINFO_GRP +`undef QBMCU_DECINFO_RV32_LSB +`undef QBMCU_DECINFO_RV32_MSB +`undef QBMCU_DECINFO_RV32 + +`undef QBMCU_DECINFO_SUBDECINFO_LSB + +// ALU group +`undef QBMCU_DECINFO_ALU_ADD_LSB +`undef QBMCU_DECINFO_ALU_ADD_MSB +`undef QBMCU_DECINFO_ALU_ADD +`undef QBMCU_DECINFO_ALU_SUB_LSB +`undef QBMCU_DECINFO_ALU_SUB_MSB +`undef QBMCU_DECINFO_ALU_SUB +`undef QBMCU_DECINFO_ALU_XOR_LSB +`undef QBMCU_DECINFO_ALU_XOR_MSB +`undef QBMCU_DECINFO_ALU_XOR +`undef QBMCU_DECINFO_ALU_SLL_LSB +`undef QBMCU_DECINFO_ALU_SLL_MSB +`undef QBMCU_DECINFO_ALU_SLL +`undef QBMCU_DECINFO_ALU_SRL_LSB +`undef QBMCU_DECINFO_ALU_SRL_MSB +`undef QBMCU_DECINFO_ALU_SRL +`undef QBMCU_DECINFO_ALU_SRA_LSB +`undef QBMCU_DECINFO_ALU_SRA_MSB +`undef QBMCU_DECINFO_ALU_SRA +`undef QBMCU_DECINFO_ALU_OR_LSB +`undef QBMCU_DECINFO_ALU_OR_MSB +`undef QBMCU_DECINFO_ALU_OR +`undef QBMCU_DECINFO_ALU_AND_LSB +`undef QBMCU_DECINFO_ALU_AND_MSB +`undef QBMCU_DECINFO_ALU_AND +`undef QBMCU_DECINFO_ALU_SLT_LSB +`undef QBMCU_DECINFO_ALU_SLT_MSB +`undef QBMCU_DECINFO_ALU_SLT +`undef QBMCU_DECINFO_ALU_SLTU_LSB +`undef QBMCU_DECINFO_ALU_SLTU_MSB +`undef QBMCU_DECINFO_ALU_SLTU +`undef QBMCU_DECINFO_ALU_LUI_LSB +`undef QBMCU_DECINFO_ALU_LUI_MSB +`undef QBMCU_DECINFO_ALU_LUI +`undef QBMCU_DECINFO_ALU_OP2IMM_LSB +`undef QBMCU_DECINFO_ALU_OP2IMM_MSB +`undef QBMCU_DECINFO_ALU_OP2IMM +`undef QBMCU_DECINFO_ALU_OP1PC_LSB +`undef QBMCU_DECINFO_ALU_OP1PC_MSB +`undef QBMCU_DECINFO_ALU_OP1PC +`undef QBMCU_DECINFO_ALU_NOP_LSB +`undef QBMCU_DECINFO_ALU_NOP_MSB +`undef QBMCU_DECINFO_ALU_NOP +`undef QBMCU_DECINFO_ALU_WIDTH + +//AGU group +`undef QBMCU_DECINFO_AGU_LOAD_LSB +`undef QBMCU_DECINFO_AGU_LOAD_MSB +`undef QBMCU_DECINFO_AGU_LOAD +`undef QBMCU_DECINFO_AGU_STORE_LSB +`undef QBMCU_DECINFO_AGU_STORE_MSB +`undef QBMCU_DECINFO_AGU_STORE +`undef QBMCU_DECINFO_AGU_SIZE_LSB +`undef QBMCU_DECINFO_AGU_SIZE_MSB +`undef QBMCU_DECINFO_AGU_SIZE +`undef QBMCU_DECINFO_AGU_USIGN_LSB +`undef QBMCU_DECINFO_AGU_USIGN_MSB +`undef QBMCU_DECINFO_AGU_USIGN +`undef QBMCU_DECINFO_AGU_OP2IMM_LSB +`undef QBMCU_DECINFO_AGU_OP2IMM_MSB +`undef QBMCU_DECINFO_AGU_OP2IMM +`undef QBMCU_DECINFO_AGU_WIDTH + +// Bxx group +`undef QBMCU_DECINFO_BJP_JUMP_LSB +`undef QBMCU_DECINFO_BJP_JUMP_MSB +`undef QBMCU_DECINFO_BJP_JUMP +`undef QBMCU_DECINFO_BJP_BPRDT_LSB +`undef QBMCU_DECINFO_BJP_BPRDT_MSB +`undef QBMCU_DECINFO_BJP_JALR +`undef QBMCU_DECINFO_BJP_BEQ_LSB +`undef QBMCU_DECINFO_BJP_BEQ_MSB +`undef QBMCU_DECINFO_BJP_BEQ +`undef QBMCU_DECINFO_BJP_BNE_LSB +`undef QBMCU_DECINFO_BJP_BNE_MSB +`undef QBMCU_DECINFO_BJP_BNE +`undef QBMCU_DECINFO_BJP_BLT_LSB +`undef QBMCU_DECINFO_BJP_BLT_MSB +`undef QBMCU_DECINFO_BJP_BLT +`undef QBMCU_DECINFO_BJP_BGT_LSB +`undef QBMCU_DECINFO_BJP_BGT_MSB +`undef QBMCU_DECINFO_BJP_BGT +`undef QBMCU_DECINFO_BJP_BLTU_LSB +`undef QBMCU_DECINFO_BJP_BLTU_MSB +`undef QBMCU_DECINFO_BJP_BLTU +`undef QBMCU_DECINFO_BJP_BGTU_LSB +`undef QBMCU_DECINFO_BJP_BGTU_MSB +`undef QBMCU_DECINFO_BJP_BGTU +`undef QBMCU_DECINFO_BJP_BXX_LSB +`undef QBMCU_DECINFO_BJP_BXX_MSB +`undef QBMCU_DECINFO_BJP_BXX +`undef QBMCU_DECINFO_BJP_WIDTH + + +// EXT group +`undef QBMCU_DECINFO_EXT_WAIT_LSB +`undef QBMCU_DECINFO_EXT_WAIT_MSB +`undef QBMCU_DECINFO_EXT_WAIT +`undef QBMCU_DECINFO_EXT_SEND_LSB +`undef QBMCU_DECINFO_EXT_SEND_MSB +`undef QBMCU_DECINFO_EXT_SEND +`undef QBMCU_DECINFO_EXT_SENDC_LSB +`undef QBMCU_DECINFO_EXT_SENDC_MSB +`undef QBMCU_DECINFO_EXT_SENDC +`undef QBMCU_DECINFO_EXT_EXIT_LSB +`undef QBMCU_DECINFO_EXT_EXIT_MSB +`undef QBMCU_DECINFO_EXT_EXIT +`undef QBMCU_DECINFO_EXT_EXITI_LSB +`undef QBMCU_DECINFO_EXT_EXITI_MSB +`undef QBMCU_DECINFO_EXT_EXITI +`undef QBMCU_DECINFO_EXT_OP2IMM_LSB +`undef QBMCU_DECINFO_EXT_OP2IMM_MSB +`undef QBMCU_DECINFO_EXT_OP2IMM +`undef QBMCU_DECINFO_EXT_WIDTH + +// Choose the longest group as the final DEC info width +`undef QBMCU_DECINFO_WIDTH + diff --git a/tb/digital_top/sim.log b/tb/digital_top/sim.log new file mode 100644 index 0000000..8b0b7ab --- /dev/null +++ b/tb/digital_top/sim.log @@ -0,0 +1,34664 @@ +Command: /home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/digital_top/./simv -l sim.log +Chronologic VCS simulator copyright 1991-2018 +Contains Synopsys proprietary information. +Compiler version O-2018.09-SP2_Full64; Runtime version O-2018.09-SP2_Full64; May 27 20:31 2024 +*Verdi* Loading libsscore_vcs201809.so +FSDB Dumper for VCS, Release Verdi_O-2018.09-SP2, Linux x86_64/64bit, 02/21/2019 +(C) 1996 - 2019 by Synopsys, Inc. +*Verdi* FSDB WARNING: The FSDB file already exists. Overwriting the FSDB file may crash the programs that are using this file. +*Verdi* FSDB: The switch FSDB file size might not match the input size (500MB) because of performance concerns. +*Verdi* FSDB: To have the FSDB file size match the input size (500MB), set the FSDB_ENV_PRECISE_AUTOSWITCH environment, though the dumping performance might decrease. +*Verdi* : Enable automatic switching of the FSDB file. +*Verdi* : (Filename='./verdplus', Limit Size=500MB, File Amount=1000000). +*Verdi* : Create FSDB file './verdplus_000.fsdb' +*Verdi* : Create the file './verdplus.log' to log the time range of each FSDB file. +*Verdi* : Create virtual FSDB file './verdplus.vf' to log each FSDB file. +*Verdi* : Begin traversing the scopes, layer (0). +*Verdi* : End of traversing. +write_item 0000000000000000000011010000000000000000000000000000000000000111 +write_item 63: 0 +write_item 62: 0 +write_item 61: 0 +write_item 60: 0 +write_item 59: 0 +write_item 58: 0 +write_item 57: 0 +write_item 56: 0 +write_item 55: 0 +write_item 54: 0 +write_item 53: 0 +write_item 52: 0 +write_item 51: 0 +write_item 50: 0 +write_item 49: 0 +write_item 48: 0 +write_item 47: 0 +write_item 46: 0 +write_item 45: 0 +write_item 44: 0 +write_item 43: 1 +write_item 42: 1 +write_item 41: 0 +write_item 40: 1 +write_item 39: 0 +write_item 38: 0 +write_item 37: 0 +write_item 36: 0 +write_item 35: 0 +write_item 34: 0 +write_item 33: 0 +write_item 32: 0 +write_item 31: 0 +write_item 30: 0 +write_item 29: 0 +write_item 28: 0 +write_item 27: 0 +write_item 26: 0 +write_item 25: 0 +write_item 24: 0 +write_item 23: 0 +write_item 22: 0 +write_item 21: 0 +write_item 20: 0 +write_item 19: 0 +write_item 18: 0 +write_item 17: 0 +write_item 16: 0 +write_item 15: 0 +write_item 14: 0 +write_item 13: 0 +write_item 12: 0 +write_item 11: 0 +write_item 10: 0 +write_item 9: 0 +write_item 8: 0 +write_item 7: 0 +write_item 6: 0 +write_item 5: 0 +write_item 4: 0 +write_item 3: 0 +write_item 2: 1 +write_item 1: 1 +write_item 0: 1 +reg 0: 0 +reg 1: 0 +reg 2: 0 +reg 3: 0 +reg 4: 0 +reg 5: 0 +reg 6: 0 +reg 7: 0 +reg 8: 0 +reg 9: 0 +reg 10: 0 +reg 11: 0 +reg 12: 0 +reg 13: 0 +reg 14: 0 +reg 15: 0 +reg 16: 0 +reg 17: 0 +reg 18: 0 +reg 19: 0 +reg 20: 1 +reg 21: 1 +reg 22: 0 +reg 23: 1 +reg 24: 0 +reg 25: 0 +reg 26: 0 +reg 27: 0 +reg 28: 0 +reg 29: 0 +reg 30: 0 +reg 31: 0 +reg 32: 0 +reg 33: 0 +reg 34: 0 +reg 35: 0 +reg 36: 0 +reg 37: 0 +reg 38: 0 +reg 39: 0 +reg 40: 0 +reg 41: 0 +reg 42: 0 +reg 43: 0 +reg 44: 0 +reg 45: 0 +reg 46: 0 +reg 47: 0 +reg 48: 0 +reg 49: 0 +reg 50: 0 +reg 51: 0 +reg 52: 0 +reg 53: 0 +reg 54: 0 +reg 55: 0 +reg 56: 0 +reg 57: 0 +reg 58: 0 +reg 59: 0 +reg 60: 0 +reg 61: 1 +reg 62: 1 +reg 63: 1 +write_item 0000110000000000010011000000000000000000000000000000000000000000 +write_item 63: 0 +write_item 62: 0 +write_item 61: 0 +write_item 60: 0 +write_item 59: 1 +write_item 58: 1 +write_item 57: 0 +write_item 56: 0 +write_item 55: 0 +write_item 54: 0 +write_item 53: 0 +write_item 52: 0 +write_item 51: 0 +write_item 50: 0 +write_item 49: 0 +write_item 48: 0 +write_item 47: 0 +write_item 46: 1 +write_item 45: 0 +write_item 44: 0 +write_item 43: 1 +write_item 42: 1 +write_item 41: 0 +write_item 40: 0 +write_item 39: 0 +write_item 38: 0 +write_item 37: 0 +write_item 36: 0 +write_item 35: 0 +write_item 34: 0 +write_item 33: 0 +write_item 32: 0 +write_item 31: 0 +write_item 30: 0 +write_item 29: 0 +write_item 28: 0 +write_item 27: 0 +write_item 26: 0 +write_item 25: 0 +write_item 24: 0 +write_item 23: 0 +write_item 22: 0 +write_item 21: 0 +write_item 20: 0 +write_item 19: 0 +write_item 18: 0 +write_item 17: 0 +write_item 16: 0 +write_item 15: 0 +write_item 14: 0 +write_item 13: 0 +write_item 12: 0 +write_item 11: 0 +write_item 10: 0 +write_item 9: 0 +write_item 8: 0 +write_item 7: 0 +write_item 6: 0 +write_item 5: 0 +write_item 4: 0 +write_item 3: 0 +write_item 2: 0 +write_item 1: 0 +write_item 0: 0 +reg 0: 0 +reg 1: 0 +reg 2: 0 +reg 3: 0 +reg 4: 1 +reg 5: 1 +reg 6: 0 +reg 7: 0 +reg 8: 0 +reg 9: 0 +reg 10: 0 +reg 11: 0 +reg 12: 0 +reg 13: 0 +reg 14: 0 +reg 15: 0 +reg 16: 0 +reg 17: 1 +reg 18: 0 +reg 19: 0 +reg 20: 1 +reg 21: 1 +reg 22: 0 +reg 23: 0 +reg 24: 0 +reg 25: 0 +reg 26: 0 +reg 27: 0 +reg 28: 0 +reg 29: 0 +reg 30: 0 +reg 31: 0 +reg 32: 0 +reg 33: 0 +reg 34: 0 +reg 35: 0 +reg 36: 0 +reg 37: 0 +reg 38: 0 +reg 39: 0 +reg 40: 0 +reg 41: 0 +reg 42: 0 +reg 43: 0 +reg 44: 0 +reg 45: 0 +reg 46: 0 +reg 47: 0 +reg 48: 0 +reg 49: 0 +reg 50: 0 +reg 51: 0 +reg 52: 0 +reg 53: 0 +reg 54: 0 +reg 55: 0 +reg 56: 0 +reg 57: 0 +reg 58: 0 +reg 59: 0 +reg 60: 0 +reg 61: 0 +reg 62: 0 +reg 63: 0 +write_item 0000110000000000010011010000000011101001011001000111011011100001 +write_item 63: 0 +write_item 62: 0 +write_item 61: 0 +write_item 60: 0 +write_item 59: 1 +write_item 58: 1 +write_item 57: 0 +write_item 56: 0 +write_item 55: 0 +write_item 54: 0 +write_item 53: 0 +write_item 52: 0 +write_item 51: 0 +write_item 50: 0 +write_item 49: 0 +write_item 48: 0 +write_item 47: 0 +write_item 46: 1 +write_item 45: 0 +write_item 44: 0 +write_item 43: 1 +write_item 42: 1 +write_item 41: 0 +write_item 40: 1 +write_item 39: 0 +write_item 38: 0 +write_item 37: 0 +write_item 36: 0 +write_item 35: 0 +write_item 34: 0 +write_item 33: 0 +write_item 32: 0 +write_item 31: 1 +write_item 30: 1 +write_item 29: 1 +write_item 28: 0 +write_item 27: 1 +write_item 26: 0 +write_item 25: 0 +write_item 24: 1 +write_item 23: 0 +write_item 22: 1 +write_item 21: 1 +write_item 20: 0 +write_item 19: 0 +write_item 18: 1 +write_item 17: 0 +write_item 16: 0 +write_item 15: 0 +write_item 14: 1 +write_item 13: 1 +write_item 12: 1 +write_item 11: 0 +write_item 10: 1 +write_item 9: 1 +write_item 8: 0 +write_item 7: 1 +write_item 6: 1 +write_item 5: 1 +write_item 4: 0 +write_item 3: 0 +write_item 2: 0 +write_item 1: 0 +write_item 0: 1 +reg 0: 0 +reg 1: 0 +reg 2: 0 +reg 3: 0 +reg 4: 1 +reg 5: 1 +reg 6: 0 +reg 7: 0 +reg 8: 0 +reg 9: 0 +reg 10: 0 +reg 11: 0 +reg 12: 0 +reg 13: 0 +reg 14: 0 +reg 15: 0 +reg 16: 0 +reg 17: 1 +reg 18: 0 +reg 19: 0 +reg 20: 1 +reg 21: 1 +reg 22: 0 +reg 23: 1 +reg 24: 0 +reg 25: 0 +reg 26: 0 +reg 27: 0 +reg 28: 0 +reg 29: 0 +reg 30: 0 +reg 31: 0 +reg 32: 1 +reg 33: 1 +reg 34: 1 +reg 35: 0 +reg 36: 1 +reg 37: 0 +reg 38: 0 +reg 39: 1 +reg 40: 0 +reg 41: 1 +reg 42: 1 +reg 43: 0 +reg 44: 0 +reg 45: 1 +reg 46: 0 +reg 47: 0 +reg 48: 0 +reg 49: 1 +reg 50: 1 +reg 51: 1 +reg 52: 0 +reg 53: 1 +reg 54: 1 +reg 55: 0 +reg 56: 1 +reg 57: 1 +reg 58: 1 +reg 59: 0 +reg 60: 0 +reg 61: 0 +reg 62: 0 +reg 63: 1 +write_item 0000110000000000010011100000000011111111111111111111111111111111 +write_item 63: 0 +write_item 62: 0 +write_item 61: 0 +write_item 60: 0 +write_item 59: 1 +write_item 58: 1 +write_item 57: 0 +write_item 56: 0 +write_item 55: 0 +write_item 54: 0 +write_item 53: 0 +write_item 52: 0 +write_item 51: 0 +write_item 50: 0 +write_item 49: 0 +write_item 48: 0 +write_item 47: 0 +write_item 46: 1 +write_item 45: 0 +write_item 44: 0 +write_item 43: 1 +write_item 42: 1 +write_item 41: 1 +write_item 40: 0 +write_item 39: 0 +write_item 38: 0 +write_item 37: 0 +write_item 36: 0 +write_item 35: 0 +write_item 34: 0 +write_item 33: 0 +write_item 32: 0 +write_item 31: 1 +write_item 30: 1 +write_item 29: 1 +write_item 28: 1 +write_item 27: 1 +write_item 26: 1 +write_item 25: 1 +write_item 24: 1 +write_item 23: 1 +write_item 22: 1 +write_item 21: 1 +write_item 20: 1 +write_item 19: 1 +write_item 18: 1 +write_item 17: 1 +write_item 16: 1 +write_item 15: 1 +write_item 14: 1 +write_item 13: 1 +write_item 12: 1 +write_item 11: 1 +write_item 10: 1 +write_item 9: 1 +write_item 8: 1 +write_item 7: 1 +write_item 6: 1 +write_item 5: 1 +write_item 4: 1 +write_item 3: 1 +write_item 2: 1 +write_item 1: 1 +write_item 0: 1 +reg 0: 0 +reg 1: 0 +reg 2: 0 +reg 3: 0 +reg 4: 1 +reg 5: 1 +reg 6: 0 +reg 7: 0 +reg 8: 0 +reg 9: 0 +reg 10: 0 +reg 11: 0 +reg 12: 0 +reg 13: 0 +reg 14: 0 +reg 15: 0 +reg 16: 0 +reg 17: 1 +reg 18: 0 +reg 19: 0 +reg 20: 1 +reg 21: 1 +reg 22: 1 +reg 23: 0 +reg 24: 0 +reg 25: 0 +reg 26: 0 +reg 27: 0 +reg 28: 0 +reg 29: 0 +reg 30: 0 +reg 31: 0 +reg 32: 1 +reg 33: 1 +reg 34: 1 +reg 35: 1 +reg 36: 1 +reg 37: 1 +reg 38: 1 +reg 39: 1 +reg 40: 1 +reg 41: 1 +reg 42: 1 +reg 43: 1 +reg 44: 1 +reg 45: 1 +reg 46: 1 +reg 47: 1 +reg 48: 1 +reg 49: 1 +reg 50: 1 +reg 51: 1 +reg 52: 1 +reg 53: 1 +reg 54: 1 +reg 55: 1 +reg 56: 1 +reg 57: 1 +reg 58: 1 +reg 59: 1 +reg 60: 1 +reg 61: 1 +reg 62: 1 +reg 63: 1 +write_item 0000110000000000010011110000000001111010110000001001001001011100 +write_item 63: 0 +write_item 62: 0 +write_item 61: 0 +write_item 60: 0 +write_item 59: 1 +write_item 58: 1 +write_item 57: 0 +write_item 56: 0 +write_item 55: 0 +write_item 54: 0 +write_item 53: 0 +write_item 52: 0 +write_item 51: 0 +write_item 50: 0 +write_item 49: 0 +write_item 48: 0 +write_item 47: 0 +write_item 46: 1 +write_item 45: 0 +write_item 44: 0 +write_item 43: 1 +write_item 42: 1 +write_item 41: 1 +write_item 40: 1 +write_item 39: 0 +write_item 38: 0 +write_item 37: 0 +write_item 36: 0 +write_item 35: 0 +write_item 34: 0 +write_item 33: 0 +write_item 32: 0 +write_item 31: 0 +write_item 30: 1 +write_item 29: 1 +write_item 28: 1 +write_item 27: 1 +write_item 26: 0 +write_item 25: 1 +write_item 24: 0 +write_item 23: 1 +write_item 22: 1 +write_item 21: 0 +write_item 20: 0 +write_item 19: 0 +write_item 18: 0 +write_item 17: 0 +write_item 16: 0 +write_item 15: 1 +write_item 14: 0 +write_item 13: 0 +write_item 12: 1 +write_item 11: 0 +write_item 10: 0 +write_item 9: 1 +write_item 8: 0 +write_item 7: 0 +write_item 6: 1 +write_item 5: 0 +write_item 4: 1 +write_item 3: 1 +write_item 2: 1 +write_item 1: 0 +write_item 0: 0 +reg 0: 0 +reg 1: 0 +reg 2: 0 +reg 3: 0 +reg 4: 1 +reg 5: 1 +reg 6: 0 +reg 7: 0 +reg 8: 0 +reg 9: 0 +reg 10: 0 +reg 11: 0 +reg 12: 0 +reg 13: 0 +reg 14: 0 +reg 15: 0 +reg 16: 0 +reg 17: 1 +reg 18: 0 +reg 19: 0 +reg 20: 1 +reg 21: 1 +reg 22: 1 +reg 23: 1 +reg 24: 0 +reg 25: 0 +reg 26: 0 +reg 27: 0 +reg 28: 0 +reg 29: 0 +reg 30: 0 +reg 31: 0 +reg 32: 0 +reg 33: 1 +reg 34: 1 +reg 35: 1 +reg 36: 1 +reg 37: 0 +reg 38: 1 +reg 39: 0 +reg 40: 1 +reg 41: 1 +reg 42: 0 +reg 43: 0 +reg 44: 0 +reg 45: 0 +reg 46: 0 +reg 47: 0 +reg 48: 1 +reg 49: 0 +reg 50: 0 +reg 51: 1 +reg 52: 0 +reg 53: 0 +reg 54: 1 +reg 55: 0 +reg 56: 0 +reg 57: 1 +reg 58: 0 +reg 59: 1 +reg 60: 1 +reg 61: 1 +reg 62: 0 +reg 63: 0 +write_item 0000110000000000010100000000000000000000000000000000000000000001 +write_item 63: 0 +write_item 62: 0 +write_item 61: 0 +write_item 60: 0 +write_item 59: 1 +write_item 58: 1 +write_item 57: 0 +write_item 56: 0 +write_item 55: 0 +write_item 54: 0 +write_item 53: 0 +write_item 52: 0 +write_item 51: 0 +write_item 50: 0 +write_item 49: 0 +write_item 48: 0 +write_item 47: 0 +write_item 46: 1 +write_item 45: 0 +write_item 44: 1 +write_item 43: 0 +write_item 42: 0 +write_item 41: 0 +write_item 40: 0 +write_item 39: 0 +write_item 38: 0 +write_item 37: 0 +write_item 36: 0 +write_item 35: 0 +write_item 34: 0 +write_item 33: 0 +write_item 32: 0 +write_item 31: 0 +write_item 30: 0 +write_item 29: 0 +write_item 28: 0 +write_item 27: 0 +write_item 26: 0 +write_item 25: 0 +write_item 24: 0 +write_item 23: 0 +write_item 22: 0 +write_item 21: 0 +write_item 20: 0 +write_item 19: 0 +write_item 18: 0 +write_item 17: 0 +write_item 16: 0 +write_item 15: 0 +write_item 14: 0 +write_item 13: 0 +write_item 12: 0 +write_item 11: 0 +write_item 10: 0 +write_item 9: 0 +write_item 8: 0 +write_item 7: 0 +write_item 6: 0 +write_item 5: 0 +write_item 4: 0 +write_item 3: 0 +write_item 2: 0 +write_item 1: 0 +write_item 0: 1 +reg 0: 0 +reg 1: 0 +reg 2: 0 +reg 3: 0 +reg 4: 1 +reg 5: 1 +reg 6: 0 +reg 7: 0 +reg 8: 0 +reg 9: 0 +reg 10: 0 +reg 11: 0 +reg 12: 0 +reg 13: 0 +reg 14: 0 +reg 15: 0 +reg 16: 0 +reg 17: 1 +reg 18: 0 +reg 19: 1 +reg 20: 0 +reg 21: 0 +reg 22: 0 +reg 23: 0 +reg 24: 0 +reg 25: 0 +reg 26: 0 +reg 27: 0 +reg 28: 0 +reg 29: 0 +reg 30: 0 +reg 31: 0 +reg 32: 0 +reg 33: 0 +reg 34: 0 +reg 35: 0 +reg 36: 0 +reg 37: 0 +reg 38: 0 +reg 39: 0 +reg 40: 0 +reg 41: 0 +reg 42: 0 +reg 43: 0 +reg 44: 0 +reg 45: 0 +reg 46: 0 +reg 47: 0 +reg 48: 0 +reg 49: 0 +reg 50: 0 +reg 51: 0 +reg 52: 0 +reg 53: 0 +reg 54: 0 +reg 55: 0 +reg 56: 0 +reg 57: 0 +reg 58: 0 +reg 59: 0 +reg 60: 0 +reg 61: 0 +reg 62: 0 +reg 63: 1 +write_item 0000110000000000010100010000000001100110011100111010100100011100 +write_item 63: 0 +write_item 62: 0 +write_item 61: 0 +write_item 60: 0 +write_item 59: 1 +write_item 58: 1 +write_item 57: 0 +write_item 56: 0 +write_item 55: 0 +write_item 54: 0 +write_item 53: 0 +write_item 52: 0 +write_item 51: 0 +write_item 50: 0 +write_item 49: 0 +write_item 48: 0 +write_item 47: 0 +write_item 46: 1 +write_item 45: 0 +write_item 44: 1 +write_item 43: 0 +write_item 42: 0 +write_item 41: 0 +write_item 40: 1 +write_item 39: 0 +write_item 38: 0 +write_item 37: 0 +write_item 36: 0 +write_item 35: 0 +write_item 34: 0 +write_item 33: 0 +write_item 32: 0 +write_item 31: 0 +write_item 30: 1 +write_item 29: 1 +write_item 28: 0 +write_item 27: 0 +write_item 26: 1 +write_item 25: 1 +write_item 24: 0 +write_item 23: 0 +write_item 22: 1 +write_item 21: 1 +write_item 20: 1 +write_item 19: 0 +write_item 18: 0 +write_item 17: 1 +write_item 16: 1 +write_item 15: 1 +write_item 14: 0 +write_item 13: 1 +write_item 12: 0 +write_item 11: 1 +write_item 10: 0 +write_item 9: 0 +write_item 8: 1 +write_item 7: 0 +write_item 6: 0 +write_item 5: 0 +write_item 4: 1 +write_item 3: 1 +write_item 2: 1 +write_item 1: 0 +write_item 0: 0 +reg 0: 0 +reg 1: 0 +reg 2: 0 +reg 3: 0 +reg 4: 1 +reg 5: 1 +reg 6: 0 +reg 7: 0 +reg 8: 0 +reg 9: 0 +reg 10: 0 +reg 11: 0 +reg 12: 0 +reg 13: 0 +reg 14: 0 +reg 15: 0 +reg 16: 0 +reg 17: 1 +reg 18: 0 +reg 19: 1 +reg 20: 0 +reg 21: 0 +reg 22: 0 +reg 23: 1 +reg 24: 0 +reg 25: 0 +reg 26: 0 +reg 27: 0 +reg 28: 0 +reg 29: 0 +reg 30: 0 +reg 31: 0 +reg 32: 0 +reg 33: 1 +reg 34: 1 +reg 35: 0 +reg 36: 0 +reg 37: 1 +reg 38: 1 +reg 39: 0 +reg 40: 0 +reg 41: 1 +reg 42: 1 +reg 43: 1 +reg 44: 0 +reg 45: 0 +reg 46: 1 +reg 47: 1 +reg 48: 1 +reg 49: 0 +reg 50: 1 +reg 51: 0 +reg 52: 1 +reg 53: 0 +reg 54: 0 +reg 55: 1 +reg 56: 0 +reg 57: 0 +reg 58: 0 +reg 59: 1 +reg 60: 1 +reg 61: 1 +reg 62: 0 +reg 63: 0 +write_item 0000110000000000010100100000000000000000000000000000000000000000 +write_item 63: 0 +write_item 62: 0 +write_item 61: 0 +write_item 60: 0 +write_item 59: 1 +write_item 58: 1 +write_item 57: 0 +write_item 56: 0 +write_item 55: 0 +write_item 54: 0 +write_item 53: 0 +write_item 52: 0 +write_item 51: 0 +write_item 50: 0 +write_item 49: 0 +write_item 48: 0 +write_item 47: 0 +write_item 46: 1 +write_item 45: 0 +write_item 44: 1 +write_item 43: 0 +write_item 42: 0 +write_item 41: 1 +write_item 40: 0 +write_item 39: 0 +write_item 38: 0 +write_item 37: 0 +write_item 36: 0 +write_item 35: 0 +write_item 34: 0 +write_item 33: 0 +write_item 32: 0 +write_item 31: 0 +write_item 30: 0 +write_item 29: 0 +write_item 28: 0 +write_item 27: 0 +write_item 26: 0 +write_item 25: 0 +write_item 24: 0 +write_item 23: 0 +write_item 22: 0 +write_item 21: 0 +write_item 20: 0 +write_item 19: 0 +write_item 18: 0 +write_item 17: 0 +write_item 16: 0 +write_item 15: 0 +write_item 14: 0 +write_item 13: 0 +write_item 12: 0 +write_item 11: 0 +write_item 10: 0 +write_item 9: 0 +write_item 8: 0 +write_item 7: 0 +write_item 6: 0 +write_item 5: 0 +write_item 4: 0 +write_item 3: 0 +write_item 2: 0 +write_item 1: 0 +write_item 0: 0 +reg 0: 0 +reg 1: 0 +reg 2: 0 +reg 3: 0 +reg 4: 1 +reg 5: 1 +reg 6: 0 +reg 7: 0 +reg 8: 0 +reg 9: 0 +reg 10: 0 +reg 11: 0 +reg 12: 0 +reg 13: 0 +reg 14: 0 +reg 15: 0 +reg 16: 0 +reg 17: 1 +reg 18: 0 +reg 19: 1 +reg 20: 0 +reg 21: 0 +reg 22: 1 +reg 23: 0 +reg 24: 0 +reg 25: 0 +reg 26: 0 +reg 27: 0 +reg 28: 0 +reg 29: 0 +reg 30: 0 +reg 31: 0 +reg 32: 0 +reg 33: 0 +reg 34: 0 +reg 35: 0 +reg 36: 0 +reg 37: 0 +reg 38: 0 +reg 39: 0 +reg 40: 0 +reg 41: 0 +reg 42: 0 +reg 43: 0 +reg 44: 0 +reg 45: 0 +reg 46: 0 +reg 47: 0 +reg 48: 0 +reg 49: 0 +reg 50: 0 +reg 51: 0 +reg 52: 0 +reg 53: 0 +reg 54: 0 +reg 55: 0 +reg 56: 0 +reg 57: 0 +reg 58: 0 +reg 59: 0 +reg 60: 0 +reg 61: 0 +reg 62: 0 +reg 63: 0 +write_item 0000110000000000010100110000000000010011110000010001101000001011 +write_item 63: 0 +write_item 62: 0 +write_item 61: 0 +write_item 60: 0 +write_item 59: 1 +write_item 58: 1 +write_item 57: 0 +write_item 56: 0 +write_item 55: 0 +write_item 54: 0 +write_item 53: 0 +write_item 52: 0 +write_item 51: 0 +write_item 50: 0 +write_item 49: 0 +write_item 48: 0 +write_item 47: 0 +write_item 46: 1 +write_item 45: 0 +write_item 44: 1 +write_item 43: 0 +write_item 42: 0 +write_item 41: 1 +write_item 40: 1 +write_item 39: 0 +write_item 38: 0 +write_item 37: 0 +write_item 36: 0 +write_item 35: 0 +write_item 34: 0 +write_item 33: 0 +write_item 32: 0 +write_item 31: 0 +write_item 30: 0 +write_item 29: 0 +write_item 28: 1 +write_item 27: 0 +write_item 26: 0 +write_item 25: 1 +write_item 24: 1 +write_item 23: 1 +write_item 22: 1 +write_item 21: 0 +write_item 20: 0 +write_item 19: 0 +write_item 18: 0 +write_item 17: 0 +write_item 16: 1 +write_item 15: 0 +write_item 14: 0 +write_item 13: 0 +write_item 12: 1 +write_item 11: 1 +write_item 10: 0 +write_item 9: 1 +write_item 8: 0 +write_item 7: 0 +write_item 6: 0 +write_item 5: 0 +write_item 4: 0 +write_item 3: 1 +write_item 2: 0 +write_item 1: 1 +write_item 0: 1 +reg 0: 0 +reg 1: 0 +reg 2: 0 +reg 3: 0 +reg 4: 1 +reg 5: 1 +reg 6: 0 +reg 7: 0 +reg 8: 0 +reg 9: 0 +reg 10: 0 +reg 11: 0 +reg 12: 0 +reg 13: 0 +reg 14: 0 +reg 15: 0 +reg 16: 0 +reg 17: 1 +reg 18: 0 +reg 19: 1 +reg 20: 0 +reg 21: 0 +reg 22: 1 +reg 23: 1 +reg 24: 0 +reg 25: 0 +reg 26: 0 +reg 27: 0 +reg 28: 0 +reg 29: 0 +reg 30: 0 +reg 31: 0 +reg 32: 0 +reg 33: 0 +reg 34: 0 +reg 35: 1 +reg 36: 0 +reg 37: 0 +reg 38: 1 +reg 39: 1 +reg 40: 1 +reg 41: 1 +reg 42: 0 +reg 43: 0 +reg 44: 0 +reg 45: 0 +reg 46: 0 +reg 47: 1 +reg 48: 0 +reg 49: 0 +reg 50: 0 +reg 51: 1 +reg 52: 1 +reg 53: 0 +reg 54: 1 +reg 55: 0 +reg 56: 0 +reg 57: 0 +reg 58: 0 +reg 59: 0 +reg 60: 1 +reg 61: 0 +reg 62: 1 +reg 63: 1 +write_item 0000110000000000010101000000000000000000000000000000000000000000 +write_item 63: 0 +write_item 62: 0 +write_item 61: 0 +write_item 60: 0 +write_item 59: 1 +write_item 58: 1 +write_item 57: 0 +write_item 56: 0 +write_item 55: 0 +write_item 54: 0 +write_item 53: 0 +write_item 52: 0 +write_item 51: 0 +write_item 50: 0 +write_item 49: 0 +write_item 48: 0 +write_item 47: 0 +write_item 46: 1 +write_item 45: 0 +write_item 44: 1 +write_item 43: 0 +write_item 42: 1 +write_item 41: 0 +write_item 40: 0 +write_item 39: 0 +write_item 38: 0 +write_item 37: 0 +write_item 36: 0 +write_item 35: 0 +write_item 34: 0 +write_item 33: 0 +write_item 32: 0 +write_item 31: 0 +write_item 30: 0 +write_item 29: 0 +write_item 28: 0 +write_item 27: 0 +write_item 26: 0 +write_item 25: 0 +write_item 24: 0 +write_item 23: 0 +write_item 22: 0 +write_item 21: 0 +write_item 20: 0 +write_item 19: 0 +write_item 18: 0 +write_item 17: 0 +write_item 16: 0 +write_item 15: 0 +write_item 14: 0 +write_item 13: 0 +write_item 12: 0 +write_item 11: 0 +write_item 10: 0 +write_item 9: 0 +write_item 8: 0 +write_item 7: 0 +write_item 6: 0 +write_item 5: 0 +write_item 4: 0 +write_item 3: 0 +write_item 2: 0 +write_item 1: 0 +write_item 0: 0 +reg 0: 0 +reg 1: 0 +reg 2: 0 +reg 3: 0 +reg 4: 1 +reg 5: 1 +reg 6: 0 +reg 7: 0 +reg 8: 0 +reg 9: 0 +reg 10: 0 +reg 11: 0 +reg 12: 0 +reg 13: 0 +reg 14: 0 +reg 15: 0 +reg 16: 0 +reg 17: 1 +reg 18: 0 +reg 19: 1 +reg 20: 0 +reg 21: 1 +reg 22: 0 +reg 23: 0 +reg 24: 0 +reg 25: 0 +reg 26: 0 +reg 27: 0 +reg 28: 0 +reg 29: 0 +reg 30: 0 +reg 31: 0 +reg 32: 0 +reg 33: 0 +reg 34: 0 +reg 35: 0 +reg 36: 0 +reg 37: 0 +reg 38: 0 +reg 39: 0 +reg 40: 0 +reg 41: 0 +reg 42: 0 +reg 43: 0 +reg 44: 0 +reg 45: 0 +reg 46: 0 +reg 47: 0 +reg 48: 0 +reg 49: 0 +reg 50: 0 +reg 51: 0 +reg 52: 0 +reg 53: 0 +reg 54: 0 +reg 55: 0 +reg 56: 0 +reg 57: 0 +reg 58: 0 +reg 59: 0 +reg 60: 0 +reg 61: 0 +reg 62: 0 +reg 63: 0 +write_item 0000110000000000010101010000000000000000000000000000000000000000 +write_item 63: 0 +write_item 62: 0 +write_item 61: 0 +write_item 60: 0 +write_item 59: 1 +write_item 58: 1 +write_item 57: 0 +write_item 56: 0 +write_item 55: 0 +write_item 54: 0 +write_item 53: 0 +write_item 52: 0 +write_item 51: 0 +write_item 50: 0 +write_item 49: 0 +write_item 48: 0 +write_item 47: 0 +write_item 46: 1 +write_item 45: 0 +write_item 44: 1 +write_item 43: 0 +write_item 42: 1 +write_item 41: 0 +write_item 40: 1 +write_item 39: 0 +write_item 38: 0 +write_item 37: 0 +write_item 36: 0 +write_item 35: 0 +write_item 34: 0 +write_item 33: 0 +write_item 32: 0 +write_item 31: 0 +write_item 30: 0 +write_item 29: 0 +write_item 28: 0 +write_item 27: 0 +write_item 26: 0 +write_item 25: 0 +write_item 24: 0 +write_item 23: 0 +write_item 22: 0 +write_item 21: 0 +write_item 20: 0 +write_item 19: 0 +write_item 18: 0 +write_item 17: 0 +write_item 16: 0 +write_item 15: 0 +write_item 14: 0 +write_item 13: 0 +write_item 12: 0 +write_item 11: 0 +write_item 10: 0 +write_item 9: 0 +write_item 8: 0 +write_item 7: 0 +write_item 6: 0 +write_item 5: 0 +write_item 4: 0 +write_item 3: 0 +write_item 2: 0 +write_item 1: 0 +write_item 0: 0 +reg 0: 0 +reg 1: 0 +reg 2: 0 +reg 3: 0 +reg 4: 1 +reg 5: 1 +reg 6: 0 +reg 7: 0 +reg 8: 0 +reg 9: 0 +reg 10: 0 +reg 11: 0 +reg 12: 0 +reg 13: 0 +reg 14: 0 +reg 15: 0 +reg 16: 0 +reg 17: 1 +reg 18: 0 +reg 19: 1 +reg 20: 0 +reg 21: 1 +reg 22: 0 +reg 23: 1 +reg 24: 0 +reg 25: 0 +reg 26: 0 +reg 27: 0 +reg 28: 0 +reg 29: 0 +reg 30: 0 +reg 31: 0 +reg 32: 0 +reg 33: 0 +reg 34: 0 +reg 35: 0 +reg 36: 0 +reg 37: 0 +reg 38: 0 +reg 39: 0 +reg 40: 0 +reg 41: 0 +reg 42: 0 +reg 43: 0 +reg 44: 0 +reg 45: 0 +reg 46: 0 +reg 47: 0 +reg 48: 0 +reg 49: 0 +reg 50: 0 +reg 51: 0 +reg 52: 0 +reg 53: 0 +reg 54: 0 +reg 55: 0 +reg 56: 0 +reg 57: 0 +reg 58: 0 +reg 59: 0 +reg 60: 0 +reg 61: 0 +reg 62: 0 +reg 63: 0 +write_item 0000110000000000010101100000000000000000000000000000000000000000 +write_item 63: 0 +write_item 62: 0 +write_item 61: 0 +write_item 60: 0 +write_item 59: 1 +write_item 58: 1 +write_item 57: 0 +write_item 56: 0 +write_item 55: 0 +write_item 54: 0 +write_item 53: 0 +write_item 52: 0 +write_item 51: 0 +write_item 50: 0 +write_item 49: 0 +write_item 48: 0 +write_item 47: 0 +write_item 46: 1 +write_item 45: 0 +write_item 44: 1 +write_item 43: 0 +write_item 42: 1 +write_item 41: 1 +write_item 40: 0 +write_item 39: 0 +write_item 38: 0 +write_item 37: 0 +write_item 36: 0 +write_item 35: 0 +write_item 34: 0 +write_item 33: 0 +write_item 32: 0 +write_item 31: 0 +write_item 30: 0 +write_item 29: 0 +write_item 28: 0 +write_item 27: 0 +write_item 26: 0 +write_item 25: 0 +write_item 24: 0 +write_item 23: 0 +write_item 22: 0 +write_item 21: 0 +write_item 20: 0 +write_item 19: 0 +write_item 18: 0 +write_item 17: 0 +write_item 16: 0 +write_item 15: 0 +write_item 14: 0 +write_item 13: 0 +write_item 12: 0 +write_item 11: 0 +write_item 10: 0 +write_item 9: 0 +write_item 8: 0 +write_item 7: 0 +write_item 6: 0 +write_item 5: 0 +write_item 4: 0 +write_item 3: 0 +write_item 2: 0 +write_item 1: 0 +write_item 0: 0 +reg 0: 0 +reg 1: 0 +reg 2: 0 +reg 3: 0 +reg 4: 1 +reg 5: 1 +reg 6: 0 +reg 7: 0 +reg 8: 0 +reg 9: 0 +reg 10: 0 +reg 11: 0 +reg 12: 0 +reg 13: 0 +reg 14: 0 +reg 15: 0 +reg 16: 0 +reg 17: 1 +reg 18: 0 +reg 19: 1 +reg 20: 0 +reg 21: 1 +reg 22: 1 +reg 23: 0 +reg 24: 0 +reg 25: 0 +reg 26: 0 +reg 27: 0 +reg 28: 0 +reg 29: 0 +reg 30: 0 +reg 31: 0 +reg 32: 0 +reg 33: 0 +reg 34: 0 +reg 35: 0 +reg 36: 0 +reg 37: 0 +reg 38: 0 +reg 39: 0 +reg 40: 0 +reg 41: 0 +reg 42: 0 +reg 43: 0 +reg 44: 0 +reg 45: 0 +reg 46: 0 +reg 47: 0 +reg 48: 0 +reg 49: 0 +reg 50: 0 +reg 51: 0 +reg 52: 0 +reg 53: 0 +reg 54: 0 +reg 55: 0 +reg 56: 0 +reg 57: 0 +reg 58: 0 +reg 59: 0 +reg 60: 0 +reg 61: 0 +reg 62: 0 +reg 63: 0 +write_item 0000110000000000010101110000000000000000000000000000000000000000 +write_item 63: 0 +write_item 62: 0 +write_item 61: 0 +write_item 60: 0 +write_item 59: 1 +write_item 58: 1 +write_item 57: 0 +write_item 56: 0 +write_item 55: 0 +write_item 54: 0 +write_item 53: 0 +write_item 52: 0 +write_item 51: 0 +write_item 50: 0 +write_item 49: 0 +write_item 48: 0 +write_item 47: 0 +write_item 46: 1 +write_item 45: 0 +write_item 44: 1 +write_item 43: 0 +write_item 42: 1 +write_item 41: 1 +write_item 40: 1 +write_item 39: 0 +write_item 38: 0 +write_item 37: 0 +write_item 36: 0 +write_item 35: 0 +write_item 34: 0 +write_item 33: 0 +write_item 32: 0 +write_item 31: 0 +write_item 30: 0 +write_item 29: 0 +write_item 28: 0 +write_item 27: 0 +write_item 26: 0 +write_item 25: 0 +write_item 24: 0 +write_item 23: 0 +write_item 22: 0 +write_item 21: 0 +write_item 20: 0 +write_item 19: 0 +write_item 18: 0 +write_item 17: 0 +write_item 16: 0 +write_item 15: 0 +write_item 14: 0 +write_item 13: 0 +write_item 12: 0 +write_item 11: 0 +write_item 10: 0 +write_item 9: 0 +write_item 8: 0 +write_item 7: 0 +write_item 6: 0 +write_item 5: 0 +write_item 4: 0 +write_item 3: 0 +write_item 2: 0 +write_item 1: 0 +write_item 0: 0 +reg 0: 0 +reg 1: 0 +reg 2: 0 +reg 3: 0 +reg 4: 1 +reg 5: 1 +reg 6: 0 +reg 7: 0 +reg 8: 0 +reg 9: 0 +reg 10: 0 +reg 11: 0 +reg 12: 0 +reg 13: 0 +reg 14: 0 +reg 15: 0 +reg 16: 0 +reg 17: 1 +reg 18: 0 +reg 19: 1 +reg 20: 0 +reg 21: 1 +reg 22: 1 +reg 23: 1 +reg 24: 0 +reg 25: 0 +reg 26: 0 +reg 27: 0 +reg 28: 0 +reg 29: 0 +reg 30: 0 +reg 31: 0 +reg 32: 0 +reg 33: 0 +reg 34: 0 +reg 35: 0 +reg 36: 0 +reg 37: 0 +reg 38: 0 +reg 39: 0 +reg 40: 0 +reg 41: 0 +reg 42: 0 +reg 43: 0 +reg 44: 0 +reg 45: 0 +reg 46: 0 +reg 47: 0 +reg 48: 0 +reg 49: 0 +reg 50: 0 +reg 51: 0 +reg 52: 0 +reg 53: 0 +reg 54: 0 +reg 55: 0 +reg 56: 0 +reg 57: 0 +reg 58: 0 +reg 59: 0 +reg 60: 0 +reg 61: 0 +reg 62: 0 +reg 63: 0 +write_item 0000110000000000010110000000000000000000000000000000000000000000 +write_item 63: 0 +write_item 62: 0 +write_item 61: 0 +write_item 60: 0 +write_item 59: 1 +write_item 58: 1 +write_item 57: 0 +write_item 56: 0 +write_item 55: 0 +write_item 54: 0 +write_item 53: 0 +write_item 52: 0 +write_item 51: 0 +write_item 50: 0 +write_item 49: 0 +write_item 48: 0 +write_item 47: 0 +write_item 46: 1 +write_item 45: 0 +write_item 44: 1 +write_item 43: 1 +write_item 42: 0 +write_item 41: 0 +write_item 40: 0 +write_item 39: 0 +write_item 38: 0 +write_item 37: 0 +write_item 36: 0 +write_item 35: 0 +write_item 34: 0 +write_item 33: 0 +write_item 32: 0 +write_item 31: 0 +write_item 30: 0 +write_item 29: 0 +write_item 28: 0 +write_item 27: 0 +write_item 26: 0 +write_item 25: 0 +write_item 24: 0 +write_item 23: 0 +write_item 22: 0 +write_item 21: 0 +write_item 20: 0 +write_item 19: 0 +write_item 18: 0 +write_item 17: 0 +write_item 16: 0 +write_item 15: 0 +write_item 14: 0 +write_item 13: 0 +write_item 12: 0 +write_item 11: 0 +write_item 10: 0 +write_item 9: 0 +write_item 8: 0 +write_item 7: 0 +write_item 6: 0 +write_item 5: 0 +write_item 4: 0 +write_item 3: 0 +write_item 2: 0 +write_item 1: 0 +write_item 0: 0 +reg 0: 0 +reg 1: 0 +reg 2: 0 +reg 3: 0 +reg 4: 1 +reg 5: 1 +reg 6: 0 +reg 7: 0 +reg 8: 0 +reg 9: 0 +reg 10: 0 +reg 11: 0 +reg 12: 0 +reg 13: 0 +reg 14: 0 +reg 15: 0 +reg 16: 0 +reg 17: 1 +reg 18: 0 +reg 19: 1 +reg 20: 1 +reg 21: 0 +reg 22: 0 +reg 23: 0 +reg 24: 0 +reg 25: 0 +reg 26: 0 +reg 27: 0 +reg 28: 0 +reg 29: 0 +reg 30: 0 +reg 31: 0 +reg 32: 0 +reg 33: 0 +reg 34: 0 +reg 35: 0 +reg 36: 0 +reg 37: 0 +reg 38: 0 +reg 39: 0 +reg 40: 0 +reg 41: 0 +reg 42: 0 +reg 43: 0 +reg 44: 0 +reg 45: 0 +reg 46: 0 +reg 47: 0 +reg 48: 0 +reg 49: 0 +reg 50: 0 +reg 51: 0 +reg 52: 0 +reg 53: 0 +reg 54: 0 +reg 55: 0 +reg 56: 0 +reg 57: 0 +reg 58: 0 +reg 59: 0 +reg 60: 0 +reg 61: 0 +reg 62: 0 +reg 63: 0 +write_item 0000110000000000010110010000000000000000000000000000000000000000 +write_item 63: 0 +write_item 62: 0 +write_item 61: 0 +write_item 60: 0 +write_item 59: 1 +write_item 58: 1 +write_item 57: 0 +write_item 56: 0 +write_item 55: 0 +write_item 54: 0 +write_item 53: 0 +write_item 52: 0 +write_item 51: 0 +write_item 50: 0 +write_item 49: 0 +write_item 48: 0 +write_item 47: 0 +write_item 46: 1 +write_item 45: 0 +write_item 44: 1 +write_item 43: 1 +write_item 42: 0 +write_item 41: 0 +write_item 40: 1 +write_item 39: 0 +write_item 38: 0 +write_item 37: 0 +write_item 36: 0 +write_item 35: 0 +write_item 34: 0 +write_item 33: 0 +write_item 32: 0 +write_item 31: 0 +write_item 30: 0 +write_item 29: 0 +write_item 28: 0 +write_item 27: 0 +write_item 26: 0 +write_item 25: 0 +write_item 24: 0 +write_item 23: 0 +write_item 22: 0 +write_item 21: 0 +write_item 20: 0 +write_item 19: 0 +write_item 18: 0 +write_item 17: 0 +write_item 16: 0 +write_item 15: 0 +write_item 14: 0 +write_item 13: 0 +write_item 12: 0 +write_item 11: 0 +write_item 10: 0 +write_item 9: 0 +write_item 8: 0 +write_item 7: 0 +write_item 6: 0 +write_item 5: 0 +write_item 4: 0 +write_item 3: 0 +write_item 2: 0 +write_item 1: 0 +write_item 0: 0 +reg 0: 0 +reg 1: 0 +reg 2: 0 +reg 3: 0 +reg 4: 1 +reg 5: 1 +reg 6: 0 +reg 7: 0 +reg 8: 0 +reg 9: 0 +reg 10: 0 +reg 11: 0 +reg 12: 0 +reg 13: 0 +reg 14: 0 +reg 15: 0 +reg 16: 0 +reg 17: 1 +reg 18: 0 +reg 19: 1 +reg 20: 1 +reg 21: 0 +reg 22: 0 +reg 23: 1 +reg 24: 0 +reg 25: 0 +reg 26: 0 +reg 27: 0 +reg 28: 0 +reg 29: 0 +reg 30: 0 +reg 31: 0 +reg 32: 0 +reg 33: 0 +reg 34: 0 +reg 35: 0 +reg 36: 0 +reg 37: 0 +reg 38: 0 +reg 39: 0 +reg 40: 0 +reg 41: 0 +reg 42: 0 +reg 43: 0 +reg 44: 0 +reg 45: 0 +reg 46: 0 +reg 47: 0 +reg 48: 0 +reg 49: 0 +reg 50: 0 +reg 51: 0 +reg 52: 0 +reg 53: 0 +reg 54: 0 +reg 55: 0 +reg 56: 0 +reg 57: 0 +reg 58: 0 +reg 59: 0 +reg 60: 0 +reg 61: 0 +reg 62: 0 +reg 63: 0 +write_item 0000110000000000010110100000000011111111111111111111111111111111 +write_item 63: 0 +write_item 62: 0 +write_item 61: 0 +write_item 60: 0 +write_item 59: 1 +write_item 58: 1 +write_item 57: 0 +write_item 56: 0 +write_item 55: 0 +write_item 54: 0 +write_item 53: 0 +write_item 52: 0 +write_item 51: 0 +write_item 50: 0 +write_item 49: 0 +write_item 48: 0 +write_item 47: 0 +write_item 46: 1 +write_item 45: 0 +write_item 44: 1 +write_item 43: 1 +write_item 42: 0 +write_item 41: 1 +write_item 40: 0 +write_item 39: 0 +write_item 38: 0 +write_item 37: 0 +write_item 36: 0 +write_item 35: 0 +write_item 34: 0 +write_item 33: 0 +write_item 32: 0 +write_item 31: 1 +write_item 30: 1 +write_item 29: 1 +write_item 28: 1 +write_item 27: 1 +write_item 26: 1 +write_item 25: 1 +write_item 24: 1 +write_item 23: 1 +write_item 22: 1 +write_item 21: 1 +write_item 20: 1 +write_item 19: 1 +write_item 18: 1 +write_item 17: 1 +write_item 16: 1 +write_item 15: 1 +write_item 14: 1 +write_item 13: 1 +write_item 12: 1 +write_item 11: 1 +write_item 10: 1 +write_item 9: 1 +write_item 8: 1 +write_item 7: 1 +write_item 6: 1 +write_item 5: 1 +write_item 4: 1 +write_item 3: 1 +write_item 2: 1 +write_item 1: 1 +write_item 0: 1 +reg 0: 0 +reg 1: 0 +reg 2: 0 +reg 3: 0 +reg 4: 1 +reg 5: 1 +reg 6: 0 +reg 7: 0 +reg 8: 0 +reg 9: 0 +reg 10: 0 +reg 11: 0 +reg 12: 0 +reg 13: 0 +reg 14: 0 +reg 15: 0 +reg 16: 0 +reg 17: 1 +reg 18: 0 +reg 19: 1 +reg 20: 1 +reg 21: 0 +reg 22: 1 +reg 23: 0 +reg 24: 0 +reg 25: 0 +reg 26: 0 +reg 27: 0 +reg 28: 0 +reg 29: 0 +reg 30: 0 +reg 31: 0 +reg 32: 1 +reg 33: 1 +reg 34: 1 +reg 35: 1 +reg 36: 1 +reg 37: 1 +reg 38: 1 +reg 39: 1 +reg 40: 1 +reg 41: 1 +reg 42: 1 +reg 43: 1 +reg 44: 1 +reg 45: 1 +reg 46: 1 +reg 47: 1 +reg 48: 1 +reg 49: 1 +reg 50: 1 +reg 51: 1 +reg 52: 1 +reg 53: 1 +reg 54: 1 +reg 55: 1 +reg 56: 1 +reg 57: 1 +reg 58: 1 +reg 59: 1 +reg 60: 1 +reg 61: 1 +reg 62: 1 +reg 63: 1 +write_item 0000110000000000010110110000000001100100000001011100111111111011 +write_item 63: 0 +write_item 62: 0 +write_item 61: 0 +write_item 60: 0 +write_item 59: 1 +write_item 58: 1 +write_item 57: 0 +write_item 56: 0 +write_item 55: 0 +write_item 54: 0 +write_item 53: 0 +write_item 52: 0 +write_item 51: 0 +write_item 50: 0 +write_item 49: 0 +write_item 48: 0 +write_item 47: 0 +write_item 46: 1 +write_item 45: 0 +write_item 44: 1 +write_item 43: 1 +write_item 42: 0 +write_item 41: 1 +write_item 40: 1 +write_item 39: 0 +write_item 38: 0 +write_item 37: 0 +write_item 36: 0 +write_item 35: 0 +write_item 34: 0 +write_item 33: 0 +write_item 32: 0 +write_item 31: 0 +write_item 30: 1 +write_item 29: 1 +write_item 28: 0 +write_item 27: 0 +write_item 26: 1 +write_item 25: 0 +write_item 24: 0 +write_item 23: 0 +write_item 22: 0 +write_item 21: 0 +write_item 20: 0 +write_item 19: 0 +write_item 18: 1 +write_item 17: 0 +write_item 16: 1 +write_item 15: 1 +write_item 14: 1 +write_item 13: 0 +write_item 12: 0 +write_item 11: 1 +write_item 10: 1 +write_item 9: 1 +write_item 8: 1 +write_item 7: 1 +write_item 6: 1 +write_item 5: 1 +write_item 4: 1 +write_item 3: 1 +write_item 2: 0 +write_item 1: 1 +write_item 0: 1 +reg 0: 0 +reg 1: 0 +reg 2: 0 +reg 3: 0 +reg 4: 1 +reg 5: 1 +reg 6: 0 +reg 7: 0 +reg 8: 0 +reg 9: 0 +reg 10: 0 +reg 11: 0 +reg 12: 0 +reg 13: 0 +reg 14: 0 +reg 15: 0 +reg 16: 0 +reg 17: 1 +reg 18: 0 +reg 19: 1 +reg 20: 1 +reg 21: 0 +reg 22: 1 +reg 23: 1 +reg 24: 0 +reg 25: 0 +reg 26: 0 +reg 27: 0 +reg 28: 0 +reg 29: 0 +reg 30: 0 +reg 31: 0 +reg 32: 0 +reg 33: 1 +reg 34: 1 +reg 35: 0 +reg 36: 0 +reg 37: 1 +reg 38: 0 +reg 39: 0 +reg 40: 0 +reg 41: 0 +reg 42: 0 +reg 43: 0 +reg 44: 0 +reg 45: 1 +reg 46: 0 +reg 47: 1 +reg 48: 1 +reg 49: 1 +reg 50: 0 +reg 51: 0 +reg 52: 1 +reg 53: 1 +reg 54: 1 +reg 55: 1 +reg 56: 1 +reg 57: 1 +reg 58: 1 +reg 59: 1 +reg 60: 1 +reg 61: 0 +reg 62: 1 +reg 63: 1 +write_item 0000110000000000010111000000000011111111111111111111111111111110 +write_item 63: 0 +write_item 62: 0 +write_item 61: 0 +write_item 60: 0 +write_item 59: 1 +write_item 58: 1 +write_item 57: 0 +write_item 56: 0 +write_item 55: 0 +write_item 54: 0 +write_item 53: 0 +write_item 52: 0 +write_item 51: 0 +write_item 50: 0 +write_item 49: 0 +write_item 48: 0 +write_item 47: 0 +write_item 46: 1 +write_item 45: 0 +write_item 44: 1 +write_item 43: 1 +write_item 42: 1 +write_item 41: 0 +write_item 40: 0 +write_item 39: 0 +write_item 38: 0 +write_item 37: 0 +write_item 36: 0 +write_item 35: 0 +write_item 34: 0 +write_item 33: 0 +write_item 32: 0 +write_item 31: 1 +write_item 30: 1 +write_item 29: 1 +write_item 28: 1 +write_item 27: 1 +write_item 26: 1 +write_item 25: 1 +write_item 24: 1 +write_item 23: 1 +write_item 22: 1 +write_item 21: 1 +write_item 20: 1 +write_item 19: 1 +write_item 18: 1 +write_item 17: 1 +write_item 16: 1 +write_item 15: 1 +write_item 14: 1 +write_item 13: 1 +write_item 12: 1 +write_item 11: 1 +write_item 10: 1 +write_item 9: 1 +write_item 8: 1 +write_item 7: 1 +write_item 6: 1 +write_item 5: 1 +write_item 4: 1 +write_item 3: 1 +write_item 2: 1 +write_item 1: 1 +write_item 0: 0 +reg 0: 0 +reg 1: 0 +reg 2: 0 +reg 3: 0 +reg 4: 1 +reg 5: 1 +reg 6: 0 +reg 7: 0 +reg 8: 0 +reg 9: 0 +reg 10: 0 +reg 11: 0 +reg 12: 0 +reg 13: 0 +reg 14: 0 +reg 15: 0 +reg 16: 0 +reg 17: 1 +reg 18: 0 +reg 19: 1 +reg 20: 1 +reg 21: 1 +reg 22: 0 +reg 23: 0 +reg 24: 0 +reg 25: 0 +reg 26: 0 +reg 27: 0 +reg 28: 0 +reg 29: 0 +reg 30: 0 +reg 31: 0 +reg 32: 1 +reg 33: 1 +reg 34: 1 +reg 35: 1 +reg 36: 1 +reg 37: 1 +reg 38: 1 +reg 39: 1 +reg 40: 1 +reg 41: 1 +reg 42: 1 +reg 43: 1 +reg 44: 1 +reg 45: 1 +reg 46: 1 +reg 47: 1 +reg 48: 1 +reg 49: 1 +reg 50: 1 +reg 51: 1 +reg 52: 1 +reg 53: 1 +reg 54: 1 +reg 55: 1 +reg 56: 1 +reg 57: 1 +reg 58: 1 +reg 59: 1 +reg 60: 1 +reg 61: 1 +reg 62: 1 +reg 63: 0 +write_item 0000110000000000010111010000000011111110111101011111000111111111 +write_item 63: 0 +write_item 62: 0 +write_item 61: 0 +write_item 60: 0 +write_item 59: 1 +write_item 58: 1 +write_item 57: 0 +write_item 56: 0 +write_item 55: 0 +write_item 54: 0 +write_item 53: 0 +write_item 52: 0 +write_item 51: 0 +write_item 50: 0 +write_item 49: 0 +write_item 48: 0 +write_item 47: 0 +write_item 46: 1 +write_item 45: 0 +write_item 44: 1 +write_item 43: 1 +write_item 42: 1 +write_item 41: 0 +write_item 40: 1 +write_item 39: 0 +write_item 38: 0 +write_item 37: 0 +write_item 36: 0 +write_item 35: 0 +write_item 34: 0 +write_item 33: 0 +write_item 32: 0 +write_item 31: 1 +write_item 30: 1 +write_item 29: 1 +write_item 28: 1 +write_item 27: 1 +write_item 26: 1 +write_item 25: 1 +write_item 24: 0 +write_item 23: 1 +write_item 22: 1 +write_item 21: 1 +write_item 20: 1 +write_item 19: 0 +write_item 18: 1 +write_item 17: 0 +write_item 16: 1 +write_item 15: 1 +write_item 14: 1 +write_item 13: 1 +write_item 12: 1 +write_item 11: 0 +write_item 10: 0 +write_item 9: 0 +write_item 8: 1 +write_item 7: 1 +write_item 6: 1 +write_item 5: 1 +write_item 4: 1 +write_item 3: 1 +write_item 2: 1 +write_item 1: 1 +write_item 0: 1 +reg 0: 0 +reg 1: 0 +reg 2: 0 +reg 3: 0 +reg 4: 1 +reg 5: 1 +reg 6: 0 +reg 7: 0 +reg 8: 0 +reg 9: 0 +reg 10: 0 +reg 11: 0 +reg 12: 0 +reg 13: 0 +reg 14: 0 +reg 15: 0 +reg 16: 0 +reg 17: 1 +reg 18: 0 +reg 19: 1 +reg 20: 1 +reg 21: 1 +reg 22: 0 +reg 23: 1 +reg 24: 0 +reg 25: 0 +reg 26: 0 +reg 27: 0 +reg 28: 0 +reg 29: 0 +reg 30: 0 +reg 31: 0 +reg 32: 1 +reg 33: 1 +reg 34: 1 +reg 35: 1 +reg 36: 1 +reg 37: 1 +reg 38: 1 +reg 39: 0 +reg 40: 1 +reg 41: 1 +reg 42: 1 +reg 43: 1 +reg 44: 0 +reg 45: 1 +reg 46: 0 +reg 47: 1 +reg 48: 1 +reg 49: 1 +reg 50: 1 +reg 51: 1 +reg 52: 0 +reg 53: 0 +reg 54: 0 +reg 55: 1 +reg 56: 1 +reg 57: 1 +reg 58: 1 +reg 59: 1 +reg 60: 1 +reg 61: 1 +reg 62: 1 +reg 63: 1 +write_item 0000110000000000010111100000000000000000000000000000000000000000 +write_item 63: 0 +write_item 62: 0 +write_item 61: 0 +write_item 60: 0 +write_item 59: 1 +write_item 58: 1 +write_item 57: 0 +write_item 56: 0 +write_item 55: 0 +write_item 54: 0 +write_item 53: 0 +write_item 52: 0 +write_item 51: 0 +write_item 50: 0 +write_item 49: 0 +write_item 48: 0 +write_item 47: 0 +write_item 46: 1 +write_item 45: 0 +write_item 44: 1 +write_item 43: 1 +write_item 42: 1 +write_item 41: 1 +write_item 40: 0 +write_item 39: 0 +write_item 38: 0 +write_item 37: 0 +write_item 36: 0 +write_item 35: 0 +write_item 34: 0 +write_item 33: 0 +write_item 32: 0 +write_item 31: 0 +write_item 30: 0 +write_item 29: 0 +write_item 28: 0 +write_item 27: 0 +write_item 26: 0 +write_item 25: 0 +write_item 24: 0 +write_item 23: 0 +write_item 22: 0 +write_item 21: 0 +write_item 20: 0 +write_item 19: 0 +write_item 18: 0 +write_item 17: 0 +write_item 16: 0 +write_item 15: 0 +write_item 14: 0 +write_item 13: 0 +write_item 12: 0 +write_item 11: 0 +write_item 10: 0 +write_item 9: 0 +write_item 8: 0 +write_item 7: 0 +write_item 6: 0 +write_item 5: 0 +write_item 4: 0 +write_item 3: 0 +write_item 2: 0 +write_item 1: 0 +write_item 0: 0 +reg 0: 0 +reg 1: 0 +reg 2: 0 +reg 3: 0 +reg 4: 1 +reg 5: 1 +reg 6: 0 +reg 7: 0 +reg 8: 0 +reg 9: 0 +reg 10: 0 +reg 11: 0 +reg 12: 0 +reg 13: 0 +reg 14: 0 +reg 15: 0 +reg 16: 0 +reg 17: 1 +reg 18: 0 +reg 19: 1 +reg 20: 1 +reg 21: 1 +reg 22: 1 +reg 23: 0 +reg 24: 0 +reg 25: 0 +reg 26: 0 +reg 27: 0 +reg 28: 0 +reg 29: 0 +reg 30: 0 +reg 31: 0 +reg 32: 0 +reg 33: 0 +reg 34: 0 +reg 35: 0 +reg 36: 0 +reg 37: 0 +reg 38: 0 +reg 39: 0 +reg 40: 0 +reg 41: 0 +reg 42: 0 +reg 43: 0 +reg 44: 0 +reg 45: 0 +reg 46: 0 +reg 47: 0 +reg 48: 0 +reg 49: 0 +reg 50: 0 +reg 51: 0 +reg 52: 0 +reg 53: 0 +reg 54: 0 +reg 55: 0 +reg 56: 0 +reg 57: 0 +reg 58: 0 +reg 59: 0 +reg 60: 0 +reg 61: 0 +reg 62: 0 +reg 63: 0 +write_item 0000110000000000010111110000000000000000000000000000000000000000 +write_item 63: 0 +write_item 62: 0 +write_item 61: 0 +write_item 60: 0 +write_item 59: 1 +write_item 58: 1 +write_item 57: 0 +write_item 56: 0 +write_item 55: 0 +write_item 54: 0 +write_item 53: 0 +write_item 52: 0 +write_item 51: 0 +write_item 50: 0 +write_item 49: 0 +write_item 48: 0 +write_item 47: 0 +write_item 46: 1 +write_item 45: 0 +write_item 44: 1 +write_item 43: 1 +write_item 42: 1 +write_item 41: 1 +write_item 40: 1 +write_item 39: 0 +write_item 38: 0 +write_item 37: 0 +write_item 36: 0 +write_item 35: 0 +write_item 34: 0 +write_item 33: 0 +write_item 32: 0 +write_item 31: 0 +write_item 30: 0 +write_item 29: 0 +write_item 28: 0 +write_item 27: 0 +write_item 26: 0 +write_item 25: 0 +write_item 24: 0 +write_item 23: 0 +write_item 22: 0 +write_item 21: 0 +write_item 20: 0 +write_item 19: 0 +write_item 18: 0 +write_item 17: 0 +write_item 16: 0 +write_item 15: 0 +write_item 14: 0 +write_item 13: 0 +write_item 12: 0 +write_item 11: 0 +write_item 10: 0 +write_item 9: 0 +write_item 8: 0 +write_item 7: 0 +write_item 6: 0 +write_item 5: 0 +write_item 4: 0 +write_item 3: 0 +write_item 2: 0 +write_item 1: 0 +write_item 0: 0 +reg 0: 0 +reg 1: 0 +reg 2: 0 +reg 3: 0 +reg 4: 1 +reg 5: 1 +reg 6: 0 +reg 7: 0 +reg 8: 0 +reg 9: 0 +reg 10: 0 +reg 11: 0 +reg 12: 0 +reg 13: 0 +reg 14: 0 +reg 15: 0 +reg 16: 0 +reg 17: 1 +reg 18: 0 +reg 19: 1 +reg 20: 1 +reg 21: 1 +reg 22: 1 +reg 23: 1 +reg 24: 0 +reg 25: 0 +reg 26: 0 +reg 27: 0 +reg 28: 0 +reg 29: 0 +reg 30: 0 +reg 31: 0 +reg 32: 0 +reg 33: 0 +reg 34: 0 +reg 35: 0 +reg 36: 0 +reg 37: 0 +reg 38: 0 +reg 39: 0 +reg 40: 0 +reg 41: 0 +reg 42: 0 +reg 43: 0 +reg 44: 0 +reg 45: 0 +reg 46: 0 +reg 47: 0 +reg 48: 0 +reg 49: 0 +reg 50: 0 +reg 51: 0 +reg 52: 0 +reg 53: 0 +reg 54: 0 +reg 55: 0 +reg 56: 0 +reg 57: 0 +reg 58: 0 +reg 59: 0 +reg 60: 0 +reg 61: 0 +reg 62: 0 +reg 63: 0 +write_item 0000110000000000011000000000000000000000000000000000000000000000 +write_item 63: 0 +write_item 62: 0 +write_item 61: 0 +write_item 60: 0 +write_item 59: 1 +write_item 58: 1 +write_item 57: 0 +write_item 56: 0 +write_item 55: 0 +write_item 54: 0 +write_item 53: 0 +write_item 52: 0 +write_item 51: 0 +write_item 50: 0 +write_item 49: 0 +write_item 48: 0 +write_item 47: 0 +write_item 46: 1 +write_item 45: 1 +write_item 44: 0 +write_item 43: 0 +write_item 42: 0 +write_item 41: 0 +write_item 40: 0 +write_item 39: 0 +write_item 38: 0 +write_item 37: 0 +write_item 36: 0 +write_item 35: 0 +write_item 34: 0 +write_item 33: 0 +write_item 32: 0 +write_item 31: 0 +write_item 30: 0 +write_item 29: 0 +write_item 28: 0 +write_item 27: 0 +write_item 26: 0 +write_item 25: 0 +write_item 24: 0 +write_item 23: 0 +write_item 22: 0 +write_item 21: 0 +write_item 20: 0 +write_item 19: 0 +write_item 18: 0 +write_item 17: 0 +write_item 16: 0 +write_item 15: 0 +write_item 14: 0 +write_item 13: 0 +write_item 12: 0 +write_item 11: 0 +write_item 10: 0 +write_item 9: 0 +write_item 8: 0 +write_item 7: 0 +write_item 6: 0 +write_item 5: 0 +write_item 4: 0 +write_item 3: 0 +write_item 2: 0 +write_item 1: 0 +write_item 0: 0 +reg 0: 0 +reg 1: 0 +reg 2: 0 +reg 3: 0 +reg 4: 1 +reg 5: 1 +reg 6: 0 +reg 7: 0 +reg 8: 0 +reg 9: 0 +reg 10: 0 +reg 11: 0 +reg 12: 0 +reg 13: 0 +reg 14: 0 +reg 15: 0 +reg 16: 0 +reg 17: 1 +reg 18: 1 +reg 19: 0 +reg 20: 0 +reg 21: 0 +reg 22: 0 +reg 23: 0 +reg 24: 0 +reg 25: 0 +reg 26: 0 +reg 27: 0 +reg 28: 0 +reg 29: 0 +reg 30: 0 +reg 31: 0 +reg 32: 0 +reg 33: 0 +reg 34: 0 +reg 35: 0 +reg 36: 0 +reg 37: 0 +reg 38: 0 +reg 39: 0 +reg 40: 0 +reg 41: 0 +reg 42: 0 +reg 43: 0 +reg 44: 0 +reg 45: 0 +reg 46: 0 +reg 47: 0 +reg 48: 0 +reg 49: 0 +reg 50: 0 +reg 51: 0 +reg 52: 0 +reg 53: 0 +reg 54: 0 +reg 55: 0 +reg 56: 0 +reg 57: 0 +reg 58: 0 +reg 59: 0 +reg 60: 0 +reg 61: 0 +reg 62: 0 +reg 63: 0 +write_item 0000110000000000011000010000000000000000000000000000000000000000 +write_item 63: 0 +write_item 62: 0 +write_item 61: 0 +write_item 60: 0 +write_item 59: 1 +write_item 58: 1 +write_item 57: 0 +write_item 56: 0 +write_item 55: 0 +write_item 54: 0 +write_item 53: 0 +write_item 52: 0 +write_item 51: 0 +write_item 50: 0 +write_item 49: 0 +write_item 48: 0 +write_item 47: 0 +write_item 46: 1 +write_item 45: 1 +write_item 44: 0 +write_item 43: 0 +write_item 42: 0 +write_item 41: 0 +write_item 40: 1 +write_item 39: 0 +write_item 38: 0 +write_item 37: 0 +write_item 36: 0 +write_item 35: 0 +write_item 34: 0 +write_item 33: 0 +write_item 32: 0 +write_item 31: 0 +write_item 30: 0 +write_item 29: 0 +write_item 28: 0 +write_item 27: 0 +write_item 26: 0 +write_item 25: 0 +write_item 24: 0 +write_item 23: 0 +write_item 22: 0 +write_item 21: 0 +write_item 20: 0 +write_item 19: 0 +write_item 18: 0 +write_item 17: 0 +write_item 16: 0 +write_item 15: 0 +write_item 14: 0 +write_item 13: 0 +write_item 12: 0 +write_item 11: 0 +write_item 10: 0 +write_item 9: 0 +write_item 8: 0 +write_item 7: 0 +write_item 6: 0 +write_item 5: 0 +write_item 4: 0 +write_item 3: 0 +write_item 2: 0 +write_item 1: 0 +write_item 0: 0 +reg 0: 0 +reg 1: 0 +reg 2: 0 +reg 3: 0 +reg 4: 1 +reg 5: 1 +reg 6: 0 +reg 7: 0 +reg 8: 0 +reg 9: 0 +reg 10: 0 +reg 11: 0 +reg 12: 0 +reg 13: 0 +reg 14: 0 +reg 15: 0 +reg 16: 0 +reg 17: 1 +reg 18: 1 +reg 19: 0 +reg 20: 0 +reg 21: 0 +reg 22: 0 +reg 23: 1 +reg 24: 0 +reg 25: 0 +reg 26: 0 +reg 27: 0 +reg 28: 0 +reg 29: 0 +reg 30: 0 +reg 31: 0 +reg 32: 0 +reg 33: 0 +reg 34: 0 +reg 35: 0 +reg 36: 0 +reg 37: 0 +reg 38: 0 +reg 39: 0 +reg 40: 0 +reg 41: 0 +reg 42: 0 +reg 43: 0 +reg 44: 0 +reg 45: 0 +reg 46: 0 +reg 47: 0 +reg 48: 0 +reg 49: 0 +reg 50: 0 +reg 51: 0 +reg 52: 0 +reg 53: 0 +reg 54: 0 +reg 55: 0 +reg 56: 0 +reg 57: 0 +reg 58: 0 +reg 59: 0 +reg 60: 0 +reg 61: 0 +reg 62: 0 +reg 63: 0 +write_item 0000110000000000011000100000000000000000000000000000000000000000 +write_item 63: 0 +write_item 62: 0 +write_item 61: 0 +write_item 60: 0 +write_item 59: 1 +write_item 58: 1 +write_item 57: 0 +write_item 56: 0 +write_item 55: 0 +write_item 54: 0 +write_item 53: 0 +write_item 52: 0 +write_item 51: 0 +write_item 50: 0 +write_item 49: 0 +write_item 48: 0 +write_item 47: 0 +write_item 46: 1 +write_item 45: 1 +write_item 44: 0 +write_item 43: 0 +write_item 42: 0 +write_item 41: 1 +write_item 40: 0 +write_item 39: 0 +write_item 38: 0 +write_item 37: 0 +write_item 36: 0 +write_item 35: 0 +write_item 34: 0 +write_item 33: 0 +write_item 32: 0 +write_item 31: 0 +write_item 30: 0 +write_item 29: 0 +write_item 28: 0 +write_item 27: 0 +write_item 26: 0 +write_item 25: 0 +write_item 24: 0 +write_item 23: 0 +write_item 22: 0 +write_item 21: 0 +write_item 20: 0 +write_item 19: 0 +write_item 18: 0 +write_item 17: 0 +write_item 16: 0 +write_item 15: 0 +write_item 14: 0 +write_item 13: 0 +write_item 12: 0 +write_item 11: 0 +write_item 10: 0 +write_item 9: 0 +write_item 8: 0 +write_item 7: 0 +write_item 6: 0 +write_item 5: 0 +write_item 4: 0 +write_item 3: 0 +write_item 2: 0 +write_item 1: 0 +write_item 0: 0 +reg 0: 0 +reg 1: 0 +reg 2: 0 +reg 3: 0 +reg 4: 1 +reg 5: 1 +reg 6: 0 +reg 7: 0 +reg 8: 0 +reg 9: 0 +reg 10: 0 +reg 11: 0 +reg 12: 0 +reg 13: 0 +reg 14: 0 +reg 15: 0 +reg 16: 0 +reg 17: 1 +reg 18: 1 +reg 19: 0 +reg 20: 0 +reg 21: 0 +reg 22: 1 +reg 23: 0 +reg 24: 0 +reg 25: 0 +reg 26: 0 +reg 27: 0 +reg 28: 0 +reg 29: 0 +reg 30: 0 +reg 31: 0 +reg 32: 0 +reg 33: 0 +reg 34: 0 +reg 35: 0 +reg 36: 0 +reg 37: 0 +reg 38: 0 +reg 39: 0 +reg 40: 0 +reg 41: 0 +reg 42: 0 +reg 43: 0 +reg 44: 0 +reg 45: 0 +reg 46: 0 +reg 47: 0 +reg 48: 0 +reg 49: 0 +reg 50: 0 +reg 51: 0 +reg 52: 0 +reg 53: 0 +reg 54: 0 +reg 55: 0 +reg 56: 0 +reg 57: 0 +reg 58: 0 +reg 59: 0 +reg 60: 0 +reg 61: 0 +reg 62: 0 +reg 63: 0 +write_item 0000110000000000011000110000000000000000000000000000000000000000 +write_item 63: 0 +write_item 62: 0 +write_item 61: 0 +write_item 60: 0 +write_item 59: 1 +write_item 58: 1 +write_item 57: 0 +write_item 56: 0 +write_item 55: 0 +write_item 54: 0 +write_item 53: 0 +write_item 52: 0 +write_item 51: 0 +write_item 50: 0 +write_item 49: 0 +write_item 48: 0 +write_item 47: 0 +write_item 46: 1 +write_item 45: 1 +write_item 44: 0 +write_item 43: 0 +write_item 42: 0 +write_item 41: 1 +write_item 40: 1 +write_item 39: 0 +write_item 38: 0 +write_item 37: 0 +write_item 36: 0 +write_item 35: 0 +write_item 34: 0 +write_item 33: 0 +write_item 32: 0 +write_item 31: 0 +write_item 30: 0 +write_item 29: 0 +write_item 28: 0 +write_item 27: 0 +write_item 26: 0 +write_item 25: 0 +write_item 24: 0 +write_item 23: 0 +write_item 22: 0 +write_item 21: 0 +write_item 20: 0 +write_item 19: 0 +write_item 18: 0 +write_item 17: 0 +write_item 16: 0 +write_item 15: 0 +write_item 14: 0 +write_item 13: 0 +write_item 12: 0 +write_item 11: 0 +write_item 10: 0 +write_item 9: 0 +write_item 8: 0 +write_item 7: 0 +write_item 6: 0 +write_item 5: 0 +write_item 4: 0 +write_item 3: 0 +write_item 2: 0 +write_item 1: 0 +write_item 0: 0 +reg 0: 0 +reg 1: 0 +reg 2: 0 +reg 3: 0 +reg 4: 1 +reg 5: 1 +reg 6: 0 +reg 7: 0 +reg 8: 0 +reg 9: 0 +reg 10: 0 +reg 11: 0 +reg 12: 0 +reg 13: 0 +reg 14: 0 +reg 15: 0 +reg 16: 0 +reg 17: 1 +reg 18: 1 +reg 19: 0 +reg 20: 0 +reg 21: 0 +reg 22: 1 +reg 23: 1 +reg 24: 0 +reg 25: 0 +reg 26: 0 +reg 27: 0 +reg 28: 0 +reg 29: 0 +reg 30: 0 +reg 31: 0 +reg 32: 0 +reg 33: 0 +reg 34: 0 +reg 35: 0 +reg 36: 0 +reg 37: 0 +reg 38: 0 +reg 39: 0 +reg 40: 0 +reg 41: 0 +reg 42: 0 +reg 43: 0 +reg 44: 0 +reg 45: 0 +reg 46: 0 +reg 47: 0 +reg 48: 0 +reg 49: 0 +reg 50: 0 +reg 51: 0 +reg 52: 0 +reg 53: 0 +reg 54: 0 +reg 55: 0 +reg 56: 0 +reg 57: 0 +reg 58: 0 +reg 59: 0 +reg 60: 0 +reg 61: 0 +reg 62: 0 +reg 63: 0 +write_item 0000110000000000011001000000000011111111111100000000111001001101 +write_item 63: 0 +write_item 62: 0 +write_item 61: 0 +write_item 60: 0 +write_item 59: 1 +write_item 58: 1 +write_item 57: 0 +write_item 56: 0 +write_item 55: 0 +write_item 54: 0 +write_item 53: 0 +write_item 52: 0 +write_item 51: 0 +write_item 50: 0 +write_item 49: 0 +write_item 48: 0 +write_item 47: 0 +write_item 46: 1 +write_item 45: 1 +write_item 44: 0 +write_item 43: 0 +write_item 42: 1 +write_item 41: 0 +write_item 40: 0 +write_item 39: 0 +write_item 38: 0 +write_item 37: 0 +write_item 36: 0 +write_item 35: 0 +write_item 34: 0 +write_item 33: 0 +write_item 32: 0 +write_item 31: 1 +write_item 30: 1 +write_item 29: 1 +write_item 28: 1 +write_item 27: 1 +write_item 26: 1 +write_item 25: 1 +write_item 24: 1 +write_item 23: 1 +write_item 22: 1 +write_item 21: 1 +write_item 20: 1 +write_item 19: 0 +write_item 18: 0 +write_item 17: 0 +write_item 16: 0 +write_item 15: 0 +write_item 14: 0 +write_item 13: 0 +write_item 12: 0 +write_item 11: 1 +write_item 10: 1 +write_item 9: 1 +write_item 8: 0 +write_item 7: 0 +write_item 6: 1 +write_item 5: 0 +write_item 4: 0 +write_item 3: 1 +write_item 2: 1 +write_item 1: 0 +write_item 0: 1 +reg 0: 0 +reg 1: 0 +reg 2: 0 +reg 3: 0 +reg 4: 1 +reg 5: 1 +reg 6: 0 +reg 7: 0 +reg 8: 0 +reg 9: 0 +reg 10: 0 +reg 11: 0 +reg 12: 0 +reg 13: 0 +reg 14: 0 +reg 15: 0 +reg 16: 0 +reg 17: 1 +reg 18: 1 +reg 19: 0 +reg 20: 0 +reg 21: 1 +reg 22: 0 +reg 23: 0 +reg 24: 0 +reg 25: 0 +reg 26: 0 +reg 27: 0 +reg 28: 0 +reg 29: 0 +reg 30: 0 +reg 31: 0 +reg 32: 1 +reg 33: 1 +reg 34: 1 +reg 35: 1 +reg 36: 1 +reg 37: 1 +reg 38: 1 +reg 39: 1 +reg 40: 1 +reg 41: 1 +reg 42: 1 +reg 43: 1 +reg 44: 0 +reg 45: 0 +reg 46: 0 +reg 47: 0 +reg 48: 0 +reg 49: 0 +reg 50: 0 +reg 51: 0 +reg 52: 1 +reg 53: 1 +reg 54: 1 +reg 55: 0 +reg 56: 0 +reg 57: 1 +reg 58: 0 +reg 59: 0 +reg 60: 1 +reg 61: 1 +reg 62: 0 +reg 63: 1 +write_item 0000110000000000011001010000000011111111111100000010110000111001 +write_item 63: 0 +write_item 62: 0 +write_item 61: 0 +write_item 60: 0 +write_item 59: 1 +write_item 58: 1 +write_item 57: 0 +write_item 56: 0 +write_item 55: 0 +write_item 54: 0 +write_item 53: 0 +write_item 52: 0 +write_item 51: 0 +write_item 50: 0 +write_item 49: 0 +write_item 48: 0 +write_item 47: 0 +write_item 46: 1 +write_item 45: 1 +write_item 44: 0 +write_item 43: 0 +write_item 42: 1 +write_item 41: 0 +write_item 40: 1 +write_item 39: 0 +write_item 38: 0 +write_item 37: 0 +write_item 36: 0 +write_item 35: 0 +write_item 34: 0 +write_item 33: 0 +write_item 32: 0 +write_item 31: 1 +write_item 30: 1 +write_item 29: 1 +write_item 28: 1 +write_item 27: 1 +write_item 26: 1 +write_item 25: 1 +write_item 24: 1 +write_item 23: 1 +write_item 22: 1 +write_item 21: 1 +write_item 20: 1 +write_item 19: 0 +write_item 18: 0 +write_item 17: 0 +write_item 16: 0 +write_item 15: 0 +write_item 14: 0 +write_item 13: 1 +write_item 12: 0 +write_item 11: 1 +write_item 10: 1 +write_item 9: 0 +write_item 8: 0 +write_item 7: 0 +write_item 6: 0 +write_item 5: 1 +write_item 4: 1 +write_item 3: 1 +write_item 2: 0 +write_item 1: 0 +write_item 0: 1 +reg 0: 0 +reg 1: 0 +reg 2: 0 +reg 3: 0 +reg 4: 1 +reg 5: 1 +reg 6: 0 +reg 7: 0 +reg 8: 0 +reg 9: 0 +reg 10: 0 +reg 11: 0 +reg 12: 0 +reg 13: 0 +reg 14: 0 +reg 15: 0 +reg 16: 0 +reg 17: 1 +reg 18: 1 +reg 19: 0 +reg 20: 0 +reg 21: 1 +reg 22: 0 +reg 23: 1 +reg 24: 0 +reg 25: 0 +reg 26: 0 +reg 27: 0 +reg 28: 0 +reg 29: 0 +reg 30: 0 +reg 31: 0 +reg 32: 1 +reg 33: 1 +reg 34: 1 +reg 35: 1 +reg 36: 1 +reg 37: 1 +reg 38: 1 +reg 39: 1 +reg 40: 1 +reg 41: 1 +reg 42: 1 +reg 43: 1 +reg 44: 0 +reg 45: 0 +reg 46: 0 +reg 47: 0 +reg 48: 0 +reg 49: 0 +reg 50: 1 +reg 51: 0 +reg 52: 1 +reg 53: 1 +reg 54: 0 +reg 55: 0 +reg 56: 0 +reg 57: 0 +reg 58: 1 +reg 59: 1 +reg 60: 1 +reg 61: 0 +reg 62: 0 +reg 63: 1 +write_item 0000110000000000011001100000000011111111111100000010100011110101 +write_item 63: 0 +write_item 62: 0 +write_item 61: 0 +write_item 60: 0 +write_item 59: 1 +write_item 58: 1 +write_item 57: 0 +write_item 56: 0 +write_item 55: 0 +write_item 54: 0 +write_item 53: 0 +write_item 52: 0 +write_item 51: 0 +write_item 50: 0 +write_item 49: 0 +write_item 48: 0 +write_item 47: 0 +write_item 46: 1 +write_item 45: 1 +write_item 44: 0 +write_item 43: 0 +write_item 42: 1 +write_item 41: 1 +write_item 40: 0 +write_item 39: 0 +write_item 38: 0 +write_item 37: 0 +write_item 36: 0 +write_item 35: 0 +write_item 34: 0 +write_item 33: 0 +write_item 32: 0 +write_item 31: 1 +write_item 30: 1 +write_item 29: 1 +write_item 28: 1 +write_item 27: 1 +write_item 26: 1 +write_item 25: 1 +write_item 24: 1 +write_item 23: 1 +write_item 22: 1 +write_item 21: 1 +write_item 20: 1 +write_item 19: 0 +write_item 18: 0 +write_item 17: 0 +write_item 16: 0 +write_item 15: 0 +write_item 14: 0 +write_item 13: 1 +write_item 12: 0 +write_item 11: 1 +write_item 10: 0 +write_item 9: 0 +write_item 8: 0 +write_item 7: 1 +write_item 6: 1 +write_item 5: 1 +write_item 4: 1 +write_item 3: 0 +write_item 2: 1 +write_item 1: 0 +write_item 0: 1 +reg 0: 0 +reg 1: 0 +reg 2: 0 +reg 3: 0 +reg 4: 1 +reg 5: 1 +reg 6: 0 +reg 7: 0 +reg 8: 0 +reg 9: 0 +reg 10: 0 +reg 11: 0 +reg 12: 0 +reg 13: 0 +reg 14: 0 +reg 15: 0 +reg 16: 0 +reg 17: 1 +reg 18: 1 +reg 19: 0 +reg 20: 0 +reg 21: 1 +reg 22: 1 +reg 23: 0 +reg 24: 0 +reg 25: 0 +reg 26: 0 +reg 27: 0 +reg 28: 0 +reg 29: 0 +reg 30: 0 +reg 31: 0 +reg 32: 1 +reg 33: 1 +reg 34: 1 +reg 35: 1 +reg 36: 1 +reg 37: 1 +reg 38: 1 +reg 39: 1 +reg 40: 1 +reg 41: 1 +reg 42: 1 +reg 43: 1 +reg 44: 0 +reg 45: 0 +reg 46: 0 +reg 47: 0 +reg 48: 0 +reg 49: 0 +reg 50: 1 +reg 51: 0 +reg 52: 1 +reg 53: 0 +reg 54: 0 +reg 55: 0 +reg 56: 1 +reg 57: 1 +reg 58: 1 +reg 59: 1 +reg 60: 0 +reg 61: 1 +reg 62: 0 +reg 63: 1 +write_item 0000110000000000011001110000000011111111111100000000000010001100 +write_item 63: 0 +write_item 62: 0 +write_item 61: 0 +write_item 60: 0 +write_item 59: 1 +write_item 58: 1 +write_item 57: 0 +write_item 56: 0 +write_item 55: 0 +write_item 54: 0 +write_item 53: 0 +write_item 52: 0 +write_item 51: 0 +write_item 50: 0 +write_item 49: 0 +write_item 48: 0 +write_item 47: 0 +write_item 46: 1 +write_item 45: 1 +write_item 44: 0 +write_item 43: 0 +write_item 42: 1 +write_item 41: 1 +write_item 40: 1 +write_item 39: 0 +write_item 38: 0 +write_item 37: 0 +write_item 36: 0 +write_item 35: 0 +write_item 34: 0 +write_item 33: 0 +write_item 32: 0 +write_item 31: 1 +write_item 30: 1 +write_item 29: 1 +write_item 28: 1 +write_item 27: 1 +write_item 26: 1 +write_item 25: 1 +write_item 24: 1 +write_item 23: 1 +write_item 22: 1 +write_item 21: 1 +write_item 20: 1 +write_item 19: 0 +write_item 18: 0 +write_item 17: 0 +write_item 16: 0 +write_item 15: 0 +write_item 14: 0 +write_item 13: 0 +write_item 12: 0 +write_item 11: 0 +write_item 10: 0 +write_item 9: 0 +write_item 8: 0 +write_item 7: 1 +write_item 6: 0 +write_item 5: 0 +write_item 4: 0 +write_item 3: 1 +write_item 2: 1 +write_item 1: 0 +write_item 0: 0 +reg 0: 0 +reg 1: 0 +reg 2: 0 +reg 3: 0 +reg 4: 1 +reg 5: 1 +reg 6: 0 +reg 7: 0 +reg 8: 0 +reg 9: 0 +reg 10: 0 +reg 11: 0 +reg 12: 0 +reg 13: 0 +reg 14: 0 +reg 15: 0 +reg 16: 0 +reg 17: 1 +reg 18: 1 +reg 19: 0 +reg 20: 0 +reg 21: 1 +reg 22: 1 +reg 23: 1 +reg 24: 0 +reg 25: 0 +reg 26: 0 +reg 27: 0 +reg 28: 0 +reg 29: 0 +reg 30: 0 +reg 31: 0 +reg 32: 1 +reg 33: 1 +reg 34: 1 +reg 35: 1 +reg 36: 1 +reg 37: 1 +reg 38: 1 +reg 39: 1 +reg 40: 1 +reg 41: 1 +reg 42: 1 +reg 43: 1 +reg 44: 0 +reg 45: 0 +reg 46: 0 +reg 47: 0 +reg 48: 0 +reg 49: 0 +reg 50: 0 +reg 51: 0 +reg 52: 0 +reg 53: 0 +reg 54: 0 +reg 55: 0 +reg 56: 1 +reg 57: 0 +reg 58: 0 +reg 59: 0 +reg 60: 1 +reg 61: 1 +reg 62: 0 +reg 63: 0 +write_item 0000110000000000011010000000000011111111111100000000000000000000 +write_item 63: 0 +write_item 62: 0 +write_item 61: 0 +write_item 60: 0 +write_item 59: 1 +write_item 58: 1 +write_item 57: 0 +write_item 56: 0 +write_item 55: 0 +write_item 54: 0 +write_item 53: 0 +write_item 52: 0 +write_item 51: 0 +write_item 50: 0 +write_item 49: 0 +write_item 48: 0 +write_item 47: 0 +write_item 46: 1 +write_item 45: 1 +write_item 44: 0 +write_item 43: 1 +write_item 42: 0 +write_item 41: 0 +write_item 40: 0 +write_item 39: 0 +write_item 38: 0 +write_item 37: 0 +write_item 36: 0 +write_item 35: 0 +write_item 34: 0 +write_item 33: 0 +write_item 32: 0 +write_item 31: 1 +write_item 30: 1 +write_item 29: 1 +write_item 28: 1 +write_item 27: 1 +write_item 26: 1 +write_item 25: 1 +write_item 24: 1 +write_item 23: 1 +write_item 22: 1 +write_item 21: 1 +write_item 20: 1 +write_item 19: 0 +write_item 18: 0 +write_item 17: 0 +write_item 16: 0 +write_item 15: 0 +write_item 14: 0 +write_item 13: 0 +write_item 12: 0 +write_item 11: 0 +write_item 10: 0 +write_item 9: 0 +write_item 8: 0 +write_item 7: 0 +write_item 6: 0 +write_item 5: 0 +write_item 4: 0 +write_item 3: 0 +write_item 2: 0 +write_item 1: 0 +write_item 0: 0 +reg 0: 0 +reg 1: 0 +reg 2: 0 +reg 3: 0 +reg 4: 1 +reg 5: 1 +reg 6: 0 +reg 7: 0 +reg 8: 0 +reg 9: 0 +reg 10: 0 +reg 11: 0 +reg 12: 0 +reg 13: 0 +reg 14: 0 +reg 15: 0 +reg 16: 0 +reg 17: 1 +reg 18: 1 +reg 19: 0 +reg 20: 1 +reg 21: 0 +reg 22: 0 +reg 23: 0 +reg 24: 0 +reg 25: 0 +reg 26: 0 +reg 27: 0 +reg 28: 0 +reg 29: 0 +reg 30: 0 +reg 31: 0 +reg 32: 1 +reg 33: 1 +reg 34: 1 +reg 35: 1 +reg 36: 1 +reg 37: 1 +reg 38: 1 +reg 39: 1 +reg 40: 1 +reg 41: 1 +reg 42: 1 +reg 43: 1 +reg 44: 0 +reg 45: 0 +reg 46: 0 +reg 47: 0 +reg 48: 0 +reg 49: 0 +reg 50: 0 +reg 51: 0 +reg 52: 0 +reg 53: 0 +reg 54: 0 +reg 55: 0 +reg 56: 0 +reg 57: 0 +reg 58: 0 +reg 59: 0 +reg 60: 0 +reg 61: 0 +reg 62: 0 +reg 63: 0 +write_item 0000110000000000011010010000000011111111111100000000000000000000 +write_item 63: 0 +write_item 62: 0 +write_item 61: 0 +write_item 60: 0 +write_item 59: 1 +write_item 58: 1 +write_item 57: 0 +write_item 56: 0 +write_item 55: 0 +write_item 54: 0 +write_item 53: 0 +write_item 52: 0 +write_item 51: 0 +write_item 50: 0 +write_item 49: 0 +write_item 48: 0 +write_item 47: 0 +write_item 46: 1 +write_item 45: 1 +write_item 44: 0 +write_item 43: 1 +write_item 42: 0 +write_item 41: 0 +write_item 40: 1 +write_item 39: 0 +write_item 38: 0 +write_item 37: 0 +write_item 36: 0 +write_item 35: 0 +write_item 34: 0 +write_item 33: 0 +write_item 32: 0 +write_item 31: 1 +write_item 30: 1 +write_item 29: 1 +write_item 28: 1 +write_item 27: 1 +write_item 26: 1 +write_item 25: 1 +write_item 24: 1 +write_item 23: 1 +write_item 22: 1 +write_item 21: 1 +write_item 20: 1 +write_item 19: 0 +write_item 18: 0 +write_item 17: 0 +write_item 16: 0 +write_item 15: 0 +write_item 14: 0 +write_item 13: 0 +write_item 12: 0 +write_item 11: 0 +write_item 10: 0 +write_item 9: 0 +write_item 8: 0 +write_item 7: 0 +write_item 6: 0 +write_item 5: 0 +write_item 4: 0 +write_item 3: 0 +write_item 2: 0 +write_item 1: 0 +write_item 0: 0 +reg 0: 0 +reg 1: 0 +reg 2: 0 +reg 3: 0 +reg 4: 1 +reg 5: 1 +reg 6: 0 +reg 7: 0 +reg 8: 0 +reg 9: 0 +reg 10: 0 +reg 11: 0 +reg 12: 0 +reg 13: 0 +reg 14: 0 +reg 15: 0 +reg 16: 0 +reg 17: 1 +reg 18: 1 +reg 19: 0 +reg 20: 1 +reg 21: 0 +reg 22: 0 +reg 23: 1 +reg 24: 0 +reg 25: 0 +reg 26: 0 +reg 27: 0 +reg 28: 0 +reg 29: 0 +reg 30: 0 +reg 31: 0 +reg 32: 1 +reg 33: 1 +reg 34: 1 +reg 35: 1 +reg 36: 1 +reg 37: 1 +reg 38: 1 +reg 39: 1 +reg 40: 1 +reg 41: 1 +reg 42: 1 +reg 43: 1 +reg 44: 0 +reg 45: 0 +reg 46: 0 +reg 47: 0 +reg 48: 0 +reg 49: 0 +reg 50: 0 +reg 51: 0 +reg 52: 0 +reg 53: 0 +reg 54: 0 +reg 55: 0 +reg 56: 0 +reg 57: 0 +reg 58: 0 +reg 59: 0 +reg 60: 0 +reg 61: 0 +reg 62: 0 +reg 63: 0 +write_item 0000110000000000011010100000000000000000000000000000000000000000 +write_item 63: 0 +write_item 62: 0 +write_item 61: 0 +write_item 60: 0 +write_item 59: 1 +write_item 58: 1 +write_item 57: 0 +write_item 56: 0 +write_item 55: 0 +write_item 54: 0 +write_item 53: 0 +write_item 52: 0 +write_item 51: 0 +write_item 50: 0 +write_item 49: 0 +write_item 48: 0 +write_item 47: 0 +write_item 46: 1 +write_item 45: 1 +write_item 44: 0 +write_item 43: 1 +write_item 42: 0 +write_item 41: 1 +write_item 40: 0 +write_item 39: 0 +write_item 38: 0 +write_item 37: 0 +write_item 36: 0 +write_item 35: 0 +write_item 34: 0 +write_item 33: 0 +write_item 32: 0 +write_item 31: 0 +write_item 30: 0 +write_item 29: 0 +write_item 28: 0 +write_item 27: 0 +write_item 26: 0 +write_item 25: 0 +write_item 24: 0 +write_item 23: 0 +write_item 22: 0 +write_item 21: 0 +write_item 20: 0 +write_item 19: 0 +write_item 18: 0 +write_item 17: 0 +write_item 16: 0 +write_item 15: 0 +write_item 14: 0 +write_item 13: 0 +write_item 12: 0 +write_item 11: 0 +write_item 10: 0 +write_item 9: 0 +write_item 8: 0 +write_item 7: 0 +write_item 6: 0 +write_item 5: 0 +write_item 4: 0 +write_item 3: 0 +write_item 2: 0 +write_item 1: 0 +write_item 0: 0 +reg 0: 0 +reg 1: 0 +reg 2: 0 +reg 3: 0 +reg 4: 1 +reg 5: 1 +reg 6: 0 +reg 7: 0 +reg 8: 0 +reg 9: 0 +reg 10: 0 +reg 11: 0 +reg 12: 0 +reg 13: 0 +reg 14: 0 +reg 15: 0 +reg 16: 0 +reg 17: 1 +reg 18: 1 +reg 19: 0 +reg 20: 1 +reg 21: 0 +reg 22: 1 +reg 23: 0 +reg 24: 0 +reg 25: 0 +reg 26: 0 +reg 27: 0 +reg 28: 0 +reg 29: 0 +reg 30: 0 +reg 31: 0 +reg 32: 0 +reg 33: 0 +reg 34: 0 +reg 35: 0 +reg 36: 0 +reg 37: 0 +reg 38: 0 +reg 39: 0 +reg 40: 0 +reg 41: 0 +reg 42: 0 +reg 43: 0 +reg 44: 0 +reg 45: 0 +reg 46: 0 +reg 47: 0 +reg 48: 0 +reg 49: 0 +reg 50: 0 +reg 51: 0 +reg 52: 0 +reg 53: 0 +reg 54: 0 +reg 55: 0 +reg 56: 0 +reg 57: 0 +reg 58: 0 +reg 59: 0 +reg 60: 0 +reg 61: 0 +reg 62: 0 +reg 63: 0 +write_item 0000110000000000011010110000000000000000000000000010100011011100 +write_item 63: 0 +write_item 62: 0 +write_item 61: 0 +write_item 60: 0 +write_item 59: 1 +write_item 58: 1 +write_item 57: 0 +write_item 56: 0 +write_item 55: 0 +write_item 54: 0 +write_item 53: 0 +write_item 52: 0 +write_item 51: 0 +write_item 50: 0 +write_item 49: 0 +write_item 48: 0 +write_item 47: 0 +write_item 46: 1 +write_item 45: 1 +write_item 44: 0 +write_item 43: 1 +write_item 42: 0 +write_item 41: 1 +write_item 40: 1 +write_item 39: 0 +write_item 38: 0 +write_item 37: 0 +write_item 36: 0 +write_item 35: 0 +write_item 34: 0 +write_item 33: 0 +write_item 32: 0 +write_item 31: 0 +write_item 30: 0 +write_item 29: 0 +write_item 28: 0 +write_item 27: 0 +write_item 26: 0 +write_item 25: 0 +write_item 24: 0 +write_item 23: 0 +write_item 22: 0 +write_item 21: 0 +write_item 20: 0 +write_item 19: 0 +write_item 18: 0 +write_item 17: 0 +write_item 16: 0 +write_item 15: 0 +write_item 14: 0 +write_item 13: 1 +write_item 12: 0 +write_item 11: 1 +write_item 10: 0 +write_item 9: 0 +write_item 8: 0 +write_item 7: 1 +write_item 6: 1 +write_item 5: 0 +write_item 4: 1 +write_item 3: 1 +write_item 2: 1 +write_item 1: 0 +write_item 0: 0 +reg 0: 0 +reg 1: 0 +reg 2: 0 +reg 3: 0 +reg 4: 1 +reg 5: 1 +reg 6: 0 +reg 7: 0 +reg 8: 0 +reg 9: 0 +reg 10: 0 +reg 11: 0 +reg 12: 0 +reg 13: 0 +reg 14: 0 +reg 15: 0 +reg 16: 0 +reg 17: 1 +reg 18: 1 +reg 19: 0 +reg 20: 1 +reg 21: 0 +reg 22: 1 +reg 23: 1 +reg 24: 0 +reg 25: 0 +reg 26: 0 +reg 27: 0 +reg 28: 0 +reg 29: 0 +reg 30: 0 +reg 31: 0 +reg 32: 0 +reg 33: 0 +reg 34: 0 +reg 35: 0 +reg 36: 0 +reg 37: 0 +reg 38: 0 +reg 39: 0 +reg 40: 0 +reg 41: 0 +reg 42: 0 +reg 43: 0 +reg 44: 0 +reg 45: 0 +reg 46: 0 +reg 47: 0 +reg 48: 0 +reg 49: 0 +reg 50: 1 +reg 51: 0 +reg 52: 1 +reg 53: 0 +reg 54: 0 +reg 55: 0 +reg 56: 1 +reg 57: 1 +reg 58: 0 +reg 59: 1 +reg 60: 1 +reg 61: 1 +reg 62: 0 +reg 63: 0 +write_item 0000110000000000011011000000000000000000000000000001000101000000 +write_item 63: 0 +write_item 62: 0 +write_item 61: 0 +write_item 60: 0 +write_item 59: 1 +write_item 58: 1 +write_item 57: 0 +write_item 56: 0 +write_item 55: 0 +write_item 54: 0 +write_item 53: 0 +write_item 52: 0 +write_item 51: 0 +write_item 50: 0 +write_item 49: 0 +write_item 48: 0 +write_item 47: 0 +write_item 46: 1 +write_item 45: 1 +write_item 44: 0 +write_item 43: 1 +write_item 42: 1 +write_item 41: 0 +write_item 40: 0 +write_item 39: 0 +write_item 38: 0 +write_item 37: 0 +write_item 36: 0 +write_item 35: 0 +write_item 34: 0 +write_item 33: 0 +write_item 32: 0 +write_item 31: 0 +write_item 30: 0 +write_item 29: 0 +write_item 28: 0 +write_item 27: 0 +write_item 26: 0 +write_item 25: 0 +write_item 24: 0 +write_item 23: 0 +write_item 22: 0 +write_item 21: 0 +write_item 20: 0 +write_item 19: 0 +write_item 18: 0 +write_item 17: 0 +write_item 16: 0 +write_item 15: 0 +write_item 14: 0 +write_item 13: 0 +write_item 12: 1 +write_item 11: 0 +write_item 10: 0 +write_item 9: 0 +write_item 8: 1 +write_item 7: 0 +write_item 6: 1 +write_item 5: 0 +write_item 4: 0 +write_item 3: 0 +write_item 2: 0 +write_item 1: 0 +write_item 0: 0 +reg 0: 0 +reg 1: 0 +reg 2: 0 +reg 3: 0 +reg 4: 1 +reg 5: 1 +reg 6: 0 +reg 7: 0 +reg 8: 0 +reg 9: 0 +reg 10: 0 +reg 11: 0 +reg 12: 0 +reg 13: 0 +reg 14: 0 +reg 15: 0 +reg 16: 0 +reg 17: 1 +reg 18: 1 +reg 19: 0 +reg 20: 1 +reg 21: 1 +reg 22: 0 +reg 23: 0 +reg 24: 0 +reg 25: 0 +reg 26: 0 +reg 27: 0 +reg 28: 0 +reg 29: 0 +reg 30: 0 +reg 31: 0 +reg 32: 0 +reg 33: 0 +reg 34: 0 +reg 35: 0 +reg 36: 0 +reg 37: 0 +reg 38: 0 +reg 39: 0 +reg 40: 0 +reg 41: 0 +reg 42: 0 +reg 43: 0 +reg 44: 0 +reg 45: 0 +reg 46: 0 +reg 47: 0 +reg 48: 0 +reg 49: 0 +reg 50: 0 +reg 51: 1 +reg 52: 0 +reg 53: 0 +reg 54: 0 +reg 55: 1 +reg 56: 0 +reg 57: 1 +reg 58: 0 +reg 59: 0 +reg 60: 0 +reg 61: 0 +reg 62: 0 +reg 63: 0 +write_item 0000110000000000011011010000000000000000000000000000000000000000 +write_item 63: 0 +write_item 62: 0 +write_item 61: 0 +write_item 60: 0 +write_item 59: 1 +write_item 58: 1 +write_item 57: 0 +write_item 56: 0 +write_item 55: 0 +write_item 54: 0 +write_item 53: 0 +write_item 52: 0 +write_item 51: 0 +write_item 50: 0 +write_item 49: 0 +write_item 48: 0 +write_item 47: 0 +write_item 46: 1 +write_item 45: 1 +write_item 44: 0 +write_item 43: 1 +write_item 42: 1 +write_item 41: 0 +write_item 40: 1 +write_item 39: 0 +write_item 38: 0 +write_item 37: 0 +write_item 36: 0 +write_item 35: 0 +write_item 34: 0 +write_item 33: 0 +write_item 32: 0 +write_item 31: 0 +write_item 30: 0 +write_item 29: 0 +write_item 28: 0 +write_item 27: 0 +write_item 26: 0 +write_item 25: 0 +write_item 24: 0 +write_item 23: 0 +write_item 22: 0 +write_item 21: 0 +write_item 20: 0 +write_item 19: 0 +write_item 18: 0 +write_item 17: 0 +write_item 16: 0 +write_item 15: 0 +write_item 14: 0 +write_item 13: 0 +write_item 12: 0 +write_item 11: 0 +write_item 10: 0 +write_item 9: 0 +write_item 8: 0 +write_item 7: 0 +write_item 6: 0 +write_item 5: 0 +write_item 4: 0 +write_item 3: 0 +write_item 2: 0 +write_item 1: 0 +write_item 0: 0 +reg 0: 0 +reg 1: 0 +reg 2: 0 +reg 3: 0 +reg 4: 1 +reg 5: 1 +reg 6: 0 +reg 7: 0 +reg 8: 0 +reg 9: 0 +reg 10: 0 +reg 11: 0 +reg 12: 0 +reg 13: 0 +reg 14: 0 +reg 15: 0 +reg 16: 0 +reg 17: 1 +reg 18: 1 +reg 19: 0 +reg 20: 1 +reg 21: 1 +reg 22: 0 +reg 23: 1 +reg 24: 0 +reg 25: 0 +reg 26: 0 +reg 27: 0 +reg 28: 0 +reg 29: 0 +reg 30: 0 +reg 31: 0 +reg 32: 0 +reg 33: 0 +reg 34: 0 +reg 35: 0 +reg 36: 0 +reg 37: 0 +reg 38: 0 +reg 39: 0 +reg 40: 0 +reg 41: 0 +reg 42: 0 +reg 43: 0 +reg 44: 0 +reg 45: 0 +reg 46: 0 +reg 47: 0 +reg 48: 0 +reg 49: 0 +reg 50: 0 +reg 51: 0 +reg 52: 0 +reg 53: 0 +reg 54: 0 +reg 55: 0 +reg 56: 0 +reg 57: 0 +reg 58: 0 +reg 59: 0 +reg 60: 0 +reg 61: 0 +reg 62: 0 +reg 63: 0 +write_item 0000110000000000011011100000000000000000000000000000000000000000 +write_item 63: 0 +write_item 62: 0 +write_item 61: 0 +write_item 60: 0 +write_item 59: 1 +write_item 58: 1 +write_item 57: 0 +write_item 56: 0 +write_item 55: 0 +write_item 54: 0 +write_item 53: 0 +write_item 52: 0 +write_item 51: 0 +write_item 50: 0 +write_item 49: 0 +write_item 48: 0 +write_item 47: 0 +write_item 46: 1 +write_item 45: 1 +write_item 44: 0 +write_item 43: 1 +write_item 42: 1 +write_item 41: 1 +write_item 40: 0 +write_item 39: 0 +write_item 38: 0 +write_item 37: 0 +write_item 36: 0 +write_item 35: 0 +write_item 34: 0 +write_item 33: 0 +write_item 32: 0 +write_item 31: 0 +write_item 30: 0 +write_item 29: 0 +write_item 28: 0 +write_item 27: 0 +write_item 26: 0 +write_item 25: 0 +write_item 24: 0 +write_item 23: 0 +write_item 22: 0 +write_item 21: 0 +write_item 20: 0 +write_item 19: 0 +write_item 18: 0 +write_item 17: 0 +write_item 16: 0 +write_item 15: 0 +write_item 14: 0 +write_item 13: 0 +write_item 12: 0 +write_item 11: 0 +write_item 10: 0 +write_item 9: 0 +write_item 8: 0 +write_item 7: 0 +write_item 6: 0 +write_item 5: 0 +write_item 4: 0 +write_item 3: 0 +write_item 2: 0 +write_item 1: 0 +write_item 0: 0 +reg 0: 0 +reg 1: 0 +reg 2: 0 +reg 3: 0 +reg 4: 1 +reg 5: 1 +reg 6: 0 +reg 7: 0 +reg 8: 0 +reg 9: 0 +reg 10: 0 +reg 11: 0 +reg 12: 0 +reg 13: 0 +reg 14: 0 +reg 15: 0 +reg 16: 0 +reg 17: 1 +reg 18: 1 +reg 19: 0 +reg 20: 1 +reg 21: 1 +reg 22: 1 +reg 23: 0 +reg 24: 0 +reg 25: 0 +reg 26: 0 +reg 27: 0 +reg 28: 0 +reg 29: 0 +reg 30: 0 +reg 31: 0 +reg 32: 0 +reg 33: 0 +reg 34: 0 +reg 35: 0 +reg 36: 0 +reg 37: 0 +reg 38: 0 +reg 39: 0 +reg 40: 0 +reg 41: 0 +reg 42: 0 +reg 43: 0 +reg 44: 0 +reg 45: 0 +reg 46: 0 +reg 47: 0 +reg 48: 0 +reg 49: 0 +reg 50: 0 +reg 51: 0 +reg 52: 0 +reg 53: 0 +reg 54: 0 +reg 55: 0 +reg 56: 0 +reg 57: 0 +reg 58: 0 +reg 59: 0 +reg 60: 0 +reg 61: 0 +reg 62: 0 +reg 63: 0 +write_item 0000110000000000011011110000000000000000000000000000000000000000 +write_item 63: 0 +write_item 62: 0 +write_item 61: 0 +write_item 60: 0 +write_item 59: 1 +write_item 58: 1 +write_item 57: 0 +write_item 56: 0 +write_item 55: 0 +write_item 54: 0 +write_item 53: 0 +write_item 52: 0 +write_item 51: 0 +write_item 50: 0 +write_item 49: 0 +write_item 48: 0 +write_item 47: 0 +write_item 46: 1 +write_item 45: 1 +write_item 44: 0 +write_item 43: 1 +write_item 42: 1 +write_item 41: 1 +write_item 40: 1 +write_item 39: 0 +write_item 38: 0 +write_item 37: 0 +write_item 36: 0 +write_item 35: 0 +write_item 34: 0 +write_item 33: 0 +write_item 32: 0 +write_item 31: 0 +write_item 30: 0 +write_item 29: 0 +write_item 28: 0 +write_item 27: 0 +write_item 26: 0 +write_item 25: 0 +write_item 24: 0 +write_item 23: 0 +write_item 22: 0 +write_item 21: 0 +write_item 20: 0 +write_item 19: 0 +write_item 18: 0 +write_item 17: 0 +write_item 16: 0 +write_item 15: 0 +write_item 14: 0 +write_item 13: 0 +write_item 12: 0 +write_item 11: 0 +write_item 10: 0 +write_item 9: 0 +write_item 8: 0 +write_item 7: 0 +write_item 6: 0 +write_item 5: 0 +write_item 4: 0 +write_item 3: 0 +write_item 2: 0 +write_item 1: 0 +write_item 0: 0 +reg 0: 0 +reg 1: 0 +reg 2: 0 +reg 3: 0 +reg 4: 1 +reg 5: 1 +reg 6: 0 +reg 7: 0 +reg 8: 0 +reg 9: 0 +reg 10: 0 +reg 11: 0 +reg 12: 0 +reg 13: 0 +reg 14: 0 +reg 15: 0 +reg 16: 0 +reg 17: 1 +reg 18: 1 +reg 19: 0 +reg 20: 1 +reg 21: 1 +reg 22: 1 +reg 23: 1 +reg 24: 0 +reg 25: 0 +reg 26: 0 +reg 27: 0 +reg 28: 0 +reg 29: 0 +reg 30: 0 +reg 31: 0 +reg 32: 0 +reg 33: 0 +reg 34: 0 +reg 35: 0 +reg 36: 0 +reg 37: 0 +reg 38: 0 +reg 39: 0 +reg 40: 0 +reg 41: 0 +reg 42: 0 +reg 43: 0 +reg 44: 0 +reg 45: 0 +reg 46: 0 +reg 47: 0 +reg 48: 0 +reg 49: 0 +reg 50: 0 +reg 51: 0 +reg 52: 0 +reg 53: 0 +reg 54: 0 +reg 55: 0 +reg 56: 0 +reg 57: 0 +reg 58: 0 +reg 59: 0 +reg 60: 0 +reg 61: 0 +reg 62: 0 +reg 63: 0 +write_item 0111110000000000000100110000000000000000000000000000000000000011 +write_item 63: 0 +write_item 62: 1 +write_item 61: 1 +write_item 60: 1 +write_item 59: 1 +write_item 58: 1 +write_item 57: 0 +write_item 56: 0 +write_item 55: 0 +write_item 54: 0 +write_item 53: 0 +write_item 52: 0 +write_item 51: 0 +write_item 50: 0 +write_item 49: 0 +write_item 48: 0 +write_item 47: 0 +write_item 46: 0 +write_item 45: 0 +write_item 44: 1 +write_item 43: 0 +write_item 42: 0 +write_item 41: 1 +write_item 40: 1 +write_item 39: 0 +write_item 38: 0 +write_item 37: 0 +write_item 36: 0 +write_item 35: 0 +write_item 34: 0 +write_item 33: 0 +write_item 32: 0 +write_item 31: 0 +write_item 30: 0 +write_item 29: 0 +write_item 28: 0 +write_item 27: 0 +write_item 26: 0 +write_item 25: 0 +write_item 24: 0 +write_item 23: 0 +write_item 22: 0 +write_item 21: 0 +write_item 20: 0 +write_item 19: 0 +write_item 18: 0 +write_item 17: 0 +write_item 16: 0 +write_item 15: 0 +write_item 14: 0 +write_item 13: 0 +write_item 12: 0 +write_item 11: 0 +write_item 10: 0 +write_item 9: 0 +write_item 8: 0 +write_item 7: 0 +write_item 6: 0 +write_item 5: 0 +write_item 4: 0 +write_item 3: 0 +write_item 2: 0 +write_item 1: 1 +write_item 0: 1 +reg 0: 0 +reg 1: 1 +reg 2: 1 +reg 3: 1 +reg 4: 1 +reg 5: 1 +reg 6: 0 +reg 7: 0 +reg 8: 0 +reg 9: 0 +reg 10: 0 +reg 11: 0 +reg 12: 0 +reg 13: 0 +reg 14: 0 +reg 15: 0 +reg 16: 0 +reg 17: 0 +reg 18: 0 +reg 19: 1 +reg 20: 0 +reg 21: 0 +reg 22: 1 +reg 23: 1 +reg 24: 0 +reg 25: 0 +reg 26: 0 +reg 27: 0 +reg 28: 0 +reg 29: 0 +reg 30: 0 +reg 31: 0 +reg 32: 0 +reg 33: 0 +reg 34: 0 +reg 35: 0 +reg 36: 0 +reg 37: 0 +reg 38: 0 +reg 39: 0 +reg 40: 0 +reg 41: 0 +reg 42: 0 +reg 43: 0 +reg 44: 0 +reg 45: 0 +reg 46: 0 +reg 47: 0 +reg 48: 0 +reg 49: 0 +reg 50: 0 +reg 51: 0 +reg 52: 0 +reg 53: 0 +reg 54: 0 +reg 55: 0 +reg 56: 0 +reg 57: 0 +reg 58: 0 +reg 59: 0 +reg 60: 0 +reg 61: 0 +reg 62: 1 +reg 63: 1 +write_item 0000110000000000010010100000000000000000000000000000000000000000 +write_item 63: 0 +write_item 62: 0 +write_item 61: 0 +write_item 60: 0 +write_item 59: 1 +write_item 58: 1 +write_item 57: 0 +write_item 56: 0 +write_item 55: 0 +write_item 54: 0 +write_item 53: 0 +write_item 52: 0 +write_item 51: 0 +write_item 50: 0 +write_item 49: 0 +write_item 48: 0 +write_item 47: 0 +write_item 46: 1 +write_item 45: 0 +write_item 44: 0 +write_item 43: 1 +write_item 42: 0 +write_item 41: 1 +write_item 40: 0 +write_item 39: 0 +write_item 38: 0 +write_item 37: 0 +write_item 36: 0 +write_item 35: 0 +write_item 34: 0 +write_item 33: 0 +write_item 32: 0 +write_item 31: 0 +write_item 30: 0 +write_item 29: 0 +write_item 28: 0 +write_item 27: 0 +write_item 26: 0 +write_item 25: 0 +write_item 24: 0 +write_item 23: 0 +write_item 22: 0 +write_item 21: 0 +write_item 20: 0 +write_item 19: 0 +write_item 18: 0 +write_item 17: 0 +write_item 16: 0 +write_item 15: 0 +write_item 14: 0 +write_item 13: 0 +write_item 12: 0 +write_item 11: 0 +write_item 10: 0 +write_item 9: 0 +write_item 8: 0 +write_item 7: 0 +write_item 6: 0 +write_item 5: 0 +write_item 4: 0 +write_item 3: 0 +write_item 2: 0 +write_item 1: 0 +write_item 0: 0 +reg 0: 0 +reg 1: 0 +reg 2: 0 +reg 3: 0 +reg 4: 1 +reg 5: 1 +reg 6: 0 +reg 7: 0 +reg 8: 0 +reg 9: 0 +reg 10: 0 +reg 11: 0 +reg 12: 0 +reg 13: 0 +reg 14: 0 +reg 15: 0 +reg 16: 0 +reg 17: 1 +reg 18: 0 +reg 19: 0 +reg 20: 1 +reg 21: 0 +reg 22: 1 +reg 23: 0 +reg 24: 0 +reg 25: 0 +reg 26: 0 +reg 27: 0 +reg 28: 0 +reg 29: 0 +reg 30: 0 +reg 31: 0 +reg 32: 0 +reg 33: 0 +reg 34: 0 +reg 35: 0 +reg 36: 0 +reg 37: 0 +reg 38: 0 +reg 39: 0 +reg 40: 0 +reg 41: 0 +reg 42: 0 +reg 43: 0 +reg 44: 0 +reg 45: 0 +reg 46: 0 +reg 47: 0 +reg 48: 0 +reg 49: 0 +reg 50: 0 +reg 51: 0 +reg 52: 0 +reg 53: 0 +reg 54: 0 +reg 55: 0 +reg 56: 0 +reg 57: 0 +reg 58: 0 +reg 59: 0 +reg 60: 0 +reg 61: 0 +reg 62: 0 +reg 63: 0 +write_item 0000110000000000010000010000000000000000000000000000000000000000 +write_item 63: 0 +write_item 62: 0 +write_item 61: 0 +write_item 60: 0 +write_item 59: 1 +write_item 58: 1 +write_item 57: 0 +write_item 56: 0 +write_item 55: 0 +write_item 54: 0 +write_item 53: 0 +write_item 52: 0 +write_item 51: 0 +write_item 50: 0 +write_item 49: 0 +write_item 48: 0 +write_item 47: 0 +write_item 46: 1 +write_item 45: 0 +write_item 44: 0 +write_item 43: 0 +write_item 42: 0 +write_item 41: 0 +write_item 40: 1 +write_item 39: 0 +write_item 38: 0 +write_item 37: 0 +write_item 36: 0 +write_item 35: 0 +write_item 34: 0 +write_item 33: 0 +write_item 32: 0 +write_item 31: 0 +write_item 30: 0 +write_item 29: 0 +write_item 28: 0 +write_item 27: 0 +write_item 26: 0 +write_item 25: 0 +write_item 24: 0 +write_item 23: 0 +write_item 22: 0 +write_item 21: 0 +write_item 20: 0 +write_item 19: 0 +write_item 18: 0 +write_item 17: 0 +write_item 16: 0 +write_item 15: 0 +write_item 14: 0 +write_item 13: 0 +write_item 12: 0 +write_item 11: 0 +write_item 10: 0 +write_item 9: 0 +write_item 8: 0 +write_item 7: 0 +write_item 6: 0 +write_item 5: 0 +write_item 4: 0 +write_item 3: 0 +write_item 2: 0 +write_item 1: 0 +write_item 0: 0 +reg 0: 0 +reg 1: 0 +reg 2: 0 +reg 3: 0 +reg 4: 1 +reg 5: 1 +reg 6: 0 +reg 7: 0 +reg 8: 0 +reg 9: 0 +reg 10: 0 +reg 11: 0 +reg 12: 0 +reg 13: 0 +reg 14: 0 +reg 15: 0 +reg 16: 0 +reg 17: 1 +reg 18: 0 +reg 19: 0 +reg 20: 0 +reg 21: 0 +reg 22: 0 +reg 23: 1 +reg 24: 0 +reg 25: 0 +reg 26: 0 +reg 27: 0 +reg 28: 0 +reg 29: 0 +reg 30: 0 +reg 31: 0 +reg 32: 0 +reg 33: 0 +reg 34: 0 +reg 35: 0 +reg 36: 0 +reg 37: 0 +reg 38: 0 +reg 39: 0 +reg 40: 0 +reg 41: 0 +reg 42: 0 +reg 43: 0 +reg 44: 0 +reg 45: 0 +reg 46: 0 +reg 47: 0 +reg 48: 0 +reg 49: 0 +reg 50: 0 +reg 51: 0 +reg 52: 0 +reg 53: 0 +reg 54: 0 +reg 55: 0 +reg 56: 0 +reg 57: 0 +reg 58: 0 +reg 59: 0 +reg 60: 0 +reg 61: 0 +reg 62: 0 +reg 63: 0 +write_item 0000110000000000011001000000000000000000000000000000000000000001 +write_item 63: 0 +write_item 62: 0 +write_item 61: 0 +write_item 60: 0 +write_item 59: 1 +write_item 58: 1 +write_item 57: 0 +write_item 56: 0 +write_item 55: 0 +write_item 54: 0 +write_item 53: 0 +write_item 52: 0 +write_item 51: 0 +write_item 50: 0 +write_item 49: 0 +write_item 48: 0 +write_item 47: 0 +write_item 46: 1 +write_item 45: 1 +write_item 44: 0 +write_item 43: 0 +write_item 42: 1 +write_item 41: 0 +write_item 40: 0 +write_item 39: 0 +write_item 38: 0 +write_item 37: 0 +write_item 36: 0 +write_item 35: 0 +write_item 34: 0 +write_item 33: 0 +write_item 32: 0 +write_item 31: 0 +write_item 30: 0 +write_item 29: 0 +write_item 28: 0 +write_item 27: 0 +write_item 26: 0 +write_item 25: 0 +write_item 24: 0 +write_item 23: 0 +write_item 22: 0 +write_item 21: 0 +write_item 20: 0 +write_item 19: 0 +write_item 18: 0 +write_item 17: 0 +write_item 16: 0 +write_item 15: 0 +write_item 14: 0 +write_item 13: 0 +write_item 12: 0 +write_item 11: 0 +write_item 10: 0 +write_item 9: 0 +write_item 8: 0 +write_item 7: 0 +write_item 6: 0 +write_item 5: 0 +write_item 4: 0 +write_item 3: 0 +write_item 2: 0 +write_item 1: 0 +write_item 0: 1 +reg 0: 0 +reg 1: 0 +reg 2: 0 +reg 3: 0 +reg 4: 1 +reg 5: 1 +reg 6: 0 +reg 7: 0 +reg 8: 0 +reg 9: 0 +reg 10: 0 +reg 11: 0 +reg 12: 0 +reg 13: 0 +reg 14: 0 +reg 15: 0 +reg 16: 0 +reg 17: 1 +reg 18: 1 +reg 19: 0 +reg 20: 0 +reg 21: 1 +reg 22: 0 +reg 23: 0 +reg 24: 0 +reg 25: 0 +reg 26: 0 +reg 27: 0 +reg 28: 0 +reg 29: 0 +reg 30: 0 +reg 31: 0 +reg 32: 0 +reg 33: 0 +reg 34: 0 +reg 35: 0 +reg 36: 0 +reg 37: 0 +reg 38: 0 +reg 39: 0 +reg 40: 0 +reg 41: 0 +reg 42: 0 +reg 43: 0 +reg 44: 0 +reg 45: 0 +reg 46: 0 +reg 47: 0 +reg 48: 0 +reg 49: 0 +reg 50: 0 +reg 51: 0 +reg 52: 0 +reg 53: 0 +reg 54: 0 +reg 55: 0 +reg 56: 0 +reg 57: 0 +reg 58: 0 +reg 59: 0 +reg 60: 0 +reg 61: 0 +reg 62: 0 +reg 63: 1 +write_item 0000110000000000011100010000000000000000000000000000000000000000 +write_item 63: 0 +write_item 62: 0 +write_item 61: 0 +write_item 60: 0 +write_item 59: 1 +write_item 58: 1 +write_item 57: 0 +write_item 56: 0 +write_item 55: 0 +write_item 54: 0 +write_item 53: 0 +write_item 52: 0 +write_item 51: 0 +write_item 50: 0 +write_item 49: 0 +write_item 48: 0 +write_item 47: 0 +write_item 46: 1 +write_item 45: 1 +write_item 44: 1 +write_item 43: 0 +write_item 42: 0 +write_item 41: 0 +write_item 40: 1 +write_item 39: 0 +write_item 38: 0 +write_item 37: 0 +write_item 36: 0 +write_item 35: 0 +write_item 34: 0 +write_item 33: 0 +write_item 32: 0 +write_item 31: 0 +write_item 30: 0 +write_item 29: 0 +write_item 28: 0 +write_item 27: 0 +write_item 26: 0 +write_item 25: 0 +write_item 24: 0 +write_item 23: 0 +write_item 22: 0 +write_item 21: 0 +write_item 20: 0 +write_item 19: 0 +write_item 18: 0 +write_item 17: 0 +write_item 16: 0 +write_item 15: 0 +write_item 14: 0 +write_item 13: 0 +write_item 12: 0 +write_item 11: 0 +write_item 10: 0 +write_item 9: 0 +write_item 8: 0 +write_item 7: 0 +write_item 6: 0 +write_item 5: 0 +write_item 4: 0 +write_item 3: 0 +write_item 2: 0 +write_item 1: 0 +write_item 0: 0 +reg 0: 0 +reg 1: 0 +reg 2: 0 +reg 3: 0 +reg 4: 1 +reg 5: 1 +reg 6: 0 +reg 7: 0 +reg 8: 0 +reg 9: 0 +reg 10: 0 +reg 11: 0 +reg 12: 0 +reg 13: 0 +reg 14: 0 +reg 15: 0 +reg 16: 0 +reg 17: 1 +reg 18: 1 +reg 19: 1 +reg 20: 0 +reg 21: 0 +reg 22: 0 +reg 23: 1 +reg 24: 0 +reg 25: 0 +reg 26: 0 +reg 27: 0 +reg 28: 0 +reg 29: 0 +reg 30: 0 +reg 31: 0 +reg 32: 0 +reg 33: 0 +reg 34: 0 +reg 35: 0 +reg 36: 0 +reg 37: 0 +reg 38: 0 +reg 39: 0 +reg 40: 0 +reg 41: 0 +reg 42: 0 +reg 43: 0 +reg 44: 0 +reg 45: 0 +reg 46: 0 +reg 47: 0 +reg 48: 0 +reg 49: 0 +reg 50: 0 +reg 51: 0 +reg 52: 0 +reg 53: 0 +reg 54: 0 +reg 55: 0 +reg 56: 0 +reg 57: 0 +reg 58: 0 +reg 59: 0 +reg 60: 0 +reg 61: 0 +reg 62: 0 +reg 63: 0 +write_item 0000110000000000010000110000000000101010101010101010101010101010 +write_item 63: 0 +write_item 62: 0 +write_item 61: 0 +write_item 60: 0 +write_item 59: 1 +write_item 58: 1 +write_item 57: 0 +write_item 56: 0 +write_item 55: 0 +write_item 54: 0 +write_item 53: 0 +write_item 52: 0 +write_item 51: 0 +write_item 50: 0 +write_item 49: 0 +write_item 48: 0 +write_item 47: 0 +write_item 46: 1 +write_item 45: 0 +write_item 44: 0 +write_item 43: 0 +write_item 42: 0 +write_item 41: 1 +write_item 40: 1 +write_item 39: 0 +write_item 38: 0 +write_item 37: 0 +write_item 36: 0 +write_item 35: 0 +write_item 34: 0 +write_item 33: 0 +write_item 32: 0 +write_item 31: 0 +write_item 30: 0 +write_item 29: 1 +write_item 28: 0 +write_item 27: 1 +write_item 26: 0 +write_item 25: 1 +write_item 24: 0 +write_item 23: 1 +write_item 22: 0 +write_item 21: 1 +write_item 20: 0 +write_item 19: 1 +write_item 18: 0 +write_item 17: 1 +write_item 16: 0 +write_item 15: 1 +write_item 14: 0 +write_item 13: 1 +write_item 12: 0 +write_item 11: 1 +write_item 10: 0 +write_item 9: 1 +write_item 8: 0 +write_item 7: 1 +write_item 6: 0 +write_item 5: 1 +write_item 4: 0 +write_item 3: 1 +write_item 2: 0 +write_item 1: 1 +write_item 0: 0 +reg 0: 0 +reg 1: 0 +reg 2: 0 +reg 3: 0 +reg 4: 1 +reg 5: 1 +reg 6: 0 +reg 7: 0 +reg 8: 0 +reg 9: 0 +reg 10: 0 +reg 11: 0 +reg 12: 0 +reg 13: 0 +reg 14: 0 +reg 15: 0 +reg 16: 0 +reg 17: 1 +reg 18: 0 +reg 19: 0 +reg 20: 0 +reg 21: 0 +reg 22: 1 +reg 23: 1 +reg 24: 0 +reg 25: 0 +reg 26: 0 +reg 27: 0 +reg 28: 0 +reg 29: 0 +reg 30: 0 +reg 31: 0 +reg 32: 0 +reg 33: 0 +reg 34: 1 +reg 35: 0 +reg 36: 1 +reg 37: 0 +reg 38: 1 +reg 39: 0 +reg 40: 1 +reg 41: 0 +reg 42: 1 +reg 43: 0 +reg 44: 1 +reg 45: 0 +reg 46: 1 +reg 47: 0 +reg 48: 1 +reg 49: 0 +reg 50: 1 +reg 51: 0 +reg 52: 1 +reg 53: 0 +reg 54: 1 +reg 55: 0 +reg 56: 1 +reg 57: 0 +reg 58: 1 +reg 59: 0 +reg 60: 1 +reg 61: 0 +reg 62: 1 +reg 63: 0 +write_item 0000110000000000010001000000000000101010101010100000000000000000 +write_item 63: 0 +write_item 62: 0 +write_item 61: 0 +write_item 60: 0 +write_item 59: 1 +write_item 58: 1 +write_item 57: 0 +write_item 56: 0 +write_item 55: 0 +write_item 54: 0 +write_item 53: 0 +write_item 52: 0 +write_item 51: 0 +write_item 50: 0 +write_item 49: 0 +write_item 48: 0 +write_item 47: 0 +write_item 46: 1 +write_item 45: 0 +write_item 44: 0 +write_item 43: 0 +write_item 42: 1 +write_item 41: 0 +write_item 40: 0 +write_item 39: 0 +write_item 38: 0 +write_item 37: 0 +write_item 36: 0 +write_item 35: 0 +write_item 34: 0 +write_item 33: 0 +write_item 32: 0 +write_item 31: 0 +write_item 30: 0 +write_item 29: 1 +write_item 28: 0 +write_item 27: 1 +write_item 26: 0 +write_item 25: 1 +write_item 24: 0 +write_item 23: 1 +write_item 22: 0 +write_item 21: 1 +write_item 20: 0 +write_item 19: 1 +write_item 18: 0 +write_item 17: 1 +write_item 16: 0 +write_item 15: 0 +write_item 14: 0 +write_item 13: 0 +write_item 12: 0 +write_item 11: 0 +write_item 10: 0 +write_item 9: 0 +write_item 8: 0 +write_item 7: 0 +write_item 6: 0 +write_item 5: 0 +write_item 4: 0 +write_item 3: 0 +write_item 2: 0 +write_item 1: 0 +write_item 0: 0 +reg 0: 0 +reg 1: 0 +reg 2: 0 +reg 3: 0 +reg 4: 1 +reg 5: 1 +reg 6: 0 +reg 7: 0 +reg 8: 0 +reg 9: 0 +reg 10: 0 +reg 11: 0 +reg 12: 0 +reg 13: 0 +reg 14: 0 +reg 15: 0 +reg 16: 0 +reg 17: 1 +reg 18: 0 +reg 19: 0 +reg 20: 0 +reg 21: 1 +reg 22: 0 +reg 23: 0 +reg 24: 0 +reg 25: 0 +reg 26: 0 +reg 27: 0 +reg 28: 0 +reg 29: 0 +reg 30: 0 +reg 31: 0 +reg 32: 0 +reg 33: 0 +reg 34: 1 +reg 35: 0 +reg 36: 1 +reg 37: 0 +reg 38: 1 +reg 39: 0 +reg 40: 1 +reg 41: 0 +reg 42: 1 +reg 43: 0 +reg 44: 1 +reg 45: 0 +reg 46: 1 +reg 47: 0 +reg 48: 0 +reg 49: 0 +reg 50: 0 +reg 51: 0 +reg 52: 0 +reg 53: 0 +reg 54: 0 +reg 55: 0 +reg 56: 0 +reg 57: 0 +reg 58: 0 +reg 59: 0 +reg 60: 0 +reg 61: 0 +reg 62: 0 +reg 63: 0 +write_item 0000110000000000010001100000000000000000000000000000000000000000 +write_item 63: 0 +write_item 62: 0 +write_item 61: 0 +write_item 60: 0 +write_item 59: 1 +write_item 58: 1 +write_item 57: 0 +write_item 56: 0 +write_item 55: 0 +write_item 54: 0 +write_item 53: 0 +write_item 52: 0 +write_item 51: 0 +write_item 50: 0 +write_item 49: 0 +write_item 48: 0 +write_item 47: 0 +write_item 46: 1 +write_item 45: 0 +write_item 44: 0 +write_item 43: 0 +write_item 42: 1 +write_item 41: 1 +write_item 40: 0 +write_item 39: 0 +write_item 38: 0 +write_item 37: 0 +write_item 36: 0 +write_item 35: 0 +write_item 34: 0 +write_item 33: 0 +write_item 32: 0 +write_item 31: 0 +write_item 30: 0 +write_item 29: 0 +write_item 28: 0 +write_item 27: 0 +write_item 26: 0 +write_item 25: 0 +write_item 24: 0 +write_item 23: 0 +write_item 22: 0 +write_item 21: 0 +write_item 20: 0 +write_item 19: 0 +write_item 18: 0 +write_item 17: 0 +write_item 16: 0 +write_item 15: 0 +write_item 14: 0 +write_item 13: 0 +write_item 12: 0 +write_item 11: 0 +write_item 10: 0 +write_item 9: 0 +write_item 8: 0 +write_item 7: 0 +write_item 6: 0 +write_item 5: 0 +write_item 4: 0 +write_item 3: 0 +write_item 2: 0 +write_item 1: 0 +write_item 0: 0 +reg 0: 0 +reg 1: 0 +reg 2: 0 +reg 3: 0 +reg 4: 1 +reg 5: 1 +reg 6: 0 +reg 7: 0 +reg 8: 0 +reg 9: 0 +reg 10: 0 +reg 11: 0 +reg 12: 0 +reg 13: 0 +reg 14: 0 +reg 15: 0 +reg 16: 0 +reg 17: 1 +reg 18: 0 +reg 19: 0 +reg 20: 0 +reg 21: 1 +reg 22: 1 +reg 23: 0 +reg 24: 0 +reg 25: 0 +reg 26: 0 +reg 27: 0 +reg 28: 0 +reg 29: 0 +reg 30: 0 +reg 31: 0 +reg 32: 0 +reg 33: 0 +reg 34: 0 +reg 35: 0 +reg 36: 0 +reg 37: 0 +reg 38: 0 +reg 39: 0 +reg 40: 0 +reg 41: 0 +reg 42: 0 +reg 43: 0 +reg 44: 0 +reg 45: 0 +reg 46: 0 +reg 47: 0 +reg 48: 0 +reg 49: 0 +reg 50: 0 +reg 51: 0 +reg 52: 0 +reg 53: 0 +reg 54: 0 +reg 55: 0 +reg 56: 0 +reg 57: 0 +reg 58: 0 +reg 59: 0 +reg 60: 0 +reg 61: 0 +reg 62: 0 +reg 63: 0 +write_item 0000110000000000010001110000000000000000000000000000000000000001 +write_item 63: 0 +write_item 62: 0 +write_item 61: 0 +write_item 60: 0 +write_item 59: 1 +write_item 58: 1 +write_item 57: 0 +write_item 56: 0 +write_item 55: 0 +write_item 54: 0 +write_item 53: 0 +write_item 52: 0 +write_item 51: 0 +write_item 50: 0 +write_item 49: 0 +write_item 48: 0 +write_item 47: 0 +write_item 46: 1 +write_item 45: 0 +write_item 44: 0 +write_item 43: 0 +write_item 42: 1 +write_item 41: 1 +write_item 40: 1 +write_item 39: 0 +write_item 38: 0 +write_item 37: 0 +write_item 36: 0 +write_item 35: 0 +write_item 34: 0 +write_item 33: 0 +write_item 32: 0 +write_item 31: 0 +write_item 30: 0 +write_item 29: 0 +write_item 28: 0 +write_item 27: 0 +write_item 26: 0 +write_item 25: 0 +write_item 24: 0 +write_item 23: 0 +write_item 22: 0 +write_item 21: 0 +write_item 20: 0 +write_item 19: 0 +write_item 18: 0 +write_item 17: 0 +write_item 16: 0 +write_item 15: 0 +write_item 14: 0 +write_item 13: 0 +write_item 12: 0 +write_item 11: 0 +write_item 10: 0 +write_item 9: 0 +write_item 8: 0 +write_item 7: 0 +write_item 6: 0 +write_item 5: 0 +write_item 4: 0 +write_item 3: 0 +write_item 2: 0 +write_item 1: 0 +write_item 0: 1 +reg 0: 0 +reg 1: 0 +reg 2: 0 +reg 3: 0 +reg 4: 1 +reg 5: 1 +reg 6: 0 +reg 7: 0 +reg 8: 0 +reg 9: 0 +reg 10: 0 +reg 11: 0 +reg 12: 0 +reg 13: 0 +reg 14: 0 +reg 15: 0 +reg 16: 0 +reg 17: 1 +reg 18: 0 +reg 19: 0 +reg 20: 0 +reg 21: 1 +reg 22: 1 +reg 23: 1 +reg 24: 0 +reg 25: 0 +reg 26: 0 +reg 27: 0 +reg 28: 0 +reg 29: 0 +reg 30: 0 +reg 31: 0 +reg 32: 0 +reg 33: 0 +reg 34: 0 +reg 35: 0 +reg 36: 0 +reg 37: 0 +reg 38: 0 +reg 39: 0 +reg 40: 0 +reg 41: 0 +reg 42: 0 +reg 43: 0 +reg 44: 0 +reg 45: 0 +reg 46: 0 +reg 47: 0 +reg 48: 0 +reg 49: 0 +reg 50: 0 +reg 51: 0 +reg 52: 0 +reg 53: 0 +reg 54: 0 +reg 55: 0 +reg 56: 0 +reg 57: 0 +reg 58: 0 +reg 59: 0 +reg 60: 0 +reg 61: 0 +reg 62: 0 +reg 63: 1 +write_item 0000110000000000010010000000000000000000000000000000000000000000 +write_item 63: 0 +write_item 62: 0 +write_item 61: 0 +write_item 60: 0 +write_item 59: 1 +write_item 58: 1 +write_item 57: 0 +write_item 56: 0 +write_item 55: 0 +write_item 54: 0 +write_item 53: 0 +write_item 52: 0 +write_item 51: 0 +write_item 50: 0 +write_item 49: 0 +write_item 48: 0 +write_item 47: 0 +write_item 46: 1 +write_item 45: 0 +write_item 44: 0 +write_item 43: 1 +write_item 42: 0 +write_item 41: 0 +write_item 40: 0 +write_item 39: 0 +write_item 38: 0 +write_item 37: 0 +write_item 36: 0 +write_item 35: 0 +write_item 34: 0 +write_item 33: 0 +write_item 32: 0 +write_item 31: 0 +write_item 30: 0 +write_item 29: 0 +write_item 28: 0 +write_item 27: 0 +write_item 26: 0 +write_item 25: 0 +write_item 24: 0 +write_item 23: 0 +write_item 22: 0 +write_item 21: 0 +write_item 20: 0 +write_item 19: 0 +write_item 18: 0 +write_item 17: 0 +write_item 16: 0 +write_item 15: 0 +write_item 14: 0 +write_item 13: 0 +write_item 12: 0 +write_item 11: 0 +write_item 10: 0 +write_item 9: 0 +write_item 8: 0 +write_item 7: 0 +write_item 6: 0 +write_item 5: 0 +write_item 4: 0 +write_item 3: 0 +write_item 2: 0 +write_item 1: 0 +write_item 0: 0 +reg 0: 0 +reg 1: 0 +reg 2: 0 +reg 3: 0 +reg 4: 1 +reg 5: 1 +reg 6: 0 +reg 7: 0 +reg 8: 0 +reg 9: 0 +reg 10: 0 +reg 11: 0 +reg 12: 0 +reg 13: 0 +reg 14: 0 +reg 15: 0 +reg 16: 0 +reg 17: 1 +reg 18: 0 +reg 19: 0 +reg 20: 1 +reg 21: 0 +reg 22: 0 +reg 23: 0 +reg 24: 0 +reg 25: 0 +reg 26: 0 +reg 27: 0 +reg 28: 0 +reg 29: 0 +reg 30: 0 +reg 31: 0 +reg 32: 0 +reg 33: 0 +reg 34: 0 +reg 35: 0 +reg 36: 0 +reg 37: 0 +reg 38: 0 +reg 39: 0 +reg 40: 0 +reg 41: 0 +reg 42: 0 +reg 43: 0 +reg 44: 0 +reg 45: 0 +reg 46: 0 +reg 47: 0 +reg 48: 0 +reg 49: 0 +reg 50: 0 +reg 51: 0 +reg 52: 0 +reg 53: 0 +reg 54: 0 +reg 55: 0 +reg 56: 0 +reg 57: 0 +reg 58: 0 +reg 59: 0 +reg 60: 0 +reg 61: 0 +reg 62: 0 +reg 63: 0 +Line 0: 0 +Line 1: 0 +Line 2: 0 +Line 3: 0 +Line 4: 0 +Line 5: 1 +Line 6: 0 +Line 7: 0 +Line 8: 0 +Line 9: 0 +Line 10: 0 +Line 11: 0 +Line 12: 0 +Line 13: 0 +Line 14: 0 +Line 15: 0 +Line 16: 0 +Line 17: 0 +Line 18: 0 +Line 19: 0 +Line 20: 0 +Line 21: 0 +Line 22: 0 +Line 23: 0 +Line 24: 0 +Line 25: 0 +Line 26: 0 +Line 27: 0 +Line 28: 0 +Line 29: 0 +Line 30: 0 +Line 31: 0 +Line 32: 0 +Line 33: 0 +Line 34: 1 +Line 35: 1 +Line 36: 1 +Line 37: 1 +Line 38: 1 +Line 39: 0 +Line 40: 1 +Line 41: 0 +Line 42: 0 +Line 43: 0 +Line 44: 0 +Line 45: 0 +Line 46: 0 +Line 47: 0 +Line 48: 0 +Line 49: 0 +Line 50: 0 +Line 51: 0 +Line 52: 0 +Line 53: 0 +Line 54: 0 +Line 55: 0 +Line 56: 1 +Line 57: 0 +Line 58: 0 +Line 59: 1 +Line 60: 0 +Line 61: 0 +Line 62: 1 +Line 63: 1 +Line 64: 0 +Line 65: 0 +Line 66: 0 +Line 67: 0 +Line 68: 0 +Line 69: 0 +Line 70: 0 +Line 71: 0 +Line 72: 0 +Line 73: 0 +Line 74: 1 +Line 75: 0 +Line 76: 0 +Line 77: 0 +Line 78: 0 +Line 79: 0 +Line 80: 0 +Line 81: 0 +Line 82: 0 +Line 83: 0 +Line 84: 0 +Line 85: 0 +Line 86: 0 +Line 87: 1 +Line 88: 1 +Line 89: 0 +Line 90: 1 +Line 91: 1 +Line 92: 0 +Line 93: 1 +Line 94: 1 +Line 95: 1 +Line 96: 0 +Line 97: 1 +Line 98: 1 +Line 99: 0 +Line 100: 0 +Line 101: 1 +Line 102: 1 +Line 103: 0 +Line 104: 0 +Line 105: 1 +Line 106: 1 +Line 107: 0 +Line 108: 0 +Line 109: 1 +Line 110: 1 +Line 111: 0 +Line 112: 0 +Line 113: 1 +Line 114: 1 +Line 115: 0 +Line 116: 0 +Line 117: 1 +Line 118: 0 +Line 119: 0 +Line 120: 0 +Line 121: 0 +Line 122: 1 +Line 123: 1 +Line 124: 0 +Line 125: 1 +Line 126: 1 +Line 127: 1 +Line 128: 0 +Line 129: 0 +Line 130: 0 +Line 131: 0 +Line 132: 0 +Line 133: 1 +Line 134: 0 +Line 135: 0 +Line 136: 1 +Line 137: 0 +Line 138: 0 +Line 139: 0 +Line 140: 0 +Line 141: 0 +Line 142: 0 +Line 143: 1 +Line 144: 1 +Line 145: 0 +Line 146: 1 +Line 147: 0 +Line 148: 0 +Line 149: 0 +Line 150: 0 +Line 151: 0 +Line 152: 0 +Line 153: 0 +Line 154: 1 +Line 155: 0 +Line 156: 0 +Line 157: 0 +Line 158: 1 +Line 159: 1 +Line 160: 0 +Line 161: 0 +Line 162: 1 +Line 163: 1 +Line 164: 0 +Line 165: 0 +Line 166: 1 +Line 167: 1 +Line 168: 0 +Line 169: 0 +Line 170: 1 +Line 171: 1 +Line 172: 0 +Line 173: 0 +Line 174: 1 +Line 175: 1 +Line 176: 0 +Line 177: 0 +Line 178: 1 +Line 179: 1 +Line 180: 0 +Line 181: 1 +Line 182: 0 +Line 183: 0 +Line 184: 0 +Line 185: 0 +Line 186: 1 +Line 187: 1 +Line 188: 0 +Line 189: 1 +Line 190: 1 +Line 191: 1 +Line 192: 0 +Line 193: 0 +Line 194: 0 +Line 195: 0 +Line 196: 0 +Line 197: 1 +Line 198: 0 +Line 199: 0 +Line 200: 1 +Line 201: 0 +Line 202: 0 +Line 203: 0 +Line 204: 0 +Line 205: 0 +Line 206: 0 +Line 207: 1 +Line 208: 1 +Line 209: 0 +Line 210: 1 +Line 211: 0 +Line 212: 0 +Line 213: 0 +Line 214: 1 +Line 215: 0 +Line 216: 0 +Line 217: 0 +Line 218: 1 +Line 219: 0 +Line 220: 0 +Line 221: 0 +Line 222: 1 +Line 223: 1 +Line 224: 0 +Line 225: 0 +Line 226: 0 +Line 227: 0 +Line 228: 0 +Line 229: 0 +Line 230: 0 +Line 231: 0 +Line 232: 0 +Line 233: 0 +Line 234: 0 +Line 235: 0 +Line 236: 0 +Line 237: 0 +Line 238: 0 +Line 239: 0 +Line 240: 0 +Line 241: 0 +Line 242: 0 +Line 243: 0 +Line 244: 0 +Line 245: 1 +Line 246: 0 +Line 247: 0 +Line 248: 1 +Line 249: 0 +Line 250: 1 +Line 251: 1 +Line 252: 0 +Line 253: 1 +Line 254: 1 +Line 255: 1 +Line 256: 0 +Line 257: 0 +Line 258: 0 +Line 259: 0 +Line 260: 0 +Line 261: 1 +Line 262: 0 +Line 263: 0 +Line 264: 1 +Line 265: 0 +Line 266: 0 +Line 267: 1 +Line 268: 0 +Line 269: 0 +Line 270: 0 +Line 271: 1 +Line 272: 1 +Line 273: 0 +Line 274: 1 +Line 275: 0 +Line 276: 1 +Line 277: 0 +Line 278: 1 +Line 279: 0 +Line 280: 0 +Line 281: 0 +Line 282: 1 +Line 283: 0 +Line 284: 0 +Line 285: 0 +Line 286: 1 +Line 287: 1 +Line 288: 0 +Line 289: 0 +Line 290: 1 +Line 291: 1 +Line 292: 1 +Line 293: 1 +Line 294: 1 +Line 295: 1 +Line 296: 1 +Line 297: 1 +Line 298: 1 +Line 299: 1 +Line 300: 1 +Line 301: 1 +Line 302: 1 +Line 303: 1 +Line 304: 0 +Line 305: 0 +Line 306: 0 +Line 307: 0 +Line 308: 0 +Line 309: 1 +Line 310: 0 +Line 311: 0 +Line 312: 1 +Line 313: 0 +Line 314: 1 +Line 315: 1 +Line 316: 0 +Line 317: 1 +Line 318: 1 +Line 319: 1 +Line 320: 0 +Line 321: 0 +Line 322: 0 +Line 323: 0 +Line 324: 0 +Line 325: 1 +Line 326: 0 +Line 327: 0 +Line 328: 1 +Line 329: 0 +Line 330: 0 +Line 331: 1 +Line 332: 0 +Line 333: 0 +Line 334: 0 +Line 335: 1 +Line 336: 1 +Line 337: 0 +Line 338: 1 +Line 339: 0 +Line 340: 1 +Line 341: 1 +Line 342: 0 +Line 343: 0 +Line 344: 0 +Line 345: 0 +Line 346: 1 +Line 347: 0 +Line 348: 0 +Line 349: 0 +Line 350: 1 +Line 351: 1 +Line 352: 0 +Line 353: 0 +Line 354: 0 +Line 355: 1 +Line 356: 1 +Line 357: 1 +Line 358: 1 +Line 359: 1 +Line 360: 1 +Line 361: 1 +Line 362: 1 +Line 363: 1 +Line 364: 1 +Line 365: 1 +Line 366: 1 +Line 367: 1 +Line 368: 0 +Line 369: 0 +Line 370: 0 +Line 371: 0 +Line 372: 0 +Line 373: 1 +Line 374: 0 +Line 375: 0 +Line 376: 1 +Line 377: 0 +Line 378: 1 +Line 379: 1 +Line 380: 0 +Line 381: 1 +Line 382: 1 +Line 383: 1 +Line 384: 0 +Line 385: 0 +Line 386: 0 +Line 387: 0 +Line 388: 0 +Line 389: 1 +Line 390: 0 +Line 391: 0 +Line 392: 1 +Line 393: 0 +Line 394: 0 +Line 395: 1 +Line 396: 0 +Line 397: 0 +Line 398: 0 +Line 399: 1 +Line 400: 1 +Line 401: 0 +Line 402: 1 +Line 403: 0 +Line 404: 1 +Line 405: 1 +Line 406: 1 +Line 407: 0 +Line 408: 0 +Line 409: 0 +Line 410: 1 +Line 411: 0 +Line 412: 0 +Line 413: 0 +Line 414: 1 +Line 415: 1 +Line 416: 0 +Line 417: 1 +Line 418: 1 +Line 419: 1 +Line 420: 1 +Line 421: 1 +Line 422: 1 +Line 423: 1 +Line 424: 1 +Line 425: 1 +Line 426: 1 +Line 427: 1 +Line 428: 1 +Line 429: 1 +Line 430: 1 +Line 431: 1 +Line 432: 0 +Line 433: 0 +Line 434: 0 +Line 435: 0 +Line 436: 0 +Line 437: 1 +Line 438: 0 +Line 439: 1 +Line 440: 0 +Line 441: 0 +Line 442: 1 +Line 443: 1 +Line 444: 0 +Line 445: 1 +Line 446: 1 +Line 447: 1 +Line 448: 0 +Line 449: 0 +Line 450: 0 +Line 451: 0 +Line 452: 0 +Line 453: 1 +Line 454: 1 +Line 455: 0 +Line 456: 1 +Line 457: 0 +Line 458: 1 +Line 459: 0 +Line 460: 0 +Line 461: 0 +Line 462: 0 +Line 463: 1 +Line 464: 1 +Line 465: 0 +Line 466: 1 +Line 467: 0 +Line 468: 1 +Line 469: 1 +Line 470: 0 +Line 471: 0 +Line 472: 0 +Line 473: 0 +Line 474: 1 +Line 475: 0 +Line 476: 0 +Line 477: 0 +Line 478: 1 +Line 479: 1 +Line 480: 0 +Line 481: 0 +Line 482: 1 +Line 483: 1 +Line 484: 1 +Line 485: 1 +Line 486: 1 +Line 487: 1 +Line 488: 1 +Line 489: 1 +Line 490: 1 +Line 491: 1 +Line 492: 1 +Line 493: 1 +Line 494: 1 +Line 495: 1 +Line 496: 0 +Line 497: 0 +Line 498: 0 +Line 499: 0 +Line 500: 0 +Line 501: 1 +Line 502: 0 +Line 503: 1 +Line 504: 0 +Line 505: 0 +Line 506: 1 +Line 507: 1 +Line 508: 0 +Line 509: 1 +Line 510: 1 +Line 511: 1 +Line 512: 0 +Line 513: 0 +Line 514: 0 +Line 515: 0 +Line 516: 0 +Line 517: 1 +Line 518: 1 +Line 519: 0 +Line 520: 1 +Line 521: 0 +Line 522: 1 +Line 523: 0 +Line 524: 0 +Line 525: 0 +Line 526: 0 +Line 527: 1 +Line 528: 1 +Line 529: 0 +Line 530: 1 +Line 531: 0 +Line 532: 1 +Line 533: 1 +Line 534: 1 +Line 535: 0 +Line 536: 0 +Line 537: 0 +Line 538: 1 +Line 539: 0 +Line 540: 0 +Line 541: 0 +Line 542: 1 +Line 543: 1 +Line 544: 0 +Line 545: 0 +Line 546: 0 +Line 547: 0 +Line 548: 0 +Line 549: 0 +Line 550: 0 +Line 551: 0 +Line 552: 1 +Line 553: 0 +Line 554: 0 +Line 555: 0 +Line 556: 0 +Line 557: 0 +Line 558: 0 +Line 559: 0 +Line 560: 0 +Line 561: 0 +Line 562: 0 +Line 563: 0 +Line 564: 0 +Line 565: 0 +Line 566: 0 +Line 567: 0 +Line 568: 0 +Line 569: 0 +Line 570: 0 +Line 571: 0 +Line 572: 1 +Line 573: 0 +Line 574: 1 +Line 575: 1 +Line 576: 0 +Line 577: 0 +Line 578: 0 +Line 579: 0 +Line 580: 0 +Line 581: 1 +Line 582: 1 +Line 583: 0 +Line 584: 0 +Line 585: 0 +Line 586: 0 +Line 587: 0 +Line 588: 0 +Line 589: 0 +Line 590: 0 +Line 591: 1 +Line 592: 1 +Line 593: 0 +Line 594: 1 +Line 595: 0 +Line 596: 1 +Line 597: 0 +Line 598: 1 +Line 599: 0 +Line 600: 0 +Line 601: 0 +Line 602: 1 +Line 603: 0 +Line 604: 0 +Line 605: 0 +Line 606: 1 +Line 607: 1 +Line 608: 0 +Line 609: 0 +Line 610: 0 +Line 611: 0 +Line 612: 0 +Line 613: 0 +Line 614: 0 +Line 615: 0 +Line 616: 0 +Line 617: 0 +Line 618: 0 +Line 619: 1 +Line 620: 0 +Line 621: 0 +Line 622: 0 +Line 623: 0 +Line 624: 0 +Line 625: 0 +Line 626: 0 +Line 627: 0 +Line 628: 0 +Line 629: 0 +Line 630: 1 +Line 631: 0 +Line 632: 0 +Line 633: 0 +Line 634: 0 +Line 635: 1 +Line 636: 0 +Line 637: 0 +Line 638: 1 +Line 639: 1 +Line 640: 0 +Line 641: 0 +Line 642: 0 +Line 643: 0 +Line 644: 0 +Line 645: 1 +Line 646: 0 +Line 647: 0 +Line 648: 0 +Line 649: 1 +Line 650: 0 +Line 651: 0 +Line 652: 0 +Line 653: 0 +Line 654: 0 +Line 655: 1 +Line 656: 1 +Line 657: 0 +Line 658: 1 +Line 659: 0 +Line 660: 1 +Line 661: 0 +Line 662: 0 +Line 663: 0 +Line 664: 0 +Line 665: 0 +Line 666: 1 +Line 667: 0 +Line 668: 0 +Line 669: 0 +Line 670: 1 +Line 671: 1 +Line 672: 0 +Line 673: 0 +Line 674: 0 +Line 675: 0 +Line 676: 0 +Line 677: 0 +Line 678: 0 +Line 679: 0 +Line 680: 0 +Line 681: 1 +Line 682: 1 +Line 683: 1 +Line 684: 0 +Line 685: 0 +Line 686: 0 +Line 687: 0 +Line 688: 0 +Line 689: 0 +Line 690: 0 +Line 691: 0 +Line 692: 0 +Line 693: 0 +Line 694: 0 +Line 695: 0 +Line 696: 0 +Line 697: 0 +Line 698: 0 +Line 699: 0 +Line 700: 1 +Line 701: 0 +Line 702: 1 +Line 703: 1 +Line 704: 0 +Line 705: 1 +Line 706: 0 +Line 707: 0 +Line 708: 0 +Line 709: 0 +Line 710: 0 +Line 711: 0 +Line 712: 1 +Line 713: 0 +Line 714: 0 +Line 715: 1 +Line 716: 0 +Line 717: 0 +Line 718: 0 +Line 719: 0 +Line 720: 0 +Line 721: 0 +Line 722: 1 +Line 723: 0 +Line 724: 0 +Line 725: 0 +Line 726: 0 +Line 727: 0 +Line 728: 0 +Line 729: 0 +Line 730: 0 +Line 731: 0 +Line 732: 1 +Line 733: 0 +Line 734: 1 +Line 735: 1 +Line 736: 0 +Line 737: 0 +Line 738: 0 +Line 739: 0 +Line 740: 0 +Line 741: 0 +Line 742: 0 +Line 743: 0 +Line 744: 0 +Line 745: 0 +Line 746: 1 +Line 747: 1 +Line 748: 0 +Line 749: 0 +Line 750: 0 +Line 751: 0 +Line 752: 0 +Line 753: 0 +Line 754: 0 +Line 755: 0 +Line 756: 0 +Line 757: 0 +Line 758: 0 +Line 759: 0 +Line 760: 0 +Line 761: 0 +Line 762: 0 +Line 763: 0 +Line 764: 1 +Line 765: 0 +Line 766: 1 +Line 767: 1 +Line 768: 0 +Line 769: 1 +Line 770: 1 +Line 771: 1 +Line 772: 1 +Line 773: 1 +Line 774: 1 +Line 775: 1 +Line 776: 1 +Line 777: 1 +Line 778: 1 +Line 779: 1 +Line 780: 1 +Line 781: 1 +Line 782: 1 +Line 783: 1 +Line 784: 0 +Line 785: 0 +Line 786: 0 +Line 787: 0 +Line 788: 0 +Line 789: 0 +Line 790: 0 +Line 791: 1 +Line 792: 0 +Line 793: 0 +Line 794: 1 +Line 795: 1 +Line 796: 0 +Line 797: 1 +Line 798: 1 +Line 799: 1 +Line 800: 0 +Line 801: 0 +Line 802: 0 +Line 803: 0 +Line 804: 0 +Line 805: 1 +Line 806: 1 +Line 807: 0 +Line 808: 0 +Line 809: 0 +Line 810: 1 +Line 811: 0 +Line 812: 0 +Line 813: 0 +Line 814: 0 +Line 815: 1 +Line 816: 1 +Line 817: 0 +Line 818: 1 +Line 819: 0 +Line 820: 1 +Line 821: 0 +Line 822: 1 +Line 823: 0 +Line 824: 0 +Line 825: 0 +Line 826: 1 +Line 827: 0 +Line 828: 0 +Line 829: 0 +Line 830: 1 +Line 831: 1 +Line 832: 0 +Line 833: 0 +Line 834: 0 +Line 835: 0 +Line 836: 0 +Line 837: 0 +Line 838: 0 +Line 839: 0 +Line 840: 0 +Line 841: 0 +Line 842: 0 +Line 843: 0 +Line 844: 0 +Line 845: 0 +Line 846: 0 +Line 847: 0 +Line 848: 0 +Line 849: 0 +Line 850: 1 +Line 851: 0 +Line 852: 0 +Line 853: 0 +Line 854: 1 +Line 855: 1 +Line 856: 0 +Line 857: 0 +Line 858: 1 +Line 859: 1 +Line 860: 0 +Line 861: 1 +Line 862: 1 +Line 863: 1 +Line 864: 0 +Line 865: 0 +Line 866: 0 +Line 867: 1 +Line 868: 0 +Line 869: 0 +Line 870: 0 +Line 871: 0 +Line 872: 0 +Line 873: 0 +Line 874: 0 +Line 875: 1 +Line 876: 0 +Line 877: 0 +Line 878: 1 +Line 879: 1 +Line 880: 0 +Line 881: 0 +Line 882: 1 +Line 883: 0 +Line 884: 0 +Line 885: 0 +Line 886: 0 +Line 887: 0 +Line 888: 0 +Line 889: 0 +Line 890: 0 +Line 891: 0 +Line 892: 1 +Line 893: 0 +Line 894: 1 +Line 895: 1 +Line 896: 0 +Line 897: 0 +Line 898: 0 +Line 899: 0 +Line 900: 0 +Line 901: 0 +Line 902: 0 +Line 903: 1 +Line 904: 0 +Line 905: 0 +Line 906: 1 +Line 907: 1 +Line 908: 0 +Line 909: 0 +Line 910: 0 +Line 911: 0 +Line 912: 0 +Line 913: 0 +Line 914: 0 +Line 915: 0 +Line 916: 0 +Line 917: 0 +Line 918: 0 +Line 919: 0 +Line 920: 0 +Line 921: 0 +Line 922: 0 +Line 923: 0 +Line 924: 1 +Line 925: 0 +Line 926: 1 +Line 927: 1 +Line 928: 0 +Line 929: 0 +Line 930: 0 +Line 931: 1 +Line 932: 0 +Line 933: 0 +Line 934: 0 +Line 935: 0 +Line 936: 0 +Line 937: 1 +Line 938: 0 +Line 939: 0 +Line 940: 0 +Line 941: 0 +Line 942: 0 +Line 943: 0 +Line 944: 0 +Line 945: 0 +Line 946: 1 +Line 947: 0 +Line 948: 0 +Line 949: 0 +Line 950: 0 +Line 951: 0 +Line 952: 0 +Line 953: 0 +Line 954: 0 +Line 955: 0 +Line 956: 1 +Line 957: 0 +Line 958: 1 +Line 959: 1 +Line 960: 0 +Line 961: 0 +Line 962: 0 +Line 963: 0 +Line 964: 0 +Line 965: 0 +Line 966: 0 +Line 967: 0 +Line 968: 0 +Line 969: 0 +Line 970: 0 +Line 971: 0 +Line 972: 0 +Line 973: 0 +Line 974: 0 +Line 975: 0 +Line 976: 0 +Line 977: 0 +Line 978: 1 +Line 979: 0 +Line 980: 0 +Line 981: 0 +Line 982: 1 +Line 983: 1 +Line 984: 0 +Line 985: 0 +Line 986: 1 +Line 987: 1 +Line 988: 0 +Line 989: 1 +Line 990: 1 +Line 991: 1 +Line 992: 0 +Line 993: 0 +Line 994: 0 +Line 995: 0 +Line 996: 0 +Line 997: 0 +Line 998: 0 +Line 999: 0 +Line 1000: 1 +Line 1001: 1 +Line 1002: 1 +Line 1003: 1 +Line 1004: 0 +Line 1005: 0 +Line 1006: 0 +Line 1007: 0 +Line 1008: 0 +Line 1009: 0 +Line 1010: 0 +Line 1011: 0 +Line 1012: 0 +Line 1013: 0 +Line 1014: 0 +Line 1015: 0 +Line 1016: 0 +Line 1017: 0 +Line 1018: 0 +Line 1019: 0 +Line 1020: 1 +Line 1021: 0 +Line 1022: 1 +Line 1023: 1 +Line 1024: 0 +Line 1025: 0 +Line 1026: 0 +Line 1027: 0 +Line 1028: 0 +Line 1029: 0 +Line 1030: 0 +Line 1031: 0 +Line 1032: 1 +Line 1033: 0 +Line 1034: 0 +Line 1035: 0 +Line 1036: 0 +Line 1037: 0 +Line 1038: 1 +Line 1039: 1 +Line 1040: 0 +Line 1041: 0 +Line 1042: 1 +Line 1043: 0 +Line 1044: 0 +Line 1045: 0 +Line 1046: 0 +Line 1047: 0 +Line 1048: 0 +Line 1049: 0 +Line 1050: 0 +Line 1051: 0 +Line 1052: 1 +Line 1053: 0 +Line 1054: 1 +Line 1055: 1 +Line 1056: 0 +Line 1057: 0 +Line 1058: 0 +Line 1059: 0 +Line 1060: 0 +Line 1061: 0 +Line 1062: 0 +Line 1063: 1 +Line 1064: 1 +Line 1065: 1 +Line 1066: 1 +Line 1067: 0 +Line 1068: 0 +Line 1069: 0 +Line 1070: 0 +Line 1071: 0 +Line 1072: 0 +Line 1073: 0 +Line 1074: 0 +Line 1075: 0 +Line 1076: 0 +Line 1077: 0 +Line 1078: 0 +Line 1079: 0 +Line 1080: 0 +Line 1081: 0 +Line 1082: 0 +Line 1083: 0 +Line 1084: 1 +Line 1085: 0 +Line 1086: 1 +Line 1087: 1 +Line 1088: 1 +Line 1089: 0 +Line 1090: 1 +Line 1091: 1 +Line 1092: 1 +Line 1093: 1 +Line 1094: 1 +Line 1095: 1 +Line 1096: 1 +Line 1097: 1 +Line 1098: 1 +Line 1099: 1 +Line 1100: 1 +Line 1101: 1 +Line 1102: 1 +Line 1103: 1 +Line 1104: 0 +Line 1105: 0 +Line 1106: 0 +Line 1107: 0 +Line 1108: 0 +Line 1109: 0 +Line 1110: 0 +Line 1111: 1 +Line 1112: 0 +Line 1113: 0 +Line 1114: 1 +Line 1115: 1 +Line 1116: 0 +Line 1117: 1 +Line 1118: 1 +Line 1119: 1 +Line 1120: 0 +Line 1121: 0 +Line 1122: 0 +Line 1123: 0 +Line 1124: 0 +Line 1125: 1 +Line 1126: 1 +Line 1127: 0 +Line 1128: 0 +Line 1129: 0 +Line 1130: 1 +Line 1131: 0 +Line 1132: 0 +Line 1133: 0 +Line 1134: 0 +Line 1135: 1 +Line 1136: 1 +Line 1137: 0 +Line 1138: 1 +Line 1139: 0 +Line 1140: 1 +Line 1141: 0 +Line 1142: 1 +Line 1143: 0 +Line 1144: 0 +Line 1145: 0 +Line 1146: 1 +Line 1147: 0 +Line 1148: 0 +Line 1149: 0 +Line 1150: 1 +Line 1151: 1 +Line 1152: 1 +Line 1153: 0 +Line 1154: 0 +Line 1155: 0 +Line 1156: 0 +Line 1157: 0 +Line 1158: 0 +Line 1159: 0 +Line 1160: 0 +Line 1161: 0 +Line 1162: 0 +Line 1163: 0 +Line 1164: 0 +Line 1165: 0 +Line 1166: 0 +Line 1167: 0 +Line 1168: 0 +Line 1169: 0 +Line 1170: 1 +Line 1171: 0 +Line 1172: 0 +Line 1173: 0 +Line 1174: 0 +Line 1175: 0 +Line 1176: 0 +Line 1177: 0 +Line 1178: 0 +Line 1179: 0 +Line 1180: 1 +Line 1181: 0 +Line 1182: 1 +Line 1183: 1 +Line 1184: 0 +Line 1185: 0 +Line 1186: 0 +Line 1187: 0 +Line 1188: 0 +Line 1189: 1 +Line 1190: 0 +Line 1191: 1 +Line 1192: 1 +Line 1193: 1 +Line 1194: 1 +Line 1195: 0 +Line 1196: 0 +Line 1197: 0 +Line 1198: 0 +Line 1199: 0 +Line 1200: 0 +Line 1201: 0 +Line 1202: 0 +Line 1203: 0 +Line 1204: 0 +Line 1205: 0 +Line 1206: 0 +Line 1207: 0 +Line 1208: 0 +Line 1209: 0 +Line 1210: 0 +Line 1211: 0 +Line 1212: 1 +Line 1213: 0 +Line 1214: 1 +Line 1215: 1 +Line 1216: 1 +Line 1217: 1 +Line 1218: 1 +Line 1219: 1 +Line 1220: 1 +Line 1221: 1 +Line 1222: 1 +Line 1223: 1 +Line 1224: 1 +Line 1225: 1 +Line 1226: 1 +Line 1227: 1 +Line 1228: 0 +Line 1229: 0 +Line 1230: 0 +Line 1231: 0 +Line 1232: 1 +Line 1233: 0 +Line 1234: 0 +Line 1235: 0 +Line 1236: 0 +Line 1237: 0 +Line 1238: 0 +Line 1239: 0 +Line 1240: 1 +Line 1241: 0 +Line 1242: 0 +Line 1243: 1 +Line 1244: 0 +Line 1245: 0 +Line 1246: 1 +Line 1247: 1 +Line 1248: 1 +Line 1249: 1 +Line 1250: 1 +Line 1251: 1 +Line 1252: 1 +Line 1253: 0 +Line 1254: 1 +Line 1255: 0 +Line 1256: 0 +Line 1257: 0 +Line 1258: 0 +Line 1259: 0 +Line 1260: 0 +Line 1261: 0 +Line 1262: 0 +Line 1263: 0 +Line 1264: 1 +Line 1265: 0 +Line 1266: 0 +Line 1267: 1 +Line 1268: 0 +Line 1269: 1 +Line 1270: 1 +Line 1271: 0 +Line 1272: 1 +Line 1273: 1 +Line 1274: 1 +Line 1275: 0 +Line 1276: 0 +Line 1277: 0 +Line 1278: 1 +Line 1279: 1 +Line 1280: 0 +Line 1281: 0 +Line 1282: 0 +Line 1283: 0 +Line 1284: 0 +Line 1285: 0 +Line 1286: 0 +Line 1287: 0 +Line 1288: 0 +Line 1289: 0 +Line 1290: 0 +Line 1291: 0 +Line 1292: 0 +Line 1293: 0 +Line 1294: 0 +Line 1295: 0 +Line 1296: 0 +Line 1297: 0 +Line 1298: 0 +Line 1299: 0 +Line 1300: 0 +Line 1301: 0 +Line 1302: 0 +Line 1303: 0 +Line 1304: 0 +Line 1305: 0 +Line 1306: 1 +Line 1307: 0 +Line 1308: 1 +Line 1309: 0 +Line 1310: 1 +Line 1311: 1 +Send MCU_INSTR_FILE +Line 0: 0 +Line 1: 0 +Line 2: 0 +Line 3: 0 +Line 4: 1 +Line 5: 0 +Line 6: 0 +Line 7: 0 +Line 8: 0 +Line 9: 0 +Line 10: 0 +Line 11: 0 +Line 12: 0 +Line 13: 0 +Line 14: 0 +Line 15: 0 +Line 16: 0 +Line 17: 0 +Line 18: 0 +Line 19: 0 +Line 20: 0 +Line 21: 0 +Line 22: 0 +Line 23: 0 +Line 24: 0 +Line 25: 0 +Line 26: 0 +Line 27: 0 +Line 28: 0 +Line 29: 0 +Line 30: 0 +Line 31: 0 +Line 32: 0 +Line 33: 0 +Line 34: 0 +Line 35: 0 +Line 36: 0 +Line 37: 0 +Line 38: 0 +Line 39: 0 +Line 40: 0 +Line 41: 0 +Line 42: 0 +Line 43: 0 +Line 44: 0 +Line 45: 0 +Line 46: 0 +Line 47: 0 +Line 48: 0 +Line 49: 0 +Line 50: 0 +Line 51: 0 +Line 52: 0 +Line 53: 0 +Line 54: 0 +Line 55: 0 +Line 56: 0 +Line 57: 0 +Line 58: 0 +Line 59: 0 +Line 60: 1 +Line 61: 0 +Line 62: 0 +Line 63: 0 +Line 64: 0 +Line 65: 0 +Line 66: 0 +Line 67: 0 +Line 68: 0 +Line 69: 0 +Line 70: 0 +Line 71: 0 +Line 72: 0 +Line 73: 0 +Line 74: 0 +Line 75: 0 +Line 76: 0 +Line 77: 0 +Line 78: 0 +Line 79: 0 +Line 80: 0 +Line 81: 0 +Line 82: 0 +Line 83: 0 +Line 84: 0 +Line 85: 0 +Line 86: 0 +Line 87: 1 +Line 88: 0 +Line 89: 0 +Line 90: 0 +Line 91: 0 +Line 92: 0 +Line 93: 0 +Line 94: 0 +Line 95: 0 +Line 96: 0 +Line 97: 0 +Line 98: 0 +Line 99: 0 +Line 100: 0 +Line 101: 0 +Line 102: 0 +Line 103: 0 +Line 104: 0 +Line 105: 0 +Line 106: 0 +Line 107: 0 +Line 108: 0 +Line 109: 0 +Line 110: 0 +Line 111: 0 +Line 112: 0 +Line 113: 0 +Line 114: 0 +Line 115: 0 +Line 116: 0 +Line 117: 0 +Line 118: 0 +Line 119: 1 +Line 120: 1 +Line 121: 0 +Line 122: 0 +Line 123: 0 +Line 124: 0 +Line 125: 0 +Line 126: 0 +Line 127: 0 +Line 128: 0 +Line 129: 1 +Line 130: 0 +Line 131: 0 +Line 132: 0 +Line 133: 0 +Line 134: 0 +Line 135: 0 +Line 136: 0 +Line 137: 0 +Line 138: 0 +Line 139: 0 +Line 140: 0 +Line 141: 0 +Line 142: 0 +Line 143: 0 +Line 144: 0 +Line 145: 0 +Line 146: 0 +Line 147: 0 +Line 148: 0 +Line 149: 0 +Line 150: 0 +Line 151: 0 +Line 152: 0 +Line 153: 0 +Line 154: 0 +Line 155: 0 +Line 156: 0 +Line 157: 0 +Line 158: 0 +Line 159: 0 +Line 160: 0 +Line 161: 0 +Line 162: 0 +Line 163: 0 +Line 164: 0 +Line 165: 1 +Line 166: 0 +Line 167: 0 +Line 168: 0 +Line 169: 0 +Line 170: 0 +Line 171: 0 +Line 172: 0 +Line 173: 0 +Line 174: 0 +Line 175: 0 +Line 176: 0 +Line 177: 0 +Line 178: 0 +Line 179: 0 +Line 180: 0 +Line 181: 0 +Line 182: 0 +Line 183: 0 +Line 184: 0 +Line 185: 0 +Line 186: 0 +Line 187: 0 +Line 188: 0 +Line 189: 0 +Line 190: 0 +Line 191: 0 +Line 192: 0 +Line 193: 0 +Line 194: 0 +Line 195: 0 +Line 196: 0 +Line 197: 0 +Line 198: 0 +Line 199: 0 +Line 200: 0 +Line 201: 0 +Line 202: 0 +Line 203: 0 +Line 204: 0 +Line 205: 0 +Line 206: 0 +Line 207: 0 +Line 208: 0 +Line 209: 0 +Line 210: 0 +Line 211: 0 +Line 212: 0 +Line 213: 0 +Line 214: 0 +Line 215: 0 +Line 216: 0 +Line 217: 0 +Line 218: 0 +Line 219: 0 +Line 220: 0 +Line 221: 0 +Line 222: 0 +Line 223: 0 +Send MCU_INSTR_FILE +Line 0: 0 +Line 1: 0 +Line 2: 0 +Line 3: 1 +Line 4: 0 +Line 5: 0 +Line 6: 0 +Line 7: 0 +Line 8: 0 +Line 9: 0 +Line 10: 0 +Line 11: 0 +Line 12: 0 +Line 13: 0 +Line 14: 0 +Line 15: 0 +Line 16: 0 +Line 17: 0 +Line 18: 0 +Line 19: 0 +Line 20: 0 +Line 21: 0 +Line 22: 0 +Line 23: 0 +Line 24: 0 +Line 25: 0 +Line 26: 0 +Line 27: 0 +Line 28: 0 +Line 29: 0 +Line 30: 0 +Line 31: 0 +Line 32: 0 +Line 33: 0 +Line 34: 0 +Line 35: 0 +Line 36: 0 +Line 37: 0 +Line 38: 0 +Line 39: 0 +Line 40: 0 +Line 41: 0 +Line 42: 0 +Line 43: 0 +Line 44: 0 +Line 45: 0 +Line 46: 0 +Line 47: 0 +Line 48: 0 +Line 49: 0 +Line 50: 0 +Line 51: 0 +Line 52: 0 +Line 53: 0 +Line 54: 0 +Line 55: 0 +Line 56: 0 +Line 57: 0 +Line 58: 0 +Line 59: 1 +Line 60: 0 +Line 61: 1 +Line 62: 0 +Line 63: 0 +Line 64: 0 +Line 65: 0 +Line 66: 0 +Line 67: 0 +Line 68: 0 +Line 69: 0 +Line 70: 0 +Line 71: 0 +Line 72: 0 +Line 73: 1 +Line 74: 0 +Line 75: 1 +Line 76: 0 +Line 77: 0 +Line 78: 0 +Line 79: 0 +Line 80: 0 +Line 81: 0 +Line 82: 0 +Line 83: 0 +Line 84: 0 +Line 85: 0 +Line 86: 0 +Line 87: 0 +Line 88: 0 +Line 89: 0 +Line 90: 0 +Line 91: 1 +Line 92: 1 +Line 93: 0 +Line 94: 0 +Line 95: 1 +Line 96: 0 +Line 97: 0 +Line 98: 0 +Line 99: 0 +Line 100: 0 +Line 101: 0 +Line 102: 0 +Line 103: 0 +Line 104: 1 +Line 105: 0 +Line 106: 1 +Line 107: 1 +Line 108: 0 +Line 109: 1 +Line 110: 0 +Line 111: 0 +Line 112: 0 +Line 113: 0 +Line 114: 0 +Line 115: 0 +Line 116: 0 +Line 117: 0 +Line 118: 0 +Line 119: 0 +Line 120: 0 +Line 121: 0 +Line 122: 1 +Line 123: 1 +Line 124: 0 +Line 125: 0 +Line 126: 1 +Line 127: 0 +Line 128: 0 +Line 129: 0 +Line 130: 0 +Line 131: 0 +Line 132: 0 +Line 133: 0 +Line 134: 0 +Line 135: 1 +Line 136: 0 +Line 137: 1 +Line 138: 1 +Line 139: 1 +Line 140: 1 +Line 141: 1 +Line 142: 0 +Line 143: 0 +Line 144: 0 +Line 145: 0 +Line 146: 0 +Line 147: 0 +Line 148: 0 +Line 149: 0 +Line 150: 0 +Line 151: 0 +Line 152: 0 +Line 153: 0 +Line 154: 1 +Line 155: 1 +Line 156: 0 +Line 157: 0 +Line 158: 1 +Line 159: 0 +Line 160: 0 +Line 161: 0 +Line 162: 0 +Line 163: 0 +Line 164: 0 +Line 165: 0 +Line 166: 1 +Line 167: 0 +Line 168: 0 +Line 169: 1 +Line 170: 0 +Line 171: 0 +Line 172: 0 +Line 173: 1 +Line 174: 0 +Line 175: 0 +Line 176: 0 +Line 177: 0 +Line 178: 0 +Line 179: 0 +Line 180: 0 +Line 181: 0 +Line 182: 0 +Line 183: 0 +Line 184: 0 +Line 185: 0 +Line 186: 0 +Line 187: 1 +Line 188: 1 +Line 189: 0 +Line 190: 0 +Line 191: 1 +Line 192: 0 +Line 193: 0 +Line 194: 0 +Line 195: 0 +Line 196: 0 +Line 197: 0 +Line 198: 1 +Line 199: 0 +Line 200: 1 +Line 201: 0 +Line 202: 1 +Line 203: 0 +Line 204: 1 +Line 205: 0 +Line 206: 0 +Line 207: 0 +Line 208: 0 +Line 209: 0 +Line 210: 0 +Line 211: 0 +Line 212: 0 +Line 213: 0 +Line 214: 0 +Line 215: 0 +Line 216: 1 +Line 217: 0 +Line 218: 1 +Line 219: 0 +Line 220: 1 +Line 221: 1 +Line 222: 1 +Line 223: 1 +Line 224: 0 +Line 225: 0 +Line 226: 0 +Line 227: 0 +Line 228: 0 +Line 229: 1 +Line 230: 0 +Line 231: 1 +Line 232: 0 +Line 233: 1 +Line 234: 1 +Line 235: 0 +Line 236: 0 +Line 237: 1 +Line 238: 0 +Line 239: 0 +Line 240: 0 +Line 241: 0 +Line 242: 0 +Line 243: 0 +Line 244: 0 +Line 245: 0 +Line 246: 0 +Line 247: 0 +Line 248: 0 +Line 249: 0 +Line 250: 0 +Line 251: 0 +Line 252: 0 +Line 253: 0 +Line 254: 0 +Line 255: 1 +Line 256: 0 +Line 257: 0 +Line 258: 0 +Line 259: 0 +Line 260: 0 +Line 261: 1 +Line 262: 0 +Line 263: 1 +Line 264: 0 +Line 265: 1 +Line 266: 1 +Line 267: 0 +Line 268: 1 +Line 269: 0 +Line 270: 0 +Line 271: 0 +Line 272: 0 +Line 273: 0 +Line 274: 0 +Line 275: 0 +Line 276: 0 +Line 277: 0 +Line 278: 0 +Line 279: 0 +Line 280: 0 +Line 281: 0 +Line 282: 0 +Line 283: 0 +Line 284: 0 +Line 285: 0 +Line 286: 0 +Line 287: 1 +Line 288: 0 +Line 289: 0 +Line 290: 0 +Line 291: 0 +Line 292: 0 +Line 293: 1 +Line 294: 0 +Line 295: 1 +Line 296: 0 +Line 297: 1 +Line 298: 1 +Line 299: 0 +Line 300: 1 +Line 301: 1 +Line 302: 0 +Line 303: 0 +Line 304: 0 +Line 305: 0 +Line 306: 0 +Line 307: 0 +Line 308: 0 +Line 309: 0 +Line 310: 0 +Line 311: 0 +Line 312: 0 +Line 313: 0 +Line 314: 1 +Line 315: 0 +Line 316: 1 +Line 317: 0 +Line 318: 0 +Line 319: 0 +Line 320: 0 +Line 321: 0 +Line 322: 0 +Line 323: 0 +Line 324: 0 +Line 325: 1 +Line 326: 1 +Line 327: 0 +Line 328: 0 +Line 329: 0 +Line 330: 0 +Line 331: 0 +Line 332: 1 +Line 333: 1 +Line 334: 0 +Line 335: 0 +Line 336: 0 +Line 337: 0 +Line 338: 0 +Line 339: 0 +Line 340: 0 +Line 341: 0 +Line 342: 0 +Line 343: 0 +Line 344: 0 +Line 345: 0 +Line 346: 0 +Line 347: 0 +Line 348: 1 +Line 349: 0 +Line 350: 1 +Line 351: 0 +Line 352: 0 +Line 353: 0 +Line 354: 0 +Line 355: 0 +Line 356: 0 +Line 357: 1 +Line 358: 1 +Line 359: 0 +Line 360: 0 +Line 361: 0 +Line 362: 1 +Line 363: 1 +Line 364: 0 +Line 365: 1 +Line 366: 0 +Line 367: 0 +Line 368: 0 +Line 369: 0 +Line 370: 0 +Line 371: 0 +Line 372: 0 +Line 373: 0 +Line 374: 0 +Line 375: 0 +Line 376: 0 +Line 377: 0 +Line 378: 0 +Line 379: 0 +Line 380: 1 +Line 381: 0 +Line 382: 0 +Line 383: 0 +Line 384: 0 +Line 385: 0 +Line 386: 0 +Line 387: 0 +Line 388: 0 +Line 389: 1 +Line 390: 1 +Line 391: 0 +Line 392: 0 +Line 393: 1 +Line 394: 0 +Line 395: 1 +Line 396: 0 +Line 397: 1 +Line 398: 0 +Line 399: 0 +Line 400: 0 +Line 401: 0 +Line 402: 0 +Line 403: 0 +Line 404: 0 +Line 405: 0 +Line 406: 0 +Line 407: 0 +Line 408: 0 +Line 409: 0 +Line 410: 0 +Line 411: 0 +Line 412: 1 +Line 413: 0 +Line 414: 0 +Line 415: 0 +Send ENVE_ID_FILE +Line 0: 0 +Line 1: 0 +Line 2: 0 +Line 3: 1 +Line 4: 0 +Line 5: 1 +Line 6: 0 +Line 7: 0 +Line 8: 0 +Line 9: 0 +Line 10: 0 +Line 11: 0 +Line 12: 0 +Line 13: 0 +Line 14: 0 +Line 15: 0 +Line 16: 0 +Line 17: 0 +Line 18: 0 +Line 19: 0 +Line 20: 0 +Line 21: 0 +Line 22: 0 +Line 23: 0 +Line 24: 0 +Line 25: 0 +Line 26: 0 +Line 27: 0 +Line 28: 0 +Line 29: 0 +Line 30: 0 +Line 31: 0 +Line 32: 0 +Line 33: 0 +Line 34: 0 +Line 35: 0 +Line 36: 0 +Line 37: 0 +Line 38: 0 +Line 39: 0 +Line 40: 0 +Line 41: 0 +Line 42: 0 +Line 43: 0 +Line 44: 0 +Line 45: 0 +Line 46: 0 +Line 47: 0 +Line 48: 0 +Line 49: 0 +Line 50: 0 +Line 51: 0 +Line 52: 0 +Line 53: 0 +Line 54: 0 +Line 55: 0 +Line 56: 0 +Line 57: 0 +Line 58: 0 +Line 59: 0 +Line 60: 0 +Line 61: 0 +Line 62: 0 +Line 63: 0 +Line 64: 0 +Line 65: 0 +Line 66: 0 +Line 67: 0 +Line 68: 0 +Line 69: 0 +Line 70: 0 +Line 71: 1 +Line 72: 1 +Line 73: 1 +Line 74: 1 +Line 75: 0 +Line 76: 0 +Line 77: 1 +Line 78: 1 +Line 79: 1 +Line 80: 0 +Line 81: 0 +Line 82: 0 +Line 83: 0 +Line 84: 0 +Line 85: 1 +Line 86: 0 +Line 87: 1 +Line 88: 0 +Line 89: 0 +Line 90: 0 +Line 91: 0 +Line 92: 1 +Line 93: 1 +Line 94: 1 +Line 95: 0 +Line 96: 0 +Line 97: 0 +Line 98: 0 +Line 99: 0 +Line 100: 0 +Line 101: 1 +Line 102: 1 +Line 103: 1 +Line 104: 0 +Line 105: 1 +Line 106: 1 +Line 107: 0 +Line 108: 1 +Line 109: 0 +Line 110: 0 +Line 111: 1 +Line 112: 0 +Line 113: 0 +Line 114: 0 +Line 115: 0 +Line 116: 1 +Line 117: 0 +Line 118: 0 +Line 119: 1 +Line 120: 1 +Line 121: 0 +Line 122: 0 +Line 123: 1 +Line 124: 0 +Line 125: 0 +Line 126: 0 +Line 127: 1 +Line 128: 0 +Line 129: 0 +Line 130: 0 +Line 131: 0 +Line 132: 1 +Line 133: 1 +Line 134: 1 +Line 135: 1 +Line 136: 1 +Line 137: 1 +Line 138: 1 +Line 139: 0 +Line 140: 1 +Line 141: 1 +Line 142: 0 +Line 143: 1 +Line 144: 0 +Line 145: 0 +Line 146: 0 +Line 147: 0 +Line 148: 1 +Line 149: 1 +Line 150: 0 +Line 151: 1 +Line 152: 0 +Line 153: 0 +Line 154: 0 +Line 155: 0 +Line 156: 1 +Line 157: 0 +Line 158: 1 +Line 159: 0 +Line 160: 0 +Line 161: 0 +Line 162: 0 +Line 163: 1 +Line 164: 1 +Line 165: 0 +Line 166: 1 +Line 167: 0 +Line 168: 1 +Line 169: 0 +Line 170: 0 +Line 171: 0 +Line 172: 0 +Line 173: 1 +Line 174: 1 +Line 175: 0 +Line 176: 0 +Line 177: 0 +Line 178: 0 +Line 179: 0 +Line 180: 1 +Line 181: 1 +Line 182: 1 +Line 183: 1 +Line 184: 0 +Line 185: 0 +Line 186: 0 +Line 187: 1 +Line 188: 1 +Line 189: 0 +Line 190: 1 +Line 191: 0 +Line 192: 0 +Line 193: 0 +Line 194: 1 +Line 195: 0 +Line 196: 0 +Line 197: 1 +Line 198: 1 +Line 199: 0 +Line 200: 0 +Line 201: 0 +Line 202: 0 +Line 203: 0 +Line 204: 1 +Line 205: 1 +Line 206: 1 +Line 207: 1 +Line 208: 0 +Line 209: 0 +Line 210: 0 +Line 211: 0 +Line 212: 1 +Line 213: 1 +Line 214: 1 +Line 215: 1 +Line 216: 1 +Line 217: 0 +Line 218: 0 +Line 219: 0 +Line 220: 0 +Line 221: 1 +Line 222: 1 +Line 223: 0 +Line 224: 0 +Line 225: 0 +Line 226: 1 +Line 227: 1 +Line 228: 0 +Line 229: 0 +Line 230: 0 +Line 231: 1 +Line 232: 0 +Line 233: 1 +Line 234: 0 +Line 235: 0 +Line 236: 0 +Line 237: 1 +Line 238: 1 +Line 239: 1 +Line 240: 0 +Line 241: 0 +Line 242: 0 +Line 243: 0 +Line 244: 1 +Line 245: 1 +Line 246: 1 +Line 247: 0 +Line 248: 0 +Line 249: 1 +Line 250: 0 +Line 251: 0 +Line 252: 0 +Line 253: 1 +Line 254: 0 +Line 255: 0 +Line 256: 0 +Line 257: 0 +Line 258: 1 +Line 259: 1 +Line 260: 1 +Line 261: 0 +Line 262: 1 +Line 263: 0 +Line 264: 1 +Line 265: 1 +Line 266: 1 +Line 267: 1 +Line 268: 0 +Line 269: 1 +Line 270: 1 +Line 271: 1 +Line 272: 0 +Line 273: 0 +Line 274: 0 +Line 275: 0 +Line 276: 1 +Line 277: 0 +Line 278: 1 +Line 279: 1 +Line 280: 0 +Line 281: 1 +Line 282: 1 +Line 283: 1 +Line 284: 0 +Line 285: 1 +Line 286: 1 +Line 287: 0 +Line 288: 0 +Line 289: 1 +Line 290: 0 +Line 291: 0 +Line 292: 0 +Line 293: 0 +Line 294: 1 +Line 295: 0 +Line 296: 0 +Line 297: 0 +Line 298: 0 +Line 299: 1 +Line 300: 0 +Line 301: 0 +Line 302: 1 +Line 303: 1 +Line 304: 0 +Line 305: 0 +Line 306: 0 +Line 307: 0 +Line 308: 0 +Line 309: 1 +Line 310: 1 +Line 311: 1 +Line 312: 0 +Line 313: 1 +Line 314: 1 +Line 315: 0 +Line 316: 1 +Line 317: 0 +Line 318: 1 +Line 319: 0 +Line 320: 0 +Line 321: 1 +Line 322: 0 +Line 323: 0 +Line 324: 0 +Line 325: 1 +Line 326: 0 +Line 327: 1 +Line 328: 1 +Line 329: 1 +Line 330: 0 +Line 331: 1 +Line 332: 0 +Line 333: 1 +Line 334: 0 +Line 335: 1 +Line 336: 0 +Line 337: 0 +Line 338: 0 +Line 339: 0 +Line 340: 0 +Line 341: 0 +Line 342: 1 +Line 343: 0 +Line 344: 1 +Line 345: 0 +Line 346: 0 +Line 347: 1 +Line 348: 0 +Line 349: 0 +Line 350: 0 +Line 351: 0 +Line 352: 0 +Line 353: 1 +Line 354: 0 +Line 355: 0 +Line 356: 0 +Line 357: 1 +Line 358: 0 +Line 359: 1 +Line 360: 1 +Line 361: 1 +Line 362: 0 +Line 363: 1 +Line 364: 0 +Line 365: 1 +Line 366: 0 +Line 367: 1 +Line 368: 1 +Line 369: 1 +Line 370: 1 +Line 371: 1 +Line 372: 1 +Line 373: 1 +Line 374: 0 +Line 375: 1 +Line 376: 0 +Line 377: 1 +Line 378: 1 +Line 379: 1 +Line 380: 0 +Line 381: 0 +Line 382: 0 +Line 383: 0 +Line 384: 0 +Line 385: 1 +Line 386: 0 +Line 387: 0 +Line 388: 0 +Line 389: 0 +Line 390: 1 +Line 391: 0 +Line 392: 0 +Line 393: 0 +Line 394: 0 +Line 395: 1 +Line 396: 0 +Line 397: 0 +Line 398: 1 +Line 399: 1 +Line 400: 1 +Line 401: 1 +Line 402: 1 +Line 403: 1 +Line 404: 1 +Line 405: 0 +Line 406: 0 +Line 407: 0 +Line 408: 1 +Line 409: 0 +Line 410: 0 +Line 411: 1 +Line 412: 0 +Line 413: 1 +Line 414: 1 +Line 415: 0 +Line 416: 0 +Line 417: 0 +Line 418: 1 +Line 419: 1 +Line 420: 1 +Line 421: 0 +Line 422: 1 +Line 423: 0 +Line 424: 1 +Line 425: 1 +Line 426: 1 +Line 427: 1 +Line 428: 0 +Line 429: 1 +Line 430: 1 +Line 431: 1 +Line 432: 1 +Line 433: 1 +Line 434: 1 +Line 435: 1 +Line 436: 0 +Line 437: 1 +Line 438: 0 +Line 439: 0 +Line 440: 1 +Line 441: 0 +Line 442: 0 +Line 443: 0 +Line 444: 1 +Line 445: 0 +Line 446: 1 +Line 447: 0 +Line 448: 0 +Line 449: 0 +Line 450: 1 +Line 451: 1 +Line 452: 0 +Line 453: 0 +Line 454: 0 +Line 455: 1 +Line 456: 0 +Line 457: 1 +Line 458: 0 +Line 459: 0 +Line 460: 0 +Line 461: 1 +Line 462: 1 +Line 463: 1 +Line 464: 1 +Line 465: 1 +Line 466: 1 +Line 467: 1 +Line 468: 0 +Line 469: 0 +Line 470: 0 +Line 471: 1 +Line 472: 1 +Line 473: 0 +Line 474: 1 +Line 475: 1 +Line 476: 1 +Line 477: 1 +Line 478: 0 +Line 479: 0 +Line 480: 0 +Line 481: 0 +Line 482: 1 +Line 483: 0 +Line 484: 0 +Line 485: 1 +Line 486: 1 +Line 487: 0 +Line 488: 0 +Line 489: 0 +Line 490: 0 +Line 491: 0 +Line 492: 1 +Line 493: 1 +Line 494: 1 +Line 495: 1 +Line 496: 1 +Line 497: 1 +Line 498: 1 +Line 499: 1 +Line 500: 0 +Line 501: 0 +Line 502: 0 +Line 503: 0 +Line 504: 0 +Line 505: 1 +Line 506: 1 +Line 507: 1 +Line 508: 1 +Line 509: 0 +Line 510: 1 +Line 511: 0 +Line 512: 0 +Line 513: 0 +Line 514: 0 +Line 515: 1 +Line 516: 1 +Line 517: 0 +Line 518: 1 +Line 519: 0 +Line 520: 1 +Line 521: 0 +Line 522: 0 +Line 523: 0 +Line 524: 0 +Line 525: 1 +Line 526: 1 +Line 527: 0 +Line 528: 1 +Line 529: 1 +Line 530: 1 +Line 531: 1 +Line 532: 0 +Line 533: 0 +Line 534: 0 +Line 535: 0 +Line 536: 1 +Line 537: 1 +Line 538: 1 +Line 539: 0 +Line 540: 0 +Line 541: 1 +Line 542: 1 +Line 543: 0 +Line 544: 0 +Line 545: 0 +Line 546: 0 +Line 547: 0 +Line 548: 1 +Line 549: 1 +Line 550: 1 +Line 551: 1 +Line 552: 1 +Line 553: 1 +Line 554: 1 +Line 555: 0 +Line 556: 1 +Line 557: 1 +Line 558: 0 +Line 559: 1 +Line 560: 1 +Line 561: 1 +Line 562: 1 +Line 563: 1 +Line 564: 0 +Line 565: 0 +Line 566: 1 +Line 567: 0 +Line 568: 1 +Line 569: 1 +Line 570: 1 +Line 571: 1 +Line 572: 0 +Line 573: 1 +Line 574: 1 +Line 575: 0 +Line 576: 0 +Line 577: 0 +Line 578: 0 +Line 579: 0 +Line 580: 0 +Line 581: 1 +Line 582: 1 +Line 583: 1 +Line 584: 0 +Line 585: 1 +Line 586: 1 +Line 587: 0 +Line 588: 1 +Line 589: 0 +Line 590: 0 +Line 591: 1 +Line 592: 1 +Line 593: 1 +Line 594: 1 +Line 595: 1 +Line 596: 0 +Line 597: 1 +Line 598: 1 +Line 599: 0 +Line 600: 0 +Line 601: 1 +Line 602: 1 +Line 603: 0 +Line 604: 1 +Line 605: 1 +Line 606: 1 +Line 607: 1 +Line 608: 0 +Line 609: 0 +Line 610: 0 +Line 611: 0 +Line 612: 0 +Line 613: 0 +Line 614: 0 +Line 615: 1 +Line 616: 1 +Line 617: 1 +Line 618: 1 +Line 619: 0 +Line 620: 0 +Line 621: 1 +Line 622: 1 +Line 623: 1 +Line 624: 1 +Line 625: 1 +Line 626: 1 +Line 627: 1 +Line 628: 1 +Line 629: 0 +Line 630: 1 +Line 631: 0 +Line 632: 1 +Line 633: 1 +Line 634: 1 +Line 635: 1 +Line 636: 0 +Line 637: 0 +Line 638: 1 +Line 639: 0 +Line 640: 0 +Line 641: 0 +Line 642: 0 +Line 643: 0 +Line 644: 0 +Line 645: 0 +Line 646: 0 +Line 647: 0 +Line 648: 0 +Line 649: 0 +Line 650: 0 +Line 651: 0 +Line 652: 0 +Line 653: 0 +Line 654: 0 +Line 655: 0 +Line 656: 0 +Line 657: 0 +Line 658: 0 +Line 659: 0 +Line 660: 0 +Line 661: 0 +Line 662: 0 +Line 663: 0 +Line 664: 0 +Line 665: 0 +Line 666: 0 +Line 667: 0 +Line 668: 0 +Line 669: 0 +Line 670: 0 +Line 671: 0 +Line 672: 0 +Line 673: 1 +Line 674: 0 +Line 675: 0 +Line 676: 0 +Line 677: 1 +Line 678: 1 +Line 679: 0 +Line 680: 0 +Line 681: 1 +Line 682: 0 +Line 683: 1 +Line 684: 0 +Line 685: 0 +Line 686: 0 +Line 687: 0 +Line 688: 0 +Line 689: 0 +Line 690: 0 +Line 691: 0 +Line 692: 0 +Line 693: 0 +Line 694: 0 +Line 695: 0 +Line 696: 0 +Line 697: 0 +Line 698: 0 +Line 699: 0 +Line 700: 0 +Line 701: 0 +Line 702: 0 +Line 703: 0 +Line 704: 0 +Line 705: 1 +Line 706: 0 +Line 707: 0 +Line 708: 0 +Line 709: 1 +Line 710: 1 +Line 711: 0 +Line 712: 0 +Line 713: 1 +Line 714: 0 +Line 715: 1 +Line 716: 0 +Line 717: 0 +Line 718: 0 +Line 719: 0 +Line 720: 0 +Line 721: 0 +Line 722: 0 +Line 723: 0 +Line 724: 0 +Line 725: 0 +Line 726: 0 +Line 727: 0 +Line 728: 0 +Line 729: 0 +Line 730: 0 +Line 731: 0 +Line 732: 0 +Line 733: 0 +Line 734: 0 +Line 735: 0 +Line 736: 0 +Line 737: 1 +Line 738: 0 +Line 739: 0 +Line 740: 0 +Line 741: 1 +Line 742: 1 +Line 743: 0 +Line 744: 0 +Line 745: 1 +Line 746: 0 +Line 747: 1 +Line 748: 0 +Line 749: 0 +Line 750: 0 +Line 751: 0 +Line 752: 0 +Line 753: 0 +Line 754: 0 +Line 755: 0 +Line 756: 0 +Line 757: 0 +Line 758: 0 +Line 759: 0 +Line 760: 0 +Line 761: 0 +Line 762: 0 +Line 763: 0 +Line 764: 0 +Line 765: 0 +Line 766: 0 +Line 767: 0 +Line 768: 0 +Line 769: 1 +Line 770: 0 +Line 771: 0 +Line 772: 0 +Line 773: 1 +Line 774: 1 +Line 775: 0 +Line 776: 0 +Line 777: 1 +Line 778: 0 +Line 779: 1 +Line 780: 0 +Line 781: 0 +Line 782: 0 +Line 783: 0 +Line 784: 0 +Line 785: 0 +Line 786: 0 +Line 787: 0 +Line 788: 0 +Line 789: 0 +Line 790: 0 +Line 791: 0 +Line 792: 0 +Line 793: 0 +Line 794: 0 +Line 795: 0 +Line 796: 0 +Line 797: 0 +Line 798: 0 +Line 799: 0 +Line 800: 0 +Line 801: 1 +Line 802: 0 +Line 803: 0 +Line 804: 0 +Line 805: 1 +Line 806: 1 +Line 807: 0 +Line 808: 0 +Line 809: 1 +Line 810: 0 +Line 811: 1 +Line 812: 0 +Line 813: 0 +Line 814: 0 +Line 815: 0 +Line 816: 0 +Line 817: 0 +Line 818: 0 +Line 819: 0 +Line 820: 0 +Line 821: 0 +Line 822: 0 +Line 823: 0 +Line 824: 0 +Line 825: 0 +Line 826: 0 +Line 827: 0 +Line 828: 0 +Line 829: 0 +Line 830: 0 +Line 831: 0 +Line 832: 0 +Line 833: 1 +Line 834: 0 +Line 835: 0 +Line 836: 0 +Line 837: 1 +Line 838: 1 +Line 839: 0 +Line 840: 0 +Line 841: 1 +Line 842: 0 +Line 843: 1 +Line 844: 0 +Line 845: 0 +Line 846: 0 +Line 847: 0 +Line 848: 0 +Line 849: 0 +Line 850: 0 +Line 851: 0 +Line 852: 0 +Line 853: 0 +Line 854: 0 +Line 855: 0 +Line 856: 0 +Line 857: 0 +Line 858: 0 +Line 859: 0 +Line 860: 0 +Line 861: 0 +Line 862: 0 +Line 863: 0 +Line 864: 0 +Line 865: 1 +Line 866: 0 +Line 867: 0 +Line 868: 0 +Line 869: 1 +Line 870: 1 +Line 871: 0 +Line 872: 0 +Line 873: 1 +Line 874: 0 +Line 875: 1 +Line 876: 0 +Line 877: 0 +Line 878: 0 +Line 879: 0 +Line 880: 0 +Line 881: 0 +Line 882: 0 +Line 883: 0 +Line 884: 0 +Line 885: 0 +Line 886: 0 +Line 887: 0 +Line 888: 0 +Line 889: 0 +Line 890: 0 +Line 891: 0 +Line 892: 0 +Line 893: 0 +Line 894: 0 +Line 895: 0 +Line 896: 0 +Line 897: 1 +Line 898: 0 +Line 899: 0 +Line 900: 0 +Line 901: 1 +Line 902: 1 +Line 903: 0 +Line 904: 0 +Line 905: 1 +Line 906: 0 +Line 907: 1 +Line 908: 0 +Line 909: 0 +Line 910: 0 +Line 911: 0 +Line 912: 0 +Line 913: 0 +Line 914: 0 +Line 915: 0 +Line 916: 0 +Line 917: 0 +Line 918: 0 +Line 919: 0 +Line 920: 0 +Line 921: 0 +Line 922: 0 +Line 923: 0 +Line 924: 0 +Line 925: 0 +Line 926: 0 +Line 927: 0 +Line 928: 0 +Line 929: 1 +Line 930: 0 +Line 931: 0 +Line 932: 0 +Line 933: 1 +Line 934: 1 +Line 935: 0 +Line 936: 0 +Line 937: 1 +Line 938: 0 +Line 939: 1 +Line 940: 0 +Line 941: 0 +Line 942: 0 +Line 943: 0 +Line 944: 0 +Line 945: 0 +Line 946: 0 +Line 947: 0 +Line 948: 0 +Line 949: 0 +Line 950: 0 +Line 951: 0 +Line 952: 0 +Line 953: 0 +Line 954: 0 +Line 955: 0 +Line 956: 0 +Line 957: 0 +Line 958: 0 +Line 959: 0 +Line 960: 0 +Line 961: 1 +Line 962: 0 +Line 963: 0 +Line 964: 0 +Line 965: 1 +Line 966: 1 +Line 967: 0 +Line 968: 0 +Line 969: 1 +Line 970: 0 +Line 971: 1 +Line 972: 0 +Line 973: 0 +Line 974: 0 +Line 975: 0 +Line 976: 0 +Line 977: 0 +Line 978: 0 +Line 979: 0 +Line 980: 0 +Line 981: 0 +Line 982: 0 +Line 983: 0 +Line 984: 0 +Line 985: 0 +Line 986: 0 +Line 987: 0 +Line 988: 0 +Line 989: 0 +Line 990: 0 +Line 991: 0 +Line 992: 0 +Line 993: 1 +Line 994: 0 +Line 995: 0 +Line 996: 0 +Line 997: 1 +Line 998: 1 +Line 999: 0 +Line 1000: 0 +Line 1001: 1 +Line 1002: 0 +Line 1003: 1 +Line 1004: 0 +Line 1005: 0 +Line 1006: 0 +Line 1007: 0 +Line 1008: 0 +Line 1009: 0 +Line 1010: 0 +Line 1011: 0 +Line 1012: 0 +Line 1013: 0 +Line 1014: 0 +Line 1015: 0 +Line 1016: 0 +Line 1017: 0 +Line 1018: 0 +Line 1019: 0 +Line 1020: 0 +Line 1021: 0 +Line 1022: 0 +Line 1023: 0 +Line 1024: 0 +Line 1025: 1 +Line 1026: 0 +Line 1027: 0 +Line 1028: 0 +Line 1029: 1 +Line 1030: 1 +Line 1031: 0 +Line 1032: 0 +Line 1033: 1 +Line 1034: 0 +Line 1035: 1 +Line 1036: 0 +Line 1037: 0 +Line 1038: 0 +Line 1039: 0 +Line 1040: 0 +Line 1041: 0 +Line 1042: 0 +Line 1043: 0 +Line 1044: 0 +Line 1045: 0 +Line 1046: 0 +Line 1047: 0 +Line 1048: 0 +Line 1049: 0 +Line 1050: 0 +Line 1051: 0 +Line 1052: 0 +Line 1053: 0 +Line 1054: 0 +Line 1055: 0 +Line 1056: 0 +Line 1057: 1 +Line 1058: 0 +Line 1059: 0 +Line 1060: 0 +Line 1061: 1 +Line 1062: 1 +Line 1063: 0 +Line 1064: 0 +Line 1065: 1 +Line 1066: 0 +Line 1067: 1 +Line 1068: 0 +Line 1069: 0 +Line 1070: 0 +Line 1071: 0 +Line 1072: 0 +Line 1073: 0 +Line 1074: 0 +Line 1075: 0 +Line 1076: 0 +Line 1077: 0 +Line 1078: 0 +Line 1079: 0 +Line 1080: 0 +Line 1081: 0 +Line 1082: 0 +Line 1083: 0 +Line 1084: 0 +Line 1085: 0 +Line 1086: 0 +Line 1087: 0 +Line 1088: 0 +Line 1089: 1 +Line 1090: 0 +Line 1091: 0 +Line 1092: 0 +Line 1093: 1 +Line 1094: 1 +Line 1095: 0 +Line 1096: 0 +Line 1097: 1 +Line 1098: 0 +Line 1099: 1 +Line 1100: 0 +Line 1101: 0 +Line 1102: 0 +Line 1103: 0 +Line 1104: 0 +Line 1105: 0 +Line 1106: 0 +Line 1107: 0 +Line 1108: 0 +Line 1109: 0 +Line 1110: 0 +Line 1111: 0 +Line 1112: 0 +Line 1113: 0 +Line 1114: 0 +Line 1115: 0 +Line 1116: 0 +Line 1117: 0 +Line 1118: 0 +Line 1119: 0 +Line 1120: 0 +Line 1121: 1 +Line 1122: 0 +Line 1123: 0 +Line 1124: 0 +Line 1125: 1 +Line 1126: 1 +Line 1127: 0 +Line 1128: 0 +Line 1129: 1 +Line 1130: 0 +Line 1131: 1 +Line 1132: 0 +Line 1133: 0 +Line 1134: 0 +Line 1135: 0 +Line 1136: 0 +Line 1137: 0 +Line 1138: 0 +Line 1139: 0 +Line 1140: 0 +Line 1141: 0 +Line 1142: 0 +Line 1143: 0 +Line 1144: 0 +Line 1145: 0 +Line 1146: 0 +Line 1147: 0 +Line 1148: 0 +Line 1149: 0 +Line 1150: 0 +Line 1151: 0 +Line 1152: 0 +Line 1153: 1 +Line 1154: 0 +Line 1155: 0 +Line 1156: 0 +Line 1157: 1 +Line 1158: 1 +Line 1159: 0 +Line 1160: 0 +Line 1161: 1 +Line 1162: 0 +Line 1163: 1 +Line 1164: 0 +Line 1165: 0 +Line 1166: 0 +Line 1167: 0 +Line 1168: 0 +Line 1169: 0 +Line 1170: 0 +Line 1171: 0 +Line 1172: 0 +Line 1173: 0 +Line 1174: 0 +Line 1175: 0 +Line 1176: 0 +Line 1177: 0 +Line 1178: 0 +Line 1179: 0 +Line 1180: 0 +Line 1181: 0 +Line 1182: 0 +Line 1183: 0 +Line 1184: 0 +Line 1185: 1 +Line 1186: 0 +Line 1187: 0 +Line 1188: 0 +Line 1189: 1 +Line 1190: 1 +Line 1191: 0 +Line 1192: 0 +Line 1193: 1 +Line 1194: 0 +Line 1195: 1 +Line 1196: 0 +Line 1197: 0 +Line 1198: 0 +Line 1199: 0 +Line 1200: 0 +Line 1201: 0 +Line 1202: 0 +Line 1203: 0 +Line 1204: 0 +Line 1205: 0 +Line 1206: 0 +Line 1207: 0 +Line 1208: 0 +Line 1209: 0 +Line 1210: 0 +Line 1211: 0 +Line 1212: 0 +Line 1213: 0 +Line 1214: 0 +Line 1215: 0 +Line 1216: 0 +Line 1217: 1 +Line 1218: 0 +Line 1219: 0 +Line 1220: 0 +Line 1221: 1 +Line 1222: 1 +Line 1223: 0 +Line 1224: 0 +Line 1225: 1 +Line 1226: 0 +Line 1227: 1 +Line 1228: 0 +Line 1229: 0 +Line 1230: 0 +Line 1231: 0 +Line 1232: 0 +Line 1233: 0 +Line 1234: 0 +Line 1235: 0 +Line 1236: 0 +Line 1237: 0 +Line 1238: 0 +Line 1239: 0 +Line 1240: 0 +Line 1241: 0 +Line 1242: 0 +Line 1243: 0 +Line 1244: 0 +Line 1245: 0 +Line 1246: 0 +Line 1247: 0 +Line 1248: 0 +Line 1249: 1 +Line 1250: 0 +Line 1251: 0 +Line 1252: 0 +Line 1253: 1 +Line 1254: 1 +Line 1255: 0 +Line 1256: 0 +Line 1257: 1 +Line 1258: 0 +Line 1259: 1 +Line 1260: 0 +Line 1261: 0 +Line 1262: 0 +Line 1263: 0 +Line 1264: 0 +Line 1265: 0 +Line 1266: 0 +Line 1267: 0 +Line 1268: 0 +Line 1269: 0 +Line 1270: 0 +Line 1271: 0 +Line 1272: 0 +Line 1273: 0 +Line 1274: 0 +Line 1275: 0 +Line 1276: 0 +Line 1277: 0 +Line 1278: 0 +Line 1279: 0 +Line 1280: 0 +Line 1281: 1 +Line 1282: 0 +Line 1283: 0 +Line 1284: 0 +Line 1285: 1 +Line 1286: 1 +Line 1287: 0 +Line 1288: 0 +Line 1289: 1 +Line 1290: 0 +Line 1291: 1 +Line 1292: 0 +Line 1293: 0 +Line 1294: 0 +Line 1295: 0 +Line 1296: 0 +Line 1297: 0 +Line 1298: 0 +Line 1299: 0 +Line 1300: 0 +Line 1301: 0 +Line 1302: 0 +Line 1303: 0 +Line 1304: 0 +Line 1305: 0 +Line 1306: 0 +Line 1307: 0 +Line 1308: 0 +Line 1309: 0 +Line 1310: 0 +Line 1311: 0 +Line 1312: 0 +Line 1313: 1 +Line 1314: 0 +Line 1315: 0 +Line 1316: 0 +Line 1317: 1 +Line 1318: 1 +Line 1319: 0 +Line 1320: 0 +Line 1321: 1 +Line 1322: 0 +Line 1323: 1 +Line 1324: 0 +Line 1325: 0 +Line 1326: 0 +Line 1327: 0 +Line 1328: 0 +Line 1329: 0 +Line 1330: 0 +Line 1331: 0 +Line 1332: 0 +Line 1333: 0 +Line 1334: 0 +Line 1335: 0 +Line 1336: 0 +Line 1337: 0 +Line 1338: 0 +Line 1339: 0 +Line 1340: 0 +Line 1341: 0 +Line 1342: 0 +Line 1343: 0 +Line 1344: 0 +Line 1345: 1 +Line 1346: 0 +Line 1347: 0 +Line 1348: 0 +Line 1349: 1 +Line 1350: 1 +Line 1351: 0 +Line 1352: 0 +Line 1353: 1 +Line 1354: 0 +Line 1355: 1 +Line 1356: 0 +Line 1357: 0 +Line 1358: 0 +Line 1359: 0 +Line 1360: 0 +Line 1361: 0 +Line 1362: 0 +Line 1363: 0 +Line 1364: 0 +Line 1365: 0 +Line 1366: 0 +Line 1367: 0 +Line 1368: 0 +Line 1369: 0 +Line 1370: 0 +Line 1371: 0 +Line 1372: 0 +Line 1373: 0 +Line 1374: 0 +Line 1375: 0 +Line 1376: 0 +Line 1377: 1 +Line 1378: 0 +Line 1379: 0 +Line 1380: 0 +Line 1381: 1 +Line 1382: 1 +Line 1383: 0 +Line 1384: 0 +Line 1385: 1 +Line 1386: 0 +Line 1387: 1 +Line 1388: 0 +Line 1389: 0 +Line 1390: 0 +Line 1391: 0 +Line 1392: 0 +Line 1393: 0 +Line 1394: 0 +Line 1395: 0 +Line 1396: 0 +Line 1397: 0 +Line 1398: 0 +Line 1399: 0 +Line 1400: 0 +Line 1401: 0 +Line 1402: 0 +Line 1403: 0 +Line 1404: 0 +Line 1405: 0 +Line 1406: 0 +Line 1407: 0 +Line 1408: 0 +Line 1409: 1 +Line 1410: 0 +Line 1411: 0 +Line 1412: 0 +Line 1413: 1 +Line 1414: 1 +Line 1415: 0 +Line 1416: 0 +Line 1417: 1 +Line 1418: 0 +Line 1419: 1 +Line 1420: 0 +Line 1421: 0 +Line 1422: 0 +Line 1423: 0 +Line 1424: 0 +Line 1425: 0 +Line 1426: 0 +Line 1427: 0 +Line 1428: 0 +Line 1429: 0 +Line 1430: 0 +Line 1431: 0 +Line 1432: 0 +Line 1433: 0 +Line 1434: 0 +Line 1435: 0 +Line 1436: 0 +Line 1437: 0 +Line 1438: 0 +Line 1439: 0 +Line 1440: 0 +Line 1441: 1 +Line 1442: 0 +Line 1443: 0 +Line 1444: 0 +Line 1445: 1 +Line 1446: 1 +Line 1447: 0 +Line 1448: 0 +Line 1449: 1 +Line 1450: 0 +Line 1451: 1 +Line 1452: 0 +Line 1453: 0 +Line 1454: 0 +Line 1455: 0 +Line 1456: 0 +Line 1457: 0 +Line 1458: 0 +Line 1459: 0 +Line 1460: 0 +Line 1461: 0 +Line 1462: 0 +Line 1463: 0 +Line 1464: 0 +Line 1465: 0 +Line 1466: 0 +Line 1467: 0 +Line 1468: 0 +Line 1469: 0 +Line 1470: 0 +Line 1471: 0 +Line 1472: 0 +Line 1473: 0 +Line 1474: 0 +Line 1475: 1 +Line 1476: 0 +Line 1477: 1 +Line 1478: 0 +Line 1479: 0 +Line 1480: 0 +Line 1481: 0 +Line 1482: 1 +Line 1483: 0 +Line 1484: 1 +Line 1485: 0 +Line 1486: 1 +Line 1487: 1 +Line 1488: 0 +Line 1489: 0 +Line 1490: 0 +Line 1491: 0 +Line 1492: 0 +Line 1493: 0 +Line 1494: 0 +Line 1495: 0 +Line 1496: 0 +Line 1497: 0 +Line 1498: 0 +Line 1499: 0 +Line 1500: 0 +Line 1501: 0 +Line 1502: 0 +Line 1503: 0 +Line 1504: 0 +Line 1505: 0 +Line 1506: 0 +Line 1507: 1 +Line 1508: 0 +Line 1509: 1 +Line 1510: 0 +Line 1511: 1 +Line 1512: 0 +Line 1513: 0 +Line 1514: 1 +Line 1515: 0 +Line 1516: 1 +Line 1517: 1 +Line 1518: 1 +Line 1519: 0 +Line 1520: 0 +Line 1521: 0 +Line 1522: 0 +Line 1523: 0 +Line 1524: 0 +Line 1525: 0 +Line 1526: 0 +Line 1527: 0 +Line 1528: 0 +Line 1529: 0 +Line 1530: 0 +Line 1531: 0 +Line 1532: 0 +Line 1533: 0 +Line 1534: 0 +Line 1535: 0 +Line 1536: 0 +Line 1537: 0 +Line 1538: 0 +Line 1539: 1 +Line 1540: 0 +Line 1541: 1 +Line 1542: 1 +Line 1543: 0 +Line 1544: 0 +Line 1545: 0 +Line 1546: 1 +Line 1547: 1 +Line 1548: 0 +Line 1549: 1 +Line 1550: 1 +Line 1551: 0 +Line 1552: 0 +Line 1553: 0 +Line 1554: 0 +Line 1555: 0 +Line 1556: 0 +Line 1557: 0 +Line 1558: 0 +Line 1559: 0 +Line 1560: 0 +Line 1561: 0 +Line 1562: 0 +Line 1563: 0 +Line 1564: 0 +Line 1565: 0 +Line 1566: 0 +Line 1567: 0 +Line 1568: 0 +Line 1569: 0 +Line 1570: 0 +Line 1571: 1 +Line 1572: 0 +Line 1573: 1 +Line 1574: 1 +Line 1575: 1 +Line 1576: 0 +Line 1577: 1 +Line 1578: 0 +Line 1579: 0 +Line 1580: 0 +Line 1581: 0 +Line 1582: 1 +Line 1583: 1 +Line 1584: 0 +Line 1585: 0 +Line 1586: 0 +Line 1587: 0 +Line 1588: 0 +Line 1589: 0 +Line 1590: 0 +Line 1591: 0 +Line 1592: 0 +Line 1593: 0 +Line 1594: 0 +Line 1595: 0 +Line 1596: 0 +Line 1597: 0 +Line 1598: 0 +Line 1599: 0 +Line 1600: 0 +Line 1601: 0 +Line 1602: 0 +Line 1603: 1 +Line 1604: 1 +Line 1605: 0 +Line 1606: 0 +Line 1607: 0 +Line 1608: 0 +Line 1609: 1 +Line 1610: 0 +Line 1611: 1 +Line 1612: 0 +Line 1613: 1 +Line 1614: 1 +Line 1615: 0 +Line 1616: 0 +Line 1617: 0 +Line 1618: 0 +Line 1619: 0 +Line 1620: 0 +Line 1621: 0 +Line 1622: 0 +Line 1623: 0 +Line 1624: 0 +Line 1625: 0 +Line 1626: 0 +Line 1627: 0 +Line 1628: 0 +Line 1629: 0 +Line 1630: 0 +Line 1631: 0 +Line 1632: 0 +Line 1633: 0 +Line 1634: 0 +Line 1635: 1 +Line 1636: 1 +Line 1637: 0 +Line 1638: 0 +Line 1639: 1 +Line 1640: 0 +Line 1641: 1 +Line 1642: 1 +Line 1643: 0 +Line 1644: 1 +Line 1645: 1 +Line 1646: 0 +Line 1647: 0 +Line 1648: 0 +Line 1649: 0 +Line 1650: 0 +Line 1651: 0 +Line 1652: 0 +Line 1653: 0 +Line 1654: 0 +Line 1655: 0 +Line 1656: 0 +Line 1657: 0 +Line 1658: 0 +Line 1659: 0 +Line 1660: 0 +Line 1661: 0 +Line 1662: 0 +Line 1663: 0 +Line 1664: 0 +Line 1665: 0 +Line 1666: 0 +Line 1667: 1 +Line 1668: 1 +Line 1669: 0 +Line 1670: 1 +Line 1671: 0 +Line 1672: 1 +Line 1673: 0 +Line 1674: 0 +Line 1675: 0 +Line 1676: 0 +Line 1677: 1 +Line 1678: 1 +Line 1679: 1 +Line 1680: 0 +Line 1681: 0 +Line 1682: 0 +Line 1683: 0 +Line 1684: 0 +Line 1685: 0 +Line 1686: 0 +Line 1687: 0 +Line 1688: 0 +Line 1689: 0 +Line 1690: 0 +Line 1691: 0 +Line 1692: 0 +Line 1693: 0 +Line 1694: 0 +Line 1695: 0 +Line 1696: 0 +Line 1697: 0 +Line 1698: 0 +Line 1699: 1 +Line 1700: 1 +Line 1701: 0 +Line 1702: 1 +Line 1703: 1 +Line 1704: 1 +Line 1705: 0 +Line 1706: 1 +Line 1707: 0 +Line 1708: 0 +Line 1709: 1 +Line 1710: 1 +Line 1711: 0 +Line 1712: 0 +Line 1713: 0 +Line 1714: 0 +Line 1715: 0 +Line 1716: 0 +Line 1717: 0 +Line 1718: 0 +Line 1719: 0 +Line 1720: 0 +Line 1721: 0 +Line 1722: 0 +Line 1723: 0 +Line 1724: 0 +Line 1725: 0 +Line 1726: 0 +Line 1727: 0 +Line 1728: 0 +Line 1729: 0 +Line 1730: 0 +Line 1731: 1 +Line 1732: 1 +Line 1733: 1 +Line 1734: 0 +Line 1735: 0 +Line 1736: 1 +Line 1737: 1 +Line 1738: 0 +Line 1739: 0 +Line 1740: 1 +Line 1741: 0 +Line 1742: 0 +Line 1743: 0 +Line 1744: 0 +Line 1745: 0 +Line 1746: 0 +Line 1747: 0 +Line 1748: 0 +Line 1749: 0 +Line 1750: 0 +Line 1751: 0 +Line 1752: 0 +Line 1753: 0 +Line 1754: 0 +Line 1755: 0 +Line 1756: 0 +Line 1757: 0 +Line 1758: 0 +Line 1759: 0 +Line 1760: 0 +Line 1761: 0 +Line 1762: 0 +Line 1763: 1 +Line 1764: 1 +Line 1765: 1 +Line 1766: 0 +Line 1767: 1 +Line 1768: 1 +Line 1769: 1 +Line 1770: 1 +Line 1771: 0 +Line 1772: 1 +Line 1773: 1 +Line 1774: 0 +Line 1775: 1 +Line 1776: 0 +Line 1777: 0 +Line 1778: 0 +Line 1779: 0 +Line 1780: 0 +Line 1781: 0 +Line 1782: 0 +Line 1783: 0 +Line 1784: 0 +Line 1785: 0 +Line 1786: 0 +Line 1787: 0 +Line 1788: 0 +Line 1789: 0 +Line 1790: 0 +Line 1791: 0 +Line 1792: 0 +Line 1793: 0 +Line 1794: 0 +Line 1795: 1 +Line 1796: 1 +Line 1797: 1 +Line 1798: 1 +Line 1799: 1 +Line 1800: 0 +Line 1801: 0 +Line 1802: 0 +Line 1803: 1 +Line 1804: 0 +Line 1805: 1 +Line 1806: 0 +Line 1807: 0 +Line 1808: 0 +Line 1809: 0 +Line 1810: 0 +Line 1811: 0 +Line 1812: 0 +Line 1813: 0 +Line 1814: 0 +Line 1815: 0 +Line 1816: 0 +Line 1817: 0 +Line 1818: 0 +Line 1819: 0 +Line 1820: 0 +Line 1821: 0 +Line 1822: 0 +Line 1823: 0 +Line 1824: 0 +Line 1825: 0 +Line 1826: 1 +Line 1827: 0 +Line 1828: 0 +Line 1829: 0 +Line 1830: 0 +Line 1831: 0 +Line 1832: 0 +Line 1833: 0 +Line 1834: 1 +Line 1835: 1 +Line 1836: 1 +Line 1837: 1 +Line 1838: 0 +Line 1839: 1 +Line 1840: 0 +Line 1841: 0 +Line 1842: 0 +Line 1843: 0 +Line 1844: 0 +Line 1845: 0 +Line 1846: 0 +Line 1847: 0 +Line 1848: 0 +Line 1849: 0 +Line 1850: 0 +Line 1851: 0 +Line 1852: 0 +Line 1853: 0 +Line 1854: 0 +Line 1855: 0 +Line 1856: 0 +Line 1857: 0 +Line 1858: 1 +Line 1859: 0 +Line 1860: 0 +Line 1861: 0 +Line 1862: 0 +Line 1863: 1 +Line 1864: 0 +Line 1865: 1 +Line 1866: 1 +Line 1867: 0 +Line 1868: 0 +Line 1869: 1 +Line 1870: 1 +Line 1871: 1 +Line 1872: 0 +Line 1873: 0 +Line 1874: 0 +Line 1875: 0 +Line 1876: 0 +Line 1877: 0 +Line 1878: 0 +Line 1879: 0 +Line 1880: 0 +Line 1881: 0 +Line 1882: 0 +Line 1883: 0 +Line 1884: 0 +Line 1885: 0 +Line 1886: 0 +Line 1887: 0 +Line 1888: 0 +Line 1889: 0 +Line 1890: 1 +Line 1891: 0 +Line 1892: 0 +Line 1893: 0 +Line 1894: 1 +Line 1895: 0 +Line 1896: 1 +Line 1897: 0 +Line 1898: 0 +Line 1899: 1 +Line 1900: 0 +Line 1901: 0 +Line 1902: 1 +Line 1903: 0 +Line 1904: 0 +Line 1905: 0 +Line 1906: 0 +Line 1907: 0 +Line 1908: 0 +Line 1909: 0 +Line 1910: 0 +Line 1911: 0 +Line 1912: 0 +Line 1913: 0 +Line 1914: 0 +Line 1915: 0 +Line 1916: 0 +Line 1917: 0 +Line 1918: 0 +Line 1919: 0 +Line 1920: 0 +Line 1921: 0 +Line 1922: 1 +Line 1923: 0 +Line 1924: 0 +Line 1925: 0 +Line 1926: 1 +Line 1927: 1 +Line 1928: 1 +Line 1929: 0 +Line 1930: 1 +Line 1931: 1 +Line 1932: 1 +Line 1933: 1 +Line 1934: 0 +Line 1935: 1 +Line 1936: 0 +Line 1937: 0 +Line 1938: 0 +Line 1939: 0 +Line 1940: 0 +Line 1941: 0 +Line 1942: 0 +Line 1943: 0 +Line 1944: 0 +Line 1945: 0 +Line 1946: 0 +Line 1947: 0 +Line 1948: 0 +Line 1949: 0 +Line 1950: 0 +Line 1951: 0 +Line 1952: 0 +Line 1953: 0 +Line 1954: 1 +Line 1955: 0 +Line 1956: 0 +Line 1957: 1 +Line 1958: 0 +Line 1959: 0 +Line 1960: 1 +Line 1961: 1 +Line 1962: 1 +Line 1963: 0 +Line 1964: 1 +Line 1965: 0 +Line 1966: 0 +Line 1967: 0 +Line 1968: 0 +Line 1969: 0 +Line 1970: 0 +Line 1971: 0 +Line 1972: 0 +Line 1973: 0 +Line 1974: 0 +Line 1975: 0 +Line 1976: 0 +Line 1977: 0 +Line 1978: 0 +Line 1979: 0 +Line 1980: 0 +Line 1981: 0 +Line 1982: 0 +Line 1983: 0 +Line 1984: 0 +Line 1985: 0 +Line 1986: 1 +Line 1987: 0 +Line 1988: 0 +Line 1989: 1 +Line 1990: 1 +Line 1991: 0 +Line 1992: 0 +Line 1993: 0 +Line 1994: 0 +Line 1995: 1 +Line 1996: 0 +Line 1997: 0 +Line 1998: 1 +Line 1999: 0 +Line 2000: 0 +Line 2001: 0 +Line 2002: 0 +Line 2003: 0 +Line 2004: 0 +Line 2005: 0 +Line 2006: 0 +Line 2007: 0 +Line 2008: 0 +Line 2009: 0 +Line 2010: 0 +Line 2011: 0 +Line 2012: 0 +Line 2013: 0 +Line 2014: 0 +Line 2015: 0 +Line 2016: 0 +Line 2017: 0 +Line 2018: 1 +Line 2019: 0 +Line 2020: 0 +Line 2021: 1 +Line 2022: 1 +Line 2023: 1 +Line 2024: 0 +Line 2025: 0 +Line 2026: 1 +Line 2027: 1 +Line 2028: 1 +Line 2029: 0 +Line 2030: 1 +Line 2031: 1 +Line 2032: 0 +Line 2033: 0 +Line 2034: 0 +Line 2035: 0 +Line 2036: 0 +Line 2037: 0 +Line 2038: 0 +Line 2039: 0 +Line 2040: 0 +Line 2041: 0 +Line 2042: 0 +Line 2043: 0 +Line 2044: 0 +Line 2045: 0 +Line 2046: 0 +Line 2047: 0 +Line 2048: 0 +Line 2049: 0 +Line 2050: 1 +Line 2051: 0 +Line 2052: 1 +Line 2053: 0 +Line 2054: 0 +Line 2055: 0 +Line 2056: 0 +Line 2057: 1 +Line 2058: 1 +Line 2059: 0 +Line 2060: 0 +Line 2061: 0 +Line 2062: 1 +Line 2063: 0 +Line 2064: 0 +Line 2065: 0 +Line 2066: 0 +Line 2067: 0 +Line 2068: 0 +Line 2069: 0 +Line 2070: 0 +Line 2071: 0 +Line 2072: 0 +Line 2073: 0 +Line 2074: 0 +Line 2075: 0 +Line 2076: 0 +Line 2077: 0 +Line 2078: 0 +Line 2079: 0 +Line 2080: 0 +Line 2081: 0 +Line 2082: 1 +Line 2083: 0 +Line 2084: 1 +Line 2085: 0 +Line 2086: 0 +Line 2087: 1 +Line 2088: 1 +Line 2089: 0 +Line 2090: 0 +Line 2091: 0 +Line 2092: 0 +Line 2093: 1 +Line 2094: 1 +Line 2095: 1 +Line 2096: 0 +Line 2097: 0 +Line 2098: 0 +Line 2099: 0 +Line 2100: 0 +Line 2101: 0 +Line 2102: 0 +Line 2103: 0 +Line 2104: 0 +Line 2105: 0 +Line 2106: 0 +Line 2107: 0 +Line 2108: 0 +Line 2109: 0 +Line 2110: 0 +Line 2111: 0 +Line 2112: 0 +Line 2113: 0 +Line 2114: 1 +Line 2115: 0 +Line 2116: 1 +Line 2117: 0 +Line 2118: 1 +Line 2119: 0 +Line 2120: 1 +Line 2121: 0 +Line 2122: 1 +Line 2123: 0 +Line 2124: 1 +Line 2125: 0 +Line 2126: 0 +Line 2127: 1 +Line 2128: 0 +Line 2129: 0 +Line 2130: 0 +Line 2131: 0 +Line 2132: 0 +Line 2133: 0 +Line 2134: 0 +Line 2135: 0 +Line 2136: 0 +Line 2137: 0 +Line 2138: 0 +Line 2139: 0 +Line 2140: 0 +Line 2141: 0 +Line 2142: 0 +Line 2143: 0 +Line 2144: 0 +Line 2145: 0 +Line 2146: 1 +Line 2147: 0 +Line 2148: 1 +Line 2149: 0 +Line 2150: 1 +Line 2151: 1 +Line 2152: 1 +Line 2153: 1 +Line 2154: 0 +Line 2155: 0 +Line 2156: 1 +Line 2157: 0 +Line 2158: 0 +Line 2159: 0 +Line 2160: 0 +Line 2161: 0 +Line 2162: 0 +Line 2163: 0 +Line 2164: 0 +Line 2165: 0 +Line 2166: 0 +Line 2167: 0 +Line 2168: 0 +Line 2169: 0 +Line 2170: 0 +Line 2171: 0 +Line 2172: 0 +Line 2173: 0 +Line 2174: 0 +Line 2175: 0 +Line 2176: 0 +Line 2177: 0 +Line 2178: 1 +Line 2179: 0 +Line 2180: 1 +Line 2181: 1 +Line 2182: 0 +Line 2183: 0 +Line 2184: 1 +Line 2185: 1 +Line 2186: 1 +Line 2187: 0 +Line 2188: 0 +Line 2189: 0 +Line 2190: 1 +Line 2191: 1 +Line 2192: 0 +Line 2193: 0 +Line 2194: 0 +Line 2195: 0 +Line 2196: 0 +Line 2197: 0 +Line 2198: 0 +Line 2199: 0 +Line 2200: 0 +Line 2201: 0 +Line 2202: 0 +Line 2203: 0 +Line 2204: 0 +Line 2205: 0 +Line 2206: 0 +Line 2207: 0 +Line 2208: 0 +Line 2209: 0 +Line 2210: 1 +Line 2211: 0 +Line 2212: 1 +Line 2213: 1 +Line 2214: 0 +Line 2215: 1 +Line 2216: 1 +Line 2217: 1 +Line 2218: 1 +Line 2219: 1 +Line 2220: 1 +Line 2221: 0 +Line 2222: 0 +Line 2223: 1 +Line 2224: 0 +Line 2225: 0 +Line 2226: 0 +Line 2227: 0 +Line 2228: 0 +Line 2229: 0 +Line 2230: 0 +Line 2231: 0 +Line 2232: 0 +Line 2233: 0 +Line 2234: 0 +Line 2235: 0 +Line 2236: 0 +Line 2237: 0 +Line 2238: 0 +Line 2239: 0 +Line 2240: 0 +Line 2241: 0 +Line 2242: 1 +Line 2243: 0 +Line 2244: 1 +Line 2245: 1 +Line 2246: 1 +Line 2247: 1 +Line 2248: 0 +Line 2249: 0 +Line 2250: 0 +Line 2251: 0 +Line 2252: 1 +Line 2253: 1 +Line 2254: 0 +Line 2255: 0 +Line 2256: 0 +Line 2257: 0 +Line 2258: 0 +Line 2259: 0 +Line 2260: 0 +Line 2261: 0 +Line 2262: 0 +Line 2263: 0 +Line 2264: 0 +Line 2265: 0 +Line 2266: 0 +Line 2267: 0 +Line 2268: 0 +Line 2269: 0 +Line 2270: 0 +Line 2271: 0 +Line 2272: 0 +Line 2273: 0 +Line 2274: 1 +Line 2275: 1 +Line 2276: 0 +Line 2277: 0 +Line 2278: 0 +Line 2279: 0 +Line 2280: 0 +Line 2281: 0 +Line 2282: 0 +Line 2283: 1 +Line 2284: 1 +Line 2285: 0 +Line 2286: 0 +Line 2287: 1 +Line 2288: 0 +Line 2289: 0 +Line 2290: 0 +Line 2291: 0 +Line 2292: 0 +Line 2293: 0 +Line 2294: 0 +Line 2295: 0 +Line 2296: 0 +Line 2297: 0 +Line 2298: 0 +Line 2299: 0 +Line 2300: 0 +Line 2301: 0 +Line 2302: 0 +Line 2303: 0 +Line 2304: 0 +Line 2305: 0 +Line 2306: 1 +Line 2307: 1 +Line 2308: 0 +Line 2309: 0 +Line 2310: 0 +Line 2311: 1 +Line 2312: 0 +Line 2313: 0 +Line 2314: 1 +Line 2315: 0 +Line 2316: 0 +Line 2317: 0 +Line 2318: 0 +Line 2319: 1 +Line 2320: 0 +Line 2321: 0 +Line 2322: 0 +Line 2323: 0 +Line 2324: 0 +Line 2325: 0 +Line 2326: 0 +Line 2327: 0 +Line 2328: 0 +Line 2329: 0 +Line 2330: 0 +Line 2331: 0 +Line 2332: 0 +Line 2333: 0 +Line 2334: 0 +Line 2335: 0 +Line 2336: 0 +Line 2337: 0 +Line 2338: 1 +Line 2339: 1 +Line 2340: 0 +Line 2341: 0 +Line 2342: 1 +Line 2343: 0 +Line 2344: 0 +Line 2345: 0 +Line 2346: 1 +Line 2347: 0 +Line 2348: 0 +Line 2349: 1 +Line 2350: 0 +Line 2351: 0 +Line 2352: 0 +Line 2353: 0 +Line 2354: 0 +Line 2355: 0 +Line 2356: 0 +Line 2357: 0 +Line 2358: 0 +Line 2359: 0 +Line 2360: 0 +Line 2361: 0 +Line 2362: 0 +Line 2363: 0 +Line 2364: 0 +Line 2365: 0 +Line 2366: 0 +Line 2367: 0 +Line 2368: 0 +Line 2369: 0 +Line 2370: 1 +Line 2371: 1 +Line 2372: 0 +Line 2373: 0 +Line 2374: 1 +Line 2375: 1 +Line 2376: 0 +Line 2377: 0 +Line 2378: 1 +Line 2379: 0 +Line 2380: 0 +Line 2381: 0 +Line 2382: 0 +Line 2383: 0 +Line 2384: 0 +Line 2385: 0 +Line 2386: 0 +Line 2387: 0 +Line 2388: 0 +Line 2389: 0 +Line 2390: 0 +Line 2391: 0 +Line 2392: 0 +Line 2393: 0 +Line 2394: 0 +Line 2395: 0 +Line 2396: 0 +Line 2397: 0 +Line 2398: 0 +Line 2399: 0 +Line 2400: 0 +Line 2401: 0 +Line 2402: 1 +Line 2403: 1 +Line 2404: 0 +Line 2405: 1 +Line 2406: 0 +Line 2407: 0 +Line 2408: 0 +Line 2409: 0 +Line 2410: 0 +Line 2411: 1 +Line 2412: 0 +Line 2413: 1 +Line 2414: 1 +Line 2415: 0 +Line 2416: 0 +Line 2417: 0 +Line 2418: 0 +Line 2419: 0 +Line 2420: 0 +Line 2421: 0 +Line 2422: 0 +Line 2423: 0 +Line 2424: 0 +Line 2425: 0 +Line 2426: 0 +Line 2427: 0 +Line 2428: 0 +Line 2429: 0 +Line 2430: 0 +Line 2431: 0 +Line 2432: 0 +Line 2433: 0 +Line 2434: 1 +Line 2435: 1 +Line 2436: 0 +Line 2437: 1 +Line 2438: 0 +Line 2439: 1 +Line 2440: 0 +Line 2441: 0 +Line 2442: 0 +Line 2443: 0 +Line 2444: 0 +Line 2445: 1 +Line 2446: 1 +Line 2447: 0 +Line 2448: 0 +Line 2449: 0 +Line 2450: 0 +Line 2451: 0 +Line 2452: 0 +Line 2453: 0 +Line 2454: 0 +Line 2455: 0 +Line 2456: 0 +Line 2457: 0 +Line 2458: 0 +Line 2459: 0 +Line 2460: 0 +Line 2461: 0 +Line 2462: 0 +Line 2463: 0 +Line 2464: 0 +Line 2465: 0 +Line 2466: 1 +Line 2467: 1 +Line 2468: 0 +Line 2469: 1 +Line 2470: 0 +Line 2471: 1 +Line 2472: 1 +Line 2473: 1 +Line 2474: 1 +Line 2475: 0 +Line 2476: 1 +Line 2477: 1 +Line 2478: 1 +Line 2479: 0 +Line 2480: 0 +Line 2481: 0 +Line 2482: 0 +Line 2483: 0 +Line 2484: 0 +Line 2485: 0 +Line 2486: 0 +Line 2487: 0 +Line 2488: 0 +Line 2489: 0 +Line 2490: 0 +Line 2491: 0 +Line 2492: 0 +Line 2493: 0 +Line 2494: 0 +Line 2495: 0 +Line 2496: 0 +Line 2497: 0 +Line 2498: 1 +Line 2499: 1 +Line 2500: 0 +Line 2501: 1 +Line 2502: 1 +Line 2503: 0 +Line 2504: 1 +Line 2505: 1 +Line 2506: 0 +Line 2507: 1 +Line 2508: 0 +Line 2509: 0 +Line 2510: 0 +Line 2511: 0 +Line 2512: 0 +Line 2513: 0 +Line 2514: 0 +Line 2515: 0 +Line 2516: 0 +Line 2517: 0 +Line 2518: 0 +Line 2519: 0 +Line 2520: 0 +Line 2521: 0 +Line 2522: 0 +Line 2523: 0 +Line 2524: 0 +Line 2525: 0 +Line 2526: 0 +Line 2527: 0 +Line 2528: 0 +Line 2529: 0 +Line 2530: 1 +Line 2531: 1 +Line 2532: 0 +Line 2533: 1 +Line 2534: 1 +Line 2535: 1 +Line 2536: 1 +Line 2537: 0 +Line 2538: 1 +Line 2539: 0 +Line 2540: 1 +Line 2541: 0 +Line 2542: 1 +Line 2543: 1 +Line 2544: 0 +Line 2545: 0 +Line 2546: 0 +Line 2547: 0 +Line 2548: 0 +Line 2549: 0 +Line 2550: 0 +Line 2551: 0 +Line 2552: 0 +Line 2553: 0 +Line 2554: 0 +Line 2555: 0 +Line 2556: 0 +Line 2557: 0 +Line 2558: 0 +Line 2559: 0 +Line 2560: 0 +Line 2561: 0 +Line 2562: 1 +Line 2563: 1 +Line 2564: 1 +Line 2565: 0 +Line 2566: 0 +Line 2567: 0 +Line 2568: 0 +Line 2569: 1 +Line 2570: 1 +Line 2571: 1 +Line 2572: 1 +Line 2573: 1 +Line 2574: 1 +Line 2575: 0 +Line 2576: 0 +Line 2577: 0 +Line 2578: 0 +Line 2579: 0 +Line 2580: 0 +Line 2581: 0 +Line 2582: 0 +Line 2583: 0 +Line 2584: 0 +Line 2585: 0 +Line 2586: 0 +Line 2587: 0 +Line 2588: 0 +Line 2589: 0 +Line 2590: 0 +Line 2591: 0 +Line 2592: 0 +Line 2593: 0 +Line 2594: 1 +Line 2595: 1 +Line 2596: 1 +Line 2597: 0 +Line 2598: 0 +Line 2599: 1 +Line 2600: 0 +Line 2601: 1 +Line 2602: 0 +Line 2603: 0 +Line 2604: 1 +Line 2605: 0 +Line 2606: 1 +Line 2607: 0 +Line 2608: 0 +Line 2609: 0 +Line 2610: 0 +Line 2611: 0 +Line 2612: 0 +Line 2613: 0 +Line 2614: 0 +Line 2615: 0 +Line 2616: 0 +Line 2617: 0 +Line 2618: 0 +Line 2619: 0 +Line 2620: 0 +Line 2621: 0 +Line 2622: 0 +Line 2623: 0 +Line 2624: 0 +Line 2625: 0 +Line 2626: 1 +Line 2627: 1 +Line 2628: 1 +Line 2629: 0 +Line 2630: 1 +Line 2631: 0 +Line 2632: 0 +Line 2633: 0 +Line 2634: 0 +Line 2635: 0 +Line 2636: 1 +Line 2637: 1 +Line 2638: 1 +Line 2639: 1 +Line 2640: 0 +Line 2641: 0 +Line 2642: 0 +Line 2643: 0 +Line 2644: 0 +Line 2645: 0 +Line 2646: 0 +Line 2647: 0 +Line 2648: 0 +Line 2649: 0 +Line 2650: 0 +Line 2651: 0 +Line 2652: 0 +Line 2653: 0 +Line 2654: 0 +Line 2655: 0 +Line 2656: 0 +Line 2657: 0 +Line 2658: 1 +Line 2659: 1 +Line 2660: 1 +Line 2661: 0 +Line 2662: 1 +Line 2663: 0 +Line 2664: 1 +Line 2665: 1 +Line 2666: 0 +Line 2667: 0 +Line 2668: 1 +Line 2669: 1 +Line 2670: 0 +Line 2671: 0 +Line 2672: 0 +Line 2673: 0 +Line 2674: 0 +Line 2675: 0 +Line 2676: 0 +Line 2677: 0 +Line 2678: 0 +Line 2679: 0 +Line 2680: 0 +Line 2681: 0 +Line 2682: 0 +Line 2683: 0 +Line 2684: 0 +Line 2685: 0 +Line 2686: 0 +Line 2687: 0 +Line 2688: 0 +Line 2689: 0 +Line 2690: 1 +Line 2691: 1 +Line 2692: 1 +Line 2693: 0 +Line 2694: 1 +Line 2695: 1 +Line 2696: 1 +Line 2697: 0 +Line 2698: 0 +Line 2699: 0 +Line 2700: 0 +Line 2701: 0 +Line 2702: 0 +Line 2703: 1 +Line 2704: 0 +Line 2705: 0 +Line 2706: 0 +Line 2707: 0 +Line 2708: 0 +Line 2709: 0 +Line 2710: 0 +Line 2711: 0 +Line 2712: 0 +Line 2713: 0 +Line 2714: 0 +Line 2715: 0 +Line 2716: 0 +Line 2717: 0 +Line 2718: 0 +Line 2719: 0 +Line 2720: 0 +Line 2721: 0 +Line 2722: 1 +Line 2723: 1 +Line 2724: 1 +Line 2725: 1 +Line 2726: 0 +Line 2727: 0 +Line 2728: 0 +Line 2729: 0 +Line 2730: 1 +Line 2731: 0 +Line 2732: 1 +Line 2733: 1 +Line 2734: 1 +Line 2735: 1 +Line 2736: 0 +Line 2737: 0 +Line 2738: 0 +Line 2739: 0 +Line 2740: 0 +Line 2741: 0 +Line 2742: 0 +Line 2743: 0 +Line 2744: 0 +Line 2745: 0 +Line 2746: 0 +Line 2747: 0 +Line 2748: 0 +Line 2749: 0 +Line 2750: 0 +Line 2751: 0 +Line 2752: 0 +Line 2753: 0 +Line 2754: 1 +Line 2755: 1 +Line 2756: 1 +Line 2757: 1 +Line 2758: 0 +Line 2759: 0 +Line 2760: 1 +Line 2761: 1 +Line 2762: 0 +Line 2763: 1 +Line 2764: 0 +Line 2765: 1 +Line 2766: 1 +Line 2767: 0 +Line 2768: 0 +Line 2769: 0 +Line 2770: 0 +Line 2771: 0 +Line 2772: 0 +Line 2773: 0 +Line 2774: 0 +Line 2775: 0 +Line 2776: 0 +Line 2777: 0 +Line 2778: 0 +Line 2779: 0 +Line 2780: 0 +Line 2781: 0 +Line 2782: 0 +Line 2783: 0 +Line 2784: 0 +Line 2785: 0 +Line 2786: 1 +Line 2787: 1 +Line 2788: 1 +Line 2789: 1 +Line 2790: 0 +Line 2791: 1 +Line 2792: 0 +Line 2793: 1 +Line 2794: 1 +Line 2795: 1 +Line 2796: 0 +Line 2797: 1 +Line 2798: 0 +Line 2799: 1 +Line 2800: 0 +Line 2801: 0 +Line 2802: 0 +Line 2803: 0 +Line 2804: 0 +Line 2805: 0 +Line 2806: 0 +Line 2807: 0 +Line 2808: 0 +Line 2809: 0 +Line 2810: 0 +Line 2811: 0 +Line 2812: 0 +Line 2813: 0 +Line 2814: 0 +Line 2815: 0 +Line 2816: 0 +Line 2817: 0 +Line 2818: 1 +Line 2819: 1 +Line 2820: 1 +Line 2821: 1 +Line 2822: 1 +Line 2823: 0 +Line 2824: 0 +Line 2825: 0 +Line 2826: 0 +Line 2827: 0 +Line 2828: 1 +Line 2829: 1 +Line 2830: 0 +Line 2831: 0 +Line 2832: 0 +Line 2833: 0 +Line 2834: 0 +Line 2835: 0 +Line 2836: 0 +Line 2837: 0 +Line 2838: 0 +Line 2839: 0 +Line 2840: 0 +Line 2841: 0 +Line 2842: 0 +Line 2843: 0 +Line 2844: 0 +Line 2845: 0 +Line 2846: 0 +Line 2847: 0 +Line 2848: 0 +Line 2849: 0 +Line 2850: 1 +Line 2851: 1 +Line 2852: 1 +Line 2853: 1 +Line 2854: 1 +Line 2855: 0 +Line 2856: 1 +Line 2857: 0 +Line 2858: 0 +Line 2859: 1 +Line 2860: 1 +Line 2861: 1 +Line 2862: 0 +Line 2863: 0 +Line 2864: 0 +Line 2865: 0 +Line 2866: 0 +Line 2867: 0 +Line 2868: 0 +Line 2869: 0 +Line 2870: 0 +Line 2871: 0 +Line 2872: 0 +Line 2873: 0 +Line 2874: 0 +Line 2875: 0 +Line 2876: 0 +Line 2877: 0 +Line 2878: 0 +Line 2879: 0 +Line 2880: 0 +Line 2881: 0 +Line 2882: 1 +Line 2883: 1 +Line 2884: 1 +Line 2885: 1 +Line 2886: 1 +Line 2887: 1 +Line 2888: 0 +Line 2889: 0 +Line 2890: 1 +Line 2891: 0 +Line 2892: 0 +Line 2893: 1 +Line 2894: 0 +Line 2895: 1 +Line 2896: 0 +Line 2897: 0 +Line 2898: 0 +Line 2899: 0 +Line 2900: 0 +Line 2901: 0 +Line 2902: 0 +Line 2903: 0 +Line 2904: 0 +Line 2905: 0 +Line 2906: 0 +Line 2907: 0 +Line 2908: 0 +Line 2909: 0 +Line 2910: 0 +Line 2911: 0 +Line 2912: 0 +Line 2913: 0 +Line 2914: 1 +Line 2915: 1 +Line 2916: 1 +Line 2917: 1 +Line 2918: 1 +Line 2919: 1 +Line 2920: 1 +Line 2921: 0 +Line 2922: 1 +Line 2923: 0 +Line 2924: 0 +Line 2925: 1 +Line 2926: 1 +Line 2927: 1 +Line 2928: 0 +Line 2929: 0 +Line 2930: 0 +Line 2931: 0 +Line 2932: 0 +Line 2933: 0 +Line 2934: 0 +Line 2935: 0 +Line 2936: 0 +Line 2937: 0 +Line 2938: 0 +Line 2939: 0 +Line 2940: 0 +Line 2941: 0 +Line 2942: 0 +Line 2943: 0 +Line 2944: 0 +Line 2945: 1 +Line 2946: 0 +Line 2947: 0 +Line 2948: 0 +Line 2949: 0 +Line 2950: 0 +Line 2951: 0 +Line 2952: 0 +Line 2953: 0 +Line 2954: 1 +Line 2955: 0 +Line 2956: 0 +Line 2957: 0 +Line 2958: 1 +Line 2959: 0 +Line 2960: 0 +Line 2961: 0 +Line 2962: 0 +Line 2963: 0 +Line 2964: 0 +Line 2965: 0 +Line 2966: 0 +Line 2967: 0 +Line 2968: 0 +Line 2969: 0 +Line 2970: 0 +Line 2971: 0 +Line 2972: 0 +Line 2973: 0 +Line 2974: 0 +Line 2975: 0 +Line 2976: 0 +Line 2977: 1 +Line 2978: 0 +Line 2979: 0 +Line 2980: 0 +Line 2981: 0 +Line 2982: 0 +Line 2983: 0 +Line 2984: 1 +Line 2985: 0 +Line 2986: 0 +Line 2987: 1 +Line 2988: 0 +Line 2989: 1 +Line 2990: 1 +Line 2991: 1 +Line 2992: 0 +Line 2993: 0 +Line 2994: 0 +Line 2995: 0 +Line 2996: 0 +Line 2997: 0 +Line 2998: 0 +Line 2999: 0 +Line 3000: 0 +Line 3001: 0 +Line 3002: 0 +Line 3003: 0 +Line 3004: 0 +Line 3005: 0 +Line 3006: 0 +Line 3007: 0 +Line 3008: 0 +Line 3009: 1 +Line 3010: 0 +Line 3011: 0 +Line 3012: 0 +Line 3013: 0 +Line 3014: 0 +Line 3015: 1 +Line 3016: 0 +Line 3017: 0 +Line 3018: 0 +Line 3019: 0 +Line 3020: 0 +Line 3021: 1 +Line 3022: 0 +Line 3023: 0 +Line 3024: 0 +Line 3025: 0 +Line 3026: 0 +Line 3027: 0 +Line 3028: 0 +Line 3029: 0 +Line 3030: 0 +Line 3031: 0 +Line 3032: 0 +Line 3033: 0 +Line 3034: 0 +Line 3035: 0 +Line 3036: 0 +Line 3037: 0 +Line 3038: 0 +Line 3039: 0 +Line 3040: 0 +Line 3041: 1 +Line 3042: 0 +Line 3043: 0 +Line 3044: 0 +Line 3045: 0 +Line 3046: 0 +Line 3047: 1 +Line 3048: 0 +Line 3049: 1 +Line 3050: 1 +Line 3051: 0 +Line 3052: 1 +Line 3053: 1 +Line 3054: 0 +Line 3055: 0 +Line 3056: 0 +Line 3057: 0 +Line 3058: 0 +Line 3059: 0 +Line 3060: 0 +Line 3061: 0 +Line 3062: 0 +Line 3063: 0 +Line 3064: 0 +Line 3065: 0 +Line 3066: 0 +Line 3067: 0 +Line 3068: 0 +Line 3069: 0 +Line 3070: 0 +Line 3071: 0 +Line 3072: 0 +Line 3073: 1 +Line 3074: 0 +Line 3075: 0 +Line 3076: 0 +Line 3077: 0 +Line 3078: 0 +Line 3079: 1 +Line 3080: 0 +Line 3081: 1 +Line 3082: 1 +Line 3083: 0 +Line 3084: 1 +Line 3085: 1 +Line 3086: 0 +Line 3087: 0 +Line 3088: 0 +Line 3089: 0 +Line 3090: 0 +Line 3091: 0 +Line 3092: 0 +Line 3093: 0 +Line 3094: 0 +Line 3095: 0 +Line 3096: 0 +Line 3097: 0 +Line 3098: 0 +Line 3099: 0 +Line 3100: 0 +Line 3101: 0 +Line 3102: 0 +Line 3103: 0 +Line 3104: 0 +Line 3105: 1 +Line 3106: 0 +Line 3107: 0 +Line 3108: 0 +Line 3109: 0 +Line 3110: 0 +Line 3111: 1 +Line 3112: 0 +Line 3113: 0 +Line 3114: 0 +Line 3115: 0 +Line 3116: 0 +Line 3117: 1 +Line 3118: 0 +Line 3119: 0 +Line 3120: 0 +Line 3121: 0 +Line 3122: 0 +Line 3123: 0 +Line 3124: 0 +Line 3125: 0 +Line 3126: 0 +Line 3127: 0 +Line 3128: 0 +Line 3129: 0 +Line 3130: 0 +Line 3131: 0 +Line 3132: 0 +Line 3133: 0 +Line 3134: 0 +Line 3135: 0 +Line 3136: 0 +Line 3137: 1 +Line 3138: 0 +Line 3139: 0 +Line 3140: 0 +Line 3141: 0 +Line 3142: 0 +Line 3143: 0 +Line 3144: 1 +Line 3145: 0 +Line 3146: 0 +Line 3147: 1 +Line 3148: 0 +Line 3149: 1 +Line 3150: 1 +Line 3151: 1 +Line 3152: 0 +Line 3153: 0 +Line 3154: 0 +Line 3155: 0 +Line 3156: 0 +Line 3157: 0 +Line 3158: 0 +Line 3159: 0 +Line 3160: 0 +Line 3161: 0 +Line 3162: 0 +Line 3163: 0 +Line 3164: 0 +Line 3165: 0 +Line 3166: 0 +Line 3167: 0 +Line 3168: 0 +Line 3169: 1 +Line 3170: 0 +Line 3171: 0 +Line 3172: 0 +Line 3173: 0 +Line 3174: 0 +Line 3175: 0 +Line 3176: 0 +Line 3177: 0 +Line 3178: 1 +Line 3179: 0 +Line 3180: 0 +Line 3181: 0 +Line 3182: 1 +Line 3183: 0 +Line 3184: 0 +Line 3185: 0 +Line 3186: 0 +Line 3187: 0 +Line 3188: 0 +Line 3189: 0 +Line 3190: 0 +Line 3191: 0 +Line 3192: 0 +Line 3193: 0 +Line 3194: 0 +Line 3195: 0 +Line 3196: 0 +Line 3197: 0 +Line 3198: 0 +Line 3199: 0 +Line 3200: 0 +Line 3201: 0 +Line 3202: 1 +Line 3203: 1 +Line 3204: 1 +Line 3205: 1 +Line 3206: 1 +Line 3207: 1 +Line 3208: 1 +Line 3209: 0 +Line 3210: 1 +Line 3211: 0 +Line 3212: 0 +Line 3213: 1 +Line 3214: 1 +Line 3215: 1 +Line 3216: 0 +Line 3217: 0 +Line 3218: 0 +Line 3219: 0 +Line 3220: 0 +Line 3221: 0 +Line 3222: 0 +Line 3223: 0 +Line 3224: 0 +Line 3225: 0 +Line 3226: 0 +Line 3227: 0 +Line 3228: 0 +Line 3229: 0 +Line 3230: 0 +Line 3231: 0 +Line 3232: 0 +Line 3233: 0 +Line 3234: 1 +Line 3235: 1 +Line 3236: 1 +Line 3237: 1 +Line 3238: 1 +Line 3239: 1 +Line 3240: 0 +Line 3241: 0 +Line 3242: 1 +Line 3243: 0 +Line 3244: 0 +Line 3245: 1 +Line 3246: 0 +Line 3247: 1 +Line 3248: 0 +Line 3249: 0 +Line 3250: 0 +Line 3251: 0 +Line 3252: 0 +Line 3253: 0 +Line 3254: 0 +Line 3255: 0 +Line 3256: 0 +Line 3257: 0 +Line 3258: 0 +Line 3259: 0 +Line 3260: 0 +Line 3261: 0 +Line 3262: 0 +Line 3263: 0 +Line 3264: 0 +Line 3265: 0 +Line 3266: 1 +Line 3267: 1 +Line 3268: 1 +Line 3269: 1 +Line 3270: 1 +Line 3271: 0 +Line 3272: 1 +Line 3273: 0 +Line 3274: 0 +Line 3275: 1 +Line 3276: 1 +Line 3277: 1 +Line 3278: 0 +Line 3279: 0 +Line 3280: 0 +Line 3281: 0 +Line 3282: 0 +Line 3283: 0 +Line 3284: 0 +Line 3285: 0 +Line 3286: 0 +Line 3287: 0 +Line 3288: 0 +Line 3289: 0 +Line 3290: 0 +Line 3291: 0 +Line 3292: 0 +Line 3293: 0 +Line 3294: 0 +Line 3295: 0 +Line 3296: 0 +Line 3297: 0 +Line 3298: 1 +Line 3299: 1 +Line 3300: 1 +Line 3301: 1 +Line 3302: 1 +Line 3303: 0 +Line 3304: 0 +Line 3305: 0 +Line 3306: 0 +Line 3307: 0 +Line 3308: 1 +Line 3309: 1 +Line 3310: 0 +Line 3311: 0 +Line 3312: 0 +Line 3313: 0 +Line 3314: 0 +Line 3315: 0 +Line 3316: 0 +Line 3317: 0 +Line 3318: 0 +Line 3319: 0 +Line 3320: 0 +Line 3321: 0 +Line 3322: 0 +Line 3323: 0 +Line 3324: 0 +Line 3325: 0 +Line 3326: 0 +Line 3327: 0 +Line 3328: 0 +Line 3329: 0 +Line 3330: 1 +Line 3331: 1 +Line 3332: 1 +Line 3333: 1 +Line 3334: 0 +Line 3335: 1 +Line 3336: 0 +Line 3337: 1 +Line 3338: 1 +Line 3339: 1 +Line 3340: 0 +Line 3341: 1 +Line 3342: 0 +Line 3343: 1 +Line 3344: 0 +Line 3345: 0 +Line 3346: 0 +Line 3347: 0 +Line 3348: 0 +Line 3349: 0 +Line 3350: 0 +Line 3351: 0 +Line 3352: 0 +Line 3353: 0 +Line 3354: 0 +Line 3355: 0 +Line 3356: 0 +Line 3357: 0 +Line 3358: 0 +Line 3359: 0 +Line 3360: 0 +Line 3361: 0 +Line 3362: 1 +Line 3363: 1 +Line 3364: 1 +Line 3365: 1 +Line 3366: 0 +Line 3367: 0 +Line 3368: 1 +Line 3369: 1 +Line 3370: 0 +Line 3371: 1 +Line 3372: 0 +Line 3373: 1 +Line 3374: 1 +Line 3375: 0 +Line 3376: 0 +Line 3377: 0 +Line 3378: 0 +Line 3379: 0 +Line 3380: 0 +Line 3381: 0 +Line 3382: 0 +Line 3383: 0 +Line 3384: 0 +Line 3385: 0 +Line 3386: 0 +Line 3387: 0 +Line 3388: 0 +Line 3389: 0 +Line 3390: 0 +Line 3391: 0 +Line 3392: 0 +Line 3393: 0 +Line 3394: 1 +Line 3395: 1 +Line 3396: 1 +Line 3397: 1 +Line 3398: 0 +Line 3399: 0 +Line 3400: 0 +Line 3401: 0 +Line 3402: 1 +Line 3403: 0 +Line 3404: 1 +Line 3405: 1 +Line 3406: 1 +Line 3407: 1 +Line 3408: 0 +Line 3409: 0 +Line 3410: 0 +Line 3411: 0 +Line 3412: 0 +Line 3413: 0 +Line 3414: 0 +Line 3415: 0 +Line 3416: 0 +Line 3417: 0 +Line 3418: 0 +Line 3419: 0 +Line 3420: 0 +Line 3421: 0 +Line 3422: 0 +Line 3423: 0 +Line 3424: 0 +Line 3425: 0 +Line 3426: 1 +Line 3427: 1 +Line 3428: 1 +Line 3429: 0 +Line 3430: 1 +Line 3431: 1 +Line 3432: 1 +Line 3433: 0 +Line 3434: 0 +Line 3435: 0 +Line 3436: 0 +Line 3437: 0 +Line 3438: 0 +Line 3439: 1 +Line 3440: 0 +Line 3441: 0 +Line 3442: 0 +Line 3443: 0 +Line 3444: 0 +Line 3445: 0 +Line 3446: 0 +Line 3447: 0 +Line 3448: 0 +Line 3449: 0 +Line 3450: 0 +Line 3451: 0 +Line 3452: 0 +Line 3453: 0 +Line 3454: 0 +Line 3455: 0 +Line 3456: 0 +Line 3457: 0 +Line 3458: 1 +Line 3459: 1 +Line 3460: 1 +Line 3461: 0 +Line 3462: 1 +Line 3463: 0 +Line 3464: 1 +Line 3465: 1 +Line 3466: 0 +Line 3467: 0 +Line 3468: 1 +Line 3469: 1 +Line 3470: 0 +Line 3471: 0 +Line 3472: 0 +Line 3473: 0 +Line 3474: 0 +Line 3475: 0 +Line 3476: 0 +Line 3477: 0 +Line 3478: 0 +Line 3479: 0 +Line 3480: 0 +Line 3481: 0 +Line 3482: 0 +Line 3483: 0 +Line 3484: 0 +Line 3485: 0 +Line 3486: 0 +Line 3487: 0 +Line 3488: 0 +Line 3489: 0 +Line 3490: 1 +Line 3491: 1 +Line 3492: 1 +Line 3493: 0 +Line 3494: 1 +Line 3495: 0 +Line 3496: 0 +Line 3497: 0 +Line 3498: 0 +Line 3499: 0 +Line 3500: 1 +Line 3501: 1 +Line 3502: 1 +Line 3503: 1 +Line 3504: 0 +Line 3505: 0 +Line 3506: 0 +Line 3507: 0 +Line 3508: 0 +Line 3509: 0 +Line 3510: 0 +Line 3511: 0 +Line 3512: 0 +Line 3513: 0 +Line 3514: 0 +Line 3515: 0 +Line 3516: 0 +Line 3517: 0 +Line 3518: 0 +Line 3519: 0 +Line 3520: 0 +Line 3521: 0 +Line 3522: 1 +Line 3523: 1 +Line 3524: 1 +Line 3525: 0 +Line 3526: 0 +Line 3527: 1 +Line 3528: 0 +Line 3529: 1 +Line 3530: 0 +Line 3531: 0 +Line 3532: 1 +Line 3533: 0 +Line 3534: 1 +Line 3535: 0 +Line 3536: 0 +Line 3537: 0 +Line 3538: 0 +Line 3539: 0 +Line 3540: 0 +Line 3541: 0 +Line 3542: 0 +Line 3543: 0 +Line 3544: 0 +Line 3545: 0 +Line 3546: 0 +Line 3547: 0 +Line 3548: 0 +Line 3549: 0 +Line 3550: 0 +Line 3551: 0 +Line 3552: 0 +Line 3553: 0 +Line 3554: 1 +Line 3555: 1 +Line 3556: 1 +Line 3557: 0 +Line 3558: 0 +Line 3559: 0 +Line 3560: 0 +Line 3561: 1 +Line 3562: 1 +Line 3563: 1 +Line 3564: 1 +Line 3565: 1 +Line 3566: 1 +Line 3567: 0 +Line 3568: 0 +Line 3569: 0 +Line 3570: 0 +Line 3571: 0 +Line 3572: 0 +Line 3573: 0 +Line 3574: 0 +Line 3575: 0 +Line 3576: 0 +Line 3577: 0 +Line 3578: 0 +Line 3579: 0 +Line 3580: 0 +Line 3581: 0 +Line 3582: 0 +Line 3583: 0 +Line 3584: 0 +Line 3585: 0 +Line 3586: 1 +Line 3587: 1 +Line 3588: 0 +Line 3589: 1 +Line 3590: 1 +Line 3591: 1 +Line 3592: 1 +Line 3593: 0 +Line 3594: 1 +Line 3595: 0 +Line 3596: 1 +Line 3597: 0 +Line 3598: 1 +Line 3599: 1 +Line 3600: 0 +Line 3601: 0 +Line 3602: 0 +Line 3603: 0 +Line 3604: 0 +Line 3605: 0 +Line 3606: 0 +Line 3607: 0 +Line 3608: 0 +Line 3609: 0 +Line 3610: 0 +Line 3611: 0 +Line 3612: 0 +Line 3613: 0 +Line 3614: 0 +Line 3615: 0 +Line 3616: 0 +Line 3617: 0 +Line 3618: 1 +Line 3619: 1 +Line 3620: 0 +Line 3621: 1 +Line 3622: 1 +Line 3623: 0 +Line 3624: 1 +Line 3625: 1 +Line 3626: 0 +Line 3627: 1 +Line 3628: 0 +Line 3629: 0 +Line 3630: 0 +Line 3631: 0 +Line 3632: 0 +Line 3633: 0 +Line 3634: 0 +Line 3635: 0 +Line 3636: 0 +Line 3637: 0 +Line 3638: 0 +Line 3639: 0 +Line 3640: 0 +Line 3641: 0 +Line 3642: 0 +Line 3643: 0 +Line 3644: 0 +Line 3645: 0 +Line 3646: 0 +Line 3647: 0 +Line 3648: 0 +Line 3649: 0 +Line 3650: 1 +Line 3651: 1 +Line 3652: 0 +Line 3653: 1 +Line 3654: 0 +Line 3655: 1 +Line 3656: 1 +Line 3657: 1 +Line 3658: 1 +Line 3659: 0 +Line 3660: 1 +Line 3661: 1 +Line 3662: 1 +Line 3663: 0 +Line 3664: 0 +Line 3665: 0 +Line 3666: 0 +Line 3667: 0 +Line 3668: 0 +Line 3669: 0 +Line 3670: 0 +Line 3671: 0 +Line 3672: 0 +Line 3673: 0 +Line 3674: 0 +Line 3675: 0 +Line 3676: 0 +Line 3677: 0 +Line 3678: 0 +Line 3679: 0 +Line 3680: 0 +Line 3681: 0 +Line 3682: 1 +Line 3683: 1 +Line 3684: 0 +Line 3685: 1 +Line 3686: 0 +Line 3687: 1 +Line 3688: 0 +Line 3689: 0 +Line 3690: 0 +Line 3691: 0 +Line 3692: 0 +Line 3693: 1 +Line 3694: 1 +Line 3695: 0 +Line 3696: 0 +Line 3697: 0 +Line 3698: 0 +Line 3699: 0 +Line 3700: 0 +Line 3701: 0 +Line 3702: 0 +Line 3703: 0 +Line 3704: 0 +Line 3705: 0 +Line 3706: 0 +Line 3707: 0 +Line 3708: 0 +Line 3709: 0 +Line 3710: 0 +Line 3711: 0 +Line 3712: 0 +Line 3713: 0 +Line 3714: 1 +Line 3715: 1 +Line 3716: 0 +Line 3717: 1 +Line 3718: 0 +Line 3719: 0 +Line 3720: 0 +Line 3721: 0 +Line 3722: 0 +Line 3723: 1 +Line 3724: 0 +Line 3725: 1 +Line 3726: 1 +Line 3727: 0 +Line 3728: 0 +Line 3729: 0 +Line 3730: 0 +Line 3731: 0 +Line 3732: 0 +Line 3733: 0 +Line 3734: 0 +Line 3735: 0 +Line 3736: 0 +Line 3737: 0 +Line 3738: 0 +Line 3739: 0 +Line 3740: 0 +Line 3741: 0 +Line 3742: 0 +Line 3743: 0 +Line 3744: 0 +Line 3745: 0 +Line 3746: 1 +Line 3747: 1 +Line 3748: 0 +Line 3749: 0 +Line 3750: 1 +Line 3751: 1 +Line 3752: 0 +Line 3753: 0 +Line 3754: 1 +Line 3755: 0 +Line 3756: 0 +Line 3757: 0 +Line 3758: 0 +Line 3759: 0 +Line 3760: 0 +Line 3761: 0 +Line 3762: 0 +Line 3763: 0 +Line 3764: 0 +Line 3765: 0 +Line 3766: 0 +Line 3767: 0 +Line 3768: 0 +Line 3769: 0 +Line 3770: 0 +Line 3771: 0 +Line 3772: 0 +Line 3773: 0 +Line 3774: 0 +Line 3775: 0 +Line 3776: 0 +Line 3777: 0 +Line 3778: 1 +Line 3779: 1 +Line 3780: 0 +Line 3781: 0 +Line 3782: 1 +Line 3783: 0 +Line 3784: 0 +Line 3785: 0 +Line 3786: 1 +Line 3787: 0 +Line 3788: 0 +Line 3789: 1 +Line 3790: 0 +Line 3791: 0 +Line 3792: 0 +Line 3793: 0 +Line 3794: 0 +Line 3795: 0 +Line 3796: 0 +Line 3797: 0 +Line 3798: 0 +Line 3799: 0 +Line 3800: 0 +Line 3801: 0 +Line 3802: 0 +Line 3803: 0 +Line 3804: 0 +Line 3805: 0 +Line 3806: 0 +Line 3807: 0 +Line 3808: 0 +Line 3809: 0 +Line 3810: 1 +Line 3811: 1 +Line 3812: 0 +Line 3813: 0 +Line 3814: 0 +Line 3815: 1 +Line 3816: 0 +Line 3817: 0 +Line 3818: 1 +Line 3819: 0 +Line 3820: 0 +Line 3821: 0 +Line 3822: 0 +Line 3823: 1 +Line 3824: 0 +Line 3825: 0 +Line 3826: 0 +Line 3827: 0 +Line 3828: 0 +Line 3829: 0 +Line 3830: 0 +Line 3831: 0 +Line 3832: 0 +Line 3833: 0 +Line 3834: 0 +Line 3835: 0 +Line 3836: 0 +Line 3837: 0 +Line 3838: 0 +Line 3839: 0 +Line 3840: 0 +Line 3841: 0 +Line 3842: 1 +Line 3843: 1 +Line 3844: 0 +Line 3845: 0 +Line 3846: 0 +Line 3847: 0 +Line 3848: 0 +Line 3849: 0 +Line 3850: 0 +Line 3851: 1 +Line 3852: 1 +Line 3853: 0 +Line 3854: 0 +Line 3855: 1 +Line 3856: 0 +Line 3857: 0 +Line 3858: 0 +Line 3859: 0 +Line 3860: 0 +Line 3861: 0 +Line 3862: 0 +Line 3863: 0 +Line 3864: 0 +Line 3865: 0 +Line 3866: 0 +Line 3867: 0 +Line 3868: 0 +Line 3869: 0 +Line 3870: 0 +Line 3871: 0 +Line 3872: 0 +Line 3873: 0 +Line 3874: 1 +Line 3875: 0 +Line 3876: 1 +Line 3877: 1 +Line 3878: 1 +Line 3879: 1 +Line 3880: 0 +Line 3881: 0 +Line 3882: 0 +Line 3883: 0 +Line 3884: 1 +Line 3885: 1 +Line 3886: 0 +Line 3887: 0 +Line 3888: 0 +Line 3889: 0 +Line 3890: 0 +Line 3891: 0 +Line 3892: 0 +Line 3893: 0 +Line 3894: 0 +Line 3895: 0 +Line 3896: 0 +Line 3897: 0 +Line 3898: 0 +Line 3899: 0 +Line 3900: 0 +Line 3901: 0 +Line 3902: 0 +Line 3903: 0 +Line 3904: 0 +Line 3905: 0 +Line 3906: 1 +Line 3907: 0 +Line 3908: 1 +Line 3909: 1 +Line 3910: 0 +Line 3911: 1 +Line 3912: 1 +Line 3913: 1 +Line 3914: 1 +Line 3915: 1 +Line 3916: 1 +Line 3917: 0 +Line 3918: 0 +Line 3919: 1 +Line 3920: 0 +Line 3921: 0 +Line 3922: 0 +Line 3923: 0 +Line 3924: 0 +Line 3925: 0 +Line 3926: 0 +Line 3927: 0 +Line 3928: 0 +Line 3929: 0 +Line 3930: 0 +Line 3931: 0 +Line 3932: 0 +Line 3933: 0 +Line 3934: 0 +Line 3935: 0 +Line 3936: 0 +Line 3937: 0 +Line 3938: 1 +Line 3939: 0 +Line 3940: 1 +Line 3941: 1 +Line 3942: 0 +Line 3943: 0 +Line 3944: 1 +Line 3945: 1 +Line 3946: 1 +Line 3947: 0 +Line 3948: 0 +Line 3949: 0 +Line 3950: 1 +Line 3951: 1 +Line 3952: 0 +Line 3953: 0 +Line 3954: 0 +Line 3955: 0 +Line 3956: 0 +Line 3957: 0 +Line 3958: 0 +Line 3959: 0 +Line 3960: 0 +Line 3961: 0 +Line 3962: 0 +Line 3963: 0 +Line 3964: 0 +Line 3965: 0 +Line 3966: 0 +Line 3967: 0 +Line 3968: 0 +Line 3969: 0 +Line 3970: 1 +Line 3971: 0 +Line 3972: 1 +Line 3973: 0 +Line 3974: 1 +Line 3975: 1 +Line 3976: 1 +Line 3977: 1 +Line 3978: 0 +Line 3979: 0 +Line 3980: 1 +Line 3981: 0 +Line 3982: 0 +Line 3983: 0 +Line 3984: 0 +Line 3985: 0 +Line 3986: 0 +Line 3987: 0 +Line 3988: 0 +Line 3989: 0 +Line 3990: 0 +Line 3991: 0 +Line 3992: 0 +Line 3993: 0 +Line 3994: 0 +Line 3995: 0 +Line 3996: 0 +Line 3997: 0 +Line 3998: 0 +Line 3999: 0 +Line 4000: 0 +Line 4001: 0 +Line 4002: 1 +Line 4003: 0 +Line 4004: 1 +Line 4005: 0 +Line 4006: 1 +Line 4007: 0 +Line 4008: 1 +Line 4009: 0 +Line 4010: 1 +Line 4011: 0 +Line 4012: 1 +Line 4013: 0 +Line 4014: 0 +Line 4015: 1 +Line 4016: 0 +Line 4017: 0 +Line 4018: 0 +Line 4019: 0 +Line 4020: 0 +Line 4021: 0 +Line 4022: 0 +Line 4023: 0 +Line 4024: 0 +Line 4025: 0 +Line 4026: 0 +Line 4027: 0 +Line 4028: 0 +Line 4029: 0 +Line 4030: 0 +Line 4031: 0 +Line 4032: 0 +Line 4033: 0 +Line 4034: 1 +Line 4035: 0 +Line 4036: 1 +Line 4037: 0 +Line 4038: 0 +Line 4039: 1 +Line 4040: 1 +Line 4041: 0 +Line 4042: 0 +Line 4043: 0 +Line 4044: 0 +Line 4045: 1 +Line 4046: 1 +Line 4047: 1 +Line 4048: 0 +Line 4049: 0 +Line 4050: 0 +Line 4051: 0 +Line 4052: 0 +Line 4053: 0 +Line 4054: 0 +Line 4055: 0 +Line 4056: 0 +Line 4057: 0 +Line 4058: 0 +Line 4059: 0 +Line 4060: 0 +Line 4061: 0 +Line 4062: 0 +Line 4063: 0 +Line 4064: 0 +Line 4065: 0 +Line 4066: 1 +Line 4067: 0 +Line 4068: 1 +Line 4069: 0 +Line 4070: 0 +Line 4071: 0 +Line 4072: 0 +Line 4073: 1 +Line 4074: 1 +Line 4075: 0 +Line 4076: 0 +Line 4077: 0 +Line 4078: 1 +Line 4079: 0 +Line 4080: 0 +Line 4081: 0 +Line 4082: 0 +Line 4083: 0 +Line 4084: 0 +Line 4085: 0 +Line 4086: 0 +Line 4087: 0 +Line 4088: 0 +Line 4089: 0 +Line 4090: 0 +Line 4091: 0 +Line 4092: 0 +Line 4093: 0 +Line 4094: 0 +Line 4095: 0 +Line 4096: 0 +Line 4097: 0 +Line 4098: 1 +Line 4099: 0 +Line 4100: 0 +Line 4101: 1 +Line 4102: 1 +Line 4103: 1 +Line 4104: 0 +Line 4105: 0 +Line 4106: 1 +Line 4107: 1 +Line 4108: 1 +Line 4109: 0 +Line 4110: 1 +Line 4111: 1 +Line 4112: 0 +Line 4113: 0 +Line 4114: 0 +Line 4115: 0 +Line 4116: 0 +Line 4117: 0 +Line 4118: 0 +Line 4119: 0 +Line 4120: 0 +Line 4121: 0 +Line 4122: 0 +Line 4123: 0 +Line 4124: 0 +Line 4125: 0 +Line 4126: 0 +Line 4127: 0 +Line 4128: 0 +Line 4129: 0 +Line 4130: 1 +Line 4131: 0 +Line 4132: 0 +Line 4133: 1 +Line 4134: 1 +Line 4135: 0 +Line 4136: 0 +Line 4137: 0 +Line 4138: 0 +Line 4139: 1 +Line 4140: 0 +Line 4141: 0 +Line 4142: 1 +Line 4143: 0 +Line 4144: 0 +Line 4145: 0 +Line 4146: 0 +Line 4147: 0 +Line 4148: 0 +Line 4149: 0 +Line 4150: 0 +Line 4151: 0 +Line 4152: 0 +Line 4153: 0 +Line 4154: 0 +Line 4155: 0 +Line 4156: 0 +Line 4157: 0 +Line 4158: 0 +Line 4159: 0 +Line 4160: 0 +Line 4161: 0 +Line 4162: 1 +Line 4163: 0 +Line 4164: 0 +Line 4165: 1 +Line 4166: 0 +Line 4167: 0 +Line 4168: 1 +Line 4169: 1 +Line 4170: 1 +Line 4171: 0 +Line 4172: 1 +Line 4173: 0 +Line 4174: 0 +Line 4175: 0 +Line 4176: 0 +Line 4177: 0 +Line 4178: 0 +Line 4179: 0 +Line 4180: 0 +Line 4181: 0 +Line 4182: 0 +Line 4183: 0 +Line 4184: 0 +Line 4185: 0 +Line 4186: 0 +Line 4187: 0 +Line 4188: 0 +Line 4189: 0 +Line 4190: 0 +Line 4191: 0 +Line 4192: 0 +Line 4193: 0 +Line 4194: 1 +Line 4195: 0 +Line 4196: 0 +Line 4197: 0 +Line 4198: 1 +Line 4199: 1 +Line 4200: 1 +Line 4201: 0 +Line 4202: 1 +Line 4203: 1 +Line 4204: 1 +Line 4205: 1 +Line 4206: 0 +Line 4207: 1 +Line 4208: 0 +Line 4209: 0 +Line 4210: 0 +Line 4211: 0 +Line 4212: 0 +Line 4213: 0 +Line 4214: 0 +Line 4215: 0 +Line 4216: 0 +Line 4217: 0 +Line 4218: 0 +Line 4219: 0 +Line 4220: 0 +Line 4221: 0 +Line 4222: 0 +Line 4223: 0 +Line 4224: 0 +Line 4225: 0 +Line 4226: 1 +Line 4227: 0 +Line 4228: 0 +Line 4229: 0 +Line 4230: 1 +Line 4231: 0 +Line 4232: 1 +Line 4233: 0 +Line 4234: 0 +Line 4235: 1 +Line 4236: 0 +Line 4237: 0 +Line 4238: 1 +Line 4239: 0 +Line 4240: 0 +Line 4241: 0 +Line 4242: 0 +Line 4243: 0 +Line 4244: 0 +Line 4245: 0 +Line 4246: 0 +Line 4247: 0 +Line 4248: 0 +Line 4249: 0 +Line 4250: 0 +Line 4251: 0 +Line 4252: 0 +Line 4253: 0 +Line 4254: 0 +Line 4255: 0 +Line 4256: 0 +Line 4257: 0 +Line 4258: 1 +Line 4259: 0 +Line 4260: 0 +Line 4261: 0 +Line 4262: 0 +Line 4263: 1 +Line 4264: 0 +Line 4265: 1 +Line 4266: 1 +Line 4267: 0 +Line 4268: 0 +Line 4269: 1 +Line 4270: 1 +Line 4271: 1 +Line 4272: 0 +Line 4273: 0 +Line 4274: 0 +Line 4275: 0 +Line 4276: 0 +Line 4277: 0 +Line 4278: 0 +Line 4279: 0 +Line 4280: 0 +Line 4281: 0 +Line 4282: 0 +Line 4283: 0 +Line 4284: 0 +Line 4285: 0 +Line 4286: 0 +Line 4287: 0 +Line 4288: 0 +Line 4289: 0 +Line 4290: 1 +Line 4291: 0 +Line 4292: 0 +Line 4293: 0 +Line 4294: 0 +Line 4295: 0 +Line 4296: 0 +Line 4297: 0 +Line 4298: 1 +Line 4299: 1 +Line 4300: 1 +Line 4301: 1 +Line 4302: 0 +Line 4303: 1 +Line 4304: 0 +Line 4305: 0 +Line 4306: 0 +Line 4307: 0 +Line 4308: 0 +Line 4309: 0 +Line 4310: 0 +Line 4311: 0 +Line 4312: 0 +Line 4313: 0 +Line 4314: 0 +Line 4315: 0 +Line 4316: 0 +Line 4317: 0 +Line 4318: 0 +Line 4319: 0 +Line 4320: 0 +Line 4321: 0 +Line 4322: 0 +Line 4323: 1 +Line 4324: 1 +Line 4325: 1 +Line 4326: 1 +Line 4327: 1 +Line 4328: 0 +Line 4329: 0 +Line 4330: 0 +Line 4331: 1 +Line 4332: 0 +Line 4333: 1 +Line 4334: 0 +Line 4335: 0 +Line 4336: 0 +Line 4337: 0 +Line 4338: 0 +Line 4339: 0 +Line 4340: 0 +Line 4341: 0 +Line 4342: 0 +Line 4343: 0 +Line 4344: 0 +Line 4345: 0 +Line 4346: 0 +Line 4347: 0 +Line 4348: 0 +Line 4349: 0 +Line 4350: 0 +Line 4351: 0 +Line 4352: 0 +Line 4353: 0 +Line 4354: 0 +Line 4355: 1 +Line 4356: 1 +Line 4357: 1 +Line 4358: 0 +Line 4359: 1 +Line 4360: 1 +Line 4361: 1 +Line 4362: 1 +Line 4363: 0 +Line 4364: 1 +Line 4365: 1 +Line 4366: 0 +Line 4367: 1 +Line 4368: 0 +Line 4369: 0 +Line 4370: 0 +Line 4371: 0 +Line 4372: 0 +Line 4373: 0 +Line 4374: 0 +Line 4375: 0 +Line 4376: 0 +Line 4377: 0 +Line 4378: 0 +Line 4379: 0 +Line 4380: 0 +Line 4381: 0 +Line 4382: 0 +Line 4383: 0 +Line 4384: 0 +Line 4385: 0 +Line 4386: 0 +Line 4387: 1 +Line 4388: 1 +Line 4389: 1 +Line 4390: 0 +Line 4391: 0 +Line 4392: 1 +Line 4393: 1 +Line 4394: 0 +Line 4395: 0 +Line 4396: 1 +Line 4397: 0 +Line 4398: 0 +Line 4399: 0 +Line 4400: 0 +Line 4401: 0 +Line 4402: 0 +Line 4403: 0 +Line 4404: 0 +Line 4405: 0 +Line 4406: 0 +Line 4407: 0 +Line 4408: 0 +Line 4409: 0 +Line 4410: 0 +Line 4411: 0 +Line 4412: 0 +Line 4413: 0 +Line 4414: 0 +Line 4415: 0 +Line 4416: 0 +Line 4417: 0 +Line 4418: 0 +Line 4419: 1 +Line 4420: 1 +Line 4421: 0 +Line 4422: 1 +Line 4423: 1 +Line 4424: 1 +Line 4425: 0 +Line 4426: 1 +Line 4427: 0 +Line 4428: 0 +Line 4429: 1 +Line 4430: 1 +Line 4431: 0 +Line 4432: 0 +Line 4433: 0 +Line 4434: 0 +Line 4435: 0 +Line 4436: 0 +Line 4437: 0 +Line 4438: 0 +Line 4439: 0 +Line 4440: 0 +Line 4441: 0 +Line 4442: 0 +Line 4443: 0 +Line 4444: 0 +Line 4445: 0 +Line 4446: 0 +Line 4447: 0 +Line 4448: 0 +Line 4449: 0 +Line 4450: 0 +Line 4451: 1 +Line 4452: 1 +Line 4453: 0 +Line 4454: 1 +Line 4455: 0 +Line 4456: 1 +Line 4457: 0 +Line 4458: 0 +Line 4459: 0 +Line 4460: 0 +Line 4461: 1 +Line 4462: 1 +Line 4463: 1 +Line 4464: 0 +Line 4465: 0 +Line 4466: 0 +Line 4467: 0 +Line 4468: 0 +Line 4469: 0 +Line 4470: 0 +Line 4471: 0 +Line 4472: 0 +Line 4473: 0 +Line 4474: 0 +Line 4475: 0 +Line 4476: 0 +Line 4477: 0 +Line 4478: 0 +Line 4479: 0 +Line 4480: 0 +Line 4481: 0 +Line 4482: 0 +Line 4483: 1 +Line 4484: 1 +Line 4485: 0 +Line 4486: 0 +Line 4487: 1 +Line 4488: 0 +Line 4489: 1 +Line 4490: 1 +Line 4491: 0 +Line 4492: 1 +Line 4493: 1 +Line 4494: 0 +Line 4495: 0 +Line 4496: 0 +Line 4497: 0 +Line 4498: 0 +Line 4499: 0 +Line 4500: 0 +Line 4501: 0 +Line 4502: 0 +Line 4503: 0 +Line 4504: 0 +Line 4505: 0 +Line 4506: 0 +Line 4507: 0 +Line 4508: 0 +Line 4509: 0 +Line 4510: 0 +Line 4511: 0 +Line 4512: 0 +Line 4513: 0 +Line 4514: 0 +Line 4515: 1 +Line 4516: 1 +Line 4517: 0 +Line 4518: 0 +Line 4519: 0 +Line 4520: 0 +Line 4521: 1 +Line 4522: 0 +Line 4523: 1 +Line 4524: 0 +Line 4525: 1 +Line 4526: 1 +Line 4527: 0 +Line 4528: 0 +Line 4529: 0 +Line 4530: 0 +Line 4531: 0 +Line 4532: 0 +Line 4533: 0 +Line 4534: 0 +Line 4535: 0 +Line 4536: 0 +Line 4537: 0 +Line 4538: 0 +Line 4539: 0 +Line 4540: 0 +Line 4541: 0 +Line 4542: 0 +Line 4543: 0 +Line 4544: 0 +Line 4545: 0 +Line 4546: 0 +Line 4547: 1 +Line 4548: 0 +Line 4549: 1 +Line 4550: 1 +Line 4551: 1 +Line 4552: 0 +Line 4553: 1 +Line 4554: 0 +Line 4555: 0 +Line 4556: 0 +Line 4557: 0 +Line 4558: 1 +Line 4559: 1 +Line 4560: 0 +Line 4561: 0 +Line 4562: 0 +Line 4563: 0 +Line 4564: 0 +Line 4565: 0 +Line 4566: 0 +Line 4567: 0 +Line 4568: 0 +Line 4569: 0 +Line 4570: 0 +Line 4571: 0 +Line 4572: 0 +Line 4573: 0 +Line 4574: 0 +Line 4575: 0 +Line 4576: 0 +Line 4577: 0 +Line 4578: 0 +Line 4579: 1 +Line 4580: 0 +Line 4581: 1 +Line 4582: 1 +Line 4583: 0 +Line 4584: 0 +Line 4585: 0 +Line 4586: 1 +Line 4587: 1 +Line 4588: 0 +Line 4589: 1 +Line 4590: 1 +Line 4591: 0 +Line 4592: 0 +Line 4593: 0 +Line 4594: 0 +Line 4595: 0 +Line 4596: 0 +Line 4597: 0 +Line 4598: 0 +Line 4599: 0 +Line 4600: 0 +Line 4601: 0 +Line 4602: 0 +Line 4603: 0 +Line 4604: 0 +Line 4605: 0 +Line 4606: 0 +Line 4607: 0 +Line 4608: 0 +Line 4609: 0 +Line 4610: 0 +Line 4611: 1 +Line 4612: 0 +Line 4613: 1 +Line 4614: 0 +Line 4615: 1 +Line 4616: 0 +Line 4617: 0 +Line 4618: 1 +Line 4619: 0 +Line 4620: 1 +Line 4621: 1 +Line 4622: 1 +Line 4623: 0 +Line 4624: 0 +Line 4625: 0 +Line 4626: 0 +Line 4627: 0 +Line 4628: 0 +Line 4629: 0 +Line 4630: 0 +Line 4631: 0 +Line 4632: 0 +Line 4633: 0 +Line 4634: 0 +Line 4635: 0 +Line 4636: 0 +Line 4637: 0 +Line 4638: 0 +Line 4639: 0 +Line 4640: 0 +Line 4641: 0 +Line 4642: 0 +Line 4643: 1 +Line 4644: 0 +Line 4645: 1 +Line 4646: 0 +Line 4647: 0 +Line 4648: 0 +Line 4649: 0 +Line 4650: 1 +Line 4651: 0 +Line 4652: 1 +Line 4653: 0 +Line 4654: 1 +Line 4655: 1 +Line 4656: 0 +Line 4657: 0 +Line 4658: 0 +Line 4659: 0 +Line 4660: 0 +Line 4661: 0 +Line 4662: 0 +Line 4663: 0 +Line 4664: 0 +Line 4665: 0 +Line 4666: 0 +Line 4667: 0 +Line 4668: 0 +Line 4669: 0 +Line 4670: 0 +Line 4671: 0 +Line 4672: 1 +Line 4673: 1 +Line 4674: 1 +Line 4675: 1 +Line 4676: 1 +Line 4677: 1 +Line 4678: 1 +Line 4679: 0 +Line 4680: 0 +Line 4681: 1 +Line 4682: 1 +Line 4683: 0 +Line 4684: 0 +Line 4685: 1 +Line 4686: 1 +Line 4687: 1 +Line 4688: 0 +Line 4689: 0 +Line 4690: 0 +Line 4691: 0 +Line 4692: 0 +Line 4693: 0 +Line 4694: 0 +Line 4695: 0 +Line 4696: 0 +Line 4697: 0 +Line 4698: 0 +Line 4699: 0 +Line 4700: 0 +Line 4701: 0 +Line 4702: 0 +Line 4703: 0 +Line 4704: 1 +Line 4705: 1 +Line 4706: 1 +Line 4707: 1 +Line 4708: 0 +Line 4709: 1 +Line 4710: 0 +Line 4711: 0 +Line 4712: 1 +Line 4713: 1 +Line 4714: 0 +Line 4715: 1 +Line 4716: 1 +Line 4717: 0 +Line 4718: 0 +Line 4719: 1 +Line 4720: 0 +Line 4721: 0 +Line 4722: 0 +Line 4723: 0 +Line 4724: 0 +Line 4725: 0 +Line 4726: 0 +Line 4727: 0 +Line 4728: 0 +Line 4729: 0 +Line 4730: 0 +Line 4731: 0 +Line 4732: 0 +Line 4733: 0 +Line 4734: 0 +Line 4735: 0 +Line 4736: 1 +Line 4737: 1 +Line 4738: 0 +Line 4739: 1 +Line 4740: 1 +Line 4741: 1 +Line 4742: 0 +Line 4743: 0 +Line 4744: 1 +Line 4745: 1 +Line 4746: 0 +Line 4747: 1 +Line 4748: 1 +Line 4749: 0 +Line 4750: 0 +Line 4751: 0 +Line 4752: 0 +Line 4753: 0 +Line 4754: 0 +Line 4755: 0 +Line 4756: 0 +Line 4757: 0 +Line 4758: 0 +Line 4759: 0 +Line 4760: 0 +Line 4761: 0 +Line 4762: 0 +Line 4763: 0 +Line 4764: 0 +Line 4765: 0 +Line 4766: 0 +Line 4767: 0 +Line 4768: 1 +Line 4769: 1 +Line 4770: 0 +Line 4771: 0 +Line 4772: 0 +Line 4773: 1 +Line 4774: 0 +Line 4775: 0 +Line 4776: 1 +Line 4777: 1 +Line 4778: 0 +Line 4779: 1 +Line 4780: 1 +Line 4781: 0 +Line 4782: 0 +Line 4783: 0 +Line 4784: 0 +Line 4785: 0 +Line 4786: 0 +Line 4787: 0 +Line 4788: 0 +Line 4789: 0 +Line 4790: 0 +Line 4791: 0 +Line 4792: 0 +Line 4793: 0 +Line 4794: 0 +Line 4795: 0 +Line 4796: 0 +Line 4797: 0 +Line 4798: 0 +Line 4799: 0 +Line 4800: 1 +Line 4801: 0 +Line 4802: 1 +Line 4803: 1 +Line 4804: 1 +Line 4805: 0 +Line 4806: 1 +Line 4807: 1 +Line 4808: 0 +Line 4809: 1 +Line 4810: 0 +Line 4811: 0 +Line 4812: 1 +Line 4813: 0 +Line 4814: 1 +Line 4815: 0 +Line 4816: 0 +Line 4817: 0 +Line 4818: 0 +Line 4819: 0 +Line 4820: 0 +Line 4821: 0 +Line 4822: 0 +Line 4823: 0 +Line 4824: 0 +Line 4825: 0 +Line 4826: 0 +Line 4827: 0 +Line 4828: 0 +Line 4829: 0 +Line 4830: 0 +Line 4831: 0 +Line 4832: 1 +Line 4833: 0 +Line 4834: 1 +Line 4835: 1 +Line 4836: 1 +Line 4837: 0 +Line 4838: 0 +Line 4839: 1 +Line 4840: 1 +Line 4841: 1 +Line 4842: 0 +Line 4843: 0 +Line 4844: 1 +Line 4845: 0 +Line 4846: 0 +Line 4847: 1 +Line 4848: 0 +Line 4849: 0 +Line 4850: 0 +Line 4851: 0 +Line 4852: 0 +Line 4853: 0 +Line 4854: 0 +Line 4855: 0 +Line 4856: 0 +Line 4857: 0 +Line 4858: 0 +Line 4859: 0 +Line 4860: 0 +Line 4861: 0 +Line 4862: 0 +Line 4863: 0 +Line 4864: 1 +Line 4865: 0 +Line 4866: 1 +Line 4867: 1 +Line 4868: 1 +Line 4869: 0 +Line 4870: 0 +Line 4871: 1 +Line 4872: 1 +Line 4873: 0 +Line 4874: 1 +Line 4875: 1 +Line 4876: 0 +Line 4877: 0 +Line 4878: 0 +Line 4879: 1 +Line 4880: 0 +Line 4881: 0 +Line 4882: 0 +Line 4883: 0 +Line 4884: 0 +Line 4885: 0 +Line 4886: 0 +Line 4887: 0 +Line 4888: 0 +Line 4889: 0 +Line 4890: 0 +Line 4891: 0 +Line 4892: 0 +Line 4893: 0 +Line 4894: 0 +Line 4895: 0 +Line 4896: 1 +Line 4897: 0 +Line 4898: 1 +Line 4899: 1 +Line 4900: 1 +Line 4901: 0 +Line 4902: 0 +Line 4903: 1 +Line 4904: 1 +Line 4905: 0 +Line 4906: 1 +Line 4907: 1 +Line 4908: 0 +Line 4909: 0 +Line 4910: 0 +Line 4911: 1 +Line 4912: 0 +Line 4913: 0 +Line 4914: 0 +Line 4915: 0 +Line 4916: 0 +Line 4917: 0 +Line 4918: 0 +Line 4919: 0 +Line 4920: 0 +Line 4921: 0 +Line 4922: 0 +Line 4923: 0 +Line 4924: 0 +Line 4925: 0 +Line 4926: 0 +Line 4927: 0 +Line 4928: 1 +Line 4929: 0 +Line 4930: 1 +Line 4931: 1 +Line 4932: 1 +Line 4933: 0 +Line 4934: 0 +Line 4935: 1 +Line 4936: 1 +Line 4937: 0 +Line 4938: 1 +Line 4939: 1 +Line 4940: 0 +Line 4941: 0 +Line 4942: 0 +Line 4943: 1 +Line 4944: 0 +Line 4945: 0 +Line 4946: 0 +Line 4947: 0 +Line 4948: 0 +Line 4949: 0 +Line 4950: 0 +Line 4951: 0 +Line 4952: 0 +Line 4953: 0 +Line 4954: 0 +Line 4955: 0 +Line 4956: 0 +Line 4957: 0 +Line 4958: 0 +Line 4959: 0 +Line 4960: 1 +Line 4961: 0 +Line 4962: 1 +Line 4963: 1 +Line 4964: 1 +Line 4965: 0 +Line 4966: 0 +Line 4967: 1 +Line 4968: 1 +Line 4969: 0 +Line 4970: 1 +Line 4971: 1 +Line 4972: 0 +Line 4973: 0 +Line 4974: 0 +Line 4975: 1 +Line 4976: 0 +Line 4977: 0 +Line 4978: 0 +Line 4979: 0 +Line 4980: 0 +Line 4981: 0 +Line 4982: 0 +Line 4983: 0 +Line 4984: 0 +Line 4985: 0 +Line 4986: 0 +Line 4987: 0 +Line 4988: 0 +Line 4989: 0 +Line 4990: 0 +Line 4991: 0 +Line 4992: 1 +Line 4993: 0 +Line 4994: 1 +Line 4995: 1 +Line 4996: 1 +Line 4997: 0 +Line 4998: 0 +Line 4999: 1 +Line 5000: 1 +Line 5001: 0 +Line 5002: 1 +Line 5003: 1 +Line 5004: 0 +Line 5005: 0 +Line 5006: 0 +Line 5007: 1 +Line 5008: 0 +Line 5009: 0 +Line 5010: 0 +Line 5011: 0 +Line 5012: 0 +Line 5013: 0 +Line 5014: 0 +Line 5015: 0 +Line 5016: 0 +Line 5017: 0 +Line 5018: 0 +Line 5019: 0 +Line 5020: 0 +Line 5021: 0 +Line 5022: 0 +Line 5023: 0 +Line 5024: 1 +Line 5025: 0 +Line 5026: 1 +Line 5027: 1 +Line 5028: 1 +Line 5029: 0 +Line 5030: 0 +Line 5031: 1 +Line 5032: 1 +Line 5033: 0 +Line 5034: 1 +Line 5035: 1 +Line 5036: 0 +Line 5037: 0 +Line 5038: 0 +Line 5039: 0 +Line 5040: 0 +Line 5041: 0 +Line 5042: 0 +Line 5043: 0 +Line 5044: 0 +Line 5045: 0 +Line 5046: 0 +Line 5047: 0 +Line 5048: 0 +Line 5049: 0 +Line 5050: 0 +Line 5051: 0 +Line 5052: 0 +Line 5053: 0 +Line 5054: 0 +Line 5055: 0 +Line 5056: 1 +Line 5057: 0 +Line 5058: 1 +Line 5059: 1 +Line 5060: 1 +Line 5061: 0 +Line 5062: 0 +Line 5063: 1 +Line 5064: 1 +Line 5065: 0 +Line 5066: 1 +Line 5067: 1 +Line 5068: 0 +Line 5069: 0 +Line 5070: 0 +Line 5071: 0 +Line 5072: 0 +Line 5073: 0 +Line 5074: 0 +Line 5075: 0 +Line 5076: 0 +Line 5077: 0 +Line 5078: 0 +Line 5079: 0 +Line 5080: 0 +Line 5081: 0 +Line 5082: 0 +Line 5083: 0 +Line 5084: 0 +Line 5085: 0 +Line 5086: 0 +Line 5087: 0 +Line 5088: 1 +Line 5089: 0 +Line 5090: 1 +Line 5091: 1 +Line 5092: 1 +Line 5093: 0 +Line 5094: 0 +Line 5095: 1 +Line 5096: 1 +Line 5097: 0 +Line 5098: 1 +Line 5099: 1 +Line 5100: 0 +Line 5101: 0 +Line 5102: 0 +Line 5103: 0 +Line 5104: 0 +Line 5105: 0 +Line 5106: 0 +Line 5107: 0 +Line 5108: 0 +Line 5109: 0 +Line 5110: 0 +Line 5111: 0 +Line 5112: 0 +Line 5113: 0 +Line 5114: 0 +Line 5115: 0 +Line 5116: 0 +Line 5117: 0 +Line 5118: 0 +Line 5119: 0 +Line 5120: 1 +Line 5121: 0 +Line 5122: 1 +Line 5123: 1 +Line 5124: 1 +Line 5125: 0 +Line 5126: 0 +Line 5127: 1 +Line 5128: 1 +Line 5129: 0 +Line 5130: 1 +Line 5131: 1 +Line 5132: 0 +Line 5133: 0 +Line 5134: 0 +Line 5135: 1 +Line 5136: 0 +Line 5137: 0 +Line 5138: 0 +Line 5139: 0 +Line 5140: 0 +Line 5141: 0 +Line 5142: 0 +Line 5143: 0 +Line 5144: 0 +Line 5145: 0 +Line 5146: 0 +Line 5147: 0 +Line 5148: 0 +Line 5149: 0 +Line 5150: 0 +Line 5151: 0 +Line 5152: 1 +Line 5153: 0 +Line 5154: 1 +Line 5155: 1 +Line 5156: 1 +Line 5157: 0 +Line 5158: 0 +Line 5159: 1 +Line 5160: 1 +Line 5161: 0 +Line 5162: 1 +Line 5163: 1 +Line 5164: 0 +Line 5165: 0 +Line 5166: 0 +Line 5167: 1 +Line 5168: 0 +Line 5169: 0 +Line 5170: 0 +Line 5171: 0 +Line 5172: 0 +Line 5173: 0 +Line 5174: 0 +Line 5175: 0 +Line 5176: 0 +Line 5177: 0 +Line 5178: 0 +Line 5179: 0 +Line 5180: 0 +Line 5181: 0 +Line 5182: 0 +Line 5183: 0 +Line 5184: 1 +Line 5185: 0 +Line 5186: 1 +Line 5187: 1 +Line 5188: 1 +Line 5189: 0 +Line 5190: 0 +Line 5191: 1 +Line 5192: 1 +Line 5193: 0 +Line 5194: 1 +Line 5195: 1 +Line 5196: 0 +Line 5197: 0 +Line 5198: 0 +Line 5199: 1 +Line 5200: 0 +Line 5201: 0 +Line 5202: 0 +Line 5203: 0 +Line 5204: 0 +Line 5205: 0 +Line 5206: 0 +Line 5207: 0 +Line 5208: 0 +Line 5209: 0 +Line 5210: 0 +Line 5211: 0 +Line 5212: 0 +Line 5213: 0 +Line 5214: 0 +Line 5215: 0 +Line 5216: 1 +Line 5217: 0 +Line 5218: 1 +Line 5219: 1 +Line 5220: 1 +Line 5221: 0 +Line 5222: 0 +Line 5223: 1 +Line 5224: 1 +Line 5225: 0 +Line 5226: 1 +Line 5227: 1 +Line 5228: 0 +Line 5229: 0 +Line 5230: 0 +Line 5231: 1 +Line 5232: 0 +Line 5233: 0 +Line 5234: 0 +Line 5235: 0 +Line 5236: 0 +Line 5237: 0 +Line 5238: 0 +Line 5239: 0 +Line 5240: 0 +Line 5241: 0 +Line 5242: 0 +Line 5243: 0 +Line 5244: 0 +Line 5245: 0 +Line 5246: 0 +Line 5247: 0 +Line 5248: 1 +Line 5249: 0 +Line 5250: 1 +Line 5251: 1 +Line 5252: 1 +Line 5253: 0 +Line 5254: 0 +Line 5255: 1 +Line 5256: 1 +Line 5257: 0 +Line 5258: 1 +Line 5259: 1 +Line 5260: 0 +Line 5261: 0 +Line 5262: 0 +Line 5263: 1 +Line 5264: 0 +Line 5265: 0 +Line 5266: 0 +Line 5267: 0 +Line 5268: 0 +Line 5269: 0 +Line 5270: 0 +Line 5271: 0 +Line 5272: 0 +Line 5273: 0 +Line 5274: 0 +Line 5275: 0 +Line 5276: 0 +Line 5277: 0 +Line 5278: 0 +Line 5279: 0 +Line 5280: 1 +Line 5281: 0 +Line 5282: 1 +Line 5283: 1 +Line 5284: 1 +Line 5285: 0 +Line 5286: 0 +Line 5287: 1 +Line 5288: 1 +Line 5289: 1 +Line 5290: 0 +Line 5291: 0 +Line 5292: 1 +Line 5293: 0 +Line 5294: 0 +Line 5295: 1 +Line 5296: 0 +Line 5297: 0 +Line 5298: 0 +Line 5299: 0 +Line 5300: 0 +Line 5301: 0 +Line 5302: 0 +Line 5303: 0 +Line 5304: 0 +Line 5305: 0 +Line 5306: 0 +Line 5307: 0 +Line 5308: 0 +Line 5309: 0 +Line 5310: 0 +Line 5311: 0 +Line 5312: 1 +Line 5313: 0 +Line 5314: 1 +Line 5315: 1 +Line 5316: 1 +Line 5317: 0 +Line 5318: 1 +Line 5319: 1 +Line 5320: 0 +Line 5321: 1 +Line 5322: 0 +Line 5323: 0 +Line 5324: 1 +Line 5325: 0 +Line 5326: 1 +Line 5327: 0 +Line 5328: 0 +Line 5329: 0 +Line 5330: 0 +Line 5331: 0 +Line 5332: 0 +Line 5333: 0 +Line 5334: 0 +Line 5335: 0 +Line 5336: 0 +Line 5337: 0 +Line 5338: 0 +Line 5339: 0 +Line 5340: 0 +Line 5341: 0 +Line 5342: 0 +Line 5343: 0 +Line 5344: 1 +Line 5345: 1 +Line 5346: 0 +Line 5347: 0 +Line 5348: 0 +Line 5349: 1 +Line 5350: 0 +Line 5351: 0 +Line 5352: 1 +Line 5353: 1 +Line 5354: 0 +Line 5355: 1 +Line 5356: 1 +Line 5357: 0 +Line 5358: 0 +Line 5359: 0 +Line 5360: 0 +Line 5361: 0 +Line 5362: 0 +Line 5363: 0 +Line 5364: 0 +Line 5365: 0 +Line 5366: 0 +Line 5367: 0 +Line 5368: 0 +Line 5369: 0 +Line 5370: 0 +Line 5371: 0 +Line 5372: 0 +Line 5373: 0 +Line 5374: 0 +Line 5375: 0 +Line 5376: 1 +Line 5377: 1 +Line 5378: 0 +Line 5379: 1 +Line 5380: 1 +Line 5381: 1 +Line 5382: 0 +Line 5383: 0 +Line 5384: 1 +Line 5385: 1 +Line 5386: 0 +Line 5387: 1 +Line 5388: 1 +Line 5389: 0 +Line 5390: 0 +Line 5391: 0 +Line 5392: 0 +Line 5393: 0 +Line 5394: 0 +Line 5395: 0 +Line 5396: 0 +Line 5397: 0 +Line 5398: 0 +Line 5399: 0 +Line 5400: 0 +Line 5401: 0 +Line 5402: 0 +Line 5403: 0 +Line 5404: 0 +Line 5405: 0 +Line 5406: 0 +Line 5407: 0 +Line 5408: 1 +Line 5409: 1 +Line 5410: 1 +Line 5411: 1 +Line 5412: 0 +Line 5413: 1 +Line 5414: 0 +Line 5415: 0 +Line 5416: 1 +Line 5417: 1 +Line 5418: 0 +Line 5419: 1 +Line 5420: 1 +Line 5421: 0 +Line 5422: 0 +Line 5423: 1 +Line 5424: 0 +Line 5425: 0 +Line 5426: 0 +Line 5427: 0 +Line 5428: 0 +Line 5429: 0 +Line 5430: 0 +Line 5431: 0 +Line 5432: 0 +Line 5433: 0 +Line 5434: 0 +Line 5435: 0 +Line 5436: 0 +Line 5437: 0 +Line 5438: 0 +Line 5439: 0 +Line 5440: 1 +Line 5441: 1 +Line 5442: 1 +Line 5443: 1 +Line 5444: 1 +Line 5445: 1 +Line 5446: 1 +Line 5447: 0 +Line 5448: 0 +Line 5449: 1 +Line 5450: 1 +Line 5451: 0 +Line 5452: 0 +Line 5453: 1 +Line 5454: 1 +Line 5455: 1 +Line 5456: 0 +Line 5457: 0 +Line 5458: 0 +Line 5459: 0 +Line 5460: 0 +Line 5461: 0 +Line 5462: 0 +Line 5463: 0 +Line 5464: 0 +Line 5465: 0 +Line 5466: 0 +Line 5467: 0 +Line 5468: 0 +Line 5469: 0 +Line 5470: 0 +Line 5471: 0 +Line 5472: 0 +Line 5473: 0 +Line 5474: 0 +Line 5475: 0 +Line 5476: 0 +Line 5477: 0 +Line 5478: 0 +Line 5479: 0 +Line 5480: 0 +Line 5481: 0 +Line 5482: 0 +Line 5483: 0 +Line 5484: 0 +Line 5485: 0 +Line 5486: 0 +Line 5487: 0 +Line 5488: 0 +Line 5489: 0 +Line 5490: 0 +Line 5491: 0 +Line 5492: 0 +Line 5493: 0 +Line 5494: 0 +Line 5495: 0 +Line 5496: 0 +Line 5497: 0 +Line 5498: 0 +Line 5499: 0 +Line 5500: 0 +Line 5501: 0 +Line 5502: 0 +Line 5503: 0 +Line 5504: 0 +Line 5505: 0 +Line 5506: 0 +Line 5507: 0 +Line 5508: 0 +Line 5509: 0 +Line 5510: 0 +Line 5511: 0 +Line 5512: 0 +Line 5513: 0 +Line 5514: 0 +Line 5515: 0 +Line 5516: 0 +Line 5517: 1 +Line 5518: 0 +Line 5519: 1 +Line 5520: 1 +Line 5521: 1 +Line 5522: 1 +Line 5523: 1 +Line 5524: 1 +Line 5525: 1 +Line 5526: 1 +Line 5527: 1 +Line 5528: 1 +Line 5529: 1 +Line 5530: 1 +Line 5531: 1 +Line 5532: 0 +Line 5533: 0 +Line 5534: 0 +Line 5535: 1 +Line 5536: 0 +Line 5537: 0 +Line 5538: 0 +Line 5539: 0 +Line 5540: 0 +Line 5541: 0 +Line 5542: 0 +Line 5543: 0 +Line 5544: 0 +Line 5545: 0 +Line 5546: 0 +Line 5547: 1 +Line 5548: 0 +Line 5549: 1 +Line 5550: 1 +Line 5551: 1 +Line 5552: 1 +Line 5553: 1 +Line 5554: 1 +Line 5555: 1 +Line 5556: 1 +Line 5557: 1 +Line 5558: 1 +Line 5559: 1 +Line 5560: 1 +Line 5561: 1 +Line 5562: 1 +Line 5563: 0 +Line 5564: 0 +Line 5565: 0 +Line 5566: 0 +Line 5567: 1 +Line 5568: 0 +Line 5569: 0 +Line 5570: 0 +Line 5571: 0 +Line 5572: 0 +Line 5573: 0 +Line 5574: 0 +Line 5575: 0 +Line 5576: 0 +Line 5577: 0 +Line 5578: 1 +Line 5579: 1 +Line 5580: 0 +Line 5581: 1 +Line 5582: 0 +Line 5583: 0 +Line 5584: 1 +Line 5585: 1 +Line 5586: 1 +Line 5587: 1 +Line 5588: 1 +Line 5589: 1 +Line 5590: 1 +Line 5591: 1 +Line 5592: 1 +Line 5593: 1 +Line 5594: 0 +Line 5595: 1 +Line 5596: 0 +Line 5597: 0 +Line 5598: 0 +Line 5599: 1 +Line 5600: 0 +Line 5601: 0 +Line 5602: 0 +Line 5603: 0 +Line 5604: 0 +Line 5605: 0 +Line 5606: 0 +Line 5607: 0 +Line 5608: 0 +Line 5609: 1 +Line 5610: 0 +Line 5611: 1 +Line 5612: 1 +Line 5613: 1 +Line 5614: 0 +Line 5615: 1 +Line 5616: 1 +Line 5617: 1 +Line 5618: 1 +Line 5619: 1 +Line 5620: 1 +Line 5621: 1 +Line 5622: 1 +Line 5623: 1 +Line 5624: 1 +Line 5625: 1 +Line 5626: 0 +Line 5627: 0 +Line 5628: 0 +Line 5629: 0 +Line 5630: 1 +Line 5631: 0 +Line 5632: 0 +Line 5633: 0 +Line 5634: 0 +Line 5635: 0 +Line 5636: 0 +Line 5637: 0 +Line 5638: 0 +Line 5639: 0 +Line 5640: 1 +Line 5641: 0 +Line 5642: 0 +Line 5643: 1 +Line 5644: 0 +Line 5645: 0 +Line 5646: 1 +Line 5647: 0 +Line 5648: 1 +Line 5649: 1 +Line 5650: 1 +Line 5651: 1 +Line 5652: 1 +Line 5653: 1 +Line 5654: 1 +Line 5655: 1 +Line 5656: 1 +Line 5657: 0 +Line 5658: 1 +Line 5659: 1 +Line 5660: 0 +Line 5661: 0 +Line 5662: 1 +Line 5663: 0 +Line 5664: 0 +Line 5665: 0 +Line 5666: 0 +Line 5667: 0 +Line 5668: 0 +Line 5669: 0 +Line 5670: 0 +Line 5671: 0 +Line 5672: 1 +Line 5673: 1 +Line 5674: 0 +Line 5675: 1 +Line 5676: 0 +Line 5677: 0 +Line 5678: 1 +Line 5679: 0 +Line 5680: 1 +Line 5681: 1 +Line 5682: 1 +Line 5683: 1 +Line 5684: 1 +Line 5685: 1 +Line 5686: 1 +Line 5687: 1 +Line 5688: 1 +Line 5689: 0 +Line 5690: 1 +Line 5691: 0 +Line 5692: 0 +Line 5693: 0 +Line 5694: 1 +Line 5695: 1 +Line 5696: 0 +Line 5697: 0 +Line 5698: 0 +Line 5699: 0 +Line 5700: 0 +Line 5701: 0 +Line 5702: 0 +Line 5703: 1 +Line 5704: 0 +Line 5705: 0 +Line 5706: 0 +Line 5707: 1 +Line 5708: 1 +Line 5709: 1 +Line 5710: 0 +Line 5711: 1 +Line 5712: 1 +Line 5713: 1 +Line 5714: 1 +Line 5715: 1 +Line 5716: 1 +Line 5717: 1 +Line 5718: 1 +Line 5719: 1 +Line 5720: 1 +Line 5721: 0 +Line 5722: 0 +Line 5723: 1 +Line 5724: 0 +Line 5725: 1 +Line 5726: 0 +Line 5727: 0 +Line 5728: 0 +Line 5729: 0 +Line 5730: 0 +Line 5731: 0 +Line 5732: 0 +Line 5733: 0 +Line 5734: 0 +Line 5735: 1 +Line 5736: 0 +Line 5737: 1 +Line 5738: 1 +Line 5739: 1 +Line 5740: 0 +Line 5741: 1 +Line 5742: 0 +Line 5743: 0 +Line 5744: 1 +Line 5745: 1 +Line 5746: 1 +Line 5747: 1 +Line 5748: 1 +Line 5749: 1 +Line 5750: 1 +Line 5751: 1 +Line 5752: 1 +Line 5753: 0 +Line 5754: 0 +Line 5755: 0 +Line 5756: 0 +Line 5757: 1 +Line 5758: 0 +Line 5759: 0 +Line 5760: 0 +Line 5761: 0 +Line 5762: 0 +Line 5763: 0 +Line 5764: 0 +Line 5765: 0 +Line 5766: 0 +Line 5767: 1 +Line 5768: 1 +Line 5769: 1 +Line 5770: 0 +Line 5771: 1 +Line 5772: 0 +Line 5773: 1 +Line 5774: 1 +Line 5775: 1 +Line 5776: 1 +Line 5777: 1 +Line 5778: 1 +Line 5779: 1 +Line 5780: 1 +Line 5781: 1 +Line 5782: 1 +Line 5783: 1 +Line 5784: 0 +Line 5785: 1 +Line 5786: 1 +Line 5787: 1 +Line 5788: 0 +Line 5789: 1 +Line 5790: 0 +Line 5791: 1 +Line 5792: 0 +Line 5793: 0 +Line 5794: 0 +Line 5795: 0 +Line 5796: 0 +Line 5797: 0 +Line 5798: 1 +Line 5799: 0 +Line 5800: 0 +Line 5801: 1 +Line 5802: 0 +Line 5803: 0 +Line 5804: 0 +Line 5805: 1 +Line 5806: 0 +Line 5807: 0 +Line 5808: 1 +Line 5809: 1 +Line 5810: 1 +Line 5811: 1 +Line 5812: 1 +Line 5813: 1 +Line 5814: 1 +Line 5815: 1 +Line 5816: 0 +Line 5817: 1 +Line 5818: 1 +Line 5819: 0 +Line 5820: 0 +Line 5821: 1 +Line 5822: 1 +Line 5823: 1 +Line 5824: 0 +Line 5825: 0 +Line 5826: 0 +Line 5827: 0 +Line 5828: 0 +Line 5829: 0 +Line 5830: 1 +Line 5831: 0 +Line 5832: 1 +Line 5833: 0 +Line 5834: 1 +Line 5835: 1 +Line 5836: 1 +Line 5837: 1 +Line 5838: 0 +Line 5839: 0 +Line 5840: 1 +Line 5841: 1 +Line 5842: 1 +Line 5843: 1 +Line 5844: 1 +Line 5845: 1 +Line 5846: 1 +Line 5847: 1 +Line 5848: 0 +Line 5849: 1 +Line 5850: 0 +Line 5851: 1 +Line 5852: 1 +Line 5853: 0 +Line 5854: 0 +Line 5855: 0 +Line 5856: 0 +Line 5857: 0 +Line 5858: 0 +Line 5859: 0 +Line 5860: 0 +Line 5861: 0 +Line 5862: 1 +Line 5863: 1 +Line 5864: 0 +Line 5865: 0 +Line 5866: 1 +Line 5867: 1 +Line 5868: 1 +Line 5869: 1 +Line 5870: 1 +Line 5871: 1 +Line 5872: 1 +Line 5873: 1 +Line 5874: 1 +Line 5875: 1 +Line 5876: 1 +Line 5877: 1 +Line 5878: 1 +Line 5879: 1 +Line 5880: 0 +Line 5881: 1 +Line 5882: 0 +Line 5883: 0 +Line 5884: 1 +Line 5885: 0 +Line 5886: 1 +Line 5887: 0 +Line 5888: 0 +Line 5889: 0 +Line 5890: 0 +Line 5891: 0 +Line 5892: 0 +Line 5893: 0 +Line 5894: 1 +Line 5895: 1 +Line 5896: 1 +Line 5897: 1 +Line 5898: 0 +Line 5899: 0 +Line 5900: 1 +Line 5901: 1 +Line 5902: 0 +Line 5903: 1 +Line 5904: 1 +Line 5905: 1 +Line 5906: 1 +Line 5907: 1 +Line 5908: 1 +Line 5909: 1 +Line 5910: 1 +Line 5911: 1 +Line 5912: 0 +Line 5913: 0 +Line 5914: 1 +Line 5915: 1 +Line 5916: 1 +Line 5917: 0 +Line 5918: 1 +Line 5919: 1 +Line 5920: 0 +Line 5921: 0 +Line 5922: 0 +Line 5923: 0 +Line 5924: 0 +Line 5925: 1 +Line 5926: 0 +Line 5927: 0 +Line 5928: 0 +Line 5929: 1 +Line 5930: 1 +Line 5931: 0 +Line 5932: 0 +Line 5933: 1 +Line 5934: 0 +Line 5935: 1 +Line 5936: 1 +Line 5937: 1 +Line 5938: 1 +Line 5939: 1 +Line 5940: 1 +Line 5941: 1 +Line 5942: 1 +Line 5943: 1 +Line 5944: 0 +Line 5945: 0 +Line 5946: 1 +Line 5947: 0 +Line 5948: 1 +Line 5949: 1 +Line 5950: 1 +Line 5951: 0 +Line 5952: 0 +Line 5953: 0 +Line 5954: 0 +Line 5955: 0 +Line 5956: 0 +Line 5957: 1 +Line 5958: 0 +Line 5959: 1 +Line 5960: 0 +Line 5961: 0 +Line 5962: 0 +Line 5963: 0 +Line 5964: 1 +Line 5965: 0 +Line 5966: 0 +Line 5967: 0 +Line 5968: 1 +Line 5969: 1 +Line 5970: 1 +Line 5971: 1 +Line 5972: 1 +Line 5973: 1 +Line 5974: 1 +Line 5975: 1 +Line 5976: 0 +Line 5977: 0 +Line 5978: 1 +Line 5979: 0 +Line 5980: 0 +Line 5981: 0 +Line 5982: 0 +Line 5983: 0 +Line 5984: 0 +Line 5985: 0 +Line 5986: 0 +Line 5987: 0 +Line 5988: 0 +Line 5989: 1 +Line 5990: 0 +Line 5991: 1 +Line 5992: 1 +Line 5993: 0 +Line 5994: 1 +Line 5995: 1 +Line 5996: 0 +Line 5997: 1 +Line 5998: 0 +Line 5999: 0 +Line 6000: 1 +Line 6001: 1 +Line 6002: 1 +Line 6003: 1 +Line 6004: 1 +Line 6005: 1 +Line 6006: 1 +Line 6007: 1 +Line 6008: 0 +Line 6009: 0 +Line 6010: 0 +Line 6011: 1 +Line 6012: 0 +Line 6013: 0 +Line 6014: 1 +Line 6015: 1 +Line 6016: 0 +Line 6017: 0 +Line 6018: 0 +Line 6019: 0 +Line 6020: 0 +Line 6021: 1 +Line 6022: 1 +Line 6023: 0 +Line 6024: 0 +Line 6025: 1 +Line 6026: 1 +Line 6027: 0 +Line 6028: 1 +Line 6029: 0 +Line 6030: 1 +Line 6031: 1 +Line 6032: 1 +Line 6033: 1 +Line 6034: 1 +Line 6035: 1 +Line 6036: 1 +Line 6037: 1 +Line 6038: 1 +Line 6039: 1 +Line 6040: 0 +Line 6041: 0 +Line 6042: 0 +Line 6043: 0 +Line 6044: 0 +Line 6045: 1 +Line 6046: 1 +Line 6047: 0 +Line 6048: 0 +Line 6049: 0 +Line 6050: 0 +Line 6051: 0 +Line 6052: 0 +Line 6053: 1 +Line 6054: 1 +Line 6055: 1 +Line 6056: 0 +Line 6057: 0 +Line 6058: 1 +Line 6059: 0 +Line 6060: 1 +Line 6061: 0 +Line 6062: 1 +Line 6063: 1 +Line 6064: 1 +Line 6065: 1 +Line 6066: 1 +Line 6067: 1 +Line 6068: 1 +Line 6069: 1 +Line 6070: 1 +Line 6071: 0 +Line 6072: 1 +Line 6073: 1 +Line 6074: 1 +Line 6075: 1 +Line 6076: 1 +Line 6077: 0 +Line 6078: 0 +Line 6079: 1 +Line 6080: 0 +Line 6081: 0 +Line 6082: 0 +Line 6083: 0 +Line 6084: 0 +Line 6085: 1 +Line 6086: 1 +Line 6087: 1 +Line 6088: 1 +Line 6089: 1 +Line 6090: 1 +Line 6091: 1 +Line 6092: 0 +Line 6093: 1 +Line 6094: 0 +Line 6095: 0 +Line 6096: 1 +Line 6097: 1 +Line 6098: 1 +Line 6099: 1 +Line 6100: 1 +Line 6101: 1 +Line 6102: 1 +Line 6103: 0 +Line 6104: 1 +Line 6105: 1 +Line 6106: 1 +Line 6107: 0 +Line 6108: 1 +Line 6109: 1 +Line 6110: 0 +Line 6111: 1 +Line 6112: 0 +Line 6113: 0 +Line 6114: 0 +Line 6115: 0 +Line 6116: 1 +Line 6117: 0 +Line 6118: 0 +Line 6119: 0 +Line 6120: 1 +Line 6121: 1 +Line 6122: 0 +Line 6123: 0 +Line 6124: 0 +Line 6125: 1 +Line 6126: 1 +Line 6127: 0 +Line 6128: 1 +Line 6129: 1 +Line 6130: 1 +Line 6131: 1 +Line 6132: 1 +Line 6133: 1 +Line 6134: 1 +Line 6135: 0 +Line 6136: 1 +Line 6137: 1 +Line 6138: 1 +Line 6139: 0 +Line 6140: 0 +Line 6141: 0 +Line 6142: 0 +Line 6143: 1 +Line 6144: 0 +Line 6145: 0 +Line 6146: 0 +Line 6147: 0 +Line 6148: 1 +Line 6149: 0 +Line 6150: 0 +Line 6151: 1 +Line 6152: 1 +Line 6153: 0 +Line 6154: 1 +Line 6155: 0 +Line 6156: 0 +Line 6157: 0 +Line 6158: 1 +Line 6159: 0 +Line 6160: 1 +Line 6161: 1 +Line 6162: 1 +Line 6163: 1 +Line 6164: 1 +Line 6165: 1 +Line 6166: 1 +Line 6167: 0 +Line 6168: 1 +Line 6169: 1 +Line 6170: 0 +Line 6171: 1 +Line 6172: 0 +Line 6173: 1 +Line 6174: 0 +Line 6175: 1 +Line 6176: 0 +Line 6177: 0 +Line 6178: 0 +Line 6179: 0 +Line 6180: 1 +Line 6181: 0 +Line 6182: 1 +Line 6183: 0 +Line 6184: 1 +Line 6185: 0 +Line 6186: 0 +Line 6187: 0 +Line 6188: 0 +Line 6189: 1 +Line 6190: 0 +Line 6191: 1 +Line 6192: 1 +Line 6193: 1 +Line 6194: 1 +Line 6195: 1 +Line 6196: 1 +Line 6197: 1 +Line 6198: 1 +Line 6199: 0 +Line 6200: 1 +Line 6201: 1 +Line 6202: 0 +Line 6203: 0 +Line 6204: 1 +Line 6205: 0 +Line 6206: 1 +Line 6207: 0 +Line 6208: 0 +Line 6209: 0 +Line 6210: 0 +Line 6211: 0 +Line 6212: 1 +Line 6213: 0 +Line 6214: 1 +Line 6215: 1 +Line 6216: 0 +Line 6217: 1 +Line 6218: 1 +Line 6219: 1 +Line 6220: 0 +Line 6221: 0 +Line 6222: 0 +Line 6223: 1 +Line 6224: 1 +Line 6225: 1 +Line 6226: 1 +Line 6227: 1 +Line 6228: 1 +Line 6229: 1 +Line 6230: 1 +Line 6231: 0 +Line 6232: 1 +Line 6233: 0 +Line 6234: 1 +Line 6235: 1 +Line 6236: 1 +Line 6237: 1 +Line 6238: 1 +Line 6239: 1 +Line 6240: 0 +Line 6241: 0 +Line 6242: 0 +Line 6243: 0 +Line 6244: 1 +Line 6245: 1 +Line 6246: 0 +Line 6247: 0 +Line 6248: 0 +Line 6249: 1 +Line 6250: 1 +Line 6251: 0 +Line 6252: 0 +Line 6253: 1 +Line 6254: 0 +Line 6255: 1 +Line 6256: 1 +Line 6257: 1 +Line 6258: 1 +Line 6259: 1 +Line 6260: 1 +Line 6261: 1 +Line 6262: 1 +Line 6263: 0 +Line 6264: 1 +Line 6265: 0 +Line 6266: 1 +Line 6267: 1 +Line 6268: 0 +Line 6269: 1 +Line 6270: 0 +Line 6271: 1 +Line 6272: 0 +Line 6273: 0 +Line 6274: 0 +Line 6275: 0 +Line 6276: 1 +Line 6277: 1 +Line 6278: 0 +Line 6279: 1 +Line 6280: 0 +Line 6281: 1 +Line 6282: 1 +Line 6283: 0 +Line 6284: 0 +Line 6285: 0 +Line 6286: 0 +Line 6287: 0 +Line 6288: 1 +Line 6289: 1 +Line 6290: 1 +Line 6291: 1 +Line 6292: 1 +Line 6293: 1 +Line 6294: 1 +Line 6295: 0 +Line 6296: 1 +Line 6297: 0 +Line 6298: 1 +Line 6299: 0 +Line 6300: 1 +Line 6301: 0 +Line 6302: 1 +Line 6303: 1 +Line 6304: 0 +Line 6305: 0 +Line 6306: 0 +Line 6307: 0 +Line 6308: 1 +Line 6309: 1 +Line 6310: 1 +Line 6311: 0 +Line 6312: 0 +Line 6313: 1 +Line 6314: 1 +Line 6315: 0 +Line 6316: 0 +Line 6317: 0 +Line 6318: 1 +Line 6319: 1 +Line 6320: 1 +Line 6321: 1 +Line 6322: 1 +Line 6323: 1 +Line 6324: 1 +Line 6325: 1 +Line 6326: 1 +Line 6327: 0 +Line 6328: 1 +Line 6329: 0 +Line 6330: 1 +Line 6331: 0 +Line 6332: 0 +Line 6333: 0 +Line 6334: 0 +Line 6335: 1 +Line 6336: 0 +Line 6337: 0 +Line 6338: 0 +Line 6339: 0 +Line 6340: 1 +Line 6341: 1 +Line 6342: 1 +Line 6343: 1 +Line 6344: 0 +Line 6345: 1 +Line 6346: 1 +Line 6347: 0 +Line 6348: 1 +Line 6349: 1 +Line 6350: 0 +Line 6351: 1 +Line 6352: 1 +Line 6353: 1 +Line 6354: 1 +Line 6355: 1 +Line 6356: 1 +Line 6357: 1 +Line 6358: 1 +Line 6359: 0 +Line 6360: 1 +Line 6361: 0 +Line 6362: 0 +Line 6363: 1 +Line 6364: 1 +Line 6365: 0 +Line 6366: 0 +Line 6367: 0 +Line 6368: 0 +Line 6369: 0 +Line 6370: 0 +Line 6371: 1 +Line 6372: 0 +Line 6373: 0 +Line 6374: 0 +Line 6375: 0 +Line 6376: 0 +Line 6377: 1 +Line 6378: 1 +Line 6379: 1 +Line 6380: 1 +Line 6381: 1 +Line 6382: 0 +Line 6383: 1 +Line 6384: 1 +Line 6385: 1 +Line 6386: 1 +Line 6387: 1 +Line 6388: 1 +Line 6389: 1 +Line 6390: 1 +Line 6391: 0 +Line 6392: 1 +Line 6393: 0 +Line 6394: 0 +Line 6395: 0 +Line 6396: 1 +Line 6397: 1 +Line 6398: 1 +Line 6399: 1 +Line 6400: 0 +Line 6401: 0 +Line 6402: 0 +Line 6403: 1 +Line 6404: 0 +Line 6405: 0 +Line 6406: 0 +Line 6407: 1 +Line 6408: 1 +Line 6409: 0 +Line 6410: 0 +Line 6411: 1 +Line 6412: 0 +Line 6413: 1 +Line 6414: 0 +Line 6415: 0 +Line 6416: 1 +Line 6417: 1 +Line 6418: 1 +Line 6419: 1 +Line 6420: 1 +Line 6421: 1 +Line 6422: 1 +Line 6423: 0 +Line 6424: 1 +Line 6425: 0 +Line 6426: 0 +Line 6427: 0 +Line 6428: 0 +Line 6429: 1 +Line 6430: 1 +Line 6431: 1 +Line 6432: 0 +Line 6433: 0 +Line 6434: 0 +Line 6435: 1 +Line 6436: 0 +Line 6437: 0 +Line 6438: 1 +Line 6439: 0 +Line 6440: 1 +Line 6441: 0 +Line 6442: 1 +Line 6443: 1 +Line 6444: 0 +Line 6445: 0 +Line 6446: 0 +Line 6447: 0 +Line 6448: 1 +Line 6449: 1 +Line 6450: 1 +Line 6451: 1 +Line 6452: 1 +Line 6453: 1 +Line 6454: 1 +Line 6455: 0 +Line 6456: 1 +Line 6457: 0 +Line 6458: 0 +Line 6459: 0 +Line 6460: 0 +Line 6461: 0 +Line 6462: 0 +Line 6463: 0 +Line 6464: 0 +Line 6465: 0 +Line 6466: 0 +Line 6467: 1 +Line 6468: 0 +Line 6469: 0 +Line 6470: 1 +Line 6471: 1 +Line 6472: 1 +Line 6473: 1 +Line 6474: 0 +Line 6475: 1 +Line 6476: 0 +Line 6477: 0 +Line 6478: 1 +Line 6479: 0 +Line 6480: 1 +Line 6481: 1 +Line 6482: 1 +Line 6483: 1 +Line 6484: 1 +Line 6485: 1 +Line 6486: 1 +Line 6487: 0 +Line 6488: 0 +Line 6489: 1 +Line 6490: 1 +Line 6491: 1 +Line 6492: 1 +Line 6493: 0 +Line 6494: 0 +Line 6495: 1 +Line 6496: 0 +Line 6497: 0 +Line 6498: 0 +Line 6499: 1 +Line 6500: 0 +Line 6501: 1 +Line 6502: 0 +Line 6503: 0 +Line 6504: 1 +Line 6505: 1 +Line 6506: 1 +Line 6507: 1 +Line 6508: 1 +Line 6509: 0 +Line 6510: 0 +Line 6511: 1 +Line 6512: 1 +Line 6513: 1 +Line 6514: 1 +Line 6515: 1 +Line 6516: 1 +Line 6517: 1 +Line 6518: 1 +Line 6519: 0 +Line 6520: 0 +Line 6521: 1 +Line 6522: 1 +Line 6523: 1 +Line 6524: 0 +Line 6525: 0 +Line 6526: 1 +Line 6527: 0 +Line 6528: 0 +Line 6529: 0 +Line 6530: 0 +Line 6531: 1 +Line 6532: 0 +Line 6533: 1 +Line 6534: 1 +Line 6535: 0 +Line 6536: 0 +Line 6537: 0 +Line 6538: 1 +Line 6539: 0 +Line 6540: 0 +Line 6541: 1 +Line 6542: 0 +Line 6543: 0 +Line 6544: 1 +Line 6545: 1 +Line 6546: 1 +Line 6547: 1 +Line 6548: 1 +Line 6549: 1 +Line 6550: 1 +Line 6551: 0 +Line 6552: 0 +Line 6553: 1 +Line 6554: 1 +Line 6555: 0 +Line 6556: 1 +Line 6557: 1 +Line 6558: 0 +Line 6559: 0 +Line 6560: 0 +Line 6561: 0 +Line 6562: 0 +Line 6563: 1 +Line 6564: 0 +Line 6565: 1 +Line 6566: 1 +Line 6567: 1 +Line 6568: 0 +Line 6569: 1 +Line 6570: 0 +Line 6571: 1 +Line 6572: 0 +Line 6573: 1 +Line 6574: 0 +Line 6575: 0 +Line 6576: 1 +Line 6577: 1 +Line 6578: 1 +Line 6579: 1 +Line 6580: 1 +Line 6581: 1 +Line 6582: 1 +Line 6583: 0 +Line 6584: 0 +Line 6585: 1 +Line 6586: 1 +Line 6587: 0 +Line 6588: 0 +Line 6589: 1 +Line 6590: 1 +Line 6591: 0 +Line 6592: 0 +Line 6593: 0 +Line 6594: 0 +Line 6595: 1 +Line 6596: 1 +Line 6597: 0 +Line 6598: 0 +Line 6599: 0 +Line 6600: 1 +Line 6601: 0 +Line 6602: 0 +Line 6603: 0 +Line 6604: 1 +Line 6605: 0 +Line 6606: 0 +Line 6607: 0 +Line 6608: 1 +Line 6609: 1 +Line 6610: 1 +Line 6611: 1 +Line 6612: 1 +Line 6613: 1 +Line 6614: 1 +Line 6615: 0 +Line 6616: 0 +Line 6617: 1 +Line 6618: 1 +Line 6619: 0 +Line 6620: 0 +Line 6621: 0 +Line 6622: 0 +Line 6623: 1 +Line 6624: 0 +Line 6625: 0 +Line 6626: 0 +Line 6627: 1 +Line 6628: 1 +Line 6629: 0 +Line 6630: 0 +Line 6631: 1 +Line 6632: 1 +Line 6633: 1 +Line 6634: 0 +Line 6635: 0 +Line 6636: 0 +Line 6637: 0 +Line 6638: 0 +Line 6639: 0 +Line 6640: 1 +Line 6641: 1 +Line 6642: 1 +Line 6643: 1 +Line 6644: 1 +Line 6645: 1 +Line 6646: 1 +Line 6647: 0 +Line 6648: 0 +Line 6649: 1 +Line 6650: 0 +Line 6651: 1 +Line 6652: 1 +Line 6653: 1 +Line 6654: 0 +Line 6655: 1 +Line 6656: 0 +Line 6657: 0 +Line 6658: 0 +Line 6659: 1 +Line 6660: 1 +Line 6661: 0 +Line 6662: 1 +Line 6663: 0 +Line 6664: 1 +Line 6665: 1 +Line 6666: 1 +Line 6667: 1 +Line 6668: 1 +Line 6669: 0 +Line 6670: 1 +Line 6671: 0 +Line 6672: 1 +Line 6673: 1 +Line 6674: 1 +Line 6675: 1 +Line 6676: 1 +Line 6677: 1 +Line 6678: 1 +Line 6679: 0 +Line 6680: 0 +Line 6681: 1 +Line 6682: 0 +Line 6683: 1 +Line 6684: 1 +Line 6685: 0 +Line 6686: 0 +Line 6687: 1 +Line 6688: 0 +Line 6689: 0 +Line 6690: 0 +Line 6691: 1 +Line 6692: 1 +Line 6693: 1 +Line 6694: 0 +Line 6695: 0 +Line 6696: 0 +Line 6697: 0 +Line 6698: 1 +Line 6699: 1 +Line 6700: 1 +Line 6701: 0 +Line 6702: 0 +Line 6703: 0 +Line 6704: 1 +Line 6705: 1 +Line 6706: 1 +Line 6707: 1 +Line 6708: 1 +Line 6709: 1 +Line 6710: 1 +Line 6711: 0 +Line 6712: 0 +Line 6713: 1 +Line 6714: 0 +Line 6715: 1 +Line 6716: 0 +Line 6717: 1 +Line 6718: 1 +Line 6719: 0 +Line 6720: 0 +Line 6721: 0 +Line 6722: 0 +Line 6723: 1 +Line 6724: 1 +Line 6725: 1 +Line 6726: 0 +Line 6727: 1 +Line 6728: 0 +Line 6729: 1 +Line 6730: 1 +Line 6731: 1 +Line 6732: 0 +Line 6733: 1 +Line 6734: 1 +Line 6735: 1 +Line 6736: 1 +Line 6737: 1 +Line 6738: 1 +Line 6739: 1 +Line 6740: 1 +Line 6741: 1 +Line 6742: 1 +Line 6743: 0 +Line 6744: 0 +Line 6745: 1 +Line 6746: 0 +Line 6747: 1 +Line 6748: 0 +Line 6749: 0 +Line 6750: 1 +Line 6751: 1 +Line 6752: 0 +Line 6753: 0 +Line 6754: 0 +Line 6755: 1 +Line 6756: 1 +Line 6757: 1 +Line 6758: 1 +Line 6759: 0 +Line 6760: 1 +Line 6761: 0 +Line 6762: 1 +Line 6763: 1 +Line 6764: 1 +Line 6765: 0 +Line 6766: 0 +Line 6767: 1 +Line 6768: 1 +Line 6769: 1 +Line 6770: 1 +Line 6771: 1 +Line 6772: 1 +Line 6773: 1 +Line 6774: 1 +Line 6775: 0 +Line 6776: 0 +Line 6777: 1 +Line 6778: 0 +Line 6779: 1 +Line 6780: 0 +Line 6781: 0 +Line 6782: 0 +Line 6783: 0 +Line 6784: 0 +Line 6785: 0 +Line 6786: 0 +Line 6787: 1 +Line 6788: 1 +Line 6789: 1 +Line 6790: 1 +Line 6791: 1 +Line 6792: 1 +Line 6793: 1 +Line 6794: 1 +Line 6795: 1 +Line 6796: 1 +Line 6797: 1 +Line 6798: 0 +Line 6799: 0 +Line 6800: 1 +Line 6801: 1 +Line 6802: 1 +Line 6803: 1 +Line 6804: 1 +Line 6805: 1 +Line 6806: 1 +Line 6807: 0 +Line 6808: 0 +Line 6809: 1 +Line 6810: 0 +Line 6811: 0 +Line 6812: 1 +Line 6813: 1 +Line 6814: 1 +Line 6815: 1 +Line 6816: 0 +Line 6817: 0 +Line 6818: 1 +Line 6819: 0 +Line 6820: 0 +Line 6821: 0 +Line 6822: 0 +Line 6823: 1 +Line 6824: 0 +Line 6825: 1 +Line 6826: 0 +Line 6827: 0 +Line 6828: 0 +Line 6829: 0 +Line 6830: 0 +Line 6831: 0 +Line 6832: 1 +Line 6833: 1 +Line 6834: 1 +Line 6835: 1 +Line 6836: 1 +Line 6837: 1 +Line 6838: 1 +Line 6839: 0 +Line 6840: 0 +Line 6841: 1 +Line 6842: 0 +Line 6843: 0 +Line 6844: 1 +Line 6845: 1 +Line 6846: 1 +Line 6847: 0 +Line 6848: 0 +Line 6849: 0 +Line 6850: 1 +Line 6851: 0 +Line 6852: 0 +Line 6853: 0 +Line 6854: 1 +Line 6855: 0 +Line 6856: 1 +Line 6857: 0 +Line 6858: 0 +Line 6859: 0 +Line 6860: 0 +Line 6861: 1 +Line 6862: 0 +Line 6863: 1 +Line 6864: 1 +Line 6865: 1 +Line 6866: 1 +Line 6867: 1 +Line 6868: 1 +Line 6869: 1 +Line 6870: 1 +Line 6871: 0 +Line 6872: 0 +Line 6873: 1 +Line 6874: 0 +Line 6875: 0 +Line 6876: 1 +Line 6877: 1 +Line 6878: 0 +Line 6879: 1 +Line 6880: 0 +Line 6881: 0 +Line 6882: 1 +Line 6883: 0 +Line 6884: 0 +Line 6885: 0 +Line 6886: 1 +Line 6887: 1 +Line 6888: 1 +Line 6889: 1 +Line 6890: 0 +Line 6891: 0 +Line 6892: 1 +Line 6893: 0 +Line 6894: 1 +Line 6895: 0 +Line 6896: 1 +Line 6897: 1 +Line 6898: 1 +Line 6899: 1 +Line 6900: 1 +Line 6901: 1 +Line 6902: 1 +Line 6903: 0 +Line 6904: 0 +Line 6905: 1 +Line 6906: 0 +Line 6907: 0 +Line 6908: 1 +Line 6909: 1 +Line 6910: 0 +Line 6911: 1 +Line 6912: 0 +Line 6913: 0 +Line 6914: 1 +Line 6915: 0 +Line 6916: 0 +Line 6917: 1 +Line 6918: 0 +Line 6919: 1 +Line 6920: 0 +Line 6921: 0 +Line 6922: 0 +Line 6923: 0 +Line 6924: 1 +Line 6925: 1 +Line 6926: 1 +Line 6927: 1 +Line 6928: 1 +Line 6929: 1 +Line 6930: 1 +Line 6931: 1 +Line 6932: 1 +Line 6933: 1 +Line 6934: 1 +Line 6935: 0 +Line 6936: 0 +Line 6937: 1 +Line 6938: 0 +Line 6939: 0 +Line 6940: 1 +Line 6941: 1 +Line 6942: 1 +Line 6943: 0 +Line 6944: 0 +Line 6945: 0 +Line 6946: 1 +Line 6947: 0 +Line 6948: 0 +Line 6949: 1 +Line 6950: 1 +Line 6951: 0 +Line 6952: 0 +Line 6953: 1 +Line 6954: 0 +Line 6955: 1 +Line 6956: 0 +Line 6957: 0 +Line 6958: 1 +Line 6959: 1 +Line 6960: 1 +Line 6961: 1 +Line 6962: 1 +Line 6963: 1 +Line 6964: 1 +Line 6965: 1 +Line 6966: 1 +Line 6967: 0 +Line 6968: 0 +Line 6969: 1 +Line 6970: 0 +Line 6971: 0 +Line 6972: 1 +Line 6973: 1 +Line 6974: 1 +Line 6975: 1 +Line 6976: 0 +Line 6977: 0 +Line 6978: 1 +Line 6979: 0 +Line 6980: 0 +Line 6981: 1 +Line 6982: 1 +Line 6983: 1 +Line 6984: 1 +Line 6985: 0 +Line 6986: 0 +Line 6987: 1 +Line 6988: 0 +Line 6989: 1 +Line 6990: 1 +Line 6991: 0 +Line 6992: 1 +Line 6993: 1 +Line 6994: 1 +Line 6995: 1 +Line 6996: 1 +Line 6997: 1 +Line 6998: 1 +Line 6999: 0 +Line 7000: 0 +Line 7001: 1 +Line 7002: 0 +Line 7003: 1 +Line 7004: 0 +Line 7005: 0 +Line 7006: 0 +Line 7007: 0 +Line 7008: 0 +Line 7009: 0 +Line 7010: 1 +Line 7011: 0 +Line 7012: 1 +Line 7013: 0 +Line 7014: 0 +Line 7015: 0 +Line 7016: 1 +Line 7017: 1 +Line 7018: 0 +Line 7019: 1 +Line 7020: 1 +Line 7021: 0 +Line 7022: 0 +Line 7023: 0 +Line 7024: 1 +Line 7025: 1 +Line 7026: 1 +Line 7027: 1 +Line 7028: 1 +Line 7029: 1 +Line 7030: 1 +Line 7031: 0 +Line 7032: 0 +Line 7033: 1 +Line 7034: 0 +Line 7035: 1 +Line 7036: 0 +Line 7037: 0 +Line 7038: 1 +Line 7039: 1 +Line 7040: 0 +Line 7041: 0 +Line 7042: 1 +Line 7043: 0 +Line 7044: 1 +Line 7045: 0 +Line 7046: 1 +Line 7047: 0 +Line 7048: 0 +Line 7049: 0 +Line 7050: 0 +Line 7051: 1 +Line 7052: 0 +Line 7053: 1 +Line 7054: 1 +Line 7055: 1 +Line 7056: 1 +Line 7057: 1 +Line 7058: 1 +Line 7059: 1 +Line 7060: 1 +Line 7061: 1 +Line 7062: 1 +Line 7063: 0 +Line 7064: 0 +Line 7065: 1 +Line 7066: 0 +Line 7067: 1 +Line 7068: 0 +Line 7069: 1 +Line 7070: 1 +Line 7071: 0 +Line 7072: 0 +Line 7073: 0 +Line 7074: 1 +Line 7075: 0 +Line 7076: 1 +Line 7077: 0 +Line 7078: 1 +Line 7079: 1 +Line 7080: 0 +Line 7081: 1 +Line 7082: 0 +Line 7083: 1 +Line 7084: 0 +Line 7085: 1 +Line 7086: 0 +Line 7087: 1 +Line 7088: 1 +Line 7089: 1 +Line 7090: 1 +Line 7091: 1 +Line 7092: 1 +Line 7093: 1 +Line 7094: 1 +Line 7095: 0 +Line 7096: 0 +Line 7097: 1 +Line 7098: 0 +Line 7099: 1 +Line 7100: 1 +Line 7101: 0 +Line 7102: 0 +Line 7103: 1 +Line 7104: 0 +Line 7105: 0 +Line 7106: 1 +Line 7107: 0 +Line 7108: 1 +Line 7109: 1 +Line 7110: 0 +Line 7111: 0 +Line 7112: 1 +Line 7113: 0 +Line 7114: 0 +Line 7115: 0 +Line 7116: 1 +Line 7117: 1 +Line 7118: 1 +Line 7119: 1 +Line 7120: 1 +Line 7121: 1 +Line 7122: 1 +Line 7123: 1 +Line 7124: 1 +Line 7125: 1 +Line 7126: 1 +Line 7127: 0 +Line 7128: 0 +Line 7129: 1 +Line 7130: 0 +Line 7131: 1 +Line 7132: 1 +Line 7133: 1 +Line 7134: 0 +Line 7135: 1 +Line 7136: 0 +Line 7137: 0 +Line 7138: 1 +Line 7139: 0 +Line 7140: 1 +Line 7141: 1 +Line 7142: 0 +Line 7143: 1 +Line 7144: 1 +Line 7145: 1 +Line 7146: 0 +Line 7147: 0 +Line 7148: 0 +Line 7149: 1 +Line 7150: 1 +Line 7151: 1 +Line 7152: 1 +Line 7153: 1 +Line 7154: 1 +Line 7155: 1 +Line 7156: 1 +Line 7157: 1 +Line 7158: 1 +Line 7159: 0 +Line 7160: 0 +Line 7161: 1 +Line 7162: 1 +Line 7163: 0 +Line 7164: 0 +Line 7165: 0 +Line 7166: 0 +Line 7167: 1 +Line 7168: 0 +Line 7169: 0 +Line 7170: 1 +Line 7171: 0 +Line 7172: 1 +Line 7173: 1 +Line 7174: 1 +Line 7175: 0 +Line 7176: 1 +Line 7177: 1 +Line 7178: 1 +Line 7179: 1 +Line 7180: 1 +Line 7181: 0 +Line 7182: 1 +Line 7183: 1 +Line 7184: 1 +Line 7185: 1 +Line 7186: 1 +Line 7187: 1 +Line 7188: 1 +Line 7189: 1 +Line 7190: 1 +Line 7191: 0 +Line 7192: 0 +Line 7193: 1 +Line 7194: 1 +Line 7195: 0 +Line 7196: 0 +Line 7197: 1 +Line 7198: 1 +Line 7199: 0 +Line 7200: 0 +Line 7201: 0 +Line 7202: 1 +Line 7203: 1 +Line 7204: 0 +Line 7205: 0 +Line 7206: 0 +Line 7207: 0 +Line 7208: 0 +Line 7209: 0 +Line 7210: 1 +Line 7211: 0 +Line 7212: 1 +Line 7213: 0 +Line 7214: 1 +Line 7215: 1 +Line 7216: 1 +Line 7217: 1 +Line 7218: 1 +Line 7219: 1 +Line 7220: 1 +Line 7221: 1 +Line 7222: 1 +Line 7223: 0 +Line 7224: 0 +Line 7225: 1 +Line 7226: 1 +Line 7227: 0 +Line 7228: 1 +Line 7229: 1 +Line 7230: 0 +Line 7231: 0 +Line 7232: 0 +Line 7233: 0 +Line 7234: 1 +Line 7235: 1 +Line 7236: 0 +Line 7237: 0 +Line 7238: 0 +Line 7239: 1 +Line 7240: 0 +Line 7241: 1 +Line 7242: 0 +Line 7243: 1 +Line 7244: 0 +Line 7245: 1 +Line 7246: 1 +Line 7247: 0 +Line 7248: 1 +Line 7249: 1 +Line 7250: 1 +Line 7251: 1 +Line 7252: 1 +Line 7253: 1 +Line 7254: 1 +Line 7255: 0 +Line 7256: 0 +Line 7257: 1 +Line 7258: 1 +Line 7259: 1 +Line 7260: 0 +Line 7261: 0 +Line 7262: 1 +Line 7263: 0 +Line 7264: 0 +Line 7265: 0 +Line 7266: 1 +Line 7267: 1 +Line 7268: 0 +Line 7269: 0 +Line 7270: 1 +Line 7271: 0 +Line 7272: 0 +Line 7273: 1 +Line 7274: 1 +Line 7275: 1 +Line 7276: 1 +Line 7277: 1 +Line 7278: 0 +Line 7279: 1 +Line 7280: 1 +Line 7281: 1 +Line 7282: 1 +Line 7283: 1 +Line 7284: 1 +Line 7285: 1 +Line 7286: 1 +Line 7287: 0 +Line 7288: 0 +Line 7289: 1 +Line 7290: 1 +Line 7291: 1 +Line 7292: 1 +Line 7293: 0 +Line 7294: 0 +Line 7295: 1 +Line 7296: 0 +Line 7297: 0 +Line 7298: 1 +Line 7299: 1 +Line 7300: 0 +Line 7301: 0 +Line 7302: 1 +Line 7303: 1 +Line 7304: 1 +Line 7305: 0 +Line 7306: 0 +Line 7307: 1 +Line 7308: 1 +Line 7309: 1 +Line 7310: 1 +Line 7311: 1 +Line 7312: 1 +Line 7313: 1 +Line 7314: 1 +Line 7315: 1 +Line 7316: 1 +Line 7317: 1 +Line 7318: 1 +Line 7319: 0 +Line 7320: 1 +Line 7321: 0 +Line 7322: 0 +Line 7323: 0 +Line 7324: 0 +Line 7325: 0 +Line 7326: 0 +Line 7327: 0 +Line 7328: 0 +Line 7329: 0 +Line 7330: 1 +Line 7331: 1 +Line 7332: 0 +Line 7333: 1 +Line 7334: 0 +Line 7335: 0 +Line 7336: 1 +Line 7337: 0 +Line 7338: 1 +Line 7339: 1 +Line 7340: 1 +Line 7341: 1 +Line 7342: 0 +Line 7343: 0 +Line 7344: 1 +Line 7345: 1 +Line 7346: 1 +Line 7347: 1 +Line 7348: 1 +Line 7349: 1 +Line 7350: 1 +Line 7351: 0 +Line 7352: 1 +Line 7353: 0 +Line 7354: 0 +Line 7355: 0 +Line 7356: 0 +Line 7357: 1 +Line 7358: 1 +Line 7359: 1 +Line 7360: 0 +Line 7361: 0 +Line 7362: 1 +Line 7363: 1 +Line 7364: 0 +Line 7365: 1 +Line 7366: 0 +Line 7367: 1 +Line 7368: 1 +Line 7369: 1 +Line 7370: 0 +Line 7371: 1 +Line 7372: 0 +Line 7373: 0 +Line 7374: 1 +Line 7375: 0 +Line 7376: 1 +Line 7377: 1 +Line 7378: 1 +Line 7379: 1 +Line 7380: 1 +Line 7381: 1 +Line 7382: 1 +Line 7383: 0 +Line 7384: 1 +Line 7385: 0 +Line 7386: 0 +Line 7387: 0 +Line 7388: 1 +Line 7389: 1 +Line 7390: 1 +Line 7391: 1 +Line 7392: 0 +Line 7393: 0 +Line 7394: 1 +Line 7395: 1 +Line 7396: 0 +Line 7397: 1 +Line 7398: 1 +Line 7399: 0 +Line 7400: 1 +Line 7401: 1 +Line 7402: 1 +Line 7403: 0 +Line 7404: 0 +Line 7405: 0 +Line 7406: 1 +Line 7407: 0 +Line 7408: 1 +Line 7409: 1 +Line 7410: 1 +Line 7411: 1 +Line 7412: 1 +Line 7413: 1 +Line 7414: 1 +Line 7415: 0 +Line 7416: 1 +Line 7417: 0 +Line 7418: 0 +Line 7419: 1 +Line 7420: 1 +Line 7421: 0 +Line 7422: 0 +Line 7423: 0 +Line 7424: 0 +Line 7425: 0 +Line 7426: 1 +Line 7427: 1 +Line 7428: 0 +Line 7429: 1 +Line 7430: 1 +Line 7431: 1 +Line 7432: 1 +Line 7433: 1 +Line 7434: 1 +Line 7435: 0 +Line 7436: 1 +Line 7437: 1 +Line 7438: 0 +Line 7439: 0 +Line 7440: 1 +Line 7441: 1 +Line 7442: 1 +Line 7443: 1 +Line 7444: 1 +Line 7445: 1 +Line 7446: 1 +Line 7447: 0 +Line 7448: 1 +Line 7449: 0 +Line 7450: 1 +Line 7451: 0 +Line 7452: 0 +Line 7453: 0 +Line 7454: 0 +Line 7455: 1 +Line 7456: 0 +Line 7457: 0 +Line 7458: 1 +Line 7459: 1 +Line 7460: 1 +Line 7461: 0 +Line 7462: 0 +Line 7463: 0 +Line 7464: 1 +Line 7465: 1 +Line 7466: 1 +Line 7467: 0 +Line 7468: 1 +Line 7469: 1 +Line 7470: 1 +Line 7471: 1 +Line 7472: 1 +Line 7473: 1 +Line 7474: 1 +Line 7475: 1 +Line 7476: 1 +Line 7477: 1 +Line 7478: 1 +Line 7479: 0 +Line 7480: 1 +Line 7481: 0 +Line 7482: 1 +Line 7483: 0 +Line 7484: 1 +Line 7485: 0 +Line 7486: 1 +Line 7487: 1 +Line 7488: 0 +Line 7489: 0 +Line 7490: 1 +Line 7491: 1 +Line 7492: 1 +Line 7493: 0 +Line 7494: 0 +Line 7495: 1 +Line 7496: 1 +Line 7497: 1 +Line 7498: 1 +Line 7499: 0 +Line 7500: 1 +Line 7501: 0 +Line 7502: 1 +Line 7503: 0 +Line 7504: 1 +Line 7505: 1 +Line 7506: 1 +Line 7507: 1 +Line 7508: 1 +Line 7509: 1 +Line 7510: 1 +Line 7511: 0 +Line 7512: 1 +Line 7513: 0 +Line 7514: 1 +Line 7515: 1 +Line 7516: 0 +Line 7517: 1 +Line 7518: 0 +Line 7519: 1 +Line 7520: 0 +Line 7521: 0 +Line 7522: 1 +Line 7523: 1 +Line 7524: 1 +Line 7525: 0 +Line 7526: 1 +Line 7527: 0 +Line 7528: 1 +Line 7529: 1 +Line 7530: 0 +Line 7531: 1 +Line 7532: 1 +Line 7533: 1 +Line 7534: 1 +Line 7535: 0 +Line 7536: 1 +Line 7537: 1 +Line 7538: 1 +Line 7539: 1 +Line 7540: 1 +Line 7541: 1 +Line 7542: 1 +Line 7543: 0 +Line 7544: 1 +Line 7545: 0 +Line 7546: 1 +Line 7547: 1 +Line 7548: 1 +Line 7549: 1 +Line 7550: 1 +Line 7551: 1 +Line 7552: 0 +Line 7553: 0 +Line 7554: 1 +Line 7555: 1 +Line 7556: 1 +Line 7557: 0 +Line 7558: 1 +Line 7559: 1 +Line 7560: 1 +Line 7561: 1 +Line 7562: 0 +Line 7563: 0 +Line 7564: 1 +Line 7565: 0 +Line 7566: 1 +Line 7567: 0 +Line 7568: 1 +Line 7569: 1 +Line 7570: 1 +Line 7571: 1 +Line 7572: 1 +Line 7573: 1 +Line 7574: 1 +Line 7575: 0 +Line 7576: 1 +Line 7577: 1 +Line 7578: 0 +Line 7579: 0 +Line 7580: 1 +Line 7581: 0 +Line 7582: 1 +Line 7583: 0 +Line 7584: 0 +Line 7585: 0 +Line 7586: 1 +Line 7587: 1 +Line 7588: 1 +Line 7589: 1 +Line 7590: 0 +Line 7591: 0 +Line 7592: 1 +Line 7593: 0 +Line 7594: 1 +Line 7595: 0 +Line 7596: 1 +Line 7597: 1 +Line 7598: 0 +Line 7599: 1 +Line 7600: 1 +Line 7601: 1 +Line 7602: 1 +Line 7603: 1 +Line 7604: 1 +Line 7605: 1 +Line 7606: 1 +Line 7607: 0 +Line 7608: 1 +Line 7609: 1 +Line 7610: 0 +Line 7611: 1 +Line 7612: 0 +Line 7613: 1 +Line 7614: 0 +Line 7615: 1 +Line 7616: 0 +Line 7617: 0 +Line 7618: 1 +Line 7619: 1 +Line 7620: 1 +Line 7621: 1 +Line 7622: 0 +Line 7623: 1 +Line 7624: 1 +Line 7625: 0 +Line 7626: 0 +Line 7627: 0 +Line 7628: 1 +Line 7629: 0 +Line 7630: 0 +Line 7631: 1 +Line 7632: 1 +Line 7633: 1 +Line 7634: 1 +Line 7635: 1 +Line 7636: 1 +Line 7637: 1 +Line 7638: 1 +Line 7639: 0 +Line 7640: 1 +Line 7641: 1 +Line 7642: 1 +Line 7643: 0 +Line 7644: 0 +Line 7645: 0 +Line 7646: 0 +Line 7647: 1 +Line 7648: 0 +Line 7649: 0 +Line 7650: 1 +Line 7651: 1 +Line 7652: 1 +Line 7653: 1 +Line 7654: 1 +Line 7655: 0 +Line 7656: 0 +Line 7657: 1 +Line 7658: 0 +Line 7659: 1 +Line 7660: 1 +Line 7661: 0 +Line 7662: 1 +Line 7663: 1 +Line 7664: 1 +Line 7665: 1 +Line 7666: 1 +Line 7667: 1 +Line 7668: 1 +Line 7669: 1 +Line 7670: 1 +Line 7671: 0 +Line 7672: 1 +Line 7673: 1 +Line 7674: 1 +Line 7675: 0 +Line 7676: 1 +Line 7677: 1 +Line 7678: 0 +Line 7679: 1 +Line 7680: 0 +Line 7681: 0 +Line 7682: 1 +Line 7683: 1 +Line 7684: 1 +Line 7685: 1 +Line 7686: 1 +Line 7687: 1 +Line 7688: 0 +Line 7689: 0 +Line 7690: 1 +Line 7691: 0 +Line 7692: 0 +Line 7693: 1 +Line 7694: 0 +Line 7695: 0 +Line 7696: 1 +Line 7697: 1 +Line 7698: 1 +Line 7699: 1 +Line 7700: 1 +Line 7701: 1 +Line 7702: 1 +Line 7703: 0 +Line 7704: 1 +Line 7705: 1 +Line 7706: 1 +Line 7707: 1 +Line 7708: 1 +Line 7709: 0 +Line 7710: 0 +Line 7711: 1 +Line 7712: 0 +Line 7713: 0 +Line 7714: 1 +Line 7715: 1 +Line 7716: 1 +Line 7717: 1 +Line 7718: 1 +Line 7719: 1 +Line 7720: 1 +Line 7721: 1 +Line 7722: 1 +Line 7723: 0 +Line 7724: 0 +Line 7725: 1 +Line 7726: 0 +Line 7727: 0 +Line 7728: 1 +Line 7729: 1 +Line 7730: 1 +Line 7731: 1 +Line 7732: 1 +Line 7733: 1 +Line 7734: 1 +Line 7735: 1 +Line 7736: 0 +Line 7737: 0 +Line 7738: 0 +Line 7739: 0 +Line 7740: 0 +Line 7741: 1 +Line 7742: 1 +Line 7743: 0 +Line 7744: 0 +Line 7745: 1 +Line 7746: 0 +Line 7747: 0 +Line 7748: 0 +Line 7749: 0 +Line 7750: 0 +Line 7751: 0 +Line 7752: 1 +Line 7753: 0 +Line 7754: 0 +Line 7755: 1 +Line 7756: 1 +Line 7757: 0 +Line 7758: 1 +Line 7759: 1 +Line 7760: 1 +Line 7761: 1 +Line 7762: 1 +Line 7763: 1 +Line 7764: 1 +Line 7765: 1 +Line 7766: 1 +Line 7767: 1 +Line 7768: 0 +Line 7769: 0 +Line 7770: 0 +Line 7771: 1 +Line 7772: 0 +Line 7773: 0 +Line 7774: 1 +Line 7775: 1 +Line 7776: 0 +Line 7777: 1 +Line 7778: 0 +Line 7779: 0 +Line 7780: 0 +Line 7781: 0 +Line 7782: 0 +Line 7783: 1 +Line 7784: 0 +Line 7785: 1 +Line 7786: 0 +Line 7787: 0 +Line 7788: 0 +Line 7789: 1 +Line 7790: 1 +Line 7791: 1 +Line 7792: 1 +Line 7793: 1 +Line 7794: 1 +Line 7795: 1 +Line 7796: 1 +Line 7797: 1 +Line 7798: 1 +Line 7799: 1 +Line 7800: 0 +Line 7801: 0 +Line 7802: 1 +Line 7803: 0 +Line 7804: 0 +Line 7805: 0 +Line 7806: 0 +Line 7807: 0 +Line 7808: 0 +Line 7809: 1 +Line 7810: 0 +Line 7811: 0 +Line 7812: 0 +Line 7813: 0 +Line 7814: 0 +Line 7815: 1 +Line 7816: 1 +Line 7817: 1 +Line 7818: 1 +Line 7819: 0 +Line 7820: 1 +Line 7821: 0 +Line 7822: 1 +Line 7823: 0 +Line 7824: 1 +Line 7825: 1 +Line 7826: 1 +Line 7827: 1 +Line 7828: 1 +Line 7829: 1 +Line 7830: 1 +Line 7831: 1 +Line 7832: 0 +Line 7833: 0 +Line 7834: 1 +Line 7835: 0 +Line 7836: 1 +Line 7837: 1 +Line 7838: 1 +Line 7839: 0 +Line 7840: 0 +Line 7841: 1 +Line 7842: 0 +Line 7843: 0 +Line 7844: 0 +Line 7845: 0 +Line 7846: 1 +Line 7847: 0 +Line 7848: 1 +Line 7849: 0 +Line 7850: 0 +Line 7851: 0 +Line 7852: 0 +Line 7853: 0 +Line 7854: 1 +Line 7855: 0 +Line 7856: 1 +Line 7857: 1 +Line 7858: 1 +Line 7859: 1 +Line 7860: 1 +Line 7861: 1 +Line 7862: 1 +Line 7863: 1 +Line 7864: 0 +Line 7865: 0 +Line 7866: 1 +Line 7867: 1 +Line 7868: 1 +Line 7869: 0 +Line 7870: 1 +Line 7871: 1 +Line 7872: 0 +Line 7873: 1 +Line 7874: 0 +Line 7875: 0 +Line 7876: 0 +Line 7877: 0 +Line 7878: 1 +Line 7879: 1 +Line 7880: 0 +Line 7881: 0 +Line 7882: 0 +Line 7883: 1 +Line 7884: 0 +Line 7885: 0 +Line 7886: 0 +Line 7887: 0 +Line 7888: 1 +Line 7889: 1 +Line 7890: 1 +Line 7891: 1 +Line 7892: 1 +Line 7893: 1 +Line 7894: 1 +Line 7895: 1 +Line 7896: 0 +Line 7897: 1 +Line 7898: 0 +Line 7899: 0 +Line 7900: 1 +Line 7901: 0 +Line 7902: 1 +Line 7903: 0 +Line 7904: 0 +Line 7905: 1 +Line 7906: 0 +Line 7907: 0 +Line 7908: 0 +Line 7909: 0 +Line 7910: 1 +Line 7911: 1 +Line 7912: 1 +Line 7913: 0 +Line 7914: 0 +Line 7915: 1 +Line 7916: 0 +Line 7917: 0 +Line 7918: 1 +Line 7919: 1 +Line 7920: 1 +Line 7921: 1 +Line 7922: 1 +Line 7923: 1 +Line 7924: 1 +Line 7925: 1 +Line 7926: 1 +Line 7927: 1 +Line 7928: 0 +Line 7929: 1 +Line 7930: 0 +Line 7931: 1 +Line 7932: 1 +Line 7933: 0 +Line 7934: 0 +Line 7935: 0 +Line 7936: 0 +Line 7937: 1 +Line 7938: 0 +Line 7939: 0 +Line 7940: 0 +Line 7941: 1 +Line 7942: 0 +Line 7943: 0 +Line 7944: 0 +Line 7945: 0 +Line 7946: 0 +Line 7947: 0 +Line 7948: 1 +Line 7949: 0 +Line 7950: 1 +Line 7951: 1 +Line 7952: 1 +Line 7953: 1 +Line 7954: 1 +Line 7955: 1 +Line 7956: 1 +Line 7957: 1 +Line 7958: 1 +Line 7959: 1 +Line 7960: 0 +Line 7961: 1 +Line 7962: 1 +Line 7963: 0 +Line 7964: 0 +Line 7965: 1 +Line 7966: 1 +Line 7967: 1 +Line 7968: 0 +Line 7969: 1 +Line 7970: 0 +Line 7971: 0 +Line 7972: 0 +Line 7973: 1 +Line 7974: 0 +Line 7975: 0 +Line 7976: 0 +Line 7977: 1 +Line 7978: 1 +Line 7979: 1 +Line 7980: 1 +Line 7981: 0 +Line 7982: 0 +Line 7983: 0 +Line 7984: 1 +Line 7985: 1 +Line 7986: 1 +Line 7987: 1 +Line 7988: 1 +Line 7989: 1 +Line 7990: 1 +Line 7991: 1 +Line 7992: 0 +Line 7993: 1 +Line 7994: 1 +Line 7995: 1 +Line 7996: 0 +Line 7997: 1 +Line 7998: 0 +Line 7999: 1 +Line 8000: 0 +Line 8001: 1 +Line 8002: 0 +Line 8003: 0 +Line 8004: 0 +Line 8005: 1 +Line 8006: 0 +Line 8007: 0 +Line 8008: 1 +Line 8009: 1 +Line 8010: 0 +Line 8011: 1 +Line 8012: 1 +Line 8013: 0 +Line 8014: 1 +Line 8015: 1 +Line 8016: 1 +Line 8017: 1 +Line 8018: 1 +Line 8019: 1 +Line 8020: 1 +Line 8021: 1 +Line 8022: 1 +Line 8023: 1 +Line 8024: 1 +Line 8025: 0 +Line 8026: 0 +Line 8027: 0 +Line 8028: 0 +Line 8029: 1 +Line 8030: 0 +Line 8031: 0 +Line 8032: 0 +Line 8033: 1 +Line 8034: 0 +Line 8035: 0 +Line 8036: 0 +Line 8037: 1 +Line 8038: 0 +Line 8039: 1 +Line 8040: 0 +Line 8041: 0 +Line 8042: 1 +Line 8043: 1 +Line 8044: 0 +Line 8045: 0 +Line 8046: 1 +Line 8047: 0 +Line 8048: 1 +Line 8049: 1 +Line 8050: 1 +Line 8051: 1 +Line 8052: 1 +Line 8053: 1 +Line 8054: 1 +Line 8055: 1 +Line 8056: 1 +Line 8057: 0 +Line 8058: 0 +Line 8059: 1 +Line 8060: 0 +Line 8061: 1 +Line 8062: 0 +Line 8063: 0 +Line 8064: 0 +Line 8065: 1 +Line 8066: 0 +Line 8067: 0 +Line 8068: 0 +Line 8069: 1 +Line 8070: 0 +Line 8071: 1 +Line 8072: 0 +Line 8073: 1 +Line 8074: 1 +Line 8075: 1 +Line 8076: 1 +Line 8077: 1 +Line 8078: 0 +Line 8079: 1 +Line 8080: 1 +Line 8081: 1 +Line 8082: 1 +Line 8083: 1 +Line 8084: 1 +Line 8085: 1 +Line 8086: 1 +Line 8087: 1 +Line 8088: 1 +Line 8089: 0 +Line 8090: 1 +Line 8091: 0 +Line 8092: 0 +Line 8093: 0 +Line 8094: 1 +Line 8095: 1 +Line 8096: 0 +Line 8097: 1 +Line 8098: 0 +Line 8099: 0 +Line 8100: 0 +Line 8101: 1 +Line 8102: 0 +Line 8103: 1 +Line 8104: 1 +Line 8105: 0 +Line 8106: 1 +Line 8107: 1 +Line 8108: 1 +Line 8109: 1 +Line 8110: 0 +Line 8111: 1 +Line 8112: 1 +Line 8113: 1 +Line 8114: 1 +Line 8115: 1 +Line 8116: 1 +Line 8117: 1 +Line 8118: 1 +Line 8119: 1 +Line 8120: 1 +Line 8121: 0 +Line 8122: 1 +Line 8123: 1 +Line 8124: 0 +Line 8125: 0 +Line 8126: 1 +Line 8127: 0 +Line 8128: 0 +Line 8129: 1 +Line 8130: 0 +Line 8131: 0 +Line 8132: 0 +Line 8133: 1 +Line 8134: 0 +Line 8135: 1 +Line 8136: 1 +Line 8137: 1 +Line 8138: 1 +Line 8139: 1 +Line 8140: 0 +Line 8141: 0 +Line 8142: 1 +Line 8143: 0 +Line 8144: 1 +Line 8145: 1 +Line 8146: 1 +Line 8147: 1 +Line 8148: 1 +Line 8149: 1 +Line 8150: 1 +Line 8151: 1 +Line 8152: 1 +Line 8153: 1 +Line 8154: 0 +Line 8155: 0 +Line 8156: 0 +Line 8157: 0 +Line 8158: 1 +Line 8159: 0 +Line 8160: 0 +Line 8161: 1 +Line 8162: 0 +Line 8163: 0 +Line 8164: 0 +Line 8165: 1 +Line 8166: 1 +Line 8167: 0 +Line 8168: 0 +Line 8169: 0 +Line 8170: 0 +Line 8171: 1 +Line 8172: 1 +Line 8173: 0 +Line 8174: 1 +Line 8175: 1 +Line 8176: 1 +Line 8177: 1 +Line 8178: 1 +Line 8179: 1 +Line 8180: 1 +Line 8181: 1 +Line 8182: 1 +Line 8183: 1 +Line 8184: 1 +Line 8185: 1 +Line 8186: 0 +Line 8187: 1 +Line 8188: 0 +Line 8189: 0 +Line 8190: 0 +Line 8191: 1 +Line 8192: 0 +Line 8193: 1 +Line 8194: 0 +Line 8195: 0 +Line 8196: 0 +Line 8197: 1 +Line 8198: 1 +Line 8199: 0 +Line 8200: 0 +Line 8201: 0 +Line 8202: 1 +Line 8203: 1 +Line 8204: 1 +Line 8205: 0 +Line 8206: 0 +Line 8207: 0 +Line 8208: 1 +Line 8209: 1 +Line 8210: 1 +Line 8211: 1 +Line 8212: 1 +Line 8213: 1 +Line 8214: 1 +Line 8215: 1 +Line 8216: 1 +Line 8217: 1 +Line 8218: 1 +Line 8219: 0 +Line 8220: 0 +Line 8221: 0 +Line 8222: 0 +Line 8223: 1 +Line 8224: 0 +Line 8225: 1 +Line 8226: 0 +Line 8227: 0 +Line 8228: 0 +Line 8229: 1 +Line 8230: 1 +Line 8231: 0 +Line 8232: 0 +Line 8233: 1 +Line 8234: 0 +Line 8235: 0 +Line 8236: 1 +Line 8237: 0 +Line 8238: 1 +Line 8239: 0 +Line 8240: 1 +Line 8241: 1 +Line 8242: 1 +Line 8243: 1 +Line 8244: 1 +Line 8245: 1 +Line 8246: 1 +Line 8247: 1 +Line 8248: 1 +Line 8249: 1 +Line 8250: 1 +Line 8251: 1 +Line 8252: 0 +Line 8253: 0 +Line 8254: 0 +Line 8255: 1 +Line 8256: 0 +Line 8257: 1 +Line 8258: 0 +Line 8259: 0 +Line 8260: 0 +Line 8261: 1 +Line 8262: 1 +Line 8263: 0 +Line 8264: 0 +Line 8265: 1 +Line 8266: 0 +Line 8267: 1 +Line 8268: 0 +Line 8269: 0 +Line 8270: 0 +Line 8271: 0 +Line 8272: 0 +Line 8273: 0 +Line 8274: 0 +Line 8275: 0 +Line 8276: 0 +Line 8277: 0 +Line 8278: 0 +Line 8279: 0 +Line 8280: 0 +Line 8281: 0 +Line 8282: 0 +Line 8283: 0 +Line 8284: 0 +Line 8285: 0 +Line 8286: 0 +Line 8287: 0 +Line 8288: 0 +Line 8289: 1 +Line 8290: 0 +Line 8291: 0 +Line 8292: 0 +Line 8293: 1 +Line 8294: 1 +Line 8295: 0 +Line 8296: 0 +Line 8297: 1 +Line 8298: 0 +Line 8299: 0 +Line 8300: 1 +Line 8301: 0 +Line 8302: 1 +Line 8303: 0 +Line 8304: 0 +Line 8305: 0 +Line 8306: 0 +Line 8307: 0 +Line 8308: 0 +Line 8309: 0 +Line 8310: 0 +Line 8311: 0 +Line 8312: 0 +Line 8313: 0 +Line 8314: 0 +Line 8315: 0 +Line 8316: 1 +Line 8317: 1 +Line 8318: 1 +Line 8319: 1 +Line 8320: 0 +Line 8321: 1 +Line 8322: 0 +Line 8323: 0 +Line 8324: 0 +Line 8325: 1 +Line 8326: 1 +Line 8327: 0 +Line 8328: 0 +Line 8329: 0 +Line 8330: 1 +Line 8331: 1 +Line 8332: 1 +Line 8333: 0 +Line 8334: 0 +Line 8335: 0 +Line 8336: 0 +Line 8337: 0 +Line 8338: 0 +Line 8339: 0 +Line 8340: 0 +Line 8341: 0 +Line 8342: 0 +Line 8343: 0 +Line 8344: 0 +Line 8345: 0 +Line 8346: 0 +Line 8347: 1 +Line 8348: 1 +Line 8349: 1 +Line 8350: 1 +Line 8351: 1 +Line 8352: 0 +Line 8353: 1 +Line 8354: 0 +Line 8355: 0 +Line 8356: 0 +Line 8357: 1 +Line 8358: 1 +Line 8359: 0 +Line 8360: 0 +Line 8361: 0 +Line 8362: 0 +Line 8363: 1 +Line 8364: 1 +Line 8365: 0 +Line 8366: 1 +Line 8367: 1 +Line 8368: 0 +Line 8369: 0 +Line 8370: 0 +Line 8371: 0 +Line 8372: 0 +Line 8373: 0 +Line 8374: 0 +Line 8375: 0 +Line 8376: 0 +Line 8377: 0 +Line 8378: 1 +Line 8379: 0 +Line 8380: 1 +Line 8381: 1 +Line 8382: 1 +Line 8383: 1 +Line 8384: 0 +Line 8385: 1 +Line 8386: 0 +Line 8387: 0 +Line 8388: 0 +Line 8389: 1 +Line 8390: 0 +Line 8391: 1 +Line 8392: 1 +Line 8393: 1 +Line 8394: 1 +Line 8395: 1 +Line 8396: 0 +Line 8397: 0 +Line 8398: 1 +Line 8399: 0 +Line 8400: 0 +Line 8401: 0 +Line 8402: 0 +Line 8403: 0 +Line 8404: 0 +Line 8405: 0 +Line 8406: 0 +Line 8407: 0 +Line 8408: 0 +Line 8409: 0 +Line 8410: 1 +Line 8411: 1 +Line 8412: 1 +Line 8413: 1 +Line 8414: 1 +Line 8415: 0 +Line 8416: 0 +Line 8417: 1 +Line 8418: 0 +Line 8419: 0 +Line 8420: 0 +Line 8421: 1 +Line 8422: 0 +Line 8423: 1 +Line 8424: 1 +Line 8425: 0 +Line 8426: 1 +Line 8427: 1 +Line 8428: 1 +Line 8429: 1 +Line 8430: 0 +Line 8431: 1 +Line 8432: 0 +Line 8433: 0 +Line 8434: 0 +Line 8435: 0 +Line 8436: 0 +Line 8437: 0 +Line 8438: 0 +Line 8439: 0 +Line 8440: 0 +Line 8441: 1 +Line 8442: 0 +Line 8443: 0 +Line 8444: 1 +Line 8445: 1 +Line 8446: 1 +Line 8447: 0 +Line 8448: 0 +Line 8449: 1 +Line 8450: 0 +Line 8451: 0 +Line 8452: 0 +Line 8453: 1 +Line 8454: 0 +Line 8455: 1 +Line 8456: 0 +Line 8457: 1 +Line 8458: 1 +Line 8459: 1 +Line 8460: 1 +Line 8461: 1 +Line 8462: 0 +Line 8463: 1 +Line 8464: 0 +Line 8465: 0 +Line 8466: 0 +Line 8467: 0 +Line 8468: 0 +Line 8469: 0 +Line 8470: 0 +Line 8471: 0 +Line 8472: 0 +Line 8473: 1 +Line 8474: 0 +Line 8475: 1 +Line 8476: 1 +Line 8477: 1 +Line 8478: 0 +Line 8479: 1 +Line 8480: 0 +Line 8481: 1 +Line 8482: 0 +Line 8483: 0 +Line 8484: 0 +Line 8485: 1 +Line 8486: 0 +Line 8487: 1 +Line 8488: 0 +Line 8489: 0 +Line 8490: 1 +Line 8491: 1 +Line 8492: 0 +Line 8493: 0 +Line 8494: 1 +Line 8495: 0 +Line 8496: 0 +Line 8497: 0 +Line 8498: 0 +Line 8499: 0 +Line 8500: 0 +Line 8501: 0 +Line 8502: 0 +Line 8503: 0 +Line 8504: 0 +Line 8505: 1 +Line 8506: 1 +Line 8507: 0 +Line 8508: 1 +Line 8509: 1 +Line 8510: 0 +Line 8511: 0 +Line 8512: 0 +Line 8513: 1 +Line 8514: 0 +Line 8515: 0 +Line 8516: 0 +Line 8517: 1 +Line 8518: 0 +Line 8519: 0 +Line 8520: 1 +Line 8521: 1 +Line 8522: 0 +Line 8523: 1 +Line 8524: 1 +Line 8525: 0 +Line 8526: 1 +Line 8527: 1 +Line 8528: 0 +Line 8529: 0 +Line 8530: 0 +Line 8531: 0 +Line 8532: 0 +Line 8533: 0 +Line 8534: 0 +Line 8535: 0 +Line 8536: 0 +Line 8537: 1 +Line 8538: 1 +Line 8539: 1 +Line 8540: 1 +Line 8541: 1 +Line 8542: 0 +Line 8543: 0 +Line 8544: 0 +Line 8545: 1 +Line 8546: 0 +Line 8547: 0 +Line 8548: 0 +Line 8549: 1 +Line 8550: 0 +Line 8551: 0 +Line 8552: 0 +Line 8553: 1 +Line 8554: 1 +Line 8555: 1 +Line 8556: 1 +Line 8557: 0 +Line 8558: 0 +Line 8559: 0 +Line 8560: 0 +Line 8561: 0 +Line 8562: 0 +Line 8563: 0 +Line 8564: 0 +Line 8565: 0 +Line 8566: 0 +Line 8567: 0 +Line 8568: 1 +Line 8569: 0 +Line 8570: 0 +Line 8571: 0 +Line 8572: 1 +Line 8573: 0 +Line 8574: 1 +Line 8575: 1 +Line 8576: 0 +Line 8577: 1 +Line 8578: 0 +Line 8579: 0 +Line 8580: 0 +Line 8581: 1 +Line 8582: 0 +Line 8583: 0 +Line 8584: 0 +Line 8585: 0 +Line 8586: 0 +Line 8587: 0 +Line 8588: 1 +Line 8589: 0 +Line 8590: 1 +Line 8591: 1 +Line 8592: 0 +Line 8593: 0 +Line 8594: 0 +Line 8595: 0 +Line 8596: 0 +Line 8597: 0 +Line 8598: 0 +Line 8599: 0 +Line 8600: 1 +Line 8601: 0 +Line 8602: 0 +Line 8603: 1 +Line 8604: 1 +Line 8605: 0 +Line 8606: 0 +Line 8607: 1 +Line 8608: 0 +Line 8609: 1 +Line 8610: 0 +Line 8611: 0 +Line 8612: 0 +Line 8613: 0 +Line 8614: 1 +Line 8615: 1 +Line 8616: 1 +Line 8617: 0 +Line 8618: 0 +Line 8619: 1 +Line 8620: 0 +Line 8621: 0 +Line 8622: 1 +Line 8623: 1 +Line 8624: 0 +Line 8625: 0 +Line 8626: 0 +Line 8627: 0 +Line 8628: 0 +Line 8629: 0 +Line 8630: 0 +Line 8631: 0 +Line 8632: 1 +Line 8633: 0 +Line 8634: 1 +Line 8635: 0 +Line 8636: 1 +Line 8637: 0 +Line 8638: 0 +Line 8639: 0 +Line 8640: 0 +Line 8641: 1 +Line 8642: 0 +Line 8643: 0 +Line 8644: 0 +Line 8645: 0 +Line 8646: 1 +Line 8647: 1 +Line 8648: 0 +Line 8649: 0 +Line 8650: 0 +Line 8651: 1 +Line 8652: 0 +Line 8653: 0 +Line 8654: 0 +Line 8655: 0 +Line 8656: 0 +Line 8657: 0 +Line 8658: 0 +Line 8659: 0 +Line 8660: 0 +Line 8661: 0 +Line 8662: 0 +Line 8663: 0 +Line 8664: 1 +Line 8665: 0 +Line 8666: 1 +Line 8667: 1 +Line 8668: 0 +Line 8669: 1 +Line 8670: 1 +Line 8671: 0 +Line 8672: 0 +Line 8673: 1 +Line 8674: 0 +Line 8675: 0 +Line 8676: 0 +Line 8677: 0 +Line 8678: 1 +Line 8679: 0 +Line 8680: 1 +Line 8681: 0 +Line 8682: 0 +Line 8683: 0 +Line 8684: 0 +Line 8685: 0 +Line 8686: 1 +Line 8687: 0 +Line 8688: 0 +Line 8689: 0 +Line 8690: 0 +Line 8691: 0 +Line 8692: 0 +Line 8693: 0 +Line 8694: 0 +Line 8695: 0 +Line 8696: 1 +Line 8697: 1 +Line 8698: 0 +Line 8699: 0 +Line 8700: 0 +Line 8701: 1 +Line 8702: 0 +Line 8703: 1 +Line 8704: 0 +Line 8705: 1 +Line 8706: 0 +Line 8707: 0 +Line 8708: 0 +Line 8709: 0 +Line 8710: 0 +Line 8711: 1 +Line 8712: 1 +Line 8713: 1 +Line 8714: 1 +Line 8715: 0 +Line 8716: 1 +Line 8717: 0 +Line 8718: 1 +Line 8719: 0 +Line 8720: 0 +Line 8721: 0 +Line 8722: 0 +Line 8723: 0 +Line 8724: 0 +Line 8725: 0 +Line 8726: 0 +Line 8727: 0 +Line 8728: 1 +Line 8729: 1 +Line 8730: 0 +Line 8731: 1 +Line 8732: 0 +Line 8733: 0 +Line 8734: 1 +Line 8735: 0 +Line 8736: 0 +Line 8737: 1 +Line 8738: 0 +Line 8739: 0 +Line 8740: 0 +Line 8741: 0 +Line 8742: 0 +Line 8743: 1 +Line 8744: 0 +Line 8745: 1 +Line 8746: 0 +Line 8747: 0 +Line 8748: 0 +Line 8749: 1 +Line 8750: 1 +Line 8751: 1 +Line 8752: 0 +Line 8753: 0 +Line 8754: 0 +Line 8755: 0 +Line 8756: 0 +Line 8757: 0 +Line 8758: 0 +Line 8759: 0 +Line 8760: 1 +Line 8761: 1 +Line 8762: 1 +Line 8763: 0 +Line 8764: 0 +Line 8765: 0 +Line 8766: 0 +Line 8767: 0 +Line 8768: 0 +Line 8769: 1 +Line 8770: 0 +Line 8771: 0 +Line 8772: 0 +Line 8773: 0 +Line 8774: 0 +Line 8775: 0 +Line 8776: 1 +Line 8777: 0 +Line 8778: 0 +Line 8779: 1 +Line 8780: 1 +Line 8781: 0 +Line 8782: 1 +Line 8783: 1 +Line 8784: 0 +Line 8785: 0 +Line 8786: 0 +Line 8787: 0 +Line 8788: 0 +Line 8789: 0 +Line 8790: 0 +Line 8791: 0 +Line 8792: 1 +Line 8793: 1 +Line 8794: 1 +Line 8795: 0 +Line 8796: 1 +Line 8797: 1 +Line 8798: 0 +Line 8799: 1 +Line 8800: 0 +Line 8801: 0 +Line 8802: 1 +Line 8803: 1 +Line 8804: 1 +Line 8805: 1 +Line 8806: 1 +Line 8807: 1 +Line 8808: 1 +Line 8809: 1 +Line 8810: 1 +Line 8811: 0 +Line 8812: 0 +Line 8813: 1 +Line 8814: 0 +Line 8815: 0 +Line 8816: 0 +Line 8817: 0 +Line 8818: 0 +Line 8819: 0 +Line 8820: 0 +Line 8821: 0 +Line 8822: 0 +Line 8823: 0 +Line 8824: 1 +Line 8825: 1 +Line 8826: 1 +Line 8827: 1 +Line 8828: 1 +Line 8829: 0 +Line 8830: 1 +Line 8831: 0 +Line 8832: 0 +Line 8833: 0 +Line 8834: 1 +Line 8835: 1 +Line 8836: 1 +Line 8837: 1 +Line 8838: 1 +Line 8839: 1 +Line 8840: 0 +Line 8841: 0 +Line 8842: 1 +Line 8843: 0 +Line 8844: 0 +Line 8845: 1 +Line 8846: 0 +Line 8847: 0 +Line 8848: 0 +Line 8849: 0 +Line 8850: 0 +Line 8851: 0 +Line 8852: 0 +Line 8853: 0 +Line 8854: 0 +Line 8855: 1 +Line 8856: 0 +Line 8857: 0 +Line 8858: 0 +Line 8859: 0 +Line 8860: 0 +Line 8861: 1 +Line 8862: 1 +Line 8863: 1 +Line 8864: 0 +Line 8865: 0 +Line 8866: 1 +Line 8867: 1 +Line 8868: 1 +Line 8869: 1 +Line 8870: 1 +Line 8871: 0 +Line 8872: 0 +Line 8873: 1 +Line 8874: 0 +Line 8875: 1 +Line 8876: 1 +Line 8877: 0 +Line 8878: 1 +Line 8879: 1 +Line 8880: 0 +Line 8881: 0 +Line 8882: 0 +Line 8883: 0 +Line 8884: 0 +Line 8885: 0 +Line 8886: 0 +Line 8887: 1 +Line 8888: 0 +Line 8889: 0 +Line 8890: 0 +Line 8891: 1 +Line 8892: 0 +Line 8893: 0 +Line 8894: 1 +Line 8895: 1 +Line 8896: 0 +Line 8897: 0 +Line 8898: 1 +Line 8899: 1 +Line 8900: 1 +Line 8901: 1 +Line 8902: 0 +Line 8903: 1 +Line 8904: 1 +Line 8905: 0 +Line 8906: 0 +Line 8907: 0 +Line 8908: 1 +Line 8909: 0 +Line 8910: 0 +Line 8911: 1 +Line 8912: 0 +Line 8913: 0 +Line 8914: 0 +Line 8915: 0 +Line 8916: 0 +Line 8917: 0 +Line 8918: 0 +Line 8919: 1 +Line 8920: 0 +Line 8921: 0 +Line 8922: 0 +Line 8923: 1 +Line 8924: 1 +Line 8925: 1 +Line 8926: 1 +Line 8927: 1 +Line 8928: 0 +Line 8929: 0 +Line 8930: 1 +Line 8931: 1 +Line 8932: 1 +Line 8933: 1 +Line 8934: 0 +Line 8935: 0 +Line 8936: 1 +Line 8937: 0 +Line 8938: 1 +Line 8939: 0 +Line 8940: 1 +Line 8941: 1 +Line 8942: 0 +Line 8943: 1 +Line 8944: 0 +Line 8945: 0 +Line 8946: 0 +Line 8947: 0 +Line 8948: 0 +Line 8949: 0 +Line 8950: 0 +Line 8951: 1 +Line 8952: 0 +Line 8953: 0 +Line 8954: 1 +Line 8955: 0 +Line 8956: 1 +Line 8957: 0 +Line 8958: 1 +Line 8959: 1 +Line 8960: 0 +Line 8961: 0 +Line 8962: 1 +Line 8963: 1 +Line 8964: 1 +Line 8965: 0 +Line 8966: 1 +Line 8967: 1 +Line 8968: 1 +Line 8969: 1 +Line 8970: 0 +Line 8971: 0 +Line 8972: 1 +Line 8973: 0 +Line 8974: 1 +Line 8975: 0 +Line 8976: 0 +Line 8977: 0 +Line 8978: 0 +Line 8979: 0 +Line 8980: 0 +Line 8981: 0 +Line 8982: 0 +Line 8983: 1 +Line 8984: 0 +Line 8985: 0 +Line 8986: 1 +Line 8987: 1 +Line 8988: 0 +Line 8989: 1 +Line 8990: 1 +Line 8991: 0 +Line 8992: 0 +Line 8993: 0 +Line 8994: 1 +Line 8995: 1 +Line 8996: 1 +Line 8997: 0 +Line 8998: 1 +Line 8999: 0 +Line 9000: 1 +Line 9001: 1 +Line 9002: 0 +Line 9003: 1 +Line 9004: 1 +Line 9005: 1 +Line 9006: 1 +Line 9007: 0 +Line 9008: 0 +Line 9009: 0 +Line 9010: 0 +Line 9011: 0 +Line 9012: 0 +Line 9013: 0 +Line 9014: 0 +Line 9015: 1 +Line 9016: 0 +Line 9017: 1 +Line 9018: 0 +Line 9019: 0 +Line 9020: 0 +Line 9021: 0 +Line 9022: 0 +Line 9023: 1 +Line 9024: 0 +Line 9025: 0 +Line 9026: 1 +Line 9027: 1 +Line 9028: 1 +Line 9029: 0 +Line 9030: 0 +Line 9031: 1 +Line 9032: 1 +Line 9033: 1 +Line 9034: 1 +Line 9035: 0 +Line 9036: 1 +Line 9037: 0 +Line 9038: 1 +Line 9039: 0 +Line 9040: 0 +Line 9041: 0 +Line 9042: 0 +Line 9043: 0 +Line 9044: 0 +Line 9045: 0 +Line 9046: 0 +Line 9047: 1 +Line 9048: 0 +Line 9049: 1 +Line 9050: 0 +Line 9051: 0 +Line 9052: 1 +Line 9053: 0 +Line 9054: 1 +Line 9055: 1 +Line 9056: 0 +Line 9057: 0 +Line 9058: 1 +Line 9059: 1 +Line 9060: 1 +Line 9061: 0 +Line 9062: 0 +Line 9063: 0 +Line 9064: 1 +Line 9065: 1 +Line 9066: 1 +Line 9067: 0 +Line 9068: 1 +Line 9069: 1 +Line 9070: 1 +Line 9071: 1 +Line 9072: 0 +Line 9073: 0 +Line 9074: 0 +Line 9075: 0 +Line 9076: 0 +Line 9077: 0 +Line 9078: 0 +Line 9079: 1 +Line 9080: 0 +Line 9081: 1 +Line 9082: 0 +Line 9083: 1 +Line 9084: 0 +Line 9085: 1 +Line 9086: 0 +Line 9087: 1 +Line 9088: 0 +Line 9089: 0 +Line 9090: 1 +Line 9091: 1 +Line 9092: 0 +Line 9093: 1 +Line 9094: 1 +Line 9095: 1 +Line 9096: 1 +Line 9097: 1 +Line 9098: 1 +Line 9099: 0 +Line 9100: 1 +Line 9101: 1 +Line 9102: 0 +Line 9103: 0 +Line 9104: 0 +Line 9105: 0 +Line 9106: 0 +Line 9107: 0 +Line 9108: 0 +Line 9109: 0 +Line 9110: 0 +Line 9111: 1 +Line 9112: 0 +Line 9113: 1 +Line 9114: 0 +Line 9115: 1 +Line 9116: 1 +Line 9117: 1 +Line 9118: 1 +Line 9119: 1 +Line 9120: 0 +Line 9121: 0 +Line 9122: 1 +Line 9123: 1 +Line 9124: 0 +Line 9125: 1 +Line 9126: 1 +Line 9127: 0 +Line 9128: 1 +Line 9129: 1 +Line 9130: 1 +Line 9131: 0 +Line 9132: 0 +Line 9133: 0 +Line 9134: 1 +Line 9135: 0 +Line 9136: 0 +Line 9137: 0 +Line 9138: 0 +Line 9139: 0 +Line 9140: 0 +Line 9141: 0 +Line 9142: 0 +Line 9143: 1 +Line 9144: 0 +Line 9145: 1 +Line 9146: 1 +Line 9147: 0 +Line 9148: 1 +Line 9149: 0 +Line 9150: 0 +Line 9151: 0 +Line 9152: 0 +Line 9153: 0 +Line 9154: 1 +Line 9155: 1 +Line 9156: 0 +Line 9157: 1 +Line 9158: 0 +Line 9159: 1 +Line 9160: 1 +Line 9161: 1 +Line 9162: 0 +Line 9163: 1 +Line 9164: 0 +Line 9165: 0 +Line 9166: 1 +Line 9167: 0 +Line 9168: 0 +Line 9169: 0 +Line 9170: 0 +Line 9171: 0 +Line 9172: 0 +Line 9173: 0 +Line 9174: 0 +Line 9175: 1 +Line 9176: 0 +Line 9177: 1 +Line 9178: 1 +Line 9179: 1 +Line 9180: 0 +Line 9181: 0 +Line 9182: 0 +Line 9183: 1 +Line 9184: 0 +Line 9185: 0 +Line 9186: 1 +Line 9187: 1 +Line 9188: 0 +Line 9189: 1 +Line 9190: 0 +Line 9191: 0 +Line 9192: 1 +Line 9193: 0 +Line 9194: 1 +Line 9195: 1 +Line 9196: 1 +Line 9197: 0 +Line 9198: 1 +Line 9199: 1 +Line 9200: 0 +Line 9201: 0 +Line 9202: 0 +Line 9203: 0 +Line 9204: 0 +Line 9205: 0 +Line 9206: 0 +Line 9207: 1 +Line 9208: 0 +Line 9209: 1 +Line 9210: 1 +Line 9211: 1 +Line 9212: 1 +Line 9213: 0 +Line 9214: 0 +Line 9215: 1 +Line 9216: 0 +Line 9217: 0 +Line 9218: 1 +Line 9219: 1 +Line 9220: 0 +Line 9221: 0 +Line 9222: 1 +Line 9223: 1 +Line 9224: 1 +Line 9225: 0 +Line 9226: 0 +Line 9227: 1 +Line 9228: 1 +Line 9229: 1 +Line 9230: 1 +Line 9231: 1 +Line 9232: 0 +Line 9233: 0 +Line 9234: 0 +Line 9235: 0 +Line 9236: 0 +Line 9237: 0 +Line 9238: 0 +Line 9239: 1 +Line 9240: 1 +Line 9241: 0 +Line 9242: 0 +Line 9243: 0 +Line 9244: 0 +Line 9245: 0 +Line 9246: 0 +Line 9247: 0 +Line 9248: 0 +Line 9249: 0 +Line 9250: 1 +Line 9251: 1 +Line 9252: 0 +Line 9253: 0 +Line 9254: 1 +Line 9255: 0 +Line 9256: 0 +Line 9257: 1 +Line 9258: 1 +Line 9259: 1 +Line 9260: 1 +Line 9261: 1 +Line 9262: 0 +Line 9263: 1 +Line 9264: 0 +Line 9265: 0 +Line 9266: 0 +Line 9267: 0 +Line 9268: 0 +Line 9269: 0 +Line 9270: 0 +Line 9271: 1 +Line 9272: 1 +Line 9273: 0 +Line 9274: 0 +Line 9275: 0 +Line 9276: 0 +Line 9277: 1 +Line 9278: 1 +Line 9279: 1 +Line 9280: 0 +Line 9281: 0 +Line 9282: 1 +Line 9283: 1 +Line 9284: 0 +Line 9285: 0 +Line 9286: 0 +Line 9287: 1 +Line 9288: 0 +Line 9289: 1 +Line 9290: 0 +Line 9291: 1 +Line 9292: 0 +Line 9293: 1 +Line 9294: 1 +Line 9295: 0 +Line 9296: 0 +Line 9297: 0 +Line 9298: 0 +Line 9299: 0 +Line 9300: 0 +Line 9301: 0 +Line 9302: 0 +Line 9303: 1 +Line 9304: 1 +Line 9305: 0 +Line 9306: 0 +Line 9307: 0 +Line 9308: 1 +Line 9309: 1 +Line 9310: 1 +Line 9311: 0 +Line 9312: 0 +Line 9313: 0 +Line 9314: 1 +Line 9315: 1 +Line 9316: 0 +Line 9317: 0 +Line 9318: 0 +Line 9319: 0 +Line 9320: 0 +Line 9321: 0 +Line 9322: 1 +Line 9323: 0 +Line 9324: 1 +Line 9325: 0 +Line 9326: 1 +Line 9327: 1 +Line 9328: 0 +Line 9329: 0 +Line 9330: 0 +Line 9331: 0 +Line 9332: 0 +Line 9333: 0 +Line 9334: 0 +Line 9335: 1 +Line 9336: 1 +Line 9337: 0 +Line 9338: 0 +Line 9339: 1 +Line 9340: 0 +Line 9341: 1 +Line 9342: 0 +Line 9343: 0 +Line 9344: 0 +Line 9345: 0 +Line 9346: 1 +Line 9347: 0 +Line 9348: 1 +Line 9349: 1 +Line 9350: 1 +Line 9351: 0 +Line 9352: 1 +Line 9353: 1 +Line 9354: 1 +Line 9355: 1 +Line 9356: 1 +Line 9357: 0 +Line 9358: 1 +Line 9359: 1 +Line 9360: 0 +Line 9361: 0 +Line 9362: 0 +Line 9363: 0 +Line 9364: 0 +Line 9365: 0 +Line 9366: 0 +Line 9367: 1 +Line 9368: 1 +Line 9369: 0 +Line 9370: 0 +Line 9371: 1 +Line 9372: 1 +Line 9373: 0 +Line 9374: 1 +Line 9375: 0 +Line 9376: 0 +Line 9377: 0 +Line 9378: 1 +Line 9379: 0 +Line 9380: 1 +Line 9381: 1 +Line 9382: 0 +Line 9383: 1 +Line 9384: 1 +Line 9385: 1 +Line 9386: 0 +Line 9387: 0 +Line 9388: 0 +Line 9389: 1 +Line 9390: 1 +Line 9391: 1 +Line 9392: 0 +Line 9393: 0 +Line 9394: 0 +Line 9395: 0 +Line 9396: 0 +Line 9397: 0 +Line 9398: 0 +Line 9399: 1 +Line 9400: 1 +Line 9401: 0 +Line 9402: 0 +Line 9403: 1 +Line 9404: 1 +Line 9405: 1 +Line 9406: 1 +Line 9407: 1 +Line 9408: 0 +Line 9409: 0 +Line 9410: 1 +Line 9411: 0 +Line 9412: 1 +Line 9413: 1 +Line 9414: 0 +Line 9415: 0 +Line 9416: 1 +Line 9417: 0 +Line 9418: 0 +Line 9419: 0 +Line 9420: 1 +Line 9421: 1 +Line 9422: 1 +Line 9423: 1 +Line 9424: 0 +Line 9425: 0 +Line 9426: 0 +Line 9427: 0 +Line 9428: 0 +Line 9429: 0 +Line 9430: 0 +Line 9431: 1 +Line 9432: 1 +Line 9433: 0 +Line 9434: 1 +Line 9435: 0 +Line 9436: 0 +Line 9437: 0 +Line 9438: 1 +Line 9439: 1 +Line 9440: 0 +Line 9441: 0 +Line 9442: 1 +Line 9443: 0 +Line 9444: 1 +Line 9445: 0 +Line 9446: 1 +Line 9447: 1 +Line 9448: 0 +Line 9449: 1 +Line 9450: 0 +Line 9451: 1 +Line 9452: 0 +Line 9453: 1 +Line 9454: 0 +Line 9455: 1 +Line 9456: 0 +Line 9457: 0 +Line 9458: 0 +Line 9459: 0 +Line 9460: 0 +Line 9461: 0 +Line 9462: 0 +Line 9463: 1 +Line 9464: 1 +Line 9465: 0 +Line 9466: 1 +Line 9467: 0 +Line 9468: 0 +Line 9469: 1 +Line 9470: 1 +Line 9471: 1 +Line 9472: 0 +Line 9473: 0 +Line 9474: 1 +Line 9475: 0 +Line 9476: 1 +Line 9477: 0 +Line 9478: 1 +Line 9479: 0 +Line 9480: 0 +Line 9481: 0 +Line 9482: 0 +Line 9483: 1 +Line 9484: 0 +Line 9485: 1 +Line 9486: 1 +Line 9487: 1 +Line 9488: 0 +Line 9489: 0 +Line 9490: 0 +Line 9491: 0 +Line 9492: 0 +Line 9493: 0 +Line 9494: 0 +Line 9495: 1 +Line 9496: 1 +Line 9497: 0 +Line 9498: 1 +Line 9499: 0 +Line 9500: 1 +Line 9501: 0 +Line 9502: 1 +Line 9503: 0 +Line 9504: 0 +Line 9505: 0 +Line 9506: 1 +Line 9507: 0 +Line 9508: 1 +Line 9509: 0 +Line 9510: 0 +Line 9511: 0 +Line 9512: 1 +Line 9513: 1 +Line 9514: 0 +Line 9515: 1 +Line 9516: 1 +Line 9517: 0 +Line 9518: 0 +Line 9519: 0 +Line 9520: 0 +Line 9521: 0 +Line 9522: 0 +Line 9523: 0 +Line 9524: 0 +Line 9525: 0 +Line 9526: 0 +Line 9527: 1 +Line 9528: 1 +Line 9529: 0 +Line 9530: 1 +Line 9531: 0 +Line 9532: 1 +Line 9533: 1 +Line 9534: 0 +Line 9535: 1 +Line 9536: 0 +Line 9537: 0 +Line 9538: 1 +Line 9539: 0 +Line 9540: 0 +Line 9541: 1 +Line 9542: 1 +Line 9543: 1 +Line 9544: 1 +Line 9545: 0 +Line 9546: 0 +Line 9547: 1 +Line 9548: 0 +Line 9549: 1 +Line 9550: 1 +Line 9551: 0 +Line 9552: 0 +Line 9553: 0 +Line 9554: 0 +Line 9555: 0 +Line 9556: 0 +Line 9557: 0 +Line 9558: 0 +Line 9559: 1 +Line 9560: 1 +Line 9561: 0 +Line 9562: 1 +Line 9563: 1 +Line 9564: 0 +Line 9565: 0 +Line 9566: 0 +Line 9567: 0 +Line 9568: 0 +Line 9569: 0 +Line 9570: 1 +Line 9571: 0 +Line 9572: 0 +Line 9573: 1 +Line 9574: 1 +Line 9575: 0 +Line 9576: 0 +Line 9577: 1 +Line 9578: 0 +Line 9579: 1 +Line 9580: 0 +Line 9581: 0 +Line 9582: 1 +Line 9583: 1 +Line 9584: 0 +Line 9585: 0 +Line 9586: 0 +Line 9587: 0 +Line 9588: 0 +Line 9589: 0 +Line 9590: 0 +Line 9591: 1 +Line 9592: 1 +Line 9593: 0 +Line 9594: 1 +Line 9595: 1 +Line 9596: 0 +Line 9597: 0 +Line 9598: 0 +Line 9599: 1 +Line 9600: 0 +Line 9601: 0 +Line 9602: 1 +Line 9603: 0 +Line 9604: 0 +Line 9605: 1 +Line 9606: 0 +Line 9607: 1 +Line 9608: 0 +Line 9609: 0 +Line 9610: 0 +Line 9611: 0 +Line 9612: 1 +Line 9613: 1 +Line 9614: 1 +Line 9615: 1 +Line 9616: 0 +Line 9617: 0 +Line 9618: 0 +Line 9619: 0 +Line 9620: 0 +Line 9621: 0 +Line 9622: 0 +Line 9623: 1 +Line 9624: 1 +Line 9625: 0 +Line 9626: 1 +Line 9627: 1 +Line 9628: 0 +Line 9629: 0 +Line 9630: 1 +Line 9631: 0 +Line 9632: 0 +Line 9633: 0 +Line 9634: 1 +Line 9635: 0 +Line 9636: 0 +Line 9637: 0 +Line 9638: 1 +Line 9639: 1 +Line 9640: 1 +Line 9641: 1 +Line 9642: 0 +Line 9643: 0 +Line 9644: 1 +Line 9645: 0 +Line 9646: 1 +Line 9647: 0 +Line 9648: 0 +Line 9649: 0 +Line 9650: 0 +Line 9651: 0 +Line 9652: 0 +Line 9653: 0 +Line 9654: 0 +Line 9655: 1 +Line 9656: 1 +Line 9657: 0 +Line 9658: 1 +Line 9659: 1 +Line 9660: 0 +Line 9661: 0 +Line 9662: 1 +Line 9663: 1 +Line 9664: 0 +Line 9665: 0 +Line 9666: 1 +Line 9667: 0 +Line 9668: 0 +Line 9669: 0 +Line 9670: 1 +Line 9671: 0 +Line 9672: 1 +Line 9673: 0 +Line 9674: 0 +Line 9675: 0 +Line 9676: 0 +Line 9677: 1 +Line 9678: 0 +Line 9679: 1 +Line 9680: 0 +Line 9681: 0 +Line 9682: 0 +Line 9683: 0 +Line 9684: 0 +Line 9685: 0 +Line 9686: 0 +Line 9687: 1 +Line 9688: 1 +Line 9689: 0 +Line 9690: 1 +Line 9691: 1 +Line 9692: 0 +Line 9693: 0 +Line 9694: 1 +Line 9695: 1 +Line 9696: 0 +Line 9697: 0 +Line 9698: 1 +Line 9699: 0 +Line 9700: 0 +Line 9701: 0 +Line 9702: 0 +Line 9703: 1 +Line 9704: 0 +Line 9705: 1 +Line 9706: 0 +Line 9707: 0 +Line 9708: 0 +Line 9709: 0 +Line 9710: 0 +Line 9711: 0 +Line 9712: 0 +Line 9713: 0 +Line 9714: 0 +Line 9715: 0 +Line 9716: 0 +Line 9717: 0 +Line 9718: 0 +Line 9719: 1 +Line 9720: 1 +Line 9721: 0 +Line 9722: 1 +Line 9723: 1 +Line 9724: 0 +Line 9725: 0 +Line 9726: 1 +Line 9727: 0 +Line 9728: 0 +Line 9729: 0 +Line 9730: 0 +Line 9731: 1 +Line 9732: 1 +Line 9733: 1 +Line 9734: 1 +Line 9735: 1 +Line 9736: 1 +Line 9737: 1 +Line 9738: 1 +Line 9739: 1 +Line 9740: 1 +Line 9741: 1 +Line 9742: 0 +Line 9743: 0 +Line 9744: 0 +Line 9745: 0 +Line 9746: 0 +Line 9747: 0 +Line 9748: 0 +Line 9749: 0 +Line 9750: 0 +Line 9751: 1 +Line 9752: 1 +Line 9753: 0 +Line 9754: 1 +Line 9755: 1 +Line 9756: 0 +Line 9757: 0 +Line 9758: 0 +Line 9759: 1 +Line 9760: 0 +Line 9761: 0 +Line 9762: 0 +Line 9763: 1 +Line 9764: 1 +Line 9765: 1 +Line 9766: 1 +Line 9767: 0 +Line 9768: 1 +Line 9769: 0 +Line 9770: 1 +Line 9771: 1 +Line 9772: 1 +Line 9773: 0 +Line 9774: 0 +Line 9775: 1 +Line 9776: 0 +Line 9777: 0 +Line 9778: 0 +Line 9779: 0 +Line 9780: 0 +Line 9781: 0 +Line 9782: 0 +Line 9783: 1 +Line 9784: 1 +Line 9785: 0 +Line 9786: 1 +Line 9787: 1 +Line 9788: 0 +Line 9789: 0 +Line 9790: 0 +Line 9791: 0 +Line 9792: 0 +Line 9793: 0 +Line 9794: 0 +Line 9795: 1 +Line 9796: 1 +Line 9797: 1 +Line 9798: 0 +Line 9799: 1 +Line 9800: 0 +Line 9801: 1 +Line 9802: 1 +Line 9803: 1 +Line 9804: 0 +Line 9805: 1 +Line 9806: 1 +Line 9807: 1 +Line 9808: 0 +Line 9809: 0 +Line 9810: 0 +Line 9811: 0 +Line 9812: 0 +Line 9813: 0 +Line 9814: 0 +Line 9815: 1 +Line 9816: 1 +Line 9817: 0 +Line 9818: 1 +Line 9819: 0 +Line 9820: 1 +Line 9821: 1 +Line 9822: 0 +Line 9823: 1 +Line 9824: 0 +Line 9825: 0 +Line 9826: 0 +Line 9827: 1 +Line 9828: 1 +Line 9829: 1 +Line 9830: 0 +Line 9831: 0 +Line 9832: 0 +Line 9833: 0 +Line 9834: 1 +Line 9835: 1 +Line 9836: 1 +Line 9837: 0 +Line 9838: 0 +Line 9839: 0 +Line 9840: 0 +Line 9841: 0 +Line 9842: 0 +Line 9843: 0 +Line 9844: 0 +Line 9845: 0 +Line 9846: 0 +Line 9847: 1 +Line 9848: 1 +Line 9849: 0 +Line 9850: 1 +Line 9851: 0 +Line 9852: 1 +Line 9853: 0 +Line 9854: 1 +Line 9855: 0 +Line 9856: 0 +Line 9857: 0 +Line 9858: 0 +Line 9859: 1 +Line 9860: 1 +Line 9861: 0 +Line 9862: 1 +Line 9863: 0 +Line 9864: 1 +Line 9865: 1 +Line 9866: 1 +Line 9867: 1 +Line 9868: 1 +Line 9869: 0 +Line 9870: 1 +Line 9871: 0 +Line 9872: 0 +Line 9873: 0 +Line 9874: 0 +Line 9875: 0 +Line 9876: 0 +Line 9877: 0 +Line 9878: 0 +Line 9879: 1 +Line 9880: 1 +Line 9881: 0 +Line 9882: 1 +Line 9883: 0 +Line 9884: 0 +Line 9885: 1 +Line 9886: 1 +Line 9887: 1 +Line 9888: 0 +Line 9889: 0 +Line 9890: 0 +Line 9891: 1 +Line 9892: 1 +Line 9893: 0 +Line 9894: 0 +Line 9895: 1 +Line 9896: 1 +Line 9897: 1 +Line 9898: 0 +Line 9899: 0 +Line 9900: 0 +Line 9901: 0 +Line 9902: 0 +Line 9903: 0 +Line 9904: 0 +Line 9905: 0 +Line 9906: 0 +Line 9907: 0 +Line 9908: 0 +Line 9909: 0 +Line 9910: 0 +Line 9911: 1 +Line 9912: 1 +Line 9913: 0 +Line 9914: 1 +Line 9915: 0 +Line 9916: 0 +Line 9917: 0 +Line 9918: 1 +Line 9919: 1 +Line 9920: 0 +Line 9921: 0 +Line 9922: 0 +Line 9923: 1 +Line 9924: 1 +Line 9925: 0 +Line 9926: 0 +Line 9927: 0 +Line 9928: 1 +Line 9929: 0 +Line 9930: 0 +Line 9931: 0 +Line 9932: 1 +Line 9933: 0 +Line 9934: 0 +Line 9935: 0 +Line 9936: 0 +Line 9937: 0 +Line 9938: 0 +Line 9939: 0 +Line 9940: 0 +Line 9941: 0 +Line 9942: 0 +Line 9943: 1 +Line 9944: 1 +Line 9945: 0 +Line 9946: 0 +Line 9947: 1 +Line 9948: 1 +Line 9949: 1 +Line 9950: 1 +Line 9951: 1 +Line 9952: 0 +Line 9953: 0 +Line 9954: 0 +Line 9955: 1 +Line 9956: 0 +Line 9957: 1 +Line 9958: 1 +Line 9959: 1 +Line 9960: 0 +Line 9961: 1 +Line 9962: 0 +Line 9963: 1 +Line 9964: 0 +Line 9965: 1 +Line 9966: 0 +Line 9967: 0 +Line 9968: 0 +Line 9969: 0 +Line 9970: 0 +Line 9971: 0 +Line 9972: 0 +Line 9973: 0 +Line 9974: 0 +Line 9975: 1 +Line 9976: 1 +Line 9977: 0 +Line 9978: 0 +Line 9979: 1 +Line 9980: 1 +Line 9981: 0 +Line 9982: 1 +Line 9983: 0 +Line 9984: 0 +Line 9985: 0 +Line 9986: 0 +Line 9987: 1 +Line 9988: 0 +Line 9989: 1 +Line 9990: 1 +Line 9991: 0 +Line 9992: 0 +Line 9993: 0 +Line 9994: 1 +Line 9995: 0 +Line 9996: 0 +Line 9997: 1 +Line 9998: 0 +Line 9999: 0 +Line 10000: 0 +Line 10001: 0 +Line 10002: 0 +Line 10003: 0 +Line 10004: 0 +Line 10005: 0 +Line 10006: 0 +Line 10007: 1 +Line 10008: 1 +Line 10009: 0 +Line 10010: 0 +Line 10011: 1 +Line 10012: 0 +Line 10013: 1 +Line 10014: 0 +Line 10015: 0 +Line 10016: 0 +Line 10017: 0 +Line 10018: 0 +Line 10019: 1 +Line 10020: 0 +Line 10021: 1 +Line 10022: 0 +Line 10023: 0 +Line 10024: 1 +Line 10025: 1 +Line 10026: 1 +Line 10027: 1 +Line 10028: 1 +Line 10029: 0 +Line 10030: 0 +Line 10031: 1 +Line 10032: 0 +Line 10033: 0 +Line 10034: 0 +Line 10035: 0 +Line 10036: 0 +Line 10037: 0 +Line 10038: 0 +Line 10039: 1 +Line 10040: 1 +Line 10041: 0 +Line 10042: 0 +Line 10043: 0 +Line 10044: 1 +Line 10045: 1 +Line 10046: 1 +Line 10047: 0 +Line 10048: 0 +Line 10049: 0 +Line 10050: 0 +Line 10051: 1 +Line 10052: 0 +Line 10053: 0 +Line 10054: 1 +Line 10055: 1 +Line 10056: 1 +Line 10057: 1 +Line 10058: 0 +Line 10059: 1 +Line 10060: 0 +Line 10061: 0 +Line 10062: 1 +Line 10063: 0 +Line 10064: 0 +Line 10065: 0 +Line 10066: 0 +Line 10067: 0 +Line 10068: 0 +Line 10069: 0 +Line 10070: 0 +Line 10071: 1 +Line 10072: 1 +Line 10073: 0 +Line 10074: 0 +Line 10075: 0 +Line 10076: 0 +Line 10077: 1 +Line 10078: 1 +Line 10079: 1 +Line 10080: 0 +Line 10081: 0 +Line 10082: 0 +Line 10083: 1 +Line 10084: 0 +Line 10085: 0 +Line 10086: 1 +Line 10087: 0 +Line 10088: 1 +Line 10089: 0 +Line 10090: 1 +Line 10091: 1 +Line 10092: 0 +Line 10093: 0 +Line 10094: 0 +Line 10095: 0 +Line 10096: 0 +Line 10097: 0 +Line 10098: 0 +Line 10099: 0 +Line 10100: 0 +Line 10101: 0 +Line 10102: 0 +Line 10103: 1 +Line 10104: 1 +Line 10105: 0 +Line 10106: 0 +Line 10107: 0 +Line 10108: 0 +Line 10109: 0 +Line 10110: 0 +Line 10111: 0 +Line 10112: 0 +Line 10113: 0 +Line 10114: 0 +Line 10115: 1 +Line 10116: 0 +Line 10117: 0 +Line 10118: 0 +Line 10119: 1 +Line 10120: 1 +Line 10121: 0 +Line 10122: 0 +Line 10123: 1 +Line 10124: 0 +Line 10125: 0 +Line 10126: 1 +Line 10127: 1 +Line 10128: 0 +Line 10129: 0 +Line 10130: 0 +Line 10131: 0 +Line 10132: 0 +Line 10133: 0 +Line 10134: 0 +Line 10135: 1 +Line 10136: 0 +Line 10137: 1 +Line 10138: 1 +Line 10139: 1 +Line 10140: 1 +Line 10141: 0 +Line 10142: 0 +Line 10143: 1 +Line 10144: 0 +Line 10145: 0 +Line 10146: 0 +Line 10147: 1 +Line 10148: 0 +Line 10149: 0 +Line 10150: 0 +Line 10151: 0 +Line 10152: 0 +Line 10153: 1 +Line 10154: 1 +Line 10155: 1 +Line 10156: 1 +Line 10157: 1 +Line 10158: 0 +Line 10159: 1 +Line 10160: 0 +Line 10161: 0 +Line 10162: 0 +Line 10163: 0 +Line 10164: 0 +Line 10165: 0 +Line 10166: 0 +Line 10167: 1 +Line 10168: 0 +Line 10169: 1 +Line 10170: 1 +Line 10171: 1 +Line 10172: 0 +Line 10173: 0 +Line 10174: 0 +Line 10175: 1 +Line 10176: 0 +Line 10177: 0 +Line 10178: 0 +Line 10179: 0 +Line 10180: 1 +Line 10181: 1 +Line 10182: 1 +Line 10183: 1 +Line 10184: 0 +Line 10185: 1 +Line 10186: 1 +Line 10187: 0 +Line 10188: 1 +Line 10189: 1 +Line 10190: 0 +Line 10191: 1 +Line 10192: 0 +Line 10193: 0 +Line 10194: 0 +Line 10195: 0 +Line 10196: 0 +Line 10197: 0 +Line 10198: 0 +Line 10199: 1 +Line 10200: 0 +Line 10201: 1 +Line 10202: 1 +Line 10203: 0 +Line 10204: 1 +Line 10205: 0 +Line 10206: 0 +Line 10207: 0 +Line 10208: 0 +Line 10209: 0 +Line 10210: 0 +Line 10211: 0 +Line 10212: 1 +Line 10213: 1 +Line 10214: 1 +Line 10215: 0 +Line 10216: 0 +Line 10217: 1 +Line 10218: 1 +Line 10219: 0 +Line 10220: 0 +Line 10221: 0 +Line 10222: 1 +Line 10223: 1 +Line 10224: 0 +Line 10225: 0 +Line 10226: 0 +Line 10227: 0 +Line 10228: 0 +Line 10229: 0 +Line 10230: 0 +Line 10231: 1 +Line 10232: 0 +Line 10233: 1 +Line 10234: 0 +Line 10235: 1 +Line 10236: 1 +Line 10237: 1 +Line 10238: 1 +Line 10239: 1 +Line 10240: 0 +Line 10241: 0 +Line 10242: 0 +Line 10243: 0 +Line 10244: 1 +Line 10245: 1 +Line 10246: 0 +Line 10247: 1 +Line 10248: 0 +Line 10249: 1 +Line 10250: 1 +Line 10251: 0 +Line 10252: 0 +Line 10253: 0 +Line 10254: 0 +Line 10255: 0 +Line 10256: 0 +Line 10257: 0 +Line 10258: 0 +Line 10259: 0 +Line 10260: 0 +Line 10261: 0 +Line 10262: 0 +Line 10263: 1 +Line 10264: 0 +Line 10265: 1 +Line 10266: 0 +Line 10267: 1 +Line 10268: 0 +Line 10269: 1 +Line 10270: 0 +Line 10271: 1 +Line 10272: 0 +Line 10273: 0 +Line 10274: 0 +Line 10275: 0 +Line 10276: 1 +Line 10277: 1 +Line 10278: 0 +Line 10279: 0 +Line 10280: 0 +Line 10281: 1 +Line 10282: 1 +Line 10283: 0 +Line 10284: 0 +Line 10285: 1 +Line 10286: 0 +Line 10287: 1 +Line 10288: 0 +Line 10289: 0 +Line 10290: 0 +Line 10291: 0 +Line 10292: 0 +Line 10293: 0 +Line 10294: 0 +Line 10295: 1 +Line 10296: 0 +Line 10297: 1 +Line 10298: 0 +Line 10299: 0 +Line 10300: 1 +Line 10301: 0 +Line 10302: 1 +Line 10303: 1 +Line 10304: 0 +Line 10305: 0 +Line 10306: 0 +Line 10307: 0 +Line 10308: 1 +Line 10309: 0 +Line 10310: 1 +Line 10311: 1 +Line 10312: 0 +Line 10313: 1 +Line 10314: 1 +Line 10315: 1 +Line 10316: 0 +Line 10317: 0 +Line 10318: 0 +Line 10319: 1 +Line 10320: 0 +Line 10321: 0 +Line 10322: 0 +Line 10323: 0 +Line 10324: 0 +Line 10325: 0 +Line 10326: 0 +Line 10327: 1 +Line 10328: 0 +Line 10329: 1 +Line 10330: 0 +Line 10331: 0 +Line 10332: 0 +Line 10333: 0 +Line 10334: 0 +Line 10335: 1 +Line 10336: 0 +Line 10337: 0 +Line 10338: 0 +Line 10339: 0 +Line 10340: 1 +Line 10341: 0 +Line 10342: 1 +Line 10343: 0 +Line 10344: 1 +Line 10345: 0 +Line 10346: 0 +Line 10347: 0 +Line 10348: 0 +Line 10349: 1 +Line 10350: 0 +Line 10351: 1 +Line 10352: 0 +Line 10353: 0 +Line 10354: 0 +Line 10355: 0 +Line 10356: 0 +Line 10357: 0 +Line 10358: 0 +Line 10359: 1 +Line 10360: 0 +Line 10361: 0 +Line 10362: 1 +Line 10363: 1 +Line 10364: 0 +Line 10365: 1 +Line 10366: 1 +Line 10367: 0 +Line 10368: 0 +Line 10369: 0 +Line 10370: 0 +Line 10371: 0 +Line 10372: 1 +Line 10373: 0 +Line 10374: 0 +Line 10375: 1 +Line 10376: 1 +Line 10377: 0 +Line 10378: 1 +Line 10379: 0 +Line 10380: 0 +Line 10381: 0 +Line 10382: 1 +Line 10383: 0 +Line 10384: 0 +Line 10385: 0 +Line 10386: 0 +Line 10387: 0 +Line 10388: 0 +Line 10389: 0 +Line 10390: 0 +Line 10391: 1 +Line 10392: 0 +Line 10393: 0 +Line 10394: 1 +Line 10395: 0 +Line 10396: 1 +Line 10397: 0 +Line 10398: 1 +Line 10399: 1 +Line 10400: 0 +Line 10401: 0 +Line 10402: 0 +Line 10403: 0 +Line 10404: 1 +Line 10405: 0 +Line 10406: 0 +Line 10407: 0 +Line 10408: 1 +Line 10409: 1 +Line 10410: 0 +Line 10411: 0 +Line 10412: 0 +Line 10413: 1 +Line 10414: 1 +Line 10415: 0 +Line 10416: 0 +Line 10417: 0 +Line 10418: 0 +Line 10419: 0 +Line 10420: 0 +Line 10421: 0 +Line 10422: 0 +Line 10423: 1 +Line 10424: 0 +Line 10425: 0 +Line 10426: 0 +Line 10427: 1 +Line 10428: 1 +Line 10429: 1 +Line 10430: 1 +Line 10431: 1 +Line 10432: 0 +Line 10433: 0 +Line 10434: 0 +Line 10435: 0 +Line 10436: 0 +Line 10437: 1 +Line 10438: 1 +Line 10439: 1 +Line 10440: 1 +Line 10441: 1 +Line 10442: 1 +Line 10443: 1 +Line 10444: 0 +Line 10445: 1 +Line 10446: 0 +Line 10447: 0 +Line 10448: 0 +Line 10449: 0 +Line 10450: 0 +Line 10451: 0 +Line 10452: 0 +Line 10453: 0 +Line 10454: 0 +Line 10455: 1 +Line 10456: 0 +Line 10457: 0 +Line 10458: 0 +Line 10459: 1 +Line 10460: 0 +Line 10461: 0 +Line 10462: 1 +Line 10463: 1 +Line 10464: 0 +Line 10465: 0 +Line 10466: 0 +Line 10467: 0 +Line 10468: 0 +Line 10469: 1 +Line 10470: 1 +Line 10471: 1 +Line 10472: 0 +Line 10473: 0 +Line 10474: 1 +Line 10475: 0 +Line 10476: 1 +Line 10477: 0 +Line 10478: 1 +Line 10479: 1 +Line 10480: 0 +Line 10481: 0 +Line 10482: 0 +Line 10483: 0 +Line 10484: 0 +Line 10485: 0 +Line 10486: 0 +Line 10487: 1 +Line 10488: 0 +Line 10489: 0 +Line 10490: 0 +Line 10491: 0 +Line 10492: 0 +Line 10493: 1 +Line 10494: 1 +Line 10495: 1 +Line 10496: 0 +Line 10497: 0 +Line 10498: 0 +Line 10499: 0 +Line 10500: 0 +Line 10501: 1 +Line 10502: 1 +Line 10503: 0 +Line 10504: 0 +Line 10505: 1 +Line 10506: 1 +Line 10507: 0 +Line 10508: 1 +Line 10509: 0 +Line 10510: 1 +Line 10511: 1 +Line 10512: 0 +Line 10513: 0 +Line 10514: 0 +Line 10515: 0 +Line 10516: 0 +Line 10517: 0 +Line 10518: 0 +Line 10519: 0 +Line 10520: 1 +Line 10521: 1 +Line 10522: 1 +Line 10523: 1 +Line 10524: 1 +Line 10525: 0 +Line 10526: 1 +Line 10527: 0 +Line 10528: 0 +Line 10529: 0 +Line 10530: 0 +Line 10531: 0 +Line 10532: 0 +Line 10533: 1 +Line 10534: 0 +Line 10535: 1 +Line 10536: 1 +Line 10537: 0 +Line 10538: 1 +Line 10539: 1 +Line 10540: 0 +Line 10541: 1 +Line 10542: 0 +Line 10543: 0 +Line 10544: 0 +Line 10545: 0 +Line 10546: 0 +Line 10547: 0 +Line 10548: 0 +Line 10549: 0 +Line 10550: 0 +Line 10551: 0 +Line 10552: 1 +Line 10553: 1 +Line 10554: 1 +Line 10555: 0 +Line 10556: 1 +Line 10557: 1 +Line 10558: 0 +Line 10559: 1 +Line 10560: 0 +Line 10561: 0 +Line 10562: 0 +Line 10563: 0 +Line 10564: 0 +Line 10565: 1 +Line 10566: 0 +Line 10567: 1 +Line 10568: 0 +Line 10569: 0 +Line 10570: 0 +Line 10571: 0 +Line 10572: 1 +Line 10573: 0 +Line 10574: 0 +Line 10575: 0 +Line 10576: 0 +Line 10577: 0 +Line 10578: 0 +Line 10579: 0 +Line 10580: 0 +Line 10581: 0 +Line 10582: 0 +Line 10583: 0 +Line 10584: 1 +Line 10585: 1 +Line 10586: 1 +Line 10587: 0 +Line 10588: 0 +Line 10589: 0 +Line 10590: 0 +Line 10591: 0 +Line 10592: 0 +Line 10593: 0 +Line 10594: 0 +Line 10595: 0 +Line 10596: 0 +Line 10597: 1 +Line 10598: 0 +Line 10599: 0 +Line 10600: 0 +Line 10601: 1 +Line 10602: 1 +Line 10603: 0 +Line 10604: 0 +Line 10605: 1 +Line 10606: 0 +Line 10607: 1 +Line 10608: 0 +Line 10609: 0 +Line 10610: 0 +Line 10611: 0 +Line 10612: 0 +Line 10613: 0 +Line 10614: 0 +Line 10615: 0 +Line 10616: 1 +Line 10617: 1 +Line 10618: 0 +Line 10619: 1 +Line 10620: 0 +Line 10621: 0 +Line 10622: 1 +Line 10623: 0 +Line 10624: 0 +Line 10625: 0 +Line 10626: 0 +Line 10627: 0 +Line 10628: 0 +Line 10629: 0 +Line 10630: 1 +Line 10631: 1 +Line 10632: 1 +Line 10633: 1 +Line 10634: 0 +Line 10635: 0 +Line 10636: 1 +Line 10637: 1 +Line 10638: 0 +Line 10639: 1 +Line 10640: 0 +Line 10641: 0 +Line 10642: 0 +Line 10643: 0 +Line 10644: 0 +Line 10645: 0 +Line 10646: 0 +Line 10647: 0 +Line 10648: 1 +Line 10649: 1 +Line 10650: 0 +Line 10651: 0 +Line 10652: 0 +Line 10653: 1 +Line 10654: 0 +Line 10655: 1 +Line 10656: 0 +Line 10657: 0 +Line 10658: 0 +Line 10659: 0 +Line 10660: 0 +Line 10661: 0 +Line 10662: 1 +Line 10663: 1 +Line 10664: 0 +Line 10665: 0 +Line 10666: 1 +Line 10667: 1 +Line 10668: 1 +Line 10669: 1 +Line 10670: 1 +Line 10671: 1 +Line 10672: 0 +Line 10673: 0 +Line 10674: 0 +Line 10675: 0 +Line 10676: 0 +Line 10677: 0 +Line 10678: 0 +Line 10679: 0 +Line 10680: 1 +Line 10681: 0 +Line 10682: 1 +Line 10683: 1 +Line 10684: 0 +Line 10685: 1 +Line 10686: 1 +Line 10687: 0 +Line 10688: 0 +Line 10689: 0 +Line 10690: 0 +Line 10691: 0 +Line 10692: 0 +Line 10693: 0 +Line 10694: 1 +Line 10695: 0 +Line 10696: 1 +Line 10697: 0 +Line 10698: 1 +Line 10699: 1 +Line 10700: 1 +Line 10701: 1 +Line 10702: 0 +Line 10703: 0 +Line 10704: 0 +Line 10705: 0 +Line 10706: 0 +Line 10707: 0 +Line 10708: 0 +Line 10709: 0 +Line 10710: 0 +Line 10711: 0 +Line 10712: 1 +Line 10713: 0 +Line 10714: 1 +Line 10715: 0 +Line 10716: 1 +Line 10717: 0 +Line 10718: 0 +Line 10719: 0 +Line 10720: 0 +Line 10721: 0 +Line 10722: 0 +Line 10723: 0 +Line 10724: 0 +Line 10725: 0 +Line 10726: 1 +Line 10727: 0 +Line 10728: 0 +Line 10729: 1 +Line 10730: 0 +Line 10731: 0 +Line 10732: 0 +Line 10733: 1 +Line 10734: 0 +Line 10735: 0 +Line 10736: 0 +Line 10737: 0 +Line 10738: 0 +Line 10739: 0 +Line 10740: 0 +Line 10741: 0 +Line 10742: 0 +Line 10743: 0 +Line 10744: 1 +Line 10745: 0 +Line 10746: 0 +Line 10747: 1 +Line 10748: 1 +Line 10749: 0 +Line 10750: 0 +Line 10751: 1 +Line 10752: 0 +Line 10753: 0 +Line 10754: 0 +Line 10755: 0 +Line 10756: 0 +Line 10757: 0 +Line 10758: 0 +Line 10759: 1 +Line 10760: 1 +Line 10761: 1 +Line 10762: 0 +Line 10763: 1 +Line 10764: 0 +Line 10765: 1 +Line 10766: 1 +Line 10767: 1 +Line 10768: 0 +Line 10769: 0 +Line 10770: 0 +Line 10771: 0 +Line 10772: 0 +Line 10773: 0 +Line 10774: 0 +Line 10775: 0 +Line 10776: 1 +Line 10777: 0 +Line 10778: 0 +Line 10779: 0 +Line 10780: 1 +Line 10781: 0 +Line 10782: 1 +Line 10783: 1 +Line 10784: 0 +Line 10785: 0 +Line 10786: 0 +Line 10787: 0 +Line 10788: 0 +Line 10789: 0 +Line 10790: 0 +Line 10791: 1 +Line 10792: 0 +Line 10793: 1 +Line 10794: 1 +Line 10795: 1 +Line 10796: 0 +Line 10797: 1 +Line 10798: 0 +Line 10799: 0 +Line 10800: 0 +Line 10801: 0 +Line 10802: 0 +Line 10803: 0 +Line 10804: 0 +Line 10805: 0 +Line 10806: 0 +Line 10807: 0 +Line 10808: 0 +Line 10809: 1 +Line 10810: 1 +Line 10811: 1 +Line 10812: 1 +Line 10813: 1 +Line 10814: 0 +Line 10815: 0 +Line 10816: 0 +Line 10817: 0 +Line 10818: 0 +Line 10819: 0 +Line 10820: 0 +Line 10821: 0 +Line 10822: 0 +Line 10823: 1 +Line 10824: 0 +Line 10825: 0 +Line 10826: 0 +Line 10827: 1 +Line 10828: 1 +Line 10829: 1 +Line 10830: 0 +Line 10831: 1 +Line 10832: 0 +Line 10833: 0 +Line 10834: 0 +Line 10835: 0 +Line 10836: 0 +Line 10837: 0 +Line 10838: 0 +Line 10839: 0 +Line 10840: 0 +Line 10841: 1 +Line 10842: 1 +Line 10843: 0 +Line 10844: 1 +Line 10845: 1 +Line 10846: 0 +Line 10847: 0 +Line 10848: 0 +Line 10849: 0 +Line 10850: 0 +Line 10851: 0 +Line 10852: 0 +Line 10853: 0 +Line 10854: 0 +Line 10855: 0 +Line 10856: 1 +Line 10857: 1 +Line 10858: 0 +Line 10859: 1 +Line 10860: 0 +Line 10861: 0 +Line 10862: 1 +Line 10863: 0 +Line 10864: 0 +Line 10865: 0 +Line 10866: 0 +Line 10867: 0 +Line 10868: 0 +Line 10869: 0 +Line 10870: 0 +Line 10871: 0 +Line 10872: 0 +Line 10873: 1 +Line 10874: 0 +Line 10875: 1 +Line 10876: 1 +Line 10877: 1 +Line 10878: 0 +Line 10879: 1 +Line 10880: 0 +Line 10881: 0 +Line 10882: 0 +Line 10883: 0 +Line 10884: 0 +Line 10885: 0 +Line 10886: 0 +Line 10887: 0 +Line 10888: 1 +Line 10889: 0 +Line 10890: 0 +Line 10891: 1 +Line 10892: 0 +Line 10893: 0 +Line 10894: 1 +Line 10895: 0 +Line 10896: 0 +Line 10897: 0 +Line 10898: 0 +Line 10899: 0 +Line 10900: 0 +Line 10901: 0 +Line 10902: 0 +Line 10903: 0 +Line 10904: 0 +Line 10905: 1 +Line 10906: 0 +Line 10907: 0 +Line 10908: 1 +Line 10909: 1 +Line 10910: 1 +Line 10911: 0 +Line 10912: 0 +Line 10913: 0 +Line 10914: 0 +Line 10915: 0 +Line 10916: 0 +Line 10917: 0 +Line 10918: 0 +Line 10919: 0 +Line 10920: 0 +Line 10921: 1 +Line 10922: 0 +Line 10923: 1 +Line 10924: 1 +Line 10925: 1 +Line 10926: 0 +Line 10927: 1 +Line 10928: 0 +Line 10929: 0 +Line 10930: 0 +Line 10931: 0 +Line 10932: 0 +Line 10933: 0 +Line 10934: 0 +Line 10935: 0 +Line 10936: 0 +Line 10937: 0 +Line 10938: 1 +Line 10939: 1 +Line 10940: 1 +Line 10941: 1 +Line 10942: 1 +Line 10943: 0 +Line 10944: 0 +Line 10945: 0 +Line 10946: 0 +Line 10947: 0 +Line 10948: 0 +Line 10949: 0 +Line 10950: 0 +Line 10951: 0 +Line 10952: 0 +Line 10953: 0 +Line 10954: 1 +Line 10955: 1 +Line 10956: 0 +Line 10957: 1 +Line 10958: 0 +Line 10959: 0 +Line 10960: 0 +Line 10961: 0 +Line 10962: 0 +Line 10963: 0 +Line 10964: 0 +Line 10965: 0 +Line 10966: 0 +Line 10967: 0 +Line 10968: 0 +Line 10969: 0 +Line 10970: 1 +Line 10971: 0 +Line 10972: 1 +Line 10973: 1 +Line 10974: 1 +Line 10975: 1 +Line 10976: 0 +Line 10977: 0 +Line 10978: 0 +Line 10979: 0 +Line 10980: 0 +Line 10981: 0 +Line 10982: 0 +Line 10983: 0 +Line 10984: 0 +Line 10985: 0 +Line 10986: 0 +Line 10987: 1 +Line 10988: 0 +Line 10989: 1 +Line 10990: 1 +Line 10991: 1 +Line 10992: 0 +Line 10993: 0 +Line 10994: 0 +Line 10995: 0 +Line 10996: 0 +Line 10997: 0 +Line 10998: 0 +Line 10999: 0 +Line 11000: 0 +Line 11001: 0 +Line 11002: 0 +Line 11003: 1 +Line 11004: 1 +Line 11005: 1 +Line 11006: 1 +Line 11007: 1 +Line 11008: 0 +Line 11009: 0 +Line 11010: 0 +Line 11011: 0 +Line 11012: 0 +Line 11013: 0 +Line 11014: 0 +Line 11015: 0 +Line 11016: 0 +Line 11017: 0 +Line 11018: 0 +Line 11019: 0 +Line 11020: 0 +Line 11021: 1 +Line 11022: 0 +Line 11023: 1 +Line 11024: 0 +Line 11025: 0 +Line 11026: 0 +Line 11027: 0 +Line 11028: 0 +Line 11029: 0 +Line 11030: 0 +Line 11031: 0 +Line 11032: 0 +Line 11033: 0 +Line 11034: 0 +Line 11035: 0 +Line 11036: 1 +Line 11037: 1 +Line 11038: 1 +Line 11039: 1 +Line 11040: 0 +Line 11041: 0 +Line 11042: 0 +Line 11043: 0 +Line 11044: 0 +Line 11045: 0 +Line 11046: 0 +Line 11047: 0 +Line 11048: 0 +Line 11049: 0 +Line 11050: 0 +Line 11051: 0 +Line 11052: 0 +Line 11053: 0 +Line 11054: 0 +Line 11055: 0 +Line 11056: 0 +Line 11057: 0 +Line 11058: 0 +Line 11059: 0 +Line 11060: 0 +Line 11061: 0 +Line 11062: 0 +Line 11063: 0 +Line 11064: 0 +Line 11065: 0 +Line 11066: 0 +Line 11067: 0 +Line 11068: 0 +Line 11069: 0 +Line 11070: 0 +Line 11071: 0 +Line 11072: 0 +Line 11073: 1 +Line 11074: 0 +Line 11075: 0 +Line 11076: 0 +Line 11077: 1 +Line 11078: 1 +Line 11079: 0 +Line 11080: 0 +Line 11081: 1 +Line 11082: 0 +Line 11083: 1 +Line 11084: 0 +Line 11085: 0 +Line 11086: 0 +Line 11087: 0 +Line 11088: 0 +Line 11089: 0 +Line 11090: 0 +Line 11091: 0 +Line 11092: 0 +Line 11093: 0 +Line 11094: 0 +Line 11095: 0 +Line 11096: 0 +Line 11097: 0 +Line 11098: 0 +Line 11099: 0 +Line 11100: 0 +Line 11101: 0 +Line 11102: 0 +Line 11103: 0 +Line 11104: 0 +Line 11105: 0 +Line 11106: 0 +Line 11107: 0 +Line 11108: 0 +Line 11109: 0 +Line 11110: 0 +Line 11111: 0 +Line 11112: 0 +Line 11113: 0 +Line 11114: 0 +Line 11115: 0 +Line 11116: 0 +Line 11117: 0 +Line 11118: 0 +Line 11119: 0 +Line 11120: 0 +Line 11121: 0 +Line 11122: 0 +Line 11123: 0 +Line 11124: 0 +Line 11125: 0 +Line 11126: 0 +Line 11127: 0 +Line 11128: 0 +Line 11129: 0 +Line 11130: 0 +Line 11131: 0 +Line 11132: 0 +Line 11133: 0 +Line 11134: 0 +Line 11135: 0 +Line 11136: 0 +Line 11137: 0 +Line 11138: 0 +Line 11139: 0 +Line 11140: 0 +Line 11141: 0 +Line 11142: 0 +Line 11143: 0 +Line 11144: 0 +Line 11145: 0 +Line 11146: 0 +Line 11147: 0 +Line 11148: 0 +Line 11149: 0 +Line 11150: 0 +Line 11151: 0 +Line 11152: 0 +Line 11153: 0 +Line 11154: 0 +Line 11155: 0 +Line 11156: 0 +Line 11157: 0 +Line 11158: 0 +Line 11159: 0 +Line 11160: 0 +Line 11161: 0 +Line 11162: 0 +Line 11163: 0 +Line 11164: 0 +Line 11165: 0 +Line 11166: 0 +Line 11167: 0 +Line 11168: 0 +Line 11169: 0 +Line 11170: 0 +Line 11171: 0 +Line 11172: 1 +Line 11173: 0 +Line 11174: 0 +Line 11175: 0 +Line 11176: 0 +Line 11177: 0 +Line 11178: 0 +Line 11179: 0 +Line 11180: 1 +Line 11181: 0 +Line 11182: 1 +Line 11183: 0 +Line 11184: 0 +Line 11185: 0 +Line 11186: 0 +Line 11187: 0 +Line 11188: 0 +Line 11189: 0 +Line 11190: 0 +Line 11191: 0 +Line 11192: 0 +Line 11193: 0 +Line 11194: 0 +Line 11195: 0 +Line 11196: 0 +Line 11197: 0 +Line 11198: 0 +Line 11199: 0 +Line 11200: 0 +Line 11201: 0 +Line 11202: 0 +Line 11203: 0 +Line 11204: 1 +Line 11205: 1 +Line 11206: 1 +Line 11207: 1 +Line 11208: 1 +Line 11209: 1 +Line 11210: 1 +Line 11211: 0 +Line 11212: 0 +Line 11213: 1 +Line 11214: 1 +Line 11215: 1 +Line 11216: 0 +Line 11217: 0 +Line 11218: 0 +Line 11219: 0 +Line 11220: 0 +Line 11221: 0 +Line 11222: 0 +Line 11223: 0 +Line 11224: 0 +Line 11225: 0 +Line 11226: 0 +Line 11227: 0 +Line 11228: 0 +Line 11229: 0 +Line 11230: 0 +Line 11231: 0 +Line 11232: 0 +Line 11233: 0 +Line 11234: 0 +Line 11235: 1 +Line 11236: 0 +Line 11237: 1 +Line 11238: 1 +Line 11239: 1 +Line 11240: 0 +Line 11241: 1 +Line 11242: 1 +Line 11243: 0 +Line 11244: 1 +Line 11245: 1 +Line 11246: 0 +Line 11247: 0 +Line 11248: 0 +Line 11249: 0 +Line 11250: 0 +Line 11251: 0 +Line 11252: 0 +Line 11253: 0 +Line 11254: 0 +Line 11255: 0 +Line 11256: 0 +Line 11257: 0 +Line 11258: 0 +Line 11259: 0 +Line 11260: 0 +Line 11261: 0 +Line 11262: 0 +Line 11263: 0 +Line 11264: 0 +Line 11265: 0 +Line 11266: 0 +Line 11267: 1 +Line 11268: 1 +Line 11269: 1 +Line 11270: 1 +Line 11271: 0 +Line 11272: 0 +Line 11273: 1 +Line 11274: 1 +Line 11275: 1 +Line 11276: 0 +Line 11277: 0 +Line 11278: 0 +Line 11279: 1 +Line 11280: 0 +Line 11281: 0 +Line 11282: 0 +Line 11283: 0 +Line 11284: 0 +Line 11285: 0 +Line 11286: 0 +Line 11287: 0 +Line 11288: 0 +Line 11289: 0 +Line 11290: 0 +Line 11291: 0 +Line 11292: 0 +Line 11293: 0 +Line 11294: 0 +Line 11295: 0 +Line 11296: 0 +Line 11297: 0 +Line 11298: 1 +Line 11299: 0 +Line 11300: 0 +Line 11301: 1 +Line 11302: 0 +Line 11303: 0 +Line 11304: 1 +Line 11305: 1 +Line 11306: 0 +Line 11307: 1 +Line 11308: 0 +Line 11309: 1 +Line 11310: 0 +Line 11311: 1 +Line 11312: 0 +Line 11313: 0 +Line 11314: 0 +Line 11315: 0 +Line 11316: 0 +Line 11317: 0 +Line 11318: 0 +Line 11319: 0 +Line 11320: 0 +Line 11321: 0 +Line 11322: 0 +Line 11323: 0 +Line 11324: 0 +Line 11325: 0 +Line 11326: 0 +Line 11327: 0 +Line 11328: 0 +Line 11329: 0 +Line 11330: 1 +Line 11331: 0 +Line 11332: 1 +Line 11333: 0 +Line 11334: 1 +Line 11335: 0 +Line 11336: 0 +Line 11337: 1 +Line 11338: 1 +Line 11339: 1 +Line 11340: 1 +Line 11341: 1 +Line 11342: 1 +Line 11343: 0 +Line 11344: 0 +Line 11345: 0 +Line 11346: 0 +Line 11347: 0 +Line 11348: 0 +Line 11349: 0 +Line 11350: 0 +Line 11351: 0 +Line 11352: 0 +Line 11353: 0 +Line 11354: 0 +Line 11355: 0 +Line 11356: 0 +Line 11357: 0 +Line 11358: 0 +Line 11359: 0 +Line 11360: 0 +Line 11361: 0 +Line 11362: 1 +Line 11363: 0 +Line 11364: 1 +Line 11365: 1 +Line 11366: 1 +Line 11367: 1 +Line 11368: 0 +Line 11369: 1 +Line 11370: 0 +Line 11371: 1 +Line 11372: 1 +Line 11373: 0 +Line 11374: 0 +Line 11375: 1 +Line 11376: 0 +Line 11377: 0 +Line 11378: 0 +Line 11379: 0 +Line 11380: 0 +Line 11381: 0 +Line 11382: 0 +Line 11383: 0 +Line 11384: 0 +Line 11385: 0 +Line 11386: 0 +Line 11387: 0 +Line 11388: 0 +Line 11389: 0 +Line 11390: 0 +Line 11391: 0 +Line 11392: 0 +Line 11393: 0 +Line 11394: 1 +Line 11395: 1 +Line 11396: 0 +Line 11397: 0 +Line 11398: 1 +Line 11399: 1 +Line 11400: 0 +Line 11401: 1 +Line 11402: 0 +Line 11403: 1 +Line 11404: 1 +Line 11405: 1 +Line 11406: 1 +Line 11407: 1 +Line 11408: 0 +Line 11409: 0 +Line 11410: 0 +Line 11411: 0 +Line 11412: 0 +Line 11413: 0 +Line 11414: 0 +Line 11415: 0 +Line 11416: 0 +Line 11417: 0 +Line 11418: 0 +Line 11419: 0 +Line 11420: 0 +Line 11421: 0 +Line 11422: 0 +Line 11423: 0 +Line 11424: 0 +Line 11425: 0 +Line 11426: 1 +Line 11427: 1 +Line 11428: 0 +Line 11429: 1 +Line 11430: 1 +Line 11431: 0 +Line 11432: 1 +Line 11433: 0 +Line 11434: 0 +Line 11435: 1 +Line 11436: 0 +Line 11437: 0 +Line 11438: 0 +Line 11439: 0 +Line 11440: 0 +Line 11441: 0 +Line 11442: 0 +Line 11443: 0 +Line 11444: 0 +Line 11445: 0 +Line 11446: 0 +Line 11447: 0 +Line 11448: 0 +Line 11449: 0 +Line 11450: 0 +Line 11451: 0 +Line 11452: 0 +Line 11453: 0 +Line 11454: 0 +Line 11455: 0 +Line 11456: 0 +Line 11457: 0 +Line 11458: 1 +Line 11459: 1 +Line 11460: 1 +Line 11461: 0 +Line 11462: 0 +Line 11463: 0 +Line 11464: 1 +Line 11465: 1 +Line 11466: 1 +Line 11467: 1 +Line 11468: 0 +Line 11469: 0 +Line 11470: 1 +Line 11471: 0 +Line 11472: 0 +Line 11473: 0 +Line 11474: 0 +Line 11475: 0 +Line 11476: 0 +Line 11477: 0 +Line 11478: 0 +Line 11479: 0 +Line 11480: 0 +Line 11481: 0 +Line 11482: 0 +Line 11483: 0 +Line 11484: 0 +Line 11485: 0 +Line 11486: 0 +Line 11487: 0 +Line 11488: 0 +Line 11489: 0 +Line 11490: 1 +Line 11491: 1 +Line 11492: 1 +Line 11493: 0 +Line 11494: 1 +Line 11495: 0 +Line 11496: 1 +Line 11497: 0 +Line 11498: 0 +Line 11499: 1 +Line 11500: 1 +Line 11501: 0 +Line 11502: 0 +Line 11503: 1 +Line 11504: 0 +Line 11505: 0 +Line 11506: 0 +Line 11507: 0 +Line 11508: 0 +Line 11509: 0 +Line 11510: 0 +Line 11511: 0 +Line 11512: 0 +Line 11513: 0 +Line 11514: 0 +Line 11515: 0 +Line 11516: 0 +Line 11517: 0 +Line 11518: 0 +Line 11519: 0 +Line 11520: 0 +Line 11521: 0 +Line 11522: 1 +Line 11523: 1 +Line 11524: 1 +Line 11525: 0 +Line 11526: 1 +Line 11527: 1 +Line 11528: 1 +Line 11529: 0 +Line 11530: 0 +Line 11531: 1 +Line 11532: 1 +Line 11533: 0 +Line 11534: 1 +Line 11535: 0 +Line 11536: 0 +Line 11537: 0 +Line 11538: 0 +Line 11539: 0 +Line 11540: 0 +Line 11541: 0 +Line 11542: 0 +Line 11543: 0 +Line 11544: 0 +Line 11545: 0 +Line 11546: 0 +Line 11547: 0 +Line 11548: 0 +Line 11549: 0 +Line 11550: 0 +Line 11551: 0 +Line 11552: 0 +Line 11553: 0 +Line 11554: 1 +Line 11555: 1 +Line 11556: 1 +Line 11557: 1 +Line 11558: 0 +Line 11559: 0 +Line 11560: 0 +Line 11561: 0 +Line 11562: 0 +Line 11563: 1 +Line 11564: 0 +Line 11565: 0 +Line 11566: 0 +Line 11567: 1 +Line 11568: 0 +Line 11569: 0 +Line 11570: 0 +Line 11571: 0 +Line 11572: 0 +Line 11573: 0 +Line 11574: 0 +Line 11575: 0 +Line 11576: 0 +Line 11577: 0 +Line 11578: 0 +Line 11579: 0 +Line 11580: 0 +Line 11581: 0 +Line 11582: 0 +Line 11583: 0 +Line 11584: 0 +Line 11585: 0 +Line 11586: 1 +Line 11587: 1 +Line 11588: 1 +Line 11589: 1 +Line 11590: 0 +Line 11591: 0 +Line 11592: 0 +Line 11593: 0 +Line 11594: 0 +Line 11595: 1 +Line 11596: 1 +Line 11597: 1 +Line 11598: 1 +Line 11599: 1 +Line 11600: 0 +Line 11601: 0 +Line 11602: 0 +Line 11603: 0 +Line 11604: 0 +Line 11605: 0 +Line 11606: 0 +Line 11607: 0 +Line 11608: 0 +Line 11609: 0 +Line 11610: 0 +Line 11611: 0 +Line 11612: 0 +Line 11613: 0 +Line 11614: 0 +Line 11615: 0 +Line 11616: 0 +Line 11617: 0 +Line 11618: 1 +Line 11619: 1 +Line 11620: 1 +Line 11621: 0 +Line 11622: 1 +Line 11623: 1 +Line 11624: 1 +Line 11625: 1 +Line 11626: 1 +Line 11627: 0 +Line 11628: 0 +Line 11629: 1 +Line 11630: 0 +Line 11631: 0 +Line 11632: 0 +Line 11633: 0 +Line 11634: 0 +Line 11635: 0 +Line 11636: 0 +Line 11637: 0 +Line 11638: 0 +Line 11639: 0 +Line 11640: 0 +Line 11641: 0 +Line 11642: 0 +Line 11643: 0 +Line 11644: 0 +Line 11645: 0 +Line 11646: 0 +Line 11647: 0 +Line 11648: 0 +Line 11649: 0 +Line 11650: 1 +Line 11651: 1 +Line 11652: 1 +Line 11653: 0 +Line 11654: 1 +Line 11655: 1 +Line 11656: 1 +Line 11657: 0 +Line 11658: 0 +Line 11659: 0 +Line 11660: 0 +Line 11661: 0 +Line 11662: 0 +Line 11663: 0 +Line 11664: 0 +Line 11665: 0 +Line 11666: 0 +Line 11667: 0 +Line 11668: 0 +Line 11669: 0 +Line 11670: 0 +Line 11671: 0 +Line 11672: 0 +Line 11673: 0 +Line 11674: 0 +Line 11675: 0 +Line 11676: 0 +Line 11677: 0 +Line 11678: 0 +Line 11679: 0 +Line 11680: 0 +Line 11681: 0 +Line 11682: 1 +Line 11683: 1 +Line 11684: 1 +Line 11685: 0 +Line 11686: 1 +Line 11687: 1 +Line 11688: 0 +Line 11689: 0 +Line 11690: 0 +Line 11691: 1 +Line 11692: 0 +Line 11693: 0 +Line 11694: 0 +Line 11695: 0 +Line 11696: 0 +Line 11697: 0 +Line 11698: 0 +Line 11699: 0 +Line 11700: 0 +Line 11701: 0 +Line 11702: 0 +Line 11703: 0 +Line 11704: 0 +Line 11705: 0 +Line 11706: 0 +Line 11707: 0 +Line 11708: 0 +Line 11709: 0 +Line 11710: 0 +Line 11711: 0 +Line 11712: 0 +Line 11713: 0 +Line 11714: 1 +Line 11715: 1 +Line 11716: 1 +Line 11717: 0 +Line 11718: 1 +Line 11719: 0 +Line 11720: 1 +Line 11721: 0 +Line 11722: 1 +Line 11723: 0 +Line 11724: 1 +Line 11725: 1 +Line 11726: 0 +Line 11727: 1 +Line 11728: 0 +Line 11729: 0 +Line 11730: 0 +Line 11731: 0 +Line 11732: 0 +Line 11733: 0 +Line 11734: 0 +Line 11735: 0 +Line 11736: 0 +Line 11737: 0 +Line 11738: 0 +Line 11739: 0 +Line 11740: 0 +Line 11741: 0 +Line 11742: 0 +Line 11743: 0 +Line 11744: 0 +Line 11745: 0 +Line 11746: 1 +Line 11747: 1 +Line 11748: 1 +Line 11749: 0 +Line 11750: 1 +Line 11751: 0 +Line 11752: 0 +Line 11753: 1 +Line 11754: 1 +Line 11755: 0 +Line 11756: 1 +Line 11757: 0 +Line 11758: 0 +Line 11759: 1 +Line 11760: 0 +Line 11761: 0 +Line 11762: 0 +Line 11763: 0 +Line 11764: 0 +Line 11765: 0 +Line 11766: 0 +Line 11767: 0 +Line 11768: 0 +Line 11769: 0 +Line 11770: 0 +Line 11771: 0 +Line 11772: 0 +Line 11773: 0 +Line 11774: 0 +Line 11775: 0 +Line 11776: 0 +Line 11777: 0 +Line 11778: 1 +Line 11779: 1 +Line 11780: 1 +Line 11781: 0 +Line 11782: 1 +Line 11783: 0 +Line 11784: 0 +Line 11785: 1 +Line 11786: 0 +Line 11787: 1 +Line 11788: 0 +Line 11789: 0 +Line 11790: 1 +Line 11791: 0 +Line 11792: 0 +Line 11793: 0 +Line 11794: 0 +Line 11795: 0 +Line 11796: 0 +Line 11797: 0 +Line 11798: 0 +Line 11799: 0 +Line 11800: 0 +Line 11801: 0 +Line 11802: 0 +Line 11803: 0 +Line 11804: 0 +Line 11805: 0 +Line 11806: 0 +Line 11807: 0 +Line 11808: 0 +Line 11809: 0 +Line 11810: 1 +Line 11811: 1 +Line 11812: 1 +Line 11813: 0 +Line 11814: 1 +Line 11815: 0 +Line 11816: 0 +Line 11817: 1 +Line 11818: 1 +Line 11819: 0 +Line 11820: 1 +Line 11821: 0 +Line 11822: 0 +Line 11823: 1 +Line 11824: 0 +Line 11825: 0 +Line 11826: 0 +Line 11827: 0 +Line 11828: 0 +Line 11829: 0 +Line 11830: 0 +Line 11831: 0 +Line 11832: 0 +Line 11833: 0 +Line 11834: 0 +Line 11835: 0 +Line 11836: 0 +Line 11837: 0 +Line 11838: 0 +Line 11839: 0 +Line 11840: 0 +Line 11841: 0 +Line 11842: 1 +Line 11843: 1 +Line 11844: 1 +Line 11845: 0 +Line 11846: 1 +Line 11847: 0 +Line 11848: 1 +Line 11849: 0 +Line 11850: 1 +Line 11851: 0 +Line 11852: 1 +Line 11853: 1 +Line 11854: 0 +Line 11855: 1 +Line 11856: 0 +Line 11857: 0 +Line 11858: 0 +Line 11859: 0 +Line 11860: 0 +Line 11861: 0 +Line 11862: 0 +Line 11863: 0 +Line 11864: 0 +Line 11865: 0 +Line 11866: 0 +Line 11867: 0 +Line 11868: 0 +Line 11869: 0 +Line 11870: 0 +Line 11871: 0 +Line 11872: 0 +Line 11873: 0 +Line 11874: 1 +Line 11875: 1 +Line 11876: 1 +Line 11877: 0 +Line 11878: 1 +Line 11879: 1 +Line 11880: 0 +Line 11881: 0 +Line 11882: 0 +Line 11883: 1 +Line 11884: 0 +Line 11885: 0 +Line 11886: 0 +Line 11887: 0 +Line 11888: 0 +Line 11889: 0 +Line 11890: 0 +Line 11891: 0 +Line 11892: 0 +Line 11893: 0 +Line 11894: 0 +Line 11895: 0 +Line 11896: 0 +Line 11897: 0 +Line 11898: 0 +Line 11899: 0 +Line 11900: 0 +Line 11901: 0 +Line 11902: 0 +Line 11903: 0 +Line 11904: 0 +Line 11905: 0 +Line 11906: 1 +Line 11907: 1 +Line 11908: 1 +Line 11909: 0 +Line 11910: 1 +Line 11911: 1 +Line 11912: 1 +Line 11913: 0 +Line 11914: 0 +Line 11915: 0 +Line 11916: 0 +Line 11917: 0 +Line 11918: 0 +Line 11919: 0 +Line 11920: 0 +Line 11921: 0 +Line 11922: 0 +Line 11923: 0 +Line 11924: 0 +Line 11925: 0 +Line 11926: 0 +Line 11927: 0 +Line 11928: 0 +Line 11929: 0 +Line 11930: 0 +Line 11931: 0 +Line 11932: 0 +Line 11933: 0 +Line 11934: 0 +Line 11935: 0 +Line 11936: 0 +Line 11937: 0 +Line 11938: 1 +Line 11939: 1 +Line 11940: 1 +Line 11941: 0 +Line 11942: 1 +Line 11943: 1 +Line 11944: 1 +Line 11945: 1 +Line 11946: 1 +Line 11947: 0 +Line 11948: 0 +Line 11949: 1 +Line 11950: 0 +Line 11951: 0 +Line 11952: 0 +Line 11953: 0 +Line 11954: 0 +Line 11955: 0 +Line 11956: 0 +Line 11957: 0 +Line 11958: 0 +Line 11959: 0 +Line 11960: 0 +Line 11961: 0 +Line 11962: 0 +Line 11963: 0 +Line 11964: 0 +Line 11965: 0 +Line 11966: 0 +Line 11967: 0 +Line 11968: 0 +Line 11969: 0 +Line 11970: 1 +Line 11971: 1 +Line 11972: 1 +Line 11973: 1 +Line 11974: 0 +Line 11975: 0 +Line 11976: 0 +Line 11977: 0 +Line 11978: 0 +Line 11979: 1 +Line 11980: 1 +Line 11981: 1 +Line 11982: 1 +Line 11983: 1 +Line 11984: 0 +Line 11985: 0 +Line 11986: 0 +Line 11987: 0 +Line 11988: 0 +Line 11989: 0 +Line 11990: 0 +Line 11991: 0 +Line 11992: 0 +Line 11993: 0 +Line 11994: 0 +Line 11995: 0 +Line 11996: 0 +Line 11997: 0 +Line 11998: 0 +Line 11999: 0 +Line 12000: 0 +Line 12001: 0 +Line 12002: 1 +Line 12003: 1 +Line 12004: 1 +Line 12005: 1 +Line 12006: 0 +Line 12007: 0 +Line 12008: 0 +Line 12009: 0 +Line 12010: 0 +Line 12011: 1 +Line 12012: 0 +Line 12013: 0 +Line 12014: 0 +Line 12015: 1 +Line 12016: 0 +Line 12017: 0 +Line 12018: 0 +Line 12019: 0 +Line 12020: 0 +Line 12021: 0 +Line 12022: 0 +Line 12023: 0 +Line 12024: 0 +Line 12025: 0 +Line 12026: 0 +Line 12027: 0 +Line 12028: 0 +Line 12029: 0 +Line 12030: 0 +Line 12031: 0 +Line 12032: 0 +Line 12033: 0 +Line 12034: 1 +Line 12035: 1 +Line 12036: 1 +Line 12037: 0 +Line 12038: 1 +Line 12039: 1 +Line 12040: 1 +Line 12041: 0 +Line 12042: 0 +Line 12043: 1 +Line 12044: 1 +Line 12045: 0 +Line 12046: 1 +Line 12047: 0 +Line 12048: 0 +Line 12049: 0 +Line 12050: 0 +Line 12051: 0 +Line 12052: 0 +Line 12053: 0 +Line 12054: 0 +Line 12055: 0 +Line 12056: 0 +Line 12057: 0 +Line 12058: 0 +Line 12059: 0 +Line 12060: 0 +Line 12061: 0 +Line 12062: 0 +Line 12063: 0 +Line 12064: 0 +Line 12065: 0 +Line 12066: 1 +Line 12067: 1 +Line 12068: 1 +Line 12069: 0 +Line 12070: 1 +Line 12071: 0 +Line 12072: 1 +Line 12073: 0 +Line 12074: 0 +Line 12075: 1 +Line 12076: 1 +Line 12077: 0 +Line 12078: 0 +Line 12079: 1 +Line 12080: 0 +Line 12081: 0 +Line 12082: 0 +Line 12083: 0 +Line 12084: 0 +Line 12085: 0 +Line 12086: 0 +Line 12087: 0 +Line 12088: 0 +Line 12089: 0 +Line 12090: 0 +Line 12091: 0 +Line 12092: 0 +Line 12093: 0 +Line 12094: 0 +Line 12095: 0 +Line 12096: 0 +Line 12097: 0 +Line 12098: 1 +Line 12099: 1 +Line 12100: 1 +Line 12101: 0 +Line 12102: 0 +Line 12103: 0 +Line 12104: 1 +Line 12105: 1 +Line 12106: 1 +Line 12107: 1 +Line 12108: 0 +Line 12109: 0 +Line 12110: 1 +Line 12111: 0 +Line 12112: 0 +Line 12113: 0 +Line 12114: 0 +Line 12115: 0 +Line 12116: 0 +Line 12117: 0 +Line 12118: 0 +Line 12119: 0 +Line 12120: 0 +Line 12121: 0 +Line 12122: 0 +Line 12123: 0 +Line 12124: 0 +Line 12125: 0 +Line 12126: 0 +Line 12127: 0 +Line 12128: 0 +Line 12129: 0 +Line 12130: 1 +Line 12131: 1 +Line 12132: 0 +Line 12133: 1 +Line 12134: 1 +Line 12135: 0 +Line 12136: 1 +Line 12137: 0 +Line 12138: 0 +Line 12139: 1 +Line 12140: 0 +Line 12141: 0 +Line 12142: 0 +Line 12143: 0 +Line 12144: 0 +Line 12145: 0 +Line 12146: 0 +Line 12147: 0 +Line 12148: 0 +Line 12149: 0 +Line 12150: 0 +Line 12151: 0 +Line 12152: 0 +Line 12153: 0 +Line 12154: 0 +Line 12155: 0 +Line 12156: 0 +Line 12157: 0 +Line 12158: 0 +Line 12159: 0 +Line 12160: 0 +Line 12161: 0 +Line 12162: 1 +Line 12163: 1 +Line 12164: 0 +Line 12165: 0 +Line 12166: 1 +Line 12167: 1 +Line 12168: 0 +Line 12169: 1 +Line 12170: 0 +Line 12171: 1 +Line 12172: 1 +Line 12173: 1 +Line 12174: 1 +Line 12175: 1 +Line 12176: 0 +Line 12177: 0 +Line 12178: 0 +Line 12179: 0 +Line 12180: 0 +Line 12181: 0 +Line 12182: 0 +Line 12183: 0 +Line 12184: 0 +Line 12185: 0 +Line 12186: 0 +Line 12187: 0 +Line 12188: 0 +Line 12189: 0 +Line 12190: 0 +Line 12191: 0 +Line 12192: 0 +Line 12193: 0 +Line 12194: 1 +Line 12195: 0 +Line 12196: 1 +Line 12197: 1 +Line 12198: 1 +Line 12199: 1 +Line 12200: 0 +Line 12201: 1 +Line 12202: 0 +Line 12203: 1 +Line 12204: 1 +Line 12205: 0 +Line 12206: 0 +Line 12207: 1 +Line 12208: 0 +Line 12209: 0 +Line 12210: 0 +Line 12211: 0 +Line 12212: 0 +Line 12213: 0 +Line 12214: 0 +Line 12215: 0 +Line 12216: 0 +Line 12217: 0 +Line 12218: 0 +Line 12219: 0 +Line 12220: 0 +Line 12221: 0 +Line 12222: 0 +Line 12223: 0 +Line 12224: 0 +Line 12225: 0 +Line 12226: 1 +Line 12227: 0 +Line 12228: 1 +Line 12229: 0 +Line 12230: 1 +Line 12231: 0 +Line 12232: 0 +Line 12233: 1 +Line 12234: 1 +Line 12235: 1 +Line 12236: 1 +Line 12237: 1 +Line 12238: 1 +Line 12239: 0 +Line 12240: 0 +Line 12241: 0 +Line 12242: 0 +Line 12243: 0 +Line 12244: 0 +Line 12245: 0 +Line 12246: 0 +Line 12247: 0 +Line 12248: 0 +Line 12249: 0 +Line 12250: 0 +Line 12251: 0 +Line 12252: 0 +Line 12253: 0 +Line 12254: 0 +Line 12255: 0 +Line 12256: 0 +Line 12257: 0 +Line 12258: 1 +Line 12259: 0 +Line 12260: 0 +Line 12261: 1 +Line 12262: 0 +Line 12263: 0 +Line 12264: 1 +Line 12265: 1 +Line 12266: 0 +Line 12267: 1 +Line 12268: 0 +Line 12269: 1 +Line 12270: 0 +Line 12271: 1 +Line 12272: 0 +Line 12273: 0 +Line 12274: 0 +Line 12275: 0 +Line 12276: 0 +Line 12277: 0 +Line 12278: 0 +Line 12279: 0 +Line 12280: 0 +Line 12281: 0 +Line 12282: 0 +Line 12283: 0 +Line 12284: 0 +Line 12285: 0 +Line 12286: 0 +Line 12287: 0 +Line 12288: 0 +Line 12289: 0 +Line 12290: 0 +Line 12291: 1 +Line 12292: 1 +Line 12293: 1 +Line 12294: 1 +Line 12295: 0 +Line 12296: 0 +Line 12297: 1 +Line 12298: 1 +Line 12299: 1 +Line 12300: 0 +Line 12301: 0 +Line 12302: 0 +Line 12303: 1 +Line 12304: 0 +Line 12305: 0 +Line 12306: 0 +Line 12307: 0 +Line 12308: 0 +Line 12309: 0 +Line 12310: 0 +Line 12311: 0 +Line 12312: 0 +Line 12313: 0 +Line 12314: 0 +Line 12315: 0 +Line 12316: 0 +Line 12317: 0 +Line 12318: 0 +Line 12319: 0 +Line 12320: 0 +Line 12321: 0 +Line 12322: 0 +Line 12323: 1 +Line 12324: 0 +Line 12325: 1 +Line 12326: 1 +Line 12327: 1 +Line 12328: 0 +Line 12329: 1 +Line 12330: 1 +Line 12331: 0 +Line 12332: 1 +Line 12333: 1 +Line 12334: 0 +Line 12335: 0 +Line 12336: 0 +Line 12337: 0 +Line 12338: 0 +Line 12339: 0 +Line 12340: 0 +Line 12341: 0 +Line 12342: 0 +Line 12343: 0 +Line 12344: 0 +Line 12345: 0 +Line 12346: 0 +Line 12347: 0 +Line 12348: 0 +Line 12349: 0 +Line 12350: 0 +Line 12351: 0 +Line 12352: 0 +Line 12353: 0 +Line 12354: 0 +Line 12355: 0 +Line 12356: 1 +Line 12357: 1 +Line 12358: 1 +Line 12359: 1 +Line 12360: 1 +Line 12361: 1 +Line 12362: 1 +Line 12363: 0 +Line 12364: 0 +Line 12365: 1 +Line 12366: 1 +Line 12367: 1 +Line 12368: 0 +Line 12369: 0 +Line 12370: 0 +Line 12371: 0 +Line 12372: 0 +Line 12373: 0 +Line 12374: 0 +Line 12375: 0 +Line 12376: 0 +Line 12377: 0 +Line 12378: 0 +Line 12379: 0 +Line 12380: 0 +Line 12381: 0 +Line 12382: 0 +Line 12383: 0 +Line 12384: 0 +Line 12385: 0 +Line 12386: 0 +Line 12387: 0 +Line 12388: 1 +Line 12389: 0 +Line 12390: 0 +Line 12391: 0 +Line 12392: 0 +Line 12393: 0 +Line 12394: 0 +Line 12395: 0 +Line 12396: 1 +Line 12397: 0 +Line 12398: 1 +Line 12399: 0 +Line 12400: 0 +Line 12401: 0 +Line 12402: 0 +Line 12403: 0 +Line 12404: 0 +Line 12405: 0 +Line 12406: 0 +Line 12407: 0 +Line 12408: 0 +Line 12409: 0 +Line 12410: 0 +Line 12411: 0 +Line 12412: 0 +Line 12413: 0 +Line 12414: 0 +Line 12415: 0 +Line 12416: 0 +Line 12417: 0 +Line 12418: 0 +Line 12419: 0 +Line 12420: 0 +Line 12421: 0 +Line 12422: 0 +Line 12423: 0 +Line 12424: 0 +Line 12425: 0 +Line 12426: 0 +Line 12427: 0 +Line 12428: 0 +Line 12429: 0 +Line 12430: 0 +Line 12431: 0 +Line 12432: 0 +Line 12433: 0 +Line 12434: 0 +Line 12435: 0 +Line 12436: 0 +Line 12437: 0 +Line 12438: 0 +Line 12439: 0 +Line 12440: 0 +Line 12441: 0 +Line 12442: 0 +Line 12443: 0 +Line 12444: 0 +Line 12445: 0 +Line 12446: 0 +Line 12447: 0 +Line 12448: 0 +Line 12449: 0 +Line 12450: 0 +Line 12451: 0 +Line 12452: 1 +Line 12453: 0 +Line 12454: 0 +Line 12455: 0 +Line 12456: 0 +Line 12457: 0 +Line 12458: 1 +Line 12459: 1 +Line 12460: 1 +Line 12461: 0 +Line 12462: 0 +Line 12463: 1 +Line 12464: 0 +Line 12465: 0 +Line 12466: 1 +Line 12467: 0 +Line 12468: 0 +Line 12469: 0 +Line 12470: 0 +Line 12471: 1 +Line 12472: 0 +Line 12473: 0 +Line 12474: 1 +Line 12475: 0 +Line 12476: 0 +Line 12477: 0 +Line 12478: 0 +Line 12479: 1 +Line 12480: 0 +Line 12481: 0 +Line 12482: 0 +Line 12483: 1 +Line 12484: 1 +Line 12485: 1 +Line 12486: 0 +Line 12487: 1 +Line 12488: 0 +Line 12489: 0 +Line 12490: 0 +Line 12491: 0 +Line 12492: 1 +Line 12493: 1 +Line 12494: 0 +Line 12495: 1 +Line 12496: 0 +Line 12497: 0 +Line 12498: 1 +Line 12499: 1 +Line 12500: 0 +Line 12501: 0 +Line 12502: 1 +Line 12503: 0 +Line 12504: 1 +Line 12505: 1 +Line 12506: 0 +Line 12507: 0 +Line 12508: 0 +Line 12509: 0 +Line 12510: 1 +Line 12511: 0 +Line 12512: 0 +Line 12513: 0 +Line 12514: 1 +Line 12515: 1 +Line 12516: 0 +Line 12517: 1 +Line 12518: 0 +Line 12519: 0 +Line 12520: 1 +Line 12521: 0 +Line 12522: 1 +Line 12523: 1 +Line 12524: 1 +Line 12525: 0 +Line 12526: 1 +Line 12527: 1 +Line 12528: 0 +Line 12529: 0 +Line 12530: 1 +Line 12531: 0 +Line 12532: 1 +Line 12533: 1 +Line 12534: 0 +Line 12535: 0 +Line 12536: 1 +Line 12537: 0 +Line 12538: 1 +Line 12539: 0 +Line 12540: 0 +Line 12541: 0 +Line 12542: 1 +Line 12543: 0 +Line 12544: 0 +Line 12545: 1 +Line 12546: 0 +Line 12547: 0 +Line 12548: 0 +Line 12549: 1 +Line 12550: 0 +Line 12551: 0 +Line 12552: 0 +Line 12553: 0 +Line 12554: 1 +Line 12555: 1 +Line 12556: 0 +Line 12557: 0 +Line 12558: 0 +Line 12559: 1 +Line 12560: 0 +Line 12561: 0 +Line 12562: 0 +Line 12563: 1 +Line 12564: 0 +Line 12565: 0 +Line 12566: 0 +Line 12567: 1 +Line 12568: 1 +Line 12569: 0 +Line 12570: 1 +Line 12571: 0 +Line 12572: 0 +Line 12573: 0 +Line 12574: 0 +Line 12575: 0 +Line 12576: 0 +Line 12577: 1 +Line 12578: 0 +Line 12579: 0 +Line 12580: 0 +Line 12581: 1 +Line 12582: 0 +Line 12583: 0 +Line 12584: 0 +Line 12585: 0 +Line 12586: 1 +Line 12587: 1 +Line 12588: 0 +Line 12589: 0 +Line 12590: 0 +Line 12591: 1 +Line 12592: 1 +Line 12593: 1 +Line 12594: 1 +Line 12595: 0 +Line 12596: 1 +Line 12597: 1 +Line 12598: 1 +Line 12599: 0 +Line 12600: 0 +Line 12601: 1 +Line 12602: 1 +Line 12603: 0 +Line 12604: 0 +Line 12605: 0 +Line 12606: 0 +Line 12607: 0 +Line 12608: 0 +Line 12609: 0 +Line 12610: 1 +Line 12611: 1 +Line 12612: 0 +Line 12613: 1 +Line 12614: 0 +Line 12615: 0 +Line 12616: 1 +Line 12617: 0 +Line 12618: 1 +Line 12619: 1 +Line 12620: 1 +Line 12621: 1 +Line 12622: 0 +Line 12623: 0 +Line 12624: 1 +Line 12625: 1 +Line 12626: 0 +Line 12627: 1 +Line 12628: 0 +Line 12629: 0 +Line 12630: 1 +Line 12631: 1 +Line 12632: 0 +Line 12633: 1 +Line 12634: 0 +Line 12635: 1 +Line 12636: 1 +Line 12637: 1 +Line 12638: 1 +Line 12639: 0 +Line 12640: 0 +Line 12641: 0 +Line 12642: 0 +Line 12643: 1 +Line 12644: 1 +Line 12645: 1 +Line 12646: 0 +Line 12647: 1 +Line 12648: 0 +Line 12649: 0 +Line 12650: 0 +Line 12651: 0 +Line 12652: 1 +Line 12653: 1 +Line 12654: 0 +Line 12655: 1 +Line 12656: 1 +Line 12657: 1 +Line 12658: 0 +Line 12659: 0 +Line 12660: 1 +Line 12661: 1 +Line 12662: 0 +Line 12663: 1 +Line 12664: 0 +Line 12665: 0 +Line 12666: 1 +Line 12667: 1 +Line 12668: 1 +Line 12669: 1 +Line 12670: 1 +Line 12671: 0 +Line 12672: 0 +Line 12673: 0 +Line 12674: 0 +Line 12675: 0 +Line 12676: 1 +Line 12677: 0 +Line 12678: 0 +Line 12679: 0 +Line 12680: 0 +Line 12681: 0 +Line 12682: 1 +Line 12683: 1 +Line 12684: 1 +Line 12685: 0 +Line 12686: 0 +Line 12687: 1 +Line 12688: 1 +Line 12689: 1 +Line 12690: 0 +Line 12691: 1 +Line 12692: 1 +Line 12693: 1 +Line 12694: 1 +Line 12695: 0 +Line 12696: 1 +Line 12697: 1 +Line 12698: 0 +Line 12699: 1 +Line 12700: 1 +Line 12701: 1 +Line 12702: 1 +Line 12703: 1 +Line 12704: 0 +Line 12705: 0 +Line 12706: 0 +Line 12707: 0 +Line 12708: 0 +Line 12709: 0 +Line 12710: 0 +Line 12711: 0 +Line 12712: 0 +Line 12713: 0 +Line 12714: 0 +Line 12715: 0 +Line 12716: 0 +Line 12717: 0 +Line 12718: 0 +Line 12719: 0 +Line 12720: 0 +Line 12721: 0 +Line 12722: 0 +Line 12723: 0 +Line 12724: 0 +Line 12725: 0 +Line 12726: 0 +Line 12727: 0 +Line 12728: 0 +Line 12729: 0 +Line 12730: 0 +Line 12731: 0 +Line 12732: 0 +Line 12733: 0 +Line 12734: 0 +Line 12735: 0 +Line 12736: 0 +Line 12737: 0 +Line 12738: 0 +Line 12739: 0 +Line 12740: 0 +Line 12741: 0 +Line 12742: 0 +Line 12743: 1 +Line 12744: 1 +Line 12745: 0 +Line 12746: 0 +Line 12747: 1 +Line 12748: 1 +Line 12749: 0 +Line 12750: 0 +Line 12751: 1 +Line 12752: 0 +Line 12753: 0 +Line 12754: 0 +Line 12755: 0 +Line 12756: 0 +Line 12757: 0 +Line 12758: 0 +Line 12759: 0 +Line 12760: 0 +Line 12761: 0 +Line 12762: 0 +Line 12763: 0 +Line 12764: 0 +Line 12765: 0 +Line 12766: 0 +Line 12767: 0 +Line 12768: 0 +Line 12769: 0 +Line 12770: 0 +Line 12771: 0 +Line 12772: 1 +Line 12773: 0 +Line 12774: 1 +Line 12775: 1 +Line 12776: 0 +Line 12777: 0 +Line 12778: 1 +Line 12779: 0 +Line 12780: 0 +Line 12781: 1 +Line 12782: 1 +Line 12783: 1 +Line 12784: 0 +Line 12785: 0 +Line 12786: 0 +Line 12787: 0 +Line 12788: 0 +Line 12789: 0 +Line 12790: 0 +Line 12791: 0 +Line 12792: 0 +Line 12793: 0 +Line 12794: 0 +Line 12795: 0 +Line 12796: 0 +Line 12797: 0 +Line 12798: 0 +Line 12799: 0 +Line 12800: 0 +Line 12801: 0 +Line 12802: 1 +Line 12803: 0 +Line 12804: 0 +Line 12805: 0 +Line 12806: 1 +Line 12807: 1 +Line 12808: 0 +Line 12809: 0 +Line 12810: 1 +Line 12811: 0 +Line 12812: 1 +Line 12813: 0 +Line 12814: 0 +Line 12815: 0 +Line 12816: 0 +Line 12817: 0 +Line 12818: 0 +Line 12819: 0 +Line 12820: 0 +Line 12821: 0 +Line 12822: 0 +Line 12823: 0 +Line 12824: 0 +Line 12825: 0 +Line 12826: 0 +Line 12827: 0 +Line 12828: 0 +Line 12829: 0 +Line 12830: 0 +Line 12831: 0 +Line 12832: 0 +Line 12833: 0 +Line 12834: 1 +Line 12835: 1 +Line 12836: 1 +Line 12837: 0 +Line 12838: 1 +Line 12839: 1 +Line 12840: 0 +Line 12841: 0 +Line 12842: 1 +Line 12843: 0 +Line 12844: 1 +Line 12845: 0 +Line 12846: 0 +Line 12847: 0 +Line 12848: 0 +Line 12849: 0 +Line 12850: 0 +Line 12851: 0 +Line 12852: 0 +Line 12853: 0 +Line 12854: 0 +Line 12855: 0 +Line 12856: 0 +Line 12857: 0 +Line 12858: 0 +Line 12859: 0 +Line 12860: 0 +Line 12861: 0 +Line 12862: 0 +Line 12863: 0 +Line 12864: 0 +Line 12865: 1 +Line 12866: 0 +Line 12867: 0 +Line 12868: 0 +Line 12869: 1 +Line 12870: 0 +Line 12871: 0 +Line 12872: 1 +Line 12873: 0 +Line 12874: 1 +Line 12875: 1 +Line 12876: 0 +Line 12877: 1 +Line 12878: 1 +Line 12879: 0 +Line 12880: 0 +Line 12881: 0 +Line 12882: 0 +Line 12883: 0 +Line 12884: 0 +Line 12885: 0 +Line 12886: 0 +Line 12887: 0 +Line 12888: 0 +Line 12889: 0 +Line 12890: 0 +Line 12891: 0 +Line 12892: 0 +Line 12893: 0 +Line 12894: 0 +Line 12895: 0 +Line 12896: 0 +Line 12897: 1 +Line 12898: 0 +Line 12899: 0 +Line 12900: 0 +Line 12901: 1 +Line 12902: 1 +Line 12903: 0 +Line 12904: 0 +Line 12905: 0 +Line 12906: 1 +Line 12907: 1 +Line 12908: 0 +Line 12909: 1 +Line 12910: 1 +Line 12911: 1 +Line 12912: 0 +Line 12913: 0 +Line 12914: 0 +Line 12915: 0 +Line 12916: 0 +Line 12917: 0 +Line 12918: 0 +Line 12919: 0 +Line 12920: 0 +Line 12921: 0 +Line 12922: 0 +Line 12923: 0 +Line 12924: 0 +Line 12925: 0 +Line 12926: 0 +Line 12927: 0 +Line 12928: 0 +Line 12929: 1 +Line 12930: 0 +Line 12931: 0 +Line 12932: 0 +Line 12933: 1 +Line 12934: 1 +Line 12935: 0 +Line 12936: 0 +Line 12937: 1 +Line 12938: 0 +Line 12939: 0 +Line 12940: 1 +Line 12941: 1 +Line 12942: 1 +Line 12943: 1 +Line 12944: 0 +Line 12945: 0 +Line 12946: 0 +Line 12947: 0 +Line 12948: 0 +Line 12949: 0 +Line 12950: 0 +Line 12951: 0 +Line 12952: 0 +Line 12953: 0 +Line 12954: 0 +Line 12955: 0 +Line 12956: 0 +Line 12957: 0 +Line 12958: 0 +Line 12959: 0 +Line 12960: 0 +Line 12961: 1 +Line 12962: 0 +Line 12963: 0 +Line 12964: 0 +Line 12965: 1 +Line 12966: 1 +Line 12967: 0 +Line 12968: 0 +Line 12969: 1 +Line 12970: 0 +Line 12971: 0 +Line 12972: 1 +Line 12973: 1 +Line 12974: 1 +Line 12975: 1 +Line 12976: 0 +Line 12977: 0 +Line 12978: 0 +Line 12979: 0 +Line 12980: 0 +Line 12981: 0 +Line 12982: 0 +Line 12983: 0 +Line 12984: 0 +Line 12985: 0 +Line 12986: 0 +Line 12987: 0 +Line 12988: 0 +Line 12989: 0 +Line 12990: 0 +Line 12991: 0 +Line 12992: 0 +Line 12993: 1 +Line 12994: 0 +Line 12995: 0 +Line 12996: 0 +Line 12997: 1 +Line 12998: 1 +Line 12999: 0 +Line 13000: 0 +Line 13001: 1 +Line 13002: 0 +Line 13003: 0 +Line 13004: 1 +Line 13005: 1 +Line 13006: 1 +Line 13007: 1 +Line 13008: 0 +Line 13009: 0 +Line 13010: 0 +Line 13011: 0 +Line 13012: 0 +Line 13013: 0 +Line 13014: 0 +Line 13015: 0 +Line 13016: 0 +Line 13017: 0 +Line 13018: 0 +Line 13019: 0 +Line 13020: 0 +Line 13021: 0 +Line 13022: 0 +Line 13023: 0 +Line 13024: 0 +Line 13025: 1 +Line 13026: 0 +Line 13027: 0 +Line 13028: 0 +Line 13029: 1 +Line 13030: 1 +Line 13031: 0 +Line 13032: 0 +Line 13033: 1 +Line 13034: 0 +Line 13035: 0 +Line 13036: 1 +Line 13037: 1 +Line 13038: 1 +Line 13039: 1 +Line 13040: 0 +Line 13041: 0 +Line 13042: 0 +Line 13043: 0 +Line 13044: 0 +Line 13045: 0 +Line 13046: 0 +Line 13047: 0 +Line 13048: 0 +Line 13049: 0 +Line 13050: 0 +Line 13051: 0 +Line 13052: 0 +Line 13053: 0 +Line 13054: 0 +Line 13055: 0 +Line 13056: 0 +Line 13057: 1 +Line 13058: 0 +Line 13059: 0 +Line 13060: 0 +Line 13061: 1 +Line 13062: 1 +Line 13063: 0 +Line 13064: 0 +Line 13065: 0 +Line 13066: 1 +Line 13067: 1 +Line 13068: 0 +Line 13069: 1 +Line 13070: 1 +Line 13071: 1 +Line 13072: 0 +Line 13073: 0 +Line 13074: 0 +Line 13075: 0 +Line 13076: 0 +Line 13077: 0 +Line 13078: 0 +Line 13079: 0 +Line 13080: 0 +Line 13081: 0 +Line 13082: 0 +Line 13083: 0 +Line 13084: 0 +Line 13085: 0 +Line 13086: 0 +Line 13087: 0 +Line 13088: 0 +Line 13089: 1 +Line 13090: 0 +Line 13091: 0 +Line 13092: 0 +Line 13093: 1 +Line 13094: 0 +Line 13095: 0 +Line 13096: 1 +Line 13097: 0 +Line 13098: 1 +Line 13099: 1 +Line 13100: 0 +Line 13101: 1 +Line 13102: 1 +Line 13103: 0 +Line 13104: 0 +Line 13105: 0 +Line 13106: 0 +Line 13107: 0 +Line 13108: 0 +Line 13109: 0 +Line 13110: 0 +Line 13111: 0 +Line 13112: 0 +Line 13113: 0 +Line 13114: 0 +Line 13115: 0 +Line 13116: 0 +Line 13117: 0 +Line 13118: 0 +Line 13119: 0 +Line 13120: 0 +Line 13121: 0 +Line 13122: 1 +Line 13123: 1 +Line 13124: 1 +Line 13125: 0 +Line 13126: 1 +Line 13127: 1 +Line 13128: 0 +Line 13129: 0 +Line 13130: 1 +Line 13131: 0 +Line 13132: 1 +Line 13133: 0 +Line 13134: 0 +Line 13135: 0 +Line 13136: 0 +Line 13137: 0 +Line 13138: 0 +Line 13139: 0 +Line 13140: 0 +Line 13141: 0 +Line 13142: 0 +Line 13143: 0 +Line 13144: 0 +Line 13145: 0 +Line 13146: 0 +Line 13147: 0 +Line 13148: 0 +Line 13149: 0 +Line 13150: 0 +Line 13151: 0 +Line 13152: 0 +Line 13153: 0 +Line 13154: 1 +Line 13155: 0 +Line 13156: 0 +Line 13157: 0 +Line 13158: 1 +Line 13159: 1 +Line 13160: 0 +Line 13161: 0 +Line 13162: 1 +Line 13163: 0 +Line 13164: 1 +Line 13165: 0 +Line 13166: 0 +Line 13167: 0 +Line 13168: 0 +Line 13169: 0 +Line 13170: 0 +Line 13171: 0 +Line 13172: 0 +Line 13173: 0 +Line 13174: 0 +Line 13175: 0 +Line 13176: 0 +Line 13177: 0 +Line 13178: 0 +Line 13179: 0 +Line 13180: 0 +Line 13181: 0 +Line 13182: 0 +Line 13183: 0 +Line 13184: 0 +Line 13185: 0 +Line 13186: 0 +Line 13187: 0 +Line 13188: 1 +Line 13189: 0 +Line 13190: 1 +Line 13191: 1 +Line 13192: 0 +Line 13193: 0 +Line 13194: 1 +Line 13195: 0 +Line 13196: 0 +Line 13197: 1 +Line 13198: 1 +Line 13199: 1 +Line 13200: 0 +Line 13201: 0 +Line 13202: 0 +Line 13203: 0 +Line 13204: 0 +Line 13205: 0 +Line 13206: 0 +Line 13207: 0 +Line 13208: 0 +Line 13209: 0 +Line 13210: 0 +Line 13211: 0 +Line 13212: 0 +Line 13213: 0 +Line 13214: 0 +Line 13215: 0 +Line 13216: 0 +Line 13217: 0 +Line 13218: 0 +Line 13219: 0 +Line 13220: 0 +Line 13221: 0 +Line 13222: 0 +Line 13223: 1 +Line 13224: 1 +Line 13225: 0 +Line 13226: 0 +Line 13227: 1 +Line 13228: 1 +Line 13229: 0 +Line 13230: 0 +Line 13231: 1 +Line 13232: 0 +Line 13233: 0 +Line 13234: 0 +Line 13235: 0 +Line 13236: 0 +Line 13237: 0 +Line 13238: 0 +Line 13239: 0 +Line 13240: 0 +Line 13241: 0 +Line 13242: 0 +Line 13243: 0 +Line 13244: 0 +Line 13245: 0 +Line 13246: 0 +Line 13247: 0 +Send ENVE_DATA1_FILE +write_item 0000000000000000000011010000000000000000000000000000000000000000 +write_item 63: 0 +write_item 62: 0 +write_item 61: 0 +write_item 60: 0 +write_item 59: 0 +write_item 58: 0 +write_item 57: 0 +write_item 56: 0 +write_item 55: 0 +write_item 54: 0 +write_item 53: 0 +write_item 52: 0 +write_item 51: 0 +write_item 50: 0 +write_item 49: 0 +write_item 48: 0 +write_item 47: 0 +write_item 46: 0 +write_item 45: 0 +write_item 44: 0 +write_item 43: 1 +write_item 42: 1 +write_item 41: 0 +write_item 40: 1 +write_item 39: 0 +write_item 38: 0 +write_item 37: 0 +write_item 36: 0 +write_item 35: 0 +write_item 34: 0 +write_item 33: 0 +write_item 32: 0 +write_item 31: 0 +write_item 30: 0 +write_item 29: 0 +write_item 28: 0 +write_item 27: 0 +write_item 26: 0 +write_item 25: 0 +write_item 24: 0 +write_item 23: 0 +write_item 22: 0 +write_item 21: 0 +write_item 20: 0 +write_item 19: 0 +write_item 18: 0 +write_item 17: 0 +write_item 16: 0 +write_item 15: 0 +write_item 14: 0 +write_item 13: 0 +write_item 12: 0 +write_item 11: 0 +write_item 10: 0 +write_item 9: 0 +write_item 8: 0 +write_item 7: 0 +write_item 6: 0 +write_item 5: 0 +write_item 4: 0 +write_item 3: 0 +write_item 2: 0 +write_item 1: 0 +write_item 0: 0 +reg 0: 0 +reg 1: 0 +reg 2: 0 +reg 3: 0 +reg 4: 0 +reg 5: 0 +reg 6: 0 +reg 7: 0 +reg 8: 0 +reg 9: 0 +reg 10: 0 +reg 11: 0 +reg 12: 0 +reg 13: 0 +reg 14: 0 +reg 15: 0 +reg 16: 0 +reg 17: 0 +reg 18: 0 +reg 19: 0 +reg 20: 1 +reg 21: 1 +reg 22: 0 +reg 23: 1 +reg 24: 0 +reg 25: 0 +reg 26: 0 +reg 27: 0 +reg 28: 0 +reg 29: 0 +reg 30: 0 +reg 31: 0 +reg 32: 0 +reg 33: 0 +reg 34: 0 +reg 35: 0 +reg 36: 0 +reg 37: 0 +reg 38: 0 +reg 39: 0 +reg 40: 0 +reg 41: 0 +reg 42: 0 +reg 43: 0 +reg 44: 0 +reg 45: 0 +reg 46: 0 +reg 47: 0 +reg 48: 0 +reg 49: 0 +reg 50: 0 +reg 51: 0 +reg 52: 0 +reg 53: 0 +reg 54: 0 +reg 55: 0 +reg 56: 0 +reg 57: 0 +reg 58: 0 +reg 59: 0 +reg 60: 0 +reg 61: 0 +reg 62: 0 +reg 63: 0 +Line 0: 1 +Line 1: 1 +Line 2: 1 +Line 3: 0 +Line 4: 0 +Line 5: 1 +Line 6: 0 +Line 7: 0 +Line 8: 0 +Line 9: 0 +Line 10: 0 +Line 11: 0 +Line 12: 0 +Line 13: 0 +Line 14: 0 +Line 15: 0 +Line 16: 0 +Line 17: 0 +Line 18: 0 +Line 19: 0 +Line 20: 0 +Line 21: 0 +Line 22: 0 +Line 23: 0 +Line 24: 0 +Line 25: 0 +Line 26: 0 +Line 27: 0 +Line 28: 0 +Line 29: 0 +Line 30: 0 +Line 31: 0 +Line 32: 0 +Line 33: 0 +Line 34: 0 +Line 35: 0 +Line 36: 0 +Line 37: 0 +Line 38: 0 +Line 39: 0 +Line 40: 0 +Line 41: 0 +Line 42: 0 +Line 43: 0 +Line 44: 0 +Line 45: 0 +Line 46: 0 +Line 47: 0 +Line 48: 0 +Line 49: 0 +Line 50: 0 +Line 51: 0 +Line 52: 0 +Line 53: 0 +Line 54: 0 +Line 55: 0 +Line 56: 0 +Line 57: 0 +Line 58: 0 +Line 59: 0 +Line 60: 0 +Line 61: 0 +Line 62: 0 +Line 63: 0 +Line 64: 0 +Line 65: 0 +Line 66: 0 +Line 67: 0 +Line 68: 0 +Line 69: 0 +Line 70: 0 +Line 71: 1 +Line 72: 1 +Line 73: 1 +Line 74: 1 +Line 75: 0 +Line 76: 0 +Line 77: 1 +Line 78: 1 +Line 79: 1 +Line 80: 0 +Line 81: 0 +Line 82: 0 +Line 83: 0 +Line 84: 0 +Line 85: 1 +Line 86: 0 +Line 87: 1 +Line 88: 0 +Line 89: 0 +Line 90: 0 +Line 91: 0 +Line 92: 1 +Line 93: 1 +Line 94: 1 +Line 95: 0 +Line 96: 0 +Line 97: 0 +Line 98: 0 +Line 99: 0 +Line 100: 0 +Line 101: 1 +Line 102: 1 +Line 103: 1 +Line 104: 0 +Line 105: 1 +Line 106: 1 +Line 107: 0 +Line 108: 1 +Line 109: 0 +Line 110: 0 +Line 111: 1 +Line 112: 0 +Line 113: 0 +Line 114: 0 +Line 115: 0 +Line 116: 1 +Line 117: 0 +Line 118: 0 +Line 119: 1 +Line 120: 1 +Line 121: 0 +Line 122: 0 +Line 123: 1 +Line 124: 0 +Line 125: 0 +Line 126: 0 +Line 127: 1 +Line 128: 0 +Line 129: 0 +Line 130: 0 +Line 131: 0 +Line 132: 1 +Line 133: 1 +Line 134: 1 +Line 135: 1 +Line 136: 1 +Line 137: 1 +Line 138: 1 +Line 139: 0 +Line 140: 1 +Line 141: 1 +Line 142: 0 +Line 143: 1 +Line 144: 0 +Line 145: 0 +Line 146: 0 +Line 147: 0 +Line 148: 1 +Line 149: 1 +Line 150: 0 +Line 151: 1 +Line 152: 0 +Line 153: 0 +Line 154: 0 +Line 155: 0 +Line 156: 1 +Line 157: 0 +Line 158: 1 +Line 159: 0 +Line 160: 0 +Line 161: 0 +Line 162: 0 +Line 163: 1 +Line 164: 1 +Line 165: 0 +Line 166: 1 +Line 167: 0 +Line 168: 1 +Line 169: 0 +Line 170: 0 +Line 171: 0 +Line 172: 0 +Line 173: 1 +Line 174: 1 +Line 175: 0 +Line 176: 0 +Line 177: 0 +Line 178: 0 +Line 179: 0 +Line 180: 1 +Line 181: 1 +Line 182: 1 +Line 183: 1 +Line 184: 0 +Line 185: 0 +Line 186: 0 +Line 187: 1 +Line 188: 1 +Line 189: 0 +Line 190: 1 +Line 191: 0 +Line 192: 0 +Line 193: 0 +Line 194: 1 +Line 195: 0 +Line 196: 0 +Line 197: 1 +Line 198: 1 +Line 199: 0 +Line 200: 0 +Line 201: 0 +Line 202: 0 +Line 203: 0 +Line 204: 1 +Line 205: 1 +Line 206: 1 +Line 207: 1 +Line 208: 0 +Line 209: 0 +Line 210: 0 +Line 211: 0 +Line 212: 1 +Line 213: 1 +Line 214: 1 +Line 215: 1 +Line 216: 1 +Line 217: 0 +Line 218: 0 +Line 219: 0 +Line 220: 0 +Line 221: 1 +Line 222: 1 +Line 223: 0 +Line 224: 0 +Line 225: 0 +Line 226: 1 +Line 227: 1 +Line 228: 0 +Line 229: 0 +Line 230: 0 +Line 231: 1 +Line 232: 0 +Line 233: 1 +Line 234: 0 +Line 235: 0 +Line 236: 0 +Line 237: 1 +Line 238: 1 +Line 239: 1 +Line 240: 0 +Line 241: 0 +Line 242: 0 +Line 243: 0 +Line 244: 1 +Line 245: 1 +Line 246: 1 +Line 247: 0 +Line 248: 0 +Line 249: 1 +Line 250: 0 +Line 251: 0 +Line 252: 0 +Line 253: 1 +Line 254: 0 +Line 255: 0 +Line 256: 0 +Line 257: 0 +Line 258: 1 +Line 259: 1 +Line 260: 1 +Line 261: 0 +Line 262: 1 +Line 263: 0 +Line 264: 1 +Line 265: 1 +Line 266: 1 +Line 267: 1 +Line 268: 0 +Line 269: 1 +Line 270: 1 +Line 271: 1 +Line 272: 0 +Line 273: 0 +Line 274: 0 +Line 275: 0 +Line 276: 1 +Line 277: 0 +Line 278: 1 +Line 279: 1 +Line 280: 0 +Line 281: 1 +Line 282: 1 +Line 283: 1 +Line 284: 0 +Line 285: 1 +Line 286: 1 +Line 287: 0 +Line 288: 0 +Line 289: 1 +Line 290: 0 +Line 291: 0 +Line 292: 0 +Line 293: 0 +Line 294: 1 +Line 295: 0 +Line 296: 0 +Line 297: 0 +Line 298: 0 +Line 299: 1 +Line 300: 0 +Line 301: 0 +Line 302: 1 +Line 303: 1 +Line 304: 0 +Line 305: 0 +Line 306: 0 +Line 307: 0 +Line 308: 0 +Line 309: 1 +Line 310: 1 +Line 311: 1 +Line 312: 0 +Line 313: 1 +Line 314: 1 +Line 315: 0 +Line 316: 1 +Line 317: 0 +Line 318: 1 +Line 319: 0 +Line 320: 0 +Line 321: 1 +Line 322: 0 +Line 323: 0 +Line 324: 0 +Line 325: 1 +Line 326: 0 +Line 327: 1 +Line 328: 1 +Line 329: 1 +Line 330: 0 +Line 331: 1 +Line 332: 0 +Line 333: 1 +Line 334: 0 +Line 335: 1 +Line 336: 0 +Line 337: 0 +Line 338: 0 +Line 339: 0 +Line 340: 0 +Line 341: 0 +Line 342: 1 +Line 343: 0 +Line 344: 1 +Line 345: 0 +Line 346: 0 +Line 347: 1 +Line 348: 0 +Line 349: 0 +Line 350: 0 +Line 351: 0 +Line 352: 0 +Line 353: 1 +Line 354: 0 +Line 355: 0 +Line 356: 0 +Line 357: 1 +Line 358: 0 +Line 359: 1 +Line 360: 1 +Line 361: 1 +Line 362: 0 +Line 363: 1 +Line 364: 0 +Line 365: 1 +Line 366: 0 +Line 367: 1 +Line 368: 1 +Line 369: 1 +Line 370: 1 +Line 371: 1 +Line 372: 1 +Line 373: 1 +Line 374: 0 +Line 375: 1 +Line 376: 0 +Line 377: 1 +Line 378: 1 +Line 379: 1 +Line 380: 0 +Line 381: 0 +Line 382: 0 +Line 383: 0 +Line 384: 0 +Line 385: 1 +Line 386: 0 +Line 387: 0 +Line 388: 0 +Line 389: 0 +Line 390: 1 +Line 391: 0 +Line 392: 0 +Line 393: 0 +Line 394: 0 +Line 395: 1 +Line 396: 0 +Line 397: 0 +Line 398: 1 +Line 399: 1 +Line 400: 1 +Line 401: 1 +Line 402: 1 +Line 403: 1 +Line 404: 1 +Line 405: 0 +Line 406: 0 +Line 407: 0 +Line 408: 1 +Line 409: 0 +Line 410: 0 +Line 411: 1 +Line 412: 0 +Line 413: 1 +Line 414: 1 +Line 415: 0 +Line 416: 0 +Line 417: 0 +Line 418: 1 +Line 419: 1 +Line 420: 1 +Line 421: 0 +Line 422: 1 +Line 423: 0 +Line 424: 1 +Line 425: 1 +Line 426: 1 +Line 427: 1 +Line 428: 0 +Line 429: 1 +Line 430: 1 +Line 431: 1 +Line 432: 1 +Line 433: 1 +Line 434: 1 +Line 435: 1 +Line 436: 0 +Line 437: 1 +Line 438: 0 +Line 439: 0 +Line 440: 1 +Line 441: 0 +Line 442: 0 +Line 443: 0 +Line 444: 1 +Line 445: 0 +Line 446: 1 +Line 447: 0 +Line 448: 0 +Line 449: 0 +Line 450: 1 +Line 451: 1 +Line 452: 0 +Line 453: 0 +Line 454: 0 +Line 455: 1 +Line 456: 0 +Line 457: 1 +Line 458: 0 +Line 459: 0 +Line 460: 0 +Line 461: 1 +Line 462: 1 +Line 463: 1 +Line 464: 1 +Line 465: 1 +Line 466: 1 +Line 467: 1 +Line 468: 0 +Line 469: 0 +Line 470: 0 +Line 471: 1 +Line 472: 1 +Line 473: 0 +Line 474: 1 +Line 475: 1 +Line 476: 1 +Line 477: 1 +Line 478: 0 +Line 479: 0 +Line 480: 0 +Line 481: 0 +Line 482: 1 +Line 483: 0 +Line 484: 0 +Line 485: 1 +Line 486: 1 +Line 487: 0 +Line 488: 0 +Line 489: 0 +Line 490: 0 +Line 491: 0 +Line 492: 1 +Line 493: 1 +Line 494: 1 +Line 495: 1 +Line 496: 1 +Line 497: 1 +Line 498: 1 +Line 499: 1 +Line 500: 0 +Line 501: 0 +Line 502: 0 +Line 503: 0 +Line 504: 0 +Line 505: 1 +Line 506: 1 +Line 507: 1 +Line 508: 1 +Line 509: 0 +Line 510: 1 +Line 511: 0 +Line 512: 0 +Line 513: 0 +Line 514: 0 +Line 515: 1 +Line 516: 1 +Line 517: 0 +Line 518: 1 +Line 519: 0 +Line 520: 1 +Line 521: 0 +Line 522: 0 +Line 523: 0 +Line 524: 0 +Line 525: 1 +Line 526: 1 +Line 527: 0 +Line 528: 1 +Line 529: 1 +Line 530: 1 +Line 531: 1 +Line 532: 0 +Line 533: 0 +Line 534: 0 +Line 535: 0 +Line 536: 1 +Line 537: 1 +Line 538: 1 +Line 539: 0 +Line 540: 0 +Line 541: 1 +Line 542: 1 +Line 543: 0 +Line 544: 0 +Line 545: 0 +Line 546: 0 +Line 547: 0 +Line 548: 1 +Line 549: 1 +Line 550: 1 +Line 551: 1 +Line 552: 1 +Line 553: 1 +Line 554: 1 +Line 555: 0 +Line 556: 1 +Line 557: 1 +Line 558: 0 +Line 559: 1 +Line 560: 1 +Line 561: 1 +Line 562: 1 +Line 563: 1 +Line 564: 0 +Line 565: 0 +Line 566: 1 +Line 567: 0 +Line 568: 1 +Line 569: 1 +Line 570: 1 +Line 571: 1 +Line 572: 0 +Line 573: 1 +Line 574: 1 +Line 575: 0 +Line 576: 0 +Line 577: 0 +Line 578: 0 +Line 579: 0 +Line 580: 0 +Line 581: 1 +Line 582: 1 +Line 583: 1 +Line 584: 0 +Line 585: 1 +Line 586: 1 +Line 587: 0 +Line 588: 1 +Line 589: 0 +Line 590: 0 +Line 591: 1 +Line 592: 1 +Line 593: 1 +Line 594: 1 +Line 595: 1 +Line 596: 0 +Line 597: 1 +Line 598: 1 +Line 599: 0 +Line 600: 0 +Line 601: 1 +Line 602: 1 +Line 603: 0 +Line 604: 1 +Line 605: 1 +Line 606: 1 +Line 607: 1 +Line 608: 0 +Line 609: 0 +Line 610: 0 +Line 611: 0 +Line 612: 0 +Line 613: 0 +Line 614: 0 +Line 615: 1 +Line 616: 1 +Line 617: 1 +Line 618: 1 +Line 619: 0 +Line 620: 0 +Line 621: 1 +Line 622: 1 +Line 623: 1 +Line 624: 1 +Line 625: 1 +Line 626: 1 +Line 627: 1 +Line 628: 1 +Line 629: 0 +Line 630: 1 +Line 631: 0 +Line 632: 1 +Line 633: 1 +Line 634: 1 +Line 635: 1 +Line 636: 0 +Line 637: 0 +Line 638: 1 +Line 639: 0 +Line 640: 0 +Line 641: 0 +Line 642: 0 +Line 643: 0 +Line 644: 0 +Line 645: 0 +Line 646: 0 +Line 647: 0 +Line 648: 0 +Line 649: 0 +Line 650: 0 +Line 651: 0 +Line 652: 0 +Line 653: 0 +Line 654: 0 +Line 655: 0 +Line 656: 0 +Line 657: 0 +Line 658: 0 +Line 659: 0 +Line 660: 0 +Line 661: 0 +Line 662: 0 +Line 663: 0 +Line 664: 0 +Line 665: 0 +Line 666: 0 +Line 667: 0 +Line 668: 0 +Line 669: 0 +Line 670: 0 +Line 671: 0 +Line 672: 0 +Line 673: 1 +Line 674: 0 +Line 675: 0 +Line 676: 0 +Line 677: 1 +Line 678: 1 +Line 679: 0 +Line 680: 0 +Line 681: 1 +Line 682: 0 +Line 683: 1 +Line 684: 0 +Line 685: 0 +Line 686: 0 +Line 687: 0 +Line 688: 0 +Line 689: 0 +Line 690: 0 +Line 691: 0 +Line 692: 0 +Line 693: 0 +Line 694: 0 +Line 695: 0 +Line 696: 0 +Line 697: 0 +Line 698: 0 +Line 699: 0 +Line 700: 0 +Line 701: 0 +Line 702: 0 +Line 703: 0 +Line 704: 0 +Line 705: 1 +Line 706: 0 +Line 707: 0 +Line 708: 0 +Line 709: 1 +Line 710: 1 +Line 711: 0 +Line 712: 0 +Line 713: 1 +Line 714: 0 +Line 715: 1 +Line 716: 0 +Line 717: 0 +Line 718: 0 +Line 719: 0 +Line 720: 0 +Line 721: 0 +Line 722: 0 +Line 723: 0 +Line 724: 0 +Line 725: 0 +Line 726: 0 +Line 727: 0 +Line 728: 0 +Line 729: 0 +Line 730: 0 +Line 731: 0 +Line 732: 0 +Line 733: 0 +Line 734: 0 +Line 735: 0 +Line 736: 0 +Line 737: 1 +Line 738: 0 +Line 739: 0 +Line 740: 0 +Line 741: 1 +Line 742: 1 +Line 743: 0 +Line 744: 0 +Line 745: 1 +Line 746: 0 +Line 747: 1 +Line 748: 0 +Line 749: 0 +Line 750: 0 +Line 751: 0 +Line 752: 0 +Line 753: 0 +Line 754: 0 +Line 755: 0 +Line 756: 0 +Line 757: 0 +Line 758: 0 +Line 759: 0 +Line 760: 0 +Line 761: 0 +Line 762: 0 +Line 763: 0 +Line 764: 0 +Line 765: 0 +Line 766: 0 +Line 767: 0 +Line 768: 0 +Line 769: 1 +Line 770: 0 +Line 771: 0 +Line 772: 0 +Line 773: 1 +Line 774: 1 +Line 775: 0 +Line 776: 0 +Line 777: 1 +Line 778: 0 +Line 779: 1 +Line 780: 0 +Line 781: 0 +Line 782: 0 +Line 783: 0 +Line 784: 0 +Line 785: 0 +Line 786: 0 +Line 787: 0 +Line 788: 0 +Line 789: 0 +Line 790: 0 +Line 791: 0 +Line 792: 0 +Line 793: 0 +Line 794: 0 +Line 795: 0 +Line 796: 0 +Line 797: 0 +Line 798: 0 +Line 799: 0 +Line 800: 0 +Line 801: 1 +Line 802: 0 +Line 803: 0 +Line 804: 0 +Line 805: 1 +Line 806: 1 +Line 807: 0 +Line 808: 0 +Line 809: 1 +Line 810: 0 +Line 811: 1 +Line 812: 0 +Line 813: 0 +Line 814: 0 +Line 815: 0 +Line 816: 0 +Line 817: 0 +Line 818: 0 +Line 819: 0 +Line 820: 0 +Line 821: 0 +Line 822: 0 +Line 823: 0 +Line 824: 0 +Line 825: 0 +Line 826: 0 +Line 827: 0 +Line 828: 0 +Line 829: 0 +Line 830: 0 +Line 831: 0 +Line 832: 0 +Line 833: 1 +Line 834: 0 +Line 835: 0 +Line 836: 0 +Line 837: 1 +Line 838: 1 +Line 839: 0 +Line 840: 0 +Line 841: 1 +Line 842: 0 +Line 843: 1 +Line 844: 0 +Line 845: 0 +Line 846: 0 +Line 847: 0 +Line 848: 0 +Line 849: 0 +Line 850: 0 +Line 851: 0 +Line 852: 0 +Line 853: 0 +Line 854: 0 +Line 855: 0 +Line 856: 0 +Line 857: 0 +Line 858: 0 +Line 859: 0 +Line 860: 0 +Line 861: 0 +Line 862: 0 +Line 863: 0 +Line 864: 0 +Line 865: 1 +Line 866: 0 +Line 867: 0 +Line 868: 0 +Line 869: 1 +Line 870: 1 +Line 871: 0 +Line 872: 0 +Line 873: 1 +Line 874: 0 +Line 875: 1 +Line 876: 0 +Line 877: 0 +Line 878: 0 +Line 879: 0 +Line 880: 0 +Line 881: 0 +Line 882: 0 +Line 883: 0 +Line 884: 0 +Line 885: 0 +Line 886: 0 +Line 887: 0 +Line 888: 0 +Line 889: 0 +Line 890: 0 +Line 891: 0 +Line 892: 0 +Line 893: 0 +Line 894: 0 +Line 895: 0 +Line 896: 0 +Line 897: 1 +Line 898: 0 +Line 899: 0 +Line 900: 0 +Line 901: 1 +Line 902: 1 +Line 903: 0 +Line 904: 0 +Line 905: 1 +Line 906: 0 +Line 907: 1 +Line 908: 0 +Line 909: 0 +Line 910: 0 +Line 911: 0 +Line 912: 0 +Line 913: 0 +Line 914: 0 +Line 915: 0 +Line 916: 0 +Line 917: 0 +Line 918: 0 +Line 919: 0 +Line 920: 0 +Line 921: 0 +Line 922: 0 +Line 923: 0 +Line 924: 0 +Line 925: 0 +Line 926: 0 +Line 927: 0 +Line 928: 0 +Line 929: 1 +Line 930: 0 +Line 931: 0 +Line 932: 0 +Line 933: 1 +Line 934: 1 +Line 935: 0 +Line 936: 0 +Line 937: 1 +Line 938: 0 +Line 939: 1 +Line 940: 0 +Line 941: 0 +Line 942: 0 +Line 943: 0 +Line 944: 0 +Line 945: 0 +Line 946: 0 +Line 947: 0 +Line 948: 0 +Line 949: 0 +Line 950: 0 +Line 951: 0 +Line 952: 0 +Line 953: 0 +Line 954: 0 +Line 955: 0 +Line 956: 0 +Line 957: 0 +Line 958: 0 +Line 959: 0 +Line 960: 0 +Line 961: 1 +Line 962: 0 +Line 963: 0 +Line 964: 0 +Line 965: 1 +Line 966: 1 +Line 967: 0 +Line 968: 0 +Line 969: 1 +Line 970: 0 +Line 971: 1 +Line 972: 0 +Line 973: 0 +Line 974: 0 +Line 975: 0 +Line 976: 0 +Line 977: 0 +Line 978: 0 +Line 979: 0 +Line 980: 0 +Line 981: 0 +Line 982: 0 +Line 983: 0 +Line 984: 0 +Line 985: 0 +Line 986: 0 +Line 987: 0 +Line 988: 0 +Line 989: 0 +Line 990: 0 +Line 991: 0 +Line 992: 0 +Line 993: 1 +Line 994: 0 +Line 995: 0 +Line 996: 0 +Line 997: 1 +Line 998: 1 +Line 999: 0 +Line 1000: 0 +Line 1001: 1 +Line 1002: 0 +Line 1003: 1 +Line 1004: 0 +Line 1005: 0 +Line 1006: 0 +Line 1007: 0 +Line 1008: 0 +Line 1009: 0 +Line 1010: 0 +Line 1011: 0 +Line 1012: 0 +Line 1013: 0 +Line 1014: 0 +Line 1015: 0 +Line 1016: 0 +Line 1017: 0 +Line 1018: 0 +Line 1019: 0 +Line 1020: 0 +Line 1021: 0 +Line 1022: 0 +Line 1023: 0 +Line 1024: 0 +Line 1025: 1 +Line 1026: 0 +Line 1027: 0 +Line 1028: 0 +Line 1029: 1 +Line 1030: 1 +Line 1031: 0 +Line 1032: 0 +Line 1033: 1 +Line 1034: 0 +Line 1035: 1 +Line 1036: 0 +Line 1037: 0 +Line 1038: 0 +Line 1039: 0 +Line 1040: 0 +Line 1041: 0 +Line 1042: 0 +Line 1043: 0 +Line 1044: 0 +Line 1045: 0 +Line 1046: 0 +Line 1047: 0 +Line 1048: 0 +Line 1049: 0 +Line 1050: 0 +Line 1051: 0 +Line 1052: 0 +Line 1053: 0 +Line 1054: 0 +Line 1055: 0 +Line 1056: 0 +Line 1057: 1 +Line 1058: 0 +Line 1059: 0 +Line 1060: 0 +Line 1061: 1 +Line 1062: 1 +Line 1063: 0 +Line 1064: 0 +Line 1065: 1 +Line 1066: 0 +Line 1067: 1 +Line 1068: 0 +Line 1069: 0 +Line 1070: 0 +Line 1071: 0 +Line 1072: 0 +Line 1073: 0 +Line 1074: 0 +Line 1075: 0 +Line 1076: 0 +Line 1077: 0 +Line 1078: 0 +Line 1079: 0 +Line 1080: 0 +Line 1081: 0 +Line 1082: 0 +Line 1083: 0 +Line 1084: 0 +Line 1085: 0 +Line 1086: 0 +Line 1087: 0 +Line 1088: 0 +Line 1089: 1 +Line 1090: 0 +Line 1091: 0 +Line 1092: 0 +Line 1093: 1 +Line 1094: 1 +Line 1095: 0 +Line 1096: 0 +Line 1097: 1 +Line 1098: 0 +Line 1099: 1 +Line 1100: 0 +Line 1101: 0 +Line 1102: 0 +Line 1103: 0 +Line 1104: 0 +Line 1105: 0 +Line 1106: 0 +Line 1107: 0 +Line 1108: 0 +Line 1109: 0 +Line 1110: 0 +Line 1111: 0 +Line 1112: 0 +Line 1113: 0 +Line 1114: 0 +Line 1115: 0 +Line 1116: 0 +Line 1117: 0 +Line 1118: 0 +Line 1119: 0 +Line 1120: 0 +Line 1121: 1 +Line 1122: 0 +Line 1123: 0 +Line 1124: 0 +Line 1125: 1 +Line 1126: 1 +Line 1127: 0 +Line 1128: 0 +Line 1129: 1 +Line 1130: 0 +Line 1131: 1 +Line 1132: 0 +Line 1133: 0 +Line 1134: 0 +Line 1135: 0 +Line 1136: 0 +Line 1137: 0 +Line 1138: 0 +Line 1139: 0 +Line 1140: 0 +Line 1141: 0 +Line 1142: 0 +Line 1143: 0 +Line 1144: 0 +Line 1145: 0 +Line 1146: 0 +Line 1147: 0 +Line 1148: 0 +Line 1149: 0 +Line 1150: 0 +Line 1151: 0 +Line 1152: 0 +Line 1153: 1 +Line 1154: 0 +Line 1155: 0 +Line 1156: 0 +Line 1157: 1 +Line 1158: 1 +Line 1159: 0 +Line 1160: 0 +Line 1161: 1 +Line 1162: 0 +Line 1163: 1 +Line 1164: 0 +Line 1165: 0 +Line 1166: 0 +Line 1167: 0 +Line 1168: 0 +Line 1169: 0 +Line 1170: 0 +Line 1171: 0 +Line 1172: 0 +Line 1173: 0 +Line 1174: 0 +Line 1175: 0 +Line 1176: 0 +Line 1177: 0 +Line 1178: 0 +Line 1179: 0 +Line 1180: 0 +Line 1181: 0 +Line 1182: 0 +Line 1183: 0 +Line 1184: 0 +Line 1185: 1 +Line 1186: 0 +Line 1187: 0 +Line 1188: 0 +Line 1189: 1 +Line 1190: 1 +Line 1191: 0 +Line 1192: 0 +Line 1193: 1 +Line 1194: 0 +Line 1195: 1 +Line 1196: 0 +Line 1197: 0 +Line 1198: 0 +Line 1199: 0 +Line 1200: 0 +Line 1201: 0 +Line 1202: 0 +Line 1203: 0 +Line 1204: 0 +Line 1205: 0 +Line 1206: 0 +Line 1207: 0 +Line 1208: 0 +Line 1209: 0 +Line 1210: 0 +Line 1211: 0 +Line 1212: 0 +Line 1213: 0 +Line 1214: 0 +Line 1215: 0 +Line 1216: 0 +Line 1217: 1 +Line 1218: 0 +Line 1219: 0 +Line 1220: 0 +Line 1221: 1 +Line 1222: 1 +Line 1223: 0 +Line 1224: 0 +Line 1225: 1 +Line 1226: 0 +Line 1227: 1 +Line 1228: 0 +Line 1229: 0 +Line 1230: 0 +Line 1231: 0 +Line 1232: 0 +Line 1233: 0 +Line 1234: 0 +Line 1235: 0 +Line 1236: 0 +Line 1237: 0 +Line 1238: 0 +Line 1239: 0 +Line 1240: 0 +Line 1241: 0 +Line 1242: 0 +Line 1243: 0 +Line 1244: 0 +Line 1245: 0 +Line 1246: 0 +Line 1247: 0 +Line 1248: 0 +Line 1249: 1 +Line 1250: 0 +Line 1251: 0 +Line 1252: 0 +Line 1253: 1 +Line 1254: 1 +Line 1255: 0 +Line 1256: 0 +Line 1257: 1 +Line 1258: 0 +Line 1259: 1 +Line 1260: 0 +Line 1261: 0 +Line 1262: 0 +Line 1263: 0 +Line 1264: 0 +Line 1265: 0 +Line 1266: 0 +Line 1267: 0 +Line 1268: 0 +Line 1269: 0 +Line 1270: 0 +Line 1271: 0 +Line 1272: 0 +Line 1273: 0 +Line 1274: 0 +Line 1275: 0 +Line 1276: 0 +Line 1277: 0 +Line 1278: 0 +Line 1279: 0 +Line 1280: 0 +Line 1281: 1 +Line 1282: 0 +Line 1283: 0 +Line 1284: 0 +Line 1285: 1 +Line 1286: 1 +Line 1287: 0 +Line 1288: 0 +Line 1289: 1 +Line 1290: 0 +Line 1291: 1 +Line 1292: 0 +Line 1293: 0 +Line 1294: 0 +Line 1295: 0 +Line 1296: 0 +Line 1297: 0 +Line 1298: 0 +Line 1299: 0 +Line 1300: 0 +Line 1301: 0 +Line 1302: 0 +Line 1303: 0 +Line 1304: 0 +Line 1305: 0 +Line 1306: 0 +Line 1307: 0 +Line 1308: 0 +Line 1309: 0 +Line 1310: 0 +Line 1311: 0 +Line 1312: 0 +Line 1313: 1 +Line 1314: 0 +Line 1315: 0 +Line 1316: 0 +Line 1317: 1 +Line 1318: 1 +Line 1319: 0 +Line 1320: 0 +Line 1321: 1 +Line 1322: 0 +Line 1323: 1 +Line 1324: 0 +Line 1325: 0 +Line 1326: 0 +Line 1327: 0 +Line 1328: 0 +Line 1329: 0 +Line 1330: 0 +Line 1331: 0 +Line 1332: 0 +Line 1333: 0 +Line 1334: 0 +Line 1335: 0 +Line 1336: 0 +Line 1337: 0 +Line 1338: 0 +Line 1339: 0 +Line 1340: 0 +Line 1341: 0 +Line 1342: 0 +Line 1343: 0 +Line 1344: 0 +Line 1345: 1 +Line 1346: 0 +Line 1347: 0 +Line 1348: 0 +Line 1349: 1 +Line 1350: 1 +Line 1351: 0 +Line 1352: 0 +Line 1353: 1 +Line 1354: 0 +Line 1355: 1 +Line 1356: 0 +Line 1357: 0 +Line 1358: 0 +Line 1359: 0 +Line 1360: 0 +Line 1361: 0 +Line 1362: 0 +Line 1363: 0 +Line 1364: 0 +Line 1365: 0 +Line 1366: 0 +Line 1367: 0 +Line 1368: 0 +Line 1369: 0 +Line 1370: 0 +Line 1371: 0 +Line 1372: 0 +Line 1373: 0 +Line 1374: 0 +Line 1375: 0 +Line 1376: 0 +Line 1377: 1 +Line 1378: 0 +Line 1379: 0 +Line 1380: 0 +Line 1381: 1 +Line 1382: 1 +Line 1383: 0 +Line 1384: 0 +Line 1385: 1 +Line 1386: 0 +Line 1387: 1 +Line 1388: 0 +Line 1389: 0 +Line 1390: 0 +Line 1391: 0 +Line 1392: 0 +Line 1393: 0 +Line 1394: 0 +Line 1395: 0 +Line 1396: 0 +Line 1397: 0 +Line 1398: 0 +Line 1399: 0 +Line 1400: 0 +Line 1401: 0 +Line 1402: 0 +Line 1403: 0 +Line 1404: 0 +Line 1405: 0 +Line 1406: 0 +Line 1407: 0 +Line 1408: 0 +Line 1409: 1 +Line 1410: 0 +Line 1411: 0 +Line 1412: 0 +Line 1413: 1 +Line 1414: 1 +Line 1415: 0 +Line 1416: 0 +Line 1417: 1 +Line 1418: 0 +Line 1419: 1 +Line 1420: 0 +Line 1421: 0 +Line 1422: 0 +Line 1423: 0 +Line 1424: 0 +Line 1425: 0 +Line 1426: 0 +Line 1427: 0 +Line 1428: 0 +Line 1429: 0 +Line 1430: 0 +Line 1431: 0 +Line 1432: 0 +Line 1433: 0 +Line 1434: 0 +Line 1435: 0 +Line 1436: 0 +Line 1437: 0 +Line 1438: 0 +Line 1439: 0 +Line 1440: 0 +Line 1441: 1 +Line 1442: 0 +Line 1443: 0 +Line 1444: 0 +Line 1445: 1 +Line 1446: 1 +Line 1447: 0 +Line 1448: 0 +Line 1449: 1 +Line 1450: 0 +Line 1451: 1 +Line 1452: 0 +Line 1453: 0 +Line 1454: 0 +Line 1455: 0 +Line 1456: 0 +Line 1457: 0 +Line 1458: 0 +Line 1459: 0 +Line 1460: 0 +Line 1461: 0 +Line 1462: 0 +Line 1463: 0 +Line 1464: 0 +Line 1465: 0 +Line 1466: 0 +Line 1467: 0 +Line 1468: 0 +Line 1469: 0 +Line 1470: 0 +Line 1471: 0 +Line 1472: 0 +Line 1473: 0 +Line 1474: 0 +Line 1475: 1 +Line 1476: 0 +Line 1477: 1 +Line 1478: 0 +Line 1479: 0 +Line 1480: 0 +Line 1481: 0 +Line 1482: 1 +Line 1483: 0 +Line 1484: 1 +Line 1485: 0 +Line 1486: 1 +Line 1487: 1 +Line 1488: 0 +Line 1489: 0 +Line 1490: 0 +Line 1491: 0 +Line 1492: 0 +Line 1493: 0 +Line 1494: 0 +Line 1495: 0 +Line 1496: 0 +Line 1497: 0 +Line 1498: 0 +Line 1499: 0 +Line 1500: 0 +Line 1501: 0 +Line 1502: 0 +Line 1503: 0 +Line 1504: 0 +Line 1505: 0 +Line 1506: 0 +Line 1507: 1 +Line 1508: 0 +Line 1509: 1 +Line 1510: 0 +Line 1511: 1 +Line 1512: 0 +Line 1513: 0 +Line 1514: 1 +Line 1515: 0 +Line 1516: 1 +Line 1517: 1 +Line 1518: 1 +Line 1519: 0 +Line 1520: 0 +Line 1521: 0 +Line 1522: 0 +Line 1523: 0 +Line 1524: 0 +Line 1525: 0 +Line 1526: 0 +Line 1527: 0 +Line 1528: 0 +Line 1529: 0 +Line 1530: 0 +Line 1531: 0 +Line 1532: 0 +Line 1533: 0 +Line 1534: 0 +Line 1535: 0 +Line 1536: 0 +Line 1537: 0 +Line 1538: 0 +Line 1539: 1 +Line 1540: 0 +Line 1541: 1 +Line 1542: 1 +Line 1543: 0 +Line 1544: 0 +Line 1545: 0 +Line 1546: 1 +Line 1547: 1 +Line 1548: 0 +Line 1549: 1 +Line 1550: 1 +Line 1551: 0 +Line 1552: 0 +Line 1553: 0 +Line 1554: 0 +Line 1555: 0 +Line 1556: 0 +Line 1557: 0 +Line 1558: 0 +Line 1559: 0 +Line 1560: 0 +Line 1561: 0 +Line 1562: 0 +Line 1563: 0 +Line 1564: 0 +Line 1565: 0 +Line 1566: 0 +Line 1567: 0 +Line 1568: 0 +Line 1569: 0 +Line 1570: 0 +Line 1571: 1 +Line 1572: 0 +Line 1573: 1 +Line 1574: 1 +Line 1575: 1 +Line 1576: 0 +Line 1577: 1 +Line 1578: 0 +Line 1579: 0 +Line 1580: 0 +Line 1581: 0 +Line 1582: 1 +Line 1583: 1 +Line 1584: 0 +Line 1585: 0 +Line 1586: 0 +Line 1587: 0 +Line 1588: 0 +Line 1589: 0 +Line 1590: 0 +Line 1591: 0 +Line 1592: 0 +Line 1593: 0 +Line 1594: 0 +Line 1595: 0 +Line 1596: 0 +Line 1597: 0 +Line 1598: 0 +Line 1599: 0 +Line 1600: 0 +Line 1601: 0 +Line 1602: 0 +Line 1603: 1 +Line 1604: 1 +Line 1605: 0 +Line 1606: 0 +Line 1607: 0 +Line 1608: 0 +Line 1609: 1 +Line 1610: 0 +Line 1611: 1 +Line 1612: 0 +Line 1613: 1 +Line 1614: 1 +Line 1615: 0 +Line 1616: 0 +Line 1617: 0 +Line 1618: 0 +Line 1619: 0 +Line 1620: 0 +Line 1621: 0 +Line 1622: 0 +Line 1623: 0 +Line 1624: 0 +Line 1625: 0 +Line 1626: 0 +Line 1627: 0 +Line 1628: 0 +Line 1629: 0 +Line 1630: 0 +Line 1631: 0 +Line 1632: 0 +Line 1633: 0 +Line 1634: 0 +Line 1635: 1 +Line 1636: 1 +Line 1637: 0 +Line 1638: 0 +Line 1639: 1 +Line 1640: 0 +Line 1641: 1 +Line 1642: 1 +Line 1643: 0 +Line 1644: 1 +Line 1645: 1 +Line 1646: 0 +Line 1647: 0 +Line 1648: 0 +Line 1649: 0 +Line 1650: 0 +Line 1651: 0 +Line 1652: 0 +Line 1653: 0 +Line 1654: 0 +Line 1655: 0 +Line 1656: 0 +Line 1657: 0 +Line 1658: 0 +Line 1659: 0 +Line 1660: 0 +Line 1661: 0 +Line 1662: 0 +Line 1663: 0 +Line 1664: 0 +Line 1665: 0 +Line 1666: 0 +Line 1667: 1 +Line 1668: 1 +Line 1669: 0 +Line 1670: 1 +Line 1671: 0 +Line 1672: 1 +Line 1673: 0 +Line 1674: 0 +Line 1675: 0 +Line 1676: 0 +Line 1677: 1 +Line 1678: 1 +Line 1679: 1 +Line 1680: 0 +Line 1681: 0 +Line 1682: 0 +Line 1683: 0 +Line 1684: 0 +Line 1685: 0 +Line 1686: 0 +Line 1687: 0 +Line 1688: 0 +Line 1689: 0 +Line 1690: 0 +Line 1691: 0 +Line 1692: 0 +Line 1693: 0 +Line 1694: 0 +Line 1695: 0 +Line 1696: 0 +Line 1697: 0 +Line 1698: 0 +Line 1699: 1 +Line 1700: 1 +Line 1701: 0 +Line 1702: 1 +Line 1703: 1 +Line 1704: 1 +Line 1705: 0 +Line 1706: 1 +Line 1707: 0 +Line 1708: 0 +Line 1709: 1 +Line 1710: 1 +Line 1711: 0 +Line 1712: 0 +Line 1713: 0 +Line 1714: 0 +Line 1715: 0 +Line 1716: 0 +Line 1717: 0 +Line 1718: 0 +Line 1719: 0 +Line 1720: 0 +Line 1721: 0 +Line 1722: 0 +Line 1723: 0 +Line 1724: 0 +Line 1725: 0 +Line 1726: 0 +Line 1727: 0 +Line 1728: 0 +Line 1729: 0 +Line 1730: 0 +Line 1731: 1 +Line 1732: 1 +Line 1733: 1 +Line 1734: 0 +Line 1735: 0 +Line 1736: 1 +Line 1737: 1 +Line 1738: 0 +Line 1739: 0 +Line 1740: 1 +Line 1741: 0 +Line 1742: 0 +Line 1743: 0 +Line 1744: 0 +Line 1745: 0 +Line 1746: 0 +Line 1747: 0 +Line 1748: 0 +Line 1749: 0 +Line 1750: 0 +Line 1751: 0 +Line 1752: 0 +Line 1753: 0 +Line 1754: 0 +Line 1755: 0 +Line 1756: 0 +Line 1757: 0 +Line 1758: 0 +Line 1759: 0 +Line 1760: 0 +Line 1761: 0 +Line 1762: 0 +Line 1763: 1 +Line 1764: 1 +Line 1765: 1 +Line 1766: 0 +Line 1767: 1 +Line 1768: 1 +Line 1769: 1 +Line 1770: 1 +Line 1771: 0 +Line 1772: 1 +Line 1773: 1 +Line 1774: 0 +Line 1775: 1 +Line 1776: 0 +Line 1777: 0 +Line 1778: 0 +Line 1779: 0 +Line 1780: 0 +Line 1781: 0 +Line 1782: 0 +Line 1783: 0 +Line 1784: 0 +Line 1785: 0 +Line 1786: 0 +Line 1787: 0 +Line 1788: 0 +Line 1789: 0 +Line 1790: 0 +Line 1791: 0 +Line 1792: 0 +Line 1793: 0 +Line 1794: 0 +Line 1795: 1 +Line 1796: 1 +Line 1797: 1 +Line 1798: 1 +Line 1799: 1 +Line 1800: 0 +Line 1801: 0 +Line 1802: 0 +Line 1803: 1 +Line 1804: 0 +Line 1805: 1 +Line 1806: 0 +Line 1807: 0 +Line 1808: 0 +Line 1809: 0 +Line 1810: 0 +Line 1811: 0 +Line 1812: 0 +Line 1813: 0 +Line 1814: 0 +Line 1815: 0 +Line 1816: 0 +Line 1817: 0 +Line 1818: 0 +Line 1819: 0 +Line 1820: 0 +Line 1821: 0 +Line 1822: 0 +Line 1823: 0 +Line 1824: 0 +Line 1825: 0 +Line 1826: 1 +Line 1827: 0 +Line 1828: 0 +Line 1829: 0 +Line 1830: 0 +Line 1831: 0 +Line 1832: 0 +Line 1833: 0 +Line 1834: 1 +Line 1835: 1 +Line 1836: 1 +Line 1837: 1 +Line 1838: 0 +Line 1839: 1 +Line 1840: 0 +Line 1841: 0 +Line 1842: 0 +Line 1843: 0 +Line 1844: 0 +Line 1845: 0 +Line 1846: 0 +Line 1847: 0 +Line 1848: 0 +Line 1849: 0 +Line 1850: 0 +Line 1851: 0 +Line 1852: 0 +Line 1853: 0 +Line 1854: 0 +Line 1855: 0 +Line 1856: 0 +Line 1857: 0 +Line 1858: 1 +Line 1859: 0 +Line 1860: 0 +Line 1861: 0 +Line 1862: 0 +Line 1863: 1 +Line 1864: 0 +Line 1865: 1 +Line 1866: 1 +Line 1867: 0 +Line 1868: 0 +Line 1869: 1 +Line 1870: 1 +Line 1871: 1 +Line 1872: 0 +Line 1873: 0 +Line 1874: 0 +Line 1875: 0 +Line 1876: 0 +Line 1877: 0 +Line 1878: 0 +Line 1879: 0 +Line 1880: 0 +Line 1881: 0 +Line 1882: 0 +Line 1883: 0 +Line 1884: 0 +Line 1885: 0 +Line 1886: 0 +Line 1887: 0 +Line 1888: 0 +Line 1889: 0 +Line 1890: 1 +Line 1891: 0 +Line 1892: 0 +Line 1893: 0 +Line 1894: 1 +Line 1895: 0 +Line 1896: 1 +Line 1897: 0 +Line 1898: 0 +Line 1899: 1 +Line 1900: 0 +Line 1901: 0 +Line 1902: 1 +Line 1903: 0 +Line 1904: 0 +Line 1905: 0 +Line 1906: 0 +Line 1907: 0 +Line 1908: 0 +Line 1909: 0 +Line 1910: 0 +Line 1911: 0 +Line 1912: 0 +Line 1913: 0 +Line 1914: 0 +Line 1915: 0 +Line 1916: 0 +Line 1917: 0 +Line 1918: 0 +Line 1919: 0 +Line 1920: 0 +Line 1921: 0 +Line 1922: 1 +Line 1923: 0 +Line 1924: 0 +Line 1925: 0 +Line 1926: 1 +Line 1927: 1 +Line 1928: 1 +Line 1929: 0 +Line 1930: 1 +Line 1931: 1 +Line 1932: 1 +Line 1933: 1 +Line 1934: 0 +Line 1935: 1 +Line 1936: 0 +Line 1937: 0 +Line 1938: 0 +Line 1939: 0 +Line 1940: 0 +Line 1941: 0 +Line 1942: 0 +Line 1943: 0 +Line 1944: 0 +Line 1945: 0 +Line 1946: 0 +Line 1947: 0 +Line 1948: 0 +Line 1949: 0 +Line 1950: 0 +Line 1951: 0 +Line 1952: 0 +Line 1953: 0 +Line 1954: 1 +Line 1955: 0 +Line 1956: 0 +Line 1957: 1 +Line 1958: 0 +Line 1959: 0 +Line 1960: 1 +Line 1961: 1 +Line 1962: 1 +Line 1963: 0 +Line 1964: 1 +Line 1965: 0 +Line 1966: 0 +Line 1967: 0 +Line 1968: 0 +Line 1969: 0 +Line 1970: 0 +Line 1971: 0 +Line 1972: 0 +Line 1973: 0 +Line 1974: 0 +Line 1975: 0 +Line 1976: 0 +Line 1977: 0 +Line 1978: 0 +Line 1979: 0 +Line 1980: 0 +Line 1981: 0 +Line 1982: 0 +Line 1983: 0 +Line 1984: 0 +Line 1985: 0 +Line 1986: 1 +Line 1987: 0 +Line 1988: 0 +Line 1989: 1 +Line 1990: 1 +Line 1991: 0 +Line 1992: 0 +Line 1993: 0 +Line 1994: 0 +Line 1995: 1 +Line 1996: 0 +Line 1997: 0 +Line 1998: 1 +Line 1999: 0 +Line 2000: 0 +Line 2001: 0 +Line 2002: 0 +Line 2003: 0 +Line 2004: 0 +Line 2005: 0 +Line 2006: 0 +Line 2007: 0 +Line 2008: 0 +Line 2009: 0 +Line 2010: 0 +Line 2011: 0 +Line 2012: 0 +Line 2013: 0 +Line 2014: 0 +Line 2015: 0 +Line 2016: 0 +Line 2017: 0 +Line 2018: 1 +Line 2019: 0 +Line 2020: 0 +Line 2021: 1 +Line 2022: 1 +Line 2023: 1 +Line 2024: 0 +Line 2025: 0 +Line 2026: 1 +Line 2027: 1 +Line 2028: 1 +Line 2029: 0 +Line 2030: 1 +Line 2031: 1 +Line 2032: 0 +Line 2033: 0 +Line 2034: 0 +Line 2035: 0 +Line 2036: 0 +Line 2037: 0 +Line 2038: 0 +Line 2039: 0 +Line 2040: 0 +Line 2041: 0 +Line 2042: 0 +Line 2043: 0 +Line 2044: 0 +Line 2045: 0 +Line 2046: 0 +Line 2047: 0 +Line 2048: 0 +Line 2049: 0 +Line 2050: 1 +Line 2051: 0 +Line 2052: 1 +Line 2053: 0 +Line 2054: 0 +Line 2055: 0 +Line 2056: 0 +Line 2057: 1 +Line 2058: 1 +Line 2059: 0 +Line 2060: 0 +Line 2061: 0 +Line 2062: 1 +Line 2063: 0 +Line 2064: 0 +Line 2065: 0 +Line 2066: 0 +Line 2067: 0 +Line 2068: 0 +Line 2069: 0 +Line 2070: 0 +Line 2071: 0 +Line 2072: 0 +Line 2073: 0 +Line 2074: 0 +Line 2075: 0 +Line 2076: 0 +Line 2077: 0 +Line 2078: 0 +Line 2079: 0 +Line 2080: 0 +Line 2081: 0 +Line 2082: 1 +Line 2083: 0 +Line 2084: 1 +Line 2085: 0 +Line 2086: 0 +Line 2087: 1 +Line 2088: 1 +Line 2089: 0 +Line 2090: 0 +Line 2091: 0 +Line 2092: 0 +Line 2093: 1 +Line 2094: 1 +Line 2095: 1 +Line 2096: 0 +Line 2097: 0 +Line 2098: 0 +Line 2099: 0 +Line 2100: 0 +Line 2101: 0 +Line 2102: 0 +Line 2103: 0 +Line 2104: 0 +Line 2105: 0 +Line 2106: 0 +Line 2107: 0 +Line 2108: 0 +Line 2109: 0 +Line 2110: 0 +Line 2111: 0 +Line 2112: 0 +Line 2113: 0 +Line 2114: 1 +Line 2115: 0 +Line 2116: 1 +Line 2117: 0 +Line 2118: 1 +Line 2119: 0 +Line 2120: 1 +Line 2121: 0 +Line 2122: 1 +Line 2123: 0 +Line 2124: 1 +Line 2125: 0 +Line 2126: 0 +Line 2127: 1 +Line 2128: 0 +Line 2129: 0 +Line 2130: 0 +Line 2131: 0 +Line 2132: 0 +Line 2133: 0 +Line 2134: 0 +Line 2135: 0 +Line 2136: 0 +Line 2137: 0 +Line 2138: 0 +Line 2139: 0 +Line 2140: 0 +Line 2141: 0 +Line 2142: 0 +Line 2143: 0 +Line 2144: 0 +Line 2145: 0 +Line 2146: 1 +Line 2147: 0 +Line 2148: 1 +Line 2149: 0 +Line 2150: 1 +Line 2151: 1 +Line 2152: 1 +Line 2153: 1 +Line 2154: 0 +Line 2155: 0 +Line 2156: 1 +Line 2157: 0 +Line 2158: 0 +Line 2159: 0 +Line 2160: 0 +Line 2161: 0 +Line 2162: 0 +Line 2163: 0 +Line 2164: 0 +Line 2165: 0 +Line 2166: 0 +Line 2167: 0 +Line 2168: 0 +Line 2169: 0 +Line 2170: 0 +Line 2171: 0 +Line 2172: 0 +Line 2173: 0 +Line 2174: 0 +Line 2175: 0 +Line 2176: 0 +Line 2177: 0 +Line 2178: 1 +Line 2179: 0 +Line 2180: 1 +Line 2181: 1 +Line 2182: 0 +Line 2183: 0 +Line 2184: 1 +Line 2185: 1 +Line 2186: 1 +Line 2187: 0 +Line 2188: 0 +Line 2189: 0 +Line 2190: 1 +Line 2191: 1 +Line 2192: 0 +Line 2193: 0 +Line 2194: 0 +Line 2195: 0 +Line 2196: 0 +Line 2197: 0 +Line 2198: 0 +Line 2199: 0 +Line 2200: 0 +Line 2201: 0 +Line 2202: 0 +Line 2203: 0 +Line 2204: 0 +Line 2205: 0 +Line 2206: 0 +Line 2207: 0 +Line 2208: 0 +Line 2209: 0 +Line 2210: 1 +Line 2211: 0 +Line 2212: 1 +Line 2213: 1 +Line 2214: 0 +Line 2215: 1 +Line 2216: 1 +Line 2217: 1 +Line 2218: 1 +Line 2219: 1 +Line 2220: 1 +Line 2221: 0 +Line 2222: 0 +Line 2223: 1 +Line 2224: 0 +Line 2225: 0 +Line 2226: 0 +Line 2227: 0 +Line 2228: 0 +Line 2229: 0 +Line 2230: 0 +Line 2231: 0 +Line 2232: 0 +Line 2233: 0 +Line 2234: 0 +Line 2235: 0 +Line 2236: 0 +Line 2237: 0 +Line 2238: 0 +Line 2239: 0 +Line 2240: 0 +Line 2241: 0 +Line 2242: 1 +Line 2243: 0 +Line 2244: 1 +Line 2245: 1 +Line 2246: 1 +Line 2247: 1 +Line 2248: 0 +Line 2249: 0 +Line 2250: 0 +Line 2251: 0 +Line 2252: 1 +Line 2253: 1 +Line 2254: 0 +Line 2255: 0 +Line 2256: 0 +Line 2257: 0 +Line 2258: 0 +Line 2259: 0 +Line 2260: 0 +Line 2261: 0 +Line 2262: 0 +Line 2263: 0 +Line 2264: 0 +Line 2265: 0 +Line 2266: 0 +Line 2267: 0 +Line 2268: 0 +Line 2269: 0 +Line 2270: 0 +Line 2271: 0 +Line 2272: 0 +Line 2273: 0 +Line 2274: 1 +Line 2275: 1 +Line 2276: 0 +Line 2277: 0 +Line 2278: 0 +Line 2279: 0 +Line 2280: 0 +Line 2281: 0 +Line 2282: 0 +Line 2283: 1 +Line 2284: 1 +Line 2285: 0 +Line 2286: 0 +Line 2287: 1 +Line 2288: 0 +Line 2289: 0 +Line 2290: 0 +Line 2291: 0 +Line 2292: 0 +Line 2293: 0 +Line 2294: 0 +Line 2295: 0 +Line 2296: 0 +Line 2297: 0 +Line 2298: 0 +Line 2299: 0 +Line 2300: 0 +Line 2301: 0 +Line 2302: 0 +Line 2303: 0 +Line 2304: 0 +Line 2305: 0 +Line 2306: 1 +Line 2307: 1 +Line 2308: 0 +Line 2309: 0 +Line 2310: 0 +Line 2311: 1 +Line 2312: 0 +Line 2313: 0 +Line 2314: 1 +Line 2315: 0 +Line 2316: 0 +Line 2317: 0 +Line 2318: 0 +Line 2319: 1 +Line 2320: 0 +Line 2321: 0 +Line 2322: 0 +Line 2323: 0 +Line 2324: 0 +Line 2325: 0 +Line 2326: 0 +Line 2327: 0 +Line 2328: 0 +Line 2329: 0 +Line 2330: 0 +Line 2331: 0 +Line 2332: 0 +Line 2333: 0 +Line 2334: 0 +Line 2335: 0 +Line 2336: 0 +Line 2337: 0 +Line 2338: 1 +Line 2339: 1 +Line 2340: 0 +Line 2341: 0 +Line 2342: 1 +Line 2343: 0 +Line 2344: 0 +Line 2345: 0 +Line 2346: 1 +Line 2347: 0 +Line 2348: 0 +Line 2349: 1 +Line 2350: 0 +Line 2351: 0 +Line 2352: 0 +Line 2353: 0 +Line 2354: 0 +Line 2355: 0 +Line 2356: 0 +Line 2357: 0 +Line 2358: 0 +Line 2359: 0 +Line 2360: 0 +Line 2361: 0 +Line 2362: 0 +Line 2363: 0 +Line 2364: 0 +Line 2365: 0 +Line 2366: 0 +Line 2367: 0 +Line 2368: 0 +Line 2369: 0 +Line 2370: 1 +Line 2371: 1 +Line 2372: 0 +Line 2373: 0 +Line 2374: 1 +Line 2375: 1 +Line 2376: 0 +Line 2377: 0 +Line 2378: 1 +Line 2379: 0 +Line 2380: 0 +Line 2381: 0 +Line 2382: 0 +Line 2383: 0 +Line 2384: 0 +Line 2385: 0 +Line 2386: 0 +Line 2387: 0 +Line 2388: 0 +Line 2389: 0 +Line 2390: 0 +Line 2391: 0 +Line 2392: 0 +Line 2393: 0 +Line 2394: 0 +Line 2395: 0 +Line 2396: 0 +Line 2397: 0 +Line 2398: 0 +Line 2399: 0 +Line 2400: 0 +Line 2401: 0 +Line 2402: 1 +Line 2403: 1 +Line 2404: 0 +Line 2405: 1 +Line 2406: 0 +Line 2407: 0 +Line 2408: 0 +Line 2409: 0 +Line 2410: 0 +Line 2411: 1 +Line 2412: 0 +Line 2413: 1 +Line 2414: 1 +Line 2415: 0 +Line 2416: 0 +Line 2417: 0 +Line 2418: 0 +Line 2419: 0 +Line 2420: 0 +Line 2421: 0 +Line 2422: 0 +Line 2423: 0 +Line 2424: 0 +Line 2425: 0 +Line 2426: 0 +Line 2427: 0 +Line 2428: 0 +Line 2429: 0 +Line 2430: 0 +Line 2431: 0 +Line 2432: 0 +Line 2433: 0 +Line 2434: 1 +Line 2435: 1 +Line 2436: 0 +Line 2437: 1 +Line 2438: 0 +Line 2439: 1 +Line 2440: 0 +Line 2441: 0 +Line 2442: 0 +Line 2443: 0 +Line 2444: 0 +Line 2445: 1 +Line 2446: 1 +Line 2447: 0 +Line 2448: 0 +Line 2449: 0 +Line 2450: 0 +Line 2451: 0 +Line 2452: 0 +Line 2453: 0 +Line 2454: 0 +Line 2455: 0 +Line 2456: 0 +Line 2457: 0 +Line 2458: 0 +Line 2459: 0 +Line 2460: 0 +Line 2461: 0 +Line 2462: 0 +Line 2463: 0 +Line 2464: 0 +Line 2465: 0 +Line 2466: 1 +Line 2467: 1 +Line 2468: 0 +Line 2469: 1 +Line 2470: 0 +Line 2471: 1 +Line 2472: 1 +Line 2473: 1 +Line 2474: 1 +Line 2475: 0 +Line 2476: 1 +Line 2477: 1 +Line 2478: 1 +Line 2479: 0 +Line 2480: 0 +Line 2481: 0 +Line 2482: 0 +Line 2483: 0 +Line 2484: 0 +Line 2485: 0 +Line 2486: 0 +Line 2487: 0 +Line 2488: 0 +Line 2489: 0 +Line 2490: 0 +Line 2491: 0 +Line 2492: 0 +Line 2493: 0 +Line 2494: 0 +Line 2495: 0 +Line 2496: 0 +Line 2497: 0 +Line 2498: 1 +Line 2499: 1 +Line 2500: 0 +Line 2501: 1 +Line 2502: 1 +Line 2503: 0 +Line 2504: 1 +Line 2505: 1 +Line 2506: 0 +Line 2507: 1 +Line 2508: 0 +Line 2509: 0 +Line 2510: 0 +Line 2511: 0 +Line 2512: 0 +Line 2513: 0 +Line 2514: 0 +Line 2515: 0 +Line 2516: 0 +Line 2517: 0 +Line 2518: 0 +Line 2519: 0 +Line 2520: 0 +Line 2521: 0 +Line 2522: 0 +Line 2523: 0 +Line 2524: 0 +Line 2525: 0 +Line 2526: 0 +Line 2527: 0 +Line 2528: 0 +Line 2529: 0 +Line 2530: 1 +Line 2531: 1 +Line 2532: 0 +Line 2533: 1 +Line 2534: 1 +Line 2535: 1 +Line 2536: 1 +Line 2537: 0 +Line 2538: 1 +Line 2539: 0 +Line 2540: 1 +Line 2541: 0 +Line 2542: 1 +Line 2543: 1 +Line 2544: 0 +Line 2545: 0 +Line 2546: 0 +Line 2547: 0 +Line 2548: 0 +Line 2549: 0 +Line 2550: 0 +Line 2551: 0 +Line 2552: 0 +Line 2553: 0 +Line 2554: 0 +Line 2555: 0 +Line 2556: 0 +Line 2557: 0 +Line 2558: 0 +Line 2559: 0 +Line 2560: 0 +Line 2561: 0 +Line 2562: 1 +Line 2563: 1 +Line 2564: 1 +Line 2565: 0 +Line 2566: 0 +Line 2567: 0 +Line 2568: 0 +Line 2569: 1 +Line 2570: 1 +Line 2571: 1 +Line 2572: 1 +Line 2573: 1 +Line 2574: 1 +Line 2575: 0 +Line 2576: 0 +Line 2577: 0 +Line 2578: 0 +Line 2579: 0 +Line 2580: 0 +Line 2581: 0 +Line 2582: 0 +Line 2583: 0 +Line 2584: 0 +Line 2585: 0 +Line 2586: 0 +Line 2587: 0 +Line 2588: 0 +Line 2589: 0 +Line 2590: 0 +Line 2591: 0 +Line 2592: 0 +Line 2593: 0 +Line 2594: 1 +Line 2595: 1 +Line 2596: 1 +Line 2597: 0 +Line 2598: 0 +Line 2599: 1 +Line 2600: 0 +Line 2601: 1 +Line 2602: 0 +Line 2603: 0 +Line 2604: 1 +Line 2605: 0 +Line 2606: 1 +Line 2607: 0 +Line 2608: 0 +Line 2609: 0 +Line 2610: 0 +Line 2611: 0 +Line 2612: 0 +Line 2613: 0 +Line 2614: 0 +Line 2615: 0 +Line 2616: 0 +Line 2617: 0 +Line 2618: 0 +Line 2619: 0 +Line 2620: 0 +Line 2621: 0 +Line 2622: 0 +Line 2623: 0 +Line 2624: 0 +Line 2625: 0 +Line 2626: 1 +Line 2627: 1 +Line 2628: 1 +Line 2629: 0 +Line 2630: 1 +Line 2631: 0 +Line 2632: 0 +Line 2633: 0 +Line 2634: 0 +Line 2635: 0 +Line 2636: 1 +Line 2637: 1 +Line 2638: 1 +Line 2639: 1 +Line 2640: 0 +Line 2641: 0 +Line 2642: 0 +Line 2643: 0 +Line 2644: 0 +Line 2645: 0 +Line 2646: 0 +Line 2647: 0 +Line 2648: 0 +Line 2649: 0 +Line 2650: 0 +Line 2651: 0 +Line 2652: 0 +Line 2653: 0 +Line 2654: 0 +Line 2655: 0 +Line 2656: 0 +Line 2657: 0 +Line 2658: 1 +Line 2659: 1 +Line 2660: 1 +Line 2661: 0 +Line 2662: 1 +Line 2663: 0 +Line 2664: 1 +Line 2665: 1 +Line 2666: 0 +Line 2667: 0 +Line 2668: 1 +Line 2669: 1 +Line 2670: 0 +Line 2671: 0 +Line 2672: 0 +Line 2673: 0 +Line 2674: 0 +Line 2675: 0 +Line 2676: 0 +Line 2677: 0 +Line 2678: 0 +Line 2679: 0 +Line 2680: 0 +Line 2681: 0 +Line 2682: 0 +Line 2683: 0 +Line 2684: 0 +Line 2685: 0 +Line 2686: 0 +Line 2687: 0 +Line 2688: 0 +Line 2689: 0 +Line 2690: 1 +Line 2691: 1 +Line 2692: 1 +Line 2693: 0 +Line 2694: 1 +Line 2695: 1 +Line 2696: 1 +Line 2697: 0 +Line 2698: 0 +Line 2699: 0 +Line 2700: 0 +Line 2701: 0 +Line 2702: 0 +Line 2703: 1 +Line 2704: 0 +Line 2705: 0 +Line 2706: 0 +Line 2707: 0 +Line 2708: 0 +Line 2709: 0 +Line 2710: 0 +Line 2711: 0 +Line 2712: 0 +Line 2713: 0 +Line 2714: 0 +Line 2715: 0 +Line 2716: 0 +Line 2717: 0 +Line 2718: 0 +Line 2719: 0 +Line 2720: 0 +Line 2721: 0 +Line 2722: 1 +Line 2723: 1 +Line 2724: 1 +Line 2725: 1 +Line 2726: 0 +Line 2727: 0 +Line 2728: 0 +Line 2729: 0 +Line 2730: 1 +Line 2731: 0 +Line 2732: 1 +Line 2733: 1 +Line 2734: 1 +Line 2735: 1 +Line 2736: 0 +Line 2737: 0 +Line 2738: 0 +Line 2739: 0 +Line 2740: 0 +Line 2741: 0 +Line 2742: 0 +Line 2743: 0 +Line 2744: 0 +Line 2745: 0 +Line 2746: 0 +Line 2747: 0 +Line 2748: 0 +Line 2749: 0 +Line 2750: 0 +Line 2751: 0 +Line 2752: 0 +Line 2753: 0 +Line 2754: 1 +Line 2755: 1 +Line 2756: 1 +Line 2757: 1 +Line 2758: 0 +Line 2759: 0 +Line 2760: 1 +Line 2761: 1 +Line 2762: 0 +Line 2763: 1 +Line 2764: 0 +Line 2765: 1 +Line 2766: 1 +Line 2767: 0 +Line 2768: 0 +Line 2769: 0 +Line 2770: 0 +Line 2771: 0 +Line 2772: 0 +Line 2773: 0 +Line 2774: 0 +Line 2775: 0 +Line 2776: 0 +Line 2777: 0 +Line 2778: 0 +Line 2779: 0 +Line 2780: 0 +Line 2781: 0 +Line 2782: 0 +Line 2783: 0 +Line 2784: 0 +Line 2785: 0 +Line 2786: 1 +Line 2787: 1 +Line 2788: 1 +Line 2789: 1 +Line 2790: 0 +Line 2791: 1 +Line 2792: 0 +Line 2793: 1 +Line 2794: 1 +Line 2795: 1 +Line 2796: 0 +Line 2797: 1 +Line 2798: 0 +Line 2799: 1 +Line 2800: 0 +Line 2801: 0 +Line 2802: 0 +Line 2803: 0 +Line 2804: 0 +Line 2805: 0 +Line 2806: 0 +Line 2807: 0 +Line 2808: 0 +Line 2809: 0 +Line 2810: 0 +Line 2811: 0 +Line 2812: 0 +Line 2813: 0 +Line 2814: 0 +Line 2815: 0 +Line 2816: 0 +Line 2817: 0 +Line 2818: 1 +Line 2819: 1 +Line 2820: 1 +Line 2821: 1 +Line 2822: 1 +Line 2823: 0 +Line 2824: 0 +Line 2825: 0 +Line 2826: 0 +Line 2827: 0 +Line 2828: 1 +Line 2829: 1 +Line 2830: 0 +Line 2831: 0 +Line 2832: 0 +Line 2833: 0 +Line 2834: 0 +Line 2835: 0 +Line 2836: 0 +Line 2837: 0 +Line 2838: 0 +Line 2839: 0 +Line 2840: 0 +Line 2841: 0 +Line 2842: 0 +Line 2843: 0 +Line 2844: 0 +Line 2845: 0 +Line 2846: 0 +Line 2847: 0 +Line 2848: 0 +Line 2849: 0 +Line 2850: 1 +Line 2851: 1 +Line 2852: 1 +Line 2853: 1 +Line 2854: 1 +Line 2855: 0 +Line 2856: 1 +Line 2857: 0 +Line 2858: 0 +Line 2859: 1 +Line 2860: 1 +Line 2861: 1 +Line 2862: 0 +Line 2863: 0 +Line 2864: 0 +Line 2865: 0 +Line 2866: 0 +Line 2867: 0 +Line 2868: 0 +Line 2869: 0 +Line 2870: 0 +Line 2871: 0 +Line 2872: 0 +Line 2873: 0 +Line 2874: 0 +Line 2875: 0 +Line 2876: 0 +Line 2877: 0 +Line 2878: 0 +Line 2879: 0 +Line 2880: 0 +Line 2881: 0 +Line 2882: 1 +Line 2883: 1 +Line 2884: 1 +Line 2885: 1 +Line 2886: 1 +Line 2887: 1 +Line 2888: 0 +Line 2889: 0 +Line 2890: 1 +Line 2891: 0 +Line 2892: 0 +Line 2893: 1 +Line 2894: 0 +Line 2895: 1 +Line 2896: 0 +Line 2897: 0 +Line 2898: 0 +Line 2899: 0 +Line 2900: 0 +Line 2901: 0 +Line 2902: 0 +Line 2903: 0 +Line 2904: 0 +Line 2905: 0 +Line 2906: 0 +Line 2907: 0 +Line 2908: 0 +Line 2909: 0 +Line 2910: 0 +Line 2911: 0 +Line 2912: 0 +Line 2913: 0 +Line 2914: 1 +Line 2915: 1 +Line 2916: 1 +Line 2917: 1 +Line 2918: 1 +Line 2919: 1 +Line 2920: 1 +Line 2921: 0 +Line 2922: 1 +Line 2923: 0 +Line 2924: 0 +Line 2925: 1 +Line 2926: 1 +Line 2927: 1 +Line 2928: 0 +Line 2929: 0 +Line 2930: 0 +Line 2931: 0 +Line 2932: 0 +Line 2933: 0 +Line 2934: 0 +Line 2935: 0 +Line 2936: 0 +Line 2937: 0 +Line 2938: 0 +Line 2939: 0 +Line 2940: 0 +Line 2941: 0 +Line 2942: 0 +Line 2943: 0 +Line 2944: 0 +Line 2945: 1 +Line 2946: 0 +Line 2947: 0 +Line 2948: 0 +Line 2949: 0 +Line 2950: 0 +Line 2951: 0 +Line 2952: 0 +Line 2953: 0 +Line 2954: 1 +Line 2955: 0 +Line 2956: 0 +Line 2957: 0 +Line 2958: 1 +Line 2959: 0 +Line 2960: 0 +Line 2961: 0 +Line 2962: 0 +Line 2963: 0 +Line 2964: 0 +Line 2965: 0 +Line 2966: 0 +Line 2967: 0 +Line 2968: 0 +Line 2969: 0 +Line 2970: 0 +Line 2971: 0 +Line 2972: 0 +Line 2973: 0 +Line 2974: 0 +Line 2975: 0 +Line 2976: 0 +Line 2977: 1 +Line 2978: 0 +Line 2979: 0 +Line 2980: 0 +Line 2981: 0 +Line 2982: 0 +Line 2983: 0 +Line 2984: 1 +Line 2985: 0 +Line 2986: 0 +Line 2987: 1 +Line 2988: 0 +Line 2989: 1 +Line 2990: 1 +Line 2991: 1 +Line 2992: 0 +Line 2993: 0 +Line 2994: 0 +Line 2995: 0 +Line 2996: 0 +Line 2997: 0 +Line 2998: 0 +Line 2999: 0 +Line 3000: 0 +Line 3001: 0 +Line 3002: 0 +Line 3003: 0 +Line 3004: 0 +Line 3005: 0 +Line 3006: 0 +Line 3007: 0 +Line 3008: 0 +Line 3009: 1 +Line 3010: 0 +Line 3011: 0 +Line 3012: 0 +Line 3013: 0 +Line 3014: 0 +Line 3015: 1 +Line 3016: 0 +Line 3017: 0 +Line 3018: 0 +Line 3019: 0 +Line 3020: 0 +Line 3021: 1 +Line 3022: 0 +Line 3023: 0 +Line 3024: 0 +Line 3025: 0 +Line 3026: 0 +Line 3027: 0 +Line 3028: 0 +Line 3029: 0 +Line 3030: 0 +Line 3031: 0 +Line 3032: 0 +Line 3033: 0 +Line 3034: 0 +Line 3035: 0 +Line 3036: 0 +Line 3037: 0 +Line 3038: 0 +Line 3039: 0 +Line 3040: 0 +Line 3041: 1 +Line 3042: 0 +Line 3043: 0 +Line 3044: 0 +Line 3045: 0 +Line 3046: 0 +Line 3047: 1 +Line 3048: 0 +Line 3049: 1 +Line 3050: 1 +Line 3051: 0 +Line 3052: 1 +Line 3053: 1 +Line 3054: 0 +Line 3055: 0 +Line 3056: 0 +Line 3057: 0 +Line 3058: 0 +Line 3059: 0 +Line 3060: 0 +Line 3061: 0 +Line 3062: 0 +Line 3063: 0 +Line 3064: 0 +Line 3065: 0 +Line 3066: 0 +Line 3067: 0 +Line 3068: 0 +Line 3069: 0 +Line 3070: 0 +Line 3071: 0 +Line 3072: 0 +Line 3073: 1 +Line 3074: 0 +Line 3075: 0 +Line 3076: 0 +Line 3077: 0 +Line 3078: 0 +Line 3079: 1 +Line 3080: 0 +Line 3081: 1 +Line 3082: 1 +Line 3083: 0 +Line 3084: 1 +Line 3085: 1 +Line 3086: 0 +Line 3087: 0 +Line 3088: 0 +Line 3089: 0 +Line 3090: 0 +Line 3091: 0 +Line 3092: 0 +Line 3093: 0 +Line 3094: 0 +Line 3095: 0 +Line 3096: 0 +Line 3097: 0 +Line 3098: 0 +Line 3099: 0 +Line 3100: 0 +Line 3101: 0 +Line 3102: 0 +Line 3103: 0 +Line 3104: 0 +Line 3105: 1 +Line 3106: 0 +Line 3107: 0 +Line 3108: 0 +Line 3109: 0 +Line 3110: 0 +Line 3111: 1 +Line 3112: 0 +Line 3113: 0 +Line 3114: 0 +Line 3115: 0 +Line 3116: 0 +Line 3117: 1 +Line 3118: 0 +Line 3119: 0 +Line 3120: 0 +Line 3121: 0 +Line 3122: 0 +Line 3123: 0 +Line 3124: 0 +Line 3125: 0 +Line 3126: 0 +Line 3127: 0 +Line 3128: 0 +Line 3129: 0 +Line 3130: 0 +Line 3131: 0 +Line 3132: 0 +Line 3133: 0 +Line 3134: 0 +Line 3135: 0 +Line 3136: 0 +Line 3137: 1 +Line 3138: 0 +Line 3139: 0 +Line 3140: 0 +Line 3141: 0 +Line 3142: 0 +Line 3143: 0 +Line 3144: 1 +Line 3145: 0 +Line 3146: 0 +Line 3147: 1 +Line 3148: 0 +Line 3149: 1 +Line 3150: 1 +Line 3151: 1 +Line 3152: 0 +Line 3153: 0 +Line 3154: 0 +Line 3155: 0 +Line 3156: 0 +Line 3157: 0 +Line 3158: 0 +Line 3159: 0 +Line 3160: 0 +Line 3161: 0 +Line 3162: 0 +Line 3163: 0 +Line 3164: 0 +Line 3165: 0 +Line 3166: 0 +Line 3167: 0 +Line 3168: 0 +Line 3169: 1 +Line 3170: 0 +Line 3171: 0 +Line 3172: 0 +Line 3173: 0 +Line 3174: 0 +Line 3175: 0 +Line 3176: 0 +Line 3177: 0 +Line 3178: 1 +Line 3179: 0 +Line 3180: 0 +Line 3181: 0 +Line 3182: 1 +Line 3183: 0 +Line 3184: 0 +Line 3185: 0 +Line 3186: 0 +Line 3187: 0 +Line 3188: 0 +Line 3189: 0 +Line 3190: 0 +Line 3191: 0 +Line 3192: 0 +Line 3193: 0 +Line 3194: 0 +Line 3195: 0 +Line 3196: 0 +Line 3197: 0 +Line 3198: 0 +Line 3199: 0 +Line 3200: 0 +Line 3201: 0 +Line 3202: 1 +Line 3203: 1 +Line 3204: 1 +Line 3205: 1 +Line 3206: 1 +Line 3207: 1 +Line 3208: 1 +Line 3209: 0 +Line 3210: 1 +Line 3211: 0 +Line 3212: 0 +Line 3213: 1 +Line 3214: 1 +Line 3215: 1 +Line 3216: 0 +Line 3217: 0 +Line 3218: 0 +Line 3219: 0 +Line 3220: 0 +Line 3221: 0 +Line 3222: 0 +Line 3223: 0 +Line 3224: 0 +Line 3225: 0 +Line 3226: 0 +Line 3227: 0 +Line 3228: 0 +Line 3229: 0 +Line 3230: 0 +Line 3231: 0 +Line 3232: 0 +Line 3233: 0 +Line 3234: 1 +Line 3235: 1 +Line 3236: 1 +Line 3237: 1 +Line 3238: 1 +Line 3239: 1 +Line 3240: 0 +Line 3241: 0 +Line 3242: 1 +Line 3243: 0 +Line 3244: 0 +Line 3245: 1 +Line 3246: 0 +Line 3247: 1 +Line 3248: 0 +Line 3249: 0 +Line 3250: 0 +Line 3251: 0 +Line 3252: 0 +Line 3253: 0 +Line 3254: 0 +Line 3255: 0 +Line 3256: 0 +Line 3257: 0 +Line 3258: 0 +Line 3259: 0 +Line 3260: 0 +Line 3261: 0 +Line 3262: 0 +Line 3263: 0 +Line 3264: 0 +Line 3265: 0 +Line 3266: 1 +Line 3267: 1 +Line 3268: 1 +Line 3269: 1 +Line 3270: 1 +Line 3271: 0 +Line 3272: 1 +Line 3273: 0 +Line 3274: 0 +Line 3275: 1 +Line 3276: 1 +Line 3277: 1 +Line 3278: 0 +Line 3279: 0 +Line 3280: 0 +Line 3281: 0 +Line 3282: 0 +Line 3283: 0 +Line 3284: 0 +Line 3285: 0 +Line 3286: 0 +Line 3287: 0 +Line 3288: 0 +Line 3289: 0 +Line 3290: 0 +Line 3291: 0 +Line 3292: 0 +Line 3293: 0 +Line 3294: 0 +Line 3295: 0 +Line 3296: 0 +Line 3297: 0 +Line 3298: 1 +Line 3299: 1 +Line 3300: 1 +Line 3301: 1 +Line 3302: 1 +Line 3303: 0 +Line 3304: 0 +Line 3305: 0 +Line 3306: 0 +Line 3307: 0 +Line 3308: 1 +Line 3309: 1 +Line 3310: 0 +Line 3311: 0 +Line 3312: 0 +Line 3313: 0 +Line 3314: 0 +Line 3315: 0 +Line 3316: 0 +Line 3317: 0 +Line 3318: 0 +Line 3319: 0 +Line 3320: 0 +Line 3321: 0 +Line 3322: 0 +Line 3323: 0 +Line 3324: 0 +Line 3325: 0 +Line 3326: 0 +Line 3327: 0 +Line 3328: 0 +Line 3329: 0 +Line 3330: 1 +Line 3331: 1 +Line 3332: 1 +Line 3333: 1 +Line 3334: 0 +Line 3335: 1 +Line 3336: 0 +Line 3337: 1 +Line 3338: 1 +Line 3339: 1 +Line 3340: 0 +Line 3341: 1 +Line 3342: 0 +Line 3343: 1 +Line 3344: 0 +Line 3345: 0 +Line 3346: 0 +Line 3347: 0 +Line 3348: 0 +Line 3349: 0 +Line 3350: 0 +Line 3351: 0 +Line 3352: 0 +Line 3353: 0 +Line 3354: 0 +Line 3355: 0 +Line 3356: 0 +Line 3357: 0 +Line 3358: 0 +Line 3359: 0 +Line 3360: 0 +Line 3361: 0 +Line 3362: 1 +Line 3363: 1 +Line 3364: 1 +Line 3365: 1 +Line 3366: 0 +Line 3367: 0 +Line 3368: 1 +Line 3369: 1 +Line 3370: 0 +Line 3371: 1 +Line 3372: 0 +Line 3373: 1 +Line 3374: 1 +Line 3375: 0 +Line 3376: 0 +Line 3377: 0 +Line 3378: 0 +Line 3379: 0 +Line 3380: 0 +Line 3381: 0 +Line 3382: 0 +Line 3383: 0 +Line 3384: 0 +Line 3385: 0 +Line 3386: 0 +Line 3387: 0 +Line 3388: 0 +Line 3389: 0 +Line 3390: 0 +Line 3391: 0 +Line 3392: 0 +Line 3393: 0 +Line 3394: 1 +Line 3395: 1 +Line 3396: 1 +Line 3397: 1 +Line 3398: 0 +Line 3399: 0 +Line 3400: 0 +Line 3401: 0 +Line 3402: 1 +Line 3403: 0 +Line 3404: 1 +Line 3405: 1 +Line 3406: 1 +Line 3407: 1 +Line 3408: 0 +Line 3409: 0 +Line 3410: 0 +Line 3411: 0 +Line 3412: 0 +Line 3413: 0 +Line 3414: 0 +Line 3415: 0 +Line 3416: 0 +Line 3417: 0 +Line 3418: 0 +Line 3419: 0 +Line 3420: 0 +Line 3421: 0 +Line 3422: 0 +Line 3423: 0 +Line 3424: 0 +Line 3425: 0 +Line 3426: 1 +Line 3427: 1 +Line 3428: 1 +Line 3429: 0 +Line 3430: 1 +Line 3431: 1 +Line 3432: 1 +Line 3433: 0 +Line 3434: 0 +Line 3435: 0 +Line 3436: 0 +Line 3437: 0 +Line 3438: 0 +Line 3439: 1 +Line 3440: 0 +Line 3441: 0 +Line 3442: 0 +Line 3443: 0 +Line 3444: 0 +Line 3445: 0 +Line 3446: 0 +Line 3447: 0 +Line 3448: 0 +Line 3449: 0 +Line 3450: 0 +Line 3451: 0 +Line 3452: 0 +Line 3453: 0 +Line 3454: 0 +Line 3455: 0 +Line 3456: 0 +Line 3457: 0 +Line 3458: 1 +Line 3459: 1 +Line 3460: 1 +Line 3461: 0 +Line 3462: 1 +Line 3463: 0 +Line 3464: 1 +Line 3465: 1 +Line 3466: 0 +Line 3467: 0 +Line 3468: 1 +Line 3469: 1 +Line 3470: 0 +Line 3471: 0 +Line 3472: 0 +Line 3473: 0 +Line 3474: 0 +Line 3475: 0 +Line 3476: 0 +Line 3477: 0 +Line 3478: 0 +Line 3479: 0 +Line 3480: 0 +Line 3481: 0 +Line 3482: 0 +Line 3483: 0 +Line 3484: 0 +Line 3485: 0 +Line 3486: 0 +Line 3487: 0 +Line 3488: 0 +Line 3489: 0 +Line 3490: 1 +Line 3491: 1 +Line 3492: 1 +Line 3493: 0 +Line 3494: 1 +Line 3495: 0 +Line 3496: 0 +Line 3497: 0 +Line 3498: 0 +Line 3499: 0 +Line 3500: 1 +Line 3501: 1 +Line 3502: 1 +Line 3503: 1 +Line 3504: 0 +Line 3505: 0 +Line 3506: 0 +Line 3507: 0 +Line 3508: 0 +Line 3509: 0 +Line 3510: 0 +Line 3511: 0 +Line 3512: 0 +Line 3513: 0 +Line 3514: 0 +Line 3515: 0 +Line 3516: 0 +Line 3517: 0 +Line 3518: 0 +Line 3519: 0 +Line 3520: 0 +Line 3521: 0 +Line 3522: 1 +Line 3523: 1 +Line 3524: 1 +Line 3525: 0 +Line 3526: 0 +Line 3527: 1 +Line 3528: 0 +Line 3529: 1 +Line 3530: 0 +Line 3531: 0 +Line 3532: 1 +Line 3533: 0 +Line 3534: 1 +Line 3535: 0 +Line 3536: 0 +Line 3537: 0 +Line 3538: 0 +Line 3539: 0 +Line 3540: 0 +Line 3541: 0 +Line 3542: 0 +Line 3543: 0 +Line 3544: 0 +Line 3545: 0 +Line 3546: 0 +Line 3547: 0 +Line 3548: 0 +Line 3549: 0 +Line 3550: 0 +Line 3551: 0 +Line 3552: 0 +Line 3553: 0 +Line 3554: 1 +Line 3555: 1 +Line 3556: 1 +Line 3557: 0 +Line 3558: 0 +Line 3559: 0 +Line 3560: 0 +Line 3561: 1 +Line 3562: 1 +Line 3563: 1 +Line 3564: 1 +Line 3565: 1 +Line 3566: 1 +Line 3567: 0 +Line 3568: 0 +Line 3569: 0 +Line 3570: 0 +Line 3571: 0 +Line 3572: 0 +Line 3573: 0 +Line 3574: 0 +Line 3575: 0 +Line 3576: 0 +Line 3577: 0 +Line 3578: 0 +Line 3579: 0 +Line 3580: 0 +Line 3581: 0 +Line 3582: 0 +Line 3583: 0 +Line 3584: 0 +Line 3585: 0 +Line 3586: 1 +Line 3587: 1 +Line 3588: 0 +Line 3589: 1 +Line 3590: 1 +Line 3591: 1 +Line 3592: 1 +Line 3593: 0 +Line 3594: 1 +Line 3595: 0 +Line 3596: 1 +Line 3597: 0 +Line 3598: 1 +Line 3599: 1 +Line 3600: 0 +Line 3601: 0 +Line 3602: 0 +Line 3603: 0 +Line 3604: 0 +Line 3605: 0 +Line 3606: 0 +Line 3607: 0 +Line 3608: 0 +Line 3609: 0 +Line 3610: 0 +Line 3611: 0 +Line 3612: 0 +Line 3613: 0 +Line 3614: 0 +Line 3615: 0 +Line 3616: 0 +Line 3617: 0 +Line 3618: 1 +Line 3619: 1 +Line 3620: 0 +Line 3621: 1 +Line 3622: 1 +Line 3623: 0 +Line 3624: 1 +Line 3625: 1 +Line 3626: 0 +Line 3627: 1 +Line 3628: 0 +Line 3629: 0 +Line 3630: 0 +Line 3631: 0 +Line 3632: 0 +Line 3633: 0 +Line 3634: 0 +Line 3635: 0 +Line 3636: 0 +Line 3637: 0 +Line 3638: 0 +Line 3639: 0 +Line 3640: 0 +Line 3641: 0 +Line 3642: 0 +Line 3643: 0 +Line 3644: 0 +Line 3645: 0 +Line 3646: 0 +Line 3647: 0 +Line 3648: 0 +Line 3649: 0 +Line 3650: 1 +Line 3651: 1 +Line 3652: 0 +Line 3653: 1 +Line 3654: 0 +Line 3655: 1 +Line 3656: 1 +Line 3657: 1 +Line 3658: 1 +Line 3659: 0 +Line 3660: 1 +Line 3661: 1 +Line 3662: 1 +Line 3663: 0 +Line 3664: 0 +Line 3665: 0 +Line 3666: 0 +Line 3667: 0 +Line 3668: 0 +Line 3669: 0 +Line 3670: 0 +Line 3671: 0 +Line 3672: 0 +Line 3673: 0 +Line 3674: 0 +Line 3675: 0 +Line 3676: 0 +Line 3677: 0 +Line 3678: 0 +Line 3679: 0 +Line 3680: 0 +Line 3681: 0 +Line 3682: 1 +Line 3683: 1 +Line 3684: 0 +Line 3685: 1 +Line 3686: 0 +Line 3687: 1 +Line 3688: 0 +Line 3689: 0 +Line 3690: 0 +Line 3691: 0 +Line 3692: 0 +Line 3693: 1 +Line 3694: 1 +Line 3695: 0 +Line 3696: 0 +Line 3697: 0 +Line 3698: 0 +Line 3699: 0 +Line 3700: 0 +Line 3701: 0 +Line 3702: 0 +Line 3703: 0 +Line 3704: 0 +Line 3705: 0 +Line 3706: 0 +Line 3707: 0 +Line 3708: 0 +Line 3709: 0 +Line 3710: 0 +Line 3711: 0 +Line 3712: 0 +Line 3713: 0 +Line 3714: 1 +Line 3715: 1 +Line 3716: 0 +Line 3717: 1 +Line 3718: 0 +Line 3719: 0 +Line 3720: 0 +Line 3721: 0 +Line 3722: 0 +Line 3723: 1 +Line 3724: 0 +Line 3725: 1 +Line 3726: 1 +Line 3727: 0 +Line 3728: 0 +Line 3729: 0 +Line 3730: 0 +Line 3731: 0 +Line 3732: 0 +Line 3733: 0 +Line 3734: 0 +Line 3735: 0 +Line 3736: 0 +Line 3737: 0 +Line 3738: 0 +Line 3739: 0 +Line 3740: 0 +Line 3741: 0 +Line 3742: 0 +Line 3743: 0 +Line 3744: 0 +Line 3745: 0 +Line 3746: 1 +Line 3747: 1 +Line 3748: 0 +Line 3749: 0 +Line 3750: 1 +Line 3751: 1 +Line 3752: 0 +Line 3753: 0 +Line 3754: 1 +Line 3755: 0 +Line 3756: 0 +Line 3757: 0 +Line 3758: 0 +Line 3759: 0 +Line 3760: 0 +Line 3761: 0 +Line 3762: 0 +Line 3763: 0 +Line 3764: 0 +Line 3765: 0 +Line 3766: 0 +Line 3767: 0 +Line 3768: 0 +Line 3769: 0 +Line 3770: 0 +Line 3771: 0 +Line 3772: 0 +Line 3773: 0 +Line 3774: 0 +Line 3775: 0 +Line 3776: 0 +Line 3777: 0 +Line 3778: 1 +Line 3779: 1 +Line 3780: 0 +Line 3781: 0 +Line 3782: 1 +Line 3783: 0 +Line 3784: 0 +Line 3785: 0 +Line 3786: 1 +Line 3787: 0 +Line 3788: 0 +Line 3789: 1 +Line 3790: 0 +Line 3791: 0 +Line 3792: 0 +Line 3793: 0 +Line 3794: 0 +Line 3795: 0 +Line 3796: 0 +Line 3797: 0 +Line 3798: 0 +Line 3799: 0 +Line 3800: 0 +Line 3801: 0 +Line 3802: 0 +Line 3803: 0 +Line 3804: 0 +Line 3805: 0 +Line 3806: 0 +Line 3807: 0 +Line 3808: 0 +Line 3809: 0 +Line 3810: 1 +Line 3811: 1 +Line 3812: 0 +Line 3813: 0 +Line 3814: 0 +Line 3815: 1 +Line 3816: 0 +Line 3817: 0 +Line 3818: 1 +Line 3819: 0 +Line 3820: 0 +Line 3821: 0 +Line 3822: 0 +Line 3823: 1 +Line 3824: 0 +Line 3825: 0 +Line 3826: 0 +Line 3827: 0 +Line 3828: 0 +Line 3829: 0 +Line 3830: 0 +Line 3831: 0 +Line 3832: 0 +Line 3833: 0 +Line 3834: 0 +Line 3835: 0 +Line 3836: 0 +Line 3837: 0 +Line 3838: 0 +Line 3839: 0 +Line 3840: 0 +Line 3841: 0 +Line 3842: 1 +Line 3843: 1 +Line 3844: 0 +Line 3845: 0 +Line 3846: 0 +Line 3847: 0 +Line 3848: 0 +Line 3849: 0 +Line 3850: 0 +Line 3851: 1 +Line 3852: 1 +Line 3853: 0 +Line 3854: 0 +Line 3855: 1 +Line 3856: 0 +Line 3857: 0 +Line 3858: 0 +Line 3859: 0 +Line 3860: 0 +Line 3861: 0 +Line 3862: 0 +Line 3863: 0 +Line 3864: 0 +Line 3865: 0 +Line 3866: 0 +Line 3867: 0 +Line 3868: 0 +Line 3869: 0 +Line 3870: 0 +Line 3871: 0 +Line 3872: 0 +Line 3873: 0 +Line 3874: 1 +Line 3875: 0 +Line 3876: 1 +Line 3877: 1 +Line 3878: 1 +Line 3879: 1 +Line 3880: 0 +Line 3881: 0 +Line 3882: 0 +Line 3883: 0 +Line 3884: 1 +Line 3885: 1 +Line 3886: 0 +Line 3887: 0 +Line 3888: 0 +Line 3889: 0 +Line 3890: 0 +Line 3891: 0 +Line 3892: 0 +Line 3893: 0 +Line 3894: 0 +Line 3895: 0 +Line 3896: 0 +Line 3897: 0 +Line 3898: 0 +Line 3899: 0 +Line 3900: 0 +Line 3901: 0 +Line 3902: 0 +Line 3903: 0 +Line 3904: 0 +Line 3905: 0 +Line 3906: 1 +Line 3907: 0 +Line 3908: 1 +Line 3909: 1 +Line 3910: 0 +Line 3911: 1 +Line 3912: 1 +Line 3913: 1 +Line 3914: 1 +Line 3915: 1 +Line 3916: 1 +Line 3917: 0 +Line 3918: 0 +Line 3919: 1 +Line 3920: 0 +Line 3921: 0 +Line 3922: 0 +Line 3923: 0 +Line 3924: 0 +Line 3925: 0 +Line 3926: 0 +Line 3927: 0 +Line 3928: 0 +Line 3929: 0 +Line 3930: 0 +Line 3931: 0 +Line 3932: 0 +Line 3933: 0 +Line 3934: 0 +Line 3935: 0 +Line 3936: 0 +Line 3937: 0 +Line 3938: 1 +Line 3939: 0 +Line 3940: 1 +Line 3941: 1 +Line 3942: 0 +Line 3943: 0 +Line 3944: 1 +Line 3945: 1 +Line 3946: 1 +Line 3947: 0 +Line 3948: 0 +Line 3949: 0 +Line 3950: 1 +Line 3951: 1 +Line 3952: 0 +Line 3953: 0 +Line 3954: 0 +Line 3955: 0 +Line 3956: 0 +Line 3957: 0 +Line 3958: 0 +Line 3959: 0 +Line 3960: 0 +Line 3961: 0 +Line 3962: 0 +Line 3963: 0 +Line 3964: 0 +Line 3965: 0 +Line 3966: 0 +Line 3967: 0 +Line 3968: 0 +Line 3969: 0 +Line 3970: 1 +Line 3971: 0 +Line 3972: 1 +Line 3973: 0 +Line 3974: 1 +Line 3975: 1 +Line 3976: 1 +Line 3977: 1 +Line 3978: 0 +Line 3979: 0 +Line 3980: 1 +Line 3981: 0 +Line 3982: 0 +Line 3983: 0 +Line 3984: 0 +Line 3985: 0 +Line 3986: 0 +Line 3987: 0 +Line 3988: 0 +Line 3989: 0 +Line 3990: 0 +Line 3991: 0 +Line 3992: 0 +Line 3993: 0 +Line 3994: 0 +Line 3995: 0 +Line 3996: 0 +Line 3997: 0 +Line 3998: 0 +Line 3999: 0 +Line 4000: 0 +Line 4001: 0 +Line 4002: 1 +Line 4003: 0 +Line 4004: 1 +Line 4005: 0 +Line 4006: 1 +Line 4007: 0 +Line 4008: 1 +Line 4009: 0 +Line 4010: 1 +Line 4011: 0 +Line 4012: 1 +Line 4013: 0 +Line 4014: 0 +Line 4015: 1 +Line 4016: 0 +Line 4017: 0 +Line 4018: 0 +Line 4019: 0 +Line 4020: 0 +Line 4021: 0 +Line 4022: 0 +Line 4023: 0 +Line 4024: 0 +Line 4025: 0 +Line 4026: 0 +Line 4027: 0 +Line 4028: 0 +Line 4029: 0 +Line 4030: 0 +Line 4031: 0 +Line 4032: 0 +Line 4033: 0 +Line 4034: 1 +Line 4035: 0 +Line 4036: 1 +Line 4037: 0 +Line 4038: 0 +Line 4039: 1 +Line 4040: 1 +Line 4041: 0 +Line 4042: 0 +Line 4043: 0 +Line 4044: 0 +Line 4045: 1 +Line 4046: 1 +Line 4047: 1 +Line 4048: 0 +Line 4049: 0 +Line 4050: 0 +Line 4051: 0 +Line 4052: 0 +Line 4053: 0 +Line 4054: 0 +Line 4055: 0 +Line 4056: 0 +Line 4057: 0 +Line 4058: 0 +Line 4059: 0 +Line 4060: 0 +Line 4061: 0 +Line 4062: 0 +Line 4063: 0 +Line 4064: 0 +Line 4065: 0 +Line 4066: 1 +Line 4067: 0 +Line 4068: 1 +Line 4069: 0 +Line 4070: 0 +Line 4071: 0 +Line 4072: 0 +Line 4073: 1 +Line 4074: 1 +Line 4075: 0 +Line 4076: 0 +Line 4077: 0 +Line 4078: 1 +Line 4079: 0 +Line 4080: 0 +Line 4081: 0 +Line 4082: 0 +Line 4083: 0 +Line 4084: 0 +Line 4085: 0 +Line 4086: 0 +Line 4087: 0 +Line 4088: 0 +Line 4089: 0 +Line 4090: 0 +Line 4091: 0 +Line 4092: 0 +Line 4093: 0 +Line 4094: 0 +Line 4095: 0 +Line 4096: 0 +Line 4097: 0 +Line 4098: 1 +Line 4099: 0 +Line 4100: 0 +Line 4101: 1 +Line 4102: 1 +Line 4103: 1 +Line 4104: 0 +Line 4105: 0 +Line 4106: 1 +Line 4107: 1 +Line 4108: 1 +Line 4109: 0 +Line 4110: 1 +Line 4111: 1 +Line 4112: 0 +Line 4113: 0 +Line 4114: 0 +Line 4115: 0 +Line 4116: 0 +Line 4117: 0 +Line 4118: 0 +Line 4119: 0 +Line 4120: 0 +Line 4121: 0 +Line 4122: 0 +Line 4123: 0 +Line 4124: 0 +Line 4125: 0 +Line 4126: 0 +Line 4127: 0 +Line 4128: 0 +Line 4129: 0 +Line 4130: 1 +Line 4131: 0 +Line 4132: 0 +Line 4133: 1 +Line 4134: 1 +Line 4135: 0 +Line 4136: 0 +Line 4137: 0 +Line 4138: 0 +Line 4139: 1 +Line 4140: 0 +Line 4141: 0 +Line 4142: 1 +Line 4143: 0 +Line 4144: 0 +Line 4145: 0 +Line 4146: 0 +Line 4147: 0 +Line 4148: 0 +Line 4149: 0 +Line 4150: 0 +Line 4151: 0 +Line 4152: 0 +Line 4153: 0 +Line 4154: 0 +Line 4155: 0 +Line 4156: 0 +Line 4157: 0 +Line 4158: 0 +Line 4159: 0 +Line 4160: 0 +Line 4161: 0 +Line 4162: 1 +Line 4163: 0 +Line 4164: 0 +Line 4165: 1 +Line 4166: 0 +Line 4167: 0 +Line 4168: 1 +Line 4169: 1 +Line 4170: 1 +Line 4171: 0 +Line 4172: 1 +Line 4173: 0 +Line 4174: 0 +Line 4175: 0 +Line 4176: 0 +Line 4177: 0 +Line 4178: 0 +Line 4179: 0 +Line 4180: 0 +Line 4181: 0 +Line 4182: 0 +Line 4183: 0 +Line 4184: 0 +Line 4185: 0 +Line 4186: 0 +Line 4187: 0 +Line 4188: 0 +Line 4189: 0 +Line 4190: 0 +Line 4191: 0 +Line 4192: 0 +Line 4193: 0 +Line 4194: 1 +Line 4195: 0 +Line 4196: 0 +Line 4197: 0 +Line 4198: 1 +Line 4199: 1 +Line 4200: 1 +Line 4201: 0 +Line 4202: 1 +Line 4203: 1 +Line 4204: 1 +Line 4205: 1 +Line 4206: 0 +Line 4207: 1 +Line 4208: 0 +Line 4209: 0 +Line 4210: 0 +Line 4211: 0 +Line 4212: 0 +Line 4213: 0 +Line 4214: 0 +Line 4215: 0 +Line 4216: 0 +Line 4217: 0 +Line 4218: 0 +Line 4219: 0 +Line 4220: 0 +Line 4221: 0 +Line 4222: 0 +Line 4223: 0 +Line 4224: 0 +Line 4225: 0 +Line 4226: 1 +Line 4227: 0 +Line 4228: 0 +Line 4229: 0 +Line 4230: 1 +Line 4231: 0 +Line 4232: 1 +Line 4233: 0 +Line 4234: 0 +Line 4235: 1 +Line 4236: 0 +Line 4237: 0 +Line 4238: 1 +Line 4239: 0 +Line 4240: 0 +Line 4241: 0 +Line 4242: 0 +Line 4243: 0 +Line 4244: 0 +Line 4245: 0 +Line 4246: 0 +Line 4247: 0 +Line 4248: 0 +Line 4249: 0 +Line 4250: 0 +Line 4251: 0 +Line 4252: 0 +Line 4253: 0 +Line 4254: 0 +Line 4255: 0 +Line 4256: 0 +Line 4257: 0 +Line 4258: 1 +Line 4259: 0 +Line 4260: 0 +Line 4261: 0 +Line 4262: 0 +Line 4263: 1 +Line 4264: 0 +Line 4265: 1 +Line 4266: 1 +Line 4267: 0 +Line 4268: 0 +Line 4269: 1 +Line 4270: 1 +Line 4271: 1 +Line 4272: 0 +Line 4273: 0 +Line 4274: 0 +Line 4275: 0 +Line 4276: 0 +Line 4277: 0 +Line 4278: 0 +Line 4279: 0 +Line 4280: 0 +Line 4281: 0 +Line 4282: 0 +Line 4283: 0 +Line 4284: 0 +Line 4285: 0 +Line 4286: 0 +Line 4287: 0 +Line 4288: 0 +Line 4289: 0 +Line 4290: 1 +Line 4291: 0 +Line 4292: 0 +Line 4293: 0 +Line 4294: 0 +Line 4295: 0 +Line 4296: 0 +Line 4297: 0 +Line 4298: 1 +Line 4299: 1 +Line 4300: 1 +Line 4301: 1 +Line 4302: 0 +Line 4303: 1 +Line 4304: 0 +Line 4305: 0 +Line 4306: 0 +Line 4307: 0 +Line 4308: 0 +Line 4309: 0 +Line 4310: 0 +Line 4311: 0 +Line 4312: 0 +Line 4313: 0 +Line 4314: 0 +Line 4315: 0 +Line 4316: 0 +Line 4317: 0 +Line 4318: 0 +Line 4319: 0 +Line 4320: 0 +Line 4321: 0 +Line 4322: 0 +Line 4323: 1 +Line 4324: 1 +Line 4325: 1 +Line 4326: 1 +Line 4327: 1 +Line 4328: 0 +Line 4329: 0 +Line 4330: 0 +Line 4331: 1 +Line 4332: 0 +Line 4333: 1 +Line 4334: 0 +Line 4335: 0 +Line 4336: 0 +Line 4337: 0 +Line 4338: 0 +Line 4339: 0 +Line 4340: 0 +Line 4341: 0 +Line 4342: 0 +Line 4343: 0 +Line 4344: 0 +Line 4345: 0 +Line 4346: 0 +Line 4347: 0 +Line 4348: 0 +Line 4349: 0 +Line 4350: 0 +Line 4351: 0 +Line 4352: 0 +Line 4353: 0 +Line 4354: 0 +Line 4355: 1 +Line 4356: 1 +Line 4357: 1 +Line 4358: 0 +Line 4359: 1 +Line 4360: 1 +Line 4361: 1 +Line 4362: 1 +Line 4363: 0 +Line 4364: 1 +Line 4365: 1 +Line 4366: 0 +Line 4367: 1 +Line 4368: 0 +Line 4369: 0 +Line 4370: 0 +Line 4371: 0 +Line 4372: 0 +Line 4373: 0 +Line 4374: 0 +Line 4375: 0 +Line 4376: 0 +Line 4377: 0 +Line 4378: 0 +Line 4379: 0 +Line 4380: 0 +Line 4381: 0 +Line 4382: 0 +Line 4383: 0 +Line 4384: 0 +Line 4385: 0 +Line 4386: 0 +Line 4387: 1 +Line 4388: 1 +Line 4389: 1 +Line 4390: 0 +Line 4391: 0 +Line 4392: 1 +Line 4393: 1 +Line 4394: 0 +Line 4395: 0 +Line 4396: 1 +Line 4397: 0 +Line 4398: 0 +Line 4399: 0 +Line 4400: 0 +Line 4401: 0 +Line 4402: 0 +Line 4403: 0 +Line 4404: 0 +Line 4405: 0 +Line 4406: 0 +Line 4407: 0 +Line 4408: 0 +Line 4409: 0 +Line 4410: 0 +Line 4411: 0 +Line 4412: 0 +Line 4413: 0 +Line 4414: 0 +Line 4415: 0 +Line 4416: 0 +Line 4417: 0 +Line 4418: 0 +Line 4419: 1 +Line 4420: 1 +Line 4421: 0 +Line 4422: 1 +Line 4423: 1 +Line 4424: 1 +Line 4425: 0 +Line 4426: 1 +Line 4427: 0 +Line 4428: 0 +Line 4429: 1 +Line 4430: 1 +Line 4431: 0 +Line 4432: 0 +Line 4433: 0 +Line 4434: 0 +Line 4435: 0 +Line 4436: 0 +Line 4437: 0 +Line 4438: 0 +Line 4439: 0 +Line 4440: 0 +Line 4441: 0 +Line 4442: 0 +Line 4443: 0 +Line 4444: 0 +Line 4445: 0 +Line 4446: 0 +Line 4447: 0 +Line 4448: 0 +Line 4449: 0 +Line 4450: 0 +Line 4451: 1 +Line 4452: 1 +Line 4453: 0 +Line 4454: 1 +Line 4455: 0 +Line 4456: 1 +Line 4457: 0 +Line 4458: 0 +Line 4459: 0 +Line 4460: 0 +Line 4461: 1 +Line 4462: 1 +Line 4463: 1 +Line 4464: 0 +Line 4465: 0 +Line 4466: 0 +Line 4467: 0 +Line 4468: 0 +Line 4469: 0 +Line 4470: 0 +Line 4471: 0 +Line 4472: 0 +Line 4473: 0 +Line 4474: 0 +Line 4475: 0 +Line 4476: 0 +Line 4477: 0 +Line 4478: 0 +Line 4479: 0 +Line 4480: 0 +Line 4481: 0 +Line 4482: 0 +Line 4483: 1 +Line 4484: 1 +Line 4485: 0 +Line 4486: 0 +Line 4487: 1 +Line 4488: 0 +Line 4489: 1 +Line 4490: 1 +Line 4491: 0 +Line 4492: 1 +Line 4493: 1 +Line 4494: 0 +Line 4495: 0 +Line 4496: 0 +Line 4497: 0 +Line 4498: 0 +Line 4499: 0 +Line 4500: 0 +Line 4501: 0 +Line 4502: 0 +Line 4503: 0 +Line 4504: 0 +Line 4505: 0 +Line 4506: 0 +Line 4507: 0 +Line 4508: 0 +Line 4509: 0 +Line 4510: 0 +Line 4511: 0 +Line 4512: 0 +Line 4513: 0 +Line 4514: 0 +Line 4515: 1 +Line 4516: 1 +Line 4517: 0 +Line 4518: 0 +Line 4519: 0 +Line 4520: 0 +Line 4521: 1 +Line 4522: 0 +Line 4523: 1 +Line 4524: 0 +Line 4525: 1 +Line 4526: 1 +Line 4527: 0 +Line 4528: 0 +Line 4529: 0 +Line 4530: 0 +Line 4531: 0 +Line 4532: 0 +Line 4533: 0 +Line 4534: 0 +Line 4535: 0 +Line 4536: 0 +Line 4537: 0 +Line 4538: 0 +Line 4539: 0 +Line 4540: 0 +Line 4541: 0 +Line 4542: 0 +Line 4543: 0 +Line 4544: 0 +Line 4545: 0 +Line 4546: 0 +Line 4547: 1 +Line 4548: 0 +Line 4549: 1 +Line 4550: 1 +Line 4551: 1 +Line 4552: 0 +Line 4553: 1 +Line 4554: 0 +Line 4555: 0 +Line 4556: 0 +Line 4557: 0 +Line 4558: 1 +Line 4559: 1 +Line 4560: 0 +Line 4561: 0 +Line 4562: 0 +Line 4563: 0 +Line 4564: 0 +Line 4565: 0 +Line 4566: 0 +Line 4567: 0 +Line 4568: 0 +Line 4569: 0 +Line 4570: 0 +Line 4571: 0 +Line 4572: 0 +Line 4573: 0 +Line 4574: 0 +Line 4575: 0 +Line 4576: 0 +Line 4577: 0 +Line 4578: 0 +Line 4579: 1 +Line 4580: 0 +Line 4581: 1 +Line 4582: 1 +Line 4583: 0 +Line 4584: 0 +Line 4585: 0 +Line 4586: 1 +Line 4587: 1 +Line 4588: 0 +Line 4589: 1 +Line 4590: 1 +Line 4591: 0 +Line 4592: 0 +Line 4593: 0 +Line 4594: 0 +Line 4595: 0 +Line 4596: 0 +Line 4597: 0 +Line 4598: 0 +Line 4599: 0 +Line 4600: 0 +Line 4601: 0 +Line 4602: 0 +Line 4603: 0 +Line 4604: 0 +Line 4605: 0 +Line 4606: 0 +Line 4607: 0 +Line 4608: 0 +Line 4609: 0 +Line 4610: 0 +Line 4611: 1 +Line 4612: 0 +Line 4613: 1 +Line 4614: 0 +Line 4615: 1 +Line 4616: 0 +Line 4617: 0 +Line 4618: 1 +Line 4619: 0 +Line 4620: 1 +Line 4621: 1 +Line 4622: 1 +Line 4623: 0 +Line 4624: 0 +Line 4625: 0 +Line 4626: 0 +Line 4627: 0 +Line 4628: 0 +Line 4629: 0 +Line 4630: 0 +Line 4631: 0 +Line 4632: 0 +Line 4633: 0 +Line 4634: 0 +Line 4635: 0 +Line 4636: 0 +Line 4637: 0 +Line 4638: 0 +Line 4639: 0 +Line 4640: 0 +Line 4641: 0 +Line 4642: 0 +Line 4643: 1 +Line 4644: 0 +Line 4645: 1 +Line 4646: 0 +Line 4647: 0 +Line 4648: 0 +Line 4649: 0 +Line 4650: 1 +Line 4651: 0 +Line 4652: 1 +Line 4653: 0 +Line 4654: 1 +Line 4655: 1 +Line 4656: 0 +Line 4657: 0 +Line 4658: 0 +Line 4659: 0 +Line 4660: 0 +Line 4661: 0 +Line 4662: 0 +Line 4663: 0 +Line 4664: 0 +Line 4665: 0 +Line 4666: 0 +Line 4667: 0 +Line 4668: 0 +Line 4669: 0 +Line 4670: 0 +Line 4671: 0 +Line 4672: 1 +Line 4673: 1 +Line 4674: 1 +Line 4675: 1 +Line 4676: 1 +Line 4677: 1 +Line 4678: 1 +Line 4679: 0 +Line 4680: 0 +Line 4681: 1 +Line 4682: 1 +Line 4683: 0 +Line 4684: 0 +Line 4685: 1 +Line 4686: 1 +Line 4687: 1 +Line 4688: 0 +Line 4689: 0 +Line 4690: 0 +Line 4691: 0 +Line 4692: 0 +Line 4693: 0 +Line 4694: 0 +Line 4695: 0 +Line 4696: 0 +Line 4697: 0 +Line 4698: 0 +Line 4699: 0 +Line 4700: 0 +Line 4701: 0 +Line 4702: 0 +Line 4703: 0 +Line 4704: 1 +Line 4705: 1 +Line 4706: 1 +Line 4707: 1 +Line 4708: 0 +Line 4709: 1 +Line 4710: 0 +Line 4711: 0 +Line 4712: 1 +Line 4713: 1 +Line 4714: 0 +Line 4715: 1 +Line 4716: 1 +Line 4717: 0 +Line 4718: 0 +Line 4719: 1 +Line 4720: 0 +Line 4721: 0 +Line 4722: 0 +Line 4723: 0 +Line 4724: 0 +Line 4725: 0 +Line 4726: 0 +Line 4727: 0 +Line 4728: 0 +Line 4729: 0 +Line 4730: 0 +Line 4731: 0 +Line 4732: 0 +Line 4733: 0 +Line 4734: 0 +Line 4735: 0 +Line 4736: 1 +Line 4737: 1 +Line 4738: 0 +Line 4739: 1 +Line 4740: 1 +Line 4741: 1 +Line 4742: 0 +Line 4743: 0 +Line 4744: 1 +Line 4745: 1 +Line 4746: 0 +Line 4747: 1 +Line 4748: 1 +Line 4749: 0 +Line 4750: 0 +Line 4751: 0 +Line 4752: 0 +Line 4753: 0 +Line 4754: 0 +Line 4755: 0 +Line 4756: 0 +Line 4757: 0 +Line 4758: 0 +Line 4759: 0 +Line 4760: 0 +Line 4761: 0 +Line 4762: 0 +Line 4763: 0 +Line 4764: 0 +Line 4765: 0 +Line 4766: 0 +Line 4767: 0 +Line 4768: 1 +Line 4769: 1 +Line 4770: 0 +Line 4771: 0 +Line 4772: 0 +Line 4773: 1 +Line 4774: 0 +Line 4775: 0 +Line 4776: 1 +Line 4777: 1 +Line 4778: 0 +Line 4779: 1 +Line 4780: 1 +Line 4781: 0 +Line 4782: 0 +Line 4783: 0 +Line 4784: 0 +Line 4785: 0 +Line 4786: 0 +Line 4787: 0 +Line 4788: 0 +Line 4789: 0 +Line 4790: 0 +Line 4791: 0 +Line 4792: 0 +Line 4793: 0 +Line 4794: 0 +Line 4795: 0 +Line 4796: 0 +Line 4797: 0 +Line 4798: 0 +Line 4799: 0 +Line 4800: 1 +Line 4801: 0 +Line 4802: 1 +Line 4803: 1 +Line 4804: 1 +Line 4805: 0 +Line 4806: 1 +Line 4807: 1 +Line 4808: 0 +Line 4809: 1 +Line 4810: 0 +Line 4811: 0 +Line 4812: 1 +Line 4813: 0 +Line 4814: 1 +Line 4815: 0 +Line 4816: 0 +Line 4817: 0 +Line 4818: 0 +Line 4819: 0 +Line 4820: 0 +Line 4821: 0 +Line 4822: 0 +Line 4823: 0 +Line 4824: 0 +Line 4825: 0 +Line 4826: 0 +Line 4827: 0 +Line 4828: 0 +Line 4829: 0 +Line 4830: 0 +Line 4831: 0 +Line 4832: 1 +Line 4833: 0 +Line 4834: 1 +Line 4835: 1 +Line 4836: 1 +Line 4837: 0 +Line 4838: 0 +Line 4839: 1 +Line 4840: 1 +Line 4841: 1 +Line 4842: 0 +Line 4843: 0 +Line 4844: 1 +Line 4845: 0 +Line 4846: 0 +Line 4847: 1 +Line 4848: 0 +Line 4849: 0 +Line 4850: 0 +Line 4851: 0 +Line 4852: 0 +Line 4853: 0 +Line 4854: 0 +Line 4855: 0 +Line 4856: 0 +Line 4857: 0 +Line 4858: 0 +Line 4859: 0 +Line 4860: 0 +Line 4861: 0 +Line 4862: 0 +Line 4863: 0 +Line 4864: 1 +Line 4865: 0 +Line 4866: 1 +Line 4867: 1 +Line 4868: 1 +Line 4869: 0 +Line 4870: 0 +Line 4871: 1 +Line 4872: 1 +Line 4873: 0 +Line 4874: 1 +Line 4875: 1 +Line 4876: 0 +Line 4877: 0 +Line 4878: 0 +Line 4879: 1 +Line 4880: 0 +Line 4881: 0 +Line 4882: 0 +Line 4883: 0 +Line 4884: 0 +Line 4885: 0 +Line 4886: 0 +Line 4887: 0 +Line 4888: 0 +Line 4889: 0 +Line 4890: 0 +Line 4891: 0 +Line 4892: 0 +Line 4893: 0 +Line 4894: 0 +Line 4895: 0 +Line 4896: 1 +Line 4897: 0 +Line 4898: 1 +Line 4899: 1 +Line 4900: 1 +Line 4901: 0 +Line 4902: 0 +Line 4903: 1 +Line 4904: 1 +Line 4905: 0 +Line 4906: 1 +Line 4907: 1 +Line 4908: 0 +Line 4909: 0 +Line 4910: 0 +Line 4911: 1 +Line 4912: 0 +Line 4913: 0 +Line 4914: 0 +Line 4915: 0 +Line 4916: 0 +Line 4917: 0 +Line 4918: 0 +Line 4919: 0 +Line 4920: 0 +Line 4921: 0 +Line 4922: 0 +Line 4923: 0 +Line 4924: 0 +Line 4925: 0 +Line 4926: 0 +Line 4927: 0 +Line 4928: 1 +Line 4929: 0 +Line 4930: 1 +Line 4931: 1 +Line 4932: 1 +Line 4933: 0 +Line 4934: 0 +Line 4935: 1 +Line 4936: 1 +Line 4937: 0 +Line 4938: 1 +Line 4939: 1 +Line 4940: 0 +Line 4941: 0 +Line 4942: 0 +Line 4943: 1 +Line 4944: 0 +Line 4945: 0 +Line 4946: 0 +Line 4947: 0 +Line 4948: 0 +Line 4949: 0 +Line 4950: 0 +Line 4951: 0 +Line 4952: 0 +Line 4953: 0 +Line 4954: 0 +Line 4955: 0 +Line 4956: 0 +Line 4957: 0 +Line 4958: 0 +Line 4959: 0 +Line 4960: 1 +Line 4961: 0 +Line 4962: 1 +Line 4963: 1 +Line 4964: 1 +Line 4965: 0 +Line 4966: 0 +Line 4967: 1 +Line 4968: 1 +Line 4969: 0 +Line 4970: 1 +Line 4971: 1 +Line 4972: 0 +Line 4973: 0 +Line 4974: 0 +Line 4975: 1 +Line 4976: 0 +Line 4977: 0 +Line 4978: 0 +Line 4979: 0 +Line 4980: 0 +Line 4981: 0 +Line 4982: 0 +Line 4983: 0 +Line 4984: 0 +Line 4985: 0 +Line 4986: 0 +Line 4987: 0 +Line 4988: 0 +Line 4989: 0 +Line 4990: 0 +Line 4991: 0 +Line 4992: 1 +Line 4993: 0 +Line 4994: 1 +Line 4995: 1 +Line 4996: 1 +Line 4997: 0 +Line 4998: 0 +Line 4999: 1 +Line 5000: 1 +Line 5001: 0 +Line 5002: 1 +Line 5003: 1 +Line 5004: 0 +Line 5005: 0 +Line 5006: 0 +Line 5007: 1 +Line 5008: 0 +Line 5009: 0 +Line 5010: 0 +Line 5011: 0 +Line 5012: 0 +Line 5013: 0 +Line 5014: 0 +Line 5015: 0 +Line 5016: 0 +Line 5017: 0 +Line 5018: 0 +Line 5019: 0 +Line 5020: 0 +Line 5021: 0 +Line 5022: 0 +Line 5023: 0 +Line 5024: 1 +Line 5025: 0 +Line 5026: 1 +Line 5027: 1 +Line 5028: 1 +Line 5029: 0 +Line 5030: 0 +Line 5031: 1 +Line 5032: 1 +Line 5033: 0 +Line 5034: 1 +Line 5035: 1 +Line 5036: 0 +Line 5037: 0 +Line 5038: 0 +Line 5039: 0 +Line 5040: 0 +Line 5041: 0 +Line 5042: 0 +Line 5043: 0 +Line 5044: 0 +Line 5045: 0 +Line 5046: 0 +Line 5047: 0 +Line 5048: 0 +Line 5049: 0 +Line 5050: 0 +Line 5051: 0 +Line 5052: 0 +Line 5053: 0 +Line 5054: 0 +Line 5055: 0 +Line 5056: 1 +Line 5057: 0 +Line 5058: 1 +Line 5059: 1 +Line 5060: 1 +Line 5061: 0 +Line 5062: 0 +Line 5063: 1 +Line 5064: 1 +Line 5065: 0 +Line 5066: 1 +Line 5067: 1 +Line 5068: 0 +Line 5069: 0 +Line 5070: 0 +Line 5071: 0 +Line 5072: 0 +Line 5073: 0 +Line 5074: 0 +Line 5075: 0 +Line 5076: 0 +Line 5077: 0 +Line 5078: 0 +Line 5079: 0 +Line 5080: 0 +Line 5081: 0 +Line 5082: 0 +Line 5083: 0 +Line 5084: 0 +Line 5085: 0 +Line 5086: 0 +Line 5087: 0 +Line 5088: 1 +Line 5089: 0 +Line 5090: 1 +Line 5091: 1 +Line 5092: 1 +Line 5093: 0 +Line 5094: 0 +Line 5095: 1 +Line 5096: 1 +Line 5097: 0 +Line 5098: 1 +Line 5099: 1 +Line 5100: 0 +Line 5101: 0 +Line 5102: 0 +Line 5103: 0 +Line 5104: 0 +Line 5105: 0 +Line 5106: 0 +Line 5107: 0 +Line 5108: 0 +Line 5109: 0 +Line 5110: 0 +Line 5111: 0 +Line 5112: 0 +Line 5113: 0 +Line 5114: 0 +Line 5115: 0 +Line 5116: 0 +Line 5117: 0 +Line 5118: 0 +Line 5119: 0 +Line 5120: 1 +Line 5121: 0 +Line 5122: 1 +Line 5123: 1 +Line 5124: 1 +Line 5125: 0 +Line 5126: 0 +Line 5127: 1 +Line 5128: 1 +Line 5129: 0 +Line 5130: 1 +Line 5131: 1 +Line 5132: 0 +Line 5133: 0 +Line 5134: 0 +Line 5135: 1 +Line 5136: 0 +Line 5137: 0 +Line 5138: 0 +Line 5139: 0 +Line 5140: 0 +Line 5141: 0 +Line 5142: 0 +Line 5143: 0 +Line 5144: 0 +Line 5145: 0 +Line 5146: 0 +Line 5147: 0 +Line 5148: 0 +Line 5149: 0 +Line 5150: 0 +Line 5151: 0 +Line 5152: 1 +Line 5153: 0 +Line 5154: 1 +Line 5155: 1 +Line 5156: 1 +Line 5157: 0 +Line 5158: 0 +Line 5159: 1 +Line 5160: 1 +Line 5161: 0 +Line 5162: 1 +Line 5163: 1 +Line 5164: 0 +Line 5165: 0 +Line 5166: 0 +Line 5167: 1 +Line 5168: 0 +Line 5169: 0 +Line 5170: 0 +Line 5171: 0 +Line 5172: 0 +Line 5173: 0 +Line 5174: 0 +Line 5175: 0 +Line 5176: 0 +Line 5177: 0 +Line 5178: 0 +Line 5179: 0 +Line 5180: 0 +Line 5181: 0 +Line 5182: 0 +Line 5183: 0 +Line 5184: 1 +Line 5185: 0 +Line 5186: 1 +Line 5187: 1 +Line 5188: 1 +Line 5189: 0 +Line 5190: 0 +Line 5191: 1 +Line 5192: 1 +Line 5193: 0 +Line 5194: 1 +Line 5195: 1 +Line 5196: 0 +Line 5197: 0 +Line 5198: 0 +Line 5199: 1 +Line 5200: 0 +Line 5201: 0 +Line 5202: 0 +Line 5203: 0 +Line 5204: 0 +Line 5205: 0 +Line 5206: 0 +Line 5207: 0 +Line 5208: 0 +Line 5209: 0 +Line 5210: 0 +Line 5211: 0 +Line 5212: 0 +Line 5213: 0 +Line 5214: 0 +Line 5215: 0 +Line 5216: 1 +Line 5217: 0 +Line 5218: 1 +Line 5219: 1 +Line 5220: 1 +Line 5221: 0 +Line 5222: 0 +Line 5223: 1 +Line 5224: 1 +Line 5225: 0 +Line 5226: 1 +Line 5227: 1 +Line 5228: 0 +Line 5229: 0 +Line 5230: 0 +Line 5231: 1 +Line 5232: 0 +Line 5233: 0 +Line 5234: 0 +Line 5235: 0 +Line 5236: 0 +Line 5237: 0 +Line 5238: 0 +Line 5239: 0 +Line 5240: 0 +Line 5241: 0 +Line 5242: 0 +Line 5243: 0 +Line 5244: 0 +Line 5245: 0 +Line 5246: 0 +Line 5247: 0 +Line 5248: 1 +Line 5249: 0 +Line 5250: 1 +Line 5251: 1 +Line 5252: 1 +Line 5253: 0 +Line 5254: 0 +Line 5255: 1 +Line 5256: 1 +Line 5257: 0 +Line 5258: 1 +Line 5259: 1 +Line 5260: 0 +Line 5261: 0 +Line 5262: 0 +Line 5263: 1 +Line 5264: 0 +Line 5265: 0 +Line 5266: 0 +Line 5267: 0 +Line 5268: 0 +Line 5269: 0 +Line 5270: 0 +Line 5271: 0 +Line 5272: 0 +Line 5273: 0 +Line 5274: 0 +Line 5275: 0 +Line 5276: 0 +Line 5277: 0 +Line 5278: 0 +Line 5279: 0 +Line 5280: 1 +Line 5281: 0 +Line 5282: 1 +Line 5283: 1 +Line 5284: 1 +Line 5285: 0 +Line 5286: 0 +Line 5287: 1 +Line 5288: 1 +Line 5289: 1 +Line 5290: 0 +Line 5291: 0 +Line 5292: 1 +Line 5293: 0 +Line 5294: 0 +Line 5295: 1 +Line 5296: 0 +Line 5297: 0 +Line 5298: 0 +Line 5299: 0 +Line 5300: 0 +Line 5301: 0 +Line 5302: 0 +Line 5303: 0 +Line 5304: 0 +Line 5305: 0 +Line 5306: 0 +Line 5307: 0 +Line 5308: 0 +Line 5309: 0 +Line 5310: 0 +Line 5311: 0 +Line 5312: 1 +Line 5313: 0 +Line 5314: 1 +Line 5315: 1 +Line 5316: 1 +Line 5317: 0 +Line 5318: 1 +Line 5319: 1 +Line 5320: 0 +Line 5321: 1 +Line 5322: 0 +Line 5323: 0 +Line 5324: 1 +Line 5325: 0 +Line 5326: 1 +Line 5327: 0 +Line 5328: 0 +Line 5329: 0 +Line 5330: 0 +Line 5331: 0 +Line 5332: 0 +Line 5333: 0 +Line 5334: 0 +Line 5335: 0 +Line 5336: 0 +Line 5337: 0 +Line 5338: 0 +Line 5339: 0 +Line 5340: 0 +Line 5341: 0 +Line 5342: 0 +Line 5343: 0 +Line 5344: 1 +Line 5345: 1 +Line 5346: 0 +Line 5347: 0 +Line 5348: 0 +Line 5349: 1 +Line 5350: 0 +Line 5351: 0 +Line 5352: 1 +Line 5353: 1 +Line 5354: 0 +Line 5355: 1 +Line 5356: 1 +Line 5357: 0 +Line 5358: 0 +Line 5359: 0 +Line 5360: 0 +Line 5361: 0 +Line 5362: 0 +Line 5363: 0 +Line 5364: 0 +Line 5365: 0 +Line 5366: 0 +Line 5367: 0 +Line 5368: 0 +Line 5369: 0 +Line 5370: 0 +Line 5371: 0 +Line 5372: 0 +Line 5373: 0 +Line 5374: 0 +Line 5375: 0 +Line 5376: 1 +Line 5377: 1 +Line 5378: 0 +Line 5379: 1 +Line 5380: 1 +Line 5381: 1 +Line 5382: 0 +Line 5383: 0 +Line 5384: 1 +Line 5385: 1 +Line 5386: 0 +Line 5387: 1 +Line 5388: 1 +Line 5389: 0 +Line 5390: 0 +Line 5391: 0 +Line 5392: 0 +Line 5393: 0 +Line 5394: 0 +Line 5395: 0 +Line 5396: 0 +Line 5397: 0 +Line 5398: 0 +Line 5399: 0 +Line 5400: 0 +Line 5401: 0 +Line 5402: 0 +Line 5403: 0 +Line 5404: 0 +Line 5405: 0 +Line 5406: 0 +Line 5407: 0 +Line 5408: 1 +Line 5409: 1 +Line 5410: 1 +Line 5411: 1 +Line 5412: 0 +Line 5413: 1 +Line 5414: 0 +Line 5415: 0 +Line 5416: 1 +Line 5417: 1 +Line 5418: 0 +Line 5419: 1 +Line 5420: 1 +Line 5421: 0 +Line 5422: 0 +Line 5423: 1 +Line 5424: 0 +Line 5425: 0 +Line 5426: 0 +Line 5427: 0 +Line 5428: 0 +Line 5429: 0 +Line 5430: 0 +Line 5431: 0 +Line 5432: 0 +Line 5433: 0 +Line 5434: 0 +Line 5435: 0 +Line 5436: 0 +Line 5437: 0 +Line 5438: 0 +Line 5439: 0 +Line 5440: 1 +Line 5441: 1 +Line 5442: 1 +Line 5443: 1 +Line 5444: 1 +Line 5445: 1 +Line 5446: 1 +Line 5447: 0 +Line 5448: 0 +Line 5449: 1 +Line 5450: 1 +Line 5451: 0 +Line 5452: 0 +Line 5453: 1 +Line 5454: 1 +Line 5455: 1 +Line 5456: 0 +Line 5457: 0 +Line 5458: 0 +Line 5459: 0 +Line 5460: 0 +Line 5461: 0 +Line 5462: 0 +Line 5463: 0 +Line 5464: 0 +Line 5465: 0 +Line 5466: 0 +Line 5467: 0 +Line 5468: 0 +Line 5469: 0 +Line 5470: 0 +Line 5471: 0 +Line 5472: 0 +Line 5473: 0 +Line 5474: 0 +Line 5475: 0 +Line 5476: 0 +Line 5477: 0 +Line 5478: 0 +Line 5479: 0 +Line 5480: 0 +Line 5481: 0 +Line 5482: 0 +Line 5483: 0 +Line 5484: 0 +Line 5485: 0 +Line 5486: 0 +Line 5487: 0 +Line 5488: 0 +Line 5489: 0 +Line 5490: 0 +Line 5491: 0 +Line 5492: 0 +Line 5493: 0 +Line 5494: 0 +Line 5495: 0 +Line 5496: 0 +Line 5497: 0 +Line 5498: 0 +Line 5499: 0 +Line 5500: 0 +Line 5501: 0 +Line 5502: 0 +Line 5503: 0 +Line 5504: 0 +Line 5505: 0 +Line 5506: 0 +Line 5507: 0 +Line 5508: 0 +Line 5509: 0 +Line 5510: 0 +Line 5511: 0 +Line 5512: 0 +Line 5513: 0 +Line 5514: 0 +Line 5515: 0 +Line 5516: 0 +Line 5517: 1 +Line 5518: 0 +Line 5519: 1 +Line 5520: 1 +Line 5521: 1 +Line 5522: 1 +Line 5523: 1 +Line 5524: 1 +Line 5525: 1 +Line 5526: 1 +Line 5527: 1 +Line 5528: 1 +Line 5529: 1 +Line 5530: 1 +Line 5531: 1 +Line 5532: 0 +Line 5533: 0 +Line 5534: 0 +Line 5535: 1 +Line 5536: 0 +Line 5537: 0 +Line 5538: 0 +Line 5539: 0 +Line 5540: 0 +Line 5541: 0 +Line 5542: 0 +Line 5543: 0 +Line 5544: 0 +Line 5545: 0 +Line 5546: 0 +Line 5547: 1 +Line 5548: 0 +Line 5549: 1 +Line 5550: 1 +Line 5551: 1 +Line 5552: 1 +Line 5553: 1 +Line 5554: 1 +Line 5555: 1 +Line 5556: 1 +Line 5557: 1 +Line 5558: 1 +Line 5559: 1 +Line 5560: 1 +Line 5561: 1 +Line 5562: 1 +Line 5563: 0 +Line 5564: 0 +Line 5565: 0 +Line 5566: 0 +Line 5567: 1 +Line 5568: 0 +Line 5569: 0 +Line 5570: 0 +Line 5571: 0 +Line 5572: 0 +Line 5573: 0 +Line 5574: 0 +Line 5575: 0 +Line 5576: 0 +Line 5577: 0 +Line 5578: 1 +Line 5579: 1 +Line 5580: 0 +Line 5581: 1 +Line 5582: 0 +Line 5583: 0 +Line 5584: 1 +Line 5585: 1 +Line 5586: 1 +Line 5587: 1 +Line 5588: 1 +Line 5589: 1 +Line 5590: 1 +Line 5591: 1 +Line 5592: 1 +Line 5593: 1 +Line 5594: 0 +Line 5595: 1 +Line 5596: 0 +Line 5597: 0 +Line 5598: 0 +Line 5599: 1 +Line 5600: 0 +Line 5601: 0 +Line 5602: 0 +Line 5603: 0 +Line 5604: 0 +Line 5605: 0 +Line 5606: 0 +Line 5607: 0 +Line 5608: 0 +Line 5609: 1 +Line 5610: 0 +Line 5611: 1 +Line 5612: 1 +Line 5613: 1 +Line 5614: 0 +Line 5615: 1 +Line 5616: 1 +Line 5617: 1 +Line 5618: 1 +Line 5619: 1 +Line 5620: 1 +Line 5621: 1 +Line 5622: 1 +Line 5623: 1 +Line 5624: 1 +Line 5625: 1 +Line 5626: 0 +Line 5627: 0 +Line 5628: 0 +Line 5629: 0 +Line 5630: 1 +Line 5631: 0 +Line 5632: 0 +Line 5633: 0 +Line 5634: 0 +Line 5635: 0 +Line 5636: 0 +Line 5637: 0 +Line 5638: 0 +Line 5639: 0 +Line 5640: 1 +Line 5641: 0 +Line 5642: 0 +Line 5643: 1 +Line 5644: 0 +Line 5645: 0 +Line 5646: 1 +Line 5647: 0 +Line 5648: 1 +Line 5649: 1 +Line 5650: 1 +Line 5651: 1 +Line 5652: 1 +Line 5653: 1 +Line 5654: 1 +Line 5655: 1 +Line 5656: 1 +Line 5657: 0 +Line 5658: 1 +Line 5659: 1 +Line 5660: 0 +Line 5661: 0 +Line 5662: 1 +Line 5663: 0 +Line 5664: 0 +Line 5665: 0 +Line 5666: 0 +Line 5667: 0 +Line 5668: 0 +Line 5669: 0 +Line 5670: 0 +Line 5671: 0 +Line 5672: 1 +Line 5673: 1 +Line 5674: 0 +Line 5675: 1 +Line 5676: 0 +Line 5677: 0 +Line 5678: 1 +Line 5679: 0 +Line 5680: 1 +Line 5681: 1 +Line 5682: 1 +Line 5683: 1 +Line 5684: 1 +Line 5685: 1 +Line 5686: 1 +Line 5687: 1 +Line 5688: 1 +Line 5689: 0 +Line 5690: 1 +Line 5691: 0 +Line 5692: 0 +Line 5693: 0 +Line 5694: 1 +Line 5695: 1 +Line 5696: 0 +Line 5697: 0 +Line 5698: 0 +Line 5699: 0 +Line 5700: 0 +Line 5701: 0 +Line 5702: 0 +Line 5703: 1 +Line 5704: 0 +Line 5705: 0 +Line 5706: 0 +Line 5707: 1 +Line 5708: 1 +Line 5709: 1 +Line 5710: 0 +Line 5711: 1 +Line 5712: 1 +Line 5713: 1 +Line 5714: 1 +Line 5715: 1 +Line 5716: 1 +Line 5717: 1 +Line 5718: 1 +Line 5719: 1 +Line 5720: 1 +Line 5721: 0 +Line 5722: 0 +Line 5723: 1 +Line 5724: 0 +Line 5725: 1 +Line 5726: 0 +Line 5727: 0 +Line 5728: 0 +Line 5729: 0 +Line 5730: 0 +Line 5731: 0 +Line 5732: 0 +Line 5733: 0 +Line 5734: 0 +Line 5735: 1 +Line 5736: 0 +Line 5737: 1 +Line 5738: 1 +Line 5739: 1 +Line 5740: 0 +Line 5741: 1 +Line 5742: 0 +Line 5743: 0 +Line 5744: 1 +Line 5745: 1 +Line 5746: 1 +Line 5747: 1 +Line 5748: 1 +Line 5749: 1 +Line 5750: 1 +Line 5751: 1 +Line 5752: 1 +Line 5753: 0 +Line 5754: 0 +Line 5755: 0 +Line 5756: 0 +Line 5757: 1 +Line 5758: 0 +Line 5759: 0 +Line 5760: 0 +Line 5761: 0 +Line 5762: 0 +Line 5763: 0 +Line 5764: 0 +Line 5765: 0 +Line 5766: 0 +Line 5767: 1 +Line 5768: 1 +Line 5769: 1 +Line 5770: 0 +Line 5771: 1 +Line 5772: 0 +Line 5773: 1 +Line 5774: 1 +Line 5775: 1 +Line 5776: 1 +Line 5777: 1 +Line 5778: 1 +Line 5779: 1 +Line 5780: 1 +Line 5781: 1 +Line 5782: 1 +Line 5783: 1 +Line 5784: 0 +Line 5785: 1 +Line 5786: 1 +Line 5787: 1 +Line 5788: 0 +Line 5789: 1 +Line 5790: 0 +Line 5791: 1 +Line 5792: 0 +Line 5793: 0 +Line 5794: 0 +Line 5795: 0 +Line 5796: 0 +Line 5797: 0 +Line 5798: 1 +Line 5799: 0 +Line 5800: 0 +Line 5801: 1 +Line 5802: 0 +Line 5803: 0 +Line 5804: 0 +Line 5805: 1 +Line 5806: 0 +Line 5807: 0 +Line 5808: 1 +Line 5809: 1 +Line 5810: 1 +Line 5811: 1 +Line 5812: 1 +Line 5813: 1 +Line 5814: 1 +Line 5815: 1 +Line 5816: 0 +Line 5817: 1 +Line 5818: 1 +Line 5819: 0 +Line 5820: 0 +Line 5821: 1 +Line 5822: 1 +Line 5823: 1 +Line 5824: 0 +Line 5825: 0 +Line 5826: 0 +Line 5827: 0 +Line 5828: 0 +Line 5829: 0 +Line 5830: 1 +Line 5831: 0 +Line 5832: 1 +Line 5833: 0 +Line 5834: 1 +Line 5835: 1 +Line 5836: 1 +Line 5837: 1 +Line 5838: 0 +Line 5839: 0 +Line 5840: 1 +Line 5841: 1 +Line 5842: 1 +Line 5843: 1 +Line 5844: 1 +Line 5845: 1 +Line 5846: 1 +Line 5847: 1 +Line 5848: 0 +Line 5849: 1 +Line 5850: 0 +Line 5851: 1 +Line 5852: 1 +Line 5853: 0 +Line 5854: 0 +Line 5855: 0 +Line 5856: 0 +Line 5857: 0 +Line 5858: 0 +Line 5859: 0 +Line 5860: 0 +Line 5861: 0 +Line 5862: 1 +Line 5863: 1 +Line 5864: 0 +Line 5865: 0 +Line 5866: 1 +Line 5867: 1 +Line 5868: 1 +Line 5869: 1 +Line 5870: 1 +Line 5871: 1 +Line 5872: 1 +Line 5873: 1 +Line 5874: 1 +Line 5875: 1 +Line 5876: 1 +Line 5877: 1 +Line 5878: 1 +Line 5879: 1 +Line 5880: 0 +Line 5881: 1 +Line 5882: 0 +Line 5883: 0 +Line 5884: 1 +Line 5885: 0 +Line 5886: 1 +Line 5887: 0 +Line 5888: 0 +Line 5889: 0 +Line 5890: 0 +Line 5891: 0 +Line 5892: 0 +Line 5893: 0 +Line 5894: 1 +Line 5895: 1 +Line 5896: 1 +Line 5897: 1 +Line 5898: 0 +Line 5899: 0 +Line 5900: 1 +Line 5901: 1 +Line 5902: 0 +Line 5903: 1 +Line 5904: 1 +Line 5905: 1 +Line 5906: 1 +Line 5907: 1 +Line 5908: 1 +Line 5909: 1 +Line 5910: 1 +Line 5911: 1 +Line 5912: 0 +Line 5913: 0 +Line 5914: 1 +Line 5915: 1 +Line 5916: 1 +Line 5917: 0 +Line 5918: 1 +Line 5919: 1 +Line 5920: 0 +Line 5921: 0 +Line 5922: 0 +Line 5923: 0 +Line 5924: 0 +Line 5925: 1 +Line 5926: 0 +Line 5927: 0 +Line 5928: 0 +Line 5929: 1 +Line 5930: 1 +Line 5931: 0 +Line 5932: 0 +Line 5933: 1 +Line 5934: 0 +Line 5935: 1 +Line 5936: 1 +Line 5937: 1 +Line 5938: 1 +Line 5939: 1 +Line 5940: 1 +Line 5941: 1 +Line 5942: 1 +Line 5943: 1 +Line 5944: 0 +Line 5945: 0 +Line 5946: 1 +Line 5947: 0 +Line 5948: 1 +Line 5949: 1 +Line 5950: 1 +Line 5951: 0 +Line 5952: 0 +Line 5953: 0 +Line 5954: 0 +Line 5955: 0 +Line 5956: 0 +Line 5957: 1 +Line 5958: 0 +Line 5959: 1 +Line 5960: 0 +Line 5961: 0 +Line 5962: 0 +Line 5963: 0 +Line 5964: 1 +Line 5965: 0 +Line 5966: 0 +Line 5967: 0 +Line 5968: 1 +Line 5969: 1 +Line 5970: 1 +Line 5971: 1 +Line 5972: 1 +Line 5973: 1 +Line 5974: 1 +Line 5975: 1 +Line 5976: 0 +Line 5977: 0 +Line 5978: 1 +Line 5979: 0 +Line 5980: 0 +Line 5981: 0 +Line 5982: 0 +Line 5983: 0 +Line 5984: 0 +Line 5985: 0 +Line 5986: 0 +Line 5987: 0 +Line 5988: 0 +Line 5989: 1 +Line 5990: 0 +Line 5991: 1 +Line 5992: 1 +Line 5993: 0 +Line 5994: 1 +Line 5995: 1 +Line 5996: 0 +Line 5997: 1 +Line 5998: 0 +Line 5999: 0 +Line 6000: 1 +Line 6001: 1 +Line 6002: 1 +Line 6003: 1 +Line 6004: 1 +Line 6005: 1 +Line 6006: 1 +Line 6007: 1 +Line 6008: 0 +Line 6009: 0 +Line 6010: 0 +Line 6011: 1 +Line 6012: 0 +Line 6013: 0 +Line 6014: 1 +Line 6015: 1 +Line 6016: 0 +Line 6017: 0 +Line 6018: 0 +Line 6019: 0 +Line 6020: 0 +Line 6021: 1 +Line 6022: 1 +Line 6023: 0 +Line 6024: 0 +Line 6025: 1 +Line 6026: 1 +Line 6027: 0 +Line 6028: 1 +Line 6029: 0 +Line 6030: 1 +Line 6031: 1 +Line 6032: 1 +Line 6033: 1 +Line 6034: 1 +Line 6035: 1 +Line 6036: 1 +Line 6037: 1 +Line 6038: 1 +Line 6039: 1 +Line 6040: 0 +Line 6041: 0 +Line 6042: 0 +Line 6043: 0 +Line 6044: 0 +Line 6045: 1 +Line 6046: 1 +Line 6047: 0 +Line 6048: 0 +Line 6049: 0 +Line 6050: 0 +Line 6051: 0 +Line 6052: 0 +Line 6053: 1 +Line 6054: 1 +Line 6055: 1 +Line 6056: 0 +Line 6057: 0 +Line 6058: 1 +Line 6059: 0 +Line 6060: 1 +Line 6061: 0 +Line 6062: 1 +Line 6063: 1 +Line 6064: 1 +Line 6065: 1 +Line 6066: 1 +Line 6067: 1 +Line 6068: 1 +Line 6069: 1 +Line 6070: 1 +Line 6071: 0 +Line 6072: 1 +Line 6073: 1 +Line 6074: 1 +Line 6075: 1 +Line 6076: 1 +Line 6077: 0 +Line 6078: 0 +Line 6079: 1 +Line 6080: 0 +Line 6081: 0 +Line 6082: 0 +Line 6083: 0 +Line 6084: 0 +Line 6085: 1 +Line 6086: 1 +Line 6087: 1 +Line 6088: 1 +Line 6089: 1 +Line 6090: 1 +Line 6091: 1 +Line 6092: 0 +Line 6093: 1 +Line 6094: 0 +Line 6095: 0 +Line 6096: 1 +Line 6097: 1 +Line 6098: 1 +Line 6099: 1 +Line 6100: 1 +Line 6101: 1 +Line 6102: 1 +Line 6103: 0 +Line 6104: 1 +Line 6105: 1 +Line 6106: 1 +Line 6107: 0 +Line 6108: 1 +Line 6109: 1 +Line 6110: 0 +Line 6111: 1 +Line 6112: 0 +Line 6113: 0 +Line 6114: 0 +Line 6115: 0 +Line 6116: 1 +Line 6117: 0 +Line 6118: 0 +Line 6119: 0 +Line 6120: 1 +Line 6121: 1 +Line 6122: 0 +Line 6123: 0 +Line 6124: 0 +Line 6125: 1 +Line 6126: 1 +Line 6127: 0 +Line 6128: 1 +Line 6129: 1 +Line 6130: 1 +Line 6131: 1 +Line 6132: 1 +Line 6133: 1 +Line 6134: 1 +Line 6135: 0 +Line 6136: 1 +Line 6137: 1 +Line 6138: 1 +Line 6139: 0 +Line 6140: 0 +Line 6141: 0 +Line 6142: 0 +Line 6143: 1 +Line 6144: 0 +Line 6145: 0 +Line 6146: 0 +Line 6147: 0 +Line 6148: 1 +Line 6149: 0 +Line 6150: 0 +Line 6151: 1 +Line 6152: 1 +Line 6153: 0 +Line 6154: 1 +Line 6155: 0 +Line 6156: 0 +Line 6157: 0 +Line 6158: 1 +Line 6159: 0 +Line 6160: 1 +Line 6161: 1 +Line 6162: 1 +Line 6163: 1 +Line 6164: 1 +Line 6165: 1 +Line 6166: 1 +Line 6167: 0 +Line 6168: 1 +Line 6169: 1 +Line 6170: 0 +Line 6171: 1 +Line 6172: 0 +Line 6173: 1 +Line 6174: 0 +Line 6175: 1 +Line 6176: 0 +Line 6177: 0 +Line 6178: 0 +Line 6179: 0 +Line 6180: 1 +Line 6181: 0 +Line 6182: 1 +Line 6183: 0 +Line 6184: 1 +Line 6185: 0 +Line 6186: 0 +Line 6187: 0 +Line 6188: 0 +Line 6189: 1 +Line 6190: 0 +Line 6191: 1 +Line 6192: 1 +Line 6193: 1 +Line 6194: 1 +Line 6195: 1 +Line 6196: 1 +Line 6197: 1 +Line 6198: 1 +Line 6199: 0 +Line 6200: 1 +Line 6201: 1 +Line 6202: 0 +Line 6203: 0 +Line 6204: 1 +Line 6205: 0 +Line 6206: 1 +Line 6207: 0 +Line 6208: 0 +Line 6209: 0 +Line 6210: 0 +Line 6211: 0 +Line 6212: 1 +Line 6213: 0 +Line 6214: 1 +Line 6215: 1 +Line 6216: 0 +Line 6217: 1 +Line 6218: 1 +Line 6219: 1 +Line 6220: 0 +Line 6221: 0 +Line 6222: 0 +Line 6223: 1 +Line 6224: 1 +Line 6225: 1 +Line 6226: 1 +Line 6227: 1 +Line 6228: 1 +Line 6229: 1 +Line 6230: 1 +Line 6231: 0 +Line 6232: 1 +Line 6233: 0 +Line 6234: 1 +Line 6235: 1 +Line 6236: 1 +Line 6237: 1 +Line 6238: 1 +Line 6239: 1 +Line 6240: 0 +Line 6241: 0 +Line 6242: 0 +Line 6243: 0 +Line 6244: 1 +Line 6245: 1 +Line 6246: 0 +Line 6247: 0 +Line 6248: 0 +Line 6249: 1 +Line 6250: 1 +Line 6251: 0 +Line 6252: 0 +Line 6253: 1 +Line 6254: 0 +Line 6255: 1 +Line 6256: 1 +Line 6257: 1 +Line 6258: 1 +Line 6259: 1 +Line 6260: 1 +Line 6261: 1 +Line 6262: 1 +Line 6263: 0 +Line 6264: 1 +Line 6265: 0 +Line 6266: 1 +Line 6267: 1 +Line 6268: 0 +Line 6269: 1 +Line 6270: 0 +Line 6271: 1 +Line 6272: 0 +Line 6273: 0 +Line 6274: 0 +Line 6275: 0 +Line 6276: 1 +Line 6277: 1 +Line 6278: 0 +Line 6279: 1 +Line 6280: 0 +Line 6281: 1 +Line 6282: 1 +Line 6283: 0 +Line 6284: 0 +Line 6285: 0 +Line 6286: 0 +Line 6287: 0 +Line 6288: 1 +Line 6289: 1 +Line 6290: 1 +Line 6291: 1 +Line 6292: 1 +Line 6293: 1 +Line 6294: 1 +Line 6295: 0 +Line 6296: 1 +Line 6297: 0 +Line 6298: 1 +Line 6299: 0 +Line 6300: 1 +Line 6301: 0 +Line 6302: 1 +Line 6303: 1 +Line 6304: 0 +Line 6305: 0 +Line 6306: 0 +Line 6307: 0 +Line 6308: 1 +Line 6309: 1 +Line 6310: 1 +Line 6311: 0 +Line 6312: 0 +Line 6313: 1 +Line 6314: 1 +Line 6315: 0 +Line 6316: 0 +Line 6317: 0 +Line 6318: 1 +Line 6319: 1 +Line 6320: 1 +Line 6321: 1 +Line 6322: 1 +Line 6323: 1 +Line 6324: 1 +Line 6325: 1 +Line 6326: 1 +Line 6327: 0 +Line 6328: 1 +Line 6329: 0 +Line 6330: 1 +Line 6331: 0 +Line 6332: 0 +Line 6333: 0 +Line 6334: 0 +Line 6335: 1 +Line 6336: 0 +Line 6337: 0 +Line 6338: 0 +Line 6339: 0 +Line 6340: 1 +Line 6341: 1 +Line 6342: 1 +Line 6343: 1 +Line 6344: 0 +Line 6345: 1 +Line 6346: 1 +Line 6347: 0 +Line 6348: 1 +Line 6349: 1 +Line 6350: 0 +Line 6351: 1 +Line 6352: 1 +Line 6353: 1 +Line 6354: 1 +Line 6355: 1 +Line 6356: 1 +Line 6357: 1 +Line 6358: 1 +Line 6359: 0 +Line 6360: 1 +Line 6361: 0 +Line 6362: 0 +Line 6363: 1 +Line 6364: 1 +Line 6365: 0 +Line 6366: 0 +Line 6367: 0 +Line 6368: 0 +Line 6369: 0 +Line 6370: 0 +Line 6371: 1 +Line 6372: 0 +Line 6373: 0 +Line 6374: 0 +Line 6375: 0 +Line 6376: 0 +Line 6377: 1 +Line 6378: 1 +Line 6379: 1 +Line 6380: 1 +Line 6381: 1 +Line 6382: 0 +Line 6383: 1 +Line 6384: 1 +Line 6385: 1 +Line 6386: 1 +Line 6387: 1 +Line 6388: 1 +Line 6389: 1 +Line 6390: 1 +Line 6391: 0 +Line 6392: 1 +Line 6393: 0 +Line 6394: 0 +Line 6395: 0 +Line 6396: 1 +Line 6397: 1 +Line 6398: 1 +Line 6399: 1 +Line 6400: 0 +Line 6401: 0 +Line 6402: 0 +Line 6403: 1 +Line 6404: 0 +Line 6405: 0 +Line 6406: 0 +Line 6407: 1 +Line 6408: 1 +Line 6409: 0 +Line 6410: 0 +Line 6411: 1 +Line 6412: 0 +Line 6413: 1 +Line 6414: 0 +Line 6415: 0 +Line 6416: 1 +Line 6417: 1 +Line 6418: 1 +Line 6419: 1 +Line 6420: 1 +Line 6421: 1 +Line 6422: 1 +Line 6423: 0 +Line 6424: 1 +Line 6425: 0 +Line 6426: 0 +Line 6427: 0 +Line 6428: 0 +Line 6429: 1 +Line 6430: 1 +Line 6431: 1 +Line 6432: 0 +Line 6433: 0 +Line 6434: 0 +Line 6435: 1 +Line 6436: 0 +Line 6437: 0 +Line 6438: 1 +Line 6439: 0 +Line 6440: 1 +Line 6441: 0 +Line 6442: 1 +Line 6443: 1 +Line 6444: 0 +Line 6445: 0 +Line 6446: 0 +Line 6447: 0 +Line 6448: 1 +Line 6449: 1 +Line 6450: 1 +Line 6451: 1 +Line 6452: 1 +Line 6453: 1 +Line 6454: 1 +Line 6455: 0 +Line 6456: 1 +Line 6457: 0 +Line 6458: 0 +Line 6459: 0 +Line 6460: 0 +Line 6461: 0 +Line 6462: 0 +Line 6463: 0 +Line 6464: 0 +Line 6465: 0 +Line 6466: 0 +Line 6467: 1 +Line 6468: 0 +Line 6469: 0 +Line 6470: 1 +Line 6471: 1 +Line 6472: 1 +Line 6473: 1 +Line 6474: 0 +Line 6475: 1 +Line 6476: 0 +Line 6477: 0 +Line 6478: 1 +Line 6479: 0 +Line 6480: 1 +Line 6481: 1 +Line 6482: 1 +Line 6483: 1 +Line 6484: 1 +Line 6485: 1 +Line 6486: 1 +Line 6487: 0 +Line 6488: 0 +Line 6489: 1 +Line 6490: 1 +Line 6491: 1 +Line 6492: 1 +Line 6493: 0 +Line 6494: 0 +Line 6495: 1 +Line 6496: 0 +Line 6497: 0 +Line 6498: 0 +Line 6499: 1 +Line 6500: 0 +Line 6501: 1 +Line 6502: 0 +Line 6503: 0 +Line 6504: 1 +Line 6505: 1 +Line 6506: 1 +Line 6507: 1 +Line 6508: 1 +Line 6509: 0 +Line 6510: 0 +Line 6511: 1 +Line 6512: 1 +Line 6513: 1 +Line 6514: 1 +Line 6515: 1 +Line 6516: 1 +Line 6517: 1 +Line 6518: 1 +Line 6519: 0 +Line 6520: 0 +Line 6521: 1 +Line 6522: 1 +Line 6523: 1 +Line 6524: 0 +Line 6525: 0 +Line 6526: 1 +Line 6527: 0 +Line 6528: 0 +Line 6529: 0 +Line 6530: 0 +Line 6531: 1 +Line 6532: 0 +Line 6533: 1 +Line 6534: 1 +Line 6535: 0 +Line 6536: 0 +Line 6537: 0 +Line 6538: 1 +Line 6539: 0 +Line 6540: 0 +Line 6541: 1 +Line 6542: 0 +Line 6543: 0 +Line 6544: 1 +Line 6545: 1 +Line 6546: 1 +Line 6547: 1 +Line 6548: 1 +Line 6549: 1 +Line 6550: 1 +Line 6551: 0 +Line 6552: 0 +Line 6553: 1 +Line 6554: 1 +Line 6555: 0 +Line 6556: 1 +Line 6557: 1 +Line 6558: 0 +Line 6559: 0 +Line 6560: 0 +Line 6561: 0 +Line 6562: 0 +Line 6563: 1 +Line 6564: 0 +Line 6565: 1 +Line 6566: 1 +Line 6567: 1 +Line 6568: 0 +Line 6569: 1 +Line 6570: 0 +Line 6571: 1 +Line 6572: 0 +Line 6573: 1 +Line 6574: 0 +Line 6575: 0 +Line 6576: 1 +Line 6577: 1 +Line 6578: 1 +Line 6579: 1 +Line 6580: 1 +Line 6581: 1 +Line 6582: 1 +Line 6583: 0 +Line 6584: 0 +Line 6585: 1 +Line 6586: 1 +Line 6587: 0 +Line 6588: 0 +Line 6589: 1 +Line 6590: 1 +Line 6591: 0 +Line 6592: 0 +Line 6593: 0 +Line 6594: 0 +Line 6595: 1 +Line 6596: 1 +Line 6597: 0 +Line 6598: 0 +Line 6599: 0 +Line 6600: 1 +Line 6601: 0 +Line 6602: 0 +Line 6603: 0 +Line 6604: 1 +Line 6605: 0 +Line 6606: 0 +Line 6607: 0 +Line 6608: 1 +Line 6609: 1 +Line 6610: 1 +Line 6611: 1 +Line 6612: 1 +Line 6613: 1 +Line 6614: 1 +Line 6615: 0 +Line 6616: 0 +Line 6617: 1 +Line 6618: 1 +Line 6619: 0 +Line 6620: 0 +Line 6621: 0 +Line 6622: 0 +Line 6623: 1 +Line 6624: 0 +Line 6625: 0 +Line 6626: 0 +Line 6627: 1 +Line 6628: 1 +Line 6629: 0 +Line 6630: 0 +Line 6631: 1 +Line 6632: 1 +Line 6633: 1 +Line 6634: 0 +Line 6635: 0 +Line 6636: 0 +Line 6637: 0 +Line 6638: 0 +Line 6639: 0 +Line 6640: 1 +Line 6641: 1 +Line 6642: 1 +Line 6643: 1 +Line 6644: 1 +Line 6645: 1 +Line 6646: 1 +Line 6647: 0 +Line 6648: 0 +Line 6649: 1 +Line 6650: 0 +Line 6651: 1 +Line 6652: 1 +Line 6653: 1 +Line 6654: 0 +Line 6655: 1 +Line 6656: 0 +Line 6657: 0 +Line 6658: 0 +Line 6659: 1 +Line 6660: 1 +Line 6661: 0 +Line 6662: 1 +Line 6663: 0 +Line 6664: 1 +Line 6665: 1 +Line 6666: 1 +Line 6667: 1 +Line 6668: 1 +Line 6669: 0 +Line 6670: 1 +Line 6671: 0 +Line 6672: 1 +Line 6673: 1 +Line 6674: 1 +Line 6675: 1 +Line 6676: 1 +Line 6677: 1 +Line 6678: 1 +Line 6679: 0 +Line 6680: 0 +Line 6681: 1 +Line 6682: 0 +Line 6683: 1 +Line 6684: 1 +Line 6685: 0 +Line 6686: 0 +Line 6687: 1 +Line 6688: 0 +Line 6689: 0 +Line 6690: 0 +Line 6691: 1 +Line 6692: 1 +Line 6693: 1 +Line 6694: 0 +Line 6695: 0 +Line 6696: 0 +Line 6697: 0 +Line 6698: 1 +Line 6699: 1 +Line 6700: 1 +Line 6701: 0 +Line 6702: 0 +Line 6703: 0 +Line 6704: 1 +Line 6705: 1 +Line 6706: 1 +Line 6707: 1 +Line 6708: 1 +Line 6709: 1 +Line 6710: 1 +Line 6711: 0 +Line 6712: 0 +Line 6713: 1 +Line 6714: 0 +Line 6715: 1 +Line 6716: 0 +Line 6717: 1 +Line 6718: 1 +Line 6719: 0 +Line 6720: 0 +Line 6721: 0 +Line 6722: 0 +Line 6723: 1 +Line 6724: 1 +Line 6725: 1 +Line 6726: 0 +Line 6727: 1 +Line 6728: 0 +Line 6729: 1 +Line 6730: 1 +Line 6731: 1 +Line 6732: 0 +Line 6733: 1 +Line 6734: 1 +Line 6735: 1 +Line 6736: 1 +Line 6737: 1 +Line 6738: 1 +Line 6739: 1 +Line 6740: 1 +Line 6741: 1 +Line 6742: 1 +Line 6743: 0 +Line 6744: 0 +Line 6745: 1 +Line 6746: 0 +Line 6747: 1 +Line 6748: 0 +Line 6749: 0 +Line 6750: 1 +Line 6751: 1 +Line 6752: 0 +Line 6753: 0 +Line 6754: 0 +Line 6755: 1 +Line 6756: 1 +Line 6757: 1 +Line 6758: 1 +Line 6759: 0 +Line 6760: 1 +Line 6761: 0 +Line 6762: 1 +Line 6763: 1 +Line 6764: 1 +Line 6765: 0 +Line 6766: 0 +Line 6767: 1 +Line 6768: 1 +Line 6769: 1 +Line 6770: 1 +Line 6771: 1 +Line 6772: 1 +Line 6773: 1 +Line 6774: 1 +Line 6775: 0 +Line 6776: 0 +Line 6777: 1 +Line 6778: 0 +Line 6779: 1 +Line 6780: 0 +Line 6781: 0 +Line 6782: 0 +Line 6783: 0 +Line 6784: 0 +Line 6785: 0 +Line 6786: 0 +Line 6787: 1 +Line 6788: 1 +Line 6789: 1 +Line 6790: 1 +Line 6791: 1 +Line 6792: 1 +Line 6793: 1 +Line 6794: 1 +Line 6795: 1 +Line 6796: 1 +Line 6797: 1 +Line 6798: 0 +Line 6799: 0 +Line 6800: 1 +Line 6801: 1 +Line 6802: 1 +Line 6803: 1 +Line 6804: 1 +Line 6805: 1 +Line 6806: 1 +Line 6807: 0 +Line 6808: 0 +Line 6809: 1 +Line 6810: 0 +Line 6811: 0 +Line 6812: 1 +Line 6813: 1 +Line 6814: 1 +Line 6815: 1 +Line 6816: 0 +Line 6817: 0 +Line 6818: 1 +Line 6819: 0 +Line 6820: 0 +Line 6821: 0 +Line 6822: 0 +Line 6823: 1 +Line 6824: 0 +Line 6825: 1 +Line 6826: 0 +Line 6827: 0 +Line 6828: 0 +Line 6829: 0 +Line 6830: 0 +Line 6831: 0 +Line 6832: 1 +Line 6833: 1 +Line 6834: 1 +Line 6835: 1 +Line 6836: 1 +Line 6837: 1 +Line 6838: 1 +Line 6839: 0 +Line 6840: 0 +Line 6841: 1 +Line 6842: 0 +Line 6843: 0 +Line 6844: 1 +Line 6845: 1 +Line 6846: 1 +Line 6847: 0 +Line 6848: 0 +Line 6849: 0 +Line 6850: 1 +Line 6851: 0 +Line 6852: 0 +Line 6853: 0 +Line 6854: 1 +Line 6855: 0 +Line 6856: 1 +Line 6857: 0 +Line 6858: 0 +Line 6859: 0 +Line 6860: 0 +Line 6861: 1 +Line 6862: 0 +Line 6863: 1 +Line 6864: 1 +Line 6865: 1 +Line 6866: 1 +Line 6867: 1 +Line 6868: 1 +Line 6869: 1 +Line 6870: 1 +Line 6871: 0 +Line 6872: 0 +Line 6873: 1 +Line 6874: 0 +Line 6875: 0 +Line 6876: 1 +Line 6877: 1 +Line 6878: 0 +Line 6879: 1 +Line 6880: 0 +Line 6881: 0 +Line 6882: 1 +Line 6883: 0 +Line 6884: 0 +Line 6885: 0 +Line 6886: 1 +Line 6887: 1 +Line 6888: 1 +Line 6889: 1 +Line 6890: 0 +Line 6891: 0 +Line 6892: 1 +Line 6893: 0 +Line 6894: 1 +Line 6895: 0 +Line 6896: 1 +Line 6897: 1 +Line 6898: 1 +Line 6899: 1 +Line 6900: 1 +Line 6901: 1 +Line 6902: 1 +Line 6903: 0 +Line 6904: 0 +Line 6905: 1 +Line 6906: 0 +Line 6907: 0 +Line 6908: 1 +Line 6909: 1 +Line 6910: 0 +Line 6911: 1 +Line 6912: 0 +Line 6913: 0 +Line 6914: 1 +Line 6915: 0 +Line 6916: 0 +Line 6917: 1 +Line 6918: 0 +Line 6919: 1 +Line 6920: 0 +Line 6921: 0 +Line 6922: 0 +Line 6923: 0 +Line 6924: 1 +Line 6925: 1 +Line 6926: 1 +Line 6927: 1 +Line 6928: 1 +Line 6929: 1 +Line 6930: 1 +Line 6931: 1 +Line 6932: 1 +Line 6933: 1 +Line 6934: 1 +Line 6935: 0 +Line 6936: 0 +Line 6937: 1 +Line 6938: 0 +Line 6939: 0 +Line 6940: 1 +Line 6941: 1 +Line 6942: 1 +Line 6943: 0 +Line 6944: 0 +Line 6945: 0 +Line 6946: 1 +Line 6947: 0 +Line 6948: 0 +Line 6949: 1 +Line 6950: 1 +Line 6951: 0 +Line 6952: 0 +Line 6953: 1 +Line 6954: 0 +Line 6955: 1 +Line 6956: 0 +Line 6957: 0 +Line 6958: 1 +Line 6959: 1 +Line 6960: 1 +Line 6961: 1 +Line 6962: 1 +Line 6963: 1 +Line 6964: 1 +Line 6965: 1 +Line 6966: 1 +Line 6967: 0 +Line 6968: 0 +Line 6969: 1 +Line 6970: 0 +Line 6971: 0 +Line 6972: 1 +Line 6973: 1 +Line 6974: 1 +Line 6975: 1 +Line 6976: 0 +Line 6977: 0 +Line 6978: 1 +Line 6979: 0 +Line 6980: 0 +Line 6981: 1 +Line 6982: 1 +Line 6983: 1 +Line 6984: 1 +Line 6985: 0 +Line 6986: 0 +Line 6987: 1 +Line 6988: 0 +Line 6989: 1 +Line 6990: 1 +Line 6991: 0 +Line 6992: 1 +Line 6993: 1 +Line 6994: 1 +Line 6995: 1 +Line 6996: 1 +Line 6997: 1 +Line 6998: 1 +Line 6999: 0 +Line 7000: 0 +Line 7001: 1 +Line 7002: 0 +Line 7003: 1 +Line 7004: 0 +Line 7005: 0 +Line 7006: 0 +Line 7007: 0 +Line 7008: 0 +Line 7009: 0 +Line 7010: 1 +Line 7011: 0 +Line 7012: 1 +Line 7013: 0 +Line 7014: 0 +Line 7015: 0 +Line 7016: 1 +Line 7017: 1 +Line 7018: 0 +Line 7019: 1 +Line 7020: 1 +Line 7021: 0 +Line 7022: 0 +Line 7023: 0 +Line 7024: 1 +Line 7025: 1 +Line 7026: 1 +Line 7027: 1 +Line 7028: 1 +Line 7029: 1 +Line 7030: 1 +Line 7031: 0 +Line 7032: 0 +Line 7033: 1 +Line 7034: 0 +Line 7035: 1 +Line 7036: 0 +Line 7037: 0 +Line 7038: 1 +Line 7039: 1 +Line 7040: 0 +Line 7041: 0 +Line 7042: 1 +Line 7043: 0 +Line 7044: 1 +Line 7045: 0 +Line 7046: 1 +Line 7047: 0 +Line 7048: 0 +Line 7049: 0 +Line 7050: 0 +Line 7051: 1 +Line 7052: 0 +Line 7053: 1 +Line 7054: 1 +Line 7055: 1 +Line 7056: 1 +Line 7057: 1 +Line 7058: 1 +Line 7059: 1 +Line 7060: 1 +Line 7061: 1 +Line 7062: 1 +Line 7063: 0 +Line 7064: 0 +Line 7065: 1 +Line 7066: 0 +Line 7067: 1 +Line 7068: 0 +Line 7069: 1 +Line 7070: 1 +Line 7071: 0 +Line 7072: 0 +Line 7073: 0 +Line 7074: 1 +Line 7075: 0 +Line 7076: 1 +Line 7077: 0 +Line 7078: 1 +Line 7079: 1 +Line 7080: 0 +Line 7081: 1 +Line 7082: 0 +Line 7083: 1 +Line 7084: 0 +Line 7085: 1 +Line 7086: 0 +Line 7087: 1 +Line 7088: 1 +Line 7089: 1 +Line 7090: 1 +Line 7091: 1 +Line 7092: 1 +Line 7093: 1 +Line 7094: 1 +Line 7095: 0 +Line 7096: 0 +Line 7097: 1 +Line 7098: 0 +Line 7099: 1 +Line 7100: 1 +Line 7101: 0 +Line 7102: 0 +Line 7103: 1 +Line 7104: 0 +Line 7105: 0 +Line 7106: 1 +Line 7107: 0 +Line 7108: 1 +Line 7109: 1 +Line 7110: 0 +Line 7111: 0 +Line 7112: 1 +Line 7113: 0 +Line 7114: 0 +Line 7115: 0 +Line 7116: 1 +Line 7117: 1 +Line 7118: 1 +Line 7119: 1 +Line 7120: 1 +Line 7121: 1 +Line 7122: 1 +Line 7123: 1 +Line 7124: 1 +Line 7125: 1 +Line 7126: 1 +Line 7127: 0 +Line 7128: 0 +Line 7129: 1 +Line 7130: 0 +Line 7131: 1 +Line 7132: 1 +Line 7133: 1 +Line 7134: 0 +Line 7135: 1 +Line 7136: 0 +Line 7137: 0 +Line 7138: 1 +Line 7139: 0 +Line 7140: 1 +Line 7141: 1 +Line 7142: 0 +Line 7143: 1 +Line 7144: 1 +Line 7145: 1 +Line 7146: 0 +Line 7147: 0 +Line 7148: 0 +Line 7149: 1 +Line 7150: 1 +Line 7151: 1 +Line 7152: 1 +Line 7153: 1 +Line 7154: 1 +Line 7155: 1 +Line 7156: 1 +Line 7157: 1 +Line 7158: 1 +Line 7159: 0 +Line 7160: 0 +Line 7161: 1 +Line 7162: 1 +Line 7163: 0 +Line 7164: 0 +Line 7165: 0 +Line 7166: 0 +Line 7167: 1 +Line 7168: 0 +Line 7169: 0 +Line 7170: 1 +Line 7171: 0 +Line 7172: 1 +Line 7173: 1 +Line 7174: 1 +Line 7175: 0 +Line 7176: 1 +Line 7177: 1 +Line 7178: 1 +Line 7179: 1 +Line 7180: 1 +Line 7181: 0 +Line 7182: 1 +Line 7183: 1 +Line 7184: 1 +Line 7185: 1 +Line 7186: 1 +Line 7187: 1 +Line 7188: 1 +Line 7189: 1 +Line 7190: 1 +Line 7191: 0 +Line 7192: 0 +Line 7193: 1 +Line 7194: 1 +Line 7195: 0 +Line 7196: 0 +Line 7197: 1 +Line 7198: 1 +Line 7199: 0 +Line 7200: 0 +Line 7201: 0 +Line 7202: 1 +Line 7203: 1 +Line 7204: 0 +Line 7205: 0 +Line 7206: 0 +Line 7207: 0 +Line 7208: 0 +Line 7209: 0 +Line 7210: 1 +Line 7211: 0 +Line 7212: 1 +Line 7213: 0 +Line 7214: 1 +Line 7215: 1 +Line 7216: 1 +Line 7217: 1 +Line 7218: 1 +Line 7219: 1 +Line 7220: 1 +Line 7221: 1 +Line 7222: 1 +Line 7223: 0 +Line 7224: 0 +Line 7225: 1 +Line 7226: 1 +Line 7227: 0 +Line 7228: 1 +Line 7229: 1 +Line 7230: 0 +Line 7231: 0 +Line 7232: 0 +Line 7233: 0 +Line 7234: 1 +Line 7235: 1 +Line 7236: 0 +Line 7237: 0 +Line 7238: 0 +Line 7239: 1 +Line 7240: 0 +Line 7241: 1 +Line 7242: 0 +Line 7243: 1 +Line 7244: 0 +Line 7245: 1 +Line 7246: 1 +Line 7247: 0 +Line 7248: 1 +Line 7249: 1 +Line 7250: 1 +Line 7251: 1 +Line 7252: 1 +Line 7253: 1 +Line 7254: 1 +Line 7255: 0 +Line 7256: 0 +Line 7257: 1 +Line 7258: 1 +Line 7259: 1 +Line 7260: 0 +Line 7261: 0 +Line 7262: 1 +Line 7263: 0 +Line 7264: 0 +Line 7265: 0 +Line 7266: 1 +Line 7267: 1 +Line 7268: 0 +Line 7269: 0 +Line 7270: 1 +Line 7271: 0 +Line 7272: 0 +Line 7273: 1 +Line 7274: 1 +Line 7275: 1 +Line 7276: 1 +Line 7277: 1 +Line 7278: 0 +Line 7279: 1 +Line 7280: 1 +Line 7281: 1 +Line 7282: 1 +Line 7283: 1 +Line 7284: 1 +Line 7285: 1 +Line 7286: 1 +Line 7287: 0 +Line 7288: 0 +Line 7289: 1 +Line 7290: 1 +Line 7291: 1 +Line 7292: 1 +Line 7293: 0 +Line 7294: 0 +Line 7295: 1 +Line 7296: 0 +Line 7297: 0 +Line 7298: 1 +Line 7299: 1 +Line 7300: 0 +Line 7301: 0 +Line 7302: 1 +Line 7303: 1 +Line 7304: 1 +Line 7305: 0 +Line 7306: 0 +Line 7307: 1 +Line 7308: 1 +Line 7309: 1 +Line 7310: 1 +Line 7311: 1 +Line 7312: 1 +Line 7313: 1 +Line 7314: 1 +Line 7315: 1 +Line 7316: 1 +Line 7317: 1 +Line 7318: 1 +Line 7319: 0 +Line 7320: 1 +Line 7321: 0 +Line 7322: 0 +Line 7323: 0 +Line 7324: 0 +Line 7325: 0 +Line 7326: 0 +Line 7327: 0 +Line 7328: 0 +Line 7329: 0 +Line 7330: 1 +Line 7331: 1 +Line 7332: 0 +Line 7333: 1 +Line 7334: 0 +Line 7335: 0 +Line 7336: 1 +Line 7337: 0 +Line 7338: 1 +Line 7339: 1 +Line 7340: 1 +Line 7341: 1 +Line 7342: 0 +Line 7343: 0 +Line 7344: 1 +Line 7345: 1 +Line 7346: 1 +Line 7347: 1 +Line 7348: 1 +Line 7349: 1 +Line 7350: 1 +Line 7351: 0 +Line 7352: 1 +Line 7353: 0 +Line 7354: 0 +Line 7355: 0 +Line 7356: 0 +Line 7357: 1 +Line 7358: 1 +Line 7359: 1 +Line 7360: 0 +Line 7361: 0 +Line 7362: 1 +Line 7363: 1 +Line 7364: 0 +Line 7365: 1 +Line 7366: 0 +Line 7367: 1 +Line 7368: 1 +Line 7369: 1 +Line 7370: 0 +Line 7371: 1 +Line 7372: 0 +Line 7373: 0 +Line 7374: 1 +Line 7375: 0 +Line 7376: 1 +Line 7377: 1 +Line 7378: 1 +Line 7379: 1 +Line 7380: 1 +Line 7381: 1 +Line 7382: 1 +Line 7383: 0 +Line 7384: 1 +Line 7385: 0 +Line 7386: 0 +Line 7387: 0 +Line 7388: 1 +Line 7389: 1 +Line 7390: 1 +Line 7391: 1 +Line 7392: 0 +Line 7393: 0 +Line 7394: 1 +Line 7395: 1 +Line 7396: 0 +Line 7397: 1 +Line 7398: 1 +Line 7399: 0 +Line 7400: 1 +Line 7401: 1 +Line 7402: 1 +Line 7403: 0 +Line 7404: 0 +Line 7405: 0 +Line 7406: 1 +Line 7407: 0 +Line 7408: 1 +Line 7409: 1 +Line 7410: 1 +Line 7411: 1 +Line 7412: 1 +Line 7413: 1 +Line 7414: 1 +Line 7415: 0 +Line 7416: 1 +Line 7417: 0 +Line 7418: 0 +Line 7419: 1 +Line 7420: 1 +Line 7421: 0 +Line 7422: 0 +Line 7423: 0 +Line 7424: 0 +Line 7425: 0 +Line 7426: 1 +Line 7427: 1 +Line 7428: 0 +Line 7429: 1 +Line 7430: 1 +Line 7431: 1 +Line 7432: 1 +Line 7433: 1 +Line 7434: 1 +Line 7435: 0 +Line 7436: 1 +Line 7437: 1 +Line 7438: 0 +Line 7439: 0 +Line 7440: 1 +Line 7441: 1 +Line 7442: 1 +Line 7443: 1 +Line 7444: 1 +Line 7445: 1 +Line 7446: 1 +Line 7447: 0 +Line 7448: 1 +Line 7449: 0 +Line 7450: 1 +Line 7451: 0 +Line 7452: 0 +Line 7453: 0 +Line 7454: 0 +Line 7455: 1 +Line 7456: 0 +Line 7457: 0 +Line 7458: 1 +Line 7459: 1 +Line 7460: 1 +Line 7461: 0 +Line 7462: 0 +Line 7463: 0 +Line 7464: 1 +Line 7465: 1 +Line 7466: 1 +Line 7467: 0 +Line 7468: 1 +Line 7469: 1 +Line 7470: 1 +Line 7471: 1 +Line 7472: 1 +Line 7473: 1 +Line 7474: 1 +Line 7475: 1 +Line 7476: 1 +Line 7477: 1 +Line 7478: 1 +Line 7479: 0 +Line 7480: 1 +Line 7481: 0 +Line 7482: 1 +Line 7483: 0 +Line 7484: 1 +Line 7485: 0 +Line 7486: 1 +Line 7487: 1 +Line 7488: 0 +Line 7489: 0 +Line 7490: 1 +Line 7491: 1 +Line 7492: 1 +Line 7493: 0 +Line 7494: 0 +Line 7495: 1 +Line 7496: 1 +Line 7497: 1 +Line 7498: 1 +Line 7499: 0 +Line 7500: 1 +Line 7501: 0 +Line 7502: 1 +Line 7503: 0 +Line 7504: 1 +Line 7505: 1 +Line 7506: 1 +Line 7507: 1 +Line 7508: 1 +Line 7509: 1 +Line 7510: 1 +Line 7511: 0 +Line 7512: 1 +Line 7513: 0 +Line 7514: 1 +Line 7515: 1 +Line 7516: 0 +Line 7517: 1 +Line 7518: 0 +Line 7519: 1 +Line 7520: 0 +Line 7521: 0 +Line 7522: 1 +Line 7523: 1 +Line 7524: 1 +Line 7525: 0 +Line 7526: 1 +Line 7527: 0 +Line 7528: 1 +Line 7529: 1 +Line 7530: 0 +Line 7531: 1 +Line 7532: 1 +Line 7533: 1 +Line 7534: 1 +Line 7535: 0 +Line 7536: 1 +Line 7537: 1 +Line 7538: 1 +Line 7539: 1 +Line 7540: 1 +Line 7541: 1 +Line 7542: 1 +Line 7543: 0 +Line 7544: 1 +Line 7545: 0 +Line 7546: 1 +Line 7547: 1 +Line 7548: 1 +Line 7549: 1 +Line 7550: 1 +Line 7551: 1 +Line 7552: 0 +Line 7553: 0 +Line 7554: 1 +Line 7555: 1 +Line 7556: 1 +Line 7557: 0 +Line 7558: 1 +Line 7559: 1 +Line 7560: 1 +Line 7561: 1 +Line 7562: 0 +Line 7563: 0 +Line 7564: 1 +Line 7565: 0 +Line 7566: 1 +Line 7567: 0 +Line 7568: 1 +Line 7569: 1 +Line 7570: 1 +Line 7571: 1 +Line 7572: 1 +Line 7573: 1 +Line 7574: 1 +Line 7575: 0 +Line 7576: 1 +Line 7577: 1 +Line 7578: 0 +Line 7579: 0 +Line 7580: 1 +Line 7581: 0 +Line 7582: 1 +Line 7583: 0 +Line 7584: 0 +Line 7585: 0 +Line 7586: 1 +Line 7587: 1 +Line 7588: 1 +Line 7589: 1 +Line 7590: 0 +Line 7591: 0 +Line 7592: 1 +Line 7593: 0 +Line 7594: 1 +Line 7595: 0 +Line 7596: 1 +Line 7597: 1 +Line 7598: 0 +Line 7599: 1 +Line 7600: 1 +Line 7601: 1 +Line 7602: 1 +Line 7603: 1 +Line 7604: 1 +Line 7605: 1 +Line 7606: 1 +Line 7607: 0 +Line 7608: 1 +Line 7609: 1 +Line 7610: 0 +Line 7611: 1 +Line 7612: 0 +Line 7613: 1 +Line 7614: 0 +Line 7615: 1 +Line 7616: 0 +Line 7617: 0 +Line 7618: 1 +Line 7619: 1 +Line 7620: 1 +Line 7621: 1 +Line 7622: 0 +Line 7623: 1 +Line 7624: 1 +Line 7625: 0 +Line 7626: 0 +Line 7627: 0 +Line 7628: 1 +Line 7629: 0 +Line 7630: 0 +Line 7631: 1 +Line 7632: 1 +Line 7633: 1 +Line 7634: 1 +Line 7635: 1 +Line 7636: 1 +Line 7637: 1 +Line 7638: 1 +Line 7639: 0 +Line 7640: 1 +Line 7641: 1 +Line 7642: 1 +Line 7643: 0 +Line 7644: 0 +Line 7645: 0 +Line 7646: 0 +Line 7647: 1 +Line 7648: 0 +Line 7649: 0 +Line 7650: 1 +Line 7651: 1 +Line 7652: 1 +Line 7653: 1 +Line 7654: 1 +Line 7655: 0 +Line 7656: 0 +Line 7657: 1 +Line 7658: 0 +Line 7659: 1 +Line 7660: 1 +Line 7661: 0 +Line 7662: 1 +Line 7663: 1 +Line 7664: 1 +Line 7665: 1 +Line 7666: 1 +Line 7667: 1 +Line 7668: 1 +Line 7669: 1 +Line 7670: 1 +Line 7671: 0 +Line 7672: 1 +Line 7673: 1 +Line 7674: 1 +Line 7675: 0 +Line 7676: 1 +Line 7677: 1 +Line 7678: 0 +Line 7679: 1 +Line 7680: 0 +Line 7681: 0 +Line 7682: 1 +Line 7683: 1 +Line 7684: 1 +Line 7685: 1 +Line 7686: 1 +Line 7687: 1 +Line 7688: 0 +Line 7689: 0 +Line 7690: 1 +Line 7691: 0 +Line 7692: 0 +Line 7693: 1 +Line 7694: 0 +Line 7695: 0 +Line 7696: 1 +Line 7697: 1 +Line 7698: 1 +Line 7699: 1 +Line 7700: 1 +Line 7701: 1 +Line 7702: 1 +Line 7703: 0 +Line 7704: 1 +Line 7705: 1 +Line 7706: 1 +Line 7707: 1 +Line 7708: 1 +Line 7709: 0 +Line 7710: 0 +Line 7711: 1 +Line 7712: 0 +Line 7713: 0 +Line 7714: 1 +Line 7715: 1 +Line 7716: 1 +Line 7717: 1 +Line 7718: 1 +Line 7719: 1 +Line 7720: 1 +Line 7721: 1 +Line 7722: 1 +Line 7723: 0 +Line 7724: 0 +Line 7725: 1 +Line 7726: 0 +Line 7727: 0 +Line 7728: 1 +Line 7729: 1 +Line 7730: 1 +Line 7731: 1 +Line 7732: 1 +Line 7733: 1 +Line 7734: 1 +Line 7735: 1 +Line 7736: 0 +Line 7737: 0 +Line 7738: 0 +Line 7739: 0 +Line 7740: 0 +Line 7741: 1 +Line 7742: 1 +Line 7743: 0 +Line 7744: 0 +Line 7745: 1 +Line 7746: 0 +Line 7747: 0 +Line 7748: 0 +Line 7749: 0 +Line 7750: 0 +Line 7751: 0 +Line 7752: 1 +Line 7753: 0 +Line 7754: 0 +Line 7755: 1 +Line 7756: 1 +Line 7757: 0 +Line 7758: 1 +Line 7759: 1 +Line 7760: 1 +Line 7761: 1 +Line 7762: 1 +Line 7763: 1 +Line 7764: 1 +Line 7765: 1 +Line 7766: 1 +Line 7767: 1 +Line 7768: 0 +Line 7769: 0 +Line 7770: 0 +Line 7771: 1 +Line 7772: 0 +Line 7773: 0 +Line 7774: 1 +Line 7775: 1 +Line 7776: 0 +Line 7777: 1 +Line 7778: 0 +Line 7779: 0 +Line 7780: 0 +Line 7781: 0 +Line 7782: 0 +Line 7783: 1 +Line 7784: 0 +Line 7785: 1 +Line 7786: 0 +Line 7787: 0 +Line 7788: 0 +Line 7789: 1 +Line 7790: 1 +Line 7791: 1 +Line 7792: 1 +Line 7793: 1 +Line 7794: 1 +Line 7795: 1 +Line 7796: 1 +Line 7797: 1 +Line 7798: 1 +Line 7799: 1 +Line 7800: 0 +Line 7801: 0 +Line 7802: 1 +Line 7803: 0 +Line 7804: 0 +Line 7805: 0 +Line 7806: 0 +Line 7807: 0 +Line 7808: 0 +Line 7809: 1 +Line 7810: 0 +Line 7811: 0 +Line 7812: 0 +Line 7813: 0 +Line 7814: 0 +Line 7815: 1 +Line 7816: 1 +Line 7817: 1 +Line 7818: 1 +Line 7819: 0 +Line 7820: 1 +Line 7821: 0 +Line 7822: 1 +Line 7823: 0 +Line 7824: 1 +Line 7825: 1 +Line 7826: 1 +Line 7827: 1 +Line 7828: 1 +Line 7829: 1 +Line 7830: 1 +Line 7831: 1 +Line 7832: 0 +Line 7833: 0 +Line 7834: 1 +Line 7835: 0 +Line 7836: 1 +Line 7837: 1 +Line 7838: 1 +Line 7839: 0 +Line 7840: 0 +Line 7841: 1 +Line 7842: 0 +Line 7843: 0 +Line 7844: 0 +Line 7845: 0 +Line 7846: 1 +Line 7847: 0 +Line 7848: 1 +Line 7849: 0 +Line 7850: 0 +Line 7851: 0 +Line 7852: 0 +Line 7853: 0 +Line 7854: 1 +Line 7855: 0 +Line 7856: 1 +Line 7857: 1 +Line 7858: 1 +Line 7859: 1 +Line 7860: 1 +Line 7861: 1 +Line 7862: 1 +Line 7863: 1 +Line 7864: 0 +Line 7865: 0 +Line 7866: 1 +Line 7867: 1 +Line 7868: 1 +Line 7869: 0 +Line 7870: 1 +Line 7871: 1 +Line 7872: 0 +Line 7873: 1 +Line 7874: 0 +Line 7875: 0 +Line 7876: 0 +Line 7877: 0 +Line 7878: 1 +Line 7879: 1 +Line 7880: 0 +Line 7881: 0 +Line 7882: 0 +Line 7883: 1 +Line 7884: 0 +Line 7885: 0 +Line 7886: 0 +Line 7887: 0 +Line 7888: 1 +Line 7889: 1 +Line 7890: 1 +Line 7891: 1 +Line 7892: 1 +Line 7893: 1 +Line 7894: 1 +Line 7895: 1 +Line 7896: 0 +Line 7897: 1 +Line 7898: 0 +Line 7899: 0 +Line 7900: 1 +Line 7901: 0 +Line 7902: 1 +Line 7903: 0 +Line 7904: 0 +Line 7905: 1 +Line 7906: 0 +Line 7907: 0 +Line 7908: 0 +Line 7909: 0 +Line 7910: 1 +Line 7911: 1 +Line 7912: 1 +Line 7913: 0 +Line 7914: 0 +Line 7915: 1 +Line 7916: 0 +Line 7917: 0 +Line 7918: 1 +Line 7919: 1 +Line 7920: 1 +Line 7921: 1 +Line 7922: 1 +Line 7923: 1 +Line 7924: 1 +Line 7925: 1 +Line 7926: 1 +Line 7927: 1 +Line 7928: 0 +Line 7929: 1 +Line 7930: 0 +Line 7931: 1 +Line 7932: 1 +Line 7933: 0 +Line 7934: 0 +Line 7935: 0 +Line 7936: 0 +Line 7937: 1 +Line 7938: 0 +Line 7939: 0 +Line 7940: 0 +Line 7941: 1 +Line 7942: 0 +Line 7943: 0 +Line 7944: 0 +Line 7945: 0 +Line 7946: 0 +Line 7947: 0 +Line 7948: 1 +Line 7949: 0 +Line 7950: 1 +Line 7951: 1 +Line 7952: 1 +Line 7953: 1 +Line 7954: 1 +Line 7955: 1 +Line 7956: 1 +Line 7957: 1 +Line 7958: 1 +Line 7959: 1 +Line 7960: 0 +Line 7961: 1 +Line 7962: 1 +Line 7963: 0 +Line 7964: 0 +Line 7965: 1 +Line 7966: 1 +Line 7967: 1 +Line 7968: 0 +Line 7969: 1 +Line 7970: 0 +Line 7971: 0 +Line 7972: 0 +Line 7973: 1 +Line 7974: 0 +Line 7975: 0 +Line 7976: 0 +Line 7977: 1 +Line 7978: 1 +Line 7979: 1 +Line 7980: 1 +Line 7981: 0 +Line 7982: 0 +Line 7983: 0 +Line 7984: 1 +Line 7985: 1 +Line 7986: 1 +Line 7987: 1 +Line 7988: 1 +Line 7989: 1 +Line 7990: 1 +Line 7991: 1 +Line 7992: 0 +Line 7993: 1 +Line 7994: 1 +Line 7995: 1 +Line 7996: 0 +Line 7997: 1 +Line 7998: 0 +Line 7999: 1 +Line 8000: 0 +Line 8001: 1 +Line 8002: 0 +Line 8003: 0 +Line 8004: 0 +Line 8005: 1 +Line 8006: 0 +Line 8007: 0 +Line 8008: 1 +Line 8009: 1 +Line 8010: 0 +Line 8011: 1 +Line 8012: 1 +Line 8013: 0 +Line 8014: 1 +Line 8015: 1 +Line 8016: 1 +Line 8017: 1 +Line 8018: 1 +Line 8019: 1 +Line 8020: 1 +Line 8021: 1 +Line 8022: 1 +Line 8023: 1 +Line 8024: 1 +Line 8025: 0 +Line 8026: 0 +Line 8027: 0 +Line 8028: 0 +Line 8029: 1 +Line 8030: 0 +Line 8031: 0 +Line 8032: 0 +Line 8033: 1 +Line 8034: 0 +Line 8035: 0 +Line 8036: 0 +Line 8037: 1 +Line 8038: 0 +Line 8039: 1 +Line 8040: 0 +Line 8041: 0 +Line 8042: 1 +Line 8043: 1 +Line 8044: 0 +Line 8045: 0 +Line 8046: 1 +Line 8047: 0 +Line 8048: 1 +Line 8049: 1 +Line 8050: 1 +Line 8051: 1 +Line 8052: 1 +Line 8053: 1 +Line 8054: 1 +Line 8055: 1 +Line 8056: 1 +Line 8057: 0 +Line 8058: 0 +Line 8059: 1 +Line 8060: 0 +Line 8061: 1 +Line 8062: 0 +Line 8063: 0 +Line 8064: 0 +Line 8065: 1 +Line 8066: 0 +Line 8067: 0 +Line 8068: 0 +Line 8069: 1 +Line 8070: 0 +Line 8071: 1 +Line 8072: 0 +Line 8073: 1 +Line 8074: 1 +Line 8075: 1 +Line 8076: 1 +Line 8077: 1 +Line 8078: 0 +Line 8079: 1 +Line 8080: 1 +Line 8081: 1 +Line 8082: 1 +Line 8083: 1 +Line 8084: 1 +Line 8085: 1 +Line 8086: 1 +Line 8087: 1 +Line 8088: 1 +Line 8089: 0 +Line 8090: 1 +Line 8091: 0 +Line 8092: 0 +Line 8093: 0 +Line 8094: 1 +Line 8095: 1 +Line 8096: 0 +Line 8097: 1 +Line 8098: 0 +Line 8099: 0 +Line 8100: 0 +Line 8101: 1 +Line 8102: 0 +Line 8103: 1 +Line 8104: 1 +Line 8105: 0 +Line 8106: 1 +Line 8107: 1 +Line 8108: 1 +Line 8109: 1 +Line 8110: 0 +Line 8111: 1 +Line 8112: 1 +Line 8113: 1 +Line 8114: 1 +Line 8115: 1 +Line 8116: 1 +Line 8117: 1 +Line 8118: 1 +Line 8119: 1 +Line 8120: 1 +Line 8121: 0 +Line 8122: 1 +Line 8123: 1 +Line 8124: 0 +Line 8125: 0 +Line 8126: 1 +Line 8127: 0 +Line 8128: 0 +Line 8129: 1 +Line 8130: 0 +Line 8131: 0 +Line 8132: 0 +Line 8133: 1 +Line 8134: 0 +Line 8135: 1 +Line 8136: 1 +Line 8137: 1 +Line 8138: 1 +Line 8139: 1 +Line 8140: 0 +Line 8141: 0 +Line 8142: 1 +Line 8143: 0 +Line 8144: 1 +Line 8145: 1 +Line 8146: 1 +Line 8147: 1 +Line 8148: 1 +Line 8149: 1 +Line 8150: 1 +Line 8151: 1 +Line 8152: 1 +Line 8153: 1 +Line 8154: 0 +Line 8155: 0 +Line 8156: 0 +Line 8157: 0 +Line 8158: 1 +Line 8159: 0 +Line 8160: 0 +Line 8161: 1 +Line 8162: 0 +Line 8163: 0 +Line 8164: 0 +Line 8165: 1 +Line 8166: 1 +Line 8167: 0 +Line 8168: 0 +Line 8169: 0 +Line 8170: 0 +Line 8171: 1 +Line 8172: 1 +Line 8173: 0 +Line 8174: 1 +Line 8175: 1 +Line 8176: 1 +Line 8177: 1 +Line 8178: 1 +Line 8179: 1 +Line 8180: 1 +Line 8181: 1 +Line 8182: 1 +Line 8183: 1 +Line 8184: 1 +Line 8185: 1 +Line 8186: 0 +Line 8187: 1 +Line 8188: 0 +Line 8189: 0 +Line 8190: 0 +Line 8191: 1 +Line 8192: 0 +Line 8193: 1 +Line 8194: 0 +Line 8195: 0 +Line 8196: 0 +Line 8197: 1 +Line 8198: 1 +Line 8199: 0 +Line 8200: 0 +Line 8201: 0 +Line 8202: 1 +Line 8203: 1 +Line 8204: 1 +Line 8205: 0 +Line 8206: 0 +Line 8207: 0 +Line 8208: 1 +Line 8209: 1 +Line 8210: 1 +Line 8211: 1 +Line 8212: 1 +Line 8213: 1 +Line 8214: 1 +Line 8215: 1 +Line 8216: 1 +Line 8217: 1 +Line 8218: 1 +Line 8219: 0 +Line 8220: 0 +Line 8221: 0 +Line 8222: 0 +Line 8223: 1 +Line 8224: 0 +Line 8225: 1 +Line 8226: 0 +Line 8227: 0 +Line 8228: 0 +Line 8229: 1 +Line 8230: 1 +Line 8231: 0 +Line 8232: 0 +Line 8233: 1 +Line 8234: 0 +Line 8235: 0 +Line 8236: 1 +Line 8237: 0 +Line 8238: 1 +Line 8239: 0 +Line 8240: 1 +Line 8241: 1 +Line 8242: 1 +Line 8243: 1 +Line 8244: 1 +Line 8245: 1 +Line 8246: 1 +Line 8247: 1 +Line 8248: 1 +Line 8249: 1 +Line 8250: 1 +Line 8251: 1 +Line 8252: 0 +Line 8253: 0 +Line 8254: 0 +Line 8255: 1 +Line 8256: 0 +Line 8257: 1 +Line 8258: 0 +Line 8259: 0 +Line 8260: 0 +Line 8261: 1 +Line 8262: 1 +Line 8263: 0 +Line 8264: 0 +Line 8265: 1 +Line 8266: 0 +Line 8267: 1 +Line 8268: 0 +Line 8269: 0 +Line 8270: 0 +Line 8271: 0 +Line 8272: 0 +Line 8273: 0 +Line 8274: 0 +Line 8275: 0 +Line 8276: 0 +Line 8277: 0 +Line 8278: 0 +Line 8279: 0 +Line 8280: 0 +Line 8281: 0 +Line 8282: 0 +Line 8283: 0 +Line 8284: 0 +Line 8285: 0 +Line 8286: 0 +Line 8287: 0 +Line 8288: 0 +Line 8289: 1 +Line 8290: 0 +Line 8291: 0 +Line 8292: 0 +Line 8293: 1 +Line 8294: 1 +Line 8295: 0 +Line 8296: 0 +Line 8297: 1 +Line 8298: 0 +Line 8299: 0 +Line 8300: 1 +Line 8301: 0 +Line 8302: 1 +Line 8303: 0 +Line 8304: 0 +Line 8305: 0 +Line 8306: 0 +Line 8307: 0 +Line 8308: 0 +Line 8309: 0 +Line 8310: 0 +Line 8311: 0 +Line 8312: 0 +Line 8313: 0 +Line 8314: 0 +Line 8315: 0 +Line 8316: 1 +Line 8317: 1 +Line 8318: 1 +Line 8319: 1 +Line 8320: 0 +Line 8321: 1 +Line 8322: 0 +Line 8323: 0 +Line 8324: 0 +Line 8325: 1 +Line 8326: 1 +Line 8327: 0 +Line 8328: 0 +Line 8329: 0 +Line 8330: 1 +Line 8331: 1 +Line 8332: 1 +Line 8333: 0 +Line 8334: 0 +Line 8335: 0 +Line 8336: 0 +Line 8337: 0 +Line 8338: 0 +Line 8339: 0 +Line 8340: 0 +Line 8341: 0 +Line 8342: 0 +Line 8343: 0 +Line 8344: 0 +Line 8345: 0 +Line 8346: 0 +Line 8347: 1 +Line 8348: 1 +Line 8349: 1 +Line 8350: 1 +Line 8351: 1 +Line 8352: 0 +Line 8353: 1 +Line 8354: 0 +Line 8355: 0 +Line 8356: 0 +Line 8357: 1 +Line 8358: 1 +Line 8359: 0 +Line 8360: 0 +Line 8361: 0 +Line 8362: 0 +Line 8363: 1 +Line 8364: 1 +Line 8365: 0 +Line 8366: 1 +Line 8367: 1 +Line 8368: 0 +Line 8369: 0 +Line 8370: 0 +Line 8371: 0 +Line 8372: 0 +Line 8373: 0 +Line 8374: 0 +Line 8375: 0 +Line 8376: 0 +Line 8377: 0 +Line 8378: 1 +Line 8379: 0 +Line 8380: 1 +Line 8381: 1 +Line 8382: 1 +Line 8383: 1 +Line 8384: 0 +Line 8385: 1 +Line 8386: 0 +Line 8387: 0 +Line 8388: 0 +Line 8389: 1 +Line 8390: 0 +Line 8391: 1 +Line 8392: 1 +Line 8393: 1 +Line 8394: 1 +Line 8395: 1 +Line 8396: 0 +Line 8397: 0 +Line 8398: 1 +Line 8399: 0 +Line 8400: 0 +Line 8401: 0 +Line 8402: 0 +Line 8403: 0 +Line 8404: 0 +Line 8405: 0 +Line 8406: 0 +Line 8407: 0 +Line 8408: 0 +Line 8409: 0 +Line 8410: 1 +Line 8411: 1 +Line 8412: 1 +Line 8413: 1 +Line 8414: 1 +Line 8415: 0 +Line 8416: 0 +Line 8417: 1 +Line 8418: 0 +Line 8419: 0 +Line 8420: 0 +Line 8421: 1 +Line 8422: 0 +Line 8423: 1 +Line 8424: 1 +Line 8425: 0 +Line 8426: 1 +Line 8427: 1 +Line 8428: 1 +Line 8429: 1 +Line 8430: 0 +Line 8431: 1 +Line 8432: 0 +Line 8433: 0 +Line 8434: 0 +Line 8435: 0 +Line 8436: 0 +Line 8437: 0 +Line 8438: 0 +Line 8439: 0 +Line 8440: 0 +Line 8441: 1 +Line 8442: 0 +Line 8443: 0 +Line 8444: 1 +Line 8445: 1 +Line 8446: 1 +Line 8447: 0 +Line 8448: 0 +Line 8449: 1 +Line 8450: 0 +Line 8451: 0 +Line 8452: 0 +Line 8453: 1 +Line 8454: 0 +Line 8455: 1 +Line 8456: 0 +Line 8457: 1 +Line 8458: 1 +Line 8459: 1 +Line 8460: 1 +Line 8461: 1 +Line 8462: 0 +Line 8463: 1 +Line 8464: 0 +Line 8465: 0 +Line 8466: 0 +Line 8467: 0 +Line 8468: 0 +Line 8469: 0 +Line 8470: 0 +Line 8471: 0 +Line 8472: 0 +Line 8473: 1 +Line 8474: 0 +Line 8475: 1 +Line 8476: 1 +Line 8477: 1 +Line 8478: 0 +Line 8479: 1 +Line 8480: 0 +Line 8481: 1 +Line 8482: 0 +Line 8483: 0 +Line 8484: 0 +Line 8485: 1 +Line 8486: 0 +Line 8487: 1 +Line 8488: 0 +Line 8489: 0 +Line 8490: 1 +Line 8491: 1 +Line 8492: 0 +Line 8493: 0 +Line 8494: 1 +Line 8495: 0 +Line 8496: 0 +Line 8497: 0 +Line 8498: 0 +Line 8499: 0 +Line 8500: 0 +Line 8501: 0 +Line 8502: 0 +Line 8503: 0 +Line 8504: 0 +Line 8505: 1 +Line 8506: 1 +Line 8507: 0 +Line 8508: 1 +Line 8509: 1 +Line 8510: 0 +Line 8511: 0 +Line 8512: 0 +Line 8513: 1 +Line 8514: 0 +Line 8515: 0 +Line 8516: 0 +Line 8517: 1 +Line 8518: 0 +Line 8519: 0 +Line 8520: 1 +Line 8521: 1 +Line 8522: 0 +Line 8523: 1 +Line 8524: 1 +Line 8525: 0 +Line 8526: 1 +Line 8527: 1 +Line 8528: 0 +Line 8529: 0 +Line 8530: 0 +Line 8531: 0 +Line 8532: 0 +Line 8533: 0 +Line 8534: 0 +Line 8535: 0 +Line 8536: 0 +Line 8537: 1 +Line 8538: 1 +Line 8539: 1 +Line 8540: 1 +Line 8541: 1 +Line 8542: 0 +Line 8543: 0 +Line 8544: 0 +Line 8545: 1 +Line 8546: 0 +Line 8547: 0 +Line 8548: 0 +Line 8549: 1 +Line 8550: 0 +Line 8551: 0 +Line 8552: 0 +Line 8553: 1 +Line 8554: 1 +Line 8555: 1 +Line 8556: 1 +Line 8557: 0 +Line 8558: 0 +Line 8559: 0 +Line 8560: 0 +Line 8561: 0 +Line 8562: 0 +Line 8563: 0 +Line 8564: 0 +Line 8565: 0 +Line 8566: 0 +Line 8567: 0 +Line 8568: 1 +Line 8569: 0 +Line 8570: 0 +Line 8571: 0 +Line 8572: 1 +Line 8573: 0 +Line 8574: 1 +Line 8575: 1 +Line 8576: 0 +Line 8577: 1 +Line 8578: 0 +Line 8579: 0 +Line 8580: 0 +Line 8581: 1 +Line 8582: 0 +Line 8583: 0 +Line 8584: 0 +Line 8585: 0 +Line 8586: 0 +Line 8587: 0 +Line 8588: 1 +Line 8589: 0 +Line 8590: 1 +Line 8591: 1 +Line 8592: 0 +Line 8593: 0 +Line 8594: 0 +Line 8595: 0 +Line 8596: 0 +Line 8597: 0 +Line 8598: 0 +Line 8599: 0 +Line 8600: 1 +Line 8601: 0 +Line 8602: 0 +Line 8603: 1 +Line 8604: 1 +Line 8605: 0 +Line 8606: 0 +Line 8607: 1 +Line 8608: 0 +Line 8609: 1 +Line 8610: 0 +Line 8611: 0 +Line 8612: 0 +Line 8613: 0 +Line 8614: 1 +Line 8615: 1 +Line 8616: 1 +Line 8617: 0 +Line 8618: 0 +Line 8619: 1 +Line 8620: 0 +Line 8621: 0 +Line 8622: 1 +Line 8623: 1 +Line 8624: 0 +Line 8625: 0 +Line 8626: 0 +Line 8627: 0 +Line 8628: 0 +Line 8629: 0 +Line 8630: 0 +Line 8631: 0 +Line 8632: 1 +Line 8633: 0 +Line 8634: 1 +Line 8635: 0 +Line 8636: 1 +Line 8637: 0 +Line 8638: 0 +Line 8639: 0 +Line 8640: 0 +Line 8641: 1 +Line 8642: 0 +Line 8643: 0 +Line 8644: 0 +Line 8645: 0 +Line 8646: 1 +Line 8647: 1 +Line 8648: 0 +Line 8649: 0 +Line 8650: 0 +Line 8651: 1 +Line 8652: 0 +Line 8653: 0 +Line 8654: 0 +Line 8655: 0 +Line 8656: 0 +Line 8657: 0 +Line 8658: 0 +Line 8659: 0 +Line 8660: 0 +Line 8661: 0 +Line 8662: 0 +Line 8663: 0 +Line 8664: 1 +Line 8665: 0 +Line 8666: 1 +Line 8667: 1 +Line 8668: 0 +Line 8669: 1 +Line 8670: 1 +Line 8671: 0 +Line 8672: 0 +Line 8673: 1 +Line 8674: 0 +Line 8675: 0 +Line 8676: 0 +Line 8677: 0 +Line 8678: 1 +Line 8679: 0 +Line 8680: 1 +Line 8681: 0 +Line 8682: 0 +Line 8683: 0 +Line 8684: 0 +Line 8685: 0 +Line 8686: 1 +Line 8687: 0 +Line 8688: 0 +Line 8689: 0 +Line 8690: 0 +Line 8691: 0 +Line 8692: 0 +Line 8693: 0 +Line 8694: 0 +Line 8695: 0 +Line 8696: 1 +Line 8697: 1 +Line 8698: 0 +Line 8699: 0 +Line 8700: 0 +Line 8701: 1 +Line 8702: 0 +Line 8703: 1 +Line 8704: 0 +Line 8705: 1 +Line 8706: 0 +Line 8707: 0 +Line 8708: 0 +Line 8709: 0 +Line 8710: 0 +Line 8711: 1 +Line 8712: 1 +Line 8713: 1 +Line 8714: 1 +Line 8715: 0 +Line 8716: 1 +Line 8717: 0 +Line 8718: 1 +Line 8719: 0 +Line 8720: 0 +Line 8721: 0 +Line 8722: 0 +Line 8723: 0 +Line 8724: 0 +Line 8725: 0 +Line 8726: 0 +Line 8727: 0 +Line 8728: 1 +Line 8729: 1 +Line 8730: 0 +Line 8731: 1 +Line 8732: 0 +Line 8733: 0 +Line 8734: 1 +Line 8735: 0 +Line 8736: 0 +Line 8737: 1 +Line 8738: 0 +Line 8739: 0 +Line 8740: 0 +Line 8741: 0 +Line 8742: 0 +Line 8743: 1 +Line 8744: 0 +Line 8745: 1 +Line 8746: 0 +Line 8747: 0 +Line 8748: 0 +Line 8749: 1 +Line 8750: 1 +Line 8751: 1 +Line 8752: 0 +Line 8753: 0 +Line 8754: 0 +Line 8755: 0 +Line 8756: 0 +Line 8757: 0 +Line 8758: 0 +Line 8759: 0 +Line 8760: 1 +Line 8761: 1 +Line 8762: 1 +Line 8763: 0 +Line 8764: 0 +Line 8765: 0 +Line 8766: 0 +Line 8767: 0 +Line 8768: 0 +Line 8769: 1 +Line 8770: 0 +Line 8771: 0 +Line 8772: 0 +Line 8773: 0 +Line 8774: 0 +Line 8775: 0 +Line 8776: 1 +Line 8777: 0 +Line 8778: 0 +Line 8779: 1 +Line 8780: 1 +Line 8781: 0 +Line 8782: 1 +Line 8783: 1 +Line 8784: 0 +Line 8785: 0 +Line 8786: 0 +Line 8787: 0 +Line 8788: 0 +Line 8789: 0 +Line 8790: 0 +Line 8791: 0 +Line 8792: 1 +Line 8793: 1 +Line 8794: 1 +Line 8795: 0 +Line 8796: 1 +Line 8797: 1 +Line 8798: 0 +Line 8799: 1 +Line 8800: 0 +Line 8801: 0 +Line 8802: 1 +Line 8803: 1 +Line 8804: 1 +Line 8805: 1 +Line 8806: 1 +Line 8807: 1 +Line 8808: 1 +Line 8809: 1 +Line 8810: 1 +Line 8811: 0 +Line 8812: 0 +Line 8813: 1 +Line 8814: 0 +Line 8815: 0 +Line 8816: 0 +Line 8817: 0 +Line 8818: 0 +Line 8819: 0 +Line 8820: 0 +Line 8821: 0 +Line 8822: 0 +Line 8823: 0 +Line 8824: 1 +Line 8825: 1 +Line 8826: 1 +Line 8827: 1 +Line 8828: 1 +Line 8829: 0 +Line 8830: 1 +Line 8831: 0 +Line 8832: 0 +Line 8833: 0 +Line 8834: 1 +Line 8835: 1 +Line 8836: 1 +Line 8837: 1 +Line 8838: 1 +Line 8839: 1 +Line 8840: 0 +Line 8841: 0 +Line 8842: 1 +Line 8843: 0 +Line 8844: 0 +Line 8845: 1 +Line 8846: 0 +Line 8847: 0 +Line 8848: 0 +Line 8849: 0 +Line 8850: 0 +Line 8851: 0 +Line 8852: 0 +Line 8853: 0 +Line 8854: 0 +Line 8855: 1 +Line 8856: 0 +Line 8857: 0 +Line 8858: 0 +Line 8859: 0 +Line 8860: 0 +Line 8861: 1 +Line 8862: 1 +Line 8863: 1 +Line 8864: 0 +Line 8865: 0 +Line 8866: 1 +Line 8867: 1 +Line 8868: 1 +Line 8869: 1 +Line 8870: 1 +Line 8871: 0 +Line 8872: 0 +Line 8873: 1 +Line 8874: 0 +Line 8875: 1 +Line 8876: 1 +Line 8877: 0 +Line 8878: 1 +Line 8879: 1 +Line 8880: 0 +Line 8881: 0 +Line 8882: 0 +Line 8883: 0 +Line 8884: 0 +Line 8885: 0 +Line 8886: 0 +Line 8887: 1 +Line 8888: 0 +Line 8889: 0 +Line 8890: 0 +Line 8891: 1 +Line 8892: 0 +Line 8893: 0 +Line 8894: 1 +Line 8895: 1 +Line 8896: 0 +Line 8897: 0 +Line 8898: 1 +Line 8899: 1 +Line 8900: 1 +Line 8901: 1 +Line 8902: 0 +Line 8903: 1 +Line 8904: 1 +Line 8905: 0 +Line 8906: 0 +Line 8907: 0 +Line 8908: 1 +Line 8909: 0 +Line 8910: 0 +Line 8911: 1 +Line 8912: 0 +Line 8913: 0 +Line 8914: 0 +Line 8915: 0 +Line 8916: 0 +Line 8917: 0 +Line 8918: 0 +Line 8919: 1 +Line 8920: 0 +Line 8921: 0 +Line 8922: 0 +Line 8923: 1 +Line 8924: 1 +Line 8925: 1 +Line 8926: 1 +Line 8927: 1 +Line 8928: 0 +Line 8929: 0 +Line 8930: 1 +Line 8931: 1 +Line 8932: 1 +Line 8933: 1 +Line 8934: 0 +Line 8935: 0 +Line 8936: 1 +Line 8937: 0 +Line 8938: 1 +Line 8939: 0 +Line 8940: 1 +Line 8941: 1 +Line 8942: 0 +Line 8943: 1 +Line 8944: 0 +Line 8945: 0 +Line 8946: 0 +Line 8947: 0 +Line 8948: 0 +Line 8949: 0 +Line 8950: 0 +Line 8951: 1 +Line 8952: 0 +Line 8953: 0 +Line 8954: 1 +Line 8955: 0 +Line 8956: 1 +Line 8957: 0 +Line 8958: 1 +Line 8959: 1 +Line 8960: 0 +Line 8961: 0 +Line 8962: 1 +Line 8963: 1 +Line 8964: 1 +Line 8965: 0 +Line 8966: 1 +Line 8967: 1 +Line 8968: 1 +Line 8969: 1 +Line 8970: 0 +Line 8971: 0 +Line 8972: 1 +Line 8973: 0 +Line 8974: 1 +Line 8975: 0 +Line 8976: 0 +Line 8977: 0 +Line 8978: 0 +Line 8979: 0 +Line 8980: 0 +Line 8981: 0 +Line 8982: 0 +Line 8983: 1 +Line 8984: 0 +Line 8985: 0 +Line 8986: 1 +Line 8987: 1 +Line 8988: 0 +Line 8989: 1 +Line 8990: 1 +Line 8991: 0 +Line 8992: 0 +Line 8993: 0 +Line 8994: 1 +Line 8995: 1 +Line 8996: 1 +Line 8997: 0 +Line 8998: 1 +Line 8999: 0 +Line 9000: 1 +Line 9001: 1 +Line 9002: 0 +Line 9003: 1 +Line 9004: 1 +Line 9005: 1 +Line 9006: 1 +Line 9007: 0 +Line 9008: 0 +Line 9009: 0 +Line 9010: 0 +Line 9011: 0 +Line 9012: 0 +Line 9013: 0 +Line 9014: 0 +Line 9015: 1 +Line 9016: 0 +Line 9017: 1 +Line 9018: 0 +Line 9019: 0 +Line 9020: 0 +Line 9021: 0 +Line 9022: 0 +Line 9023: 1 +Line 9024: 0 +Line 9025: 0 +Line 9026: 1 +Line 9027: 1 +Line 9028: 1 +Line 9029: 0 +Line 9030: 0 +Line 9031: 1 +Line 9032: 1 +Line 9033: 1 +Line 9034: 1 +Line 9035: 0 +Line 9036: 1 +Line 9037: 0 +Line 9038: 1 +Line 9039: 0 +Line 9040: 0 +Line 9041: 0 +Line 9042: 0 +Line 9043: 0 +Line 9044: 0 +Line 9045: 0 +Line 9046: 0 +Line 9047: 1 +Line 9048: 0 +Line 9049: 1 +Line 9050: 0 +Line 9051: 0 +Line 9052: 1 +Line 9053: 0 +Line 9054: 1 +Line 9055: 1 +Line 9056: 0 +Line 9057: 0 +Line 9058: 1 +Line 9059: 1 +Line 9060: 1 +Line 9061: 0 +Line 9062: 0 +Line 9063: 0 +Line 9064: 1 +Line 9065: 1 +Line 9066: 1 +Line 9067: 0 +Line 9068: 1 +Line 9069: 1 +Line 9070: 1 +Line 9071: 1 +Line 9072: 0 +Line 9073: 0 +Line 9074: 0 +Line 9075: 0 +Line 9076: 0 +Line 9077: 0 +Line 9078: 0 +Line 9079: 1 +Line 9080: 0 +Line 9081: 1 +Line 9082: 0 +Line 9083: 1 +Line 9084: 0 +Line 9085: 1 +Line 9086: 0 +Line 9087: 1 +Line 9088: 0 +Line 9089: 0 +Line 9090: 1 +Line 9091: 1 +Line 9092: 0 +Line 9093: 1 +Line 9094: 1 +Line 9095: 1 +Line 9096: 1 +Line 9097: 1 +Line 9098: 1 +Line 9099: 0 +Line 9100: 1 +Line 9101: 1 +Line 9102: 0 +Line 9103: 0 +Line 9104: 0 +Line 9105: 0 +Line 9106: 0 +Line 9107: 0 +Line 9108: 0 +Line 9109: 0 +Line 9110: 0 +Line 9111: 1 +Line 9112: 0 +Line 9113: 1 +Line 9114: 0 +Line 9115: 1 +Line 9116: 1 +Line 9117: 1 +Line 9118: 1 +Line 9119: 1 +Line 9120: 0 +Line 9121: 0 +Line 9122: 1 +Line 9123: 1 +Line 9124: 0 +Line 9125: 1 +Line 9126: 1 +Line 9127: 0 +Line 9128: 1 +Line 9129: 1 +Line 9130: 1 +Line 9131: 0 +Line 9132: 0 +Line 9133: 0 +Line 9134: 1 +Line 9135: 0 +Line 9136: 0 +Line 9137: 0 +Line 9138: 0 +Line 9139: 0 +Line 9140: 0 +Line 9141: 0 +Line 9142: 0 +Line 9143: 1 +Line 9144: 0 +Line 9145: 1 +Line 9146: 1 +Line 9147: 0 +Line 9148: 1 +Line 9149: 0 +Line 9150: 0 +Line 9151: 0 +Line 9152: 0 +Line 9153: 0 +Line 9154: 1 +Line 9155: 1 +Line 9156: 0 +Line 9157: 1 +Line 9158: 0 +Line 9159: 1 +Line 9160: 1 +Line 9161: 1 +Line 9162: 0 +Line 9163: 1 +Line 9164: 0 +Line 9165: 0 +Line 9166: 1 +Line 9167: 0 +Line 9168: 0 +Line 9169: 0 +Line 9170: 0 +Line 9171: 0 +Line 9172: 0 +Line 9173: 0 +Line 9174: 0 +Line 9175: 1 +Line 9176: 0 +Line 9177: 1 +Line 9178: 1 +Line 9179: 1 +Line 9180: 0 +Line 9181: 0 +Line 9182: 0 +Line 9183: 1 +Line 9184: 0 +Line 9185: 0 +Line 9186: 1 +Line 9187: 1 +Line 9188: 0 +Line 9189: 1 +Line 9190: 0 +Line 9191: 0 +Line 9192: 1 +Line 9193: 0 +Line 9194: 1 +Line 9195: 1 +Line 9196: 1 +Line 9197: 0 +Line 9198: 1 +Line 9199: 1 +Line 9200: 0 +Line 9201: 0 +Line 9202: 0 +Line 9203: 0 +Line 9204: 0 +Line 9205: 0 +Line 9206: 0 +Line 9207: 1 +Line 9208: 0 +Line 9209: 1 +Line 9210: 1 +Line 9211: 1 +Line 9212: 1 +Line 9213: 0 +Line 9214: 0 +Line 9215: 1 +Line 9216: 0 +Line 9217: 0 +Line 9218: 1 +Line 9219: 1 +Line 9220: 0 +Line 9221: 0 +Line 9222: 1 +Line 9223: 1 +Line 9224: 1 +Line 9225: 0 +Line 9226: 0 +Line 9227: 1 +Line 9228: 1 +Line 9229: 1 +Line 9230: 1 +Line 9231: 1 +Line 9232: 0 +Line 9233: 0 +Line 9234: 0 +Line 9235: 0 +Line 9236: 0 +Line 9237: 0 +Line 9238: 0 +Line 9239: 1 +Line 9240: 1 +Line 9241: 0 +Line 9242: 0 +Line 9243: 0 +Line 9244: 0 +Line 9245: 0 +Line 9246: 0 +Line 9247: 0 +Line 9248: 0 +Line 9249: 0 +Line 9250: 1 +Line 9251: 1 +Line 9252: 0 +Line 9253: 0 +Line 9254: 1 +Line 9255: 0 +Line 9256: 0 +Line 9257: 1 +Line 9258: 1 +Line 9259: 1 +Line 9260: 1 +Line 9261: 1 +Line 9262: 0 +Line 9263: 1 +Line 9264: 0 +Line 9265: 0 +Line 9266: 0 +Line 9267: 0 +Line 9268: 0 +Line 9269: 0 +Line 9270: 0 +Line 9271: 1 +Line 9272: 1 +Line 9273: 0 +Line 9274: 0 +Line 9275: 0 +Line 9276: 0 +Line 9277: 1 +Line 9278: 1 +Line 9279: 1 +Line 9280: 0 +Line 9281: 0 +Line 9282: 1 +Line 9283: 1 +Line 9284: 0 +Line 9285: 0 +Line 9286: 0 +Line 9287: 1 +Line 9288: 0 +Line 9289: 1 +Line 9290: 0 +Line 9291: 1 +Line 9292: 0 +Line 9293: 1 +Line 9294: 1 +Line 9295: 0 +Line 9296: 0 +Line 9297: 0 +Line 9298: 0 +Line 9299: 0 +Line 9300: 0 +Line 9301: 0 +Line 9302: 0 +Line 9303: 1 +Line 9304: 1 +Line 9305: 0 +Line 9306: 0 +Line 9307: 0 +Line 9308: 1 +Line 9309: 1 +Line 9310: 1 +Line 9311: 0 +Line 9312: 0 +Line 9313: 0 +Line 9314: 1 +Line 9315: 1 +Line 9316: 0 +Line 9317: 0 +Line 9318: 0 +Line 9319: 0 +Line 9320: 0 +Line 9321: 0 +Line 9322: 1 +Line 9323: 0 +Line 9324: 1 +Line 9325: 0 +Line 9326: 1 +Line 9327: 1 +Line 9328: 0 +Line 9329: 0 +Line 9330: 0 +Line 9331: 0 +Line 9332: 0 +Line 9333: 0 +Line 9334: 0 +Line 9335: 1 +Line 9336: 1 +Line 9337: 0 +Line 9338: 0 +Line 9339: 1 +Line 9340: 0 +Line 9341: 1 +Line 9342: 0 +Line 9343: 0 +Line 9344: 0 +Line 9345: 0 +Line 9346: 1 +Line 9347: 0 +Line 9348: 1 +Line 9349: 1 +Line 9350: 1 +Line 9351: 0 +Line 9352: 1 +Line 9353: 1 +Line 9354: 1 +Line 9355: 1 +Line 9356: 1 +Line 9357: 0 +Line 9358: 1 +Line 9359: 1 +Line 9360: 0 +Line 9361: 0 +Line 9362: 0 +Line 9363: 0 +Line 9364: 0 +Line 9365: 0 +Line 9366: 0 +Line 9367: 1 +Line 9368: 1 +Line 9369: 0 +Line 9370: 0 +Line 9371: 1 +Line 9372: 1 +Line 9373: 0 +Line 9374: 1 +Line 9375: 0 +Line 9376: 0 +Line 9377: 0 +Line 9378: 1 +Line 9379: 0 +Line 9380: 1 +Line 9381: 1 +Line 9382: 0 +Line 9383: 1 +Line 9384: 1 +Line 9385: 1 +Line 9386: 0 +Line 9387: 0 +Line 9388: 0 +Line 9389: 1 +Line 9390: 1 +Line 9391: 1 +Line 9392: 0 +Line 9393: 0 +Line 9394: 0 +Line 9395: 0 +Line 9396: 0 +Line 9397: 0 +Line 9398: 0 +Line 9399: 1 +Line 9400: 1 +Line 9401: 0 +Line 9402: 0 +Line 9403: 1 +Line 9404: 1 +Line 9405: 1 +Line 9406: 1 +Line 9407: 1 +Line 9408: 0 +Line 9409: 0 +Line 9410: 1 +Line 9411: 0 +Line 9412: 1 +Line 9413: 1 +Line 9414: 0 +Line 9415: 0 +Line 9416: 1 +Line 9417: 0 +Line 9418: 0 +Line 9419: 0 +Line 9420: 1 +Line 9421: 1 +Line 9422: 1 +Line 9423: 1 +Line 9424: 0 +Line 9425: 0 +Line 9426: 0 +Line 9427: 0 +Line 9428: 0 +Line 9429: 0 +Line 9430: 0 +Line 9431: 1 +Line 9432: 1 +Line 9433: 0 +Line 9434: 1 +Line 9435: 0 +Line 9436: 0 +Line 9437: 0 +Line 9438: 1 +Line 9439: 1 +Line 9440: 0 +Line 9441: 0 +Line 9442: 1 +Line 9443: 0 +Line 9444: 1 +Line 9445: 0 +Line 9446: 1 +Line 9447: 1 +Line 9448: 0 +Line 9449: 1 +Line 9450: 0 +Line 9451: 1 +Line 9452: 0 +Line 9453: 1 +Line 9454: 0 +Line 9455: 1 +Line 9456: 0 +Line 9457: 0 +Line 9458: 0 +Line 9459: 0 +Line 9460: 0 +Line 9461: 0 +Line 9462: 0 +Line 9463: 1 +Line 9464: 1 +Line 9465: 0 +Line 9466: 1 +Line 9467: 0 +Line 9468: 0 +Line 9469: 1 +Line 9470: 1 +Line 9471: 1 +Line 9472: 0 +Line 9473: 0 +Line 9474: 1 +Line 9475: 0 +Line 9476: 1 +Line 9477: 0 +Line 9478: 1 +Line 9479: 0 +Line 9480: 0 +Line 9481: 0 +Line 9482: 0 +Line 9483: 1 +Line 9484: 0 +Line 9485: 1 +Line 9486: 1 +Line 9487: 1 +Line 9488: 0 +Line 9489: 0 +Line 9490: 0 +Line 9491: 0 +Line 9492: 0 +Line 9493: 0 +Line 9494: 0 +Line 9495: 1 +Line 9496: 1 +Line 9497: 0 +Line 9498: 1 +Line 9499: 0 +Line 9500: 1 +Line 9501: 0 +Line 9502: 1 +Line 9503: 0 +Line 9504: 0 +Line 9505: 0 +Line 9506: 1 +Line 9507: 0 +Line 9508: 1 +Line 9509: 0 +Line 9510: 0 +Line 9511: 0 +Line 9512: 1 +Line 9513: 1 +Line 9514: 0 +Line 9515: 1 +Line 9516: 1 +Line 9517: 0 +Line 9518: 0 +Line 9519: 0 +Line 9520: 0 +Line 9521: 0 +Line 9522: 0 +Line 9523: 0 +Line 9524: 0 +Line 9525: 0 +Line 9526: 0 +Line 9527: 1 +Line 9528: 1 +Line 9529: 0 +Line 9530: 1 +Line 9531: 0 +Line 9532: 1 +Line 9533: 1 +Line 9534: 0 +Line 9535: 1 +Line 9536: 0 +Line 9537: 0 +Line 9538: 1 +Line 9539: 0 +Line 9540: 0 +Line 9541: 1 +Line 9542: 1 +Line 9543: 1 +Line 9544: 1 +Line 9545: 0 +Line 9546: 0 +Line 9547: 1 +Line 9548: 0 +Line 9549: 1 +Line 9550: 1 +Line 9551: 0 +Line 9552: 0 +Line 9553: 0 +Line 9554: 0 +Line 9555: 0 +Line 9556: 0 +Line 9557: 0 +Line 9558: 0 +Line 9559: 1 +Line 9560: 1 +Line 9561: 0 +Line 9562: 1 +Line 9563: 1 +Line 9564: 0 +Line 9565: 0 +Line 9566: 0 +Line 9567: 0 +Line 9568: 0 +Line 9569: 0 +Line 9570: 1 +Line 9571: 0 +Line 9572: 0 +Line 9573: 1 +Line 9574: 1 +Line 9575: 0 +Line 9576: 0 +Line 9577: 1 +Line 9578: 0 +Line 9579: 1 +Line 9580: 0 +Line 9581: 0 +Line 9582: 1 +Line 9583: 1 +Line 9584: 0 +Line 9585: 0 +Line 9586: 0 +Line 9587: 0 +Line 9588: 0 +Line 9589: 0 +Line 9590: 0 +Line 9591: 1 +Line 9592: 1 +Line 9593: 0 +Line 9594: 1 +Line 9595: 1 +Line 9596: 0 +Line 9597: 0 +Line 9598: 0 +Line 9599: 1 +Line 9600: 0 +Line 9601: 0 +Line 9602: 1 +Line 9603: 0 +Line 9604: 0 +Line 9605: 1 +Line 9606: 0 +Line 9607: 1 +Line 9608: 0 +Line 9609: 0 +Line 9610: 0 +Line 9611: 0 +Line 9612: 1 +Line 9613: 1 +Line 9614: 1 +Line 9615: 1 +Line 9616: 0 +Line 9617: 0 +Line 9618: 0 +Line 9619: 0 +Line 9620: 0 +Line 9621: 0 +Line 9622: 0 +Line 9623: 1 +Line 9624: 1 +Line 9625: 0 +Line 9626: 1 +Line 9627: 1 +Line 9628: 0 +Line 9629: 0 +Line 9630: 1 +Line 9631: 0 +Line 9632: 0 +Line 9633: 0 +Line 9634: 1 +Line 9635: 0 +Line 9636: 0 +Line 9637: 0 +Line 9638: 1 +Line 9639: 1 +Line 9640: 1 +Line 9641: 1 +Line 9642: 0 +Line 9643: 0 +Line 9644: 1 +Line 9645: 0 +Line 9646: 1 +Line 9647: 0 +Line 9648: 0 +Line 9649: 0 +Line 9650: 0 +Line 9651: 0 +Line 9652: 0 +Line 9653: 0 +Line 9654: 0 +Line 9655: 1 +Line 9656: 1 +Line 9657: 0 +Line 9658: 1 +Line 9659: 1 +Line 9660: 0 +Line 9661: 0 +Line 9662: 1 +Line 9663: 1 +Line 9664: 0 +Line 9665: 0 +Line 9666: 1 +Line 9667: 0 +Line 9668: 0 +Line 9669: 0 +Line 9670: 1 +Line 9671: 0 +Line 9672: 1 +Line 9673: 0 +Line 9674: 0 +Line 9675: 0 +Line 9676: 0 +Line 9677: 1 +Line 9678: 0 +Line 9679: 1 +Line 9680: 0 +Line 9681: 0 +Line 9682: 0 +Line 9683: 0 +Line 9684: 0 +Line 9685: 0 +Line 9686: 0 +Line 9687: 1 +Line 9688: 1 +Line 9689: 0 +Line 9690: 1 +Line 9691: 1 +Line 9692: 0 +Line 9693: 0 +Line 9694: 1 +Line 9695: 1 +Line 9696: 0 +Line 9697: 0 +Line 9698: 1 +Line 9699: 0 +Line 9700: 0 +Line 9701: 0 +Line 9702: 0 +Line 9703: 1 +Line 9704: 0 +Line 9705: 1 +Line 9706: 0 +Line 9707: 0 +Line 9708: 0 +Line 9709: 0 +Line 9710: 0 +Line 9711: 0 +Line 9712: 0 +Line 9713: 0 +Line 9714: 0 +Line 9715: 0 +Line 9716: 0 +Line 9717: 0 +Line 9718: 0 +Line 9719: 1 +Line 9720: 1 +Line 9721: 0 +Line 9722: 1 +Line 9723: 1 +Line 9724: 0 +Line 9725: 0 +Line 9726: 1 +Line 9727: 0 +Line 9728: 0 +Line 9729: 0 +Line 9730: 0 +Line 9731: 1 +Line 9732: 1 +Line 9733: 1 +Line 9734: 1 +Line 9735: 1 +Line 9736: 1 +Line 9737: 1 +Line 9738: 1 +Line 9739: 1 +Line 9740: 1 +Line 9741: 1 +Line 9742: 0 +Line 9743: 0 +Line 9744: 0 +Line 9745: 0 +Line 9746: 0 +Line 9747: 0 +Line 9748: 0 +Line 9749: 0 +Line 9750: 0 +Line 9751: 1 +Line 9752: 1 +Line 9753: 0 +Line 9754: 1 +Line 9755: 1 +Line 9756: 0 +Line 9757: 0 +Line 9758: 0 +Line 9759: 1 +Line 9760: 0 +Line 9761: 0 +Line 9762: 0 +Line 9763: 1 +Line 9764: 1 +Line 9765: 1 +Line 9766: 1 +Line 9767: 0 +Line 9768: 1 +Line 9769: 0 +Line 9770: 1 +Line 9771: 1 +Line 9772: 1 +Line 9773: 0 +Line 9774: 0 +Line 9775: 1 +Line 9776: 0 +Line 9777: 0 +Line 9778: 0 +Line 9779: 0 +Line 9780: 0 +Line 9781: 0 +Line 9782: 0 +Line 9783: 1 +Line 9784: 1 +Line 9785: 0 +Line 9786: 1 +Line 9787: 1 +Line 9788: 0 +Line 9789: 0 +Line 9790: 0 +Line 9791: 0 +Line 9792: 0 +Line 9793: 0 +Line 9794: 0 +Line 9795: 1 +Line 9796: 1 +Line 9797: 1 +Line 9798: 0 +Line 9799: 1 +Line 9800: 0 +Line 9801: 1 +Line 9802: 1 +Line 9803: 1 +Line 9804: 0 +Line 9805: 1 +Line 9806: 1 +Line 9807: 1 +Line 9808: 0 +Line 9809: 0 +Line 9810: 0 +Line 9811: 0 +Line 9812: 0 +Line 9813: 0 +Line 9814: 0 +Line 9815: 1 +Line 9816: 1 +Line 9817: 0 +Line 9818: 1 +Line 9819: 0 +Line 9820: 1 +Line 9821: 1 +Line 9822: 0 +Line 9823: 1 +Line 9824: 0 +Line 9825: 0 +Line 9826: 0 +Line 9827: 1 +Line 9828: 1 +Line 9829: 1 +Line 9830: 0 +Line 9831: 0 +Line 9832: 0 +Line 9833: 0 +Line 9834: 1 +Line 9835: 1 +Line 9836: 1 +Line 9837: 0 +Line 9838: 0 +Line 9839: 0 +Line 9840: 0 +Line 9841: 0 +Line 9842: 0 +Line 9843: 0 +Line 9844: 0 +Line 9845: 0 +Line 9846: 0 +Line 9847: 1 +Line 9848: 1 +Line 9849: 0 +Line 9850: 1 +Line 9851: 0 +Line 9852: 1 +Line 9853: 0 +Line 9854: 1 +Line 9855: 0 +Line 9856: 0 +Line 9857: 0 +Line 9858: 0 +Line 9859: 1 +Line 9860: 1 +Line 9861: 0 +Line 9862: 1 +Line 9863: 0 +Line 9864: 1 +Line 9865: 1 +Line 9866: 1 +Line 9867: 1 +Line 9868: 1 +Line 9869: 0 +Line 9870: 1 +Line 9871: 0 +Line 9872: 0 +Line 9873: 0 +Line 9874: 0 +Line 9875: 0 +Line 9876: 0 +Line 9877: 0 +Line 9878: 0 +Line 9879: 1 +Line 9880: 1 +Line 9881: 0 +Line 9882: 1 +Line 9883: 0 +Line 9884: 0 +Line 9885: 1 +Line 9886: 1 +Line 9887: 1 +Line 9888: 0 +Line 9889: 0 +Line 9890: 0 +Line 9891: 1 +Line 9892: 1 +Line 9893: 0 +Line 9894: 0 +Line 9895: 1 +Line 9896: 1 +Line 9897: 1 +Line 9898: 0 +Line 9899: 0 +Line 9900: 0 +Line 9901: 0 +Line 9902: 0 +Line 9903: 0 +Line 9904: 0 +Line 9905: 0 +Line 9906: 0 +Line 9907: 0 +Line 9908: 0 +Line 9909: 0 +Line 9910: 0 +Line 9911: 1 +Line 9912: 1 +Line 9913: 0 +Line 9914: 1 +Line 9915: 0 +Line 9916: 0 +Line 9917: 0 +Line 9918: 1 +Line 9919: 1 +Line 9920: 0 +Line 9921: 0 +Line 9922: 0 +Line 9923: 1 +Line 9924: 1 +Line 9925: 0 +Line 9926: 0 +Line 9927: 0 +Line 9928: 1 +Line 9929: 0 +Line 9930: 0 +Line 9931: 0 +Line 9932: 1 +Line 9933: 0 +Line 9934: 0 +Line 9935: 0 +Line 9936: 0 +Line 9937: 0 +Line 9938: 0 +Line 9939: 0 +Line 9940: 0 +Line 9941: 0 +Line 9942: 0 +Line 9943: 1 +Line 9944: 1 +Line 9945: 0 +Line 9946: 0 +Line 9947: 1 +Line 9948: 1 +Line 9949: 1 +Line 9950: 1 +Line 9951: 1 +Line 9952: 0 +Line 9953: 0 +Line 9954: 0 +Line 9955: 1 +Line 9956: 0 +Line 9957: 1 +Line 9958: 1 +Line 9959: 1 +Line 9960: 0 +Line 9961: 1 +Line 9962: 0 +Line 9963: 1 +Line 9964: 0 +Line 9965: 1 +Line 9966: 0 +Line 9967: 0 +Line 9968: 0 +Line 9969: 0 +Line 9970: 0 +Line 9971: 0 +Line 9972: 0 +Line 9973: 0 +Line 9974: 0 +Line 9975: 1 +Line 9976: 1 +Line 9977: 0 +Line 9978: 0 +Line 9979: 1 +Line 9980: 1 +Line 9981: 0 +Line 9982: 1 +Line 9983: 0 +Line 9984: 0 +Line 9985: 0 +Line 9986: 0 +Line 9987: 1 +Line 9988: 0 +Line 9989: 1 +Line 9990: 1 +Line 9991: 0 +Line 9992: 0 +Line 9993: 0 +Line 9994: 1 +Line 9995: 0 +Line 9996: 0 +Line 9997: 1 +Line 9998: 0 +Line 9999: 0 +Line 10000: 0 +Line 10001: 0 +Line 10002: 0 +Line 10003: 0 +Line 10004: 0 +Line 10005: 0 +Line 10006: 0 +Line 10007: 1 +Line 10008: 1 +Line 10009: 0 +Line 10010: 0 +Line 10011: 1 +Line 10012: 0 +Line 10013: 1 +Line 10014: 0 +Line 10015: 0 +Line 10016: 0 +Line 10017: 0 +Line 10018: 0 +Line 10019: 1 +Line 10020: 0 +Line 10021: 1 +Line 10022: 0 +Line 10023: 0 +Line 10024: 1 +Line 10025: 1 +Line 10026: 1 +Line 10027: 1 +Line 10028: 1 +Line 10029: 0 +Line 10030: 0 +Line 10031: 1 +Line 10032: 0 +Line 10033: 0 +Line 10034: 0 +Line 10035: 0 +Line 10036: 0 +Line 10037: 0 +Line 10038: 0 +Line 10039: 1 +Line 10040: 1 +Line 10041: 0 +Line 10042: 0 +Line 10043: 0 +Line 10044: 1 +Line 10045: 1 +Line 10046: 1 +Line 10047: 0 +Line 10048: 0 +Line 10049: 0 +Line 10050: 0 +Line 10051: 1 +Line 10052: 0 +Line 10053: 0 +Line 10054: 1 +Line 10055: 1 +Line 10056: 1 +Line 10057: 1 +Line 10058: 0 +Line 10059: 1 +Line 10060: 0 +Line 10061: 0 +Line 10062: 1 +Line 10063: 0 +Line 10064: 0 +Line 10065: 0 +Line 10066: 0 +Line 10067: 0 +Line 10068: 0 +Line 10069: 0 +Line 10070: 0 +Line 10071: 1 +Line 10072: 1 +Line 10073: 0 +Line 10074: 0 +Line 10075: 0 +Line 10076: 0 +Line 10077: 1 +Line 10078: 1 +Line 10079: 1 +Line 10080: 0 +Line 10081: 0 +Line 10082: 0 +Line 10083: 1 +Line 10084: 0 +Line 10085: 0 +Line 10086: 1 +Line 10087: 0 +Line 10088: 1 +Line 10089: 0 +Line 10090: 1 +Line 10091: 1 +Line 10092: 0 +Line 10093: 0 +Line 10094: 0 +Line 10095: 0 +Line 10096: 0 +Line 10097: 0 +Line 10098: 0 +Line 10099: 0 +Line 10100: 0 +Line 10101: 0 +Line 10102: 0 +Line 10103: 1 +Line 10104: 1 +Line 10105: 0 +Line 10106: 0 +Line 10107: 0 +Line 10108: 0 +Line 10109: 0 +Line 10110: 0 +Line 10111: 0 +Line 10112: 0 +Line 10113: 0 +Line 10114: 0 +Line 10115: 1 +Line 10116: 0 +Line 10117: 0 +Line 10118: 0 +Line 10119: 1 +Line 10120: 1 +Line 10121: 0 +Line 10122: 0 +Line 10123: 1 +Line 10124: 0 +Line 10125: 0 +Line 10126: 1 +Line 10127: 1 +Line 10128: 0 +Line 10129: 0 +Line 10130: 0 +Line 10131: 0 +Line 10132: 0 +Line 10133: 0 +Line 10134: 0 +Line 10135: 1 +Line 10136: 0 +Line 10137: 1 +Line 10138: 1 +Line 10139: 1 +Line 10140: 1 +Line 10141: 0 +Line 10142: 0 +Line 10143: 1 +Line 10144: 0 +Line 10145: 0 +Line 10146: 0 +Line 10147: 1 +Line 10148: 0 +Line 10149: 0 +Line 10150: 0 +Line 10151: 0 +Line 10152: 0 +Line 10153: 1 +Line 10154: 1 +Line 10155: 1 +Line 10156: 1 +Line 10157: 1 +Line 10158: 0 +Line 10159: 1 +Line 10160: 0 +Line 10161: 0 +Line 10162: 0 +Line 10163: 0 +Line 10164: 0 +Line 10165: 0 +Line 10166: 0 +Line 10167: 1 +Line 10168: 0 +Line 10169: 1 +Line 10170: 1 +Line 10171: 1 +Line 10172: 0 +Line 10173: 0 +Line 10174: 0 +Line 10175: 1 +Line 10176: 0 +Line 10177: 0 +Line 10178: 0 +Line 10179: 0 +Line 10180: 1 +Line 10181: 1 +Line 10182: 1 +Line 10183: 1 +Line 10184: 0 +Line 10185: 1 +Line 10186: 1 +Line 10187: 0 +Line 10188: 1 +Line 10189: 1 +Line 10190: 0 +Line 10191: 1 +Line 10192: 0 +Line 10193: 0 +Line 10194: 0 +Line 10195: 0 +Line 10196: 0 +Line 10197: 0 +Line 10198: 0 +Line 10199: 1 +Line 10200: 0 +Line 10201: 1 +Line 10202: 1 +Line 10203: 0 +Line 10204: 1 +Line 10205: 0 +Line 10206: 0 +Line 10207: 0 +Line 10208: 0 +Line 10209: 0 +Line 10210: 0 +Line 10211: 0 +Line 10212: 1 +Line 10213: 1 +Line 10214: 1 +Line 10215: 0 +Line 10216: 0 +Line 10217: 1 +Line 10218: 1 +Line 10219: 0 +Line 10220: 0 +Line 10221: 0 +Line 10222: 1 +Line 10223: 1 +Line 10224: 0 +Line 10225: 0 +Line 10226: 0 +Line 10227: 0 +Line 10228: 0 +Line 10229: 0 +Line 10230: 0 +Line 10231: 1 +Line 10232: 0 +Line 10233: 1 +Line 10234: 0 +Line 10235: 1 +Line 10236: 1 +Line 10237: 1 +Line 10238: 1 +Line 10239: 1 +Line 10240: 0 +Line 10241: 0 +Line 10242: 0 +Line 10243: 0 +Line 10244: 1 +Line 10245: 1 +Line 10246: 0 +Line 10247: 1 +Line 10248: 0 +Line 10249: 1 +Line 10250: 1 +Line 10251: 0 +Line 10252: 0 +Line 10253: 0 +Line 10254: 0 +Line 10255: 0 +Line 10256: 0 +Line 10257: 0 +Line 10258: 0 +Line 10259: 0 +Line 10260: 0 +Line 10261: 0 +Line 10262: 0 +Line 10263: 1 +Line 10264: 0 +Line 10265: 1 +Line 10266: 0 +Line 10267: 1 +Line 10268: 0 +Line 10269: 1 +Line 10270: 0 +Line 10271: 1 +Line 10272: 0 +Line 10273: 0 +Line 10274: 0 +Line 10275: 0 +Line 10276: 1 +Line 10277: 1 +Line 10278: 0 +Line 10279: 0 +Line 10280: 0 +Line 10281: 1 +Line 10282: 1 +Line 10283: 0 +Line 10284: 0 +Line 10285: 1 +Line 10286: 0 +Line 10287: 1 +Line 10288: 0 +Line 10289: 0 +Line 10290: 0 +Line 10291: 0 +Line 10292: 0 +Line 10293: 0 +Line 10294: 0 +Line 10295: 1 +Line 10296: 0 +Line 10297: 1 +Line 10298: 0 +Line 10299: 0 +Line 10300: 1 +Line 10301: 0 +Line 10302: 1 +Line 10303: 1 +Line 10304: 0 +Line 10305: 0 +Line 10306: 0 +Line 10307: 0 +Line 10308: 1 +Line 10309: 0 +Line 10310: 1 +Line 10311: 1 +Line 10312: 0 +Line 10313: 1 +Line 10314: 1 +Line 10315: 1 +Line 10316: 0 +Line 10317: 0 +Line 10318: 0 +Line 10319: 1 +Line 10320: 0 +Line 10321: 0 +Line 10322: 0 +Line 10323: 0 +Line 10324: 0 +Line 10325: 0 +Line 10326: 0 +Line 10327: 1 +Line 10328: 0 +Line 10329: 1 +Line 10330: 0 +Line 10331: 0 +Line 10332: 0 +Line 10333: 0 +Line 10334: 0 +Line 10335: 1 +Line 10336: 0 +Line 10337: 0 +Line 10338: 0 +Line 10339: 0 +Line 10340: 1 +Line 10341: 0 +Line 10342: 1 +Line 10343: 0 +Line 10344: 1 +Line 10345: 0 +Line 10346: 0 +Line 10347: 0 +Line 10348: 0 +Line 10349: 1 +Line 10350: 0 +Line 10351: 1 +Line 10352: 0 +Line 10353: 0 +Line 10354: 0 +Line 10355: 0 +Line 10356: 0 +Line 10357: 0 +Line 10358: 0 +Line 10359: 1 +Line 10360: 0 +Line 10361: 0 +Line 10362: 1 +Line 10363: 1 +Line 10364: 0 +Line 10365: 1 +Line 10366: 1 +Line 10367: 0 +Line 10368: 0 +Line 10369: 0 +Line 10370: 0 +Line 10371: 0 +Line 10372: 1 +Line 10373: 0 +Line 10374: 0 +Line 10375: 1 +Line 10376: 1 +Line 10377: 0 +Line 10378: 1 +Line 10379: 0 +Line 10380: 0 +Line 10381: 0 +Line 10382: 1 +Line 10383: 0 +Line 10384: 0 +Line 10385: 0 +Line 10386: 0 +Line 10387: 0 +Line 10388: 0 +Line 10389: 0 +Line 10390: 0 +Line 10391: 1 +Line 10392: 0 +Line 10393: 0 +Line 10394: 1 +Line 10395: 0 +Line 10396: 1 +Line 10397: 0 +Line 10398: 1 +Line 10399: 1 +Line 10400: 0 +Line 10401: 0 +Line 10402: 0 +Line 10403: 0 +Line 10404: 1 +Line 10405: 0 +Line 10406: 0 +Line 10407: 0 +Line 10408: 1 +Line 10409: 1 +Line 10410: 0 +Line 10411: 0 +Line 10412: 0 +Line 10413: 1 +Line 10414: 1 +Line 10415: 0 +Line 10416: 0 +Line 10417: 0 +Line 10418: 0 +Line 10419: 0 +Line 10420: 0 +Line 10421: 0 +Line 10422: 0 +Line 10423: 1 +Line 10424: 0 +Line 10425: 0 +Line 10426: 0 +Line 10427: 1 +Line 10428: 1 +Line 10429: 1 +Line 10430: 1 +Line 10431: 1 +Line 10432: 0 +Line 10433: 0 +Line 10434: 0 +Line 10435: 0 +Line 10436: 0 +Line 10437: 1 +Line 10438: 1 +Line 10439: 1 +Line 10440: 1 +Line 10441: 1 +Line 10442: 1 +Line 10443: 1 +Line 10444: 0 +Line 10445: 1 +Line 10446: 0 +Line 10447: 0 +Line 10448: 0 +Line 10449: 0 +Line 10450: 0 +Line 10451: 0 +Line 10452: 0 +Line 10453: 0 +Line 10454: 0 +Line 10455: 1 +Line 10456: 0 +Line 10457: 0 +Line 10458: 0 +Line 10459: 1 +Line 10460: 0 +Line 10461: 0 +Line 10462: 1 +Line 10463: 1 +Line 10464: 0 +Line 10465: 0 +Line 10466: 0 +Line 10467: 0 +Line 10468: 0 +Line 10469: 1 +Line 10470: 1 +Line 10471: 1 +Line 10472: 0 +Line 10473: 0 +Line 10474: 1 +Line 10475: 0 +Line 10476: 1 +Line 10477: 0 +Line 10478: 1 +Line 10479: 1 +Line 10480: 0 +Line 10481: 0 +Line 10482: 0 +Line 10483: 0 +Line 10484: 0 +Line 10485: 0 +Line 10486: 0 +Line 10487: 1 +Line 10488: 0 +Line 10489: 0 +Line 10490: 0 +Line 10491: 0 +Line 10492: 0 +Line 10493: 1 +Line 10494: 1 +Line 10495: 1 +Line 10496: 0 +Line 10497: 0 +Line 10498: 0 +Line 10499: 0 +Line 10500: 0 +Line 10501: 1 +Line 10502: 1 +Line 10503: 0 +Line 10504: 0 +Line 10505: 1 +Line 10506: 1 +Line 10507: 0 +Line 10508: 1 +Line 10509: 0 +Line 10510: 1 +Line 10511: 1 +Line 10512: 0 +Line 10513: 0 +Line 10514: 0 +Line 10515: 0 +Line 10516: 0 +Line 10517: 0 +Line 10518: 0 +Line 10519: 0 +Line 10520: 1 +Line 10521: 1 +Line 10522: 1 +Line 10523: 1 +Line 10524: 1 +Line 10525: 0 +Line 10526: 1 +Line 10527: 0 +Line 10528: 0 +Line 10529: 0 +Line 10530: 0 +Line 10531: 0 +Line 10532: 0 +Line 10533: 1 +Line 10534: 0 +Line 10535: 1 +Line 10536: 1 +Line 10537: 0 +Line 10538: 1 +Line 10539: 1 +Line 10540: 0 +Line 10541: 1 +Line 10542: 0 +Line 10543: 0 +Line 10544: 0 +Line 10545: 0 +Line 10546: 0 +Line 10547: 0 +Line 10548: 0 +Line 10549: 0 +Line 10550: 0 +Line 10551: 0 +Line 10552: 1 +Line 10553: 1 +Line 10554: 1 +Line 10555: 0 +Line 10556: 1 +Line 10557: 1 +Line 10558: 0 +Line 10559: 1 +Line 10560: 0 +Line 10561: 0 +Line 10562: 0 +Line 10563: 0 +Line 10564: 0 +Line 10565: 1 +Line 10566: 0 +Line 10567: 1 +Line 10568: 0 +Line 10569: 0 +Line 10570: 0 +Line 10571: 0 +Line 10572: 1 +Line 10573: 0 +Line 10574: 0 +Line 10575: 0 +Line 10576: 0 +Line 10577: 0 +Line 10578: 0 +Line 10579: 0 +Line 10580: 0 +Line 10581: 0 +Line 10582: 0 +Line 10583: 0 +Line 10584: 1 +Line 10585: 1 +Line 10586: 1 +Line 10587: 0 +Line 10588: 0 +Line 10589: 0 +Line 10590: 0 +Line 10591: 0 +Line 10592: 0 +Line 10593: 0 +Line 10594: 0 +Line 10595: 0 +Line 10596: 0 +Line 10597: 1 +Line 10598: 0 +Line 10599: 0 +Line 10600: 0 +Line 10601: 1 +Line 10602: 1 +Line 10603: 0 +Line 10604: 0 +Line 10605: 1 +Line 10606: 0 +Line 10607: 1 +Line 10608: 0 +Line 10609: 0 +Line 10610: 0 +Line 10611: 0 +Line 10612: 0 +Line 10613: 0 +Line 10614: 0 +Line 10615: 0 +Line 10616: 1 +Line 10617: 1 +Line 10618: 0 +Line 10619: 1 +Line 10620: 0 +Line 10621: 0 +Line 10622: 1 +Line 10623: 0 +Line 10624: 0 +Line 10625: 0 +Line 10626: 0 +Line 10627: 0 +Line 10628: 0 +Line 10629: 0 +Line 10630: 1 +Line 10631: 1 +Line 10632: 1 +Line 10633: 1 +Line 10634: 0 +Line 10635: 0 +Line 10636: 1 +Line 10637: 1 +Line 10638: 0 +Line 10639: 1 +Line 10640: 0 +Line 10641: 0 +Line 10642: 0 +Line 10643: 0 +Line 10644: 0 +Line 10645: 0 +Line 10646: 0 +Line 10647: 0 +Line 10648: 1 +Line 10649: 1 +Line 10650: 0 +Line 10651: 0 +Line 10652: 0 +Line 10653: 1 +Line 10654: 0 +Line 10655: 1 +Line 10656: 0 +Line 10657: 0 +Line 10658: 0 +Line 10659: 0 +Line 10660: 0 +Line 10661: 0 +Line 10662: 1 +Line 10663: 1 +Line 10664: 0 +Line 10665: 0 +Line 10666: 1 +Line 10667: 1 +Line 10668: 1 +Line 10669: 1 +Line 10670: 1 +Line 10671: 1 +Line 10672: 0 +Line 10673: 0 +Line 10674: 0 +Line 10675: 0 +Line 10676: 0 +Line 10677: 0 +Line 10678: 0 +Line 10679: 0 +Line 10680: 1 +Line 10681: 0 +Line 10682: 1 +Line 10683: 1 +Line 10684: 0 +Line 10685: 1 +Line 10686: 1 +Line 10687: 0 +Line 10688: 0 +Line 10689: 0 +Line 10690: 0 +Line 10691: 0 +Line 10692: 0 +Line 10693: 0 +Line 10694: 1 +Line 10695: 0 +Line 10696: 1 +Line 10697: 0 +Line 10698: 1 +Line 10699: 1 +Line 10700: 1 +Line 10701: 1 +Line 10702: 0 +Line 10703: 0 +Line 10704: 0 +Line 10705: 0 +Line 10706: 0 +Line 10707: 0 +Line 10708: 0 +Line 10709: 0 +Line 10710: 0 +Line 10711: 0 +Line 10712: 1 +Line 10713: 0 +Line 10714: 1 +Line 10715: 0 +Line 10716: 1 +Line 10717: 0 +Line 10718: 0 +Line 10719: 0 +Line 10720: 0 +Line 10721: 0 +Line 10722: 0 +Line 10723: 0 +Line 10724: 0 +Line 10725: 0 +Line 10726: 1 +Line 10727: 0 +Line 10728: 0 +Line 10729: 1 +Line 10730: 0 +Line 10731: 0 +Line 10732: 0 +Line 10733: 1 +Line 10734: 0 +Line 10735: 0 +Line 10736: 0 +Line 10737: 0 +Line 10738: 0 +Line 10739: 0 +Line 10740: 0 +Line 10741: 0 +Line 10742: 0 +Line 10743: 0 +Line 10744: 1 +Line 10745: 0 +Line 10746: 0 +Line 10747: 1 +Line 10748: 1 +Line 10749: 0 +Line 10750: 0 +Line 10751: 1 +Line 10752: 0 +Line 10753: 0 +Line 10754: 0 +Line 10755: 0 +Line 10756: 0 +Line 10757: 0 +Line 10758: 0 +Line 10759: 1 +Line 10760: 1 +Line 10761: 1 +Line 10762: 0 +Line 10763: 1 +Line 10764: 0 +Line 10765: 1 +Line 10766: 1 +Line 10767: 1 +Line 10768: 0 +Line 10769: 0 +Line 10770: 0 +Line 10771: 0 +Line 10772: 0 +Line 10773: 0 +Line 10774: 0 +Line 10775: 0 +Line 10776: 1 +Line 10777: 0 +Line 10778: 0 +Line 10779: 0 +Line 10780: 1 +Line 10781: 0 +Line 10782: 1 +Line 10783: 1 +Line 10784: 0 +Line 10785: 0 +Line 10786: 0 +Line 10787: 0 +Line 10788: 0 +Line 10789: 0 +Line 10790: 0 +Line 10791: 1 +Line 10792: 0 +Line 10793: 1 +Line 10794: 1 +Line 10795: 1 +Line 10796: 0 +Line 10797: 1 +Line 10798: 0 +Line 10799: 0 +Line 10800: 0 +Line 10801: 0 +Line 10802: 0 +Line 10803: 0 +Line 10804: 0 +Line 10805: 0 +Line 10806: 0 +Line 10807: 0 +Line 10808: 0 +Line 10809: 1 +Line 10810: 1 +Line 10811: 1 +Line 10812: 1 +Line 10813: 1 +Line 10814: 0 +Line 10815: 0 +Line 10816: 0 +Line 10817: 0 +Line 10818: 0 +Line 10819: 0 +Line 10820: 0 +Line 10821: 0 +Line 10822: 0 +Line 10823: 1 +Line 10824: 0 +Line 10825: 0 +Line 10826: 0 +Line 10827: 1 +Line 10828: 1 +Line 10829: 1 +Line 10830: 0 +Line 10831: 1 +Line 10832: 0 +Line 10833: 0 +Line 10834: 0 +Line 10835: 0 +Line 10836: 0 +Line 10837: 0 +Line 10838: 0 +Line 10839: 0 +Line 10840: 0 +Line 10841: 1 +Line 10842: 1 +Line 10843: 0 +Line 10844: 1 +Line 10845: 1 +Line 10846: 0 +Line 10847: 0 +Line 10848: 0 +Line 10849: 0 +Line 10850: 0 +Line 10851: 0 +Line 10852: 0 +Line 10853: 0 +Line 10854: 0 +Line 10855: 0 +Line 10856: 1 +Line 10857: 1 +Line 10858: 0 +Line 10859: 1 +Line 10860: 0 +Line 10861: 0 +Line 10862: 1 +Line 10863: 0 +Line 10864: 0 +Line 10865: 0 +Line 10866: 0 +Line 10867: 0 +Line 10868: 0 +Line 10869: 0 +Line 10870: 0 +Line 10871: 0 +Line 10872: 0 +Line 10873: 1 +Line 10874: 0 +Line 10875: 1 +Line 10876: 1 +Line 10877: 1 +Line 10878: 0 +Line 10879: 1 +Line 10880: 0 +Line 10881: 0 +Line 10882: 0 +Line 10883: 0 +Line 10884: 0 +Line 10885: 0 +Line 10886: 0 +Line 10887: 0 +Line 10888: 1 +Line 10889: 0 +Line 10890: 0 +Line 10891: 1 +Line 10892: 0 +Line 10893: 0 +Line 10894: 1 +Line 10895: 0 +Line 10896: 0 +Line 10897: 0 +Line 10898: 0 +Line 10899: 0 +Line 10900: 0 +Line 10901: 0 +Line 10902: 0 +Line 10903: 0 +Line 10904: 0 +Line 10905: 1 +Line 10906: 0 +Line 10907: 0 +Line 10908: 1 +Line 10909: 1 +Line 10910: 1 +Line 10911: 0 +Line 10912: 0 +Line 10913: 0 +Line 10914: 0 +Line 10915: 0 +Line 10916: 0 +Line 10917: 0 +Line 10918: 0 +Line 10919: 0 +Line 10920: 0 +Line 10921: 1 +Line 10922: 0 +Line 10923: 1 +Line 10924: 1 +Line 10925: 1 +Line 10926: 0 +Line 10927: 1 +Line 10928: 0 +Line 10929: 0 +Line 10930: 0 +Line 10931: 0 +Line 10932: 0 +Line 10933: 0 +Line 10934: 0 +Line 10935: 0 +Line 10936: 0 +Line 10937: 0 +Line 10938: 1 +Line 10939: 1 +Line 10940: 1 +Line 10941: 1 +Line 10942: 1 +Line 10943: 0 +Line 10944: 0 +Line 10945: 0 +Line 10946: 0 +Line 10947: 0 +Line 10948: 0 +Line 10949: 0 +Line 10950: 0 +Line 10951: 0 +Line 10952: 0 +Line 10953: 0 +Line 10954: 1 +Line 10955: 1 +Line 10956: 0 +Line 10957: 1 +Line 10958: 0 +Line 10959: 0 +Line 10960: 0 +Line 10961: 0 +Line 10962: 0 +Line 10963: 0 +Line 10964: 0 +Line 10965: 0 +Line 10966: 0 +Line 10967: 0 +Line 10968: 0 +Line 10969: 0 +Line 10970: 1 +Line 10971: 0 +Line 10972: 1 +Line 10973: 1 +Line 10974: 1 +Line 10975: 1 +Line 10976: 0 +Line 10977: 0 +Line 10978: 0 +Line 10979: 0 +Line 10980: 0 +Line 10981: 0 +Line 10982: 0 +Line 10983: 0 +Line 10984: 0 +Line 10985: 0 +Line 10986: 0 +Line 10987: 1 +Line 10988: 0 +Line 10989: 1 +Line 10990: 1 +Line 10991: 1 +Line 10992: 0 +Line 10993: 0 +Line 10994: 0 +Line 10995: 0 +Line 10996: 0 +Line 10997: 0 +Line 10998: 0 +Line 10999: 0 +Line 11000: 0 +Line 11001: 0 +Line 11002: 0 +Line 11003: 1 +Line 11004: 1 +Line 11005: 1 +Line 11006: 1 +Line 11007: 1 +Line 11008: 0 +Line 11009: 0 +Line 11010: 0 +Line 11011: 0 +Line 11012: 0 +Line 11013: 0 +Line 11014: 0 +Line 11015: 0 +Line 11016: 0 +Line 11017: 0 +Line 11018: 0 +Line 11019: 0 +Line 11020: 0 +Line 11021: 1 +Line 11022: 0 +Line 11023: 1 +Line 11024: 0 +Line 11025: 0 +Line 11026: 0 +Line 11027: 0 +Line 11028: 0 +Line 11029: 0 +Line 11030: 0 +Line 11031: 0 +Line 11032: 0 +Line 11033: 0 +Line 11034: 0 +Line 11035: 0 +Line 11036: 1 +Line 11037: 1 +Line 11038: 1 +Line 11039: 1 +Line 11040: 0 +Line 11041: 0 +Line 11042: 0 +Line 11043: 0 +Line 11044: 0 +Line 11045: 0 +Line 11046: 0 +Line 11047: 0 +Line 11048: 0 +Line 11049: 0 +Line 11050: 0 +Line 11051: 0 +Line 11052: 0 +Line 11053: 0 +Line 11054: 0 +Line 11055: 0 +Line 11056: 0 +Line 11057: 0 +Line 11058: 0 +Line 11059: 0 +Line 11060: 0 +Line 11061: 0 +Line 11062: 0 +Line 11063: 0 +Line 11064: 0 +Line 11065: 0 +Line 11066: 0 +Line 11067: 0 +Line 11068: 0 +Line 11069: 0 +Line 11070: 0 +Line 11071: 0 +Line 11072: 0 +Line 11073: 1 +Line 11074: 0 +Line 11075: 0 +Line 11076: 0 +Line 11077: 1 +Line 11078: 1 +Line 11079: 0 +Line 11080: 0 +Line 11081: 1 +Line 11082: 0 +Line 11083: 1 +Line 11084: 0 +Line 11085: 0 +Line 11086: 0 +Line 11087: 0 +Line 11088: 0 +Line 11089: 0 +Line 11090: 0 +Line 11091: 0 +Line 11092: 0 +Line 11093: 0 +Line 11094: 0 +Line 11095: 0 +Line 11096: 0 +Line 11097: 0 +Line 11098: 0 +Line 11099: 0 +Line 11100: 0 +Line 11101: 0 +Line 11102: 0 +Line 11103: 0 +Line 11104: 0 +Line 11105: 0 +Line 11106: 0 +Line 11107: 0 +Line 11108: 0 +Line 11109: 0 +Line 11110: 0 +Line 11111: 0 +Line 11112: 0 +Line 11113: 0 +Line 11114: 0 +Line 11115: 0 +Line 11116: 0 +Line 11117: 0 +Line 11118: 0 +Line 11119: 0 +Line 11120: 0 +Line 11121: 0 +Line 11122: 0 +Line 11123: 0 +Line 11124: 0 +Line 11125: 0 +Line 11126: 0 +Line 11127: 0 +Line 11128: 0 +Line 11129: 0 +Line 11130: 0 +Line 11131: 0 +Line 11132: 0 +Line 11133: 0 +Line 11134: 0 +Line 11135: 0 +Line 11136: 0 +Line 11137: 0 +Line 11138: 0 +Line 11139: 0 +Line 11140: 0 +Line 11141: 0 +Line 11142: 0 +Line 11143: 0 +Line 11144: 0 +Line 11145: 0 +Line 11146: 0 +Line 11147: 0 +Line 11148: 0 +Line 11149: 0 +Line 11150: 0 +Line 11151: 0 +Line 11152: 0 +Line 11153: 0 +Line 11154: 0 +Line 11155: 0 +Line 11156: 0 +Line 11157: 0 +Line 11158: 0 +Line 11159: 0 +Line 11160: 0 +Line 11161: 0 +Line 11162: 0 +Line 11163: 0 +Line 11164: 0 +Line 11165: 0 +Line 11166: 0 +Line 11167: 0 +Line 11168: 0 +Line 11169: 0 +Line 11170: 0 +Line 11171: 0 +Line 11172: 1 +Line 11173: 0 +Line 11174: 0 +Line 11175: 0 +Line 11176: 0 +Line 11177: 0 +Line 11178: 0 +Line 11179: 0 +Line 11180: 1 +Line 11181: 0 +Line 11182: 1 +Line 11183: 0 +Line 11184: 0 +Line 11185: 0 +Line 11186: 0 +Line 11187: 0 +Line 11188: 0 +Line 11189: 0 +Line 11190: 0 +Line 11191: 0 +Line 11192: 0 +Line 11193: 0 +Line 11194: 0 +Line 11195: 0 +Line 11196: 0 +Line 11197: 0 +Line 11198: 0 +Line 11199: 0 +Line 11200: 0 +Line 11201: 0 +Line 11202: 0 +Line 11203: 0 +Line 11204: 1 +Line 11205: 1 +Line 11206: 1 +Line 11207: 1 +Line 11208: 1 +Line 11209: 1 +Line 11210: 1 +Line 11211: 0 +Line 11212: 0 +Line 11213: 1 +Line 11214: 1 +Line 11215: 1 +Line 11216: 0 +Line 11217: 0 +Line 11218: 0 +Line 11219: 0 +Line 11220: 0 +Line 11221: 0 +Line 11222: 0 +Line 11223: 0 +Line 11224: 0 +Line 11225: 0 +Line 11226: 0 +Line 11227: 0 +Line 11228: 0 +Line 11229: 0 +Line 11230: 0 +Line 11231: 0 +Line 11232: 0 +Line 11233: 0 +Line 11234: 0 +Line 11235: 1 +Line 11236: 0 +Line 11237: 1 +Line 11238: 1 +Line 11239: 1 +Line 11240: 0 +Line 11241: 1 +Line 11242: 1 +Line 11243: 0 +Line 11244: 1 +Line 11245: 1 +Line 11246: 0 +Line 11247: 0 +Line 11248: 0 +Line 11249: 0 +Line 11250: 0 +Line 11251: 0 +Line 11252: 0 +Line 11253: 0 +Line 11254: 0 +Line 11255: 0 +Line 11256: 0 +Line 11257: 0 +Line 11258: 0 +Line 11259: 0 +Line 11260: 0 +Line 11261: 0 +Line 11262: 0 +Line 11263: 0 +Line 11264: 0 +Line 11265: 0 +Line 11266: 0 +Line 11267: 1 +Line 11268: 1 +Line 11269: 1 +Line 11270: 1 +Line 11271: 0 +Line 11272: 0 +Line 11273: 1 +Line 11274: 1 +Line 11275: 1 +Line 11276: 0 +Line 11277: 0 +Line 11278: 0 +Line 11279: 1 +Line 11280: 0 +Line 11281: 0 +Line 11282: 0 +Line 11283: 0 +Line 11284: 0 +Line 11285: 0 +Line 11286: 0 +Line 11287: 0 +Line 11288: 0 +Line 11289: 0 +Line 11290: 0 +Line 11291: 0 +Line 11292: 0 +Line 11293: 0 +Line 11294: 0 +Line 11295: 0 +Line 11296: 0 +Line 11297: 0 +Line 11298: 1 +Line 11299: 0 +Line 11300: 0 +Line 11301: 1 +Line 11302: 0 +Line 11303: 0 +Line 11304: 1 +Line 11305: 1 +Line 11306: 0 +Line 11307: 1 +Line 11308: 0 +Line 11309: 1 +Line 11310: 0 +Line 11311: 1 +Line 11312: 0 +Line 11313: 0 +Line 11314: 0 +Line 11315: 0 +Line 11316: 0 +Line 11317: 0 +Line 11318: 0 +Line 11319: 0 +Line 11320: 0 +Line 11321: 0 +Line 11322: 0 +Line 11323: 0 +Line 11324: 0 +Line 11325: 0 +Line 11326: 0 +Line 11327: 0 +Line 11328: 0 +Line 11329: 0 +Line 11330: 1 +Line 11331: 0 +Line 11332: 1 +Line 11333: 0 +Line 11334: 1 +Line 11335: 0 +Line 11336: 0 +Line 11337: 1 +Line 11338: 1 +Line 11339: 1 +Line 11340: 1 +Line 11341: 1 +Line 11342: 1 +Line 11343: 0 +Line 11344: 0 +Line 11345: 0 +Line 11346: 0 +Line 11347: 0 +Line 11348: 0 +Line 11349: 0 +Line 11350: 0 +Line 11351: 0 +Line 11352: 0 +Line 11353: 0 +Line 11354: 0 +Line 11355: 0 +Line 11356: 0 +Line 11357: 0 +Line 11358: 0 +Line 11359: 0 +Line 11360: 0 +Line 11361: 0 +Line 11362: 1 +Line 11363: 0 +Line 11364: 1 +Line 11365: 1 +Line 11366: 1 +Line 11367: 1 +Line 11368: 0 +Line 11369: 1 +Line 11370: 0 +Line 11371: 1 +Line 11372: 1 +Line 11373: 0 +Line 11374: 0 +Line 11375: 1 +Line 11376: 0 +Line 11377: 0 +Line 11378: 0 +Line 11379: 0 +Line 11380: 0 +Line 11381: 0 +Line 11382: 0 +Line 11383: 0 +Line 11384: 0 +Line 11385: 0 +Line 11386: 0 +Line 11387: 0 +Line 11388: 0 +Line 11389: 0 +Line 11390: 0 +Line 11391: 0 +Line 11392: 0 +Line 11393: 0 +Line 11394: 1 +Line 11395: 1 +Line 11396: 0 +Line 11397: 0 +Line 11398: 1 +Line 11399: 1 +Line 11400: 0 +Line 11401: 1 +Line 11402: 0 +Line 11403: 1 +Line 11404: 1 +Line 11405: 1 +Line 11406: 1 +Line 11407: 1 +Line 11408: 0 +Line 11409: 0 +Line 11410: 0 +Line 11411: 0 +Line 11412: 0 +Line 11413: 0 +Line 11414: 0 +Line 11415: 0 +Line 11416: 0 +Line 11417: 0 +Line 11418: 0 +Line 11419: 0 +Line 11420: 0 +Line 11421: 0 +Line 11422: 0 +Line 11423: 0 +Line 11424: 0 +Line 11425: 0 +Line 11426: 1 +Line 11427: 1 +Line 11428: 0 +Line 11429: 1 +Line 11430: 1 +Line 11431: 0 +Line 11432: 1 +Line 11433: 0 +Line 11434: 0 +Line 11435: 1 +Line 11436: 0 +Line 11437: 0 +Line 11438: 0 +Line 11439: 0 +Line 11440: 0 +Line 11441: 0 +Line 11442: 0 +Line 11443: 0 +Line 11444: 0 +Line 11445: 0 +Line 11446: 0 +Line 11447: 0 +Line 11448: 0 +Line 11449: 0 +Line 11450: 0 +Line 11451: 0 +Line 11452: 0 +Line 11453: 0 +Line 11454: 0 +Line 11455: 0 +Line 11456: 0 +Line 11457: 0 +Line 11458: 1 +Line 11459: 1 +Line 11460: 1 +Line 11461: 0 +Line 11462: 0 +Line 11463: 0 +Line 11464: 1 +Line 11465: 1 +Line 11466: 1 +Line 11467: 1 +Line 11468: 0 +Line 11469: 0 +Line 11470: 1 +Line 11471: 0 +Line 11472: 0 +Line 11473: 0 +Line 11474: 0 +Line 11475: 0 +Line 11476: 0 +Line 11477: 0 +Line 11478: 0 +Line 11479: 0 +Line 11480: 0 +Line 11481: 0 +Line 11482: 0 +Line 11483: 0 +Line 11484: 0 +Line 11485: 0 +Line 11486: 0 +Line 11487: 0 +Line 11488: 0 +Line 11489: 0 +Line 11490: 1 +Line 11491: 1 +Line 11492: 1 +Line 11493: 0 +Line 11494: 1 +Line 11495: 0 +Line 11496: 1 +Line 11497: 0 +Line 11498: 0 +Line 11499: 1 +Line 11500: 1 +Line 11501: 0 +Line 11502: 0 +Line 11503: 1 +Line 11504: 0 +Line 11505: 0 +Line 11506: 0 +Line 11507: 0 +Line 11508: 0 +Line 11509: 0 +Line 11510: 0 +Line 11511: 0 +Line 11512: 0 +Line 11513: 0 +Line 11514: 0 +Line 11515: 0 +Line 11516: 0 +Line 11517: 0 +Line 11518: 0 +Line 11519: 0 +Line 11520: 0 +Line 11521: 0 +Line 11522: 1 +Line 11523: 1 +Line 11524: 1 +Line 11525: 0 +Line 11526: 1 +Line 11527: 1 +Line 11528: 1 +Line 11529: 0 +Line 11530: 0 +Line 11531: 1 +Line 11532: 1 +Line 11533: 0 +Line 11534: 1 +Line 11535: 0 +Line 11536: 0 +Line 11537: 0 +Line 11538: 0 +Line 11539: 0 +Line 11540: 0 +Line 11541: 0 +Line 11542: 0 +Line 11543: 0 +Line 11544: 0 +Line 11545: 0 +Line 11546: 0 +Line 11547: 0 +Line 11548: 0 +Line 11549: 0 +Line 11550: 0 +Line 11551: 0 +Line 11552: 0 +Line 11553: 0 +Line 11554: 1 +Line 11555: 1 +Line 11556: 1 +Line 11557: 1 +Line 11558: 0 +Line 11559: 0 +Line 11560: 0 +Line 11561: 0 +Line 11562: 0 +Line 11563: 1 +Line 11564: 0 +Line 11565: 0 +Line 11566: 0 +Line 11567: 1 +Line 11568: 0 +Line 11569: 0 +Line 11570: 0 +Line 11571: 0 +Line 11572: 0 +Line 11573: 0 +Line 11574: 0 +Line 11575: 0 +Line 11576: 0 +Line 11577: 0 +Line 11578: 0 +Line 11579: 0 +Line 11580: 0 +Line 11581: 0 +Line 11582: 0 +Line 11583: 0 +Line 11584: 0 +Line 11585: 0 +Line 11586: 1 +Line 11587: 1 +Line 11588: 1 +Line 11589: 1 +Line 11590: 0 +Line 11591: 0 +Line 11592: 0 +Line 11593: 0 +Line 11594: 0 +Line 11595: 1 +Line 11596: 1 +Line 11597: 1 +Line 11598: 1 +Line 11599: 1 +Line 11600: 0 +Line 11601: 0 +Line 11602: 0 +Line 11603: 0 +Line 11604: 0 +Line 11605: 0 +Line 11606: 0 +Line 11607: 0 +Line 11608: 0 +Line 11609: 0 +Line 11610: 0 +Line 11611: 0 +Line 11612: 0 +Line 11613: 0 +Line 11614: 0 +Line 11615: 0 +Line 11616: 0 +Line 11617: 0 +Line 11618: 1 +Line 11619: 1 +Line 11620: 1 +Line 11621: 0 +Line 11622: 1 +Line 11623: 1 +Line 11624: 1 +Line 11625: 1 +Line 11626: 1 +Line 11627: 0 +Line 11628: 0 +Line 11629: 1 +Line 11630: 0 +Line 11631: 0 +Line 11632: 0 +Line 11633: 0 +Line 11634: 0 +Line 11635: 0 +Line 11636: 0 +Line 11637: 0 +Line 11638: 0 +Line 11639: 0 +Line 11640: 0 +Line 11641: 0 +Line 11642: 0 +Line 11643: 0 +Line 11644: 0 +Line 11645: 0 +Line 11646: 0 +Line 11647: 0 +Line 11648: 0 +Line 11649: 0 +Line 11650: 1 +Line 11651: 1 +Line 11652: 1 +Line 11653: 0 +Line 11654: 1 +Line 11655: 1 +Line 11656: 1 +Line 11657: 0 +Line 11658: 0 +Line 11659: 0 +Line 11660: 0 +Line 11661: 0 +Line 11662: 0 +Line 11663: 0 +Line 11664: 0 +Line 11665: 0 +Line 11666: 0 +Line 11667: 0 +Line 11668: 0 +Line 11669: 0 +Line 11670: 0 +Line 11671: 0 +Line 11672: 0 +Line 11673: 0 +Line 11674: 0 +Line 11675: 0 +Line 11676: 0 +Line 11677: 0 +Line 11678: 0 +Line 11679: 0 +Line 11680: 0 +Line 11681: 0 +Line 11682: 1 +Line 11683: 1 +Line 11684: 1 +Line 11685: 0 +Line 11686: 1 +Line 11687: 1 +Line 11688: 0 +Line 11689: 0 +Line 11690: 0 +Line 11691: 1 +Line 11692: 0 +Line 11693: 0 +Line 11694: 0 +Line 11695: 0 +Line 11696: 0 +Line 11697: 0 +Line 11698: 0 +Line 11699: 0 +Line 11700: 0 +Line 11701: 0 +Line 11702: 0 +Line 11703: 0 +Line 11704: 0 +Line 11705: 0 +Line 11706: 0 +Line 11707: 0 +Line 11708: 0 +Line 11709: 0 +Line 11710: 0 +Line 11711: 0 +Line 11712: 0 +Line 11713: 0 +Line 11714: 1 +Line 11715: 1 +Line 11716: 1 +Line 11717: 0 +Line 11718: 1 +Line 11719: 0 +Line 11720: 1 +Line 11721: 0 +Line 11722: 1 +Line 11723: 0 +Line 11724: 1 +Line 11725: 1 +Line 11726: 0 +Line 11727: 1 +Line 11728: 0 +Line 11729: 0 +Line 11730: 0 +Line 11731: 0 +Line 11732: 0 +Line 11733: 0 +Line 11734: 0 +Line 11735: 0 +Line 11736: 0 +Line 11737: 0 +Line 11738: 0 +Line 11739: 0 +Line 11740: 0 +Line 11741: 0 +Line 11742: 0 +Line 11743: 0 +Line 11744: 0 +Line 11745: 0 +Line 11746: 1 +Line 11747: 1 +Line 11748: 1 +Line 11749: 0 +Line 11750: 1 +Line 11751: 0 +Line 11752: 0 +Line 11753: 1 +Line 11754: 1 +Line 11755: 0 +Line 11756: 1 +Line 11757: 0 +Line 11758: 0 +Line 11759: 1 +Line 11760: 0 +Line 11761: 0 +Line 11762: 0 +Line 11763: 0 +Line 11764: 0 +Line 11765: 0 +Line 11766: 0 +Line 11767: 0 +Line 11768: 0 +Line 11769: 0 +Line 11770: 0 +Line 11771: 0 +Line 11772: 0 +Line 11773: 0 +Line 11774: 0 +Line 11775: 0 +Line 11776: 0 +Line 11777: 0 +Line 11778: 1 +Line 11779: 1 +Line 11780: 1 +Line 11781: 0 +Line 11782: 1 +Line 11783: 0 +Line 11784: 0 +Line 11785: 1 +Line 11786: 0 +Line 11787: 1 +Line 11788: 0 +Line 11789: 0 +Line 11790: 1 +Line 11791: 0 +Line 11792: 0 +Line 11793: 0 +Line 11794: 0 +Line 11795: 0 +Line 11796: 0 +Line 11797: 0 +Line 11798: 0 +Line 11799: 0 +Line 11800: 0 +Line 11801: 0 +Line 11802: 0 +Line 11803: 0 +Line 11804: 0 +Line 11805: 0 +Line 11806: 0 +Line 11807: 0 +Line 11808: 0 +Line 11809: 0 +Line 11810: 1 +Line 11811: 1 +Line 11812: 1 +Line 11813: 0 +Line 11814: 1 +Line 11815: 0 +Line 11816: 0 +Line 11817: 1 +Line 11818: 1 +Line 11819: 0 +Line 11820: 1 +Line 11821: 0 +Line 11822: 0 +Line 11823: 1 +Line 11824: 0 +Line 11825: 0 +Line 11826: 0 +Line 11827: 0 +Line 11828: 0 +Line 11829: 0 +Line 11830: 0 +Line 11831: 0 +Line 11832: 0 +Line 11833: 0 +Line 11834: 0 +Line 11835: 0 +Line 11836: 0 +Line 11837: 0 +Line 11838: 0 +Line 11839: 0 +Line 11840: 0 +Line 11841: 0 +Line 11842: 1 +Line 11843: 1 +Line 11844: 1 +Line 11845: 0 +Line 11846: 1 +Line 11847: 0 +Line 11848: 1 +Line 11849: 0 +Line 11850: 1 +Line 11851: 0 +Line 11852: 1 +Line 11853: 1 +Line 11854: 0 +Line 11855: 1 +Line 11856: 0 +Line 11857: 0 +Line 11858: 0 +Line 11859: 0 +Line 11860: 0 +Line 11861: 0 +Line 11862: 0 +Line 11863: 0 +Line 11864: 0 +Line 11865: 0 +Line 11866: 0 +Line 11867: 0 +Line 11868: 0 +Line 11869: 0 +Line 11870: 0 +Line 11871: 0 +Line 11872: 0 +Line 11873: 0 +Line 11874: 1 +Line 11875: 1 +Line 11876: 1 +Line 11877: 0 +Line 11878: 1 +Line 11879: 1 +Line 11880: 0 +Line 11881: 0 +Line 11882: 0 +Line 11883: 1 +Line 11884: 0 +Line 11885: 0 +Line 11886: 0 +Line 11887: 0 +Line 11888: 0 +Line 11889: 0 +Line 11890: 0 +Line 11891: 0 +Line 11892: 0 +Line 11893: 0 +Line 11894: 0 +Line 11895: 0 +Line 11896: 0 +Line 11897: 0 +Line 11898: 0 +Line 11899: 0 +Line 11900: 0 +Line 11901: 0 +Line 11902: 0 +Line 11903: 0 +Line 11904: 0 +Line 11905: 0 +Line 11906: 1 +Line 11907: 1 +Line 11908: 1 +Line 11909: 0 +Line 11910: 1 +Line 11911: 1 +Line 11912: 1 +Line 11913: 0 +Line 11914: 0 +Line 11915: 0 +Line 11916: 0 +Line 11917: 0 +Line 11918: 0 +Line 11919: 0 +Line 11920: 0 +Line 11921: 0 +Line 11922: 0 +Line 11923: 0 +Line 11924: 0 +Line 11925: 0 +Line 11926: 0 +Line 11927: 0 +Line 11928: 0 +Line 11929: 0 +Line 11930: 0 +Line 11931: 0 +Line 11932: 0 +Line 11933: 0 +Line 11934: 0 +Line 11935: 0 +Line 11936: 0 +Line 11937: 0 +Line 11938: 1 +Line 11939: 1 +Line 11940: 1 +Line 11941: 0 +Line 11942: 1 +Line 11943: 1 +Line 11944: 1 +Line 11945: 1 +Line 11946: 1 +Line 11947: 0 +Line 11948: 0 +Line 11949: 1 +Line 11950: 0 +Line 11951: 0 +Line 11952: 0 +Line 11953: 0 +Line 11954: 0 +Line 11955: 0 +Line 11956: 0 +Line 11957: 0 +Line 11958: 0 +Line 11959: 0 +Line 11960: 0 +Line 11961: 0 +Line 11962: 0 +Line 11963: 0 +Line 11964: 0 +Line 11965: 0 +Line 11966: 0 +Line 11967: 0 +Line 11968: 0 +Line 11969: 0 +Line 11970: 1 +Line 11971: 1 +Line 11972: 1 +Line 11973: 1 +Line 11974: 0 +Line 11975: 0 +Line 11976: 0 +Line 11977: 0 +Line 11978: 0 +Line 11979: 1 +Line 11980: 1 +Line 11981: 1 +Line 11982: 1 +Line 11983: 1 +Line 11984: 0 +Line 11985: 0 +Line 11986: 0 +Line 11987: 0 +Line 11988: 0 +Line 11989: 0 +Line 11990: 0 +Line 11991: 0 +Line 11992: 0 +Line 11993: 0 +Line 11994: 0 +Line 11995: 0 +Line 11996: 0 +Line 11997: 0 +Line 11998: 0 +Line 11999: 0 +Line 12000: 0 +Line 12001: 0 +Line 12002: 1 +Line 12003: 1 +Line 12004: 1 +Line 12005: 1 +Line 12006: 0 +Line 12007: 0 +Line 12008: 0 +Line 12009: 0 +Line 12010: 0 +Line 12011: 1 +Line 12012: 0 +Line 12013: 0 +Line 12014: 0 +Line 12015: 1 +Line 12016: 0 +Line 12017: 0 +Line 12018: 0 +Line 12019: 0 +Line 12020: 0 +Line 12021: 0 +Line 12022: 0 +Line 12023: 0 +Line 12024: 0 +Line 12025: 0 +Line 12026: 0 +Line 12027: 0 +Line 12028: 0 +Line 12029: 0 +Line 12030: 0 +Line 12031: 0 +Line 12032: 0 +Line 12033: 0 +Line 12034: 1 +Line 12035: 1 +Line 12036: 1 +Line 12037: 0 +Line 12038: 1 +Line 12039: 1 +Line 12040: 1 +Line 12041: 0 +Line 12042: 0 +Line 12043: 1 +Line 12044: 1 +Line 12045: 0 +Line 12046: 1 +Line 12047: 0 +Line 12048: 0 +Line 12049: 0 +Line 12050: 0 +Line 12051: 0 +Line 12052: 0 +Line 12053: 0 +Line 12054: 0 +Line 12055: 0 +Line 12056: 0 +Line 12057: 0 +Line 12058: 0 +Line 12059: 0 +Line 12060: 0 +Line 12061: 0 +Line 12062: 0 +Line 12063: 0 +Line 12064: 0 +Line 12065: 0 +Line 12066: 1 +Line 12067: 1 +Line 12068: 1 +Line 12069: 0 +Line 12070: 1 +Line 12071: 0 +Line 12072: 1 +Line 12073: 0 +Line 12074: 0 +Line 12075: 1 +Line 12076: 1 +Line 12077: 0 +Line 12078: 0 +Line 12079: 1 +Line 12080: 0 +Line 12081: 0 +Line 12082: 0 +Line 12083: 0 +Line 12084: 0 +Line 12085: 0 +Line 12086: 0 +Line 12087: 0 +Line 12088: 0 +Line 12089: 0 +Line 12090: 0 +Line 12091: 0 +Line 12092: 0 +Line 12093: 0 +Line 12094: 0 +Line 12095: 0 +Line 12096: 0 +Line 12097: 0 +Line 12098: 1 +Line 12099: 1 +Line 12100: 1 +Line 12101: 0 +Line 12102: 0 +Line 12103: 0 +Line 12104: 1 +Line 12105: 1 +Line 12106: 1 +Line 12107: 1 +Line 12108: 0 +Line 12109: 0 +Line 12110: 1 +Line 12111: 0 +Line 12112: 0 +Line 12113: 0 +Line 12114: 0 +Line 12115: 0 +Line 12116: 0 +Line 12117: 0 +Line 12118: 0 +Line 12119: 0 +Line 12120: 0 +Line 12121: 0 +Line 12122: 0 +Line 12123: 0 +Line 12124: 0 +Line 12125: 0 +Line 12126: 0 +Line 12127: 0 +Line 12128: 0 +Line 12129: 0 +Line 12130: 1 +Line 12131: 1 +Line 12132: 0 +Line 12133: 1 +Line 12134: 1 +Line 12135: 0 +Line 12136: 1 +Line 12137: 0 +Line 12138: 0 +Line 12139: 1 +Line 12140: 0 +Line 12141: 0 +Line 12142: 0 +Line 12143: 0 +Line 12144: 0 +Line 12145: 0 +Line 12146: 0 +Line 12147: 0 +Line 12148: 0 +Line 12149: 0 +Line 12150: 0 +Line 12151: 0 +Line 12152: 0 +Line 12153: 0 +Line 12154: 0 +Line 12155: 0 +Line 12156: 0 +Line 12157: 0 +Line 12158: 0 +Line 12159: 0 +Line 12160: 0 +Line 12161: 0 +Line 12162: 1 +Line 12163: 1 +Line 12164: 0 +Line 12165: 0 +Line 12166: 1 +Line 12167: 1 +Line 12168: 0 +Line 12169: 1 +Line 12170: 0 +Line 12171: 1 +Line 12172: 1 +Line 12173: 1 +Line 12174: 1 +Line 12175: 1 +Line 12176: 0 +Line 12177: 0 +Line 12178: 0 +Line 12179: 0 +Line 12180: 0 +Line 12181: 0 +Line 12182: 0 +Line 12183: 0 +Line 12184: 0 +Line 12185: 0 +Line 12186: 0 +Line 12187: 0 +Line 12188: 0 +Line 12189: 0 +Line 12190: 0 +Line 12191: 0 +Line 12192: 0 +Line 12193: 0 +Line 12194: 1 +Line 12195: 0 +Line 12196: 1 +Line 12197: 1 +Line 12198: 1 +Line 12199: 1 +Line 12200: 0 +Line 12201: 1 +Line 12202: 0 +Line 12203: 1 +Line 12204: 1 +Line 12205: 0 +Line 12206: 0 +Line 12207: 1 +Line 12208: 0 +Line 12209: 0 +Line 12210: 0 +Line 12211: 0 +Line 12212: 0 +Line 12213: 0 +Line 12214: 0 +Line 12215: 0 +Line 12216: 0 +Line 12217: 0 +Line 12218: 0 +Line 12219: 0 +Line 12220: 0 +Line 12221: 0 +Line 12222: 0 +Line 12223: 0 +Line 12224: 0 +Line 12225: 0 +Line 12226: 1 +Line 12227: 0 +Line 12228: 1 +Line 12229: 0 +Line 12230: 1 +Line 12231: 0 +Line 12232: 0 +Line 12233: 1 +Line 12234: 1 +Line 12235: 1 +Line 12236: 1 +Line 12237: 1 +Line 12238: 1 +Line 12239: 0 +Line 12240: 0 +Line 12241: 0 +Line 12242: 0 +Line 12243: 0 +Line 12244: 0 +Line 12245: 0 +Line 12246: 0 +Line 12247: 0 +Line 12248: 0 +Line 12249: 0 +Line 12250: 0 +Line 12251: 0 +Line 12252: 0 +Line 12253: 0 +Line 12254: 0 +Line 12255: 0 +Line 12256: 0 +Line 12257: 0 +Line 12258: 1 +Line 12259: 0 +Line 12260: 0 +Line 12261: 1 +Line 12262: 0 +Line 12263: 0 +Line 12264: 1 +Line 12265: 1 +Line 12266: 0 +Line 12267: 1 +Line 12268: 0 +Line 12269: 1 +Line 12270: 0 +Line 12271: 1 +Line 12272: 0 +Line 12273: 0 +Line 12274: 0 +Line 12275: 0 +Line 12276: 0 +Line 12277: 0 +Line 12278: 0 +Line 12279: 0 +Line 12280: 0 +Line 12281: 0 +Line 12282: 0 +Line 12283: 0 +Line 12284: 0 +Line 12285: 0 +Line 12286: 0 +Line 12287: 0 +Line 12288: 0 +Line 12289: 0 +Line 12290: 0 +Line 12291: 1 +Line 12292: 1 +Line 12293: 1 +Line 12294: 1 +Line 12295: 0 +Line 12296: 0 +Line 12297: 1 +Line 12298: 1 +Line 12299: 1 +Line 12300: 0 +Line 12301: 0 +Line 12302: 0 +Line 12303: 1 +Line 12304: 0 +Line 12305: 0 +Line 12306: 0 +Line 12307: 0 +Line 12308: 0 +Line 12309: 0 +Line 12310: 0 +Line 12311: 0 +Line 12312: 0 +Line 12313: 0 +Line 12314: 0 +Line 12315: 0 +Line 12316: 0 +Line 12317: 0 +Line 12318: 0 +Line 12319: 0 +Line 12320: 0 +Line 12321: 0 +Line 12322: 0 +Line 12323: 1 +Line 12324: 0 +Line 12325: 1 +Line 12326: 1 +Line 12327: 1 +Line 12328: 0 +Line 12329: 1 +Line 12330: 1 +Line 12331: 0 +Line 12332: 1 +Line 12333: 1 +Line 12334: 0 +Line 12335: 0 +Line 12336: 0 +Line 12337: 0 +Line 12338: 0 +Line 12339: 0 +Line 12340: 0 +Line 12341: 0 +Line 12342: 0 +Line 12343: 0 +Line 12344: 0 +Line 12345: 0 +Line 12346: 0 +Line 12347: 0 +Line 12348: 0 +Line 12349: 0 +Line 12350: 0 +Line 12351: 0 +Line 12352: 0 +Line 12353: 0 +Line 12354: 0 +Line 12355: 0 +Line 12356: 1 +Line 12357: 1 +Line 12358: 1 +Line 12359: 1 +Line 12360: 1 +Line 12361: 1 +Line 12362: 1 +Line 12363: 0 +Line 12364: 0 +Line 12365: 1 +Line 12366: 1 +Line 12367: 1 +Line 12368: 0 +Line 12369: 0 +Line 12370: 0 +Line 12371: 0 +Line 12372: 0 +Line 12373: 0 +Line 12374: 0 +Line 12375: 0 +Line 12376: 0 +Line 12377: 0 +Line 12378: 0 +Line 12379: 0 +Line 12380: 0 +Line 12381: 0 +Line 12382: 0 +Line 12383: 0 +Line 12384: 0 +Line 12385: 0 +Line 12386: 0 +Line 12387: 0 +Line 12388: 1 +Line 12389: 0 +Line 12390: 0 +Line 12391: 0 +Line 12392: 0 +Line 12393: 0 +Line 12394: 0 +Line 12395: 0 +Line 12396: 1 +Line 12397: 0 +Line 12398: 1 +Line 12399: 0 +Line 12400: 0 +Line 12401: 0 +Line 12402: 0 +Line 12403: 0 +Line 12404: 0 +Line 12405: 0 +Line 12406: 0 +Line 12407: 0 +Line 12408: 0 +Line 12409: 0 +Line 12410: 0 +Line 12411: 0 +Line 12412: 0 +Line 12413: 0 +Line 12414: 0 +Line 12415: 0 +Line 12416: 0 +Line 12417: 0 +Line 12418: 0 +Line 12419: 0 +Line 12420: 0 +Line 12421: 0 +Line 12422: 0 +Line 12423: 0 +Line 12424: 0 +Line 12425: 0 +Line 12426: 0 +Line 12427: 0 +Line 12428: 0 +Line 12429: 0 +Line 12430: 0 +Line 12431: 0 +Line 12432: 0 +Line 12433: 0 +Line 12434: 0 +Line 12435: 0 +Line 12436: 0 +Line 12437: 0 +Line 12438: 0 +Line 12439: 0 +Line 12440: 0 +Line 12441: 0 +Line 12442: 0 +Line 12443: 0 +Line 12444: 0 +Line 12445: 0 +Line 12446: 0 +Line 12447: 0 +Line 12448: 0 +Line 12449: 0 +Line 12450: 0 +Line 12451: 0 +Line 12452: 1 +Line 12453: 0 +Line 12454: 0 +Line 12455: 0 +Line 12456: 0 +Line 12457: 0 +Line 12458: 1 +Line 12459: 1 +Line 12460: 1 +Line 12461: 0 +Line 12462: 0 +Line 12463: 1 +Line 12464: 0 +Line 12465: 0 +Line 12466: 1 +Line 12467: 0 +Line 12468: 0 +Line 12469: 0 +Line 12470: 0 +Line 12471: 1 +Line 12472: 0 +Line 12473: 0 +Line 12474: 1 +Line 12475: 0 +Line 12476: 0 +Line 12477: 0 +Line 12478: 0 +Line 12479: 1 +Line 12480: 0 +Line 12481: 0 +Line 12482: 0 +Line 12483: 1 +Line 12484: 1 +Line 12485: 1 +Line 12486: 0 +Line 12487: 1 +Line 12488: 0 +Line 12489: 0 +Line 12490: 0 +Line 12491: 0 +Line 12492: 1 +Line 12493: 1 +Line 12494: 0 +Line 12495: 1 +Line 12496: 0 +Line 12497: 0 +Line 12498: 1 +Line 12499: 1 +Line 12500: 0 +Line 12501: 0 +Line 12502: 1 +Line 12503: 0 +Line 12504: 1 +Line 12505: 1 +Line 12506: 0 +Line 12507: 0 +Line 12508: 0 +Line 12509: 0 +Line 12510: 1 +Line 12511: 0 +Line 12512: 0 +Line 12513: 0 +Line 12514: 1 +Line 12515: 1 +Line 12516: 0 +Line 12517: 1 +Line 12518: 0 +Line 12519: 0 +Line 12520: 1 +Line 12521: 0 +Line 12522: 1 +Line 12523: 1 +Line 12524: 1 +Line 12525: 0 +Line 12526: 1 +Line 12527: 1 +Line 12528: 0 +Line 12529: 0 +Line 12530: 1 +Line 12531: 0 +Line 12532: 1 +Line 12533: 1 +Line 12534: 0 +Line 12535: 0 +Line 12536: 1 +Line 12537: 0 +Line 12538: 1 +Line 12539: 0 +Line 12540: 0 +Line 12541: 0 +Line 12542: 1 +Line 12543: 0 +Line 12544: 0 +Line 12545: 1 +Line 12546: 0 +Line 12547: 0 +Line 12548: 0 +Line 12549: 1 +Line 12550: 0 +Line 12551: 0 +Line 12552: 0 +Line 12553: 0 +Line 12554: 1 +Line 12555: 1 +Line 12556: 0 +Line 12557: 0 +Line 12558: 0 +Line 12559: 1 +Line 12560: 0 +Line 12561: 0 +Line 12562: 0 +Line 12563: 1 +Line 12564: 0 +Line 12565: 0 +Line 12566: 0 +Line 12567: 1 +Line 12568: 1 +Line 12569: 0 +Line 12570: 1 +Line 12571: 0 +Line 12572: 0 +Line 12573: 0 +Line 12574: 0 +Line 12575: 0 +Line 12576: 0 +Line 12577: 1 +Line 12578: 0 +Line 12579: 0 +Line 12580: 0 +Line 12581: 1 +Line 12582: 0 +Line 12583: 0 +Line 12584: 0 +Line 12585: 0 +Line 12586: 1 +Line 12587: 1 +Line 12588: 0 +Line 12589: 0 +Line 12590: 0 +Line 12591: 1 +Line 12592: 1 +Line 12593: 1 +Line 12594: 1 +Line 12595: 0 +Line 12596: 1 +Line 12597: 1 +Line 12598: 1 +Line 12599: 0 +Line 12600: 0 +Line 12601: 1 +Line 12602: 1 +Line 12603: 0 +Line 12604: 0 +Line 12605: 0 +Line 12606: 0 +Line 12607: 0 +Line 12608: 0 +Line 12609: 0 +Line 12610: 1 +Line 12611: 1 +Line 12612: 0 +Line 12613: 1 +Line 12614: 0 +Line 12615: 0 +Line 12616: 1 +Line 12617: 0 +Line 12618: 1 +Line 12619: 1 +Line 12620: 1 +Line 12621: 1 +Line 12622: 0 +Line 12623: 0 +Line 12624: 1 +Line 12625: 1 +Line 12626: 0 +Line 12627: 1 +Line 12628: 0 +Line 12629: 0 +Line 12630: 1 +Line 12631: 1 +Line 12632: 0 +Line 12633: 1 +Line 12634: 0 +Line 12635: 1 +Line 12636: 1 +Line 12637: 1 +Line 12638: 1 +Line 12639: 0 +Line 12640: 0 +Line 12641: 0 +Line 12642: 0 +Line 12643: 1 +Line 12644: 1 +Line 12645: 1 +Line 12646: 0 +Line 12647: 1 +Line 12648: 0 +Line 12649: 0 +Line 12650: 0 +Line 12651: 0 +Line 12652: 1 +Line 12653: 1 +Line 12654: 0 +Line 12655: 1 +Line 12656: 1 +Line 12657: 1 +Line 12658: 0 +Line 12659: 0 +Line 12660: 1 +Line 12661: 1 +Line 12662: 0 +Line 12663: 1 +Line 12664: 0 +Line 12665: 0 +Line 12666: 1 +Line 12667: 1 +Line 12668: 1 +Line 12669: 1 +Line 12670: 1 +Line 12671: 0 +Line 12672: 0 +Line 12673: 0 +Line 12674: 0 +Line 12675: 0 +Line 12676: 1 +Line 12677: 0 +Line 12678: 0 +Line 12679: 0 +Line 12680: 0 +Line 12681: 0 +Line 12682: 1 +Line 12683: 1 +Line 12684: 1 +Line 12685: 0 +Line 12686: 0 +Line 12687: 1 +Line 12688: 1 +Line 12689: 1 +Line 12690: 0 +Line 12691: 1 +Line 12692: 1 +Line 12693: 1 +Line 12694: 1 +Line 12695: 0 +Line 12696: 1 +Line 12697: 1 +Line 12698: 0 +Line 12699: 1 +Line 12700: 1 +Line 12701: 1 +Line 12702: 1 +Line 12703: 1 +Line 12704: 0 +Line 12705: 0 +Line 12706: 0 +Line 12707: 0 +Line 12708: 0 +Line 12709: 0 +Line 12710: 0 +Line 12711: 0 +Line 12712: 0 +Line 12713: 0 +Line 12714: 0 +Line 12715: 0 +Line 12716: 0 +Line 12717: 0 +Line 12718: 0 +Line 12719: 0 +Line 12720: 0 +Line 12721: 0 +Line 12722: 0 +Line 12723: 0 +Line 12724: 0 +Line 12725: 0 +Line 12726: 0 +Line 12727: 0 +Line 12728: 0 +Line 12729: 0 +Line 12730: 0 +Line 12731: 0 +Line 12732: 0 +Line 12733: 0 +Line 12734: 0 +Line 12735: 0 +Line 12736: 0 +Line 12737: 0 +Line 12738: 0 +Line 12739: 0 +Line 12740: 0 +Line 12741: 0 +Line 12742: 0 +Line 12743: 1 +Line 12744: 1 +Line 12745: 0 +Line 12746: 0 +Line 12747: 1 +Line 12748: 1 +Line 12749: 0 +Line 12750: 0 +Line 12751: 1 +Line 12752: 0 +Line 12753: 0 +Line 12754: 0 +Line 12755: 0 +Line 12756: 0 +Line 12757: 0 +Line 12758: 0 +Line 12759: 0 +Line 12760: 0 +Line 12761: 0 +Line 12762: 0 +Line 12763: 0 +Line 12764: 0 +Line 12765: 0 +Line 12766: 0 +Line 12767: 0 +Line 12768: 0 +Line 12769: 0 +Line 12770: 0 +Line 12771: 0 +Line 12772: 1 +Line 12773: 0 +Line 12774: 1 +Line 12775: 1 +Line 12776: 0 +Line 12777: 0 +Line 12778: 1 +Line 12779: 0 +Line 12780: 0 +Line 12781: 1 +Line 12782: 1 +Line 12783: 1 +Line 12784: 0 +Line 12785: 0 +Line 12786: 0 +Line 12787: 0 +Line 12788: 0 +Line 12789: 0 +Line 12790: 0 +Line 12791: 0 +Line 12792: 0 +Line 12793: 0 +Line 12794: 0 +Line 12795: 0 +Line 12796: 0 +Line 12797: 0 +Line 12798: 0 +Line 12799: 0 +Line 12800: 0 +Line 12801: 0 +Line 12802: 1 +Line 12803: 0 +Line 12804: 0 +Line 12805: 0 +Line 12806: 1 +Line 12807: 1 +Line 12808: 0 +Line 12809: 0 +Line 12810: 1 +Line 12811: 0 +Line 12812: 1 +Line 12813: 0 +Line 12814: 0 +Line 12815: 0 +Line 12816: 0 +Line 12817: 0 +Line 12818: 0 +Line 12819: 0 +Line 12820: 0 +Line 12821: 0 +Line 12822: 0 +Line 12823: 0 +Line 12824: 0 +Line 12825: 0 +Line 12826: 0 +Line 12827: 0 +Line 12828: 0 +Line 12829: 0 +Line 12830: 0 +Line 12831: 0 +Line 12832: 0 +Line 12833: 0 +Line 12834: 1 +Line 12835: 1 +Line 12836: 1 +Line 12837: 0 +Line 12838: 1 +Line 12839: 1 +Line 12840: 0 +Line 12841: 0 +Line 12842: 1 +Line 12843: 0 +Line 12844: 1 +Line 12845: 0 +Line 12846: 0 +Line 12847: 0 +Line 12848: 0 +Line 12849: 0 +Line 12850: 0 +Line 12851: 0 +Line 12852: 0 +Line 12853: 0 +Line 12854: 0 +Line 12855: 0 +Line 12856: 0 +Line 12857: 0 +Line 12858: 0 +Line 12859: 0 +Line 12860: 0 +Line 12861: 0 +Line 12862: 0 +Line 12863: 0 +Line 12864: 0 +Line 12865: 1 +Line 12866: 0 +Line 12867: 0 +Line 12868: 0 +Line 12869: 1 +Line 12870: 0 +Line 12871: 0 +Line 12872: 1 +Line 12873: 0 +Line 12874: 1 +Line 12875: 1 +Line 12876: 0 +Line 12877: 1 +Line 12878: 1 +Line 12879: 0 +Line 12880: 0 +Line 12881: 0 +Line 12882: 0 +Line 12883: 0 +Line 12884: 0 +Line 12885: 0 +Line 12886: 0 +Line 12887: 0 +Line 12888: 0 +Line 12889: 0 +Line 12890: 0 +Line 12891: 0 +Line 12892: 0 +Line 12893: 0 +Line 12894: 0 +Line 12895: 0 +Line 12896: 0 +Line 12897: 1 +Line 12898: 0 +Line 12899: 0 +Line 12900: 0 +Line 12901: 1 +Line 12902: 1 +Line 12903: 0 +Line 12904: 0 +Line 12905: 0 +Line 12906: 1 +Line 12907: 1 +Line 12908: 0 +Line 12909: 1 +Line 12910: 1 +Line 12911: 1 +Line 12912: 0 +Line 12913: 0 +Line 12914: 0 +Line 12915: 0 +Line 12916: 0 +Line 12917: 0 +Line 12918: 0 +Line 12919: 0 +Line 12920: 0 +Line 12921: 0 +Line 12922: 0 +Line 12923: 0 +Line 12924: 0 +Line 12925: 0 +Line 12926: 0 +Line 12927: 0 +Line 12928: 0 +Line 12929: 1 +Line 12930: 0 +Line 12931: 0 +Line 12932: 0 +Line 12933: 1 +Line 12934: 1 +Line 12935: 0 +Line 12936: 0 +Line 12937: 1 +Line 12938: 0 +Line 12939: 0 +Line 12940: 1 +Line 12941: 1 +Line 12942: 1 +Line 12943: 1 +Line 12944: 0 +Line 12945: 0 +Line 12946: 0 +Line 12947: 0 +Line 12948: 0 +Line 12949: 0 +Line 12950: 0 +Line 12951: 0 +Line 12952: 0 +Line 12953: 0 +Line 12954: 0 +Line 12955: 0 +Line 12956: 0 +Line 12957: 0 +Line 12958: 0 +Line 12959: 0 +Line 12960: 0 +Line 12961: 1 +Line 12962: 0 +Line 12963: 0 +Line 12964: 0 +Line 12965: 1 +Line 12966: 1 +Line 12967: 0 +Line 12968: 0 +Line 12969: 1 +Line 12970: 0 +Line 12971: 0 +Line 12972: 1 +Line 12973: 1 +Line 12974: 1 +Line 12975: 1 +Line 12976: 0 +Line 12977: 0 +Line 12978: 0 +Line 12979: 0 +Line 12980: 0 +Line 12981: 0 +Line 12982: 0 +Line 12983: 0 +Line 12984: 0 +Line 12985: 0 +Line 12986: 0 +Line 12987: 0 +Line 12988: 0 +Line 12989: 0 +Line 12990: 0 +Line 12991: 0 +Line 12992: 0 +Line 12993: 1 +Line 12994: 0 +Line 12995: 0 +Line 12996: 0 +Line 12997: 1 +Line 12998: 1 +Line 12999: 0 +Line 13000: 0 +Line 13001: 1 +Line 13002: 0 +Line 13003: 0 +Line 13004: 1 +Line 13005: 1 +Line 13006: 1 +Line 13007: 1 +Line 13008: 0 +Line 13009: 0 +Line 13010: 0 +Line 13011: 0 +Line 13012: 0 +Line 13013: 0 +Line 13014: 0 +Line 13015: 0 +Line 13016: 0 +Line 13017: 0 +Line 13018: 0 +Line 13019: 0 +Line 13020: 0 +Line 13021: 0 +Line 13022: 0 +Line 13023: 0 +Line 13024: 0 +Line 13025: 1 +Line 13026: 0 +Line 13027: 0 +Line 13028: 0 +Line 13029: 1 +Line 13030: 1 +Line 13031: 0 +Line 13032: 0 +Line 13033: 1 +Line 13034: 0 +Line 13035: 0 +Line 13036: 1 +Line 13037: 1 +Line 13038: 1 +Line 13039: 1 +Line 13040: 0 +Line 13041: 0 +Line 13042: 0 +Line 13043: 0 +Line 13044: 0 +Line 13045: 0 +Line 13046: 0 +Line 13047: 0 +Line 13048: 0 +Line 13049: 0 +Line 13050: 0 +Line 13051: 0 +Line 13052: 0 +Line 13053: 0 +Line 13054: 0 +Line 13055: 0 +Line 13056: 0 +Line 13057: 1 +Line 13058: 0 +Line 13059: 0 +Line 13060: 0 +Line 13061: 1 +Line 13062: 1 +Line 13063: 0 +Line 13064: 0 +Line 13065: 0 +Line 13066: 1 +Line 13067: 1 +Line 13068: 0 +Line 13069: 1 +Line 13070: 1 +Line 13071: 1 +Line 13072: 0 +Line 13073: 0 +Line 13074: 0 +Line 13075: 0 +Line 13076: 0 +Line 13077: 0 +Line 13078: 0 +Line 13079: 0 +Line 13080: 0 +Line 13081: 0 +Line 13082: 0 +Line 13083: 0 +Line 13084: 0 +Line 13085: 0 +Line 13086: 0 +Line 13087: 0 +Line 13088: 0 +Line 13089: 1 +Line 13090: 0 +Line 13091: 0 +Line 13092: 0 +Line 13093: 1 +Line 13094: 0 +Line 13095: 0 +Line 13096: 1 +Line 13097: 0 +Line 13098: 1 +Line 13099: 1 +Line 13100: 0 +Line 13101: 1 +Line 13102: 1 +Line 13103: 0 +Line 13104: 0 +Line 13105: 0 +Line 13106: 0 +Line 13107: 0 +Line 13108: 0 +Line 13109: 0 +Line 13110: 0 +Line 13111: 0 +Line 13112: 0 +Line 13113: 0 +Line 13114: 0 +Line 13115: 0 +Line 13116: 0 +Line 13117: 0 +Line 13118: 0 +Line 13119: 0 +Line 13120: 0 +Line 13121: 0 +Line 13122: 1 +Line 13123: 1 +Line 13124: 1 +Line 13125: 0 +Line 13126: 1 +Line 13127: 1 +Line 13128: 0 +Line 13129: 0 +Line 13130: 1 +Line 13131: 0 +Line 13132: 1 +Line 13133: 0 +Line 13134: 0 +Line 13135: 0 +Line 13136: 0 +Line 13137: 0 +Line 13138: 0 +Line 13139: 0 +Line 13140: 0 +Line 13141: 0 +Line 13142: 0 +Line 13143: 0 +Line 13144: 0 +Line 13145: 0 +Line 13146: 0 +Line 13147: 0 +Line 13148: 0 +Line 13149: 0 +Line 13150: 0 +Line 13151: 0 +Line 13152: 0 +Line 13153: 0 +Line 13154: 1 +Line 13155: 0 +Line 13156: 0 +Line 13157: 0 +Line 13158: 1 +Line 13159: 1 +Line 13160: 0 +Line 13161: 0 +Line 13162: 1 +Line 13163: 0 +Line 13164: 1 +Line 13165: 0 +Line 13166: 0 +Line 13167: 0 +Line 13168: 0 +Line 13169: 0 +Line 13170: 0 +Line 13171: 0 +Line 13172: 0 +Line 13173: 0 +Line 13174: 0 +Line 13175: 0 +Line 13176: 0 +Line 13177: 0 +Line 13178: 0 +Line 13179: 0 +Line 13180: 0 +Line 13181: 0 +Line 13182: 0 +Line 13183: 0 +Line 13184: 0 +Line 13185: 0 +Line 13186: 0 +Line 13187: 0 +Line 13188: 1 +Line 13189: 0 +Line 13190: 1 +Line 13191: 1 +Line 13192: 0 +Line 13193: 0 +Line 13194: 1 +Line 13195: 0 +Line 13196: 0 +Line 13197: 1 +Line 13198: 1 +Line 13199: 1 +Line 13200: 0 +Line 13201: 0 +Line 13202: 0 +Line 13203: 0 +Line 13204: 0 +Line 13205: 0 +Line 13206: 0 +Line 13207: 0 +Line 13208: 0 +Line 13209: 0 +Line 13210: 0 +Line 13211: 0 +Line 13212: 0 +Line 13213: 0 +Line 13214: 0 +Line 13215: 0 +Line 13216: 0 +Line 13217: 0 +Line 13218: 0 +Line 13219: 0 +Line 13220: 0 +Line 13221: 0 +Line 13222: 0 +Line 13223: 1 +Line 13224: 1 +Line 13225: 0 +Line 13226: 0 +Line 13227: 1 +Line 13228: 1 +Line 13229: 0 +Line 13230: 0 +Line 13231: 1 +Line 13232: 0 +Line 13233: 0 +Line 13234: 0 +Line 13235: 0 +Line 13236: 0 +Line 13237: 0 +Line 13238: 0 +Line 13239: 0 +Line 13240: 0 +Line 13241: 0 +Line 13242: 0 +Line 13243: 0 +Line 13244: 0 +Line 13245: 0 +Line 13246: 0 +Line 13247: 0 +Send READ_FILE + V C S S i m u l a t i o n R e p o r t +Time: 3202992000 ps diff --git a/tb/digital_top/simv b/tb/digital_top/simv new file mode 100644 index 0000000..be1a4b2 Binary files /dev/null and b/tb/digital_top/simv differ diff --git a/tb/digital_top/simv.daidir/.daidir_complete b/tb/digital_top/simv.daidir/.daidir_complete new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/simv.daidir/.normal_done b/tb/digital_top/simv.daidir/.normal_done new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/simv.daidir/.vcs.timestamp b/tb/digital_top/simv.daidir/.vcs.timestamp new file mode 100644 index 0000000..5d16b7f --- /dev/null +++ b/tb/digital_top/simv.daidir/.vcs.timestamp @@ -0,0 +1,232 @@ +0 +40 ++define+DUMP_FSDB ++itf+/home/synopsys/vcs/O-2018.09-SP2/linux64/lib/vcsdp_lite.tab ++lint=TFIPC-L ++nospecify ++v2k ++vcsd1 ++vpi +-Mamsrun= +-Masflags= +-Mcc=gcc +-Mcfl= -pipe -fPIC -O -I/home/synopsys/vcs/O-2018.09-SP2/include +-Mcplusplus=g++ +-Mcrt0= +-Mcrtn= +-Mcsrc= +-Mexternalobj= +-Mldflags= -rdynamic +-Mobjects= /home/synopsys/vcs/O-2018.09-SP2/linux64/lib/libvirsim.so /home/synopsys/vcs/O-2018.09-SP2/linux64/lib/liberrorinf.so /home/synopsys/vcs/O-2018.09-SP2/linux64/lib/libsnpsmalloc.so /home/synopsys/vcs/O-2018.09-SP2/linux64/lib/libvfs.so /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/pli.a +-Mout=simv +-Msaverestoreobj=/home/synopsys/vcs/O-2018.09-SP2/linux64/lib/vcs_save_restore_new.o +-Msyslibs=/home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/pli.a -ldl -lm +-Mvcsaceobjs= +-Mxcflags= -pipe -fPIC -I/home/synopsys/vcs/O-2018.09-SP2/include +-P +-P +-debug_access+all +-f files.f +-fsdb +-full64 +-gen_obj +-l +-lca +-picarchive +-q +-sverilog +-timescale=1ns/1ps +/home/synopsys/vcs/O-2018.09-SP2/linux64/bin/vcs1 +/home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +/home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +compile.log +76 +sysc_uni_pwd=/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/digital_top +XMODIFIERS=@im=ibus +XDG_VTNR=1 +XDG_SESSION_TYPE=x11 +XDG_SESSION_ID=1 +XDG_SESSION_DESKTOP=gnome-classic +XDG_SEAT=seat0 +XDG_RUNTIME_DIR=/run/user/1000 +XDG_MENU_PREFIX=gnome- +XDG_DATA_DIRS=/home/ICer/.local/share/flatpak/exports/share/:/var/lib/flatpak/exports/share/:/usr/local/share/:/usr/share/ +XDG_CURRENT_DESKTOP=GNOME-Classic:GNOME +XAUTHORITY=/run/gdm/auth-for-ICer-FQtMgs/database +WINDOWPATH=1 +VTE_VERSION=5204 +VMR_MODE_FLAG=64 +VERDI_HOME=/home/synopsys/verdi/Verdi_O-2018.09-SP2 +VCS_MODE_FLAG=64 +VCS_LOG_FILE=compile.log +VCS_LCAMSG_PRINT_OFF=1 +VCS_HOME=/home/synopsys/vcs/O-2018.09-SP2 +VCS_DEPTH=0 +VCS_ARG_ADDED_FOR_TMP=1 +VCS_ARCH_OVERRIDE=linux +VCS_ARCH=linux64 +USERNAME=ICer +UNAME=/bin/uname +TOOL_HOME=/home/synopsys/vcs/O-2018.09-SP2/linux64 +SSH_AUTH_SOCK=/run/user/1000/keyring/ssh +SSH_AGENT_PID=10423 +SPYGLASS_HOME=/home/synopsys/SpyGlass-L2016.06/SPYGLASS_HOME/ +SESSION_MANAGER=local/unix:@/tmp/.ICE-unix/10289,unix/unix:/tmp/.ICE-unix/10289 +SCRNAME=vcs +SCRIPT_NAME=vcs +SCL_HOME=/home/synopsys/scl/2018.06 +RISCV=/home/Riscv_Tools +QUESTASIM_HOME=/home/mentor/questasim +QT_PLUGIN_PATH=/usr/lib64/kde4/plugins:/usr/lib/kde4/plugins +QT_IM_MODULE=ibus +QT_GRAPHICSSYSTEM_CHECKED=1 +QTLIB=/usr/lib/qt-3.3/lib +QTINC=/usr/lib/qt-3.3/include +QTDIR=/usr/lib/qt-3.3 +QEMU_HOME=/home/Riscv_Tools/riscv-gnu-toolchain/qemu-6.0.0 +PT_HOME=/home/synopsys/pts/O-2018.06-SP1 +OVA_UUM=0 +MGLS_LICENSE_FILE=/home/mentor/questasim/mentor.dat +MFLAGS= +MAKE_TERMOUT=/dev/pts/3 +MAKE_TERMERR=/dev/pts/3 +MAKELEVEL=1 +MAKEFLAGS= +LESSOPEN=||/usr/bin/lesspipe.sh %s +LC_TIME=zh_CN.UTF-8 +LC_PAPER=zh_CN.UTF-8 +LC_NUMERIC=zh_CN.UTF-8 +LC_MONETARY=zh_CN.UTF-8 +LC_MEASUREMENT=zh_CN.UTF-8 +LC_HOME=/home/synopsys/lc/O-2018.06-SP1 +LC_ALL=C +KDEDIRS=/usr +IMSETTINGS_MODULE=none +IMSETTINGS_INTEGRATE_DESKTOP=yes +HISTCONTROL=ignoredups +GNOME_TERMINAL_SERVICE=:1.108 +GNOME_TERMINAL_SCREEN=/org/gnome/Terminal/screen/b3faae4f_07ba_4ce6_b83c_c942094b753b +GNOME_SHELL_SESSION_MODE=classic +GNOME_DESKTOP_SESSION_ID=this-is-deprecated +GDM_LANG=zh_CN.UTF-8 +GDMSESSION=gnome-classic +DVE_HOME=/home/synopsys/vcs/O-2018.09-SP2 +DESKTOP_SESSION=gnome-classic +DC_HOME=/home/synopsys/syn/O-2018.06-SP1 +DBUS_STARTER_BUS_TYPE=session +DBUS_STARTER_ADDRESS=unix:abstract=/tmp/dbus-DIYqQioq7q,guid=a50f166bc97a0937429a75936639b5b6 +DBUS_SESSION_BUS_ADDRESS=unix:abstract=/tmp/dbus-DIYqQioq7q,guid=a50f166bc97a0937429a75936639b5b6 +COLORTERM=truecolor +0 +103 +1715587843 qbmcu_undefines.v +1715564372 qbmcu_defines.v +1715825058 chip_undefine.v +1716628557 chip_define.v +1715584846 ../../sim/digital_top/spi_if.sv +1692987349 ../../sim/digital_top/clk_gen.v +1699539018 ../../sim/digital_top/DW02_mult.v +1692987348 ../../sim/digital_top/DW01_addsub.v +1699539018 ../../sim/digital_top/DW_mult_pipe.v +1716468015 ../../sim/digital_top/TB.sv +1715756264 ../../rtl/z_dsp/z_dsp.v +1715832037 ../../rtl/z_dsp/z_data_mux.v +1715747132 ../../rtl/z_dsp/TailCorr_top.v +1716445311 ../../rtl/z_dsp/mult_C.v +1716370622 ../../rtl/z_dsp/MeanIntp4_top.v +1716371209 ../../rtl/z_dsp/MeanIntp2.v +1716371241 ../../rtl/z_dsp/MeanIntp_s1.v +1716371346 ../../rtl/z_dsp/MeanIntp.v +1715681186 ../../rtl/z_dsp/lsdacif.v +1716445311 ../../rtl/z_dsp/IIR_Filter.v +1716370751 ../../rtl/z_dsp/diff.v +1715479955 ../../rtl/xy_dsp/qam/ssb.v +1715776566 ../../rtl/xy_dsp/qam/qam_top.v +1716260096 ../../rtl/xy_dsp/duc/duc4.v +1715336081 ../../rtl/xy_dsp/duc/duc_hb4_top_s3.v +1716371502 ../../rtl/xy_dsp/duc/duc_hb4_pipe_shift.v +1715336081 ../../rtl/xy_dsp/duc/duc_hb3_top_s2.v +1716371468 ../../rtl/xy_dsp/duc/duc_hb3_pipe_shift.v +1715336084 ../../rtl/xy_dsp/duc/duc_hb2_top_s.v +1716371436 ../../rtl/xy_dsp/duc/duc_hb2_pipe_shift.v +1715336084 ../../rtl/xy_dsp/duc/duc_hb1_top.v +1716371402 ../../rtl/xy_dsp/duc/duc_hb1_pipe_shift.v +1715488548 ../../rtl/xy_dsp/dsp_top/xy_dsp.v +1716378963 ../../rtl/xy_dsp/dacif/dacif.v +1716378911 ../../rtl/top/digital_top.sv +1716207913 ../../rtl/top/channel_top.sv +1715863673 ../../rtl/system_regfile/system_regfile.v +1715740446 ../../rtl/sync/sync_buf.sv +1716012464 ../../rtl/spi/spi_sys.v +1714632519 ../../rtl/spi/spi_slave.v +1716012606 ../../rtl/spi/spi_pll.v +1716628045 ../../rtl/spi/spi_bus_decoder.sv +1714632519 ../../rtl/rstgen/rst_sync.v +1715837885 ../../rtl/rstgen/rst_gen_unit.v +1716362658 ../../rtl/qubitmcu/qbmcu_wbck.v +1715587843 ../../rtl/qubitmcu/qbmcu_undefines.v +1715565068 ../../rtl/qubitmcu/qbmcu_regfile.v +1716388027 ../../rtl/qubitmcu/qbmcu_ifu.v +1716365241 ../../rtl/qubitmcu/qbmcu_fsm.v +1715565035 ../../rtl/qubitmcu/qbmcu_exu_lsuagu.v +1716378800 ../../rtl/qubitmcu/qbmcu_exu_ext.v +1716388041 ../../rtl/qubitmcu/qbmcu_exu_dpath.v +1715565006 ../../rtl/qubitmcu/qbmcu_exu_bjp.v +1715863407 ../../rtl/qubitmcu/qbmcu_exu_alu.v +1716388078 ../../rtl/qubitmcu/qbmcu_exu.v +1715564372 ../../rtl/qubitmcu/qbmcu_defines.v +1716378757 ../../rtl/qubitmcu/qbmcu_decode.v +1715564955 ../../rtl/qubitmcu/qbmcu_datalock.v +1716378701 ../../rtl/qubitmcu/qbmcu.v +1716295724 ../../rtl/perips/qbmcu_busdecoder.v +1715863339 ../../rtl/perips/mcu_regfile.sv +1714632519 ../../rtl/perips/DW03_updn_ctr.v +1714632519 ../../rtl/nco/sin_op.v +1714632519 ../../rtl/nco/pipe_add_48bit.v +1714632519 ../../rtl/nco/pipe_acc_48bit.v +1714632519 ../../rtl/nco/ph2amp.v +1715858907 ../../rtl/nco/p_nco_ch1.v +1714632519 ../../rtl/nco/p_nco.v +1714632519 ../../rtl/nco/nco_ch1.v +1715850409 ../../rtl/nco/nco.v +1714632519 ../../rtl/nco/cos_op.v +1714632519 ../../rtl/nco/coef_s.v +1714632519 ../../rtl/nco/coef_c.v +1716468135 ../../rtl/modem/freqmod.v +1716271781 ../../rtl/modem/baisset.v +1715823244 ../../rtl/modem/ampmod.v +1715909085 ../../rtl/memory/tsmc_dpram.v +1712728963 ../../rtl/memory/tsdn28hpcpuhdb64x32m4mw_170a_ffg0p99v0c.v +1714990733 ../../rtl/memory/tsdn28hpcpuhdb4096x32m4mwr_170a_ffg0p99v0c.v +1714632519 ../../rtl/memory/tsdn28hpcpuhdb4096x32m4mw_170a_ffg0p99v0c.v +1714632519 ../../rtl/memory/tsdn28hpcpuhdb128x128m4mw_170a_ffg0p99v0c.v +1715856272 ../../rtl/memory/sram_dmux.sv +1715687309 ../../rtl/memory/dpram_model.v +1715762418 ../../rtl/memory/dpram.v +1715825058 ../../rtl/define/chip_undefine.v +1716628532 ../../rtl/define/chip_define.v +1715908982 ../../rtl/debug/debug_top.sv +1715920037 ../../rtl/debug/debug_sample.sv +1715863256 ../../rtl/dac_regfile/dac_regfile.v +1714632519 ../../rtl/comm/sirv_gnrl_xchecker.v +1715740226 ../../rtl/comm/sirv_gnrl_dffs.v +1716378588 ../../rtl/clk/intpll_regfile.v +1715827745 ../../rtl/awg/modout_mux.v +1715653014 ../../rtl/awg/param_lut.sv +1716372692 ../../rtl/awg/ctrl_regfile.v +1714632519 ../../rtl/awg/codeword_decode.v +1716271976 ../../rtl/awg/awg_top.sv +1716261949 ../../rtl/awg/awg_ctrl.v +1714632519 ../../rtl/memory/sram_if.sv +1716289365 files.f +1550753332 /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +1550753332 /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +1551421246 /home/synopsys/vcs/O-2018.09-SP2/linux64/lib/vcsdp_lite.tab +5 +1551422344 /home/synopsys/vcs/O-2018.09-SP2/linux64/lib/libvirsim.so +1551421792 /home/synopsys/vcs/O-2018.09-SP2/linux64/lib/liberrorinf.so +1551421768 /home/synopsys/vcs/O-2018.09-SP2/linux64/lib/libsnpsmalloc.so +1551421789 /home/synopsys/vcs/O-2018.09-SP2/linux64/lib/libvfs.so +1550752033 /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/pli.a +1716628562 simv.daidir +-1 partitionlib diff --git a/tb/digital_top/simv.daidir/_3127_archive_1.so b/tb/digital_top/simv.daidir/_3127_archive_1.so new file mode 100644 index 0000000..124ddb2 Binary files /dev/null and b/tb/digital_top/simv.daidir/_3127_archive_1.so differ diff --git a/tb/digital_top/simv.daidir/_csrc0.so b/tb/digital_top/simv.daidir/_csrc0.so new file mode 100644 index 0000000..d16cd74 Binary files /dev/null and b/tb/digital_top/simv.daidir/_csrc0.so differ diff --git a/tb/digital_top/simv.daidir/_prev_archive_1.so b/tb/digital_top/simv.daidir/_prev_archive_1.so new file mode 100644 index 0000000..13e42bb Binary files /dev/null and b/tb/digital_top/simv.daidir/_prev_archive_1.so differ diff --git a/tb/digital_top/simv.daidir/binmap.sdb b/tb/digital_top/simv.daidir/binmap.sdb new file mode 100644 index 0000000..f4e9847 Binary files /dev/null and b/tb/digital_top/simv.daidir/binmap.sdb differ diff --git a/tb/digital_top/simv.daidir/build_db b/tb/digital_top/simv.daidir/build_db new file mode 100644 index 0000000..f0a2b99 --- /dev/null +++ b/tb/digital_top/simv.daidir/build_db @@ -0,0 +1,4 @@ +#!/bin/sh -e +# This file is automatically generated by VCS. Any changes you make +# to it will be overwritten the next time VCS is run. +vcs '-full64' '-sverilog' '+lint=TFIPC-L' '+v2k' '-debug_access+all' '+define+DUMP_FSDB' '-lca' '-q' '-timescale=1ns/1ps' '+nospecify' '-P' '/home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab' '/home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/pli.a' '-l' 'compile.log' '-f' 'files.f' -static_dbgen_only -daidir=$1 2>&1 diff --git a/tb/digital_top/simv.daidir/cc/cc_bcode.db b/tb/digital_top/simv.daidir/cc/cc_bcode.db new file mode 100644 index 0000000..0e2bc81 --- /dev/null +++ b/tb/digital_top/simv.daidir/cc/cc_bcode.db @@ -0,0 +1,992 @@ +sid spi_slave +bcid 0 0 WIDTH,1 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 RET +bcid 1 1 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,5 CALL_ARG_VAL,3,0 OPT_CONST,31 WIDTH,1 M_EQU AND RET +bcid 2 2 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,5 OPT_CONST,0 WIDTH,1 CALL_ARG_VAL,3,0 WIDTH,5 CALL_ARG_VAL,4,0 OPT_CONST,1 ADD CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 3 3 WIDTH,1 CALL_ARG_VAL,2,0 NOT CALL_ARG_VAL,3,0 WIDTH,5 CALL_ARG_VAL,4,0 OPT_CONST,26 WIDTH,1 M_EQU AND AND RET +bcid 4 4 WIDTH,1 CALL_ARG_VAL,2,0 NOT CALL_ARG_VAL,3,0 WIDTH,5 CALL_ARG_VAL,4,0 OPT_CONST,31 WIDTH,1 M_EQU AND AND RET +bcid 5 5 WIDTH,5 CALL_ARG_VAL,2,0 OPT_CONST,31 WIDTH,1 M_EQU WIDTH,5 CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 WIDTH,1 M_EQU AND RET +bcid 6 6 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,5 CALL_ARG_VAL,3,0 OPT_CONST,0 WIDTH,1 M_EQU AND RET +bcid 7 7 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,5 CALL_ARG_VAL,3,0 OPT_CONST,30 WIDTH,1 M_EQU CALL_ARG_VAL,4,0 AND AND RET +bcid 8 8 WIDTH,1 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 AND CALL_ARG_VAL,4,0 OR CALL_ARG_VAL,5,0 WIDTH,5 CALL_ARG_VAL,6,0 OPT_CONST,27 WIDTH,1 M_EQU AND AND RET +bcid 9 9 WIDTH,1 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 WIDTH,8 CALL_ARG_VAL,4,0 OPT_CONST,4 ADD CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 CALL_ARG_VAL,5,0 MITECONDNOINSTR,4 RET +bcid 10 10 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,0 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,31 WIDTH,1 SLICE,1 OPT_CONST,0 MITECONDNOINSTR,4 RET +bcid 11 11 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,1 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,30 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,0 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 12 12 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,2 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,29 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,1 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 13 13 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,3 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,28 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,2 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 14 14 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,4 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,27 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,3 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 15 15 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,5 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,26 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,4 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 16 16 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,6 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,25 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,5 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 17 17 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,7 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,24 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,6 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 18 18 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,8 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,23 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,7 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 19 19 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,9 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,22 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,8 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 20 20 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,10 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,21 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,9 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 21 21 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,11 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,20 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,10 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 22 22 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,12 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,19 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,11 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 23 23 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,13 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,18 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,12 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 24 24 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,14 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,17 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,13 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 25 25 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,15 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,16 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,14 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 26 26 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,16 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,15 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,15 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 27 27 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,17 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,14 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,16 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 28 28 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,18 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,13 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,17 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 29 29 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,19 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,12 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,18 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 30 30 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,20 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,11 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,19 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 31 31 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,21 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,10 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,20 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 32 32 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,22 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,9 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,21 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 33 33 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,23 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,8 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,22 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 34 34 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,24 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,7 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,23 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 35 35 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,25 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,6 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,24 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 36 36 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,26 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,5 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,25 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 37 37 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,27 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,4 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,26 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 38 38 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,28 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,3 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,27 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 39 39 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,29 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,2 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,28 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 40 40 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,30 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,1 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,29 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 41 41 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,31 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,0 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,30 WIDTH,1 SLICE,1 MITECONDNOINSTR,4 RET +bcid 42 42 WIDTH,2 CALL_ARG_VAL,2,0 OPT_CONST,1 WIDTH,1 M_EQU RET +bcid 43 43 WIDTH,2 CALL_ARG_VAL,2,0 OPT_CONST,2 WIDTH,1 M_EQU RET +bcid 44 44 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,5 CALL_ARG_VAL,3,0 OPT_CONST,31 WIDTH,1 M_EQU AND CALL_ARG_VAL,4,0 OR RET +bcid 45 45 WIDTH,2 CALL_ARG_VAL,2,0 OPT_CONST,1 WIDTH,1 M_EQU CALL_ARG_VAL,3,0 AND WIDTH,5 CALL_ARG_VAL,4,0 OPT_CONST,26 WIDTH,1 M_EQU AND RET +bcid 46 46 WIDTH,2 CALL_ARG_VAL,2,0 OPT_CONST,1 WIDTH,1 M_EQU CALL_ARG_VAL,3,0 WIDTH,5 CALL_ARG_VAL,4,0 OPT_CONST,30 WIDTH,1 M_EQU AND AND RET +bcid 47 47 WIDTH,5 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 WIDTH,1 M_EQU RET +bcid 48 48 WIDTH,5 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 WIDTH,1 M_NEQU RET +bcid 49 49 WIDTH,2 CALL_ARG_VAL,2,0 OPT_CONST,0 WIDTH,1 M_EQU CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 AND AND RET +bcid 50 50 WIDTH,2 CALL_ARG_VAL,2,0 OPT_CONST,1 WIDTH,1 M_EQU CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 AND AND RET +bcid 51 51 WIDTH,2 CALL_ARG_VAL,2,0 OPT_CONST,1 WIDTH,1 M_EQU CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 NOT CALL_ARG_VAL,5,0 AND AND AND RET +bcid 52 52 WIDTH,2 CALL_ARG_VAL,2,0 OPT_CONST,1 WIDTH,1 M_EQU CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 CALL_ARG_VAL,5,0 AND AND AND RET +bcid 53 53 WIDTH,2 CALL_ARG_VAL,2,0 OPT_CONST,2 WIDTH,1 M_EQU CALL_ARG_VAL,3,0 AND RET +bcid 54 54 WIDTH,2 CALL_ARG_VAL,2,0 OPT_CONST,3 WIDTH,1 M_EQU CALL_ARG_VAL,3,0 AND RET +bcid 55 55 WIDTH,2 CALL_ARG_VAL,2,0 OPT_CONST,0 WIDTH,1 M_EQU CALL_ARG_VAL,3,0 AND WIDTH,2 OPT_CONST,1 CALL_ARG_VAL,2,0 OPT_CONST,1 WIDTH,1 M_EQU CALL_ARG_VAL,4,0 AND WIDTH,2 OPT_CONST,0 CALL_ARG_VAL,2,0 OPT_CONST,1 WIDTH,1 M_EQU CALL_ARG_VAL,5,0 AND WIDTH,2 OPT_CONST,2 CALL_ARG_VAL,2,0 OPT_CONST,1 WIDTH,1 M_EQU CALL_ARG_VAL,6,0 AND WIDTH,2 OPT_CONST,3 CALL_ARG_VAL,2,0 OPT_CONST,2 WIDTH,1 M_EQU CALL_ARG_VAL,7,0 AND WIDTH,2 OPT_CONST,0 CALL_ARG_VAL,2,0 OPT_CONST,3 WIDTH,1 M_EQU CALL_ARG_VAL,8,0 AND WIDTH,2 OPT_CONST,0 CALL_ARG_VAL,2,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 56 56 WIDTH,2 CALL_ARG_VAL,2,0 OPT_CONST,3 WIDTH,1 M_EQU WIDTH,2 CALL_ARG_VAL,2,0 OPT_CONST,2 WIDTH,1 M_EQU CALL_ARG_VAL,3,0 AND OR CALL_ARG_VAL,4,0 WIDTH,5 CALL_ARG_VAL,5,0 OPT_CONST,27 WIDTH,1 M_EQU AND AND RET +bcid 57 57 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,25 OPT_CONST,0 WIDTH,1 CALL_ARG_VAL,3,0 WIDTH,25 CALL_ARG_VAL,4,0 WIDTH,1 CALL_ARG_VAL,5,0 WIDTH,25 CALL_ARG_VAL,6,0 OPT_CONST,4 ADD CALL_ARG_VAL,6,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 58 58 WIDTH,2 CALL_ARG_VAL,2,0 OPT_CONST,2 WIDTH,1 M_EQU CALL_ARG_VAL,3,0 WIDTH,5 CALL_ARG_VAL,4,0 OPT_CONST,31 WIDTH,1 M_EQU AND AND RET +bcid 59 59 WIDTH,1 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 WIDTH,5 CALL_ARG_VAL,4,0 OPT_CONST,28 WIDTH,1 M_EQU AND AND RET +bcid 60 60 WIDTH,1 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 WIDTH,5 CALL_ARG_VAL,4,0 OPT_CONST,30 WIDTH,1 M_EQU AND AND RET +bcid 61 61 WIDTH,1 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 WIDTH,5 CALL_ARG_VAL,4,0 OPT_CONST,31 WIDTH,1 M_EQU AND AND RET +bcid 62 62 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,32 CALL_ARG_VAL,3,0 WIDTH,2 CALL_ARG_VAL,4,0 OPT_CONST,3 WIDTH,1 M_EQU CALL_ARG_VAL,5,0 AND WIDTH,32 CALL_ARG_VAL,6,0 OPT_CONST,0 WIDTH,31 SLICE,1 WIDTH,1 OPT_CONST,0 WIDTH,32 CONCATENATE,2 CALL_ARG_VAL,6,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 63 63 WIDTH,2 CALL_ARG_VAL,2,0 OPT_CONST,3 WIDTH,1 M_EQU RET +sid system_regfile +bcid 64 0 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,6 WIDTH,26 SLICE,1 WIDTH,1 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,5,0 OPT_CONST,6 WIDTH,26 SLICE,1 WIDTH,1 CALL_ARG_VAL,6,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,7,0 OPT_CONST,6 WIDTH,26 SLICE,1 WIDTH,1 CALL_ARG_VAL,8,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,9,0 OPT_CONST,6 WIDTH,26 SLICE,1 WIDTH,1 CALL_ARG_VAL,10,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,11,0 OPT_CONST,6 WIDTH,26 SLICE,1 WIDTH,1 CALL_ARG_VAL,12,0 OPT_CONST,1 EQU WIDTH,26 OPT_CONST,0 WIDTH,1 CALL_ARG_VAL,13,0 OPT_CONST,1 EQU WIDTH,26 OPT_CONST,8423456 WIDTH,1 CALL_ARG_VAL,14,0 OPT_CONST,1 EQU WIDTH,26 OPT_CONST,22367569 WIDTH,1 CALL_ARG_VAL,15,0 OPT_CONST,1 EQU WIDTH,26 OPT_CONST,17128733 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 65 1 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 EQU WIDTH,6 CALL_ARG_VAL,3,0 WIDTH,1 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,5,0 OPT_CONST,0 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,6,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,7,0 OPT_CONST,0 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,8,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,9,0 OPT_CONST,0 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,10,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,11,0 OPT_CONST,0 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,12,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,13,0 OPT_CONST,0 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,14,0 OPT_CONST,1 EQU WIDTH,6 OPT_CONST,1 WIDTH,1 CALL_ARG_VAL,15,0 OPT_CONST,1 EQU WIDTH,6 OPT_CONST,49 WIDTH,1 CALL_ARG_VAL,16,0 OPT_CONST,1 EQU WIDTH,6 OPT_CONST,3 WIDTH,1 CALL_ARG_VAL,17,0 OPT_CONST,1 EQU WIDTH,6 OPT_CONST,3 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 66 2 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,0 WIDTH,1 M_EQU RET +bcid 67 3 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,1 WIDTH,1 M_EQU RET +bcid 68 4 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,2 WIDTH,1 M_EQU RET +bcid 69 5 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,3 WIDTH,1 M_EQU RET +bcid 70 6 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,4 WIDTH,1 M_EQU RET +bcid 71 7 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,5 WIDTH,1 M_EQU RET +bcid 72 8 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,6 WIDTH,1 M_EQU RET +bcid 73 9 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,16 WIDTH,1 M_EQU RET +bcid 74 10 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,7 WIDTH,1 M_EQU RET +bcid 75 11 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,8 WIDTH,1 M_EQU RET +bcid 76 12 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,9 WIDTH,1 M_EQU RET +bcid 77 13 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,10 WIDTH,1 M_EQU RET +bcid 78 14 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,11 WIDTH,1 M_EQU RET +bcid 79 15 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,12 WIDTH,1 M_EQU RET +bcid 80 16 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,13 WIDTH,1 M_EQU RET +bcid 81 17 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,32 CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 OPT_CONST,1 SUBTRACT WIDTH,1 M_EQU AND RET +bcid 82 18 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,0 WIDTH,1 CALL_ARG_VAL,3,0 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,1 ADD CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 83 19 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,0 WIDTH,1 M_NEQU RET +sid qbmcu_datalatch +bcid 84 0 WIDTH,1 CALL_ARG_VAL,2,0 NOT WIDTH,3 CALL_ARG_VAL,3,0 PARAMETER,4 WIDTH,1 M_EQU AND RET +bcid 85 1 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,32 MULTI_CONCATENATE,1,32 CALL_ARG_VAL,3,0 AND RET +bcid 86 2 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,19 MULTI_CONCATENATE,1,19 CALL_ARG_VAL,3,0 AND RET +sid qbmcu +bcid 87 0 WIDTH,1 CALL_ARG_VAL,2,0 NOT CALL_ARG_VAL,3,0 OR WIDTH,32 CALL_ARG_VAL,4,0 CALL_ARG_VAL,5,0 MITECONDNOINSTR,4 RET +bcid 88 1 WIDTH,1 CALL_ARG_VAL,2,0 NOT CALL_ARG_VAL,3,0 OR WIDTH,32 MULTI_CONCATENATE,1,32 NOT OPT_CONST,4 AND RET +bcid 89 2 WIDTH,32 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 ADD RET +bcid 90 3 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,1 WIDTH,31 SLICE,1 WIDTH,1 OPT_CONST,0 WIDTH,32 CONCATENATE,2 CALL_ARG_VAL,4,0 OPT_CONST,1 WIDTH,31 SLICE,1 WIDTH,1 OPT_CONST,0 WIDTH,32 CONCATENATE,2 MITECONDNOINSTR,4 RET +bcid 91 4 WIDTH,5 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,2 WIDTH,2 SLICE,1 OPT_CONST,0 WIDTH,1 M_EQU RET +bcid 92 5 WIDTH,5 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,2 WIDTH,2 SLICE,1 OPT_CONST,1 WIDTH,1 M_EQU RET +bcid 93 6 WIDTH,5 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,2 WIDTH,2 SLICE,1 OPT_CONST,2 WIDTH,1 M_EQU RET +bcid 94 7 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,0 WIDTH,1 SLICE,1 AND CALL_ARG_VAL,4,0 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,0 WIDTH,2 SLICE,1 OPT_CONST,0 WIDTH,1 M_NEQU AND OR RET +bcid 95 8 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,32 MULTI_CONCATENATE,1,32 WIDTH,8 CALL_ARG_VAL,3,0 WIDTH,32 MULTI_CONCATENATE,1,4 AND WIDTH,1 CALL_ARG_VAL,4,0 WIDTH,32 MULTI_CONCATENATE,1,32 WIDTH,16 CALL_ARG_VAL,5,0 WIDTH,32 MULTI_CONCATENATE,1,2 AND WIDTH,1 CALL_ARG_VAL,6,0 WIDTH,32 MULTI_CONCATENATE,1,32 CALL_ARG_VAL,7,0 AND OR OR RET +bcid 96 9 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,4 MULTI_CONCATENATE,1,4 OPT_CONST,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,0 WIDTH,2 SLICE,1 WIDTH,4 SHIFT_L AND WIDTH,1 CALL_ARG_VAL,4,0 WIDTH,4 MULTI_CONCATENATE,1,4 OPT_CONST,3 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,1 WIDTH,1 SLICE,1 OPT_CONST,0 WIDTH,2 CONCATENATE,2 WIDTH,4 SHIFT_L AND WIDTH,1 CALL_ARG_VAL,5,0 WIDTH,4 MULTI_CONCATENATE,1,4 OR OR RET +bcid 97 10 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,5 MULTI_CONCATENATE,1,5 CALL_ARG_VAL,3,0 AND RET +bcid 98 11 WIDTH,5 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,3 WIDTH,2 SLICE,1 OPT_CONST,0 WIDTH,1 M_NEQU RET +bcid 99 12 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,32 CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 RET +bcid 100 13 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,4 CALL_ARG_VAL,3,0 MITECONDNOINSTR,4 RET +bcid 101 14 WIDTH,9 CALL_ARG_VAL,2,0 OPT_CONST,257 AND OPT_CONST,0 WIDTH,1 M_NEQU RET +bcid 102 15 WIDTH,9 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 OPT_CONST,1 CALL_ARG_VAL,3,0 MITECONDNOINSTR,4 RET +bcid 103 16 WIDTH,9 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 RET +bcid 104 17 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,9 MULTI_CONCATENATE,1,9 CALL_ARG_VAL,3,0 AND RET +bcid 105 18 WIDTH,13 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,11 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 RET +bcid 106 19 WIDTH,13 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,10 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 RET +bcid 107 20 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,13 MULTI_CONCATENATE,1,13 CALL_ARG_VAL,3,0 AND RET +bcid 108 21 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,32 MULTI_CONCATENATE,1,32 WIDTH,10 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,4 WIDTH,1 SLICE,1 WIDTH,10 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,3 WIDTH,1 SLICE,1 OR WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,0 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,1 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,2 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,3 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,4 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,5 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,6 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,7 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,8 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,9 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,10 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,11 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,12 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,13 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,14 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,15 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,16 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,17 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,18 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,19 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,20 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,21 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,22 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,23 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,24 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,25 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,26 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,27 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,28 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,29 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,30 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,31 WIDTH,1 SLICE,1 WIDTH,32 CONCATENATE,32 CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 AND RET +bcid 109 22 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,5 MULTI_CONCATENATE,1,5 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,0 WIDTH,5 SLICE,1 AND RET +bcid 110 23 WIDTH,32 CALL_ARG_VAL,2,0 WIDTH,5 CALL_ARG_VAL,3,0 WIDTH,32 SHIFT_L RET +bcid 111 24 WIDTH,32 OPT_CONST,-1 WIDTH,5 CALL_ARG_VAL,2,0 WIDTH,32 SHIFT_R RET +bcid 112 25 WIDTH,32 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 AND CALL_ARG_VAL,4,0 OPT_CONST,31 WIDTH,1 SLICE,1 WIDTH,32 MULTI_CONCATENATE,1,32 CALL_ARG_VAL,3,0 NOT AND OR RET +bcid 113 26 WIDTH,1 CALL_ARG_VAL,2,0 NOT WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,31 WIDTH,1 SLICE,1 AND WIDTH,32 CALL_ARG_VAL,3,0 WIDTH,33 CONCATENATE,2 RET +bcid 114 27 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,33 MULTI_CONCATENATE,1,33 CALL_ARG_VAL,3,0 AND RET +bcid 115 28 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,33 MULTI_CONCATENATE,1,33 WIDTH,1 CALL_ARG_VAL,3,0 WIDTH,33 CALL_ARG_VAL,4,0 NOT CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 AND RET +bcid 116 29 WIDTH,33 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 WIDTH,1 CALL_ARG_VAL,4,0 WIDTH,33 PAD ADD ADD RET +bcid 117 30 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,32 MULTI_CONCATENATE,1,32 CALL_ARG_VAL,3,0 AND RET +bcid 118 31 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,0 WIDTH,1 M_NEQU RET +bcid 119 32 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,32 MULTI_CONCATENATE,1,32 OPT_CONST,1 AND RET +bcid 120 33 WIDTH,10 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,5 WIDTH,1 SLICE,1 WIDTH,32 MULTI_CONCATENATE,1,32 CALL_ARG_VAL,3,0 AND WIDTH,10 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,6 WIDTH,1 SLICE,1 WIDTH,32 MULTI_CONCATENATE,1,32 CALL_ARG_VAL,4,0 AND OR WIDTH,10 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 WIDTH,32 MULTI_CONCATENATE,1,32 CALL_ARG_VAL,5,0 AND WIDTH,1 CALL_ARG_VAL,6,0 WIDTH,32 MULTI_CONCATENATE,1,32 WIDTH,33 CALL_ARG_VAL,7,0 WIDTH,32 OPT_CONST,0 SLICE,1 AND OR OR WIDTH,10 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,3 WIDTH,1 SLICE,1 WIDTH,32 MULTI_CONCATENATE,1,32 CALL_ARG_VAL,8,0 AND WIDTH,10 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,2 WIDTH,1 SLICE,1 WIDTH,32 MULTI_CONCATENATE,1,32 CALL_ARG_VAL,9,0 AND OR WIDTH,10 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,4 WIDTH,1 SLICE,1 WIDTH,32 MULTI_CONCATENATE,1,32 CALL_ARG_VAL,10,0 AND WIDTH,10 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,9 WIDTH,1 SLICE,1 WIDTH,32 MULTI_CONCATENATE,1,32 CALL_ARG_VAL,11,0 AND WIDTH,1 CALL_ARG_VAL,12,0 WIDTH,32 MULTI_CONCATENATE,1,32 CALL_ARG_VAL,13,0 AND OR OR OR OR RET +bcid 121 34 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,32 MULTI_CONCATENATE,1,32 CALL_ARG_VAL,3,0 AND WIDTH,1 CALL_ARG_VAL,4,0 WIDTH,32 MULTI_CONCATENATE,1,32 CALL_ARG_VAL,5,0 AND OR RET +bcid 122 35 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,32 MULTI_CONCATENATE,1,32 CALL_ARG_VAL,3,0 AND WIDTH,1 CALL_ARG_VAL,4,0 WIDTH,32 MULTI_CONCATENATE,1,32 CALL_ARG_VAL,5,0 AND OR WIDTH,1 CALL_ARG_VAL,6,0 WIDTH,32 MULTI_CONCATENATE,1,32 CALL_ARG_VAL,7,0 AND WIDTH,1 CALL_ARG_VAL,8,0 WIDTH,32 MULTI_CONCATENATE,1,32 CALL_ARG_VAL,9,0 AND OR OR RET +bcid 123 36 WIDTH,3 CALL_ARG_VAL,2,0 OPT_CONST,0 WIDTH,1 M_EQU CALL_ARG_VAL,3,0 AND WIDTH,3 OPT_CONST,1 CALL_ARG_VAL,2,0 OPT_CONST,1 WIDTH,1 M_EQU CALL_ARG_VAL,4,0 AND WIDTH,3 OPT_CONST,2 CALL_ARG_VAL,2,0 OPT_CONST,2 WIDTH,1 M_EQU CALL_ARG_VAL,5,0 AND WIDTH,3 OPT_CONST,3 CALL_ARG_VAL,2,0 OPT_CONST,3 WIDTH,1 M_EQU CALL_ARG_VAL,6,0 AND WIDTH,3 OPT_CONST,0 CALL_ARG_VAL,2,0 OPT_CONST,3 WIDTH,1 M_EQU CALL_ARG_VAL,7,0 AND WIDTH,3 OPT_CONST,1 CALL_ARG_VAL,2,0 OPT_CONST,3 WIDTH,1 M_EQU CALL_ARG_VAL,8,0 AND WIDTH,3 OPT_CONST,4 CALL_ARG_VAL,2,0 OPT_CONST,4 WIDTH,1 M_EQU CALL_ARG_VAL,9,0 AND WIDTH,3 OPT_CONST,1 CALL_ARG_VAL,2,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 124 37 WIDTH,3 CALL_ARG_VAL,2,0 OPT_CONST,0 WIDTH,1 M_EQU CALL_ARG_VAL,3,0 AND RET +bcid 125 38 WIDTH,3 CALL_ARG_VAL,2,0 OPT_CONST,1 WIDTH,1 M_EQU RET +bcid 126 39 WIDTH,3 CALL_ARG_VAL,2,0 OPT_CONST,2 WIDTH,1 M_EQU RET +bcid 127 40 WIDTH,3 CALL_ARG_VAL,2,0 OPT_CONST,3 WIDTH,1 M_EQU CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 CALL_ARG_VAL,5,0 OR CALL_ARG_VAL,6,0 OR OR NOT AND RET +bcid 128 41 WIDTH,3 CALL_ARG_VAL,2,0 OPT_CONST,3 WIDTH,1 M_EQU CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 CALL_ARG_VAL,5,0 OR CALL_ARG_VAL,6,0 OR NOT AND AND RET +bcid 129 42 WIDTH,3 CALL_ARG_VAL,2,0 OPT_CONST,3 WIDTH,1 M_EQU CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 CALL_ARG_VAL,5,0 OR OR AND RET +bcid 130 43 WIDTH,3 CALL_ARG_VAL,2,0 OPT_CONST,4 WIDTH,1 M_EQU CALL_ARG_VAL,3,0 AND RET +bcid 131 44 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,0 WIDTH,2 SLICE,1 OPT_CONST,0 WIDTH,1 M_EQU RET +bcid 132 45 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,0 WIDTH,2 SLICE,1 OPT_CONST,1 WIDTH,1 M_EQU RET +bcid 133 46 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,0 WIDTH,2 SLICE,1 OPT_CONST,2 WIDTH,1 M_EQU RET +bcid 134 47 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,0 WIDTH,2 SLICE,1 OPT_CONST,3 WIDTH,1 M_EQU RET +bcid 135 48 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,2 WIDTH,3 SLICE,1 OPT_CONST,7 WIDTH,1 M_NEQU CALL_ARG_VAL,3,0 AND RET +bcid 136 49 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,2 WIDTH,3 SLICE,1 OPT_CONST,0 WIDTH,1 M_EQU RET +bcid 137 50 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,2 WIDTH,3 SLICE,1 OPT_CONST,1 WIDTH,1 M_EQU RET +bcid 138 51 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,2 WIDTH,3 SLICE,1 OPT_CONST,2 WIDTH,1 M_EQU RET +bcid 139 52 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,2 WIDTH,3 SLICE,1 OPT_CONST,3 WIDTH,1 M_EQU RET +bcid 140 53 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,2 WIDTH,3 SLICE,1 OPT_CONST,4 WIDTH,1 M_EQU RET +bcid 141 54 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,2 WIDTH,3 SLICE,1 OPT_CONST,5 WIDTH,1 M_EQU RET +bcid 142 55 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,2 WIDTH,3 SLICE,1 OPT_CONST,6 WIDTH,1 M_EQU RET +bcid 143 56 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,2 WIDTH,3 SLICE,1 OPT_CONST,7 WIDTH,1 M_EQU RET +bcid 144 57 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,5 WIDTH,2 SLICE,1 OPT_CONST,0 WIDTH,1 M_EQU RET +bcid 145 58 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,5 WIDTH,2 SLICE,1 OPT_CONST,1 WIDTH,1 M_EQU RET +bcid 146 59 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,5 WIDTH,2 SLICE,1 OPT_CONST,2 WIDTH,1 M_EQU RET +bcid 147 60 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,5 WIDTH,2 SLICE,1 OPT_CONST,3 WIDTH,1 M_EQU RET +bcid 148 61 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,25 WIDTH,7 SLICE,1 OPT_CONST,0 WIDTH,1 M_EQU RET +bcid 149 62 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,25 WIDTH,7 SLICE,1 OPT_CONST,32 WIDTH,1 M_EQU RET +bcid 150 63 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,25 WIDTH,7 SLICE,1 OPT_CONST,127 WIDTH,1 M_EQU RET +bcid 151 64 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,15 WIDTH,5 SLICE,1 OPT_CONST,0 WIDTH,1 M_EQU RET +bcid 152 65 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,20 WIDTH,5 SLICE,1 OPT_CONST,0 WIDTH,1 M_EQU RET +bcid 153 66 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,20 WIDTH,5 SLICE,1 OPT_CONST,1 WIDTH,1 M_EQU RET +bcid 154 67 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,7 WIDTH,5 SLICE,1 OPT_CONST,0 WIDTH,1 M_EQU RET +bcid 155 68 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,7 WIDTH,5 SLICE,1 OPT_CONST,2 WIDTH,1 M_EQU RET +bcid 156 69 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,15 WIDTH,5 SLICE,1 OPT_CONST,31 WIDTH,1 M_EQU RET +bcid 157 70 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,20 WIDTH,5 SLICE,1 OPT_CONST,31 WIDTH,1 M_EQU RET +bcid 158 71 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,7 WIDTH,5 SLICE,1 OPT_CONST,31 WIDTH,1 M_EQU RET +bcid 159 72 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,8 CALL_ARG_VAL,3,0 OPT_CONST,129 AND OPT_CONST,0 WIDTH,1 M_NEQU OR RET +bcid 160 73 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,4 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,26 WIDTH,6 SLICE,1 OPT_CONST,0 WIDTH,1 M_EQU AND AND RET +bcid 161 74 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,4 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,3 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,26 WIDTH,6 SLICE,1 OPT_CONST,0 WIDTH,1 M_EQU AND AND RET +bcid 162 75 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,4 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,3 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,26 WIDTH,6 SLICE,1 OPT_CONST,16 WIDTH,1 M_EQU AND AND RET +bcid 163 76 WIDTH,8 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,1 WIDTH,3 SLICE,1 OPT_CONST,0 WIDTH,1 M_NEQU CALL_ARG_VAL,3,0 NOT AND RET +bcid 164 77 WIDTH,1 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 AND CALL_ARG_VAL,4,0 WIDTH,32 CALL_ARG_VAL,5,0 OPT_CONST,20 WIDTH,12 SLICE,1 OPT_CONST,0 WIDTH,1 M_EQU AND AND RET +bcid 165 78 WIDTH,1 CALL_ARG_VAL,2,0 NOT CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 OR WIDTH,4 CALL_ARG_VAL,5,0 OPT_CONST,13 AND OPT_CONST,0 WIDTH,1 M_NEQU OR AND RET +bcid 166 79 WIDTH,6 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 OPT_CONST,0 WIDTH,1 M_NEQU RET +bcid 167 80 WIDTH,1 CALL_ARG_VAL,2,0 NOT WIDTH,5 CALL_ARG_VAL,3,0 OPT_CONST,0 WIDTH,1 M_NEQU AND RET +bcid 168 81 WIDTH,1 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 AND CALL_ARG_VAL,4,0 WIDTH,4 CALL_ARG_VAL,5,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 AND AND CALL_ARG_VAL,6,0 CALL_ARG_VAL,7,0 AND CALL_ARG_VAL,8,0 WIDTH,32 CALL_ARG_VAL,9,0 OPT_CONST,0 WIDTH,2 SLICE,1 OPT_CONST,0 WIDTH,1 M_EQU AND AND AND RET +bcid 169 82 WIDTH,1 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 AND CALL_ARG_VAL,4,0 WIDTH,4 CALL_ARG_VAL,5,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 AND AND CALL_ARG_VAL,6,0 CALL_ARG_VAL,7,0 AND CALL_ARG_VAL,8,0 WIDTH,32 CALL_ARG_VAL,9,0 OPT_CONST,0 WIDTH,2 SLICE,1 OPT_CONST,3 WIDTH,1 M_EQU AND AND AND RET +bcid 170 83 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,31 WIDTH,1 SLICE,1 WIDTH,20 MULTI_CONCATENATE,1,20 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,20 WIDTH,12 SLICE,1 WIDTH,32 CONCATENATE,2 RET +bcid 171 84 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,31 WIDTH,1 SLICE,1 WIDTH,20 MULTI_CONCATENATE,1,20 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,25 WIDTH,7 SLICE,1 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,7 WIDTH,5 SLICE,1 WIDTH,32 CONCATENATE,3 RET +bcid 172 85 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,31 WIDTH,1 SLICE,1 WIDTH,20 MULTI_CONCATENATE,1,20 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,7 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,25 WIDTH,6 SLICE,1 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,8 WIDTH,4 SLICE,1 WIDTH,1 OPT_CONST,0 WIDTH,32 CONCATENATE,5 RET +bcid 173 86 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,31 WIDTH,1 SLICE,1 WIDTH,12 MULTI_CONCATENATE,1,12 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,12 WIDTH,8 SLICE,1 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,20 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,21 WIDTH,10 SLICE,1 WIDTH,1 OPT_CONST,0 WIDTH,32 CONCATENATE,5 RET +bcid 174 87 WIDTH,4 CALL_ARG_VAL,2,0 OPT_CONST,5 AND OPT_CONST,0 WIDTH,1 M_NEQU RET +bcid 175 88 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,32 MULTI_CONCATENATE,1,32 CALL_ARG_VAL,3,0 AND WIDTH,1 CALL_ARG_VAL,4,0 WIDTH,32 MULTI_CONCATENATE,1,32 CALL_ARG_VAL,5,0 AND WIDTH,1 CALL_ARG_VAL,6,0 WIDTH,32 MULTI_CONCATENATE,1,32 CALL_ARG_VAL,7,0 AND OR OR WIDTH,1 CALL_ARG_VAL,8,0 WIDTH,32 MULTI_CONCATENATE,1,32 CALL_ARG_VAL,9,0 AND WIDTH,1 CALL_ARG_VAL,10,0 WIDTH,32 MULTI_CONCATENATE,1,32 CALL_ARG_VAL,11,0 AND WIDTH,1 CALL_ARG_VAL,12,0 WIDTH,32 MULTI_CONCATENATE,1,32 CALL_ARG_VAL,13,0 AND OR OR OR RET +bcid 176 89 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,19 MULTI_CONCATENATE,1,19 WIDTH,1 OPT_CONST,0 WIDTH,18 CALL_ARG_VAL,3,0 WIDTH,19 CONCATENATE,2 AND WIDTH,1 CALL_ARG_VAL,4,0 WIDTH,19 MULTI_CONCATENATE,1,19 WIDTH,9 OPT_CONST,0 WIDTH,10 CALL_ARG_VAL,5,0 WIDTH,19 CONCATENATE,2 AND OR WIDTH,1 CALL_ARG_VAL,6,0 WIDTH,19 MULTI_CONCATENATE,1,19 WIDTH,6 OPT_CONST,0 WIDTH,13 CALL_ARG_VAL,7,0 WIDTH,19 CONCATENATE,2 AND WIDTH,1 CALL_ARG_VAL,8,0 WIDTH,19 MULTI_CONCATENATE,1,19 WIDTH,9 OPT_CONST,0 WIDTH,10 CALL_ARG_VAL,9,0 WIDTH,19 CONCATENATE,2 AND OR OR RET +bcid 177 90 WIDTH,1 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 AND WIDTH,4 MULTI_CONCATENATE,1,4 CALL_ARG_VAL,4,0 AND RET +bcid 178 91 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,4 MULTI_CONCATENATE,1,4 CALL_ARG_VAL,3,0 AND RET +bcid 179 92 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,2 MULTI_CONCATENATE,1,2 WIDTH,4 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,0 WIDTH,2 SLICE,1 AND RET +bcid 180 93 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,4 MULTI_CONCATENATE,1,4 CALL_ARG_VAL,3,0 AND RET +bcid 181 94 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,2 MULTI_CONCATENATE,1,2 WIDTH,4 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,0 WIDTH,2 SLICE,1 AND RET +bcid 182 95 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,2 MULTI_CONCATENATE,1,2 WIDTH,4 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,2 WIDTH,2 SLICE,1 AND RET +bcid 183 96 WIDTH,1 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 WIDTH,32 CALL_ARG_VAL,5,0 OPT_CONST,-1 SUBTRACT CALL_ARG_VAL,5,0 OPT_CONST,-1 ADD MITECONDNOINSTR,4 CALL_ARG_VAL,5,0 MITECONDNOINSTR,4 CALL_ARG_VAL,6,0 NOT NOT MITECONDNOINSTR,4 RET +bcid 184 97 WIDTH,32 CALL_ARG_VAL,2,0 WIDTH,1 CALL_ARG_VAL,3,0 WIDTH,32 MULTI_CONCATENATE,1,32 WIDTH,1 M_EQU RET +bcid 185 98 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,1 SUBTRACT RET +bcid 186 99 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,10 MULTI_CONCATENATE,1,10 CALL_ARG_VAL,3,0 AND RET +bcid 187 100 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,6 MULTI_CONCATENATE,1,6 CALL_ARG_VAL,3,0 AND RET +sid qbmcu_busdecoder +bcid 188 0 WIDTH,16 CALL_ARG_VAL,2,0 OPT_CONST,16 WIDTH,1 M_EQU RET +bcid 189 1 WIDTH,16 CALL_ARG_VAL,2,0 OPT_CONST,32 WIDTH,1 M_EQU RET +bcid 190 2 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,4 MULTI_CONCATENATE,1,4 CALL_ARG_VAL,3,0 AND RET +bcid 191 3 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,32 MULTI_CONCATENATE,1,32 CALL_ARG_VAL,3,0 AND RET +bcid 192 4 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,32 MULTI_CONCATENATE,1,32 CALL_ARG_VAL,3,0 AND WIDTH,1 CALL_ARG_VAL,4,0 WIDTH,32 MULTI_CONCATENATE,1,32 CALL_ARG_VAL,5,0 AND OR RET +sid mcu_regfile +bcid 193 0 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,4,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,5,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,6,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,7,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,8,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,9,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,10,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,11,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,12,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,13,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,14,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,15,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,16,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,17,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,18,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,19,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,20,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,21,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,22,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,23,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,24,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,25,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,26,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU CALL_ARG_VAL,27,0 CALL_ARG_VAL,28,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,29,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,30,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,31,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,32,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,33,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,34,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,35,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,36,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,37,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,38,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,39,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,40,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,41,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,42,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,43,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,44,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,45,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,46,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,47,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,48,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,49,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,50,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,51,0 OPT_CONST,0 WIDTH,1 SLICE,1 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 194 1 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,2 WIDTH,14 SLICE,1 WIDTH,1 CALL_ARG_VAL,4,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,5,0 WIDTH,32 OPT_CONST,2 WIDTH,14 SLICE,1 WIDTH,1 CALL_ARG_VAL,6,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,7,0 WIDTH,32 OPT_CONST,2 WIDTH,14 SLICE,1 WIDTH,1 CALL_ARG_VAL,8,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,9,0 WIDTH,32 OPT_CONST,2 WIDTH,14 SLICE,1 WIDTH,1 CALL_ARG_VAL,10,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,11,0 WIDTH,32 OPT_CONST,2 WIDTH,14 SLICE,1 WIDTH,1 CALL_ARG_VAL,12,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,13,0 WIDTH,32 OPT_CONST,2 WIDTH,14 SLICE,1 WIDTH,1 CALL_ARG_VAL,14,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,15,0 WIDTH,32 OPT_CONST,2 WIDTH,14 SLICE,1 WIDTH,1 CALL_ARG_VAL,16,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,17,0 WIDTH,32 OPT_CONST,2 WIDTH,14 SLICE,1 WIDTH,1 CALL_ARG_VAL,18,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,19,0 WIDTH,32 OPT_CONST,2 WIDTH,14 SLICE,1 WIDTH,1 CALL_ARG_VAL,20,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,21,0 WIDTH,32 OPT_CONST,2 WIDTH,14 SLICE,1 WIDTH,1 CALL_ARG_VAL,22,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,23,0 WIDTH,32 OPT_CONST,2 WIDTH,14 SLICE,1 WIDTH,1 CALL_ARG_VAL,24,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,25,0 WIDTH,32 OPT_CONST,2 WIDTH,14 SLICE,1 WIDTH,1 CALL_ARG_VAL,26,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,27,0 WIDTH,32 OPT_CONST,2 WIDTH,14 SLICE,1 WIDTH,1 CALL_ARG_VAL,28,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,29,0 OPT_CONST,2 WIDTH,14 SLICE,1 WIDTH,1 CALL_ARG_VAL,30,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,31,0 OPT_CONST,2 WIDTH,14 SLICE,1 WIDTH,1 CALL_ARG_VAL,32,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,33,0 OPT_CONST,2 WIDTH,14 SLICE,1 WIDTH,1 CALL_ARG_VAL,34,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,35,0 OPT_CONST,2 WIDTH,14 SLICE,1 WIDTH,1 CALL_ARG_VAL,36,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,37,0 OPT_CONST,2 WIDTH,14 SLICE,1 WIDTH,1 CALL_ARG_VAL,38,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,39,0 OPT_CONST,2 WIDTH,14 SLICE,1 WIDTH,1 CALL_ARG_VAL,40,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,41,0 OPT_CONST,2 WIDTH,14 SLICE,1 WIDTH,1 CALL_ARG_VAL,42,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,43,0 OPT_CONST,2 WIDTH,14 SLICE,1 WIDTH,1 CALL_ARG_VAL,44,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,45,0 OPT_CONST,2 WIDTH,14 SLICE,1 WIDTH,1 CALL_ARG_VAL,46,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,47,0 OPT_CONST,2 WIDTH,14 SLICE,1 WIDTH,1 CALL_ARG_VAL,48,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,49,0 OPT_CONST,2 WIDTH,14 SLICE,1 WIDTH,1 CALL_ARG_VAL,50,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,51,0 OPT_CONST,2 WIDTH,14 SLICE,1 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 195 2 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,4,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,5,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,6,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,7,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,8,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,9,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,10,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,11,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,12,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,13,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,14,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,15,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,16,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,17,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,18,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,19,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,20,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,21,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,22,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,23,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,24,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,25,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,26,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,27,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,28,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,29,0 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,30,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,31,0 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,32,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,33,0 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,34,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,35,0 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,36,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,37,0 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,38,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,39,0 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,40,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,41,0 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,42,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,43,0 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,44,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,45,0 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,46,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,47,0 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,48,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,49,0 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,50,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,51,0 OPT_CONST,1 WIDTH,1 SLICE,1 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 196 3 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,16 WIDTH,16 SLICE,1 WIDTH,1 CALL_ARG_VAL,4,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,5,0 OPT_CONST,16 WIDTH,16 SLICE,1 WIDTH,1 CALL_ARG_VAL,6,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,7,0 OPT_CONST,16 WIDTH,16 SLICE,1 WIDTH,1 CALL_ARG_VAL,8,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,9,0 OPT_CONST,16 WIDTH,16 SLICE,1 WIDTH,1 CALL_ARG_VAL,10,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,11,0 OPT_CONST,16 WIDTH,16 SLICE,1 WIDTH,1 CALL_ARG_VAL,12,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,13,0 OPT_CONST,16 WIDTH,16 SLICE,1 WIDTH,1 CALL_ARG_VAL,14,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,15,0 OPT_CONST,16 WIDTH,16 SLICE,1 WIDTH,1 CALL_ARG_VAL,16,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,17,0 OPT_CONST,16 WIDTH,16 SLICE,1 WIDTH,1 CALL_ARG_VAL,18,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,19,0 OPT_CONST,16 WIDTH,16 SLICE,1 WIDTH,1 CALL_ARG_VAL,20,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,21,0 OPT_CONST,16 WIDTH,16 SLICE,1 WIDTH,1 CALL_ARG_VAL,22,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,23,0 OPT_CONST,16 WIDTH,16 SLICE,1 WIDTH,1 CALL_ARG_VAL,24,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,25,0 OPT_CONST,16 WIDTH,16 SLICE,1 WIDTH,1 CALL_ARG_VAL,26,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,27,0 OPT_CONST,16 WIDTH,16 SLICE,1 WIDTH,1 CALL_ARG_VAL,28,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,29,0 OPT_CONST,16 WIDTH,16 SLICE,1 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 197 4 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,2 WIDTH,14 SLICE,1 WIDTH,1 CALL_ARG_VAL,4,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,5,0 OPT_CONST,2 WIDTH,14 SLICE,1 WIDTH,1 CALL_ARG_VAL,6,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,7,0 WIDTH,32 OPT_CONST,2 WIDTH,14 SLICE,1 WIDTH,1 CALL_ARG_VAL,8,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,9,0 WIDTH,32 OPT_CONST,2 WIDTH,14 SLICE,1 WIDTH,1 CALL_ARG_VAL,10,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,11,0 WIDTH,32 OPT_CONST,2 WIDTH,14 SLICE,1 WIDTH,1 CALL_ARG_VAL,12,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,13,0 WIDTH,32 OPT_CONST,2 WIDTH,14 SLICE,1 CALL_ARG_VAL,14,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 198 5 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,2 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,4,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,2 CALL_ARG_VAL,5,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,6,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,7,0 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,8,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,9,0 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,10,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,11,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,12,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,13,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,14,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,15,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,16,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,17,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,18,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 199 6 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,2 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,4,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,2 CALL_ARG_VAL,5,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,6,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,7,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,8,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,9,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,10,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,11,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,12,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,13,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,14,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,15,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,16,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,17,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,18,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,19,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,20,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 200 7 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,0 WIDTH,1 M_EQU RET +bcid 201 8 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,1 WIDTH,1 M_EQU RET +bcid 202 9 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,2 WIDTH,1 M_EQU RET +bcid 203 10 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,3 WIDTH,1 M_EQU RET +bcid 204 11 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,4 WIDTH,1 M_EQU RET +bcid 205 12 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,5 WIDTH,1 M_EQU RET +bcid 206 13 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,6 WIDTH,1 M_EQU RET +bcid 207 14 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,7 WIDTH,1 M_EQU RET +bcid 208 15 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,16 WIDTH,1 M_EQU RET +bcid 209 16 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,17 WIDTH,1 M_EQU RET +bcid 210 17 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,18 WIDTH,1 M_EQU RET +bcid 211 18 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,19 WIDTH,1 M_EQU RET +bcid 212 19 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,20 WIDTH,1 M_EQU RET +bcid 213 20 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,21 WIDTH,1 M_EQU RET +bcid 214 21 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,22 WIDTH,1 M_EQU RET +bcid 215 22 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,23 WIDTH,1 M_EQU RET +bcid 216 23 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,24 WIDTH,1 M_EQU RET +bcid 217 24 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,25 WIDTH,1 M_EQU RET +bcid 218 25 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,26 WIDTH,1 M_EQU RET +bcid 219 26 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,27 WIDTH,1 M_EQU RET +bcid 220 27 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,28 WIDTH,1 M_EQU RET +bcid 221 28 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,29 WIDTH,1 M_EQU RET +bcid 222 29 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,30 WIDTH,1 M_EQU RET +bcid 223 30 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,31 WIDTH,1 M_EQU RET +bcid 224 31 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,32 WIDTH,1 M_EQU RET +bcid 225 32 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,33 WIDTH,1 M_EQU RET +bcid 226 33 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,34 WIDTH,1 M_EQU RET +bcid 227 34 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,35 WIDTH,1 M_EQU RET +bcid 228 35 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,36 WIDTH,1 M_EQU RET +bcid 229 36 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,37 WIDTH,1 M_EQU RET +bcid 230 37 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,38 WIDTH,1 M_EQU RET +bcid 231 38 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,39 WIDTH,1 M_EQU RET +bcid 232 39 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,40 WIDTH,1 M_EQU RET +bcid 233 40 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,41 WIDTH,1 M_EQU RET +bcid 234 41 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,8 CALL_ARG_VAL,3,0 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,24 WIDTH,8 SLICE,1 MITECONDNOINSTR,4 RET +bcid 235 42 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,8 CALL_ARG_VAL,3,0 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,16 WIDTH,8 SLICE,1 MITECONDNOINSTR,4 RET +bcid 236 43 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,8 CALL_ARG_VAL,3,0 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,8 WIDTH,8 SLICE,1 MITECONDNOINSTR,4 RET +bcid 237 44 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,8 CALL_ARG_VAL,3,0 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,0 WIDTH,8 SLICE,1 MITECONDNOINSTR,4 RET +bcid 238 45 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,8 CALL_ARG_VAL,3,0 WIDTH,16 CALL_ARG_VAL,4,0 WIDTH,32 OPT_CONST,8 WIDTH,8 SLICE,1 MITECONDNOINSTR,4 RET +bcid 239 46 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,8 CALL_ARG_VAL,3,0 WIDTH,16 CALL_ARG_VAL,4,0 WIDTH,32 OPT_CONST,0 WIDTH,8 SLICE,1 MITECONDNOINSTR,4 RET +bcid 240 47 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,2 CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 RET +sid ctrl_regfile +bcid 241 0 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 EQU WIDTH,5 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,5,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,6,0 OPT_CONST,1 EQU WIDTH,5 CALL_ARG_VAL,7,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,8,0 OPT_CONST,1 EQU CALL_ARG_VAL,9,0 CALL_ARG_VAL,10,0 OPT_CONST,1 EQU WIDTH,2 CALL_ARG_VAL,11,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,12,0 OPT_CONST,1 EQU WIDTH,2 CALL_ARG_VAL,13,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,14,0 OPT_CONST,1 EQU CALL_ARG_VAL,15,0 CALL_ARG_VAL,16,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,17,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,18,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,19,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,20,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,21,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,22,0 OPT_CONST,1 EQU CALL_ARG_VAL,23,0 CALL_ARG_VAL,24,0 OPT_CONST,1 EQU WIDTH,2 CALL_ARG_VAL,25,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,26,0 OPT_CONST,1 EQU WIDTH,3 CALL_ARG_VAL,27,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,28,0 OPT_CONST,1 EQU CALL_ARG_VAL,29,0 CALL_ARG_VAL,30,0 OPT_CONST,1 EQU WIDTH,2 CALL_ARG_VAL,31,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,32,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,33,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,34,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,35,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,36,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,37,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,38,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,39,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,40,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,41,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,42,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,43,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,44,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,45,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,46,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,47,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,48,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,49,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,50,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,51,0 OPT_CONST,0 WIDTH,1 SLICE,1 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 242 1 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 EQU WIDTH,5 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,5,0 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,6,0 OPT_CONST,1 EQU WIDTH,5 CALL_ARG_VAL,7,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,8,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,9,0 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,10,0 OPT_CONST,1 EQU WIDTH,5 CALL_ARG_VAL,11,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,12,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,13,0 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,14,0 OPT_CONST,1 EQU WIDTH,5 CALL_ARG_VAL,15,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,16,0 OPT_CONST,1 EQU WIDTH,2 CALL_ARG_VAL,17,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,18,0 OPT_CONST,1 EQU WIDTH,2 CALL_ARG_VAL,19,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,20,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,21,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,22,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,23,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,24,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,25,0 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,26,0 OPT_CONST,1 EQU WIDTH,2 CALL_ARG_VAL,27,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,28,0 OPT_CONST,1 EQU WIDTH,3 CALL_ARG_VAL,29,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,30,0 OPT_CONST,1 EQU WIDTH,2 CALL_ARG_VAL,31,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,32,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,33,0 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,34,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,35,0 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,36,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,37,0 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,38,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,39,0 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,40,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,41,0 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,42,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,43,0 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,44,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,45,0 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,46,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,47,0 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,48,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,49,0 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,50,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,51,0 OPT_CONST,1 WIDTH,1 SLICE,1 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 243 2 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 EQU WIDTH,5 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,2 WIDTH,1 SLICE,1 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,5,0 OPT_CONST,2 WIDTH,1 SLICE,1 CALL_ARG_VAL,6,0 OPT_CONST,1 EQU WIDTH,5 CALL_ARG_VAL,7,0 WIDTH,32 OPT_CONST,2 WIDTH,1 SLICE,1 CALL_ARG_VAL,8,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,9,0 OPT_CONST,2 WIDTH,1 SLICE,1 CALL_ARG_VAL,10,0 OPT_CONST,1 EQU WIDTH,5 CALL_ARG_VAL,11,0 WIDTH,32 OPT_CONST,2 WIDTH,1 SLICE,1 CALL_ARG_VAL,12,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,13,0 OPT_CONST,2 WIDTH,1 SLICE,1 CALL_ARG_VAL,14,0 OPT_CONST,1 EQU WIDTH,5 CALL_ARG_VAL,15,0 WIDTH,32 OPT_CONST,2 WIDTH,1 SLICE,1 CALL_ARG_VAL,16,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,17,0 OPT_CONST,2 WIDTH,1 SLICE,1 CALL_ARG_VAL,18,0 OPT_CONST,1 EQU WIDTH,5 CALL_ARG_VAL,19,0 WIDTH,32 OPT_CONST,2 WIDTH,1 SLICE,1 CALL_ARG_VAL,20,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,21,0 OPT_CONST,2 WIDTH,1 SLICE,1 CALL_ARG_VAL,22,0 OPT_CONST,1 EQU WIDTH,5 CALL_ARG_VAL,23,0 WIDTH,32 OPT_CONST,2 WIDTH,1 SLICE,1 CALL_ARG_VAL,24,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,25,0 WIDTH,32 OPT_CONST,2 WIDTH,1 SLICE,1 CALL_ARG_VAL,26,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,27,0 WIDTH,32 OPT_CONST,2 WIDTH,1 SLICE,1 CALL_ARG_VAL,28,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,29,0 OPT_CONST,2 WIDTH,1 SLICE,1 CALL_ARG_VAL,30,0 OPT_CONST,1 EQU WIDTH,3 CALL_ARG_VAL,31,0 WIDTH,32 OPT_CONST,2 WIDTH,1 SLICE,1 CALL_ARG_VAL,32,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,33,0 OPT_CONST,2 WIDTH,1 SLICE,1 CALL_ARG_VAL,34,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,35,0 OPT_CONST,2 WIDTH,1 SLICE,1 CALL_ARG_VAL,36,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,37,0 OPT_CONST,2 WIDTH,1 SLICE,1 CALL_ARG_VAL,38,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,39,0 OPT_CONST,2 WIDTH,1 SLICE,1 CALL_ARG_VAL,40,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,41,0 OPT_CONST,2 WIDTH,1 SLICE,1 CALL_ARG_VAL,42,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,43,0 OPT_CONST,2 WIDTH,1 SLICE,1 CALL_ARG_VAL,44,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,45,0 OPT_CONST,2 WIDTH,1 SLICE,1 CALL_ARG_VAL,46,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,47,0 OPT_CONST,2 WIDTH,1 SLICE,1 CALL_ARG_VAL,48,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,49,0 OPT_CONST,2 WIDTH,1 SLICE,1 CALL_ARG_VAL,50,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,51,0 OPT_CONST,2 WIDTH,1 SLICE,1 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 244 3 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,3 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU WIDTH,5 CALL_ARG_VAL,5,0 WIDTH,32 OPT_CONST,3 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,6,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,7,0 OPT_CONST,3 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,8,0 OPT_CONST,1 EQU WIDTH,5 CALL_ARG_VAL,9,0 WIDTH,32 OPT_CONST,3 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,10,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,11,0 OPT_CONST,3 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,12,0 OPT_CONST,1 EQU WIDTH,5 CALL_ARG_VAL,13,0 WIDTH,32 OPT_CONST,3 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,14,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,15,0 OPT_CONST,3 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,16,0 OPT_CONST,1 EQU WIDTH,5 CALL_ARG_VAL,17,0 WIDTH,32 OPT_CONST,3 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,18,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,19,0 OPT_CONST,3 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,20,0 OPT_CONST,1 EQU WIDTH,5 CALL_ARG_VAL,21,0 WIDTH,32 OPT_CONST,3 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,22,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,23,0 OPT_CONST,3 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,24,0 OPT_CONST,1 EQU WIDTH,5 CALL_ARG_VAL,25,0 WIDTH,32 OPT_CONST,3 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,26,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,27,0 WIDTH,32 OPT_CONST,3 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,28,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,29,0 WIDTH,32 OPT_CONST,3 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,30,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,31,0 OPT_CONST,3 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,32,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,33,0 OPT_CONST,3 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,34,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,35,0 OPT_CONST,3 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,36,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,37,0 OPT_CONST,3 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,38,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,39,0 OPT_CONST,3 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,40,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,41,0 OPT_CONST,3 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,42,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,43,0 OPT_CONST,3 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,44,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,45,0 OPT_CONST,3 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,46,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,47,0 OPT_CONST,3 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,48,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,49,0 OPT_CONST,3 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,50,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,51,0 OPT_CONST,3 WIDTH,2 SLICE,1 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 245 4 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,21 WIDTH,11 SLICE,1 WIDTH,1 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,5,0 OPT_CONST,21 WIDTH,11 SLICE,1 WIDTH,1 CALL_ARG_VAL,6,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,7,0 OPT_CONST,21 WIDTH,11 SLICE,1 WIDTH,1 CALL_ARG_VAL,8,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,9,0 OPT_CONST,21 WIDTH,11 SLICE,1 WIDTH,1 CALL_ARG_VAL,10,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,11,0 OPT_CONST,21 WIDTH,11 SLICE,1 WIDTH,1 CALL_ARG_VAL,12,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,13,0 OPT_CONST,21 WIDTH,11 SLICE,1 WIDTH,1 CALL_ARG_VAL,14,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,15,0 OPT_CONST,21 WIDTH,11 SLICE,1 WIDTH,1 CALL_ARG_VAL,16,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,17,0 OPT_CONST,21 WIDTH,11 SLICE,1 WIDTH,1 CALL_ARG_VAL,18,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,19,0 OPT_CONST,21 WIDTH,11 SLICE,1 WIDTH,1 CALL_ARG_VAL,20,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,21,0 OPT_CONST,21 WIDTH,11 SLICE,1 WIDTH,1 CALL_ARG_VAL,22,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,23,0 OPT_CONST,21 WIDTH,11 SLICE,1 WIDTH,1 CALL_ARG_VAL,24,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,25,0 OPT_CONST,21 WIDTH,11 SLICE,1 WIDTH,1 CALL_ARG_VAL,26,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,27,0 OPT_CONST,21 WIDTH,11 SLICE,1 WIDTH,1 CALL_ARG_VAL,28,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,29,0 OPT_CONST,21 WIDTH,11 SLICE,1 WIDTH,1 CALL_ARG_VAL,30,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,31,0 OPT_CONST,21 WIDTH,11 SLICE,1 WIDTH,1 CALL_ARG_VAL,32,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,33,0 OPT_CONST,21 WIDTH,11 SLICE,1 WIDTH,1 CALL_ARG_VAL,34,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,35,0 OPT_CONST,21 WIDTH,11 SLICE,1 WIDTH,1 CALL_ARG_VAL,36,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,37,0 OPT_CONST,21 WIDTH,11 SLICE,1 WIDTH,1 CALL_ARG_VAL,38,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,39,0 OPT_CONST,21 WIDTH,11 SLICE,1 WIDTH,1 CALL_ARG_VAL,40,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,41,0 OPT_CONST,21 WIDTH,11 SLICE,1 WIDTH,1 CALL_ARG_VAL,42,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,43,0 OPT_CONST,21 WIDTH,11 SLICE,1 WIDTH,1 CALL_ARG_VAL,44,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,45,0 OPT_CONST,21 WIDTH,11 SLICE,1 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 246 5 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,5 WIDTH,11 SLICE,1 WIDTH,1 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,5,0 OPT_CONST,5 WIDTH,11 SLICE,1 WIDTH,1 CALL_ARG_VAL,6,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,7,0 OPT_CONST,5 WIDTH,11 SLICE,1 WIDTH,1 CALL_ARG_VAL,8,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,9,0 OPT_CONST,5 WIDTH,11 SLICE,1 WIDTH,1 CALL_ARG_VAL,10,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,11,0 OPT_CONST,5 WIDTH,11 SLICE,1 WIDTH,1 CALL_ARG_VAL,12,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,13,0 OPT_CONST,5 WIDTH,11 SLICE,1 WIDTH,1 CALL_ARG_VAL,14,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,15,0 OPT_CONST,5 WIDTH,11 SLICE,1 WIDTH,1 CALL_ARG_VAL,16,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,17,0 OPT_CONST,5 WIDTH,11 SLICE,1 WIDTH,1 CALL_ARG_VAL,18,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,19,0 OPT_CONST,5 WIDTH,11 SLICE,1 WIDTH,1 CALL_ARG_VAL,20,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,21,0 OPT_CONST,5 WIDTH,11 SLICE,1 WIDTH,1 CALL_ARG_VAL,22,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,23,0 OPT_CONST,5 WIDTH,11 SLICE,1 WIDTH,1 CALL_ARG_VAL,24,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,25,0 OPT_CONST,5 WIDTH,11 SLICE,1 WIDTH,1 CALL_ARG_VAL,26,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,27,0 WIDTH,32 OPT_CONST,5 WIDTH,11 SLICE,1 WIDTH,1 CALL_ARG_VAL,28,0 OPT_CONST,1 EQU WIDTH,16 CALL_ARG_VAL,29,0 WIDTH,32 OPT_CONST,5 WIDTH,11 SLICE,1 WIDTH,1 CALL_ARG_VAL,30,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,31,0 OPT_CONST,5 WIDTH,11 SLICE,1 WIDTH,1 CALL_ARG_VAL,32,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,33,0 OPT_CONST,5 WIDTH,11 SLICE,1 WIDTH,1 CALL_ARG_VAL,34,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,35,0 OPT_CONST,5 WIDTH,11 SLICE,1 WIDTH,1 CALL_ARG_VAL,36,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,37,0 OPT_CONST,5 WIDTH,11 SLICE,1 WIDTH,1 CALL_ARG_VAL,38,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,39,0 OPT_CONST,5 WIDTH,11 SLICE,1 WIDTH,1 CALL_ARG_VAL,40,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,41,0 OPT_CONST,5 WIDTH,11 SLICE,1 WIDTH,1 CALL_ARG_VAL,42,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,43,0 OPT_CONST,5 WIDTH,11 SLICE,1 WIDTH,1 CALL_ARG_VAL,44,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,45,0 OPT_CONST,5 WIDTH,11 SLICE,1 WIDTH,1 CALL_ARG_VAL,46,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,47,0 OPT_CONST,5 WIDTH,11 SLICE,1 WIDTH,1 CALL_ARG_VAL,48,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,49,0 OPT_CONST,5 WIDTH,11 SLICE,1 WIDTH,1 CALL_ARG_VAL,50,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,51,0 OPT_CONST,5 WIDTH,11 SLICE,1 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 247 6 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 EQU WIDTH,21 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,16 WIDTH,5 SLICE,1 WIDTH,1 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU WIDTH,21 CALL_ARG_VAL,5,0 WIDTH,32 OPT_CONST,16 WIDTH,5 SLICE,1 WIDTH,1 CALL_ARG_VAL,6,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,7,0 OPT_CONST,16 WIDTH,5 SLICE,1 WIDTH,1 CALL_ARG_VAL,8,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,9,0 OPT_CONST,16 WIDTH,5 SLICE,1 WIDTH,1 CALL_ARG_VAL,10,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,11,0 OPT_CONST,16 WIDTH,5 SLICE,1 WIDTH,1 CALL_ARG_VAL,12,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,13,0 OPT_CONST,16 WIDTH,5 SLICE,1 WIDTH,1 CALL_ARG_VAL,14,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,15,0 OPT_CONST,16 WIDTH,5 SLICE,1 WIDTH,1 CALL_ARG_VAL,16,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,17,0 OPT_CONST,16 WIDTH,5 SLICE,1 WIDTH,1 CALL_ARG_VAL,18,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,19,0 OPT_CONST,16 WIDTH,5 SLICE,1 WIDTH,1 CALL_ARG_VAL,20,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,21,0 OPT_CONST,16 WIDTH,5 SLICE,1 WIDTH,1 CALL_ARG_VAL,22,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,23,0 OPT_CONST,16 WIDTH,5 SLICE,1 WIDTH,1 CALL_ARG_VAL,24,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,25,0 OPT_CONST,16 WIDTH,5 SLICE,1 WIDTH,1 CALL_ARG_VAL,26,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,27,0 OPT_CONST,16 WIDTH,5 SLICE,1 WIDTH,1 CALL_ARG_VAL,28,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,29,0 OPT_CONST,16 WIDTH,5 SLICE,1 WIDTH,1 CALL_ARG_VAL,30,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,31,0 OPT_CONST,16 WIDTH,5 SLICE,1 WIDTH,1 CALL_ARG_VAL,32,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,33,0 OPT_CONST,16 WIDTH,5 SLICE,1 WIDTH,1 CALL_ARG_VAL,34,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,35,0 OPT_CONST,16 WIDTH,5 SLICE,1 WIDTH,1 CALL_ARG_VAL,36,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,37,0 OPT_CONST,16 WIDTH,5 SLICE,1 WIDTH,1 CALL_ARG_VAL,38,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,39,0 OPT_CONST,16 WIDTH,5 SLICE,1 WIDTH,1 CALL_ARG_VAL,40,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,41,0 OPT_CONST,16 WIDTH,5 SLICE,1 WIDTH,1 CALL_ARG_VAL,42,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,43,0 OPT_CONST,16 WIDTH,5 SLICE,1 WIDTH,1 CALL_ARG_VAL,44,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,45,0 OPT_CONST,16 WIDTH,5 SLICE,1 WIDTH,1 CALL_ARG_VAL,46,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,47,0 OPT_CONST,16 WIDTH,5 SLICE,1 WIDTH,1 CALL_ARG_VAL,48,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,49,0 OPT_CONST,16 WIDTH,5 SLICE,1 WIDTH,1 CALL_ARG_VAL,50,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,51,0 OPT_CONST,16 WIDTH,5 SLICE,1 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 248 7 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 EQU WIDTH,21 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU WIDTH,21 CALL_ARG_VAL,5,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,6,0 OPT_CONST,1 EQU WIDTH,21 CALL_ARG_VAL,7,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,8,0 OPT_CONST,1 EQU WIDTH,21 CALL_ARG_VAL,9,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,10,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,11,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,12,0 OPT_CONST,1 EQU WIDTH,5 CALL_ARG_VAL,13,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,14,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,15,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,16,0 OPT_CONST,1 EQU WIDTH,5 CALL_ARG_VAL,17,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,18,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,19,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,20,0 OPT_CONST,1 EQU WIDTH,5 CALL_ARG_VAL,21,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,22,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,23,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,24,0 OPT_CONST,1 EQU WIDTH,5 CALL_ARG_VAL,25,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,26,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,27,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,28,0 OPT_CONST,1 EQU WIDTH,5 CALL_ARG_VAL,29,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,30,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,31,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,32,0 OPT_CONST,1 EQU WIDTH,5 CALL_ARG_VAL,33,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,34,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,35,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,36,0 OPT_CONST,1 EQU WIDTH,5 CALL_ARG_VAL,37,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,38,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,39,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,40,0 OPT_CONST,1 EQU WIDTH,5 CALL_ARG_VAL,41,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,42,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,43,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,44,0 OPT_CONST,1 EQU WIDTH,5 CALL_ARG_VAL,45,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,46,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,47,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,48,0 OPT_CONST,1 EQU WIDTH,5 CALL_ARG_VAL,49,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,50,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,51,0 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,52,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 249 8 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 EQU WIDTH,21 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU WIDTH,21 CALL_ARG_VAL,5,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,6,0 OPT_CONST,1 EQU WIDTH,21 CALL_ARG_VAL,7,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,8,0 OPT_CONST,1 EQU WIDTH,21 CALL_ARG_VAL,9,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,10,0 OPT_CONST,1 EQU WIDTH,21 CALL_ARG_VAL,11,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,12,0 OPT_CONST,1 EQU WIDTH,21 CALL_ARG_VAL,13,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,14,0 OPT_CONST,1 EQU WIDTH,21 CALL_ARG_VAL,15,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,16,0 OPT_CONST,1 EQU WIDTH,21 CALL_ARG_VAL,17,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,18,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,19,0 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,20,0 OPT_CONST,1 EQU WIDTH,5 CALL_ARG_VAL,21,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,22,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,23,0 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,24,0 OPT_CONST,1 EQU WIDTH,5 CALL_ARG_VAL,25,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,26,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,27,0 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,28,0 OPT_CONST,1 EQU WIDTH,5 CALL_ARG_VAL,29,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,30,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,31,0 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,32,0 OPT_CONST,1 EQU WIDTH,5 CALL_ARG_VAL,33,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,34,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,35,0 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,36,0 OPT_CONST,1 EQU WIDTH,5 CALL_ARG_VAL,37,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,38,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,39,0 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,40,0 OPT_CONST,1 EQU WIDTH,5 CALL_ARG_VAL,41,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,42,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,43,0 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,44,0 OPT_CONST,1 EQU WIDTH,5 CALL_ARG_VAL,45,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,46,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,47,0 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,48,0 OPT_CONST,1 EQU WIDTH,5 CALL_ARG_VAL,49,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,50,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,51,0 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,52,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 250 9 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 EQU WIDTH,21 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,16 WIDTH,5 SLICE,1 WIDTH,1 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU WIDTH,21 CALL_ARG_VAL,5,0 WIDTH,32 OPT_CONST,16 WIDTH,5 SLICE,1 WIDTH,1 CALL_ARG_VAL,6,0 OPT_CONST,1 EQU WIDTH,21 CALL_ARG_VAL,7,0 WIDTH,32 OPT_CONST,16 WIDTH,5 SLICE,1 WIDTH,1 CALL_ARG_VAL,8,0 OPT_CONST,1 EQU WIDTH,21 CALL_ARG_VAL,9,0 WIDTH,32 OPT_CONST,16 WIDTH,5 SLICE,1 WIDTH,1 CALL_ARG_VAL,10,0 OPT_CONST,1 EQU WIDTH,21 CALL_ARG_VAL,11,0 WIDTH,32 OPT_CONST,16 WIDTH,5 SLICE,1 WIDTH,1 CALL_ARG_VAL,12,0 OPT_CONST,1 EQU WIDTH,21 CALL_ARG_VAL,13,0 WIDTH,32 OPT_CONST,16 WIDTH,5 SLICE,1 WIDTH,1 CALL_ARG_VAL,14,0 OPT_CONST,1 EQU WIDTH,21 CALL_ARG_VAL,15,0 WIDTH,32 OPT_CONST,16 WIDTH,5 SLICE,1 WIDTH,1 CALL_ARG_VAL,16,0 OPT_CONST,1 EQU WIDTH,21 CALL_ARG_VAL,17,0 WIDTH,32 OPT_CONST,16 WIDTH,5 SLICE,1 WIDTH,1 CALL_ARG_VAL,18,0 OPT_CONST,1 EQU WIDTH,21 CALL_ARG_VAL,19,0 WIDTH,32 OPT_CONST,16 WIDTH,5 SLICE,1 WIDTH,1 CALL_ARG_VAL,20,0 OPT_CONST,1 EQU WIDTH,21 CALL_ARG_VAL,21,0 WIDTH,32 OPT_CONST,16 WIDTH,5 SLICE,1 CALL_ARG_VAL,22,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 251 10 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 EQU WIDTH,21 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,5 WIDTH,11 SLICE,1 WIDTH,1 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU WIDTH,21 CALL_ARG_VAL,5,0 WIDTH,32 OPT_CONST,5 WIDTH,11 SLICE,1 WIDTH,1 CALL_ARG_VAL,6,0 OPT_CONST,1 EQU WIDTH,21 CALL_ARG_VAL,7,0 WIDTH,32 OPT_CONST,5 WIDTH,11 SLICE,1 WIDTH,1 CALL_ARG_VAL,8,0 OPT_CONST,1 EQU WIDTH,21 CALL_ARG_VAL,9,0 WIDTH,32 OPT_CONST,5 WIDTH,11 SLICE,1 WIDTH,1 CALL_ARG_VAL,10,0 OPT_CONST,1 EQU WIDTH,21 CALL_ARG_VAL,11,0 WIDTH,32 OPT_CONST,5 WIDTH,11 SLICE,1 WIDTH,1 CALL_ARG_VAL,12,0 OPT_CONST,1 EQU WIDTH,21 CALL_ARG_VAL,13,0 WIDTH,32 OPT_CONST,5 WIDTH,11 SLICE,1 WIDTH,1 CALL_ARG_VAL,14,0 OPT_CONST,1 EQU WIDTH,21 CALL_ARG_VAL,15,0 WIDTH,32 OPT_CONST,5 WIDTH,11 SLICE,1 WIDTH,1 CALL_ARG_VAL,16,0 OPT_CONST,1 EQU WIDTH,21 CALL_ARG_VAL,17,0 WIDTH,32 OPT_CONST,5 WIDTH,11 SLICE,1 WIDTH,1 CALL_ARG_VAL,18,0 OPT_CONST,1 EQU WIDTH,21 CALL_ARG_VAL,19,0 WIDTH,32 OPT_CONST,5 WIDTH,11 SLICE,1 WIDTH,1 CALL_ARG_VAL,20,0 OPT_CONST,1 EQU WIDTH,21 CALL_ARG_VAL,21,0 WIDTH,32 OPT_CONST,5 WIDTH,11 SLICE,1 WIDTH,1 CALL_ARG_VAL,22,0 OPT_CONST,1 EQU WIDTH,21 CALL_ARG_VAL,23,0 WIDTH,32 OPT_CONST,5 WIDTH,11 SLICE,1 WIDTH,1 CALL_ARG_VAL,24,0 OPT_CONST,1 EQU WIDTH,21 CALL_ARG_VAL,25,0 WIDTH,32 OPT_CONST,5 WIDTH,11 SLICE,1 CALL_ARG_VAL,26,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 252 11 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 EQU WIDTH,21 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,3 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU WIDTH,21 CALL_ARG_VAL,5,0 WIDTH,32 OPT_CONST,3 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,6,0 OPT_CONST,1 EQU WIDTH,21 CALL_ARG_VAL,7,0 WIDTH,32 OPT_CONST,3 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,8,0 OPT_CONST,1 EQU WIDTH,21 CALL_ARG_VAL,9,0 WIDTH,32 OPT_CONST,3 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,10,0 OPT_CONST,1 EQU WIDTH,21 CALL_ARG_VAL,11,0 WIDTH,32 OPT_CONST,3 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,12,0 OPT_CONST,1 EQU WIDTH,21 CALL_ARG_VAL,13,0 WIDTH,32 OPT_CONST,3 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,14,0 OPT_CONST,1 EQU WIDTH,21 CALL_ARG_VAL,15,0 WIDTH,32 OPT_CONST,3 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,16,0 OPT_CONST,1 EQU WIDTH,21 CALL_ARG_VAL,17,0 WIDTH,32 OPT_CONST,3 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,18,0 OPT_CONST,1 EQU WIDTH,21 CALL_ARG_VAL,19,0 WIDTH,32 OPT_CONST,3 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,20,0 OPT_CONST,1 EQU WIDTH,21 CALL_ARG_VAL,21,0 WIDTH,32 OPT_CONST,3 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,22,0 OPT_CONST,1 EQU WIDTH,21 CALL_ARG_VAL,23,0 WIDTH,32 OPT_CONST,3 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,24,0 OPT_CONST,1 EQU WIDTH,21 CALL_ARG_VAL,25,0 WIDTH,32 OPT_CONST,3 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,26,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,27,0 OPT_CONST,3 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,28,0 OPT_CONST,1 EQU WIDTH,5 CALL_ARG_VAL,29,0 WIDTH,32 OPT_CONST,3 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,30,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,31,0 OPT_CONST,3 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,32,0 OPT_CONST,1 EQU WIDTH,5 CALL_ARG_VAL,33,0 WIDTH,32 OPT_CONST,3 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,34,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,35,0 OPT_CONST,3 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,36,0 OPT_CONST,1 EQU WIDTH,5 CALL_ARG_VAL,37,0 WIDTH,32 OPT_CONST,3 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,38,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,39,0 OPT_CONST,3 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,40,0 OPT_CONST,1 EQU WIDTH,5 CALL_ARG_VAL,41,0 WIDTH,32 OPT_CONST,3 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,42,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,43,0 OPT_CONST,3 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,44,0 OPT_CONST,1 EQU WIDTH,5 CALL_ARG_VAL,45,0 WIDTH,32 OPT_CONST,3 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,46,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,47,0 OPT_CONST,3 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,48,0 OPT_CONST,1 EQU WIDTH,5 CALL_ARG_VAL,49,0 WIDTH,32 OPT_CONST,3 WIDTH,2 SLICE,1 CALL_ARG_VAL,50,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 253 12 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 EQU WIDTH,21 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,2 WIDTH,1 SLICE,1 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU WIDTH,21 CALL_ARG_VAL,5,0 WIDTH,32 OPT_CONST,2 WIDTH,1 SLICE,1 CALL_ARG_VAL,6,0 OPT_CONST,1 EQU WIDTH,21 CALL_ARG_VAL,7,0 WIDTH,32 OPT_CONST,2 WIDTH,1 SLICE,1 CALL_ARG_VAL,8,0 OPT_CONST,1 EQU WIDTH,21 CALL_ARG_VAL,9,0 WIDTH,32 OPT_CONST,2 WIDTH,1 SLICE,1 CALL_ARG_VAL,10,0 OPT_CONST,1 EQU WIDTH,21 CALL_ARG_VAL,11,0 WIDTH,32 OPT_CONST,2 WIDTH,1 SLICE,1 CALL_ARG_VAL,12,0 OPT_CONST,1 EQU WIDTH,21 CALL_ARG_VAL,13,0 WIDTH,32 OPT_CONST,2 WIDTH,1 SLICE,1 CALL_ARG_VAL,14,0 OPT_CONST,1 EQU WIDTH,21 CALL_ARG_VAL,15,0 WIDTH,32 OPT_CONST,2 WIDTH,1 SLICE,1 CALL_ARG_VAL,16,0 OPT_CONST,1 EQU WIDTH,21 CALL_ARG_VAL,17,0 WIDTH,32 OPT_CONST,2 WIDTH,1 SLICE,1 CALL_ARG_VAL,18,0 OPT_CONST,1 EQU WIDTH,21 CALL_ARG_VAL,19,0 WIDTH,32 OPT_CONST,2 WIDTH,1 SLICE,1 CALL_ARG_VAL,20,0 OPT_CONST,1 EQU WIDTH,21 CALL_ARG_VAL,21,0 WIDTH,32 OPT_CONST,2 WIDTH,1 SLICE,1 CALL_ARG_VAL,22,0 OPT_CONST,1 EQU WIDTH,21 CALL_ARG_VAL,23,0 WIDTH,32 OPT_CONST,2 WIDTH,1 SLICE,1 CALL_ARG_VAL,24,0 OPT_CONST,1 EQU WIDTH,21 CALL_ARG_VAL,25,0 WIDTH,32 OPT_CONST,2 WIDTH,1 SLICE,1 CALL_ARG_VAL,26,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,27,0 OPT_CONST,2 WIDTH,1 SLICE,1 CALL_ARG_VAL,28,0 OPT_CONST,1 EQU WIDTH,5 CALL_ARG_VAL,29,0 WIDTH,32 OPT_CONST,2 WIDTH,1 SLICE,1 CALL_ARG_VAL,30,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,31,0 OPT_CONST,2 WIDTH,1 SLICE,1 CALL_ARG_VAL,32,0 OPT_CONST,1 EQU WIDTH,5 CALL_ARG_VAL,33,0 WIDTH,32 OPT_CONST,2 WIDTH,1 SLICE,1 CALL_ARG_VAL,34,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,35,0 OPT_CONST,2 WIDTH,1 SLICE,1 CALL_ARG_VAL,36,0 OPT_CONST,1 EQU WIDTH,5 CALL_ARG_VAL,37,0 WIDTH,32 OPT_CONST,2 WIDTH,1 SLICE,1 CALL_ARG_VAL,38,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,39,0 OPT_CONST,2 WIDTH,1 SLICE,1 CALL_ARG_VAL,40,0 OPT_CONST,1 EQU WIDTH,5 CALL_ARG_VAL,41,0 WIDTH,32 OPT_CONST,2 WIDTH,1 SLICE,1 CALL_ARG_VAL,42,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,43,0 OPT_CONST,2 WIDTH,1 SLICE,1 CALL_ARG_VAL,44,0 OPT_CONST,1 EQU WIDTH,5 CALL_ARG_VAL,45,0 WIDTH,32 OPT_CONST,2 WIDTH,1 SLICE,1 CALL_ARG_VAL,46,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,47,0 OPT_CONST,2 WIDTH,1 SLICE,1 CALL_ARG_VAL,48,0 OPT_CONST,1 EQU WIDTH,5 CALL_ARG_VAL,49,0 WIDTH,32 OPT_CONST,2 WIDTH,1 SLICE,1 CALL_ARG_VAL,50,0 OPT_CONST,1 EQU WIDTH,32 CALL_ARG_VAL,51,0 OPT_CONST,2 WIDTH,1 SLICE,1 CALL_ARG_VAL,52,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 254 13 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 EQU CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 RET +bcid 255 14 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 EQU CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU WIDTH,21 CALL_ARG_VAL,5,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,6,0 OPT_CONST,1 EQU WIDTH,21 CALL_ARG_VAL,7,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,8,0 OPT_CONST,1 EQU WIDTH,21 CALL_ARG_VAL,9,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,10,0 OPT_CONST,1 EQU WIDTH,21 CALL_ARG_VAL,11,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,12,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 256 15 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 EQU CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU CALL_ARG_VAL,5,0 CALL_ARG_VAL,6,0 OPT_CONST,1 EQU CALL_ARG_VAL,7,0 CALL_ARG_VAL,8,0 OPT_CONST,1 EQU WIDTH,21 CALL_ARG_VAL,9,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,10,0 OPT_CONST,1 EQU WIDTH,21 CALL_ARG_VAL,11,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,12,0 OPT_CONST,1 EQU WIDTH,21 CALL_ARG_VAL,13,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,14,0 OPT_CONST,1 EQU WIDTH,21 CALL_ARG_VAL,15,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,16,0 OPT_CONST,1 EQU WIDTH,21 CALL_ARG_VAL,17,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,18,0 OPT_CONST,1 EQU WIDTH,21 CALL_ARG_VAL,19,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,20,0 OPT_CONST,1 EQU WIDTH,21 CALL_ARG_VAL,21,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,22,0 OPT_CONST,1 EQU WIDTH,21 CALL_ARG_VAL,23,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,24,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 257 16 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,0 WIDTH,1 M_EQU RET +bcid 258 17 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,1 WIDTH,1 M_EQU RET +bcid 259 18 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,2 WIDTH,1 M_EQU RET +bcid 260 19 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,3 WIDTH,1 M_EQU RET +bcid 261 20 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,4 WIDTH,1 M_EQU RET +bcid 262 21 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,5 WIDTH,1 M_EQU RET +bcid 263 22 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,6 WIDTH,1 M_EQU RET +bcid 264 23 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,7 WIDTH,1 M_EQU RET +bcid 265 24 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,38 WIDTH,1 M_EQU RET +bcid 266 25 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,39 WIDTH,1 M_EQU RET +bcid 267 26 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,40 WIDTH,1 M_EQU RET +bcid 268 27 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,64 WIDTH,1 M_EQU RET +bcid 269 28 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,65 WIDTH,1 M_EQU RET +bcid 270 29 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,66 WIDTH,1 M_EQU RET +bcid 271 30 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,67 WIDTH,1 M_EQU RET +bcid 272 31 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,68 WIDTH,1 M_EQU RET +bcid 273 32 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,69 WIDTH,1 M_EQU RET +bcid 274 33 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,70 WIDTH,1 M_EQU RET +bcid 275 34 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,71 WIDTH,1 M_EQU RET +bcid 276 35 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,72 WIDTH,1 M_EQU RET +bcid 277 36 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,74 WIDTH,1 M_EQU RET +bcid 278 37 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,75 WIDTH,1 M_EQU RET +bcid 279 38 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,76 WIDTH,1 M_EQU RET +bcid 280 39 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,77 WIDTH,1 M_EQU RET +bcid 281 40 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,78 WIDTH,1 M_EQU RET +bcid 282 41 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,79 WIDTH,1 M_EQU RET +bcid 283 42 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,80 WIDTH,1 M_EQU RET +bcid 284 43 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,81 WIDTH,1 M_EQU RET +bcid 285 44 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,82 WIDTH,1 M_EQU RET +bcid 286 45 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,83 WIDTH,1 M_EQU RET +bcid 287 46 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,84 WIDTH,1 M_EQU RET +bcid 288 47 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,85 WIDTH,1 M_EQU RET +bcid 289 48 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,86 WIDTH,1 M_EQU RET +bcid 290 49 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,87 WIDTH,1 M_EQU RET +bcid 291 50 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,88 WIDTH,1 M_EQU RET +bcid 292 51 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,89 WIDTH,1 M_EQU RET +bcid 293 52 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,90 WIDTH,1 M_EQU RET +bcid 294 53 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,91 WIDTH,1 M_EQU RET +bcid 295 54 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,92 WIDTH,1 M_EQU RET +bcid 296 55 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,93 WIDTH,1 M_EQU RET +bcid 297 56 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,94 WIDTH,1 M_EQU RET +bcid 298 57 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,95 WIDTH,1 M_EQU RET +bcid 299 58 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,96 WIDTH,1 M_EQU RET +bcid 300 59 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,97 WIDTH,1 M_EQU RET +bcid 301 60 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,98 WIDTH,1 M_EQU RET +bcid 302 61 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,99 WIDTH,1 M_EQU RET +bcid 303 62 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,100 WIDTH,1 M_EQU RET +bcid 304 63 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,101 WIDTH,1 M_EQU RET +bcid 305 64 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,102 WIDTH,1 M_EQU RET +bcid 306 65 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,103 WIDTH,1 M_EQU RET +bcid 307 66 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,104 WIDTH,1 M_EQU RET +bcid 308 67 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,105 WIDTH,1 M_EQU RET +bcid 309 68 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,106 WIDTH,1 M_EQU RET +bcid 310 69 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,107 WIDTH,1 M_EQU RET +bcid 311 70 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,108 WIDTH,1 M_EQU RET +bcid 312 71 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,109 WIDTH,1 M_EQU RET +bcid 313 72 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,110 WIDTH,1 M_EQU RET +bcid 314 73 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,111 WIDTH,1 M_EQU RET +bcid 315 74 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,112 WIDTH,1 M_EQU RET +bcid 316 75 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,114 WIDTH,1 M_EQU RET +bcid 317 76 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,113 WIDTH,1 M_EQU RET +bcid 318 77 WIDTH,2 CALL_ARG_VAL,2,0 OPT_CONST,3 WIDTH,1 M_EQU RET +sid DUC_HB2 +bcid 319 0 WIDTH,33 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,15 WIDTH,18 SLICE,1 WIDTH,33 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,14 WIDTH,1 SLICE,1 WIDTH,18 PAD ADD RET +sid DUC_HB3 +bcid 320 0 WIDTH,33 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,15 WIDTH,18 SLICE,1 WIDTH,33 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,14 WIDTH,1 SLICE,1 WIDTH,18 PAD ADD RET +sid DUC_HB4 +bcid 321 0 WIDTH,33 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,15 WIDTH,18 SLICE,1 WIDTH,33 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,14 WIDTH,1 SLICE,1 WIDTH,18 PAD ADD RET +sid DUC4 +bcid 322 0 WIDTH,34 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,15 WIDTH,19 SLICE,1 WIDTH,20 PAD WIDTH,34 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,14 WIDTH,1 SLICE,1 WIDTH,20 PAD ADD RET +sid DW_mult_pipe_0000_0000 +bcid 323 0 WIDTH,11 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,10 WIDTH,1 SLICE,1 WIDTH,11 CALL_ARG_VAL,2,0 NOT OPT_CONST,1 ADD CALL_ARG_VAL,2,0 MITECONDNOINSTR,4 RET +bcid 324 1 WIDTH,12 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,11 WIDTH,1 SLICE,1 WIDTH,12 CALL_ARG_VAL,2,0 NOT OPT_CONST,1 ADD CALL_ARG_VAL,2,0 MITECONDNOINSTR,4 RET +bcid 325 2 WIDTH,11 CALL_ARG_VAL,2,0 WIDTH,22 PAD WIDTH,12 CALL_ARG_VAL,3,0 WIDTH,22 PAD MULTIPLY RET +bcid 326 3 WIDTH,22 CALL_ARG_VAL,2,0 OPT_CONST,1 SUBTRACT NOT RET +bcid 327 4 WIDTH,11 CALL_ARG_VAL,2,0 CALL_ARG_VAL,2,0 XOR WIDTH,1 XOR_REDUCE OPT_CONST,0 NEQU WIDTH,12 CALL_ARG_VAL,3,0 CALL_ARG_VAL,3,0 XOR WIDTH,1 XOR_REDUCE OPT_CONST,0 NEQU CALL_ARG_VAL,4,0 CALL_ARG_VAL,4,0 XOR XOR_REDUCE OPT_CONST,0 NEQU OR OR WIDTH,23 OPT_CONST_4ST,8388607,8388607 WIDTH,1 CALL_ARG_VAL,4,0 WIDTH,11 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,10 WIDTH,1 SLICE,1 WIDTH,12 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,11 WIDTH,1 SLICE,1 XOR WIDTH,22 CALL_ARG_VAL,5,0 OPT_CONST,0 WIDTH,1 M_NEQU AND OPT_CONST,1 WIDTH,22 CALL_ARG_VAL,6,0 WIDTH,23 CONCATENATE,2 WIDTH,1 OPT_CONST,0 WIDTH,22 CALL_ARG_VAL,5,0 WIDTH,23 CONCATENATE,2 MITECONDNOINSTR,4 WIDTH,11 CALL_ARG_VAL,2,0 WIDTH,23 PAD WIDTH,12 CALL_ARG_VAL,3,0 WIDTH,23 PAD MULTIPLY MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +sid PH2AMP +bcid 328 0 WIDTH,16 CALL_ARG_VAL,2,0 OPT_CONST,0 WIDTH,1 M_NEQU WIDTH,16 MULTI_CONCATENATE,1,16 CALL_ARG_VAL,2,0 NOT OPT_CONST,1 ADD AND RET +bcid 329 1 WIDTH,19 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,16 WIDTH,1 SLICE,1 WIDTH,19 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,0 WIDTH,16 SLICE,1 NOT WIDTH,19 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,0 WIDTH,16 SLICE,1 MITECONDNOINSTR,4 RET +bcid 330 2 WIDTH,16 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,10 WIDTH,1 SLICE,1 WIDTH,16 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,11 WIDTH,5 SLICE,1 OPT_CONST,1 ADD WIDTH,16 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,11 WIDTH,5 SLICE,1 MITECONDNOINSTR,4 RET +bcid 331 3 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,13 CALL_ARG_VAL,3,0 OPT_CONST,1 ADD CALL_ARG_VAL,3,0 MITECONDNOINSTR,4 RET +bcid 332 4 WIDTH,18 CALL_ARG_VAL,2,0 WIDTH,13 CALL_ARG_VAL,3,0 WIDTH,18 PAD ADD RET +bcid 333 5 WIDTH,18 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,2 WIDTH,1 SLICE,1 WIDTH,18 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,3 WIDTH,15 SLICE,1 OPT_CONST,1 ADD WIDTH,18 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,3 WIDTH,15 SLICE,1 MITECONDNOINSTR,4 RET +bcid 334 6 WIDTH,11 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,10 WIDTH,1 SLICE,1 WIDTH,11 CALL_ARG_VAL,2,0 NOT OPT_CONST,1 ADD CALL_ARG_VAL,2,0 MITECONDNOINSTR,4 RET +bcid 335 7 WIDTH,5 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,4 WIDTH,1 SLICE,1 WIDTH,5 CALL_ARG_VAL,2,0 NOT OPT_CONST,1 ADD CALL_ARG_VAL,2,0 MITECONDNOINSTR,4 RET +bcid 336 8 WIDTH,11 CALL_ARG_VAL,2,0 WIDTH,15 PAD WIDTH,5 CALL_ARG_VAL,3,0 WIDTH,15 PAD MULTIPLY RET +bcid 337 9 WIDTH,15 CALL_ARG_VAL,2,0 OPT_CONST,1 SUBTRACT NOT RET +bcid 338 10 WIDTH,11 CALL_ARG_VAL,2,0 CALL_ARG_VAL,2,0 XOR WIDTH,1 XOR_REDUCE OPT_CONST,0 NEQU WIDTH,5 CALL_ARG_VAL,3,0 CALL_ARG_VAL,3,0 XOR WIDTH,1 XOR_REDUCE OPT_CONST,0 NEQU CALL_ARG_VAL,4,0 CALL_ARG_VAL,4,0 XOR XOR_REDUCE OPT_CONST,0 NEQU OR OR WIDTH,16 OPT_CONST_4ST,65535,65535 WIDTH,1 CALL_ARG_VAL,4,0 WIDTH,11 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,10 WIDTH,1 SLICE,1 WIDTH,5 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,4 WIDTH,1 SLICE,1 XOR WIDTH,15 CALL_ARG_VAL,5,0 OPT_CONST,0 WIDTH,1 M_NEQU AND OPT_CONST,1 WIDTH,15 CALL_ARG_VAL,6,0 WIDTH,16 CONCATENATE,2 WIDTH,1 OPT_CONST,0 WIDTH,15 CALL_ARG_VAL,5,0 WIDTH,16 CONCATENATE,2 MITECONDNOINSTR,4 WIDTH,11 CALL_ARG_VAL,2,0 WIDTH,16 PAD WIDTH,5 CALL_ARG_VAL,3,0 WIDTH,16 PAD MULTIPLY MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 339 11 WIDTH,17 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,10 WIDTH,1 SLICE,1 WIDTH,17 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,11 WIDTH,6 SLICE,1 OPT_CONST,1 ADD WIDTH,17 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,11 WIDTH,6 SLICE,1 MITECONDNOINSTR,4 RET +bcid 340 12 WIDTH,18 CALL_ARG_VAL,2,0 WIDTH,13 CALL_ARG_VAL,3,0 WIDTH,18 PAD SUBTRACT RET +bcid 341 13 WIDTH,18 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,2 WIDTH,1 SLICE,1 OPT_CONST,0 WIDTH,18 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,3 WIDTH,15 SLICE,1 WIDTH,16 CONCATENATE,2 OPT_CONST,1 ADD WIDTH,1 OPT_CONST,0 WIDTH,18 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,3 WIDTH,15 SLICE,1 WIDTH,16 CONCATENATE,2 MITECONDNOINSTR,4 RET +bcid 342 14 WIDTH,16 CALL_ARG_VAL,2,0 OPT_CONST,32766 WIDTH,1 M_GT WIDTH,15 OPT_CONST,32767 WIDTH,16 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,0 WIDTH,15 SLICE,1 MITECONDNOINSTR,4 RET +bcid 343 15 WIDTH,6 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,5 WIDTH,1 SLICE,1 WIDTH,6 CALL_ARG_VAL,2,0 NOT OPT_CONST,1 ADD CALL_ARG_VAL,2,0 MITECONDNOINSTR,4 RET +bcid 344 16 WIDTH,11 CALL_ARG_VAL,2,0 WIDTH,16 PAD WIDTH,6 CALL_ARG_VAL,3,0 WIDTH,16 PAD MULTIPLY RET +bcid 345 17 WIDTH,16 CALL_ARG_VAL,2,0 OPT_CONST,1 SUBTRACT NOT RET +bcid 346 18 WIDTH,11 CALL_ARG_VAL,2,0 CALL_ARG_VAL,2,0 XOR WIDTH,1 XOR_REDUCE OPT_CONST,0 NEQU WIDTH,6 CALL_ARG_VAL,3,0 CALL_ARG_VAL,3,0 XOR WIDTH,1 XOR_REDUCE OPT_CONST,0 NEQU CALL_ARG_VAL,4,0 CALL_ARG_VAL,4,0 XOR XOR_REDUCE OPT_CONST,0 NEQU OR OR WIDTH,17 OPT_CONST_4ST,131071,131071 WIDTH,1 CALL_ARG_VAL,4,0 WIDTH,11 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,10 WIDTH,1 SLICE,1 WIDTH,6 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,5 WIDTH,1 SLICE,1 XOR WIDTH,16 CALL_ARG_VAL,5,0 OPT_CONST,0 WIDTH,1 M_NEQU AND OPT_CONST,1 WIDTH,16 CALL_ARG_VAL,6,0 WIDTH,17 CONCATENATE,2 WIDTH,1 OPT_CONST,0 WIDTH,16 CALL_ARG_VAL,5,0 WIDTH,17 CONCATENATE,2 MITECONDNOINSTR,4 WIDTH,11 CALL_ARG_VAL,2,0 WIDTH,17 PAD WIDTH,6 CALL_ARG_VAL,3,0 WIDTH,17 PAD MULTIPLY MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +sid DW_mult_pipe_0000_0003 +bcid 347 0 WIDTH,16 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,15 WIDTH,1 SLICE,1 WIDTH,16 CALL_ARG_VAL,2,0 NOT OPT_CONST,1 ADD CALL_ARG_VAL,2,0 MITECONDNOINSTR,4 RET +bcid 348 1 WIDTH,16 CALL_ARG_VAL,2,0 WIDTH,31 PAD WIDTH,16 CALL_ARG_VAL,3,0 WIDTH,31 PAD MULTIPLY RET +bcid 349 2 WIDTH,31 CALL_ARG_VAL,2,0 OPT_CONST,1 SUBTRACT NOT RET +bcid 350 3 WIDTH,16 CALL_ARG_VAL,2,0 CALL_ARG_VAL,2,0 XOR WIDTH,1 XOR_REDUCE OPT_CONST,0 NEQU WIDTH,16 CALL_ARG_VAL,3,0 CALL_ARG_VAL,3,0 XOR WIDTH,1 XOR_REDUCE OPT_CONST,0 NEQU CALL_ARG_VAL,4,0 CALL_ARG_VAL,4,0 XOR XOR_REDUCE OPT_CONST,0 NEQU OR OR WIDTH,32 OPT_CONST_4ST,-1,-1 WIDTH,1 CALL_ARG_VAL,4,0 WIDTH,16 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,15 WIDTH,1 SLICE,1 WIDTH,16 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,15 WIDTH,1 SLICE,1 XOR WIDTH,31 CALL_ARG_VAL,5,0 OPT_CONST,0 WIDTH,1 M_NEQU AND OPT_CONST,1 WIDTH,31 CALL_ARG_VAL,6,0 WIDTH,32 CONCATENATE,2 WIDTH,1 OPT_CONST,0 WIDTH,31 CALL_ARG_VAL,5,0 WIDTH,32 CONCATENATE,2 MITECONDNOINSTR,4 WIDTH,16 CALL_ARG_VAL,2,0 WIDTH,32 PAD WIDTH,16 CALL_ARG_VAL,3,0 WIDTH,32 PAD MULTIPLY MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +sid xy_dsp +bcid 351 0 WIDTH,48 CALL_ARG_VAL,2,0 WIDTH,3 OPT_CONST,1 WIDTH,48 SHIFT_L RET +bcid 352 1 WIDTH,48 CALL_ARG_VAL,2,0 WIDTH,3 OPT_CONST,2 WIDTH,48 SHIFT_L RET +bcid 353 2 WIDTH,48 CALL_ARG_VAL,2,0 WIDTH,3 OPT_CONST,3 WIDTH,48 SHIFT_L RET +bcid 354 3 WIDTH,48 CALL_ARG_VAL,2,0 WIDTH,3 OPT_CONST,4 WIDTH,48 SHIFT_L RET +bcid 355 4 WIDTH,1 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 WIDTH,15 CALL_ARG_VAL,4,0 WIDTH,16 CONCATENATE,2 OPT_CONST,1 ADD WIDTH,1 CALL_ARG_VAL,3,0 WIDTH,15 CALL_ARG_VAL,4,0 WIDTH,16 CONCATENATE,2 MITECONDNOINSTR,4 RET +bcid 356 5 WIDTH,17 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,15 WIDTH,2 SLICE,1 OPT_CONST,1 WIDTH,1 M_EQU WIDTH,16 OPT_CONST,32767 WIDTH,17 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,15 WIDTH,2 SLICE,1 OPT_CONST,2 WIDTH,1 M_EQU WIDTH,16 OPT_CONST,32768 WIDTH,17 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,16 WIDTH,1 SLICE,1 WIDTH,17 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,0 WIDTH,15 SLICE,1 WIDTH,16 CONCATENATE,2 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +sid DW02_mult_0004 +bcid 357 0 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,16 CALL_ARG_VAL,3,0 NOT OPT_CONST,1 ADD CALL_ARG_VAL,3,0 MITECONDNOINSTR,4 RET +bcid 358 1 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,37 CALL_ARG_VAL,3,0 NOT CONST,2,0,0,1 ADD CALL_ARG_VAL,3,0 MITECONDNOINSTR,4 RET +bcid 359 2 WIDTH,16 CALL_ARG_VAL,2,0 WIDTH,52 PAD WIDTH,37 CALL_ARG_VAL,3,0 WIDTH,52 PAD MULTIPLY RET +bcid 360 3 WIDTH,52 CALL_ARG_VAL,2,0 CONST,2,0,0,1 SUBTRACT NOT RET +bcid 361 4 WIDTH,16 CALL_ARG_VAL,2,0 CALL_ARG_VAL,2,0 XOR WIDTH,1 XOR_REDUCE OPT_CONST,0 NEQU WIDTH,37 CALL_ARG_VAL,3,0 CALL_ARG_VAL,3,0 XOR WIDTH,1 XOR_REDUCE OPT_CONST,0 NEQU CALL_ARG_VAL,4,0 CALL_ARG_VAL,4,0 XOR XOR_REDUCE OPT_CONST,0 NEQU OR OR WIDTH,53 CONST,4,0,-1,-1,2097151,2097151 WIDTH,1 CALL_ARG_VAL,4,0 CALL_ARG_VAL,5,0 CALL_ARG_VAL,6,0 XOR WIDTH,52 CALL_ARG_VAL,7,0 CONST,0,0 WIDTH,1 M_NEQU AND OPT_CONST,1 WIDTH,52 CALL_ARG_VAL,8,0 WIDTH,53 CONCATENATE,2 WIDTH,1 OPT_CONST,0 WIDTH,52 CALL_ARG_VAL,7,0 WIDTH,53 CONCATENATE,2 MITECONDNOINSTR,4 WIDTH,16 CALL_ARG_VAL,2,0 WIDTH,53 PAD WIDTH,37 CALL_ARG_VAL,3,0 WIDTH,53 PAD MULTIPLY MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +sid DW02_mult_0005 +bcid 362 0 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,35 CALL_ARG_VAL,3,0 NOT CONST,2,0,0,1 ADD CALL_ARG_VAL,3,0 MITECONDNOINSTR,4 RET +bcid 363 1 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,21 CALL_ARG_VAL,3,0 NOT OPT_CONST,1 ADD CALL_ARG_VAL,3,0 MITECONDNOINSTR,4 RET +bcid 364 2 WIDTH,35 CALL_ARG_VAL,2,0 WIDTH,55 PAD WIDTH,21 CALL_ARG_VAL,3,0 WIDTH,55 PAD MULTIPLY RET +bcid 365 3 WIDTH,55 CALL_ARG_VAL,2,0 CONST,2,0,0,1 SUBTRACT NOT RET +bcid 366 4 WIDTH,35 CALL_ARG_VAL,2,0 CALL_ARG_VAL,2,0 XOR WIDTH,1 XOR_REDUCE OPT_CONST,0 NEQU WIDTH,21 CALL_ARG_VAL,3,0 CALL_ARG_VAL,3,0 XOR WIDTH,1 XOR_REDUCE OPT_CONST,0 NEQU CALL_ARG_VAL,4,0 CALL_ARG_VAL,4,0 XOR XOR_REDUCE OPT_CONST,0 NEQU OR OR WIDTH,56 CONST,4,0,-1,-1,16777215,16777215 WIDTH,1 CALL_ARG_VAL,4,0 CALL_ARG_VAL,5,0 CALL_ARG_VAL,6,0 XOR WIDTH,55 CALL_ARG_VAL,7,0 CONST,0,0 WIDTH,1 M_NEQU AND OPT_CONST,1 WIDTH,55 CALL_ARG_VAL,8,0 WIDTH,56 CONCATENATE,2 WIDTH,1 OPT_CONST,0 WIDTH,55 CALL_ARG_VAL,7,0 WIDTH,56 CONCATENATE,2 MITECONDNOINSTR,4 WIDTH,35 CALL_ARG_VAL,2,0 WIDTH,56 PAD WIDTH,21 CALL_ARG_VAL,3,0 WIDTH,56 PAD MULTIPLY MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +sid IIR_Filter +bcid 367 0 WIDTH,54 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,53 WIDTH,1 SLICE,1 WIDTH,54 CALL_ARG_VAL,2,0 WIDTH,55 CONCATENATE,2 WIDTH,57 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,56 WIDTH,1 SLICE,1 WIDTH,57 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,0 WIDTH,54 SLICE,1 WIDTH,55 CONCATENATE,2 SUBTRACT RET +sid dac_regfile +bcid 368 0 WIDTH,15 OPT_CONST,0 RET +bcid 369 1 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,17 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,15 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,4,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,17 CALL_ARG_VAL,5,0 WIDTH,32 OPT_CONST,15 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,6,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,17 CALL_ARG_VAL,7,0 WIDTH,32 OPT_CONST,15 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,8,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,17 CALL_ARG_VAL,9,0 WIDTH,32 OPT_CONST,15 WIDTH,2 SLICE,1 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 370 2 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,17 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,9 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,4,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,17 CALL_ARG_VAL,5,0 WIDTH,32 OPT_CONST,9 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,6,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,17 CALL_ARG_VAL,7,0 WIDTH,32 OPT_CONST,9 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,8,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,17 CALL_ARG_VAL,9,0 WIDTH,32 OPT_CONST,9 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,10,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,11,0 WIDTH,32 OPT_CONST,9 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,12,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,13,0 WIDTH,32 OPT_CONST,9 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,14,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,15,0 WIDTH,32 OPT_CONST,9 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,16,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,17,0 WIDTH,32 OPT_CONST,9 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,18,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,19,0 WIDTH,32 OPT_CONST,9 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,20,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,21,0 WIDTH,32 OPT_CONST,9 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,22,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,23,0 WIDTH,32 OPT_CONST,9 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,24,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,25,0 WIDTH,32 OPT_CONST,9 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,26,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,27,0 WIDTH,32 OPT_CONST,9 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,28,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,29,0 WIDTH,32 OPT_CONST,9 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,30,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,31,0 WIDTH,32 OPT_CONST,9 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,32,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,33,0 WIDTH,32 OPT_CONST,9 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,34,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,35,0 WIDTH,32 OPT_CONST,9 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,36,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,37,0 WIDTH,32 OPT_CONST,9 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,38,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,39,0 WIDTH,32 OPT_CONST,9 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,40,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,41,0 WIDTH,32 OPT_CONST,9 WIDTH,6 SLICE,1 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 371 3 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,17 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,3 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,4,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,17 CALL_ARG_VAL,5,0 WIDTH,32 OPT_CONST,3 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,6,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,17 CALL_ARG_VAL,7,0 WIDTH,32 OPT_CONST,3 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,8,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,17 CALL_ARG_VAL,9,0 WIDTH,32 OPT_CONST,3 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,10,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,9 CALL_ARG_VAL,11,0 WIDTH,32 OPT_CONST,3 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,12,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,13,0 WIDTH,32 OPT_CONST,3 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,14,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,15,0 WIDTH,32 OPT_CONST,3 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,16,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,17,0 WIDTH,32 OPT_CONST,3 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,18,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,19,0 WIDTH,32 OPT_CONST,3 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,20,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,21,0 WIDTH,32 OPT_CONST,3 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,22,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,23,0 WIDTH,32 OPT_CONST,3 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,24,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,25,0 WIDTH,32 OPT_CONST,3 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,26,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,27,0 WIDTH,32 OPT_CONST,3 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,28,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,29,0 WIDTH,32 OPT_CONST,3 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,30,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,31,0 WIDTH,32 OPT_CONST,3 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,32,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,33,0 WIDTH,32 OPT_CONST,3 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,34,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,35,0 WIDTH,32 OPT_CONST,3 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,36,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,37,0 WIDTH,32 OPT_CONST,3 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,38,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,39,0 WIDTH,32 OPT_CONST,3 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,40,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,41,0 WIDTH,32 OPT_CONST,3 WIDTH,6 SLICE,1 WIDTH,1 CALL_ARG_VAL,42,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,43,0 WIDTH,32 OPT_CONST,3 WIDTH,6 SLICE,1 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 372 4 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,17 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,4,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,17 CALL_ARG_VAL,5,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,6,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,17 CALL_ARG_VAL,7,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,8,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,17 CALL_ARG_VAL,9,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,10,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,9 CALL_ARG_VAL,11,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,12,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,3 CALL_ARG_VAL,13,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,14,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,3 CALL_ARG_VAL,15,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,16,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,17,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,18,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,19,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,20,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,21,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,22,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,23,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,24,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,25,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,26,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,27,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,28,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,29,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,30,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,31,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,32,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,33,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,34,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,35,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,36,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,37,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,38,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,39,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,40,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,41,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,42,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,43,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,44,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,45,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 WIDTH,1 CALL_ARG_VAL,46,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,47,0 WIDTH,32 OPT_CONST,1 WIDTH,2 SLICE,1 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 373 5 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,17 CALL_ARG_VAL,5,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,6,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,17 CALL_ARG_VAL,7,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,8,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,17 CALL_ARG_VAL,9,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,10,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,17 CALL_ARG_VAL,11,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,12,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,9 CALL_ARG_VAL,13,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,14,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,3 CALL_ARG_VAL,15,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,16,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,3 CALL_ARG_VAL,17,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,18,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,19,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,20,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,21,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,22,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,23,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,24,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,25,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,26,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,27,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,28,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,29,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,30,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,31,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,32,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,33,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,34,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,35,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,36,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,37,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,38,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,39,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,40,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,41,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,42,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,43,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,44,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,45,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,46,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,47,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,48,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,49,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,50,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU CALL_ARG_VAL,51,0 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 374 6 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 OPT_CONST,1 XNOR OPT_CONST,1 EQU CALL_ARG_VAL,5,0 CALL_ARG_VAL,6,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 375 7 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,0 WIDTH,1 M_EQU RET +bcid 376 8 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,1 WIDTH,1 M_EQU RET +bcid 377 9 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,2 WIDTH,1 M_EQU RET +bcid 378 10 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,3 WIDTH,1 M_EQU RET +bcid 379 11 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,4 WIDTH,1 M_EQU RET +bcid 380 12 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,5 WIDTH,1 M_EQU RET +bcid 381 13 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,6 WIDTH,1 M_EQU RET +bcid 382 14 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,7 WIDTH,1 M_EQU RET +bcid 383 15 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,8 WIDTH,1 M_EQU RET +bcid 384 16 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,9 WIDTH,1 M_EQU RET +bcid 385 17 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,10 WIDTH,1 M_EQU RET +bcid 386 18 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,11 WIDTH,1 M_EQU RET +bcid 387 19 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,12 WIDTH,1 M_EQU RET +bcid 388 20 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,13 WIDTH,1 M_EQU RET +bcid 389 21 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,14 WIDTH,1 M_EQU RET +bcid 390 22 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,15 WIDTH,1 M_EQU RET +bcid 391 23 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,16 WIDTH,1 M_EQU RET +bcid 392 24 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,17 WIDTH,1 M_EQU RET +bcid 393 25 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,18 WIDTH,1 M_EQU RET +bcid 394 26 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,19 WIDTH,1 M_EQU RET +bcid 395 27 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,20 WIDTH,1 M_EQU RET +bcid 396 28 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,21 WIDTH,1 M_EQU RET +bcid 397 29 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,22 WIDTH,1 M_EQU RET +bcid 398 30 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,23 WIDTH,1 M_EQU RET +bcid 399 31 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,24 WIDTH,1 M_EQU RET +bcid 400 32 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,25 WIDTH,1 M_EQU RET +bcid 401 33 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,26 WIDTH,1 M_EQU RET +bcid 402 34 WIDTH,14 CALL_ARG_VAL,2,0 OPT_CONST,27 WIDTH,1 M_EQU RET +bcid 403 35 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,14 CALL_ARG_VAL,3,0 OPT_CONST,10000 WIDTH,1 M_EQU AND RET +bcid 404 36 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,14 OPT_CONST,0 WIDTH,1 CALL_ARG_VAL,3,0 WIDTH,14 CALL_ARG_VAL,4,0 OPT_CONST,1 ADD CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +sid param_lut_0002 +bcid 405 0 WIDTH,4 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 WIDTH,16 CALL_ARG_VAL,3,0 OPT_CONST,0 MITECONDNOINSTR,4 RET +bcid 406 1 WIDTH,4 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 WIDTH,16 CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 RET +bcid 407 2 WIDTH,4 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,2 WIDTH,1 SLICE,1 WIDTH,16 CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 RET +bcid 408 3 WIDTH,4 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,3 WIDTH,1 SLICE,1 WIDTH,16 CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 RET +sid TSDN28HPCPUHDB4096X32M4MWR +bcid 409 0 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 410 1 WIDTH,1 OPT_CONST,0 RET +bcid 411 2 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 412 3 WIDTH,1 OPT_CONST,0 RET +bcid 413 4 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 414 5 WIDTH,1 OPT_CONST,0 RET +bcid 415 6 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 416 7 WIDTH,1 OPT_CONST,0 RET +bcid 417 8 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 418 9 WIDTH,1 OPT_CONST,0 RET +bcid 419 10 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 420 11 WIDTH,1 OPT_CONST,0 RET +bcid 421 12 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 422 13 WIDTH,1 OPT_CONST,0 RET +bcid 423 14 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 424 15 WIDTH,1 OPT_CONST,0 RET +bcid 425 16 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 426 17 WIDTH,1 OPT_CONST,0 RET +bcid 427 18 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 428 19 WIDTH,1 OPT_CONST,0 RET +bcid 429 20 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 430 21 WIDTH,1 OPT_CONST,0 RET +bcid 431 22 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 432 23 WIDTH,1 OPT_CONST,0 RET +bcid 433 24 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 434 25 WIDTH,1 OPT_CONST,0 RET +bcid 435 26 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 436 27 WIDTH,1 OPT_CONST,0 RET +bcid 437 28 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 438 29 WIDTH,1 OPT_CONST,0 RET +bcid 439 30 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 440 31 WIDTH,1 OPT_CONST,0 RET +bcid 441 32 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 442 33 WIDTH,1 OPT_CONST,0 RET +bcid 443 34 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 444 35 WIDTH,1 OPT_CONST,0 RET +bcid 445 36 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 446 37 WIDTH,1 OPT_CONST,0 RET +bcid 447 38 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 448 39 WIDTH,1 OPT_CONST,0 RET +bcid 449 40 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 450 41 WIDTH,1 OPT_CONST,0 RET +bcid 451 42 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 452 43 WIDTH,1 OPT_CONST,0 RET +bcid 453 44 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 454 45 WIDTH,1 OPT_CONST,0 RET +bcid 455 46 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 456 47 WIDTH,1 OPT_CONST,0 RET +bcid 457 48 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 458 49 WIDTH,1 OPT_CONST,0 RET +bcid 459 50 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 460 51 WIDTH,1 OPT_CONST,0 RET +bcid 461 52 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 462 53 WIDTH,1 OPT_CONST,0 RET +bcid 463 54 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 464 55 WIDTH,1 OPT_CONST,0 RET +bcid 465 56 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 466 57 WIDTH,1 OPT_CONST,0 RET +bcid 467 58 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 468 59 WIDTH,1 OPT_CONST,0 RET +bcid 469 60 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 470 61 WIDTH,1 OPT_CONST,0 RET +bcid 471 62 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 472 63 WIDTH,1 OPT_CONST,0 RET +sid DW_mult_pipe_0000_0002 +bcid 473 0 WIDTH,16 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,15 WIDTH,1 SLICE,1 WIDTH,16 CALL_ARG_VAL,2,0 NOT OPT_CONST,1 ADD CALL_ARG_VAL,2,0 MITECONDNOINSTR,4 RET +bcid 474 1 WIDTH,17 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,16 WIDTH,1 SLICE,1 WIDTH,17 CALL_ARG_VAL,2,0 NOT OPT_CONST,1 ADD CALL_ARG_VAL,2,0 MITECONDNOINSTR,4 RET +bcid 475 2 WIDTH,16 CALL_ARG_VAL,2,0 WIDTH,32 PAD WIDTH,17 CALL_ARG_VAL,3,0 WIDTH,32 PAD MULTIPLY RET +bcid 476 3 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,1 SUBTRACT NOT RET +bcid 477 4 WIDTH,16 CALL_ARG_VAL,2,0 CALL_ARG_VAL,2,0 XOR WIDTH,1 XOR_REDUCE OPT_CONST,0 NEQU WIDTH,17 CALL_ARG_VAL,3,0 CALL_ARG_VAL,3,0 XOR WIDTH,1 XOR_REDUCE OPT_CONST,0 NEQU CALL_ARG_VAL,4,0 CALL_ARG_VAL,4,0 XOR XOR_REDUCE OPT_CONST,0 NEQU OR OR WIDTH,33 CONST,4,0,-1,-1,1,1 WIDTH,1 CALL_ARG_VAL,4,0 WIDTH,16 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,15 WIDTH,1 SLICE,1 WIDTH,17 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,16 WIDTH,1 SLICE,1 XOR WIDTH,32 CALL_ARG_VAL,5,0 OPT_CONST,0 WIDTH,1 M_NEQU AND OPT_CONST,1 WIDTH,32 CALL_ARG_VAL,6,0 WIDTH,33 CONCATENATE,2 WIDTH,1 OPT_CONST,0 WIDTH,32 CALL_ARG_VAL,5,0 WIDTH,33 CONCATENATE,2 MITECONDNOINSTR,4 WIDTH,16 CALL_ARG_VAL,2,0 WIDTH,33 PAD WIDTH,17 CALL_ARG_VAL,3,0 WIDTH,33 PAD MULTIPLY MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +sid modout_mux +bcid 478 0 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,16 CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 RET +bcid 479 1 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 CALL_ARG_VAL,3,0 MITECONDNOINSTR,4 RET +sid channel_top +bcid 480 0 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 481 1 WIDTH,1 OPT_CONST,0 RET +bcid 482 2 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 483 3 WIDTH,1 OPT_CONST,0 RET +bcid 484 4 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 485 5 WIDTH,1 OPT_CONST,0 RET +bcid 486 6 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 487 7 WIDTH,1 OPT_CONST,0 RET +bcid 488 8 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 489 9 WIDTH,1 OPT_CONST,0 RET +bcid 490 10 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 491 11 WIDTH,1 OPT_CONST,0 RET +bcid 492 12 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 493 13 WIDTH,1 OPT_CONST,0 RET +bcid 494 14 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 495 15 WIDTH,1 OPT_CONST,0 RET +bcid 496 16 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 497 17 WIDTH,1 OPT_CONST,0 RET +bcid 498 18 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 499 19 WIDTH,1 OPT_CONST,0 RET +bcid 500 20 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 501 21 WIDTH,1 OPT_CONST,0 RET +bcid 502 22 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 503 23 WIDTH,1 OPT_CONST,0 RET +bcid 504 24 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 505 25 WIDTH,1 OPT_CONST,0 RET +bcid 506 26 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 507 27 WIDTH,1 OPT_CONST,0 RET +bcid 508 28 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 509 29 WIDTH,1 OPT_CONST,0 RET +bcid 510 30 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 511 31 WIDTH,1 OPT_CONST,0 RET +bcid 512 32 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 513 33 WIDTH,1 OPT_CONST,0 RET +bcid 514 34 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 515 35 WIDTH,1 OPT_CONST,0 RET +bcid 516 36 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 517 37 WIDTH,1 OPT_CONST,0 RET +bcid 518 38 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 519 39 WIDTH,1 OPT_CONST,0 RET +bcid 520 40 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 521 41 WIDTH,1 OPT_CONST,0 RET +bcid 522 42 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 523 43 WIDTH,1 OPT_CONST,0 RET +bcid 524 44 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 525 45 WIDTH,1 OPT_CONST,0 RET +bcid 526 46 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 527 47 WIDTH,1 OPT_CONST,0 RET +bcid 528 48 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 529 49 WIDTH,1 OPT_CONST,0 RET +bcid 530 50 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 531 51 WIDTH,1 OPT_CONST,0 RET +bcid 532 52 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 533 53 WIDTH,1 OPT_CONST,0 RET +bcid 534 54 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 535 55 WIDTH,1 OPT_CONST,0 RET +bcid 536 56 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 537 57 WIDTH,1 OPT_CONST,0 RET +bcid 538 58 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 539 59 WIDTH,1 OPT_CONST,0 RET +bcid 540 60 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 541 61 WIDTH,1 OPT_CONST,0 RET +bcid 542 62 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 543 63 WIDTH,1 OPT_CONST,0 RET +bcid 544 64 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,16 CALL_ARG_VAL,3,0 OPT_CONST,0 MITECONDNOINSTR,4 RET +bcid 545 65 WIDTH,8 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,2 WIDTH,8 SHIFT_L RET +bcid 546 66 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,16 MULTI_CONCATENATE,1,16 CALL_ARG_VAL,3,0 AND RET +bcid 547 67 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,16 CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 RET +bcid 548 68 WIDTH,1 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 RET +bcid 549 69 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,8 CALL_ARG_VAL,3,0 WIDTH,2 CALL_ARG_VAL,4,0 WIDTH,8 PAD ADD CALL_ARG_VAL,3,0 MITECONDNOINSTR,4 RET +bcid 550 70 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,16 CALL_ARG_VAL,3,0 WIDTH,32 PAD WIDTH,16 CALL_ARG_VAL,4,0 WIDTH,32 PAD OPT_CONST,1 SUBTRACT WIDTH,1 M_EQU AND RET +bcid 551 71 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,16 OPT_CONST,0 WIDTH,1 CALL_ARG_VAL,3,0 WIDTH,16 CALL_ARG_VAL,4,0 OPT_CONST,1 ADD CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 552 72 WIDTH,1 CALL_ARG_VAL,2,0 NOT CALL_ARG_VAL,3,0 AND OPT_CONST,1 CALL_ARG_VAL,2,0 CALL_ARG_VAL,4,0 AND OPT_CONST,0 CALL_ARG_VAL,2,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 553 73 WIDTH,16 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,2 WIDTH,16 SHIFT_L ADD RET +bcid 554 74 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,32 CALL_ARG_VAL,3,0 WIDTH,1 CALL_ARG_VAL,4,0 WIDTH,32 CALL_ARG_VAL,5,0 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 555 75 WIDTH,16 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 ADD RET +bcid 556 76 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,16 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,15 WIDTH,1 SLICE,1 WIDTH,2 MULTI_CONCATENATE,1,2 WIDTH,16 CALL_ARG_VAL,3,0 WIDTH,18 CONCATENATE,2 WIDTH,16 CALL_ARG_VAL,4,0 WIDTH,32 OPT_CONST,15 WIDTH,1 SLICE,1 WIDTH,2 MULTI_CONCATENATE,1,2 WIDTH,16 CALL_ARG_VAL,4,0 WIDTH,18 CONCATENATE,2 ADD WIDTH,16 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,15 WIDTH,1 SLICE,1 WIDTH,2 MULTI_CONCATENATE,1,2 WIDTH,16 CALL_ARG_VAL,3,0 WIDTH,18 CONCATENATE,2 MITECONDNOINSTR,4 RET +bcid 557 77 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,15 CALL_ARG_VAL,3,0 WIDTH,16 CONCATENATE,2 WIDTH,1 CALL_ARG_VAL,4,0 WIDTH,16 PAD ADD RET +bcid 558 78 WIDTH,4 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,0 MITECONDNOINSTR,4 RET +bcid 559 79 WIDTH,4 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 RET +bcid 560 80 WIDTH,4 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,2 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 RET +bcid 561 81 WIDTH,4 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,3 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 RET +bcid 562 82 WIDTH,8 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 WIDTH,16 CALL_ARG_VAL,3,0 OPT_CONST,0 MITECONDNOINSTR,4 RET +bcid 563 83 WIDTH,8 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 WIDTH,16 CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 RET +bcid 564 84 WIDTH,8 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,2 WIDTH,1 SLICE,1 WIDTH,16 CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 RET +bcid 565 85 WIDTH,8 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,3 WIDTH,1 SLICE,1 WIDTH,16 CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 RET +bcid 566 86 WIDTH,8 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,4 WIDTH,1 SLICE,1 WIDTH,16 CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 RET +bcid 567 87 WIDTH,8 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,5 WIDTH,1 SLICE,1 WIDTH,16 CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 RET +bcid 568 88 WIDTH,8 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,6 WIDTH,1 SLICE,1 WIDTH,16 CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 RET +bcid 569 89 WIDTH,8 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,7 WIDTH,1 SLICE,1 WIDTH,16 CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 RET +bcid 570 90 WIDTH,4 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,3 WIDTH,1 SLICE,1 WIDTH,8 MULTI_CONCATENATE,1,8 WIDTH,4 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,2 WIDTH,1 SLICE,1 WIDTH,8 MULTI_CONCATENATE,1,8 WIDTH,4 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 WIDTH,8 MULTI_CONCATENATE,1,8 WIDTH,4 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 WIDTH,8 MULTI_CONCATENATE,1,8 WIDTH,32 CONCATENATE,4 RET +bcid 571 91 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,32 MULTI_CONCATENATE,1,32 NOT CALL_ARG_VAL,3,0 AND WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,32 MULTI_CONCATENATE,1,32 CALL_ARG_VAL,4,0 AND OR RET +bcid 572 92 WIDTH,1 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 WIDTH,32 CALL_ARG_VAL,5,0 OPT_CONST,-1 SUBTRACT CALL_ARG_VAL,5,0 OPT_CONST,-1 ADD MITECONDNOINSTR,4 CALL_ARG_VAL,5,0 MITECONDNOINSTR,4 CALL_ARG_VAL,6,0 NOT NOT MITECONDNOINSTR,4 RET +bcid 573 93 WIDTH,32 CALL_ARG_VAL,2,0 WIDTH,1 CALL_ARG_VAL,3,0 WIDTH,32 MULTI_CONCATENATE,1,32 WIDTH,1 M_EQU RET +bcid 574 94 WIDTH,3 CALL_ARG_VAL,2,0 OPT_CONST,0 WIDTH,1 M_NEQU RET +bcid 575 95 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,8 MULTI_CONCATENATE,1,8 WIDTH,1 CALL_ARG_VAL,3,0 WIDTH,8 MULTI_CONCATENATE,1,8 WIDTH,1 CALL_ARG_VAL,4,0 WIDTH,8 MULTI_CONCATENATE,1,8 WIDTH,1 CALL_ARG_VAL,5,0 WIDTH,8 MULTI_CONCATENATE,1,8 WIDTH,32 CONCATENATE,4 RET +sid tsdn28hpcpuhdb128x128m4mw_170a +bcid 576 0 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 577 1 WIDTH,1 OPT_CONST,0 RET +bcid 578 2 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 579 3 WIDTH,1 OPT_CONST,0 RET +bcid 580 4 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 581 5 WIDTH,1 OPT_CONST,0 RET +bcid 582 6 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 583 7 WIDTH,1 OPT_CONST,0 RET +bcid 584 8 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 585 9 WIDTH,1 OPT_CONST,0 RET +bcid 586 10 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 587 11 WIDTH,1 OPT_CONST,0 RET +bcid 588 12 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 589 13 WIDTH,1 OPT_CONST,0 RET +bcid 590 14 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 591 15 WIDTH,1 OPT_CONST,0 RET +bcid 592 16 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 593 17 WIDTH,1 OPT_CONST,0 RET +bcid 594 18 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 595 19 WIDTH,1 OPT_CONST,0 RET +bcid 596 20 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 597 21 WIDTH,1 OPT_CONST,0 RET +bcid 598 22 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 599 23 WIDTH,1 OPT_CONST,0 RET +bcid 600 24 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 601 25 WIDTH,1 OPT_CONST,0 RET +bcid 602 26 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 603 27 WIDTH,1 OPT_CONST,0 RET +bcid 604 28 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 605 29 WIDTH,1 OPT_CONST,0 RET +bcid 606 30 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 607 31 WIDTH,1 OPT_CONST,0 RET +bcid 608 32 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 609 33 WIDTH,1 OPT_CONST,0 RET +bcid 610 34 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 611 35 WIDTH,1 OPT_CONST,0 RET +bcid 612 36 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 613 37 WIDTH,1 OPT_CONST,0 RET +bcid 614 38 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 615 39 WIDTH,1 OPT_CONST,0 RET +bcid 616 40 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 617 41 WIDTH,1 OPT_CONST,0 RET +bcid 618 42 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 619 43 WIDTH,1 OPT_CONST,0 RET +bcid 620 44 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 621 45 WIDTH,1 OPT_CONST,0 RET +bcid 622 46 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 623 47 WIDTH,1 OPT_CONST,0 RET +bcid 624 48 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 625 49 WIDTH,1 OPT_CONST,0 RET +bcid 626 50 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 627 51 WIDTH,1 OPT_CONST,0 RET +bcid 628 52 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 629 53 WIDTH,1 OPT_CONST,0 RET +bcid 630 54 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 631 55 WIDTH,1 OPT_CONST,0 RET +bcid 632 56 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 633 57 WIDTH,1 OPT_CONST,0 RET +bcid 634 58 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 635 59 WIDTH,1 OPT_CONST,0 RET +bcid 636 60 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 637 61 WIDTH,1 OPT_CONST,0 RET +bcid 638 62 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 639 63 WIDTH,1 OPT_CONST,0 RET +bcid 640 64 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 641 65 WIDTH,1 OPT_CONST,0 RET +bcid 642 66 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 643 67 WIDTH,1 OPT_CONST,0 RET +bcid 644 68 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 645 69 WIDTH,1 OPT_CONST,0 RET +bcid 646 70 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 647 71 WIDTH,1 OPT_CONST,0 RET +bcid 648 72 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 649 73 WIDTH,1 OPT_CONST,0 RET +bcid 650 74 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 651 75 WIDTH,1 OPT_CONST,0 RET +bcid 652 76 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 653 77 WIDTH,1 OPT_CONST,0 RET +bcid 654 78 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 655 79 WIDTH,1 OPT_CONST,0 RET +bcid 656 80 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 657 81 WIDTH,1 OPT_CONST,0 RET +bcid 658 82 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 659 83 WIDTH,1 OPT_CONST,0 RET +bcid 660 84 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 661 85 WIDTH,1 OPT_CONST,0 RET +bcid 662 86 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 663 87 WIDTH,1 OPT_CONST,0 RET +bcid 664 88 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 665 89 WIDTH,1 OPT_CONST,0 RET +bcid 666 90 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 667 91 WIDTH,1 OPT_CONST,0 RET +bcid 668 92 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 669 93 WIDTH,1 OPT_CONST,0 RET +bcid 670 94 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 671 95 WIDTH,1 OPT_CONST,0 RET +bcid 672 96 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 673 97 WIDTH,1 OPT_CONST,0 RET +bcid 674 98 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 675 99 WIDTH,1 OPT_CONST,0 RET +bcid 676 100 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 677 101 WIDTH,1 OPT_CONST,0 RET +bcid 678 102 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 679 103 WIDTH,1 OPT_CONST,0 RET +bcid 680 104 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 681 105 WIDTH,1 OPT_CONST,0 RET +bcid 682 106 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 683 107 WIDTH,1 OPT_CONST,0 RET +bcid 684 108 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 685 109 WIDTH,1 OPT_CONST,0 RET +bcid 686 110 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 687 111 WIDTH,1 OPT_CONST,0 RET +bcid 688 112 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 689 113 WIDTH,1 OPT_CONST,0 RET +bcid 690 114 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 691 115 WIDTH,1 OPT_CONST,0 RET +bcid 692 116 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 693 117 WIDTH,1 OPT_CONST,0 RET +bcid 694 118 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 695 119 WIDTH,1 OPT_CONST,0 RET +bcid 696 120 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 697 121 WIDTH,1 OPT_CONST,0 RET +bcid 698 122 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 699 123 WIDTH,1 OPT_CONST,0 RET +bcid 700 124 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 701 125 WIDTH,1 OPT_CONST,0 RET +bcid 702 126 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 703 127 WIDTH,1 OPT_CONST,0 RET +bcid 704 128 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 705 129 WIDTH,1 OPT_CONST,0 RET +bcid 706 130 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 707 131 WIDTH,1 OPT_CONST,0 RET +bcid 708 132 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 709 133 WIDTH,1 OPT_CONST,0 RET +bcid 710 134 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 711 135 WIDTH,1 OPT_CONST,0 RET +bcid 712 136 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 713 137 WIDTH,1 OPT_CONST,0 RET +bcid 714 138 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 715 139 WIDTH,1 OPT_CONST,0 RET +bcid 716 140 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 717 141 WIDTH,1 OPT_CONST,0 RET +bcid 718 142 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 719 143 WIDTH,1 OPT_CONST,0 RET +bcid 720 144 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 721 145 WIDTH,1 OPT_CONST,0 RET +bcid 722 146 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 723 147 WIDTH,1 OPT_CONST,0 RET +bcid 724 148 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 725 149 WIDTH,1 OPT_CONST,0 RET +bcid 726 150 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 727 151 WIDTH,1 OPT_CONST,0 RET +bcid 728 152 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 729 153 WIDTH,1 OPT_CONST,0 RET +bcid 730 154 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 731 155 WIDTH,1 OPT_CONST,0 RET +bcid 732 156 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 733 157 WIDTH,1 OPT_CONST,0 RET +bcid 734 158 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 735 159 WIDTH,1 OPT_CONST,0 RET +bcid 736 160 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 737 161 WIDTH,1 OPT_CONST,0 RET +bcid 738 162 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 739 163 WIDTH,1 OPT_CONST,0 RET +bcid 740 164 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 741 165 WIDTH,1 OPT_CONST,0 RET +bcid 742 166 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 743 167 WIDTH,1 OPT_CONST,0 RET +bcid 744 168 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 745 169 WIDTH,1 OPT_CONST,0 RET +bcid 746 170 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 747 171 WIDTH,1 OPT_CONST,0 RET +bcid 748 172 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 749 173 WIDTH,1 OPT_CONST,0 RET +bcid 750 174 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 751 175 WIDTH,1 OPT_CONST,0 RET +bcid 752 176 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 753 177 WIDTH,1 OPT_CONST,0 RET +bcid 754 178 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 755 179 WIDTH,1 OPT_CONST,0 RET +bcid 756 180 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 757 181 WIDTH,1 OPT_CONST,0 RET +bcid 758 182 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 759 183 WIDTH,1 OPT_CONST,0 RET +bcid 760 184 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 761 185 WIDTH,1 OPT_CONST,0 RET +bcid 762 186 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 763 187 WIDTH,1 OPT_CONST,0 RET +bcid 764 188 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 765 189 WIDTH,1 OPT_CONST,0 RET +bcid 766 190 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 767 191 WIDTH,1 OPT_CONST,0 RET +bcid 768 192 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 769 193 WIDTH,1 OPT_CONST,0 RET +bcid 770 194 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 771 195 WIDTH,1 OPT_CONST,0 RET +bcid 772 196 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 773 197 WIDTH,1 OPT_CONST,0 RET +bcid 774 198 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 775 199 WIDTH,1 OPT_CONST,0 RET +bcid 776 200 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 777 201 WIDTH,1 OPT_CONST,0 RET +bcid 778 202 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 779 203 WIDTH,1 OPT_CONST,0 RET +bcid 780 204 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 781 205 WIDTH,1 OPT_CONST,0 RET +bcid 782 206 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 783 207 WIDTH,1 OPT_CONST,0 RET +bcid 784 208 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 785 209 WIDTH,1 OPT_CONST,0 RET +bcid 786 210 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 787 211 WIDTH,1 OPT_CONST,0 RET +bcid 788 212 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 789 213 WIDTH,1 OPT_CONST,0 RET +bcid 790 214 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 791 215 WIDTH,1 OPT_CONST,0 RET +bcid 792 216 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 793 217 WIDTH,1 OPT_CONST,0 RET +bcid 794 218 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 795 219 WIDTH,1 OPT_CONST,0 RET +bcid 796 220 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 797 221 WIDTH,1 OPT_CONST,0 RET +bcid 798 222 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 799 223 WIDTH,1 OPT_CONST,0 RET +bcid 800 224 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 801 225 WIDTH,1 OPT_CONST,0 RET +bcid 802 226 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 803 227 WIDTH,1 OPT_CONST,0 RET +bcid 804 228 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 805 229 WIDTH,1 OPT_CONST,0 RET +bcid 806 230 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 807 231 WIDTH,1 OPT_CONST,0 RET +bcid 808 232 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 809 233 WIDTH,1 OPT_CONST,0 RET +bcid 810 234 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 811 235 WIDTH,1 OPT_CONST,0 RET +bcid 812 236 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 813 237 WIDTH,1 OPT_CONST,0 RET +bcid 814 238 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 815 239 WIDTH,1 OPT_CONST,0 RET +bcid 816 240 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 817 241 WIDTH,1 OPT_CONST,0 RET +bcid 818 242 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 819 243 WIDTH,1 OPT_CONST,0 RET +bcid 820 244 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 821 245 WIDTH,1 OPT_CONST,0 RET +bcid 822 246 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 823 247 WIDTH,1 OPT_CONST,0 RET +bcid 824 248 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 825 249 WIDTH,1 OPT_CONST,0 RET +bcid 826 250 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 827 251 WIDTH,1 OPT_CONST,0 RET +bcid 828 252 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 829 253 WIDTH,1 OPT_CONST,0 RET +bcid 830 254 WIDTH,1 OPT_CONST_4ST,1,1 RET +bcid 831 255 WIDTH,1 OPT_CONST,0 RET +sid debug_top +bcid 832 0 WIDTH,1 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 NOT WIDTH,10 CALL_ARG_VAL,4,0 OPT_CONST,1023 WIDTH,1 M_EQU AND CALL_ARG_VAL,3,0 WIDTH,10 CALL_ARG_VAL,4,0 OPT_CONST,127 WIDTH,1 M_EQU AND OR AND RET +bcid 833 1 WIDTH,1 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 WIDTH,10 CALL_ARG_VAL,4,0 WIDTH,1 CALL_ARG_VAL,5,0 WIDTH,10 CALL_ARG_VAL,4,0 OPT_CONST,1 ADD CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 OPT_CONST,0 MITECONDNOINSTR,4 RET +bcid 834 2 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,32 MULTI_CONCATENATE,1,32 WIDTH,16 CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 WIDTH,32 CONCATENATE,2 AND WIDTH,1 CALL_ARG_VAL,5,0 WIDTH,32 MULTI_CONCATENATE,1,32 WIDTH,16 CALL_ARG_VAL,6,0 CALL_ARG_VAL,7,0 WIDTH,32 CONCATENATE,2 AND OR WIDTH,1 CALL_ARG_VAL,8,0 WIDTH,32 MULTI_CONCATENATE,1,32 WIDTH,16 CALL_ARG_VAL,9,0 CALL_ARG_VAL,10,0 WIDTH,32 CONCATENATE,2 AND WIDTH,1 CALL_ARG_VAL,11,0 WIDTH,32 MULTI_CONCATENATE,1,32 WIDTH,16 CALL_ARG_VAL,12,0 CALL_ARG_VAL,13,0 WIDTH,32 CONCATENATE,2 AND OR OR RET +bcid 835 3 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,32 CALL_ARG_VAL,3,0 WIDTH,256 CALL_ARG_VAL,4,0 WIDTH,32 OPT_CONST,32 WIDTH,224 SLICE,1 WIDTH,256 CONCATENATE,2 CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 RET +bcid 836 4 WIDTH,3 CALL_ARG_VAL,2,0 OPT_CONST,7 WIDTH,1 M_EQU CALL_ARG_VAL,3,0 AND NOT RET +bcid 837 5 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,256 CALL_ARG_VAL,3,0 WIDTH,1 CALL_ARG_VAL,4,0 WIDTH,256 CALL_ARG_VAL,5,0 WIDTH,1 CALL_ARG_VAL,6,0 WIDTH,256 CALL_ARG_VAL,7,0 WIDTH,1 CALL_ARG_VAL,8,0 WIDTH,256 CALL_ARG_VAL,9,0 CONST,0,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 838 6 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,12 CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 RET +bcid 839 7 WIDTH,1 CALL_ARG_VAL,2,0 CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 RET +bcid 840 8 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,256 CALL_ARG_VAL,3,0 CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 RET +bcid 841 9 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,0 WIDTH,1 SLICE,1 WIDTH,8 MULTI_CONCATENATE,1,8 RET +bcid 842 10 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,1 WIDTH,1 SLICE,1 WIDTH,8 MULTI_CONCATENATE,1,8 RET +bcid 843 11 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,2 WIDTH,1 SLICE,1 WIDTH,8 MULTI_CONCATENATE,1,8 RET +bcid 844 12 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,3 WIDTH,1 SLICE,1 WIDTH,8 MULTI_CONCATENATE,1,8 RET +bcid 845 13 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,4 WIDTH,1 SLICE,1 WIDTH,8 MULTI_CONCATENATE,1,8 RET +bcid 846 14 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,5 WIDTH,1 SLICE,1 WIDTH,8 MULTI_CONCATENATE,1,8 RET +bcid 847 15 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,6 WIDTH,1 SLICE,1 WIDTH,8 MULTI_CONCATENATE,1,8 RET +bcid 848 16 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,7 WIDTH,1 SLICE,1 WIDTH,8 MULTI_CONCATENATE,1,8 RET +bcid 849 17 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,8 WIDTH,1 SLICE,1 WIDTH,8 MULTI_CONCATENATE,1,8 RET +bcid 850 18 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,9 WIDTH,1 SLICE,1 WIDTH,8 MULTI_CONCATENATE,1,8 RET +bcid 851 19 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,10 WIDTH,1 SLICE,1 WIDTH,8 MULTI_CONCATENATE,1,8 RET +bcid 852 20 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,11 WIDTH,1 SLICE,1 WIDTH,8 MULTI_CONCATENATE,1,8 RET +bcid 853 21 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,12 WIDTH,1 SLICE,1 WIDTH,8 MULTI_CONCATENATE,1,8 RET +bcid 854 22 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,13 WIDTH,1 SLICE,1 WIDTH,8 MULTI_CONCATENATE,1,8 RET +bcid 855 23 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,14 WIDTH,1 SLICE,1 WIDTH,8 MULTI_CONCATENATE,1,8 RET +bcid 856 24 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,15 WIDTH,1 SLICE,1 WIDTH,8 MULTI_CONCATENATE,1,8 RET +bcid 857 25 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,16 WIDTH,1 SLICE,1 WIDTH,8 MULTI_CONCATENATE,1,8 RET +bcid 858 26 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,17 WIDTH,1 SLICE,1 WIDTH,8 MULTI_CONCATENATE,1,8 RET +bcid 859 27 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,18 WIDTH,1 SLICE,1 WIDTH,8 MULTI_CONCATENATE,1,8 RET +bcid 860 28 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,19 WIDTH,1 SLICE,1 WIDTH,8 MULTI_CONCATENATE,1,8 RET +bcid 861 29 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,20 WIDTH,1 SLICE,1 WIDTH,8 MULTI_CONCATENATE,1,8 RET +bcid 862 30 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,21 WIDTH,1 SLICE,1 WIDTH,8 MULTI_CONCATENATE,1,8 RET +bcid 863 31 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,22 WIDTH,1 SLICE,1 WIDTH,8 MULTI_CONCATENATE,1,8 RET +bcid 864 32 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,23 WIDTH,1 SLICE,1 WIDTH,8 MULTI_CONCATENATE,1,8 RET +bcid 865 33 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,24 WIDTH,1 SLICE,1 WIDTH,8 MULTI_CONCATENATE,1,8 RET +bcid 866 34 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,25 WIDTH,1 SLICE,1 WIDTH,8 MULTI_CONCATENATE,1,8 RET +bcid 867 35 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,26 WIDTH,1 SLICE,1 WIDTH,8 MULTI_CONCATENATE,1,8 RET +bcid 868 36 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,27 WIDTH,1 SLICE,1 WIDTH,8 MULTI_CONCATENATE,1,8 RET +bcid 869 37 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,28 WIDTH,1 SLICE,1 WIDTH,8 MULTI_CONCATENATE,1,8 RET +bcid 870 38 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,29 WIDTH,1 SLICE,1 WIDTH,8 MULTI_CONCATENATE,1,8 RET +bcid 871 39 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,30 WIDTH,1 SLICE,1 WIDTH,8 MULTI_CONCATENATE,1,8 RET +bcid 872 40 WIDTH,32 CALL_ARG_VAL,2,0 OPT_CONST,31 WIDTH,1 SLICE,1 WIDTH,8 MULTI_CONCATENATE,1,8 RET +sid digital_top +bcid 873 0 WIDTH,17 OPT_CONST,0 RET +bcid 874 1 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,12 WIDTH,3 SLICE,1 WIDTH,1 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,5,0 WIDTH,32 OPT_CONST,12 WIDTH,3 SLICE,1 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 875 2 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,11 WIDTH,1 SLICE,1 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,5,0 WIDTH,32 OPT_CONST,11 WIDTH,1 SLICE,1 CALL_ARG_VAL,6,0 OPT_CONST,1 EQU WIDTH,12 CALL_ARG_VAL,7,0 WIDTH,32 OPT_CONST,11 WIDTH,1 SLICE,1 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 876 3 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,8 WIDTH,3 SLICE,1 WIDTH,1 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,5,0 WIDTH,32 OPT_CONST,8 WIDTH,3 SLICE,1 WIDTH,1 CALL_ARG_VAL,6,0 OPT_CONST,1 EQU WIDTH,11 CALL_ARG_VAL,7,0 WIDTH,32 OPT_CONST,8 WIDTH,3 SLICE,1 WIDTH,1 CALL_ARG_VAL,8,0 OPT_CONST,1 EQU WIDTH,11 CALL_ARG_VAL,9,0 WIDTH,32 OPT_CONST,8 WIDTH,3 SLICE,1 WIDTH,1 CALL_ARG_VAL,10,0 OPT_CONST,1 EQU WIDTH,12 CALL_ARG_VAL,11,0 WIDTH,32 OPT_CONST,8 WIDTH,3 SLICE,1 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 877 4 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 EQU WIDTH,8 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,7 WIDTH,1 SLICE,1 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,5,0 WIDTH,32 OPT_CONST,7 WIDTH,1 SLICE,1 CALL_ARG_VAL,6,0 OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,7,0 WIDTH,32 OPT_CONST,7 WIDTH,1 SLICE,1 CALL_ARG_VAL,8,0 OPT_CONST,1 EQU WIDTH,11 CALL_ARG_VAL,9,0 WIDTH,32 OPT_CONST,7 WIDTH,1 SLICE,1 CALL_ARG_VAL,10,0 OPT_CONST,1 EQU WIDTH,11 CALL_ARG_VAL,11,0 WIDTH,32 OPT_CONST,7 WIDTH,1 SLICE,1 CALL_ARG_VAL,12,0 OPT_CONST,1 EQU WIDTH,12 CALL_ARG_VAL,13,0 WIDTH,32 OPT_CONST,7 WIDTH,1 SLICE,1 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 878 5 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 EQU WIDTH,8 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,6 WIDTH,1 SLICE,1 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,5,0 WIDTH,32 OPT_CONST,6 WIDTH,1 SLICE,1 CALL_ARG_VAL,6,0 OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,7,0 WIDTH,32 OPT_CONST,6 WIDTH,1 SLICE,1 CALL_ARG_VAL,8,0 OPT_CONST,1 EQU WIDTH,11 CALL_ARG_VAL,9,0 WIDTH,32 OPT_CONST,6 WIDTH,1 SLICE,1 CALL_ARG_VAL,10,0 OPT_CONST,1 EQU WIDTH,11 CALL_ARG_VAL,11,0 WIDTH,32 OPT_CONST,6 WIDTH,1 SLICE,1 CALL_ARG_VAL,12,0 OPT_CONST,1 EQU WIDTH,7 CALL_ARG_VAL,13,0 WIDTH,32 OPT_CONST,6 WIDTH,1 SLICE,1 CALL_ARG_VAL,14,0 OPT_CONST,1 EQU WIDTH,12 CALL_ARG_VAL,15,0 WIDTH,32 OPT_CONST,6 WIDTH,1 SLICE,1 CALL_ARG_VAL,16,0 OPT_CONST,1 EQU WIDTH,7 CALL_ARG_VAL,17,0 WIDTH,32 OPT_CONST,6 WIDTH,1 SLICE,1 CALL_ARG_VAL,18,0 OPT_CONST,1 EQU WIDTH,7 CALL_ARG_VAL,19,0 WIDTH,32 OPT_CONST,6 WIDTH,1 SLICE,1 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 879 6 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 EQU WIDTH,8 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,5 WIDTH,1 SLICE,1 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,5,0 WIDTH,32 OPT_CONST,5 WIDTH,1 SLICE,1 CALL_ARG_VAL,6,0 OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,7,0 WIDTH,32 OPT_CONST,5 WIDTH,1 SLICE,1 CALL_ARG_VAL,8,0 OPT_CONST,1 EQU WIDTH,11 CALL_ARG_VAL,9,0 WIDTH,32 OPT_CONST,5 WIDTH,1 SLICE,1 CALL_ARG_VAL,10,0 OPT_CONST,1 EQU WIDTH,11 CALL_ARG_VAL,11,0 WIDTH,32 OPT_CONST,5 WIDTH,1 SLICE,1 CALL_ARG_VAL,12,0 OPT_CONST,1 EQU WIDTH,7 CALL_ARG_VAL,13,0 WIDTH,32 OPT_CONST,5 WIDTH,1 SLICE,1 CALL_ARG_VAL,14,0 OPT_CONST,1 EQU WIDTH,12 CALL_ARG_VAL,15,0 WIDTH,32 OPT_CONST,5 WIDTH,1 SLICE,1 CALL_ARG_VAL,16,0 OPT_CONST,1 EQU WIDTH,7 CALL_ARG_VAL,17,0 WIDTH,32 OPT_CONST,5 WIDTH,1 SLICE,1 CALL_ARG_VAL,18,0 OPT_CONST,1 EQU WIDTH,6 CALL_ARG_VAL,19,0 WIDTH,32 OPT_CONST,5 WIDTH,1 SLICE,1 CALL_ARG_VAL,20,0 OPT_CONST,1 EQU WIDTH,7 CALL_ARG_VAL,21,0 WIDTH,32 OPT_CONST,5 WIDTH,1 SLICE,1 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 880 7 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 EQU WIDTH,8 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,4 WIDTH,1 SLICE,1 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,5,0 WIDTH,32 OPT_CONST,4 WIDTH,1 SLICE,1 CALL_ARG_VAL,6,0 OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,7,0 WIDTH,32 OPT_CONST,4 WIDTH,1 SLICE,1 CALL_ARG_VAL,8,0 OPT_CONST,1 EQU WIDTH,11 CALL_ARG_VAL,9,0 WIDTH,32 OPT_CONST,4 WIDTH,1 SLICE,1 CALL_ARG_VAL,10,0 OPT_CONST,1 EQU WIDTH,11 CALL_ARG_VAL,11,0 WIDTH,32 OPT_CONST,4 WIDTH,1 SLICE,1 CALL_ARG_VAL,12,0 OPT_CONST,1 EQU WIDTH,5 CALL_ARG_VAL,13,0 WIDTH,32 OPT_CONST,4 WIDTH,1 SLICE,1 CALL_ARG_VAL,14,0 OPT_CONST,1 EQU WIDTH,7 CALL_ARG_VAL,15,0 WIDTH,32 OPT_CONST,4 WIDTH,1 SLICE,1 CALL_ARG_VAL,16,0 OPT_CONST,1 EQU WIDTH,12 CALL_ARG_VAL,17,0 WIDTH,32 OPT_CONST,4 WIDTH,1 SLICE,1 CALL_ARG_VAL,18,0 OPT_CONST,1 EQU WIDTH,7 CALL_ARG_VAL,19,0 WIDTH,32 OPT_CONST,4 WIDTH,1 SLICE,1 CALL_ARG_VAL,20,0 OPT_CONST,1 EQU WIDTH,6 CALL_ARG_VAL,21,0 WIDTH,32 OPT_CONST,4 WIDTH,1 SLICE,1 CALL_ARG_VAL,22,0 OPT_CONST,1 EQU WIDTH,7 CALL_ARG_VAL,23,0 WIDTH,32 OPT_CONST,4 WIDTH,1 SLICE,1 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 881 8 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 EQU WIDTH,8 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,5,0 WIDTH,32 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,6,0 OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,7,0 WIDTH,32 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,8,0 OPT_CONST,1 EQU WIDTH,4 CALL_ARG_VAL,9,0 WIDTH,32 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,10,0 OPT_CONST,1 EQU WIDTH,11 CALL_ARG_VAL,11,0 WIDTH,32 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,12,0 OPT_CONST,1 EQU WIDTH,11 CALL_ARG_VAL,13,0 WIDTH,32 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,14,0 OPT_CONST,1 EQU WIDTH,5 CALL_ARG_VAL,15,0 WIDTH,32 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,16,0 OPT_CONST,1 EQU WIDTH,7 CALL_ARG_VAL,17,0 WIDTH,32 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,18,0 OPT_CONST,1 EQU WIDTH,12 CALL_ARG_VAL,19,0 WIDTH,32 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,20,0 OPT_CONST,1 EQU WIDTH,7 CALL_ARG_VAL,21,0 WIDTH,32 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,22,0 OPT_CONST,1 EQU WIDTH,6 CALL_ARG_VAL,23,0 WIDTH,32 OPT_CONST,3 WIDTH,1 SLICE,1 CALL_ARG_VAL,24,0 OPT_CONST,1 EQU WIDTH,7 CALL_ARG_VAL,25,0 WIDTH,32 OPT_CONST,3 WIDTH,1 SLICE,1 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 882 9 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 EQU WIDTH,8 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,2 WIDTH,1 SLICE,1 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU WIDTH,3 CALL_ARG_VAL,5,0 WIDTH,32 OPT_CONST,2 WIDTH,1 SLICE,1 CALL_ARG_VAL,6,0 OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,7,0 WIDTH,32 OPT_CONST,2 WIDTH,1 SLICE,1 CALL_ARG_VAL,8,0 OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,9,0 WIDTH,32 OPT_CONST,2 WIDTH,1 SLICE,1 CALL_ARG_VAL,10,0 OPT_CONST,1 EQU WIDTH,4 CALL_ARG_VAL,11,0 WIDTH,32 OPT_CONST,2 WIDTH,1 SLICE,1 CALL_ARG_VAL,12,0 OPT_CONST,1 EQU WIDTH,11 CALL_ARG_VAL,13,0 WIDTH,32 OPT_CONST,2 WIDTH,1 SLICE,1 CALL_ARG_VAL,14,0 OPT_CONST,1 EQU WIDTH,11 CALL_ARG_VAL,15,0 WIDTH,32 OPT_CONST,2 WIDTH,1 SLICE,1 CALL_ARG_VAL,16,0 OPT_CONST,1 EQU WIDTH,5 CALL_ARG_VAL,17,0 WIDTH,32 OPT_CONST,2 WIDTH,1 SLICE,1 CALL_ARG_VAL,18,0 OPT_CONST,1 EQU WIDTH,7 CALL_ARG_VAL,19,0 WIDTH,32 OPT_CONST,2 WIDTH,1 SLICE,1 CALL_ARG_VAL,20,0 OPT_CONST,1 EQU WIDTH,12 CALL_ARG_VAL,21,0 WIDTH,32 OPT_CONST,2 WIDTH,1 SLICE,1 CALL_ARG_VAL,22,0 OPT_CONST,1 EQU WIDTH,3 CALL_ARG_VAL,23,0 WIDTH,32 OPT_CONST,2 WIDTH,1 SLICE,1 CALL_ARG_VAL,24,0 OPT_CONST,1 EQU WIDTH,3 CALL_ARG_VAL,25,0 WIDTH,32 OPT_CONST,2 WIDTH,1 SLICE,1 CALL_ARG_VAL,26,0 OPT_CONST,1 EQU WIDTH,7 CALL_ARG_VAL,27,0 WIDTH,32 OPT_CONST,2 WIDTH,1 SLICE,1 CALL_ARG_VAL,28,0 OPT_CONST,1 EQU WIDTH,6 CALL_ARG_VAL,29,0 WIDTH,32 OPT_CONST,2 WIDTH,1 SLICE,1 CALL_ARG_VAL,30,0 OPT_CONST,1 EQU WIDTH,3 CALL_ARG_VAL,31,0 WIDTH,32 OPT_CONST,2 WIDTH,1 SLICE,1 CALL_ARG_VAL,32,0 OPT_CONST,1 EQU WIDTH,7 CALL_ARG_VAL,33,0 WIDTH,32 OPT_CONST,2 WIDTH,1 SLICE,1 CALL_ARG_VAL,34,0 OPT_CONST,1 EQU WIDTH,3 CALL_ARG_VAL,35,0 WIDTH,32 OPT_CONST,2 WIDTH,1 SLICE,1 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 883 10 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 EQU WIDTH,2 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU WIDTH,2 CALL_ARG_VAL,5,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,6,0 OPT_CONST,1 EQU WIDTH,8 CALL_ARG_VAL,7,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,8,0 OPT_CONST,1 EQU WIDTH,3 CALL_ARG_VAL,9,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,10,0 OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,11,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,12,0 OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,13,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,14,0 OPT_CONST,1 EQU WIDTH,4 CALL_ARG_VAL,15,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,16,0 OPT_CONST,1 EQU WIDTH,11 CALL_ARG_VAL,17,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,18,0 OPT_CONST,1 EQU WIDTH,11 CALL_ARG_VAL,19,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,20,0 OPT_CONST,1 EQU WIDTH,5 CALL_ARG_VAL,21,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,22,0 OPT_CONST,1 EQU WIDTH,7 CALL_ARG_VAL,23,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,24,0 OPT_CONST,1 EQU WIDTH,12 CALL_ARG_VAL,25,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,26,0 OPT_CONST,1 EQU WIDTH,3 CALL_ARG_VAL,27,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,28,0 OPT_CONST,1 EQU WIDTH,3 CALL_ARG_VAL,29,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,30,0 OPT_CONST,1 EQU WIDTH,7 CALL_ARG_VAL,31,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,32,0 OPT_CONST,1 EQU WIDTH,6 CALL_ARG_VAL,33,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,34,0 OPT_CONST,1 EQU WIDTH,3 CALL_ARG_VAL,35,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,36,0 OPT_CONST,1 EQU WIDTH,7 CALL_ARG_VAL,37,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 CALL_ARG_VAL,38,0 OPT_CONST,1 EQU WIDTH,3 CALL_ARG_VAL,39,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 884 11 WIDTH,1 CALL_ARG_VAL,2,0 OPT_CONST,1 EQU WIDTH,2 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,4,0 OPT_CONST,1 EQU WIDTH,2 CALL_ARG_VAL,5,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,6,0 OPT_CONST,1 EQU CALL_ARG_VAL,7,0 CALL_ARG_VAL,8,0 OPT_CONST,1 EQU WIDTH,8 CALL_ARG_VAL,9,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,10,0 OPT_CONST,1 EQU WIDTH,3 CALL_ARG_VAL,11,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,12,0 OPT_CONST,1 EQU CALL_ARG_VAL,13,0 CALL_ARG_VAL,14,0 OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,15,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,16,0 OPT_CONST,1 EQU WIDTH,15 CALL_ARG_VAL,17,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,18,0 OPT_CONST,1 EQU WIDTH,4 CALL_ARG_VAL,19,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,20,0 OPT_CONST,1 EQU WIDTH,11 CALL_ARG_VAL,21,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,22,0 OPT_CONST,1 EQU WIDTH,11 CALL_ARG_VAL,23,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,24,0 OPT_CONST,1 EQU WIDTH,5 CALL_ARG_VAL,25,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,26,0 OPT_CONST,1 EQU WIDTH,7 CALL_ARG_VAL,27,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,28,0 OPT_CONST,1 EQU WIDTH,12 CALL_ARG_VAL,29,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,30,0 OPT_CONST,1 EQU WIDTH,3 CALL_ARG_VAL,31,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,32,0 OPT_CONST,1 EQU WIDTH,3 CALL_ARG_VAL,33,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,34,0 OPT_CONST,1 EQU WIDTH,7 CALL_ARG_VAL,35,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,36,0 OPT_CONST,1 EQU WIDTH,6 CALL_ARG_VAL,37,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,38,0 OPT_CONST,1 EQU WIDTH,3 CALL_ARG_VAL,39,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,40,0 OPT_CONST,1 EQU WIDTH,7 CALL_ARG_VAL,41,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 CALL_ARG_VAL,42,0 OPT_CONST,1 EQU WIDTH,3 CALL_ARG_VAL,43,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 885 12 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,2 PAD RET +bcid 886 13 WIDTH,6 CALL_ARG_VAL,2,0 OPT_CONST,0 WIDTH,1 M_EQU RET +bcid 887 14 WIDTH,6 CALL_ARG_VAL,2,0 OPT_CONST,1 WIDTH,1 M_EQU RET +bcid 888 15 WIDTH,6 CALL_ARG_VAL,2,0 OPT_CONST,2 WIDTH,1 M_EQU RET +bcid 889 16 WIDTH,6 CALL_ARG_VAL,2,0 OPT_CONST,3 WIDTH,1 M_EQU RET +bcid 890 17 WIDTH,6 CALL_ARG_VAL,2,0 OPT_CONST,4 WIDTH,1 M_EQU RET +bcid 891 18 WIDTH,6 CALL_ARG_VAL,2,0 OPT_CONST,5 WIDTH,1 M_EQU RET +bcid 892 19 WIDTH,6 CALL_ARG_VAL,2,0 OPT_CONST,6 WIDTH,1 M_EQU RET +bcid 893 20 WIDTH,6 CALL_ARG_VAL,2,0 OPT_CONST,7 WIDTH,1 M_EQU RET +bcid 894 21 WIDTH,6 CALL_ARG_VAL,2,0 OPT_CONST,8 WIDTH,1 M_EQU RET +bcid 895 22 WIDTH,6 CALL_ARG_VAL,2,0 OPT_CONST,9 WIDTH,1 M_EQU RET +bcid 896 23 WIDTH,6 CALL_ARG_VAL,2,0 OPT_CONST,10 WIDTH,1 M_EQU RET +bcid 897 24 WIDTH,6 CALL_ARG_VAL,2,0 OPT_CONST,11 WIDTH,1 M_EQU RET +bcid 898 25 WIDTH,6 CALL_ARG_VAL,2,0 OPT_CONST,12 WIDTH,1 M_EQU RET +bcid 899 26 WIDTH,6 CALL_ARG_VAL,2,0 OPT_CONST,13 WIDTH,1 M_EQU RET +bcid 900 27 WIDTH,6 CALL_ARG_VAL,2,0 OPT_CONST,14 WIDTH,1 M_EQU RET +bcid 901 28 WIDTH,6 CALL_ARG_VAL,2,0 OPT_CONST,15 WIDTH,1 M_EQU RET +bcid 902 29 WIDTH,6 CALL_ARG_VAL,2,0 OPT_CONST,16 WIDTH,1 M_EQU RET +bcid 903 30 WIDTH,6 CALL_ARG_VAL,2,0 OPT_CONST,17 WIDTH,1 M_EQU RET +bcid 904 31 WIDTH,6 CALL_ARG_VAL,2,0 OPT_CONST,18 WIDTH,1 M_EQU RET +bcid 905 32 WIDTH,6 CALL_ARG_VAL,2,0 OPT_CONST,19 WIDTH,1 M_EQU RET +bcid 906 33 WIDTH,6 CALL_ARG_VAL,2,0 OPT_CONST,20 WIDTH,1 M_EQU RET +bcid 907 34 WIDTH,26 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 WIDTH,25 MULTI_CONCATENATE,1,25 WIDTH,5 OPT_CONST,0 WIDTH,25 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,0 WIDTH,20 SLICE,1 WIDTH,25 CONCATENATE,2 AND RET +bcid 908 35 WIDTH,26 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 WIDTH,25 MULTI_CONCATENATE,1,25 WIDTH,5 OPT_CONST,0 WIDTH,25 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,0 WIDTH,20 SLICE,1 WIDTH,25 CONCATENATE,2 AND RET +bcid 909 36 WIDTH,26 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,2 WIDTH,1 SLICE,1 WIDTH,25 MULTI_CONCATENATE,1,25 WIDTH,5 OPT_CONST,0 WIDTH,25 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,0 WIDTH,20 SLICE,1 WIDTH,25 CONCATENATE,2 AND RET +bcid 910 37 WIDTH,26 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,3 WIDTH,1 SLICE,1 WIDTH,25 MULTI_CONCATENATE,1,25 WIDTH,5 OPT_CONST,0 WIDTH,25 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,0 WIDTH,20 SLICE,1 WIDTH,25 CONCATENATE,2 AND RET +bcid 911 38 WIDTH,26 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,4 WIDTH,1 SLICE,1 WIDTH,25 MULTI_CONCATENATE,1,25 WIDTH,5 OPT_CONST,0 WIDTH,25 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,0 WIDTH,20 SLICE,1 WIDTH,25 CONCATENATE,2 AND RET +bcid 912 39 WIDTH,26 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,5 WIDTH,1 SLICE,1 WIDTH,25 MULTI_CONCATENATE,1,25 WIDTH,5 OPT_CONST,0 WIDTH,25 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,0 WIDTH,20 SLICE,1 WIDTH,25 CONCATENATE,2 AND RET +bcid 913 40 WIDTH,26 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,6 WIDTH,1 SLICE,1 WIDTH,25 MULTI_CONCATENATE,1,25 WIDTH,5 OPT_CONST,0 WIDTH,25 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,0 WIDTH,20 SLICE,1 WIDTH,25 CONCATENATE,2 AND RET +bcid 914 41 WIDTH,26 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,7 WIDTH,1 SLICE,1 WIDTH,25 MULTI_CONCATENATE,1,25 WIDTH,5 OPT_CONST,0 WIDTH,25 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,0 WIDTH,20 SLICE,1 WIDTH,25 CONCATENATE,2 AND RET +bcid 915 42 WIDTH,26 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,8 WIDTH,1 SLICE,1 WIDTH,25 MULTI_CONCATENATE,1,25 WIDTH,5 OPT_CONST,0 WIDTH,25 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,0 WIDTH,20 SLICE,1 WIDTH,25 CONCATENATE,2 AND RET +bcid 916 43 WIDTH,26 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,9 WIDTH,1 SLICE,1 WIDTH,25 MULTI_CONCATENATE,1,25 WIDTH,5 OPT_CONST,0 WIDTH,25 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,0 WIDTH,20 SLICE,1 WIDTH,25 CONCATENATE,2 AND RET +bcid 917 44 WIDTH,26 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,10 WIDTH,1 SLICE,1 WIDTH,25 MULTI_CONCATENATE,1,25 WIDTH,5 OPT_CONST,0 WIDTH,25 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,0 WIDTH,20 SLICE,1 WIDTH,25 CONCATENATE,2 AND RET +bcid 918 45 WIDTH,26 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,11 WIDTH,1 SLICE,1 WIDTH,25 MULTI_CONCATENATE,1,25 WIDTH,5 OPT_CONST,0 WIDTH,25 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,0 WIDTH,20 SLICE,1 WIDTH,25 CONCATENATE,2 AND RET +bcid 919 46 WIDTH,26 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,12 WIDTH,1 SLICE,1 WIDTH,25 MULTI_CONCATENATE,1,25 WIDTH,5 OPT_CONST,0 WIDTH,25 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,0 WIDTH,20 SLICE,1 WIDTH,25 CONCATENATE,2 AND RET +bcid 920 47 WIDTH,26 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,13 WIDTH,1 SLICE,1 WIDTH,25 MULTI_CONCATENATE,1,25 WIDTH,5 OPT_CONST,0 WIDTH,25 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,0 WIDTH,20 SLICE,1 WIDTH,25 CONCATENATE,2 AND RET +bcid 921 48 WIDTH,26 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,14 WIDTH,1 SLICE,1 WIDTH,25 MULTI_CONCATENATE,1,25 WIDTH,5 OPT_CONST,0 WIDTH,25 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,0 WIDTH,20 SLICE,1 WIDTH,25 CONCATENATE,2 AND RET +bcid 922 49 WIDTH,26 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,15 WIDTH,1 SLICE,1 WIDTH,25 MULTI_CONCATENATE,1,25 WIDTH,5 OPT_CONST,0 WIDTH,25 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,0 WIDTH,20 SLICE,1 WIDTH,25 CONCATENATE,2 AND RET +bcid 923 50 WIDTH,26 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,16 WIDTH,1 SLICE,1 WIDTH,25 MULTI_CONCATENATE,1,25 WIDTH,5 OPT_CONST,0 WIDTH,25 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,0 WIDTH,20 SLICE,1 WIDTH,25 CONCATENATE,2 AND RET +bcid 924 51 WIDTH,26 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,17 WIDTH,1 SLICE,1 WIDTH,25 MULTI_CONCATENATE,1,25 WIDTH,5 OPT_CONST,0 WIDTH,25 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,0 WIDTH,20 SLICE,1 WIDTH,25 CONCATENATE,2 AND RET +bcid 925 52 WIDTH,26 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,18 WIDTH,1 SLICE,1 WIDTH,25 MULTI_CONCATENATE,1,25 WIDTH,5 OPT_CONST,0 WIDTH,25 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,0 WIDTH,20 SLICE,1 WIDTH,25 CONCATENATE,2 AND RET +bcid 926 53 WIDTH,26 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,19 WIDTH,1 SLICE,1 WIDTH,25 MULTI_CONCATENATE,1,25 WIDTH,5 OPT_CONST,0 WIDTH,25 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,0 WIDTH,20 SLICE,1 WIDTH,25 CONCATENATE,2 AND RET +bcid 927 54 WIDTH,26 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,20 WIDTH,1 SLICE,1 WIDTH,25 MULTI_CONCATENATE,1,25 WIDTH,5 OPT_CONST,0 WIDTH,25 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,0 WIDTH,20 SLICE,1 WIDTH,25 CONCATENATE,2 AND RET +bcid 928 55 WIDTH,26 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,21 WIDTH,1 SLICE,1 WIDTH,25 MULTI_CONCATENATE,1,25 WIDTH,5 OPT_CONST,0 WIDTH,25 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,0 WIDTH,20 SLICE,1 WIDTH,25 CONCATENATE,2 AND RET +bcid 929 56 WIDTH,26 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,22 WIDTH,1 SLICE,1 WIDTH,25 MULTI_CONCATENATE,1,25 WIDTH,5 OPT_CONST,0 WIDTH,25 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,0 WIDTH,20 SLICE,1 WIDTH,25 CONCATENATE,2 AND RET +bcid 930 57 WIDTH,26 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,23 WIDTH,1 SLICE,1 WIDTH,25 MULTI_CONCATENATE,1,25 WIDTH,5 OPT_CONST,0 WIDTH,25 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,0 WIDTH,20 SLICE,1 WIDTH,25 CONCATENATE,2 AND RET +bcid 931 58 WIDTH,26 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,24 WIDTH,1 SLICE,1 WIDTH,25 MULTI_CONCATENATE,1,25 WIDTH,5 OPT_CONST,0 WIDTH,25 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,0 WIDTH,20 SLICE,1 WIDTH,25 CONCATENATE,2 AND RET +bcid 932 59 WIDTH,26 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,25 WIDTH,1 SLICE,1 WIDTH,25 MULTI_CONCATENATE,1,25 WIDTH,5 OPT_CONST,0 WIDTH,25 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,0 WIDTH,20 SLICE,1 WIDTH,25 CONCATENATE,2 AND RET +bcid 933 60 WIDTH,26 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,0 WIDTH,1 SLICE,1 WIDTH,32 MULTI_CONCATENATE,1,32 CALL_ARG_VAL,3,0 AND RET +bcid 934 61 WIDTH,26 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,1 WIDTH,1 SLICE,1 WIDTH,32 MULTI_CONCATENATE,1,32 CALL_ARG_VAL,3,0 AND RET +bcid 935 62 WIDTH,26 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,2 WIDTH,1 SLICE,1 WIDTH,32 MULTI_CONCATENATE,1,32 CALL_ARG_VAL,3,0 AND RET +bcid 936 63 WIDTH,26 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,3 WIDTH,1 SLICE,1 WIDTH,32 MULTI_CONCATENATE,1,32 CALL_ARG_VAL,3,0 AND RET +bcid 937 64 WIDTH,26 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,4 WIDTH,1 SLICE,1 WIDTH,32 MULTI_CONCATENATE,1,32 CALL_ARG_VAL,3,0 AND RET +bcid 938 65 WIDTH,26 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,5 WIDTH,1 SLICE,1 WIDTH,32 MULTI_CONCATENATE,1,32 CALL_ARG_VAL,3,0 AND RET +bcid 939 66 WIDTH,26 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,6 WIDTH,1 SLICE,1 WIDTH,32 MULTI_CONCATENATE,1,32 CALL_ARG_VAL,3,0 AND RET +bcid 940 67 WIDTH,26 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,7 WIDTH,1 SLICE,1 WIDTH,32 MULTI_CONCATENATE,1,32 CALL_ARG_VAL,3,0 AND RET +bcid 941 68 WIDTH,26 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,8 WIDTH,1 SLICE,1 WIDTH,32 MULTI_CONCATENATE,1,32 CALL_ARG_VAL,3,0 AND RET +bcid 942 69 WIDTH,26 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,9 WIDTH,1 SLICE,1 WIDTH,32 MULTI_CONCATENATE,1,32 CALL_ARG_VAL,3,0 AND RET +bcid 943 70 WIDTH,26 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,10 WIDTH,1 SLICE,1 WIDTH,32 MULTI_CONCATENATE,1,32 CALL_ARG_VAL,3,0 AND RET +bcid 944 71 WIDTH,26 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,11 WIDTH,1 SLICE,1 WIDTH,32 MULTI_CONCATENATE,1,32 CALL_ARG_VAL,3,0 AND RET +bcid 945 72 WIDTH,26 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,12 WIDTH,1 SLICE,1 WIDTH,32 MULTI_CONCATENATE,1,32 CALL_ARG_VAL,3,0 AND RET +bcid 946 73 WIDTH,26 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,13 WIDTH,1 SLICE,1 WIDTH,32 MULTI_CONCATENATE,1,32 CALL_ARG_VAL,3,0 AND RET +bcid 947 74 WIDTH,26 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,14 WIDTH,1 SLICE,1 WIDTH,32 MULTI_CONCATENATE,1,32 CALL_ARG_VAL,3,0 AND RET +bcid 948 75 WIDTH,26 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,15 WIDTH,1 SLICE,1 WIDTH,32 MULTI_CONCATENATE,1,32 CALL_ARG_VAL,3,0 AND RET +bcid 949 76 WIDTH,26 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,16 WIDTH,1 SLICE,1 WIDTH,32 MULTI_CONCATENATE,1,32 CALL_ARG_VAL,3,0 AND RET +bcid 950 77 WIDTH,26 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,17 WIDTH,1 SLICE,1 WIDTH,32 MULTI_CONCATENATE,1,32 CALL_ARG_VAL,3,0 AND RET +bcid 951 78 WIDTH,26 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,18 WIDTH,1 SLICE,1 WIDTH,32 MULTI_CONCATENATE,1,32 CALL_ARG_VAL,3,0 AND RET +bcid 952 79 WIDTH,26 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,19 WIDTH,1 SLICE,1 WIDTH,32 MULTI_CONCATENATE,1,32 CALL_ARG_VAL,3,0 AND RET +bcid 953 80 WIDTH,26 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,20 WIDTH,1 SLICE,1 WIDTH,32 MULTI_CONCATENATE,1,32 CALL_ARG_VAL,3,0 AND RET +bcid 954 81 WIDTH,26 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,21 WIDTH,1 SLICE,1 WIDTH,32 MULTI_CONCATENATE,1,32 CALL_ARG_VAL,3,0 AND RET +bcid 955 82 WIDTH,26 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,22 WIDTH,1 SLICE,1 WIDTH,32 MULTI_CONCATENATE,1,32 CALL_ARG_VAL,3,0 AND RET +bcid 956 83 WIDTH,26 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,23 WIDTH,1 SLICE,1 WIDTH,32 MULTI_CONCATENATE,1,32 CALL_ARG_VAL,3,0 AND RET +bcid 957 84 WIDTH,26 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,24 WIDTH,1 SLICE,1 WIDTH,32 MULTI_CONCATENATE,1,32 CALL_ARG_VAL,3,0 AND RET +bcid 958 85 WIDTH,26 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,25 WIDTH,1 SLICE,1 WIDTH,32 MULTI_CONCATENATE,1,32 CALL_ARG_VAL,3,0 AND RET +bcid 959 86 WIDTH,26 CALL_ARG_VAL,2,0 WIDTH,1 CALL_ARG_VAL,3,0 WIDTH,26 MULTI_CONCATENATE,1,26 AND RET +sid TB +bcid 960 0 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,0 WIDTH,1 CALL_ARG_VAL,3,0 WIDTH,32 CALL_ARG_VAL,4,0 OPT_CONST,1 ADD CALL_ARG_VAL,4,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET +bcid 961 1 WIDTH,4 CALL_ARG_VAL,2,0 OPT_CONST,8 WIDTH,1 M_EQU RET +sid DW01_addsub +bcid 962 0 WIDTH,4 CALL_ARG_VAL,2,0 CALL_ARG_VAL,2,0 XOR WIDTH,1 XOR_REDUCE OPT_CONST,0 NEQU WIDTH,4 CALL_ARG_VAL,3,0 CALL_ARG_VAL,3,0 XOR WIDTH,1 XOR_REDUCE OPT_CONST,0 NEQU CALL_ARG_VAL,4,0 CALL_ARG_VAL,4,0 XOR XOR_REDUCE OPT_CONST,0 NEQU OR OR WIDTH,5 OPT_CONST_4ST,31,31 WIDTH,1 CALL_ARG_VAL,4,0 WIDTH,4 CALL_ARG_VAL,2,0 WIDTH,5 PAD WIDTH,4 CALL_ARG_VAL,3,0 WIDTH,5 PAD SUBTRACT WIDTH,1 CALL_ARG_VAL,5,0 WIDTH,5 PAD SUBTRACT WIDTH,4 CALL_ARG_VAL,2,0 WIDTH,5 PAD WIDTH,4 CALL_ARG_VAL,3,0 WIDTH,5 PAD WIDTH,1 CALL_ARG_VAL,5,0 WIDTH,5 PAD ADD ADD MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET diff --git a/tb/digital_top/simv.daidir/cc/cc_dummy_file b/tb/digital_top/simv.daidir/cc/cc_dummy_file new file mode 100644 index 0000000..9ec9235 --- /dev/null +++ b/tb/digital_top/simv.daidir/cc/cc_dummy_file @@ -0,0 +1,2 @@ +Dummy_file +Missing line/file info diff --git a/tb/digital_top/simv.daidir/cgname.json b/tb/digital_top/simv.daidir/cgname.json new file mode 100644 index 0000000..e23f031 --- /dev/null +++ b/tb/digital_top/simv.daidir/cgname.json @@ -0,0 +1,278 @@ +{ + "dac_regfile": [ + "dac_regfile", + "LR0zI", + "module", + 11 + ], + "modout_mux": [ + "modout_mux", + "jEu9i", + "module", + 15 + ], + "tsdn28hpcpuhdb128x128m4mw_170a_Int_Array": [ + "tsdn28hpcpuhdb128x128m4mw_170a_Int_Array", + "eFLuy", + "module", + 9 + ], + "_vcs_unit__504089786": [ + "_vcs_unit__504089786", + "D1hM1", + "module", + 2 + ], + "std": [ + "std", + "reYIK", + "module", + 3 + ], + "tsdn28hpcpuhdb4096x32m4mw_170a": [ + "tsdn28hpcpuhdb4096x32m4mw_170a", + "d6TPd", + "module", + 13 + ], + "debug_top": [ + "debug_top", + "gNaPt", + "module", + 12 + ], + "sram_if": [ + "sram_if", + "NABmh", + "module", + 4 + ], + "spi_if": [ + "spi_if", + "IHYdB", + "module", + 44 + ], + "sram_if_0000": [ + "sram_if_0000", + "nJgqZ", + "module", + 5 + ], + "rst_gen_unit": [ + "rst_gen_unit", + "anuMN", + "module", + 24 + ], + "xy_dsp": [ + "xy_dsp", + "U33JQ", + "module", + 16 + ], + "ctrl_regfile": [ + "ctrl_regfile", + "mLA3J", + "module", + 6 + ], + "PH2AMP": [ + "PH2AMP", + "iYIEc", + "module", + 18 + ], + "DUC_HB3": [ + "DUC_HB3", + "Rdd8k", + "module", + 31 + ], + "param_lut_0002": [ + "param_lut_0002", + "nJN5E", + "module", + 7 + ], + "mcu_regfile": [ + "mcu_regfile", + "HWLgR", + "module", + 19 + ], + "sirv_gnrl_dffl": [ + "sirv_gnrl_dffl", + "BM4bj", + "module", + 8 + ], + "DW_mult_pipe_0000_0000": [ + "DW_mult_pipe_0000_0000", + "HNRiG", + "module", + 37 + ], + "sirv_gnrl_ltch": [ + "sirv_gnrl_ltch", + "UTi0b", + "module", + 10 + ], + "digital_top": [ + "digital_top", + "rTmJG", + "module", + 46 + ], + "tsdn28hpcpuhdb128x128m4mw_170a": [ + "tsdn28hpcpuhdb128x128m4mw_170a", + "rShyv", + "module", + 43 + ], + "DW02_mult_0005": [ + "DW02_mult_0005", + "UIt6b", + "module", + 42 + ], + "tsdn28hpcpuhdb4096x32m4mw_170a_Int_Array": [ + "tsdn28hpcpuhdb4096x32m4mw_170a_Int_Array", + "ay4xz", + "module", + 14 + ], + "qbmcu": [ + "qbmcu", + "xnbfb", + "module", + 20 + ], + "TSDN28HPCPUHDB4096X32M4MWR_Int_Array": [ + "TSDN28HPCPUHDB4096X32M4MWR_Int_Array", + "e36VC", + "module", + 29 + ], + "TSDN28HPCPUHDB4096X32M4MWR": [ + "TSDN28HPCPUHDB4096X32M4MWR", + "Sg3ri", + "module", + 36 + ], + "tsdn28hpcpuhdb64x32m4mw_170a_Int_Array": [ + "tsdn28hpcpuhdb64x32m4mw_170a_Int_Array", + "JweIx", + "module", + 17 + ], + "qbmcu_busdecoder": [ + "qbmcu_busdecoder", + "jAiwN", + "module", + 21 + ], + "qbmcu_datalatch": [ + "qbmcu_datalatch", + "MsCBG", + "module", + 22 + ], + "qbmcu_regfile_0000": [ + "qbmcu_regfile_0000", + "Hit7c", + "module", + 23 + ], + "dacif": [ + "dacif", + "SMgga", + "module", + 28 + ], + "...MASTER...": [ + "SIM", + "amcQw", + "module", + 45 + ], + "DUC4": [ + "DUC4", + "cwtAY", + "module", + 33 + ], + "spi_slave": [ + "spi_slave", + "eAsJz", + "module", + 25 + ], + "system_regfile": [ + "system_regfile", + "W3x1b", + "module", + 26 + ], + "channel_top": [ + "channel_top", + "xFWdC", + "module", + 27 + ], + "DUC_HB2": [ + "DUC_HB2", + "ksFw4", + "module", + 30 + ], + "DUC_HB4": [ + "DUC_HB4", + "zwWSN", + "module", + 32 + ], + "IIR_Filter": [ + "IIR_Filter", + "rLaFI", + "module", + 34 + ], + "z_dsp": [ + "z_dsp", + "zpIk1", + "module", + 35 + ], + "TB": [ + "TB", + "sH4Fc", + "module", + 47 + ], + "DW_mult_pipe_0000_0002": [ + "DW_mult_pipe_0000_0002", + "SiiVi", + "module", + 38 + ], + "DW_mult_pipe_0000_0003": [ + "DW_mult_pipe_0000_0003", + "ZpmS6", + "module", + 39 + ], + "DW01_addsub": [ + "DW01_addsub", + "KysYq", + "module", + 40 + ], + "DW02_mult_0004": [ + "DW02_mult_0004", + "hwIug", + "module", + 41 + ] +} \ No newline at end of file diff --git a/tb/digital_top/simv.daidir/covg_defs b/tb/digital_top/simv.daidir/covg_defs new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/simv.daidir/debug_dump/.version b/tb/digital_top/simv.daidir/debug_dump/.version new file mode 100644 index 0000000..f69ff87 --- /dev/null +++ b/tb/digital_top/simv.daidir/debug_dump/.version @@ -0,0 +1,4 @@ +O-2018.09-SP2_Full64 +Build Date = Feb 28 2019 22:34:30 +RedHat +Compile Location: /home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/digital_top diff --git a/tb/digital_top/simv.daidir/debug_dump/AllModulesSkeletons.sdb b/tb/digital_top/simv.daidir/debug_dump/AllModulesSkeletons.sdb new file mode 100644 index 0000000..a46ba94 Binary files /dev/null and b/tb/digital_top/simv.daidir/debug_dump/AllModulesSkeletons.sdb differ diff --git a/tb/digital_top/simv.daidir/debug_dump/HsimSigOptDb.sdb b/tb/digital_top/simv.daidir/debug_dump/HsimSigOptDb.sdb new file mode 100644 index 0000000..328a2ac Binary files /dev/null and b/tb/digital_top/simv.daidir/debug_dump/HsimSigOptDb.sdb differ diff --git a/tb/digital_top/simv.daidir/debug_dump/dumpcheck.db b/tb/digital_top/simv.daidir/debug_dump/dumpcheck.db new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/simv.daidir/debug_dump/dve_debug.db.gz b/tb/digital_top/simv.daidir/debug_dump/dve_debug.db.gz new file mode 100644 index 0000000..7bc27eb Binary files /dev/null and b/tb/digital_top/simv.daidir/debug_dump/dve_debug.db.gz differ diff --git a/tb/digital_top/simv.daidir/debug_dump/fsearch/.create_fsearch_db b/tb/digital_top/simv.daidir/debug_dump/fsearch/.create_fsearch_db new file mode 100644 index 0000000..fcf3dcb --- /dev/null +++ b/tb/digital_top/simv.daidir/debug_dump/fsearch/.create_fsearch_db @@ -0,0 +1,9 @@ +#!/bin/sh -h +PYTHONHOME=/home/synopsys/vcs/O-2018.09-SP2/etc/search/pyh +export PYTHONHOME +PYTHONPATH=/home/synopsys/vcs/O-2018.09-SP2/linux64/lib/pylib27 +export PYTHONPATH +LD_LIBRARY_PATH=/home/synopsys/vcs/O-2018.09-SP2/linux64/lib:/home/synopsys/vcs/O-2018.09-SP2/linux64/lib/pylib27 +export LD_LIBRARY_PATH +/home/synopsys/vcs/O-2018.09-SP2/linux64/bin/vcsfind_create_index.exe -z "/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/digital_top/simv.daidir/debug_dump/fsearch/./idents_uXI5BR.xml.gz" "/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/digital_top/simv.daidir/debug_dump/fsearch/./idents_tapi.xml.gz" -o "/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/digital_top/simv.daidir/debug_dump/fsearch/fsearch.db_tmp" +\mv "/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/digital_top/simv.daidir/debug_dump/fsearch/fsearch.db_tmp" "/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/digital_top/simv.daidir/debug_dump/fsearch/fsearch.db" diff --git a/tb/digital_top/simv.daidir/debug_dump/fsearch/check_fsearch_db b/tb/digital_top/simv.daidir/debug_dump/fsearch/check_fsearch_db new file mode 100644 index 0000000..b032e43 --- /dev/null +++ b/tb/digital_top/simv.daidir/debug_dump/fsearch/check_fsearch_db @@ -0,0 +1,57 @@ +#!/bin/sh -h + +FILE_PATH="/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/digital_top/simv.daidir/debug_dump/fsearch" +lockfile="${FILE_PATH}"/lock + +FSearch_lock_release() { + echo "" > /dev/null +} +create_fsearch_db_ctrl() { + if [ -s "${FILE_PATH}"/fsearch.stat ]; then + if [ -s "${FILE_PATH}"/fsearch.log ]; then + echo "ERROR building identifier database failed. Check ${FILE_PATH}/fsearch.log" + else + cat "${FILE_PATH}"/fsearch.stat + fi + return + fi + nohup "$1" > "${FILE_PATH}"/fsearch.log 2>&1 193>/dev/null & + MY_PID=`echo $!` + BUILDER="pid ${MY_PID} ${USER}@${hostname}" + echo "INFO Started building database for Identifiers, please wait ($BUILDER). Use VCS elab option '-debug_access+idents_db' to build the database earlier." + echo "INFO Still building database for Identifiers, please wait ($BUILDER). Use VCS elab option '-debug_access+idents_db' to build the database earlier." > "${FILE_PATH}"/fsearch.stat + return +} + +dir_name=`/bin/dirname "$0"` +if [ "${dir_name}" = "." ]; then + cd $dir_name + dir_name=`/bin/pwd` +fi +if [ -d "$dir_name"/../../../../../../../../../.. ]; then + cd "$dir_name"/../../../../../../../../../.. +fi + +if [ -f "/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/digital_top/simv.daidir/debug_dump/fsearch/.create_fsearch_db" ]; then + if [ ! -f "/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/digital_top/simv.daidir/debug_dump/fsearch/fsearch.db" ]; then + if [ "$#" -eq 1 ] && [ "x$1" == "x-background" ]; then + trap FSearch_lock_release EXIT + ( + flock 193 + create_fsearch_db_ctrl "/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/digital_top/simv.daidir/debug_dump/fsearch/.create_fsearch_db" + exit 193 + ) 193> "$lockfile" + rstat=$? + if [ "${rstat}"x != "193x" ]; then + exit $rstat + fi + else + "/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/digital_top/simv.daidir/debug_dump/fsearch/.create_fsearch_db" + if [ -f "/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/digital_top/simv.daidir/debug_dump/fsearch/fsearch.stat" ]; then + rm -f "/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/digital_top/simv.daidir/debug_dump/fsearch/fsearch.stat" + fi + fi + elif [ -f "/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/digital_top/simv.daidir/debug_dump/fsearch/fsearch.stat" ]; then + rm -f "/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/digital_top/simv.daidir/debug_dump/fsearch/fsearch.stat" + fi +fi diff --git a/tb/digital_top/simv.daidir/debug_dump/fsearch/fsearch.stat b/tb/digital_top/simv.daidir/debug_dump/fsearch/fsearch.stat new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/simv.daidir/debug_dump/fsearch/idents_tapi.xml.gz b/tb/digital_top/simv.daidir/debug_dump/fsearch/idents_tapi.xml.gz new file mode 100644 index 0000000..48d0145 Binary files /dev/null and b/tb/digital_top/simv.daidir/debug_dump/fsearch/idents_tapi.xml.gz differ diff --git a/tb/digital_top/simv.daidir/debug_dump/fsearch/idents_uXI5BR.xml.gz b/tb/digital_top/simv.daidir/debug_dump/fsearch/idents_uXI5BR.xml.gz new file mode 100644 index 0000000..3072986 Binary files /dev/null and b/tb/digital_top/simv.daidir/debug_dump/fsearch/idents_uXI5BR.xml.gz differ diff --git a/tb/digital_top/simv.daidir/debug_dump/src_files_verilog b/tb/digital_top/simv.daidir/debug_dump/src_files_verilog new file mode 100644 index 0000000..545a842 --- /dev/null +++ b/tb/digital_top/simv.daidir/debug_dump/src_files_verilog @@ -0,0 +1,99 @@ +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/awg/awg_ctrl.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/awg/awg_top.sv +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/awg/codeword_decode.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/awg/ctrl_regfile.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/awg/modout_mux.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/awg/param_lut.sv +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/clk/intpll_regfile.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/comm/sirv_gnrl_dffs.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/comm/sirv_gnrl_xchecker.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/dac_regfile/dac_regfile.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/debug/debug_sample.sv +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/debug/debug_top.sv +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/define/chip_define.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/define/chip_undefine.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/memory/dpram.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/memory/dpram_model.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/memory/sram_dmux.sv +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/memory/sram_if.sv +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/memory/tsdn28hpcpuhdb128x128m4mw_170a_ffg0p99v0c.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/memory/tsdn28hpcpuhdb4096x32m4mw_170a_ffg0p99v0c.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/memory/tsdn28hpcpuhdb4096x32m4mwr_170a_ffg0p99v0c.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/memory/tsdn28hpcpuhdb64x32m4mw_170a_ffg0p99v0c.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/memory/tsmc_dpram.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/modem/ampmod.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/modem/baisset.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/modem/freqmod.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/nco/coef_c.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/nco/coef_s.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/nco/cos_op.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/nco/nco.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/nco/nco_ch1.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/nco/p_nco.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/nco/p_nco_ch1.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/nco/ph2amp.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/nco/pipe_acc_48bit.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/nco/pipe_add_48bit.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/nco/sin_op.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/perips/DW03_updn_ctr.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/perips/mcu_regfile.sv +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/perips/qbmcu_busdecoder.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/qubitmcu/qbmcu.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/qubitmcu/qbmcu_datalock.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/qubitmcu/qbmcu_decode.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/qubitmcu/qbmcu_defines.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/qubitmcu/qbmcu_exu.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/qubitmcu/qbmcu_exu_alu.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/qubitmcu/qbmcu_exu_bjp.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/qubitmcu/qbmcu_exu_dpath.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/qubitmcu/qbmcu_exu_ext.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/qubitmcu/qbmcu_exu_lsuagu.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/qubitmcu/qbmcu_fsm.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/qubitmcu/qbmcu_ifu.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/qubitmcu/qbmcu_regfile.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/qubitmcu/qbmcu_undefines.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/qubitmcu/qbmcu_wbck.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/rstgen/rst_gen_unit.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/rstgen/rst_sync.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/spi/spi_bus_decoder.sv +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/spi/spi_pll.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/spi/spi_slave.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/spi/spi_sys.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/sync/sync_buf.sv +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/system_regfile/system_regfile.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/top/channel_top.sv +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/top/digital_top.sv +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/xy_dsp/dacif/dacif.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/xy_dsp/dsp_top/xy_dsp.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/xy_dsp/duc/duc4.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/xy_dsp/duc/duc_hb1_pipe_shift.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/xy_dsp/duc/duc_hb1_top.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/xy_dsp/duc/duc_hb2_pipe_shift.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/xy_dsp/duc/duc_hb2_top_s.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/xy_dsp/duc/duc_hb3_pipe_shift.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/xy_dsp/duc/duc_hb3_top_s2.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/xy_dsp/duc/duc_hb4_pipe_shift.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/xy_dsp/duc/duc_hb4_top_s3.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/xy_dsp/qam/qam_top.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/xy_dsp/qam/ssb.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/z_dsp/IIR_Filter.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/z_dsp/MeanIntp.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/z_dsp/MeanIntp2.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/z_dsp/MeanIntp4_top.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/z_dsp/MeanIntp_s1.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/z_dsp/TailCorr_top.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/z_dsp/diff.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/z_dsp/lsdacif.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/z_dsp/mult_C.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/z_dsp/z_data_mux.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/z_dsp/z_dsp.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/digital_top/DW01_addsub.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/digital_top/DW02_mult.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/digital_top/DW_mult_pipe.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/digital_top/TB.sv +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/digital_top/chip_define.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/digital_top/chip_undefine.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/digital_top/clk_gen.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/digital_top/qbmcu_defines.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/digital_top/qbmcu_undefines.v +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/digital_top/spi_if.sv diff --git a/tb/digital_top/simv.daidir/debug_dump/topmodules b/tb/digital_top/simv.daidir/debug_dump/topmodules new file mode 100644 index 0000000..e7d567c --- /dev/null +++ b/tb/digital_top/simv.daidir/debug_dump/topmodules @@ -0,0 +1 @@ +˜›%³fœZ©x±C \ No newline at end of file diff --git a/tb/digital_top/simv.daidir/debug_dump/vir.sdb b/tb/digital_top/simv.daidir/debug_dump/vir.sdb new file mode 100644 index 0000000..a8453e4 Binary files /dev/null and b/tb/digital_top/simv.daidir/debug_dump/vir.sdb differ diff --git a/tb/digital_top/simv.daidir/eblklvl.db b/tb/digital_top/simv.daidir/eblklvl.db new file mode 100644 index 0000000..8181d9c Binary files /dev/null and b/tb/digital_top/simv.daidir/eblklvl.db differ diff --git a/tb/digital_top/simv.daidir/elabmoddb.sdb b/tb/digital_top/simv.daidir/elabmoddb.sdb new file mode 100644 index 0000000..3ec42ed Binary files /dev/null and b/tb/digital_top/simv.daidir/elabmoddb.sdb differ diff --git a/tb/digital_top/simv.daidir/external_functions b/tb/digital_top/simv.daidir/external_functions new file mode 100644 index 0000000..9dbd31f --- /dev/null +++ b/tb/digital_top/simv.daidir/external_functions @@ -0,0 +1,129 @@ +pli $fsdbDumpvars novas_call_fsdbDumpvars - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbDumpvarsES novas_call_fsdbDumpvarsES - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbDumpMDA novas_call_fsdbDumpMDA - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbDumpSVA novas_call_fsdbDumpSVA - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbDumpvarsByFile novas_call_fsdbDumpvarsByFile - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbSuppress novas_call_fsdbSuppress - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbDumpon novas_call_fsdbDumpon - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbDumpoff novas_call_fsdbDumpoff - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbSwitchDumpfile novas_call_fsdbSwitchDumpfile - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbDumpfile novas_call_fsdbDumpfile - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbAutoSwitchDumpfile novas_call_fsdbAutoSwitchDumpfile - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbDumpFinish novas_call_fsdbDumpFinish - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbDumpflush novas_call_fsdbDumpflush - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbLog novas_call_fsdbLog - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbAddRuntimeSignal novas_call_fsdbAddRuntimeSignal - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbDumpSC novas_call_fsdbDumpSC - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbDumpvarsToFile novas_call_fsdbDumpvarsToFile - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $sps_create_transaction_stream novas_call_sps_create_transaction_stream - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $sps_begin_transaction novas_call_sps_begin_transaction - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $sps_end_transaction novas_call_sps_end_transaction - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $sps_free_transaction novas_call_sps_free_transaction - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $sps_add_attribute novas_call_sps_add_attribute - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $sps_update_label novas_call_sps_update_label - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $sps_add_relation novas_call_sps_add_relation - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbWhatif novas_call_fsdbWhatif - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $paa_init novas_call_paa_init - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $paa_sync novas_call_paa_sync - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbDumpClassMethod novas_call_fsdbDumpClassMethod - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbSuppressClassMethod novas_call_fsdbSuppressClassMethod - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbSuppressClassProp novas_call_fsdbSuppressClassProp - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbDumpMDAByFile novas_call_fsdbDumpMDAByFile - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbTrans_create_stream_begin novas_call_fsdbEvent_create_stream_begin - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbTrans_define_attribute novas_call_fsdbEvent_add_stream_attribute - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbTrans_create_stream_end novas_call_fsdbEvent_create_stream_end - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbTrans_begin novas_call_fsdbEvent_begin - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbTrans_set_label novas_call_fsdbEvent_set_label - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbTrans_add_attribute novas_call_fsdbEvent_add_attribute - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbTrans_add_tag novas_call_fsdbEvent_add_tag - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbTrans_end novas_call_fsdbEvent_end - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbTrans_add_relation novas_call_fsdbEvent_add_relation - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbTrans_get_error_code novas_call_fsdbEvent_get_error_code - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbTrans_add_stream_attribute novas_call_fsdbTrans_add_stream_attribute - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbTrans_add_scope_attribute novas_call_fsdbTrans_add_scope_attribute - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $sps_interactive novas_call_sps_interactive - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $sps_test novas_call_sps_test - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbDumpClassObject novas_call_fsdbDumpClassObject - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbDumpClassObjectByFile novas_call_fsdbDumpClassObjectByFile - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $ridbDump novas_call_ridbDump - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $sps_flush_file novas_call_sps_flush_file - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbDumpPSL novas_call_fsdbDumpPSL - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbDumplimit novas_call_fsdbDumplimit - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab +pli $fsdbDumpvars novas_call_fsdbDumpvars - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpvarsES novas_call_fsdbDumpvarsES - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpMDA novas_call_fsdbDumpMDA - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpSVA novas_call_fsdbDumpSVA - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpvarsByFile novas_call_fsdbDumpvarsByFile - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbSuppress novas_call_fsdbSuppress - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpon novas_call_fsdbDumpon - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpoff novas_call_fsdbDumpoff - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbSwitchDumpfile novas_call_fsdbSwitchDumpfile - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpfile novas_call_fsdbDumpfile - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbAutoSwitchDumpfile novas_call_fsdbAutoSwitchDumpfile - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpFinish novas_call_fsdbDumpFinish - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpflush novas_call_fsdbDumpflush - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbLog novas_call_fsdbLog - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbAddRuntimeSignal novas_call_fsdbAddRuntimeSignal - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpSC novas_call_fsdbDumpSC - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpvarsToFile novas_call_fsdbDumpvarsToFile - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $sps_create_transaction_stream novas_call_sps_create_transaction_stream - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $sps_begin_transaction novas_call_sps_begin_transaction - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $sps_end_transaction novas_call_sps_end_transaction - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $sps_free_transaction novas_call_sps_free_transaction - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $sps_add_attribute novas_call_sps_add_attribute - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $sps_update_label novas_call_sps_update_label - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $sps_add_relation novas_call_sps_add_relation - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbWhatif novas_call_fsdbWhatif - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $paa_init novas_call_paa_init - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $paa_sync novas_call_paa_sync - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpClassMethod novas_call_fsdbDumpClassMethod - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbSuppressClassMethod novas_call_fsdbSuppressClassMethod - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbSuppressClassProp novas_call_fsdbSuppressClassProp - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpMDAByFile novas_call_fsdbDumpMDAByFile - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbTrans_create_stream_begin novas_call_fsdbEvent_create_stream_begin - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbTrans_define_attribute novas_call_fsdbEvent_add_stream_attribute - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbTrans_create_stream_end novas_call_fsdbEvent_create_stream_end - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbTrans_begin novas_call_fsdbEvent_begin - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbTrans_set_label novas_call_fsdbEvent_set_label - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbTrans_add_attribute novas_call_fsdbEvent_add_attribute - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbTrans_add_tag novas_call_fsdbEvent_add_tag - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbTrans_end novas_call_fsdbEvent_end - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbTrans_add_relation novas_call_fsdbEvent_add_relation - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbTrans_get_error_code novas_call_fsdbEvent_get_error_code - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbTrans_add_stream_attribute novas_call_fsdbTrans_add_stream_attribute - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbTrans_add_scope_attribute novas_call_fsdbTrans_add_scope_attribute - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $sps_interactive novas_call_sps_interactive - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $sps_test novas_call_sps_test - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpClassObject novas_call_fsdbDumpClassObject - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpClassObjectByFile novas_call_fsdbDumpClassObjectByFile - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $ridbDump novas_call_ridbDump - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $sps_flush_file novas_call_sps_flush_file - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpPSL novas_call_fsdbDumpPSL - novas_misc /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDisplay novas_call_fsdbDisplay - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumplimit novas_call_fsdbDumplimit - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpMem novas_call_fsdbDumpMem - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpMemNow novas_call_fsdbDumpMemNow - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpMemInScope novas_call_fsdbDumpMemInScope - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpMDANow novas_call_fsdbDumpMDANow - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpMDAOnChange novas_call_fsdbDumpMDAOnChange - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpMDAInScope novas_call_fsdbDumpMDAInScope - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpMemInFile novas_call_fsdbDumpMemInFile - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpPSLon novas_call_fsdbDumpPSLon - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpPSLoff novas_call_fsdbDumpPSLoff - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpSVAon novas_call_fsdbDumpSVAon - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpSVAoff novas_call_fsdbDumpSVAoff - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpStrength novas_call_fsdbDumpStrength - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpSingle novas_call_fsdbDumpSingle - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpIO novas_call_fsdbDumpIO - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbDumpPattern novas_call_fsdbDumpPattern - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $fsdbSubstituteHier novas_call_fsdbSubstituteHier - - /home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/verdi.tab +pli $dumpports DumpPortsIeeeCALL - DumpPortsMISC +pli $lsi_dumpports DumpPortsLsiCALL - DumpPortsMISC +pli $dumpportson DumpPortsOnCALL - DumpPortsMISC +pli $dumpportsoff DumpPortsOffCALL - DumpPortsMISC +pli $dumpportsflush DumpPortsFlushCALL - DumpPortsMISC +pli $simlearn simLearnCall simLearnCheck simLearnMisc +pli $dumpportsall DumpPortsAllCALL - DumpPortsMISC +pli $dumpportslimit DumpPortsLimitCALL - DumpPortsMISC +pli $countdrivers CountDriversCALL - - +pli $vcsmemprof DMMemProfCALL DMMemProfCheck DMMemProfMISC diff --git a/tb/digital_top/simv.daidir/hslevel_callgraph.sdb b/tb/digital_top/simv.daidir/hslevel_callgraph.sdb new file mode 100644 index 0000000..88fd465 Binary files /dev/null and b/tb/digital_top/simv.daidir/hslevel_callgraph.sdb differ diff --git a/tb/digital_top/simv.daidir/hslevel_level.sdb b/tb/digital_top/simv.daidir/hslevel_level.sdb new file mode 100644 index 0000000..a3def2e Binary files /dev/null and b/tb/digital_top/simv.daidir/hslevel_level.sdb differ diff --git a/tb/digital_top/simv.daidir/hslevel_rtime_level.sdb b/tb/digital_top/simv.daidir/hslevel_rtime_level.sdb new file mode 100644 index 0000000..e5675ae Binary files /dev/null and b/tb/digital_top/simv.daidir/hslevel_rtime_level.sdb differ diff --git a/tb/digital_top/simv.daidir/hsscan_cfg.dat b/tb/digital_top/simv.daidir/hsscan_cfg.dat new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/simv.daidir/nsparam.dat b/tb/digital_top/simv.daidir/nsparam.dat new file mode 100644 index 0000000..8d40f34 Binary files /dev/null and b/tb/digital_top/simv.daidir/nsparam.dat differ diff --git a/tb/digital_top/simv.daidir/pcc.sdb b/tb/digital_top/simv.daidir/pcc.sdb new file mode 100644 index 0000000..9b8325a Binary files /dev/null and b/tb/digital_top/simv.daidir/pcc.sdb differ diff --git a/tb/digital_top/simv.daidir/pcxpxmr.dat b/tb/digital_top/simv.daidir/pcxpxmr.dat new file mode 100644 index 0000000..51a6230 Binary files /dev/null and b/tb/digital_top/simv.daidir/pcxpxmr.dat differ diff --git a/tb/digital_top/simv.daidir/prof.sdb b/tb/digital_top/simv.daidir/prof.sdb new file mode 100644 index 0000000..14dd04e Binary files /dev/null and b/tb/digital_top/simv.daidir/prof.sdb differ diff --git a/tb/digital_top/simv.daidir/rmapats.dat b/tb/digital_top/simv.daidir/rmapats.dat new file mode 100644 index 0000000..6930bb1 Binary files /dev/null and b/tb/digital_top/simv.daidir/rmapats.dat differ diff --git a/tb/digital_top/simv.daidir/rmapats.so b/tb/digital_top/simv.daidir/rmapats.so new file mode 100644 index 0000000..3e14ee7 Binary files /dev/null and b/tb/digital_top/simv.daidir/rmapats.so differ diff --git a/tb/digital_top/simv.daidir/saifNetInfo.db b/tb/digital_top/simv.daidir/saifNetInfo.db new file mode 100644 index 0000000..f0d367b --- /dev/null +++ b/tb/digital_top/simv.daidir/saifNetInfo.db @@ -0,0 +1,43 @@ +14 +tsmc_dpram +dpram_32X4096_generation®BWEBA +All +tsmc_dpram +dpram_32X4096_generation®BWEBB +All +tsmc_dpram +dpram_32X4096_generation®U0_CEBA +Scal +tsmc_dpram +dpram_32X4096_generation®U0_CEBB +Scal +tsmc_dpram +dpram_32X4096_generation®U0_QA +All +tsmc_dpram +dpram_32X4096_generation®U0_QB +All +tsmc_dpram +dpram_32X4096_generation®U1_CEBA +Scal +tsmc_dpram +dpram_32X4096_generation®U1_CEBB +Scal +tsmc_dpram +dpram_32X4096_generation®U1_QA +All +tsmc_dpram +dpram_32X4096_generation®U1_QB +All +tsmc_dpram +spram_32X64_generation®BWEBA +All +tsmc_dpram +spram_32X64_generation®BWEBB +All +tsmc_dpram +spram_512X128_generation®BWEBA +All +tsmc_dpram +spram_512X128_generation®BWEBB +All diff --git a/tb/digital_top/simv.daidir/simv.kdb b/tb/digital_top/simv.daidir/simv.kdb new file mode 100644 index 0000000..caf06be --- /dev/null +++ b/tb/digital_top/simv.daidir/simv.kdb @@ -0,0 +1,16 @@ +rc file Version 1.0 + +[Design] +COMPILE_PATH=/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/digital_top +SystemC=FALSE +UUM=FALSE +KDB=FALSE +USE_NOVAS_HOME=FALSE +COSIM=FALSE +TOP=sirv_gnrl_dffl sirv_gnrl_ltch tsdn28hpcpuhdb4096x32m4mw_170a TB DW01_addsub +OPTION=-ssv -ssy +ELAB_OPTION=-ssv -ssy + +[Value] +WREALX=ffff534e50535f58 +WREALZ=ffff534e50535f5a diff --git a/tb/digital_top/simv.daidir/stitch_nsparam.dat b/tb/digital_top/simv.daidir/stitch_nsparam.dat new file mode 100644 index 0000000..0357d47 Binary files /dev/null and b/tb/digital_top/simv.daidir/stitch_nsparam.dat differ diff --git a/tb/digital_top/simv.daidir/tt.sdb b/tb/digital_top/simv.daidir/tt.sdb new file mode 100644 index 0000000..5a759ca Binary files /dev/null and b/tb/digital_top/simv.daidir/tt.sdb differ diff --git a/tb/digital_top/simv.daidir/vcs_rebuild b/tb/digital_top/simv.daidir/vcs_rebuild new file mode 100644 index 0000000..68cf71e --- /dev/null +++ b/tb/digital_top/simv.daidir/vcs_rebuild @@ -0,0 +1,4 @@ +#!/bin/sh -e +# This file is automatically generated by VCS. Any changes you make +# to it will be overwritten the next time VCS is run. +vcs '-full64' '-sverilog' '+lint=TFIPC-L' '+v2k' '-debug_access+all' '+define+DUMP_FSDB' '-lca' '-q' '-timescale=1ns/1ps' '+nospecify' '-P' '/home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/novas_new_dumper.tab' '/home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/linux64/pli.a' '-l' 'compile.log' '-f' 'files.f' 2>&1 diff --git a/tb/digital_top/simv.daidir/vcselab_master_hsim_elabout.db b/tb/digital_top/simv.daidir/vcselab_master_hsim_elabout.db new file mode 100644 index 0000000..b59ee40 --- /dev/null +++ b/tb/digital_top/simv.daidir/vcselab_master_hsim_elabout.db @@ -0,0 +1,691 @@ +hsDirType 1 +fHsimDesignHasDebugNodes 63 +fNSParam 1024 +fLargeSizeSdfTest 0 +fHsimDelayGateMbme 0 +fNoMergeDelays 0 +fHsimAllMtmPat 0 +fHsimCertRaptMode 0 +fSharedMasterElab 0 +hsimLevelizeDone 1 +fHsimCompressDiag 1 +fHsimPowerOpt 0 +fLoopReportElab 0 +fHsimRtl 0 +fHsimCbkOptVec 1 +fHsimDynamicCcnHeur 1 +fHsimPvcs 0 +fHsimPvcsCcn 0 +fHsimOldLdr 0 +fHsimSingleDB 1 +uVfsGcLimit 50 +fHsimCompatSched 0 +fHsimCompatOrder 0 +fHsimTransUsingdoMpd32 0 +fHsimDynamicElabForGates 1 +fHsimDynamicElabForVectors 0 +fHsimDynamicElabForVectorsAlways 0 +fHsimDynamicElabForVectorsMinputs 0 +fHsimDeferForceSelTillReElab 0 +fHsimModByModElab 1 +fSvNettRealResType 0 +fHsimExprID 1 +fHsimSequdpon 0 +fHsimDatapinOpt 0 +fHsimExprPrune 0 +fHsimMimoGate 0 +fHsimNewChangeCheckFrankch 1 +fHsimNoSched0Front 0 +fHsimNoSched0FrontForMd 1 +fHsimScalReg 0 +fHsimNtbVl 0 +fHsimICTimeStamp 0 +fHsimICDiag 0 +fHsimNewCSDF 1 +vcselabIncrMode 2 +fHsimMPPackDelay 0 +fHsimMultDriver 0 +fHsimPart 0 +fHsimPrlComp 0 +fHsimPartTest 0 +fHsimTestChangeCheck 0 +fHsimTestFlatNodeOrder 0 +fHsimTestNState 0 +fHsimPartDebug 0 +fHsimPartFlags 0 +fHsimOdeSched0 0 +fHsimNewRootSig 1 +fHsimDisableRootSigModeOpt 0 +fHsimTestRootSigModeOpt 0 +fHsimIncrWriteOnce 0 +fHsimUnifInterfaceFlow 1 +fHsimUnifInterfaceFlowDiag 0 +fHsimUnifInterfaceFlowXmrDiag 0 +fHsimUnifInterfaceMultiDrvChk 1 +fHsimXVirForGenerateScope 0 +fHsimCongruencyIntTestI 0 +fHsimCongruencySVA 0 +fHsimCongruencySVADbg 0 +fHsimCongruencyLatchEdgeFix 0 +fHsimCongruencyFlopEdgeFix 0 +fHsimCongruencyXprop 0 +fHsimCongruencyXpropFix 0 +fHsimCongruencyXpropDbsEdge 0 +fHsimCongruencyResetRecoveryDbs 0 +fHsimCongruencyClockControlDiag 0 +fHsimCongruencySampleUpdate 0 +fHsimCongruencyFFDbsFix 0 +fHsimCongruency 0 +fHsimCongruencySlave 0 +fHsimCongruencyCombinedLoads 0 +fHsimCongruencyFGP 0 +fHsimDeraceClockDataUdp 0 +fHsimDeraceClockDataLERUpdate 0 +fHsimCongruencyPC 0 +fHsimCongruencyPCInl 0 +fHsimCongruencyPCDbg 0 +fHsimCongruencyPCNoReuse 0 +fHsimCongruencyDumpHier 0 +fHsimCongruencyResolution 0 +fHsimCongruencyEveBus 0 +fHsimHcExpr 0 +fHsCgOptModOpt 0 +fHsCgOptSlowProp 0 +fHsimCcnOpt 1 +fHsimCcnOpt2 1 +fHsimCcnOpt3 0 +fHsimSmdMap 0 +fHsimSmdDiag 0 +fHsimSmdSimProf 0 +fHsimSgdDiag 0 +fHsimRtDiagLite 0 +fHsimRtDiagLiteCevent 100 +fHsimRtDiag 0 +fHsimSkRtDiag 0 +fHsimDDBSRtdiag 0 +fHsimDbg 0 +fHsimCompWithGates 0 +fHsimMdbDebugOpt 0 +fHsimMdbDebugOptP1 0 +fHsimMdbDebugOptP2 0 +fHsimMdbPruneOpt 1 +fHsimMdbMemOpt 0 +hsimRandValue 0 +fHsimSimMemProfile 0 +fHsimSimTimeProfile 0 +fHsimElabMemProfile 0 +fHsimElabTimeProfile 0 +fHsimElabMemNodesProfile 0 +fHsimElabMemAllNodesProfile 0 +fHsimDisableVpdGatesProfile 0 +fHsimFileProfile 0 +fHsimCountProfile 0 +fHsimXmrDefault 1 +fHsimFuseWireAndReg 0 +fHsimFuseSelfDrvLogic 0 +fHsimFuseProcess 0 +fHsimNoStitchDump 0 +fHsimAllExtXmrs 0 +fHsimAllXmrs 1 +fHsimMvsimDb 0 +fHsimTaskFuncXmrs 0 +fHsimTaskFuncXmrsDbg 0 +fHsimAllTaskFuncXmrs 0 +fHsimPageArray 16383 +fHsimPageControls 16383 +hsDfsNodePageElems 0 +hsNodePageElems 0 +hsFlatNodePageElems 0 +hsGateMapPageElems 0 +hsGateOffsetPageElems 0 +hsGateInputOffsetPageElems 0 +hsDbsOffsetPageElems 0 +hsMinPulseWidthPageElems 0 +hsNodeUpPatternPageElems 0 +hsNodeDownPatternPageElems 0 +hsNodeUpOffsetPageElems 0 +hsNodeEblkOffsetPageElems 0 +hsNodeDownOffsetPageElems 0 +hsNodeUpdateOffsetPageElems 0 +hsSdfOffsetPageElems 0 +fHsimPageAllLevelData 0 +fHsimAggrCg 0 +fHsimViWire 1 +fHsimPcCbOpt 1 +fHsimAmsTunneling 0 +fHsimAmsTunnelingDiag 0 +fHsimScUpwardXmrNoSplit 1 +fHsimOrigNdbViewOnly 0 +fHsimVcsInterface 1 +fHsimVcsInterfaceAlias 1 +fHsimSVTypesIntf 1 +fUnifiedAssertCtrlDiag 0 +fHsimEnable2StateScal 0 +fHsimDisable2StateScalIbn 0 +fHsimVcsInterfaceAliasDbg 0 +fHsimVcsInterfaceDbg 0 +fHsimVcsVirtIntfDbg 0 +fHsimVcsAllIntfVarMem 0 +fHsimCheckVIDynLoadOffsets 0 +fHsimModInline 1 +fHsimModInlineDbg 0 +fHsimPCDrvLoadDbg 0 +fHsimDrvChk 1 +fHsimRtlProcessingNeeded 0 +fHsimGrpByGrpElab 0 +fHsimGrpByGrpElabMaster 0 +fHsimNoParentSplitPC 0 +fHsimNusymMode 0 +fHsimOneIntfPart 0 +fHsimCompressInSingleDb 2 +fHsimCompressFlatDb 0 +fHsimNoTime0Sched 1 +fHsimMdbVectorizeInstances 0 +fHsimMdbSplitGates 0 +fHsimDeleteInstances 0 +fHsimUserDeleteInstances 0 +fHsimDeleteGdb 0 +fHsimDeleteInstancesMdb 0 +fHsimShortInstMap 0 +fHsimMdbVectorizationDump 0 +fHsimScanVectorize 0 +fHsimParallelScanVectorize 0 +noInstsInVectorization 0 +cHsimNonReplicatedInstances 0 +fHsimScanRaptor 0 +fHsimConfigFileCount 0 +fHsimVectorConstProp 0 +fHsimPromoteParam 0 +fHsimNoVecInRaptor 0 +fRaptorDumpVal 0 +fRaptorVecNodes 0 +fRaptorVecNodes2 0 +fRaptorNonVecNodes 0 +fRaptorBdrNodes 0 +fRaptorVecGates 0 +fRaptorNonVecGates 0 +fRaptorTotalNodesBeforeVect 0 +fRaptorTotalGatesBeforeVect 0 +fHsimCountRaptorBits 0 +fHsimNewEvcd 1 +fHsimNewEvcdMX 0 +fHsimNewEvcdVecRoot 1 +fHsimNewEvcdForce 1 +fHsimNewEvcdTest 0 +fHsimNewEvcdObnDrv 1 +fHsimNewEvcdW 1 +fHsimNewEvcdWTest 0 +fHsimEvcdDbgFlags 0 +fHsimNewEvcdMultiDrvFmt 1 +fHsimDumpOffsetData 1 +fFlopGlitchDetect 0 +fHsimClkGlitch 0 +fHsimGlitchDumpOnce 0 +fHsimDynamicElab 1 +fHsimCgVectors2Debug 0 +fHsimOdeDynElab 0 +fHsimOdeDynElabDiag 0 +fHsimOdeSeqUdp 0 +fHsimOdeSeqUdpXEdge 0 +fHsimOdeSeqUdpDbg 0 +fHsimOdeRmvSched0 0 +fHsimAllLevelSame 0 +fHsimRtlDbsList 0 +fHsimPePort 0 +fHsimPeXmr 0 +fHsimPePortDiag 0 +fHsimUdpDbs 0 +fHsimRemoveDbgCaps 0 +fFsdbGateOnepassTraverse 0 +fHsimAllowVecGateInVpd 1 +fHsimAllowAllVecGateInVpd 0 +fHsimAllowUdpInVpd 1 +fHsimAllowAlwaysCombInVpd 1 +fHsimAllowAlwaysCombCmpDvcSimv 0 +fHsimAllowAlwaysCombDbg 0 +fHsimMakeAllP2SPrimary 0 +fHsimMakeAllSeqPrimary 0 +fHsimNoCcnDump 0 +fHsimFsdbProfDiag 0 +fVpdSeqGate 0 +fVpdUseMaxBCode 0 +fVpdHsIntVecGate 0 +fVpdHsCmplxVecGate 0 +fVpdHsVecGateDiags 0 +fSeqGateCodePatch 0 +fVpdLongFaninOpt 0 +fVpdSeqLongFaninOpt 0 +fVpdNoLoopDetect 0 +fVpdNoSeqLoopDetect 0 +fVpdOptAllowConstDriver 0 +fVpdAllowCellReconstruction 0 +fVpdRtlForSharedLib 0 +fHsimVpdOptGate 1 +fHsimVpdOptDelay 0 +fHsimVpdOptMPDelay 0 +fHsimCbkOptDiag 0 +fHsimSK 0 +fHsimSharedKernel 1 +fHsimOnepass 0 +fHsimStitchNew 0 +fHsimParallelLevelize 0 +fHsimParallelLevelizeDbg 0 +fHsimSeqUdpDbsByteArray 0 +fHsimCoLocate 0 +fHsimSeqUdpEblkOpt 0 +fHsimSeqUdpEblkOptDiag 0 +fHsimGateInputAndDbsOffsetsOpt 1 +fHsimUdpDynElab 0 +fHsimCompressData 4 +fHsimIgnoreZForDfuse 1 +fHsimIgnoreDifferentCaps 0 +fHandleGlitchQC 1 +fGlitchDetectForAllRtlLoads 0 +fHsimFuseConstDriversOpt 1 +fHsimMdSchedTr 0 +fHsimIgnoreReElab 0 +fHsimFuseMultiDrivers 0 +fHsimNoSched0Reg 0 +fHsimAmsFusionEnabled 0 +fHsimRtlDbs 0 +fHsimWakeupId 0 +fHsimPassiveIbn 0 +fHsimBcOpt 1 +fHsimCertitude 0 +fHsimCertRapAutoTest 0 +fHsimRaceDetect 0 +fCheckTcCond 0 +fHsimScanOptRelaxDbg 0 +fHsimScanOptRelaxDbgDynamic 0 +fHsimScanOptRelaxDbgDynamicPli 0 +fHsimScanOptRelaxDbgDiag 0 +fHsimScanOptRelaxDbgDiagHi 0 +fHsimScanOptNoErrorOnPliAccess 0 +fHsimScanOptTiming 0 +fRelaxIbnSchedCheck 0 +fHsimScanOptNoDumpCombo 0 +fHsimScanOptPrintSwitchState 0 +fHsimScanOptSelectiveSwitchOn 0 +fHsimScanOptSingleSEPliOpt 1 +fHsimScanOptDesignHasDebugAccessOnly 0 +fHsimScanOptPrintPcode 0 +fHsimScanDbgPerf 0 +fHsimNoStitchMap 0 +fHsimUnifiedModName 0 +fHsimCbkMemOptDebug 0 +fHsimMasterModuleOnly 0 +fHsimMdbOptimizeSelects 0 +fHsimMdbScalarizePorts 0 +fHsimMdbOptimizeSelectsHeuristic 1 +fHsimMdb1006Partition 0 +fHsimVectorPgate 0 +fHsimNoHs 0 +fHsimXmrPartition 0 +fHsimNewPartition 0 +fHsimElabPart 0 +fHsimElabPartThreshHoldDesign 1 +fHsimPMdb 0 +fHsimParitionCellInstNum 1000 +fHsimParitionCellNodeNum 1000 +fHsimParitionCellXMRNum 1000 +fHsimNewPartCutSingleInstLimit 268435455 +fHsimElabModDistNum 0 +fHsimElabPartThreshHoldModule 3000000 +fHsimPCPortPartition 0 +fHsimPortPartition 0 +fHsimDumpMdb 0 +fHsimElabDiag 0 +fHsimSimpCollect 0 +fHsimPcodeDiag 0 +fHsimFastelab 0 +fHsimMacroOpt 0 +fHsimSkipOpt 0 +fHsimSkipOptFanoutlimit 0 +fHsimSkipOptRootlimit 0 +fHsimFuseDelayChains 0 +fFusempchainsFanoutlimit 0 +fFusempchainsDiagCount 0 +fHsimCgVectorGates 0 +fHsimCgVectorGates1 0 +fHsimCgVectorGates2 0 +fHsimCgVectorGatesNoReElab 0 +fHsimCgScalarGates 0 +fHsimCgScalarGatesExpr 0 +fHsimCgScalarGatesLut 0 +fHsimCgRtl 1 +fHsimCgRtlFilter 0 +fHsimCgRtlDebug 0 +fHsimCgRtlSize 15 +fHsimNewCgRt 0 +fHsimNewCgMPRt 0 +fHsimNewCgMPRetain 0 +fHsimCgRtlInfra 1 +fHsimGlueOpt 0 +fHsimPGatePatchOpt 0 +fHsimCgNoPic 0 +fHsimElabModCg 0 +fPossibleNullChecks 0 +fHsimProcessNoSplit 1 +fHsimMdbOptInSchedDelta 0 +fScaleTimeValue 0 +fDebugTimeScale 0 +fPartCompSDF 0 +fHsimNbaGate 1 +fDumpDtviInfoInSC 0 +fDumpSDFBasedMod 1 +fHsimSdfIC 0 +fOptimisticNtcSolver 0 +fHsimAllMtm 0 +fHsimAllMtmPat 0 +fHsimSdgOptEnable 0 +fHsimSVTypesRefPorts 0 +fHsimGrpByGrpElabIncr 0 +fHsimMarkRefereeInVcsElab 0 +fHsimStreamOpFix 1 +fHsimInterface 0 +fHsimMxWrapOpt 0 +fHsimMxTopBdryOpt 0 +fHsimClasses 0 +fHsimAggressiveDce 0 +fHsimDceDebug 1 +fHsimDceDebugUseHeuristics 1 +fHsimMdbNewDebugOpt 0 +fHsimMdbNewDebugOptExitOnError 1 +fHsimNewDebugOptMemDiag 0 +hsGlobalVerboseLevel 0 +fHsimMdbVectorConstProp 1 +fHsimEnableSeqUdpWrite 1 +fHsimDumpMDBOnlyForSeqUdp 0 +fHsimInitRegRandom 0 +fHsimInitRegRandomVcs 1 +fEnableNewFinalStrHash 0 +fEnableNewAssert 1 +fRunDbgDmma 0 +fAssrtCtrlSigChk 1 +fCheckSigValidity 0 +fUniqPriToAstRewrite 0 +fUniqPriToAstCtrl 0 +fAssertcontrolUniqPriNewImpl 0 +fRTLoopDectEna 0 +fCmplLoopDectEna 0 +fHsimMopFlow 1 +fUCaseLabelCtrl 0 +fUniSolRtSvaEna 1 +fUniSolSvaEna 1 +fXpropRtCtrlCallerOnly 0 +fHsimRaptorPart 0 +fHsimEnableDbsMemOpt 1 +fHsimDebugDbsMemOpt 0 +fHsimRenPart 0 +fHsimShortElabInsts 0 +fHsimXmrAllWires 0 +fHsimXmrDiag 0 +fHsimXmrPort 0 +fHsimFalcon 1 +fHsimGenForProfile 0 +fCompressSDF 0 +fDlpSvtbExclElab 0 +fHsimGates1209 0 +fHsimCgRtlNoShareSmd 0 +fHsimGenForErSum 0 +fVpdOpt 1 +fHsimMdbCell 0 +fHsimCellDebug 0 +fHsimNoPeekInMdbCell 0 +igetOpcodeSmdPtrLayoutId -1 +igetFieldSmdPtr -1 +fDebugDump 1 +fHsimOrigNodeNames 0 +fHsimCgVectors2VOnly 0 +fHsimMdbDeltaGate 0 +fHsimMdbDeltaGateAggr 0 +fHsimMdbVecDeltaGate 1 +fHsimVpdOptVfsDB 1 +fHsimMdbPruneVpdGates 1 +fHsimPcPe 0 +fHsimVpdGateOnlyFlag 1 +fHsimMxConnFrc 0 +fHsimNewForceCbkVec 0 +fHsimNewForceCbkVecDiag 0 +fHsimMdbReplaceVpdHighConn 1 +fHsimVpdOptSVTypes 1 +fHsHasPeUpXmr 0 +fHsimCompactVpdFn 1 +fHsimPIP 0 +fHsimRTLoopDectOrgName 0 +fHsimVpdOptPC 0 +fHsimFusePeXmrFo 0 +fHsimXmrSched 0 +fHsimNoMdg 0 +fHsimVectorGates 0 +fHsimRtlLite 0 +fHsimMdbcgLut 0 +fHsimMdbcgSelective 0 +fHsimVcselabGates 0 +fHsimMdbcgLevelize 0 +fHsimParGateEvalMode 0 +fHsimDFuseVectors 0 +fHsimDFuseZero 0 +fHsimDFuseOpt 1 +fHsimPruneOpt 0 +fHsimSeqUdpPruneWithConstInputs 0 +fHsimSafeDFuse 0 +fHsimVpdOptExpVec 0 +fHsimVpdOptSelGate 1 +fHsimVpdOptSkipFuncPorts 0 +fHsimVpdOptAlways 1 +fHsimVpdOptMdbCell 0 +fHsimVpdOptPartialMdb 1 +fHsimVpdOptPartitionGate 1 +fHsimVpdOptXmr 1 +fHsimVpdOptMoreLevels 1 +fHsimVpdHilRtl 0 +fHsimSWave 0 +fHsimNoSched0InCell 1 +fHsimPartialMdb 0 +hsimPdbLargeOffsetThreshold 1048576 +fHsimFlatCell 0 +fHsimFlatCellLimit 0 +fHsimRegBank 0 +fHsimHmetisMaxPartSize 0 +fHsimHmetisGateWt 0 +fHsimHmetisUbFactor 0 +fHsimHmetis 0 +fHsimHmetisDiag 0 +fHsimRenumGatesForMdbCell 0 +fHsimHmetisMinPart 0 +fHsim2stCell 0 +fHsim2stCellMinSize 0 +fHsimMdbcgDebug 0 +fHsimMdbcgDebugLite 0 +fHsimMdbcgDistrib 0 +fHsimMdbcgSepmem 1 +fHsimMdbcgObjDiag 0 +fHsimMdbcg2stDiag 0 +fHsimMdbcgRttrace 0 +fHsimMdbVectorGateGroup 1 +fHsimMdbProcDfuse 1 +fHsimMdbHilPrune 0 +fHsCgOpt 1 +fHsCgOptUdp 1 +fHsCgOptRtl 1 +fHsCgOptDiag 0 +fHsCgOptAggr 0 +fHsCgOptNoZCheck 0 +fHsCgOptEnableZSupport 0 +fHsCgOpt4StateInfra 0 +fHsCgOptDce 0 +fHsCgOptUdpChkDataForWakeup 1 +fHsCgOptXprop 0 +fHsimMdbcgDiag 0 +fHsCgMaxInputs 6 +fHsCgOptFwdPass 1 +fHsimHpnodes 0 +fLightDump 0 +fHDLCosim 0 +fHDLCosimDebug 0 +fHDLCosimTimeCoupled 0 +fHDLCosimTimeCoupledPorts 0 +HDLCosimMaxDataPerDpi 1 +HDLCosimMaxCallsPerDpi 2147483647 +fHDLCosimCompileDUT 0 +fHDLCosimCustomCompile 0 +fHDLCosimBoundaryAnalysis 0 +fVpdBeforeScan 1 +fHsCgOptMiSched0 0 +fgcAddSched0 0 +fParamClassOptRtDiag 0 +fHsRegress 0 +fHsBenchmark 0 +fHsimCgScalarVerilogForce 1 +fVcsElabToRoot 1 +fHilIbnObnCallByName 0 +fHsimMdbcgCellPartition 0 +fHsimCompressVpdSig 0 +fHsimLowPowerOpt 0 +fHsimUdpOpt 1 +fHsVecOneld 0 +fNativeVpdDebug 0 +fNewDtviFuse 0 +fHsimVcsGenTLS 1 +fAssertSuccDebugLevelDump 0 +fHsimMinputsChangeCheck 0 +fHsimClkLayout 0 +fHsimIslandLayout 0 +fHsimConfigSched0 0 +fHsimSelectFuseAfterDfuse 0 +fHsimFoldedCell 0 +fHsimSWaveEmul 0 +fHsimSWaveDumpMDB 0 +fHsimSWaveDumpFlatData 0 +fHsimRenumberAlias 0 +fHsimAliasRenumbered 0 +fHilCgMode 115 +fHsimUnionOpt 0 +fHsimFuseSGDBoundaryNodes 0 +fHsimRemoveCapsVec 0 +fHsimCertRaptScal 0 +fHsimCertRaptMdbClock 0 +fHsCgOptMux 0 +fHsCgOptFrc 0 +fHsCgOpt30 0 +fHsLpNoCapsOpt 0 +fHsCgOpt4State 1 +fSkipStrChangeOnDelay 1 +fHsimTcheckOpt 0 +fHsCgOptMuxMClk 0 +fHsCgOptMuxFrc 0 +fHsCgOptNoPcb 0 +fHsCgOptMin1 0 +fHsCgOptUdpChk 0 +fHsChkXForSlowSigProp 1 +fHsimVcsParallelDbg 0 +fHsimVcsParallelStrategy 0 +fHsimVcsParallelOpt 0 +fHsimVcsParallelSubLevel 4 +fHsimParallelEblk 0 +fHsimByteCodeParts 1 +fFgpNovlInComp 0 +fFutEventPRL 0 +fFgpNbaDelay 0 +fHsimDbsFlagsByteArray 0 +fHsimDbsFlagsByteArrayTC 0 +fHsimDbsFlagsThreadArray 0 +fHsimGateEdgeEventSched 0 +fHsimEgschedDynelab 0 +fHsimUdpClkDynelab 0 +fUdpLayoutOnClk 0 +fHsimDiagClk 1 +fDbsPreCheck 0 +fHsimSched0Analysis 0 +fHsimMultiDriverSched0 0 +fHsimLargeIbnSched 0 +fFgpHierarchical 0 +fFgpHierAllElabModAsRoot 0 +fFgpHierPCElabModAsRoot 0 +fFgpAdjustDataLevelOfLatch 1 +fHsimUdpXedgeEval 0 +fFgpRaceCheck 0 +fFgpUnifyClk 0 +fFgpSmallClkTree 0 +fFgpSmallRtlClkTree 4 +fFgpNoRtlUnlink 0 +fFgpNoRtlAuxLevel 0 +fFgpNumPartitions 8 +fFgpMultiSocketCompile 0 +fFgpDataDepOn 0 +fFgpDDIgnore 0 +fFgpTbCbOn 0 +fFgpTbEvOn 1 +fFgpTbNoVSA 0 +fFgpTbEvXmr 0 +fFgpTbEvCgCall 1 +fFgpDisabledLevel 512 +fFgpSched0User 0 +fFgpNoSdDelayedNbas 1 +fFgpTimingFlags 0 +fFgpSched0Level 0 +fHsimFgpMultiClock 0 +fFgpScanOptFix 0 +fFgpSched0UdpData 0 +fFgpLoadBalance0CompileTime 1 +fFgpDepositDiag 0 +fFgpEvtDiag.diagOn 0 +fFgpEvtDiag.printAllNodes 0 +fFgpMangleDiagLog 0 +fFgpMultiExclDiag 0 +fFgpSingleExclReason 0 +fHsDoFaninFanoutSanity 0 +fHsFgpNonDbsOva 1 +fFgpParallelTask 1 +fFgpIbnSched 0 +fFgpIbnSchedOpt 0 +fFgpIbnSchedThreshold 0 +fFgpIbnSchedDyn 0 +fFgpMpStateByte 0 +fFgpTcStateByte 0 +fHsimVirtIntfDynLoadSched 0 +fFgpNoRtimeFgp 0 +fHsFgpGlSched0 0 +fFgpExclReason 0 +fHsimIslandByIslandElab 0 +fHsimIslandByIslandFlat 151652416 +fHsimIslandByIslandFlat1 4 +fHsimVpdIBIF 0 +fHsimXmrIBIF 0 +fHsimReportTime 0 +fHsimElabJ 0 +hf_fHsimElabJ 0 +fHsimElabJOpt 0 +fHsimSchedMinput 0 +fHsimSchedSeqPrim 0 +fHsimSchedSelectFanout 0 +fHsimSchedSelectFanoutDebug 0 +fSpecifyInDesign 0 +fFgpDynamicReadOn 0 +fHsCgOptAllUc 0 +fHsimXmrRepl 0 +fZoix 0 +fHsimDfuseNewOpt 0 +fHsimBfuseNewOpt 0 +fFgpXmrSched 0 +fHsimClearClkCaps 0 +fHsimDiagClkConfig 0 +fHsimDiagClkConfigDebug 0 +fHsimDiagClkConfigDumpAll 0 +fHsDiagClkConfigPara 0 +fHsimDiagClkConfigAn 0 +fHsimCanDumpClkConfig 0 +fFgpInitRout 0 +fFgpIgnoreExclSD 0 +fHsCgOptNoClockFusing 0 +fHsClkWheelLimit 50000 +fHsimPCSharedLibSpecified 0 +fHsFgpSchedCgUcLoads 1 +fHsCgOptNewSelCheck 1 +fFgpReportUnsafeFuncs 0 +fHsCgOptUncPrlThreshold 4 +fHsSVNettypePerfOpt 0 +fHsimLowPowerRetAnalysisInChild 0 +fRetainWithDelayedSig 0 +fHsimChargeDecay 0 diff --git a/tb/digital_top/simv.daidir/vcselab_master_hsim_virtintf_info.dat b/tb/digital_top/simv.daidir/vcselab_master_hsim_virtintf_info.dat new file mode 100644 index 0000000..394d0dc Binary files /dev/null and b/tb/digital_top/simv.daidir/vcselab_master_hsim_virtintf_info.dat differ diff --git a/tb/digital_top/simv.daidir/vcselab_misc_hil_stmts.db b/tb/digital_top/simv.daidir/vcselab_misc_hil_stmts.db new file mode 100644 index 0000000..7aff9af Binary files /dev/null and b/tb/digital_top/simv.daidir/vcselab_misc_hil_stmts.db differ diff --git a/tb/digital_top/simv.daidir/vcselab_misc_hsdef.db b/tb/digital_top/simv.daidir/vcselab_misc_hsdef.db new file mode 100644 index 0000000..3eaf548 Binary files /dev/null and b/tb/digital_top/simv.daidir/vcselab_misc_hsdef.db differ diff --git a/tb/digital_top/simv.daidir/vcselab_misc_hsim_elab.db b/tb/digital_top/simv.daidir/vcselab_misc_hsim_elab.db new file mode 100644 index 0000000..ea71f44 --- /dev/null +++ b/tb/digital_top/simv.daidir/vcselab_misc_hsim_elab.db @@ -0,0 +1,1217 @@ +psSimBaseName simv +psLogFileName compile.log +pDaiDir /home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/digital_top/simv.daidir +destPath csrc/ +fSharedMaster 0 +fHsimPCSharedLibSpecified 0 +hsMainFileCount 0 +hsMainFileName dummy +hsAuxFileName dummy +hsimDlpPartitionFilename 0 +partitionName 6 MASTER +hsimInitRegValue 3 +fNSParam 1024 +hsim_noschedinl 0 +hsim_hdbs 4096 +eval_order_seq 0 +simorder_light 0 +partialelab 0 +hsim_csdf -2147483648 +fHsimRuntimeElabSdf 0 +fNtcNewSolver 0 +fHsimSdfFileOpt 0 +fHsimTransUsingdoMpd32 0 +hsDirType 1 +fHsimClasses 0 +fHsimPulseMPDelay 1 +fHsimMvsimDb 0 +fHsimMvsimDebug 0 +fHsimAllXmrs 1 +fHsimTaskFuncXmrs 0 +fHsimTaskFuncXmrsDbg 0 +fHsimAllTaskFuncXmrs 0 +fHsimDoXmrProcessing 1 +fNoMergeDelays 0 +uGlblTimeUnit 4 +fHsimAllMtm 0 +fSimprofileNew 0 +fHsimVhVlOpt 0 +fHsimMdbVhVlInputFuseOpt 0 +fHsimMdbVhVlInoutFuseOpt 0 +fHsimMdbVhVlCcnOpt 0 +fHsimVlVhOpt 0 +fHsimVlVhVlOpt 0 +fHsimVlVhBfuseOpt 0 +xpropMergeMode 0 +xpropUnifiedInferenceMode 0 +xpropOverride 0 +isXpropConfigEnabled 0 +fHsimVectorConst 0 +fHsimAllMtmPat 0 +fHsimCertRaptMode 0 +fNewCBSemantics 1 +fSchedAtEnd 0 +fSpecifyInDesign 0 +fHsimDumpFlatData 1 +fHsimCompressDiag 1 +fHsimPowerOpt 0 +fLoopReportElab 0 +fHsimRtl 0 +fHsimCbkOptVec 1 +fHsimDynamicCcnHeur 1 +fHsimPvcs 0 +fHsimPvcsCcn 0 +fHsimOldLdr 0 +fHsimSingleDB 1 +uVfsGcLimit 50 +fHsimCompatSched 0 +fHsimCompatOrder 0 +fHsimDynamicElabForGates 1 +fHsimDynamicElabForVectors 0 +fHsimDynamicElabForVectorsAlways 0 +fHsimDynamicElabForVectorsMinputs 0 +fHsimDeferForceSelTillReElab 0 +fHsimModByModElab 1 +fSvNettRealResType 0 +fHsimExprID 1 +fHsimSequdpon 0 +fHsimDatapinOpt 0 +fHsimExprPrune 0 +fHsimMimoGate 0 +fHsimNewChangeCheckFrankch 1 +fHsimNoSched0Front 0 +fHsimNoSched0FrontForMd 1 +fHsimScalReg 0 +fHsimNtbVl 0 +fHsimICTimeStamp 0 +fHsimICDiag 0 +fHsimNewCSDF 1 +vcselabIncrMode 2 +fHsimMPPackDelay 0 +fHsimMultDriver 0 +fHsimPart 0 +fHsimPrlComp 0 +fHsimPartTest 0 +fHsimTestChangeCheck 0 +fHsimTestFlatNodeOrder 0 +fHsimTestNState 0 +fHsimPartDebug 0 +fHsimPartFlags 0 +fHsimOdeSched0 0 +fHsimNewRootSig 1 +fHsimDisableRootSigModeOpt 0 +fHsimTestRootSigModeOpt 0 +fHsimIncrWriteOnce 0 +fHsimUnifInterfaceStrId 1 +fHsimUnifInterfaceFlow 1 +fHsimUnifInterfaceFlowDiag 0 +fHsimUnifInterfaceFlowXmrDiag 0 +fHsimUnifInterfaceMultiDrvChk 1 +fHsimXVirForGenerateScope 0 +fHsimCongruencyIntTestI 0 +fHsimCongruencySVA 0 +fHsimCongruencySVADbg 0 +fHsimCongruencyLatchEdgeFix 0 +fHsimCongruencyFlopEdgeFix 0 +fHsimCongruencyXprop 0 +fHsimCongruencyXpropFix 0 +fHsimCongruencyXpropDbsEdge 0 +fHsimCongruencyResetRecoveryDbs 0 +fHsimCongruencyClockControlDiag 0 +fHsimCongruencySampleUpdate 0 +fHsimCongruencyFFDbsFix 0 +fHsimCongruency 0 +fHsimCongruencySlave 0 +fHsimCongruencyCombinedLoads 0 +fHsimCongruencyFGP 0 +fHsimDeraceClockDataUdp 0 +fHsimDeraceClockDataLERUpdate 0 +fHsimCongruencyPC 0 +fHsimCongruencyPCInl 0 +fHsimCongruencyPCDbg 0 +fHsimCongruencyPCNoReuse 0 +fHsimCongruencyDumpHier 0 +fHsimCongruencyResolution 0 +fHsimCongruencyEveBus 0 +fHsimHcExpr 0 +fHsCgOptModOpt 0 +fHsCgOptSlowProp 0 +fHsimCcnOpt 1 +fHsimCcnOpt2 1 +fHsimCcnOpt3 0 +fHsimSmdMap 0 +fHsimSmdDiag 0 +fHsimSmdSimProf 0 +fHsimSgdDiag 0 +fHsimRtDiagLite 0 +fHsimRtDiagLiteCevent 100 +fHsimRtDiag 0 +fHsimSkRtDiag 0 +fHsimDDBSRtdiag 0 +fHsimDbg 0 +fHsimCompWithGates 0 +fHsimMdbDebugOpt 0 +fHsimMdbDebugOptP1 0 +fHsimMdbDebugOptP2 0 +fHsimMdbPruneOpt 1 +fHsimMdbMemOpt 0 +hsimRandValue 0 +fHsimSimMemProfile 0 +fHsimSimTimeProfile 0 +fHsimElabMemProfile 0 +fHsimElabTimeProfile 0 +fHsimElabMemNodesProfile 0 +fHsimElabMemAllNodesProfile 0 +fHsimDisableVpdGatesProfile 0 +fHsimFileProfile 0 +fHsimCountProfile 0 +fHsimXmrDefault 1 +fHsimFuseWireAndReg 0 +fHsimFuseSelfDrvLogic 0 +fHsimFuseProcess 0 +fHsimNoStitchDump 0 +fHsimAllExtXmrs 0 +fHsimAllExtXmrsDiag 0 +fHsimAllExtXmrsAllowClkFusing 0 +fHsimPageArray 16383 +fHsimPageControls 16383 +hsDfsNodePageElems 0 +hsNodePageElems 0 +hsFlatNodePageElems 0 +hsGateMapPageElems 0 +hsGateOffsetPageElems 0 +hsGateInputOffsetPageElems 0 +hsDbsOffsetPageElems 0 +hsMinPulseWidthPageElems 0 +hsNodeUpPatternPageElems 0 +hsNodeDownPatternPageElems 0 +hsNodeUpOffsetPageElems 0 +hsNodeEblkOffsetPageElems 0 +hsNodeDownOffsetPageElems 0 +hsNodeUpdateOffsetPageElems 0 +hsSdfOffsetPageElems 0 +fHsimPageAllLevelData 0 +fHsimAggrCg 0 +fHsimViWire 1 +fHsimPcCbOpt 1 +fHsimAmsTunneling 0 +fHsimAmsTunnelingDiag 0 +fHsimAmsNewDrs 0 +fHsimScUpwardXmrNoSplit 1 +fHsimOrigNdbViewOnly 0 +fHsimVcsInterface 1 +fHsimVcsInterfaceAlias 1 +fHsimSVTypesIntf 1 +fUnifiedAssertCtrlDiag 0 +fHsimEnable2StateScal 0 +fHsimDisable2StateScalIbn 0 +fHsimVcsInterfaceAliasDbg 0 +fHsimVcsInterfaceDbg 0 +fHsimVcsVirtIntfDbg 0 +fHsimVcsAllIntfVarMem 0 +fHsimCheckVIDynLoadOffsets 0 +fHsimModInline 1 +fHsimModInlineDbg 0 +fHsimPCDrvLoadDbg 0 +fHsimDrvChk 1 +fHsimRtlProcessingNeeded 0 +fHsimGrpByGrpElab 0 +fHsimGrpByGrpElabMaster 0 +fHsimNoParentSplitPC 0 +fHsimNusymMode 0 +fHsimOneIntfPart 0 +fHsimCompressInSingleDb 2 +fHsimCompressFlatDb 0 +fHsimNoTime0Sched 1 +fHsimMdbVectorizeInstances 0 +fHsimMdbSplitGates 0 +fHsimDeleteInstances 0 +fHsimUserDeleteInstances 0 +fHsimDeleteGdb 0 +fHsimDeleteInstancesMdb 0 +fHsimShortInstMap 0 +fHsimMdbVectorizationDump 0 +fHsimScanVectorize 0 +fHsimParallelScanVectorize 0 +noInstsInVectorization 0 +cHsimNonReplicatedInstances 0 +fHsimScanRaptor 0 +fHsimConfigFileCount 0 +fHsimVectorConstProp 0 +fHsimPromoteParam 0 +fHsimNoVecInRaptor 0 +fRaptorDumpVal 0 +fRaptorVecNodes 0 +fRaptorVecNodes2 0 +fRaptorNonVecNodes 0 +fRaptorBdrNodes 0 +fRaptorVecGates 0 +fRaptorNonVecGates 0 +fRaptorTotalNodesBeforeVect 0 +fRaptorTotalGatesBeforeVect 0 +fHsimCountRaptorBits 0 +fHsimNewEvcd 1 +fHsimNewEvcdMX 0 +fHsimNewEvcdVecRoot 1 +fHsimNewEvcdForce 1 +fHsimNewEvcdTest 0 +fHsimNewEvcdObnDrv 1 +fHsimNewEvcdW 1 +fHsimNewEvcdWTest 0 +fHsimEvcdDbgFlags 0 +fHsimNewEvcdMultiDrvFmt 1 +fHsimDumpElabData 1 +fHsimNoDeposit 0 +fHsimDumpOffsetData 1 +fNoOfsOpt 0 +fFlopGlitchDetect 0 +fHsimClkGlitch 0 +fHsimGlitchDumpOnce 0 +fHsimDynamicElab 1 +fHsimDynamicElabDiag 0 +fHsimPrintPats 1 +fHsimInterpreted 0 +fHsimAggressiveCodegenForDelays 1 +fHsimAggressiveCgNtcDelays 1 +fHsimCgDelaysDiag 0 +fHsimCodegenForVectors 1 +fHsimCgVectors2E 1 +fHsimCgVectors2W 1 +fHsimCgVectors2Cbk 1 +fHsimCgVectors2Force 0 +fHsimCgVectors2Debug 0 +fHsimCgVectors2Diag 0 +fHsimHdlForceInfoDiag 0 +fHsimHdlForceInfo 0 +fHsimCodegenForTcheck 1 +fHsimUdpsched 0 +fHsimUdpTetramax 0 +fHsimUdpDelta 0 +fHsimMasterNodesOpt 0 +fHsimTransOpt 1 +fHsimNoPortOBN 0 +fHsimGateGroup 0 +fHsimOldXmr 0 +fHsimConst 1 +fHsimOptimizeSeqUdp 1 +fHsimOptimizeNotifier 0 +fHsimPrintUdpTable 0 +fHsimConstDelay 0 +fHsimConstForce 0 +fHsimCcnOpt4 0 +fHsimCcnOptDiag 0 +fHsimCcn 1 +fHsimDynamicCcn 0 +fHsimTestBoundaryConditions1 0 +fHsimTestBoundaryConditions2 0 +fHsimTestBoundaryConditions3 0 +fHsimTestElabNodeLimit 0 +fHsimInsertSched0ForLhsSelects 1 +fHsimVectors 1 +fHsimOde 0 +fHsimOdeDynElab 0 +fHsimOdeDynElabDiag 0 +fHsimOdeUdp 0 +fHsimOdeSeqUdp 0 +fHsimOdeSeqUdpXEdge 0 +fHsimOdeSeqUdpDbg 0 +fHsimOdeRmvSched0 0 +fHsimOde4State 0 +fHsimOdeDiag 0 +fHsimOdeWithVecNew 0 +fHsimOdeAcceptDeadGates 0 +fHsimOdeAcceptValue4Loads 0 +fHsimOdeAmdSRLatch 0 +fHsimRmvSched0OnDataOfFlop 0 +fHsimRmvSched0OnMpd 0 +fHsimAllLevelSame 0 +fHsimDbsList 0 +fHsimRtlDbsList 0 +fHsimPePort 0 +fHsimPeXmr 0 +fHsimPePortDiag 0 +fHsimUdpDbs 0 +fHsimCodeShare 0 +fHsimRemoveDbgCaps 0 +fFsdbGateOnepassTraverse 0 +fHsimAllowVecGateInVpd 1 +fHsimAllowAllVecGateInVpd 0 +fHsimAllowUdpInVpd 1 +fHsimAllowAlwaysCombInVpd 1 +fHsimAllowAlwaysCombCmpDvcSimv 0 +fHsimAllowAlwaysCombDbg 0 +fHsimMakeAllP2SPrimary 0 +fHsimMakeAllSeqPrimary 0 +fHsimNoCcnDump 0 +fHsimFsdbProfDiag 0 +fVpdSeqGate 0 +fVpdUseMaxBCode 0 +fVpdHsIntVecGate 0 +fVpdHsCmplxVecGate 0 +fVpdHsVecGateDiags 0 +fSeqGateCodePatch 0 +fVpdLongFaninOpt 0 +fVpdSeqLongFaninOpt 0 +fVpdNoLoopDetect 0 +fVpdNoSeqLoopDetect 0 +fVpdOptAllowConstDriver 0 +fVpdAllowCellReconstruction 0 +fVpdRtlForSharedLib 0 +fRaptorProf 0 +fHsimVpdOptGateMustDisable 0 +fHsimVpdOptGate 1 +fHsimVpdOptDelay 0 +fHsimVpdOptMPDelay 0 +fHsimVpdOptDiag 0 +fHsimVpdOptRtlIncrFix 0 +fHsimVpdOptDiagV 0 +fHsimCbkOptVecWithVcsd 0 +fHsimCbkOptDiag 0 +fHsimByRefIBN 1 +fHsimWireMda 1 +fHsimUniqifyElabDiag 0 +fHsimForceCbkVec 1 +fHsimSplitForceCbkVec 1 +fHsimLowPower 0 +fHsimLowPowerDumpOnly 0 +fHsimLowPowerDiag 0 +fHsimXpropFix 1 +fHsimXpropConfigTrace 0 +fHsimNameBasedInterface 1 +fHsimVcsInterfaceHierDiag 0 +fHsimCbSchedFix 0 +fHsimIncrDebug 0 +fHsimSK 0 +fHsimSharedKernel 1 +fHsimSKIncr 0 +fElabModTimeProfCount 0 +fHsimChangeSharedLib 0 +fHsimNewIncr 1 +fHsimIncrSkip 0 +fHsimSecondCheckMdb 0 +fHsimIntraXmrNotMaster 0 +fHsimExtNodeDiag 0 +fHsimExtIntfXmrDebug 0 +fHsimExtXmrNodeDiag 0 +fPartTopElabModName 0 +fHsimPreResolveXmr 1 +fHsimNoIntfXmrNonMaster 1 +fHsimXmrPropDebug 0 +fHsimXmrElabDebug 0 +fHsimXmrNoMaster 1 +fHsimXmrNoMasterIBIF 1 +fHsimIncrMaster 0 +fHsimEffTest 0 +fHsimIncrTest 0 +fHsimIncrTesting 0 +fHsimOnepass 0 +fHsimPartModSplit 0 +fHsimNoIncrMatch 0 +fHsimMergeOnly 0 +fHsimStitchNew 0 +fHsimCbkOpt 1 +fFrcRelCbk 1 +fPulserrWarn 1 +hsMtmSpec 0 +fprofile 0 +fPreserveDaidir 1 +fHsimLevelize 1 +fHsimSelectLevelize 0 +fHsimSelectEdgeData 0 +fHsimSelectEdgeDataDbg 0 +fHsimSelectEdgeDataSched0 0 +fHsimSelectEdgeDataSanity 0 +fHsimLevelizeFlatNodeLimit 22 +fHsimLevelizeNoSizeLimit 1 +fHsimLevelizeForce 0 +fHsimParallelLevelize 0 +fHsimParallelLevelizeDbg 0 +fHsimLevelizeNoCgDump 0 +fHsimReuseVcs1Sem 0 +semLevelizeVar -1 +fHsimLevelizeDbg 0 +fHsimMinputsPostEval 0 +fHsimSeqUdpDbsByteArray 0 +fHsimHilRtlAny 0 +fHsimHilRtlAll 0 +fHsimCoLocate 0 +fHsimNoinlSched0lq 0 +fHsimUdpOutputOpt 0 +fHsimSeqUdpEblkOpt 0 +fHsimSeqUdpEblkOptDiag 0 +fHsimGateInputAndDbsOffsetsOpt 1 +fHsimRelaxSched0 0 +fHsimLocalVar 0 +fHsimUdpDynElab 0 +fHsimCbDynElab 0 +fHsimCompressData 4 +fHsimIgnoreCaps 0 +fHsimMdbIgnoreCaps 0 +fHsimIgnoreZForDfuse 1 +fHsimIgnoreDifferentCaps 0 +fHsimIgnoreDifferentNStates 0 +fHandleGlitchQC 1 +fGlitchDetectForAllRtlLoads 0 +fHsimAllowFuseOnRegWithMultDrivers 0 +fHsimFuseConstDriversOpt 1 +fHsimMdSchedTr 0 +fHsimIgnoreReElab 0 +fHsimFuseMultiDrivers 0 +fHsimSched0 0 +fHsimPulseFilter 0 +fHsimNoSched0Reg 0 +fHsimAddSched0 0 +fHsimLargeBc 0 +fHsimLargePdbModule 0 +fHsimMMDebug 0 +fHsimMMLimit 0 +hsimMMLimit 0 +fHsimAmsFusionEnabled 0 +fHsimAmsWrealMdrEnabled 0 +fHsimAmsWrealInitValZero 1 +fWrealForce 0 +fHsimCgMarkers 0 +fHsimSplitRmaCode 1 +rmapatsPattCountThreshold 1000 +fHsimElab64 0 +fHsimTestFnn64 0 +fHsimTestDgn64 0 +fHsimRtlDbs 0 +fHsimWakeupId 0 +fHsimPassiveIbn 0 +fHsimInitialConst 0 +fHsimForceRtlDbs 0 +fHsimBcOpt 1 +fHsimBcOptDebug 0 +fHsimBfuseFast 1 +fHsimParallelElab 0 +fHsimParallelElabVcs1 0 +fpicArchive 1 +fCsrcInTmpDir 0 +fHsimInterconFE 1 +fHsimMxOpt 1 +fHsimModpathFE 1 +fHsimPathOnCCN 0 +fHsimOptMPDelayLoad 0 +fHsimTransMPDelay 1 +fLargeSizeSdfTest 0 +fAllMtm 0 +fHsimDelayGateMbme 0 +fHsimDelayGateMbmeOld 0 +fHsimNdb 1 +fHsimNdbDebug 0 +fHsimNdbTest 0 +fHsimGrpByGrpElabIncrTest 0 +fHsimGrpByGrpElabIncrTest2 0 +fHsimTestAggrCg 0 +fHsimOneInputGateAggrCg 0 +fHsimCertitude 0 +fHsimCertRapAutoTest 0 +fHsimRaceDetect 0 +fCheckTcCond 0 +fHsimSimlearnDdce 0 +fHsimSimlearnDdce_diag 0 +fHsimScanOpt 0 +fHsimScanOptPartComp 0 +fHsimHsoptNoScanOpt 0 +fHsimNoScanOptDeadLogic 1 +fHsimScanOptFixForDInSIPath 1 +fHsimNoScanOptForNonScanLoad 0 +fHsimScanOptLoopFix 1 +fHsimScanOptLoopFix2 0 +fHsimScanOptRelaxDbg 0 +fHsimScanOptRelaxDbgDynamic 0 +fHsimScanOptRelaxDbgDynamicPli 0 +fHsimScanOptRelaxDbgDiag 0 +fHsimScanOptRelaxDbgDiagHi 0 +fHsimScanOptNoErrorOnPliAccess 0 +fHsimScanOptTiming 0 +fRelaxIbnSchedCheck 0 +fHsimScanOptNoDumpCombo 0 +fHsimScanOptPrintSwitchState 0 +fHsimScanOptSelectiveSwitchOn 0 +fHsimScanOptSingleSEPliOpt 1 +fHsimScanOptDesignHasDebugAccessOnly 0 +fHsimScanOptPrintPcode 0 +fHsimNettypeOneDrvPerfOpt 0 +fHsimOldNettypeResFnOffset 0 +fHsimScanoptDump 0 +fHsimScanDbgFunc 0 +fHsimScanDbgPerf 0 +fHsimAutoScanSuppWarn 0 +fHsimScanOptAggr 0 +fHsimScanOptFuse 1 +fHsimScanMemOpt 1 +fHsimScanChainOpt 0 +fHsimForceChangeCheck 0 +fHsimFuseConsts 0 +fHsimMemBusOpt 0 +fHsimDefLevelElab 0 +fHsimOneInstElabMods 0 +fHsimOneInstElabModsHeur 1 +fHsimOneInstElabModsAllowDbg 0 +fHsimTopElabMods 0 +fHsimPVCS 0 +fHsimNoStitchMap 0 +fHsimUnifiedModName 0 +fHsimVIIntegrityCheck 0 +fHsimOrigViewType 0 +fHsimXmrDumpFullDR 0 +fHsimXmrDumpDebug 0 +fHsimRTLoopDectEna 0 +fHsimAssertInActive 0 +dGblTeE 1.000000 +dGblTeR 1.000000 +dGblPeE 1.000000 +dGblPeR 1.000000 +fNewdaidirpath 0 +fHsimDelayMbmeCheck 4 +fHsimMdbPartInputLimit 1 +fHsimSdfData 0 +fHsimDesignHasSdfAnnotation 0 +fHsimDesignUsesParallelVcs 0 +fHsimCMEnabled 0 +fGblMSah 0 +fGblMSTe 0 +fGblIntPe 0 +fGblTe 0 +fGblPe 0 +iPulseR 100 +iPulseE 100 +iTransR 100 +iTransE 100 +fPulseOpt 0 +fGblPulseOnD 0 +fGblPulseOnE 0 +fVCSiFlow 0 +fSystemVCSEnabled 1 +fHsimForcedPort 0 +fpicOption 1 +fModelSave 0 +fHsimGenObj 1 +fHsimCbkMemOpt 1 +fHsimCbkMemOptDebug 0 +fHsimMasterModuleOnly 0 +fHsimDumpOriginalFlatNodeNumsMap 0 +fHsimRecordPli 0 +fHsimPlaybackPli 0 +fHsimModByModElabForGates 0 +fHsimMdbOpts 0 +fHsimMdbInlineNew 0 +fHsimMdbSelUdp2Rtl 0 +fHsimMdbUdp2Rtl 0 +fHsimZeroDelayDelta 1 +fHsimMdbUdp2Rtl_3state 0 +fHsimMdbUdp2Rtl_noxedge 0 +fHsimMdbUdp2Rtl_dfsr 0 +fHsimMdbInsertComplexSelect 0 +fHsimMdbNoComplexSelect 0 +fHsimMdbScalarization 0 +fHsimCmplxOperScalarization 0 +fHsimMdbVectorizeInstances2 0 +fHsimMdbVectorizeInstancesCfg 0 +fHsimMdbVectorizeInstDiag 0 +fHsimMdbVectorizeInstances3 0 +fHsimMdbOptimizeSeqUdp 0 +fHsimMdbB2BLatch 0 +fHsimMdbAggr 0 +fHsimMdbGateGroupNew 0 +fHsimMdbUdpGroup 0 +fHsimMdbOptimizeConstants 0 +fHsimMdbDfuse 0 +fHsimMdbBfuse 0 +fHsimMdbDce 0 +fHsimMdbMpopt 0 +fHsimMdbCondMpOpt 0 +fHsimMdbSimplifyMpCond 0 +fHsimDceIgnorecaps 0 +fHsimCondModPathDbs 0 +fHsimCondModPathCompact 0 +fHsimMdbCondMpMerge 0 +fHsimModPathCg 0 +fHsimNoCondModPathCg 0 +fHsimCompactCode 0 +fHsimCondTC 0 +fHsimMacroTC 0 +fHsimCondMPConst 0 +fHsimCondTCConst 0 +fHsimMergeDelay 0 +fHsimDelayOpt 0 +fRemoveDelonTrans 1 +fHsimModPathLoadOpt 1 +fHsimMdbTranOpt 0 +fHsimMdbTranMerge 0 +fHsimRmapatsCsh 0 +fHsimLrmSupply 0 +fHsimNewMbmeFlow 0 +fHsimBackEndInteg 0 +fHsimBackEndIntegCapsOk 0 +fHsimBackEndIntegDiag 0 +fHsimBackEndIntegMaxIbns 1024 +fHsimBackEndIntegDeadObns 0 +fHsimTran2MosDriver 1 +fHsimDumpCcn 0 +fHsimMdbNStateAnalysis 0 +fHsimMdbAdjustWidth 0 +fHsimMdbOptimizeSelects 0 +fHsimMdbScalarizePorts 0 +fHsimMdbOptimizeSelectsHeuristic 1 +fHsimMdbPart 0 +fHsimMdb1006Partition 0 +fHsimVectorPgate 0 +fHsimNoHs 0 +fHsimXmrPartition 0 +fHsimNewPartition 0 +fHsimElabPart 0 +fHsimElabPartThreshHoldDesign 1 +fHsimPMdb 0 +fHsimParitionCellInstNum 1000 +fHsimParitionCellNodeNum 1000 +fHsimParitionCellXMRNum 1000 +fHsimNewPartCutSingleInstLimit 268435455 +fHsimElabModDistNum 0 +fHsimElabPartThreshHoldModule 3000000 +fHsimPCPortPartition 0 +fHsimPortPartition 0 +fHsimMdbHdbsBehavior 0 +fHsimMdbHdbsBehaviorTC 0 +fHsimMdbIbnObnPartition 0 +fHsimMdbDebugOpt0 0 +fHsimMdbClockAnalysis 0 +fHsimMdbMimo 0 +fHsimMdbMimoLite 0 +fHsimMdbMimoAggr 0 +fHsimDumpMdb 0 +fHsimDumpMdbVpd 0 +fHsimElabDiag 0 +fHsimElabMasterDiag 0 +fHsimElabDiagSummary 0 +fHsimElabDiagMn 0 +fHsimElabDiagMnCount 0 +fHsimElabDiagLite 0 +fHsimSimpCollect 0 +fHsimPcodeDiag 0 +fHsimDbsAlwaysBlocks 1 +fHsimPrintNodeMap 0 +fHsimSvAggr 0 +fHsimDynamicFlatNode 0 +fHsimSeqPrimCg 1 +fHsimDiagPats 0 +fHsimDdPats 0 +fHsimPatOpt 3 +fHsimPatInline 0 +fHsimPatOutline 0 +fHsimFastelab 0 +fHsimMacroOpt 0 +fHsimSkipOpt 0 +fHsimSkipOptFanoutlimit 0 +fHsimSkipOptRootlimit 0 +fHsimFuseDelayChains 0 +fFusempchainsFanoutlimit 0 +fFusempchainsDiagCount 0 +fHsimCloadOpt 0 +fHsimNoICDelayPropPwEqDelay 0 +fHsimPrintMopComment 0 +fNewRace 0 +fHsimCgVectorGates 0 +fHsimCgVectorGates1 0 +fHsimCgVectorGates2 0 +fHsimCgVectorGatesNoReElab 0 +fHsimCgScalarGates 0 +fHsimCgScalarGatesExpr 0 +fHsimCgScalarGatesLut 0 +fHsimCgRtl 1 +fHsimCgRtlFilter 0 +fHsimCgRtlDebug 0 +fHsimCgRtlSize 15 +fHsimNewCg 0 +fHsimNewCgRt 0 +fHsimNewCgFg 0 +fHsimNewCgMinput 0 +fHsimNewCgUpdate 0 +fHsimNewCgMP 0 +fHsimNewCgMPRt 0 +fHsimNewCgMPRetain 0 +fHsimNewCgTC 0 +fHsimCgRtlInfra 1 +fHsimGlueOpt 0 +fHsimPGatePatchOpt 0 +fHsimCgNoPic 0 +fHsimElabModCg 0 +fPossibleNullChecks 0 +fHsimProcessNoSplit 1 +fHsimMdbInstDiag 0 +fHsimMdbOptInSchedDelta 0 +fScaleTimeValue 0 +fDebugTimeScale 0 +fPartCompSDF 0 +fHsimNbaGate 1 +fDumpDtviInfoInSC 0 +fDumpSDFBasedMod 1 +fHsimSdfIC 0 +fHsimSdfICOverlap 0 +fHsimSdfICDiag 0 +fHsimSdfICOpt 0 +fHsimMsvSdfInout 0 +fOptimisticNtcSolver 0 +fHsimAllMtm 0 +fHsimAllMtmPat 0 +fHsimSdgOptEnable 0 +fHsimSVTypesRefPorts 0 +fHsimGrpByGrpElabIncr 0 +fHsimGrpByGrpElabIncrDiag 0 +fHsimEvcdTranSeen 0 +fHsimMarkRefereeInVcsElab 0 +fHsimStreamOpFix 1 +fHsimInterface 0 +fHsimNoPruning 0 +fHsimNoVarBidirs 0 +fHsimMxWrapOpt 0 +fHsimMxTopBdryOpt 0 +fHsimAggressiveDce 0 +fHsimDceDebug 1 +fHsimDceDebugUseHeuristics 1 +fHsimMdbUnidirSelects 0 +fHsimMdbNewDebugOpt 0 +fHsimMdbNewDebugOptExitOnError 1 +fHsimNewDebugOptMemDiag 0 +hsGlobalVerboseLevel 0 +fHsimMdbVectorConstProp 1 +fHsimEnableSeqUdpWrite 1 +fHsimDumpMDBOnlyForSeqUdp 0 +fHsimInitRegRandom 0 +fHsimInitRegRandomVcs 1 +fEnableNewFinalStrHash 0 +fEnableNewAssert 1 +fRunDbgDmma 0 +fAssrtCtrlSigChk 1 +fCheckSigValidity 0 +fUniqPriToAstRewrite 0 +fUniqPriToAstCtrl 0 +fAssertcontrolUniqPriNewImpl 0 +fRTLoopDectEna 0 +fCmplLoopDectEna 0 +fHsimMopFlow 1 +fUCaseLabelCtrl 0 +fUniSolRtSvaEna 1 +fUniSolSvaEna 1 +fXpropRtCtrlCallerOnly 0 +fHsimRaptorPart 0 +fHsimEnableDbsMemOpt 1 +fHsimDebugDbsMemOpt 0 +fHsimRenPart 0 +fHsimShortElabInsts 0 +fHsimNoTcSched 0 +fHsimSchedOpt 0 +fHsimXmrAllWires 0 +fHsimXmrDiag 0 +fHsimXmrPort 0 +fHsimFalcon 1 +fHsimGenForProfile 0 +fHsimDumpMdbAll 0 +fHsimDumpMdbRaptor 0 +fHsimDumpMdbGates 0 +fHsimDumpMdbPrune 0 +fHsimDumpMdbInline 0 +fHsimDumpMdbCondTC 0 +fHsimDumpMdbNState 0 +fHsimDumpMdbVhVlInputFuseOpt 0 +fHsimDumpMdbVhVlInoutFuseOpt 0 +fHsimDumpMdbVhVlCcnOpt 0 +fCompressSDF 0 +fHsimDumpMdbSchedDelta 0 +fHsimDumpMdbNoVarBidirs 0 +fHsimDumpMdbScalarize 0 +fHsimDumpMdbVecInst 0 +fHsimDumpMdbVecInst2 0 +fHsimDumpMdbDce 0 +fHsimDumpMdbScanopt 0 +fHsimDumpMdbSelects 0 +fHsimDumpMdbAggr 0 +fHsimDumpMdbOptConst 0 +fHsimDumpMdbVcsInterface 0 +fHsimDumpMdbDfuse 0 +fHsimDumpMdbBfuse 0 +fHsimDumpMdbTranOpt 0 +fHsimDumpMdbOptLoops 0 +fHsimDumpMdbSeqUdp 0 +fHsimDumpMdbMpOpt 0 +fHsimDumpMdbGG 0 +fHsimDumpMdbUdpGG 0 +fHsimDumpMdbMimo 0 +fHsimDumpMdbUdp2rtl 0 +fHsimDumpMdbUdpDelta 0 +fHsimDumpMdbDebugOpt 0 +fHsimDumpMdbSplitGates 0 +fHsimDumpMdb1006Part 0 +fHsimDumpMdbPart 0 +fHsimDumpMdbSimplifyMpCond 0 +fDlpSvtbExclElab 0 +fHsimDumpMdbCondMpMerge 0 +fHsimDumpMdbCondMp 0 +fHsimDumpMdbCondModPathDbs 0 +fHsimSdfAltRetain 0 +fHsimDumpMdbCompress 1 +fHsimDumpMdbSummary 0 +fHsimBfuseOn 1 +fHsimBfuseHeur 0 +fHsimBfuseHash 1 +fHsimSelectCell 0 +fHsimBfuseNoRedundantFanout 1 +fHsimBFuseVectorMinputGates 0 +fHsimBFuseVectorAlways 0 +fHsimDfuseOn 1 +fHsimDumpMdbPruneVpdGates 0 +fHsimGates1209 0 +fHsimCgRtlNoShareSmd 0 +fHsimGenForErSum 0 +fVpdOpt 1 +fHsimMdbCell 0 +fHsimCellDebug 0 +fHsimMdbCellComplexity 1.500000 +fHsimMdbCellHeur 1 +fHsimNoPeekInMdbCell 0 +fDebugDump 1 +fHsimOrigNodeNames 0 +hsimSrcList filelist +fHsimCgVectors2VOnly 0 +fHsimPortCoerce 0 +fHsimBidirOpt 0 +fHsimCheckLoop 1 +fHsimCheckLoopDiag 0 +fHsimCheckLoopMore 0 +fHsimLoop 1 +fHsimMdbDeltaGate 0 +fHsimMdbDeltaGateAggr 0 +fHsimMdbVecDeltaGate 1 +fHsimVpdOptVfsDB 1 +fHsimMdbPruneVpdGates 1 +fHsimPcPe 0 +fHsimVpdGateOnlyFlag 1 +fHsimMxConnFrc 0 +fHsimNewForceCbkVec 0 +fHsimNewForceCbkVecDiag 0 +fHsimMdbReplaceVpdHighConn 1 +fHsimVpdHighConnReplaced 1 +fHsimVpdOptSVTypes 1 +fHsimDlyInitFrc 0 +fHsimCompactVpdFn 1 +fHsimPIP 0 +fHsimRTLoopDectOrgName 0 +fHsimVpdOptPC 0 +fHsimFusePeXmrFo 0 +fHsimXmrSched 0 +fHsimNoMdg 0 +fHsimUseBidirSelectsInVectorGates 0 +fHsimGates2 0 +fHsimVectorGates 0 +fHsimHilCg 0 +fHsimHilVecAndRtl 0 +fHsimRtlLite 0 +fHsimMdbcgLut 0 +fHsimMdbcgSelective 0 +fHsimVcselabGates 0 +fHsimMdbcgUnidirSel 0 +fHsimMdbcgLhsConcat 0 +fHsimMdbcgSelectSplit 0 +fHsimMdbcgProcessSelSplit 0 +fHsimMdbcgEdgeop 0 +fHsimMdbcgMultiDelayControl 1 +fHsimParGateEvalMode 0 +fHsimDFuseVectors 0 +fHsimDFuseVecIgnoreFrc 0 +fHsimDFuseZero 0 +fHsimDFuseOpt 1 +fHsimAllPortsDiag 0 +fHsimPruneOpt 0 +fHsimSeqUdpPruneWithConstInputs 0 +fHsimSafeDFuse 0 +fHsimVpdOptExpVec 0 +fHsimVpdOptSelGate 1 +fHsimVpdOptSkipFuncPorts 0 +fHsimVpdOptAlways 1 +fHsimVpdOptMdbCell 0 +fHsimVpdOptPartialMdb 1 +fHsimVpdOptPartitionGate 1 +fHsimVpdOptXmr 1 +fHsimVpdOptConst 1 +fHsimVpdOptMoreLevels 1 +fHsimVpdHilRtl 0 +fHsimSWave 0 +fHsimNoSched0InCell 1 +fHsimPartialMdb 0 +hsimPdbLargeOffsetThreshold 1048576 +fHsimFlatCell 0 +fHsimFlatCellLimit 0 +fHsimRegBank 0 +fHsimHmetisMaxPartSize 0 +fHsimHmetisGateWt 0 +fHsimHmetisUbFactor 0 +fHsimHmetis 0 +fHsimHmetisDiag 0 +fHsimRenumGatesForMdbCell 0 +fHsimHmetisMinPart 0 +fHsim2stCell 0 +fHsim2stCellMinSize 0 +fHsimMdbcgDebug 0 +fHsimMdbcgDebugLite 0 +fHsimMdbcgDistrib 0 +fHsimMdbcgSepmem 0 +fHsimMdbcgObjDiag 0 +fHsimMdbcg2stDiag 0 +fHsimMdbcgRttrace 0 +fHsimMdbVectorGateGroup 1 +fHsimMdbProcDfuse 1 +fHsimMdbHilPrune 0 +fHsimNewConstProp 0 +fHsimSignedOp 0 +fHsimVarIndex 0 +fHsimNewMdbNstate 0 +fHsimProcessNstate 0 +fHsimMdbModpathNstate 0 +fHsimPgateConst 0 +fHsCgOpt 1 +fHsCgOptUdp 1 +fHsCgOptRtl 1 +fHsCgOptDiag 0 +fHsCgOptAggr 0 +fHsCgOptNoZCheck 0 +fHsCgOptEnableZSupport 0 +fHsCgOpt4StateInfra 0 +fHsCgOptDce 0 +fHsCgOptUdpChkDataForWakeup 1 +fHsNBACgOpt 1 +fHsCgOptXprop 0 +fHsimMdbcgDiag 0 +fHsCgMaxInputs 6 +fHsimMemory 0 +fHsCgOptFwdPass 1 +fHsimHpnodes 0 +fLightDump 0 +fRtdbgAccess 0 +fRtdbgOption 0 +fHDLCosim 0 +fHDLCosimDebug 0 +fHDLCosimTimeCoupled 0 +fHDLCosimTimeCoupledPorts 0 +HDLCosimMaxDataPerDpi 1 +HDLCosimMaxCallsPerDpi 2147483647 +fHDLCosimCompileDUT 0 +fHDLCosimCustomCompile 0 +fHDLCosimBoundaryAnalysis 0 +fVpdBeforeScan 1 +fHsCgOptMiSched0 0 +fgcAddSched0 0 +fParamClassOptRtDiag 0 +fHsRegress 0 +fHsBenchmark 0 +fHsimCgScalarVerilogForce 1 +fVcsElabToRoot 1 +fHilIbnObnCallByName 0 +fHsimMdbcgCellPartition 0 +fHsimCompressVpdSig 0 +fHsimLowPowerOpt 0 +fHsimUdpOpt 1 +fHsVecOneld 0 +fNativeVpdDebug 0 +fNewDtviFuse 0 +fHsimVcsGenTLS 1 +fAssertSuccDebugLevelDump 0 +fHsimMinputsChangeCheck 0 +fHsimClkLayout 0 +fHsimIslandLayout 0 +fHsimConfigSched0 0 +fHsimSelectFuseAfterDfuse 0 +vcsNettypeDbgOpt 4 +fHsimFoldedCell 0 +fHsimSimon2Mdb 0 +fHsimSWaveEmul 0 +fHsimSWaveDumpMDB 0 +fHsimSWaveDumpFlatData 0 +fHsimRenumberAlias 0 +fHsimAliasRenumbered 0 +fHilCgMode 115 +fHsimUnionOpt 0 +fHsimFuseSGDBoundaryNodes 0 +fHsimRemoveCapsVec 0 +fHsimSlowNfsRmapats 0 +fHsimCertRaptScal 0 +fHsimCertRaptMdbClock 0 +fHsCgOptMux 0 +fHsCgOptFrc 0 +fHsCgOpt30 0 +fHsLpNoCapsOpt 0 +fHsCgOpt4State 1 +fHashTableSize 12 +fSkipStrChangeOnDelay 1 +fHsimTcheckOpt 0 +fHsCgOptMuxMClk 0 +fHsCgOptMuxFrc 0 +fHsCgOptNoPcb 0 +fHsCgOptMin1 0 +fHsCgOptUdpChk 0 +fHsChkXForSlowSigProp 1 +fHsimVcsParallelDbg 0 +fHsimVcsParallelStrategy 0 +fHsimVcsParallelOpt 0 +fHsimVcsParallelSubLevel 4 +fHsimParallelEblk 0 +fHsimByteCodeParts 1 +fHsimByteCodePartTesting 0 +fHsimByteCodePartAssert 0 +fFgpNovlInComp 0 +fFutEventPRL 0 +fFgpNbaDelay 0 +fHsimDbsFlagsByteArray 0 +fHsimDbsFlagsByteArrayTC 0 +fHsimDbsFlagsThreadArray 0 +fHsimLevelCompaction 0 +fHsimLevelCompactionThreshold 0 +fHsimGateEdgeEventSched 0 +fHsimGateEdgeEventSchedThreshold 0 +fHsimGateEdgeEventSchedSanity 0 +fHsimSelectEdgeEventSched 0 +fHsimSelectEdgeEventSchedNoTempReuse 0 +fHsimSelectEdgeEventSchedThreshold 0 +fHsimMaxComboLevels 0 +fHsimEgschedDynelab 0 +fHsimUdpClkDynelab 0 +fUdpLayoutOnClk 0 +fHsimDiagClk 1 +fDbsPreCheck 0 +fHsimSched0Analysis 0 +fHsimMultiDriverSched0 0 +fHsimLargeIbnSched 0 +fFgpHierarchical 0 +fFgpHierAllElabModAsRoot 0 +fFgpHierPCElabModAsRoot 0 +fFgpAdjustDataLevelOfLatch 1 +fHsimUdpXedgeEval 0 +fFgpRaceCheck 0 +fFgpUnifyClk 0 +fFgpSmallClkTree 0 +fFgpSmallRtlClkTree 4 +fFgpNoRtlUnlink 0 +fFgpNoRtlAuxLevel 0 +fFgpNumPartitions 8 +fFgpMultiSocketCompile 0 +fFgpMultiSocketAfterGrping 0 +fFgpMultiSocketNCuts 1 +fFgpMultiSocketDiag 0 +fFgpMultiSocketRecomputePart 1 +fFgpDataDepOn 0 +fFgpDDIgnore 0 +fFgpXmrDepOn 0 +fFgpTbCbOn 0 +fFgpTbEvOn 1 +fFgpTbNoVSA 0 +fFgpTbEvXmr 0 +fFgpTbEvCgCall 1 +fFgpDisabledLevel 512 +fFgpSched0User 0 +fFgpNoSdDelayedNbas 1 +fFgpTimingFlags 0 +fFgpTcLoadThreshold 0 +fFgpSched0Level 0 +fHsimFgpMultiClock 0 +fFgpScanOptFix 0 +fFgpSched0UdpData 0 +fFgpSanityTest 0 +fFgpSanityTest_Eng 1 +fFgpAlternativeLevelization 0 +fFgpHighFanoutThreshold 1024 +fFgpSplitGroupLevels 1 +fFgpSplitGroupIbn 1 +fFgpSplitGroupGateEdge 1 +fFgpSplitGroupEval 3 +fFgpGroupingPerfDiag 0 +fFgpSplitGroupDiag 0 +fFgpStricDepModDiag 0 +fFgpIPProtect 0 +fFgpIPProtectStrict 0 +fFgpNoVirtualThreads 0 +fFgpLoadBalance0DiagComp 0 +fFgpLoadBalance0CompileTime 1 +fFgpDepositDiag 0 +fFgpEvtDiag.diagOn 0 +fFgpEvtDiag.printAllNodes 0 +fFgpMangleDiagLog 0 +fFgpMultiExclDiag 0 +fFgpSingleExclReason 0 +fHsDoFaninFanoutSanity 0 +fHsFgpNonDbsOva 1 +fFgpParallelTask 1 +fFgpIbnSched 0 +fFgpIbnSchedOpt 0 +fFgpIbnSchedNoLevel 0 +fFgpIbnSchedThreshold 0 +fFgpIbnSchedDyn 0 +fFgpObnSched 0 +fFgpMpStateByte 0 +fFgpTcStateByte 0 +fHsimVirtIntfDynLoadSched 0 +fHsimNetXmrDrvChk 0 +fFgpNoRtimeFgp 0 +fHsFgpGlSched0 0 +fFgpExclReason 0 +fHsimIslandByIslandElab 0 +fHsimIslandByIslandFlat 0 +fHsimIslandByIslandFlat1 0 +fHsimVpdIBIF 0 +fHsimXmrIBIF 0 +fHsimReportTime 0 +fHsimElabJ 0 +fHsimElabJ4SDF 0 +cElabProcs 0 +hf_fHsimElabJ 0 +fHsimElabJOpt 0 +fHsimElabJMMFactor 0 +fHsimOneInstCap 0 +fHsimSchedMinput 0 +fHsimSchedSeqPrim 0 +fHsimSchedRandom 0 +fHsimSchedAll 0 +fHsimSchedSelectFanout 0 +fHsimSchedSelectFanoutDebug 0 +fHsimSchedSelectFanoutRandom 0 +fFgpDynamicReadOn 0 +fHsCgOptAllUc 0 +fHsimNoReconvergenceSched0 0 +fHsimXmrRepl 0 +fZoix 0 +fHsimDfuseNewOpt 0 +fHsimBfuseNewOpt 0 +fFgpMbme 0 +fFgpXmrSched 0 +fHsimClearClkCaps 0 +fFgpHideXmrNodes 0 +fHsimDiagClkConfig 0 +fHsimDiagClkConfigDebug 0 +fHsimDiagClkConfigDumpAll 0 +fHsDiagClkConfigPara 0 +fHsimDiagClkConfigAn 0 +fHsimCanDumpClkConfig 0 +fFgpInitRout 0 +fFgpIgnoreExclSD 0 +fHsimAggrTCOpt 0 +fFgpNewAggrXmrIterFlow 0 +fFgpNoLocalReferer 0 +fHsCgOptNoClockFusing 0 +fHsClkWheelLimit 50000 +fHsFgpSchedCgUcLoads 1 +fHsimAdvanceUdpInfer 0 +fFgpIbnSchedIntf 0 +fHsCgOptNewSelCheck 1 +fFgpReportUnsafeFuncs 0 +fHsCgOptUncPrlThreshold 4 +fHsimCosimGatesProp 0 +fHsSVNettypePerfOpt 0 +fHsCgOptHashFixMap 1 +fHsimLowPowerRetAnalysisInChild 0 +fRetainWithDelayedSig 0 +fHsimChargeDecay 0 +fHsimCongruencyConfigFile 0 +fHsimCongruencyLogFile 0 +fHsimCoverageEnabled 0 +fHsimCoverageOptions 0 +fHsimCoverageDir NULL diff --git a/tb/digital_top/simv.daidir/vcselab_misc_hsim_fegate.db b/tb/digital_top/simv.daidir/vcselab_misc_hsim_fegate.db new file mode 100644 index 0000000..3c0770d Binary files /dev/null and b/tb/digital_top/simv.daidir/vcselab_misc_hsim_fegate.db differ diff --git a/tb/digital_top/simv.daidir/vcselab_misc_hsim_lvl.db b/tb/digital_top/simv.daidir/vcselab_misc_hsim_lvl.db new file mode 100644 index 0000000..61e7af4 Binary files /dev/null and b/tb/digital_top/simv.daidir/vcselab_misc_hsim_lvl.db differ diff --git a/tb/digital_top/simv.daidir/vcselab_misc_hsim_merge.db b/tb/digital_top/simv.daidir/vcselab_misc_hsim_merge.db new file mode 100644 index 0000000..c51f36f Binary files /dev/null and b/tb/digital_top/simv.daidir/vcselab_misc_hsim_merge.db differ diff --git a/tb/digital_top/simv.daidir/vcselab_misc_hsim_name.db b/tb/digital_top/simv.daidir/vcselab_misc_hsim_name.db new file mode 100644 index 0000000..1781b5a Binary files /dev/null and b/tb/digital_top/simv.daidir/vcselab_misc_hsim_name.db differ diff --git a/tb/digital_top/simv.daidir/vcselab_misc_hsim_uds.db b/tb/digital_top/simv.daidir/vcselab_misc_hsim_uds.db new file mode 100644 index 0000000..b994050 --- /dev/null +++ b/tb/digital_top/simv.daidir/vcselab_misc_hsim_uds.db @@ -0,0 +1,815 @@ +vcselab_misc_midd.db 40517 +vcselab_misc_mnmn.db 854 +vcselab_misc_hsim_name.db 10229 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 920160 +vcselab_misc_midd.db 40533 +vcselab_misc_mnmn.db 854 +vcselab_misc_hsim_name.db 10241 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 918684 +vcselab_misc_midd.db 40533 +vcselab_misc_mnmn.db 854 +vcselab_misc_hsim_name.db 10241 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 918684 +vcselab_misc_midd.db 40533 +vcselab_misc_mnmn.db 854 +vcselab_misc_hsim_name.db 10241 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 918684 +vcselab_misc_midd.db 40533 +vcselab_misc_mnmn.db 854 +vcselab_misc_hsim_name.db 10241 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 918684 +vcselab_misc_midd.db 40485 +vcselab_misc_mnmn.db 849 +vcselab_misc_hsim_name.db 10249 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 927148 +vcselab_misc_midd.db 40485 +vcselab_misc_mnmn.db 849 +vcselab_misc_hsim_name.db 10249 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 927148 +vcselab_misc_midd.db 40477 +vcselab_misc_mnmn.db 840 +vcselab_misc_hsim_name.db 10233 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 927148 +vcselab_misc_midd.db 40477 +vcselab_misc_mnmn.db 840 +vcselab_misc_hsim_name.db 10233 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 927148 +vcselab_misc_midd.db 40477 +vcselab_misc_mnmn.db 840 +vcselab_misc_hsim_name.db 10233 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 927148 +vcselab_misc_midd.db 40477 +vcselab_misc_mnmn.db 840 +vcselab_misc_hsim_name.db 10233 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 927148 +vcselab_misc_midd.db 40477 +vcselab_misc_mnmn.db 840 +vcselab_misc_hsim_name.db 10233 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 927148 +vcselab_misc_midd.db 40477 +vcselab_misc_mnmn.db 840 +vcselab_misc_hsim_name.db 10233 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 927148 +vcselab_misc_midd.db 40477 +vcselab_misc_mnmn.db 840 +vcselab_misc_hsim_name.db 10233 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 927220 +vcselab_misc_midd.db 40477 +vcselab_misc_mnmn.db 840 +vcselab_misc_hsim_name.db 10233 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 927220 +vcselab_misc_midd.db 40477 +vcselab_misc_mnmn.db 840 +vcselab_misc_hsim_name.db 10233 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 927396 +vcselab_misc_midd.db 40477 +vcselab_misc_mnmn.db 840 +vcselab_misc_hsim_name.db 10233 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 927388 +vcselab_misc_midd.db 40477 +vcselab_misc_mnmn.db 840 +vcselab_misc_hsim_name.db 10233 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 927388 +vcselab_misc_midd.db 40477 +vcselab_misc_mnmn.db 840 +vcselab_misc_hsim_name.db 10233 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 927388 +vcselab_misc_midd.db 40477 +vcselab_misc_mnmn.db 840 +vcselab_misc_hsim_name.db 10233 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 927388 +vcselab_misc_midd.db 40477 +vcselab_misc_mnmn.db 840 +vcselab_misc_hsim_name.db 10233 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 927388 +vcselab_misc_midd.db 40477 +vcselab_misc_mnmn.db 840 +vcselab_misc_hsim_name.db 10233 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 927388 +vcselab_misc_midd.db 40477 +vcselab_misc_mnmn.db 840 +vcselab_misc_hsim_name.db 10233 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 927388 +vcselab_misc_midd.db 40477 +vcselab_misc_mnmn.db 840 +vcselab_misc_hsim_name.db 10233 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 927388 +vcselab_misc_midd.db 40477 +vcselab_misc_mnmn.db 840 +vcselab_misc_hsim_name.db 10233 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 927388 +vcselab_misc_midd.db 40477 +vcselab_misc_mnmn.db 840 +vcselab_misc_hsim_name.db 10233 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 927388 +vcselab_misc_midd.db 40477 +vcselab_misc_mnmn.db 840 +vcselab_misc_hsim_name.db 10233 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 932284 +vcselab_misc_midd.db 40477 +vcselab_misc_mnmn.db 840 +vcselab_misc_hsim_name.db 10233 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 934732 +vcselab_misc_midd.db 40477 +vcselab_misc_mnmn.db 840 +vcselab_misc_hsim_name.db 10233 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 934612 +vcselab_misc_midd.db 40477 +vcselab_misc_mnmn.db 840 +vcselab_misc_hsim_name.db 10233 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 934612 +vcselab_misc_midd.db 40477 +vcselab_misc_mnmn.db 840 +vcselab_misc_hsim_name.db 10233 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 934612 +vcselab_misc_midd.db 40477 +vcselab_misc_mnmn.db 840 +vcselab_misc_hsim_name.db 10233 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 934612 +vcselab_misc_midd.db 40477 +vcselab_misc_mnmn.db 840 +vcselab_misc_hsim_name.db 10233 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 934612 +vcselab_misc_midd.db 40477 +vcselab_misc_mnmn.db 840 +vcselab_misc_hsim_name.db 10233 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 934612 +vcselab_misc_midd.db 40477 +vcselab_misc_mnmn.db 840 +vcselab_misc_hsim_name.db 10233 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 934612 +vcselab_misc_midd.db 40477 +vcselab_misc_mnmn.db 840 +vcselab_misc_hsim_name.db 10233 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 934612 +vcselab_misc_midd.db 40477 +vcselab_misc_mnmn.db 840 +vcselab_misc_hsim_name.db 10233 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 934612 +vcselab_misc_midd.db 40477 +vcselab_misc_mnmn.db 840 +vcselab_misc_hsim_name.db 10233 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 934612 +vcselab_misc_midd.db 40477 +vcselab_misc_mnmn.db 840 +vcselab_misc_hsim_name.db 10233 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 934612 +vcselab_misc_midd.db 40477 +vcselab_misc_mnmn.db 840 +vcselab_misc_hsim_name.db 10233 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 934612 +vcselab_misc_midd.db 40477 +vcselab_misc_mnmn.db 840 +vcselab_misc_hsim_name.db 10233 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 934612 +vcselab_misc_midd.db 40477 +vcselab_misc_mnmn.db 840 +vcselab_misc_hsim_name.db 10233 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 934544 +vcselab_misc_midd.db 40477 +vcselab_misc_mnmn.db 840 +vcselab_misc_hsim_name.db 10233 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 934544 +vcselab_misc_midd.db 40477 +vcselab_misc_mnmn.db 840 +vcselab_misc_hsim_name.db 10233 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 934612 +vcselab_misc_midd.db 40477 +vcselab_misc_mnmn.db 840 +vcselab_misc_hsim_name.db 10233 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 934612 +vcselab_misc_midd.db 40513 +vcselab_misc_mnmn.db 828 +vcselab_misc_hsim_name.db 10181 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 934696 +vcselab_misc_midd.db 40513 +vcselab_misc_mnmn.db 828 +vcselab_misc_hsim_name.db 10181 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 934696 +vcselab_misc_midd.db 40513 +vcselab_misc_mnmn.db 828 +vcselab_misc_hsim_name.db 10181 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 934696 +vcselab_misc_midd.db 40513 +vcselab_misc_mnmn.db 828 +vcselab_misc_hsim_name.db 10181 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 934696 +vcselab_misc_midd.db 40513 +vcselab_misc_mnmn.db 828 +vcselab_misc_hsim_name.db 10181 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 934696 +vcselab_misc_midd.db 40513 +vcselab_misc_mnmn.db 828 +vcselab_misc_hsim_name.db 10181 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 934696 +vcselab_misc_midd.db 40513 +vcselab_misc_mnmn.db 828 +vcselab_misc_hsim_name.db 10181 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 934696 +vcselab_misc_midd.db 40513 +vcselab_misc_mnmn.db 828 +vcselab_misc_hsim_name.db 10181 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 934696 +vcselab_misc_midd.db 40513 +vcselab_misc_mnmn.db 828 +vcselab_misc_hsim_name.db 10181 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 934696 +vcselab_misc_midd.db 40513 +vcselab_misc_mnmn.db 828 +vcselab_misc_hsim_name.db 10181 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 934696 +vcselab_misc_midd.db 40513 +vcselab_misc_mnmn.db 828 +vcselab_misc_hsim_name.db 10181 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 934776 +vcselab_misc_midd.db 40513 +vcselab_misc_mnmn.db 828 +vcselab_misc_hsim_name.db 10181 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 937816 +vcselab_misc_midd.db 40513 +vcselab_misc_mnmn.db 828 +vcselab_misc_hsim_name.db 10181 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 939736 +vcselab_misc_midd.db 40317 +vcselab_misc_mnmn.db 828 +vcselab_misc_hsim_name.db 10181 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 941832 +vcselab_misc_midd.db 40317 +vcselab_misc_mnmn.db 828 +vcselab_misc_hsim_name.db 10181 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 941744 +vcselab_misc_midd.db 40833 +vcselab_misc_mnmn.db 828 +vcselab_misc_hsim_name.db 10325 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 970096 +vcselab_misc_midd.db 40833 +vcselab_misc_mnmn.db 828 +vcselab_misc_hsim_name.db 10325 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 969500 +vcselab_misc_midd.db 40833 +vcselab_misc_mnmn.db 828 +vcselab_misc_hsim_name.db 10325 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 963816 +vcselab_misc_midd.db 39905 +vcselab_misc_mnmn.db 717 +vcselab_misc_hsim_name.db 9977 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 867108 +vcselab_misc_midd.db 39905 +vcselab_misc_mnmn.db 717 +vcselab_misc_hsim_name.db 9977 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 867432 +vcselab_misc_midd.db 39905 +vcselab_misc_mnmn.db 717 +vcselab_misc_hsim_name.db 9977 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 866640 +vcselab_misc_midd.db 39905 +vcselab_misc_mnmn.db 717 +vcselab_misc_hsim_name.db 9977 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 864264 +vcselab_misc_midd.db 40833 +vcselab_misc_mnmn.db 828 +vcselab_misc_hsim_name.db 10325 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 960976 +vcselab_misc_midd.db 40833 +vcselab_misc_mnmn.db 828 +vcselab_misc_hsim_name.db 10325 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 960976 +vcselab_misc_midd.db 40833 +vcselab_misc_mnmn.db 828 +vcselab_misc_hsim_name.db 10325 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 960976 +vcselab_misc_midd.db 40833 +vcselab_misc_mnmn.db 828 +vcselab_misc_hsim_name.db 10325 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 960976 +vcselab_misc_midd.db 40833 +vcselab_misc_mnmn.db 828 +vcselab_misc_hsim_name.db 10325 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 961520 +vcselab_misc_midd.db 40833 +vcselab_misc_mnmn.db 828 +vcselab_misc_hsim_name.db 10325 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 961456 +vcselab_misc_midd.db 40833 +vcselab_misc_mnmn.db 828 +vcselab_misc_hsim_name.db 10325 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 961456 +vcselab_misc_midd.db 40833 +vcselab_misc_mnmn.db 828 +vcselab_misc_hsim_name.db 10325 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 961456 +vcselab_misc_midd.db 40833 +vcselab_misc_mnmn.db 828 +vcselab_misc_hsim_name.db 10325 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 961456 +vcselab_misc_midd.db 40833 +vcselab_misc_mnmn.db 828 +vcselab_misc_hsim_name.db 10325 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 961372 +vcselab_misc_midd.db 40837 +vcselab_misc_mnmn.db 828 +vcselab_misc_hsim_name.db 10325 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 961132 +vcselab_misc_midd.db 40833 +vcselab_misc_mnmn.db 828 +vcselab_misc_hsim_name.db 10325 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 961372 +vcselab_misc_midd.db 40833 +vcselab_misc_mnmn.db 828 +vcselab_misc_hsim_name.db 10325 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 961132 +vcselab_misc_midd.db 40877 +vcselab_misc_mnmn.db 828 +vcselab_misc_hsim_name.db 10333 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 961484 +vcselab_misc_midd.db 40833 +vcselab_misc_mnmn.db 828 +vcselab_misc_hsim_name.db 10325 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 961372 +vcselab_misc_midd.db 40833 +vcselab_misc_mnmn.db 828 +vcselab_misc_hsim_name.db 10325 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 961372 +vcselab_misc_midd.db 40953 +vcselab_misc_mnmn.db 843 +vcselab_misc_hsim_name.db 10409 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 965600 +vcselab_misc_midd.db 40953 +vcselab_misc_mnmn.db 843 +vcselab_misc_hsim_name.db 10409 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 965592 +vcselab_misc_midd.db 40953 +vcselab_misc_mnmn.db 843 +vcselab_misc_hsim_name.db 10409 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 965040 +vcselab_misc_midd.db 40953 +vcselab_misc_mnmn.db 843 +vcselab_misc_hsim_name.db 10409 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 965040 +vcselab_misc_midd.db 41181 +vcselab_misc_mnmn.db 842 +vcselab_misc_hsim_name.db 10453 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 967560 +vcselab_misc_midd.db 41181 +vcselab_misc_mnmn.db 842 +vcselab_misc_hsim_name.db 10453 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 967560 +vcselab_misc_midd.db 41181 +vcselab_misc_mnmn.db 842 +vcselab_misc_hsim_name.db 10453 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 967560 +vcselab_misc_midd.db 41181 +vcselab_misc_mnmn.db 842 +vcselab_misc_hsim_name.db 10453 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 967560 +vcselab_misc_midd.db 41181 +vcselab_misc_mnmn.db 842 +vcselab_misc_hsim_name.db 10453 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 988508 +vcselab_misc_midd.db 41181 +vcselab_misc_mnmn.db 842 +vcselab_misc_hsim_name.db 10453 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 988508 +vcselab_misc_midd.db 41181 +vcselab_misc_mnmn.db 842 +vcselab_misc_hsim_name.db 10453 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 988524 +vcselab_misc_midd.db 41181 +vcselab_misc_mnmn.db 842 +vcselab_misc_hsim_name.db 10453 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 989540 +vcselab_misc_midd.db 41181 +vcselab_misc_mnmn.db 842 +vcselab_misc_hsim_name.db 10453 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 989540 +vcselab_misc_midd.db 41333 +vcselab_misc_mnmn.db 842 +vcselab_misc_hsim_name.db 10469 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 990796 +vcselab_misc_midd.db 41253 +vcselab_misc_mnmn.db 842 +vcselab_misc_hsim_name.db 10469 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 990556 +vcselab_misc_midd.db 41253 +vcselab_misc_mnmn.db 822 +vcselab_misc_hsim_name.db 10397 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 989744 +vcselab_misc_midd.db 41253 +vcselab_misc_mnmn.db 822 +vcselab_misc_hsim_name.db 10397 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 989744 +vcselab_misc_midd.db 41701 +vcselab_misc_mnmn.db 902 +vcselab_misc_hsim_name.db 10601 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 1181868 +vcselab_misc_midd.db 41701 +vcselab_misc_mnmn.db 902 +vcselab_misc_hsim_name.db 10601 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 1182100 +vcselab_misc_midd.db 41701 +vcselab_misc_mnmn.db 902 +vcselab_misc_hsim_name.db 10601 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 1182100 +vcselab_misc_midd.db 41701 +vcselab_misc_mnmn.db 902 +vcselab_misc_hsim_name.db 10601 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 1182100 +vcselab_misc_midd.db 41701 +vcselab_misc_mnmn.db 902 +vcselab_misc_hsim_name.db 10601 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 1182100 +vcselab_misc_midd.db 41701 +vcselab_misc_mnmn.db 902 +vcselab_misc_hsim_name.db 10601 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 1156672 +vcselab_misc_midd.db 41701 +vcselab_misc_mnmn.db 902 +vcselab_misc_hsim_name.db 10601 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 1156672 +vcselab_misc_midd.db 41701 +vcselab_misc_mnmn.db 902 +vcselab_misc_hsim_name.db 10601 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 1156672 +vcselab_misc_midd.db 41253 +vcselab_misc_mnmn.db 822 +vcselab_misc_hsim_name.db 10397 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 941540 +vcselab_misc_midd.db 41253 +vcselab_misc_mnmn.db 822 +vcselab_misc_hsim_name.db 10397 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 940276 +vcselab_misc_midd.db 41253 +vcselab_misc_mnmn.db 822 +vcselab_misc_hsim_name.db 10397 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 939496 +vcselab_misc_midd.db 41253 +vcselab_misc_mnmn.db 822 +vcselab_misc_hsim_name.db 10397 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 939496 +vcselab_misc_midd.db 41253 +vcselab_misc_mnmn.db 822 +vcselab_misc_hsim_name.db 10397 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 939496 +vcselab_misc_midd.db 41253 +vcselab_misc_mnmn.db 822 +vcselab_misc_hsim_name.db 10397 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 939432 +vcselab_misc_midd.db 41541 +vcselab_misc_mnmn.db 902 +vcselab_misc_hsim_name.db 10593 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 1121932 +vcselab_misc_midd.db 41541 +vcselab_misc_mnmn.db 902 +vcselab_misc_hsim_name.db 10593 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 1121932 +vcselab_misc_midd.db 41541 +vcselab_misc_mnmn.db 902 +vcselab_misc_hsim_name.db 10593 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 1121952 +vcselab_misc_midd.db 41541 +vcselab_misc_mnmn.db 902 +vcselab_misc_hsim_name.db 10593 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 1121936 +vcselab_misc_midd.db 41581 +vcselab_misc_mnmn.db 902 +vcselab_misc_hsim_name.db 10601 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 1122300 +vcselab_misc_midd.db 41581 +vcselab_misc_mnmn.db 902 +vcselab_misc_hsim_name.db 10601 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 1122436 +vcselab_misc_midd.db 41581 +vcselab_misc_mnmn.db 902 +vcselab_misc_hsim_name.db 10601 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 1122436 +vcselab_misc_midd.db 41581 +vcselab_misc_mnmn.db 902 +vcselab_misc_hsim_name.db 10601 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 1122436 +vcselab_misc_midd.db 41581 +vcselab_misc_mnmn.db 902 +vcselab_misc_hsim_name.db 10601 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 1122436 +vcselab_misc_midd.db 41581 +vcselab_misc_mnmn.db 902 +vcselab_misc_hsim_name.db 10601 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 1122436 +vcselab_misc_midd.db 41581 +vcselab_misc_mnmn.db 902 +vcselab_misc_hsim_name.db 10601 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 1122436 +vcselab_misc_midd.db 41581 +vcselab_misc_mnmn.db 902 +vcselab_misc_hsim_name.db 10601 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 1122444 +vcselab_misc_midd.db 41581 +vcselab_misc_mnmn.db 902 +vcselab_misc_hsim_name.db 10601 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 1122588 +vcselab_misc_midd.db 41581 +vcselab_misc_mnmn.db 902 +vcselab_misc_hsim_name.db 10601 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 1122588 +vcselab_misc_midd.db 41581 +vcselab_misc_mnmn.db 902 +vcselab_misc_hsim_name.db 10601 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 1122588 +vcselab_misc_midd.db 41581 +vcselab_misc_mnmn.db 902 +vcselab_misc_hsim_name.db 10601 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 1122588 +vcselab_misc_midd.db 41581 +vcselab_misc_mnmn.db 902 +vcselab_misc_hsim_name.db 10601 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 1122588 +vcselab_misc_midd.db 41729 +vcselab_misc_mnmn.db 902 +vcselab_misc_hsim_name.db 10613 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 1123492 +vcselab_misc_midd.db 41729 +vcselab_misc_mnmn.db 902 +vcselab_misc_hsim_name.db 10613 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 1123492 +vcselab_misc_midd.db 41729 +vcselab_misc_mnmn.db 929 +vcselab_misc_hsim_name.db 10697 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 1124664 +vcselab_misc_midd.db 41641 +vcselab_misc_mnmn.db 929 +vcselab_misc_hsim_name.db 10681 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 1132260 +vcselab_misc_midd.db 41641 +vcselab_misc_mnmn.db 929 +vcselab_misc_hsim_name.db 10681 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 1132380 +vcselab_misc_midd.db 41641 +vcselab_misc_mnmn.db 929 +vcselab_misc_hsim_name.db 10681 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 1132380 +vcselab_misc_midd.db 41641 +vcselab_misc_mnmn.db 929 +vcselab_misc_hsim_name.db 10681 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 1132380 +vcselab_misc_midd.db 41601 +vcselab_misc_mnmn.db 929 +vcselab_misc_hsim_name.db 10673 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 1132020 +vcselab_misc_midd.db 41601 +vcselab_misc_mnmn.db 929 +vcselab_misc_hsim_name.db 10673 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 1131676 +vcselab_misc_midd.db 41601 +vcselab_misc_mnmn.db 929 +vcselab_misc_hsim_name.db 10673 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 1131676 +vcselab_misc_midd.db 41601 +vcselab_misc_mnmn.db 929 +vcselab_misc_hsim_name.db 10673 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 1131676 +vcselab_misc_midd.db 41601 +vcselab_misc_mnmn.db 929 +vcselab_misc_hsim_name.db 10673 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 1131676 +vcselab_misc_midd.db 41601 +vcselab_misc_mnmn.db 929 +vcselab_misc_hsim_name.db 10673 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 1129760 +vcselab_misc_midd.db 41601 +vcselab_misc_mnmn.db 929 +vcselab_misc_hsim_name.db 10673 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 1130016 +vcselab_misc_midd.db 41601 +vcselab_misc_mnmn.db 929 +vcselab_misc_hsim_name.db 10673 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 1129680 +vcselab_misc_midd.db 41601 +vcselab_misc_mnmn.db 929 +vcselab_misc_hsim_name.db 10673 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 1129868 +vcselab_misc_midd.db 41601 +vcselab_misc_mnmn.db 929 +vcselab_misc_hsim_name.db 10673 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 1129868 +vcselab_misc_midd.db 41601 +vcselab_misc_mnmn.db 929 +vcselab_misc_hsim_name.db 10673 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 1129868 +vcselab_misc_midd.db 41729 +vcselab_misc_mnmn.db 929 +vcselab_misc_hsim_name.db 10697 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 1130872 +vcselab_misc_midd.db 41729 +vcselab_misc_mnmn.db 929 +vcselab_misc_hsim_name.db 10697 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 1130872 +vcselab_misc_midd.db 41729 +vcselab_misc_mnmn.db 929 +vcselab_misc_hsim_name.db 10697 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 1131008 +vcselab_misc_midd.db 41729 +vcselab_misc_mnmn.db 929 +vcselab_misc_hsim_name.db 10697 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 1131028 +vcselab_misc_midd.db 41545 +vcselab_misc_mnmn.db 902 +vcselab_misc_hsim_name.db 10593 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 1128696 +vcselab_misc_midd.db 41545 +vcselab_misc_mnmn.db 902 +vcselab_misc_hsim_name.db 10593 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 1128696 +vcselab_misc_midd.db 41545 +vcselab_misc_mnmn.db 902 +vcselab_misc_hsim_name.db 10593 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 1128696 +vcselab_misc_midd.db 41545 +vcselab_misc_mnmn.db 902 +vcselab_misc_hsim_name.db 10593 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 1128696 +vcselab_misc_midd.db 41545 +vcselab_misc_mnmn.db 902 +vcselab_misc_hsim_name.db 10593 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 1128696 +vcselab_misc_midd.db 41589 +vcselab_misc_mnmn.db 921 +vcselab_misc_hsim_name.db 10813 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 1134400 +vcselab_misc_midd.db 41589 +vcselab_misc_mnmn.db 921 +vcselab_misc_hsim_name.db 10813 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 1134632 +vcselab_misc_midd.db 41669 +vcselab_misc_mnmn.db 921 +vcselab_misc_hsim_name.db 10813 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 1134728 +vcselab_misc_midd.db 41669 +vcselab_misc_mnmn.db 921 +vcselab_misc_hsim_name.db 10813 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 1134400 +vcselab_misc_midd.db 41505 +vcselab_misc_mnmn.db 902 +vcselab_misc_hsim_name.db 10585 +vcselab_master_hsim_virtintf_info.dat 160 +vcselab_misc_hsim_merge.db 1128352 diff --git a/tb/digital_top/simv.daidir/vcselab_misc_midd.db b/tb/digital_top/simv.daidir/vcselab_misc_midd.db new file mode 100644 index 0000000..6a6ae5c Binary files /dev/null and b/tb/digital_top/simv.daidir/vcselab_misc_midd.db differ diff --git a/tb/digital_top/simv.daidir/vcselab_misc_mnmn.db b/tb/digital_top/simv.daidir/vcselab_misc_mnmn.db new file mode 100644 index 0000000..d85cb27 Binary files /dev/null and b/tb/digital_top/simv.daidir/vcselab_misc_mnmn.db differ diff --git a/tb/digital_top/simv.daidir/vcselab_misc_partition.db b/tb/digital_top/simv.daidir/vcselab_misc_partition.db new file mode 100644 index 0000000..6fb3313 Binary files /dev/null and b/tb/digital_top/simv.daidir/vcselab_misc_partition.db differ diff --git a/tb/digital_top/simv.daidir/vcselab_misc_partitionDbg.db b/tb/digital_top/simv.daidir/vcselab_misc_partitionDbg.db new file mode 100644 index 0000000..8e89e0a Binary files /dev/null and b/tb/digital_top/simv.daidir/vcselab_misc_partitionDbg.db differ diff --git a/tb/digital_top/simv.daidir/vcselab_misc_tCEYNb b/tb/digital_top/simv.daidir/vcselab_misc_tCEYNb new file mode 100644 index 0000000..d3266cb Binary files /dev/null and b/tb/digital_top/simv.daidir/vcselab_misc_tCEYNb differ diff --git a/tb/digital_top/simv.daidir/vcselab_misc_vcselabref.db b/tb/digital_top/simv.daidir/vcselab_misc_vcselabref.db new file mode 100644 index 0000000..f76dd23 Binary files /dev/null and b/tb/digital_top/simv.daidir/vcselab_misc_vcselabref.db differ diff --git a/tb/digital_top/simv.daidir/vcselab_misc_vpdnodenums b/tb/digital_top/simv.daidir/vcselab_misc_vpdnodenums new file mode 100644 index 0000000..857020d Binary files /dev/null and b/tb/digital_top/simv.daidir/vcselab_misc_vpdnodenums differ diff --git a/tb/digital_top/spi_if.sv b/tb/digital_top/spi_if.sv new file mode 100644 index 0000000..d143592 --- /dev/null +++ b/tb/digital_top/spi_if.sv @@ -0,0 +1,17 @@ + + +interface spi_if(input clk,input rstn); + + //timeunit 1ns; + //timeprecision 1ps; + logic sclk; + logic csn; + logic mosi; + logic miso; + + + +endinterface : spi_if + + + diff --git a/tb/digital_top/thermo15_binary4.v b/tb/digital_top/thermo15_binary4.v new file mode 100644 index 0000000..86297d3 --- /dev/null +++ b/tb/digital_top/thermo15_binary4.v @@ -0,0 +1,30 @@ +module thermo15_binary4( + input [14:0] thermo_code + ,output reg [3 :0] binary_code + ); + +wire [3:0]sum; +assign sum=thermo_code[0]+thermo_code[1]+thermo_code[2]+thermo_code[3]+thermo_code[4]+thermo_code[5]+thermo_code[6]+thermo_code[7]+thermo_code[8]+thermo_code[9]+thermo_code[10]+thermo_code[11]+thermo_code[12]+thermo_code[13]+thermo_code[14]; + +always @(*) begin + +case(sum) + 4'd0 : binary_code<=4'b0000; + 4'd1 : binary_code<=4'b0001; + 4'd2 : binary_code<=4'b0010; + 4'd3 : binary_code<=4'b0011; + 4'd4 : binary_code<=4'b0100; + 4'd5 : binary_code<=4'b0101; + 4'd6 : binary_code<=4'b0110; + 4'd7 : binary_code<=4'b0111; + 4'd8 : binary_code<=4'b1000; + 4'd9 : binary_code<=4'b1001; + 4'd10: binary_code<=4'b1010; + 4'd11: binary_code<=4'b1011; + 4'd12: binary_code<=4'b1100; + 4'd13: binary_code<=4'b1101; + 4'd14: binary_code<=4'b1110; + 4'd15: binary_code<=4'b1111; +endcase +end +endmodule \ No newline at end of file diff --git a/tb/digital_top/thermo2binary_top.v b/tb/digital_top/thermo2binary_top.v new file mode 100644 index 0000000..776e27b --- /dev/null +++ b/tb/digital_top/thermo2binary_top.v @@ -0,0 +1,30 @@ + + + + + +module thermo2binary_top ( + + input [14:0] DEM_MSB_IN + ,input [6 :0] DEM_ISB_IN + ,input [8 :0] DEM_LSB_IN + + ,output [15:0] DOUT +); + +wire [3:0] temp_data15_12; +thermo15_binary4 U_thermo15_binary4 ( + .thermo_code ( DEM_MSB_IN ) + ,.binary_code ( temp_data15_12 ) + ); + +wire [2:0] temp_data11_9; +thermo7_binary3 thermo7_binary3 ( + .thermo_code ( DEM_ISB_IN ) + ,.binary_code ( temp_data11_9 ) + ); + + +assign DOUT = {temp_data15_12[3:0],temp_data11_9[2:0],DEM_LSB_IN[8:0]}; + +endmodule \ No newline at end of file diff --git a/tb/digital_top/thermo7_binary3.v b/tb/digital_top/thermo7_binary3.v new file mode 100644 index 0000000..ce1f1e4 --- /dev/null +++ b/tb/digital_top/thermo7_binary3.v @@ -0,0 +1,22 @@ +module thermo7_binary3( + input [6:0] thermo_code + ,output reg [2 :0] binary_code +); + +wire [2:0]sum; +assign sum=thermo_code[0]+thermo_code[1]+thermo_code[2]+thermo_code[3]+thermo_code[4]+thermo_code[5]+thermo_code[6]; + +always @(*) begin + +case(sum) + 3'd0 : binary_code<=3'b000; + 3'd1 : binary_code<=3'b001; + 3'd2 : binary_code<=3'b010; + 3'd3 : binary_code<=3'b011; + 3'd4 : binary_code<=3'b100; + 3'd5 : binary_code<=3'b101; + 3'd6 : binary_code<=3'b110; + 3'd7 : binary_code<=3'b111; +endcase +end +endmodule \ No newline at end of file diff --git a/tb/digital_top/ucli.key b/tb/digital_top/ucli.key new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/verdiLog/.74196IC_EDA.conf b/tb/digital_top/verdiLog/.74196IC_EDA.conf new file mode 100644 index 0000000..d755d45 --- /dev/null +++ b/tb/digital_top/verdiLog/.74196IC_EDA.conf @@ -0,0 +1,2261 @@ +[qBaseWindowStateGroup] +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\ProductVersion=201809 +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\Layout="@ByteArray(\0\0\0\xff\0\0\0\0\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x2\xf2\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x3P\0\0\0\x89\0\xff\xff\xff\xfa\0\0\0\x1\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\x2\xc7\0\0\x1\xa8\0\0\0k\0\0\0k\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\x1\0\0\x3V\0\0\x6\xaa\0\0\0k\0\xff\xff\xff\0\0\0\x3\0\0\n\0\0\0\x1\xd8\xfc\x1\0\0\0\x1\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\x1\0\0\0\0\0\0\n\0\0\0\0\xa0\0\xff\xff\xff\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x3\x16\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x3\x1e\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\x1f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x43\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3g\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\isNestedWindow=0 +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\size=@Size(2560 1337) +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\geometry_x=-1 +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\geometry_y=27 +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\geometry_width=2560 +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\geometry_height=1337 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=false +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=false +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=false +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=false +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\ProductVersion=201809 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\Layout="@ByteArray(\0\0\0\xff\0\0\0\0\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x4\xeb\xfc\x1\0\0\0\x4\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x33\0\0\0\0\0\0\0\n\0\0\0\0\x80\0\xff\xff\xff\xfc\0\0\0\0\0\0\x2\\\0\0\0\0\0\xff\xff\xff\xfa\xff\xff\xff\xff\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfc\0\0\x2\x62\0\0\0\xb7\0\0\0\0\0\xff\xff\xff\xfa\xff\xff\xff\xff\x1\0\0\0\x2\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\0\0k\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0h\0\x65\0r\0i\0t\0\x61\0n\0\x63\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xae\0\xff\xff\xff\xfc\0\0\x3\x1f\0\0\x6\xe1\0\0\0\0\0\xff\xff\xff\xfa\0\0\0\x5\x1\0\0\0\b\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\0\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x34\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x35\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x36\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x37\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x32\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x38\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x39\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\0\0\0\x3\0\0\n\0\0\0\x4\xeb\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\n\0\0\0\0\0\0\xff\xff\xff\xfa\0\0\0\x2\x1\0\0\0\x3\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\0\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x33\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x34\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\isNestedWindow=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\size=@Size(2560 1337) +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\geometry_x=-1 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\geometry_y=27 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\geometry_width=2560 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\geometry_height=1337 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_OneSearch\isNestedWindow=1 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_OneSearch\isVisible=false +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_OneSearch\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nWave_2\isNestedWindow=1 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nWave_2\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nWave_2\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nWave_2\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nWave_2\dockIsFloating=false +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qDockerWindow_qDockContentType\Verdi=1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qDockerWindow_qDockContentType\hdlHier=1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qDockerWindow_qDockContentType\hdlSrc=1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qDockerWindow_qDockContentType\messageWindow=1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qDockerWindow_qDockContentType\svtbHier=1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qDockerWindow_qDockContentType\OneSearch=1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qDockerWindowMgr_saveDockerChildList\Verdi_1=7 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qDockerWindowMgr_saveDockerChildList\Verdi_1_0=widgetDock_hdlHier_1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qDockerWindowMgr_saveDockerChildList\Verdi_1_1=widgetDock_messageWindow_1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qDockerWindowMgr_saveDockerChildList\Verdi_1_2=widgetDock_hdlSrc_1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qDockerWindowMgr_saveDockerChildList\Verdi_1_3=widgetDock_signalList_1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qDockerWindowMgr_saveDockerChildList\Verdi_1_4=widgetDock_svtbHier_1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qDockerWindowMgr_saveDockerChildList\Verdi_1_5=windowDock_OneSearch_1 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\widgetDock_hdlHier_1\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\widgetDock_hdlHier_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\widgetDock_hdlHier_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\widgetDock_hdlHier_1\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\widgetDock_messageWindow_1\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\widgetDock_messageWindow_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\widgetDock_messageWindow_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\widgetDock_messageWindow_1\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\widgetDock_hdlSrc_1\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\widgetDock_hdlSrc_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\widgetDock_hdlSrc_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\widgetDock_hdlSrc_1\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\widgetDock_signalList_1\isVisible=false +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\widgetDock_svtbHier_1\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\widgetDock_svtbHier_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\widgetDock_svtbHier_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\widgetDock_svtbHier_1\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\windowDock_OneSearch_1\isNestedWindow=1 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\windowDock_OneSearch_1\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\windowDock_OneSearch_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\windowDock_OneSearch_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\windowDock_OneSearch_1\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\windowDock_nWave_1\isNestedWindow=1 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\windowDock_nWave_1\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\windowDock_nWave_1\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\windowDock_nWave_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\windowDock_nWave_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\windowDock_nWave_1\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\ProductVersion=201809 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\Layout="@ByteArray(\0\0\0\xff\0\0\0\0\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x2\xcb\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x2\x8d\0\0\0\x89\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x2\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0h\0\x64\0l\0H\0i\0\x65\0r\0_\0\x31\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0*\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0s\0v\0t\0\x62\0H\0i\0\x65\0r\0_\0\x31\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0s\0i\0g\0n\0\x61\0l\0L\0i\0s\0t\0_\0\x31\0\0\0\0\xe9\0\0\0\xc6\0\0\0k\0\0\0k\xfb\0\0\0&\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0h\0\x64\0l\0S\0r\0\x63\0_\0\x31\x1\0\0\x2\x93\0\0\am\0\0\0k\0\xff\xff\xff\0\0\0\x3\0\0\n\0\0\0\x2\x1a\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\n\0\0\0\x2,\0\xff\xff\xff\xfa\0\0\0\x2\x1\0\0\0\x3\xfb\0\0\0\x34\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0m\0\x65\0s\0s\0\x61\0g\0\x65\0W\0i\0n\0\x64\0o\0w\0_\0\x31\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0,\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\0_\0\x31\x1\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x31\x1\0\0\0\0\xff\xff\xff\xff\0\0\x1-\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x33\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x34\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\isNestedWindow=0 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\size=@Size(2560 1337) +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\geometry_x=-1 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\geometry_y=27 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\geometry_width=2560 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\geometry_height=1337 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nWave_2\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nMemory_3\isNestedWindow=1 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nMemory_3\isVisible=false +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nMemory_3\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nMemory_3\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nMemory_3\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nMemory_4\isNestedWindow=1 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nMemory_4\isVisible=false +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nMemory_4\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nMemory_4\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nMemory_4\dockIsFloating=false +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qDockerWindow_qDockContentType\nWave=1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qDockerWindowMgr_saveDockerChildList\Verdi_1_6=windowDock_nWave_1 +Verdi_1\qBaseWindowNextStateGroup\0\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\0\ProductVersion=201809 +Verdi_1\qBaseWindowNextStateGroup\0\Layout="@ByteArray(\0\0\0\xff\0\0\0\x1e\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x3\xb3\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x2\\\0\0\0\0\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfc\0\0\x2\x62\0\0\0\xb7\0\0\0\0\0\xff\xff\xff\xfa\0\0\0\x1\x1\0\0\0\x2\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\0\0k\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0h\0\x65\0r\0i\0t\0\x61\0n\0\x63\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xae\0\xff\xff\xff\xfc\0\0\x3\x1f\0\0\x6\xe1\0\0\0\0\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\b\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\0\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x34\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x35\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x36\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x37\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x32\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x38\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x39\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\0\0\0\x3\0\0\n\0\0\0\x1\x32\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\n\0\0\0\x1[\0\xff\xff\xff\xfa\0\0\0\x3\x1\0\0\0\x4\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\0\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x33\x1\0\0\0\0\xff\xff\xff\xff\0\0\x1[\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x33\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x34\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowNextStateGroup\0\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\0\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\0\size=@Size(2560 1337) +Verdi_1\qBaseWindowNextStateGroup\0\geometry_x=-1 +Verdi_1\qBaseWindowNextStateGroup\0\geometry_y=27 +Verdi_1\qBaseWindowNextStateGroup\0\geometry_width=2560 +Verdi_1\qBaseWindowNextStateGroup\0\geometry_height=1337 +Verdi_1\qBaseWindowNextStateGroup\1\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_OneSearch\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_OneSearch\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_OneSearch\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\1\ProductVersion=201809 +Verdi_1\qBaseWindowNextStateGroup\1\Layout="@ByteArray(\0\0\0\xff\0\0\0\x1f\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x3\xb3\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x2\\\0\0\0\x89\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfc\0\0\x2\x62\0\0\0\xb7\0\0\0\xae\0\xff\xff\xff\xfa\0\0\0\x1\x1\0\0\0\x2\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\0\0k\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0h\0\x65\0r\0i\0t\0\x61\0n\0\x63\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xae\0\xff\xff\xff\xfc\0\0\x3\x1f\0\0\x6\xe1\0\0\0\xbf\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\b\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\x1\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x34\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x35\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x36\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x37\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x32\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x38\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x39\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\0\0\0\x3\0\0\n\0\0\0\x1\x32\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\n\0\0\0\x2,\0\xff\xff\xff\xfa\0\0\0\x3\x1\0\0\0\x4\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\x1\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x33\x1\0\0\0\0\xff\xff\xff\xff\0\0\x1[\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x33\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x34\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowNextStateGroup\1\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\1\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\1\size=@Size(2560 1337) +Verdi_1\qBaseWindowNextStateGroup\1\geometry_x=-1 +Verdi_1\qBaseWindowNextStateGroup\1\geometry_y=27 +Verdi_1\qBaseWindowNextStateGroup\1\geometry_width=2560 +Verdi_1\qBaseWindowNextStateGroup\1\geometry_height=1337 +Verdi_1\qBaseWindowNextStateGroup\2\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\windowDock_OneSearch\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\windowDock_OneSearch\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\2\ProductVersion=201809 +Verdi_1\qBaseWindowNextStateGroup\2\Layout="@ByteArray(\0\0\0\xff\0\0\0 \xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x3\xb3\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x2\\\0\0\0\0\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfc\0\0\x2\x62\0\0\0\xb7\0\0\0\0\0\xff\xff\xff\xfa\0\0\0\x1\x1\0\0\0\x2\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\0\0k\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0h\0\x65\0r\0i\0t\0\x61\0n\0\x63\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xae\0\xff\xff\xff\xfc\0\0\x3\x1f\0\0\x6\xe1\0\0\0\0\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\b\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\0\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x34\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x35\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x36\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x37\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x32\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x38\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x39\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\0\0\0\x3\0\0\n\0\0\0\x1\x32\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\n\0\0\0\x1[\0\xff\xff\xff\xfa\0\0\0\x3\x1\0\0\0\x4\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\0\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x33\x1\0\0\0\0\xff\xff\xff\xff\0\0\x1[\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x33\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x34\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowNextStateGroup\2\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\2\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\2\size=@Size(2560 1337) +Verdi_1\qBaseWindowNextStateGroup\2\geometry_x=-1 +Verdi_1\qBaseWindowNextStateGroup\2\geometry_y=27 +Verdi_1\qBaseWindowNextStateGroup\2\geometry_width=2560 +Verdi_1\qBaseWindowNextStateGroup\2\geometry_height=1337 +Verdi_1\qBaseWindowNextStateGroup\3\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeMax=1 +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\windowDock_OneSearch\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\windowDock_OneSearch\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\windowDock_OneSearch\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\3\ProductVersion=201809 +Verdi_1\qBaseWindowNextStateGroup\3\Layout="@ByteArray(\0\0\0\xff\0\0\0!\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x3\xb3\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x2\\\0\0\0\0\0\xff\xff\xff\xfa\xff\xff\xff\xff\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfc\0\0\x2\x62\0\0\0\xb7\0\0\0\0\0\xff\xff\xff\xfa\xff\xff\xff\xff\x1\0\0\0\x2\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\0\0k\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0h\0\x65\0r\0i\0t\0\x61\0n\0\x63\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xae\0\xff\xff\xff\xfc\0\0\x3\x1f\0\0\x6\xe1\0\0\0\0\0\xff\xff\xff\xfa\0\0\0\x5\x1\0\0\0\b\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\0\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x34\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x35\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x36\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x37\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x32\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x38\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x39\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\0\0\0\x3\0\0\n\0\0\0\x4\xeb\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\n\0\0\0\x1[\0\xff\xff\xff\xfa\0\0\0\x3\x1\0\0\0\x4\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\0\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x33\x1\0\0\0\0\xff\xff\xff\xff\0\0\x1[\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x33\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x34\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowNextStateGroup\3\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\3\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\3\size=@Size(2560 1337) +Verdi_1\qBaseWindowNextStateGroup\3\geometry_x=-1 +Verdi_1\qBaseWindowNextStateGroup\3\geometry_y=27 +Verdi_1\qBaseWindowNextStateGroup\3\geometry_width=2560 +Verdi_1\qBaseWindowNextStateGroup\3\geometry_height=1337 +Verdi_1\qBaseWindowNextStateGroup\4\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeMax=1 +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\windowDock_OneSearch\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\windowDock_OneSearch\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\windowDock_OneSearch\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\4\ProductVersion=201809 +Verdi_1\qBaseWindowNextStateGroup\4\Layout="@ByteArray(\0\0\0\xff\0\0\0\"\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x3\xb3\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x2\\\0\0\0\0\0\xff\xff\xff\xfa\xff\xff\xff\xff\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfc\0\0\x2\x62\0\0\0\xb7\0\0\0\0\0\xff\xff\xff\xfa\xff\xff\xff\xff\x1\0\0\0\x2\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\0\0k\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0h\0\x65\0r\0i\0t\0\x61\0n\0\x63\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xae\0\xff\xff\xff\xfc\0\0\x3\x1f\0\0\x6\xe1\0\0\0\0\0\xff\xff\xff\xfa\0\0\0\x4\x1\0\0\0\a\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x34\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x35\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x36\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x37\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x32\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x38\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x39\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\0\0\0\x3\0\0\n\0\0\0\x4\xeb\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\n\0\0\0\x1[\0\xff\xff\xff\xfa\0\0\0\x3\x1\0\0\0\x5\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\0\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x33\x1\0\0\0\0\xff\xff\xff\xff\0\0\x1[\0\xff\xff\xff\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\0\0\0\0\0\xff\xff\xff\xff\0\0\x6\xe1\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x33\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x34\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowNextStateGroup\4\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\4\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\4\size=@Size(2560 1337) +Verdi_1\qBaseWindowNextStateGroup\4\geometry_x=-1 +Verdi_1\qBaseWindowNextStateGroup\4\geometry_y=27 +Verdi_1\qBaseWindowNextStateGroup\4\geometry_width=2560 +Verdi_1\qBaseWindowNextStateGroup\4\geometry_height=1337 +Verdi_1\qBaseWindowNextStateGroup\5\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_OneSearch\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_OneSearch\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_OneSearch\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nWave_2\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nWave_2\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nWave_2\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nWave_2\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nWave_2\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\5\ProductVersion=201809 +Verdi_1\qBaseWindowNextStateGroup\5\Layout="@ByteArray(\0\0\0\xff\0\0\0#\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x3\xb3\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x2\\\0\0\0\x89\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfc\0\0\x2\x62\0\0\0\xb7\0\0\0\xae\0\xff\xff\xff\xfa\0\0\0\x1\x1\0\0\0\x2\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\0\0k\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0h\0\x65\0r\0i\0t\0\x61\0n\0\x63\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xae\0\xff\xff\xff\xfc\0\0\x3\x1f\0\0\x6\xe1\0\0\0\xbf\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\b\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\x1\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x34\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x35\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x36\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x37\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x32\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x38\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x39\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\0\0\0\x3\0\0\n\0\0\0\x1\x32\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\n\0\0\0\x2,\0\xff\xff\xff\xfa\0\0\0\x3\x1\0\0\0\x4\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\x1\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x33\x1\0\0\0\0\xff\xff\xff\xff\0\0\x1[\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x33\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x34\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowNextStateGroup\5\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\5\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\5\size=@Size(2560 1337) +Verdi_1\qBaseWindowNextStateGroup\5\geometry_x=-1 +Verdi_1\qBaseWindowNextStateGroup\5\geometry_y=27 +Verdi_1\qBaseWindowNextStateGroup\5\geometry_width=2560 +Verdi_1\qBaseWindowNextStateGroup\5\geometry_height=1337 +Verdi_1\qBaseWindowNextStateGroup\6\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\windowDock_OneSearch\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\windowDock_OneSearch\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\windowDock_nWave_2\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\windowDock_nWave_2\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\windowDock_nWave_2\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\windowDock_nWave_2\qBaseWindowBeMax=1 +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\windowDock_nWave_2\qBaseWindowBeFix=1 +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\windowDock_nWave_2\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\6\ProductVersion=201809 +Verdi_1\qBaseWindowNextStateGroup\6\Layout="@ByteArray(\0\0\0\xff\0\0\0$\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x3\xb3\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x2\\\0\0\0\0\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfc\0\0\x2\x62\0\0\0\xb7\0\0\0\0\0\xff\xff\xff\xfa\0\0\0\x1\x1\0\0\0\x2\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\0\0k\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0h\0\x65\0r\0i\0t\0\x61\0n\0\x63\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xae\0\xff\xff\xff\xfc\0\0\x3\x1f\0\0\x6\xe1\0\0\0\0\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\b\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\0\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x34\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x35\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x36\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x37\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x32\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x38\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x39\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\0\0\0\x3\0\0\n\0\0\0\x1\x32\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\n\0\0\0\x1[\0\xff\xff\xff\xfa\0\0\0\x3\x1\0\0\0\x4\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\0\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x33\x1\0\0\0\0\xff\xff\xff\xff\0\0\x1[\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x33\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x34\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowNextStateGroup\6\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\6\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\6\size=@Size(2560 1337) +Verdi_1\qBaseWindowNextStateGroup\6\geometry_x=-1 +Verdi_1\qBaseWindowNextStateGroup\6\geometry_y=27 +Verdi_1\qBaseWindowNextStateGroup\6\geometry_width=2560 +Verdi_1\qBaseWindowNextStateGroup\6\geometry_height=1337 +Verdi_1\qBaseWindowNextStateGroup\7\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_OneSearch\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_OneSearch\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_OneSearch\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\7\ProductVersion=201809 +Verdi_1\qBaseWindowNextStateGroup\7\Layout="@ByteArray(\0\0\0\xff\0\0\0%\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x3\xb3\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x2\\\0\0\0\x89\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfc\0\0\x2\x62\0\0\0\xb7\0\0\0\xae\0\xff\xff\xff\xfa\0\0\0\x1\x1\0\0\0\x2\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\0\0k\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0h\0\x65\0r\0i\0t\0\x61\0n\0\x63\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xae\0\xff\xff\xff\xfc\0\0\x3\x1f\0\0\x6\xe1\0\0\0\xbf\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\b\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\x1\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x34\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x35\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x36\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x37\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x32\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x38\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x39\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\0\0\0\x3\0\0\n\0\0\0\x1\x32\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\n\0\0\0\x2,\0\xff\xff\xff\xfa\0\0\0\x3\x1\0\0\0\x4\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\x1\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x33\x1\0\0\0\0\xff\xff\xff\xff\0\0\x1[\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x33\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x34\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowNextStateGroup\7\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\7\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\7\size=@Size(2560 1337) +Verdi_1\qBaseWindowNextStateGroup\7\geometry_x=-1 +Verdi_1\qBaseWindowNextStateGroup\7\geometry_y=27 +Verdi_1\qBaseWindowNextStateGroup\7\geometry_width=2560 +Verdi_1\qBaseWindowNextStateGroup\7\geometry_height=1337 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nWave_3\isNestedWindow=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nWave_3\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nWave_3\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\8\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\windowDock_OneSearch\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\windowDock_OneSearch\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\windowDock_OneSearch\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\windowDock_nWave_3\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\windowDock_nWave_3\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeMax=1 +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeFix=1 +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\windowDock_nWave_3\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\8\ProductVersion=201809 +Verdi_1\qBaseWindowNextStateGroup\8\Layout="@ByteArray(\0\0\0\xff\0\0\0&\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x3\xb3\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x2\\\0\0\0\0\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfc\0\0\x2\x62\0\0\0\xb7\0\0\0\0\0\xff\xff\xff\xfa\0\0\0\x1\x1\0\0\0\x2\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\0\0k\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0h\0\x65\0r\0i\0t\0\x61\0n\0\x63\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xae\0\xff\xff\xff\xfc\0\0\x3\x1f\0\0\x6\xe1\0\0\0\0\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\b\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\0\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x34\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x35\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x36\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x37\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x32\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x38\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x39\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\0\0\0\x3\0\0\n\0\0\0\x1\x32\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\n\0\0\0\x1[\0\xff\xff\xff\xfa\0\0\0\x3\x1\0\0\0\x4\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\0\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x33\x1\0\0\0\0\xff\xff\xff\xff\0\0\x1[\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x33\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x34\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowNextStateGroup\8\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\8\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\8\size=@Size(2560 1337) +Verdi_1\qBaseWindowNextStateGroup\8\geometry_x=-1 +Verdi_1\qBaseWindowNextStateGroup\8\geometry_y=27 +Verdi_1\qBaseWindowNextStateGroup\8\geometry_width=2560 +Verdi_1\qBaseWindowNextStateGroup\8\geometry_height=1337 +Verdi_1\qBaseWindowNextStateGroup\9\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\windowDock_OneSearch\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\windowDock_OneSearch\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\windowDock_nWave_3\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\windowDock_nWave_3\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\windowDock_nWave_3\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeMax=1 +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeFix=1 +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\windowDock_nWave_3\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\9\ProductVersion=201809 +Verdi_1\qBaseWindowNextStateGroup\9\Layout="@ByteArray(\0\0\0\xff\0\0\0'\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x3\xb3\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x2\\\0\0\0\0\0\xff\xff\xff\xfa\xff\xff\xff\xff\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfc\0\0\x2\x62\0\0\0\xb7\0\0\0\0\0\xff\xff\xff\xfa\xff\xff\xff\xff\x1\0\0\0\x2\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\0\0k\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0h\0\x65\0r\0i\0t\0\x61\0n\0\x63\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xae\0\xff\xff\xff\xfc\0\0\x3\x1f\0\0\x6\xe1\0\0\0\0\0\xff\xff\xff\xfa\0\0\0\x5\x1\0\0\0\b\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\0\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x34\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x35\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x36\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x37\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x32\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x38\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x39\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\0\0\0\x3\0\0\n\0\0\0\x4\xeb\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\n\0\0\0\x1[\0\xff\xff\xff\xfa\0\0\0\x3\x1\0\0\0\x4\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\0\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x33\x1\0\0\0\0\xff\xff\xff\xff\0\0\x1[\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x33\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x34\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowNextStateGroup\9\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\9\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\9\size=@Size(2560 1337) +Verdi_1\qBaseWindowNextStateGroup\9\geometry_x=-1 +Verdi_1\qBaseWindowNextStateGroup\9\geometry_y=27 +Verdi_1\qBaseWindowNextStateGroup\9\geometry_width=2560 +Verdi_1\qBaseWindowNextStateGroup\9\geometry_height=1337 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nWave_3\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\10\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeMax=1 +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\windowDock_OneSearch\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\windowDock_OneSearch\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\windowDock_OneSearch\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\windowDock_nWave_3\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\windowDock_nWave_3\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\windowDock_nWave_3\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeMax=1 +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeFix=1 +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\windowDock_nWave_3\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\10\ProductVersion=201809 +Verdi_1\qBaseWindowNextStateGroup\10\Layout="@ByteArray(\0\0\0\xff\0\0\0(\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x3\xb3\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x2\\\0\0\0\0\0\xff\xff\xff\xfa\xff\xff\xff\xff\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfc\0\0\x2\x62\0\0\0\xb7\0\0\0\0\0\xff\xff\xff\xfa\xff\xff\xff\xff\x1\0\0\0\x2\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\0\0k\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0h\0\x65\0r\0i\0t\0\x61\0n\0\x63\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xae\0\xff\xff\xff\xfc\0\0\x3\x1f\0\0\x6\xe1\0\0\0\0\0\xff\xff\xff\xfa\0\0\0\x4\x1\0\0\0\a\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x34\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x35\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x36\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x37\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x32\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x38\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x39\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\0\0\0\x3\0\0\n\0\0\0\x4\xeb\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\n\0\0\0\x1[\0\xff\xff\xff\xfa\0\0\0\x3\x1\0\0\0\x5\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\0\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x33\x1\0\0\0\0\xff\xff\xff\xff\0\0\x1[\0\xff\xff\xff\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\0\0\0\0\0\xff\xff\xff\xff\0\0\x6\xe1\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x33\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x34\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowNextStateGroup\10\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\10\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\10\size=@Size(2560 1337) +Verdi_1\qBaseWindowNextStateGroup\10\geometry_x=-1 +Verdi_1\qBaseWindowNextStateGroup\10\geometry_y=27 +Verdi_1\qBaseWindowNextStateGroup\10\geometry_width=2560 +Verdi_1\qBaseWindowNextStateGroup\10\geometry_height=1337 +Verdi_1\qBaseWindowNextStateGroup\11\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_OneSearch\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_OneSearch\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_nWave_3\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_nWave_3\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_nWave_3\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_nWave_3\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\11\ProductVersion=201809 +Verdi_1\qBaseWindowNextStateGroup\11\Layout="@ByteArray(\0\0\0\xff\0\0\0)\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x3\xb3\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x2\\\0\0\0\x89\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfc\0\0\x2\x62\0\0\0\xb7\0\0\0\xae\0\xff\xff\xff\xfa\0\0\0\x1\x1\0\0\0\x2\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\0\0k\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0h\0\x65\0r\0i\0t\0\x61\0n\0\x63\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xae\0\xff\xff\xff\xfc\0\0\x3\x1f\0\0\x6\xe1\0\0\0\xbf\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\b\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\x1\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x34\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x35\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x36\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x37\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x32\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x38\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x39\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\0\0\0\x3\0\0\n\0\0\0\x1\x32\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\n\0\0\0\x2,\0\xff\xff\xff\xfa\0\0\0\x3\x1\0\0\0\x4\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\x1\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x33\x1\0\0\0\0\xff\xff\xff\xff\0\0\x1[\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x33\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x34\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowNextStateGroup\11\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\11\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\11\size=@Size(2560 1337) +Verdi_1\qBaseWindowNextStateGroup\11\geometry_x=-1 +Verdi_1\qBaseWindowNextStateGroup\11\geometry_y=27 +Verdi_1\qBaseWindowNextStateGroup\11\geometry_width=2560 +Verdi_1\qBaseWindowNextStateGroup\11\geometry_height=1337 +Verdi_1\qBaseWindowNextStateGroup\12\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\windowDock_OneSearch\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\windowDock_OneSearch\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\windowDock_OneSearch\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\windowDock_nWave_3\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\windowDock_nWave_3\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\windowDock_nWave_3\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeMax=1 +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeFix=1 +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\windowDock_nWave_3\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\12\ProductVersion=201809 +Verdi_1\qBaseWindowNextStateGroup\12\Layout="@ByteArray(\0\0\0\xff\0\0\0*\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x3\xb3\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x2\\\0\0\0\0\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfc\0\0\x2\x62\0\0\0\xb7\0\0\0\0\0\xff\xff\xff\xfa\0\0\0\x1\x1\0\0\0\x2\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\0\0k\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0h\0\x65\0r\0i\0t\0\x61\0n\0\x63\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xae\0\xff\xff\xff\xfc\0\0\x3\x1f\0\0\x6\xe1\0\0\0\0\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\b\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\0\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x34\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x35\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x36\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x37\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x32\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x38\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x39\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\0\0\0\x3\0\0\n\0\0\0\x1\x32\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\n\0\0\0\x1[\0\xff\xff\xff\xfa\0\0\0\x3\x1\0\0\0\x4\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\0\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x33\x1\0\0\0\0\xff\xff\xff\xff\0\0\x1[\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x33\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x34\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowNextStateGroup\12\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\12\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\12\size=@Size(2560 1337) +Verdi_1\qBaseWindowNextStateGroup\12\geometry_x=-1 +Verdi_1\qBaseWindowNextStateGroup\12\geometry_y=27 +Verdi_1\qBaseWindowNextStateGroup\12\geometry_width=2560 +Verdi_1\qBaseWindowNextStateGroup\12\geometry_height=1337 +Verdi_1\qBaseWindowNextStateGroup\13\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_OneSearch\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_OneSearch\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_nWave_3\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_nWave_3\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_nWave_3\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_nWave_3\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\13\ProductVersion=201809 +Verdi_1\qBaseWindowNextStateGroup\13\Layout="@ByteArray(\0\0\0\xff\0\0\0+\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x3\xb3\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x2\\\0\0\0\x89\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfc\0\0\x2\x62\0\0\0\xb7\0\0\0\xae\0\xff\xff\xff\xfa\0\0\0\x1\x1\0\0\0\x2\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\0\0k\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0h\0\x65\0r\0i\0t\0\x61\0n\0\x63\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xae\0\xff\xff\xff\xfc\0\0\x3\x1f\0\0\x6\xe1\0\0\0\xbf\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\b\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\x1\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x34\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x35\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x36\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x37\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x32\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x38\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x39\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\0\0\0\x3\0\0\n\0\0\0\x1\x32\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\n\0\0\0\x2,\0\xff\xff\xff\xfa\0\0\0\x3\x1\0\0\0\x4\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\x1\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x33\x1\0\0\0\0\xff\xff\xff\xff\0\0\x1[\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x33\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x34\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowNextStateGroup\13\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\13\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\13\size=@Size(2560 1337) +Verdi_1\qBaseWindowNextStateGroup\13\geometry_x=-1 +Verdi_1\qBaseWindowNextStateGroup\13\geometry_y=27 +Verdi_1\qBaseWindowNextStateGroup\13\geometry_width=2560 +Verdi_1\qBaseWindowNextStateGroup\13\geometry_height=1337 +Verdi_1\qBaseWindowNextStateGroup\14\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowNextStateGroup\14\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\14\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\14\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\14\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\14\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\14\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\14\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\14\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\14\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\14\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\14\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\14\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\14\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\14\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\14\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\14\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\14\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\14\qBaseDockWidgetGroup\windowDock_OneSearch\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\14\qBaseDockWidgetGroup\windowDock_OneSearch\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\14\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\14\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\14\qBaseDockWidgetGroup\windowDock_OneSearch\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\14\qBaseDockWidgetGroup\windowDock_nWave_3\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\14\qBaseDockWidgetGroup\windowDock_nWave_3\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\14\qBaseDockWidgetGroup\windowDock_nWave_3\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\14\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeMax=1 +Verdi_1\qBaseWindowNextStateGroup\14\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeFix=1 +Verdi_1\qBaseWindowNextStateGroup\14\qBaseDockWidgetGroup\windowDock_nWave_3\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\14\ProductVersion=201809 +Verdi_1\qBaseWindowNextStateGroup\14\Layout="@ByteArray(\0\0\0\xff\0\0\0,\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x3\xb3\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x2\\\0\0\0\0\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfc\0\0\x2\x62\0\0\0\xb7\0\0\0\0\0\xff\xff\xff\xfa\0\0\0\x1\x1\0\0\0\x2\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\0\0k\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0h\0\x65\0r\0i\0t\0\x61\0n\0\x63\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xae\0\xff\xff\xff\xfc\0\0\x3\x1f\0\0\x6\xe1\0\0\0\0\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\b\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\0\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x34\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x35\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x36\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x37\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x32\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x38\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x39\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\0\0\0\x3\0\0\n\0\0\0\x1\x32\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\n\0\0\0\x1[\0\xff\xff\xff\xfa\0\0\0\x3\x1\0\0\0\x4\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\0\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x33\x1\0\0\0\0\xff\xff\xff\xff\0\0\x1[\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x33\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x34\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowNextStateGroup\14\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\14\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\14\size=@Size(2560 1337) +Verdi_1\qBaseWindowNextStateGroup\14\geometry_x=-1 +Verdi_1\qBaseWindowNextStateGroup\14\geometry_y=27 +Verdi_1\qBaseWindowNextStateGroup\14\geometry_width=2560 +Verdi_1\qBaseWindowNextStateGroup\14\geometry_height=1337 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_4\isNestedWindow=1 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_4\isVisible=false +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_4\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_4\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_4\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_4\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_4\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\15\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowNextStateGroup\15\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\15\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\15\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\15\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\15\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\15\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\15\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\15\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\15\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\15\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\15\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\15\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\15\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\15\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\15\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\15\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\15\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\15\qBaseDockWidgetGroup\windowDock_OneSearch\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\15\qBaseDockWidgetGroup\windowDock_OneSearch\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\15\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\15\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\15\qBaseDockWidgetGroup\windowDock_OneSearch\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\15\qBaseDockWidgetGroup\windowDock_nWave_3\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\15\qBaseDockWidgetGroup\windowDock_nWave_3\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\15\qBaseDockWidgetGroup\windowDock_nWave_3\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\15\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\15\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\15\qBaseDockWidgetGroup\windowDock_nWave_3\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\15\qBaseDockWidgetGroup\windowDock_nSchema_4\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\15\qBaseDockWidgetGroup\windowDock_nSchema_4\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\15\qBaseDockWidgetGroup\windowDock_nSchema_4\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\15\qBaseDockWidgetGroup\windowDock_nSchema_4\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\15\qBaseDockWidgetGroup\windowDock_nSchema_4\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\15\qBaseDockWidgetGroup\windowDock_nSchema_4\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\15\qBaseDockWidgetGroup\windowDock_nSchema_4\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\15\ProductVersion=201809 +Verdi_1\qBaseWindowNextStateGroup\15\Layout="@ByteArray(\0\0\0\xff\0\0\0-\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x4\xeb\xfc\x1\0\0\0\x4\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x33\x2\xff\xff\xff\x8a\0\0\0v\0\0\n\0\0\0\x4\xec\xfc\0\0\0\0\0\0\x2\\\0\0\0\0\0\xff\xff\xff\xfa\xff\xff\xff\xff\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfc\0\0\x2\x62\0\0\0\xb7\0\0\0\0\0\xff\xff\xff\xfa\xff\xff\xff\xff\x1\0\0\0\x2\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\0\0k\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0h\0\x65\0r\0i\0t\0\x61\0n\0\x63\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xae\0\xff\xff\xff\xfc\0\0\x3\x1f\0\0\x6\xe1\0\0\0\0\0\xff\xff\xff\xfa\0\0\0\x5\x1\0\0\0\b\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\0\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x34\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x35\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x36\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x37\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x32\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x38\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x39\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\0\0\0\x3\0\0\n\0\0\0\x4\xeb\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\n\0\0\0\0\0\0\xff\xff\xff\xfa\0\0\0\x2\x1\0\0\0\x3\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\0\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x33\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x34\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowNextStateGroup\15\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\15\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\15\size=@Size(2560 1337) +Verdi_1\qBaseWindowNextStateGroup\15\geometry_x=-1 +Verdi_1\qBaseWindowNextStateGroup\15\geometry_y=27 +Verdi_1\qBaseWindowNextStateGroup\15\geometry_width=2560 +Verdi_1\qBaseWindowNextStateGroup\15\geometry_height=1337 +Verdi_1\qBaseWindowNextStateGroup\16\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowNextStateGroup\16\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\16\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\16\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\16\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\16\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\16\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\16\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\16\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\16\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\16\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\16\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\16\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\16\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\16\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\16\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\16\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\16\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\16\qBaseDockWidgetGroup\windowDock_OneSearch\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\16\qBaseDockWidgetGroup\windowDock_OneSearch\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\16\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\16\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\16\qBaseDockWidgetGroup\windowDock_OneSearch\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\16\qBaseDockWidgetGroup\windowDock_nWave_3\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\16\qBaseDockWidgetGroup\windowDock_nWave_3\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\16\qBaseDockWidgetGroup\windowDock_nWave_3\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\16\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\16\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\16\qBaseDockWidgetGroup\windowDock_nWave_3\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\16\qBaseDockWidgetGroup\windowDock_nSchema_4\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\16\qBaseDockWidgetGroup\windowDock_nSchema_4\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\16\qBaseDockWidgetGroup\windowDock_nSchema_4\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\16\qBaseDockWidgetGroup\windowDock_nSchema_4\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\16\qBaseDockWidgetGroup\windowDock_nSchema_4\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\16\qBaseDockWidgetGroup\windowDock_nSchema_4\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\16\qBaseDockWidgetGroup\windowDock_nSchema_4\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\16\ProductVersion=201809 +Verdi_1\qBaseWindowNextStateGroup\16\Layout="@ByteArray(\0\0\0\xff\0\0\0.\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x4\xeb\xfc\x1\0\0\0\x4\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x33\0\0\0\0\0\0\0\n\0\0\0\0\x80\0\xff\xff\xff\xfc\0\0\0\0\0\0\x2\\\0\0\0\0\0\xff\xff\xff\xfa\xff\xff\xff\xff\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfc\0\0\x2\x62\0\0\0\xb7\0\0\0\0\0\xff\xff\xff\xfa\xff\xff\xff\xff\x1\0\0\0\x2\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\0\0k\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0h\0\x65\0r\0i\0t\0\x61\0n\0\x63\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xae\0\xff\xff\xff\xfc\0\0\x3\x1f\0\0\x6\xe1\0\0\0\0\0\xff\xff\xff\xfa\0\0\0\x5\x1\0\0\0\b\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\0\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x34\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x35\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x36\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x37\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x32\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x38\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x39\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\0\0\0\x3\0\0\n\0\0\0\x4\xeb\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\n\0\0\0\0\0\0\xff\xff\xff\xfa\0\0\0\x2\x1\0\0\0\x3\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\0\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x33\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x34\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowNextStateGroup\16\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\16\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\16\size=@Size(2560 1337) +Verdi_1\qBaseWindowNextStateGroup\16\geometry_x=-1 +Verdi_1\qBaseWindowNextStateGroup\16\geometry_y=27 +Verdi_1\qBaseWindowNextStateGroup\16\geometry_width=2560 +Verdi_1\qBaseWindowNextStateGroup\16\geometry_height=1337 +Verdi_1\qBaseWindowNextStateGroup\17\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowNextStateGroup\17\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\17\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\17\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\17\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\17\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\17\qBaseDockWidgetGroup\windowDock_OneSearch\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\17\qBaseDockWidgetGroup\windowDock_OneSearch\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\17\qBaseDockWidgetGroup\windowDock_nWave_3\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\17\qBaseDockWidgetGroup\windowDock_nWave_3\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\17\qBaseDockWidgetGroup\windowDock_nWave_3\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\17\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeMax=1 +Verdi_1\qBaseWindowNextStateGroup\17\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeFix=1 +Verdi_1\qBaseWindowNextStateGroup\17\qBaseDockWidgetGroup\windowDock_nWave_3\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\17\qBaseDockWidgetGroup\windowDock_nSchema_4\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\17\qBaseDockWidgetGroup\windowDock_nSchema_4\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\17\qBaseDockWidgetGroup\windowDock_nSchema_4\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\17\qBaseDockWidgetGroup\windowDock_nSchema_4\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\17\ProductVersion=201809 +Verdi_1\qBaseWindowNextStateGroup\17\Layout="@ByteArray(\0\0\0\xff\0\0\0/\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x4\xeb\xfc\x1\0\0\0\x4\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x33\0\0\0\0\0\0\0\n\0\0\0\0\x80\0\xff\xff\xff\xfc\0\0\0\0\0\0\x2\\\0\0\0\0\0\xff\xff\xff\xfa\xff\xff\xff\xff\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfc\0\0\x2\x62\0\0\0\xb7\0\0\0\0\0\xff\xff\xff\xfa\xff\xff\xff\xff\x1\0\0\0\x2\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\0\0k\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0h\0\x65\0r\0i\0t\0\x61\0n\0\x63\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xae\0\xff\xff\xff\xfc\0\0\x3\x1f\0\0\x6\xe1\0\0\0\0\0\xff\xff\xff\xfa\0\0\0\x5\x1\0\0\0\b\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\0\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x34\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x35\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x36\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x37\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x32\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x38\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x39\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\0\0\0\x3\0\0\n\0\0\0\x4\xeb\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\n\0\0\0\n\0\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x3\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\n\0\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\0\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x33\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x34\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowNextStateGroup\17\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\17\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\17\size=@Size(2560 1337) +Verdi_1\qBaseWindowNextStateGroup\17\geometry_x=-1 +Verdi_1\qBaseWindowNextStateGroup\17\geometry_y=27 +Verdi_1\qBaseWindowNextStateGroup\17\geometry_width=2560 +Verdi_1\qBaseWindowNextStateGroup\17\geometry_height=1337 +Verdi_1\qBaseWindowNextStateGroup\18\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowNextStateGroup\18\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\18\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\18\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\18\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\18\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\18\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeMax=1 +Verdi_1\qBaseWindowNextStateGroup\18\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\18\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\18\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\18\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\18\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\18\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\18\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\18\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\18\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\18\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\18\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\18\qBaseDockWidgetGroup\windowDock_OneSearch\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\18\qBaseDockWidgetGroup\windowDock_OneSearch\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\18\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\18\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\18\qBaseDockWidgetGroup\windowDock_OneSearch\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\18\qBaseDockWidgetGroup\windowDock_nWave_3\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\18\qBaseDockWidgetGroup\windowDock_nWave_3\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\18\qBaseDockWidgetGroup\windowDock_nWave_3\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\18\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\18\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\18\qBaseDockWidgetGroup\windowDock_nWave_3\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\18\qBaseDockWidgetGroup\windowDock_nSchema_4\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\18\qBaseDockWidgetGroup\windowDock_nSchema_4\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\18\qBaseDockWidgetGroup\windowDock_nSchema_4\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\18\qBaseDockWidgetGroup\windowDock_nSchema_4\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\18\qBaseDockWidgetGroup\windowDock_nSchema_4\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\18\qBaseDockWidgetGroup\windowDock_nSchema_4\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\18\qBaseDockWidgetGroup\windowDock_nSchema_4\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\18\ProductVersion=201809 +Verdi_1\qBaseWindowNextStateGroup\18\Layout="@ByteArray(\0\0\0\xff\0\0\0\x30\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x4\xeb\xfc\x1\0\0\0\x4\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x33\0\0\0\0\0\0\0\n\0\0\0\0\x80\0\xff\xff\xff\xfc\0\0\0\0\0\0\x2\\\0\0\0\0\0\xff\xff\xff\xfa\xff\xff\xff\xff\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfc\0\0\x2\x62\0\0\0\xb7\0\0\0\0\0\xff\xff\xff\xfa\xff\xff\xff\xff\x1\0\0\0\x2\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\0\0k\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0h\0\x65\0r\0i\0t\0\x61\0n\0\x63\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xae\0\xff\xff\xff\xfc\0\0\x3\x1f\0\0\x6\xe1\0\0\0\0\0\xff\xff\xff\xfa\0\0\0\x4\x1\0\0\0\a\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x34\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x35\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x36\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x37\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x32\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x38\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x39\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\0\0\0\x3\0\0\n\0\0\0\x4\xeb\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\n\0\0\0\n\0\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x4\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\n\0\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\0\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\0\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x33\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x34\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowNextStateGroup\18\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\18\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\18\size=@Size(2560 1337) +Verdi_1\qBaseWindowNextStateGroup\18\geometry_x=-1 +Verdi_1\qBaseWindowNextStateGroup\18\geometry_y=27 +Verdi_1\qBaseWindowNextStateGroup\18\geometry_width=2560 +Verdi_1\qBaseWindowNextStateGroup\18\geometry_height=1337 +Verdi_1\qBaseWindowNextStateGroup\19\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowNextStateGroup\19\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\19\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\19\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\19\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\19\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\19\qBaseDockWidgetGroup\windowDock_OneSearch\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\19\qBaseDockWidgetGroup\windowDock_OneSearch\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\19\qBaseDockWidgetGroup\windowDock_nWave_3\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\19\qBaseDockWidgetGroup\windowDock_nWave_3\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\19\qBaseDockWidgetGroup\windowDock_nWave_3\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\19\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeMax=1 +Verdi_1\qBaseWindowNextStateGroup\19\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeFix=1 +Verdi_1\qBaseWindowNextStateGroup\19\qBaseDockWidgetGroup\windowDock_nWave_3\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\19\qBaseDockWidgetGroup\windowDock_nSchema_4\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\19\qBaseDockWidgetGroup\windowDock_nSchema_4\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\19\qBaseDockWidgetGroup\windowDock_nSchema_4\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\19\qBaseDockWidgetGroup\windowDock_nSchema_4\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\19\ProductVersion=201809 +Verdi_1\qBaseWindowNextStateGroup\19\Layout="@ByteArray(\0\0\0\xff\0\0\0\x31\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x4\xeb\xfc\x1\0\0\0\x4\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x33\0\0\0\0\0\0\0\n\0\0\0\0\x80\0\xff\xff\xff\xfc\0\0\0\0\0\0\x2\\\0\0\0\0\0\xff\xff\xff\xfa\xff\xff\xff\xff\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfc\0\0\x2\x62\0\0\0\xb7\0\0\0\0\0\xff\xff\xff\xfa\xff\xff\xff\xff\x1\0\0\0\x2\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\0\0k\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0h\0\x65\0r\0i\0t\0\x61\0n\0\x63\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xae\0\xff\xff\xff\xfc\0\0\x3\x1f\0\0\x6\xe1\0\0\0\0\0\xff\xff\xff\xfa\0\0\0\x4\x1\0\0\0\a\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x34\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x35\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x36\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x37\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x32\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x38\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x39\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\0\0\0\x3\0\0\n\0\0\0\x4\xeb\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\n\0\0\0\x2\xc6\0\xff\xff\xff\xfa\0\0\0\x4\x1\0\0\0\x5\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\0\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\x1\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\xff\xff\xff\xfb\0\0\0*\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x31\0\x30\x1\0\0\0\0\xff\xff\xff\xff\0\0\x2\xc6\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x33\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x34\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowNextStateGroup\19\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\19\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\19\size=@Size(2560 1337) +Verdi_1\qBaseWindowNextStateGroup\19\geometry_x=-1 +Verdi_1\qBaseWindowNextStateGroup\19\geometry_y=27 +Verdi_1\qBaseWindowNextStateGroup\19\geometry_width=2560 +Verdi_1\qBaseWindowNextStateGroup\19\geometry_height=1337 +Verdi_1\qBaseWindowNextStateGroup\20\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeMax=1 +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeMax=1 +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\windowDock_OneSearch\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\windowDock_OneSearch\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeMax=1 +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\windowDock_OneSearch\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\windowDock_nWave_3\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\windowDock_nWave_3\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\windowDock_nWave_3\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\windowDock_nWave_3\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\windowDock_nSchema_4\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\windowDock_nSchema_4\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\windowDock_nSchema_4\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\windowDock_nSchema_4\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\windowDock_nSchema_4\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\windowDock_nSchema_4\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\windowDock_nSchema_4\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\20\ProductVersion=201809 +Verdi_1\qBaseWindowNextStateGroup\20\Layout="@ByteArray(\0\0\0\xff\0\0\0\x32\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x4\xeb\xfc\x1\0\0\0\x4\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x33\0\0\0\0\0\0\0\n\0\0\0\0\x80\0\xff\xff\xff\xfc\0\0\0\0\0\0\x2\\\0\0\0\0\0\xff\xff\xff\xfa\xff\xff\xff\xff\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfc\0\0\x2\x62\0\0\0\xb7\0\0\0\0\0\xff\xff\xff\xfa\xff\xff\xff\xff\x1\0\0\0\x2\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\0\0k\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0h\0\x65\0r\0i\0t\0\x61\0n\0\x63\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xae\0\xff\xff\xff\xfc\0\0\x3\x1f\0\0\x6\xe1\0\0\0\0\0\xff\xff\xff\xfa\0\0\0\x4\x1\0\0\0\a\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x34\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x35\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x36\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x37\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x32\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x38\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x39\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\0\0\0\x3\0\0\n\0\0\0\x4\xeb\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\n\0\0\0\x2,\0\xff\xff\xff\xfa\0\0\0\x3\x1\0\0\0\x5\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\x1\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\x1\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\xff\xff\xff\xfb\0\0\0*\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x31\0\x30\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x33\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x34\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowNextStateGroup\20\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\20\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\20\size=@Size(2560 1337) +Verdi_1\qBaseWindowNextStateGroup\20\geometry_x=-1 +Verdi_1\qBaseWindowNextStateGroup\20\geometry_y=27 +Verdi_1\qBaseWindowNextStateGroup\20\geometry_width=2560 +Verdi_1\qBaseWindowNextStateGroup\20\geometry_height=1337 +Verdi_1\qBaseWindowNextStateGroup\21\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\windowDock_OneSearch\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\windowDock_OneSearch\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\windowDock_nWave_3\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\windowDock_nWave_3\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\windowDock_nWave_3\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeMax=1 +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeFix=1 +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\windowDock_nWave_3\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\windowDock_nSchema_4\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\windowDock_nSchema_4\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\windowDock_nSchema_4\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\windowDock_nSchema_4\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\21\ProductVersion=201809 +Verdi_1\qBaseWindowNextStateGroup\21\Layout="@ByteArray(\0\0\0\xff\0\0\0\x33\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x4\xeb\xfc\x1\0\0\0\x4\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x33\0\0\0\0\0\0\0\n\0\0\0\0\x80\0\xff\xff\xff\xfc\0\0\0\0\0\0\x2\\\0\0\0\0\0\xff\xff\xff\xfa\xff\xff\xff\xff\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfc\0\0\x2\x62\0\0\0\xb7\0\0\0\0\0\xff\xff\xff\xfa\xff\xff\xff\xff\x1\0\0\0\x2\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\0\0k\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0h\0\x65\0r\0i\0t\0\x61\0n\0\x63\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xae\0\xff\xff\xff\xfc\0\0\x3\x1f\0\0\x6\xe1\0\0\0\0\0\xff\xff\xff\xfa\0\0\0\x4\x1\0\0\0\a\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x34\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x35\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x36\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x37\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x32\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x38\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x39\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\0\0\0\x3\0\0\n\0\0\0\x4\xeb\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\n\0\0\0\x2\xc6\0\xff\xff\xff\xfa\0\0\0\x5\x1\0\0\0\x6\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\x1\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\x1\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\xff\xff\xff\xfb\0\0\0*\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x31\0\x30\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0*\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x31\0\x31\x1\0\0\0\0\xff\xff\xff\xff\0\0\x2\xc6\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x33\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x34\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowNextStateGroup\21\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\21\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\21\size=@Size(2560 1337) +Verdi_1\qBaseWindowNextStateGroup\21\geometry_x=-1 +Verdi_1\qBaseWindowNextStateGroup\21\geometry_y=27 +Verdi_1\qBaseWindowNextStateGroup\21\geometry_width=2560 +Verdi_1\qBaseWindowNextStateGroup\21\geometry_height=1337 +Verdi_1\qBaseWindowNextStateGroup\22\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowNextStateGroup\22\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\22\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\22\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\22\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\22\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\22\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\22\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\22\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\22\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\22\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\22\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\22\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\22\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\22\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\22\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\22\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\22\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\22\qBaseDockWidgetGroup\windowDock_OneSearch\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\22\qBaseDockWidgetGroup\windowDock_OneSearch\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\22\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\22\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\22\qBaseDockWidgetGroup\windowDock_OneSearch\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\22\qBaseDockWidgetGroup\windowDock_nWave_3\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\22\qBaseDockWidgetGroup\windowDock_nWave_3\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\22\qBaseDockWidgetGroup\windowDock_nWave_3\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\22\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\22\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\22\qBaseDockWidgetGroup\windowDock_nWave_3\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\22\qBaseDockWidgetGroup\windowDock_nSchema_4\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\22\qBaseDockWidgetGroup\windowDock_nSchema_4\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\22\qBaseDockWidgetGroup\windowDock_nSchema_4\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\22\qBaseDockWidgetGroup\windowDock_nSchema_4\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\22\qBaseDockWidgetGroup\windowDock_nSchema_4\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\22\qBaseDockWidgetGroup\windowDock_nSchema_4\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\22\qBaseDockWidgetGroup\windowDock_nSchema_4\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\22\ProductVersion=201809 +Verdi_1\qBaseWindowNextStateGroup\22\Layout="@ByteArray(\0\0\0\xff\0\0\0\x16\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x2s\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x1\xba\0\0\0\x89\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\xe9\0\0\0\xc6\0\0\0k\0\0\0k\xfc\0\0\x1\xc0\0\0\b@\0\0\0\xbf\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x2\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\x1\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x34\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\0\0\0\x3\0\0\n\0\0\0\x2r\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\n\0\0\0\x2,\0\xff\xff\xff\xfa\0\0\0\x3\x1\0\0\0\x4\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\x1\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x33\x1\0\0\0\0\xff\xff\xff\xff\0\0\x1[\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x33\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x34\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowNextStateGroup\22\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\22\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\22\size=@Size(2560 1337) +Verdi_1\qBaseWindowNextStateGroup\22\geometry_x=-1 +Verdi_1\qBaseWindowNextStateGroup\22\geometry_y=27 +Verdi_1\qBaseWindowNextStateGroup\22\geometry_width=2560 +Verdi_1\qBaseWindowNextStateGroup\22\geometry_height=1337 +Verdi_1\qBaseWindowNextStateGroup\23\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowNextStateGroup\23\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\23\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\23\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\23\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\23\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\23\qBaseDockWidgetGroup\windowDock_OneSearch\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\23\qBaseDockWidgetGroup\windowDock_OneSearch\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\23\qBaseDockWidgetGroup\windowDock_nWave_3\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\23\qBaseDockWidgetGroup\windowDock_nWave_3\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\23\qBaseDockWidgetGroup\windowDock_nWave_3\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\23\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeMax=1 +Verdi_1\qBaseWindowNextStateGroup\23\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeFix=1 +Verdi_1\qBaseWindowNextStateGroup\23\qBaseDockWidgetGroup\windowDock_nWave_3\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\23\qBaseDockWidgetGroup\windowDock_nSchema_4\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\23\qBaseDockWidgetGroup\windowDock_nSchema_4\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\23\qBaseDockWidgetGroup\windowDock_nSchema_4\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\23\qBaseDockWidgetGroup\windowDock_nSchema_4\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\23\ProductVersion=201809 +Verdi_1\qBaseWindowNextStateGroup\23\Layout="@ByteArray(\0\0\0\xff\0\0\0\x17\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x3\x6\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x2\x8c\0\0\0\0\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\xe9\0\0\0\xc6\0\0\0k\0\0\0k\xfc\0\0\x2\x92\0\0\an\0\0\0\0\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x2\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\0\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x34\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\0\0\0\x3\0\0\n\0\0\0\x1\xdf\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\n\0\0\0\x1[\0\xff\xff\xff\xfa\0\0\0\x3\x1\0\0\0\x4\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\0\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x33\x1\0\0\0\0\xff\xff\xff\xff\0\0\x1[\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x33\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x34\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowNextStateGroup\23\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\23\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\23\size=@Size(2560 1337) +Verdi_1\qBaseWindowNextStateGroup\23\geometry_x=-1 +Verdi_1\qBaseWindowNextStateGroup\23\geometry_y=27 +Verdi_1\qBaseWindowNextStateGroup\23\geometry_width=2560 +Verdi_1\qBaseWindowNextStateGroup\23\geometry_height=1337 +Verdi_1\qBaseWindowNextStateGroup\24\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowNextStateGroup\24\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\24\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\24\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\24\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\24\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\24\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\24\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\24\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\24\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\24\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\24\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\24\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\24\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\24\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\24\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\24\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\24\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\24\qBaseDockWidgetGroup\windowDock_OneSearch\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\24\qBaseDockWidgetGroup\windowDock_OneSearch\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\24\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\24\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\24\qBaseDockWidgetGroup\windowDock_OneSearch\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\24\qBaseDockWidgetGroup\windowDock_nWave_3\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\24\qBaseDockWidgetGroup\windowDock_nWave_3\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\24\qBaseDockWidgetGroup\windowDock_nWave_3\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\24\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\24\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\24\qBaseDockWidgetGroup\windowDock_nWave_3\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\24\qBaseDockWidgetGroup\windowDock_nSchema_4\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\24\qBaseDockWidgetGroup\windowDock_nSchema_4\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\24\qBaseDockWidgetGroup\windowDock_nSchema_4\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\24\qBaseDockWidgetGroup\windowDock_nSchema_4\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\24\qBaseDockWidgetGroup\windowDock_nSchema_4\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\24\qBaseDockWidgetGroup\windowDock_nSchema_4\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\24\qBaseDockWidgetGroup\windowDock_nSchema_4\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\24\ProductVersion=201809 +Verdi_1\qBaseWindowNextStateGroup\24\Layout="@ByteArray(\0\0\0\xff\0\0\0\x18\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x3\x6\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x2\x8c\0\0\0\x89\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\xe9\0\0\0\xc6\0\0\0k\0\0\0k\xfc\0\0\x2\x92\0\0\an\0\0\0\xbf\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x2\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\x1\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x34\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\0\0\0\x3\0\0\n\0\0\0\x1\xdf\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\n\0\0\0\x2,\0\xff\xff\xff\xfa\0\0\0\x3\x1\0\0\0\x4\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\x1\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x33\x1\0\0\0\0\xff\xff\xff\xff\0\0\x1[\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x33\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x34\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowNextStateGroup\24\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\24\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\24\size=@Size(2560 1337) +Verdi_1\qBaseWindowNextStateGroup\24\geometry_x=-1 +Verdi_1\qBaseWindowNextStateGroup\24\geometry_y=27 +Verdi_1\qBaseWindowNextStateGroup\24\geometry_width=2560 +Verdi_1\qBaseWindowNextStateGroup\24\geometry_height=1337 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_5\isNestedWindow=1 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_5\isVisible=false +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_5\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_5\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_5\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_5\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_5\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\25\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowNextStateGroup\25\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\25\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\25\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\25\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\25\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\25\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\25\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\25\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\25\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\25\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\25\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\25\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\25\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\25\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\25\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\25\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\25\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\25\qBaseDockWidgetGroup\windowDock_OneSearch\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\25\qBaseDockWidgetGroup\windowDock_OneSearch\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\25\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\25\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\25\qBaseDockWidgetGroup\windowDock_OneSearch\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\25\qBaseDockWidgetGroup\windowDock_nWave_3\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\25\qBaseDockWidgetGroup\windowDock_nWave_3\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\25\qBaseDockWidgetGroup\windowDock_nWave_3\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\25\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\25\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\25\qBaseDockWidgetGroup\windowDock_nWave_3\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\25\qBaseDockWidgetGroup\windowDock_nSchema_4\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\25\qBaseDockWidgetGroup\windowDock_nSchema_4\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\25\qBaseDockWidgetGroup\windowDock_nSchema_4\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\25\qBaseDockWidgetGroup\windowDock_nSchema_4\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\25\qBaseDockWidgetGroup\windowDock_nSchema_4\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\25\qBaseDockWidgetGroup\windowDock_nSchema_4\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\25\qBaseDockWidgetGroup\windowDock_nSchema_4\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\25\qBaseDockWidgetGroup\windowDock_nSchema_5\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\25\qBaseDockWidgetGroup\windowDock_nSchema_5\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\25\qBaseDockWidgetGroup\windowDock_nSchema_5\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\25\qBaseDockWidgetGroup\windowDock_nSchema_5\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\25\qBaseDockWidgetGroup\windowDock_nSchema_5\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\25\qBaseDockWidgetGroup\windowDock_nSchema_5\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\25\qBaseDockWidgetGroup\windowDock_nSchema_5\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\25\ProductVersion=201809 +Verdi_1\qBaseWindowNextStateGroup\25\Layout="@ByteArray(\0\0\0\xff\0\0\0\x19\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x3\x6\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x2\x8c\0\0\0\x89\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\xe9\0\0\0\xc6\0\0\0k\0\0\0k\xfc\0\0\x2\x92\0\0\an\0\0\x2\xc6\0\0\bC\xfa\0\0\0\x2\x1\0\0\0\x3\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\x1\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x34\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x35\x1\0\0\0\0\xff\xff\xff\xff\0\0\x2\xc6\0\0\bC\0\0\0\x3\0\0\n\0\0\0\x1\xdf\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\n\0\0\0\x2,\0\xff\xff\xff\xfa\0\0\0\x3\x1\0\0\0\x4\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\x1\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x33\x1\0\0\0\0\xff\xff\xff\xff\0\0\x1[\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x33\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x34\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowNextStateGroup\25\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\25\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\25\size=@Size(2560 1337) +Verdi_1\qBaseWindowNextStateGroup\25\geometry_x=-1 +Verdi_1\qBaseWindowNextStateGroup\25\geometry_y=27 +Verdi_1\qBaseWindowNextStateGroup\25\geometry_width=2560 +Verdi_1\qBaseWindowNextStateGroup\25\geometry_height=1337 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\isVisible=false +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_6\isNestedWindow=1 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_6\isVisible=false +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_6\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_6\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_6\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_6\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_6\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\26\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowNextStateGroup\26\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\26\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\26\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\26\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\26\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\26\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\26\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\26\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\26\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\26\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\26\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\26\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\26\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\26\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\26\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\26\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\26\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\26\qBaseDockWidgetGroup\windowDock_OneSearch\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\26\qBaseDockWidgetGroup\windowDock_OneSearch\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\26\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\26\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\26\qBaseDockWidgetGroup\windowDock_OneSearch\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\26\qBaseDockWidgetGroup\windowDock_nWave_3\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\26\qBaseDockWidgetGroup\windowDock_nWave_3\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\26\qBaseDockWidgetGroup\windowDock_nWave_3\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\26\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\26\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\26\qBaseDockWidgetGroup\windowDock_nWave_3\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\26\qBaseDockWidgetGroup\windowDock_nSchema_4\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\26\qBaseDockWidgetGroup\windowDock_nSchema_4\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\26\qBaseDockWidgetGroup\windowDock_nSchema_4\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\26\qBaseDockWidgetGroup\windowDock_nSchema_4\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\26\qBaseDockWidgetGroup\windowDock_nSchema_4\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\26\qBaseDockWidgetGroup\windowDock_nSchema_4\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\26\qBaseDockWidgetGroup\windowDock_nSchema_4\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\26\qBaseDockWidgetGroup\windowDock_nSchema_5\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\26\qBaseDockWidgetGroup\windowDock_nSchema_5\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\26\qBaseDockWidgetGroup\windowDock_nSchema_5\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\26\qBaseDockWidgetGroup\windowDock_nSchema_5\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\26\qBaseDockWidgetGroup\windowDock_nSchema_5\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\26\qBaseDockWidgetGroup\windowDock_nSchema_5\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\26\qBaseDockWidgetGroup\windowDock_nSchema_5\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\26\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\26\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\26\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\26\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\26\qBaseDockWidgetGroup\windowDock_nSchema_6\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\26\qBaseDockWidgetGroup\windowDock_nSchema_6\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\26\qBaseDockWidgetGroup\windowDock_nSchema_6\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\26\qBaseDockWidgetGroup\windowDock_nSchema_6\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\26\qBaseDockWidgetGroup\windowDock_nSchema_6\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\26\qBaseDockWidgetGroup\windowDock_nSchema_6\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\26\qBaseDockWidgetGroup\windowDock_nSchema_6\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\26\ProductVersion=201809 +Verdi_1\qBaseWindowNextStateGroup\26\Layout="@ByteArray(\0\0\0\xff\0\0\0\x1a\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x3\x6\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x2\\\0\0\0\x89\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfc\0\0\x2\x62\0\0\0\xb7\0\0\0\xae\0\xff\xff\xff\xfa\0\0\0\x1\x1\0\0\0\x2\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\0\0k\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0h\0\x65\0r\0i\0t\0\x61\0n\0\x63\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xae\0\xff\xff\xff\xfc\0\0\x3\x1f\0\0\x6\xe1\0\0\x2\xc6\0\0\x6\xe1\xfa\0\0\0\x3\x1\0\0\0\x4\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\x1\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x34\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x35\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x36\x1\0\0\0\0\xff\xff\xff\xff\0\0\x2\xc6\0\0\x6\xe1\0\0\0\x3\0\0\n\0\0\0\x1\xdf\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\n\0\0\0\x2,\0\xff\xff\xff\xfa\0\0\0\x3\x1\0\0\0\x4\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\x1\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x33\x1\0\0\0\0\xff\xff\xff\xff\0\0\x1[\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x33\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x34\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowNextStateGroup\26\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\26\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\26\size=@Size(2560 1337) +Verdi_1\qBaseWindowNextStateGroup\26\geometry_x=-1 +Verdi_1\qBaseWindowNextStateGroup\26\geometry_y=27 +Verdi_1\qBaseWindowNextStateGroup\26\geometry_width=2560 +Verdi_1\qBaseWindowNextStateGroup\26\geometry_height=1337 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_7\isNestedWindow=1 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_7\isVisible=false +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_7\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_7\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_7\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_7\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_7\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\27\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowNextStateGroup\27\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\27\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\27\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\27\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\27\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\27\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\27\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\27\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\27\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\27\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\27\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\27\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\27\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\27\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\27\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\27\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\27\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\27\qBaseDockWidgetGroup\windowDock_OneSearch\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\27\qBaseDockWidgetGroup\windowDock_OneSearch\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\27\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\27\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\27\qBaseDockWidgetGroup\windowDock_OneSearch\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\27\qBaseDockWidgetGroup\windowDock_nWave_3\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\27\qBaseDockWidgetGroup\windowDock_nWave_3\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\27\qBaseDockWidgetGroup\windowDock_nWave_3\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\27\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\27\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\27\qBaseDockWidgetGroup\windowDock_nWave_3\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\27\qBaseDockWidgetGroup\windowDock_nSchema_4\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\27\qBaseDockWidgetGroup\windowDock_nSchema_4\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\27\qBaseDockWidgetGroup\windowDock_nSchema_4\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\27\qBaseDockWidgetGroup\windowDock_nSchema_4\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\27\qBaseDockWidgetGroup\windowDock_nSchema_4\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\27\qBaseDockWidgetGroup\windowDock_nSchema_4\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\27\qBaseDockWidgetGroup\windowDock_nSchema_4\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\27\qBaseDockWidgetGroup\windowDock_nSchema_5\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\27\qBaseDockWidgetGroup\windowDock_nSchema_5\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\27\qBaseDockWidgetGroup\windowDock_nSchema_5\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\27\qBaseDockWidgetGroup\windowDock_nSchema_5\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\27\qBaseDockWidgetGroup\windowDock_nSchema_5\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\27\qBaseDockWidgetGroup\windowDock_nSchema_5\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\27\qBaseDockWidgetGroup\windowDock_nSchema_5\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\27\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\27\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\27\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\27\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\27\qBaseDockWidgetGroup\windowDock_nSchema_6\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\27\qBaseDockWidgetGroup\windowDock_nSchema_6\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\27\qBaseDockWidgetGroup\windowDock_nSchema_6\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\27\qBaseDockWidgetGroup\windowDock_nSchema_6\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\27\qBaseDockWidgetGroup\windowDock_nSchema_6\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\27\qBaseDockWidgetGroup\windowDock_nSchema_6\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\27\qBaseDockWidgetGroup\windowDock_nSchema_6\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\27\qBaseDockWidgetGroup\windowDock_nSchema_7\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\27\qBaseDockWidgetGroup\windowDock_nSchema_7\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\27\qBaseDockWidgetGroup\windowDock_nSchema_7\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\27\qBaseDockWidgetGroup\windowDock_nSchema_7\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\27\qBaseDockWidgetGroup\windowDock_nSchema_7\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\27\qBaseDockWidgetGroup\windowDock_nSchema_7\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\27\qBaseDockWidgetGroup\windowDock_nSchema_7\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\27\ProductVersion=201809 +Verdi_1\qBaseWindowNextStateGroup\27\Layout="@ByteArray(\0\0\0\xff\0\0\0\x1b\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x3\x6\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x2\\\0\0\0\x89\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfc\0\0\x2\x62\0\0\0\xb7\0\0\0\xae\0\xff\xff\xff\xfa\0\0\0\x1\x1\0\0\0\x2\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\0\0k\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0h\0\x65\0r\0i\0t\0\x61\0n\0\x63\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xae\0\xff\xff\xff\xfc\0\0\x3\x1f\0\0\x6\xe1\0\0\x2\xc6\0\0\x6\xe1\xfa\0\0\0\x4\x1\0\0\0\x5\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\x1\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x34\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x35\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x36\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x37\x1\0\0\0\0\xff\xff\xff\xff\0\0\x2\xc6\0\0\x6\xe1\0\0\0\x3\0\0\n\0\0\0\x1\xdf\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\n\0\0\0\x2,\0\xff\xff\xff\xfa\0\0\0\x3\x1\0\0\0\x4\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\x1\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x33\x1\0\0\0\0\xff\xff\xff\xff\0\0\x1[\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x33\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x34\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowNextStateGroup\27\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\27\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\27\size=@Size(2560 1337) +Verdi_1\qBaseWindowNextStateGroup\27\geometry_x=-1 +Verdi_1\qBaseWindowNextStateGroup\27\geometry_y=27 +Verdi_1\qBaseWindowNextStateGroup\27\geometry_width=2560 +Verdi_1\qBaseWindowNextStateGroup\27\geometry_height=1337 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_8\isNestedWindow=1 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_8\isVisible=false +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_8\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_8\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_8\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_8\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_8\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\28\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\windowDock_OneSearch\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\windowDock_OneSearch\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\windowDock_OneSearch\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\windowDock_nWave_3\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\windowDock_nWave_3\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\windowDock_nWave_3\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\windowDock_nWave_3\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\windowDock_nSchema_4\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\windowDock_nSchema_4\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\windowDock_nSchema_4\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\windowDock_nSchema_4\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\windowDock_nSchema_4\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\windowDock_nSchema_4\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\windowDock_nSchema_4\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\windowDock_nSchema_5\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\windowDock_nSchema_5\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\windowDock_nSchema_5\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\windowDock_nSchema_5\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\windowDock_nSchema_5\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\windowDock_nSchema_5\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\windowDock_nSchema_5\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\windowDock_nSchema_6\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\windowDock_nSchema_6\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\windowDock_nSchema_6\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\windowDock_nSchema_6\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\windowDock_nSchema_6\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\windowDock_nSchema_6\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\windowDock_nSchema_6\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\windowDock_nSchema_7\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\windowDock_nSchema_7\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\windowDock_nSchema_7\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\windowDock_nSchema_7\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\windowDock_nSchema_7\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\windowDock_nSchema_7\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\windowDock_nSchema_7\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\windowDock_nSchema_8\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\windowDock_nSchema_8\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\windowDock_nSchema_8\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\windowDock_nSchema_8\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\windowDock_nSchema_8\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\windowDock_nSchema_8\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\28\qBaseDockWidgetGroup\windowDock_nSchema_8\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\28\ProductVersion=201809 +Verdi_1\qBaseWindowNextStateGroup\28\Layout="@ByteArray(\0\0\0\xff\0\0\0\x1c\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x3\xb3\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x2\\\0\0\0\x89\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfc\0\0\x2\x62\0\0\0\xb7\0\0\0\xae\0\xff\xff\xff\xfa\0\0\0\x1\x1\0\0\0\x2\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\0\0k\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0h\0\x65\0r\0i\0t\0\x61\0n\0\x63\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xae\0\xff\xff\xff\xfc\0\0\x3\x1f\0\0\x6\xe1\0\0\x2\xc6\0\0\x6\xe1\xfa\0\0\0\x6\x1\0\0\0\a\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\x1\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x34\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x35\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x36\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x37\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x32\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x38\x1\0\0\0\0\xff\xff\xff\xff\0\0\x2\xc6\0\0\x6\xe1\0\0\0\x3\0\0\n\0\0\0\x1\x32\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\n\0\0\0\x2,\0\xff\xff\xff\xfa\0\0\0\x3\x1\0\0\0\x4\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\x1\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x33\x1\0\0\0\0\xff\xff\xff\xff\0\0\x1[\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x33\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x34\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowNextStateGroup\28\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\28\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\28\size=@Size(2560 1337) +Verdi_1\qBaseWindowNextStateGroup\28\geometry_x=-1 +Verdi_1\qBaseWindowNextStateGroup\28\geometry_y=27 +Verdi_1\qBaseWindowNextStateGroup\28\geometry_width=2560 +Verdi_1\qBaseWindowNextStateGroup\28\geometry_height=1337 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_9\isNestedWindow=1 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_9\isVisible=false +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_9\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_9\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_9\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_9\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_9\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\29\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\windowDock_OneSearch\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\windowDock_OneSearch\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\windowDock_OneSearch\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\windowDock_nWave_3\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\windowDock_nWave_3\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\windowDock_nWave_3\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\windowDock_nWave_3\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\windowDock_nSchema_4\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\windowDock_nSchema_4\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\windowDock_nSchema_4\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\windowDock_nSchema_4\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\windowDock_nSchema_4\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\windowDock_nSchema_4\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\windowDock_nSchema_4\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\windowDock_nSchema_5\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\windowDock_nSchema_5\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\windowDock_nSchema_5\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\windowDock_nSchema_5\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\windowDock_nSchema_5\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\windowDock_nSchema_5\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\windowDock_nSchema_5\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\windowDock_nSchema_6\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\windowDock_nSchema_6\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\windowDock_nSchema_6\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\windowDock_nSchema_6\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\windowDock_nSchema_6\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\windowDock_nSchema_6\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\windowDock_nSchema_6\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\windowDock_nSchema_7\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\windowDock_nSchema_7\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\windowDock_nSchema_7\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\windowDock_nSchema_7\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\windowDock_nSchema_7\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\windowDock_nSchema_7\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\windowDock_nSchema_7\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\windowDock_nSchema_8\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\windowDock_nSchema_8\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\windowDock_nSchema_8\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\windowDock_nSchema_8\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\windowDock_nSchema_8\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\windowDock_nSchema_8\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\windowDock_nSchema_8\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\windowDock_nSchema_9\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\windowDock_nSchema_9\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\windowDock_nSchema_9\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\windowDock_nSchema_9\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\windowDock_nSchema_9\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\windowDock_nSchema_9\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\29\qBaseDockWidgetGroup\windowDock_nSchema_9\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\29\ProductVersion=201809 +Verdi_1\qBaseWindowNextStateGroup\29\Layout="@ByteArray(\0\0\0\xff\0\0\0\x1d\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x3\xb3\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x2\\\0\0\0\x89\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfc\0\0\x2\x62\0\0\0\xb7\0\0\0\xae\0\xff\xff\xff\xfa\0\0\0\x1\x1\0\0\0\x2\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\0\0k\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0h\0\x65\0r\0i\0t\0\x61\0n\0\x63\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xae\0\xff\xff\xff\xfc\0\0\x3\x1f\0\0\x6\xe1\0\0\x2\xc6\0\0\x6\xe1\xfa\0\0\0\a\x1\0\0\0\b\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\x1\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x34\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x35\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x36\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x37\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x32\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x38\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x39\x1\0\0\0\0\xff\xff\xff\xff\0\0\x2\xc6\0\0\x6\xe1\0\0\0\x3\0\0\n\0\0\0\x1\x32\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\n\0\0\0\x2,\0\xff\xff\xff\xfa\0\0\0\x3\x1\0\0\0\x4\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\x1\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x33\x1\0\0\0\0\xff\xff\xff\xff\0\0\x1[\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x33\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x34\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowNextStateGroup\29\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\29\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\29\size=@Size(2560 1337) +Verdi_1\qBaseWindowNextStateGroup\29\geometry_x=-1 +Verdi_1\qBaseWindowNextStateGroup\29\geometry_y=27 +Verdi_1\qBaseWindowNextStateGroup\29\geometry_width=2560 +Verdi_1\qBaseWindowNextStateGroup\29\geometry_height=1337 +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\windowDock_OneSearch\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\windowDock_OneSearch\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\windowDock_nWave_3\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\windowDock_nWave_3\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\windowDock_nWave_3\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeMax=1 +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeFix=1 +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\windowDock_nWave_3\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\windowDock_nSchema_4\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\windowDock_nSchema_4\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\windowDock_nSchema_4\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\windowDock_nSchema_4\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\windowDock_nSchema_5\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\windowDock_nSchema_5\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\windowDock_nSchema_5\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\windowDock_nSchema_5\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\windowDock_nSchema_6\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\windowDock_nSchema_6\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\windowDock_nSchema_6\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\windowDock_nSchema_6\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\windowDock_nSchema_7\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\windowDock_nSchema_7\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\windowDock_nSchema_7\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\windowDock_nSchema_7\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\windowDock_nSchema_8\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\windowDock_nSchema_8\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\windowDock_nSchema_8\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\windowDock_nSchema_8\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\windowDock_nSchema_9\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\windowDock_nSchema_9\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\windowDock_nSchema_9\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\windowDock_nSchema_9\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_nWave_3\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_nWave_3\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_nWave_3\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_nWave_3\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_nSchema_4\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_nSchema_4\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_nSchema_4\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_nSchema_4\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_nSchema_4\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_nSchema_4\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_nSchema_4\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_nSchema_5\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_nSchema_5\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_nSchema_5\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_nSchema_5\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_nSchema_5\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_nSchema_5\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_nSchema_5\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_nSchema_6\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_nSchema_6\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_nSchema_6\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_nSchema_6\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_nSchema_6\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_nSchema_6\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_nSchema_6\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_nSchema_7\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_nSchema_7\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_nSchema_7\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_nSchema_7\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_nSchema_7\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_nSchema_7\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_nSchema_7\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_nSchema_8\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_nSchema_8\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_nSchema_8\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_nSchema_8\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_nSchema_8\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_nSchema_8\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_nSchema_8\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_nSchema_9\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_nSchema_9\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_nSchema_9\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_nSchema_9\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_nSchema_9\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_nSchema_9\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_nSchema_9\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\windowDock_nWave_3\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\windowDock_nWave_3\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\windowDock_nWave_3\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeMax=1 +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeFix=1 +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\windowDock_nWave_3\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\windowDock_nSchema_4\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\windowDock_nSchema_4\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\windowDock_nSchema_4\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\windowDock_nSchema_4\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\windowDock_nSchema_5\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\windowDock_nSchema_5\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\windowDock_nSchema_5\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\windowDock_nSchema_5\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\windowDock_nSchema_6\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\windowDock_nSchema_6\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\windowDock_nSchema_6\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\windowDock_nSchema_6\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\windowDock_nSchema_7\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\windowDock_nSchema_7\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\windowDock_nSchema_7\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\windowDock_nSchema_7\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\windowDock_nSchema_8\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\windowDock_nSchema_8\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\windowDock_nSchema_8\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\windowDock_nSchema_8\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\windowDock_nSchema_9\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\windowDock_nSchema_9\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\windowDock_nSchema_9\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\windowDock_nSchema_9\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\windowDock_nWave_3\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\windowDock_nWave_3\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\windowDock_nWave_3\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeMax=1 +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeFix=1 +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\windowDock_nWave_3\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\windowDock_nSchema_4\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\windowDock_nSchema_4\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\windowDock_nSchema_4\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\windowDock_nSchema_4\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\windowDock_nSchema_5\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\windowDock_nSchema_5\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\windowDock_nSchema_5\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\windowDock_nSchema_5\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\windowDock_nSchema_6\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\windowDock_nSchema_6\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\windowDock_nSchema_6\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\windowDock_nSchema_6\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\windowDock_nSchema_7\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\windowDock_nSchema_7\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\windowDock_nSchema_7\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\windowDock_nSchema_7\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\windowDock_nSchema_8\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\windowDock_nSchema_8\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\windowDock_nSchema_8\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\windowDock_nSchema_8\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\windowDock_nSchema_9\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\windowDock_nSchema_9\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\windowDock_nSchema_9\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\windowDock_nSchema_9\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\windowDock_nWave_3\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\windowDock_nWave_3\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\windowDock_nWave_3\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeMax=1 +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeFix=1 +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\windowDock_nWave_3\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\windowDock_nSchema_4\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\windowDock_nSchema_4\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\windowDock_nSchema_4\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\windowDock_nSchema_4\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\windowDock_nSchema_5\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\windowDock_nSchema_5\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\windowDock_nSchema_5\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\windowDock_nSchema_5\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\windowDock_nSchema_6\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\windowDock_nSchema_6\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\windowDock_nSchema_6\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\windowDock_nSchema_6\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\windowDock_nSchema_7\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\windowDock_nSchema_7\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\windowDock_nSchema_7\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\windowDock_nSchema_7\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\windowDock_nSchema_8\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\windowDock_nSchema_8\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\windowDock_nSchema_8\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\windowDock_nSchema_8\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\windowDock_nSchema_9\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\windowDock_nSchema_9\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\windowDock_nSchema_9\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\windowDock_nSchema_9\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nWave_3\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nWave_3\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nWave_3\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nWave_3\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nSchema_4\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nSchema_4\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nSchema_4\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nSchema_4\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nSchema_4\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nSchema_4\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nSchema_4\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nSchema_5\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nSchema_5\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nSchema_5\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nSchema_5\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nSchema_5\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nSchema_5\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nSchema_5\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nSchema_6\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nSchema_6\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nSchema_6\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nSchema_6\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nSchema_6\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nSchema_6\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nSchema_6\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nSchema_7\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nSchema_7\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nSchema_7\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nSchema_7\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nSchema_7\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nSchema_7\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nSchema_7\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nSchema_8\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nSchema_8\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nSchema_8\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nSchema_8\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nSchema_8\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nSchema_8\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nSchema_8\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nSchema_9\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nSchema_9\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nSchema_9\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nSchema_9\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nSchema_9\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nSchema_9\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nSchema_9\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\windowDock_nWave_3\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\windowDock_nWave_3\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\windowDock_nWave_3\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeMax=1 +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeFix=1 +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\windowDock_nWave_3\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\windowDock_nSchema_4\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\windowDock_nSchema_4\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\windowDock_nSchema_4\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\windowDock_nSchema_4\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\windowDock_nSchema_5\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\windowDock_nSchema_5\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\windowDock_nSchema_5\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\windowDock_nSchema_5\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\windowDock_nSchema_6\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\windowDock_nSchema_6\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\windowDock_nSchema_6\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\windowDock_nSchema_6\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\windowDock_nSchema_7\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\windowDock_nSchema_7\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\windowDock_nSchema_7\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\windowDock_nSchema_7\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\windowDock_nSchema_8\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\windowDock_nSchema_8\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\windowDock_nSchema_8\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\windowDock_nSchema_8\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\windowDock_nSchema_9\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\windowDock_nSchema_9\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\windowDock_nSchema_9\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\windowDock_nSchema_9\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_nWave_3\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_nWave_3\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_nWave_3\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_nWave_3\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_nSchema_4\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_nSchema_4\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_nSchema_4\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_nSchema_4\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_nSchema_4\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_nSchema_4\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_nSchema_4\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_nSchema_5\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_nSchema_5\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_nSchema_5\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_nSchema_5\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_nSchema_5\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_nSchema_5\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_nSchema_5\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_nSchema_6\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_nSchema_6\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_nSchema_6\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_nSchema_6\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_nSchema_6\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_nSchema_6\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_nSchema_6\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_nSchema_7\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_nSchema_7\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_nSchema_7\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_nSchema_7\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_nSchema_7\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_nSchema_7\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_nSchema_7\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_nSchema_8\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_nSchema_8\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_nSchema_8\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_nSchema_8\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_nSchema_8\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_nSchema_8\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_nSchema_8\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_nSchema_9\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_nSchema_9\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_nSchema_9\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_nSchema_9\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_nSchema_9\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_nSchema_9\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_nSchema_9\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\windowDock_nWave_3\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\windowDock_nSchema_4\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\windowDock_nSchema_4\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\windowDock_nSchema_4\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\windowDock_nSchema_4\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\windowDock_nSchema_5\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\windowDock_nSchema_5\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\windowDock_nSchema_5\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\windowDock_nSchema_5\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\windowDock_nSchema_6\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\windowDock_nSchema_6\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\windowDock_nSchema_6\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\windowDock_nSchema_6\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\windowDock_nSchema_7\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\windowDock_nSchema_7\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\windowDock_nSchema_7\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\windowDock_nSchema_7\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\windowDock_nSchema_8\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\windowDock_nSchema_8\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\windowDock_nSchema_8\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\windowDock_nSchema_8\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\windowDock_nSchema_9\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\windowDock_nSchema_9\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\windowDock_nSchema_9\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\windowDock_nSchema_9\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeMax=1 +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\windowDock_nSchema_4\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\windowDock_nSchema_4\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\windowDock_nSchema_4\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\windowDock_nSchema_4\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\windowDock_nSchema_5\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\windowDock_nSchema_5\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\windowDock_nSchema_5\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\windowDock_nSchema_5\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\windowDock_nSchema_6\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\windowDock_nSchema_6\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\windowDock_nSchema_6\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\windowDock_nSchema_6\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\windowDock_nSchema_7\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\windowDock_nSchema_7\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\windowDock_nSchema_7\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\windowDock_nSchema_7\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\windowDock_nSchema_8\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\windowDock_nSchema_8\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\windowDock_nSchema_8\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\windowDock_nSchema_8\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\windowDock_nSchema_9\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\windowDock_nSchema_9\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\windowDock_nSchema_9\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\windowDock_nSchema_9\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\windowDock_nSchema_4\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\windowDock_nSchema_4\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\windowDock_nSchema_4\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\windowDock_nSchema_4\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\windowDock_nSchema_5\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\windowDock_nSchema_5\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\windowDock_nSchema_5\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\windowDock_nSchema_5\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\windowDock_nSchema_6\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\windowDock_nSchema_6\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\windowDock_nSchema_6\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\windowDock_nSchema_6\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\windowDock_nSchema_7\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\windowDock_nSchema_7\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\windowDock_nSchema_7\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\windowDock_nSchema_7\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\windowDock_nSchema_8\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\windowDock_nSchema_8\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\windowDock_nSchema_8\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\windowDock_nSchema_8\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\windowDock_nSchema_9\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\windowDock_nSchema_9\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\windowDock_nSchema_9\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\windowDock_nSchema_9\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_OneSearch\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_nSchema_4\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_nSchema_4\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_nSchema_4\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_nSchema_4\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_nSchema_4\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_nSchema_4\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_nSchema_4\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_nSchema_5\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_nSchema_5\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_nSchema_5\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_nSchema_5\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_nSchema_5\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_nSchema_5\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_nSchema_5\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_nSchema_6\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_nSchema_6\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_nSchema_6\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_nSchema_6\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_nSchema_6\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_nSchema_6\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_nSchema_6\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_nSchema_7\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_nSchema_7\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_nSchema_7\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_nSchema_7\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_nSchema_7\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_nSchema_7\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_nSchema_7\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_nSchema_8\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_nSchema_8\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_nSchema_8\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_nSchema_8\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_nSchema_8\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_nSchema_8\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_nSchema_8\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_nSchema_9\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_nSchema_9\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_nSchema_9\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_nSchema_9\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_nSchema_9\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_nSchema_9\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_nSchema_9\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\windowDock_nSchema_4\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\windowDock_nSchema_4\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\windowDock_nSchema_4\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\windowDock_nSchema_4\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\windowDock_nSchema_5\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\windowDock_nSchema_5\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\windowDock_nSchema_5\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\windowDock_nSchema_5\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\windowDock_nSchema_6\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\windowDock_nSchema_6\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\windowDock_nSchema_6\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\windowDock_nSchema_6\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\windowDock_nSchema_7\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\windowDock_nSchema_7\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\windowDock_nSchema_7\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\windowDock_nSchema_7\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\windowDock_nSchema_8\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\windowDock_nSchema_8\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\windowDock_nSchema_8\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\windowDock_nSchema_8\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\windowDock_nSchema_9\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\windowDock_nSchema_9\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\windowDock_nSchema_9\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\windowDock_nSchema_9\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_OneSearch\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_nSchema_4\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_nSchema_4\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_nSchema_4\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_nSchema_4\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_nSchema_4\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_nSchema_4\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_nSchema_4\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_nSchema_5\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_nSchema_5\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_nSchema_5\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_nSchema_5\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_nSchema_5\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_nSchema_5\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_nSchema_5\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_nSchema_6\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_nSchema_6\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_nSchema_6\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_nSchema_6\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_nSchema_6\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_nSchema_6\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_nSchema_6\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_nSchema_7\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_nSchema_7\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_nSchema_7\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_nSchema_7\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_nSchema_7\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_nSchema_7\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_nSchema_7\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_nSchema_8\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_nSchema_8\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_nSchema_8\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_nSchema_8\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_nSchema_8\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_nSchema_8\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_nSchema_8\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_nSchema_9\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_nSchema_9\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_nSchema_9\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_nSchema_9\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_nSchema_9\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_nSchema_9\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_nSchema_9\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\windowDock_OneSearch\isNestedWindow=1 +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\windowDock_OneSearch\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\windowDock_OneSearch\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\windowDock_nWave_3\isNestedWindow=1 +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\windowDock_nWave_3\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\windowDock_nWave_3\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\windowDock_nWave_3\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\windowDock_nWave_3\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_4\isNestedWindow=1 +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_4\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_4\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_4\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_4\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_4\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_4\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_5\isNestedWindow=1 +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_5\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_5\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_5\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_5\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_5\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_5\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_6\isNestedWindow=1 +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_6\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_6\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_6\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_6\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_6\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_6\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_7\isNestedWindow=1 +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_7\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_7\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_7\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_7\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_7\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_7\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_8\isNestedWindow=1 +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_8\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_8\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_8\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_8\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_8\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_8\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_9\isNestedWindow=1 +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_9\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_9\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_9\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_9\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_9\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\qBaseDockWidgetGroup\windowDock_nSchema_9\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\ProductVersion=201809 +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\Layout="@ByteArray(\0\0\0\xff\0\0\0\0\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x3\xb3\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x2\\\0\0\0\x89\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfc\0\0\x2\x62\0\0\0\xb7\0\0\0\xae\0\xff\xff\xff\xfa\0\0\0\x1\x1\0\0\0\x2\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\0\0k\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0h\0\x65\0r\0i\0t\0\x61\0n\0\x63\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xae\0\xff\xff\xff\xfc\0\0\x3\x1f\0\0\x6\xe1\0\0\0\xbf\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\b\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\x1\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x34\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x35\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x36\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x37\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x32\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x38\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0S\0\x63\0h\0\x65\0m\0\x61\0_\0\x39\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xbf\0\xff\xff\xff\0\0\0\x3\0\0\n\0\0\0\x1\x32\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\n\0\0\0\x2,\0\xff\xff\xff\xfa\0\0\0\x3\x1\0\0\0\x4\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\x1\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x33\x1\0\0\0\0\xff\xff\xff\xff\0\0\x1[\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x33\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x34\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\isNestedWindow=0 +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\size=@Size(2560 1337) +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\geometry_x=-1 +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\geometry_y=27 +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\geometry_width=2560 +Verdi_1\qBaseWindowRestoreStateGroup\layout_to_restore\geometry_height=1337 +Verdi_1\qBaseWindowNextStateGroup\14\qBaseDockWidgetGroup\windowDock_nSchema_4\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\14\qBaseDockWidgetGroup\windowDock_nSchema_4\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\14\qBaseDockWidgetGroup\windowDock_nSchema_4\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\14\qBaseDockWidgetGroup\windowDock_nSchema_4\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\14\qBaseDockWidgetGroup\windowDock_nSchema_5\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\14\qBaseDockWidgetGroup\windowDock_nSchema_5\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\14\qBaseDockWidgetGroup\windowDock_nSchema_5\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\14\qBaseDockWidgetGroup\windowDock_nSchema_5\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\14\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\14\qBaseDockWidgetGroup\windowDock_nSchema_6\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\14\qBaseDockWidgetGroup\windowDock_nSchema_6\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\14\qBaseDockWidgetGroup\windowDock_nSchema_6\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\14\qBaseDockWidgetGroup\windowDock_nSchema_6\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\14\qBaseDockWidgetGroup\windowDock_nSchema_7\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\14\qBaseDockWidgetGroup\windowDock_nSchema_7\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\14\qBaseDockWidgetGroup\windowDock_nSchema_7\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\14\qBaseDockWidgetGroup\windowDock_nSchema_7\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\14\qBaseDockWidgetGroup\windowDock_nSchema_8\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\14\qBaseDockWidgetGroup\windowDock_nSchema_8\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\14\qBaseDockWidgetGroup\windowDock_nSchema_8\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\14\qBaseDockWidgetGroup\windowDock_nSchema_8\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\14\qBaseDockWidgetGroup\windowDock_nSchema_9\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\14\qBaseDockWidgetGroup\windowDock_nSchema_9\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\14\qBaseDockWidgetGroup\windowDock_nSchema_9\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\14\qBaseDockWidgetGroup\windowDock_nSchema_9\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nWave_3\geometry=@ByteArray(\x1\xd9\xd0\xcb\0\x1\0\0\xff\xff\xff\x8a\0\0\0v\0\0\t\x89\0\0\x5\x61\xff\xff\xff\x8a\0\0\0v\0\0\t\x89\0\0\x5\x61\0\0\0\0\0\0) +Verdi_1\qBaseWindowNextStateGroup\15\qBaseDockWidgetGroup\windowDock_nWave_3\geometry=@ByteArray(\x1\xd9\xd0\xcb\0\x1\0\0\xff\xff\xff\x8a\0\0\0v\0\0\t\x89\0\0\x5\x61\xff\xff\xff\x8a\0\0\0v\0\0\t\x89\0\0\x5\x61\0\0\0\0\0\0) +Verdi_1\qBaseWindowNextStateGroup\15\qBaseDockWidgetGroup\windowDock_nSchema_5\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\15\qBaseDockWidgetGroup\windowDock_nSchema_5\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\15\qBaseDockWidgetGroup\windowDock_nSchema_5\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\15\qBaseDockWidgetGroup\windowDock_nSchema_5\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\15\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\15\qBaseDockWidgetGroup\windowDock_nSchema_6\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\15\qBaseDockWidgetGroup\windowDock_nSchema_6\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\15\qBaseDockWidgetGroup\windowDock_nSchema_6\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\15\qBaseDockWidgetGroup\windowDock_nSchema_6\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\15\qBaseDockWidgetGroup\windowDock_nSchema_7\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\15\qBaseDockWidgetGroup\windowDock_nSchema_7\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\15\qBaseDockWidgetGroup\windowDock_nSchema_7\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\15\qBaseDockWidgetGroup\windowDock_nSchema_7\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\15\qBaseDockWidgetGroup\windowDock_nSchema_8\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\15\qBaseDockWidgetGroup\windowDock_nSchema_8\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\15\qBaseDockWidgetGroup\windowDock_nSchema_8\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\15\qBaseDockWidgetGroup\windowDock_nSchema_8\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\15\qBaseDockWidgetGroup\windowDock_nSchema_9\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\15\qBaseDockWidgetGroup\windowDock_nSchema_9\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\15\qBaseDockWidgetGroup\windowDock_nSchema_9\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\15\qBaseDockWidgetGroup\windowDock_nSchema_9\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\16\qBaseDockWidgetGroup\windowDock_nWave_3\geometry=@ByteArray(\x1\xd9\xd0\xcb\0\x1\0\0\xff\xff\xff\x8a\0\0\0v\0\0\t\x89\0\0\x5\x61\xff\xff\xff\x8a\0\0\0v\0\0\t\x89\0\0\x5\x61\0\0\0\0\0\0) +Verdi_1\qBaseWindowNextStateGroup\16\qBaseDockWidgetGroup\windowDock_nSchema_5\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\16\qBaseDockWidgetGroup\windowDock_nSchema_5\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\16\qBaseDockWidgetGroup\windowDock_nSchema_5\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\16\qBaseDockWidgetGroup\windowDock_nSchema_5\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\16\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\16\qBaseDockWidgetGroup\windowDock_nSchema_6\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\16\qBaseDockWidgetGroup\windowDock_nSchema_6\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\16\qBaseDockWidgetGroup\windowDock_nSchema_6\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\16\qBaseDockWidgetGroup\windowDock_nSchema_6\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\16\qBaseDockWidgetGroup\windowDock_nSchema_7\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\16\qBaseDockWidgetGroup\windowDock_nSchema_7\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\16\qBaseDockWidgetGroup\windowDock_nSchema_7\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\16\qBaseDockWidgetGroup\windowDock_nSchema_7\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\16\qBaseDockWidgetGroup\windowDock_nSchema_8\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\16\qBaseDockWidgetGroup\windowDock_nSchema_8\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\16\qBaseDockWidgetGroup\windowDock_nSchema_8\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\16\qBaseDockWidgetGroup\windowDock_nSchema_8\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\16\qBaseDockWidgetGroup\windowDock_nSchema_9\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\16\qBaseDockWidgetGroup\windowDock_nSchema_9\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\16\qBaseDockWidgetGroup\windowDock_nSchema_9\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\16\qBaseDockWidgetGroup\windowDock_nSchema_9\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\17\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeMax=1 +Verdi_1\qBaseWindowNextStateGroup\17\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\17\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\17\qBaseDockWidgetGroup\windowDock_nWave_3\geometry=@ByteArray(\x1\xd9\xd0\xcb\0\x1\0\0\xff\xff\xff\xf6\0\0\0Z\0\0\n\t\0\0\x5|\0\0\0\0\0\0\0\x87\0\0\t\xff\0\0\x5r\0\0\0\0\0\0) +Verdi_1\qBaseWindowNextStateGroup\17\qBaseDockWidgetGroup\windowDock_nSchema_5\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\17\qBaseDockWidgetGroup\windowDock_nSchema_5\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\17\qBaseDockWidgetGroup\windowDock_nSchema_5\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\17\qBaseDockWidgetGroup\windowDock_nSchema_5\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\17\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\17\qBaseDockWidgetGroup\windowDock_nSchema_6\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\17\qBaseDockWidgetGroup\windowDock_nSchema_6\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\17\qBaseDockWidgetGroup\windowDock_nSchema_6\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\17\qBaseDockWidgetGroup\windowDock_nSchema_6\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\17\qBaseDockWidgetGroup\windowDock_nSchema_7\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\17\qBaseDockWidgetGroup\windowDock_nSchema_7\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\17\qBaseDockWidgetGroup\windowDock_nSchema_7\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\17\qBaseDockWidgetGroup\windowDock_nSchema_7\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\17\qBaseDockWidgetGroup\windowDock_nSchema_8\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\17\qBaseDockWidgetGroup\windowDock_nSchema_8\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\17\qBaseDockWidgetGroup\windowDock_nSchema_8\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\17\qBaseDockWidgetGroup\windowDock_nSchema_8\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\17\qBaseDockWidgetGroup\windowDock_nSchema_9\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\17\qBaseDockWidgetGroup\windowDock_nSchema_9\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\17\qBaseDockWidgetGroup\windowDock_nSchema_9\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\17\qBaseDockWidgetGroup\windowDock_nSchema_9\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\18\qBaseDockWidgetGroup\windowDock_nWave_3\geometry=@ByteArray(\x1\xd9\xd0\xcb\0\x1\0\0\xff\xff\xff\xf6\0\0\0Z\0\0\n\t\0\0\x5|\0\0\0\0\0\0\0\x87\0\0\t\xff\0\0\x5r\0\0\0\0\0\0) +Verdi_1\qBaseWindowNextStateGroup\18\qBaseDockWidgetGroup\windowDock_nSchema_5\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\18\qBaseDockWidgetGroup\windowDock_nSchema_5\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\18\qBaseDockWidgetGroup\windowDock_nSchema_5\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\18\qBaseDockWidgetGroup\windowDock_nSchema_5\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\18\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\18\qBaseDockWidgetGroup\windowDock_nSchema_6\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\18\qBaseDockWidgetGroup\windowDock_nSchema_6\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\18\qBaseDockWidgetGroup\windowDock_nSchema_6\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\18\qBaseDockWidgetGroup\windowDock_nSchema_6\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\18\qBaseDockWidgetGroup\windowDock_nSchema_7\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\18\qBaseDockWidgetGroup\windowDock_nSchema_7\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\18\qBaseDockWidgetGroup\windowDock_nSchema_7\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\18\qBaseDockWidgetGroup\windowDock_nSchema_7\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\18\qBaseDockWidgetGroup\windowDock_nSchema_8\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\18\qBaseDockWidgetGroup\windowDock_nSchema_8\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\18\qBaseDockWidgetGroup\windowDock_nSchema_8\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\18\qBaseDockWidgetGroup\windowDock_nSchema_8\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\18\qBaseDockWidgetGroup\windowDock_nSchema_9\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\18\qBaseDockWidgetGroup\windowDock_nSchema_9\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\18\qBaseDockWidgetGroup\windowDock_nSchema_9\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\18\qBaseDockWidgetGroup\windowDock_nSchema_9\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\19\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeMax=1 +Verdi_1\qBaseWindowNextStateGroup\19\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\19\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\19\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeMax=1 +Verdi_1\qBaseWindowNextStateGroup\19\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\19\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\19\qBaseDockWidgetGroup\windowDock_nWave_3\geometry=@ByteArray(\x1\xd9\xd0\xcb\0\x1\0\0\xff\xff\xff\xf6\0\0\0Z\0\0\n\t\0\0\x5|\0\0\0\0\0\0\0\x87\0\0\t\xff\0\0\x5r\0\0\0\0\0\0) +Verdi_1\qBaseWindowNextStateGroup\19\qBaseDockWidgetGroup\windowDock_nSchema_5\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\19\qBaseDockWidgetGroup\windowDock_nSchema_5\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\19\qBaseDockWidgetGroup\windowDock_nSchema_5\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\19\qBaseDockWidgetGroup\windowDock_nSchema_5\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\19\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\19\qBaseDockWidgetGroup\windowDock_nSchema_6\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\19\qBaseDockWidgetGroup\windowDock_nSchema_6\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\19\qBaseDockWidgetGroup\windowDock_nSchema_6\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\19\qBaseDockWidgetGroup\windowDock_nSchema_6\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\19\qBaseDockWidgetGroup\windowDock_nSchema_7\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\19\qBaseDockWidgetGroup\windowDock_nSchema_7\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\19\qBaseDockWidgetGroup\windowDock_nSchema_7\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\19\qBaseDockWidgetGroup\windowDock_nSchema_7\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\19\qBaseDockWidgetGroup\windowDock_nSchema_8\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\19\qBaseDockWidgetGroup\windowDock_nSchema_8\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\19\qBaseDockWidgetGroup\windowDock_nSchema_8\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\19\qBaseDockWidgetGroup\windowDock_nSchema_8\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\19\qBaseDockWidgetGroup\windowDock_nSchema_9\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\19\qBaseDockWidgetGroup\windowDock_nSchema_9\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\19\qBaseDockWidgetGroup\windowDock_nSchema_9\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\19\qBaseDockWidgetGroup\windowDock_nSchema_9\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\19\qBaseDockWidgetGroup\windowDock_nSchema_10\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\19\qBaseDockWidgetGroup\windowDock_nSchema_10\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\19\qBaseDockWidgetGroup\windowDock_nSchema_10\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\19\qBaseDockWidgetGroup\windowDock_nSchema_10\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\19\qBaseDockWidgetGroup\windowDock_nSchema_10\qBaseWindowBeMax=1 +Verdi_1\qBaseWindowNextStateGroup\19\qBaseDockWidgetGroup\windowDock_nSchema_10\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\19\qBaseDockWidgetGroup\windowDock_nSchema_10\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\windowDock_nWave_3\geometry=@ByteArray(\x1\xd9\xd0\xcb\0\x1\0\0\xff\xff\xff\xf6\0\0\0Z\0\0\n\t\0\0\x5|\0\0\0\0\0\0\0\x87\0\0\t\xff\0\0\x5r\0\0\0\0\0\0) +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\windowDock_nSchema_5\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\windowDock_nSchema_5\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\windowDock_nSchema_5\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\windowDock_nSchema_5\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\windowDock_nSchema_6\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\windowDock_nSchema_6\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\windowDock_nSchema_6\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\windowDock_nSchema_6\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\windowDock_nSchema_7\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\windowDock_nSchema_7\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\windowDock_nSchema_7\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\windowDock_nSchema_7\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\windowDock_nSchema_8\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\windowDock_nSchema_8\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\windowDock_nSchema_8\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\windowDock_nSchema_8\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\windowDock_nSchema_9\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\windowDock_nSchema_9\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\windowDock_nSchema_9\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\windowDock_nSchema_9\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\windowDock_nSchema_10\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\windowDock_nSchema_10\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\windowDock_nSchema_10\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\windowDock_nSchema_10\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\windowDock_nSchema_10\qBaseWindowBeMax=1 +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\windowDock_nSchema_10\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\20\qBaseDockWidgetGroup\windowDock_nSchema_10\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeMax=1 +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeMax=1 +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeMax=1 +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\windowDock_OneSearch\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\windowDock_nWave_3\geometry=@ByteArray(\x1\xd9\xd0\xcb\0\x1\0\0\xff\xff\xff\xf6\0\0\0Z\0\0\n\t\0\0\x5|\0\0\0\0\0\0\0\x87\0\0\t\xff\0\0\x5r\0\0\0\0\0\0) +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\windowDock_nSchema_5\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\windowDock_nSchema_5\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\windowDock_nSchema_5\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\windowDock_nSchema_5\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\widgetDock_%3CInheritance%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\windowDock_nSchema_6\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\windowDock_nSchema_6\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\windowDock_nSchema_6\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\windowDock_nSchema_6\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\windowDock_nSchema_7\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\windowDock_nSchema_7\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\windowDock_nSchema_7\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\windowDock_nSchema_7\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\windowDock_nSchema_8\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\windowDock_nSchema_8\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\windowDock_nSchema_8\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\windowDock_nSchema_8\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\windowDock_nSchema_9\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\windowDock_nSchema_9\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\windowDock_nSchema_9\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\windowDock_nSchema_9\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\windowDock_nSchema_10\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\windowDock_nSchema_10\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\windowDock_nSchema_10\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\windowDock_nSchema_10\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\windowDock_nSchema_10\qBaseWindowBeMax=1 +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\windowDock_nSchema_10\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\windowDock_nSchema_10\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\windowDock_nSchema_11\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\windowDock_nSchema_11\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\windowDock_nSchema_11\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\windowDock_nSchema_11\PRESELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\windowDock_nSchema_11\qBaseWindowBeMax=1 +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\windowDock_nSchema_11\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\21\qBaseDockWidgetGroup\windowDock_nSchema_11\dockIsFloating=false + +[QwMainWindow] +window\Verdi_1\layout="@ByteArray(\0\0\0\xff\0\x3\x14Q\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x2\xcb\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x2\x8d\0\0\0\x89\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\xe9\0\0\0\xc6\0\0\0k\0\0\0k\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\x1\0\0\x2\x93\0\0\am\0\0\0k\0\xff\xff\xff\0\0\0\x3\0\0\n\0\0\0\x2\x1a\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\n\0\0\0\x2,\0\xff\xff\xff\xfa\0\0\0\x2\x1\0\0\0\x3\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\x1\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\x1-\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x33\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x34\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +window\Verdi_1\geometry=@ByteArray(\x1\xd9\xd0\xcb\0\x1\0\0\xff\xff\xff\xff\0\0\0\x1b\0\0\n\0\0\0\x5z\0\0\0\0\0\0\0\0\xff\xff\xff\xfe\xff\xff\xff\xfe\0\0\0\0\x2\0) +window\Verdi_1\menubar=true +window\Verdi_1\splitters\tbvConstrDbgSplitter\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x2\0\0\0\x8d\0\0\0\x8d\x1\0\0\0\x6\x1\0\0\0\x1) +window\Verdi_1\splitters\tbvConstrRerandSplitter\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x2\0\0\0G\0\0\0\x4\x1\0\0\0\x6\x1\0\0\0\x2) +window\Verdi_1\splitters\tbvConstrOriginSplitter\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x2\0\0\0!\0\0\0\x4\x1\0\0\0\x6\x1\0\0\0\x2) +window\Verdi_1\splitters\ThreadPane\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x2\0\0\0\x37\0\0\0\x37\x1\0\0\0\x6\x1\0\0\0\x2) +window\Verdi_1\splitters\tbvInteractiveSplitter\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x2\0\0\0\x1f\0\0\0\x1f\x1\0\0\0\x6\x1\0\0\0\x2) +window\Verdi_1\splitters\tbvVSimSplitter\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x2\0\0\0\x1f\0\0\0\x1f\x1\0\0\0\x6\x1\0\0\0\x2) +window\Verdi_1\splitters\tbvTBHSplitter\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x2\0\0\0-\0\0\0?\x1\0\0\0\x6\x1\0\0\0\x2) +window\nWave_2\layout="@ByteArray(\0\0\0\xff\0\x3\x14Q\xfd\0\0\0\0\0\0\n\0\0\0\x4\x9e\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x2\0\0\0\x2\0\0\0\f\0\0\0\x12\0W\0\x41\0V\0\x45\0_\0O\0P\0\x45\0N\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x12\0W\0\x41\0V\0\x45\0_\0\x45\0\x44\0I\0T\x1\0\0\0?\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x16\0W\0\x41\0V\0\x45\0_\0\x43\0U\0R\0S\0O\0R\x1\0\0\0\xb4\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x12\0W\0\x41\0V\0\x45\0_\0V\0I\0\x45\0W\x1\0\0\x2%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\"\0W\0\x41\0V\0\x45\0_\0S\0\x45\0\x41\0R\0\x43\0H\0_\0\x45\0V\0\x45\0N\0T\x1\0\0\x2\x7f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0W\0\x41\0V\0\x45\0_\0R\0\x45\0P\0L\0\x41\0Y\0_\0S\0I\0M\0\0\0\x5K\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x12\0W\0\x41\0V\0\x45\0_\0G\0O\0T\0O\x1\0\0\x3\x1b\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0W\0\x41\0V\0\x45\0_\0G\0O\0T\0O\0_\0N\0\x41\0M\0\x45\0\x44\0_\0M\0\x41\0R\0K\0\x45\0R\0\0\0\x5\xed\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0W\0\x41\0V\0\x45\0_\0T\0R\0\x41\0N\0S\0\x41\0\x43\0T\0I\0O\0N\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0W\0\x41\0V\0\x45\0_\0\x45\0X\0P\0L\0O\0R\0\x45\0_\0P\0R\0O\0P\0\x45\0R\0T\0Y\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0W\0\x41\0V\0\x45\0_\0\x46\0I\0N\0\x44\0_\0S\0I\0G\0N\0\x41\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x18\0W\0\x41\0V\0\x45\0_\0P\0R\0I\0M\0\x41\0R\0Y\0\0\0\x6\x1b\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x32\0S\0\x45\0L\0\x45\0\x43\0T\0I\0O\0N\0_\0M\0\x45\0S\0S\0\x41\0G\0\x45\0_\0T\0O\0O\0L\0\x42\0\x41\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +window\nWave_2\geometry=@ByteArray(\x1\xd9\xd0\xcb\0\x1\0\0\0\0\0\0\0\0\0\x1b\0\0\t\xff\0\0\x4\xea\0\0\0\0\0\0\0\x1b\0\0\t\xff\0\0\x4\xea\0\0\0\0\0\0) +window\nWave_2\menubar=true +window\nWave_2\splitters\splitter_5\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x83\x1\0\0\0\x1\0\0\0\0\x2) +window\nWave_2\splitters\splitter_2\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x2\0\0\0\xd8\0\0\t(\x1\0\0\0\x1\0\0\0\0\x1) +window\nWave_2\splitters\splitter\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x3\0\0\0?\0\0\0\x1\0\0\b\xe6\x1\0\0\0\x1\0\0\0\0\x1) +window\nWave_2\splitters\Pane_Upper\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x2\0\0\0\xd8\0\0\t%\x1\0\0\0\x1\0\0\0\0\x1) +window\nWave_2\splitters\splitter_3\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x2\0\0\0?\0\0\tW\x1\0\0\0\x1\0\0\0\0\x1) +window\nWave_2\splitters\wholeSplitter\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x3\0\0\0O\0\0\0\xa3\0\0\0\x4\x1\0\0\0\x6\x1\0\0\0\x1) +window\nWave_2\splitters\middleSplitter\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0\x4\x1\0\0\0\x6\x1\0\0\0\x2) +window\nMemory_3\layout=@ByteArray(\0\0\0\xff\0\x3\x14Q\xfd\0\0\0\0\0\0\x4\xfd\0\0\x1\xda\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x2\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0M\0\x45\0M\0_\0T\0O\0O\0L\0\x42\0\x41\0R\0_\0U\0P\0P\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x34\0N\0M\0\x45\0M\0_\0T\0O\0O\0L\0\x42\0\x41\0R\0_\0U\0P\0P\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0_\0\x32\x1\0\0\0?\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x34\0N\0M\0\x45\0M\0_\0T\0O\0O\0L\0\x42\0\x41\0R\0_\0U\0P\0P\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0_\0\x33\x1\0\0\x1\xd3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x34\0N\0M\0\x45\0M\0_\0T\0O\0O\0L\0\x42\0\x41\0R\0_\0L\0O\0W\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0_\0\x31\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0) +window\nMemory_3\geometry=@ByteArray(\x1\xd9\xd0\xcb\0\x1\0\0\0\0\0\0\0\0\0\x1b\0\0\x4\xfc\0\0\x2@\0\0\0\0\0\0\0\x1b\0\0\x4\xfc\0\0\x2@\0\0\0\0\0\0) +window\nMemory_3\menubar=true +window\nMemory_4\layout=@ByteArray(\0\0\0\xff\0\x3\x14Q\xfd\0\0\0\0\0\0\x4\xfd\0\0\x1\xda\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x2\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0M\0\x45\0M\0_\0T\0O\0O\0L\0\x42\0\x41\0R\0_\0U\0P\0P\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x34\0N\0M\0\x45\0M\0_\0T\0O\0O\0L\0\x42\0\x41\0R\0_\0U\0P\0P\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0_\0\x32\x1\0\0\0?\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x34\0N\0M\0\x45\0M\0_\0T\0O\0O\0L\0\x42\0\x41\0R\0_\0U\0P\0P\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0_\0\x33\x1\0\0\x1\xd3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x34\0N\0M\0\x45\0M\0_\0T\0O\0O\0L\0\x42\0\x41\0R\0_\0L\0O\0W\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0_\0\x31\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0) +window\nMemory_4\geometry=@ByteArray(\x1\xd9\xd0\xcb\0\x1\0\0\0\0\0\0\0\0\0\x1b\0\0\x4\xfc\0\0\x2@\0\0\0\0\0\0\0\x1b\0\0\x4\xfc\0\0\x2@\0\0\0\0\0\0) +window\nMemory_4\menubar=true + +[qBaseWindow_saveRestoreSession_group] +10=/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/digital_top/verdiLog/novas_autosave.ses + +[qDockerWindow_C] +Verdi_1\position.x=-1 +Verdi_1\position.y=27 +Verdi_1\width=2560 +Verdi_1\height=1337 + +[nWave_3_qBaseWindow_Be_Window_Group] +geometry_x=-118 +geometry_y=118 +geometry_width=2560 +geometry_height=1260 diff --git a/tb/digital_top/verdiLog/.diagnose.oneSearch b/tb/digital_top/verdiLog/.diagnose.oneSearch new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/verdiLog/ToNetlist.log b/tb/digital_top/verdiLog/ToNetlist.log new file mode 100644 index 0000000..e709d4f --- /dev/null +++ b/tb/digital_top/verdiLog/ToNetlist.log @@ -0,0 +1 @@ +Compiling Netlist: Failed to create net (slv[25].slave[0:95]) - Create operation net failed: bit range not inside declaration net diff --git a/tb/digital_top/verdiLog/compiler.log b/tb/digital_top/verdiLog/compiler.log new file mode 100644 index 0000000..cfa6b2e --- /dev/null +++ b/tb/digital_top/verdiLog/compiler.log @@ -0,0 +1,111 @@ +*design* DebussyLib (btIdent Verdi_O-2018.09-SP2) +Command arguments: + +define+verilog + -sverilog + -f files.f + ../../rtl/memory/sram_if.sv + ../../rtl/awg/awg_ctrl.v + ../../rtl/awg/awg_top.sv + ../../rtl/awg/codeword_decode.v + ../../rtl/awg/ctrl_regfile.v + ../../rtl/awg/param_lut.sv + ../../rtl/awg/modout_mux.v + ../../rtl/clk/intpll_regfile.v + ../../rtl/comm/sirv_gnrl_dffs.v + ../../rtl/comm/sirv_gnrl_xchecker.v + ../../rtl/dac_regfile/dac_regfile.v + ../../rtl/debug/debug_sample.sv + ../../rtl/debug/debug_top.sv + ../../rtl/define/chip_define.v + ../../rtl/define/chip_undefine.v + ../../rtl/memory/dpram.v + ../../rtl/memory/dpram_model.v + ../../rtl/memory/sram_dmux.sv + ../../rtl/memory/tsdn28hpcpuhdb128x128m4mw_170a_ffg0p99v0c.v + ../../rtl/memory/tsdn28hpcpuhdb4096x32m4mw_170a_ffg0p99v0c.v + ../../rtl/memory/tsdn28hpcpuhdb4096x32m4mwr_170a_ffg0p99v0c.v + ../../rtl/memory/tsdn28hpcpuhdb64x32m4mw_170a_ffg0p99v0c.v + ../../rtl/memory/tsmc_dpram.v + ../../rtl/modem/ampmod.v + ../../rtl/modem/baisset.v + ../../rtl/modem/freqmod.v + ../../rtl/nco/coef_c.v + ../../rtl/nco/coef_s.v + ../../rtl/nco/cos_op.v + ../../rtl/nco/nco.v + ../../rtl/nco/nco_ch1.v + ../../rtl/nco/p_nco.v + ../../rtl/nco/p_nco_ch1.v + ../../rtl/nco/ph2amp.v + ../../rtl/nco/pipe_acc_48bit.v + ../../rtl/nco/pipe_add_48bit.v + ../../rtl/nco/sin_op.v + ../../rtl/perips/DW03_updn_ctr.v + ../../rtl/perips/mcu_regfile.sv + ../../rtl/perips/qbmcu_busdecoder.v + ../../rtl/qubitmcu/qbmcu.v + ../../rtl/qubitmcu/qbmcu_datalock.v + ../../rtl/qubitmcu/qbmcu_decode.v + ../../rtl/qubitmcu/qbmcu_defines.v + ../../rtl/qubitmcu/qbmcu_exu.v + ../../rtl/qubitmcu/qbmcu_exu_alu.v + ../../rtl/qubitmcu/qbmcu_exu_bjp.v + ../../rtl/qubitmcu/qbmcu_exu_dpath.v + ../../rtl/qubitmcu/qbmcu_exu_ext.v + ../../rtl/qubitmcu/qbmcu_exu_lsuagu.v + ../../rtl/qubitmcu/qbmcu_fsm.v + ../../rtl/qubitmcu/qbmcu_ifu.v + ../../rtl/qubitmcu/qbmcu_regfile.v + ../../rtl/qubitmcu/qbmcu_undefines.v + ../../rtl/qubitmcu/qbmcu_wbck.v + ../../rtl/rstgen/rst_gen_unit.v + ../../rtl/rstgen/rst_sync.v + ../../rtl/spi/spi_bus_decoder.sv + ../../rtl/spi/spi_pll.v + ../../rtl/spi/spi_slave.v + ../../rtl/spi/spi_sys.v + ../../rtl/sync/sync_buf.sv + ../../rtl/system_regfile/system_regfile.v + ../../rtl/top/channel_top.sv + ../../rtl/top/digital_top.sv + ../../rtl/xy_dsp/dacif/dacif.v + ../../rtl/xy_dsp/dsp_top/xy_dsp.v + ../../rtl/xy_dsp/duc/duc_hb1_pipe_shift.v + ../../rtl/xy_dsp/duc/duc_hb1_top.v + ../../rtl/xy_dsp/duc/duc_hb2_pipe_shift.v + ../../rtl/xy_dsp/duc/duc_hb2_top_s.v + ../../rtl/xy_dsp/duc/duc_hb3_pipe_shift.v + ../../rtl/xy_dsp/duc/duc_hb3_top_s2.v + ../../rtl/xy_dsp/duc/duc_hb4_pipe_shift.v + ../../rtl/xy_dsp/duc/duc_hb4_top_s3.v + ../../rtl/xy_dsp/duc/duc4.v + ../../rtl/xy_dsp/qam/qam_top.v + ../../rtl/xy_dsp/qam/ssb.v + ../../rtl/z_dsp/diff.v + ../../rtl/z_dsp/IIR_Filter.v + ../../rtl/z_dsp/lsdacif.v + ../../rtl/z_dsp/MeanIntp.v + ../../rtl/z_dsp/MeanIntp_s1.v + ../../rtl/z_dsp/MeanIntp2.v + ../../rtl/z_dsp/MeanIntp4_top.v + ../../rtl/z_dsp/mult_C.v + ../../rtl/z_dsp/TailCorr_top.v + ../../rtl/z_dsp/z_data_mux.v + ../../rtl/z_dsp/z_dsp.v + ../../sim/digital_top/TB.sv + ../../sim/digital_top/DW_mult_pipe.v + ../../sim/digital_top/DW01_addsub.v + ../../sim/digital_top/DW02_mult.v + ../../sim/digital_top/clk_gen.v + ../../sim/digital_top/spi_if.sv + -top + TB + +Highest level modules: +sirv_gnrl_dffl +sirv_gnrl_ltch +tsdn28hpcpuhdb4096x32m4mw_170a +TB +DW01_addsub + +Total 0 error(s), 0 warning(s) diff --git a/tb/digital_top/verdiLog/coredump b/tb/digital_top/verdiLog/coredump new file mode 100644 index 0000000..1616df7 --- /dev/null +++ b/tb/digital_top/verdiLog/coredump @@ -0,0 +1,443 @@ +91158: /home/synopsys/verdi/Verdi_O-2018.09-SP2/platform/LINUXAMD64/bin/Novas -sverilog -f files.f -top TB -nologo +0000000000400000 182584K r-x-- novas +000000000b84d000 444K r-x-- novas +000000000b8bc000 12544K rwx-- novas +000000000c4fc000 81756K rwx-- [ anon ] +0000000011ebc000 215860K rwx-- [ anon ] +00007fc4e0000000 8988K rwx-- [ anon ] +00007fc4e08c7000 56548K ----- [ anon ] +00007fc4e4000000 13896K rwx-- [ anon ] +00007fc4e4d92000 51640K ----- [ anon ] +00007fc4e8000000 65200K rwx-- [ anon ] +00007fc4ebfac000 336K ----- [ anon ] +00007fc4ec000000 5560K rwx-- [ anon ] +00007fc4ec56e000 59976K ----- [ anon ] +00007fc4f0000000 6384K rwx-- [ anon ] +00007fc4f063c000 59152K ----- [ anon ] +00007fc4f4ff8000 4K ----- [ anon ] +00007fc4f4ff9000 6144K rwx-- [ anon ] +00007fc4f55f9000 4K ----- [ anon ] +00007fc4f55fa000 6144K rwx-- [ anon ] +00007fc4f5bfa000 4K ----- [ anon ] +00007fc4f5bfb000 6144K rwx-- [ anon ] +00007fc4f61fb000 4K ----- [ anon ] +00007fc4f61fc000 6144K rwx-- [ anon ] +00007fc4f67fc000 4K ----- [ anon ] +00007fc4f67fd000 6144K rwx-- [ anon ] +00007fc4f6dfd000 4K ----- [ anon ] +00007fc4f6dfe000 6144K rwx-- [ anon ] +00007fc4f73fe000 4K ----- [ anon ] +00007fc4f73ff000 6144K rwx-- [ anon ] +00007fc4f79ff000 4K ----- [ anon ] +00007fc4f7a00000 6144K rwx-- [ anon ] +00007fc4f8000000 132K rwx-- [ anon ] +00007fc4f8021000 65404K ----- [ anon ] +00007fc4fc000000 132K rwx-- [ anon ] +00007fc4fc021000 65404K ----- [ anon ] +00007fc500000000 292K rwx-- [ anon ] +00007fc500049000 65244K ----- [ anon ] +00007fc50440f000 4K ----- [ anon ] +00007fc504410000 6144K rwx-- [ anon ] +00007fc504a10000 4K ----- [ anon ] +00007fc504a11000 8192K rwx-- [ anon ] +00007fc505211000 4K ----- [ anon ] +00007fc505212000 8192K rwx-- [ anon ] +00007fc505a12000 4K ----- [ anon ] +00007fc505a13000 8192K rwx-- [ anon ] +00007fc506413000 4K ----- [ anon ] +00007fc506414000 6144K rwx-- [ anon ] +00007fc506a14000 4K ----- [ anon ] +00007fc506a15000 8192K rwx-- [ anon ] +00007fc507215000 396K r-x-- libtiff.so.3.9.4 +00007fc507278000 2044K ----- libtiff.so.3.9.4 +00007fc507477000 8K r-x-- libtiff.so.3.9.4 +00007fc507479000 4K rwx-- libtiff.so.3.9.4 +00007fc50747a000 24K r-x-- libqtiff.so +00007fc507480000 2048K ----- libqtiff.so +00007fc507680000 4K rwx-- libqtiff.so +00007fc507681000 16K r-x-- libqtga.so +00007fc507685000 2048K ----- libqtga.so +00007fc507885000 4K rwx-- libqtga.so +00007fc507886000 340K r-x-- libQtSvg.so.4.8.7 +00007fc5078db000 2048K ----- libQtSvg.so.4.8.7 +00007fc507adb000 8K r-x-- libQtSvg.so.4.8.7 +00007fc507add000 4K rwx-- libQtSvg.so.4.8.7 +00007fc507ade000 20K r-x-- libqsvg.so +00007fc507ae3000 2044K ----- libqsvg.so +00007fc507ce2000 4K rwx-- libqsvg.so +00007fc507ce3000 436K r-x-- libmng.so.1.0.0 +00007fc507d50000 2048K ----- libmng.so.1.0.0 +00007fc507f50000 12K r-x-- libmng.so.1.0.0 +00007fc507f53000 8K rwx-- libmng.so.1.0.0 +00007fc507f55000 20K r-x-- libqmng.so +00007fc507f5a000 2048K ----- libqmng.so +00007fc50815a000 4K rwx-- libqmng.so +00007fc50815b000 132K r-x-- libjpeg.so.62.0.0 +00007fc50817c000 2048K ----- libjpeg.so.62.0.0 +00007fc50837c000 4K rwx-- libjpeg.so.62.0.0 +00007fc50837d000 28K r-x-- libqjpeg.so +00007fc508384000 2044K ----- libqjpeg.so +00007fc508583000 4K rwx-- libqjpeg.so +00007fc508584000 24K r-x-- libqico.so +00007fc50858a000 2048K ----- libqico.so +00007fc50878a000 4K rwx-- libqico.so +00007fc50878b000 24K r-x-- libqgif.so +00007fc508791000 2048K ----- libqgif.so +00007fc508991000 4K rwx-- libqgif.so +00007fc508992000 92K r-x-- libelf-0.176.so +00007fc5089a9000 2044K ----- libelf-0.176.so +00007fc508ba8000 4K r-x-- libelf-0.176.so +00007fc508ba9000 4K rwx-- libelf-0.176.so +00007fc508baa000 16K r-x-- libattr.so.1.1.0 +00007fc508bae000 2044K ----- libattr.so.1.1.0 +00007fc508dad000 4K r-x-- libattr.so.1.1.0 +00007fc508dae000 4K rwx-- libattr.so.1.1.0 +00007fc508daf000 240K r-x-- libblkid.so.1.1.0 +00007fc508deb000 2044K ----- libblkid.so.1.1.0 +00007fc508fea000 12K r-x-- libblkid.so.1.1.0 +00007fc508fed000 4K rwx-- libblkid.so.1.1.0 +00007fc508fee000 4K rwx-- [ anon ] +00007fc508fef000 312K r-x-- libdw-0.176.so +00007fc50903d000 2048K ----- libdw-0.176.so +00007fc50923d000 8K r-x-- libdw-0.176.so +00007fc50923f000 4K rwx-- libdw-0.176.so +00007fc509240000 16K r-x-- libgpg-error.so.0.10.0 +00007fc509244000 2044K ----- libgpg-error.so.0.10.0 +00007fc509443000 4K r-x-- libgpg-error.so.0.10.0 +00007fc509444000 4K rwx-- libgpg-error.so.0.10.0 +00007fc509445000 500K r-x-- libgcrypt.so.11.8.2 +00007fc5094c2000 2044K ----- libgcrypt.so.11.8.2 +00007fc5096c1000 4K r-x-- libgcrypt.so.11.8.2 +00007fc5096c2000 12K rwx-- libgcrypt.so.11.8.2 +00007fc5096c5000 4K rwx-- [ anon ] +00007fc5096c6000 56K r-x-- liblz4.so.1.8.3 +00007fc5096d4000 2044K ----- liblz4.so.1.8.3 +00007fc5098d3000 4K r-x-- liblz4.so.1.8.3 +00007fc5098d4000 4K rwx-- liblz4.so.1.8.3 +00007fc5098d5000 148K r-x-- liblzma.so.5.2.2 +00007fc5098fa000 2044K ----- liblzma.so.5.2.2 +00007fc509af9000 4K r-x-- liblzma.so.5.2.2 +00007fc509afa000 4K rwx-- liblzma.so.5.2.2 +00007fc509afb000 16K r-x-- libcap.so.2.22 +00007fc509aff000 2044K ----- libcap.so.2.22 +00007fc509cfe000 4K r-x-- libcap.so.2.22 +00007fc509cff000 4K rwx-- libcap.so.2.22 +00007fc509d00000 256K r-x-- libmount.so.1.1.0 +00007fc509d40000 2048K ----- libmount.so.1.1.0 +00007fc509f40000 4K r-x-- libmount.so.1.1.0 +00007fc509f41000 4K rwx-- libmount.so.1.1.0 +00007fc509f42000 4K rwx-- [ anon ] +00007fc509f43000 88K r-x-- libresolv-2.17.so +00007fc509f59000 2048K ----- libresolv-2.17.so +00007fc50a159000 4K r-x-- libresolv-2.17.so +00007fc50a15a000 4K rwx-- libresolv-2.17.so +00007fc50a15b000 8K rwx-- [ anon ] +00007fc50a15d000 144K r-x-- libselinux.so.1 +00007fc50a181000 2044K ----- libselinux.so.1 +00007fc50a380000 4K r-x-- libselinux.so.1 +00007fc50a381000 4K rwx-- libselinux.so.1 +00007fc50a382000 8K rwx-- [ anon ] +00007fc50a384000 384K r-x-- libpcre.so.1.2.0 +00007fc50a3e4000 2048K ----- libpcre.so.1.2.0 +00007fc50a5e4000 4K r-x-- libpcre.so.1.2.0 +00007fc50a5e5000 4K rwx-- libpcre.so.1.2.0 +00007fc50a5e6000 12K r-x-- libgmodule-2.0.so.0.5600.1 +00007fc50a5e9000 2044K ----- libgmodule-2.0.so.0.5600.1 +00007fc50a7e8000 4K r-x-- libgmodule-2.0.so.0.5600.1 +00007fc50a7e9000 4K rwx-- libgmodule-2.0.so.0.5600.1 +00007fc50a7ea000 28K r-x-- libffi.so.6.0.1 +00007fc50a7f1000 2044K ----- libffi.so.6.0.1 +00007fc50a9f0000 4K r-x-- libffi.so.6.0.1 +00007fc50a9f1000 4K rwx-- libffi.so.6.0.1 +00007fc50a9f2000 188K r-x-- libsystemd.so.0.6.0 +00007fc50aa21000 2048K ----- libsystemd.so.0.6.0 +00007fc50ac21000 4K r-x-- libsystemd.so.0.6.0 +00007fc50ac22000 4K rwx-- libsystemd.so.0.6.0 +00007fc50ac23000 1104K r-x-- libglib-2.0.so.0.5600.1 +00007fc50ad37000 2044K ----- libglib-2.0.so.0.5600.1 +00007fc50af36000 4K r-x-- libglib-2.0.so.0.5600.1 +00007fc50af37000 4K rwx-- libglib-2.0.so.0.5600.1 +00007fc50af38000 4K rwx-- [ anon ] +00007fc50af39000 316K r-x-- libgobject-2.0.so.0.5600.1 +00007fc50af88000 2048K ----- libgobject-2.0.so.0.5600.1 +00007fc50b188000 4K r-x-- libgobject-2.0.so.0.5600.1 +00007fc50b189000 4K rwx-- libgobject-2.0.so.0.5600.1 +00007fc50b18a000 1624K r-x-- libgio-2.0.so.0.5600.1 +00007fc50b320000 2048K ----- libgio-2.0.so.0.5600.1 +00007fc50b520000 20K r-x-- libgio-2.0.so.0.5600.1 +00007fc50b525000 12K rwx-- libgio-2.0.so.0.5600.1 +00007fc50b528000 8K rwx-- [ anon ] +00007fc50b52a000 312K r-x-- libdbus-1.so.3.14.14 +00007fc50b578000 2044K ----- libdbus-1.so.3.14.14 +00007fc50b777000 4K r-x-- libdbus-1.so.3.14.14 +00007fc50b778000 4K rwx-- libdbus-1.so.3.14.14 +00007fc50b779000 4K rwx-- [ anon ] +00007fc50b77a000 152K r-x-- libdbus-glib-1.so.2.2.2 +00007fc50b7a0000 2048K ----- libdbus-glib-1.so.2.2.2 +00007fc50b9a0000 4K r-x-- libdbus-glib-1.so.2.2.2 +00007fc50b9a1000 4K rwx-- libdbus-glib-1.so.2.2.2 +00007fc50b9a2000 6520K r-x-- novas.rcc +00007fc50c000000 284K rwx-- [ anon ] +00007fc50c047000 65252K ----- [ anon ] +00007fc5101ba000 108K r-x-- LiberationMono-Regular.ttf +00007fc5101d5000 268K rwx-- [ anon ] +00007fc510226000 24K rwx-- [ anon ] +00007fc51022c000 140K r-x-- LiberationSans-Regular.ttf +00007fc51024f000 60K r-x-- VeraBd.ttf +00007fc51025e000 8K r-x-- libXinerama.so.1.0.0 +00007fc510260000 2044K ----- libXinerama.so.1.0.0 +00007fc51045f000 4K r-x-- libXinerama.so.1.0.0 +00007fc510460000 4K rwx-- libXinerama.so.1.0.0 +00007fc510461000 40K r-x-- libXrandr.so.2.2.0 +00007fc51046b000 2044K ----- libXrandr.so.2.2.0 +00007fc51066a000 4K r-x-- libXrandr.so.2.2.0 +00007fc51066b000 4K rwx-- libXrandr.so.2.2.0 +00007fc51066c000 16K rwx-- [ anon ] +00007fc510670000 40K r-x-- c0419bt_.pfb +00007fc51067a000 68K r-x-- Vera.ttf +00007fc51068b000 8K r-x-- UTF-16.so +00007fc51068d000 2048K ----- UTF-16.so +00007fc51088d000 4K r-x-- UTF-16.so +00007fc51088e000 4K rwx-- UTF-16.so +00007fc51088f000 4K ----- [ anon ] +00007fc510890000 8192K rwx-- [ anon ] +00007fc511090000 20K r-x-- libXfixes.so.3.1.0 +00007fc511095000 2044K ----- libXfixes.so.3.1.0 +00007fc511294000 4K r-x-- libXfixes.so.3.1.0 +00007fc511295000 4K rwx-- libXfixes.so.3.1.0 +00007fc511296000 36K r-x-- libXcursor.so.1.0.2 +00007fc51129f000 2048K ----- libXcursor.so.1.0.2 +00007fc51149f000 4K r-x-- libXcursor.so.1.0.2 +00007fc5114a0000 4K rwx-- libXcursor.so.1.0.2 +00007fc5114a1000 4K ----- [ anon ] +00007fc5114a2000 8192K rwx-- [ anon ] +00007fc511ca2000 4K ----- [ anon ] +00007fc511ca3000 8192K rwx-- [ anon ] +00007fc5124a3000 48K r-x-- libnss_files-2.17.so +00007fc5124af000 2044K ----- libnss_files-2.17.so +00007fc5126ae000 4K r-x-- libnss_files-2.17.so +00007fc5126af000 4K rwx-- libnss_files-2.17.so +00007fc5126b0000 1052K rwx-- [ anon ] +00007fc5127b7000 8K r-x-- libXau.so.6.0.0 +00007fc5127b9000 2048K ----- libXau.so.6.0.0 +00007fc5129b9000 4K r-x-- libXau.so.6.0.0 +00007fc5129ba000 4K rwx-- libXau.so.6.0.0 +00007fc5129bb000 16K r-x-- libuuid.so.1.3.0 +00007fc5129bf000 2044K ----- libuuid.so.1.3.0 +00007fc512bbe000 4K r-x-- libuuid.so.1.3.0 +00007fc512bbf000 4K rwx-- libuuid.so.1.3.0 +00007fc512bc0000 156K r-x-- libexpat.so.1.6.0 +00007fc512be7000 2048K ----- libexpat.so.1.6.0 +00007fc512de7000 8K r-x-- libexpat.so.1.6.0 +00007fc512de9000 4K rwx-- libexpat.so.1.6.0 +00007fc512dea000 156K r-x-- libxcb.so.1.1.0 +00007fc512e11000 2044K ----- libxcb.so.1.1.0 +00007fc513010000 4K r-x-- libxcb.so.1.1.0 +00007fc513011000 4K rwx-- libxcb.so.1.1.0 +00007fc513012000 36K r-x-- libXrender.so.1.3.0 +00007fc51301b000 2048K ----- libXrender.so.1.3.0 +00007fc51321b000 4K r-x-- libXrender.so.1.3.0 +00007fc51321c000 4K rwx-- libXrender.so.1.3.0 +00007fc51321d000 84K r-x-- libgcc_s.so.1 +00007fc513232000 2048K ----- libgcc_s.so.1 +00007fc513432000 4K rwx-- libgcc_s.so.1 +00007fc513433000 92K r-x-- libICE.so.6.3.0 +00007fc51344a000 2044K ----- libICE.so.6.3.0 +00007fc513649000 4K r-x-- libICE.so.6.3.0 +00007fc51364a000 4K rwx-- libICE.so.6.3.0 +00007fc51364b000 16K rwx-- [ anon ] +00007fc51364f000 28K r-x-- libSM.so.6.0.1 +00007fc513656000 2044K ----- libSM.so.6.0.1 +00007fc513855000 4K r-x-- libSM.so.6.0.1 +00007fc513856000 4K rwx-- libSM.so.6.0.1 +00007fc513857000 164K r-x-- libpng15.so.15.13.0 +00007fc513880000 2048K ----- libpng15.so.15.13.0 +00007fc513a80000 4K r-x-- libpng15.so.15.13.0 +00007fc513a81000 4K rwx-- libpng15.so.15.13.0 +00007fc513a82000 60K r-x-- libbz2.so.1.0.6 +00007fc513a91000 2044K ----- libbz2.so.1.0.6 +00007fc513c90000 4K r-x-- libbz2.so.1.0.6 +00007fc513c91000 4K rwx-- libbz2.so.1.0.6 +00007fc513c92000 84K r-x-- libz.so.1.2.7 +00007fc513ca7000 2044K ----- libz.so.1.2.7 +00007fc513ea6000 4K r-x-- libz.so.1.2.7 +00007fc513ea7000 4K rwx-- libz.so.1.2.7 +00007fc513ea8000 1808K r-x-- libc-2.17.so +00007fc51406c000 2044K ----- libc-2.17.so +00007fc51426b000 16K r-x-- libc-2.17.so +00007fc51426f000 8K rwx-- libc-2.17.so +00007fc514271000 20K rwx-- [ anon ] +00007fc514276000 1028K r-x-- libm-2.17.so +00007fc514377000 2044K ----- libm-2.17.so +00007fc514576000 4K r-x-- libm-2.17.so +00007fc514577000 4K rwx-- libm-2.17.so +00007fc514578000 152K r-x-- libpng12.so.0.50.0 +00007fc51459e000 2044K ----- libpng12.so.0.50.0 +00007fc51479d000 4K r-x-- libpng12.so.0.50.0 +00007fc51479e000 4K rwx-- libpng12.so.0.50.0 +00007fc51479f000 28K r-x-- librt-2.17.so +00007fc5147a6000 2044K ----- librt-2.17.so +00007fc5149a5000 4K r-x-- librt-2.17.so +00007fc5149a6000 4K rwx-- librt-2.17.so +00007fc5149a7000 92K r-x-- libpthread-2.17.so +00007fc5149be000 2044K ----- libpthread-2.17.so +00007fc514bbd000 4K r-x-- libpthread-2.17.so +00007fc514bbe000 4K rwx-- libpthread-2.17.so +00007fc514bbf000 16K rwx-- [ anon ] +00007fc514bc3000 40K r-x-- libnuma.so.1.0.0 +00007fc514bcd000 2048K ----- libnuma.so.1.0.0 +00007fc514dcd000 4K r-x-- libnuma.so.1.0.0 +00007fc514dce000 4K rwx-- libnuma.so.1.0.0 +00007fc514dcf000 92K r-x-- libnsl-2.17.so +00007fc514de6000 2044K ----- libnsl-2.17.so +00007fc514fe5000 4K r-x-- libnsl-2.17.so +00007fc514fe6000 4K rwx-- libnsl-2.17.so +00007fc514fe7000 8K rwx-- [ anon ] +00007fc514fe9000 256K r-x-- libfontconfig.so.1.11.1 +00007fc515029000 2044K ----- libfontconfig.so.1.11.1 +00007fc515228000 8K r-x-- libfontconfig.so.1.11.1 +00007fc51522a000 4K rwx-- libfontconfig.so.1.11.1 +00007fc51522b000 68K r-x-- libXext.so.6.4.0 +00007fc51523c000 2044K ----- libXext.so.6.4.0 +00007fc51543b000 4K r-x-- libXext.so.6.4.0 +00007fc51543c000 4K rwx-- libXext.so.6.4.0 +00007fc51543d000 1248K r-x-- libX11.so.6.3.0 +00007fc515575000 2048K ----- libX11.so.6.3.0 +00007fc515775000 4K r-x-- libX11.so.6.3.0 +00007fc515776000 20K rwx-- libX11.so.6.3.0 +00007fc51577b000 96K r-x-- libXmu.so.6.2.0 +00007fc515793000 2048K ----- libXmu.so.6.2.0 +00007fc515993000 4K r-x-- libXmu.so.6.2.0 +00007fc515994000 4K rwx-- libXmu.so.6.2.0 +00007fc515995000 4K rwx-- [ anon ] +00007fc515996000 388K r-x-- libXt.so.6.0.0 +00007fc5159f7000 2044K ----- libXt.so.6.0.0 +00007fc515bf6000 4K r-x-- libXt.so.6.0.0 +00007fc515bf7000 20K rwx-- libXt.so.6.0.0 +00007fc515bfc000 4K rwx-- [ anon ] +00007fc515bfd000 84K r-x-- libXft.so.2.3.2 +00007fc515c12000 2044K ----- libXft.so.2.3.2 +00007fc515e11000 4K r-x-- libXft.so.2.3.2 +00007fc515e12000 4K rwx-- libXft.so.2.3.2 +00007fc515e13000 8K r-x-- libXss.so.1.0.0 +00007fc515e15000 2048K ----- libXss.so.1.0.0 +00007fc516015000 4K r-x-- libXss.so.1.0.0 +00007fc516016000 4K rwx-- libXss.so.1.0.0 +00007fc516017000 1476K r-x-- libstdc++.so.6 +00007fc516188000 2048K ----- libstdc++.so.6 +00007fc516388000 40K r-x-- libstdc++.so.6 +00007fc516392000 8K rwx-- libstdc++.so.6 +00007fc516394000 16K rwx-- [ anon ] +00007fc516398000 1688K r-x-- libsimprofile_verdi.so +00007fc51653e000 2044K ----- libsimprofile_verdi.so +00007fc51673d000 52K r-x-- libsimprofile_verdi.so +00007fc51674a000 4K rwx-- libsimprofile_verdi.so +00007fc51674b000 20K rwx-- [ anon ] +00007fc516750000 208K r-x-- libQtSql.so.4.8.5 +00007fc516784000 2044K ----- libQtSql.so.4.8.5 +00007fc516983000 12K rwx-- libQtSql.so.4.8.5 +00007fc516986000 2564K r-x-- libQt3Support.so.4.8.5 +00007fc516c07000 2048K ----- libQt3Support.so.4.8.5 +00007fc516e07000 124K rwx-- libQt3Support.so.4.8.5 +00007fc516e26000 1048K r-x-- libQtNetwork.so.4.8.5 +00007fc516f2c000 2044K ----- libQtNetwork.so.4.8.5 +00007fc51712b000 36K rwx-- libQtNetwork.so.4.8.5 +00007fc517134000 21820K r-x-- libQtWebKit.so.4.9.4 +00007fc518683000 2048K ----- libQtWebKit.so.4.9.4 +00007fc518883000 1632K rwx-- libQtWebKit.so.4.9.4 +00007fc518a1b000 168K rwx-- [ anon ] +00007fc518a45000 224K r-x-- libQtXml.so.4.8.5 +00007fc518a7d000 2044K ----- libQtXml.so.4.8.5 +00007fc518c7c000 12K rwx-- libQtXml.so.4.8.5 +00007fc518c7f000 2600K r-x-- libQtCore.so.4.8.5 +00007fc518f09000 2044K ----- libQtCore.so.4.8.5 +00007fc519108000 60K rwx-- libQtCore.so.4.8.5 +00007fc519117000 4K rwx-- [ anon ] +00007fc519118000 9524K r-x-- libQtGui.so.4.8.5 +00007fc519a65000 2044K ----- libQtGui.so.4.8.5 +00007fc519c64000 340K rwx-- libQtGui.so.4.8.5 +00007fc519cb9000 12K rwx-- [ anon ] +00007fc519cbc000 84K r-x-- libQtSolutions_MotifExtension-2.7.so.1.0.0 +00007fc519cd1000 2044K ----- libQtSolutions_MotifExtension-2.7.so.1.0.0 +00007fc519ed0000 8K rwx-- libQtSolutions_MotifExtension-2.7.so.1.0.0 +00007fc519ed2000 732K r-x-- libfreetype.so.6.14.0 +00007fc519f89000 2048K ----- libfreetype.so.6.14.0 +00007fc51a189000 28K r-x-- libfreetype.so.6.14.0 +00007fc51a190000 4K rwx-- libfreetype.so.6.14.0 +00007fc51a191000 1028K r-x-- libvfs.so +00007fc51a292000 2044K ----- libvfs.so +00007fc51a491000 28K r-x-- libvfs.so +00007fc51a498000 4K rwx-- libvfs.so +00007fc51a499000 20K rwx-- [ anon ] +00007fc51a49e000 8K r-x-- libdl-2.17.so +00007fc51a4a0000 2048K ----- libdl-2.17.so +00007fc51a6a0000 4K r-x-- libdl-2.17.so +00007fc51a6a1000 4K rwx-- libdl-2.17.so +00007fc51a6a2000 136K r-x-- ld-2.17.so +00007fc51a6c4000 48K rwx-- [ anon ] +00007fc51a6d0000 20K r-x-- access.rcc +00007fc51a6d5000 12K r-xs- 25052d8b-0a4d-4120-b7c0-49c39777638f-le64.cache-7 +00007fc51a6d8000 8K r-xs- b9d6a7e6-d9c6-447f-9d5c-078d24e10a55-le64.cache-7 +00007fc51a6da000 8K r-xs- b4ff5cf7-9766-47f8-9078-1b2fb59dfdc4-le64.cache-7 +00007fc51a6dc000 96K r-xs- 507eb2c7-aa72-4556-a723-82b3d0e61db2-le64.cache-7 +00007fc51a6f4000 44K r-xs- 955347f6-7d91-4f8c-879e-e31b12a49edb-le64.cache-7 +00007fc51a6ff000 8K r-xs- edf143a7-6212-4f3c-baa3-93dff078c158-le64.cache-7 +00007fc51a701000 12K r-xs- 4bf7f7d7-7d6d-46b5-ba19-b338022a553f-le64.cache-7 +00007fc51a704000 4K r-xs- 0f81de0c-45f3-457e-9a1a-20656baf05b3-le64.cache-7 +00007fc51a705000 4K r-xs- 84d76674-e845-4fdb-84e5-08f7fa5bfa20-le64.cache-7 +00007fc51a706000 4K r-xs- 73b2c246-8ec2-4cec-a9f7-8b69a879c11f-le64.cache-7 +00007fc51a707000 4K r-xs- 6d7fd616-c632-433b-b2a1-1a439844cb4c-le64.cache-7 +00007fc51a708000 12K r-xs- 94515895-7b91-4b92-a153-6168de8eb31f-le64.cache-7 +00007fc51a70b000 4K r-xs- bf59a3ff-18f7-458a-9f3c-45f045bfd41d-le64.cache-7 +00007fc51a70c000 16K r-xs- 3c4a99bc-95e1-4a81-b6e2-4093e7436024-le64.cache-7 +00007fc51a710000 16K r-xs- 231c47af-f39e-45c2-be83-f2cf926f3d24-le64.cache-7 +00007fc51a714000 12K r-xs- 9b1ada64-557e-4486-9164-e350371d5977-le64.cache-7 +00007fc51a717000 4K r-xs- 2bef893d-53ce-4d50-85aa-6dfea1db2c09-le64.cache-7 +00007fc51a718000 4K r-xs- ba6f3da1-6f47-4f77-97f7-2c3ca34b7945-le64.cache-7 +00007fc51a719000 4K r-xs- 8c1ea774-9391-418c-b3b1-907b6f0fa42f-le64.cache-7 +00007fc51a71a000 4K r-xs- a9656883-81b3-4353-8422-374f190304ff-le64.cache-7 +00007fc51a71b000 4K r-xs- 72111187-2413-48dd-8bad-f3ae4733a141-le64.cache-7 +00007fc51a71c000 4K r-xs- 178aeec4-0594-4743-a0c3-4e00175af393-le64.cache-7 +00007fc51a71d000 4K r-xs- 52a9c7f4-4118-482e-9b5f-3609406ef52f-le64.cache-7 +00007fc51a71e000 4K r-xs- 464ac9c6-b340-4ebc-887d-bd9fb6a54740-le64.cache-7 +00007fc51a71f000 4K r-xs- e04247dc-5989-4dd8-b993-085ab6fdf38c-le64.cache-7 +00007fc51a720000 4K r-xs- d1cbab9e-6c73-4eeb-8d4c-bd2c3ee72d9f-le64.cache-7 +00007fc51a721000 4K r-xs- 4d2f7af5-90a7-407d-8f91-27b43fa4eaf0-le64.cache-7 +00007fc51a722000 4K r-xs- 2f0faddf-403a-4776-952b-d1c2ca48367a-le64.cache-7 +00007fc51a723000 4K r-xs- 4b6e2fa7-8d67-46ee-8e1d-072b4048d149-le64.cache-7 +00007fc51a724000 4K r-xs- 3a57024f-d45a-4a94-aab6-457a97da8cb4-le64.cache-7 +00007fc51a725000 20K r-xs- 6f90bf98-dc57-4b19-9ea2-609bab43e579-le64.cache-7 +00007fc51a72a000 8K r-xs- d9966c19-a1c8-4a84-8e8b-67b9a5359c30-le64.cache-7 +00007fc51a72c000 4K r-xs- 1aedb7a2-5540-4639-b125-3803affd7c69-le64.cache-7 +00007fc51a72d000 32K r-xs- 27cca8a0-9a0b-41eb-ab8b-bc11685292d5-le64.cache-7 +00007fc51a735000 44K r-xs- 26b986c5-881b-4ee7-afce-080eb5c1aa62-le64.cache-7 +00007fc51a740000 72K rwx-- [ anon ] +00007fc51a752000 276K r-x-- libtbb.so.2 +00007fc51a797000 1024K ----- libtbb.so.2 +00007fc51a897000 20K rwx-- libtbb.so.2 +00007fc51a89c000 28K rwx-- [ anon ] +00007fc51a8a3000 8K r-xs- 6d459492-a742-40a3-b56b-31b84086b270-le64.cache-7 +00007fc51a8a5000 8K r-xs- 0d14775e-ba0b-409e-985d-aea8000857bd-le64.cache-7 +00007fc51a8a7000 8K r-xs- 586711aa-7365-4876-9dad-3549bfb47790-le64.cache-7 +00007fc51a8a9000 32K r-xs- 98268496-283c-48cd-8915-f21958b2b549-le64.cache-7 +00007fc51a8b1000 8K r-xs- 08dbea36-fd86-40ff-bb03-7fdcc9589253-le64.cache-7 +00007fc51a8b3000 4K r-xs- ca77f4a9-cc46-46b4-90f1-e56998c495b1-le64.cache-7 +00007fc51a8b4000 20K r-xs- c74708f5-7f19-4d87-8b35-3252086ba113-le64.cache-7 +00007fc51a8b9000 28K r-xs- gconv-modules.cache +00007fc51a8c0000 12K rwx-- [ anon ] +00007fc51a8c3000 4K r-x-- ld-2.17.so +00007fc51a8c4000 4K rwx-- ld-2.17.so +00007fc51a8c5000 4K rwx-- [ anon ] +00007ffdca0fd000 852K rwx-- [ stack ] +00007ffdca1dd000 8K r-x-- [ anon ] +ffffffffff600000 4K r-x-- [ anon ] + total 1428928K +--------------- +branchName=Verdi_O-2018.09-SP2 cnlDate=-- Thu Feb 21 04:40:56 PDT 2019 cnlEnv=Linux.0/64bit +uname(Linux IC_EDA 3.10.0-1160.53.1.el7.x86_64 #1 SMP Fri Jan 14 13:59:45 UTC 2022 x86_64) +--------------- +Process Size: 1463218176 bytes +verdi detected abnormal termination. +Log information written to +/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/digital_top/verdiLog/sysinfo_May15_1728.tar. +Please send this file to customer support. diff --git a/tb/digital_top/verdiLog/da_debug.log b/tb/digital_top/verdiLog/da_debug.log new file mode 100644 index 0000000..94d3d9c --- /dev/null +++ b/tb/digital_top/verdiLog/da_debug.log @@ -0,0 +1,5 @@ +##################################################################################################### +# da_debug.log : log primitive debug message of Data Agent (Verdi internal layer to access FSDB). # +# This is for R&D to analyze when there are issues happening when Verdi reading FSDB # +##################################################################################################### +[DA][EVDP][XML]: start update xml in interactive mode at init[DA][EVDP][XML]: start update xml file in interactive mode diff --git a/tb/digital_top/verdiLog/exe.log b/tb/digital_top/verdiLog/exe.log new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/verdiLog/novas.conf b/tb/digital_top/verdiLog/novas.conf new file mode 100644 index 0000000..9f6292b --- /dev/null +++ b/tb/digital_top/verdiLog/novas.conf @@ -0,0 +1,590 @@ +[qBaseWindowStateGroup] +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\ProductVersion=201809 +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\Layout="@ByteArray(\0\0\0\xff\0\0\0\0\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x2\xf2\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x3P\0\0\0\x89\0\xff\xff\xff\xfa\0\0\0\x1\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\x2\xc7\0\0\x1\xa8\0\0\0k\0\0\0k\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\x1\0\0\x3V\0\0\x6\xaa\0\0\0k\0\xff\xff\xff\0\0\0\x3\0\0\n\0\0\0\x1\xd8\xfc\x1\0\0\0\x1\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\x1\0\0\0\0\0\0\n\0\0\0\0\xa0\0\xff\xff\xff\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x3\x16\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x3\x1e\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\x1f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x43\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3g\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\isNestedWindow=0 +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\size=@Size(2560 1337) +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\geometry_x=-1 +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\geometry_y=27 +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\geometry_width=2560 +Verdi_1\qBaseWindowRestoreStateGroup\qDockerWindow_defaultLayout\geometry_height=1337 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\ProductVersion=201809 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\Layout="@ByteArray(\0\0\0\xff\0\0\0\0\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x3<\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x2\x8e\0\0\0\x89\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\xe9\0\0\0\xc6\0\0\0k\0\0\0k\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\x1\0\0\x2\x94\0\0\al\0\0\0k\0\xff\xff\xff\0\0\0\x3\0\0\n\0\0\0\x1\xa9\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\n\0\0\0\x2,\0\xff\xff\xff\xfa\0\0\0\x2\x1\0\0\0\x3\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\x1\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\x1-\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x33\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x34\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\isNestedWindow=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\size=@Size(2560 1337) +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\geometry_x=-1 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\geometry_y=27 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\geometry_width=2560 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\geometry_height=1337 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_OneSearch\isNestedWindow=1 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_OneSearch\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_OneSearch\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nWave_2\isNestedWindow=1 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nWave_2\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nWave_2\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nWave_2\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nWave_2\dockIsFloating=false +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qDockerWindow_qDockContentType\Verdi=1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qDockerWindow_qDockContentType\hdlHier=1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qDockerWindow_qDockContentType\hdlSrc=1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qDockerWindow_qDockContentType\messageWindow=1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qDockerWindow_qDockContentType\svtbHier=1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qDockerWindow_qDockContentType\OneSearch=1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qDockerWindowMgr_saveDockerChildList\Verdi_1=7 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qDockerWindowMgr_saveDockerChildList\Verdi_1_0=widgetDock_hdlHier_1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qDockerWindowMgr_saveDockerChildList\Verdi_1_1=widgetDock_messageWindow_1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qDockerWindowMgr_saveDockerChildList\Verdi_1_2=widgetDock_hdlSrc_1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qDockerWindowMgr_saveDockerChildList\Verdi_1_3=widgetDock_signalList_1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qDockerWindowMgr_saveDockerChildList\Verdi_1_4=widgetDock_svtbHier_1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qDockerWindowMgr_saveDockerChildList\Verdi_1_5=windowDock_OneSearch_1 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\widgetDock_hdlHier_1\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\widgetDock_hdlHier_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\widgetDock_hdlHier_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\widgetDock_hdlHier_1\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\widgetDock_messageWindow_1\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\widgetDock_messageWindow_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\widgetDock_messageWindow_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\widgetDock_messageWindow_1\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\widgetDock_hdlSrc_1\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\widgetDock_hdlSrc_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\widgetDock_hdlSrc_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\widgetDock_hdlSrc_1\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\widgetDock_signalList_1\isVisible=false +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\widgetDock_svtbHier_1\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\widgetDock_svtbHier_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\widgetDock_svtbHier_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\widgetDock_svtbHier_1\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\windowDock_OneSearch_1\isNestedWindow=1 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\windowDock_OneSearch_1\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\windowDock_OneSearch_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\windowDock_OneSearch_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\windowDock_OneSearch_1\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\windowDock_nWave_1\isNestedWindow=1 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\windowDock_nWave_1\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\windowDock_nWave_1\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\windowDock_nWave_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\windowDock_nWave_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qBaseDockWidgetGroup\windowDock_nWave_1\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\ProductVersion=201809 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\Layout="@ByteArray(\0\0\0\xff\0\0\0\0\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x2\xcb\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x2\x8d\0\0\0\x89\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x2\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0h\0\x64\0l\0H\0i\0\x65\0r\0_\0\x31\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0*\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0s\0v\0t\0\x62\0H\0i\0\x65\0r\0_\0\x31\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0s\0i\0g\0n\0\x61\0l\0L\0i\0s\0t\0_\0\x31\0\0\0\0\xe9\0\0\0\xc6\0\0\0k\0\0\0k\xfb\0\0\0&\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0h\0\x64\0l\0S\0r\0\x63\0_\0\x31\x1\0\0\x2\x93\0\0\am\0\0\0k\0\xff\xff\xff\0\0\0\x3\0\0\n\0\0\0\x2\x1a\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\n\0\0\0\x2,\0\xff\xff\xff\xfa\0\0\0\x2\x1\0\0\0\x3\xfb\0\0\0\x34\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0m\0\x65\0s\0s\0\x61\0g\0\x65\0W\0i\0n\0\x64\0o\0w\0_\0\x31\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0,\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\0_\0\x31\x1\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x31\x1\0\0\0\0\xff\xff\xff\xff\0\0\x1-\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x33\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x34\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\isNestedWindow=0 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\size=@Size(2560 1337) +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\geometry_x=-1 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\geometry_y=27 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\geometry_width=2560 +Verdi_1\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\geometry_height=1337 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nWave_2\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nMemory_3\isNestedWindow=1 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nMemory_3\isVisible=false +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nMemory_3\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nMemory_3\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nMemory_3\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nMemory_4\isNestedWindow=1 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nMemory_4\isVisible=false +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nMemory_4\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nMemory_4\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\backup_layout_to_restore\qBaseDockWidgetGroup\windowDock_nMemory_4\dockIsFloating=false +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qDockerWindow_qDockContentType\nWave=1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\VERDI_LAST_RUN_LAYOUT\qDockerWindowMgr_saveDockerChildList\Verdi_1_6=windowDock_nWave_1 +Verdi_1\qBaseWindowNextStateGroup\0\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\0\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\0\ProductVersion=201809 +Verdi_1\qBaseWindowNextStateGroup\0\Layout="@ByteArray(\0\0\0\xff\0\0\0\0\xfd\0\0\0\x2\0\0\0\x2\0\0\x3U\0\0\x1L\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\0\xd9\0\0\0\x89\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\xe9\0\0\0\xc6\0\0\0k\0\0\0k\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\x1\0\0\0\xdf\0\0\x2v\0\0\0k\0\xff\xff\xff\0\0\0\x3\0\0\x3U\0\0\0\x9c\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x3U\0\0\0\xa0\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x3\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x33\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x34\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\0\0\x3U\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowNextStateGroup\0\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\0\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\0\size=@Size(853 572) +Verdi_1\qBaseWindowNextStateGroup\0\geometry_x=-1 +Verdi_1\qBaseWindowNextStateGroup\0\geometry_y=27 +Verdi_1\qBaseWindowNextStateGroup\0\geometry_width=853 +Verdi_1\qBaseWindowNextStateGroup\0\geometry_height=572 +Verdi_1\qBaseWindowNextStateGroup\1\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_OneSearch\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_OneSearch\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\1\qBaseDockWidgetGroup\windowDock_OneSearch\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\1\ProductVersion=201809 +Verdi_1\qBaseWindowNextStateGroup\1\Layout="@ByteArray(\0\0\0\xff\0\0\0\x1\xfd\0\0\0\x2\0\0\0\x2\0\0\x3U\0\0\x1\x33\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\0\xd9\0\0\0\x89\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\xe9\0\0\0\xc6\0\0\0k\0\0\0k\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\x1\0\0\0\xdf\0\0\x2v\0\0\0k\0\xff\xff\xff\0\0\0\x3\0\0\x3U\0\0\0\xb5\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x3U\0\0\x2,\0\xff\xff\xff\xfa\0\0\0\x2\x1\0\0\0\x3\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\x1\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x33\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x34\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\0\0\x3U\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowNextStateGroup\1\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\1\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\1\size=@Size(853 572) +Verdi_1\qBaseWindowNextStateGroup\1\geometry_x=-1 +Verdi_1\qBaseWindowNextStateGroup\1\geometry_y=27 +Verdi_1\qBaseWindowNextStateGroup\1\geometry_width=853 +Verdi_1\qBaseWindowNextStateGroup\1\geometry_height=572 +Verdi_1\qBaseWindowNextStateGroup\2\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\windowDock_OneSearch\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\2\qBaseDockWidgetGroup\windowDock_OneSearch\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\2\ProductVersion=201809 +Verdi_1\qBaseWindowNextStateGroup\2\Layout="@ByteArray(\0\0\0\xff\0\0\0\x2\xfd\0\0\0\x2\0\0\0\x2\0\0\x3U\0\0\x1\x33\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\0\xd9\0\0\0\x89\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\xe9\0\0\0\xc6\0\0\0k\0\0\0k\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\x1\0\0\0\xdf\0\0\x2v\0\0\0k\0\xff\xff\xff\0\0\0\x3\0\0\x3U\0\0\0\xb5\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x3U\0\0\0\xa0\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x3\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\0\0\0\0\0\xff\xff\xff\xff\0\0\0k\0\0\0k\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x33\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x34\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\0\0\x3U\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowNextStateGroup\2\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\2\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\2\size=@Size(853 572) +Verdi_1\qBaseWindowNextStateGroup\2\geometry_x=-1 +Verdi_1\qBaseWindowNextStateGroup\2\geometry_y=27 +Verdi_1\qBaseWindowNextStateGroup\2\geometry_width=853 +Verdi_1\qBaseWindowNextStateGroup\2\geometry_height=572 +Verdi_1\qBaseWindowNextStateGroup\3\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\windowDock_OneSearch\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\windowDock_OneSearch\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\3\qBaseDockWidgetGroup\windowDock_OneSearch\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\3\ProductVersion=201809 +Verdi_1\qBaseWindowNextStateGroup\3\Layout="@ByteArray(\0\0\0\xff\0\0\0\x3\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x4\x30\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x2\x8e\0\0\0\x89\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\xe9\0\0\0\xc6\0\0\0k\0\0\0k\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\x1\0\0\x2\x94\0\0\al\0\0\0k\0\xff\xff\xff\0\0\0\x3\0\0\n\0\0\0\0\xb5\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\n\0\0\0\x2,\0\xff\xff\xff\xfa\0\0\0\x2\x1\0\0\0\x3\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\x1\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x33\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x34\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowNextStateGroup\3\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\3\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\3\size=@Size(2560 1337) +Verdi_1\qBaseWindowNextStateGroup\3\geometry_x=-1 +Verdi_1\qBaseWindowNextStateGroup\3\geometry_y=27 +Verdi_1\qBaseWindowNextStateGroup\3\geometry_width=2560 +Verdi_1\qBaseWindowNextStateGroup\3\geometry_height=1337 +Verdi_1\qBaseWindowNextStateGroup\4\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\windowDock_OneSearch\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\windowDock_OneSearch\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\4\qBaseDockWidgetGroup\windowDock_OneSearch\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\4\ProductVersion=201809 +Verdi_1\qBaseWindowNextStateGroup\4\Layout="@ByteArray(\0\0\0\xff\0\0\0\x4\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x4\x30\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x2\x8e\0\0\0\x89\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\xe9\0\0\0\xc6\0\0\0k\0\0\0k\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\x1\0\0\x2\x94\0\0\al\0\0\0k\0\xff\xff\xff\0\0\0\x3\0\0\n\0\0\0\0\xb5\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\n\0\0\0\x2,\0\xff\xff\xff\xfa\0\0\0\x2\x1\0\0\0\x3\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\x1\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x33\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x34\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowNextStateGroup\4\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\4\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\4\size=@Size(2560 1337) +Verdi_1\qBaseWindowNextStateGroup\4\geometry_x=-1 +Verdi_1\qBaseWindowNextStateGroup\4\geometry_y=27 +Verdi_1\qBaseWindowNextStateGroup\4\geometry_width=2560 +Verdi_1\qBaseWindowNextStateGroup\4\geometry_height=1337 +Verdi_1\qBaseWindowNextStateGroup\5\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_OneSearch\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_OneSearch\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_OneSearch\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nWave_2\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nWave_2\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nWave_2\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nWave_2\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\5\qBaseDockWidgetGroup\windowDock_nWave_2\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\5\ProductVersion=201809 +Verdi_1\qBaseWindowNextStateGroup\5\Layout="@ByteArray(\0\0\0\xff\0\0\0\x5\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x4/\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x2\x8e\0\0\0\x89\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\xe9\0\0\0\xc6\0\0\0k\0\0\0k\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\x1\0\0\x2\x94\0\0\al\0\0\0k\0\xff\xff\xff\0\0\0\x3\0\0\n\0\0\0\0\xb6\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\n\0\0\0\x2,\0\xff\xff\xff\xfa\0\0\0\x2\x1\0\0\0\x3\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\x1\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\x1\xd5\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x33\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x34\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowNextStateGroup\5\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\5\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\5\size=@Size(2560 1337) +Verdi_1\qBaseWindowNextStateGroup\5\geometry_x=-1 +Verdi_1\qBaseWindowNextStateGroup\5\geometry_y=27 +Verdi_1\qBaseWindowNextStateGroup\5\geometry_width=2560 +Verdi_1\qBaseWindowNextStateGroup\5\geometry_height=1337 +Verdi_1\qBaseWindowNextStateGroup\6\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\windowDock_OneSearch\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\windowDock_OneSearch\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\windowDock_nWave_2\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\windowDock_nWave_2\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\windowDock_nWave_2\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\windowDock_nWave_2\qBaseWindowBeMax=1 +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\windowDock_nWave_2\qBaseWindowBeFix=1 +Verdi_1\qBaseWindowNextStateGroup\6\qBaseDockWidgetGroup\windowDock_nWave_2\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\6\ProductVersion=201809 +Verdi_1\qBaseWindowNextStateGroup\6\Layout="@ByteArray(\0\0\0\xff\0\0\0\x6\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x3<\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x2\x8e\0\0\0\0\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\xe9\0\0\0\xc6\0\0\0k\0\0\0k\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\0\0\0\x2\x94\0\0\al\0\0\0k\0\xff\xff\xff\0\0\0\x3\0\0\n\0\0\0\x1\xa9\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\n\0\0\0\x1-\0\xff\xff\xff\xfa\0\0\0\x2\x1\0\0\0\x3\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\0\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\x1-\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x33\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x34\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowNextStateGroup\6\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\6\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\6\size=@Size(2560 1337) +Verdi_1\qBaseWindowNextStateGroup\6\geometry_x=-1 +Verdi_1\qBaseWindowNextStateGroup\6\geometry_y=27 +Verdi_1\qBaseWindowNextStateGroup\6\geometry_width=2560 +Verdi_1\qBaseWindowNextStateGroup\6\geometry_height=1337 +Verdi_1\qBaseWindowNextStateGroup\7\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_OneSearch\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_OneSearch\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_OneSearch\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_nWave_2\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_nWave_2\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_nWave_2\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_nWave_2\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_nWave_2\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\7\qBaseDockWidgetGroup\windowDock_nWave_2\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\7\ProductVersion=201809 +Verdi_1\qBaseWindowNextStateGroup\7\Layout="@ByteArray(\0\0\0\xff\0\0\0\a\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x3<\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x2\x8e\0\0\0\x89\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\xe9\0\0\0\xc6\0\0\0k\0\0\0k\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\x1\0\0\x2\x94\0\0\al\0\0\0k\0\xff\xff\xff\0\0\0\x3\0\0\n\0\0\0\x1\xa9\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\n\0\0\0\x2,\0\xff\xff\xff\xfa\0\0\0\x2\x1\0\0\0\x3\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\x1\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\x1-\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x33\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x34\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowNextStateGroup\7\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\7\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\7\size=@Size(2560 1337) +Verdi_1\qBaseWindowNextStateGroup\7\geometry_x=-1 +Verdi_1\qBaseWindowNextStateGroup\7\geometry_y=27 +Verdi_1\qBaseWindowNextStateGroup\7\geometry_width=2560 +Verdi_1\qBaseWindowNextStateGroup\7\geometry_height=1337 +Verdi_1\qBaseWindowNextStateGroup\8\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\windowDock_OneSearch\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\windowDock_OneSearch\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\windowDock_nWave_2\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\windowDock_nWave_2\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\windowDock_nWave_2\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\windowDock_nWave_2\qBaseWindowBeMax=1 +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\windowDock_nWave_2\qBaseWindowBeFix=1 +Verdi_1\qBaseWindowNextStateGroup\8\qBaseDockWidgetGroup\windowDock_nWave_2\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\8\ProductVersion=201809 +Verdi_1\qBaseWindowNextStateGroup\8\Layout="@ByteArray(\0\0\0\xff\0\0\0\b\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x3<\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x2\x8e\0\0\0\0\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\xe9\0\0\0\xc6\0\0\0k\0\0\0k\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\0\0\0\x2\x94\0\0\al\0\0\0k\0\xff\xff\xff\0\0\0\x3\0\0\n\0\0\0\x1\xa9\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\n\0\0\0\x1-\0\xff\xff\xff\xfa\0\0\0\x2\x1\0\0\0\x3\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\0\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\x1-\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x33\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x34\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowNextStateGroup\8\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\8\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\8\size=@Size(2560 1337) +Verdi_1\qBaseWindowNextStateGroup\8\geometry_x=-1 +Verdi_1\qBaseWindowNextStateGroup\8\geometry_y=27 +Verdi_1\qBaseWindowNextStateGroup\8\geometry_width=2560 +Verdi_1\qBaseWindowNextStateGroup\8\geometry_height=1337 +Verdi_1\qBaseWindowNextStateGroup\9\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\windowDock_OneSearch\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\windowDock_OneSearch\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\windowDock_OneSearch\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\windowDock_nWave_2\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\windowDock_nWave_2\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\windowDock_nWave_2\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\windowDock_nWave_2\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\windowDock_nWave_2\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\9\qBaseDockWidgetGroup\windowDock_nWave_2\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\9\ProductVersion=201809 +Verdi_1\qBaseWindowNextStateGroup\9\Layout="@ByteArray(\0\0\0\xff\0\0\0\t\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x3<\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x2\x8e\0\0\0\x89\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\xe9\0\0\0\xc6\0\0\0k\0\0\0k\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\x1\0\0\x2\x94\0\0\al\0\0\0k\0\xff\xff\xff\0\0\0\x3\0\0\n\0\0\0\x1\xa9\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\n\0\0\0\x2,\0\xff\xff\xff\xfa\0\0\0\x2\x1\0\0\0\x3\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\x1\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\x1-\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x33\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x34\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowNextStateGroup\9\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\9\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\9\size=@Size(2560 1337) +Verdi_1\qBaseWindowNextStateGroup\9\geometry_x=-1 +Verdi_1\qBaseWindowNextStateGroup\9\geometry_y=27 +Verdi_1\qBaseWindowNextStateGroup\9\geometry_width=2560 +Verdi_1\qBaseWindowNextStateGroup\9\geometry_height=1337 +Verdi_1\qBaseWindowNextStateGroup\10\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\windowDock_OneSearch\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\windowDock_OneSearch\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\windowDock_nWave_2\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\windowDock_nWave_2\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\windowDock_nWave_2\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\windowDock_nWave_2\qBaseWindowBeMax=1 +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\windowDock_nWave_2\qBaseWindowBeFix=1 +Verdi_1\qBaseWindowNextStateGroup\10\qBaseDockWidgetGroup\windowDock_nWave_2\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\10\ProductVersion=201809 +Verdi_1\qBaseWindowNextStateGroup\10\Layout="@ByteArray(\0\0\0\xff\0\0\0\n\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x3<\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x2\x8e\0\0\0\0\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\xe9\0\0\0\xc6\0\0\0k\0\0\0k\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\0\0\0\x2\x94\0\0\al\0\0\0k\0\xff\xff\xff\0\0\0\x3\0\0\n\0\0\0\x1\xa9\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\n\0\0\0\x1-\0\xff\xff\xff\xfa\0\0\0\x2\x1\0\0\0\x3\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\0\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\x1-\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x33\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x34\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowNextStateGroup\10\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\10\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\10\size=@Size(2560 1337) +Verdi_1\qBaseWindowNextStateGroup\10\geometry_x=-1 +Verdi_1\qBaseWindowNextStateGroup\10\geometry_y=27 +Verdi_1\qBaseWindowNextStateGroup\10\geometry_width=2560 +Verdi_1\qBaseWindowNextStateGroup\10\geometry_height=1337 +Verdi_1\qBaseWindowNextStateGroup\11\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeMax=1 +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_OneSearch\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_OneSearch\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_nWave_2\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_nWave_2\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_nWave_2\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_nWave_2\qBaseWindowBeMax=1 +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_nWave_2\qBaseWindowBeFix=1 +Verdi_1\qBaseWindowNextStateGroup\11\qBaseDockWidgetGroup\windowDock_nWave_2\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\11\ProductVersion=201809 +Verdi_1\qBaseWindowNextStateGroup\11\Layout="@ByteArray(\0\0\0\xff\0\0\0\v\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x3<\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x2\x8e\0\0\0\0\0\xff\xff\xff\xfa\xff\xff\xff\xff\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\xe9\0\0\0\xc6\0\0\0k\0\0\0k\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\0\0\0\x2\x94\0\0\al\0\0\0k\0\xff\xff\xff\0\0\0\x3\0\0\n\0\0\0\x4\xeb\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\n\0\0\0\x1-\0\xff\xff\xff\xfa\0\0\0\x2\x1\0\0\0\x3\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\0\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\x1-\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x33\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x34\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowNextStateGroup\11\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\11\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\11\size=@Size(2560 1337) +Verdi_1\qBaseWindowNextStateGroup\11\geometry_x=-1 +Verdi_1\qBaseWindowNextStateGroup\11\geometry_y=27 +Verdi_1\qBaseWindowNextStateGroup\11\geometry_width=2560 +Verdi_1\qBaseWindowNextStateGroup\11\geometry_height=1337 +Verdi_1\qBaseWindowNextStateGroup\12\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeMax=1 +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\windowDock_OneSearch\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\windowDock_OneSearch\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\windowDock_nWave_2\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\windowDock_nWave_2\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\windowDock_nWave_2\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\windowDock_nWave_2\qBaseWindowBeMax=1 +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\windowDock_nWave_2\qBaseWindowBeFix=1 +Verdi_1\qBaseWindowNextStateGroup\12\qBaseDockWidgetGroup\windowDock_nWave_2\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\12\ProductVersion=201809 +Verdi_1\qBaseWindowNextStateGroup\12\Layout="@ByteArray(\0\0\0\xff\0\0\0\f\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x3<\xfc\x1\0\0\0\x2\xfc\0\0\0\0\0\0\x2\x8e\0\0\0\0\0\xff\xff\xff\xfa\xff\xff\xff\xff\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\0\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\xe9\0\0\0\xc6\0\0\0k\0\0\0k\0\0\0\x3\0\0\n\0\0\0\x4\xeb\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\n\0\0\0\x1-\0\xff\xff\xff\xfa\0\0\0\x2\x1\0\0\0\x4\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\0\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\x1-\0\xff\xff\xff\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\0\0\0\0\0\xff\xff\xff\xff\0\0\al\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x33\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x34\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowNextStateGroup\12\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\12\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\12\size=@Size(2560 1337) +Verdi_1\qBaseWindowNextStateGroup\12\geometry_x=-1 +Verdi_1\qBaseWindowNextStateGroup\12\geometry_y=27 +Verdi_1\qBaseWindowNextStateGroup\12\geometry_width=2560 +Verdi_1\qBaseWindowNextStateGroup\12\geometry_height=1337 +Verdi_1\qBaseWindowNextStateGroup\13\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\widgetDock_%3CInst._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\widgetDock_%3CMessage%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\widgetDock_MTB_SOURCE_TAB_1\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\widgetDock_%3CSignal_List%3E\isVisible=false +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\widgetDock_%3CDecl._Tree%3E\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_OneSearch\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_OneSearch\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_OneSearch\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_OneSearch\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_nWave_2\isNestedWindow=1 +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_nWave_2\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_nWave_2\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_nWave_2\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_nWave_2\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowNextStateGroup\13\qBaseDockWidgetGroup\windowDock_nWave_2\dockIsFloating=false +Verdi_1\qBaseWindowNextStateGroup\13\ProductVersion=201809 +Verdi_1\qBaseWindowNextStateGroup\13\Layout="@ByteArray(\0\0\0\xff\0\0\0\r\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x3<\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x2\x8e\0\0\0\x89\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\xe9\0\0\0\xc6\0\0\0k\0\0\0k\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\x1\0\0\x2\x94\0\0\al\0\0\0k\0\xff\xff\xff\0\0\0\x3\0\0\n\0\0\0\x1\xa9\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\n\0\0\0\x2,\0\xff\xff\xff\xfa\0\0\0\x2\x1\0\0\0\x3\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\x1\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\x1-\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x33\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x34\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowNextStateGroup\13\isNestedWindow=0 +Verdi_1\qBaseWindowNextStateGroup\13\isVisible=true +Verdi_1\qBaseWindowNextStateGroup\13\size=@Size(2560 1337) +Verdi_1\qBaseWindowNextStateGroup\13\geometry_x=-1 +Verdi_1\qBaseWindowNextStateGroup\13\geometry_y=27 +Verdi_1\qBaseWindowNextStateGroup\13\geometry_width=2560 +Verdi_1\qBaseWindowNextStateGroup\13\geometry_height=1337 + +[QwMainWindow] +window\Verdi_1\layout="@ByteArray(\0\0\0\xff\0\x3\x14Q\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x2\xcb\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x2\x8d\0\0\0\x89\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x2\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0I\0n\0s\0t\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0\x44\0\x65\0\x63\0l\0.\0_\0T\0r\0\x65\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0\x30\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0S\0i\0g\0n\0\x61\0l\0_\0L\0i\0s\0t\0>\0\0\0\0\xe9\0\0\0\xc6\0\0\0k\0\0\0k\xfb\0\0\0\x36\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0M\0T\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0T\0\x41\0\x42\0_\0\x31\x1\0\0\x2\x93\0\0\am\0\0\0k\0\xff\xff\xff\0\0\0\x3\0\0\n\0\0\0\x2\x1a\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\n\0\0\0\x2,\0\xff\xff\xff\xfa\0\0\0\x2\x1\0\0\0\x3\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0<\0M\0\x65\0s\0s\0\x61\0g\0\x65\0>\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\x1\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x32\x1\0\0\0\0\xff\xff\xff\xff\0\0\x1-\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x33\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x34\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +window\Verdi_1\geometry=@ByteArray(\x1\xd9\xd0\xcb\0\x1\0\0\xff\xff\xff\xff\0\0\0\x1b\0\0\n\0\0\0\x5z\0\0\0\0\0\0\0\0\xff\xff\xff\xfe\xff\xff\xff\xfe\0\0\0\0\x2\0) +window\Verdi_1\menubar=true +window\Verdi_1\splitters\tbvConstrDbgSplitter\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x2\0\0\0\x8d\0\0\0\x8d\x1\0\0\0\x6\x1\0\0\0\x1) +window\Verdi_1\splitters\tbvConstrRerandSplitter\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x2\0\0\0G\0\0\0\x4\x1\0\0\0\x6\x1\0\0\0\x2) +window\Verdi_1\splitters\tbvConstrOriginSplitter\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x2\0\0\0!\0\0\0\x4\x1\0\0\0\x6\x1\0\0\0\x2) +window\Verdi_1\splitters\ThreadPane\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x2\0\0\0\x37\0\0\0\x37\x1\0\0\0\x6\x1\0\0\0\x2) +window\Verdi_1\splitters\tbvInteractiveSplitter\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x2\0\0\0\x1f\0\0\0\x1f\x1\0\0\0\x6\x1\0\0\0\x2) +window\Verdi_1\splitters\tbvVSimSplitter\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x2\0\0\0\x1f\0\0\0\x1f\x1\0\0\0\x6\x1\0\0\0\x2) +window\Verdi_1\splitters\tbvTBHSplitter\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x2\0\0\0-\0\0\0?\x1\0\0\0\x6\x1\0\0\0\x2) +window\nWave_2\layout="@ByteArray(\0\0\0\xff\0\x3\x14Q\xfd\0\0\0\0\0\0\n\0\0\0\x1\xb2\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x2\0\0\0\x2\0\0\0\f\0\0\0\x12\0W\0\x41\0V\0\x45\0_\0O\0P\0\x45\0N\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x12\0W\0\x41\0V\0\x45\0_\0\x45\0\x44\0I\0T\x1\0\0\0?\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x16\0W\0\x41\0V\0\x45\0_\0\x43\0U\0R\0S\0O\0R\x1\0\0\0\xb4\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x12\0W\0\x41\0V\0\x45\0_\0V\0I\0\x45\0W\x1\0\0\x2R\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\"\0W\0\x41\0V\0\x45\0_\0S\0\x45\0\x41\0R\0\x43\0H\0_\0\x45\0V\0\x45\0N\0T\x1\0\0\x2\xac\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0W\0\x41\0V\0\x45\0_\0R\0\x45\0P\0L\0\x41\0Y\0_\0S\0I\0M\0\0\0\x5K\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x12\0W\0\x41\0V\0\x45\0_\0G\0O\0T\0O\x1\0\0\x3H\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0W\0\x41\0V\0\x45\0_\0G\0O\0T\0O\0_\0N\0\x41\0M\0\x45\0\x44\0_\0M\0\x41\0R\0K\0\x45\0R\0\0\0\x5\xed\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0W\0\x41\0V\0\x45\0_\0T\0R\0\x41\0N\0S\0\x41\0\x43\0T\0I\0O\0N\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0W\0\x41\0V\0\x45\0_\0\x45\0X\0P\0L\0O\0R\0\x45\0_\0P\0R\0O\0P\0\x45\0R\0T\0Y\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0W\0\x41\0V\0\x45\0_\0\x46\0I\0N\0\x44\0_\0S\0I\0G\0N\0\x41\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x18\0W\0\x41\0V\0\x45\0_\0P\0R\0I\0M\0\x41\0R\0Y\0\0\0\x6\x1b\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x32\0S\0\x45\0L\0\x45\0\x43\0T\0I\0O\0N\0_\0M\0\x45\0S\0S\0\x41\0G\0\x45\0_\0T\0O\0O\0L\0\x42\0\x41\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +window\nWave_2\geometry=@ByteArray(\x1\xd9\xd0\xcb\0\x1\0\0\0\0\0\0\0\0\0\x1b\0\0\t\xff\0\0\x1\xfe\0\0\0\0\0\0\0\x1b\0\0\t\xff\0\0\x1\xfe\0\0\0\0\0\0) +window\nWave_2\menubar=true +window\nWave_2\splitters\splitter_5\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\x1\xb2\x1\0\0\0\x1\0\0\0\0\x2) +window\nWave_2\splitters\splitter_2\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x2\0\0\0\xd8\0\0\t(\x1\0\0\0\x1\0\0\0\0\x1) +window\nWave_2\splitters\splitter\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x3\0\0\0?\0\0\0\x1\0\0\b\xe6\x1\0\0\0\x1\0\0\0\0\x1) +window\nWave_2\splitters\Pane_Upper\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x2\0\0\0\xd8\0\0\t%\x1\0\0\0\x1\0\0\0\0\x1) +window\nWave_2\splitters\splitter_3\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x2\0\0\0?\0\0\tW\x1\0\0\0\x1\0\0\0\0\x1) +window\nWave_2\splitters\wholeSplitter\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x3\0\0\0O\0\0\0\xa3\0\0\0\x4\x1\0\0\0\x6\x1\0\0\0\x1) +window\nWave_2\splitters\middleSplitter\layout=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0\x4\x1\0\0\0\x6\x1\0\0\0\x2) +window\nMemory_3\layout=@ByteArray(\0\0\0\xff\0\x3\x14Q\xfd\0\0\0\0\0\0\x4\xfd\0\0\x1\xda\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x2\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0M\0\x45\0M\0_\0T\0O\0O\0L\0\x42\0\x41\0R\0_\0U\0P\0P\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x34\0N\0M\0\x45\0M\0_\0T\0O\0O\0L\0\x42\0\x41\0R\0_\0U\0P\0P\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0_\0\x32\x1\0\0\0?\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x34\0N\0M\0\x45\0M\0_\0T\0O\0O\0L\0\x42\0\x41\0R\0_\0U\0P\0P\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0_\0\x33\x1\0\0\x1\xd3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x34\0N\0M\0\x45\0M\0_\0T\0O\0O\0L\0\x42\0\x41\0R\0_\0L\0O\0W\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0_\0\x31\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0) +window\nMemory_3\geometry=@ByteArray(\x1\xd9\xd0\xcb\0\x1\0\0\0\0\0\0\0\0\0\x1b\0\0\x4\xfc\0\0\x2@\0\0\0\0\0\0\0\x1b\0\0\x4\xfc\0\0\x2@\0\0\0\0\0\0) +window\nMemory_3\menubar=true +window\nMemory_4\layout=@ByteArray(\0\0\0\xff\0\x3\x14Q\xfd\0\0\0\0\0\0\x4\xfd\0\0\x1\xda\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x2\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0M\0\x45\0M\0_\0T\0O\0O\0L\0\x42\0\x41\0R\0_\0U\0P\0P\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x34\0N\0M\0\x45\0M\0_\0T\0O\0O\0L\0\x42\0\x41\0R\0_\0U\0P\0P\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0_\0\x32\x1\0\0\0?\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x34\0N\0M\0\x45\0M\0_\0T\0O\0O\0L\0\x42\0\x41\0R\0_\0U\0P\0P\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0_\0\x33\x1\0\0\x1\xd3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x34\0N\0M\0\x45\0M\0_\0T\0O\0O\0L\0\x42\0\x41\0R\0_\0L\0O\0W\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0_\0\x31\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0) +window\nMemory_4\geometry=@ByteArray(\x1\xd9\xd0\xcb\0\x1\0\0\0\0\0\0\0\0\0\x1b\0\0\x4\xfc\0\0\x2@\0\0\0\0\0\0\0\x1b\0\0\x4\xfc\0\0\x2@\0\0\0\0\0\0) +window\nMemory_4\menubar=true + +[qBaseWindow_saveRestoreSession_group] +10=/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/digital_top/verdiLog/novas_autosave.ses + +[qDockerWindow_C] +Verdi_1\position.x=-1 +Verdi_1\position.y=27 +Verdi_1\width=2560 +Verdi_1\height=1337 diff --git a/tb/digital_top/verdiLog/novas.log b/tb/digital_top/verdiLog/novas.log new file mode 100644 index 0000000..157ce72 --- /dev/null +++ b/tb/digital_top/verdiLog/novas.log @@ -0,0 +1,10 @@ +Verdi (R) + +Release Verdi_O-2018.09-SP2 for (RH Linux x86_64/64bit) -- Thu Feb 21 04:40:56 PDT 2019 + +Copyright (c) 1999 - 2019 Synopsys, Inc. +This software and the associated documentation are proprietary to Synopsys, Inc. +This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. +All other use, reproduction, or distribution of this software is strictly prohibited. + + diff --git a/tb/digital_top/verdiLog/novas.rc b/tb/digital_top/verdiLog/novas.rc new file mode 100644 index 0000000..66543f4 --- /dev/null +++ b/tb/digital_top/verdiLog/novas.rc @@ -0,0 +1,1319 @@ +@verdi rc file Version 1.0 +[Library] +work = ./work +[Annotation] +3D_Active_Annotation = FALSE +[CommandSyntax.finsim] +InvokeCommand = +FullFileName = TRUE +Separator = . +SimPromptSign = ">" +HierNameLevel = 1 +RunContinue = "continue" +Finish = "quit" +UseAbsTime = FALSE +NextTime = "run 1" +NextNTime = "run ${SimBPTime}" +NextEvent = "run 1" +Reset = +ObjPosBreak = "break posedge ${SimBPObj}" +ObjNegBreak = "break negedge ${SimBPObj}" +ObjAnyBreak = "break change ${SimBPObj}" +ObjLevelBreak = +LineBreak = "breakline ${SimBPFile} ${SimBPLine}" +AbsTimeBreak = "break abstimeaf ${SimBPTime}" +RelTimeBreak = "break reltimeaf ${SimBPTime}" +EnableBP = "breakon ${SimBPId}" +DisableBP = "breakoff ${SimBPId}" +DeleteBP = "breakclr ${SimBPId}" +DeleteAllBP = "breakclr" +SimSetScope = "cd ${SimDmpObj}" +[CommandSyntax.ikos] +InvokeCommand = "setvar debussy true;elaborate -p ${SimTop} -s ${SimArch}; run until 0;fsdbInteractive; " +FullFileName = TRUE +NeedTimeUnit = TRUE +NormalizeTimeUnit = TRUE +Separator = / +HierNameLevel = 2 +RunContinue = "run" +Finish = "exit" +NextTime = "run ${SimBPTime} ${SimTimeUnit}" +NextNTime = "run for ${SimBPTime} ${SimTimeUnit}" +NextEvent = "step 1" +Reset = "reset" +ObjPosBreak = "stop if ${SimBPObj} = \"'1'\"" +ObjNegBreak = "stop if ${SimBPObj} = \"'0'\"" +ObjAnyBreak = +ObjLevelBreak = "stop if ${SimBPObj} = ${SimBPValue}" +LineBreak = "stop at ${SimBPFile}:${SimBPLine}" +AbsTimeBreak = +RelTimeBreak = +EnableBP = "enable ${SimBPId}" +DisableBP = "disable ${SimBPId}" +DeleteBP = "delete ${SimBPId}" +DeleteAllBP = "delete *" +[CommandSyntax.verisity] +InvokeCommand = +FullFileName = FALSE +Separator = . +SimPromptSign = "> " +HierNameLevel = 1 +RunContinue = "." +Finish = "$finish;" +NextTime = "$db_steptime(1);" +NextNTime = "$db_steptime(${SimBPTime});" +NextEvent = "$db_step;" +SimSetScope = "$scope(${SimDmpObj});" +Reset = "$reset;" +ObjPosBreak = "$db_breakonposedge(${SimBPObj});" +ObjNegBreak = "$db_breakonnegedge(${SimBPObj});" +ObjAnyBreak = "$db_breakwhen(${SimBPObj});" +ObjLevelBreak = "$db_breakwhen(${SimBPObj}, ${SimBPValue});" +LineBreak = "$db_breakatline(${SimBPLine}, ${SimBPScope}, \"${SimBPFile}\");" +AbsTimeBreak = "$db_breakbeforetime(${SimBPTime});" +RelTimeBreak = "$db_breakbeforetime(${SimBPTime});" +EnableBP = "$db_enablebreak(${SimBPId});" +DisableBP = "$db_disablebreak(${SimBPId});" +DeleteBP = "$db_deletebreak(${SimBPId});" +DeleteAllBP = "$db_deletebreak;" +FSDBInit = "$novasInteractive;" +FSDBDumpvars = "$novasDumpvars(0, ${SimDmpObj});" +FSDBDumpsingle = "$novasDumpsingle(${SimDmpObj});" +FSDBDumpvarsInFile = "$novasDumpvarsToFile(\"${SimDmpFile}\");" +FSDBDumpMem = "$novasDumpMemNow(${SimDmpObj}, ${SimDmpBegin}, ${SimDmpSize});" +[CoverageDetail] +cross_filter_limit = 1000 +branch_limit_vector_display = 50 +showgrid = TRUE +reuseFirst = TRUE +justify = TRUE +scrollbar_mode = per pane +test_combo_left_truncate = TRUE +instance_combo_left_truncate = TRUE +loop_navigation = TRUE +condSubExpr = 20 +tglMda = 1000 +linecoverable = 100000 +lineuncovered = 50000 +tglcoverable = 30000 +tgluncovered = 30000 +pendingMax = 1000 +show_full_more = FALSE +[CoverageHier] +showgrid = FALSE +[CoverageWeight] +Assert = 1 +Covergroup = 1 +Line = 1 +Condition = 1 +Toggle = 1 +FSM = 1 +Branch = 1 +[DesignTree] +IfShowModule = {TRUE, FALSE} +[DisabledMessages] +version = Verdi_O-2018.09-SP2 +[Editor] +editorName = TurboEditor +[Emacs] +EmacsFont = "Clean 14" +EmacsBG = white +EmacsFG = black +[Exclusion] +enableAsDefault = TRUE +saveAsDefault = TRUE +saveManually = TRUE +illegalBehavior = FALSE +DisplayExcludedItem = FALSE +adaptiveExclusion = TRUE +warningExcludeInstance = TRUE +favorite_exclude_annotation = "" +[FSM] +viewport = 65 336 387 479 +WndBk-FillColor = Gray3 +Background-FillColor = gray5 +prefKey_Link-FillColor = yellow4 +prefKey_Link-TextColor = black +Trap = red3 +Hilight = blue4 +Window = Gray3 +Selected = white +Trans. = green2 +State = black +Init. = black +SmartTips = TRUE +VectorFont = FALSE +StopAskBkgndColor = FALSE +ShowStateAction = FALSE +ShowTransAction = FALSE +ShowTransCond = FALSE +StateLable = NAME +StateValueRadix = ORIG +State-LineColor = ID_BLACK +State-LineWidth = 1 +State-FillColor = ID_BLUE2 +State-TextColor = ID_WHITE +Init_State-LineColor = ID_BLACK +Init_State-LineWidth = 2 +Init_State-FillColor = ID_YELLOW2 +Init_State-TextColor = ID_BLACK +Reset_State-LineColor = ID_BLACK +Reset_State-LineWidth = 2 +Reset_State-FillColor = ID_YELLOW7 +Reset_State-TextColor = ID_BLACK +Trap_State-LineColor = ID_RED2 +Trap_State-LineWidth = 2 +Trap_State-FillColor = ID_CYAN5 +Trap_State-TextColor = ID_RED2 +State_Action-LineColor = ID_BLACK +State_Action-LineWidth = 1 +State_Action-FillColor = ID_WHITE +State_Action-TextColor = ID_BLACK +Junction-LineColor = ID_BLACK +Junction-LineWidth = 1 +Junction-FillColor = ID_GREEN2 +Junction-TextColor = ID_BLACK +Connection-LineColor = ID_BLACK +Connection-LineWidth = 1 +Connection-FillColor = ID_GRAY5 +Connection-TextColor = ID_BLACK +prefKey_Port-LineColor = ID_BLACK +prefKey_Port-LineWidth = 1 +prefKey_Port-FillColor = ID_ORANGE6 +prefKey_Port-TextColor = ID_YELLOW2 +Transition-LineColor = ID_BLACK +Transition-LineWidth = 1 +Transition-FillColor = ID_WHITE +Transition-TextColor = ID_BLACK +Trans_Condition-LineColor = ID_BLACK +Trans_Condition-LineWidth = 1 +Trans_Condition-FillColor = ID_WHITE +Trans_Condition-TextColor = ID_ORANGE2 +Trans_Action-LineColor = ID_BLACK +Trans_Action-LineWidth = 1 +Trans_Action-FillColor = ID_WHITE +Trans_Action-TextColor = ID_GREEN2 +SelectedSet-LineColor = ID_RED2 +SelectedSet-LineWidth = 1 +SelectedSet-FillColor = ID_RED2 +SelectedSet-TextColor = ID_WHITE +StickSet-LineColor = ID_ORANGE5 +StickSet-LineWidth = 1 +StickSet-FillColor = ID_PURPLE6 +StickSet-TextColor = ID_BLACK +HilightSet-LineColor = ID_RED5 +HilightSet-LineWidth = 1 +HilightSet-FillColor = ID_RED7 +HilightSet-TextColor = ID_BLUE5 +ControlPoint-LineColor = ID_BLACK +ControlPoint-LineWidth = 1 +ControlPoint-FillColor = ID_WHITE +Bundle-LineColor = ID_BLACK +Bundle-LineWidth = 1 +Bundle-FillColor = ID_WHITE +Bundle-TextColor = ID_BLUE4 +QtBackground-FillColor = ID_GRAY6 +prefKey_Link-LineColor = ID_ORANGE2 +prefKey_Link-LineWidth = 1 +Selection-LineColor = ID_BLUE2 +Selection-LineWidth = 1 +[FSM_Dlg-Print] +Orientation = Landscape +[FileBrowser] +nWaveOpenFsdbDirHistory = "\"/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/digital_top/verdplus_000.fsdb\"" +[Form] +version = Verdi_O-2018.09-SP2 +nMemory/nMemGetVariable.fm = 347,480,638,472 +wave/unknownSave.fm = 100,100,520,275 +wave/sigCPL.fm = 100,100,243,333 +[General] +autoSaveSession = FALSE +TclAutoSource = +cmd_enter_form = FALSE +SyncBrowserDir = TRUE +SignalCaseInSensitive = FALSE +ShowWndCtntDuringResizing = FALSE +version = Verdi_O-2018.09-SP2 +[GlobalProp] +ErrWindow_Font = Helvetica_M_R_12 +[Globals] +app_default_font = Bitstream Vera Sans,10,-1,5,50,0,0,0,0,0 +app_fixed_width_font = Courier,10,-1,5,50,0,0,0,0,0 +text_encoding = Unicode(utf8) +smart_resize = TRUE +smart_resize_child_limit = 2000 +tooltip_max_width = 200 +tooltip_max_height = 20 +tooltip_viewer_key = F3 +tooltip_display_time = 1000 +bookmark_name_length_limit = 12 +disable_tooltip = FALSE +auto_load_source = TRUE +max_array_size = 4096 +filter_when_typing = TRUE +filter_keep_children = TRUE +filter_syntax = Wildcards +filter_keystroke_interval = 800 +filter_case_sensitive = FALSE +filter_full_path = FALSE +load_detail_for_funcov = FALSE +sort_limit = 100000 +ignoreDBVersionChecking = FALSE +[HB] +ViewSchematic = FALSE +windowLayout = 0 0 804 500 182 214 804 148 +import_filter = *.v; *.vc; *.f +designTreeFont = *-adobe-courier-medium-r-*-*-12-*-*-*-*-*-iso8859-* +import_filter_vhdl = *.vhd; *.vhdl; *.f +import_default_language = Verilog +import_filter_verilog = *.v; *.vc; *.f +simulation_file_type = *.fsdb;*.fsdb.gz;*.fsdb.bz2;*.ff;*.dump +PrefetchViewableAnnot = TRUE +[Hier] +filterTimeout = 1500 +[ImportLiberty] +SearchPriority = .lib++ +bSkipStateCell = False +bImportPowerInfo = False +bSkipFFCell = False +bScpecifyCellNameCase = False +bSpecifyPinNameCase = False +CellNameToCase = +PinNameToCase = +[Language] +EditWindow_Font = COURIER12 +Background = ID_WHITE +Comment = ID_GRAY4 +Keyword = ID_BLUE5 +UserKeyword = ID_GREEN2 +Text = ID_BLACK +SelText = ID_WHITE +SelBackground = ID_BLUE2 +[Library.Ikos] +pack = ./work.lib++ +vital = ./work.lib++ +work = ./work.lib++ +std = ${dls_std}.lib++ +ieee = ${dls_ieee}.lib++ +synopsys = ${dls_synopsys}.lib++ +silc = ${dls_silc}.lib++ +ikos = ${dls_ikos}.lib++ +novas = ${VOYAGER_LIB_VHDL}/${VOYAGER_MACHINE}/novas.lib++ +[MDT] +ART_RF_SP = spr[0-9]*bx[0-9]* +ART_RF_2P = dpr[0-9]*bx[0-9]* +ART_SRAM_SP = spm[0-9]*bx[0-9]* +ART_SRAM_DP = dpm[0-9]*bx[0-9]* +VIR_SRAM_SP = hdsd1_[0-9]*x[0-9]*cm4sw1 +VIR_SRAM_DP = hdsd2_[0-9]*x[0-9]*cm4sw1 +VIR_RF_SP = rfsd1_[0-9]*x[0-9]*cm2sw0 +VIR_RF_DP = rfsd2_[0-9]*x[0-9]*cm2sw1 +VIR_STAR_SRAM_SP = shsd1_[0-9]*x[0-9]*cm4sw0 +[NPExpanding] +functiongroups = FALSE +modules = FALSE +[NPFilter] +showAssertion = TRUE +showCoverGroup = TRUE +showProperty = TRUE +showSequence = TRUE +showDollarUnit = TRUE +[OldFontRC] +Wave_legend_window_font = -f COURIER12 -c ID_CYAN5 +Wave_value_window_font = -f COURIER12 -c ID_CYAN5 +Wave_curve_window_font = -f COURIER12 -c ID_CYAN5 +Wave_group_name_font = -f COURIER12 -c ID_GREEN5 +Wave_ruler_value_font = -f COURIER12 -c ID_CYAN5 +Wave_analog_ruler_value_font = -f COURIER12 -c ID_CYAN5 +Wave_comment_string_font = -f COURIER12 -c ID_RED5 +HB_designTreeFont = *-adobe-courier-medium-r-*-*-12-*-*-*-*-*-iso8859-* +Text_font = COURIER12 +nMemory_font = Fixed 14 +Wave_getsignal_form_font = -f COURIER12 +Text_annotFont = Helvetica_M_R_10 +[OtherEditor] +cmd1 = "xterm -font 9x15 -fg black -bg gray -e" +name = "vi" +options = "+${CurLine} ${CurFullFileName}" +[Power] +PowerDownInstance = ID_GRAY1 +RetentionSignal = ID_YELLOW2 +IsolationSignal = ID_RED6 +LevelShiftedSignal = ID_GREEN6 +PowerSwitchObject = ID_ORANGE5 +AlwaysOnObject = ID_GREEN5 +PowerNet = ID_RED2 +GroundNet = ID_RED2 +SimulationOnly = ID_CYAN3 +SRSN/SPA = ID_CYAN3 +CNSSignal = ID_CYAN3 +RPTRSignal = ID_CYAN3 +AcknowledgeSignal = ID_CYAN3 +BoundaryPort = ID_CYAN3 +DisplayInstrumentedCell = TRUE +ShowCmdByFile = FALSE +ShowPstAnnot = FALSE +ShowIsoSymbol = TRUE +ExtractIsoSameNets = FALSE +AnnotateSignal = TRUE +HighlightPowerObject = TRUE +HighlightPowerDomain = TRUE +TraceThroughInstruLowPower = FALSE +BrightenPowerColorInSchematicWindow = FALSE +ShowAlias = FALSE +ShowVoltage = TRUE +MatchTreeNodesCaseInsensitive = FALSE +SearchHBNodeDynamically = FALSE +ContinueTracingSupplyOrLogicNet = FALSE +[Print] +PrinterName = lp +FileName = test.ps +PaperSize = A4 - 210x297 (mm) +ColorPrint = FALSE +[PropertyTools] +saveWaveformStat = TRUE +savePropStat = FALSE +savePropDtl = TRUE +[QtDialog] +ExpressionDialog_AppendLogicalExpression = 984,563,590,340 +ExpressionDialog = 890,486,778,493 +QwWarnMsgDlg = 979,811,600,250 +QwUserAskDlg = 1118,679,324,110 +openFileDlg = 978,491,602,483 +SetWindowTimeUnitDialog = 1062,689,433,86 +[Relationship] +hideRecursiceNode = FALSE +[Session Cache] +2 = string (session file name) +3 = string (session file name) +4 = string (session file name) +5 = string (session file name) +1 = /home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/digital_top/verdiLog/novas_autosave.ses +[Simulation] +scsPath = scsim +scsOption = +xlPath = verilog +xlOption = +ncPath = ncsim +ncOption = -f ncsim.args +osciPath = gdb +osciOption = +vcsPath = simv +vcsOption = +mtiPath = vsim +mtiOption = +vhncPath = ncsim +vhncOption = -log debussy.nc.log +mixncPath = ncsim +mixncOption = -log debussy.mixnc.log +speedsimPath = +speedsimOption = +mti_vlogPath = vsim +mti_vlogOption = novas_vlog +vcs_mixPath = simv +vcs_mixOption = -vhdlrun "-vhpi debussy:FSDBDumpCmd" +scs_mixPath = scsim +scs_mixOption = -vhpi debussy:FSDBDumpCmd +interactiveDebugging = {True, False} +KeepBreakPoints = False +ScsDebugAll = False +simType = {vcssv, xl, nc, vcs, mti, mti_vlog, vhnc, scs, mixnc} +thirdpartyIdx = -1 +iscCmdSep = FALSE +NoAppendOption = False +[SimulationPlus] +xlPath = verilog +xlOption = +ncPath = ncsim +ncOption = -f ncsim.args +vcsPath = simv +vcsOption = +mti_vlogPath = vsim +mti_vlogOption = novas_vlog +mtiPath = vsim +mtiOption = +vhncPath = ncsim +vhncOption = -log debussy.nc.log +speedsimPath = verilog +speedsimOption = +mixncPath = ncsim +mixncOption = -log debussy.mixnc.log +scsPath = scsim +scsOption = +vcs_mixPath = simv +vcs_mixOption = -vhdlrun "-vhpi debussy:FSDBDumpCmd" +scs_mixPath = scsim +scs_mixOption = -vhpi debussy:FSDBDumpCmd +vcs_svPath = simv +vcs_svOption = +simType = vcssv +thirdpartyIdx = -1 +interactiveDebugging = FALSE +KeepBreakPoints = FALSE +iscCmdSep = FALSE +ScsDebugAll = FALSE +NoAppendOption = FALSE +invokeSimPath = work +[SimulationPlus2] +eventDumpUnfinish = FALSE +[Source] +wordWrapOn = TRUE +viewReuse = TRUE +lineNumberOn = TRUE +warnOutdatedDlg = TRUE +showEncrypt = FALSE +loadInclude = FALSE +showColorForActive = FALSE +tabWidth = 8 +editor = vi +reload = Never +sync_active_to_source = TRUE +navigateAsColored = FALSE +navigateCovered = FALSE +navigateUncovered = TRUE +navigateExcluded = FALSE +not_ask_for_source_path = FALSE +expandMacroOn = TRUE +expandMacroInstancesThreshold = 10000 +[SourceVHDL] +vhSimType = ModelSim +ohSimType = VerilogXL +[TclShell] +nLineSize = 1024 +[Test] +verbose_progress = FALSE +[TestBenchBrowser] +-showUVMDynamicHierTreeWin = FALSE +[Text] +hdlTypeName = blue4 +hdlLibrary = blue4 +viewport = 396 392 445 487 +hdlOther = ID_BLACK +hdlComment = ID_GRAY1 +hdlKeyword = ID_BLUE5 +hdlEntity = ID_BLACK +hdlEntityInst = ID_BLACK +hdlSignal = ID_RED2 +hdlInSignal = ID_RED2 +hdlOutSignal = ID_RED2 +hdlInOutSignal = ID_RED2 +hdlOperator = ID_BLACK +hdlMinus = ID_BLACK +hdlSymbol = ID_BLACK +hdlString = ID_BLACK +hdlNumberBase = ID_BLACK +hdlNumber = ID_BLACK +hdlLiteral = ID_BLACK +hdlIdentifier = ID_BLACK +hdlSystemTask = ID_BLACK +hdlParameter = ID_BLACK +hdlIncFile = ID_BLACK +hdlDataFile = ID_BLACK +hdlCDSkipIf = ID_GRAY1 +hdlMacro = ID_BLACK +hdlMacroValue = ID_BLACK +hdlPlainText = ID_BLACK +hdlOvaId = ID_PURPLE2 +hdlPslId = ID_PURPLE2 +HvlEId = ID_BLACK +HvlVERAId = ID_BLACK +hdlEscSignal = ID_BLACK +hdlEscInSignal = ID_BLACK +hdlEscOutSignal = ID_BLACK +hdlEscInOutSignal = ID_BLACK +textBackgroundColor = ID_GRAY6 +textHiliteBK = ID_BLUE5 +textHiliteText = ID_WHITE +textTracedMark = ID_GREEN2 +textLineNo = ID_BLACK +textFoldedLineNo = ID_RED5 +textUserKeyword = ID_GREEN2 +textParaAnnotText = ID_BLACK +textFuncAnnotText = ID_BLUE2 +textAnnotText = ID_BLACK +textUserDefAnnotText = ID_BLACK +ComputedSignal = ID_PURPLE5 +textAnnotTextShadow = ID_WHITE +parenthesisBGColor = ID_YELLOW5 +codeInParenthesis = ID_CYAN5 +text3DLight = ID_WHITE +text3DShadow = ID_BLACK +textHvlDriver = ID_GREEN3 +textHvlLoad = ID_YELLOW3 +textHvlDriverLoad = ID_BLUE3 +irOutline = ID_RED2 +irDriver = ID_YELLOW5 +irLoad = ID_BLACK +irBookMark = ID_YELLOW2 +irIndicator = ID_WHITE +irBreakpoint = ID_GREEN5 +irCurLine = ID_BLUE5 +hdlVhEntity = ID_BLACK +hdlArchitecture = ID_BLACK +hdlPackage = ID_BLUE5 +hdlRefPackage = ID_BLUE5 +hdlAlias = ID_BLACK +hdlGeneric = ID_BLUE5 +specialAnnotShadow = ID_BLUE1 +hdlZeroInHead = ID_GREEN2 +hdlZeroInComment = ID_GREEN2 +hdlPslHead = ID_BLACK +hdlPslComment = ID_BLACK +hdlSynopsysHead = ID_GREEN2 +hdlSynopsysComment = ID_GREEN2 +pdmlIdentifier = ID_BLACK +pdmlCommand = ID_BLACK +pdmlMacro = ID_BLACK +font = COURIER12 +annotFont = Helvetica_M_R_10 +[Text.1] +viewport = -1 27 2560 1337 45 +[TextPrinter] +Orientation = Landscape +Indicator = FALSE +LineNum = TRUE +FontSize = 7 +Column = 2 +Annotation = TRUE +[Texteditor] +TexteditorFont = "Clean 14" +TexteditorBG = white +TexteditorFG = black +[ThirdParty] +ThirdPartySimTool = verisity surefire ikos finsim +[TurboEditor] +autoBackup = TRUE +[UserButton.mixnc] +Button1 = "Dump All Signals" "call fsdbDumpvars\n" +Button2 = "Next 1000 Time" "run 1000 -relative\n" +Button3 = "Next ? Time" "run ${Arg:Next Time} -relative\n" +Button4 = "Run Next" "run -next\n" +Button5 = "Run Step" "run -step\n" +Button6 = "Run Return" "run -return\n" +Button7 = "Show Variables" "value {${NCSelVars}}\n" +Button8 = "FSDB Ver" "call fsdbVersion" +Button9 = "Dump On" "call fsdbDumpon" +Button10 = "Dump Off" "call fsdbDumpoff" +Button11 = "All Tasks" "call" +Button12 = "Dump Selected Instance" "call fsdbDumpvars 1 ${SelInst}" +[UserButton.mti] +Button1 = "Dump All Signals" "fsdbDumpvars\n" +Button2 = "Next 1000 Time" "run 1000\n" +Button3 = "Next ? Time" "run ${Arg:Next Time}\n" +Button4 = "Show Variables" "exa ${SelVars}\n" +Button5 = "Force Variable" "force -freeze ${SelVar} ${Arg:New Value} 0\n" +Button6 = "Release Variable" "noforce ${SelVar}\n" +Button7 = "Deposit Variable" "force -deposit ${SelVar} ${Arg:New Value} 0\n" +[UserButton.mti_vlog] +Button1 = "Dump All Signals" "fsdbDumpvars\n" +Button2 = "Next 1000 Time" "run 1000\n" +Button3 = "Next ? Time" "run ${Arg:Next Time}\n" +Button4 = "Show Variables" "exa ${SelVars}\n" +Button5 = "Force Variable" "force -freeze ${SelVar} ${Arg:New Value} 0\n" +Button6 = "Release Variable" "noforce ${SelVar}\n" +Button7 = "Deposit Variable" "force -deposit ${SelVar} ${Arg:New Value} 0\n" +[UserButton.nc] +Button1 = "Dump All Signals" "call fsdbDumpvars\n" +Button2 = "Next 1000 Time" "run 1000 -relative\n" +Button3 = "Next ? Time" "run ${Arg:Next Time} -relative\n" +Button4 = "Run Next" "run -next\n" +Button5 = "Run Step" "run -step\n" +Button6 = "Run Return" "run -return\n" +Button7 = "Show Variables" "value {${NCSelVars}}\n" +[UserButton.scs] +Button1 = "Dump All Signals" "call fsdbDumpvars(0, \"${TopScope}\");\n" +Button2 = "Next 1000 Time" "run 1000 \n" +Button3 = "Next ? Time" "run ${Arg:Next Time} \n" +Button4 = "Run Step" "step\n" +Button5 = "Show Variables" "ls -v {${SelVars}}\n" +[UserButton.vhnc] +Button1 = "Dump All Signals" "call fsdbDumpvars\n" +Button2 = "Next 1000 Time" "run 1000 -relative\n" +Button3 = "Next ? Time" "run ${Arg:Next Time} -relative\n" +Button4 = "Run Next" "run -next\n" +Button5 = "Run Step" "run -step\n" +Button6 = "Run Return" "run -return\n" +Button7 = "Show Variables" "value {${NCSelVars}}\n" +[UserButton.xl] +Button13 = "Dump Off" "$fsdbDumpoff;\n" +Button12 = "Dump On" "$fsdbDumpon;\n" +Button11 = "Delete Focus" "$db_deletefocus(${treeSelScope});\n" +Button10 = "Set Focus" "$db_setfocus(${treeSelScope});\n" +Button9 = "Deposit Variable" "$deposit(${SelVar},${Arg:New Value});\n" +Button8 = "Release Variable" "release ${SelVar};\n" +Button7 = "Force Variable" "force ${SelVar} = ${Arg:New Value};\n" +Button6 = "Show Variables" "$showvars(${SelVars});\n" +Button5 = "Next ? Event" "$db_step(${Arg:Next Event});\n" +Button4 = "Next Event" "$db_step(1);\n" +Button3 = "Next ? Time" "#${Arg:Next Time} $stop;.\n" +Button2 = "Next 1000 Time" "#1000 $stop;.\n" +Button1 = "Dump All Signals" "$fsdbDumpvars;\n" +[VIA] +viaLogViewerDefaultRuleOneSearchForm = "share/VIA/Apps/PredefinedRules/Misc/Onesearch_rule.rc" +[VIA.oneSearch.preference] +DefaultDisplayTimeUnit = "1.000000ns" +DefaultLogTimeUnit = "1.000000ns" +[VIA.oneSearch.preference.vgifColumnSettingRC] +[VIA.oneSearch.preference.vgifColumnSettingRC.setting0] +parRuleSets = "" +[VIA.oneSearch.preference.vgifColumnSettingRC.setting0.column0] +name = Code +width = 60 +visualIndex = 2 +isHidden = TRUE +isUserChangeColumnVisible = FALSE +[VIA.oneSearch.preference.vgifColumnSettingRC.setting0.column1] +name = Type +width = 60 +visualIndex = 3 +isHidden = TRUE +isUserChangeColumnVisible = FALSE +[VIA.oneSearch.preference.vgifColumnSettingRC.setting0.column2] +name = Severity +width = 60 +visualIndex = 1 +isHidden = TRUE +isUserChangeColumnVisible = FALSE +[VIA.oneSearch.preference.vgifColumnSettingRC.setting0.column3] +name = Message +width = 2000 +visualIndex = 4 +isHidden = FALSE +isUserChangeColumnVisible = FALSE +[VIA.oneSearch.preference.vgifColumnSettingRC.setting0.column4] +name = Time +width = 60 +visualIndex = 0 +isHidden = TRUE +isUserChangeColumnVisible = FALSE +[Vi] +ViFont = "Clean 14" +ViBG = white +ViFG = black +[Wave] +ovaEventSuccessColor = -c ID_CYAN5 +ovaEventFailureColor = -c ID_RED5 +ovaBooleanSuccessColor = -c ID_CYAN5 +ovaBooleanFailureColor = -c ID_RED5 +ovaAssertSuccessColor = -c ID_GREEN5 +ovaAssertFailureColor = -c ID_RED5 +ovaForbidSuccessColor = -c ID_GREEN5 +SigGroupRuleFile = +DisplayFileName = FALSE +waveform_vertical_scroll_bar = TRUE +scope_to_save_with_macro +open_file_dir +open_rc_file_dir +viewPort = 0 27 2560 484 216 63 +signalSpacing = 5 +digitalSignalHeight = 15 +analogSignalHeight = 98 +commentSignalHeight = 98 +transactionSignalHeight = 98 +messageSignalHeight = 98 +minCompErrWidth = 4 +DragZoomTolerance = 4 +maxTransExpandedLayer = 10 +WaveMaxPoint = 512 +legendBackground = -c ID_BLACK +valueBackground = -c ID_BLACK +curveBackground = -c ID_BLACK +getSignalSignalList_BackgroundColor = -c ID_GRAY6 +glitchColor = -c ID_RED5 +cursor = -c ID_YELLOW5 -lw 1 -ls long_dashed +marker = -c ID_WHITE -lw 1 -ls dash_dot_l +usermarker = -c ID_GREEN5 -lw 1 -ls long_dashed +trace = -c ID_GRAY5 -lw 1 -ls long_dashed +grid = -c ID_WHITE -lw 1 -ls short_dashed +rulerBackground = -c ID_GRAY3 +rulerForeground = -c ID_YELLOW5 +busTextColor = -c ID_ORANGE8 +legendForeground = -c ID_CYAN5 +valueForeground = -c ID_CYAN5 +curveForeground = -c ID_CYAN5 +groupNameColor = -c ID_GREEN5 +commentStringColor = -c ID_RED5 +region(Active)Background = -c ID_YELLOW1 +region(NBA)Background = -c ID_RED1 +region(Re-Active)Background = -c ID_YELLOW3 +region(Re-NBA)Background = -c ID_RED3 +region(VHDL-Delta)Background = -c ID_ORANGE3 +region(Dump-Off)Background = -c ID_GRAY4 +High_Light = -c ID_GRAY2 +Input_Signal = -c ID_RED5 +Output_Signal = -c ID_GREEN5 +InOut_Signal = -c ID_BLUE5 +Net_Signal = -c ID_YELLOW5 +Register_Signal = -c ID_PURPLE5 +Verilog_Signal = -c ID_CYAN5 +VHDL_Signal = -c ID_ORANGE5 +SystemC_Signal = -c ID_BLUE7 +Dump_Off_Color = -c ID_BLUE2 +Compress_Bar_Color = -c ID_YELLOW4 +Vector_Dense_Block_Color = -c ID_ORANGE8 +Scalar_Dense_Block_Color = -c ID_GREEN6 +Analog_Dense_Block_Color = -c ID_PURPLE2 +Composite_Dense_Block_Color = -c ID_ORANGE5 +RPTR_Power_Off_Layer = -c ID_CYAN3 -stipple dots +DB_Power_Off_Layer = -c ID_BLUE4 -stipple dots +SPA_Driver_Power_Off_Layer = -c ID_ORANGE4 -stipple dots +SPA_Receiver_Power_Off_Layer = -c ID_GREEN5 -stipple dots +SRSN_Power_Off_Layer = -c ID_GREEN4 -stipple dots +Isolation_Power_Off_Layer = -c ID_RED4 -stipple dots +PD_Power_Off_Layer = -c ID_GRAY4 -stipple dots +Isolation_Layer = -c ID_RED4 -stipple vLine +Retention_Level_Trigger_Layer = -c ID_ORANGE1 -stipple fill_solid +Retention_Edge_Trigger_Layer = -c ID_YELLOW6 -stipple fill_solid +Driving_Power_Off_Layer = -c ID_YELLOW2 -stipple x +Toggle_Layer = -c ID_YELLOW4 -stipple slash +analogRealStyle = pwl +analogVoltageStyle = pwl +analogCurrentStyle = pwl +analogOthersStyle = pwl +busSignalLayer = -c ID_ORANGE8 +busXLayer = -c ID_RED5 +busZLayer = -c ID_ORANGE6 +busMixedLayer = -c ID_GREEN5 +busNotComputedLayer = -c ID_GRAY1 +busNoValueLayer = -c ID_BLUE2 +signalGridLayer = -c ID_WHITE +analogGridLayer = -c ID_GRAY6 +analogRulerLayer = -c ID_GRAY6 +keywordLayer = -c ID_RED5 +loadedLayer = -c ID_BLUE5 +loadingLayer = -c ID_BLACK +qdsCurMarkerLayer = -c ID_BLUE5 +qdsBrkMarkerLayer = -c ID_GREEN5 +qdsTrgMarkerLayer = -c ID_RED5 +arrowDefaultColor = -c ID_ORANGE6 +startNodeArrowColor = -c ID_WHITE +endNodeArrowColor = -c ID_YELLOW5 +propertyEventMatchColor = -c ID_GREEN5 +propertyEventNoMatchColor = -c ID_RED5 +propertyVacuousSuccessMatchColor = -c ID_YELLOW2 +propertyStatusBoundaryColor = -c ID_WHITE +propertyBooleanSuccessColor = -c ID_CYAN5 +propertyBooleanFailureColor = -c ID_RED5 +propertyAssertSuccessColor = -c ID_GREEN5 +propertyAssertFailureColor = -c ID_RED5 +propertyForbidSuccessColor = -c ID_GREEN5 +transactionForegroundColor = -c ID_YELLOW8 +transactionBackgroundColor = -c ID_BLACK +transactionHighLightColor = -c ID_CYAN6 +transactionRelationshipColor = -c ID_PURPLE6 +transactionErrorTypeColor = -c ID_RED5 +coverageFullyCoveredColor = -c ID_GREEN5 +coverageNoCoverageColor = -c ID_RED5 +coveragePartialCoverageColor = -c ID_YELLOW5 +coverageReferenceLineColor = -c ID_GRAY4 +messageForegroundColor = -c ID_YELLOW4 +messageBackgroundColor = -c ID_PURPLE1 +messageHighLightColor = -c ID_CYAN6 +messageInformationColor = -c ID_RED5 +ComputedAnnotColor = -c ID_PURPLE5 +fsvSecurityDataColor = -c ID_PURPLE3 +qdsAutoBusGroup = TRUE +qdsTimeStampMode = FALSE +qdsVbfBusOrderAscending = FALSE +openDumpFilter = *.fsdb;*.vf;*.jf +DumpFileFilter = *.vcd +RestoreSignalFilter = *.rc +SaveSignalFilter = *.rc +AddAliasFilter = *.alias;*.adb +CompareSignalFilter = *.err +ConvertFFFilter = *.vcd;*.out;*.tr0;*.xp;*.raw;*.wfm +Scroll_Ratio = 100 +Zoom_Ratio = 10 +EventSequence_SyncCursorTime = TRUE +EventSequence_Sorting = FALSE +EventSequence_RemoveGrid = FALSE +EventSequence_IsGridMode = FALSE +SetDefaultRadix_global = FALSE +DefaultRadix = Hex +SigSearchSignalMatchCase = FALSE +SigSearchSignalScopeOption = FALSE +SigSearchSignalSamenetInterface = FALSE +SigSearchSignalFullScope = FALSE +SigSearchSignalWithRegExp = FALSE +SigSearchDynamically = FALSE +SigDisplayBySelectionOrder = FALSE +SigDisplayRowMajor = FALSE +SigDragSelFollowColumn = FALSE +SigDisplayHierarchyBox = TRUE +SigDisplaySubscopeBox = TRUE +SigDisplayEmptyScope = TRUE +SigDisplaySignalNavigationBox = FALSE +SigDisplayFormBus = TRUE +SigShowSubProgram = TRUE +SigSearchScopeDynamically = TRUE +SigCollapseSubtreeNodes = FALSE +activeFileApplyToAnnotation = FALSE +GrpSelMode = TRUE +dispGridCount = FALSE +hierarchyName = FALSE +partial_level_name = FALSE +partial_level_head = 1 +partial_level_tail = 1 +displayMessageLabelOnly = TRUE +autoInsertDumpoffs = TRUE +displayMessageCallStack = FALSE +displayCallStackWithFullSections = TRUE +displayCallStackWithLastSection = FALSE +limitMessageMaxWidth = FALSE +messageMaxWidth = 50 +displayTransBySpecificColor = FALSE +fittedTransHeight = FALSE +snap = TRUE +gravitySnap = FALSE +displayLeadingZero = FALSE +displayGlitchs = FALSE +allfileTimeRange = FALSE +fixDelta = FALSE +displayCursorMarker = FALSE +autoUpdate = FALSE +restoreFromActiveFile = TRUE +restoreToEnd = FALSE +dispCompErr = TRUE +showMsgDes = TRUE +anaAutoFit = FALSE +anaAutoPattn = FALSE +anaAuto100VertFit = FALSE +displayDeltaY = FALSE +centerCursor = FALSE +denseBlockDrawing = TRUE +relativeFreqPrecision = 3 +showMarkerAbsolute = FALSE +showMarkerAdjacent = FALSE +showMarkerRelative = FALSE +showMarkerFrequency = FALSE +stickCursorMarkerOnWaveform = TRUE +keepMarkerAtEndTimeOfTransaction = FALSE +doubleClickToExpandTransaction = TRUE +expandTransactionAssociatedSignals = TRUE +expandTransactionAttributeSignals = FALSE +WaveExtendLastTick = TRUE +InOutSignal = FALSE +NetRegisterSignal = FALSE +VerilogVHDLSignal = FALSE +LabelMarker = TRUE +ResolveSymbolicLink = TRUE +signal_rc_abspath = TRUE +signal_rc_no_natural_bus_range = FALSE +save_scope_with_macro = FALSE +TipInSignalWin = FALSE +DisplayPackedSiganlInBitwiseManner = FALSE +DisplaySignalTypeAheadOfSignalName = TRUE ICON +TipInCurveWin = FALSE +MouseGesturesInCurveWin = TRUE +DisplayLSBsFirst = FALSE +PaintSpecificColorPattern = TRUE +ModuleName = TRUE +form_all_memory_signal = FALSE +formBusSignalFromPartSelects = FALSE +read_value_change_on_demand_for_drawing = FALSE +load_scopes_on_demand = on 5 +TransitionMode = TRUE +DisplayRadix = FALSE +SchemaX = FALSE +Hilight = TRUE +UseBeforeValue = FALSE +DisplayFileNameAheadOfSignalName = FALSE +DisplayFileNumberAheadOfSignalName = FALSE +DisplayValueSpace = TRUE +FitAnaByBusSize = FALSE +displayTransactionAttributeName = FALSE +expandOverlappedTrans = FALSE +dispSamplePointForAttrSig = TRUE +dispClassName = TRUE +ReloadActiveFileOnly = FALSE +NormalizeEVCD = FALSE +OverwriteAliasWithRC = TRUE +overlay_added_analog_signals = FALSE +case_insensitive = FALSE +vhdlVariableCalculate = TRUE +showError = TRUE +signal_vertical_scroll_bar = TRUE +showPortNameForDroppedInstance = FALSE +truncateFilePathInTitleBar = TRUE +filterPropVacuousSuccess = FALSE +includeLocalSignals = FALSE +encloseSignalsByGroup = TRUE +resaveSignals = TRUE +adjustBusPrefix = adjustBus_ +adjustBusBits = 1 +adjustBusSettings = 69889 +maskPowerOff = TRUE +maskIsolation = TRUE +maskRetention = TRUE +maskDrivingPowerOff = TRUE +maskToggle = TRUE +autoBackupSignals = off 5 "\"/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/digital_top/verdiLog\"" "\"novas_autosave_sig\"" +signal_rc_attribute = 65535 +signal_rc_alias_attribute = 0 +ConvertAttr1 = -inc FALSE +ConvertAttr2 = -hier FALSE +ConvertAttr3 = -ucase FALSE +ConvertAttr4 = -lcase FALSE +ConvertAttr5 = -org FALSE +ConvertAttr6 = -mem 24 +ConvertAttr7 = -deli . +ConvertAttr8 = -hier_scope FALSE +ConvertAttr9 = -inst_array FALSE +ConvertAttr10 = -vhdlnaming FALSE +ConvertAttr11 = -orgScope FALSE +analogFmtPrecision = Automatic 2 +confirmOverwrite = TRUE +confirmExit = TRUE +confirmGetAll = TRUE +printTimeRange = TRUE 0.000000 0.000000 0.000000 +printPageRange = TRUE 1 1 +printOption = 0 +printBasic = 1 0 0 FALSE FALSE +printDest = -printer {} +printSignature = {%f %h %t} {} +curveWindow_Drag&Drop_Mode = TRUE +hspiceIncOpenMode = TRUE +pcSelectMode = TRUE +hierarchyDelimiter = / +RecentFile1 = "\"/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/digital_top/verdplus_000.fsdb\"" +open_file_time_range = FALSE +value_window_aligment = Right +signal_window_alignment = Auto +ShowDeltaTime = TRUE +legend_window_font = -f COURIER12 -c ID_CYAN5 +value_window_font = -f COURIER12 -c ID_CYAN5 +curve_window_font = -f COURIER12 -c ID_CYAN5 +group_name_font = -f COURIER12 -c ID_GREEN5 +ruler_value_font = -f COURIER12 -c ID_CYAN5 +analog_ruler_value_font = -f COURIER12 -c ID_CYAN5 +comment_string_font = -f COURIER12 -c ID_RED5 +getsignal_form_font = -f COURIER12 +SigsCheckNum = on 1000 +filter_synthesized_net = off n +filterOutNet = on +filter_synthesized_instance = off +filterOutInstance = on +showGroupTree = TRUE +hierGroupDelim = / +MsgSeverityColor = {y \"Severity\"==\"1\" ID_RED5} {y \"Severity\"==\"2\" ID_RED6} {y \"Severity\"==\"3\" ID_RED7} {y \"Severity\"==\"4\" ID_RED8} {y \"Severity\"==\"5\" ID_ORANGE5} {y \"Severity\"==\"6\" ID_ORANGE6} {y \"Severity\"==\"7\" ID_ORANGE7} {y \"Severity\"==\"8\" \ +ID_GREEN7} {y \"Severity\"==\"9\" ID_GREEN6} {y \"Severity\"==\"10\" ID_GREEN5} +AutoApplySeverityColor = TRUE +AutoAdjustMsgWidthByLabel = off +verilogStrengthDispType = type1 +waveDblClkActiveTrace = on +autoConnectTBrowser = FALSE +connectTBrowserInContainer = TRUE +SEQShowComparisonIcon = TRUE +SEQAddDriverLoadInSameGroup = TRUE +autoSyncCursorMarker = FALSE +autoSyncHorizontalRange = FALSE +autoSyncVerticalScroll = FALSE +getSignalForm = 0 0 800 479 100 30 100 30 +[cov_hier_name_column] +justify = TRUE +[coverageColors] +sou_uncov = TRUE +sou_pc = TRUE +sou_cov = TRUE +sou_exuncov = TRUE +sou_excov = TRUE +sou_unreach = TRUE +sou_unreachcon = TRUE +sou_fillColor_uncov = red +sou_fillColor_pc = yellow +sou_fillColor_cov = green3 +sou_fillColor_exuncov = grey +sou_fillColor_excov = #3C9371 +sou_fillColor_unreach = grey +sou_fillColor_unreachcon = orange +numberOfBins = 6 +rangeMin_0 = 0 +rangeMax_0 = 20 +fillColor_0 = #FF6464 +rangeMin_1 = 20 +rangeMax_1 = 40 +fillColor_1 = #FF9999 +rangeMin_2 = 40 +rangeMax_2 = 60 +fillColor_2 = #FF8040 +rangeMin_3 = 60 +rangeMax_3 = 80 +fillColor_3 = #FFFF99 +rangeMin_4 = 80 +rangeMax_4 = 100 +fillColor_4 = #99FF99 +rangeMin_5 = 100 +rangeMax_5 = 100 +fillColor_5 = #64FF64 +[coveragesetting] +assertTopoMode = FALSE +urgAppendOptions = +group_instance_new_format_name = TRUE +showvalue = FALSE +computeGroupsScoreByRatio = FALSE +computeGroupsScoreByInst = FALSE +showConditionId = FALSE +showfullhier = FALSE +nameLeftAlignment = TRUE +showAllInfoInTooltips = FALSE +copyItemHvpName = TRUE +ignoreGroupWeight = FALSE +absTestName = FALSE +HvpMergeTool = +ShowMergeMenuItem = FALSE +fsmScoreMode = transition +[eco] +NameRule = +IsFreezeSilicon = FALSE +cellQuantityManagement = FALSE +ManageMode = INSTANCE_NAME +SpareCellsPinsManagement = TRUE +LogCommitReport = FALSE +InputPinStatus = 1 +OutputPinStatus = 2 +RevisedComponentColor = ID_BLUE5 +SpareCellColor = ID_RED5 +UserName = ICer +CommentFormat = Novas ECO updated by ${UserName} ${Date} ${Time} +PrefixN = eco_n +PrefixP = eco_p +PrefixI = eco_i +DefaultTieUpNet = 1'b1 +DefaultTieDownNet = 1'b0 +MultipleInstantiations = TRUE +KeepClockPinConnection = FALSE +KeepAsyncResetPinConnection = FALSE +ScriptFileModeType = 1 +MagmaScriptPower = VDD +MagmaScriptGround = GND +ShowModeMsg = TRUE +AstroScriptPower = VDD +AstroScriptGround = VSS +ClearFloatingPorts = FALSE +[eco_connection] +Port/NetIsUnique = TRUE +SerialNet = 0 +SerialPort = 0 +SerialInst = 0 +[finsim] +TPLanguage = Verilog +TPName = Super-FinSim +TPPath = TOP.sim +TPOption = +AddImportArgument = FALSE +LineBreakWithScope = FALSE +StopAfterCompileOption = -i +[hvpsetting] +importExcelXMLOptions = +use_test_loca_as_source = FALSE +autoTurnOffHideMeetGoalInit = FALSE +autoTurnOffHideMeetGoal = TRUE +autoTurnOffModifierInit = FALSE +autoTurnOffModifier = TRUE +enableNumbering = TRUE +autoSaveCheck = TRUE +autoSaveTime = 5 +ShowMissingScore = TRUE +enableFeatureId = FALSE +enable_HVP_FEAT_ID = FALSE +enableMeasureConcealment = FALSE +HvpCloneHierShowMsgAgain = 1 +HvpCloneHierType = tree +HvpCloneHierMetrics = Line,Cond,FSM,Toggle,Branch,Assert +autoRecalPlanAfterLoadingCovDBUserDataPlan = false +warnMeAutoRecalPlanAfterLoadingCovDBUserDataPlan = true +autoRecalExclWithPlan = false +warnMeAutoRecalExclWithPlan = true +autoRecalPlanWithExcl = false +warnMeAutoRecalPlanWithExcl = true +warnPopupWarnWhenMultiFilters = true +warnPopupWarnIfHvpReadOnly = true +unmappedObjsReportLevel = def_var_inst +unmappedObjsReportInst = true +unmappedObjsNumOfObjs = High +[ikos] +TPLanguage = VHDL +TPName = Voyager +TPPath = vsh +TPOption = -X +AddImportArgument = FALSE +LineBreakWithScope = FALSE +StopAfterCompileOption = -i +[imp] +options = NULL +libPath = NULL +libDir = NULL +[nCompare] +ErrorViewport = 80 180 800 550 +EditorViewport = 409 287 676 475 +EditorHeightWidth = 802 380 +WaveCommand = "novas" +WaveArgs = "-nWave" +[nCompare.Wnd0] +ViewByHier = FALSE +[nMemory] +dispMode = ADDR_HINT +addrColWidth = 120 +valueColWidth = 100 +showCellBitRangeWithAddr = TRUE +wordsShownInOneRow = 8 +syncCursorTime = FALSE +fixCellColumnWidth = FALSE +font = Courier 12 +[planColors] +plan_fillColor_inactive = lightGray +plan_fillColor_warning = orange +plan_fillColor_error = red +plan_fillColor_invalid = #F0DCDB +plan_fillColor_subplan = lightGray +[schematics] +viewport = 178 262 638 516 +schBackgroundColor = black lineSolid +schBackgroundColor_qt = #000000 qt_solidLine 1 +schBodyColor = orange6 lineSolid +schBodyColor_qt = #ffb973 qt_solidLine 1 +schAsmBodyColor = blue7 lineSolid +schAsmBodyColor_qt = #a5a5ff qt_solidLine 1 +schPortColor = orange6 lineSolid +schPortColor_qt = #ffb973 qt_solidLine 1 +schCellNameColor = Gray6 lineSolid +schCellNameColor_qt = #e0e0e0 qt_solidLine 1 +schCLKNetColor = red6 lineSolid +schCLKNetColor_qt = #ff7373 qt_solidLine 1 +schPWRNetColor = red4 lineSolid +schPWRNetColor_qt = #ff0101 qt_solidLine 1 +schGNDNetColor = cyan4 lineSolid +schGNDNetColor_qt = #01ffff qt_solidLine 1 +schSIGNetColor = green8 lineSolid +schSIGNetColor_qt = #cdffcd qt_solidLine 1 +schTraceColor = yellow4 lineSolid +schTraceColor_qt = #ffff01 qt_solidLine 2 +schBackAnnotateColor = white lineSolid +schBackAnnotateColor_qt = #ffffff qt_solidLine 1 +schValue0 = yellow4 lineSolid +schValue0_qt = #ffff01 qt_solidLine 1 +schValue1 = green3 lineSolid +schValue1_qt = #008000 qt_solidLine 1 +schValueX = red4 lineSolid +schValueX_qt = #ff0101 qt_solidLine 1 +schValueZ = purple7 lineSolid +schValueZ_qt = #ffcdff qt_solidLine 1 +dimColor = cyan2 lineSolid +dimColor_qt = #008080 qt_solidLine 1 +schPreSelColor = green4 lineDash +schPreSelColor_qt = #01ff01 qt_dashLine 2 +schSIGBusNetColor = green8 lineSolid +schSIGBusNetColor_qt = #cdffcd qt_solidLine +schGNDBusNetColor = cyan4 lineSolid +schGNDBusNetColor_qt = #01ffff qt_solidLine +schPWRBusNetColor = red4 lineSolid +schPWRBusNetColor_qt = #ff0101 qt_solidLine +schCLKBusNetColor = red6 lineSolid +schCLKBusNetColor_qt = #ff7373 qt_solidLine +schEdgeSensitiveColor = orange6 lineSolid +schEdgeSensitiveColor_qt = #ffb973 qt_solidLine +schAnnotColor = cyan4 lineSolid +schAnnotColor_qt = #01ffff qt_solidLine +schInstNameColor = orange6 lineSolid +schInstNameColor_qt = #ffb973 qt_solidLine +schPortNameColor = cyan4 lineSolid +schPortNameColor_qt = #01ffff qt_solidLine +schAsmLatchColor = cyan4 lineSolid +schAsmLatchColor_qt = #01ffff qt_solidLine +schAsmRegColor = cyan4 lineSolid +schAsmRegColor_qt = #01ffff qt_solidLine +schAsmTriColor = cyan4 lineSolid +schAsmTriColor_qt = #01ffff qt_solidLine +pre_select = True +ShowPassThroughNet = False +ComputedAnnotColor = ID_PURPLE5 +[schematics_print] +Signature = FALSE +DesignName = PCU +DesignerName = bai +SignatureLocation = LowerRight +MultiPage = TRUE +AutoSliver = FALSE +[sourceColors] +BackgroundActive = gray88 +BackgroundInactive = lightgray +InactiveCode = dimgray +Selection = darkblue +Standard = black +Keyword = blue +Comment = gray25 +Number = black +String = black +Identifier = darkred +Inline = green +colorIdentifier = green +Value = darkgreen +MacroBackground = white +Missing = #400040 +[specColors] +top_plan_linked = #ADFFA6 +top_plan_ignore = #D3D3D3 +top_plan_todo = #EECBAD +sub_plan_ignore = #919191 +sub_plan_todo = #EFAFAF +sub_plan_linked = darkorange +[spec_link_setting] +use_spline = true +goto_section = false +exclude_ignore = true +truncate_abstract = false +abstract_length = 999 +compare_strategy = 2 +auto_apply_margin = FALSE +margin_top = 0.80 +margin_bottom = 0.80 +margin_left = 0.50 +margin_right = 0.50 +margin_unit = inches +[spiceDebug] +ThroughNet = ID_YELLOW5 +InstrumentSig = ID_GREEN5 +InterfaceElement = ID_GREEN5 +Run-timeInterfaceElement = ID_BLUE5 +HighlightThroughNet = TRUE +HighlightInterfaceElement = TRUE +HighlightRuntimeInterfaceElement = TRUE +HighlightSameNet = TRUE +[surefire] +TPLanguage = Verilog +TPName = SureFire +TPPath = verilog +TPOption = +AddImportArgument = TRUE +LineBreakWithScope = TRUE +StopAfterCompileOption = -tcl +[turboSchema_Printer_Options] +Orientation = Landscape +[turbo_library] +bdb_load_scope = +[vdCovFilteringSearchesStrings] +keepLastUsedFiltersMaxNum = 10 +[verisity] +TPLanguage = Verilog +TPName = "Verisity SpeXsim" +TPPath = vlg +TPOption = +AddImportArgument = FALSE +LineBreakWithScope = TRUE +StopAfterCompileOption = -s +[wave.0] +viewPort = 0 27 2560 484 216 63 +[wave.1] +viewPort = 127 219 960 332 100 65 +[wave.2] +viewPort = 38 314 686 205 100 65 +[wave.3] +viewPort = 63 63 700 400 65 41 +[wave.4] +viewPort = 84 84 700 400 65 41 +[wave.5] +viewPort = 92 105 700 400 65 41 +[wave.6] +viewPort = 0 0 700 400 65 41 +[wave.7] +viewPort = 21 21 700 400 65 41 diff --git a/tb/digital_top/verdiLog/novas_autosave.ses b/tb/digital_top/verdiLog/novas_autosave.ses new file mode 100644 index 0000000..a040bbb --- /dev/null +++ b/tb/digital_top/verdiLog/novas_autosave.ses @@ -0,0 +1,82 @@ +@verdi rc file Version 1.0 +[General] +saveDB = TRUE +relativePath = FALSE +saveSingleView = FALSE +saveNWaveWinId = +VerdiVersion = Verdi_O-2018.09-SP2 +[KeyNote] +Line1 = Automatic Backup 0 +Line2 = Save Open Database Information: Yes +Line3 = Path Option: Absolute Paths +Line4 = Windows Option: All Windows +[TestBench] +ConstrViewShow = 0 +InherViewShow = 0 +FSDBMsgShow = 0 +AnnotationShow = 0 +Console = FALSE +powerDumped = 0 +[hb] +postSimFile = /home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/digital_top/verdplus_000.fsdb +syncTime = 8911000 +viewport = 0 27 2560 1337 0 0 102 2558 +activeNode = "TB.U_digital_top.U0_channel_top.U_ITCM.U_tsmc_dpram" +activeScope = "TB.U_digital_top.U0_channel_top.U_ITCM.U_tsmc_dpram" +activeFile = "../../rtl/memory/tsmc_dpram.v" +interactiveMode = False +viewType = Source +simulatorMode = False +sourceBeginLine = 69 +baMode = False +srcLineNum = True +AutoWrap = True +IdentifyFalseLogic = False +syncSignal = False +traceMode = Hierarchical +showTraceInSchema = True +paMode = False +funcMode = False +powerAwareAnnot = True +amsAnnot = True +traceCrossHier = True +DnDtraceCrossHierOnly = True +traceIncTopPort = False +leadingZero = False +signalPane = False +Scope1 = "TB.U_digital_top.U0_channel_top.U_ITCM.U_tsmc_dpram" +multipleSelection = 1 2 2 0 0 +sdfCheckUndef = FALSE +simFlow = FALSE +[hb.design] +importCmd = "-sverilog" "-f" "files.f" "-top" "TB" +invokeDir = /home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/digital_top +[hb.sourceTab.1] +scope = TB.U_digital_top.U0_channel_top.U_ITCM.U_tsmc_dpram +File = /home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/rtl/memory/tsmc_dpram.v +Line = 70 +[nMemoryManager] +WaveformFile = /home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/digital_top/verdplus_000.fsdb +UserActionNum = 0 +nMemWindowNum = 0 +[wave.0] +viewPort = 0 27 2560 484 216 63 +primaryWindow = TRUE +SessionFile = /home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/digital_top/verdiLog/novas_autosave.ses.wave.0 +displayGrid = FALSE +hierarchicalName = FALSE +snap = TRUE +displayLeadingZeros = FALSE +fixDelta = FALSE +displayCursorMarker = FALSE +autoUpdate = FALSE +highlightGlitchs = FALSE +waveformSyncCursorMarker = FALSE +waveformSyncHorizontalRange = FALSE +waveformSyncVerticalscroll = FALSE +displayErrors = TRUE +displayMsgSymbols = TRUE +showMsgDescriptions = TRUE +autoFit = FALSE +displayDeltaY = FALSE +centerCursor = FALSE diff --git a/tb/digital_top/verdiLog/novas_autosave.ses.config b/tb/digital_top/verdiLog/novas_autosave.ses.config new file mode 100644 index 0000000..8581b13 --- /dev/null +++ b/tb/digital_top/verdiLog/novas_autosave.ses.config @@ -0,0 +1,55 @@ +[qBaseWindowStateGroup] +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qDockerWindow_qDockContentType\Verdi=1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qDockerWindow_qDockContentType\hdlHier=1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qDockerWindow_qDockContentType\hdlSrc=1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qDockerWindow_qDockContentType\messageWindow=1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qDockerWindow_qDockContentType\svtbHier=1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qDockerWindow_qDockContentType\OneSearch=1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qDockerWindowMgr_saveDockerChildList\Verdi_1=7 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qDockerWindowMgr_saveDockerChildList\Verdi_1_0=widgetDock_hdlHier_1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qDockerWindowMgr_saveDockerChildList\Verdi_1_1=widgetDock_messageWindow_1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qDockerWindowMgr_saveDockerChildList\Verdi_1_2=widgetDock_hdlSrc_1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qDockerWindowMgr_saveDockerChildList\Verdi_1_3=widgetDock_signalList_1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qDockerWindowMgr_saveDockerChildList\Verdi_1_4=widgetDock_svtbHier_1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qDockerWindowMgr_saveDockerChildList\Verdi_1_5=windowDock_OneSearch_1 +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qDockerWindow_encode_to_relative_window_id_name=true +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qDockerWindow_restoreNewChildState=true +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\widgetDock_hdlHier_1\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\widgetDock_hdlHier_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\widgetDock_hdlHier_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\widgetDock_hdlHier_1\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\widgetDock_messageWindow_1\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\widgetDock_messageWindow_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\widgetDock_messageWindow_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\widgetDock_messageWindow_1\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\widgetDock_hdlSrc_1\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\widgetDock_hdlSrc_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\widgetDock_hdlSrc_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\widgetDock_hdlSrc_1\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\widgetDock_signalList_1\isVisible=false +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\widgetDock_svtbHier_1\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\widgetDock_svtbHier_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\widgetDock_svtbHier_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\widgetDock_svtbHier_1\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\windowDock_OneSearch_1\isNestedWindow=1 +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\windowDock_OneSearch_1\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\windowDock_OneSearch_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\windowDock_OneSearch_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\windowDock_OneSearch_1\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\windowDock_nWave_1\isNestedWindow=1 +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\windowDock_nWave_1\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\windowDock_nWave_1\SELECTION_MESSAGE_TOOLBAR=false +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\windowDock_nWave_1\qBaseWindowBeMax=0 +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\windowDock_nWave_1\qBaseWindowBeFix=0 +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qBaseDockWidgetGroup\windowDock_nWave_1\dockIsFloating=false +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\ProductVersion=201809 +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\Layout="@ByteArray(\0\0\0\xff\0\0\0\0\xfd\0\0\0\x2\0\0\0\x2\0\0\n\0\0\0\x2\xcb\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\x2\x8d\0\0\0\x89\0\xff\xff\xff\xfa\0\0\0\0\x1\0\0\0\x2\xfb\0\0\0(\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0h\0\x64\0l\0H\0i\0\x65\0r\0_\0\x31\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0*\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0s\0v\0t\0\x62\0H\0i\0\x65\0r\0_\0\x31\x1\0\0\0\0\xff\xff\xff\xff\0\0\0V\0\xff\xff\xff\xfb\0\0\0.\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0s\0i\0g\0n\0\x61\0l\0L\0i\0s\0t\0_\0\x31\0\0\0\0\xe9\0\0\0\xc6\0\0\0k\0\0\0k\xfb\0\0\0&\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0h\0\x64\0l\0S\0r\0\x63\0_\0\x31\x1\0\0\x2\x93\0\0\am\0\0\0k\0\xff\xff\xff\0\0\0\x3\0\0\n\0\0\0\x2\x1a\xfc\x1\0\0\0\x3\xfc\0\0\0\0\0\0\n\0\0\0\x2,\0\xff\xff\xff\xfa\0\0\0\x2\x1\0\0\0\x3\xfb\0\0\0\x34\0w\0i\0\x64\0g\0\x65\0t\0\x44\0o\0\x63\0k\0_\0m\0\x65\0s\0s\0\x61\0g\0\x65\0W\0i\0n\0\x64\0o\0w\0_\0\x31\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\xa0\0\xff\xff\xff\xfb\0\0\0,\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0O\0n\0\x65\0S\0\x65\0\x61\0r\0\x63\0h\0_\0\x31\x1\0\0\0\0\xff\xff\xff\xff\0\0\x2,\0\xff\xff\xff\xfb\0\0\0$\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0W\0\x61\0v\0\x65\0_\0\x31\x1\0\0\0\0\xff\xff\xff\xff\0\0\x1-\0\xff\xff\xff\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x33\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\xfb\0\0\0(\0w\0i\0n\0\x64\0o\0w\0\x44\0o\0\x63\0k\0_\0n\0M\0\x65\0m\0o\0r\0y\0_\0\x34\0\0\0\x5\x3\0\0\x4\xfd\0\0\0\0\0\0\0\0\0\0\n\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x6\0\0\0\x2\0\0\0\x10\0\0\0.\0H\0\x42\0_\0I\0M\0P\0O\0R\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0N\0\x45\0W\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0$\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0(\0H\0\x42\0_\0S\0I\0G\0N\0\x41\0L\0_\0P\0\x41\0N\0\x45\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0~\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0H\0\x42\0_\0M\0U\0L\0T\0I\0_\0T\0\x41\0\x42\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xa2\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0*\0H\0\x42\0_\0\x45\0\x44\0I\0T\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\0\xc6\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\x1\0\0\0\xea\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0H\0\x42\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x1\x18\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0.\0H\0\x42\0_\0S\0O\0U\0R\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\x1\0\0\x2/\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0,\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0T\0O\0G\0G\0L\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe3\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xbb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x30\0t\0o\0o\0l\0\x62\0\x61\0r\0H\0\x42\0_\0P\0R\0O\0\x44\0T\0Y\0P\0\x45\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xf8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0<\0\x41\0\x42\0V\0_\0\x41\0\x44\0\x44\0_\0T\0\x45\0M\0P\0O\0R\0\x41\0R\0Y\0_\0\x41\0S\0S\0\x45\0R\0T\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x2\xe8\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x1e\0U\0V\0M\0_\0\x41\0W\0\x41\0R\0\x45\0_\0\x44\0\x45\0\x42\0U\0G\0\0\0\x3\f\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0 \0V\0\x43\0_\0\x41\0P\0P\0S\0_\0T\0O\0O\0L\0_\0\x42\0O\0X\x1\0\0\x3\x1\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x14\0L\0O\0G\0_\0V\0I\0\x45\0W\0\x45\0R\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0$\0\x41\0M\0S\0_\0\x43\0O\0N\0\x46\0I\0G\0_\0T\0O\0O\0L\0\x42\0\x41\0R\x1\0\0\x3%\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x3\0\0\0\x30\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0&\0H\0\x42\0_\0\x42\0\x41\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\x1\xfb\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x32\0t\0o\0o\0l\0\x42\0\x61\0r\0\x46\0o\0r\0m\0\x61\0l\0V\0\x65\0r\0i\0\x66\0i\0\x63\0\x61\0t\0i\0o\0n\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x4\0\0\0>\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0R\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0W\0I\0N\0\x44\0_\0U\0N\0\x44\0O\0_\0R\0\x45\0\x44\0O\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x5\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0@\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0R\0\x45\0V\0\x45\0R\0S\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\x1\x95\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x38\0H\0\x42\0_\0P\0O\0W\0\x45\0R\0_\0T\0R\0\x41\0\x43\0\x45\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0T\0\x42\0\x42\0R\0_\0\x44\0\x45\0\x42\0U\0G\0_\0V\0S\0I\0M\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0:\0N\0O\0V\0\x41\0S\0_\0\x45\0M\0U\0L\0\x41\0T\0I\0O\0N\0_\0\x44\0\x45\0\x42\0U\0G\0_\0\x43\0O\0M\0M\0\x41\0N\0\x44\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0\0\0\0\x2\0\0\0\x1\0\0\0\x1a\0\x43\0V\0G\0_\0\x43\0\x45\0R\0_\0P\0\x41\0N\0\x45\0L\0\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)" +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\isNestedWindow=0 +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\isVisible=true +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\size=@Size(2560 1337) +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\geometry_x=-1 +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\geometry_y=27 +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\geometry_width=2560 +Verdi_1\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\geometry_height=1337 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qDockerWindow_qDockContentType\nWave=1 +qDockerWindowMgr_C\qBaseWindowRestoreStateGroup\qBaseWindow_saveRestoreSession_group\qDockerWindowMgr_saveDockerChildList\Verdi_1_6=windowDock_nWave_1 diff --git a/tb/digital_top/verdiLog/novas_autosave.ses.png b/tb/digital_top/verdiLog/novas_autosave.ses.png new file mode 100644 index 0000000..3fbe999 Binary files /dev/null and b/tb/digital_top/verdiLog/novas_autosave.ses.png differ diff --git a/tb/digital_top/verdiLog/novas_autosave.ses.wave.0 b/tb/digital_top/verdiLog/novas_autosave.ses.wave.0 new file mode 100644 index 0000000..67be6de --- /dev/null +++ b/tb/digital_top/verdiLog/novas_autosave.ses.wave.0 @@ -0,0 +1,97 @@ +Magic 271485 +Revision Verdi_O-2018.09-SP2 + +; Window Layout +viewPort 0 27 2560 484 216 63 + +; File list: +; openDirFile [-d delimiter] [-s time_offset] [-rf auto_bus_rule_file] path_name file_name +openDirFile -d / "" "/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/digital_top/verdplus_000.fsdb" + +; file time scale: +; fileTimeScale ### s|ms|us|ns|ps + +; signal spacing: +signalSpacing 5 + +; windowTimeUnit is used for zoom, cursor & marker +; waveform viewport range +zoom 0.000000 0.100000 +cursor 8911000.000000 +marker 0.000000 + +; user define markers +; userMarker time_pos marker_name color linestyle +; visible top row signal index +top 4 +; marker line index +markerPos 21 + +; Run Time Signal and Member +; userBusMem member ... +; saveRunSig name +activeDirFile "" "/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/digital_top/verdplus_000.fsdb" +userBusMem /TB/U_digital_top/U0_channel_top/U_awg_top/U_mod_nco/inst_p_nco/inst_ph2amp_0/inst_sin_op/pha_indx_lsb[0] +userBusMem /TB/U_digital_top/U0_channel_top/U_awg_top/U_mod_nco/inst_p_nco/inst_ph2amp_0/inst_sin_op/pha_indx_lsb[1] +userBusMem /TB/U_digital_top/U0_channel_top/U_awg_top/U_mod_nco/inst_p_nco/inst_ph2amp_0/inst_sin_op/pha_indx_lsb[2] +userBusMem /TB/U_digital_top/U0_channel_top/U_awg_top/U_mod_nco/inst_p_nco/inst_ph2amp_0/inst_sin_op/pha_indx_lsb[3] +userBusMem /TB/U_digital_top/U0_channel_top/U_awg_top/U_mod_nco/inst_p_nco/inst_ph2amp_0/inst_sin_op/pha_indx_lsb[4] +userBusMem /TB/U_digital_top/U0_channel_top/U_awg_top/U_mod_nco/inst_p_nco/inst_ph2amp_0/inst_sin_op/pha_indx_lsb[5] +userBusMem /TB/U_digital_top/U0_channel_top/U_awg_top/U_mod_nco/inst_p_nco/inst_ph2amp_0/inst_sin_op/pha_indx_lsb[6] +userBusMem /TB/U_digital_top/U0_channel_top/U_awg_top/U_mod_nco/inst_p_nco/inst_ph2amp_0/inst_sin_op/pha_indx_lsb[7] +userBusMem /TB/U_digital_top/U0_channel_top/U_awg_top/U_mod_nco/inst_p_nco/inst_ph2amp_0/inst_sin_op/pha_indx_lsb[8] +userBusMem /TB/U_digital_top/U0_channel_top/U_awg_top/U_mod_nco/inst_p_nco/inst_ph2amp_0/inst_sin_op/pha_indx_lsb[9] +userBusMem /TB/U_digital_top/U0_channel_top/U_awg_top/U_mod_nco/inst_p_nco/inst_ph2amp_0/inst_sin_op/pha_indx_lsb[10] +userBusMem /TB/U_digital_top/U0_channel_top/U_awg_top/U_mod_nco/inst_p_nco/inst_ph2amp_0/inst_sin_op/pha_indx_lsb[11] +userBusMem /TB/U_digital_top/U0_channel_top/U_awg_top/U_mod_nco/inst_p_nco/inst_ph2amp_0/inst_sin_op/pha_indx_lsb[12] +userBusMem /TB/U_digital_top/U0_channel_top/U_awg_top/U_mod_nco/inst_p_nco/inst_ph2amp_0/inst_sin_op/pha_indx_lsb[13] +userBusMem /TB/U_digital_top/U0_channel_top/U_awg_top/U_mod_nco/inst_p_nco/inst_ph2amp_0/inst_sin_op/pha_indx_lsb[14] +userBusMem /TB/U_digital_top/U0_channel_top/U_awg_top/U_mod_nco/inst_p_nco/inst_ph2amp_0/inst_sin_op/pha_indx_lsb[15] +saveRunSig "pha_indx_lsb[0:15]" + +; event list +; addEvent event_name event_expression +; curEvent event_name + + + +COMPLEX_EVENT_BEGIN + + +COMPLEX_EVENT_END + + + +; toolbar current search type +; curSTATUS search_type +curSTATUS ByChange + + +addGroup "G1" +activeDirFile "" "/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/digital_top/verdplus_000.fsdb" +addSignal -h 15 /TB/U_digital_top/sync_in +addSignal -h 15 -holdScope sync_out +addSignal -h 15 /TB/U_digital_top/U0_channel_top/ctrl_wren +addSignal -h 15 -holdScope xy_dsp_dout0[15:0] +addSignal -h 15 -holdScope xy_dsp_dout1[15:0] +addSignal -h 15 -holdScope xy_dsp_dout2[15:0] +addSignal -h 15 -holdScope xy_dsp_dout3[15:0] +addSignal -h 15 -holdScope xy_dsp_dout4[15:0] +addSignal -h 15 -holdScope xy_dsp_dout5[15:0] +addSignal -h 15 -holdScope xy_dsp_dout6[15:0] +addSignal -h 15 -holdScope xy_dsp_dout7[15:0] +addSignal -h 15 -holdScope xy_dsp_dout8[15:0] +addSignal -h 15 -holdScope xy_dsp_dout9[15:0] +addSignal -h 15 -holdScope xy_dsp_dout10[15:0] +addSignal -h 15 -holdScope xy_dsp_dout11[15:0] +addSignal -h 15 -holdScope xy_dsp_dout12[15:0] +addSignal -h 15 -holdScope xy_dsp_dout13[15:0] +addSignal -h 15 -holdScope xy_dsp_dout14[15:0] +addSignal -h 15 -holdScope xy_dsp_dout15[15:0] +addSignal -h 15 -holdScope xy_dsp_dout_vld +addSignal -h 15 /TB/U_digital_top/clk +addGroup "G2" + +; getSignalForm Scope Hierarchy Status +; active file of getSignalForm + diff --git a/tb/digital_top/verdiLog/novas_ones_IC_EDA_74196.log.result b/tb/digital_top/verdiLog/novas_ones_IC_EDA_74196.log.result new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/verdiLog/pes.bat b/tb/digital_top/verdiLog/pes.bat new file mode 100644 index 0000000..7c6e4ac --- /dev/null +++ b/tb/digital_top/verdiLog/pes.bat @@ -0,0 +1,3 @@ +where +detach +quit diff --git a/tb/digital_top/verdiLog/sysinfo.log b/tb/digital_top/verdiLog/sysinfo.log new file mode 100644 index 0000000..01a43bd --- /dev/null +++ b/tb/digital_top/verdiLog/sysinfo.log @@ -0,0 +1,2229 @@ +========== uname -a ========== +Linux IC_EDA 3.10.0-1160.53.1.el7.x86_64 #1 SMP Fri Jan 14 13:59:45 UTC 2022 x86_64 x86_64 x86_64 GNU/Linux +------------- end(uname -a) ------------- + +========== limit ========== +cputime unlimited +filesize unlimited +datasize unlimited +stacksize 8192 kbytes +coredumpsize 0 kbytes +memoryuse unlimited +vmemoryuse unlimited +descriptors 4096 +memorylocked 64 kbytes +maxproc 4096 +maxlocks unlimited +maxsignal 39142 +maxmessage 819200 +maxnice 0 +maxrtprio 0 +maxrttime unlimited +------------- end(limit) ------------- +========== xdpyinfo ========== +name of display: :0 +version number: 11.0 +vendor string: The X.Org Foundation +vendor release number: 12004000 +X.Org version: 1.20.4 +maximum request size: 16777212 bytes +motion buffer size: 256 +bitmap unit, bit order, padding: 32, LSBFirst, 32 +image byte order: LSBFirst +number of supported pixmap formats: 7 +supported pixmap formats: + depth 1, bits_per_pixel 1, scanline_pad 32 + depth 4, bits_per_pixel 8, scanline_pad 32 + depth 8, bits_per_pixel 8, scanline_pad 32 + depth 15, bits_per_pixel 16, scanline_pad 32 + depth 16, bits_per_pixel 16, scanline_pad 32 + depth 24, bits_per_pixel 32, scanline_pad 32 + depth 32, bits_per_pixel 32, scanline_pad 32 +keycode range: minimum 8, maximum 255 +focus: window 0x2e006f9, revert to Parent +number of extensions: 28 + BIG-REQUESTS + Composite + DAMAGE + DOUBLE-BUFFER + DPMS + DRI2 + GLX + Generic Event Extension + MIT-SCREEN-SAVER + MIT-SHM + Present + RANDR + RECORD + RENDER + SECURITY + SHAPE + SYNC + VMWARE_CTRL + X-Resource + XC-MISC + XFIXES + XFree86-DGA + XFree86-VidModeExtension + XINERAMA + XInputExtension + XKEYBOARD + XTEST + XVideo +default screen number: 0 +number of screens: 1 + +screen #0: + dimensions: 2560x1440 pixels (677x381 millimeters) + resolution: 96x96 dots per inch + depths (7): 24, 1, 4, 8, 15, 16, 32 + root window id: 0x3ad + depth of root window: 24 planes + number of colormaps: minimum 1, maximum 1 + default colormap: 0x20 + default number of colormap cells: 256 + preallocated pixels: black 0, white 16777215 + options: backing-store WHEN MAPPED, save-unders NO + largest cursor: 64x64 + current input event mask: 0xda4033 + KeyPressMask KeyReleaseMask EnterWindowMask + LeaveWindowMask KeymapStateMask StructureNotifyMask + SubstructureNotifyMask SubstructureRedirectMask PropertyChangeMask + ColormapChangeMask + number of visuals: 270 + default visual id: 0x21 + visual: + visual id: 0x21 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x22 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2a1 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2a2 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2a3 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2a4 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2a5 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2a6 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2a7 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2a8 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2a9 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2aa + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2ab + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2ac + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2ad + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2ae + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2af + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2b0 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2b1 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2b2 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2b3 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2b4 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2b5 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2b6 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2b7 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2b8 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2b9 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2ba + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2bb + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2bc + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2bd + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2be + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2bf + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2c0 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2c1 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2c2 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2c3 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2c4 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2c5 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2c6 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2c7 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2c8 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2c9 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2ca + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2cb + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2cc + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2cd + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2ce + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2cf + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2d0 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2d1 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2d2 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2d3 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2d4 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2d5 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2d6 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2d7 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2d8 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2d9 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2da + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2db + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2dc + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2dd + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2de + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2df + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2e0 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2e1 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2e2 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2e3 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2e4 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2e5 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2e6 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2e7 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2e8 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2e9 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2ea + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2eb + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2ec + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2ed + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2ee + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2ef + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2f0 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2f1 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2f2 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2f3 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2f4 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2f5 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2f6 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2f7 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2f8 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2f9 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2fa + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2fb + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2fc + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2fd + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2fe + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x2ff + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x300 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x301 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x302 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x303 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x304 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x305 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x306 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x307 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x308 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x309 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x30a + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x30b + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x30c + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x30d + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x30e + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x30f + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x310 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x311 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x312 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x313 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x314 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x315 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x316 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x317 + class: TrueColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x318 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x319 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x31a + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x31b + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x31c + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x31d + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x31e + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x31f + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x320 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x321 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x322 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x323 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x324 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x325 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x326 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x327 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x328 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x329 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x32a + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x32b + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x32c + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x32d + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x32e + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x32f + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x330 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x331 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x332 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x333 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x334 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x335 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x336 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x337 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x338 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x339 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x33a + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x33b + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x33c + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x33d + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x33e + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x33f + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x340 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x341 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x342 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x343 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x344 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x345 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x346 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x347 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x348 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x349 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x34a + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x34b + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x34c + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x34d + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x34e + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x34f + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x350 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x351 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x352 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x353 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x354 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x355 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x356 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x357 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x358 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x359 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x35a + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x35b + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x35c + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x35d + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x35e + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x35f + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x360 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x361 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x362 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x363 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x364 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x365 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x366 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x367 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x368 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x369 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x36a + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x36b + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x36c + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x36d + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x36e + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x36f + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x370 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x371 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x372 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x373 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x374 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x375 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x376 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x377 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x378 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x379 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x37a + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x37b + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x37c + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x37d + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x37e + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x37f + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x380 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x381 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x382 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x383 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x384 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x385 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x386 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x387 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x388 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x389 + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x38a + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x38b + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x38c + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x38d + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x38e + class: DirectColor + depth: 24 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x66 + class: TrueColor + depth: 32 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x38f + class: TrueColor + depth: 32 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x390 + class: TrueColor + depth: 32 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x391 + class: TrueColor + depth: 32 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x392 + class: TrueColor + depth: 32 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x393 + class: TrueColor + depth: 32 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x394 + class: TrueColor + depth: 32 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x395 + class: TrueColor + depth: 32 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x396 + class: TrueColor + depth: 32 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x397 + class: TrueColor + depth: 32 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x398 + class: TrueColor + depth: 32 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x399 + class: TrueColor + depth: 32 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x39a + class: TrueColor + depth: 32 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x39b + class: TrueColor + depth: 32 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x39c + class: TrueColor + depth: 32 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x39d + class: TrueColor + depth: 32 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x39e + class: TrueColor + depth: 32 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x39f + class: TrueColor + depth: 32 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x3a0 + class: TrueColor + depth: 32 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x3a1 + class: TrueColor + depth: 32 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x3a2 + class: TrueColor + depth: 32 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x3a3 + class: TrueColor + depth: 32 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x3a4 + class: TrueColor + depth: 32 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x3a5 + class: TrueColor + depth: 32 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x3a6 + class: TrueColor + depth: 32 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x3a7 + class: TrueColor + depth: 32 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x3a8 + class: TrueColor + depth: 32 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x3a9 + class: TrueColor + depth: 32 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x3aa + class: TrueColor + depth: 32 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits + visual: + visual id: 0x3ab + class: TrueColor + depth: 32 planes + available colormap entries: 256 per subfield + red, green, blue masks: 0xff0000, 0xff00, 0xff + significant bits in color specification: 8 bits +------------- end(xdpyinfo) ------------- +========== Environment Variables ========== +LC_PAPER=zh_CN.UTF-8 +XDG_VTNR=1 +DISABLE_LIBRARY_MAP_CHECK=1 +XDG_SESSION_ID=1 +SSH_AGENT_PID=10423 +XLOCALEDIR=/home/synopsys/verdi/Verdi_O-2018.09-SP2/etc/access/locale +DBUS_STARTER_ADDRESS=unix:abstract=/tmp/dbus-DIYqQioq7q,guid=a50f166bc97a0937429a75936639b5b6 +LC_MONETARY=zh_CN.UTF-8 +HOSTNAME=IC_EDA +XKEYSYMDB=/home/synopsys/verdi/Verdi_O-2018.09-SP2/etc/access/XKeysymDB2.1 +SIGNAL_BASE_EXTRACTION=1 +IMSETTINGS_INTEGRATE_DESKTOP=yes +NOVAS_SYNC_MOTIF_DISP= +TERM=xterm-256color +XDG_MENU_PREFIX=gnome- +VTE_VERSION=5204 +SHELL=/bin/bash +HISTSIZE=1000 +MAKEFLAGS= +NOVAS_VERDI_SVTB_ALPHA=1 +NOVAS_WAVE_REDRAW_ALLVC=1 +GNOME_TERMINAL_SCREEN=/org/gnome/Terminal/screen/b3faae4f_07ba_4ce6_b83c_c942094b753b +QUESTASIM_HOME=/home/mentor/questasim +SPS_FONT_PATH=/home/synopsys/verdi/Verdi_O-2018.09-SP2/font +LC_NUMERIC=zh_CN.UTF-8 +QTDIR=/usr/lib/qt-3.3 +SPS_XFONT_PATH=/home/synopsys/verdi/Verdi_O-2018.09-SP2/XFont +QTINC=/usr/lib/qt-3.3/include +LC_ALL=C +IMSETTINGS_MODULE=none +QT_GRAPHICSSYSTEM_CHECKED=1 +USER=ICer +WAVE_REDRAW_ALLVC=1 +PS_HWPC=OFF +LD_LIBRARY_PATH=/home/synopsys/verdi/Verdi_O-2018.09-SP2/platform/LINUXAMD64/bin:/home/synopsys/verdi/Verdi_O-2018.09-SP2/platform/LINUXAMD64/lib/Qt:/home/synopsys/verdi/Verdi_O-2018.09-SP2/platform/LINUXAMD64/lib/tbb:/home/synopsys/verdi/Verdi_O-2018.09-SP2/etc/lib/libstdc++/LINUXAMD64:/home/synopsys/verdi/Verdi_O-2018.09-SP2/share/NPI/lib/LINUXAMD64::/home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/lib/LINUX64:/home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/IUS/LINUX64/boot +LS_COLORS=rs=0:di=38;5;27:ln=38;5;51:mh=44;38;5;15:pi=40;38;5;11:so=38;5;13:do=38;5;5:bd=48;5;232;38;5;11:cd=48;5;232;38;5;3:or=48;5;232;38;5;9:mi=05;48;5;232;38;5;15:su=48;5;196;38;5;15:sg=48;5;11;38;5;16:ca=48;5;196;38;5;226:tw=48;5;10;38;5;16:ow=48;5;10;38;5;21:st=48;5;21;38;5;15:ex=38;5;34:*.tar=38;5;9:*.tgz=38;5;9:*.arc=38;5;9:*.arj=38;5;9:*.taz=38;5;9:*.lha=38;5;9:*.lz4=38;5;9:*.lzh=38;5;9:*.lzma=38;5;9:*.tlz=38;5;9:*.txz=38;5;9:*.tzo=38;5;9:*.t7z=38;5;9:*.zip=38;5;9:*.z=38;5;9:*.Z=38;5;9:*.dz=38;5;9:*.gz=38;5;9:*.lrz=38;5;9:*.lz=38;5;9:*.lzo=38;5;9:*.xz=38;5;9:*.bz2=38;5;9:*.bz=38;5;9:*.tbz=38;5;9:*.tbz2=38;5;9:*.tz=38;5;9:*.deb=38;5;9:*.rpm=38;5;9:*.jar=38;5;9:*.war=38;5;9:*.ear=38;5;9:*.sar=38;5;9:*.rar=38;5;9:*.alz=38;5;9:*.ace=38;5;9:*.zoo=38;5;9:*.cpio=38;5;9:*.7z=38;5;9:*.rz=38;5;9:*.cab=38;5;9:*.jpg=38;5;13:*.jpeg=38;5;13:*.gif=38;5;13:*.bmp=38;5;13:*.pbm=38;5;13:*.pgm=38;5;13:*.ppm=38;5;13:*.tga=38;5;13:*.xbm=38;5;13:*.xpm=38;5;13:*.tif=38;5;13:*.tiff=38;5;13:*.png=38;5;13:*.svg=38;5;13:*.svgz=38;5;13:*.mng=38;5;13:*.pcx=38;5;13:*.mov=38;5;13:*.mpg=38;5;13:*.mpeg=38;5;13:*.m2v=38;5;13:*.mkv=38;5;13:*.webm=38;5;13:*.ogm=38;5;13:*.mp4=38;5;13:*.m4v=38;5;13:*.mp4v=38;5;13:*.vob=38;5;13:*.qt=38;5;13:*.nuv=38;5;13:*.wmv=38;5;13:*.asf=38;5;13:*.rm=38;5;13:*.rmvb=38;5;13:*.flc=38;5;13:*.avi=38;5;13:*.fli=38;5;13:*.flv=38;5;13:*.gl=38;5;13:*.dl=38;5;13:*.xcf=38;5;13:*.xwd=38;5;13:*.yuv=38;5;13:*.cgm=38;5;13:*.emf=38;5;13:*.axv=38;5;13:*.anx=38;5;13:*.ogv=38;5;13:*.ogx=38;5;13:*.aac=38;5;45:*.au=38;5;45:*.flac=38;5;45:*.mid=38;5;45:*.midi=38;5;45:*.mka=38;5;45:*.mp3=38;5;45:*.mpc=38;5;45:*.ogg=38;5;45:*.ra=38;5;45:*.wav=38;5;45:*.axa=38;5;45:*.oga=38;5;45:*.spx=38;5;45:*.xspf=38;5;45: +GNOME_TERMINAL_SERVICE=:1.108 +SIGNAL_BASED_BA=0 +XNLSPATH=/home/synopsys/verdi/Verdi_O-2018.09-SP2/etc/access/nls +TCL_LIBRARY=/home/synopsys/verdi/Verdi_O-2018.09-SP2/etc/access/tcl86_library +MAKE_TERMOUT=/dev/pts/3 +SSH_AUTH_SOCK=/run/user/1000/keyring/ssh +DVE_HOME=/home/synopsys/vcs/O-2018.09-SP2 +MAKELEVEL=1 +SESSION_MANAGER=local/unix:@/tmp/.ICE-unix/10289,unix/unix:/tmp/.ICE-unix/10289 +USERNAME=ICer +SNPSLMD_LICENSE_FILE=27000@IC_EDA +MFLAGS= +NOVAS_SIGNAL_BASED_BA=0 +GNOME_SHELL_SESSION_MODE=classic +NOVAS_TCL_LIBRARY=/home/synopsys/verdi/Verdi_O-2018.09-SP2/etc/access/tcl86_library +NOVAS_VERDI_SVTB_BETA=1 +MAIL=/var/spool/mail/ICer +PATH=/bin:/usr/lib/qt-3.3/bin:/usr/local/bin:/usr/local/sbin:/usr/bin:/usr/sbin:/bin:/sbin:/home/synopsys/pts/O-2018.06-SP1/bin:/home/synopsys/syn/O-2018.06-SP1/bin:/home/synopsys/lc/O-2018.06-SP1/bin:/home/synopsys/SpyGlass-L2016.06/SPYGLASS_HOME//bin:/home/synopsys/vcs/O-2018.09-SP2/gui/dve/bin:/home/synopsys/vcs/O-2018.09-SP2/bin:/home/synopsys/verdi/Verdi_O-2018.09-SP2/bin:/home/synopsys/verdi/Verdi_O-2018.09-SP2/platform/LINUX/bin:/home/synopsys/scl/2018.06/linux64/bin::/home/mentor/questasim/linux_x86_64:/home/Riscv_Tools/bin:/home/Riscv_Tools/riscv-gnu-toolchain/qemu-6.0.0/build/riscv32-linux-user +DESKTOP_SESSION=gnome-classic +PT_HOME=/home/synopsys/pts/O-2018.06-SP1 +QT_IM_MODULE=ibus +VERDI_HOME=/home/synopsys/verdi/Verdi_O-2018.09-SP2 +PWD=/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/digital_top +XDG_SESSION_TYPE=x11 +VCS_HOME=/home/synopsys/vcs/O-2018.09-SP2 +XMODIFIERS=@im=none +LANG=C +SYS_PROG_NAME=verdi +GDM_LANG=zh_CN.UTF-8 +SYNOPSYS_SIM=/home/synopsys/vcs/O-2018.09-SP2 +VERDI_TB_HT=1 +LC_MEASUREMENT=zh_CN.UTF-8 +VCS_ARCH_OVERRIDE=linux +KDEDIRS=/usr +QEMU_HOME=/home/Riscv_Tools/riscv-gnu-toolchain/qemu-6.0.0 +GDMSESSION=gnome-classic +SYS_INST_DIR=/home/synopsys/verdi/Verdi_O-2018.09-SP2 +HISTCONTROL=ignoredups +DBUS_STARTER_BUS_TYPE=session +SHLVL=5 +RISCV=/home/Riscv_Tools +XDG_SEAT=seat0 +HOME=/home/ICer +GNOME_DESKTOP_SESSION_ID=this-is-deprecated +VERDI_ORIGNAL_LD_LIBRARY_PATH=:/home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/lib/LINUX64:/home/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/IUS/LINUX64/boot +VERDI_SVTB_ALPHA=1 +DC_HOME=/home/synopsys/syn/O-2018.06-SP1 +LOGNAME=ICer +XDG_SESSION_DESKTOP=gnome-classic +MAKE_TERMERR=/dev/pts/3 +SPYGLASS_HOME=/home/synopsys/SpyGlass-L2016.06/SPYGLASS_HOME/ +QTLIB=/usr/lib/qt-3.3/lib +MGLS_LICENSE_FILE=/home/mentor/questasim/mentor.dat +VERDI_SVTB_BETA=1 +DBUS_SESSION_BUS_ADDRESS=unix:abstract=/tmp/dbus-DIYqQioq7q,guid=a50f166bc97a0937429a75936639b5b6 +XDG_DATA_DIRS=/home/ICer/.local/share/flatpak/exports/share/:/var/lib/flatpak/exports/share/:/usr/local/share/:/usr/share/ +SPS_RGB_PATH=/home/synopsys/verdi/Verdi_O-2018.09-SP2/etc/rgb +NOVASHLPPATH=/home/synopsys/verdi/Verdi_O-2018.09-SP2/doc +NOVAS_LC_ALL=C +LESSOPEN=||/usr/bin/lesspipe.sh %s +SCL_HOME=/home/synopsys/scl/2018.06 +WINDOWPATH=1 +DISPLAY=:0 +XDG_RUNTIME_DIR=/run/user/1000 +LD_NOVERSION=1 +LC_HOME=/home/synopsys/lc/O-2018.06-SP1 +QT_PLUGIN_PATH=/home/synopsys/verdi/Verdi_O-2018.09-SP2/platform/LINUXAMD64/lib/Qt/plugins +NOVAS_SIGNAL_BASE_EXTRACTION=1 +XDG_CURRENT_DESKTOP=GNOME-Classic:GNOME +LC_TIME=zh_CN.UTF-8 +NOVAS_VERDI_TB_HT=1 +COLORTERM=truecolor +XAUTHORITY=/run/gdm/auth-for-ICer-FQtMgs/database +_=/home/synopsys/verdi/Verdi_O-2018.09-SP2/etc/access/sysinfo.sh +HOSTTYPE=x86_64-linux +VENDOR=unknown +OSTYPE=linux +MACHTYPE=x86_64 +GROUP=ICer +HOST=IC_EDA +------------- end(env) ------------- +========== ps ========== + PID TTY TIME CMD + 22848 pts/3 00:00:00 bash + 74015 pts/3 00:00:00 sysinfo.sh + 74029 pts/3 00:00:00 ps + 86437 pts/3 00:00:00 make + 87088 pts/3 00:02:10 simv + 91158 pts/3 00:04:37 Novas +------------- end(ps) ------------- +========== cat /proc/meminfo ========== +MemTotal: 10054436 kB +MemFree: 2888288 kB +MemAvailable: 6919124 kB +Buffers: 2152 kB +Cached: 4349736 kB +SwapCached: 0 kB +Active: 4558976 kB +Inactive: 1730636 kB +Active(anon): 1939208 kB +Inactive(anon): 262608 kB +Active(file): 2619768 kB +Inactive(file): 1468028 kB +Unevictable: 0 kB +Mlocked: 0 kB +SwapTotal: 10481660 kB +SwapFree: 10481660 kB +Dirty: 12 kB +Writeback: 0 kB +AnonPages: 1938352 kB +Mapped: 529440 kB +Shmem: 263904 kB +Slab: 390328 kB +SReclaimable: 256964 kB +SUnreclaim: 133364 kB +KernelStack: 12016 kB +PageTables: 45816 kB +NFS_Unstable: 0 kB +Bounce: 0 kB +WritebackTmp: 0 kB +CommitLimit: 15508876 kB +Committed_AS: 6368600 kB +VmallocTotal: 34359738367 kB +VmallocUsed: 243676 kB +VmallocChunk: 34359277564 kB +Percpu: 56320 kB +HardwareCorrupted: 0 kB +AnonHugePages: 1312768 kB +CmaTotal: 0 kB +CmaFree: 0 kB +HugePages_Total: 0 +HugePages_Free: 0 +HugePages_Rsvd: 0 +HugePages_Surp: 0 +Hugepagesize: 2048 kB +DirectMap4k: 159552 kB +DirectMap2M: 6131712 kB +DirectMap1G: 6291456 kB +------------- end(cat /proc/meminfo) ------------- +========== show OS patch level ========== +\S +Kernel \r on an \m + +------------- end(show OS patch level) ------------- +========= uptime ========== + 17:28:00 up 8 days, 30 min, 4 users, load average: 1.00, 1.01, 0.96 +------------ end(uptime) ------------- +========= locale ========== +LANG=C +LC_CTYPE="C" +LC_NUMERIC="C" +LC_TIME="C" +LC_COLLATE="C" +LC_MONETARY="C" +LC_MESSAGES="C" +LC_PAPER="C" +LC_NAME="C" +LC_ADDRESS="C" +LC_TELEPHONE="C" +LC_MEASUREMENT="C" +LC_IDENTIFICATION="C" +LC_ALL=C +------------ end(locale) ------------- +========== ldd ========== +ldd /home/synopsys/verdi/Verdi_O-2018.09-SP2/platform/LINUXAMD64/bin/Novas + linux-vdso.so.1 => (0x00007fff2b1d9000) + libdl.so.2 => /lib64/libdl.so.2 (0x00007f95c5319000) + libvfs.so => /home/synopsys/verdi/Verdi_O-2018.09-SP2/platform/LINUXAMD64/bin/libvfs.so (0x00007f95c500c000) + libfreetype.so.6 => /lib64/libfreetype.so.6 (0x00007f95c4d4d000) + libQtSolutions_MotifExtension-2.7.so.1 => /home/synopsys/verdi/Verdi_O-2018.09-SP2/platform/LINUXAMD64/lib/Qt/libQtSolutions_MotifExtension-2.7.so.1 (0x00007f95c4b37000) + libQtGui.so.4 => /home/synopsys/verdi/Verdi_O-2018.09-SP2/platform/LINUXAMD64/lib/Qt/libQtGui.so.4 (0x00007f95c3f93000) + libQtCore.so.4 => /home/synopsys/verdi/Verdi_O-2018.09-SP2/platform/LINUXAMD64/lib/Qt/libQtCore.so.4 (0x00007f95c3afa000) + libQtXml.so.4 => /home/synopsys/verdi/Verdi_O-2018.09-SP2/platform/LINUXAMD64/lib/Qt/libQtXml.so.4 (0x00007f95c38c0000) + libQtWebKit.so.4 => /home/synopsys/verdi/Verdi_O-2018.09-SP2/platform/LINUXAMD64/lib/Qt/libQtWebKit.so.4 (0x00007f95c1faf000) + libQtNetwork.so.4 => /home/synopsys/verdi/Verdi_O-2018.09-SP2/platform/LINUXAMD64/lib/Qt/libQtNetwork.so.4 (0x00007f95c1ca1000) + libQt3Support.so.4 => /home/synopsys/verdi/Verdi_O-2018.09-SP2/platform/LINUXAMD64/lib/Qt/libQt3Support.so.4 (0x00007f95c1801000) + libQtSql.so.4 => /home/synopsys/verdi/Verdi_O-2018.09-SP2/platform/LINUXAMD64/lib/Qt/libQtSql.so.4 (0x00007f95c15cb000) + libsimprofile_verdi.so => /home/synopsys/verdi/Verdi_O-2018.09-SP2/platform/LINUXAMD64/bin/libsimprofile_verdi.so (0x00007f95c1213000) + libstdc++.so.6 => /home/synopsys/verdi/Verdi_O-2018.09-SP2/etc/lib/libstdc++/LINUXAMD64/libstdc++.so.6 (0x00007f95c0e92000) + libtbb.so.2 => /home/synopsys/verdi/Verdi_O-2018.09-SP2/platform/LINUXAMD64/bin/libtbb.so.2 (0x00007f95c55cd000) + libXss.so.1 => /lib64/libXss.so.1 (0x00007f95c0c8e000) + libXft.so.2 => /lib64/libXft.so.2 (0x00007f95c0a78000) + libXt.so.6 => /lib64/libXt.so.6 (0x00007f95c0811000) + libXmu.so.6 => /lib64/libXmu.so.6 (0x00007f95c05f6000) + libX11.so.6 => /lib64/libX11.so.6 (0x00007f95c02b8000) + libXext.so.6 => /lib64/libXext.so.6 (0x00007f95c00a6000) + libfontconfig.so.1 => /lib64/libfontconfig.so.1 (0x00007f95bfe64000) + libnsl.so.1 => /lib64/libnsl.so.1 (0x00007f95bfc4a000) + libnuma.so.1 => /lib64/libnuma.so.1 (0x00007f95bfa3e000) + libpthread.so.0 => /lib64/libpthread.so.0 (0x00007f95bf822000) + librt.so.1 => /lib64/librt.so.1 (0x00007f95bf61a000) + libpng12.so.0 => /lib64/libpng12.so.0 (0x00007f95bf3f3000) + libm.so.6 => /lib64/libm.so.6 (0x00007f95bf0f1000) + libc.so.6 => /lib64/libc.so.6 (0x00007f95bed23000) + /lib64/ld-linux-x86-64.so.2 (0x00007f95c551d000) + libz.so.1 => /lib64/libz.so.1 (0x00007f95beb0d000) + libbz2.so.1 => /lib64/libbz2.so.1 (0x00007f95be8fd000) + libpng15.so.15 => /lib64/libpng15.so.15 (0x00007f95be6d2000) + libSM.so.6 => /lib64/libSM.so.6 (0x00007f95be4ca000) + libICE.so.6 => /lib64/libICE.so.6 (0x00007f95be2ae000) + libgcc_s.so.1 => /home/synopsys/verdi/Verdi_O-2018.09-SP2/etc/lib/libstdc++/LINUXAMD64/libgcc_s.so.1 (0x00007f95be098000) + libXrender.so.1 => /lib64/libXrender.so.1 (0x00007f95bde8d000) + libxcb.so.1 => /lib64/libxcb.so.1 (0x00007f95bdc65000) + libexpat.so.1 => /lib64/libexpat.so.1 (0x00007f95bda3b000) + libuuid.so.1 => /lib64/libuuid.so.1 (0x00007f95bd836000) + libXau.so.6 => /lib64/libXau.so.6 (0x00007f95bd632000) +------------- end(ldd) ------------- diff --git a/tb/digital_top/verdiLog/sysinfo_May15_1728.tar b/tb/digital_top/verdiLog/sysinfo_May15_1728.tar new file mode 100644 index 0000000..cb47e80 Binary files /dev/null and b/tb/digital_top/verdiLog/sysinfo_May15_1728.tar differ diff --git a/tb/digital_top/verdiLog/tdc.list.oneSearch b/tb/digital_top/verdiLog/tdc.list.oneSearch new file mode 100644 index 0000000..7769794 --- /dev/null +++ b/tb/digital_top/verdiLog/tdc.list.oneSearch @@ -0,0 +1,133 @@ +../../rtl/memory/tsmc_dpram.v +../../rtl/z_dsp/MeanIntp2.v +../../rtl/xy_dsp/duc/duc_hb1_top.v +qbmcu_undefines.v +qbmcu_defines.v +qbmcu_defines.v +../../rtl/z_dsp/lsdacif.v +../../rtl/modem/ampmod.v +chip_define.v +../../rtl/z_dsp/TailCorr_top.v +../../rtl/xy_dsp/duc/duc_hb3_pipe_shift.v +qbmcu_undefines.v +../../rtl/nco/pipe_acc_48bit.v +../../rtl/rstgen/rst_sync.v +../../rtl/rstgen/rst_gen_unit.v +qbmcu_defines.v +qbmcu_undefines.v +../../rtl/spi/spi_bus_decoder.sv +qbmcu_defines.v +chip_undefine.v +../../rtl/z_dsp/MeanIntp.v +../../rtl/define/chip_undefine.v +../../rtl/clk/intpll_regfile.v +chip_undefine.v +qbmcu_undefines.v +../../rtl/qubitmcu/qbmcu_undefines.v +qbmcu_defines.v +chip_define.v +../../rtl/dac_regfile/dac_regfile.v +../../rtl/spi/spi_pll.v +../../rtl/xy_dsp/duc/duc_hb4_top_s3.v +../../rtl/perips/DW03_updn_ctr.v +../../rtl/modem/baisset.v +../../rtl/z_dsp/diff.v +../../rtl/xy_dsp/qam/qam_top.v +../../rtl/xy_dsp/duc/duc_hb2_pipe_shift.v +../../rtl/memory/tsdn28hpcpuhdb128x128m4mw_170a_ffg0p99v0c.v +chip_define.v +../../rtl/qubitmcu/qbmcu_ifu.v +../../rtl/nco/sin_op.v +../../rtl/awg/ctrl_regfile.v +../../sim/digital_top/DW02_mult.v +../../sim/digital_top/DW01_addsub.v +../../rtl/xy_dsp/duc/duc_hb3_top_s2.v +../../rtl/system_regfile/system_regfile.v +../../rtl/qubitmcu/qbmcu_regfile.v +../../rtl/qubitmcu/qbmcu_fsm.v +qbmcu_defines.v +chip_define.v +../../rtl/nco/nco_ch1.v +../../rtl/top/channel_top.sv +../../rtl/memory/tsdn28hpcpuhdb4096x32m4mw_170a_ffg0p99v0c.v +../../rtl/xy_dsp/dacif/dacif.v +../../rtl/qubitmcu/qbmcu_exu_alu.v +../../rtl/qubitmcu/qbmcu_decode.v +qbmcu_defines.v +../../rtl/modem/freqmod.v +../../rtl/nco/p_nco.v +../../rtl/qubitmcu/qbmcu_exu_ext.v +../../rtl/spi/spi_slave.v +../../rtl/qubitmcu/qbmcu_exu.v +qbmcu_defines.v +../../rtl/qubitmcu/qbmcu.v +qbmcu_defines.v +../../rtl/memory/dpram.v +../../rtl/xy_dsp/duc/duc_hb1_pipe_shift.v +../../rtl/nco/p_nco_ch1.v +qbmcu_defines.v +../../rtl/memory/dpram_model.v +../../sim/digital_top/clk_gen.v +../../rtl/top/digital_top.sv +../../rtl/spi/spi_sys.v +../../rtl/debug/debug_top.sv +../../rtl/awg/awg_top.sv +../../rtl/z_dsp/mult_C.v +../../rtl/xy_dsp/duc/duc4.v +../../rtl/xy_dsp/duc/duc_hb2_top_s.v +qbmcu_defines.v +qbmcu_undefines.v +../../rtl/nco/pipe_add_48bit.v +../../rtl/awg/param_lut.sv +../../rtl/awg/codeword_decode.v +chip_undefine.v +../../rtl/xy_dsp/qam/ssb.v +../../rtl/perips/mcu_regfile.sv +../../rtl/comm/sirv_gnrl_dffs.v +../../rtl/debug/debug_sample.sv +../../rtl/z_dsp/IIR_Filter.v +../../rtl/xy_dsp/dsp_top/xy_dsp.v +../../sim/digital_top/spi_if.sv +../../rtl/qubitmcu/qbmcu_exu_bjp.v +../../rtl/nco/ph2amp.v +../../rtl/awg/awg_ctrl.v +qbmcu_undefines.v +qbmcu_undefines.v +../../rtl/memory/sram_dmux.sv +chip_undefine.v +../../rtl/qubitmcu/qbmcu_wbck.v +../../rtl/memory/sram_if.sv +qbmcu_undefines.v +qbmcu_undefines.v +../../rtl/comm/sirv_gnrl_xchecker.v +qbmcu_defines.v +../../rtl/nco/coef_s.v +../../rtl/define/chip_define.v +../../rtl/qubitmcu/qbmcu_datalock.v +qbmcu_undefines.v +qbmcu_undefines.v +../../rtl/memory/tsdn28hpcpuhdb4096x32m4mwr_170a_ffg0p99v0c.v +../../rtl/z_dsp/MeanIntp_s1.v +qbmcu_defines.v +../../rtl/awg/modout_mux.v +../../rtl/z_dsp/z_dsp.v +../../rtl/xy_dsp/duc/duc_hb4_pipe_shift.v +../../rtl/perips/qbmcu_busdecoder.v +../../rtl/nco/coef_c.v +../../sim/digital_top/TB.sv +qbmcu_undefines.v +../../rtl/qubitmcu/qbmcu_exu_dpath.v +qbmcu_undefines.v +../../rtl/z_dsp/z_data_mux.v +qbmcu_defines.v +../../rtl/nco/cos_op.v +../../rtl/qubitmcu/qbmcu_defines.v +../../rtl/nco/nco.v +../../rtl/memory/tsdn28hpcpuhdb64x32m4mw_170a_ffg0p99v0c.v +../../sim/digital_top/DW_mult_pipe.v +../../rtl/z_dsp/MeanIntp4_top.v +qbmcu_undefines.v +../../rtl/qubitmcu/qbmcu_exu_lsuagu.v +qbmcu_defines.v +../../rtl/sync/sync_buf.sv +qbmcu_undefines.v diff --git a/tb/digital_top/verdiLog/turbo.log b/tb/digital_top/verdiLog/turbo.log new file mode 100644 index 0000000..96a4d3e --- /dev/null +++ b/tb/digital_top/verdiLog/turbo.log @@ -0,0 +1,2 @@ +Command Line: /home/synopsys/verdi/Verdi_O-2018.09-SP2/platform/LINUXAMD64/bin/Novas -sverilog -f files.f -top TB -nologo +uname(Linux IC_EDA 3.10.0-1160.53.1.el7.x86_64 #1 SMP Fri Jan 14 13:59:45 UTC 2022 x86_64) diff --git a/tb/digital_top/verdiLog/verdi.cmd b/tb/digital_top/verdiLog/verdi.cmd new file mode 100644 index 0000000..d8f256a --- /dev/null +++ b/tb/digital_top/verdiLog/verdi.cmd @@ -0,0 +1,12466 @@ +sidCmdLineBehaviorAnalysisOpt -incr -clockSkew 0 -loopUnroll 0 -bboxEmptyModule 0 -cellModel 0 -bboxIgnoreProtected 0 +debImport "-sverilog" "-f" "files.f" "-top" "TB" +srcHBSelect "TB.U_digital_top" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top" -delim "." +srcHBSelect "TB.U_digital_top" -win $_nTrace1 +srcHBSelect "TB" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB" -delim "." +srcHBSelect "TB" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "cs_wave" -line 808 -pos 1 -win $_nTrace1 +wvCreateWindow +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +wvSetPosition -win $_nWave2 {("G1" 0)} +wvOpenFile -win $_nWave2 \ + {/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/digital_top/verdplus_000.fsdb} +srcDeselectAll -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "cs_wave" -line 808 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +srcDeselectAll -win $_nTrace1 +debReload +verdiDockWidgetMaximize -dock windowDock_nWave_2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 15475214.758315 27379226.110865 +wvZoom -win $_nWave2 22427579.703458 23187747.168986 +wvZoom -win $_nWave2 22776481.400489 22886377.007479 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvTpfCloseForm -win $_nWave2 +wvGetSignalClose -win $_nWave2 +wvCloseWindow -win $_nWave2 +srcHBSelect "TB.U_digital_top" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top" -delim "." +srcHBSelect "TB.U_digital_top" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "sclk" -line 58 -pos 1 -win $_nTrace1 +srcSelect -win $_nTrace1 -range {58 59 5 5 3 1} +srcDeselectAll -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "sclk" -line 58 -pos 1 -win $_nTrace1 +srcSelect -signal "csn" -line 59 -pos 1 -win $_nTrace1 +srcSelect -signal "mosi" -line 60 -pos 1 -win $_nTrace1 +srcSelect -signal "miso" -line 61 -pos 1 -win $_nTrace1 +wvCreateWindow +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +verdiDockWidgetMaximize -dock windowDock_nWave_3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 28667868.665188 1032043271.946785 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +verdiDockWidgetRestore -dock windowDock_nWave_3 +srcHBSelect "TB" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB" -delim "." +srcHBSelect "TB" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "cs_wave" -line 836 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "cs_wave" -line 836 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +debReload +srcDeselectAll -win $_nTrace1 +srcSelect -signal "cs_wave" -line 836 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "i_cs_f" -line 836 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "ch0_xy_dsp_dout0" -line 744 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcHBSelect "TB.U_digital_top" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top" -delim "." +srcHBSelect "TB.U_digital_top" -win $_nTrace1 +srcHBSelect "TB.U_digital_top.U0_channel_top" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U0_channel_top" -delim "." +srcHBSelect "TB.U_digital_top.U0_channel_top" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "dec_o_ilegl" -line 42 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcHBSelect "TB" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB" -delim "." +srcHBSelect "TB" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "clk_rstn" -line 166 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "rstn" -line 167 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvSetCursor -win $_nWave3 3798492598.137472 -snap {("G1" 9)} +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +verdiDockWidgetMaximize -dock windowDock_nWave_3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +verdiDockWidgetRestore -dock windowDock_nWave_3 +srcHBSelect "TB.U_digital_top.U0_channel_top.U_qbmcu" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U0_channel_top.U_qbmcu" -delim "." +srcHBSelect "TB.U_digital_top.U0_channel_top.U_qbmcu" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "qbmcu_o_fsm_st" -line 43 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "qbmcu_o_fsm_st" -line 43 -pos 1 -win $_nTrace1 +srcAction -pos 42 11 5 -win $_nTrace1 -name "qbmcu_o_fsm_st" -ctrlKey off +srcHBSelect "TB.U_digital_top.U0_channel_top.U_DTCM" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U0_channel_top.U_DTCM" -delim "." +srcHBSelect "TB.U_digital_top.U0_channel_top.U_DTCM" -win $_nTrace1 +verdiDockWidgetMaximize -dock windowDock_nWave_3 +wvSetCursor -win $_nWave3 13000878439.662971 -snap {("G2" 0)} +wvDisplayGridCount -win $_nWave3 -off +wvGetSignalClose -win $_nWave3 +wvReloadFile -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvSelectSignal -win $_nWave3 {( "G1" 5 )} +wvSetRadix -win $_nWave3 -2Com +wvSetRadix -win $_nWave3 -Unsigned +wvBusWaveform -win $_nWave3 -analog +wvSetPosition -win $_nWave3 {("G1" 11)} +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvBusWaveform -win $_nWave3 -analog +wvChangeDisplayAttr -win $_nWave3 -c ID_YELLOW5 -lw 1 -ls solid +wvChangeDisplayAttr -win $_nWave3 -c ID_ORANGE5 -lw 1 -ls solid +wvChangeDisplayAttr -win $_nWave3 -c ID_ORANGE4 -lw 1 -ls solid +wvChangeDisplayAttr -win $_nWave3 -c ID_GREEN4 -lw 1 -ls solid +wvChangeDisplayAttr -win $_nWave3 -c ID_YELLOW4 -lw 1 -ls solid +wvChangeDisplayAttr -win $_nWave3 -c ID_ORANGE3 -lw 1 -ls solid +wvChangeDisplayAttr -win $_nWave3 -c ID_RED2 -lw 1 -ls solid +wvChangeDisplayAttr -win $_nWave3 -c ID_RED3 -lw 1 -ls solid +wvChangeDisplayAttr -win $_nWave3 -c ID_RED8 -lw 1 -ls solid +wvChangeDisplayAttr -win $_nWave3 -c ID_RED7 -lw 1 -ls solid +wvSetCursor -win $_nWave3 8313761979.270512 -snap {("G2" 0)} +wvSelectSignal -win $_nWave3 {( "G1" 6 )} +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomOut -win $_nWave3 +wvSelectSignal -win $_nWave3 {( "G1" 6 7 8 9 10 11 )} +wvCut -win $_nWave3 +wvSetPosition -win $_nWave3 {("G1" 5)} +wvSelectSignal -win $_nWave3 {( "G1" 1 )} +wvSelectSignal -win $_nWave3 {( "G1" 1 2 3 4 )} +wvCut -win $_nWave3 +wvSetPosition -win $_nWave3 {("G1" 1)} +wvSetCursor -win $_nWave3 8318435891.533748 -snap {("G2" 0)} +verdiDockWidgetRestore -dock windowDock_nWave_3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +srcDeselectAll -win $_nTrace1 +debReload +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomIn -win $_nWave3 +wvSetCursor -win $_nWave3 8316111548.118384 -snap {("G1" 1)} +wvSetCursor -win $_nWave3 8324097199.294590 -snap {("G1" 1)} +wvSetCursor -win $_nWave3 8315650283.068495 -snap {("G1" 1)} +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvSetCursor -win $_nWave3 8308111482.409369 -snap {("G1" 1)} +wvSelectSignal -win $_nWave3 {( "G1" 1 )} +wvSetMarker -win $_nWave3 -keepViewRange -name "M1" 8308111482.409369 +wvSetMarker -win $_nWave3 -keepViewRange -name "M1" 8308113000.000000 +wvSetMarker -win $_nWave3 -keepViewRange -name "M2" 8316154791.716811 +wvSetMarker -win $_nWave3 -keepViewRange -name "M2" 8316155000.000000 +wvSelectGroup -win $_nWave3 {G2} +wvSetMarker -win $_nWave3 -keepViewRange -name "M3" 8324140442.893017 +wvSetMarker -win $_nWave3 -keepViewRange -name "M3" 8324141000.000000 +wvSetCursor -win $_nWave3 8308097067.876560 -snap {("G2" 0)} +wvSetMarkerOption -win $_nWave3 -absolute on +wvSetMarkerOption -win $_nWave3 -relative on +srcHBSelect "TB" -win $_nTrace1 +srcHBSelect "TB" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB" -delim "." +srcHBSelect "TB" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcAction -pos 7 0 78 -win $_nTrace1 -name \ + "//`define ENVE_DATA2_FILE \"../../cfgdata/envemem/env2_len20_amp20000_drag1p34_bin.txt\"" \ + -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcAction -pos 3 5 35 -win $_nTrace1 -name \ + "\"../../cfgdata/instrmem/SingleWaveCosine_bin.txt\"" -ctrlKey off +wvSetWindowTimeUnit -win $_nWave3 1.000000 ns +wvSelectSignal -win $_nWave3 {( "G1" 1 )} +wvAddSignal -win $_nWave3 "/TB/cs_wave\[15:0\]" -color ID_RED7 +wvSetPosition -win $_nWave3 {("G1" 1)} +wvSetPosition -win $_nWave3 {("G1" 2)} +wvSetCursor -win $_nWave3 8308774.550919 -snap {("G1" 2)} +wvSetCursor -win $_nWave3 8308111.482409 -snap {("G1" 1)} +wvZoom -win $_nWave3 8308082.653344 8308543.918394 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvSetCursor -win $_nWave3 8308768.209802 -snap {("G1" 2)} +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomIn -win $_nWave3 +wvSetCursor -win $_nWave3 8316043.719911 -snap {("G1" 2)} +wvSetCursor -win $_nWave3 8308817.302313 -snap {("G1" 2)} +wvSetCursor -win $_nWave3 8316069.902583 -snap {("G1" 2)} +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top" -win $_nTrace1 +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.U_awg_ctrl" -win $_nTrace1 +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.U_awg_ctrl" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U0_channel_top.U_awg_top.U_awg_ctrl" \ + -delim "." +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.U_awg_ctrl" -win $_nTrace1 +srcHBSelect "TB.U_digital_top.U0_channel_top.U_qbmcu" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U0_channel_top.U_qbmcu" -delim "." +srcHBSelect "TB.U_digital_top.U0_channel_top.U_qbmcu" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "ext_o_sendc" -line 64 -pos 1 -win $_nTrace1 +srcSelect -signal "ext_wait_cnt" -line 252 -pos 1 -win $_nTrace1 +srcSelect -signal "ext_wait" -line 254 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "clk" -line 250 -pos 2 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -inst "U_DW03_updn_ctr" -line 249 -pos 1 -win $_nTrace1 +srcAction -pos 248 2 8 -win $_nTrace1 -name "U_DW03_updn_ctr" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -signal "count" -line 57 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvZoom -win $_nWave3 8297480.205140 8299142.804841 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 8297946.544080 8298142.664488 +wvZoomOut -win $_nWave3 +wvSelectSignal -win $_nWave3 {( "G1" 7 )} +wvSetRadix -win $_nWave3 -format UDec +wvZoomOut -win $_nWave3 +wvSetCursor -win $_nWave3 8297999.205235 -snap {("G1" 5)} +wvSetCursor -win $_nWave3 8298030.514924 -snap {("G1" 7)} +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomOut -win $_nWave3 +wvSetCursor -win $_nWave3 8297779.515590 -snap {("G1" 5)} +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvSetCursor -win $_nWave3 8292784.576662 -snap {("G1" 2)} +wvSelectSignal -win $_nWave3 {( "G1" 1 )} +wvZoomAll -win $_nWave3 +wvSetCursor -win $_nWave3 15279973.998545 -snap {("G2" 0)} +wvSelectGroup -win $_nWave3 {G2} +wvSelectSignal -win $_nWave3 {( "G1" 3 )} +wvSetCursor -win $_nWave3 10349100.588133 -snap {("G2" 0)} +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 5575900.455379 7582651.261942 +wvZoom -win $_nWave3 5946103.708386 6122306.218230 +wvZoom -win $_nWave3 5984079.060839 6004785.785943 +wvZoom -win $_nWave3 5987752.094117 5989505.967507 +wvSetCursor -win $_nWave3 5988109.868732 -snap {("G1" 2)} +wvSelectSignal -win $_nWave3 {( "G1" 1 )} +wvSetMarker -win $_nWave3 -keepViewRange -name "M4" 5988112.202045 +wvSetMarker -win $_nWave3 -keepViewRange -name "M4" 5988112.202045 +wvSetCursor -win $_nWave3 5988756.974125 -snap {("G1" 2)} +wvSelectSignal -win $_nWave3 {( "G1" 2 )} +wvSetMarker -win $_nWave3 -keepViewRange -name "M5" 5988753.863041 +wvSetMarker -win $_nWave3 -keepViewRange -name "M5" 5988753.863041 +wvZoomOut -win $_nWave3 +wvZoomIn -win $_nWave3 +srcHBSelect "TB.U_digital_top" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top" -delim "." +srcHBSelect "TB.U_digital_top" -win $_nTrace1 +srcSelect -signal "ch0_xy_dsp_dout_vld" -line 1081 -pos 1 -win $_nTrace1 +srcSelect -signal "ch0_xy_dsp_dout0" -line 1082 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvSetCursor -win $_nWave3 5988143.312881 -snap {("G1" 6)} +wvSetCursor -win $_nWave3 5988304.311458 -snap {("G1" 6)} +wvSetCursor -win $_nWave3 5988142.535110 -snap {("G1" 6)} +srcHBSelect "TB" -win $_nTrace1 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +srcHBSelect "TB" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB" -delim "." +srcHBSelect "TB" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "clk_div16_0" -line 299 -pos 2 -win $_nTrace1 +srcSelect -signal "clk" -line 298 -pos 2 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvZoom -win $_nWave3 5985950.387816 5986665.937048 +wvZoom -win $_nWave3 5986171.874894 5986221.376305 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvSetCursor -win $_nWave3 5986159.000136 -snap {("G1" 11)} +wvSetCursor -win $_nWave3 5986161.546550 -snap {("G1" 11)} +wvSetCursor -win $_nWave3 5986159.175751 -snap {("G1" 11)} +wvSetCursor -win $_nWave3 5986160.931899 -snap {("G1" 11)} +wvSetCursor -win $_nWave3 5986159.087944 -snap {("G1" 11)} +wvSetCursor -win $_nWave3 5986161.370936 -snap {("G1" 11)} +wvSetCursor -win $_nWave3 5986159.175751 -snap {("G1" 11)} +wvSetCursor -win $_nWave3 5986161.019706 -snap {("G1" 11)} +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 8987376.826537 10148425.507477 +wvZoom -win $_nWave3 9338523.256869 9503284.045295 +wvZoom -win $_nWave3 9410857.261544 9416629.368988 +wvZoomOut -win $_nWave3 +wvSelectSignal -win $_nWave3 {( "G1" 8 )} +wvSetPosition -win $_nWave3 {("G1" 8)} +wvSetPosition -win $_nWave3 {("G1" 7)} +wvSetPosition -win $_nWave3 {("G1" 6)} +wvSetPosition -win $_nWave3 {("G1" 5)} +wvSetPosition -win $_nWave3 {("G1" 4)} +wvSetPosition -win $_nWave3 {("G1" 3)} +wvSetPosition -win $_nWave3 {("G1" 2)} +wvSetPosition -win $_nWave3 {("G1" 1)} +wvSetPosition -win $_nWave3 {("G1" 0)} +wvMoveSelected -win $_nWave3 +wvSetPosition -win $_nWave3 {("G1" 0)} +wvSetPosition -win $_nWave3 {("G1" 1)} +wvZoom -win $_nWave3 9411831.224684 9413192.981296 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +srcDeselectAll -win $_nTrace1 +debReload +wvZoomIn -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoom -win $_nWave3 9407453.977322 9409792.213065 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.U_awg_ctrl" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U0_channel_top.U_awg_top.U_awg_ctrl" \ + -delim "." +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.U_awg_ctrl" -win $_nTrace1 +srcSelect -signal "enve_vld_o" -line 100 -pos 1 -win $_nTrace1 +srcSelect -signal "enve_qdata_o" -line 99 -pos 1 -win $_nTrace1 +srcSelect -signal "enve_idata_o" -line 98 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvSetPosition -win $_nWave3 {("G1" 2)} +wvSetPosition -win $_nWave3 {("G1" 1)} +wvSetPosition -win $_nWave3 {("G1" 0)} +wvMoveSelected -win $_nWave3 +wvSetPosition -win $_nWave3 {("G1" 0)} +wvSetPosition -win $_nWave3 {("G1" 3)} +wvSelectSignal -win $_nWave3 {( "G1" 3 )} +wvSetRadix -win $_nWave3 -2Com +wvBusWaveform -win $_nWave3 -analog +wvSetPosition -win $_nWave3 {("G1" 3)} +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 9396769.121348 9398710.219935 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 9404557.187627 9408881.834765 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 9407106.907525 9408012.110828 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomIn -win $_nWave3 +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U0_channel_top.U_awg_top" -delim "." +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top" -win $_nTrace1 +srcSelect -signal "awg_vld" -line 82 -pos 1 -win $_nTrace1 +srcSelect -signal "awg_data_q" -line 81 -pos 1 -win $_nTrace1 +srcSelect -signal "awg_data_i" -line 80 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvSelectSignal -win $_nWave3 {( "G1" 6 )} +wvSetRadix -win $_nWave3 -2Com +wvBusWaveform -win $_nWave3 -analog +wvSetPosition -win $_nWave3 {("G1" 6)} +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvSelectSignal -win $_nWave3 {( "G1" 5 )} +wvSelectSignal -win $_nWave3 {( "G1" 5 )} +wvSetRadix -win $_nWave3 -2Com +wvBusWaveform -win $_nWave3 -analog +wvSetPosition -win $_nWave3 {("G1" 6)} +wvSelectSignal -win $_nWave3 {( "G1" 5 )} +wvSelectSignal -win $_nWave3 {( "G1" 5 )} +wvSelectSignal -win $_nWave3 {( "G1" 6 )} +wvSelectSignal -win $_nWave3 {( "G1" 5 )} +wvSetCursor -win $_nWave3 9405868.725888 -snap {("G1" 5)} +wvSelectSignal -win $_nWave3 {( "G1" 2 )} +wvSetRadix -win $_nWave3 -2Com +wvBusWaveform -win $_nWave3 -analog +wvSetPosition -win $_nWave3 {("G1" 6)} +wvScrollDown -win $_nWave3 1 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomOut -win $_nWave3 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvZoom -win $_nWave3 9408577.511649 9409007.834461 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvSetCursor -win $_nWave3 9408759.850206 -snap {("G1" 7)} +wvSetCursor -win $_nWave3 9408724.737391 -snap {("G1" 7)} +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvSetCursor -win $_nWave3 9408612.529048 -snap {("G1" 7)} +wvSelectSignal -win $_nWave3 {( "G1" 7 )} +wvZoom -win $_nWave3 9408600.315895 9409113.268321 +wvZoomOut -win $_nWave3 +wvSelectSignal -win $_nWave3 {( "G1" 13 )} +wvSetPosition -win $_nWave3 {("G1" 13)} +wvSetPosition -win $_nWave3 {("G1" 12)} +wvSetPosition -win $_nWave3 {("G1" 11)} +wvSetPosition -win $_nWave3 {("G1" 10)} +wvSetPosition -win $_nWave3 {("G1" 9)} +wvSetPosition -win $_nWave3 {("G1" 8)} +wvSetPosition -win $_nWave3 {("G1" 7)} +wvSetPosition -win $_nWave3 {("G1" 6)} +wvMoveSelected -win $_nWave3 +wvSetPosition -win $_nWave3 {("G1" 6)} +wvSetPosition -win $_nWave3 {("G1" 7)} +wvSetCursor -win $_nWave3 9408751.926889 -snap {("G1" 9)} +srcHBSelect "TB.U_digital_top.U0_channel_top.U_xy_dsp.dacif_inst" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U0_channel_top.U_xy_dsp.dacif_inst" \ + -delim "." +srcHBSelect "TB.U_digital_top.U0_channel_top.U_xy_dsp.dacif_inst" -win $_nTrace1 +srcHBSelect "TB.U_digital_top.U0_channel_top.U_xy_dsp.inst_qam_top" -win \ + $_nTrace1 +srcHBSelect "TB.U_digital_top.U0_channel_top.U_xy_dsp.inst_duc_top_i" -win \ + $_nTrace1 +srcSetScope -win $_nTrace1 \ + "TB.U_digital_top.U0_channel_top.U_xy_dsp.inst_duc_top_i" -delim \ + "." +srcHBSelect "TB.U_digital_top.U0_channel_top.U_xy_dsp.inst_duc_top_i" -win \ + $_nTrace1 +srcHBSelect "TB.U_digital_top.U0_channel_top.U_xy_dsp.inst_qam_top" -win \ + $_nTrace1 +srcSetScope -win $_nTrace1 \ + "TB.U_digital_top.U0_channel_top.U_xy_dsp.inst_qam_top" -delim "." +srcHBSelect "TB.U_digital_top.U0_channel_top.U_xy_dsp.inst_qam_top" -win \ + $_nTrace1 +srcHBSelect "TB.U_digital_top.U0_channel_top.U_ctrl_regfile" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U0_channel_top.U_ctrl_regfile" \ + -delim "." +srcHBSelect "TB.U_digital_top.U0_channel_top.U_ctrl_regfile" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -win $_nTrace1 -range {198 198 14 14 25 31} +srcDeselectAll -win $_nTrace1 +debReload +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvSelectSignal -win $_nWave3 {( "G1" 9 )} +srcHBSelect "TB.U_digital_top.U0_channel_top.U_z_dsp" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U0_channel_top.U_z_dsp" -delim "." +srcHBSelect "TB.U_digital_top.U0_channel_top.U_z_dsp" -win $_nTrace1 +srcSelect -signal "dout0" -line 69 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvSetRadix -win $_nWave3 -2Com +wvSetRadix -win $_nWave3 -Unsigned +wvBusWaveform -win $_nWave3 -analog +wvSetPosition -win $_nWave3 {("G1" 8)} +wvZoomIn -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvSetCursor -win $_nWave3 9398251.074208 -snap {("G1" 8)} +wvSetCursor -win $_nWave3 9398003.583193 -snap {("G1" 8)} +wvSelectSignal -win $_nWave3 {( "G1" 8 )} +wvSetRadix -win $_nWave3 -format UDec +wvSetCursor -win $_nWave3 9398047.258078 -snap {("G1" 8)} +wvSetCursor -win $_nWave3 9398527.681812 -snap {("G1" 8)} +wvSetCursor -win $_nWave3 9397959.908308 -snap {("G1" 8)} +wvZoomOut -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +srcDeselectAll -win $_nTrace1 +debReload +srcHBSelect "TB" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB" -delim "." +srcHBSelect "TB" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "Z_fid" -line 895 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "ch0_z_dsp_dout0" -line 857 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "intp_mode" -line 867 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "intp_mode" -line 867 -pos 1 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +debReload +wvSelectSignal -win $_nWave3 {( "G1" 9 )} +wvCut -win $_nWave3 +wvSetPosition -win $_nWave3 {("G1" 11)} +wvSetPosition -win $_nWave3 {("G1" 10)} +srcDeselectAll -win $_nTrace1 +srcSelect -signal "z_wave" -line 882 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvBusWaveform -win $_nWave3 -analog +wvSetPosition -win $_nWave3 {("G1" 11)} +wvScrollDown -win $_nWave3 1 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 9406079.797338 9406778.595497 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvSelectSignal -win $_nWave3 {( "G1" 8 )} +wvCut -win $_nWave3 +wvSetPosition -win $_nWave3 {("G1" 11)} +wvSetPosition -win $_nWave3 {("G1" 10)} +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvSelectSignal -win $_nWave3 {( "G1" 9 )} +wvSelectSignal -win $_nWave3 {( "G1" 10 )} +wvZoom -win $_nWave3 9397712.657779 9399755.441578 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +srcDeselectAll -win $_nTrace1 +debReload +wvZoom -win $_nWave3 9397581.756555 9399755.894524 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 9397934.150093 9399191.389964 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +srcHBSelect "TB.U_digital_top.U0_channel_top.U_z_dsp" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U0_channel_top.U_z_dsp" -delim "." +srcHBSelect "TB.U_digital_top.U0_channel_top.U_z_dsp" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "dout0" -line 69 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvBusWaveform -win $_nWave3 -analog +wvSetPosition -win $_nWave3 {("G1" 11)} +wvSelectSignal -win $_nWave3 {( "G1" 11 )} +wvAddSignal -win $_nWave3 \ + "/TB/U_digital_top/U0_channel_top/U_z_dsp/dout0\[15:0\]" +wvSetPosition -win $_nWave3 {("G1" 11)} +wvSetPosition -win $_nWave3 {("G1" 12)} +wvZoom -win $_nWave3 9397971.783658 9398457.953578 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +srcHBSelect "TB.U_digital_top.U_sync_buf" -win $_nTrace1 +srcHBSelect "TB.U_digital_top.U0_channel_top.U_z_dsp" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U0_channel_top.U_z_dsp" -delim "." +srcHBSelect "TB.U_digital_top.U0_channel_top.U_z_dsp" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "a0_re" -line 45 -pos 1 -win $_nTrace1 +srcSelect -signal "b5_im" -line 68 -pos 1 -win $_nTrace1 +srcSelect -signal "b5_re" -line 67 -pos 1 -win $_nTrace1 +srcSelect -signal "a5_im" -line 66 -pos 1 -win $_nTrace1 +srcSelect -signal "a5_re" -line 65 -pos 1 -win $_nTrace1 +srcSelect -signal "b4_im" -line 64 -pos 1 -win $_nTrace1 +srcSelect -signal "b4_re" -line 63 -pos 1 -win $_nTrace1 +srcSelect -signal "a4_im" -line 62 -pos 1 -win $_nTrace1 +srcSelect -signal "a4_re" -line 61 -pos 1 -win $_nTrace1 +srcSelect -signal "b3_im" -line 60 -pos 1 -win $_nTrace1 +srcSelect -signal "b3_re" -line 59 -pos 1 -win $_nTrace1 +srcSelect -signal "a3_im" -line 58 -pos 1 -win $_nTrace1 +srcSelect -signal "a3_re" -line 57 -pos 1 -win $_nTrace1 +srcSelect -signal "b2_im" -line 56 -pos 1 -win $_nTrace1 +srcSelect -signal "b2_re" -line 55 -pos 1 -win $_nTrace1 +srcSelect -signal "a2_im" -line 54 -pos 1 -win $_nTrace1 +srcSelect -signal "a2_re" -line 53 -pos 1 -win $_nTrace1 +srcSelect -signal "b1_im" -line 52 -pos 1 -win $_nTrace1 +srcSelect -signal "b1_re" -line 51 -pos 1 -win $_nTrace1 +srcSelect -signal "a1_im" -line 50 -pos 1 -win $_nTrace1 +srcSelect -signal "a1_re" -line 49 -pos 1 -win $_nTrace1 +srcSelect -signal "b0_im" -line 48 -pos 1 -win $_nTrace1 +srcSelect -signal "b0_re" -line 47 -pos 1 -win $_nTrace1 +srcSelect -signal "a0_im" -line 46 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvCut -win $_nWave3 +wvSetPosition -win $_nWave3 {("G1" 12)} +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.U_ampmod" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U0_channel_top.U_awg_top.U_ampmod" \ + -delim "." +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.U_ampmod" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "Amp" -line 11 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "Amp" -line 11 -pos 1 -win $_nTrace1 +srcAction -pos 10 10 1 -win $_nTrace1 -name "Amp" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -signal "dnxt" -line 107 -pos 1 -win $_nTrace1 +srcAction -pos 106 12 3 -win $_nTrace1 -name "dnxt" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -signal "dnxt" -line 107 -pos 1 -win $_nTrace1 +srcAction -pos 106 12 2 -win $_nTrace1 -name "dnxt" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -signal "index_i" -line 60 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "index_vld_i" -line 61 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvSelectSignal -win $_nWave3 {( "G1" 14 )} +srcShowCalling -win $_nTrace1 +srcSelect -win $_nTrace1 -range {74 74 7 8 1 1} +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.ampr_lut.CS_SLV\[3\]" -win \ + $_nTrace1 +srcShowCalling -win $_nTrace1 +srcSelect -win $_nTrace1 -range {69 69 22 23 1 1} +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.ampr_lut" -win $_nTrace1 +srcShowCalling -win $_nTrace1 +srcSelect -win $_nTrace1 -range {152 152 4 5 1 1} +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "mod_amp_i" -line 158 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "z_bais_i" -line 174 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "mod_nco_pha_i" -line 142 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "mod_nco_fcw_i" -line 126 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 0 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +srcDeselectAll -win $_nTrace1 +debReload +wvZoom -win $_nWave3 17639.229249 30868.651185 +wvZoom -win $_nWave3 22467.528253 23576.335679 +wvZoom -win $_nWave3 22765.504883 22883.515429 +wvScrollDown -win $_nWave3 2 +wvSelectSignal -win $_nWave3 {( "G1" 21 )} +wvScrollDown -win $_nWave3 2 +wvSelectSignal -win $_nWave3 {( "G1" 21 22 23 24 25 26 27 28 29 )} +wvCut -win $_nWave3 +wvSetPosition -win $_nWave3 {("G1" 19)} +srcDeselectAll -win $_nTrace1 +srcSelect -signal "mod_nco_pha_i" -line 142 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "mcu_rz_pha" -line 47 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 1490799.375220 1694219.518976 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 1519440.570626 1619752.410917 +wvZoom -win $_nWave3 1537723.571229 1550134.659230 +wvSetCursor -win $_nWave3 1541559.725701 -snap {("G1" 21)} +wvZoomOut -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "mod_pha_sfot_clr" -line 74 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 1507869.597073 1648698.927366 +wvCut -win $_nWave3 +wvSetPosition -win $_nWave3 {("G1" 22)} +wvSetPosition -win $_nWave3 {("G1" 21)} +srcDeselectAll -win $_nTrace1 +srcSelect -signal "mcu_nco_pha_clr" -line 46 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.U_awg_ctrl" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U0_channel_top.U_awg_top.U_awg_ctrl" \ + -delim "." +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.U_awg_ctrl" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "mod_nco_pha_o" -line 114 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvZoom -win $_nWave3 1548588.321397 1552460.347330 +wvZoomOut -win $_nWave3 +wvSetCursor -win $_nWave3 1549904.466796 -snap {("G1" 23)} +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 1547708.315503 1551746.898649 +wvZoomOut -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "mod_nco_pha_o" -line 114 -pos 1 -win $_nTrace1 +srcAction -pos 113 10 8 -win $_nTrace1 -name "mod_nco_pha_o" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -signal "dnxt" -line 107 -pos 1 -win $_nTrace1 +srcAction -pos 106 12 1 -win $_nTrace1 -name "dnxt" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "nco_rz_pha" -line 259 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "nco_rz_pha_acc" -line 260 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcHBSelect "TB.U_digital_top.U0_channel_top.U_mcu_regfile" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U0_channel_top.U_mcu_regfile" -delim \ + "." +srcHBSelect "TB.U_digital_top.U0_channel_top.U_mcu_regfile" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "mcu_rz_pha" -line 131 -pos 1 -win $_nTrace1 +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.U_awg_ctrl" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U0_channel_top.U_awg_top.U_awg_ctrl" \ + -delim "." +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.U_awg_ctrl" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "muc_mod_nco_pha_i" -line 109 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvSetCursor -win $_nWave3 1549206.441801 -snap {("G1" 26)} +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.U_awg_ctrl.state_c_dffr" \ + -win $_nTrace1 +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.U_mod_nco" -win $_nTrace1 +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.U_mod_nco" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U0_channel_top.U_awg_top.U_mod_nco" \ + -delim "." +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.U_mod_nco" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "pha" -line 7 -pos 1 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -inst "inst_p_nco" -line 34 -pos 1 -win $_nTrace1 +srcAction -pos 33 3 6 -win $_nTrace1 -name "inst_p_nco" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -signal "pha" -line 26 -pos 1 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -inst "inst_pipe" -line 61 -pos 1 -win $_nTrace1 +srcAction -pos 60 2 3 -win $_nTrace1 -name "inst_pipe" -ctrlKey off +srcShowCalling -win $_nTrace1 +srcSelect -win $_nTrace1 -range {61 61 3 4 1 1} +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.U_mod_nco.inst_p_nco" -win \ + $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "pha0" -line 59 -pos 1 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "pha_r" -line 61 -pos 1 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "ptw" -line 61 -pos 1 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "pha_r" -line 61 -pos 1 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -inst "inst_pipe" -line 61 -pos 1 -win $_nTrace1 +srcAction -pos 60 2 4 -win $_nTrace1 -name "inst_pipe" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -signal "ptw" -line 8 -pos 1 -win $_nTrace1 +srcSearchString "ptw" -win $_nTrace1 -next -case +srcSearchString "ptw" -win $_nTrace1 -next -case +srcDeselectAll -win $_nTrace1 +srcSelect -signal "pha_w" -line 60 -pos 1 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "ptw" -line 60 -pos 1 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "pha_w" -line 60 -pos 1 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "pha_r" -line 60 -pos 1 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "pha_w" -line 60 -pos 1 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "pha_r" -line 60 -pos 1 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "pha_w" -line 60 -pos 1 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "pha_r" -line 60 -pos 1 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "ptw" -line 60 -pos 1 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "acc\[47:29\]" -line 57 -pos 1 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -win $_nTrace1 -range {44 45 4 1 1 1} -backward +srcDeselectAll -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "pha_w" -line 60 -pos 1 -win $_nTrace1 +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.U_awg_ctrl" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U0_channel_top.U_awg_top.U_awg_ctrl" \ + -delim "." +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.U_awg_ctrl" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "ilde2read" -line 185 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 0 +wvZoom -win $_nWave3 1549116.894502 1549389.118289 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "muc_mod_nco_rz_pha_i" -line 110 -pos 1 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "muc_mod_nco_pha_i" -line 109 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +debReload +srcDeselectAll -win $_nTrace1 +srcSelect -signal "mod_nco_pha_o" -line 114 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +debReload +wvSelectSignal -win $_nWave3 {( "G1" 27 )} +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.U_awg_ctrl" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U0_channel_top.U_awg_top.U_awg_ctrl" \ + -delim "." +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.U_awg_ctrl" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "muc_mod_nco_pha_r" -line 259 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "muc_mod_nco_rz_pha_i" -line 259 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 0 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "mod_nco_pha_o" -line 259 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvScrollDown -win $_nWave3 1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "enve_index_vld_i" -line 88 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.U_codeword_decode" -win \ + $_nTrace1 +srcSetScope -win $_nTrace1 \ + "TB.U_digital_top.U0_channel_top.U_awg_top.U_codeword_decode" \ + -delim "." +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.U_codeword_decode" -win \ + $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "index_vld_o" -line 58 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "nco_pha_index_o" -line 52 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.U_awg_ctrl" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U0_channel_top.U_awg_top.U_awg_ctrl" \ + -delim "." +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.U_awg_ctrl" -win $_nTrace1 +srcSelect -signal "enve_vld_o" -line 100 -pos 1 -win $_nTrace1 +srcSelect -signal "enve_qdata_o" -line 99 -pos 1 -win $_nTrace1 +wvSelectSignal -win $_nWave3 {( "G1" 24 )} +wvSelectAll -win $_nWave3 +wvCut -win $_nWave3 +wvSetPosition -win $_nWave3 {("G2" 0)} +srcSelect -signal "enve_idata_o" -line 98 -pos 1 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "enve_idata_o" -line 98 -pos 1 -win $_nTrace1 +srcSelect -signal "enve_qdata_o" -line 99 -pos 1 -win $_nTrace1 +srcSelect -signal "enve_vld_o" -line 100 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "mod_nco_pha_o" -line 114 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvZoom -win $_nWave3 1540808.395176 1543419.812003 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 1540654.952723 1543638.105604 +wvZoom -win $_nWave3 1541180.146378 1541947.431820 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "muc_mod_nco_pha_r" -line 259 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvSelectSignal -win $_nWave3 {( "G2" 5 )} +wvCut -win $_nWave3 +wvSetPosition -win $_nWave3 {("G3" 0)} +wvSetPosition -win $_nWave3 {("G2" 4)} +wvUnknownSaveResult -win $_nWave3 -clear +srcDeselectAll -win $_nTrace1 +debReload +wvSelectSignal -win $_nWave3 {( "G2" 3 )} +wvSetCursor -win $_nWave3 1541293.622961 -snap {("G2" 3)} +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 1541200.391824 1541821.025370 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +debReload +srcDeselectAll -win $_nTrace1 +debReload +wvSetCursor -win $_nWave3 1541957.674841 -snap {("G3" 0)} +srcDeselectAll -win $_nTrace1 +debReload +srcDeselectAll -win $_nTrace1 +srcSelect -signal "muc_mod_nco_rz_pha_i" -line 262 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvSetCursor -win $_nWave3 1541583.368135 -snap {("G2" 5)} +wvSelectSignal -win $_nWave3 {( "G2" 3 )} +srcDeselectAll -win $_nTrace1 +debReload +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 1539872.566307 1546354.677735 +srcHBSelect "TB" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB" -delim "." +srcHBSelect "TB" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "z_wave" -line 889 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 1521399.178603 1813322.472772 +wvZoom -win $_nWave3 1533568.043194 1565543.676746 +wvSelectSignal -win $_nWave3 {( "G2" 1 )} +wvBusWaveform -win $_nWave3 -analog +wvSetPosition -win $_nWave3 {("G2" 6)} +wvZoomOut -win $_nWave3 +srcDeselectAll -win $_nTrace1 +debReload +wvSelectSignal -win $_nWave3 {( "G2" 6 )} +wvBusWaveform -win $_nWave3 -analog +wvSetPosition -win $_nWave3 {("G2" 6)} +wvZoomOut -win $_nWave3 +wvZoomIn -win $_nWave3 +wvSetCursor -win $_nWave3 1542168.141531 -snap {("G2" 6)} +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoom -win $_nWave3 1541352.798325 1544401.472921 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 7181301.100630 12929208.768000 +wvZoom -win $_nWave3 8840674.888415 9638499.766414 +wvZoom -win $_nWave3 9091167.133924 9190939.469000 +wvZoom -win $_nWave3 9123288.958875 9130810.598327 +wvZoomOut -win $_nWave3 +wvSelectSignal -win $_nWave3 {( "G2" 4 )} +wvSelectSignal -win $_nWave3 {( "G2" 3 )} +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +srcDeselectAll -win $_nTrace1 +debReload +wvSetCursor -win $_nWave3 51041.981318 -snap {("G2" 6)} +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 1522144.800018 1975598.116191 +wvZoom -win $_nWave3 1665520.504865 1701917.422925 +wvZoomOut -win $_nWave3 +wvSelectSignal -win $_nWave3 {( "G2" 5 )} +wvSelectSignal -win $_nWave3 {( "G2" 3 )} +wvSelectAll -win $_nWave3 +wvCut -win $_nWave3 +wvSetPosition -win $_nWave3 {("G2" 0)} +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U0_channel_top.U_awg_top" -delim "." +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top" -win $_nTrace1 +srcSelect -signal "awg_vld" -line 83 -pos 1 -win $_nTrace1 +srcSelect -signal "awg_data_q" -line 82 -pos 1 -win $_nTrace1 +srcSelect -signal "awg_data_i" -line 81 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvZoom -win $_nWave3 1668369.310203 1670306.175022 +wvBusWaveform -win $_nWave3 -analog +wvAddSignal -win $_nWave3 \ + "/TB/U_digital_top/U0_channel_top/U_awg_top/DtoA_awg_vld" +wvSetPosition -win $_nWave3 {("G2" 3)} +wvSetPosition -win $_nWave3 {("G2" 4)} +wvSetPosition -win $_nWave3 {("G2" 4)} +wvSelectSignal -win $_nWave3 {( "G2" 1 )} +wvBusWaveform -win $_nWave3 -analog +wvSelectSignal -win $_nWave3 {( "G2" 2 )} +wvSetRadix -win $_nWave3 -2Com +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoom -win $_nWave3 1668269.246011 1670227.583833 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvSelectAll -win $_nWave3 +wvCut -win $_nWave3 +wvSetPosition -win $_nWave3 {("G2" 0)} +srcDeselectAll -win $_nTrace1 +srcSelect -signal "awg_data_i" -line 81 -pos 1 -win $_nTrace1 +srcAction -pos 80 11 3 -win $_nTrace1 -name "awg_data_i" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -signal "mux_data_i_w" -line 62 -pos 1 -win $_nTrace1 +srcAction -pos 61 6 4 -win $_nTrace1 -name "mux_data_i_w" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -signal "sel" -line 53 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "sel" -line 53 -pos 1 -win $_nTrace1 +srcAction -pos 52 12 2 -win $_nTrace1 -name "sel" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -signal "moddotren" -line 1138 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "moddotren" -line 1138 -pos 1 -win $_nTrace1 +srcAction -pos 1137 6 5 -win $_nTrace1 -name "moddotren" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -signal "moddotrwe" -line 357 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 20507.938922 107097.014373 +wvZoom -win $_nWave3 35137.844797 39438.499542 +wvShowFilterTextField -win $_nWave3 -on +srcDeselectAll -win $_nTrace1 +srcSelect -signal "moddotrwe" -line 357 -pos 1 -win $_nTrace1 +srcSearchString "moddotrwe" -win $_nTrace1 -next -case +srcSearchString "moddotrwe" -win $_nTrace1 -next -case +srcDeselectAll -win $_nTrace1 +srcSelect -signal "moddotr" -line 992 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U0_channel_top.U_awg_top" -delim "." +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "mod_dout_sel" -line 77 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "mod_dout_sel" -line 77 -pos 1 -win $_nTrace1 +srcAction -pos 76 4 7 -win $_nTrace1 -name "mod_dout_sel" -ctrlKey off +wvSetPosition -win $_nWave3 {("G2" 5)} +wvSetPosition -win $_nWave3 {("G2" 5)} +wvSetPosition -win $_nWave3 {("G2" 5)} +wvDisplayGridCount -win $_nWave3 -off +wvGetSignalClose -win $_nWave3 +wvReloadFile -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "rddata_reg" -line 1140 -pos 1 -win $_nTrace1 +debReload +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U0_channel_top.U_awg_top" -delim "." +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top" -win $_nTrace1 +srcSelect -signal "awg_vld" -line 83 -pos 1 -win $_nTrace1 +srcSelect -signal "awg_data_q" -line 82 -pos 1 -win $_nTrace1 +srcSelect -signal "awg_data_i" -line 81 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvSelectSignal -win $_nWave3 {( "G2" 7 )} +wvSetRadix -win $_nWave3 -2Com +wvBusWaveform -win $_nWave3 -analog +wvSetPosition -win $_nWave3 {("G2" 8)} +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomOut -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "awg_data_i" -line 81 -pos 1 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "awg_data_i" -line 81 -pos 1 -win $_nTrace1 +srcAction -pos 80 11 7 -win $_nTrace1 -name "awg_data_i" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -signal "mux_data_i_w" -line 62 -pos 1 -win $_nTrace1 +srcAction -pos 61 6 4 -win $_nTrace1 -name "mux_data_i_w" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "sin" -line 53 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +debReload +srcDeselectAll -win $_nTrace1 +srcSelect -signal "sin" -line 53 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvSetRadix -win $_nWave3 -2Com +wvBusWaveform -win $_nWave3 -analog +wvSetPosition -win $_nWave3 {("G2" 9)} +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvSelectSignal -win $_nWave3 {( "G2" 8 )} +wvSetRadix -win $_nWave3 -2Com +wvBusWaveform -win $_nWave3 -analog +wvSetPosition -win $_nWave3 {("G2" 9)} +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +srcHBSelect "TB.U_digital_top.U0_channel_top.U_xy_dsp" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U0_channel_top.U_xy_dsp" -delim "." +srcHBSelect "TB.U_digital_top.U0_channel_top.U_xy_dsp" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "dout0" -line 55 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "din_vld" -line 53 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "din_q" -line 52 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "din_i" -line 50 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "dout15" -line 70 -pos 1 -win $_nTrace1 +srcAction -pos 69 10 2 -win $_nTrace1 -name "dout15" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -signal "dout15_r" -line 367 -pos 1 -win $_nTrace1 +srcAction -pos 366 6 5 -win $_nTrace1 -name "dout15_r" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -signal "dac_mode_sel" -line 257 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "mux_p_0" -line 313 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "mux_p_0" -line 313 -pos 1 -win $_nTrace1 +srcAction -pos 312 5 4 -win $_nTrace1 -name "mux_p_0" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -signal "intp_mode" -line 122 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "din0\[15\]" -line 196 -pos 1 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "din0\[14:0\]" -line 196 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "din0\[14:0\]" -line 196 -pos 1 -win $_nTrace1 +srcAction -pos 195 9 2 -win $_nTrace1 -name "din0\[14:0\]" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -signal "dout_i_r0" -line 432 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "dout_i_r0" -line 432 -pos 1 -win $_nTrace1 +srcAction -pos 431 6 3 -win $_nTrace1 -name "dout_i_r0" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -signal "mix_dout_vld" -line 335 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "qam_mod" -line 354 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "cos_0" -line 392 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "cos_1" -line 393 -pos 1 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "cos_0" -line 392 -pos 1 -win $_nTrace1 +srcAction -pos 391 5 4 -win $_nTrace1 -name "cos_0" -ctrlKey off +srcHBSelect "TB.U_digital_top.U0_channel_top.U_xy_dsp.inst_qam_top.inst_nco_0" \ + -win $_nTrace1 +srcSetScope -win $_nTrace1 \ + "TB.U_digital_top.U0_channel_top.U_xy_dsp.inst_qam_top.inst_nco_0" \ + -delim "." +srcHBSelect "TB.U_digital_top.U0_channel_top.U_xy_dsp.inst_qam_top.inst_nco_0" \ + -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "phase_auto_clr" -line 5 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "phase_manual_clr" -line 4 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvScrollUp -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 0 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "phase_auto_clr" -line 5 -pos 1 -win $_nTrace1 +srcAction -pos 4 1 9 -win $_nTrace1 -name "phase_auto_clr" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -signal "qam_nco_sclr_en" -line 556 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcHBSelect "TB.U_digital_top.U0_channel_top.U_qbmcu_busdecoder" -win $_nTrace1 +srcHBSelect "TB.U_digital_top.U0_channel_top.U_xy_dsp.inst_qam_top" -win \ + $_nTrace1 +srcSetScope -win $_nTrace1 \ + "TB.U_digital_top.U0_channel_top.U_xy_dsp.inst_qam_top" -delim "." +srcHBSelect "TB.U_digital_top.U0_channel_top.U_xy_dsp.inst_qam_top" -win \ + $_nTrace1 +srcDeselectAll -win $_nTrace1 +debReload +wvSelectSignal -win $_nWave3 {( "G2" 21 )} +wvSetRadix -win $_nWave3 -2Com +wvBusWaveform -win $_nWave3 -analog +wvSetPosition -win $_nWave3 {("G2" 24)} +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvSetRadix -win $_nWave3 -Unsigned +wvSetRadix -win $_nWave3 -2Com +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvScrollDown -win $_nWave3 2 +wvScrollUp -win $_nWave3 2 +wvCut -win $_nWave3 +wvSetPosition -win $_nWave3 {("G3" 0)} +wvSetPosition -win $_nWave3 {("G2" 23)} +wvSetPosition -win $_nWave3 {("G2" 23)} +wvSetPosition -win $_nWave3 {("G2" 23)} +wvSetPosition -win $_nWave3 {("G2" 23)} +wvSelectSignal -win $_nWave3 {( "G2" 19 )} +wvSelectAll -win $_nWave3 +wvCut -win $_nWave3 +wvSetPosition -win $_nWave3 {("G2" 0)} +wvSetPosition -win $_nWave3 {("G2" 0)} +wvSetPosition -win $_nWave3 {("G2" 0)} +wvSetPosition -win $_nWave3 {("G2" 0)} +srcHBSelect "TB.U_digital_top.U0_channel_top.U_xy_dsp.inst_qam_top" -win \ + $_nTrace1 +srcSetScope -win $_nTrace1 \ + "TB.U_digital_top.U0_channel_top.U_xy_dsp.inst_qam_top" -delim "." +srcHBSelect "TB.U_digital_top.U0_channel_top.U_xy_dsp.inst_qam_top" -win \ + $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "din_i_0" -line 51 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcSelect -signal "dout_i_0" -line 85 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvSelectSignal -win $_nWave3 {( "G2" 1 2 3 )} +wvSelectSignal -win $_nWave3 {( "G2" 3 )} +wvSelectAll -win $_nWave3 +wvCut -win $_nWave3 +wvSetPosition -win $_nWave3 {("G2" 0)} +wvSetPosition -win $_nWave3 {("G2" 0)} +wvSetPosition -win $_nWave3 {("G2" 0)} +wvSetPosition -win $_nWave3 {("G2" 0)} +srcHBSelect "TB" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB" -delim "." +srcHBSelect "TB" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "cs_wave" -line 853 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvBusWaveform -win $_nWave3 -analog +wvSetPosition -win $_nWave3 {("G2" 1)} +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +srcHBSelect "TB.U_digital_top" -win $_nTrace1 +schCreateWindow -delim "." -win $_nSchema1 -scope "TB" +schSelect -win $_nSchema4 -inst "U_digital_top" +schPushViewIn -win $_nSchema4 +schZoomIn -win $_nSchema4 -pos 116728 -77225 +schZoomIn -win $_nSchema4 -pos 115061 -77559 +schZoomIn -win $_nSchema4 -pos 91054 -68057 +schZoomIn -win $_nSchema4 -pos 90865 -68808 +schZoomOut -win $_nSchema4 -pos 90162 -69371 +schZoomIn -win $_nSchema4 -pos 84535 -52756 +schZoomIn -win $_nSchema4 -pos 84535 -52756 +schZoomOut -win $_nSchema4 -pos 82162 -52558 +schZoomOut -win $_nSchema4 -pos 81914 -52559 +schZoomIn -win $_nSchema4 -pos 167219 -67901 +schZoomIn -win $_nSchema4 -pos 165017 -68829 +schSelect -win $_nSchema4 -inst "U0_channel_top" +schPushViewIn -win $_nSchema4 +schSelect -win $_nSchema4 -inst "U_z_dsp" +schSelect -win $_nSchema4 -inst "U_xy_dsp" +schZoomIn -win $_nSchema4 -pos 212276 79892 +schZoomIn -win $_nSchema4 -pos 212096 79531 +schZoomIn -win $_nSchema4 -pos 212366 78447 +schZoomIn -win $_nSchema4 -pos 212417 78040 +schZoomIn -win $_nSchema4 -pos 212418 77926 +schZoomIn -win $_nSchema4 -pos 212390 77612 +schZoomIn -win $_nSchema4 -pos 212196 77654 +schZoomIn -win $_nSchema4 -pos 212196 77654 +schZoomIn -win $_nSchema4 -pos 212195 77654 +schZoomIn -win $_nSchema4 -pos 210867 77951 +schZoomIn -win $_nSchema4 -pos 210867 77952 +schZoomOut -win $_nSchema4 -pos 210770 77996 +schZoomOut -win $_nSchema4 -pos 210770 77996 +schSelect -win $_nSchema4 -port "z_dsp_dout0\[15:0\]" +schZoomOut -win $_nSchema4 -pos 209339 77448 +schZoomOut -win $_nSchema4 -pos 209339 77447 +schZoomOut -win $_nSchema4 -pos 209326 77447 +schZoomOut -win $_nSchema4 -pos 209324 77446 +schZoomOut -win $_nSchema4 -pos 209324 77446 +schZoomOut -win $_nSchema4 -pos 209324 77446 +schZoomOut -win $_nSchema4 -pos 209384 77931 +schZoomOut -win $_nSchema4 -pos 209383 77930 +schZoomOut -win $_nSchema4 -pos 209383 77930 +schZoomOut -win $_nSchema4 -pos 209382 77930 +schSelect -win $_nSchema4 -signal "clk" +schZoomOut -win $_nSchema4 -pos 217152 69389 +schZoomOut -win $_nSchema4 -pos 217151 69389 +schZoomOut -win $_nSchema4 -pos 216341 71123 +schSelect -win $_nSchema4 -signal "dac_Cal_end" +schSelect -win $_nSchema4 -signal "dac_rden" +schSelect -win $_nSchema4 -signal "dac_rwaddr\[15:0\]" +schSelect -win $_nSchema4 -signal "dac_wrdata\[31:0\]" +schSelect -win $_nSchema4 -signal "clk" +schSelect -win $_nSchema4 -signal "dac_wrdata\[31:0\]" +schSelect -win $_nSchema4 -signal "rst_n" +schSelect -win $_nSchema4 -signal "dac_wrdata\[31:0\]" +schSelect -win $_nSchema4 -signal "dac_rwaddr\[15:0\]" +schSelect -win $_nSchema4 -signal "dac_wren" +schSelect -win $_nSchema4 -signal "dac_Cal_end" +schSelect -win $_nSchema4 -signal "dac_rden" +schSelect -win $_nSchema4 -signal "dac_rwaddr\[15:0\]" +schDeselectAll -win $_nSchema4 +schZoomIn -win $_nSchema4 -pos 185270 24444 +schZoomIn -win $_nSchema4 -pos 185921 23360 +schZoomIn -win $_nSchema4 -pos 185921 23197 +schZoomIn -win $_nSchema4 -pos 185860 23013 +schZoomIn -win $_nSchema4 -pos 185722 22738 +schZoomIn -win $_nSchema4 -pos 185585 22601 +schZoomOut -win $_nSchema4 -pos 180234 24479 +schZoomOut -win $_nSchema4 -pos 180105 24478 +schZoomOut -win $_nSchema4 -pos 180065 24479 +schZoomOut -win $_nSchema4 -pos 180015 24478 +schZoomOut -win $_nSchema4 -pos 180014 24478 +schZoomIn -win $_nSchema4 -pos 189747 45749 +schZoomIn -win $_nSchema4 -pos 189806 45396 +schZoomIn -win $_nSchema4 -pos 189806 44998 +schZoomOut -win $_nSchema4 -pos 189805 44866 +schZoomOut -win $_nSchema4 -pos 189804 44866 +schSelect -win $_nSchema4 -inst "U_xy_dsp" +srcHBSelect "TB.U_digital_top.U0_channel_top.U_z_dsp" -win $_nTrace1 +srcHBSelect "TB.U_digital_top.U0_channel_top.U_z_dsp" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U0_channel_top.U_z_dsp" -delim "." +srcHBSelect "TB.U_digital_top.U0_channel_top.U_z_dsp" -win $_nTrace1 +srcHBSelect "TB.U_digital_top.U0_channel_top.U_z_dsp.inst_TailCorr_top" -win \ + $_nTrace1 +srcHBSelect "TB.U_digital_top.U0_channel_top.U_ctrl_regfile" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U0_channel_top.U_ctrl_regfile" \ + -delim "." +srcHBSelect "TB.U_digital_top.U0_channel_top.U_ctrl_regfile" -win $_nTrace1 +wvSelectSignal -win $_nWave3 {( "G2" 1 )} +srcHBSelect "TB" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB" -delim "." +srcHBSelect "TB" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "z_wave" -line 898 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +debReload +srcDeselectAll -win $_nTrace1 +srcSelect -signal "cs_wave" -line 897 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "cs_wave" -line 897 -pos 1 -win $_nTrace1 +srcAction -pos 896 4 3 -win $_nTrace1 -name "cs_wave" -ctrlKey off +wvSelectSignal -win $_nWave3 {( "G2" 1 2 )} +wvSelectSignal -win $_nWave3 {( "G2" 1 )} +wvCut -win $_nWave3 +wvSetPosition -win $_nWave3 {("G3" 0)} +wvSetPosition -win $_nWave3 {("G2" 1)} +wvSetPosition -win $_nWave3 {("G2" 1)} +wvSetPosition -win $_nWave3 {("G2" 1)} +wvSetPosition -win $_nWave3 {("G2" 1)} +wvSelectGroup -win $_nWave3 {G3} +wvSelectSignal -win $_nWave3 {( "G2" 1 )} +wvCut -win $_nWave3 +wvSetPosition -win $_nWave3 {("G3" 0)} +wvSetPosition -win $_nWave3 {("G2" 0)} +wvSetPosition -win $_nWave3 {("G2" 0)} +wvSetPosition -win $_nWave3 {("G2" 0)} +wvSetPosition -win $_nWave3 {("G2" 0)} +srcDeselectAll -win $_nTrace1 +srcSelect -signal "z_wave" -line 1000 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvBusWaveform -win $_nWave3 -analog +wvSetPosition -win $_nWave3 {("G2" 1)} +wvZoom -win $_nWave3 1624257.410195 2161890.399118 +wvZoom -win $_nWave3 1735598.698810 1771361.425346 +wvZoom -win $_nWave3 1737771.423215 1742513.354583 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "z_cs_0" -line 988 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvBusWaveform -win $_nWave3 -analog +wvSetPosition -win $_nWave3 {("G2" 2)} +wvSetCursor -win $_nWave3 1739115.145673 -snap {("G2" 2)} +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 4645603.362027 5425549.810745 +wvZoom -win $_nWave3 5081059.051133 5128443.824292 +wvZoom -win $_nWave3 5107892.911587 5110309.429952 +wvZoom -win $_nWave3 5109159.574428 5109305.315669 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "intp_mode" -line 985 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +debReload +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 199821.611845 406194.751947 +wvZoom -win $_nWave3 257020.375731 266904.322131 +wvZoom -win $_nWave3 259983.368088 261158.045532 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +srcHBSelect "TB.U_digital_top" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +debReload +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +srcHBSelect "TB.U_digital_top.U0_channel_top" -win $_nTrace1 +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U0_channel_top.U_awg_top" -delim "." +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top" -win $_nTrace1 +srcSelect -signal "awg_vld" -line 83 -pos 1 -win $_nTrace1 +srcSelect -signal "awg_data_q" -line 82 -pos 1 -win $_nTrace1 +srcSelect -signal "awg_data_i" -line 81 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 1892643.680488 3235810.163415 +wvZoom -win $_nWave3 2020110.477536 2101713.053218 +wvZoom -win $_nWave3 2032957.002754 2038204.175026 +wvSetRadix -win $_nWave3 -2Com +wvBusWaveform -win $_nWave3 -analog +wvAddSignal -win $_nWave3 \ + "/TB/U_digital_top/U0_channel_top/U_awg_top/DtoA_awg_vld" +wvSetPosition -win $_nWave3 {("G2" 6)} +wvSetPosition -win $_nWave3 {("G2" 7)} +wvSetPosition -win $_nWave3 {("G2" 6)} +wvSetPosition -win $_nWave3 {("G2" 7)} +wvSetPosition -win $_nWave3 {("G2" 7)} +wvSetPosition -win $_nWave3 {("G2" 7)} +wvSetPosition -win $_nWave3 {("G2" 7)} +wvSetPosition -win $_nWave3 {("G2" 7)} +wvSelectSignal -win $_nWave3 {( "G2" 7 )} +wvSelectSignal -win $_nWave3 {( "G2" 7 )} +wvCut -win $_nWave3 +wvSetPosition -win $_nWave3 {("G3" 0)} +wvSetPosition -win $_nWave3 {("G2" 6)} +wvSetPosition -win $_nWave3 {("G2" 6)} +wvSetPosition -win $_nWave3 {("G2" 6)} +wvSetPosition -win $_nWave3 {("G2" 6)} +srcDeselectAll -win $_nTrace1 +srcSelect -signal "awg_vld" -line 83 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcHBSelect "TB.U_digital_top.U0_channel_top.U_z_data_mux" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U0_channel_top.U_z_data_mux" -delim \ + "." +srcHBSelect "TB.U_digital_top.U0_channel_top.U_z_data_mux" -win $_nTrace1 +srcHBSelect "TB.U_digital_top.U0_channel_top.U_z_dsp" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U0_channel_top.U_z_dsp" -delim "." +srcHBSelect "TB.U_digital_top.U0_channel_top.U_z_dsp" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "din_re" -line 43 -pos 1 -win $_nTrace1 +srcSelect -signal "din_im" -line 44 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvSetRadix -win $_nWave3 -2Com +wvBusWaveform -win $_nWave3 -analog +wvSetPosition -win $_nWave3 {("G2" 9)} +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "dout0" -line 69 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvSetRadix -win $_nWave3 -2Com +wvBusWaveform -win $_nWave3 -analog +wvSetPosition -win $_nWave3 {("G2" 10)} +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvSetCursor -win $_nWave3 2034987.227946 -snap {("G2" 8)} +wvSetCursor -win $_nWave3 2034279.848624 -snap {("G2" 8)} +wvSetCursor -win $_nWave3 2034735.922134 -snap {("G2" 10)} +srcHBSelect "TB.U_digital_top.U0_channel_top.U_xy_dsp" -win $_nTrace1 +srcHBSelect "TB.U_digital_top.U0_channel_top.U_z_data_mux" -win $_nTrace1 +srcHBSelect "TB.U_digital_top.U0_channel_top.U_xy_dsp" -win $_nTrace1 +srcHBSelect "TB.U_digital_top.U0_channel_top.U_z_dsp" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U0_channel_top.U_z_dsp" -delim "." +srcHBSelect "TB.U_digital_top.U0_channel_top.U_z_dsp" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "tc_bypass" -line 41 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "intp_mode" -line 42 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -win $_nTrace1 -range {42 42 9 9 24 29} +srcDeselectAll -win $_nTrace1 +srcSelect -signal "dout1" -line 70 -pos 1 -win $_nTrace1 +srcSelect -signal "dout2" -line 71 -pos 1 -win $_nTrace1 +srcSelect -signal "dout3" -line 72 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvScrollDown -win $_nWave3 1 +wvSetRadix -win $_nWave3 -2Com +wvBusWaveform -win $_nWave3 -analog +wvSetPosition -win $_nWave3 {("G2" 15)} +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 0 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvSetCursor -win $_nWave3 2026412.580574 -snap {("G2" 8)} +wvSetCursor -win $_nWave3 2031085.007147 -snap {("G2" 10)} +wvSelectSignal -win $_nWave3 {( "G2" 10 )} +wvAddSignal -win $_nWave3 \ + "/TB/U_digital_top/U0_channel_top/U_z_dsp/dout0\[15:0\]" +wvSetPosition -win $_nWave3 {("G2" 15)} +wvSetPosition -win $_nWave3 {("G2" 16)} +wvSetPosition -win $_nWave3 {("G2" 15)} +wvSetPosition -win $_nWave3 {("G2" 16)} +wvSetPosition -win $_nWave3 {("G2" 16)} +wvSetPosition -win $_nWave3 {("G2" 16)} +wvSetPosition -win $_nWave3 {("G2" 16)} +wvSelectSignal -win $_nWave3 {( "G2" 15 )} +wvCut -win $_nWave3 +wvSetPosition -win $_nWave3 {("G3" 0)} +wvSetPosition -win $_nWave3 {("G2" 15)} +wvSetPosition -win $_nWave3 {("G2" 15)} +wvSetPosition -win $_nWave3 {("G2" 15)} +wvSetPosition -win $_nWave3 {("G2" 15)} +wvSelectSignal -win $_nWave3 {( "G2" 14 )} +wvCut -win $_nWave3 +wvSetPosition -win $_nWave3 {("G3" 0)} +wvSetPosition -win $_nWave3 {("G2" 14)} +wvSetPosition -win $_nWave3 {("G2" 14)} +wvSetPosition -win $_nWave3 {("G2" 14)} +wvSetPosition -win $_nWave3 {("G2" 14)} +wvSelectSignal -win $_nWave3 {( "G2" 13 )} +wvCut -win $_nWave3 +wvSetPosition -win $_nWave3 {("G3" 0)} +wvSetPosition -win $_nWave3 {("G2" 13)} +wvSetPosition -win $_nWave3 {("G2" 13)} +wvSetPosition -win $_nWave3 {("G2" 13)} +wvSetPosition -win $_nWave3 {("G2" 13)} +wvSelectSignal -win $_nWave3 {( "G2" 12 )} +wvCut -win $_nWave3 +wvSetPosition -win $_nWave3 {("G3" 0)} +wvSetPosition -win $_nWave3 {("G2" 12)} +wvSetPosition -win $_nWave3 {("G2" 12)} +wvSetPosition -win $_nWave3 {("G2" 12)} +wvSetPosition -win $_nWave3 {("G2" 12)} +wvZoom -win $_nWave3 2022317.226605 2029204.867371 +wvZoom -win $_nWave3 2022967.810855 2024800.442544 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 2019407.791735 2020422.037565 +wvSelectSignal -win $_nWave3 {( "G2" 12 )} +wvExpandBus -win $_nWave3 {("G2" 12)} +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "dout0" -line 69 -pos 1 -win $_nTrace1 +srcAction -pos 68 3 1 -win $_nTrace1 -name "dout0" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -signal "din0\[14:0\]" -line 107 -pos 1 -win $_nTrace1 +srcAction -pos 106 12 5 -win $_nTrace1 -name "din0\[14:0\]" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -signal "mux_p_0" -line 127 -pos 1 -win $_nTrace1 +srcAction -pos 126 6 2 -win $_nTrace1 -name "mux_p_0" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -signal "dt2_p_0" -line 112 -pos 1 -win $_nTrace1 +srcAction -pos 111 8 3 -win $_nTrace1 -name "dt2_p_0" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -signal "mean_temp" -line 106 -pos 1 -win $_nTrace1 +srcAction -pos 105 6 4 -win $_nTrace1 -name "mean_temp" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -signal "sum_0_1\[16:1\]" -line 79 -pos 1 -win $_nTrace1 +srcAction -pos 78 8 2 -win $_nTrace1 -name "sum_0_1\[16:1\]" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -signal "din_1" -line 63 -pos 1 -win $_nTrace1 +srcAction -pos 62 32 1 -win $_nTrace1 -name "din_1" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -signal "din_0" -line 66 -pos 1 -win $_nTrace1 +srcAction -pos 65 9 3 -win $_nTrace1 -name "din_0" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -signal "din_r2" -line 107 -pos 1 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "din_r2" -line 107 -pos 1 -win $_nTrace1 +srcAction -pos 106 6 4 -win $_nTrace1 -name "din_r2" -ctrlKey off +srcHBSelect \ + "TB.U_digital_top.U0_channel_top.U_z_dsp.inst_MeanIntp4.inst_MeanIntp_s1" \ + -win $_nTrace1 +srcSetScope -win $_nTrace1 \ + "TB.U_digital_top.U0_channel_top.U_z_dsp.inst_MeanIntp4.inst_MeanIntp_s1" \ + -delim "." +srcHBSelect \ + "TB.U_digital_top.U0_channel_top.U_z_dsp.inst_MeanIntp4.inst_MeanIntp_s1" \ + -win $_nTrace1 +srcHBSelect \ + "TB.U_digital_top.U0_channel_top.U_z_dsp.inst_MeanIntp4.inst_MeanIntp_s1.inst0_MeanIntp" \ + -win $_nTrace1 +srcHBSelect "TB.U_digital_top.U0_channel_top.U_z_dsp.inst_TailCorr_top" -win \ + $_nTrace1 +srcSetScope -win $_nTrace1 \ + "TB.U_digital_top.U0_channel_top.U_z_dsp.inst_TailCorr_top" -delim \ + "." +srcHBSelect "TB.U_digital_top.U0_channel_top.U_z_dsp.inst_TailCorr_top" -win \ + $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "dout" -line 67 -pos 1 -win $_nTrace1 +srcAction -pos 66 3 0 -win $_nTrace1 -name "dout" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -signal "Ysum\[16:15\]" -line 255 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvSelectSignal -win $_nWave3 {( "G2" 29 )} +srcDeselectAll -win $_nTrace1 +srcSelect -signal "Ysum" -line 244 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvSetRadix -win $_nWave3 -2Com +wvBusWaveform -win $_nWave3 -analog +wvSetPosition -win $_nWave3 {("G2" 30)} +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvZoomOut -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomOut -win $_nWave3 +wvScrollUp -win $_nWave3 8 +wvScrollUp -win $_nWave3 2 +wvScrollDown -win $_nWave3 3 +wvSelectSignal -win $_nWave3 {( "G2" 8 )} +wvSetPosition -win $_nWave3 {("G2" 8)} +wvSetPosition -win $_nWave3 {("G2" 9)} +wvSetPosition -win $_nWave3 {("G2" 10)} +wvSetPosition -win $_nWave3 {("G2" 11)} +wvSetPosition -win $_nWave3 {("G2" 12)} +wvSetPosition -win $_nWave3 {("G2" 13)} +wvSetPosition -win $_nWave3 {("G2" 14)} +wvSetPosition -win $_nWave3 {("G2" 15)} +wvSetPosition -win $_nWave3 {("G2" 16)} +wvSetPosition -win $_nWave3 {("G2" 17)} +wvSetPosition -win $_nWave3 {("G2" 23)} +wvSetPosition -win $_nWave3 {("G2" 28)} +wvSetPosition -win $_nWave3 {("G2" 30)} +wvSetPosition -win $_nWave3 {("G3" 0)} +wvSetPosition -win $_nWave3 {("G2" 30)} +wvMoveSelected -win $_nWave3 +wvSetPosition -win $_nWave3 {("G2" 30)} +wvSetPosition -win $_nWave3 {("G2" 30)} +wvSetPosition -win $_nWave3 {("G2" 30)} +wvSetPosition -win $_nWave3 {("G2" 30)} +wvScrollDown -win $_nWave3 4 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvSelectSignal -win $_nWave3 {( "G2" 30 )} +wvSelectSignal -win $_nWave3 {( "G2" 30 )} +wvSelectSignal -win $_nWave3 {( "G2" 29 )} +wvSetPosition -win $_nWave3 {("G2" 29)} +wvSetPosition -win $_nWave3 {("G2" 30)} +wvMoveSelected -win $_nWave3 +wvSetPosition -win $_nWave3 {("G2" 30)} +wvSetPosition -win $_nWave3 {("G2" 30)} +wvSetPosition -win $_nWave3 {("G2" 30)} +wvSetPosition -win $_nWave3 {("G2" 30)} +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvSelectSignal -win $_nWave3 {( "G2" 29 )} +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvSelectSignal -win $_nWave3 {( "G2" 30 )} +wvSetCursor -win $_nWave3 2018959.589530 -snap {("G3" 0)} +wvSetCursor -win $_nWave3 2018905.616360 -snap {("G3" 0)} +wvSetCursor -win $_nWave3 2018855.241400 -snap {("G2" 30)} +wvSelectSignal -win $_nWave3 {( "G2" 30 )} +wvSetRadix -win $_nWave3 -format UDec +wvSetCursor -win $_nWave3 2018369.482865 -snap {("G2" 30)} +wvSetCursor -win $_nWave3 2018121.206280 -snap {("G2" 30)} +wvSetCursor -win $_nWave3 2018920.009205 -snap {("G2" 30)} +wvSelectSignal -win $_nWave3 {( "G2" 30 )} +wvExpandBus -win $_nWave3 {("G2" 30)} +wvScrollUp -win $_nWave3 1 +wvSelectSignal -win $_nWave3 {( "G2" 36 )} +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvSelectSignal -win $_nWave3 {( "G2" 33 )} +wvSelectSignal -win $_nWave3 {( "G2" 34 )} +wvSelectSignal -win $_nWave3 {( "G2" 33 34 )} +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvScrollUp -win $_nWave3 4 +wvSelectSignal -win $_nWave3 {( "G2" 29 )} +wvSetPosition -win $_nWave3 {("G2" 29)} +wvExpandBus -win $_nWave3 {("G2" 29)} +wvSetPosition -win $_nWave3 {("G2" 65)} +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvSelectSignal -win $_nWave3 {( "G2" 29 )} +wvSetPosition -win $_nWave3 {("G2" 29)} +wvCollapseBus -win $_nWave3 {("G2" 29)} +wvSetPosition -win $_nWave3 {("G2" 29)} +wvSetPosition -win $_nWave3 {("G2" 29)} +wvSetPosition -win $_nWave3 {("G2" 29)} +wvSetPosition -win $_nWave3 {("G2" 29)} +wvSetPosition -win $_nWave3 {("G2" 49)} +wvScrollUp -win $_nWave3 20 +wvSelectSignal -win $_nWave3 {( "G2" 10 )} +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvSelectSignal -win $_nWave3 {( "G2" 11 )} +wvSetPosition -win $_nWave3 {("G2" 11)} +wvSetPosition -win $_nWave3 {("G2" 12)} +wvSetPosition -win $_nWave3 {("G2" 13)} +wvSetPosition -win $_nWave3 {("G2" 14)} +wvSetPosition -win $_nWave3 {("G2" 15)} +wvSetPosition -win $_nWave3 {("G2" 16)} +wvSetPosition -win $_nWave3 {("G2" 17)} +wvSetPosition -win $_nWave3 {("G2" 18)} +wvSetPosition -win $_nWave3 {("G2" 19)} +wvSetPosition -win $_nWave3 {("G2" 20)} +wvSetPosition -win $_nWave3 {("G2" 21)} +wvSetPosition -win $_nWave3 {("G2" 22)} +wvSetPosition -win $_nWave3 {("G2" 23)} +wvSetPosition -win $_nWave3 {("G2" 24)} +wvSetPosition -win $_nWave3 {("G2" 25)} +wvSetPosition -win $_nWave3 {("G2" 26)} +wvSetPosition -win $_nWave3 {("G2" 27)} +wvSetPosition -win $_nWave3 {("G2" 29)} +wvSetPosition -win $_nWave3 {("G2" 30)} +wvSetPosition -win $_nWave3 {("G2" 31)} +wvSetPosition -win $_nWave3 {("G2" 32)} +wvSetPosition -win $_nWave3 {("G2" 33)} +wvSetPosition -win $_nWave3 {("G2" 32)} +wvSetPosition -win $_nWave3 {("G2" 31)} +wvSetPosition -win $_nWave3 {("G2" 30)} +wvSetPosition -win $_nWave3 {("G2" 31)} +wvSetPosition -win $_nWave3 {("G2" 32)} +wvSetPosition -win $_nWave3 {("G2" 33)} +wvSetPosition -win $_nWave3 {("G2" 34)} +wvSetPosition -win $_nWave3 {("G2" 35)} +wvSetPosition -win $_nWave3 {("G2" 36)} +wvSetPosition -win $_nWave3 {("G2" 37)} +wvSetPosition -win $_nWave3 {("G2" 38)} +wvSetPosition -win $_nWave3 {("G2" 39)} +wvSetPosition -win $_nWave3 {("G2" 40)} +wvSetPosition -win $_nWave3 {("G2" 39)} +wvSetPosition -win $_nWave3 {("G2" 38)} +wvSetPosition -win $_nWave3 {("G2" 37)} +wvSetPosition -win $_nWave3 {("G2" 36)} +wvSetPosition -win $_nWave3 {("G2" 35)} +wvSetPosition -win $_nWave3 {("G2" 34)} +wvSetPosition -win $_nWave3 {("G2" 33)} +wvSetPosition -win $_nWave3 {("G2" 32)} +wvSetPosition -win $_nWave3 {("G2" 31)} +wvSetPosition -win $_nWave3 {("G2" 30)} +wvSetPosition -win $_nWave3 {("G2" 29)} +wvSetPosition -win $_nWave3 {("G2" 30)} +wvSetPosition -win $_nWave3 {("G2" 31)} +wvSetPosition -win $_nWave3 {("G2" 32)} +wvSetPosition -win $_nWave3 {("G2" 31)} +wvSetPosition -win $_nWave3 {("G2" 30)} +wvSetPosition -win $_nWave3 {("G2" 29)} +wvMoveSelected -win $_nWave3 +wvSetPosition -win $_nWave3 {("G2" 29)} +wvSetPosition -win $_nWave3 {("G2" 29)} +wvSetPosition -win $_nWave3 {("G2" 29)} +wvSetPosition -win $_nWave3 {("G2" 29)} +wvSelectSignal -win $_nWave3 {( "G2" 30 )} +wvSelectSignal -win $_nWave3 {( "G2" 29 )} +wvSelectSignal -win $_nWave3 {( "G2" 29 )} +wvSelectSignal -win $_nWave3 {( "G2" 29 )} +wvExpandBus -win $_nWave3 {("G2" 29)} +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvSelectSignal -win $_nWave3 {( "G2" 30 )} +wvSelectSignal -win $_nWave3 {( "G2" 29 )} +wvSetPosition -win $_nWave3 {("G2" 29)} +wvCollapseBus -win $_nWave3 {("G2" 29)} +wvSetPosition -win $_nWave3 {("G2" 29)} +wvSetPosition -win $_nWave3 {("G2" 29)} +wvSetPosition -win $_nWave3 {("G2" 29)} +wvSetPosition -win $_nWave3 {("G2" 29)} +wvSetRadix -win $_nWave3 -Unsigned +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvBusWaveform -win $_nWave3 -analog +wvSetPosition -win $_nWave3 {("G2" 29)} +wvZoom -win $_nWave3 2010336.475976 2012250.724426 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvSetCursor -win $_nWave3 2010950.648371 -snap {("G2" 29)} +wvSetCursor -win $_nWave3 2011690.881031 -snap {("G2" 29)} +wvSetCursor -win $_nWave3 2011514.311773 -snap {("G2" 29)} +wvSetCursor -win $_nWave3 2010726.541236 -snap {("G2" 28)} +wvScrollUp -win $_nWave3 29 +wvSelectSignal -win $_nWave3 {( "G2" 1 )} +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +srcHBSelect "TB" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB" -delim "." +srcHBSelect "TB" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "z_wave" -line 989 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvSetCursor -win $_nWave3 1160007.417073 -snap {("G2" 29)} +srcDeselectAll -win $_nTrace1 +srcSelect -signal "intp_mode" -line 986 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +debReload +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "z_cs_0" -line 989 -pos 1 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "z_cs_0" -line 976 -pos 1 -win $_nTrace1 +srcSelect -signal "z_cs_1" -line 977 -pos 1 -win $_nTrace1 +srcSelect -signal "z_cs_2" -line 978 -pos 1 -win $_nTrace1 +srcSelect -signal "z_cs_3" -line 979 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "ch0_z_dsp_dout0" -line 976 -pos 1 -win $_nTrace1 +srcSelect -signal "ch0_z_dsp_dout1" -line 977 -pos 1 -win $_nTrace1 +srcSelect -signal "ch0_z_dsp_dout2" -line 978 -pos 1 -win $_nTrace1 +srcSelect -toggle -signal "ch0_z_dsp_dout2" -line 978 -pos 1 -win $_nTrace1 +srcSelect -signal "ch0_z_dsp_dout2" -line 978 -pos 1 -win $_nTrace1 +srcSelect -signal "ch0_z_dsp_dout3" -line 979 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvSelectSignal -win $_nWave3 {( "G2" 33 )} +wvSelectAll -win $_nWave3 +wvCut -win $_nWave3 +wvSetPosition -win $_nWave3 {("G2" 0)} +wvSetPosition -win $_nWave3 {("G2" 0)} +wvSetPosition -win $_nWave3 {("G2" 0)} +wvSetPosition -win $_nWave3 {("G2" 0)} +srcDeselectAll -win $_nTrace1 +srcSelect -signal "ch0_z_dsp_dout0" -line 976 -pos 1 -win $_nTrace1 +srcAction -pos 975 12 9 -win $_nTrace1 -name "ch0_z_dsp_dout0" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -signal "dnxt" -line 277 -pos 1 -win $_nTrace1 +srcAction -pos 276 12 2 -win $_nTrace1 -name "dnxt" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -signal "sel" -line 58 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "xy_dsp_data0" -line 58 -pos 1 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +debReload +srcHBSelect "TB" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB" -delim "." +srcHBSelect "TB" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "z_wave" -line 1005 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +srcDeselectAll -win $_nTrace1 +debReload +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 1669962.590390 2649769.335073 +wvZoom -win $_nWave3 1877655.550017 1996709.673318 +wvZoom -win $_nWave3 1905954.002384 1916671.513262 +wvZoom -win $_nWave3 1906899.804895 1908658.332179 +wvZoom -win $_nWave3 1907155.590682 1907465.964899 +wvSelectSignal -win $_nWave3 {( "G2" 2 )} +wvBusWaveform -win $_nWave3 -analog +wvSetPosition -win $_nWave3 {("G2" 2)} +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +srcDeselectAll -win $_nTrace1 +wvSetCursor -win $_nWave3 1900558.796601 -snap {("G2" 0)} +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 7151874.048780 7788390.839122 +wvZoom -win $_nWave3 7644151.335856 7707097.342173 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 7611254.720137 7622531.964728 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +srcDeselectAll -win $_nTrace1 +debReload +srcHBSelect "TB.U_digital_top" -win $_nTrace1 +srcHBSelect "TB.U_digital_top.U_debug_top" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U_debug_top" -delim "." +srcHBSelect "TB.U_digital_top.U_debug_top" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "debug_update" -line 43 -pos 1 -win $_nTrace1 +srcSelect -signal "debug_ch_sel" -line 41 -pos 1 -win $_nTrace1 +srcSelect -signal "debug_data_sel" -line 40 -pos 1 -win $_nTrace1 +srcSelect -toggle -signal "debug_data_sel" -line 40 -pos 1 -win $_nTrace1 +srcSelect -signal "debug_data_sel" -line 40 -pos 1 -win $_nTrace1 +srcSelect -signal "debug_enable" -line 39 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "debug_update" -line 43 -pos 1 -win $_nTrace1 +srcAction -pos 42 4 8 -win $_nTrace1 -name "debug_update" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -signal "dnxt" -line 277 -pos 1 -win $_nTrace1 +srcAction -pos 276 12 2 -win $_nTrace1 -name "dnxt" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -signal "add_cnt" -line 88 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "debug_data_sel" -line 88 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "cnt_c" -line 88 -pos 1 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "debug_enable" -line 86 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "debug_data_sel" -line 86 -pos 1 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "mod_vld" -line 86 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "debug_data_sel" -line 86 -pos 2 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "dsp_vld" -line 86 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "end_cnt" -line 88 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "rst_n" -line 95 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "cnt_c" -line 95 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "cnt_n" -line 95 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "clk" -line 95 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvScrollDown -win $_nWave3 1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "cnt_n" -line 95 -pos 1 -win $_nTrace1 +srcAction -pos 94 10 3 -win $_nTrace1 -name "cnt_n" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -signal "end_cnt" -line 90 -pos 1 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "end_cnt" -line 90 -pos 1 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "end_cnt" -line 90 -pos 1 -win $_nTrace1 +srcAction -pos 89 13 4 -win $_nTrace1 -name "end_cnt" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -signal "add_cnt" -line 88 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "add_cnt" -line 88 -pos 1 -win $_nTrace1 +srcAction -pos 87 6 3 -win $_nTrace1 -name "add_cnt" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -signal "debug_enable" -line 86 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "debug_data_sel" -line 86 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "mod_vld" -line 86 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "debug_data_sel" -line 86 -pos 2 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "dsp_vld" -line 86 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvSelectSignal -win $_nWave3 {( "G2" 17 )} +wvZoom -win $_nWave3 1261386.221268 4887871.607415 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "add_cnt" -line 86 -pos 1 -win $_nTrace1 +srcSearchString "add_cnt" -win $_nTrace1 -next -case +srcSearchString "add_cnt" -win $_nTrace1 -next -case +srcSearchString "add_cnt" -win $_nTrace1 -next -case +srcSearchString "add_cnt" -win $_nTrace1 -next -case +srcSearchString "add_cnt" -win $_nTrace1 -next -case +srcSearchString "add_cnt" -win $_nTrace1 -next -case +wvSelectSignal -win $_nWave3 {( "G2" 9 )} +wvSelectAll -win $_nWave3 +wvCut -win $_nWave3 +wvSetPosition -win $_nWave3 {("G2" 0)} +wvSetPosition -win $_nWave3 {("G2" 0)} +wvSetPosition -win $_nWave3 {("G2" 0)} +wvSetPosition -win $_nWave3 {("G2" 0)} +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 14333.934333 1634068.513916 +wvZoom -win $_nWave3 718.285845 81166.300440 +wvZoom -win $_nWave3 1182.065973 10992.799460 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "debug_enable" -line 86 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "debug_data_sel" -line 86 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "mod_vld" -line 86 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "debug_data_sel" -line 86 -pos 2 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "dsp_vld" -line 86 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "add_cnt" -line 86 -pos 1 -win $_nTrace1 +srcAction -pos 85 2 3 -win $_nTrace1 -name "add_cnt" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -signal "add_cnt" -line 86 -pos 1 -win $_nTrace1 +srcAction -pos 85 2 3 -win $_nTrace1 -name "add_cnt" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -signal "add_cnt" -line 86 -pos 1 -win $_nTrace1 +srcAction -pos 85 2 3 -win $_nTrace1 -name "add_cnt" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -signal "add_cnt" -line 86 -pos 1 -win $_nTrace1 +srcAction -pos 85 2 3 -win $_nTrace1 -name "add_cnt" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -signal "add_cnt" -line 86 -pos 1 -win $_nTrace1 +srcAction -pos 85 2 3 -win $_nTrace1 -name "add_cnt" -ctrlKey off +srcSearchString "add_cnt" -win $_nTrace1 -next -case +srcSearchString "add_cnt" -win $_nTrace1 -next -case +srcSearchString "add_cnt" -win $_nTrace1 -next -case +srcSearchString "add_cnt" -win $_nTrace1 -next -case +srcSearchString "add_cnt" -win $_nTrace1 -next -case +srcSearchString "add_cnt" -win $_nTrace1 -next -case +srcDeselectAll -win $_nTrace1 +debReload +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvSelectSignal -win $_nWave3 {( "G2" 2 )} +wvSelectAll -win $_nWave3 +wvCut -win $_nWave3 +wvSetPosition -win $_nWave3 {("G2" 0)} +wvSetPosition -win $_nWave3 {("G2" 0)} +wvSetPosition -win $_nWave3 {("G2" 0)} +wvSetPosition -win $_nWave3 {("G2" 0)} +srcDeselectAll -win $_nTrace1 +debReload +srcDeselectAll -win $_nTrace1 +srcSelect -signal "debug_update" -line 44 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvZoom -win $_nWave3 1579003.302718 2458448.180182 +wvZoom -win $_nWave3 1733442.403151 1833281.821612 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "debug_update" -line 44 -pos 1 -win $_nTrace1 +srcAction -pos 43 4 10 -win $_nTrace1 -name "debug_update" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -signal "dnxt" -line 277 -pos 1 -win $_nTrace1 +srcAction -pos 276 12 1 -win $_nTrace1 -name "dnxt" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -signal "cnt_n" -line 91 -pos 1 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "cnt_c" -line 93 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "add_cnt" -line 92 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "debug_data_sel" -line 89 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +debReload +wvSelectSignal -win $_nWave3 {( "G2" 2 )} +srcDeselectAll -win $_nTrace1 +srcSelect -signal "rst_n" -line 96 -pos 1 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "cnt_c" -line 96 -pos 1 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "end_cnt" -line 91 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "add_cnt" -line 87 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "debug_data_sel" -line 89 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "cnt_c" -line 89 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "cnt_c" -line 89 -pos 2 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 71669.671663 1548064.907920 +wvZoom -win $_nWave3 77562.158193 222910.159280 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "cnt_c" -line 96 -pos 1 -win $_nTrace1 +srcAction -pos 95 13 2 -win $_nTrace1 -name "cnt_c" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -signal "qout_r" -line 275 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvZoom -win $_nWave3 128.911753 7605.793405 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "rst_n" -line 272 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvZoom -win $_nWave3 0.000000 354.778863 +wvZoom -win $_nWave3 0.471990 18.722255 +wvZoom -win $_nWave3 0.561015 2.721911 +wvZoom -win $_nWave3 0.565807 0.786208 +wvZoom -win $_nWave3 0.000586 0.038118 +wvZoom -win $_nWave3 0.000033 0.004560 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "rst_n" -line 272 -pos 1 -win $_nTrace1 +srcAction -pos 271 12 3 -win $_nTrace1 -name "rst_n" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -signal "sys_soft_rstn_r" -line 442 -pos 1 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "sys_soft_rstn_r" -line 442 -pos 1 -win $_nTrace1 +srcAction -pos 441 6 9 -win $_nTrace1 -name "sys_soft_rstn_r" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -signal "dnxt" -line 60 -pos 1 -win $_nTrace1 +srcAction -pos 59 12 2 -win $_nTrace1 -name "dnxt" -ctrlKey off +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "sys_soft_rstn_r" -line 411 -pos 1 -win $_nTrace1 +srcAction -pos 410 16 3 -win $_nTrace1 -name "sys_soft_rstn_r" -ctrlKey off +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "rst_n" -line 50 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 673.636433 6466.909753 +srcShowCalling -win $_nTrace1 +srcSelect -win $_nTrace1 -range {411 411 8 9 1 1} +srcHBSelect "TB.U_digital_top.U_system_regfile" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "ch1_soft_rstn_r" -line 425 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "ch0_soft_rstn_r" -line 418 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "sys_soft_rstn_r" -line 411 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "ch2_soft_rstn_r" -line 432 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcHBSelect "TB.U_digital_top.U_rst_gen_unit" -win $_nTrace1 +srcHBSelect "TB.U_digital_top.U_rst_gen_unit" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U_rst_gen_unit" -delim "." +srcHBSelect "TB.U_digital_top.U_rst_gen_unit" -win $_nTrace1 +srcSelect -signal "ch0_rstn_o" -line 25 -pos 1 -win $_nTrace1 +srcSelect -signal "ch1_rstn_o" -line 26 -pos 1 -win $_nTrace1 +srcSelect -signal "ch2_rstn_o" -line 27 -pos 1 -win $_nTrace1 +srcSelect -signal "ch3_rstn_o" -line 28 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "ch2_rstn_o" -line 27 -pos 1 -win $_nTrace1 +srcAction -pos 26 4 4 -win $_nTrace1 -name "ch2_rstn_o" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -signal "ch2_rstn_o" -line 27 -pos 1 -win $_nTrace1 +srcAction -pos 26 4 4 -win $_nTrace1 -name "ch2_rstn_o" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -signal "ch3_rstn_o" -line 28 -pos 1 -win $_nTrace1 +srcAction -pos 27 4 4 -win $_nTrace1 -name "ch3_rstn_o" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -signal "ch1_rstn_o" -line 26 -pos 1 -win $_nTrace1 +srcAction -pos 25 4 6 -win $_nTrace1 -name "ch1_rstn_o" -ctrlKey off +srcBackwardHistory -win $_nTrace1 +srcHBSelect "TB.U_digital_top.U_rst_gen_unit.ch1_rstn_sync" -win $_nTrace1 +srcHBSelect "TB.U_digital_top.U_rst_gen_unit" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -inst "ch3_rstn_sync" -line 55 -pos 1 -win $_nTrace1 +srcAction -pos 54 2 6 -win $_nTrace1 -name "ch3_rstn_sync" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -signal "rstn_s2" -line 27 -pos 1 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "sync_rstn" -line 27 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcShowCalling -win $_nTrace1 +srcSelect -win $_nTrace1 -range {55 55 3 4 1 1} +srcHBSelect "TB.U_digital_top.U_rst_gen_unit" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +debReload +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvSelectSignal -win $_nWave3 {( "G2" 5 )} +wvZoom -win $_nWave3 1562398.842253 2981458.341180 +wvZoom -win $_nWave3 1723498.279824 1802160.114576 +wvZoom -win $_nWave3 1744323.608138 1747114.271898 +wvZoom -win $_nWave3 1744822.338734 1745976.968130 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvSelectSignal -win $_nWave3 {( "G2" 6 )} +wvSelectSignal -win $_nWave3 {( "G2" 5 )} +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 9259721.578856 10134091.573144 +wvZoom -win $_nWave3 9711834.844194 9774649.894782 +wvZoom -win $_nWave3 9736236.611074 9739105.768595 +wvZoom -win $_nWave3 9737578.944194 9737760.890768 +wvZoomOut -win $_nWave3 +wvSelectSignal -win $_nWave3 {( "G2" 2 )} +wvSelectSignal -win $_nWave3 {( "G2" 2 )} +wvSetRadix -win $_nWave3 -format UDec +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 9736285.993912 9739962.686377 +wvZoom -win $_nWave3 9737502.318781 9737984.935618 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvSelectSignal -win $_nWave3 {( "G2" 17 )} +wvSelectAll -win $_nWave3 +wvCut -win $_nWave3 +wvSetPosition -win $_nWave3 {("G2" 0)} +wvSetPosition -win $_nWave3 {("G2" 0)} +wvSetPosition -win $_nWave3 {("G2" 0)} +wvSetPosition -win $_nWave3 {("G2" 0)} +srcDeselectAll -win $_nTrace1 +srcSelect -signal "sys_soft_resetn_i" -line 43 -pos 1 -win $_nTrace1 +srcHBSelect "TB.U_digital_top.U_debug_top" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U_debug_top" -delim "." +srcHBSelect "TB.U_digital_top.U_debug_top" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "debug_rwaddr" -line 116 -pos 2 -win $_nTrace1 +srcSelect -signal "debug_wrdata" -line 117 -pos 2 -win $_nTrace1 +srcSelect -signal "debug_bwen" -line 118 -pos 2 -win $_nTrace1 +srcSelect -toggle -signal "debug_bwen" -line 118 -pos 2 -win $_nTrace1 +srcSelect -win $_nTrace1 -range {118 119 8 8 6 6} +srcDeselectAll -win $_nTrace1 +srcSelect -signal "debug_cen" -line 120 -pos 2 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "debug_wrdata" -line 117 -pos 2 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "debug_rwaddr" -line 116 -pos 2 -win $_nTrace1 +srcSelect -signal "debug_wrdata" -line 117 -pos 2 -win $_nTrace1 +srcSelect -signal "debug_bwen" -line 118 -pos 2 -win $_nTrace1 +srcSelect -signal "debug_wren" -line 119 -pos 2 -win $_nTrace1 +srcSelect -signal "debug_cen" -line 120 -pos 2 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 9736742.009993 9737313.873492 +wvSelectSignal -win $_nWave3 {( "G2" 2 )} +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 1497762.687325 2702698.100225 +wvZoom -win $_nWave3 1717910.532165 1802336.161983 +wvZoom -win $_nWave3 1743593.894495 1748273.807456 +wvZoom -win $_nWave3 1745208.516350 1745588.305296 +wvSetCursor -win $_nWave3 1745423.252893 -snap {("G2" 2)} +wvSetCursor -win $_nWave3 1745431.673934 -snap {("G2" 2)} +wvSetCursor -win $_nWave3 1745456.431795 -snap {("G2" 2)} +wvZoom -win $_nWave3 1745418.873952 1745472.263352 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "ch0_mod_data_i" -line 92 -pos 2 -win $_nTrace1 +srcSelect -signal "ch0_mod_data_q" -line 93 -pos 2 -win $_nTrace1 +srcSelect -signal "ch0_mod_vld" -line 94 -pos 2 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvSelectSignal -win $_nWave3 {( "G2" 5 )} +wvSelectSignal -win $_nWave3 {( "G2" 4 )} +srcDeselectAll -win $_nTrace1 +srcSelect -signal "debug_rwaddr\[11:5\]" -line 141 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 1075045.074945 4486521.446102 +wvZoom -win $_nWave3 1466873.181432 2253555.094071 +wvZoom -win $_nWave3 1740729.190931 1806663.949906 +wvZoom -win $_nWave3 1760699.674469 1763506.653121 +srcDeselectAll -win $_nTrace1 +srcSelect -inst "U_debug_sampling" -line 85 -pos 1 -win $_nTrace1 +srcAction -pos 84 2 11 -win $_nTrace1 -name "U_debug_sampling" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -signal "mod_wrdata" -line 205 -pos 1 -win $_nTrace1 +srcAction -pos 204 20 1 -win $_nTrace1 -name "mod_wrdata" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -signal "mod_data_c" -line 123 -pos 1 -win $_nTrace1 +srcAction -pos 122 12 4 -win $_nTrace1 -name "mod_data_c" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -signal "dnxt" -line 277 -pos 1 -win $_nTrace1 +srcAction -pos 276 12 3 -win $_nTrace1 -name "dnxt" -ctrlKey off +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "add_cnt" -line 116 -pos 1 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "mem_cen" -line 204 -pos 1 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "dsp_cen" -line 204 -pos 1 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "mod_cen" -line 204 -pos 1 -win $_nTrace1 +srcAction -pos 203 14 2 -win $_nTrace1 -name "mod_cen" -ctrlKey off +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvZoom -win $_nWave3 1761272.273218 1761486.375359 +wvZoom -win $_nWave3 1761318.701575 1761391.429841 +wvZoom -win $_nWave3 1761327.151599 1761368.014886 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "clk" -line 96 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvSetCursor -win $_nWave3 1761327.831143 -snap {("G2" 10)} +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "mod_data" -line 105 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvSetCursor -win $_nWave3 1761295.901603 -snap {("G2" 12)} +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "mod_vld" -line 100 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvSetCursor -win $_nWave3 1761326.997568 -snap {("G2" 12)} +wvSetCursor -win $_nWave3 1761293.944514 -snap {("G2" 12)} +wvSetCursor -win $_nWave3 1761264.950608 -snap {("G2" 12)} +wvSetCursor -win $_nWave3 1761231.317676 -snap {("G2" 12)} +wvSetCursor -win $_nWave3 1761198.844500 -snap {("G2" 12)} +wvSetCursor -win $_nWave3 1761165.791446 -snap {("G2" 12)} +wvSetCursor -win $_nWave3 1761137.377418 -snap {("G2" 12)} +wvSetCursor -win $_nWave3 1761104.904242 -snap {("G2" 12)} +wvZoom -win $_nWave3 1761304.382321 1761398.322579 +wvZoom -win $_nWave3 1761325.253304 1761367.786787 +wvSetCursor -win $_nWave3 1761349.264445 -snap {("G2" 10)} +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 1760885.083627 1761230.934598 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvSetCursor -win $_nWave3 1761328.248318 -snap {("G2" 11)} +wvZoom -win $_nWave3 1761309.843832 1761396.958400 +wvZoom -win $_nWave3 1761325.064736 1761367.443752 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvSetCursor -win $_nWave3 1760909.346320 -snap {("G2" 13)} +srcDeselectAll -win $_nTrace1 +debReload +wvSelectSignal -win $_nWave3 {( "G2" 13 )} +wvSelectSignal -win $_nWave3 {( "G2" 14 )} +wvSelectSignal -win $_nWave3 {( "G2" 10 )} +wvCut -win $_nWave3 +wvSetPosition -win $_nWave3 {("G3" 0)} +wvSetPosition -win $_nWave3 {("G2" 13)} +wvSetPosition -win $_nWave3 {("G2" 13)} +wvSetPosition -win $_nWave3 {("G2" 13)} +wvSetPosition -win $_nWave3 {("G2" 13)} +srcDeselectAll -win $_nTrace1 +srcSelect -signal "mod_data_c" -line 123 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +debReload +srcDeselectAll -win $_nTrace1 +srcSelect -signal "mod_data_c" -line 123 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvSelectSignal -win $_nWave3 {( "G2" 5 )} +wvSelectSignal -win $_nWave3 {( "G2" 1 )} +wvSelectSignal -win $_nWave3 {( "G2" 1 2 3 4 5 6 7 8 9 )} +wvCut -win $_nWave3 +wvSetPosition -win $_nWave3 {("G2" 5)} +wvSetPosition -win $_nWave3 {("G2" 5)} +wvSetPosition -win $_nWave3 {("G2" 5)} +wvSetPosition -win $_nWave3 {("G2" 5)} +wvSelectSignal -win $_nWave3 {( "G2" 1 )} +wvSetPosition -win $_nWave3 {("G2" 1)} +wvSetPosition -win $_nWave3 {("G2" 2)} +wvSetPosition -win $_nWave3 {("G2" 3)} +wvSetPosition -win $_nWave3 {("G2" 4)} +wvSetPosition -win $_nWave3 {("G2" 5)} +wvMoveSelected -win $_nWave3 +wvSetPosition -win $_nWave3 {("G2" 5)} +wvSetPosition -win $_nWave3 {("G2" 5)} +wvSetPosition -win $_nWave3 {("G2" 5)} +wvSetPosition -win $_nWave3 {("G2" 5)} +wvZoom -win $_nWave3 1761310.471695 1761400.679800 +wvZoom -win $_nWave3 1761324.752978 1761376.197601 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 1730794.149053 1754715.921274 +wvZoom -win $_nWave3 1744701.662747 1746568.727896 +wvZoom -win $_nWave3 1745300.282747 1745728.341586 +wvZoom -win $_nWave3 1745346.600422 1745506.624192 +wvZoom -win $_nWave3 1745356.677306 1745450.633612 +wvSetCursor -win $_nWave3 1745391.884879 -snap {("G2" 4)} +wvZoom -win $_nWave3 1745387.593305 1745432.634000 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 1744234.062153 1745952.119994 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "cnt_c" -line 93 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "add_cnt" -line 116 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvSetCursor -win $_nWave3 1744912.142631 -snap {("G2" 7)} +wvZoom -win $_nWave3 1744905.285637 1745015.759423 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 1745331.283333 1745564.870477 +wvZoom -win $_nWave3 1745421.196256 1745462.423610 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvSetCursor -win $_nWave3 1745455.704739 -snap {("G2" 6)} +srcDeselectAll -win $_nTrace1 +srcSelect -signal "cnt_n" -line 121 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "mod_data_n" -line 119 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvZoom -win $_nWave3 1745385.280009 1745454.607781 +wvZoom -win $_nWave3 1745391.428813 1745426.722951 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "mod_addr" -line 121 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 1745359.491921 1745490.714120 +wvZoomOut -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "mem_addr" -line 203 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcHBSelect "TB.U_digital_top.U_debug_top" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U_debug_top" -delim "." +srcHBSelect "TB.U_digital_top.U_debug_top" -win $_nTrace1 +srcSelect -signal "debug_rwaddr" -line 79 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "dbg_sramb_addr" -line 128 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 3508556.888619 4225522.861511 +wvZoom -win $_nWave3 3597263.543358 3686606.088095 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "debug_rwaddr\[11:5\]" -line 141 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 2940506.695093 3251125.564601 +wvZoom -win $_nWave3 2948771.498715 2996845.106457 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 1664561.992238 2090253.255827 +wvZoom -win $_nWave3 1740072.637664 1766123.810336 +wvZoom -win $_nWave3 1744462.635719 1746784.713637 +wvSetCursor -win $_nWave3 1745390.437139 -snap {("G2" 5)} +wvSelectSignal -win $_nWave3 {( "G2" 14 )} +wvSelectSignal -win $_nWave3 {( "G2" 14 )} +wvExpandBus -win $_nWave3 {("G2" 14)} +wvSelectSignal -win $_nWave3 {( "G2" 15 )} +wvSelectSignal -win $_nWave3 {( "G2" 15 16 17 18 19 20 )} +wvCreateBusOpen -win $_nWave3 +wvSetPosition -win $_nWave3 {("G2" 21)} +wvSetPosition -win $_nWave3 {("G2" 21)} +wvSetPosition -win $_nWave3 {("G2" 22)} +wvSetPosition -win $_nWave3 {("G2" 21)} +wvSetPosition -win $_nWave3 {("G2" 22)} +wvSetPosition -win $_nWave3 {("G2" 22)} +wvSetPosition -win $_nWave3 {("G2" 22)} +wvSetPosition -win $_nWave3 {("G2" 22)} +wvSetPosition -win $_nWave3 {("G2" 21)} +wvSetPosition -win $_nWave3 {("G2" 21)} +wvCreateBus -win $_nWave3 "NewBus\[5:0\]" \ + "/TB/U_digital_top/U_debug_top/debug_rwaddr\[11\]" \ + "/TB/U_digital_top/U_debug_top/debug_rwaddr\[10\]" \ + "/TB/U_digital_top/U_debug_top/debug_rwaddr\[9\]" \ + "/TB/U_digital_top/U_debug_top/debug_rwaddr\[8\]" \ + "/TB/U_digital_top/U_debug_top/debug_rwaddr\[7\]" \ + "/TB/U_digital_top/U_debug_top/debug_rwaddr\[6\]" +wvSetPosition -win $_nWave3 {("G2" 22)} +wvSetPosition -win $_nWave3 {("G2" 22)} +wvSelectSignal -win $_nWave3 {( "G2" 14 )} +wvSetPosition -win $_nWave3 {("G2" 14)} +wvCollapseBus -win $_nWave3 {("G2" 14)} +wvSetPosition -win $_nWave3 {("G2" 14)} +wvSetPosition -win $_nWave3 {("G2" 14)} +wvSetPosition -win $_nWave3 {("G2" 14)} +wvSetPosition -win $_nWave3 {("G2" 14)} +wvSetPosition -win $_nWave3 {("G2" 15)} +wvSelectSignal -win $_nWave3 {( "G2" 15 )} +wvSetCursor -win $_nWave3 1745424.418767 -snap {("G2" 5)} +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 1752671.258392 1753593.911082 +wvSetCursor -win $_nWave3 1753136.471744 -snap {("G2" 5)} +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvSetCursor -win $_nWave3 1753625.211716 -snap {("G2" 5)} +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +srcDeselectAll -win $_nTrace1 +debReload +wvZoom -win $_nWave3 1753125.629040 1753219.735523 +wvZoom -win $_nWave3 1753163.772421 1753171.242515 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 1744374.965813 1755012.855716 +wvZoom -win $_nWave3 1744860.864997 1746290.257742 +wvZoom -win $_nWave3 1745354.655218 1745489.671030 +wvZoom -win $_nWave3 1745388.783383 1745443.208826 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 1745421.161090 1745460.453605 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvSetCursor -win $_nWave3 1745456.106162 -snap {("G2" 5)} +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvSelectSignal -win $_nWave3 {( "G2" 13 )} +wvSelectSignal -win $_nWave3 {( "G2" 14 )} +wvSelectSignal -win $_nWave3 {( "G2" 15 )} +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 1751882.061485 1757056.476166 +wvZoom -win $_nWave3 1752994.962203 1753332.274379 +wvZoomOut -win $_nWave3 +wvSetCursor -win $_nWave3 1753169.152903 -snap {("G2" 5)} +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvSetCursor -win $_nWave3 1744853.921602 -snap {("G2" 5)} +wvZoom -win $_nWave3 1741177.742421 1749678.906776 +wvZoom -win $_nWave3 1744992.899107 1745916.528937 +srcDeselectAll -win $_nTrace1 +debReload +wvSelectSignal -win $_nWave3 {( "G2" 5 )} +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 1742335.261789 1748941.160635 +wvZoom -win $_nWave3 1745115.305250 1745704.123728 +wvZoom -win $_nWave3 1745386.866765 1745491.052385 +wvSelectSignal -win $_nWave3 {( "G2" 11 )} +wvSelectAll -win $_nWave3 +wvCut -win $_nWave3 +wvSetPosition -win $_nWave3 {("G2" 0)} +wvSetPosition -win $_nWave3 {("G2" 0)} +wvSetPosition -win $_nWave3 {("G2" 0)} +wvSetPosition -win $_nWave3 {("G2" 0)} +srcHBSelect "TB.U_digital_top.U_debug_top.U_debug_sampling" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U_debug_top.U_debug_sampling" -delim \ + "." +srcHBSelect "TB.U_digital_top.U_debug_top.U_debug_sampling" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "mod_cen" -line 124 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "mod_wrdata" -line 119 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "mod_data_c" -line 119 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvSelectSignal -win $_nWave3 {( "G2" 2 )} +wvCut -win $_nWave3 +wvSetPosition -win $_nWave3 {("G3" 0)} +wvSetPosition -win $_nWave3 {("G2" 2)} +wvSetPosition -win $_nWave3 {("G2" 2)} +wvSetPosition -win $_nWave3 {("G2" 2)} +wvSetPosition -win $_nWave3 {("G2" 2)} +wvZoom -win $_nWave3 1745421.980322 1745460.559033 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "mod_cen_w" -line 123 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvSelectSignal -win $_nWave3 {( "G2" 3 )} +wvCut -win $_nWave3 +wvSetPosition -win $_nWave3 {("G3" 0)} +wvSetPosition -win $_nWave3 {("G2" 2)} +wvSetPosition -win $_nWave3 {("G2" 2)} +wvSetPosition -win $_nWave3 {("G2" 2)} +wvSetPosition -win $_nWave3 {("G2" 2)} +srcDeselectAll -win $_nTrace1 +srcSelect -signal "mod_addr" -line 127 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvSelectSignal -win $_nWave3 {( "G2" 3 )} +wvCut -win $_nWave3 +wvSetPosition -win $_nWave3 {("G3" 0)} +wvSetPosition -win $_nWave3 {("G2" 2)} +wvSetPosition -win $_nWave3 {("G2" 2)} +wvSetPosition -win $_nWave3 {("G2" 2)} +wvSetPosition -win $_nWave3 {("G2" 2)} +wvSetCursor -win $_nWave3 1745263.756283 -snap {("G3" 0)} +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 78870.220545 2028091.385455 +wvZoom -win $_nWave3 94429.413880 231004.555368 +wvZoom -win $_nWave3 95277.330501 108541.169075 +wvSetCursor -win $_nWave3 3029.213688 -snap {("G2" 1)} +srcHBSelect "TB.U_digital_top.U_debug_top" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U_debug_top" -delim "." +srcHBSelect "TB.U_digital_top.U_debug_top" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "debug_rwaddr\[12:6\]" -line 141 -pos 1 -win $_nTrace1 +srcSelect -signal "debug_wren" -line 143 -pos 1 -win $_nTrace1 +srcSelect -signal "debug_wrdata" -line 142 -pos 1 -win $_nTrace1 +srcSelect -signal "debug_cen" -line 144 -pos 1 -win $_nTrace1 +srcSelect -signal "debug_bwen" -line 145 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +debReload +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +srcSelect -signal "debug_rwaddr\[12:6\]" -line 141 -pos 1 -win $_nTrace1 +srcSelect -signal "debug_wrdata" -line 142 -pos 1 -win $_nTrace1 +srcSelect -signal "debug_wren" -line 143 -pos 1 -win $_nTrace1 +srcSelect -signal "debug_cen" -line 144 -pos 1 -win $_nTrace1 +srcSelect -signal "debug_bwen" -line 145 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvZoom -win $_nWave3 1722954.024798 1880759.972115 +wvZoom -win $_nWave3 1740869.023695 1755354.979835 +wvZoom -win $_nWave3 1744325.096601 1746522.079749 +srcDeselectAll -win $_nTrace1 +srcSelect -inst "U_dbg_sram" -line 139 -pos 1 -win $_nTrace1 +srcAction -pos 138 3 6 -win $_nTrace1 -name "U_dbg_sram" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -inst "U_tsmc_dpram" -line 70 -pos 1 -win $_nTrace1 +srcAction -pos 69 3 5 -win $_nTrace1 -name "U_tsmc_dpram" -ctrlKey off +srcDeselectAll -win $_nTrace1 +debReload +wvSetCursor -win $_nWave3 1745457.200556 -snap {("G2" 3)} +srcHBSelect \ + "TB.U_digital_top.U_debug_top.U_dbg_sram.U_tsmc_dpram.spram_512X128_generation" \ + -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +debReload +srcDeselectAll -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcHBSelect \ + "TB.U_digital_top.U_debug_top.U_dbg_sram.U_tsmc_dpram.spram_512X128_generation" \ + -win $_nTrace1 +srcSetScope -win $_nTrace1 \ + "TB.U_digital_top.U_debug_top.U_dbg_sram.U_tsmc_dpram.spram_512X128_generation" \ + -delim "." +srcHBSelect \ + "TB.U_digital_top.U_debug_top.U_dbg_sram.U_tsmc_dpram.spram_512X128_generation" \ + -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "BWEBA\[127:0\]" -line 169 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "PortAWriteEnable" -line 168 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "PortAChipEnable" -line 167 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "PortADataIn\[127:0\]" -line 171 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvZoom -win $_nWave3 1745423.101039 1745532.219493 +wvZoomOut -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "PortADataOut\[127:0\]" -line 172 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "PortBChipEnable" -line 173 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "PortBWriteEnable" -line 174 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "BWEBB\[127:0\]" -line 175 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "PortBAddr\[ADDRWIDTH-1:LSB\]" -line 176 -pos 1 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "BWEBB\[127:0\]" -line 175 -pos 1 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "BWEBB\[127:0\]" -line 175 -pos 1 -win $_nTrace1 +srcAction -pos 174 7 3 -win $_nTrace1 -name "BWEBB\[127:0\]" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -signal "PortBByteWriteEnable\[i\]" -line 163 -pos 1 -win $_nTrace1 +srcAction -pos 162 11 7 -win $_nTrace1 -name "PortBByteWriteEnable\[i\]" -ctrlKey \ + off +srcDeselectAll -win $_nTrace1 +srcSelect -win $_nTrace1 -signal "dbg_sram_out.wben" -line 130 -pos 1 +srcDeselectAll -win $_nTrace1 +srcSelect -win $_nTrace1 -signal "dbg_sram_out.wben" -line 130 -pos 1 +srcAction -pos 129 13 14 -win $_nTrace1 -name "dbg_sram_out.wben" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -win $_nTrace1 -signal "port_in.wben" -line 86 -pos 1 +srcAction -pos 85 17 9 -win $_nTrace1 -name "port_in.wben" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -win $_nTrace1 -signal "mst.din" -line 69 -pos 1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "cs_slv\[i\]" -line 69 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -win $_nTrace1 -signal "slv\[i\].wben" -line 69 -pos 1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcBackwardHistory -win $_nTrace1 +srcHBSelect "TB.U_digital_top.U_spi_bus_decoder.MAIN\[25\]" -win $_nTrace1 +srcHBSelect "TB.U_digital_top.U_debug_top.U_sram_dmux_w.MAIN\[0\]" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "data_sel" -line 86 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -win $_nTrace1 -signal \ + "port_out.wben\[DATA_WIDTH_I/8*i +: DATA_WIDTH_I/8\]" -line 86 -pos \ + 1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "data_sel" -line 86 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -win $_nTrace1 -signal "port_in.wben" -line 86 -pos 1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "data_sel" -line 86 -pos 1 -win $_nTrace1 +srcAction -pos 85 12 4 -win $_nTrace1 -name "data_sel" -ctrlKey off +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -win $_nTrace1 -signal "port_in.addr\[DH-1:DL\]" -line 70 -pos 1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "data_sel" -line 70 -pos 1 -win $_nTrace1 +srcAction -pos 69 3 5 -win $_nTrace1 -name "data_sel" -ctrlKey off +srcSearchString "data_sel" -win $_nTrace1 -next -case +srcSearchString "data_sel" -win $_nTrace1 -next -case +srcSearchString "data_sel" -win $_nTrace1 -next -case +srcSearchString "data_sel" -win $_nTrace1 -next -case +srcSearchString "data_sel" -win $_nTrace1 -next -case +srcSearchString "data_sel" -win $_nTrace1 -next -case +srcSearchString "data_sel" -win $_nTrace1 -next -case +srcSearchString "data_sel" -win $_nTrace1 -next -case +srcSearchString "data_sel" -win $_nTrace1 -next -case +srcSearchString "data_sel" -win $_nTrace1 -next -case +srcSearchString "data_sel" -win $_nTrace1 -next -case +srcSearchString "data_sel" -win $_nTrace1 -next -case +wvSelectSignal -win $_nWave3 {( "G2" 10 )} +wvSelectAll -win $_nWave3 +wvCut -win $_nWave3 +wvSetPosition -win $_nWave3 {("G2" 0)} +wvSetPosition -win $_nWave3 {("G2" 0)} +wvSetPosition -win $_nWave3 {("G2" 0)} +wvSetPosition -win $_nWave3 {("G2" 0)} +srcHBSelect "TB.U_digital_top.U_debug_top.U_debug_sampling" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U_debug_top.U_debug_sampling" -delim \ + "." +srcHBSelect "TB.U_digital_top.U_debug_top.U_debug_sampling" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "dsp_data" -line 137 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcSelect -win $_nTrace1 -range {137 139 9 16 7 6} +srcDeselectAll -win $_nTrace1 +srcSelect -signal "ch0_dsp_data_i\[10\]" -line 142 -pos 1 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "ch0_dsp_data_i\[0 \]" -line 152 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "ch0_dsp_data_i\[0 \]" -line 152 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcHBSelect "TB.U_digital_top.U_debug_top" -win $_nTrace1 +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top" -win $_nTrace1 +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.U_awg_ctrl" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U0_channel_top.U_awg_top.U_awg_ctrl" \ + -delim "." +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.U_awg_ctrl" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "enve_vld_o" -line 100 -pos 1 -win $_nTrace1 +srcSelect -signal "enve_qdata_o" -line 99 -pos 1 -win $_nTrace1 +srcSelect -signal "enve_idata_o" -line 98 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 1745341.395270 1753319.091373 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvSetCursor -win $_nWave3 1745721.706725 -snap {("G2" 2)} +wvSetCursor -win $_nWave3 1752825.570927 -snap {("G2" 2)} +wvZoom -win $_nWave3 1744419.803325 1758967.158703 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "enve_vld_r\[0\]" -line 217 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "wave_hold_r2" -line 218 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvZoom -win $_nWave3 1752441.815037 1753886.873842 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 1752643.995104 1754023.049006 +wvZoomOut -win $_nWave3 +srcHBSelect "TB.U_digital_top" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top" -delim "." +srcHBSelect "TB.U_digital_top" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -win $_nTrace1 -signal "slv\[25\].slave" -line 1201 -pos 1 +srcDeselectAll -win $_nTrace1 +debReload +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 2988270.802377 3183376.337242 +wvSelectSignal -win $_nWave3 {( "G2" 4 )} +wvSelectAll -win $_nWave3 +wvCut -win $_nWave3 +wvSetPosition -win $_nWave3 {("G2" 0)} +wvSetPosition -win $_nWave3 {("G2" 0)} +wvSetPosition -win $_nWave3 {("G2" 0)} +wvSetPosition -win $_nWave3 {("G2" 0)} +srcHBSelect "TB.U_digital_top.U_debug_top" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U_debug_top" -delim "." +srcHBSelect "TB.U_digital_top.U_debug_top" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -word -line 70 -pos 6 -win $_nTrace1 +wvDrop -win $_nWave3 +wvDrop -win $_nWave3 +wvDrop -win $_nWave3 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "dbg_sramb_addr" -line 147 -pos 1 -win $_nTrace1 +srcSelect -signal "dbg_sramb_din" -line 148 -pos 1 -win $_nTrace1 +srcSelect -signal "dbg_sramb_wren" -line 149 -pos 1 -win $_nTrace1 +srcSelect -signal "dbg_sramb_cen" -line 150 -pos 1 -win $_nTrace1 +srcSelect -signal "dbg_sramb_wben" -line 151 -pos 1 -win $_nTrace1 +srcSelect -signal "dbg_sramb_dout" -line 152 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvZoom -win $_nWave3 2989049.494089 2994413.814782 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 1701435.031982 1842025.785047 +wvZoom -win $_nWave3 1740837.850579 1752683.634651 +wvZoom -win $_nWave3 1744320.668690 1745187.433378 +wvSelectSignal -win $_nWave3 {( "G2" 2 )} +wvSelectSignal -win $_nWave3 {( "G2" 6 )} +wvSetCursor -win $_nWave3 1744688.899541 -snap {("G2" 6)} +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 1794199.997592 1808861.581745 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 1924180.955288 1968081.184204 +wvZoom -win $_nWave3 1953752.772460 1958425.080637 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 2900760.231592 3171899.541073 +wvZoom -win $_nWave3 3051780.618602 3080517.778232 +srcDeselectAll -win $_nTrace1 +debReload +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 1827507.985477 1977775.751885 +wvZoom -win $_nWave3 1894145.575901 1904674.315188 +wvZoom -win $_nWave3 1896246.654693 1897385.906306 +wvZoomOut -win $_nWave3 +srcHBSelect "TB.U_digital_top.U_spi_slave" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U_spi_slave" -delim "." +srcHBSelect "TB.U_digital_top.U_spi_slave" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "sys_rddata" -line 56 -pos 1 -win $_nTrace1 +srcSelect -signal "sys_rden" -line 55 -pos 1 -win $_nTrace1 +srcSelect -signal "sys_rwaddr" -line 54 -pos 1 -win $_nTrace1 +srcSelect -signal "sys_wren" -line 53 -pos 1 -win $_nTrace1 +srcSelect -signal "sys_wrdata" -line 52 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvSetCursor -win $_nWave3 1896426.762542 -snap {("G2" 8)} +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 1912134.288876 1913152.794974 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvSetCursor -win $_nWave3 1268727.848115 -snap {("G3" 0)} +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 1864400.071840 1975976.137916 +wvSelectSignal -win $_nWave3 {( "G2" 9 )} +wvZoom -win $_nWave3 1910168.524665 1916798.765398 +wvZoomOut -win $_nWave3 +wvSelectSignal -win $_nWave3 {( "G2" 9 )} +wvSetPosition -win $_nWave3 {("G2" 9)} +wvExpandBus -win $_nWave3 {("G2" 9)} +wvSetPosition -win $_nWave3 {("G2" 36)} +wvScrollUp -win $_nWave3 4 +wvScrollUp -win $_nWave3 4 +wvSelectSignal -win $_nWave3 {( "G2" 10 )} +wvSelectSignal -win $_nWave3 {( "G2" 11 )} +wvSelectSignal -win $_nWave3 {( "G2" 9 )} +wvSetPosition -win $_nWave3 {("G2" 9)} +wvCollapseBus -win $_nWave3 {("G2" 9)} +wvSetPosition -win $_nWave3 {("G2" 9)} +wvSetPosition -win $_nWave3 {("G2" 9)} +wvSetPosition -win $_nWave3 {("G2" 9)} +wvSetPosition -win $_nWave3 {("G2" 9)} +wvSetPosition -win $_nWave3 {("G2" 11)} +wvSelectSignal -win $_nWave3 {( "G2" 7 )} +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 2000085.746598 2022290.437516 +wvZoom -win $_nWave3 2020646.010295 2021896.562732 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 1927272.554431 1955666.472302 +wvZoom -win $_nWave3 1944988.848197 1948753.718017 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvSelectSignal -win $_nWave3 {( "G2" 10 )} +wvSelectAll -win $_nWave3 +wvCut -win $_nWave3 +wvSetPosition -win $_nWave3 {("G2" 0)} +wvSetPosition -win $_nWave3 {("G2" 0)} +wvSetPosition -win $_nWave3 {("G2" 0)} +wvSetPosition -win $_nWave3 {("G2" 0)} +verdiWindowResize -win $_Verdi_1 -1547 "127" "1920" "993" +srcDeselectAll -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "sys_rddata" -line 56 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +debReload +srcDeselectAll -win $_nTrace1 +srcSelect -signal "sys_rwaddr" -line 54 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 677130.973942 1032911.655166 +wvZoom -win $_nWave3 786468.451587 815025.570567 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 1932405.554874 2194937.267228 +wvZoom -win $_nWave3 2077933.111611 2099587.612053 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "sys_rden" -line 55 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "pll_rden" -line 49 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 238143.520497 338565.486971 +wvZoom -win $_nWave3 248831.445975 256001.262650 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 1801856.998457 2014177.727574 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "sys_wren" -line 53 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "pll_wren" -line 47 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvZoom -win $_nWave3 220928.326244 380168.873082 +wvZoom -win $_nWave3 246138.470466 255742.334932 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 497806.033809 737384.153827 +wvZoom -win $_nWave3 539665.802894 555920.992412 +wvZoomOut -win $_nWave3 +srcDeselectAll -win $_nTrace1 +debReload +srcDeselectAll -win $_nTrace1 +debReload +srcHBSelect "TB.U_digital_top.U_debug_top" -win $_nTrace1 +srcHBSelect "TB.U_digital_top.U_debug_top.U_debug_sampling" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U_debug_top.U_debug_sampling" -delim \ + "." +srcHBSelect "TB.U_digital_top.U_debug_top.U_debug_sampling" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "debug_data_sel" -line 40 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "mem_cen" -line 210 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "dsp_cen" -line 210 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "mem_addr" -line 209 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "mem_wrdata" -line 211 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "dsp_wrdata" -line 211 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "dsp_wrdata" -line 211 -pos 1 -win $_nTrace1 +srcAction -pos 210 16 5 -win $_nTrace1 -name "dsp_wrdata" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -signal "debug_ch_sel\[0\]" -line 137 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "debug_ch_sel\[1\]" -line 153 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "debug_ch_sel\[3\]" -line 185 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "debug_ch_sel\[2\]" -line 169 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "ch0_dsp_data_i\[13\]" -line 139 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvUnknownSaveResult -win $_nWave3 -clear +srcHBSelect "TB.U_digital_top.U_debug_top" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U_debug_top" -delim "." +srcHBSelect "TB.U_digital_top.U_debug_top" -win $_nTrace1 +srcHBSelect "TB.U_digital_top.U0_channel_top" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U0_channel_top" -delim "." +srcHBSelect "TB.U_digital_top.U0_channel_top" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "xy_dsp_dout0" -line 122 -pos 1 -win $_nTrace1 +srcSelect -win $_nTrace1 -range {122 138 12 5 7 9} +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +srcDeselectAll -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "xy_dsp_dout_vld" -line 138 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +srcHBSelect "TB.U_digital_top.U_debug_top.U_debug_sampling" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U_debug_top.U_debug_sampling" -delim \ + "." +srcHBSelect "TB.U_digital_top.U_debug_top.U_debug_sampling" -win $_nTrace1 +srcHBSelect "TB.U_digital_top.U_debug_top" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U_debug_top" -delim "." +srcHBSelect "TB.U_digital_top.U_debug_top" -win $_nTrace1 +srcHBSelect "TB.U_digital_top" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top" -delim "." +srcHBSelect "TB.U_digital_top" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "ch0_dsp_data_q" -line 1190 -pos 2 -win $_nTrace1 +srcSearchString "ch0_dsp_data_q" -win $_nTrace1 -next -case +srcSearchString "ch0_dsp_data_q" -win $_nTrace1 -next -case +srcSearchString "ch0_dsp_data_q" -win $_nTrace1 -next -case +srcSearchString "ch0_dsp_data_q" -win $_nTrace1 -next -case +srcDeselectAll -win $_nTrace1 +debReload +wvZoom -win $_nWave3 1731561.621925 1867848.576426 +wvZoom -win $_nWave3 1802152.824965 1803965.955180 +wvZoom -win $_nWave3 1802779.983087 1802891.745881 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvScrollDown -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +srcHBSelect "TB.U_digital_top.U_debug_top" -win $_nTrace1 +srcHBSelect "TB.U_digital_top.U_debug_top.U_debug_sampling" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U_debug_top.U_debug_sampling" -delim \ + "." +srcHBSelect "TB.U_digital_top.U_debug_top.U_debug_sampling" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "end_cnt" -line 89 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "cnt_c" -line 89 -pos 2 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "add_cnt" -line 87 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +verdiDockWidgetSetCurTab -dock widgetDock_MTB_SOURCE_TAB_1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "debug_enable" -line 87 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "dsp_vld" -line 87 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +debReload +srcHBSelect "TB.U_digital_top.U_debug_top" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U_debug_top" -delim "." +srcHBSelect "TB.U_digital_top.U_debug_top" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "ch3_mod_data_q" -line 97 -pos 2 -win $_nTrace1 +srcAction -pos 96 7 4 -win $_nTrace1 -name "ch3_mod_data_q" -ctrlKey off +srcShowCalling -win $_nTrace1 +srcSelect -win $_nTrace1 -range {578 578 3 4 1 1} +srcHBSelect "TB" -win $_nTrace1 +srcBackwardHistory -win $_nTrace1 +srcHBSelect "TB" -win $_nTrace1 +srcHBSelect "TB.U_digital_top" -win $_nTrace1 +srcBackwardHistory -win $_nTrace1 +srcHBSelect "TB.U_digital_top.U_debug_top" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -inst "U_debug_sampling" -line 81 -pos 1 -win $_nTrace1 +srcAction -pos 80 2 5 -win $_nTrace1 -name "U_debug_sampling" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -signal "ch3_mod_data_q" -line 56 -pos 1 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "ch3_mod_data_q" -line 56 -pos 1 -win $_nTrace1 +srcAction -pos 55 11 8 -win $_nTrace1 -name "ch3_mod_data_q" -ctrlKey off +srcDeselectAll -win $_nTrace1 +debReload +wvSelectSignal -win $_nWave3 {( "G2" 29 )} +wvZoom -win $_nWave3 1760253.612346 1796118.600373 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +srcHBSelect "TB.U_digital_top.U0_channel_top" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U0_channel_top" -delim "." +srcHBSelect "TB.U_digital_top.U0_channel_top" -win $_nTrace1 +srcHBSelect "TB.U_digital_top.U_debug_top" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U_debug_top" -delim "." +srcHBSelect "TB.U_digital_top.U_debug_top" -win $_nTrace1 +srcHBSelect "TB.U_digital_top.U_debug_top.U_dbg_sram" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U_debug_top.U_dbg_sram" -delim "." +srcHBSelect "TB.U_digital_top.U_debug_top.U_dbg_sram" -win $_nTrace1 +srcHBSelect "TB.U_digital_top.U_debug_top.U_debug_sampling" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U_debug_top.U_debug_sampling" -delim \ + "." +srcHBSelect "TB.U_digital_top.U_debug_top.U_debug_sampling" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +debReload +srcHBSelect "TB.U_digital_top.U_debug_top.U_dbg_sram" -win $_nTrace1 +srcHBSelect \ + "TB.U_digital_top.U_debug_top.U_dbg_sram.U_tsmc_dpram.spram_512X128_generation" \ + -win $_nTrace1 +srcHBSelect \ + "TB.U_digital_top.U_debug_top.U_dbg_sram.U_tsmc_dpram.spram_512X128_generation" \ + -win $_nTrace1 +srcSetScope -win $_nTrace1 \ + "TB.U_digital_top.U_debug_top.U_dbg_sram.U_tsmc_dpram.spram_512X128_generation" \ + -delim "." +srcHBSelect \ + "TB.U_digital_top.U_debug_top.U_dbg_sram.U_tsmc_dpram.spram_512X128_generation" \ + -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +debReload +srcHBSelect "TB.U_digital_top.U_debug_top.U_debug_sampling" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U_debug_top.U_debug_sampling" -delim \ + "." +srcHBSelect "TB.U_digital_top.U_debug_top.U_debug_sampling" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "cnt_n" -line 87 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvZoom -win $_nWave3 1744277.390407 1753438.469389 +wvZoom -win $_nWave3 1746999.307444 1747474.627284 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 1753860.670545 1756127.029271 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "end_cnt" -line 85 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "debug_data_sel" -line 85 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "debug_data_sel" -line 85 -pos 2 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvZoom -win $_nWave3 1773165.008035 1794684.000851 +wvZoom -win $_nWave3 1786419.944186 1786992.511623 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 1779105.173016 1779454.553411 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvSelectSignal -win $_nWave3 {( "G2" 30 )} +wvSelectSignal -win $_nWave3 {( "G3" 3 )} +wvSelectAll -win $_nWave3 +wvCut -win $_nWave3 +wvSetPosition -win $_nWave3 {("G3" 0)} +wvSetPosition -win $_nWave3 {("G3" 0)} +wvSetPosition -win $_nWave3 {("G3" 0)} +wvSetPosition -win $_nWave3 {("G3" 0)} +srcHBSelect \ + "TB.U_digital_top.U_debug_top.U_dbg_sram.U_tsmc_dpram.spram_512X128_generation" \ + -win $_nTrace1 +srcSetScope -win $_nTrace1 \ + "TB.U_digital_top.U_debug_top.U_dbg_sram.U_tsmc_dpram.spram_512X128_generation" \ + -delim "." +srcHBSelect \ + "TB.U_digital_top.U_debug_top.U_dbg_sram.U_tsmc_dpram.spram_512X128_generation" \ + -win $_nTrace1 +srcSelect -signal "PortAChipEnable" -line 167 -pos 1 -win $_nTrace1 +srcSelect -signal "PortClk" -line 166 -pos 1 -win $_nTrace1 +srcSelect -signal "PortAWriteEnable" -line 168 -pos 1 -win $_nTrace1 +srcSelect -signal "BWEBA\[127:0\]" -line 169 -pos 1 -win $_nTrace1 +srcSelect -signal "PortAAddr\[ADDRWIDTH-1:LSB\]" -line 170 -pos 1 -win $_nTrace1 +srcSelect -signal "PortADataIn\[127:0\]" -line 171 -pos 1 -win $_nTrace1 +srcSelect -signal "PortADataOut\[127:0\]" -line 172 -pos 1 -win $_nTrace1 +srcSelect -signal "PortBChipEnable" -line 173 -pos 1 -win $_nTrace1 +srcSelect -signal "PortBWriteEnable" -line 174 -pos 1 -win $_nTrace1 +srcSelect -signal "BWEBB\[127:0\]" -line 175 -pos 1 -win $_nTrace1 +srcSelect -signal "ADDRWIDTH" -win $_nTrace1 +srcSelect -signal "PortBDataIn\[127:0\]" -line 177 -pos 1 -win $_nTrace1 +srcSelect -signal "PortBDataOut\[127:0\]" -line 178 -pos 1 -win $_nTrace1 +srcSelect -toggle -signal "ADDRWIDTH" -win $_nTrace1 +srcSelect -toggle -signal "PortBDataIn\[127:0\]" -line 177 -pos 1 -win $_nTrace1 +srcSelect -toggle -signal "PortBDataOut\[127:0\]" -line 178 -pos 1 -win $_nTrace1 +srcSelect -signal "PortBAddr\[ADDRWIDTH-1:LSB\]" -line 176 -pos 1 -win $_nTrace1 +srcSelect -signal "PortBDataIn\[127:0\]" -line 177 -pos 1 -win $_nTrace1 +srcSelect -signal "PortBDataOut\[127:0\]" -line 178 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvSetCursor -win $_nWave3 1853371.437621 -snap {("G4" 0)} +wvZoom -win $_nWave3 1843217.560186 1872409.957812 +wvZoomOut -win $_nWave3 +wvSelectSignal -win $_nWave3 {( "G3" 9 )} +wvSelectSignal -win $_nWave3 {( "G3" 8 )} +wvZoom -win $_nWave3 1844673.943659 1846382.766935 +wvSetCursor -win $_nWave3 1845298.365113 -snap {("G3" 10)} +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 1823375.991273 1975443.540506 +wvZoom -win $_nWave3 1843269.528755 1851226.943748 +wvSelectSignal -win $_nWave3 {( "G3" 12 )} +wvSetCursor -win $_nWave3 1845298.581358 -snap {("G3" 13)} +wvSelectSignal -win $_nWave3 {( "G3" 9 )} +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvSelectSignal -win $_nWave3 {( "G3" 13 )} +wvExpandBus -win $_nWave3 {("G3" 13)} +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 48 +wvSelectSignal -win $_nWave3 {( "G3" 14 )} +wvSelectSignal -win $_nWave3 {( "G3" 13 )} +wvSetPosition -win $_nWave3 {("G3" 13)} +wvCollapseBus -win $_nWave3 {("G3" 13)} +wvSetPosition -win $_nWave3 {("G3" 13)} +wvSetPosition -win $_nWave3 {("G3" 13)} +wvSetPosition -win $_nWave3 {("G3" 13)} +wvSetPosition -win $_nWave3 {("G3" 13)} +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 1731842.781735 1752168.595642 +wvZoom -win $_nWave3 1746066.344637 1747409.380677 +wvZoom -win $_nWave3 1746501.119053 1746608.323703 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 1746500.714955 1747002.746490 +wvSelectSignal -win $_nWave3 {( "G3" 5 )} +wvZoomOut -win $_nWave3 +srcHBSelect "TB.U_digital_top.U_debug_top.U_debug_sampling" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U_debug_top.U_debug_sampling" -delim \ + "." +srcHBSelect "TB.U_digital_top.U_debug_top.U_debug_sampling" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "debug_rwaddr" -line 68 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +debReload +srcDeselectAll -win $_nTrace1 +srcSelect -signal "mem_addr" -line 205 -pos 1 -win $_nTrace1 +srcSelect -signal "mem_cen" -line 206 -pos 1 -win $_nTrace1 +srcSelect -signal "mem_wrdata" -line 207 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "dsp_addr" -line 205 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "dsp_data" -line 200 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "add_cnt" -line 199 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 0 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "ch3_dsp_vld" -line 66 -pos 1 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "ch0_dsp_vld" -line 60 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvZoom -win $_nWave3 1746465.873298 1746693.846820 +wvZoomOut -win $_nWave3 +srcHBSelect \ + "TB.U_digital_top.U_debug_top.U_dbg_sram.U_tsmc_dpram.spram_512X128_generation" \ + -win $_nTrace1 +srcSetScope -win $_nTrace1 \ + "TB.U_digital_top.U_debug_top.U_dbg_sram.U_tsmc_dpram.spram_512X128_generation" \ + -delim "." +srcHBSelect \ + "TB.U_digital_top.U_debug_top.U_dbg_sram.U_tsmc_dpram.spram_512X128_generation" \ + -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "PortAAddr\[ADDRWIDTH-1:LSB\]" -line 170 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvSetCursor -win $_nWave3 1746512.024035 -snap {("G3" 20)} +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvZoom -win $_nWave3 2101688.298359 2196371.866749 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "PortBChipEnable" -line 173 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcSelect -signal "PortBAddr\[ADDRWIDTH-1:LSB\]" -line 176 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcSelect -signal "PortBDataIn\[127:0\]" -line 177 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvZoom -win $_nWave3 1836301.383055 1900123.566626 +wvZoom -win $_nWave3 1844282.693815 1848046.929033 +wvSelectSignal -win $_nWave3 {( "G3" 27 )} +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 1853502.581215 1938143.952958 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 2102115.497285 2159769.221009 +wvSelectSignal -win $_nWave3 {( "G3" 25 )} +wvSelectSignal -win $_nWave3 {( "G3" 24 )} +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 1743345.706530 1785889.296896 +wvZoom -win $_nWave3 1745854.929375 1749024.474024 +wvZoom -win $_nWave3 1746349.687564 1747507.871506 +wvZoom -win $_nWave3 1746671.205589 1746747.733042 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 2166504.802508 2334422.935785 +wvZoom -win $_nWave3 2254075.412146 2260628.314908 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 2896456.433029 3103038.764062 +wvZoom -win $_nWave3 3048805.176491 3066577.669715 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 1932405.554874 2042869.717996 +wvZoom -win $_nWave3 1976836.151747 1982469.579135 +wvZoom -win $_nWave3 1978332.569931 1979226.923370 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 1708704.838550 1817547.057153 +wvZoom -win $_nWave3 1744760.331808 1750793.714214 +wvZoom -win $_nWave3 1746403.124178 1747074.689138 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +srcHBSelect "TB.U_digital_top.U_debug_top.U_debug_sampling" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U_debug_top.U_debug_sampling" -delim \ + "." +srcHBSelect "TB.U_digital_top.U_debug_top.U_debug_sampling" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +debReload +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvSelectSignal -win $_nWave3 {( "G3" 23 )} +wvScrollUp -win $_nWave3 11 +wvSelectSignal -win $_nWave3 {( "G3" 9 )} +wvSelectAll -win $_nWave3 +wvCut -win $_nWave3 +wvSetPosition -win $_nWave3 {("G3" 0)} +wvSetPosition -win $_nWave3 {("G3" 0)} +wvSetPosition -win $_nWave3 {("G3" 0)} +wvSetPosition -win $_nWave3 {("G3" 0)} +srcDeselectAll -win $_nTrace1 +srcSelect -signal "end_cnt" -line 88 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "cnt_n" -line 87 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvZoom -win $_nWave3 1760253.612346 1854937.180736 +wvZoom -win $_nWave3 1785782.485774 1790779.090935 +wvZoom -win $_nWave3 1786420.633128 1786730.843648 +srcDeselectAll -win $_nTrace1 +debReload +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 1781715.819430 1796084.275480 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "cnt_c" -line 90 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvZoom -win $_nWave3 1786134.677199 1787332.579521 +wvSetCursor -win $_nWave3 1786573.996586 -snap {("G3" 3)} +srcDeselectAll -win $_nTrace1 +srcSelect -signal "add_cnt" -line 85 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "cnt_c" -line 85 -pos 2 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvSelectSignal -win $_nWave3 {( "G3" 5 )} +wvSetRadix -win $_nWave3 -format UDec +wvSetCursor -win $_nWave3 1786544.248236 -snap {("G3" 5)} +wvSetCursor -win $_nWave3 1786576.652689 -snap {("G3" 5)} +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "dsp_cen" -line 200 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +srcDeselectAll -win $_nTrace1 +debReload +wvZoom -win $_nWave3 1785492.697174 1789538.472823 +wvZoom -win $_nWave3 1786422.059385 1786737.827241 +wvSelectSignal -win $_nWave3 {( "G3" 6 )} +wvSelectSignal -win $_nWave3 {( "G3" 4 )} +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +srcDeselectAll -win $_nTrace1 +debReload +srcDeselectAll -win $_nTrace1 +srcSelect -signal "end_cnt_flag" -line 94 -pos 2 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 1781489.569440 1797692.731345 +wvZoom -win $_nWave3 1786713.382613 1787166.065185 +srcDeselectAll -win $_nTrace1 +debReload +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 2065823.310333 2166245.276807 +wvZoom -win $_nWave3 2096150.298877 2101316.129525 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 1737300.020009 1910886.562058 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "debug_data_sel" -line 40 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "debug_ch_sel" -line 41 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 11476.796169 100421.966475 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvSetCursor -win $_nWave3 9466.448281 -snap {("G3" 8)} +wvSetCursor -win $_nWave3 26032.732772 -snap {("G3" 8)} +srcDeselectAll -win $_nTrace1 +srcSelect -signal "clk" -line 36 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvZoom -win $_nWave3 8519.803453 23981.668978 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 24409.863091 28633.592210 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 1787511.003246 2170549.075370 +wvZoom -win $_nWave3 1854096.778977 1943444.018860 +wvZoom -win $_nWave3 1873273.747536 1879890.594126 +wvZoom -win $_nWave3 1874514.956453 1875462.735366 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 1699820.809559 1972686.989034 +wvZoom -win $_nWave3 1786218.349312 1815380.544103 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +srcDeselectAll -win $_nTrace1 +debReload +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 14345.995211 77468.374137 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 2227933.056213 2270971.041845 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 1430295.722501 2817553.459370 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 1738734.619530 2189198.869144 +wvZoom -win $_nWave3 2101103.643387 2126872.995139 +wvZoom -win $_nWave3 2108120.220760 2109822.940676 +srcDeselectAll -win $_nTrace1 +debReload +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +srcDeselectAll -win $_nTrace1 +debReload +wvZoom -win $_nWave3 1685654.437251 2318312.826040 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 1952489.948169 2308270.629392 +wvZoom -win $_nWave3 2068927.262023 2159489.617244 +wvZoom -win $_nWave3 2105794.775146 2113987.555840 +wvZoom -win $_nWave3 2108145.431070 2109722.223452 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +srcDeselectAll -win $_nTrace1 +debReload +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvSelectSignal -win $_nWave3 {( "G3" 1 )} +srcDeselectAll -win $_nTrace1 +srcSelect -signal "end_cnt_flag" -line 84 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +debReload +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +srcDeselectAll -win $_nTrace1 +debReload +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 2851983.847876 3002616.797588 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 2047173.516559 2225063.857171 +wvZoom -win $_nWave3 2106259.931245 2113754.202800 +wvZoom -win $_nWave3 2109048.265539 2109646.477903 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 1710042.629109 1926667.156789 +wvZoom -win $_nWave3 1784876.556852 1797749.145193 +srcHBSelect "TB.U_digital_top.U_spi_slave" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U_spi_slave" -delim "." +srcHBSelect "TB.U_digital_top.U_spi_slave" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "sys_wrdata" -line 52 -pos 1 -win $_nTrace1 +srcSelect -signal "sys_wren" -line 53 -pos 1 -win $_nTrace1 +srcHBSelect "TB.U_digital_top.U_debug_top.U_dbg_sram.U_tsmc_dpram" -win $_nTrace1 +srcHBSelect \ + "TB.U_digital_top.U_debug_top.U_dbg_sram.U_tsmc_dpram.spram_512X128_generation" \ + -win $_nTrace1 +srcSetScope -win $_nTrace1 \ + "TB.U_digital_top.U_debug_top.U_dbg_sram.U_tsmc_dpram.spram_512X128_generation" \ + -delim "." +srcHBSelect \ + "TB.U_digital_top.U_debug_top.U_dbg_sram.U_tsmc_dpram.spram_512X128_generation" \ + -win $_nTrace1 +srcSelect -signal "PortBDataOut\[127:0\]" -line 178 -pos 1 -win $_nTrace1 +srcSelect -signal "PortBDataIn\[127:0\]" -line 177 -pos 1 -win $_nTrace1 +srcSelect -signal "PortBAddr\[ADDRWIDTH-1:LSB\]" -line 176 -pos 1 -win $_nTrace1 +srcSelect -signal "BWEBB\[127:0\]" -line 175 -pos 1 -win $_nTrace1 +srcSelect -signal "PortBWriteEnable" -line 174 -pos 1 -win $_nTrace1 +srcSelect -signal "PortBChipEnable" -line 173 -pos 1 -win $_nTrace1 +srcSelect -signal "PortClk" -line 166 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 2844810.850271 2989705.401898 +wvZoom -win $_nWave3 2891716.847027 2898270.835615 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 3174768.740115 3226414.322874 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 2916216.371443 2936737.188361 +wvSelectSignal -win $_nWave3 {( "G3" 14 )} +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 1717264.080110 1819768.063157 +wvZoom -win $_nWave3 1786675.868186 1796039.868411 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "PortADataOut\[127:0\]" -line 172 -pos 1 -win $_nTrace1 +srcSelect -signal "PortADataIn\[127:0\]" -line 171 -pos 1 -win $_nTrace1 +srcSelect -signal "PortAAddr\[ADDRWIDTH-1:LSB\]" -line 170 -pos 1 -win $_nTrace1 +srcSelect -signal "BWEBA\[127:0\]" -line 169 -pos 1 -win $_nTrace1 +srcSelect -signal "PortAWriteEnable" -line 168 -pos 1 -win $_nTrace1 +srcSelect -signal "PortAChipEnable" -line 167 -pos 1 -win $_nTrace1 +srcSelect -signal "PortClk" -line 166 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 1748776.816177 1896540.566847 +wvZoom -win $_nWave3 1784423.592392 1794645.829689 +wvZoom -win $_nWave3 1788507.954167 1789867.897044 +wvZoom -win $_nWave3 1788703.351724 1789074.245236 +wvZoom -win $_nWave3 1788741.345693 1788805.326879 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 2867764.442608 3044220.183698 +wvZoom -win $_nWave3 2891474.460146 2910411.173824 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 2919518.431466 2922944.675005 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvSelectSignal -win $_nWave3 {( "G3" 19 )} +wvSelectSignal -win $_nWave3 {( "G3" 19 )} +wvSelectSignal -win $_nWave3 {( "G3" 17 )} +wvSelectSignal -win $_nWave3 {( "G3" 12 )} +wvZoom -win $_nWave3 2870633.641650 2933756.020576 +wvZoom -win $_nWave3 2897562.124366 2899801.499228 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 2919830.249520 2925264.333443 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 1740169.219051 1989789.535716 +wvZoom -win $_nWave3 1784004.981977 1822305.926352 +wvZoom -win $_nWave3 1787894.523556 1791223.563510 +wvZoom -win $_nWave3 1788676.958666 1789506.635143 +wvZoomOut -win $_nWave3 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvSelectSignal -win $_nWave3 {( "G3" 21 )} +wvSetCursor -win $_nWave3 1788847.125128 -snap {("G3" 24)} +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 1788735.275172 1789030.353015 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 1788835.968032 1788913.434144 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 2857722.245960 3011224.394714 +wvZoom -win $_nWave3 2919599.608806 2924160.426529 +wvScrollDown -win $_nWave3 1 +srcHBSelect "TB.U_digital_top.U_debug_top.U_debug_sampling" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U_debug_top.U_debug_sampling" -delim \ + "." +srcHBSelect "TB.U_digital_top.U_debug_top.U_debug_sampling" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "mod_cen" -line 130 -pos 1 -win $_nTrace1 +srcSelect -signal "mod_addr" -line 133 -pos 1 -win $_nTrace1 +srcSelect -signal "mod_wrdata" -line 125 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 1770295.808993 1872152.374989 +wvZoom -win $_nWave3 1787279.431527 1791841.521623 +wvZoom -win $_nWave3 1788406.298127 1789191.260858 +wvZoomOut -win $_nWave3 +srcHBSelect "TB.U_digital_top.U_debug_top" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U_debug_top" -delim "." +srcHBSelect "TB.U_digital_top.U_debug_top" -win $_nTrace1 +srcSelect -signal "debug_cen" -line 79 -pos 1 -win $_nTrace1 +srcSelect -signal "debug_wren" -line 78 -pos 1 -win $_nTrace1 +srcSelect -signal "debug_bwen" -line 77 -pos 1 -win $_nTrace1 +srcSelect -signal "debug_wrdata" -line 76 -pos 1 -win $_nTrace1 +srcSelect -signal "debug_rwaddr" -line 75 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "debug_rwaddr" -line 133 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +srcDeselectAll -win $_nTrace1 +srcSelect -inst "U_dbg_sram" -line 131 -pos 1 -win $_nTrace1 +srcAction -pos 130 3 7 -win $_nTrace1 -name "U_dbg_sram" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -inst "U_tsmc_dpram" -line 70 -pos 1 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -inst "U_tsmc_dpram" -line 70 -pos 1 -win $_nTrace1 +srcAction -pos 69 3 7 -win $_nTrace1 -name "U_tsmc_dpram" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -signal "PortAAddr\[ADDRWIDTH-2:LSB\]" -line 93 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvZoom -win $_nWave3 1788837.418455 1788950.202457 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 1789008.244956 1789208.305270 +wvZoom -win $_nWave3 1789102.907640 1789139.991991 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 1788548.887172 1791916.902722 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 1786122.571756 1797019.707655 +wvZoom -win $_nWave3 1788480.798948 1789418.290906 +wvZoom -win $_nWave3 1788831.682856 1788918.156615 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 1789081.383026 1789176.484987 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 1789357.347409 1789418.077708 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvZoom -win $_nWave3 2860591.445002 3051393.181304 +wvZoom -win $_nWave3 2915758.953680 2935135.271912 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvZoom -win $_nWave3 1745907.617135 1948186.149605 +wvZoom -win $_nWave3 1785825.110239 1799370.147225 +wvZoom -win $_nWave3 1788035.564167 1789471.157888 +wvZoom -win $_nWave3 1788761.955491 1788885.461115 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvZoom -win $_nWave3 1789080.906710 1789144.877693 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 1788692.584398 1789026.651939 +wvZoom -win $_nWave3 1788737.916844 1788838.063034 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvZoomOut -win $_nWave3 +wvSetCursor -win $_nWave3 1789104.549602 -snap {("G3" 20)} +wvZoom -win $_nWave3 1789088.206455 1789155.000188 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 1789084.874172 1789173.024129 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 1788773.065690 1788979.465588 +wvSetCursor -win $_nWave3 1788847.571019 -snap {("G3" 24)} +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvSelectSignal -win $_nWave3 {( "G3" 22 )} +wvSelectAll -win $_nWave3 +wvCut -win $_nWave3 +wvSetPosition -win $_nWave3 {("G3" 0)} +wvSetPosition -win $_nWave3 {("G3" 0)} +wvSetPosition -win $_nWave3 {("G3" 0)} +wvSetPosition -win $_nWave3 {("G3" 0)} +srcSelect -signal "PortADataIn" -line 94 -pos 1 -win $_nTrace1 +srcSelect -signal "PortAWriteEnable" -line 91 -pos 1 -win $_nTrace1 +srcSelect -signal "BWEBA" -line 92 -pos 2 -win $_nTrace1 +srcSelect -signal "U0_CEBA" -line 90 -pos 1 -win $_nTrace1 +srcSelect -signal "PortClk" -line 89 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "PortAWriteEnable" -line 91 -pos 1 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "U0_CEBA" -line 90 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +debReload +srcDeselectAll -win $_nTrace1 +srcSelect -signal "PortClk" -line 89 -pos 1 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "U0_CEBA" -line 90 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvSelectGroup -win $_nWave3 {G4} +wvSelectSignal -win $_nWave3 {( "G3" 3 )} +wvSelectAll -win $_nWave3 +wvCut -win $_nWave3 +wvSetPosition -win $_nWave3 {("G3" 0)} +wvSetPosition -win $_nWave3 {("G3" 0)} +wvSetPosition -win $_nWave3 {("G3" 0)} +wvSetPosition -win $_nWave3 {("G3" 0)} +srcHBSelect \ + "TB.U_digital_top.U_debug_top.U_dbg_sram.U_tsmc_dpram.spram_512X128_generation" \ + -win $_nTrace1 +srcSetScope -win $_nTrace1 \ + "TB.U_digital_top.U_debug_top.U_dbg_sram.U_tsmc_dpram.spram_512X128_generation" \ + -delim "." +srcHBSelect \ + "TB.U_digital_top.U_debug_top.U_dbg_sram.U_tsmc_dpram.spram_512X128_generation" \ + -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "PortAWriteEnable" -line 168 -pos 1 -win $_nTrace1 +srcSelect -signal "BWEBA\[127:0\]" -line 169 -pos 1 -win $_nTrace1 +srcSelect -signal "PortAChipEnable" -line 167 -pos 1 -win $_nTrace1 +srcSelect -signal "PortAAddr\[ADDRWIDTH-1:LSB\]" -line 170 -pos 1 -win $_nTrace1 +srcSelect -signal "PortADataIn\[127:0\]" -line 171 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvZoom -win $_nWave3 1788838.372266 1788894.754677 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoom -win $_nWave3 1796048.307463 1798890.281021 +wvZoom -win $_nWave3 1796752.814433 1796943.119536 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 1787979.327220 1790485.447105 +wvZoom -win $_nWave3 1788727.273421 1788971.772922 +wvCut -win $_nWave3 +wvSetPosition -win $_nWave3 {("G3" 0)} +wvSetPosition -win $_nWave3 {("G3" 0)} +wvSetPosition -win $_nWave3 {("G3" 0)} +wvSetPosition -win $_nWave3 {("G3" 0)} +srcHBSelect "TB.U_digital_top.U_debug_top.U_dbg_sram.U_tsmc_dpram" -win $_nTrace1 +srcHBDrag -win $_nTrace1 +srcHBSelect "TB.U_digital_top.U_debug_top.U_debug_sampling" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U_debug_top.U_debug_sampling" -delim \ + "." +srcHBSelect "TB.U_digital_top.U_debug_top.U_debug_sampling" -win $_nTrace1 +srcSelect -signal "debug_cen" -line 72 -pos 1 -win $_nTrace1 +srcSelect -signal "debug_wren" -line 71 -pos 1 -win $_nTrace1 +srcSelect -signal "debug_bwen" -line 70 -pos 1 -win $_nTrace1 +srcSelect -signal "debug_wrdata" -line 69 -pos 1 -win $_nTrace1 +srcSelect -signal "debug_rwaddr" -line 68 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvZoom -win $_nWave3 1788844.264534 1788903.790133 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 1788618.925164 1789237.252274 +wvZoom -win $_nWave3 1788837.738926 1788901.628158 +wvSetCursor -win $_nWave3 1788864.087922 -snap {("G3" 4)} +wvSetCursor -win $_nWave3 1788864.144586 -snap {("G3" 4)} +wvSetCursor -win $_nWave3 1788864.144586 -snap {("G3" 4)} +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvSelectSignal -win $_nWave3 {( "G3" 5 )} +wvZoomOut -win $_nWave3 +wvSetCursor -win $_nWave3 1788607.440205 -snap {("G3" 5)} +wvSetCursor -win $_nWave3 1788645.518753 -snap {("G3" 5)} +wvSetCursor -win $_nWave3 1788669.544504 -snap {("G3" 5)} +wvSetCursor -win $_nWave3 1788707.169736 -snap {("G3" 5)} +wvSetCursor -win $_nWave3 1788732.555436 -snap {("G3" 5)} +wvSetCursor -win $_nWave3 1788762.927611 -snap {("G3" 5)} +wvSetCursor -win $_nWave3 1788790.579890 -snap {("G3" 5)} +wvSetCursor -win $_nWave3 1788832.738283 -snap {("G3" 5)} +wvZoom -win $_nWave3 1788817.778854 1788897.562479 +wvZoomOut -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 1788829.649100 1788932.677888 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "cnt_c" -line 86 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "mod_addr" -line 133 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "cnt_n" -line 135 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +debReload +wvSetCursor -win $_nWave3 1788838.398551 -snap {("G3" 3)} +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvSelectSignal -win $_nWave3 {( "G3" 5 )} +wvZoom -win $_nWave3 1767426.609951 1893671.367805 +wvZoom -win $_nWave3 1787692.952453 1792171.702178 +wvZoom -win $_nWave3 1788497.339876 1789067.362568 +wvZoom -win $_nWave3 1788846.178596 1788883.590285 +wvZoomOut -win $_nWave3 +wvSetCursor -win $_nWave3 1788848.078213 -snap {("G3" 1)} +srcHBSelect "TB.U_digital_top.U_debug_top.U_dbg_sram" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U_debug_top.U_dbg_sram" -delim "." +srcHBSelect "TB.U_digital_top.U_debug_top.U_dbg_sram" -win $_nTrace1 +srcHBSelect "TB.U_digital_top.U_debug_top.U_dbg_sram.U_tsmc_dpram" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U_debug_top.U_dbg_sram.U_tsmc_dpram" \ + -delim "." +srcHBSelect "TB.U_digital_top.U_debug_top.U_dbg_sram.U_tsmc_dpram" -win $_nTrace1 +srcHBSelect \ + "TB.U_digital_top.U_debug_top.U_dbg_sram.U_tsmc_dpram.spram_512X128_generation" \ + -win $_nTrace1 +srcSetScope -win $_nTrace1 \ + "TB.U_digital_top.U_debug_top.U_dbg_sram.U_tsmc_dpram.spram_512X128_generation" \ + -delim "." +srcHBSelect \ + "TB.U_digital_top.U_debug_top.U_dbg_sram.U_tsmc_dpram.spram_512X128_generation" \ + -win $_nTrace1 +srcSelect -signal "PortClk" -line 166 -pos 1 -win $_nTrace1 +srcSelect -signal "PortAChipEnable" -line 167 -pos 1 -win $_nTrace1 +srcSelect -signal "PortAWriteEnable" -line 168 -pos 1 -win $_nTrace1 +srcSelect -signal "BWEBA\[127:0\]" -line 169 -pos 1 -win $_nTrace1 +srcSelect -signal "PortAAddr\[ADDRWIDTH-1:LSB\]" -line 170 -pos 1 -win $_nTrace1 +srcSelect -signal "PortADataIn\[127:0\]" -line 171 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvSelectSignal -win $_nWave3 {( "G3" 10 )} +wvSetCursor -win $_nWave3 1788880.081383 -snap {("G3" 13)} +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 1788752.334153 1789206.782482 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 1788840.704703 1788921.719439 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 1789272.094696 1789777.942800 +wvZoom -win $_nWave3 1789347.915831 1789416.334311 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 1794384.228943 1803332.091772 +wvZoom -win $_nWave3 1796380.138035 1798340.335036 +wvZoom -win $_nWave3 1796753.053562 1796938.207425 +wvZoomOut -win $_nWave3 +wvSetCursor -win $_nWave3 1796848.011629 -snap {("G3" 10)} +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "PortBDataOut\[127:0\]" -line 178 -pos 1 -win $_nTrace1 +srcSelect -win $_nTrace1 -range {177 178 8 8 10 10} -backward +srcSelect -win $_nTrace1 -range {176 178 8 8 9 10} -backward +srcSelect -win $_nTrace1 -range {175 178 8 8 5 10} -backward +srcSelect -win $_nTrace1 -range {174 178 8 8 4 10} -backward +srcSelect -win $_nTrace1 -range {173 178 8 8 4 10} -backward +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvSelectSignal -win $_nWave3 {( "G3" 18 )} +srcDeselectAll -win $_nTrace1 +srcSelect -signal "PortBChipEnable" -line 173 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvZoom -win $_nWave3 2846245.449792 3051393.181304 +wvZoom -win $_nWave3 2891277.878660 2903923.348584 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 2878997.266084 2950417.534360 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "PortADataOut\[127:0\]" -line 172 -pos 1 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "PortBDataOut\[127:0\]" -line 178 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvZoom -win $_nWave3 2890319.991542 2917811.252235 +wvZoom -win $_nWave3 2894721.031502 2900377.769844 +wvZoomOut -win $_nWave3 +srcHBSelect "TB.U_digital_top.U_spi_slave" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U_spi_slave" -delim "." +srcHBSelect "TB.U_digital_top.U_spi_slave" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "sys_wrdata" -line 52 -pos 1 -win $_nTrace1 +srcSelect -signal "sys_wren" -line 53 -pos 1 -win $_nTrace1 +srcSelect -signal "sys_rden" -line 55 -pos 1 -win $_nTrace1 +srcSelect -signal "sys_rwaddr" -line 54 -pos 1 -win $_nTrace1 +srcSelect -signal "sys_rddata" -line 56 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvSelectSignal -win $_nWave3 {( "G3" 24 )} +wvSetCursor -win $_nWave3 2895158.770234 -snap {("G3" 25)} +wvSetCursor -win $_nWave3 2898259.315064 -snap {("G3" 25)} +wvZoomOut -win $_nWave3 +wvZoomIn -win $_nWave3 +wvSelectSignal -win $_nWave3 {( "G3" 22 )} +wvSetCursor -win $_nWave3 2895068.463103 -snap {("G3" 23)} +wvSelectSignal -win $_nWave3 {( "G3" 9 )} +wvSetPosition -win $_nWave3 {("G3" 9)} +wvSetPosition -win $_nWave3 {("G3" 10)} +wvSetPosition -win $_nWave3 {("G3" 11)} +wvSetPosition -win $_nWave3 {("G3" 12)} +wvSetPosition -win $_nWave3 {("G3" 13)} +wvSetPosition -win $_nWave3 {("G3" 14)} +wvSetPosition -win $_nWave3 {("G3" 15)} +wvSetPosition -win $_nWave3 {("G3" 16)} +wvSetPosition -win $_nWave3 {("G3" 17)} +wvSetPosition -win $_nWave3 {("G3" 18)} +wvSetPosition -win $_nWave3 {("G3" 19)} +wvSetPosition -win $_nWave3 {("G3" 20)} +wvSetPosition -win $_nWave3 {("G3" 21)} +wvSetPosition -win $_nWave3 {("G3" 22)} +wvSetPosition -win $_nWave3 {("G3" 23)} +wvSetPosition -win $_nWave3 {("G3" 24)} +wvSetPosition -win $_nWave3 {("G3" 25)} +wvSetPosition -win $_nWave3 {("G4" 0)} +wvMoveSelected -win $_nWave3 +wvSetPosition -win $_nWave3 {("G4" 1)} +wvSetPosition -win $_nWave3 {("G4" 1)} +wvSetPosition -win $_nWave3 {("G4" 1)} +wvSetPosition -win $_nWave3 {("G4" 1)} +wvSetPosition -win $_nWave3 {("G4" 1)} +wvZoom -win $_nWave3 2894922.968281 2895530.032884 +wvZoomOut -win $_nWave3 +wvSetCursor -win $_nWave3 2895088.396750 -snap {("G3" 23)} +wvSetCursor -win $_nWave3 2895087.858333 -snap {("G3" 22)} +wvSetCursor -win $_nWave3 2895121.240156 -snap {("G4" 1)} +wvSetCursor -win $_nWave3 2895149.237814 -snap {("G4" 1)} +wvZoomOut -win $_nWave3 +srcHBSelect "TB.U_digital_top.U_spi_slave.U_spi_sys" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U_spi_slave.U_spi_sys" -delim "." +srcHBSelect "TB.U_digital_top.U_spi_slave.U_spi_sys" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "spi_dout" -line 266 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "rddata_sr" -line 273 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "miso" -line 280 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 0 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvSetCursor -win $_nWave3 2895344.952211 -snap {("G4" 4)} +srcSelect -signal "sclk" -line 53 -pos 1 -win $_nTrace1 +srcSelect -signal "csn" -line 54 -pos 1 -win $_nTrace1 +srcSelect -signal "mosi" -line 55 -pos 1 -win $_nTrace1 +srcSelect -signal "miso" -line 56 -pos 1 -win $_nTrace1 +srcSelect -signal "oen" -line 57 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvScrollDown -win $_nWave3 1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "cnt_c" -line 120 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 0 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 2883286.576301 2897380.166578 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 2885177.179874 2891189.611735 +wvSetCursor -win $_nWave3 2888747.311254 -snap {("G4" 10)} +srcDeselectAll -win $_nTrace1 +srcSelect -signal "rden" -line 62 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 0 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "cmd" -line 166 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "wren" -line 61 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 2891580.219835 2892604.066325 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvSelectSignal -win $_nWave3 {( "G4" 12 )} +wvSetCursor -win $_nWave3 2894907.153384 -snap {("G4" 12)} +wvZoom -win $_nWave3 2894623.836218 2895546.433144 +wvZoomOut -win $_nWave3 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvZoomOut -win $_nWave3 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvZoom -win $_nWave3 2894851.928362 2895115.410588 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "cmd" -line 166 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "spi_din\[31\]" -line 167 -pos 1 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "initaddr_vld_r\[0\]" -line 167 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "spi_din\[31\]" -line 167 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 0 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 2891775.612711 2892658.015271 +wvZoomOut -win $_nWave3 +wvSetCursor -win $_nWave3 2891965.202085 -snap {("G4" 13)} +wvSelectSignal -win $_nWave3 {( "G4" 7 )} +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvSelectSignal -win $_nWave3 {( "G4" 2 )} +wvZoom -win $_nWave3 2895237.722089 2895650.944751 +wvSetCursor -win $_nWave3 2895344.372017 -snap {("G4" 3)} +wvZoomOut -win $_nWave3 +wvSetCursor -win $_nWave3 2895345.563124 -snap {("G4" 2)} +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 2895266.217044 2895571.140551 +wvZoomOut -win $_nWave3 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvZoom -win $_nWave3 2895327.945460 2895364.725591 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvSelectSignal -win $_nWave3 {( "G4" 8 )} +wvSelectSignal -win $_nWave3 {( "G4" 4 )} +wvSetCursor -win $_nWave3 2895378.956483 -snap {("G4" 6)} +wvSetCursor -win $_nWave3 2895475.514519 -snap {("G4" 6)} +wvSetCursor -win $_nWave3 2895574.682232 -snap {("G4" 6)} +wvSetCursor -win $_nWave3 2895678.547363 -snap {("G4" 6)} +wvSetCursor -win $_nWave3 2895777.193141 -snap {("G4" 6)} +wvSetCursor -win $_nWave3 2895876.491338 -snap {("G4" 6)} +wvSetCursor -win $_nWave3 2895925.553259 -snap {("G4" 6)} +wvSetCursor -win $_nWave3 2895977.224857 -snap {("G4" 6)} +wvSetCursor -win $_nWave3 2896076.131602 -snap {("G4" 6)} +wvSelectSignal -win $_nWave3 {( "G4" 2 )} +wvSetPosition -win $_nWave3 {("G4" 2)} +wvSetPosition -win $_nWave3 {("G4" 3)} +wvSetPosition -win $_nWave3 {("G4" 4)} +wvMoveSelected -win $_nWave3 +wvSetPosition -win $_nWave3 {("G4" 4)} +wvSetPosition -win $_nWave3 {("G4" 4)} +wvSetPosition -win $_nWave3 {("G4" 4)} +wvSetPosition -win $_nWave3 {("G4" 4)} +wvSelectSignal -win $_nWave3 {( "G4" 4 )} +wvSetRadix -win $_nWave3 -format Bin +wvSetCursor -win $_nWave3 2895374.128581 -snap {("G4" 6)} +wvSetCursor -win $_nWave3 2895474.340165 -snap {("G4" 6)} +wvSetCursor -win $_nWave3 2895575.073684 -snap {("G4" 6)} +wvSetCursor -win $_nWave3 2895673.197526 -snap {("G4" 6)} +wvSetCursor -win $_nWave3 2895778.106528 -snap {("G4" 6)} +wvSetCursor -win $_nWave3 2895879.361982 -snap {("G4" 6)} +wvSetCursor -win $_nWave3 2895975.398083 -snap {("G4" 6)} +wvSetCursor -win $_nWave3 2896077.697408 -snap {("G4" 6)} +wvSetCursor -win $_nWave3 2896176.865121 -snap {("G4" 6)} +wvSetCursor -win $_nWave3 2896278.120576 -snap {("G4" 6)} +wvSetCursor -win $_nWave3 2896374.939580 -snap {("G4" 6)} +wvSetCursor -win $_nWave3 2896477.238905 -snap {("G4" 6)} +wvSetCursor -win $_nWave3 2896575.884683 -snap {("G4" 6)} +wvSetCursor -win $_nWave3 2896677.662072 -snap {("G4" 6)} +wvZoom -win $_nWave3 2895411.838409 2895461.422266 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 2896562.436747 2898290.549586 +wvSetCursor -win $_nWave3 2896774.714908 -snap {("G4" 6)} +wvSetCursor -win $_nWave3 2896875.106386 -snap {("G4" 6)} +wvSetCursor -win $_nWave3 2896972.432475 -snap {("G4" 6)} +wvSetCursor -win $_nWave3 2897076.655688 -snap {("G4" 6)} +wvSetCursor -win $_nWave3 2897177.813513 -snap {("G4" 6)} +wvSetCursor -win $_nWave3 2897271.307866 -snap {("G4" 6)} +wvSetCursor -win $_nWave3 2897375.531080 -snap {("G4" 6)} +wvSetCursor -win $_nWave3 2897475.922557 -snap {("G4" 6)} +wvSetCursor -win $_nWave3 2897577.846729 -snap {("G4" 6)} +wvSetCursor -win $_nWave3 2897681.303595 -snap {("G4" 6)} +wvSetCursor -win $_nWave3 2897780.928726 -snap {("G4" 6)} +wvSetCursor -win $_nWave3 2897879.787509 -snap {("G4" 6)} +wvSetCursor -win $_nWave3 2897975.580904 -snap {("G4" 6)} +wvSetCursor -win $_nWave3 2898073.673340 -snap {("G4" 6)} +wvSetCursor -win $_nWave3 2898179.429247 -snap {("G4" 6)} +wvSetCursor -win $_nWave3 2898275.605816 -snap {("G4" 6)} +wvSetCursor -win $_nWave3 2898477.155118 -snap {("G4" 6)} +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 2894946.976939 2897877.488468 +wvZoom -win $_nWave3 2895283.563407 2896227.045168 +wvZoom -win $_nWave3 2895322.892580 2895502.384232 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 2867764.442608 3232152.720958 +wvZoom -win $_nWave3 3140530.479793 3205974.937768 +wvZoom -win $_nWave3 3167172.613904 3195643.129768 +wvZoom -win $_nWave3 3179469.856676 3189671.265465 +wvZoom -win $_nWave3 3183310.653156 3186965.969475 +wvZoom -win $_nWave3 3184878.143568 3186084.154806 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 2866999.702153 3228450.094681 +srcDeselectAll -win $_nTrace1 +debReload +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvSelectSignal -win $_nWave3 {( "G4" 6 )} +wvSelectAll -win $_nWave3 +wvCut -win $_nWave3 +wvSetPosition -win $_nWave3 {("G4" 0)} +wvSetPosition -win $_nWave3 {("G4" 0)} +wvSetPosition -win $_nWave3 {("G4" 0)} +wvSetPosition -win $_nWave3 {("G4" 0)} +srcHBSelect "TB.U_digital_top.U_debug_top" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U_debug_top" -delim "." +srcHBSelect "TB.U_digital_top.U_debug_top" -win $_nTrace1 +srcHBSelect "TB.U_digital_top.U_debug_top.U_debug_sampling" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U_debug_top.U_debug_sampling" -delim \ + "." +srcHBSelect "TB.U_digital_top.U_debug_top.U_debug_sampling" -win $_nTrace1 +srcSelect -signal "debug_cen" -line 72 -pos 1 -win $_nTrace1 +srcSelect -signal "debug_wren" -line 71 -pos 1 -win $_nTrace1 +srcSelect -signal "debug_bwen" -line 70 -pos 1 -win $_nTrace1 +srcSelect -signal "debug_wrdata" -line 69 -pos 1 -win $_nTrace1 +srcSelect -signal "debug_rwaddr" -line 68 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 1665570.043956 1860675.578820 +wvZoom -win $_nWave3 1743698.779202 1753475.686271 +wvZoom -win $_nWave3 1746235.138685 1748082.128668 +wvZoom -win $_nWave3 1746487.410488 1746702.824397 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "debug_wrdata" -line 69 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcHBSelect "TB.U_digital_top.U0_channel_top" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U0_channel_top" -delim "." +srcHBSelect "TB.U_digital_top.U0_channel_top" -win $_nTrace1 +srcSelect -signal "xy_dsp_dout_vld" -line 138 -pos 1 -win $_nTrace1 +srcSelect -signal "xy_dsp_dout15" -line 137 -pos 1 -win $_nTrace1 +srcSelect -signal "xy_dsp_dout14" -line 136 -pos 1 -win $_nTrace1 +srcSelect -signal "xy_dsp_dout13" -line 135 -pos 1 -win $_nTrace1 +srcSelect -signal "xy_dsp_dout4" -line 126 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvSelectSignal -win $_nWave3 {( "G4" 8 )} +wvSelectAll -win $_nWave3 +wvCut -win $_nWave3 +wvSetPosition -win $_nWave3 {("G4" 0)} +wvSetPosition -win $_nWave3 {("G4" 0)} +wvSetPosition -win $_nWave3 {("G4" 0)} +wvSetPosition -win $_nWave3 {("G4" 0)} +srcDeselectAll -win $_nTrace1 +debReload +srcDeselectAll -win $_nTrace1 +srcSelect -signal "xy_dsp_dout15" -line 137 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvSelectSignal -win $_nWave3 {( "G4" 1 )} +wvCut -win $_nWave3 +wvSetPosition -win $_nWave3 {("G5" 0)} +wvSetPosition -win $_nWave3 {("G4" 0)} +wvSetPosition -win $_nWave3 {("G4" 0)} +wvSetPosition -win $_nWave3 {("G4" 0)} +wvSetPosition -win $_nWave3 {("G4" 0)} +srcHBSelect "TB.U_digital_top.U_debug_top.U_debug_sampling" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U_debug_top.U_debug_sampling" -delim \ + "." +srcHBSelect "TB.U_digital_top.U_debug_top.U_debug_sampling" -win $_nTrace1 +srcSelect -signal "debug_cen" -line 72 -pos 1 -win $_nTrace1 +srcSelect -signal "debug_wren" -line 71 -pos 1 -win $_nTrace1 +srcSelect -signal "debug_bwen" -line 70 -pos 1 -win $_nTrace1 +srcSelect -signal "debug_wrdata" -line 69 -pos 1 -win $_nTrace1 +srcSelect -signal "debug_rwaddr" -line 68 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvZoom -win $_nWave3 1744785.449552 1750165.543279 +wvZoom -win $_nWave3 1746720.374612 1747925.229305 +wvZoom -win $_nWave3 1746803.191675 1746995.540983 +wvZoom -win $_nWave3 1746825.795917 1746884.396350 +srcHBSelect "TB.U_digital_top.U0_channel_top" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U0_channel_top" -delim "." +srcHBSelect "TB.U_digital_top.U0_channel_top" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "xy_dsp_dout15" -line 137 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 1746818.194752 1746904.055429 +wvZoomOut -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "xy_dsp_dout0" -line 122 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvZoom -win $_nWave3 1746853.852634 1746873.880446 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvSelectSignal -win $_nWave3 {( "G4" 6 7 )} +wvCut -win $_nWave3 +wvSetPosition -win $_nWave3 {("G4" 5)} +wvSetPosition -win $_nWave3 {("G4" 5)} +wvSetPosition -win $_nWave3 {("G4" 5)} +wvSetPosition -win $_nWave3 {("G4" 5)} +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 1783606.331175 1799176.405298 +wvZoom -win $_nWave3 1786375.111539 1788184.140107 +wvZoom -win $_nWave3 1786778.633211 1786959.937182 +wvZoomOut -win $_nWave3 +srcHBSelect "TB.U_digital_top.U_debug_top.U_debug_sampling" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U_debug_top.U_debug_sampling" -delim \ + "." +srcHBSelect "TB.U_digital_top.U_debug_top.U_debug_sampling" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "end_cnt_flag_w" -line 94 -pos 1 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "end_cnt_flag" -line 94 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomIn -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "cnt_c" -line 86 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvSetCursor -win $_nWave3 1786894.531071 -snap {("G4" 6)} +srcHBSelect "TB.U_digital_top.U_debug_top.U_dbg_sram" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U_debug_top.U_dbg_sram" -delim "." +srcHBSelect "TB.U_digital_top.U_debug_top.U_dbg_sram" -win $_nTrace1 +srcHBSelect "TB.U_digital_top.U_debug_top.U_dbg_sram.U_tsmc_dpram" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U_debug_top.U_dbg_sram.U_tsmc_dpram" \ + -delim "." +srcHBSelect "TB.U_digital_top.U_debug_top.U_dbg_sram.U_tsmc_dpram" -win $_nTrace1 +srcHBSelect \ + "TB.U_digital_top.U_debug_top.U_dbg_sram.U_tsmc_dpram.spram_512X128_generation" \ + -win $_nTrace1 +srcSetScope -win $_nTrace1 \ + "TB.U_digital_top.U_debug_top.U_dbg_sram.U_tsmc_dpram.spram_512X128_generation" \ + -delim "." +srcHBSelect \ + "TB.U_digital_top.U_debug_top.U_dbg_sram.U_tsmc_dpram.spram_512X128_generation" \ + -win $_nTrace1 +srcSelect -signal "PortBDataOut\[127:0\]" -line 178 -pos 1 -win $_nTrace1 +srcSelect -signal "PortBAddr\[ADDRWIDTH-1:LSB\]" -line 176 -pos 1 -win $_nTrace1 +srcSelect -signal "BWEBB\[127:0\]" -line 175 -pos 1 -win $_nTrace1 +srcSelect -signal "PortBWriteEnable" -line 174 -pos 1 -win $_nTrace1 +srcSelect -signal "PortBChipEnable" -line 173 -pos 1 -win $_nTrace1 +srcSelect -signal "PortClk" -line 166 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 2801772.864639 2976794.006208 +wvZoom -win $_nWave3 2846478.930068 2865028.842633 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "BWEBA\[255:128\]" -line 187 -pos 1 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "PortADataIn\[255:128\]" -line 189 -pos 1 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "PortADataOut\[255:128\]" -line 190 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvSelectSignal -win $_nWave3 {( "G4" 14 )} +wvCut -win $_nWave3 +wvSetPosition -win $_nWave3 {("G5" 0)} +wvSetPosition -win $_nWave3 {("G4" 13)} +wvSetPosition -win $_nWave3 {("G4" 13)} +wvSetPosition -win $_nWave3 {("G4" 13)} +wvSetPosition -win $_nWave3 {("G4" 13)} +srcSelect -signal "PortBDataIn\[255:128\]" -line 195 -pos 1 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "PortBDataIn\[255:128\]" -line 195 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "PortBDataIn\[255:128\]" -line 195 -pos 1 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "PortBDataOut\[255:128\]" -line 196 -pos 1 -win $_nTrace1 +wvSelectSignal -win $_nWave3 {( "G4" 14 )} +wvCut -win $_nWave3 +wvSetPosition -win $_nWave3 {("G5" 0)} +wvSetPosition -win $_nWave3 {("G4" 13)} +wvSetPosition -win $_nWave3 {("G4" 13)} +wvSetPosition -win $_nWave3 {("G4" 13)} +wvSetPosition -win $_nWave3 {("G4" 13)} +srcDeselectAll -win $_nTrace1 +srcSelect -signal "PortBDataOut\[255:128\]" -line 196 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 2846245.449792 3016962.792798 +wvZoom -win $_nWave3 2873575.365900 2909914.312527 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 2876161.796469 2879642.600225 +wvSelectSignal -win $_nWave3 {( "G4" 9 )} +wvSetCursor -win $_nWave3 2877453.784381 -snap {("G4" 11)} +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 2902772.579778 2904945.959684 +wvSetCursor -win $_nWave3 2903018.350010 -snap {("G4" 11)} +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 2864895.243565 3170464.941552 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 2860591.445002 3146076.749694 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "PortAAddr\[ADDRWIDTH-1:LSB\]" -line 188 -pos 1 -win $_nTrace1 +debReload +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvSetCursor -win $_nWave3 1810464.595583 -snap {("G4" 3)} +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 1741603.818572 1869283.175947 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvSetCursor -win $_nWave3 1268680.611267 -snap {("G4" 0)} +srcHBSelect "TB.U_digital_top.U0_channel_top.U_ctrl_regfile" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U0_channel_top.U_ctrl_regfile" \ + -delim "." +srcHBSelect "TB.U_digital_top.U0_channel_top.U_ctrl_regfile" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -win $_nTrace1 -range {63 64 6 1 5 1} +srcDeselectAll -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +debReload +wvZoom -win $_nWave3 1739763.650450 1848475.121031 +wvZoom -win $_nWave3 1744006.049302 1749550.093256 +wvZoom -win $_nWave3 1745373.006480 1746916.979696 +wvZoom -win $_nWave3 1745582.521248 1746416.472192 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +srcSelect -signal "mod_sel_sideband" -line 189 -pos 1 -win $_nTrace1 +srcSelect -signal "qam_nco_clr" -line 191 -pos 1 -win $_nTrace1 +srcSelect -signal "qam_nco_sclr_en" -line 192 -pos 1 -win $_nTrace1 +srcSelect -signal "qam_sel_sideband" -line 197 -pos 1 -win $_nTrace1 +srcSelect -signal "intp_mode" -line 198 -pos 1 -win $_nTrace1 +srcSelect -signal "role_sel" -line 200 -pos 1 -win $_nTrace1 +srcSelect -signal "dac_mode_sel" -line 204 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvSelectSignal -win $_nWave3 {( "G4" 19 )} +srcDeselectAll -win $_nTrace1 +srcSelect -signal "qam_mod" -line 195 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcHBSelect "TB.U_digital_top.U_intpll_regfile" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U_intpll_regfile" -delim "." +srcHBSelect "TB.U_digital_top.U_intpll_regfile" -win $_nTrace1 +wvSelectSignal -win $_nWave3 {( "G4" 7 )} +wvSelectAll -win $_nWave3 +wvCut -win $_nWave3 +wvSetPosition -win $_nWave3 {("G4" 0)} +wvSetPosition -win $_nWave3 {("G4" 0)} +wvSetPosition -win $_nWave3 {("G4" 0)} +wvSetPosition -win $_nWave3 {("G4" 0)} +srcDeselectAll -win $_nTrace1 +srcSelect -signal "ref_sel" -line 60 -pos 1 -win $_nTrace1 +srcSelect -signal "ref_en" -line 63 -pos 1 -win $_nTrace1 +srcSelect -signal "ref_s2d_en" -line 65 -pos 1 -win $_nTrace1 +srcSelect -signal "p_cnt" -line 67 -pos 1 -win $_nTrace1 +srcSelect -signal "pfd_delay" -line 68 -pos 1 -win $_nTrace1 +srcSelect -signal "pfd_dff_Set" -line 69 -pos 1 -win $_nTrace1 +srcSelect -signal "pfd_dff_4and" -line 70 -pos 1 -win $_nTrace1 +srcSelect -signal "spd_div" -line 71 -pos 1 -win $_nTrace1 +srcSelect -signal "spd_pulse_width" -line 72 -pos 1 -win $_nTrace1 +srcSelect -signal "spd_pulse_sw" -line 73 -pos 1 -win $_nTrace1 +srcSelect -signal "cpc_sel" -line 74 -pos 1 -win $_nTrace1 +srcSelect -signal "swcp_i" -line 75 -pos 1 -win $_nTrace1 +srcSelect -signal "sw_ptat_r" -line 76 -pos 1 -win $_nTrace1 +srcSelect -signal "sw_fll_cpi" -line 77 -pos 1 -win $_nTrace1 +srcSelect -signal "sw_fll_delay" -line 78 -pos 1 -win $_nTrace1 +srcSelect -toggle -signal "sw_fll_delay" -line 78 -pos 1 -win $_nTrace1 +srcSelect -signal "sw_fll_delay" -line 78 -pos 1 -win $_nTrace1 +srcSelect -signal "pfd_sel" -line 79 -pos 1 -win $_nTrace1 +srcSelect -signal "spd_sel" -line 80 -pos 1 -win $_nTrace1 +srcSelect -signal "fll_sel" -line 81 -pos 1 -win $_nTrace1 +srcSelect -signal "vco_tc" -line 82 -pos 1 -win $_nTrace1 +srcSelect -signal "vco_tcr" -line 83 -pos 1 -win $_nTrace1 +srcSelect -signal "vco_gain_adj" -line 84 -pos 1 -win $_nTrace1 +srcSelect -signal "vco_gain_adj_r" -line 85 -pos 1 -win $_nTrace1 +srcSelect -signal "vco_cur_adj" -line 86 -pos 1 -win $_nTrace1 +srcSelect -signal "vco_buff_en" -line 87 -pos 1 -win $_nTrace1 +srcSelect -signal "vco_en" -line 88 -pos 1 -win $_nTrace1 +srcSelect -signal "pll_dpwr_adj" -line 89 -pos 1 -win $_nTrace1 +srcSelect -signal "vco_fb_adj" -line 90 -pos 1 -win $_nTrace1 +srcSelect -signal "afc_en" -line 91 -pos 1 -win $_nTrace1 +srcSelect -signal "afc_shutdown" -line 92 -pos 1 -win $_nTrace1 +srcSelect -signal "afc_det_speed" -line 93 -pos 1 -win $_nTrace1 +srcSelect -signal "flag_out_sel" -line 94 -pos 1 -win $_nTrace1 +srcSelect -signal "afc_reset" -line 95 -pos 1 -win $_nTrace1 +srcSelect -signal "afc_cnt" -line 96 -pos 1 -win $_nTrace1 +srcSelect -signal "afc_ld_cnt" -line 98 -pos 1 -win $_nTrace1 +srcSelect -signal "afc_pres" -line 100 -pos 1 -win $_nTrace1 +srcSelect -signal "afc_ld_tcc" -line 101 -pos 1 -win $_nTrace1 +srcSelect -signal "afc_fb_tcc" -line 102 -pos 1 -win $_nTrace1 +srcSelect -signal "div_rstn_sel" -line 104 -pos 1 -win $_nTrace1 +srcSelect -signal "test_clk_sel" -line 105 -pos 1 -win $_nTrace1 +srcSelect -signal "test_clk_oen" -line 106 -pos 1 -win $_nTrace1 +srcSelect -signal "dig_clk_sel" -line 107 -pos 1 -win $_nTrace1 +srcSelect -signal "div_sync_en" -line 108 -pos 1 -win $_nTrace1 +srcSelect -signal "sync_oe" -line 109 -pos 1 -win $_nTrace1 +srcSelect -signal "pll_lock" -line 110 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvScrollDown -win $_nWave3 1 +wvSetCursor -win $_nWave3 288354.503734 -snap {("G4" 32)} +wvSetCursor -win $_nWave3 78902.973659 -snap {("G4" 37)} +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 25 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvSelectSignal -win $_nWave3 {( "G4" 1 )} +wvSelectSignal -win $_nWave3 {( "G4" 2 )} +wvSetCursor -win $_nWave3 489632.054881 -snap {("G4" 2)} +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvSelectSignal -win $_nWave3 {( "G4" 3 )} +wvSelectSignal -win $_nWave3 {( "G4" 5 )} +wvSelectSignal -win $_nWave3 {( "G4" 11 )} +wvSelectSignal -win $_nWave3 {( "G4" 12 )} +wvScrollDown -win $_nWave3 3 +wvSelectSignal -win $_nWave3 {( "G4" 13 )} +wvScrollDown -win $_nWave3 4 +wvSelectSignal -win $_nWave3 {( "G4" 15 )} +wvSelectSignal -win $_nWave3 {( "G4" 17 )} +wvSelectSignal -win $_nWave3 {( "G4" 18 )} +wvScrollDown -win $_nWave3 2 +wvScrollDown -win $_nWave3 5 +verdiDockWidgetMaximize -dock windowDock_nWave_3 +wvSelectSignal -win $_nWave3 {( "G4" 19 )} +wvSelectSignal -win $_nWave3 {( "G4" 19 20 )} +wvSelectSignal -win $_nWave3 {( "G4" 19 20 21 )} +wvSelectSignal -win $_nWave3 {( "G4" 19 20 21 22 )} +wvSelectSignal -win $_nWave3 {( "G4" 19 20 21 22 23 )} +wvSelectSignal -win $_nWave3 {( "G4" 24 )} +wvSelectSignal -win $_nWave3 {( "G4" 24 25 )} +wvSelectSignal -win $_nWave3 {( "G4" 26 )} +wvSelectSignal -win $_nWave3 {( "G4" 27 )} +wvSelectSignal -win $_nWave3 {( "G4" 28 )} +wvSelectSignal -win $_nWave3 {( "G4" 29 )} +wvSelectSignal -win $_nWave3 {( "G4" 30 )} +wvSelectSignal -win $_nWave3 {( "G4" 31 )} +wvSelectSignal -win $_nWave3 {( "G4" 32 )} +wvSelectSignal -win $_nWave3 {( "G4" 33 )} +wvSelectSignal -win $_nWave3 {( "G4" 34 )} +wvSelectSignal -win $_nWave3 {( "G4" 35 )} +wvSelectSignal -win $_nWave3 {( "G4" 36 )} +wvSelectSignal -win $_nWave3 {( "G4" 41 )} +wvSelectSignal -win $_nWave3 {( "G4" 42 )} +wvSelectSignal -win $_nWave3 {( "G4" 43 )} +wvSelectSignal -win $_nWave3 {( "G4" 44 )} +verdiDockWidgetRestore -dock windowDock_nWave_3 +srcHBSelect "TB.U_digital_top.U0_channel_top.U_ch0_dac_regfile" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U0_channel_top.U_ch0_dac_regfile" \ + -delim "." +srcHBSelect "TB.U_digital_top.U0_channel_top.U_ch0_dac_regfile" -win $_nTrace1 +wvSelectSignal -win $_nWave3 {( "G4" 3 )} +wvSelectAll -win $_nWave3 +wvCut -win $_nWave3 +wvSetPosition -win $_nWave3 {("G4" 0)} +wvSetPosition -win $_nWave3 {("G4" 0)} +wvSetPosition -win $_nWave3 {("G4" 0)} +wvSetPosition -win $_nWave3 {("G4" 0)} +srcDeselectAll -win $_nTrace1 +srcSelect -signal "Prbs" -line 68 -pos 1 -win $_nTrace1 +srcSelect -win $_nTrace1 -range {68 69 5 12 3 3} +srcSelect -win $_nTrace1 -range {68 70 5 12 3 3} +srcDeselectAll -win $_nTrace1 +srcSelect -signal "Prbs" -line 68 -pos 1 -win $_nTrace1 +srcSelect -signal "Set0" -line 69 -pos 1 -win $_nTrace1 +srcSelect -signal "Set1" -line 70 -pos 1 -win $_nTrace1 +srcSelect -signal "Set2" -line 71 -pos 1 -win $_nTrace1 +srcSelect -signal "Set3" -line 72 -pos 1 -win $_nTrace1 +srcSelect -signal "Set4" -line 73 -pos 1 -win $_nTrace1 +srcSelect -signal "Set5" -line 74 -pos 1 -win $_nTrace1 +srcSelect -signal "Set6" -line 75 -pos 1 -win $_nTrace1 +srcSelect -signal "Set7" -line 76 -pos 1 -win $_nTrace1 +srcSelect -signal "Set8" -line 77 -pos 1 -win $_nTrace1 +srcSelect -signal "Set9" -line 78 -pos 1 -win $_nTrace1 +srcSelect -signal "Set10" -line 79 -pos 1 -win $_nTrace1 +srcSelect -signal "Set11" -line 80 -pos 1 -win $_nTrace1 +srcSelect -signal "Set12" -line 81 -pos 1 -win $_nTrace1 +srcSelect -signal "Set13" -line 82 -pos 1 -win $_nTrace1 +srcSelect -signal "Set14" -line 83 -pos 1 -win $_nTrace1 +srcSelect -signal "Set15" -line 84 -pos 1 -win $_nTrace1 +srcSelect -signal "Dac_addr" -line 86 -pos 1 -win $_nTrace1 +srcSelect -signal "Dac_dw" -line 87 -pos 1 -win $_nTrace1 +srcSelect -signal "Dac_ref" -line 88 -pos 1 -win $_nTrace1 +srcSelect -signal "Prbs_rst0" -line 90 -pos 1 -win $_nTrace1 +srcSelect -signal "Prbs_set0" -line 91 -pos 1 -win $_nTrace1 +srcSelect -signal "Prbs_rst1" -line 92 -pos 1 -win $_nTrace1 +srcSelect -signal "Prbs_set1" -line 93 -pos 1 -win $_nTrace1 +srcSelect -signal "Cal_sig" -line 95 -pos 1 -win $_nTrace1 +srcSelect -signal "Cal_end" -line 96 -pos 1 -win $_nTrace1 +srcSelect -signal "Cal_rstn" -line 97 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvSelectSignal -win $_nWave3 {( "G4" 9 )} +wvSelectSignal -win $_nWave3 {( "G4" 10 )} +wvScrollUp -win $_nWave3 10 +verdiDockWidgetMaximize -dock windowDock_nWave_3 +wvSelectSignal -win $_nWave3 {( "G4" 18 )} +wvSelectSignal -win $_nWave3 {( "G4" 19 )} +wvSelectSignal -win $_nWave3 {( "G4" 20 )} +wvSetCursor -win $_nWave3 930387.719180 -snap {("G4" 20)} +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 0.000000 107502.266880 +wvZoom -win $_nWave3 0.000000 7607.852733 +wvSelectSignal -win $_nWave3 {( "G4" 27 )} +wvSelectAll -win $_nWave3 +verdiDockWidgetRestore -dock windowDock_nWave_3 +wvCut -win $_nWave3 +wvSetPosition -win $_nWave3 {("G4" 0)} +wvSetPosition -win $_nWave3 {("G4" 0)} +wvSetPosition -win $_nWave3 {("G4" 0)} +wvSetPosition -win $_nWave3 {("G4" 0)} +srcHBSelect "TB.U_digital_top.U_spi_slave" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U_spi_slave" -delim "." +srcHBSelect "TB.U_digital_top.U_spi_slave" -win $_nTrace1 +srcSelect -signal "sclk" -line 39 -pos 1 -win $_nTrace1 +srcSelect -signal "csn" -line 40 -pos 1 -win $_nTrace1 +srcSelect -signal "mosi" -line 41 -pos 1 -win $_nTrace1 +srcSelect -signal "miso" -line 43 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvSelectSignal -win $_nWave3 {( "G4" 2 )} +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +verdiDockWidgetMaximize -dock windowDock_nWave_3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvSetCursor -win $_nWave3 1727999.400960 -snap {("G4" 2)} +wvSelectSignal -win $_nWave3 {( "G4" 2 )} +wvZoom -win $_nWave3 392184.195840 650985.949440 +wvZoom -win $_nWave3 413843.911834 430725.749299 +wvSetCursor -win $_nWave3 416565.783474 -snap {("G4" 2)} +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvSetCursor -win $_nWave3 1747907.228160 -snap {("G4" 2)} +wvSetCursor -win $_nWave3 414082.805760 -snap {("G4" 2)} +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 113474.615040 420055.153920 +wvZoom -win $_nWave3 144227.001402 207807.088542 +wvZoom -win $_nWave3 152639.136008 157060.397452 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvSetCursor -win $_nWave3 148466.825593 -snap {("G4" 2)} +wvSetCursor -win $_nWave3 154920.506913 -snap {("G4" 2)} +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvSetCursor -win $_nWave3 424036.719360 -snap {("G4" 2)} +verdiDockWidgetRestore -dock windowDock_nWave_3 +srcHBSelect "TB.U_digital_top" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top" -delim "." +srcHBSelect "TB.U_digital_top" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "sync_in" -line 45 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvZoom -win $_nWave3 1694156.094720 1799667.578880 +wvZoom -win $_nWave3 1737074.919969 1747918.254034 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 1712073.139200 1907169.845760 +wvZoom -win $_nWave3 1736205.101057 1751572.718558 +srcHBSelect "TB.U_digital_top.U_spi_slave.U_spi_pll" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U_spi_slave.U_spi_pll" -delim "." +srcHBSelect "TB.U_digital_top.U_spi_slave.U_spi_pll" -win $_nTrace1 +srcHBSelect "TB.U_digital_top.U_intpll_regfile" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U_intpll_regfile" -delim "." +srcHBSelect "TB.U_digital_top.U_intpll_regfile" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "dig_clk_sel" -line 107 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +debReload +srcDeselectAll -win $_nTrace1 +srcSelect -signal "dig_clk_sel" -line 107 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvZoomOut -win $_nWave3 +srcSelect -all -win $_nTrace1 +srcSelect -win $_nTrace1 -range {1 677 1 6 1 1} +wvSelectSignal -win $_nWave3 {( "G4" 1 )} +wvSelectSignal -win $_nWave3 {( "G4" 4 )} +wvSelectAll -win $_nWave3 +wvCut -win $_nWave3 +wvSetPosition -win $_nWave3 {("G4" 0)} +wvSetPosition -win $_nWave3 {("G4" 0)} +wvSetPosition -win $_nWave3 {("G4" 0)} +wvSetPosition -win $_nWave3 {("G4" 0)} +srcHBSelect "TB.U_digital_top.U0_channel_top" -win $_nTrace1 +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top" -win $_nTrace1 +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.U_codeword_decode" -win \ + $_nTrace1 +srcSetScope -win $_nTrace1 \ + "TB.U_digital_top.U0_channel_top.U_awg_top.U_codeword_decode" \ + -delim "." +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.U_codeword_decode" -win \ + $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "sendc_i" -line 42 -pos 1 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "send_i" -line 41 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "index_vld_o" -line 58 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvZoom -win $_nWave3 1744352.302581 1745695.195926 +wvSetCursor -win $_nWave3 1744655.589877 -snap {("G5" 0)} +wvSetCursor -win $_nWave3 1744655.589877 -snap {("G4" 2)} +srcDeselectAll -win $_nTrace1 +srcSelect -signal "bais_index_o" -line 48 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "codeword_i" -line 43 -pos 1 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "bais_index_o" -line 48 -pos 1 -win $_nTrace1 +srcSearchString "bais_index_o" -win $_nTrace1 -next -case +srcDeselectAll -win $_nTrace1 +srcSelect -signal "bais_index_o" -line 90 -pos 1 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "bais_index_w" -line 90 -pos 1 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "codeword_i\[16:15\]" -line 65 -pos 1 -win $_nTrace1 +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.enve_dpram" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U0_channel_top.U_awg_top.enve_dpram" \ + -delim "." +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.enve_dpram" -win $_nTrace1 +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.ampr_lut" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U0_channel_top.U_awg_top.ampr_lut" \ + -delim "." +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.ampr_lut" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "index_vld_i" -line 40 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "param_o" -line 41 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.U_awg_ctrl" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U0_channel_top.U_awg_top.U_awg_ctrl" \ + -delim "." +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.U_awg_ctrl" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "enve_index_vld_i" -line 88 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "enve_vld_o" -line 100 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "clk" -line 85 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvSetCursor -win $_nWave3 1744625.013228 -snap {("G4" 1)} +wvSetCursor -win $_nWave3 1744654.763481 -snap {("G4" 8)} +wvSetCursor -win $_nWave3 1744686.992921 -snap {("G4" 8)} +wvSetCursor -win $_nWave3 1744719.222362 -snap {("G4" 8)} +wvSetCursor -win $_nWave3 1744754.757385 -snap {("G4" 8)} +wvSetCursor -win $_nWave3 1744785.334034 -snap {("G4" 8)} +srcDeselectAll -win $_nTrace1 +srcSelect -signal "muc_mod_nco_fcw_i" -line 108 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "mod_nco_fcw_o" -line 113 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvSetCursor -win $_nWave3 1744620.054853 -snap {("G4" 1)} +wvSelectSignal -win $_nWave3 {( "G4" 2 )} +srcDeselectAll -win $_nTrace1 +srcSelect -signal "muc_mod_nco_fcw_i" -line 108 -pos 1 -win $_nTrace1 +srcSelect -signal "muc_mod_nco_pha_i" -line 109 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvSetCursor -win $_nWave3 1744694.430484 -snap {("G4" 11)} +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.U_freqmod" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U0_channel_top.U_awg_top.U_freqmod" \ + -delim "." +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.U_freqmod" -win $_nTrace1 +srcSelect -signal "Mod_Vld" -line 51 -pos 1 -win $_nTrace1 +srcSelect -signal "Mod_Data_Q" -line 50 -pos 1 -win $_nTrace1 +srcSelect -signal "Mod_Data_I" -line 49 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvSetCursor -win $_nWave3 1745293.567515 -snap {("G4" 13)} +srcDeselectAll -win $_nTrace1 +srcSelect -signal "Env_Vld" -line 40 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvSetCursor -win $_nWave3 1744881.195959 -snap {("G4" 16)} +wvSetCursor -win $_nWave3 1744910.119815 -snap {("G4" 8)} +wvSetCursor -win $_nWave3 1744945.654839 -snap {("G4" 8)} +wvSetCursor -win $_nWave3 1744978.710676 -snap {("G4" 8)} +wvSetCursor -win $_nWave3 1745008.460928 -snap {("G4" 8)} +wvSetCursor -win $_nWave3 1745044.822348 -snap {("G4" 8)} +wvSetCursor -win $_nWave3 1745077.878184 -snap {("G4" 8)} +wvSetCursor -win $_nWave3 1745105.149249 -snap {("G4" 8)} +wvSetCursor -win $_nWave3 1745134.899501 -snap {("G4" 8)} +wvSetCursor -win $_nWave3 1745168.781734 -snap {("G4" 8)} +wvSetCursor -win $_nWave3 1745202.663966 -snap {("G4" 8)} +wvSetCursor -win $_nWave3 1745229.108635 -snap {("G4" 8)} +wvSetCursor -win $_nWave3 1745267.949242 -snap {("G4" 8)} +wvSetCursor -win $_nWave3 1745297.699495 -snap {("G4" 8)} +srcSelect -signal "Env_Qdata_r9" -line 257 -pos 1 -win $_nTrace1 +srcSelect -signal "Nco_Cos" -line 258 -pos 1 -win $_nTrace1 +srcSelect -signal "mult_qcos_tmp" -line 260 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 0 +wvSelectSignal -win $_nWave3 {( "G4" 18 )} +srcSelect -signal "Env_Idata_r9" -line 221 -pos 1 -win $_nTrace1 +srcSelect -signal "Nco_Cos" -line 222 -pos 1 -win $_nTrace1 +srcSelect -signal "mult_icos_tmp" -line 224 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvSelectSignal -win $_nWave3 {( "G4" 24 )} +wvSelectSignal -win $_nWave3 {( "G4" 26 )} +wvSelectSignal -win $_nWave3 {( "G4" 25 26 )} +wvSelectSignal -win $_nWave3 {( "G4" 24 25 26 )} +wvSelectSignal -win $_nWave3 {( "G4" 26 )} +wvSelectSignal -win $_nWave3 {( "G4" 25 )} +srcDeselectAll -win $_nTrace1 +srcSelect -signal "Env_Idata_r9" -line 221 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvSelectSignal -win $_nWave3 {( "G4" 25 )} +srcDeselectAll -win $_nTrace1 +srcSelect -signal "Nco_Cos" -line 222 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "Env_Qdata_r7" -line 180 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcSelect -signal "Env_Idata_r7" -line 131 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvSelectSignal -win $_nWave3 {( "G4" 28 )} +wvSetPosition -win $_nWave3 {("G4" 28)} +wvSetPosition -win $_nWave3 {("G4" 29)} +wvSetPosition -win $_nWave3 {("G4" 30)} +wvSetPosition -win $_nWave3 {("G4" 31)} +wvMoveSelected -win $_nWave3 +wvSetPosition -win $_nWave3 {("G4" 31)} +wvSetPosition -win $_nWave3 {("G4" 31)} +wvSetPosition -win $_nWave3 {("G4" 31)} +wvSetPosition -win $_nWave3 {("G4" 31)} +wvSelectSignal -win $_nWave3 {( "G4" 23 )} +wvSelectAll -win $_nWave3 +wvCut -win $_nWave3 +wvSetPosition -win $_nWave3 {("G4" 0)} +wvSetPosition -win $_nWave3 {("G4" 0)} +wvSetPosition -win $_nWave3 {("G4" 0)} +wvSetPosition -win $_nWave3 {("G4" 0)} +srcSelect -signal "mult_isin_tmp" -line 205 -pos 1 -win $_nTrace1 +srcSelect -signal "Nco_Sin" -line 203 -pos 1 -win $_nTrace1 +srcSelect -signal "Env_Idata_r9" -line 202 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvCut -win $_nWave3 +wvSetPosition -win $_nWave3 {("G4" 0)} +wvSetPosition -win $_nWave3 {("G4" 0)} +wvSetPosition -win $_nWave3 {("G4" 0)} +wvSetPosition -win $_nWave3 {("G4" 0)} +srcDeselectAll -win $_nTrace1 +srcSelect -signal "mult_isin_tmp" -line 205 -pos 1 -win $_nTrace1 +srcSelect -signal "Nco_Sin" -line 203 -pos 1 -win $_nTrace1 +srcSelect -signal "Env_Idata_r9" -line 202 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvSelectSignal -win $_nWave3 {( "G4" 3 )} +wvSetCursor -win $_nWave3 1745229.935031 -snap {("G4" 1)} +wvSelectAll -win $_nWave3 +wvSetCursor -win $_nWave3 1744886.980730 -snap {("G4" 0)} +srcDeselectAll -win $_nTrace1 +srcSelect -signal "Env_Idata_r9" -line 202 -pos 1 -win $_nTrace1 +srcSelect -signal "Nco_Sin" -line 203 -pos 1 -win $_nTrace1 +srcSelect -signal "mult_isin_tmp" -line 205 -pos 1 -win $_nTrace1 +wvSetCursor -win $_nWave3 1745094.406102 -snap {("G3" 0)} +wvSetCursor -win $_nWave3 1745096.885290 -snap {("G4" 2)} +srcDeselectAll -win $_nTrace1 +srcSelect -signal "Env_Qdata_r7" -line 180 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvSelectSignal -win $_nWave3 {( "G4" 4 )} +wvCut -win $_nWave3 +wvSetPosition -win $_nWave3 {("G5" 0)} +wvSetPosition -win $_nWave3 {("G4" 3)} +wvSetPosition -win $_nWave3 {("G4" 3)} +wvSetPosition -win $_nWave3 {("G4" 3)} +wvSetPosition -win $_nWave3 {("G4" 3)} +srcDeselectAll -win $_nTrace1 +srcSelect -signal "Env_Idata_r7" -line 120 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvSelectSignal -win $_nWave3 {( "G4" 2 )} +wvSetPosition -win $_nWave3 {("G4" 2)} +wvSetPosition -win $_nWave3 {("G4" 3)} +wvSetPosition -win $_nWave3 {("G4" 4)} +wvSetPosition -win $_nWave3 {("G5" 0)} +wvSetPosition -win $_nWave3 {("G4" 4)} +wvMoveSelected -win $_nWave3 +wvSetPosition -win $_nWave3 {("G4" 4)} +wvSetPosition -win $_nWave3 {("G4" 4)} +wvSetPosition -win $_nWave3 {("G4" 4)} +wvSetPosition -win $_nWave3 {("G4" 4)} +wvSetCursor -win $_nWave3 1745100.190874 -snap {("G4" 3)} +wvSelectSignal -win $_nWave3 {( "G4" 2 )} +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.U_ampmod" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U0_channel_top.U_awg_top.U_ampmod" \ + -delim "." +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.U_ampmod" -win $_nTrace1 +srcSelect -signal "Mod_Data_I" -line 7 -pos 1 -win $_nTrace1 +srcSelect -signal "Mod_Data_Q" -line 8 -pos 1 -win $_nTrace1 +srcSelect -signal "Mod_Vld" -line 9 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "Amod_Data_I" -line 14 -pos 1 -win $_nTrace1 +srcSelect -signal "Amod_Data_Q" -line 15 -pos 1 -win $_nTrace1 +srcSelect -signal "Amod_Vld" -line 16 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvSetCursor -win $_nWave3 1744786.160430 -snap {("G4" 7)} +wvSetCursor -win $_nWave3 1744816.737078 -snap {("G4" 5)} +wvSetCursor -win $_nWave3 1744848.140123 -snap {("G4" 5)} +wvSetCursor -win $_nWave3 1744879.543167 -snap {("G4" 5)} +srcDeselectAll -win $_nTrace1 +srcSelect -win $_nTrace1 -range {41 41 8 9 1 1} +srcDeselectAll -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -win $_nTrace1 -range {48 48 8 9 1 2} -backward +srcDeselectAll -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -win $_nTrace1 -range {40 40 8 9 2 1} -backward +srcDeselectAll -win $_nTrace1 +srcSelect -win $_nTrace1 -range {41 41 7 9 1 3} -backward +srcDeselectAll -win $_nTrace1 +srcSelect -inst "inst_I_Amp" -line 45 -pos 1 -win $_nTrace1 +srcAction -pos 44 3 6 -win $_nTrace1 -name "inst_I_Amp" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -signal "num_stages" -line 87 -pos 1 -win $_nTrace1 +srcSearchString "num_stages" -win $_nTrace1 -next -case +srcSearchString "num_stages" -win $_nTrace1 -next -case +srcSearchString "num_stages" -win $_nTrace1 -next -case +srcSearchString "num_stages" -win $_nTrace1 -next -case +srcDeselectAll -win $_nTrace1 +srcSelect -signal "a_reg\[0\]" -line 136 -pos 2 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "a" -line 136 -pos 1 -win $_nTrace1 +wvSelectSignal -win $_nWave3 {( "G4" 7 )} +wvSelectAll -win $_nWave3 +wvCut -win $_nWave3 +wvSetPosition -win $_nWave3 {("G4" 0)} +wvSetPosition -win $_nWave3 {("G4" 0)} +wvSetPosition -win $_nWave3 {("G4" 0)} +wvSetPosition -win $_nWave3 {("G4" 0)} +srcShowCalling -win $_nTrace1 +srcSelect -win $_nTrace1 -range {45 45 4 5 1 1} +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.U_ampmod" -win $_nTrace1 +srcShowCalling -win $_nTrace1 +srcSelect -win $_nTrace1 -range {342 342 3 4 1 1} +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top" -win $_nTrace1 +srcSelect -signal "enve_vld" -line 347 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "Amod_Vld" -line 352 -pos 2 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "vld" -line 377 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "fmod_vld" -line 384 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -inst "U_freqmod" -line 372 -pos 1 -win $_nTrace1 +srcAction -pos 371 2 4 -win $_nTrace1 -name "U_freqmod" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -signal "Env_Idata_r6" -line 130 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "Nco_Sin" -line 203 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvSetCursor -win $_nWave3 1745076.225392 -snap {("G4" 5)} +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.U_modout_mux" -win \ + $_nTrace1 +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.U_mod_nco" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U0_channel_top.U_awg_top.U_mod_nco" \ + -delim "." +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.U_mod_nco" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "cos" -line 9 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "sin" -line 11 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "fcw" -line 6 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvSetCursor -win $_nWave3 1744783.681242 -snap {("G4" 9)} +srcDeselectAll -win $_nTrace1 +srcSelect -signal "clk" -line 2 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvSetCursor -win $_nWave3 1744817.563474 -snap {("G4" 10)} +wvSetCursor -win $_nWave3 1744847.313727 -snap {("G4" 10)} +wvSetCursor -win $_nWave3 1744876.237583 -snap {("G4" 10)} +wvSetCursor -win $_nWave3 1744912.599003 -snap {("G4" 9)} +wvSetCursor -win $_nWave3 1744945.654839 -snap {("G4" 10)} +wvSetCursor -win $_nWave3 1744976.231488 -snap {("G4" 10)} +wvSetCursor -win $_nWave3 1745008.460928 -snap {("G4" 10)} +wvSetCursor -win $_nWave3 1745042.343160 -snap {("G4" 10)} +wvSetCursor -win $_nWave3 1745073.746205 -snap {("G4" 10)} +wvSetCursor -win $_nWave3 1745104.322853 -snap {("G4" 10)} +wvSetCursor -win $_nWave3 1745069.614225 -snap {("G4" 10)} +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 1698137.660160 1819575.406080 +wvZoom -win $_nWave3 1742154.172373 1754335.312426 +wvZoom -win $_nWave3 1744725.329935 1746194.562827 +wvZoom -win $_nWave3 1744998.381216 1745263.295208 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.U_awg_ctrl" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U0_channel_top.U_awg_top.U_awg_ctrl" \ + -delim "." +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.U_awg_ctrl" -win $_nTrace1 +wvSelectSignal -win $_nWave3 {( "G4" 9 )} +wvSelectAll -win $_nWave3 +wvCut -win $_nWave3 +wvSetPosition -win $_nWave3 {("G4" 0)} +wvSetPosition -win $_nWave3 {("G4" 0)} +wvSetPosition -win $_nWave3 {("G4" 0)} +wvSetPosition -win $_nWave3 {("G4" 0)} +srcDeselectAll -win $_nTrace1 +srcSelect -signal "enve_index_vld_i" -line 88 -pos 1 -win $_nTrace1 +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U0_channel_top.U_awg_top" -delim "." +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "send" -line 49 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvSetCursor -win $_nWave3 1744622.855443 -snap {("G4" 1)} +srcDeselectAll -win $_nTrace1 +srcSelect -signal "enve_vld" -line 257 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "clk" -line 245 -pos 2 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvSetCursor -win $_nWave3 1744655.460242 -snap {("G4" 3)} +wvSetCursor -win $_nWave3 1744685.456657 -snap {("G4" 3)} +wvSetCursor -win $_nWave3 1744718.061456 -snap {("G4" 3)} +wvSetCursor -win $_nWave3 1744754.578831 -snap {("G4" 3)} +wvSetCursor -win $_nWave3 1744791.096206 -snap {("G4" 3)} +srcDeselectAll -win $_nTrace1 +srcSelect -signal "mod_nco_fcw_i" -line 261 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvSetCursor -win $_nWave3 1744655.460242 -snap {("G4" 3)} +wvSetCursor -win $_nWave3 1744686.760849 -snap {("G4" 3)} +wvSetCursor -win $_nWave3 1744659.372818 -snap {("G4" 3)} +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.U_codeword_decode" -win \ + $_nTrace1 +srcSetScope -win $_nTrace1 \ + "TB.U_digital_top.U0_channel_top.U_awg_top.U_codeword_decode" \ + -delim "." +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.U_codeword_decode" -win \ + $_nTrace1 +wvSelectSignal -win $_nWave3 {( "G4" 3 )} +wvSelectAll -win $_nWave3 +wvCut -win $_nWave3 +wvSetPosition -win $_nWave3 {("G4" 0)} +wvSetPosition -win $_nWave3 {("G4" 0)} +wvSetPosition -win $_nWave3 {("G4" 0)} +wvSetPosition -win $_nWave3 {("G4" 0)} +srcDeselectAll -win $_nTrace1 +srcSelect -signal "sendc_i" -line 42 -pos 1 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "send_i" -line 41 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "index_vld_o" -line 58 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.ampr_lut" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U0_channel_top.U_awg_top.ampr_lut" \ + -delim "." +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.ampr_lut" -win $_nTrace1 +srcSelect -signal "index_vld_i" -line 61 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcSelect -signal "param_o" -line 62 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvSetCursor -win $_nWave3 1744684.152465 -snap {("G4" 5)} +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.U_freqmod.inst_icos_mult" \ + -win $_nTrace1 +srcSetScope -win $_nTrace1 \ + "TB.U_digital_top.U0_channel_top.U_awg_top.U_freqmod.inst_icos_mult" \ + -delim "." +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.U_freqmod.inst_icos_mult" \ + -win $_nTrace1 +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.U_freqmod" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U0_channel_top.U_awg_top.U_freqmod" \ + -delim "." +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.U_freqmod" -win $_nTrace1 +wvSetCursor -win $_nWave3 1744626.768019 -snap {("G4" 1)} +srcDeselectAll -win $_nTrace1 +srcSelect -inst "inst_qcos_mult" -line 253 -pos 1 -win $_nTrace1 +srcAction -pos 252 3 9 -win $_nTrace1 -name "inst_qcos_mult" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -signal "en" -line 136 -pos 1 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -win $_nTrace1 -range {60 61 1 1 42 1} +srcDeselectAll -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -win $_nTrace1 -range {59 60 1 1 49 40} -backward +srcDeselectAll -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -win $_nTrace1 -range {60 61 1 1 41 1} +srcDeselectAll -win $_nTrace1 +srcSelect -win $_nTrace1 -range {32 32 1 1 8 42} +srcDeselectAll -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -win $_nTrace1 -range {33 34 1 1 40 1} +srcDeselectAll -win $_nTrace1 +srcSelect -win $_nTrace1 -range {87 87 10 11 1 1} +wvSelectSignal -win $_nWave3 {( "G4" 2 )} +wvSelectAll -win $_nWave3 +wvCut -win $_nWave3 +wvSetPosition -win $_nWave3 {("G4" 0)} +wvSetPosition -win $_nWave3 {("G4" 0)} +wvSetPosition -win $_nWave3 {("G4" 0)} +wvSetPosition -win $_nWave3 {("G4" 0)} +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.U_freqmod.inst_isin_mult" \ + -win $_nTrace1 +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.U_freqmod" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U0_channel_top.U_awg_top.U_freqmod" \ + -delim "." +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.U_freqmod" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +debReload +srcDeselectAll -win $_nTrace1 +srcSelect -signal "Nco_Sin" -line 203 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "mult_isin_tmp" -line 205 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "Nco_Cos" -line 222 -pos 1 -win $_nTrace1 +srcSelect -win $_nTrace1 -range {222 224 8 8 6 8} +srcDeselectAll -win $_nTrace1 +srcSelect -signal "mult_icos_tmp" -line 224 -pos 1 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "Nco_Cos" -line 222 -pos 1 -win $_nTrace1 +srcSelect -signal "mult_icos_tmp" -line 224 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "Nco_Sin" -line 240 -pos 1 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "mult_qsin_tmp" -line 242 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvSelectGroup -win $_nWave3 {G5} +wvSelectSignal -win $_nWave3 {( "G4" 5 )} +wvCut -win $_nWave3 +wvSetPosition -win $_nWave3 {("G5" 0)} +wvSetPosition -win $_nWave3 {("G4" 4)} +wvSetPosition -win $_nWave3 {("G4" 4)} +wvSetPosition -win $_nWave3 {("G4" 4)} +wvSetPosition -win $_nWave3 {("G4" 4)} +wvSelectSignal -win $_nWave3 {( "G4" 2 )} +srcDeselectAll -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +debReload +srcDeselectAll -win $_nTrace1 +srcSelect -word -line 200 -pos 3 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +debReload +srcDeselectAll -win $_nTrace1 +srcSelect -inst "inst_isin_mult" -line 198 -pos 1 -win $_nTrace1 +srcAction -pos 197 3 3 -win $_nTrace1 -name "inst_isin_mult" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -signal "en" -line 98 -pos 1 -win $_nTrace1 +srcSearchString "en" -win $_nTrace1 -next -case +srcSearchString "en" -win $_nTrace1 -next -case +srcDeselectAll -win $_nTrace1 +srcSelect -signal "a_reg\[0\]" -line 136 -pos 2 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "a" -line 136 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "a_reg\[0\]" -line 136 -pos 2 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "stall_mode" -line 114 -pos 1 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -win $_nTrace1 -range {37 38 1 1 48 1} +srcDeselectAll -win $_nTrace1 +srcSelect -win $_nTrace1 -range {38 38 1 2 49 1} +srcDeselectAll -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -win $_nTrace1 -range {38 39 1 1 48 1} +srcDeselectAll -win $_nTrace1 +srcAction -pos 45 0 13 -win $_nTrace1 -name \ + "// op_iso_mode 0 to 4 default: 0" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -win $_nTrace1 -range {49 50 1 1 57 1} +srcDeselectAll -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -win $_nTrace1 -range {50 50 1 2 47 1} +srcDeselectAll -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -win $_nTrace1 -range {51 51 1 2 46 1} +srcDeselectAll -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -win $_nTrace1 -range {52 53 1 1 47 1} +srcDeselectAll -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -win $_nTrace1 -range {53 53 1 1 45 54} +srcDeselectAll -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -win $_nTrace1 -range {53 53 1 2 74 1} +srcDeselectAll -win $_nTrace1 +srcShowCalling -win $_nTrace1 +srcSelect -win $_nTrace1 -range {198 198 4 5 1 1} +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.U_freqmod" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -inst "inst_isin_mult" -line 198 -pos 1 -win $_nTrace1 +srcAction -pos 197 3 9 -win $_nTrace1 -name "inst_isin_mult" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -win $_nTrace1 -range {49 49 1 1 72 73} +srcDeselectAll -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -win $_nTrace1 -range {48 48 1 1 44 60} +srcDeselectAll -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -win $_nTrace1 -range {48 49 1 1 64 1} +srcDeselectAll -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -win $_nTrace1 -range {42 43 1 2 38 1} -backward +srcDeselectAll -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -win $_nTrace1 -range {42 44 1 1 33 1} -backward +srcDeselectAll -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcAction -pos 37 0 52 -win $_nTrace1 -name \ + "// 1 => stallable" -ctrlKey \ + off +srcDeselectAll -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -win $_nTrace1 -range {37 38 1 1 48 1} +srcDeselectAll -win $_nTrace1 +srcSelect -signal "product" -line 283 -pos 1 -win $_nTrace1 +srcShowCalling -win $_nTrace1 +srcSelect -win $_nTrace1 -range {198 198 4 5 1 1} +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.U_freqmod" -win $_nTrace1 +wvSelectSignal -win $_nWave3 {( "G4" 5 )} +wvSelectAll -win $_nWave3 +wvCut -win $_nWave3 +wvSetPosition -win $_nWave3 {("G4" 0)} +wvSetPosition -win $_nWave3 {("G4" 0)} +wvSetPosition -win $_nWave3 {("G4" 0)} +wvSetPosition -win $_nWave3 {("G4" 0)} +srcDeselectAll -win $_nTrace1 +srcSelect -signal "mult_isin_tmp" -line 205 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "Nco_Sin" -line 203 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "Env_Idata_r9" -line 202 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvSelectSignal -win $_nWave3 {( "G4" 3 )} +wvCut -win $_nWave3 +wvSetPosition -win $_nWave3 {("G5" 0)} +wvSetPosition -win $_nWave3 {("G4" 2)} +wvSetPosition -win $_nWave3 {("G4" 2)} +wvSetPosition -win $_nWave3 {("G4" 2)} +wvSetPosition -win $_nWave3 {("G4" 2)} +srcDeselectAll -win $_nTrace1 +srcSelect -signal "adder1_isinqcos_r" -line 350 -pos 1 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "mult_icos_r" -line 289 -pos 1 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "mult_qcos_tmp" -line 260 -pos 1 -win $_nTrace1 +srcAction -pos 259 7 6 -win $_nTrace1 -name "mult_qcos_tmp" -ctrlKey off +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.bais_lut" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U0_channel_top.U_awg_top.bais_lut" \ + -delim "." +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.bais_lut" -win $_nTrace1 +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.U_baisset" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U0_channel_top.U_awg_top.U_baisset" \ + -delim "." +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.U_baisset" -win $_nTrace1 +wvSelectSignal -win $_nWave3 {( "G4" 2 )} +wvSelectAll -win $_nWave3 +wvCut -win $_nWave3 +wvSetPosition -win $_nWave3 {("G4" 0)} +wvSetPosition -win $_nWave3 {("G4" 0)} +wvSetPosition -win $_nWave3 {("G4" 0)} +wvSetPosition -win $_nWave3 {("G4" 0)} +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U0_channel_top.U_awg_top" -delim "." +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "send" -line 49 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "awg_vld" -line 83 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "clk" -line 36 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvSetCursor -win $_nWave3 1744655.460242 -snap {("G4" 3)} +wvSetCursor -win $_nWave3 1744685.456657 -snap {("G4" 3)} +wvSetCursor -win $_nWave3 1744720.669840 -snap {("G4" 2)} +wvSetCursor -win $_nWave3 1744748.057872 -snap {("G4" 2)} +wvSetCursor -win $_nWave3 1744780.662671 -snap {("G4" 3)} +wvSetCursor -win $_nWave3 1744818.484237 -snap {("G4" 3)} +wvSetCursor -win $_nWave3 1744847.176461 -snap {("G4" 2)} +wvSetCursor -win $_nWave3 1744883.693836 -snap {("G4" 3)} +wvSetCursor -win $_nWave3 1744913.690251 -snap {("G4" 3)} +wvSetCursor -win $_nWave3 1744939.774090 -snap {("G4" 3)} +wvSetCursor -win $_nWave3 1744972.378889 -snap {("G4" 3)} +wvSetCursor -win $_nWave3 1745010.200456 -snap {("G4" 3)} +wvSetCursor -win $_nWave3 1745042.805255 -snap {("G4" 3)} +wvSetCursor -win $_nWave3 1745074.105862 -snap {("G4" 3)} +wvSetCursor -win $_nWave3 1745102.798085 -snap {("G4" 3)} +wvSetCursor -win $_nWave3 1745136.707076 -snap {("G4" 3)} +wvSetCursor -win $_nWave3 1745162.790916 -snap {("G4" 3)} +wvSetCursor -win $_nWave3 1745198.004099 -snap {("G4" 3)} +wvSetCursor -win $_nWave3 1745233.217282 -snap {("G4" 3)} +wvSetCursor -win $_nWave3 1745267.126273 -snap {("G4" 3)} +wvSetCursor -win $_nWave3 1745294.514304 -snap {("G4" 3)} +wvSetCursor -win $_nWave3 1745334.944255 -snap {("G4" 3)} +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.U_codeword_decode" -win \ + $_nTrace1 +srcSetScope -win $_nTrace1 \ + "TB.U_digital_top.U0_channel_top.U_awg_top.U_codeword_decode" \ + -delim "." +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.U_codeword_decode" -win \ + $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "send_i" -line 41 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "index_vld_o" -line 58 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.ampr_lut" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U0_channel_top.U_awg_top.ampr_lut" \ + -delim "." +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.ampr_lut" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "index_vld_i" -line 61 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "param_o" -line 62 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvSetCursor -win $_nWave3 1744695.890193 -snap {("G4" 6)} +wvSetCursor -win $_nWave3 1744630.680595 -snap {("G4" 4)} +wvSetCursor -win $_nWave3 1744654.156050 -snap {("G4" 5)} +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.U_awg_ctrl" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U0_channel_top.U_awg_top.U_awg_ctrl" \ + -delim "." +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.U_awg_ctrl" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "muc_mod_nco_fcw_i" -line 108 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvSetCursor -win $_nWave3 1744707.627921 -snap {("G4" 8)} +wvSetCursor -win $_nWave3 1744660.677010 -snap {("G4" 6)} +srcDeselectAll -win $_nTrace1 +srcSelect -signal "mod_nco_fcw_o" -line 113 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvSetCursor -win $_nWave3 1744689.369233 -snap {("G4" 8)} +wvSetCursor -win $_nWave3 1744719.365648 -snap {("G4" 3)} +wvSetCursor -win $_nWave3 1744751.970447 -snap {("G4" 3)} +wvSetCursor -win $_nWave3 1744785.879438 -snap {("G4" 3)} +wvSetCursor -win $_nWave3 1744661.981202 -snap {("G4" 3)} +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.U_mod_nco" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U0_channel_top.U_awg_top.U_mod_nco" \ + -delim "." +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.U_mod_nco" -win $_nTrace1 +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.U_freqmod" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U0_channel_top.U_awg_top.U_freqmod" \ + -delim "." +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.U_freqmod" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "Env_Idata_r4" -line 105 -pos 1 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "Env_Idata_r6" -line 107 -pos 1 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "Env_Idata_r4" -line 105 -pos 1 -win $_nTrace1 +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.U_ampmod" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U0_channel_top.U_awg_top.U_ampmod" \ + -delim "." +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.U_ampmod" -win $_nTrace1 +wvSelectSignal -win $_nWave3 {( "G4" 3 )} +wvSelectAll -win $_nWave3 +wvCut -win $_nWave3 +wvSetPosition -win $_nWave3 {("G4" 0)} +wvSetPosition -win $_nWave3 {("G4" 0)} +wvSetPosition -win $_nWave3 {("G4" 0)} +wvSetPosition -win $_nWave3 {("G4" 0)} +srcDeselectAll -win $_nTrace1 +srcSelect -signal "Mod_Vld" -line 9 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "Amod_Vld" -line 16 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "Dig_Clk" -line 4 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvSetCursor -win $_nWave3 1744813.267470 -snap {("G4" 3)} +wvSetCursor -win $_nWave3 1744845.872269 -snap {("G4" 3)} +wvSetCursor -win $_nWave3 1744879.781260 -snap {("G4" 3)} +wvSelectSignal -win $_nWave3 {( "G4" 2 )} +wvSelectSignal -win $_nWave3 {( "G4" 1 2 )} +wvSelectSignal -win $_nWave3 {( "G4" 1 2 3 )} +wvCut -win $_nWave3 +wvSetPosition -win $_nWave3 {("G4" 0)} +wvSetPosition -win $_nWave3 {("G4" 0)} +wvSetPosition -win $_nWave3 {("G4" 0)} +wvSetPosition -win $_nWave3 {("G4" 0)} +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.U_freqmod" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U0_channel_top.U_awg_top.U_freqmod" \ + -delim "." +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.U_freqmod" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "Nco_Sin" -line 203 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvZoom -win $_nWave3 1745054.542983 1745277.559808 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvSetCursor -win $_nWave3 1745103.194961 -snap {("G4" 1)} +srcDeselectAll -win $_nTrace1 +srcSelect -signal "Env_Idata_r9" -line 202 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvSetCursor -win $_nWave3 1745164.678984 -snap {("G4" 2)} +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.U_mod_nco" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U0_channel_top.U_awg_top.U_mod_nco" \ + -delim "." +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.U_mod_nco" -win $_nTrace1 +srcSelect -signal "fcw" -line 46 -pos 2 -win $_nTrace1 +srcSelect -signal "pha" -line 39 -pos 2 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvSetCursor -win $_nWave3 1744784.795554 -snap {("G4" 3)} +wvSetCursor -win $_nWave3 1744913.253246 -snap {("G4" 1)} +wvSetCursor -win $_nWave3 1745088.372919 -snap {("G4" 1)} +wvSelectSignal -win $_nWave3 {( "G4" 2 )} +wvSelectSignal -win $_nWave3 {( "G4" 2 )} +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.U_freqmod" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U0_channel_top.U_awg_top.U_freqmod" \ + -delim "." +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.U_freqmod" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "Env_Vld" -line 40 -pos 1 -win $_nTrace1 +srcSelect -signal "Env_Idata" -line 38 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvSelectAll -win $_nWave3 +wvCut -win $_nWave3 +wvSetPosition -win $_nWave3 {("G4" 0)} +wvSetPosition -win $_nWave3 {("G4" 0)} +wvSetPosition -win $_nWave3 {("G4" 0)} +wvSetPosition -win $_nWave3 {("G4" 0)} +srcDeselectAll -win $_nTrace1 +debReload +srcDeselectAll -win $_nTrace1 +srcSelect -signal "Env_Idata_r6" -line 202 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "Nco_Sin" -line 203 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "mult_isin_tmp" -line 205 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvSetCursor -win $_nWave3 1745137.230760 -snap {("G4" 3)} +srcDeselectAll -win $_nTrace1 +srcSelect -signal "Env_Vld" -line 40 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "Mod_Vld" -line 372 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "Mod_Data_I" -line 357 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "freqmod_data_vld_dly\[11:0\]" -line 368 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvSelectSignal -win $_nWave3 {( "G4" 7 )} +wvExpandBus -win $_nWave3 {("G4" 7)} +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvSelectSignal -win $_nWave3 {( "G4" 12 )} +wvSetPosition -win $_nWave3 {("G4" 12)} +wvSetPosition -win $_nWave3 {("G4" 11)} +wvSetPosition -win $_nWave3 {("G4" 10)} +wvSetPosition -win $_nWave3 {("G4" 9)} +wvSetPosition -win $_nWave3 {("G4" 8)} +wvSetPosition -win $_nWave3 {("G4" 7)} +wvSetPosition -win $_nWave3 {("G4" 6)} +wvSetPosition -win $_nWave3 {("G4" 5)} +wvSetPosition -win $_nWave3 {("G4" 4)} +wvSetPosition -win $_nWave3 {("G4" 3)} +wvMoveSelected -win $_nWave3 +wvSetPosition -win $_nWave3 {("G4" 3)} +wvSetPosition -win $_nWave3 {("G4" 4)} +wvSetPosition -win $_nWave3 {("G4" 4)} +wvSetPosition -win $_nWave3 {("G4" 4)} +wvSetPosition -win $_nWave3 {("G4" 4)} +wvSetCursor -win $_nWave3 1745102.097032 -snap {("G4" 3)} +wvScrollDown -win $_nWave3 0 +wvSelectSignal -win $_nWave3 {( "G4" 4 )} +wvSetCursor -win $_nWave3 1744878.668483 -snap {("G4" 5)} +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "Dig_Clk" -line 342 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvSetCursor -win $_nWave3 1744909.959459 -snap {("G4" 5)} +wvSetCursor -win $_nWave3 1744941.250435 -snap {("G4" 5)} +wvSetCursor -win $_nWave3 1744975.835198 -snap {("G4" 5)} +wvSetCursor -win $_nWave3 1745012.066855 -snap {("G4" 5)} +wvSetCursor -win $_nWave3 1745040.064044 -snap {("G4" 5)} +wvSetCursor -win $_nWave3 1745075.197772 -snap {("G4" 5)} +wvSetCursor -win $_nWave3 1745105.939783 -snap {("G4" 5)} +wvSetCursor -win $_nWave3 1745139.975582 -snap {("G4" 5)} +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U0_channel_top.U_awg_top" -delim "." +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "send" -line 49 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomIn -win $_nWave3 +wvSetCursor -win $_nWave3 1744688.177803 -snap {("G4" 5)} +wvSetCursor -win $_nWave3 1744718.919815 -snap {("G4" 5)} +wvSetCursor -win $_nWave3 1744752.955613 -snap {("G4" 5)} +wvSetCursor -win $_nWave3 1744784.795554 -snap {("G4" 5)} +wvSetCursor -win $_nWave3 1744818.831353 -snap {("G4" 5)} +wvSetCursor -win $_nWave3 1744849.573364 -snap {("G4" 5)} +wvSetCursor -win $_nWave3 1744882.511234 -snap {("G4" 5)} +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.U_awg_ctrl" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U0_channel_top.U_awg_top.U_awg_ctrl" \ + -delim "." +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.U_awg_ctrl" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "wave_hold_i" -line 91 -pos 1 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "intp_sel_i" -line 92 -pos 1 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "enve_index_vld_i" -line 88 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvSetCursor -win $_nWave3 1744687.628838 -snap {("G4" 7)} +srcDeselectAll -win $_nTrace1 +srcSelect -signal "enve_vld_o" -line 100 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvSetCursor -win $_nWave3 1744721.115673 -snap {("G4" 5)} +wvSetCursor -win $_nWave3 1744750.210791 -snap {("G4" 5)} +wvSetCursor -win $_nWave3 1744782.599696 -snap {("G4" 5)} +verdiDockWidgetMaximize -dock windowDock_nWave_3 +wvSelectSignal -win $_nWave3 {( "G4" 17 )} +wvSelectAll -win $_nWave3 +wvCut -win $_nWave3 +wvSetPosition -win $_nWave3 {("G4" 0)} +wvSetPosition -win $_nWave3 {("G4" 0)} +wvSetPosition -win $_nWave3 {("G4" 0)} +wvSetPosition -win $_nWave3 {("G4" 0)} +verdiDockWidgetRestore -dock windowDock_nWave_3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "muc_mod_nco_fcw_i" -line 108 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "enve_index_vld_i" -line 88 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "muc_mod_nco_pha_i" -line 109 -pos 1 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "mod_nco_pha_o" -line 114 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 1688183.746560 1980828.806400 +wvZoom -win $_nWave3 1738248.562951 1758238.471654 +wvZoom -win $_nWave3 1744177.877409 1745875.481964 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "muc_mod_nco_fcw_i" -line 108 -pos 1 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "muc_mod_nco_pha_i" -line 109 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "muc_mod_nco_rz_pha_i" -line 110 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "muc_mod_pha_clr_i" -line 111 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "ilde2read_r\[0\]" -line 262 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvSetCursor -win $_nWave3 1744717.976827 -snap {("G4" 7)} +srcDeselectAll -win $_nTrace1 +srcSelect -signal "mod_nco_pha_o" -line 264 -pos 1 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "ilde2read_r\[1\]" -line 253 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "mod_nco_fcw_o" -line 253 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "muc_mod_nco_rz_pha_i" -line 264 -pos 1 -win $_nTrace1 +debReload +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 1733393.126256 1781264.530027 +wvZoom -win $_nWave3 1742172.005224 1751510.611375 +wvZoom -win $_nWave3 1743453.549329 1746010.890705 +wvZoomOut -win $_nWave3 +debReload +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 1767735.128000 1907794.141988 +wvZoom -win $_nWave3 1808503.074841 1826258.248306 +wvSelectSignal -win $_nWave3 {( "G4" 5 )} +wvZoom -win $_nWave3 1814337.697997 1818238.373029 +wvSelectSignal -win $_nWave3 {( "G4" 3 )} +wvSetCursor -win $_nWave3 1815405.882852 -snap {("G4" 2)} +wvSetCursor -win $_nWave3 1815453.891160 -snap {("G4" 7)} +wvSetCursor -win $_nWave3 1815504.299884 -snap {("G4" 9)} +wvSelectSignal -win $_nWave3 {( "G4" 4 )} +wvSetCursor -win $_nWave3 1815405.882852 -snap {("G4" 4)} +wvSelectSignal -win $_nWave3 {( "G4" 5 )} +srcDeselectAll -win $_nTrace1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvSelectSignal -win $_nWave3 {( "G4" 2 )} +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 1814641.350546 1817589.060662 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "enve_start_addr_i" -line 89 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "enve_len_i" -line 90 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvSelectSignal -win $_nWave3 {( "G4" 5 )} +srcDeselectAll -win $_nTrace1 +srcSelect -signal "cnt_c" -line 142 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvSetCursor -win $_nWave3 1815762.387377 -snap {("G4" 12)} +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvSelectSignal -win $_nWave3 {( "G4" 5 )} +wvSetCursor -win $_nWave3 1818868.820346 -snap {("G4" 5)} +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomOut -win $_nWave3 +wvSetCursor -win $_nWave3 1815414.104089 -snap {("G4" 2)} +srcDeselectAll -win $_nTrace1 +debReload +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvSelectSignal -win $_nWave3 {( "G4" 7 )} +wvScrollUp -win $_nWave3 1 +wvSelectSignal -win $_nWave3 {( "G4" 2 )} +wvSelectSignal -win $_nWave3 {( "G4" 3 )} +wvSetCursor -win $_nWave3 1815434.057820 -snap {("G4" 3)} +wvScrollDown -win $_nWave3 0 +wvSelectSignal -win $_nWave3 {( "G4" 9 )} +wvSetPosition -win $_nWave3 {("G4" 9)} +wvSetPosition -win $_nWave3 {("G4" 8)} +wvSetPosition -win $_nWave3 {("G4" 7)} +wvSetPosition -win $_nWave3 {("G4" 6)} +wvSetPosition -win $_nWave3 {("G4" 5)} +wvSetPosition -win $_nWave3 {("G4" 4)} +wvSetPosition -win $_nWave3 {("G4" 3)} +wvMoveSelected -win $_nWave3 +wvSetPosition -win $_nWave3 {("G4" 3)} +wvSetPosition -win $_nWave3 {("G4" 4)} +wvSetPosition -win $_nWave3 {("G4" 4)} +wvSetPosition -win $_nWave3 {("G4" 4)} +wvSetPosition -win $_nWave3 {("G4" 4)} +wvSelectSignal -win $_nWave3 {( "G4" 8 )} +wvSelectAll -win $_nWave3 +wvCut -win $_nWave3 +wvSetPosition -win $_nWave3 {("G4" 0)} +wvSetPosition -win $_nWave3 {("G4" 0)} +wvSetPosition -win $_nWave3 {("G4" 0)} +wvSetPosition -win $_nWave3 {("G4" 0)} +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.U_freqmod" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U0_channel_top.U_awg_top.U_freqmod" \ + -delim "." +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.U_freqmod" -win $_nTrace1 +srcSelect -signal "Env_Idata_r6" -line 202 -pos 1 -win $_nTrace1 +srcSelect -signal "Nco_Sin" -line 203 -pos 1 -win $_nTrace1 +srcSelect -signal "mult_isin_tmp" -line 205 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvZoom -win $_nWave3 1815658.990777 1816052.623451 +wvZoomOut -win $_nWave3 +wvSelectSignal -win $_nWave3 {( "G4" 2 )} +srcDeselectAll -win $_nTrace1 +srcSelect -signal "Env_Qdata_r2" -line 152 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "Env_Qdata_r4" -line 154 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "Env_Qdata_r3" -line 153 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "Env_Vld" -line 40 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "Env_Idata" -line 38 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvSetCursor -win $_nWave3 1815596.857372 -snap {("G4" 7)} +wvSelectSignal -win $_nWave3 {( "G4" 6 7 8 )} +wvSelectSignal -win $_nWave3 {( "G4" 5 )} +wvSelectSignal -win $_nWave3 {( "G4" 4 )} +wvCut -win $_nWave3 +wvSetPosition -win $_nWave3 {("G5" 0)} +wvSetPosition -win $_nWave3 {("G4" 7)} +wvSetPosition -win $_nWave3 {("G4" 7)} +wvSetPosition -win $_nWave3 {("G4" 7)} +wvSetPosition -win $_nWave3 {("G4" 7)} +wvPaste -win $_nWave3 +wvSetPosition -win $_nWave3 {("G4" 7)} +wvSetPosition -win $_nWave3 {("G4" 8)} +wvSetPosition -win $_nWave3 {("G4" 7)} +wvSetPosition -win $_nWave3 {("G4" 8)} +wvSetPosition -win $_nWave3 {("G4" 8)} +wvSetPosition -win $_nWave3 {("G4" 8)} +wvSetPosition -win $_nWave3 {("G4" 8)} +wvSelectSignal -win $_nWave3 {( "G4" 4 )} +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.U_mod_nco" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U0_channel_top.U_awg_top.U_mod_nco" \ + -delim "." +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.U_mod_nco" -win $_nTrace1 +srcSelect -win $_nTrace1 -range {1 39 3 10 1 2} +srcDeselectAll -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "pha" -line 39 -pos 2 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvScrollDown -win $_nWave3 1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "cos" -line 21 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "sin" -line 22 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "phase_auto_clr" -line 17 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "phase_manual_clr" -line 16 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 1815471.137152 1816013.744653 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "pha" -line 7 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvSelectSignal -win $_nWave3 {( "G4" 7 )} +wvSelectAll -win $_nWave3 +wvCut -win $_nWave3 +wvSetPosition -win $_nWave3 {("G4" 0)} +wvSetPosition -win $_nWave3 {("G4" 0)} +wvSetPosition -win $_nWave3 {("G4" 0)} +wvSetPosition -win $_nWave3 {("G4" 0)} +srcDeselectAll -win $_nTrace1 +srcSelect -signal "pha" -line 7 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "fcw" -line 6 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 1815297.669707 1815612.882927 +wvSetCursor -win $_nWave3 1815440.243071 -snap {("G4" 2)} +srcDeselectAll -win $_nTrace1 +srcSelect -signal "cos" -line 9 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 1815687.661201 1815860.689011 +wvSetCursor -win $_nWave3 1815759.108376 -snap {("G4" 3)} +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.U_freqmod" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U0_channel_top.U_awg_top.U_freqmod" \ + -delim "." +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.U_freqmod" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "Env_Idata_r3" -line 127 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvSelectSignal -win $_nWave3 {( "G4" 4 )} +wvCut -win $_nWave3 +wvSetPosition -win $_nWave3 {("G5" 0)} +wvSetPosition -win $_nWave3 {("G4" 3)} +wvSetPosition -win $_nWave3 {("G4" 3)} +wvSetPosition -win $_nWave3 {("G4" 3)} +wvSetPosition -win $_nWave3 {("G4" 3)} +srcDeselectAll -win $_nTrace1 +srcSelect -signal "Env_Idata_r4" -line 128 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcSelect -signal "Env_Idata" -line 38 -pos 1 -win $_nTrace1 +srcSelect -signal "Env_Vld" -line 40 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvSelectSignal -win $_nWave3 {( "G4" 5 )} +wvSelectSignal -win $_nWave3 {( "G4" 5 6 )} +wvSelectSignal -win $_nWave3 {( "G4" 5 6 7 )} +wvCut -win $_nWave3 +wvSetPosition -win $_nWave3 {("G4" 4)} +wvSetPosition -win $_nWave3 {("G4" 4)} +wvSetPosition -win $_nWave3 {("G4" 4)} +wvSetPosition -win $_nWave3 {("G4" 4)} +srcDeselectAll -win $_nTrace1 +srcSelect -signal "Env_Idata_r5" -line 92 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "Env_Idata_r6" -line 202 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvSetCursor -win $_nWave3 1815758.416264 -snap {("G4" 5)} +wvSetCursor -win $_nWave3 1815758.416264 -snap {("G4" 4)} +srcDeselectAll -win $_nTrace1 +srcSelect -signal "Env_Vld" -line 40 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvSetCursor -win $_nWave3 1815602.531517 -snap {("G4" 7)} +srcDeselectAll -win $_nTrace1 +srcSelect -signal "Dig_Clk" -line 35 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvSetCursor -win $_nWave3 1815436.424819 -snap {("G4" 8)} +wvSetCursor -win $_nWave3 1815469.646159 -snap {("G4" 8)} +wvSetCursor -win $_nWave3 1815502.867498 -snap {("G4" 7)} +wvSetCursor -win $_nWave3 1815534.385179 -snap {("G4" 8)} +wvSetCursor -win $_nWave3 1815564.199202 -snap {("G4" 8)} +wvSetCursor -win $_nWave3 1815597.420542 -snap {("G4" 8)} +wvSelectSignal -win $_nWave3 {( "G4" 3 )} +wvSelectSignal -win $_nWave3 {( "G4" 8 )} +wvSetPosition -win $_nWave3 {("G4" 7)} +wvSetPosition -win $_nWave3 {("G4" 6)} +wvSetPosition -win $_nWave3 {("G4" 2)} +wvSetPosition -win $_nWave3 {("G4" 3)} +wvSetPosition -win $_nWave3 {("G4" 2)} +wvMoveSelected -win $_nWave3 +wvSetPosition -win $_nWave3 {("G4" 2)} +wvSetPosition -win $_nWave3 {("G4" 3)} +wvSetPosition -win $_nWave3 {("G4" 3)} +wvSetPosition -win $_nWave3 {("G4" 3)} +wvSetPosition -win $_nWave3 {("G4" 3)} +wvSetCursor -win $_nWave3 1815470.497988 -snap {("G4" 3)} +wvSetCursor -win $_nWave3 1815503.719328 -snap {("G4" 3)} +wvSetCursor -win $_nWave3 1815533.533350 -snap {("G4" 3)} +wvSetCursor -win $_nWave3 1815565.051031 -snap {("G4" 3)} +wvSetCursor -win $_nWave3 1815597.420542 -snap {("G4" 3)} +wvSetCursor -win $_nWave3 1815628.938223 -snap {("G4" 3)} +wvSetCursor -win $_nWave3 1815663.011392 -snap {("G4" 3)} +wvSetCursor -win $_nWave3 1815699.640048 -snap {("G4" 3)} +wvSetCursor -win $_nWave3 1815727.750412 -snap {("G4" 3)} +wvSetCursor -win $_nWave3 1815759.268093 -snap {("G4" 4)} +wvSetCursor -win $_nWave3 1815596.568713 -snap {("G4" 8)} +wvSetCursor -win $_nWave3 1815628.086394 -snap {("G4" 3)} +wvSetCursor -win $_nWave3 1815660.455904 -snap {("G4" 3)} +wvSetCursor -win $_nWave3 1815696.232731 -snap {("G4" 3)} +wvSetCursor -win $_nWave3 1815727.750412 -snap {("G4" 3)} +wvSetCursor -win $_nWave3 1815762.675410 -snap {("G4" 3)} +srcDeselectAll -win $_nTrace1 +debReload +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 1699107.645260 1777612.226090 +wvZoom -win $_nWave3 1739785.095758 1744181.352284 +wvZoom -win $_nWave3 1740926.769760 1742585.172991 +wvSelectSignal -win $_nWave3 {( "G4" 4 )} +wvSetCursor -win $_nWave3 1741200.278723 -snap {("G4" 2)} +wvSetCursor -win $_nWave3 1741231.915954 -snap {("G4" 3)} +wvSetCursor -win $_nWave3 1741267.635408 -snap {("G4" 3)} +wvSetCursor -win $_nWave3 1741296.210971 -snap {("G4" 3)} +wvSetCursor -win $_nWave3 1741326.827646 -snap {("G4" 3)} +wvSetCursor -win $_nWave3 1741364.588212 -snap {("G4" 3)} +wvSetCursor -win $_nWave3 1741395.204887 -snap {("G4" 3)} +wvSetCursor -win $_nWave3 1741423.780450 -snap {("G4" 3)} +wvSetCursor -win $_nWave3 1741460.520460 -snap {("G4" 3)} +wvSetCursor -win $_nWave3 1741487.054912 -snap {("G4" 3)} +wvSelectSignal -win $_nWave3 {( "G4" 5 )} +srcDeselectAll -win $_nTrace1 +srcSelect -signal "Env_Qdata" -line 39 -pos 1 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "Env_Idata" -line 38 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvScrollDown -win $_nWave3 0 +wvSetPosition -win $_nWave3 {("G4" 5)} +wvSetPosition -win $_nWave3 {("G4" 6)} +wvSetPosition -win $_nWave3 {("G4" 7)} +wvSetPosition -win $_nWave3 {("G4" 8)} +wvSetPosition -win $_nWave3 {("G4" 9)} +wvMoveSelected -win $_nWave3 +wvSetPosition -win $_nWave3 {("G4" 9)} +wvSetPosition -win $_nWave3 {("G4" 9)} +wvSetPosition -win $_nWave3 {("G4" 9)} +wvSetPosition -win $_nWave3 {("G4" 9)} +wvSelectSignal -win $_nWave3 {( "G4" 5 )} +wvSelectSignal -win $_nWave3 {( "G4" 6 )} +wvSelectSignal -win $_nWave3 {( "G4" 5 )} +srcDeselectAll -win $_nTrace1 +debReload +wvSelectSignal -win $_nWave3 {( "G4" 9 )} +wvSelectAll -win $_nWave3 +wvCut -win $_nWave3 +wvSetPosition -win $_nWave3 {("G4" 0)} +wvSetPosition -win $_nWave3 {("G4" 0)} +wvSetPosition -win $_nWave3 {("G4" 0)} +wvSetPosition -win $_nWave3 {("G4" 0)} +srcSelect -signal "Env_Idata" -line 38 -pos 1 -win $_nTrace1 +srcSelect -signal "Env_Qdata" -line 39 -pos 1 -win $_nTrace1 +srcSelect -signal "Env_Vld" -line 40 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "Nco_Cos" -line 43 -pos 1 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "Env_Idata_r4" -line 202 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "Nco_Sin" -line 203 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "mult_isin_tmp" -line 205 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "mult_icos_r" -line 289 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "Mod_Data_I" -line 357 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvSelectSignal -win $_nWave3 {( "G4" 3 )} +wvSelectSignal -win $_nWave3 {( "G4" 4 )} +wvSelectSignal -win $_nWave3 {( "G4" 4 5 )} +wvSetCursor -win $_nWave3 1741550.329375 -snap {("G4" 6)} +wvSetCursor -win $_nWave3 1741581.966606 -snap {("G4" 7)} +srcDeselectAll -win $_nTrace1 +srcSelect -signal "freqmod_data_vld_dly" -line 368 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvSelectSignal -win $_nWave3 {( "G4" 9 )} +wvExpandBus -win $_nWave3 {("G4" 9)} +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvSelectSignal -win $_nWave3 {( "G4" 16 )} +wvSetPosition -win $_nWave3 {("G4" 16)} +wvSetPosition -win $_nWave3 {("G4" 15)} +wvSetPosition -win $_nWave3 {("G4" 14)} +wvSetPosition -win $_nWave3 {("G4" 13)} +wvSetPosition -win $_nWave3 {("G4" 12)} +wvSetPosition -win $_nWave3 {("G4" 11)} +wvSetPosition -win $_nWave3 {("G4" 10)} +wvSetPosition -win $_nWave3 {("G4" 9)} +wvSetPosition -win $_nWave3 {("G4" 8)} +wvMoveSelected -win $_nWave3 +wvSetPosition -win $_nWave3 {("G4" 8)} +wvSetPosition -win $_nWave3 {("G4" 9)} +wvSetPosition -win $_nWave3 {("G4" 9)} +wvSetPosition -win $_nWave3 {("G4" 9)} +wvSetPosition -win $_nWave3 {("G4" 9)} +wvSelectSignal -win $_nWave3 {( "G4" 10 )} +wvScrollDown -win $_nWave3 5 +wvSelectSignal -win $_nWave3 {( "G4" 10 11 12 13 14 15 16 17 18 19 20 21 22 )} \ + +wvCut -win $_nWave3 +wvSetPosition -win $_nWave3 {("G4" 9)} +wvSetPosition -win $_nWave3 {("G4" 9)} +wvSetPosition -win $_nWave3 {("G4" 9)} +wvSetPosition -win $_nWave3 {("G4" 9)} +srcDeselectAll -win $_nTrace1 +srcSelect -signal "freqmod_data_vld_dly\[12\]" -line 372 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvSelectSignal -win $_nWave3 {( "G4" 10 )} +wvCut -win $_nWave3 +wvSetPosition -win $_nWave3 {("G5" 0)} +wvSetPosition -win $_nWave3 {("G4" 9)} +wvSetPosition -win $_nWave3 {("G4" 9)} +wvSetPosition -win $_nWave3 {("G4" 9)} +wvSetPosition -win $_nWave3 {("G4" 9)} +srcDeselectAll -win $_nTrace1 +debReload +wvSetCursor -win $_nWave3 1742224.916781 -snap {("G4" 9)} +wvSetCursor -win $_nWave3 1741585.028273 -snap {("G4" 9)} +wvSetCursor -win $_nWave3 1742221.855114 -snap {("G4" 9)} +wvSetCursor -win $_nWave3 1741580.946050 -snap {("G4" 9)} +wvSetCursor -win $_nWave3 1742219.814002 -snap {("G4" 9)} +wvSetCursor -win $_nWave3 1741584.007717 -snap {("G4" 9)} +wvSetCursor -win $_nWave3 1741358.464878 -snap {("G4" 3)} +srcDeselectAll -win $_nTrace1 +srcSelect -signal "Dig_Clk" -line 284 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvSetCursor -win $_nWave3 1741389.081553 -snap {("G4" 10)} +wvSetCursor -win $_nWave3 1741423.780451 -snap {("G4" 10)} +wvSetCursor -win $_nWave3 1741454.397126 -snap {("G4" 10)} +wvSetCursor -win $_nWave3 1741487.054913 -snap {("G4" 10)} +wvSetCursor -win $_nWave3 1741519.712700 -snap {("G4" 10)} +wvSetCursor -win $_nWave3 1741551.349931 -snap {("G4" 10)} +wvSetCursor -win $_nWave3 1741582.987162 -snap {("G4" 10)} +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U0_channel_top.U_awg_top" -delim "." +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "clk" -line 36 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +srcSelect -signal "awg_data_i" -line 81 -pos 1 -win $_nTrace1 +srcSelect -signal "awg_data_q" -line 82 -pos 1 -win $_nTrace1 +srcSelect -signal "awg_vld" -line 83 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvSelectSignal -win $_nWave3 {( "G4" 3 )} +wvSetPosition -win $_nWave3 {("G4" 3)} +wvSetPosition -win $_nWave3 {("G4" 4)} +wvSetPosition -win $_nWave3 {("G4" 5)} +wvSetPosition -win $_nWave3 {("G4" 6)} +wvSetPosition -win $_nWave3 {("G4" 7)} +wvSetPosition -win $_nWave3 {("G4" 8)} +wvSetPosition -win $_nWave3 {("G4" 9)} +wvSetPosition -win $_nWave3 {("G4" 10)} +wvSetPosition -win $_nWave3 {("G4" 11)} +wvSetPosition -win $_nWave3 {("G4" 12)} +wvSetPosition -win $_nWave3 {("G4" 13)} +wvSetPosition -win $_nWave3 {("G4" 14)} +wvSetPosition -win $_nWave3 {("G4" 15)} +wvMoveSelected -win $_nWave3 +wvSetPosition -win $_nWave3 {("G4" 15)} +wvSetPosition -win $_nWave3 {("G4" 15)} +wvSetPosition -win $_nWave3 {("G4" 15)} +wvSetPosition -win $_nWave3 {("G4" 15)} +wvSetCursor -win $_nWave3 1741358.464878 -snap {("G4" 11)} +wvSetCursor -win $_nWave3 1741390.102109 -snap {("G4" 11)} +wvSetCursor -win $_nWave3 1741420.718784 -snap {("G4" 11)} +wvSetCursor -win $_nWave3 1741452.356015 -snap {("G4" 11)} +wvSetCursor -win $_nWave3 1741485.013801 -snap {("G4" 11)} +wvSetCursor -win $_nWave3 1741519.712700 -snap {("G4" 11)} +wvSetCursor -win $_nWave3 1741551.349931 -snap {("G4" 11)} +wvSetCursor -win $_nWave3 1741585.028273 -snap {("G4" 11)} +wvSetCursor -win $_nWave3 1741612.583281 -snap {("G4" 11)} +wvSetCursor -win $_nWave3 1741361.526545 -snap {("G4" 11)} +wvSetCursor -win $_nWave3 1741391.122665 -snap {("G4" 11)} +wvSetCursor -win $_nWave3 1741421.739340 -snap {("G4" 11)} +wvSetCursor -win $_nWave3 1741452.356015 -snap {("G4" 11)} +wvSetCursor -win $_nWave3 1741486.034357 -snap {("G4" 11)} +wvSetCursor -win $_nWave3 1741516.651032 -snap {("G4" 11)} +wvSetCursor -win $_nWave3 1741548.288263 -snap {("G4" 11)} +wvSetCursor -win $_nWave3 1741585.028273 -snap {("G4" 11)} +wvSetCursor -win $_nWave3 1741616.665504 -snap {("G4" 11)} +wvSetCursor -win $_nWave3 1741616.665504 -snap {("G4" 14)} +wvSetCursor -win $_nWave3 1741359.485434 -snap {("G4" 15)} +wvSetCursor -win $_nWave3 1741390.102109 -snap {("G4" 11)} +wvSetCursor -win $_nWave3 1741419.698228 -snap {("G4" 11)} +wvSetCursor -win $_nWave3 1741455.417682 -snap {("G4" 11)} +wvSetCursor -win $_nWave3 1741489.096025 -snap {("G4" 11)} +wvSetCursor -win $_nWave3 1741519.712700 -snap {("G4" 11)} +wvSetCursor -win $_nWave3 1741550.329375 -snap {("G4" 11)} +wvSetCursor -win $_nWave3 1741585.028273 -snap {("G4" 11)} +wvSetCursor -win $_nWave3 1741616.665504 -snap {("G4" 11)} +srcDeselectAll -win $_nTrace1 +srcSelect -signal "send" -line 49 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvSetPosition -win $_nWave3 {("G4" 15)} +wvSetPosition -win $_nWave3 {("G4" 14)} +wvMoveSelected -win $_nWave3 +wvSetPosition -win $_nWave3 {("G4" 14)} +wvSetPosition -win $_nWave3 {("G4" 15)} +wvSetPosition -win $_nWave3 {("G4" 15)} +wvSetPosition -win $_nWave3 {("G4" 15)} +wvSetPosition -win $_nWave3 {("G4" 15)} +wvSetCursor -win $_nWave3 1741137.004262 -snap {("G4" 11)} +wvSetCursor -win $_nWave3 1741163.538714 -snap {("G4" 11)} +wvSetCursor -win $_nWave3 1741200.278724 -snap {("G4" 11)} +wvSetCursor -win $_nWave3 1741230.895399 -snap {("G4" 11)} +wvSetCursor -win $_nWave3 1741260.491518 -snap {("G4" 11)} +wvSetCursor -win $_nWave3 1741292.128749 -snap {("G4" 11)} +wvSetCursor -win $_nWave3 1741325.807091 -snap {("G4" 11)} +wvSetCursor -win $_nWave3 1741358.464878 -snap {("G4" 11)} +wvSetCursor -win $_nWave3 1741391.122665 -snap {("G4" 11)} +wvSetCursor -win $_nWave3 1741421.739340 -snap {("G4" 11)} +wvSetCursor -win $_nWave3 1741454.397126 -snap {("G4" 11)} +wvSetCursor -win $_nWave3 1741485.013801 -snap {("G4" 11)} +wvSetCursor -win $_nWave3 1741520.733256 -snap {("G4" 11)} +wvSetCursor -win $_nWave3 1741551.349931 -snap {("G4" 11)} +wvSetCursor -win $_nWave3 1741581.966606 -snap {("G4" 11)} +wvSetCursor -win $_nWave3 1741616.665504 -snap {("G4" 11)} +srcHBSelect "TB.U_digital_top" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top" -delim "." +srcHBSelect "TB.U_digital_top" -win $_nTrace1 +schCreateWindow -delim "." -win $_nSchema1 -scope "TB.U_digital_top" +schZoomIn -win $_nSchema5 -pos 80034 20089 +schZoomIn -win $_nSchema5 -pos 78153 18209 +schZoomIn -win $_nSchema5 -pos 78153 17973 +schZoomIn -win $_nSchema5 -pos 66523 21850 +schZoomIn -win $_nSchema5 -pos 65994 21189 +schZoomIn -win $_nSchema5 -pos 67877 26838 +schZoomIn -win $_nSchema5 -pos 67877 26837 +schZoomIn -win $_nSchema5 -pos 67988 26670 +schZoomIn -win $_nSchema5 -pos 68030 26628 +schZoomIn -win $_nSchema5 -pos 70350 26032 +schZoomIn -win $_nSchema5 -pos 70561 25819 +schZoomIn -win $_nSchema5 -pos 70455 25696 +schZoomIn -win $_nSchema5 -pos 70442 25669 +schZoomOut -win $_nSchema5 -pos 70442 25708 +schZoomOut -win $_nSchema5 -pos 70442 25708 +schSelect -win $_nSchema5 -inst "U_rst_gen_unit" +srcTBInherViewTogg +schSetOptions -win $_nSchema5 -pinName on +schZoomIn -win $_nSchema5 -pos 73165 27877 +schZoomIn -win $_nSchema5 -pos 73165 27877 +schZoomIn -win $_nSchema5 -pos 73165 27858 +schZoomIn -win $_nSchema5 -pos 73137 27821 +schSetOptions -win $_nSchema5 -instName on +schSetOptions -win $_nSchema5 -localNetName on +schZoomIn -win $_nSchema5 -pos 72707 27545 +schZoomOut -win $_nSchema5 -pos 72706 27545 +schZoomOut -win $_nSchema5 -pos 72706 27544 +schZoomOut -win $_nSchema5 -pos 72706 27544 +schZoomOut -win $_nSchema5 -pos 71595 28087 +schZoomOut -win $_nSchema5 -pos 71527 28048 +schZoomOut -win $_nSchema5 -pos 71466 28035 +schZoomOut -win $_nSchema5 -pos 71436 28035 +schZoomOut -win $_nSchema5 -pos 71056 28110 +schZoomOut -win $_nSchema5 -pos 71032 28110 +schZoomIn -win $_nSchema5 -pos 87118 24733 +schZoomIn -win $_nSchema5 -pos 87141 24710 +schZoomIn -win $_nSchema5 -pos 87275 24460 +schZoomIn -win $_nSchema5 -pos 87276 24460 +schZoomOut -win $_nSchema5 -pos 85260 24947 +schZoomOut -win $_nSchema5 -pos 84990 24899 +schZoomOut -win $_nSchema5 -pos 84506 24899 +schZoomOut -win $_nSchema5 -pos 84012 24936 +schZoomOut -win $_nSchema5 -pos 83417 25095 +schZoomOut -win $_nSchema5 -pos 83359 25066 +schZoomOut -win $_nSchema5 -pos 83359 25066 +schZoomOut -win $_nSchema5 -pos 82688 25379 +schZoomOut -win $_nSchema5 -pos 82519 25379 +schZoomOut -win $_nSchema5 -pos 82379 25379 +schZoomIn -win $_nSchema5 -pos 71728 26164 +schZoomIn -win $_nSchema5 -pos 71727 26163 +schZoomIn -win $_nSchema5 -pos 71726 26163 +schZoomIn -win $_nSchema5 -pos 71727 26862 +schZoomIn -win $_nSchema5 -pos 71726 26862 +schZoomIn -win $_nSchema5 -pos 71726 26861 +schZoomOut -win $_nSchema5 -pos 71726 26861 +schZoomOut -win $_nSchema5 -pos 71725 26861 +schZoomOut -win $_nSchema5 -pos 71725 26861 +schZoomIn -win $_nSchema5 -pos 71179 18453 +schZoomIn -win $_nSchema5 -pos 71156 18362 +schZoomIn -win $_nSchema5 -pos 71155 18361 +schZoomIn -win $_nSchema5 -pos 71130 19040 +schZoomIn -win $_nSchema5 -pos 71130 19040 +schZoomIn -win $_nSchema5 -pos 71836 18985 +schZoomIn -win $_nSchema5 -pos 71830 18984 +schZoomIn -win $_nSchema5 -pos 71830 18972 +schZoomIn -win $_nSchema5 -pos 71830 18968 +schZoomOut -win $_nSchema5 -pos 71847 18966 +schZoomOut -win $_nSchema5 -pos 71848 18965 +schZoomOut -win $_nSchema5 -pos 71847 18965 +schZoomOut -win $_nSchema5 -pos 71847 18965 +schZoomIn -win $_nSchema5 -pos 69491 19388 +schZoomIn -win $_nSchema5 -pos 69490 19388 +schZoomIn -win $_nSchema5 -pos 69489 19387 +schZoomIn -win $_nSchema5 -pos 69489 19387 +schZoomIn -win $_nSchema5 -pos 69388 19412 +schZoomIn -win $_nSchema5 -pos 69387 19412 +schZoomIn -win $_nSchema5 -pos 69387 19412 +schZoomOut -win $_nSchema5 -pos 69385 19413 +schZoomOut -win $_nSchema5 -pos 69387 19414 +schZoomOut -win $_nSchema5 -pos 69387 19414 +schZoomOut -win $_nSchema5 -pos 69403 19414 +schZoomOut -win $_nSchema5 -pos 69431 19409 +schZoomOut -win $_nSchema5 -pos 69432 19409 +schZoomOut -win $_nSchema5 -pos 69431 19408 +schSelect -win $_nSchema5 -instport "mst" "clk" +schSelect -win $_nSchema5 -instport "mst" "clk" +schSelect -win $_nSchema5 -instport "mst" "clk" +schSelect -win $_nSchema5 -inst "mst" +schZoomOut -win $_nSchema5 -pos 70694 17847 +schZoomOut -win $_nSchema5 -pos 70694 17846 +schZoomOut -win $_nSchema5 -pos 70689 18779 +schZoomOut -win $_nSchema5 -pos 70689 18779 +schZoomOut -win $_nSchema5 -pos 70671 18779 +schZoomOut -win $_nSchema5 -pos 70670 18778 +schZoomOut -win $_nSchema5 -pos 70670 18779 +schZoomOut -win $_nSchema5 -pos 70619 18778 +schZoomOut -win $_nSchema5 -pos 70470 18947 +schZoomOut -win $_nSchema5 -pos 70444 18947 +schZoomOut -win $_nSchema5 -pos 70443 18946 +schZoomIn -win $_nSchema5 -pos 71516 19424 +schZoomIn -win $_nSchema5 -pos 71484 19300 +schZoomIn -win $_nSchema5 -pos 71484 19253 +schZoomIn -win $_nSchema5 -pos 71466 19044 +schZoomIn -win $_nSchema5 -pos 71466 19017 +schZoomIn -win $_nSchema5 -pos 71456 18987 +schZoomIn -win $_nSchema5 -pos 71426 18980 +schZoomIn -win $_nSchema5 -pos 71425 18979 +schZoomIn -win $_nSchema5 -pos 71426 18979 +schZoomIn -win $_nSchema5 -pos 71425 18978 +schZoomOut -win $_nSchema5 -pos 71369 19015 +schZoomOut -win $_nSchema5 -pos 71366 19015 +schZoomOut -win $_nSchema5 -pos 71358 19014 +schZoomOut -win $_nSchema5 -pos 71354 19014 +schZoomOut -win $_nSchema5 -pos 71348 19013 +schZoomIn -win $_nSchema5 -pos 70390 18981 +schZoomIn -win $_nSchema5 -pos 70390 18980 +schSelect -win $_nSchema5 -inst "mst" +schSetOptions -win $_nSchema5 -portName on +schZoomIn -win $_nSchema5 -pos 70996 19044 +schZoomIn -win $_nSchema5 -pos 71014 19002 +schZoomOut -win $_nSchema5 -pos 70692 19238 +schZoomOut -win $_nSchema5 -pos 70690 19237 +schZoomOut -win $_nSchema5 -pos 70690 19237 +schZoomOut -win $_nSchema5 -pos 70673 19263 +schZoomOut -win $_nSchema5 -pos 70667 19262 +schZoomOut -win $_nSchema5 -pos 70668 19262 +schZoomOut -win $_nSchema5 -pos 70625 19296 +schZoomOut -win $_nSchema5 -pos 70614 19253 +schZoomOut -win $_nSchema5 -pos 70588 19212 +schZoomOut -win $_nSchema5 -pos 70587 19212 +schSelect -win $_nSchema5 -signal "mst" +schZoomOut -win $_nSchema5 -pos 77352 23468 +schZoomOut -win $_nSchema5 -pos 77143 23468 +schZoomOut -win $_nSchema5 -pos 77012 23468 +schZoomOut -win $_nSchema5 -pos 76848 23467 +schZoomOut -win $_nSchema5 -pos 75982 24079 +schZoomOut -win $_nSchema5 -pos 75918 24078 +schZoomOut -win $_nSchema5 -pos 94711 25034 +schZoomOut -win $_nSchema5 -pos 92820 25033 +schZoomOut -win $_nSchema5 -pos 90207 25033 +schZoomOut -win $_nSchema5 -pos 87407 25966 +schZoomOut -win $_nSchema5 -pos 87212 25966 +schZoomOut -win $_nSchema5 -pos 87212 25966 +schZoomIn -win $_nSchema5 -pos 196876 24447 +schZoomIn -win $_nSchema5 -pos 197104 24447 +schZoomIn -win $_nSchema5 -pos 197104 24447 +schZoomIn -win $_nSchema5 -pos 197745 24446 +schZoomIn -win $_nSchema5 -pos 201398 27425 +schZoomIn -win $_nSchema5 -pos 201398 27425 +schZoomIn -win $_nSchema5 -pos 187773 29480 +schZoomIn -win $_nSchema5 -pos 197505 1728 +schZoomIn -win $_nSchema5 -pos 197535 1697 +schZoomIn -win $_nSchema5 -pos 197580 1629 +schZoomIn -win $_nSchema5 -pos 197580 1577 +schZoomIn -win $_nSchema5 -pos 195783 1885 +schZoomIn -win $_nSchema5 -pos 195784 1884 +schZoomOut -win $_nSchema5 -pos 195770 1884 +schZoomOut -win $_nSchema5 -pos 195742 1901 +schZoomOut -win $_nSchema5 -pos 195741 1900 +schSelect -win $_nSchema5 -signal "slv" +schZoomOut -win $_nSchema5 -pos 193005 871 +schZoomOut -win $_nSchema5 -pos 193005 870 +schZoomOut -win $_nSchema5 -pos 193004 870 +schZoomOut -win $_nSchema5 -pos 193003 870 +schZoomOut -win $_nSchema5 -pos 193003 870 +schZoomOut -win $_nSchema5 -pos 193087 1085 +schZoomOut -win $_nSchema5 -pos 193087 1084 +schZoomOut -win $_nSchema5 -pos 193087 1085 +schZoomIn -win $_nSchema5 -pos 146953 15789 +schZoomIn -win $_nSchema5 -pos 146952 16482 +schZoomIn -win $_nSchema5 -pos 146952 16481 +schZoomIn -win $_nSchema5 -pos 146952 16481 +schZoomIn -win $_nSchema5 -pos 146925 18768 +schZoomIn -win $_nSchema5 -pos 146925 18768 +schZoomIn -win $_nSchema5 -pos 146925 18769 +schZoomIn -win $_nSchema5 -pos 147182 20488 +schZoomOut -win $_nSchema5 -pos 147308 19848 +schZoomOut -win $_nSchema5 -pos 147297 19827 +schZoomOut -win $_nSchema5 -pos 148599 -10459 +schZoomOut -win $_nSchema5 -pos 148582 -10476 +schZoomOut -win $_nSchema5 -pos 148582 -10476 +schZoomOut -win $_nSchema5 -pos 148582 -10477 +schZoomOut -win $_nSchema5 -pos 148581 -10476 +schZoomOut -win $_nSchema5 -pos 148582 -10476 +schZoomOut -win $_nSchema5 -pos 148581 -10476 +schZoomOut -win $_nSchema5 -pos 148581 -10476 +schZoomIn -win $_nSchema5 -pos 145604 -7026 +schZoomIn -win $_nSchema5 -pos 145722 -7379 +schZoomIn -win $_nSchema5 -pos 145809 -7599 +schZoomIn -win $_nSchema5 -pos 145876 -7698 +schZoomOut -win $_nSchema5 -pos 145454 -9137 +schZoomOut -win $_nSchema5 -pos 145299 -9385 +schZoomOut -win $_nSchema5 -pos 145183 -9424 +schZoomOut -win $_nSchema5 -pos 145134 -9473 +schZoomOut -win $_nSchema5 -pos 145134 -9473 +schZoomOut -win $_nSchema5 -pos 145134 -9473 +schZoomOut -win $_nSchema5 -pos 145134 -9474 +schZoomOut -win $_nSchema5 -pos 145134 -9474 +schZoomOut -win $_nSchema5 -pos 145133 -9474 +schZoomIn -win $_nSchema5 -pos 195182 -9659 +schZoomIn -win $_nSchema5 -pos 195598 -11598 +schZoomIn -win $_nSchema5 -pos 195805 -13157 +schZoomIn -win $_nSchema5 -pos 195805 -13702 +schZoomIn -win $_nSchema5 -pos 195805 -13819 +schZoomIn -win $_nSchema5 -pos 195805 -13863 +schZoomIn -win $_nSchema5 -pos 185844 -15441 +schZoomIn -win $_nSchema5 -pos 185547 -15540 +schZoomIn -win $_nSchema5 -pos 182531 -15041 +schZoomIn -win $_nSchema5 -pos 182531 -15041 +schZoomIn -win $_nSchema5 -pos 182531 -15041 +schZoomIn -win $_nSchema5 -pos 181266 -14706 +schZoomOut -win $_nSchema5 -pos 183479 -14829 +schZoomOut -win $_nSchema5 -pos 183479 -14829 +schZoomOut -win $_nSchema5 -pos 186478 -23204 +schZoomOut -win $_nSchema5 -pos 186477 -23204 +schZoomOut -win $_nSchema5 -pos 186477 -23204 +schZoomOut -win $_nSchema5 -pos 186476 -23204 +schZoomOut -win $_nSchema5 -pos 186476 -23205 +schZoomOut -win $_nSchema5 -pos 186476 -23204 +schZoomOut -win $_nSchema5 -pos 186476 -23204 +schZoomOut -win $_nSchema5 -pos 186476 -23205 +schZoomOut -win $_nSchema5 -pos 186475 -23205 +schZoomOut -win $_nSchema5 -pos 186475 -23206 +schZoomOut -win $_nSchema5 -pos 186475 -23206 +schZoomOut -win $_nSchema5 -pos 186474 -23206 +schZoomOut -win $_nSchema5 -pos 186474 -23207 +schZoomIn -win $_nSchema5 -pos 203434 -28694 +schZoomIn -win $_nSchema5 -pos 203434 -28695 +schZoomIn -win $_nSchema5 -pos 203434 -28695 +schZoomIn -win $_nSchema5 -pos 203434 -28696 +schZoomIn -win $_nSchema5 -pos 203434 -28696 +schZoomIn -win $_nSchema5 -pos 200672 -26250 +schZoomIn -win $_nSchema5 -pos 200672 -26250 +schZoomIn -win $_nSchema5 -pos 200672 -26250 +schZoomIn -win $_nSchema5 -pos 200655 -26234 +schZoomIn -win $_nSchema5 -pos 200630 -25897 +schZoomIn -win $_nSchema5 -pos 200630 -25898 +schZoomIn -win $_nSchema5 -pos 200629 -25898 +schZoomIn -win $_nSchema5 -pos 200629 -25899 +schZoomIn -win $_nSchema5 -pos 200629 -25900 +schZoomIn -win $_nSchema5 -pos 200629 -25900 +schZoomIn -win $_nSchema5 -pos 200629 -25900 +schZoomIn -win $_nSchema5 -pos 200629 -25900 +schZoomOut -win $_nSchema5 -pos 200952 -26030 +schZoomOut -win $_nSchema5 -pos 200952 -26032 +schZoomOut -win $_nSchema5 -pos 200951 -26033 +schZoomOut -win $_nSchema5 -pos 200945 -26038 +schZoomOut -win $_nSchema5 -pos 200943 -26040 +schZoomOut -win $_nSchema5 -pos 200941 -26040 +schZoomOut -win $_nSchema5 -pos 200940 -26041 +schZoomOut -win $_nSchema5 -pos 200935 -26029 +schZoomOut -win $_nSchema5 -pos 200934 -26029 +schZoomOut -win $_nSchema5 -pos 200933 -26030 +schZoomOut -win $_nSchema5 -pos 200932 -26030 +schZoomOut -win $_nSchema5 -pos 200931 -26030 +schZoomOut -win $_nSchema5 -pos 200913 -25958 +schZoomOut -win $_nSchema5 -pos 200912 -25959 +schZoomOut -win $_nSchema5 -pos 200912 -25959 +schZoomOut -win $_nSchema5 -pos 200912 -25959 +schZoomOut -win $_nSchema5 -pos 200911 -25959 +schZoomOut -win $_nSchema5 -pos 200910 -25959 +schZoomOut -win $_nSchema5 -pos 200840 -25960 +schZoomOut -win $_nSchema5 -pos 200839 -25961 +schZoomOut -win $_nSchema5 -pos 200730 -25853 +schZoomOut -win $_nSchema5 -pos 200728 -25853 +schZoomOut -win $_nSchema5 -pos 157685 -8738 +schZoomOut -win $_nSchema5 -pos 156837 -8738 +schZoomOut -win $_nSchema5 -pos 155778 -8738 +schZoomOut -win $_nSchema5 -pos 155778 -8738 +schZoomOut -win $_nSchema5 -pos 155778 -8739 +schZoomIn -win $_nSchema5 -pos 50797 42458 +schZoomIn -win $_nSchema5 -pos 50797 42458 +schZoomIn -win $_nSchema5 -pos 51088 42748 +schZoomIn -win $_nSchema5 -pos 51305 40348 +schZoomIn -win $_nSchema5 -pos 51632 39202 +schZoomIn -win $_nSchema5 -pos 51632 39079 +schZoomIn -win $_nSchema5 -pos 51816 38803 +schZoomIn -win $_nSchema5 -pos 51954 38595 +schZoomIn -win $_nSchema5 -pos 53041 30467 +schZoomIn -win $_nSchema5 -pos 53041 30234 +schZoomIn -win $_nSchema5 -pos 53041 29825 +schZoomIn -win $_nSchema5 -pos 53041 29803 +schZoomOut -win $_nSchema5 -pos 53353 29984 +schZoomOut -win $_nSchema5 -pos 53353 29983 +schZoomOut -win $_nSchema5 -pos 53353 30008 +schZoomOut -win $_nSchema5 -pos 53353 30008 +schZoomOut -win $_nSchema5 -pos 53273 30128 +schZoomOut -win $_nSchema5 -pos 53272 30128 +schZoomOut -win $_nSchema5 -pos 53148 30315 +schDeselectAll -win $_nSchema5 +schZoomOut -win $_nSchema5 -pos 7609 21567 +schZoomOut -win $_nSchema5 -pos 7610 21567 +schZoomOut -win $_nSchema5 -pos 7610 21566 +schZoomOut -win $_nSchema5 -pos 7610 21566 +schZoomOut -win $_nSchema5 -pos 7610 21947 +schZoomOut -win $_nSchema5 -pos 7609 21947 +schZoomOut -win $_nSchema5 -pos 7609 21946 +schZoomOut -win $_nSchema5 -pos 7609 21947 +schZoomOut -win $_nSchema5 -pos 7609 21946 +schZoomOut -win $_nSchema5 -pos 7610 21946 +wvUnselectUserMarker -win $_nWave3 +srcHBSelect "TB.U_digital_top" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top" -delim "." +srcHBSelect "TB.U_digital_top" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +debReload +wvSelectSignal -win $_nWave3 {( "G4" 9 )} +wvSelectAll -win $_nWave3 +wvCut -win $_nWave3 +wvSetPosition -win $_nWave3 {("G4" 0)} +wvSetPosition -win $_nWave3 {("G4" 0)} +wvSetPosition -win $_nWave3 {("G4" 0)} +wvSetPosition -win $_nWave3 {("G4" 0)} +srcHBSelect "TB.U_digital_top.U0_channel_top" -win $_nTrace1 +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U0_channel_top.U_awg_top" -delim "." +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top" -win $_nTrace1 +srcHBSelect "TB.U_digital_top.U0_channel_top.U_qbmcu" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U0_channel_top.U_qbmcu" -delim "." +srcHBSelect "TB.U_digital_top.U0_channel_top.U_qbmcu" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "ext_wait" -line 254 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -word -line 255 -pos 3 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvSetCursor -win $_nWave3 1739637.297463 -snap {("G4" 2)} +srcDeselectAll -win $_nTrace1 +srcSelect -signal "ext_wait_cnt" -line 252 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvZoom -win $_nWave3 1739465.844082 1741408.982391 +wvZoom -win $_nWave3 1740597.049522 1740721.410374 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "qbmcu_i_timer_done" -line 257 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvZoomOut -win $_nWave3 +wvSelectSignal -win $_nWave3 {( "G4" 3 )} +wvSelectAll -win $_nWave3 +wvCut -win $_nWave3 +wvSetPosition -win $_nWave3 {("G4" 0)} +wvSetPosition -win $_nWave3 {("G4" 0)} +wvSetPosition -win $_nWave3 {("G4" 0)} +wvSetPosition -win $_nWave3 {("G4" 0)} +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U0_channel_top.U_awg_top" -delim "." +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "mcu_nco_pha_clr" -line 46 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 1740193.929038 1741731.870993 +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.U_mod_nco" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U0_channel_top.U_awg_top.U_mod_nco" \ + -delim "." +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.U_mod_nco" -win $_nTrace1 +srcSelect -signal "fcw" -line 6 -pos 1 -win $_nTrace1 +srcSelect -signal "pha" -line 7 -pos 1 -win $_nTrace1 +srcSelect -signal "cos" -line 9 -pos 1 -win $_nTrace1 +srcSelect -signal "sin" -line 11 -pos 1 -win $_nTrace1 +srcSelect -signal "phase_auto_clr" -line 5 -pos 1 -win $_nTrace1 +srcSelect -signal "phase_manual_clr" -line 4 -pos 1 -win $_nTrace1 +srcSelect -signal "clk" -line 2 -pos 1 -win $_nTrace1 +srcSelect -signal "rstn" -line 3 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvSetCursor -win $_nWave3 1740882.927033 -snap {("G4" 7)} +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 1678229.832960 1905179.063040 +wvZoom -win $_nWave3 1735211.547343 1751551.891909 +wvZoom -win $_nWave3 1740601.347151 1742039.297472 +wvSelectSignal -win $_nWave3 {( "G4" 4 )} +wvSelectSignal -win $_nWave3 {( "G4" 2 )} +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 1648368.092160 1970874.892800 +wvZoom -win $_nWave3 1718624.958269 1782133.989779 +wvZoom -win $_nWave3 1736329.322129 1749734.613088 +wvZoom -win $_nWave3 1739422.850812 1743159.833461 +wvZoom -win $_nWave3 1740579.590671 1741393.677968 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +srcDeselectAll -win $_nTrace1 +debReload +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvSelectSignal -win $_nWave3 {( "G4" 6 )} +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 1733971.749120 2012681.329920 +wvZoom -win $_nWave3 1801205.075688 1847170.717322 +wvZoom -win $_nWave3 1812491.408618 1823070.577831 +wvZoom -win $_nWave3 1815049.940003 1817016.037912 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvSelectSignal -win $_nWave3 {( "G4" 1 )} +wvSetPosition -win $_nWave3 {("G4" 1)} +wvSetPosition -win $_nWave3 {("G4" 2)} +wvSetPosition -win $_nWave3 {("G4" 3)} +wvSetPosition -win $_nWave3 {("G4" 4)} +wvSetPosition -win $_nWave3 {("G4" 5)} +wvMoveSelected -win $_nWave3 +wvSetPosition -win $_nWave3 {("G4" 5)} +wvSetPosition -win $_nWave3 {("G4" 5)} +wvSetPosition -win $_nWave3 {("G4" 5)} +wvSetPosition -win $_nWave3 {("G4" 5)} +wvZoom -win $_nWave3 1814324.601113 1817421.961511 +wvZoom -win $_nWave3 1814774.433145 1816064.841139 +wvZoomOut -win $_nWave3 +wvSetCursor -win $_nWave3 1815374.373600 -snap {("G4" 1)} +wvSelectSignal -win $_nWave3 {( "G4" 8 )} +wvSetPosition -win $_nWave3 {("G4" 8)} +wvSetPosition -win $_nWave3 {("G4" 7)} +wvSetPosition -win $_nWave3 {("G4" 6)} +wvMoveSelected -win $_nWave3 +wvSetPosition -win $_nWave3 {("G4" 6)} +wvSetPosition -win $_nWave3 {("G4" 7)} +wvSetPosition -win $_nWave3 {("G4" 7)} +wvSetPosition -win $_nWave3 {("G4" 7)} +wvSetPosition -win $_nWave3 {("G4" 7)} +wvScrollUp -win $_nWave3 1 +wvSetPosition -win $_nWave3 {("G4" 6)} +wvSetPosition -win $_nWave3 {("G4" 5)} +wvSetPosition -win $_nWave3 {("G4" 4)} +wvMoveSelected -win $_nWave3 +wvSetPosition -win $_nWave3 {("G4" 4)} +wvSetPosition -win $_nWave3 {("G4" 5)} +wvSetPosition -win $_nWave3 {("G4" 5)} +wvSetPosition -win $_nWave3 {("G4" 5)} +wvSetPosition -win $_nWave3 {("G4" 5)} +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 1821855.001068 1823163.673297 +wvZoom -win $_nWave3 1822312.432345 1822551.617362 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 1843452.192891 1848049.255318 +wvZoom -win $_nWave3 1844688.449064 1845293.846823 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 2076457.902843 2132537.480666 +wvZoom -win $_nWave3 2120355.270836 2127982.093420 +srcDeselectAll -win $_nTrace1 +debReload +wvZoom -win $_nWave3 2124846.882658 2125414.787601 +wvSetCursor -win $_nWave3 2125040.145079 -snap {("G4" 5)} +wvSetCursor -win $_nWave3 2125070.549836 -snap {("G4" 5)} +wvSetCursor -win $_nWave3 2125104.099912 -snap {("G4" 5)} +wvSetCursor -win $_nWave3 2125135.553109 -snap {("G4" 5)} +wvSetCursor -win $_nWave3 2125168.404226 -snap {("G4" 5)} +wvSetCursor -win $_nWave3 2125199.507943 -snap {("G4" 5)} +wvSetCursor -win $_nWave3 2125232.708539 -snap {("G4" 5)} +wvSetCursor -win $_nWave3 2125265.210176 -snap {("G4" 5)} +wvSetCursor -win $_nWave3 2125297.362333 -snap {("G4" 5)} +wvSetCursor -win $_nWave3 2125327.767090 -snap {("G4" 5)} +wvSetCursor -win $_nWave3 2125039.795599 -snap {("G4" 5)} +wvSetCursor -win $_nWave3 2125070.549836 -snap {("G4" 5)} +wvSetCursor -win $_nWave3 2125103.051472 -snap {("G4" 5)} +wvSetCursor -win $_nWave3 2125135.553109 -snap {("G4" 5)} +wvSetCursor -win $_nWave3 2125169.103186 -snap {("G4" 5)} +wvSetCursor -win $_nWave3 2125201.604823 -snap {("G4" 5)} +wvSetCursor -win $_nWave3 2125232.009579 -snap {("G4" 5)} +wvSetCursor -win $_nWave3 2125264.860696 -snap {("G4" 5)} +wvSetCursor -win $_nWave3 2125296.313893 -snap {("G4" 5)} +wvSetCursor -win $_nWave3 2125039.795599 -snap {("G4" 5)} +wvSetCursor -win $_nWave3 2125072.646715 -snap {("G4" 5)} +wvSetCursor -win $_nWave3 2125102.003032 -snap {("G4" 5)} +wvSetCursor -win $_nWave3 2125135.553109 -snap {("G4" 5)} +wvSetCursor -win $_nWave3 2125164.559946 -snap {("G4" 5)} +wvSetCursor -win $_nWave3 2125199.507943 -snap {("G4" 4)} +wvSetCursor -win $_nWave3 2125232.708539 -snap {("G4" 5)} +wvSetCursor -win $_nWave3 2125263.462776 -snap {("G4" 5)} +wvSetCursor -win $_nWave3 2125294.566493 -snap {("G4" 5)} +wvSetCursor -win $_nWave3 2125328.466050 -snap {("G4" 5)} +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 1608872.071825 1859379.310761 +wvZoom -win $_nWave3 1733277.820638 1773050.662266 +wvZoom -win $_nWave3 1742382.741920 1751610.041178 +wvZoom -win $_nWave3 1744478.048644 1747038.979084 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 1743883.124802 1746543.340546 +wvZoom -win $_nWave3 1744549.406530 1745462.883690 +wvSetCursor -win $_nWave3 1744655.650949 -snap {("G4" 5)} +wvSetCursor -win $_nWave3 1744687.130778 -snap {("G4" 5)} +wvSetCursor -win $_nWave3 1744720.297025 -snap {("G4" 5)} +wvSetCursor -win $_nWave3 1744751.776854 -snap {("G4" 5)} +wvSetCursor -win $_nWave3 1744785.505241 -snap {("G4" 5)} +wvSetCursor -win $_nWave3 1744819.233629 -snap {("G4" 5)} +wvSetCursor -win $_nWave3 1744847.902758 -snap {("G4" 5)} +wvSetCursor -win $_nWave3 1744883.879704 -snap {("G4" 5)} +wvSetCursor -win $_nWave3 1744914.797393 -snap {("G4" 5)} +wvSetCursor -win $_nWave3 1744944.590802 -snap {("G4" 5)} +wvSetCursor -win $_nWave3 1744657.337369 -snap {("G4" 5)} +wvSetCursor -win $_nWave3 1744688.255057 -snap {("G4" 5)} +wvSetCursor -win $_nWave3 1744718.610606 -snap {("G4" 5)} +wvSetCursor -win $_nWave3 1744751.214714 -snap {("G4" 5)} +wvSetCursor -win $_nWave3 1744788.315940 -snap {("G4" 5)} +wvSetCursor -win $_nWave3 1744816.985069 -snap {("G4" 5)} +wvSetCursor -win $_nWave3 1744846.778478 -snap {("G4" 5)} +wvSetCursor -win $_nWave3 1744882.193285 -snap {("G4" 5)} +wvSetCursor -win $_nWave3 1744910.300275 -snap {("G4" 5)} +wvSetCursor -win $_nWave3 1744949.087920 -snap {("G4" 5)} +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 1743728.963504 1748298.035723 +wvZoom -win $_nWave3 1744783.364785 1745483.487236 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvSetCursor -win $_nWave3 1744101.984074 -snap {("G4" 6)} +wvSetCursor -win $_nWave3 1744974.013514 -snap {("G4" 3)} +srcDeselectAll -win $_nTrace1 +debReload +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvSelectSignal -win $_nWave3 {( "G4" 4 )} +wvSelectSignal -win $_nWave3 {( "G4" 6 )} +wvSelectAll -win $_nWave3 +wvCut -win $_nWave3 +wvSetPosition -win $_nWave3 {("G4" 0)} +wvSetPosition -win $_nWave3 {("G4" 0)} +wvSetPosition -win $_nWave3 {("G4" 0)} +wvSetPosition -win $_nWave3 {("G4" 0)} +srcHBSelect "TB.U_digital_top.U0_channel_top.U_qbmcu" -win $_nTrace1 +srcHBSelect "TB.U_digital_top.U0_channel_top.U_qbmcu" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U0_channel_top.U_qbmcu" -delim "." +srcHBSelect "TB.U_digital_top.U0_channel_top.U_qbmcu" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "qbmcu_i_start" -line 42 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "qbmcu_o_fsm_st" -line 43 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvZoom -win $_nWave3 1714069.073852 1766054.319563 +wvZoom -win $_nWave3 1737134.527487 1743372.756973 +wvZoom -win $_nWave3 1738904.265206 1741061.732880 +wvZoom -win $_nWave3 1739027.738740 1740624.928655 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "ext_o_send" -line 63 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "ext_wbck_wdat" -line 164 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "ext_wbck_valid" -line 165 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "ext_wait" -line 187 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "ext_wait_cnt" -line 188 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcSelect -signal "ifu_o_req_pc" -line 46 -pos 1 -win $_nTrace1 +srcSelect -signal "ifu_o_req" -line 47 -pos 1 -win $_nTrace1 +srcSelect -signal "ifu_rsp_instr" -line 48 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvScrollDown -win $_nWave3 1 +wvZoom -win $_nWave3 1740160.023528 1740348.737660 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvSetCursor -win $_nWave3 1740244.160997 -snap {("G4" 10)} +srcHBSelect "TB.U_digital_top.U0_channel_top.U_qbmcu.qbmcu_decode" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U0_channel_top.U_qbmcu.qbmcu_decode" \ + -delim "." +srcHBSelect "TB.U_digital_top.U0_channel_top.U_qbmcu.qbmcu_decode" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "rv32_jal" -line 135 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvScrollDown -win $_nWave3 1 +wvZoom -win $_nWave3 1740156.829904 1740212.573155 +wvZoom -win $_nWave3 1740174.256101 1740178.132401 +wvZoom -win $_nWave3 1740174.924016 1740175.186412 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvScrollDown -win $_nWave3 1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "rv32_jalr" -line 130 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "ext_op" -line 272 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvSetCursor -win $_nWave3 1740175.385913 -snap {("G4" 2)} +wvSetCursor -win $_nWave3 1740208.455843 -snap {("G4" 2)} +wvSetCursor -win $_nWave3 1740237.557382 -snap {("G4" 2)} +srcDeselectAll -win $_nTrace1 +srcSelect -signal "rv32_imm" -line 405 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "need_imm" -line 424 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "legl_ops" -line 458 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 1739077.133528 1740362.892418 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "dec_ilegl_w" -line 468 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 0 +wvSelectSignal -win $_nWave3 {( "G4" 12 )} +wvSelectAll -win $_nWave3 +wvCut -win $_nWave3 +wvSetPosition -win $_nWave3 {("G4" 0)} +wvSetPosition -win $_nWave3 {("G4" 0)} +wvSetPosition -win $_nWave3 {("G4" 0)} +wvSetPosition -win $_nWave3 {("G4" 0)} +srcDeselectAll -win $_nTrace1 +srcSelect -signal "ext_op" -line 272 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "alu_op" -line 207 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "bjp_op" -line 162 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcHBSelect "TB.U_digital_top" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top" -delim "." +srcHBSelect "TB.U_digital_top" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +debReload +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 1707954.706640 1888423.293563 +wvZoom -win $_nWave3 1756708.989507 1770924.361277 +wvZoom -win $_nWave3 1761047.958367 1763366.157456 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 1689185.973600 1947616.990074 +wvZoom -win $_nWave3 1762818.933986 1789218.656284 +wvZoom -win $_nWave3 1770227.102212 1772290.342047 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 1823711.992322 1831919.242964 +wvZoom -win $_nWave3 1827878.750340 1828893.924112 +srcHBSelect "TB.U_digital_top.U0_channel_top.U_qbmcu" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U0_channel_top.U_qbmcu" -delim "." +srcHBSelect "TB.U_digital_top.U0_channel_top.U_qbmcu" -win $_nTrace1 +srcSelect -signal "ext_o_wait_cnt" -line 188 -pos 1 -win $_nTrace1 +srcSelect -signal "ext_o_wait" -line 187 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -inst "U_qbmcu_regfile" -line 238 -pos 1 -win $_nTrace1 +srcAction -pos 237 2 9 -win $_nTrace1 -name "U_qbmcu_regfile" -ctrlKey off +srcSelect -signal "wbck_dest_dat" -line 46 -pos 1 -win $_nTrace1 +srcSelect -signal "wbck_dest_idx" -line 45 -pos 1 -win $_nTrace1 +srcSelect -signal "wbck_dest_wen" -line 44 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvSelectSignal -win $_nWave3 {( "G4" 6 )} +wvZoom -win $_nWave3 1828165.185524 1828555.012252 +wvZoomOut -win $_nWave3 +wvSelectSignal -win $_nWave3 {( "G4" 7 )} +srcDeselectAll -win $_nTrace1 +srcSelect -signal "wbck_dest_wen" -line 44 -pos 1 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "wbck_dest_wen" -line 44 -pos 1 -win $_nTrace1 +srcAction -pos 43 4 4 -win $_nTrace1 -name "wbck_dest_wen" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -signal "dnxt" -line 277 -pos 1 -win $_nTrace1 +srcAction -pos 276 12 1 -win $_nTrace1 -name "dnxt" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -signal "wbck_i_active" -line 76 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "wbck_i_rdwen" -line 76 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "wbck_i_rdwen" -line 76 -pos 1 -win $_nTrace1 +srcAction -pos 75 6 7 -win $_nTrace1 -name "wbck_i_rdwen" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -signal "dnxt" -line 107 -pos 1 -win $_nTrace1 +srcAction -pos 106 12 1 -win $_nTrace1 -name "dnxt" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -signal "rv32_rd_x0" -line 315 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvSelectSignal -win $_nWave3 {( "G4" 7 )} +srcDeselectAll -win $_nTrace1 +srcSelect -signal "rv32_branch" -line 316 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "rv32_store" -line 317 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "rv32_branch" -line 316 -pos 1 -win $_nTrace1 +srcAction -pos 315 9 3 -win $_nTrace1 -name "rv32_branch" -ctrlKey off +srcBackwardHistory -win $_nTrace1 +srcHBSelect "TB.U_digital_top.U0_channel_top.U_qbmcu.qbmcu_decode" -win $_nTrace1 +srcHBSelect "TB.U_digital_top.U0_channel_top.U_qbmcu.qbmcu_decode" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "rv32_rd_x0" -line 315 -pos 1 -win $_nTrace1 +srcAction -pos 314 8 5 -win $_nTrace1 -name "rv32_rd_x0" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -signal "rv32_rd" -line 118 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvSelectSignal -win $_nWave3 {( "G4" 11 )} +wvSelectSignal -win $_nWave3 {( "G4" 7 )} +wvSetCursor -win $_nWave3 1828126.682637 -snap {("G4" 7)} +srcActiveTrace \ + "TB.U_digital_top.U0_channel_top.U_qbmcu.U_qbmcu_regfile.wbck_dest_idx\[4:0\]" \ + -win $_nTrace1 -TraceByDConWave -TraceTime 1820368000 -TraceValue \ + 00001 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "dnxt" -line 107 -pos 1 -win $_nTrace1 +srcAction -pos 106 12 1 -win $_nTrace1 -name "dnxt" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -signal "dnxt" -line 107 -pos 1 -win $_nTrace1 +srcAction -pos 106 12 1 -win $_nTrace1 -name "dnxt" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -signal "rv32_instr\[11:7\]" -line 81 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvSelectSignal -win $_nWave3 {( "G4" 7 )} +wvSetCursor -win $_nWave3 1827984.185975 -snap {("G4" 7)} +srcActiveTrace \ + "TB.U_digital_top.U0_channel_top.U_qbmcu.U_qbmcu_regfile.wbck_dest_idx\[4:0\]" \ + -win $_nTrace1 -TraceByDConWave -TraceTime 1820368000 -TraceValue \ + 00001 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "dnxt" -line 107 -pos 1 -win $_nTrace1 +srcAction -pos 106 12 2 -win $_nTrace1 -name "dnxt" -ctrlKey off +srcBackwardHistory -win $_nTrace1 +srcHBSelect \ + "TB.U_digital_top.U0_channel_top.U_qbmcu.qbmcu_decode.dec_o_rdidx_dfflr" \ + -win $_nTrace1 +srcHBSelect \ + "TB.U_digital_top.U0_channel_top.U_qbmcu.U_qbmcu_wbck.wbck_o_rdidx_dfflr" \ + -win $_nTrace1 +srcHBSelect "TB.U_digital_top.U0_channel_top.U_qbmcu.U_qbmcu_wbck" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U0_channel_top.U_qbmcu.U_qbmcu_wbck" \ + -delim "." +srcHBSelect "TB.U_digital_top.U0_channel_top.U_qbmcu.U_qbmcu_wbck" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "wbck_i_rdidx" -line 43 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "wbck_o_rdidx" -line 64 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "wbck_i_active" -line 83 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "wbck_i_active" -line 83 -pos 1 -win $_nTrace1 +srcAction -pos 82 13 8 -win $_nTrace1 -name "wbck_i_active" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -signal "dnxt" -line 277 -pos 1 -win $_nTrace1 +srcAction -pos 276 12 3 -win $_nTrace1 -name "dnxt" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -signal "wait2ifuwb" -line 94 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "qbmcu_timer_done" -line 94 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "exu2wait" -line 92 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "exit" -line 93 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "dec_ilegl" -line 93 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "agu_addr_unalgn" -line 93 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "state_c" -line 94 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvSetCursor -win $_nWave3 1828119.245943 -snap {("G4" 20)} +wvSelectSignal -win $_nWave3 {( "G4" 21 )} +wvSelectSignal -win $_nWave3 {( "G4" 20 )} +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "wait2ifuwb" -line 84 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 1825535.114548 1831922.035665 +wvZoom -win $_nWave3 1827979.831430 1828341.429426 +wvSelectSignal -win $_nWave3 {( "G4" 16 )} +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "wait2ifuwb" -line 94 -pos 1 -win $_nTrace1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 5 +wvScrollUp -win $_nWave3 2 +wvSelectSignal -win $_nWave3 {( "G4" 6 )} +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +srcDeselectAll -win $_nTrace1 +debReload +wvSelectSignal -win $_nWave3 {( "G4" 18 )} +wvSelectSignal -win $_nWave3 {( "G4" 17 18 )} +wvSelectSignal -win $_nWave3 {( "G4" 12 )} +wvSelectAll -win $_nWave3 +wvCut -win $_nWave3 +wvSetPosition -win $_nWave3 {("G4" 0)} +wvSetPosition -win $_nWave3 {("G4" 0)} +wvSetPosition -win $_nWave3 {("G4" 0)} +wvSetPosition -win $_nWave3 {("G4" 0)} +srcHBSelect "TB.U_digital_top.U0_channel_top.U_qbmcu.U_qbmcu_wbck" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U0_channel_top.U_qbmcu.U_qbmcu_wbck" \ + -delim "." +srcHBSelect "TB.U_digital_top.U0_channel_top.U_qbmcu.U_qbmcu_wbck" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "wbck_i_rdidx" -line 43 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "wbck_i_rdwen" -line 45 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "bjp_i_wbck_wdat" -line 48 -pos 1 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "ext_i_wbck_wdat" -line 57 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "ext_i_wbck_valid" -line 58 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "wbck_i_active" -line 41 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "wbck_o_rdidx" -line 64 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "wbck_o_ena_w" -line 78 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "alu_i_wbck_valid" -line 71 -pos 1 -win $_nTrace1 +debReload +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 1722027.052800 1825547.754240 +wvZoom -win $_nWave3 1758657.454848 1768213.211904 +wvZoom -win $_nWave3 1762814.944225 1763408.871279 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 1761671.863078 1762154.314593 +wvSelectSignal -win $_nWave3 {( "G4" 6 )} +wvSelectAll -win $_nWave3 +wvCut -win $_nWave3 +wvSetPosition -win $_nWave3 {("G4" 0)} +wvSetPosition -win $_nWave3 {("G4" 0)} +wvSetPosition -win $_nWave3 {("G4" 0)} +wvSetPosition -win $_nWave3 {("G4" 0)} +srcSelect -signal "wbck_o_rdidx" -line 64 -pos 1 -win $_nTrace1 +srcSelect -signal "wbck_o_wdat" -line 63 -pos 1 -win $_nTrace1 +srcSelect -signal "wbck_o_ena" -line 62 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 1761644.697347 1763801.329840 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 1676239.050240 1990782.720000 +wvZoom -win $_nWave3 1752697.357659 1781151.461938 +wvZoom -win $_nWave3 1760226.751406 1765724.959864 +wvZoom -win $_nWave3 1761654.593848 1763864.027769 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "ext_i_wbck_wdat" -line 57 -pos 1 -win $_nTrace1 +srcSelect -signal "ext_i_wbck_valid" -line 58 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 1721686.953941 1867876.698723 +wvZoom -win $_nWave3 1761450.564521 1769367.301469 +wvZoom -win $_nWave3 1762415.188468 1764032.638725 +wvZoomOut -win $_nWave3 +srcHBSelect "TB.U_digital_top.U0_channel_top.U_qbmcu.U_qbmcu_exu.U_qbmcu_exu_ext" \ + -win $_nTrace1 +srcSetScope -win $_nTrace1 \ + "TB.U_digital_top.U0_channel_top.U_qbmcu.U_qbmcu_exu.U_qbmcu_exu_ext" \ + -delim "." +srcHBSelect "TB.U_digital_top.U0_channel_top.U_qbmcu.U_qbmcu_exu.U_qbmcu_exu_ext" \ + -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "ext_o_wait" -line 55 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +srcDeselectAll -win $_nTrace1 +debReload +wvZoom -win $_nWave3 1759851.924480 1980828.806400 +wvZoom -win $_nWave3 1801463.571168 1843619.160949 +wvZoom -win $_nWave3 1817417.840531 1824162.734896 +wvZoom -win $_nWave3 1819991.277149 1821058.008135 +wvSelectSignal -win $_nWave3 {( "G4" 1 )} +srcDeselectAll -win $_nTrace1 +srcSelect -signal "ext_o_wbck_valid" -line 63 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvZoomOut -win $_nWave3 +srcDeselectAll -win $_nTrace1 +debReload +wvSelectSignal -win $_nWave3 {( "G4" 3 )} +wvSetCursor -win $_nWave3 1820362.499532 -snap {("G4" 3)} +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 1824641.896022 1834724.965527 +wvZoom -win $_nWave3 1827967.757717 1828718.558585 +wvSetCursor -win $_nWave3 1828176.595866 -snap {("G4" 2)} +wvSetCursor -win $_nWave3 1828174.285710 -snap {("G4" 1)} +srcDeselectAll -win $_nTrace1 +srcSelect -signal "ext_o_exit" -line 60 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvSetCursor -win $_nWave3 1828496.321528 -snap {("G4" 8)} +srcHBSelect "TB.U_digital_top.U0_channel_top.U_qbmcu.U_qbmcu_fsm" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U0_channel_top.U_qbmcu.U_qbmcu_fsm" \ + -delim "." +srcHBSelect "TB.U_digital_top.U0_channel_top.U_qbmcu.U_qbmcu_fsm" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "exit" -line 40 -pos 1 -win $_nTrace1 +srcSearchString "exit" -win $_nTrace1 -next -case +srcSearchString "exit" -win $_nTrace1 -next -case +srcSearchString "exit" -win $_nTrace1 -next -case +srcHBSelect "TB.U_digital_top.U0_channel_top.U_qbmcu" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U0_channel_top.U_qbmcu" -delim "." +srcHBSelect "TB.U_digital_top.U0_channel_top.U_qbmcu" -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +debReload +srcDeselectAll -win $_nTrace1 +srcSelect -word -line 257 -pos 3 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 1818230.216983 1824380.777693 +wvZoom -win $_nWave3 1820289.235460 1820607.172137 +wvSetCursor -win $_nWave3 1820400.170903 -snap {("G4" 9)} +srcDeselectAll -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "qbmcu_i_timer_done" -line 263 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -word -line 261 -pos 3 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 1827854.856619 1828643.730884 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 0 +wvSelectAll -win $_nWave3 +wvCut -win $_nWave3 +wvSetPosition -win $_nWave3 {("G4" 0)} +wvSetPosition -win $_nWave3 {("G4" 0)} +wvSetPosition -win $_nWave3 {("G4" 0)} +wvSetPosition -win $_nWave3 {("G4" 0)} +srcHBSelect "TB.U_digital_top.U0_channel_top.U_qbmcu.U_qbmcu_regfile" -win \ + $_nTrace1 +srcSetScope -win $_nTrace1 \ + "TB.U_digital_top.U0_channel_top.U_qbmcu.U_qbmcu_regfile" -delim \ + "." +srcHBSelect "TB.U_digital_top.U0_channel_top.U_qbmcu.U_qbmcu_regfile" -win \ + $_nTrace1 +srcHBSelect "TB.U_digital_top.U0_channel_top.U_qbmcu.U_qbmcu_wbck" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U0_channel_top.U_qbmcu.U_qbmcu_wbck" \ + -delim "." +srcHBSelect "TB.U_digital_top.U0_channel_top.U_qbmcu.U_qbmcu_wbck" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "wbck_o_wdat" -line 63 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "wbck_o_rdidx" -line 64 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "wbck_o_ena" -line 62 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvSetCursor -win $_nWave3 1828176.231857 -snap {("G4" 2)} +srcDeselectAll -win $_nTrace1 +srcSelect -signal "wbck_i_rdidx" -line 43 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcHBSelect "TB.U_digital_top.U0_channel_top.U_qbmcu.U_qbmcu_fsm" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U0_channel_top.U_qbmcu.U_qbmcu_fsm" \ + -delim "." +srcHBSelect "TB.U_digital_top.U0_channel_top.U_qbmcu.U_qbmcu_fsm" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "state_c" -line 59 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcHBSelect "TB.U_digital_top.U0_channel_top.U_qbmcu.U_qbmcu_wbck" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U0_channel_top.U_qbmcu.U_qbmcu_wbck" \ + -delim "." +srcHBSelect "TB.U_digital_top.U0_channel_top.U_qbmcu.U_qbmcu_wbck" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "wbck_i_rdwen" -line 45 -pos 1 -win $_nTrace1 +srcSelect -signal "wbck_i_rdidx" -line 43 -pos 1 -win $_nTrace1 +srcSelect -signal "wbck_i_active" -line 41 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvSelectSignal -win $_nWave3 {( "G4" 8 )} +wvSetCursor -win $_nWave3 1828144.191425 -snap {("G4" 8)} +srcDeselectAll -win $_nTrace1 +srcSelect -signal "wbck_i_wdat" -line 69 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvSetCursor -win $_nWave3 1828176.231857 -snap {("G4" 3)} +srcDeselectAll -win $_nTrace1 +srcSelect -signal "bjp_i_wbck_wdat" -line 69 -pos 1 -win $_nTrace1 +srcSelect -signal "bjp_i_wbck_valid" -line 69 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvSelectSignal -win $_nWave3 {( "G4" 9 )} +wvSetCursor -win $_nWave3 1828144.676886 -snap {("G4" 8)} +wvSetCursor -win $_nWave3 1828238.856337 -snap {("G4" 8)} +srcDeselectAll -win $_nTrace1 +srcSelect -signal "agu_i_wbck_valid" -line 70 -pos 1 -win $_nTrace1 +srcSelect -signal "agu_i_wbck_wdat" -line 70 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 0 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 1751569.744272 1784627.702394 +wvZoom -win $_nWave3 1760337.731934 1765057.391186 +wvZoom -win $_nWave3 1761575.008758 1763105.630559 +wvZoom -win $_nWave3 1761880.191197 1762911.594810 +wvSelectSignal -win $_nWave3 {( "G4" 12 )} +wvSelectSignal -win $_nWave3 {( "G4" 4 )} +wvScrollUp -win $_nWave3 2 +wvSelectSignal -win $_nWave3 {( "G4" 1 )} +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvSelectSignal -win $_nWave3 {( "G4" 12 )} +wvSelectSignal -win $_nWave3 {( "G4" 8 )} +wvSetPosition -win $_nWave3 {("G4" 8)} +wvSetPosition -win $_nWave3 {("G4" 9)} +wvSetPosition -win $_nWave3 {("G4" 10)} +wvSetPosition -win $_nWave3 {("G4" 11)} +wvMoveSelected -win $_nWave3 +wvSetPosition -win $_nWave3 {("G4" 11)} +wvSetPosition -win $_nWave3 {("G4" 11)} +wvSetPosition -win $_nWave3 {("G4" 11)} +wvSetPosition -win $_nWave3 {("G4" 11)} +wvSetCursor -win $_nWave3 1761932.872119 -snap {("G4" 11)} +srcHBSelect "TB.U_digital_top.U0_channel_top.U_z_dsp" -win $_nTrace1 +srcHBSelect "TB.U_digital_top.U0_channel_top.U_z_dsp" -win $_nTrace1 +srcHBSelect "TB.U_digital_top.U0_channel_top.U_z_dsp" -win $_nTrace1 +srcHBSelect "TB.U_digital_top.U0_channel_top.U_z_dsp" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U0_channel_top.U_z_dsp" -delim "." +srcHBSelect "TB.U_digital_top.U0_channel_top.U_z_dsp" -win $_nTrace1 +schCreateWindow -delim "." -win $_nSchema1 -scope \ + "TB.U_digital_top.U0_channel_top.U_z_dsp" +schZoomIn -win $_nSchema6 -pos 16840 17222 +schZoomIn -win $_nSchema6 -pos 16840 17221 +schSelect -win $_nSchema6 -inst "inst_TailCorr_top" +schPushViewIn -win $_nSchema6 +schZoomIn -win $_nSchema6 -pos 14245 18358 +schZoomIn -win $_nSchema6 -pos 14245 18358 +schZoomIn -win $_nSchema6 -pos 14443 18490 +schZoomIn -win $_nSchema6 -pos 14443 18489 +schZoomIn -win $_nSchema6 -pos 14442 18489 +schZoomIn -win $_nSchema6 -pos 14525 18629 +schZoomOut -win $_nSchema6 -pos 14546 18713 +schZoomOut -win $_nSchema6 -pos 14467 18686 +schZoomOut -win $_nSchema6 -pos 14434 18686 +schZoomOut -win $_nSchema6 -pos 14393 18685 +schZoomOut -win $_nSchema6 -pos 14343 18685 +schZoomIn -win $_nSchema6 -pos 38836 36720 +schZoomIn -win $_nSchema6 -pos 38979 35760 +schZoomIn -win $_nSchema6 -pos 39015 35580 +schZoomIn -win $_nSchema6 -pos 38179 34042 +schZoomIn -win $_nSchema6 -pos 38179 34002 +schSelect -win $_nSchema6 -inst "inst_iir_3" +schPushViewIn -win $_nSchema6 +schZoomOut -win $_nSchema6 -pos 17261 6227 +schZoomOut -win $_nSchema6 -pos 17201 6196 +schZoomIn -win $_nSchema6 -pos 5171 8393 +schZoomIn -win $_nSchema6 -pos 5170 8394 +schZoomOut -win $_nSchema6 -pos 5191 8392 +schSelect -win $_nSchema6 -inst "inst_c1" +schPushViewIn -win $_nSchema6 +schZoomIn -win $_nSchema6 -pos 9992 18684 +schZoomIn -win $_nSchema6 -pos 10072 18709 +schZoomIn -win $_nSchema6 -pos 10111 18710 +schZoomIn -win $_nSchema6 -pos 10304 18768 +schZoomIn -win $_nSchema6 -pos 10304 18768 +schSelect -win $_nSchema6 -inst "inst_c3" +schPushViewIn -win $_nSchema6 +schPopViewUp -win $_nSchema6 +schPopViewUp -win $_nSchema6 +schPopViewUp -win $_nSchema6 +schZoomOut -win $_nSchema6 -pos 29185 34556 +schZoomOut -win $_nSchema6 -pos 29185 34556 +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top" -win $_nTrace1 +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.U_freqmod" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U0_channel_top.U_awg_top.U_freqmod" \ + -delim "." +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.U_freqmod" -win $_nTrace1 +schCreateWindow -delim "." -win $_nSchema1 -scope \ + "TB.U_digital_top.U0_channel_top.U_awg_top.U_freqmod" +schZoomIn -win $_nSchema7 -pos 24715 30970 +schZoomIn -win $_nSchema7 -pos 24715 30808 +schZoomIn -win $_nSchema7 -pos 24714 30728 +schZoomIn -win $_nSchema7 -pos 14681 32511 +schZoomIn -win $_nSchema7 -pos 14863 32579 +schSelect -win $_nSchema7 -inst "inst_isin_mult" +schPushViewIn -win $_nSchema7 +schSelect -win $_nSchema7 -inst "U1" +schPushViewIn -win $_nSchema7 +schSelect -win $_nSchema7 -inst "DW02_mult\(@5\):SigOp4:94:97:Combo" +schDisplaySource -win $_nSchema7 +srcCloseSourceTab -win $_nTrace1 -tab 2 +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.U_freqmod" -win $_nTrace1 +srcHBSelect "TB.U_digital_top.U0_channel_top.U_z_data_mux" -win $_nTrace1 +srcHBSelect "TB.U_digital_top.U0_channel_top.U_z_dsp" -win $_nTrace1 +srcHBSelect "TB.U_digital_top.U0_channel_top.U_z_dsp.inst_TailCorr_top" -win \ + $_nTrace1 +srcHBSelect \ + "TB.U_digital_top.U0_channel_top.U_z_dsp.inst_TailCorr_top.inst_iir_0" \ + -win $_nTrace1 +srcSetScope -win $_nTrace1 \ + "TB.U_digital_top.U0_channel_top.U_z_dsp.inst_TailCorr_top.inst_iir_0" \ + -delim "." +srcHBSelect \ + "TB.U_digital_top.U0_channel_top.U_z_dsp.inst_TailCorr_top.inst_iir_0" \ + -win $_nTrace1 +srcHBSelect \ + "TB.U_digital_top.U0_channel_top.U_z_dsp.inst_TailCorr_top.inst_iir_0.inst_c1" \ + -win $_nTrace1 +srcSetScope -win $_nTrace1 \ + "TB.U_digital_top.U0_channel_top.U_z_dsp.inst_TailCorr_top.inst_iir_0.inst_c1" \ + -delim "." +srcHBSelect \ + "TB.U_digital_top.U0_channel_top.U_z_dsp.inst_TailCorr_top.inst_iir_0.inst_c1" \ + -win $_nTrace1 +srcHBSelect \ + "TB.U_digital_top.U0_channel_top.U_z_dsp.inst_TailCorr_top.inst_iir_0" \ + -win $_nTrace1 +srcSetScope -win $_nTrace1 \ + "TB.U_digital_top.U0_channel_top.U_z_dsp.inst_TailCorr_top.inst_iir_0" \ + -delim "." +srcHBSelect \ + "TB.U_digital_top.U0_channel_top.U_z_dsp.inst_TailCorr_top.inst_iir_0" \ + -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -inst "inst_c1" -line 73 -pos 1 -win $_nTrace1 +srcAction -pos 72 13 2 -win $_nTrace1 -name "inst_c1" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -win $_nTrace1 -range {60 64 1 1 1 1} +srcDeselectAll -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "Re" -line 82 -pos 1 -win $_nTrace1 +srcSelect -win $_nTrace1 -range {82 84 3 1 1 1} +srcDeselectAll -win $_nTrace1 +srcSelect -signal "ac" -line 82 -pos 1 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "Re" -line 82 -pos 1 -win $_nTrace1 +srcHBSelect \ + "TB.U_digital_top.U0_channel_top.U_z_dsp.inst_TailCorr_top.inst_iir_0" \ + -win $_nTrace1 +srcSetScope -win $_nTrace1 \ + "TB.U_digital_top.U0_channel_top.U_z_dsp.inst_TailCorr_top.inst_iir_0" \ + -delim "." +srcHBSelect \ + "TB.U_digital_top.U0_channel_top.U_z_dsp.inst_TailCorr_top.inst_iir_0" \ + -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -inst "inst_c1" -line 73 -pos 1 -win $_nTrace1 +srcAction -pos 72 13 2 -win $_nTrace1 -name "inst_c1" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -win $_nTrace1 -range {60 66 1 1 1 1} -backward +srcDeselectAll -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "ac" -line 63 -pos 1 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "bd" -line 69 -pos 1 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "ad" -line 75 -pos 1 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "bc" -line 80 -pos 1 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "bd" -line 69 -pos 1 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "ac" -line 63 -pos 1 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -win $_nTrace1 -range {60 65 3 1 1 1} -backward +srcDeselectAll -win $_nTrace1 +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.U_freqmod" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U0_channel_top.U_awg_top.U_freqmod" \ + -delim "." +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.U_freqmod" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -inst "inst_isin_mult" -line 159 -pos 1 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -inst "inst_isin_mult" -line 159 -pos 1 -win $_nTrace1 +srcAction -pos 158 3 5 -win $_nTrace1 -name "inst_isin_mult" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -win $_nTrace1 -range {279 284 1 1 1 1} -backward +srcDeselectAll -win $_nTrace1 +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.U_freqmod.inst_isin_mult" \ + -win $_nTrace1 +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.U_freqmod.inst_isin_mult" \ + -win $_nTrace1 +srcSetScope -win $_nTrace1 \ + "TB.U_digital_top.U0_channel_top.U_awg_top.U_freqmod.inst_isin_mult" \ + -delim "." +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.U_freqmod.inst_isin_mult" \ + -win $_nTrace1 +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.U_freqmod" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U0_channel_top.U_awg_top.U_freqmod" \ + -delim "." +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.U_freqmod" -win $_nTrace1 +srcHBSelect "TB.U_digital_top.U0_channel_top.U_xy_dsp.inst_qam_top" -win \ + $_nTrace1 +srcHBSelect "TB.U_digital_top.U0_channel_top.U_xy_dsp.inst_qam_top.inst_nco_0" \ + -win $_nTrace1 +srcHBSelect "TB.U_digital_top.U0_channel_top.U_xy_dsp.inst_qam_top.inst_nco_0" \ + -win $_nTrace1 +srcHBSelect "TB.U_digital_top.U0_channel_top.U_xy_dsp.inst_qam_top.inst_nco_0" \ + -win $_nTrace1 +schCreateWindow -delim "." -win $_nSchema1 -scope \ + "TB.U_digital_top.U0_channel_top.U_awg_top.U_freqmod" +schZoomIn -win $_nSchema8 -pos 15663 31323 +schZoomIn -win $_nSchema8 -pos 15535 31195 +schZoomIn -win $_nSchema8 -pos 15312 31036 +schZoomIn -win $_nSchema8 -pos 893 29170 +schZoomIn -win $_nSchema8 -pos 874 29080 +schZoomIn -win $_nSchema8 -pos 860 29054 +schZoomIn -win $_nSchema8 -pos 769 29013 +schZoomIn -win $_nSchema8 -pos 769 29012 +schZoomOut -win $_nSchema8 -pos 1467 28631 +schZoomOut -win $_nSchema8 -pos 1502 28610 +schZoomOut -win $_nSchema8 -pos 1538 28592 +schZoomOut -win $_nSchema8 -pos 1627 28570 +schZoomOut -win $_nSchema8 -pos 1849 28528 +schSetOptions -win $_nSchema8 -portName on +schSetOptions -win $_nSchema8 -pinName on +schZoomIn -win $_nSchema8 -pos -316 22954 +schZoomIn -win $_nSchema8 -pos -225 22823 +schZoomIn -win $_nSchema8 -pos -226 22823 +schZoomIn -win $_nSchema8 -pos 131 23450 +schZoomIn -win $_nSchema8 -pos 136 23460 +schZoomOut -win $_nSchema8 -pos 161 23510 +schZoomOut -win $_nSchema8 -pos 161 23509 +schZoomOut -win $_nSchema8 -pos 162 23509 +schZoomOut -win $_nSchema8 -pos 170 23509 +schZoomOut -win $_nSchema8 -pos 210 23508 +schZoomOut -win $_nSchema8 -pos 749 23496 +schZoomIn -win $_nSchema8 -pos 686 29028 +schZoomIn -win $_nSchema8 -pos 708 29039 +schZoomIn -win $_nSchema8 -pos 708 29039 +schZoomIn -win $_nSchema8 -pos 707 29039 +schZoomOut -win $_nSchema8 -pos 1174 28295 +schZoomOut -win $_nSchema8 -pos 1174 28283 +schZoomOut -win $_nSchema8 -pos 1173 28267 +schZoomOut -win $_nSchema8 -pos 1174 28257 +schZoomOut -win $_nSchema8 -pos 1174 28221 +schZoomOut -win $_nSchema8 -pos 1265 27373 +schZoomOut -win $_nSchema8 -pos 1265 27240 +schZoomOut -win $_nSchema8 -pos 1265 27216 +schZoomOut -win $_nSchema8 -pos 1265 27216 +schZoomIn -win $_nSchema8 -pos 1633 29554 +schZoomIn -win $_nSchema8 -pos 1633 29554 +schZoomIn -win $_nSchema8 -pos 1633 29490 +schZoomIn -win $_nSchema8 -pos -81 28883 +schZoomIn -win $_nSchema8 -pos -94 28730 +schZoomIn -win $_nSchema8 -pos -94 28678 +schZoomIn -win $_nSchema8 -pos -94 28652 +schZoomOut -win $_nSchema8 -pos 197 28311 +schZoomOut -win $_nSchema8 -pos 197 28285 +schZoomOut -win $_nSchema8 -pos 197 28285 +schZoomOut -win $_nSchema8 -pos 197 28265 +schZoomOut -win $_nSchema8 -pos 198 28265 +schZoomOut -win $_nSchema8 -pos 198 28265 +schZoomOut -win $_nSchema8 -pos 199 28264 +schZoomOut -win $_nSchema8 -pos 199 28264 +schZoomOut -win $_nSchema8 -pos 200 28263 +srcHBSelect "TB.U_digital_top.U0_channel_top.U_xy_dsp.inst_qam_top.inst_nco_0" \ + -win $_nTrace1 +srcSetScope -win $_nTrace1 \ + "TB.U_digital_top.U0_channel_top.U_xy_dsp.inst_qam_top.inst_nco_0" \ + -delim "." +srcHBSelect "TB.U_digital_top.U0_channel_top.U_xy_dsp.inst_qam_top.inst_nco_0" \ + -win $_nTrace1 +schCreateWindow -delim "." -win $_nSchema1 -scope \ + "TB.U_digital_top.U0_channel_top.U_xy_dsp.inst_qam_top.inst_nco_0" +schSetOptions -win $_nSchema9 -pinName on +schZoomIn -win $_nSchema9 -pos -176 39046 +schZoomIn -win $_nSchema9 -pos 303 38898 +schZoomIn -win $_nSchema9 -pos 634 38760 +schZoomIn -win $_nSchema9 -pos 759 38718 +schZoomIn -win $_nSchema9 -pos 649 37907 +schZoomIn -win $_nSchema9 -pos 649 37779 +schZoomIn -win $_nSchema9 -pos 640 37673 +schSelect -win $_nSchema9 -signal "fcw\[47:0\]" +schSelect -win $_nSchema9 -instpin "NCO:SigOp0:112:112:Combo" "I0" +schFocusConnection -win $_nSchema9 +schSelect -win $_nSchema9 -inst "NCO:SigOp0:112:112:Combo" +schPushViewIn -win $_nSchema9 +srcSelect -win $_nTrace1 -range {112 112 1 9 1 1} +srcDeselectAll -win $_nTrace1 +debReload +srcDeselectAll -win $_nTrace1 +debReload +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.U_freqmod" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U0_channel_top.U_awg_top.U_freqmod" \ + -delim "." +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.U_freqmod" -win $_nTrace1 +srcSelect -signal "Mod_Vld" -line 51 -pos 1 -win $_nTrace1 +srcSelect -signal "Mod_Data_Q" -line 50 -pos 1 -win $_nTrace1 +srcSelect -signal "Mod_Data_I" -line 49 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 0 +wvZoom -win $_nWave3 1753134.205913 1785631.353597 +wvZoom -win $_nWave3 1763893.261577 1768532.854354 +wvSelectAll -win $_nWave3 +wvCut -win $_nWave3 +wvSetPosition -win $_nWave3 {("G4" 0)} +wvSetPosition -win $_nWave3 {("G4" 0)} +wvSetPosition -win $_nWave3 {("G4" 0)} +wvSetPosition -win $_nWave3 {("G4" 0)} +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "Env_Qdata" -line 39 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "Env_Idata" -line 38 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.U_awg_ctrl" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U0_channel_top.U_awg_top.U_awg_ctrl" \ + -delim "." +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.U_awg_ctrl" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "enve_index_vld_i" -line 88 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 0 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "enve_start_addr_i" -line 89 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvZoom -win $_nWave3 1733971.749120 1911151.411200 +wvZoom -win $_nWave3 1764065.033264 1772569.657044 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "enve_len_i" -line 90 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "enve_rddata_i" -line 96 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvZoom -win $_nWave3 1766590.252325 1768934.911680 +wvZoom -win $_nWave3 1767305.914503 1767842.661137 +wvScrollDown -win $_nWave3 1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "enve_idata_o" -line 98 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "enve_vld_o" -line 100 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.U_freqmod" -win $_nTrace1 +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.U_freqmod" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U0_channel_top.U_awg_top.U_freqmod" \ + -delim "." +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.U_freqmod" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "Env_Vld" -line 40 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "Env_Qdata" -line 39 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "Env_Idata" -line 38 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 1757258.182664 1786684.449826 +wvZoom -win $_nWave3 1766221.876353 1770622.235074 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "Env_Idata" -line 38 -pos 1 -win $_nTrace1 +srcAction -pos 37 12 4 -win $_nTrace1 -name "Env_Idata" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -signal "mod_enable" -line 364 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "Amod_Data_I" -line 364 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "Amod_Data_I" -line 364 -pos 1 -win $_nTrace1 +srcAction -pos 363 21 5 -win $_nTrace1 -name "Amod_Data_I" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -signal "I_Amp_tmp_r" -line 90 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "I_Amp_tmp_r" -line 90 -pos 1 -win $_nTrace1 +srcAction -pos 89 6 6 -win $_nTrace1 -name "I_Amp_tmp_r" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -signal "Dig_Resetn" -line 73 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 0 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "I_Amp_tmp\[30:16\]" -line 77 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "Mod_Vld" -line 9 -pos 1 -win $_nTrace1 +srcSelect -signal "Mod_Data_I" -line 7 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "Amod_Enable" -line 12 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "Amp" -line 11 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +debReload +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +srcDeselectAll -win $_nTrace1 +debReload +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 1805639.927040 2146063.772160 +wvZoom -win $_nWave3 1959406.759236 1983707.784487 +wvZoom -win $_nWave3 1967138.223884 1969904.802144 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.U_freqmod" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U0_channel_top.U_awg_top.U_freqmod" \ + -delim "." +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.U_freqmod" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "Env_Idata" -line 38 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "Env_Vld" -line 40 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcSelect -signal "Mod_Vld" -line 51 -pos 1 -win $_nTrace1 +srcSelect -signal "Mod_Data_Q" -line 50 -pos 1 -win $_nTrace1 +srcSelect -signal "Mod_Data_I" -line 49 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 0 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "Mod_Vld" -line 51 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvSelectSignal -win $_nWave3 {( "G4" 30 )} +wvSelectAll -win $_nWave3 +wvCut -win $_nWave3 +wvSetPosition -win $_nWave3 {("G4" 0)} +wvSetPosition -win $_nWave3 {("G4" 0)} +wvSetPosition -win $_nWave3 {("G4" 0)} +wvSetPosition -win $_nWave3 {("G4" 0)} +srcSelect -signal "Mod_Data_Q" -line 50 -pos 1 -win $_nTrace1 +srcSelect -signal "Mod_Data_I" -line 49 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "Mod_Vld" -line 51 -pos 1 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "Mod_Vld" -line 51 -pos 1 -win $_nTrace1 +srcAction -pos 50 4 5 -win $_nTrace1 -name "Mod_Vld" -ctrlKey off +srcDeselectAll -win $_nTrace1 +debReload +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 0 +wvZoom -win $_nWave3 1826218.942408 1863701.395921 +wvZoom -win $_nWave3 1837152.285770 1842180.701072 +wvZoom -win $_nWave3 1838294.122845 1838950.137641 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.U_freqmod" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U0_channel_top.U_awg_top.U_freqmod" \ + -delim "." +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.U_freqmod" -win $_nTrace1 +srcSelect -signal "Env_Vld" -line 40 -pos 1 -win $_nTrace1 +srcSelect -signal "Env_Qdata" -line 39 -pos 1 -win $_nTrace1 +srcSelect -signal "Env_Idata" -line 38 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvScrollUp -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +srcHBSelect "TB.U_digital_top" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top" -delim "." +srcHBSelect "TB.U_digital_top" -win $_nTrace1 +srcSelect -signal "sclk" -line 58 -pos 1 -win $_nTrace1 +srcSelect -signal "csn" -line 59 -pos 1 -win $_nTrace1 +srcSelect -signal "mosi" -line 60 -pos 1 -win $_nTrace1 +srcSelect -signal "miso" -line 61 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvSelectAll -win $_nWave3 +wvCut -win $_nWave3 +wvSetPosition -win $_nWave3 {("G4" 0)} +wvSetPosition -win $_nWave3 {("G4" 0)} +wvSetPosition -win $_nWave3 {("G4" 0)} +wvSetPosition -win $_nWave3 {("G4" 0)} +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +verdiDockWidgetMaximize -dock windowDock_nWave_3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 0.000000 336442.279680 +wvZoom -win $_nWave3 621.124209 12215.442770 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 2368.808469 10859.417139 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 9101.932494 10606.729599 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 2074.304933 11230.879568 +wvZoom -win $_nWave3 9298.137968 10171.534318 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 2717.471966 13656.156588 +wvSetCursor -win $_nWave3 3101.167365 -snap {("G4" 1)} +wvSetCursor -win $_nWave3 3195.408340 -snap {("G4" 1)} +wvSetCursor -win $_nWave3 3303.112312 -snap {("G4" 1)} +wvSetCursor -win $_nWave3 3383.890290 -snap {("G4" 1)} +wvSetCursor -win $_nWave3 3498.325760 -snap {("G4" 1)} +wvSetCursor -win $_nWave3 3572.372241 -snap {("G4" 1)} +wvSetCursor -win $_nWave3 3680.076213 -snap {("G4" 1)} +wvSetCursor -win $_nWave3 3767.585690 -snap {("G4" 1)} +wvSetCursor -win $_nWave3 3848.363668 -snap {("G4" 1)} +wvSetCursor -win $_nWave3 3094.435867 -snap {("G4" 1)} +wvSetCursor -win $_nWave3 3181.945344 -snap {("G4" 1)} +wvSetCursor -win $_nWave3 3289.649315 -snap {("G4" 1)} +wvSetCursor -win $_nWave3 3383.890290 -snap {("G4" 1)} +wvSetCursor -win $_nWave3 3498.325760 -snap {("G4" 1)} +wvSetCursor -win $_nWave3 3572.372241 -snap {("G4" 1)} +wvSetCursor -win $_nWave3 3680.076213 -snap {("G4" 1)} +wvSetCursor -win $_nWave3 3794.511682 -snap {("G4" 1)} +wvSetCursor -win $_nWave3 3868.558163 -snap {("G4" 1)} +wvSetCursor -win $_nWave3 3996.456629 -snap {("G4" 1)} +wvSetCursor -win $_nWave3 4097.429103 -snap {("G4" 1)} +wvSetCursor -win $_nWave3 4198.401576 -snap {("G4" 1)} +wvSetCursor -win $_nWave3 4299.374050 -snap {("G4" 1)} +wvSetCursor -win $_nWave3 4380.152028 -snap {("G4" 1)} +wvSetCursor -win $_nWave3 4508.050495 -snap {("G4" 1)} +wvSetCursor -win $_nWave3 4602.291470 -snap {("G4" 1)} +wvSetCursor -win $_nWave3 4676.337950 -snap {("G4" 1)} +wvSetCursor -win $_nWave3 4784.041922 -snap {("G4" 1)} +wvSetCursor -win $_nWave3 4891.745894 -snap {("G4" 1)} +wvSetCursor -win $_nWave3 4992.718367 -snap {("G4" 1)} +wvSetCursor -win $_nWave3 5100.422339 -snap {("G4" 1)} +wvSetCursor -win $_nWave3 5181.200318 -snap {("G4" 1)} +wvSetCursor -win $_nWave3 5295.635787 -snap {("G4" 1)} +wvSetCursor -win $_nWave3 5389.876763 -snap {("G4" 1)} +wvSetCursor -win $_nWave3 5497.580734 -snap {("G4" 1)} +wvSetCursor -win $_nWave3 5585.090211 -snap {("G4" 1)} +wvSetCursor -win $_nWave3 5686.062685 -snap {("G4" 1)} +wvSetCursor -win $_nWave3 5787.035158 -snap {("G4" 1)} +wvSetCursor -win $_nWave3 5874.544635 -snap {("G4" 1)} +wvSetCursor -win $_nWave3 6015.906098 -snap {("G4" 1)} +wvSetCursor -win $_nWave3 6103.415575 -snap {("G4" 1)} +wvSetCursor -win $_nWave3 6184.193554 -snap {("G4" 1)} +wvSetCursor -win $_nWave3 6271.703031 -snap {("G4" 1)} +wvSetCursor -win $_nWave3 6386.138501 -snap {("G4" 1)} +wvSetCursor -win $_nWave3 6487.110974 -snap {("G4" 1)} +wvSetCursor -win $_nWave3 6594.814946 -snap {("G4" 1)} +wvSetCursor -win $_nWave3 6709.250416 -snap {("G4" 1)} +wvSetCursor -win $_nWave3 6796.759893 -snap {("G4" 1)} +wvSetCursor -win $_nWave3 6904.463864 -snap {("G4" 1)} +wvSetCursor -win $_nWave3 7012.167836 -snap {("G4" 1)} +wvSetCursor -win $_nWave3 7079.482818 -snap {("G4" 1)} +wvSetCursor -win $_nWave3 7200.649786 -snap {("G4" 1)} +wvSetCursor -win $_nWave3 7288.159263 -snap {("G4" 1)} +wvSetCursor -win $_nWave3 7382.400238 -snap {("G4" 1)} +wvSetCursor -win $_nWave3 7490.104210 -snap {("G4" 1)} +wvSetCursor -win $_nWave3 7611.271178 -snap {("G4" 1)} +wvSetCursor -win $_nWave3 7705.512153 -snap {("G4" 1)} +wvSetCursor -win $_nWave3 7793.021630 -snap {("G4" 1)} +wvSetCursor -win $_nWave3 7900.725602 -snap {("G4" 1)} +wvSetCursor -win $_nWave3 7994.966577 -snap {("G4" 1)} +wvSetCursor -win $_nWave3 8102.670549 -snap {("G4" 1)} +wvSetCursor -win $_nWave3 8210.374521 -snap {("G4" 1)} +wvSetCursor -win $_nWave3 8291.152499 -snap {("G4" 1)} +wvSetCursor -win $_nWave3 8385.393475 -snap {("G4" 1)} +wvSetCursor -win $_nWave3 8486.365948 -snap {("G4" 1)} +wvSetCursor -win $_nWave3 8600.801418 -snap {("G4" 1)} +wvSetCursor -win $_nWave3 8701.773891 -snap {("G4" 1)} +wvSetCursor -win $_nWave3 8802.746365 -snap {("G4" 1)} +wvSetCursor -win $_nWave3 8890.255842 -snap {("G4" 1)} +wvSetCursor -win $_nWave3 8997.959813 -snap {("G4" 1)} +wvSetCursor -win $_nWave3 9092.200789 -snap {("G4" 1)} +wvSetCursor -win $_nWave3 9193.173262 -snap {("G4" 1)} +wvSetCursor -win $_nWave3 9273.951241 -snap {("G4" 1)} +wvSetCursor -win $_nWave3 9374.923714 -snap {("G4" 1)} +wvZoom -win $_nWave3 9455.701693 9563.405665 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 2290.614930 5293.865615 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomIn -win $_nWave3 +wvZoomOut -win $_nWave3 +wvSetCursor -win $_nWave3 194022.931364 -snap {("G5" 0)} +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 2795058.938880 3039925.213440 +wvZoom -win $_nWave3 2923142.836342 2974677.769203 +wvZoom -win $_nWave3 2934623.233693 2948006.459335 +wvZoomOut -win $_nWave3 +verdiDockWidgetRestore -dock windowDock_nWave_3 +srcHBSelect "TB.U_digital_top.U_spi_slave" -win $_nTrace1 +srcHBSelect "TB.U_digital_top.U_spi_slave.U_spi_sys" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U_spi_slave.U_spi_sys" -delim "." +srcHBSelect "TB.U_digital_top.U_spi_slave.U_spi_sys" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "oen" -line 57 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcSelect -signal "miso" -line 56 -pos 1 -win $_nTrace1 +srcSelect -signal "mosi" -line 55 -pos 1 -win $_nTrace1 +srcSelect -signal "csn" -line 54 -pos 1 -win $_nTrace1 +srcSelect -signal "sclk" -line 53 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 0 +wvZoom -win $_nWave3 2934932.077361 2944073.849953 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvZoom -win $_nWave3 2919622.327015 3026195.705466 +wvZoom -win $_nWave3 2933788.388396 2962841.930952 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "rddata_sr" -line 273 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 0 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "spi_dout" -line 273 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvZoom -win $_nWave3 2944390.696540 2947698.330616 +wvSetCursor -win $_nWave3 2945219.131659 -snap {("G4" 10)} +wvSetCursor -win $_nWave3 2945267.982870 -snap {("G4" 10)} +srcHBSelect "TB.U_digital_top.U_spi_bus_decoder" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U_spi_bus_decoder" -delim "." +srcHBSelect "TB.U_digital_top.U_spi_bus_decoder" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -word -line 40 -pos 6 -win $_nTrace1 +wvDrop -win $_nWave3 +wvSelectSignal -win $_nWave3 {( "G4" 11 )} +wvSelectAll -win $_nWave3 +wvCut -win $_nWave3 +wvSetPosition -win $_nWave3 {("G4" 0)} +wvSetPosition -win $_nWave3 {("G4" 0)} +wvSetPosition -win $_nWave3 {("G4" 0)} +wvSetPosition -win $_nWave3 {("G4" 0)} +srcDeselectAll -win $_nTrace1 +srcSelect -word -line 40 -pos 6 -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -word -line 40 -pos 6 -win $_nTrace1 +srcAction -pos 40 6 1 -win $_nTrace1 -name "mst" -ctrlKey off +srcSelect -signal "rden" -line 24 -pos 1 -win $_nTrace1 +srcSelect -signal "din" -line 21 -pos 1 -win $_nTrace1 +srcSelect -toggle -signal "din" -line 21 -pos 1 -win $_nTrace1 +srcSelect -signal "dout" -line 22 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 0 +wvZoom -win $_nWave3 2944696.016609 2945101.074566 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +srcBackwardHistory -win $_nTrace1 +srcHBSelect "TB.U_digital_top.U_spi_bus_decoder" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "clk" -line 39 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvScrollDown -win $_nWave3 1 +wvSetCursor -win $_nWave3 2944883.091068 -snap {("G4" 3)} +srcHBSelect "TB.U_digital_top.U_spi_bus_decoder.slv\[0\]" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U_spi_bus_decoder.slv\[0\]" -delim \ + "." +srcHBSelect "TB.U_digital_top.U_spi_bus_decoder.slv\[0\]" -win $_nTrace1 +srcHBSelect "TB.U_digital_top.U_spi_bus_decoder.slv\[0\].read" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U_spi_bus_decoder.slv\[0\].read" \ + -delim "." +srcHBSelect "TB.U_digital_top.U_spi_bus_decoder.slv\[0\].read" -win $_nTrace1 +srcShowCalling -win $_nTrace1 +srcBackwardHistory -win $_nTrace1 +srcHBSelect "TB.U_digital_top.U_spi_bus_decoder.slv\[0\].read" -win $_nTrace1 +srcBackwardHistory -win $_nTrace1 +srcHBSelect "TB.U_digital_top.U_spi_bus_decoder.slv\[0\]" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "rden" -line 15 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 2946398.132463 2950992.611400 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 0 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +srcHBSelect "TB.U_digital_top.U_spi_bus_decoder.slv\[1\]" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U_spi_bus_decoder.slv\[1\]" -delim \ + "." +srcHBSelect "TB.U_digital_top.U_spi_bus_decoder.slv\[1\]" -win $_nTrace1 +srcHBSelect "TB.U_digital_top.U_spi_bus_decoder.slv\[7\]" -win $_nTrace1 +srcHBSelect "TB.U_digital_top.U_spi_bus_decoder.slv\[6\]" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U_spi_bus_decoder.slv\[6\]" -delim \ + "." +srcHBSelect "TB.U_digital_top.U_spi_bus_decoder.slv\[6\]" -win $_nTrace1 +srcHBSelect "TB.U_digital_top.U_spi_bus_decoder.slv\[6\].read" -win $_nTrace1 +srcHBSelect "TB.U_digital_top.U_spi_bus_decoder.slv\[6\].read" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U_spi_bus_decoder.slv\[6\].read" \ + -delim "." +srcHBSelect "TB.U_digital_top.U_spi_bus_decoder.slv\[6\].read" -win $_nTrace1 +srcBackwardHistory -win $_nTrace1 +srcHBSelect "TB.U_digital_top.U_spi_bus_decoder.slv\[6\]" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "rden" -line 15 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +srcHBSelect "TB.U_digital_top.U_spi_bus_decoder.slv\[5\]" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U_spi_bus_decoder.slv\[5\]" -delim \ + "." +srcHBSelect "TB.U_digital_top.U_spi_bus_decoder.slv\[5\]" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "rden" -line 15 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvSelectSignal -win $_nWave3 {( "G4" 4 )} +wvSelectAll -win $_nWave3 +wvCut -win $_nWave3 +wvSetPosition -win $_nWave3 {("G4" 0)} +wvSetPosition -win $_nWave3 {("G4" 0)} +wvSetPosition -win $_nWave3 {("G4" 0)} +wvSetPosition -win $_nWave3 {("G4" 0)} +srcHBSelect "TB.U_digital_top.U_spi_slave.U_spi_sys" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U_spi_slave.U_spi_sys" -delim "." +srcHBSelect "TB.U_digital_top.U_spi_slave.U_spi_sys" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "rden" -line 62 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvScrollDown -win $_nWave3 0 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 2876681.030400 3101639.477760 +wvZoom -win $_nWave3 2947975.553717 2961126.970640 +wvZoom -win $_nWave3 2950856.725671 2952256.845749 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 2931153.805119 2955857.954591 +wvZoom -win $_nWave3 2943239.835168 2945459.407982 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "rddata" -line 63 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvZoom -win $_nWave3 2944739.583445 2945214.913500 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "sclk" -line 53 -pos 1 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "clk" -line 48 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvSetCursor -win $_nWave3 2944910.117242 -snap {("G4" 3)} +wvSetCursor -win $_nWave3 2944943.755985 -snap {("G4" 3)} +wvSetCursor -win $_nWave3 2944976.224684 -snap {("G4" 3)} +srcDeselectAll -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "rddata_vld" -line 260 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "rddata\[31:0\]" -line 260 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "rddata_reg" -line 260 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvScrollUp -win $_nWave3 1 +wvSetCursor -win $_nWave3 2944910.994775 -snap {("G4" 3)} +wvSetCursor -win $_nWave3 2944941.123387 -snap {("G4" 3)} +wvSetCursor -win $_nWave3 2944974.177108 -snap {("G4" 3)} +wvSetCursor -win $_nWave3 2945006.645807 -snap {("G4" 3)} +wvSetCursor -win $_nWave3 2945041.747104 -snap {("G4" 3)} +wvSetCursor -win $_nWave3 2945072.460738 -snap {("G4" 3)} +wvScrollDown -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +srcHBSelect "TB.U_digital_top" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top" -delim "." +srcHBSelect "TB.U_digital_top" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -inst "U_debug_top" -line 1244 -pos 1 -win $_nTrace1 +srcAction -pos 1243 2 5 -win $_nTrace1 -name "U_debug_top" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -signal "dbg_sramb_dout" -line 144 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvSetCursor -win $_nWave3 2944941.708409 -snap {("G4" 7)} +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvSetCursor -win $_nWave3 2944910.994775 -snap {("G4" 1)} +wvScrollDown -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +wvSetCursor -win $_nWave3 2944943.755985 -snap {("G4" 3)} +wvScrollDown -win $_nWave3 1 +wvScrollDown -win $_nWave3 0 +wvScrollUp -win $_nWave3 1 +wvScrollUp -win $_nWave3 1 +verdiDockWidgetMaximize -dock windowDock_nWave_3 +wvSetCursor -win $_nWave3 2944876.185989 -snap {("G2" 0)} +wvSetPosition -win $_nWave3 {("G4" 7)} +wvSetPosition -win $_nWave3 {("G4" 7)} +wvSetPosition -win $_nWave3 {("G4" 7)} +wvDisplayGridCount -win $_nWave3 -off +wvGetSignalClose -win $_nWave3 +wvReloadFile -win $_nWave3 +wvSelectSignal -win $_nWave3 {( "G4" 6 )} +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvSetCursor -win $_nWave3 2944273.467480 -snap {("G4" 4)} +srcActiveTrace "TB.U_digital_top.U_spi_slave.U_spi_sys.rddata_vld" -win $_nTrace1 \ + -TraceByDConWave -TraceTime 0 -TraceValue 0 +wvSetCursor -win $_nWave3 2945093.667772 -snap {("G4" 4)} +srcActiveTrace "TB.U_digital_top.U_spi_slave.U_spi_sys.rddata_vld" -win $_nTrace1 \ + -TraceByDConWave -TraceTime 2945072000 -TraceValue 1 +verdiDockWidgetRestore -dock windowDock_nWave_3 +srcDeselectAll -win $_nTrace1 +debReload +verdiDockWidgetMaximize -dock windowDock_nWave_3 +wvSelectSignal -win $_nWave3 {( "G4" 5 )} +wvSelectSignal -win $_nWave3 {( "G4" 6 )} +verdiDockWidgetRestore -dock windowDock_nWave_3 +srcHBSelect "TB.U_digital_top.U_spi_bus_decoder" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U_spi_bus_decoder" -delim "." +srcHBSelect "TB.U_digital_top.U_spi_bus_decoder" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "rden_dly\[2\]" -line 82 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +verdiDockWidgetMaximize -dock windowDock_nWave_3 +wvSelectSignal -win $_nWave3 {( "G4" 8 )} +wvSetPosition -win $_nWave3 {("G4" 7)} +wvSetPosition -win $_nWave3 {("G4" 6)} +wvSetPosition -win $_nWave3 {("G4" 5)} +wvSetPosition -win $_nWave3 {("G4" 4)} +wvSetPosition -win $_nWave3 {("G4" 3)} +wvSetPosition -win $_nWave3 {("G4" 2)} +wvSetPosition -win $_nWave3 {("G4" 1)} +wvSetPosition -win $_nWave3 {("G4" 0)} +wvMoveSelected -win $_nWave3 +wvSetPosition -win $_nWave3 {("G4" 0)} +wvSetPosition -win $_nWave3 {("G4" 1)} +wvSetPosition -win $_nWave3 {("G4" 1)} +wvSetPosition -win $_nWave3 {("G4" 1)} +wvSetPosition -win $_nWave3 {("G4" 1)} +wvZoomIn -win $_nWave3 +wvSetCursor -win $_nWave3 2944912.603584 -snap {("G4" 4)} +wvSetCursor -win $_nWave3 2944945.364794 -snap {("G4" 4)} +wvSetCursor -win $_nWave3 2944975.200896 -snap {("G4" 4)} +wvSelectSignal -win $_nWave3 {( "G4" 8 )} +wvSetCursor -win $_nWave3 2944944.779773 -snap {("G4" 8)} +wvSetCursor -win $_nWave3 2944978.711026 -snap {("G4" 4)} +wvSetCursor -win $_nWave3 2944911.433541 -snap {("G4" 4)} +wvSetCursor -win $_nWave3 2944945.949816 -snap {("G4" 4)} +wvSetCursor -win $_nWave3 2944976.955961 -snap {("G4" 4)} +wvSetCursor -win $_nWave3 2944910.848519 -snap {("G4" 4)} +wvSetCursor -win $_nWave3 2944795.014242 -snap {("G4" 8)} +srcActiveTrace "TB.U_digital_top.U_debug_top.dbg_sramb_dout\[255:0\]" -win \ + $_nTrace1 -TraceByDConWave -TraceTime 0 -TraceValue \ + xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +verdiDockWidgetRestore -dock windowDock_nWave_3 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "PortBChipEnable" -line 173 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +verdiDockWidgetMaximize -dock windowDock_nWave_3 +wvSetCursor -win $_nWave3 2944914.358649 -snap {("G4" 3)} +wvSetCursor -win $_nWave3 2944941.269643 -snap {("G4" 2)} +wvSetCursor -win $_nWave3 2944975.785918 -snap {("G4" 1)} +verdiDockWidgetRestore -dock windowDock_nWave_3 +srcDeselectAll -win $_nTrace1 +debReload +verdiDockWidgetMaximize -dock windowDock_nWave_3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +verdiWindowBeWindow -win $_nWave3 +wvResizeWindow -win $_nWave3 -10 97 2560 1260 +wvSetCursor -win $_nWave3 523839.646228 -snap {("G5" 0)} +wvSetPosition -win $_nWave3 {("G4" 2)} +wvSetPosition -win $_nWave3 {("G4" 2)} +wvSetPosition -win $_nWave3 {("G4" 2)} +wvDisplayGridCount -win $_nWave3 -off +wvGetSignalClose -win $_nWave3 +wvReloadFile -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 2814966.766080 3067796.171520 +wvZoom -win $_nWave3 2924811.418536 2976310.823582 +wvZoom -win $_nWave3 2942653.981637 2948960.678009 +wvZoom -win $_nWave3 2944423.737665 2945747.173642 +wvSelectSignal -win $_nWave3 {( "G4" 1 )} +wvSetCursor -win $_nWave3 2944630.600888 -snap {("G4" 1)} +srcActiveTrace "TB.U_digital_top.U_spi_bus_decoder.OUT_REG.rden_dly\[2\]" -win \ + $_nTrace1 -TraceByDConWave -TraceTime 0 -TraceValue 0 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "dnxt" -line 277 -pos 1 -win $_nTrace1 +srcAction -pos 276 12 2 -win $_nTrace1 -name "dnxt" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -signal "dnxt" -line 263 -pos 1 -win $_nTrace1 +srcAction -pos 262 11 2 -win $_nTrace1 -name "dnxt" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -signal "dnxt" -line 263 -pos 1 -win $_nTrace1 +srcAction -pos 262 11 2 -win $_nTrace1 -name "dnxt" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -signal "dnxt" -line 263 -pos 1 -win $_nTrace1 +srcAction -pos 262 11 2 -win $_nTrace1 -name "dnxt" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -signal "dnxt" -line 263 -pos 1 -win $_nTrace1 +srcAction -pos 262 11 2 -win $_nTrace1 -name "dnxt" -ctrlKey off +verdiDockWidgetSetCurTab -dock widgetDock_ +verdiDockWidgetSetCurTab -dock widgetDock_MTB_SOURCE_TAB_1 +srcShowCalling -win $_nTrace1 +srcSelect -win $_nTrace1 -range {81 81 9 10 1 1} +srcHBSelect "TB.U_digital_top.U_spi_bus_decoder.OUT_REG" -win $_nTrace1 +srcShowCalling -win $_nTrace1 +srcSelect -win $_nTrace1 -range {79 79 14 15 1 1} +srcHBSelect "TB.U_digital_top.U_spi_bus_decoder" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "rden_dly\[3\]" -line 82 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvSelectSignal -win $_nWave3 {( "G4" 1 )} +wvCut -win $_nWave3 +wvSetPosition -win $_nWave3 {("G4" 3)} +wvSetPosition -win $_nWave3 {("G4" 2)} +wvSetPosition -win $_nWave3 {("G4" 2)} +wvSetPosition -win $_nWave3 {("G4" 2)} +wvSetPosition -win $_nWave3 {("G4" 2)} +wvSelectSignal -win $_nWave3 {( "G4" 2 )} +wvSetCursor -win $_nWave3 2944913.205371 -snap {("G4" 5)} +wvSetCursor -win $_nWave3 2944940.895724 -snap {("G4" 5)} +wvSetCursor -win $_nWave3 2944975.101454 -snap {("G4" 5)} +wvSetCursor -win $_nWave3 2945007.678339 -snap {("G4" 5)} +wvSetCursor -win $_nWave3 2945041.884069 -snap {("G4" 3)} +wvSetCursor -win $_nWave3 2945039.440803 -snap {("G4" 7)} +wvSetCursor -win $_nWave3 2945105.408996 -snap {("G4" 6)} +srcShowCalling -win $_nTrace1 +srcSelect -win $_nTrace1 -range {464 464 4 5 1 1} +srcHBSelect "TB.U_digital_top" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -inst "U_spi_slave" -line 364 -pos 1 -win $_nTrace1 +srcAction -pos 363 2 5 -win $_nTrace1 -name "U_spi_slave" -ctrlKey off +schCreateWindow -delim "." -win $_nSchema1 -scope "TB.U_digital_top.U_spi_slave" +schSelect -win $_nSchema10 -inst "U_spi_sys" +schPushViewIn -win $_nSchema10 +schZoomIn -win $_nSchema10 -pos 157473 2199 +schZoomIn -win $_nSchema10 -pos 157473 1708 +schZoomIn -win $_nSchema10 -pos 157474 1616 +schSetOptions -win $_nSchema10 -portName on +schSetOptions -win $_nSchema10 -pinName on +schZoomIn -win $_nSchema10 -pos 154720 556 +schZoomIn -win $_nSchema10 -pos 154720 246 +schZoomIn -win $_nSchema10 -pos 154721 14 +schZoomIn -win $_nSchema10 -pos 155621 304 +schZoomIn -win $_nSchema10 -pos 155621 303 +schZoomIn -win $_nSchema10 -pos 155637 319 +schZoomOut -win $_nSchema10 -pos 155648 1115 +schZoomOut -win $_nSchema10 -pos 155649 1146 +schZoomOut -win $_nSchema10 -pos 155648 1165 +schZoomOut -win $_nSchema10 -pos 155600 1213 +schZoomOut -win $_nSchema10 -pos 155569 1362 +schZoomOut -win $_nSchema10 -pos 155531 2110 +schZoomOut -win $_nSchema10 -pos 155530 2110 +schZoomOut -win $_nSchema10 -pos 155530 1935 +schZoomOut -win $_nSchema10 -pos 155529 1935 +schZoomOut -win $_nSchema10 -pos 155529 1934 +schZoomIn -win $_nSchema10 -pos -3317 565 +schZoomIn -win $_nSchema10 -pos 1304 -34 +schZoomIn -win $_nSchema10 -pos 1689 -34 +schZoomIn -win $_nSchema10 -pos 1832 -34 +schZoomIn -win $_nSchema10 -pos 207 8451 +schZoomIn -win $_nSchema10 -pos 207 8505 +schZoomIn -win $_nSchema10 -pos 206 8544 +schZoomIn -win $_nSchema10 -pos 875 -7079 +schZoomIn -win $_nSchema10 -pos 875 -7079 +schZoomIn -win $_nSchema10 -pos 831 -7071 +schSelect -win $_nSchema10 -signal "rddata\[31:0\]" +schZoomOut -win $_nSchema10 -pos 4051 -7033 +schZoomOut -win $_nSchema10 -pos 4011 -7041 +schZoomOut -win $_nSchema10 -pos 3810 -7061 +schZoomOut -win $_nSchema10 -pos 3610 -7062 +schZoomOut -win $_nSchema10 -pos 3343 -7062 +schZoomOut -win $_nSchema10 -pos 3284 -7042 +schZoomOut -win $_nSchema10 -pos 3260 -7043 +schZoomOut -win $_nSchema10 -pos 3199 -7043 +schZoomOut -win $_nSchema10 -pos 3122 -7044 +schZoomOut -win $_nSchema10 -pos 3074 -7044 +schZoomOut -win $_nSchema10 -pos 3014 -7103 +schZoomOut -win $_nSchema10 -pos 2865 -6954 +schZoomOut -win $_nSchema10 -pos 2865 -6955 +schZoomIn -win $_nSchema10 -pos 127214 -2398 +schZoomIn -win $_nSchema10 -pos 127215 -2573 +schZoomIn -win $_nSchema10 -pos 125965 -2508 +schZoomIn -win $_nSchema10 -pos 125965 -2508 +schZoomIn -win $_nSchema10 -pos 125965 -2508 +schZoomIn -win $_nSchema10 -pos 124717 -456 +schZoomIn -win $_nSchema10 -pos 124717 -456 +schZoomIn -win $_nSchema10 -pos 124717 -456 +schZoomIn -win $_nSchema10 -pos 124565 -538 +schZoomIn -win $_nSchema10 -pos 124556 -547 +schSelect -win $_nSchema10 -inst "rddata_reg_dfflr" +schPushViewIn -win $_nSchema10 +schZoomOut -win $_nSchema10 -pos 9040 2789 +schZoomOut -win $_nSchema10 -pos 9033 2782 +schZoomOut -win $_nSchema10 -pos 9033 2781 +schZoomOut -win $_nSchema10 -pos 9021 2781 +schZoomIn -win $_nSchema10 -pos 2216 2996 +schZoomIn -win $_nSchema10 -pos 2215 2966 +schSelect -win $_nSchema10 -inst "DFFLR_PROC" +schPushViewIn -win $_nSchema10 +srcSetScope -win $_nTrace1 \ + "TB.U_digital_top.U_spi_slave.U_spi_sys.rddata_reg_dfflr" -delim \ + "." +srcSelect -win $_nTrace1 -range {102 108 1 2 1 1} +srcShowCalling -win $_nTrace1 +srcSelect -win $_nTrace1 -range {260 260 8 9 1 1} +srcHBSelect "TB.U_digital_top.U_spi_slave.U_spi_sys" -win $_nTrace1 +verdiDockWidgetSetCurTab -dock windowDock_nSchema_10 +verdiDockWidgetSetCurTab -dock widgetDock_MTB_SOURCE_TAB_1 +wvSetCursor -win $_nWave3 2944957.184167 -snap {("G4" 9)} +srcActiveTrace "TB.U_digital_top.U_debug_top.dbg_sramb_dout\[255:0\]" -win \ + $_nTrace1 -TraceByDConWave -TraceTime 2944943010 -TraceValue \ + 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "PortBAddr\[ADDRWIDTH-1:LSB\]" -line 176 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvSetPosition -win $_nWave3 {("G4" 4)} +wvSetPosition -win $_nWave3 {("G4" 5)} +wvSetPosition -win $_nWave3 {("G4" 6)} +wvSetPosition -win $_nWave3 {("G4" 7)} +wvSetPosition -win $_nWave3 {("G4" 8)} +wvSetPosition -win $_nWave3 {("G4" 9)} +wvSetPosition -win $_nWave3 {("G4" 10)} +wvMoveSelected -win $_nWave3 +wvSetPosition -win $_nWave3 {("G4" 10)} +wvSetPosition -win $_nWave3 {("G4" 10)} +wvSetPosition -win $_nWave3 {("G4" 10)} +wvSetPosition -win $_nWave3 {("G4" 10)} +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 2951055.723686 3026112.868086 +wvZoom -win $_nWave3 2967083.310828 2993780.559728 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 2961637.072051 3042336.694574 +wvZoom -win $_nWave3 2967199.138342 2987858.241708 +wvSelectSignal -win $_nWave3 {( "G4" 6 )} +wvZoom -win $_nWave3 2969042.566026 2976670.542653 +wvZoom -win $_nWave3 2970079.970846 2971826.190727 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 2970366.350906 2971354.980007 +wvZoomOut -win $_nWave3 +srcShowCalling -win $_nTrace1 +srcSelect -win $_nTrace1 -range {157 157 27 28 1 1} +srcHBSelect "TB.U_digital_top.U_debug_top.U_dbg_sram.U_tsmc_dpram" -win $_nTrace1 +srcShowCalling -win $_nTrace1 +srcSelect -win $_nTrace1 -range {70 70 4 5 1 1} +srcHBSelect "TB.U_digital_top.U_debug_top.U_dbg_sram" -win $_nTrace1 +srcShowCalling -win $_nTrace1 +srcSelect -win $_nTrace1 -range {131 131 4 5 1 1} +srcHBSelect "TB.U_digital_top.U_debug_top" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -inst "U_sram_dmux_w" -line 154 -pos 1 -win $_nTrace1 +srcAction -pos 153 3 7 -win $_nTrace1 -name "U_sram_dmux_w" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -win $_nTrace1 -signal "port_out.addr" -line 68 -pos 1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvSelectSignal -win $_nWave3 {( "G4" 10 )} +wvZoom -win $_nWave3 2945103.987525 2952852.406131 +wvZoom -win $_nWave3 2947707.456176 2950854.506195 +srcDeselectAll -win $_nTrace1 +debReload +srcDeselectAll -win $_nTrace1 +debReload +wvSetCursor -win $_nWave3 2948133.518332 -snap {("G5" 0)} +wvZoom -win $_nWave3 2947974.713347 2948584.756889 +wvSelectSignal -win $_nWave3 {( "G4" 8 )} +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoomOut -win $_nWave3 +wvZoom -win $_nWave3 2943252.225507 2947865.280920 +wvZoom -win $_nWave3 2944424.651283 2945943.411065 +wvSetCursor -win $_nWave3 2944911.589034 -snap {("G4" 4)} +wvSetCursor -win $_nWave3 2944946.170026 -snap {("G4" 4)} +wvSetCursor -win $_nWave3 2944973.274046 -snap {("G4" 4)} +wvSetCursor -win $_nWave3 2945006.920417 -snap {("G4" 4)} +wvSetCursor -win $_nWave3 2945037.762923 -snap {("G4" 4)} +wvSetCursor -win $_nWave3 2945074.213158 -snap {("G4" 4)} +wvSetCursor -win $_nWave3 2944945.235404 -snap {("G4" 8)} +wvSetCursor -win $_nWave3 2944977.012532 -snap {("G4" 4)} +wvSetCursor -win $_nWave3 2945006.920417 -snap {("G4" 4)} +wvSetCursor -win $_nWave3 2945038.697545 -snap {("G4" 4)} +wvSetCursor -win $_nWave3 2945069.540051 -snap {("G4" 4)} +srcShowCalling -win $_nTrace1 +srcSelect -win $_nTrace1 -range {154 154 4 5 1 1} +srcHBSelect "TB.U_digital_top.U_debug_top" -win $_nTrace1 +srcShowCalling -win $_nTrace1 +srcSelect -win $_nTrace1 -range {1244 1244 3 4 1 1} +srcHBSelect "TB.U_digital_top" -win $_nTrace1 +srcShowCalling -win $_nTrace1 +srcSelect -win $_nTrace1 -range {645 645 3 4 1 1} +srcHBSelect "TB" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -win $_nTrace1 -signal "aif.sclk" -line 658 -pos 1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave3 +wvSetPosition -win $_nWave3 {("G5" 0)} +wvSetPosition -win $_nWave3 {("G4" 10)} +wvSetPosition -win $_nWave3 {("G4" 9)} +wvSetPosition -win $_nWave3 {("G4" 8)} +wvSetPosition -win $_nWave3 {("G4" 7)} +wvSetPosition -win $_nWave3 {("G4" 6)} +wvSetPosition -win $_nWave3 {("G4" 5)} +wvSetPosition -win $_nWave3 {("G4" 4)} +wvSetPosition -win $_nWave3 {("G4" 3)} +wvMoveSelected -win $_nWave3 +wvSetPosition -win $_nWave3 {("G4" 3)} +wvSetPosition -win $_nWave3 {("G4" 4)} +wvSetPosition -win $_nWave3 {("G4" 4)} +wvSetPosition -win $_nWave3 {("G4" 4)} +wvSetPosition -win $_nWave3 {("G4" 4)} +wvSetCursor -win $_nWave3 2944623.725641 -snap {("G4" 5)} +wvSetCursor -win $_nWave3 2944656.437390 -snap {("G4" 5)} +wvSetCursor -win $_nWave3 2944690.083761 -snap {("G4" 5)} +wvSetCursor -win $_nWave3 2944718.122403 -snap {("G4" 5)} +wvSetCursor -win $_nWave3 2944687.279897 -snap {("G4" 5)} +wvSetCursor -win $_nWave3 2944719.057024 -snap {("G4" 5)} +wvSetCursor -win $_nWave3 2944688.214518 -snap {("G4" 5)} +wvSetCursor -win $_nWave3 2944718.122403 -snap {("G4" 5)} +wvSetCursor -win $_nWave3 2944814.388408 -snap {("G4" 4)} +wvSetCursor -win $_nWave3 2944915.327519 -snap {("G4" 4)} +wvSetCursor -win $_nWave3 2944815.323029 -snap {("G4" 4)} +wvSetCursor -win $_nWave3 2944847.100157 -snap {("G4" 5)} +wvSetCursor -win $_nWave3 2944880.746527 -snap {("G4" 5)} +wvSetCursor -win $_nWave3 2944913.458276 -snap {("G4" 5)} +wvSelectSignal -win $_nWave3 {( "G4" 1 )} +wvSelectSignal -win $_nWave3 {( "G4" 3 )} +wvSelectSignal -win $_nWave3 {( "G4" 8 )} +wvSetCursor -win $_nWave3 2945109.728771 -snap {("G4" 8)} +srcActiveTrace "TB.U_digital_top.U_spi_slave.U_spi_sys.rddata_reg\[31:0\]" -win \ + $_nTrace1 -TraceByDConWave -TraceTime 2945104000 -TraceValue \ + 00000000000000001000000000000000 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "dnxt" -line 93 -pos 1 -win $_nTrace1 +srcAction -pos 92 11 3 -win $_nTrace1 -name "dnxt" -ctrlKey off +srcShowCalling -win $_nTrace1 +srcSelect -win $_nTrace1 -range {84 84 8 9 1 1} +srcHBSelect "TB.U_digital_top.U_spi_bus_decoder" -win $_nTrace1 +srcShowCalling -win $_nTrace1 +srcSelect -win $_nTrace1 -range {464 464 4 5 1 1} +srcHBSelect "TB.U_digital_top" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -inst "U_spi_slave" -line 364 -pos 1 -win $_nTrace1 +srcAction -pos 363 2 7 -win $_nTrace1 -name "U_spi_slave" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -inst "U_spi_sys" -line 87 -pos 1 -win $_nTrace1 +srcAction -pos 86 2 6 -win $_nTrace1 -name "U_spi_sys" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -signal "rddata_reg" -line 260 -pos 1 -win $_nTrace1 +schCreateWindow -win $_nSchema1 -conn +schZoomOut -win $_nSchema11 -pos 7542 5021 +schZoomOut -win $_nSchema11 -pos 7543 5020 +schZoomOut -win $_nSchema11 -pos 7543 5009 +srcShowCalling -win $_nTrace1 +srcSelect -win $_nTrace1 -range {87 87 3 4 1 1} +srcHBSelect "TB.U_digital_top.U_spi_slave" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -inst "U_spi_sys" -line 87 -pos 1 -win $_nTrace1 +srcAction -pos 86 2 6 -win $_nTrace1 -name "U_spi_sys" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -signal "rddata_reg" -line 260 -pos 1 -win $_nTrace1 +srcCopySignalFullPath -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -inst "rddata_reg_dfflr" -line 260 -pos 1 -win $_nTrace1 +srcAction -pos 259 7 13 -win $_nTrace1 -name "rddata_reg_dfflr" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -signal "qout_r" -line 107 -pos 1 -win $_nTrace1 +srcCopySignalFullPath -win $_nTrace1 +wvResizeWindow -win $_nWave3 -10 20 1432 929 +wvResizeWindow -win $_nWave3 -10 89 2560 1260 diff --git a/tb/digital_top/verdiLog/verdi.cmd.bak b/tb/digital_top/verdiLog/verdi.cmd.bak new file mode 100644 index 0000000..dc2c3f1 --- /dev/null +++ b/tb/digital_top/verdiLog/verdi.cmd.bak @@ -0,0 +1,1139 @@ +sidCmdLineBehaviorAnalysisOpt -incr -clockSkew 0 -loopUnroll 0 -bboxEmptyModule 0 -cellModel 0 -bboxIgnoreProtected 0 +debImport "-sverilog" "-f" "files.f" "-top" "TB" +wvCreateWindow +wvSetPosition -win $_nWave2 {("G1" 0)} +wvOpenFile -win $_nWave2 \ + {/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/digital_top/verdplus_000.fsdb} +srcDeselectAll -win $_nTrace1 +srcSelect -signal "clk" -line 151 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +srcHBSelect "TB.U_digital_top" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top" -delim "." +srcHBSelect "TB.U_digital_top" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "sclk" -line 58 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +wvZoom -win $_nWave2 183894753.436807 259270219.235033 +wvZoom -win $_nWave2 196897439.111084 202111883.751671 +wvZoom -win $_nWave2 197903329.762288 198386619.753367 +wvZoom -win $_nWave2 197998916.163983 198078428.619278 +wvZoomOut -win $_nWave2 +srcHBSelect "TB.U_digital_top.U_debug_top" -win $_nTrace1 +srcHBSelect "TB.U_digital_top.U0_channel_top" -win $_nTrace1 +srcHBSelect "TB.U_digital_top.U0_channel_top.U_ITCM" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U0_channel_top.U_ITCM" -delim "." +srcHBSelect "TB.U_digital_top.U0_channel_top.U_ITCM" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -inst "U_tsmc_dpram" -line 70 -pos 1 -win $_nTrace1 +srcAction -pos 69 3 5 -win $_nTrace1 -name "U_tsmc_dpram" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -signal "U0_CEBB" -line 96 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 60081656.330637 274989119.359453 +wvZoom -win $_nWave2 66276328.213944 73709934.473921 +wvZoom -win $_nWave2 67917984.940090 68244338.385650 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "PortBWriteEnable" -line 97 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "PortBDataIn" -line 100 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 67851918.266964 68236306.183330 +wvSetCursor -win $_nWave2 68016241.970453 -snap {("G1" 3)} +srcDeselectAll -win $_nTrace1 +srcSelect -signal "PortClk" -line 89 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +wvZoom -win $_nWave2 68041470.090907 68058857.038787 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvSetCursor -win $_nWave2 68047110.247164 -snap {("G1" 6)} +wvSetCursor -win $_nWave2 68014849.941208 -snap {("G1" 6)} +srcDeselectAll -win $_nTrace1 +debReload +wvSelectSignal -win $_nWave2 {( "G1" 3 )} +wvSetCursor -win $_nWave2 68047295.296720 -snap {("G1" 6)} +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvSetCursor -win $_nWave2 68013400.386351 -snap {("G1" 6)} +wvSelectSignal -win $_nWave2 {( "G1" 4 )} +wvSelectSignal -win $_nWave2 {( "G1" 4 5 )} +wvSelectSignal -win $_nWave2 {( "G1" 3 4 5 )} +wvCut -win $_nWave2 +wvSetPosition -win $_nWave2 {("G1" 3)} +wvSelectGroup -win $_nWave2 {G2} +srcDeselectAll -win $_nTrace1 +srcSelect -signal "U0_CEBB" -line 96 -pos 1 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "U0_CEBA" -line 90 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "U0_CEBA" -line 90 -pos 1 -win $_nTrace1 +srcAction -pos 89 7 5 -win $_nTrace1 -name "U0_CEBA" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -signal "PortAChipEnable" -line 48 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "PortAChipEnable" -line 48 -pos 1 -win $_nTrace1 +srcAction -pos 47 11 11 -win $_nTrace1 -name "PortAChipEnable" -ctrlKey off +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "ifu_o_req" -line 342 -pos 1 -win $_nTrace1 +srcAction -pos 341 8 6 -win $_nTrace1 -name "ifu_o_req" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -signal "ifu_req_w" -line 112 -pos 1 -win $_nTrace1 +srcAction -pos 111 6 5 -win $_nTrace1 -name "ifu_req_w" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -signal "ifu_active" -line 65 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "ifu_active" -line 65 -pos 1 -win $_nTrace1 +srcAction -pos 64 6 6 -win $_nTrace1 -name "ifu_active" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -signal "dnxt" -line 263 -pos 1 -win $_nTrace1 +srcAction -pos 262 11 1 -win $_nTrace1 -name "dnxt" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -signal "clk" -line 37 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "start" -line 39 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +wvZoom -win $_nWave2 281730289.068736 361465276.541020 +wvZoom -win $_nWave2 302167904.482882 304254097.059762 +wvSetCursor -win $_nWave2 302816428.206256 -snap {("G2" 0)} +wvDisplayGridCount -win $_nWave2 -off +wvGetSignalClose -win $_nWave2 +wvReloadFile -win $_nWave2 +wvSetCursor -win $_nWave2 302703561.024713 -snap {("G2" 0)} +wvSetCursor -win $_nWave2 302673031.377246 -snap {("G2" 0)} +wvSetCursor -win $_nWave2 302600870.392325 -snap {("G1" 9)} +wvZoom -win $_nWave2 302576816.730685 302747967.784664 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "start" -line 39 -pos 1 -win $_nTrace1 +srcAction -pos 38 4 1 -win $_nTrace1 -name "start" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -signal "sync_in" -line 6 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "sync_int" -line 7 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "sync_int" -line 15 -pos 2 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "sync_r\[1\]" -line 15 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "sync_r\[1:0\]" -line 14 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "sync_r\[1\]" -line 15 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "sync_r\[1\]" -line 16 -pos 1 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +wvSetCursor -win $_nWave2 302310830.536111 -snap {("G1" 11)} +wvDisplayGridCount -win $_nWave2 -off +wvGetSignalClose -win $_nWave2 +wvReloadFile -win $_nWave2 +wvSetCursor -win $_nWave2 303060100.250027 -snap {("G1" 12)} +srcBackwardHistory -win $_nTrace1 +srcHBSelect "TB.U_digital_top.U_sync_buf" -win $_nTrace1 +srcHBSelect "TB.U_digital_top.U0_channel_top.U_qbmcu.U_qbmcu_fsm" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "state_c" -line 59 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 792751.463415 11362770.975610 +wvZoom -win $_nWave2 1880221.320102 2405206.768157 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "rst_n" -line 38 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 1691128.290323 2488268.057127 +wvSelectSignal -win $_nWave2 {( "G1" 8 )} +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +srcHBSelect \ + "TB.U_digital_top.U0_channel_top.U_ITCM.U_tsmc_dpram.dpram_32X4096_generation" \ + -win $_nTrace1 +srcHBSelect "TB.inst_clk_gen" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.inst_clk_gen" -delim "." +srcHBSelect "TB.inst_clk_gen" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "clk" -line 3 -pos 1 -win $_nTrace1 +wvSelectSignal -win $_nWave2 {( "G1" 8 )} +wvSelectSignal -win $_nWave2 {( "G1" 13 )} +wvSelectAll -win $_nWave2 +wvCut -win $_nWave2 +wvSetPosition -win $_nWave2 {("G1" 0)} +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "clk_div16_0" -line 4 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +wvZoom -win $_nWave2 622157.866774 3744259.161857 +wvZoom -win $_nWave2 1875151.956375 2183900.776243 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "clk_l" -line 22 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +wvZoom -win $_nWave2 1824835.596988 2381268.059935 +wvZoom -win $_nWave2 1999044.607560 2113538.914792 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "rstn" -line 2 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +srcHBSelect "TB" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB" -delim "." +srcHBSelect "TB" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "rstn" -line 152 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +srcHBSelect "TB.inst_clk_gen" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.inst_clk_gen" -delim "." +srcHBSelect "TB.inst_clk_gen" -win $_nTrace1 +wvSetCursor -win $_nWave2 2041542.051087 -snap {("G1" 4)} +wvSetCursor -win $_nWave2 2031184.251231 -snap {("G1" 3)} +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvSetWindowTimeUnit -win $_nWave2 1.000000 ns +wvSetCursor -win $_nWave2 1999.222315 -snap {("G1" 4)} +wvSetCursor -win $_nWave2 2030.904997 -snap {("G1" 3)} +wvSetCursor -win $_nWave2 1999.222315 -snap {("G1" 4)} +srcDeselectAll -win $_nTrace1 +debReload +srcHBSelect "TB.U_digital_top" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top" -delim "." +srcHBSelect "TB.U_digital_top" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "por_rstn" -line 40 -pos 1 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "async_rstn" -line 43 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvSelectSignal -win $_nWave2 {( "G1" 3 )} +wvSelectAll -win $_nWave2 +wvCut -win $_nWave2 +wvSetPosition -win $_nWave2 {("G1" 0)} +srcDeselectAll -win $_nTrace1 +srcSelect -signal "ch0_xy_dsp_dout0" -line 239 -pos 1 -win $_nTrace1 +srcSelect -win $_nTrace1 -range {239 254 12 12 10 12} +srcDeselectAll -win $_nTrace1 +srcSelect -signal "ch0_xy_dsp_dout15" -line 254 -pos 1 -win $_nTrace1 +srcHBSelect "TB" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB" -delim "." +srcHBSelect "TB" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "cs_wave" -line 836 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "i_cs_f" -line 836 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "ch0_xy_dsp_dout0" -line 744 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "ch0_xy_dsp_dout0" -line 744 -pos 1 -win $_nTrace1 +srcAction -pos 743 12 10 -win $_nTrace1 -name "ch0_xy_dsp_dout0" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -signal "ch0_xy_dsp_dout0" -line 744 -pos 1 -win $_nTrace1 +srcAction -pos 743 12 10 -win $_nTrace1 -name "ch0_xy_dsp_dout0" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -signal "ch0_xy_dsp_dout0" -line 744 -pos 1 -win $_nTrace1 +srcAction -pos 743 12 10 -win $_nTrace1 -name "ch0_xy_dsp_dout0" -ctrlKey off +srcHBSelect "TB" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB" -delim "." +srcHBSelect "TB" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +debReload +wvSelectSignal -win $_nWave2 {( "G1" 1 )} +wvSelectSignal -win $_nWave2 {( "G1" 1 2 )} +wvCut -win $_nWave2 +wvSetPosition -win $_nWave2 {("G1" 1)} +wvZoom -win $_nWave2 594458.977237 792611.969650 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "ch0_xy_dsp_dout13" -line 633 -pos 2 -win $_nTrace1 +srcSearchString "ch0_xy_dsp_dout13" -win $_nTrace1 -next -case +srcDeselectAll -win $_nTrace1 +srcSelect -signal "i_cs_d" -line 757 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "ch0_xy_dsp_dout9" -line 753 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "i_cs_a" -line 754 -pos 1 -win $_nTrace1 +srcSearchString "i_cs_a" -win $_nTrace1 -next -case +srcSearchString "i_cs_a" -win $_nTrace1 -next -case +srcDeselectAll -win $_nTrace1 +srcSelect -signal "i_cs_8" -line 752 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "i_cs_8" -line 752 -pos 1 -win $_nTrace1 +srcAction -pos 751 8 3 -win $_nTrace1 -name "i_cs_8" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -signal "i_cs_8" -line 752 -pos 1 -win $_nTrace1 +srcAction -pos 751 8 3 -win $_nTrace1 -name "i_cs_8" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -signal "i_cs_8" -line 752 -pos 1 -win $_nTrace1 +srcAction -pos 751 8 3 -win $_nTrace1 -name "i_cs_8" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -signal "i_cs_8" -line 752 -pos 1 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +debReload +wvSelectSignal -win $_nWave2 {( "G1" 3 )} +srcDeselectAll -win $_nTrace1 +srcSelect -signal "cs_wave" -line 743 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +wvSelectSignal -win $_nWave2 {( "G1" 4 )} +wvSelectSignal -win $_nWave2 {( "G1" 5 )} +wvBusWaveform -win $_nWave2 -analog +wvSetPosition -win $_nWave2 {("G1" 5)} +wvZoomIn -win $_nWave2 +wvZoom -win $_nWave2 661220.279226 667722.860795 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 1868528.810754 2059533.978075 +wvZoom -win $_nWave2 1994143.295515 2004646.462144 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvSelectSignal -win $_nWave2 {( "G1" 3 )} +wvSetCursor -win $_nWave2 161345.979849 -snap {("G1" 3)} +srcActiveTrace "TB.ch0_xy_dsp_dout9\[15:0\]" -win $_nTrace1 -TraceByDConWave \ + -TraceTime 22863000 -TraceValue 1000000000000000 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "dout9_r" -line 361 -pos 1 -win $_nTrace1 +srcAction -pos 360 6 2 -win $_nTrace1 -name "dout9_r" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -signal "rstn" -line 237 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +wvZoom -win $_nWave2 0.000000 39150.127463 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 298895.163818 370563.335068 +wvZoom -win $_nWave2 308397.950161 312307.123139 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomIn -win $_nWave2 +verdiDockWidgetMaximize -dock windowDock_nWave_2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 357671.732033 362664.378673 +wvZoomOut -win $_nWave2 +wvSetCursor -win $_nWave2 359213.806704 -snap {("G1" 5)} +wvZoom -win $_nWave2 359036.683985 359652.185434 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 366244.601723 371380.422234 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 375198.694113 378223.248276 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 375776.108999 376540.630450 +wvZoomOut -win $_nWave2 +wvSelectSignal -win $_nWave2 {( "G1" 5 )} +wvAddSignal -win $_nWave2 "/TB/cs_wave\[15:0\]" +wvSetPosition -win $_nWave2 {("G1" 6)} +wvSetPosition -win $_nWave2 {("G1" 7)} +wvSetCursor -win $_nWave2 375865.105398 -snap {("G1" 7)} +wvSetCursor -win $_nWave2 375901.721060 -snap {("G1" 7)} +wvSelectSignal -win $_nWave2 {( "G1" 1 )} +wvSelectSignal -win $_nWave2 {( "G1" 1 2 3 4 )} +wvCut -win $_nWave2 +wvSetPosition -win $_nWave2 {("G1" 3)} +verdiDockWidgetRestore -dock windowDock_nWave_2 +srcHBSelect "TB" -win $_nTrace1 +srcHBSelect "TB.U_digital_top" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top" -delim "." +srcHBSelect "TB.U_digital_top" -win $_nTrace1 +verdiDockWidgetMaximize -dock windowDock_nWave_2 +verdiDockWidgetRestore -dock windowDock_nWave_2 +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U0_channel_top.U_awg_top" -delim "." +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top" -win $_nTrace1 +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.U_awg_ctrl" -win $_nTrace1 +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.U_awg_ctrl" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U0_channel_top.U_awg_top.U_awg_ctrl" \ + -delim "." +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.U_awg_ctrl" -win $_nTrace1 +srcSelect -signal "enve_vld_o" -line 100 -pos 1 -win $_nTrace1 +srcSelect -signal "enve_qdata_o" -line 99 -pos 1 -win $_nTrace1 +srcSelect -signal "enve_idata_o" -line 98 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +wvZoomOut -win $_nWave2 +wvSelectSignal -win $_nWave2 {( "G1" 5 )} +wvSelectSignal -win $_nWave2 {( "G1" 6 )} +wvSetRadix -win $_nWave2 -2Com +wvBusWaveform -win $_nWave2 -analog +wvSetPosition -win $_nWave2 {("G1" 6)} +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 0 +verdiDockWidgetMaximize -dock windowDock_nWave_2 +wvZoomIn -win $_nWave2 +wvSetCursor -win $_nWave2 367506.224517 -snap {("G1" 6)} +wvSetCursor -win $_nWave2 365401.502046 -snap {("G1" 6)} +wvSetCursor -win $_nWave2 367506.224517 -snap {("G1" 6)} +wvSetCursor -win $_nWave2 373842.090098 -snap {("G1" 6)} +wvSetCursor -win $_nWave2 376001.057993 -snap {("G1" 6)} +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomOut -win $_nWave2 +wvSetCursor -win $_nWave2 373877.349624 -snap {("G1" 6)} +wvSetCursor -win $_nWave2 374452.351124 -snap {("G1" 6)} +wvSetCursor -win $_nWave2 375314.853373 -snap {("G1" 6)} +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 363725.318429 369193.257219 +wvZoomOut -win $_nWave2 +wvSetCursor -win $_nWave2 365554.834978 -snap {("G1" 6)} +wvSelectSignal -win $_nWave2 {( "G1" 5 )} +wvSetRadix -win $_nWave2 -2Com +wvBusWaveform -win $_nWave2 -analog +wvSetPosition -win $_nWave2 {("G1" 6)} +wvSetCursor -win $_nWave2 361718.791002 -snap {("G1" 5)} +srcActiveTrace \ + "TB.U_digital_top.U0_channel_top.U_awg_top.U_awg_ctrl.enve_qdata_o\[15:0\]" \ + -win $_nTrace1 -TraceByDConWave -TraceTime 358480000 -TraceValue \ + 0110001001000111 +wvSetCursor -win $_nWave2 359488.827971 -snap {("G1" 5)} +srcActiveTrace \ + "TB.U_digital_top.U0_channel_top.U_awg_top.U_awg_ctrl.enve_qdata_o\[15:0\]" \ + -win $_nTrace1 -TraceByDConWave -TraceTime 359056000 -TraceValue \ + 0000000000000000 +verdiDockWidgetRestore -dock windowDock_nWave_2 +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.U_awg_ctrl" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U0_channel_top.U_awg_top.U_awg_ctrl" \ + -delim "." +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.U_awg_ctrl" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "enve_idata_o" -line 98 -pos 1 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "enve_idata_o" -line 98 -pos 1 -win $_nTrace1 +srcAction -pos 97 11 7 -win $_nTrace1 -name "enve_idata_o" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -signal "dnxt" -line 277 -pos 1 -win $_nTrace1 +srcAction -pos 276 12 3 -win $_nTrace1 -name "dnxt" -ctrlKey off +srcDeselectAll -win $_nTrace1 +srcSelect -signal "enve_idata_o" -line 98 -pos 1 -win $_nTrace1 +srcSearchString "enve_idata_o" -win $_nTrace1 -next -case +srcDeselectAll -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +debReload +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 379796.582900 386159.275310 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 405573.246542 411803.324077 +wvZoomOut -win $_nWave2 +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.U_awg_ctrl.cnt_c_dffr" \ + -win $_nTrace1 +srcHBSelect "TB" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB" -delim "." +srcHBSelect "TB" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "cs_wave" -line 812 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 0 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 409605.529541 412279.904288 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "clk_div16_b" -line 813 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "intp_mode" -line 765 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U0_channel_top.U_awg_top" -delim "." +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +debReload +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvSelectSignal -win $_nWave2 {( "G1" 7 )} +wvSetRadix -win $_nWave2 -2Com +wvSetRadix -win $_nWave2 -Unsigned +wvBusWaveform -win $_nWave2 -analog +wvSetPosition -win $_nWave2 {("G1" 9)} +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 409670.165206 410275.012709 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 408985.520747 413071.124817 +wvZoomOut -win $_nWave2 +wvScrollUp -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 402251.974173 404339.165254 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvZoom -win $_nWave2 402358.879082 403713.933513 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvSelectSignal -win $_nWave2 {( "G1" 6 )} +wvScrollUp -win $_nWave2 1 +wvSelectSignal -win $_nWave2 {( "G1" 5 )} +wvSelectSignal -win $_nWave2 {( "G1" 6 )} +wvScrollDown -win $_nWave2 1 +wvSelectSignal -win $_nWave2 {( "G1" 6 )} +wvSelectSignal -win $_nWave2 {( "G1" 7 )} +wvSelectSignal -win $_nWave2 {( "G1" 6 )} +wvAddSignal -win $_nWave2 \ + "/TB/U_digital_top/U0_channel_top/U_awg_top/U_awg_ctrl/enve_idata_o\[15:0\]" +wvSetPosition -win $_nWave2 {("G1" 9)} +wvSetPosition -win $_nWave2 {("G1" 10)} +wvSetCursor -win $_nWave2 401279.342370 -snap {("G1" 10)} +wvZoom -win $_nWave2 400534.212660 401663.925445 +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.U_awg_ctrl" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U0_channel_top.U_awg_top.U_awg_ctrl" \ + -delim "." +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.U_awg_ctrl" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "enve_vld_o" -line 100 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +wvSetCursor -win $_nWave2 400658.956999 -snap {("G1" 11)} +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvSetCursor -win $_nWave2 399173.297014 -snap {("G1" 11)} +wvSetCursor -win $_nWave2 400680.248703 -snap {("G1" 11)} +wvSetCursor -win $_nWave2 401313.489040 -snap {("G1" 11)} +srcHBSelect "TB.U_digital_top" -win $_nTrace1 +srcHBSelect "TB.U_digital_top.U0_channel_top" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U0_channel_top" -delim "." +srcHBSelect "TB.U_digital_top.U0_channel_top" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "xy_dsp_dout_vld" -line 588 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +wvSetCursor -win $_nWave2 403341.461260 -snap {("G1" 7)} +wvSetCursor -win $_nWave2 402668.142420 -snap {("G1" 7)} +wvSetCursor -win $_nWave2 403329.437709 -snap {("G1" 7)} +wvSetCursor -win $_nWave2 402672.150271 -snap {("G1" 7)} +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.U_awg_ctrl" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U0_channel_top.U_awg_top.U_awg_ctrl" \ + -delim "." +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.U_awg_ctrl" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "enve_rden_o" -line 94 -pos 1 -win $_nTrace1 +srcSelect -signal "enve_rdaddr_o" -line 95 -pos 1 -win $_nTrace1 +srcSelect -signal "enve_rddata_i" -line 96 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +wvSelectSignal -win $_nWave2 {( "G1" 15 )} +wvSelectSignal -win $_nWave2 {( "G1" 14 )} +wvCut -win $_nWave2 +wvSetPosition -win $_nWave2 {("G2" 0)} +wvSetPosition -win $_nWave2 {("G1" 14)} +wvZoom -win $_nWave2 400535.966094 401309.481190 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvSelectSignal -win $_nWave2 {( "G1" 6 )} +wvSetPosition -win $_nWave2 {("G1" 6)} +wvSetPosition -win $_nWave2 {("G1" 7)} +wvSetPosition -win $_nWave2 {("G1" 10)} +wvSetPosition -win $_nWave2 {("G2" 0)} +wvMoveSelected -win $_nWave2 +wvSetPosition -win $_nWave2 {("G2" 1)} +wvSetPosition -win $_nWave2 {("G2" 1)} +wvZoom -win $_nWave2 400526.189961 401442.745321 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "enve_rden_o" -line 94 -pos 1 -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +srcSelect -signal "enve_rdaddr_o" -line 95 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +wvSetCursor -win $_nWave2 400595.084034 -snap {("G1" 12)} +wvSetPosition -win $_nWave2 {("G2" 1)} +wvSetPosition -win $_nWave2 {("G1" 12)} +wvMoveSelected -win $_nWave2 +wvSetPosition -win $_nWave2 {("G1" 12)} +wvSetPosition -win $_nWave2 {("G1" 13)} +srcDeselectAll -win $_nTrace1 +srcSelect -signal "enve_start_addr_i" -line 89 -pos 1 -win $_nTrace1 +srcSelect -signal "enve_index_vld_i" -line 88 -pos 1 -win $_nTrace1 +srcSelect -signal "enve_len_i" -line 90 -pos 1 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.enve_dpram" -win $_nTrace1 +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.enve_dpram" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U0_channel_top.U_awg_top.enve_dpram" \ + -delim "." +srcHBSelect "TB.U_digital_top.U0_channel_top.U_awg_top.enve_dpram" -win $_nTrace1 +srcSelect -signal "PortBAddr" -line 78 -pos 2 -win $_nTrace1 +srcSelect -signal "PortADataOut" -line 77 -pos 2 -win $_nTrace1 +srcSelect -toggle -signal "PortADataOut" -line 77 -pos 2 -win $_nTrace1 +srcSelect -signal "PortBDataIn" -line 79 -pos 2 -win $_nTrace1 +srcSelect -signal "PortBWriteEnable" -line 80 -pos 2 -win $_nTrace1 +srcSelect -signal "PortBChipEnable" -line 81 -pos 2 -win $_nTrace1 +srcAddSelectedToWave -clipboard -win $_nTrace1 +wvDrop -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 230580.128255 326308.340346 +wvScrollDown -win $_nWave2 1 +wvZoom -win $_nWave2 241490.172826 243867.458802 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +srcDeselectAll -win $_nTrace1 +debReload +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomOut -win $_nWave2 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollDown -win $_nWave2 0 +wvZoomIn -win $_nWave2 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvSelectSignal -win $_nWave2 {( "G1" 6 )} +wvSetCursor -win $_nWave2 9736100.393815 -snap {("G1" 6)} +wvZoom -win $_nWave2 9736007.621680 9737449.806698 +wvZoomOut -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomOut -win $_nWave2 +wvSetCursor -win $_nWave2 9728286.655546 -snap {("G1" 6)} +wvSelectSignal -win $_nWave2 {( "G1" 5 )} +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 0 +wvSelectSignal -win $_nWave2 {( "G1" 21 )} +wvCut -win $_nWave2 +wvSetPosition -win $_nWave2 {("G1" 20)} +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 0 +wvZoom -win $_nWave2 9725298.678426 9726485.683035 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 9726919.689819 9732983.677889 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 9727687.436424 9733151.748512 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 9717654.184007 9724012.656254 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 9710067.722994 9714421.373172 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 9774396.524365 9799356.164939 +wvZoomOut -win $_nWave2 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 1 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 0 +wvScrollUp -win $_nWave2 1 +wvScrollUp -win $_nWave2 1 +wvScrollDown -win $_nWave2 0 +wvScrollDown -win $_nWave2 0 +wvZoomIn -win $_nWave2 +wvZoom -win $_nWave2 9786483.410177 9787988.736615 +wvZoom -win $_nWave2 9786971.389611 9787466.712102 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +srcDeselectAll -win $_nTrace1 +debReload +srcHBSelect "TB.U_digital_top.U0_channel_top" -win $_nTrace1 +srcSetScope -win $_nTrace1 "TB.U_digital_top.U0_channel_top" -delim "." +srcHBSelect "TB.U_digital_top.U0_channel_top" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +debReload +srcDeselectAll -win $_nTrace1 +debReload +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 9751286.973534 9756572.756427 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 9760263.428340 9764342.036869 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 9785482.975135 9792138.974863 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 9794354.197833 9798037.873070 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 9811002.612991 9816177.727471 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 9827671.989499 9834611.921289 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 9845655.799440 9849447.371930 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 9854203.231260 9857202.861115 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoom -win $_nWave2 9862572.265066 9865200.765550 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoom -win $_nWave2 9856025.492128 9856790.146814 +wvSetCursor -win $_nWave2 9856274.725473 -snap {("G1" 1)} +wvSetCursor -win $_nWave2 9856285.237355 -snap {("G1" 1)} +wvSetCursor -win $_nWave2 9856295.749238 -snap {("G1" 1)} +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvSelectSignal -win $_nWave2 {( "G1" 1 )} +wvChangeDisplayAttr -win $_nWave2 -c ID_YELLOW6 -lw 1 -ls solid +wvChangeDisplayAttr -win $_nWave2 -c ID_ORANGE5 -lw 1 -ls solid +wvChangeDisplayAttr -win $_nWave2 -c ID_RED5 -lw 1 -ls solid +wvChangeDisplayAttr -win $_nWave2 -c ID_RED8 -lw 1 -ls solid +wvChangeDisplayAttr -win $_nWave2 -c ID_GREEN4 -lw 1 -ls solid +wvChangeDisplayAttr -win $_nWave2 -c ID_YELLOW4 -lw 1 -ls solid +wvChangeDisplayAttr -win $_nWave2 -c ID_ORANGE5 -lw 1 -ls solid +wvChangeDisplayAttr -win $_nWave2 -c ID_RED3 -lw 1 -ls solid +wvSetCursor -win $_nWave2 9841596.237782 -snap {("G1" 3)} +wvSetCursor -win $_nWave2 9839556.254370 -snap {("G1" 5)} +wvSelectSignal -win $_nWave2 {( "G1" 1 )} +wvSetCursor -win $_nWave2 9840185.610955 -snap {("G1" 1)} +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomIn -win $_nWave2 +wvSetCursor -win $_nWave2 9843788.134853 -snap {("G1" 5)} +wvSelectSignal -win $_nWave2 {( "G1" 3 )} +wvSetCursor -win $_nWave2 9839209.023151 -snap {("G1" 5)} +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomOut -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomIn -win $_nWave2 +wvZoomOut -win $_nWave2 +srcHBSelect "TB.U_digital_top.U0_channel_top.U_DTCM" -win $_nTrace1 +srcDeselectAll -win $_nTrace1 +debReload diff --git a/tb/digital_top/verdiLog/verdi_perf_err.log b/tb/digital_top/verdiLog/verdi_perf_err.log new file mode 100644 index 0000000..e69de29 diff --git a/tb/digital_top/verdplus.log b/tb/digital_top/verdplus.log new file mode 100644 index 0000000..258a6e6 --- /dev/null +++ b/tb/digital_top/verdplus.log @@ -0,0 +1,2 @@ +File Name Time +./verdplus_000.fsdb 0 to 3,202,992,000 diff --git a/tb/digital_top/verdplus.vf b/tb/digital_top/verdplus.vf new file mode 100644 index 0000000..1ef6a51 --- /dev/null +++ b/tb/digital_top/verdplus.vf @@ -0,0 +1,7 @@ +@FSDB rc file Version 1.0 +[VRTL_FILE_HEADER] +# !! DON'T EDIT [VRTL_FILE_HEADER] SESSION !! +Version = 1 +[VRTL_FILE_SOURCE] +FileType = switch +File1 = ./verdplus_000.fsdb diff --git a/tb/digital_top/verdplus_000.fsdb b/tb/digital_top/verdplus_000.fsdb new file mode 100644 index 0000000..b5faa45 Binary files /dev/null and b/tb/digital_top/verdplus_000.fsdb differ diff --git a/tb/digital_top/verdplus_001.fsdb b/tb/digital_top/verdplus_001.fsdb new file mode 100644 index 0000000..d76bb51 Binary files /dev/null and b/tb/digital_top/verdplus_001.fsdb differ diff --git a/tb/env.sv b/tb/env.sv new file mode 100644 index 0000000..4a90f06 --- /dev/null +++ b/tb/env.sv @@ -0,0 +1,177 @@ +class env; + + static int pktnum; + + int s_error =0; + int p_error =0; + int d_error =0; + int m_error =0; + int a_error =0; + int inst_error =0; + int data_error =0; + int envID_error =0; + int envData_error =0; + int dbg_error =0; + + integer fid; + + //Interface: + virtual spi_if wif; + virtual pllreg_if pif; + virtual dacreg_if dif; + virtual sysreg_if vif; + virtual awgreg_if aif; + virtual mcureg_if mif; + virtual sram_if#(25,32) xif; + + //Component: + spi_driver w_drv; spi_monitor w_mon; + pllreg_driver p_drv; pllreg_monitor p_mon; pll_refmodel p_mdl ; pllreg_scoreboard p_scb ; + dacreg_monitor d_mon; dac_refmodel d_mdl ; dacreg_scoreboard d_scb ; + sysreg_monitor s_mon; sys_refmodel s_mdl ; sysreg_scoreboard s_scb ; + mcureg_monitor m_mon; mcu_refmodel m_mdl ; mcureg_scoreboard m_scb ; + awgreg_monitor a_mon; awg_refmodel a_mdl ; awgreg_scoreboard a_scb ; + ram_refmodel inst_mdl ; ramreg_scoreboard inst_scb ; + ram_refmodel data_mdl ; ramreg_scoreboard data_scb ; + ram_refmodel envID_mdl ; ramreg_scoreboard envID_scb ; + ram_refmodel envData_mdl; ramreg_scoreboard envData_scb; + ram_refmodel dbg_mdl ; ramreg_scoreboard dbg_scb ; + + function new(); + endfunction; + + extern function build(); + + extern task run(); + +endclass: env + +function env::build(); + + fid = $fopen("./reports.txt"); + + w_drv = new(); + if(!w_drv.randomize() with { error_time == 0; }) + $fatal(0,"Randomize Failed"); + + w_drv.pktnum = pktnum; w_drv.vif=wif; + w_drv.autarchy = 1'b1 ; + w_drv.half_sclk = 16 ; + w_mon = new(); w_mon.wif=wif; w_mon.xif=xif; + w_mon.fid=fid; + + p_drv = new(); p_drv.pif=pif; p_drv.wif=wif; + p_mon = new(); p_mon.pif=pif; p_mon.xif=xif; p_mon.wif=wif; + p_mdl = new(); p_mdl.pif=pif; p_mdl.xif=xif; p_mdl.wif=wif; + p_scb = new(); p_scb.fid=fid; + + d_mon = new(); d_mon.dif=dif; d_mon.xif=xif; d_mon.wif=wif; + d_mdl = new(); d_mdl.dif=dif; d_mdl.xif=xif; d_mdl.wif=wif; + d_scb = new(); d_scb.fid=fid; + + s_mon = new(); s_mon.vif=vif; s_mon.xif=xif; + s_mdl = new(); s_mdl.vif=vif; s_mdl.xif=xif; s_mdl.wif=wif; + s_scb = new(); s_scb.fid=fid; + + m_mon = new(); m_mon.mif=mif; m_mon.xif=xif; + m_mdl = new(); m_mdl.mif=mif; m_mdl.xif=xif; m_mdl.wif=wif; + m_scb = new(); m_scb.fid=fid; + + a_mon = new(); a_mon.aif=aif; a_mon.xif=xif; + a_mdl = new(); a_mdl.aif=aif; a_mdl.xif=xif; a_mdl.wif=wif; + a_scb = new(); a_scb.fid=fid; + + //sel 1 for 8192, 2 for 64, 3 for 1024 + + inst_mdl = new(); data_mdl = new(); envID_mdl = new(); + inst_mdl.xif=xif; data_mdl.xif=xif; envID_mdl.xif=xif; + inst_mdl.wif=wif; data_mdl.wif=wif; envID_mdl.wif=wif; + inst_mdl.base_addr = 5'h1; data_mdl.base_addr = 5'h2; envID_mdl.base_addr = 5'h4; + inst_mdl.sel=1; data_mdl.sel=1; envID_mdl.sel=2; + inst_scb = new(); data_scb = new(); envID_scb = new(); + inst_scb.fid=fid; data_scb.fid=fid; envID_scb.fid=fid; + + envData_mdl = new(); dbg_mdl = new(); + envData_mdl.xif=xif; dbg_mdl.xif=xif; + envData_mdl.wif=wif; dbg_mdl.wif=wif; + envData_mdl.base_addr = 5'h5; dbg_mdl.base_addr = 5'h19; + envData_mdl.sel=1; dbg_mdl.sel=3; + envData_scb = new(); dbg_scb = new(); + envData_scb.fid=fid; dbg_scb.fid=fid; +endfunction + + +task env::run(); + + fork + + w_drv.do_drive(); w_mon.do_mon(); + p_drv.do_drive(); p_mon.do_mon(); p_mdl.do_imitate(); + d_mon.do_mon(); d_mdl.do_imitate(); + s_mon.do_mon(); s_mdl.do_imitate(); + m_mon.do_mon(); m_mdl.do_imitate(); + a_mon.do_mon(); a_mdl.do_imitate(); + inst_mdl.do_imitate(); + data_mdl.do_imitate(); + envID_mdl.do_imitate(); + envData_mdl.do_imitate(); + dbg_mdl.do_imitate(); +while(1) begin + repeat(2) @(posedge wif.csn); + @(posedge wif.clk); + p_mdl.dout.pop_back() ; + d_mdl.dout.pop_back() ; + s_mdl.dout.pop_back() ; + m_mdl.dout.pop_back() ; + a_mdl.dout.pop_back() ; + inst_mdl.dout.pop_back() ; + data_mdl.dout.pop_back() ; + envID_mdl.dout.pop_back() ; + envData_mdl.dout.pop_back(); + dbg_mdl.dout.pop_back() ; + + case(xif.addr[24:20]) + 5'b00000: if(s_scb.compare(s_mdl.dout, w_mon.act_trans.data, s_mdl.sysout, s_mon.act_trans)) s_error++ ; + 5'b00001: if(inst_scb.compare(inst_mdl.dout, w_mon.act_trans.data )) inst_error++ ; + 5'b00010: if(data_scb.compare(data_mdl.dout, w_mon.act_trans.data )) data_error++ ; + 5'b00011: if(a_scb.compare(a_mdl.dout, w_mon.act_trans.data, a_mdl.awgout, a_mon.act_trans)) a_error++ ; + 5'b00100: if(envID_scb.compare(envID_mdl.dout, w_mon.act_trans.data )) envID_error++ ; + 5'b00101: if(envData_scb.compare(envData_mdl.dout, w_mon.act_trans.data )) envData_error++; + 5'b00110: if(d_scb.compare(d_mdl.dout, w_mon.act_trans.data, d_mdl.dacout, d_mon.act_trans)) d_error++ ; + 5'b00111: if(m_scb.compare(m_mdl.dout, w_mon.act_trans.data, m_mdl.mcuout, m_mon.act_trans)) m_error++ ; + 5'b11001: if(dbg_scb.compare(dbg_mdl.dout, w_mon.act_trans.data )) dbg_error++ ; + 5'b11111: if(p_scb.compare(p_mdl.dout, w_mon.act_trans.data, p_mdl.pllout, p_mon.act_trans)) p_error++ ; + endcase + p_mdl.dout.delete() ; p_mdl.pllout.delete() ; p_mon.act_trans.delete(); + d_mdl.dout.delete() ; d_mdl.dacout.delete() ; d_mon.act_trans.delete(); + s_mdl.dout.delete() ; s_mdl.sysout.delete() ; s_mon.act_trans.delete(); + m_mdl.dout.delete() ; m_mdl.mcuout.delete() ; m_mon.act_trans.delete(); + a_mdl.dout.delete() ; a_mdl.awgout.delete() ; a_mon.act_trans.delete(); + inst_mdl.dout.delete() ; inst_mdl.ramout.delete() ; + data_mdl.dout.delete() ; data_mdl.ramout.delete() ; + envID_mdl.dout.delete() ; envID_mdl.ramout.delete() ; + envData_mdl.dout.delete(); envData_mdl.ramout.delete(); + dbg_mdl.dout.delete() ; dbg_mdl.ramout.delete() ; + end + + + join + + $display("SCOREBOARD:"); + $display("INTPLL_REGFILE:"); + $display("\tError:\t\t%0d",p_error); + $display("SYSTEM_REGFILE:"); + $display("\tError:\t\t%0d",s_error); + $display("\tError_sysrst:\t%0d",s_mdl.rst_error[0]); + $display("\tError_ch0rst:\t%0d",s_mdl.rst_error[1]); + $display("\tError_ch1rst:\t%0d",s_mdl.rst_error[2]); + $display("\tError_ch2rst:\t%0d",s_mdl.rst_error[3]); + $display("\tError_ch3rst:\t%0d",s_mdl.rst_error[3]); + $display("MCU_REGFILE:"); + $display("\tError:\t\t%0d",m_error); + $display("AWG_REGFILE:"); + $display("\tError:\t\t%0d",a_error); + + +endtask + diff --git a/tb/mcureg_tb/mcu_refmodel.sv b/tb/mcureg_tb/mcu_refmodel.sv new file mode 100644 index 0000000..c91dfce --- /dev/null +++ b/tb/mcureg_tb/mcu_refmodel.sv @@ -0,0 +1,284 @@ +//For mcu_regfile, the ROreg: mcu_para/rtimr/icntr/fsir are updated by the inputs +//at this clk_posedge due to dff(inputs->regs) +class mcu_refmodel; + + virtual mcureg_if mif; + virtual spi_if wif; + virtual sram_if#(25,32) xif; + + + //poor-quality register model + bit[31:0] rm[42]; + + //members to be sent to scoreboard + int rst_error[5]; + bit[31:0] dout[$]; + mcureg_trans mcuout[$]; + + + + function new(); + endfunction + extern task do_imitate(); + extern task RWreg_write (bit[24:0] addr,bit[32:0] din ); + extern task ROreg_update (bit[24:0] addr ); + extern task reg_read (bit[24:0] addr ); + extern task output_trace (bit[24:0] addr ); + +endclass : mcu_refmodel + +task mcu_refmodel::do_imitate(); + + int i=0,j=0; + + rm[ 0] = 32'h0; //MCUPARAR0 + rm[ 1] = 32'h0; //MCUPARAR1 + rm[ 2] = 32'h0; //MCUPARAR2 + rm[ 3] = 32'h0; //MCUPARAR3 + rm[ 4] = 32'h0; //MCURESR0 + rm[ 5] = 32'h0; //MCURESR1 + rm[ 6] = 32'h0; //MCURESR2 + rm[ 7] = 32'h0; //MCURESR3 + rm[16] = 32'h0; //CWFR0 + rm[17] = 32'h0; //CWFR1 + rm[18] = 32'h0; //CWFR2 + rm[19] = 32'h0; //CWFR3 + rm[20] = 32'h0; //CWPRR + rm[21] = 32'h0; //GAPR0 + rm[22] = 32'h0; //GAPR1 + rm[23] = 32'h0; //GAPR2 + rm[24] = 32'h0; //GAPR3 + rm[25] = 32'h0; //GAPR4 + rm[26] = 32'h0; //GAPR5 + rm[27] = 32'h0; //GAPR6 + rm[28] = 32'h0; //GAPR7 + rm[29] = 32'h0; //LCPR + rm[30] = 32'h0; //AMPR0 + rm[31] = 32'h0; //AMPR1 + rm[32] = 32'h0; //AMPR2 + rm[33] = 32'h0; //AMPR3 + rm[34] = 32'h0; //BIASR0 + rm[35] = 32'h0; //BIASR1 + rm[36] = 32'h0; //BIASR2 + rm[37] = 32'h0; //BIASR3 + rm[38] = 32'h0; //RTIMR + rm[39] = 32'h0; //ICNTR + rm[40] = 32'h0; //FSIR + rm[41] = 32'h0; //INTPSELR + + + + + fork + + + while(1) begin: write_reg_RW + + @(negedge xif.wren); + + RWreg_write(xif.addr,xif.din); + + end: write_reg_RW + + + + while(1) begin: update_reg_RO + + @(negedge xif.rden); + + ROreg_update(xif.addr); + + end: update_reg_RO + + + while(1) begin: read_reg + + @(negedge xif.rden); + + reg_read(xif.addr); + + end: read_reg + + + + while(1) begin: output_port + + @(negedge xif.wren); + + output_trace(xif.addr); + + end: output_port + + + join + +endtask: do_imitate + + + +task mcu_refmodel::RWreg_write(bit[24:0] addr,bit[32:0] din); + + bit[31:0] wrmask; + + //make mask into 32bit + wrmask = {{8{mif.wrmask[3]}},{8{mif.wrmask[2]}},{8{mif.wrmask[1]}},{8{mif.wrmask[0]}}}; + + //delay caused by decoder + @(posedge wif.clk); + + case(addr[24: 2]) + 23'h1C0004: rm[ 4] = wrmask ? din : rm[ 4]; //MCURESR0 + 23'h1C0005: rm[ 5] = wrmask ? din : rm[ 5]; //MCURESR1 + 23'h1C0006: rm[ 6] = wrmask ? din : rm[ 6]; //MCURESR2 + 23'h1C0007: rm[ 7] = wrmask ? din : rm[ 7]; //MCURESR3 + 23'h1C0010: rm[16] = wrmask ? din : rm[16]; //CWFR0 + 23'h1C0011: rm[17] = wrmask ? din : rm[17]; //CWFR1 + 23'h1C0012: rm[18] = wrmask ? din : rm[18]; //CWFR2 + 23'h1C0013: rm[19] = wrmask ? din : rm[19]; //CWFR3 + 23'h1C0014: rm[20] = wrmask[0 : 0] ? {din[0 : 0],rm[20][31: 1]} : rm[20]; //CWPRR + 23'h1C0015: rm[21] = wrmask[31:16] ? {din[31:16],rm[21][31:16]} : rm[21]; //GAPR0 + 23'h1C0016: rm[22] = wrmask[31:16] ? {din[31:16],rm[22][31:16]} : rm[22]; //GAPR1 + 23'h1C0017: rm[23] = wrmask[31:16] ? {din[31:16],rm[23][31:16]} : rm[23]; //GAPR2 + 23'h1C0018: rm[24] = wrmask[31:16] ? {din[31:16],rm[24][31:16]} : rm[24]; //GAPR3 + 23'h1C0019: rm[25] = wrmask[31:16] ? {din[31:16],rm[25][31:16]} : rm[25]; //GAPR4 + 23'h1C001a: rm[26] = wrmask[31:16] ? {din[31:16],rm[26][31:16]} : rm[26]; //GAPR5 + 23'h1C001b: rm[27] = wrmask[31:16] ? {din[31:16],rm[27][31:16]} : rm[27]; //GAPR6 + 23'h1C001c: rm[28] = wrmask[31:16] ? {din[31:16],rm[28][31:16]} : rm[28]; //GAPR7 + 23'h1C001d: rm[29] = wrmask[31:16] ? {din[31:16],rm[29][31:16]} : rm[29]; //LCPR + 23'h1C001e: rm[30] = wrmask[31:16] ? {din[31:16],rm[30][31:16]} : rm[30]; //AMPR0 + 23'h1C001f: rm[31] = wrmask[31:16] ? {din[31:16],rm[31][31:16]} : rm[31]; //AMPR1 + 23'h1C0020: rm[32] = wrmask[31:16] ? {din[31:16],rm[32][31:16]} : rm[32]; //AMPR2 + 23'h1C0021: rm[33] = wrmask[31:16] ? {din[31:16],rm[33][31:16]} : rm[33]; //AMPR3 + 23'h1C0022: rm[34] = wrmask[31:16] ? {din[31:16],rm[34][31:16]} : rm[34]; //BIASR0 + 23'h1C0023: rm[35] = wrmask[31:16] ? {din[31:16],rm[35][31:16]} : rm[35]; //BIASR1 + 23'h1C0024: rm[36] = wrmask[31:16] ? {din[31:16],rm[36][31:16]} : rm[36]; //BIASR2 + 23'h1C0025: rm[37] = wrmask[31:16] ? {din[31:16],rm[37][31:16]} : rm[37]; //BIASR3 + 23'h1C0029: rm[41] = wrmask[1 : 0] ? {rm[37][31:2 ],din[1 : 0]} : rm[41]; //INTPSELR + endcase + + @(posedge wif.clk); + case(addr[24: 2]) + 23'h04_0014: rm[12] = 32'b0; + endcase +/* $display("mask:%h",wrmask); + $display("addr:%0h",addr); + $display("rm[%d]:%h",addr[15:2],rm[addr[15: 2]]); + $display("din:%h",din);//*/ + +endtask: RWreg_write + + + +task mcu_refmodel::ROreg_update(bit[24:0] addr); + + //@(posedge wif.clk); + + rm[ 0] = mif.mcu_param[0]; //MCUPARAR0 + rm[ 1] = mif.mcu_param[1]; //MCUPARAR1 + rm[ 2] = mif.mcu_param[2]; //MCUPARAR2 + rm[ 3] = mif.mcu_param[3]; //MCUPARAR3 + rm[38] = mif.run_time ; //RTIMR + rm[39] = mif.instr_num ; //ICNTR + rm[40] = {rm[32][31:2],mif.fb_st_info[1:0]}; //FSIR + +endtask: ROreg_update + + +task mcu_refmodel::reg_read(bit[24:0] addr); + + + //delay caused be decoder + //@(posedge wif.clk); + + case(addr[24: 2]) + 23'h1C0000: dout.push_back(rm[ 0]); //MCUPARAR0 + 23'h1C0001: dout.push_back(rm[ 1]); //MCUPARAR1 + 23'h1C0002: dout.push_back(rm[ 2]); //MCUPARAR2 + 23'h1C0003: dout.push_back(rm[ 3]); //MCUPARAR3 + 23'h1C0004: dout.push_back(rm[ 4]); //MCURESR0 + 23'h1C0005: dout.push_back(rm[ 5]); //MCURESR1 + 23'h1C0006: dout.push_back(rm[ 6]); //MCURESR2 + 23'h1C0007: dout.push_back(rm[ 7]); //MCURESR3 + 23'h1C0008: dout.push_back(32'b0) ; + 23'h1C0010: dout.push_back(rm[16]); //CWFR0 + 23'h1C0011: dout.push_back(rm[17]); //CWFR1 + 23'h1C0012: dout.push_back(rm[18]); //CWFR2 + 23'h1C0013: dout.push_back(rm[19]); //CWFR3 + 23'h1C0014: dout.push_back(rm[20]); //CWPRR + 23'h1C0015: dout.push_back(rm[21]); //GAPR0 + 23'h1C0016: dout.push_back(rm[22]); //GAPR1 + 23'h1C0017: dout.push_back(rm[23]); //GAPR2 + 23'h1C0018: dout.push_back(rm[24]); //GAPR3 + 23'h1C0019: dout.push_back(rm[25]); //GAPR4 + 23'h1C001a: dout.push_back(rm[26]); //GAPR5 + 23'h1C001b: dout.push_back(rm[27]); //GAPR6 + 23'h1C001c: dout.push_back(rm[28]); //GAPR7 + 23'h1C001d: dout.push_back(rm[29]); //LCPR + 23'h1C001e: dout.push_back(rm[30]); //AMPR0 + 23'h1C001f: dout.push_back(rm[31]); //AMPR1 + 23'h1C0020: dout.push_back(rm[32]); //AMPR2 + 23'h1C0021: dout.push_back(rm[33]); //AMPR3 + 23'h1C0022: dout.push_back(rm[34]); //BIASR0 + 23'h1C0023: dout.push_back(rm[35]); //BIASR1 + 23'h1C0024: dout.push_back(rm[36]); //BIASR2 + 23'h1C0025: dout.push_back(rm[37]); //BIASR3 + 23'h1C0026: dout.push_back(rm[38]); //RTIMR + 23'h1C0027: dout.push_back(rm[39]); //ICNTR + 23'h1C0028: dout.push_back(rm[40]); //FSIR + 23'h1C0029: dout.push_back(rm[41]); //INTPSELR + 23'h1C002a: dout.push_back(32'b0) ; + endcase +// $display("dout:%h",dout[$]); + +endtask: reg_read + + + +task mcu_refmodel::output_trace(bit[24:0] addr); + + mcureg_trans tr_temp; + + //delay caused by decoder + @(posedge wif.clk); + + @(negedge wif.clk); + tr_temp = new(); + if(addr[24:20] == 5'h7) + begin + tr_temp.mcu_result[0] = rm[ 4] ; //MCURESR0 + tr_temp.mcu_result[1] = rm[ 5] ; //MCURESR1 + tr_temp.mcu_result[2] = rm[ 6] ; //MCURESR2 + tr_temp.mcu_result[3] = rm[ 7] ; //MCURESR3 + tr_temp.mcu_cwfr[0] = rm[16] ; //CWFR0 + tr_temp.mcu_cwfr[1] = rm[17] ; //CWFR1 + tr_temp.mcu_cwfr[2] = rm[18] ; //CWFR2 + tr_temp.mcu_cwfr[3] = rm[19] ; //CWFR3 + tr_temp.mcu_nco_pha_clr = rm[20][0 : 0]; //CWPRR + tr_temp.mcu_gapr[0] = rm[21][31:16]; //GAPR0 + tr_temp.mcu_gapr[1] = rm[22][31:16]; //GAPR1 + tr_temp.mcu_gapr[2] = rm[23][31:16]; //GAPR2 + tr_temp.mcu_gapr[3] = rm[24][31:16]; //GAPR3 + tr_temp.mcu_gapr[4] = rm[25][31:16]; //GAPR4 + tr_temp.mcu_gapr[5] = rm[26][31:16]; //GAPR5 + tr_temp.mcu_gapr[6] = rm[27][31:16]; //GAPR6 + tr_temp.mcu_gapr[7] = rm[28][31:16]; //GAPR7 + tr_temp.mcu_rz_pha = rm[29][15: 0]; //LCPR + tr_temp.mcu_ampr[0] = rm[30][31:16]; //AMPR0 + tr_temp.mcu_ampr[1] = rm[31][31:16]; //AMPR1 + tr_temp.mcu_ampr[2] = rm[32][31:16]; //AMPR2 + tr_temp.mcu_ampr[3] = rm[33][31:16]; //AMPR3 + tr_temp.mcu_baisr[0] = rm[34][31:16]; //BIASR0 + tr_temp.mcu_baisr[1] = rm[35][31:16]; //BIASR1 + tr_temp.mcu_baisr[2] = rm[36][31:16]; //BIASR2 + tr_temp.mcu_baisr[3] = rm[37][31:16]; //BIASR3 + tr_temp.mcu_intp_sel = rm[38][1 : 0]; //INTPSELR + + + mcuout.push_back(tr_temp); + end + //$display("addr:%0h",addr); + + //$display("rm:",rm); + //$display("din:%h",din); + +endtask: output_trace diff --git a/tb/mcureg_tb/mcureg_driver.sv b/tb/mcureg_tb/mcureg_driver.sv new file mode 100644 index 0000000..e76545b --- /dev/null +++ b/tb/mcureg_tb/mcureg_driver.sv @@ -0,0 +1,65 @@ +class mcureg_driver; + + + mcureg_trans tr; + + //interface + virtual mcureg_if mif; + virtual spi_if wif; + + + function new(); + endfunction + extern task do_drive(); + extern task make_pkt(); + +endclass : mcureg_driver + +task mcureg_driver::do_drive(); + + mif.fb_st_info = 2'b0 ; + mif.run_time = 32'b0 ; + mif.instr_num = 32'b0 ; + mif.mcu_param[3:0] = {32'b0,32'b0,32'b0,32'b0} ; + + fork + + while(1) begin + make_pkt(); + end + + join + +endtask + +task mcureg_driver::make_pkt(); + int cnt=0; + + cnt = 0; + + + tr = new(); + if(!tr.randomize()) + $fatal(0,"Randomize Failed"); + + + while(cnt<2000) begin + @(posedge wif.clk); + + cnt = cnt + 1; + + case(cnt) + tr.wrmask_time: mif.wrmask <= tr.wrmask; + tr.fb_st_info_time: mif.fb_st_info <= tr.fb_st_info; + tr.run_time_time: mif.run_time <= tr.run_time; + tr.instr_num_time: mif.instr_num <= tr.instr_num; + tr.mcu_param_time[0]: mif.mcu_param[0] <= tr.mcu_param[0]; + tr.mcu_param_time[1]: mif.mcu_param[1] <= tr.mcu_param[1]; + tr.mcu_param_time[2]: mif.mcu_param[2] <= tr.mcu_param[2]; + tr.mcu_param_time[3]: mif.mcu_param[3] <= tr.mcu_param[3]; + endcase + + end + +endtask : make_pkt + diff --git a/tb/mcureg_tb/mcureg_env.sv b/tb/mcureg_tb/mcureg_env.sv new file mode 100644 index 0000000..df6fcc1 --- /dev/null +++ b/tb/mcureg_tb/mcureg_env.sv @@ -0,0 +1,103 @@ +class mcureg_env; + + + static int pktnum; + + //Interface: + virtual mcureg_if mif; + virtual spi_if wif; + virtual sram_if#(25,32) xif; + + //Component: + spi_driver w_driver; + mcureg_driver m_driver; + spi_monitor w_monitor; + mcu_refmodel m_model; + mcureg_monitor m_monitor; + mcureg_scoreboard m_scb; + + + function new(); + endfunction; + + extern function build(); + + extern task run(); + +endclass + +function mcureg_env::build(); + + w_driver = new(); + if(!w_driver.randomize() with { + error_time < 0; + }) + $fatal(0,"Randomize Failed"); + w_driver.pktnum = pktnum; + w_driver.vif = wif; + w_driver.autarchy = 1'b1; + w_driver.half_sclk = 4; + + w_monitor = new(); + w_monitor.wif = wif; + w_monitor.xif = xif; + + m_driver = new(); + m_driver.mif = mif; + m_driver.wif = wif; + + m_monitor = new(); + m_monitor.mif = mif; + m_monitor.xif = xif; + + m_model = new(); + m_model.mif = mif; + m_model.wif = wif; + m_model.xif = xif; + + m_scb = new(); + +endfunction + + +task mcureg_env::run(); + int error=0; + + fork + + w_driver.do_drive(); + + m_driver.do_drive(); + + w_monitor.do_mon(); + + m_monitor.do_mon(); + + m_model.do_imitate(); + + + while(1) begin + repeat(2) @(posedge wif.csn); + @(posedge wif.clk); + m_model.dout.pop_back(); + if(m_scb.compare( + m_model.dout , + w_monitor.act_trans.data , + m_model.mcuout , + m_monitor.act_trans + )) + error++; + m_model.dout.delete(); + m_model.mcuout.delete(); + m_monitor.act_trans.delete(); + end + + + join + + $display("SCOREBOARD:"); + $display("\tError_mcu:\t%0d",error); + + +endtask + diff --git a/tb/mcureg_tb/mcureg_if.sv b/tb/mcureg_tb/mcureg_if.sv new file mode 100644 index 0000000..8108a3d --- /dev/null +++ b/tb/mcureg_tb/mcureg_if.sv @@ -0,0 +1,28 @@ + + +interface mcureg_if(input clk,input rstn); + + //input port + logic [3 :0] wrmask ; + logic [2 :0] fb_st_info ; + logic [31 :0] run_time ; + logic [31 :0] instr_num ; + logic [31 :0] mcu_param [3:0] ; // MCU parameter 0~3 + + //output port + logic [31 :0] mcu_result [3:0] ; // MCU result 0~3 + logic [31 :0] mcu_cwfr [3:0] ; // Carrier frequency ctrl word 0~3 + logic [31 :0] mcu_gapr [7:0] ; // Carrier phase ctrl word 0~3 + logic [31 :0] mcu_ampr [3:0] ; // Carrier Amplitude 0~3 + logic [31 :0] mcu_baisr [3:0] ; // Carrier Bais 0~3 + logic [1 :0] mcu_intp_sel ; //2'b00:HBF;2'b01:Nearest-neighbor interpolator; + logic mcu_nco_pha_clr ; + logic [15 :0] mcu_rz_pha ; + + + + +endinterface : mcureg_if + + + diff --git a/tb/mcureg_tb/mcureg_monitor.sv b/tb/mcureg_tb/mcureg_monitor.sv new file mode 100644 index 0000000..75df705 --- /dev/null +++ b/tb/mcureg_tb/mcureg_monitor.sv @@ -0,0 +1,49 @@ +class mcureg_monitor; + + + virtual mcureg_if mif; + virtual sram_if#(25,32) xif; + + //collect + mcureg_trans act_trans[$]; + + + function new(); + endfunction + extern task collect(); + extern task do_mon(); + +endclass : mcureg_monitor + + +task mcureg_monitor::do_mon(); + + while(1) begin + @(negedge xif.wren); + collect(); + end + +endtask: do_mon + + + + +task mcureg_monitor::collect(); + mcureg_trans tr_temp; + + @(posedge xif.clk); + @(negedge xif.clk); + + tr_temp = new(); + tr_temp.mcu_result = mif.mcu_result ; + tr_temp.mcu_cwfr = mif.mcu_cwfr ; + tr_temp.mcu_gapr = mif.mcu_gapr ; + tr_temp.mcu_ampr = mif.mcu_ampr ; + tr_temp.mcu_baisr = mif.mcu_baisr ; + tr_temp.mcu_intp_sel = mif.mcu_intp_sel ; + tr_temp.mcu_nco_pha_clr = mif.mcu_nco_pha_clr ; + tr_temp.mcu_rz_pha = mif.mcu_rz_pha ; + + act_trans.push_back(tr_temp); + +endtask: collect diff --git a/tb/mcureg_tb/mcureg_scb.sv b/tb/mcureg_tb/mcureg_scb.sv new file mode 100644 index 0000000..d72bf68 --- /dev/null +++ b/tb/mcureg_tb/mcureg_scb.sv @@ -0,0 +1,91 @@ +class mcureg_scoreboard; + integer fid; + + function new(); + endfunction; + + //extern task do_check(); + + extern function bit compare( + bit[31:0] spi_exp[$], + bit[31:0] spi_act[$], + mcureg_trans mcu_exp[$], + mcureg_trans mcu_act[$] + ); + +endclass + +function bit mcureg_scoreboard::compare( + bit[31:0] spi_exp[$], + bit[31:0] spi_act[$], + mcureg_trans mcu_exp[$], + mcureg_trans mcu_act[$] +); + + bit result=1'b1; + int i=0; + +//$display(dout); + + if(spi_exp.size() != spi_act.size()) begin + result = 1'b0; + //$display("ScoreBoard(ERROR): write & read datanum ARNT'T equal!"); + //$display("Exp spi_data size:%0d",spi_exp.size()); + //$display("Act spi_data size:%0d",spi_act.size()); + $fwrite(fid,"ScoreBoard(ERROR): write & read datanum ARNT'T equal!\n"); + $fwrite(fid,"Exp spi_data size:%0d\n",spi_exp.size()); + $fwrite(fid,"Act spi_data size:%0d\n",spi_act.size()); + end + + else if(mcu_exp.size() != mcu_act.size()) begin + result = 1'b0; + //$display("ScoreBoard(ERROR): regmdl & read datanum ARNT'T equal!"); + //$display("Exp mcu_trs size:%0d",mcu_exp.size()); + //$display("Act mcu_trs size:%0d",mcu_act.size()); + $fwrite(fid,"ScoreBoard(ERROR): regmdl & read datanum ARNT'T equal!\n"); + $fwrite(fid,"Exp mcu_trs size:%0d\n",mcu_exp.size()); + $fwrite(fid,"Act mcu_trs size:%0d\n",mcu_act.size()); + end + + + else + for(i=0;i= 0 ; + fb_st_info_time >= 0 ; + run_time_time >= 0 ; + instr_num_time >= 0 ; + mcu_param_time[0] >= 0 ; + mcu_param_time[1] >= 0 ; + mcu_param_time[2] >= 0 ; + mcu_param_time[3] >= 0 ; + wrmask_time <= 2000 ; + fb_st_info_time <= 2000 ; + run_time_time <= 2000 ; + instr_num_time <= 2000 ; + mcu_param_time[0] <= 2000 ; + mcu_param_time[1] <= 2000 ; + mcu_param_time[2] <= 2000 ; + mcu_param_time[3] <= 2000 ; +} + + function new(); + endfunction + + function bit[7:0] compare(mcureg_trans tr); + bit[7:0] result=8'b0; + if(tr.mcu_result != mcu_result ) result[0]=1'b1; + if(tr.mcu_cwfr != mcu_cwfr ) result[1]=1'b1; + if(tr.mcu_gapr != mcu_gapr ) result[2]=1'b1; + if(tr.mcu_ampr != mcu_ampr ) result[3]=1'b1; + if(tr.mcu_baisr != mcu_baisr ) result[4]=1'b1; + if(tr.mcu_intp_sel != mcu_intp_sel ) result[5]=1'b1; + if(tr.mcu_nco_pha_clr != mcu_nco_pha_clr) result[6]=1'b1; + if(tr.mcu_rz_pha != mcu_rz_pha ) result[7]=1'b1; + return result; + endfunction + + function print(bit[7:0] ctrl,integer fid); + if(ctrl[0]) begin + $fwrite(fid,"mcu_result0 =%b\n",mcu_result[0] ); + $fwrite(fid,"mcu_result1 =%b\n",mcu_result[1] ); + $fwrite(fid,"mcu_result2 =%b\n",mcu_result[2] ); + $fwrite(fid,"mcu_result3 =%b\n",mcu_result[3] ); + end + if(ctrl[1]) begin + $fwrite(fid,"mcu_cwfr0 =%b\n",mcu_cwfr[0] ); + $fwrite(fid,"mcu_cwfr1 =%b\n",mcu_cwfr[1] ); + $fwrite(fid,"mcu_cwfr2 =%b\n",mcu_cwfr[2] ); + $fwrite(fid,"mcu_cwfr3 =%b\n",mcu_cwfr[3] ); + end + if(ctrl[2]) begin + $fwrite(fid,"mcu_gapr0 =%b\n",mcu_gapr[0] ); + $fwrite(fid,"mcu_gapr1 =%b\n",mcu_gapr[1] ); + $fwrite(fid,"mcu_gapr2 =%b\n",mcu_gapr[2] ); + $fwrite(fid,"mcu_gapr3 =%b\n",mcu_gapr[3] ); + $fwrite(fid,"mcu_gapr4 =%b\n",mcu_gapr[4] ); + $fwrite(fid,"mcu_gapr5 =%b\n",mcu_gapr[5] ); + $fwrite(fid,"mcu_gapr6 =%b\n",mcu_gapr[6] ); + $fwrite(fid,"mcu_gapr7 =%b\n",mcu_gapr[7] ); + end + if(ctrl[3]) begin + $fwrite(fid,"mcu_ampr0 =%b\n",mcu_ampr[0] ); + $fwrite(fid,"mcu_ampr1 =%b\n",mcu_ampr[1] ); + $fwrite(fid,"mcu_ampr2 =%b\n",mcu_ampr[2] ); + $fwrite(fid,"mcu_ampr3 =%b\n",mcu_ampr[3] ); + end + if(ctrl[4]) begin + $fwrite(fid,"mcu_baisr0 =%b\n",mcu_baisr[0] ); + $fwrite(fid,"mcu_baisr1 =%b\n",mcu_baisr[1] ); + $fwrite(fid,"mcu_baisr2 =%b\n",mcu_baisr[2] ); + $fwrite(fid,"mcu_baisr3 =%b\n",mcu_baisr[3] ); + end + if(ctrl[5]) $fwrite(fid,"mcu_intp_sel =%b\n",mcu_intp_sel ); + if(ctrl[6]) $fwrite(fid,"mcu_nco_pha_clr =%b\n",mcu_nco_pha_clr); + if(ctrl[7]) $fwrite(fid,"mcu_rz_pha =%b\n",mcu_rz_pha ); + endfunction + +endclass : mcureg_trans diff --git a/tb/pllreg_tb/pll_refmodel.sv b/tb/pllreg_tb/pll_refmodel.sv new file mode 100644 index 0000000..3e3108c --- /dev/null +++ b/tb/pllreg_tb/pll_refmodel.sv @@ -0,0 +1,300 @@ +//For intpll_regfile, the ROreg: status is updated by the pll_lock at present +//update output wire after wren, but the divsync_r & syncoe_r needn't update +class pll_refmodel; + + virtual pllreg_if pif; + virtual spi_if wif; + virtual sram_if#(25,32) xif; + + + //poor-quality register model + bit[31:0] rm[22]; + bit[31:0] update_rm[22]; + + //members to be sent to scoreboard + int rst_error[5]; + bit[31:0] dout[$]; + pllreg_trans pllout[$]; + + + + function new(); + endfunction + extern task do_imitate(); + extern task RWreg_write (bit[24:0] addr,bit[32:0] din ); + extern task ROreg_update (bit[24:0] addr ); + extern task reg_read (bit[24:0] addr ); + extern task output_trace (bit[24:0] addr ); + +endclass : pll_refmodel + +task pll_refmodel::do_imitate(); + + int i=0,j=0; + + rm[ 0] = 32'h0006_0000; //INTPLL_REFCTRL 8'h00 + rm[ 1] = 32'h000C_0000; //INTPLL_PCNT 8'h04 + rm[ 2] = 32'h0006_0000; //INTPLL_PFDCTRL 8'h08 + rm[ 3] = 32'h0004_0000; //INTPLL_SPDCTRL 8'h0C + rm[ 4] = 32'h0058_0000; //INTPLL_PTATCTRL 8'h10 + rm[ 5] = 32'h0003_0000; //INTPLL_FLLCTRL 8'h14 + rm[ 6] = 32'h0002_0000; //INTPLL_SELCTRL 8'h18 + rm[ 7] = 32'h0ff0_0000; //INTPLL_VCOCTRL 8'h1C + rm[ 8] = 32'h0; //INTPLL_VCOFBADJ 8'h20 + rm[ 9] = 32'h0; //INTPLL_AFCCTRL 8'h24 + rm[10] = 32'h00C8_0000; //INTPLL_AFCCNT 8'h28 + rm[11] = 32'h0640_0000; //INTPLL_AFCLDCNT 8'h2C + rm[12] = 32'h0003_0000; //INTPLL_AFCPRES 8'h30 + rm[13] = 32'h0; //INTPLL_AFCLDTCC 8'h34 + rm[14] = 32'h0; //INTPLL_AFCFBTCC 8'h38 + rm[15] = 32'h0; //INTPLL_DIVCFG 8'h3C + rm[16] = 32'h0; //INTPLL_TCLKCFG 8'h40 + rm[17] = 32'h1_0000; //INTPLL_DCLKSEL 8'h44 + rm[18] = 32'h0; //INTPLL_STATUS 8'h48 + rm[19] = 32'h0; //INTPLL_SYNCFG 8'h4C + rm[20] = 32'h0; //INTPLL_UPDATE 8'h50 + rm[21] = 32'h0; //INTPLL_CLKRXPD 8'h54 + + update_rm[ 0] = 32'h0006_0000; + update_rm[ 1] = 32'h000C_0000; + update_rm[ 2] = 32'h0006_0000; + update_rm[ 3] = 32'h0004_0000; + update_rm[ 4] = 32'h0058_0000; + update_rm[ 5] = 32'h0003_0000; + update_rm[ 6] = 32'h0002_0000; + update_rm[ 7] = 32'h0ff0_0000; + update_rm[ 8] = 32'h0; + update_rm[ 9] = 32'h0; + update_rm[10] = 32'h00C8_0000; + update_rm[11] = 32'h0640_0000; + update_rm[12] = 32'h0003_0000; + update_rm[13] = 32'h0; + update_rm[14] = 32'h0; + update_rm[15] = 32'h0; + update_rm[16] = 32'h0; + update_rm[17] = 32'h1_0000; + update_rm[18] = 32'h0; + update_rm[19] = 32'h0; + update_rm[20] = 32'h0; + update_rm[21] = 32'h0; + + + fork + + + while(1) begin: write_reg_RW + + @(negedge xif.wren); + + RWreg_write(xif.addr,xif.din); + + end: write_reg_RW + + + + while(1) begin: update_reg_RO + + ROreg_update(xif.addr); + + end: update_reg_RO + + + while(1) begin: read_reg + + @(negedge xif.rden); + + reg_read(xif.addr); + + end: read_reg + + + + while(1) begin: output_port + + @(negedge xif.wren); + + output_trace(xif.addr); + + end: output_port + + + join + +endtask: do_imitate + + + +task pll_refmodel::RWreg_write(bit[24:0] addr,bit[32:0] din); + + //delay caused by decoder + @(posedge wif.sclk); + case(addr[24: 2]) + 23'h7C0000: rm[ 0] = {rm[ 0][31:17+ 2],din[16+ 2:16],rm[ 0][15:0]}; //INTPLL_REFCTRL + 23'h7C0001: rm[ 1] = {rm[ 1][31:17+ 6],din[16+ 6:16],rm[ 1][15:0]}; //INTPLL_PCNT + 23'h7C0002: rm[ 2] = {rm[ 2][31:17+ 2],din[16+ 2:16],rm[ 2][15:0]}; //INTPLL_PFDCTRL + 23'h7C0003: rm[ 3] = {rm[ 3][31:17+ 5],din[16+ 5:16],rm[ 3][15:0]}; //INTPLL_SPDCTRL + 23'h7C0004: rm[ 4] = {rm[ 4][31:17+ 6],din[16+ 6:16],rm[ 4][15:0]}; //INTPLL_PTATCTRL + 23'h7C0005: rm[ 5] = {rm[ 5][31:17+ 2],din[16+ 2:16],rm[ 5][15:0]}; //INTPLL_FLLCTRL + 23'h7C0006: rm[ 6] = {rm[ 6][31:17+ 2],din[16+ 2:16],rm[ 6][15:0]}; //INTPLL_SELCTRL + 23'h7C0007: rm[ 7] = {rm[ 7][31:17+11],din[16+11:16],rm[ 7][15:0]}; //INTPLL_VCOCTRL + 23'h7C0008: rm[ 8] = {rm[ 8][31:17+ 6],din[16+ 6:16],rm[ 8][15:0]}; //INTPLL_VCOFBADJ + 23'h7C0009: rm[ 9] = {rm[ 9][31:17+ 4],din[16+ 4:16],rm[ 9][15:0]}; //INTPLL_AFCCTRL + 23'h7C000a: rm[10] = {rm[10][31:17+10],din[16+10:16],rm[10][15:0]}; //INTPLL_AFCCNT + 23'h7C000b: rm[11] = {rm[11][31:17+10],din[16+10:16],rm[11][15:0]}; //INTPLL_AFCLDCNT + 23'h7C000c: rm[12] = {rm[12][31:17+ 3],din[16+ 3:16],rm[12][15:0]}; //INTPLL_AFCPRES + 23'h7C000d: rm[13] = {rm[13][31:17+14],din[16+14:16],rm[13][15:0]}; //INTPLL_AFCLDTCC + 23'h7C000e: rm[14] = {rm[14][31:17+14],din[16+14:16],rm[14][15:0]}; //INTPLL_AFCFBTCC + 23'h7C000f: rm[15] = {rm[15][31:17+ 0],din[16+ 0:16],rm[15][15:0]}; //INTPLL_DIVCFG + 23'h7C0010: rm[16] = {rm[16][31:17+ 2],din[16+ 2:16],rm[16][15:0]}; //INTPLL_TCLKCFG + 23'h7C0011: rm[17] = {rm[17][31:17+ 7],din[16+ 7:16],rm[17][15:0]}; //INTPLL_DCLKSEL + 23'h7C0013: rm[19] = {rm[19][31:17+ 1],din[16+ 1:16],rm[19][15:0]}; //INTPLL_SYNCFG + 23'h7C0015: rm[21] = {rm[21][31:17+ 0],din[16+ 0:16],rm[21][15:0]}; //CLKRXPD + endcase +//$display("addr:%0h",addr); +//$display("rm:%h",rm[addr[15: 2]]); +//$display("din:%h",din); + +endtask: RWreg_write + + + +task pll_refmodel::ROreg_update(bit[24:0] addr); + + @(negedge wif.sclk); + + rm[18] = pif.pll_lock ; + +endtask: ROreg_update + + +task pll_refmodel::reg_read(bit[24:0] addr); + + + //delay caused be decoder + @(posedge wif.clk); + case(addr[24: 2]) + 23'h7C0000: dout.push_back(rm[ 0]); //INTPLL_REFCTRL 8'h00 + 23'h7C0001: dout.push_back(rm[ 1]); //INTPLL_PCNT 8'h04 + 23'h7C0002: dout.push_back(rm[ 2]); //INTPLL_PFDCTRL 8'h08 + 23'h7C0003: dout.push_back(rm[ 3]); //INTPLL_SPDCTRL 8'h0C + 23'h7C0004: dout.push_back(rm[ 4]); //INTPLL_PTATCTRL 8'h10 + 23'h7C0005: dout.push_back(rm[ 5]); //INTPLL_FLLCTRL 8'h14 + 23'h7C0006: dout.push_back(rm[ 6]); //INTPLL_SELCTRL 8'h18 + 23'h7C0007: dout.push_back(rm[ 7]); //INTPLL_VCOCTRL 8'h1C + 23'h7C0008: dout.push_back(rm[ 8]); //INTPLL_VCOFBADJ 8'h20 + 23'h7C0009: dout.push_back(rm[ 9]); //INTPLL_AFCCTRL 8'h24 + 23'h7C000a: dout.push_back(rm[10]); //INTPLL_AFCCNT 8'h28 + 23'h7C000b: dout.push_back(rm[11]); //INTPLL_AFCLDCNT 8'h2C + 23'h7C000c: dout.push_back(rm[12]); //INTPLL_AFCPRES 8'h30 + 23'h7C000d: dout.push_back(rm[13]); //INTPLL_AFCLDTCC 8'h34 + 23'h7C000e: dout.push_back(rm[14]); //INTPLL_AFCFBTCC 8'h38 + 23'h7C000f: dout.push_back(rm[15]); //INTPLL_DIVCFG 8'h3C + 23'h7C0010: dout.push_back(rm[16]); //INTPLL_TCLKCFG 8'h40 + 23'h7C0011: dout.push_back(rm[17]); //INTPLL_DCLKSEL 8'h44 + 23'h7C0012: dout.push_back({rm[18][15:0],rm[18][31:16]}); //INTPLL_STATUS 8'h48 + 23'h7C0013: dout.push_back(rm[19]); //INTPLL_SYNCFG 8'h4C + 23'h7C0014: dout.push_back({rm[20][15:0],rm[20][31:16]}); //INTPLL_UPDATE 8'h50 + 23'h7C0015: dout.push_back(rm[21]); //INTPLL_CLKRXPD 8'h54 + 23'h7C0016: dout.push_back(0); + endcase + //$display("dout:%h",dout[$]); + +endtask: reg_read + + + +task pll_refmodel::output_trace(bit[24:0] addr); + + pllreg_trans tr_temp; + + //delay caused by decoder + // @(posedge wif.sclk); + if(addr[24:2]==23'h7c0014) begin + update_rm[ 0] = rm[ 0]; //INTPLL_REFCTRL + update_rm[ 1] = rm[ 1]; //INTPLL_PCNT + update_rm[ 2] = rm[ 2]; //INTPLL_PFDCTRL + update_rm[ 3] = rm[ 3]; //INTPLL_SPDCTRL + update_rm[ 4] = rm[ 4]; //INTPLL_PTATCTRL + update_rm[ 5] = rm[ 5]; //INTPLL_FLLCTRL + update_rm[ 6] = rm[ 6]; //INTPLL_SELCTRL + update_rm[ 7] = rm[ 7]; //INTPLL_VCOCTRL + update_rm[ 8] = rm[ 8]; //INTPLL_VCOFBADJ + update_rm[ 9] = rm[ 9]; //INTPLL_AFCCTRL + update_rm[10] = rm[10]; //INTPLL_AFCCNT + update_rm[11] = rm[11]; //INTPLL_AFCLDCNT + update_rm[12] = rm[12]; //INTPLL_AFCPRES + update_rm[13] = rm[13]; //INTPLL_AFCLDTCC + update_rm[14] = rm[14]; //INTPLL_AFCFBTCC + update_rm[15] = rm[15]; //INTPLL_DIVCFG + update_rm[16] = rm[16]; //INTPLL_TCLKCFG + update_rm[17] = rm[17]; //INTPLL_DCLKSEL + //update_rm[18] = rm[18]; + //update_rm[21] = rm[21]; + end + + @(negedge wif.sclk); + + tr_temp = new(); + if(addr[24:20] == 5'h1F) begin + tr_temp.ref_sel = update_rm[ 0][16+0] ; // Clock source selection for a frequency divider; + // 1'b0:External clock source + // 1'b1:internal phase-locked loop clock source + tr_temp.ref_en = update_rm[ 0][16+1] ; // Input reference clock enable + // 1'b0:enable,1'b1:disable + tr_temp.ref_s2d_en = update_rm[ 0][16+2] ; // Referenced clock differential to single-ended conversion enable + // 1'b0:enable,1'b1:disable + tr_temp.p_cnt = update_rm[ 1][16+6 :16]; // P counter + tr_temp.pfd_delay = update_rm[ 2][16+0 ]; // PFD Dead Zone + tr_temp.pfd_dff_Set = update_rm[ 2][16+1 ]; // Setting the PFD register,active high + tr_temp.pfd_dff_4and = update_rm[ 2][16+2 ]; // PFD output polarity + tr_temp.spd_div = update_rm[ 3][16+3 :16]; // SPD Frequency Divider + tr_temp.spd_pulse_width = update_rm[ 3][16+4 ]; // Pulse Width of SPD + tr_temp.spd_pulse_sw = update_rm[ 3][16+5 ]; // Pulse sw of SPD + tr_temp.cpc_sel = update_rm[ 4][16+6 ]; // current source selection + tr_temp.swcp_i = update_rm[ 4][16+5 :16+4]; // PTAT current switch + tr_temp.sw_ptat_r = update_rm[ 4][16+3 :16+0]; // PTAT current adjustment + tr_temp.sw_fll_cpi = update_rm[ 5][16+1 :16+0]; // Phase-locked loop charge pump current + tr_temp.sw_fll_delay = update_rm[ 5][16+2 ]; // PLL Dead Zone + tr_temp.pfd_sel = update_rm[ 6][16+0 ]; // PFD Loop selection + tr_temp.spd_sel = update_rm[ 6][16+1 ]; // SPD Loop selection + tr_temp.fll_sel = update_rm[ 6][16+2 ]; // FLL Loop selection + tr_temp.vco_tc = update_rm[ 7][16+0 ]; // VCO temperature compensation + tr_temp.vco_tcr = update_rm[ 7][16+1 ]; // VCO temperature compensation resistor + tr_temp.vco_gain_adj = update_rm[ 7][16+2 ]; // VCO gain adjustment + tr_temp.vco_gain_adj_r = update_rm[ 7][16+3 ]; // VCO gain adjustment resistor + tr_temp.vco_cur_adj = update_rm[ 7][16+6 :16+4]; // VCO current adjustment + tr_temp.vco_buff_en = update_rm[ 7][16+7 ]; // VCO buff enable,active high + tr_temp.vco_en = update_rm[ 7][16+8 ]; // VCO enable,active high + tr_temp.pll_dpwr_adj = update_rm[ 7][16+11:16+9]; // PLL frequency division output power adjustment + tr_temp.vco_fb_adj = update_rm[ 8][16+6 :16+0]; // VCO frequency band adjustment + tr_temp.afc_en = update_rm[ 9][16+0 ]; // AFC enable + tr_temp.afc_reset = update_rm[ 9][16+1 ]; // AFC reset + tr_temp.afc_shutdown = update_rm[ 9][16+2 ]; // AFC module shutdown signal + tr_temp.flag_out_sel = update_rm[ 9][16+3 ]; // Read and choose the signs + tr_temp.afc_det_speed = update_rm[ 9][16+4 ]; // AFC detection speed + tr_temp.afc_cnt = update_rm[10][16+10:16]; // AFC frequency band adjustment function counter + // counting time adjustment + tr_temp.afc_ld_cnt = update_rm[11][16+10:16] ; // Adjust the counting time of the AFC lock detection + // feature counter + tr_temp.afc_pres = update_rm[12][16+ 3:16] ; // Adjusting the resolution of the AFC comparator + tr_temp.afc_ld_tcc = update_rm[13][16+14:16] ; // AFC Lock Detection Function Target Cycle Count + tr_temp.afc_fb_tcc = update_rm[14][16+14:16] ; // Target number of cycles for AFC frequency band + // adjustment function + repeat(1) @(posedge wif.sclk); + + tr_temp.div_rstn_sel = rm[15][16+0 ] ; // DAC frequency divider frequency control + tr_temp.test_clk_sel = rm[16][16+1:16+0] ; // ADC frequency divider frequency control + tr_temp.test_clk_oen = rm[16][16+2 ] ; // DIGITAL frequency divider frequency contr + tr_temp.dig_clk_sel = rm[17][16+7:16+0] ; + tr_temp.div_sync_en = rm[19][16+0 ] ; // Frequency Divider Synchronous Clear Enable + + tr_temp.sync_oe = rm[19][16+1] ; // SYNC signal output enable, hign active + tr_temp.clkrx_pdn = rm[21][16+0] ; // + pllout.push_back(tr_temp); + end + //$display("addr:%0h",addr); + + //$display("rm:",rm); + //$display("din:%h",din); + +endtask: output_trace diff --git a/tb/pllreg_tb/pllreg_driver.sv b/tb/pllreg_tb/pllreg_driver.sv new file mode 100644 index 0000000..5b02aed --- /dev/null +++ b/tb/pllreg_tb/pllreg_driver.sv @@ -0,0 +1,55 @@ +class pllreg_driver; + + + pllreg_trans tr; + + //interface + virtual pllreg_if pif; + virtual spi_if wif; + + + function new(); + endfunction + extern task do_drive(); + extern task make_pkt(); + +endclass : pllreg_driver + +task pllreg_driver::do_drive(); + + pif.pll_lock =32'b0; + + fork + + while(1) begin + make_pkt(); + end + + join + +endtask + +task pllreg_driver::make_pkt(); + int cnt=0; + + cnt = 0; + + + tr = new(); + if(!tr.randomize()) + $fatal(0,"Randomize Failed"); + + + while(cnt<3000) begin + @(posedge wif.clk); + + cnt = cnt + 1; + + case(cnt) + tr.pll_lock: pif.pll_lock <=tr.pll_lock; + endcase + + end + +endtask : make_pkt + diff --git a/tb/pllreg_tb/pllreg_env.sv b/tb/pllreg_tb/pllreg_env.sv new file mode 100644 index 0000000..0bb378a --- /dev/null +++ b/tb/pllreg_tb/pllreg_env.sv @@ -0,0 +1,103 @@ +class pllreg_env; + + + static int pktnum; + + //Interface: + virtual pllreg_if pif; + virtual spi_if wif; + virtual sram_if#(25,32) xif; + + //Component: + spi_driver w_driver; + pllreg_driver p_driver; + spi_monitor w_monitor; + pll_refmodel p_model; + pllreg_monitor p_monitor; + pllreg_scoreboard p_scb; + + + function new(); + endfunction; + + extern function build(); + + extern task run(); + +endclass + +function pllreg_env::build(); + + w_driver = new(); + if(!w_driver.randomize() with { + error_time < 0; + }) + $fatal(0,"Randomize Failed"); + w_driver.pktnum = pktnum; + w_driver.vif = wif; + w_driver.autarchy = 1'b1; + w_driver.half_sclk = 4; + + w_monitor = new(); + w_monitor.wif = wif; + w_monitor.xif = xif; + + p_driver = new(); + p_driver.pif = pif; + p_driver.wif = wif; + + p_monitor = new(); + p_monitor.pif = pif; + p_monitor.xif = xif; + + p_model = new(); + p_model.pif = pif; + p_model.wif = wif; + p_model.xif = xif; + + p_scb = new(); + +endfunction + + +task pllreg_env::run(); + int error=0; + + fork + + w_driver.do_drive(); + + p_driver.do_drive(); + + w_monitor.do_mon(); + + p_monitor.do_mon(); + + p_model.do_imitate(); + + + while(1) begin + repeat(2) @(posedge wif.csn); + @(posedge wif.clk); + p_model.dout.pop_back(); + if(p_scb.compare( + p_model.dout , + w_monitor.act_trans.data , + p_model.pllout , + p_monitor.act_trans + )) + error++; + p_model.dout.delete(); + p_model.pllout.delete(); + p_monitor.act_trans.delete(); + end + + + join + + $display("SCOREBOARD:"); + $display("\tError_pll:\t%0d",error); + + +endtask + diff --git a/tb/pllreg_tb/pllreg_if.sv b/tb/pllreg_tb/pllreg_if.sv new file mode 100644 index 0000000..daa3349 --- /dev/null +++ b/tb/pllreg_tb/pllreg_if.sv @@ -0,0 +1,73 @@ + + +interface pllreg_if(input clk,input rstn); + + //input port + logic [31 :0] wrdata // write data + ;logic wren // write enable + ;logic [15 :0] rwaddr // read & write address + ;logic rden // read enable + ;logic pll_lock // PLL LOCK + + //output port + ;logic [31 :0] rddata // read data + + ;logic ref_sel // Clock source selection for a frequency divider; + // 1'b0:External clock source + // 1'b1:internal phase-locked loop clock source + ;logic ref_en // logic reference clock enable + // 1'b0:enable;1'b1:disable + ;logic ref_s2d_en // Referenced clock differential to single-ended conversion enable + // 1'b0:enable;1'b1:disable + ;logic [6 :0] p_cnt // P counter + ;logic pfd_delay // PFD Dead Zone + ;logic pfd_dff_Set // Setting the PFD register;active high + ;logic pfd_dff_4and // PFD logic polarity + ;logic [3 :0] spd_div // SPD Frequency Divider + ;logic spd_pulse_width // Pulse Width of SPD + ;logic spd_pulse_sw // Pulse sw of SPD + ;logic cpc_sel // current source selection + ;logic [1 :0] swcp_i // PTAT current switch + ;logic [3 :0] sw_ptat_r // PTAT current adjustment + ;logic [1 :0] sw_fll_cpi // Phase-locked loop charge pump current + ;logic sw_fll_delay // PLL Dead Zone + ;logic pfd_sel // PFD Loop selection + ;logic spd_sel // SPD Loop selection + ;logic fll_sel // FLL Loop selection + ;logic vco_tc // VCO temperature compensation + ;logic vco_tcr // VCO temperature compensation resistor + ;logic vco_gain_adj // VCO gain adjustment + ;logic vco_gain_adj_r // VCO gain adjustment resistor + ;logic [2 :0] vco_cur_adj // VCO current adjustment + ;logic vco_buff_en // VCO buff enable;active high + ;logic vco_en // VCO enable;active high + ;logic [2 :0] pll_dpwr_adj // PLL frequency division logic power adjustment + ;logic [6 :0] vco_fb_adj // VCO frequency band adjustment + ;logic afc_en // AFC enable + ;logic afc_shutdown // AFC module shutdown signal + ;logic [0 :0] afc_det_speed // AFC detection speed + ;logic [0 :0] flag_out_sel // Read and choose the signs + ;logic afc_reset // AFC reset + ;logic [10 :0] afc_cnt // AFC frequency band adjustment function counter + // counting time adjustment + ;logic [10 :0] afc_ld_cnt // Adjust the counting time of the AFC lock detection + // feature counter + ;logic [3 :0] afc_pres // Adjusting the resolution of the AFC comparator + ;logic [14 :0] afc_ld_tcc // AFC Lock Detection Function Target Cycle Count + ;logic [14 :0] afc_fb_tcc // Target number of cycles for AFC frequency band + // adjustment function + ;logic [0 :0] div_rstn_sel // div rstn select, 1'b0: ext clear, 1'b1:inter pll lock + ;logic [1 :0] test_clk_sel // test clk select, 2'b00:DIV1 clk, 2'b01:DIV2 clk, 2'b10:DIV4 clk, 2'b11:DIV8 clk + ;logic [0 :0] test_clk_oen // test clk output enable, 1'b0:disenable, 1'b1:enable + ;logic [7 :0] dig_clk_sel // digital main clk select, one hot code,bit[0]-->0 degree phase,bit[1]-->45 degree phase.....bit[7]-->315degree phae + ;logic [0 :0] div_sync_en // Frequency Divider Synchronous Clear Enable + ;logic sync_oe; + + + + + +endinterface : pllreg_if + + + diff --git a/tb/pllreg_tb/pllreg_monitor.sv b/tb/pllreg_tb/pllreg_monitor.sv new file mode 100644 index 0000000..078d9a3 --- /dev/null +++ b/tb/pllreg_tb/pllreg_monitor.sv @@ -0,0 +1,85 @@ +class pllreg_monitor; + + + virtual pllreg_if pif; + virtual spi_if wif; + virtual sram_if#(25,32) xif; + + //collect + pllreg_trans act_trans[$]; + + + function new(); + endfunction + extern task collect(); + extern task do_mon(); + +endclass : pllreg_monitor + + +task pllreg_monitor::do_mon(); + + while(1) begin + @(negedge xif.wren); + collect(); + end + +endtask: do_mon + + + + +task pllreg_monitor::collect(); + pllreg_trans tr_temp; + + @(posedge wif.sclk); + @(negedge wif.sclk); + + tr_temp = new(); + tr_temp.ref_sel = pif.ref_sel ; + tr_temp.ref_en = pif.ref_en ; + tr_temp.ref_s2d_en = pif.ref_s2d_en ; + tr_temp.p_cnt = pif.p_cnt ; + tr_temp.pfd_delay = pif.pfd_delay ; + tr_temp.pfd_dff_Set = pif.pfd_dff_Set ; + tr_temp.pfd_dff_4and = pif.pfd_dff_4and ; + tr_temp.spd_div = pif.spd_div ; + tr_temp.spd_pulse_width = pif.spd_pulse_width ; + tr_temp.spd_pulse_sw = pif.spd_pulse_sw ; + tr_temp.cpc_sel = pif.cpc_sel ; + tr_temp.swcp_i = pif.swcp_i ; + tr_temp.sw_ptat_r = pif.sw_ptat_r ; + tr_temp.sw_fll_cpi = pif.sw_fll_cpi ; + tr_temp.sw_fll_delay = pif.sw_fll_delay ; + tr_temp.pfd_sel = pif.pfd_sel ; + tr_temp.spd_sel = pif.spd_sel ; + tr_temp.fll_sel = pif.fll_sel ; + tr_temp.vco_tc = pif.vco_tc ; + tr_temp.vco_tcr = pif.vco_tcr ; + tr_temp.vco_gain_adj = pif.vco_gain_adj ; + tr_temp.vco_gain_adj_r = pif.vco_gain_adj_r ; + tr_temp.vco_cur_adj = pif.vco_cur_adj ; + tr_temp.vco_buff_en = pif.vco_buff_en ; + tr_temp.vco_en = pif.vco_en ; + tr_temp.pll_dpwr_adj = pif.pll_dpwr_adj ; + tr_temp.vco_fb_adj = pif.vco_fb_adj ; + tr_temp.afc_en = pif.afc_en ; + tr_temp.afc_reset = pif.afc_reset ; + tr_temp.afc_shutdown = pif.afc_shutdown ; + tr_temp.flag_out_sel = pif.flag_out_sel ; + tr_temp.afc_det_speed = pif.afc_det_speed ; + tr_temp.afc_cnt = pif.afc_cnt ; + tr_temp.afc_ld_cnt = pif.afc_ld_cnt ; + tr_temp.afc_pres = pif.afc_pres ; + tr_temp.afc_ld_tcc = pif.afc_ld_tcc ; + tr_temp.afc_fb_tcc = pif.afc_fb_tcc ; + tr_temp.div_rstn_sel = pif.div_rstn_sel ; + tr_temp.test_clk_sel = pif.test_clk_sel ; + tr_temp.test_clk_oen = pif.test_clk_oen ; + tr_temp.dig_clk_sel = pif.dig_clk_sel ; + tr_temp.div_sync_en = pif.div_sync_en ; + tr_temp.sync_oe = pif.sync_oe ; + + act_trans.push_back(tr_temp); + +endtask: collect diff --git a/tb/pllreg_tb/pllreg_scb.sv b/tb/pllreg_tb/pllreg_scb.sv new file mode 100644 index 0000000..dc23bc2 --- /dev/null +++ b/tb/pllreg_tb/pllreg_scb.sv @@ -0,0 +1,94 @@ +class pllreg_scoreboard; + + //Vars in intr_check + int isr_error=0; + integer fid; + + function new(); + endfunction; + + //extern task do_check(); + + extern function bit compare( + bit[31:0] spi_exp[$], + bit[31:0] spi_act[$], + pllreg_trans pll_exp[$], + pllreg_trans pll_act[$] + ); + +endclass + +function bit pllreg_scoreboard::compare( + bit[31:0] spi_exp[$], + bit[31:0] spi_act[$], + pllreg_trans pll_exp[$], + pllreg_trans pll_act[$] +); + + bit result=1'b1; + int i=0; + +//$display(dout); + + if(spi_exp.size() != spi_act.size()) begin + result = 1'b0; + //$display("ScoreBoard(ERROR): write & read datanum ARNT'T equal!"); + //$display("Exp spi_data size:%0d",spi_exp.size()); + //$display("Act spi_data size:%0d",spi_act.size()); + $fwrite(fid,"ScoreBoard(ERROR): write & read datanum ARNT'T equal!\t@:%t\n",$realtime); + $fwrite(fid,"Exp spi_data size:%0d\n",spi_exp.size()); + $fwrite(fid,"Act spi_data size:%0d\n",spi_act.size()); + end + + else if(pll_exp.size() != pll_act.size()) begin + result = 1'b0; + //$display("ScoreBoard(ERROR): regmdl & read datanum ARNT'T equal!"); + //$display("Exp pll_trs size:%0d",pll_exp.size()); + //$display("Act pll_trs size:%0d",pll_act.size()); + $fwrite(fid,"ScoreBoard(ERROR): regmdl & read datanum ARNT'T equal\t@:%t!\n",$realtime); + $fwrite(fid,"Exp pll_trs size:%0d\n",pll_exp.size()); + $fwrite(fid,"Act pll_trs size:%0d\n",pll_act.size()); + end + + + else + for(i=0;i0 degree phase,bit[1]-->45 degree phase.....bit[7]-->315degree phae + ;rand bit [0 :0] div_sync_en // Frequency Divider Synchronous Clear Enable + ;rand bit sync_oe // SYNC signal output enable, hign active + ;rand bit clkrx_pdn; // Clock Rx Power down, Ative Low + +constraint cstr { + pll_lock_time >= 0 ; + pll_lock_time <= 3000 ; +} + + function new(); + endfunction + + function bit[42:0] compare(pllreg_trans tr); + bit[42:0] result=43'b0; + if(tr.ref_sel != ref_sel ) result[ 0]=1'b1; + if(tr.ref_en != ref_en ) result[ 1]=1'b1; + if(tr.ref_s2d_en != ref_s2d_en ) result[ 2]=1'b1; + if(tr.p_cnt != p_cnt ) result[ 3]=1'b1; + if(tr.pfd_delay != pfd_delay ) result[ 4]=1'b1; + if(tr.pfd_dff_Set != pfd_dff_Set ) result[ 5]=1'b1; + if(tr.pfd_dff_4and != pfd_dff_4and ) result[ 6]=1'b1; + if(tr.spd_div != spd_div ) result[ 7]=1'b1; + if(tr.spd_pulse_width != spd_pulse_width ) result[ 8]=1'b1; + if(tr.spd_pulse_sw != spd_pulse_sw ) result[ 9]=1'b1; + if(tr.cpc_sel != cpc_sel ) result[10]=1'b1; + if(tr.swcp_i != swcp_i ) result[11]=1'b1; + if(tr.sw_ptat_r != sw_ptat_r ) result[12]=1'b1; + if(tr.sw_fll_cpi != sw_fll_cpi ) result[13]=1'b1; + if(tr.sw_fll_delay != sw_fll_delay ) result[14]=1'b1; + if(tr.pfd_sel != pfd_sel ) result[15]=1'b1; + if(tr.spd_sel != spd_sel ) result[16]=1'b1; + if(tr.fll_sel != fll_sel ) result[17]=1'b1; + if(tr.vco_tc != vco_tc ) result[18]=1'b1; + if(tr.vco_tcr != vco_tcr ) result[19]=1'b1; + if(tr.vco_gain_adj != vco_gain_adj ) result[20]=1'b1; + if(tr.vco_gain_adj_r != vco_gain_adj_r ) result[21]=1'b1; + if(tr.vco_cur_adj != vco_cur_adj ) result[22]=1'b1; + if(tr.vco_buff_en != vco_buff_en ) result[23]=1'b1; + if(tr.vco_en != vco_en ) result[24]=1'b1; + if(tr.pll_dpwr_adj != pll_dpwr_adj ) result[25]=1'b1; + if(tr.vco_fb_adj != vco_fb_adj ) result[26]=1'b1; + if(tr.afc_en != afc_en ) result[27]=1'b1; + if(tr.afc_shutdown != afc_shutdown ) result[28]=1'b1; + if(tr.afc_det_speed != afc_det_speed ) result[29]=1'b1; + if(tr.flag_out_sel != flag_out_sel ) result[30]=1'b1; + if(tr.afc_reset != afc_reset ) result[31]=1'b1; + if(tr.afc_cnt != afc_cnt ) result[32]=1'b1; + if(tr.afc_ld_cnt != afc_ld_cnt ) result[33]=1'b1; + if(tr.afc_pres != afc_pres ) result[34]=1'b1; + if(tr.afc_ld_tcc != afc_ld_tcc ) result[35]=1'b1; + if(tr.afc_fb_tcc != afc_fb_tcc ) result[36]=1'b1; + if(tr.div_rstn_sel != div_rstn_sel ) result[37]=1'b1; + if(tr.test_clk_sel != test_clk_sel ) result[38]=1'b1; + if(tr.test_clk_oen != test_clk_oen ) result[39]=1'b1; + if(tr.dig_clk_sel != dig_clk_sel ) result[40]=1'b1; + if(tr.div_sync_en != div_sync_en ) result[41]=1'b1; + if(tr.sync_oe != sync_oe ) result[42]=1'b1; + return result; + endfunction + + function print(bit[42:0] ctrl,integer fid); + if(ctrl[ 0]) $fwrite(fid," ref_sel =%b\n", ref_sel ); + if(ctrl[ 1]) $fwrite(fid," ref_en =%b\n", ref_en ); + if(ctrl[ 2]) $fwrite(fid," ref_s2d_en =%b\n", ref_s2d_en ); + if(ctrl[ 3]) $fwrite(fid," p_cnt =%b\n", p_cnt ); + if(ctrl[ 4]) $fwrite(fid," pfd_delay =%b\n", pfd_delay ); + if(ctrl[ 5]) $fwrite(fid," pfd_dff_Set =%b\n", pfd_dff_Set ); + if(ctrl[ 6]) $fwrite(fid," pfd_dff_4and =%b\n", pfd_dff_4and ); + if(ctrl[ 7]) $fwrite(fid," spd_div =%b\n", spd_div ); + if(ctrl[ 8]) $fwrite(fid," spd_pulse_width =%b\n", spd_pulse_width); + if(ctrl[ 9]) $fwrite(fid," spd_pulse_sw =%b\n", spd_pulse_sw ); + if(ctrl[10]) $fwrite(fid," cpc_sel =%b\n", cpc_sel ); + if(ctrl[11]) $fwrite(fid," swcp_i =%b\n", swcp_i ); + if(ctrl[12]) $fwrite(fid," sw_ptat_r =%b\n", sw_ptat_r ); + if(ctrl[13]) $fwrite(fid," sw_fll_cpi =%b\n", sw_fll_cpi ); + if(ctrl[14]) $fwrite(fid," sw_fll_delay =%b\n", sw_fll_delay ); + if(ctrl[15]) $fwrite(fid," pfd_sel =%b\n", pfd_sel ); + if(ctrl[16]) $fwrite(fid," spd_sel =%b\n", spd_sel ); + if(ctrl[17]) $fwrite(fid," fll_sel =%b\n", fll_sel ); + if(ctrl[18]) $fwrite(fid," vco_tc =%b\n", vco_tc ); + if(ctrl[19]) $fwrite(fid," vco_tcr =%b\n", vco_tcr ); + if(ctrl[20]) $fwrite(fid," vco_gain_adj =%b\n", vco_gain_adj ); + if(ctrl[21]) $fwrite(fid," vco_gain_adj_r =%b\n", vco_gain_adj_r ); + if(ctrl[22]) $fwrite(fid," vco_cur_adj =%b\n", vco_cur_adj ); + if(ctrl[23]) $fwrite(fid," vco_buff_en =%b\n", vco_buff_en ); + if(ctrl[24]) $fwrite(fid," vco_en =%b\n", vco_en ); + if(ctrl[25]) $fwrite(fid," pll_dpwr_adj =%b\n", pll_dpwr_adj ); + if(ctrl[26]) $fwrite(fid," vco_fb_adj =%b\n", vco_fb_adj ); + if(ctrl[27]) $fwrite(fid," afc_en =%b\n", afc_en ); + if(ctrl[28]) $fwrite(fid," afc_shutdown =%b\n", afc_shutdown ); + if(ctrl[29]) $fwrite(fid," afc_det_speed =%b\n", afc_det_speed ); + if(ctrl[30]) $fwrite(fid," flag_out_sel =%b\n", flag_out_sel ); + if(ctrl[31]) $fwrite(fid," afc_reset =%b\n", afc_reset ); + if(ctrl[32]) $fwrite(fid," afc_cnt =%b\n", afc_cnt ); + if(ctrl[33]) $fwrite(fid," afc_ld_cnt =%b\n", afc_ld_cnt ); + if(ctrl[34]) $fwrite(fid," afc_pres =%b\n", afc_pres ); + if(ctrl[35]) $fwrite(fid," afc_ld_tcc =%b\n", afc_ld_tcc ); + if(ctrl[36]) $fwrite(fid," afc_fb_tcc =%b\n", afc_fb_tcc ); + if(ctrl[37]) $fwrite(fid," div_rstn_sel =%b\n", div_rstn_sel ); + if(ctrl[38]) $fwrite(fid," test_clk_sel =%b\n", test_clk_sel ); + if(ctrl[39]) $fwrite(fid," test_clk_oen =%b\n", test_clk_oen ); + if(ctrl[40]) $fwrite(fid," dig_clk_sel =%b\n", dig_clk_sel ); + if(ctrl[41]) $fwrite(fid," div_sync_en =%b\n", div_sync_en ); + if(ctrl[42]) $fwrite(fid," sync_oe =%b\n", sync_oe ); + endfunction + +endclass : pllreg_trans + + + + + + + + + + + + diff --git a/tb/qumcu/chip/rtl_v00/CHIP_TOP.v b/tb/qumcu/chip/rtl_v00/CHIP_TOP.v new file mode 100644 index 0000000..2b7f6ec --- /dev/null +++ b/tb/qumcu/chip/rtl_v00/CHIP_TOP.v @@ -0,0 +1,295 @@ +//+FHDR-------------------------------------------------------------------------------------------------------- +// Company: +//----------------------------------------------------------------------------------------------------------------- +// File Name : CHIP_TOP.v +// Department : +// Author : pwy +// Author's Tel : +//----------------------------------------------------------------------------------------------------------------- +// Relese History +// Version Date Author Description +// 1.2 2024-04-16 pwy XYZ channel the top-level module +//----------------------------------------------------------------------------------------------------------------- +// Keywords : +// +//----------------------------------------------------------------------------------------------------------------- +// Parameter +// +//----------------------------------------------------------------------------------------------------------------- +// Purpose : +// +//----------------------------------------------------------------------------------------------------------------- +// Target Device: +// Tool versions: +//----------------------------------------------------------------------------------------------------------------- +// Reuse Issues +// Reset Strategy: +// Clock Domains: +// Critical Timing: +// Asynchronous I/F: +// Synthesizable (y/n): +// Other: +//-FHDR------------------------------------------------------------------------------------------------------------ + + + +module CHIP_TOP( + + input sys_clk , + input sys_rst_n , + + output led_test + +); +//================================================================================= +// Parameter declaration +//================================================================================= + + +//================================================================================= +// Signal declaration +//================================================================================= +wire clk = sys_clk ; +wire rst_n = sys_rst_n ; +wire fb_st_in = 2'b10; +reg sync_int ; +initial begin + sync_int = 1'b0; + #10000 sync_int = 1'b1; + #100 sync_int = 1'b0; +end + +//================================================================================= +// Body +//================================================================================= +//--------------------------------------------------------------------------------------------- +// qbmcu instantiation start +//--------------------------------------------------------------------------------------------- +wire [`QBMCU_PC_SIZE-1 :0] ifu_i_pc_rtvec = 32'h0 ; +wire [`QBMCU_PC_SIZE-1 :0] ifu_o_req_pc ; +wire ifu_o_req ; +wire [`QBMCU_INSTR_SIZE-1:0] ifu_rsp_instr ; + +wire dec_o_ilegl ; +wire agu_o_addr_unalgn ; +wire ext_o_send ; +wire ext_o_sendc ; +wire ext_o_codeword ; +wire ext_o_intr ; + +wire [`QBMCU_ADDR_SIZE-1 :0] agu_o_addr ; +wire [`QBMCU_XLEN-1 :0] agu_o_wrdata ; +wire agu_o_wren ; +wire [`QBMCU_XLEN/8-1 :0] agu_o_wrmask ; +wire agu_o_rden ; +wire [`QBMCU_XLEN-1 :0] agu_i_rddata ; +wire [2 :0] qbmcu_o_fsm_st ; + +qbmcu U_qbmcu ( + .clk ( clk ) + ,.rst_n ( rst_n ) + ,.qbmcu_i_start ( sync_int ) + ,.qbmcu_o_fsm_st ( qbmcu_o_fsm_st ) + ,.ifu_i_pc_rtvec ( ifu_i_pc_rtvec ) + ,.ifu_o_req_pc ( ifu_o_req_pc ) + ,.ifu_o_req ( ifu_o_req ) + ,.ifu_rsp_instr ( ifu_rsp_instr ) + ,.dec_o_ilegl ( dec_o_ilegl ) + ,.agu_o_addr ( agu_o_addr ) + ,.agu_o_wrdata ( agu_o_wrdata ) + ,.agu_o_wren ( agu_o_wren ) + ,.agu_o_wrmask ( agu_o_wrmask ) + ,.agu_o_rden ( agu_o_rden ) + ,.agu_i_rddata ( agu_i_rddata ) + ,.agu_o_addr_unalgn ( agu_o_addr_unalgn ) + ,.ext_o_send ( ext_o_send ) + ,.ext_o_sendc ( ext_o_sendc ) + ,.ext_o_codeword ( ext_o_codeword ) + ,.ext_o_intr ( ext_o_intr ) + ); +//--------------------------------------------------------------------------------------------- +// qbmcu instantiation end +//--------------------------------------------------------------------------------------------- + + +//--------------------------------------------------------------------------------------------- +// MCU runtime counter instantiation start +//--------------------------------------------------------------------------------------------- + +defparam qbmcu_runtime.width = 32; +//MCU runtime +wire [31 :0] run_time ; +DW03_updn_ctr qbmcu_runtime ( + .clk ( clk ) // clock input + ,.reset ( rst_n ) // asynchronous reset input (active low) + ,.data ( 32'd0 ) // data used for load operation + ,.up_dn ( 1'b1 ) // up/down control input (0=down, 1-up) + ,.load ( ~sync_int ) // load operation control input (active low) + ,.cen ( |qbmcu_o_fsm_st ) // count enable control input (active high enable) + ,.count ( run_time ) // count value output + ,.tercnt ( ) // terminal count output flag (active high) + ); +//--------------------------------------------------------------------------------------------- +// MCU runtime counter instantiation end +//--------------------------------------------------------------------------------------------- + +//--------------------------------------------------------------------------------------------- +// fetch instructions number counter instantiation start +//--------------------------------------------------------------------------------------------- +defparam instr_num.width = 32; +//Count the number of fetch instructions +wire [31 :0] run_instr_num ; +DW03_updn_ctr instr_num ( + .clk ( clk ) // clock input + ,.reset ( rst_n ) // asynchronous reset input (active low) + ,.data ( 32'd0 ) // data used for load operation + ,.up_dn ( 1'b1 ) // up/down control input (0=down, 1-up) + ,.load ( ~sync_int ) // load operation control input (active low) + ,.cen ( ifu_o_req ) // count enable control input (active high enable) + ,.count ( run_instr_num ) // count value output + ,.tercnt ( ) // terminal count output flag (active high) + ); +//--------------------------------------------------------------------------------------------- +// fetch instructions number counter instantiation end +//--------------------------------------------------------------------------------------------- + + +//--------------------------------------------------------------------------------------------- +// qbmcu_busdecoder instantiation start +//--------------------------------------------------------------------------------------------- + +wire [`QBMCU_ADDR_SIZE-1 :0] dsram_o_rwaddr ; +wire [`QBMCU_XLEN-1 :0] dsram_o_wrdata ; +wire dsram_o_wren ; +wire [`QBMCU_XLEN/8-1 :0] dsram_o_wrmask ; +wire dsram_o_rden ; +wire [`QBMCU_XLEN-1 :0] dsram_i_rddata ; +wire [`QBMCU_ADDR_SIZE-1 :0] preg_o_rwaddr ; +wire [`QBMCU_XLEN-1 :0] preg_o_wrdata ; +wire preg_o_wren ; +wire [`QBMCU_XLEN/8-1 :0] preg_o_wrmask ; +wire preg_o_rden ; +wire [`QBMCU_XLEN-1 :0] preg_i_rddata ; + +qbmcu_busdecoder #( + .S0_BASEADDR ( 32'h0010_0000 ) + ,.S1_BASEADDR ( 32'h0020_0000 ) + )U_qbmcu_busdecoder ( + .wren ( agu_o_wren ) + ,.wrmask ( agu_o_wrmask ) + ,.wrdata ( agu_o_wrdata ) + ,.rwaddr ( agu_o_addr ) + ,.rden ( agu_o_rden ) + ,.rddata ( agu_i_rddata ) + ,.s0_wren ( dsram_o_wren ) + ,.s0_wrmask ( dsram_o_wrmask ) + ,.s0_rwaddr ( dsram_o_rwaddr ) + ,.s0_wrdata ( dsram_o_wrdata ) + ,.s0_rden ( dsram_o_rden ) + ,.s0_rddata ( dsram_i_rddata ) + ,.s1_wren ( preg_o_wren ) + ,.s1_wrmask ( preg_o_wrmask ) + ,.s1_rwaddr ( preg_o_rwaddr ) + ,.s1_wrdata ( preg_o_wrdata ) + ,.s1_rden ( preg_o_rden ) + ,.s1_rddata ( preg_i_rddata ) +); + +//--------------------------------------------------------------------------------------------- +// qbmcu_busdecoder instantiation end +//--------------------------------------------------------------------------------------------- + +//--------------------------------------------------------------------------------------------- +// mcu_regfile instantiation start +//--------------------------------------------------------------------------------------------- + + //MCU and SPI interface for interaction +wire [31 :0] mcu_param [3:0] ; // MCU parameter 0~3 +wire [31 :0] mcu_result [3:0] ; // MCU result 0~3 +//lookup table data ; +wire [31 :0] mcu_cwfr [3:0] ; // Carrier frequency ctrl word 0~3 +wire [15 :0] mcu_gapr [7:0] ; // Carrier phase ctrl word 0~3 +wire [15 :0] mcu_ampr [3:0] ; // Carrier Amplitude 0~3 +wire [15 :0] mcu_baisr [3:0] ; // Carrier Bais 0~3 +//CFG Port +wire [1 :0] mcu_intp_sel ; //2'b00:HBF;2'b01:Nearest-neighbor interpolator; +wire mcu_nco_pha_clr ; +wire [15 :0] mcu_rz_pha ; + +mcu_regfile U_mcu_regfile ( + .clk ( clk ) + ,.rst_n ( rst_n ) + ,.rwaddr ( preg_o_rwaddr ) + ,.wrdata ( preg_o_wrdata ) + ,.wren ( preg_o_wren ) + ,.wrmask ( preg_o_wrmask ) + ,.rden ( preg_o_rden ) + ,.rddata ( preg_i_rddata ) + ,.fb_st_info ( fb_st_in ) + ,.run_time ( run_time ) + ,.instr_num ( run_instr_num ) + ,.mcu_param ( mcu_param ) + ,.mcu_result ( mcu_result ) + ,.mcu_cwfr ( mcu_cwfr ) + ,.mcu_gapr ( mcu_gapr ) + ,.mcu_ampr ( mcu_ampr ) + ,.mcu_baisr ( mcu_baisr ) + ,.mcu_intp_sel ( mcu_intp_sel ) + ,.mcu_nco_pha_clr ( mcu_nco_pha_clr ) + ,.mcu_rz_pha ( mcu_rz_pha ) +); +//--------------------------------------------------------------------------------------------- +// mcu_regfile instantiation end +//--------------------------------------------------------------------------------------------- + +//--------------------------------------------------------------------------------------------- +// U_ITCM instantiation start +//--------------------------------------------------------------------------------------------- + +dpram #( + .DATAWIDTH ( 32 ) + ,.ADDRWIDTH ( 15 ) + ) U_ITCM ( + .PortClk ( clk ) + ,.PortAAddr ( ifu_o_req_pc[`QBMCU_ITCM_ADDR_SIZE-1:0] ) + ,.PortADataIn ( 32'b0 ) + ,.PortAWriteEnable ( 1'b1 ) + ,.PortAChipEnable ( ~ifu_o_req ) + ,.PortAByteWriteEnable ( 4'b0 ) + ,.PortADataOut ( ifu_rsp_instr ) + ,.PortBAddr ( `QBMCU_ITCM_ADDR_SIZE'b0 ) + ,.PortBDataIn ( 32'b0 ) + ,.PortBWriteEnable ( 1'b1 ) + ,.PortBChipEnable ( 1'b0 ) + ,.PortBByteWriteEnable ( 4'b0 ) + ,.PortBDataOut ( ) +); +//--------------------------------------------------------------------------------------------- +// U_ITCM instantiation end +//--------------------------------------------------------------------------------------------- + +//////////////////////////////////////////////////////////////////////////////////////////////////////////// +//DTCM +//////////////////////////////////////////////////////////////////////////////////////////////////////////// + +dpram #( + .DATAWIDTH ( 32 ) + ,.ADDRWIDTH ( 15 ) + ) U_DTCM ( + .PortClk ( clk ) + ,.PortAAddr ( dsram_o_rwaddr[`QBMCU_DTCM_ADDR_SIZE-1:0] ) + ,.PortADataIn ( dsram_o_wrdata ) + ,.PortAWriteEnable ( ~dsram_o_wren ) + ,.PortAChipEnable ( ~(dsram_o_rden | dsram_o_wren) ) + ,.PortAByteWriteEnable ( ~dsram_o_wrmask ) + ,.PortADataOut ( dsram_i_rddata ) + ,.PortBAddr ( `QBMCU_ITCM_ADDR_SIZE'b0 ) + ,.PortBDataIn ( 32'b0 ) + ,.PortBWriteEnable ( 1'b1 ) + ,.PortBChipEnable ( 1'b0 ) + ,.PortBByteWriteEnable ( 4'b0 ) + ,.PortBDataOut ( ) +); + + +endmodule diff --git a/tb/qumcu/chip/rtl_v00/file_list b/tb/qumcu/chip/rtl_v00/file_list new file mode 100644 index 0000000..bb5d6e9 --- /dev/null +++ b/tb/qumcu/chip/rtl_v00/file_list @@ -0,0 +1 @@ +CHIP_TOP.v diff --git a/tb/qumcu/isa/.gitignore b/tb/qumcu/isa/.gitignore new file mode 100644 index 0000000..c93c5ff --- /dev/null +++ b/tb/qumcu/isa/.gitignore @@ -0,0 +1 @@ +rv*-* diff --git a/tb/qumcu/isa/Makefile b/tb/qumcu/isa/Makefile new file mode 100644 index 0000000..7920082 --- /dev/null +++ b/tb/qumcu/isa/Makefile @@ -0,0 +1,143 @@ +#======================================================================= +# Makefile for riscv-tests/isa +#----------------------------------------------------------------------- + +XLEN ?= 32 + +src_dir := . + +ifeq ($(XLEN),64) +include $(src_dir)/rv64ui/Makefrag +include $(src_dir)/rv64uc/Makefrag +include $(src_dir)/rv64um/Makefrag +include $(src_dir)/rv64ua/Makefrag +include $(src_dir)/rv64uf/Makefrag +include $(src_dir)/rv64ud/Makefrag +include $(src_dir)/rv64uzfh/Makefrag +include $(src_dir)/rv64uzba/Makefrag +include $(src_dir)/rv64uzbb/Makefrag +include $(src_dir)/rv64uzbc/Makefrag +include $(src_dir)/rv64uzbs/Makefrag +include $(src_dir)/rv64si/Makefrag +include $(src_dir)/rv64ssvnapot/Makefrag +include $(src_dir)/rv64mi/Makefrag +include $(src_dir)/rv64mzicbo/Makefrag +endif +include $(src_dir)/rv32ui/Makefrag +include $(src_dir)/rv32uc/Makefrag +include $(src_dir)/rv32um/Makefrag +include $(src_dir)/rv32ua/Makefrag +include $(src_dir)/rv32uf/Makefrag +include $(src_dir)/rv32ud/Makefrag +include $(src_dir)/rv32uzfh/Makefrag +include $(src_dir)/rv32uzba/Makefrag +include $(src_dir)/rv32uzbb/Makefrag +include $(src_dir)/rv32uzbc/Makefrag +include $(src_dir)/rv32uzbs/Makefrag +include $(src_dir)/rv32si/Makefrag +include $(src_dir)/rv32mi/Makefrag + +default: all + +#-------------------------------------------------------------------- +# Build rules +#-------------------------------------------------------------------- + +RISCV_PREFIX ?= riscv$(XLEN)-unknown-elf- +RISCV_GCC ?= $(RISCV_PREFIX)gcc +RISCV_GCC_OPTS ?= -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles +RISCV_OBJDUMP ?= $(RISCV_PREFIX)objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.text.init --section=.data +RISCV_OBJCOPY ?= riscv32-unknown-elf-objcopy -O verilog +RISCV_SIM ?= spike + +vpath %.S $(src_dir) + +#------------------------------------------------------------ +# Build assembly tests + +%.dump: % + $(RISCV_OBJDUMP) $< > $@ + $(RISCV_OBJCOPY) $< $<.verilog + sed -i 's/@800/@000/g' $<.verilog + sed -i 's/@00002FB8/@00002000/g' $<.verilog + +%.out: % + $(RISCV_SIM) --isa=rv64gc_zfh_zicboz_svnapot_zicntr_zba_zbb_zbc_zbs --misaligned $< 2> $@ + +%.out32: % + $(RISCV_SIM) --isa=rv32gc_zfh_zicboz_svnapot_zicntr_zba_zbb_zbc_zbs --misaligned $< 2> $@ + +define compile_template + +$$($(1)_p_tests): $(1)-p-%: $(1)/%.S + $$(RISCV_GCC) $(2) $$(RISCV_GCC_OPTS) -I$(src_dir)/../env/p -I$(src_dir)/macros/scalar -T$(src_dir)/../env/p/link.ld $$< -o $$@ +$(1)_tests += $$($(1)_p_tests) + +$$($(1)_v_tests): $(1)-v-%: $(1)/%.S + $$(RISCV_GCC) $(2) $$(RISCV_GCC_OPTS) -DENTROPY=0x$$(shell echo \$$@ | md5sum | cut -c 1-7) -std=gnu99 -O2 -I$(src_dir)/../env/v -I$(src_dir)/macros/scalar -T$(src_dir)/../env/v/link.ld $(src_dir)/../env/v/entry.S $(src_dir)/../env/v/*.c $$< -o $$@ +$(1)_tests += $$($(1)_v_tests) + +$(1)_tests_dump = $$(addsuffix .dump, $$($(1)_tests)) + +$(1): $$($(1)_tests_dump) + +.PHONY: $(1) + +COMPILER_SUPPORTS_$(1) := $$(shell $$(RISCV_GCC) $(2) -c -x c /dev/null -o /dev/null 2> /dev/null; echo $$$$?) + +ifeq ($$(COMPILER_SUPPORTS_$(1)),0) +tests += $$($(1)_tests) +endif + +endef + +$(eval $(call compile_template,rv32ui,-march=rv32g -mabi=ilp32)) +$(eval $(call compile_template,rv32uc,-march=rv32g -mabi=ilp32)) +$(eval $(call compile_template,rv32um,-march=rv32g -mabi=ilp32)) +$(eval $(call compile_template,rv32ua,-march=rv32g -mabi=ilp32)) +$(eval $(call compile_template,rv32uf,-march=rv32g -mabi=ilp32)) +$(eval $(call compile_template,rv32ud,-march=rv32g -mabi=ilp32)) +$(eval $(call compile_template,rv32uzfh,-march=rv32g_zfh -mabi=ilp32)) +$(eval $(call compile_template,rv32uzba,-march=rv32g_zba -mabi=ilp32)) +$(eval $(call compile_template,rv32uzbb,-march=rv32g_zbb -mabi=ilp32)) +$(eval $(call compile_template,rv32uzbc,-march=rv32g_zbc -mabi=ilp32)) +$(eval $(call compile_template,rv32uzbs,-march=rv32g_zbs -mabi=ilp32)) +$(eval $(call compile_template,rv32si,-march=rv32g -mabi=ilp32)) +$(eval $(call compile_template,rv32mi,-march=rv32g -mabi=ilp32)) +ifeq ($(XLEN),64) +$(eval $(call compile_template,rv64ui,-march=rv64g -mabi=lp64)) +$(eval $(call compile_template,rv64uc,-march=rv64g -mabi=lp64)) +$(eval $(call compile_template,rv64um,-march=rv64g -mabi=lp64)) +$(eval $(call compile_template,rv64ua,-march=rv64g -mabi=lp64)) +$(eval $(call compile_template,rv64uf,-march=rv64g -mabi=lp64)) +$(eval $(call compile_template,rv64ud,-march=rv64g -mabi=lp64)) +$(eval $(call compile_template,rv64uzfh,-march=rv64g_zfh -mabi=lp64)) +$(eval $(call compile_template,rv64uzba,-march=rv64g_zba -mabi=lp64)) +$(eval $(call compile_template,rv64uzbb,-march=rv64g_zbb -mabi=lp64)) +$(eval $(call compile_template,rv64uzbc,-march=rv64g_zbc -mabi=lp64)) +$(eval $(call compile_template,rv64uzbs,-march=rv64g_zbs -mabi=lp64)) +$(eval $(call compile_template,rv64mzicbo,-march=rv64g_zicboz -mabi=lp64)) +$(eval $(call compile_template,rv64si,-march=rv64g -mabi=lp64)) +$(eval $(call compile_template,rv64ssvnapot,-march=rv64g -mabi=lp64)) +$(eval $(call compile_template,rv64mi,-march=rv64g -mabi=lp64)) +endif + +tests_dump = $(addsuffix .dump, $(tests)) +tests_hex = $(addsuffix .hex, $(tests)) +tests_out = $(addsuffix .out, $(filter rv64%,$(tests))) +tests32_out = $(addsuffix .out32, $(filter rv32%,$(tests))) + +run: $(tests_out) $(tests32_out) + +junk += $(tests) $(tests_dump) $(tests_hex) $(tests_out) $(tests32_out) + +#------------------------------------------------------------ +# Default + +all: $(tests_dump) + +#------------------------------------------------------------ +# Clean up + +clean: + rm -rf $(junk) diff --git a/tb/qumcu/isa/Makefile(å¦ä¸€ä¸ªå¤ä»¶) b/tb/qumcu/isa/Makefile(å¦ä¸€ä¸ªå¤ä»¶) new file mode 100644 index 0000000..039a51b --- /dev/null +++ b/tb/qumcu/isa/Makefile(å¦ä¸€ä¸ªå¤ä»¶) @@ -0,0 +1,139 @@ +#======================================================================= +# Makefile for riscv-tests/isa +#----------------------------------------------------------------------- + +XLEN ?= 32 + +src_dir := . + +ifeq ($(XLEN),64) +include $(src_dir)/rv64ui/Makefrag +include $(src_dir)/rv64uc/Makefrag +include $(src_dir)/rv64um/Makefrag +include $(src_dir)/rv64ua/Makefrag +include $(src_dir)/rv64uf/Makefrag +include $(src_dir)/rv64ud/Makefrag +include $(src_dir)/rv64uzfh/Makefrag +include $(src_dir)/rv64uzba/Makefrag +include $(src_dir)/rv64uzbb/Makefrag +include $(src_dir)/rv64uzbc/Makefrag +include $(src_dir)/rv64uzbs/Makefrag +include $(src_dir)/rv64si/Makefrag +include $(src_dir)/rv64ssvnapot/Makefrag +include $(src_dir)/rv64mi/Makefrag +include $(src_dir)/rv64mzicbo/Makefrag +endif +include $(src_dir)/rv32ui/Makefrag +include $(src_dir)/rv32uc/Makefrag +include $(src_dir)/rv32um/Makefrag +include $(src_dir)/rv32ua/Makefrag +include $(src_dir)/rv32uf/Makefrag +include $(src_dir)/rv32ud/Makefrag +include $(src_dir)/rv32uzfh/Makefrag +include $(src_dir)/rv32uzba/Makefrag +include $(src_dir)/rv32uzbb/Makefrag +include $(src_dir)/rv32uzbc/Makefrag +include $(src_dir)/rv32uzbs/Makefrag +include $(src_dir)/rv32si/Makefrag +include $(src_dir)/rv32mi/Makefrag + +default: all + +#-------------------------------------------------------------------- +# Build rules +#-------------------------------------------------------------------- + +RISCV_PREFIX ?= riscv$(XLEN)-unknown-elf- +RISCV_GCC ?= $(RISCV_PREFIX)gcc +RISCV_GCC_OPTS ?= -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles +RISCV_OBJDUMP ?= $(RISCV_PREFIX)objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.text.init --section=.data +RISCV_SIM ?= spike + +vpath %.S $(src_dir) + +#------------------------------------------------------------ +# Build assembly tests + +%.dump: % + $(RISCV_OBJDUMP) $< > $@ + +%.out: % + $(RISCV_SIM) --isa=rv64gc_zfh_zicboz_svnapot_zicntr_zba_zbb_zbc_zbs --misaligned $< 2> $@ + +%.out32: % + $(RISCV_SIM) --isa=rv32gc_zfh_zicboz_svnapot_zicntr_zba_zbb_zbc_zbs --misaligned $< 2> $@ + +define compile_template + +$$($(1)_p_tests): $(1)-p-%: $(1)/%.S + $$(RISCV_GCC) $(2) $$(RISCV_GCC_OPTS) -I$(src_dir)/../env/p -I$(src_dir)/macros/scalar -T$(src_dir)/../env/p/link.ld $$< -o $$@ +$(1)_tests += $$($(1)_p_tests) + +$$($(1)_v_tests): $(1)-v-%: $(1)/%.S + $$(RISCV_GCC) $(2) $$(RISCV_GCC_OPTS) -DENTROPY=0x$$(shell echo \$$@ | md5sum | cut -c 1-7) -std=gnu99 -O2 -I$(src_dir)/../env/v -I$(src_dir)/macros/scalar -T$(src_dir)/../env/v/link.ld $(src_dir)/../env/v/entry.S $(src_dir)/../env/v/*.c $$< -o $$@ +$(1)_tests += $$($(1)_v_tests) + +$(1)_tests_dump = $$(addsuffix .dump, $$($(1)_tests)) + +$(1): $$($(1)_tests_dump) + +.PHONY: $(1) + +COMPILER_SUPPORTS_$(1) := $$(shell $$(RISCV_GCC) $(2) -c -x c /dev/null -o /dev/null 2> /dev/null; echo $$$$?) + +ifeq ($$(COMPILER_SUPPORTS_$(1)),0) +tests += $$($(1)_tests) +endif + +endef + +$(eval $(call compile_template,rv32ui,-march=rv32g -mabi=ilp32)) +$(eval $(call compile_template,rv32uc,-march=rv32g -mabi=ilp32)) +$(eval $(call compile_template,rv32um,-march=rv32g -mabi=ilp32)) +$(eval $(call compile_template,rv32ua,-march=rv32g -mabi=ilp32)) +$(eval $(call compile_template,rv32uf,-march=rv32g -mabi=ilp32)) +$(eval $(call compile_template,rv32ud,-march=rv32g -mabi=ilp32)) +$(eval $(call compile_template,rv32uzfh,-march=rv32g_zfh -mabi=ilp32)) +$(eval $(call compile_template,rv32uzba,-march=rv32g_zba -mabi=ilp32)) +$(eval $(call compile_template,rv32uzbb,-march=rv32g_zbb -mabi=ilp32)) +$(eval $(call compile_template,rv32uzbc,-march=rv32g_zbc -mabi=ilp32)) +$(eval $(call compile_template,rv32uzbs,-march=rv32g_zbs -mabi=ilp32)) +$(eval $(call compile_template,rv32si,-march=rv32g -mabi=ilp32)) +$(eval $(call compile_template,rv32mi,-march=rv32g -mabi=ilp32)) +ifeq ($(XLEN),64) +$(eval $(call compile_template,rv64ui,-march=rv64g -mabi=lp64)) +$(eval $(call compile_template,rv64uc,-march=rv64g -mabi=lp64)) +$(eval $(call compile_template,rv64um,-march=rv64g -mabi=lp64)) +$(eval $(call compile_template,rv64ua,-march=rv64g -mabi=lp64)) +$(eval $(call compile_template,rv64uf,-march=rv64g -mabi=lp64)) +$(eval $(call compile_template,rv64ud,-march=rv64g -mabi=lp64)) +$(eval $(call compile_template,rv64uzfh,-march=rv64g_zfh -mabi=lp64)) +$(eval $(call compile_template,rv64uzba,-march=rv64g_zba -mabi=lp64)) +$(eval $(call compile_template,rv64uzbb,-march=rv64g_zbb -mabi=lp64)) +$(eval $(call compile_template,rv64uzbc,-march=rv64g_zbc -mabi=lp64)) +$(eval $(call compile_template,rv64uzbs,-march=rv64g_zbs -mabi=lp64)) +$(eval $(call compile_template,rv64mzicbo,-march=rv64g_zicboz -mabi=lp64)) +$(eval $(call compile_template,rv64si,-march=rv64g -mabi=lp64)) +$(eval $(call compile_template,rv64ssvnapot,-march=rv64g -mabi=lp64)) +$(eval $(call compile_template,rv64mi,-march=rv64g -mabi=lp64)) +endif + +tests_dump = $(addsuffix .dump, $(tests)) +tests_hex = $(addsuffix .hex, $(tests)) +tests_out = $(addsuffix .out, $(filter rv64%,$(tests))) +tests32_out = $(addsuffix .out32, $(filter rv32%,$(tests))) + +run: $(tests_out) $(tests32_out) + +junk += $(tests) $(tests_dump) $(tests_hex) $(tests_out) $(tests32_out) + +#------------------------------------------------------------ +# Default + +all: $(tests_dump) + +#------------------------------------------------------------ +# Clean up + +clean: + rm -rf $(junk) diff --git a/tb/qumcu/isa/case/Add_0x0_test/main.c b/tb/qumcu/isa/case/Add_0x0_test/main.c new file mode 100644 index 0000000..f92eb3f --- /dev/null +++ b/tb/qumcu/isa/case/Add_0x0_test/main.c @@ -0,0 +1,20 @@ +//#include + + +//int main(){ +// printf("\t=====================================\n"); +// printf("\t hello world !!! \n"); +// printf("\t=====================================\n"); +//} + +void main(void){ + +unsigned int a,b; + a=5; + b=3; + //c=a+b; + //d=c+b; +} + + + diff --git a/tb/qumcu/isa/case/Add_0x0_test/main.s b/tb/qumcu/isa/case/Add_0x0_test/main.s new file mode 100644 index 0000000..7f4366d --- /dev/null +++ b/tb/qumcu/isa/case/Add_0x0_test/main.s @@ -0,0 +1,31 @@ +lui x1, 0x0 +lui x2, 0x0 +add x3, x1,x2 +add x4, x1,x2 +add x5, x1,x2 +add x6, x1,x2 +add x7, x1,x2 +add x8, x1,x2 +add x9, x1,x2 +add x10, x1,x2 +add x11, x1,x2 +add x12, x1,x2 +add x13, x1,x2 +add x14, x1,x2 +add x15, x1,x2 +add x16, x1,x2 +add x17, x1,x2 +add x18, x1,x2 +add x19, x1,x2 +add x20, x1,x2 +add x21, x1,x2 +add x22, x1,x2 +add x23, x1,x2 +add x24, x1,x2 +add x25, x1,x2 +add x26, x1,x2 +add x27, x1,x2 +add x28, x1,x2 +add x29, x1,x2 +add x30, x1,x2 +add x31, x1,x2 \ No newline at end of file diff --git a/tb/qumcu/isa/case/Add_0x0_test/user.sv b/tb/qumcu/isa/case/Add_0x0_test/user.sv new file mode 100644 index 0000000..f7e3d4b --- /dev/null +++ b/tb/qumcu/isa/case/Add_0x0_test/user.sv @@ -0,0 +1,110 @@ + +wire ram_clk = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CLK; +wire ram_cs = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CEBA; +wire reg_clk = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.clk; +wire reg_en = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_wen; +reg ram_cs_dly1 ; +reg reg_en_dly1 ; +always @(posedge ram_clk) begin + ram_cs_dly1 <= ~ram_cs; + reg_en_dly1 <= reg_en; +end + + +initial begin + #1ns; + //@(posedge ram_cs_dly1 ); + #5ns; + //while(1)begin + #1ns; + //@(posedge reg_en_dly1 ); + REGFILE_CHECK(6'd1 ,32'h0000_0000); + REGFILE_CHECK(6'd2 ,32'h0000_0000); + REGFILE_CHECK(6'd3 ,32'h0000_0000); + REGFILE_CHECK(6'd4 ,32'h0000_0000); + REGFILE_CHECK(6'd5 ,32'h0000_0000); + REGFILE_CHECK(6'd6 ,32'h0000_0000); + REGFILE_CHECK(6'd7 ,32'h0000_0000); + REGFILE_CHECK(6'd8 ,32'h0000_0000); + REGFILE_CHECK(6'd9 ,32'h0000_0000); + REGFILE_CHECK(6'd10,32'h0000_0000); + REGFILE_CHECK(6'd11,32'h0000_0000); + REGFILE_CHECK(6'd12,32'h0000_0000); + REGFILE_CHECK(6'd13,32'h0000_0000); + REGFILE_CHECK(6'd14,32'h0000_0000); + REGFILE_CHECK(6'd15,32'h0000_0000); + REGFILE_CHECK(6'd16,32'h0000_0000); + REGFILE_CHECK(6'd17,32'h0000_0000); + REGFILE_CHECK(6'd18,32'h0000_0000); + REGFILE_CHECK(6'd19,32'h0000_0000); + REGFILE_CHECK(6'd20,32'h0000_0000); + REGFILE_CHECK(6'd21,32'h0000_0000); + REGFILE_CHECK(6'd22,32'h0000_0000); + REGFILE_CHECK(6'd23,32'h0000_0000); + REGFILE_CHECK(6'd24,32'h0000_0000); + REGFILE_CHECK(6'd25,32'h0000_0000); + REGFILE_CHECK(6'd26,32'h0000_0000); + REGFILE_CHECK(6'd27,32'h0000_0000); + REGFILE_CHECK(6'd28,32'h0000_0000); + REGFILE_CHECK(6'd29,32'h0000_0000); + REGFILE_CHECK(6'd30,32'h0000_0000); + REGFILE_CHECK(6'd31,32'h0000_0000); + #10us; + TEST_PASS; +end + +task DRAM_DATA_CHECK; + input [9:0] addr ; + input [31:0] edata ; + + logic [31:0] ram_data; + + @(posedge ram_cs_dly1 ); + @(posedge ram_clk ); + //$monitor($time, " Simulation time: %t", $time); + if(ram_cs_dly1) begin + ram_data = `TB_DRAM.mem[addr]; + //$display("* RAM_DATA[%x]: %x | EXP_DATA: %x ",addr,ram_data, edata); + if(ram_data !== edata) begin + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,ram_data, edata); + #1us; + TEST_FAIL; + end + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, ram_data, edata); + end + else begin + $display("* DRAM CS is High => Error!!!"); + TEST_FAIL; + end +endtask + +task REGFILE_CHECK; + input [4:0] addr ; + input [31:0] edata ; + + logic [31:0] reg_data; + @(posedge reg_en ); + @(posedge reg_clk); + if(reg_en)begin + reg_data = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_dat; + if(reg_data !== edata) begin + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,reg_data, edata); + #1us; + //TEST_FAIL; + end + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, reg_data, edata); + end + else begin + $display("* REG WR EN is High => Error!!!"); + //TEST_FAIL; + end + +endtask + +initial begin + #100us; + $display("\n----------------------------------------\n"); + $display("\t Timeout Error !!!!\n"); + TEST_FAIL; +end + diff --git a/tb/qumcu/isa/case/Add_0x11111111_test/main.c b/tb/qumcu/isa/case/Add_0x11111111_test/main.c new file mode 100644 index 0000000..f92eb3f --- /dev/null +++ b/tb/qumcu/isa/case/Add_0x11111111_test/main.c @@ -0,0 +1,20 @@ +//#include + + +//int main(){ +// printf("\t=====================================\n"); +// printf("\t hello world !!! \n"); +// printf("\t=====================================\n"); +//} + +void main(void){ + +unsigned int a,b; + a=5; + b=3; + //c=a+b; + //d=c+b; +} + + + diff --git a/tb/qumcu/isa/case/Add_0x11111111_test/main.s b/tb/qumcu/isa/case/Add_0x11111111_test/main.s new file mode 100644 index 0000000..ed5e14c --- /dev/null +++ b/tb/qumcu/isa/case/Add_0x11111111_test/main.s @@ -0,0 +1,33 @@ +addi x2, x0, 0x111 +lui x3, 0x11111 +add x1, x2, x3 +add x2, x1, x1 +add x3, x1,x1 +add x4, x1,x1 +add x5, x1,x1 +add x6, x1,x1 +add x7, x1,x1 +add x8, x1,x1 +add x9, x1,x1 +add x10, x1,x1 +add x11, x1,x1 +add x12, x1,x1 +add x13, x1,x1 +add x14, x1,x1 +add x15, x1,x1 +add x16, x1,x1 +add x17, x1,x1 +add x18, x1,x1 +add x19, x1,x1 +add x20, x1,x1 +add x21, x1,x1 +add x22, x1,x1 +add x23, x1,x1 +add x24, x1,x1 +add x25, x1,x1 +add x26, x1,x1 +add x27, x1,x1 +add x28, x1,x1 +add x29, x1,x1 +add x30, x1,x1 +add x31, x1,x1 \ No newline at end of file diff --git a/tb/qumcu/isa/case/Add_0x11111111_test/user.sv b/tb/qumcu/isa/case/Add_0x11111111_test/user.sv new file mode 100644 index 0000000..bcf32f4 --- /dev/null +++ b/tb/qumcu/isa/case/Add_0x11111111_test/user.sv @@ -0,0 +1,112 @@ + +wire ram_clk = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CLK; +wire ram_cs = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CEBA; +wire reg_clk = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.clk; +wire reg_en = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_wen; +reg ram_cs_dly1 ; +reg reg_en_dly1 ; +always @(posedge ram_clk) begin + ram_cs_dly1 <= ~ram_cs; + reg_en_dly1 <= reg_en; +end + + +initial begin + #1ns; + //@(posedge ram_cs_dly1 ); + #5ns; + //while(1)begin + #1ns; + //@(posedge reg_en_dly1 ); + REGFILE_CHECK(6'd2 ,32'h0000_0111); + REGFILE_CHECK(6'd3 ,32'h1111_1000); + REGFILE_CHECK(6'd1 ,32'h1111_1111); + REGFILE_CHECK(6'd2 ,32'h2222_2222); + REGFILE_CHECK(6'd3 ,32'h2222_2222); + REGFILE_CHECK(6'd4 ,32'h2222_2222); + REGFILE_CHECK(6'd5 ,32'h2222_2222); + REGFILE_CHECK(6'd6 ,32'h2222_2222); + REGFILE_CHECK(6'd7 ,32'h2222_2222); + REGFILE_CHECK(6'd8 ,32'h2222_2222); + REGFILE_CHECK(6'd9 ,32'h2222_2222); + REGFILE_CHECK(6'd10,32'h2222_2222); + REGFILE_CHECK(6'd11,32'h2222_2222); + REGFILE_CHECK(6'd12,32'h2222_2222); + REGFILE_CHECK(6'd13,32'h2222_2222); + REGFILE_CHECK(6'd14,32'h2222_2222); + REGFILE_CHECK(6'd15,32'h2222_2222); + REGFILE_CHECK(6'd16,32'h2222_2222); + REGFILE_CHECK(6'd17,32'h2222_2222); + REGFILE_CHECK(6'd18,32'h2222_2222); + REGFILE_CHECK(6'd19,32'h2222_2222); + REGFILE_CHECK(6'd20,32'h2222_2222); + REGFILE_CHECK(6'd21,32'h2222_2222); + REGFILE_CHECK(6'd22,32'h2222_2222); + REGFILE_CHECK(6'd23,32'h2222_2222); + REGFILE_CHECK(6'd24,32'h2222_2222); + REGFILE_CHECK(6'd25,32'h2222_2222); + REGFILE_CHECK(6'd26,32'h2222_2222); + REGFILE_CHECK(6'd27,32'h2222_2222); + REGFILE_CHECK(6'd28,32'h2222_2222); + REGFILE_CHECK(6'd29,32'h2222_2222); + REGFILE_CHECK(6'd30,32'h2222_2222); + REGFILE_CHECK(6'd31,32'h2222_2222); + #10us; + TEST_PASS; +end + +task DRAM_DATA_CHECK; + input [9:0] addr ; + input [31:0] edata ; + + logic [31:0] ram_data; + + @(posedge ram_cs_dly1 ); + @(posedge ram_clk ); + //$monitor($time, " Simulation time: %t", $time); + if(ram_cs_dly1) begin + ram_data = `TB_DRAM.mem[addr]; + //$display("* RAM_DATA[%x]: %x | EXP_DATA: %x ",addr,ram_data, edata); + if(ram_data !== edata) begin + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,ram_data, edata); + #1us; + TEST_FAIL; + end + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, ram_data, edata); + end + else begin + $display("* DRAM CS is High => Error!!!"); + TEST_FAIL; + end +endtask + +task REGFILE_CHECK; + input [4:0] addr ; + input [31:0] edata ; + + logic [31:0] reg_data; + @(posedge reg_en ); + @(posedge reg_clk); + if(reg_en)begin + reg_data = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_dat; + if(reg_data !== edata) begin + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,reg_data, edata); + #1us; + //TEST_FAIL; + end + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, reg_data, edata); + end + else begin + $display("* REG WR EN is High => Error!!!"); + //TEST_FAIL; + end + +endtask + +initial begin + #100us; + $display("\n----------------------------------------\n"); + $display("\t Timeout Error !!!!\n"); + TEST_FAIL; +end + diff --git a/tb/qumcu/isa/case/Add_0x55555555_test/main.c b/tb/qumcu/isa/case/Add_0x55555555_test/main.c new file mode 100644 index 0000000..f92eb3f --- /dev/null +++ b/tb/qumcu/isa/case/Add_0x55555555_test/main.c @@ -0,0 +1,20 @@ +//#include + + +//int main(){ +// printf("\t=====================================\n"); +// printf("\t hello world !!! \n"); +// printf("\t=====================================\n"); +//} + +void main(void){ + +unsigned int a,b; + a=5; + b=3; + //c=a+b; + //d=c+b; +} + + + diff --git a/tb/qumcu/isa/case/Add_0x55555555_test/main.s b/tb/qumcu/isa/case/Add_0x55555555_test/main.s new file mode 100644 index 0000000..eddf59a --- /dev/null +++ b/tb/qumcu/isa/case/Add_0x55555555_test/main.s @@ -0,0 +1,33 @@ +addi x2, x0, 0x555 +lui x3, 0x55555 +add x1, x2, x3 +add x2, x1, x1 +add x3, x1,x1 +add x4, x1,x1 +add x5, x1,x1 +add x6, x1,x1 +add x7, x1,x1 +add x8, x1,x1 +add x9, x1,x1 +add x10, x1,x1 +add x11, x1,x1 +add x12, x1,x1 +add x13, x1,x1 +add x14, x1,x1 +add x15, x1,x1 +add x16, x1,x1 +add x17, x1,x1 +add x18, x1,x1 +add x19, x1,x1 +add x20, x1,x1 +add x21, x1,x1 +add x22, x1,x1 +add x23, x1,x1 +add x24, x1,x1 +add x25, x1,x1 +add x26, x1,x1 +add x27, x1,x1 +add x28, x1,x1 +add x29, x1,x1 +add x30, x1,x1 +add x31, x1,x1 \ No newline at end of file diff --git a/tb/qumcu/isa/case/Add_0x55555555_test/user.sv b/tb/qumcu/isa/case/Add_0x55555555_test/user.sv new file mode 100644 index 0000000..010b7de --- /dev/null +++ b/tb/qumcu/isa/case/Add_0x55555555_test/user.sv @@ -0,0 +1,112 @@ + +wire ram_clk = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CLK; +wire ram_cs = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CEBA; +wire reg_clk = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.clk; +wire reg_en = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_wen; +reg ram_cs_dly1 ; +reg reg_en_dly1 ; +always @(posedge ram_clk) begin + ram_cs_dly1 <= ~ram_cs; + reg_en_dly1 <= reg_en; +end + + +initial begin + #1ns; + //@(posedge ram_cs_dly1 ); + #5ns; + //while(1)begin + #1ns; + //@(posedge reg_en_dly1 ); + REGFILE_CHECK(6'd2 ,32'h0000_0555); + REGFILE_CHECK(6'd3 ,32'h5555_5000); + REGFILE_CHECK(6'd1 ,32'h5555_5555); + REGFILE_CHECK(6'd2 ,32'haaaa_aaaa); + REGFILE_CHECK(6'd3 ,32'haaaa_aaaa); + REGFILE_CHECK(6'd4 ,32'haaaa_aaaa); + REGFILE_CHECK(6'd5 ,32'haaaa_aaaa); + REGFILE_CHECK(6'd6 ,32'haaaa_aaaa); + REGFILE_CHECK(6'd7 ,32'haaaa_aaaa); + REGFILE_CHECK(6'd8 ,32'haaaa_aaaa); + REGFILE_CHECK(6'd9 ,32'haaaa_aaaa); + REGFILE_CHECK(6'd10,32'haaaa_aaaa); + REGFILE_CHECK(6'd11,32'haaaa_aaaa); + REGFILE_CHECK(6'd12,32'haaaa_aaaa); + REGFILE_CHECK(6'd13,32'haaaa_aaaa); + REGFILE_CHECK(6'd14,32'haaaa_aaaa); + REGFILE_CHECK(6'd15,32'haaaa_aaaa); + REGFILE_CHECK(6'd16,32'haaaa_aaaa); + REGFILE_CHECK(6'd17,32'haaaa_aaaa); + REGFILE_CHECK(6'd18,32'haaaa_aaaa); + REGFILE_CHECK(6'd19,32'haaaa_aaaa); + REGFILE_CHECK(6'd20,32'haaaa_aaaa); + REGFILE_CHECK(6'd21,32'haaaa_aaaa); + REGFILE_CHECK(6'd22,32'haaaa_aaaa); + REGFILE_CHECK(6'd23,32'haaaa_aaaa); + REGFILE_CHECK(6'd24,32'haaaa_aaaa); + REGFILE_CHECK(6'd25,32'haaaa_aaaa); + REGFILE_CHECK(6'd26,32'haaaa_aaaa); + REGFILE_CHECK(6'd27,32'haaaa_aaaa); + REGFILE_CHECK(6'd28,32'haaaa_aaaa); + REGFILE_CHECK(6'd29,32'haaaa_aaaa); + REGFILE_CHECK(6'd30,32'haaaa_aaaa); + REGFILE_CHECK(6'd31,32'haaaa_aaaa); + #10us; + TEST_PASS; +end + +task DRAM_DATA_CHECK; + input [9:0] addr ; + input [31:0] edata ; + + logic [31:0] ram_data; + + @(posedge ram_cs_dly1 ); + @(posedge ram_clk ); + //$monitor($time, " Simulation time: %t", $time); + if(ram_cs_dly1) begin + ram_data = `TB_DRAM.mem[addr]; + //$display("* RAM_DATA[%x]: %x | EXP_DATA: %x ",addr,ram_data, edata); + if(ram_data !== edata) begin + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,ram_data, edata); + #1us; + TEST_FAIL; + end + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, ram_data, edata); + end + else begin + $display("* DRAM CS is High => Error!!!"); + TEST_FAIL; + end +endtask + +task REGFILE_CHECK; + input [4:0] addr ; + input [31:0] edata ; + + logic [31:0] reg_data; + @(posedge reg_en ); + @(posedge reg_clk); + if(reg_en)begin + reg_data = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_dat; + if(reg_data !== edata) begin + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,reg_data, edata); + #1us; + //TEST_FAIL; + end + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, reg_data, edata); + end + else begin + $display("* REG WR EN is High => Error!!!"); + //TEST_FAIL; + end + +endtask + +initial begin + #100us; + $display("\n----------------------------------------\n"); + $display("\t Timeout Error !!!!\n"); + TEST_FAIL; +end + diff --git a/tb/qumcu/isa/case/Add_0x55555_test/main.c b/tb/qumcu/isa/case/Add_0x55555_test/main.c new file mode 100644 index 0000000..f92eb3f --- /dev/null +++ b/tb/qumcu/isa/case/Add_0x55555_test/main.c @@ -0,0 +1,20 @@ +//#include + + +//int main(){ +// printf("\t=====================================\n"); +// printf("\t hello world !!! \n"); +// printf("\t=====================================\n"); +//} + +void main(void){ + +unsigned int a,b; + a=5; + b=3; + //c=a+b; + //d=c+b; +} + + + diff --git a/tb/qumcu/isa/case/Add_0x55555_test/main.s b/tb/qumcu/isa/case/Add_0x55555_test/main.s new file mode 100644 index 0000000..bde4c12 --- /dev/null +++ b/tb/qumcu/isa/case/Add_0x55555_test/main.s @@ -0,0 +1,31 @@ +lui x1, 0x55555 +lui x2, 0x55555 +add x3, x1,x2 +add x4, x1,x2 +add x5, x1,x2 +add x6, x1,x2 +add x7, x1,x2 +add x8, x1,x2 +add x9, x1,x2 +add x10, x1,x2 +add x11, x1,x2 +add x12, x1,x2 +add x13, x1,x2 +add x14, x1,x2 +add x15, x1,x2 +add x16, x1,x2 +add x17, x1,x2 +add x18, x1,x2 +add x19, x1,x2 +add x20, x1,x2 +add x21, x1,x2 +add x22, x1,x2 +add x23, x1,x2 +add x24, x1,x2 +add x25, x1,x2 +add x26, x1,x2 +add x27, x1,x2 +add x28, x1,x2 +add x29, x1,x2 +add x30, x1,x2 +add x31, x1,x2 \ No newline at end of file diff --git a/tb/qumcu/isa/case/Add_0x55555_test/user.sv b/tb/qumcu/isa/case/Add_0x55555_test/user.sv new file mode 100644 index 0000000..f24803e --- /dev/null +++ b/tb/qumcu/isa/case/Add_0x55555_test/user.sv @@ -0,0 +1,110 @@ + +wire ram_clk = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CLK; +wire ram_cs = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CEBA; +wire reg_clk = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.clk; +wire reg_en = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_wen; +reg ram_cs_dly1 ; +reg reg_en_dly1 ; +always @(posedge ram_clk) begin + ram_cs_dly1 <= ~ram_cs; + reg_en_dly1 <= reg_en; +end + + +initial begin + #1ns; + //@(posedge ram_cs_dly1 ); + #5ns; + //while(1)begin + #1ns; + //@(posedge reg_en_dly1 ); + REGFILE_CHECK(6'd1 ,32'h5555_5000); + REGFILE_CHECK(6'd2 ,32'h5555_5000); + REGFILE_CHECK(6'd3 ,32'haaaa_a000); + REGFILE_CHECK(6'd4 ,32'haaaa_a000); + REGFILE_CHECK(6'd5 ,32'haaaa_a000); + REGFILE_CHECK(6'd6 ,32'haaaa_a000); + REGFILE_CHECK(6'd7 ,32'haaaa_a000); + REGFILE_CHECK(6'd8 ,32'haaaa_a000); + REGFILE_CHECK(6'd9 ,32'haaaa_a000); + REGFILE_CHECK(6'd10,32'haaaa_a000); + REGFILE_CHECK(6'd11,32'haaaa_a000); + REGFILE_CHECK(6'd12,32'haaaa_a000); + REGFILE_CHECK(6'd13,32'haaaa_a000); + REGFILE_CHECK(6'd14,32'haaaa_a000); + REGFILE_CHECK(6'd15,32'haaaa_a000); + REGFILE_CHECK(6'd16,32'haaaa_a000); + REGFILE_CHECK(6'd17,32'haaaa_a000); + REGFILE_CHECK(6'd18,32'haaaa_a000); + REGFILE_CHECK(6'd19,32'haaaa_a000); + REGFILE_CHECK(6'd20,32'haaaa_a000); + REGFILE_CHECK(6'd21,32'haaaa_a000); + REGFILE_CHECK(6'd22,32'haaaa_a000); + REGFILE_CHECK(6'd23,32'haaaa_a000); + REGFILE_CHECK(6'd24,32'haaaa_a000); + REGFILE_CHECK(6'd25,32'haaaa_a000); + REGFILE_CHECK(6'd26,32'haaaa_a000); + REGFILE_CHECK(6'd27,32'haaaa_a000); + REGFILE_CHECK(6'd28,32'haaaa_a000); + REGFILE_CHECK(6'd29,32'haaaa_a000); + REGFILE_CHECK(6'd30,32'haaaa_a000); + REGFILE_CHECK(6'd31,32'haaaa_a000); + #10us; + TEST_PASS; +end + +task DRAM_DATA_CHECK; + input [9:0] addr ; + input [31:0] edata ; + + logic [31:0] ram_data; + + @(posedge ram_cs_dly1 ); + @(posedge ram_clk ); + //$monitor($time, " Simulation time: %t", $time); + if(ram_cs_dly1) begin + ram_data = `TB_DRAM.mem[addr]; + //$display("* RAM_DATA[%x]: %x | EXP_DATA: %x ",addr,ram_data, edata); + if(ram_data !== edata) begin + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,ram_data, edata); + #1us; + TEST_FAIL; + end + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, ram_data, edata); + end + else begin + $display("* DRAM CS is High => Error!!!"); + TEST_FAIL; + end +endtask + +task REGFILE_CHECK; + input [4:0] addr ; + input [31:0] edata ; + + logic [31:0] reg_data; + @(posedge reg_en ); + @(posedge reg_clk); + if(reg_en)begin + reg_data = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_dat; + if(reg_data !== edata) begin + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,reg_data, edata); + #1us; + //TEST_FAIL; + end + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, reg_data, edata); + end + else begin + $display("* REG WR EN is High => Error!!!"); + //TEST_FAIL; + end + +endtask + +initial begin + #100us; + $display("\n----------------------------------------\n"); + $display("\t Timeout Error !!!!\n"); + TEST_FAIL; +end + diff --git a/tb/qumcu/isa/case/Add_0xaaaaa_test/main.c b/tb/qumcu/isa/case/Add_0xaaaaa_test/main.c new file mode 100644 index 0000000..f92eb3f --- /dev/null +++ b/tb/qumcu/isa/case/Add_0xaaaaa_test/main.c @@ -0,0 +1,20 @@ +//#include + + +//int main(){ +// printf("\t=====================================\n"); +// printf("\t hello world !!! \n"); +// printf("\t=====================================\n"); +//} + +void main(void){ + +unsigned int a,b; + a=5; + b=3; + //c=a+b; + //d=c+b; +} + + + diff --git a/tb/qumcu/isa/case/Add_0xaaaaa_test/main.s b/tb/qumcu/isa/case/Add_0xaaaaa_test/main.s new file mode 100644 index 0000000..f889368 --- /dev/null +++ b/tb/qumcu/isa/case/Add_0xaaaaa_test/main.s @@ -0,0 +1,31 @@ +lui x1, 0xaaaaa +lui x2, 0xaaaaa +add x3, x1,x2 +add x4, x1,x2 +add x5, x1,x2 +add x6, x1,x2 +add x7, x1,x2 +add x8, x1,x2 +add x9, x1,x2 +add x10, x1,x2 +add x11, x1,x2 +add x12, x1,x2 +add x13, x1,x2 +add x14, x1,x2 +add x15, x1,x2 +add x16, x1,x2 +add x17, x1,x2 +add x18, x1,x2 +add x19, x1,x2 +add x20, x1,x2 +add x21, x1,x2 +add x22, x1,x2 +add x23, x1,x2 +add x24, x1,x2 +add x25, x1,x2 +add x26, x1,x2 +add x27, x1,x2 +add x28, x1,x2 +add x29, x1,x2 +add x30, x1,x2 +add x31, x1,x2 \ No newline at end of file diff --git a/tb/qumcu/isa/case/Add_0xaaaaa_test/user.sv b/tb/qumcu/isa/case/Add_0xaaaaa_test/user.sv new file mode 100644 index 0000000..6620e44 --- /dev/null +++ b/tb/qumcu/isa/case/Add_0xaaaaa_test/user.sv @@ -0,0 +1,110 @@ + +wire ram_clk = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CLK; +wire ram_cs = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CEBA; +wire reg_clk = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.clk; +wire reg_en = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_wen; +reg ram_cs_dly1 ; +reg reg_en_dly1 ; +always @(posedge ram_clk) begin + ram_cs_dly1 <= ~ram_cs; + reg_en_dly1 <= reg_en; +end + + +initial begin + #1ns; + //@(posedge ram_cs_dly1 ); + #5ns; + //while(1)begin + #1ns; + //@(posedge reg_en_dly1 ); + REGFILE_CHECK(6'd1 ,32'haaaa_a000); + REGFILE_CHECK(6'd2 ,32'haaaa_a000); + REGFILE_CHECK(6'd3 ,32'h5555_4000); + REGFILE_CHECK(6'd4 ,32'h5555_4000); + REGFILE_CHECK(6'd5 ,32'h5555_4000); + REGFILE_CHECK(6'd6 ,32'h5555_4000); + REGFILE_CHECK(6'd7 ,32'h5555_4000); + REGFILE_CHECK(6'd8 ,32'h5555_4000); + REGFILE_CHECK(6'd9 ,32'h5555_4000); + REGFILE_CHECK(6'd10,32'h5555_4000); + REGFILE_CHECK(6'd11,32'h5555_4000); + REGFILE_CHECK(6'd12,32'h5555_4000); + REGFILE_CHECK(6'd13,32'h5555_4000); + REGFILE_CHECK(6'd14,32'h5555_4000); + REGFILE_CHECK(6'd15,32'h5555_4000); + REGFILE_CHECK(6'd16,32'h5555_4000); + REGFILE_CHECK(6'd17,32'h5555_4000); + REGFILE_CHECK(6'd18,32'h5555_4000); + REGFILE_CHECK(6'd19,32'h5555_4000); + REGFILE_CHECK(6'd20,32'h5555_4000); + REGFILE_CHECK(6'd21,32'h5555_4000); + REGFILE_CHECK(6'd22,32'h5555_4000); + REGFILE_CHECK(6'd23,32'h5555_4000); + REGFILE_CHECK(6'd24,32'h5555_4000); + REGFILE_CHECK(6'd25,32'h5555_4000); + REGFILE_CHECK(6'd26,32'h5555_4000); + REGFILE_CHECK(6'd27,32'h5555_4000); + REGFILE_CHECK(6'd28,32'h5555_4000); + REGFILE_CHECK(6'd29,32'h5555_4000); + REGFILE_CHECK(6'd30,32'h5555_4000); + REGFILE_CHECK(6'd31,32'h5555_4000); + #10us; + TEST_PASS; +end + +task DRAM_DATA_CHECK; + input [9:0] addr ; + input [31:0] edata ; + + logic [31:0] ram_data; + + @(posedge ram_cs_dly1 ); + @(posedge ram_clk ); + //$monitor($time, " Simulation time: %t", $time); + if(ram_cs_dly1) begin + ram_data = `TB_DRAM.mem[addr]; + //$display("* RAM_DATA[%x]: %x | EXP_DATA: %x ",addr,ram_data, edata); + if(ram_data !== edata) begin + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,ram_data, edata); + #1us; + TEST_FAIL; + end + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, ram_data, edata); + end + else begin + $display("* DRAM CS is High => Error!!!"); + TEST_FAIL; + end +endtask + +task REGFILE_CHECK; + input [4:0] addr ; + input [31:0] edata ; + + logic [31:0] reg_data; + @(posedge reg_en ); + @(posedge reg_clk); + if(reg_en)begin + reg_data = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_dat; + if(reg_data !== edata) begin + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,reg_data, edata); + #1us; + //TEST_FAIL; + end + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, reg_data, edata); + end + else begin + $display("* REG WR EN is High => Error!!!"); + //TEST_FAIL; + end + +endtask + +initial begin + #100us; + $display("\n----------------------------------------\n"); + $display("\t Timeout Error !!!!\n"); + TEST_FAIL; +end + diff --git a/tb/qumcu/isa/case/Add_0xaaaaaaaa_test/main.c b/tb/qumcu/isa/case/Add_0xaaaaaaaa_test/main.c new file mode 100644 index 0000000..f92eb3f --- /dev/null +++ b/tb/qumcu/isa/case/Add_0xaaaaaaaa_test/main.c @@ -0,0 +1,20 @@ +//#include + + +//int main(){ +// printf("\t=====================================\n"); +// printf("\t hello world !!! \n"); +// printf("\t=====================================\n"); +//} + +void main(void){ + +unsigned int a,b; + a=5; + b=3; + //c=a+b; + //d=c+b; +} + + + diff --git a/tb/qumcu/isa/case/Add_0xaaaaaaaa_test/main.s b/tb/qumcu/isa/case/Add_0xaaaaaaaa_test/main.s new file mode 100644 index 0000000..ba83cf2 --- /dev/null +++ b/tb/qumcu/isa/case/Add_0xaaaaaaaa_test/main.s @@ -0,0 +1,34 @@ +addi x2, x0, 0x5aa +lui x3, 0xaaaaa +add x1, x2, x3 +addi x1, x1, 0x500 +add x2, x1, x1 +add x3, x1,x1 +add x4, x1,x1 +add x5, x1,x1 +add x6, x1,x1 +add x7, x1,x1 +add x8, x1,x1 +add x9, x1,x1 +add x10, x1,x1 +add x11, x1,x1 +add x12, x1,x1 +add x13, x1,x1 +add x14, x1,x1 +add x15, x1,x1 +add x16, x1,x1 +add x17, x1,x1 +add x18, x1,x1 +add x19, x1,x1 +add x20, x1,x1 +add x21, x1,x1 +add x22, x1,x1 +add x23, x1,x1 +add x24, x1,x1 +add x25, x1,x1 +add x26, x1,x1 +add x27, x1,x1 +add x28, x1,x1 +add x29, x1,x1 +add x30, x1,x1 +add x31, x1,x1 \ No newline at end of file diff --git a/tb/qumcu/isa/case/Add_0xaaaaaaaa_test/user.sv b/tb/qumcu/isa/case/Add_0xaaaaaaaa_test/user.sv new file mode 100644 index 0000000..d375486 --- /dev/null +++ b/tb/qumcu/isa/case/Add_0xaaaaaaaa_test/user.sv @@ -0,0 +1,113 @@ + +wire ram_clk = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CLK; +wire ram_cs = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CEBA; +wire reg_clk = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.clk; +wire reg_en = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_wen; +reg ram_cs_dly1 ; +reg reg_en_dly1 ; +always @(posedge ram_clk) begin + ram_cs_dly1 <= ~ram_cs; + reg_en_dly1 <= reg_en; +end + + +initial begin + #1ns; + //@(posedge ram_cs_dly1 ); + #5ns; + //while(1)begin + #1ns; + //@(posedge reg_en_dly1 ); + REGFILE_CHECK(6'd2 ,32'h0000_05aa); + REGFILE_CHECK(6'd3 ,32'haaaa_a000); + REGFILE_CHECK(6'd1 ,32'haaaa_a5aa); + REGFILE_CHECK(6'd1 ,32'haaaa_aaaa); + REGFILE_CHECK(6'd2 ,32'h5555_5554); + REGFILE_CHECK(6'd3 ,32'h5555_5554); + REGFILE_CHECK(6'd4 ,32'h5555_5554); + REGFILE_CHECK(6'd5 ,32'h5555_5554); + REGFILE_CHECK(6'd6 ,32'h5555_5554); + REGFILE_CHECK(6'd7 ,32'h5555_5554); + REGFILE_CHECK(6'd8 ,32'h5555_5554); + REGFILE_CHECK(6'd9 ,32'h5555_5554); + REGFILE_CHECK(6'd10,32'h5555_5554); + REGFILE_CHECK(6'd11,32'h5555_5554); + REGFILE_CHECK(6'd12,32'h5555_5554); + REGFILE_CHECK(6'd13,32'h5555_5554); + REGFILE_CHECK(6'd14,32'h5555_5554); + REGFILE_CHECK(6'd15,32'h5555_5554); + REGFILE_CHECK(6'd16,32'h5555_5554); + REGFILE_CHECK(6'd17,32'h5555_5554); + REGFILE_CHECK(6'd18,32'h5555_5554); + REGFILE_CHECK(6'd19,32'h5555_5554); + REGFILE_CHECK(6'd20,32'h5555_5554); + REGFILE_CHECK(6'd21,32'h5555_5554); + REGFILE_CHECK(6'd22,32'h5555_5554); + REGFILE_CHECK(6'd23,32'h5555_5554); + REGFILE_CHECK(6'd24,32'h5555_5554); + REGFILE_CHECK(6'd25,32'h5555_5554); + REGFILE_CHECK(6'd26,32'h5555_5554); + REGFILE_CHECK(6'd27,32'h5555_5554); + REGFILE_CHECK(6'd28,32'h5555_5554); + REGFILE_CHECK(6'd29,32'h5555_5554); + REGFILE_CHECK(6'd30,32'h5555_5554); + REGFILE_CHECK(6'd31,32'h5555_5554); + #10us; + TEST_PASS; +end + +task DRAM_DATA_CHECK; + input [9:0] addr ; + input [31:0] edata ; + + logic [31:0] ram_data; + + @(posedge ram_cs_dly1 ); + @(posedge ram_clk ); + //$monitor($time, " Simulation time: %t", $time); + if(ram_cs_dly1) begin + ram_data = `TB_DRAM.mem[addr]; + //$display("* RAM_DATA[%x]: %x | EXP_DATA: %x ",addr,ram_data, edata); + if(ram_data !== edata) begin + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,ram_data, edata); + #1us; + TEST_FAIL; + end + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, ram_data, edata); + end + else begin + $display("* DRAM CS is High => Error!!!"); + TEST_FAIL; + end +endtask + +task REGFILE_CHECK; + input [4:0] addr ; + input [31:0] edata ; + + logic [31:0] reg_data; + @(posedge reg_en ); + @(posedge reg_clk); + if(reg_en)begin + reg_data = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_dat; + if(reg_data !== edata) begin + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,reg_data, edata); + #1us; + //TEST_FAIL; + end + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, reg_data, edata); + end + else begin + $display("* REG WR EN is High => Error!!!"); + //TEST_FAIL; + end + +endtask + +initial begin + #100us; + $display("\n----------------------------------------\n"); + $display("\t Timeout Error !!!!\n"); + TEST_FAIL; +end + diff --git a/tb/qumcu/isa/case/Add_0xfffff_test/main.c b/tb/qumcu/isa/case/Add_0xfffff_test/main.c new file mode 100644 index 0000000..f92eb3f --- /dev/null +++ b/tb/qumcu/isa/case/Add_0xfffff_test/main.c @@ -0,0 +1,20 @@ +//#include + + +//int main(){ +// printf("\t=====================================\n"); +// printf("\t hello world !!! \n"); +// printf("\t=====================================\n"); +//} + +void main(void){ + +unsigned int a,b; + a=5; + b=3; + //c=a+b; + //d=c+b; +} + + + diff --git a/tb/qumcu/isa/case/Add_0xfffff_test/main.s b/tb/qumcu/isa/case/Add_0xfffff_test/main.s new file mode 100644 index 0000000..e1cac66 --- /dev/null +++ b/tb/qumcu/isa/case/Add_0xfffff_test/main.s @@ -0,0 +1,31 @@ +lui x1, 0xfffff +lui x2, 0xfffff +add x3, x1,x2 +add x4, x1,x2 +add x5, x1,x2 +add x6, x1,x2 +add x7, x1,x2 +add x8, x1,x2 +add x9, x1,x2 +add x10, x1,x2 +add x11, x1,x2 +add x12, x1,x2 +add x13, x1,x2 +add x14, x1,x2 +add x15, x1,x2 +add x16, x1,x2 +add x17, x1,x2 +add x18, x1,x2 +add x19, x1,x2 +add x20, x1,x2 +add x21, x1,x2 +add x22, x1,x2 +add x23, x1,x2 +add x24, x1,x2 +add x25, x1,x2 +add x26, x1,x2 +add x27, x1,x2 +add x28, x1,x2 +add x29, x1,x2 +add x30, x1,x2 +add x31, x1,x2 \ No newline at end of file diff --git a/tb/qumcu/isa/case/Add_0xfffff_test/user.sv b/tb/qumcu/isa/case/Add_0xfffff_test/user.sv new file mode 100644 index 0000000..2f82999 --- /dev/null +++ b/tb/qumcu/isa/case/Add_0xfffff_test/user.sv @@ -0,0 +1,110 @@ + +wire ram_clk = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CLK; +wire ram_cs = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CEBA; +wire reg_clk = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.clk; +wire reg_en = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_wen; +reg ram_cs_dly1 ; +reg reg_en_dly1 ; +always @(posedge ram_clk) begin + ram_cs_dly1 <= ~ram_cs; + reg_en_dly1 <= reg_en; +end + + +initial begin + #1ns; + //@(posedge ram_cs_dly1 ); + #5ns; + //while(1)begin + #1ns; + //@(posedge reg_en_dly1 ); + REGFILE_CHECK(6'd1 ,32'hffff_f000); + REGFILE_CHECK(6'd2 ,32'hffff_f000); + REGFILE_CHECK(6'd3 ,32'hffff_e000); + REGFILE_CHECK(6'd4 ,32'hffff_e000); + REGFILE_CHECK(6'd5 ,32'hffff_e000); + REGFILE_CHECK(6'd6 ,32'hffff_e000); + REGFILE_CHECK(6'd7 ,32'hffff_e000); + REGFILE_CHECK(6'd8 ,32'hffff_e000); + REGFILE_CHECK(6'd9 ,32'hffff_e000); + REGFILE_CHECK(6'd10,32'hffff_e000); + REGFILE_CHECK(6'd11,32'hffff_e000); + REGFILE_CHECK(6'd12,32'hffff_e000); + REGFILE_CHECK(6'd13,32'hffff_e000); + REGFILE_CHECK(6'd14,32'hffff_e000); + REGFILE_CHECK(6'd15,32'hffff_e000); + REGFILE_CHECK(6'd16,32'hffff_e000); + REGFILE_CHECK(6'd17,32'hffff_e000); + REGFILE_CHECK(6'd18,32'hffff_e000); + REGFILE_CHECK(6'd19,32'hffff_e000); + REGFILE_CHECK(6'd20,32'hffff_e000); + REGFILE_CHECK(6'd21,32'hffff_e000); + REGFILE_CHECK(6'd22,32'hffff_e000); + REGFILE_CHECK(6'd23,32'hffff_e000); + REGFILE_CHECK(6'd24,32'hffff_e000); + REGFILE_CHECK(6'd25,32'hffff_e000); + REGFILE_CHECK(6'd26,32'hffff_e000); + REGFILE_CHECK(6'd27,32'hffff_e000); + REGFILE_CHECK(6'd28,32'hffff_e000); + REGFILE_CHECK(6'd29,32'hffff_e000); + REGFILE_CHECK(6'd30,32'hffff_e000); + REGFILE_CHECK(6'd31,32'hffff_e000); + #10us; + TEST_PASS; +end + +task DRAM_DATA_CHECK; + input [9:0] addr ; + input [31:0] edata ; + + logic [31:0] ram_data; + + @(posedge ram_cs_dly1 ); + @(posedge ram_clk ); + //$monitor($time, " Simulation time: %t", $time); + if(ram_cs_dly1) begin + ram_data = `TB_DRAM.mem[addr]; + //$display("* RAM_DATA[%x]: %x | EXP_DATA: %x ",addr,ram_data, edata); + if(ram_data !== edata) begin + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,ram_data, edata); + #1us; + TEST_FAIL; + end + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, ram_data, edata); + end + else begin + $display("* DRAM CS is High => Error!!!"); + TEST_FAIL; + end +endtask + +task REGFILE_CHECK; + input [4:0] addr ; + input [31:0] edata ; + + logic [31:0] reg_data; + @(posedge reg_en ); + @(posedge reg_clk); + if(reg_en)begin + reg_data = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_dat; + if(reg_data !== edata) begin + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,reg_data, edata); + #1us; + //TEST_FAIL; + end + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, reg_data, edata); + end + else begin + $display("* REG WR EN is High => Error!!!"); + //TEST_FAIL; + end + +endtask + +initial begin + #100us; + $display("\n----------------------------------------\n"); + $display("\t Timeout Error !!!!\n"); + TEST_FAIL; +end + diff --git a/tb/qumcu/isa/case/Add_0xffffffff_test/main.c b/tb/qumcu/isa/case/Add_0xffffffff_test/main.c new file mode 100644 index 0000000..f92eb3f --- /dev/null +++ b/tb/qumcu/isa/case/Add_0xffffffff_test/main.c @@ -0,0 +1,20 @@ +//#include + + +//int main(){ +// printf("\t=====================================\n"); +// printf("\t hello world !!! \n"); +// printf("\t=====================================\n"); +//} + +void main(void){ + +unsigned int a,b; + a=5; + b=3; + //c=a+b; + //d=c+b; +} + + + diff --git a/tb/qumcu/isa/case/Add_0xffffffff_test/main.s b/tb/qumcu/isa/case/Add_0xffffffff_test/main.s new file mode 100644 index 0000000..ed5e14c --- /dev/null +++ b/tb/qumcu/isa/case/Add_0xffffffff_test/main.s @@ -0,0 +1,33 @@ +addi x2, x0, 0x111 +lui x3, 0x11111 +add x1, x2, x3 +add x2, x1, x1 +add x3, x1,x1 +add x4, x1,x1 +add x5, x1,x1 +add x6, x1,x1 +add x7, x1,x1 +add x8, x1,x1 +add x9, x1,x1 +add x10, x1,x1 +add x11, x1,x1 +add x12, x1,x1 +add x13, x1,x1 +add x14, x1,x1 +add x15, x1,x1 +add x16, x1,x1 +add x17, x1,x1 +add x18, x1,x1 +add x19, x1,x1 +add x20, x1,x1 +add x21, x1,x1 +add x22, x1,x1 +add x23, x1,x1 +add x24, x1,x1 +add x25, x1,x1 +add x26, x1,x1 +add x27, x1,x1 +add x28, x1,x1 +add x29, x1,x1 +add x30, x1,x1 +add x31, x1,x1 \ No newline at end of file diff --git a/tb/qumcu/isa/case/Add_0xffffffff_test/user.sv b/tb/qumcu/isa/case/Add_0xffffffff_test/user.sv new file mode 100644 index 0000000..4e48fa2 --- /dev/null +++ b/tb/qumcu/isa/case/Add_0xffffffff_test/user.sv @@ -0,0 +1,114 @@ + +wire ram_clk = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CLK; +wire ram_cs = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CEBA; +wire reg_clk = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.clk; +wire reg_en = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_wen; +reg ram_cs_dly1 ; +reg reg_en_dly1 ; +always @(posedge ram_clk) begin + ram_cs_dly1 <= ~ram_cs; + reg_en_dly1 <= reg_en; +end + + +initial begin + #1ns; + //@(posedge ram_cs_dly1 ); + #5ns; + //while(1)begin + #1ns; + //@(posedge reg_en_dly1 ); + REGFILE_CHECK(6'd2 ,32'h0000_07ff); + REGFILE_CHECK(6'd3 ,32'hffff_f000); + REGFILE_CHECK(6'd1 ,32'hffff_f7ff); + REGFILE_CHECK(6'd1 ,32'hffff_fffe); + REGFILE_CHECK(6'd1 ,32'hffff_ffff); + REGFILE_CHECK(6'd2 ,32'hffff_fffe); + REGFILE_CHECK(6'd3 ,32'hffff_fffe); + REGFILE_CHECK(6'd4 ,32'hffff_fffe); + REGFILE_CHECK(6'd5 ,32'hffff_fffe); + REGFILE_CHECK(6'd6 ,32'hffff_fffe); + REGFILE_CHECK(6'd7 ,32'hffff_fffe); + REGFILE_CHECK(6'd8 ,32'hffff_fffe); + REGFILE_CHECK(6'd9 ,32'hffff_fffe); + REGFILE_CHECK(6'd10,32'hffff_fffe); + REGFILE_CHECK(6'd11,32'hffff_fffe); + REGFILE_CHECK(6'd12,32'hffff_fffe); + REGFILE_CHECK(6'd13,32'hffff_fffe); + REGFILE_CHECK(6'd14,32'hffff_fffe); + REGFILE_CHECK(6'd15,32'hffff_fffe); + REGFILE_CHECK(6'd16,32'hffff_fffe); + REGFILE_CHECK(6'd17,32'hffff_fffe); + REGFILE_CHECK(6'd18,32'hffff_fffe); + REGFILE_CHECK(6'd19,32'hffff_fffe); + REGFILE_CHECK(6'd20,32'hffff_fffe); + REGFILE_CHECK(6'd21,32'hffff_fffe); + REGFILE_CHECK(6'd22,32'hffff_fffe); + REGFILE_CHECK(6'd23,32'hffff_fffe); + REGFILE_CHECK(6'd24,32'hffff_fffe); + REGFILE_CHECK(6'd25,32'hffff_fffe); + REGFILE_CHECK(6'd26,32'hffff_fffe); + REGFILE_CHECK(6'd27,32'hffff_fffe); + REGFILE_CHECK(6'd28,32'hffff_fffe); + REGFILE_CHECK(6'd29,32'hffff_fffe); + REGFILE_CHECK(6'd30,32'hffff_fffe); + REGFILE_CHECK(6'd31,32'hffff_fffe); + #10us; + TEST_PASS; +end + +task DRAM_DATA_CHECK; + input [9:0] addr ; + input [31:0] edata ; + + logic [31:0] ram_data; + + @(posedge ram_cs_dly1 ); + @(posedge ram_clk ); + //$monitor($time, " Simulation time: %t", $time); + if(ram_cs_dly1) begin + ram_data = `TB_DRAM.mem[addr]; + //$display("* RAM_DATA[%x]: %x | EXP_DATA: %x ",addr,ram_data, edata); + if(ram_data !== edata) begin + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,ram_data, edata); + #1us; + TEST_FAIL; + end + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, ram_data, edata); + end + else begin + $display("* DRAM CS is High => Error!!!"); + TEST_FAIL; + end +endtask + +task REGFILE_CHECK; + input [4:0] addr ; + input [31:0] edata ; + + logic [31:0] reg_data; + @(posedge reg_en ); + @(posedge reg_clk); + if(reg_en)begin + reg_data = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_dat; + if(reg_data !== edata) begin + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,reg_data, edata); + #1us; + //TEST_FAIL; + end + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, reg_data, edata); + end + else begin + $display("* REG WR EN is High => Error!!!"); + //TEST_FAIL; + end + +endtask + +initial begin + #100us; + $display("\n----------------------------------------\n"); + $display("\t Timeout Error !!!!\n"); + TEST_FAIL; +end + diff --git a/tb/qumcu/isa/case/Addi_-2048_test/main.c b/tb/qumcu/isa/case/Addi_-2048_test/main.c new file mode 100644 index 0000000..f92eb3f --- /dev/null +++ b/tb/qumcu/isa/case/Addi_-2048_test/main.c @@ -0,0 +1,20 @@ +//#include + + +//int main(){ +// printf("\t=====================================\n"); +// printf("\t hello world !!! \n"); +// printf("\t=====================================\n"); +//} + +void main(void){ + +unsigned int a,b; + a=5; + b=3; + //c=a+b; + //d=c+b; +} + + + diff --git a/tb/qumcu/isa/case/Addi_-2048_test/main.s b/tb/qumcu/isa/case/Addi_-2048_test/main.s new file mode 100644 index 0000000..e49fd4a --- /dev/null +++ b/tb/qumcu/isa/case/Addi_-2048_test/main.s @@ -0,0 +1,31 @@ +addi x1, x0, -0x800 +addi x2, x0, -0x800 +addi x3, x0, -0x800 +addi x4, x0, -0x800 +addi x5, x0, -0x800 +addi x6, x0, -0x800 +addi x7, x0, -0x800 +addi x8, x0, -0x800 +addi x9, x0, -0x800 +addi x10, x0, -0x800 +addi x11, x0, -0x800 +addi x12, x0, -0x800 +addi x13, x0, -0x800 +addi x14, x0, -0x800 +addi x15, x0, -0x800 +addi x16, x0, -0x800 +addi x17, x0, -0x800 +addi x18, x0, -0x800 +addi x19, x0, -0x800 +addi x20, x0, -0x800 +addi x21, x0, -0x800 +addi x22, x0, -0x800 +addi x23, x0, -0x800 +addi x24, x0, -0x800 +addi x25, x0, -0x800 +addi x26, x0, -0x800 +addi x27, x0, -0x800 +addi x28, x0, -0x800 +addi x29, x0, -0x800 +addi x30, x0, -0x800 +addi x31, x0, -0x800 \ No newline at end of file diff --git a/tb/qumcu/isa/case/Addi_-2048_test/user.sv b/tb/qumcu/isa/case/Addi_-2048_test/user.sv new file mode 100644 index 0000000..b52840a --- /dev/null +++ b/tb/qumcu/isa/case/Addi_-2048_test/user.sv @@ -0,0 +1,110 @@ + +wire ram_clk = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CLK; +wire ram_cs = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CEBA; +wire reg_clk = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.clk; +wire reg_en = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_wen; +reg ram_cs_dly1 ; +reg reg_en_dly1 ; +always @(posedge ram_clk) begin + ram_cs_dly1 <= ~ram_cs; + reg_en_dly1 <= reg_en; +end + + +initial begin + #1ns; + //@(posedge ram_cs_dly1 ); + #5ns; + //while(1)begin + #1ns; + //@(posedge reg_en_dly1 ); + REGFILE_CHECK(6'd1 ,32'hffff_f800); + REGFILE_CHECK(6'd2 ,32'hffff_f800); + REGFILE_CHECK(6'd3 ,32'hffff_f800); + REGFILE_CHECK(6'd4 ,32'hffff_f800); + REGFILE_CHECK(6'd5 ,32'hffff_f800); + REGFILE_CHECK(6'd6 ,32'hffff_f800); + REGFILE_CHECK(6'd7 ,32'hffff_f800); + REGFILE_CHECK(6'd8 ,32'hffff_f800); + REGFILE_CHECK(6'd9 ,32'hffff_f800); + REGFILE_CHECK(6'd10,32'hffff_f800); + REGFILE_CHECK(6'd11,32'hffff_f800); + REGFILE_CHECK(6'd12,32'hffff_f800); + REGFILE_CHECK(6'd13,32'hffff_f800); + REGFILE_CHECK(6'd14,32'hffff_f800); + REGFILE_CHECK(6'd15,32'hffff_f800); + REGFILE_CHECK(6'd16,32'hffff_f800); + REGFILE_CHECK(6'd17,32'hffff_f800); + REGFILE_CHECK(6'd18,32'hffff_f800); + REGFILE_CHECK(6'd19,32'hffff_f800); + REGFILE_CHECK(6'd20,32'hffff_f800); + REGFILE_CHECK(6'd21,32'hffff_f800); + REGFILE_CHECK(6'd22,32'hffff_f800); + REGFILE_CHECK(6'd23,32'hffff_f800); + REGFILE_CHECK(6'd24,32'hffff_f800); + REGFILE_CHECK(6'd25,32'hffff_f800); + REGFILE_CHECK(6'd26,32'hffff_f800); + REGFILE_CHECK(6'd27,32'hffff_f800); + REGFILE_CHECK(6'd28,32'hffff_f800); + REGFILE_CHECK(6'd29,32'hffff_f800); + REGFILE_CHECK(6'd30,32'hffff_f800); + REGFILE_CHECK(6'd31,32'hffff_f800); + #10us; + TEST_PASS; +end + +task DRAM_DATA_CHECK; + input [9:0] addr ; + input [31:0] edata ; + + logic [31:0] ram_data; + + @(posedge ram_cs_dly1 ); + @(posedge ram_clk ); + //$monitor($time, " Simulation time: %t", $time); + if(ram_cs_dly1) begin + ram_data = `TB_DRAM.mem[addr]; + //$display("* RAM_DATA[%x]: %x | EXP_DATA: %x ",addr,ram_data, edata); + if(ram_data !== edata) begin + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,ram_data, edata); + #1us; + TEST_FAIL; + end + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, ram_data, edata); + end + else begin + $display("* DRAM CS is High => Error!!!"); + TEST_FAIL; + end +endtask + +task REGFILE_CHECK; + input [4:0] addr ; + input [31:0] edata ; + + logic [31:0] reg_data; + @(posedge reg_en ); + @(posedge reg_clk); + if(reg_en)begin + reg_data = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_dat; + if(reg_data !== edata) begin + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,reg_data, edata); + #1us; + //TEST_FAIL; + end + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, reg_data, edata); + end + else begin + $display("* REG WR EN is High => Error!!!"); + //TEST_FAIL; + end + +endtask + +initial begin + #100us; + $display("\n----------------------------------------\n"); + $display("\t Timeout Error !!!!\n"); + TEST_FAIL; +end + diff --git a/tb/qumcu/isa/case/Addi_0x0_test/main.c b/tb/qumcu/isa/case/Addi_0x0_test/main.c new file mode 100644 index 0000000..f92eb3f --- /dev/null +++ b/tb/qumcu/isa/case/Addi_0x0_test/main.c @@ -0,0 +1,20 @@ +//#include + + +//int main(){ +// printf("\t=====================================\n"); +// printf("\t hello world !!! \n"); +// printf("\t=====================================\n"); +//} + +void main(void){ + +unsigned int a,b; + a=5; + b=3; + //c=a+b; + //d=c+b; +} + + + diff --git a/tb/qumcu/isa/case/Addi_0x0_test/main.s b/tb/qumcu/isa/case/Addi_0x0_test/main.s new file mode 100644 index 0000000..b9c7b94 --- /dev/null +++ b/tb/qumcu/isa/case/Addi_0x0_test/main.s @@ -0,0 +1,31 @@ +addi x1, x0, 0x0 +addi x2, x0, 0x0 +addi x3, x0, 0x0 +addi x4, x0, 0x0 +addi x5, x0, 0x0 +addi x6, x0, 0x0 +addi x7, x0, 0x0 +addi x8, x0, 0x0 +addi x9, x0, 0x0 +addi x10, x0, 0x0 +addi x11, x0, 0x0 +addi x12, x0, 0x0 +addi x13, x0, 0x0 +addi x14, x0, 0x0 +addi x15, x0, 0x0 +addi x16, x0, 0x0 +addi x17, x0, 0x0 +addi x18, x0, 0x0 +addi x19, x0, 0x0 +addi x20, x0, 0x0 +addi x21, x0, 0x0 +addi x22, x0, 0x0 +addi x23, x0, 0x0 +addi x24, x0, 0x0 +addi x25, x0, 0x0 +addi x26, x0, 0x0 +addi x27, x0, 0x0 +addi x28, x0, 0x0 +addi x29, x0, 0x0 +addi x30, x0, 0x0 +addi x31, x0, 0x0 \ No newline at end of file diff --git a/tb/qumcu/isa/case/Addi_0x0_test/user.sv b/tb/qumcu/isa/case/Addi_0x0_test/user.sv new file mode 100644 index 0000000..7824b08 --- /dev/null +++ b/tb/qumcu/isa/case/Addi_0x0_test/user.sv @@ -0,0 +1,110 @@ + +wire ram_clk = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CLK; +wire ram_cs = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CEBA; +wire reg_clk = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.clk; +wire reg_en = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_wen; +reg ram_cs_dly1 ; +reg reg_en_dly1 ; +always @(posedge ram_clk) begin + ram_cs_dly1 <= ~ram_cs; + reg_en_dly1 <= reg_en; +end + + +initial begin + #1ns; + //@(posedge ram_cs_dly1 ); + #5ns; + //while(1)begin + #1ns; + //@(posedge reg_en_dly1 ); + REGFILE_CHECK(6'd1 ,32'h0000_0000); + REGFILE_CHECK(6'd2 ,32'h0000_0000); + REGFILE_CHECK(6'd3 ,32'h0000_0000); + REGFILE_CHECK(6'd4 ,32'h0000_0000); + REGFILE_CHECK(6'd5 ,32'h0000_0000); + REGFILE_CHECK(6'd6 ,32'h0000_0000); + REGFILE_CHECK(6'd7 ,32'h0000_0000); + REGFILE_CHECK(6'd8 ,32'h0000_0000); + REGFILE_CHECK(6'd9 ,32'h0000_0000); + REGFILE_CHECK(6'd10,32'h0000_0000); + REGFILE_CHECK(6'd11,32'h0000_0000); + REGFILE_CHECK(6'd12,32'h0000_0000); + REGFILE_CHECK(6'd13,32'h0000_0000); + REGFILE_CHECK(6'd14,32'h0000_0000); + REGFILE_CHECK(6'd15,32'h0000_0000); + REGFILE_CHECK(6'd16,32'h0000_0000); + REGFILE_CHECK(6'd17,32'h0000_0000); + REGFILE_CHECK(6'd18,32'h0000_0000); + REGFILE_CHECK(6'd19,32'h0000_0000); + REGFILE_CHECK(6'd20,32'h0000_0000); + REGFILE_CHECK(6'd21,32'h0000_0000); + REGFILE_CHECK(6'd22,32'h0000_0000); + REGFILE_CHECK(6'd23,32'h0000_0000); + REGFILE_CHECK(6'd24,32'h0000_0000); + REGFILE_CHECK(6'd25,32'h0000_0000); + REGFILE_CHECK(6'd26,32'h0000_0000); + REGFILE_CHECK(6'd27,32'h0000_0000); + REGFILE_CHECK(6'd28,32'h0000_0000); + REGFILE_CHECK(6'd29,32'h0000_0000); + REGFILE_CHECK(6'd30,32'h0000_0000); + REGFILE_CHECK(6'd31,32'h0000_0000); + #10us; + TEST_PASS; +end + +task DRAM_DATA_CHECK; + input [9:0] addr ; + input [31:0] edata ; + + logic [31:0] ram_data; + + @(posedge ram_cs_dly1 ); + @(posedge ram_clk ); + //$monitor($time, " Simulation time: %t", $time); + if(ram_cs_dly1) begin + ram_data = `TB_DRAM.mem[addr]; + //$display("* RAM_DATA[%x]: %x | EXP_DATA: %x ",addr,ram_data, edata); + if(ram_data !== edata) begin + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,ram_data, edata); + #1us; + TEST_FAIL; + end + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, ram_data, edata); + end + else begin + $display("* DRAM CS is High => Error!!!"); + TEST_FAIL; + end +endtask + +task REGFILE_CHECK; + input [4:0] addr ; + input [31:0] edata ; + + logic [31:0] reg_data; + @(posedge reg_en ); + @(posedge reg_clk); + if(reg_en)begin + reg_data = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_dat; + if(reg_data !== edata) begin + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,reg_data, edata); + #1us; + //TEST_FAIL; + end + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, reg_data, edata); + end + else begin + $display("* REG WR EN is High => Error!!!"); + //TEST_FAIL; + end + +endtask + +initial begin + #100us; + $display("\n----------------------------------------\n"); + $display("\t Timeout Error !!!!\n"); + TEST_FAIL; +end + diff --git a/tb/qumcu/isa/case/Addi_0x11111+111_test/main.c b/tb/qumcu/isa/case/Addi_0x11111+111_test/main.c new file mode 100644 index 0000000..f92eb3f --- /dev/null +++ b/tb/qumcu/isa/case/Addi_0x11111+111_test/main.c @@ -0,0 +1,20 @@ +//#include + + +//int main(){ +// printf("\t=====================================\n"); +// printf("\t hello world !!! \n"); +// printf("\t=====================================\n"); +//} + +void main(void){ + +unsigned int a,b; + a=5; + b=3; + //c=a+b; + //d=c+b; +} + + + diff --git a/tb/qumcu/isa/case/Addi_0x11111+111_test/main.s b/tb/qumcu/isa/case/Addi_0x11111+111_test/main.s new file mode 100644 index 0000000..607388d --- /dev/null +++ b/tb/qumcu/isa/case/Addi_0x11111+111_test/main.s @@ -0,0 +1,32 @@ +lui x31, 0xfffff +addi x1, x31, 0x7ff +addi x2, x31, 0x7ff +addi x3, x31, 0x7ff +addi x4, x31, 0x7ff +addi x5, x31, 0x7ff +addi x6, x31, 0x7ff +addi x7, x31, 0x7ff +addi x8, x31, 0x7ff +addi x9, x31, 0x7ff +addi x10, x31, 0x7ff +addi x11, x31, 0x7ff +addi x12, x31, 0x7ff +addi x13, x31, 0x7ff +addi x14, x31, 0x7ff +addi x15, x31, 0x7ff +addi x16, x31, 0x7ff +addi x17, x31, 0x7ff +addi x18, x31, 0x7ff +addi x19, x31, 0x7ff +addi x20, x31, 0x7ff +addi x21, x31, 0x7ff +addi x22, x31, 0x7ff +addi x23, x31, 0x7ff +addi x24, x31, 0x7ff +addi x25, x31, 0x7ff +addi x26, x31, 0x7ff +addi x27, x31, 0x7ff +addi x28, x31, 0x7ff +addi x29, x31, 0x7ff +addi x30, x31, 0x7ff +addi x31, x31, 0x7ff \ No newline at end of file diff --git a/tb/qumcu/isa/case/Addi_0x11111+111_test/user.sv b/tb/qumcu/isa/case/Addi_0x11111+111_test/user.sv new file mode 100644 index 0000000..861b024 --- /dev/null +++ b/tb/qumcu/isa/case/Addi_0x11111+111_test/user.sv @@ -0,0 +1,111 @@ + +wire ram_clk = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CLK; +wire ram_cs = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CEBA; +wire reg_clk = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.clk; +wire reg_en = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_wen; +reg ram_cs_dly1 ; +reg reg_en_dly1 ; +always @(posedge ram_clk) begin + ram_cs_dly1 <= ~ram_cs; + reg_en_dly1 <= reg_en; +end + + +initial begin + #1ns; + //@(posedge ram_cs_dly1 ); + #5ns; + //while(1)begin + #1ns; + //@(posedge reg_en_dly1 ); + REGFILE_CHECK(6'd31,32'hffff_f000); + REGFILE_CHECK(6'd1 ,32'hffff_f7ff); + REGFILE_CHECK(6'd2 ,32'hffff_f7ff); + REGFILE_CHECK(6'd3 ,32'hffff_f7ff); + REGFILE_CHECK(6'd4 ,32'hffff_f7ff); + REGFILE_CHECK(6'd5 ,32'hffff_f7ff); + REGFILE_CHECK(6'd6 ,32'hffff_f7ff); + REGFILE_CHECK(6'd7 ,32'hffff_f7ff); + REGFILE_CHECK(6'd8 ,32'hffff_f7ff); + REGFILE_CHECK(6'd9 ,32'hffff_f7ff); + REGFILE_CHECK(6'd10,32'hffff_f7ff); + REGFILE_CHECK(6'd11,32'hffff_f7ff); + REGFILE_CHECK(6'd12,32'hffff_f7ff); + REGFILE_CHECK(6'd13,32'hffff_f7ff); + REGFILE_CHECK(6'd14,32'hffff_f7ff); + REGFILE_CHECK(6'd15,32'hffff_f7ff); + REGFILE_CHECK(6'd16,32'hffff_f7ff); + REGFILE_CHECK(6'd17,32'hffff_f7ff); + REGFILE_CHECK(6'd18,32'hffff_f7ff); + REGFILE_CHECK(6'd19,32'hffff_f7ff); + REGFILE_CHECK(6'd20,32'hffff_f7ff); + REGFILE_CHECK(6'd21,32'hffff_f7ff); + REGFILE_CHECK(6'd22,32'hffff_f7ff); + REGFILE_CHECK(6'd23,32'hffff_f7ff); + REGFILE_CHECK(6'd24,32'hffff_f7ff); + REGFILE_CHECK(6'd25,32'hffff_f7ff); + REGFILE_CHECK(6'd26,32'hffff_f7ff); + REGFILE_CHECK(6'd27,32'hffff_f7ff); + REGFILE_CHECK(6'd28,32'hffff_f7ff); + REGFILE_CHECK(6'd29,32'hffff_f7ff); + REGFILE_CHECK(6'd30,32'hffff_f7ff); + REGFILE_CHECK(6'd31,32'hffff_f7ff); + #10us; + TEST_PASS; +end + +task DRAM_DATA_CHECK; + input [9:0] addr ; + input [31:0] edata ; + + logic [31:0] ram_data; + + @(posedge ram_cs_dly1 ); + @(posedge ram_clk ); + //$monitor($time, " Simulation time: %t", $time); + if(ram_cs_dly1) begin + ram_data = `TB_DRAM.mem[addr]; + //$display("* RAM_DATA[%x]: %x | EXP_DATA: %x ",addr,ram_data, edata); + if(ram_data !== edata) begin + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,ram_data, edata); + #1us; + TEST_FAIL; + end + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, ram_data, edata); + end + else begin + $display("* DRAM CS is High => Error!!!"); + TEST_FAIL; + end +endtask + +task REGFILE_CHECK; + input [4:0] addr ; + input [31:0] edata ; + + logic [31:0] reg_data; + @(posedge reg_en ); + @(posedge reg_clk); + if(reg_en)begin + reg_data = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_dat; + if(reg_data !== edata) begin + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,reg_data, edata); + #1us; + //TEST_FAIL; + end + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, reg_data, edata); + end + else begin + $display("* REG WR EN is High => Error!!!"); + //TEST_FAIL; + end + +endtask + +initial begin + #100us; + $display("\n----------------------------------------\n"); + $display("\t Timeout Error !!!!\n"); + TEST_FAIL; +end + diff --git a/tb/qumcu/isa/case/Addi_0x111_test/main.c b/tb/qumcu/isa/case/Addi_0x111_test/main.c new file mode 100644 index 0000000..f92eb3f --- /dev/null +++ b/tb/qumcu/isa/case/Addi_0x111_test/main.c @@ -0,0 +1,20 @@ +//#include + + +//int main(){ +// printf("\t=====================================\n"); +// printf("\t hello world !!! \n"); +// printf("\t=====================================\n"); +//} + +void main(void){ + +unsigned int a,b; + a=5; + b=3; + //c=a+b; + //d=c+b; +} + + + diff --git a/tb/qumcu/isa/case/Addi_0x111_test/main.s b/tb/qumcu/isa/case/Addi_0x111_test/main.s new file mode 100644 index 0000000..f586f99 --- /dev/null +++ b/tb/qumcu/isa/case/Addi_0x111_test/main.s @@ -0,0 +1,31 @@ +addi x1, x0, 0x111 +addi x2, x0, 0x111 +addi x3, x0, 0x111 +addi x4, x0, 0x111 +addi x5, x0, 0x111 +addi x6, x0, 0x111 +addi x7, x0, 0x111 +addi x8, x0, 0x111 +addi x9, x0, 0x111 +addi x10, x0, 0x111 +addi x11, x0, 0x111 +addi x12, x0, 0x111 +addi x13, x0, 0x111 +addi x14, x0, 0x111 +addi x15, x0, 0x111 +addi x16, x0, 0x111 +addi x17, x0, 0x111 +addi x18, x0, 0x111 +addi x19, x0, 0x111 +addi x20, x0, 0x111 +addi x21, x0, 0x111 +addi x22, x0, 0x111 +addi x23, x0, 0x111 +addi x24, x0, 0x111 +addi x25, x0, 0x111 +addi x26, x0, 0x111 +addi x27, x0, 0x111 +addi x28, x0, 0x111 +addi x29, x0, 0x111 +addi x30, x0, 0x111 +addi x31, x0, 0x111 \ No newline at end of file diff --git a/tb/qumcu/isa/case/Addi_0x111_test/user.sv b/tb/qumcu/isa/case/Addi_0x111_test/user.sv new file mode 100644 index 0000000..fe90f44 --- /dev/null +++ b/tb/qumcu/isa/case/Addi_0x111_test/user.sv @@ -0,0 +1,110 @@ + +wire ram_clk = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CLK; +wire ram_cs = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CEBA; +wire reg_clk = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.clk; +wire reg_en = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_wen; +reg ram_cs_dly1 ; +reg reg_en_dly1 ; +always @(posedge ram_clk) begin + ram_cs_dly1 <= ~ram_cs; + reg_en_dly1 <= reg_en; +end + + +initial begin + #1ns; + //@(posedge ram_cs_dly1 ); + #5ns; + //while(1)begin + #1ns; + //@(posedge reg_en_dly1 ); + REGFILE_CHECK(6'd1 ,32'h0000_0111); + REGFILE_CHECK(6'd2 ,32'h0000_0111); + REGFILE_CHECK(6'd3 ,32'h0000_0111); + REGFILE_CHECK(6'd4 ,32'h0000_0111); + REGFILE_CHECK(6'd5 ,32'h0000_0111); + REGFILE_CHECK(6'd6 ,32'h0000_0111); + REGFILE_CHECK(6'd7 ,32'h0000_0111); + REGFILE_CHECK(6'd8 ,32'h0000_0111); + REGFILE_CHECK(6'd9 ,32'h0000_0111); + REGFILE_CHECK(6'd10,32'h0000_0111); + REGFILE_CHECK(6'd11,32'h0000_0111); + REGFILE_CHECK(6'd12,32'h0000_0111); + REGFILE_CHECK(6'd13,32'h0000_0111); + REGFILE_CHECK(6'd14,32'h0000_0111); + REGFILE_CHECK(6'd15,32'h0000_0111); + REGFILE_CHECK(6'd16,32'h0000_0111); + REGFILE_CHECK(6'd17,32'h0000_0111); + REGFILE_CHECK(6'd18,32'h0000_0111); + REGFILE_CHECK(6'd19,32'h0000_0111); + REGFILE_CHECK(6'd20,32'h0000_0111); + REGFILE_CHECK(6'd21,32'h0000_0111); + REGFILE_CHECK(6'd22,32'h0000_0111); + REGFILE_CHECK(6'd23,32'h0000_0111); + REGFILE_CHECK(6'd24,32'h0000_0111); + REGFILE_CHECK(6'd25,32'h0000_0111); + REGFILE_CHECK(6'd26,32'h0000_0111); + REGFILE_CHECK(6'd27,32'h0000_0111); + REGFILE_CHECK(6'd28,32'h0000_0111); + REGFILE_CHECK(6'd29,32'h0000_0111); + REGFILE_CHECK(6'd30,32'h0000_0111); + REGFILE_CHECK(6'd31,32'h0000_0111); + #10us; + TEST_PASS; +end + +task DRAM_DATA_CHECK; + input [9:0] addr ; + input [31:0] edata ; + + logic [31:0] ram_data; + + @(posedge ram_cs_dly1 ); + @(posedge ram_clk ); + //$monitor($time, " Simulation time: %t", $time); + if(ram_cs_dly1) begin + ram_data = `TB_DRAM.mem[addr]; + //$display("* RAM_DATA[%x]: %x | EXP_DATA: %x ",addr,ram_data, edata); + if(ram_data !== edata) begin + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,ram_data, edata); + #1us; + TEST_FAIL; + end + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, ram_data, edata); + end + else begin + $display("* DRAM CS is High => Error!!!"); + TEST_FAIL; + end +endtask + +task REGFILE_CHECK; + input [4:0] addr ; + input [31:0] edata ; + + logic [31:0] reg_data; + @(posedge reg_en ); + @(posedge reg_clk); + if(reg_en)begin + reg_data = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_dat; + if(reg_data !== edata) begin + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,reg_data, edata); + #1us; + //TEST_FAIL; + end + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, reg_data, edata); + end + else begin + $display("* REG WR EN is High => Error!!!"); + //TEST_FAIL; + end + +endtask + +initial begin + #100us; + $display("\n----------------------------------------\n"); + $display("\t Timeout Error !!!!\n"); + TEST_FAIL; +end + diff --git a/tb/qumcu/isa/case/Addi_0x555_test/main.c b/tb/qumcu/isa/case/Addi_0x555_test/main.c new file mode 100644 index 0000000..f92eb3f --- /dev/null +++ b/tb/qumcu/isa/case/Addi_0x555_test/main.c @@ -0,0 +1,20 @@ +//#include + + +//int main(){ +// printf("\t=====================================\n"); +// printf("\t hello world !!! \n"); +// printf("\t=====================================\n"); +//} + +void main(void){ + +unsigned int a,b; + a=5; + b=3; + //c=a+b; + //d=c+b; +} + + + diff --git a/tb/qumcu/isa/case/Addi_0x555_test/main.s b/tb/qumcu/isa/case/Addi_0x555_test/main.s new file mode 100644 index 0000000..86cb14e --- /dev/null +++ b/tb/qumcu/isa/case/Addi_0x555_test/main.s @@ -0,0 +1,31 @@ +addi x1, x0, 0x555 +addi x2, x0, 0x555 +addi x3, x0, 0x555 +addi x4, x0, 0x555 +addi x5, x0, 0x555 +addi x6, x0, 0x555 +addi x7, x0, 0x555 +addi x8, x0, 0x555 +addi x9, x0, 0x555 +addi x10, x0, 0x555 +addi x11, x0, 0x555 +addi x12, x0, 0x555 +addi x13, x0, 0x555 +addi x14, x0, 0x555 +addi x15, x0, 0x555 +addi x16, x0, 0x555 +addi x17, x0, 0x555 +addi x18, x0, 0x555 +addi x19, x0, 0x555 +addi x20, x0, 0x555 +addi x21, x0, 0x555 +addi x22, x0, 0x555 +addi x23, x0, 0x555 +addi x24, x0, 0x555 +addi x25, x0, 0x555 +addi x26, x0, 0x555 +addi x27, x0, 0x555 +addi x28, x0, 0x555 +addi x29, x0, 0x555 +addi x30, x0, 0x555 +addi x31, x0, 0x555 \ No newline at end of file diff --git a/tb/qumcu/isa/case/Addi_0x555_test/user.sv b/tb/qumcu/isa/case/Addi_0x555_test/user.sv new file mode 100644 index 0000000..433e6a3 --- /dev/null +++ b/tb/qumcu/isa/case/Addi_0x555_test/user.sv @@ -0,0 +1,110 @@ + +wire ram_clk = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CLK; +wire ram_cs = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CEBA; +wire reg_clk = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.clk; +wire reg_en = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_wen; +reg ram_cs_dly1 ; +reg reg_en_dly1 ; +always @(posedge ram_clk) begin + ram_cs_dly1 <= ~ram_cs; + reg_en_dly1 <= reg_en; +end + + +initial begin + #1ns; + //@(posedge ram_cs_dly1 ); + #5ns; + //while(1)begin + #1ns; + //@(posedge reg_en_dly1 ); + REGFILE_CHECK(6'd1 ,32'h0000_0555); + REGFILE_CHECK(6'd2 ,32'h0000_0555); + REGFILE_CHECK(6'd3 ,32'h0000_0555); + REGFILE_CHECK(6'd4 ,32'h0000_0555); + REGFILE_CHECK(6'd5 ,32'h0000_0555); + REGFILE_CHECK(6'd6 ,32'h0000_0555); + REGFILE_CHECK(6'd7 ,32'h0000_0555); + REGFILE_CHECK(6'd8 ,32'h0000_0555); + REGFILE_CHECK(6'd9 ,32'h0000_0555); + REGFILE_CHECK(6'd10,32'h0000_0555); + REGFILE_CHECK(6'd11,32'h0000_0555); + REGFILE_CHECK(6'd12,32'h0000_0555); + REGFILE_CHECK(6'd13,32'h0000_0555); + REGFILE_CHECK(6'd14,32'h0000_0555); + REGFILE_CHECK(6'd15,32'h0000_0555); + REGFILE_CHECK(6'd16,32'h0000_0555); + REGFILE_CHECK(6'd17,32'h0000_0555); + REGFILE_CHECK(6'd18,32'h0000_0555); + REGFILE_CHECK(6'd19,32'h0000_0555); + REGFILE_CHECK(6'd20,32'h0000_0555); + REGFILE_CHECK(6'd21,32'h0000_0555); + REGFILE_CHECK(6'd22,32'h0000_0555); + REGFILE_CHECK(6'd23,32'h0000_0555); + REGFILE_CHECK(6'd24,32'h0000_0555); + REGFILE_CHECK(6'd25,32'h0000_0555); + REGFILE_CHECK(6'd26,32'h0000_0555); + REGFILE_CHECK(6'd27,32'h0000_0555); + REGFILE_CHECK(6'd28,32'h0000_0555); + REGFILE_CHECK(6'd29,32'h0000_0555); + REGFILE_CHECK(6'd30,32'h0000_0555); + REGFILE_CHECK(6'd31,32'h0000_0555); + #10us; + TEST_PASS; +end + +task DRAM_DATA_CHECK; + input [9:0] addr ; + input [31:0] edata ; + + logic [31:0] ram_data; + + @(posedge ram_cs_dly1 ); + @(posedge ram_clk ); + //$monitor($time, " Simulation time: %t", $time); + if(ram_cs_dly1) begin + ram_data = `TB_DRAM.mem[addr]; + //$display("* RAM_DATA[%x]: %x | EXP_DATA: %x ",addr,ram_data, edata); + if(ram_data !== edata) begin + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,ram_data, edata); + #1us; + TEST_FAIL; + end + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, ram_data, edata); + end + else begin + $display("* DRAM CS is High => Error!!!"); + TEST_FAIL; + end +endtask + +task REGFILE_CHECK; + input [4:0] addr ; + input [31:0] edata ; + + logic [31:0] reg_data; + @(posedge reg_en ); + @(posedge reg_clk); + if(reg_en)begin + reg_data = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_dat; + if(reg_data !== edata) begin + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,reg_data, edata); + #1us; + //TEST_FAIL; + end + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, reg_data, edata); + end + else begin + $display("* REG WR EN is High => Error!!!"); + //TEST_FAIL; + end + +endtask + +initial begin + #100us; + $display("\n----------------------------------------\n"); + $display("\t Timeout Error !!!!\n"); + TEST_FAIL; +end + diff --git a/tb/qumcu/isa/case/Addi_0xfffff+7ff_test/main.c b/tb/qumcu/isa/case/Addi_0xfffff+7ff_test/main.c new file mode 100644 index 0000000..f92eb3f --- /dev/null +++ b/tb/qumcu/isa/case/Addi_0xfffff+7ff_test/main.c @@ -0,0 +1,20 @@ +//#include + + +//int main(){ +// printf("\t=====================================\n"); +// printf("\t hello world !!! \n"); +// printf("\t=====================================\n"); +//} + +void main(void){ + +unsigned int a,b; + a=5; + b=3; + //c=a+b; + //d=c+b; +} + + + diff --git a/tb/qumcu/isa/case/Addi_0xfffff+7ff_test/main.s b/tb/qumcu/isa/case/Addi_0xfffff+7ff_test/main.s new file mode 100644 index 0000000..cfe72b8 --- /dev/null +++ b/tb/qumcu/isa/case/Addi_0xfffff+7ff_test/main.s @@ -0,0 +1,31 @@ +lui x1, 0xfffff +addi x2, x1, 0x7ff +addi x3, x1, 0x7ff +addi x4, x1, 0x7ff +addi x5, x1, 0x7ff +addi x6, x1, 0x7ff +addi x7, x1, 0x7ff +addi x8, x1, 0x7ff +addi x9, x1, 0x7ff +addi x10, x1, 0x7ff +addi x11, x1, 0x7ff +addi x12, x1, 0x7ff +addi x13, x1, 0x7ff +addi x14, x1, 0x7ff +addi x15, x1, 0x7ff +addi x16, x1, 0x7ff +addi x17, x1, 0x7ff +addi x18, x1, 0x7ff +addi x19, x1, 0x7ff +addi x20, x1, 0x7ff +addi x21, x1, 0x7ff +addi x22, x1, 0x7ff +addi x23, x1, 0x7ff +addi x24, x1, 0x7ff +addi x25, x1, 0x7ff +addi x26, x1, 0x7ff +addi x27, x1, 0x7ff +addi x28, x1, 0x7ff +addi x29, x1, 0x7ff +addi x30, x1, 0x7ff +addi x31, x1, 0x7ff \ No newline at end of file diff --git a/tb/qumcu/isa/case/Addi_0xfffff+7ff_test/user.sv b/tb/qumcu/isa/case/Addi_0xfffff+7ff_test/user.sv new file mode 100644 index 0000000..85bd3e8 --- /dev/null +++ b/tb/qumcu/isa/case/Addi_0xfffff+7ff_test/user.sv @@ -0,0 +1,110 @@ + +wire ram_clk = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CLK; +wire ram_cs = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CEBA; +wire reg_clk = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.clk; +wire reg_en = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_wen; +reg ram_cs_dly1 ; +reg reg_en_dly1 ; +always @(posedge ram_clk) begin + ram_cs_dly1 <= ~ram_cs; + reg_en_dly1 <= reg_en; +end + + +initial begin + #1ns; + //@(posedge ram_cs_dly1 ); + #5ns; + //while(1)begin + #1ns; + //@(posedge reg_en_dly1 ); + REGFILE_CHECK(6'd1 ,32'hffff_f000); + REGFILE_CHECK(6'd2 ,32'hffff_f7ff); + REGFILE_CHECK(6'd3 ,32'hffff_f7ff); + REGFILE_CHECK(6'd4 ,32'hffff_f7ff); + REGFILE_CHECK(6'd5 ,32'hffff_f7ff); + REGFILE_CHECK(6'd6 ,32'hffff_f7ff); + REGFILE_CHECK(6'd7 ,32'hffff_f7ff); + REGFILE_CHECK(6'd8 ,32'hffff_f7ff); + REGFILE_CHECK(6'd9 ,32'hffff_f7ff); + REGFILE_CHECK(6'd10,32'hffff_f7ff); + REGFILE_CHECK(6'd11,32'hffff_f7ff); + REGFILE_CHECK(6'd12,32'hffff_f7ff); + REGFILE_CHECK(6'd13,32'hffff_f7ff); + REGFILE_CHECK(6'd14,32'hffff_f7ff); + REGFILE_CHECK(6'd15,32'hffff_f7ff); + REGFILE_CHECK(6'd16,32'hffff_f7ff); + REGFILE_CHECK(6'd17,32'hffff_f7ff); + REGFILE_CHECK(6'd18,32'hffff_f7ff); + REGFILE_CHECK(6'd19,32'hffff_f7ff); + REGFILE_CHECK(6'd20,32'hffff_f7ff); + REGFILE_CHECK(6'd21,32'hffff_f7ff); + REGFILE_CHECK(6'd22,32'hffff_f7ff); + REGFILE_CHECK(6'd23,32'hffff_f7ff); + REGFILE_CHECK(6'd24,32'hffff_f7ff); + REGFILE_CHECK(6'd25,32'hffff_f7ff); + REGFILE_CHECK(6'd26,32'hffff_f7ff); + REGFILE_CHECK(6'd27,32'hffff_f7ff); + REGFILE_CHECK(6'd28,32'hffff_f7ff); + REGFILE_CHECK(6'd29,32'hffff_f7ff); + REGFILE_CHECK(6'd30,32'hffff_f7ff); + REGFILE_CHECK(6'd31,32'hffff_f7ff); + #10us; + TEST_PASS; +end + +task DRAM_DATA_CHECK; + input [9:0] addr ; + input [31:0] edata ; + + logic [31:0] ram_data; + + @(posedge ram_cs_dly1 ); + @(posedge ram_clk ); + //$monitor($time, " Simulation time: %t", $time); + if(ram_cs_dly1) begin + ram_data = `TB_DRAM.mem[addr]; + //$display("* RAM_DATA[%x]: %x | EXP_DATA: %x ",addr,ram_data, edata); + if(ram_data !== edata) begin + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,ram_data, edata); + #1us; + TEST_FAIL; + end + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, ram_data, edata); + end + else begin + $display("* DRAM CS is High => Error!!!"); + TEST_FAIL; + end +endtask + +task REGFILE_CHECK; + input [4:0] addr ; + input [31:0] edata ; + + logic [31:0] reg_data; + @(posedge reg_en ); + @(posedge reg_clk); + if(reg_en)begin + reg_data = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_dat; + if(reg_data !== edata) begin + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,reg_data, edata); + #1us; + //TEST_FAIL; + end + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, reg_data, edata); + end + else begin + $display("* REG WR EN is High => Error!!!"); + //TEST_FAIL; + end + +endtask + +initial begin + #100us; + $display("\n----------------------------------------\n"); + $display("\t Timeout Error !!!!\n"); + TEST_FAIL; +end + diff --git a/tb/qumcu/isa/case/Addi_2047_test/main.c b/tb/qumcu/isa/case/Addi_2047_test/main.c new file mode 100644 index 0000000..f92eb3f --- /dev/null +++ b/tb/qumcu/isa/case/Addi_2047_test/main.c @@ -0,0 +1,20 @@ +//#include + + +//int main(){ +// printf("\t=====================================\n"); +// printf("\t hello world !!! \n"); +// printf("\t=====================================\n"); +//} + +void main(void){ + +unsigned int a,b; + a=5; + b=3; + //c=a+b; + //d=c+b; +} + + + diff --git a/tb/qumcu/isa/case/Addi_2047_test/main.s b/tb/qumcu/isa/case/Addi_2047_test/main.s new file mode 100644 index 0000000..1aba524 --- /dev/null +++ b/tb/qumcu/isa/case/Addi_2047_test/main.s @@ -0,0 +1,31 @@ +addi x1, x0, 0x7ff +addi x2, x0, 0x7ff +addi x3, x0, 0x7ff +addi x4, x0, 0x7ff +addi x5, x0, 0x7ff +addi x6, x0, 0x7ff +addi x7, x0, 0x7ff +addi x8, x0, 0x7ff +addi x9, x0, 0x7ff +addi x10, x0, 0x7ff +addi x11, x0, 0x7ff +addi x12, x0, 0x7ff +addi x13, x0, 0x7ff +addi x14, x0, 0x7ff +addi x15, x0, 0x7ff +addi x16, x0, 0x7ff +addi x17, x0, 0x7ff +addi x18, x0, 0x7ff +addi x19, x0, 0x7ff +addi x20, x0, 0x7ff +addi x21, x0, 0x7ff +addi x22, x0, 0x7ff +addi x23, x0, 0x7ff +addi x24, x0, 0x7ff +addi x25, x0, 0x7ff +addi x26, x0, 0x7ff +addi x27, x0, 0x7ff +addi x28, x0, 0x7ff +addi x29, x0, 0x7ff +addi x30, x0, 0x7ff +addi x31, x0, 0x7ff \ No newline at end of file diff --git a/tb/qumcu/isa/case/Addi_2047_test/user.sv b/tb/qumcu/isa/case/Addi_2047_test/user.sv new file mode 100644 index 0000000..b7e2b47 --- /dev/null +++ b/tb/qumcu/isa/case/Addi_2047_test/user.sv @@ -0,0 +1,110 @@ + +wire ram_clk = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CLK; +wire ram_cs = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CEBA; +wire reg_clk = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.clk; +wire reg_en = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_wen; +reg ram_cs_dly1 ; +reg reg_en_dly1 ; +always @(posedge ram_clk) begin + ram_cs_dly1 <= ~ram_cs; + reg_en_dly1 <= reg_en; +end + + +initial begin + #1ns; + //@(posedge ram_cs_dly1 ); + #5ns; + //while(1)begin + #1ns; + //@(posedge reg_en_dly1 ); + REGFILE_CHECK(6'd1 ,32'h0000_07ff); + REGFILE_CHECK(6'd2 ,32'h0000_07ff); + REGFILE_CHECK(6'd3 ,32'h0000_07ff); + REGFILE_CHECK(6'd4 ,32'h0000_07ff); + REGFILE_CHECK(6'd5 ,32'h0000_07ff); + REGFILE_CHECK(6'd6 ,32'h0000_07ff); + REGFILE_CHECK(6'd7 ,32'h0000_07ff); + REGFILE_CHECK(6'd8 ,32'h0000_07ff); + REGFILE_CHECK(6'd9 ,32'h0000_07ff); + REGFILE_CHECK(6'd10,32'h0000_07ff); + REGFILE_CHECK(6'd11,32'h0000_07ff); + REGFILE_CHECK(6'd12,32'h0000_07ff); + REGFILE_CHECK(6'd13,32'h0000_07ff); + REGFILE_CHECK(6'd14,32'h0000_07ff); + REGFILE_CHECK(6'd15,32'h0000_07ff); + REGFILE_CHECK(6'd16,32'h0000_07ff); + REGFILE_CHECK(6'd17,32'h0000_07ff); + REGFILE_CHECK(6'd18,32'h0000_07ff); + REGFILE_CHECK(6'd19,32'h0000_07ff); + REGFILE_CHECK(6'd20,32'h0000_07ff); + REGFILE_CHECK(6'd21,32'h0000_07ff); + REGFILE_CHECK(6'd22,32'h0000_07ff); + REGFILE_CHECK(6'd23,32'h0000_07ff); + REGFILE_CHECK(6'd24,32'h0000_07ff); + REGFILE_CHECK(6'd25,32'h0000_07ff); + REGFILE_CHECK(6'd26,32'h0000_07ff); + REGFILE_CHECK(6'd27,32'h0000_07ff); + REGFILE_CHECK(6'd28,32'h0000_07ff); + REGFILE_CHECK(6'd29,32'h0000_07ff); + REGFILE_CHECK(6'd30,32'h0000_07ff); + REGFILE_CHECK(6'd31,32'h0000_07ff); + #10us; + TEST_PASS; +end + +task DRAM_DATA_CHECK; + input [9:0] addr ; + input [31:0] edata ; + + logic [31:0] ram_data; + + @(posedge ram_cs_dly1 ); + @(posedge ram_clk ); + //$monitor($time, " Simulation time: %t", $time); + if(ram_cs_dly1) begin + ram_data = `TB_DRAM.mem[addr]; + //$display("* RAM_DATA[%x]: %x | EXP_DATA: %x ",addr,ram_data, edata); + if(ram_data !== edata) begin + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,ram_data, edata); + #1us; + TEST_FAIL; + end + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, ram_data, edata); + end + else begin + $display("* DRAM CS is High => Error!!!"); + TEST_FAIL; + end +endtask + +task REGFILE_CHECK; + input [4:0] addr ; + input [31:0] edata ; + + logic [31:0] reg_data; + @(posedge reg_en ); + @(posedge reg_clk); + if(reg_en)begin + reg_data = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_dat; + if(reg_data !== edata) begin + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,reg_data, edata); + #1us; + //TEST_FAIL; + end + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, reg_data, edata); + end + else begin + $display("* REG WR EN is High => Error!!!"); + //TEST_FAIL; + end + +endtask + +initial begin + #100us; + $display("\n----------------------------------------\n"); + $display("\t Timeout Error !!!!\n"); + TEST_FAIL; +end + diff --git a/tb/qumcu/isa/case/And_0x00000000_test/main.c b/tb/qumcu/isa/case/And_0x00000000_test/main.c new file mode 100644 index 0000000..f92eb3f --- /dev/null +++ b/tb/qumcu/isa/case/And_0x00000000_test/main.c @@ -0,0 +1,20 @@ +//#include + + +//int main(){ +// printf("\t=====================================\n"); +// printf("\t hello world !!! \n"); +// printf("\t=====================================\n"); +//} + +void main(void){ + +unsigned int a,b; + a=5; + b=3; + //c=a+b; + //d=c+b; +} + + + diff --git a/tb/qumcu/isa/case/And_0x00000000_test/main.s b/tb/qumcu/isa/case/And_0x00000000_test/main.s new file mode 100644 index 0000000..d8e003d --- /dev/null +++ b/tb/qumcu/isa/case/And_0x00000000_test/main.s @@ -0,0 +1,33 @@ +lui x31, 0x0 +addi x1, x31, 0x0 +and x1, x1, x31 +and x2, x1, x31 +and x3, x1, x31 +and x4, x1, x31 +and x5, x1, x31 +and x6, x1, x31 +and x7, x1, x31 +and x8, x1, x31 +and x9, x1, x31 +and x10, x1, x31 +and x11, x1, x31 +and x12, x1, x31 +and x13, x1, x31 +and x14, x1, x31 +and x15, x1, x31 +and x16, x1, x31 +and x17, x1, x31 +and x18, x1, x31 +and x19, x1, x31 +and x20, x1, x31 +and x21, x1, x31 +and x22, x1, x31 +and x23, x1, x31 +and x24, x1, x31 +and x25, x1, x31 +and x26, x1, x31 +and x27, x1, x31 +and x28, x1, x31 +and x29, x1, x31 +and x30, x1, x31 +and x31, x1, x31 \ No newline at end of file diff --git a/tb/qumcu/isa/case/And_0x00000000_test/user.sv b/tb/qumcu/isa/case/And_0x00000000_test/user.sv new file mode 100644 index 0000000..f7512bb --- /dev/null +++ b/tb/qumcu/isa/case/And_0x00000000_test/user.sv @@ -0,0 +1,111 @@ + +wire ram_clk = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CLK; +wire ram_cs = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CEBA; +wire reg_clk = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.clk; +wire reg_en = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_wen; +reg ram_cs_dly1 ; +reg reg_en_dly1 ; +always @(posedge ram_clk) begin + ram_cs_dly1 <= ~ram_cs; + reg_en_dly1 <= reg_en; +end + + +initial begin + #1ns; + //@(posedge ram_cs_dly1 ); + #5ns; + //while(1)begin + #1ns; + //@(posedge reg_en_dly1 ); + REGFILE_CHECK(6'd31,32'h0000_0000); + REGFILE_CHECK(6'd1 ,32'h0000_0000); + REGFILE_CHECK(6'd2 ,32'h0000_0000); + REGFILE_CHECK(6'd3 ,32'h0000_0000); + REGFILE_CHECK(6'd4 ,32'h0000_0000); + REGFILE_CHECK(6'd5 ,32'h0000_0000); + REGFILE_CHECK(6'd6 ,32'h0000_0000); + REGFILE_CHECK(6'd7 ,32'h0000_0000); + REGFILE_CHECK(6'd8 ,32'h0000_0000); + REGFILE_CHECK(6'd9 ,32'h0000_0000); + REGFILE_CHECK(6'd10,32'h0000_0000); + REGFILE_CHECK(6'd11,32'h0000_0000); + REGFILE_CHECK(6'd12,32'h0000_0000); + REGFILE_CHECK(6'd13,32'h0000_0000); + REGFILE_CHECK(6'd14,32'h0000_0000); + REGFILE_CHECK(6'd15,32'h0000_0000); + REGFILE_CHECK(6'd16,32'h0000_0000); + REGFILE_CHECK(6'd17,32'h0000_0000); + REGFILE_CHECK(6'd18,32'h0000_0000); + REGFILE_CHECK(6'd19,32'h0000_0000); + REGFILE_CHECK(6'd20,32'h0000_0000); + REGFILE_CHECK(6'd21,32'h0000_0000); + REGFILE_CHECK(6'd22,32'h0000_0000); + REGFILE_CHECK(6'd23,32'h0000_0000); + REGFILE_CHECK(6'd24,32'h0000_0000); + REGFILE_CHECK(6'd25,32'h0000_0000); + REGFILE_CHECK(6'd26,32'h0000_0000); + REGFILE_CHECK(6'd27,32'h0000_0000); + REGFILE_CHECK(6'd28,32'h0000_0000); + REGFILE_CHECK(6'd29,32'h0000_0000); + REGFILE_CHECK(6'd30,32'h0000_0000); + REGFILE_CHECK(6'd31,32'h0000_0000); + #10us; + TEST_PASS; +end + +task DRAM_DATA_CHECK; + input [9:0] addr ; + input [31:0] edata ; + + logic [31:0] ram_data; + + @(posedge ram_cs_dly1 ); + @(posedge ram_clk ); + //$monitor($time, " Simulation time: %t", $time); + if(ram_cs_dly1) begin + ram_data = `TB_DRAM.mem[addr]; + //$display("* RAM_DATA[%x]: %x | EXP_DATA: %x ",addr,ram_data, edata); + if(ram_data !== edata) begin + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,ram_data, edata); + #1us; + TEST_FAIL; + end + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, ram_data, edata); + end + else begin + $display("* DRAM CS is High => Error!!!"); + TEST_FAIL; + end +endtask + +task REGFILE_CHECK; + input [4:0] addr ; + input [31:0] edata ; + + logic [31:0] reg_data; + @(posedge reg_en ); + @(posedge reg_clk); + if(reg_en)begin + reg_data = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_dat; + if(reg_data !== edata) begin + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,reg_data, edata); + #1us; + //TEST_FAIL; + end + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, reg_data, edata); + end + else begin + $display("* REG WR EN is High => Error!!!"); + //TEST_FAIL; + end + +endtask + +initial begin + #100us; + $display("\n----------------------------------------\n"); + $display("\t Timeout Error !!!!\n"); + TEST_FAIL; +end + diff --git a/tb/qumcu/isa/case/And_0x00xf_test/main.c b/tb/qumcu/isa/case/And_0x00xf_test/main.c new file mode 100644 index 0000000..f92eb3f --- /dev/null +++ b/tb/qumcu/isa/case/And_0x00xf_test/main.c @@ -0,0 +1,20 @@ +//#include + + +//int main(){ +// printf("\t=====================================\n"); +// printf("\t hello world !!! \n"); +// printf("\t=====================================\n"); +//} + +void main(void){ + +unsigned int a,b; + a=5; + b=3; + //c=a+b; + //d=c+b; +} + + + diff --git a/tb/qumcu/isa/case/And_0x00xf_test/main.s b/tb/qumcu/isa/case/And_0x00xf_test/main.s new file mode 100644 index 0000000..04b1286 --- /dev/null +++ b/tb/qumcu/isa/case/And_0x00xf_test/main.s @@ -0,0 +1,37 @@ +lui x31, 0x00000 +addi x31, x31, 0x000 +lui x30, 0xfffff +addi x30, x30, 0x7ff +addi x30, x30, 0x7ff +addi x30, x30, 0x1 +and x1, x31, x30 +and x2, x31, x30 +and x3, x31, x30 +and x4, x31, x30 +and x5, x31, x30 +and x6, x31, x30 +and x7, x31, x30 +and x8, x31, x30 +and x9, x31, x30 +and x10, x31, x30 +and x11, x31, x30 +and x12, x31, x30 +and x13, x31, x30 +and x14, x31, x30 +and x15, x31, x30 +and x16, x31, x30 +and x17, x31, x30 +and x18, x31, x30 +and x19, x31, x30 +and x20, x31, x30 +and x21, x31, x30 +and x22, x31, x30 +and x23, x31, x30 +and x24, x31, x30 +and x25, x31, x30 +and x26, x31, x30 +and x27, x31, x30 +and x28, x31, x30 +and x29, x31, x30 +and x30, x31, x30 +and x31, x31, x30 \ No newline at end of file diff --git a/tb/qumcu/isa/case/And_0x00xf_test/user.sv b/tb/qumcu/isa/case/And_0x00xf_test/user.sv new file mode 100644 index 0000000..857e0ea --- /dev/null +++ b/tb/qumcu/isa/case/And_0x00xf_test/user.sv @@ -0,0 +1,116 @@ + +wire ram_clk = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CLK; +wire ram_cs = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CEBA; +wire reg_clk = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.clk; +wire reg_en = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_wen; +reg ram_cs_dly1 ; +reg reg_en_dly1 ; +always @(posedge ram_clk) begin + ram_cs_dly1 <= ~ram_cs; + reg_en_dly1 <= reg_en; +end + + +initial begin + #1ns; + //@(posedge ram_cs_dly1 ); + #5ns; + //while(1)begin + #1ns; + //@(posedge reg_en_dly1 ); + REGFILE_CHECK(6'd31,32'h0000_0000); + REGFILE_CHECK(6'd31,32'h0000_0000); + REGFILE_CHECK(6'd30,32'hffff_f000); + REGFILE_CHECK(6'd30,32'hffff_f7ff); + REGFILE_CHECK(6'd30,32'hffff_fffe); + REGFILE_CHECK(6'd30,32'hffff_ffff); + REGFILE_CHECK(6'd1 ,32'h0000_0000); + REGFILE_CHECK(6'd2 ,32'h0000_0000); + REGFILE_CHECK(6'd3 ,32'h0000_0000); + REGFILE_CHECK(6'd4 ,32'h0000_0000); + REGFILE_CHECK(6'd5 ,32'h0000_0000); + REGFILE_CHECK(6'd6 ,32'h0000_0000); + REGFILE_CHECK(6'd7 ,32'h0000_0000); + REGFILE_CHECK(6'd8 ,32'h0000_0000); + REGFILE_CHECK(6'd9 ,32'h0000_0000); + REGFILE_CHECK(6'd10,32'h0000_0000); + REGFILE_CHECK(6'd11,32'h0000_0000); + REGFILE_CHECK(6'd12,32'h0000_0000); + REGFILE_CHECK(6'd13,32'h0000_0000); + REGFILE_CHECK(6'd14,32'h0000_0000); + REGFILE_CHECK(6'd15,32'h0000_0000); + REGFILE_CHECK(6'd16,32'h0000_0000); + REGFILE_CHECK(6'd17,32'h0000_0000); + REGFILE_CHECK(6'd18,32'h0000_0000); + REGFILE_CHECK(6'd19,32'h0000_0000); + REGFILE_CHECK(6'd20,32'h0000_0000); + REGFILE_CHECK(6'd21,32'h0000_0000); + REGFILE_CHECK(6'd22,32'h0000_0000); + REGFILE_CHECK(6'd23,32'h0000_0000); + REGFILE_CHECK(6'd24,32'h0000_0000); + REGFILE_CHECK(6'd25,32'h0000_0000); + REGFILE_CHECK(6'd26,32'h0000_0000); + REGFILE_CHECK(6'd27,32'h0000_0000); + REGFILE_CHECK(6'd28,32'h0000_0000); + REGFILE_CHECK(6'd29,32'h0000_0000); + REGFILE_CHECK(6'd30,32'h0000_0000); + REGFILE_CHECK(6'd31,32'h0000_0000); + #10us; + TEST_PASS; +end + +task DRAM_DATA_CHECK; + input [9:0] addr ; + input [31:0] edata ; + + logic [31:0] ram_data; + + @(posedge ram_cs_dly1 ); + @(posedge ram_clk ); + //$monitor($time, " Simulation time: %t", $time); + if(ram_cs_dly1) begin + ram_data = `TB_DRAM.mem[addr]; + //$display("* RAM_DATA[%x]: %x | EXP_DATA: %x ",addr,ram_data, edata); + if(ram_data !== edata) begin + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,ram_data, edata); + #1us; + TEST_FAIL; + end + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, ram_data, edata); + end + else begin + $display("* DRAM CS is High => Error!!!"); + TEST_FAIL; + end +endtask + +task REGFILE_CHECK; + input [4:0] addr ; + input [31:0] edata ; + + logic [31:0] reg_data; + @(posedge reg_en ); + @(posedge reg_clk); + if(reg_en)begin + reg_data = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_dat; + if(reg_data !== edata) begin + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,reg_data, edata); + #1us; + //TEST_FAIL; + end + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, reg_data, edata); + end + else begin + $display("* REG WR EN is High => Error!!!"); + //TEST_FAIL; + end + +endtask + +initial begin + #100us; + $display("\n----------------------------------------\n"); + $display("\t Timeout Error !!!!\n"); + TEST_FAIL; +end + diff --git a/tb/qumcu/isa/case/And_0x11111111_test/main.c b/tb/qumcu/isa/case/And_0x11111111_test/main.c new file mode 100644 index 0000000..f92eb3f --- /dev/null +++ b/tb/qumcu/isa/case/And_0x11111111_test/main.c @@ -0,0 +1,20 @@ +//#include + + +//int main(){ +// printf("\t=====================================\n"); +// printf("\t hello world !!! \n"); +// printf("\t=====================================\n"); +//} + +void main(void){ + +unsigned int a,b; + a=5; + b=3; + //c=a+b; + //d=c+b; +} + + + diff --git a/tb/qumcu/isa/case/And_0x11111111_test/main.s b/tb/qumcu/isa/case/And_0x11111111_test/main.s new file mode 100644 index 0000000..a3a383f --- /dev/null +++ b/tb/qumcu/isa/case/And_0x11111111_test/main.s @@ -0,0 +1,34 @@ +lui x31, 0x11111 +addi x31, x31, 0x111 +addi x1, x31, 0x0 +and x1, x1, x31 +and x2, x1, x31 +and x3, x1, x31 +and x4, x1, x31 +and x5, x1, x31 +and x6, x1, x31 +and x7, x1, x31 +and x8, x1, x31 +and x9, x1, x31 +and x10, x1, x31 +and x11, x1, x31 +and x12, x1, x31 +and x13, x1, x31 +and x14, x1, x31 +and x15, x1, x31 +and x16, x1, x31 +and x17, x1, x31 +and x18, x1, x31 +and x19, x1, x31 +and x20, x1, x31 +and x21, x1, x31 +and x22, x1, x31 +and x23, x1, x31 +and x24, x1, x31 +and x25, x1, x31 +and x26, x1, x31 +and x27, x1, x31 +and x28, x1, x31 +and x29, x1, x31 +and x30, x1, x31 +and x31, x1, x31 \ No newline at end of file diff --git a/tb/qumcu/isa/case/And_0x11111111_test/user.sv b/tb/qumcu/isa/case/And_0x11111111_test/user.sv new file mode 100644 index 0000000..31d08c4 --- /dev/null +++ b/tb/qumcu/isa/case/And_0x11111111_test/user.sv @@ -0,0 +1,112 @@ + +wire ram_clk = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CLK; +wire ram_cs = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CEBA; +wire reg_clk = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.clk; +wire reg_en = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_wen; +reg ram_cs_dly1 ; +reg reg_en_dly1 ; +always @(posedge ram_clk) begin + ram_cs_dly1 <= ~ram_cs; + reg_en_dly1 <= reg_en; +end + + +initial begin + #1ns; + //@(posedge ram_cs_dly1 ); + #5ns; + //while(1)begin + #1ns; + //@(posedge reg_en_dly1 ); + REGFILE_CHECK(6'd31,32'h1111_1000); + REGFILE_CHECK(6'd31,32'h1111_1111); + REGFILE_CHECK(6'd1 ,32'h1111_1111); + REGFILE_CHECK(6'd2 ,32'h1111_1111); + REGFILE_CHECK(6'd3 ,32'h1111_1111); + REGFILE_CHECK(6'd4 ,32'h1111_1111); + REGFILE_CHECK(6'd5 ,32'h1111_1111); + REGFILE_CHECK(6'd6 ,32'h1111_1111); + REGFILE_CHECK(6'd7 ,32'h1111_1111); + REGFILE_CHECK(6'd8 ,32'h1111_1111); + REGFILE_CHECK(6'd9 ,32'h1111_1111); + REGFILE_CHECK(6'd10,32'h1111_1111); + REGFILE_CHECK(6'd11,32'h1111_1111); + REGFILE_CHECK(6'd12,32'h1111_1111); + REGFILE_CHECK(6'd13,32'h1111_1111); + REGFILE_CHECK(6'd14,32'h1111_1111); + REGFILE_CHECK(6'd15,32'h1111_1111); + REGFILE_CHECK(6'd16,32'h1111_1111); + REGFILE_CHECK(6'd17,32'h1111_1111); + REGFILE_CHECK(6'd18,32'h1111_1111); + REGFILE_CHECK(6'd19,32'h1111_1111); + REGFILE_CHECK(6'd20,32'h1111_1111); + REGFILE_CHECK(6'd21,32'h1111_1111); + REGFILE_CHECK(6'd22,32'h1111_1111); + REGFILE_CHECK(6'd23,32'h1111_1111); + REGFILE_CHECK(6'd24,32'h1111_1111); + REGFILE_CHECK(6'd25,32'h1111_1111); + REGFILE_CHECK(6'd26,32'h1111_1111); + REGFILE_CHECK(6'd27,32'h1111_1111); + REGFILE_CHECK(6'd28,32'h1111_1111); + REGFILE_CHECK(6'd29,32'h1111_1111); + REGFILE_CHECK(6'd30,32'h1111_1111); + REGFILE_CHECK(6'd31,32'h1111_1111); + #10us; + TEST_PASS; +end + +task DRAM_DATA_CHECK; + input [9:0] addr ; + input [31:0] edata ; + + logic [31:0] ram_data; + + @(posedge ram_cs_dly1 ); + @(posedge ram_clk ); + //$monitor($time, " Simulation time: %t", $time); + if(ram_cs_dly1) begin + ram_data = `TB_DRAM.mem[addr]; + //$display("* RAM_DATA[%x]: %x | EXP_DATA: %x ",addr,ram_data, edata); + if(ram_data !== edata) begin + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,ram_data, edata); + #1us; + TEST_FAIL; + end + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, ram_data, edata); + end + else begin + $display("* DRAM CS is High => Error!!!"); + TEST_FAIL; + end +endtask + +task REGFILE_CHECK; + input [4:0] addr ; + input [31:0] edata ; + + logic [31:0] reg_data; + @(posedge reg_en ); + @(posedge reg_clk); + if(reg_en)begin + reg_data = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_dat; + if(reg_data !== edata) begin + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,reg_data, edata); + #1us; + //TEST_FAIL; + end + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, reg_data, edata); + end + else begin + $display("* REG WR EN is High => Error!!!"); + //TEST_FAIL; + end + +endtask + +initial begin + #100us; + $display("\n----------------------------------------\n"); + $display("\t Timeout Error !!!!\n"); + TEST_FAIL; +end + diff --git a/tb/qumcu/isa/case/And_0x50x0_test/main.c b/tb/qumcu/isa/case/And_0x50x0_test/main.c new file mode 100644 index 0000000..f92eb3f --- /dev/null +++ b/tb/qumcu/isa/case/And_0x50x0_test/main.c @@ -0,0 +1,20 @@ +//#include + + +//int main(){ +// printf("\t=====================================\n"); +// printf("\t hello world !!! \n"); +// printf("\t=====================================\n"); +//} + +void main(void){ + +unsigned int a,b; + a=5; + b=3; + //c=a+b; + //d=c+b; +} + + + diff --git a/tb/qumcu/isa/case/And_0x50x0_test/main.s b/tb/qumcu/isa/case/And_0x50x0_test/main.s new file mode 100644 index 0000000..94c9c21 --- /dev/null +++ b/tb/qumcu/isa/case/And_0x50x0_test/main.s @@ -0,0 +1,33 @@ +lui x31, 0x55555 +addi x31, x31, 0x555 +and x1, x1, x0 +and x2, x1, x0 +and x3, x1, x0 +and x4, x1, x0 +and x5, x1, x0 +and x6, x1, x0 +and x7, x1, x0 +and x8, x1, x0 +and x9, x1, x0 +and x10, x1, x0 +and x11, x1, x0 +and x12, x1, x0 +and x13, x1, x0 +and x14, x1, x0 +and x15, x1, x0 +and x16, x1, x0 +and x17, x1, x0 +and x18, x1, x0 +and x19, x1, x0 +and x20, x1, x0 +and x21, x1, x0 +and x22, x1, x0 +and x23, x1, x0 +and x24, x1, x0 +and x25, x1, x0 +and x26, x1, x0 +and x27, x1, x0 +and x28, x1, x0 +and x29, x1, x0 +and x30, x1, x0 +and x31, x1, x0 \ No newline at end of file diff --git a/tb/qumcu/isa/case/And_0x50x0_test/user.sv b/tb/qumcu/isa/case/And_0x50x0_test/user.sv new file mode 100644 index 0000000..101e44a --- /dev/null +++ b/tb/qumcu/isa/case/And_0x50x0_test/user.sv @@ -0,0 +1,112 @@ + +wire ram_clk = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CLK; +wire ram_cs = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CEBA; +wire reg_clk = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.clk; +wire reg_en = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_wen; +reg ram_cs_dly1 ; +reg reg_en_dly1 ; +always @(posedge ram_clk) begin + ram_cs_dly1 <= ~ram_cs; + reg_en_dly1 <= reg_en; +end + + +initial begin + #1ns; + //@(posedge ram_cs_dly1 ); + #5ns; + //while(1)begin + #1ns; + //@(posedge reg_en_dly1 ); + REGFILE_CHECK(6'd31,32'h5555_5000); + REGFILE_CHECK(6'd31,32'h5555_5555); + REGFILE_CHECK(6'd1 ,32'h0000_0000); + REGFILE_CHECK(6'd2 ,32'h0000_0000); + REGFILE_CHECK(6'd3 ,32'h0000_0000); + REGFILE_CHECK(6'd4 ,32'h0000_0000); + REGFILE_CHECK(6'd5 ,32'h0000_0000); + REGFILE_CHECK(6'd6 ,32'h0000_0000); + REGFILE_CHECK(6'd7 ,32'h0000_0000); + REGFILE_CHECK(6'd8 ,32'h0000_0000); + REGFILE_CHECK(6'd9 ,32'h0000_0000); + REGFILE_CHECK(6'd10,32'h0000_0000); + REGFILE_CHECK(6'd11,32'h0000_0000); + REGFILE_CHECK(6'd12,32'h0000_0000); + REGFILE_CHECK(6'd13,32'h0000_0000); + REGFILE_CHECK(6'd14,32'h0000_0000); + REGFILE_CHECK(6'd15,32'h0000_0000); + REGFILE_CHECK(6'd16,32'h0000_0000); + REGFILE_CHECK(6'd17,32'h0000_0000); + REGFILE_CHECK(6'd18,32'h0000_0000); + REGFILE_CHECK(6'd19,32'h0000_0000); + REGFILE_CHECK(6'd20,32'h0000_0000); + REGFILE_CHECK(6'd21,32'h0000_0000); + REGFILE_CHECK(6'd22,32'h0000_0000); + REGFILE_CHECK(6'd23,32'h0000_0000); + REGFILE_CHECK(6'd24,32'h0000_0000); + REGFILE_CHECK(6'd25,32'h0000_0000); + REGFILE_CHECK(6'd26,32'h0000_0000); + REGFILE_CHECK(6'd27,32'h0000_0000); + REGFILE_CHECK(6'd28,32'h0000_0000); + REGFILE_CHECK(6'd29,32'h0000_0000); + REGFILE_CHECK(6'd30,32'h0000_0000); + REGFILE_CHECK(6'd31,32'h0000_0000); + #10us; + TEST_PASS; +end + +task DRAM_DATA_CHECK; + input [9:0] addr ; + input [31:0] edata ; + + logic [31:0] ram_data; + + @(posedge ram_cs_dly1 ); + @(posedge ram_clk ); + //$monitor($time, " Simulation time: %t", $time); + if(ram_cs_dly1) begin + ram_data = `TB_DRAM.mem[addr]; + //$display("* RAM_DATA[%x]: %x | EXP_DATA: %x ",addr,ram_data, edata); + if(ram_data !== edata) begin + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,ram_data, edata); + #1us; + TEST_FAIL; + end + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, ram_data, edata); + end + else begin + $display("* DRAM CS is High => Error!!!"); + TEST_FAIL; + end +endtask + +task REGFILE_CHECK; + input [4:0] addr ; + input [31:0] edata ; + + logic [31:0] reg_data; + @(posedge reg_en ); + @(posedge reg_clk); + if(reg_en)begin + reg_data = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_dat; + if(reg_data !== edata) begin + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,reg_data, edata); + #1us; + //TEST_FAIL; + end + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, reg_data, edata); + end + else begin + $display("* REG WR EN is High => Error!!!"); + //TEST_FAIL; + end + +endtask + +initial begin + #100us; + $display("\n----------------------------------------\n"); + $display("\t Timeout Error !!!!\n"); + TEST_FAIL; +end + diff --git a/tb/qumcu/isa/case/And_0x50x1_test/main.c b/tb/qumcu/isa/case/And_0x50x1_test/main.c new file mode 100644 index 0000000..f92eb3f --- /dev/null +++ b/tb/qumcu/isa/case/And_0x50x1_test/main.c @@ -0,0 +1,20 @@ +//#include + + +//int main(){ +// printf("\t=====================================\n"); +// printf("\t hello world !!! \n"); +// printf("\t=====================================\n"); +//} + +void main(void){ + +unsigned int a,b; + a=5; + b=3; + //c=a+b; + //d=c+b; +} + + + diff --git a/tb/qumcu/isa/case/And_0x50x1_test/main.s b/tb/qumcu/isa/case/And_0x50x1_test/main.s new file mode 100644 index 0000000..b1d4c35 --- /dev/null +++ b/tb/qumcu/isa/case/And_0x50x1_test/main.s @@ -0,0 +1,37 @@ +lui x31, 0x55555 +addi x31, x31, 0x555 +lui x30, 0x11111 +addi x30, x30, 0x111 +addi x30, x30, 0x0 +addi x30, x30, 0x0 +and x1, x31, x30 +and x2, x31, x30 +and x3, x31, x30 +and x4, x31, x30 +and x5, x31, x30 +and x6, x31, x30 +and x7, x31, x30 +and x8, x31, x30 +and x9, x31, x30 +and x10, x31, x30 +and x11, x31, x30 +and x12, x31, x30 +and x13, x31, x30 +and x14, x31, x30 +and x15, x31, x30 +and x16, x31, x30 +and x17, x31, x30 +and x18, x31, x30 +and x19, x31, x30 +and x20, x31, x30 +and x21, x31, x30 +and x22, x31, x30 +and x23, x31, x30 +and x24, x31, x30 +and x25, x31, x30 +and x26, x31, x30 +and x27, x31, x30 +and x28, x31, x30 +and x29, x31, x30 +and x30, x31, x30 +and x31, x31, x30 \ No newline at end of file diff --git a/tb/qumcu/isa/case/And_0x50x1_test/user.sv b/tb/qumcu/isa/case/And_0x50x1_test/user.sv new file mode 100644 index 0000000..33371d9 --- /dev/null +++ b/tb/qumcu/isa/case/And_0x50x1_test/user.sv @@ -0,0 +1,116 @@ + +wire ram_clk = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CLK; +wire ram_cs = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CEBA; +wire reg_clk = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.clk; +wire reg_en = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_wen; +reg ram_cs_dly1 ; +reg reg_en_dly1 ; +always @(posedge ram_clk) begin + ram_cs_dly1 <= ~ram_cs; + reg_en_dly1 <= reg_en; +end + + +initial begin + #1ns; + //@(posedge ram_cs_dly1 ); + #5ns; + //while(1)begin + #1ns; + //@(posedge reg_en_dly1 ); + REGFILE_CHECK(6'd31,32'h5555_5000); + REGFILE_CHECK(6'd31,32'h5555_5555); + REGFILE_CHECK(6'd30,32'h1111_1000); + REGFILE_CHECK(6'd30,32'h1111_1111); + REGFILE_CHECK(6'd30,32'h1111_1111); + REGFILE_CHECK(6'd30,32'h1111_1111); + REGFILE_CHECK(6'd1 ,32'h1111_1111); + REGFILE_CHECK(6'd2 ,32'h1111_1111); + REGFILE_CHECK(6'd3 ,32'h1111_1111); + REGFILE_CHECK(6'd4 ,32'h1111_1111); + REGFILE_CHECK(6'd5 ,32'h1111_1111); + REGFILE_CHECK(6'd6 ,32'h1111_1111); + REGFILE_CHECK(6'd7 ,32'h1111_1111); + REGFILE_CHECK(6'd8 ,32'h1111_1111); + REGFILE_CHECK(6'd9 ,32'h1111_1111); + REGFILE_CHECK(6'd10,32'h1111_1111); + REGFILE_CHECK(6'd11,32'h1111_1111); + REGFILE_CHECK(6'd12,32'h1111_1111); + REGFILE_CHECK(6'd13,32'h1111_1111); + REGFILE_CHECK(6'd14,32'h1111_1111); + REGFILE_CHECK(6'd15,32'h1111_1111); + REGFILE_CHECK(6'd16,32'h1111_1111); + REGFILE_CHECK(6'd17,32'h1111_1111); + REGFILE_CHECK(6'd18,32'h1111_1111); + REGFILE_CHECK(6'd19,32'h1111_1111); + REGFILE_CHECK(6'd20,32'h1111_1111); + REGFILE_CHECK(6'd21,32'h1111_1111); + REGFILE_CHECK(6'd22,32'h1111_1111); + REGFILE_CHECK(6'd23,32'h1111_1111); + REGFILE_CHECK(6'd24,32'h1111_1111); + REGFILE_CHECK(6'd25,32'h1111_1111); + REGFILE_CHECK(6'd26,32'h1111_1111); + REGFILE_CHECK(6'd27,32'h1111_1111); + REGFILE_CHECK(6'd28,32'h1111_1111); + REGFILE_CHECK(6'd29,32'h1111_1111); + REGFILE_CHECK(6'd30,32'h1111_1111); + REGFILE_CHECK(6'd31,32'h1111_1111); + #10us; + TEST_PASS; +end + +task DRAM_DATA_CHECK; + input [9:0] addr ; + input [31:0] edata ; + + logic [31:0] ram_data; + + @(posedge ram_cs_dly1 ); + @(posedge ram_clk ); + //$monitor($time, " Simulation time: %t", $time); + if(ram_cs_dly1) begin + ram_data = `TB_DRAM.mem[addr]; + //$display("* RAM_DATA[%x]: %x | EXP_DATA: %x ",addr,ram_data, edata); + if(ram_data !== edata) begin + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,ram_data, edata); + #1us; + TEST_FAIL; + end + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, ram_data, edata); + end + else begin + $display("* DRAM CS is High => Error!!!"); + TEST_FAIL; + end +endtask + +task REGFILE_CHECK; + input [4:0] addr ; + input [31:0] edata ; + + logic [31:0] reg_data; + @(posedge reg_en ); + @(posedge reg_clk); + if(reg_en)begin + reg_data = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_dat; + if(reg_data !== edata) begin + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,reg_data, edata); + #1us; + //TEST_FAIL; + end + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, reg_data, edata); + end + else begin + $display("* REG WR EN is High => Error!!!"); + //TEST_FAIL; + end + +endtask + +initial begin + #100us; + $display("\n----------------------------------------\n"); + $display("\t Timeout Error !!!!\n"); + TEST_FAIL; +end + diff --git a/tb/qumcu/isa/case/And_0x50xa_test/main.c b/tb/qumcu/isa/case/And_0x50xa_test/main.c new file mode 100644 index 0000000..f92eb3f --- /dev/null +++ b/tb/qumcu/isa/case/And_0x50xa_test/main.c @@ -0,0 +1,20 @@ +//#include + + +//int main(){ +// printf("\t=====================================\n"); +// printf("\t hello world !!! \n"); +// printf("\t=====================================\n"); +//} + +void main(void){ + +unsigned int a,b; + a=5; + b=3; + //c=a+b; + //d=c+b; +} + + + diff --git a/tb/qumcu/isa/case/And_0x50xa_test/main.s b/tb/qumcu/isa/case/And_0x50xa_test/main.s new file mode 100644 index 0000000..080c9f1 --- /dev/null +++ b/tb/qumcu/isa/case/And_0x50xa_test/main.s @@ -0,0 +1,36 @@ +lui x31, 0x55555 +addi x31, x31, 0x555 +lui x30, 0xaaaaa +addi x30, x30, 0x555 +addi x30, x30, 0x555 +and x1, x31, x30 +and x2, x31, x30 +and x3, x31, x30 +and x4, x31, x30 +and x5, x31, x30 +and x6, x31, x30 +and x7, x31, x30 +and x8, x31, x30 +and x9, x31, x30 +and x10, x31, x30 +and x11, x31, x30 +and x12, x31, x30 +and x13, x31, x30 +and x14, x31, x30 +and x15, x31, x30 +and x16, x31, x30 +and x17, x31, x30 +and x18, x31, x30 +and x19, x31, x30 +and x20, x31, x30 +and x21, x31, x30 +and x22, x31, x30 +and x23, x31, x30 +and x24, x31, x30 +and x25, x31, x30 +and x26, x31, x30 +and x27, x31, x30 +and x28, x31, x30 +and x29, x31, x30 +and x30, x31, x30 +and x31, x31, x30 \ No newline at end of file diff --git a/tb/qumcu/isa/case/And_0x50xa_test/user.sv b/tb/qumcu/isa/case/And_0x50xa_test/user.sv new file mode 100644 index 0000000..5d9b1ae --- /dev/null +++ b/tb/qumcu/isa/case/And_0x50xa_test/user.sv @@ -0,0 +1,115 @@ + +wire ram_clk = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CLK; +wire ram_cs = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CEBA; +wire reg_clk = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.clk; +wire reg_en = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_wen; +reg ram_cs_dly1 ; +reg reg_en_dly1 ; +always @(posedge ram_clk) begin + ram_cs_dly1 <= ~ram_cs; + reg_en_dly1 <= reg_en; +end + + +initial begin + #1ns; + //@(posedge ram_cs_dly1 ); + #5ns; + //while(1)begin + #1ns; + //@(posedge reg_en_dly1 ); + REGFILE_CHECK(6'd31,32'h5555_5000); + REGFILE_CHECK(6'd31,32'h5555_5555); + REGFILE_CHECK(6'd30,32'haaaa_a000); + REGFILE_CHECK(6'd30,32'haaaa_a555); + REGFILE_CHECK(6'd30,32'haaaa_aaaa); + REGFILE_CHECK(6'd1 ,32'h0000_0000); + REGFILE_CHECK(6'd2 ,32'h0000_0000); + REGFILE_CHECK(6'd3 ,32'h0000_0000); + REGFILE_CHECK(6'd4 ,32'h0000_0000); + REGFILE_CHECK(6'd5 ,32'h0000_0000); + REGFILE_CHECK(6'd6 ,32'h0000_0000); + REGFILE_CHECK(6'd7 ,32'h0000_0000); + REGFILE_CHECK(6'd8 ,32'h0000_0000); + REGFILE_CHECK(6'd9 ,32'h0000_0000); + REGFILE_CHECK(6'd10,32'h0000_0000); + REGFILE_CHECK(6'd11,32'h0000_0000); + REGFILE_CHECK(6'd12,32'h0000_0000); + REGFILE_CHECK(6'd13,32'h0000_0000); + REGFILE_CHECK(6'd14,32'h0000_0000); + REGFILE_CHECK(6'd15,32'h0000_0000); + REGFILE_CHECK(6'd16,32'h0000_0000); + REGFILE_CHECK(6'd17,32'h0000_0000); + REGFILE_CHECK(6'd18,32'h0000_0000); + REGFILE_CHECK(6'd19,32'h0000_0000); + REGFILE_CHECK(6'd20,32'h0000_0000); + REGFILE_CHECK(6'd21,32'h0000_0000); + REGFILE_CHECK(6'd22,32'h0000_0000); + REGFILE_CHECK(6'd23,32'h0000_0000); + REGFILE_CHECK(6'd24,32'h0000_0000); + REGFILE_CHECK(6'd25,32'h0000_0000); + REGFILE_CHECK(6'd26,32'h0000_0000); + REGFILE_CHECK(6'd27,32'h0000_0000); + REGFILE_CHECK(6'd28,32'h0000_0000); + REGFILE_CHECK(6'd29,32'h0000_0000); + REGFILE_CHECK(6'd30,32'h0000_0000); + REGFILE_CHECK(6'd31,32'h0000_0000); + #10us; + TEST_PASS; +end + +task DRAM_DATA_CHECK; + input [9:0] addr ; + input [31:0] edata ; + + logic [31:0] ram_data; + + @(posedge ram_cs_dly1 ); + @(posedge ram_clk ); + //$monitor($time, " Simulation time: %t", $time); + if(ram_cs_dly1) begin + ram_data = `TB_DRAM.mem[addr]; + //$display("* RAM_DATA[%x]: %x | EXP_DATA: %x ",addr,ram_data, edata); + if(ram_data !== edata) begin + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,ram_data, edata); + #1us; + TEST_FAIL; + end + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, ram_data, edata); + end + else begin + $display("* DRAM CS is High => Error!!!"); + TEST_FAIL; + end +endtask + +task REGFILE_CHECK; + input [4:0] addr ; + input [31:0] edata ; + + logic [31:0] reg_data; + @(posedge reg_en ); + @(posedge reg_clk); + if(reg_en)begin + reg_data = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_dat; + if(reg_data !== edata) begin + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,reg_data, edata); + #1us; + //TEST_FAIL; + end + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, reg_data, edata); + end + else begin + $display("* REG WR EN is High => Error!!!"); + //TEST_FAIL; + end + +endtask + +initial begin + #100us; + $display("\n----------------------------------------\n"); + $display("\t Timeout Error !!!!\n"); + TEST_FAIL; +end + diff --git a/tb/qumcu/isa/case/And_0x50xf_test/main.c b/tb/qumcu/isa/case/And_0x50xf_test/main.c new file mode 100644 index 0000000..f92eb3f --- /dev/null +++ b/tb/qumcu/isa/case/And_0x50xf_test/main.c @@ -0,0 +1,20 @@ +//#include + + +//int main(){ +// printf("\t=====================================\n"); +// printf("\t hello world !!! \n"); +// printf("\t=====================================\n"); +//} + +void main(void){ + +unsigned int a,b; + a=5; + b=3; + //c=a+b; + //d=c+b; +} + + + diff --git a/tb/qumcu/isa/case/And_0x50xf_test/main.s b/tb/qumcu/isa/case/And_0x50xf_test/main.s new file mode 100644 index 0000000..96f2a1f --- /dev/null +++ b/tb/qumcu/isa/case/And_0x50xf_test/main.s @@ -0,0 +1,37 @@ +lui x31, 0x55555 +addi x31, x31, 0x555 +lui x30, 0xfffff +addi x30, x30, 0x7ff +addi x30, x30, 0x7ff +addi x30, x30, 0x1 +and x1, x31, x30 +and x2, x31, x30 +and x3, x31, x30 +and x4, x31, x30 +and x5, x31, x30 +and x6, x31, x30 +and x7, x31, x30 +and x8, x31, x30 +and x9, x31, x30 +and x10, x31, x30 +and x11, x31, x30 +and x12, x31, x30 +and x13, x31, x30 +and x14, x31, x30 +and x15, x31, x30 +and x16, x31, x30 +and x17, x31, x30 +and x18, x31, x30 +and x19, x31, x30 +and x20, x31, x30 +and x21, x31, x30 +and x22, x31, x30 +and x23, x31, x30 +and x24, x31, x30 +and x25, x31, x30 +and x26, x31, x30 +and x27, x31, x30 +and x28, x31, x30 +and x29, x31, x30 +and x30, x31, x30 +and x31, x31, x30 \ No newline at end of file diff --git a/tb/qumcu/isa/case/And_0x50xf_test/user.sv b/tb/qumcu/isa/case/And_0x50xf_test/user.sv new file mode 100644 index 0000000..9c3ad56 --- /dev/null +++ b/tb/qumcu/isa/case/And_0x50xf_test/user.sv @@ -0,0 +1,116 @@ + +wire ram_clk = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CLK; +wire ram_cs = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CEBA; +wire reg_clk = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.clk; +wire reg_en = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_wen; +reg ram_cs_dly1 ; +reg reg_en_dly1 ; +always @(posedge ram_clk) begin + ram_cs_dly1 <= ~ram_cs; + reg_en_dly1 <= reg_en; +end + + +initial begin + #1ns; + //@(posedge ram_cs_dly1 ); + #5ns; + //while(1)begin + #1ns; + //@(posedge reg_en_dly1 ); + REGFILE_CHECK(6'd31,32'h5555_5000); + REGFILE_CHECK(6'd31,32'h5555_5555); + REGFILE_CHECK(6'd30,32'hffff_f000); + REGFILE_CHECK(6'd30,32'hffff_f7ff); + REGFILE_CHECK(6'd30,32'hffff_fffe); + REGFILE_CHECK(6'd30,32'hffff_ffff); + REGFILE_CHECK(6'd1 ,32'h5555_5555); + REGFILE_CHECK(6'd2 ,32'h5555_5555); + REGFILE_CHECK(6'd3 ,32'h5555_5555); + REGFILE_CHECK(6'd4 ,32'h5555_5555); + REGFILE_CHECK(6'd5 ,32'h5555_5555); + REGFILE_CHECK(6'd6 ,32'h5555_5555); + REGFILE_CHECK(6'd7 ,32'h5555_5555); + REGFILE_CHECK(6'd8 ,32'h5555_5555); + REGFILE_CHECK(6'd9 ,32'h5555_5555); + REGFILE_CHECK(6'd10,32'h5555_5555); + REGFILE_CHECK(6'd11,32'h5555_5555); + REGFILE_CHECK(6'd12,32'h5555_5555); + REGFILE_CHECK(6'd13,32'h5555_5555); + REGFILE_CHECK(6'd14,32'h5555_5555); + REGFILE_CHECK(6'd15,32'h5555_5555); + REGFILE_CHECK(6'd16,32'h5555_5555); + REGFILE_CHECK(6'd17,32'h5555_5555); + REGFILE_CHECK(6'd18,32'h5555_5555); + REGFILE_CHECK(6'd19,32'h5555_5555); + REGFILE_CHECK(6'd20,32'h5555_5555); + REGFILE_CHECK(6'd21,32'h5555_5555); + REGFILE_CHECK(6'd22,32'h5555_5555); + REGFILE_CHECK(6'd23,32'h5555_5555); + REGFILE_CHECK(6'd24,32'h5555_5555); + REGFILE_CHECK(6'd25,32'h5555_5555); + REGFILE_CHECK(6'd26,32'h5555_5555); + REGFILE_CHECK(6'd27,32'h5555_5555); + REGFILE_CHECK(6'd28,32'h5555_5555); + REGFILE_CHECK(6'd29,32'h5555_5555); + REGFILE_CHECK(6'd30,32'h5555_5555); + REGFILE_CHECK(6'd31,32'h5555_5555); + #10us; + TEST_PASS; +end + +task DRAM_DATA_CHECK; + input [9:0] addr ; + input [31:0] edata ; + + logic [31:0] ram_data; + + @(posedge ram_cs_dly1 ); + @(posedge ram_clk ); + //$monitor($time, " Simulation time: %t", $time); + if(ram_cs_dly1) begin + ram_data = `TB_DRAM.mem[addr]; + //$display("* RAM_DATA[%x]: %x | EXP_DATA: %x ",addr,ram_data, edata); + if(ram_data !== edata) begin + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,ram_data, edata); + #1us; + TEST_FAIL; + end + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, ram_data, edata); + end + else begin + $display("* DRAM CS is High => Error!!!"); + TEST_FAIL; + end +endtask + +task REGFILE_CHECK; + input [4:0] addr ; + input [31:0] edata ; + + logic [31:0] reg_data; + @(posedge reg_en ); + @(posedge reg_clk); + if(reg_en)begin + reg_data = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_dat; + if(reg_data !== edata) begin + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,reg_data, edata); + #1us; + //TEST_FAIL; + end + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, reg_data, edata); + end + else begin + $display("* REG WR EN is High => Error!!!"); + //TEST_FAIL; + end + +endtask + +initial begin + #100us; + $display("\n----------------------------------------\n"); + $display("\t Timeout Error !!!!\n"); + TEST_FAIL; +end + diff --git a/tb/qumcu/isa/case/And_0x55555555_test/main.c b/tb/qumcu/isa/case/And_0x55555555_test/main.c new file mode 100644 index 0000000..f92eb3f --- /dev/null +++ b/tb/qumcu/isa/case/And_0x55555555_test/main.c @@ -0,0 +1,20 @@ +//#include + + +//int main(){ +// printf("\t=====================================\n"); +// printf("\t hello world !!! \n"); +// printf("\t=====================================\n"); +//} + +void main(void){ + +unsigned int a,b; + a=5; + b=3; + //c=a+b; + //d=c+b; +} + + + diff --git a/tb/qumcu/isa/case/And_0x55555555_test/main.s b/tb/qumcu/isa/case/And_0x55555555_test/main.s new file mode 100644 index 0000000..785e6e9 --- /dev/null +++ b/tb/qumcu/isa/case/And_0x55555555_test/main.s @@ -0,0 +1,34 @@ +lui x31, 0x55555 +addi x31, x31, 0x555 +addi x1, x31, 0x0 +and x1, x1, x31 +and x2, x1, x31 +and x3, x1, x31 +and x4, x1, x31 +and x5, x1, x31 +and x6, x1, x31 +and x7, x1, x31 +and x8, x1, x31 +and x9, x1, x31 +and x10, x1, x31 +and x11, x1, x31 +and x12, x1, x31 +and x13, x1, x31 +and x14, x1, x31 +and x15, x1, x31 +and x16, x1, x31 +and x17, x1, x31 +and x18, x1, x31 +and x19, x1, x31 +and x20, x1, x31 +and x21, x1, x31 +and x22, x1, x31 +and x23, x1, x31 +and x24, x1, x31 +and x25, x1, x31 +and x26, x1, x31 +and x27, x1, x31 +and x28, x1, x31 +and x29, x1, x31 +and x30, x1, x31 +and x31, x1, x31 \ No newline at end of file diff --git a/tb/qumcu/isa/case/And_0x55555555_test/user.sv b/tb/qumcu/isa/case/And_0x55555555_test/user.sv new file mode 100644 index 0000000..d113938 --- /dev/null +++ b/tb/qumcu/isa/case/And_0x55555555_test/user.sv @@ -0,0 +1,112 @@ + +wire ram_clk = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CLK; +wire ram_cs = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CEBA; +wire reg_clk = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.clk; +wire reg_en = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_wen; +reg ram_cs_dly1 ; +reg reg_en_dly1 ; +always @(posedge ram_clk) begin + ram_cs_dly1 <= ~ram_cs; + reg_en_dly1 <= reg_en; +end + + +initial begin + #1ns; + //@(posedge ram_cs_dly1 ); + #5ns; + //while(1)begin + #1ns; + //@(posedge reg_en_dly1 ); + REGFILE_CHECK(6'd31,32'h5555_5000); + REGFILE_CHECK(6'd31,32'h5555_5555); + REGFILE_CHECK(6'd1 ,32'h5555_5555); + REGFILE_CHECK(6'd2 ,32'h5555_5555); + REGFILE_CHECK(6'd3 ,32'h5555_5555); + REGFILE_CHECK(6'd4 ,32'h5555_5555); + REGFILE_CHECK(6'd5 ,32'h5555_5555); + REGFILE_CHECK(6'd6 ,32'h5555_5555); + REGFILE_CHECK(6'd7 ,32'h5555_5555); + REGFILE_CHECK(6'd8 ,32'h5555_5555); + REGFILE_CHECK(6'd9 ,32'h5555_5555); + REGFILE_CHECK(6'd10,32'h5555_5555); + REGFILE_CHECK(6'd11,32'h5555_5555); + REGFILE_CHECK(6'd12,32'h5555_5555); + REGFILE_CHECK(6'd13,32'h5555_5555); + REGFILE_CHECK(6'd14,32'h5555_5555); + REGFILE_CHECK(6'd15,32'h5555_5555); + REGFILE_CHECK(6'd16,32'h5555_5555); + REGFILE_CHECK(6'd17,32'h5555_5555); + REGFILE_CHECK(6'd18,32'h5555_5555); + REGFILE_CHECK(6'd19,32'h5555_5555); + REGFILE_CHECK(6'd20,32'h5555_5555); + REGFILE_CHECK(6'd21,32'h5555_5555); + REGFILE_CHECK(6'd22,32'h5555_5555); + REGFILE_CHECK(6'd23,32'h5555_5555); + REGFILE_CHECK(6'd24,32'h5555_5555); + REGFILE_CHECK(6'd25,32'h5555_5555); + REGFILE_CHECK(6'd26,32'h5555_5555); + REGFILE_CHECK(6'd27,32'h5555_5555); + REGFILE_CHECK(6'd28,32'h5555_5555); + REGFILE_CHECK(6'd29,32'h5555_5555); + REGFILE_CHECK(6'd30,32'h5555_5555); + REGFILE_CHECK(6'd31,32'h5555_5555); + #10us; + TEST_PASS; +end + +task DRAM_DATA_CHECK; + input [9:0] addr ; + input [31:0] edata ; + + logic [31:0] ram_data; + + @(posedge ram_cs_dly1 ); + @(posedge ram_clk ); + //$monitor($time, " Simulation time: %t", $time); + if(ram_cs_dly1) begin + ram_data = `TB_DRAM.mem[addr]; + //$display("* RAM_DATA[%x]: %x | EXP_DATA: %x ",addr,ram_data, edata); + if(ram_data !== edata) begin + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,ram_data, edata); + #1us; + TEST_FAIL; + end + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, ram_data, edata); + end + else begin + $display("* DRAM CS is High => Error!!!"); + TEST_FAIL; + end +endtask + +task REGFILE_CHECK; + input [4:0] addr ; + input [31:0] edata ; + + logic [31:0] reg_data; + @(posedge reg_en ); + @(posedge reg_clk); + if(reg_en)begin + reg_data = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_dat; + if(reg_data !== edata) begin + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,reg_data, edata); + #1us; + //TEST_FAIL; + end + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, reg_data, edata); + end + else begin + $display("* REG WR EN is High => Error!!!"); + //TEST_FAIL; + end + +endtask + +initial begin + #100us; + $display("\n----------------------------------------\n"); + $display("\t Timeout Error !!!!\n"); + TEST_FAIL; +end + diff --git a/tb/qumcu/isa/case/And_0xffffffff_test/main.c b/tb/qumcu/isa/case/And_0xffffffff_test/main.c new file mode 100644 index 0000000..f92eb3f --- /dev/null +++ b/tb/qumcu/isa/case/And_0xffffffff_test/main.c @@ -0,0 +1,20 @@ +//#include + + +//int main(){ +// printf("\t=====================================\n"); +// printf("\t hello world !!! \n"); +// printf("\t=====================================\n"); +//} + +void main(void){ + +unsigned int a,b; + a=5; + b=3; + //c=a+b; + //d=c+b; +} + + + diff --git a/tb/qumcu/isa/case/And_0xffffffff_test/main.s b/tb/qumcu/isa/case/And_0xffffffff_test/main.s new file mode 100644 index 0000000..ae2845e --- /dev/null +++ b/tb/qumcu/isa/case/And_0xffffffff_test/main.s @@ -0,0 +1,36 @@ +lui x31, 0xfffff +addi x31, x31, 0x7ff +addi x31, x31, 0x7ff +addi x31, x31, 0x1 +addi x1, x31, 0x0 +and x1, x1, x31 +and x2, x1, x31 +and x3, x1, x31 +and x4, x1, x31 +and x5, x1, x31 +and x6, x1, x31 +and x7, x1, x31 +and x8, x1, x31 +and x9, x1, x31 +and x10, x1, x31 +and x11, x1, x31 +and x12, x1, x31 +and x13, x1, x31 +and x14, x1, x31 +and x15, x1, x31 +and x16, x1, x31 +and x17, x1, x31 +and x18, x1, x31 +and x19, x1, x31 +and x20, x1, x31 +and x21, x1, x31 +and x22, x1, x31 +and x23, x1, x31 +and x24, x1, x31 +and x25, x1, x31 +and x26, x1, x31 +and x27, x1, x31 +and x28, x1, x31 +and x29, x1, x31 +and x30, x1, x31 +and x31, x1, x31 \ No newline at end of file diff --git a/tb/qumcu/isa/case/And_0xffffffff_test/user.sv b/tb/qumcu/isa/case/And_0xffffffff_test/user.sv new file mode 100644 index 0000000..b493565 --- /dev/null +++ b/tb/qumcu/isa/case/And_0xffffffff_test/user.sv @@ -0,0 +1,114 @@ + +wire ram_clk = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CLK; +wire ram_cs = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CEBA; +wire reg_clk = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.clk; +wire reg_en = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_wen; +reg ram_cs_dly1 ; +reg reg_en_dly1 ; +always @(posedge ram_clk) begin + ram_cs_dly1 <= ~ram_cs; + reg_en_dly1 <= reg_en; +end + + +initial begin + #1ns; + //@(posedge ram_cs_dly1 ); + #5ns; + //while(1)begin + #1ns; + //@(posedge reg_en_dly1 ); + REGFILE_CHECK(6'd31,32'hffff_f000); + REGFILE_CHECK(6'd31,32'hffff_f7ff); + REGFILE_CHECK(6'd31,32'hffff_fffe); + REGFILE_CHECK(6'd31,32'hffff_ffff); + REGFILE_CHECK(6'd1 ,32'hffff_ffff); + REGFILE_CHECK(6'd2 ,32'hffff_ffff); + REGFILE_CHECK(6'd3 ,32'hffff_ffff); + REGFILE_CHECK(6'd4 ,32'hffff_ffff); + REGFILE_CHECK(6'd5 ,32'hffff_ffff); + REGFILE_CHECK(6'd6 ,32'hffff_ffff); + REGFILE_CHECK(6'd7 ,32'hffff_ffff); + REGFILE_CHECK(6'd8 ,32'hffff_ffff); + REGFILE_CHECK(6'd9 ,32'hffff_ffff); + REGFILE_CHECK(6'd10,32'hffff_ffff); + REGFILE_CHECK(6'd11,32'hffff_ffff); + REGFILE_CHECK(6'd12,32'hffff_ffff); + REGFILE_CHECK(6'd13,32'hffff_ffff); + REGFILE_CHECK(6'd14,32'hffff_ffff); + REGFILE_CHECK(6'd15,32'hffff_ffff); + REGFILE_CHECK(6'd16,32'hffff_ffff); + REGFILE_CHECK(6'd17,32'hffff_ffff); + REGFILE_CHECK(6'd18,32'hffff_ffff); + REGFILE_CHECK(6'd19,32'hffff_ffff); + REGFILE_CHECK(6'd20,32'hffff_ffff); + REGFILE_CHECK(6'd21,32'hffff_ffff); + REGFILE_CHECK(6'd22,32'hffff_ffff); + REGFILE_CHECK(6'd23,32'hffff_ffff); + REGFILE_CHECK(6'd24,32'hffff_ffff); + REGFILE_CHECK(6'd25,32'hffff_ffff); + REGFILE_CHECK(6'd26,32'hffff_ffff); + REGFILE_CHECK(6'd27,32'hffff_ffff); + REGFILE_CHECK(6'd28,32'hffff_ffff); + REGFILE_CHECK(6'd29,32'hffff_ffff); + REGFILE_CHECK(6'd30,32'hffff_ffff); + REGFILE_CHECK(6'd31,32'hffff_ffff); + #10us; + TEST_PASS; +end + +task DRAM_DATA_CHECK; + input [9:0] addr ; + input [31:0] edata ; + + logic [31:0] ram_data; + + @(posedge ram_cs_dly1 ); + @(posedge ram_clk ); + //$monitor($time, " Simulation time: %t", $time); + if(ram_cs_dly1) begin + ram_data = `TB_DRAM.mem[addr]; + //$display("* RAM_DATA[%x]: %x | EXP_DATA: %x ",addr,ram_data, edata); + if(ram_data !== edata) begin + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,ram_data, edata); + #1us; + TEST_FAIL; + end + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, ram_data, edata); + end + else begin + $display("* DRAM CS is High => Error!!!"); + TEST_FAIL; + end +endtask + +task REGFILE_CHECK; + input [4:0] addr ; + input [31:0] edata ; + + logic [31:0] reg_data; + @(posedge reg_en ); + @(posedge reg_clk); + if(reg_en)begin + reg_data = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_dat; + if(reg_data !== edata) begin + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,reg_data, edata); + #1us; + //TEST_FAIL; + end + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, reg_data, edata); + end + else begin + $display("* REG WR EN is High => Error!!!"); + //TEST_FAIL; + end + +endtask + +initial begin + #100us; + $display("\n----------------------------------------\n"); + $display("\t Timeout Error !!!!\n"); + TEST_FAIL; +end + diff --git a/tb/qumcu/isa/case/Andi_0x00x0_test/main.c b/tb/qumcu/isa/case/Andi_0x00x0_test/main.c new file mode 100644 index 0000000..f92eb3f --- /dev/null +++ b/tb/qumcu/isa/case/Andi_0x00x0_test/main.c @@ -0,0 +1,20 @@ +//#include + + +//int main(){ +// printf("\t=====================================\n"); +// printf("\t hello world !!! \n"); +// printf("\t=====================================\n"); +//} + +void main(void){ + +unsigned int a,b; + a=5; + b=3; + //c=a+b; + //d=c+b; +} + + + diff --git a/tb/qumcu/isa/case/Andi_0x00x0_test/main.s b/tb/qumcu/isa/case/Andi_0x00x0_test/main.s new file mode 100644 index 0000000..9eb3660 --- /dev/null +++ b/tb/qumcu/isa/case/Andi_0x00x0_test/main.s @@ -0,0 +1,37 @@ +lui x31, 0x00000 +addi x31, x31, 0x000 +lui x30, 0xfffff +addi x30, x30, 0x7ff +addi x30, x30, 0x7ff +addi x30, x30, 0x1 +andi x1, x0, 0x0 +andi x2, x0, 0x0 +andi x3, x0, 0x0 +andi x4, x0, 0x0 +andi x5, x0, 0x0 +andi x6, x0, 0x0 +andi x7, x0, 0x0 +andi x8, x0, 0x0 +andi x9, x0, 0x0 +andi x10, x0, 0x0 +andi x11, x0, 0x0 +andi x12, x0, 0x0 +andi x13, x0, 0x0 +andi x14, x0, 0x0 +andi x15, x0, 0x0 +andi x16, x0, 0x0 +andi x17, x0, 0x0 +andi x18, x0, 0x0 +andi x19, x0, 0x0 +andi x20, x0, 0x0 +andi x21, x0, 0x0 +andi x22, x0, 0x0 +andi x23, x0, 0x0 +andi x24, x0, 0x0 +andi x25, x0, 0x0 +andi x26, x0, 0x0 +andi x27, x0, 0x0 +andi x28, x0, 0x0 +andi x29, x0, 0x0 +andi x30, x0, 0x0 +andi x31, x0, 0x0 \ No newline at end of file diff --git a/tb/qumcu/isa/case/Andi_0x00x0_test/user.sv b/tb/qumcu/isa/case/Andi_0x00x0_test/user.sv new file mode 100644 index 0000000..857e0ea --- /dev/null +++ b/tb/qumcu/isa/case/Andi_0x00x0_test/user.sv @@ -0,0 +1,116 @@ + +wire ram_clk = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CLK; +wire ram_cs = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CEBA; +wire reg_clk = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.clk; +wire reg_en = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_wen; +reg ram_cs_dly1 ; +reg reg_en_dly1 ; +always @(posedge ram_clk) begin + ram_cs_dly1 <= ~ram_cs; + reg_en_dly1 <= reg_en; +end + + +initial begin + #1ns; + //@(posedge ram_cs_dly1 ); + #5ns; + //while(1)begin + #1ns; + //@(posedge reg_en_dly1 ); + REGFILE_CHECK(6'd31,32'h0000_0000); + REGFILE_CHECK(6'd31,32'h0000_0000); + REGFILE_CHECK(6'd30,32'hffff_f000); + REGFILE_CHECK(6'd30,32'hffff_f7ff); + REGFILE_CHECK(6'd30,32'hffff_fffe); + REGFILE_CHECK(6'd30,32'hffff_ffff); + REGFILE_CHECK(6'd1 ,32'h0000_0000); + REGFILE_CHECK(6'd2 ,32'h0000_0000); + REGFILE_CHECK(6'd3 ,32'h0000_0000); + REGFILE_CHECK(6'd4 ,32'h0000_0000); + REGFILE_CHECK(6'd5 ,32'h0000_0000); + REGFILE_CHECK(6'd6 ,32'h0000_0000); + REGFILE_CHECK(6'd7 ,32'h0000_0000); + REGFILE_CHECK(6'd8 ,32'h0000_0000); + REGFILE_CHECK(6'd9 ,32'h0000_0000); + REGFILE_CHECK(6'd10,32'h0000_0000); + REGFILE_CHECK(6'd11,32'h0000_0000); + REGFILE_CHECK(6'd12,32'h0000_0000); + REGFILE_CHECK(6'd13,32'h0000_0000); + REGFILE_CHECK(6'd14,32'h0000_0000); + REGFILE_CHECK(6'd15,32'h0000_0000); + REGFILE_CHECK(6'd16,32'h0000_0000); + REGFILE_CHECK(6'd17,32'h0000_0000); + REGFILE_CHECK(6'd18,32'h0000_0000); + REGFILE_CHECK(6'd19,32'h0000_0000); + REGFILE_CHECK(6'd20,32'h0000_0000); + REGFILE_CHECK(6'd21,32'h0000_0000); + REGFILE_CHECK(6'd22,32'h0000_0000); + REGFILE_CHECK(6'd23,32'h0000_0000); + REGFILE_CHECK(6'd24,32'h0000_0000); + REGFILE_CHECK(6'd25,32'h0000_0000); + REGFILE_CHECK(6'd26,32'h0000_0000); + REGFILE_CHECK(6'd27,32'h0000_0000); + REGFILE_CHECK(6'd28,32'h0000_0000); + REGFILE_CHECK(6'd29,32'h0000_0000); + REGFILE_CHECK(6'd30,32'h0000_0000); + REGFILE_CHECK(6'd31,32'h0000_0000); + #10us; + TEST_PASS; +end + +task DRAM_DATA_CHECK; + input [9:0] addr ; + input [31:0] edata ; + + logic [31:0] ram_data; + + @(posedge ram_cs_dly1 ); + @(posedge ram_clk ); + //$monitor($time, " Simulation time: %t", $time); + if(ram_cs_dly1) begin + ram_data = `TB_DRAM.mem[addr]; + //$display("* RAM_DATA[%x]: %x | EXP_DATA: %x ",addr,ram_data, edata); + if(ram_data !== edata) begin + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,ram_data, edata); + #1us; + TEST_FAIL; + end + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, ram_data, edata); + end + else begin + $display("* DRAM CS is High => Error!!!"); + TEST_FAIL; + end +endtask + +task REGFILE_CHECK; + input [4:0] addr ; + input [31:0] edata ; + + logic [31:0] reg_data; + @(posedge reg_en ); + @(posedge reg_clk); + if(reg_en)begin + reg_data = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_dat; + if(reg_data !== edata) begin + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,reg_data, edata); + #1us; + //TEST_FAIL; + end + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, reg_data, edata); + end + else begin + $display("* REG WR EN is High => Error!!!"); + //TEST_FAIL; + end + +endtask + +initial begin + #100us; + $display("\n----------------------------------------\n"); + $display("\t Timeout Error !!!!\n"); + TEST_FAIL; +end + diff --git a/tb/qumcu/isa/case/Andi_0x10-2048_test/main.c b/tb/qumcu/isa/case/Andi_0x10-2048_test/main.c new file mode 100644 index 0000000..f92eb3f --- /dev/null +++ b/tb/qumcu/isa/case/Andi_0x10-2048_test/main.c @@ -0,0 +1,20 @@ +//#include + + +//int main(){ +// printf("\t=====================================\n"); +// printf("\t hello world !!! \n"); +// printf("\t=====================================\n"); +//} + +void main(void){ + +unsigned int a,b; + a=5; + b=3; + //c=a+b; + //d=c+b; +} + + + diff --git a/tb/qumcu/isa/case/Andi_0x10-2048_test/main.s b/tb/qumcu/isa/case/Andi_0x10-2048_test/main.s new file mode 100644 index 0000000..b445221 --- /dev/null +++ b/tb/qumcu/isa/case/Andi_0x10-2048_test/main.s @@ -0,0 +1,37 @@ +lui x31, 0x11111 +addi x31, x31, 0x111 +lui x30, 0xfffff +addi x30, x30, 0x7ff +addi x30, x30, 0x7ff +addi x30, x30, 0x1 +andi x1, x31, -0x800 +andi x2, x31, -0x800 +andi x3, x31, -0x800 +andi x4, x31, -0x800 +andi x5, x31, -0x800 +andi x6, x31, -0x800 +andi x7, x31, -0x800 +andi x8, x31, -0x800 +andi x9, x31, -0x800 +andi x10, x31, -0x800 +andi x11, x31, -0x800 +andi x12, x31, -0x800 +andi x13, x31, -0x800 +andi x14, x31, -0x800 +andi x15, x31, -0x800 +andi x16, x31, -0x800 +andi x17, x31, -0x800 +andi x18, x31, -0x800 +andi x19, x31, -0x800 +andi x20, x31, -0x800 +andi x21, x31, -0x800 +andi x22, x31, -0x800 +andi x23, x31, -0x800 +andi x24, x31, -0x800 +andi x25, x31, -0x800 +andi x26, x31, -0x800 +andi x27, x31, -0x800 +andi x28, x31, -0x800 +andi x29, x31, -0x800 +andi x30, x31, -0x800 +andi x31, x31, -0x800 \ No newline at end of file diff --git a/tb/qumcu/isa/case/Andi_0x10-2048_test/user.sv b/tb/qumcu/isa/case/Andi_0x10-2048_test/user.sv new file mode 100644 index 0000000..3ccb892 --- /dev/null +++ b/tb/qumcu/isa/case/Andi_0x10-2048_test/user.sv @@ -0,0 +1,116 @@ + +wire ram_clk = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CLK; +wire ram_cs = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CEBA; +wire reg_clk = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.clk; +wire reg_en = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_wen; +reg ram_cs_dly1 ; +reg reg_en_dly1 ; +always @(posedge ram_clk) begin + ram_cs_dly1 <= ~ram_cs; + reg_en_dly1 <= reg_en; +end + + +initial begin + #1ns; + //@(posedge ram_cs_dly1 ); + #5ns; + //while(1)begin + #1ns; + //@(posedge reg_en_dly1 ); + REGFILE_CHECK(6'd31,32'h1111_1000); + REGFILE_CHECK(6'd31,32'h1111_1111); + REGFILE_CHECK(6'd30,32'hffff_f000); + REGFILE_CHECK(6'd30,32'hffff_f7ff); + REGFILE_CHECK(6'd30,32'hffff_fffe); + REGFILE_CHECK(6'd30,32'hffff_ffff); + REGFILE_CHECK(6'd1 ,32'h1111_1000); + REGFILE_CHECK(6'd2 ,32'h1111_1000); + REGFILE_CHECK(6'd3 ,32'h1111_1000); + REGFILE_CHECK(6'd4 ,32'h1111_1000); + REGFILE_CHECK(6'd5 ,32'h1111_1000); + REGFILE_CHECK(6'd6 ,32'h1111_1000); + REGFILE_CHECK(6'd7 ,32'h1111_1000); + REGFILE_CHECK(6'd8 ,32'h1111_1000); + REGFILE_CHECK(6'd9 ,32'h1111_1000); + REGFILE_CHECK(6'd10,32'h1111_1000); + REGFILE_CHECK(6'd11,32'h1111_1000); + REGFILE_CHECK(6'd12,32'h1111_1000); + REGFILE_CHECK(6'd13,32'h1111_1000); + REGFILE_CHECK(6'd14,32'h1111_1000); + REGFILE_CHECK(6'd15,32'h1111_1000); + REGFILE_CHECK(6'd16,32'h1111_1000); + REGFILE_CHECK(6'd17,32'h1111_1000); + REGFILE_CHECK(6'd18,32'h1111_1000); + REGFILE_CHECK(6'd19,32'h1111_1000); + REGFILE_CHECK(6'd20,32'h1111_1000); + REGFILE_CHECK(6'd21,32'h1111_1000); + REGFILE_CHECK(6'd22,32'h1111_1000); + REGFILE_CHECK(6'd23,32'h1111_1000); + REGFILE_CHECK(6'd24,32'h1111_1000); + REGFILE_CHECK(6'd25,32'h1111_1000); + REGFILE_CHECK(6'd26,32'h1111_1000); + REGFILE_CHECK(6'd27,32'h1111_1000); + REGFILE_CHECK(6'd28,32'h1111_1000); + REGFILE_CHECK(6'd29,32'h1111_1000); + REGFILE_CHECK(6'd30,32'h1111_1000); + REGFILE_CHECK(6'd31,32'h1111_1000); + #10us; + TEST_PASS; +end + +task DRAM_DATA_CHECK; + input [9:0] addr ; + input [31:0] edata ; + + logic [31:0] ram_data; + + @(posedge ram_cs_dly1 ); + @(posedge ram_clk ); + //$monitor($time, " Simulation time: %t", $time); + if(ram_cs_dly1) begin + ram_data = `TB_DRAM.mem[addr]; + //$display("* RAM_DATA[%x]: %x | EXP_DATA: %x ",addr,ram_data, edata); + if(ram_data !== edata) begin + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,ram_data, edata); + #1us; + TEST_FAIL; + end + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, ram_data, edata); + end + else begin + $display("* DRAM CS is High => Error!!!"); + TEST_FAIL; + end +endtask + +task REGFILE_CHECK; + input [4:0] addr ; + input [31:0] edata ; + + logic [31:0] reg_data; + @(posedge reg_en ); + @(posedge reg_clk); + if(reg_en)begin + reg_data = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_dat; + if(reg_data !== edata) begin + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,reg_data, edata); + #1us; + //TEST_FAIL; + end + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, reg_data, edata); + end + else begin + $display("* REG WR EN is High => Error!!!"); + //TEST_FAIL; + end + +endtask + +initial begin + #100us; + $display("\n----------------------------------------\n"); + $display("\t Timeout Error !!!!\n"); + TEST_FAIL; +end + diff --git a/tb/qumcu/isa/case/Andi_0x10x0_test/main.c b/tb/qumcu/isa/case/Andi_0x10x0_test/main.c new file mode 100644 index 0000000..f92eb3f --- /dev/null +++ b/tb/qumcu/isa/case/Andi_0x10x0_test/main.c @@ -0,0 +1,20 @@ +//#include + + +//int main(){ +// printf("\t=====================================\n"); +// printf("\t hello world !!! \n"); +// printf("\t=====================================\n"); +//} + +void main(void){ + +unsigned int a,b; + a=5; + b=3; + //c=a+b; + //d=c+b; +} + + + diff --git a/tb/qumcu/isa/case/Andi_0x10x0_test/main.s b/tb/qumcu/isa/case/Andi_0x10x0_test/main.s new file mode 100644 index 0000000..54e6dee --- /dev/null +++ b/tb/qumcu/isa/case/Andi_0x10x0_test/main.s @@ -0,0 +1,37 @@ +lui x31, 0x11111 +addi x31, x31, 0x111 +lui x30, 0xfffff +addi x30, x30, 0x7ff +addi x30, x30, 0x7ff +addi x30, x30, 0x1 +andi x1, x31, 0x0 +andi x2, x31, 0x0 +andi x3, x31, 0x0 +andi x4, x31, 0x0 +andi x5, x31, 0x0 +andi x6, x31, 0x0 +andi x7, x31, 0x0 +andi x8, x31, 0x0 +andi x9, x31, 0x0 +andi x10, x31, 0x0 +andi x11, x31, 0x0 +andi x12, x31, 0x0 +andi x13, x31, 0x0 +andi x14, x31, 0x0 +andi x15, x31, 0x0 +andi x16, x31, 0x0 +andi x17, x31, 0x0 +andi x18, x31, 0x0 +andi x19, x31, 0x0 +andi x20, x31, 0x0 +andi x21, x31, 0x0 +andi x22, x31, 0x0 +andi x23, x31, 0x0 +andi x24, x31, 0x0 +andi x25, x31, 0x0 +andi x26, x31, 0x0 +andi x27, x31, 0x0 +andi x28, x31, 0x0 +andi x29, x31, 0x0 +andi x30, x31, 0x0 +andi x31, x31, 0x0 \ No newline at end of file diff --git a/tb/qumcu/isa/case/Andi_0x10x0_test/user.sv b/tb/qumcu/isa/case/Andi_0x10x0_test/user.sv new file mode 100644 index 0000000..275c0c8 --- /dev/null +++ b/tb/qumcu/isa/case/Andi_0x10x0_test/user.sv @@ -0,0 +1,116 @@ + +wire ram_clk = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CLK; +wire ram_cs = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CEBA; +wire reg_clk = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.clk; +wire reg_en = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_wen; +reg ram_cs_dly1 ; +reg reg_en_dly1 ; +always @(posedge ram_clk) begin + ram_cs_dly1 <= ~ram_cs; + reg_en_dly1 <= reg_en; +end + + +initial begin + #1ns; + //@(posedge ram_cs_dly1 ); + #5ns; + //while(1)begin + #1ns; + //@(posedge reg_en_dly1 ); + REGFILE_CHECK(6'd31,32'h1111_1000); + REGFILE_CHECK(6'd31,32'h1111_1111); + REGFILE_CHECK(6'd30,32'hffff_f000); + REGFILE_CHECK(6'd30,32'hffff_f7ff); + REGFILE_CHECK(6'd30,32'hffff_fffe); + REGFILE_CHECK(6'd30,32'hffff_ffff); + REGFILE_CHECK(6'd1 ,32'h0000_0000); + REGFILE_CHECK(6'd2 ,32'h0000_0000); + REGFILE_CHECK(6'd3 ,32'h0000_0000); + REGFILE_CHECK(6'd4 ,32'h0000_0000); + REGFILE_CHECK(6'd5 ,32'h0000_0000); + REGFILE_CHECK(6'd6 ,32'h0000_0000); + REGFILE_CHECK(6'd7 ,32'h0000_0000); + REGFILE_CHECK(6'd8 ,32'h0000_0000); + REGFILE_CHECK(6'd9 ,32'h0000_0000); + REGFILE_CHECK(6'd10,32'h0000_0000); + REGFILE_CHECK(6'd11,32'h0000_0000); + REGFILE_CHECK(6'd12,32'h0000_0000); + REGFILE_CHECK(6'd13,32'h0000_0000); + REGFILE_CHECK(6'd14,32'h0000_0000); + REGFILE_CHECK(6'd15,32'h0000_0000); + REGFILE_CHECK(6'd16,32'h0000_0000); + REGFILE_CHECK(6'd17,32'h0000_0000); + REGFILE_CHECK(6'd18,32'h0000_0000); + REGFILE_CHECK(6'd19,32'h0000_0000); + REGFILE_CHECK(6'd20,32'h0000_0000); + REGFILE_CHECK(6'd21,32'h0000_0000); + REGFILE_CHECK(6'd22,32'h0000_0000); + REGFILE_CHECK(6'd23,32'h0000_0000); + REGFILE_CHECK(6'd24,32'h0000_0000); + REGFILE_CHECK(6'd25,32'h0000_0000); + REGFILE_CHECK(6'd26,32'h0000_0000); + REGFILE_CHECK(6'd27,32'h0000_0000); + REGFILE_CHECK(6'd28,32'h0000_0000); + REGFILE_CHECK(6'd29,32'h0000_0000); + REGFILE_CHECK(6'd30,32'h0000_0000); + REGFILE_CHECK(6'd31,32'h0000_0000); + #10us; + TEST_PASS; +end + +task DRAM_DATA_CHECK; + input [9:0] addr ; + input [31:0] edata ; + + logic [31:0] ram_data; + + @(posedge ram_cs_dly1 ); + @(posedge ram_clk ); + //$monitor($time, " Simulation time: %t", $time); + if(ram_cs_dly1) begin + ram_data = `TB_DRAM.mem[addr]; + //$display("* RAM_DATA[%x]: %x | EXP_DATA: %x ",addr,ram_data, edata); + if(ram_data !== edata) begin + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,ram_data, edata); + #1us; + TEST_FAIL; + end + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, ram_data, edata); + end + else begin + $display("* DRAM CS is High => Error!!!"); + TEST_FAIL; + end +endtask + +task REGFILE_CHECK; + input [4:0] addr ; + input [31:0] edata ; + + logic [31:0] reg_data; + @(posedge reg_en ); + @(posedge reg_clk); + if(reg_en)begin + reg_data = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_dat; + if(reg_data !== edata) begin + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,reg_data, edata); + #1us; + //TEST_FAIL; + end + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, reg_data, edata); + end + else begin + $display("* REG WR EN is High => Error!!!"); + //TEST_FAIL; + end + +endtask + +initial begin + #100us; + $display("\n----------------------------------------\n"); + $display("\t Timeout Error !!!!\n"); + TEST_FAIL; +end + diff --git a/tb/qumcu/isa/case/Andi_0x10x1_test/main.c b/tb/qumcu/isa/case/Andi_0x10x1_test/main.c new file mode 100644 index 0000000..f92eb3f --- /dev/null +++ b/tb/qumcu/isa/case/Andi_0x10x1_test/main.c @@ -0,0 +1,20 @@ +//#include + + +//int main(){ +// printf("\t=====================================\n"); +// printf("\t hello world !!! \n"); +// printf("\t=====================================\n"); +//} + +void main(void){ + +unsigned int a,b; + a=5; + b=3; + //c=a+b; + //d=c+b; +} + + + diff --git a/tb/qumcu/isa/case/Andi_0x10x1_test/main.s b/tb/qumcu/isa/case/Andi_0x10x1_test/main.s new file mode 100644 index 0000000..1f2a71f --- /dev/null +++ b/tb/qumcu/isa/case/Andi_0x10x1_test/main.s @@ -0,0 +1,37 @@ +lui x31, 0x11111 +addi x31, x31, 0x111 +lui x30, 0xfffff +addi x30, x30, 0x7ff +addi x30, x30, 0x7ff +addi x30, x30, 0x1 +andi x1, x31, 0x111 +andi x2, x31, 0x111 +andi x3, x31, 0x111 +andi x4, x31, 0x111 +andi x5, x31, 0x111 +andi x6, x31, 0x111 +andi x7, x31, 0x111 +andi x8, x31, 0x111 +andi x9, x31, 0x111 +andi x10, x31, 0x111 +andi x11, x31, 0x111 +andi x12, x31, 0x111 +andi x13, x31, 0x111 +andi x14, x31, 0x111 +andi x15, x31, 0x111 +andi x16, x31, 0x111 +andi x17, x31, 0x111 +andi x18, x31, 0x111 +andi x19, x31, 0x111 +andi x20, x31, 0x111 +andi x21, x31, 0x111 +andi x22, x31, 0x111 +andi x23, x31, 0x111 +andi x24, x31, 0x111 +andi x25, x31, 0x111 +andi x26, x31, 0x111 +andi x27, x31, 0x111 +andi x28, x31, 0x111 +andi x29, x31, 0x111 +andi x30, x31, 0x111 +andi x31, x31, 0x111 \ No newline at end of file diff --git a/tb/qumcu/isa/case/Andi_0x10x1_test/user.sv b/tb/qumcu/isa/case/Andi_0x10x1_test/user.sv new file mode 100644 index 0000000..bada3cb --- /dev/null +++ b/tb/qumcu/isa/case/Andi_0x10x1_test/user.sv @@ -0,0 +1,116 @@ + +wire ram_clk = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CLK; +wire ram_cs = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CEBA; +wire reg_clk = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.clk; +wire reg_en = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_wen; +reg ram_cs_dly1 ; +reg reg_en_dly1 ; +always @(posedge ram_clk) begin + ram_cs_dly1 <= ~ram_cs; + reg_en_dly1 <= reg_en; +end + + +initial begin + #1ns; + //@(posedge ram_cs_dly1 ); + #5ns; + //while(1)begin + #1ns; + //@(posedge reg_en_dly1 ); + REGFILE_CHECK(6'd31,32'h1111_1000); + REGFILE_CHECK(6'd31,32'h1111_1111); + REGFILE_CHECK(6'd30,32'hffff_f000); + REGFILE_CHECK(6'd30,32'hffff_f7ff); + REGFILE_CHECK(6'd30,32'hffff_fffe); + REGFILE_CHECK(6'd30,32'hffff_ffff); + REGFILE_CHECK(6'd1 ,32'h0000_0111); + REGFILE_CHECK(6'd2 ,32'h0000_0111); + REGFILE_CHECK(6'd3 ,32'h0000_0111); + REGFILE_CHECK(6'd4 ,32'h0000_0111); + REGFILE_CHECK(6'd5 ,32'h0000_0111); + REGFILE_CHECK(6'd6 ,32'h0000_0111); + REGFILE_CHECK(6'd7 ,32'h0000_0111); + REGFILE_CHECK(6'd8 ,32'h0000_0111); + REGFILE_CHECK(6'd9 ,32'h0000_0111); + REGFILE_CHECK(6'd10,32'h0000_0111); + REGFILE_CHECK(6'd11,32'h0000_0111); + REGFILE_CHECK(6'd12,32'h0000_0111); + REGFILE_CHECK(6'd13,32'h0000_0111); + REGFILE_CHECK(6'd14,32'h0000_0111); + REGFILE_CHECK(6'd15,32'h0000_0111); + REGFILE_CHECK(6'd16,32'h0000_0111); + REGFILE_CHECK(6'd17,32'h0000_0111); + REGFILE_CHECK(6'd18,32'h0000_0111); + REGFILE_CHECK(6'd19,32'h0000_0111); + REGFILE_CHECK(6'd20,32'h0000_0111); + REGFILE_CHECK(6'd21,32'h0000_0111); + REGFILE_CHECK(6'd22,32'h0000_0111); + REGFILE_CHECK(6'd23,32'h0000_0111); + REGFILE_CHECK(6'd24,32'h0000_0111); + REGFILE_CHECK(6'd25,32'h0000_0111); + REGFILE_CHECK(6'd26,32'h0000_0111); + REGFILE_CHECK(6'd27,32'h0000_0111); + REGFILE_CHECK(6'd28,32'h0000_0111); + REGFILE_CHECK(6'd29,32'h0000_0111); + REGFILE_CHECK(6'd30,32'h0000_0111); + REGFILE_CHECK(6'd31,32'h0000_0111); + #10us; + TEST_PASS; +end + +task DRAM_DATA_CHECK; + input [9:0] addr ; + input [31:0] edata ; + + logic [31:0] ram_data; + + @(posedge ram_cs_dly1 ); + @(posedge ram_clk ); + //$monitor($time, " Simulation time: %t", $time); + if(ram_cs_dly1) begin + ram_data = `TB_DRAM.mem[addr]; + //$display("* RAM_DATA[%x]: %x | EXP_DATA: %x ",addr,ram_data, edata); + if(ram_data !== edata) begin + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,ram_data, edata); + #1us; + TEST_FAIL; + end + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, ram_data, edata); + end + else begin + $display("* DRAM CS is High => Error!!!"); + TEST_FAIL; + end +endtask + +task REGFILE_CHECK; + input [4:0] addr ; + input [31:0] edata ; + + logic [31:0] reg_data; + @(posedge reg_en ); + @(posedge reg_clk); + if(reg_en)begin + reg_data = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_dat; + if(reg_data !== edata) begin + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,reg_data, edata); + #1us; + //TEST_FAIL; + end + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, reg_data, edata); + end + else begin + $display("* REG WR EN is High => Error!!!"); + //TEST_FAIL; + end + +endtask + +initial begin + #100us; + $display("\n----------------------------------------\n"); + $display("\t Timeout Error !!!!\n"); + TEST_FAIL; +end + diff --git a/tb/qumcu/isa/case/Andi_0x10x7ff_test/main.c b/tb/qumcu/isa/case/Andi_0x10x7ff_test/main.c new file mode 100644 index 0000000..f92eb3f --- /dev/null +++ b/tb/qumcu/isa/case/Andi_0x10x7ff_test/main.c @@ -0,0 +1,20 @@ +//#include + + +//int main(){ +// printf("\t=====================================\n"); +// printf("\t hello world !!! \n"); +// printf("\t=====================================\n"); +//} + +void main(void){ + +unsigned int a,b; + a=5; + b=3; + //c=a+b; + //d=c+b; +} + + + diff --git a/tb/qumcu/isa/case/Andi_0x10x7ff_test/main.s b/tb/qumcu/isa/case/Andi_0x10x7ff_test/main.s new file mode 100644 index 0000000..79279e9 --- /dev/null +++ b/tb/qumcu/isa/case/Andi_0x10x7ff_test/main.s @@ -0,0 +1,37 @@ +lui x31, 0x11111 +addi x31, x31, 0x111 +lui x30, 0xfffff +addi x30, x30, 0x7ff +addi x30, x30, 0x7ff +addi x30, x30, 0x1 +andi x1, x31, 0x7ff +andi x2, x31, 0x7ff +andi x3, x31, 0x7ff +andi x4, x31, 0x7ff +andi x5, x31, 0x7ff +andi x6, x31, 0x7ff +andi x7, x31, 0x7ff +andi x8, x31, 0x7ff +andi x9, x31, 0x7ff +andi x10, x31, 0x7ff +andi x11, x31, 0x7ff +andi x12, x31, 0x7ff +andi x13, x31, 0x7ff +andi x14, x31, 0x7ff +andi x15, x31, 0x7ff +andi x16, x31, 0x7ff +andi x17, x31, 0x7ff +andi x18, x31, 0x7ff +andi x19, x31, 0x7ff +andi x20, x31, 0x7ff +andi x21, x31, 0x7ff +andi x22, x31, 0x7ff +andi x23, x31, 0x7ff +andi x24, x31, 0x7ff +andi x25, x31, 0x7ff +andi x26, x31, 0x7ff +andi x27, x31, 0x7ff +andi x28, x31, 0x7ff +andi x29, x31, 0x7ff +andi x30, x31, 0x7ff +andi x31, x31, 0x7ff \ No newline at end of file diff --git a/tb/qumcu/isa/case/Andi_0x10x7ff_test/user.sv b/tb/qumcu/isa/case/Andi_0x10x7ff_test/user.sv new file mode 100644 index 0000000..bada3cb --- /dev/null +++ b/tb/qumcu/isa/case/Andi_0x10x7ff_test/user.sv @@ -0,0 +1,116 @@ + +wire ram_clk = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CLK; +wire ram_cs = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CEBA; +wire reg_clk = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.clk; +wire reg_en = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_wen; +reg ram_cs_dly1 ; +reg reg_en_dly1 ; +always @(posedge ram_clk) begin + ram_cs_dly1 <= ~ram_cs; + reg_en_dly1 <= reg_en; +end + + +initial begin + #1ns; + //@(posedge ram_cs_dly1 ); + #5ns; + //while(1)begin + #1ns; + //@(posedge reg_en_dly1 ); + REGFILE_CHECK(6'd31,32'h1111_1000); + REGFILE_CHECK(6'd31,32'h1111_1111); + REGFILE_CHECK(6'd30,32'hffff_f000); + REGFILE_CHECK(6'd30,32'hffff_f7ff); + REGFILE_CHECK(6'd30,32'hffff_fffe); + REGFILE_CHECK(6'd30,32'hffff_ffff); + REGFILE_CHECK(6'd1 ,32'h0000_0111); + REGFILE_CHECK(6'd2 ,32'h0000_0111); + REGFILE_CHECK(6'd3 ,32'h0000_0111); + REGFILE_CHECK(6'd4 ,32'h0000_0111); + REGFILE_CHECK(6'd5 ,32'h0000_0111); + REGFILE_CHECK(6'd6 ,32'h0000_0111); + REGFILE_CHECK(6'd7 ,32'h0000_0111); + REGFILE_CHECK(6'd8 ,32'h0000_0111); + REGFILE_CHECK(6'd9 ,32'h0000_0111); + REGFILE_CHECK(6'd10,32'h0000_0111); + REGFILE_CHECK(6'd11,32'h0000_0111); + REGFILE_CHECK(6'd12,32'h0000_0111); + REGFILE_CHECK(6'd13,32'h0000_0111); + REGFILE_CHECK(6'd14,32'h0000_0111); + REGFILE_CHECK(6'd15,32'h0000_0111); + REGFILE_CHECK(6'd16,32'h0000_0111); + REGFILE_CHECK(6'd17,32'h0000_0111); + REGFILE_CHECK(6'd18,32'h0000_0111); + REGFILE_CHECK(6'd19,32'h0000_0111); + REGFILE_CHECK(6'd20,32'h0000_0111); + REGFILE_CHECK(6'd21,32'h0000_0111); + REGFILE_CHECK(6'd22,32'h0000_0111); + REGFILE_CHECK(6'd23,32'h0000_0111); + REGFILE_CHECK(6'd24,32'h0000_0111); + REGFILE_CHECK(6'd25,32'h0000_0111); + REGFILE_CHECK(6'd26,32'h0000_0111); + REGFILE_CHECK(6'd27,32'h0000_0111); + REGFILE_CHECK(6'd28,32'h0000_0111); + REGFILE_CHECK(6'd29,32'h0000_0111); + REGFILE_CHECK(6'd30,32'h0000_0111); + REGFILE_CHECK(6'd31,32'h0000_0111); + #10us; + TEST_PASS; +end + +task DRAM_DATA_CHECK; + input [9:0] addr ; + input [31:0] edata ; + + logic [31:0] ram_data; + + @(posedge ram_cs_dly1 ); + @(posedge ram_clk ); + //$monitor($time, " Simulation time: %t", $time); + if(ram_cs_dly1) begin + ram_data = `TB_DRAM.mem[addr]; + //$display("* RAM_DATA[%x]: %x | EXP_DATA: %x ",addr,ram_data, edata); + if(ram_data !== edata) begin + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,ram_data, edata); + #1us; + TEST_FAIL; + end + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, ram_data, edata); + end + else begin + $display("* DRAM CS is High => Error!!!"); + TEST_FAIL; + end +endtask + +task REGFILE_CHECK; + input [4:0] addr ; + input [31:0] edata ; + + logic [31:0] reg_data; + @(posedge reg_en ); + @(posedge reg_clk); + if(reg_en)begin + reg_data = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_dat; + if(reg_data !== edata) begin + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,reg_data, edata); + #1us; + //TEST_FAIL; + end + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, reg_data, edata); + end + else begin + $display("* REG WR EN is High => Error!!!"); + //TEST_FAIL; + end + +endtask + +initial begin + #100us; + $display("\n----------------------------------------\n"); + $display("\t Timeout Error !!!!\n"); + TEST_FAIL; +end + diff --git a/tb/qumcu/isa/case/Andi_0x50-2048_test/main.c b/tb/qumcu/isa/case/Andi_0x50-2048_test/main.c new file mode 100644 index 0000000..f92eb3f --- /dev/null +++ b/tb/qumcu/isa/case/Andi_0x50-2048_test/main.c @@ -0,0 +1,20 @@ +//#include + + +//int main(){ +// printf("\t=====================================\n"); +// printf("\t hello world !!! \n"); +// printf("\t=====================================\n"); +//} + +void main(void){ + +unsigned int a,b; + a=5; + b=3; + //c=a+b; + //d=c+b; +} + + + diff --git a/tb/qumcu/isa/case/Andi_0x50-2048_test/main.s b/tb/qumcu/isa/case/Andi_0x50-2048_test/main.s new file mode 100644 index 0000000..c45281b --- /dev/null +++ b/tb/qumcu/isa/case/Andi_0x50-2048_test/main.s @@ -0,0 +1,37 @@ +lui x31, 0x55555 +addi x31, x31, 0x555 +lui x30, 0xfffff +addi x30, x30, 0x7ff +addi x30, x30, 0x7ff +addi x30, x30, 0x1 +andi x1, x31, -0x800 +andi x2, x31, -0x800 +andi x3, x31, -0x800 +andi x4, x31, -0x800 +andi x5, x31, -0x800 +andi x6, x31, -0x800 +andi x7, x31, -0x800 +andi x8, x31, -0x800 +andi x9, x31, -0x800 +andi x10, x31, -0x800 +andi x11, x31, -0x800 +andi x12, x31, -0x800 +andi x13, x31, -0x800 +andi x14, x31, -0x800 +andi x15, x31, -0x800 +andi x16, x31, -0x800 +andi x17, x31, -0x800 +andi x18, x31, -0x800 +andi x19, x31, -0x800 +andi x20, x31, -0x800 +andi x21, x31, -0x800 +andi x22, x31, -0x800 +andi x23, x31, -0x800 +andi x24, x31, -0x800 +andi x25, x31, -0x800 +andi x26, x31, -0x800 +andi x27, x31, -0x800 +andi x28, x31, -0x800 +andi x29, x31, -0x800 +andi x30, x31, -0x800 +andi x31, x31, -0x800 \ No newline at end of file diff --git a/tb/qumcu/isa/case/Andi_0x50-2048_test/user.sv b/tb/qumcu/isa/case/Andi_0x50-2048_test/user.sv new file mode 100644 index 0000000..2de1432 --- /dev/null +++ b/tb/qumcu/isa/case/Andi_0x50-2048_test/user.sv @@ -0,0 +1,116 @@ + +wire ram_clk = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CLK; +wire ram_cs = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CEBA; +wire reg_clk = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.clk; +wire reg_en = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_wen; +reg ram_cs_dly1 ; +reg reg_en_dly1 ; +always @(posedge ram_clk) begin + ram_cs_dly1 <= ~ram_cs; + reg_en_dly1 <= reg_en; +end + + +initial begin + #1ns; + //@(posedge ram_cs_dly1 ); + #5ns; + //while(1)begin + #1ns; + //@(posedge reg_en_dly1 ); + REGFILE_CHECK(6'd31,32'h5555_5000); + REGFILE_CHECK(6'd31,32'h5555_5555); + REGFILE_CHECK(6'd30,32'hffff_f000); + REGFILE_CHECK(6'd30,32'hffff_f7ff); + REGFILE_CHECK(6'd30,32'hffff_fffe); + REGFILE_CHECK(6'd30,32'hffff_ffff); + REGFILE_CHECK(6'd1 ,32'h5555_5000); + REGFILE_CHECK(6'd2 ,32'h5555_5000); + REGFILE_CHECK(6'd3 ,32'h5555_5000); + REGFILE_CHECK(6'd4 ,32'h5555_5000); + REGFILE_CHECK(6'd5 ,32'h5555_5000); + REGFILE_CHECK(6'd6 ,32'h5555_5000); + REGFILE_CHECK(6'd7 ,32'h5555_5000); + REGFILE_CHECK(6'd8 ,32'h5555_5000); + REGFILE_CHECK(6'd9 ,32'h5555_5000); + REGFILE_CHECK(6'd10,32'h5555_5000); + REGFILE_CHECK(6'd11,32'h5555_5000); + REGFILE_CHECK(6'd12,32'h5555_5000); + REGFILE_CHECK(6'd13,32'h5555_5000); + REGFILE_CHECK(6'd14,32'h5555_5000); + REGFILE_CHECK(6'd15,32'h5555_5000); + REGFILE_CHECK(6'd16,32'h5555_5000); + REGFILE_CHECK(6'd17,32'h5555_5000); + REGFILE_CHECK(6'd18,32'h5555_5000); + REGFILE_CHECK(6'd19,32'h5555_5000); + REGFILE_CHECK(6'd20,32'h5555_5000); + REGFILE_CHECK(6'd21,32'h5555_5000); + REGFILE_CHECK(6'd22,32'h5555_5000); + REGFILE_CHECK(6'd23,32'h5555_5000); + REGFILE_CHECK(6'd24,32'h5555_5000); + REGFILE_CHECK(6'd25,32'h5555_5000); + REGFILE_CHECK(6'd26,32'h5555_5000); + REGFILE_CHECK(6'd27,32'h5555_5000); + REGFILE_CHECK(6'd28,32'h5555_5000); + REGFILE_CHECK(6'd29,32'h5555_5000); + REGFILE_CHECK(6'd30,32'h5555_5000); + REGFILE_CHECK(6'd31,32'h5555_5000); + #10us; + TEST_PASS; +end + +task DRAM_DATA_CHECK; + input [9:0] addr ; + input [31:0] edata ; + + logic [31:0] ram_data; + + @(posedge ram_cs_dly1 ); + @(posedge ram_clk ); + //$monitor($time, " Simulation time: %t", $time); + if(ram_cs_dly1) begin + ram_data = `TB_DRAM.mem[addr]; + //$display("* RAM_DATA[%x]: %x | EXP_DATA: %x ",addr,ram_data, edata); + if(ram_data !== edata) begin + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,ram_data, edata); + #1us; + TEST_FAIL; + end + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, ram_data, edata); + end + else begin + $display("* DRAM CS is High => Error!!!"); + TEST_FAIL; + end +endtask + +task REGFILE_CHECK; + input [4:0] addr ; + input [31:0] edata ; + + logic [31:0] reg_data; + @(posedge reg_en ); + @(posedge reg_clk); + if(reg_en)begin + reg_data = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_dat; + if(reg_data !== edata) begin + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,reg_data, edata); + #1us; + //TEST_FAIL; + end + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, reg_data, edata); + end + else begin + $display("* REG WR EN is High => Error!!!"); + //TEST_FAIL; + end + +endtask + +initial begin + #100us; + $display("\n----------------------------------------\n"); + $display("\t Timeout Error !!!!\n"); + TEST_FAIL; +end + diff --git a/tb/qumcu/isa/case/Andi_0x50x7ff_test/main.c b/tb/qumcu/isa/case/Andi_0x50x7ff_test/main.c new file mode 100644 index 0000000..f92eb3f --- /dev/null +++ b/tb/qumcu/isa/case/Andi_0x50x7ff_test/main.c @@ -0,0 +1,20 @@ +//#include + + +//int main(){ +// printf("\t=====================================\n"); +// printf("\t hello world !!! \n"); +// printf("\t=====================================\n"); +//} + +void main(void){ + +unsigned int a,b; + a=5; + b=3; + //c=a+b; + //d=c+b; +} + + + diff --git a/tb/qumcu/isa/case/Andi_0x50x7ff_test/main.s b/tb/qumcu/isa/case/Andi_0x50x7ff_test/main.s new file mode 100644 index 0000000..79279e9 --- /dev/null +++ b/tb/qumcu/isa/case/Andi_0x50x7ff_test/main.s @@ -0,0 +1,37 @@ +lui x31, 0x11111 +addi x31, x31, 0x111 +lui x30, 0xfffff +addi x30, x30, 0x7ff +addi x30, x30, 0x7ff +addi x30, x30, 0x1 +andi x1, x31, 0x7ff +andi x2, x31, 0x7ff +andi x3, x31, 0x7ff +andi x4, x31, 0x7ff +andi x5, x31, 0x7ff +andi x6, x31, 0x7ff +andi x7, x31, 0x7ff +andi x8, x31, 0x7ff +andi x9, x31, 0x7ff +andi x10, x31, 0x7ff +andi x11, x31, 0x7ff +andi x12, x31, 0x7ff +andi x13, x31, 0x7ff +andi x14, x31, 0x7ff +andi x15, x31, 0x7ff +andi x16, x31, 0x7ff +andi x17, x31, 0x7ff +andi x18, x31, 0x7ff +andi x19, x31, 0x7ff +andi x20, x31, 0x7ff +andi x21, x31, 0x7ff +andi x22, x31, 0x7ff +andi x23, x31, 0x7ff +andi x24, x31, 0x7ff +andi x25, x31, 0x7ff +andi x26, x31, 0x7ff +andi x27, x31, 0x7ff +andi x28, x31, 0x7ff +andi x29, x31, 0x7ff +andi x30, x31, 0x7ff +andi x31, x31, 0x7ff \ No newline at end of file diff --git a/tb/qumcu/isa/case/Andi_0x50x7ff_test/user.sv b/tb/qumcu/isa/case/Andi_0x50x7ff_test/user.sv new file mode 100644 index 0000000..bada3cb --- /dev/null +++ b/tb/qumcu/isa/case/Andi_0x50x7ff_test/user.sv @@ -0,0 +1,116 @@ + +wire ram_clk = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CLK; +wire ram_cs = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CEBA; +wire reg_clk = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.clk; +wire reg_en = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_wen; +reg ram_cs_dly1 ; +reg reg_en_dly1 ; +always @(posedge ram_clk) begin + ram_cs_dly1 <= ~ram_cs; + reg_en_dly1 <= reg_en; +end + + +initial begin + #1ns; + //@(posedge ram_cs_dly1 ); + #5ns; + //while(1)begin + #1ns; + //@(posedge reg_en_dly1 ); + REGFILE_CHECK(6'd31,32'h1111_1000); + REGFILE_CHECK(6'd31,32'h1111_1111); + REGFILE_CHECK(6'd30,32'hffff_f000); + REGFILE_CHECK(6'd30,32'hffff_f7ff); + REGFILE_CHECK(6'd30,32'hffff_fffe); + REGFILE_CHECK(6'd30,32'hffff_ffff); + REGFILE_CHECK(6'd1 ,32'h0000_0111); + REGFILE_CHECK(6'd2 ,32'h0000_0111); + REGFILE_CHECK(6'd3 ,32'h0000_0111); + REGFILE_CHECK(6'd4 ,32'h0000_0111); + REGFILE_CHECK(6'd5 ,32'h0000_0111); + REGFILE_CHECK(6'd6 ,32'h0000_0111); + REGFILE_CHECK(6'd7 ,32'h0000_0111); + REGFILE_CHECK(6'd8 ,32'h0000_0111); + REGFILE_CHECK(6'd9 ,32'h0000_0111); + REGFILE_CHECK(6'd10,32'h0000_0111); + REGFILE_CHECK(6'd11,32'h0000_0111); + REGFILE_CHECK(6'd12,32'h0000_0111); + REGFILE_CHECK(6'd13,32'h0000_0111); + REGFILE_CHECK(6'd14,32'h0000_0111); + REGFILE_CHECK(6'd15,32'h0000_0111); + REGFILE_CHECK(6'd16,32'h0000_0111); + REGFILE_CHECK(6'd17,32'h0000_0111); + REGFILE_CHECK(6'd18,32'h0000_0111); + REGFILE_CHECK(6'd19,32'h0000_0111); + REGFILE_CHECK(6'd20,32'h0000_0111); + REGFILE_CHECK(6'd21,32'h0000_0111); + REGFILE_CHECK(6'd22,32'h0000_0111); + REGFILE_CHECK(6'd23,32'h0000_0111); + REGFILE_CHECK(6'd24,32'h0000_0111); + REGFILE_CHECK(6'd25,32'h0000_0111); + REGFILE_CHECK(6'd26,32'h0000_0111); + REGFILE_CHECK(6'd27,32'h0000_0111); + REGFILE_CHECK(6'd28,32'h0000_0111); + REGFILE_CHECK(6'd29,32'h0000_0111); + REGFILE_CHECK(6'd30,32'h0000_0111); + REGFILE_CHECK(6'd31,32'h0000_0111); + #10us; + TEST_PASS; +end + +task DRAM_DATA_CHECK; + input [9:0] addr ; + input [31:0] edata ; + + logic [31:0] ram_data; + + @(posedge ram_cs_dly1 ); + @(posedge ram_clk ); + //$monitor($time, " Simulation time: %t", $time); + if(ram_cs_dly1) begin + ram_data = `TB_DRAM.mem[addr]; + //$display("* RAM_DATA[%x]: %x | EXP_DATA: %x ",addr,ram_data, edata); + if(ram_data !== edata) begin + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,ram_data, edata); + #1us; + TEST_FAIL; + end + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, ram_data, edata); + end + else begin + $display("* DRAM CS is High => Error!!!"); + TEST_FAIL; + end +endtask + +task REGFILE_CHECK; + input [4:0] addr ; + input [31:0] edata ; + + logic [31:0] reg_data; + @(posedge reg_en ); + @(posedge reg_clk); + if(reg_en)begin + reg_data = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_dat; + if(reg_data !== edata) begin + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,reg_data, edata); + #1us; + //TEST_FAIL; + end + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, reg_data, edata); + end + else begin + $display("* REG WR EN is High => Error!!!"); + //TEST_FAIL; + end + +endtask + +initial begin + #100us; + $display("\n----------------------------------------\n"); + $display("\t Timeout Error !!!!\n"); + TEST_FAIL; +end + diff --git a/tb/qumcu/isa/case/Andi_0xa0-2048_test/main.c b/tb/qumcu/isa/case/Andi_0xa0-2048_test/main.c new file mode 100644 index 0000000..f92eb3f --- /dev/null +++ b/tb/qumcu/isa/case/Andi_0xa0-2048_test/main.c @@ -0,0 +1,20 @@ +//#include + + +//int main(){ +// printf("\t=====================================\n"); +// printf("\t hello world !!! \n"); +// printf("\t=====================================\n"); +//} + +void main(void){ + +unsigned int a,b; + a=5; + b=3; + //c=a+b; + //d=c+b; +} + + + diff --git a/tb/qumcu/isa/case/Andi_0xa0-2048_test/main.s b/tb/qumcu/isa/case/Andi_0xa0-2048_test/main.s new file mode 100644 index 0000000..6d44d80 --- /dev/null +++ b/tb/qumcu/isa/case/Andi_0xa0-2048_test/main.s @@ -0,0 +1,37 @@ +lui x31, 0x55555 +addi x31, x31, 0x555 +lui x30, 0xaaaaa +addi x30, x30, 0x555 +addi x30, x30, 0x554 +addi x30, x30, 0x1 +andi x1, x30, -0x800 +andi x2, x30, -0x800 +andi x3, x30, -0x800 +andi x4, x30, -0x800 +andi x5, x30, -0x800 +andi x6, x30, -0x800 +andi x7, x30, -0x800 +andi x8, x30, -0x800 +andi x9, x30, -0x800 +andi x10, x30, -0x800 +andi x11, x30, -0x800 +andi x12, x30, -0x800 +andi x13, x30, -0x800 +andi x14, x30, -0x800 +andi x15, x30, -0x800 +andi x16, x30, -0x800 +andi x17, x30, -0x800 +andi x18, x30, -0x800 +andi x19, x30, -0x800 +andi x20, x30, -0x800 +andi x21, x30, -0x800 +andi x22, x30, -0x800 +andi x23, x30, -0x800 +andi x24, x30, -0x800 +andi x25, x30, -0x800 +andi x26, x30, -0x800 +andi x27, x30, -0x800 +andi x28, x30, -0x800 +andi x29, x30, -0x800 +andi x30, x30, -0x800 +andi x31, x30, -0x800 \ No newline at end of file diff --git a/tb/qumcu/isa/case/Andi_0xa0-2048_test/user.sv b/tb/qumcu/isa/case/Andi_0xa0-2048_test/user.sv new file mode 100644 index 0000000..24d2cf7 --- /dev/null +++ b/tb/qumcu/isa/case/Andi_0xa0-2048_test/user.sv @@ -0,0 +1,116 @@ + +wire ram_clk = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CLK; +wire ram_cs = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CEBA; +wire reg_clk = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.clk; +wire reg_en = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_wen; +reg ram_cs_dly1 ; +reg reg_en_dly1 ; +always @(posedge ram_clk) begin + ram_cs_dly1 <= ~ram_cs; + reg_en_dly1 <= reg_en; +end + + +initial begin + #1ns; + //@(posedge ram_cs_dly1 ); + #5ns; + //while(1)begin + #1ns; + //@(posedge reg_en_dly1 ); + REGFILE_CHECK(6'd31,32'h5555_5000); + REGFILE_CHECK(6'd31,32'h5555_5555); + REGFILE_CHECK(6'd30,32'haaaa_a000); + REGFILE_CHECK(6'd30,32'haaaa_a555); + REGFILE_CHECK(6'd30,32'haaaa_aaa9); + REGFILE_CHECK(6'd30,32'haaaa_aaaa); + REGFILE_CHECK(6'd1 ,32'haaaa_a800); + REGFILE_CHECK(6'd2 ,32'haaaa_a800); + REGFILE_CHECK(6'd3 ,32'haaaa_a800); + REGFILE_CHECK(6'd4 ,32'haaaa_a800); + REGFILE_CHECK(6'd5 ,32'haaaa_a800); + REGFILE_CHECK(6'd6 ,32'haaaa_a800); + REGFILE_CHECK(6'd7 ,32'haaaa_a800); + REGFILE_CHECK(6'd8 ,32'haaaa_a800); + REGFILE_CHECK(6'd9 ,32'haaaa_a800); + REGFILE_CHECK(6'd10,32'haaaa_a800); + REGFILE_CHECK(6'd11,32'haaaa_a800); + REGFILE_CHECK(6'd12,32'haaaa_a800); + REGFILE_CHECK(6'd13,32'haaaa_a800); + REGFILE_CHECK(6'd14,32'haaaa_a800); + REGFILE_CHECK(6'd15,32'haaaa_a800); + REGFILE_CHECK(6'd16,32'haaaa_a800); + REGFILE_CHECK(6'd17,32'haaaa_a800); + REGFILE_CHECK(6'd18,32'haaaa_a800); + REGFILE_CHECK(6'd19,32'haaaa_a800); + REGFILE_CHECK(6'd20,32'haaaa_a800); + REGFILE_CHECK(6'd21,32'haaaa_a800); + REGFILE_CHECK(6'd22,32'haaaa_a800); + REGFILE_CHECK(6'd23,32'haaaa_a800); + REGFILE_CHECK(6'd24,32'haaaa_a800); + REGFILE_CHECK(6'd25,32'haaaa_a800); + REGFILE_CHECK(6'd26,32'haaaa_a800); + REGFILE_CHECK(6'd27,32'haaaa_a800); + REGFILE_CHECK(6'd28,32'haaaa_a800); + REGFILE_CHECK(6'd29,32'haaaa_a800); + REGFILE_CHECK(6'd30,32'haaaa_a800); + REGFILE_CHECK(6'd31,32'haaaa_a800); + #10us; + TEST_PASS; +end + +task DRAM_DATA_CHECK; + input [9:0] addr ; + input [31:0] edata ; + + logic [31:0] ram_data; + + @(posedge ram_cs_dly1 ); + @(posedge ram_clk ); + //$monitor($time, " Simulation time: %t", $time); + if(ram_cs_dly1) begin + ram_data = `TB_DRAM.mem[addr]; + //$display("* RAM_DATA[%x]: %x | EXP_DATA: %x ",addr,ram_data, edata); + if(ram_data !== edata) begin + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,ram_data, edata); + #1us; + TEST_FAIL; + end + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, ram_data, edata); + end + else begin + $display("* DRAM CS is High => Error!!!"); + TEST_FAIL; + end +endtask + +task REGFILE_CHECK; + input [4:0] addr ; + input [31:0] edata ; + + logic [31:0] reg_data; + @(posedge reg_en ); + @(posedge reg_clk); + if(reg_en)begin + reg_data = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_dat; + if(reg_data !== edata) begin + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,reg_data, edata); + #1us; + //TEST_FAIL; + end + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, reg_data, edata); + end + else begin + $display("* REG WR EN is High => Error!!!"); + //TEST_FAIL; + end + +endtask + +initial begin + #100us; + $display("\n----------------------------------------\n"); + $display("\t Timeout Error !!!!\n"); + TEST_FAIL; +end + diff --git a/tb/qumcu/isa/case/Andi_0xa0x7ff_test/main.c b/tb/qumcu/isa/case/Andi_0xa0x7ff_test/main.c new file mode 100644 index 0000000..f92eb3f --- /dev/null +++ b/tb/qumcu/isa/case/Andi_0xa0x7ff_test/main.c @@ -0,0 +1,20 @@ +//#include + + +//int main(){ +// printf("\t=====================================\n"); +// printf("\t hello world !!! \n"); +// printf("\t=====================================\n"); +//} + +void main(void){ + +unsigned int a,b; + a=5; + b=3; + //c=a+b; + //d=c+b; +} + + + diff --git a/tb/qumcu/isa/case/Andi_0xa0x7ff_test/main.s b/tb/qumcu/isa/case/Andi_0xa0x7ff_test/main.s new file mode 100644 index 0000000..205d93a --- /dev/null +++ b/tb/qumcu/isa/case/Andi_0xa0x7ff_test/main.s @@ -0,0 +1,37 @@ +lui x31, 0x11111 +addi x31, x31, 0x111 +lui x30, 0xaaaaa +addi x30, x30, 0x555 +addi x30, x30, 0x555 +addi x30, x30, 0x0 +andi x1, x30, 0x7ff +andi x2, x30, 0x7ff +andi x3, x30, 0x7ff +andi x4, x30, 0x7ff +andi x5, x30, 0x7ff +andi x6, x30, 0x7ff +andi x7, x30, 0x7ff +andi x8, x30, 0x7ff +andi x9, x30, 0x7ff +andi x10, x30, 0x7ff +andi x11, x30, 0x7ff +andi x12, x30, 0x7ff +andi x13, x30, 0x7ff +andi x14, x30, 0x7ff +andi x15, x30, 0x7ff +andi x16, x30, 0x7ff +andi x17, x30, 0x7ff +andi x18, x30, 0x7ff +andi x19, x30, 0x7ff +andi x20, x30, 0x7ff +andi x21, x30, 0x7ff +andi x22, x30, 0x7ff +andi x23, x30, 0x7ff +andi x24, x30, 0x7ff +andi x25, x30, 0x7ff +andi x26, x30, 0x7ff +andi x27, x30, 0x7ff +andi x28, x30, 0x7ff +andi x29, x30, 0x7ff +andi x30, x30, 0x7ff +andi x31, x30, 0x7ff \ No newline at end of file diff --git a/tb/qumcu/isa/case/Andi_0xa0x7ff_test/user.sv b/tb/qumcu/isa/case/Andi_0xa0x7ff_test/user.sv new file mode 100644 index 0000000..6f5297e --- /dev/null +++ b/tb/qumcu/isa/case/Andi_0xa0x7ff_test/user.sv @@ -0,0 +1,116 @@ + +wire ram_clk = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CLK; +wire ram_cs = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CEBA; +wire reg_clk = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.clk; +wire reg_en = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_wen; +reg ram_cs_dly1 ; +reg reg_en_dly1 ; +always @(posedge ram_clk) begin + ram_cs_dly1 <= ~ram_cs; + reg_en_dly1 <= reg_en; +end + + +initial begin + #1ns; + //@(posedge ram_cs_dly1 ); + #5ns; + //while(1)begin + #1ns; + //@(posedge reg_en_dly1 ); + REGFILE_CHECK(6'd31,32'h1111_1000); + REGFILE_CHECK(6'd31,32'h1111_1111); + REGFILE_CHECK(6'd30,32'haaaa_a000); + REGFILE_CHECK(6'd30,32'haaaa_a555); + REGFILE_CHECK(6'd30,32'haaaa_aaaa); + REGFILE_CHECK(6'd30,32'haaaa_aaaa); + REGFILE_CHECK(6'd1 ,32'h0000_02aa); + REGFILE_CHECK(6'd2 ,32'h0000_02aa); + REGFILE_CHECK(6'd3 ,32'h0000_02aa); + REGFILE_CHECK(6'd4 ,32'h0000_02aa); + REGFILE_CHECK(6'd5 ,32'h0000_02aa); + REGFILE_CHECK(6'd6 ,32'h0000_02aa); + REGFILE_CHECK(6'd7 ,32'h0000_02aa); + REGFILE_CHECK(6'd8 ,32'h0000_02aa); + REGFILE_CHECK(6'd9 ,32'h0000_02aa); + REGFILE_CHECK(6'd10,32'h0000_02aa); + REGFILE_CHECK(6'd11,32'h0000_02aa); + REGFILE_CHECK(6'd12,32'h0000_02aa); + REGFILE_CHECK(6'd13,32'h0000_02aa); + REGFILE_CHECK(6'd14,32'h0000_02aa); + REGFILE_CHECK(6'd15,32'h0000_02aa); + REGFILE_CHECK(6'd16,32'h0000_02aa); + REGFILE_CHECK(6'd17,32'h0000_02aa); + REGFILE_CHECK(6'd18,32'h0000_02aa); + REGFILE_CHECK(6'd19,32'h0000_02aa); + REGFILE_CHECK(6'd20,32'h0000_02aa); + REGFILE_CHECK(6'd21,32'h0000_02aa); + REGFILE_CHECK(6'd22,32'h0000_02aa); + REGFILE_CHECK(6'd23,32'h0000_02aa); + REGFILE_CHECK(6'd24,32'h0000_02aa); + REGFILE_CHECK(6'd25,32'h0000_02aa); + REGFILE_CHECK(6'd26,32'h0000_02aa); + REGFILE_CHECK(6'd27,32'h0000_02aa); + REGFILE_CHECK(6'd28,32'h0000_02aa); + REGFILE_CHECK(6'd29,32'h0000_02aa); + REGFILE_CHECK(6'd30,32'h0000_02aa); + REGFILE_CHECK(6'd31,32'h0000_02aa); + #10us; + TEST_PASS; +end + +task DRAM_DATA_CHECK; + input [9:0] addr ; + input [31:0] edata ; + + logic [31:0] ram_data; + + @(posedge ram_cs_dly1 ); + @(posedge ram_clk ); + //$monitor($time, " Simulation time: %t", $time); + if(ram_cs_dly1) begin + ram_data = `TB_DRAM.mem[addr]; + //$display("* RAM_DATA[%x]: %x | EXP_DATA: %x ",addr,ram_data, edata); + if(ram_data !== edata) begin + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,ram_data, edata); + #1us; + TEST_FAIL; + end + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, ram_data, edata); + end + else begin + $display("* DRAM CS is High => Error!!!"); + TEST_FAIL; + end +endtask + +task REGFILE_CHECK; + input [4:0] addr ; + input [31:0] edata ; + + logic [31:0] reg_data; + @(posedge reg_en ); + @(posedge reg_clk); + if(reg_en)begin + reg_data = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_dat; + if(reg_data !== edata) begin + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,reg_data, edata); + #1us; + //TEST_FAIL; + end + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, reg_data, edata); + end + else begin + $display("* REG WR EN is High => Error!!!"); + //TEST_FAIL; + end + +endtask + +initial begin + #100us; + $display("\n----------------------------------------\n"); + $display("\t Timeout Error !!!!\n"); + TEST_FAIL; +end + diff --git a/tb/qumcu/isa/case/Andi_0xf0-2048_test/main.c b/tb/qumcu/isa/case/Andi_0xf0-2048_test/main.c new file mode 100644 index 0000000..f92eb3f --- /dev/null +++ b/tb/qumcu/isa/case/Andi_0xf0-2048_test/main.c @@ -0,0 +1,20 @@ +//#include + + +//int main(){ +// printf("\t=====================================\n"); +// printf("\t hello world !!! \n"); +// printf("\t=====================================\n"); +//} + +void main(void){ + +unsigned int a,b; + a=5; + b=3; + //c=a+b; + //d=c+b; +} + + + diff --git a/tb/qumcu/isa/case/Andi_0xf0-2048_test/main.s b/tb/qumcu/isa/case/Andi_0xf0-2048_test/main.s new file mode 100644 index 0000000..653393b --- /dev/null +++ b/tb/qumcu/isa/case/Andi_0xf0-2048_test/main.s @@ -0,0 +1,37 @@ +lui x31, 0x55555 +addi x31, x31, 0x555 +lui x30, 0xfffff +addi x30, x30, 0x7ff +addi x30, x30, 0x7ff +addi x30, x30, 0x1 +andi x1, x30, -0x800 +andi x2, x30, -0x800 +andi x3, x30, -0x800 +andi x4, x30, -0x800 +andi x5, x30, -0x800 +andi x6, x30, -0x800 +andi x7, x30, -0x800 +andi x8, x30, -0x800 +andi x9, x30, -0x800 +andi x10, x30, -0x800 +andi x11, x30, -0x800 +andi x12, x30, -0x800 +andi x13, x30, -0x800 +andi x14, x30, -0x800 +andi x15, x30, -0x800 +andi x16, x30, -0x800 +andi x17, x30, -0x800 +andi x18, x30, -0x800 +andi x19, x30, -0x800 +andi x20, x30, -0x800 +andi x21, x30, -0x800 +andi x22, x30, -0x800 +andi x23, x30, -0x800 +andi x24, x30, -0x800 +andi x25, x30, -0x800 +andi x26, x30, -0x800 +andi x27, x30, -0x800 +andi x28, x30, -0x800 +andi x29, x30, -0x800 +andi x30, x30, -0x800 +andi x31, x30, -0x800 \ No newline at end of file diff --git a/tb/qumcu/isa/case/Andi_0xf0-2048_test/user.sv b/tb/qumcu/isa/case/Andi_0xf0-2048_test/user.sv new file mode 100644 index 0000000..afaba5c --- /dev/null +++ b/tb/qumcu/isa/case/Andi_0xf0-2048_test/user.sv @@ -0,0 +1,116 @@ + +wire ram_clk = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CLK; +wire ram_cs = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CEBA; +wire reg_clk = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.clk; +wire reg_en = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_wen; +reg ram_cs_dly1 ; +reg reg_en_dly1 ; +always @(posedge ram_clk) begin + ram_cs_dly1 <= ~ram_cs; + reg_en_dly1 <= reg_en; +end + + +initial begin + #1ns; + //@(posedge ram_cs_dly1 ); + #5ns; + //while(1)begin + #1ns; + //@(posedge reg_en_dly1 ); + REGFILE_CHECK(6'd31,32'h5555_5000); + REGFILE_CHECK(6'd31,32'h5555_5555); + REGFILE_CHECK(6'd30,32'hffff_f000); + REGFILE_CHECK(6'd30,32'hffff_f7ff); + REGFILE_CHECK(6'd30,32'hffff_fffe); + REGFILE_CHECK(6'd30,32'hffff_ffff); + REGFILE_CHECK(6'd1 ,32'hffff_f800); + REGFILE_CHECK(6'd2 ,32'hffff_f800); + REGFILE_CHECK(6'd3 ,32'hffff_f800); + REGFILE_CHECK(6'd4 ,32'hffff_f800); + REGFILE_CHECK(6'd5 ,32'hffff_f800); + REGFILE_CHECK(6'd6 ,32'hffff_f800); + REGFILE_CHECK(6'd7 ,32'hffff_f800); + REGFILE_CHECK(6'd8 ,32'hffff_f800); + REGFILE_CHECK(6'd9 ,32'hffff_f800); + REGFILE_CHECK(6'd10,32'hffff_f800); + REGFILE_CHECK(6'd11,32'hffff_f800); + REGFILE_CHECK(6'd12,32'hffff_f800); + REGFILE_CHECK(6'd13,32'hffff_f800); + REGFILE_CHECK(6'd14,32'hffff_f800); + REGFILE_CHECK(6'd15,32'hffff_f800); + REGFILE_CHECK(6'd16,32'hffff_f800); + REGFILE_CHECK(6'd17,32'hffff_f800); + REGFILE_CHECK(6'd18,32'hffff_f800); + REGFILE_CHECK(6'd19,32'hffff_f800); + REGFILE_CHECK(6'd20,32'hffff_f800); + REGFILE_CHECK(6'd21,32'hffff_f800); + REGFILE_CHECK(6'd22,32'hffff_f800); + REGFILE_CHECK(6'd23,32'hffff_f800); + REGFILE_CHECK(6'd24,32'hffff_f800); + REGFILE_CHECK(6'd25,32'hffff_f800); + REGFILE_CHECK(6'd26,32'hffff_f800); + REGFILE_CHECK(6'd27,32'hffff_f800); + REGFILE_CHECK(6'd28,32'hffff_f800); + REGFILE_CHECK(6'd29,32'hffff_f800); + REGFILE_CHECK(6'd30,32'hffff_f800); + REGFILE_CHECK(6'd31,32'hffff_f800); + #10us; + TEST_PASS; +end + +task DRAM_DATA_CHECK; + input [9:0] addr ; + input [31:0] edata ; + + logic [31:0] ram_data; + + @(posedge ram_cs_dly1 ); + @(posedge ram_clk ); + //$monitor($time, " Simulation time: %t", $time); + if(ram_cs_dly1) begin + ram_data = `TB_DRAM.mem[addr]; + //$display("* RAM_DATA[%x]: %x | EXP_DATA: %x ",addr,ram_data, edata); + if(ram_data !== edata) begin + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,ram_data, edata); + #1us; + TEST_FAIL; + end + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, ram_data, edata); + end + else begin + $display("* DRAM CS is High => Error!!!"); + TEST_FAIL; + end +endtask + +task REGFILE_CHECK; + input [4:0] addr ; + input [31:0] edata ; + + logic [31:0] reg_data; + @(posedge reg_en ); + @(posedge reg_clk); + if(reg_en)begin + reg_data = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_dat; + if(reg_data !== edata) begin + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,reg_data, edata); + #1us; + //TEST_FAIL; + end + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, reg_data, edata); + end + else begin + $display("* REG WR EN is High => Error!!!"); + //TEST_FAIL; + end + +endtask + +initial begin + #100us; + $display("\n----------------------------------------\n"); + $display("\t Timeout Error !!!!\n"); + TEST_FAIL; +end + diff --git a/tb/qumcu/isa/case/Andi_0xf0x7ff_test/main.c b/tb/qumcu/isa/case/Andi_0xf0x7ff_test/main.c new file mode 100644 index 0000000..f92eb3f --- /dev/null +++ b/tb/qumcu/isa/case/Andi_0xf0x7ff_test/main.c @@ -0,0 +1,20 @@ +//#include + + +//int main(){ +// printf("\t=====================================\n"); +// printf("\t hello world !!! \n"); +// printf("\t=====================================\n"); +//} + +void main(void){ + +unsigned int a,b; + a=5; + b=3; + //c=a+b; + //d=c+b; +} + + + diff --git a/tb/qumcu/isa/case/Andi_0xf0x7ff_test/main.s b/tb/qumcu/isa/case/Andi_0xf0x7ff_test/main.s new file mode 100644 index 0000000..7420d1a --- /dev/null +++ b/tb/qumcu/isa/case/Andi_0xf0x7ff_test/main.s @@ -0,0 +1,20 @@ +.global main +main: +addi x1,x0,0x5 +addi x2,x0,0x4 +lui x3,0x50 + +jalr x1,x0,string1 +lui x4,0x60 +string1: +jalr x2,x0,string2 +lui x5,0x70 +lui x6,0x80 +string2: +jalr x3,x0,string3 +lui x5,0x77 +lui x6,0x88 +string3: +lui x5,0x99 +lui x6,0xaa +exit: \ No newline at end of file diff --git a/tb/qumcu/isa/case/Andi_0xf0x7ff_test/user.sv b/tb/qumcu/isa/case/Andi_0xf0x7ff_test/user.sv new file mode 100644 index 0000000..acb5026 --- /dev/null +++ b/tb/qumcu/isa/case/Andi_0xf0x7ff_test/user.sv @@ -0,0 +1,116 @@ + +wire ram_clk = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CLK; +wire ram_cs = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CEBA; +wire reg_clk = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.clk; +wire reg_en = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_wen; +reg ram_cs_dly1 ; +reg reg_en_dly1 ; +always @(posedge ram_clk) begin + ram_cs_dly1 <= ~ram_cs; + reg_en_dly1 <= reg_en; +end + + +initial begin + #1ns; + //@(posedge ram_cs_dly1 ); + #5ns; + //while(1)begin + #1ns; + //@(posedge reg_en_dly1 ); + REGFILE_CHECK(6'd31,32'h1111_1000); + REGFILE_CHECK(6'd31,32'h1111_1111); + REGFILE_CHECK(6'd30,32'hffff_f000); + REGFILE_CHECK(6'd30,32'hffff_f7ff); + REGFILE_CHECK(6'd30,32'hffff_fffe); + REGFILE_CHECK(6'd30,32'hffff_ffff); + REGFILE_CHECK(6'd1 ,32'h0000_07ff); + REGFILE_CHECK(6'd2 ,32'h0000_07ff); + REGFILE_CHECK(6'd3 ,32'h0000_07ff); + REGFILE_CHECK(6'd4 ,32'h0000_07ff); + REGFILE_CHECK(6'd5 ,32'h0000_07ff); + REGFILE_CHECK(6'd6 ,32'h0000_07ff); + REGFILE_CHECK(6'd7 ,32'h0000_07ff); + REGFILE_CHECK(6'd8 ,32'h0000_07ff); + REGFILE_CHECK(6'd9 ,32'h0000_07ff); + REGFILE_CHECK(6'd10,32'h0000_07ff); + REGFILE_CHECK(6'd11,32'h0000_07ff); + REGFILE_CHECK(6'd12,32'h0000_07ff); + REGFILE_CHECK(6'd13,32'h0000_07ff); + REGFILE_CHECK(6'd14,32'h0000_07ff); + REGFILE_CHECK(6'd15,32'h0000_07ff); + REGFILE_CHECK(6'd16,32'h0000_07ff); + REGFILE_CHECK(6'd17,32'h0000_07ff); + REGFILE_CHECK(6'd18,32'h0000_07ff); + REGFILE_CHECK(6'd19,32'h0000_07ff); + REGFILE_CHECK(6'd20,32'h0000_07ff); + REGFILE_CHECK(6'd21,32'h0000_07ff); + REGFILE_CHECK(6'd22,32'h0000_07ff); + REGFILE_CHECK(6'd23,32'h0000_07ff); + REGFILE_CHECK(6'd24,32'h0000_07ff); + REGFILE_CHECK(6'd25,32'h0000_07ff); + REGFILE_CHECK(6'd26,32'h0000_07ff); + REGFILE_CHECK(6'd27,32'h0000_07ff); + REGFILE_CHECK(6'd28,32'h0000_07ff); + REGFILE_CHECK(6'd29,32'h0000_07ff); + REGFILE_CHECK(6'd30,32'h0000_07ff); + REGFILE_CHECK(6'd31,32'h0000_07ff); + #10us; + TEST_PASS; +end + +task DRAM_DATA_CHECK; + input [9:0] addr ; + input [31:0] edata ; + + logic [31:0] ram_data; + + @(posedge ram_cs_dly1 ); + @(posedge ram_clk ); + //$monitor($time, " Simulation time: %t", $time); + if(ram_cs_dly1) begin + ram_data = `TB_DRAM.mem[addr]; + //$display("* RAM_DATA[%x]: %x | EXP_DATA: %x ",addr,ram_data, edata); + if(ram_data !== edata) begin + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,ram_data, edata); + #1us; + TEST_FAIL; + end + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, ram_data, edata); + end + else begin + $display("* DRAM CS is High => Error!!!"); + TEST_FAIL; + end +endtask + +task REGFILE_CHECK; + input [4:0] addr ; + input [31:0] edata ; + + logic [31:0] reg_data; + @(posedge reg_en ); + @(posedge reg_clk); + if(reg_en)begin + reg_data = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_dat; + if(reg_data !== edata) begin + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,reg_data, edata); + #1us; + //TEST_FAIL; + end + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, reg_data, edata); + end + else begin + $display("* REG WR EN is High => Error!!!"); + //TEST_FAIL; + end + +endtask + +initial begin + #100us; + $display("\n----------------------------------------\n"); + $display("\t Timeout Error !!!!\n"); + TEST_FAIL; +end + diff --git a/tb/qumcu/isa/case/Auipc_0x0_test/main.c b/tb/qumcu/isa/case/Auipc_0x0_test/main.c new file mode 100644 index 0000000..f92eb3f --- /dev/null +++ b/tb/qumcu/isa/case/Auipc_0x0_test/main.c @@ -0,0 +1,20 @@ +//#include + + +//int main(){ +// printf("\t=====================================\n"); +// printf("\t hello world !!! \n"); +// printf("\t=====================================\n"); +//} + +void main(void){ + +unsigned int a,b; + a=5; + b=3; + //c=a+b; + //d=c+b; +} + + + diff --git a/tb/qumcu/isa/case/Auipc_0x0_test/main.s b/tb/qumcu/isa/case/Auipc_0x0_test/main.s new file mode 100644 index 0000000..3c43c53 --- /dev/null +++ b/tb/qumcu/isa/case/Auipc_0x0_test/main.s @@ -0,0 +1,124 @@ +auipc x1, 0x0 +auipc x1, 0x0 +auipc x1, 0x0 +auipc x1, 0x0 +auipc x2, 0x0 +auipc x2, 0x0 +auipc x2, 0x0 +auipc x2, 0x0 +auipc x3, 0x0 +auipc x3, 0x0 +auipc x3, 0x0 +auipc x3, 0x0 +auipc x4, 0x0 +auipc x4, 0x0 +auipc x4, 0x0 +auipc x4, 0x0 +auipc x5, 0x0 +auipc x5, 0x0 +auipc x5, 0x0 +auipc x5, 0x0 +auipc x6, 0x0 +auipc x6, 0x0 +auipc x6, 0x0 +auipc x6, 0x0 +auipc x7, 0x0 +auipc x7, 0x0 +auipc x7, 0x0 +auipc x7, 0x0 +auipc x8, 0x0 +auipc x8, 0x0 +auipc x8, 0x0 +auipc x8, 0x0 +auipc x9, 0x0 +auipc x9, 0x0 +auipc x9, 0x0 +auipc x9, 0x0 +auipc x10,0x0 +auipc x10,0x0 +auipc x10,0x0 +auipc x10,0x0 +auipc x11,0x0 +auipc x11,0x0 +auipc x11,0x0 +auipc x11,0x0 +auipc x12,0x0 +auipc x12,0x0 +auipc x12,0x0 +auipc x12,0x0 +auipc x13,0x0 +auipc x13,0x0 +auipc x13,0x0 +auipc x13,0x0 +auipc x14,0x0 +auipc x14,0x0 +auipc x14,0x0 +auipc x14,0x0 +auipc x15,0x0 +auipc x15,0x0 +auipc x15,0x0 +auipc x15,0x0 +auipc x16,0x0 +auipc x16,0x0 +auipc x16,0x0 +auipc x16,0x0 +auipc x17,0x0 +auipc x17,0x0 +auipc x17,0x0 +auipc x17,0x0 +auipc x18,0x0 +auipc x18,0x0 +auipc x18,0x0 +auipc x18,0x0 +auipc x19,0x0 +auipc x19,0x0 +auipc x19,0x0 +auipc x19,0x0 +auipc x20,0x0 +auipc x20,0x0 +auipc x20,0x0 +auipc x20,0x0 +auipc x21,0x0 +auipc x21,0x0 +auipc x21,0x0 +auipc x21,0x0 +auipc x22,0x0 +auipc x22,0x0 +auipc x22,0x0 +auipc x22,0x0 +auipc x23,0x0 +auipc x23,0x0 +auipc x23,0x0 +auipc x23,0x0 +auipc x24,0x0 +auipc x24,0x0 +auipc x24,0x0 +auipc x24,0x0 +auipc x25,0x0 +auipc x25,0x0 +auipc x25,0x0 +auipc x25,0x0 +auipc x26,0x0 +auipc x26,0x0 +auipc x26,0x0 +auipc x26,0x0 +auipc x27,0x0 +auipc x27,0x0 +auipc x27,0x0 +auipc x27,0x0 +auipc x28,0x0 +auipc x28,0x0 +auipc x28,0x0 +auipc x28,0x0 +auipc x29,0x0 +auipc x29,0x0 +auipc x29,0x0 +auipc x29,0x0 +auipc x30,0x0 +auipc x30,0x0 +auipc x30,0x0 +auipc x30,0x0 +auipc x31,0x0 +auipc x31,0x0 +auipc x31,0x0 +auipc x31,0x0 \ No newline at end of file diff --git a/tb/qumcu/isa/case/Auipc_0x0_test/user.sv b/tb/qumcu/isa/case/Auipc_0x0_test/user.sv new file mode 100644 index 0000000..245c9eb --- /dev/null +++ b/tb/qumcu/isa/case/Auipc_0x0_test/user.sv @@ -0,0 +1,203 @@ + +wire ram_clk = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CLK; +wire ram_cs = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CEBA; +wire reg_clk = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.clk; +wire reg_en = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_wen; +reg ram_cs_dly1 ; +reg reg_en_dly1 ; +always @(posedge ram_clk) begin + ram_cs_dly1 <= ~ram_cs; + reg_en_dly1 <= reg_en; +end + + +initial begin + #1ns; + //@(posedge ram_cs_dly1 ); + #5ns; + //while(1)begin + #1ns; + //@(posedge reg_en_dly1 ); + REGFILE_CHECK(6'd1 ,32'h0000_0000); + REGFILE_CHECK(6'd1 ,32'h0000_0004); + REGFILE_CHECK(6'd1 ,32'h0000_0008); + REGFILE_CHECK(6'd1 ,32'h0000_000c); + REGFILE_CHECK(6'd2 ,32'h0000_0010); + REGFILE_CHECK(6'd2 ,32'h0000_0014); + REGFILE_CHECK(6'd2 ,32'h0000_0018); + REGFILE_CHECK(6'd2 ,32'h0000_001c); + REGFILE_CHECK(6'd3 ,32'h0000_0020); + REGFILE_CHECK(6'd3 ,32'h0000_0024); + REGFILE_CHECK(6'd3 ,32'h0000_0028); + REGFILE_CHECK(6'd3 ,32'h0000_002c); + REGFILE_CHECK(6'd4 ,32'h0000_0030); + REGFILE_CHECK(6'd4 ,32'h0000_0034); + REGFILE_CHECK(6'd4 ,32'h0000_0038); + REGFILE_CHECK(6'd4 ,32'h0000_003c); + REGFILE_CHECK(6'd5 ,32'h0000_0040); + REGFILE_CHECK(6'd5 ,32'h0000_0044); + REGFILE_CHECK(6'd5 ,32'h0000_0048); + REGFILE_CHECK(6'd5 ,32'h0000_004c); + REGFILE_CHECK(6'd6 ,32'h0000_0050); + REGFILE_CHECK(6'd6 ,32'h0000_0054); + REGFILE_CHECK(6'd6 ,32'h0000_0058); + REGFILE_CHECK(6'd6 ,32'h0000_005c); + REGFILE_CHECK(6'd7 ,32'h0000_0060); + REGFILE_CHECK(6'd7 ,32'h0000_0064); + REGFILE_CHECK(6'd7 ,32'h0000_0068); + REGFILE_CHECK(6'd7 ,32'h0000_006c); + REGFILE_CHECK(6'd8 ,32'h0000_0070); + REGFILE_CHECK(6'd8 ,32'h0000_0074); + REGFILE_CHECK(6'd8 ,32'h0000_0078); + REGFILE_CHECK(6'd8 ,32'h0000_007c); + REGFILE_CHECK(6'd9 ,32'h0000_0080); + REGFILE_CHECK(6'd9 ,32'h0000_0084); + REGFILE_CHECK(6'd9 ,32'h0000_0088); + REGFILE_CHECK(6'd9 ,32'h0000_008c); + REGFILE_CHECK(6'd10,32'h0000_0090); + REGFILE_CHECK(6'd10,32'h0000_0094); + REGFILE_CHECK(6'd10,32'h0000_0098); + REGFILE_CHECK(6'd10,32'h0000_009c); + REGFILE_CHECK(6'd11,32'h0000_00a0); + REGFILE_CHECK(6'd11,32'h0000_00a4); + REGFILE_CHECK(6'd11,32'h0000_00a8); + REGFILE_CHECK(6'd11,32'h0000_00ac); + REGFILE_CHECK(6'd12,32'h0000_00b0); + REGFILE_CHECK(6'd12,32'h0000_00b4); + REGFILE_CHECK(6'd12,32'h0000_00b8); + REGFILE_CHECK(6'd12,32'h0000_00bc); + REGFILE_CHECK(6'd13,32'h0000_00c0); + REGFILE_CHECK(6'd13,32'h0000_00c4); + REGFILE_CHECK(6'd13,32'h0000_00c8); + REGFILE_CHECK(6'd13,32'h0000_00cc); + REGFILE_CHECK(6'd14,32'h0000_00d0); + REGFILE_CHECK(6'd14,32'h0000_00d4); + REGFILE_CHECK(6'd14,32'h0000_00d8); + REGFILE_CHECK(6'd14,32'h0000_00dc); + REGFILE_CHECK(6'd15,32'h0000_00e0); + REGFILE_CHECK(6'd15,32'h0000_00e4); + REGFILE_CHECK(6'd15,32'h0000_00e8); + REGFILE_CHECK(6'd15,32'h0000_00ec); + REGFILE_CHECK(6'd16,32'h0000_00f0); + REGFILE_CHECK(6'd16,32'h0000_00f4); + REGFILE_CHECK(6'd16,32'h0000_00f8); + REGFILE_CHECK(6'd16,32'h0000_00fc); + REGFILE_CHECK(6'd17,32'h0000_0100); + REGFILE_CHECK(6'd17,32'h0000_0104); + REGFILE_CHECK(6'd17,32'h0000_0108); + REGFILE_CHECK(6'd17,32'h0000_010c); + REGFILE_CHECK(6'd18,32'h0000_0110); + REGFILE_CHECK(6'd18,32'h0000_0114); + REGFILE_CHECK(6'd18,32'h0000_0118); + REGFILE_CHECK(6'd18,32'h0000_011c); + REGFILE_CHECK(6'd19,32'h0000_0120); + REGFILE_CHECK(6'd19,32'h0000_0124); + REGFILE_CHECK(6'd19,32'h0000_0128); + REGFILE_CHECK(6'd19,32'h0000_012c); + REGFILE_CHECK(6'd20,32'h0000_0130); + REGFILE_CHECK(6'd20,32'h0000_0134); + REGFILE_CHECK(6'd20,32'h0000_0138); + REGFILE_CHECK(6'd20,32'h0000_013c); + REGFILE_CHECK(6'd21,32'h0000_0140); + REGFILE_CHECK(6'd21,32'h0000_0144); + REGFILE_CHECK(6'd21,32'h0000_0148); + REGFILE_CHECK(6'd21,32'h0000_014c); + REGFILE_CHECK(6'd22,32'h0000_0150); + REGFILE_CHECK(6'd22,32'h0000_0154); + REGFILE_CHECK(6'd22,32'h0000_0158); + REGFILE_CHECK(6'd22,32'h0000_015c); + REGFILE_CHECK(6'd23,32'h0000_0160); + REGFILE_CHECK(6'd23,32'h0000_0164); + REGFILE_CHECK(6'd23,32'h0000_0168); + REGFILE_CHECK(6'd23,32'h0000_016c); + REGFILE_CHECK(6'd24,32'h0000_0170); + REGFILE_CHECK(6'd24,32'h0000_0174); + REGFILE_CHECK(6'd24,32'h0000_0178); + REGFILE_CHECK(6'd24,32'h0000_017c); + REGFILE_CHECK(6'd25,32'h0000_0180); + REGFILE_CHECK(6'd25,32'h0000_0184); + REGFILE_CHECK(6'd25,32'h0000_0188); + REGFILE_CHECK(6'd25,32'h0000_018c); + REGFILE_CHECK(6'd26,32'h0000_0190); + REGFILE_CHECK(6'd26,32'h0000_0194); + REGFILE_CHECK(6'd26,32'h0000_0198); + REGFILE_CHECK(6'd26,32'h0000_019c); + REGFILE_CHECK(6'd27,32'h0000_01a0); + REGFILE_CHECK(6'd27,32'h0000_01a4); + REGFILE_CHECK(6'd27,32'h0000_01a8); + REGFILE_CHECK(6'd27,32'h0000_01ac); + REGFILE_CHECK(6'd28,32'h0000_01b0); + REGFILE_CHECK(6'd28,32'h0000_01b4); + REGFILE_CHECK(6'd28,32'h0000_01b8); + REGFILE_CHECK(6'd28,32'h0000_01bc); + REGFILE_CHECK(6'd29,32'h0000_01c0); + REGFILE_CHECK(6'd29,32'h0000_01c4); + REGFILE_CHECK(6'd29,32'h0000_01c8); + REGFILE_CHECK(6'd29,32'h0000_01cc); + REGFILE_CHECK(6'd30,32'h0000_01d0); + REGFILE_CHECK(6'd30,32'h0000_01d4); + REGFILE_CHECK(6'd30,32'h0000_01d8); + REGFILE_CHECK(6'd30,32'h0000_01dc); + REGFILE_CHECK(6'd31,32'h0000_01e0); + REGFILE_CHECK(6'd31,32'h0000_01e4); + REGFILE_CHECK(6'd31,32'h0000_01e8); + REGFILE_CHECK(6'd31,32'h0000_01ec); + #10us; + TEST_PASS; +end + +task DRAM_DATA_CHECK; + input [9:0] addr ; + input [31:0] edata ; + + logic [31:0] ram_data; + + @(posedge ram_cs_dly1 ); + @(posedge ram_clk ); + //$monitor($time, " Simulation time: %t", $time); + if(ram_cs_dly1) begin + ram_data = `TB_DRAM.mem[addr]; + //$display("* RAM_DATA[%x]: %x | EXP_DATA: %x ",addr,ram_data, edata); + if(ram_data !== edata) begin + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,ram_data, edata); + #1us; + TEST_FAIL; + end + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, ram_data, edata); + end + else begin + $display("* DRAM CS is High => Error!!!"); + TEST_FAIL; + end +endtask + +task REGFILE_CHECK; + input [4:0] addr ; + input [31:0] edata ; + + logic [31:0] reg_data; + @(posedge reg_en ); + @(posedge reg_clk); + if(reg_en)begin + reg_data = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_dat; + if(reg_data !== edata) begin + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,reg_data, edata); + #1us; + //TEST_FAIL; + end + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, reg_data, edata); + end + else begin + $display("* REG WR EN is High => Error!!!"); + //TEST_FAIL; + end + +endtask + +initial begin + #100us; + $display("\n----------------------------------------\n"); + $display("\t Timeout Error !!!!\n"); + TEST_FAIL; +end + diff --git a/tb/qumcu/isa/case/Auipc_0x1_test/main.c b/tb/qumcu/isa/case/Auipc_0x1_test/main.c new file mode 100644 index 0000000..f92eb3f --- /dev/null +++ b/tb/qumcu/isa/case/Auipc_0x1_test/main.c @@ -0,0 +1,20 @@ +//#include + + +//int main(){ +// printf("\t=====================================\n"); +// printf("\t hello world !!! \n"); +// printf("\t=====================================\n"); +//} + +void main(void){ + +unsigned int a,b; + a=5; + b=3; + //c=a+b; + //d=c+b; +} + + + diff --git a/tb/qumcu/isa/case/Auipc_0x1_test/main.s b/tb/qumcu/isa/case/Auipc_0x1_test/main.s new file mode 100644 index 0000000..97a437f --- /dev/null +++ b/tb/qumcu/isa/case/Auipc_0x1_test/main.s @@ -0,0 +1,125 @@ +auipc x1,0x1 +auipc x1,0x1 +auipc x1,0x1 +auipc x1,0x1 +auipc x2,0x1 +auipc x2,0x1 +auipc x2,0x1 +auipc x2,0x1 +auipc x3,0x1 +auipc x3,0x1 +auipc x3,0x1 +auipc x3,0x1 +auipc x4,0x1 +auipc x4,0x1 +auipc x4,0x1 +auipc x4,0x1 +auipc x5,0x1 +auipc x5,0x1 +auipc x5,0x1 +auipc x5,0x1 +auipc x6,0x1 +auipc x6,0x1 +auipc x6,0x1 +auipc x6,0x1 +auipc x7,0x1 +auipc x7,0x1 +auipc x7,0x1 +auipc x7,0x1 +auipc x8,0x1 +auipc x8,0x1 +auipc x8,0x1 +auipc x8,0x1 +auipc x9,0x1 +auipc x9,0x1 +auipc x9,0x1 +auipc x9,0x1 +auipc x10,0x1 +auipc x10,0x1 +auipc x10,0x1 +auipc x10,0x1 +auipc x11,0x1 +auipc x11,0x1 +auipc x11,0x1 +auipc x11,0x1 +auipc x12,0x1 +auipc x12,0x1 +auipc x12,0x1 +auipc x12,0x1 +auipc x13,0x1 +auipc x13,0x1 +auipc x13,0x1 +auipc x13,0x1 +auipc x14,0x1 +auipc x14,0x1 +auipc x14,0x1 +auipc x14,0x1 +auipc x15,0x1 +auipc x15,0x1 +auipc x15,0x1 +auipc x15,0x1 +auipc x16,0x1 +auipc x16,0x1 +auipc x16,0x1 +auipc x16,0x1 +auipc x17,0x1 +auipc x17,0x1 +auipc x17,0x1 +auipc x17,0x1 +auipc x18,0x1 +auipc x18,0x1 +auipc x18,0x1 +auipc x18,0x1 +auipc x19,0x1 +auipc x19,0x1 +auipc x19,0x1 +auipc x19,0x1 +auipc x20,0x1 +auipc x20,0x1 +auipc x20,0x1 +auipc x20,0x1 +auipc x21,0x1 +auipc x21,0x1 +auipc x21,0x1 +auipc x21,0x1 +auipc x22,0x1 +auipc x22,0x1 +auipc x22,0x1 +auipc x22,0x1 +auipc x23,0x1 +auipc x23,0x1 +auipc x23,0x1 +auipc x23,0x1 +auipc x24,0x1 +auipc x24,0x1 +auipc x24,0x1 +auipc x24,0x1 +auipc x25,0x1 +auipc x25,0x1 +auipc x25,0x1 +auipc x25,0x1 +auipc x26,0x1 +auipc x26,0x1 +auipc x26,0x1 +auipc x26,0x1 +auipc x27,0x1 +auipc x27,0x1 +auipc x27,0x1 +auipc x27,0x1 +auipc x28,0x1 +auipc x28,0x1 +auipc x28,0x1 +auipc x28,0x1 +auipc x29,0x1 +auipc x29,0x1 +auipc x29,0x1 +auipc x29,0x1 +auipc x30,0x1 +auipc x30,0x1 +auipc x30,0x1 +auipc x30,0x1 +auipc x29,0x1 +auipc x31,0x1 +auipc x31,0x1 +auipc x31,0x1 +auipc x31,0x1 \ No newline at end of file diff --git a/tb/qumcu/isa/case/Auipc_0x1_test/user.sv b/tb/qumcu/isa/case/Auipc_0x1_test/user.sv new file mode 100644 index 0000000..dee9896 --- /dev/null +++ b/tb/qumcu/isa/case/Auipc_0x1_test/user.sv @@ -0,0 +1,203 @@ + +wire ram_clk = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CLK; +wire ram_cs = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CEBA; +wire reg_clk = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.clk; +wire reg_en = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_wen; +reg ram_cs_dly1 ; +reg reg_en_dly1 ; +always @(posedge ram_clk) begin + ram_cs_dly1 <= ~ram_cs; + reg_en_dly1 <= reg_en; +end + + +initial begin + #1ns; + //@(posedge ram_cs_dly1 ); + #5ns; + //while(1)begin + #1ns; + //@(posedge reg_en_dly1 ); + REGFILE_CHECK(6'd1,32'h0000_1000); + REGFILE_CHECK(6'd1,32'h0000_1004); + REGFILE_CHECK(6'd1,32'h0000_1008); + REGFILE_CHECK(6'd1,32'h0000_100c); + REGFILE_CHECK(6'd2,32'h0000_1010); + REGFILE_CHECK(6'd2,32'h0000_1014); + REGFILE_CHECK(6'd2,32'h0000_1018); + REGFILE_CHECK(6'd2,32'h0000_101c); + REGFILE_CHECK(6'd3,32'h0000_1020); + REGFILE_CHECK(6'd3,32'h0000_1024); + REGFILE_CHECK(6'd3,32'h0000_1028); + REGFILE_CHECK(6'd3,32'h0000_102c); + REGFILE_CHECK(6'd4,32'h0000_1030); + REGFILE_CHECK(6'd4,32'h0000_1034); + REGFILE_CHECK(6'd4,32'h0000_1038); + REGFILE_CHECK(6'd4,32'h0000_103c); + REGFILE_CHECK(6'd5,32'h0000_1040); + REGFILE_CHECK(6'd5,32'h0000_1044); + REGFILE_CHECK(6'd5,32'h0000_1048); + REGFILE_CHECK(6'd5,32'h0000_104c); + REGFILE_CHECK(6'd6,32'h0000_1050); + REGFILE_CHECK(6'd6,32'h0000_1054); + REGFILE_CHECK(6'd6,32'h0000_1058); + REGFILE_CHECK(6'd6,32'h0000_105c); + REGFILE_CHECK(6'd7,32'h0000_1060); + REGFILE_CHECK(6'd7,32'h0000_1064); + REGFILE_CHECK(6'd7,32'h0000_1068); + REGFILE_CHECK(6'd7,32'h0000_106c); + REGFILE_CHECK(6'd8,32'h0000_1070); + REGFILE_CHECK(6'd8,32'h0000_1074); + REGFILE_CHECK(6'd8,32'h0000_1078); + REGFILE_CHECK(6'd8,32'h0000_107c); + REGFILE_CHECK(6'd9,32'h0000_1080); + REGFILE_CHECK(6'd9,32'h0000_1084); + REGFILE_CHECK(6'd9,32'h0000_1088); + REGFILE_CHECK(6'd9,32'h0000_108c); + REGFILE_CHECK(6'd10,32'h0000_1090); + REGFILE_CHECK(6'd10,32'h0000_1094); + REGFILE_CHECK(6'd10,32'h0000_1098); + REGFILE_CHECK(6'd10,32'h0000_109c); + REGFILE_CHECK(6'd11,32'h0000_10a0); + REGFILE_CHECK(6'd11,32'h0000_10a4); + REGFILE_CHECK(6'd11,32'h0000_10a8); + REGFILE_CHECK(6'd11,32'h0000_10ac); + REGFILE_CHECK(6'd12,32'h0000_10b0); + REGFILE_CHECK(6'd12,32'h0000_10b4); + REGFILE_CHECK(6'd12,32'h0000_10b8); + REGFILE_CHECK(6'd12,32'h0000_10bc); + REGFILE_CHECK(6'd13,32'h0000_10c0); + REGFILE_CHECK(6'd13,32'h0000_10c4); + REGFILE_CHECK(6'd13,32'h0000_10c8); + REGFILE_CHECK(6'd13,32'h0000_10cc); + REGFILE_CHECK(6'd14,32'h0000_10d0); + REGFILE_CHECK(6'd14,32'h0000_10d4); + REGFILE_CHECK(6'd14,32'h0000_10d8); + REGFILE_CHECK(6'd14,32'h0000_10dc); + REGFILE_CHECK(6'd15,32'h0000_10e0); + REGFILE_CHECK(6'd15,32'h0000_10e4); + REGFILE_CHECK(6'd15,32'h0000_10e8); + REGFILE_CHECK(6'd15,32'h0000_10ec); + REGFILE_CHECK(6'd16,32'h0000_10f0); + REGFILE_CHECK(6'd16,32'h0000_10f4); + REGFILE_CHECK(6'd16,32'h0000_10f8); + REGFILE_CHECK(6'd16,32'h0000_10fc); + REGFILE_CHECK(6'd17,32'h0000_1100); + REGFILE_CHECK(6'd17,32'h0000_1104); + REGFILE_CHECK(6'd17,32'h0000_1108); + REGFILE_CHECK(6'd17,32'h0000_110c); + REGFILE_CHECK(6'd18,32'h0000_1110); + REGFILE_CHECK(6'd18,32'h0000_1114); + REGFILE_CHECK(6'd18,32'h0000_1118); + REGFILE_CHECK(6'd18,32'h0000_111c); + REGFILE_CHECK(6'd19,32'h0000_1120); + REGFILE_CHECK(6'd19,32'h0000_1124); + REGFILE_CHECK(6'd19,32'h0000_1128); + REGFILE_CHECK(6'd19,32'h0000_112c); + REGFILE_CHECK(6'd20,32'h0000_1130); + REGFILE_CHECK(6'd20,32'h0000_1134); + REGFILE_CHECK(6'd20,32'h0000_1138); + REGFILE_CHECK(6'd20,32'h0000_113c); + REGFILE_CHECK(6'd21,32'h0000_1140); + REGFILE_CHECK(6'd21,32'h0000_1144); + REGFILE_CHECK(6'd21,32'h0000_1148); + REGFILE_CHECK(6'd21,32'h0000_114c); + REGFILE_CHECK(6'd22,32'h0000_1150); + REGFILE_CHECK(6'd22,32'h0000_1154); + REGFILE_CHECK(6'd22,32'h0000_1158); + REGFILE_CHECK(6'd22,32'h0000_115c); + REGFILE_CHECK(6'd23,32'h0000_1160); + REGFILE_CHECK(6'd23,32'h0000_1164); + REGFILE_CHECK(6'd23,32'h0000_1168); + REGFILE_CHECK(6'd23,32'h0000_116c); + REGFILE_CHECK(6'd24,32'h0000_1170); + REGFILE_CHECK(6'd24,32'h0000_1174); + REGFILE_CHECK(6'd24,32'h0000_1178); + REGFILE_CHECK(6'd24,32'h0000_117c); + REGFILE_CHECK(6'd25,32'h0000_1180); + REGFILE_CHECK(6'd25,32'h0000_1184); + REGFILE_CHECK(6'd25,32'h0000_1188); + REGFILE_CHECK(6'd25,32'h0000_118c); + REGFILE_CHECK(6'd26,32'h0000_1190); + REGFILE_CHECK(6'd26,32'h0000_1194); + REGFILE_CHECK(6'd26,32'h0000_1198); + REGFILE_CHECK(6'd26,32'h0000_119c); + REGFILE_CHECK(6'd27,32'h0000_11a0); + REGFILE_CHECK(6'd27,32'h0000_11a4); + REGFILE_CHECK(6'd27,32'h0000_11a8); + REGFILE_CHECK(6'd27,32'h0000_11ac); + REGFILE_CHECK(6'd28,32'h0000_11b0); + REGFILE_CHECK(6'd28,32'h0000_11b4); + REGFILE_CHECK(6'd28,32'h0000_11b8); + REGFILE_CHECK(6'd28,32'h0000_11bc); + REGFILE_CHECK(6'd29,32'h0000_11c0); + REGFILE_CHECK(6'd29,32'h0000_11c4); + REGFILE_CHECK(6'd29,32'h0000_11c8); + REGFILE_CHECK(6'd29,32'h0000_11cc); + REGFILE_CHECK(6'd30,32'h0000_11d0); + REGFILE_CHECK(6'd30,32'h0000_11d4); + REGFILE_CHECK(6'd30,32'h0000_11d8); + REGFILE_CHECK(6'd30,32'h0000_11dc); + REGFILE_CHECK(6'd31,32'h0000_11e0); + REGFILE_CHECK(6'd31,32'h0000_11e4); + REGFILE_CHECK(6'd31,32'h0000_11e8); + REGFILE_CHECK(6'd31,32'h0000_11ec); + #10us; + TEST_PASS; +end + +task DRAM_DATA_CHECK; + input [9:0] addr ; + input [31:0] edata ; + + logic [31:0] ram_data; + + @(posedge ram_cs_dly1 ); + @(posedge ram_clk ); + //$monitor($time, " Simulation time: %t", $time); + if(ram_cs_dly1) begin + ram_data = `TB_DRAM.mem[addr]; + //$display("* RAM_DATA[%x]: %x | EXP_DATA: %x ",addr,ram_data, edata); + if(ram_data !== edata) begin + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,ram_data, edata); + #1us; + TEST_FAIL; + end + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, ram_data, edata); + end + else begin + $display("* DRAM CS is High => Error!!!"); + TEST_FAIL; + end +endtask + +task REGFILE_CHECK; + input [4:0] addr ; + input [31:0] edata ; + + logic [31:0] reg_data; + @(posedge reg_en ); + @(posedge reg_clk); + if(reg_en)begin + reg_data = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_dat; + if(reg_data !== edata) begin + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,reg_data, edata); + #1us; + //TEST_FAIL; + end + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, reg_data, edata); + end + else begin + $display("* REG WR EN is High => Error!!!"); + //TEST_FAIL; + end + +endtask + +initial begin + #100us; + $display("\n----------------------------------------\n"); + $display("\t Timeout Error !!!!\n"); + TEST_FAIL; +end + diff --git a/tb/qumcu/isa/case/Auipc_0x55555_test/main.c b/tb/qumcu/isa/case/Auipc_0x55555_test/main.c new file mode 100644 index 0000000..f92eb3f --- /dev/null +++ b/tb/qumcu/isa/case/Auipc_0x55555_test/main.c @@ -0,0 +1,20 @@ +//#include + + +//int main(){ +// printf("\t=====================================\n"); +// printf("\t hello world !!! \n"); +// printf("\t=====================================\n"); +//} + +void main(void){ + +unsigned int a,b; + a=5; + b=3; + //c=a+b; + //d=c+b; +} + + + diff --git a/tb/qumcu/isa/case/Auipc_0x55555_test/main.s b/tb/qumcu/isa/case/Auipc_0x55555_test/main.s new file mode 100644 index 0000000..81be95c --- /dev/null +++ b/tb/qumcu/isa/case/Auipc_0x55555_test/main.s @@ -0,0 +1,124 @@ +auipc x1, 0x55555 +auipc x1, 0x55555 +auipc x1, 0x55555 +auipc x1, 0x55555 +auipc x2, 0x55555 +auipc x2, 0x55555 +auipc x2, 0x55555 +auipc x2, 0x55555 +auipc x3, 0x55555 +auipc x3, 0x55555 +auipc x3, 0x55555 +auipc x3, 0x55555 +auipc x4, 0x55555 +auipc x4, 0x55555 +auipc x4, 0x55555 +auipc x4, 0x55555 +auipc x5, 0x55555 +auipc x5, 0x55555 +auipc x5, 0x55555 +auipc x5, 0x55555 +auipc x6, 0x55555 +auipc x6, 0x55555 +auipc x6, 0x55555 +auipc x6, 0x55555 +auipc x7, 0x55555 +auipc x7, 0x55555 +auipc x7, 0x55555 +auipc x7, 0x55555 +auipc x8, 0x55555 +auipc x8, 0x55555 +auipc x8, 0x55555 +auipc x8, 0x55555 +auipc x9, 0x55555 +auipc x9, 0x55555 +auipc x9, 0x55555 +auipc x9, 0x55555 +auipc x10,0x55555 +auipc x10,0x55555 +auipc x10,0x55555 +auipc x10,0x55555 +auipc x11,0x55555 +auipc x11,0x55555 +auipc x11,0x55555 +auipc x11,0x55555 +auipc x12,0x55555 +auipc x12,0x55555 +auipc x12,0x55555 +auipc x12,0x55555 +auipc x13,0x55555 +auipc x13,0x55555 +auipc x13,0x55555 +auipc x13,0x55555 +auipc x14,0x55555 +auipc x14,0x55555 +auipc x14,0x55555 +auipc x14,0x55555 +auipc x15,0x55555 +auipc x15,0x55555 +auipc x15,0x55555 +auipc x15,0x55555 +auipc x16,0x55555 +auipc x16,0x55555 +auipc x16,0x55555 +auipc x16,0x55555 +auipc x17,0x55555 +auipc x17,0x55555 +auipc x17,0x55555 +auipc x17,0x55555 +auipc x18,0x55555 +auipc x18,0x55555 +auipc x18,0x55555 +auipc x18,0x55555 +auipc x19,0x55555 +auipc x19,0x55555 +auipc x19,0x55555 +auipc x19,0x55555 +auipc x20,0x55555 +auipc x20,0x55555 +auipc x20,0x55555 +auipc x20,0x55555 +auipc x21,0x55555 +auipc x21,0x55555 +auipc x21,0x55555 +auipc x21,0x55555 +auipc x22,0x55555 +auipc x22,0x55555 +auipc x22,0x55555 +auipc x22,0x55555 +auipc x23,0x55555 +auipc x23,0x55555 +auipc x23,0x55555 +auipc x23,0x55555 +auipc x24,0x55555 +auipc x24,0x55555 +auipc x24,0x55555 +auipc x24,0x55555 +auipc x25,0x55555 +auipc x25,0x55555 +auipc x25,0x55555 +auipc x25,0x55555 +auipc x26,0x55555 +auipc x26,0x55555 +auipc x26,0x55555 +auipc x26,0x55555 +auipc x27,0x55555 +auipc x27,0x55555 +auipc x27,0x55555 +auipc x27,0x55555 +auipc x28,0x55555 +auipc x28,0x55555 +auipc x28,0x55555 +auipc x28,0x55555 +auipc x29,0x55555 +auipc x29,0x55555 +auipc x29,0x55555 +auipc x29,0x55555 +auipc x30,0x55555 +auipc x30,0x55555 +auipc x30,0x55555 +auipc x30,0x55555 +auipc x31,0x55555 +auipc x31,0x55555 +auipc x31,0x55555 +auipc x31,0x55555 \ No newline at end of file diff --git a/tb/qumcu/isa/case/Auipc_0x55555_test/user.sv b/tb/qumcu/isa/case/Auipc_0x55555_test/user.sv new file mode 100644 index 0000000..ea0ec8f --- /dev/null +++ b/tb/qumcu/isa/case/Auipc_0x55555_test/user.sv @@ -0,0 +1,203 @@ + +wire ram_clk = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CLK; +wire ram_cs = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CEBA; +wire reg_clk = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.clk; +wire reg_en = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_wen; +reg ram_cs_dly1 ; +reg reg_en_dly1 ; +always @(posedge ram_clk) begin + ram_cs_dly1 <= ~ram_cs; + reg_en_dly1 <= reg_en; +end + + +initial begin + #1ns; + //@(posedge ram_cs_dly1 ); + #5ns; + //while(1)begin + #1ns; + //@(posedge reg_en_dly1 ); + REGFILE_CHECK(6'd1 ,32'h5555_5000); + REGFILE_CHECK(6'd1 ,32'h5555_5004); + REGFILE_CHECK(6'd1 ,32'h5555_5008); + REGFILE_CHECK(6'd1 ,32'h5555_500c); + REGFILE_CHECK(6'd2 ,32'h5555_5010); + REGFILE_CHECK(6'd2 ,32'h5555_5014); + REGFILE_CHECK(6'd2 ,32'h5555_5018); + REGFILE_CHECK(6'd2 ,32'h5555_501c); + REGFILE_CHECK(6'd3 ,32'h5555_5020); + REGFILE_CHECK(6'd3 ,32'h5555_5024); + REGFILE_CHECK(6'd3 ,32'h5555_5028); + REGFILE_CHECK(6'd3 ,32'h5555_502c); + REGFILE_CHECK(6'd4 ,32'h5555_5030); + REGFILE_CHECK(6'd4 ,32'h5555_5034); + REGFILE_CHECK(6'd4 ,32'h5555_5038); + REGFILE_CHECK(6'd4 ,32'h5555_503c); + REGFILE_CHECK(6'd5 ,32'h5555_5040); + REGFILE_CHECK(6'd5 ,32'h5555_5044); + REGFILE_CHECK(6'd5 ,32'h5555_5048); + REGFILE_CHECK(6'd5 ,32'h5555_504c); + REGFILE_CHECK(6'd6 ,32'h5555_5050); + REGFILE_CHECK(6'd6 ,32'h5555_5054); + REGFILE_CHECK(6'd6 ,32'h5555_5058); + REGFILE_CHECK(6'd6 ,32'h5555_505c); + REGFILE_CHECK(6'd7 ,32'h5555_5060); + REGFILE_CHECK(6'd7 ,32'h5555_5064); + REGFILE_CHECK(6'd7 ,32'h5555_5068); + REGFILE_CHECK(6'd7 ,32'h5555_506c); + REGFILE_CHECK(6'd8 ,32'h5555_5070); + REGFILE_CHECK(6'd8 ,32'h5555_5074); + REGFILE_CHECK(6'd8 ,32'h5555_5078); + REGFILE_CHECK(6'd8 ,32'h5555_507c); + REGFILE_CHECK(6'd9 ,32'h5555_5080); + REGFILE_CHECK(6'd9 ,32'h5555_5084); + REGFILE_CHECK(6'd9 ,32'h5555_5088); + REGFILE_CHECK(6'd9 ,32'h5555_508c); + REGFILE_CHECK(6'd10,32'h5555_5090); + REGFILE_CHECK(6'd10,32'h5555_5094); + REGFILE_CHECK(6'd10,32'h5555_5098); + REGFILE_CHECK(6'd10,32'h5555_509c); + REGFILE_CHECK(6'd11,32'h5555_50a0); + REGFILE_CHECK(6'd11,32'h5555_50a4); + REGFILE_CHECK(6'd11,32'h5555_50a8); + REGFILE_CHECK(6'd11,32'h5555_50ac); + REGFILE_CHECK(6'd12,32'h5555_50b0); + REGFILE_CHECK(6'd12,32'h5555_50b4); + REGFILE_CHECK(6'd12,32'h5555_50b8); + REGFILE_CHECK(6'd12,32'h5555_50bc); + REGFILE_CHECK(6'd13,32'h5555_50c0); + REGFILE_CHECK(6'd13,32'h5555_50c4); + REGFILE_CHECK(6'd13,32'h5555_50c8); + REGFILE_CHECK(6'd13,32'h5555_50cc); + REGFILE_CHECK(6'd14,32'h5555_50d0); + REGFILE_CHECK(6'd14,32'h5555_50d4); + REGFILE_CHECK(6'd14,32'h5555_50d8); + REGFILE_CHECK(6'd14,32'h5555_50dc); + REGFILE_CHECK(6'd15,32'h5555_50e0); + REGFILE_CHECK(6'd15,32'h5555_50e4); + REGFILE_CHECK(6'd15,32'h5555_50e8); + REGFILE_CHECK(6'd15,32'h5555_50ec); + REGFILE_CHECK(6'd16,32'h5555_50f0); + REGFILE_CHECK(6'd16,32'h5555_50f4); + REGFILE_CHECK(6'd16,32'h5555_50f8); + REGFILE_CHECK(6'd16,32'h5555_50fc); + REGFILE_CHECK(6'd17,32'h5555_5100); + REGFILE_CHECK(6'd17,32'h5555_5104); + REGFILE_CHECK(6'd17,32'h5555_5108); + REGFILE_CHECK(6'd17,32'h5555_510c); + REGFILE_CHECK(6'd18,32'h5555_5110); + REGFILE_CHECK(6'd18,32'h5555_5114); + REGFILE_CHECK(6'd18,32'h5555_5118); + REGFILE_CHECK(6'd18,32'h5555_511c); + REGFILE_CHECK(6'd19,32'h5555_5120); + REGFILE_CHECK(6'd19,32'h5555_5124); + REGFILE_CHECK(6'd19,32'h5555_5128); + REGFILE_CHECK(6'd19,32'h5555_512c); + REGFILE_CHECK(6'd20,32'h5555_5130); + REGFILE_CHECK(6'd20,32'h5555_5134); + REGFILE_CHECK(6'd20,32'h5555_5138); + REGFILE_CHECK(6'd20,32'h5555_513c); + REGFILE_CHECK(6'd21,32'h5555_5140); + REGFILE_CHECK(6'd21,32'h5555_5144); + REGFILE_CHECK(6'd21,32'h5555_5148); + REGFILE_CHECK(6'd21,32'h5555_514c); + REGFILE_CHECK(6'd22,32'h5555_5150); + REGFILE_CHECK(6'd22,32'h5555_5154); + REGFILE_CHECK(6'd22,32'h5555_5158); + REGFILE_CHECK(6'd22,32'h5555_515c); + REGFILE_CHECK(6'd23,32'h5555_5160); + REGFILE_CHECK(6'd23,32'h5555_5164); + REGFILE_CHECK(6'd23,32'h5555_5168); + REGFILE_CHECK(6'd23,32'h5555_516c); + REGFILE_CHECK(6'd24,32'h5555_5170); + REGFILE_CHECK(6'd24,32'h5555_5174); + REGFILE_CHECK(6'd24,32'h5555_5178); + REGFILE_CHECK(6'd24,32'h5555_517c); + REGFILE_CHECK(6'd25,32'h5555_5180); + REGFILE_CHECK(6'd25,32'h5555_5184); + REGFILE_CHECK(6'd25,32'h5555_5188); + REGFILE_CHECK(6'd25,32'h5555_518c); + REGFILE_CHECK(6'd26,32'h5555_5190); + REGFILE_CHECK(6'd26,32'h5555_5194); + REGFILE_CHECK(6'd26,32'h5555_5198); + REGFILE_CHECK(6'd26,32'h5555_519c); + REGFILE_CHECK(6'd27,32'h5555_51a0); + REGFILE_CHECK(6'd27,32'h5555_51a4); + REGFILE_CHECK(6'd27,32'h5555_51a8); + REGFILE_CHECK(6'd27,32'h5555_51ac); + REGFILE_CHECK(6'd28,32'h5555_51b0); + REGFILE_CHECK(6'd28,32'h5555_51b4); + REGFILE_CHECK(6'd28,32'h5555_51b8); + REGFILE_CHECK(6'd28,32'h5555_51bc); + REGFILE_CHECK(6'd29,32'h5555_51c0); + REGFILE_CHECK(6'd29,32'h5555_51c4); + REGFILE_CHECK(6'd29,32'h5555_51c8); + REGFILE_CHECK(6'd29,32'h5555_51cc); + REGFILE_CHECK(6'd30,32'h5555_51d0); + REGFILE_CHECK(6'd30,32'h5555_51d4); + REGFILE_CHECK(6'd30,32'h5555_51d8); + REGFILE_CHECK(6'd30,32'h5555_51dc); + REGFILE_CHECK(6'd31,32'h5555_51e0); + REGFILE_CHECK(6'd31,32'h5555_51e4); + REGFILE_CHECK(6'd31,32'h5555_51e8); + REGFILE_CHECK(6'd31,32'h5555_51ec); + #10us; + TEST_PASS; +end + +task DRAM_DATA_CHECK; + input [9:0] addr ; + input [31:0] edata ; + + logic [31:0] ram_data; + + @(posedge ram_cs_dly1 ); + @(posedge ram_clk ); + //$monitor($time, " Simulation time: %t", $time); + if(ram_cs_dly1) begin + ram_data = `TB_DRAM.mem[addr]; + //$display("* RAM_DATA[%x]: %x | EXP_DATA: %x ",addr,ram_data, edata); + if(ram_data !== edata) begin + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,ram_data, edata); + #1us; + TEST_FAIL; + end + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, ram_data, edata); + end + else begin + $display("* DRAM CS is High => Error!!!"); + TEST_FAIL; + end +endtask + +task REGFILE_CHECK; + input [4:0] addr ; + input [31:0] edata ; + + logic [31:0] reg_data; + @(posedge reg_en ); + @(posedge reg_clk); + if(reg_en)begin + reg_data = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_dat; + if(reg_data !== edata) begin + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,reg_data, edata); + #1us; + //TEST_FAIL; + end + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, reg_data, edata); + end + else begin + $display("* REG WR EN is High => Error!!!"); + //TEST_FAIL; + end + +endtask + +initial begin + #100us; + $display("\n----------------------------------------\n"); + $display("\t Timeout Error !!!!\n"); + TEST_FAIL; +end + diff --git a/tb/qumcu/isa/case/Auipc_0xaaaaa_test/main.c b/tb/qumcu/isa/case/Auipc_0xaaaaa_test/main.c new file mode 100644 index 0000000..f92eb3f --- /dev/null +++ b/tb/qumcu/isa/case/Auipc_0xaaaaa_test/main.c @@ -0,0 +1,20 @@ +//#include + + +//int main(){ +// printf("\t=====================================\n"); +// printf("\t hello world !!! \n"); +// printf("\t=====================================\n"); +//} + +void main(void){ + +unsigned int a,b; + a=5; + b=3; + //c=a+b; + //d=c+b; +} + + + diff --git a/tb/qumcu/isa/case/Auipc_0xaaaaa_test/main.s b/tb/qumcu/isa/case/Auipc_0xaaaaa_test/main.s new file mode 100644 index 0000000..153cece --- /dev/null +++ b/tb/qumcu/isa/case/Auipc_0xaaaaa_test/main.s @@ -0,0 +1,124 @@ +auipc x1, 0xaaaaa +auipc x1, 0xaaaaa +auipc x1, 0xaaaaa +auipc x1, 0xaaaaa +auipc x2, 0xaaaaa +auipc x2, 0xaaaaa +auipc x2, 0xaaaaa +auipc x2, 0xaaaaa +auipc x3, 0xaaaaa +auipc x3, 0xaaaaa +auipc x3, 0xaaaaa +auipc x3, 0xaaaaa +auipc x4, 0xaaaaa +auipc x4, 0xaaaaa +auipc x4, 0xaaaaa +auipc x4, 0xaaaaa +auipc x5, 0xaaaaa +auipc x5, 0xaaaaa +auipc x5, 0xaaaaa +auipc x5, 0xaaaaa +auipc x6, 0xaaaaa +auipc x6, 0xaaaaa +auipc x6, 0xaaaaa +auipc x6, 0xaaaaa +auipc x7, 0xaaaaa +auipc x7, 0xaaaaa +auipc x7, 0xaaaaa +auipc x7, 0xaaaaa +auipc x8, 0xaaaaa +auipc x8, 0xaaaaa +auipc x8, 0xaaaaa +auipc x8, 0xaaaaa +auipc x9, 0xaaaaa +auipc x9, 0xaaaaa +auipc x9, 0xaaaaa +auipc x9, 0xaaaaa +auipc x10,0xaaaaa +auipc x10,0xaaaaa +auipc x10,0xaaaaa +auipc x10,0xaaaaa +auipc x11,0xaaaaa +auipc x11,0xaaaaa +auipc x11,0xaaaaa +auipc x11,0xaaaaa +auipc x12,0xaaaaa +auipc x12,0xaaaaa +auipc x12,0xaaaaa +auipc x12,0xaaaaa +auipc x13,0xaaaaa +auipc x13,0xaaaaa +auipc x13,0xaaaaa +auipc x13,0xaaaaa +auipc x14,0xaaaaa +auipc x14,0xaaaaa +auipc x14,0xaaaaa +auipc x14,0xaaaaa +auipc x15,0xaaaaa +auipc x15,0xaaaaa +auipc x15,0xaaaaa +auipc x15,0xaaaaa +auipc x16,0xaaaaa +auipc x16,0xaaaaa +auipc x16,0xaaaaa +auipc x16,0xaaaaa +auipc x17,0xaaaaa +auipc x17,0xaaaaa +auipc x17,0xaaaaa +auipc x17,0xaaaaa +auipc x18,0xaaaaa +auipc x18,0xaaaaa +auipc x18,0xaaaaa +auipc x18,0xaaaaa +auipc x19,0xaaaaa +auipc x19,0xaaaaa +auipc x19,0xaaaaa +auipc x19,0xaaaaa +auipc x20,0xaaaaa +auipc x20,0xaaaaa +auipc x20,0xaaaaa +auipc x20,0xaaaaa +auipc x21,0xaaaaa +auipc x21,0xaaaaa +auipc x21,0xaaaaa +auipc x21,0xaaaaa +auipc x22,0xaaaaa +auipc x22,0xaaaaa +auipc x22,0xaaaaa +auipc x22,0xaaaaa +auipc x23,0xaaaaa +auipc x23,0xaaaaa +auipc x23,0xaaaaa +auipc x23,0xaaaaa +auipc x24,0xaaaaa +auipc x24,0xaaaaa +auipc x24,0xaaaaa +auipc x24,0xaaaaa +auipc x25,0xaaaaa +auipc x25,0xaaaaa +auipc x25,0xaaaaa +auipc x25,0xaaaaa +auipc x26,0xaaaaa +auipc x26,0xaaaaa +auipc x26,0xaaaaa +auipc x26,0xaaaaa +auipc x27,0xaaaaa +auipc x27,0xaaaaa +auipc x27,0xaaaaa +auipc x27,0xaaaaa +auipc x28,0xaaaaa +auipc x28,0xaaaaa +auipc x28,0xaaaaa +auipc x28,0xaaaaa +auipc x29,0xaaaaa +auipc x29,0xaaaaa +auipc x29,0xaaaaa +auipc x29,0xaaaaa +auipc x30,0xaaaaa +auipc x30,0xaaaaa +auipc x30,0xaaaaa +auipc x30,0xaaaaa +auipc x31,0xaaaaa +auipc x31,0xaaaaa +auipc x31,0xaaaaa +auipc x31,0xaaaaa \ No newline at end of file diff --git a/tb/qumcu/isa/case/Auipc_0xaaaaa_test/user.sv b/tb/qumcu/isa/case/Auipc_0xaaaaa_test/user.sv new file mode 100644 index 0000000..43000d6 --- /dev/null +++ b/tb/qumcu/isa/case/Auipc_0xaaaaa_test/user.sv @@ -0,0 +1,203 @@ + +wire ram_clk = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CLK; +wire ram_cs = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CEBA; +wire reg_clk = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.clk; +wire reg_en = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_wen; +reg ram_cs_dly1 ; +reg reg_en_dly1 ; +always @(posedge ram_clk) begin + ram_cs_dly1 <= ~ram_cs; + reg_en_dly1 <= reg_en; +end + + +initial begin + #1ns; + //@(posedge ram_cs_dly1 ); + #5ns; + //while(1)begin + #1ns; + //@(posedge reg_en_dly1 ); + REGFILE_CHECK(6'd1 ,32'haaaa_a000); + REGFILE_CHECK(6'd1 ,32'haaaa_a004); + REGFILE_CHECK(6'd1 ,32'haaaa_a008); + REGFILE_CHECK(6'd1 ,32'haaaa_a00c); + REGFILE_CHECK(6'd2 ,32'haaaa_a010); + REGFILE_CHECK(6'd2 ,32'haaaa_a014); + REGFILE_CHECK(6'd2 ,32'haaaa_a018); + REGFILE_CHECK(6'd2 ,32'haaaa_a01c); + REGFILE_CHECK(6'd3 ,32'haaaa_a020); + REGFILE_CHECK(6'd3 ,32'haaaa_a024); + REGFILE_CHECK(6'd3 ,32'haaaa_a028); + REGFILE_CHECK(6'd3 ,32'haaaa_a02c); + REGFILE_CHECK(6'd4 ,32'haaaa_a030); + REGFILE_CHECK(6'd4 ,32'haaaa_a034); + REGFILE_CHECK(6'd4 ,32'haaaa_a038); + REGFILE_CHECK(6'd4 ,32'haaaa_a03c); + REGFILE_CHECK(6'd5 ,32'haaaa_a040); + REGFILE_CHECK(6'd5 ,32'haaaa_a044); + REGFILE_CHECK(6'd5 ,32'haaaa_a048); + REGFILE_CHECK(6'd5 ,32'haaaa_a04c); + REGFILE_CHECK(6'd6 ,32'haaaa_a050); + REGFILE_CHECK(6'd6 ,32'haaaa_a054); + REGFILE_CHECK(6'd6 ,32'haaaa_a058); + REGFILE_CHECK(6'd6 ,32'haaaa_a05c); + REGFILE_CHECK(6'd7 ,32'haaaa_a060); + REGFILE_CHECK(6'd7 ,32'haaaa_a064); + REGFILE_CHECK(6'd7 ,32'haaaa_a068); + REGFILE_CHECK(6'd7 ,32'haaaa_a06c); + REGFILE_CHECK(6'd8 ,32'haaaa_a070); + REGFILE_CHECK(6'd8 ,32'haaaa_a074); + REGFILE_CHECK(6'd8 ,32'haaaa_a078); + REGFILE_CHECK(6'd8 ,32'haaaa_a07c); + REGFILE_CHECK(6'd9 ,32'haaaa_a080); + REGFILE_CHECK(6'd9 ,32'haaaa_a084); + REGFILE_CHECK(6'd9 ,32'haaaa_a088); + REGFILE_CHECK(6'd9 ,32'haaaa_a08c); + REGFILE_CHECK(6'd10,32'haaaa_a090); + REGFILE_CHECK(6'd10,32'haaaa_a094); + REGFILE_CHECK(6'd10,32'haaaa_a098); + REGFILE_CHECK(6'd10,32'haaaa_a09c); + REGFILE_CHECK(6'd11,32'haaaa_a0a0); + REGFILE_CHECK(6'd11,32'haaaa_a0a4); + REGFILE_CHECK(6'd11,32'haaaa_a0a8); + REGFILE_CHECK(6'd11,32'haaaa_a0ac); + REGFILE_CHECK(6'd12,32'haaaa_a0b0); + REGFILE_CHECK(6'd12,32'haaaa_a0b4); + REGFILE_CHECK(6'd12,32'haaaa_a0b8); + REGFILE_CHECK(6'd12,32'haaaa_a0bc); + REGFILE_CHECK(6'd13,32'haaaa_a0c0); + REGFILE_CHECK(6'd13,32'haaaa_a0c4); + REGFILE_CHECK(6'd13,32'haaaa_a0c8); + REGFILE_CHECK(6'd13,32'haaaa_a0cc); + REGFILE_CHECK(6'd14,32'haaaa_a0d0); + REGFILE_CHECK(6'd14,32'haaaa_a0d4); + REGFILE_CHECK(6'd14,32'haaaa_a0d8); + REGFILE_CHECK(6'd14,32'haaaa_a0dc); + REGFILE_CHECK(6'd15,32'haaaa_a0e0); + REGFILE_CHECK(6'd15,32'haaaa_a0e4); + REGFILE_CHECK(6'd15,32'haaaa_a0e8); + REGFILE_CHECK(6'd15,32'haaaa_a0ec); + REGFILE_CHECK(6'd16,32'haaaa_a0f0); + REGFILE_CHECK(6'd16,32'haaaa_a0f4); + REGFILE_CHECK(6'd16,32'haaaa_a0f8); + REGFILE_CHECK(6'd16,32'haaaa_a0fc); + REGFILE_CHECK(6'd17,32'haaaa_a100); + REGFILE_CHECK(6'd17,32'haaaa_a104); + REGFILE_CHECK(6'd17,32'haaaa_a108); + REGFILE_CHECK(6'd17,32'haaaa_a10c); + REGFILE_CHECK(6'd18,32'haaaa_a110); + REGFILE_CHECK(6'd18,32'haaaa_a114); + REGFILE_CHECK(6'd18,32'haaaa_a118); + REGFILE_CHECK(6'd18,32'haaaa_a11c); + REGFILE_CHECK(6'd19,32'haaaa_a120); + REGFILE_CHECK(6'd19,32'haaaa_a124); + REGFILE_CHECK(6'd19,32'haaaa_a128); + REGFILE_CHECK(6'd19,32'haaaa_a12c); + REGFILE_CHECK(6'd20,32'haaaa_a130); + REGFILE_CHECK(6'd20,32'haaaa_a134); + REGFILE_CHECK(6'd20,32'haaaa_a138); + REGFILE_CHECK(6'd20,32'haaaa_a13c); + REGFILE_CHECK(6'd21,32'haaaa_a140); + REGFILE_CHECK(6'd21,32'haaaa_a144); + REGFILE_CHECK(6'd21,32'haaaa_a148); + REGFILE_CHECK(6'd21,32'haaaa_a14c); + REGFILE_CHECK(6'd22,32'haaaa_a150); + REGFILE_CHECK(6'd22,32'haaaa_a154); + REGFILE_CHECK(6'd22,32'haaaa_a158); + REGFILE_CHECK(6'd22,32'haaaa_a15c); + REGFILE_CHECK(6'd23,32'haaaa_a160); + REGFILE_CHECK(6'd23,32'haaaa_a164); + REGFILE_CHECK(6'd23,32'haaaa_a168); + REGFILE_CHECK(6'd23,32'haaaa_a16c); + REGFILE_CHECK(6'd24,32'haaaa_a170); + REGFILE_CHECK(6'd24,32'haaaa_a174); + REGFILE_CHECK(6'd24,32'haaaa_a178); + REGFILE_CHECK(6'd24,32'haaaa_a17c); + REGFILE_CHECK(6'd25,32'haaaa_a180); + REGFILE_CHECK(6'd25,32'haaaa_a184); + REGFILE_CHECK(6'd25,32'haaaa_a188); + REGFILE_CHECK(6'd25,32'haaaa_a18c); + REGFILE_CHECK(6'd26,32'haaaa_a190); + REGFILE_CHECK(6'd26,32'haaaa_a194); + REGFILE_CHECK(6'd26,32'haaaa_a198); + REGFILE_CHECK(6'd26,32'haaaa_a19c); + REGFILE_CHECK(6'd27,32'haaaa_a1a0); + REGFILE_CHECK(6'd27,32'haaaa_a1a4); + REGFILE_CHECK(6'd27,32'haaaa_a1a8); + REGFILE_CHECK(6'd27,32'haaaa_a1ac); + REGFILE_CHECK(6'd28,32'haaaa_a1b0); + REGFILE_CHECK(6'd28,32'haaaa_a1b4); + REGFILE_CHECK(6'd28,32'haaaa_a1b8); + REGFILE_CHECK(6'd28,32'haaaa_a1bc); + REGFILE_CHECK(6'd29,32'haaaa_a1c0); + REGFILE_CHECK(6'd29,32'haaaa_a1c4); + REGFILE_CHECK(6'd29,32'haaaa_a1c8); + REGFILE_CHECK(6'd29,32'haaaa_a1cc); + REGFILE_CHECK(6'd30,32'haaaa_a1d0); + REGFILE_CHECK(6'd30,32'haaaa_a1d4); + REGFILE_CHECK(6'd30,32'haaaa_a1d8); + REGFILE_CHECK(6'd30,32'haaaa_a1dc); + REGFILE_CHECK(6'd31,32'haaaa_a1e0); + REGFILE_CHECK(6'd31,32'haaaa_a1e4); + REGFILE_CHECK(6'd31,32'haaaa_a1e8); + REGFILE_CHECK(6'd31,32'haaaa_a1ec); + #10us; + TEST_PASS; +end + +task DRAM_DATA_CHECK; + input [9:0] addr ; + input [31:0] edata ; + + logic [31:0] ram_data; + + @(posedge ram_cs_dly1 ); + @(posedge ram_clk ); + //$monitor($time, " Simulation time: %t", $time); + if(ram_cs_dly1) begin + ram_data = `TB_DRAM.mem[addr]; + //$display("* RAM_DATA[%x]: %x | EXP_DATA: %x ",addr,ram_data, edata); + if(ram_data !== edata) begin + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,ram_data, edata); + #1us; + TEST_FAIL; + end + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, ram_data, edata); + end + else begin + $display("* DRAM CS is High => Error!!!"); + TEST_FAIL; + end +endtask + +task REGFILE_CHECK; + input [4:0] addr ; + input [31:0] edata ; + + logic [31:0] reg_data; + @(posedge reg_en ); + @(posedge reg_clk); + if(reg_en)begin + reg_data = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_dat; + if(reg_data !== edata) begin + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,reg_data, edata); + #1us; + //TEST_FAIL; + end + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, reg_data, edata); + end + else begin + $display("* REG WR EN is High => Error!!!"); + //TEST_FAIL; + end + +endtask + +initial begin + #100us; + $display("\n----------------------------------------\n"); + $display("\t Timeout Error !!!!\n"); + TEST_FAIL; +end + diff --git a/tb/qumcu/isa/case/Auipc_0xfffff_test/main.c b/tb/qumcu/isa/case/Auipc_0xfffff_test/main.c new file mode 100644 index 0000000..f92eb3f --- /dev/null +++ b/tb/qumcu/isa/case/Auipc_0xfffff_test/main.c @@ -0,0 +1,20 @@ +//#include + + +//int main(){ +// printf("\t=====================================\n"); +// printf("\t hello world !!! \n"); +// printf("\t=====================================\n"); +//} + +void main(void){ + +unsigned int a,b; + a=5; + b=3; + //c=a+b; + //d=c+b; +} + + + diff --git a/tb/qumcu/isa/case/Auipc_0xfffff_test/main.s b/tb/qumcu/isa/case/Auipc_0xfffff_test/main.s new file mode 100644 index 0000000..d3abf79 --- /dev/null +++ b/tb/qumcu/isa/case/Auipc_0xfffff_test/main.s @@ -0,0 +1,124 @@ +auipc x1, 0xfffff +auipc x1, 0xfffff +auipc x1, 0xfffff +auipc x1, 0xfffff +auipc x2, 0xfffff +auipc x2, 0xfffff +auipc x2, 0xfffff +auipc x2, 0xfffff +auipc x3, 0xfffff +auipc x3, 0xfffff +auipc x3, 0xfffff +auipc x3, 0xfffff +auipc x4, 0xfffff +auipc x4, 0xfffff +auipc x4, 0xfffff +auipc x4, 0xfffff +auipc x5, 0xfffff +auipc x5, 0xfffff +auipc x5, 0xfffff +auipc x5, 0xfffff +auipc x6, 0xfffff +auipc x6, 0xfffff +auipc x6, 0xfffff +auipc x6, 0xfffff +auipc x7, 0xfffff +auipc x7, 0xfffff +auipc x7, 0xfffff +auipc x7, 0xfffff +auipc x8, 0xfffff +auipc x8, 0xfffff +auipc x8, 0xfffff +auipc x8, 0xfffff +auipc x9, 0xfffff +auipc x9, 0xfffff +auipc x9, 0xfffff +auipc x9, 0xfffff +auipc x10,0xfffff +auipc x10,0xfffff +auipc x10,0xfffff +auipc x10,0xfffff +auipc x11,0xfffff +auipc x11,0xfffff +auipc x11,0xfffff +auipc x11,0xfffff +auipc x12,0xfffff +auipc x12,0xfffff +auipc x12,0xfffff +auipc x12,0xfffff +auipc x13,0xfffff +auipc x13,0xfffff +auipc x13,0xfffff +auipc x13,0xfffff +auipc x14,0xfffff +auipc x14,0xfffff +auipc x14,0xfffff +auipc x14,0xfffff +auipc x15,0xfffff +auipc x15,0xfffff +auipc x15,0xfffff +auipc x15,0xfffff +auipc x16,0xfffff +auipc x16,0xfffff +auipc x16,0xfffff +auipc x16,0xfffff +auipc x17,0xfffff +auipc x17,0xfffff +auipc x17,0xfffff +auipc x17,0xfffff +auipc x18,0xfffff +auipc x18,0xfffff +auipc x18,0xfffff +auipc x18,0xfffff +auipc x19,0xfffff +auipc x19,0xfffff +auipc x19,0xfffff +auipc x19,0xfffff +auipc x20,0xfffff +auipc x20,0xfffff +auipc x20,0xfffff +auipc x20,0xfffff +auipc x21,0xfffff +auipc x21,0xfffff +auipc x21,0xfffff +auipc x21,0xfffff +auipc x22,0xfffff +auipc x22,0xfffff +auipc x22,0xfffff +auipc x22,0xfffff +auipc x23,0xfffff +auipc x23,0xfffff +auipc x23,0xfffff +auipc x23,0xfffff +auipc x24,0xfffff +auipc x24,0xfffff +auipc x24,0xfffff +auipc x24,0xfffff +auipc x25,0xfffff +auipc x25,0xfffff +auipc x25,0xfffff +auipc x25,0xfffff +auipc x26,0xfffff +auipc x26,0xfffff +auipc x26,0xfffff +auipc x26,0xfffff +auipc x27,0xfffff +auipc x27,0xfffff +auipc x27,0xfffff +auipc x27,0xfffff +auipc x28,0xfffff +auipc x28,0xfffff +auipc x28,0xfffff +auipc x28,0xfffff +auipc x29,0xfffff +auipc x29,0xfffff +auipc x29,0xfffff +auipc x29,0xfffff +auipc x30,0xfffff +auipc x30,0xfffff +auipc x30,0xfffff +auipc x30,0xfffff +auipc x31,0xfffff +auipc x31,0xfffff +auipc x31,0xfffff +auipc x31,0xfffff \ No newline at end of file diff --git a/tb/qumcu/isa/case/Auipc_0xfffff_test/user.sv b/tb/qumcu/isa/case/Auipc_0xfffff_test/user.sv new file mode 100644 index 0000000..d4edbbc --- /dev/null +++ b/tb/qumcu/isa/case/Auipc_0xfffff_test/user.sv @@ -0,0 +1,203 @@ + +wire ram_clk = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CLK; +wire ram_cs = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CEBA; +wire reg_clk = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.clk; +wire reg_en = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_wen; +reg ram_cs_dly1 ; +reg reg_en_dly1 ; +always @(posedge ram_clk) begin + ram_cs_dly1 <= ~ram_cs; + reg_en_dly1 <= reg_en; +end + + +initial begin + #1ns; + //@(posedge ram_cs_dly1 ); + #5ns; + //while(1)begin + #1ns; + //@(posedge reg_en_dly1 ); + REGFILE_CHECK(6'd1 ,32'hffff_f000); + REGFILE_CHECK(6'd1 ,32'hffff_f004); + REGFILE_CHECK(6'd1 ,32'hffff_f008); + REGFILE_CHECK(6'd1 ,32'hffff_f00c); + REGFILE_CHECK(6'd2 ,32'hffff_f010); + REGFILE_CHECK(6'd2 ,32'hffff_f014); + REGFILE_CHECK(6'd2 ,32'hffff_f018); + REGFILE_CHECK(6'd2 ,32'hffff_f01c); + REGFILE_CHECK(6'd3 ,32'hffff_f020); + REGFILE_CHECK(6'd3 ,32'hffff_f024); + REGFILE_CHECK(6'd3 ,32'hffff_f028); + REGFILE_CHECK(6'd3 ,32'hffff_f02c); + REGFILE_CHECK(6'd4 ,32'hffff_f030); + REGFILE_CHECK(6'd4 ,32'hffff_f034); + REGFILE_CHECK(6'd4 ,32'hffff_f038); + REGFILE_CHECK(6'd4 ,32'hffff_f03c); + REGFILE_CHECK(6'd5 ,32'hffff_f040); + REGFILE_CHECK(6'd5 ,32'hffff_f044); + REGFILE_CHECK(6'd5 ,32'hffff_f048); + REGFILE_CHECK(6'd5 ,32'hffff_f04c); + REGFILE_CHECK(6'd6 ,32'hffff_f050); + REGFILE_CHECK(6'd6 ,32'hffff_f054); + REGFILE_CHECK(6'd6 ,32'hffff_f058); + REGFILE_CHECK(6'd6 ,32'hffff_f05c); + REGFILE_CHECK(6'd7 ,32'hffff_f060); + REGFILE_CHECK(6'd7 ,32'hffff_f064); + REGFILE_CHECK(6'd7 ,32'hffff_f068); + REGFILE_CHECK(6'd7 ,32'hffff_f06c); + REGFILE_CHECK(6'd8 ,32'hffff_f070); + REGFILE_CHECK(6'd8 ,32'hffff_f074); + REGFILE_CHECK(6'd8 ,32'hffff_f078); + REGFILE_CHECK(6'd8 ,32'hffff_f07c); + REGFILE_CHECK(6'd9 ,32'hffff_f080); + REGFILE_CHECK(6'd9 ,32'hffff_f084); + REGFILE_CHECK(6'd9 ,32'hffff_f088); + REGFILE_CHECK(6'd9 ,32'hffff_f08c); + REGFILE_CHECK(6'd10,32'hffff_f090); + REGFILE_CHECK(6'd10,32'hffff_f094); + REGFILE_CHECK(6'd10,32'hffff_f098); + REGFILE_CHECK(6'd10,32'hffff_f09c); + REGFILE_CHECK(6'd11,32'hffff_f0a0); + REGFILE_CHECK(6'd11,32'hffff_f0a4); + REGFILE_CHECK(6'd11,32'hffff_f0a8); + REGFILE_CHECK(6'd11,32'hffff_f0ac); + REGFILE_CHECK(6'd12,32'hffff_f0b0); + REGFILE_CHECK(6'd12,32'hffff_f0b4); + REGFILE_CHECK(6'd12,32'hffff_f0b8); + REGFILE_CHECK(6'd12,32'hffff_f0bc); + REGFILE_CHECK(6'd13,32'hffff_f0c0); + REGFILE_CHECK(6'd13,32'hffff_f0c4); + REGFILE_CHECK(6'd13,32'hffff_f0c8); + REGFILE_CHECK(6'd13,32'hffff_f0cc); + REGFILE_CHECK(6'd14,32'hffff_f0d0); + REGFILE_CHECK(6'd14,32'hffff_f0d4); + REGFILE_CHECK(6'd14,32'hffff_f0d8); + REGFILE_CHECK(6'd14,32'hffff_f0dc); + REGFILE_CHECK(6'd15,32'hffff_f0e0); + REGFILE_CHECK(6'd15,32'hffff_f0e4); + REGFILE_CHECK(6'd15,32'hffff_f0e8); + REGFILE_CHECK(6'd15,32'hffff_f0ec); + REGFILE_CHECK(6'd16,32'hffff_f0f0); + REGFILE_CHECK(6'd16,32'hffff_f0f4); + REGFILE_CHECK(6'd16,32'hffff_f0f8); + REGFILE_CHECK(6'd16,32'hffff_f0fc); + REGFILE_CHECK(6'd17,32'hffff_f100); + REGFILE_CHECK(6'd17,32'hffff_f104); + REGFILE_CHECK(6'd17,32'hffff_f108); + REGFILE_CHECK(6'd17,32'hffff_f10c); + REGFILE_CHECK(6'd18,32'hffff_f110); + REGFILE_CHECK(6'd18,32'hffff_f114); + REGFILE_CHECK(6'd18,32'hffff_f118); + REGFILE_CHECK(6'd18,32'hffff_f11c); + REGFILE_CHECK(6'd19,32'hffff_f120); + REGFILE_CHECK(6'd19,32'hffff_f124); + REGFILE_CHECK(6'd19,32'hffff_f128); + REGFILE_CHECK(6'd19,32'hffff_f12c); + REGFILE_CHECK(6'd20,32'hffff_f130); + REGFILE_CHECK(6'd20,32'hffff_f134); + REGFILE_CHECK(6'd20,32'hffff_f138); + REGFILE_CHECK(6'd20,32'hffff_f13c); + REGFILE_CHECK(6'd21,32'hffff_f140); + REGFILE_CHECK(6'd21,32'hffff_f144); + REGFILE_CHECK(6'd21,32'hffff_f148); + REGFILE_CHECK(6'd21,32'hffff_f14c); + REGFILE_CHECK(6'd22,32'hffff_f150); + REGFILE_CHECK(6'd22,32'hffff_f154); + REGFILE_CHECK(6'd22,32'hffff_f158); + REGFILE_CHECK(6'd22,32'hffff_f15c); + REGFILE_CHECK(6'd23,32'hffff_f160); + REGFILE_CHECK(6'd23,32'hffff_f164); + REGFILE_CHECK(6'd23,32'hffff_f168); + REGFILE_CHECK(6'd23,32'hffff_f16c); + REGFILE_CHECK(6'd24,32'hffff_f170); + REGFILE_CHECK(6'd24,32'hffff_f174); + REGFILE_CHECK(6'd24,32'hffff_f178); + REGFILE_CHECK(6'd24,32'hffff_f17c); + REGFILE_CHECK(6'd25,32'hffff_f180); + REGFILE_CHECK(6'd25,32'hffff_f184); + REGFILE_CHECK(6'd25,32'hffff_f188); + REGFILE_CHECK(6'd25,32'hffff_f18c); + REGFILE_CHECK(6'd26,32'hffff_f190); + REGFILE_CHECK(6'd26,32'hffff_f194); + REGFILE_CHECK(6'd26,32'hffff_f198); + REGFILE_CHECK(6'd26,32'hffff_f19c); + REGFILE_CHECK(6'd27,32'hffff_f1a0); + REGFILE_CHECK(6'd27,32'hffff_f1a4); + REGFILE_CHECK(6'd27,32'hffff_f1a8); + REGFILE_CHECK(6'd27,32'hffff_f1ac); + REGFILE_CHECK(6'd28,32'hffff_f1b0); + REGFILE_CHECK(6'd28,32'hffff_f1b4); + REGFILE_CHECK(6'd28,32'hffff_f1b8); + REGFILE_CHECK(6'd28,32'hffff_f1bc); + REGFILE_CHECK(6'd29,32'hffff_f1c0); + REGFILE_CHECK(6'd29,32'hffff_f1c4); + REGFILE_CHECK(6'd29,32'hffff_f1c8); + REGFILE_CHECK(6'd29,32'hffff_f1cc); + REGFILE_CHECK(6'd30,32'hffff_f1d0); + REGFILE_CHECK(6'd30,32'hffff_f1d4); + REGFILE_CHECK(6'd30,32'hffff_f1d8); + REGFILE_CHECK(6'd30,32'hffff_f1dc); + REGFILE_CHECK(6'd31,32'hffff_f1e0); + REGFILE_CHECK(6'd31,32'hffff_f1e4); + REGFILE_CHECK(6'd31,32'hffff_f1e8); + REGFILE_CHECK(6'd31,32'hffff_f1ec); + #10us; + TEST_PASS; +end + +task DRAM_DATA_CHECK; + input [9:0] addr ; + input [31:0] edata ; + + logic [31:0] ram_data; + + @(posedge ram_cs_dly1 ); + @(posedge ram_clk ); + //$monitor($time, " Simulation time: %t", $time); + if(ram_cs_dly1) begin + ram_data = `TB_DRAM.mem[addr]; + //$display("* RAM_DATA[%x]: %x | EXP_DATA: %x ",addr,ram_data, edata); + if(ram_data !== edata) begin + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,ram_data, edata); + #1us; + TEST_FAIL; + end + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, ram_data, edata); + end + else begin + $display("* DRAM CS is High => Error!!!"); + TEST_FAIL; + end +endtask + +task REGFILE_CHECK; + input [4:0] addr ; + input [31:0] edata ; + + logic [31:0] reg_data; + @(posedge reg_en ); + @(posedge reg_clk); + if(reg_en)begin + reg_data = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_dat; + if(reg_data !== edata) begin + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,reg_data, edata); + #1us; + //TEST_FAIL; + end + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, reg_data, edata); + end + else begin + $display("* REG WR EN is High => Error!!!"); + //TEST_FAIL; + end + +endtask + +initial begin + #100us; + $display("\n----------------------------------------\n"); + $display("\t Timeout Error !!!!\n"); + TEST_FAIL; +end + diff --git a/tb/qumcu/isa/case/Beq_beq_beq_test/main.c b/tb/qumcu/isa/case/Beq_beq_beq_test/main.c new file mode 100644 index 0000000..f92eb3f --- /dev/null +++ b/tb/qumcu/isa/case/Beq_beq_beq_test/main.c @@ -0,0 +1,20 @@ +//#include + + +//int main(){ +// printf("\t=====================================\n"); +// printf("\t hello world !!! \n"); +// printf("\t=====================================\n"); +//} + +void main(void){ + +unsigned int a,b; + a=5; + b=3; + //c=a+b; + //d=c+b; +} + + + diff --git a/tb/qumcu/isa/case/Beq_beq_beq_test/main.s b/tb/qumcu/isa/case/Beq_beq_beq_test/main.s new file mode 100644 index 0000000..7ffedc3 --- /dev/null +++ b/tb/qumcu/isa/case/Beq_beq_beq_test/main.s @@ -0,0 +1,20 @@ +.global main +main: +addi x1,x0,-0x5 +addi x2,x0,-0x5 +lui x3,0x50 + +beq x2,x1,string1 +lui x4,0x60 +string1: +beq x2,x1,string2 +lui x5,0x70 +lui x6,0x80 +string2: +beq x2,x1,string3 +lui x5,0x77 +lui x6,0x88 +string3: +lui x5,0x99 +lui x6,0xaa +exit: diff --git a/tb/qumcu/isa/case/Beq_beq_beq_test/user.sv b/tb/qumcu/isa/case/Beq_beq_beq_test/user.sv new file mode 100644 index 0000000..ab1633b --- /dev/null +++ b/tb/qumcu/isa/case/Beq_beq_beq_test/user.sv @@ -0,0 +1,20 @@ + +initial begin + #10ns; + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[1].rfno0.rf_dfflr.qout_r == 32'hffff_fffb); + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[2].rfno0.rf_dfflr.qout_r == 32'hffff_fffb); + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[3].rfno0.rf_dfflr.qout_r == 32'h50000); + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[4].rfno0.rf_dfflr.qout_r == 32'h00000); + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[5].rfno0.rf_dfflr.qout_r == 32'h99000); + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[6].rfno0.rf_dfflr.qout_r == 32'haa000); + TEST_PASS; + +end + +initial begin + #100us; + $display("\n----------------------------------------\n"); + $display("\t Timeout Error !!!!\n"); + TEST_FAIL; +end + diff --git a/tb/qumcu/isa/case/Beq_test/main.c b/tb/qumcu/isa/case/Beq_test/main.c new file mode 100644 index 0000000..f92eb3f --- /dev/null +++ b/tb/qumcu/isa/case/Beq_test/main.c @@ -0,0 +1,20 @@ +//#include + + +//int main(){ +// printf("\t=====================================\n"); +// printf("\t hello world !!! \n"); +// printf("\t=====================================\n"); +//} + +void main(void){ + +unsigned int a,b; + a=5; + b=3; + //c=a+b; + //d=c+b; +} + + + diff --git a/tb/qumcu/isa/case/Beq_test/main.s b/tb/qumcu/isa/case/Beq_test/main.s new file mode 100644 index 0000000..3312776 --- /dev/null +++ b/tb/qumcu/isa/case/Beq_test/main.s @@ -0,0 +1,13 @@ + +.global main +main: +lui x1,0x40 +lui x2,0x40 +lui x3,0x50 + +bge x1,x2,string1 +lui x4,0x60 +string1: +lui x5,0x70 +lui x6,0x80 +exit: diff --git a/tb/qumcu/isa/case/Beq_test/user.sv b/tb/qumcu/isa/case/Beq_test/user.sv new file mode 100644 index 0000000..136fc9c --- /dev/null +++ b/tb/qumcu/isa/case/Beq_test/user.sv @@ -0,0 +1,20 @@ + +initial begin + #10ns; + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[1].rfno0.rf_dfflr.qout_r == 32'h40000); + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[2].rfno0.rf_dfflr.qout_r == 32'h40000); + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[3].rfno0.rf_dfflr.qout_r == 32'h50000); + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[4].rfno0.rf_dfflr.qout_r == 32'h00000); + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[5].rfno0.rf_dfflr.qout_r == 32'h70000); + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[6].rfno0.rf_dfflr.qout_r == 32'h80000); + TEST_PASS; + +end + +initial begin + #100us; + $display("\n----------------------------------------\n"); + $display("\t Timeout Error !!!!\n"); + TEST_FAIL; +end + diff --git a/tb/qumcu/isa/case/Bge_bge_bge_test/main.c b/tb/qumcu/isa/case/Bge_bge_bge_test/main.c new file mode 100644 index 0000000..f92eb3f --- /dev/null +++ b/tb/qumcu/isa/case/Bge_bge_bge_test/main.c @@ -0,0 +1,20 @@ +//#include + + +//int main(){ +// printf("\t=====================================\n"); +// printf("\t hello world !!! \n"); +// printf("\t=====================================\n"); +//} + +void main(void){ + +unsigned int a,b; + a=5; + b=3; + //c=a+b; + //d=c+b; +} + + + diff --git a/tb/qumcu/isa/case/Bge_bge_bge_test/main.s b/tb/qumcu/isa/case/Bge_bge_bge_test/main.s new file mode 100644 index 0000000..1cbe5f3 --- /dev/null +++ b/tb/qumcu/isa/case/Bge_bge_bge_test/main.s @@ -0,0 +1,20 @@ +.global main +main: +addi x1,x0,-0x5 +addi x2,x0,-0x4 +lui x3,0x50 + +bge x2,x1,string1 +lui x4,0x60 +string1: +bge x2,x1,string2 +lui x5,0x70 +lui x6,0x80 +string2: +bge x2,x1,string3 +lui x5,0x77 +lui x6,0x88 +string3: +lui x5,0x99 +lui x6,0xaa +exit: diff --git a/tb/qumcu/isa/case/Bge_bge_bge_test/user.sv b/tb/qumcu/isa/case/Bge_bge_bge_test/user.sv new file mode 100644 index 0000000..05b73f7 --- /dev/null +++ b/tb/qumcu/isa/case/Bge_bge_bge_test/user.sv @@ -0,0 +1,20 @@ + +initial begin + #10ns; + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[1].rfno0.rf_dfflr.qout_r == 32'hffff_fffb); + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[2].rfno0.rf_dfflr.qout_r == 32'hffff_fffc); + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[3].rfno0.rf_dfflr.qout_r == 32'h50000); + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[4].rfno0.rf_dfflr.qout_r == 32'h00000); + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[5].rfno0.rf_dfflr.qout_r == 32'h99000); + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[6].rfno0.rf_dfflr.qout_r == 32'haa000); + TEST_PASS; + +end + +initial begin + #100us; + $display("\n----------------------------------------\n"); + $display("\t Timeout Error !!!!\n"); + TEST_FAIL; +end + diff --git a/tb/qumcu/isa/case/Bge_bge_test/main.c b/tb/qumcu/isa/case/Bge_bge_test/main.c new file mode 100644 index 0000000..f92eb3f --- /dev/null +++ b/tb/qumcu/isa/case/Bge_bge_test/main.c @@ -0,0 +1,20 @@ +//#include + + +//int main(){ +// printf("\t=====================================\n"); +// printf("\t hello world !!! \n"); +// printf("\t=====================================\n"); +//} + +void main(void){ + +unsigned int a,b; + a=5; + b=3; + //c=a+b; + //d=c+b; +} + + + diff --git a/tb/qumcu/isa/case/Bge_bge_test/main.s b/tb/qumcu/isa/case/Bge_bge_test/main.s new file mode 100644 index 0000000..9bbd3e4 --- /dev/null +++ b/tb/qumcu/isa/case/Bge_bge_test/main.s @@ -0,0 +1,16 @@ +.global main +main: +addi x1,x0,-0x5 +addi x2,x0,-0x4 +lui x3,0x50 + +bge x2,x1,string1 +lui x4,0x60 +string1: +bge x2,x1,string2 +lui x5,0x70 +lui x6,0x80 +string2: +lui x5,0x77 +lui x6,0x88 +exit: diff --git a/tb/qumcu/isa/case/Bge_bge_test/user.sv b/tb/qumcu/isa/case/Bge_bge_test/user.sv new file mode 100644 index 0000000..a5ca4f1 --- /dev/null +++ b/tb/qumcu/isa/case/Bge_bge_test/user.sv @@ -0,0 +1,20 @@ + +initial begin + #10ns; + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[1].rfno0.rf_dfflr.qout_r == 32'hffff_fffb); + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[2].rfno0.rf_dfflr.qout_r == 32'hffff_fffc); + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[3].rfno0.rf_dfflr.qout_r == 32'h50000); + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[4].rfno0.rf_dfflr.qout_r == 32'h00000); + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[5].rfno0.rf_dfflr.qout_r == 32'h77000); + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[6].rfno0.rf_dfflr.qout_r == 32'h88000); + TEST_PASS; + +end + +initial begin + #100us; + $display("\n----------------------------------------\n"); + $display("\t Timeout Error !!!!\n"); + TEST_FAIL; +end + diff --git a/tb/qumcu/isa/case/Bge_neg_test/main.c b/tb/qumcu/isa/case/Bge_neg_test/main.c new file mode 100644 index 0000000..f92eb3f --- /dev/null +++ b/tb/qumcu/isa/case/Bge_neg_test/main.c @@ -0,0 +1,20 @@ +//#include + + +//int main(){ +// printf("\t=====================================\n"); +// printf("\t hello world !!! \n"); +// printf("\t=====================================\n"); +//} + +void main(void){ + +unsigned int a,b; + a=5; + b=3; + //c=a+b; + //d=c+b; +} + + + diff --git a/tb/qumcu/isa/case/Bge_neg_test/main.s b/tb/qumcu/isa/case/Bge_neg_test/main.s new file mode 100644 index 0000000..3815574 --- /dev/null +++ b/tb/qumcu/isa/case/Bge_neg_test/main.s @@ -0,0 +1,17 @@ + +.global main +main: +addi x1,x0,-0x5 +addi x2,x0,-0x4 +lui x3,0x50 + +bge x2,x1,string1 +lui x4,0x60 +string1: +bge x2,x1,string2 +lui x5,0x70 +lui x6,0x80 +string2: +lui x5,0x77 +lui x6,0x88 +exit: diff --git a/tb/qumcu/isa/case/Bge_neg_test/user.sv b/tb/qumcu/isa/case/Bge_neg_test/user.sv new file mode 100644 index 0000000..fd63669 --- /dev/null +++ b/tb/qumcu/isa/case/Bge_neg_test/user.sv @@ -0,0 +1,20 @@ + +initial begin + #10ns; + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[1].rfno0.rf_dfflr.qout_r == 32'hffff_fffb); + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[2].rfno0.rf_dfflr.qout_r == 32'hffff_fffc); + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[3].rfno0.rf_dfflr.qout_r == 32'h50000); + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[4].rfno0.rf_dfflr.qout_r == 32'h00000); + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[5].rfno0.rf_dfflr.qout_r == 32'h70000); + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[6].rfno0.rf_dfflr.qout_r == 32'h80000); + TEST_PASS; + +end + +initial begin + #100us; + $display("\n----------------------------------------\n"); + $display("\t Timeout Error !!!!\n"); + TEST_FAIL; +end + diff --git a/tb/qumcu/isa/case/Bge_test/main.c b/tb/qumcu/isa/case/Bge_test/main.c new file mode 100644 index 0000000..f92eb3f --- /dev/null +++ b/tb/qumcu/isa/case/Bge_test/main.c @@ -0,0 +1,20 @@ +//#include + + +//int main(){ +// printf("\t=====================================\n"); +// printf("\t hello world !!! \n"); +// printf("\t=====================================\n"); +//} + +void main(void){ + +unsigned int a,b; + a=5; + b=3; + //c=a+b; + //d=c+b; +} + + + diff --git a/tb/qumcu/isa/case/Bge_test/main.s b/tb/qumcu/isa/case/Bge_test/main.s new file mode 100644 index 0000000..51ddcc2 --- /dev/null +++ b/tb/qumcu/isa/case/Bge_test/main.s @@ -0,0 +1,13 @@ + +.global main +main: +lui x1,0x40 +lui x2,0x40 +lui x3,0x50 + +beq x1,x2,string1 +lui x4,0x60 +string1: +lui x5,0x70 +lui x6,0x80 +exit: diff --git a/tb/qumcu/isa/case/Bge_test/user.sv b/tb/qumcu/isa/case/Bge_test/user.sv new file mode 100644 index 0000000..136fc9c --- /dev/null +++ b/tb/qumcu/isa/case/Bge_test/user.sv @@ -0,0 +1,20 @@ + +initial begin + #10ns; + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[1].rfno0.rf_dfflr.qout_r == 32'h40000); + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[2].rfno0.rf_dfflr.qout_r == 32'h40000); + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[3].rfno0.rf_dfflr.qout_r == 32'h50000); + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[4].rfno0.rf_dfflr.qout_r == 32'h00000); + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[5].rfno0.rf_dfflr.qout_r == 32'h70000); + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[6].rfno0.rf_dfflr.qout_r == 32'h80000); + TEST_PASS; + +end + +initial begin + #100us; + $display("\n----------------------------------------\n"); + $display("\t Timeout Error !!!!\n"); + TEST_FAIL; +end + diff --git a/tb/qumcu/isa/case/Bgeu_bgeu_bgeu_test/main.c b/tb/qumcu/isa/case/Bgeu_bgeu_bgeu_test/main.c new file mode 100644 index 0000000..f92eb3f --- /dev/null +++ b/tb/qumcu/isa/case/Bgeu_bgeu_bgeu_test/main.c @@ -0,0 +1,20 @@ +//#include + + +//int main(){ +// printf("\t=====================================\n"); +// printf("\t hello world !!! \n"); +// printf("\t=====================================\n"); +//} + +void main(void){ + +unsigned int a,b; + a=5; + b=3; + //c=a+b; + //d=c+b; +} + + + diff --git a/tb/qumcu/isa/case/Bgeu_bgeu_bgeu_test/main.s b/tb/qumcu/isa/case/Bgeu_bgeu_bgeu_test/main.s new file mode 100644 index 0000000..d05ed02 --- /dev/null +++ b/tb/qumcu/isa/case/Bgeu_bgeu_bgeu_test/main.s @@ -0,0 +1,20 @@ +.global main +main: +addi x1,x0,-0x5 +addi x2,x0,-0x4 +lui x3,0x50 + +bgeu x2,x1,string1 +lui x4,0x60 +string1: +bgeu x2,x1,string2 +lui x5,0x70 +lui x6,0x80 +string2: +bgeu x2,x1,string3 +lui x5,0x77 +lui x6,0x88 +string3: +lui x5,0x99 +lui x6,0xaa +exit: diff --git a/tb/qumcu/isa/case/Bgeu_bgeu_bgeu_test/user.sv b/tb/qumcu/isa/case/Bgeu_bgeu_bgeu_test/user.sv new file mode 100644 index 0000000..05b73f7 --- /dev/null +++ b/tb/qumcu/isa/case/Bgeu_bgeu_bgeu_test/user.sv @@ -0,0 +1,20 @@ + +initial begin + #10ns; + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[1].rfno0.rf_dfflr.qout_r == 32'hffff_fffb); + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[2].rfno0.rf_dfflr.qout_r == 32'hffff_fffc); + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[3].rfno0.rf_dfflr.qout_r == 32'h50000); + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[4].rfno0.rf_dfflr.qout_r == 32'h00000); + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[5].rfno0.rf_dfflr.qout_r == 32'h99000); + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[6].rfno0.rf_dfflr.qout_r == 32'haa000); + TEST_PASS; + +end + +initial begin + #100us; + $display("\n----------------------------------------\n"); + $display("\t Timeout Error !!!!\n"); + TEST_FAIL; +end + diff --git a/tb/qumcu/isa/case/Bgeu_nbgeu_nbgeu_test/main.c b/tb/qumcu/isa/case/Bgeu_nbgeu_nbgeu_test/main.c new file mode 100644 index 0000000..f92eb3f --- /dev/null +++ b/tb/qumcu/isa/case/Bgeu_nbgeu_nbgeu_test/main.c @@ -0,0 +1,20 @@ +//#include + + +//int main(){ +// printf("\t=====================================\n"); +// printf("\t hello world !!! \n"); +// printf("\t=====================================\n"); +//} + +void main(void){ + +unsigned int a,b; + a=5; + b=3; + //c=a+b; + //d=c+b; +} + + + diff --git a/tb/qumcu/isa/case/Bgeu_nbgeu_nbgeu_test/main.s b/tb/qumcu/isa/case/Bgeu_nbgeu_nbgeu_test/main.s new file mode 100644 index 0000000..70844fc --- /dev/null +++ b/tb/qumcu/isa/case/Bgeu_nbgeu_nbgeu_test/main.s @@ -0,0 +1,21 @@ +.global main +main: +addi x1,x0,-0x5 +addi x2,x0,-0x4 +lui x3,0x50 + +bgeu x2,x1,string1 +lui x4,0x60 +string1: +addi x2,x0,-0x6 +bgeu x2,x1,string2 +lui x5,0x70 +lui x6,0x80 +string2: +bgeu x2,x1,string3 +lui x5,0x77 +lui x6,0x88 +string3: +lui x5,0x99 +lui x6,0xaa +exit: diff --git a/tb/qumcu/isa/case/Bgeu_nbgeu_nbgeu_test/user.sv b/tb/qumcu/isa/case/Bgeu_nbgeu_nbgeu_test/user.sv new file mode 100644 index 0000000..58e735e --- /dev/null +++ b/tb/qumcu/isa/case/Bgeu_nbgeu_nbgeu_test/user.sv @@ -0,0 +1,24 @@ + +initial begin + #10ns; + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[1].rfno0.rf_dfflr.qout_r == 32'hffff_fffb); + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[2].rfno0.rf_dfflr.qout_r == 32'hffff_fffc); + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[3].rfno0.rf_dfflr.qout_r == 32'h50000); + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[2].rfno0.rf_dfflr.qout_r == 32'hffff_fffa); + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[5].rfno0.rf_dfflr.qout_r == 32'h70000); + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[6].rfno0.rf_dfflr.qout_r == 32'h80000); + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[5].rfno0.rf_dfflr.qout_r == 32'h77000); + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[6].rfno0.rf_dfflr.qout_r == 32'h88000); + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[5].rfno0.rf_dfflr.qout_r == 32'h99000); + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[6].rfno0.rf_dfflr.qout_r == 32'haa000); + TEST_PASS; + +end + +initial begin + #100us; + $display("\n----------------------------------------\n"); + $display("\t Timeout Error !!!!\n"); + TEST_FAIL; +end + diff --git a/tb/qumcu/isa/case/Blt_blt_blt_test/main.c b/tb/qumcu/isa/case/Blt_blt_blt_test/main.c new file mode 100644 index 0000000..f92eb3f --- /dev/null +++ b/tb/qumcu/isa/case/Blt_blt_blt_test/main.c @@ -0,0 +1,20 @@ +//#include + + +//int main(){ +// printf("\t=====================================\n"); +// printf("\t hello world !!! \n"); +// printf("\t=====================================\n"); +//} + +void main(void){ + +unsigned int a,b; + a=5; + b=3; + //c=a+b; + //d=c+b; +} + + + diff --git a/tb/qumcu/isa/case/Blt_blt_blt_test/main.s b/tb/qumcu/isa/case/Blt_blt_blt_test/main.s new file mode 100644 index 0000000..f1a05df --- /dev/null +++ b/tb/qumcu/isa/case/Blt_blt_blt_test/main.s @@ -0,0 +1,20 @@ +.global main +main: +addi x1,x0,0x5 +addi x2,x0,0x4 +lui x3,0x50 + +blt x2,x1,string1 +lui x4,0x60 +string1: +blt x2,x1,string2 +lui x5,0x70 +lui x6,0x80 +string2: +blt x2,x1,string3 +lui x5,0x77 +lui x6,0x88 +string3: +lui x5,0x99 +lui x6,0xaa +exit: diff --git a/tb/qumcu/isa/case/Blt_blt_blt_test/user.sv b/tb/qumcu/isa/case/Blt_blt_blt_test/user.sv new file mode 100644 index 0000000..78d5590 --- /dev/null +++ b/tb/qumcu/isa/case/Blt_blt_blt_test/user.sv @@ -0,0 +1,20 @@ + +initial begin + #10ns; + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[1].rfno0.rf_dfflr.qout_r == 32'h5); + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[2].rfno0.rf_dfflr.qout_r == 32'h4); + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[3].rfno0.rf_dfflr.qout_r == 32'h50000); + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[4].rfno0.rf_dfflr.qout_r == 32'h00000); + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[5].rfno0.rf_dfflr.qout_r == 32'h99000); + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[6].rfno0.rf_dfflr.qout_r == 32'haa000); + TEST_PASS; + +end + +initial begin + #100us; + $display("\n----------------------------------------\n"); + $display("\t Timeout Error !!!!\n"); + TEST_FAIL; +end + diff --git a/tb/qumcu/isa/case/Blt_nblt_nblt_test/main.c b/tb/qumcu/isa/case/Blt_nblt_nblt_test/main.c new file mode 100644 index 0000000..f92eb3f --- /dev/null +++ b/tb/qumcu/isa/case/Blt_nblt_nblt_test/main.c @@ -0,0 +1,20 @@ +//#include + + +//int main(){ +// printf("\t=====================================\n"); +// printf("\t hello world !!! \n"); +// printf("\t=====================================\n"); +//} + +void main(void){ + +unsigned int a,b; + a=5; + b=3; + //c=a+b; + //d=c+b; +} + + + diff --git a/tb/qumcu/isa/case/Blt_nblt_nblt_test/main.s b/tb/qumcu/isa/case/Blt_nblt_nblt_test/main.s new file mode 100644 index 0000000..de81227 --- /dev/null +++ b/tb/qumcu/isa/case/Blt_nblt_nblt_test/main.s @@ -0,0 +1,21 @@ +.global main +main: +addi x1,x0,0x5 +addi x2,x0,0x4 +lui x3,0x50 + +blt x2,x1,string1 +lui x4,0x60 +string1: +addi x2,x0,0x6 +blt x2,x1,string2 +lui x5,0x70 +lui x6,0x80 +string2: +blt x2,x1,string3 +lui x5,0x77 +lui x6,0x88 +string3: +lui x5,0x99 +lui x6,0xaa +exit: diff --git a/tb/qumcu/isa/case/Blt_nblt_nblt_test/user.sv b/tb/qumcu/isa/case/Blt_nblt_nblt_test/user.sv new file mode 100644 index 0000000..c102c9a --- /dev/null +++ b/tb/qumcu/isa/case/Blt_nblt_nblt_test/user.sv @@ -0,0 +1,24 @@ + +initial begin + #10ns; + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[1].rfno0.rf_dfflr.qout_r == 32'h5); + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[2].rfno0.rf_dfflr.qout_r == 32'h4); + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[3].rfno0.rf_dfflr.qout_r == 32'h50000); + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[2].rfno0.rf_dfflr.qout_r == 32'h6); + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[5].rfno0.rf_dfflr.qout_r == 32'h70000); + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[6].rfno0.rf_dfflr.qout_r == 32'h80000); + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[5].rfno0.rf_dfflr.qout_r == 32'h77000); + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[6].rfno0.rf_dfflr.qout_r == 32'h88000); + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[5].rfno0.rf_dfflr.qout_r == 32'h99000); + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[6].rfno0.rf_dfflr.qout_r == 32'haa000); + TEST_PASS; + +end + +initial begin + #100us; + $display("\n----------------------------------------\n"); + $display("\t Timeout Error !!!!\n"); + TEST_FAIL; +end + diff --git a/tb/qumcu/isa/case/Bltu_bltu_bltu_test/main.c b/tb/qumcu/isa/case/Bltu_bltu_bltu_test/main.c new file mode 100644 index 0000000..f92eb3f --- /dev/null +++ b/tb/qumcu/isa/case/Bltu_bltu_bltu_test/main.c @@ -0,0 +1,20 @@ +//#include + + +//int main(){ +// printf("\t=====================================\n"); +// printf("\t hello world !!! \n"); +// printf("\t=====================================\n"); +//} + +void main(void){ + +unsigned int a,b; + a=5; + b=3; + //c=a+b; + //d=c+b; +} + + + diff --git a/tb/qumcu/isa/case/Bltu_bltu_bltu_test/main.s b/tb/qumcu/isa/case/Bltu_bltu_bltu_test/main.s new file mode 100644 index 0000000..9c4f4ac --- /dev/null +++ b/tb/qumcu/isa/case/Bltu_bltu_bltu_test/main.s @@ -0,0 +1,20 @@ +.global main +main: +addi x1,x0,-0x5 +addi x2,x0,-0x6 +lui x3,0x50 + +bltu x2,x1,string1 +lui x4,0x60 +string1: +bltu x2,x1,string2 +lui x5,0x70 +lui x6,0x80 +string2: +bltu x2,x1,string3 +lui x5,0x77 +lui x6,0x88 +string3: +lui x5,0x99 +lui x6,0xaa +exit: diff --git a/tb/qumcu/isa/case/Bltu_bltu_bltu_test/user.sv b/tb/qumcu/isa/case/Bltu_bltu_bltu_test/user.sv new file mode 100644 index 0000000..914a406 --- /dev/null +++ b/tb/qumcu/isa/case/Bltu_bltu_bltu_test/user.sv @@ -0,0 +1,20 @@ + +initial begin + #10ns; + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[1].rfno0.rf_dfflr.qout_r == 32'hffff_fffb); + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[2].rfno0.rf_dfflr.qout_r == 32'hffff_fffa); + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[3].rfno0.rf_dfflr.qout_r == 32'h50000); + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[4].rfno0.rf_dfflr.qout_r == 32'h00000); + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[5].rfno0.rf_dfflr.qout_r == 32'h99000); + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[6].rfno0.rf_dfflr.qout_r == 32'haa000); + TEST_PASS; + +end + +initial begin + #100us; + $display("\n----------------------------------------\n"); + $display("\t Timeout Error !!!!\n"); + TEST_FAIL; +end + diff --git a/tb/qumcu/isa/case/Bltu_nbltu_nbltu_test/main.c b/tb/qumcu/isa/case/Bltu_nbltu_nbltu_test/main.c new file mode 100644 index 0000000..f92eb3f --- /dev/null +++ b/tb/qumcu/isa/case/Bltu_nbltu_nbltu_test/main.c @@ -0,0 +1,20 @@ +//#include + + +//int main(){ +// printf("\t=====================================\n"); +// printf("\t hello world !!! \n"); +// printf("\t=====================================\n"); +//} + +void main(void){ + +unsigned int a,b; + a=5; + b=3; + //c=a+b; + //d=c+b; +} + + + diff --git a/tb/qumcu/isa/case/Bltu_nbltu_nbltu_test/main.s b/tb/qumcu/isa/case/Bltu_nbltu_nbltu_test/main.s new file mode 100644 index 0000000..a89ed36 --- /dev/null +++ b/tb/qumcu/isa/case/Bltu_nbltu_nbltu_test/main.s @@ -0,0 +1,21 @@ +.global main +main: +addi x1,x0,-0x5 +addi x2,x0,-0x6 +lui x3,0x50 + +bltu x2,x1,string1 +lui x4,0x60 +string1: +addi x2,x0,-0x4 +bltu x2,x1,string2 +lui x5,0x70 +lui x6,0x80 +string2: +bltu x2,x1,string3 +lui x5,0x77 +lui x6,0x88 +string3: +lui x5,0x99 +lui x6,0xaa +exit: diff --git a/tb/qumcu/isa/case/Bltu_nbltu_nbltu_test/user.sv b/tb/qumcu/isa/case/Bltu_nbltu_nbltu_test/user.sv new file mode 100644 index 0000000..8734ea6 --- /dev/null +++ b/tb/qumcu/isa/case/Bltu_nbltu_nbltu_test/user.sv @@ -0,0 +1,24 @@ + +initial begin + #10ns; + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[1].rfno0.rf_dfflr.qout_r == 32'hffff_fffb); + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[2].rfno0.rf_dfflr.qout_r == 32'hffff_fffa); + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[3].rfno0.rf_dfflr.qout_r == 32'h50000); + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[2].rfno0.rf_dfflr.qout_r == 32'hffff_fffc); + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[5].rfno0.rf_dfflr.qout_r == 32'h70000); + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[6].rfno0.rf_dfflr.qout_r == 32'h80000); + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[5].rfno0.rf_dfflr.qout_r == 32'h77000); + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[6].rfno0.rf_dfflr.qout_r == 32'h88000); + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[5].rfno0.rf_dfflr.qout_r == 32'h99000); + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[6].rfno0.rf_dfflr.qout_r == 32'haa000); + TEST_PASS; + +end + +initial begin + #100us; + $display("\n----------------------------------------\n"); + $display("\t Timeout Error !!!!\n"); + TEST_FAIL; +end + diff --git a/tb/qumcu/isa/case/Bne_bne_bne_test/main.c b/tb/qumcu/isa/case/Bne_bne_bne_test/main.c new file mode 100644 index 0000000..f92eb3f --- /dev/null +++ b/tb/qumcu/isa/case/Bne_bne_bne_test/main.c @@ -0,0 +1,20 @@ +//#include + + +//int main(){ +// printf("\t=====================================\n"); +// printf("\t hello world !!! \n"); +// printf("\t=====================================\n"); +//} + +void main(void){ + +unsigned int a,b; + a=5; + b=3; + //c=a+b; + //d=c+b; +} + + + diff --git a/tb/qumcu/isa/case/Bne_bne_bne_test/main.s b/tb/qumcu/isa/case/Bne_bne_bne_test/main.s new file mode 100644 index 0000000..eb6acee --- /dev/null +++ b/tb/qumcu/isa/case/Bne_bne_bne_test/main.s @@ -0,0 +1,20 @@ +.global main +main: +addi x1,x0,0x5 +addi x2,x0,0x4 +lui x3,0x50 + +bne x2,x1,string1 +lui x4,0x60 +string1: +bne x2,x1,string2 +lui x5,0x70 +lui x6,0x80 +string2: +bne x2,x1,string3 +lui x5,0x77 +lui x6,0x88 +string3: +lui x5,0x99 +lui x6,0xaa +exit: diff --git a/tb/qumcu/isa/case/Bne_bne_bne_test/user.sv b/tb/qumcu/isa/case/Bne_bne_bne_test/user.sv new file mode 100644 index 0000000..78d5590 --- /dev/null +++ b/tb/qumcu/isa/case/Bne_bne_bne_test/user.sv @@ -0,0 +1,20 @@ + +initial begin + #10ns; + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[1].rfno0.rf_dfflr.qout_r == 32'h5); + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[2].rfno0.rf_dfflr.qout_r == 32'h4); + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[3].rfno0.rf_dfflr.qout_r == 32'h50000); + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[4].rfno0.rf_dfflr.qout_r == 32'h00000); + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[5].rfno0.rf_dfflr.qout_r == 32'h99000); + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[6].rfno0.rf_dfflr.qout_r == 32'haa000); + TEST_PASS; + +end + +initial begin + #100us; + $display("\n----------------------------------------\n"); + $display("\t Timeout Error !!!!\n"); + TEST_FAIL; +end + diff --git a/tb/qumcu/isa/case/Bne_nbnen_nbne_test/main.c b/tb/qumcu/isa/case/Bne_nbnen_nbne_test/main.c new file mode 100644 index 0000000..f92eb3f --- /dev/null +++ b/tb/qumcu/isa/case/Bne_nbnen_nbne_test/main.c @@ -0,0 +1,20 @@ +//#include + + +//int main(){ +// printf("\t=====================================\n"); +// printf("\t hello world !!! \n"); +// printf("\t=====================================\n"); +//} + +void main(void){ + +unsigned int a,b; + a=5; + b=3; + //c=a+b; + //d=c+b; +} + + + diff --git a/tb/qumcu/isa/case/Bne_nbnen_nbne_test/main.s b/tb/qumcu/isa/case/Bne_nbnen_nbne_test/main.s new file mode 100644 index 0000000..52dd89a --- /dev/null +++ b/tb/qumcu/isa/case/Bne_nbnen_nbne_test/main.s @@ -0,0 +1,21 @@ +.global main +main: +addi x1,x0,-0x5 +addi x2,x0,-0x6 +lui x3,0x50 + +bltu x2,x1,string1 +lui x4,0x60 +string1: +addi x2,x0,-0x5 +bltu x2,x1,string2 +lui x5,0x70 +lui x6,0x80 +string2: +bltu x2,x1,string3 +lui x5,0x77 +lui x6,0x88 +string3: +lui x5,0x99 +lui x6,0xaa +exit: diff --git a/tb/qumcu/isa/case/Bne_nbnen_nbne_test/user.sv b/tb/qumcu/isa/case/Bne_nbnen_nbne_test/user.sv new file mode 100644 index 0000000..2957ed9 --- /dev/null +++ b/tb/qumcu/isa/case/Bne_nbnen_nbne_test/user.sv @@ -0,0 +1,24 @@ + +initial begin + #10ns; + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[1].rfno0.rf_dfflr.qout_r == 32'hffff_fffb); + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[2].rfno0.rf_dfflr.qout_r == 32'hffff_fffa); + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[3].rfno0.rf_dfflr.qout_r == 32'h50000); + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[2].rfno0.rf_dfflr.qout_r == 32'hffff_fffb); + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[5].rfno0.rf_dfflr.qout_r == 32'h70000); + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[6].rfno0.rf_dfflr.qout_r == 32'h80000); + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[5].rfno0.rf_dfflr.qout_r == 32'h77000); + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[6].rfno0.rf_dfflr.qout_r == 32'h88000); + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[5].rfno0.rf_dfflr.qout_r == 32'h99000); + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[6].rfno0.rf_dfflr.qout_r == 32'haa000); + TEST_PASS; + +end + +initial begin + #100us; + $display("\n----------------------------------------\n"); + $display("\t Timeout Error !!!!\n"); + TEST_FAIL; +end + diff --git a/tb/qumcu/isa/case/JR_test/main.c b/tb/qumcu/isa/case/JR_test/main.c new file mode 100644 index 0000000..f92eb3f --- /dev/null +++ b/tb/qumcu/isa/case/JR_test/main.c @@ -0,0 +1,20 @@ +//#include + + +//int main(){ +// printf("\t=====================================\n"); +// printf("\t hello world !!! \n"); +// printf("\t=====================================\n"); +//} + +void main(void){ + +unsigned int a,b; + a=5; + b=3; + //c=a+b; + //d=c+b; +} + + + diff --git a/tb/qumcu/isa/case/JR_test/main.s b/tb/qumcu/isa/case/JR_test/main.s new file mode 100644 index 0000000..9c9b198 --- /dev/null +++ b/tb/qumcu/isa/case/JR_test/main.s @@ -0,0 +1,16 @@ + + +.global main +main: +lui x3,0x100 +lui x6,0x1234 +auipc x7,0x8765 +sw x6,0x0(x3) +sw x7,0x4(x3) +jalr ra,0x18(x1) +sh x6,0x0(x3) +sh x7,0x4(x3) +string1: +sb x6,0x2(x3) +sb x7,0x7(x3) +exit: diff --git a/tb/qumcu/isa/case/JR_test/user.sv b/tb/qumcu/isa/case/JR_test/user.sv new file mode 100644 index 0000000..f88a6c6 --- /dev/null +++ b/tb/qumcu/isa/case/JR_test/user.sv @@ -0,0 +1,26 @@ +initial begin + #10ns; + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[1].rfno0.rf_dfflr.qout_r == 32'h18); + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[6].rfno0.rf_dfflr.qout_r == 32'h01234000); + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[7].rfno0.rf_dfflr.qout_r == 32'h08765008); + + wait(`TB_DRAM.mem[0] == 32'h01004000); + wait(`TB_DRAM.mem[1] == 32'h08765008); + + + TEST_PASS; + +end + +initial begin + #100us; + $display("\n"); + $display("*\tDDATA: 0x00: %h", `TB_DRAM.mem[0]); + $display("*\tDDATA: 0x04: %h", `TB_DRAM.mem[1]); + $display("\n----------------------------------------\n"); + $display("\t Timeout Error !!!!\n"); + TEST_FAIL; +end + + + diff --git a/tb/qumcu/isa/case/J_test/main.c b/tb/qumcu/isa/case/J_test/main.c new file mode 100644 index 0000000..f92eb3f --- /dev/null +++ b/tb/qumcu/isa/case/J_test/main.c @@ -0,0 +1,20 @@ +//#include + + +//int main(){ +// printf("\t=====================================\n"); +// printf("\t hello world !!! \n"); +// printf("\t=====================================\n"); +//} + +void main(void){ + +unsigned int a,b; + a=5; + b=3; + //c=a+b; + //d=c+b; +} + + + diff --git a/tb/qumcu/isa/case/J_test/main.s b/tb/qumcu/isa/case/J_test/main.s new file mode 100644 index 0000000..4c01671 --- /dev/null +++ b/tb/qumcu/isa/case/J_test/main.s @@ -0,0 +1,23 @@ + +.global main +main: +lui x3,0x100 +lui x6,0x1234 +auipc x7,0x8765 +sw x6,0x0(x3) +sw x7,0x4(x3) +jal ra,string1 +sh x6,0x0(x3) +sh x7,0x4(x3) +string1: +jal ra,string2 +sb x6,0x2(x3) +sb x7,0x7(x3) +string2: +jal ra,string3 +sb x6,0x2(x3) +sb x7,0x7(x3) +jal ra,string3 +sb x6,0x2(x3) +sb x7,0x7(x3) +exit: diff --git a/tb/qumcu/isa/case/J_test/user.sv b/tb/qumcu/isa/case/J_test/user.sv new file mode 100644 index 0000000..151bfa1 --- /dev/null +++ b/tb/qumcu/isa/case/J_test/user.sv @@ -0,0 +1,21 @@ + +initial begin + #10ns; + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[1].rfno0.rf_dfflr.qout_r == 32'h18); + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[6].rfno0.rf_dfflr.qout_r == 32'h01234000); + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[7].rfno0.rf_dfflr.qout_r == 32'h08765008); + + //wait(`TB_DRAM.ram[0] == 32'h01004000); + //wait(`TB_DRAM.ram[1] == 32'h04765004); + + TEST_PASS; + +end + +initial begin + #100us; + $display("\n----------------------------------------\n"); + $display("\t Timeout Error !!!!\n"); + TEST_FAIL; +end + diff --git a/tb/qumcu/isa/case/Jal_jal_jal_test/main.c b/tb/qumcu/isa/case/Jal_jal_jal_test/main.c new file mode 100644 index 0000000..f92eb3f --- /dev/null +++ b/tb/qumcu/isa/case/Jal_jal_jal_test/main.c @@ -0,0 +1,20 @@ +//#include + + +//int main(){ +// printf("\t=====================================\n"); +// printf("\t hello world !!! \n"); +// printf("\t=====================================\n"); +//} + +void main(void){ + +unsigned int a,b; + a=5; + b=3; + //c=a+b; + //d=c+b; +} + + + diff --git a/tb/qumcu/isa/case/Jal_jal_jal_test/main.s b/tb/qumcu/isa/case/Jal_jal_jal_test/main.s new file mode 100644 index 0000000..403405f --- /dev/null +++ b/tb/qumcu/isa/case/Jal_jal_jal_test/main.s @@ -0,0 +1,20 @@ +.global main +main: +addi x1,x0,0x5 +addi x2,x0,0x4 +lui x3,0x50 + +jal x1,string1 +lui x4,0x60 +string1: +jal x2,string2 +lui x5,0x70 +lui x6,0x80 +string2: +jal x3,string3 +lui x5,0x77 +lui x6,0x88 +string3: +lui x5,0x99 +lui x6,0xaa +exit: diff --git a/tb/qumcu/isa/case/Jal_jal_jal_test/user.sv b/tb/qumcu/isa/case/Jal_jal_jal_test/user.sv new file mode 100644 index 0000000..d7a71d8 --- /dev/null +++ b/tb/qumcu/isa/case/Jal_jal_jal_test/user.sv @@ -0,0 +1,22 @@ + +initial begin + #10ns; + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[1].rfno0.rf_dfflr.qout_r == 32'h5); + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[2].rfno0.rf_dfflr.qout_r == 32'h4); + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[3].rfno0.rf_dfflr.qout_r == 32'h50000); + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[1].rfno0.rf_dfflr.qout_r == 32'h10); + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[2].rfno0.rf_dfflr.qout_r == 32'h18); + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[3].rfno0.rf_dfflr.qout_r == 32'h24); + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[5].rfno0.rf_dfflr.qout_r == 32'h99000); + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[6].rfno0.rf_dfflr.qout_r == 32'haa000); + TEST_PASS; + +end + +initial begin + #100us; + $display("\n----------------------------------------\n"); + $display("\t Timeout Error !!!!\n"); + TEST_FAIL; +end + diff --git a/tb/qumcu/isa/case/Jalr_jalr_jalr_test/main.c b/tb/qumcu/isa/case/Jalr_jalr_jalr_test/main.c new file mode 100644 index 0000000..f92eb3f --- /dev/null +++ b/tb/qumcu/isa/case/Jalr_jalr_jalr_test/main.c @@ -0,0 +1,20 @@ +//#include + + +//int main(){ +// printf("\t=====================================\n"); +// printf("\t hello world !!! \n"); +// printf("\t=====================================\n"); +//} + +void main(void){ + +unsigned int a,b; + a=5; + b=3; + //c=a+b; + //d=c+b; +} + + + diff --git a/tb/qumcu/isa/case/Jalr_jalr_jalr_test/main.s b/tb/qumcu/isa/case/Jalr_jalr_jalr_test/main.s new file mode 100644 index 0000000..10618c7 --- /dev/null +++ b/tb/qumcu/isa/case/Jalr_jalr_jalr_test/main.s @@ -0,0 +1,20 @@ +.global main +main: +addi x1,x0,0x5 +addi x2,x0,0x4 +lui x3,0x50 + +jalr x1,0x14(x0) +lui x4,0x60 +string1: +jalr x2,0x20(x0) +lui x5,0x70 +lui x6,0x80 +string2: +jalr x3,0x2c(x0) +lui x5,0x77 +lui x6,0x88 +string3: +lui x5,0x99 +lui x6,0xaa +exit: diff --git a/tb/qumcu/isa/case/Jalr_jalr_jalr_test/user.sv b/tb/qumcu/isa/case/Jalr_jalr_jalr_test/user.sv new file mode 100644 index 0000000..d7a71d8 --- /dev/null +++ b/tb/qumcu/isa/case/Jalr_jalr_jalr_test/user.sv @@ -0,0 +1,22 @@ + +initial begin + #10ns; + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[1].rfno0.rf_dfflr.qout_r == 32'h5); + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[2].rfno0.rf_dfflr.qout_r == 32'h4); + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[3].rfno0.rf_dfflr.qout_r == 32'h50000); + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[1].rfno0.rf_dfflr.qout_r == 32'h10); + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[2].rfno0.rf_dfflr.qout_r == 32'h18); + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[3].rfno0.rf_dfflr.qout_r == 32'h24); + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[5].rfno0.rf_dfflr.qout_r == 32'h99000); + wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[6].rfno0.rf_dfflr.qout_r == 32'haa000); + TEST_PASS; + +end + +initial begin + #100us; + $display("\n----------------------------------------\n"); + $display("\t Timeout Error !!!!\n"); + TEST_FAIL; +end + diff --git a/tb/qumcu/isa/case/Lb_test/main.c b/tb/qumcu/isa/case/Lb_test/main.c new file mode 100644 index 0000000..f92eb3f --- /dev/null +++ b/tb/qumcu/isa/case/Lb_test/main.c @@ -0,0 +1,20 @@ +//#include + + +//int main(){ +// printf("\t=====================================\n"); +// printf("\t hello world !!! \n"); +// printf("\t=====================================\n"); +//} + +void main(void){ + +unsigned int a,b; + a=5; + b=3; + //c=a+b; + //d=c+b; +} + + + diff --git a/tb/qumcu/isa/case/Lb_test/main.s b/tb/qumcu/isa/case/Lb_test/main.s new file mode 100644 index 0000000..75e3dba --- /dev/null +++ b/tb/qumcu/isa/case/Lb_test/main.s @@ -0,0 +1,17 @@ +lui x3,0x87654 +addi x3,x3,0x321 +lui x4,0xfedcb +addi x4,x4,0x765 +lui x1,0x100 +sw x3,0x0(x1) +sw x4,0x4(x1) +lb x8,0x0(x1) +lb x9,0x1(x1) +lb x10,0x2(x1) +lb x11,0x3(x1) +lb x12,0x4(x1) +lb x13,0x5(x1) +lb x14,0x6(x1) +lb x15,0x7(x1) +exit: + diff --git a/tb/qumcu/isa/case/Lb_test/user.sv b/tb/qumcu/isa/case/Lb_test/user.sv new file mode 100644 index 0000000..d0fff5a --- /dev/null +++ b/tb/qumcu/isa/case/Lb_test/user.sv @@ -0,0 +1,95 @@ + +wire ram_clk = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CLK; +wire ram_cs = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CEBA; +wire reg_clk = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.clk; +wire reg_en = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_wen; +reg ram_cs_dly1 ; +reg reg_en_dly1 ; +always @(posedge ram_clk) begin + ram_cs_dly1 <= ~ram_cs; + reg_en_dly1 <= reg_en; +end + + +initial begin + #1ns; + //@(posedge ram_cs_dly1 ); + #5ns; + //while(1)begin + #1ns; + REGFILE_CHECK(6'd3,32'h8765_4000); + REGFILE_CHECK(6'd3,32'h8765_4321); + REGFILE_CHECK(6'd4,32'hfedc_b000); + REGFILE_CHECK(6'd4,32'hfedc_b765); + REGFILE_CHECK(6'd1,32'h0010_0000); + DRAM_DATA_CHECK(10'd0,32'h8765_4321); + DRAM_DATA_CHECK(10'd1,32'hfedc_b765); + //@(posedge reg_en_dly1 ); + REGFILE_CHECK(6'd8,32'h0000_0021); + REGFILE_CHECK(6'd9,32'h0000_0043); + REGFILE_CHECK(6'd10,32'h0000_0065); + REGFILE_CHECK(6'd11,32'hffff_ff87); + REGFILE_CHECK(6'd12,32'h0000_0065); + REGFILE_CHECK(6'd13,32'hffff_ffb7); + REGFILE_CHECK(6'd14,32'hffff_ffdc); + REGFILE_CHECK(6'd15,32'hffff_fffe); + + #10us; + TEST_PASS; +end + +task DRAM_DATA_CHECK; + input [9:0] addr ; + input [31:0] edata ; + + logic [31:0] ram_data; + + @(posedge ram_cs_dly1 ); + @(posedge ram_clk ); + //$monitor($time, " Simulation time: %t", $time); + if(ram_cs_dly1) begin + ram_data = `TB_DRAM.mem[addr]; + //$display("* RAM_DATA[%x]: %x | EXP_DATA: %x ",addr,ram_data, edata); + if(ram_data !== edata) begin + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,ram_data, edata); + #1us; + TEST_FAIL; + end + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, ram_data, edata); + end + else begin + $display("* DRAM CS is High => Error!!!"); + TEST_FAIL; + end +endtask + +task REGFILE_CHECK; + input [4:0] addr ; + input [31:0] edata ; + + logic [31:0] reg_data; + @(posedge reg_en ); + @(posedge reg_clk); + if(reg_en)begin + reg_data = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_dat; + if(reg_data !== edata) begin + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,reg_data, edata); + #1us; + //TEST_FAIL; + end + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, reg_data, edata); + end + else begin + $display("* REG WR EN is High => Error!!!"); + //TEST_FAIL; + end + +endtask + +initial begin + #100us; + $display("\n----------------------------------------\n"); + $display("\t Timeout Error !!!!\n"); + TEST_FAIL; +end + diff --git a/tb/qumcu/isa/case/Lbu_test/main.c b/tb/qumcu/isa/case/Lbu_test/main.c new file mode 100644 index 0000000..f92eb3f --- /dev/null +++ b/tb/qumcu/isa/case/Lbu_test/main.c @@ -0,0 +1,20 @@ +//#include + + +//int main(){ +// printf("\t=====================================\n"); +// printf("\t hello world !!! \n"); +// printf("\t=====================================\n"); +//} + +void main(void){ + +unsigned int a,b; + a=5; + b=3; + //c=a+b; + //d=c+b; +} + + + diff --git a/tb/qumcu/isa/case/Lbu_test/main.s b/tb/qumcu/isa/case/Lbu_test/main.s new file mode 100644 index 0000000..a70c0c3 --- /dev/null +++ b/tb/qumcu/isa/case/Lbu_test/main.s @@ -0,0 +1,17 @@ +lui x3,0x87654 +addi x3,x3,0x321 +lui x4,0xfedcb +addi x4,x4,0x765 +lui x1,0x100 +sw x3,0x0(x1) +sw x4,0x4(x1) +lbu x8,0x0(x1) +lbu x9,0x1(x1) +lbu x10,0x2(x1) +lbu x11,0x3(x1) +lbu x12,0x4(x1) +lbu x13,0x5(x1) +lbu x14,0x6(x1) +lbu x15,0x7(x1) +exit: + diff --git a/tb/qumcu/isa/case/Lbu_test/user.sv b/tb/qumcu/isa/case/Lbu_test/user.sv new file mode 100644 index 0000000..2dd9b11 --- /dev/null +++ b/tb/qumcu/isa/case/Lbu_test/user.sv @@ -0,0 +1,95 @@ + +wire ram_clk = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CLK; +wire ram_cs = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CEBA; +wire reg_clk = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.clk; +wire reg_en = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_wen; +reg ram_cs_dly1 ; +reg reg_en_dly1 ; +always @(posedge ram_clk) begin + ram_cs_dly1 <= ~ram_cs; + reg_en_dly1 <= reg_en; +end + + +initial begin + #1ns; + //@(posedge ram_cs_dly1 ); + #5ns; + //while(1)begin + #1ns; + REGFILE_CHECK(6'd3,32'h8765_4000); + REGFILE_CHECK(6'd3,32'h8765_4321); + REGFILE_CHECK(6'd4,32'hfedc_b000); + REGFILE_CHECK(6'd4,32'hfedc_b765); + REGFILE_CHECK(6'd1,32'h0010_0000); + DRAM_DATA_CHECK(10'd0,32'h8765_4321); + DRAM_DATA_CHECK(10'd1,32'hfedc_b765); + //@(posedge reg_en_dly1 ); + REGFILE_CHECK(6'd8,32'h0000_0021); + REGFILE_CHECK(6'd9,32'h0000_0043); + REGFILE_CHECK(6'd10,32'h0000_0065); + REGFILE_CHECK(6'd11,32'h0000_0087); + REGFILE_CHECK(6'd12,32'h0000_0065); + REGFILE_CHECK(6'd13,32'h0000_00b7); + REGFILE_CHECK(6'd14,32'h0000_00dc); + REGFILE_CHECK(6'd15,32'h0000_00fe); + + #10us; + TEST_PASS; +end + +task DRAM_DATA_CHECK; + input [9:0] addr ; + input [31:0] edata ; + + logic [31:0] ram_data; + + @(posedge ram_cs_dly1 ); + @(posedge ram_clk ); + //$monitor($time, " Simulation time: %t", $time); + if(ram_cs_dly1) begin + ram_data = `TB_DRAM.mem[addr]; + //$display("* RAM_DATA[%x]: %x | EXP_DATA: %x ",addr,ram_data, edata); + if(ram_data !== edata) begin + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,ram_data, edata); + #1us; + TEST_FAIL; + end + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, ram_data, edata); + end + else begin + $display("* DRAM CS is High => Error!!!"); + TEST_FAIL; + end +endtask + +task REGFILE_CHECK; + input [4:0] addr ; + input [31:0] edata ; + + logic [31:0] reg_data; + @(posedge reg_en ); + @(posedge reg_clk); + if(reg_en)begin + reg_data = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_dat; + if(reg_data !== edata) begin + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,reg_data, edata); + #1us; + //TEST_FAIL; + end + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, reg_data, edata); + end + else begin + $display("* REG WR EN is High => Error!!!"); + //TEST_FAIL; + end + +endtask + +initial begin + #100us; + $display("\n----------------------------------------\n"); + $display("\t Timeout Error !!!!\n"); + TEST_FAIL; +end + diff --git a/tb/qumcu/isa/case/Lh_test/main.c b/tb/qumcu/isa/case/Lh_test/main.c new file mode 100644 index 0000000..f92eb3f --- /dev/null +++ b/tb/qumcu/isa/case/Lh_test/main.c @@ -0,0 +1,20 @@ +//#include + + +//int main(){ +// printf("\t=====================================\n"); +// printf("\t hello world !!! \n"); +// printf("\t=====================================\n"); +//} + +void main(void){ + +unsigned int a,b; + a=5; + b=3; + //c=a+b; + //d=c+b; +} + + + diff --git a/tb/qumcu/isa/case/Lh_test/main.s b/tb/qumcu/isa/case/Lh_test/main.s new file mode 100644 index 0000000..f683a99 --- /dev/null +++ b/tb/qumcu/isa/case/Lh_test/main.s @@ -0,0 +1,17 @@ +lui x3,0x87654 +addi x3,x3,0x321 +lui x4,0xfedcb +addi x4,x4,0x765 +lui x1,0x100 +sw x3,0x0(x1) +sw x4,0x4(x1) +lh x8,0x0(x1) +lh x9,0x0(x1) +lh x10,0x2(x1) +lh x11,0x2(x1) +lh x12,0x4(x1) +lh x13,0x4(x1) +lh x14,0x6(x1) +lh x15,0x6(x1) +exit: + diff --git a/tb/qumcu/isa/case/Lh_test/user.sv b/tb/qumcu/isa/case/Lh_test/user.sv new file mode 100644 index 0000000..4322037 --- /dev/null +++ b/tb/qumcu/isa/case/Lh_test/user.sv @@ -0,0 +1,95 @@ + +wire ram_clk = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CLK; +wire ram_cs = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CEBA; +wire reg_clk = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.clk; +wire reg_en = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_wen; +reg ram_cs_dly1 ; +reg reg_en_dly1 ; +always @(posedge ram_clk) begin + ram_cs_dly1 <= ~ram_cs; + reg_en_dly1 <= reg_en; +end + + +initial begin + #1ns; + //@(posedge ram_cs_dly1 ); + #5ns; + //while(1)begin + #1ns; + REGFILE_CHECK(6'd3,32'h8765_4000); + REGFILE_CHECK(6'd3,32'h8765_4321); + REGFILE_CHECK(6'd4,32'hfedc_b000); + REGFILE_CHECK(6'd4,32'hfedc_b765); + REGFILE_CHECK(6'd1,32'h0010_0000); + DRAM_DATA_CHECK(10'd0,32'h8765_4321); + DRAM_DATA_CHECK(10'd1,32'hfedc_b765); + //@(posedge reg_en_dly1 ); + REGFILE_CHECK(6'd8,32'h0000_4321); + REGFILE_CHECK(6'd9,32'h0000_4321); + REGFILE_CHECK(6'd10,32'hffff_8765); + REGFILE_CHECK(6'd11,32'hffff_8765); + REGFILE_CHECK(6'd12,32'hffff_b765); + REGFILE_CHECK(6'd13,32'hffff_b765); + REGFILE_CHECK(6'd14,32'hffff_fedc); + REGFILE_CHECK(6'd15,32'hffff_fedc); + + #10us; + TEST_PASS; +end + +task DRAM_DATA_CHECK; + input [9:0] addr ; + input [31:0] edata ; + + logic [31:0] ram_data; + + @(posedge ram_cs_dly1 ); + @(posedge ram_clk ); + //$monitor($time, " Simulation time: %t", $time); + if(ram_cs_dly1) begin + ram_data = `TB_DRAM.mem[addr]; + //$display("* RAM_DATA[%x]: %x | EXP_DATA: %x ",addr,ram_data, edata); + if(ram_data !== edata) begin + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,ram_data, edata); + #1us; + TEST_FAIL; + end + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, ram_data, edata); + end + else begin + $display("* DRAM CS is High => Error!!!"); + TEST_FAIL; + end +endtask + +task REGFILE_CHECK; + input [4:0] addr ; + input [31:0] edata ; + + logic [31:0] reg_data; + @(posedge reg_en ); + @(posedge reg_clk); + if(reg_en)begin + reg_data = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_dat; + if(reg_data !== edata) begin + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,reg_data, edata); + #1us; + //TEST_FAIL; + end + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, reg_data, edata); + end + else begin + $display("* REG WR EN is High => Error!!!"); + //TEST_FAIL; + end + +endtask + +initial begin + #100us; + $display("\n----------------------------------------\n"); + $display("\t Timeout Error !!!!\n"); + TEST_FAIL; +end + diff --git a/tb/qumcu/isa/case/Lh_unalgn_test/main.c b/tb/qumcu/isa/case/Lh_unalgn_test/main.c new file mode 100644 index 0000000..f92eb3f --- /dev/null +++ b/tb/qumcu/isa/case/Lh_unalgn_test/main.c @@ -0,0 +1,20 @@ +//#include + + +//int main(){ +// printf("\t=====================================\n"); +// printf("\t hello world !!! \n"); +// printf("\t=====================================\n"); +//} + +void main(void){ + +unsigned int a,b; + a=5; + b=3; + //c=a+b; + //d=c+b; +} + + + diff --git a/tb/qumcu/isa/case/Lh_unalgn_test/main.s b/tb/qumcu/isa/case/Lh_unalgn_test/main.s new file mode 100644 index 0000000..9920ce8 --- /dev/null +++ b/tb/qumcu/isa/case/Lh_unalgn_test/main.s @@ -0,0 +1,17 @@ +lui x3,0x87654 +addi x3,x3,0x321 +lui x4,0xfedcb +addi x4,x4,0x765 +lui x1,0x100 +sw x3,0x0(x1) +sw x4,0x4(x1) +lh x8,0x0(x1) +lh x9,0x1(x1) +lh x10,0x2(x1) +lh x11,0x3(x1) +lh x12,0x4(x1) +lh x13,0x5(x1) +lh x14,0x6(x1) +lh x15,0x7(x1) +exit: + diff --git a/tb/qumcu/isa/case/Lh_unalgn_test/user.sv b/tb/qumcu/isa/case/Lh_unalgn_test/user.sv new file mode 100644 index 0000000..d7dd731 --- /dev/null +++ b/tb/qumcu/isa/case/Lh_unalgn_test/user.sv @@ -0,0 +1,95 @@ + +wire ram_clk = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CLK; +wire ram_cs = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CEBA; +wire reg_clk = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.clk; +wire reg_en = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_wen; +reg ram_cs_dly1 ; +reg reg_en_dly1 ; +always @(posedge ram_clk) begin + ram_cs_dly1 <= ~ram_cs; + reg_en_dly1 <= reg_en; +end + + +initial begin + #1ns; + //@(posedge ram_cs_dly1 ); + #5ns; + //while(1)begin + #1ns; + REGFILE_CHECK(6'd3,32'h8765_4000); + REGFILE_CHECK(6'd3,32'h8765_4321); + REGFILE_CHECK(6'd4,32'hfedc_b000); + REGFILE_CHECK(6'd4,32'hfedc_b765); + REGFILE_CHECK(6'd1,32'h0010_0000); + DRAM_DATA_CHECK(10'd0,32'h8765_4321); + DRAM_DATA_CHECK(10'd1,32'hfedc_b765); + //@(posedge reg_en_dly1 ); + REGFILE_CHECK(6'd8,32'h0000_4321); + REGFILE_CHECK(6'd9,32'h0000_6543); + REGFILE_CHECK(6'd10,32'hffff_8765); + REGFILE_CHECK(6'd11,32'h0000_6587); + REGFILE_CHECK(6'd12,32'hffff_b765); + REGFILE_CHECK(6'd13,32'hffff_dcb7); + REGFILE_CHECK(6'd14,32'hffff_fedc); + REGFILE_CHECK(6'd15,32'h0000_00fe); + + #10us; + TEST_PASS; +end + +task DRAM_DATA_CHECK; + input [9:0] addr ; + input [31:0] edata ; + + logic [31:0] ram_data; + + @(posedge ram_cs_dly1 ); + @(posedge ram_clk ); + //$monitor($time, " Simulation time: %t", $time); + if(ram_cs_dly1) begin + ram_data = `TB_DRAM.mem[addr]; + //$display("* RAM_DATA[%x]: %x | EXP_DATA: %x ",addr,ram_data, edata); + if(ram_data !== edata) begin + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,ram_data, edata); + #1us; + TEST_FAIL; + end + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, ram_data, edata); + end + else begin + $display("* DRAM CS is High => Error!!!"); + TEST_FAIL; + end +endtask + +task REGFILE_CHECK; + input [4:0] addr ; + input [31:0] edata ; + + logic [31:0] reg_data; + @(posedge reg_en ); + @(posedge reg_clk); + if(reg_en)begin + reg_data = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_dat; + if(reg_data !== edata) begin + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,reg_data, edata); + #1us; + //TEST_FAIL; + end + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, reg_data, edata); + end + else begin + $display("* REG WR EN is High => Error!!!"); + //TEST_FAIL; + end + +endtask + +initial begin + #100us; + $display("\n----------------------------------------\n"); + $display("\t Timeout Error !!!!\n"); + TEST_FAIL; +end + diff --git a/tb/qumcu/isa/case/Lhu_test/main.c b/tb/qumcu/isa/case/Lhu_test/main.c new file mode 100644 index 0000000..f92eb3f --- /dev/null +++ b/tb/qumcu/isa/case/Lhu_test/main.c @@ -0,0 +1,20 @@ +//#include + + +//int main(){ +// printf("\t=====================================\n"); +// printf("\t hello world !!! \n"); +// printf("\t=====================================\n"); +//} + +void main(void){ + +unsigned int a,b; + a=5; + b=3; + //c=a+b; + //d=c+b; +} + + + diff --git a/tb/qumcu/isa/case/Lhu_test/main.s b/tb/qumcu/isa/case/Lhu_test/main.s new file mode 100644 index 0000000..6f3fe4f --- /dev/null +++ b/tb/qumcu/isa/case/Lhu_test/main.s @@ -0,0 +1,17 @@ +lui x3,0x87654 +addi x3,x3,0x321 +lui x4,0xfedcb +addi x4,x4,0x765 +lui x1,0x100 +sw x3,0x0(x1) +sw x4,0x4(x1) +lhu x8,0x0(x1) +lhu x9,0x0(x1) +lhu x10,0x2(x1) +lhu x11,0x2(x1) +lhu x12,0x4(x1) +lhu x13,0x4(x1) +lhu x14,0x6(x1) +lhu x15,0x6(x1) +exit: + diff --git a/tb/qumcu/isa/case/Lhu_test/user.sv b/tb/qumcu/isa/case/Lhu_test/user.sv new file mode 100644 index 0000000..3abbc77 --- /dev/null +++ b/tb/qumcu/isa/case/Lhu_test/user.sv @@ -0,0 +1,95 @@ + +wire ram_clk = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CLK; +wire ram_cs = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CEBA; +wire reg_clk = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.clk; +wire reg_en = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_wen; +reg ram_cs_dly1 ; +reg reg_en_dly1 ; +always @(posedge ram_clk) begin + ram_cs_dly1 <= ~ram_cs; + reg_en_dly1 <= reg_en; +end + + +initial begin + #1ns; + //@(posedge ram_cs_dly1 ); + #5ns; + //while(1)begin + #1ns; + REGFILE_CHECK(6'd3,32'h8765_4000); + REGFILE_CHECK(6'd3,32'h8765_4321); + REGFILE_CHECK(6'd4,32'hfedc_b000); + REGFILE_CHECK(6'd4,32'hfedc_b765); + REGFILE_CHECK(6'd1,32'h0010_0000); + DRAM_DATA_CHECK(10'd0,32'h8765_4321); + DRAM_DATA_CHECK(10'd1,32'hfedc_b765); + //@(posedge reg_en_dly1 ); + REGFILE_CHECK(6'd8,32'h0000_4321); + REGFILE_CHECK(6'd9,32'h0000_4321); + REGFILE_CHECK(6'd10,32'h0000_8765); + REGFILE_CHECK(6'd11,32'h0000_8765); + REGFILE_CHECK(6'd12,32'h0000_b765); + REGFILE_CHECK(6'd13,32'h0000_b765); + REGFILE_CHECK(6'd14,32'h0000_fedc); + REGFILE_CHECK(6'd15,32'h0000_fedc); + + #10us; + TEST_PASS; +end + +task DRAM_DATA_CHECK; + input [9:0] addr ; + input [31:0] edata ; + + logic [31:0] ram_data; + + @(posedge ram_cs_dly1 ); + @(posedge ram_clk ); + //$monitor($time, " Simulation time: %t", $time); + if(ram_cs_dly1) begin + ram_data = `TB_DRAM.mem[addr]; + //$display("* RAM_DATA[%x]: %x | EXP_DATA: %x ",addr,ram_data, edata); + if(ram_data !== edata) begin + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,ram_data, edata); + #1us; + TEST_FAIL; + end + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, ram_data, edata); + end + else begin + $display("* DRAM CS is High => Error!!!"); + TEST_FAIL; + end +endtask + +task REGFILE_CHECK; + input [4:0] addr ; + input [31:0] edata ; + + logic [31:0] reg_data; + @(posedge reg_en ); + @(posedge reg_clk); + if(reg_en)begin + reg_data = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_dat; + if(reg_data !== edata) begin + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,reg_data, edata); + #1us; + //TEST_FAIL; + end + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, reg_data, edata); + end + else begin + $display("* REG WR EN is High => Error!!!"); + //TEST_FAIL; + end + +endtask + +initial begin + #100us; + $display("\n----------------------------------------\n"); + $display("\t Timeout Error !!!!\n"); + TEST_FAIL; +end + diff --git a/tb/qumcu/isa/case/Load_test/main.c b/tb/qumcu/isa/case/Load_test/main.c new file mode 100644 index 0000000..f92eb3f --- /dev/null +++ b/tb/qumcu/isa/case/Load_test/main.c @@ -0,0 +1,20 @@ +//#include + + +//int main(){ +// printf("\t=====================================\n"); +// printf("\t hello world !!! \n"); +// printf("\t=====================================\n"); +//} + +void main(void){ + +unsigned int a,b; + a=5; + b=3; + //c=a+b; + //d=c+b; +} + + + diff --git a/tb/qumcu/isa/case/Load_test/main.s b/tb/qumcu/isa/case/Load_test/main.s new file mode 100644 index 0000000..44a0424 --- /dev/null +++ b/tb/qumcu/isa/case/Load_test/main.s @@ -0,0 +1,27 @@ +.option norvc +lui x1,0xfffff +addi x2,x0,0xff +slli x3,x2,4 +addi x3,x3,0xf +add x4,x3,x1 +auipc x5,0xfff +lui x11,0x100 +sw x5,0x0(x11) +sw x5,0x4(x11) +sw x5,0x8(x11) +sw x5,0xC(x11) +sw x5,0x10(x11) + +sb x5,0x1(x11) +sb x5,0x6(x11) +sb x5,0xB(x11) + +sh x5,0xC(x11) +sh x5,0x12(x11) + +lw x6,0x0(x11) +lh x7,0x4(x11) +lb x8,0x2(x11) +lhu x9,0x4(x11) +lbu x10,0x2(x11) + diff --git a/tb/qumcu/isa/case/Load_test/user.sv b/tb/qumcu/isa/case/Load_test/user.sv new file mode 100644 index 0000000..4e2baf9 --- /dev/null +++ b/tb/qumcu/isa/case/Load_test/user.sv @@ -0,0 +1,96 @@ + +wire ram_clk = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CLK; +wire ram_cs = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CEBA; +wire reg_clk = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.clk; +wire reg_en = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_wen; +reg ram_cs_dly1 ; +reg reg_en_dly1 ; +always @(posedge ram_clk) begin + ram_cs_dly1 <= ~ram_cs; + reg_en_dly1 <= reg_en; +end + + +initial begin + #1ns; + //@(posedge ram_cs_dly1 ); + #5ns; + //while(1)begin + #1ns; + + DRAM_DATA_CHECK(10'd0,32'h00ff_f014); + DRAM_DATA_CHECK(10'd1,32'h00ff_f014); + DRAM_DATA_CHECK(10'd2,32'h00ff_f014); + DRAM_DATA_CHECK(10'd3,32'h00ff_f014); + DRAM_DATA_CHECK(10'd4,32'h00ff_f014); + + DRAM_DATA_CHECK(10'd0,32'h00ff_1414); + DRAM_DATA_CHECK(10'd1,32'h0014_f014); + DRAM_DATA_CHECK(10'd2,32'h14FF_f014); + DRAM_DATA_CHECK(10'd3,32'h00ff_f014); + DRAM_DATA_CHECK(10'd4,32'hf014_f014); + //@(posedge reg_en_dly1 ); + REGFILE_CHECK(6'd6,32'h00ff_1414); + REGFILE_CHECK(6'd7,32'hffff_f014); + REGFILE_CHECK(6'd8,32'hffff_ffff); + REGFILE_CHECK(6'd9,32'h0000_f014); + REGFILE_CHECK(6'd10,32'h0000_00ff); + #10us; + TEST_PASS; +end + +task DRAM_DATA_CHECK; + input [9:0] addr ; + input [31:0] edata ; + + logic [31:0] ram_data; + + @(posedge ram_cs_dly1 ); + @(posedge ram_clk ); + //$monitor($time, " Simulation time: %t", $time); + if(ram_cs_dly1) begin + ram_data = `TB_DRAM.mem[addr]; + //$display("* RAM_DATA[%x]: %x | EXP_DATA: %x ",addr,ram_data, edata); + if(ram_data !== edata) begin + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,ram_data, edata); + #1us; + TEST_FAIL; + end + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, ram_data, edata); + end + else begin + $display("* DRAM CS is High => Error!!!"); + TEST_FAIL; + end +endtask + +task REGFILE_CHECK; + input [4:0] addr ; + input [31:0] edata ; + + logic [31:0] reg_data; + @(posedge reg_en ); + @(posedge reg_clk); + if(reg_en)begin + reg_data = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_dat; + if(reg_data !== edata) begin + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,reg_data, edata); + #1us; + //TEST_FAIL; + end + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, reg_data, edata); + end + else begin + $display("* REG WR EN is High => Error!!!"); + //TEST_FAIL; + end + +endtask + +initial begin + #100us; + $display("\n----------------------------------------\n"); + $display("\t Timeout Error !!!!\n"); + TEST_FAIL; +end + diff --git a/tb/qumcu/isa/case/Lui_0x0_test/main.c b/tb/qumcu/isa/case/Lui_0x0_test/main.c new file mode 100644 index 0000000..f92eb3f --- /dev/null +++ b/tb/qumcu/isa/case/Lui_0x0_test/main.c @@ -0,0 +1,20 @@ +//#include + + +//int main(){ +// printf("\t=====================================\n"); +// printf("\t hello world !!! \n"); +// printf("\t=====================================\n"); +//} + +void main(void){ + +unsigned int a,b; + a=5; + b=3; + //c=a+b; + //d=c+b; +} + + + diff --git a/tb/qumcu/isa/case/Lui_0x0_test/main.s b/tb/qumcu/isa/case/Lui_0x0_test/main.s new file mode 100644 index 0000000..08c1fb7 --- /dev/null +++ b/tb/qumcu/isa/case/Lui_0x0_test/main.s @@ -0,0 +1,31 @@ +li x1, 0x0 +li x2, 0x0 +li x3, 0x0 +li x4, 0x0 +li x5, 0x0 +li x6, 0x0 +li x7, 0x0 +li x8, 0x0 +li x9, 0x0 +li x10,0x0 +li x11,0x0 +li x12,0x0 +li x13,0x0 +li x14,0x0 +li x15,0x0 +li x16,0x0 +li x17,0x0 +li x18,0x0 +li x19,0x0 +li x20,0x0 +li x21,0x0 +li x22,0x0 +li x23,0x0 +li x24,0x0 +li x25,0x0 +li x26,0x0 +li x27,0x0 +li x28,0x0 +li x29,0x0 +li x30,0x0 +li x31,0x0 \ No newline at end of file diff --git a/tb/qumcu/isa/case/Lui_0x0_test/user.sv b/tb/qumcu/isa/case/Lui_0x0_test/user.sv new file mode 100644 index 0000000..f7e3d4b --- /dev/null +++ b/tb/qumcu/isa/case/Lui_0x0_test/user.sv @@ -0,0 +1,110 @@ + +wire ram_clk = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CLK; +wire ram_cs = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CEBA; +wire reg_clk = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.clk; +wire reg_en = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_wen; +reg ram_cs_dly1 ; +reg reg_en_dly1 ; +always @(posedge ram_clk) begin + ram_cs_dly1 <= ~ram_cs; + reg_en_dly1 <= reg_en; +end + + +initial begin + #1ns; + //@(posedge ram_cs_dly1 ); + #5ns; + //while(1)begin + #1ns; + //@(posedge reg_en_dly1 ); + REGFILE_CHECK(6'd1 ,32'h0000_0000); + REGFILE_CHECK(6'd2 ,32'h0000_0000); + REGFILE_CHECK(6'd3 ,32'h0000_0000); + REGFILE_CHECK(6'd4 ,32'h0000_0000); + REGFILE_CHECK(6'd5 ,32'h0000_0000); + REGFILE_CHECK(6'd6 ,32'h0000_0000); + REGFILE_CHECK(6'd7 ,32'h0000_0000); + REGFILE_CHECK(6'd8 ,32'h0000_0000); + REGFILE_CHECK(6'd9 ,32'h0000_0000); + REGFILE_CHECK(6'd10,32'h0000_0000); + REGFILE_CHECK(6'd11,32'h0000_0000); + REGFILE_CHECK(6'd12,32'h0000_0000); + REGFILE_CHECK(6'd13,32'h0000_0000); + REGFILE_CHECK(6'd14,32'h0000_0000); + REGFILE_CHECK(6'd15,32'h0000_0000); + REGFILE_CHECK(6'd16,32'h0000_0000); + REGFILE_CHECK(6'd17,32'h0000_0000); + REGFILE_CHECK(6'd18,32'h0000_0000); + REGFILE_CHECK(6'd19,32'h0000_0000); + REGFILE_CHECK(6'd20,32'h0000_0000); + REGFILE_CHECK(6'd21,32'h0000_0000); + REGFILE_CHECK(6'd22,32'h0000_0000); + REGFILE_CHECK(6'd23,32'h0000_0000); + REGFILE_CHECK(6'd24,32'h0000_0000); + REGFILE_CHECK(6'd25,32'h0000_0000); + REGFILE_CHECK(6'd26,32'h0000_0000); + REGFILE_CHECK(6'd27,32'h0000_0000); + REGFILE_CHECK(6'd28,32'h0000_0000); + REGFILE_CHECK(6'd29,32'h0000_0000); + REGFILE_CHECK(6'd30,32'h0000_0000); + REGFILE_CHECK(6'd31,32'h0000_0000); + #10us; + TEST_PASS; +end + +task DRAM_DATA_CHECK; + input [9:0] addr ; + input [31:0] edata ; + + logic [31:0] ram_data; + + @(posedge ram_cs_dly1 ); + @(posedge ram_clk ); + //$monitor($time, " Simulation time: %t", $time); + if(ram_cs_dly1) begin + ram_data = `TB_DRAM.mem[addr]; + //$display("* RAM_DATA[%x]: %x | EXP_DATA: %x ",addr,ram_data, edata); + if(ram_data !== edata) begin + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,ram_data, edata); + #1us; + TEST_FAIL; + end + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, ram_data, edata); + end + else begin + $display("* DRAM CS is High => Error!!!"); + TEST_FAIL; + end +endtask + +task REGFILE_CHECK; + input [4:0] addr ; + input [31:0] edata ; + + logic [31:0] reg_data; + @(posedge reg_en ); + @(posedge reg_clk); + if(reg_en)begin + reg_data = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_dat; + if(reg_data !== edata) begin + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,reg_data, edata); + #1us; + //TEST_FAIL; + end + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, reg_data, edata); + end + else begin + $display("* REG WR EN is High => Error!!!"); + //TEST_FAIL; + end + +endtask + +initial begin + #100us; + $display("\n----------------------------------------\n"); + $display("\t Timeout Error !!!!\n"); + TEST_FAIL; +end + diff --git a/tb/qumcu/isa/case/Lui_0x55555_test/main.c b/tb/qumcu/isa/case/Lui_0x55555_test/main.c new file mode 100644 index 0000000..f92eb3f --- /dev/null +++ b/tb/qumcu/isa/case/Lui_0x55555_test/main.c @@ -0,0 +1,20 @@ +//#include + + +//int main(){ +// printf("\t=====================================\n"); +// printf("\t hello world !!! \n"); +// printf("\t=====================================\n"); +//} + +void main(void){ + +unsigned int a,b; + a=5; + b=3; + //c=a+b; + //d=c+b; +} + + + diff --git a/tb/qumcu/isa/case/Lui_0x55555_test/main.s b/tb/qumcu/isa/case/Lui_0x55555_test/main.s new file mode 100644 index 0000000..48e9d59 --- /dev/null +++ b/tb/qumcu/isa/case/Lui_0x55555_test/main.s @@ -0,0 +1,31 @@ +lui x1, 0x55555 +lui x2, 0x55555 +lui x3, 0x55555 +lui x4, 0x55555 +lui x5, 0x55555 +lui x6, 0x55555 +lui x7, 0x55555 +lui x8, 0x55555 +lui x9, 0x55555 +lui x10,0x55555 +lui x11,0x55555 +lui x12,0x55555 +lui x13,0x55555 +lui x14,0x55555 +lui x15,0x55555 +lui x16,0x55555 +lui x17,0x55555 +lui x18,0x55555 +lui x19,0x55555 +lui x20,0x55555 +lui x21,0x55555 +lui x22,0x55555 +lui x23,0x55555 +lui x24,0x55555 +lui x25,0x55555 +lui x26,0x55555 +lui x27,0x55555 +lui x28,0x55555 +lui x29,0x55555 +lui x30,0x55555 +lui x31,0x55555 \ No newline at end of file diff --git a/tb/qumcu/isa/case/Lui_0x55555_test/user.sv b/tb/qumcu/isa/case/Lui_0x55555_test/user.sv new file mode 100644 index 0000000..33ff25a --- /dev/null +++ b/tb/qumcu/isa/case/Lui_0x55555_test/user.sv @@ -0,0 +1,110 @@ + +wire ram_clk = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CLK; +wire ram_cs = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CEBA; +wire reg_clk = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.clk; +wire reg_en = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_wen; +reg ram_cs_dly1 ; +reg reg_en_dly1 ; +always @(posedge ram_clk) begin + ram_cs_dly1 <= ~ram_cs; + reg_en_dly1 <= reg_en; +end + + +initial begin + #1ns; + //@(posedge ram_cs_dly1 ); + #5ns; + //while(1)begin + #1ns; + //@(posedge reg_en_dly1 ); + REGFILE_CHECK(6'd1 ,32'h5555_5000); + REGFILE_CHECK(6'd2 ,32'h5555_5000); + REGFILE_CHECK(6'd3 ,32'h5555_5000); + REGFILE_CHECK(6'd4 ,32'h5555_5000); + REGFILE_CHECK(6'd5 ,32'h5555_5000); + REGFILE_CHECK(6'd6 ,32'h5555_5000); + REGFILE_CHECK(6'd7 ,32'h5555_5000); + REGFILE_CHECK(6'd8 ,32'h5555_5000); + REGFILE_CHECK(6'd9 ,32'h5555_5000); + REGFILE_CHECK(6'd10,32'h5555_5000); + REGFILE_CHECK(6'd11,32'h5555_5000); + REGFILE_CHECK(6'd12,32'h5555_5000); + REGFILE_CHECK(6'd13,32'h5555_5000); + REGFILE_CHECK(6'd14,32'h5555_5000); + REGFILE_CHECK(6'd15,32'h5555_5000); + REGFILE_CHECK(6'd16,32'h5555_5000); + REGFILE_CHECK(6'd17,32'h5555_5000); + REGFILE_CHECK(6'd18,32'h5555_5000); + REGFILE_CHECK(6'd19,32'h5555_5000); + REGFILE_CHECK(6'd20,32'h5555_5000); + REGFILE_CHECK(6'd21,32'h5555_5000); + REGFILE_CHECK(6'd22,32'h5555_5000); + REGFILE_CHECK(6'd23,32'h5555_5000); + REGFILE_CHECK(6'd24,32'h5555_5000); + REGFILE_CHECK(6'd25,32'h5555_5000); + REGFILE_CHECK(6'd26,32'h5555_5000); + REGFILE_CHECK(6'd27,32'h5555_5000); + REGFILE_CHECK(6'd28,32'h5555_5000); + REGFILE_CHECK(6'd29,32'h5555_5000); + REGFILE_CHECK(6'd30,32'h5555_5000); + REGFILE_CHECK(6'd31,32'h5555_5000); + #10us; + TEST_PASS; +end + +task DRAM_DATA_CHECK; + input [9:0] addr ; + input [31:0] edata ; + + logic [31:0] ram_data; + + @(posedge ram_cs_dly1 ); + @(posedge ram_clk ); + //$monitor($time, " Simulation time: %t", $time); + if(ram_cs_dly1) begin + ram_data = `TB_DRAM.mem[addr]; + //$display("* RAM_DATA[%x]: %x | EXP_DATA: %x ",addr,ram_data, edata); + if(ram_data !== edata) begin + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,ram_data, edata); + #1us; + TEST_FAIL; + end + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, ram_data, edata); + end + else begin + $display("* DRAM CS is High => Error!!!"); + TEST_FAIL; + end +endtask + +task REGFILE_CHECK; + input [4:0] addr ; + input [31:0] edata ; + + logic [31:0] reg_data; + @(posedge reg_en ); + @(posedge reg_clk); + if(reg_en)begin + reg_data = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_dat; + if(reg_data !== edata) begin + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,reg_data, edata); + #1us; + //TEST_FAIL; + end + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, reg_data, edata); + end + else begin + $display("* REG WR EN is High => Error!!!"); + //TEST_FAIL; + end + +endtask + +initial begin + #100us; + $display("\n----------------------------------------\n"); + $display("\t Timeout Error !!!!\n"); + TEST_FAIL; +end + diff --git a/tb/qumcu/isa/case/Lui_0xaaaaa_test/main.c b/tb/qumcu/isa/case/Lui_0xaaaaa_test/main.c new file mode 100644 index 0000000..f92eb3f --- /dev/null +++ b/tb/qumcu/isa/case/Lui_0xaaaaa_test/main.c @@ -0,0 +1,20 @@ +//#include + + +//int main(){ +// printf("\t=====================================\n"); +// printf("\t hello world !!! \n"); +// printf("\t=====================================\n"); +//} + +void main(void){ + +unsigned int a,b; + a=5; + b=3; + //c=a+b; + //d=c+b; +} + + + diff --git a/tb/qumcu/isa/case/Lui_0xaaaaa_test/main.s b/tb/qumcu/isa/case/Lui_0xaaaaa_test/main.s new file mode 100644 index 0000000..2001247 --- /dev/null +++ b/tb/qumcu/isa/case/Lui_0xaaaaa_test/main.s @@ -0,0 +1,31 @@ +lui x1, 0xaaaaa +lui x2, 0xaaaaa +lui x3, 0xaaaaa +lui x4, 0xaaaaa +lui x5, 0xaaaaa +lui x6, 0xaaaaa +lui x7, 0xaaaaa +lui x8, 0xaaaaa +lui x9, 0xaaaaa +lui x10,0xaaaaa +lui x11,0xaaaaa +lui x12,0xaaaaa +lui x13,0xaaaaa +lui x14,0xaaaaa +lui x15,0xaaaaa +lui x16,0xaaaaa +lui x17,0xaaaaa +lui x18,0xaaaaa +lui x19,0xaaaaa +lui x20,0xaaaaa +lui x21,0xaaaaa +lui x22,0xaaaaa +lui x23,0xaaaaa +lui x24,0xaaaaa +lui x25,0xaaaaa +lui x26,0xaaaaa +lui x27,0xaaaaa +lui x28,0xaaaaa +lui x29,0xaaaaa +lui x30,0xaaaaa +lui x31,0xaaaaa \ No newline at end of file diff --git a/tb/qumcu/isa/case/Lui_0xaaaaa_test/user.sv b/tb/qumcu/isa/case/Lui_0xaaaaa_test/user.sv new file mode 100644 index 0000000..50644cd --- /dev/null +++ b/tb/qumcu/isa/case/Lui_0xaaaaa_test/user.sv @@ -0,0 +1,110 @@ + +wire ram_clk = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CLK; +wire ram_cs = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CEBA; +wire reg_clk = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.clk; +wire reg_en = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_wen; +reg ram_cs_dly1 ; +reg reg_en_dly1 ; +always @(posedge ram_clk) begin + ram_cs_dly1 <= ~ram_cs; + reg_en_dly1 <= reg_en; +end + + +initial begin + #1ns; + //@(posedge ram_cs_dly1 ); + #5ns; + //while(1)begin + #1ns; + //@(posedge reg_en_dly1 ); + REGFILE_CHECK(6'd1 ,32'haaaa_a000); + REGFILE_CHECK(6'd2 ,32'haaaa_a000); + REGFILE_CHECK(6'd3 ,32'haaaa_a000); + REGFILE_CHECK(6'd4 ,32'haaaa_a000); + REGFILE_CHECK(6'd5 ,32'haaaa_a000); + REGFILE_CHECK(6'd6 ,32'haaaa_a000); + REGFILE_CHECK(6'd7 ,32'haaaa_a000); + REGFILE_CHECK(6'd8 ,32'haaaa_a000); + REGFILE_CHECK(6'd9 ,32'haaaa_a000); + REGFILE_CHECK(6'd10,32'haaaa_a000); + REGFILE_CHECK(6'd11,32'haaaa_a000); + REGFILE_CHECK(6'd12,32'haaaa_a000); + REGFILE_CHECK(6'd13,32'haaaa_a000); + REGFILE_CHECK(6'd14,32'haaaa_a000); + REGFILE_CHECK(6'd15,32'haaaa_a000); + REGFILE_CHECK(6'd16,32'haaaa_a000); + REGFILE_CHECK(6'd17,32'haaaa_a000); + REGFILE_CHECK(6'd18,32'haaaa_a000); + REGFILE_CHECK(6'd19,32'haaaa_a000); + REGFILE_CHECK(6'd20,32'haaaa_a000); + REGFILE_CHECK(6'd21,32'haaaa_a000); + REGFILE_CHECK(6'd22,32'haaaa_a000); + REGFILE_CHECK(6'd23,32'haaaa_a000); + REGFILE_CHECK(6'd24,32'haaaa_a000); + REGFILE_CHECK(6'd25,32'haaaa_a000); + REGFILE_CHECK(6'd26,32'haaaa_a000); + REGFILE_CHECK(6'd27,32'haaaa_a000); + REGFILE_CHECK(6'd28,32'haaaa_a000); + REGFILE_CHECK(6'd29,32'haaaa_a000); + REGFILE_CHECK(6'd30,32'haaaa_a000); + REGFILE_CHECK(6'd31,32'haaaa_a000); + #10us; + TEST_PASS; +end + +task DRAM_DATA_CHECK; + input [9:0] addr ; + input [31:0] edata ; + + logic [31:0] ram_data; + + @(posedge ram_cs_dly1 ); + @(posedge ram_clk ); + //$monitor($time, " Simulation time: %t", $time); + if(ram_cs_dly1) begin + ram_data = `TB_DRAM.mem[addr]; + //$display("* RAM_DATA[%x]: %x | EXP_DATA: %x ",addr,ram_data, edata); + if(ram_data !== edata) begin + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,ram_data, edata); + #1us; + TEST_FAIL; + end + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, ram_data, edata); + end + else begin + $display("* DRAM CS is High => Error!!!"); + TEST_FAIL; + end +endtask + +task REGFILE_CHECK; + input [4:0] addr ; + input [31:0] edata ; + + logic [31:0] reg_data; + @(posedge reg_en ); + @(posedge reg_clk); + if(reg_en)begin + reg_data = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_dat; + if(reg_data !== edata) begin + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,reg_data, edata); + #1us; + //TEST_FAIL; + end + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, reg_data, edata); + end + else begin + $display("* REG WR EN is High => Error!!!"); + //TEST_FAIL; + end + +endtask + +initial begin + #100us; + $display("\n----------------------------------------\n"); + $display("\t Timeout Error !!!!\n"); + TEST_FAIL; +end + diff --git a/tb/qumcu/isa/case/Lui_0xfffff_test/main.c b/tb/qumcu/isa/case/Lui_0xfffff_test/main.c new file mode 100644 index 0000000..f92eb3f --- /dev/null +++ b/tb/qumcu/isa/case/Lui_0xfffff_test/main.c @@ -0,0 +1,20 @@ +//#include + + +//int main(){ +// printf("\t=====================================\n"); +// printf("\t hello world !!! \n"); +// printf("\t=====================================\n"); +//} + +void main(void){ + +unsigned int a,b; + a=5; + b=3; + //c=a+b; + //d=c+b; +} + + + diff --git a/tb/qumcu/isa/case/Lui_0xfffff_test/main.s b/tb/qumcu/isa/case/Lui_0xfffff_test/main.s new file mode 100644 index 0000000..8e8481f --- /dev/null +++ b/tb/qumcu/isa/case/Lui_0xfffff_test/main.s @@ -0,0 +1,31 @@ +lui x1, 0xfffff +lui x2, 0xfffff +lui x3, 0xfffff +lui x4, 0xfffff +lui x5, 0xfffff +lui x6, 0xfffff +lui x7, 0xfffff +lui x8, 0xfffff +lui x9, 0xfffff +lui x10,0xfffff +lui x11,0xfffff +lui x12,0xfffff +lui x13,0xfffff +lui x14,0xfffff +lui x15,0xfffff +lui x16,0xfffff +lui x17,0xfffff +lui x18,0xfffff +lui x19,0xfffff +lui x20,0xfffff +lui x21,0xfffff +lui x22,0xfffff +lui x23,0xfffff +lui x24,0xfffff +lui x25,0xfffff +lui x26,0xfffff +lui x27,0xfffff +lui x28,0xfffff +lui x29,0xfffff +lui x30,0xfffff +lui x31,0xfffff \ No newline at end of file diff --git a/tb/qumcu/isa/case/Lui_0xfffff_test/user.sv b/tb/qumcu/isa/case/Lui_0xfffff_test/user.sv new file mode 100644 index 0000000..0c9ee2d --- /dev/null +++ b/tb/qumcu/isa/case/Lui_0xfffff_test/user.sv @@ -0,0 +1,110 @@ + +wire ram_clk = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CLK; +wire ram_cs = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CEBA; +wire reg_clk = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.clk; +wire reg_en = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_wen; +reg ram_cs_dly1 ; +reg reg_en_dly1 ; +always @(posedge ram_clk) begin + ram_cs_dly1 <= ~ram_cs; + reg_en_dly1 <= reg_en; +end + + +initial begin + #1ns; + //@(posedge ram_cs_dly1 ); + #5ns; + //while(1)begin + #1ns; + //@(posedge reg_en_dly1 ); + REGFILE_CHECK(6'd1 ,32'hffff_f000); + REGFILE_CHECK(6'd2 ,32'hffff_f000); + REGFILE_CHECK(6'd3 ,32'hffff_f000); + REGFILE_CHECK(6'd4 ,32'hffff_f000); + REGFILE_CHECK(6'd5 ,32'hffff_f000); + REGFILE_CHECK(6'd6 ,32'hffff_f000); + REGFILE_CHECK(6'd7 ,32'hffff_f000); + REGFILE_CHECK(6'd8 ,32'hffff_f000); + REGFILE_CHECK(6'd9 ,32'hffff_f000); + REGFILE_CHECK(6'd10,32'hffff_f000); + REGFILE_CHECK(6'd11,32'hffff_f000); + REGFILE_CHECK(6'd12,32'hffff_f000); + REGFILE_CHECK(6'd13,32'hffff_f000); + REGFILE_CHECK(6'd14,32'hffff_f000); + REGFILE_CHECK(6'd15,32'hffff_f000); + REGFILE_CHECK(6'd16,32'hffff_f000); + REGFILE_CHECK(6'd17,32'hffff_f000); + REGFILE_CHECK(6'd18,32'hffff_f000); + REGFILE_CHECK(6'd19,32'hffff_f000); + REGFILE_CHECK(6'd20,32'hffff_f000); + REGFILE_CHECK(6'd21,32'hffff_f000); + REGFILE_CHECK(6'd22,32'hffff_f000); + REGFILE_CHECK(6'd23,32'hffff_f000); + REGFILE_CHECK(6'd24,32'hffff_f000); + REGFILE_CHECK(6'd25,32'hffff_f000); + REGFILE_CHECK(6'd26,32'hffff_f000); + REGFILE_CHECK(6'd27,32'hffff_f000); + REGFILE_CHECK(6'd28,32'hffff_f000); + REGFILE_CHECK(6'd29,32'hffff_f000); + REGFILE_CHECK(6'd30,32'hffff_f000); + REGFILE_CHECK(6'd31,32'hffff_f000); + #10us; + TEST_PASS; +end + +task DRAM_DATA_CHECK; + input [9:0] addr ; + input [31:0] edata ; + + logic [31:0] ram_data; + + @(posedge ram_cs_dly1 ); + @(posedge ram_clk ); + //$monitor($time, " Simulation time: %t", $time); + if(ram_cs_dly1) begin + ram_data = `TB_DRAM.mem[addr]; + //$display("* RAM_DATA[%x]: %x | EXP_DATA: %x ",addr,ram_data, edata); + if(ram_data !== edata) begin + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,ram_data, edata); + #1us; + TEST_FAIL; + end + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, ram_data, edata); + end + else begin + $display("* DRAM CS is High => Error!!!"); + TEST_FAIL; + end +endtask + +task REGFILE_CHECK; + input [4:0] addr ; + input [31:0] edata ; + + logic [31:0] reg_data; + @(posedge reg_en ); + @(posedge reg_clk); + if(reg_en)begin + reg_data = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_dat; + if(reg_data !== edata) begin + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,reg_data, edata); + #1us; + //TEST_FAIL; + end + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, reg_data, edata); + end + else begin + $display("* REG WR EN is High => Error!!!"); + //TEST_FAIL; + end + +endtask + +initial begin + #100us; + $display("\n----------------------------------------\n"); + $display("\t Timeout Error !!!!\n"); + TEST_FAIL; +end + diff --git a/tb/qumcu/isa/case/Lw_test/main.c b/tb/qumcu/isa/case/Lw_test/main.c new file mode 100644 index 0000000..f92eb3f --- /dev/null +++ b/tb/qumcu/isa/case/Lw_test/main.c @@ -0,0 +1,20 @@ +//#include + + +//int main(){ +// printf("\t=====================================\n"); +// printf("\t hello world !!! \n"); +// printf("\t=====================================\n"); +//} + +void main(void){ + +unsigned int a,b; + a=5; + b=3; + //c=a+b; + //d=c+b; +} + + + diff --git a/tb/qumcu/isa/case/Lw_test/main.s b/tb/qumcu/isa/case/Lw_test/main.s new file mode 100644 index 0000000..8fe846e --- /dev/null +++ b/tb/qumcu/isa/case/Lw_test/main.s @@ -0,0 +1,21 @@ +lui x3,0x87654 +addi x3,x3,0x321 +lui x4,0xfedcb +addi x4,x4,0x765 +lui x1,0x100 +lui x5,0xfffff +lui x6,0xaaaaa +sw x3,0x0(x1) +sw x4,0x4(x1) +sw x5,0x8(x1) +sw x6,0xc(x1) +lwu x8,0x0(x1) +lwu x9,0x0(x1) +lwu x10,0x4(x1) +lwu x11,0x4(x1) +lwu x12,0x8(x1) +lwu x13,0x8(x1) +lwu x14,0xc(x1) +lwu x15,0xc(x1) +exit: + diff --git a/tb/qumcu/isa/case/Lw_test/user.sv b/tb/qumcu/isa/case/Lw_test/user.sv new file mode 100644 index 0000000..60062e1 --- /dev/null +++ b/tb/qumcu/isa/case/Lw_test/user.sv @@ -0,0 +1,99 @@ + +wire ram_clk = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CLK; +wire ram_cs = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CEBA; +wire reg_clk = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.clk; +wire reg_en = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_wen; +reg ram_cs_dly1 ; +reg reg_en_dly1 ; +always @(posedge ram_clk) begin + ram_cs_dly1 <= ~ram_cs; + reg_en_dly1 <= reg_en; +end + + +initial begin + #1ns; + //@(posedge ram_cs_dly1 ); + #5ns; + //while(1)begin + #1ns; + REGFILE_CHECK(6'd3,32'h8765_4000); + REGFILE_CHECK(6'd3,32'h8765_4321); + REGFILE_CHECK(6'd4,32'hfedc_b000); + REGFILE_CHECK(6'd4,32'hfedc_b765); + REGFILE_CHECK(6'd1,32'h0010_0000); + REGFILE_CHECK(6'd5,32'hffff_f000); + REGFILE_CHECK(6'd6,32'haaaa_a000); + DRAM_DATA_CHECK(10'd0,32'h8765_4321); + DRAM_DATA_CHECK(10'd1,32'hfedc_b765); + DRAM_DATA_CHECK(10'd2,32'hffff_f000); + DRAM_DATA_CHECK(10'd3,32'haaaa_a000); + //@(posedge reg_en_dly1 ); + REGFILE_CHECK(6'd8,32'h8765_4321); + REGFILE_CHECK(6'd9,32'h8765_4321); + REGFILE_CHECK(6'd10,32'hfedc_b765); + REGFILE_CHECK(6'd11,32'hfedc_b765); + REGFILE_CHECK(6'd12,32'hffff_f000); + REGFILE_CHECK(6'd13,32'hffff_f000); + REGFILE_CHECK(6'd14,32'haaaa_a000); + REGFILE_CHECK(6'd15,32'haaaa_a000); + + #10us; + TEST_PASS; +end + +task DRAM_DATA_CHECK; + input [9:0] addr ; + input [31:0] edata ; + + logic [31:0] ram_data; + + @(posedge ram_cs_dly1 ); + @(posedge ram_clk ); + //$monitor($time, " Simulation time: %t", $time); + if(ram_cs_dly1) begin + ram_data = `TB_DRAM.mem[addr]; + //$display("* RAM_DATA[%x]: %x | EXP_DATA: %x ",addr,ram_data, edata); + if(ram_data !== edata) begin + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,ram_data, edata); + #1us; + TEST_FAIL; + end + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, ram_data, edata); + end + else begin + $display("* DRAM CS is High => Error!!!"); + TEST_FAIL; + end +endtask + +task REGFILE_CHECK; + input [4:0] addr ; + input [31:0] edata ; + + logic [31:0] reg_data; + @(posedge reg_en ); + @(posedge reg_clk); + if(reg_en)begin + reg_data = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_dat; + if(reg_data !== edata) begin + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,reg_data, edata); + #1us; + //TEST_FAIL; + end + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, reg_data, edata); + end + else begin + $display("* REG WR EN is High => Error!!!"); + //TEST_FAIL; + end + +endtask + +initial begin + #100us; + $display("\n----------------------------------------\n"); + $display("\t Timeout Error !!!!\n"); + TEST_FAIL; +end + diff --git a/tb/qumcu/isa/case/Lwu_test/main.c b/tb/qumcu/isa/case/Lwu_test/main.c new file mode 100644 index 0000000..f92eb3f --- /dev/null +++ b/tb/qumcu/isa/case/Lwu_test/main.c @@ -0,0 +1,20 @@ +//#include + + +//int main(){ +// printf("\t=====================================\n"); +// printf("\t hello world !!! \n"); +// printf("\t=====================================\n"); +//} + +void main(void){ + +unsigned int a,b; + a=5; + b=3; + //c=a+b; + //d=c+b; +} + + + diff --git a/tb/qumcu/isa/case/Lwu_test/main.s b/tb/qumcu/isa/case/Lwu_test/main.s new file mode 100644 index 0000000..f29d977 --- /dev/null +++ b/tb/qumcu/isa/case/Lwu_test/main.s @@ -0,0 +1,21 @@ +lui x3,0x87654 +addi x3,x3,0x321 +lui x4,0xfedcb +addi x4,x4,0x765 +lui x1,0x100 +lui x5,0xfffff +lui x6,0xaaaaa +sw x3,0x0(x1) +sw x4,0x4(x1) +sw x5,0x8(x1) +sw x6,0xc(x1) +lw x8,0x0(x1) +lw x9,0x0(x1) +lw x10,0x4(x1) +lw x11,0x4(x1) +lw x12,0x8(x1) +lw x13,0x8(x1) +lw x14,0xc(x1) +lw x15,0xc(x1) +exit: + diff --git a/tb/qumcu/isa/case/Lwu_test/user.sv b/tb/qumcu/isa/case/Lwu_test/user.sv new file mode 100644 index 0000000..60062e1 --- /dev/null +++ b/tb/qumcu/isa/case/Lwu_test/user.sv @@ -0,0 +1,99 @@ + +wire ram_clk = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CLK; +wire ram_cs = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CEBA; +wire reg_clk = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.clk; +wire reg_en = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_wen; +reg ram_cs_dly1 ; +reg reg_en_dly1 ; +always @(posedge ram_clk) begin + ram_cs_dly1 <= ~ram_cs; + reg_en_dly1 <= reg_en; +end + + +initial begin + #1ns; + //@(posedge ram_cs_dly1 ); + #5ns; + //while(1)begin + #1ns; + REGFILE_CHECK(6'd3,32'h8765_4000); + REGFILE_CHECK(6'd3,32'h8765_4321); + REGFILE_CHECK(6'd4,32'hfedc_b000); + REGFILE_CHECK(6'd4,32'hfedc_b765); + REGFILE_CHECK(6'd1,32'h0010_0000); + REGFILE_CHECK(6'd5,32'hffff_f000); + REGFILE_CHECK(6'd6,32'haaaa_a000); + DRAM_DATA_CHECK(10'd0,32'h8765_4321); + DRAM_DATA_CHECK(10'd1,32'hfedc_b765); + DRAM_DATA_CHECK(10'd2,32'hffff_f000); + DRAM_DATA_CHECK(10'd3,32'haaaa_a000); + //@(posedge reg_en_dly1 ); + REGFILE_CHECK(6'd8,32'h8765_4321); + REGFILE_CHECK(6'd9,32'h8765_4321); + REGFILE_CHECK(6'd10,32'hfedc_b765); + REGFILE_CHECK(6'd11,32'hfedc_b765); + REGFILE_CHECK(6'd12,32'hffff_f000); + REGFILE_CHECK(6'd13,32'hffff_f000); + REGFILE_CHECK(6'd14,32'haaaa_a000); + REGFILE_CHECK(6'd15,32'haaaa_a000); + + #10us; + TEST_PASS; +end + +task DRAM_DATA_CHECK; + input [9:0] addr ; + input [31:0] edata ; + + logic [31:0] ram_data; + + @(posedge ram_cs_dly1 ); + @(posedge ram_clk ); + //$monitor($time, " Simulation time: %t", $time); + if(ram_cs_dly1) begin + ram_data = `TB_DRAM.mem[addr]; + //$display("* RAM_DATA[%x]: %x | EXP_DATA: %x ",addr,ram_data, edata); + if(ram_data !== edata) begin + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,ram_data, edata); + #1us; + TEST_FAIL; + end + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, ram_data, edata); + end + else begin + $display("* DRAM CS is High => Error!!!"); + TEST_FAIL; + end +endtask + +task REGFILE_CHECK; + input [4:0] addr ; + input [31:0] edata ; + + logic [31:0] reg_data; + @(posedge reg_en ); + @(posedge reg_clk); + if(reg_en)begin + reg_data = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_dat; + if(reg_data !== edata) begin + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,reg_data, edata); + #1us; + //TEST_FAIL; + end + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, reg_data, edata); + end + else begin + $display("* REG WR EN is High => Error!!!"); + //TEST_FAIL; + end + +endtask + +initial begin + #100us; + $display("\n----------------------------------------\n"); + $display("\t Timeout Error !!!!\n"); + TEST_FAIL; +end + diff --git a/tb/qumcu/isa/case/Or0x0x0_test/main.c b/tb/qumcu/isa/case/Or0x0x0_test/main.c new file mode 100644 index 0000000..f92eb3f --- /dev/null +++ b/tb/qumcu/isa/case/Or0x0x0_test/main.c @@ -0,0 +1,20 @@ +//#include + + +//int main(){ +// printf("\t=====================================\n"); +// printf("\t hello world !!! \n"); +// printf("\t=====================================\n"); +//} + +void main(void){ + +unsigned int a,b; + a=5; + b=3; + //c=a+b; + //d=c+b; +} + + + diff --git a/tb/qumcu/isa/case/Or0x0x0_test/main.s b/tb/qumcu/isa/case/Or0x0x0_test/main.s new file mode 100644 index 0000000..8240d3e --- /dev/null +++ b/tb/qumcu/isa/case/Or0x0x0_test/main.s @@ -0,0 +1,18 @@ +lui x3,0x87654 +addi x3,x3,0x321 +lui x4,0xfedcb +addi x4,x4,0x765 +or x5,x0,x0 +or x6,x0,x0 +or x7,x0,x0 +or x8,x0,x0 +or x9,x0,x0 +or x10,x0,x0 +or x11,x0,x0 +or x20,x0,x0 +or x22,x0,x0 +or x25,x0,x0 +or x29,x0,x0 +or x31,x0,x0 +exit: + diff --git a/tb/qumcu/isa/case/Or0x0x0_test/user.sv b/tb/qumcu/isa/case/Or0x0x0_test/user.sv new file mode 100644 index 0000000..356e529 --- /dev/null +++ b/tb/qumcu/isa/case/Or0x0x0_test/user.sv @@ -0,0 +1,96 @@ + +wire ram_clk = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CLK; +wire ram_cs = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CEBA; +wire reg_clk = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.clk; +wire reg_en = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_wen; +reg ram_cs_dly1 ; +reg reg_en_dly1 ; +always @(posedge ram_clk) begin + ram_cs_dly1 <= ~ram_cs; + reg_en_dly1 <= reg_en; +end + + +initial begin + #1ns; + //@(posedge ram_cs_dly1 ); + #5ns; + //while(1)begin + #1ns; + REGFILE_CHECK(6'd3,32'h8765_4000); + REGFILE_CHECK(6'd3,32'h8765_4321); + REGFILE_CHECK(6'd4,32'hfedc_b000); + REGFILE_CHECK(6'd4,32'hfedc_b765); + //@(posedge reg_en_dly1 ); + REGFILE_CHECK(6'd5 ,32'h0000_0000); + REGFILE_CHECK(6'd6 ,32'h0000_0000); + REGFILE_CHECK(6'd7 ,32'h0000_0000); + REGFILE_CHECK(6'd8 ,32'h0000_0000); + REGFILE_CHECK(6'd9 ,32'h0000_0000); + REGFILE_CHECK(6'd10,32'h0000_0000); + REGFILE_CHECK(6'd11,32'h0000_0000); + REGFILE_CHECK(6'd20,32'h0000_0000); + REGFILE_CHECK(6'd22,32'h0000_0000); + REGFILE_CHECK(6'd25,32'h0000_0000); + REGFILE_CHECK(6'd29,32'h0000_0000); + REGFILE_CHECK(6'd31,32'h0000_0000); + + #10us; + TEST_PASS; +end + +task DRAM_DATA_CHECK; + input [9:0] addr ; + input [31:0] edata ; + + logic [31:0] ram_data; + + @(posedge ram_cs_dly1 ); + @(posedge ram_clk ); + //$monitor($time, " Simulation time: %t", $time); + if(ram_cs_dly1) begin + ram_data = `TB_DRAM.mem[addr]; + //$display("* RAM_DATA[%x]: %x | EXP_DATA: %x ",addr,ram_data, edata); + if(ram_data !== edata) begin + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,ram_data, edata); + #1us; + TEST_FAIL; + end + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, ram_data, edata); + end + else begin + $display("* DRAM CS is High => Error!!!"); + TEST_FAIL; + end +endtask + +task REGFILE_CHECK; + input [4:0] addr ; + input [31:0] edata ; + + logic [31:0] reg_data; + @(posedge reg_en ); + @(posedge reg_clk); + if(reg_en)begin + reg_data = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_dat; + if(reg_data !== edata) begin + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,reg_data, edata); + #1us; + //TEST_FAIL; + end + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, reg_data, edata); + end + else begin + $display("* REG WR EN is High => Error!!!"); + //TEST_FAIL; + end + +endtask + +initial begin + #100us; + $display("\n----------------------------------------\n"); + $display("\t Timeout Error !!!!\n"); + TEST_FAIL; +end + diff --git a/tb/qumcu/isa/case/Orall0_all1_test/main.c b/tb/qumcu/isa/case/Orall0_all1_test/main.c new file mode 100644 index 0000000..f92eb3f --- /dev/null +++ b/tb/qumcu/isa/case/Orall0_all1_test/main.c @@ -0,0 +1,20 @@ +//#include + + +//int main(){ +// printf("\t=====================================\n"); +// printf("\t hello world !!! \n"); +// printf("\t=====================================\n"); +//} + +void main(void){ + +unsigned int a,b; + a=5; + b=3; + //c=a+b; + //d=c+b; +} + + + diff --git a/tb/qumcu/isa/case/Orall0_all1_test/main.s b/tb/qumcu/isa/case/Orall0_all1_test/main.s new file mode 100644 index 0000000..d8107a5 --- /dev/null +++ b/tb/qumcu/isa/case/Orall0_all1_test/main.s @@ -0,0 +1,20 @@ +lui x3,0x87654 +addi x3,x3,0x321 +lui x4,0xfffff +addi x4,x4,0x7ff +addi x4,x4,0x7ff +addi x4,x4,0x1 +or x5 ,x0,x4 +or x6 ,x0,x4 +or x7 ,x0,x4 +or x8 ,x0,x4 +or x9 ,x0,x4 +or x10,x0,x4 +or x11,x0,x4 +or x20,x0,x4 +or x22,x0,x4 +or x25,x0,x4 +or x29,x0,x4 +or x31,x0,x4 +exit: + diff --git a/tb/qumcu/isa/case/Orall0_all1_test/user.sv b/tb/qumcu/isa/case/Orall0_all1_test/user.sv new file mode 100644 index 0000000..7c09d82 --- /dev/null +++ b/tb/qumcu/isa/case/Orall0_all1_test/user.sv @@ -0,0 +1,98 @@ + +wire ram_clk = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CLK; +wire ram_cs = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CEBA; +wire reg_clk = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.clk; +wire reg_en = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_wen; +reg ram_cs_dly1 ; +reg reg_en_dly1 ; +always @(posedge ram_clk) begin + ram_cs_dly1 <= ~ram_cs; + reg_en_dly1 <= reg_en; +end + + +initial begin + #1ns; + //@(posedge ram_cs_dly1 ); + #5ns; + //while(1)begin + #1ns; + REGFILE_CHECK(6'd3,32'h8765_4000); + REGFILE_CHECK(6'd3,32'h8765_4321); + REGFILE_CHECK(6'd4,32'hffff_f000); + REGFILE_CHECK(6'd4,32'hffff_f7ff); + REGFILE_CHECK(6'd4,32'hffff_fffe); + REGFILE_CHECK(6'd4,32'hffff_ffff); + //@(posedge reg_en_dly1 ); + REGFILE_CHECK(6'd5 ,32'hffff_ffff); + REGFILE_CHECK(6'd6 ,32'hffff_ffff); + REGFILE_CHECK(6'd7 ,32'hffff_ffff); + REGFILE_CHECK(6'd8 ,32'hffff_ffff); + REGFILE_CHECK(6'd9 ,32'hffff_ffff); + REGFILE_CHECK(6'd10,32'hffff_ffff); + REGFILE_CHECK(6'd11,32'hffff_ffff); + REGFILE_CHECK(6'd20,32'hffff_ffff); + REGFILE_CHECK(6'd22,32'hffff_ffff); + REGFILE_CHECK(6'd25,32'hffff_ffff); + REGFILE_CHECK(6'd29,32'hffff_ffff); + REGFILE_CHECK(6'd31,32'hffff_ffff); + + #10us; + TEST_PASS; +end + +task DRAM_DATA_CHECK; + input [9:0] addr ; + input [31:0] edata ; + + logic [31:0] ram_data; + + @(posedge ram_cs_dly1 ); + @(posedge ram_clk ); + //$monitor($time, " Simulation time: %t", $time); + if(ram_cs_dly1) begin + ram_data = `TB_DRAM.mem[addr]; + //$display("* RAM_DATA[%x]: %x | EXP_DATA: %x ",addr,ram_data, edata); + if(ram_data !== edata) begin + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,ram_data, edata); + #1us; + TEST_FAIL; + end + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, ram_data, edata); + end + else begin + $display("* DRAM CS is High => Error!!!"); + TEST_FAIL; + end +endtask + +task REGFILE_CHECK; + input [4:0] addr ; + input [31:0] edata ; + + logic [31:0] reg_data; + @(posedge reg_en ); + @(posedge reg_clk); + if(reg_en)begin + reg_data = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_dat; + if(reg_data !== edata) begin + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,reg_data, edata); + #1us; + //TEST_FAIL; + end + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, reg_data, edata); + end + else begin + $display("* REG WR EN is High => Error!!!"); + //TEST_FAIL; + end + +endtask + +initial begin + #100us; + $display("\n----------------------------------------\n"); + $display("\t Timeout Error !!!!\n"); + TEST_FAIL; +end + diff --git a/tb/qumcu/isa/case/Oralla_all5_test/main.c b/tb/qumcu/isa/case/Oralla_all5_test/main.c new file mode 100644 index 0000000..f92eb3f --- /dev/null +++ b/tb/qumcu/isa/case/Oralla_all5_test/main.c @@ -0,0 +1,20 @@ +//#include + + +//int main(){ +// printf("\t=====================================\n"); +// printf("\t hello world !!! \n"); +// printf("\t=====================================\n"); +//} + +void main(void){ + +unsigned int a,b; + a=5; + b=3; + //c=a+b; + //d=c+b; +} + + + diff --git a/tb/qumcu/isa/case/Oralla_all5_test/main.s b/tb/qumcu/isa/case/Oralla_all5_test/main.s new file mode 100644 index 0000000..0f76ba8 --- /dev/null +++ b/tb/qumcu/isa/case/Oralla_all5_test/main.s @@ -0,0 +1,20 @@ +lui x3,0x55555 +addi x3,x3,0x555 +lui x4,0xaaaaa +addi x4,x4,0x555 +addi x4,x4,0x554 +addi x4,x4,0x1 +or x5 ,x3,x4 +or x6 ,x3,x4 +or x7 ,x3,x4 +or x8 ,x3,x4 +or x9 ,x3,x4 +or x10,x3,x4 +or x11,x3,x4 +or x20,x3,x4 +or x22,x3,x4 +or x25,x3,x4 +or x29,x3,x4 +or x31,x3,x4 +exit: + diff --git a/tb/qumcu/isa/case/Oralla_all5_test/user.sv b/tb/qumcu/isa/case/Oralla_all5_test/user.sv new file mode 100644 index 0000000..753ceea --- /dev/null +++ b/tb/qumcu/isa/case/Oralla_all5_test/user.sv @@ -0,0 +1,98 @@ + +wire ram_clk = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CLK; +wire ram_cs = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CEBA; +wire reg_clk = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.clk; +wire reg_en = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_wen; +reg ram_cs_dly1 ; +reg reg_en_dly1 ; +always @(posedge ram_clk) begin + ram_cs_dly1 <= ~ram_cs; + reg_en_dly1 <= reg_en; +end + + +initial begin + #1ns; + //@(posedge ram_cs_dly1 ); + #5ns; + //while(1)begin + #1ns; + REGFILE_CHECK(6'd3,32'h5555_5000); + REGFILE_CHECK(6'd3,32'h5555_5555); + REGFILE_CHECK(6'd4,32'haaaa_a000); + REGFILE_CHECK(6'd4,32'haaaa_a555); + REGFILE_CHECK(6'd4,32'haaaa_aaa9); + REGFILE_CHECK(6'd4,32'haaaa_aaaa); + //@(posedge reg_en_dly1 ); + REGFILE_CHECK(6'd5 ,32'hffff_ffff); + REGFILE_CHECK(6'd6 ,32'hffff_ffff); + REGFILE_CHECK(6'd7 ,32'hffff_ffff); + REGFILE_CHECK(6'd8 ,32'hffff_ffff); + REGFILE_CHECK(6'd9 ,32'hffff_ffff); + REGFILE_CHECK(6'd10,32'hffff_ffff); + REGFILE_CHECK(6'd11,32'hffff_ffff); + REGFILE_CHECK(6'd20,32'hffff_ffff); + REGFILE_CHECK(6'd22,32'hffff_ffff); + REGFILE_CHECK(6'd25,32'hffff_ffff); + REGFILE_CHECK(6'd29,32'hffff_ffff); + REGFILE_CHECK(6'd31,32'hffff_ffff); + + #10us; + TEST_PASS; +end + +task DRAM_DATA_CHECK; + input [9:0] addr ; + input [31:0] edata ; + + logic [31:0] ram_data; + + @(posedge ram_cs_dly1 ); + @(posedge ram_clk ); + //$monitor($time, " Simulation time: %t", $time); + if(ram_cs_dly1) begin + ram_data = `TB_DRAM.mem[addr]; + //$display("* RAM_DATA[%x]: %x | EXP_DATA: %x ",addr,ram_data, edata); + if(ram_data !== edata) begin + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,ram_data, edata); + #1us; + TEST_FAIL; + end + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, ram_data, edata); + end + else begin + $display("* DRAM CS is High => Error!!!"); + TEST_FAIL; + end +endtask + +task REGFILE_CHECK; + input [4:0] addr ; + input [31:0] edata ; + + logic [31:0] reg_data; + @(posedge reg_en ); + @(posedge reg_clk); + if(reg_en)begin + reg_data = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_dat; + if(reg_data !== edata) begin + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,reg_data, edata); + #1us; + //TEST_FAIL; + end + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, reg_data, edata); + end + else begin + $display("* REG WR EN is High => Error!!!"); + //TEST_FAIL; + end + +endtask + +initial begin + #100us; + $display("\n----------------------------------------\n"); + $display("\t Timeout Error !!!!\n"); + TEST_FAIL; +end + diff --git a/tb/qumcu/isa/case/Ori0x0x0_test/main.c b/tb/qumcu/isa/case/Ori0x0x0_test/main.c new file mode 100644 index 0000000..f92eb3f --- /dev/null +++ b/tb/qumcu/isa/case/Ori0x0x0_test/main.c @@ -0,0 +1,20 @@ +//#include + + +//int main(){ +// printf("\t=====================================\n"); +// printf("\t hello world !!! \n"); +// printf("\t=====================================\n"); +//} + +void main(void){ + +unsigned int a,b; + a=5; + b=3; + //c=a+b; + //d=c+b; +} + + + diff --git a/tb/qumcu/isa/case/Ori0x0x0_test/main.s b/tb/qumcu/isa/case/Ori0x0x0_test/main.s new file mode 100644 index 0000000..1f5b488 --- /dev/null +++ b/tb/qumcu/isa/case/Ori0x0x0_test/main.s @@ -0,0 +1,18 @@ +lui x3,0x87654 +addi x3,x3,0x321 +lui x4,0xfedcb +addi x4,x4,0x765 +ori x5 ,x0,0x0 +ori x6 ,x0,0x0 +ori x7 ,x0,0x0 +ori x8 ,x0,0x0 +ori x9 ,x0,0x0 +ori x10,x0,0x0 +ori x11,x0,0x0 +ori x20,x0,0x0 +ori x22,x0,0x0 +ori x25,x0,0x0 +ori x29,x0,0x0 +ori x31,x0,0x0 +exit: + diff --git a/tb/qumcu/isa/case/Ori0x0x0_test/user.sv b/tb/qumcu/isa/case/Ori0x0x0_test/user.sv new file mode 100644 index 0000000..356e529 --- /dev/null +++ b/tb/qumcu/isa/case/Ori0x0x0_test/user.sv @@ -0,0 +1,96 @@ + +wire ram_clk = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CLK; +wire ram_cs = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CEBA; +wire reg_clk = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.clk; +wire reg_en = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_wen; +reg ram_cs_dly1 ; +reg reg_en_dly1 ; +always @(posedge ram_clk) begin + ram_cs_dly1 <= ~ram_cs; + reg_en_dly1 <= reg_en; +end + + +initial begin + #1ns; + //@(posedge ram_cs_dly1 ); + #5ns; + //while(1)begin + #1ns; + REGFILE_CHECK(6'd3,32'h8765_4000); + REGFILE_CHECK(6'd3,32'h8765_4321); + REGFILE_CHECK(6'd4,32'hfedc_b000); + REGFILE_CHECK(6'd4,32'hfedc_b765); + //@(posedge reg_en_dly1 ); + REGFILE_CHECK(6'd5 ,32'h0000_0000); + REGFILE_CHECK(6'd6 ,32'h0000_0000); + REGFILE_CHECK(6'd7 ,32'h0000_0000); + REGFILE_CHECK(6'd8 ,32'h0000_0000); + REGFILE_CHECK(6'd9 ,32'h0000_0000); + REGFILE_CHECK(6'd10,32'h0000_0000); + REGFILE_CHECK(6'd11,32'h0000_0000); + REGFILE_CHECK(6'd20,32'h0000_0000); + REGFILE_CHECK(6'd22,32'h0000_0000); + REGFILE_CHECK(6'd25,32'h0000_0000); + REGFILE_CHECK(6'd29,32'h0000_0000); + REGFILE_CHECK(6'd31,32'h0000_0000); + + #10us; + TEST_PASS; +end + +task DRAM_DATA_CHECK; + input [9:0] addr ; + input [31:0] edata ; + + logic [31:0] ram_data; + + @(posedge ram_cs_dly1 ); + @(posedge ram_clk ); + //$monitor($time, " Simulation time: %t", $time); + if(ram_cs_dly1) begin + ram_data = `TB_DRAM.mem[addr]; + //$display("* RAM_DATA[%x]: %x | EXP_DATA: %x ",addr,ram_data, edata); + if(ram_data !== edata) begin + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,ram_data, edata); + #1us; + TEST_FAIL; + end + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, ram_data, edata); + end + else begin + $display("* DRAM CS is High => Error!!!"); + TEST_FAIL; + end +endtask + +task REGFILE_CHECK; + input [4:0] addr ; + input [31:0] edata ; + + logic [31:0] reg_data; + @(posedge reg_en ); + @(posedge reg_clk); + if(reg_en)begin + reg_data = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_dat; + if(reg_data !== edata) begin + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,reg_data, edata); + #1us; + //TEST_FAIL; + end + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, reg_data, edata); + end + else begin + $display("* REG WR EN is High => Error!!!"); + //TEST_FAIL; + end + +endtask + +initial begin + #100us; + $display("\n----------------------------------------\n"); + $display("\t Timeout Error !!!!\n"); + TEST_FAIL; +end + diff --git a/tb/qumcu/isa/case/Oriall0_all1_test/main.c b/tb/qumcu/isa/case/Oriall0_all1_test/main.c new file mode 100644 index 0000000..f92eb3f --- /dev/null +++ b/tb/qumcu/isa/case/Oriall0_all1_test/main.c @@ -0,0 +1,20 @@ +//#include + + +//int main(){ +// printf("\t=====================================\n"); +// printf("\t hello world !!! \n"); +// printf("\t=====================================\n"); +//} + +void main(void){ + +unsigned int a,b; + a=5; + b=3; + //c=a+b; + //d=c+b; +} + + + diff --git a/tb/qumcu/isa/case/Oriall0_all1_test/main.s b/tb/qumcu/isa/case/Oriall0_all1_test/main.s new file mode 100644 index 0000000..da6a909 --- /dev/null +++ b/tb/qumcu/isa/case/Oriall0_all1_test/main.s @@ -0,0 +1,20 @@ +lui x3,0x87654 +addi x3,x3,0x321 +lui x4,0xfffff +addi x4,x4,0x7ff +addi x4,x4,0x7ff +addi x4,x4,0x1 +ori x5 ,x0,0x7ff +ori x6 ,x0,0x7ff +ori x7 ,x0,0x7ff +ori x8 ,x0,0x7ff +ori x9 ,x0,0x7ff +ori x10,x0,0x7ff +ori x11,x0,0x7ff +ori x20,x0,0x7ff +ori x22,x0,0x7ff +ori x25,x0,0x7ff +ori x29,x0,0x7ff +ori x31,x0,0x7ff +exit: + diff --git a/tb/qumcu/isa/case/Oriall0_all1_test/user.sv b/tb/qumcu/isa/case/Oriall0_all1_test/user.sv new file mode 100644 index 0000000..ea449e1 --- /dev/null +++ b/tb/qumcu/isa/case/Oriall0_all1_test/user.sv @@ -0,0 +1,98 @@ + +wire ram_clk = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CLK; +wire ram_cs = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CEBA; +wire reg_clk = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.clk; +wire reg_en = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_wen; +reg ram_cs_dly1 ; +reg reg_en_dly1 ; +always @(posedge ram_clk) begin + ram_cs_dly1 <= ~ram_cs; + reg_en_dly1 <= reg_en; +end + + +initial begin + #1ns; + //@(posedge ram_cs_dly1 ); + #5ns; + //while(1)begin + #1ns; + REGFILE_CHECK(6'd3,32'h8765_4000); + REGFILE_CHECK(6'd3,32'h8765_4321); + REGFILE_CHECK(6'd4,32'hffff_f000); + REGFILE_CHECK(6'd4,32'hffff_f7ff); + REGFILE_CHECK(6'd4,32'hffff_fffe); + REGFILE_CHECK(6'd4,32'hffff_ffff); + //@(posedge reg_en_dly1 ); + REGFILE_CHECK(6'd5 ,32'h0000_07ff); + REGFILE_CHECK(6'd6 ,32'h0000_07ff); + REGFILE_CHECK(6'd7 ,32'h0000_07ff); + REGFILE_CHECK(6'd8 ,32'h0000_07ff); + REGFILE_CHECK(6'd9 ,32'h0000_07ff); + REGFILE_CHECK(6'd10,32'h0000_07ff); + REGFILE_CHECK(6'd11,32'h0000_07ff); + REGFILE_CHECK(6'd20,32'h0000_07ff); + REGFILE_CHECK(6'd22,32'h0000_07ff); + REGFILE_CHECK(6'd25,32'h0000_07ff); + REGFILE_CHECK(6'd29,32'h0000_07ff); + REGFILE_CHECK(6'd31,32'h0000_07ff); + + #10us; + TEST_PASS; +end + +task DRAM_DATA_CHECK; + input [9:0] addr ; + input [31:0] edata ; + + logic [31:0] ram_data; + + @(posedge ram_cs_dly1 ); + @(posedge ram_clk ); + //$monitor($time, " Simulation time: %t", $time); + if(ram_cs_dly1) begin + ram_data = `TB_DRAM.mem[addr]; + //$display("* RAM_DATA[%x]: %x | EXP_DATA: %x ",addr,ram_data, edata); + if(ram_data !== edata) begin + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,ram_data, edata); + #1us; + TEST_FAIL; + end + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, ram_data, edata); + end + else begin + $display("* DRAM CS is High => Error!!!"); + TEST_FAIL; + end +endtask + +task REGFILE_CHECK; + input [4:0] addr ; + input [31:0] edata ; + + logic [31:0] reg_data; + @(posedge reg_en ); + @(posedge reg_clk); + if(reg_en)begin + reg_data = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_dat; + if(reg_data !== edata) begin + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,reg_data, edata); + #1us; + //TEST_FAIL; + end + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, reg_data, edata); + end + else begin + $display("* REG WR EN is High => Error!!!"); + //TEST_FAIL; + end + +endtask + +initial begin + #100us; + $display("\n----------------------------------------\n"); + $display("\t Timeout Error !!!!\n"); + TEST_FAIL; +end + diff --git a/tb/qumcu/isa/case/Orialla_all5_test/main.c b/tb/qumcu/isa/case/Orialla_all5_test/main.c new file mode 100644 index 0000000..f92eb3f --- /dev/null +++ b/tb/qumcu/isa/case/Orialla_all5_test/main.c @@ -0,0 +1,20 @@ +//#include + + +//int main(){ +// printf("\t=====================================\n"); +// printf("\t hello world !!! \n"); +// printf("\t=====================================\n"); +//} + +void main(void){ + +unsigned int a,b; + a=5; + b=3; + //c=a+b; + //d=c+b; +} + + + diff --git a/tb/qumcu/isa/case/Orialla_all5_test/main.s b/tb/qumcu/isa/case/Orialla_all5_test/main.s new file mode 100644 index 0000000..65b40d1 --- /dev/null +++ b/tb/qumcu/isa/case/Orialla_all5_test/main.s @@ -0,0 +1,20 @@ +lui x3,0x55555 +addi x3,x3,0x555 +lui x4,0xaaaaa +addi x4,x4,0x555 +addi x4,x4,0x554 +addi x4,x4,0x1 +ori x5 ,x4,0x555 +ori x6 ,x4,0x555 +ori x7 ,x4,0x555 +ori x8 ,x4,0x555 +ori x9 ,x4,0x555 +ori x10,x4,0x555 +ori x11,x4,0x555 +ori x20,x4,0x555 +ori x22,x4,0x555 +ori x25,x4,0x555 +ori x29,x4,0x555 +ori x31,x4,0x555 +exit: + diff --git a/tb/qumcu/isa/case/Orialla_all5_test/user.sv b/tb/qumcu/isa/case/Orialla_all5_test/user.sv new file mode 100644 index 0000000..323a08a --- /dev/null +++ b/tb/qumcu/isa/case/Orialla_all5_test/user.sv @@ -0,0 +1,98 @@ + +wire ram_clk = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CLK; +wire ram_cs = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CEBA; +wire reg_clk = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.clk; +wire reg_en = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_wen; +reg ram_cs_dly1 ; +reg reg_en_dly1 ; +always @(posedge ram_clk) begin + ram_cs_dly1 <= ~ram_cs; + reg_en_dly1 <= reg_en; +end + + +initial begin + #1ns; + //@(posedge ram_cs_dly1 ); + #5ns; + //while(1)begin + #1ns; + REGFILE_CHECK(6'd3,32'h5555_5000); + REGFILE_CHECK(6'd3,32'h5555_5555); + REGFILE_CHECK(6'd4,32'haaaa_a000); + REGFILE_CHECK(6'd4,32'haaaa_a555); + REGFILE_CHECK(6'd4,32'haaaa_aaa9); + REGFILE_CHECK(6'd4,32'haaaa_aaaa); + //@(posedge reg_en_dly1 ); + REGFILE_CHECK(6'd5 ,32'haaaa_afff); + REGFILE_CHECK(6'd6 ,32'haaaa_afff); + REGFILE_CHECK(6'd7 ,32'haaaa_afff); + REGFILE_CHECK(6'd8 ,32'haaaa_afff); + REGFILE_CHECK(6'd9 ,32'haaaa_afff); + REGFILE_CHECK(6'd10,32'haaaa_afff); + REGFILE_CHECK(6'd11,32'haaaa_afff); + REGFILE_CHECK(6'd20,32'haaaa_afff); + REGFILE_CHECK(6'd22,32'haaaa_afff); + REGFILE_CHECK(6'd25,32'haaaa_afff); + REGFILE_CHECK(6'd29,32'haaaa_afff); + REGFILE_CHECK(6'd31,32'haaaa_afff); + + #10us; + TEST_PASS; +end + +task DRAM_DATA_CHECK; + input [9:0] addr ; + input [31:0] edata ; + + logic [31:0] ram_data; + + @(posedge ram_cs_dly1 ); + @(posedge ram_clk ); + //$monitor($time, " Simulation time: %t", $time); + if(ram_cs_dly1) begin + ram_data = `TB_DRAM.mem[addr]; + //$display("* RAM_DATA[%x]: %x | EXP_DATA: %x ",addr,ram_data, edata); + if(ram_data !== edata) begin + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,ram_data, edata); + #1us; + TEST_FAIL; + end + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, ram_data, edata); + end + else begin + $display("* DRAM CS is High => Error!!!"); + TEST_FAIL; + end +endtask + +task REGFILE_CHECK; + input [4:0] addr ; + input [31:0] edata ; + + logic [31:0] reg_data; + @(posedge reg_en ); + @(posedge reg_clk); + if(reg_en)begin + reg_data = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_dat; + if(reg_data !== edata) begin + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,reg_data, edata); + #1us; + //TEST_FAIL; + end + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, reg_data, edata); + end + else begin + $display("* REG WR EN is High => Error!!!"); + //TEST_FAIL; + end + +endtask + +initial begin + #100us; + $display("\n----------------------------------------\n"); + $display("\t Timeout Error !!!!\n"); + TEST_FAIL; +end + diff --git a/tb/qumcu/isa/case/Sb_test/main.c b/tb/qumcu/isa/case/Sb_test/main.c new file mode 100644 index 0000000..f92eb3f --- /dev/null +++ b/tb/qumcu/isa/case/Sb_test/main.c @@ -0,0 +1,20 @@ +//#include + + +//int main(){ +// printf("\t=====================================\n"); +// printf("\t hello world !!! \n"); +// printf("\t=====================================\n"); +//} + +void main(void){ + +unsigned int a,b; + a=5; + b=3; + //c=a+b; + //d=c+b; +} + + + diff --git a/tb/qumcu/isa/case/Sb_test/main.s b/tb/qumcu/isa/case/Sb_test/main.s new file mode 100644 index 0000000..c2c4573 --- /dev/null +++ b/tb/qumcu/isa/case/Sb_test/main.s @@ -0,0 +1,19 @@ +lui x3,0x87654 +addi x3,x3,0x321 +lui x4,0xfedcb +addi x4,x4,0x7f5 +lui x1,0x100 +sw x3 ,0x0(x1) +sw x4 ,0x4(x1) +sw x0 ,0x7d0(x1) +sw x0 ,0x7d4(x1) +sb x3,0x7d0(x1) +sb x3,0x7d1(x1) +sb x3,0x7d2(x1) +sb x3,0x7d3(x1) +sb x4,0x7d4(x1) +sb x4,0x7d5(x1) +sb x4,0x7d6(x1) +sb x4,0x7d7(x1) +exit: + diff --git a/tb/qumcu/isa/case/Sb_test/user.sv b/tb/qumcu/isa/case/Sb_test/user.sv new file mode 100644 index 0000000..e70f405 --- /dev/null +++ b/tb/qumcu/isa/case/Sb_test/user.sv @@ -0,0 +1,97 @@ + +wire ram_clk = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CLK; +wire ram_cs = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CEBA; +wire reg_clk = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.clk; +wire reg_en = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_wen; +reg ram_cs_dly1 ; +reg reg_en_dly1 ; +always @(posedge ram_clk) begin + ram_cs_dly1 <= ~ram_cs; + reg_en_dly1 <= reg_en; +end + + +initial begin + #1ns; + //@(posedge ram_cs_dly1 ); + #5ns; + //while(1)begin + #1ns; + REGFILE_CHECK(6'd3,32'h8765_4000); + REGFILE_CHECK(6'd3,32'h8765_4321); + REGFILE_CHECK(6'd4,32'hfedc_b000); + REGFILE_CHECK(6'd4,32'hfedc_b7f5); + REGFILE_CHECK(6'd1,32'h0010_0000); + DRAM_DATA_CHECK(10'd0,32'h8765_4321); + DRAM_DATA_CHECK(10'd1,32'hfedc_b7f5); + DRAM_DATA_CHECK(10'd500,32'h0000_0000); + DRAM_DATA_CHECK(10'd501,32'h0000_0000); + DRAM_DATA_CHECK(10'd500,32'h0000_0021); + DRAM_DATA_CHECK(10'd500,32'h0000_2121); + DRAM_DATA_CHECK(10'd500,32'h0021_2121); + DRAM_DATA_CHECK(10'd500,32'h2121_2121); + DRAM_DATA_CHECK(10'd501,32'h0000_00f5); + DRAM_DATA_CHECK(10'd501,32'h0000_f5f5); + DRAM_DATA_CHECK(10'd501,32'h00f5_f5f5); + DRAM_DATA_CHECK(10'd501,32'hf5f5_f5f5); + //@(posedge reg_en_dly1 ); + + #10us; + TEST_PASS; +end + +task DRAM_DATA_CHECK; + input [9:0] addr ; + input [31:0] edata ; + + logic [31:0] ram_data; + + @(posedge ram_cs_dly1 ); + @(posedge ram_clk ); + //$monitor($time, " Simulation time: %t", $time); + if(ram_cs_dly1) begin + ram_data = `TB_DRAM.mem[addr]; + //$display("* RAM_DATA[%x]: %x | EXP_DATA: %x ",addr,ram_data, edata); + if(ram_data !== edata) begin + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,ram_data, edata); + #1us; + TEST_FAIL; + end + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, ram_data, edata); + end + else begin + $display("* DRAM CS is High => Error!!!"); + TEST_FAIL; + end +endtask + +task REGFILE_CHECK; + input [4:0] addr ; + input [31:0] edata ; + + logic [31:0] reg_data; + @(posedge reg_en ); + @(posedge reg_clk); + if(reg_en)begin + reg_data = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_dat; + if(reg_data !== edata) begin + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,reg_data, edata); + #1us; + //TEST_FAIL; + end + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, reg_data, edata); + end + else begin + $display("* REG WR EN is High => Error!!!"); + //TEST_FAIL; + end + +endtask + +initial begin + #100us; + $display("\n----------------------------------------\n"); + $display("\t Timeout Error !!!!\n"); + TEST_FAIL; +end + diff --git a/tb/qumcu/isa/case/Sh_test/main.c b/tb/qumcu/isa/case/Sh_test/main.c new file mode 100644 index 0000000..f92eb3f --- /dev/null +++ b/tb/qumcu/isa/case/Sh_test/main.c @@ -0,0 +1,20 @@ +//#include + + +//int main(){ +// printf("\t=====================================\n"); +// printf("\t hello world !!! \n"); +// printf("\t=====================================\n"); +//} + +void main(void){ + +unsigned int a,b; + a=5; + b=3; + //c=a+b; + //d=c+b; +} + + + diff --git a/tb/qumcu/isa/case/Sh_test/main.s b/tb/qumcu/isa/case/Sh_test/main.s new file mode 100644 index 0000000..d796da5 --- /dev/null +++ b/tb/qumcu/isa/case/Sh_test/main.s @@ -0,0 +1,19 @@ +lui x3,0x87654 +addi x3,x3,0x321 +lui x4,0xfedcb +addi x4,x4,0x7f5 +lui x1,0x100 +sw x3 ,0x0(x1) +sw x4 ,0x4(x1) +sw x0 ,0x7d0(x1) +sw x0 ,0x7d4(x1) +sh x3 ,0x7d0(x1) +sh x3 ,0x7d0(x1) +sh x3 ,0x7d2(x1) +sh x3 ,0x7d2(x1) +sh x4 ,0x7d4(x1) +sh x4 ,0x7d4(x1) +sh x4 ,0x7d6(x1) +sh x4 ,0x7d6(x1) +exit: + diff --git a/tb/qumcu/isa/case/Sh_test/user.sv b/tb/qumcu/isa/case/Sh_test/user.sv new file mode 100644 index 0000000..2eac1d4 --- /dev/null +++ b/tb/qumcu/isa/case/Sh_test/user.sv @@ -0,0 +1,97 @@ + +wire ram_clk = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CLK; +wire ram_cs = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CEBA; +wire reg_clk = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.clk; +wire reg_en = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_wen; +reg ram_cs_dly1 ; +reg reg_en_dly1 ; +always @(posedge ram_clk) begin + ram_cs_dly1 <= ~ram_cs; + reg_en_dly1 <= reg_en; +end + + +initial begin + #1ns; + //@(posedge ram_cs_dly1 ); + #5ns; + //while(1)begin + #1ns; + REGFILE_CHECK(6'd3,32'h8765_4000); + REGFILE_CHECK(6'd3,32'h8765_4321); + REGFILE_CHECK(6'd4,32'hfedc_b000); + REGFILE_CHECK(6'd4,32'hfedc_b7f5); + REGFILE_CHECK(6'd1,32'h0010_0000); + DRAM_DATA_CHECK(10'd0,32'h8765_4321); + DRAM_DATA_CHECK(10'd1,32'hfedc_b7f5); + DRAM_DATA_CHECK(10'd500,32'h0000_0000); + DRAM_DATA_CHECK(10'd501,32'h0000_0000); + DRAM_DATA_CHECK(10'd500,32'h0000_4321); + DRAM_DATA_CHECK(10'd500,32'h0000_4321); + DRAM_DATA_CHECK(10'd500,32'h4321_4321); + DRAM_DATA_CHECK(10'd500,32'h4321_4321); + DRAM_DATA_CHECK(10'd501,32'h0000_b7f5); + DRAM_DATA_CHECK(10'd501,32'h0000_b7f5); + DRAM_DATA_CHECK(10'd501,32'hb7f5_b7f5); + DRAM_DATA_CHECK(10'd501,32'hb7f5_b7f5); + //@(posedge reg_en_dly1 ); + + #10us; + TEST_PASS; +end + +task DRAM_DATA_CHECK; + input [9:0] addr ; + input [31:0] edata ; + + logic [31:0] ram_data; + + @(posedge ram_cs_dly1 ); + @(posedge ram_clk ); + //$monitor($time, " Simulation time: %t", $time); + if(ram_cs_dly1) begin + ram_data = `TB_DRAM.mem[addr]; + //$display("* RAM_DATA[%x]: %x | EXP_DATA: %x ",addr,ram_data, edata); + if(ram_data !== edata) begin + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,ram_data, edata); + #1us; + TEST_FAIL; + end + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, ram_data, edata); + end + else begin + $display("* DRAM CS is High => Error!!!"); + TEST_FAIL; + end +endtask + +task REGFILE_CHECK; + input [4:0] addr ; + input [31:0] edata ; + + logic [31:0] reg_data; + @(posedge reg_en ); + @(posedge reg_clk); + if(reg_en)begin + reg_data = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_dat; + if(reg_data !== edata) begin + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,reg_data, edata); + #1us; + //TEST_FAIL; + end + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, reg_data, edata); + end + else begin + $display("* REG WR EN is High => Error!!!"); + //TEST_FAIL; + end + +endtask + +initial begin + #100us; + $display("\n----------------------------------------\n"); + $display("\t Timeout Error !!!!\n"); + TEST_FAIL; +end + diff --git a/tb/qumcu/isa/case/Sll_0x2_test/main.c b/tb/qumcu/isa/case/Sll_0x2_test/main.c new file mode 100644 index 0000000..f92eb3f --- /dev/null +++ b/tb/qumcu/isa/case/Sll_0x2_test/main.c @@ -0,0 +1,20 @@ +//#include + + +//int main(){ +// printf("\t=====================================\n"); +// printf("\t hello world !!! \n"); +// printf("\t=====================================\n"); +//} + +void main(void){ + +unsigned int a,b; + a=5; + b=3; + //c=a+b; + //d=c+b; +} + + + diff --git a/tb/qumcu/isa/case/Sll_0x2_test/main.s b/tb/qumcu/isa/case/Sll_0x2_test/main.s new file mode 100644 index 0000000..bf58ece --- /dev/null +++ b/tb/qumcu/isa/case/Sll_0x2_test/main.s @@ -0,0 +1,7 @@ +addi x1, x0,1 +addi x2, x0,2 +addi x4, x0, 15 +loop: +sll x1,x1,x2 +bne x1,x0,loop + diff --git a/tb/qumcu/isa/case/Sll_0x2_test/user.sv b/tb/qumcu/isa/case/Sll_0x2_test/user.sv new file mode 100644 index 0000000..44b9b49 --- /dev/null +++ b/tb/qumcu/isa/case/Sll_0x2_test/user.sv @@ -0,0 +1,87 @@ + +wire ram_clk = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CLK; +wire ram_cs = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CEBA; +wire reg_clk = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.clk; +wire reg_en = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_wen; +reg ram_cs_dly1 ; +reg reg_en_dly1 ; +always @(posedge ram_clk) begin + ram_cs_dly1 <= ~ram_cs; + reg_en_dly1 <= reg_en; +end + + +initial begin + #1ns; + //@(posedge ram_cs_dly1 ); + #5ns; + //while(1)begin + #1ns; + REGFILE_CHECK(6'd1,32'h0000_0001); + REGFILE_CHECK(6'd2,32'h0000_0002); + REGFILE_CHECK(6'd4,32'h0000_000f); + for(int i = 1; i < 17; i++) begin + REGFILE_CHECK(6'd1,32'h0000_0001< Error!!!",addr,ram_data, edata); + #1us; + TEST_FAIL; + end + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, ram_data, edata); + end + else begin + $display("* DRAM CS is High => Error!!!"); + TEST_FAIL; + end +endtask + +task REGFILE_CHECK; + input [4:0] addr ; + input [31:0] edata ; + + logic [31:0] reg_data; + @(posedge reg_en ); + @(posedge reg_clk); + if(reg_en)begin + reg_data = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_dat; + if(reg_data !== edata) begin + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,reg_data, edata); + #1us; + //TEST_FAIL; + end + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, reg_data, edata); + end + else begin + $display("* REG WR EN is High => Error!!!"); + //TEST_FAIL; + end + +endtask + +initial begin + #100us; + $display("\n----------------------------------------\n"); + $display("\t Timeout Error !!!!\n"); + TEST_FAIL; +end + diff --git a/tb/qumcu/isa/case/Sll_0x3_test/main.c b/tb/qumcu/isa/case/Sll_0x3_test/main.c new file mode 100644 index 0000000..f92eb3f --- /dev/null +++ b/tb/qumcu/isa/case/Sll_0x3_test/main.c @@ -0,0 +1,20 @@ +//#include + + +//int main(){ +// printf("\t=====================================\n"); +// printf("\t hello world !!! \n"); +// printf("\t=====================================\n"); +//} + +void main(void){ + +unsigned int a,b; + a=5; + b=3; + //c=a+b; + //d=c+b; +} + + + diff --git a/tb/qumcu/isa/case/Sll_0x3_test/main.s b/tb/qumcu/isa/case/Sll_0x3_test/main.s new file mode 100644 index 0000000..fc9c6e7 --- /dev/null +++ b/tb/qumcu/isa/case/Sll_0x3_test/main.s @@ -0,0 +1,7 @@ +addi x1, x0,1 +addi x2, x0,3 +addi x4, x0, 15 +loop: +sll x1,x1,x2 +bne x1,x0,loop + diff --git a/tb/qumcu/isa/case/Sll_0x3_test/user.sv b/tb/qumcu/isa/case/Sll_0x3_test/user.sv new file mode 100644 index 0000000..a3722ce --- /dev/null +++ b/tb/qumcu/isa/case/Sll_0x3_test/user.sv @@ -0,0 +1,87 @@ + +wire ram_clk = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CLK; +wire ram_cs = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CEBA; +wire reg_clk = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.clk; +wire reg_en = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_wen; +reg ram_cs_dly1 ; +reg reg_en_dly1 ; +always @(posedge ram_clk) begin + ram_cs_dly1 <= ~ram_cs; + reg_en_dly1 <= reg_en; +end + + +initial begin + #1ns; + //@(posedge ram_cs_dly1 ); + #5ns; + //while(1)begin + #1ns; + REGFILE_CHECK(6'd1,32'h0000_0001); + REGFILE_CHECK(6'd2,32'h0000_0003); + REGFILE_CHECK(6'd4,32'h0000_000f); + for(int i = 1; i < 12; i++) begin + REGFILE_CHECK(6'd1,32'h0000_0001< Error!!!",addr,ram_data, edata); + #1us; + TEST_FAIL; + end + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, ram_data, edata); + end + else begin + $display("* DRAM CS is High => Error!!!"); + TEST_FAIL; + end +endtask + +task REGFILE_CHECK; + input [4:0] addr ; + input [31:0] edata ; + + logic [31:0] reg_data; + @(posedge reg_en ); + @(posedge reg_clk); + if(reg_en)begin + reg_data = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_dat; + if(reg_data !== edata) begin + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,reg_data, edata); + #1us; + //TEST_FAIL; + end + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, reg_data, edata); + end + else begin + $display("* REG WR EN is High => Error!!!"); + //TEST_FAIL; + end + +endtask + +initial begin + #100us; + $display("\n----------------------------------------\n"); + $display("\t Timeout Error !!!!\n"); + TEST_FAIL; +end + diff --git a/tb/qumcu/isa/case/Sll_0x4_test/main.c b/tb/qumcu/isa/case/Sll_0x4_test/main.c new file mode 100644 index 0000000..f92eb3f --- /dev/null +++ b/tb/qumcu/isa/case/Sll_0x4_test/main.c @@ -0,0 +1,20 @@ +//#include + + +//int main(){ +// printf("\t=====================================\n"); +// printf("\t hello world !!! \n"); +// printf("\t=====================================\n"); +//} + +void main(void){ + +unsigned int a,b; + a=5; + b=3; + //c=a+b; + //d=c+b; +} + + + diff --git a/tb/qumcu/isa/case/Sll_0x4_test/main.s b/tb/qumcu/isa/case/Sll_0x4_test/main.s new file mode 100644 index 0000000..b47539f --- /dev/null +++ b/tb/qumcu/isa/case/Sll_0x4_test/main.s @@ -0,0 +1,7 @@ +addi x1, x0,1 +addi x2, x0,4 +addi x4, x0, 15 +loop: +sll x1,x1,x2 +bne x1,x0,loop + diff --git a/tb/qumcu/isa/case/Sll_0x4_test/user.sv b/tb/qumcu/isa/case/Sll_0x4_test/user.sv new file mode 100644 index 0000000..ff253ca --- /dev/null +++ b/tb/qumcu/isa/case/Sll_0x4_test/user.sv @@ -0,0 +1,87 @@ + +wire ram_clk = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CLK; +wire ram_cs = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CEBA; +wire reg_clk = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.clk; +wire reg_en = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_wen; +reg ram_cs_dly1 ; +reg reg_en_dly1 ; +always @(posedge ram_clk) begin + ram_cs_dly1 <= ~ram_cs; + reg_en_dly1 <= reg_en; +end + + +initial begin + #1ns; + //@(posedge ram_cs_dly1 ); + #5ns; + //while(1)begin + #1ns; + REGFILE_CHECK(6'd1,32'h0000_0001); + REGFILE_CHECK(6'd2,32'h0000_0004); + REGFILE_CHECK(6'd4,32'h0000_000f); + for(int i = 1; i < 9; i++) begin + REGFILE_CHECK(6'd1,32'h0000_0001< Error!!!",addr,ram_data, edata); + #1us; + TEST_FAIL; + end + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, ram_data, edata); + end + else begin + $display("* DRAM CS is High => Error!!!"); + TEST_FAIL; + end +endtask + +task REGFILE_CHECK; + input [4:0] addr ; + input [31:0] edata ; + + logic [31:0] reg_data; + @(posedge reg_en ); + @(posedge reg_clk); + if(reg_en)begin + reg_data = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_dat; + if(reg_data !== edata) begin + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,reg_data, edata); + #1us; + //TEST_FAIL; + end + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, reg_data, edata); + end + else begin + $display("* REG WR EN is High => Error!!!"); + //TEST_FAIL; + end + +endtask + +initial begin + #100us; + $display("\n----------------------------------------\n"); + $display("\t Timeout Error !!!!\n"); + TEST_FAIL; +end + diff --git a/tb/qumcu/isa/case/Sll_0x5_test/main.c b/tb/qumcu/isa/case/Sll_0x5_test/main.c new file mode 100644 index 0000000..f92eb3f --- /dev/null +++ b/tb/qumcu/isa/case/Sll_0x5_test/main.c @@ -0,0 +1,20 @@ +//#include + + +//int main(){ +// printf("\t=====================================\n"); +// printf("\t hello world !!! \n"); +// printf("\t=====================================\n"); +//} + +void main(void){ + +unsigned int a,b; + a=5; + b=3; + //c=a+b; + //d=c+b; +} + + + diff --git a/tb/qumcu/isa/case/Sll_0x5_test/main.s b/tb/qumcu/isa/case/Sll_0x5_test/main.s new file mode 100644 index 0000000..6158749 --- /dev/null +++ b/tb/qumcu/isa/case/Sll_0x5_test/main.s @@ -0,0 +1,7 @@ +addi x1, x0,1 +addi x2, x0,5 +addi x4, x0, 15 +loop: +sll x1,x1,x2 +bne x1,x0,loop + diff --git a/tb/qumcu/isa/case/Sll_0x5_test/user.sv b/tb/qumcu/isa/case/Sll_0x5_test/user.sv new file mode 100644 index 0000000..60127d6 --- /dev/null +++ b/tb/qumcu/isa/case/Sll_0x5_test/user.sv @@ -0,0 +1,87 @@ + +wire ram_clk = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CLK; +wire ram_cs = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CEBA; +wire reg_clk = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.clk; +wire reg_en = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_wen; +reg ram_cs_dly1 ; +reg reg_en_dly1 ; +always @(posedge ram_clk) begin + ram_cs_dly1 <= ~ram_cs; + reg_en_dly1 <= reg_en; +end + + +initial begin + #1ns; + //@(posedge ram_cs_dly1 ); + #5ns; + //while(1)begin + #1ns; + REGFILE_CHECK(6'd1,32'h0000_0001); + REGFILE_CHECK(6'd2,32'h0000_0005); + REGFILE_CHECK(6'd4,32'h0000_000f); + for(int i = 1; i < 8; i++) begin + REGFILE_CHECK(6'd1,32'h0000_0001< Error!!!",addr,ram_data, edata); + #1us; + TEST_FAIL; + end + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, ram_data, edata); + end + else begin + $display("* DRAM CS is High => Error!!!"); + TEST_FAIL; + end +endtask + +task REGFILE_CHECK; + input [4:0] addr ; + input [31:0] edata ; + + logic [31:0] reg_data; + @(posedge reg_en ); + @(posedge reg_clk); + if(reg_en)begin + reg_data = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_dat; + if(reg_data !== edata) begin + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,reg_data, edata); + #1us; + //TEST_FAIL; + end + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, reg_data, edata); + end + else begin + $display("* REG WR EN is High => Error!!!"); + //TEST_FAIL; + end + +endtask + +initial begin + #100us; + $display("\n----------------------------------------\n"); + $display("\t Timeout Error !!!!\n"); + TEST_FAIL; +end + diff --git a/tb/qumcu/isa/case/Sll_0x6_test/main.c b/tb/qumcu/isa/case/Sll_0x6_test/main.c new file mode 100644 index 0000000..f92eb3f --- /dev/null +++ b/tb/qumcu/isa/case/Sll_0x6_test/main.c @@ -0,0 +1,20 @@ +//#include + + +//int main(){ +// printf("\t=====================================\n"); +// printf("\t hello world !!! \n"); +// printf("\t=====================================\n"); +//} + +void main(void){ + +unsigned int a,b; + a=5; + b=3; + //c=a+b; + //d=c+b; +} + + + diff --git a/tb/qumcu/isa/case/Sll_0x6_test/main.s b/tb/qumcu/isa/case/Sll_0x6_test/main.s new file mode 100644 index 0000000..96458fc --- /dev/null +++ b/tb/qumcu/isa/case/Sll_0x6_test/main.s @@ -0,0 +1,7 @@ +addi x1, x0,1 +addi x2, x0,6 +addi x4, x0, 15 +loop: +sll x1,x1,x2 +bne x1,x0,loop + diff --git a/tb/qumcu/isa/case/Sll_0x6_test/user.sv b/tb/qumcu/isa/case/Sll_0x6_test/user.sv new file mode 100644 index 0000000..b79093c --- /dev/null +++ b/tb/qumcu/isa/case/Sll_0x6_test/user.sv @@ -0,0 +1,87 @@ + +wire ram_clk = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CLK; +wire ram_cs = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CEBA; +wire reg_clk = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.clk; +wire reg_en = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_wen; +reg ram_cs_dly1 ; +reg reg_en_dly1 ; +always @(posedge ram_clk) begin + ram_cs_dly1 <= ~ram_cs; + reg_en_dly1 <= reg_en; +end + + +initial begin + #1ns; + //@(posedge ram_cs_dly1 ); + #5ns; + //while(1)begin + #1ns; + REGFILE_CHECK(6'd1,32'h0000_0001); + REGFILE_CHECK(6'd2,32'h0000_0006); + REGFILE_CHECK(6'd4,32'h0000_000f); + for(int i = 1; i < 7; i++) begin + REGFILE_CHECK(6'd1,32'h0000_0001< Error!!!",addr,ram_data, edata); + #1us; + TEST_FAIL; + end + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, ram_data, edata); + end + else begin + $display("* DRAM CS is High => Error!!!"); + TEST_FAIL; + end +endtask + +task REGFILE_CHECK; + input [4:0] addr ; + input [31:0] edata ; + + logic [31:0] reg_data; + @(posedge reg_en ); + @(posedge reg_clk); + if(reg_en)begin + reg_data = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_dat; + if(reg_data !== edata) begin + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,reg_data, edata); + #1us; + //TEST_FAIL; + end + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, reg_data, edata); + end + else begin + $display("* REG WR EN is High => Error!!!"); + //TEST_FAIL; + end + +endtask + +initial begin + #100us; + $display("\n----------------------------------------\n"); + $display("\t Timeout Error !!!!\n"); + TEST_FAIL; +end + diff --git a/tb/qumcu/isa/case/Sll_0x7_test/main.c b/tb/qumcu/isa/case/Sll_0x7_test/main.c new file mode 100644 index 0000000..f92eb3f --- /dev/null +++ b/tb/qumcu/isa/case/Sll_0x7_test/main.c @@ -0,0 +1,20 @@ +//#include + + +//int main(){ +// printf("\t=====================================\n"); +// printf("\t hello world !!! \n"); +// printf("\t=====================================\n"); +//} + +void main(void){ + +unsigned int a,b; + a=5; + b=3; + //c=a+b; + //d=c+b; +} + + + diff --git a/tb/qumcu/isa/case/Sll_0x7_test/main.s b/tb/qumcu/isa/case/Sll_0x7_test/main.s new file mode 100644 index 0000000..5b7c174 --- /dev/null +++ b/tb/qumcu/isa/case/Sll_0x7_test/main.s @@ -0,0 +1,7 @@ +addi x1, x0,1 +addi x2, x0,7 +addi x4, x0, 15 +loop: +sll x1,x1,x2 +bne x1,x0,loop + diff --git a/tb/qumcu/isa/case/Sll_0x7_test/user.sv b/tb/qumcu/isa/case/Sll_0x7_test/user.sv new file mode 100644 index 0000000..1c37817 --- /dev/null +++ b/tb/qumcu/isa/case/Sll_0x7_test/user.sv @@ -0,0 +1,87 @@ + +wire ram_clk = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CLK; +wire ram_cs = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CEBA; +wire reg_clk = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.clk; +wire reg_en = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_wen; +reg ram_cs_dly1 ; +reg reg_en_dly1 ; +always @(posedge ram_clk) begin + ram_cs_dly1 <= ~ram_cs; + reg_en_dly1 <= reg_en; +end + + +initial begin + #1ns; + //@(posedge ram_cs_dly1 ); + #5ns; + //while(1)begin + #1ns; + REGFILE_CHECK(6'd1,32'h0000_0001); + REGFILE_CHECK(6'd2,32'h0000_0007); + REGFILE_CHECK(6'd4,32'h0000_000f); + for(int i = 1; i < 6; i++) begin + REGFILE_CHECK(6'd1,32'h0000_0001< Error!!!",addr,ram_data, edata); + #1us; + TEST_FAIL; + end + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, ram_data, edata); + end + else begin + $display("* DRAM CS is High => Error!!!"); + TEST_FAIL; + end +endtask + +task REGFILE_CHECK; + input [4:0] addr ; + input [31:0] edata ; + + logic [31:0] reg_data; + @(posedge reg_en ); + @(posedge reg_clk); + if(reg_en)begin + reg_data = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_dat; + if(reg_data !== edata) begin + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,reg_data, edata); + #1us; + //TEST_FAIL; + end + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, reg_data, edata); + end + else begin + $display("* REG WR EN is High => Error!!!"); + //TEST_FAIL; + end + +endtask + +initial begin + #100us; + $display("\n----------------------------------------\n"); + $display("\t Timeout Error !!!!\n"); + TEST_FAIL; +end + diff --git a/tb/qumcu/isa/case/Sll_0x8_test/main.c b/tb/qumcu/isa/case/Sll_0x8_test/main.c new file mode 100644 index 0000000..f92eb3f --- /dev/null +++ b/tb/qumcu/isa/case/Sll_0x8_test/main.c @@ -0,0 +1,20 @@ +//#include + + +//int main(){ +// printf("\t=====================================\n"); +// printf("\t hello world !!! \n"); +// printf("\t=====================================\n"); +//} + +void main(void){ + +unsigned int a,b; + a=5; + b=3; + //c=a+b; + //d=c+b; +} + + + diff --git a/tb/qumcu/isa/case/Sll_0x8_test/main.s b/tb/qumcu/isa/case/Sll_0x8_test/main.s new file mode 100644 index 0000000..51993cc --- /dev/null +++ b/tb/qumcu/isa/case/Sll_0x8_test/main.s @@ -0,0 +1,7 @@ +addi x1, x0,1 +addi x2, x0,8 +addi x4, x0, 15 +loop: +sll x1,x1,x2 +bne x1,x0,loop + diff --git a/tb/qumcu/isa/case/Sll_0x8_test/user.sv b/tb/qumcu/isa/case/Sll_0x8_test/user.sv new file mode 100644 index 0000000..d6c1f3d --- /dev/null +++ b/tb/qumcu/isa/case/Sll_0x8_test/user.sv @@ -0,0 +1,87 @@ + +wire ram_clk = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CLK; +wire ram_cs = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CEBA; +wire reg_clk = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.clk; +wire reg_en = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_wen; +reg ram_cs_dly1 ; +reg reg_en_dly1 ; +always @(posedge ram_clk) begin + ram_cs_dly1 <= ~ram_cs; + reg_en_dly1 <= reg_en; +end + + +initial begin + #1ns; + //@(posedge ram_cs_dly1 ); + #5ns; + //while(1)begin + #1ns; + REGFILE_CHECK(6'd1,32'h0000_0001); + REGFILE_CHECK(6'd2,32'h0000_0008); + REGFILE_CHECK(6'd4,32'h0000_000f); + for(int i = 1; i < 5; i++) begin + REGFILE_CHECK(6'd1,32'h0000_0001< Error!!!",addr,ram_data, edata); + #1us; + TEST_FAIL; + end + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, ram_data, edata); + end + else begin + $display("* DRAM CS is High => Error!!!"); + TEST_FAIL; + end +endtask + +task REGFILE_CHECK; + input [4:0] addr ; + input [31:0] edata ; + + logic [31:0] reg_data; + @(posedge reg_en ); + @(posedge reg_clk); + if(reg_en)begin + reg_data = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_dat; + if(reg_data !== edata) begin + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,reg_data, edata); + #1us; + //TEST_FAIL; + end + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, reg_data, edata); + end + else begin + $display("* REG WR EN is High => Error!!!"); + //TEST_FAIL; + end + +endtask + +initial begin + #100us; + $display("\n----------------------------------------\n"); + $display("\t Timeout Error !!!!\n"); + TEST_FAIL; +end + diff --git a/tb/qumcu/isa/case/Sll_0x9_test/main.c b/tb/qumcu/isa/case/Sll_0x9_test/main.c new file mode 100644 index 0000000..f92eb3f --- /dev/null +++ b/tb/qumcu/isa/case/Sll_0x9_test/main.c @@ -0,0 +1,20 @@ +//#include + + +//int main(){ +// printf("\t=====================================\n"); +// printf("\t hello world !!! \n"); +// printf("\t=====================================\n"); +//} + +void main(void){ + +unsigned int a,b; + a=5; + b=3; + //c=a+b; + //d=c+b; +} + + + diff --git a/tb/qumcu/isa/case/Sll_0x9_test/main.s b/tb/qumcu/isa/case/Sll_0x9_test/main.s new file mode 100644 index 0000000..9210d61 --- /dev/null +++ b/tb/qumcu/isa/case/Sll_0x9_test/main.s @@ -0,0 +1,7 @@ +addi x1, x0,1 +addi x2, x0,9 +addi x4, x0, 15 +loop: +sll x1,x1,x2 +bne x1,x0,loop + diff --git a/tb/qumcu/isa/case/Sll_0x9_test/user.sv b/tb/qumcu/isa/case/Sll_0x9_test/user.sv new file mode 100644 index 0000000..854c12a --- /dev/null +++ b/tb/qumcu/isa/case/Sll_0x9_test/user.sv @@ -0,0 +1,87 @@ + +wire ram_clk = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CLK; +wire ram_cs = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CEBA; +wire reg_clk = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.clk; +wire reg_en = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_wen; +reg ram_cs_dly1 ; +reg reg_en_dly1 ; +always @(posedge ram_clk) begin + ram_cs_dly1 <= ~ram_cs; + reg_en_dly1 <= reg_en; +end + + +initial begin + #1ns; + //@(posedge ram_cs_dly1 ); + #5ns; + //while(1)begin + #1ns; + REGFILE_CHECK(6'd1,32'h0000_0001); + REGFILE_CHECK(6'd2,32'h0000_0009); + REGFILE_CHECK(6'd4,32'h0000_000f); + for(int i = 1; i < 5; i++) begin + REGFILE_CHECK(6'd1,32'h0000_0001< Error!!!",addr,ram_data, edata); + #1us; + TEST_FAIL; + end + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, ram_data, edata); + end + else begin + $display("* DRAM CS is High => Error!!!"); + TEST_FAIL; + end +endtask + +task REGFILE_CHECK; + input [4:0] addr ; + input [31:0] edata ; + + logic [31:0] reg_data; + @(posedge reg_en ); + @(posedge reg_clk); + if(reg_en)begin + reg_data = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_dat; + if(reg_data !== edata) begin + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,reg_data, edata); + #1us; + //TEST_FAIL; + end + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, reg_data, edata); + end + else begin + $display("* REG WR EN is High => Error!!!"); + //TEST_FAIL; + end + +endtask + +initial begin + #100us; + $display("\n----------------------------------------\n"); + $display("\t Timeout Error !!!!\n"); + TEST_FAIL; +end + diff --git a/tb/qumcu/isa/case/Sll_0xa_test/main.c b/tb/qumcu/isa/case/Sll_0xa_test/main.c new file mode 100644 index 0000000..f92eb3f --- /dev/null +++ b/tb/qumcu/isa/case/Sll_0xa_test/main.c @@ -0,0 +1,20 @@ +//#include + + +//int main(){ +// printf("\t=====================================\n"); +// printf("\t hello world !!! \n"); +// printf("\t=====================================\n"); +//} + +void main(void){ + +unsigned int a,b; + a=5; + b=3; + //c=a+b; + //d=c+b; +} + + + diff --git a/tb/qumcu/isa/case/Sll_0xa_test/main.s b/tb/qumcu/isa/case/Sll_0xa_test/main.s new file mode 100644 index 0000000..723f4f7 --- /dev/null +++ b/tb/qumcu/isa/case/Sll_0xa_test/main.s @@ -0,0 +1,7 @@ +addi x1, x0,1 +addi x2, x0,10 +addi x4, x0, 15 +loop: +sll x1,x1,x2 +bne x1,x0,loop + diff --git a/tb/qumcu/isa/case/Sll_0xa_test/user.sv b/tb/qumcu/isa/case/Sll_0xa_test/user.sv new file mode 100644 index 0000000..4ab8e6d --- /dev/null +++ b/tb/qumcu/isa/case/Sll_0xa_test/user.sv @@ -0,0 +1,87 @@ + +wire ram_clk = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CLK; +wire ram_cs = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CEBA; +wire reg_clk = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.clk; +wire reg_en = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_wen; +reg ram_cs_dly1 ; +reg reg_en_dly1 ; +always @(posedge ram_clk) begin + ram_cs_dly1 <= ~ram_cs; + reg_en_dly1 <= reg_en; +end + + +initial begin + #1ns; + //@(posedge ram_cs_dly1 ); + #5ns; + //while(1)begin + #1ns; + REGFILE_CHECK(6'd1,32'h0000_0001); + REGFILE_CHECK(6'd2,32'h0000_000a); + REGFILE_CHECK(6'd4,32'h0000_000f); + for(int i = 1; i < 5; i++) begin + REGFILE_CHECK(6'd1,32'h0000_0001< Error!!!",addr,ram_data, edata); + #1us; + TEST_FAIL; + end + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, ram_data, edata); + end + else begin + $display("* DRAM CS is High => Error!!!"); + TEST_FAIL; + end +endtask + +task REGFILE_CHECK; + input [4:0] addr ; + input [31:0] edata ; + + logic [31:0] reg_data; + @(posedge reg_en ); + @(posedge reg_clk); + if(reg_en)begin + reg_data = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_dat; + if(reg_data !== edata) begin + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,reg_data, edata); + #1us; + //TEST_FAIL; + end + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, reg_data, edata); + end + else begin + $display("* REG WR EN is High => Error!!!"); + //TEST_FAIL; + end + +endtask + +initial begin + #100us; + $display("\n----------------------------------------\n"); + $display("\t Timeout Error !!!!\n"); + TEST_FAIL; +end + diff --git a/tb/qumcu/isa/case/Sll_0xb_test/main.c b/tb/qumcu/isa/case/Sll_0xb_test/main.c new file mode 100644 index 0000000..f92eb3f --- /dev/null +++ b/tb/qumcu/isa/case/Sll_0xb_test/main.c @@ -0,0 +1,20 @@ +//#include + + +//int main(){ +// printf("\t=====================================\n"); +// printf("\t hello world !!! \n"); +// printf("\t=====================================\n"); +//} + +void main(void){ + +unsigned int a,b; + a=5; + b=3; + //c=a+b; + //d=c+b; +} + + + diff --git a/tb/qumcu/isa/case/Sll_0xb_test/main.s b/tb/qumcu/isa/case/Sll_0xb_test/main.s new file mode 100644 index 0000000..2ed32cc --- /dev/null +++ b/tb/qumcu/isa/case/Sll_0xb_test/main.s @@ -0,0 +1,7 @@ +addi x1, x0,1 +addi x2, x0,11 +addi x4, x0, 15 +loop: +sll x1,x1,x2 +bne x1,x0,loop + diff --git a/tb/qumcu/isa/case/Sll_0xb_test/user.sv b/tb/qumcu/isa/case/Sll_0xb_test/user.sv new file mode 100644 index 0000000..63a7c27 --- /dev/null +++ b/tb/qumcu/isa/case/Sll_0xb_test/user.sv @@ -0,0 +1,87 @@ + +wire ram_clk = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CLK; +wire ram_cs = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CEBA; +wire reg_clk = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.clk; +wire reg_en = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_wen; +reg ram_cs_dly1 ; +reg reg_en_dly1 ; +always @(posedge ram_clk) begin + ram_cs_dly1 <= ~ram_cs; + reg_en_dly1 <= reg_en; +end + + +initial begin + #1ns; + //@(posedge ram_cs_dly1 ); + #5ns; + //while(1)begin + #1ns; + REGFILE_CHECK(6'd1,32'h0000_0001); + REGFILE_CHECK(6'd2,32'h0000_000b); + REGFILE_CHECK(6'd4,32'h0000_000f); + for(int i = 1; i < 4; i++) begin + REGFILE_CHECK(6'd1,32'h0000_0001< Error!!!",addr,ram_data, edata); + #1us; + TEST_FAIL; + end + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, ram_data, edata); + end + else begin + $display("* DRAM CS is High => Error!!!"); + TEST_FAIL; + end +endtask + +task REGFILE_CHECK; + input [4:0] addr ; + input [31:0] edata ; + + logic [31:0] reg_data; + @(posedge reg_en ); + @(posedge reg_clk); + if(reg_en)begin + reg_data = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_dat; + if(reg_data !== edata) begin + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,reg_data, edata); + #1us; + //TEST_FAIL; + end + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, reg_data, edata); + end + else begin + $display("* REG WR EN is High => Error!!!"); + //TEST_FAIL; + end + +endtask + +initial begin + #100us; + $display("\n----------------------------------------\n"); + $display("\t Timeout Error !!!!\n"); + TEST_FAIL; +end + diff --git a/tb/qumcu/isa/case/Sll_0xc_test/main.c b/tb/qumcu/isa/case/Sll_0xc_test/main.c new file mode 100644 index 0000000..f92eb3f --- /dev/null +++ b/tb/qumcu/isa/case/Sll_0xc_test/main.c @@ -0,0 +1,20 @@ +//#include + + +//int main(){ +// printf("\t=====================================\n"); +// printf("\t hello world !!! \n"); +// printf("\t=====================================\n"); +//} + +void main(void){ + +unsigned int a,b; + a=5; + b=3; + //c=a+b; + //d=c+b; +} + + + diff --git a/tb/qumcu/isa/case/Sll_0xc_test/main.s b/tb/qumcu/isa/case/Sll_0xc_test/main.s new file mode 100644 index 0000000..7b3f973 --- /dev/null +++ b/tb/qumcu/isa/case/Sll_0xc_test/main.s @@ -0,0 +1,7 @@ +addi x1, x0,1 +addi x2, x0,12 +addi x4, x0, 15 +loop: +sll x1,x1,x2 +bne x1,x0,loop + diff --git a/tb/qumcu/isa/case/Sll_0xc_test/user.sv b/tb/qumcu/isa/case/Sll_0xc_test/user.sv new file mode 100644 index 0000000..b06e9d0 --- /dev/null +++ b/tb/qumcu/isa/case/Sll_0xc_test/user.sv @@ -0,0 +1,87 @@ + +wire ram_clk = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CLK; +wire ram_cs = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CEBA; +wire reg_clk = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.clk; +wire reg_en = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_wen; +reg ram_cs_dly1 ; +reg reg_en_dly1 ; +always @(posedge ram_clk) begin + ram_cs_dly1 <= ~ram_cs; + reg_en_dly1 <= reg_en; +end + + +initial begin + #1ns; + //@(posedge ram_cs_dly1 ); + #5ns; + //while(1)begin + #1ns; + REGFILE_CHECK(6'd1,32'h0000_0001); + REGFILE_CHECK(6'd2,32'h0000_000c); + REGFILE_CHECK(6'd4,32'h0000_000f); + for(int i = 1; i < 4; i++) begin + REGFILE_CHECK(6'd1,32'h0000_0001< Error!!!",addr,ram_data, edata); + #1us; + TEST_FAIL; + end + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, ram_data, edata); + end + else begin + $display("* DRAM CS is High => Error!!!"); + TEST_FAIL; + end +endtask + +task REGFILE_CHECK; + input [4:0] addr ; + input [31:0] edata ; + + logic [31:0] reg_data; + @(posedge reg_en ); + @(posedge reg_clk); + if(reg_en)begin + reg_data = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_dat; + if(reg_data !== edata) begin + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,reg_data, edata); + #1us; + //TEST_FAIL; + end + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, reg_data, edata); + end + else begin + $display("* REG WR EN is High => Error!!!"); + //TEST_FAIL; + end + +endtask + +initial begin + #100us; + $display("\n----------------------------------------\n"); + $display("\t Timeout Error !!!!\n"); + TEST_FAIL; +end + diff --git a/tb/qumcu/isa/case/Sll_0xd_test/main.c b/tb/qumcu/isa/case/Sll_0xd_test/main.c new file mode 100644 index 0000000..f92eb3f --- /dev/null +++ b/tb/qumcu/isa/case/Sll_0xd_test/main.c @@ -0,0 +1,20 @@ +//#include + + +//int main(){ +// printf("\t=====================================\n"); +// printf("\t hello world !!! \n"); +// printf("\t=====================================\n"); +//} + +void main(void){ + +unsigned int a,b; + a=5; + b=3; + //c=a+b; + //d=c+b; +} + + + diff --git a/tb/qumcu/isa/case/Sll_0xd_test/main.s b/tb/qumcu/isa/case/Sll_0xd_test/main.s new file mode 100644 index 0000000..a08fe88 --- /dev/null +++ b/tb/qumcu/isa/case/Sll_0xd_test/main.s @@ -0,0 +1,7 @@ +addi x1, x0,1 +addi x2, x0,13 +addi x4, x0, 15 +loop: +sll x1,x1,x2 +bne x1,x0,loop + diff --git a/tb/qumcu/isa/case/Sll_0xd_test/user.sv b/tb/qumcu/isa/case/Sll_0xd_test/user.sv new file mode 100644 index 0000000..6fc59dc --- /dev/null +++ b/tb/qumcu/isa/case/Sll_0xd_test/user.sv @@ -0,0 +1,87 @@ + +wire ram_clk = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CLK; +wire ram_cs = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CEBA; +wire reg_clk = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.clk; +wire reg_en = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_wen; +reg ram_cs_dly1 ; +reg reg_en_dly1 ; +always @(posedge ram_clk) begin + ram_cs_dly1 <= ~ram_cs; + reg_en_dly1 <= reg_en; +end + + +initial begin + #1ns; + //@(posedge ram_cs_dly1 ); + #5ns; + //while(1)begin + #1ns; + REGFILE_CHECK(6'd1,32'h0000_0001); + REGFILE_CHECK(6'd2,32'h0000_000d); + REGFILE_CHECK(6'd4,32'h0000_000f); + for(int i = 1; i < 4; i++) begin + REGFILE_CHECK(6'd1,32'h0000_0001< Error!!!",addr,ram_data, edata); + #1us; + TEST_FAIL; + end + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, ram_data, edata); + end + else begin + $display("* DRAM CS is High => Error!!!"); + TEST_FAIL; + end +endtask + +task REGFILE_CHECK; + input [4:0] addr ; + input [31:0] edata ; + + logic [31:0] reg_data; + @(posedge reg_en ); + @(posedge reg_clk); + if(reg_en)begin + reg_data = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_dat; + if(reg_data !== edata) begin + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,reg_data, edata); + #1us; + //TEST_FAIL; + end + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, reg_data, edata); + end + else begin + $display("* REG WR EN is High => Error!!!"); + //TEST_FAIL; + end + +endtask + +initial begin + #100us; + $display("\n----------------------------------------\n"); + $display("\t Timeout Error !!!!\n"); + TEST_FAIL; +end + diff --git a/tb/qumcu/isa/case/Sll_0xe_test/main.c b/tb/qumcu/isa/case/Sll_0xe_test/main.c new file mode 100644 index 0000000..f92eb3f --- /dev/null +++ b/tb/qumcu/isa/case/Sll_0xe_test/main.c @@ -0,0 +1,20 @@ +//#include + + +//int main(){ +// printf("\t=====================================\n"); +// printf("\t hello world !!! \n"); +// printf("\t=====================================\n"); +//} + +void main(void){ + +unsigned int a,b; + a=5; + b=3; + //c=a+b; + //d=c+b; +} + + + diff --git a/tb/qumcu/isa/case/Sll_0xe_test/main.s b/tb/qumcu/isa/case/Sll_0xe_test/main.s new file mode 100644 index 0000000..2f497f2 --- /dev/null +++ b/tb/qumcu/isa/case/Sll_0xe_test/main.s @@ -0,0 +1,7 @@ +addi x1, x0,1 +addi x2, x0,14 +addi x4, x0, 15 +loop: +sll x1,x1,x2 +bne x1,x0,loop + diff --git a/tb/qumcu/isa/case/Sll_0xe_test/user.sv b/tb/qumcu/isa/case/Sll_0xe_test/user.sv new file mode 100644 index 0000000..0815a76 --- /dev/null +++ b/tb/qumcu/isa/case/Sll_0xe_test/user.sv @@ -0,0 +1,87 @@ + +wire ram_clk = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CLK; +wire ram_cs = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CEBA; +wire reg_clk = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.clk; +wire reg_en = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_wen; +reg ram_cs_dly1 ; +reg reg_en_dly1 ; +always @(posedge ram_clk) begin + ram_cs_dly1 <= ~ram_cs; + reg_en_dly1 <= reg_en; +end + + +initial begin + #1ns; + //@(posedge ram_cs_dly1 ); + #5ns; + //while(1)begin + #1ns; + REGFILE_CHECK(6'd1,32'h0000_0001); + REGFILE_CHECK(6'd2,32'h0000_000e); + REGFILE_CHECK(6'd4,32'h0000_000f); + for(int i = 1; i < 4; i++) begin + REGFILE_CHECK(6'd1,32'h0000_0001< Error!!!",addr,ram_data, edata); + #1us; + TEST_FAIL; + end + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, ram_data, edata); + end + else begin + $display("* DRAM CS is High => Error!!!"); + TEST_FAIL; + end +endtask + +task REGFILE_CHECK; + input [4:0] addr ; + input [31:0] edata ; + + logic [31:0] reg_data; + @(posedge reg_en ); + @(posedge reg_clk); + if(reg_en)begin + reg_data = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_dat; + if(reg_data !== edata) begin + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,reg_data, edata); + #1us; + //TEST_FAIL; + end + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, reg_data, edata); + end + else begin + $display("* REG WR EN is High => Error!!!"); + //TEST_FAIL; + end + +endtask + +initial begin + #100us; + $display("\n----------------------------------------\n"); + $display("\t Timeout Error !!!!\n"); + TEST_FAIL; +end + diff --git a/tb/qumcu/isa/case/Sll_0xf20x1f_test/main.c b/tb/qumcu/isa/case/Sll_0xf20x1f_test/main.c new file mode 100644 index 0000000..f92eb3f --- /dev/null +++ b/tb/qumcu/isa/case/Sll_0xf20x1f_test/main.c @@ -0,0 +1,20 @@ +//#include + + +//int main(){ +// printf("\t=====================================\n"); +// printf("\t hello world !!! \n"); +// printf("\t=====================================\n"); +//} + +void main(void){ + +unsigned int a,b; + a=5; + b=3; + //c=a+b; + //d=c+b; +} + + + diff --git a/tb/qumcu/isa/case/Sll_0xf20x1f_test/main.s b/tb/qumcu/isa/case/Sll_0xf20x1f_test/main.s new file mode 100644 index 0000000..73fc080 --- /dev/null +++ b/tb/qumcu/isa/case/Sll_0xf20x1f_test/main.s @@ -0,0 +1,9 @@ + +addi x4, x0, 31 +main_loop: +addi x2, x2,1 +addi x1, x0,1 +loop1: +sll x1,x1,x2 +bne x1,x0,loop1 +bne x2,x4,main_loop \ No newline at end of file diff --git a/tb/qumcu/isa/case/Sll_0xf20x1f_test/user.sv b/tb/qumcu/isa/case/Sll_0xf20x1f_test/user.sv new file mode 100644 index 0000000..0ff2d91 --- /dev/null +++ b/tb/qumcu/isa/case/Sll_0xf20x1f_test/user.sv @@ -0,0 +1,134 @@ + +wire ram_clk = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CLK; +wire ram_cs = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CEBA; +wire reg_clk = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.clk; +wire reg_en = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_wen; +reg ram_cs_dly1 ; +reg reg_en_dly1 ; +always @(posedge ram_clk) begin + ram_cs_dly1 <= ~ram_cs; + reg_en_dly1 <= reg_en; +end + +int q; +initial begin + #1ns; + //@(posedge ram_cs_dly1 ); + #5ns; + //while(1)begin + #1ns; + REGFILE_CHECK(6'd4,32'h0000_001f); + for(int j = 1; j < 32; j++) begin + $display("* loop[%x]", j); + REGFILE_CHECK(6'd2,j); + REGFILE_CHECK(6'd1,32'h0000_0001); + if(j == 1) begin + q = 33; + end + else if(j == 2) begin + q = 17; + end + else if(j == 3) begin + q = 12; + end + else if(j == 4) begin + q = 9; + end + else if(j == 5) begin + q = 8; + end + else if(j == 6) begin + q = 7; + end + else if(j == 7) begin + q = 6; + end + else if(j == 8) begin + q = 5; + end + else if(j == 9) begin + q = 5; + end + else if(j == 10) begin + q = 5; + end + else if(j == 11) begin + q = 4; + end + else if(j == 12) begin + q = 4; + end + else if(j == 13) begin + q = 4; + end + else if(j == 15) begin + q = 4; + end + else if(j >= 16) begin + q = 3; + end + for(int i = 1; i < q; i++) begin + REGFILE_CHECK(6'd1,32'h0000_0001< Error!!!",addr,ram_data, edata); + #1us; + TEST_FAIL; + end + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, ram_data, edata); + end + else begin + $display("* DRAM CS is High => Error!!!"); + TEST_FAIL; + end +endtask + +task REGFILE_CHECK; + input [4:0] addr ; + input [31:0] edata ; + + logic [31:0] reg_data; + @(posedge reg_en ); + @(posedge reg_clk); + if(reg_en)begin + reg_data = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_dat; + if(reg_data !== edata) begin + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,reg_data, edata); + #1us; + //TEST_FAIL; + end + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, reg_data, edata); + end + else begin + $display("* REG WR EN is High => Error!!!"); + //TEST_FAIL; + end + +endtask + +initial begin + #1000us; + $display("\n----------------------------------------\n"); + $display("\t Timeout Error !!!!\n"); + TEST_FAIL; +end + diff --git a/tb/qumcu/isa/case/Sll_0xf_test/main.c b/tb/qumcu/isa/case/Sll_0xf_test/main.c new file mode 100644 index 0000000..f92eb3f --- /dev/null +++ b/tb/qumcu/isa/case/Sll_0xf_test/main.c @@ -0,0 +1,20 @@ +//#include + + +//int main(){ +// printf("\t=====================================\n"); +// printf("\t hello world !!! \n"); +// printf("\t=====================================\n"); +//} + +void main(void){ + +unsigned int a,b; + a=5; + b=3; + //c=a+b; + //d=c+b; +} + + + diff --git a/tb/qumcu/isa/case/Sll_0xf_test/main.s b/tb/qumcu/isa/case/Sll_0xf_test/main.s new file mode 100644 index 0000000..7b33956 --- /dev/null +++ b/tb/qumcu/isa/case/Sll_0xf_test/main.s @@ -0,0 +1,7 @@ +addi x1, x0,1 +addi x2, x0,15 +addi x4, x0, 15 +loop: +sll x1,x1,x2 +bne x1,x0,loop + diff --git a/tb/qumcu/isa/case/Sll_0xf_test/user.sv b/tb/qumcu/isa/case/Sll_0xf_test/user.sv new file mode 100644 index 0000000..2b2a340 --- /dev/null +++ b/tb/qumcu/isa/case/Sll_0xf_test/user.sv @@ -0,0 +1,87 @@ + +wire ram_clk = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CLK; +wire ram_cs = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CEBA; +wire reg_clk = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.clk; +wire reg_en = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_wen; +reg ram_cs_dly1 ; +reg reg_en_dly1 ; +always @(posedge ram_clk) begin + ram_cs_dly1 <= ~ram_cs; + reg_en_dly1 <= reg_en; +end + + +initial begin + #1ns; + //@(posedge ram_cs_dly1 ); + #5ns; + //while(1)begin + #1ns; + REGFILE_CHECK(6'd1,32'h0000_0001); + REGFILE_CHECK(6'd2,32'h0000_000f); + REGFILE_CHECK(6'd4,32'h0000_000f); + for(int i = 1; i < 4; i++) begin + REGFILE_CHECK(6'd1,32'h0000_0001< Error!!!",addr,ram_data, edata); + #1us; + TEST_FAIL; + end + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, ram_data, edata); + end + else begin + $display("* DRAM CS is High => Error!!!"); + TEST_FAIL; + end +endtask + +task REGFILE_CHECK; + input [4:0] addr ; + input [31:0] edata ; + + logic [31:0] reg_data; + @(posedge reg_en ); + @(posedge reg_clk); + if(reg_en)begin + reg_data = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_dat; + if(reg_data !== edata) begin + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,reg_data, edata); + #1us; + //TEST_FAIL; + end + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, reg_data, edata); + end + else begin + $display("* REG WR EN is High => Error!!!"); + //TEST_FAIL; + end + +endtask + +initial begin + #100us; + $display("\n----------------------------------------\n"); + $display("\t Timeout Error !!!!\n"); + TEST_FAIL; +end + diff --git a/tb/qumcu/isa/case/Sll_test/main.c b/tb/qumcu/isa/case/Sll_test/main.c new file mode 100644 index 0000000..f92eb3f --- /dev/null +++ b/tb/qumcu/isa/case/Sll_test/main.c @@ -0,0 +1,20 @@ +//#include + + +//int main(){ +// printf("\t=====================================\n"); +// printf("\t hello world !!! \n"); +// printf("\t=====================================\n"); +//} + +void main(void){ + +unsigned int a,b; + a=5; + b=3; + //c=a+b; + //d=c+b; +} + + + diff --git a/tb/qumcu/isa/case/Sll_test/main.s b/tb/qumcu/isa/case/Sll_test/main.s new file mode 100644 index 0000000..96b8d25 --- /dev/null +++ b/tb/qumcu/isa/case/Sll_test/main.s @@ -0,0 +1,7 @@ +addi x1, x0,1 +addi x2, x0,1 +addi x4, x0, 15 +loop: +sll x1,x1,x2 +bne x1,x0,loop + diff --git a/tb/qumcu/isa/case/Sll_test/user.sv b/tb/qumcu/isa/case/Sll_test/user.sv new file mode 100644 index 0000000..0b11397 --- /dev/null +++ b/tb/qumcu/isa/case/Sll_test/user.sv @@ -0,0 +1,87 @@ + +wire ram_clk = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CLK; +wire ram_cs = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CEBA; +wire reg_clk = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.clk; +wire reg_en = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_wen; +reg ram_cs_dly1 ; +reg reg_en_dly1 ; +always @(posedge ram_clk) begin + ram_cs_dly1 <= ~ram_cs; + reg_en_dly1 <= reg_en; +end + + +initial begin + #1ns; + //@(posedge ram_cs_dly1 ); + #5ns; + //while(1)begin + #1ns; + REGFILE_CHECK(6'd1,32'h0000_0001); + REGFILE_CHECK(6'd2,32'h0000_0001); + REGFILE_CHECK(6'd4,32'h0000_000f); + for(int i = 1; i < 33; i++) begin + REGFILE_CHECK(6'd1,32'h0000_0001< Error!!!",addr,ram_data, edata); + #1us; + TEST_FAIL; + end + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, ram_data, edata); + end + else begin + $display("* DRAM CS is High => Error!!!"); + TEST_FAIL; + end +endtask + +task REGFILE_CHECK; + input [4:0] addr ; + input [31:0] edata ; + + logic [31:0] reg_data; + @(posedge reg_en ); + @(posedge reg_clk); + if(reg_en)begin + reg_data = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_dat; + if(reg_data !== edata) begin + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,reg_data, edata); + #1us; + //TEST_FAIL; + end + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, reg_data, edata); + end + else begin + $display("* REG WR EN is High => Error!!!"); + //TEST_FAIL; + end + +endtask + +initial begin + #100us; + $display("\n----------------------------------------\n"); + $display("\t Timeout Error !!!!\n"); + TEST_FAIL; +end + diff --git a/tb/qumcu/isa/case/Slli_0x120x1f_test/main.c b/tb/qumcu/isa/case/Slli_0x120x1f_test/main.c new file mode 100644 index 0000000..f92eb3f --- /dev/null +++ b/tb/qumcu/isa/case/Slli_0x120x1f_test/main.c @@ -0,0 +1,20 @@ +//#include + + +//int main(){ +// printf("\t=====================================\n"); +// printf("\t hello world !!! \n"); +// printf("\t=====================================\n"); +//} + +void main(void){ + +unsigned int a,b; + a=5; + b=3; + //c=a+b; + //d=c+b; +} + + + diff --git a/tb/qumcu/isa/case/Slli_0x120x1f_test/main.s b/tb/qumcu/isa/case/Slli_0x120x1f_test/main.s new file mode 100644 index 0000000..f2fd941 --- /dev/null +++ b/tb/qumcu/isa/case/Slli_0x120x1f_test/main.s @@ -0,0 +1,124 @@ +addi x1, x0,1 +loop1: +slli x1,x1,1 +bne x1,x0,loop1 +addi x1, x0,1 +loop2: +slli x1,x1,2 +bne x1,x0,loop2 +addi x1, x0,1 +loop3: +slli x1,x1,3 +bne x1,x0,loop3 +addi x1, x0,1 +loop4: +slli x1,x1,4 +bne x1,x0,loop4 +addi x1, x0,1 +loop5: +slli x1,x1,5 +bne x1,x0,loop5 +addi x1, x0,1 +loop6: +slli x1,x1,6 +bne x1,x0,loop6 +addi x1, x0,1 +loop7: +slli x1,x1,7 +bne x1,x0,loop7 +addi x1, x0,1 +loop8: +slli x1,x1,8 +bne x1,x0,loop8 +addi x1, x0,1 +loop9: +slli x1,x1,9 +bne x1,x0,loop9 +addi x1, x0,1 +loop10: +slli x1,x1,10 +bne x1,x0,loop10 +addi x1, x0,1 +loop11: +slli x1,x1,11 +bne x1,x0,loop11 +addi x1, x0,1 +loop12: +slli x1,x1,12 +bne x1,x0,loop12 +addi x1, x0,1 +loop13: +slli x1,x1,13 +bne x1,x0,loop13 +addi x1, x0,1 +loop14: +slli x1,x1,14 +bne x1,x0,loop14 +addi x1, x0,1 +loop15: +slli x1,x1,15 +bne x1,x0,loop15 +addi x1, x0,1 +loop16: +slli x1,x1,16 +bne x1,x0,loop16 +addi x1, x0,1 +loop17: +slli x1,x1,17 +bne x1,x0,loop17 +addi x1, x0,1 +loop18: +slli x1,x1,18 +bne x1,x0,loop18 +addi x1, x0,1 +loop19: +slli x1,x1,19 +bne x1,x0,loop19 +addi x1, x0,1 +loop20: +slli x1,x1,20 +bne x1,x0,loop20 +addi x1, x0,1 +loop21: +slli x1,x1,21 +bne x1,x0,loop21 +addi x1, x0,1 +loop22: +slli x1,x1,22 +bne x1,x0,loop22 +addi x1, x0,1 +loop23: +slli x1,x1,23 +bne x1,x0,loop23 +addi x1, x0,1 +loop24: +slli x1,x1,24 +bne x1,x0,loop24 +addi x1, x0,1 +loop25: +slli x1,x1,25 +bne x1,x0,loop25 +addi x1, x0,1 +loop26: +slli x1,x1,26 +bne x1,x0,loop26 +addi x1, x0,1 +loop27: +slli x1,x1,27 +bne x1,x0,loop27 +addi x1, x0,1 +loop28: +slli x1,x1,28 +bne x1,x0,loop28 +addi x1, x0,1 +loop29: +slli x1,x1,29 +bne x1,x0,loop29 +addi x1, x0,1 +loop30: +slli x1,x1,30 +bne x1,x0,loop30 +addi x1, x0,1 +loop31: +slli x1,x1,31 +bne x1,x0,loop31 \ No newline at end of file diff --git a/tb/qumcu/isa/case/Slli_0x120x1f_test/user.sv b/tb/qumcu/isa/case/Slli_0x120x1f_test/user.sv new file mode 100644 index 0000000..f757e2e --- /dev/null +++ b/tb/qumcu/isa/case/Slli_0x120x1f_test/user.sv @@ -0,0 +1,134 @@ + +wire ram_clk = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CLK; +wire ram_cs = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CEBA; +wire reg_clk = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.clk; +wire reg_en = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_wen; +reg ram_cs_dly1 ; +reg reg_en_dly1 ; +always @(posedge ram_clk) begin + ram_cs_dly1 <= ~ram_cs; + reg_en_dly1 <= reg_en; +end + +int q; +initial begin + #1ns; + //@(posedge ram_cs_dly1 ); + #5ns; + //while(1)begin + #1ns; + //REGFILE_CHECK(6'd4,32'h0000_001f); + for(int j = 1; j < 32; j++) begin + $display("* loop[%x]", j); + //REGFILE_CHECK(6'd2,j); + REGFILE_CHECK(6'd1,32'h0000_0001); + if(j == 1) begin + q = 33; + end + else if(j == 2) begin + q = 17; + end + else if(j == 3) begin + q = 12; + end + else if(j == 4) begin + q = 9; + end + else if(j == 5) begin + q = 8; + end + else if(j == 6) begin + q = 7; + end + else if(j == 7) begin + q = 6; + end + else if(j == 8) begin + q = 5; + end + else if(j == 9) begin + q = 5; + end + else if(j == 10) begin + q = 5; + end + else if(j == 11) begin + q = 4; + end + else if(j == 12) begin + q = 4; + end + else if(j == 13) begin + q = 4; + end + else if(j == 15) begin + q = 4; + end + else if(j >= 16) begin + q = 3; + end + for(int i = 1; i < q; i++) begin + REGFILE_CHECK(6'd1,32'h0000_0001< Error!!!",addr,ram_data, edata); + #1us; + TEST_FAIL; + end + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, ram_data, edata); + end + else begin + $display("* DRAM CS is High => Error!!!"); + TEST_FAIL; + end +endtask + +task REGFILE_CHECK; + input [4:0] addr ; + input [31:0] edata ; + + logic [31:0] reg_data; + @(posedge reg_en ); + @(posedge reg_clk); + if(reg_en)begin + reg_data = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_dat; + if(reg_data !== edata) begin + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,reg_data, edata); + #1us; + TEST_FAIL; + end + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, reg_data, edata); + end + else begin + $display("* REG WR EN is High => Error!!!"); + TEST_FAIL; + end + +endtask + +initial begin + #1000us; + $display("\n----------------------------------------\n"); + $display("\t Timeout Error !!!!\n"); + TEST_FAIL; +end + diff --git a/tb/qumcu/isa/case/Slt_sign_test/main.c b/tb/qumcu/isa/case/Slt_sign_test/main.c new file mode 100644 index 0000000..f92eb3f --- /dev/null +++ b/tb/qumcu/isa/case/Slt_sign_test/main.c @@ -0,0 +1,20 @@ +//#include + + +//int main(){ +// printf("\t=====================================\n"); +// printf("\t hello world !!! \n"); +// printf("\t=====================================\n"); +//} + +void main(void){ + +unsigned int a,b; + a=5; + b=3; + //c=a+b; + //d=c+b; +} + + + diff --git a/tb/qumcu/isa/case/Slt_sign_test/main.s b/tb/qumcu/isa/case/Slt_sign_test/main.s new file mode 100644 index 0000000..424be16 --- /dev/null +++ b/tb/qumcu/isa/case/Slt_sign_test/main.s @@ -0,0 +1,7 @@ +addi x1, x0,-100 +addi x2, x0,-50 +loop: +slt x4,x1,x2 +addi x1, x1,1 +bne x1,x0,loop + diff --git a/tb/qumcu/isa/case/Slt_sign_test/user.sv b/tb/qumcu/isa/case/Slt_sign_test/user.sv new file mode 100644 index 0000000..5fba75e --- /dev/null +++ b/tb/qumcu/isa/case/Slt_sign_test/user.sv @@ -0,0 +1,94 @@ + +wire ram_clk = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CLK; +wire ram_cs = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CEBA; +wire reg_clk = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.clk; +wire reg_en = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_wen; +reg ram_cs_dly1 ; +reg reg_en_dly1 ; +always @(posedge ram_clk) begin + ram_cs_dly1 <= ~ram_cs; + reg_en_dly1 <= reg_en; +end + + +initial begin + #1ns; + //@(posedge ram_cs_dly1 ); + #5ns; + //while(1)begin + #1ns; + REGFILE_CHECK(6'd1,32'hffff_ff9c); + REGFILE_CHECK(6'd2,32'hffff_ffce); + + for(int i = -99; i < 0; i++) begin + + if(i < -49) begin + REGFILE_CHECK(6'd4,32'h0000_0001); + end + else begin + REGFILE_CHECK(6'd4,32'h0000_0000); + end + REGFILE_CHECK(6'd1,i); + end + + //@(posedge reg_en_dly1 ); + + #10us; + TEST_PASS; +end + +task DRAM_DATA_CHECK; + input [9:0] addr ; + input [31:0] edata ; + + logic [31:0] ram_data; + + @(posedge ram_cs_dly1 ); + @(posedge ram_clk ); + //$monitor($time, " Simulation time: %t", $time); + if(ram_cs_dly1) begin + ram_data = `TB_DRAM.mem[addr]; + //$display("* RAM_DATA[%x]: %x | EXP_DATA: %x ",addr,ram_data, edata); + if(ram_data !== edata) begin + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,ram_data, edata); + #1us; + TEST_FAIL; + end + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, ram_data, edata); + end + else begin + $display("* DRAM CS is High => Error!!!"); + TEST_FAIL; + end +endtask + +task REGFILE_CHECK; + input [4:0] addr ; + input [31:0] edata ; + + logic [31:0] reg_data; + @(posedge reg_en ); + @(posedge reg_clk); + if(reg_en)begin + reg_data = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_dat; + if(reg_data !== edata) begin + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,reg_data, edata); + #1us; + TEST_FAIL; + end + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, reg_data, edata); + end + else begin + $display("* REG WR EN is High => Error!!!"); + TEST_FAIL; + end + +endtask + +initial begin + #100us; + $display("\n----------------------------------------\n"); + $display("\t Timeout Error !!!!\n"); + TEST_FAIL; +end + diff --git a/tb/qumcu/isa/case/Slt_test/main.c b/tb/qumcu/isa/case/Slt_test/main.c new file mode 100644 index 0000000..f92eb3f --- /dev/null +++ b/tb/qumcu/isa/case/Slt_test/main.c @@ -0,0 +1,20 @@ +//#include + + +//int main(){ +// printf("\t=====================================\n"); +// printf("\t hello world !!! \n"); +// printf("\t=====================================\n"); +//} + +void main(void){ + +unsigned int a,b; + a=5; + b=3; + //c=a+b; + //d=c+b; +} + + + diff --git a/tb/qumcu/isa/case/Slt_test/main.s b/tb/qumcu/isa/case/Slt_test/main.s new file mode 100644 index 0000000..91b8e3d --- /dev/null +++ b/tb/qumcu/isa/case/Slt_test/main.s @@ -0,0 +1,7 @@ +addi x1, x0,100 +addi x2, x0,50 +loop: +slt x4,x1,x2 +addi x1, x1,-1 +bne x1,x0,loop + diff --git a/tb/qumcu/isa/case/Slt_test/user.sv b/tb/qumcu/isa/case/Slt_test/user.sv new file mode 100644 index 0000000..237d07b --- /dev/null +++ b/tb/qumcu/isa/case/Slt_test/user.sv @@ -0,0 +1,94 @@ + +wire ram_clk = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CLK; +wire ram_cs = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CEBA; +wire reg_clk = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.clk; +wire reg_en = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_wen; +reg ram_cs_dly1 ; +reg reg_en_dly1 ; +always @(posedge ram_clk) begin + ram_cs_dly1 <= ~ram_cs; + reg_en_dly1 <= reg_en; +end + + +initial begin + #1ns; + //@(posedge ram_cs_dly1 ); + #5ns; + //while(1)begin + #1ns; + REGFILE_CHECK(6'd1,32'h0000_0064); + REGFILE_CHECK(6'd2,32'h0000_0032); + + for(int i = 99; i > 0; i--) begin + + if(i < 49) begin + REGFILE_CHECK(6'd4,32'h0000_0001); + end + else begin + REGFILE_CHECK(6'd4,32'h0000_0000); + end + REGFILE_CHECK(6'd1,i); + end + + //@(posedge reg_en_dly1 ); + + #10us; + TEST_PASS; +end + +task DRAM_DATA_CHECK; + input [9:0] addr ; + input [31:0] edata ; + + logic [31:0] ram_data; + + @(posedge ram_cs_dly1 ); + @(posedge ram_clk ); + //$monitor($time, " Simulation time: %t", $time); + if(ram_cs_dly1) begin + ram_data = `TB_DRAM.mem[addr]; + //$display("* RAM_DATA[%x]: %x | EXP_DATA: %x ",addr,ram_data, edata); + if(ram_data !== edata) begin + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,ram_data, edata); + #1us; + TEST_FAIL; + end + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, ram_data, edata); + end + else begin + $display("* DRAM CS is High => Error!!!"); + TEST_FAIL; + end +endtask + +task REGFILE_CHECK; + input [4:0] addr ; + input [31:0] edata ; + + logic [31:0] reg_data; + @(posedge reg_en ); + @(posedge reg_clk); + if(reg_en)begin + reg_data = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_dat; + if(reg_data !== edata) begin + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,reg_data, edata); + #1us; + TEST_FAIL; + end + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, reg_data, edata); + end + else begin + $display("* REG WR EN is High => Error!!!"); + TEST_FAIL; + end + +endtask + +initial begin + #100us; + $display("\n----------------------------------------\n"); + $display("\t Timeout Error !!!!\n"); + TEST_FAIL; +end + diff --git a/tb/qumcu/isa/case/Slti_sign_test/main.c b/tb/qumcu/isa/case/Slti_sign_test/main.c new file mode 100644 index 0000000..f92eb3f --- /dev/null +++ b/tb/qumcu/isa/case/Slti_sign_test/main.c @@ -0,0 +1,20 @@ +//#include + + +//int main(){ +// printf("\t=====================================\n"); +// printf("\t hello world !!! \n"); +// printf("\t=====================================\n"); +//} + +void main(void){ + +unsigned int a,b; + a=5; + b=3; + //c=a+b; + //d=c+b; +} + + + diff --git a/tb/qumcu/isa/case/Slti_sign_test/main.s b/tb/qumcu/isa/case/Slti_sign_test/main.s new file mode 100644 index 0000000..4014743 --- /dev/null +++ b/tb/qumcu/isa/case/Slti_sign_test/main.s @@ -0,0 +1,7 @@ +addi x1, x0,-100 +addi x2, x0,-50 +loop: +slt x4,x1,-50 +addi x1, x1,1 +bne x1,x0,loop + diff --git a/tb/qumcu/isa/case/Slti_sign_test/user.sv b/tb/qumcu/isa/case/Slti_sign_test/user.sv new file mode 100644 index 0000000..5fba75e --- /dev/null +++ b/tb/qumcu/isa/case/Slti_sign_test/user.sv @@ -0,0 +1,94 @@ + +wire ram_clk = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CLK; +wire ram_cs = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CEBA; +wire reg_clk = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.clk; +wire reg_en = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_wen; +reg ram_cs_dly1 ; +reg reg_en_dly1 ; +always @(posedge ram_clk) begin + ram_cs_dly1 <= ~ram_cs; + reg_en_dly1 <= reg_en; +end + + +initial begin + #1ns; + //@(posedge ram_cs_dly1 ); + #5ns; + //while(1)begin + #1ns; + REGFILE_CHECK(6'd1,32'hffff_ff9c); + REGFILE_CHECK(6'd2,32'hffff_ffce); + + for(int i = -99; i < 0; i++) begin + + if(i < -49) begin + REGFILE_CHECK(6'd4,32'h0000_0001); + end + else begin + REGFILE_CHECK(6'd4,32'h0000_0000); + end + REGFILE_CHECK(6'd1,i); + end + + //@(posedge reg_en_dly1 ); + + #10us; + TEST_PASS; +end + +task DRAM_DATA_CHECK; + input [9:0] addr ; + input [31:0] edata ; + + logic [31:0] ram_data; + + @(posedge ram_cs_dly1 ); + @(posedge ram_clk ); + //$monitor($time, " Simulation time: %t", $time); + if(ram_cs_dly1) begin + ram_data = `TB_DRAM.mem[addr]; + //$display("* RAM_DATA[%x]: %x | EXP_DATA: %x ",addr,ram_data, edata); + if(ram_data !== edata) begin + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,ram_data, edata); + #1us; + TEST_FAIL; + end + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, ram_data, edata); + end + else begin + $display("* DRAM CS is High => Error!!!"); + TEST_FAIL; + end +endtask + +task REGFILE_CHECK; + input [4:0] addr ; + input [31:0] edata ; + + logic [31:0] reg_data; + @(posedge reg_en ); + @(posedge reg_clk); + if(reg_en)begin + reg_data = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_dat; + if(reg_data !== edata) begin + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,reg_data, edata); + #1us; + TEST_FAIL; + end + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, reg_data, edata); + end + else begin + $display("* REG WR EN is High => Error!!!"); + TEST_FAIL; + end + +endtask + +initial begin + #100us; + $display("\n----------------------------------------\n"); + $display("\t Timeout Error !!!!\n"); + TEST_FAIL; +end + diff --git a/tb/qumcu/isa/case/Slti_test/main.c b/tb/qumcu/isa/case/Slti_test/main.c new file mode 100644 index 0000000..f92eb3f --- /dev/null +++ b/tb/qumcu/isa/case/Slti_test/main.c @@ -0,0 +1,20 @@ +//#include + + +//int main(){ +// printf("\t=====================================\n"); +// printf("\t hello world !!! \n"); +// printf("\t=====================================\n"); +//} + +void main(void){ + +unsigned int a,b; + a=5; + b=3; + //c=a+b; + //d=c+b; +} + + + diff --git a/tb/qumcu/isa/case/Slti_test/main.s b/tb/qumcu/isa/case/Slti_test/main.s new file mode 100644 index 0000000..2193c94 --- /dev/null +++ b/tb/qumcu/isa/case/Slti_test/main.s @@ -0,0 +1,7 @@ +addi x1, x0,100 +addi x2, x0,50 +loop: +slti x4,x1,50 +addi x1, x1,-1 +bne x1,x0,loop + diff --git a/tb/qumcu/isa/case/Slti_test/user.sv b/tb/qumcu/isa/case/Slti_test/user.sv new file mode 100644 index 0000000..237d07b --- /dev/null +++ b/tb/qumcu/isa/case/Slti_test/user.sv @@ -0,0 +1,94 @@ + +wire ram_clk = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CLK; +wire ram_cs = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CEBA; +wire reg_clk = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.clk; +wire reg_en = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_wen; +reg ram_cs_dly1 ; +reg reg_en_dly1 ; +always @(posedge ram_clk) begin + ram_cs_dly1 <= ~ram_cs; + reg_en_dly1 <= reg_en; +end + + +initial begin + #1ns; + //@(posedge ram_cs_dly1 ); + #5ns; + //while(1)begin + #1ns; + REGFILE_CHECK(6'd1,32'h0000_0064); + REGFILE_CHECK(6'd2,32'h0000_0032); + + for(int i = 99; i > 0; i--) begin + + if(i < 49) begin + REGFILE_CHECK(6'd4,32'h0000_0001); + end + else begin + REGFILE_CHECK(6'd4,32'h0000_0000); + end + REGFILE_CHECK(6'd1,i); + end + + //@(posedge reg_en_dly1 ); + + #10us; + TEST_PASS; +end + +task DRAM_DATA_CHECK; + input [9:0] addr ; + input [31:0] edata ; + + logic [31:0] ram_data; + + @(posedge ram_cs_dly1 ); + @(posedge ram_clk ); + //$monitor($time, " Simulation time: %t", $time); + if(ram_cs_dly1) begin + ram_data = `TB_DRAM.mem[addr]; + //$display("* RAM_DATA[%x]: %x | EXP_DATA: %x ",addr,ram_data, edata); + if(ram_data !== edata) begin + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,ram_data, edata); + #1us; + TEST_FAIL; + end + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, ram_data, edata); + end + else begin + $display("* DRAM CS is High => Error!!!"); + TEST_FAIL; + end +endtask + +task REGFILE_CHECK; + input [4:0] addr ; + input [31:0] edata ; + + logic [31:0] reg_data; + @(posedge reg_en ); + @(posedge reg_clk); + if(reg_en)begin + reg_data = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_dat; + if(reg_data !== edata) begin + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,reg_data, edata); + #1us; + TEST_FAIL; + end + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, reg_data, edata); + end + else begin + $display("* REG WR EN is High => Error!!!"); + TEST_FAIL; + end + +endtask + +initial begin + #100us; + $display("\n----------------------------------------\n"); + $display("\t Timeout Error !!!!\n"); + TEST_FAIL; +end + diff --git a/tb/qumcu/isa/case/Sltiu_test/main.c b/tb/qumcu/isa/case/Sltiu_test/main.c new file mode 100644 index 0000000..f92eb3f --- /dev/null +++ b/tb/qumcu/isa/case/Sltiu_test/main.c @@ -0,0 +1,20 @@ +//#include + + +//int main(){ +// printf("\t=====================================\n"); +// printf("\t hello world !!! \n"); +// printf("\t=====================================\n"); +//} + +void main(void){ + +unsigned int a,b; + a=5; + b=3; + //c=a+b; + //d=c+b; +} + + + diff --git a/tb/qumcu/isa/case/Sltiu_test/main.s b/tb/qumcu/isa/case/Sltiu_test/main.s new file mode 100644 index 0000000..fe577f5 --- /dev/null +++ b/tb/qumcu/isa/case/Sltiu_test/main.s @@ -0,0 +1,7 @@ +addi x1, x0,100 +addi x2, x0,50 +loop: +sltiu x4,x1,50 +addi x1, x1,-1 +bne x1,x0,loop + diff --git a/tb/qumcu/isa/case/Sltiu_test/user.sv b/tb/qumcu/isa/case/Sltiu_test/user.sv new file mode 100644 index 0000000..237d07b --- /dev/null +++ b/tb/qumcu/isa/case/Sltiu_test/user.sv @@ -0,0 +1,94 @@ + +wire ram_clk = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CLK; +wire ram_cs = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CEBA; +wire reg_clk = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.clk; +wire reg_en = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_wen; +reg ram_cs_dly1 ; +reg reg_en_dly1 ; +always @(posedge ram_clk) begin + ram_cs_dly1 <= ~ram_cs; + reg_en_dly1 <= reg_en; +end + + +initial begin + #1ns; + //@(posedge ram_cs_dly1 ); + #5ns; + //while(1)begin + #1ns; + REGFILE_CHECK(6'd1,32'h0000_0064); + REGFILE_CHECK(6'd2,32'h0000_0032); + + for(int i = 99; i > 0; i--) begin + + if(i < 49) begin + REGFILE_CHECK(6'd4,32'h0000_0001); + end + else begin + REGFILE_CHECK(6'd4,32'h0000_0000); + end + REGFILE_CHECK(6'd1,i); + end + + //@(posedge reg_en_dly1 ); + + #10us; + TEST_PASS; +end + +task DRAM_DATA_CHECK; + input [9:0] addr ; + input [31:0] edata ; + + logic [31:0] ram_data; + + @(posedge ram_cs_dly1 ); + @(posedge ram_clk ); + //$monitor($time, " Simulation time: %t", $time); + if(ram_cs_dly1) begin + ram_data = `TB_DRAM.mem[addr]; + //$display("* RAM_DATA[%x]: %x | EXP_DATA: %x ",addr,ram_data, edata); + if(ram_data !== edata) begin + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,ram_data, edata); + #1us; + TEST_FAIL; + end + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, ram_data, edata); + end + else begin + $display("* DRAM CS is High => Error!!!"); + TEST_FAIL; + end +endtask + +task REGFILE_CHECK; + input [4:0] addr ; + input [31:0] edata ; + + logic [31:0] reg_data; + @(posedge reg_en ); + @(posedge reg_clk); + if(reg_en)begin + reg_data = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_dat; + if(reg_data !== edata) begin + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,reg_data, edata); + #1us; + TEST_FAIL; + end + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, reg_data, edata); + end + else begin + $display("* REG WR EN is High => Error!!!"); + TEST_FAIL; + end + +endtask + +initial begin + #100us; + $display("\n----------------------------------------\n"); + $display("\t Timeout Error !!!!\n"); + TEST_FAIL; +end + diff --git a/tb/qumcu/isa/case/Sltu_test/main.c b/tb/qumcu/isa/case/Sltu_test/main.c new file mode 100644 index 0000000..f92eb3f --- /dev/null +++ b/tb/qumcu/isa/case/Sltu_test/main.c @@ -0,0 +1,20 @@ +//#include + + +//int main(){ +// printf("\t=====================================\n"); +// printf("\t hello world !!! \n"); +// printf("\t=====================================\n"); +//} + +void main(void){ + +unsigned int a,b; + a=5; + b=3; + //c=a+b; + //d=c+b; +} + + + diff --git a/tb/qumcu/isa/case/Sltu_test/main.s b/tb/qumcu/isa/case/Sltu_test/main.s new file mode 100644 index 0000000..fa8a27f --- /dev/null +++ b/tb/qumcu/isa/case/Sltu_test/main.s @@ -0,0 +1,7 @@ +addi x1, x0,100 +addi x2, x0,50 +loop: +sltu x4,x1,x2 +addi x1, x1,-1 +bne x1,x0,loop + diff --git a/tb/qumcu/isa/case/Sltu_test/user.sv b/tb/qumcu/isa/case/Sltu_test/user.sv new file mode 100644 index 0000000..237d07b --- /dev/null +++ b/tb/qumcu/isa/case/Sltu_test/user.sv @@ -0,0 +1,94 @@ + +wire ram_clk = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CLK; +wire ram_cs = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CEBA; +wire reg_clk = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.clk; +wire reg_en = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_wen; +reg ram_cs_dly1 ; +reg reg_en_dly1 ; +always @(posedge ram_clk) begin + ram_cs_dly1 <= ~ram_cs; + reg_en_dly1 <= reg_en; +end + + +initial begin + #1ns; + //@(posedge ram_cs_dly1 ); + #5ns; + //while(1)begin + #1ns; + REGFILE_CHECK(6'd1,32'h0000_0064); + REGFILE_CHECK(6'd2,32'h0000_0032); + + for(int i = 99; i > 0; i--) begin + + if(i < 49) begin + REGFILE_CHECK(6'd4,32'h0000_0001); + end + else begin + REGFILE_CHECK(6'd4,32'h0000_0000); + end + REGFILE_CHECK(6'd1,i); + end + + //@(posedge reg_en_dly1 ); + + #10us; + TEST_PASS; +end + +task DRAM_DATA_CHECK; + input [9:0] addr ; + input [31:0] edata ; + + logic [31:0] ram_data; + + @(posedge ram_cs_dly1 ); + @(posedge ram_clk ); + //$monitor($time, " Simulation time: %t", $time); + if(ram_cs_dly1) begin + ram_data = `TB_DRAM.mem[addr]; + //$display("* RAM_DATA[%x]: %x | EXP_DATA: %x ",addr,ram_data, edata); + if(ram_data !== edata) begin + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,ram_data, edata); + #1us; + TEST_FAIL; + end + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, ram_data, edata); + end + else begin + $display("* DRAM CS is High => Error!!!"); + TEST_FAIL; + end +endtask + +task REGFILE_CHECK; + input [4:0] addr ; + input [31:0] edata ; + + logic [31:0] reg_data; + @(posedge reg_en ); + @(posedge reg_clk); + if(reg_en)begin + reg_data = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_dat; + if(reg_data !== edata) begin + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,reg_data, edata); + #1us; + TEST_FAIL; + end + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, reg_data, edata); + end + else begin + $display("* REG WR EN is High => Error!!!"); + TEST_FAIL; + end + +endtask + +initial begin + #100us; + $display("\n----------------------------------------\n"); + $display("\t Timeout Error !!!!\n"); + TEST_FAIL; +end + diff --git a/tb/qumcu/isa/case/Sra_signed_test/main.c b/tb/qumcu/isa/case/Sra_signed_test/main.c new file mode 100644 index 0000000..f92eb3f --- /dev/null +++ b/tb/qumcu/isa/case/Sra_signed_test/main.c @@ -0,0 +1,20 @@ +//#include + + +//int main(){ +// printf("\t=====================================\n"); +// printf("\t hello world !!! \n"); +// printf("\t=====================================\n"); +//} + +void main(void){ + +unsigned int a,b; + a=5; + b=3; + //c=a+b; + //d=c+b; +} + + + diff --git a/tb/qumcu/isa/case/Sra_signed_test/main.s b/tb/qumcu/isa/case/Sra_signed_test/main.s new file mode 100644 index 0000000..6b4e3ce --- /dev/null +++ b/tb/qumcu/isa/case/Sra_signed_test/main.s @@ -0,0 +1,9 @@ +addi x5,x0,-1 +addi x4, x0, 31 +main_loop: +addi x2, x2,1 +lui x1, 0x80000 +loop1: +sra x1,x1,x2 +bne x1,x5,loop1 +bne x2,x4,main_loop \ No newline at end of file diff --git a/tb/qumcu/isa/case/Sra_signed_test/user.sv b/tb/qumcu/isa/case/Sra_signed_test/user.sv new file mode 100644 index 0000000..0b8e086 --- /dev/null +++ b/tb/qumcu/isa/case/Sra_signed_test/user.sv @@ -0,0 +1,140 @@ + +wire ram_clk = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CLK; +wire ram_cs = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CEBA; +wire reg_clk = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.clk; +wire reg_en = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_wen; +reg ram_cs_dly1 ; +reg reg_en_dly1 ; +always @(posedge ram_clk) begin + ram_cs_dly1 <= ~ram_cs; + reg_en_dly1 <= reg_en; +end + +reg signed [31:0] data; +int q; +initial begin + #1ns; + //@(posedge ram_cs_dly1 ); + #5ns; + //while(1)begin + #1ns; + REGFILE_CHECK(6'd4,32'hffff_ffff); + REGFILE_CHECK(6'd4,32'h0000_001f); + for(int j = 1; j < 32; j++) begin + $display("* loop[%x]", j); + data = 32'h8000_0000; + REGFILE_CHECK(6'd2,j); + REGFILE_CHECK(6'd1,32'h8000_0000); + if(j == 1) begin + q = 32; + end + else if(j == 2) begin + q = 17; + end + else if(j == 3) begin + q = 12; + end + else if(j == 4) begin + q = 9; + end + else if(j == 5) begin + q = 8; + end + else if(j == 6) begin + q = 7; + end + else if(j == 7) begin + q = 6; + end + else if(j == 8) begin + q = 5; + end + else if(j == 9) begin + q = 5; + end + else if(j == 10) begin + q = 5; + end + else if(j == 11) begin + q = 4; + end + else if(j == 12) begin + q = 4; + end + else if(j == 13) begin + q = 4; + end + else if(j == 15) begin + q = 4; + end + else if(j >= 16 & j < 31) begin + q = 3; + end + else if(j == 31) begin + q = 2; + end + for(int i = 1; i < q; i++) begin + REGFILE_CHECK(6'd1,data>>>i*j); + end + end + //@(posedge reg_en_dly1 ); + + #10us; + TEST_PASS; +end + +task DRAM_DATA_CHECK; + input [9:0] addr ; + input [31:0] edata ; + + logic [31:0] ram_data; + + @(posedge ram_cs_dly1 ); + @(posedge ram_clk ); + //$monitor($time, " Simulation time: %t", $time); + if(ram_cs_dly1) begin + ram_data = `TB_DRAM.mem[addr]; + //$display("* RAM_DATA[%x]: %x | EXP_DATA: %x ",addr,ram_data, edata); + if(ram_data !== edata) begin + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,ram_data, edata); + #1us; + TEST_FAIL; + end + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, ram_data, edata); + end + else begin + $display("* DRAM CS is High => Error!!!"); + TEST_FAIL; + end +endtask + +task REGFILE_CHECK; + input [4:0] addr ; + input [31:0] edata ; + + logic [31:0] reg_data; + @(posedge reg_en ); + @(posedge reg_clk); + if(reg_en)begin + reg_data = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_dat; + if(reg_data !== edata) begin + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,reg_data, edata); + #1us; + //TEST_FAIL; + end + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, reg_data, edata); + end + else begin + $display("* REG WR EN is High => Error!!!"); + //TEST_FAIL; + end + +endtask + +initial begin + #1000us; + $display("\n----------------------------------------\n"); + $display("\t Timeout Error !!!!\n"); + TEST_FAIL; +end + diff --git a/tb/qumcu/isa/case/Srai_0x120x1f_test/main.c b/tb/qumcu/isa/case/Srai_0x120x1f_test/main.c new file mode 100644 index 0000000..f92eb3f --- /dev/null +++ b/tb/qumcu/isa/case/Srai_0x120x1f_test/main.c @@ -0,0 +1,20 @@ +//#include + + +//int main(){ +// printf("\t=====================================\n"); +// printf("\t hello world !!! \n"); +// printf("\t=====================================\n"); +//} + +void main(void){ + +unsigned int a,b; + a=5; + b=3; + //c=a+b; + //d=c+b; +} + + + diff --git a/tb/qumcu/isa/case/Srai_0x120x1f_test/main.s b/tb/qumcu/isa/case/Srai_0x120x1f_test/main.s new file mode 100644 index 0000000..8f796b1 --- /dev/null +++ b/tb/qumcu/isa/case/Srai_0x120x1f_test/main.s @@ -0,0 +1,127 @@ + +addi x2,x0,-1 +lui x1, 0x80000 +loop1: +srai x1,x1,1 +bne x1,x2,loop1 +lui x1, 0x80000 +loop2: +srai x1,x1,2 +bne x1,x2,loop2 +lui x1, 0x80000 +loop3: +srai x1,x1,3 +bne x1,x2,loop3 +lui x1, 0x80000 +loop4: +srai x1,x1,4 +bne x1,x2,loop4 +lui x1, 0x80000 +loop5: +srai x1,x1,5 +bne x1,x2,loop5 +lui x1, 0x80000 +loop6: +srai x1,x1,6 +bne x1,x2,loop6 +lui x1, 0x80000 +loop7: +srai x1,x1,7 +bne x1,x2,loop7 +lui x1, 0x80000 +loop8: +srai x1,x1,8 +bne x1,x2,loop8 +lui x1, 0x80000 +loop9: +srai x1,x1,9 +bne x1,x2,loop9 +lui x1, 0x80000 +loop10: +srai x1,x1,10 +bne x1,x2,loop10 +lui x1, 0x80000 +loop11: +srai x1,x1,11 +bne x1,x2,loop11 +lui x1, 0x80000 +loop12: +srai x1,x1,12 +bne x1,x2,loop12 +lui x1, 0x80000 +loop13: +srai x1,x1,13 +bne x1,x2,loop13 +lui x1, 0x80000 +loop14: +srai x1,x1,14 +bne x1,x2,loop14 +lui x1, 0x80000 +loop15: +srai x1,x1,15 +bne x1,x2,loop15 +lui x1, 0x80000 +loop16: +srai x1,x1,16 +bne x1,x2,loop16 +lui x1, 0x80000 +loop17: +srai x1,x1,17 +bne x1,x2,loop17 +lui x1, 0x80000 +loop18: +srai x1,x1,18 +bne x1,x2,loop18 +lui x1, 0x80000 +loop19: +srai x1,x1,19 +bne x1,x2,loop19 +lui x1, 0x80000 +loop20: +srai x1,x1,20 +bne x1,x2,loop20 +lui x1, 0x80000 +loop21: +srai x1,x1,21 +bne x1,x2,loop21 +lui x1, 0x80000 +loop22: +srai x1,x1,22 +bne x1,x2,loop22 +lui x1, 0x80000 +loop23: +srai x1,x1,23 +bne x1,x2,loop23 +lui x1, 0x80000 +loop24: +srai x1,x1,24 +bne x1,x2,loop24 +lui x1, 0x80000 +loop25: +srai x1,x1,25 +bne x1,x2,loop25 +lui x1, 0x80000 +loop26: +srai x1,x1,26 +bne x1,x2,loop26 +lui x1, 0x80000 +loop27: +srai x1,x1,27 +bne x1,x2,loop27 +lui x1, 0x80000 +loop28: +srai x1,x1,28 +bne x1,x2,loop28 +lui x1, 0x80000 +loop29: +srai x1,x1,29 +bne x1,x2,loop29 +lui x1, 0x80000 +loop30: +srai x1,x1,30 +bne x1,x2,loop30 +lui x1, 0x80000 +loop31: +srai x1,x1,31 +bne x1,x2,loop31 +addi x3,x0,-1 \ No newline at end of file diff --git a/tb/qumcu/isa/case/Srai_0x120x1f_test/user.sv b/tb/qumcu/isa/case/Srai_0x120x1f_test/user.sv new file mode 100644 index 0000000..167dc0b --- /dev/null +++ b/tb/qumcu/isa/case/Srai_0x120x1f_test/user.sv @@ -0,0 +1,140 @@ + +wire ram_clk = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CLK; +wire ram_cs = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CEBA; +wire reg_clk = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.clk; +wire reg_en = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_wen; +reg ram_cs_dly1 ; +reg reg_en_dly1 ; +always @(posedge ram_clk) begin + ram_cs_dly1 <= ~ram_cs; + reg_en_dly1 <= reg_en; +end +reg signed [31:0] data; +int q; +initial begin + #1ns; + //@(posedge ram_cs_dly1 ); + #5ns; + //while(1)begin + #1ns; + REGFILE_CHECK(6'd2,32'hffff_ffff); + for(int j = 1; j < 32; j++) begin + $display("* loop[%x]", j); + //REGFILE_CHECK(6'd2,j); + data = 32'h8000_0000; + REGFILE_CHECK(6'd1,32'h8000_0000); + if(j == 1) begin + q = 32; + end + else if(j == 2) begin + q = 17; + end + else if(j == 3) begin + q = 12; + end + else if(j == 4) begin + q = 9; + end + else if(j == 5) begin + q = 8; + end + else if(j == 6) begin + q = 7; + end + else if(j == 7) begin + q = 6; + end + else if(j == 8) begin + q = 5; + end + else if(j == 9) begin + q = 5; + end + else if(j == 10) begin + q = 5; + end + else if(j == 11) begin + q = 4; + end + else if(j == 12) begin + q = 4; + end + else if(j == 13) begin + q = 4; + end + else if(j == 15) begin + q = 4; + end + else if(j >= 16 & j < 31) begin + q = 3; + end + else if(j == 31) begin + q = 2; + end + + for(int i = 1; i < q; i++) begin + REGFILE_CHECK(6'd1,data>>>i*j); + end + end + REGFILE_CHECK(6'd3,32'hffff_ffff); + //@(posedge reg_en_dly1 ); + + #10us; + TEST_PASS; +end + +task DRAM_DATA_CHECK; + input [9:0] addr ; + input [31:0] edata ; + + logic [31:0] ram_data; + + @(posedge ram_cs_dly1 ); + @(posedge ram_clk ); + //$monitor($time, " Simulation time: %t", $time); + if(ram_cs_dly1) begin + ram_data = `TB_DRAM.mem[addr]; + //$display("* RAM_DATA[%x]: %x | EXP_DATA: %x ",addr,ram_data, edata); + if(ram_data !== edata) begin + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,ram_data, edata); + #1us; + TEST_FAIL; + end + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, ram_data, edata); + end + else begin + $display("* DRAM CS is High => Error!!!"); + TEST_FAIL; + end +endtask + +task REGFILE_CHECK; + input [4:0] addr ; + input [31:0] edata ; + + logic [31:0] reg_data; + @(posedge reg_en ); + @(posedge reg_clk); + if(reg_en)begin + reg_data = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_dat; + if(reg_data !== edata) begin + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,reg_data, edata); + #1us; + TEST_FAIL; + end + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, reg_data, edata); + end + else begin + $display("* REG WR EN is High => Error!!!"); + TEST_FAIL; + end + +endtask + +initial begin + #10000us; + $display("\n----------------------------------------\n"); + $display("\t Timeout Error !!!!\n"); + TEST_FAIL; +end + diff --git a/tb/qumcu/isa/case/Srai_unsign_test/main.c b/tb/qumcu/isa/case/Srai_unsign_test/main.c new file mode 100644 index 0000000..f92eb3f --- /dev/null +++ b/tb/qumcu/isa/case/Srai_unsign_test/main.c @@ -0,0 +1,20 @@ +//#include + + +//int main(){ +// printf("\t=====================================\n"); +// printf("\t hello world !!! \n"); +// printf("\t=====================================\n"); +//} + +void main(void){ + +unsigned int a,b; + a=5; + b=3; + //c=a+b; + //d=c+b; +} + + + diff --git a/tb/qumcu/isa/case/Srai_unsign_test/main.s b/tb/qumcu/isa/case/Srai_unsign_test/main.s new file mode 100644 index 0000000..179f9de --- /dev/null +++ b/tb/qumcu/isa/case/Srai_unsign_test/main.s @@ -0,0 +1,127 @@ + +addi x2,x0,0 +lui x1, 0x40000 +loop1: +srai x1,x1,1 +bne x1,x2,loop1 +lui x1, 0x40000 +loop2: +srai x1,x1,2 +bne x1,x2,loop2 +lui x1, 0x40000 +loop3: +srai x1,x1,3 +bne x1,x2,loop3 +lui x1, 0x40000 +loop4: +srai x1,x1,4 +bne x1,x2,loop4 +lui x1, 0x40000 +loop5: +srai x1,x1,5 +bne x1,x2,loop5 +lui x1, 0x40000 +loop6: +srai x1,x1,6 +bne x1,x2,loop6 +lui x1, 0x40000 +loop7: +srai x1,x1,7 +bne x1,x2,loop7 +lui x1, 0x40000 +loop8: +srai x1,x1,8 +bne x1,x2,loop8 +lui x1, 0x40000 +loop9: +srai x1,x1,9 +bne x1,x2,loop9 +lui x1, 0x40000 +loop10: +srai x1,x1,10 +bne x1,x2,loop10 +lui x1, 0x40000 +loop11: +srai x1,x1,11 +bne x1,x2,loop11 +lui x1, 0x40000 +loop12: +srai x1,x1,12 +bne x1,x2,loop12 +lui x1, 0x40000 +loop13: +srai x1,x1,13 +bne x1,x2,loop13 +lui x1, 0x40000 +loop14: +srai x1,x1,14 +bne x1,x2,loop14 +lui x1, 0x40000 +loop15: +srai x1,x1,15 +bne x1,x2,loop15 +lui x1, 0x40000 +loop16: +srai x1,x1,16 +bne x1,x2,loop16 +lui x1, 0x40000 +loop17: +srai x1,x1,17 +bne x1,x2,loop17 +lui x1, 0x40000 +loop18: +srai x1,x1,18 +bne x1,x2,loop18 +lui x1, 0x40000 +loop19: +srai x1,x1,19 +bne x1,x2,loop19 +lui x1, 0x40000 +loop20: +srai x1,x1,20 +bne x1,x2,loop20 +lui x1, 0x40000 +loop21: +srai x1,x1,21 +bne x1,x2,loop21 +lui x1, 0x40000 +loop22: +srai x1,x1,22 +bne x1,x2,loop22 +lui x1, 0x40000 +loop23: +srai x1,x1,23 +bne x1,x2,loop23 +lui x1, 0x40000 +loop24: +srai x1,x1,24 +bne x1,x2,loop24 +lui x1, 0x40000 +loop25: +srai x1,x1,25 +bne x1,x2,loop25 +lui x1, 0x40000 +loop26: +srai x1,x1,26 +bne x1,x2,loop26 +lui x1, 0x40000 +loop27: +srai x1,x1,27 +bne x1,x2,loop27 +lui x1, 0x40000 +loop28: +srai x1,x1,28 +bne x1,x2,loop28 +lui x1, 0x40000 +loop29: +srai x1,x1,29 +bne x1,x2,loop29 +lui x1, 0x40000 +loop30: +srai x1,x1,30 +bne x1,x2,loop30 +lui x1, 0x40000 +loop31: +srai x1,x1,31 +bne x1,x2,loop31 +addi x3,x0,-1 \ No newline at end of file diff --git a/tb/qumcu/isa/case/Srai_unsign_test/user.sv b/tb/qumcu/isa/case/Srai_unsign_test/user.sv new file mode 100644 index 0000000..a73e76d --- /dev/null +++ b/tb/qumcu/isa/case/Srai_unsign_test/user.sv @@ -0,0 +1,140 @@ + +wire ram_clk = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CLK; +wire ram_cs = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CEBA; +wire reg_clk = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.clk; +wire reg_en = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_wen; +reg ram_cs_dly1 ; +reg reg_en_dly1 ; +always @(posedge ram_clk) begin + ram_cs_dly1 <= ~ram_cs; + reg_en_dly1 <= reg_en; +end +reg signed [31:0] data; +int q; +initial begin + #1ns; + //@(posedge ram_cs_dly1 ); + #5ns; + //while(1)begin + #1ns; + REGFILE_CHECK(6'd2,32'h0000_0000); + for(int j = 1; j < 32; j++) begin + $display("* loop[%x]", j); + //REGFILE_CHECK(6'd2,j); + data = 32'h4000_0000; + REGFILE_CHECK(6'd1,32'h4000_0000); + if(j == 1) begin + q = 32; + end + else if(j == 2) begin + q = 17; + end + else if(j == 3) begin + q = 12; + end + else if(j == 4) begin + q = 9; + end + else if(j == 5) begin + q = 8; + end + else if(j == 6) begin + q = 7; + end + else if(j == 7) begin + q = 6; + end + else if(j == 8) begin + q = 5; + end + else if(j == 9) begin + q = 5; + end + else if(j == 10) begin + q = 5; + end + else if(j == 11) begin + q = 4; + end + else if(j == 12) begin + q = 4; + end + else if(j == 13) begin + q = 4; + end + else if(j == 15) begin + q = 4; + end + else if(j >= 16 & j < 31) begin + q = 3; + end + else if(j == 31) begin + q = 2; + end + + for(int i = 1; i < q; i++) begin + REGFILE_CHECK(6'd1,data>>>i*j); + end + end + REGFILE_CHECK(6'd3,32'hffff_ffff); + //@(posedge reg_en_dly1 ); + + #10us; + TEST_PASS; +end + +task DRAM_DATA_CHECK; + input [9:0] addr ; + input [31:0] edata ; + + logic [31:0] ram_data; + + @(posedge ram_cs_dly1 ); + @(posedge ram_clk ); + //$monitor($time, " Simulation time: %t", $time); + if(ram_cs_dly1) begin + ram_data = `TB_DRAM.mem[addr]; + //$display("* RAM_DATA[%x]: %x | EXP_DATA: %x ",addr,ram_data, edata); + if(ram_data !== edata) begin + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,ram_data, edata); + #1us; + TEST_FAIL; + end + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, ram_data, edata); + end + else begin + $display("* DRAM CS is High => Error!!!"); + TEST_FAIL; + end +endtask + +task REGFILE_CHECK; + input [4:0] addr ; + input [31:0] edata ; + + logic [31:0] reg_data; + @(posedge reg_en ); + @(posedge reg_clk); + if(reg_en)begin + reg_data = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_dat; + if(reg_data !== edata) begin + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,reg_data, edata); + #1us; + TEST_FAIL; + end + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, reg_data, edata); + end + else begin + $display("* REG WR EN is High => Error!!!"); + TEST_FAIL; + end + +endtask + +initial begin + #10000us; + $display("\n----------------------------------------\n"); + $display("\t Timeout Error !!!!\n"); + TEST_FAIL; +end + diff --git a/tb/qumcu/isa/case/Srl_0xf20x1f_test/main.c b/tb/qumcu/isa/case/Srl_0xf20x1f_test/main.c new file mode 100644 index 0000000..f92eb3f --- /dev/null +++ b/tb/qumcu/isa/case/Srl_0xf20x1f_test/main.c @@ -0,0 +1,20 @@ +//#include + + +//int main(){ +// printf("\t=====================================\n"); +// printf("\t hello world !!! \n"); +// printf("\t=====================================\n"); +//} + +void main(void){ + +unsigned int a,b; + a=5; + b=3; + //c=a+b; + //d=c+b; +} + + + diff --git a/tb/qumcu/isa/case/Srl_0xf20x1f_test/main.s b/tb/qumcu/isa/case/Srl_0xf20x1f_test/main.s new file mode 100644 index 0000000..7bddb79 --- /dev/null +++ b/tb/qumcu/isa/case/Srl_0xf20x1f_test/main.s @@ -0,0 +1,9 @@ + +addi x4, x0, 31 +main_loop: +addi x2, x2,1 +lui x1, 0x80000 +loop1: +srl x1,x1,x2 +bne x1,x0,loop1 +bne x2,x4,main_loop \ No newline at end of file diff --git a/tb/qumcu/isa/case/Srl_0xf20x1f_test/user.sv b/tb/qumcu/isa/case/Srl_0xf20x1f_test/user.sv new file mode 100644 index 0000000..cdd9f56 --- /dev/null +++ b/tb/qumcu/isa/case/Srl_0xf20x1f_test/user.sv @@ -0,0 +1,134 @@ + +wire ram_clk = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CLK; +wire ram_cs = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CEBA; +wire reg_clk = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.clk; +wire reg_en = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_wen; +reg ram_cs_dly1 ; +reg reg_en_dly1 ; +always @(posedge ram_clk) begin + ram_cs_dly1 <= ~ram_cs; + reg_en_dly1 <= reg_en; +end + +int q; +initial begin + #1ns; + //@(posedge ram_cs_dly1 ); + #5ns; + //while(1)begin + #1ns; + REGFILE_CHECK(6'd4,32'h0000_001f); + for(int j = 1; j < 32; j++) begin + $display("* loop[%x]", j); + REGFILE_CHECK(6'd2,j); + REGFILE_CHECK(6'd1,32'h8000_0000); + if(j == 1) begin + q = 33; + end + else if(j == 2) begin + q = 17; + end + else if(j == 3) begin + q = 12; + end + else if(j == 4) begin + q = 9; + end + else if(j == 5) begin + q = 8; + end + else if(j == 6) begin + q = 7; + end + else if(j == 7) begin + q = 6; + end + else if(j == 8) begin + q = 5; + end + else if(j == 9) begin + q = 5; + end + else if(j == 10) begin + q = 5; + end + else if(j == 11) begin + q = 4; + end + else if(j == 12) begin + q = 4; + end + else if(j == 13) begin + q = 4; + end + else if(j == 15) begin + q = 4; + end + else if(j >= 16) begin + q = 3; + end + for(int i = 1; i < q; i++) begin + REGFILE_CHECK(6'd1,32'h8000_0000>>i*j); + end + end + //@(posedge reg_en_dly1 ); + + #10us; + TEST_PASS; +end + +task DRAM_DATA_CHECK; + input [9:0] addr ; + input [31:0] edata ; + + logic [31:0] ram_data; + + @(posedge ram_cs_dly1 ); + @(posedge ram_clk ); + //$monitor($time, " Simulation time: %t", $time); + if(ram_cs_dly1) begin + ram_data = `TB_DRAM.mem[addr]; + //$display("* RAM_DATA[%x]: %x | EXP_DATA: %x ",addr,ram_data, edata); + if(ram_data !== edata) begin + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,ram_data, edata); + #1us; + TEST_FAIL; + end + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, ram_data, edata); + end + else begin + $display("* DRAM CS is High => Error!!!"); + TEST_FAIL; + end +endtask + +task REGFILE_CHECK; + input [4:0] addr ; + input [31:0] edata ; + + logic [31:0] reg_data; + @(posedge reg_en ); + @(posedge reg_clk); + if(reg_en)begin + reg_data = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_dat; + if(reg_data !== edata) begin + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,reg_data, edata); + #1us; + //TEST_FAIL; + end + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, reg_data, edata); + end + else begin + $display("* REG WR EN is High => Error!!!"); + //TEST_FAIL; + end + +endtask + +initial begin + #1000us; + $display("\n----------------------------------------\n"); + $display("\t Timeout Error !!!!\n"); + TEST_FAIL; +end + diff --git a/tb/qumcu/isa/case/Srli_test/main.c b/tb/qumcu/isa/case/Srli_test/main.c new file mode 100644 index 0000000..f92eb3f --- /dev/null +++ b/tb/qumcu/isa/case/Srli_test/main.c @@ -0,0 +1,20 @@ +//#include + + +//int main(){ +// printf("\t=====================================\n"); +// printf("\t hello world !!! \n"); +// printf("\t=====================================\n"); +//} + +void main(void){ + +unsigned int a,b; + a=5; + b=3; + //c=a+b; + //d=c+b; +} + + + diff --git a/tb/qumcu/isa/case/Srli_test/main.s b/tb/qumcu/isa/case/Srli_test/main.s new file mode 100644 index 0000000..d53c760 --- /dev/null +++ b/tb/qumcu/isa/case/Srli_test/main.s @@ -0,0 +1,127 @@ + +addi x2,x0,0 +lui x1, 0x80000 +loop1: +srli x1,x1,1 +bne x1,x2,loop1 +lui x1, 0x80000 +loop2: +srli x1,x1,2 +bne x1,x2,loop2 +lui x1, 0x80000 +loop3: +srli x1,x1,3 +bne x1,x2,loop3 +lui x1, 0x80000 +loop4: +srli x1,x1,4 +bne x1,x2,loop4 +lui x1, 0x80000 +loop5: +srli x1,x1,5 +bne x1,x2,loop5 +lui x1, 0x80000 +loop6: +srli x1,x1,6 +bne x1,x2,loop6 +lui x1, 0x80000 +loop7: +srli x1,x1,7 +bne x1,x2,loop7 +lui x1, 0x80000 +loop8: +srli x1,x1,8 +bne x1,x2,loop8 +lui x1, 0x80000 +loop9: +srli x1,x1,9 +bne x1,x2,loop9 +lui x1, 0x80000 +loop10: +srli x1,x1,10 +bne x1,x2,loop10 +lui x1, 0x80000 +loop11: +srli x1,x1,11 +bne x1,x2,loop11 +lui x1, 0x80000 +loop12: +srli x1,x1,12 +bne x1,x2,loop12 +lui x1, 0x80000 +loop13: +srli x1,x1,13 +bne x1,x2,loop13 +lui x1, 0x80000 +loop14: +srli x1,x1,14 +bne x1,x2,loop14 +lui x1, 0x80000 +loop15: +srli x1,x1,15 +bne x1,x2,loop15 +lui x1, 0x80000 +loop16: +srli x1,x1,16 +bne x1,x2,loop16 +lui x1, 0x80000 +loop17: +srli x1,x1,17 +bne x1,x2,loop17 +lui x1, 0x80000 +loop18: +srli x1,x1,18 +bne x1,x2,loop18 +lui x1, 0x80000 +loop19: +srli x1,x1,19 +bne x1,x2,loop19 +lui x1, 0x80000 +loop20: +srli x1,x1,20 +bne x1,x2,loop20 +lui x1, 0x80000 +loop21: +srli x1,x1,21 +bne x1,x2,loop21 +lui x1, 0x80000 +loop22: +srli x1,x1,22 +bne x1,x2,loop22 +lui x1, 0x80000 +loop23: +srli x1,x1,23 +bne x1,x2,loop23 +lui x1, 0x80000 +loop24: +srli x1,x1,24 +bne x1,x2,loop24 +lui x1, 0x80000 +loop25: +srli x1,x1,25 +bne x1,x2,loop25 +lui x1, 0x80000 +loop26: +srli x1,x1,26 +bne x1,x2,loop26 +lui x1, 0x80000 +loop27: +srli x1,x1,27 +bne x1,x2,loop27 +lui x1, 0x80000 +loop28: +srli x1,x1,28 +bne x1,x2,loop28 +lui x1, 0x80000 +loop29: +srli x1,x1,29 +bne x1,x2,loop29 +lui x1, 0x80000 +loop30: +srli x1,x1,30 +bne x1,x2,loop30 +lui x1, 0x80000 +loop31: +srli x1,x1,31 +bne x1,x2,loop31 +addi x3,x0,-1 \ No newline at end of file diff --git a/tb/qumcu/isa/case/Srli_test/user.sv b/tb/qumcu/isa/case/Srli_test/user.sv new file mode 100644 index 0000000..475ba5f --- /dev/null +++ b/tb/qumcu/isa/case/Srli_test/user.sv @@ -0,0 +1,140 @@ + +wire ram_clk = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CLK; +wire ram_cs = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CEBA; +wire reg_clk = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.clk; +wire reg_en = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_wen; +reg ram_cs_dly1 ; +reg reg_en_dly1 ; +always @(posedge ram_clk) begin + ram_cs_dly1 <= ~ram_cs; + reg_en_dly1 <= reg_en; +end +reg signed [31:0] data; +int q; +initial begin + #1ns; + //@(posedge ram_cs_dly1 ); + #5ns; + //while(1)begin + #1ns; + REGFILE_CHECK(6'd2,32'h0000_0000); + for(int j = 1; j < 32; j++) begin + $display("* loop[%x]", j); + //REGFILE_CHECK(6'd2,j); + data = 32'h8000_0000; + REGFILE_CHECK(6'd1,32'h8000_0000); + if(j == 1) begin + q = 33; + end + else if(j == 2) begin + q = 17; + end + else if(j == 3) begin + q = 12; + end + else if(j == 4) begin + q = 9; + end + else if(j == 5) begin + q = 8; + end + else if(j == 6) begin + q = 7; + end + else if(j == 7) begin + q = 6; + end + else if(j == 8) begin + q = 5; + end + else if(j == 9) begin + q = 5; + end + else if(j == 10) begin + q = 5; + end + else if(j == 11) begin + q = 4; + end + else if(j == 12) begin + q = 4; + end + else if(j == 13) begin + q = 4; + end + else if(j == 15) begin + q = 4; + end + else if(j >= 16 & j < 31) begin + q = 3; + end + else if(j == 31) begin + q = 3; + end + + for(int i = 1; i < q; i++) begin + REGFILE_CHECK(6'd1,data>>i*j); + end + end + REGFILE_CHECK(6'd3,32'hffff_ffff); + //@(posedge reg_en_dly1 ); + + #10us; + TEST_PASS; +end + +task DRAM_DATA_CHECK; + input [9:0] addr ; + input [31:0] edata ; + + logic [31:0] ram_data; + + @(posedge ram_cs_dly1 ); + @(posedge ram_clk ); + //$monitor($time, " Simulation time: %t", $time); + if(ram_cs_dly1) begin + ram_data = `TB_DRAM.mem[addr]; + //$display("* RAM_DATA[%x]: %x | EXP_DATA: %x ",addr,ram_data, edata); + if(ram_data !== edata) begin + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,ram_data, edata); + #1us; + TEST_FAIL; + end + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, ram_data, edata); + end + else begin + $display("* DRAM CS is High => Error!!!"); + TEST_FAIL; + end +endtask + +task REGFILE_CHECK; + input [4:0] addr ; + input [31:0] edata ; + + logic [31:0] reg_data; + @(posedge reg_en ); + @(posedge reg_clk); + if(reg_en)begin + reg_data = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_dat; + if(reg_data !== edata) begin + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,reg_data, edata); + #1us; + TEST_FAIL; + end + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, reg_data, edata); + end + else begin + $display("* REG WR EN is High => Error!!!"); + TEST_FAIL; + end + +endtask + +initial begin + #10000us; + $display("\n----------------------------------------\n"); + $display("\t Timeout Error !!!!\n"); + TEST_FAIL; +end + diff --git a/tb/qumcu/isa/case/Sub_test/main.c b/tb/qumcu/isa/case/Sub_test/main.c new file mode 100644 index 0000000..f92eb3f --- /dev/null +++ b/tb/qumcu/isa/case/Sub_test/main.c @@ -0,0 +1,20 @@ +//#include + + +//int main(){ +// printf("\t=====================================\n"); +// printf("\t hello world !!! \n"); +// printf("\t=====================================\n"); +//} + +void main(void){ + +unsigned int a,b; + a=5; + b=3; + //c=a+b; + //d=c+b; +} + + + diff --git a/tb/qumcu/isa/case/Sub_test/main.s b/tb/qumcu/isa/case/Sub_test/main.s new file mode 100644 index 0000000..d93a63c --- /dev/null +++ b/tb/qumcu/isa/case/Sub_test/main.s @@ -0,0 +1,10 @@ +lui x3,0x10 +addi x3,x3,0x0 +addi x3,x3,0x0 +addi x3,x3,0 +addi x5,x0,0x1 +loop: +sub x3,x3,x5 +bne x3, x0, loop +exit: + diff --git a/tb/qumcu/isa/case/Sub_test/user.sv b/tb/qumcu/isa/case/Sub_test/user.sv new file mode 100644 index 0000000..8c76283 --- /dev/null +++ b/tb/qumcu/isa/case/Sub_test/user.sv @@ -0,0 +1,89 @@ + +wire ram_clk = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CLK; +wire ram_cs = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CEBA; +wire reg_clk = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.clk; +wire reg_en = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_wen; +reg ram_cs_dly1 ; +reg reg_en_dly1 ; +always @(posedge ram_clk) begin + ram_cs_dly1 <= ~ram_cs; + reg_en_dly1 <= reg_en; +end + +reg [31:0] temp; +initial begin + #1ns; + //@(posedge ram_cs_dly1 ); + #5ns; + //while(1)begin + #1ns; + REGFILE_CHECK(6'd3,32'h70001_0000); + REGFILE_CHECK(6'd3,32'h70001_0000); + REGFILE_CHECK(6'd3,32'h70001_0000); + REGFILE_CHECK(6'd3,32'h70001_0000); + REGFILE_CHECK(6'd5,32'h0000_0001); + for(int i = 65536; i > 0; i--) begin + REGFILE_CHECK(6'd3,i-1); + //$monitor($time, " Simulation time: %t", $time); + end + //@(posedge reg_en_dly1 ); + + #10us; + TEST_PASS; +end + +task DRAM_DATA_CHECK; + input [12:0] addr ; + input [31:0] edata ; + + logic [31:0] ram_data; + + @(posedge ram_cs_dly1 ); + @(posedge ram_clk ); + //$monitor($time, " Simulation time: %t", $time); + if(ram_cs_dly1) begin + ram_data = `TB_DRAM.mem[addr]; + //$display("* RAM_DATA[%x]: %x | EXP_DATA: %x ",addr,ram_data, edata); + if(ram_data !== edata) begin + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,ram_data, edata); + #1us; + TEST_FAIL; + end + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, ram_data, edata); + end + else begin + $display("* DRAM CS is High => Error!!!"); + TEST_FAIL; + end +endtask + +task REGFILE_CHECK; + input [4:0] addr ; + input [31:0] edata ; + + logic [31:0] reg_data; + @(posedge reg_en ); + @(posedge reg_clk); + if(reg_en)begin + reg_data = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_dat; + if(reg_data !== edata) begin + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,reg_data, edata); + #1us; + TEST_FAIL; + end + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, reg_data, edata); + end + else begin + $display("* REG WR EN is High => Error!!!"); + TEST_FAIL; + end + +endtask + +initial begin + #1000000us; + $display("\n----------------------------------------\n"); + $display("\t Timeout Error !!!!\n"); + TEST_FAIL; +end + diff --git a/tb/qumcu/isa/case/Sw_haddr_test/main.c b/tb/qumcu/isa/case/Sw_haddr_test/main.c new file mode 100644 index 0000000..f92eb3f --- /dev/null +++ b/tb/qumcu/isa/case/Sw_haddr_test/main.c @@ -0,0 +1,20 @@ +//#include + + +//int main(){ +// printf("\t=====================================\n"); +// printf("\t hello world !!! \n"); +// printf("\t=====================================\n"); +//} + +void main(void){ + +unsigned int a,b; + a=5; + b=3; + //c=a+b; + //d=c+b; +} + + + diff --git a/tb/qumcu/isa/case/Sw_haddr_test/main.s b/tb/qumcu/isa/case/Sw_haddr_test/main.s new file mode 100644 index 0000000..7814966 --- /dev/null +++ b/tb/qumcu/isa/case/Sw_haddr_test/main.s @@ -0,0 +1,12 @@ +lui x3,0x87654 +addi x3,x3,0x321 +lui x4,0xfedcb +addi x4,x4,0x7f5 +lui x1,0x104 +lui x2,0x108 +loop: +addi x2,x2,-0x4 +sw x2 ,0x0(x2) +bne x2, x1, loop +exit: + diff --git a/tb/qumcu/isa/case/Sw_haddr_test/user.sv b/tb/qumcu/isa/case/Sw_haddr_test/user.sv new file mode 100644 index 0000000..52e08db --- /dev/null +++ b/tb/qumcu/isa/case/Sw_haddr_test/user.sv @@ -0,0 +1,94 @@ + +wire ram_clk = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U1_TSDN28HPCPUHDB4096X32M4MWR.CLK; +wire ram_cs = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U1_TSDN28HPCPUHDB4096X32M4MWR.CEBA; +wire reg_clk = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.clk; +wire reg_en = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_wen; +reg ram_cs_dly1 ; +reg reg_en_dly1 ; +always @(posedge ram_clk) begin + ram_cs_dly1 <= ~ram_cs; + reg_en_dly1 <= reg_en; +end + +reg [15:0] temp; +reg [15:0] temp1; +initial begin + #1ns; + //@(posedge ram_cs_dly1 ); + #5ns; + //while(1)begin + #1ns; + REGFILE_CHECK(6'd3,32'h8765_4000); + REGFILE_CHECK(6'd3,32'h8765_4321); + REGFILE_CHECK(6'd4,32'hfedc_b000); + REGFILE_CHECK(6'd4,32'hfedc_b7f5); + REGFILE_CHECK(6'd1,32'h0010_4000); + REGFILE_CHECK(6'd2,32'h0010_8000); + for(int i = 8191; i > 4095; i--) begin + temp = i*4; + temp1 = i - 4096; + REGFILE_CHECK(6'd2,{16'h0010,temp}); + //$monitor($time, " Simulation time: %t", $time); + DRAM_DATA_CHECK(temp1,{16'h0010,temp}); + end + //@(posedge reg_en_dly1 ); + + #10us; + TEST_PASS; +end + +task DRAM_DATA_CHECK; + input [12:0] addr ; + input [31:0] edata ; + + logic [31:0] ram_data; + + @(posedge ram_cs_dly1 ); + @(posedge ram_clk ); + //$monitor($time, " Simulation time: %t", $time); + if(ram_cs_dly1) begin + ram_data = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U1_TSDN28HPCPUHDB4096X32M4MWR.MX.mem[addr]; + //$display("* RAM_DATA[%x]: %x | EXP_DATA: %x ",addr,ram_data, edata); + if(ram_data !== edata) begin + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,ram_data, edata); + #1us; + TEST_FAIL; + end + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, ram_data, edata); + end + else begin + $display("* DRAM CS is High => Error!!!"); + TEST_FAIL; + end +endtask + +task REGFILE_CHECK; + input [4:0] addr ; + input [31:0] edata ; + + logic [31:0] reg_data; + @(posedge reg_en ); + @(posedge reg_clk); + if(reg_en)begin + reg_data = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_dat; + if(reg_data !== edata) begin + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,reg_data, edata); + #1us; + //TEST_FAIL; + end + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, reg_data, edata); + end + else begin + $display("* REG WR EN is High => Error!!!"); + //TEST_FAIL; + end + +endtask + +initial begin + #10000us; + $display("\n----------------------------------------\n"); + $display("\t Timeout Error !!!!\n"); + TEST_FAIL; +end + diff --git a/tb/qumcu/isa/case/Sw_test/main.c b/tb/qumcu/isa/case/Sw_test/main.c new file mode 100644 index 0000000..f92eb3f --- /dev/null +++ b/tb/qumcu/isa/case/Sw_test/main.c @@ -0,0 +1,20 @@ +//#include + + +//int main(){ +// printf("\t=====================================\n"); +// printf("\t hello world !!! \n"); +// printf("\t=====================================\n"); +//} + +void main(void){ + +unsigned int a,b; + a=5; + b=3; + //c=a+b; + //d=c+b; +} + + + diff --git a/tb/qumcu/isa/case/Sw_test/main.s b/tb/qumcu/isa/case/Sw_test/main.s new file mode 100644 index 0000000..7516e26 --- /dev/null +++ b/tb/qumcu/isa/case/Sw_test/main.s @@ -0,0 +1,12 @@ +lui x3,0x87654 +addi x3,x3,0x321 +lui x4,0xfedcb +addi x4,x4,0x7f5 +lui x1,0x100 +lui x2,0x104 +loop: +addi x2,x2,-0x4 +sw x2 ,0x0(x2) +bne x2, x1, loop +exit: + diff --git a/tb/qumcu/isa/case/Sw_test/user.sv b/tb/qumcu/isa/case/Sw_test/user.sv new file mode 100644 index 0000000..ff08bb6 --- /dev/null +++ b/tb/qumcu/isa/case/Sw_test/user.sv @@ -0,0 +1,92 @@ + +wire ram_clk = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CLK; +wire ram_cs = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CEBA; +wire reg_clk = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.clk; +wire reg_en = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_wen; +reg ram_cs_dly1 ; +reg reg_en_dly1 ; +always @(posedge ram_clk) begin + ram_cs_dly1 <= ~ram_cs; + reg_en_dly1 <= reg_en; +end + +reg [15:0] temp; +initial begin + #1ns; + //@(posedge ram_cs_dly1 ); + #5ns; + //while(1)begin + #1ns; + REGFILE_CHECK(6'd3,32'h8765_4000); + REGFILE_CHECK(6'd3,32'h8765_4321); + REGFILE_CHECK(6'd4,32'hfedc_b000); + REGFILE_CHECK(6'd4,32'hfedc_b7f5); + REGFILE_CHECK(6'd1,32'h0010_0000); + REGFILE_CHECK(6'd2,32'h0010_4000); + for(int i = 4095; i > 0; i--) begin + temp = i*4; + REGFILE_CHECK(6'd2,{16'h0010,temp}); + //$monitor($time, " Simulation time: %t", $time); + DRAM_DATA_CHECK(i,{16'h0010,temp}); + end + //@(posedge reg_en_dly1 ); + + #10us; + TEST_PASS; +end + +task DRAM_DATA_CHECK; + input [12:0] addr ; + input [31:0] edata ; + + logic [31:0] ram_data; + + @(posedge ram_cs_dly1 ); + @(posedge ram_clk ); + //$monitor($time, " Simulation time: %t", $time); + if(ram_cs_dly1) begin + ram_data = `TB_DRAM.mem[addr]; + //$display("* RAM_DATA[%x]: %x | EXP_DATA: %x ",addr,ram_data, edata); + if(ram_data !== edata) begin + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,ram_data, edata); + #1us; + TEST_FAIL; + end + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, ram_data, edata); + end + else begin + $display("* DRAM CS is High => Error!!!"); + TEST_FAIL; + end +endtask + +task REGFILE_CHECK; + input [4:0] addr ; + input [31:0] edata ; + + logic [31:0] reg_data; + @(posedge reg_en ); + @(posedge reg_clk); + if(reg_en)begin + reg_data = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_dat; + if(reg_data !== edata) begin + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,reg_data, edata); + #1us; + //TEST_FAIL; + end + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, reg_data, edata); + end + else begin + $display("* REG WR EN is High => Error!!!"); + //TEST_FAIL; + end + +endtask + +initial begin + #10000us; + $display("\n----------------------------------------\n"); + $display("\t Timeout Error !!!!\n"); + TEST_FAIL; +end + diff --git a/tb/qumcu/isa/case/Xor_test/main.c b/tb/qumcu/isa/case/Xor_test/main.c new file mode 100644 index 0000000..f92eb3f --- /dev/null +++ b/tb/qumcu/isa/case/Xor_test/main.c @@ -0,0 +1,20 @@ +//#include + + +//int main(){ +// printf("\t=====================================\n"); +// printf("\t hello world !!! \n"); +// printf("\t=====================================\n"); +//} + +void main(void){ + +unsigned int a,b; + a=5; + b=3; + //c=a+b; + //d=c+b; +} + + + diff --git a/tb/qumcu/isa/case/Xor_test/main.s b/tb/qumcu/isa/case/Xor_test/main.s new file mode 100644 index 0000000..3b723e4 --- /dev/null +++ b/tb/qumcu/isa/case/Xor_test/main.s @@ -0,0 +1,40 @@ +lui x1,0xfffff +addi x1,x1,0x7ff +addi x1,x1,0x7ff +addi x1,x1,0x1 + +lui x2,0xaaaaa +addi x2,x2,0x555 +addi x2,x2,0x555 + +lui x3,0x55555 +addi x3,x3,0x555 + +lui x4,0x11111 +addi x4,x4,0x111 + +addi x5,x0,0x0 + + +xor x6,x1,x1 +xor x7,x1,x2 +xor x8,x1,x3 +xor x9,x1,x4 +xor x10,x1,x5 + +xor x11,x2,x2 +xor x12,x2,x3 +xor x13,x2,x4 +xor x14,x2,x5 + +xor x15,x3,x3 +xor x16,x3,x4 +xor x17,x3,x5 + +xor x18,x4,x4 +xor x19,x4,x5 + +xor x20,x5,x5 + + + diff --git a/tb/qumcu/isa/case/Xor_test/user.sv b/tb/qumcu/isa/case/Xor_test/user.sv new file mode 100644 index 0000000..6103aca --- /dev/null +++ b/tb/qumcu/isa/case/Xor_test/user.sv @@ -0,0 +1,111 @@ + +wire ram_clk = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CLK; +wire ram_cs = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CEBA; +wire reg_clk = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.clk; +wire reg_en = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_wen; +reg ram_cs_dly1 ; +reg reg_en_dly1 ; +always @(posedge ram_clk) begin + ram_cs_dly1 <= ~ram_cs; + reg_en_dly1 <= reg_en; +end + +reg [31:0] temp; +initial begin + #1ns; + //@(posedge ram_cs_dly1 ); + #5ns; + //while(1)begin + #1ns; + REGFILE_CHECK(6'd1 ,32'hffff_f000); + REGFILE_CHECK(6'd1 ,32'hffff_f7ff); + REGFILE_CHECK(6'd1 ,32'hffff_fffe); + REGFILE_CHECK(6'd1 ,32'hffff_ffff); + REGFILE_CHECK(6'd2 ,32'haaaa_a000); + REGFILE_CHECK(6'd2 ,32'haaaa_a555); + REGFILE_CHECK(6'd2 ,32'haaaa_aaaa); + REGFILE_CHECK(6'd3 ,32'h5555_5000); + REGFILE_CHECK(6'd3 ,32'h5555_5555); + REGFILE_CHECK(6'd4 ,32'h1111_1000); + REGFILE_CHECK(6'd4 ,32'h1111_1111); + REGFILE_CHECK(6'd5 ,32'h0000_0000); + REGFILE_CHECK(6'd6 ,32'h0000_0000); + REGFILE_CHECK(6'd7 ,32'h5555_5555); + REGFILE_CHECK(6'd8 ,32'haaaa_aaaa); + REGFILE_CHECK(6'd9 ,32'heeee_eeee); + REGFILE_CHECK(6'd10,32'hffff_ffff); + REGFILE_CHECK(6'd11,32'h0000_0000); + REGFILE_CHECK(6'd12,32'hffff_ffff); + REGFILE_CHECK(6'd13,32'hbbbb_bbbb); + REGFILE_CHECK(6'd14,32'haaaa_aaaa); + REGFILE_CHECK(6'd15,32'h0000_0000); + REGFILE_CHECK(6'd16,32'h4444_4444); + REGFILE_CHECK(6'd17,32'h5555_5555); + REGFILE_CHECK(6'd18,32'h0000_0000); + REGFILE_CHECK(6'd19,32'h1111_1111); + REGFILE_CHECK(6'd20,32'h0000_0000); + + + + + //@(posedge reg_en_dly1 ); + + #10us; + TEST_PASS; +end + +task DRAM_DATA_CHECK; + input [12:0] addr ; + input [31:0] edata ; + + logic [31:0] ram_data; + + @(posedge ram_cs_dly1 ); + @(posedge ram_clk ); + //$monitor($time, " Simulation time: %t", $time); + if(ram_cs_dly1) begin + ram_data = `TB_DRAM.mem[addr]; + //$display("* RAM_DATA[%x]: %x | EXP_DATA: %x ",addr,ram_data, edata); + if(ram_data !== edata) begin + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,ram_data, edata); + #1us; + TEST_FAIL; + end + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, ram_data, edata); + end + else begin + $display("* DRAM CS is High => Error!!!"); + TEST_FAIL; + end +endtask + +task REGFILE_CHECK; + input [4:0] addr ; + input [31:0] edata ; + + logic [31:0] reg_data; + @(posedge reg_en ); + @(posedge reg_clk); + if(reg_en)begin + reg_data = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_dat; + if(reg_data !== edata) begin + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,reg_data, edata); + #1us; + TEST_FAIL; + end + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, reg_data, edata); + end + else begin + $display("* REG WR EN is High => Error!!!"); + TEST_FAIL; + end + +endtask + +initial begin + #1000000us; + $display("\n----------------------------------------\n"); + $display("\t Timeout Error !!!!\n"); + TEST_FAIL; +end + diff --git a/tb/qumcu/isa/case/Xori_test/main.c b/tb/qumcu/isa/case/Xori_test/main.c new file mode 100644 index 0000000..f92eb3f --- /dev/null +++ b/tb/qumcu/isa/case/Xori_test/main.c @@ -0,0 +1,20 @@ +//#include + + +//int main(){ +// printf("\t=====================================\n"); +// printf("\t hello world !!! \n"); +// printf("\t=====================================\n"); +//} + +void main(void){ + +unsigned int a,b; + a=5; + b=3; + //c=a+b; + //d=c+b; +} + + + diff --git a/tb/qumcu/isa/case/Xori_test/main.s b/tb/qumcu/isa/case/Xori_test/main.s new file mode 100644 index 0000000..6e32983 --- /dev/null +++ b/tb/qumcu/isa/case/Xori_test/main.s @@ -0,0 +1,50 @@ +lui x1,0xfffff +addi x1,x1,0x7ff +addi x1,x1,0x7ff +addi x1,x1,0x1 + +lui x2,0xaaaaa +addi x2,x2,0x555 +addi x2,x2,0x555 + +lui x3,0x55555 +addi x3,x3,0x555 + +lui x4,0x11111 +addi x4,x4,0x111 + +addi x5,x0,0x0 + + +xori x6 ,x1,0x7ff +xori x7 ,x1,0x7aa +xori x8 ,x1,0x555 +xori x9 ,x1,0x111 +xori x10,x1,0x000 + +xori x11,x2,0x7ff +xori x12,x2,0x7aa +xori x13,x2,0x555 +xori x14,x2,0x111 +xori x15,x2,0x000 + +xori x16,x3,0x7ff +xori x17,x3,0x7aa +xori x18,x3,0x555 +xori x19,x3,0x111 +xori x20,x3,0x000 + +xori x21,x4,0x7ff +xori x22,x4,0x7aa +xori x23,x4,0x555 +xori x24,x4,0x111 +xori x25,x4,0x000 + +xori x26,x5,0x7ff +xori x27,x5,0x7aa +xori x28,x5,0x555 +xori x29,x5,0x111 +xori x30,x5,0x000 + + + diff --git a/tb/qumcu/isa/case/Xori_test/user.sv b/tb/qumcu/isa/case/Xori_test/user.sv new file mode 100644 index 0000000..c787260 --- /dev/null +++ b/tb/qumcu/isa/case/Xori_test/user.sv @@ -0,0 +1,121 @@ + +wire ram_clk = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CLK; +wire ram_cs = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CEBA; +wire reg_clk = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.clk; +wire reg_en = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_wen; +reg ram_cs_dly1 ; +reg reg_en_dly1 ; +always @(posedge ram_clk) begin + ram_cs_dly1 <= ~ram_cs; + reg_en_dly1 <= reg_en; +end + +reg [31:0] temp; +initial begin + #1ns; + //@(posedge ram_cs_dly1 ); + #5ns; + //while(1)begin + #1ns; + REGFILE_CHECK(6'd1 ,32'hffff_f000); + REGFILE_CHECK(6'd1 ,32'hffff_f7ff); + REGFILE_CHECK(6'd1 ,32'hffff_fffe); + REGFILE_CHECK(6'd1 ,32'hffff_ffff); + REGFILE_CHECK(6'd2 ,32'haaaa_a000); + REGFILE_CHECK(6'd2 ,32'haaaa_a555); + REGFILE_CHECK(6'd2 ,32'haaaa_aaaa); + REGFILE_CHECK(6'd3 ,32'h5555_5000); + REGFILE_CHECK(6'd3 ,32'h5555_5555); + REGFILE_CHECK(6'd4 ,32'h1111_1000); + REGFILE_CHECK(6'd4 ,32'h1111_1111); + REGFILE_CHECK(6'd5 ,32'h0000_0000); + REGFILE_CHECK(6'd6 ,32'hffff_f800); + REGFILE_CHECK(6'd7 ,32'hffff_f855); + REGFILE_CHECK(6'd8 ,32'hffff_faaa); + REGFILE_CHECK(6'd9 ,32'hffff_feee); + REGFILE_CHECK(6'd10,32'hffff_ffff); + REGFILE_CHECK(6'd11,32'haaaa_ad55); + REGFILE_CHECK(6'd12,32'haaaa_ad00); + REGFILE_CHECK(6'd13,32'haaaa_afff); + REGFILE_CHECK(6'd14,32'haaaa_abbb); + REGFILE_CHECK(6'd15,32'haaaa_aaaa); + REGFILE_CHECK(6'd16,32'h5555_52aa); + REGFILE_CHECK(6'd17,32'h5555_52ff); + REGFILE_CHECK(6'd18,32'h5555_5000); + REGFILE_CHECK(6'd19,32'h5555_5444); + REGFILE_CHECK(6'd20,32'h5555_5555); + REGFILE_CHECK(6'd21,32'h1111_16ee); + REGFILE_CHECK(6'd22,32'h1111_16bb); + REGFILE_CHECK(6'd23,32'h1111_1444); + REGFILE_CHECK(6'd24,32'h1111_1000); + REGFILE_CHECK(6'd25,32'h1111_1111); + REGFILE_CHECK(6'd26,32'h0000_07ff); + REGFILE_CHECK(6'd27,32'h0000_07aa); + REGFILE_CHECK(6'd28,32'h0000_0555); + REGFILE_CHECK(6'd29,32'h0000_0111); + REGFILE_CHECK(6'd30,32'h0000_0000); + + + + + //@(posedge reg_en_dly1 ); + + #10us; + TEST_PASS; +end + +task DRAM_DATA_CHECK; + input [12:0] addr ; + input [31:0] edata ; + + logic [31:0] ram_data; + + @(posedge ram_cs_dly1 ); + @(posedge ram_clk ); + //$monitor($time, " Simulation time: %t", $time); + if(ram_cs_dly1) begin + ram_data = `TB_DRAM.mem[addr]; + //$display("* RAM_DATA[%x]: %x | EXP_DATA: %x ",addr,ram_data, edata); + if(ram_data !== edata) begin + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,ram_data, edata); + #1us; + TEST_FAIL; + end + $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, ram_data, edata); + end + else begin + $display("* DRAM CS is High => Error!!!"); + TEST_FAIL; + end +endtask + +task REGFILE_CHECK; + input [4:0] addr ; + input [31:0] edata ; + + logic [31:0] reg_data; + @(posedge reg_en ); + @(posedge reg_clk); + if(reg_en)begin + reg_data = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_dat; + if(reg_data !== edata) begin + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,reg_data, edata); + #1us; + TEST_FAIL; + end + $display("* REG_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, reg_data, edata); + end + else begin + $display("* REG WR EN is High => Error!!!"); + TEST_FAIL; + end + +endtask + +initial begin + #1000000us; + $display("\n----------------------------------------\n"); + $display("\t Timeout Error !!!!\n"); + TEST_FAIL; +end + diff --git a/tb/qumcu/isa/macros/scalar/test_macros.h b/tb/qumcu/isa/macros/scalar/test_macros.h new file mode 100644 index 0000000..6c901d0 --- /dev/null +++ b/tb/qumcu/isa/macros/scalar/test_macros.h @@ -0,0 +1,753 @@ +// See LICENSE for license details. + +#ifndef __TEST_MACROS_SCALAR_H +#define __TEST_MACROS_SCALAR_H + + +#----------------------------------------------------------------------- +# Helper macros +#----------------------------------------------------------------------- + +#define MASK_XLEN(x) ((x) & ((1 << (__riscv_xlen - 1) << 1) - 1)) + +#define TEST_CASE( testnum, testreg, correctval, code... ) \ +test_ ## testnum: \ + li TESTNUM, testnum; \ + code; \ + li x7, MASK_XLEN(correctval); \ + bne testreg, x7, fail; + +# We use a macro hack to simpify code generation for various numbers +# of bubble cycles. + +#define TEST_INSERT_NOPS_0 +#define TEST_INSERT_NOPS_1 nop; TEST_INSERT_NOPS_0 +#define TEST_INSERT_NOPS_2 nop; TEST_INSERT_NOPS_1 +#define TEST_INSERT_NOPS_3 nop; TEST_INSERT_NOPS_2 +#define TEST_INSERT_NOPS_4 nop; TEST_INSERT_NOPS_3 +#define TEST_INSERT_NOPS_5 nop; TEST_INSERT_NOPS_4 +#define TEST_INSERT_NOPS_6 nop; TEST_INSERT_NOPS_5 +#define TEST_INSERT_NOPS_7 nop; TEST_INSERT_NOPS_6 +#define TEST_INSERT_NOPS_8 nop; TEST_INSERT_NOPS_7 +#define TEST_INSERT_NOPS_9 nop; TEST_INSERT_NOPS_8 +#define TEST_INSERT_NOPS_10 nop; TEST_INSERT_NOPS_9 + + +#----------------------------------------------------------------------- +# RV64UI MACROS +#----------------------------------------------------------------------- + +#----------------------------------------------------------------------- +# Tests for instructions with immediate operand +#----------------------------------------------------------------------- + +#define SEXT_IMM(x) ((x) | (-(((x) >> 11) & 1) << 11)) + +#define TEST_IMM_OP( testnum, inst, result, val1, imm ) \ + TEST_CASE( testnum, x14, result, \ + li x1, MASK_XLEN(val1); \ + inst x14, x1, SEXT_IMM(imm); \ + ) + +#define TEST_IMM_SRC1_EQ_DEST( testnum, inst, result, val1, imm ) \ + TEST_CASE( testnum, x1, result, \ + li x1, MASK_XLEN(val1); \ + inst x1, x1, SEXT_IMM(imm); \ + ) + +#define TEST_IMM_DEST_BYPASS( testnum, nop_cycles, inst, result, val1, imm ) \ + TEST_CASE( testnum, x6, result, \ + li x4, 0; \ +1: li x1, MASK_XLEN(val1); \ + inst x14, x1, SEXT_IMM(imm); \ + TEST_INSERT_NOPS_ ## nop_cycles \ + addi x6, x14, 0; \ + addi x4, x4, 1; \ + li x5, 2; \ + bne x4, x5, 1b \ + ) + +#define TEST_IMM_SRC1_BYPASS( testnum, nop_cycles, inst, result, val1, imm ) \ + TEST_CASE( testnum, x14, result, \ + li x4, 0; \ +1: li x1, MASK_XLEN(val1); \ + TEST_INSERT_NOPS_ ## nop_cycles \ + inst x14, x1, SEXT_IMM(imm); \ + addi x4, x4, 1; \ + li x5, 2; \ + bne x4, x5, 1b \ + ) + +#define TEST_IMM_ZEROSRC1( testnum, inst, result, imm ) \ + TEST_CASE( testnum, x1, result, \ + inst x1, x0, SEXT_IMM(imm); \ + ) + +#define TEST_IMM_ZERODEST( testnum, inst, val1, imm ) \ + TEST_CASE( testnum, x0, 0, \ + li x1, MASK_XLEN(val1); \ + inst x0, x1, SEXT_IMM(imm); \ + ) + +#----------------------------------------------------------------------- +# Tests for an instruction with register operands +#----------------------------------------------------------------------- + +#define TEST_R_OP( testnum, inst, result, val1 ) \ + TEST_CASE( testnum, x14, result, \ + li x1, val1; \ + inst x14, x1; \ + ) + +#define TEST_R_SRC1_EQ_DEST( testnum, inst, result, val1 ) \ + TEST_CASE( testnum, x1, result, \ + li x1, val1; \ + inst x1, x1; \ + ) + +#define TEST_R_DEST_BYPASS( testnum, nop_cycles, inst, result, val1 ) \ + TEST_CASE( testnum, x6, result, \ + li x4, 0; \ +1: li x1, val1; \ + inst x14, x1; \ + TEST_INSERT_NOPS_ ## nop_cycles \ + addi x6, x14, 0; \ + addi x4, x4, 1; \ + li x5, 2; \ + bne x4, x5, 1b \ + ) + +#----------------------------------------------------------------------- +# Tests for an instruction with register-register operands +#----------------------------------------------------------------------- + +#define TEST_RR_OP( testnum, inst, result, val1, val2 ) \ + TEST_CASE( testnum, x14, result, \ + li x1, MASK_XLEN(val1); \ + li x2, MASK_XLEN(val2); \ + inst x14, x1, x2; \ + ) + +#define TEST_RR_SRC1_EQ_DEST( testnum, inst, result, val1, val2 ) \ + TEST_CASE( testnum, x1, result, \ + li x1, MASK_XLEN(val1); \ + li x2, MASK_XLEN(val2); \ + inst x1, x1, x2; \ + ) + +#define TEST_RR_SRC2_EQ_DEST( testnum, inst, result, val1, val2 ) \ + TEST_CASE( testnum, x2, result, \ + li x1, MASK_XLEN(val1); \ + li x2, MASK_XLEN(val2); \ + inst x2, x1, x2; \ + ) + +#define TEST_RR_SRC12_EQ_DEST( testnum, inst, result, val1 ) \ + TEST_CASE( testnum, x1, result, \ + li x1, MASK_XLEN(val1); \ + inst x1, x1, x1; \ + ) + +#define TEST_RR_DEST_BYPASS( testnum, nop_cycles, inst, result, val1, val2 ) \ + TEST_CASE( testnum, x6, result, \ + li x4, 0; \ +1: li x1, MASK_XLEN(val1); \ + li x2, MASK_XLEN(val2); \ + inst x14, x1, x2; \ + TEST_INSERT_NOPS_ ## nop_cycles \ + addi x6, x14, 0; \ + addi x4, x4, 1; \ + li x5, 2; \ + bne x4, x5, 1b \ + ) + +#define TEST_RR_SRC12_BYPASS( testnum, src1_nops, src2_nops, inst, result, val1, val2 ) \ + TEST_CASE( testnum, x14, result, \ + li x4, 0; \ +1: li x1, MASK_XLEN(val1); \ + TEST_INSERT_NOPS_ ## src1_nops \ + li x2, MASK_XLEN(val2); \ + TEST_INSERT_NOPS_ ## src2_nops \ + inst x14, x1, x2; \ + addi x4, x4, 1; \ + li x5, 2; \ + bne x4, x5, 1b \ + ) + +#define TEST_RR_SRC21_BYPASS( testnum, src1_nops, src2_nops, inst, result, val1, val2 ) \ + TEST_CASE( testnum, x14, result, \ + li x4, 0; \ +1: li x2, MASK_XLEN(val2); \ + TEST_INSERT_NOPS_ ## src1_nops \ + li x1, MASK_XLEN(val1); \ + TEST_INSERT_NOPS_ ## src2_nops \ + inst x14, x1, x2; \ + addi x4, x4, 1; \ + li x5, 2; \ + bne x4, x5, 1b \ + ) + +#define TEST_RR_ZEROSRC1( testnum, inst, result, val ) \ + TEST_CASE( testnum, x2, result, \ + li x1, MASK_XLEN(val); \ + inst x2, x0, x1; \ + ) + +#define TEST_RR_ZEROSRC2( testnum, inst, result, val ) \ + TEST_CASE( testnum, x2, result, \ + li x1, MASK_XLEN(val); \ + inst x2, x1, x0; \ + ) + +#define TEST_RR_ZEROSRC12( testnum, inst, result ) \ + TEST_CASE( testnum, x1, result, \ + inst x1, x0, x0; \ + ) + +#define TEST_RR_ZERODEST( testnum, inst, val1, val2 ) \ + TEST_CASE( testnum, x0, 0, \ + li x1, MASK_XLEN(val1); \ + li x2, MASK_XLEN(val2); \ + inst x0, x1, x2; \ + ) + +#----------------------------------------------------------------------- +# Test memory instructions +#----------------------------------------------------------------------- + +#define TEST_LD_OP( testnum, inst, result, offset, base ) \ + TEST_CASE( testnum, x14, result, \ + li x15, result; /* Tell the exception handler the expected result. */ \ + la x1, base; \ + inst x14, offset(x1); \ + ) + +#define TEST_ST_OP( testnum, load_inst, store_inst, result, offset, base ) \ + TEST_CASE( testnum, x14, result, \ + la x1, base; \ + li x2, result; \ + la x15, 7f; /* Tell the exception handler how to skip this test. */ \ + store_inst x2, offset(x1); \ + load_inst x14, offset(x1); \ + j 8f; \ +7: \ + /* Set up the correct result for TEST_CASE(). */ \ + mv x14, x2; \ +8: \ + ) + +#define TEST_LD_DEST_BYPASS( testnum, nop_cycles, inst, result, offset, base ) \ +test_ ## testnum: \ + li TESTNUM, testnum; \ + li x4, 0; \ +1: la x1, base; \ + inst x14, offset(x1); \ + TEST_INSERT_NOPS_ ## nop_cycles \ + addi x6, x14, 0; \ + li x7, result; \ + bne x6, x7, fail; \ + addi x4, x4, 1; \ + li x5, 2; \ + bne x4, x5, 1b; \ + +#define TEST_LD_SRC1_BYPASS( testnum, nop_cycles, inst, result, offset, base ) \ +test_ ## testnum: \ + li TESTNUM, testnum; \ + li x4, 0; \ +1: la x1, base; \ + TEST_INSERT_NOPS_ ## nop_cycles \ + inst x14, offset(x1); \ + li x7, result; \ + bne x14, x7, fail; \ + addi x4, x4, 1; \ + li x5, 2; \ + bne x4, x5, 1b \ + +#define TEST_ST_SRC12_BYPASS( testnum, src1_nops, src2_nops, load_inst, store_inst, result, offset, base ) \ +test_ ## testnum: \ + li TESTNUM, testnum; \ + li x4, 0; \ +1: li x1, result; \ + TEST_INSERT_NOPS_ ## src1_nops \ + la x2, base; \ + TEST_INSERT_NOPS_ ## src2_nops \ + store_inst x1, offset(x2); \ + load_inst x14, offset(x2); \ + li x7, result; \ + bne x14, x7, fail; \ + addi x4, x4, 1; \ + li x5, 2; \ + bne x4, x5, 1b \ + +#define TEST_ST_SRC21_BYPASS( testnum, src1_nops, src2_nops, load_inst, store_inst, result, offset, base ) \ +test_ ## testnum: \ + li TESTNUM, testnum; \ + li x4, 0; \ +1: la x2, base; \ + TEST_INSERT_NOPS_ ## src1_nops \ + li x1, result; \ + TEST_INSERT_NOPS_ ## src2_nops \ + store_inst x1, offset(x2); \ + load_inst x14, offset(x2); \ + li x7, result; \ + bne x14, x7, fail; \ + addi x4, x4, 1; \ + li x5, 2; \ + bne x4, x5, 1b \ + +#define TEST_BR2_OP_TAKEN( testnum, inst, val1, val2 ) \ +test_ ## testnum: \ + li TESTNUM, testnum; \ + li x1, val1; \ + li x2, val2; \ + inst x1, x2, 2f; \ + bne x0, TESTNUM, fail; \ +1: bne x0, TESTNUM, 3f; \ +2: inst x1, x2, 1b; \ + bne x0, TESTNUM, fail; \ +3: + +#define TEST_BR2_OP_NOTTAKEN( testnum, inst, val1, val2 ) \ +test_ ## testnum: \ + li TESTNUM, testnum; \ + li x1, val1; \ + li x2, val2; \ + inst x1, x2, 1f; \ + bne x0, TESTNUM, 2f; \ +1: bne x0, TESTNUM, fail; \ +2: inst x1, x2, 1b; \ +3: + +#define TEST_BR2_SRC12_BYPASS( testnum, src1_nops, src2_nops, inst, val1, val2 ) \ +test_ ## testnum: \ + li TESTNUM, testnum; \ + li x4, 0; \ +1: li x1, val1; \ + TEST_INSERT_NOPS_ ## src1_nops \ + li x2, val2; \ + TEST_INSERT_NOPS_ ## src2_nops \ + inst x1, x2, fail; \ + addi x4, x4, 1; \ + li x5, 2; \ + bne x4, x5, 1b \ + +#define TEST_BR2_SRC21_BYPASS( testnum, src1_nops, src2_nops, inst, val1, val2 ) \ +test_ ## testnum: \ + li TESTNUM, testnum; \ + li x4, 0; \ +1: li x2, val2; \ + TEST_INSERT_NOPS_ ## src1_nops \ + li x1, val1; \ + TEST_INSERT_NOPS_ ## src2_nops \ + inst x1, x2, fail; \ + addi x4, x4, 1; \ + li x5, 2; \ + bne x4, x5, 1b \ + +#----------------------------------------------------------------------- +# Test jump instructions +#----------------------------------------------------------------------- + +#define TEST_JR_SRC1_BYPASS( testnum, nop_cycles, inst ) \ +test_ ## testnum: \ + li TESTNUM, testnum; \ + li x4, 0; \ +1: la x6, 2f; \ + TEST_INSERT_NOPS_ ## nop_cycles \ + inst x6; \ + bne x0, TESTNUM, fail; \ +2: addi x4, x4, 1; \ + li x5, 2; \ + bne x4, x5, 1b \ + +#define TEST_JALR_SRC1_BYPASS( testnum, nop_cycles, inst ) \ +test_ ## testnum: \ + li TESTNUM, testnum; \ + li x4, 0; \ +1: la x6, 2f; \ + TEST_INSERT_NOPS_ ## nop_cycles \ + inst x13, x6, 0; \ + bne x0, TESTNUM, fail; \ +2: addi x4, x4, 1; \ + li x5, 2; \ + bne x4, x5, 1b \ + + +#----------------------------------------------------------------------- +# RV64UF MACROS +#----------------------------------------------------------------------- + +#----------------------------------------------------------------------- +# Tests floating-point instructions +#----------------------------------------------------------------------- + +#define qNaNh 0h:7e00 +#define sNaNh 0h:7c01 +#define qNaNf 0f:7fc00000 +#define sNaNf 0f:7f800001 +#define qNaN 0d:7ff8000000000000 +#define sNaN 0d:7ff0000000000001 + +#define TEST_FP_OP_H_INTERNAL( testnum, flags, result, val1, val2, val3, code... ) \ +test_ ## testnum: \ + li TESTNUM, testnum; \ + la a0, test_ ## testnum ## _data ;\ + flh f0, 0(a0); \ + flh f1, 2(a0); \ + flh f2, 4(a0); \ + lh a3, 6(a0); \ + code; \ + fsflags a1, x0; \ + li a2, flags; \ + bne a0, a3, fail; \ + bne a1, a2, fail; \ + .pushsection .data; \ + .align 1; \ + test_ ## testnum ## _data: \ + .float16 val1; \ + .float16 val2; \ + .float16 val3; \ + .result; \ + .popsection + +#define TEST_FP_OP_S_INTERNAL( testnum, flags, result, val1, val2, val3, code... ) \ +test_ ## testnum: \ + li TESTNUM, testnum; \ + la a0, test_ ## testnum ## _data ;\ + flw f0, 0(a0); \ + flw f1, 4(a0); \ + flw f2, 8(a0); \ + lw a3, 12(a0); \ + code; \ + fsflags a1, x0; \ + li a2, flags; \ + bne a0, a3, fail; \ + bne a1, a2, fail; \ + .pushsection .data; \ + .align 2; \ + test_ ## testnum ## _data: \ + .float val1; \ + .float val2; \ + .float val3; \ + .result; \ + .popsection + +#define TEST_FP_OP_D_INTERNAL( testnum, flags, result, val1, val2, val3, code... ) \ +test_ ## testnum: \ + li TESTNUM, testnum; \ + la a0, test_ ## testnum ## _data ;\ + fld f0, 0(a0); \ + fld f1, 8(a0); \ + fld f2, 16(a0); \ + ld a3, 24(a0); \ + code; \ + fsflags a1, x0; \ + li a2, flags; \ + bne a0, a3, fail; \ + bne a1, a2, fail; \ + .pushsection .data; \ + .align 3; \ + test_ ## testnum ## _data: \ + .double val1; \ + .double val2; \ + .double val3; \ + .result; \ + .popsection + +// TODO: assign a separate mem location for the comparison address? +#define TEST_FP_OP_D32_INTERNAL( testnum, flags, result, val1, val2, val3, code... ) \ +test_ ## testnum: \ + li TESTNUM, testnum; \ + la a0, test_ ## testnum ## _data ;\ + fld f0, 0(a0); \ + fld f1, 8(a0); \ + fld f2, 16(a0); \ + lw a3, 24(a0); \ + lw t1, 28(a0); \ + code; \ + fsflags a1, x0; \ + li a2, flags; \ + bne a0, a3, fail; \ + bne t1, t2, fail; \ + bne a1, a2, fail; \ + .pushsection .data; \ + .align 3; \ + test_ ## testnum ## _data: \ + .double val1; \ + .double val2; \ + .double val3; \ + .result; \ + .popsection + +#define TEST_FCVT_S_D32( testnum, result, val1 ) \ + TEST_FP_OP_D32_INTERNAL( testnum, 0, double result, val1, 0.0, 0.0, \ + fcvt.s.d f3, f0; fcvt.d.s f3, f3; fsd f3, 0(a0); lw t2, 4(a0); lw a0, 0(a0)) + +#define TEST_FCVT_S_D( testnum, result, val1 ) \ + TEST_FP_OP_D_INTERNAL( testnum, 0, double result, val1, 0.0, 0.0, \ + fcvt.s.d f3, f0; fcvt.d.s f3, f3; fmv.x.d a0, f3) + +#define TEST_FCVT_D_S( testnum, result, val1 ) \ + TEST_FP_OP_S_INTERNAL( testnum, 0, float result, val1, 0.0, 0.0, \ + fcvt.d.s f3, f0; fcvt.s.d f3, f3; fmv.x.s a0, f3) + +#define TEST_FCVT_H_S( testnum, result, val1 ) \ + TEST_FP_OP_H_INTERNAL( testnum, 0, float16 result, val1, 0.0, 0.0, \ + fcvt.s.h f3, f0; fcvt.h.s f3, f3; fmv.x.h a0, f3) + +#define TEST_FCVT_H_D( testnum, result, val1 ) \ + TEST_FP_OP_H_INTERNAL( testnum, 0, float16 result, val1, 0.0, 0.0, \ + fcvt.d.h f3, f0; fcvt.h.d f3, f3; fmv.x.h a0, f3) + + +#define TEST_FP_OP1_H( testnum, inst, flags, result, val1 ) \ + TEST_FP_OP_H_INTERNAL( testnum, flags, float16 result, val1, 0.0, 0.0, \ + inst f3, f0; fmv.x.h a0, f3;) + +#define TEST_FP_OP1_S( testnum, inst, flags, result, val1 ) \ + TEST_FP_OP_S_INTERNAL( testnum, flags, float result, val1, 0.0, 0.0, \ + inst f3, f0; fmv.x.s a0, f3) + +#define TEST_FP_OP1_D32( testnum, inst, flags, result, val1 ) \ + TEST_FP_OP_D32_INTERNAL( testnum, flags, double result, val1, 0.0, 0.0, \ + inst f3, f0; fsd f3, 0(a0); lw t2, 4(a0); lw a0, 0(a0)) +// ^: store computation result in address from a0, load high-word into t2 + +#define TEST_FP_OP1_D( testnum, inst, flags, result, val1 ) \ + TEST_FP_OP_D_INTERNAL( testnum, flags, double result, val1, 0.0, 0.0, \ + inst f3, f0; fmv.x.d a0, f3) + +#define TEST_FP_OP1_S_DWORD_RESULT( testnum, inst, flags, result, val1 ) \ + TEST_FP_OP_S_INTERNAL( testnum, flags, dword result, val1, 0.0, 0.0, \ + inst f3, f0; fmv.x.s a0, f3) + +#define TEST_FP_OP1_H_DWORD_RESULT( testnum, inst, flags, result, val1 ) \ + TEST_FP_OP_H_INTERNAL( testnum, flags, word result, val1, 0.0, 0.0, \ + inst f3, f0; fmv.x.h a0, f3) + +#define TEST_FP_OP1_D32_DWORD_RESULT( testnum, inst, flags, result, val1 ) \ + TEST_FP_OP_D32_INTERNAL( testnum, flags, dword result, val1, 0.0, 0.0, \ + inst f3, f0; fsd f3, 0(a0); lw t2, 4(a0); lw a0, 0(a0)) +// ^: store computation result in address from a0, load high-word into t2 + +#define TEST_FP_OP1_D_DWORD_RESULT( testnum, inst, flags, result, val1 ) \ + TEST_FP_OP_D_INTERNAL( testnum, flags, dword result, val1, 0.0, 0.0, \ + inst f3, f0; fmv.x.d a0, f3) + +#define TEST_FP_OP2_S( testnum, inst, flags, result, val1, val2 ) \ + TEST_FP_OP_S_INTERNAL( testnum, flags, float result, val1, val2, 0.0, \ + inst f3, f0, f1; fmv.x.s a0, f3) + +#define TEST_FP_OP2_H( testnum, inst, flags, result, val1, val2 ) \ + TEST_FP_OP_H_INTERNAL( testnum, flags, float16 result, val1, val2, 0.0, \ + inst f3, f0, f1; fmv.x.h a0, f3) + +#define TEST_FP_OP2_D32( testnum, inst, flags, result, val1, val2 ) \ + TEST_FP_OP_D32_INTERNAL( testnum, flags, double result, val1, val2, 0.0, \ + inst f3, f0, f1; fsd f3, 0(a0); lw t2, 4(a0); lw a0, 0(a0)) +// ^: store computation result in address from a0, load high-word into t2 + +#define TEST_FP_OP2_D( testnum, inst, flags, result, val1, val2 ) \ + TEST_FP_OP_D_INTERNAL( testnum, flags, double result, val1, val2, 0.0, \ + inst f3, f0, f1; fmv.x.d a0, f3) + +#define TEST_FP_OP3_S( testnum, inst, flags, result, val1, val2, val3 ) \ + TEST_FP_OP_S_INTERNAL( testnum, flags, float result, val1, val2, val3, \ + inst f3, f0, f1, f2; fmv.x.s a0, f3) + +#define TEST_FP_OP3_H( testnum, inst, flags, result, val1, val2, val3 ) \ + TEST_FP_OP_H_INTERNAL( testnum, flags, float16 result, val1, val2, val3, \ + inst f3, f0, f1, f2; fmv.x.h a0, f3) + +#define TEST_FP_OP3_D32( testnum, inst, flags, result, val1, val2, val3 ) \ + TEST_FP_OP_D32_INTERNAL( testnum, flags, double result, val1, val2, val3, \ + inst f3, f0, f1, f2; fsd f3, 0(a0); lw t2, 4(a0); lw a0, 0(a0)) +// ^: store computation result in address from a0, load high-word into t2 + +#define TEST_FP_OP3_D( testnum, inst, flags, result, val1, val2, val3 ) \ + TEST_FP_OP_D_INTERNAL( testnum, flags, double result, val1, val2, val3, \ + inst f3, f0, f1, f2; fmv.x.d a0, f3) + +#define TEST_FP_INT_OP_S( testnum, inst, flags, result, val1, rm ) \ + TEST_FP_OP_S_INTERNAL( testnum, flags, word result, val1, 0.0, 0.0, \ + inst a0, f0, rm) + +#define TEST_FP_INT_OP_H( testnum, inst, flags, result, val1, rm ) \ + TEST_FP_OP_H_INTERNAL( testnum, flags, word result, val1, 0.0, 0.0, \ + inst a0, f0, rm) + +#define TEST_FP_INT_OP_D32( testnum, inst, flags, result, val1, rm ) \ + TEST_FP_OP_D32_INTERNAL( testnum, flags, dword result, val1, 0.0, 0.0, \ + inst a0, f0, f1; li t2, 0) + +#define TEST_FP_INT_OP_D( testnum, inst, flags, result, val1, rm ) \ + TEST_FP_OP_D_INTERNAL( testnum, flags, dword result, val1, 0.0, 0.0, \ + inst a0, f0, rm) + +#define TEST_FP_CMP_OP_S( testnum, inst, flags, result, val1, val2 ) \ + TEST_FP_OP_S_INTERNAL( testnum, flags, word result, val1, val2, 0.0, \ + inst a0, f0, f1) + +#define TEST_FP_CMP_OP_H( testnum, inst, flags, result, val1, val2 ) \ + TEST_FP_OP_H_INTERNAL( testnum, flags, hword result, val1, val2, 0.0, \ + inst a0, f0, f1) + +#define TEST_FP_CMP_OP_D32( testnum, inst, flags, result, val1, val2 ) \ + TEST_FP_OP_D32_INTERNAL( testnum, flags, dword result, val1, val2, 0.0, \ + inst a0, f0, f1; li t2, 0) + +#define TEST_FP_CMP_OP_D( testnum, inst, flags, result, val1, val2 ) \ + TEST_FP_OP_D_INTERNAL( testnum, flags, dword result, val1, val2, 0.0, \ + inst a0, f0, f1) + +#define TEST_FCLASS_S(testnum, correct, input) \ + TEST_CASE(testnum, a0, correct, li a0, input; fmv.s.x fa0, a0; \ + fclass.s a0, fa0) + +#define TEST_FCLASS_D32(testnum, correct, input) \ + TEST_CASE(testnum, a0, correct, \ + la a0, test_ ## testnum ## _data ;\ + fld fa0, 0(a0); \ + fclass.d a0, fa0) \ + .pushsection .data; \ + .align 3; \ + test_ ## testnum ## _data: \ + .dword input; \ + .popsection + +#define TEST_FCLASS_D(testnum, correct, input) \ + TEST_CASE(testnum, a0, correct, li a0, input; fmv.d.x fa0, a0; \ + fclass.d a0, fa0) + +#define TEST_INT_FP_OP_S( testnum, inst, result, val1 ) \ +test_ ## testnum: \ + li TESTNUM, testnum; \ + la a0, test_ ## testnum ## _data ;\ + lw a3, 0(a0); \ + li a0, val1; \ + inst f0, a0; \ + fsflags x0; \ + fmv.x.s a0, f0; \ + bne a0, a3, fail; \ + .pushsection .data; \ + .align 2; \ + test_ ## testnum ## _data: \ + .float result; \ + .popsection + +#define TEST_INT_FP_OP_H( testnum, inst, result, val1 ) \ +test_ ## testnum: \ + li TESTNUM, testnum; \ + la a0, test_ ## testnum ## _data ;\ + lh a3, 0(a0); \ + li a0, val1; \ + inst f0, a0; \ + fsflags x0; \ + fmv.x.h a0, f0; \ + bne a0, a3, fail; \ + .pushsection .data; \ + .align 1; \ + test_ ## testnum ## _data: \ + .float16 result; \ + .popsection + +#define TEST_INT_FP_OP_D32( testnum, inst, result, val1 ) \ +test_ ## testnum: \ + li TESTNUM, testnum; \ + la a0, test_ ## testnum ## _data ;\ + lw a3, 0(a0); \ + lw a4, 4(a0); \ + li a1, val1; \ + inst f0, a1; \ + \ + fsd f0, 0(a0); \ + lw a1, 4(a0); \ + lw a0, 0(a0); \ + \ + fsflags x0; \ + bne a0, a3, fail; \ + bne a1, a4, fail; \ + .pushsection .data; \ + .align 3; \ + test_ ## testnum ## _data: \ + .double result; \ + .popsection + +#define TEST_INT_FP_OP_D( testnum, inst, result, val1 ) \ +test_ ## testnum: \ + li TESTNUM, testnum; \ + la a0, test_ ## testnum ## _data ;\ + ld a3, 0(a0); \ + li a0, val1; \ + inst f0, a0; \ + fsflags x0; \ + fmv.x.d a0, f0; \ + bne a0, a3, fail; \ + .pushsection .data; \ + .align 3; \ + test_ ## testnum ## _data: \ + .double result; \ + .popsection + +// We need some special handling here to allow 64-bit comparison in 32-bit arch +// TODO: find a better name and clean up when intended for general usage? +#define TEST_CASE_D32( testnum, testreg1, testreg2, correctval, code... ) \ +test_ ## testnum: \ + code; \ + la x15, test_ ## testnum ## _data ; \ + lw x7, 0(x15); \ + lw x15, 4(x15); \ + li TESTNUM, testnum; \ + bne testreg1, x7, fail;\ + bne testreg2, x15, fail;\ + .pushsection .data; \ + .align 3; \ + test_ ## testnum ## _data: \ + .dword correctval; \ + .popsection + +// ^ x14 is used in some other macros, to avoid issues we use x15 for upper word + +#define MISALIGNED_LOAD_HANDLER \ + li t0, CAUSE_MISALIGNED_LOAD; \ + csrr t1, mcause; \ + bne t0, t1, fail; \ + \ + /* We got a misaligned exception. Pretend we handled it in software */ \ + /* by loading the correct result here. */ \ + mv a4, a5; \ + \ + /* And skip this instruction */ \ + csrr t0, mepc; \ + addi t0, t0, 4; \ + csrw mepc, t0; \ + mret + +#define MISALIGNED_STORE_HANDLER \ + li t0, CAUSE_MISALIGNED_STORE; \ + csrr t1, mcause; \ + bne t0, t1, fail; \ + \ + /* We got a misaligned exception. Skip this test. */ \ + csrw mepc, x15; \ + mret + +#----------------------------------------------------------------------- +# Pass and fail code (assumes test num is in TESTNUM) +#----------------------------------------------------------------------- + +#define TEST_PASSFAIL \ + bne x0, TESTNUM, pass; \ +fail: \ + RVTEST_FAIL; \ +pass: \ + RVTEST_PASS \ + + +#----------------------------------------------------------------------- +# Test data section +#----------------------------------------------------------------------- + +#define TEST_DATA + +#endif diff --git a/tb/qumcu/isa/rv32mi/Makefrag b/tb/qumcu/isa/rv32mi/Makefrag new file mode 100644 index 0000000..d871990 --- /dev/null +++ b/tb/qumcu/isa/rv32mi/Makefrag @@ -0,0 +1,21 @@ +#======================================================================= +# Makefrag for rv32mi tests +#----------------------------------------------------------------------- + +rv32mi_sc_tests = \ + breakpoint \ + csr \ + mcsr \ + illegal \ + ma_fetch \ + ma_addr \ + scall \ + sbreak \ + shamt \ + lw-misaligned \ + lh-misaligned \ + sh-misaligned \ + sw-misaligned \ + zicntr \ + +rv32mi_p_tests = $(addprefix rv32mi-p-, $(rv32mi_sc_tests)) diff --git a/tb/qumcu/isa/rv32mi/breakpoint.S b/tb/qumcu/isa/rv32mi/breakpoint.S new file mode 100644 index 0000000..ecbec6a --- /dev/null +++ b/tb/qumcu/isa/rv32mi/breakpoint.S @@ -0,0 +1,8 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64M +#define RVTEST_RV64M RVTEST_RV32M +#define __MACHINE_MODE + +#include "../rv64mi/breakpoint.S" diff --git a/tb/qumcu/isa/rv32mi/csr.S b/tb/qumcu/isa/rv32mi/csr.S new file mode 100644 index 0000000..6361f86 --- /dev/null +++ b/tb/qumcu/isa/rv32mi/csr.S @@ -0,0 +1,8 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64S +#define RVTEST_RV64S RVTEST_RV32M +#define __MACHINE_MODE + +#include "../rv64si/csr.S" diff --git a/tb/qumcu/isa/rv32mi/illegal.S b/tb/qumcu/isa/rv32mi/illegal.S new file mode 100644 index 0000000..e167c71 --- /dev/null +++ b/tb/qumcu/isa/rv32mi/illegal.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64M +#define RVTEST_RV64M RVTEST_RV32M + +#include "../rv64mi/illegal.S" diff --git a/tb/qumcu/isa/rv32mi/lh-misaligned.S b/tb/qumcu/isa/rv32mi/lh-misaligned.S new file mode 100644 index 0000000..42755f5 --- /dev/null +++ b/tb/qumcu/isa/rv32mi/lh-misaligned.S @@ -0,0 +1,8 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64M +#define RVTEST_RV64M RVTEST_RV32M +#define __MACHINE_MODE + +#include "../rv64mi/lh-misaligned.S" diff --git a/tb/qumcu/isa/rv32mi/lw-misaligned.S b/tb/qumcu/isa/rv32mi/lw-misaligned.S new file mode 100644 index 0000000..0614aee --- /dev/null +++ b/tb/qumcu/isa/rv32mi/lw-misaligned.S @@ -0,0 +1,8 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64M +#define RVTEST_RV64M RVTEST_RV32M +#define __MACHINE_MODE + +#include "../rv64mi/lw-misaligned.S" diff --git a/tb/qumcu/isa/rv32mi/ma_addr.S b/tb/qumcu/isa/rv32mi/ma_addr.S new file mode 100644 index 0000000..7575a3f --- /dev/null +++ b/tb/qumcu/isa/rv32mi/ma_addr.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64M +#define RVTEST_RV64M RVTEST_RV32M + +#include "../rv64mi/ma_addr.S" diff --git a/tb/qumcu/isa/rv32mi/ma_fetch.S b/tb/qumcu/isa/rv32mi/ma_fetch.S new file mode 100644 index 0000000..ec0e0f6 --- /dev/null +++ b/tb/qumcu/isa/rv32mi/ma_fetch.S @@ -0,0 +1,8 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64S +#define RVTEST_RV64S RVTEST_RV32M +#define __MACHINE_MODE + +#include "../rv64si/ma_fetch.S" diff --git a/tb/qumcu/isa/rv32mi/mcsr.S b/tb/qumcu/isa/rv32mi/mcsr.S new file mode 100644 index 0000000..0d5a5cd --- /dev/null +++ b/tb/qumcu/isa/rv32mi/mcsr.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64M +#define RVTEST_RV64M RVTEST_RV32M + +#include "../rv64mi/mcsr.S" diff --git a/tb/qumcu/isa/rv32mi/sbreak.S b/tb/qumcu/isa/rv32mi/sbreak.S new file mode 100644 index 0000000..c1b127d --- /dev/null +++ b/tb/qumcu/isa/rv32mi/sbreak.S @@ -0,0 +1,8 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64S +#define RVTEST_RV64S RVTEST_RV32M +#define __MACHINE_MODE + +#include "../rv64si/sbreak.S" diff --git a/tb/qumcu/isa/rv32mi/scall.S b/tb/qumcu/isa/rv32mi/scall.S new file mode 100644 index 0000000..e5b3153 --- /dev/null +++ b/tb/qumcu/isa/rv32mi/scall.S @@ -0,0 +1,8 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64S +#define RVTEST_RV64S RVTEST_RV32M +#define __MACHINE_MODE + +#include "../rv64si/scall.S" diff --git a/tb/qumcu/isa/rv32mi/sh-misaligned.S b/tb/qumcu/isa/rv32mi/sh-misaligned.S new file mode 100644 index 0000000..b2fb4f5 --- /dev/null +++ b/tb/qumcu/isa/rv32mi/sh-misaligned.S @@ -0,0 +1,8 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64M +#define RVTEST_RV64M RVTEST_RV32M +#define __MACHINE_MODE + +#include "../rv64mi/sh-misaligned.S" diff --git a/tb/qumcu/isa/rv32mi/shamt.S b/tb/qumcu/isa/rv32mi/shamt.S new file mode 100644 index 0000000..89a07ee --- /dev/null +++ b/tb/qumcu/isa/rv32mi/shamt.S @@ -0,0 +1,44 @@ +# See LICENSE for license details. + +#***************************************************************************** +# shamt.S +#----------------------------------------------------------------------------- +# +# Test illegal shamt[5] of shift instruction in 32-bit ISA. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32M +RVTEST_CODE_BEGIN + + # Make sure slli with shamt[4] set is legal. + TEST_CASE( 2, a0, 65536, li a0, 1; slli a0, a0, 16); + + # Make sure slli with shamt[5] set is not legal. + TEST_CASE( 3, x0, 1, .word 0x02051513); # slli a0, a0, 32 + + TEST_PASSFAIL + +.align 2 +.global mtvec_handler +mtvec_handler: + # Trapping on test 3 is good. + li t0, 3 + bne TESTNUM, t0, fail + + # Make sure CAUSE indicates an illegal instructino. + csrr t0, mcause + li t1, CAUSE_ILLEGAL_INSTRUCTION + bne t0, t1, fail + j pass + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv32mi/sw-misaligned.S b/tb/qumcu/isa/rv32mi/sw-misaligned.S new file mode 100644 index 0000000..94edd9f --- /dev/null +++ b/tb/qumcu/isa/rv32mi/sw-misaligned.S @@ -0,0 +1,8 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64M +#define RVTEST_RV64M RVTEST_RV32M +#define __MACHINE_MODE + +#include "../rv64mi/sw-misaligned.S" diff --git a/tb/qumcu/isa/rv32mi/zicntr.S b/tb/qumcu/isa/rv32mi/zicntr.S new file mode 100644 index 0000000..17e5f48 --- /dev/null +++ b/tb/qumcu/isa/rv32mi/zicntr.S @@ -0,0 +1,8 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64M +#define RVTEST_RV64M RVTEST_RV32M +#define __MACHINE_MODE + +#include "../rv64mi/zicntr.S" diff --git a/tb/qumcu/isa/rv32si/Makefrag b/tb/qumcu/isa/rv32si/Makefrag new file mode 100644 index 0000000..1392c24 --- /dev/null +++ b/tb/qumcu/isa/rv32si/Makefrag @@ -0,0 +1,13 @@ +#======================================================================= +# Makefrag for rv32si tests +#----------------------------------------------------------------------- + +rv32si_sc_tests = \ + csr \ + dirty \ + ma_fetch \ + scall \ + sbreak \ + wfi \ + +rv32si_p_tests = $(addprefix rv32si-p-, $(rv32si_sc_tests)) diff --git a/tb/qumcu/isa/rv32si/csr.S b/tb/qumcu/isa/rv32si/csr.S new file mode 100644 index 0000000..3c414c0 --- /dev/null +++ b/tb/qumcu/isa/rv32si/csr.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64S +#define RVTEST_RV64S RVTEST_RV32S + +#include "../rv64si/csr.S" diff --git a/tb/qumcu/isa/rv32si/dirty.S b/tb/qumcu/isa/rv32si/dirty.S new file mode 100644 index 0000000..bdbc1e4 --- /dev/null +++ b/tb/qumcu/isa/rv32si/dirty.S @@ -0,0 +1,10 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64M +#define RVTEST_RV64M RVTEST_RV32M + +#undef SATP_MODE_SV39 +#define SATP_MODE_SV39 SATP_MODE_SV32 + +#include "../rv64si/dirty.S" diff --git a/tb/qumcu/isa/rv32si/ma_fetch.S b/tb/qumcu/isa/rv32si/ma_fetch.S new file mode 100644 index 0000000..2e5254f --- /dev/null +++ b/tb/qumcu/isa/rv32si/ma_fetch.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64S +#define RVTEST_RV64S RVTEST_RV32S + +#include "../rv64si/ma_fetch.S" diff --git a/tb/qumcu/isa/rv32si/sbreak.S b/tb/qumcu/isa/rv32si/sbreak.S new file mode 100644 index 0000000..3dcfba2 --- /dev/null +++ b/tb/qumcu/isa/rv32si/sbreak.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64S +#define RVTEST_RV64S RVTEST_RV32S + +#include "../rv64si/sbreak.S" diff --git a/tb/qumcu/isa/rv32si/scall.S b/tb/qumcu/isa/rv32si/scall.S new file mode 100644 index 0000000..5b732c8 --- /dev/null +++ b/tb/qumcu/isa/rv32si/scall.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64S +#define RVTEST_RV64S RVTEST_RV32S + +#include "../rv64si/scall.S" diff --git a/tb/qumcu/isa/rv32si/wfi.S b/tb/qumcu/isa/rv32si/wfi.S new file mode 100644 index 0000000..8bc9279 --- /dev/null +++ b/tb/qumcu/isa/rv32si/wfi.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64S +#define RVTEST_RV64S RVTEST_RV32S + +#include "../rv64si/wfi.S" diff --git a/tb/qumcu/isa/rv32ua/Makefrag b/tb/qumcu/isa/rv32ua/Makefrag new file mode 100644 index 0000000..3f35810 --- /dev/null +++ b/tb/qumcu/isa/rv32ua/Makefrag @@ -0,0 +1,10 @@ +#======================================================================= +# Makefrag for rv32ua tests +#----------------------------------------------------------------------- + +rv32ua_sc_tests = \ + amoadd_w amoand_w amomax_w amomaxu_w amomin_w amominu_w amoor_w amoxor_w amoswap_w \ + lrsc \ + +rv32ua_p_tests = $(addprefix rv32ua-p-, $(rv32ua_sc_tests)) +rv32ua_v_tests = $(addprefix rv32ua-v-, $(rv32ua_sc_tests)) diff --git a/tb/qumcu/isa/rv32ua/amoadd_w.S b/tb/qumcu/isa/rv32ua/amoadd_w.S new file mode 100644 index 0000000..df4560d --- /dev/null +++ b/tb/qumcu/isa/rv32ua/amoadd_w.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64ua/amoadd_w.S" diff --git a/tb/qumcu/isa/rv32ua/amoand_w.S b/tb/qumcu/isa/rv32ua/amoand_w.S new file mode 100644 index 0000000..b824483 --- /dev/null +++ b/tb/qumcu/isa/rv32ua/amoand_w.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64ua/amoand_w.S" diff --git a/tb/qumcu/isa/rv32ua/amomax_w.S b/tb/qumcu/isa/rv32ua/amomax_w.S new file mode 100644 index 0000000..899d7d6 --- /dev/null +++ b/tb/qumcu/isa/rv32ua/amomax_w.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64ua/amomax_w.S" diff --git a/tb/qumcu/isa/rv32ua/amomaxu_w.S b/tb/qumcu/isa/rv32ua/amomaxu_w.S new file mode 100644 index 0000000..662f023 --- /dev/null +++ b/tb/qumcu/isa/rv32ua/amomaxu_w.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64ua/amomaxu_w.S" diff --git a/tb/qumcu/isa/rv32ua/amomin_w.S b/tb/qumcu/isa/rv32ua/amomin_w.S new file mode 100644 index 0000000..cbd88e6 --- /dev/null +++ b/tb/qumcu/isa/rv32ua/amomin_w.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64ua/amomin_w.S" diff --git a/tb/qumcu/isa/rv32ua/amominu_w.S b/tb/qumcu/isa/rv32ua/amominu_w.S new file mode 100644 index 0000000..acb0d79 --- /dev/null +++ b/tb/qumcu/isa/rv32ua/amominu_w.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64ua/amominu_w.S" diff --git a/tb/qumcu/isa/rv32ua/amoor_w.S b/tb/qumcu/isa/rv32ua/amoor_w.S new file mode 100644 index 0000000..0a2a57d --- /dev/null +++ b/tb/qumcu/isa/rv32ua/amoor_w.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64ua/amoor_w.S" diff --git a/tb/qumcu/isa/rv32ua/amoswap_w.S b/tb/qumcu/isa/rv32ua/amoswap_w.S new file mode 100644 index 0000000..722b7bc --- /dev/null +++ b/tb/qumcu/isa/rv32ua/amoswap_w.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64ua/amoswap_w.S" diff --git a/tb/qumcu/isa/rv32ua/amoxor_w.S b/tb/qumcu/isa/rv32ua/amoxor_w.S new file mode 100644 index 0000000..1858d7e --- /dev/null +++ b/tb/qumcu/isa/rv32ua/amoxor_w.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64ua/amoxor_w.S" diff --git a/tb/qumcu/isa/rv32ua/lrsc.S b/tb/qumcu/isa/rv32ua/lrsc.S new file mode 100644 index 0000000..695a5c8 --- /dev/null +++ b/tb/qumcu/isa/rv32ua/lrsc.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64ua/lrsc.S" diff --git a/tb/qumcu/isa/rv32uc/Makefrag b/tb/qumcu/isa/rv32uc/Makefrag new file mode 100644 index 0000000..674ece8 --- /dev/null +++ b/tb/qumcu/isa/rv32uc/Makefrag @@ -0,0 +1,9 @@ +#======================================================================= +# Makefrag for rv32uc tests +#----------------------------------------------------------------------- + +rv32uc_sc_tests = \ + rvc \ + +rv32uc_p_tests = $(addprefix rv32uc-p-, $(rv32uc_sc_tests)) +rv32uc_v_tests = $(addprefix rv32uc-v-, $(rv32uc_sc_tests)) diff --git a/tb/qumcu/isa/rv32uc/rvc.S b/tb/qumcu/isa/rv32uc/rvc.S new file mode 100644 index 0000000..debbbd8 --- /dev/null +++ b/tb/qumcu/isa/rv32uc/rvc.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64uc/rvc.S" diff --git a/tb/qumcu/isa/rv32ud/Makefrag b/tb/qumcu/isa/rv32ud/Makefrag new file mode 100644 index 0000000..1a38cec --- /dev/null +++ b/tb/qumcu/isa/rv32ud/Makefrag @@ -0,0 +1,13 @@ +#======================================================================= +# Makefrag for rv32ud tests +#----------------------------------------------------------------------- + +rv32ud_sc_tests = \ + fadd fdiv fclass fcmp fcvt fcvt_w fmadd fmin \ + ldst recoding \ + +# TODO: use this line instead of the last of the previous once move and structural tests have been implemented +# ldst move structural recoding \ + +rv32ud_p_tests = $(addprefix rv32ud-p-, $(rv32ud_sc_tests)) +rv32ud_v_tests = $(addprefix rv32ud-v-, $(rv32ud_sc_tests)) diff --git a/tb/qumcu/isa/rv32ud/fadd.S b/tb/qumcu/isa/rv32ud/fadd.S new file mode 100644 index 0000000..5fb9090 --- /dev/null +++ b/tb/qumcu/isa/rv32ud/fadd.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64UF +#define RVTEST_RV64UF RVTEST_RV32UF + +#include "../rv64ud/fadd.S" diff --git a/tb/qumcu/isa/rv32ud/fclass.S b/tb/qumcu/isa/rv32ud/fclass.S new file mode 100644 index 0000000..c960ad6 --- /dev/null +++ b/tb/qumcu/isa/rv32ud/fclass.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64UF +#define RVTEST_RV64UF RVTEST_RV32UF + +#include "../rv64ud/fclass.S" diff --git a/tb/qumcu/isa/rv32ud/fcmp.S b/tb/qumcu/isa/rv32ud/fcmp.S new file mode 100644 index 0000000..55d1c3a --- /dev/null +++ b/tb/qumcu/isa/rv32ud/fcmp.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64UF +#define RVTEST_RV64UF RVTEST_RV32UF + +#include "../rv64ud/fcmp.S" diff --git a/tb/qumcu/isa/rv32ud/fcvt.S b/tb/qumcu/isa/rv32ud/fcvt.S new file mode 100644 index 0000000..8811b6e --- /dev/null +++ b/tb/qumcu/isa/rv32ud/fcvt.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64UF +#define RVTEST_RV64UF RVTEST_RV32UF + +#include "../rv64ud/fcvt.S" diff --git a/tb/qumcu/isa/rv32ud/fcvt_w.S b/tb/qumcu/isa/rv32ud/fcvt_w.S new file mode 100644 index 0000000..3447530 --- /dev/null +++ b/tb/qumcu/isa/rv32ud/fcvt_w.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64UF +#define RVTEST_RV64UF RVTEST_RV32UF + +#include "../rv64uf/fcvt_w.S" diff --git a/tb/qumcu/isa/rv32ud/fdiv.S b/tb/qumcu/isa/rv32ud/fdiv.S new file mode 100644 index 0000000..793e51a --- /dev/null +++ b/tb/qumcu/isa/rv32ud/fdiv.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64UF +#define RVTEST_RV64UF RVTEST_RV32UF + +#include "../rv64ud/fdiv.S" diff --git a/tb/qumcu/isa/rv32ud/fmadd.S b/tb/qumcu/isa/rv32ud/fmadd.S new file mode 100644 index 0000000..e60934c --- /dev/null +++ b/tb/qumcu/isa/rv32ud/fmadd.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64UF +#define RVTEST_RV64UF RVTEST_RV32UF + +#include "../rv64ud/fmadd.S" diff --git a/tb/qumcu/isa/rv32ud/fmin.S b/tb/qumcu/isa/rv32ud/fmin.S new file mode 100644 index 0000000..c80c880 --- /dev/null +++ b/tb/qumcu/isa/rv32ud/fmin.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64UF +#define RVTEST_RV64UF RVTEST_RV32UF + +#include "../rv64ud/fmin.S" diff --git a/tb/qumcu/isa/rv32ud/ldst.S b/tb/qumcu/isa/rv32ud/ldst.S new file mode 100644 index 0000000..e39fe30 --- /dev/null +++ b/tb/qumcu/isa/rv32ud/ldst.S @@ -0,0 +1,42 @@ +# See LICENSE for license details. + +#***************************************************************************** +# ldst.S +#----------------------------------------------------------------------------- +# +# This test verifies that flw, fld, fsw, and fsd work properly. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32UF +RVTEST_CODE_BEGIN + + la s0, tdat + TEST_CASE_D32(2, a0, a1, 0x40000000bf800000, fld f2, 0(s0); fsd f2, 16(s0); lw a0, 16(s0); lw a1, 20(s0)) + TEST_CASE_D32(3, a0, a1, 0x40000000bf800000, fld f2, 0(s0); fsw f2, 16(s0); lw a0, 16(s0); lw a1, 20(s0)) + TEST_CASE_D32(4, a0, a1, 0x40000000bf800000, flw f2, 0(s0); fsw f2, 16(s0); lw a0, 16(s0); lw a1, 20(s0)) + TEST_CASE_D32(5, a0, a1, 0xc080000040400000, fld f2, 8(s0); fsd f2, 16(s0); lw a0, 16(s0); lw a1, 20(s0)) + TEST_CASE_D32(6, a0, a1, 0xffffffff40400000, flw f2, 8(s0); fsd f2, 16(s0); lw a0, 16(s0); lw a1, 20(s0)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +tdat: +.word 0xbf800000 +.word 0x40000000 +.word 0x40400000 +.word 0xc0800000 +.word 0xdeadbeef +.word 0xcafebabe +.word 0xabad1dea +.word 0x1337d00d + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv32ud/move.S b/tb/qumcu/isa/rv32ud/move.S new file mode 100644 index 0000000..4551ffd --- /dev/null +++ b/tb/qumcu/isa/rv32ud/move.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64UF +#define RVTEST_RV64UF RVTEST_RV32UF + +#include "../rv64ud/move.S" diff --git a/tb/qumcu/isa/rv32ud/recoding.S b/tb/qumcu/isa/rv32ud/recoding.S new file mode 100644 index 0000000..5dc0113 --- /dev/null +++ b/tb/qumcu/isa/rv32ud/recoding.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64UF +#define RVTEST_RV64UF RVTEST_RV32UF + +#include "../rv64uf/recoding.S" diff --git a/tb/qumcu/isa/rv32uf/Makefrag b/tb/qumcu/isa/rv32uf/Makefrag new file mode 100644 index 0000000..e82705f --- /dev/null +++ b/tb/qumcu/isa/rv32uf/Makefrag @@ -0,0 +1,10 @@ +#======================================================================= +# Makefrag for rv32uf tests +#----------------------------------------------------------------------- + +rv32uf_sc_tests = \ + fadd fdiv fclass fcmp fcvt fcvt_w fmadd fmin \ + ldst move recoding \ + +rv32uf_p_tests = $(addprefix rv32uf-p-, $(rv32uf_sc_tests)) +rv32uf_v_tests = $(addprefix rv32uf-v-, $(rv32uf_sc_tests)) diff --git a/tb/qumcu/isa/rv32uf/fadd.S b/tb/qumcu/isa/rv32uf/fadd.S new file mode 100644 index 0000000..b832c3d --- /dev/null +++ b/tb/qumcu/isa/rv32uf/fadd.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64UF +#define RVTEST_RV64UF RVTEST_RV32UF + +#include "../rv64uf/fadd.S" diff --git a/tb/qumcu/isa/rv32uf/fclass.S b/tb/qumcu/isa/rv32uf/fclass.S new file mode 100644 index 0000000..19bbcc5 --- /dev/null +++ b/tb/qumcu/isa/rv32uf/fclass.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64UF +#define RVTEST_RV64UF RVTEST_RV32UF + +#include "../rv64uf/fclass.S" diff --git a/tb/qumcu/isa/rv32uf/fcmp.S b/tb/qumcu/isa/rv32uf/fcmp.S new file mode 100644 index 0000000..2dbf451 --- /dev/null +++ b/tb/qumcu/isa/rv32uf/fcmp.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64UF +#define RVTEST_RV64UF RVTEST_RV32UF + +#include "../rv64uf/fcmp.S" diff --git a/tb/qumcu/isa/rv32uf/fcvt.S b/tb/qumcu/isa/rv32uf/fcvt.S new file mode 100644 index 0000000..627f1f2 --- /dev/null +++ b/tb/qumcu/isa/rv32uf/fcvt.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64UF +#define RVTEST_RV64UF RVTEST_RV32UF + +#include "../rv64uf/fcvt.S" diff --git a/tb/qumcu/isa/rv32uf/fcvt_w.S b/tb/qumcu/isa/rv32uf/fcvt_w.S new file mode 100644 index 0000000..3447530 --- /dev/null +++ b/tb/qumcu/isa/rv32uf/fcvt_w.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64UF +#define RVTEST_RV64UF RVTEST_RV32UF + +#include "../rv64uf/fcvt_w.S" diff --git a/tb/qumcu/isa/rv32uf/fdiv.S b/tb/qumcu/isa/rv32uf/fdiv.S new file mode 100644 index 0000000..12aaa3d --- /dev/null +++ b/tb/qumcu/isa/rv32uf/fdiv.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64UF +#define RVTEST_RV64UF RVTEST_RV32UF + +#include "../rv64uf/fdiv.S" diff --git a/tb/qumcu/isa/rv32uf/fmadd.S b/tb/qumcu/isa/rv32uf/fmadd.S new file mode 100644 index 0000000..8a5aacb --- /dev/null +++ b/tb/qumcu/isa/rv32uf/fmadd.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64UF +#define RVTEST_RV64UF RVTEST_RV32UF + +#include "../rv64uf/fmadd.S" diff --git a/tb/qumcu/isa/rv32uf/fmin.S b/tb/qumcu/isa/rv32uf/fmin.S new file mode 100644 index 0000000..9231d01 --- /dev/null +++ b/tb/qumcu/isa/rv32uf/fmin.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64UF +#define RVTEST_RV64UF RVTEST_RV32UF + +#include "../rv64uf/fmin.S" diff --git a/tb/qumcu/isa/rv32uf/ldst.S b/tb/qumcu/isa/rv32uf/ldst.S new file mode 100644 index 0000000..01f7fef --- /dev/null +++ b/tb/qumcu/isa/rv32uf/ldst.S @@ -0,0 +1,38 @@ +# See LICENSE for license details. + +#***************************************************************************** +# ldst.S +#----------------------------------------------------------------------------- +# +# This test verifies that flw, fld, fsw, and fsd work properly. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32UF +RVTEST_CODE_BEGIN + + TEST_CASE(2, a0, 0x40000000, la a1, tdat; flw f1, 4(a1); fsw f1, 20(a1); lw a0, 20(a1)) + TEST_CASE(3, a0, 0xbf800000, la a1, tdat; flw f1, 0(a1); fsw f1, 24(a1); lw a0, 24(a1)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +tdat: +.word 0xbf800000 +.word 0x40000000 +.word 0x40400000 +.word 0xc0800000 +.word 0xdeadbeef +.word 0xcafebabe +.word 0xabad1dea +.word 0x1337d00d + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv32uf/move.S b/tb/qumcu/isa/rv32uf/move.S new file mode 100644 index 0000000..949da6f --- /dev/null +++ b/tb/qumcu/isa/rv32uf/move.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64UF +#define RVTEST_RV64UF RVTEST_RV32UF + +#include "../rv64uf/move.S" diff --git a/tb/qumcu/isa/rv32uf/recoding.S b/tb/qumcu/isa/rv32uf/recoding.S new file mode 100644 index 0000000..5dc0113 --- /dev/null +++ b/tb/qumcu/isa/rv32uf/recoding.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64UF +#define RVTEST_RV64UF RVTEST_RV32UF + +#include "../rv64uf/recoding.S" diff --git a/tb/qumcu/isa/rv32ui/Makefrag b/tb/qumcu/isa/rv32ui/Makefrag new file mode 100644 index 0000000..b7d85e1 --- /dev/null +++ b/tb/qumcu/isa/rv32ui/Makefrag @@ -0,0 +1,26 @@ +#======================================================================= +# Makefrag for rv32ui tests +#----------------------------------------------------------------------- + +rv32ui_sc_tests = \ + simple \ + add addi \ + and andi \ + auipc \ + beq bge bgeu blt bltu bne \ + fence_i \ + jal jalr \ + lb lbu lh lhu lw \ + lui \ + ma_data \ + or ori \ + sb sh sw \ + sll slli \ + slt slti sltiu sltu \ + sra srai \ + srl srli \ + sub \ + xor xori \ + +rv32ui_p_tests = $(addprefix rv32ui-p-, $(rv32ui_sc_tests)) +rv32ui_v_tests = $(addprefix rv32ui-v-, $(rv32ui_sc_tests)) diff --git a/tb/qumcu/isa/rv32ui/add.S b/tb/qumcu/isa/rv32ui/add.S new file mode 100644 index 0000000..3ab883d --- /dev/null +++ b/tb/qumcu/isa/rv32ui/add.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64ui/add.S" diff --git a/tb/qumcu/isa/rv32ui/addi.S b/tb/qumcu/isa/rv32ui/addi.S new file mode 100644 index 0000000..fa80a68 --- /dev/null +++ b/tb/qumcu/isa/rv32ui/addi.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64ui/addi.S" diff --git a/tb/qumcu/isa/rv32ui/and.S b/tb/qumcu/isa/rv32ui/and.S new file mode 100644 index 0000000..4ee105b --- /dev/null +++ b/tb/qumcu/isa/rv32ui/and.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64ui/and.S" diff --git a/tb/qumcu/isa/rv32ui/andi.S b/tb/qumcu/isa/rv32ui/andi.S new file mode 100644 index 0000000..e6b1529 --- /dev/null +++ b/tb/qumcu/isa/rv32ui/andi.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64ui/andi.S" diff --git a/tb/qumcu/isa/rv32ui/auipc.S b/tb/qumcu/isa/rv32ui/auipc.S new file mode 100644 index 0000000..0827f7d --- /dev/null +++ b/tb/qumcu/isa/rv32ui/auipc.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64ui/auipc.S" diff --git a/tb/qumcu/isa/rv32ui/beq.S b/tb/qumcu/isa/rv32ui/beq.S new file mode 100644 index 0000000..7c3996d --- /dev/null +++ b/tb/qumcu/isa/rv32ui/beq.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64ui/beq.S" diff --git a/tb/qumcu/isa/rv32ui/bge.S b/tb/qumcu/isa/rv32ui/bge.S new file mode 100644 index 0000000..d47c304 --- /dev/null +++ b/tb/qumcu/isa/rv32ui/bge.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64ui/bge.S" diff --git a/tb/qumcu/isa/rv32ui/bgeu.S b/tb/qumcu/isa/rv32ui/bgeu.S new file mode 100644 index 0000000..560ec45 --- /dev/null +++ b/tb/qumcu/isa/rv32ui/bgeu.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64ui/bgeu.S" diff --git a/tb/qumcu/isa/rv32ui/blt.S b/tb/qumcu/isa/rv32ui/blt.S new file mode 100644 index 0000000..72017dd --- /dev/null +++ b/tb/qumcu/isa/rv32ui/blt.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64ui/blt.S" diff --git a/tb/qumcu/isa/rv32ui/bltu.S b/tb/qumcu/isa/rv32ui/bltu.S new file mode 100644 index 0000000..80f7468 --- /dev/null +++ b/tb/qumcu/isa/rv32ui/bltu.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64ui/bltu.S" diff --git a/tb/qumcu/isa/rv32ui/bne.S b/tb/qumcu/isa/rv32ui/bne.S new file mode 100644 index 0000000..ddb7d9f --- /dev/null +++ b/tb/qumcu/isa/rv32ui/bne.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64ui/bne.S" diff --git a/tb/qumcu/isa/rv32ui/fence_i.S b/tb/qumcu/isa/rv32ui/fence_i.S new file mode 100644 index 0000000..cd1dbc3 --- /dev/null +++ b/tb/qumcu/isa/rv32ui/fence_i.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64ui/fence_i.S" diff --git a/tb/qumcu/isa/rv32ui/jal.S b/tb/qumcu/isa/rv32ui/jal.S new file mode 100644 index 0000000..93f407b --- /dev/null +++ b/tb/qumcu/isa/rv32ui/jal.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64ui/jal.S" diff --git a/tb/qumcu/isa/rv32ui/jalr.S b/tb/qumcu/isa/rv32ui/jalr.S new file mode 100644 index 0000000..59f6425 --- /dev/null +++ b/tb/qumcu/isa/rv32ui/jalr.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64ui/jalr.S" diff --git a/tb/qumcu/isa/rv32ui/lb.S b/tb/qumcu/isa/rv32ui/lb.S new file mode 100644 index 0000000..6cf4d44 --- /dev/null +++ b/tb/qumcu/isa/rv32ui/lb.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64ui/lb.S" diff --git a/tb/qumcu/isa/rv32ui/lbu.S b/tb/qumcu/isa/rv32ui/lbu.S new file mode 100644 index 0000000..a479a0f --- /dev/null +++ b/tb/qumcu/isa/rv32ui/lbu.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64ui/lbu.S" diff --git a/tb/qumcu/isa/rv32ui/lh.S b/tb/qumcu/isa/rv32ui/lh.S new file mode 100644 index 0000000..f1b2390 --- /dev/null +++ b/tb/qumcu/isa/rv32ui/lh.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64ui/lh.S" diff --git a/tb/qumcu/isa/rv32ui/lhu.S b/tb/qumcu/isa/rv32ui/lhu.S new file mode 100644 index 0000000..775765f --- /dev/null +++ b/tb/qumcu/isa/rv32ui/lhu.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64ui/lhu.S" diff --git a/tb/qumcu/isa/rv32ui/lui.S b/tb/qumcu/isa/rv32ui/lui.S new file mode 100644 index 0000000..a127d61 --- /dev/null +++ b/tb/qumcu/isa/rv32ui/lui.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64ui/lui.S" diff --git a/tb/qumcu/isa/rv32ui/lw.S b/tb/qumcu/isa/rv32ui/lw.S new file mode 100644 index 0000000..3b747d8 --- /dev/null +++ b/tb/qumcu/isa/rv32ui/lw.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64ui/lw.S" diff --git a/tb/qumcu/isa/rv32ui/ma_data.S b/tb/qumcu/isa/rv32ui/ma_data.S new file mode 100644 index 0000000..ea1ed11 --- /dev/null +++ b/tb/qumcu/isa/rv32ui/ma_data.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64ui/ma_data.S" diff --git a/tb/qumcu/isa/rv32ui/or.S b/tb/qumcu/isa/rv32ui/or.S new file mode 100644 index 0000000..1cf5674 --- /dev/null +++ b/tb/qumcu/isa/rv32ui/or.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64ui/or.S" diff --git a/tb/qumcu/isa/rv32ui/ori.S b/tb/qumcu/isa/rv32ui/ori.S new file mode 100644 index 0000000..3399649 --- /dev/null +++ b/tb/qumcu/isa/rv32ui/ori.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64ui/ori.S" diff --git a/tb/qumcu/isa/rv32ui/sb.S b/tb/qumcu/isa/rv32ui/sb.S new file mode 100644 index 0000000..b2f99ac --- /dev/null +++ b/tb/qumcu/isa/rv32ui/sb.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64ui/sb.S" diff --git a/tb/qumcu/isa/rv32ui/sh.S b/tb/qumcu/isa/rv32ui/sh.S new file mode 100644 index 0000000..eb5a72d --- /dev/null +++ b/tb/qumcu/isa/rv32ui/sh.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64ui/sh.S" diff --git a/tb/qumcu/isa/rv32ui/simple.S b/tb/qumcu/isa/rv32ui/simple.S new file mode 100644 index 0000000..20e5546 --- /dev/null +++ b/tb/qumcu/isa/rv32ui/simple.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64ui/simple.S" diff --git a/tb/qumcu/isa/rv32ui/sll.S b/tb/qumcu/isa/rv32ui/sll.S new file mode 100644 index 0000000..237df9e --- /dev/null +++ b/tb/qumcu/isa/rv32ui/sll.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64ui/sll.S" diff --git a/tb/qumcu/isa/rv32ui/slli.S b/tb/qumcu/isa/rv32ui/slli.S new file mode 100644 index 0000000..5f950e1 --- /dev/null +++ b/tb/qumcu/isa/rv32ui/slli.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64ui/slli.S" diff --git a/tb/qumcu/isa/rv32ui/slt.S b/tb/qumcu/isa/rv32ui/slt.S new file mode 100644 index 0000000..64a3dd9 --- /dev/null +++ b/tb/qumcu/isa/rv32ui/slt.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64ui/slt.S" diff --git a/tb/qumcu/isa/rv32ui/slti.S b/tb/qumcu/isa/rv32ui/slti.S new file mode 100644 index 0000000..7484505 --- /dev/null +++ b/tb/qumcu/isa/rv32ui/slti.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64ui/slti.S" diff --git a/tb/qumcu/isa/rv32ui/sltiu.S b/tb/qumcu/isa/rv32ui/sltiu.S new file mode 100644 index 0000000..4185f9b --- /dev/null +++ b/tb/qumcu/isa/rv32ui/sltiu.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64ui/sltiu.S" diff --git a/tb/qumcu/isa/rv32ui/sltu.S b/tb/qumcu/isa/rv32ui/sltu.S new file mode 100644 index 0000000..bd92b26 --- /dev/null +++ b/tb/qumcu/isa/rv32ui/sltu.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64ui/sltu.S" diff --git a/tb/qumcu/isa/rv32ui/sra.S b/tb/qumcu/isa/rv32ui/sra.S new file mode 100644 index 0000000..08abe19 --- /dev/null +++ b/tb/qumcu/isa/rv32ui/sra.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64ui/sra.S" diff --git a/tb/qumcu/isa/rv32ui/srai.S b/tb/qumcu/isa/rv32ui/srai.S new file mode 100644 index 0000000..b62a880 --- /dev/null +++ b/tb/qumcu/isa/rv32ui/srai.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64ui/srai.S" diff --git a/tb/qumcu/isa/rv32ui/srl.S b/tb/qumcu/isa/rv32ui/srl.S new file mode 100644 index 0000000..c0ac841 --- /dev/null +++ b/tb/qumcu/isa/rv32ui/srl.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64ui/srl.S" diff --git a/tb/qumcu/isa/rv32ui/srli.S b/tb/qumcu/isa/rv32ui/srli.S new file mode 100644 index 0000000..ef0203b --- /dev/null +++ b/tb/qumcu/isa/rv32ui/srli.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64ui/srli.S" diff --git a/tb/qumcu/isa/rv32ui/sub.S b/tb/qumcu/isa/rv32ui/sub.S new file mode 100644 index 0000000..330f478 --- /dev/null +++ b/tb/qumcu/isa/rv32ui/sub.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64ui/sub.S" diff --git a/tb/qumcu/isa/rv32ui/sw.S b/tb/qumcu/isa/rv32ui/sw.S new file mode 100644 index 0000000..3098133 --- /dev/null +++ b/tb/qumcu/isa/rv32ui/sw.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64ui/sw.S" diff --git a/tb/qumcu/isa/rv32ui/xor.S b/tb/qumcu/isa/rv32ui/xor.S new file mode 100644 index 0000000..a9c1e41 --- /dev/null +++ b/tb/qumcu/isa/rv32ui/xor.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64ui/xor.S" diff --git a/tb/qumcu/isa/rv32ui/xori.S b/tb/qumcu/isa/rv32ui/xori.S new file mode 100644 index 0000000..9e71152 --- /dev/null +++ b/tb/qumcu/isa/rv32ui/xori.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64ui/xori.S" diff --git a/tb/qumcu/isa/rv32um/Makefrag b/tb/qumcu/isa/rv32um/Makefrag new file mode 100644 index 0000000..688cb5a --- /dev/null +++ b/tb/qumcu/isa/rv32um/Makefrag @@ -0,0 +1,11 @@ +#======================================================================= +# Makefrag for rv32um tests +#----------------------------------------------------------------------- + +rv32um_sc_tests = \ + div divu \ + mul mulh mulhsu mulhu \ + rem remu \ + +rv32um_p_tests = $(addprefix rv32um-p-, $(rv32um_sc_tests)) +rv32um_v_tests = $(addprefix rv32um-v-, $(rv32um_sc_tests)) diff --git a/tb/qumcu/isa/rv32um/div.S b/tb/qumcu/isa/rv32um/div.S new file mode 100644 index 0000000..24dc9ff --- /dev/null +++ b/tb/qumcu/isa/rv32um/div.S @@ -0,0 +1,41 @@ +# See LICENSE for license details. + +#***************************************************************************** +# div.S +#----------------------------------------------------------------------------- +# +# Test div instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, div, 3, 20, 6 ); + TEST_RR_OP( 3, div, -3, -20, 6 ); + TEST_RR_OP( 4, div, -3, 20, -6 ); + TEST_RR_OP( 5, div, 3, -20, -6 ); + + TEST_RR_OP( 6, div, -1<<31, -1<<31, 1 ); + TEST_RR_OP( 7, div, -1<<31, -1<<31, -1 ); + + TEST_RR_OP( 8, div, -1, -1<<31, 0 ); + TEST_RR_OP( 9, div, -1, 1, 0 ); + TEST_RR_OP(10, div, -1, 0, 0 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv32um/divu.S b/tb/qumcu/isa/rv32um/divu.S new file mode 100644 index 0000000..cd348c9 --- /dev/null +++ b/tb/qumcu/isa/rv32um/divu.S @@ -0,0 +1,41 @@ +# See LICENSE for license details. + +#***************************************************************************** +# divu.S +#----------------------------------------------------------------------------- +# +# Test divu instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, divu, 3, 20, 6 ); + TEST_RR_OP( 3, divu, 715827879, -20, 6 ); + TEST_RR_OP( 4, divu, 0, 20, -6 ); + TEST_RR_OP( 5, divu, 0, -20, -6 ); + + TEST_RR_OP( 6, divu, -1<<31, -1<<31, 1 ); + TEST_RR_OP( 7, divu, 0, -1<<31, -1 ); + + TEST_RR_OP( 8, divu, -1, -1<<31, 0 ); + TEST_RR_OP( 9, divu, -1, 1, 0 ); + TEST_RR_OP(10, divu, -1, 0, 0 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv32um/mul.S b/tb/qumcu/isa/rv32um/mul.S new file mode 100644 index 0000000..0368629 --- /dev/null +++ b/tb/qumcu/isa/rv32um/mul.S @@ -0,0 +1,84 @@ +# See LICENSE for license details. + +#***************************************************************************** +# mul.S +#----------------------------------------------------------------------------- +# +# Test mul instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP(32, mul, 0x00001200, 0x00007e00, 0xb6db6db7 ); + TEST_RR_OP(33, mul, 0x00001240, 0x00007fc0, 0xb6db6db7 ); + + TEST_RR_OP( 2, mul, 0x00000000, 0x00000000, 0x00000000 ); + TEST_RR_OP( 3, mul, 0x00000001, 0x00000001, 0x00000001 ); + TEST_RR_OP( 4, mul, 0x00000015, 0x00000003, 0x00000007 ); + + TEST_RR_OP( 5, mul, 0x00000000, 0x00000000, 0xffff8000 ); + TEST_RR_OP( 6, mul, 0x00000000, 0x80000000, 0x00000000 ); + TEST_RR_OP( 7, mul, 0x00000000, 0x80000000, 0xffff8000 ); + + TEST_RR_OP(30, mul, 0x0000ff7f, 0xaaaaaaab, 0x0002fe7d ); + TEST_RR_OP(31, mul, 0x0000ff7f, 0x0002fe7d, 0xaaaaaaab ); + + TEST_RR_OP(34, mul, 0x00000000, 0xff000000, 0xff000000 ); + + TEST_RR_OP(35, mul, 0x00000001, 0xffffffff, 0xffffffff ); + TEST_RR_OP(36, mul, 0xffffffff, 0xffffffff, 0x00000001 ); + TEST_RR_OP(37, mul, 0xffffffff, 0x00000001, 0xffffffff ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 8, mul, 143, 13, 11 ); + TEST_RR_SRC2_EQ_DEST( 9, mul, 154, 14, 11 ); + TEST_RR_SRC12_EQ_DEST( 10, mul, 169, 13 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 11, 0, mul, 143, 13, 11 ); + TEST_RR_DEST_BYPASS( 12, 1, mul, 154, 14, 11 ); + TEST_RR_DEST_BYPASS( 13, 2, mul, 165, 15, 11 ); + + TEST_RR_SRC12_BYPASS( 14, 0, 0, mul, 143, 13, 11 ); + TEST_RR_SRC12_BYPASS( 15, 0, 1, mul, 154, 14, 11 ); + TEST_RR_SRC12_BYPASS( 16, 0, 2, mul, 165, 15, 11 ); + TEST_RR_SRC12_BYPASS( 17, 1, 0, mul, 143, 13, 11 ); + TEST_RR_SRC12_BYPASS( 18, 1, 1, mul, 154, 14, 11 ); + TEST_RR_SRC12_BYPASS( 19, 2, 0, mul, 165, 15, 11 ); + + TEST_RR_SRC21_BYPASS( 20, 0, 0, mul, 143, 13, 11 ); + TEST_RR_SRC21_BYPASS( 21, 0, 1, mul, 154, 14, 11 ); + TEST_RR_SRC21_BYPASS( 22, 0, 2, mul, 165, 15, 11 ); + TEST_RR_SRC21_BYPASS( 23, 1, 0, mul, 143, 13, 11 ); + TEST_RR_SRC21_BYPASS( 24, 1, 1, mul, 154, 14, 11 ); + TEST_RR_SRC21_BYPASS( 25, 2, 0, mul, 165, 15, 11 ); + + TEST_RR_ZEROSRC1( 26, mul, 0, 31 ); + TEST_RR_ZEROSRC2( 27, mul, 0, 32 ); + TEST_RR_ZEROSRC12( 28, mul, 0 ); + TEST_RR_ZERODEST( 29, mul, 33, 34 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv32um/mulh.S b/tb/qumcu/isa/rv32um/mulh.S new file mode 100644 index 0000000..e583f5f --- /dev/null +++ b/tb/qumcu/isa/rv32um/mulh.S @@ -0,0 +1,81 @@ +# See LICENSE for license details. + +#***************************************************************************** +# mulh.S +#----------------------------------------------------------------------------- +# +# Test mulh instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, mulh, 0x00000000, 0x00000000, 0x00000000 ); + TEST_RR_OP( 3, mulh, 0x00000000, 0x00000001, 0x00000001 ); + TEST_RR_OP( 4, mulh, 0x00000000, 0x00000003, 0x00000007 ); + + TEST_RR_OP( 5, mulh, 0x00000000, 0x00000000, 0xffff8000 ); + TEST_RR_OP( 6, mulh, 0x00000000, 0x80000000, 0x00000000 ); + TEST_RR_OP( 7, mulh, 0x00000000, 0x80000000, 0x00000000 ); + + TEST_RR_OP(30, mulh, 0xffff0081, 0xaaaaaaab, 0x0002fe7d ); + TEST_RR_OP(31, mulh, 0xffff0081, 0x0002fe7d, 0xaaaaaaab ); + + TEST_RR_OP(32, mulh, 0x00010000, 0xff000000, 0xff000000 ); + + TEST_RR_OP(33, mulh, 0x00000000, 0xffffffff, 0xffffffff ); + TEST_RR_OP(34, mulh, 0xffffffff, 0xffffffff, 0x00000001 ); + TEST_RR_OP(35, mulh, 0xffffffff, 0x00000001, 0xffffffff ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 8, mulh, 36608, 13<<20, 11<<20 ); + TEST_RR_SRC2_EQ_DEST( 9, mulh, 39424, 14<<20, 11<<20 ); + TEST_RR_SRC12_EQ_DEST( 10, mulh, 43264, 13<<20 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 11, 0, mulh, 36608, 13<<20, 11<<20 ); + TEST_RR_DEST_BYPASS( 12, 1, mulh, 39424, 14<<20, 11<<20 ); + TEST_RR_DEST_BYPASS( 13, 2, mulh, 42240, 15<<20, 11<<20 ); + + TEST_RR_SRC12_BYPASS( 14, 0, 0, mulh, 36608, 13<<20, 11<<20 ); + TEST_RR_SRC12_BYPASS( 15, 0, 1, mulh, 39424, 14<<20, 11<<20 ); + TEST_RR_SRC12_BYPASS( 16, 0, 2, mulh, 42240, 15<<20, 11<<20 ); + TEST_RR_SRC12_BYPASS( 17, 1, 0, mulh, 36608, 13<<20, 11<<20 ); + TEST_RR_SRC12_BYPASS( 18, 1, 1, mulh, 39424, 14<<20, 11<<20 ); + TEST_RR_SRC12_BYPASS( 19, 2, 0, mulh, 42240, 15<<20, 11<<20 ); + + TEST_RR_SRC21_BYPASS( 20, 0, 0, mulh, 36608, 13<<20, 11<<20 ); + TEST_RR_SRC21_BYPASS( 21, 0, 1, mulh, 39424, 14<<20, 11<<20 ); + TEST_RR_SRC21_BYPASS( 22, 0, 2, mulh, 42240, 15<<20, 11<<20 ); + TEST_RR_SRC21_BYPASS( 23, 1, 0, mulh, 36608, 13<<20, 11<<20 ); + TEST_RR_SRC21_BYPASS( 24, 1, 1, mulh, 39424, 14<<20, 11<<20 ); + TEST_RR_SRC21_BYPASS( 25, 2, 0, mulh, 42240, 15<<20, 11<<20 ); + + TEST_RR_ZEROSRC1( 26, mulh, 0, 31<<26 ); + TEST_RR_ZEROSRC2( 27, mulh, 0, 32<<26 ); + TEST_RR_ZEROSRC12( 28, mulh, 0 ); + TEST_RR_ZERODEST( 29, mulh, 33<<20, 34<<20 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv32um/mulhsu.S b/tb/qumcu/isa/rv32um/mulhsu.S new file mode 100644 index 0000000..28b3690 --- /dev/null +++ b/tb/qumcu/isa/rv32um/mulhsu.S @@ -0,0 +1,83 @@ +# See LICENSE for license details. + +#***************************************************************************** +# mulhsu.S +#----------------------------------------------------------------------------- +# +# Test mulhsu instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, mulhsu, 0x00000000, 0x00000000, 0x00000000 ); + TEST_RR_OP( 3, mulhsu, 0x00000000, 0x00000001, 0x00000001 ); + TEST_RR_OP( 4, mulhsu, 0x00000000, 0x00000003, 0x00000007 ); + + TEST_RR_OP( 5, mulhsu, 0x00000000, 0x00000000, 0xffff8000 ); + TEST_RR_OP( 6, mulhsu, 0x00000000, 0x80000000, 0x00000000 ); + TEST_RR_OP( 7, mulhsu, 0x80004000, 0x80000000, 0xffff8000 ); + + TEST_RR_OP(30, mulhsu, 0xffff0081, 0xaaaaaaab, 0x0002fe7d ); + TEST_RR_OP(31, mulhsu, 0x0001fefe, 0x0002fe7d, 0xaaaaaaab ); + + TEST_RR_OP(32, mulhsu, 0xff010000, 0xff000000, 0xff000000 ); + + TEST_RR_OP(33, mulhsu, 0xffffffff, 0xffffffff, 0xffffffff ); + TEST_RR_OP(34, mulhsu, 0xffffffff, 0xffffffff, 0x00000001 ); + TEST_RR_OP(35, mulhsu, 0x00000000, 0x00000001, 0xffffffff ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 8, mulhsu, 36608, 13<<20, 11<<20 ); + TEST_RR_SRC2_EQ_DEST( 9, mulhsu, 39424, 14<<20, 11<<20 ); + TEST_RR_SRC12_EQ_DEST( 10, mulhsu, 43264, 13<<20 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 11, 0, mulhsu, 36608, 13<<20, 11<<20 ); + TEST_RR_DEST_BYPASS( 12, 1, mulhsu, 39424, 14<<20, 11<<20 ); + TEST_RR_DEST_BYPASS( 13, 2, mulhsu, 42240, 15<<20, 11<<20 ); + + TEST_RR_SRC12_BYPASS( 14, 0, 0, mulhsu, 36608, 13<<20, 11<<20 ); + TEST_RR_SRC12_BYPASS( 15, 0, 1, mulhsu, 39424, 14<<20, 11<<20 ); + TEST_RR_SRC12_BYPASS( 16, 0, 2, mulhsu, 42240, 15<<20, 11<<20 ); + TEST_RR_SRC12_BYPASS( 17, 1, 0, mulhsu, 36608, 13<<20, 11<<20 ); + TEST_RR_SRC12_BYPASS( 18, 1, 1, mulhsu, 39424, 14<<20, 11<<20 ); + TEST_RR_SRC12_BYPASS( 19, 2, 0, mulhsu, 42240, 15<<20, 11<<20 ); + + TEST_RR_SRC21_BYPASS( 20, 0, 0, mulhsu, 36608, 13<<20, 11<<20 ); + TEST_RR_SRC21_BYPASS( 21, 0, 1, mulhsu, 39424, 14<<20, 11<<20 ); + TEST_RR_SRC21_BYPASS( 22, 0, 2, mulhsu, 42240, 15<<20, 11<<20 ); + TEST_RR_SRC21_BYPASS( 23, 1, 0, mulhsu, 36608, 13<<20, 11<<20 ); + TEST_RR_SRC21_BYPASS( 24, 1, 1, mulhsu, 39424, 14<<20, 11<<20 ); + TEST_RR_SRC21_BYPASS( 25, 2, 0, mulhsu, 42240, 15<<20, 11<<20 ); + + TEST_RR_ZEROSRC1( 26, mulhsu, 0, 31<<26 ); + TEST_RR_ZEROSRC2( 27, mulhsu, 0, 32<<26 ); + TEST_RR_ZEROSRC12( 28, mulhsu, 0 ); + TEST_RR_ZERODEST( 29, mulhsu, 33<<20, 34<<20 ); + + + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv32um/mulhu.S b/tb/qumcu/isa/rv32um/mulhu.S new file mode 100644 index 0000000..601dcff --- /dev/null +++ b/tb/qumcu/isa/rv32um/mulhu.S @@ -0,0 +1,82 @@ +# See LICENSE for license details. + +#***************************************************************************** +# mulhu.S +#----------------------------------------------------------------------------- +# +# Test mulhu instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, mulhu, 0x00000000, 0x00000000, 0x00000000 ); + TEST_RR_OP( 3, mulhu, 0x00000000, 0x00000001, 0x00000001 ); + TEST_RR_OP( 4, mulhu, 0x00000000, 0x00000003, 0x00000007 ); + + TEST_RR_OP( 5, mulhu, 0x00000000, 0x00000000, 0xffff8000 ); + TEST_RR_OP( 6, mulhu, 0x00000000, 0x80000000, 0x00000000 ); + TEST_RR_OP( 7, mulhu, 0x7fffc000, 0x80000000, 0xffff8000 ); + + TEST_RR_OP(30, mulhu, 0x0001fefe, 0xaaaaaaab, 0x0002fe7d ); + TEST_RR_OP(31, mulhu, 0x0001fefe, 0x0002fe7d, 0xaaaaaaab ); + + TEST_RR_OP(32, mulhu, 0xfe010000, 0xff000000, 0xff000000 ); + + TEST_RR_OP(33, mulhu, 0xfffffffe, 0xffffffff, 0xffffffff ); + TEST_RR_OP(34, mulhu, 0x00000000, 0xffffffff, 0x00000001 ); + TEST_RR_OP(35, mulhu, 0x00000000, 0x00000001, 0xffffffff ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 8, mulhu, 36608, 13<<20, 11<<20 ); + TEST_RR_SRC2_EQ_DEST( 9, mulhu, 39424, 14<<20, 11<<20 ); + TEST_RR_SRC12_EQ_DEST( 10, mulhu, 43264, 13<<20 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 11, 0, mulhu, 36608, 13<<20, 11<<20 ); + TEST_RR_DEST_BYPASS( 12, 1, mulhu, 39424, 14<<20, 11<<20 ); + TEST_RR_DEST_BYPASS( 13, 2, mulhu, 42240, 15<<20, 11<<20 ); + + TEST_RR_SRC12_BYPASS( 14, 0, 0, mulhu, 36608, 13<<20, 11<<20 ); + TEST_RR_SRC12_BYPASS( 15, 0, 1, mulhu, 39424, 14<<20, 11<<20 ); + TEST_RR_SRC12_BYPASS( 16, 0, 2, mulhu, 42240, 15<<20, 11<<20 ); + TEST_RR_SRC12_BYPASS( 17, 1, 0, mulhu, 36608, 13<<20, 11<<20 ); + TEST_RR_SRC12_BYPASS( 18, 1, 1, mulhu, 39424, 14<<20, 11<<20 ); + TEST_RR_SRC12_BYPASS( 19, 2, 0, mulhu, 42240, 15<<20, 11<<20 ); + + TEST_RR_SRC21_BYPASS( 20, 0, 0, mulhu, 36608, 13<<20, 11<<20 ); + TEST_RR_SRC21_BYPASS( 21, 0, 1, mulhu, 39424, 14<<20, 11<<20 ); + TEST_RR_SRC21_BYPASS( 22, 0, 2, mulhu, 42240, 15<<20, 11<<20 ); + TEST_RR_SRC21_BYPASS( 23, 1, 0, mulhu, 36608, 13<<20, 11<<20 ); + TEST_RR_SRC21_BYPASS( 24, 1, 1, mulhu, 39424, 14<<20, 11<<20 ); + TEST_RR_SRC21_BYPASS( 25, 2, 0, mulhu, 42240, 15<<20, 11<<20 ); + + TEST_RR_ZEROSRC1( 26, mulhu, 0, 31<<26 ); + TEST_RR_ZEROSRC2( 27, mulhu, 0, 32<<26 ); + TEST_RR_ZEROSRC12( 28, mulhu, 0 ); + TEST_RR_ZERODEST( 29, mulhu, 33<<20, 34<<20 ); + + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv32um/rem.S b/tb/qumcu/isa/rv32um/rem.S new file mode 100644 index 0000000..7955736 --- /dev/null +++ b/tb/qumcu/isa/rv32um/rem.S @@ -0,0 +1,41 @@ +# See LICENSE for license details. + +#***************************************************************************** +# rem.S +#----------------------------------------------------------------------------- +# +# Test rem instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, rem, 2, 20, 6 ); + TEST_RR_OP( 3, rem, -2, -20, 6 ); + TEST_RR_OP( 4, rem, 2, 20, -6 ); + TEST_RR_OP( 5, rem, -2, -20, -6 ); + + TEST_RR_OP( 6, rem, 0, -1<<31, 1 ); + TEST_RR_OP( 7, rem, 0, -1<<31, -1 ); + + TEST_RR_OP( 8, rem, -1<<31, -1<<31, 0 ); + TEST_RR_OP( 9, rem, 1, 1, 0 ); + TEST_RR_OP(10, rem, 0, 0, 0 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv32um/remu.S b/tb/qumcu/isa/rv32um/remu.S new file mode 100644 index 0000000..a96cfc1 --- /dev/null +++ b/tb/qumcu/isa/rv32um/remu.S @@ -0,0 +1,41 @@ +# See LICENSE for license details. + +#***************************************************************************** +# remu.S +#----------------------------------------------------------------------------- +# +# Test remu instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, remu, 2, 20, 6 ); + TEST_RR_OP( 3, remu, 2, -20, 6 ); + TEST_RR_OP( 4, remu, 20, 20, -6 ); + TEST_RR_OP( 5, remu, -20, -20, -6 ); + + TEST_RR_OP( 6, remu, 0, -1<<31, 1 ); + TEST_RR_OP( 7, remu, -1<<31, -1<<31, -1 ); + + TEST_RR_OP( 8, remu, -1<<31, -1<<31, 0 ); + TEST_RR_OP( 9, remu, 1, 1, 0 ); + TEST_RR_OP(10, remu, 0, 0, 0 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv32uzba/Makefrag b/tb/qumcu/isa/rv32uzba/Makefrag new file mode 100644 index 0000000..39a2c99 --- /dev/null +++ b/tb/qumcu/isa/rv32uzba/Makefrag @@ -0,0 +1,14 @@ +#======================================================================= +# Makefrag for rv32uzba tests +#----------------------------------------------------------------------- + +rv32uzba_sc_tests = \ + sh1add \ + sh2add \ + sh3add \ + +rv32uzba_p_tests = $(addprefix rv32uzba-p-, $(rv32uzba_sc_tests)) +rv32uzba_v_tests = $(addprefix rv32uzba-v-, $(rv32uzba_sc_tests)) +rv32uzba_ps_tests = $(addprefix rv32uzba-ps-, $(rv32uzba_sc_tests)) + +spike_tests += $(rv32uzba_p_tests) $(rv32uzba_v_tests) diff --git a/tb/qumcu/isa/rv32uzba/sh1add.S b/tb/qumcu/isa/rv32uzba/sh1add.S new file mode 100644 index 0000000..03ae190 --- /dev/null +++ b/tb/qumcu/isa/rv32uzba/sh1add.S @@ -0,0 +1,85 @@ +# See LICENSE for license details. + +#***************************************************************************** +# sh1add.S +#----------------------------------------------------------------------------- +# +# Test sh1add instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, sh1add, 0x00000000, 0x00000000, 0x00000000 ); + TEST_RR_OP( 3, sh1add, 0x00000003, 0x00000001, 0x00000001 ); + TEST_RR_OP( 4, sh1add, 0x0000000d, 0x00000003, 0x00000007 ); + + TEST_RR_OP( 5, sh1add, 0xffff8000, 0x00000000, 0xffff8000 ); + TEST_RR_OP( 6, sh1add, 0x00000000, 0x80000000, 0x00000000 ); + TEST_RR_OP( 7, sh1add, 0xffff8000, 0x80000000, 0xffff8000 ); + + TEST_RR_OP( 8, sh1add, 0x00007fff, 0x00000000, 0x00007fff ); + TEST_RR_OP( 9, sh1add, 0xfffffffe, 0x7fffffff, 0x00000000 ); + TEST_RR_OP( 10, sh1add, 0x00007ffd, 0x7fffffff, 0x00007fff ); + + TEST_RR_OP( 11, sh1add, 0x00007fff, 0x80000000, 0x00007fff ); + TEST_RR_OP( 12, sh1add, 0xffff7ffe, 0x7fffffff, 0xffff8000 ); + + TEST_RR_OP( 13, sh1add, 0xffffffff, 0x00000000, 0xffffffff ); + TEST_RR_OP( 14, sh1add, 0xffffffff, 0xffffffff, 0x00000001 ); + TEST_RR_OP( 15, sh1add, 0xfffffffd, 0xffffffff, 0xffffffff ); + + TEST_RR_OP( 16, sh1add, 0x80000001, 0x00000001, 0x7fffffff ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 17, sh1add, 37, 13, 11 ); + TEST_RR_SRC2_EQ_DEST( 18, sh1add, 39, 14, 11 ); + TEST_RR_SRC12_EQ_DEST( 19, sh1add, 39, 13 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 20, 0, sh1add, 37, 13, 11 ); + TEST_RR_DEST_BYPASS( 21, 1, sh1add, 39, 14, 11 ); + TEST_RR_DEST_BYPASS( 22, 2, sh1add, 41, 15, 11 ); + + TEST_RR_SRC12_BYPASS( 23, 0, 0, sh1add, 37, 13, 11 ); + TEST_RR_SRC12_BYPASS( 24, 0, 1, sh1add, 39, 14, 11 ); + TEST_RR_SRC12_BYPASS( 25, 0, 2, sh1add, 41, 15, 11 ); + TEST_RR_SRC12_BYPASS( 26, 1, 0, sh1add, 37, 13, 11 ); + TEST_RR_SRC12_BYPASS( 27, 1, 1, sh1add, 39, 14, 11 ); + TEST_RR_SRC12_BYPASS( 28, 2, 0, sh1add, 41, 15, 11 ); + + TEST_RR_SRC21_BYPASS( 29, 0, 0, sh1add, 37, 13, 11 ); + TEST_RR_SRC21_BYPASS( 30, 0, 1, sh1add, 39, 14, 11 ); + TEST_RR_SRC21_BYPASS( 31, 0, 2, sh1add, 41, 15, 11 ); + TEST_RR_SRC21_BYPASS( 32, 1, 0, sh1add, 37, 13, 11 ); + TEST_RR_SRC21_BYPASS( 33, 1, 1, sh1add, 39, 14, 11 ); + TEST_RR_SRC21_BYPASS( 34, 2, 0, sh1add, 41, 15, 11 ); + + TEST_RR_ZEROSRC1( 35, sh1add, 15, 15 ); + TEST_RR_ZEROSRC2( 36, sh1add, 64, 32 ); + TEST_RR_ZEROSRC12( 37, sh1add, 0 ); + TEST_RR_ZERODEST( 38, sh1add, 16, 30 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv32uzba/sh2add.S b/tb/qumcu/isa/rv32uzba/sh2add.S new file mode 100644 index 0000000..057dba5 --- /dev/null +++ b/tb/qumcu/isa/rv32uzba/sh2add.S @@ -0,0 +1,85 @@ +# See LICENSE for license details. + +#***************************************************************************** +# sh2add.S +#----------------------------------------------------------------------------- +# +# Test sh2add instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, sh2add, 0x00000000, 0x00000000, 0x00000000 ); + TEST_RR_OP( 3, sh2add, 0x00000005, 0x00000001, 0x00000001 ); + TEST_RR_OP( 4, sh2add, 0x00000013, 0x00000003, 0x00000007 ); + + TEST_RR_OP( 5, sh2add, 0xffff8000, 0x00000000, 0xffff8000 ); + TEST_RR_OP( 6, sh2add, 0x00000000, 0x80000000, 0x00000000 ); + TEST_RR_OP( 7, sh2add, 0xffff8000, 0x80000000, 0xffff8000 ); + + TEST_RR_OP( 8, sh2add, 0x00007fff, 0x00000000, 0x00007fff ); + TEST_RR_OP( 9, sh2add, 0xfffffffc, 0x7fffffff, 0x00000000 ); + TEST_RR_OP( 10, sh2add, 0x00007ffb, 0x7fffffff, 0x00007fff ); + + TEST_RR_OP( 11, sh2add, 0x00007fff, 0x80000000, 0x00007fff ); + TEST_RR_OP( 12, sh2add, 0xffff7ffc, 0x7fffffff, 0xffff8000 ); + + TEST_RR_OP( 13, sh2add, 0xffffffff, 0x00000000, 0xffffffff ); + TEST_RR_OP( 14, sh2add, 0xfffffffd, 0xffffffff, 0x00000001 ); + TEST_RR_OP( 15, sh2add, 0xfffffffb, 0xffffffff, 0xffffffff ); + + TEST_RR_OP( 16, sh2add, 0x80000003, 0x00000001, 0x7fffffff ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 17, sh2add, 63, 13, 11 ); + TEST_RR_SRC2_EQ_DEST( 18, sh2add, 67, 14, 11 ); + TEST_RR_SRC12_EQ_DEST( 19, sh2add, 65, 13 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 20, 0, sh2add, 63, 13, 11 ); + TEST_RR_DEST_BYPASS( 21, 1, sh2add, 67, 14, 11 ); + TEST_RR_DEST_BYPASS( 22, 2, sh2add, 71, 15, 11 ); + + TEST_RR_SRC12_BYPASS( 23, 0, 0, sh2add, 63, 13, 11 ); + TEST_RR_SRC12_BYPASS( 24, 0, 1, sh2add, 67, 14, 11 ); + TEST_RR_SRC12_BYPASS( 25, 0, 2, sh2add, 71, 15, 11 ); + TEST_RR_SRC12_BYPASS( 26, 1, 0, sh2add, 63, 13, 11 ); + TEST_RR_SRC12_BYPASS( 27, 1, 1, sh2add, 67, 14, 11 ); + TEST_RR_SRC12_BYPASS( 28, 2, 0, sh2add, 71, 15, 11 ); + + TEST_RR_SRC21_BYPASS( 29, 0, 0, sh2add, 63, 13, 11 ); + TEST_RR_SRC21_BYPASS( 30, 0, 1, sh2add, 67, 14, 11 ); + TEST_RR_SRC21_BYPASS( 31, 0, 2, sh2add, 71, 15, 11 ); + TEST_RR_SRC21_BYPASS( 32, 1, 0, sh2add, 63, 13, 11 ); + TEST_RR_SRC21_BYPASS( 33, 1, 1, sh2add, 67, 14, 11 ); + TEST_RR_SRC21_BYPASS( 34, 2, 0, sh2add, 71, 15, 11 ); + + TEST_RR_ZEROSRC1( 35, sh2add, 15, 15 ); + TEST_RR_ZEROSRC2( 36, sh2add, 128, 32 ); + TEST_RR_ZEROSRC12( 37, sh2add, 0 ); + TEST_RR_ZERODEST( 38, sh2add, 16, 30 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv32uzba/sh3add.S b/tb/qumcu/isa/rv32uzba/sh3add.S new file mode 100644 index 0000000..530241e --- /dev/null +++ b/tb/qumcu/isa/rv32uzba/sh3add.S @@ -0,0 +1,85 @@ +# See LICENSE for license details. + +#***************************************************************************** +# sh3add.S +#----------------------------------------------------------------------------- +# +# Test sh3add instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, sh3add, 0x00000000, 0x00000000, 0x00000000 ); + TEST_RR_OP( 3, sh3add, 0x00000009, 0x00000001, 0x00000001 ); + TEST_RR_OP( 4, sh3add, 0x0000001f, 0x00000003, 0x00000007 ); + + TEST_RR_OP( 5, sh3add, 0xffff8000, 0x00000000, 0xffff8000 ); + TEST_RR_OP( 6, sh3add, 0x00000000, 0x80000000, 0x00000000 ); + TEST_RR_OP( 7, sh3add, 0xffff8000, 0x80000000, 0xffff8000 ); + + TEST_RR_OP( 8, sh3add, 0x00007fff, 0x00000000, 0x00007fff ); + TEST_RR_OP( 9, sh3add, 0xfffffff8, 0x7fffffff, 0x00000000 ); + TEST_RR_OP( 10, sh3add, 0x00007ff7, 0x7fffffff, 0x00007fff ); + + TEST_RR_OP( 11, sh3add, 0x00007fff, 0x80000000, 0x00007fff ); + TEST_RR_OP( 12, sh3add, 0xffff7ff8, 0x7fffffff, 0xffff8000 ); + + TEST_RR_OP( 13, sh3add, 0xffffffff, 0x00000000, 0xffffffff ); + TEST_RR_OP( 14, sh3add, 0xfffffff9, 0xffffffff, 0x00000001 ); + TEST_RR_OP( 15, sh3add, 0xfffffff7, 0xffffffff, 0xffffffff ); + + TEST_RR_OP( 16, sh3add, 0x80000007, 0x00000001, 0x7fffffff ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 17, sh3add, 115, 13, 11 ); + TEST_RR_SRC2_EQ_DEST( 18, sh3add, 123, 14, 11 ); + TEST_RR_SRC12_EQ_DEST( 19, sh3add, 117, 13 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 20, 0, sh3add, 115, 13, 11 ); + TEST_RR_DEST_BYPASS( 21, 1, sh3add, 123, 14, 11 ); + TEST_RR_DEST_BYPASS( 22, 2, sh3add, 131, 15, 11 ); + + TEST_RR_SRC12_BYPASS( 23, 0, 0, sh3add, 115, 13, 11 ); + TEST_RR_SRC12_BYPASS( 24, 0, 1, sh3add, 123, 14, 11 ); + TEST_RR_SRC12_BYPASS( 25, 0, 2, sh3add, 131, 15, 11 ); + TEST_RR_SRC12_BYPASS( 26, 1, 0, sh3add, 115, 13, 11 ); + TEST_RR_SRC12_BYPASS( 27, 1, 1, sh3add, 123, 14, 11 ); + TEST_RR_SRC12_BYPASS( 28, 2, 0, sh3add, 131, 15, 11 ); + + TEST_RR_SRC21_BYPASS( 29, 0, 0, sh3add, 115, 13, 11 ); + TEST_RR_SRC21_BYPASS( 30, 0, 1, sh3add, 123, 14, 11 ); + TEST_RR_SRC21_BYPASS( 31, 0, 2, sh3add, 131, 15, 11 ); + TEST_RR_SRC21_BYPASS( 32, 1, 0, sh3add, 115, 13, 11 ); + TEST_RR_SRC21_BYPASS( 33, 1, 1, sh3add, 123, 14, 11 ); + TEST_RR_SRC21_BYPASS( 34, 2, 0, sh3add, 131, 15, 11 ); + + TEST_RR_ZEROSRC1( 35, sh3add, 15, 15 ); + TEST_RR_ZEROSRC2( 36, sh3add, 256, 32 ); + TEST_RR_ZEROSRC12( 37, sh3add, 0 ); + TEST_RR_ZERODEST( 38, sh3add, 16, 30 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv32uzbb/Makefrag b/tb/qumcu/isa/rv32uzbb/Makefrag new file mode 100644 index 0000000..752f8d0 --- /dev/null +++ b/tb/qumcu/isa/rv32uzbb/Makefrag @@ -0,0 +1,26 @@ +#======================================================================= +# Makefrag for rv32uzbb tests +#----------------------------------------------------------------------- + +rv32uzbb_sc_tests = \ + andn \ + clz \ + cpop \ + ctz \ + max maxu \ + min minu \ + orc_b \ + orn \ + rev8 \ + rol \ + ror \ + rori \ + sext_b sext_h \ + xnor \ + zext_h \ + +rv32uzbb_p_tests = $(addprefix rv32uzbb-p-, $(rv32uzbb_sc_tests)) +rv32uzbb_v_tests = $(addprefix rv32uzbb-v-, $(rv32uzbb_sc_tests)) +rv32uzbb_ps_tests = $(addprefix rv32uzbb-ps-, $(rv32uzbb_sc_tests)) + +spike_tests += $(rv32uzbb_p_tests) $(rv32uzbb_v_tests) diff --git a/tb/qumcu/isa/rv32uzbb/andn.S b/tb/qumcu/isa/rv32uzbb/andn.S new file mode 100644 index 0000000..f54aa1a --- /dev/null +++ b/tb/qumcu/isa/rv32uzbb/andn.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64uzbb/andn.S" diff --git a/tb/qumcu/isa/rv32uzbb/clz.S b/tb/qumcu/isa/rv32uzbb/clz.S new file mode 100644 index 0000000..4b349ad --- /dev/null +++ b/tb/qumcu/isa/rv32uzbb/clz.S @@ -0,0 +1,76 @@ +# See LICENSE for license details. + +#***************************************************************************** +# clz.S +#----------------------------------------------------------------------------- +# +# Test clz instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_R_OP( 2, clz, 32, 0x00000000); + TEST_R_OP( 3, clz, 31, 0x00000001); + TEST_R_OP( 4, clz, 30, 0x00000003); + + TEST_R_OP( 5, clz, 0, 0xffff8000 ); + TEST_R_OP( 6, clz, 8, 0x00800000 ); + TEST_R_OP( 7, clz, 0, 0xffff8000 ); + + TEST_R_OP( 8, clz, 17, 0x00007fff); + TEST_R_OP( 9, clz, 1, 0x7fffffff); + TEST_R_OP( 10, clz, 13, 0x0007ffff ); + + TEST_R_OP( 11, clz, 0, 0x80000000); + TEST_R_OP( 12, clz, 3, 0x121f5000); + + TEST_R_OP( 13, clz, 5, 0x04000000); + TEST_R_OP( 14, clz, 28, 0x0000000e); + TEST_R_OP( 15, clz, 2, 0x20401341); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_R_SRC1_EQ_DEST( 16, clz, 28, 13); + TEST_R_SRC1_EQ_DEST( 17, clz, 28, 11); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_R_DEST_BYPASS( 18, 0, clz, 28, 13); + TEST_R_DEST_BYPASS( 29, 1, clz, 27, 19); + TEST_R_DEST_BYPASS( 20, 2, clz, 26, 34); + + #------------------------------------------------------------- + # Other tests + #------------------------------------------------------------- + + + TEST_R_OP( 21, clz, 5, 0x070f8000 ); + TEST_R_OP( 22, clz, 4, 0x08008000 ); + TEST_R_OP( 23, clz, 3, 0x18008000 ); + + TEST_R_OP( 24, clz, 17, 0x00007fff); + TEST_R_OP( 25, clz, 1, 0x7fffffff); + TEST_R_OP( 26, clz, 13, 0x0007ffff); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv32uzbb/cpop.S b/tb/qumcu/isa/rv32uzbb/cpop.S new file mode 100644 index 0000000..4d97758 --- /dev/null +++ b/tb/qumcu/isa/rv32uzbb/cpop.S @@ -0,0 +1,75 @@ +# See LICENSE for license details. + +#***************************************************************************** +# cpop.S +#----------------------------------------------------------------------------- +# +# Test cpop instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_R_OP( 2, cpop, 0, 0x00000000); + TEST_R_OP( 3, cpop, 1, 0x00000001); + TEST_R_OP( 4, cpop, 2, 0x00000003); + + TEST_R_OP( 5, cpop, 17, 0xffff8000 ); + TEST_R_OP( 6, cpop, 1, 0x00800000 ); + TEST_R_OP( 7, cpop, 18, 0xffff6000 ); + + TEST_R_OP( 8, cpop, 15, 0x00007fff); + TEST_R_OP( 9, cpop, 31, 0x7fffffff); + TEST_R_OP( 10, cpop, 19, 0x0007ffff ); + + TEST_R_OP( 11, cpop, 1, 0x80000000); + TEST_R_OP( 12, cpop, 9, 0x121f5000); + + TEST_R_OP( 13, cpop, 0, 0x00000000); + TEST_R_OP( 14, cpop, 3, 0x0000000e); + TEST_R_OP( 15, cpop, 7, 0x20401341); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_R_SRC1_EQ_DEST( 16, cpop, 3, 13); + TEST_R_SRC1_EQ_DEST( 17, cpop, 3, 11); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_R_DEST_BYPASS( 18, 0, cpop, 3, 13); + TEST_R_DEST_BYPASS( 29, 1, cpop, 3, 19); + TEST_R_DEST_BYPASS( 20, 2, cpop, 2, 34); + + #------------------------------------------------------------- + # Other tests + #------------------------------------------------------------- + + TEST_R_OP( 21, cpop, 8, 0x007f8000 ); + TEST_R_OP( 22, cpop, 2, 0x00808000 ); + TEST_R_OP( 23, cpop, 3, 0x01808000 ); + + TEST_R_OP( 24, cpop, 17, 0x30007fff); + TEST_R_OP( 25, cpop, 30, 0x77ffffff); + TEST_R_OP( 26, cpop, 19, 0x0007ffff); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv32uzbb/ctz.S b/tb/qumcu/isa/rv32uzbb/ctz.S new file mode 100644 index 0000000..58bf2f1 --- /dev/null +++ b/tb/qumcu/isa/rv32uzbb/ctz.S @@ -0,0 +1,75 @@ +# See LICENSE for license details. + +#***************************************************************************** +# ctz.S +#----------------------------------------------------------------------------- +# +# Test ctz instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_R_OP( 2, ctz, 32, 0x00000000); + TEST_R_OP( 3, ctz, 0, 0x00000001); + TEST_R_OP( 4, ctz, 0, 0x00000003); + + TEST_R_OP( 5, ctz, 15, 0xffff8000 ); + TEST_R_OP( 6, ctz, 23, 0x00800000 ); + TEST_R_OP( 7, ctz, 15, 0xffff8000 ); + + TEST_R_OP( 8, ctz, 0, 0x00007fff); + TEST_R_OP( 9, ctz, 0, 0x7fffffff); + TEST_R_OP( 10, ctz, 0, 0x0007ffff ); + + TEST_R_OP( 11, ctz, 31, 0x80000000); + TEST_R_OP( 12, ctz, 12, 0x121f5000); + + TEST_R_OP( 13, ctz, 30, 0xc0000000); + TEST_R_OP( 14, ctz, 1, 0x0000000e); + TEST_R_OP( 15, ctz, 0, 0x20401341); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_R_SRC1_EQ_DEST( 16, ctz, 0, 13); + TEST_R_SRC1_EQ_DEST( 17, ctz, 0, 11); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_R_DEST_BYPASS( 18, 0, ctz, 0, 13); + TEST_R_DEST_BYPASS( 29, 1, ctz, 0, 19); + TEST_R_DEST_BYPASS( 20, 2, ctz, 1, 34); + + #------------------------------------------------------------- + # Other tests + #------------------------------------------------------------- + + TEST_R_OP( 21, ctz, 15, 0x007f8000 ); + TEST_R_OP( 22, ctz, 15, 0x00808000 ); + TEST_R_OP( 23, ctz, 12, 0x01809000 ); + + TEST_R_OP( 24, ctz, 0, 0x00007fff); + TEST_R_OP( 25, ctz, 0, 0x7fffffff); + TEST_R_OP( 26, ctz, 0, 0x0007ffff); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv32uzbb/max.S b/tb/qumcu/isa/rv32uzbb/max.S new file mode 100644 index 0000000..ecd713c --- /dev/null +++ b/tb/qumcu/isa/rv32uzbb/max.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64uzbb/max.S" diff --git a/tb/qumcu/isa/rv32uzbb/maxu.S b/tb/qumcu/isa/rv32uzbb/maxu.S new file mode 100644 index 0000000..27cfc29 --- /dev/null +++ b/tb/qumcu/isa/rv32uzbb/maxu.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64uzbb/maxu.S" diff --git a/tb/qumcu/isa/rv32uzbb/min.S b/tb/qumcu/isa/rv32uzbb/min.S new file mode 100644 index 0000000..c24a514 --- /dev/null +++ b/tb/qumcu/isa/rv32uzbb/min.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64uzbb/min.S" diff --git a/tb/qumcu/isa/rv32uzbb/minu.S b/tb/qumcu/isa/rv32uzbb/minu.S new file mode 100644 index 0000000..4b2549d --- /dev/null +++ b/tb/qumcu/isa/rv32uzbb/minu.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64uzbb/minu.S" diff --git a/tb/qumcu/isa/rv32uzbb/orc_b.S b/tb/qumcu/isa/rv32uzbb/orc_b.S new file mode 100644 index 0000000..7fb8441 --- /dev/null +++ b/tb/qumcu/isa/rv32uzbb/orc_b.S @@ -0,0 +1,75 @@ +# See LICENSE for license details. + +#***************************************************************************** +# orc.b.S +#----------------------------------------------------------------------------- +# +# Test orc.b instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_R_OP( 2, orc.b, 0x00000000, 0x00000000); + TEST_R_OP( 3, orc.b, 0x000000ff, 0x00000001); + TEST_R_OP( 4, orc.b, 0x000000ff, 0x00000003); + + TEST_R_OP( 5, orc.b, 0xffffff00, 0xffff8000 ); + TEST_R_OP( 6, orc.b, 0x00ff0000, 0x00800000 ); + TEST_R_OP( 7, orc.b, 0xffffff00, 0xffff8000 ); + + TEST_R_OP( 8, orc.b, 0x0000ffff, 0x00007fff); + TEST_R_OP( 9, orc.b, 0xffffffff, 0x7fffffff); + TEST_R_OP( 10, orc.b, 0x00ffffff, 0x0007ffff ); + + TEST_R_OP( 11, orc.b, 0xff000000, 0x80000000); + TEST_R_OP( 12, orc.b, 0xffffff00, 0x121f5000); + + TEST_R_OP( 13, orc.b, 0x00000000, 0x00000000); + TEST_R_OP( 14, orc.b, 0x000000ff, 0x0000000e); + TEST_R_OP( 15, orc.b, 0xffffffff, 0x20401341); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_R_SRC1_EQ_DEST( 16, orc.b, 0xff, 13); + TEST_R_SRC1_EQ_DEST( 17, orc.b, 0xff, 11); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_R_DEST_BYPASS( 18, 0, orc.b, 0xff, 13); + TEST_R_DEST_BYPASS( 29, 1, orc.b, 0xff, 19); + TEST_R_DEST_BYPASS( 20, 2, orc.b, 0xff, 34); + + #------------------------------------------------------------- + # Other tests + #------------------------------------------------------------- + + TEST_R_OP( 21, orc.b, 0x00ffff00, 0x007f8000 ); + TEST_R_OP( 22, orc.b, 0x00ffff00, 0x00808000 ); + TEST_R_OP( 23, orc.b, 0xffffff00, 0x01808000 ); + + TEST_R_OP( 24, orc.b, 0x0000ffff, 0x00007fff); + TEST_R_OP( 25, orc.b, 0xffffffff, 0x7fffffff); + TEST_R_OP( 26, orc.b, 0x00ffffff, 0x0007ffff); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv32uzbb/orn.S b/tb/qumcu/isa/rv32uzbb/orn.S new file mode 100644 index 0000000..cdfafcc --- /dev/null +++ b/tb/qumcu/isa/rv32uzbb/orn.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64uzbb/orn.S" diff --git a/tb/qumcu/isa/rv32uzbb/rev8.S b/tb/qumcu/isa/rv32uzbb/rev8.S new file mode 100644 index 0000000..2828f27 --- /dev/null +++ b/tb/qumcu/isa/rv32uzbb/rev8.S @@ -0,0 +1,75 @@ +# See LICENSE for license details. + +#***************************************************************************** +# rev8.S +#----------------------------------------------------------------------------- +# +# Test rev8 instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_R_OP( 2, rev8, 0x00000000, 0x00000000); + TEST_R_OP( 3, rev8, 0x01000000, 0x00000001); + TEST_R_OP( 4, rev8, 0x03000000, 0x00000003); + + TEST_R_OP( 5, rev8, 0x0080ffff, 0xffff8000 ); + TEST_R_OP( 6, rev8, 0x00008000, 0x00800000 ); + TEST_R_OP( 7, rev8, 0x0080ffff, 0xffff8000 ); + + TEST_R_OP( 8, rev8, 0xff7f0000, 0x00007fff); + TEST_R_OP( 9, rev8, 0xffffff7f, 0x7fffffff); + TEST_R_OP( 10, rev8, 0xffff0700, 0x0007ffff ); + + TEST_R_OP( 11, rev8, 0x00000080, 0x80000000); + TEST_R_OP( 12, rev8, 0x00501f12, 0x121f5000); + + TEST_R_OP( 13, rev8, 0x00000000, 0x00000000); + TEST_R_OP( 14, rev8, 0x0e000000, 0x0000000e); + TEST_R_OP( 15, rev8, 0x41134020, 0x20401341); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_R_SRC1_EQ_DEST( 16, rev8, 0x0d000000, 13); + TEST_R_SRC1_EQ_DEST( 17, rev8, 0x0b000000, 11); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_R_DEST_BYPASS( 18, 0, rev8, 0x0d000000, 13); + TEST_R_DEST_BYPASS( 29, 1, rev8, 0x13000000, 19); + TEST_R_DEST_BYPASS( 20, 2, rev8, 0x22000000, 34); + + #------------------------------------------------------------- + # Other tests + #------------------------------------------------------------- + + TEST_R_OP( 21, rev8, 0x00807f00, 0x007f8000 ); + TEST_R_OP( 22, rev8, 0x00808000, 0x00808000 ); + TEST_R_OP( 23, rev8, 0x00808001, 0x01808000 ); + + TEST_R_OP( 24, rev8, 0xff7f0000, 0x00007fff); + TEST_R_OP( 25, rev8, 0xffffff7f, 0x7fffffff); + TEST_R_OP( 26, rev8, 0xffff0700, 0x0007ffff); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv32uzbb/rol.S b/tb/qumcu/isa/rv32uzbb/rol.S new file mode 100644 index 0000000..a7c04fe --- /dev/null +++ b/tb/qumcu/isa/rv32uzbb/rol.S @@ -0,0 +1,97 @@ +# See LICENSE for license details. + +#***************************************************************************** +# rol.S +#----------------------------------------------------------------------------- +# +# Test rol instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, rol, 0x00000001, 0x00000001, 0 ); + TEST_RR_OP( 3, rol, 0x00000002, 0x00000001, 1 ); + TEST_RR_OP( 4, rol, 0x00000080, 0x00000001, 7 ); + TEST_RR_OP( 5, rol, 0x00004000, 0x00000001, 14 ); + TEST_RR_OP( 6, rol, 0x80000000, 0x00000001, 31 ); + + TEST_RR_OP( 7, rol, 0xffffffff, 0xffffffff, 0 ); + TEST_RR_OP( 8, rol, 0xffffffff, 0xffffffff, 1 ); + TEST_RR_OP( 9, rol, 0xffffffff, 0xffffffff, 7 ); + TEST_RR_OP( 10, rol, 0xffffffff, 0xffffffff, 14 ); + TEST_RR_OP( 11, rol, 0xffffffff, 0xffffffff, 31 ); + + TEST_RR_OP( 12, rol, 0x21212121, 0x21212121, 0 ); + TEST_RR_OP( 13, rol, 0x42424242, 0x21212121, 1 ); + TEST_RR_OP( 14, rol, 0x90909090, 0x21212121, 7 ); + TEST_RR_OP( 15, rol, 0x48484848, 0x21212121, 14 ); + TEST_RR_OP( 16, rol, 0x90909090, 0x21212121, 31 ); + + # Verify that rotates only use bottom five bits + + TEST_RR_OP( 17, rol, 0x21212121, 0x21212121, 0xffffffe0 ); + TEST_RR_OP( 18, rol, 0x42424242, 0x21212121, 0xffffffe1 ); + TEST_RR_OP( 19, rol, 0x90909090, 0x21212121, 0xffffffe7 ); + TEST_RR_OP( 20, rol, 0x48484848, 0x21212121, 0xffffffee ); + TEST_RR_OP( 21, rol, 0x90909090, 0x21212121, 0xffffffff ); + + # Verify that rotates ignore top 32 (using true 64-bit values) + + TEST_RR_OP( 44, rol, 0x12345678, 0x12345678, 0 ); + TEST_RR_OP( 45, rol, 0x23456781, 0x12345678, 4 ); + TEST_RR_OP( 46, rol, 0x92345678, 0x92345678, 0 ); + TEST_RR_OP( 47, rol, 0x93456789, 0x99345678, 4 ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 22, rol, 0x00000080, 0x00000001, 7 ); + TEST_RR_SRC2_EQ_DEST( 23, rol, 0x00004000, 0x00000001, 14 ); + TEST_RR_SRC12_EQ_DEST( 24, rol, 24, 3 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 25, 0, rol, 0x00000080, 0x00000001, 7 ); + TEST_RR_DEST_BYPASS( 26, 1, rol, 0x00004000, 0x00000001, 14 ); + TEST_RR_DEST_BYPASS( 27, 2, rol, 0x80000000, 0x00000001, 31 ); + + TEST_RR_SRC12_BYPASS( 28, 0, 0, rol, 0x00000080, 0x00000001, 7 ); + TEST_RR_SRC12_BYPASS( 29, 0, 1, rol, 0x00004000, 0x00000001, 14 ); + TEST_RR_SRC12_BYPASS( 30, 0, 2, rol, 0x80000000, 0x00000001, 31 ); + TEST_RR_SRC12_BYPASS( 31, 1, 0, rol, 0x00000080, 0x00000001, 7 ); + TEST_RR_SRC12_BYPASS( 32, 1, 1, rol, 0x00004000, 0x00000001, 14 ); + TEST_RR_SRC12_BYPASS( 33, 2, 0, rol, 0x80000000, 0x00000001, 31 ); + + TEST_RR_SRC21_BYPASS( 34, 0, 0, rol, 0x00000080, 0x00000001, 7 ); + TEST_RR_SRC21_BYPASS( 35, 0, 1, rol, 0x00004000, 0x00000001, 14 ); + TEST_RR_SRC21_BYPASS( 36, 0, 2, rol, 0x80000000, 0x00000001, 31 ); + TEST_RR_SRC21_BYPASS( 37, 1, 0, rol, 0x00000080, 0x00000001, 7 ); + TEST_RR_SRC21_BYPASS( 38, 1, 1, rol, 0x00004000, 0x00000001, 14 ); + TEST_RR_SRC21_BYPASS( 39, 2, 0, rol, 0x80000000, 0x00000001, 31 ); + + TEST_RR_ZEROSRC1( 40, rol, 0, 15 ); + TEST_RR_ZEROSRC2( 41, rol, 32, 32 ); + TEST_RR_ZEROSRC12( 42, rol, 0 ); + TEST_RR_ZERODEST( 43, rol, 1024, 2048 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv32uzbb/ror.S b/tb/qumcu/isa/rv32uzbb/ror.S new file mode 100644 index 0000000..5b57740 --- /dev/null +++ b/tb/qumcu/isa/rv32uzbb/ror.S @@ -0,0 +1,91 @@ +# See LICENSE for license details. + +#***************************************************************************** +# ror.S +#----------------------------------------------------------------------------- +# +# Test ror instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, ror, 0x00000001, 0x00000001, 0 ); + TEST_RR_OP( 3, ror, 0x80000000, 0x00000001, 1 ); + TEST_RR_OP( 4, ror, 0x02000000, 0x00000001, 7 ); + TEST_RR_OP( 5, ror, 0x00040000, 0x00000001, 14 ); + TEST_RR_OP( 6, ror, 0x00000002, 0x00000001, 31 ); + + TEST_RR_OP( 7, ror, 0xffffffff, 0xffffffff, 0 ); + TEST_RR_OP( 8, ror, 0xffffffff, 0xffffffff, 1 ); + TEST_RR_OP( 9, ror, 0xffffffff, 0xffffffff, 7 ); + TEST_RR_OP( 10, ror, 0xffffffff, 0xffffffff, 14 ); + TEST_RR_OP( 11, ror, 0xffffffff, 0xffffffff, 31 ); + + TEST_RR_OP( 12, ror, 0x21212121, 0x21212121, 0 ); + TEST_RR_OP( 13, ror, 0x90909090, 0x21212121, 1 ); + TEST_RR_OP( 14, ror, 0x42424242, 0x21212121, 7 ); + TEST_RR_OP( 15, ror, 0x84848484, 0x21212121, 14 ); + TEST_RR_OP( 16, ror, 0x42424242, 0x21212121, 31 ); + + # Verify that shifts only use bottom six(rv64) or five(rv32) bits + + TEST_RR_OP( 17, ror, 0x21212121, 0x21212121, 0xffffffc0 ); + TEST_RR_OP( 18, ror, 0x90909090, 0x21212121, 0xffffffc1 ); + TEST_RR_OP( 19, ror, 0x42424242, 0x21212121, 0xffffffc7 ); + TEST_RR_OP( 20, ror, 0x84848484, 0x21212121, 0xffffffce ); + + TEST_RR_OP( 21, ror, 0x42424242, 0x21212121, 0xffffffff ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 22, ror, 0x02000000, 0x00000001, 7 ); + TEST_RR_SRC2_EQ_DEST( 23, ror, 0x00040000, 0x00000001, 14 ); + TEST_RR_SRC12_EQ_DEST( 24, ror, 0x60000000, 3 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 25, 0, ror, 0x02000000, 0x00000001, 7 ); + TEST_RR_DEST_BYPASS( 26, 1, ror, 0x00040000, 0x00000001, 14 ); + TEST_RR_DEST_BYPASS( 27, 2, ror, 0x00000002, 0x00000001, 31 ); + + TEST_RR_SRC12_BYPASS( 28, 0, 0, ror, 0x02000000, 0x00000001, 7 ); + TEST_RR_SRC12_BYPASS( 29, 0, 1, ror, 0x00040000, 0x00000001, 14 ); + TEST_RR_SRC12_BYPASS( 30, 0, 2, ror, 0x00000002, 0x00000001, 31 ); + TEST_RR_SRC12_BYPASS( 31, 1, 0, ror, 0x02000000, 0x00000001, 7 ); + TEST_RR_SRC12_BYPASS( 32, 1, 1, ror, 0x00040000, 0x00000001, 14 ); + TEST_RR_SRC12_BYPASS( 33, 2, 0, ror, 0x00000002, 0x00000001, 31 ); + + TEST_RR_SRC21_BYPASS( 34, 0, 0, ror, 0x02000000, 0x00000001, 7 ); + TEST_RR_SRC21_BYPASS( 35, 0, 1, ror, 0x00040000, 0x00000001, 14 ); + TEST_RR_SRC21_BYPASS( 36, 0, 2, ror, 0x00000002, 0x00000001, 31 ); + TEST_RR_SRC21_BYPASS( 37, 1, 0, ror, 0x02000000, 0x00000001, 7 ); + TEST_RR_SRC21_BYPASS( 38, 1, 1, ror, 0x00040000, 0x00000001, 14 ); + TEST_RR_SRC21_BYPASS( 39, 2, 0, ror, 0x00000002, 0x00000001, 31 ); + + TEST_RR_ZEROSRC1( 40, ror, 0, 15 ); + TEST_RR_ZEROSRC2( 41, ror, 32, 32 ); + TEST_RR_ZEROSRC12( 42, ror, 0 ); + TEST_RR_ZERODEST( 43, ror, 1024, 2048 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv32uzbb/rori.S b/tb/qumcu/isa/rv32uzbb/rori.S new file mode 100644 index 0000000..c98ed85 --- /dev/null +++ b/tb/qumcu/isa/rv32uzbb/rori.S @@ -0,0 +1,68 @@ +# See LICENSE for license details. + +#***************************************************************************** +# rori.S +#----------------------------------------------------------------------------- +# +# Test rori instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_IMM_OP( 2, rori, 0x00000001, 0x00000001, 0 ); + TEST_IMM_OP( 3, rori, 0x80000000, 0x00000001, 1 ); + TEST_IMM_OP( 4, rori, 0x02000000, 0x00000001, 7 ); + TEST_IMM_OP( 5, rori, 0x00040000, 0x00000001, 14 ); + TEST_IMM_OP( 6, rori, 0x00000002, 0x00000001, 31 ); + + TEST_IMM_OP( 7, rori, 0xffffffff, 0xffffffff, 0 ); + TEST_IMM_OP( 8, rori, 0xffffffff, 0xffffffff, 1 ); + TEST_IMM_OP( 9, rori, 0xffffffff, 0xffffffff, 7 ); + TEST_IMM_OP( 10, rori, 0xffffffff, 0xffffffff, 14 ); + TEST_IMM_OP( 11, rori, 0xffffffff, 0xffffffff, 31 ); + + TEST_IMM_OP( 12, rori, 0x21212121, 0x21212121, 0 ); + TEST_IMM_OP( 13, rori, 0x90909090, 0x21212121, 1 ); + TEST_IMM_OP( 14, rori, 0x42424242, 0x21212121, 7 ); + TEST_IMM_OP( 15, rori, 0x84848484, 0x21212121, 14 ); + TEST_IMM_OP( 16, rori, 0x42424242, 0x21212121, 31 ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_IMM_SRC1_EQ_DEST( 20, rori, 0x02000000, 0x00000001, 7 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_IMM_DEST_BYPASS( 21, 0, rori, 0x02000000, 0x00000001, 7 ); + TEST_IMM_DEST_BYPASS( 22, 1, rori, 0x00040000, 0x00000001, 14 ); + TEST_IMM_DEST_BYPASS( 23, 2, rori, 0x00000002, 0x00000001, 31 ); + + TEST_IMM_SRC1_BYPASS( 24, 0, rori, 0x02000000, 0x00000001, 7 ); + TEST_IMM_SRC1_BYPASS( 25, 1, rori, 0x00040000, 0x00000001, 14 ); + TEST_IMM_SRC1_BYPASS( 26, 2, rori, 0x00000002, 0x00000001, 31 ); + + TEST_IMM_ZEROSRC1( 27, rori, 0, 31 ); + TEST_IMM_ZERODEST( 28, rori, 33, 20 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv32uzbb/sext_b.S b/tb/qumcu/isa/rv32uzbb/sext_b.S new file mode 100644 index 0000000..f73e107 --- /dev/null +++ b/tb/qumcu/isa/rv32uzbb/sext_b.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64uzbb/sext_b.S" diff --git a/tb/qumcu/isa/rv32uzbb/sext_h.S b/tb/qumcu/isa/rv32uzbb/sext_h.S new file mode 100644 index 0000000..d4b4206 --- /dev/null +++ b/tb/qumcu/isa/rv32uzbb/sext_h.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64uzbb/sext_h.S" diff --git a/tb/qumcu/isa/rv32uzbb/xnor.S b/tb/qumcu/isa/rv32uzbb/xnor.S new file mode 100644 index 0000000..c5e453a --- /dev/null +++ b/tb/qumcu/isa/rv32uzbb/xnor.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64uzbb/xnor.S" diff --git a/tb/qumcu/isa/rv32uzbb/zext_h.S b/tb/qumcu/isa/rv32uzbb/zext_h.S new file mode 100644 index 0000000..d339ccc --- /dev/null +++ b/tb/qumcu/isa/rv32uzbb/zext_h.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64uzbb/zext_h.S" diff --git a/tb/qumcu/isa/rv32uzbc/Makefrag b/tb/qumcu/isa/rv32uzbc/Makefrag new file mode 100644 index 0000000..7dcf6d5 --- /dev/null +++ b/tb/qumcu/isa/rv32uzbc/Makefrag @@ -0,0 +1,14 @@ +#======================================================================= +# Makefrag for rv32uzbc tests +#----------------------------------------------------------------------- + +rv32uzbc_sc_tests = \ + clmul \ + clmulh \ + clmulr \ + +rv32uzbc_p_tests = $(addprefix rv32uzbc-p-, $(rv32uzbc_sc_tests)) +rv32uzbc_v_tests = $(addprefix rv32uzbc-v-, $(rv32uzbc_sc_tests)) +rv32uzbc_ps_tests = $(addprefix rv32uzbc-ps-, $(rv32uzbc_sc_tests)) + +spike_tests += $(rv32uzbc_p_tests) $(rv32uzbc_v_tests) diff --git a/tb/qumcu/isa/rv32uzbc/clmul.S b/tb/qumcu/isa/rv32uzbc/clmul.S new file mode 100644 index 0000000..8a50300 --- /dev/null +++ b/tb/qumcu/isa/rv32uzbc/clmul.S @@ -0,0 +1,84 @@ +# See LICENSE for license details. + +#***************************************************************************** +# clmul.S +#----------------------------------------------------------------------------- +# +# Test clmul instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP(32, clmul, 0x00005a00, 0x00007e00, 0xb6db6db7 ); + TEST_RR_OP(33, clmul, 0x00005b40, 0x00007fc0, 0xb6db6db7 ); + + TEST_RR_OP( 2, clmul, 0x00000000, 0x00000000, 0x00000000 ); + TEST_RR_OP( 3, clmul, 0x00000001, 0x00000001, 0x00000001 ); + TEST_RR_OP( 4, clmul, 0x00000009, 0x00000003, 0x00000007 ); + + TEST_RR_OP( 5, clmul, 0x00000000, 0x00000000, 0xffff8000 ); + TEST_RR_OP( 6, clmul, 0x00000000, 0x80000000, 0x00000000 ); + TEST_RR_OP( 7, clmul, 0x00000000, 0x80000000, 0xffff8000 ); + + TEST_RR_OP(30, clmul, 0xfffc324f, 0xaaaaaaab, 0x0002fe7d ); + TEST_RR_OP(31, clmul, 0xfffc324f, 0x0002fe7d, 0xaaaaaaab ); + + TEST_RR_OP(34, clmul, 0x00000000, 0xff000000, 0xff000000 ); + + TEST_RR_OP(35, clmul, 0x55555555, 0xffffffff, 0xffffffff ); + TEST_RR_OP(36, clmul, 0xffffffff, 0xffffffff, 0x00000001 ); + TEST_RR_OP(37, clmul, 0xffffffff, 0x00000001, 0xffffffff ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 8, clmul, 0x7f, 13, 11 ); + TEST_RR_SRC2_EQ_DEST( 9, clmul, 0x62, 14, 11 ); + TEST_RR_SRC12_EQ_DEST( 10, clmul, 0x51, 13 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 11, 0, clmul, 0x7f, 13, 11 ); + TEST_RR_DEST_BYPASS( 12, 1, clmul, 0x62, 14, 11 ); + TEST_RR_DEST_BYPASS( 13, 2, clmul, 0x69, 15, 11 ); + + TEST_RR_SRC12_BYPASS( 14, 0, 0, clmul, 0x7f, 13, 11 ); + TEST_RR_SRC12_BYPASS( 15, 0, 1, clmul, 0x62, 14, 11 ); + TEST_RR_SRC12_BYPASS( 16, 0, 2, clmul, 0x69, 15, 11 ); + TEST_RR_SRC12_BYPASS( 17, 1, 0, clmul, 0x7f, 13, 11 ); + TEST_RR_SRC12_BYPASS( 18, 1, 1, clmul, 0x62, 14, 11 ); + TEST_RR_SRC12_BYPASS( 19, 2, 0, clmul, 0x69, 15, 11 ); + + TEST_RR_SRC21_BYPASS( 20, 0, 0, clmul, 0x7f, 13, 11 ); + TEST_RR_SRC21_BYPASS( 21, 0, 1, clmul, 0x62, 14, 11 ); + TEST_RR_SRC21_BYPASS( 22, 0, 2, clmul, 0x69, 15, 11 ); + TEST_RR_SRC21_BYPASS( 23, 1, 0, clmul, 0x7f, 13, 11 ); + TEST_RR_SRC21_BYPASS( 24, 1, 1, clmul, 0x62, 14, 11 ); + TEST_RR_SRC21_BYPASS( 25, 2, 0, clmul, 0x69, 15, 11 ); + + TEST_RR_ZEROSRC1( 26, clmul, 0, 31 ); + TEST_RR_ZEROSRC2( 27, clmul, 0, 32 ); + TEST_RR_ZEROSRC12( 28, clmul, 0 ); + TEST_RR_ZERODEST( 29, clmul, 33, 34 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv32uzbc/clmulh.S b/tb/qumcu/isa/rv32uzbc/clmulh.S new file mode 100644 index 0000000..b5fde88 --- /dev/null +++ b/tb/qumcu/isa/rv32uzbc/clmulh.S @@ -0,0 +1,84 @@ +# See LICENSE for license details. + +#***************************************************************************** +# clmulh.S +#----------------------------------------------------------------------------- +# +# Test clmulh instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP(32, clmulh, 0x00003600, 0x00007e00, 0xb6db6db7 ); + TEST_RR_OP(33, clmulh, 0x000036c0, 0x00007fc0, 0xb6db6db7 ); + + TEST_RR_OP( 2, clmulh, 0x00000000, 0x00000000, 0x00000000 ); + TEST_RR_OP( 3, clmulh, 0x00000000, 0x00000001, 0x00000001 ); + TEST_RR_OP( 4, clmulh, 0x00000000, 0x00000003, 0x00000007 ); + + TEST_RR_OP( 5, clmulh, 0x00000000, 0x00000000, 0xffff8000 ); + TEST_RR_OP( 6, clmulh, 0x00000000, 0x80000000, 0x00000000 ); + TEST_RR_OP( 7, clmulh, 0x7fffc000, 0x80000000, 0xffff8000 ); + + TEST_RR_OP(30, clmulh, 0x000133cd, 0xaaaaaaab, 0x0002fe7d ); + TEST_RR_OP(31, clmulh, 0x000133cd, 0x0002fe7d, 0xaaaaaaab ); + + TEST_RR_OP(34, clmulh, 0x55550000, 0xff000000, 0xff000000 ); + + TEST_RR_OP(35, clmulh, 0x55555555, 0xffffffff, 0xffffffff ); + TEST_RR_OP(36, clmulh, 0x00000000, 0xffffffff, 0x00000001 ); + TEST_RR_OP(37, clmulh, 0x00000000, 0x00000001, 0xffffffff ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 8, clmulh, 0, 13, 11 ); + TEST_RR_SRC2_EQ_DEST( 9, clmulh, 0, 14, 11 ); + TEST_RR_SRC12_EQ_DEST( 10, clmulh, 0, 13 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 11, 0, clmulh, 0, 13, 11 ); + TEST_RR_DEST_BYPASS( 12, 1, clmulh, 0, 14, 11 ); + TEST_RR_DEST_BYPASS( 13, 2, clmulh, 0, 15, 11 ); + + TEST_RR_SRC12_BYPASS( 14, 0, 0, clmulh, 0, 13, 11 ); + TEST_RR_SRC12_BYPASS( 15, 0, 1, clmulh, 0, 14, 11 ); + TEST_RR_SRC12_BYPASS( 16, 0, 2, clmulh, 0, 15, 11 ); + TEST_RR_SRC12_BYPASS( 17, 1, 0, clmulh, 0, 13, 11 ); + TEST_RR_SRC12_BYPASS( 18, 1, 1, clmulh, 0, 14, 11 ); + TEST_RR_SRC12_BYPASS( 19, 2, 0, clmulh, 0, 15, 11 ); + + TEST_RR_SRC21_BYPASS( 20, 0, 0, clmulh, 0, 13, 11 ); + TEST_RR_SRC21_BYPASS( 21, 0, 1, clmulh, 0, 14, 11 ); + TEST_RR_SRC21_BYPASS( 22, 0, 2, clmulh, 0, 15, 11 ); + TEST_RR_SRC21_BYPASS( 23, 1, 0, clmulh, 0, 13, 11 ); + TEST_RR_SRC21_BYPASS( 24, 1, 1, clmulh, 0, 14, 11 ); + TEST_RR_SRC21_BYPASS( 25, 2, 0, clmulh, 0, 15, 11 ); + + TEST_RR_ZEROSRC1( 26, clmulh, 0, 31 ); + TEST_RR_ZEROSRC2( 27, clmulh, 0, 32 ); + TEST_RR_ZEROSRC12( 28, clmulh, 0 ); + TEST_RR_ZERODEST( 29, clmulh, 33, 34 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv32uzbc/clmulr.S b/tb/qumcu/isa/rv32uzbc/clmulr.S new file mode 100644 index 0000000..dc255ec --- /dev/null +++ b/tb/qumcu/isa/rv32uzbc/clmulr.S @@ -0,0 +1,84 @@ +# See LICENSE for license details. + +#***************************************************************************** +# clmulr.S +#----------------------------------------------------------------------------- +# +# Test clmulr instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP(32, clmulr, 0x00006c00, 0x00007e00, 0xb6db6db7 ); + TEST_RR_OP(33, clmulr, 0x00006d80, 0x00007fc0, 0xb6db6db7 ); + + TEST_RR_OP( 2, clmulr, 0x00000000, 0x00000000, 0x00000000 ); + TEST_RR_OP( 3, clmulr, 0x00000000, 0x00000001, 0x00000001 ); + TEST_RR_OP( 4, clmulr, 0x00000000, 0x00000003, 0x00000007 ); + + TEST_RR_OP( 5, clmulr, 0x00000000, 0x00000000, 0xffff8000 ); + TEST_RR_OP( 6, clmulr, 0x00000000, 0x80000000, 0x00000000 ); + TEST_RR_OP( 7, clmulr, 0xffff8000, 0x80000000, 0xffff8000 ); + + TEST_RR_OP(30, clmulr, 0x0002679b, 0xaaaaaaab, 0x0002fe7d ); + TEST_RR_OP(31, clmulr, 0x0002679b, 0x0002fe7d, 0xaaaaaaab ); + + TEST_RR_OP(34, clmulr, 0xaaaa0000, 0xff000000, 0xff000000 ); + + TEST_RR_OP(35, clmulr, 0xaaaaaaaa, 0xffffffff, 0xffffffff ); + TEST_RR_OP(36, clmulr, 0x00000001, 0xffffffff, 0x00000001 ); + TEST_RR_OP(37, clmulr, 0x00000001, 0x00000001, 0xffffffff ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 8, clmulr, 0, 13, 11 ); + TEST_RR_SRC2_EQ_DEST( 9, clmulr, 0, 14, 11 ); + TEST_RR_SRC12_EQ_DEST( 10, clmulr, 0, 13 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 11, 0, clmulr, 0, 13, 11 ); + TEST_RR_DEST_BYPASS( 12, 1, clmulr, 0, 14, 11 ); + TEST_RR_DEST_BYPASS( 13, 2, clmulr, 0, 15, 11 ); + + TEST_RR_SRC12_BYPASS( 14, 0, 0, clmulr, 0, 13, 11 ); + TEST_RR_SRC12_BYPASS( 15, 0, 1, clmulr, 0, 14, 11 ); + TEST_RR_SRC12_BYPASS( 16, 0, 2, clmulr, 0, 15, 11 ); + TEST_RR_SRC12_BYPASS( 17, 1, 0, clmulr, 0, 13, 11 ); + TEST_RR_SRC12_BYPASS( 18, 1, 1, clmulr, 0, 14, 11 ); + TEST_RR_SRC12_BYPASS( 19, 2, 0, clmulr, 0, 15, 11 ); + + TEST_RR_SRC21_BYPASS( 20, 0, 0, clmulr, 0, 13, 11 ); + TEST_RR_SRC21_BYPASS( 21, 0, 1, clmulr, 0, 14, 11 ); + TEST_RR_SRC21_BYPASS( 22, 0, 2, clmulr, 0, 15, 11 ); + TEST_RR_SRC21_BYPASS( 23, 1, 0, clmulr, 0, 13, 11 ); + TEST_RR_SRC21_BYPASS( 24, 1, 1, clmulr, 0, 14, 11 ); + TEST_RR_SRC21_BYPASS( 25, 2, 0, clmulr, 0, 15, 11 ); + + TEST_RR_ZEROSRC1( 26, clmulr, 0, 31 ); + TEST_RR_ZEROSRC2( 27, clmulr, 0, 32 ); + TEST_RR_ZEROSRC12( 28, clmulr, 0 ); + TEST_RR_ZERODEST( 29, clmulr, 33, 34 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv32uzbs/Makefrag b/tb/qumcu/isa/rv32uzbs/Makefrag new file mode 100644 index 0000000..7af7c42 --- /dev/null +++ b/tb/qumcu/isa/rv32uzbs/Makefrag @@ -0,0 +1,15 @@ +#======================================================================= +# Makefrag for rv32uzbs tests +#----------------------------------------------------------------------- + +rv32uzbs_sc_tests = \ + bclr bclri \ + bext bexti \ + binv binvi \ + bset bseti \ + +rv32uzbs_p_tests = $(addprefix rv32uzbs-p-, $(rv32uzbs_sc_tests)) +rv32uzbs_v_tests = $(addprefix rv32uzbs-v-, $(rv32uzbs_sc_tests)) +rv32uzbs_ps_tests = $(addprefix rv32uzbs-ps-, $(rv32uzbs_sc_tests)) + +spike_tests += $(rv32uzbs_p_tests) $(rv32uzbs_v_tests) diff --git a/tb/qumcu/isa/rv32uzbs/bclr.S b/tb/qumcu/isa/rv32uzbs/bclr.S new file mode 100644 index 0000000..10f7e50 --- /dev/null +++ b/tb/qumcu/isa/rv32uzbs/bclr.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64uzbs/bclr.S" diff --git a/tb/qumcu/isa/rv32uzbs/bclri.S b/tb/qumcu/isa/rv32uzbs/bclri.S new file mode 100644 index 0000000..2f709d8 --- /dev/null +++ b/tb/qumcu/isa/rv32uzbs/bclri.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64uzbs/bclri.S" diff --git a/tb/qumcu/isa/rv32uzbs/bext.S b/tb/qumcu/isa/rv32uzbs/bext.S new file mode 100644 index 0000000..0f838e5 --- /dev/null +++ b/tb/qumcu/isa/rv32uzbs/bext.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64uzbs/bext.S" diff --git a/tb/qumcu/isa/rv32uzbs/bexti.S b/tb/qumcu/isa/rv32uzbs/bexti.S new file mode 100644 index 0000000..91ee2d6 --- /dev/null +++ b/tb/qumcu/isa/rv32uzbs/bexti.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64uzbs/bexti.S" diff --git a/tb/qumcu/isa/rv32uzbs/binv.S b/tb/qumcu/isa/rv32uzbs/binv.S new file mode 100644 index 0000000..55ea39b --- /dev/null +++ b/tb/qumcu/isa/rv32uzbs/binv.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64uzbs/binv.S" diff --git a/tb/qumcu/isa/rv32uzbs/binvi.S b/tb/qumcu/isa/rv32uzbs/binvi.S new file mode 100644 index 0000000..5874363 --- /dev/null +++ b/tb/qumcu/isa/rv32uzbs/binvi.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64uzbs/binvi.S" diff --git a/tb/qumcu/isa/rv32uzbs/bset.S b/tb/qumcu/isa/rv32uzbs/bset.S new file mode 100644 index 0000000..4220823 --- /dev/null +++ b/tb/qumcu/isa/rv32uzbs/bset.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64uzbs/bset.S" diff --git a/tb/qumcu/isa/rv32uzbs/bseti.S b/tb/qumcu/isa/rv32uzbs/bseti.S new file mode 100644 index 0000000..4a6179e --- /dev/null +++ b/tb/qumcu/isa/rv32uzbs/bseti.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64uzbs/bseti.S" diff --git a/tb/qumcu/isa/rv32uzfh/Makefrag b/tb/qumcu/isa/rv32uzfh/Makefrag new file mode 100644 index 0000000..f24cdf2 --- /dev/null +++ b/tb/qumcu/isa/rv32uzfh/Makefrag @@ -0,0 +1,10 @@ +#======================================================================= +# Makefrag for rv32uzfh tests +#----------------------------------------------------------------------- + +rv32uzfh_sc_tests = \ + fadd fdiv fclass fcmp fcvt fcvt_w fmadd fmin \ + ldst move recoding \ + +rv32uzfh_p_tests = $(addprefix rv32uzfh-p-, $(rv32uzfh_sc_tests)) +rv32uzfh_v_tests = $(addprefix rv32uzfh-v-, $(rv32uzfh_sc_tests)) diff --git a/tb/qumcu/isa/rv32uzfh/fadd.S b/tb/qumcu/isa/rv32uzfh/fadd.S new file mode 100644 index 0000000..11dba9d --- /dev/null +++ b/tb/qumcu/isa/rv32uzfh/fadd.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64UH +#define RVTEST_RV64UH RVTEST_RV32UH + +#include "../rv64uzfh/fadd.S" diff --git a/tb/qumcu/isa/rv32uzfh/fclass.S b/tb/qumcu/isa/rv32uzfh/fclass.S new file mode 100644 index 0000000..b1fcf24 --- /dev/null +++ b/tb/qumcu/isa/rv32uzfh/fclass.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64UH +#define RVTEST_RV64UH RVTEST_RV32UH + +#include "../rv64uzfh/fclass.S" diff --git a/tb/qumcu/isa/rv32uzfh/fcmp.S b/tb/qumcu/isa/rv32uzfh/fcmp.S new file mode 100644 index 0000000..9793dea --- /dev/null +++ b/tb/qumcu/isa/rv32uzfh/fcmp.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64UH +#define RVTEST_RV64UH RVTEST_RV32UH + +#include "../rv64uzfh/fcmp.S" diff --git a/tb/qumcu/isa/rv32uzfh/fcvt.S b/tb/qumcu/isa/rv32uzfh/fcvt.S new file mode 100644 index 0000000..2b5bf5a --- /dev/null +++ b/tb/qumcu/isa/rv32uzfh/fcvt.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64UF +#define RVTEST_RV64UF RVTEST_RV32UF + +#include "../rv64uzfh/fcvt.S" diff --git a/tb/qumcu/isa/rv32uzfh/fcvt_w.S b/tb/qumcu/isa/rv32uzfh/fcvt_w.S new file mode 100644 index 0000000..d532b35 --- /dev/null +++ b/tb/qumcu/isa/rv32uzfh/fcvt_w.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64UF +#define RVTEST_RV64UF RVTEST_RV32UF + +#include "../rv64uzfh/fcvt_w.S" diff --git a/tb/qumcu/isa/rv32uzfh/fdiv.S b/tb/qumcu/isa/rv32uzfh/fdiv.S new file mode 100644 index 0000000..2bf43a7 --- /dev/null +++ b/tb/qumcu/isa/rv32uzfh/fdiv.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64UH +#define RVTEST_RV64UH RVTEST_RV32UH + +#include "../rv64uzfh/fdiv.S" diff --git a/tb/qumcu/isa/rv32uzfh/fmadd.S b/tb/qumcu/isa/rv32uzfh/fmadd.S new file mode 100644 index 0000000..2a5ea91 --- /dev/null +++ b/tb/qumcu/isa/rv32uzfh/fmadd.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64UH +#define RVTEST_RV64UH RVTEST_RV32UH + +#include "../rv64uzfh/fmadd.S" diff --git a/tb/qumcu/isa/rv32uzfh/fmin.S b/tb/qumcu/isa/rv32uzfh/fmin.S new file mode 100644 index 0000000..360e02f --- /dev/null +++ b/tb/qumcu/isa/rv32uzfh/fmin.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64UH +#define RVTEST_RV64UH RVTEST_RV32UH + +#include "../rv64uzfh/fmin.S" diff --git a/tb/qumcu/isa/rv32uzfh/ldst.S b/tb/qumcu/isa/rv32uzfh/ldst.S new file mode 100644 index 0000000..7f09872 --- /dev/null +++ b/tb/qumcu/isa/rv32uzfh/ldst.S @@ -0,0 +1,38 @@ +# See LICENSE for license details. + +#***************************************************************************** +# ldst.S +#----------------------------------------------------------------------------- +# +# This test verifies that flw, fld, fsw, and fsd work properly. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32UF +RVTEST_CODE_BEGIN + + TEST_CASE(2, a0, 0xcafe4000, la a1, tdat; flh f1, 4(a1); fsh f1, 20(a1); lw a0, 20(a1)) + TEST_CASE(3, a0, 0xabadbf80, la a1, tdat; flh f1, 0(a1); fsh f1, 24(a1); lw a0, 24(a1)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +tdat: +.word 0xbf80bf80 +.word 0x40004000 +.word 0x40404040 +.word 0xc080c080 +.word 0xdeadbeef +.word 0xcafebabe +.word 0xabad1dea +.word 0x1337d00d + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv32uzfh/move.S b/tb/qumcu/isa/rv32uzfh/move.S new file mode 100644 index 0000000..b399a76 --- /dev/null +++ b/tb/qumcu/isa/rv32uzfh/move.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64UH +#define RVTEST_RV64UH RVTEST_RV32UH + +#include "../rv64uzfh/move.S" diff --git a/tb/qumcu/isa/rv32uzfh/recoding.S b/tb/qumcu/isa/rv32uzfh/recoding.S new file mode 100644 index 0000000..271a5cb --- /dev/null +++ b/tb/qumcu/isa/rv32uzfh/recoding.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64UH +#define RVTEST_RV64UH RVTEST_RV32UH + +#include "../rv64uzfh/recoding.S" diff --git a/tb/qumcu/isa/rv64mi/Makefrag b/tb/qumcu/isa/rv64mi/Makefrag new file mode 100644 index 0000000..a6f23e4 --- /dev/null +++ b/tb/qumcu/isa/rv64mi/Makefrag @@ -0,0 +1,23 @@ +#======================================================================= +# Makefrag for rv64mi tests +#----------------------------------------------------------------------- + +rv64mi_sc_tests = \ + access \ + breakpoint \ + csr \ + mcsr \ + illegal \ + ma_fetch \ + ma_addr \ + scall \ + sbreak \ + ld-misaligned \ + lw-misaligned \ + lh-misaligned \ + sh-misaligned \ + sw-misaligned \ + sd-misaligned \ + zicntr \ + +rv64mi_p_tests = $(addprefix rv64mi-p-, $(rv64mi_sc_tests)) diff --git a/tb/qumcu/isa/rv64mi/access.S b/tb/qumcu/isa/rv64mi/access.S new file mode 100644 index 0000000..40a28d3 --- /dev/null +++ b/tb/qumcu/isa/rv64mi/access.S @@ -0,0 +1,70 @@ +# See LICENSE for license details. + +#***************************************************************************** +# access.S +#----------------------------------------------------------------------------- +# +# Test access-exception behavior. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64M +RVTEST_CODE_BEGIN + + .align 2 + + # Flipping just the MSB should result in an illegal address for RV64. + la t2, fail + li t0, 1 << (__riscv_xlen - 1) + xor t0, t0, t2 + + # jalr to an illegal address should commit (hence should write rd). + # after the pc is set to rs1, an access exception should be raised. + li TESTNUM, 2 + li t1, CAUSE_FETCH_ACCESS + la s1, 1f + li t2, 0 + jalr t2, t0 +1: + + # A load to an illegal address should not commit. + li TESTNUM, 3 + li t1, CAUSE_LOAD_ACCESS + la s1, 1f + mv t2, s1 + lb t2, (t0) + j fail +1: + + j pass + + TEST_PASSFAIL + + .align 2 + .global mtvec_handler +mtvec_handler: + li a0, 2 + beq TESTNUM, a0, 2f + li a0, 3 + beq TESTNUM, a0, 2f + j fail + +2: + bne t2, s1, fail + + csrr t2, mcause + bne t2, t1, fail + + csrw mepc, s1 + mret + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64mi/breakpoint.S b/tb/qumcu/isa/rv64mi/breakpoint.S new file mode 100644 index 0000000..153963a --- /dev/null +++ b/tb/qumcu/isa/rv64mi/breakpoint.S @@ -0,0 +1,142 @@ +# See LICENSE for license details. + +#***************************************************************************** +# breakpoint.S +#----------------------------------------------------------------------------- +# +# Test breakpoints, if they are implemented. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64M +RVTEST_CODE_BEGIN + + # Set up breakpoint to trap on M-mode fetches. + li TESTNUM, 2 + + # Set tcontrol.mte, otherwise breakpoints are disabled. This may trap, + # because tcontrol is an optional register. + la a0, 1f + csrrw a0, mtvec, a0 + li a1, 0x8 + csrs tcontrol, a1 +.p2align 2 +1: + csrw mtvec, a0 + + # Enable interrupts; see https://github.com/riscv/riscv-debug-spec/blob/f510a7dd33317d0eee0f26b4fa082cd43a5ac7ea/Sdtrig.tex#L213-L214 + csrsi mstatus, MSTATUS_MIE + + # Skip tselect if hard-wired. + csrw tselect, x0 + csrr a1, tselect + bne x0, a1, pass + + la a2, 1f + csrw tdata2, a2 + li a0, (2 << (__riscv_xlen - 4)) | MCONTROL_M | MCONTROL_EXECUTE + csrw tdata1, a0 + # Skip if breakpoint type is unsupported. + csrr a1, tdata1 + bne a0, a1, 2f + .align 2 +1: + # Trap handler should skip this instruction. + beqz x0, fail + + # Make sure reads don't trap. + li TESTNUM, 3 + lw a0, (a2) + +2: + # Set up breakpoint to trap on M-mode reads. + li TESTNUM, 4 + li a0, (2 << (__riscv_xlen - 4)) | MCONTROL_M | MCONTROL_LOAD + csrw tdata1, a0 + # Skip if breakpoint type is unsupported. + csrr a1, tdata1 + bne a0, a1, 2f + la a2, data1 + csrw tdata2, a2 + + # Trap handler should skip this instruction. + lw a2, (a2) + beqz a2, fail + + # Make sure writes don't trap. + li TESTNUM, 5 + sw x0, (a2) + +2: + # Set up breakpoint to trap on M-mode stores. + li TESTNUM, 6 + li a0, (2 << (__riscv_xlen - 4)) | MCONTROL_M | MCONTROL_STORE + csrw tdata1, a0 + # Skip if breakpoint type is unsupported. + csrr a1, tdata1 + bne a0, a1, 2f + + # Trap handler should skip this instruction. + sw a2, (a2) + + # Make sure store didn't succeed. + li TESTNUM, 7 + lw a2, (a2) + bnez a2, fail + + # Try to set up a second breakpoint. + li a0, 1 + csrw tselect, a0 + csrr a1, tselect + bne a0, a1, pass + + li a0, (2 << (__riscv_xlen - 4)) | MCONTROL_M | MCONTROL_LOAD + csrw tdata1, a0 + la a3, data2 + csrw tdata2, a3 + + # Make sure the second breakpoint triggers. + li TESTNUM, 8 + lw a3, (a3) + beqz a3, fail + + # Make sure the first breakpoint still triggers. + li TESTNUM, 10 + la a2, data1 + sw a2, (a2) + li TESTNUM, 11 + lw a2, (a2) + bnez a2, fail + +2: + TEST_PASSFAIL + + .align 2 + .global mtvec_handler +mtvec_handler: + # Only even-numbered tests should trap. + andi t0, TESTNUM, 1 + bnez t0, fail + + li t0, CAUSE_BREAKPOINT + csrr t1, mcause + bne t0, t1, fail + + csrr t0, mepc + addi t0, t0, 4 + csrw mepc, t0 + mret + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +data1: .word 0 +data2: .word 0 + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64mi/csr.S b/tb/qumcu/isa/rv64mi/csr.S new file mode 100644 index 0000000..77e7619 --- /dev/null +++ b/tb/qumcu/isa/rv64mi/csr.S @@ -0,0 +1,8 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64S +#define RVTEST_RV64S RVTEST_RV64M +#define __MACHINE_MODE + +#include "../rv64si/csr.S" diff --git a/tb/qumcu/isa/rv64mi/illegal.S b/tb/qumcu/isa/rv64mi/illegal.S new file mode 100644 index 0000000..fb6643b --- /dev/null +++ b/tb/qumcu/isa/rv64mi/illegal.S @@ -0,0 +1,215 @@ +# See LICENSE for license details. + +#***************************************************************************** +# illegal.S +#----------------------------------------------------------------------------- +# +# Test illegal instruction trap. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64M +RVTEST_CODE_BEGIN + + .align 2 + .option norvc + + li TESTNUM, 2 +bad2: + .word 0 + j fail + + # Skip the rest of the test if S-mode is not present. + li t0, MSTATUS_MPP + csrc mstatus, t0 + li t1, (MSTATUS_MPP & -MSTATUS_MPP) * PRV_S + csrs mstatus, t1 + csrr t2, mstatus + and t2, t2, t0 + bne t1, t2, pass + + # Test vectored interrupts if they are supported. +test_vectored_interrupts: + csrwi mip, MIP_SSIP + csrwi mie, MIP_SSIP + la t0, mtvec_handler + 1 + csrrw s0, mtvec, t0 + csrr t0, mtvec + andi t0, t0, 1 + beqz t0, msip + csrsi mstatus, MSTATUS_MIE +1: + j 1b +msip: + csrw mtvec, s0 + + # Delegate supervisor software interrupts so WFI won't stall. + csrwi mideleg, MIP_SSIP + # Enter supervisor mode. + la t0, 1f + csrw mepc, t0 + li t0, MSTATUS_MPP + csrc mstatus, t0 + li t1, (MSTATUS_MPP & -MSTATUS_MPP) * PRV_S + csrs mstatus, t1 + mret + +1: + # Make sure WFI doesn't trap when TW=0. + wfi + + # Check if paging is supported (Set SUM & MXR and read it back) + and t0, t0, zero + li t0, (SSTATUS_SUM | SSTATUS_MXR) + csrc sstatus, t0 + and t1, t1, zero + li t1, (SSTATUS_SUM | SSTATUS_MXR) + csrs sstatus, t1 + csrr t2, sstatus + and t2, t2, t0 + beqz t2, bare_s_1 + csrc sstatus, t0 + + # Make sure SFENCE.VMA and sptbr don't trap when TVM=0. + sfence.vma + csrr t0, sptbr +bad5: + .word 0 + j fail + +bad6: + # Make sure SFENCE.VMA and sptbr do trap when TVM=1. + sfence.vma + j fail +bad7: + csrr t0, sptbr + j fail + +test_tsr: + # Make sure SRET doesn't trap when TSR=0. + la t0, bad8 + csrw sepc, t0 + li t0, SSTATUS_SPP + csrs sstatus, t0 + li t0, SSTATUS_SPIE + csrc sstatus, t0 + sret +bad8: + .word 0 + j fail + + # Make sure SRET does trap when TSR=1. + la t0, 1f + csrw sepc, t0 +bad9: + sret +1: + j fail + j skip_bare_s + +bare_s_1: + # Make sure SFENCE.VMA trap when TVM=0. + sfence.vma + j fail + +bare_s_2: + # Set TVM=1. TVM should stay 0 and SFENCE.VMA should still trap + sfence.vma + j fail + + # And access to satp should not trap + csrr t0, sptbr +bare_s_3: + .word 0 + j fail + j test_tsr + +skip_bare_s: + TEST_PASSFAIL + + .align 8 + .global mtvec_handler +mtvec_handler: + j synchronous_exception + j msip + j fail + j fail + j fail + j fail + j fail + j fail + j fail + j fail + j fail + j fail + j fail + j fail + j fail + j fail + +synchronous_exception: + li t1, CAUSE_ILLEGAL_INSTRUCTION + csrr t0, mcause + bne t0, t1, fail + csrr t0, mepc + + # Make sure mtval contains either 0 or the instruction word. + csrr t2, mbadaddr + beqz t2, 1f + lhu t1, 0(t0) + xor t2, t2, t1 + lhu t1, 2(t0) + slli t1, t1, 16 + xor t2, t2, t1 + bnez t2, fail +1: + + la t1, bad2 + beq t0, t1, 2f + la t1, bad5 + beq t0, t1, 5f + la t1, bad6 + beq t0, t1, 6f + la t1, bad7 + beq t0, t1, 7f + la t1, bad8 + beq t0, t1, 8f + la t1, bad9 + beq t0, t1, 9f + la t1, bare_s_1 + beq t0, t1, 5f + la t1, bare_s_2 + beq t0, t1, 7f + la t1, bare_s_3 + beq t0, t1, 7f + j fail +2: +6: +7: + addi t0, t0, 8 + csrw mepc, t0 + mret + +5: + li t1, MSTATUS_TVM + csrs mstatus, t1 + j 2b + +8: + li t1, MSTATUS_TSR + csrs mstatus, t1 + j 2b + +9: + j 2b + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64mi/ld-misaligned.S b/tb/qumcu/isa/rv64mi/ld-misaligned.S new file mode 100644 index 0000000..fb210ad --- /dev/null +++ b/tb/qumcu/isa/rv64mi/ld-misaligned.S @@ -0,0 +1,45 @@ +# See LICENSE for license details. + +#***************************************************************************** +# lw-unaligned.S +#----------------------------------------------------------------------------- +# +# Test that misaligned loads work or raise the correct exception +# This test assumes the target is little-endian +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64M +RVTEST_CODE_BEGIN + + TEST_LD_OP( 2, ld, 0x0807060504030201, 0, tdat ); + TEST_LD_OP( 3, ld, 0x0908070605040302, 1, tdat ); + TEST_LD_OP( 4, ld, 0x0a09080706050403, 2, tdat ); + TEST_LD_OP( 5, ld, 0x0b0a090807060504, 3, tdat ); + TEST_LD_OP( 6, ld, 0x0c0b0a0908070605, 4, tdat ); + TEST_LD_OP( 7, ld, 0x0d0c0b0a09080706, 5, tdat ); + TEST_LD_OP( 8, ld, 0x0e0d0c0b0a090807, 6, tdat ); + TEST_LD_OP( 9, ld, 0x0f0e0d0c0b0a0908, 7, tdat ); + +2: + TEST_PASSFAIL + + .align 2 + .global mtvec_handler +mtvec_handler: + MISALIGNED_LOAD_HANDLER + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +tdat: + .byte 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08 + .byte 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10 + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64mi/lh-misaligned.S b/tb/qumcu/isa/rv64mi/lh-misaligned.S new file mode 100644 index 0000000..c21551d --- /dev/null +++ b/tb/qumcu/isa/rv64mi/lh-misaligned.S @@ -0,0 +1,38 @@ +# See LICENSE for license details. + +#***************************************************************************** +# lh-unaligned.S +#----------------------------------------------------------------------------- +# +# Test that misaligned loads work or raise the correct exception +# This test assumes the target is little-endian +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64M +RVTEST_CODE_BEGIN + + TEST_LD_OP( 2, lh, 0x0201, 0, tdat ); + TEST_LD_OP( 3, lh, 0x0302, 1, tdat ); + +2: + TEST_PASSFAIL + + .align 2 + .global mtvec_handler +mtvec_handler: + MISALIGNED_LOAD_HANDLER + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +tdat: + .byte 0x01, 0x02, 0x03, 0x04 + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64mi/lw-misaligned.S b/tb/qumcu/isa/rv64mi/lw-misaligned.S new file mode 100644 index 0000000..3029085 --- /dev/null +++ b/tb/qumcu/isa/rv64mi/lw-misaligned.S @@ -0,0 +1,40 @@ +# See LICENSE for license details. + +#***************************************************************************** +# lw-unaligned.S +#----------------------------------------------------------------------------- +# +# Test that misaligned loads work or raise the correct exception +# This test assumes the target is little-endian +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64M +RVTEST_CODE_BEGIN + + TEST_LD_OP( 2, lw, 0x04030201, 0, tdat ); + TEST_LD_OP( 3, lw, 0x05040302, 1, tdat ); + TEST_LD_OP( 4, lw, 0x06050403, 2, tdat ); + TEST_LD_OP( 5, lw, 0x07060504, 3, tdat ); + +2: + TEST_PASSFAIL + + .align 2 + .global mtvec_handler +mtvec_handler: + MISALIGNED_LOAD_HANDLER + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +tdat: + .byte 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08 + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64mi/ma_addr.S b/tb/qumcu/isa/rv64mi/ma_addr.S new file mode 100644 index 0000000..8579c01 --- /dev/null +++ b/tb/qumcu/isa/rv64mi/ma_addr.S @@ -0,0 +1,133 @@ +# See LICENSE for license details. + +#***************************************************************************** +# ma_addr.S +#----------------------------------------------------------------------------- +# +# Test misaligned ld/st trap. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64M +RVTEST_CODE_BEGIN + + .align 2 + .option norvc + + la s0, data + + # indicate it's a load test + li s1, CAUSE_MISALIGNED_LOAD + li s2, CAUSE_LOAD_ACCESS + +#define SEXT(x, n) ((-((x) >> ((n)-1)) << (n)) | ((x) & ((1 << (n))-1))) + +/* Check that a misaligned load either writes the correct value, or + takes an exception and performs no writeback. */ +#define MISALIGNED_LOAD_TEST(testnum, insn, base, offset, res) \ + li TESTNUM, testnum; \ + la t2, 1f; \ + addi t1, base, offset; \ + insn t1, offset(base); \ + li t2, res; \ + bne t1, t2, fail; \ +1: + + MISALIGNED_LOAD_TEST(2, lh, s0, 1, SEXT(0xbbcc, 16)) + MISALIGNED_LOAD_TEST(3, lhu, s0, 1, 0xbbcc) + MISALIGNED_LOAD_TEST(4, lw, s0, 1, SEXT(0x99aabbcc, 32)) + MISALIGNED_LOAD_TEST(5, lw, s0, 2, SEXT(0x8899aabb, 32)) + MISALIGNED_LOAD_TEST(6, lw, s0, 3, SEXT(0x778899aa, 32)) + +#if __riscv_xlen == 64 + MISALIGNED_LOAD_TEST(7, lwu, s0, 1, 0x99aabbcc) + MISALIGNED_LOAD_TEST(8, lwu, s0, 2, 0x8899aabb) + MISALIGNED_LOAD_TEST(9, lwu, s0, 3, 0x778899aa) + + MISALIGNED_LOAD_TEST(10, ld, s0, 1, 0x5566778899aabbcc) + MISALIGNED_LOAD_TEST(11, ld, s0, 2, 0x445566778899aabb) + MISALIGNED_LOAD_TEST(12, ld, s0, 3, 0x33445566778899aa) + MISALIGNED_LOAD_TEST(13, ld, s0, 4, 0x2233445566778899) + MISALIGNED_LOAD_TEST(14, ld, s0, 5, 0x1122334455667788) + MISALIGNED_LOAD_TEST(15, ld, s0, 6, 0xee11223344556677) + MISALIGNED_LOAD_TEST(16, ld, s0, 7, 0xffee112233445566) +#endif + + # indicate it's a store test + li s1, CAUSE_MISALIGNED_STORE + li s2, CAUSE_STORE_ACCESS + +/* Check that a misaligned store has some effect and takes no exception, + or takes no effect and generates an exception. This is not very + thorough. */ +#define MISALIGNED_STORE_TEST(testnum, insn, base, offset, size) \ + li TESTNUM, testnum; \ + la t2, 1f; \ + addi t1, base, offset; \ + insn x0, offset(base); \ + lb t1, (offset - 1)(base); \ + beqz t1, fail; \ + lb t1, (offset + size)(base); \ + beqz t1, fail; \ + lb t1, (offset + 0)(base); \ + bnez t1, fail; \ + lb t1, (offset + size - 1)(base); \ + bnez t1, fail; \ +1: + + MISALIGNED_STORE_TEST(22, sh, s0, 1, 2) + MISALIGNED_STORE_TEST(23, sw, s0, 5, 4) + MISALIGNED_STORE_TEST(24, sw, s0, 10, 4) + MISALIGNED_STORE_TEST(25, sw, s0, 15, 4) + +#if __riscv_xlen == 64 + MISALIGNED_STORE_TEST(26, sd, s0, 25, 8) + MISALIGNED_STORE_TEST(27, sd, s0, 34, 8) + MISALIGNED_STORE_TEST(28, sd, s0, 43, 8) + MISALIGNED_STORE_TEST(29, sd, s0, 52, 8) + MISALIGNED_STORE_TEST(30, sd, s0, 61, 8) + MISALIGNED_STORE_TEST(31, sd, s0, 70, 8) + MISALIGNED_STORE_TEST(32, sd, s0, 79, 8) +#endif + + TEST_PASSFAIL + + .align 3 + .global mtvec_handler +mtvec_handler: + csrr t0, mcause + beq t0, s1, 1f + beq t0, s2, 1f + j fail +1: + + csrr t0, mbadaddr + beqz t0, 1f + bne t0, t1, fail + + lb t0, (t0) + beqz t0, fail +1: + + csrw mepc, t2 + mret + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + +data: + .align 3 +.word 0xaabbccdd +.word 0x66778899 +.word 0x22334455 +.word 0xeeffee11 +.fill 0xff, 1, 80 + + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64mi/ma_fetch.S b/tb/qumcu/isa/rv64mi/ma_fetch.S new file mode 100644 index 0000000..cfcb90c --- /dev/null +++ b/tb/qumcu/isa/rv64mi/ma_fetch.S @@ -0,0 +1,8 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64S +#define RVTEST_RV64S RVTEST_RV64M +#define __MACHINE_MODE + +#include "../rv64si/ma_fetch.S" diff --git a/tb/qumcu/isa/rv64mi/mcsr.S b/tb/qumcu/isa/rv64mi/mcsr.S new file mode 100644 index 0000000..03cf29a --- /dev/null +++ b/tb/qumcu/isa/rv64mi/mcsr.S @@ -0,0 +1,45 @@ +# See LICENSE for license details. + +#***************************************************************************** +# mcsr.S +#----------------------------------------------------------------------------- +# +# Test various M-mode CSRs. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64M +RVTEST_CODE_BEGIN + + # Check that mcpuid reports the correct XLEN +#if __riscv_xlen == 64 + TEST_CASE(2, a0, 0x2, csrr a0, misa; srl a0, a0, 62) +#else + TEST_CASE(2, a0, 0x1, csrr a0, misa; srl a0, a0, 30) +#endif + + # Check that mhartid reports 0 + TEST_CASE(3, a0, 0x0, csrr a0, mhartid) + + # Check that reading the following CSRs doesn't cause an exception + csrr a0, mimpid + csrr a0, marchid + csrr a0, mvendorid + + # Check that writing the following CSRs doesn't cause an exception + li t0, 0 + csrs mtvec, t0 + csrs mepc, t0 + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64mi/sbreak.S b/tb/qumcu/isa/rv64mi/sbreak.S new file mode 100644 index 0000000..f36a9f8 --- /dev/null +++ b/tb/qumcu/isa/rv64mi/sbreak.S @@ -0,0 +1,8 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64S +#define RVTEST_RV64S RVTEST_RV64M +#define __MACHINE_MODE + +#include "../rv64si/sbreak.S" diff --git a/tb/qumcu/isa/rv64mi/scall.S b/tb/qumcu/isa/rv64mi/scall.S new file mode 100644 index 0000000..22e9eb5 --- /dev/null +++ b/tb/qumcu/isa/rv64mi/scall.S @@ -0,0 +1,8 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64S +#define RVTEST_RV64S RVTEST_RV64M +#define __MACHINE_MODE + +#include "../rv64si/scall.S" diff --git a/tb/qumcu/isa/rv64mi/sd-misaligned.S b/tb/qumcu/isa/rv64mi/sd-misaligned.S new file mode 100644 index 0000000..5f5a0b3 --- /dev/null +++ b/tb/qumcu/isa/rv64mi/sd-misaligned.S @@ -0,0 +1,44 @@ +# See LICENSE for license details. + +#***************************************************************************** +# sd-unaligned.S +#----------------------------------------------------------------------------- +# +# Test that misaligned stores work or raise the correct exception +# This test assumes the target is little-endian +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64M +RVTEST_CODE_BEGIN + + TEST_ST_OP( 2, ld, sd, 0x0102030405060708, 0, tdat ); + TEST_ST_OP( 3, ld, sd, 0x090a0b0c0d0e0f10, 1, tdat ); + TEST_ST_OP( 4, ld, sd, 0x1112131415161718, 2, tdat ); + TEST_ST_OP( 5, ld, sd, 0x191a1b1c1d1e1f20, 3, tdat ); + TEST_ST_OP( 6, ld, sd, 0x2122232425262728, 4, tdat ); + TEST_ST_OP( 7, ld, sd, 0x292a2b2c2d2e2f30, 5, tdat ); + TEST_ST_OP( 8, ld, sd, 0x3132333435363738, 6, tdat ); + TEST_ST_OP( 9, ld, sd, 0x393a3b3c3d3e3f40, 7, tdat ); + +2: + TEST_PASSFAIL + + .align 2 + .global mtvec_handler +mtvec_handler: + MISALIGNED_STORE_HANDLER + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +tdat: + .zero 16 + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64mi/sh-misaligned.S b/tb/qumcu/isa/rv64mi/sh-misaligned.S new file mode 100644 index 0000000..668c918 --- /dev/null +++ b/tb/qumcu/isa/rv64mi/sh-misaligned.S @@ -0,0 +1,38 @@ +# See LICENSE for license details. + +#***************************************************************************** +# sh-unaligned.S +#----------------------------------------------------------------------------- +# +# Test that misaligned stores work or raise the correct exception +# This test assumes the target is little-endian +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64M +RVTEST_CODE_BEGIN + + TEST_ST_OP( 2, lh, sh, 0x1234, 0, tdat ); + TEST_ST_OP( 3, lh, sh, 0x5678, 1, tdat ); + +2: + TEST_PASSFAIL + + .align 2 + .global mtvec_handler +mtvec_handler: + MISALIGNED_STORE_HANDLER + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +tdat: + .zero 4 + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64mi/sw-misaligned.S b/tb/qumcu/isa/rv64mi/sw-misaligned.S new file mode 100644 index 0000000..8da698b --- /dev/null +++ b/tb/qumcu/isa/rv64mi/sw-misaligned.S @@ -0,0 +1,40 @@ +# See LICENSE for license details. + +#***************************************************************************** +# sw-unaligned.S +#----------------------------------------------------------------------------- +# +# Test that misaligned stores work or raise the correct exception +# This test assumes the target is little-endian +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64M +RVTEST_CODE_BEGIN + + TEST_ST_OP( 2, lw, sw, 0x12345678, 0, tdat ); + TEST_ST_OP( 3, lw, sw, 0xffffffff9abcdef0, 1, tdat ); + TEST_ST_OP( 4, lw, sw, 0xffffffffdeadbeef, 2, tdat ); + TEST_ST_OP( 5, lw, sw, 0xfffffffffeed0011, 3, tdat ); + +2: + TEST_PASSFAIL + + .align 2 + .global mtvec_handler +mtvec_handler: + MISALIGNED_STORE_HANDLER + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +tdat: + .zero 8 + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64mi/zicntr.S b/tb/qumcu/isa/rv64mi/zicntr.S new file mode 100644 index 0000000..0153b61 --- /dev/null +++ b/tb/qumcu/isa/rv64mi/zicntr.S @@ -0,0 +1,51 @@ +# See LICENSE for license details. + +#***************************************************************************** +# zicntr.S +#----------------------------------------------------------------------------- +# +# Test if Zicntr is implemented correctly +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64M +RVTEST_CODE_BEGIN + + # Make sure reading the cycle counter in four ways doesn't trap. + TEST_CASE( 2, x0, 0, csrrc x0, cycle, x0); + TEST_CASE( 3, x0, 0, csrrs x0, cycle, x0); + TEST_CASE( 4, x0, 0, csrrci x0, cycle, 0); + TEST_CASE( 5, x0, 0, csrrsi x0, cycle, 0); + TEST_CASE( 6, x0, 0, csrrc x0, instret, x0); + TEST_CASE( 7, x0, 0, csrrs x0, instret, x0); + TEST_CASE( 8, x0, 0, csrrci x0, instret, 0); + TEST_CASE( 9, x0, 0, csrrsi x0, instret, 0); +#if __riscv_xlen == 32 + TEST_CASE(12, x0, 0, csrrc x0, cycleh, x0); + TEST_CASE(13, x0, 0, csrrs x0, cycleh, x0); + TEST_CASE(14, x0, 0, csrrci x0, cycleh, 0); + TEST_CASE(15, x0, 0, csrrsi x0, cycleh, 0); + TEST_CASE(16, x0, 0, csrrc x0, instreth, x0); + TEST_CASE(17, x0, 0, csrrs x0, instreth, x0); + TEST_CASE(18, x0, 0, csrrci x0, instreth, 0); + TEST_CASE(19, x0, 0, csrrsi x0, instreth, 0); +#endif + +2: + TEST_PASSFAIL + + .align 2 + .global mtvec_handler +mtvec_handler: + j fail + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64mzicbo/Makefrag b/tb/qumcu/isa/rv64mzicbo/Makefrag new file mode 100644 index 0000000..a002cc9 --- /dev/null +++ b/tb/qumcu/isa/rv64mzicbo/Makefrag @@ -0,0 +1,8 @@ +#======================================================================= +# Makefrag for rv64mzicbo tests +#----------------------------------------------------------------------- + +rv64mzicbo_sc_tests = \ + zero \ + +rv64mzicbo_p_tests = $(addprefix rv64mzicbo-p-, $(rv64mzicbo_sc_tests)) diff --git a/tb/qumcu/isa/rv64mzicbo/zero.S b/tb/qumcu/isa/rv64mzicbo/zero.S new file mode 100644 index 0000000..bccefc2 --- /dev/null +++ b/tb/qumcu/isa/rv64mzicbo/zero.S @@ -0,0 +1,37 @@ +#***************************************************************************** +#----------------------------------------------------------------------------- +# +# Test CBO.ZERO instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64M +RVTEST_CODE_BEGIN + + la x1, tdat + .word 0x0040A00F # cbo.zero(x1) + TEST_LD_OP( 1, ld, 0, 0, tdat ) + TEST_LD_OP( 2, ld, 0, 8, tdat ) + TEST_LD_OP( 3, ld, 0, 16, tdat ) + TEST_LD_OP( 4, ld, 0, 24, tdat ) + TEST_LD_OP( 5, ld, 0, 32, tdat ) + TEST_LD_OP( 6, ld, 0, 40, tdat ) + TEST_LD_OP( 7, ld, 0, 48, tdat ) + TEST_LD_OP( 8, ld, 0, 56, tdat ) + + j pass + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +tdat: .dword 0xdeadbeefdeadbeef + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64si/Makefrag b/tb/qumcu/isa/rv64si/Makefrag new file mode 100644 index 0000000..604005c --- /dev/null +++ b/tb/qumcu/isa/rv64si/Makefrag @@ -0,0 +1,14 @@ +#======================================================================= +# Makefrag for rv64si tests +#----------------------------------------------------------------------- + +rv64si_sc_tests = \ + csr \ + dirty \ + icache-alias \ + ma_fetch \ + scall \ + wfi \ + sbreak \ + +rv64si_p_tests = $(addprefix rv64si-p-, $(rv64si_sc_tests)) diff --git a/tb/qumcu/isa/rv64si/csr.S b/tb/qumcu/isa/rv64si/csr.S new file mode 100644 index 0000000..b37795e --- /dev/null +++ b/tb/qumcu/isa/rv64si/csr.S @@ -0,0 +1,167 @@ +# See LICENSE for license details. + +#***************************************************************************** +# csr.S +#----------------------------------------------------------------------------- +# +# Test CSRRx and CSRRxI instructions. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64S +RVTEST_CODE_BEGIN + +#ifdef __MACHINE_MODE + #define sscratch mscratch + #define sstatus mstatus + #define scause mcause + #define sepc mepc + #define sret mret + #define stvec_handler mtvec_handler + #undef SSTATUS_SPP + #define SSTATUS_SPP MSTATUS_MPP +#endif + + # For RV64, make sure UXL encodes RV64. (UXL does not exist for RV32.) +#if __riscv_xlen == 64 + # If running in M mode, use mstatus.MPP to check existence of U mode. + # Otherwise, if in S mode, then U mode must exist and we don't need to check. +#ifdef __MACHINE_MODE + li t0, MSTATUS_MPP + csrc mstatus, t0 + csrr t1, mstatus + and t0, t0, t1 + bnez t0, 1f +#endif + # If U mode is present, UXL should be 2 (XLEN = 64-bit) + TEST_CASE(18, a0, SSTATUS_UXL & (SSTATUS_UXL << 1), csrr a0, sstatus; li a1, SSTATUS_UXL; and a0, a0, a1) +#ifdef __MACHINE_MODE + j 2f +1: + # If U mode is not present, UXL should be 0 + TEST_CASE(19, a0, 0, csrr a0, sstatus; li a1, SSTATUS_UXL; and a0, a0, a1) +2: +#endif +#endif + + TEST_CASE(20, a0, 0, csrw sscratch, zero; csrr a0, sscratch); + TEST_CASE(21, a0, 0, csrrwi a0, sscratch, 0; csrrwi a0, sscratch, 0xF); + TEST_CASE(22, a0, 0x1f, csrrsi x0, sscratch, 0x10; csrr a0, sscratch); + + csrwi sscratch, 3 + TEST_CASE( 2, a0, 3, csrr a0, sscratch); + TEST_CASE( 3, a1, 3, csrrci a1, sscratch, 1); + TEST_CASE( 4, a2, 2, csrrsi a2, sscratch, 4); + TEST_CASE( 5, a3, 6, csrrwi a3, sscratch, 2); + TEST_CASE( 6, a1, 2, li a0, 0xbad1dea; csrrw a1, sscratch, a0); + TEST_CASE( 7, a1, 0xbad1dea, li a0, 0x0001dea; csrrc a1, sscratch, a0); + TEST_CASE( 8, a1, 0xbad0000, li a0, 0x000beef; csrrs a1, sscratch, a0); + TEST_CASE( 9, a0, 0xbadbeef, li a0, 0xbad1dea; csrrw a0, sscratch, a0); + TEST_CASE(10, a0, 0xbad1dea, li a0, 0x0001dea; csrrc a0, sscratch, a0); + TEST_CASE(11, a0, 0xbad0000, li a0, 0x000beef; csrrs a0, sscratch, a0); + TEST_CASE(12, a0, 0xbadbeef, csrr a0, sscratch); + +#ifdef __MACHINE_MODE + # Is F extension present? + csrr a0, misa + andi a0, a0, (1 << ('F' - 'A')) + beqz a0, 1f + # If so, make sure FP stores have no effect when mstatus.FS is off. + li a1, MSTATUS_FS + csrs mstatus, a1 +#ifdef __riscv_flen + fmv.s.x f0, x0 + csrc mstatus, a1 + la a1, fsw_data + TEST_CASE(13, a0, 1, fsw f0, (a1); lw a0, (a1)); +#else + # Fail if this test is compiled without F but executed on a core with F. + TEST_CASE(13, zero, 1) +#endif +1: + + # Figure out if 'U' is set in misa + csrr a0, misa # a0 = csr(misa) + srli a0, a0, 20 # a0 = a0 >> 20 + andi a0, a0, 1 # a0 = a0 & 1 + beqz a0, finish # if no user mode, skip the rest of these checks + + # Enable access to the cycle counter + csrwi mcounteren, 1 + + # Figure out if 'S' is set in misa + csrr a0, misa # a0 = csr(misa) + srli a0, a0, 18 # a0 = a0 >> 20 + andi a0, a0, 1 # a0 = a0 & 1 + beqz a0, 1f + + # Enable access to the cycle counter + csrwi scounteren, 1 +1: +#endif /* __MACHINE_MODE */ + + # jump to user land + li t0, SSTATUS_SPP + csrc sstatus, t0 + la t0, 1f + csrw sepc, t0 + sret + 1: + + # Make sure writing the cycle counter causes an exception. + # Don't run in supervisor, as we don't delegate illegal instruction traps. +#ifdef __MACHINE_MODE + TEST_CASE(14, a0, 255, li a0, 255; csrrw a0, cycle, x0); +#endif + + # Make sure reading status in user mode causes an exception. + # Don't run in supervisor, as we don't delegate illegal instruction traps. +#ifdef __MACHINE_MODE + TEST_CASE(15, a0, 255, li a0, 255; csrr a0, sstatus) +#else + TEST_CASE(15, x0, 0, nop) +#endif + +finish: + RVTEST_PASS + + # We should only fall through to this if scall failed. + TEST_PASSFAIL + + .align 2 + .global stvec_handler +stvec_handler: + # Trapping on tests 13-15 is good news. + li t0, 13 + bltu TESTNUM, t0, 1f + li t0, 15 + bleu TESTNUM, t0, privileged +1: + + # catch RVTEST_PASS and kick it up to M-mode + csrr t0, scause + li t1, CAUSE_USER_ECALL + bne t0, t1, fail + RVTEST_PASS + +privileged: + # Make sure scause indicates a lack of privilege. + csrr t0, scause + li t1, CAUSE_ILLEGAL_INSTRUCTION + bne t0, t1, fail + # Return to user mode, but skip the trapping instruction. + csrr t0, sepc + addi t0, t0, 4 + csrw sepc, t0 + sret + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + +fsw_data: .word 1 + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64si/dirty.S b/tb/qumcu/isa/rv64si/dirty.S new file mode 100644 index 0000000..15f3163 --- /dev/null +++ b/tb/qumcu/isa/rv64si/dirty.S @@ -0,0 +1,133 @@ +# See LICENSE for license details. + +#***************************************************************************** +# dirty.S +#----------------------------------------------------------------------------- +# +# Test VM referenced and dirty bits. +# + +#include "riscv_test.h" +#include "test_macros.h" + +#if (DRAM_BASE >> 30 << 30) != DRAM_BASE +# error This test requires DRAM_BASE be SV39 superpage-aligned +#endif + +RVTEST_RV64M +RVTEST_CODE_BEGIN + + # Turn on VM + li a0, (SATP_MODE & ~(SATP_MODE<<1)) * SATP_MODE_SV39 + la a1, page_table_1 + srl a1, a1, RISCV_PGSHIFT + or a1, a1, a0 + csrw sptbr, a1 + sfence.vma + + # Set up MPRV with MPP=S, so loads and stores use S-mode + li a1, ((MSTATUS_MPP & ~(MSTATUS_MPP<<1)) * PRV_S) | MSTATUS_MPRV + csrs mstatus, a1 + + # Try a faulting store to make sure dirty bit is not set + li TESTNUM, 2 + li t2, 1 + sw t2, dummy - DRAM_BASE, a0 + + # Set SUM=1 so user memory access is permitted + li TESTNUM, 3 + li a1, ((MSTATUS_MPP & ~(MSTATUS_MPP<<1)) * PRV_S) | MSTATUS_SUM + csrs mstatus, a1 + + # Make sure SUM=1 works + lw t0, dummy - DRAM_BASE + bnez t0, die + + # Try a non-faulting store to make sure dirty bit is set + sw t2, dummy - DRAM_BASE, a0 + + # Make sure it succeeded + lw t0, dummy - DRAM_BASE + bne t0, t2, die + + # Leave MPRV + li t0, MSTATUS_MPRV + csrc mstatus, t0 + + # Make sure D bit is set + lw t0, page_table_1 + li a0, PTE_A | PTE_D + and t0, t0, a0 + bne t0, a0, die + + # Enter MPRV again + li t0, MSTATUS_MPRV + csrs mstatus, t0 + + # Make sure that superpage entries trap when PPN LSBs are set. + li TESTNUM, 4 + lw a0, page_table_1 - DRAM_BASE + or a0, a0, 1 << PTE_PPN_SHIFT + sw a0, page_table_1 - DRAM_BASE, t0 + sfence.vma + sw a0, page_table_1 - DRAM_BASE, t0 + j die + + RVTEST_PASS + + TEST_PASSFAIL + + .align 2 + .global mtvec_handler +mtvec_handler: + csrr t0, mcause + add t0, t0, -CAUSE_STORE_PAGE_FAULT + bnez t0, die + + li t1, 2 + bne TESTNUM, t1, 1f + # Make sure D bit is clear + lw t0, page_table_1 + and t1, t0, PTE_D + bnez t1, die +skip: + csrr t0, mepc + add t0, t0, 4 + csrw mepc, t0 + mret + +1: + li t1, 3 + bne TESTNUM, t1, 1f + # The implementation doesn't appear to set D bits in HW. + # Make sure the D bit really is clear. + lw t0, page_table_1 + and t1, t0, PTE_D + bnez t1, die + # Set the D bit. + or t0, t0, PTE_D + sw t0, page_table_1, t1 + sfence.vma + mret + +1: + li t1, 4 + bne TESTNUM, t1, 1f + j pass + +1: +die: + RVTEST_FAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +.align 12 +page_table_1: .dword (DRAM_BASE/RISCV_PGSIZE << PTE_PPN_SHIFT) | PTE_V | PTE_U | PTE_R | PTE_W | PTE_X | PTE_A +dummy: .dword 0 + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64si/icache-alias.S b/tb/qumcu/isa/rv64si/icache-alias.S new file mode 100644 index 0000000..dbc934e --- /dev/null +++ b/tb/qumcu/isa/rv64si/icache-alias.S @@ -0,0 +1,141 @@ +# See LICENSE for license details. + +#***************************************************************************** +# icache-alias.S +#----------------------------------------------------------------------------- +# +# Test that instruction memory appears to be physically addressed, i.e., +# that disagreements in the low-order VPN and PPN bits don't cause the +# wrong instruction to be fetched. It also tests that changing a page +# mapping takes effect without executing FENCE.I. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64M +RVTEST_CODE_BEGIN + + li TESTNUM, 2 + + # Set up intermediate page tables + + la t0, page_table_3 + srl t0, t0, RISCV_PGSHIFT - PTE_PPN_SHIFT + ori t0, t0, PTE_V + sd t0, page_table_2, t1 + + la t0, page_table_2 + srl t0, t0, RISCV_PGSHIFT - PTE_PPN_SHIFT + ori t0, t0, PTE_V + sd t0, page_table_1, t1 + + # Set up leaf mappings where va[12] != pa[12] + + la t0, code_page_1 + srl t0, t0, RISCV_PGSHIFT - PTE_PPN_SHIFT + ori t0, t0, PTE_V | PTE_X | PTE_A + sd t0, page_table_3 + 8, t1 + + la t0, code_page_2 + srl t0, t0, RISCV_PGSHIFT - PTE_PPN_SHIFT + ori t0, t0, PTE_V | PTE_X | PTE_A + sd t0, page_table_3 + 0, t1 + + # Turn on VM + + li a0, (SATP_MODE & ~(SATP_MODE<<1)) * SATP_MODE_SV39 + la a1, page_table_1 + srl a1, a1, RISCV_PGSHIFT + or a1, a1, a0 + csrw sptbr, a1 + sfence.vma + + # Enter supervisor mode and make sure correct page is accessed + + la a2, 1f + csrwi mepc, 0 + li a1, ((MSTATUS_MPP & ~(MSTATUS_MPP<<1)) * PRV_S) + csrs mstatus, a1 + mret + +1: + li TESTNUM, 2 + addi a0, a0, -321 + bnez a0, fail + + li TESTNUM, 3 + la a2, 1f + li t0, RISCV_PGSIZE + csrw mepc, t0 + mret + +1: + addi a0, a0, -123 + bnez a0, fail + + li TESTNUM, 4 + la a2, 1f + csrwi mepc, 0 + mret + + .align 2 +1: + addi a0, a0, -321 + bnez a0, fail + + li TESTNUM, 5 + + # Change mapping and try again + + la t0, code_page_1 + srl t0, t0, RISCV_PGSHIFT - PTE_PPN_SHIFT + ori t0, t0, PTE_V | PTE_X | PTE_A + sd t0, page_table_3 + 0, t1 + sfence.vma + + la a2, 1f + csrwi mepc, 0 + mret + + .align 2 +1: + addi a0, a0, -123 + bnez a0, fail + + RVTEST_PASS + + TEST_PASSFAIL + + .align 2 + .global mtvec_handler +mtvec_handler: + csrr t0, mcause + add t0, t0, -CAUSE_STORE_PAGE_FAULT + bnez t0, fail + + jr a2 + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +.align 12 +page_table_1: .dword 0 +.align 12 +page_table_2: .dword 0 +.align 12 +page_table_3: .dword 0 +.align 13 +code_page_1: + li a0, 123 + sw x0, (x0) +.align 12 +code_page_2: + li a0, 321 + sw x0, (x0) + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64si/ma_fetch.S b/tb/qumcu/isa/rv64si/ma_fetch.S new file mode 100644 index 0000000..b683b6f --- /dev/null +++ b/tb/qumcu/isa/rv64si/ma_fetch.S @@ -0,0 +1,226 @@ +# See LICENSE for license details. + +#***************************************************************************** +# ma_fetch.S +#----------------------------------------------------------------------------- +# +# Test misaligned fetch trap. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64S +RVTEST_CODE_BEGIN + +#ifdef __MACHINE_MODE + #define sscratch mscratch + #define sstatus mstatus + #define scause mcause + #define sbadaddr mbadaddr + #define sepc mepc + #define sret mret + #define stvec_handler mtvec_handler +#endif + + .align 2 + .option norvc + + # Without RVC, the jalr should trap, and the handler will skip ahead. + # With RVC, the jalr should not trap, and "j fail" should get skipped. + li TESTNUM, 2 + li t1, 0 + la t0, 1f + jalr t1, t0, 2 +1: + .option rvc + c.j 1f + c.j 2f + .option norvc +1: + j fail +2: + + // This test should pass, since JALR ignores the target LSB + li TESTNUM, 3 + la t0, 1f + jalr t1, t0, 1 +1: + j 1f + j fail +1: + + li TESTNUM, 4 + li t1, 0 + la t0, 1f + jalr t1, t0, 3 +1: + .option rvc + c.j 1f + c.j 2f + .option norvc +1: + j fail +2: + + # Like test 2, but with jal instead of jalr. + li TESTNUM, 5 + li t1, 0 + la t0, 1f + jal t1, 2f +1: + .option rvc + c.j 1f +2: + c.j 2f + .option norvc +1: + j fail +2: + + # Like test 2, but with a taken branch instead of jalr. + li TESTNUM, 6 + li t1, 0 + la t0, 1f + beqz x0, 2f +1: + .option rvc + c.j 1f +2: + c.j 2f + .option norvc +1: + j fail +2: + + # Not-taken branches should not trap, even without RVC. + li TESTNUM, 7 + bnez x0, 1f + j 2f + .option rvc + c.j 1f +1: + c.j 1f + .option norvc +1: + j fail +2: + +#ifdef __MACHINE_MODE + # Skip if C cannot be enabled + csrsi misa, 1 << ('c' - 'a') + csrr t2, misa + andi t2, t2, 1 << ('c' - 'a') + beqz t2, pass + + # Skip if C cannot be disabled + csrci misa, 1 << ('c' - 'a') + csrr t2, misa + andi t2, t2, 1 << ('c' - 'a') + bnez t2, pass + + # Skip if clearing misa.C does not set IALIGN=32 + csrr t0, mtvec + la t1, 1f + addi t1, t1, 2 + csrw mtvec, t1 + j 1f + + .option rvc + c.nop +1: + j pass + .option norvc +2: + csrw mtvec, t0 + csrsi misa, 1 << ('c' - 'a') + + # IALIGN=32 cannot be set if doing so would cause a misaligned instruction + # exception on the next instruction fetch. (This test assumes no other + # extensions that support misalignment are present.) + li TESTNUM, 8 + csrr t2, misa + andi t2, t2, 1 << ('c' - 'a') + beqz t2, pass + + .option rvc + c.nop + csrci misa, 1 << ('c' - 'a') +1: + c.nop + .option norvc + + csrr t2, misa + andi t2, t2, 1 << ('c' - 'a') + beqz t2, fail + + # IALIGN=32, mret to a misaligned mepc should succeed, + # masking off mepc[1]. + la t0, 1f + addi t0, t0, -2 + csrw mepc, t0 + + csrci misa, 1 << ('c' - 'a') + li t2, MSTATUS_MPP + csrs mstatus, t2 + mret + + # mret should transfer control to this branch. Otherwise, it will + # transfer control two bytes into the branch, which happens to be the + # illegal instruction c.unimp. + beqz x0, 1f +1: + csrsi misa, 1 << ('c' - 'a') +#endif + + j pass + + TEST_PASSFAIL + + .align 2 + .global stvec_handler +stvec_handler: + # tests 2, 4, 5, 6, and 8 should trap + li a0, 2 + beq TESTNUM, a0, 1f + li a0, 4 + beq TESTNUM, a0, 1f + li a0, 5 + beq TESTNUM, a0, 1f + li a0, 6 + beq TESTNUM, a0, 1f + j fail +1: + + # verify that return address was not written + bnez t1, fail + + # verify trap cause + li a1, CAUSE_MISALIGNED_FETCH + csrr a0, scause + bne a0, a1, fail + + # verify that epc == &jalr (== t0 - 4) + csrr a1, sepc + addi a1, a1, 4 + bne t0, a1, fail + + # verify that badaddr == 0 or badaddr == t0+2. + csrr a0, sbadaddr + beqz a0, 1f + addi a0, a0, -2 + bne a0, t0, fail +1: + + addi a1, a1, 8 + csrw sepc, a1 + sret + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64si/sbreak.S b/tb/qumcu/isa/rv64si/sbreak.S new file mode 100644 index 0000000..475bf65 --- /dev/null +++ b/tb/qumcu/isa/rv64si/sbreak.S @@ -0,0 +1,59 @@ +# See LICENSE for license details. + +#***************************************************************************** +# scall.S +#----------------------------------------------------------------------------- +# +# Test syscall trap. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64S +RVTEST_CODE_BEGIN + +#ifdef __MACHINE_MODE + #define sscratch mscratch + #define sstatus mstatus + #define scause mcause + #define stvec mtvec + #define sepc mepc + #define sret mret + #define stvec_handler mtvec_handler +#endif + + li TESTNUM, 2 + +do_break: + sbreak + j fail + + TEST_PASSFAIL + + .align 2 + .global stvec_handler +stvec_handler: + li t1, CAUSE_BREAKPOINT + csrr t0, scause + # Check if CLIC mode + csrr t2, stvec + andi t2, t2, 2 + # Skip masking if non-CLIC mode + beqz t2, skip_mask + andi t0, t0, 255 +skip_mask: + bne t0, t1, fail + la t1, do_break + csrr t0, sepc + bne t0, t1, fail + j pass + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64si/scall.S b/tb/qumcu/isa/rv64si/scall.S new file mode 100644 index 0000000..eb6f1e6 --- /dev/null +++ b/tb/qumcu/isa/rv64si/scall.S @@ -0,0 +1,91 @@ +# See LICENSE for license details. + +#***************************************************************************** +# scall.S +#----------------------------------------------------------------------------- +# +# Test syscall trap. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64S +RVTEST_CODE_BEGIN + +#ifdef __MACHINE_MODE + #define sscratch mscratch + #define sstatus mstatus + #define scause mcause + #define stvec mtvec + #define sepc mepc + #define sret mret + #define stvec_handler mtvec_handler + #undef SSTATUS_SPP + #define SSTATUS_SPP MSTATUS_MPP +#endif + + li TESTNUM, 2 + + # This is the expected trap code. + li t1, CAUSE_USER_ECALL + +#ifdef __MACHINE_MODE + # If running in M mode, use mstatus.MPP to check existence of U mode. + # Otherwise, if in S mode, then U mode must exist and we don't need to check. + li t0, MSTATUS_MPP + csrc mstatus, t0 + csrr t2, mstatus + and t0, t0, t2 + beqz t0, 1f + + # If U mode doesn't exist, mcause should indicate ECALL from M mode. + li t1, CAUSE_MACHINE_ECALL +#endif + +1: + li t0, SSTATUS_SPP + csrc sstatus, t0 + la t0, 1f + csrw sepc, t0 + sret +1: + + li TESTNUM, 1 +do_scall: + scall + j fail + + TEST_PASSFAIL + +# Depending on the test environment, the M-mode version of this test might +# not actually invoke the following handler. Instead, the usual ECALL +# handler in the test environment might detect the CAUSE_USER_ECALL or +# CAUSE_MACHINE_ECALL exception and mark the test as having passed. +# Either way, we'll get the coverage we desire: such a handler must check +# both mcause and TESTNUM, just like the following handler. + .align 2 + .global stvec_handler +stvec_handler: + csrr t0, scause + # Check if CLIC mode + csrr t2, stvec + andi t2, t2, 2 + # Skip masking if non-CLIC mode + beqz t2, skip_mask + andi t0, t0, 255 +skip_mask: + bne t0, t1, fail + la t2, do_scall + csrr t0, sepc + bne t0, t2, fail + j pass + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64si/wfi.S b/tb/qumcu/isa/rv64si/wfi.S new file mode 100644 index 0000000..0302034 --- /dev/null +++ b/tb/qumcu/isa/rv64si/wfi.S @@ -0,0 +1,33 @@ +# See LICENSE for license details. + +#***************************************************************************** +# wfi.S +#----------------------------------------------------------------------------- +# +# Test wait-for-interrupt instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64S +RVTEST_CODE_BEGIN + + # Make sure wfi doesn't halt the hart, even if interrupts are disabled + csrc sstatus, SSTATUS_SIE + csrs sie, SIP_SSIP + csrs sip, SIP_SSIP + wfi + + RVTEST_PASS + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64ssvnapot/Makefrag b/tb/qumcu/isa/rv64ssvnapot/Makefrag new file mode 100644 index 0000000..79e1f2a --- /dev/null +++ b/tb/qumcu/isa/rv64ssvnapot/Makefrag @@ -0,0 +1,8 @@ +#======================================================================= +# Makefrag for rv64ssvnapot tests +#----------------------------------------------------------------------- + +rv64ssvnapot_sc_tests = \ + napot \ + +rv64ssvnapot_p_tests = $(addprefix rv64ssvnapot-p-, $(rv64ssvnapot_sc_tests)) diff --git a/tb/qumcu/isa/rv64ssvnapot/napot.S b/tb/qumcu/isa/rv64ssvnapot/napot.S new file mode 100644 index 0000000..fbc4014 --- /dev/null +++ b/tb/qumcu/isa/rv64ssvnapot/napot.S @@ -0,0 +1,183 @@ +# See LICENSE for license details. + +#***************************************************************************** +# napot.S +#----------------------------------------------------------------------------- +# +# Test Svnapot +# + +#include "riscv_test.h" +#include "test_macros.h" + +#if (DRAM_BASE >> 30 << 30) != DRAM_BASE +# error This test requires DRAM_BASE be SV39 superpage-aligned +#endif + +#if __riscv_xlen != 64 +# error This test requires RV64 +#endif + +RVTEST_RV64M +RVTEST_CODE_BEGIN + + # Construct the page table + +#define MY_VA 0x40201010 + # VPN 2 == VPN 1 == VPN 0 == 0x1 + # Page offset == 0x10 + + #### + + # Level 0 PTE contents + + # PPN + la a0, my_data + srl a0, a0, 12 + + # adjust the PPN to be in NAPOT form + li a1, ~0xF + and a0, a0, a1 + ori a0, a0, 0x8 + + # attributes + sll a0, a0, PTE_PPN_SHIFT + li a1, PTE_V | PTE_U | PTE_R | PTE_W | PTE_X | PTE_A | PTE_D | PTE_N + or a0, a0, a1 + + # Level 0 PTE address + la a1, page_table + addi a1, a1, ((MY_VA >> 12) & 0x1FF) * 8 + + # Level 0 PTE store + sd a0, (a1) + + #### + + # Level 1 PTE contents + la a0, page_table + srl a0, a0, 12 + sll a0, a0, PTE_PPN_SHIFT + li a1, PTE_V + or a0, a0, a1 + + # Level 1 PTE address + la a1, page_table + addi a1, a1, ((MY_VA >> 21) & 0x1FF) * 8 + li a2, 1 << 12 + add a1, a1, a2 + + # Level 1 PTE store + sd a0, (a1) + + #### + + # Level 2 PTE contents + la a0, page_table + li a1, 1 << 12 + add a0, a0, a1 + srl a0, a0, 12 + sll a0, a0, PTE_PPN_SHIFT + li a1, PTE_V + or a0, a0, a1 + + # Level 2 PTE address + la a1, page_table + addi a1, a1, ((MY_VA >> 30) & 0x1FF) * 8 + li a2, 2 << 12 + add a1, a1, a2 + + # Level 2 PTE store + sd a0, (a1) + + #### + + # Do a load from the PA that would be written if the PTE were misinterpreted as non-NAPOT + la a0, my_data + li a1, ~0xFFFF + and a0, a0, a1 + li a1, 0x8000 | (MY_VA & 0xFFF) + or a3, a0, a1 + li a1, 0 + sw a1, (a3) + + #### + li TESTNUM, 1 + + ## Turn on VM + la a1, page_table + li a2, 2 << 12 + add a1, a1, a2 + srl a1, a1, 12 + li a0, (SATP_MODE & ~(SATP_MODE<<1)) * SATP_MODE_SV39 + or a0, a0, a1 + csrw satp, a0 + sfence.vma + + # Set up MPRV with MPP=S and SUM=1, so loads and stores use S-mode and S can access U pages + li a1, ((MSTATUS_MPP & ~(MSTATUS_MPP<<1)) * PRV_S) | MSTATUS_MPRV | MSTATUS_SUM + csrs mstatus, a1 + + # Do a store to MY_VA + li a0, MY_VA + li a1, 42 +napot_store: + sw a1, (a0) + + # Clear MPRV + li a1, MSTATUS_MPRV + csrc mstatus, a1 + + # Do a load from the PA that would be written if the PTE were misinterpreted as non-NAPOT + lw a1, (a3) + + # Check the result + li a0, 42 + beq a1, a0, die + + # Do a load from the PA for MY_VA + la a0, my_data + li a1, MY_VA & 0xFFFF + add a0, a0, a1 + lw a1, (a0) + li a2, 42 + + # Check the result + bne a1, a2, die + + #### + + RVTEST_PASS + + TEST_PASSFAIL + + .align 2 + .global mtvec_handler +mtvec_handler: + # Skip if Svnapot is not implemented. + csrr t5, mcause + li t6, CAUSE_STORE_PAGE_FAULT + bne t5, t6, die + csrr t5, mepc + la t6, napot_store + bne t5, t6, die + csrr t5, mtval + li t6, MY_VA + beq t5, t6, pass +die: + RVTEST_FAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +.align 20 +page_table: .dword 0 + +.align 20 +my_data: .dword 0 + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64ua/Makefrag b/tb/qumcu/isa/rv64ua/Makefrag new file mode 100644 index 0000000..f0e8ad6 --- /dev/null +++ b/tb/qumcu/isa/rv64ua/Makefrag @@ -0,0 +1,11 @@ +#======================================================================= +# Makefrag for rv64ua tests +#----------------------------------------------------------------------- + +rv64ua_sc_tests = \ + amoadd_d amoand_d amomax_d amomaxu_d amomin_d amominu_d amoor_d amoxor_d amoswap_d \ + amoadd_w amoand_w amomax_w amomaxu_w amomin_w amominu_w amoor_w amoxor_w amoswap_w \ + lrsc \ + +rv64ua_p_tests = $(addprefix rv64ua-p-, $(rv64ua_sc_tests)) +rv64ua_v_tests = $(addprefix rv64ua-v-, $(rv64ua_sc_tests)) diff --git a/tb/qumcu/isa/rv64ua/amoadd_d.S b/tb/qumcu/isa/rv64ua/amoadd_d.S new file mode 100644 index 0000000..05b2f38 --- /dev/null +++ b/tb/qumcu/isa/rv64ua/amoadd_d.S @@ -0,0 +1,47 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amoadd_d.S +#----------------------------------------------------------------------------- +# +# Test amoadd.d instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a4, 0xffffffff80000000, \ + li a0, 0xffffffff80000000; \ + li a1, 0xfffffffffffff800; \ + la a3, amo_operand; \ + sd a0, 0(a3); \ + amoadd.d a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0xffffffff7ffff800, ld a5, 0(a3)) + + # try again after a cache miss + TEST_CASE(4, a4, 0xffffffff7ffff800, \ + amoadd.d a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0xffffffff7ffff000, ld a5, 0(a3)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 diff --git a/tb/qumcu/isa/rv64ua/amoadd_w.S b/tb/qumcu/isa/rv64ua/amoadd_w.S new file mode 100644 index 0000000..d076d45 --- /dev/null +++ b/tb/qumcu/isa/rv64ua/amoadd_w.S @@ -0,0 +1,48 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amoadd_w.S +#----------------------------------------------------------------------------- +# +# Test amoadd.w instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a4, 0xffffffff80000000, \ + li a0, 0xffffffff80000000; \ + li a1, 0xfffffffffffff800; \ + la a3, amo_operand; \ + sw a0, 0(a3); \ + amoadd.w a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0x000000007ffff800, lw a5, 0(a3)) + + # try again after a cache miss + TEST_CASE(4, a4, 0x000000007ffff800, \ + li a1, 0xffffffff80000000; \ + amoadd.w a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0xfffffffffffff800, lw a5, 0(a3)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 diff --git a/tb/qumcu/isa/rv64ua/amoand_d.S b/tb/qumcu/isa/rv64ua/amoand_d.S new file mode 100644 index 0000000..c1148c0 --- /dev/null +++ b/tb/qumcu/isa/rv64ua/amoand_d.S @@ -0,0 +1,48 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amoand_d.S +#----------------------------------------------------------------------------- +# +# Test amoand.d instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a4, 0xffffffff80000000, \ + li a0, 0xffffffff80000000; \ + li a1, 0xfffffffffffff800; \ + la a3, amo_operand; \ + sd a0, 0(a3); \ + amoand.d a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0xffffffff80000000, ld a5, 0(a3)) + + # try again after a cache miss + TEST_CASE(4, a4, 0xffffffff80000000, \ + li a1, 0x0000000080000000; \ + amoand.d a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0x0000000080000000, ld a5, 0(a3)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 diff --git a/tb/qumcu/isa/rv64ua/amoand_w.S b/tb/qumcu/isa/rv64ua/amoand_w.S new file mode 100644 index 0000000..7fe3bd0 --- /dev/null +++ b/tb/qumcu/isa/rv64ua/amoand_w.S @@ -0,0 +1,48 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amoand.w.S +#----------------------------------------------------------------------------- +# +# Test amoand.w instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a4, 0xffffffff80000000, \ + li a0, 0xffffffff80000000; \ + li a1, 0xfffffffffffff800; \ + la a3, amo_operand; \ + sw a0, 0(a3); \ + amoand.w a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0xffffffff80000000, lw a5, 0(a3)) + + # try again after a cache miss + TEST_CASE(4, a4, 0xffffffff80000000, \ + li a1, 0x0000000080000000; \ + amoand.w a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0xffffffff80000000, lw a5, 0(a3)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 diff --git a/tb/qumcu/isa/rv64ua/amomax_d.S b/tb/qumcu/isa/rv64ua/amomax_d.S new file mode 100644 index 0000000..b7f8703 --- /dev/null +++ b/tb/qumcu/isa/rv64ua/amomax_d.S @@ -0,0 +1,48 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amomax_d.S +#----------------------------------------------------------------------------- +# +# Test amomax.d instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a4, 0xffffffff80000000, \ + li a0, 0xffffffff80000000; \ + li a1, 0xfffffffffffff800; \ + la a3, amo_operand; \ + sd a0, 0(a3); \ + amomax.d a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0xfffffffffffff800, ld a5, 0(a3)) + + TEST_CASE(4, a4, 0, \ + li a1, 1; \ + sd x0, 0(a3); \ + amomax.d a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 1, ld a5, 0(a3)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 diff --git a/tb/qumcu/isa/rv64ua/amomax_w.S b/tb/qumcu/isa/rv64ua/amomax_w.S new file mode 100644 index 0000000..2c42982 --- /dev/null +++ b/tb/qumcu/isa/rv64ua/amomax_w.S @@ -0,0 +1,58 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amomax_d.S +#----------------------------------------------------------------------------- +# +# Test amomax.w instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a4, 0xffffffff80000000, \ + li a0, 0xffffffff80000000; \ + li a1, 0xfffffffffffff800; \ + la a3, amo_operand; \ + sw a0, 0(a3); \ + amomax.w a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0xfffffffffffff800, lw a5, 0(a3)) + + TEST_CASE(4, a4, 0, \ + li a1, 1; \ + sw x0, 0(a3); \ + amomax.w a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 1, lw a5, 0(a3)) + + TEST_CASE(6, a4, 1, \ + li a0, 0x0000000000000001; \ + li a1, 0x0000000080000000; \ + la a3, amo_operand; \ + sw a0, 0(a3); \ + amomax.w a4, a1, 0(a3); \ + ) + + TEST_CASE(7, a5, 1, lw a5, 0(a3)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 diff --git a/tb/qumcu/isa/rv64ua/amomaxu_d.S b/tb/qumcu/isa/rv64ua/amomaxu_d.S new file mode 100644 index 0000000..227ac4c --- /dev/null +++ b/tb/qumcu/isa/rv64ua/amomaxu_d.S @@ -0,0 +1,48 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amomaxu_d.S +#----------------------------------------------------------------------------- +# +# Test amomaxu.d instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a4, 0xffffffff80000000, \ + li a0, 0xffffffff80000000; \ + li a1, 0xfffffffffffff800; \ + la a3, amo_operand; \ + sd a0, 0(a3); \ + amomaxu.d a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0xfffffffffffff800, ld a5, 0(a3)) + + TEST_CASE(4, a4, 0, \ + li a1, 0xffffffffffffffff; \ + sd x0, 0(a3); \ + amomaxu.d a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0xffffffffffffffff, ld a5, 0(a3)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 diff --git a/tb/qumcu/isa/rv64ua/amomaxu_w.S b/tb/qumcu/isa/rv64ua/amomaxu_w.S new file mode 100644 index 0000000..6eabcd2 --- /dev/null +++ b/tb/qumcu/isa/rv64ua/amomaxu_w.S @@ -0,0 +1,58 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amomaxu_d.S +#----------------------------------------------------------------------------- +# +# Test amomaxu.w instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a4, 0xffffffff80000000, \ + li a0, 0xffffffff80000000; \ + li a1, 0xfffffffffffff800; \ + la a3, amo_operand; \ + sw a0, 0(a3); \ + amomaxu.w a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0xfffffffffffff800, lw a5, 0(a3)) + + TEST_CASE(4, a4, 0, \ + li a1, 0xffffffffffffffff; \ + sw x0, 0(a3); \ + amomaxu.w a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0xffffffffffffffff, lw a5, 0(a3)) + + TEST_CASE(6, a4, 1, \ + li a0, 0x0000000000000001; \ + li a1, 0x8000000000000000; \ + la a3, amo_operand; \ + sw a0, 0(a3); \ + amomaxu.w a4, a1, 0(a3); \ + ) + + TEST_CASE(7, a5, 1, lw a5, 0(a3)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 diff --git a/tb/qumcu/isa/rv64ua/amomin_d.S b/tb/qumcu/isa/rv64ua/amomin_d.S new file mode 100644 index 0000000..ee6bbf3 --- /dev/null +++ b/tb/qumcu/isa/rv64ua/amomin_d.S @@ -0,0 +1,48 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amomin_d.S +#----------------------------------------------------------------------------- +# +# Test amomin.d instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a4, 0xffffffff80000000, \ + li a0, 0xffffffff80000000; \ + li a1, 0xfffffffffffff800; \ + la a3, amo_operand; \ + sd a0, 0(a3); \ + amomin.d a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0xffffffff80000000, ld a5, 0(a3)) + + TEST_CASE(4, a4, 0, \ + li a1, 0xffffffffffffffff; \ + sd x0, 0(a3); \ + amomin.d a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0xffffffffffffffff, ld a5, 0(a3)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 diff --git a/tb/qumcu/isa/rv64ua/amomin_w.S b/tb/qumcu/isa/rv64ua/amomin_w.S new file mode 100644 index 0000000..754f64d --- /dev/null +++ b/tb/qumcu/isa/rv64ua/amomin_w.S @@ -0,0 +1,58 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amomin_d.S +#----------------------------------------------------------------------------- +# +# Test amomin.w instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a4, 0xffffffff80000000, \ + li a0, 0xffffffff80000000; \ + li a1, 0xfffffffffffff800; \ + la a3, amo_operand; \ + sw a0, 0(a3); \ + amomin.w a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0xffffffff80000000, lw a5, 0(a3)) + + TEST_CASE(4, a4, 0, \ + li a1, 0xffffffffffffffff; \ + sw x0, 0(a3); \ + amomin.w a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0xffffffffffffffff, lw a5, 0(a3)) + + TEST_CASE(6, a4, 1, \ + li a0, 0x0000000000000001; \ + li a1, 0x0000000080000000; \ + la a3, amo_operand; \ + sw a0, 0(a3); \ + amomin.w a4, a1, 0(a3); \ + ) + + TEST_CASE(7, a5, 0xffffffff80000000, lw a5, 0(a3)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 diff --git a/tb/qumcu/isa/rv64ua/amominu_d.S b/tb/qumcu/isa/rv64ua/amominu_d.S new file mode 100644 index 0000000..08bfb5b --- /dev/null +++ b/tb/qumcu/isa/rv64ua/amominu_d.S @@ -0,0 +1,49 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amominu_d.S +#----------------------------------------------------------------------------- +# +# Test amominu.d instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a4, 0xffffffff80000000, \ + li a0, 0xffffffff80000000; \ + li a1, 0xfffffffffffff800; \ + la a3, amo_operand; \ + sd a0, 0(a3); \ + amominu.d a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0xffffffff80000000, ld a5, 0(a3)) + + TEST_CASE(4, a4, 0, \ + li a1, 0xffffffffffffffff; \ + sd x0, 0(a3); \ + amominu.d a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0, ld a5, 0(a3)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 + diff --git a/tb/qumcu/isa/rv64ua/amominu_w.S b/tb/qumcu/isa/rv64ua/amominu_w.S new file mode 100644 index 0000000..d04a650 --- /dev/null +++ b/tb/qumcu/isa/rv64ua/amominu_w.S @@ -0,0 +1,58 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amominu_d.S +#----------------------------------------------------------------------------- +# +# Test amominu.w instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a4, 0xffffffff80000000, \ + li a0, 0xffffffff80000000; \ + li a1, 0xfffffffffffff800; \ + la a3, amo_operand; \ + sw a0, 0(a3); \ + amominu.w a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0xffffffff80000000, lw a5, 0(a3)) + + TEST_CASE(4, a4, 0, \ + li a1, 0xffffffffffffffff; \ + sw x0, 0(a3); \ + amominu.w a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0, lw a5, 0(a3)) + + TEST_CASE(6, a4, 1, \ + li a0, 0x0000000000000001; \ + li a1, 0x8000000000000000; \ + la a3, amo_operand; \ + sw a0, 0(a3); \ + amominu.w a4, a1, 0(a3); \ + ) + + TEST_CASE(7, a5, 0, lw a5, 0(a3)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 diff --git a/tb/qumcu/isa/rv64ua/amoor_d.S b/tb/qumcu/isa/rv64ua/amoor_d.S new file mode 100644 index 0000000..6f71495 --- /dev/null +++ b/tb/qumcu/isa/rv64ua/amoor_d.S @@ -0,0 +1,48 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amoor_d.S +#----------------------------------------------------------------------------- +# +# Test amoor.d instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a4, 0xffffffff80000000, \ + li a0, 0xffffffff80000000; \ + li a1, 0xfffffffffffff800; \ + la a3, amo_operand; \ + sd a0, 0(a3); \ + amoor.d a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0xfffffffffffff800, ld a5, 0(a3)) + + # try again after a cache miss + TEST_CASE(4, a4, 0xfffffffffffff800, \ + li a1, 1; \ + amoor.d a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0xfffffffffffff801, ld a5, 0(a3)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 diff --git a/tb/qumcu/isa/rv64ua/amoor_w.S b/tb/qumcu/isa/rv64ua/amoor_w.S new file mode 100644 index 0000000..e64b8c2 --- /dev/null +++ b/tb/qumcu/isa/rv64ua/amoor_w.S @@ -0,0 +1,48 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amoor.w.S +#----------------------------------------------------------------------------- +# +# Test amoor.w instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a4, 0xffffffff80000000, \ + li a0, 0xffffffff80000000; \ + li a1, 0xfffffffffffff800; \ + la a3, amo_operand; \ + sw a0, 0(a3); \ + amoor.w a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0xfffffffffffff800, lw a5, 0(a3)) + + # try again after a cache miss + TEST_CASE(4, a4, 0xfffffffffffff800, \ + li a1, 1; \ + amoor.w a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0xfffffffffffff801, lw a5, 0(a3)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 diff --git a/tb/qumcu/isa/rv64ua/amoswap_d.S b/tb/qumcu/isa/rv64ua/amoswap_d.S new file mode 100644 index 0000000..6b07d74 --- /dev/null +++ b/tb/qumcu/isa/rv64ua/amoswap_d.S @@ -0,0 +1,48 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amoswap.d.S +#----------------------------------------------------------------------------- +# +# Test amoswap.d instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a4, 0xffffffff80000000, \ + li a0, 0xffffffff80000000; \ + li a1, 0xfffffffffffff800; \ + la a3, amo_operand; \ + sd a0, 0(a3); \ + amoswap.d a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0xfffffffffffff800, ld a5, 0(a3)) + + # try again after a cache miss + TEST_CASE(4, a4, 0xfffffffffffff800, \ + li a1, 0x0000000080000000; \ + amoswap.d a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0x0000000080000000, ld a5, 0(a3)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 diff --git a/tb/qumcu/isa/rv64ua/amoswap_w.S b/tb/qumcu/isa/rv64ua/amoswap_w.S new file mode 100644 index 0000000..c4276dc --- /dev/null +++ b/tb/qumcu/isa/rv64ua/amoswap_w.S @@ -0,0 +1,48 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amoswap_w.S +#----------------------------------------------------------------------------- +# +# Test amoswap.w instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a4, 0xffffffff80000000, \ + li a0, 0xffffffff80000000; \ + li a1, 0xfffffffffffff800; \ + la a3, amo_operand; \ + sw a0, 0(a3); \ + amoswap.w a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0xfffffffffffff800, lw a5, 0(a3)) + + # try again after a cache miss + TEST_CASE(4, a4, 0xfffffffffffff800, \ + li a1, 0x0000000080000000; \ + amoswap.w a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0xffffffff80000000, lw a5, 0(a3)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 diff --git a/tb/qumcu/isa/rv64ua/amoxor_d.S b/tb/qumcu/isa/rv64ua/amoxor_d.S new file mode 100644 index 0000000..8305434 --- /dev/null +++ b/tb/qumcu/isa/rv64ua/amoxor_d.S @@ -0,0 +1,48 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amoxor_d.S +#----------------------------------------------------------------------------- +# +# Test amoxor.d instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a4, 0xffffffff80000000, \ + li a0, 0xffffffff80000000; \ + li a1, 0xfffffffffffff800; \ + la a3, amo_operand; \ + sd a0, 0(a3); \ + amoxor.d a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0x000000007ffff800, ld a5, 0(a3)) + + # try again after a cache miss + TEST_CASE(4, a4, 0x000000007ffff800, \ + li a1, 1; \ + amoxor.d a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0x000000007ffff801, ld a5, 0(a3)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 diff --git a/tb/qumcu/isa/rv64ua/amoxor_w.S b/tb/qumcu/isa/rv64ua/amoxor_w.S new file mode 100644 index 0000000..1b6fc48 --- /dev/null +++ b/tb/qumcu/isa/rv64ua/amoxor_w.S @@ -0,0 +1,48 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amoxor_w.S +#----------------------------------------------------------------------------- +# +# Test amoxor.w instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a4, 0xffffffff80000000, \ + li a0, 0xffffffff80000000; \ + li a1, 0xfffffffffffff800; \ + la a3, amo_operand; \ + sw a0, 0(a3); \ + amoxor.w a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0x7ffff800, lw a5, 0(a3)) + + # try again after a cache miss + TEST_CASE(4, a4, 0x7ffff800, \ + li a1, 0xc0000001; \ + amoxor.w a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0xffffffffbffff801, lw a5, 0(a3)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 diff --git a/tb/qumcu/isa/rv64ua/lrsc.S b/tb/qumcu/isa/rv64ua/lrsc.S new file mode 100644 index 0000000..39fb156 --- /dev/null +++ b/tb/qumcu/isa/rv64ua/lrsc.S @@ -0,0 +1,111 @@ +# See LICENSE for license details. + +#***************************************************************************** +# lrsr.S +#----------------------------------------------------------------------------- +# +# Test LR/SC instructions. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + +# get a unique core id +la a0, coreid +li a1, 1 +amoadd.w a2, a1, (a0) + +# for now, only run this on core 0 +1:li a3, 1 +bgeu a2, a3, 1b + +1: lw a1, (a0) +bltu a1, a3, 1b + +# make sure that sc without a reservation fails. +TEST_CASE( 2, a4, 1, \ + la a0, foo; \ + li a5, 0xdeadbeef; \ + sc.w a4, a5, (a0); \ +) + +# make sure the failing sc did not commit into memory +TEST_CASE( 3, a4, 0, \ + lw a4, foo; \ +) + +# +# Disable test case 4 for now. It assumes a <1K reservation granule, when +# in reality any size granule is valid. After discussion in issue #315, +# decided to simply disable the test for now. +# (See https://github.com/riscv/riscv-tests/issues/315) +# +## make sure that sc with the wrong reservation fails. +## TODO is this actually mandatory behavior? +#TEST_CASE( 4, a4, 1, \ +# la a0, foo; \ +# la a1, fooTest3; \ +# lr.w a1, (a1); \ +# sc.w a4, a1, (a0); \ +#) + +#define LOG_ITERATIONS 10 + +# have each core add its coreid+1 to foo 1024 times +la a0, foo +li a1, 1<= 64 + TEST_INT_FP_OP_D(6, fcvt.d.l, 2.0, 2); + TEST_INT_FP_OP_D(7, fcvt.d.l, -2.0, -2); + + TEST_INT_FP_OP_D(8, fcvt.d.lu, 2.0, 2); + TEST_INT_FP_OP_D(9, fcvt.d.lu, 1.8446744073709552e19, -2); +#endif + + TEST_FCVT_S_D(10, -1.5, -1.5) + TEST_FCVT_D_S(11, -1.5, -1.5) + +#if __riscv_xlen >= 64 + TEST_CASE(12, a0, 0x7ff8000000000000, + la a1, test_data_22; + ld a2, 0(a1); + fmv.d.x f2, a2; + fcvt.s.d f2, f2; + fcvt.d.s f2, f2; + fmv.x.d a0, f2; + ) +#else + TEST_CASE_D32(12, a0, a1, 0x7ff8000000000000, + la a1, test_data_22; + fld f2, 0(a1); + fcvt.s.d f2, f2; + fcvt.d.s f2, f2; + fsd f2, 0(a1); + lw a0, 0(a1); + lw a1, 4(a1) + ) +#endif + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +test_data_22: + .dword 0x7ffcffffffff8004 + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64ud/fcvt_w.S b/tb/qumcu/isa/rv64ud/fcvt_w.S new file mode 100644 index 0000000..56cc29d --- /dev/null +++ b/tb/qumcu/isa/rv64ud/fcvt_w.S @@ -0,0 +1,114 @@ +# See LICENSE for license details. + +#***************************************************************************** +# fcvt_w.S +#----------------------------------------------------------------------------- +# +# Test fcvt{wu|w|lu|l}.d instructions. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64UF +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_FP_INT_OP_D( 2, fcvt.w.d, 0x01, -1, -1.1, rtz); + TEST_FP_INT_OP_D( 3, fcvt.w.d, 0x00, -1, -1.0, rtz); + TEST_FP_INT_OP_D( 4, fcvt.w.d, 0x01, 0, -0.9, rtz); + TEST_FP_INT_OP_D( 5, fcvt.w.d, 0x01, 0, 0.9, rtz); + TEST_FP_INT_OP_D( 6, fcvt.w.d, 0x00, 1, 1.0, rtz); + TEST_FP_INT_OP_D( 7, fcvt.w.d, 0x01, 1, 1.1, rtz); + TEST_FP_INT_OP_D( 8, fcvt.w.d, 0x10, -1<<31, -3e9, rtz); + TEST_FP_INT_OP_D( 9, fcvt.w.d, 0x10, (1<<31)-1, 3e9, rtz); + + TEST_FP_INT_OP_D(12, fcvt.wu.d, 0x10, 0, -3.0, rtz); + TEST_FP_INT_OP_D(13, fcvt.wu.d, 0x10, 0, -1.0, rtz); + TEST_FP_INT_OP_D(14, fcvt.wu.d, 0x01, 0, -0.9, rtz); + TEST_FP_INT_OP_D(15, fcvt.wu.d, 0x01, 0, 0.9, rtz); + TEST_FP_INT_OP_D(16, fcvt.wu.d, 0x00, 1, 1.0, rtz); + TEST_FP_INT_OP_D(17, fcvt.wu.d, 0x01, 1, 1.1, rtz); + TEST_FP_INT_OP_D(18, fcvt.wu.d, 0x10, 0, -3e9, rtz); + TEST_FP_INT_OP_D(19, fcvt.wu.d, 0x00, 0xffffffffb2d05e00, 3e9, rtz); + +#if __riscv_xlen >= 64 + TEST_FP_INT_OP_D(22, fcvt.l.d, 0x01, -1, -1.1, rtz); + TEST_FP_INT_OP_D(23, fcvt.l.d, 0x00, -1, -1.0, rtz); + TEST_FP_INT_OP_D(24, fcvt.l.d, 0x01, 0, -0.9, rtz); + TEST_FP_INT_OP_D(25, fcvt.l.d, 0x01, 0, 0.9, rtz); + TEST_FP_INT_OP_D(26, fcvt.l.d, 0x00, 1, 1.0, rtz); + TEST_FP_INT_OP_D(27, fcvt.l.d, 0x01, 1, 1.1, rtz); + TEST_FP_INT_OP_D(28, fcvt.l.d, 0x00,-3000000000, -3e9, rtz); + TEST_FP_INT_OP_D(29, fcvt.l.d, 0x00, 3000000000, 3e9, rtz); + TEST_FP_INT_OP_D(20, fcvt.l.d, 0x10, -1<<63,-3e19, rtz); + TEST_FP_INT_OP_D(21, fcvt.l.d, 0x10, (1<<63)-1, 3e19, rtz); + + TEST_FP_INT_OP_D(32, fcvt.lu.d, 0x10, 0, -3.0, rtz); + TEST_FP_INT_OP_D(33, fcvt.lu.d, 0x10, 0, -1.0, rtz); + TEST_FP_INT_OP_D(34, fcvt.lu.d, 0x01, 0, -0.9, rtz); + TEST_FP_INT_OP_D(35, fcvt.lu.d, 0x01, 0, 0.9, rtz); + TEST_FP_INT_OP_D(36, fcvt.lu.d, 0x00, 1, 1.0, rtz); + TEST_FP_INT_OP_D(37, fcvt.lu.d, 0x01, 1, 1.1, rtz); + TEST_FP_INT_OP_D(38, fcvt.lu.d, 0x10, 0, -3e9, rtz); + TEST_FP_INT_OP_D(39, fcvt.lu.d, 0x00, 3000000000, 3e9, rtz); +#endif + + # test negative NaN, negative infinity conversion + TEST_CASE(42, x1, 0x000000007fffffff, la x1, tdat_d; fld f1, 0(x1); fcvt.w.d x1, f1) +#if __riscv_xlen >= 64 + TEST_CASE(43, x1, 0x7fffffffffffffff, la x1, tdat_d; fld f1, 0(x1); fcvt.l.d x1, f1) +#endif + TEST_CASE(44, x1, 0xffffffff80000000, la x1, tdat_d; fld f1, 16(x1); fcvt.w.d x1, f1) +#if __riscv_xlen >= 64 + TEST_CASE(45, x1, 0x8000000000000000, la x1, tdat_d; fld f1, 16(x1); fcvt.l.d x1, f1) +#endif + + # test positive NaN, positive infinity conversion + TEST_CASE(52, x1, 0x000000007fffffff, la x1, tdat_d; fld f1, 8(x1); fcvt.w.d x1, f1) +#if __riscv_xlen >= 64 + TEST_CASE(53, x1, 0x7fffffffffffffff, la x1, tdat_d; fld f1, 8(x1); fcvt.l.d x1, f1) +#endif + TEST_CASE(54, x1, 0x000000007fffffff, la x1, tdat_d; fld f1, 24(x1); fcvt.w.d x1, f1) +#if __riscv_xlen >= 64 + TEST_CASE(55, x1, 0x7fffffffffffffff, la x1, tdat_d; fld f1, 24(x1); fcvt.l.d x1, f1) +#endif + + # test NaN, infinity conversions to unsigned integer + TEST_CASE(62, x1, 0xffffffffffffffff, la x1, tdat_d; fld f1, 0(x1); fcvt.wu.d x1, f1) + TEST_CASE(63, x1, 0xffffffffffffffff, la x1, tdat_d; fld f1, 8(x1); fcvt.wu.d x1, f1) + TEST_CASE(64, x1, 0, la x1, tdat_d; fld f1, 16(x1); fcvt.wu.d x1, f1) + TEST_CASE(65, x1, 0xffffffffffffffff, la x1, tdat_d; fld f1, 24(x1); fcvt.wu.d x1, f1) +#if __riscv_xlen >= 64 + TEST_CASE(66, x1, 0xffffffffffffffff, la x1, tdat_d; fld f1, 0(x1); fcvt.lu.d x1, f1) + TEST_CASE(67, x1, 0xffffffffffffffff, la x1, tdat_d; fld f1, 8(x1); fcvt.lu.d x1, f1) + TEST_CASE(68, x1, 0, la x1, tdat_d; fld f1, 16(x1); fcvt.lu.d x1, f1) + TEST_CASE(69, x1, 0xffffffffffffffff, la x1, tdat_d; fld f1, 24(x1); fcvt.lu.d x1, f1) +#endif + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +# -NaN, NaN, -inf, +inf +tdat: +.word 0xffffffff +.word 0x7fffffff +.word 0xff800000 +.word 0x7f800000 + +tdat_d: +.dword 0xffffffffffffffff +.dword 0x7fffffffffffffff +.dword 0xfff0000000000000 +.dword 0x7ff0000000000000 + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64ud/fdiv.S b/tb/qumcu/isa/rv64ud/fdiv.S new file mode 100644 index 0000000..f985fa1 --- /dev/null +++ b/tb/qumcu/isa/rv64ud/fdiv.S @@ -0,0 +1,54 @@ +# See LICENSE for license details. + +#***************************************************************************** +# fdiv.S +#----------------------------------------------------------------------------- +# +# Test f{div|sqrt}.d instructions. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64UF +RVTEST_CODE_BEGIN + +#if __riscv_xlen == 32 + # Replace the functions with the 32-bit variants defined in test_macros.h + #undef TEST_FP_OP2_D + #define TEST_FP_OP2_D TEST_FP_OP2_D32 + + #undef TEST_FP_OP1_D + #define TEST_FP_OP1_D TEST_FP_OP1_D32 + + #undef TEST_FP_OP1_D_DWORD_RESULT + #define TEST_FP_OP1_D_DWORD_RESULT TEST_FP_OP1_D32_DWORD_RESULT +#endif + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_FP_OP2_D( 2, fdiv.d, 1, 1.1557273520668288, 3.14159265, 2.71828182 ); + TEST_FP_OP2_D( 3, fdiv.d, 1,-0.9991093838555584, -1234, 1235.1 ); + TEST_FP_OP2_D( 4, fdiv.d, 0, 3.14159265, 3.14159265, 1.0 ); + + TEST_FP_OP1_D( 5, fsqrt.d, 1, 1.7724538498928541, 3.14159265 ); + TEST_FP_OP1_D( 6, fsqrt.d, 0, 100, 10000 ); + + TEST_FP_OP1_D_DWORD_RESULT(16, fsqrt.d, 0x10, 0x7FF8000000000000, -1.0 ); + + TEST_FP_OP1_D( 7, fsqrt.d, 1, 13.076696830622021, 171.0); + + TEST_FP_OP1_D( 8, fsqrt.d, 1,0.00040099251863345283320230749702, 1.60795e-7); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64ud/fmadd.S b/tb/qumcu/isa/rv64ud/fmadd.S new file mode 100644 index 0000000..1e3ba66 --- /dev/null +++ b/tb/qumcu/isa/rv64ud/fmadd.S @@ -0,0 +1,51 @@ +# See LICENSE for license details. + +#***************************************************************************** +# fmadd.S +#----------------------------------------------------------------------------- +# +# Test f[n]m{add|sub}.s and f[n]m{add|sub}.d instructions. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64UF +RVTEST_CODE_BEGIN + +#if __riscv_xlen == 32 + # Replace the function with the 32-bit variant defined in test_macros.h + #undef TEST_FP_OP3_D + #define TEST_FP_OP3_D TEST_FP_OP3_D32 +#endif + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_FP_OP3_D( 2, fmadd.d, 0, 3.5, 1.0, 2.5, 1.0 ); + TEST_FP_OP3_D( 3, fmadd.d, 1, 1236.1999999999999, -1.0, -1235.1, 1.1 ); + TEST_FP_OP3_D( 4, fmadd.d, 0, -12.0, 2.0, -5.0, -2.0 ); + + TEST_FP_OP3_D( 5, fnmadd.d, 0, -3.5, 1.0, 2.5, 1.0 ); + TEST_FP_OP3_D( 6, fnmadd.d, 1, -1236.1999999999999, -1.0, -1235.1, 1.1 ); + TEST_FP_OP3_D( 7, fnmadd.d, 0, 12.0, 2.0, -5.0, -2.0 ); + + TEST_FP_OP3_D( 8, fmsub.d, 0, 1.5, 1.0, 2.5, 1.0 ); + TEST_FP_OP3_D( 9, fmsub.d, 1, 1234, -1.0, -1235.1, 1.1 ); + TEST_FP_OP3_D(10, fmsub.d, 0, -8.0, 2.0, -5.0, -2.0 ); + + TEST_FP_OP3_D(11, fnmsub.d, 0, -1.5, 1.0, 2.5, 1.0 ); + TEST_FP_OP3_D(12, fnmsub.d, 1, -1234, -1.0, -1235.1, 1.1 ); + TEST_FP_OP3_D(13, fnmsub.d, 0, 8.0, 2.0, -5.0, -2.0 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64ud/fmin.S b/tb/qumcu/isa/rv64ud/fmin.S new file mode 100644 index 0000000..8f270a5 --- /dev/null +++ b/tb/qumcu/isa/rv64ud/fmin.S @@ -0,0 +1,60 @@ +# See LICENSE for license details. + +#***************************************************************************** +# fmin.S +#----------------------------------------------------------------------------- +# +# Test f{min|max}.d instructinos. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64UF +RVTEST_CODE_BEGIN + +#if __riscv_xlen == 32 + # Replace the function with the 32-bit variant defined in test_macros.h + #undef TEST_FP_OP2_D + #define TEST_FP_OP2_D TEST_FP_OP2_D32 +#endif + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_FP_OP2_D( 2, fmin.d, 0, 1.0, 2.5, 1.0 ); + TEST_FP_OP2_D( 3, fmin.d, 0, -1235.1, -1235.1, 1.1 ); + TEST_FP_OP2_D( 4, fmin.d, 0, -1235.1, 1.1, -1235.1 ); + TEST_FP_OP2_D( 5, fmin.d, 0, -1235.1, NaN, -1235.1 ); + TEST_FP_OP2_D( 6, fmin.d, 0, 0.00000001, 3.14159265, 0.00000001 ); + TEST_FP_OP2_D( 7, fmin.d, 0, -2.0, -1.0, -2.0 ); + + TEST_FP_OP2_D(12, fmax.d, 0, 2.5, 2.5, 1.0 ); + TEST_FP_OP2_D(13, fmax.d, 0, 1.1, -1235.1, 1.1 ); + TEST_FP_OP2_D(14, fmax.d, 0, 1.1, 1.1, -1235.1 ); + TEST_FP_OP2_D(15, fmax.d, 0, -1235.1, NaN, -1235.1 ); + TEST_FP_OP2_D(16, fmax.d, 0, 3.14159265, 3.14159265, 0.00000001 ); + TEST_FP_OP2_D(17, fmax.d, 0, -1.0, -1.0, -2.0 ); + + # FMAX(sNaN, x) = x + TEST_FP_OP2_D(20, fmax.d, 0x10, 1.0, sNaN, 1.0); + # FMAX(qNaN, qNaN) = canonical NaN + TEST_FP_OP2_D(21, fmax.d, 0x00, qNaN, NaN, NaN); + + # -0.0 < +0.0 + TEST_FP_OP2_D(30, fmin.d, 0, -0.0, -0.0, 0.0 ); + TEST_FP_OP2_D(31, fmin.d, 0, -0.0, 0.0, -0.0 ); + TEST_FP_OP2_D(32, fmax.d, 0, 0.0, -0.0, 0.0 ); + TEST_FP_OP2_D(33, fmax.d, 0, 0.0, 0.0, -0.0 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64ud/ldst.S b/tb/qumcu/isa/rv64ud/ldst.S new file mode 100644 index 0000000..9629341 --- /dev/null +++ b/tb/qumcu/isa/rv64ud/ldst.S @@ -0,0 +1,42 @@ +# See LICENSE for license details. + +#***************************************************************************** +# ldst.S +#----------------------------------------------------------------------------- +# +# This test verifies that flw, fld, fsw, and fsd work properly. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64UF +RVTEST_CODE_BEGIN + + la s0, tdat + TEST_CASE(2, a0, 0x40000000bf800000, fld f2, 0(s0); fsd f2, 16(s0); ld a0, 16(s0)) + TEST_CASE(3, a0, 0x40000000bf800000, fld f2, 0(s0); fsw f2, 16(s0); ld a0, 16(s0)) + TEST_CASE(4, a0, 0x40000000bf800000, flw f2, 0(s0); fsw f2, 16(s0); ld a0, 16(s0)) + TEST_CASE(5, a0, 0xc080000040400000, fld f2, 8(s0); fsd f2, 16(s0); ld a0, 16(s0)) + TEST_CASE(6, a0, 0xffffffff40400000, flw f2, 8(s0); fsd f2, 16(s0); ld a0, 16(s0)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +tdat: +.word 0xbf800000 +.word 0x40000000 +.word 0x40400000 +.word 0xc0800000 +.word 0xdeadbeef +.word 0xcafebabe +.word 0xabad1dea +.word 0x1337d00d + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64ud/move.S b/tb/qumcu/isa/rv64ud/move.S new file mode 100644 index 0000000..8911d95 --- /dev/null +++ b/tb/qumcu/isa/rv64ud/move.S @@ -0,0 +1,113 @@ +# See LICENSE for license details. + +#***************************************************************************** +# move.S +#----------------------------------------------------------------------------- +# +# This test verifies that fmv.d.x, fmv.x.d, and fsgnj[x|n].d work properly. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64UF +RVTEST_CODE_BEGIN + +#TODO: make 32-bit compatible version +#define TEST_FSGNJD(n, insn, new_sign, rs1_sign, rs2_sign) \ + TEST_CASE(n, a0, 0x123456789abcdef0 | (-(new_sign) << 63), \ + li a1, ((rs1_sign) << 63) | 0x123456789abcdef0; \ + li a2, -(rs2_sign); \ + fmv.d.x f1, a1; \ + fmv.d.x f2, a2; \ + insn f0, f1, f2; \ + fmv.x.d a0, f0) + + TEST_FSGNJD(10, fsgnj.d, 0, 0, 0) + TEST_FSGNJD(11, fsgnj.d, 1, 0, 1) + TEST_FSGNJD(12, fsgnj.d, 0, 1, 0) + TEST_FSGNJD(13, fsgnj.d, 1, 1, 1) + + TEST_FSGNJD(20, fsgnjn.d, 1, 0, 0) + TEST_FSGNJD(21, fsgnjn.d, 0, 0, 1) + TEST_FSGNJD(22, fsgnjn.d, 1, 1, 0) + TEST_FSGNJD(23, fsgnjn.d, 0, 1, 1) + + TEST_FSGNJD(30, fsgnjx.d, 0, 0, 0) + TEST_FSGNJD(31, fsgnjx.d, 1, 0, 1) + TEST_FSGNJD(32, fsgnjx.d, 1, 1, 0) + TEST_FSGNJD(33, fsgnjx.d, 0, 1, 1) + +// Test fsgnj.s in conjunction with double-precision moves +#define TEST_FSGNJS(n, rd, rs1, rs2) \ + TEST_CASE(n, a0, (rd) | (-((rd) >> 31) << 32), \ + li a1, rs1; \ + li a2, rs2; \ + fmv.d.x f1, a1; \ + fmv.d.x f2, a2; \ + fsgnj.s f0, f1, f2; \ + fmv.x.s a0, f0); \ + TEST_CASE(1##n, a0, (rd) | 0xffffffff00000000, \ + li a1, rs1; \ + li a2, rs2; \ + fmv.d.x f1, a1; \ + fmv.d.x f2, a2; \ + fsgnj.s f0, f1, f2; \ + fmv.x.d a0, f0) + + TEST_FSGNJS(40, 0x7fc00000, 0x7ffffffe12345678, 0) + TEST_FSGNJS(41, 0x7fc00000, 0xfffffffe12345678, 0) + TEST_FSGNJS(42, 0x7fc00000, 0x7fffffff12345678, 0) + TEST_FSGNJS(43, 0x12345678, 0xffffffff12345678, 0) + + TEST_FSGNJS(50, 0x7fc00000, 0x7ffffffe12345678, 0x80000000) + TEST_FSGNJS(51, 0x7fc00000, 0xfffffffe12345678, 0x80000000) + TEST_FSGNJS(52, 0x7fc00000, 0x7fffffff12345678, 0x80000000) + TEST_FSGNJS(53, 0x12345678, 0xffffffff12345678, 0x80000000) + + TEST_FSGNJS(60, 0xffc00000, 0x7ffffffe12345678, 0xffffffff80000000) + TEST_FSGNJS(61, 0xffc00000, 0xfffffffe12345678, 0xffffffff80000000) + TEST_FSGNJS(62, 0x92345678, 0xffffffff12345678, 0xffffffff80000000) + TEST_FSGNJS(63, 0x12345678, 0xffffffff12345678, 0x7fffffff80000000) + +// Test fsgnj.d in conjunction with single-precision moves +#define TEST_FSGNJD_SP(n, isnan, rd, rs1, rs2) \ + TEST_CASE(n, a0, ((rd) & 0xffffffff) | (-(((rd) >> 31) & 1) << 32), \ + li a1, rs1; \ + li a2, rs2; \ + fmv.d.x f1, a1; \ + fmv.d.x f2, a2; \ + fsgnj.d f0, f1, f2; \ + feq.s a0, f0, f0; \ + addi a0, a0, -!(isnan); \ + bnez a0, 1f; \ + fmv.x.s a0, f0; \ + 1:); \ + TEST_CASE(1##n, a0, rd, \ + li a1, rs1; \ + li a2, rs2; \ + fmv.d.x f1, a1; \ + fmv.d.x f2, a2; \ + fsgnj.d f0, f1, f2; \ + fmv.x.d a0, f0; \ + 1:) + + TEST_FSGNJD_SP(70, 0, 0xffffffff11111111, 0xffffffff11111111, 0xffffffff11111111) + TEST_FSGNJD_SP(71, 1, 0x7fffffff11111111, 0xffffffff11111111, 0x7fffffff11111111) + TEST_FSGNJD_SP(72, 0, 0xffffffff11111111, 0xffffffff11111111, 0xffffffff91111111) + TEST_FSGNJD_SP(73, 0, 0xffffffff11111111, 0xffffffff11111111, 0x8000000000000000) + TEST_FSGNJD_SP(74, 0, 0xffffffff11111111, 0x7fffffff11111111, 0xffffffff11111111) + TEST_FSGNJD_SP(75, 1, 0x7fffffff11111111, 0x7fffffff11111111, 0x7fffffff11111111) + TEST_FSGNJD_SP(76, 0, 0xffffffff11111111, 0x7fffffff11111111, 0xffffffff91111111) + TEST_FSGNJD_SP(77, 0, 0xffffffff11111111, 0x7fffffff11111111, 0x8000000000000000) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64ud/recoding.S b/tb/qumcu/isa/rv64ud/recoding.S new file mode 100644 index 0000000..69ad665 --- /dev/null +++ b/tb/qumcu/isa/rv64ud/recoding.S @@ -0,0 +1,67 @@ +# See LICENSE for license details. + +#***************************************************************************** +# recoding.S +#----------------------------------------------------------------------------- +# +# Test corner cases of John Hauser's microarchitectural recoding scheme. +# There are twice as many recoded values as IEEE-754 values; some of these +# extras are redundant (e.g. Inf) and others are illegal (subnormals with +# too many bits set). +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64UF +RVTEST_CODE_BEGIN + + # Make sure infinities with different mantissas compare as equal. + fld f0, minf, a0 + fld f1, three, a0 + fmul.d f1, f1, f0 + TEST_CASE( 2, a0, 1, feq.d a0, f0, f1) + TEST_CASE( 3, a0, 1, fle.d a0, f0, f1) + TEST_CASE( 4, a0, 0, flt.d a0, f0, f1) + + # Likewise, but for zeroes. + fcvt.d.w f0, x0 + li a0, 1 + fcvt.d.w f1, a0 + fmul.d f1, f1, f0 + TEST_CASE(5, a0, 1, feq.d a0, f0, f1) + TEST_CASE(6, a0, 1, fle.d a0, f0, f1) + TEST_CASE(7, a0, 0, flt.d a0, f0, f1) + + # When converting small doubles to single-precision subnormals, + # ensure that the extra precision is discarded. + flw f0, big, a0 + fld f1, tiny, a0 + fcvt.s.d f1, f1 + fmul.s f0, f0, f1 + fmv.x.s a0, f0 + lw a1, small + TEST_CASE(10, a0, 0, sub a0, a0, a1) + + # Make sure FSD+FLD correctly saves and restores a single-precision value. + flw f0, three, a0 + fadd.s f1, f0, f0 + fadd.s f0, f0, f0 + fsd f0, tiny, a0 + fld f0, tiny, a0 + TEST_CASE(20, a0, 1, feq.s a0, f0, f1) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + +minf: .double -Inf +three: .double 3.0 +big: .float 1221 +small: .float 2.9133121e-37 +tiny: .double 2.3860049081905093e-40 + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64ud/structural.S b/tb/qumcu/isa/rv64ud/structural.S new file mode 100644 index 0000000..726275a --- /dev/null +++ b/tb/qumcu/isa/rv64ud/structural.S @@ -0,0 +1,60 @@ +# See LICENSE for license details. + +#***************************************************************************** +# structural.S +#----------------------------------------------------------------------------- +# +# This test verifies that the FPU correctly obviates structural hazards on its +# writeback port (e.g. fadd followed by fsgnj) +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64UF +RVTEST_CODE_BEGIN + +li x12, 1 + +li x2, 0x3FF0000000000000 +li x1, 0x3F800000 + +#define TEST(testnum, nops) \ +test_ ## testnum: \ + li TESTNUM, testnum; \ + fmv.d.x f4, x0 ;\ + fmv.s.x f3, x0 ;\ + fmv.d.x f2, x2 ;\ + fmv.s.x f1, x1 ;\ + j 1f ;\ + .align 5 ;\ +1:fmul.d f4, f2, f2 ;\ + nops ;\ + fsgnj.s f3, f1, f1 ;\ + fmv.x.d x4, f4 ;\ + fmv.x.s x5, f3 ;\ + beq x1, x5, 2f ;\ + j fail;\ +2:beq x2, x4, 2f ;\ + j fail; \ +2:fmv.d.x f2, zero ;\ + fmv.s.x f1, zero ;\ + +TEST(1,;) +TEST(2,nop) +TEST(3,nop;nop) +TEST(4,nop;nop;nop) +TEST(5,nop;nop;nop;nop) +TEST(6,nop;nop;nop;nop;nop) +TEST(7,nop;nop;nop;nop;nop;nop) + +TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64uf/Makefrag b/tb/qumcu/isa/rv64uf/Makefrag new file mode 100644 index 0000000..2b67905 --- /dev/null +++ b/tb/qumcu/isa/rv64uf/Makefrag @@ -0,0 +1,10 @@ +#======================================================================= +# Makefrag for rv64uf tests +#----------------------------------------------------------------------- + +rv64uf_sc_tests = \ + fadd fdiv fclass fcmp fcvt fcvt_w fmadd fmin \ + ldst move recoding \ + +rv64uf_p_tests = $(addprefix rv64uf-p-, $(rv64uf_sc_tests)) +rv64uf_v_tests = $(addprefix rv64uf-v-, $(rv64uf_sc_tests)) diff --git a/tb/qumcu/isa/rv64uf/fadd.S b/tb/qumcu/isa/rv64uf/fadd.S new file mode 100644 index 0000000..b6259df --- /dev/null +++ b/tb/qumcu/isa/rv64uf/fadd.S @@ -0,0 +1,44 @@ +# See LICENSE for license details. + +#***************************************************************************** +# fadd.S +#----------------------------------------------------------------------------- +# +# Test f{add|sub|mul}.s instructions. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64UF +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_FP_OP2_S( 2, fadd.s, 0, 3.5, 2.5, 1.0 ); + TEST_FP_OP2_S( 3, fadd.s, 1, -1234, -1235.1, 1.1 ); + TEST_FP_OP2_S( 4, fadd.s, 1, 3.14159265, 3.14159265, 0.00000001 ); + + TEST_FP_OP2_S( 5, fsub.s, 0, 1.5, 2.5, 1.0 ); + TEST_FP_OP2_S( 6, fsub.s, 1, -1234, -1235.1, -1.1 ); + TEST_FP_OP2_S( 7, fsub.s, 1, 3.14159265, 3.14159265, 0.00000001 ); + + TEST_FP_OP2_S( 8, fmul.s, 0, 2.5, 2.5, 1.0 ); + TEST_FP_OP2_S( 9, fmul.s, 1, 1358.61, -1235.1, -1.1 ); + TEST_FP_OP2_S(10, fmul.s, 1, 3.14159265e-8, 3.14159265, 0.00000001 ); + + # Is the canonical NaN generated for Inf - Inf? + TEST_FP_OP2_S(11, fsub.s, 0x10, qNaNf, Inf, Inf); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64uf/fclass.S b/tb/qumcu/isa/rv64uf/fclass.S new file mode 100644 index 0000000..9bb86b1 --- /dev/null +++ b/tb/qumcu/isa/rv64uf/fclass.S @@ -0,0 +1,40 @@ +# See LICENSE for license details. + +#***************************************************************************** +# fclass.S +#----------------------------------------------------------------------------- +# +# Test fclass.s instructions. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64UF +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_FCLASS_S( 2, 1 << 0, 0xff800000 ) + TEST_FCLASS_S( 3, 1 << 1, 0xbf800000 ) + TEST_FCLASS_S( 4, 1 << 2, 0x807fffff ) + TEST_FCLASS_S( 5, 1 << 3, 0x80000000 ) + TEST_FCLASS_S( 6, 1 << 4, 0x00000000 ) + TEST_FCLASS_S( 7, 1 << 5, 0x007fffff ) + TEST_FCLASS_S( 8, 1 << 6, 0x3f800000 ) + TEST_FCLASS_S( 9, 1 << 7, 0x7f800000 ) + TEST_FCLASS_S(10, 1 << 8, 0x7f800001 ) + TEST_FCLASS_S(11, 1 << 9, 0x7fc00000 ) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64uf/fcmp.S b/tb/qumcu/isa/rv64uf/fcmp.S new file mode 100644 index 0000000..2d7fcc2 --- /dev/null +++ b/tb/qumcu/isa/rv64uf/fcmp.S @@ -0,0 +1,50 @@ +# See LICENSE for license details. + +#***************************************************************************** +# fcmp.S +#----------------------------------------------------------------------------- +# +# Test f{eq|lt|le}.s instructions. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64UF +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_FP_CMP_OP_S( 2, feq.s, 0x00, 1, -1.36, -1.36) + TEST_FP_CMP_OP_S( 3, fle.s, 0x00, 1, -1.36, -1.36) + TEST_FP_CMP_OP_S( 4, flt.s, 0x00, 0, -1.36, -1.36) + + TEST_FP_CMP_OP_S( 5, feq.s, 0x00, 0, -1.37, -1.36) + TEST_FP_CMP_OP_S( 6, fle.s, 0x00, 1, -1.37, -1.36) + TEST_FP_CMP_OP_S( 7, flt.s, 0x00, 1, -1.37, -1.36) + + # Only sNaN should signal invalid for feq. + TEST_FP_CMP_OP_S( 8, feq.s, 0x00, 0, NaN, 0) + TEST_FP_CMP_OP_S( 9, feq.s, 0x00, 0, NaN, NaN) + TEST_FP_CMP_OP_S(10, feq.s, 0x10, 0, sNaNf, 0) + + # qNaN should signal invalid for fle/flt. + TEST_FP_CMP_OP_S(11, flt.s, 0x10, 0, NaN, 0) + TEST_FP_CMP_OP_S(12, flt.s, 0x10, 0, NaN, NaN) + TEST_FP_CMP_OP_S(13, flt.s, 0x10, 0, sNaNf, 0) + TEST_FP_CMP_OP_S(14, fle.s, 0x10, 0, NaN, 0) + TEST_FP_CMP_OP_S(15, fle.s, 0x10, 0, NaN, NaN) + TEST_FP_CMP_OP_S(16, fle.s, 0x10, 0, sNaNf, 0) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64uf/fcvt.S b/tb/qumcu/isa/rv64uf/fcvt.S new file mode 100644 index 0000000..a41686e --- /dev/null +++ b/tb/qumcu/isa/rv64uf/fcvt.S @@ -0,0 +1,43 @@ +# See LICENSE for license details. + +#***************************************************************************** +# fcvt.S +#----------------------------------------------------------------------------- +# +# Test fcvt.s.{wu|w|lu|l}, fcvt.s.d, and fcvt.d.s instructions. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64UF +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_INT_FP_OP_S( 2, fcvt.s.w, 2.0, 2); + TEST_INT_FP_OP_S( 3, fcvt.s.w, -2.0, -2); + + TEST_INT_FP_OP_S( 4, fcvt.s.wu, 2.0, 2); + TEST_INT_FP_OP_S( 5, fcvt.s.wu, 4.2949673e9, -2); + +#if __riscv_xlen >= 64 + TEST_INT_FP_OP_S( 6, fcvt.s.l, 2.0, 2); + TEST_INT_FP_OP_S( 7, fcvt.s.l, -2.0, -2); + + TEST_INT_FP_OP_S( 8, fcvt.s.lu, 2.0, 2); + TEST_INT_FP_OP_S( 9, fcvt.s.lu, 1.8446744e19, -2); +#endif + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64uf/fcvt_w.S b/tb/qumcu/isa/rv64uf/fcvt_w.S new file mode 100644 index 0000000..cad5cba --- /dev/null +++ b/tb/qumcu/isa/rv64uf/fcvt_w.S @@ -0,0 +1,105 @@ +# See LICENSE for license details. + +#***************************************************************************** +# fcvt_w.S +#----------------------------------------------------------------------------- +# +# Test fcvt{wu|w|lu|l}.s instructions. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64UF +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_FP_INT_OP_S( 2, fcvt.w.s, 0x01, -1, -1.1, rtz); + TEST_FP_INT_OP_S( 3, fcvt.w.s, 0x00, -1, -1.0, rtz); + TEST_FP_INT_OP_S( 4, fcvt.w.s, 0x01, 0, -0.9, rtz); + TEST_FP_INT_OP_S( 5, fcvt.w.s, 0x01, 0, 0.9, rtz); + TEST_FP_INT_OP_S( 6, fcvt.w.s, 0x00, 1, 1.0, rtz); + TEST_FP_INT_OP_S( 7, fcvt.w.s, 0x01, 1, 1.1, rtz); + TEST_FP_INT_OP_S( 8, fcvt.w.s, 0x10, -1<<31, -3e9, rtz); + TEST_FP_INT_OP_S( 9, fcvt.w.s, 0x10, (1<<31)-1, 3e9, rtz); + + TEST_FP_INT_OP_S(12, fcvt.wu.s, 0x10, 0, -3.0, rtz); + TEST_FP_INT_OP_S(13, fcvt.wu.s, 0x10, 0, -1.0, rtz); + TEST_FP_INT_OP_S(14, fcvt.wu.s, 0x01, 0, -0.9, rtz); + TEST_FP_INT_OP_S(15, fcvt.wu.s, 0x01, 0, 0.9, rtz); + TEST_FP_INT_OP_S(16, fcvt.wu.s, 0x00, 1, 1.0, rtz); + TEST_FP_INT_OP_S(17, fcvt.wu.s, 0x01, 1, 1.1, rtz); + TEST_FP_INT_OP_S(18, fcvt.wu.s, 0x10, 0, -3e9, rtz); + TEST_FP_INT_OP_S(19, fcvt.wu.s, 0x00, 3000000000, 3e9, rtz); + +#if __riscv_xlen >= 64 + TEST_FP_INT_OP_S(22, fcvt.l.s, 0x01, -1, -1.1, rtz); + TEST_FP_INT_OP_S(23, fcvt.l.s, 0x00, -1, -1.0, rtz); + TEST_FP_INT_OP_S(24, fcvt.l.s, 0x01, 0, -0.9, rtz); + TEST_FP_INT_OP_S(25, fcvt.l.s, 0x01, 0, 0.9, rtz); + TEST_FP_INT_OP_S(26, fcvt.l.s, 0x00, 1, 1.0, rtz); + TEST_FP_INT_OP_S(27, fcvt.l.s, 0x01, 1, 1.1, rtz); + + TEST_FP_INT_OP_S(32, fcvt.lu.s, 0x10, 0, -3.0, rtz); + TEST_FP_INT_OP_S(33, fcvt.lu.s, 0x10, 0, -1.0, rtz); + TEST_FP_INT_OP_S(34, fcvt.lu.s, 0x01, 0, -0.9, rtz); + TEST_FP_INT_OP_S(35, fcvt.lu.s, 0x01, 0, 0.9, rtz); + TEST_FP_INT_OP_S(36, fcvt.lu.s, 0x00, 1, 1.0, rtz); + TEST_FP_INT_OP_S(37, fcvt.lu.s, 0x01, 1, 1.1, rtz); + TEST_FP_INT_OP_S(38, fcvt.lu.s, 0x10, 0, -3e9, rtz); +#endif + + # test negative NaN, negative infinity conversion + TEST_CASE( 42, x1, 0x000000007fffffff, la x1, tdat ; flw f1, 0(x1); fcvt.w.s x1, f1) + TEST_CASE( 44, x1, 0xffffffff80000000, la x1, tdat ; flw f1, 8(x1); fcvt.w.s x1, f1) +#if __riscv_xlen >= 64 + TEST_CASE( 43, x1, 0x7fffffffffffffff, la x1, tdat ; flw f1, 0(x1); fcvt.l.s x1, f1) + TEST_CASE( 45, x1, 0x8000000000000000, la x1, tdat ; flw f1, 8(x1); fcvt.l.s x1, f1) +#endif + + # test positive NaN, positive infinity conversion + TEST_CASE( 52, x1, 0x000000007fffffff, la x1, tdat ; flw f1, 4(x1); fcvt.w.s x1, f1) + TEST_CASE( 54, x1, 0x000000007fffffff, la x1, tdat ; flw f1, 12(x1); fcvt.w.s x1, f1) +#if __riscv_xlen >= 64 + TEST_CASE( 53, x1, 0x7fffffffffffffff, la x1, tdat ; flw f1, 4(x1); fcvt.l.s x1, f1) + TEST_CASE( 55, x1, 0x7fffffffffffffff, la x1, tdat ; flw f1, 12(x1); fcvt.l.s x1, f1) +#endif + + # test NaN, infinity conversions to unsigned integer + TEST_CASE( 62, x1, 0xffffffffffffffff, la x1, tdat ; flw f1, 0(x1); fcvt.wu.s x1, f1) + TEST_CASE( 63, x1, 0xffffffffffffffff, la x1, tdat ; flw f1, 4(x1); fcvt.wu.s x1, f1) + TEST_CASE( 64, x1, 0, la x1, tdat ; flw f1, 8(x1); fcvt.wu.s x1, f1) + TEST_CASE( 65, x1, 0xffffffffffffffff, la x1, tdat ; flw f1, 12(x1); fcvt.wu.s x1, f1) +#if __riscv_xlen >= 64 + TEST_CASE( 66, x1, 0xffffffffffffffff, la x1, tdat ; flw f1, 0(x1); fcvt.lu.s x1, f1) + TEST_CASE( 67, x1, 0xffffffffffffffff, la x1, tdat ; flw f1, 4(x1); fcvt.lu.s x1, f1) + TEST_CASE( 68, x1, 0, la x1, tdat ; flw f1, 8(x1); fcvt.lu.s x1, f1) + TEST_CASE( 69, x1, 0xffffffffffffffff, la x1, tdat ; flw f1, 12(x1); fcvt.lu.s x1, f1) +#endif + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +# -NaN, NaN, -inf, +inf +tdat: +.word 0xffffffff +.word 0x7fffffff +.word 0xff800000 +.word 0x7f800000 + +tdat_d: +.dword 0xffffffffffffffff +.dword 0x7fffffffffffffff +.dword 0xfff0000000000000 +.dword 0x7ff0000000000000 + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64uf/fdiv.S b/tb/qumcu/isa/rv64uf/fdiv.S new file mode 100644 index 0000000..a75a23d --- /dev/null +++ b/tb/qumcu/isa/rv64uf/fdiv.S @@ -0,0 +1,40 @@ +# See LICENSE for license details. + +#***************************************************************************** +# fdiv.S +#----------------------------------------------------------------------------- +# +# Test f{div|sqrt}.s instructions. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64UF +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_FP_OP2_S(2, fdiv.s, 1, 1.1557273520668288, 3.14159265, 2.71828182 ); + TEST_FP_OP2_S(3, fdiv.s, 1,-0.9991093838555584, -1234, 1235.1 ); + TEST_FP_OP2_S(4, fdiv.s, 0, 3.14159265, 3.14159265, 1.0 ); + + TEST_FP_OP1_S(5, fsqrt.s, 1, 1.7724538498928541, 3.14159265 ); + TEST_FP_OP1_S(6, fsqrt.s, 0, 100, 10000 ); + + TEST_FP_OP1_S_DWORD_RESULT(7, fsqrt.s, 0x10, 0x7FC00000, -1.0 ); + + TEST_FP_OP1_S(8, fsqrt.s, 1, 13.076696, 171.0); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64uf/fmadd.S b/tb/qumcu/isa/rv64uf/fmadd.S new file mode 100644 index 0000000..241bead --- /dev/null +++ b/tb/qumcu/isa/rv64uf/fmadd.S @@ -0,0 +1,45 @@ +# See LICENSE for license details. + +#***************************************************************************** +# fmadd.S +#----------------------------------------------------------------------------- +# +# Test f[n]m{add|sub}.s and f[n]m{add|sub}.d instructions. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64UF +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_FP_OP3_S( 2, fmadd.s, 0, 3.5, 1.0, 2.5, 1.0 ); + TEST_FP_OP3_S( 3, fmadd.s, 1, 1236.2, -1.0, -1235.1, 1.1 ); + TEST_FP_OP3_S( 4, fmadd.s, 0, -12.0, 2.0, -5.0, -2.0 ); + + TEST_FP_OP3_S( 5, fnmadd.s, 0, -3.5, 1.0, 2.5, 1.0 ); + TEST_FP_OP3_S( 6, fnmadd.s, 1, -1236.2, -1.0, -1235.1, 1.1 ); + TEST_FP_OP3_S( 7, fnmadd.s, 0, 12.0, 2.0, -5.0, -2.0 ); + + TEST_FP_OP3_S( 8, fmsub.s, 0, 1.5, 1.0, 2.5, 1.0 ); + TEST_FP_OP3_S( 9, fmsub.s, 1, 1234, -1.0, -1235.1, 1.1 ); + TEST_FP_OP3_S(10, fmsub.s, 0, -8.0, 2.0, -5.0, -2.0 ); + + TEST_FP_OP3_S(11, fnmsub.s, 0, -1.5, 1.0, 2.5, 1.0 ); + TEST_FP_OP3_S(12, fnmsub.s, 1, -1234, -1.0, -1235.1, 1.1 ); + TEST_FP_OP3_S(13, fnmsub.s, 0, 8.0, 2.0, -5.0, -2.0 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64uf/fmin.S b/tb/qumcu/isa/rv64uf/fmin.S new file mode 100644 index 0000000..1f97533 --- /dev/null +++ b/tb/qumcu/isa/rv64uf/fmin.S @@ -0,0 +1,54 @@ +# See LICENSE for license details. + +#***************************************************************************** +# fmin.S +#----------------------------------------------------------------------------- +# +# Test f{min|max}.s instructinos. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64UF +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_FP_OP2_S( 2, fmin.s, 0, 1.0, 2.5, 1.0 ); + TEST_FP_OP2_S( 3, fmin.s, 0, -1235.1, -1235.1, 1.1 ); + TEST_FP_OP2_S( 4, fmin.s, 0, -1235.1, 1.1, -1235.1 ); + TEST_FP_OP2_S( 5, fmin.s, 0, -1235.1, NaN, -1235.1 ); + TEST_FP_OP2_S( 6, fmin.s, 0, 0.00000001, 3.14159265, 0.00000001 ); + TEST_FP_OP2_S( 7, fmin.s, 0, -2.0, -1.0, -2.0 ); + + TEST_FP_OP2_S(12, fmax.s, 0, 2.5, 2.5, 1.0 ); + TEST_FP_OP2_S(13, fmax.s, 0, 1.1, -1235.1, 1.1 ); + TEST_FP_OP2_S(14, fmax.s, 0, 1.1, 1.1, -1235.1 ); + TEST_FP_OP2_S(15, fmax.s, 0, -1235.1, NaN, -1235.1 ); + TEST_FP_OP2_S(16, fmax.s, 0, 3.14159265, 3.14159265, 0.00000001 ); + TEST_FP_OP2_S(17, fmax.s, 0, -1.0, -1.0, -2.0 ); + + # FMAX(sNaN, x) = x + TEST_FP_OP2_S(20, fmax.s, 0x10, 1.0, sNaNf, 1.0); + # FMAX(qNaN, qNaN) = canonical NaN + TEST_FP_OP2_S(21, fmax.s, 0x00, qNaNf, NaN, NaN); + + # -0.0 < +0.0 + TEST_FP_OP2_S(30, fmin.s, 0, -0.0, -0.0, 0.0 ); + TEST_FP_OP2_S(31, fmin.s, 0, -0.0, 0.0, -0.0 ); + TEST_FP_OP2_S(32, fmax.s, 0, 0.0, -0.0, 0.0 ); + TEST_FP_OP2_S(33, fmax.s, 0, 0.0, 0.0, -0.0 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64uf/ldst.S b/tb/qumcu/isa/rv64uf/ldst.S new file mode 100644 index 0000000..c35dd8d --- /dev/null +++ b/tb/qumcu/isa/rv64uf/ldst.S @@ -0,0 +1,38 @@ +# See LICENSE for license details. + +#***************************************************************************** +# ldst.S +#----------------------------------------------------------------------------- +# +# This test verifies that flw, fld, fsw, and fsd work properly. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64UF +RVTEST_CODE_BEGIN + + TEST_CASE(2, a0, 0x40000000deadbeef, la a1, tdat; flw f1, 4(a1); fsw f1, 20(a1); ld a0, 16(a1)) + TEST_CASE(3, a0, 0x1337d00dbf800000, la a1, tdat; flw f1, 0(a1); fsw f1, 24(a1); ld a0, 24(a1)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +tdat: +.word 0xbf800000 +.word 0x40000000 +.word 0x40400000 +.word 0xc0800000 +.word 0xdeadbeef +.word 0xcafebabe +.word 0xabad1dea +.word 0x1337d00d + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64uf/move.S b/tb/qumcu/isa/rv64uf/move.S new file mode 100644 index 0000000..60f7cf3 --- /dev/null +++ b/tb/qumcu/isa/rv64uf/move.S @@ -0,0 +1,58 @@ +# See LICENSE for license details. + +#***************************************************************************** +# move.S +#----------------------------------------------------------------------------- +# +# This test verifies that the fmv.s.x, fmv.x.s, and fsgnj[x|n].d instructions +# and the fcsr work properly. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64UF +RVTEST_CODE_BEGIN + + TEST_CASE(2, a1, 1, csrwi fcsr, 1; li a0, 0x1234; fssr a1, a0) + TEST_CASE(3, a0, 0x34, frsr a0) + TEST_CASE(4, a0, 0x14, frflags a0) + TEST_CASE(5, a0, 0x01, csrrwi a0, frm, 2) + TEST_CASE(6, a0, 0x54, frsr a0) + TEST_CASE(7, a0, 0x14, csrrci a0, fflags, 4) + TEST_CASE(8, a0, 0x50, frsr a0) + +#define TEST_FSGNJS(n, insn, new_sign, rs1_sign, rs2_sign) \ + TEST_CASE(n, a0, 0x12345678 | (-(new_sign) << 31), \ + li a1, ((rs1_sign) << 31) | 0x12345678; \ + li a2, -(rs2_sign); \ + fmv.s.x f1, a1; \ + fmv.s.x f2, a2; \ + insn f0, f1, f2; \ + fmv.x.s a0, f0) + + TEST_FSGNJS(10, fsgnj.s, 0, 0, 0) + TEST_FSGNJS(11, fsgnj.s, 1, 0, 1) + TEST_FSGNJS(12, fsgnj.s, 0, 1, 0) + TEST_FSGNJS(13, fsgnj.s, 1, 1, 1) + + TEST_FSGNJS(20, fsgnjn.s, 1, 0, 0) + TEST_FSGNJS(21, fsgnjn.s, 0, 0, 1) + TEST_FSGNJS(22, fsgnjn.s, 1, 1, 0) + TEST_FSGNJS(23, fsgnjn.s, 0, 1, 1) + + TEST_FSGNJS(30, fsgnjx.s, 0, 0, 0) + TEST_FSGNJS(31, fsgnjx.s, 1, 0, 1) + TEST_FSGNJS(32, fsgnjx.s, 1, 1, 0) + TEST_FSGNJS(33, fsgnjx.s, 0, 1, 1) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64uf/recoding.S b/tb/qumcu/isa/rv64uf/recoding.S new file mode 100644 index 0000000..802be66 --- /dev/null +++ b/tb/qumcu/isa/rv64uf/recoding.S @@ -0,0 +1,46 @@ +# See LICENSE for license details. + +#***************************************************************************** +# recoding.S +#----------------------------------------------------------------------------- +# +# Test corner cases of John Hauser's microarchitectural recoding scheme. +# There are twice as many recoded values as IEEE-754 values; some of these +# extras are redundant (e.g. Inf) and others are illegal (subnormals with +# too many bits set). +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64UF +RVTEST_CODE_BEGIN + + # Make sure infinities with different mantissas compare as equal. + flw f0, minf, a0 + flw f1, three, a0 + fmul.s f1, f1, f0 + TEST_CASE( 2, a0, 1, feq.s a0, f0, f1) + TEST_CASE( 3, a0, 1, fle.s a0, f0, f1) + TEST_CASE( 4, a0, 0, flt.s a0, f0, f1) + + # Likewise, but for zeroes. + fcvt.s.w f0, x0 + li a0, 1 + fcvt.s.w f1, a0 + fmul.s f1, f1, f0 + TEST_CASE(5, a0, 1, feq.s a0, f0, f1) + TEST_CASE(6, a0, 1, fle.s a0, f0, f1) + TEST_CASE(7, a0, 0, flt.s a0, f0, f1) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + +minf: .float -Inf +three: .float 3.0 + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64ui/Makefrag b/tb/qumcu/isa/rv64ui/Makefrag new file mode 100644 index 0000000..d90347c --- /dev/null +++ b/tb/qumcu/isa/rv64ui/Makefrag @@ -0,0 +1,26 @@ +#======================================================================= +# Makefrag for rv64ui tests +#----------------------------------------------------------------------- + +rv64ui_sc_tests = \ + add addi addiw addw \ + and andi \ + auipc \ + beq bge bgeu blt bltu bne \ + simple \ + fence_i \ + jal jalr \ + lb lbu lh lhu lw lwu ld \ + lui \ + ma_data \ + or ori \ + sb sh sw sd \ + sll slli slliw sllw \ + slt slti sltiu sltu \ + sra srai sraiw sraw \ + srl srli srliw srlw \ + sub subw \ + xor xori \ + +rv64ui_p_tests = $(addprefix rv64ui-p-, $(rv64ui_sc_tests)) +rv64ui_v_tests = $(addprefix rv64ui-v-, $(rv64ui_sc_tests)) diff --git a/tb/qumcu/isa/rv64ui/add.S b/tb/qumcu/isa/rv64ui/add.S new file mode 100644 index 0000000..0696428 --- /dev/null +++ b/tb/qumcu/isa/rv64ui/add.S @@ -0,0 +1,85 @@ +# See LICENSE for license details. + +#***************************************************************************** +# add.S +#----------------------------------------------------------------------------- +# +# Test add instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, add, 0x00000000, 0x00000000, 0x00000000 ); + TEST_RR_OP( 3, add, 0x00000002, 0x00000001, 0x00000001 ); + TEST_RR_OP( 4, add, 0x0000000a, 0x00000003, 0x00000007 ); + + TEST_RR_OP( 5, add, 0xffffffffffff8000, 0x0000000000000000, 0xffffffffffff8000 ); + TEST_RR_OP( 6, add, 0xffffffff80000000, 0xffffffff80000000, 0x00000000 ); + TEST_RR_OP( 7, add, 0xffffffff7fff8000, 0xffffffff80000000, 0xffffffffffff8000 ); + + TEST_RR_OP( 8, add, 0x0000000000007fff, 0x0000000000000000, 0x0000000000007fff ); + TEST_RR_OP( 9, add, 0x000000007fffffff, 0x000000007fffffff, 0x0000000000000000 ); + TEST_RR_OP( 10, add, 0x0000000080007ffe, 0x000000007fffffff, 0x0000000000007fff ); + + TEST_RR_OP( 11, add, 0xffffffff80007fff, 0xffffffff80000000, 0x0000000000007fff ); + TEST_RR_OP( 12, add, 0x000000007fff7fff, 0x000000007fffffff, 0xffffffffffff8000 ); + + TEST_RR_OP( 13, add, 0xffffffffffffffff, 0x0000000000000000, 0xffffffffffffffff ); + TEST_RR_OP( 14, add, 0x0000000000000000, 0xffffffffffffffff, 0x0000000000000001 ); + TEST_RR_OP( 15, add, 0xfffffffffffffffe, 0xffffffffffffffff, 0xffffffffffffffff ); + + TEST_RR_OP( 16, add, 0x0000000080000000, 0x0000000000000001, 0x000000007fffffff ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 17, add, 24, 13, 11 ); + TEST_RR_SRC2_EQ_DEST( 18, add, 25, 14, 11 ); + TEST_RR_SRC12_EQ_DEST( 19, add, 26, 13 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 20, 0, add, 24, 13, 11 ); + TEST_RR_DEST_BYPASS( 21, 1, add, 25, 14, 11 ); + TEST_RR_DEST_BYPASS( 22, 2, add, 26, 15, 11 ); + + TEST_RR_SRC12_BYPASS( 23, 0, 0, add, 24, 13, 11 ); + TEST_RR_SRC12_BYPASS( 24, 0, 1, add, 25, 14, 11 ); + TEST_RR_SRC12_BYPASS( 25, 0, 2, add, 26, 15, 11 ); + TEST_RR_SRC12_BYPASS( 26, 1, 0, add, 24, 13, 11 ); + TEST_RR_SRC12_BYPASS( 27, 1, 1, add, 25, 14, 11 ); + TEST_RR_SRC12_BYPASS( 28, 2, 0, add, 26, 15, 11 ); + + TEST_RR_SRC21_BYPASS( 29, 0, 0, add, 24, 13, 11 ); + TEST_RR_SRC21_BYPASS( 30, 0, 1, add, 25, 14, 11 ); + TEST_RR_SRC21_BYPASS( 31, 0, 2, add, 26, 15, 11 ); + TEST_RR_SRC21_BYPASS( 32, 1, 0, add, 24, 13, 11 ); + TEST_RR_SRC21_BYPASS( 33, 1, 1, add, 25, 14, 11 ); + TEST_RR_SRC21_BYPASS( 34, 2, 0, add, 26, 15, 11 ); + + TEST_RR_ZEROSRC1( 35, add, 15, 15 ); + TEST_RR_ZEROSRC2( 36, add, 32, 32 ); + TEST_RR_ZEROSRC12( 37, add, 0 ); + TEST_RR_ZERODEST( 38, add, 16, 30 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64ui/addi.S b/tb/qumcu/isa/rv64ui/addi.S new file mode 100644 index 0000000..e6b67ca --- /dev/null +++ b/tb/qumcu/isa/rv64ui/addi.S @@ -0,0 +1,71 @@ +# See LICENSE for license details. + +#***************************************************************************** +# addi.S +#----------------------------------------------------------------------------- +# +# Test addi instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_IMM_OP( 2, addi, 0x00000000, 0x00000000, 0x000 ); + TEST_IMM_OP( 3, addi, 0x00000002, 0x00000001, 0x001 ); + TEST_IMM_OP( 4, addi, 0x0000000a, 0x00000003, 0x007 ); + + TEST_IMM_OP( 5, addi, 0xfffffffffffff800, 0x0000000000000000, 0x800 ); + TEST_IMM_OP( 6, addi, 0xffffffff80000000, 0xffffffff80000000, 0x000 ); + TEST_IMM_OP( 7, addi, 0xffffffff7ffff800, 0xffffffff80000000, 0x800 ); + + TEST_IMM_OP( 8, addi, 0x00000000000007ff, 0x00000000, 0x7ff ); + TEST_IMM_OP( 9, addi, 0x000000007fffffff, 0x7fffffff, 0x000 ); + TEST_IMM_OP( 10, addi, 0x00000000800007fe, 0x7fffffff, 0x7ff ); + + TEST_IMM_OP( 11, addi, 0xffffffff800007ff, 0xffffffff80000000, 0x7ff ); + TEST_IMM_OP( 12, addi, 0x000000007ffff7ff, 0x000000007fffffff, 0x800 ); + + TEST_IMM_OP( 13, addi, 0xffffffffffffffff, 0x0000000000000000, 0xfff ); + TEST_IMM_OP( 14, addi, 0x0000000000000000, 0xffffffffffffffff, 0x001 ); + TEST_IMM_OP( 15, addi, 0xfffffffffffffffe, 0xffffffffffffffff, 0xfff ); + + TEST_IMM_OP( 16, addi, 0x0000000080000000, 0x7fffffff, 0x001 ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_IMM_SRC1_EQ_DEST( 17, addi, 24, 13, 11 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_IMM_DEST_BYPASS( 18, 0, addi, 24, 13, 11 ); + TEST_IMM_DEST_BYPASS( 19, 1, addi, 23, 13, 10 ); + TEST_IMM_DEST_BYPASS( 20, 2, addi, 22, 13, 9 ); + + TEST_IMM_SRC1_BYPASS( 21, 0, addi, 24, 13, 11 ); + TEST_IMM_SRC1_BYPASS( 22, 1, addi, 23, 13, 10 ); + TEST_IMM_SRC1_BYPASS( 23, 2, addi, 22, 13, 9 ); + + TEST_IMM_ZEROSRC1( 24, addi, 32, 32 ); + TEST_IMM_ZERODEST( 25, addi, 33, 50 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64ui/addiw.S b/tb/qumcu/isa/rv64ui/addiw.S new file mode 100644 index 0000000..c0f9a61 --- /dev/null +++ b/tb/qumcu/isa/rv64ui/addiw.S @@ -0,0 +1,71 @@ +# See LICENSE for license details. + +#***************************************************************************** +# addiw.S +#----------------------------------------------------------------------------- +# +# Test addiw instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_IMM_OP( 2, addiw, 0x00000000, 0x00000000, 0x000 ); + TEST_IMM_OP( 3, addiw, 0x00000002, 0x00000001, 0x001 ); + TEST_IMM_OP( 4, addiw, 0x0000000a, 0x00000003, 0x007 ); + + TEST_IMM_OP( 5, addiw, 0xfffffffffffff800, 0x0000000000000000, 0x800 ); + TEST_IMM_OP( 6, addiw, 0xffffffff80000000, 0xffffffff80000000, 0x000 ); + TEST_IMM_OP( 7, addiw, 0x000000007ffff800, 0xffffffff80000000, 0x800 ); + + TEST_IMM_OP( 8, addiw, 0x00000000000007ff, 0x00000000, 0x7ff ); + TEST_IMM_OP( 9, addiw, 0x000000007fffffff, 0x7fffffff, 0x000 ); + TEST_IMM_OP( 10, addiw, 0xffffffff800007fe, 0x7fffffff, 0x7ff ); + + TEST_IMM_OP( 11, addiw, 0xffffffff800007ff, 0xffffffff80000000, 0x7ff ); + TEST_IMM_OP( 12, addiw, 0x000000007ffff7ff, 0x000000007fffffff, 0x800 ); + + TEST_IMM_OP( 13, addiw, 0xffffffffffffffff, 0x0000000000000000, 0xfff ); + TEST_IMM_OP( 14, addiw, 0x0000000000000000, 0xffffffffffffffff, 0x001 ); + TEST_IMM_OP( 15, addiw, 0xfffffffffffffffe, 0xffffffffffffffff, 0xfff ); + + TEST_IMM_OP( 16, addiw, 0xffffffff80000000, 0x7fffffff, 0x001 ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_IMM_SRC1_EQ_DEST( 17, addiw, 24, 13, 11 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_IMM_DEST_BYPASS( 18, 0, addiw, 24, 13, 11 ); + TEST_IMM_DEST_BYPASS( 19, 1, addiw, 23, 13, 10 ); + TEST_IMM_DEST_BYPASS( 20, 2, addiw, 22, 13, 9 ); + + TEST_IMM_SRC1_BYPASS( 21, 0, addiw, 24, 13, 11 ); + TEST_IMM_SRC1_BYPASS( 22, 1, addiw, 23, 13, 10 ); + TEST_IMM_SRC1_BYPASS( 23, 2, addiw, 22, 13, 9 ); + + TEST_IMM_ZEROSRC1( 24, addiw, 32, 32 ); + TEST_IMM_ZERODEST( 25, addiw, 33, 50 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64ui/addw.S b/tb/qumcu/isa/rv64ui/addw.S new file mode 100644 index 0000000..ad7fe0b --- /dev/null +++ b/tb/qumcu/isa/rv64ui/addw.S @@ -0,0 +1,85 @@ +# See LICENSE for license details. + +#***************************************************************************** +# addw.S +#----------------------------------------------------------------------------- +# +# Test addw instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, addw, 0x00000000, 0x00000000, 0x00000000 ); + TEST_RR_OP( 3, addw, 0x00000002, 0x00000001, 0x00000001 ); + TEST_RR_OP( 4, addw, 0x0000000a, 0x00000003, 0x00000007 ); + + TEST_RR_OP( 5, addw, 0xffffffffffff8000, 0x0000000000000000, 0xffffffffffff8000 ); + TEST_RR_OP( 6, addw, 0xffffffff80000000, 0xffffffff80000000, 0x00000000 ); + TEST_RR_OP( 7, addw, 0x000000007fff8000, 0xffffffff80000000, 0xffffffffffff8000 ); + + TEST_RR_OP( 8, addw, 0x0000000000007fff, 0x0000000000000000, 0x0000000000007fff ); + TEST_RR_OP( 9, addw, 0x000000007fffffff, 0x000000007fffffff, 0x0000000000000000 ); + TEST_RR_OP( 10, addw, 0xffffffff80007ffe, 0x000000007fffffff, 0x0000000000007fff ); + + TEST_RR_OP( 11, addw, 0xffffffff80007fff, 0xffffffff80000000, 0x0000000000007fff ); + TEST_RR_OP( 12, addw, 0x000000007fff7fff, 0x000000007fffffff, 0xffffffffffff8000 ); + + TEST_RR_OP( 13, addw, 0xffffffffffffffff, 0x0000000000000000, 0xffffffffffffffff ); + TEST_RR_OP( 14, addw, 0x0000000000000000, 0xffffffffffffffff, 0x0000000000000001 ); + TEST_RR_OP( 15, addw, 0xfffffffffffffffe, 0xffffffffffffffff, 0xffffffffffffffff ); + + TEST_RR_OP( 16, addw, 0xffffffff80000000, 0x0000000000000001, 0x000000007fffffff ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 17, addw, 24, 13, 11 ); + TEST_RR_SRC2_EQ_DEST( 18, addw, 25, 14, 11 ); + TEST_RR_SRC12_EQ_DEST( 19, addw, 26, 13 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 20, 0, addw, 24, 13, 11 ); + TEST_RR_DEST_BYPASS( 21, 1, addw, 25, 14, 11 ); + TEST_RR_DEST_BYPASS( 22, 2, addw, 26, 15, 11 ); + + TEST_RR_SRC12_BYPASS( 23, 0, 0, addw, 24, 13, 11 ); + TEST_RR_SRC12_BYPASS( 24, 0, 1, addw, 25, 14, 11 ); + TEST_RR_SRC12_BYPASS( 25, 0, 2, addw, 26, 15, 11 ); + TEST_RR_SRC12_BYPASS( 26, 1, 0, addw, 24, 13, 11 ); + TEST_RR_SRC12_BYPASS( 27, 1, 1, addw, 25, 14, 11 ); + TEST_RR_SRC12_BYPASS( 28, 2, 0, addw, 26, 15, 11 ); + + TEST_RR_SRC21_BYPASS( 29, 0, 0, addw, 24, 13, 11 ); + TEST_RR_SRC21_BYPASS( 30, 0, 1, addw, 25, 14, 11 ); + TEST_RR_SRC21_BYPASS( 31, 0, 2, addw, 26, 15, 11 ); + TEST_RR_SRC21_BYPASS( 32, 1, 0, addw, 24, 13, 11 ); + TEST_RR_SRC21_BYPASS( 33, 1, 1, addw, 25, 14, 11 ); + TEST_RR_SRC21_BYPASS( 34, 2, 0, addw, 26, 15, 11 ); + + TEST_RR_ZEROSRC1( 35, addw, 15, 15 ); + TEST_RR_ZEROSRC2( 36, addw, 32, 32 ); + TEST_RR_ZEROSRC12( 37, addw, 0 ); + TEST_RR_ZERODEST( 38, addw, 16, 30 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64ui/and.S b/tb/qumcu/isa/rv64ui/and.S new file mode 100644 index 0000000..3f63790 --- /dev/null +++ b/tb/qumcu/isa/rv64ui/and.S @@ -0,0 +1,69 @@ +# See LICENSE for license details. + +#***************************************************************************** +# and.S +#----------------------------------------------------------------------------- +# +# Test and instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Logical tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, and, 0x0f000f00, 0xff00ff00, 0x0f0f0f0f ); + TEST_RR_OP( 3, and, 0x00f000f0, 0x0ff00ff0, 0xf0f0f0f0 ); + TEST_RR_OP( 4, and, 0x000f000f, 0x00ff00ff, 0x0f0f0f0f ); + TEST_RR_OP( 5, and, 0xf000f000, 0xf00ff00f, 0xf0f0f0f0 ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 6, and, 0x0f000f00, 0xff00ff00, 0x0f0f0f0f ); + TEST_RR_SRC2_EQ_DEST( 7, and, 0x00f000f0, 0x0ff00ff0, 0xf0f0f0f0 ); + TEST_RR_SRC12_EQ_DEST( 8, and, 0xff00ff00, 0xff00ff00 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 9, 0, and, 0x0f000f00, 0xff00ff00, 0x0f0f0f0f ); + TEST_RR_DEST_BYPASS( 10, 1, and, 0x00f000f0, 0x0ff00ff0, 0xf0f0f0f0 ); + TEST_RR_DEST_BYPASS( 11, 2, and, 0x000f000f, 0x00ff00ff, 0x0f0f0f0f ); + + TEST_RR_SRC12_BYPASS( 12, 0, 0, and, 0x0f000f00, 0xff00ff00, 0x0f0f0f0f ); + TEST_RR_SRC12_BYPASS( 13, 0, 1, and, 0x00f000f0, 0x0ff00ff0, 0xf0f0f0f0 ); + TEST_RR_SRC12_BYPASS( 14, 0, 2, and, 0x000f000f, 0x00ff00ff, 0x0f0f0f0f ); + TEST_RR_SRC12_BYPASS( 15, 1, 0, and, 0x0f000f00, 0xff00ff00, 0x0f0f0f0f ); + TEST_RR_SRC12_BYPASS( 16, 1, 1, and, 0x00f000f0, 0x0ff00ff0, 0xf0f0f0f0 ); + TEST_RR_SRC12_BYPASS( 17, 2, 0, and, 0x000f000f, 0x00ff00ff, 0x0f0f0f0f ); + + TEST_RR_SRC21_BYPASS( 18, 0, 0, and, 0x0f000f00, 0xff00ff00, 0x0f0f0f0f ); + TEST_RR_SRC21_BYPASS( 19, 0, 1, and, 0x00f000f0, 0x0ff00ff0, 0xf0f0f0f0 ); + TEST_RR_SRC21_BYPASS( 20, 0, 2, and, 0x000f000f, 0x00ff00ff, 0x0f0f0f0f ); + TEST_RR_SRC21_BYPASS( 21, 1, 0, and, 0x0f000f00, 0xff00ff00, 0x0f0f0f0f ); + TEST_RR_SRC21_BYPASS( 22, 1, 1, and, 0x00f000f0, 0x0ff00ff0, 0xf0f0f0f0 ); + TEST_RR_SRC21_BYPASS( 23, 2, 0, and, 0x000f000f, 0x00ff00ff, 0x0f0f0f0f ); + + TEST_RR_ZEROSRC1( 24, and, 0, 0xff00ff00 ); + TEST_RR_ZEROSRC2( 25, and, 0, 0x00ff00ff ); + TEST_RR_ZEROSRC12( 26, and, 0 ); + TEST_RR_ZERODEST( 27, and, 0x11111111, 0x22222222 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64ui/andi.S b/tb/qumcu/isa/rv64ui/andi.S new file mode 100644 index 0000000..913af9d --- /dev/null +++ b/tb/qumcu/isa/rv64ui/andi.S @@ -0,0 +1,55 @@ +# See LICENSE for license details. + +#***************************************************************************** +# andi.S +#----------------------------------------------------------------------------- +# +# Test andi instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Logical tests + #------------------------------------------------------------- + + TEST_IMM_OP( 2, andi, 0xff00ff00, 0xff00ff00, 0xf0f ); + TEST_IMM_OP( 3, andi, 0x000000f0, 0x0ff00ff0, 0x0f0 ); + TEST_IMM_OP( 4, andi, 0x0000000f, 0x00ff00ff, 0x70f ); + TEST_IMM_OP( 5, andi, 0x00000000, 0xf00ff00f, 0x0f0 ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_IMM_SRC1_EQ_DEST( 6, andi, 0x00000000, 0xff00ff00, 0x0f0 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_IMM_DEST_BYPASS( 7, 0, andi, 0x00000700, 0x0ff00ff0, 0x70f ); + TEST_IMM_DEST_BYPASS( 8, 1, andi, 0x000000f0, 0x00ff00ff, 0x0f0 ); + TEST_IMM_DEST_BYPASS( 9, 2, andi, 0xf00ff00f, 0xf00ff00f, 0xf0f ); + + TEST_IMM_SRC1_BYPASS( 10, 0, andi, 0x00000700, 0x0ff00ff0, 0x70f ); + TEST_IMM_SRC1_BYPASS( 11, 1, andi, 0x000000f0, 0x00ff00ff, 0x0f0 ); + TEST_IMM_SRC1_BYPASS( 12, 2, andi, 0x0000000f, 0xf00ff00f, 0x70f ); + + TEST_IMM_ZEROSRC1( 13, andi, 0, 0x0f0 ); + TEST_IMM_ZERODEST( 14, andi, 0x00ff00ff, 0x70f ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64ui/auipc.S b/tb/qumcu/isa/rv64ui/auipc.S new file mode 100644 index 0000000..6fe5962 --- /dev/null +++ b/tb/qumcu/isa/rv64ui/auipc.S @@ -0,0 +1,39 @@ +# See LICENSE for license details. + +#***************************************************************************** +# auipc.S +#----------------------------------------------------------------------------- +# +# Test auipc instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a0, 10000, \ + .align 3; \ + lla a0, 1f + 10000; \ + jal a1, 1f; \ + 1: sub a0, a0, a1; \ + ) + + TEST_CASE(3, a0, -10000, \ + .align 3; \ + lla a0, 1f - 10000; \ + jal a1, 1f; \ + 1: sub a0, a0, a1; \ + ) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64ui/beq.S b/tb/qumcu/isa/rv64ui/beq.S new file mode 100644 index 0000000..436db8c --- /dev/null +++ b/tb/qumcu/isa/rv64ui/beq.S @@ -0,0 +1,73 @@ +# See LICENSE for license details. + +#***************************************************************************** +# beq.S +#----------------------------------------------------------------------------- +# +# Test beq instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Branch tests + #------------------------------------------------------------- + + # Each test checks both forward and backward branches + + TEST_BR2_OP_TAKEN( 2, beq, 0, 0 ); + TEST_BR2_OP_TAKEN( 3, beq, 1, 1 ); + TEST_BR2_OP_TAKEN( 4, beq, -1, -1 ); + + TEST_BR2_OP_NOTTAKEN( 5, beq, 0, 1 ); + TEST_BR2_OP_NOTTAKEN( 6, beq, 1, 0 ); + TEST_BR2_OP_NOTTAKEN( 7, beq, -1, 1 ); + TEST_BR2_OP_NOTTAKEN( 8, beq, 1, -1 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_BR2_SRC12_BYPASS( 9, 0, 0, beq, 0, -1 ); + TEST_BR2_SRC12_BYPASS( 10, 0, 1, beq, 0, -1 ); + TEST_BR2_SRC12_BYPASS( 11, 0, 2, beq, 0, -1 ); + TEST_BR2_SRC12_BYPASS( 12, 1, 0, beq, 0, -1 ); + TEST_BR2_SRC12_BYPASS( 13, 1, 1, beq, 0, -1 ); + TEST_BR2_SRC12_BYPASS( 14, 2, 0, beq, 0, -1 ); + + TEST_BR2_SRC12_BYPASS( 15, 0, 0, beq, 0, -1 ); + TEST_BR2_SRC12_BYPASS( 16, 0, 1, beq, 0, -1 ); + TEST_BR2_SRC12_BYPASS( 17, 0, 2, beq, 0, -1 ); + TEST_BR2_SRC12_BYPASS( 18, 1, 0, beq, 0, -1 ); + TEST_BR2_SRC12_BYPASS( 19, 1, 1, beq, 0, -1 ); + TEST_BR2_SRC12_BYPASS( 20, 2, 0, beq, 0, -1 ); + + #------------------------------------------------------------- + # Test delay slot instructions not executed nor bypassed + #------------------------------------------------------------- + + TEST_CASE( 21, x1, 3, \ + li x1, 1; \ + beq x0, x0, 1f; \ + addi x1, x1, 1; \ + addi x1, x1, 1; \ + addi x1, x1, 1; \ + addi x1, x1, 1; \ +1: addi x1, x1, 1; \ + addi x1, x1, 1; \ + ) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64ui/bge.S b/tb/qumcu/isa/rv64ui/bge.S new file mode 100644 index 0000000..04aebbc --- /dev/null +++ b/tb/qumcu/isa/rv64ui/bge.S @@ -0,0 +1,76 @@ +# See LICENSE for license details. + +#***************************************************************************** +# bge.S +#----------------------------------------------------------------------------- +# +# Test bge instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Branch tests + #------------------------------------------------------------- + + # Each test checks both forward and backward branches + + TEST_BR2_OP_TAKEN( 2, bge, 0, 0 ); + TEST_BR2_OP_TAKEN( 3, bge, 1, 1 ); + TEST_BR2_OP_TAKEN( 4, bge, -1, -1 ); + TEST_BR2_OP_TAKEN( 5, bge, 1, 0 ); + TEST_BR2_OP_TAKEN( 6, bge, 1, -1 ); + TEST_BR2_OP_TAKEN( 7, bge, -1, -2 ); + + TEST_BR2_OP_NOTTAKEN( 8, bge, 0, 1 ); + TEST_BR2_OP_NOTTAKEN( 9, bge, -1, 1 ); + TEST_BR2_OP_NOTTAKEN( 10, bge, -2, -1 ); + TEST_BR2_OP_NOTTAKEN( 11, bge, -2, 1 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_BR2_SRC12_BYPASS( 12, 0, 0, bge, -1, 0 ); + TEST_BR2_SRC12_BYPASS( 13, 0, 1, bge, -1, 0 ); + TEST_BR2_SRC12_BYPASS( 14, 0, 2, bge, -1, 0 ); + TEST_BR2_SRC12_BYPASS( 15, 1, 0, bge, -1, 0 ); + TEST_BR2_SRC12_BYPASS( 16, 1, 1, bge, -1, 0 ); + TEST_BR2_SRC12_BYPASS( 17, 2, 0, bge, -1, 0 ); + + TEST_BR2_SRC12_BYPASS( 18, 0, 0, bge, -1, 0 ); + TEST_BR2_SRC12_BYPASS( 19, 0, 1, bge, -1, 0 ); + TEST_BR2_SRC12_BYPASS( 20, 0, 2, bge, -1, 0 ); + TEST_BR2_SRC12_BYPASS( 21, 1, 0, bge, -1, 0 ); + TEST_BR2_SRC12_BYPASS( 22, 1, 1, bge, -1, 0 ); + TEST_BR2_SRC12_BYPASS( 23, 2, 0, bge, -1, 0 ); + + #------------------------------------------------------------- + # Test delay slot instructions not executed nor bypassed + #------------------------------------------------------------- + + TEST_CASE( 24, x1, 3, \ + li x1, 1; \ + bge x1, x0, 1f; \ + addi x1, x1, 1; \ + addi x1, x1, 1; \ + addi x1, x1, 1; \ + addi x1, x1, 1; \ +1: addi x1, x1, 1; \ + addi x1, x1, 1; \ + ) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64ui/bgeu.S b/tb/qumcu/isa/rv64ui/bgeu.S new file mode 100644 index 0000000..36b6b3a --- /dev/null +++ b/tb/qumcu/isa/rv64ui/bgeu.S @@ -0,0 +1,76 @@ +# See LICENSE for license details. + +#***************************************************************************** +# bgeu.S +#----------------------------------------------------------------------------- +# +# Test bgeu instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Branch tests + #------------------------------------------------------------- + + # Each test checks both forward and backward branches + + TEST_BR2_OP_TAKEN( 2, bgeu, 0x00000000, 0x00000000 ); + TEST_BR2_OP_TAKEN( 3, bgeu, 0x00000001, 0x00000001 ); + TEST_BR2_OP_TAKEN( 4, bgeu, 0xffffffff, 0xffffffff ); + TEST_BR2_OP_TAKEN( 5, bgeu, 0x00000001, 0x00000000 ); + TEST_BR2_OP_TAKEN( 6, bgeu, 0xffffffff, 0xfffffffe ); + TEST_BR2_OP_TAKEN( 7, bgeu, 0xffffffff, 0x00000000 ); + + TEST_BR2_OP_NOTTAKEN( 8, bgeu, 0x00000000, 0x00000001 ); + TEST_BR2_OP_NOTTAKEN( 9, bgeu, 0xfffffffe, 0xffffffff ); + TEST_BR2_OP_NOTTAKEN( 10, bgeu, 0x00000000, 0xffffffff ); + TEST_BR2_OP_NOTTAKEN( 11, bgeu, 0x7fffffff, 0x80000000 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_BR2_SRC12_BYPASS( 12, 0, 0, bgeu, 0xefffffff, 0xf0000000 ); + TEST_BR2_SRC12_BYPASS( 13, 0, 1, bgeu, 0xefffffff, 0xf0000000 ); + TEST_BR2_SRC12_BYPASS( 14, 0, 2, bgeu, 0xefffffff, 0xf0000000 ); + TEST_BR2_SRC12_BYPASS( 15, 1, 0, bgeu, 0xefffffff, 0xf0000000 ); + TEST_BR2_SRC12_BYPASS( 16, 1, 1, bgeu, 0xefffffff, 0xf0000000 ); + TEST_BR2_SRC12_BYPASS( 17, 2, 0, bgeu, 0xefffffff, 0xf0000000 ); + + TEST_BR2_SRC12_BYPASS( 18, 0, 0, bgeu, 0xefffffff, 0xf0000000 ); + TEST_BR2_SRC12_BYPASS( 19, 0, 1, bgeu, 0xefffffff, 0xf0000000 ); + TEST_BR2_SRC12_BYPASS( 20, 0, 2, bgeu, 0xefffffff, 0xf0000000 ); + TEST_BR2_SRC12_BYPASS( 21, 1, 0, bgeu, 0xefffffff, 0xf0000000 ); + TEST_BR2_SRC12_BYPASS( 22, 1, 1, bgeu, 0xefffffff, 0xf0000000 ); + TEST_BR2_SRC12_BYPASS( 23, 2, 0, bgeu, 0xefffffff, 0xf0000000 ); + + #------------------------------------------------------------- + # Test delay slot instructions not executed nor bypassed + #------------------------------------------------------------- + + TEST_CASE( 24, x1, 3, \ + li x1, 1; \ + bgeu x1, x0, 1f; \ + addi x1, x1, 1; \ + addi x1, x1, 1; \ + addi x1, x1, 1; \ + addi x1, x1, 1; \ +1: addi x1, x1, 1; \ + addi x1, x1, 1; \ + ) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64ui/blt.S b/tb/qumcu/isa/rv64ui/blt.S new file mode 100644 index 0000000..1c0ca69 --- /dev/null +++ b/tb/qumcu/isa/rv64ui/blt.S @@ -0,0 +1,73 @@ +# See LICENSE for license details. + +#***************************************************************************** +# blt.S +#----------------------------------------------------------------------------- +# +# Test blt instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Branch tests + #------------------------------------------------------------- + + # Each test checks both forward and backward branches + + TEST_BR2_OP_TAKEN( 2, blt, 0, 1 ); + TEST_BR2_OP_TAKEN( 3, blt, -1, 1 ); + TEST_BR2_OP_TAKEN( 4, blt, -2, -1 ); + + TEST_BR2_OP_NOTTAKEN( 5, blt, 1, 0 ); + TEST_BR2_OP_NOTTAKEN( 6, blt, 1, -1 ); + TEST_BR2_OP_NOTTAKEN( 7, blt, -1, -2 ); + TEST_BR2_OP_NOTTAKEN( 8, blt, 1, -2 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_BR2_SRC12_BYPASS( 9, 0, 0, blt, 0, -1 ); + TEST_BR2_SRC12_BYPASS( 10, 0, 1, blt, 0, -1 ); + TEST_BR2_SRC12_BYPASS( 11, 0, 2, blt, 0, -1 ); + TEST_BR2_SRC12_BYPASS( 12, 1, 0, blt, 0, -1 ); + TEST_BR2_SRC12_BYPASS( 13, 1, 1, blt, 0, -1 ); + TEST_BR2_SRC12_BYPASS( 14, 2, 0, blt, 0, -1 ); + + TEST_BR2_SRC12_BYPASS( 15, 0, 0, blt, 0, -1 ); + TEST_BR2_SRC12_BYPASS( 16, 0, 1, blt, 0, -1 ); + TEST_BR2_SRC12_BYPASS( 17, 0, 2, blt, 0, -1 ); + TEST_BR2_SRC12_BYPASS( 18, 1, 0, blt, 0, -1 ); + TEST_BR2_SRC12_BYPASS( 19, 1, 1, blt, 0, -1 ); + TEST_BR2_SRC12_BYPASS( 20, 2, 0, blt, 0, -1 ); + + #------------------------------------------------------------- + # Test delay slot instructions not executed nor bypassed + #------------------------------------------------------------- + + TEST_CASE( 21, x1, 3, \ + li x1, 1; \ + blt x0, x1, 1f; \ + addi x1, x1, 1; \ + addi x1, x1, 1; \ + addi x1, x1, 1; \ + addi x1, x1, 1; \ +1: addi x1, x1, 1; \ + addi x1, x1, 1; \ + ) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64ui/bltu.S b/tb/qumcu/isa/rv64ui/bltu.S new file mode 100644 index 0000000..4e880d6 --- /dev/null +++ b/tb/qumcu/isa/rv64ui/bltu.S @@ -0,0 +1,73 @@ +# See LICENSE for license details. + +#***************************************************************************** +# bltu.S +#----------------------------------------------------------------------------- +# +# Test bltu instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Branch tests + #------------------------------------------------------------- + + # Each test checks both forward and backward branches + + TEST_BR2_OP_TAKEN( 2, bltu, 0x00000000, 0x00000001 ); + TEST_BR2_OP_TAKEN( 3, bltu, 0xfffffffe, 0xffffffff ); + TEST_BR2_OP_TAKEN( 4, bltu, 0x00000000, 0xffffffff ); + + TEST_BR2_OP_NOTTAKEN( 5, bltu, 0x00000001, 0x00000000 ); + TEST_BR2_OP_NOTTAKEN( 6, bltu, 0xffffffff, 0xfffffffe ); + TEST_BR2_OP_NOTTAKEN( 7, bltu, 0xffffffff, 0x00000000 ); + TEST_BR2_OP_NOTTAKEN( 8, bltu, 0x80000000, 0x7fffffff ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_BR2_SRC12_BYPASS( 9, 0, 0, bltu, 0xf0000000, 0xefffffff ); + TEST_BR2_SRC12_BYPASS( 10, 0, 1, bltu, 0xf0000000, 0xefffffff ); + TEST_BR2_SRC12_BYPASS( 11, 0, 2, bltu, 0xf0000000, 0xefffffff ); + TEST_BR2_SRC12_BYPASS( 12, 1, 0, bltu, 0xf0000000, 0xefffffff ); + TEST_BR2_SRC12_BYPASS( 13, 1, 1, bltu, 0xf0000000, 0xefffffff ); + TEST_BR2_SRC12_BYPASS( 14, 2, 0, bltu, 0xf0000000, 0xefffffff ); + + TEST_BR2_SRC12_BYPASS( 15, 0, 0, bltu, 0xf0000000, 0xefffffff ); + TEST_BR2_SRC12_BYPASS( 16, 0, 1, bltu, 0xf0000000, 0xefffffff ); + TEST_BR2_SRC12_BYPASS( 17, 0, 2, bltu, 0xf0000000, 0xefffffff ); + TEST_BR2_SRC12_BYPASS( 18, 1, 0, bltu, 0xf0000000, 0xefffffff ); + TEST_BR2_SRC12_BYPASS( 19, 1, 1, bltu, 0xf0000000, 0xefffffff ); + TEST_BR2_SRC12_BYPASS( 20, 2, 0, bltu, 0xf0000000, 0xefffffff ); + + #------------------------------------------------------------- + # Test delay slot instructions not executed nor bypassed + #------------------------------------------------------------- + + TEST_CASE( 21, x1, 3, \ + li x1, 1; \ + bltu x0, x1, 1f; \ + addi x1, x1, 1; \ + addi x1, x1, 1; \ + addi x1, x1, 1; \ + addi x1, x1, 1; \ +1: addi x1, x1, 1; \ + addi x1, x1, 1; \ + ) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64ui/bne.S b/tb/qumcu/isa/rv64ui/bne.S new file mode 100644 index 0000000..3ca4e6c --- /dev/null +++ b/tb/qumcu/isa/rv64ui/bne.S @@ -0,0 +1,73 @@ +# See LICENSE for license details. + +#***************************************************************************** +# bne.S +#----------------------------------------------------------------------------- +# +# Test bne instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Branch tests + #------------------------------------------------------------- + + # Each test checks both forward and backward branches + + TEST_BR2_OP_TAKEN( 2, bne, 0, 1 ); + TEST_BR2_OP_TAKEN( 3, bne, 1, 0 ); + TEST_BR2_OP_TAKEN( 4, bne, -1, 1 ); + TEST_BR2_OP_TAKEN( 5, bne, 1, -1 ); + + TEST_BR2_OP_NOTTAKEN( 6, bne, 0, 0 ); + TEST_BR2_OP_NOTTAKEN( 7, bne, 1, 1 ); + TEST_BR2_OP_NOTTAKEN( 8, bne, -1, -1 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_BR2_SRC12_BYPASS( 9, 0, 0, bne, 0, 0 ); + TEST_BR2_SRC12_BYPASS( 10, 0, 1, bne, 0, 0 ); + TEST_BR2_SRC12_BYPASS( 11, 0, 2, bne, 0, 0 ); + TEST_BR2_SRC12_BYPASS( 12, 1, 0, bne, 0, 0 ); + TEST_BR2_SRC12_BYPASS( 13, 1, 1, bne, 0, 0 ); + TEST_BR2_SRC12_BYPASS( 14, 2, 0, bne, 0, 0 ); + + TEST_BR2_SRC12_BYPASS( 15, 0, 0, bne, 0, 0 ); + TEST_BR2_SRC12_BYPASS( 16, 0, 1, bne, 0, 0 ); + TEST_BR2_SRC12_BYPASS( 17, 0, 2, bne, 0, 0 ); + TEST_BR2_SRC12_BYPASS( 18, 1, 0, bne, 0, 0 ); + TEST_BR2_SRC12_BYPASS( 19, 1, 1, bne, 0, 0 ); + TEST_BR2_SRC12_BYPASS( 20, 2, 0, bne, 0, 0 ); + + #------------------------------------------------------------- + # Test delay slot instructions not executed nor bypassed + #------------------------------------------------------------- + + TEST_CASE( 21, x1, 3, \ + li x1, 1; \ + bne x1, x0, 1f; \ + addi x1, x1, 1; \ + addi x1, x1, 1; \ + addi x1, x1, 1; \ + addi x1, x1, 1; \ +1: addi x1, x1, 1; \ + addi x1, x1, 1; \ + ) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64ui/fence_i.S b/tb/qumcu/isa/rv64ui/fence_i.S new file mode 100644 index 0000000..e6a6912 --- /dev/null +++ b/tb/qumcu/isa/rv64ui/fence_i.S @@ -0,0 +1,62 @@ +# See LICENSE for license details. + +#***************************************************************************** +# fence_i.S +#----------------------------------------------------------------------------- +# +# Test self-modifying code and the fence.i instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + +li a3, 111 +lh a0, insn +lh a1, insn+2 + +# test I$ hit +.align 6 +sh a0, 2f, t0 +sh a1, 2f+2, t0 +fence.i + +la a5, 2f +jalr t1, a5, 0 +TEST_CASE( 2, a3, 444, nop ) + +# test prefetcher hit +li a4, 100 +1: addi a4, a4, -1 +bnez a4, 1b + +sh a0, 3f, t0 +sh a1, 3f+2, t0 +fence.i + +.align 6 +la a5, 3f +jalr t1, a5, 0 +TEST_CASE( 3, a3, 777, nop ) + +TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +insn: + addi a3, a3, 333 + +2: addi a3, a3, 222 +jalr a5, t1, 0 + +3: addi a3, a3, 555 +jalr a5, t1, 0 + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64ui/jal.S b/tb/qumcu/isa/rv64ui/jal.S new file mode 100644 index 0000000..00c65d8 --- /dev/null +++ b/tb/qumcu/isa/rv64ui/jal.S @@ -0,0 +1,59 @@ +# See LICENSE for license details. + +#***************************************************************************** +# jal.S +#----------------------------------------------------------------------------- +# +# Test jal instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Test 2: Basic test + #------------------------------------------------------------- + +test_2: + li TESTNUM, 2 + li ra, 0 + + jal x4, target_2 +linkaddr_2: + nop + nop + + j fail + +target_2: + la x2, linkaddr_2 + bne x2, x4, fail + + #------------------------------------------------------------- + # Test delay slot instructions not executed nor bypassed + #------------------------------------------------------------- + + TEST_CASE( 3, ra, 3, \ + li ra, 1; \ + jal x0, 1f; \ + addi ra, ra, 1; \ + addi ra, ra, 1; \ + addi ra, ra, 1; \ + addi ra, ra, 1; \ +1: addi ra, ra, 1; \ + addi ra, ra, 1; \ + ) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64ui/jalr.S b/tb/qumcu/isa/rv64ui/jalr.S new file mode 100644 index 0000000..c922b11 --- /dev/null +++ b/tb/qumcu/isa/rv64ui/jalr.S @@ -0,0 +1,86 @@ +# See LICENSE for license details. + +#***************************************************************************** +# jalr.S +#----------------------------------------------------------------------------- +# +# Test jalr instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Test 2: Basic test + #------------------------------------------------------------- + +test_2: + li TESTNUM, 2 + li t0, 0 + la t1, target_2 + + jalr t0, t1, 0 +linkaddr_2: + j fail + +target_2: + la t1, linkaddr_2 + bne t0, t1, fail + + #------------------------------------------------------------- + # Test 3: Basic test2, rs = rd + #------------------------------------------------------------- + +test_3: + li TESTNUM, 3 + la t0, target_3 + + jalr t0, t0, 0 +linkaddr_3: + j fail + +target_3: + la t1, linkaddr_3 + bne t0, t1, fail + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_JALR_SRC1_BYPASS( 4, 0, jalr ); + TEST_JALR_SRC1_BYPASS( 5, 1, jalr ); + TEST_JALR_SRC1_BYPASS( 6, 2, jalr ); + + #------------------------------------------------------------- + # Test delay slot instructions not executed nor bypassed + #------------------------------------------------------------- + + .option push + .align 2 + .option norvc + TEST_CASE( 7, t0, 4, \ + li t0, 1; \ + la t1, 1f; \ + jr t1, -4; \ + addi t0, t0, 1; \ + addi t0, t0, 1; \ + addi t0, t0, 1; \ + addi t0, t0, 1; \ +1: addi t0, t0, 1; \ + addi t0, t0, 1; \ + ) + .option pop + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64ui/lb.S b/tb/qumcu/isa/rv64ui/lb.S new file mode 100644 index 0000000..856dfe9 --- /dev/null +++ b/tb/qumcu/isa/rv64ui/lb.S @@ -0,0 +1,92 @@ +# See LICENSE for license details. + +#***************************************************************************** +# lb.S +#----------------------------------------------------------------------------- +# +# Test lb instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Basic tests + #------------------------------------------------------------- + + TEST_LD_OP( 2, lb, 0xffffffffffffffff, 0, tdat ); + TEST_LD_OP( 3, lb, 0x0000000000000000, 1, tdat ); + TEST_LD_OP( 4, lb, 0xfffffffffffffff0, 2, tdat ); + TEST_LD_OP( 5, lb, 0x000000000000000f, 3, tdat ); + + # Test with negative offset + + TEST_LD_OP( 6, lb, 0xffffffffffffffff, -3, tdat4 ); + TEST_LD_OP( 7, lb, 0x0000000000000000, -2, tdat4 ); + TEST_LD_OP( 8, lb, 0xfffffffffffffff0, -1, tdat4 ); + TEST_LD_OP( 9, lb, 0x000000000000000f, 0, tdat4 ); + + # Test with a negative base + + TEST_CASE( 10, x5, 0xffffffffffffffff, \ + la x1, tdat; \ + addi x1, x1, -32; \ + lb x5, 32(x1); \ + ) + + # Test with unaligned base + + TEST_CASE( 11, x5, 0x0000000000000000, \ + la x1, tdat; \ + addi x1, x1, -6; \ + lb x5, 7(x1); \ + ) + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_LD_DEST_BYPASS( 12, 0, lb, 0xfffffffffffffff0, 1, tdat2 ); + TEST_LD_DEST_BYPASS( 13, 1, lb, 0x000000000000000f, 1, tdat3 ); + TEST_LD_DEST_BYPASS( 14, 2, lb, 0x0000000000000000, 1, tdat1 ); + + TEST_LD_SRC1_BYPASS( 15, 0, lb, 0xfffffffffffffff0, 1, tdat2 ); + TEST_LD_SRC1_BYPASS( 16, 1, lb, 0x000000000000000f, 1, tdat3 ); + TEST_LD_SRC1_BYPASS( 17, 2, lb, 0x0000000000000000, 1, tdat1 ); + + #------------------------------------------------------------- + # Test write-after-write hazard + #------------------------------------------------------------- + + TEST_CASE( 18, x2, 2, \ + la x5, tdat; \ + lb x2, 0(x5); \ + li x2, 2; \ + ) + + TEST_CASE( 19, x2, 2, \ + la x5, tdat; \ + lb x2, 0(x5); \ + nop; \ + li x2, 2; \ + ) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +tdat: +tdat1: .byte 0xff +tdat2: .byte 0x00 +tdat3: .byte 0xf0 +tdat4: .byte 0x0f + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64ui/lbu.S b/tb/qumcu/isa/rv64ui/lbu.S new file mode 100644 index 0000000..adc3a05 --- /dev/null +++ b/tb/qumcu/isa/rv64ui/lbu.S @@ -0,0 +1,92 @@ +# See LICENSE for license details. + +#***************************************************************************** +# lbu.S +#----------------------------------------------------------------------------- +# +# Test lbu instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Basic tests + #------------------------------------------------------------- + + TEST_LD_OP( 2, lbu, 0x00000000000000ff, 0, tdat ); + TEST_LD_OP( 3, lbu, 0x0000000000000000, 1, tdat ); + TEST_LD_OP( 4, lbu, 0x00000000000000f0, 2, tdat ); + TEST_LD_OP( 5, lbu, 0x000000000000000f, 3, tdat ); + + # Test with negative offset + + TEST_LD_OP( 6, lbu, 0x00000000000000ff, -3, tdat4 ); + TEST_LD_OP( 7, lbu, 0x0000000000000000, -2, tdat4 ); + TEST_LD_OP( 8, lbu, 0x00000000000000f0, -1, tdat4 ); + TEST_LD_OP( 9, lbu, 0x000000000000000f, 0, tdat4 ); + + # Test with a negative base + + TEST_CASE( 10, x5, 0x00000000000000ff, \ + la x1, tdat; \ + addi x1, x1, -32; \ + lbu x5, 32(x1); \ + ) + + # Test with unaligned base + + TEST_CASE( 11, x5, 0x0000000000000000, \ + la x1, tdat; \ + addi x1, x1, -6; \ + lbu x5, 7(x1); \ + ) + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_LD_DEST_BYPASS( 12, 0, lbu, 0x00000000000000f0, 1, tdat2 ); + TEST_LD_DEST_BYPASS( 13, 1, lbu, 0x000000000000000f, 1, tdat3 ); + TEST_LD_DEST_BYPASS( 14, 2, lbu, 0x0000000000000000, 1, tdat1 ); + + TEST_LD_SRC1_BYPASS( 15, 0, lbu, 0x00000000000000f0, 1, tdat2 ); + TEST_LD_SRC1_BYPASS( 16, 1, lbu, 0x000000000000000f, 1, tdat3 ); + TEST_LD_SRC1_BYPASS( 17, 2, lbu, 0x0000000000000000, 1, tdat1 ); + + #------------------------------------------------------------- + # Test write-after-write hazard + #------------------------------------------------------------- + + TEST_CASE( 18, x2, 2, \ + la x5, tdat; \ + lbu x2, 0(x5); \ + li x2, 2; \ + ) + + TEST_CASE( 19, x2, 2, \ + la x5, tdat; \ + lbu x2, 0(x5); \ + nop; \ + li x2, 2; \ + ) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +tdat: +tdat1: .byte 0xff +tdat2: .byte 0x00 +tdat3: .byte 0xf0 +tdat4: .byte 0x0f + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64ui/ld.S b/tb/qumcu/isa/rv64ui/ld.S new file mode 100644 index 0000000..948c34b --- /dev/null +++ b/tb/qumcu/isa/rv64ui/ld.S @@ -0,0 +1,92 @@ +# See LICENSE for license details. + +#***************************************************************************** +# ld.S +#----------------------------------------------------------------------------- +# +# Test ld instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Basic tests + #------------------------------------------------------------- + + TEST_LD_OP( 2, ld, 0x00ff00ff00ff00ff, 0, tdat ); + TEST_LD_OP( 3, ld, 0xff00ff00ff00ff00, 8, tdat ); + TEST_LD_OP( 4, ld, 0x0ff00ff00ff00ff0, 16, tdat ); + TEST_LD_OP( 5, ld, 0xf00ff00ff00ff00f, 24, tdat ); + + # Test with negative offset + + TEST_LD_OP( 6, ld, 0x00ff00ff00ff00ff, -24, tdat4 ); + TEST_LD_OP( 7, ld, 0xff00ff00ff00ff00, -16, tdat4 ); + TEST_LD_OP( 8, ld, 0x0ff00ff00ff00ff0, -8, tdat4 ); + TEST_LD_OP( 9, ld, 0xf00ff00ff00ff00f, 0, tdat4 ); + + # Test with a negative base + + TEST_CASE( 10, x5, 0x00ff00ff00ff00ff, \ + la x1, tdat; \ + addi x1, x1, -32; \ + ld x5, 32(x1); \ + ) + + # Test with unaligned base + + TEST_CASE( 11, x5, 0xff00ff00ff00ff00, \ + la x1, tdat; \ + addi x1, x1, -3; \ + ld x5, 11(x1); \ + ) + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_LD_DEST_BYPASS( 12, 0, ld, 0x0ff00ff00ff00ff0, 8, tdat2 ); + TEST_LD_DEST_BYPASS( 13, 1, ld, 0xf00ff00ff00ff00f, 8, tdat3 ); + TEST_LD_DEST_BYPASS( 14, 2, ld, 0xff00ff00ff00ff00, 8, tdat1 ); + + TEST_LD_SRC1_BYPASS( 15, 0, ld, 0x0ff00ff00ff00ff0, 8, tdat2 ); + TEST_LD_SRC1_BYPASS( 16, 1, ld, 0xf00ff00ff00ff00f, 8, tdat3 ); + TEST_LD_SRC1_BYPASS( 17, 2, ld, 0xff00ff00ff00ff00, 8, tdat1 ); + + #------------------------------------------------------------- + # Test write-after-write hazard + #------------------------------------------------------------- + + TEST_CASE( 18, x2, 2, \ + la x5, tdat; \ + ld x2, 0(x5); \ + li x2, 2; \ + ) + + TEST_CASE( 19, x2, 2, \ + la x5, tdat; \ + ld x2, 0(x5); \ + nop; \ + li x2, 2; \ + ) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +tdat: +tdat1: .dword 0x00ff00ff00ff00ff +tdat2: .dword 0xff00ff00ff00ff00 +tdat3: .dword 0x0ff00ff00ff00ff0 +tdat4: .dword 0xf00ff00ff00ff00f + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64ui/lh.S b/tb/qumcu/isa/rv64ui/lh.S new file mode 100644 index 0000000..338ed69 --- /dev/null +++ b/tb/qumcu/isa/rv64ui/lh.S @@ -0,0 +1,92 @@ +# See LICENSE for license details. + +#***************************************************************************** +# lh.S +#----------------------------------------------------------------------------- +# +# Test lh instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Basic tests + #------------------------------------------------------------- + + TEST_LD_OP( 2, lh, 0x00000000000000ff, 0, tdat ); + TEST_LD_OP( 3, lh, 0xffffffffffffff00, 2, tdat ); + TEST_LD_OP( 4, lh, 0x0000000000000ff0, 4, tdat ); + TEST_LD_OP( 5, lh, 0xfffffffffffff00f, 6, tdat ); + + # Test with negative offset + + TEST_LD_OP( 6, lh, 0x00000000000000ff, -6, tdat4 ); + TEST_LD_OP( 7, lh, 0xffffffffffffff00, -4, tdat4 ); + TEST_LD_OP( 8, lh, 0x0000000000000ff0, -2, tdat4 ); + TEST_LD_OP( 9, lh, 0xfffffffffffff00f, 0, tdat4 ); + + # Test with a negative base + + TEST_CASE( 10, x5, 0x00000000000000ff, \ + la x1, tdat; \ + addi x1, x1, -32; \ + lh x5, 32(x1); \ + ) + + # Test with unaligned base + + TEST_CASE( 11, x5, 0xffffffffffffff00, \ + la x1, tdat; \ + addi x1, x1, -5; \ + lh x5, 7(x1); \ + ) + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_LD_DEST_BYPASS( 12, 0, lh, 0x0000000000000ff0, 2, tdat2 ); + TEST_LD_DEST_BYPASS( 13, 1, lh, 0xfffffffffffff00f, 2, tdat3 ); + TEST_LD_DEST_BYPASS( 14, 2, lh, 0xffffffffffffff00, 2, tdat1 ); + + TEST_LD_SRC1_BYPASS( 15, 0, lh, 0x0000000000000ff0, 2, tdat2 ); + TEST_LD_SRC1_BYPASS( 16, 1, lh, 0xfffffffffffff00f, 2, tdat3 ); + TEST_LD_SRC1_BYPASS( 17, 2, lh, 0xffffffffffffff00, 2, tdat1 ); + + #------------------------------------------------------------- + # Test write-after-write hazard + #------------------------------------------------------------- + + TEST_CASE( 18, x2, 2, \ + la x5, tdat; \ + lh x2, 0(x5); \ + li x2, 2; \ + ) + + TEST_CASE( 19, x2, 2, \ + la x5, tdat; \ + lh x2, 0(x5); \ + nop; \ + li x2, 2; \ + ) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +tdat: +tdat1: .half 0x00ff +tdat2: .half 0xff00 +tdat3: .half 0x0ff0 +tdat4: .half 0xf00f + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64ui/lhu.S b/tb/qumcu/isa/rv64ui/lhu.S new file mode 100644 index 0000000..a4cc49b --- /dev/null +++ b/tb/qumcu/isa/rv64ui/lhu.S @@ -0,0 +1,92 @@ +# See LICENSE for license details. + +#***************************************************************************** +# lhu.S +#----------------------------------------------------------------------------- +# +# Test lhu instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Basic tests + #------------------------------------------------------------- + + TEST_LD_OP( 2, lhu, 0x00000000000000ff, 0, tdat ); + TEST_LD_OP( 3, lhu, 0x000000000000ff00, 2, tdat ); + TEST_LD_OP( 4, lhu, 0x0000000000000ff0, 4, tdat ); + TEST_LD_OP( 5, lhu, 0x000000000000f00f, 6, tdat ); + + # Test with negative offset + + TEST_LD_OP( 6, lhu, 0x00000000000000ff, -6, tdat4 ); + TEST_LD_OP( 7, lhu, 0x000000000000ff00, -4, tdat4 ); + TEST_LD_OP( 8, lhu, 0x0000000000000ff0, -2, tdat4 ); + TEST_LD_OP( 9, lhu, 0x000000000000f00f, 0, tdat4 ); + + # Test with a negative base + + TEST_CASE( 10, x5, 0x00000000000000ff, \ + la x1, tdat; \ + addi x1, x1, -32; \ + lhu x5, 32(x1); \ + ) + + # Test with unaligned base + + TEST_CASE( 11, x5, 0x000000000000ff00, \ + la x1, tdat; \ + addi x1, x1, -5; \ + lhu x5, 7(x1); \ + ) + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_LD_DEST_BYPASS( 12, 0, lhu, 0x0000000000000ff0, 2, tdat2 ); + TEST_LD_DEST_BYPASS( 13, 1, lhu, 0x000000000000f00f, 2, tdat3 ); + TEST_LD_DEST_BYPASS( 14, 2, lhu, 0x000000000000ff00, 2, tdat1 ); + + TEST_LD_SRC1_BYPASS( 15, 0, lhu, 0x0000000000000ff0, 2, tdat2 ); + TEST_LD_SRC1_BYPASS( 16, 1, lhu, 0x000000000000f00f, 2, tdat3 ); + TEST_LD_SRC1_BYPASS( 17, 2, lhu, 0x000000000000ff00, 2, tdat1 ); + + #------------------------------------------------------------- + # Test write-after-write hazard + #------------------------------------------------------------- + + TEST_CASE( 18, x2, 2, \ + la x5, tdat; \ + lhu x2, 0(x5); \ + li x2, 2; \ + ) + + TEST_CASE( 19, x2, 2, \ + la x5, tdat; \ + lhu x2, 0(x5); \ + nop; \ + li x2, 2; \ + ) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +tdat: +tdat1: .half 0x00ff +tdat2: .half 0xff00 +tdat3: .half 0x0ff0 +tdat4: .half 0xf00f + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64ui/lui.S b/tb/qumcu/isa/rv64ui/lui.S new file mode 100644 index 0000000..8a4e70c --- /dev/null +++ b/tb/qumcu/isa/rv64ui/lui.S @@ -0,0 +1,36 @@ +# See LICENSE for license details. + +#***************************************************************************** +# lui.S +#----------------------------------------------------------------------------- +# +# Test lui instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Basic tests + #------------------------------------------------------------- + + TEST_CASE( 2, x1, 0x0000000000000000, lui x1, 0x00000 ); + TEST_CASE( 3, x1, 0xfffffffffffff800, lui x1, 0xfffff;sra x1,x1,1); + TEST_CASE( 4, x1, 0x00000000000007ff, lui x1, 0x7ffff;sra x1,x1,20); + TEST_CASE( 5, x1, 0xfffffffffffff800, lui x1, 0x80000;sra x1,x1,20); + + TEST_CASE( 6, x0, 0, lui x0, 0x80000 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64ui/lw.S b/tb/qumcu/isa/rv64ui/lw.S new file mode 100644 index 0000000..40a73f1 --- /dev/null +++ b/tb/qumcu/isa/rv64ui/lw.S @@ -0,0 +1,92 @@ +# See LICENSE for license details. + +#***************************************************************************** +# lw.S +#----------------------------------------------------------------------------- +# +# Test lw instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Basic tests + #------------------------------------------------------------- + + TEST_LD_OP( 2, lw, 0x0000000000ff00ff, 0, tdat ); + TEST_LD_OP( 3, lw, 0xffffffffff00ff00, 4, tdat ); + TEST_LD_OP( 4, lw, 0x000000000ff00ff0, 8, tdat ); + TEST_LD_OP( 5, lw, 0xfffffffff00ff00f, 12, tdat ); + + # Test with negative offset + + TEST_LD_OP( 6, lw, 0x0000000000ff00ff, -12, tdat4 ); + TEST_LD_OP( 7, lw, 0xffffffffff00ff00, -8, tdat4 ); + TEST_LD_OP( 8, lw, 0x000000000ff00ff0, -4, tdat4 ); + TEST_LD_OP( 9, lw, 0xfffffffff00ff00f, 0, tdat4 ); + + # Test with a negative base + + TEST_CASE( 10, x5, 0x0000000000ff00ff, \ + la x1, tdat; \ + addi x1, x1, -32; \ + lw x5, 32(x1); \ + ) + + # Test with unaligned base + + TEST_CASE( 11, x5, 0xffffffffff00ff00, \ + la x1, tdat; \ + addi x1, x1, -3; \ + lw x5, 7(x1); \ + ) + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_LD_DEST_BYPASS( 12, 0, lw, 0x000000000ff00ff0, 4, tdat2 ); + TEST_LD_DEST_BYPASS( 13, 1, lw, 0xfffffffff00ff00f, 4, tdat3 ); + TEST_LD_DEST_BYPASS( 14, 2, lw, 0xffffffffff00ff00, 4, tdat1 ); + + TEST_LD_SRC1_BYPASS( 15, 0, lw, 0x000000000ff00ff0, 4, tdat2 ); + TEST_LD_SRC1_BYPASS( 16, 1, lw, 0xfffffffff00ff00f, 4, tdat3 ); + TEST_LD_SRC1_BYPASS( 17, 2, lw, 0xffffffffff00ff00, 4, tdat1 ); + + #------------------------------------------------------------- + # Test write-after-write hazard + #------------------------------------------------------------- + + TEST_CASE( 18, x2, 2, \ + la x5, tdat; \ + lw x2, 0(x5); \ + li x2, 2; \ + ) + + TEST_CASE( 19, x2, 2, \ + la x5, tdat; \ + lw x2, 0(x5); \ + nop; \ + li x2, 2; \ + ) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +tdat: +tdat1: .word 0x00ff00ff +tdat2: .word 0xff00ff00 +tdat3: .word 0x0ff00ff0 +tdat4: .word 0xf00ff00f + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64ui/lwu.S b/tb/qumcu/isa/rv64ui/lwu.S new file mode 100644 index 0000000..9f7cf67 --- /dev/null +++ b/tb/qumcu/isa/rv64ui/lwu.S @@ -0,0 +1,92 @@ +# See LICENSE for license details. + +#***************************************************************************** +# lwu.S +#----------------------------------------------------------------------------- +# +# Test lwu instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Basic tests + #------------------------------------------------------------- + + TEST_LD_OP( 2, lwu, 0x0000000000ff00ff, 0, tdat ); + TEST_LD_OP( 3, lwu, 0x00000000ff00ff00, 4, tdat ); + TEST_LD_OP( 4, lwu, 0x000000000ff00ff0, 8, tdat ); + TEST_LD_OP( 5, lwu, 0x00000000f00ff00f, 12, tdat ); + + # Test with negative offset + + TEST_LD_OP( 6, lwu, 0x0000000000ff00ff, -12, tdat4 ); + TEST_LD_OP( 7, lwu, 0x00000000ff00ff00, -8, tdat4 ); + TEST_LD_OP( 8, lwu, 0x000000000ff00ff0, -4, tdat4 ); + TEST_LD_OP( 9, lwu, 0x00000000f00ff00f, 0, tdat4 ); + + # Test with a negative base + + TEST_CASE( 10, x5, 0x0000000000ff00ff, \ + la x1, tdat; \ + addi x1, x1, -32; \ + lwu x5, 32(x1); \ + ) + + # Test with unaligned base + + TEST_CASE( 11, x5, 0x00000000ff00ff00, \ + la x1, tdat; \ + addi x1, x1, -3; \ + lwu x5, 7(x1); \ + ) + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_LD_DEST_BYPASS( 12, 0, lwu, 0x000000000ff00ff0, 4, tdat2 ); + TEST_LD_DEST_BYPASS( 13, 1, lwu, 0x00000000f00ff00f, 4, tdat3 ); + TEST_LD_DEST_BYPASS( 14, 2, lwu, 0x00000000ff00ff00, 4, tdat1 ); + + TEST_LD_SRC1_BYPASS( 15, 0, lwu, 0x000000000ff00ff0, 4, tdat2 ); + TEST_LD_SRC1_BYPASS( 16, 1, lwu, 0x00000000f00ff00f, 4, tdat3 ); + TEST_LD_SRC1_BYPASS( 17, 2, lwu, 0x00000000ff00ff00, 4, tdat1 ); + + #------------------------------------------------------------- + # Test write-after-write hazard + #------------------------------------------------------------- + + TEST_CASE( 18, x2, 2, \ + la x5, tdat; \ + lwu x2, 0(x5); \ + li x2, 2; \ + ) + + TEST_CASE( 19, x2, 2, \ + la x5, tdat; \ + lwu x2, 0(x5); \ + nop; \ + li x2, 2; \ + ) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +tdat: +tdat1: .word 0x00ff00ff +tdat2: .word 0xff00ff00 +tdat3: .word 0x0ff00ff0 +tdat4: .word 0xf00ff00f + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64ui/ma_data.S b/tb/qumcu/isa/rv64ui/ma_data.S new file mode 100644 index 0000000..eec7c55 --- /dev/null +++ b/tb/qumcu/isa/rv64ui/ma_data.S @@ -0,0 +1,383 @@ +# See LICENSE for license details. + +#***************************************************************************** +# ma_data.S +#----------------------------------------------------------------------------- +# +# Test misaligned ld/st data. +# Based on rv64mi-ma_addr.S +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + la s0, data + +#define SEXT(x, n) ((-((x) >> ((n)-1)) << (n)) | ((x) & ((1 << (n))-1))) + +/* Check that a misaligned load reads the correct value. */ +#define MISALIGNED_LOAD_TEST(testnum, insn, base, offset, res) \ + li TESTNUM, testnum; \ + li t1, res; \ + insn t2, offset(base); \ + bne t1, t2, fail; \ +1: + +# within quadword + MISALIGNED_LOAD_TEST(1, lh, s0, 1, SEXT(0x0201, 16)) + MISALIGNED_LOAD_TEST(2, lhu, s0, 1, 0x0201) + MISALIGNED_LOAD_TEST(3, lw, s0, 1, SEXT(0x04030201, 32)) + MISALIGNED_LOAD_TEST(4, lw, s0, 2, SEXT(0x05040302, 32)) + MISALIGNED_LOAD_TEST(5, lw, s0, 3, SEXT(0x06050403, 32)) + +#if __riscv_xlen == 64 + MISALIGNED_LOAD_TEST(6, lwu, s0, 1, 0x04030201) + MISALIGNED_LOAD_TEST(7, lwu, s0, 2, 0x05040302) + MISALIGNED_LOAD_TEST(8, lwu, s0, 3, 0x06050403) + + MISALIGNED_LOAD_TEST(9, ld, s0, 1, 0x0807060504030201) + MISALIGNED_LOAD_TEST(10, ld, s0, 2, 0x0908070605040302) + MISALIGNED_LOAD_TEST(11, ld, s0, 3, 0x0a09080706050403) + MISALIGNED_LOAD_TEST(12, ld, s0, 4, 0x0b0a090807060504) + MISALIGNED_LOAD_TEST(13, ld, s0, 5, 0x0c0b0a0908070605) + MISALIGNED_LOAD_TEST(14, ld, s0, 6, 0x0d0c0b0a09080706) + MISALIGNED_LOAD_TEST(15, ld, s0, 7, 0x0e0d0c0b0a090807) +#endif + +# octword crossing + MISALIGNED_LOAD_TEST(16, lh, s0, 31, SEXT(0x201f, 16)) + MISALIGNED_LOAD_TEST(17, lhu, s0, 31, 0x201f) + MISALIGNED_LOAD_TEST(18, lw, s0, 29, SEXT(0x201f1e1d, 32)) + MISALIGNED_LOAD_TEST(19, lw, s0, 30, SEXT(0x21201f1e, 32)) + MISALIGNED_LOAD_TEST(20, lw, s0, 31, SEXT(0x2221201f, 32)) + +#if __riscv_xlen == 64 + MISALIGNED_LOAD_TEST(21, lwu, s0, 29, 0x201f1e1d) + MISALIGNED_LOAD_TEST(22, lwu, s0, 30, 0x21201f1e) + MISALIGNED_LOAD_TEST(23, lwu, s0, 31, 0x2221201f) + + MISALIGNED_LOAD_TEST(24, ld, s0, 25, 0x201f1e1d1c1b1a19) + MISALIGNED_LOAD_TEST(25, ld, s0, 26, 0x21201f1e1d1c1b1a) + MISALIGNED_LOAD_TEST(26, ld, s0, 27, 0x2221201f1e1d1c1b) + MISALIGNED_LOAD_TEST(27, ld, s0, 28, 0x232221201f1e1d1c) + MISALIGNED_LOAD_TEST(28, ld, s0, 29, 0x24232221201f1e1d) + MISALIGNED_LOAD_TEST(29, ld, s0, 30, 0x2524232221201f1e) + MISALIGNED_LOAD_TEST(30, ld, s0, 31, 0x262524232221201f) +#endif + +# cacheline crossing + MISALIGNED_LOAD_TEST(31, lh, s0, 63, SEXT(0x403f, 16)) + MISALIGNED_LOAD_TEST(32, lhu, s0, 63, 0x403f) + MISALIGNED_LOAD_TEST(33, lw, s0, 61, SEXT(0x403f3e3d, 32)) + MISALIGNED_LOAD_TEST(34, lw, s0, 62, SEXT(0x41403f3e, 32)) + MISALIGNED_LOAD_TEST(35, lw, s0, 63, SEXT(0x4241403f, 32)) + +#if __riscv_xlen == 64 + MISALIGNED_LOAD_TEST(36, lwu, s0, 61, 0x403f3e3d) + MISALIGNED_LOAD_TEST(37, lwu, s0, 62, 0x41403f3e) + MISALIGNED_LOAD_TEST(38, lwu, s0, 63, 0x4241403f) + + MISALIGNED_LOAD_TEST(39, ld, s0, 57, 0x403f3e3d3c3b3a39) + MISALIGNED_LOAD_TEST(40, ld, s0, 58, 0x41403f3e3d3c3b3a) + MISALIGNED_LOAD_TEST(41, ld, s0, 59, 0x4241403f3e3d3c3b) + MISALIGNED_LOAD_TEST(42, ld, s0, 60, 0x434241403f3e3d3c) + MISALIGNED_LOAD_TEST(43, ld, s0, 61, 0x44434241403f3e3d) + MISALIGNED_LOAD_TEST(44, ld, s0, 62, 0x4544434241403f3e) + MISALIGNED_LOAD_TEST(45, ld, s0, 63, 0x464544434241403f) +#endif + + +/* Check that a misaligned store writes the correct value. */ +#define MISALIGNED_STORE_TEST(testnum, st_insn, ld_insn, base, offset, st_data) \ + li TESTNUM, testnum; \ + li t1, st_data; \ + st_insn t1, offset(base); \ + ld_insn t2, offset(base); \ + bne t1, t2, fail; \ +1: + +# within quadword + MISALIGNED_STORE_TEST(46, sh, lh, s0, 1, SEXT(0x8180, 16)) + MISALIGNED_STORE_TEST(47, sh, lhu, s0, 1, 0x8382) + MISALIGNED_STORE_TEST(48, sw, lw, s0, 1, SEXT(0x87868584, 32)) + MISALIGNED_STORE_TEST(49, sw, lw, s0, 2, SEXT(0x8b8a8988, 32)) + MISALIGNED_STORE_TEST(50, sw, lw, s0, 3, SEXT(0x8f8e8d8c, 32)) + +#if __riscv_xlen == 64 + MISALIGNED_STORE_TEST(51, sw, lwu, s0, 1, 0x93929190) + MISALIGNED_STORE_TEST(52, sw, lwu, s0, 2, 0x97969594) + MISALIGNED_STORE_TEST(53, sw, lwu, s0, 3, 0x9b9a9998) + + MISALIGNED_STORE_TEST(54, sd, ld, s0, 1, 0xa3a2a1a09f9e9d9c) + MISALIGNED_STORE_TEST(55, sd, ld, s0, 2, 0xabaaa9a8a7a6a5a4) + MISALIGNED_STORE_TEST(56, sd, ld, s0, 3, 0xb3b2b1b0afaeadac) + MISALIGNED_STORE_TEST(57, sd, ld, s0, 4, 0xbbbab9b8b7b6b5b4) + MISALIGNED_STORE_TEST(58, sd, ld, s0, 5, 0xc3c2c1c0bfbebdbc) + MISALIGNED_STORE_TEST(59, sd, ld, s0, 6, 0xcbcac9c8c7c6c5c4) + MISALIGNED_STORE_TEST(60, sd, ld, s0, 7, 0xd3d2d1d0cfcecdcc) +#endif + +# octword crossing + MISALIGNED_STORE_TEST(61, sh, lh, s0, 31, SEXT(0xd5d4, 16)) + MISALIGNED_STORE_TEST(62, sh, lhu, s0, 31, 0xd7d6) + MISALIGNED_STORE_TEST(63, sw, lw, s0, 29, SEXT(0xdbdad9d8, 32)) + MISALIGNED_STORE_TEST(64, sw, lw, s0, 30, SEXT(0xdfdedddc, 32)) + MISALIGNED_STORE_TEST(65, sw, lw, s0, 31, SEXT(0xe3e2e1e0, 32)) + +#if __riscv_xlen == 64 + MISALIGNED_STORE_TEST(66, sw, lwu, s0, 29, 0xe7e6e5e4) + MISALIGNED_STORE_TEST(67, sw, lwu, s0, 30, 0xebeae9e8) + MISALIGNED_STORE_TEST(68, sw, lwu, s0, 31, 0xefeeedec) + + MISALIGNED_STORE_TEST(69, sd, ld, s0, 25, 0xf7f6f5f4f3f2f1f0) + MISALIGNED_STORE_TEST(70, sd, ld, s0, 26, 0xfffefdfcfbfaf9f8) + MISALIGNED_STORE_TEST(71, sd, ld, s0, 27, 0x0706050403020100) + MISALIGNED_STORE_TEST(72, sd, ld, s0, 28, 0x0f0e0d0c0b0a0908) + MISALIGNED_STORE_TEST(73, sd, ld, s0, 29, 0x1716151413121110) + MISALIGNED_STORE_TEST(74, sd, ld, s0, 30, 0x1f1e1d1c1b1a1918) + MISALIGNED_STORE_TEST(75, sd, ld, s0, 31, 0x2726252423222120) +#endif + +# cacheline crossing + MISALIGNED_STORE_TEST(76, sh, lh, s0, 63, SEXT(0x3534, 16)) + MISALIGNED_STORE_TEST(77, sh, lhu, s0, 63, 0x3736) + MISALIGNED_STORE_TEST(78, sw, lw, s0, 61, SEXT(0x3b3a3938, 32)) + MISALIGNED_STORE_TEST(79, sw, lw, s0, 62, SEXT(0x3f3e3d3c, 32)) + MISALIGNED_STORE_TEST(80, sw, lw, s0, 63, SEXT(0x43424140, 32)) + +#if __riscv_xlen == 64 + MISALIGNED_STORE_TEST(81, sw, lwu, s0, 61, 0x47464544) + MISALIGNED_STORE_TEST(82, sw, lwu, s0, 62, 0x4b4a4948) + MISALIGNED_STORE_TEST(83, sw, lwu, s0, 63, 0x4f4e4d4c) + + MISALIGNED_STORE_TEST(84, sd, ld, s0, 57, 0x5756555453525150) + MISALIGNED_STORE_TEST(85, sd, ld, s0, 58, 0x5f5e5d5c5b5a5958) + MISALIGNED_STORE_TEST(86, sd, ld, s0, 59, 0x6766656463626160) + MISALIGNED_STORE_TEST(87, sd, ld, s0, 60, 0x6f6e6d6c6b6a6968) + MISALIGNED_STORE_TEST(88, sd, ld, s0, 61, 0x7776757473727170) + MISALIGNED_STORE_TEST(89, sd, ld, s0, 62, 0x7f7e7d7c7b7a7978) + MISALIGNED_STORE_TEST(90, sd, ld, s0, 63, 0x8786858483828180) +#endif + + +/* Check that a misaligned store writes the correct value, checked by a narrower load. */ +#define MISMATCHED_STORE_TEST(testnum, st_insn, ld_insn, base, st_offset, ld_offset, st_data, ld_data) \ + li TESTNUM, testnum; \ + li t1, st_data; \ + li t2, ld_data; \ + st_insn t1, st_offset(base); \ + ld_insn t3, ld_offset(base); \ + bne t2, t3, fail; \ +1: + +# within quadword + MISMATCHED_STORE_TEST(91, sh, lb, s0, 1, 1, 0x9998, SEXT(0x98, 8)) + MISMATCHED_STORE_TEST(92, sh, lb, s0, 1, 2, 0x9b9a, SEXT(0x9b, 8)) + MISMATCHED_STORE_TEST(93, sh, lbu, s0, 1, 1, 0x9d9c, 0x9c) + MISMATCHED_STORE_TEST(94, sh, lbu, s0, 1, 2, 0x9f9e, 0x9f) + MISMATCHED_STORE_TEST(95, sw, lb, s0, 1, 1, 0xa3a2a1a0, SEXT(0xa0, 8)) + MISMATCHED_STORE_TEST(96, sw, lbu, s0, 2, 3, 0xa7a6a5a4, 0xa5) + MISMATCHED_STORE_TEST(97, sw, lh, s0, 3, 4, 0xabaaa9a8, SEXT(0xaaa9, 16)) + MISMATCHED_STORE_TEST(98, sw, lhu, s0, 3, 5, 0xafaeadac, 0xafae) + +#if __riscv_xlen == 64 + MISMATCHED_STORE_TEST(99, sd, lb, s0, 1, 7, 0xb7b6b5b4b3b2b1b0, SEXT(0xb6, 8)) + MISMATCHED_STORE_TEST(100, sd, lbu, s0, 2, 3, 0xbfbebdbcbbbab9b8, 0xb9) + MISMATCHED_STORE_TEST(101, sd, lh, s0, 3, 9, 0xc7c6c5c4c3c2c1c0, SEXT(0xc7c6, 16)) + MISMATCHED_STORE_TEST(102, sd, lhu, s0, 4, 5, 0xcfcecdcccbcac9c8, 0xcac9) + MISMATCHED_STORE_TEST(103, sd, lw, s0, 5, 9, 0xd7d6d5d4d3d2d1d0, SEXT(0xd7d6d5d4, 32)) + MISMATCHED_STORE_TEST(104, sd, lw, s0, 6, 8, 0xdfdedddcdbdad9d8, SEXT(0xdddcdbda, 32)) + MISMATCHED_STORE_TEST(105, sd, lwu, s0, 7, 8, 0xe7e6e5e4e3e2e1e0, 0xe4e3e2e1) +#endif + +# octword crossing + MISMATCHED_STORE_TEST(106, sh, lb, s0, 31, 31, 0xe9e8, SEXT(0xe8, 8)) + MISMATCHED_STORE_TEST(107, sh, lb, s0, 31, 32, 0xebea, SEXT(0xeb, 8)) + MISMATCHED_STORE_TEST(108, sh, lbu, s0, 31, 31, 0xedec, 0xec) + MISMATCHED_STORE_TEST(109, sh, lbu, s0, 31, 32, 0xefee, 0xef) + MISMATCHED_STORE_TEST(110, sw, lb, s0, 29, 29, 0xf3f2f1f0, SEXT(0xf0, 8)) + MISMATCHED_STORE_TEST(111, sw, lbu, s0, 30, 32, 0xf7f6f5f4, 0xf6) + MISMATCHED_STORE_TEST(112, sw, lh, s0, 29, 31, 0xfbfaf9f8, SEXT(0xfbfa, 16)) + MISMATCHED_STORE_TEST(113, sw, lhu, s0, 31, 31, 0xfffefdfc, 0xfdfc) + +#if __riscv_xlen == 64 + MISMATCHED_STORE_TEST(114, sd, lb, s0, 25, 32, 0x0706050403020100, SEXT(0x07, 8)) + MISMATCHED_STORE_TEST(115, sd, lbu, s0, 26, 33, 0x0f0e0d0c0b0a0908, 0x0f) + MISMATCHED_STORE_TEST(116, sd, lh, s0, 27, 31, 0x1716151413121110, SEXT(0x1514, 16)) + MISMATCHED_STORE_TEST(117, sd, lhu, s0, 28, 31, 0x1f1e1d1c1b1a1918, 0x1c1b) + MISMATCHED_STORE_TEST(118, sd, lw, s0, 29, 29, 0x2726252423222120, SEXT(0x23222120, 32)) + MISMATCHED_STORE_TEST(119, sd, lw, s0, 30, 30, 0x2f2e2d2c2b2a2928, SEXT(0x2b2a2928, 32)) + MISMATCHED_STORE_TEST(120, sd, lwu, s0, 31, 31, 0x3736353433323130, 0x33323130) +#endif + +# cacheline crossing + MISMATCHED_STORE_TEST(121, sh, lb, s0, 63, 63, 0x4948, SEXT(0x48, 8)) + MISMATCHED_STORE_TEST(122, sh, lb, s0, 63, 64, 0x4b4a, SEXT(0x4b, 8)) + MISMATCHED_STORE_TEST(123, sh, lbu, s0, 63, 63, 0x4d4c, 0x4c) + MISMATCHED_STORE_TEST(124, sh, lbu, s0, 63, 64, 0x4f4e, 0x4f) + MISMATCHED_STORE_TEST(125, sw, lb, s0, 61, 61, 0x53525150, SEXT(0x50, 8)) + MISMATCHED_STORE_TEST(126, sw, lbu, s0, 62, 64, 0x57565554, 0x56) + MISMATCHED_STORE_TEST(127, sw, lh, s0, 61, 63, 0x5b5a5958, SEXT(0x5b5a, 16)) + MISMATCHED_STORE_TEST(128, sw, lhu, s0, 63, 63, 0x5f5e5d5c, 0x5d5c) + +#if __riscv_xlen == 64 + MISMATCHED_STORE_TEST(129, sd, lb, s0, 57, 64, 0x6766656463626160, SEXT(0x67, 8)) + MISMATCHED_STORE_TEST(130, sd, lbu, s0, 58, 65, 0x6f6e6d6c6b6a6968, 0x6f) + MISMATCHED_STORE_TEST(131, sd, lh, s0, 59, 63, 0x7776757473727170, SEXT(0x7574, 16)) + MISMATCHED_STORE_TEST(132, sd, lhu, s0, 60, 63, 0x7f7e7d7c7b7a7978, 0x7c7b) + MISMATCHED_STORE_TEST(133, sd, lw, s0, 61, 61, 0x8786858483828180, SEXT(0x83828180, 32)) + MISMATCHED_STORE_TEST(134, sd, lw, s0, 62, 62, 0x8f8e8d8c8b8a8988, SEXT(0x8b8a8988, 32)) + MISMATCHED_STORE_TEST(135, sd, lwu, s0, 63, 63, 0x9796959493929190, 0x93929190) +#endif + +/* Memory contents at this point should be: +.word 0x10080000 +.word 0x30282018 +.word 0x34333231 +.word 0x0f373635 +.word 0x13121110 +.word 0x17161514 +.word 0x10080018 +.word 0x30282018 + +.word 0x34333231 +.word 0x27373635 +.word 0x2b2a2928 +.word 0x2f2e2d2c +.word 0x33323130 +.word 0x37363534 +.word 0x70686038 +.word 0x90888078 + +.word 0x94939291 +.word 0x47979695 +.word 0x4b4a4948 +.word 0x4f4e4d4c +.word 0x53525150 +.word 0x57565554 +.word 0x5b5a5958 +.word 0x5f5e5d5c +.word 0x63626160 +.word 0x67666564 +.word 0x6b6a6968 +.word 0x6f6e6d6c +.word 0x73727170 +.word 0x77767574 +.word 0x7b7a7978 +.word 0x7f7e7d7c +*/ + +/* Check that a misaligned store writes the correct value, checked by a wider load. */ + +#if __riscv_xlen == 64 +# within quadword + MISMATCHED_STORE_TEST(136, sb, lh, s0, 1, 1, 0x98, SEXT(0xb898, 16)) + MISMATCHED_STORE_TEST(137, sb, lhu, s0, 2, 1, 0x99, 0x9998) + MISMATCHED_STORE_TEST(138, sh, lw, s0, 1, 1, 0x9b9a, SEXT(0xc8c09b9a, 32)) + MISMATCHED_STORE_TEST(139, sh, lw, s0, 3, 2, 0x9d9c, SEXT(0xd09d9c9b, 32)) + MISMATCHED_STORE_TEST(140, sh, lw, s0, 5, 3, 0x9f9e, SEXT(0x9f9e9d9c, 32)) + + MISMATCHED_STORE_TEST(141, sb, lwu, s0, 2, 1, 0xa0, 0x9d9ca09a) + MISMATCHED_STORE_TEST(142, sh, lwu, s0, 3, 2, 0xa2a1, 0x9ea2a1a0) + MISMATCHED_STORE_TEST(143, sh, lwu, s0, 5, 3, 0xa4a3, 0xa4a3a2a1) + + MISMATCHED_STORE_TEST(144, sb, ld, s0, 2, 1, 0xa5, 0xe1e0a4a3a2a1a59a) + MISMATCHED_STORE_TEST(145, sh, ld, s0, 7, 2, 0xa7a6, 0xe2a7a6a4a3a2a1a5) + MISMATCHED_STORE_TEST(146, sh, ld, s0, 9, 3, 0xa9a8, 0xa9a8a7a6a4a3a2a1) + MISMATCHED_STORE_TEST(147, sw, ld, s0, 5, 4, 0xadacabaa, 0xe4a9a8adacabaaa2) + MISMATCHED_STORE_TEST(148, sw, ld, s0, 7, 5, 0xb1b0afae, 0xe5e4b1b0afaeabaa) + MISMATCHED_STORE_TEST(149, sw, ld, s0, 9, 6, 0xb5b4b3b2, 0xe6b5b4b3b2afaeab) + MISMATCHED_STORE_TEST(150, sw, ld, s0, 11, 7, 0xb9b8b7b6, 0xb9b8b7b6b3b2afae) + +# octword crossing + MISMATCHED_STORE_TEST(151, sb, lh, s0, 31, 31, 0xba, SEXT(0x31ba, 16)) + MISMATCHED_STORE_TEST(152, sb, lhu, s0, 32, 31, 0xbb, 0xbbba) + MISMATCHED_STORE_TEST(153, sh, lw, s0, 30, 30, 0xbdbc, SEXT(0x32bbbdbc, 32)) + MISMATCHED_STORE_TEST(154, sh, lw, s0, 31, 30, 0xbfbe, SEXT(0x32bfbebc, 32)) + MISMATCHED_STORE_TEST(155, sh, lw, s0, 32, 30, 0xc1c0, SEXT(0xc1c0bebc, 32)) + + MISMATCHED_STORE_TEST(156, sb, lwu, s0, 32, 31, 0xc2, 0x33c1c2be) + MISMATCHED_STORE_TEST(157, sh, lwu, s0, 31, 29, 0xc4c3, 0xc4c3bc20) + MISMATCHED_STORE_TEST(158, sh, lwu, s0, 32, 30, 0xc6c5, 0xc6c5c3bc) + + MISMATCHED_STORE_TEST(159, sb, ld, s0, 32, 25, 0xc7, 0xc7c3bc2018100800) + MISMATCHED_STORE_TEST(160, sh, ld, s0, 31, 26, 0xc9c8, 0xc6c9c8bc20181008) + MISMATCHED_STORE_TEST(161, sh, ld, s0, 31, 27, 0xcbca, 0x33c6cbcabc201810) + MISMATCHED_STORE_TEST(162, sw, ld, s0, 32, 28, 0xcfcecdcc, 0xcfcecdcccabc2018) + MISMATCHED_STORE_TEST(163, sw, ld, s0, 31, 29, 0xd3d2d1d0, 0x35cfd3d2d1d0bc20) + MISMATCHED_STORE_TEST(164, sw, ld, s0, 30, 30, 0xd7d6d5d4, 0x3635cfd3d7d6d5d4) + MISMATCHED_STORE_TEST(165, sw, ld, s0, 29, 31, 0xdbdad9d8, 0x373635cfd3d7dbda) + +# cacheline crossing + MISMATCHED_STORE_TEST(166, sb, lh, s0, 63, 63, 0xdc, SEXT(0x91dc, 16)) + MISMATCHED_STORE_TEST(167, sb, lhu, s0, 64, 63, 0xdd, 0xdddc) + MISMATCHED_STORE_TEST(168, sh, lw, s0, 62, 62, 0xdfde, SEXT(0x92dddfde, 32)) + MISMATCHED_STORE_TEST(169, sh, lw, s0, 63, 62, 0xe1e0, SEXT(0x92e1e0de, 32)) + MISMATCHED_STORE_TEST(170, sh, lw, s0, 64, 62, 0xe3e2, SEXT(0xe3e2e0de, 32)) + + MISMATCHED_STORE_TEST(171, sb, lwu, s0, 64, 63, 0xe4, 0x93e3e4e0) + MISMATCHED_STORE_TEST(172, sh, lwu, s0, 63, 61, 0xe6e5, 0xe6e5de80) + MISMATCHED_STORE_TEST(173, sh, lwu, s0, 64, 62, 0xe8e7, 0xe8e7e5de) + + MISMATCHED_STORE_TEST(174, sb, ld, s0, 64, 57, 0xe9, 0xe9e5de8078706860) + MISMATCHED_STORE_TEST(175, sh, ld, s0, 63, 58, 0xebea, 0xe8ebeade80787068) + MISMATCHED_STORE_TEST(176, sh, ld, s0, 63, 59, 0xedec, 0x93e8edecde807870) + MISMATCHED_STORE_TEST(177, sw, ld, s0, 64, 60, 0xf1f0efee, 0xf1f0efeeecde8078) + MISMATCHED_STORE_TEST(178, sw, ld, s0, 63, 61, 0xf5f4f3f2, 0x95f1f5f4f3f2de80) + MISMATCHED_STORE_TEST(179, sw, ld, s0, 62, 62, 0xf9f8f7f6, 0x9695f1f5f9f8f7f6) + MISMATCHED_STORE_TEST(180, sw, ld, s0, 61, 63, 0xfdfcfbfa, 0x979695f1f5f9fdfc) +#endif + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + +data: + .align 3 + +.word 0x03020100 +.word 0x07060504 +.word 0x0b0a0908 +.word 0x0f0e0d0c +.word 0x13121110 +.word 0x17161514 +.word 0x1b1a1918 +.word 0x1f1e1d1c +.word 0x23222120 +.word 0x27262524 +.word 0x2b2a2928 +.word 0x2f2e2d2c +.word 0x33323130 +.word 0x37363534 +.word 0x3b3a3938 +.word 0x3f3e3d3c + +.word 0x43424140 +.word 0x47464544 +.word 0x4b4a4948 +.word 0x4f4e4d4c +.word 0x53525150 +.word 0x57565554 +.word 0x5b5a5958 +.word 0x5f5e5d5c +.word 0x63626160 +.word 0x67666564 +.word 0x6b6a6968 +.word 0x6f6e6d6c +.word 0x73727170 +.word 0x77767574 +.word 0x7b7a7978 +.word 0x7f7e7d7c + +.fill 0xff, 1, 80 + + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64ui/or.S b/tb/qumcu/isa/rv64ui/or.S new file mode 100644 index 0000000..6d84f53 --- /dev/null +++ b/tb/qumcu/isa/rv64ui/or.S @@ -0,0 +1,69 @@ +# See LICENSE for license details. + +#***************************************************************************** +# or.S +#----------------------------------------------------------------------------- +# +# Test or instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Logical tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f ); + TEST_RR_OP( 3, or, 0xfff0fff0, 0x0ff00ff0, 0xf0f0f0f0 ); + TEST_RR_OP( 4, or, 0x0fff0fff, 0x00ff00ff, 0x0f0f0f0f ); + TEST_RR_OP( 5, or, 0xf0fff0ff, 0xf00ff00f, 0xf0f0f0f0 ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 6, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f ); + TEST_RR_SRC2_EQ_DEST( 7, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f ); + TEST_RR_SRC12_EQ_DEST( 8, or, 0xff00ff00, 0xff00ff00 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 9, 0, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f ); + TEST_RR_DEST_BYPASS( 10, 1, or, 0xfff0fff0, 0x0ff00ff0, 0xf0f0f0f0 ); + TEST_RR_DEST_BYPASS( 11, 2, or, 0x0fff0fff, 0x00ff00ff, 0x0f0f0f0f ); + + TEST_RR_SRC12_BYPASS( 12, 0, 0, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f ); + TEST_RR_SRC12_BYPASS( 13, 0, 1, or, 0xfff0fff0, 0x0ff00ff0, 0xf0f0f0f0 ); + TEST_RR_SRC12_BYPASS( 14, 0, 2, or, 0x0fff0fff, 0x00ff00ff, 0x0f0f0f0f ); + TEST_RR_SRC12_BYPASS( 15, 1, 0, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f ); + TEST_RR_SRC12_BYPASS( 16, 1, 1, or, 0xfff0fff0, 0x0ff00ff0, 0xf0f0f0f0 ); + TEST_RR_SRC12_BYPASS( 17, 2, 0, or, 0x0fff0fff, 0x00ff00ff, 0x0f0f0f0f ); + + TEST_RR_SRC21_BYPASS( 18, 0, 0, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f ); + TEST_RR_SRC21_BYPASS( 19, 0, 1, or, 0xfff0fff0, 0x0ff00ff0, 0xf0f0f0f0 ); + TEST_RR_SRC21_BYPASS( 20, 0, 2, or, 0x0fff0fff, 0x00ff00ff, 0x0f0f0f0f ); + TEST_RR_SRC21_BYPASS( 21, 1, 0, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f ); + TEST_RR_SRC21_BYPASS( 22, 1, 1, or, 0xfff0fff0, 0x0ff00ff0, 0xf0f0f0f0 ); + TEST_RR_SRC21_BYPASS( 23, 2, 0, or, 0x0fff0fff, 0x00ff00ff, 0x0f0f0f0f ); + + TEST_RR_ZEROSRC1( 24, or, 0xff00ff00, 0xff00ff00 ); + TEST_RR_ZEROSRC2( 25, or, 0x00ff00ff, 0x00ff00ff ); + TEST_RR_ZEROSRC12( 26, or, 0 ); + TEST_RR_ZERODEST( 27, or, 0x11111111, 0x22222222 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64ui/ori.S b/tb/qumcu/isa/rv64ui/ori.S new file mode 100644 index 0000000..437c00a --- /dev/null +++ b/tb/qumcu/isa/rv64ui/ori.S @@ -0,0 +1,55 @@ +# See LICENSE for license details. + +#***************************************************************************** +# ori.S +#----------------------------------------------------------------------------- +# +# Test ori instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Logical tests + #------------------------------------------------------------- + + TEST_IMM_OP( 2, ori, 0xffffffffffffff0f, 0xffffffffff00ff00, 0xf0f ); + TEST_IMM_OP( 3, ori, 0x000000000ff00ff0, 0x000000000ff00ff0, 0x0f0 ); + TEST_IMM_OP( 4, ori, 0x0000000000ff07ff, 0x0000000000ff00ff, 0x70f ); + TEST_IMM_OP( 5, ori, 0xfffffffff00ff0ff, 0xfffffffff00ff00f, 0x0f0 ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_IMM_SRC1_EQ_DEST( 6, ori, 0xff00fff0, 0xff00ff00, 0x0f0 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_IMM_DEST_BYPASS( 7, 0, ori, 0x000000000ff00ff0, 0x000000000ff00ff0, 0x0f0 ); + TEST_IMM_DEST_BYPASS( 8, 1, ori, 0x0000000000ff07ff, 0x0000000000ff00ff, 0x70f ); + TEST_IMM_DEST_BYPASS( 9, 2, ori, 0xfffffffff00ff0ff, 0xfffffffff00ff00f, 0x0f0 ); + + TEST_IMM_SRC1_BYPASS( 10, 0, ori, 0x000000000ff00ff0, 0x000000000ff00ff0, 0x0f0 ); + TEST_IMM_SRC1_BYPASS( 11, 1, ori, 0xffffffffffffffff, 0x0000000000ff00ff, 0xf0f ); + TEST_IMM_SRC1_BYPASS( 12, 2, ori, 0xfffffffff00ff0ff, 0xfffffffff00ff00f, 0x0f0 ); + + TEST_IMM_ZEROSRC1( 13, ori, 0x0f0, 0x0f0 ); + TEST_IMM_ZERODEST( 14, ori, 0x00ff00ff, 0x70f ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64ui/sb.S b/tb/qumcu/isa/rv64ui/sb.S new file mode 100644 index 0000000..19e32d6 --- /dev/null +++ b/tb/qumcu/isa/rv64ui/sb.S @@ -0,0 +1,96 @@ +# See LICENSE for license details. + +#***************************************************************************** +# sb.S +#----------------------------------------------------------------------------- +# +# Test sb instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Basic tests + #------------------------------------------------------------- + + TEST_ST_OP( 2, lb, sb, 0xffffffffffffffaa, 0, tdat ); + TEST_ST_OP( 3, lb, sb, 0x0000000000000000, 1, tdat ); + TEST_ST_OP( 4, lh, sb, 0xffffffffffffefa0, 2, tdat ); + TEST_ST_OP( 5, lb, sb, 0x000000000000000a, 3, tdat ); + + # Test with negative offset + + TEST_ST_OP( 6, lb, sb, 0xffffffffffffffaa, -3, tdat8 ); + TEST_ST_OP( 7, lb, sb, 0x0000000000000000, -2, tdat8 ); + TEST_ST_OP( 8, lb, sb, 0xffffffffffffffa0, -1, tdat8 ); + TEST_ST_OP( 9, lb, sb, 0x000000000000000a, 0, tdat8 ); + + # Test with a negative base + + TEST_CASE( 10, x5, 0x78, \ + la x1, tdat9; \ + li x2, 0x12345678; \ + addi x4, x1, -32; \ + sb x2, 32(x4); \ + lb x5, 0(x1); \ + ) + + # Test with unaligned base + + TEST_CASE( 11, x5, 0xffffffffffffff98, \ + la x1, tdat9; \ + li x2, 0x00003098; \ + addi x1, x1, -6; \ + sb x2, 7(x1); \ + la x4, tdat10; \ + lb x5, 0(x4); \ + ) + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_ST_SRC12_BYPASS( 12, 0, 0, lb, sb, 0xffffffffffffffdd, 0, tdat ); + TEST_ST_SRC12_BYPASS( 13, 0, 1, lb, sb, 0xffffffffffffffcd, 1, tdat ); + TEST_ST_SRC12_BYPASS( 14, 0, 2, lb, sb, 0xffffffffffffffcc, 2, tdat ); + TEST_ST_SRC12_BYPASS( 15, 1, 0, lb, sb, 0xffffffffffffffbc, 3, tdat ); + TEST_ST_SRC12_BYPASS( 16, 1, 1, lb, sb, 0xffffffffffffffbb, 4, tdat ); + TEST_ST_SRC12_BYPASS( 17, 2, 0, lb, sb, 0xffffffffffffffab, 5, tdat ); + + TEST_ST_SRC21_BYPASS( 18, 0, 0, lb, sb, 0x33, 0, tdat ); + TEST_ST_SRC21_BYPASS( 19, 0, 1, lb, sb, 0x23, 1, tdat ); + TEST_ST_SRC21_BYPASS( 20, 0, 2, lb, sb, 0x22, 2, tdat ); + TEST_ST_SRC21_BYPASS( 21, 1, 0, lb, sb, 0x12, 3, tdat ); + TEST_ST_SRC21_BYPASS( 22, 1, 1, lb, sb, 0x11, 4, tdat ); + TEST_ST_SRC21_BYPASS( 23, 2, 0, lb, sb, 0x01, 5, tdat ); + + li a0, 0xef + la a1, tdat + sb a0, 3(a1) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +tdat: +tdat1: .byte 0xef +tdat2: .byte 0xef +tdat3: .byte 0xef +tdat4: .byte 0xef +tdat5: .byte 0xef +tdat6: .byte 0xef +tdat7: .byte 0xef +tdat8: .byte 0xef +tdat9: .byte 0xef +tdat10: .byte 0xef + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64ui/sd.S b/tb/qumcu/isa/rv64ui/sd.S new file mode 100644 index 0000000..b6fd66d --- /dev/null +++ b/tb/qumcu/isa/rv64ui/sd.S @@ -0,0 +1,92 @@ +# See LICENSE for license details. + +#***************************************************************************** +# sd.S +#----------------------------------------------------------------------------- +# +# Test sd instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Basic tests + #------------------------------------------------------------- + + TEST_ST_OP( 2, ld, sd, 0x00aa00aa00aa00aa, 0, tdat ); + TEST_ST_OP( 3, ld, sd, 0xaa00aa00aa00aa00, 8, tdat ); + TEST_ST_OP( 4, ld, sd, 0x0aa00aa00aa00aa0, 16, tdat ); + TEST_ST_OP( 5, ld, sd, 0xa00aa00aa00aa00a, 24, tdat ); + + # Test with negative offset + + TEST_ST_OP( 6, ld, sd, 0x00aa00aa00aa00aa, -24, tdat8 ); + TEST_ST_OP( 7, ld, sd, 0xaa00aa00aa00aa00, -16, tdat8 ); + TEST_ST_OP( 8, ld, sd, 0x0aa00aa00aa00aa0, -8, tdat8 ); + TEST_ST_OP( 9, ld, sd, 0xa00aa00aa00aa00a, 0, tdat8 ); + + # Test with a negative base + + TEST_CASE( 10, x5, 0x1234567812345678, \ + la x1, tdat9; \ + li x2, 0x1234567812345678; \ + addi x4, x1, -32; \ + sd x2, 32(x4); \ + ld x5, 0(x1); \ + ) + + # Test with unaligned base + + TEST_CASE( 11, x5, 0x5821309858213098, \ + la x1, tdat9; \ + li x2, 0x5821309858213098; \ + addi x1, x1, -3; \ + sd x2, 11(x1); \ + la x4, tdat10; \ + ld x5, 0(x4); \ + ) + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_ST_SRC12_BYPASS( 12, 0, 0, ld, sd, 0xabbccdd, 0, tdat ); + TEST_ST_SRC12_BYPASS( 13, 0, 1, ld, sd, 0xaabbccd, 8, tdat ); + TEST_ST_SRC12_BYPASS( 14, 0, 2, ld, sd, 0xdaabbcc, 16, tdat ); + TEST_ST_SRC12_BYPASS( 15, 1, 0, ld, sd, 0xddaabbc, 24, tdat ); + TEST_ST_SRC12_BYPASS( 16, 1, 1, ld, sd, 0xcddaabb, 32, tdat ); + TEST_ST_SRC12_BYPASS( 17, 2, 0, ld, sd, 0xccddaab, 40, tdat ); + + TEST_ST_SRC21_BYPASS( 18, 0, 0, ld, sd, 0x00112233, 0, tdat ); + TEST_ST_SRC21_BYPASS( 19, 0, 1, ld, sd, 0x30011223, 8, tdat ); + TEST_ST_SRC21_BYPASS( 20, 0, 2, ld, sd, 0x33001122, 16, tdat ); + TEST_ST_SRC21_BYPASS( 21, 1, 0, ld, sd, 0x23300112, 24, tdat ); + TEST_ST_SRC21_BYPASS( 22, 1, 1, ld, sd, 0x22330011, 32, tdat ); + TEST_ST_SRC21_BYPASS( 23, 2, 0, ld, sd, 0x12233001, 40, tdat ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +tdat: +tdat1: .dword 0xdeadbeefdeadbeef +tdat2: .dword 0xdeadbeefdeadbeef +tdat3: .dword 0xdeadbeefdeadbeef +tdat4: .dword 0xdeadbeefdeadbeef +tdat5: .dword 0xdeadbeefdeadbeef +tdat6: .dword 0xdeadbeefdeadbeef +tdat7: .dword 0xdeadbeefdeadbeef +tdat8: .dword 0xdeadbeefdeadbeef +tdat9: .dword 0xdeadbeefdeadbeef +tdat10: .dword 0xdeadbeefdeadbeef + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64ui/sh.S b/tb/qumcu/isa/rv64ui/sh.S new file mode 100644 index 0000000..ea9eb23 --- /dev/null +++ b/tb/qumcu/isa/rv64ui/sh.S @@ -0,0 +1,96 @@ +# See LICENSE for license details. + +#***************************************************************************** +# sh.S +#----------------------------------------------------------------------------- +# +# Test sh instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Basic tests + #------------------------------------------------------------- + + TEST_ST_OP( 2, lh, sh, 0x00000000000000aa, 0, tdat ); + TEST_ST_OP( 3, lh, sh, 0xffffffffffffaa00, 2, tdat ); + TEST_ST_OP( 4, lw, sh, 0xffffffffbeef0aa0, 4, tdat ); + TEST_ST_OP( 5, lh, sh, 0xffffffffffffa00a, 6, tdat ); + + # Test with negative offset + + TEST_ST_OP( 6, lh, sh, 0x00000000000000aa, -6, tdat8 ); + TEST_ST_OP( 7, lh, sh, 0xffffffffffffaa00, -4, tdat8 ); + TEST_ST_OP( 8, lh, sh, 0x0000000000000aa0, -2, tdat8 ); + TEST_ST_OP( 9, lh, sh, 0xffffffffffffa00a, 0, tdat8 ); + + # Test with a negative base + + TEST_CASE( 10, x5, 0x5678, \ + la x1, tdat9; \ + li x2, 0x12345678; \ + addi x4, x1, -32; \ + sh x2, 32(x4); \ + lh x5, 0(x1); \ + ) + + # Test with unaligned base + + TEST_CASE( 11, x5, 0x3098, \ + la x1, tdat9; \ + li x2, 0x00003098; \ + addi x1, x1, -5; \ + sh x2, 7(x1); \ + la x4, tdat10; \ + lh x5, 0(x4); \ + ) + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_ST_SRC12_BYPASS( 12, 0, 0, lh, sh, 0xffffffffffffccdd, 0, tdat ); + TEST_ST_SRC12_BYPASS( 13, 0, 1, lh, sh, 0xffffffffffffbccd, 2, tdat ); + TEST_ST_SRC12_BYPASS( 14, 0, 2, lh, sh, 0xffffffffffffbbcc, 4, tdat ); + TEST_ST_SRC12_BYPASS( 15, 1, 0, lh, sh, 0xffffffffffffabbc, 6, tdat ); + TEST_ST_SRC12_BYPASS( 16, 1, 1, lh, sh, 0xffffffffffffaabb, 8, tdat ); + TEST_ST_SRC12_BYPASS( 17, 2, 0, lh, sh, 0xffffffffffffdaab, 10, tdat ); + + TEST_ST_SRC21_BYPASS( 18, 0, 0, lh, sh, 0x2233, 0, tdat ); + TEST_ST_SRC21_BYPASS( 19, 0, 1, lh, sh, 0x1223, 2, tdat ); + TEST_ST_SRC21_BYPASS( 20, 0, 2, lh, sh, 0x1122, 4, tdat ); + TEST_ST_SRC21_BYPASS( 21, 1, 0, lh, sh, 0x0112, 6, tdat ); + TEST_ST_SRC21_BYPASS( 22, 1, 1, lh, sh, 0x0011, 8, tdat ); + TEST_ST_SRC21_BYPASS( 23, 2, 0, lh, sh, 0x3001, 10, tdat ); + + li a0, 0xbeef + la a1, tdat + sh a0, 6(a1) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +tdat: +tdat1: .half 0xbeef +tdat2: .half 0xbeef +tdat3: .half 0xbeef +tdat4: .half 0xbeef +tdat5: .half 0xbeef +tdat6: .half 0xbeef +tdat7: .half 0xbeef +tdat8: .half 0xbeef +tdat9: .half 0xbeef +tdat10: .half 0xbeef + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64ui/simple.S b/tb/qumcu/isa/rv64ui/simple.S new file mode 100644 index 0000000..6c45fbd --- /dev/null +++ b/tb/qumcu/isa/rv64ui/simple.S @@ -0,0 +1,27 @@ +# See LICENSE for license details. + +#***************************************************************************** +# simple.S +#----------------------------------------------------------------------------- +# +# This is the most basic self checking test. If your simulator does not +# pass thiss then there is little chance that it will pass any of the +# more complicated self checking tests. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + +RVTEST_PASS + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64ui/sll.S b/tb/qumcu/isa/rv64ui/sll.S new file mode 100644 index 0000000..8682743 --- /dev/null +++ b/tb/qumcu/isa/rv64ui/sll.S @@ -0,0 +1,96 @@ +# See LICENSE for license details. + +#***************************************************************************** +# sll.S +#----------------------------------------------------------------------------- +# +# Test sll instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, sll, 0x0000000000000001, 0x0000000000000001, 0 ); + TEST_RR_OP( 3, sll, 0x0000000000000002, 0x0000000000000001, 1 ); + TEST_RR_OP( 4, sll, 0x0000000000000080, 0x0000000000000001, 7 ); + TEST_RR_OP( 5, sll, 0x0000000000004000, 0x0000000000000001, 14 ); + TEST_RR_OP( 6, sll, 0x0000000080000000, 0x0000000000000001, 31 ); + + TEST_RR_OP( 7, sll, 0xffffffffffffffff, 0xffffffffffffffff, 0 ); + TEST_RR_OP( 8, sll, 0xfffffffffffffffe, 0xffffffffffffffff, 1 ); + TEST_RR_OP( 9, sll, 0xffffffffffffff80, 0xffffffffffffffff, 7 ); + TEST_RR_OP( 10, sll, 0xffffffffffffc000, 0xffffffffffffffff, 14 ); + TEST_RR_OP( 11, sll, 0xffffffff80000000, 0xffffffffffffffff, 31 ); + + TEST_RR_OP( 12, sll, 0x0000000021212121, 0x0000000021212121, 0 ); + TEST_RR_OP( 13, sll, 0x0000000042424242, 0x0000000021212121, 1 ); + TEST_RR_OP( 14, sll, 0x0000001090909080, 0x0000000021212121, 7 ); + TEST_RR_OP( 15, sll, 0x0000084848484000, 0x0000000021212121, 14 ); + TEST_RR_OP( 16, sll, 0x1090909080000000, 0x0000000021212121, 31 ); + + # Verify that shifts only use bottom six(rv64) or five(rv32) bits + + TEST_RR_OP( 17, sll, 0x0000000021212121, 0x0000000021212121, 0xffffffffffffffc0 ); + TEST_RR_OP( 18, sll, 0x0000000042424242, 0x0000000021212121, 0xffffffffffffffc1 ); + TEST_RR_OP( 19, sll, 0x0000001090909080, 0x0000000021212121, 0xffffffffffffffc7 ); + TEST_RR_OP( 20, sll, 0x0000084848484000, 0x0000000021212121, 0xffffffffffffffce ); + +#if __riscv_xlen == 64 + TEST_RR_OP( 21, sll, 0x8000000000000000, 0x0000000021212121, 0xffffffffffffffff ); + TEST_RR_OP( 50, sll, 0x8000000000000000, 0x0000000000000001, 63 ); + TEST_RR_OP( 51, sll, 0xffffff8000000000, 0xffffffffffffffff, 39 ); + TEST_RR_OP( 52, sll, 0x0909080000000000, 0x0000000021212121, 43 ); +#endif + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 22, sll, 0x00000080, 0x00000001, 7 ); + TEST_RR_SRC2_EQ_DEST( 23, sll, 0x00004000, 0x00000001, 14 ); + TEST_RR_SRC12_EQ_DEST( 24, sll, 24, 3 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 25, 0, sll, 0x0000000000000080, 0x0000000000000001, 7 ); + TEST_RR_DEST_BYPASS( 26, 1, sll, 0x0000000000004000, 0x0000000000000001, 14 ); + TEST_RR_DEST_BYPASS( 27, 2, sll, 0x0000000080000000, 0x0000000000000001, 31 ); + + TEST_RR_SRC12_BYPASS( 28, 0, 0, sll, 0x0000000000000080, 0x0000000000000001, 7 ); + TEST_RR_SRC12_BYPASS( 29, 0, 1, sll, 0x0000000000004000, 0x0000000000000001, 14 ); + TEST_RR_SRC12_BYPASS( 30, 0, 2, sll, 0x0000000080000000, 0x0000000000000001, 31 ); + TEST_RR_SRC12_BYPASS( 31, 1, 0, sll, 0x0000000000000080, 0x0000000000000001, 7 ); + TEST_RR_SRC12_BYPASS( 32, 1, 1, sll, 0x0000000000004000, 0x0000000000000001, 14 ); + TEST_RR_SRC12_BYPASS( 33, 2, 0, sll, 0x0000000080000000, 0x0000000000000001, 31 ); + + TEST_RR_SRC21_BYPASS( 34, 0, 0, sll, 0x0000000000000080, 0x0000000000000001, 7 ); + TEST_RR_SRC21_BYPASS( 35, 0, 1, sll, 0x0000000000004000, 0x0000000000000001, 14 ); + TEST_RR_SRC21_BYPASS( 36, 0, 2, sll, 0x0000000080000000, 0x0000000000000001, 31 ); + TEST_RR_SRC21_BYPASS( 37, 1, 0, sll, 0x0000000000000080, 0x0000000000000001, 7 ); + TEST_RR_SRC21_BYPASS( 38, 1, 1, sll, 0x0000000000004000, 0x0000000000000001, 14 ); + TEST_RR_SRC21_BYPASS( 39, 2, 0, sll, 0x0000000080000000, 0x0000000000000001, 31 ); + + TEST_RR_ZEROSRC1( 40, sll, 0, 15 ); + TEST_RR_ZEROSRC2( 41, sll, 32, 32 ); + TEST_RR_ZEROSRC12( 42, sll, 0 ); + TEST_RR_ZERODEST( 43, sll, 1024, 2048 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64ui/slli.S b/tb/qumcu/isa/rv64ui/slli.S new file mode 100644 index 0000000..b5341ad --- /dev/null +++ b/tb/qumcu/isa/rv64ui/slli.S @@ -0,0 +1,74 @@ +# See LICENSE for license details. + +#***************************************************************************** +# slli.S +#----------------------------------------------------------------------------- +# +# Test slli instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_IMM_OP( 2, slli, 0x0000000000000001, 0x0000000000000001, 0 ); + TEST_IMM_OP( 3, slli, 0x0000000000000002, 0x0000000000000001, 1 ); + TEST_IMM_OP( 4, slli, 0x0000000000000080, 0x0000000000000001, 7 ); + TEST_IMM_OP( 5, slli, 0x0000000000004000, 0x0000000000000001, 14 ); + TEST_IMM_OP( 6, slli, 0x0000000080000000, 0x0000000000000001, 31 ); + + TEST_IMM_OP( 7, slli, 0xffffffffffffffff, 0xffffffffffffffff, 0 ); + TEST_IMM_OP( 8, slli, 0xfffffffffffffffe, 0xffffffffffffffff, 1 ); + TEST_IMM_OP( 9, slli, 0xffffffffffffff80, 0xffffffffffffffff, 7 ); + TEST_IMM_OP( 10, slli, 0xffffffffffffc000, 0xffffffffffffffff, 14 ); + TEST_IMM_OP( 11, slli, 0xffffffff80000000, 0xffffffffffffffff, 31 ); + + TEST_IMM_OP( 12, slli, 0x0000000021212121, 0x0000000021212121, 0 ); + TEST_IMM_OP( 13, slli, 0x0000000042424242, 0x0000000021212121, 1 ); + TEST_IMM_OP( 14, slli, 0x0000001090909080, 0x0000000021212121, 7 ); + TEST_IMM_OP( 15, slli, 0x0000084848484000, 0x0000000021212121, 14 ); + TEST_IMM_OP( 16, slli, 0x1090909080000000, 0x0000000021212121, 31 ); + +#if __riscv_xlen == 64 + TEST_IMM_OP( 50, slli, 0x8000000000000000, 0x0000000000000001, 63 ); + TEST_IMM_OP( 51, slli, 0xffffff8000000000, 0xffffffffffffffff, 39 ); + TEST_IMM_OP( 52, slli, 0x0909080000000000, 0x0000000021212121, 43 ); +#endif + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_IMM_SRC1_EQ_DEST( 17, slli, 0x00000080, 0x00000001, 7 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_IMM_DEST_BYPASS( 18, 0, slli, 0x0000000000000080, 0x0000000000000001, 7 ); + TEST_IMM_DEST_BYPASS( 19, 1, slli, 0x0000000000004000, 0x0000000000000001, 14 ); + TEST_IMM_DEST_BYPASS( 20, 2, slli, 0x0000000080000000, 0x0000000000000001, 31 ); + + TEST_IMM_SRC1_BYPASS( 21, 0, slli, 0x0000000000000080, 0x0000000000000001, 7 ); + TEST_IMM_SRC1_BYPASS( 22, 1, slli, 0x0000000000004000, 0x0000000000000001, 14 ); + TEST_IMM_SRC1_BYPASS( 23, 2, slli, 0x0000000080000000, 0x0000000000000001, 31 ); + + TEST_IMM_ZEROSRC1( 24, slli, 0, 31 ); + TEST_IMM_ZERODEST( 25, slli, 33, 20 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64ui/slliw.S b/tb/qumcu/isa/rv64ui/slliw.S new file mode 100644 index 0000000..0ed888b --- /dev/null +++ b/tb/qumcu/isa/rv64ui/slliw.S @@ -0,0 +1,75 @@ +# See LICENSE for license details. + +#***************************************************************************** +# slliw.S +#----------------------------------------------------------------------------- +# +# Test slliw instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_IMM_OP( 2, slliw, 0x0000000000000001, 0x0000000000000001, 0 ); + TEST_IMM_OP( 3, slliw, 0x0000000000000002, 0x0000000000000001, 1 ); + TEST_IMM_OP( 4, slliw, 0x0000000000000080, 0x0000000000000001, 7 ); + TEST_IMM_OP( 5, slliw, 0x0000000000004000, 0x0000000000000001, 14 ); + TEST_IMM_OP( 6, slliw, 0xffffffff80000000, 0x0000000000000001, 31 ); + + TEST_IMM_OP( 7, slliw, 0xffffffffffffffff, 0xffffffffffffffff, 0 ); + TEST_IMM_OP( 8, slliw, 0xfffffffffffffffe, 0xffffffffffffffff, 1 ); + TEST_IMM_OP( 9, slliw, 0xffffffffffffff80, 0xffffffffffffffff, 7 ); + TEST_IMM_OP( 10, slliw, 0xffffffffffffc000, 0xffffffffffffffff, 14 ); + TEST_IMM_OP( 11, slliw, 0xffffffff80000000, 0xffffffffffffffff, 31 ); + + TEST_IMM_OP( 12, slliw, 0x0000000021212121, 0x0000000021212121, 0 ); + TEST_IMM_OP( 13, slliw, 0x0000000042424242, 0x0000000021212121, 1 ); + TEST_IMM_OP( 14, slliw, 0xffffffff90909080, 0x0000000021212121, 7 ); + TEST_IMM_OP( 15, slliw, 0x0000000048484000, 0x0000000021212121, 14 ); + TEST_IMM_OP( 16, slliw, 0xffffffff80000000, 0x0000000021212121, 31 ); + + # Verify that shifts ignore top 32 (using true 64-bit values) + + TEST_IMM_OP( 44, slliw, 0x0000000012345678, 0xffffffff12345678, 0 ); + TEST_IMM_OP( 45, slliw, 0x0000000023456780, 0xffffffff12345678, 4 ); + TEST_IMM_OP( 46, slliw, 0xffffffff92345678, 0x0000000092345678, 0 ); + TEST_IMM_OP( 47, slliw, 0xffffffff93456780, 0x0000000099345678, 4 ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_IMM_SRC1_EQ_DEST( 17, slliw, 0x00000080, 0x00000001, 7 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_IMM_DEST_BYPASS( 18, 0, slliw, 0x0000000000000080, 0x0000000000000001, 7 ); + TEST_IMM_DEST_BYPASS( 19, 1, slliw, 0x0000000000004000, 0x0000000000000001, 14 ); + TEST_IMM_DEST_BYPASS( 20, 2, slliw, 0xffffffff80000000, 0x0000000000000001, 31 ); + + TEST_IMM_SRC1_BYPASS( 21, 0, slliw, 0x0000000000000080, 0x0000000000000001, 7 ); + TEST_IMM_SRC1_BYPASS( 22, 1, slliw, 0x0000000000004000, 0x0000000000000001, 14 ); + TEST_IMM_SRC1_BYPASS( 23, 2, slliw, 0xffffffff80000000, 0x0000000000000001, 31 ); + + TEST_IMM_ZEROSRC1( 24, slliw, 0, 31 ); + TEST_IMM_ZERODEST( 25, slliw, 31, 28 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64ui/sllw.S b/tb/qumcu/isa/rv64ui/sllw.S new file mode 100644 index 0000000..62b4db6 --- /dev/null +++ b/tb/qumcu/isa/rv64ui/sllw.S @@ -0,0 +1,97 @@ +# See LICENSE for license details. + +#***************************************************************************** +# sllw.S +#----------------------------------------------------------------------------- +# +# Test sllw instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, sllw, 0x0000000000000001, 0x0000000000000001, 0 ); + TEST_RR_OP( 3, sllw, 0x0000000000000002, 0x0000000000000001, 1 ); + TEST_RR_OP( 4, sllw, 0x0000000000000080, 0x0000000000000001, 7 ); + TEST_RR_OP( 5, sllw, 0x0000000000004000, 0x0000000000000001, 14 ); + TEST_RR_OP( 6, sllw, 0xffffffff80000000, 0x0000000000000001, 31 ); + + TEST_RR_OP( 7, sllw, 0xffffffffffffffff, 0xffffffffffffffff, 0 ); + TEST_RR_OP( 8, sllw, 0xfffffffffffffffe, 0xffffffffffffffff, 1 ); + TEST_RR_OP( 9, sllw, 0xffffffffffffff80, 0xffffffffffffffff, 7 ); + TEST_RR_OP( 10, sllw, 0xffffffffffffc000, 0xffffffffffffffff, 14 ); + TEST_RR_OP( 11, sllw, 0xffffffff80000000, 0xffffffffffffffff, 31 ); + + TEST_RR_OP( 12, sllw, 0x0000000021212121, 0x0000000021212121, 0 ); + TEST_RR_OP( 13, sllw, 0x0000000042424242, 0x0000000021212121, 1 ); + TEST_RR_OP( 14, sllw, 0xffffffff90909080, 0x0000000021212121, 7 ); + TEST_RR_OP( 15, sllw, 0x0000000048484000, 0x0000000021212121, 14 ); + TEST_RR_OP( 16, sllw, 0xffffffff80000000, 0x0000000021212121, 31 ); + + # Verify that shifts only use bottom five bits + + TEST_RR_OP( 17, sllw, 0x0000000021212121, 0x0000000021212121, 0xffffffffffffffe0 ); + TEST_RR_OP( 18, sllw, 0x0000000042424242, 0x0000000021212121, 0xffffffffffffffe1 ); + TEST_RR_OP( 19, sllw, 0xffffffff90909080, 0x0000000021212121, 0xffffffffffffffe7 ); + TEST_RR_OP( 20, sllw, 0x0000000048484000, 0x0000000021212121, 0xffffffffffffffee ); + TEST_RR_OP( 21, sllw, 0xffffffff80000000, 0x0000000021212121, 0xffffffffffffffff ); + + # Verify that shifts ignore top 32 (using true 64-bit values) + + TEST_RR_OP( 44, sllw, 0x0000000012345678, 0xffffffff12345678, 0 ); + TEST_RR_OP( 45, sllw, 0x0000000023456780, 0xffffffff12345678, 4 ); + TEST_RR_OP( 46, sllw, 0xffffffff92345678, 0x0000000092345678, 0 ); + TEST_RR_OP( 47, sllw, 0xffffffff93456780, 0x0000000099345678, 4 ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 22, sllw, 0x00000080, 0x00000001, 7 ); + TEST_RR_SRC2_EQ_DEST( 23, sllw, 0x00004000, 0x00000001, 14 ); + TEST_RR_SRC12_EQ_DEST( 24, sllw, 24, 3 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 25, 0, sllw, 0x0000000000000080, 0x0000000000000001, 7 ); + TEST_RR_DEST_BYPASS( 26, 1, sllw, 0x0000000000004000, 0x0000000000000001, 14 ); + TEST_RR_DEST_BYPASS( 27, 2, sllw, 0xffffffff80000000, 0x0000000000000001, 31 ); + + TEST_RR_SRC12_BYPASS( 28, 0, 0, sllw, 0x0000000000000080, 0x0000000000000001, 7 ); + TEST_RR_SRC12_BYPASS( 29, 0, 1, sllw, 0x0000000000004000, 0x0000000000000001, 14 ); + TEST_RR_SRC12_BYPASS( 30, 0, 2, sllw, 0xffffffff80000000, 0x0000000000000001, 31 ); + TEST_RR_SRC12_BYPASS( 31, 1, 0, sllw, 0x0000000000000080, 0x0000000000000001, 7 ); + TEST_RR_SRC12_BYPASS( 32, 1, 1, sllw, 0x0000000000004000, 0x0000000000000001, 14 ); + TEST_RR_SRC12_BYPASS( 33, 2, 0, sllw, 0xffffffff80000000, 0x0000000000000001, 31 ); + + TEST_RR_SRC21_BYPASS( 34, 0, 0, sllw, 0x0000000000000080, 0x0000000000000001, 7 ); + TEST_RR_SRC21_BYPASS( 35, 0, 1, sllw, 0x0000000000004000, 0x0000000000000001, 14 ); + TEST_RR_SRC21_BYPASS( 36, 0, 2, sllw, 0xffffffff80000000, 0x0000000000000001, 31 ); + TEST_RR_SRC21_BYPASS( 37, 1, 0, sllw, 0x0000000000000080, 0x0000000000000001, 7 ); + TEST_RR_SRC21_BYPASS( 38, 1, 1, sllw, 0x0000000000004000, 0x0000000000000001, 14 ); + TEST_RR_SRC21_BYPASS( 39, 2, 0, sllw, 0xffffffff80000000, 0x0000000000000001, 31 ); + + TEST_RR_ZEROSRC1( 40, sllw, 0, 15 ); + TEST_RR_ZEROSRC2( 41, sllw, 32, 32 ); + TEST_RR_ZEROSRC12( 42, sllw, 0 ); + TEST_RR_ZERODEST( 43, sllw, 1024, 2048 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64ui/slt.S b/tb/qumcu/isa/rv64ui/slt.S new file mode 100644 index 0000000..644a51a --- /dev/null +++ b/tb/qumcu/isa/rv64ui/slt.S @@ -0,0 +1,84 @@ +# See LICENSE for license details. + +#***************************************************************************** +# slt.S +#----------------------------------------------------------------------------- +# +# Test slt instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, slt, 0, 0x0000000000000000, 0x0000000000000000 ); + TEST_RR_OP( 3, slt, 0, 0x0000000000000001, 0x0000000000000001 ); + TEST_RR_OP( 4, slt, 1, 0x0000000000000003, 0x0000000000000007 ); + TEST_RR_OP( 5, slt, 0, 0x0000000000000007, 0x0000000000000003 ); + + TEST_RR_OP( 6, slt, 0, 0x0000000000000000, 0xffffffffffff8000 ); + TEST_RR_OP( 7, slt, 1, 0xffffffff80000000, 0x0000000000000000 ); + TEST_RR_OP( 8, slt, 1, 0xffffffff80000000, 0xffffffffffff8000 ); + + TEST_RR_OP( 9, slt, 1, 0x0000000000000000, 0x0000000000007fff ); + TEST_RR_OP( 10, slt, 0, 0x000000007fffffff, 0x0000000000000000 ); + TEST_RR_OP( 11, slt, 0, 0x000000007fffffff, 0x0000000000007fff ); + + TEST_RR_OP( 12, slt, 1, 0xffffffff80000000, 0x0000000000007fff ); + TEST_RR_OP( 13, slt, 0, 0x000000007fffffff, 0xffffffffffff8000 ); + + TEST_RR_OP( 14, slt, 0, 0x0000000000000000, 0xffffffffffffffff ); + TEST_RR_OP( 15, slt, 1, 0xffffffffffffffff, 0x0000000000000001 ); + TEST_RR_OP( 16, slt, 0, 0xffffffffffffffff, 0xffffffffffffffff ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 17, slt, 0, 14, 13 ); + TEST_RR_SRC2_EQ_DEST( 18, slt, 1, 11, 13 ); + TEST_RR_SRC12_EQ_DEST( 19, slt, 0, 13 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 20, 0, slt, 1, 11, 13 ); + TEST_RR_DEST_BYPASS( 21, 1, slt, 0, 14, 13 ); + TEST_RR_DEST_BYPASS( 22, 2, slt, 1, 12, 13 ); + + TEST_RR_SRC12_BYPASS( 23, 0, 0, slt, 0, 14, 13 ); + TEST_RR_SRC12_BYPASS( 24, 0, 1, slt, 1, 11, 13 ); + TEST_RR_SRC12_BYPASS( 25, 0, 2, slt, 0, 15, 13 ); + TEST_RR_SRC12_BYPASS( 26, 1, 0, slt, 1, 10, 13 ); + TEST_RR_SRC12_BYPASS( 27, 1, 1, slt, 0, 16, 13 ); + TEST_RR_SRC12_BYPASS( 28, 2, 0, slt, 1, 9, 13 ); + + TEST_RR_SRC21_BYPASS( 29, 0, 0, slt, 0, 17, 13 ); + TEST_RR_SRC21_BYPASS( 30, 0, 1, slt, 1, 8, 13 ); + TEST_RR_SRC21_BYPASS( 31, 0, 2, slt, 0, 18, 13 ); + TEST_RR_SRC21_BYPASS( 32, 1, 0, slt, 1, 7, 13 ); + TEST_RR_SRC21_BYPASS( 33, 1, 1, slt, 0, 19, 13 ); + TEST_RR_SRC21_BYPASS( 34, 2, 0, slt, 1, 6, 13 ); + + TEST_RR_ZEROSRC1( 35, slt, 0, -1 ); + TEST_RR_ZEROSRC2( 36, slt, 1, -1 ); + TEST_RR_ZEROSRC12( 37, slt, 0 ); + TEST_RR_ZERODEST( 38, slt, 16, 30 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64ui/slti.S b/tb/qumcu/isa/rv64ui/slti.S new file mode 100644 index 0000000..9222fa4 --- /dev/null +++ b/tb/qumcu/isa/rv64ui/slti.S @@ -0,0 +1,70 @@ +# See LICENSE for license details. + +#***************************************************************************** +# slti.S +#----------------------------------------------------------------------------- +# +# Test slti instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_IMM_OP( 2, slti, 0, 0x0000000000000000, 0x000 ); + TEST_IMM_OP( 3, slti, 0, 0x0000000000000001, 0x001 ); + TEST_IMM_OP( 4, slti, 1, 0x0000000000000003, 0x007 ); + TEST_IMM_OP( 5, slti, 0, 0x0000000000000007, 0x003 ); + + TEST_IMM_OP( 6, slti, 0, 0x0000000000000000, 0x800 ); + TEST_IMM_OP( 7, slti, 1, 0xffffffff80000000, 0x000 ); + TEST_IMM_OP( 8, slti, 1, 0xffffffff80000000, 0x800 ); + + TEST_IMM_OP( 9, slti, 1, 0x0000000000000000, 0x7ff ); + TEST_IMM_OP( 10, slti, 0, 0x000000007fffffff, 0x000 ); + TEST_IMM_OP( 11, slti, 0, 0x000000007fffffff, 0x7ff ); + + TEST_IMM_OP( 12, slti, 1, 0xffffffff80000000, 0x7ff ); + TEST_IMM_OP( 13, slti, 0, 0x000000007fffffff, 0x800 ); + + TEST_IMM_OP( 14, slti, 0, 0x0000000000000000, 0xfff ); + TEST_IMM_OP( 15, slti, 1, 0xffffffffffffffff, 0x001 ); + TEST_IMM_OP( 16, slti, 0, 0xffffffffffffffff, 0xfff ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_IMM_SRC1_EQ_DEST( 17, slti, 1, 11, 13 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_IMM_DEST_BYPASS( 18, 0, slti, 0, 15, 10 ); + TEST_IMM_DEST_BYPASS( 19, 1, slti, 1, 10, 16 ); + TEST_IMM_DEST_BYPASS( 20, 2, slti, 0, 16, 9 ); + + TEST_IMM_SRC1_BYPASS( 21, 0, slti, 1, 11, 15 ); + TEST_IMM_SRC1_BYPASS( 22, 1, slti, 0, 17, 8 ); + TEST_IMM_SRC1_BYPASS( 23, 2, slti, 1, 12, 14 ); + + TEST_IMM_ZEROSRC1( 24, slti, 0, 0xfff ); + TEST_IMM_ZERODEST( 25, slti, 0x00ff00ff, 0xfff ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64ui/sltiu.S b/tb/qumcu/isa/rv64ui/sltiu.S new file mode 100644 index 0000000..f6a719b --- /dev/null +++ b/tb/qumcu/isa/rv64ui/sltiu.S @@ -0,0 +1,70 @@ +# See LICENSE for license details. + +#***************************************************************************** +# sltiu.S +#----------------------------------------------------------------------------- +# +# Test sltiu instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_IMM_OP( 2, sltiu, 0, 0x0000000000000000, 0x000 ); + TEST_IMM_OP( 3, sltiu, 0, 0x0000000000000001, 0x001 ); + TEST_IMM_OP( 4, sltiu, 1, 0x0000000000000003, 0x007 ); + TEST_IMM_OP( 5, sltiu, 0, 0x0000000000000007, 0x003 ); + + TEST_IMM_OP( 6, sltiu, 1, 0x0000000000000000, 0x800 ); + TEST_IMM_OP( 7, sltiu, 0, 0xffffffff80000000, 0x000 ); + TEST_IMM_OP( 8, sltiu, 1, 0xffffffff80000000, 0x800 ); + + TEST_IMM_OP( 9, sltiu, 1, 0x0000000000000000, 0x7ff ); + TEST_IMM_OP( 10, sltiu, 0, 0x000000007fffffff, 0x000 ); + TEST_IMM_OP( 11, sltiu, 0, 0x000000007fffffff, 0x7ff ); + + TEST_IMM_OP( 12, sltiu, 0, 0xffffffff80000000, 0x7ff ); + TEST_IMM_OP( 13, sltiu, 1, 0x000000007fffffff, 0x800 ); + + TEST_IMM_OP( 14, sltiu, 1, 0x0000000000000000, 0xfff ); + TEST_IMM_OP( 15, sltiu, 0, 0xffffffffffffffff, 0x001 ); + TEST_IMM_OP( 16, sltiu, 0, 0xffffffffffffffff, 0xfff ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_IMM_SRC1_EQ_DEST( 17, sltiu, 1, 11, 13 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_IMM_DEST_BYPASS( 18, 0, sltiu, 0, 15, 10 ); + TEST_IMM_DEST_BYPASS( 19, 1, sltiu, 1, 10, 16 ); + TEST_IMM_DEST_BYPASS( 20, 2, sltiu, 0, 16, 9 ); + + TEST_IMM_SRC1_BYPASS( 21, 0, sltiu, 1, 11, 15 ); + TEST_IMM_SRC1_BYPASS( 22, 1, sltiu, 0, 17, 8 ); + TEST_IMM_SRC1_BYPASS( 23, 2, sltiu, 1, 12, 14 ); + + TEST_IMM_ZEROSRC1( 24, sltiu, 1, 0xfff ); + TEST_IMM_ZERODEST( 25, sltiu, 0x00ff00ff, 0xfff ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64ui/sltu.S b/tb/qumcu/isa/rv64ui/sltu.S new file mode 100644 index 0000000..52ff685 --- /dev/null +++ b/tb/qumcu/isa/rv64ui/sltu.S @@ -0,0 +1,84 @@ +# See LICENSE for license details. + +#***************************************************************************** +# sltu.S +#----------------------------------------------------------------------------- +# +# Test sltu instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, sltu, 0, 0x00000000, 0x00000000 ); + TEST_RR_OP( 3, sltu, 0, 0x00000001, 0x00000001 ); + TEST_RR_OP( 4, sltu, 1, 0x00000003, 0x00000007 ); + TEST_RR_OP( 5, sltu, 0, 0x00000007, 0x00000003 ); + + TEST_RR_OP( 6, sltu, 1, 0x00000000, 0xffff8000 ); + TEST_RR_OP( 7, sltu, 0, 0x80000000, 0x00000000 ); + TEST_RR_OP( 8, sltu, 1, 0x80000000, 0xffff8000 ); + + TEST_RR_OP( 9, sltu, 1, 0x00000000, 0x00007fff ); + TEST_RR_OP( 10, sltu, 0, 0x7fffffff, 0x00000000 ); + TEST_RR_OP( 11, sltu, 0, 0x7fffffff, 0x00007fff ); + + TEST_RR_OP( 12, sltu, 0, 0x80000000, 0x00007fff ); + TEST_RR_OP( 13, sltu, 1, 0x7fffffff, 0xffff8000 ); + + TEST_RR_OP( 14, sltu, 1, 0x00000000, 0xffffffff ); + TEST_RR_OP( 15, sltu, 0, 0xffffffff, 0x00000001 ); + TEST_RR_OP( 16, sltu, 0, 0xffffffff, 0xffffffff ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 17, sltu, 0, 14, 13 ); + TEST_RR_SRC2_EQ_DEST( 18, sltu, 1, 11, 13 ); + TEST_RR_SRC12_EQ_DEST( 19, sltu, 0, 13 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 20, 0, sltu, 1, 11, 13 ); + TEST_RR_DEST_BYPASS( 21, 1, sltu, 0, 14, 13 ); + TEST_RR_DEST_BYPASS( 22, 2, sltu, 1, 12, 13 ); + + TEST_RR_SRC12_BYPASS( 23, 0, 0, sltu, 0, 14, 13 ); + TEST_RR_SRC12_BYPASS( 24, 0, 1, sltu, 1, 11, 13 ); + TEST_RR_SRC12_BYPASS( 25, 0, 2, sltu, 0, 15, 13 ); + TEST_RR_SRC12_BYPASS( 26, 1, 0, sltu, 1, 10, 13 ); + TEST_RR_SRC12_BYPASS( 27, 1, 1, sltu, 0, 16, 13 ); + TEST_RR_SRC12_BYPASS( 28, 2, 0, sltu, 1, 9, 13 ); + + TEST_RR_SRC21_BYPASS( 29, 0, 0, sltu, 0, 17, 13 ); + TEST_RR_SRC21_BYPASS( 30, 0, 1, sltu, 1, 8, 13 ); + TEST_RR_SRC21_BYPASS( 31, 0, 2, sltu, 0, 18, 13 ); + TEST_RR_SRC21_BYPASS( 32, 1, 0, sltu, 1, 7, 13 ); + TEST_RR_SRC21_BYPASS( 33, 1, 1, sltu, 0, 19, 13 ); + TEST_RR_SRC21_BYPASS( 34, 2, 0, sltu, 1, 6, 13 ); + + TEST_RR_ZEROSRC1( 35, sltu, 1, -1 ); + TEST_RR_ZEROSRC2( 36, sltu, 0, -1 ); + TEST_RR_ZEROSRC12( 37, sltu, 0 ); + TEST_RR_ZERODEST( 38, sltu, 16, 30 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64ui/sra.S b/tb/qumcu/isa/rv64ui/sra.S new file mode 100644 index 0000000..580ae89 --- /dev/null +++ b/tb/qumcu/isa/rv64ui/sra.S @@ -0,0 +1,90 @@ +# See LICENSE for license details. + +#***************************************************************************** +# sra.S +#----------------------------------------------------------------------------- +# +# Test sra instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, sra, 0xffffffff80000000, 0xffffffff80000000, 0 ); + TEST_RR_OP( 3, sra, 0xffffffffc0000000, 0xffffffff80000000, 1 ); + TEST_RR_OP( 4, sra, 0xffffffffff000000, 0xffffffff80000000, 7 ); + TEST_RR_OP( 5, sra, 0xfffffffffffe0000, 0xffffffff80000000, 14 ); + TEST_RR_OP( 6, sra, 0xffffffffffffffff, 0xffffffff80000001, 31 ); + + TEST_RR_OP( 7, sra, 0x000000007fffffff, 0x000000007fffffff, 0 ); + TEST_RR_OP( 8, sra, 0x000000003fffffff, 0x000000007fffffff, 1 ); + TEST_RR_OP( 9, sra, 0x0000000000ffffff, 0x000000007fffffff, 7 ); + TEST_RR_OP( 10, sra, 0x000000000001ffff, 0x000000007fffffff, 14 ); + TEST_RR_OP( 11, sra, 0x0000000000000000, 0x000000007fffffff, 31 ); + + TEST_RR_OP( 12, sra, 0xffffffff81818181, 0xffffffff81818181, 0 ); + TEST_RR_OP( 13, sra, 0xffffffffc0c0c0c0, 0xffffffff81818181, 1 ); + TEST_RR_OP( 14, sra, 0xffffffffff030303, 0xffffffff81818181, 7 ); + TEST_RR_OP( 15, sra, 0xfffffffffffe0606, 0xffffffff81818181, 14 ); + TEST_RR_OP( 16, sra, 0xffffffffffffffff, 0xffffffff81818181, 31 ); + + # Verify that shifts only use bottom six(rv64) or five(rv32) bits + + TEST_RR_OP( 17, sra, 0xffffffff81818181, 0xffffffff81818181, 0xffffffffffffffc0 ); + TEST_RR_OP( 18, sra, 0xffffffffc0c0c0c0, 0xffffffff81818181, 0xffffffffffffffc1 ); + TEST_RR_OP( 19, sra, 0xffffffffff030303, 0xffffffff81818181, 0xffffffffffffffc7 ); + TEST_RR_OP( 20, sra, 0xfffffffffffe0606, 0xffffffff81818181, 0xffffffffffffffce ); + TEST_RR_OP( 21, sra, 0xffffffffffffffff, 0xffffffff81818181, 0xffffffffffffffff ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 22, sra, 0xffffffffff000000, 0xffffffff80000000, 7 ); + TEST_RR_SRC2_EQ_DEST( 23, sra, 0xfffffffffffe0000, 0xffffffff80000000, 14 ); + TEST_RR_SRC12_EQ_DEST( 24, sra, 0, 7 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 25, 0, sra, 0xffffffffff000000, 0xffffffff80000000, 7 ); + TEST_RR_DEST_BYPASS( 26, 1, sra, 0xfffffffffffe0000, 0xffffffff80000000, 14 ); + TEST_RR_DEST_BYPASS( 27, 2, sra, 0xffffffffffffffff, 0xffffffff80000000, 31 ); + + TEST_RR_SRC12_BYPASS( 28, 0, 0, sra, 0xffffffffff000000, 0xffffffff80000000, 7 ); + TEST_RR_SRC12_BYPASS( 29, 0, 1, sra, 0xfffffffffffe0000, 0xffffffff80000000, 14 ); + TEST_RR_SRC12_BYPASS( 30, 0, 2, sra, 0xffffffffffffffff, 0xffffffff80000000, 31 ); + TEST_RR_SRC12_BYPASS( 31, 1, 0, sra, 0xffffffffff000000, 0xffffffff80000000, 7 ); + TEST_RR_SRC12_BYPASS( 32, 1, 1, sra, 0xfffffffffffe0000, 0xffffffff80000000, 14 ); + TEST_RR_SRC12_BYPASS( 33, 2, 0, sra, 0xffffffffffffffff, 0xffffffff80000000, 31 ); + + TEST_RR_SRC21_BYPASS( 34, 0, 0, sra, 0xffffffffff000000, 0xffffffff80000000, 7 ); + TEST_RR_SRC21_BYPASS( 35, 0, 1, sra, 0xfffffffffffe0000, 0xffffffff80000000, 14 ); + TEST_RR_SRC21_BYPASS( 36, 0, 2, sra, 0xffffffffffffffff, 0xffffffff80000000, 31 ); + TEST_RR_SRC21_BYPASS( 37, 1, 0, sra, 0xffffffffff000000, 0xffffffff80000000, 7 ); + TEST_RR_SRC21_BYPASS( 38, 1, 1, sra, 0xfffffffffffe0000, 0xffffffff80000000, 14 ); + TEST_RR_SRC21_BYPASS( 39, 2, 0, sra, 0xffffffffffffffff, 0xffffffff80000000, 31 ); + + TEST_RR_ZEROSRC1( 40, sra, 0, 15 ); + TEST_RR_ZEROSRC2( 41, sra, 32, 32 ); + TEST_RR_ZEROSRC12( 42, sra, 0 ); + TEST_RR_ZERODEST( 43, sra, 1024, 2048 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64ui/srai.S b/tb/qumcu/isa/rv64ui/srai.S new file mode 100644 index 0000000..8d05213 --- /dev/null +++ b/tb/qumcu/isa/rv64ui/srai.S @@ -0,0 +1,68 @@ +# See LICENSE for license details. + +#***************************************************************************** +# srai.S +#----------------------------------------------------------------------------- +# +# Test srai instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_IMM_OP( 2, srai, 0xffffff8000000000, 0xffffff8000000000, 0 ); + TEST_IMM_OP( 3, srai, 0xffffffffc0000000, 0xffffffff80000000, 1 ); + TEST_IMM_OP( 4, srai, 0xffffffffff000000, 0xffffffff80000000, 7 ); + TEST_IMM_OP( 5, srai, 0xfffffffffffe0000, 0xffffffff80000000, 14 ); + TEST_IMM_OP( 6, srai, 0xffffffffffffffff, 0xffffffff80000001, 31 ); + + TEST_IMM_OP( 7, srai, 0x000000007fffffff, 0x000000007fffffff, 0 ); + TEST_IMM_OP( 8, srai, 0x000000003fffffff, 0x000000007fffffff, 1 ); + TEST_IMM_OP( 9, srai, 0x0000000000ffffff, 0x000000007fffffff, 7 ); + TEST_IMM_OP( 10, srai, 0x000000000001ffff, 0x000000007fffffff, 14 ); + TEST_IMM_OP( 11, srai, 0x0000000000000000, 0x000000007fffffff, 31 ); + + TEST_IMM_OP( 12, srai, 0xffffffff81818181, 0xffffffff81818181, 0 ); + TEST_IMM_OP( 13, srai, 0xffffffffc0c0c0c0, 0xffffffff81818181, 1 ); + TEST_IMM_OP( 14, srai, 0xffffffffff030303, 0xffffffff81818181, 7 ); + TEST_IMM_OP( 15, srai, 0xfffffffffffe0606, 0xffffffff81818181, 14 ); + TEST_IMM_OP( 16, srai, 0xffffffffffffffff, 0xffffffff81818181, 31 ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_IMM_SRC1_EQ_DEST( 17, srai, 0xffffffffff000000, 0xffffffff80000000, 7 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_IMM_DEST_BYPASS( 18, 0, srai, 0xffffffffff000000, 0xffffffff80000000, 7 ); + TEST_IMM_DEST_BYPASS( 19, 1, srai, 0xfffffffffffe0000, 0xffffffff80000000, 14 ); + TEST_IMM_DEST_BYPASS( 20, 2, srai, 0xffffffffffffffff, 0xffffffff80000001, 31 ); + + TEST_IMM_SRC1_BYPASS( 21, 0, srai, 0xffffffffff000000, 0xffffffff80000000, 7 ); + TEST_IMM_SRC1_BYPASS( 22, 1, srai, 0xfffffffffffe0000, 0xffffffff80000000, 14 ); + TEST_IMM_SRC1_BYPASS( 23, 2, srai, 0xffffffffffffffff, 0xffffffff80000001, 31 ); + + TEST_IMM_ZEROSRC1( 24, srai, 0, 4 ); + TEST_IMM_ZERODEST( 25, srai, 33, 10 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64ui/sraiw.S b/tb/qumcu/isa/rv64ui/sraiw.S new file mode 100644 index 0000000..a435e59 --- /dev/null +++ b/tb/qumcu/isa/rv64ui/sraiw.S @@ -0,0 +1,78 @@ +# See LICENSE for license details. + +#***************************************************************************** +# sraiw.S +#----------------------------------------------------------------------------- +# +# Test sraiw instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_IMM_OP( 2, sraiw, 0xffffffff80000000, 0xffffffff80000000, 0 ); + TEST_IMM_OP( 3, sraiw, 0xffffffffc0000000, 0xffffffff80000000, 1 ); + TEST_IMM_OP( 4, sraiw, 0xffffffffff000000, 0xffffffff80000000, 7 ); + TEST_IMM_OP( 5, sraiw, 0xfffffffffffe0000, 0xffffffff80000000, 14 ); + TEST_IMM_OP( 6, sraiw, 0xffffffffffffffff, 0xffffffff80000001, 31 ); + + TEST_IMM_OP( 7, sraiw, 0x000000007fffffff, 0x000000007fffffff, 0 ); + TEST_IMM_OP( 8, sraiw, 0x000000003fffffff, 0x000000007fffffff, 1 ); + TEST_IMM_OP( 9, sraiw, 0x0000000000ffffff, 0x000000007fffffff, 7 ); + TEST_IMM_OP( 10, sraiw, 0x000000000001ffff, 0x000000007fffffff, 14 ); + TEST_IMM_OP( 11, sraiw, 0x0000000000000000, 0x000000007fffffff, 31 ); + + TEST_IMM_OP( 12, sraiw, 0xffffffff81818181, 0xffffffff81818181, 0 ); + TEST_IMM_OP( 13, sraiw, 0xffffffffc0c0c0c0, 0xffffffff81818181, 1 ); + TEST_IMM_OP( 14, sraiw, 0xffffffffff030303, 0xffffffff81818181, 7 ); + TEST_IMM_OP( 15, sraiw, 0xfffffffffffe0606, 0xffffffff81818181, 14 ); + TEST_IMM_OP( 16, sraiw, 0xffffffffffffffff, 0xffffffff81818181, 31 ); + + # Verify that shifts ignore top 32 (using true 64-bit values) + + TEST_IMM_OP( 44, sraiw, 0x0000000012345678, 0xffffffff12345678, 0 ); + TEST_IMM_OP( 45, sraiw, 0x0000000001234567, 0xffffffff12345678, 4 ); + TEST_IMM_OP( 46, sraiw, 0xffffffff92345678, 0x0000000092345678, 0 ); + TEST_IMM_OP( 47, sraiw, 0xfffffffff9234567, 0x0000000092345678, 4 ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_IMM_SRC1_EQ_DEST( 17, sraiw, 0xffffffffff000000, 0xffffffff80000000, 7 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_IMM_DEST_BYPASS( 18, 0, sraiw, 0xffffffffff000000, 0xffffffff80000000, 7 ); + TEST_IMM_DEST_BYPASS( 19, 1, sraiw, 0xfffffffffffe0000, 0xffffffff80000000, 14 ); + TEST_IMM_DEST_BYPASS( 20, 2, sraiw, 0xffffffffffffffff, 0xffffffff80000001, 31 ); + + TEST_IMM_SRC1_BYPASS( 21, 0, sraiw, 0xffffffffff000000, 0xffffffff80000000, 7 ); + TEST_IMM_SRC1_BYPASS( 22, 1, sraiw, 0xfffffffffffe0000, 0xffffffff80000000, 14 ); + TEST_IMM_SRC1_BYPASS( 23, 2, sraiw, 0xffffffffffffffff, 0xffffffff80000001, 31 ); + + TEST_IMM_ZEROSRC1( 24, sraiw, 0, 31 ); + TEST_IMM_ZERODEST( 25, sraiw, 31, 28 ); + + TEST_IMM_OP( 26, sraiw, 0x0000000000000000, 0x00e0000000000000, 28) + TEST_IMM_OP( 27, sraiw, 0xffffffffff000000, 0x00000000f0000000, 4) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64ui/sraw.S b/tb/qumcu/isa/rv64ui/sraw.S new file mode 100644 index 0000000..68d913e --- /dev/null +++ b/tb/qumcu/isa/rv64ui/sraw.S @@ -0,0 +1,97 @@ +# See LICENSE for license details. + +#***************************************************************************** +# sraw.S +#----------------------------------------------------------------------------- +# +# Test sraw instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, sraw, 0xffffffff80000000, 0xffffffff80000000, 0 ); + TEST_RR_OP( 3, sraw, 0xffffffffc0000000, 0xffffffff80000000, 1 ); + TEST_RR_OP( 4, sraw, 0xffffffffff000000, 0xffffffff80000000, 7 ); + TEST_RR_OP( 5, sraw, 0xfffffffffffe0000, 0xffffffff80000000, 14 ); + TEST_RR_OP( 6, sraw, 0xffffffffffffffff, 0xffffffff80000001, 31 ); + + TEST_RR_OP( 7, sraw, 0x000000007fffffff, 0x000000007fffffff, 0 ); + TEST_RR_OP( 8, sraw, 0x000000003fffffff, 0x000000007fffffff, 1 ); + TEST_RR_OP( 9, sraw, 0x0000000000ffffff, 0x000000007fffffff, 7 ); + TEST_RR_OP( 10, sraw, 0x000000000001ffff, 0x000000007fffffff, 14 ); + TEST_RR_OP( 11, sraw, 0x0000000000000000, 0x000000007fffffff, 31 ); + + TEST_RR_OP( 12, sraw, 0xffffffff81818181, 0xffffffff81818181, 0 ); + TEST_RR_OP( 13, sraw, 0xffffffffc0c0c0c0, 0xffffffff81818181, 1 ); + TEST_RR_OP( 14, sraw, 0xffffffffff030303, 0xffffffff81818181, 7 ); + TEST_RR_OP( 15, sraw, 0xfffffffffffe0606, 0xffffffff81818181, 14 ); + TEST_RR_OP( 16, sraw, 0xffffffffffffffff, 0xffffffff81818181, 31 ); + + # Verify that shifts only use bottom five bits + + TEST_RR_OP( 17, sraw, 0xffffffff81818181, 0xffffffff81818181, 0xffffffffffffffe0 ); + TEST_RR_OP( 18, sraw, 0xffffffffc0c0c0c0, 0xffffffff81818181, 0xffffffffffffffe1 ); + TEST_RR_OP( 19, sraw, 0xffffffffff030303, 0xffffffff81818181, 0xffffffffffffffe7 ); + TEST_RR_OP( 20, sraw, 0xfffffffffffe0606, 0xffffffff81818181, 0xffffffffffffffee ); + TEST_RR_OP( 21, sraw, 0xffffffffffffffff, 0xffffffff81818181, 0xffffffffffffffff ); + + # Verify that shifts ignore top 32 (using true 64-bit values) + + TEST_RR_OP( 44, sraw, 0x0000000012345678, 0xffffffff12345678, 0 ); + TEST_RR_OP( 45, sraw, 0x0000000001234567, 0xffffffff12345678, 4 ); + TEST_RR_OP( 46, sraw, 0xffffffff92345678, 0x0000000092345678, 0 ); + TEST_RR_OP( 47, sraw, 0xfffffffff9234567, 0x0000000092345678, 4 ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 22, sraw, 0xffffffffff000000, 0xffffffff80000000, 7 ); + TEST_RR_SRC2_EQ_DEST( 23, sraw, 0xfffffffffffe0000, 0xffffffff80000000, 14 ); + TEST_RR_SRC12_EQ_DEST( 24, sraw, 0, 7 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 25, 0, sraw, 0xffffffffff000000, 0xffffffff80000000, 7 ); + TEST_RR_DEST_BYPASS( 26, 1, sraw, 0xfffffffffffe0000, 0xffffffff80000000, 14 ); + TEST_RR_DEST_BYPASS( 27, 2, sraw, 0xffffffffffffffff, 0xffffffff80000000, 31 ); + + TEST_RR_SRC12_BYPASS( 28, 0, 0, sraw, 0xffffffffff000000, 0xffffffff80000000, 7 ); + TEST_RR_SRC12_BYPASS( 29, 0, 1, sraw, 0xfffffffffffe0000, 0xffffffff80000000, 14 ); + TEST_RR_SRC12_BYPASS( 30, 0, 2, sraw, 0xffffffffffffffff, 0xffffffff80000000, 31 ); + TEST_RR_SRC12_BYPASS( 31, 1, 0, sraw, 0xffffffffff000000, 0xffffffff80000000, 7 ); + TEST_RR_SRC12_BYPASS( 32, 1, 1, sraw, 0xfffffffffffe0000, 0xffffffff80000000, 14 ); + TEST_RR_SRC12_BYPASS( 33, 2, 0, sraw, 0xffffffffffffffff, 0xffffffff80000000, 31 ); + + TEST_RR_SRC21_BYPASS( 34, 0, 0, sraw, 0xffffffffff000000, 0xffffffff80000000, 7 ); + TEST_RR_SRC21_BYPASS( 35, 0, 1, sraw, 0xfffffffffffe0000, 0xffffffff80000000, 14 ); + TEST_RR_SRC21_BYPASS( 36, 0, 2, sraw, 0xffffffffffffffff, 0xffffffff80000000, 31 ); + TEST_RR_SRC21_BYPASS( 37, 1, 0, sraw, 0xffffffffff000000, 0xffffffff80000000, 7 ); + TEST_RR_SRC21_BYPASS( 38, 1, 1, sraw, 0xfffffffffffe0000, 0xffffffff80000000, 14 ); + TEST_RR_SRC21_BYPASS( 39, 2, 0, sraw, 0xffffffffffffffff, 0xffffffff80000000, 31 ); + + TEST_RR_ZEROSRC1( 40, sraw, 0, 15 ); + TEST_RR_ZEROSRC2( 41, sraw, 32, 32 ); + TEST_RR_ZEROSRC12( 42, sraw, 0 ); + TEST_RR_ZERODEST( 43, sraw, 1024, 2048 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64ui/srl.S b/tb/qumcu/isa/rv64ui/srl.S new file mode 100644 index 0000000..5ee223f --- /dev/null +++ b/tb/qumcu/isa/rv64ui/srl.S @@ -0,0 +1,93 @@ +# See LICENSE for license details. + +#***************************************************************************** +# srl.S +#----------------------------------------------------------------------------- +# +# Test srl instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + +#define TEST_SRL(n, v, a) \ + TEST_RR_OP(n, srl, ((v) & ((1 << (__riscv_xlen-1) << 1) - 1)) >> (a), v, a) + + TEST_SRL( 2, 0xffffffff80000000, 0 ); + TEST_SRL( 3, 0xffffffff80000000, 1 ); + TEST_SRL( 4, 0xffffffff80000000, 7 ); + TEST_SRL( 5, 0xffffffff80000000, 14 ); + TEST_SRL( 6, 0xffffffff80000001, 31 ); + + TEST_SRL( 7, 0xffffffffffffffff, 0 ); + TEST_SRL( 8, 0xffffffffffffffff, 1 ); + TEST_SRL( 9, 0xffffffffffffffff, 7 ); + TEST_SRL( 10, 0xffffffffffffffff, 14 ); + TEST_SRL( 11, 0xffffffffffffffff, 31 ); + + TEST_SRL( 12, 0x0000000021212121, 0 ); + TEST_SRL( 13, 0x0000000021212121, 1 ); + TEST_SRL( 14, 0x0000000021212121, 7 ); + TEST_SRL( 15, 0x0000000021212121, 14 ); + TEST_SRL( 16, 0x0000000021212121, 31 ); + + # Verify that shifts only use bottom six(rv64) or five(rv32) bits + + TEST_RR_OP( 17, srl, 0x0000000021212121, 0x0000000021212121, 0xffffffffffffffc0 ); + TEST_RR_OP( 18, srl, 0x0000000010909090, 0x0000000021212121, 0xffffffffffffffc1 ); + TEST_RR_OP( 19, srl, 0x0000000000424242, 0x0000000021212121, 0xffffffffffffffc7 ); + TEST_RR_OP( 20, srl, 0x0000000000008484, 0x0000000021212121, 0xffffffffffffffce ); + TEST_RR_OP( 21, srl, 0x0000000000000000, 0x0000000021212121, 0xffffffffffffffff ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 22, srl, 0x01000000, 0x80000000, 7 ); + TEST_RR_SRC2_EQ_DEST( 23, srl, 0x00020000, 0x80000000, 14 ); + TEST_RR_SRC12_EQ_DEST( 24, srl, 0, 7 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 25, 0, srl, 0x01000000, 0x80000000, 7 ); + TEST_RR_DEST_BYPASS( 26, 1, srl, 0x00020000, 0x80000000, 14 ); + TEST_RR_DEST_BYPASS( 27, 2, srl, 0x00000001, 0x80000000, 31 ); + + TEST_RR_SRC12_BYPASS( 28, 0, 0, srl, 0x01000000, 0x80000000, 7 ); + TEST_RR_SRC12_BYPASS( 29, 0, 1, srl, 0x00020000, 0x80000000, 14 ); + TEST_RR_SRC12_BYPASS( 30, 0, 2, srl, 0x00000001, 0x80000000, 31 ); + TEST_RR_SRC12_BYPASS( 31, 1, 0, srl, 0x01000000, 0x80000000, 7 ); + TEST_RR_SRC12_BYPASS( 32, 1, 1, srl, 0x00020000, 0x80000000, 14 ); + TEST_RR_SRC12_BYPASS( 33, 2, 0, srl, 0x00000001, 0x80000000, 31 ); + + TEST_RR_SRC21_BYPASS( 34, 0, 0, srl, 0x01000000, 0x80000000, 7 ); + TEST_RR_SRC21_BYPASS( 35, 0, 1, srl, 0x00020000, 0x80000000, 14 ); + TEST_RR_SRC21_BYPASS( 36, 0, 2, srl, 0x00000001, 0x80000000, 31 ); + TEST_RR_SRC21_BYPASS( 37, 1, 0, srl, 0x01000000, 0x80000000, 7 ); + TEST_RR_SRC21_BYPASS( 38, 1, 1, srl, 0x00020000, 0x80000000, 14 ); + TEST_RR_SRC21_BYPASS( 39, 2, 0, srl, 0x00000001, 0x80000000, 31 ); + + TEST_RR_ZEROSRC1( 40, srl, 0, 15 ); + TEST_RR_ZEROSRC2( 41, srl, 32, 32 ); + TEST_RR_ZEROSRC12( 42, srl, 0 ); + TEST_RR_ZERODEST( 43, srl, 1024, 2048 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64ui/srli.S b/tb/qumcu/isa/rv64ui/srli.S new file mode 100644 index 0000000..3522957 --- /dev/null +++ b/tb/qumcu/isa/rv64ui/srli.S @@ -0,0 +1,71 @@ +# See LICENSE for license details. + +#***************************************************************************** +# srli.S +#----------------------------------------------------------------------------- +# +# Test srli instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + +#define TEST_SRLI(n, v, a) \ + TEST_IMM_OP(n, srli, ((v) & ((1 << (__riscv_xlen-1) << 1) - 1)) >> (a), v, a) + + TEST_SRLI( 2, 0xffffffff80000000, 0 ); + TEST_SRLI( 3, 0xffffffff80000000, 1 ); + TEST_SRLI( 4, 0xffffffff80000000, 7 ); + TEST_SRLI( 5, 0xffffffff80000000, 14 ); + TEST_SRLI( 6, 0xffffffff80000001, 31 ); + + TEST_SRLI( 7, 0xffffffffffffffff, 0 ); + TEST_SRLI( 8, 0xffffffffffffffff, 1 ); + TEST_SRLI( 9, 0xffffffffffffffff, 7 ); + TEST_SRLI( 10, 0xffffffffffffffff, 14 ); + TEST_SRLI( 11, 0xffffffffffffffff, 31 ); + + TEST_SRLI( 12, 0x0000000021212121, 0 ); + TEST_SRLI( 13, 0x0000000021212121, 1 ); + TEST_SRLI( 14, 0x0000000021212121, 7 ); + TEST_SRLI( 15, 0x0000000021212121, 14 ); + TEST_SRLI( 16, 0x0000000021212121, 31 ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_IMM_SRC1_EQ_DEST( 17, srli, 0x01000000, 0x80000000, 7 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_IMM_DEST_BYPASS( 18, 0, srli, 0x01000000, 0x80000000, 7 ); + TEST_IMM_DEST_BYPASS( 19, 1, srli, 0x00020000, 0x80000000, 14 ); + TEST_IMM_DEST_BYPASS( 20, 2, srli, 0x00000001, 0x80000001, 31 ); + + TEST_IMM_SRC1_BYPASS( 21, 0, srli, 0x01000000, 0x80000000, 7 ); + TEST_IMM_SRC1_BYPASS( 22, 1, srli, 0x00020000, 0x80000000, 14 ); + TEST_IMM_SRC1_BYPASS( 23, 2, srli, 0x00000001, 0x80000001, 31 ); + + TEST_IMM_ZEROSRC1( 24, srli, 0, 4 ); + TEST_IMM_ZERODEST( 25, srli, 33, 10 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64ui/srliw.S b/tb/qumcu/isa/rv64ui/srliw.S new file mode 100644 index 0000000..471042f --- /dev/null +++ b/tb/qumcu/isa/rv64ui/srliw.S @@ -0,0 +1,75 @@ +# See LICENSE for license details. + +#***************************************************************************** +# srliw.S +#----------------------------------------------------------------------------- +# +# Test srliw instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_IMM_OP( 2, srliw, 0xffffffff80000000, 0xffffffff80000000, 0 ); + TEST_IMM_OP( 3, srliw, 0x0000000040000000, 0xffffffff80000000, 1 ); + TEST_IMM_OP( 4, srliw, 0x0000000001000000, 0xffffffff80000000, 7 ); + TEST_IMM_OP( 5, srliw, 0x0000000000020000, 0xffffffff80000000, 14 ); + TEST_IMM_OP( 6, srliw, 0x0000000000000001, 0xffffffff80000001, 31 ); + + TEST_IMM_OP( 7, srliw, 0xffffffffffffffff, 0xffffffffffffffff, 0 ); + TEST_IMM_OP( 8, srliw, 0x000000007fffffff, 0xffffffffffffffff, 1 ); + TEST_IMM_OP( 9, srliw, 0x0000000001ffffff, 0xffffffffffffffff, 7 ); + TEST_IMM_OP( 10, srliw, 0x000000000003ffff, 0xffffffffffffffff, 14 ); + TEST_IMM_OP( 11, srliw, 0x0000000000000001, 0xffffffffffffffff, 31 ); + + TEST_IMM_OP( 12, srliw, 0x0000000021212121, 0x0000000021212121, 0 ); + TEST_IMM_OP( 13, srliw, 0x0000000010909090, 0x0000000021212121, 1 ); + TEST_IMM_OP( 14, srliw, 0x0000000000424242, 0x0000000021212121, 7 ); + TEST_IMM_OP( 15, srliw, 0x0000000000008484, 0x0000000021212121, 14 ); + TEST_IMM_OP( 16, srliw, 0x0000000000000000, 0x0000000021212121, 31 ); + + # Verify that shifts ignore top 32 (using true 64-bit values) + + TEST_IMM_OP( 44, srliw, 0x0000000012345678, 0xffffffff12345678, 0 ); + TEST_IMM_OP( 45, srliw, 0x0000000001234567, 0xffffffff12345678, 4 ); + TEST_IMM_OP( 46, srliw, 0xffffffff92345678, 0x0000000092345678, 0 ); + TEST_IMM_OP( 47, srliw, 0x0000000009234567, 0x0000000092345678, 4 ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_IMM_SRC1_EQ_DEST( 17, srliw, 0x0000000001000000, 0xffffffff80000000, 7 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_IMM_DEST_BYPASS( 18, 0, srliw, 0x0000000001000000, 0xffffffff80000000, 7 ); + TEST_IMM_DEST_BYPASS( 19, 1, srliw, 0x0000000000020000, 0xffffffff80000000, 14 ); + TEST_IMM_DEST_BYPASS( 20, 2, srliw, 0x0000000000000001, 0xffffffff80000001, 31 ); + + TEST_IMM_SRC1_BYPASS( 21, 0, srliw, 0x0000000001000000, 0xffffffff80000000, 7 ); + TEST_IMM_SRC1_BYPASS( 22, 1, srliw, 0x0000000000020000, 0xffffffff80000000, 14 ); + TEST_IMM_SRC1_BYPASS( 23, 2, srliw, 0x0000000000000001, 0xffffffff80000001, 31 ); + + TEST_IMM_ZEROSRC1( 24, srliw, 0, 31 ); + TEST_IMM_ZERODEST( 25, srliw, 31, 28 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64ui/srlw.S b/tb/qumcu/isa/rv64ui/srlw.S new file mode 100644 index 0000000..f0d1dae --- /dev/null +++ b/tb/qumcu/isa/rv64ui/srlw.S @@ -0,0 +1,97 @@ +# See LICENSE for license details. + +#***************************************************************************** +# srlw.S +#----------------------------------------------------------------------------- +# +# Test srlw instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, srlw, 0xffffffff80000000, 0xffffffff80000000, 0 ); + TEST_RR_OP( 3, srlw, 0x0000000040000000, 0xffffffff80000000, 1 ); + TEST_RR_OP( 4, srlw, 0x0000000001000000, 0xffffffff80000000, 7 ); + TEST_RR_OP( 5, srlw, 0x0000000000020000, 0xffffffff80000000, 14 ); + TEST_RR_OP( 6, srlw, 0x0000000000000001, 0xffffffff80000001, 31 ); + + TEST_RR_OP( 7, srlw, 0xffffffffffffffff, 0xffffffffffffffff, 0 ); + TEST_RR_OP( 8, srlw, 0x000000007fffffff, 0xffffffffffffffff, 1 ); + TEST_RR_OP( 9, srlw, 0x0000000001ffffff, 0xffffffffffffffff, 7 ); + TEST_RR_OP( 10, srlw, 0x000000000003ffff, 0xffffffffffffffff, 14 ); + TEST_RR_OP( 11, srlw, 0x0000000000000001, 0xffffffffffffffff, 31 ); + + TEST_RR_OP( 12, srlw, 0x0000000021212121, 0x0000000021212121, 0 ); + TEST_RR_OP( 13, srlw, 0x0000000010909090, 0x0000000021212121, 1 ); + TEST_RR_OP( 14, srlw, 0x0000000000424242, 0x0000000021212121, 7 ); + TEST_RR_OP( 15, srlw, 0x0000000000008484, 0x0000000021212121, 14 ); + TEST_RR_OP( 16, srlw, 0x0000000000000000, 0x0000000021212121, 31 ); + + # Verify that shifts only use bottom five bits + + TEST_RR_OP( 17, srlw, 0x0000000021212121, 0x0000000021212121, 0xffffffffffffffe0 ); + TEST_RR_OP( 18, srlw, 0x0000000010909090, 0x0000000021212121, 0xffffffffffffffe1 ); + TEST_RR_OP( 19, srlw, 0x0000000000424242, 0x0000000021212121, 0xffffffffffffffe7 ); + TEST_RR_OP( 20, srlw, 0x0000000000008484, 0x0000000021212121, 0xffffffffffffffee ); + TEST_RR_OP( 21, srlw, 0x0000000000000000, 0x0000000021212121, 0xffffffffffffffff ); + + # Verify that shifts ignore top 32 (using true 64-bit values) + + TEST_RR_OP( 44, srlw, 0x0000000012345678, 0xffffffff12345678, 0 ); + TEST_RR_OP( 45, srlw, 0x0000000001234567, 0xffffffff12345678, 4 ); + TEST_RR_OP( 46, srlw, 0xffffffff92345678, 0x0000000092345678, 0 ); + TEST_RR_OP( 47, srlw, 0x0000000009234567, 0x0000000092345678, 4 ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 22, srlw, 0x0000000001000000, 0xffffffff80000000, 7 ); + TEST_RR_SRC2_EQ_DEST( 23, srlw, 0x0000000000020000, 0xffffffff80000000, 14 ); + TEST_RR_SRC12_EQ_DEST( 24, srlw, 0, 7 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 25, 0, srlw, 0x0000000001000000, 0xffffffff80000000, 7 ); + TEST_RR_DEST_BYPASS( 26, 1, srlw, 0x0000000000020000, 0xffffffff80000000, 14 ); + TEST_RR_DEST_BYPASS( 27, 2, srlw, 0x0000000000000001, 0xffffffff80000000, 31 ); + + TEST_RR_SRC12_BYPASS( 28, 0, 0, srlw, 0x0000000001000000, 0xffffffff80000000, 7 ); + TEST_RR_SRC12_BYPASS( 29, 0, 1, srlw, 0x0000000000020000, 0xffffffff80000000, 14 ); + TEST_RR_SRC12_BYPASS( 30, 0, 2, srlw, 0x0000000000000001, 0xffffffff80000000, 31 ); + TEST_RR_SRC12_BYPASS( 31, 1, 0, srlw, 0x0000000001000000, 0xffffffff80000000, 7 ); + TEST_RR_SRC12_BYPASS( 32, 1, 1, srlw, 0x0000000000020000, 0xffffffff80000000, 14 ); + TEST_RR_SRC12_BYPASS( 33, 2, 0, srlw, 0x0000000000000001, 0xffffffff80000000, 31 ); + + TEST_RR_SRC21_BYPASS( 34, 0, 0, srlw, 0x0000000001000000, 0xffffffff80000000, 7 ); + TEST_RR_SRC21_BYPASS( 35, 0, 1, srlw, 0x0000000000020000, 0xffffffff80000000, 14 ); + TEST_RR_SRC21_BYPASS( 36, 0, 2, srlw, 0x0000000000000001, 0xffffffff80000000, 31 ); + TEST_RR_SRC21_BYPASS( 37, 1, 0, srlw, 0x0000000001000000, 0xffffffff80000000, 7 ); + TEST_RR_SRC21_BYPASS( 38, 1, 1, srlw, 0x0000000000020000, 0xffffffff80000000, 14 ); + TEST_RR_SRC21_BYPASS( 39, 2, 0, srlw, 0x0000000000000001, 0xffffffff80000000, 31 ); + + TEST_RR_ZEROSRC1( 40, srlw, 0, 15 ); + TEST_RR_ZEROSRC2( 41, srlw, 32, 32 ); + TEST_RR_ZEROSRC12( 42, srlw, 0 ); + TEST_RR_ZERODEST( 43, srlw, 1024, 2048 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64ui/sub.S b/tb/qumcu/isa/rv64ui/sub.S new file mode 100644 index 0000000..005bdea --- /dev/null +++ b/tb/qumcu/isa/rv64ui/sub.S @@ -0,0 +1,83 @@ +# See LICENSE for license details. + +#***************************************************************************** +# sub.S +#----------------------------------------------------------------------------- +# +# Test sub instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, sub, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000 ); + TEST_RR_OP( 3, sub, 0x0000000000000000, 0x0000000000000001, 0x0000000000000001 ); + TEST_RR_OP( 4, sub, 0xfffffffffffffffc, 0x0000000000000003, 0x0000000000000007 ); + + TEST_RR_OP( 5, sub, 0x0000000000008000, 0x0000000000000000, 0xffffffffffff8000 ); + TEST_RR_OP( 6, sub, 0xffffffff80000000, 0xffffffff80000000, 0x0000000000000000 ); + TEST_RR_OP( 7, sub, 0xffffffff80008000, 0xffffffff80000000, 0xffffffffffff8000 ); + + TEST_RR_OP( 8, sub, 0xffffffffffff8001, 0x0000000000000000, 0x0000000000007fff ); + TEST_RR_OP( 9, sub, 0x000000007fffffff, 0x000000007fffffff, 0x0000000000000000 ); + TEST_RR_OP( 10, sub, 0x000000007fff8000, 0x000000007fffffff, 0x0000000000007fff ); + + TEST_RR_OP( 11, sub, 0xffffffff7fff8001, 0xffffffff80000000, 0x0000000000007fff ); + TEST_RR_OP( 12, sub, 0x0000000080007fff, 0x000000007fffffff, 0xffffffffffff8000 ); + + TEST_RR_OP( 13, sub, 0x0000000000000001, 0x0000000000000000, 0xffffffffffffffff ); + TEST_RR_OP( 14, sub, 0xfffffffffffffffe, 0xffffffffffffffff, 0x0000000000000001 ); + TEST_RR_OP( 15, sub, 0x0000000000000000, 0xffffffffffffffff, 0xffffffffffffffff ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 16, sub, 2, 13, 11 ); + TEST_RR_SRC2_EQ_DEST( 17, sub, 3, 14, 11 ); + TEST_RR_SRC12_EQ_DEST( 18, sub, 0, 13 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 19, 0, sub, 2, 13, 11 ); + TEST_RR_DEST_BYPASS( 20, 1, sub, 3, 14, 11 ); + TEST_RR_DEST_BYPASS( 21, 2, sub, 4, 15, 11 ); + + TEST_RR_SRC12_BYPASS( 22, 0, 0, sub, 2, 13, 11 ); + TEST_RR_SRC12_BYPASS( 23, 0, 1, sub, 3, 14, 11 ); + TEST_RR_SRC12_BYPASS( 24, 0, 2, sub, 4, 15, 11 ); + TEST_RR_SRC12_BYPASS( 25, 1, 0, sub, 2, 13, 11 ); + TEST_RR_SRC12_BYPASS( 26, 1, 1, sub, 3, 14, 11 ); + TEST_RR_SRC12_BYPASS( 27, 2, 0, sub, 4, 15, 11 ); + + TEST_RR_SRC21_BYPASS( 28, 0, 0, sub, 2, 13, 11 ); + TEST_RR_SRC21_BYPASS( 29, 0, 1, sub, 3, 14, 11 ); + TEST_RR_SRC21_BYPASS( 30, 0, 2, sub, 4, 15, 11 ); + TEST_RR_SRC21_BYPASS( 31, 1, 0, sub, 2, 13, 11 ); + TEST_RR_SRC21_BYPASS( 32, 1, 1, sub, 3, 14, 11 ); + TEST_RR_SRC21_BYPASS( 33, 2, 0, sub, 4, 15, 11 ); + + TEST_RR_ZEROSRC1( 34, sub, 15, -15 ); + TEST_RR_ZEROSRC2( 35, sub, 32, 32 ); + TEST_RR_ZEROSRC12( 36, sub, 0 ); + TEST_RR_ZERODEST( 37, sub, 16, 30 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64ui/subw.S b/tb/qumcu/isa/rv64ui/subw.S new file mode 100644 index 0000000..9940d8c --- /dev/null +++ b/tb/qumcu/isa/rv64ui/subw.S @@ -0,0 +1,83 @@ +# See LICENSE for license details. + +#***************************************************************************** +# subw.S +#----------------------------------------------------------------------------- +# +# Test subw instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, subw, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000 ); + TEST_RR_OP( 3, subw, 0x0000000000000000, 0x0000000000000001, 0x0000000000000001 ); + TEST_RR_OP( 4, subw, 0xfffffffffffffffc, 0x0000000000000003, 0x0000000000000007 ); + + TEST_RR_OP( 5, subw, 0x0000000000008000, 0x0000000000000000, 0xffffffffffff8000 ); + TEST_RR_OP( 6, subw, 0xffffffff80000000, 0xffffffff80000000, 0x0000000000000000 ); + TEST_RR_OP( 7, subw, 0xffffffff80008000, 0xffffffff80000000, 0xffffffffffff8000 ); + + TEST_RR_OP( 8, subw, 0xffffffffffff8001, 0x0000000000000000, 0x0000000000007fff ); + TEST_RR_OP( 9, subw, 0x000000007fffffff, 0x000000007fffffff, 0x0000000000000000 ); + TEST_RR_OP( 10, subw, 0x000000007fff8000, 0x000000007fffffff, 0x0000000000007fff ); + + TEST_RR_OP( 11, subw, 0x000000007fff8001, 0xffffffff80000000, 0x0000000000007fff ); + TEST_RR_OP( 12, subw, 0xffffffff80007fff, 0x000000007fffffff, 0xffffffffffff8000 ); + + TEST_RR_OP( 13, subw, 0x0000000000000001, 0x0000000000000000, 0xffffffffffffffff ); + TEST_RR_OP( 14, subw, 0xfffffffffffffffe, 0xffffffffffffffff, 0x0000000000000001 ); + TEST_RR_OP( 15, subw, 0x0000000000000000, 0xffffffffffffffff, 0xffffffffffffffff ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 16, subw, 2, 13, 11 ); + TEST_RR_SRC2_EQ_DEST( 17, subw, 3, 14, 11 ); + TEST_RR_SRC12_EQ_DEST( 18, subw, 0, 13 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 19, 0, subw, 2, 13, 11 ); + TEST_RR_DEST_BYPASS( 20, 1, subw, 3, 14, 11 ); + TEST_RR_DEST_BYPASS( 21, 2, subw, 4, 15, 11 ); + + TEST_RR_SRC12_BYPASS( 22, 0, 0, subw, 2, 13, 11 ); + TEST_RR_SRC12_BYPASS( 23, 0, 1, subw, 3, 14, 11 ); + TEST_RR_SRC12_BYPASS( 24, 0, 2, subw, 4, 15, 11 ); + TEST_RR_SRC12_BYPASS( 25, 1, 0, subw, 2, 13, 11 ); + TEST_RR_SRC12_BYPASS( 26, 1, 1, subw, 3, 14, 11 ); + TEST_RR_SRC12_BYPASS( 27, 2, 0, subw, 4, 15, 11 ); + + TEST_RR_SRC21_BYPASS( 28, 0, 0, subw, 2, 13, 11 ); + TEST_RR_SRC21_BYPASS( 29, 0, 1, subw, 3, 14, 11 ); + TEST_RR_SRC21_BYPASS( 30, 0, 2, subw, 4, 15, 11 ); + TEST_RR_SRC21_BYPASS( 31, 1, 0, subw, 2, 13, 11 ); + TEST_RR_SRC21_BYPASS( 32, 1, 1, subw, 3, 14, 11 ); + TEST_RR_SRC21_BYPASS( 33, 2, 0, subw, 4, 15, 11 ); + + TEST_RR_ZEROSRC1( 34, subw, 15, -15 ); + TEST_RR_ZEROSRC2( 35, subw, 32, 32 ); + TEST_RR_ZEROSRC12( 36, subw, 0 ); + TEST_RR_ZERODEST( 37, subw, 16, 30 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64ui/sw.S b/tb/qumcu/isa/rv64ui/sw.S new file mode 100644 index 0000000..ab094b3 --- /dev/null +++ b/tb/qumcu/isa/rv64ui/sw.S @@ -0,0 +1,92 @@ +# See LICENSE for license details. + +#***************************************************************************** +# sw.S +#----------------------------------------------------------------------------- +# +# Test sw instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Basic tests + #------------------------------------------------------------- + + TEST_ST_OP( 2, lw, sw, 0x0000000000aa00aa, 0, tdat ); + TEST_ST_OP( 3, lw, sw, 0xffffffffaa00aa00, 4, tdat ); + TEST_ST_OP( 4, lw, sw, 0x000000000aa00aa0, 8, tdat ); + TEST_ST_OP( 5, lw, sw, 0xffffffffa00aa00a, 12, tdat ); + + # Test with negative offset + + TEST_ST_OP( 6, lw, sw, 0x0000000000aa00aa, -12, tdat8 ); + TEST_ST_OP( 7, lw, sw, 0xffffffffaa00aa00, -8, tdat8 ); + TEST_ST_OP( 8, lw, sw, 0x000000000aa00aa0, -4, tdat8 ); + TEST_ST_OP( 9, lw, sw, 0xffffffffa00aa00a, 0, tdat8 ); + + # Test with a negative base + + TEST_CASE( 10, x5, 0x12345678, \ + la x1, tdat9; \ + li x2, 0x12345678; \ + addi x4, x1, -32; \ + sw x2, 32(x4); \ + lw x5, 0(x1); \ + ) + + # Test with unaligned base + + TEST_CASE( 11, x5, 0x58213098, \ + la x1, tdat9; \ + li x2, 0x58213098; \ + addi x1, x1, -3; \ + sw x2, 7(x1); \ + la x4, tdat10; \ + lw x5, 0(x4); \ + ) + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_ST_SRC12_BYPASS( 12, 0, 0, lw, sw, 0xffffffffaabbccdd, 0, tdat ); + TEST_ST_SRC12_BYPASS( 13, 0, 1, lw, sw, 0xffffffffdaabbccd, 4, tdat ); + TEST_ST_SRC12_BYPASS( 14, 0, 2, lw, sw, 0xffffffffddaabbcc, 8, tdat ); + TEST_ST_SRC12_BYPASS( 15, 1, 0, lw, sw, 0xffffffffcddaabbc, 12, tdat ); + TEST_ST_SRC12_BYPASS( 16, 1, 1, lw, sw, 0xffffffffccddaabb, 16, tdat ); + TEST_ST_SRC12_BYPASS( 17, 2, 0, lw, sw, 0xffffffffbccddaab, 20, tdat ); + + TEST_ST_SRC21_BYPASS( 18, 0, 0, lw, sw, 0x00112233, 0, tdat ); + TEST_ST_SRC21_BYPASS( 19, 0, 1, lw, sw, 0x30011223, 4, tdat ); + TEST_ST_SRC21_BYPASS( 20, 0, 2, lw, sw, 0x33001122, 8, tdat ); + TEST_ST_SRC21_BYPASS( 21, 1, 0, lw, sw, 0x23300112, 12, tdat ); + TEST_ST_SRC21_BYPASS( 22, 1, 1, lw, sw, 0x22330011, 16, tdat ); + TEST_ST_SRC21_BYPASS( 23, 2, 0, lw, sw, 0x12233001, 20, tdat ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +tdat: +tdat1: .word 0xdeadbeef +tdat2: .word 0xdeadbeef +tdat3: .word 0xdeadbeef +tdat4: .word 0xdeadbeef +tdat5: .word 0xdeadbeef +tdat6: .word 0xdeadbeef +tdat7: .word 0xdeadbeef +tdat8: .word 0xdeadbeef +tdat9: .word 0xdeadbeef +tdat10: .word 0xdeadbeef + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64ui/xor.S b/tb/qumcu/isa/rv64ui/xor.S new file mode 100644 index 0000000..c4e9552 --- /dev/null +++ b/tb/qumcu/isa/rv64ui/xor.S @@ -0,0 +1,69 @@ +# See LICENSE for license details. + +#***************************************************************************** +# xor.S +#----------------------------------------------------------------------------- +# +# Test xor instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Logical tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, xor, 0xf00ff00f, 0xff00ff00, 0x0f0f0f0f ); + TEST_RR_OP( 3, xor, 0xff00ff00, 0x0ff00ff0, 0xf0f0f0f0 ); + TEST_RR_OP( 4, xor, 0x0ff00ff0, 0x00ff00ff, 0x0f0f0f0f ); + TEST_RR_OP( 5, xor, 0x00ff00ff, 0xf00ff00f, 0xf0f0f0f0 ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 6, xor, 0xf00ff00f, 0xff00ff00, 0x0f0f0f0f ); + TEST_RR_SRC2_EQ_DEST( 7, xor, 0xf00ff00f, 0xff00ff00, 0x0f0f0f0f ); + TEST_RR_SRC12_EQ_DEST( 8, xor, 0x00000000, 0xff00ff00 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 9, 0, xor, 0xf00ff00f, 0xff00ff00, 0x0f0f0f0f ); + TEST_RR_DEST_BYPASS( 10, 1, xor, 0xff00ff00, 0x0ff00ff0, 0xf0f0f0f0 ); + TEST_RR_DEST_BYPASS( 11, 2, xor, 0x0ff00ff0, 0x00ff00ff, 0x0f0f0f0f ); + + TEST_RR_SRC12_BYPASS( 12, 0, 0, xor, 0xf00ff00f, 0xff00ff00, 0x0f0f0f0f ); + TEST_RR_SRC12_BYPASS( 13, 0, 1, xor, 0xff00ff00, 0x0ff00ff0, 0xf0f0f0f0 ); + TEST_RR_SRC12_BYPASS( 14, 0, 2, xor, 0x0ff00ff0, 0x00ff00ff, 0x0f0f0f0f ); + TEST_RR_SRC12_BYPASS( 15, 1, 0, xor, 0xf00ff00f, 0xff00ff00, 0x0f0f0f0f ); + TEST_RR_SRC12_BYPASS( 16, 1, 1, xor, 0xff00ff00, 0x0ff00ff0, 0xf0f0f0f0 ); + TEST_RR_SRC12_BYPASS( 17, 2, 0, xor, 0x0ff00ff0, 0x00ff00ff, 0x0f0f0f0f ); + + TEST_RR_SRC21_BYPASS( 18, 0, 0, xor, 0xf00ff00f, 0xff00ff00, 0x0f0f0f0f ); + TEST_RR_SRC21_BYPASS( 19, 0, 1, xor, 0xff00ff00, 0x0ff00ff0, 0xf0f0f0f0 ); + TEST_RR_SRC21_BYPASS( 20, 0, 2, xor, 0x0ff00ff0, 0x00ff00ff, 0x0f0f0f0f ); + TEST_RR_SRC21_BYPASS( 21, 1, 0, xor, 0xf00ff00f, 0xff00ff00, 0x0f0f0f0f ); + TEST_RR_SRC21_BYPASS( 22, 1, 1, xor, 0xff00ff00, 0x0ff00ff0, 0xf0f0f0f0 ); + TEST_RR_SRC21_BYPASS( 23, 2, 0, xor, 0x0ff00ff0, 0x00ff00ff, 0x0f0f0f0f ); + + TEST_RR_ZEROSRC1( 24, xor, 0xff00ff00, 0xff00ff00 ); + TEST_RR_ZEROSRC2( 25, xor, 0x00ff00ff, 0x00ff00ff ); + TEST_RR_ZEROSRC12( 26, xor, 0 ); + TEST_RR_ZERODEST( 27, xor, 0x11111111, 0x22222222 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64ui/xori.S b/tb/qumcu/isa/rv64ui/xori.S new file mode 100644 index 0000000..eb59d12 --- /dev/null +++ b/tb/qumcu/isa/rv64ui/xori.S @@ -0,0 +1,55 @@ +# See LICENSE for license details. + +#***************************************************************************** +# xori.S +#----------------------------------------------------------------------------- +# +# Test xori instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Logical tests + #------------------------------------------------------------- + + TEST_IMM_OP( 2, xori, 0xffffffffff00f00f, 0x0000000000ff0f00, 0xf0f ); + TEST_IMM_OP( 3, xori, 0x000000000ff00f00, 0x000000000ff00ff0, 0x0f0 ); + TEST_IMM_OP( 4, xori, 0x0000000000ff0ff0, 0x0000000000ff08ff, 0x70f ); + TEST_IMM_OP( 5, xori, 0xfffffffff00ff0ff, 0xfffffffff00ff00f, 0x0f0 ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_IMM_SRC1_EQ_DEST( 6, xori, 0xffffffffff00f00f, 0xffffffffff00f700, 0x70f ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_IMM_DEST_BYPASS( 7, 0, xori, 0x000000000ff00f00, 0x000000000ff00ff0, 0x0f0 ); + TEST_IMM_DEST_BYPASS( 8, 1, xori, 0x0000000000ff0ff0, 0x0000000000ff08ff, 0x70f ); + TEST_IMM_DEST_BYPASS( 9, 2, xori, 0xfffffffff00ff0ff, 0xfffffffff00ff00f, 0x0f0 ); + + TEST_IMM_SRC1_BYPASS( 10, 0, xori, 0x000000000ff00f00, 0x000000000ff00ff0, 0x0f0 ); + TEST_IMM_SRC1_BYPASS( 11, 1, xori, 0x0000000000ff0ff0, 0x0000000000ff0fff, 0x00f ); + TEST_IMM_SRC1_BYPASS( 12, 2, xori, 0xfffffffff00ff0ff, 0xfffffffff00ff00f, 0x0f0 ); + + TEST_IMM_ZEROSRC1( 13, xori, 0x0f0, 0x0f0 ); + TEST_IMM_ZERODEST( 14, xori, 0x00ff00ff, 0x70f ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64um/Makefrag b/tb/qumcu/isa/rv64um/Makefrag new file mode 100644 index 0000000..2a9e66d --- /dev/null +++ b/tb/qumcu/isa/rv64um/Makefrag @@ -0,0 +1,11 @@ +#======================================================================= +# Makefrag for rv64um tests +#----------------------------------------------------------------------- + +rv64um_sc_tests = \ + div divu divuw divw \ + mul mulh mulhsu mulhu mulw \ + rem remu remuw remw \ + +rv64um_p_tests = $(addprefix rv64um-p-, $(rv64um_sc_tests)) +rv64um_v_tests = $(addprefix rv64um-v-, $(rv64um_sc_tests)) diff --git a/tb/qumcu/isa/rv64um/div.S b/tb/qumcu/isa/rv64um/div.S new file mode 100644 index 0000000..ee21f0c --- /dev/null +++ b/tb/qumcu/isa/rv64um/div.S @@ -0,0 +1,41 @@ +# See LICENSE for license details. + +#***************************************************************************** +# div.S +#----------------------------------------------------------------------------- +# +# Test div instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, div, 3, 20, 6 ); + TEST_RR_OP( 3, div, -3, -20, 6 ); + TEST_RR_OP( 4, div, -3, 20, -6 ); + TEST_RR_OP( 5, div, 3, -20, -6 ); + + TEST_RR_OP( 6, div, -1<<63, -1<<63, 1 ); + TEST_RR_OP( 7, div, -1<<63, -1<<63, -1 ); + + TEST_RR_OP( 8, div, -1, -1<<63, 0 ); + TEST_RR_OP( 9, div, -1, 1, 0 ); + TEST_RR_OP(10, div, -1, 0, 0 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64um/divu.S b/tb/qumcu/isa/rv64um/divu.S new file mode 100644 index 0000000..e63fd65 --- /dev/null +++ b/tb/qumcu/isa/rv64um/divu.S @@ -0,0 +1,41 @@ +# See LICENSE for license details. + +#***************************************************************************** +# divu.S +#----------------------------------------------------------------------------- +# +# Test divu instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, divu, 3, 20, 6 ); + TEST_RR_OP( 3, divu, 3074457345618258599, -20, 6 ); + TEST_RR_OP( 4, divu, 0, 20, -6 ); + TEST_RR_OP( 5, divu, 0, -20, -6 ); + + TEST_RR_OP( 6, divu, -1<<63, -1<<63, 1 ); + TEST_RR_OP( 7, divu, 0, -1<<63, -1 ); + + TEST_RR_OP( 8, divu, -1, -1<<63, 0 ); + TEST_RR_OP( 9, divu, -1, 1, 0 ); + TEST_RR_OP(10, divu, -1, 0, 0 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64um/divuw.S b/tb/qumcu/isa/rv64um/divuw.S new file mode 100644 index 0000000..4c9eee7 --- /dev/null +++ b/tb/qumcu/isa/rv64um/divuw.S @@ -0,0 +1,41 @@ +# See LICENSE for license details. + +#***************************************************************************** +# divuw.S +#----------------------------------------------------------------------------- +# +# Test divuw instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, divuw, 3, 20, 6 ); + TEST_RR_OP( 3, divuw, 715827879, -20 << 32 >> 32, 6 ); + TEST_RR_OP( 4, divuw, 0, 20, -6 ); + TEST_RR_OP( 5, divuw, 0, -20, -6 ); + + TEST_RR_OP( 6, divuw, -1<<31, -1<<31, 1 ); + TEST_RR_OP( 7, divuw, 0, -1<<31, -1 ); + + TEST_RR_OP( 8, divuw, -1, -1<<31, 0 ); + TEST_RR_OP( 9, divuw, -1, 1, 0 ); + TEST_RR_OP(10, divuw, -1, 0, 0 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64um/divw.S b/tb/qumcu/isa/rv64um/divw.S new file mode 100644 index 0000000..4cffa1a --- /dev/null +++ b/tb/qumcu/isa/rv64um/divw.S @@ -0,0 +1,41 @@ +# See LICENSE for license details. + +#***************************************************************************** +# divw.S +#----------------------------------------------------------------------------- +# +# Test divw instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, divw, 3, 20, 6 ); + TEST_RR_OP( 3, divw, -3, -20, 6 ); + TEST_RR_OP( 4, divw, -3, 20, -6 ); + TEST_RR_OP( 5, divw, 3, -20, -6 ); + + TEST_RR_OP( 6, divw, -1<<31, -1<<31, 1 ); + TEST_RR_OP( 7, divw, -1<<31, -1<<31, -1 ); + + TEST_RR_OP( 8, divw, -1, -1<<31, 0 ); + TEST_RR_OP( 9, divw, -1, 1, 0 ); + TEST_RR_OP(10, divw, -1, 0, 0 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64um/mul.S b/tb/qumcu/isa/rv64um/mul.S new file mode 100644 index 0000000..c647e97 --- /dev/null +++ b/tb/qumcu/isa/rv64um/mul.S @@ -0,0 +1,78 @@ +# See LICENSE for license details. + +#***************************************************************************** +# mul.S +#----------------------------------------------------------------------------- +# +# Test mul instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP(32, mul, 0x0000000000001200, 0x0000000000007e00, 0x6db6db6db6db6db7 ); + TEST_RR_OP(33, mul, 0x0000000000001240, 0x0000000000007fc0, 0x6db6db6db6db6db7 ); + + TEST_RR_OP( 2, mul, 0x00000000, 0x00000000, 0x00000000 ); + TEST_RR_OP( 3, mul, 0x00000001, 0x00000001, 0x00000001 ); + TEST_RR_OP( 4, mul, 0x00000015, 0x00000003, 0x00000007 ); + + TEST_RR_OP( 5, mul, 0x0000000000000000, 0x0000000000000000, 0xffffffffffff8000 ); + TEST_RR_OP( 6, mul, 0x0000000000000000, 0xffffffff80000000, 0x00000000 ); + TEST_RR_OP( 7, mul, 0x0000400000000000, 0xffffffff80000000, 0xffffffffffff8000 ); + + TEST_RR_OP(30, mul, 0x000000000000ff7f, 0xaaaaaaaaaaaaaaab, 0x000000000002fe7d ); + TEST_RR_OP(31, mul, 0x000000000000ff7f, 0x000000000002fe7d, 0xaaaaaaaaaaaaaaab ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 8, mul, 143, 13, 11 ); + TEST_RR_SRC2_EQ_DEST( 9, mul, 154, 14, 11 ); + TEST_RR_SRC12_EQ_DEST( 10, mul, 169, 13 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 11, 0, mul, 143, 13, 11 ); + TEST_RR_DEST_BYPASS( 12, 1, mul, 154, 14, 11 ); + TEST_RR_DEST_BYPASS( 13, 2, mul, 165, 15, 11 ); + + TEST_RR_SRC12_BYPASS( 14, 0, 0, mul, 143, 13, 11 ); + TEST_RR_SRC12_BYPASS( 15, 0, 1, mul, 154, 14, 11 ); + TEST_RR_SRC12_BYPASS( 16, 0, 2, mul, 165, 15, 11 ); + TEST_RR_SRC12_BYPASS( 17, 1, 0, mul, 143, 13, 11 ); + TEST_RR_SRC12_BYPASS( 18, 1, 1, mul, 154, 14, 11 ); + TEST_RR_SRC12_BYPASS( 19, 2, 0, mul, 165, 15, 11 ); + + TEST_RR_SRC21_BYPASS( 20, 0, 0, mul, 143, 13, 11 ); + TEST_RR_SRC21_BYPASS( 21, 0, 1, mul, 154, 14, 11 ); + TEST_RR_SRC21_BYPASS( 22, 0, 2, mul, 165, 15, 11 ); + TEST_RR_SRC21_BYPASS( 23, 1, 0, mul, 143, 13, 11 ); + TEST_RR_SRC21_BYPASS( 24, 1, 1, mul, 154, 14, 11 ); + TEST_RR_SRC21_BYPASS( 25, 2, 0, mul, 165, 15, 11 ); + + TEST_RR_ZEROSRC1( 26, mul, 0, 31 ); + TEST_RR_ZEROSRC2( 27, mul, 0, 32 ); + TEST_RR_ZEROSRC12( 28, mul, 0 ); + TEST_RR_ZERODEST( 29, mul, 33, 34 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64um/mulh.S b/tb/qumcu/isa/rv64um/mulh.S new file mode 100644 index 0000000..1fd12a1 --- /dev/null +++ b/tb/qumcu/isa/rv64um/mulh.S @@ -0,0 +1,72 @@ +# See LICENSE for license details. + +#***************************************************************************** +# mulh.S +#----------------------------------------------------------------------------- +# +# Test mulh instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, mulh, 0x00000000, 0x00000000, 0x00000000 ); + TEST_RR_OP( 3, mulh, 0x00000000, 0x00000001, 0x00000001 ); + TEST_RR_OP( 4, mulh, 0x00000000, 0x00000003, 0x00000007 ); + + TEST_RR_OP( 5, mulh, 0x0000000000000000, 0x0000000000000000, 0xffffffffffff8000 ); + TEST_RR_OP( 6, mulh, 0x0000000000000000, 0xffffffff80000000, 0x00000000 ); + TEST_RR_OP( 7, mulh, 0x0000000000000000, 0xffffffff80000000, 0xffffffffffff8000 ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 8, mulh, 143, 13<<32, 11<<32 ); + TEST_RR_SRC2_EQ_DEST( 9, mulh, 154, 14<<32, 11<<32 ); + TEST_RR_SRC12_EQ_DEST( 10, mulh, 169, 13<<32 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 11, 0, mulh, 143, 13<<32, 11<<32 ); + TEST_RR_DEST_BYPASS( 12, 1, mulh, 154, 14<<32, 11<<32 ); + TEST_RR_DEST_BYPASS( 13, 2, mulh, 165, 15<<32, 11<<32 ); + + TEST_RR_SRC12_BYPASS( 14, 0, 0, mulh, 143, 13<<32, 11<<32 ); + TEST_RR_SRC12_BYPASS( 15, 0, 1, mulh, 154, 14<<32, 11<<32 ); + TEST_RR_SRC12_BYPASS( 16, 0, 2, mulh, 165, 15<<32, 11<<32 ); + TEST_RR_SRC12_BYPASS( 17, 1, 0, mulh, 143, 13<<32, 11<<32 ); + TEST_RR_SRC12_BYPASS( 18, 1, 1, mulh, 154, 14<<32, 11<<32 ); + TEST_RR_SRC12_BYPASS( 19, 2, 0, mulh, 165, 15<<32, 11<<32 ); + + TEST_RR_SRC21_BYPASS( 20, 0, 0, mulh, 143, 13<<32, 11<<32 ); + TEST_RR_SRC21_BYPASS( 21, 0, 1, mulh, 154, 14<<32, 11<<32 ); + TEST_RR_SRC21_BYPASS( 22, 0, 2, mulh, 165, 15<<32, 11<<32 ); + TEST_RR_SRC21_BYPASS( 23, 1, 0, mulh, 143, 13<<32, 11<<32 ); + TEST_RR_SRC21_BYPASS( 24, 1, 1, mulh, 154, 14<<32, 11<<32 ); + TEST_RR_SRC21_BYPASS( 25, 2, 0, mulh, 165, 15<<32, 11<<32 ); + + TEST_RR_ZEROSRC1( 26, mulh, 0, 31<<32 ); + TEST_RR_ZEROSRC2( 27, mulh, 0, 32<<32 ); + TEST_RR_ZEROSRC12( 28, mulh, 0 ); + TEST_RR_ZERODEST( 29, mulh, 33<<32, 34<<32 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64um/mulhsu.S b/tb/qumcu/isa/rv64um/mulhsu.S new file mode 100644 index 0000000..c037db2 --- /dev/null +++ b/tb/qumcu/isa/rv64um/mulhsu.S @@ -0,0 +1,72 @@ +# See LICENSE for license details. + +#***************************************************************************** +# mulhsu.S +#----------------------------------------------------------------------------- +# +# Test mulhsu instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, mulhsu, 0x00000000, 0x00000000, 0x00000000 ); + TEST_RR_OP( 3, mulhsu, 0x00000000, 0x00000001, 0x00000001 ); + TEST_RR_OP( 4, mulhsu, 0x00000000, 0x00000003, 0x00000007 ); + + TEST_RR_OP( 5, mulhsu, 0x0000000000000000, 0x0000000000000000, 0xffffffffffff8000 ); + TEST_RR_OP( 6, mulhsu, 0x0000000000000000, 0xffffffff80000000, 0x00000000 ); + TEST_RR_OP( 7, mulhsu, 0xffffffff80000000, 0xffffffff80000000, 0xffffffffffff8000 ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 8, mulhsu, 143, 13<<32, 11<<32 ); + TEST_RR_SRC2_EQ_DEST( 9, mulhsu, 154, 14<<32, 11<<32 ); + TEST_RR_SRC12_EQ_DEST( 10, mulhsu, 169, 13<<32 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 11, 0, mulhsu, 143, 13<<32, 11<<32 ); + TEST_RR_DEST_BYPASS( 12, 1, mulhsu, 154, 14<<32, 11<<32 ); + TEST_RR_DEST_BYPASS( 13, 2, mulhsu, 165, 15<<32, 11<<32 ); + + TEST_RR_SRC12_BYPASS( 14, 0, 0, mulhsu, 143, 13<<32, 11<<32 ); + TEST_RR_SRC12_BYPASS( 15, 0, 1, mulhsu, 154, 14<<32, 11<<32 ); + TEST_RR_SRC12_BYPASS( 16, 0, 2, mulhsu, 165, 15<<32, 11<<32 ); + TEST_RR_SRC12_BYPASS( 17, 1, 0, mulhsu, 143, 13<<32, 11<<32 ); + TEST_RR_SRC12_BYPASS( 18, 1, 1, mulhsu, 154, 14<<32, 11<<32 ); + TEST_RR_SRC12_BYPASS( 19, 2, 0, mulhsu, 165, 15<<32, 11<<32 ); + + TEST_RR_SRC21_BYPASS( 20, 0, 0, mulhsu, 143, 13<<32, 11<<32 ); + TEST_RR_SRC21_BYPASS( 21, 0, 1, mulhsu, 154, 14<<32, 11<<32 ); + TEST_RR_SRC21_BYPASS( 22, 0, 2, mulhsu, 165, 15<<32, 11<<32 ); + TEST_RR_SRC21_BYPASS( 23, 1, 0, mulhsu, 143, 13<<32, 11<<32 ); + TEST_RR_SRC21_BYPASS( 24, 1, 1, mulhsu, 154, 14<<32, 11<<32 ); + TEST_RR_SRC21_BYPASS( 25, 2, 0, mulhsu, 165, 15<<32, 11<<32 ); + + TEST_RR_ZEROSRC1( 26, mulhsu, 0, 31<<32 ); + TEST_RR_ZEROSRC2( 27, mulhsu, 0, 32<<32 ); + TEST_RR_ZEROSRC12( 28, mulhsu, 0 ); + TEST_RR_ZERODEST( 29, mulhsu, 33<<32, 34<<32 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64um/mulhu.S b/tb/qumcu/isa/rv64um/mulhu.S new file mode 100644 index 0000000..aa7b762 --- /dev/null +++ b/tb/qumcu/isa/rv64um/mulhu.S @@ -0,0 +1,75 @@ +# See LICENSE for license details. + +#***************************************************************************** +# mulhu.S +#----------------------------------------------------------------------------- +# +# Test mulhu instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, mulhu, 0x00000000, 0x00000000, 0x00000000 ); + TEST_RR_OP( 3, mulhu, 0x00000000, 0x00000001, 0x00000001 ); + TEST_RR_OP( 4, mulhu, 0x00000000, 0x00000003, 0x00000007 ); + + TEST_RR_OP( 5, mulhu, 0x0000000000000000, 0x0000000000000000, 0xffffffffffff8000 ); + TEST_RR_OP( 6, mulhu, 0x0000000000000000, 0xffffffff80000000, 0x00000000 ); + TEST_RR_OP( 7, mulhu, 0xffffffff7fff8000, 0xffffffff80000000, 0xffffffffffff8000 ); + + TEST_RR_OP(30, mulhu, 0x000000000001fefe, 0xaaaaaaaaaaaaaaab, 0x000000000002fe7d ); + TEST_RR_OP(31, mulhu, 0x000000000001fefe, 0x000000000002fe7d, 0xaaaaaaaaaaaaaaab ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 8, mulhu, 143, 13<<32, 11<<32 ); + TEST_RR_SRC2_EQ_DEST( 9, mulhu, 154, 14<<32, 11<<32 ); + TEST_RR_SRC12_EQ_DEST( 10, mulhu, 169, 13<<32 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 11, 0, mulhu, 143, 13<<32, 11<<32 ); + TEST_RR_DEST_BYPASS( 12, 1, mulhu, 154, 14<<32, 11<<32 ); + TEST_RR_DEST_BYPASS( 13, 2, mulhu, 165, 15<<32, 11<<32 ); + + TEST_RR_SRC12_BYPASS( 14, 0, 0, mulhu, 143, 13<<32, 11<<32 ); + TEST_RR_SRC12_BYPASS( 15, 0, 1, mulhu, 154, 14<<32, 11<<32 ); + TEST_RR_SRC12_BYPASS( 16, 0, 2, mulhu, 165, 15<<32, 11<<32 ); + TEST_RR_SRC12_BYPASS( 17, 1, 0, mulhu, 143, 13<<32, 11<<32 ); + TEST_RR_SRC12_BYPASS( 18, 1, 1, mulhu, 154, 14<<32, 11<<32 ); + TEST_RR_SRC12_BYPASS( 19, 2, 0, mulhu, 165, 15<<32, 11<<32 ); + + TEST_RR_SRC21_BYPASS( 20, 0, 0, mulhu, 143, 13<<32, 11<<32 ); + TEST_RR_SRC21_BYPASS( 21, 0, 1, mulhu, 154, 14<<32, 11<<32 ); + TEST_RR_SRC21_BYPASS( 22, 0, 2, mulhu, 165, 15<<32, 11<<32 ); + TEST_RR_SRC21_BYPASS( 23, 1, 0, mulhu, 143, 13<<32, 11<<32 ); + TEST_RR_SRC21_BYPASS( 24, 1, 1, mulhu, 154, 14<<32, 11<<32 ); + TEST_RR_SRC21_BYPASS( 25, 2, 0, mulhu, 165, 15<<32, 11<<32 ); + + TEST_RR_ZEROSRC1( 26, mulhu, 0, 31<<32 ); + TEST_RR_ZEROSRC2( 27, mulhu, 0, 32<<32 ); + TEST_RR_ZEROSRC12( 28, mulhu, 0 ); + TEST_RR_ZERODEST( 29, mulhu, 33<<32, 34<<32 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64um/mulw.S b/tb/qumcu/isa/rv64um/mulw.S new file mode 100644 index 0000000..379c3f2 --- /dev/null +++ b/tb/qumcu/isa/rv64um/mulw.S @@ -0,0 +1,72 @@ +# See LICENSE for license details. + +#***************************************************************************** +# mulw.S +#----------------------------------------------------------------------------- +# +# Test mulw instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, mulw, 0x00000000, 0x00000000, 0x00000000 ); + TEST_RR_OP( 3, mulw, 0x00000001, 0x00000001, 0x00000001 ); + TEST_RR_OP( 4, mulw, 0x00000015, 0x00000003, 0x00000007 ); + + TEST_RR_OP( 5, mulw, 0x0000000000000000, 0x0000000000000000, 0xffffffffffff8000 ); + TEST_RR_OP( 6, mulw, 0x0000000000000000, 0xffffffff80000000, 0x00000000 ); + TEST_RR_OP( 7, mulw, 0x0000000000000000, 0xffffffff80000000, 0xffffffffffff8000 ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 8, mulw, 143, 13, 11 ); + TEST_RR_SRC2_EQ_DEST( 9, mulw, 154, 14, 11 ); + TEST_RR_SRC12_EQ_DEST( 10, mulw, 169, 13 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 11, 0, mulw, 143, 13, 11 ); + TEST_RR_DEST_BYPASS( 12, 1, mulw, 154, 14, 11 ); + TEST_RR_DEST_BYPASS( 13, 2, mulw, 165, 15, 11 ); + + TEST_RR_SRC12_BYPASS( 14, 0, 0, mulw, 143, 13, 11 ); + TEST_RR_SRC12_BYPASS( 15, 0, 1, mulw, 154, 14, 11 ); + TEST_RR_SRC12_BYPASS( 16, 0, 2, mulw, 165, 15, 11 ); + TEST_RR_SRC12_BYPASS( 17, 1, 0, mulw, 143, 13, 11 ); + TEST_RR_SRC12_BYPASS( 18, 1, 1, mulw, 154, 14, 11 ); + TEST_RR_SRC12_BYPASS( 19, 2, 0, mulw, 165, 15, 11 ); + + TEST_RR_SRC21_BYPASS( 20, 0, 0, mulw, 143, 13, 11 ); + TEST_RR_SRC21_BYPASS( 21, 0, 1, mulw, 154, 14, 11 ); + TEST_RR_SRC21_BYPASS( 22, 0, 2, mulw, 165, 15, 11 ); + TEST_RR_SRC21_BYPASS( 23, 1, 0, mulw, 143, 13, 11 ); + TEST_RR_SRC21_BYPASS( 24, 1, 1, mulw, 154, 14, 11 ); + TEST_RR_SRC21_BYPASS( 25, 2, 0, mulw, 165, 15, 11 ); + + TEST_RR_ZEROSRC1( 26, mulw, 0, 31 ); + TEST_RR_ZEROSRC2( 27, mulw, 0, 32 ); + TEST_RR_ZEROSRC12( 28, mulw, 0 ); + TEST_RR_ZERODEST( 29, mulw, 33, 34 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64um/rem.S b/tb/qumcu/isa/rv64um/rem.S new file mode 100644 index 0000000..e3248ff --- /dev/null +++ b/tb/qumcu/isa/rv64um/rem.S @@ -0,0 +1,41 @@ +# See LICENSE for license details. + +#***************************************************************************** +# rem.S +#----------------------------------------------------------------------------- +# +# Test rem instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, rem, 2, 20, 6 ); + TEST_RR_OP( 3, rem, -2, -20, 6 ); + TEST_RR_OP( 4, rem, 2, 20, -6 ); + TEST_RR_OP( 5, rem, -2, -20, -6 ); + + TEST_RR_OP( 6, rem, 0, -1<<63, 1 ); + TEST_RR_OP( 7, rem, 0, -1<<63, -1 ); + + TEST_RR_OP( 8, rem, -1<<63, -1<<63, 0 ); + TEST_RR_OP( 9, rem, 1, 1, 0 ); + TEST_RR_OP(10, rem, 0, 0, 0 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64um/remu.S b/tb/qumcu/isa/rv64um/remu.S new file mode 100644 index 0000000..6946d0d --- /dev/null +++ b/tb/qumcu/isa/rv64um/remu.S @@ -0,0 +1,41 @@ +# See LICENSE for license details. + +#***************************************************************************** +# remu.S +#----------------------------------------------------------------------------- +# +# Test remu instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, remu, 2, 20, 6 ); + TEST_RR_OP( 3, remu, 2, -20, 6 ); + TEST_RR_OP( 4, remu, 20, 20, -6 ); + TEST_RR_OP( 5, remu, -20, -20, -6 ); + + TEST_RR_OP( 6, remu, 0, -1<<63, 1 ); + TEST_RR_OP( 7, remu, -1<<63, -1<<63, -1 ); + + TEST_RR_OP( 8, remu, -1<<63, -1<<63, 0 ); + TEST_RR_OP( 9, remu, 1, 1, 0 ); + TEST_RR_OP(10, remu, 0, 0, 0 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64um/remuw.S b/tb/qumcu/isa/rv64um/remuw.S new file mode 100644 index 0000000..334b5c5 --- /dev/null +++ b/tb/qumcu/isa/rv64um/remuw.S @@ -0,0 +1,41 @@ +# See LICENSE for license details. + +#***************************************************************************** +# remuw.S +#----------------------------------------------------------------------------- +# +# Test remuw instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, remuw, 2, 20, 6 ); + TEST_RR_OP( 3, remuw, 2, -20, 6 ); + TEST_RR_OP( 4, remuw, 20, 20, -6 ); + TEST_RR_OP( 5, remuw, -20, -20, -6 ); + + TEST_RR_OP( 6, remuw, 0, -1<<31, 1 ); + TEST_RR_OP( 7, remuw, -1<<31, -1<<31, -1 ); + + TEST_RR_OP( 8, remuw, -1<<31, -1<<31, 0 ); + TEST_RR_OP( 9, remuw, 1, 1, 0 ); + TEST_RR_OP(10, remuw, 0, 0, 0 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64um/remw.S b/tb/qumcu/isa/rv64um/remw.S new file mode 100644 index 0000000..3ae8e3d --- /dev/null +++ b/tb/qumcu/isa/rv64um/remw.S @@ -0,0 +1,42 @@ +# See LICENSE for license details. + +#***************************************************************************** +# remw.S +#----------------------------------------------------------------------------- +# +# Test remw instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, remw, 2, 20, 6 ); + TEST_RR_OP( 3, remw, -2, -20, 6 ); + TEST_RR_OP( 4, remw, 2, 20, -6 ); + TEST_RR_OP( 5, remw, -2, -20, -6 ); + + TEST_RR_OP( 6, remw, 0, -1<<31, 1 ); + TEST_RR_OP( 7, remw, 0, -1<<31, -1 ); + + TEST_RR_OP( 8, remw, -1<<31, -1<<31, 0 ); + TEST_RR_OP( 9, remw, 1, 1, 0 ); + TEST_RR_OP(10, remw, 0, 0, 0 ); + TEST_RR_OP(11, remw, 0xfffffffffffff897,0xfffffffffffff897, 0 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64uzba/Makefrag b/tb/qumcu/isa/rv64uzba/Makefrag new file mode 100644 index 0000000..a2428f3 --- /dev/null +++ b/tb/qumcu/isa/rv64uzba/Makefrag @@ -0,0 +1,16 @@ +#======================================================================= +# Makefrag for rv64uzba tests +#----------------------------------------------------------------------- + +rv64uzba_sc_tests = \ + add_uw \ + sh1add sh1add_uw \ + sh2add sh2add_uw \ + sh3add sh3add_uw \ + slli_uw \ + +rv64uzba_p_tests = $(addprefix rv64uzba-p-, $(rv64uzba_sc_tests)) +rv64uzba_v_tests = $(addprefix rv64uzba-v-, $(rv64uzba_sc_tests)) +rv64uzba_ps_tests = $(addprefix rv64uzba-ps-, $(rv64uzba_sc_tests)) + +spike_tests += $(rv64uzba_p_tests) $(rv64uzba_v_tests) diff --git a/tb/qumcu/isa/rv64uzba/add_uw.S b/tb/qumcu/isa/rv64uzba/add_uw.S new file mode 100644 index 0000000..cd89628 --- /dev/null +++ b/tb/qumcu/isa/rv64uzba/add_uw.S @@ -0,0 +1,85 @@ +# See LICENSE for license details. + +#***************************************************************************** +# add_uw.S +#----------------------------------------------------------------------------- +# +# Test add.uw instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, add.uw, 0x00000000, 0x00000000, 0x00000000 ); + TEST_RR_OP( 3, add.uw, 0x00000002, 0x00000001, 0x00000001 ); + TEST_RR_OP( 4, add.uw, 0x0000000a, 0x00000003, 0x00000007 ); + + TEST_RR_OP( 5, add.uw, 0xffffffffffff8000, 0x0000000000000000, 0xffffffffffff8000 ); + TEST_RR_OP( 6, add.uw, 0x0000000080000000, 0xffffffff80000000, 0x00000000 ); + TEST_RR_OP( 7, add.uw, 0x000000007fff8000, 0xffffffff80000000, 0xffffffffffff8000 ); + + TEST_RR_OP( 8, add.uw, 0x0000000000007fff, 0x0000000000000000, 0x0000000000007fff ); + TEST_RR_OP( 9, add.uw, 0x000000007fffffff, 0x000000007fffffff, 0x0000000000000000 ); + TEST_RR_OP( 10, add.uw, 0x0000000080007ffe, 0x000000007fffffff, 0x0000000000007fff ); + + TEST_RR_OP( 11, add.uw, 0x0000000080007fff, 0xffffffff80000000, 0x0000000000007fff ); + TEST_RR_OP( 12, add.uw, 0x000000007fff7fff, 0x000000007fffffff, 0xffffffffffff8000 ); + + TEST_RR_OP( 13, add.uw, 0xffffffffffffffff, 0x0000000000000000, 0xffffffffffffffff ); + TEST_RR_OP( 14, add.uw, 0x0000000100000000, 0xffffffffffffffff, 0x0000000000000001 ); + TEST_RR_OP( 15, add.uw, 0x00000000fffffffe, 0xffffffffffffffff, 0xffffffffffffffff ); + + TEST_RR_OP( 16, add.uw, 0x0000000080000000, 0x0000000000000001, 0x000000007fffffff ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 17, add.uw, 24, 13, 11 ); + TEST_RR_SRC2_EQ_DEST( 18, add.uw, 25, 14, 11 ); + TEST_RR_SRC12_EQ_DEST( 19, add.uw, 26, 13 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 20, 0, add.uw, 24, 13, 11 ); + TEST_RR_DEST_BYPASS( 21, 1, add.uw, 25, 14, 11 ); + TEST_RR_DEST_BYPASS( 22, 2, add.uw, 26, 15, 11 ); + + TEST_RR_SRC12_BYPASS( 23, 0, 0, add.uw, 24, 13, 11 ); + TEST_RR_SRC12_BYPASS( 24, 0, 1, add.uw, 25, 14, 11 ); + TEST_RR_SRC12_BYPASS( 25, 0, 2, add.uw, 26, 15, 11 ); + TEST_RR_SRC12_BYPASS( 26, 1, 0, add.uw, 24, 13, 11 ); + TEST_RR_SRC12_BYPASS( 27, 1, 1, add.uw, 25, 14, 11 ); + TEST_RR_SRC12_BYPASS( 28, 2, 0, add.uw, 26, 15, 11 ); + + TEST_RR_SRC21_BYPASS( 29, 0, 0, add.uw, 24, 13, 11 ); + TEST_RR_SRC21_BYPASS( 30, 0, 1, add.uw, 25, 14, 11 ); + TEST_RR_SRC21_BYPASS( 31, 0, 2, add.uw, 26, 15, 11 ); + TEST_RR_SRC21_BYPASS( 32, 1, 0, add.uw, 24, 13, 11 ); + TEST_RR_SRC21_BYPASS( 33, 1, 1, add.uw, 25, 14, 11 ); + TEST_RR_SRC21_BYPASS( 34, 2, 0, add.uw, 26, 15, 11 ); + + TEST_RR_ZEROSRC1( 35, add.uw, 15, 15 ); + TEST_RR_ZEROSRC2( 36, add.uw, 32, 32 ); + TEST_RR_ZEROSRC12( 37, add.uw, 0 ); + TEST_RR_ZERODEST( 38, add.uw, 16, 30 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64uzba/sh1add.S b/tb/qumcu/isa/rv64uzba/sh1add.S new file mode 100644 index 0000000..1ccaf77 --- /dev/null +++ b/tb/qumcu/isa/rv64uzba/sh1add.S @@ -0,0 +1,85 @@ +# See LICENSE for license details. + +#***************************************************************************** +# sh1add.S +#----------------------------------------------------------------------------- +# +# Test sh1add instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, sh1add, 0x00000000, 0x00000000, 0x00000000 ); + TEST_RR_OP( 3, sh1add, 0x00000003, 0x00000001, 0x00000001 ); + TEST_RR_OP( 4, sh1add, 0x0000000d, 0x00000003, 0x00000007 ); + + TEST_RR_OP( 5, sh1add, 0xffffffffffff8000, 0x0000000000000000, 0xffffffffffff8000 ); + TEST_RR_OP( 6, sh1add, 0xffffffff00000000, 0xffffffff80000000, 0x00000000 ); + TEST_RR_OP( 7, sh1add, 0xfffffffeffff8000, 0xffffffff80000000, 0xffffffffffff8000 ); + + TEST_RR_OP( 8, sh1add, 0x0000000000007fff, 0x0000000000000000, 0x0000000000007fff ); + TEST_RR_OP( 9, sh1add, 0x00000000fffffffe, 0x000000007fffffff, 0x0000000000000000 ); + TEST_RR_OP( 10, sh1add, 0x0000000100007ffd, 0x000000007fffffff, 0x0000000000007fff ); + + TEST_RR_OP( 11, sh1add, 0xffffffff00007fff, 0xffffffff80000000, 0x0000000000007fff ); + TEST_RR_OP( 12, sh1add, 0x00000000ffff7ffe, 0x000000007fffffff, 0xffffffffffff8000 ); + + TEST_RR_OP( 13, sh1add, 0xffffffffffffffff, 0x0000000000000000, 0xffffffffffffffff ); + TEST_RR_OP( 14, sh1add, 0xffffffffffffffff, 0xffffffffffffffff, 0x0000000000000001 ); + TEST_RR_OP( 15, sh1add, 0xfffffffffffffffd, 0xffffffffffffffff, 0xffffffffffffffff ); + + TEST_RR_OP( 16, sh1add, 0x0000000080000001, 0x0000000000000001, 0x000000007fffffff ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 17, sh1add, 37, 13, 11 ); + TEST_RR_SRC2_EQ_DEST( 18, sh1add, 39, 14, 11 ); + TEST_RR_SRC12_EQ_DEST( 19, sh1add, 39, 13 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 20, 0, sh1add, 37, 13, 11 ); + TEST_RR_DEST_BYPASS( 21, 1, sh1add, 39, 14, 11 ); + TEST_RR_DEST_BYPASS( 22, 2, sh1add, 41, 15, 11 ); + + TEST_RR_SRC12_BYPASS( 23, 0, 0, sh1add, 37, 13, 11 ); + TEST_RR_SRC12_BYPASS( 24, 0, 1, sh1add, 39, 14, 11 ); + TEST_RR_SRC12_BYPASS( 25, 0, 2, sh1add, 41, 15, 11 ); + TEST_RR_SRC12_BYPASS( 26, 1, 0, sh1add, 37, 13, 11 ); + TEST_RR_SRC12_BYPASS( 27, 1, 1, sh1add, 39, 14, 11 ); + TEST_RR_SRC12_BYPASS( 28, 2, 0, sh1add, 41, 15, 11 ); + + TEST_RR_SRC21_BYPASS( 29, 0, 0, sh1add, 37, 13, 11 ); + TEST_RR_SRC21_BYPASS( 30, 0, 1, sh1add, 39, 14, 11 ); + TEST_RR_SRC21_BYPASS( 31, 0, 2, sh1add, 41, 15, 11 ); + TEST_RR_SRC21_BYPASS( 32, 1, 0, sh1add, 37, 13, 11 ); + TEST_RR_SRC21_BYPASS( 33, 1, 1, sh1add, 39, 14, 11 ); + TEST_RR_SRC21_BYPASS( 34, 2, 0, sh1add, 41, 15, 11 ); + + TEST_RR_ZEROSRC1( 35, sh1add, 15, 15 ); + TEST_RR_ZEROSRC2( 36, sh1add, 64, 32 ); + TEST_RR_ZEROSRC12( 37, sh1add, 0 ); + TEST_RR_ZERODEST( 38, sh1add, 16, 30 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64uzba/sh1add_uw.S b/tb/qumcu/isa/rv64uzba/sh1add_uw.S new file mode 100644 index 0000000..78b198d --- /dev/null +++ b/tb/qumcu/isa/rv64uzba/sh1add_uw.S @@ -0,0 +1,85 @@ +# See LICENSE for license details. + +#***************************************************************************** +# sh1add.uw.S +#----------------------------------------------------------------------------- +# +# Test sh1add.uw instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, sh1add.uw, 0x00000000, 0x00000000, 0x00000000 ); + TEST_RR_OP( 3, sh1add.uw, 0x00000003, 0x00000001, 0x00000001 ); + TEST_RR_OP( 4, sh1add.uw, 0x0000000d, 0x00000003, 0x00000007 ); + + TEST_RR_OP( 5, sh1add.uw, 0xffffffffffff8000, 0x0000000000000000, 0xffffffffffff8000 ); + TEST_RR_OP( 6, sh1add.uw, 0x0000000100000000, 0xffffffff80000000, 0x00000000 ); + TEST_RR_OP( 7, sh1add.uw, 0x00000000ffff8000, 0xffffffff80000000, 0xffffffffffff8000 ); + + TEST_RR_OP( 8, sh1add.uw, 0x0000000000007fff, 0x0000000000000000, 0x0000000000007fff ); + TEST_RR_OP( 9, sh1add.uw, 0x00000000fffffffe, 0x000000007fffffff, 0x0000000000000000 ); + TEST_RR_OP( 10, sh1add.uw, 0x0000000100007ffd, 0x000000007fffffff, 0x0000000000007fff ); + + TEST_RR_OP( 11, sh1add.uw, 0x0000000100007fff, 0xffffffff80000000, 0x0000000000007fff ); + TEST_RR_OP( 12, sh1add.uw, 0x00000000ffff7ffe, 0x000000007fffffff, 0xffffffffffff8000 ); + + TEST_RR_OP( 13, sh1add.uw, 0xffffffffffffffff, 0x0000000000000000, 0xffffffffffffffff ); + TEST_RR_OP( 14, sh1add.uw, 0x00000001ffffffff, 0xffffffffffffffff, 0x0000000000000001 ); + TEST_RR_OP( 15, sh1add.uw, 0x00000001fffffffd, 0xffffffffffffffff, 0xffffffffffffffff ); + + TEST_RR_OP( 16, sh1add.uw, 0x0000000080000001, 0x0000000000000001, 0x000000007fffffff ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 17, sh1add.uw, 37, 13, 11 ); + TEST_RR_SRC2_EQ_DEST( 18, sh1add.uw, 39, 14, 11 ); + TEST_RR_SRC12_EQ_DEST( 19, sh1add.uw, 39, 13 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 20, 0, sh1add.uw, 37, 13, 11 ); + TEST_RR_DEST_BYPASS( 21, 1, sh1add.uw, 39, 14, 11 ); + TEST_RR_DEST_BYPASS( 22, 2, sh1add.uw, 41, 15, 11 ); + + TEST_RR_SRC12_BYPASS( 23, 0, 0, sh1add.uw, 37, 13, 11 ); + TEST_RR_SRC12_BYPASS( 24, 0, 1, sh1add.uw, 39, 14, 11 ); + TEST_RR_SRC12_BYPASS( 25, 0, 2, sh1add.uw, 41, 15, 11 ); + TEST_RR_SRC12_BYPASS( 26, 1, 0, sh1add.uw, 37, 13, 11 ); + TEST_RR_SRC12_BYPASS( 27, 1, 1, sh1add.uw, 39, 14, 11 ); + TEST_RR_SRC12_BYPASS( 28, 2, 0, sh1add.uw, 41, 15, 11 ); + + TEST_RR_SRC21_BYPASS( 29, 0, 0, sh1add.uw, 37, 13, 11 ); + TEST_RR_SRC21_BYPASS( 30, 0, 1, sh1add.uw, 39, 14, 11 ); + TEST_RR_SRC21_BYPASS( 31, 0, 2, sh1add.uw, 41, 15, 11 ); + TEST_RR_SRC21_BYPASS( 32, 1, 0, sh1add.uw, 37, 13, 11 ); + TEST_RR_SRC21_BYPASS( 33, 1, 1, sh1add.uw, 39, 14, 11 ); + TEST_RR_SRC21_BYPASS( 34, 2, 0, sh1add.uw, 41, 15, 11 ); + + TEST_RR_ZEROSRC1( 35, sh1add.uw, 15, 15 ); + TEST_RR_ZEROSRC2( 36, sh1add.uw, 64, 32 ); + TEST_RR_ZEROSRC12( 37, sh1add.uw, 0 ); + TEST_RR_ZERODEST( 38, sh1add.uw, 16, 30 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64uzba/sh2add.S b/tb/qumcu/isa/rv64uzba/sh2add.S new file mode 100644 index 0000000..a8756bb --- /dev/null +++ b/tb/qumcu/isa/rv64uzba/sh2add.S @@ -0,0 +1,85 @@ +# See LICENSE for license details. + +#***************************************************************************** +# sh2add.S +#----------------------------------------------------------------------------- +# +# Test sh2add instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, sh2add, 0x00000000, 0x00000000, 0x00000000 ); + TEST_RR_OP( 3, sh2add, 0x00000005, 0x00000001, 0x00000001 ); + TEST_RR_OP( 4, sh2add, 0x00000013, 0x00000003, 0x00000007 ); + + TEST_RR_OP( 5, sh2add, 0xffffffffffff8000, 0x0000000000000000, 0xffffffffffff8000 ); + TEST_RR_OP( 6, sh2add, 0xfffffffe00000000, 0xffffffff80000000, 0x00000000 ); + TEST_RR_OP( 7, sh2add, 0xfffffffdffff8000, 0xffffffff80000000, 0xffffffffffff8000 ); + + TEST_RR_OP( 8, sh2add, 0x0000000000007fff, 0x0000000000000000, 0x0000000000007fff ); + TEST_RR_OP( 9, sh2add, 0x00000001fffffffc, 0x000000007fffffff, 0x0000000000000000 ); + TEST_RR_OP( 10, sh2add, 0x0000000200007ffb, 0x000000007fffffff, 0x0000000000007fff ); + + TEST_RR_OP( 11, sh2add, 0xfffffffe00007fff, 0xffffffff80000000, 0x0000000000007fff ); + TEST_RR_OP( 12, sh2add, 0x00000001ffff7ffc, 0x000000007fffffff, 0xffffffffffff8000 ); + + TEST_RR_OP( 13, sh2add, 0xffffffffffffffff, 0x0000000000000000, 0xffffffffffffffff ); + TEST_RR_OP( 14, sh2add, 0xfffffffffffffffd, 0xffffffffffffffff, 0x0000000000000001 ); + TEST_RR_OP( 15, sh2add, 0xfffffffffffffffb, 0xffffffffffffffff, 0xffffffffffffffff ); + + TEST_RR_OP( 16, sh2add, 0x0000000080000003, 0x0000000000000001, 0x000000007fffffff ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 17, sh2add, 63, 13, 11 ); + TEST_RR_SRC2_EQ_DEST( 18, sh2add, 67, 14, 11 ); + TEST_RR_SRC12_EQ_DEST( 19, sh2add, 65, 13 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 20, 0, sh2add, 63, 13, 11 ); + TEST_RR_DEST_BYPASS( 21, 1, sh2add, 67, 14, 11 ); + TEST_RR_DEST_BYPASS( 22, 2, sh2add, 71, 15, 11 ); + + TEST_RR_SRC12_BYPASS( 23, 0, 0, sh2add, 63, 13, 11 ); + TEST_RR_SRC12_BYPASS( 24, 0, 1, sh2add, 67, 14, 11 ); + TEST_RR_SRC12_BYPASS( 25, 0, 2, sh2add, 71, 15, 11 ); + TEST_RR_SRC12_BYPASS( 26, 1, 0, sh2add, 63, 13, 11 ); + TEST_RR_SRC12_BYPASS( 27, 1, 1, sh2add, 67, 14, 11 ); + TEST_RR_SRC12_BYPASS( 28, 2, 0, sh2add, 71, 15, 11 ); + + TEST_RR_SRC21_BYPASS( 29, 0, 0, sh2add, 63, 13, 11 ); + TEST_RR_SRC21_BYPASS( 30, 0, 1, sh2add, 67, 14, 11 ); + TEST_RR_SRC21_BYPASS( 31, 0, 2, sh2add, 71, 15, 11 ); + TEST_RR_SRC21_BYPASS( 32, 1, 0, sh2add, 63, 13, 11 ); + TEST_RR_SRC21_BYPASS( 33, 1, 1, sh2add, 67, 14, 11 ); + TEST_RR_SRC21_BYPASS( 34, 2, 0, sh2add, 71, 15, 11 ); + + TEST_RR_ZEROSRC1( 35, sh2add, 15, 15 ); + TEST_RR_ZEROSRC2( 36, sh2add, 128, 32 ); + TEST_RR_ZEROSRC12( 37, sh2add, 0 ); + TEST_RR_ZERODEST( 38, sh2add, 16, 30 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64uzba/sh2add_uw.S b/tb/qumcu/isa/rv64uzba/sh2add_uw.S new file mode 100644 index 0000000..1da3a43 --- /dev/null +++ b/tb/qumcu/isa/rv64uzba/sh2add_uw.S @@ -0,0 +1,85 @@ +# See LICENSE for license details. + +#***************************************************************************** +# sh2add.uw.S +#----------------------------------------------------------------------------- +# +# Test sh2add.uw instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, sh2add.uw, 0x00000000, 0x00000000, 0x00000000 ); + TEST_RR_OP( 3, sh2add.uw, 0x00000005, 0x00000001, 0x00000001 ); + TEST_RR_OP( 4, sh2add.uw, 0x00000013, 0x00000003, 0x00000007 ); + + TEST_RR_OP( 5, sh2add.uw, 0xffffffffffff8000, 0x0000000000000000, 0xffffffffffff8000 ); + TEST_RR_OP( 6, sh2add.uw, 0x0000000200000000, 0xffffffff80000000, 0x00000000 ); + TEST_RR_OP( 7, sh2add.uw, 0x00000001ffff8000, 0xffffffff80000000, 0xffffffffffff8000 ); + + TEST_RR_OP( 8, sh2add.uw, 0x0000000000007fff, 0x0000000000000000, 0x0000000000007fff ); + TEST_RR_OP( 9, sh2add.uw, 0x00000001fffffffc, 0x000000007fffffff, 0x0000000000000000 ); + TEST_RR_OP( 10, sh2add.uw, 0x0000000200007ffb, 0x000000007fffffff, 0x0000000000007fff ); + + TEST_RR_OP( 11, sh2add.uw, 0x0000000200007fff, 0xffffffff80000000, 0x0000000000007fff ); + TEST_RR_OP( 12, sh2add.uw, 0x00000001ffff7ffc, 0x000000007fffffff, 0xffffffffffff8000 ); + + TEST_RR_OP( 13, sh2add.uw, 0xffffffffffffffff, 0x0000000000000000, 0xffffffffffffffff ); + TEST_RR_OP( 14, sh2add.uw, 0x00000003fffffffd, 0xffffffffffffffff, 0x0000000000000001 ); + TEST_RR_OP( 15, sh2add.uw, 0x00000003fffffffb, 0xffffffffffffffff, 0xffffffffffffffff ); + + TEST_RR_OP( 16, sh2add.uw, 0x0000000080000003, 0x0000000000000001, 0x000000007fffffff ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 17, sh2add.uw, 63, 13, 11 ); + TEST_RR_SRC2_EQ_DEST( 18, sh2add.uw, 67, 14, 11 ); + TEST_RR_SRC12_EQ_DEST( 19, sh2add.uw, 65, 13 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 20, 0, sh2add.uw, 63, 13, 11 ); + TEST_RR_DEST_BYPASS( 21, 1, sh2add.uw, 67, 14, 11 ); + TEST_RR_DEST_BYPASS( 22, 2, sh2add.uw, 71, 15, 11 ); + + TEST_RR_SRC12_BYPASS( 23, 0, 0, sh2add.uw, 63, 13, 11 ); + TEST_RR_SRC12_BYPASS( 24, 0, 1, sh2add.uw, 67, 14, 11 ); + TEST_RR_SRC12_BYPASS( 25, 0, 2, sh2add.uw, 71, 15, 11 ); + TEST_RR_SRC12_BYPASS( 26, 1, 0, sh2add.uw, 63, 13, 11 ); + TEST_RR_SRC12_BYPASS( 27, 1, 1, sh2add.uw, 67, 14, 11 ); + TEST_RR_SRC12_BYPASS( 28, 2, 0, sh2add.uw, 71, 15, 11 ); + + TEST_RR_SRC21_BYPASS( 29, 0, 0, sh2add.uw, 63, 13, 11 ); + TEST_RR_SRC21_BYPASS( 30, 0, 1, sh2add.uw, 67, 14, 11 ); + TEST_RR_SRC21_BYPASS( 31, 0, 2, sh2add.uw, 71, 15, 11 ); + TEST_RR_SRC21_BYPASS( 32, 1, 0, sh2add.uw, 63, 13, 11 ); + TEST_RR_SRC21_BYPASS( 33, 1, 1, sh2add.uw, 67, 14, 11 ); + TEST_RR_SRC21_BYPASS( 34, 2, 0, sh2add.uw, 71, 15, 11 ); + + TEST_RR_ZEROSRC1( 35, sh2add.uw, 15, 15 ); + TEST_RR_ZEROSRC2( 36, sh2add.uw, 128, 32 ); + TEST_RR_ZEROSRC12( 37, sh2add.uw, 0 ); + TEST_RR_ZERODEST( 38, sh2add.uw, 16, 30 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64uzba/sh3add.S b/tb/qumcu/isa/rv64uzba/sh3add.S new file mode 100644 index 0000000..086e07a --- /dev/null +++ b/tb/qumcu/isa/rv64uzba/sh3add.S @@ -0,0 +1,85 @@ +# See LICENSE for license details. + +#***************************************************************************** +# sh3add.S +#----------------------------------------------------------------------------- +# +# Test sh3add instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, sh3add, 0x00000000, 0x00000000, 0x00000000 ); + TEST_RR_OP( 3, sh3add, 0x00000009, 0x00000001, 0x00000001 ); + TEST_RR_OP( 4, sh3add, 0x0000001f, 0x00000003, 0x00000007 ); + + TEST_RR_OP( 5, sh3add, 0xffffffffffff8000, 0x0000000000000000, 0xffffffffffff8000 ); + TEST_RR_OP( 6, sh3add, 0xfffffffc00000000, 0xffffffff80000000, 0x00000000 ); + TEST_RR_OP( 7, sh3add, 0xfffffffbffff8000, 0xffffffff80000000, 0xffffffffffff8000 ); + + TEST_RR_OP( 8, sh3add, 0x0000000000007fff, 0x0000000000000000, 0x0000000000007fff ); + TEST_RR_OP( 9, sh3add, 0x00000003fffffff8, 0x000000007fffffff, 0x0000000000000000 ); + TEST_RR_OP( 10, sh3add, 0x0000000400007ff7, 0x000000007fffffff, 0x0000000000007fff ); + + TEST_RR_OP( 11, sh3add, 0xfffffffc00007fff, 0xffffffff80000000, 0x0000000000007fff ); + TEST_RR_OP( 12, sh3add, 0x00000003ffff7ff8, 0x000000007fffffff, 0xffffffffffff8000 ); + + TEST_RR_OP( 13, sh3add, 0xffffffffffffffff, 0x0000000000000000, 0xffffffffffffffff ); + TEST_RR_OP( 14, sh3add, 0xfffffffffffffff9, 0xffffffffffffffff, 0x0000000000000001 ); + TEST_RR_OP( 15, sh3add, 0xfffffffffffffff7, 0xffffffffffffffff, 0xffffffffffffffff ); + + TEST_RR_OP( 16, sh3add, 0x0000000080000007, 0x0000000000000001, 0x000000007fffffff ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 17, sh3add, 115, 13, 11 ); + TEST_RR_SRC2_EQ_DEST( 18, sh3add, 123, 14, 11 ); + TEST_RR_SRC12_EQ_DEST( 19, sh3add, 117, 13 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 20, 0, sh3add, 115, 13, 11 ); + TEST_RR_DEST_BYPASS( 21, 1, sh3add, 123, 14, 11 ); + TEST_RR_DEST_BYPASS( 22, 2, sh3add, 131, 15, 11 ); + + TEST_RR_SRC12_BYPASS( 23, 0, 0, sh3add, 115, 13, 11 ); + TEST_RR_SRC12_BYPASS( 24, 0, 1, sh3add, 123, 14, 11 ); + TEST_RR_SRC12_BYPASS( 25, 0, 2, sh3add, 131, 15, 11 ); + TEST_RR_SRC12_BYPASS( 26, 1, 0, sh3add, 115, 13, 11 ); + TEST_RR_SRC12_BYPASS( 27, 1, 1, sh3add, 123, 14, 11 ); + TEST_RR_SRC12_BYPASS( 28, 2, 0, sh3add, 131, 15, 11 ); + + TEST_RR_SRC21_BYPASS( 29, 0, 0, sh3add, 115, 13, 11 ); + TEST_RR_SRC21_BYPASS( 30, 0, 1, sh3add, 123, 14, 11 ); + TEST_RR_SRC21_BYPASS( 31, 0, 2, sh3add, 131, 15, 11 ); + TEST_RR_SRC21_BYPASS( 32, 1, 0, sh3add, 115, 13, 11 ); + TEST_RR_SRC21_BYPASS( 33, 1, 1, sh3add, 123, 14, 11 ); + TEST_RR_SRC21_BYPASS( 34, 2, 0, sh3add, 131, 15, 11 ); + + TEST_RR_ZEROSRC1( 35, sh3add, 15, 15 ); + TEST_RR_ZEROSRC2( 36, sh3add, 256, 32 ); + TEST_RR_ZEROSRC12( 37, sh3add, 0 ); + TEST_RR_ZERODEST( 38, sh3add, 16, 30 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64uzba/sh3add_uw.S b/tb/qumcu/isa/rv64uzba/sh3add_uw.S new file mode 100644 index 0000000..f07375f --- /dev/null +++ b/tb/qumcu/isa/rv64uzba/sh3add_uw.S @@ -0,0 +1,85 @@ +# See LICENSE for license details. + +#***************************************************************************** +# sh3add_uw.S +#----------------------------------------------------------------------------- +# +# Test sh3add.uw instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, sh3add.uw, 0x00000000, 0x00000000, 0x00000000 ); + TEST_RR_OP( 3, sh3add.uw, 0x00000009, 0x00000001, 0x00000001 ); + TEST_RR_OP( 4, sh3add.uw, 0x0000001f, 0x00000003, 0x00000007 ); + + TEST_RR_OP( 5, sh3add.uw, 0xffffffffffff8000, 0x0000000000000000, 0xffffffffffff8000 ); + TEST_RR_OP( 6, sh3add.uw, 0x0000000400000000, 0xffffffff80000000, 0x00000000 ); + TEST_RR_OP( 7, sh3add.uw, 0x00000003ffff8000, 0xffffffff80000000, 0xffffffffffff8000 ); + + TEST_RR_OP( 8, sh3add.uw, 0x0000000000007fff, 0x0000000000000000, 0x0000000000007fff ); + TEST_RR_OP( 9, sh3add.uw, 0x00000003fffffff8, 0x000000007fffffff, 0x0000000000000000 ); + TEST_RR_OP( 10, sh3add.uw, 0x0000000400007ff7, 0x000000007fffffff, 0x0000000000007fff ); + + TEST_RR_OP( 11, sh3add.uw, 0x0000000400007fff, 0xffffffff80000000, 0x0000000000007fff ); + TEST_RR_OP( 12, sh3add.uw, 0x00000003ffff7ff8, 0x000000007fffffff, 0xffffffffffff8000 ); + + TEST_RR_OP( 13, sh3add.uw, 0xffffffffffffffff, 0x0000000000000000, 0xffffffffffffffff ); + TEST_RR_OP( 14, sh3add.uw, 0x00000007fffffff9, 0xffffffffffffffff, 0x0000000000000001 ); + TEST_RR_OP( 15, sh3add.uw, 0x00000007fffffff7, 0xffffffffffffffff, 0xffffffffffffffff ); + + TEST_RR_OP( 16, sh3add.uw, 0x0000000080000007, 0x0000000000000001, 0x000000007fffffff ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 17, sh3add.uw, 115, 13, 11 ); + TEST_RR_SRC2_EQ_DEST( 18, sh3add.uw, 123, 14, 11 ); + TEST_RR_SRC12_EQ_DEST( 19, sh3add.uw, 117, 13 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 20, 0, sh3add.uw, 115, 13, 11 ); + TEST_RR_DEST_BYPASS( 21, 1, sh3add.uw, 123, 14, 11 ); + TEST_RR_DEST_BYPASS( 22, 2, sh3add.uw, 131, 15, 11 ); + + TEST_RR_SRC12_BYPASS( 23, 0, 0, sh3add.uw, 115, 13, 11 ); + TEST_RR_SRC12_BYPASS( 24, 0, 1, sh3add.uw, 123, 14, 11 ); + TEST_RR_SRC12_BYPASS( 25, 0, 2, sh3add.uw, 131, 15, 11 ); + TEST_RR_SRC12_BYPASS( 26, 1, 0, sh3add.uw, 115, 13, 11 ); + TEST_RR_SRC12_BYPASS( 27, 1, 1, sh3add.uw, 123, 14, 11 ); + TEST_RR_SRC12_BYPASS( 28, 2, 0, sh3add.uw, 131, 15, 11 ); + + TEST_RR_SRC21_BYPASS( 29, 0, 0, sh3add.uw, 115, 13, 11 ); + TEST_RR_SRC21_BYPASS( 30, 0, 1, sh3add.uw, 123, 14, 11 ); + TEST_RR_SRC21_BYPASS( 31, 0, 2, sh3add.uw, 131, 15, 11 ); + TEST_RR_SRC21_BYPASS( 32, 1, 0, sh3add.uw, 115, 13, 11 ); + TEST_RR_SRC21_BYPASS( 33, 1, 1, sh3add.uw, 123, 14, 11 ); + TEST_RR_SRC21_BYPASS( 34, 2, 0, sh3add.uw, 131, 15, 11 ); + + TEST_RR_ZEROSRC1( 35, sh3add.uw, 15, 15 ); + TEST_RR_ZEROSRC2( 36, sh3add.uw, 256, 32 ); + TEST_RR_ZEROSRC12( 37, sh3add.uw, 0 ); + TEST_RR_ZERODEST( 38, sh3add.uw, 16, 30 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64uzba/slli_uw.S b/tb/qumcu/isa/rv64uzba/slli_uw.S new file mode 100644 index 0000000..e60f912 --- /dev/null +++ b/tb/qumcu/isa/rv64uzba/slli_uw.S @@ -0,0 +1,72 @@ +# See LICENSE for license details. + +#***************************************************************************** +# slli_uw.S +#----------------------------------------------------------------------------- +# +# Test slli.uw instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_IMM_OP( 2, slli.uw, 0x0000000000000001, 0x0000000000000001, 0 ); + TEST_IMM_OP( 3, slli.uw, 0x0000000000000002, 0x0000000000000001, 1 ); + TEST_IMM_OP( 4, slli.uw, 0x0000000000000080, 0x0000000000000001, 7 ); + TEST_IMM_OP( 5, slli.uw, 0x0000000000004000, 0x0000000000000001, 14 ); + TEST_IMM_OP( 6, slli.uw, 0x0000000080000000, 0x0000000000000001, 31 ); + + TEST_IMM_OP( 7, slli.uw, 0x00000000ffffffff, 0xffffffffffffffff, 0 ); + TEST_IMM_OP( 8, slli.uw, 0x00000001fffffffe, 0xffffffffffffffff, 1 ); + TEST_IMM_OP( 9, slli.uw, 0x0000007fffffff80, 0xffffffffffffffff, 7 ); + TEST_IMM_OP( 10, slli.uw, 0x00003fffffffc000, 0xffffffffffffffff, 14 ); + TEST_IMM_OP( 11, slli.uw, 0x7fffffff80000000, 0xffffffffffffffff, 31 ); + + TEST_IMM_OP( 12, slli.uw, 0x0000000021212121, 0x0000000021212121, 0 ); + TEST_IMM_OP( 13, slli.uw, 0x0000000042424242, 0x0000000021212121, 1 ); + TEST_IMM_OP( 14, slli.uw, 0x0000001090909080, 0x0000000021212121, 7 ); + TEST_IMM_OP( 15, slli.uw, 0x0000084848484000, 0x0000000021212121, 14 ); + TEST_IMM_OP( 16, slli.uw, 0x1090909080000000, 0x0000000021212121, 31 ); + + TEST_IMM_OP( 50, slli.uw, 0x8000000000000000, 0x0000000000000001, 63 ); + TEST_IMM_OP( 51, slli.uw, 0xffffff8000000000, 0xffffffffffffffff, 39 ); + TEST_IMM_OP( 52, slli.uw, 0x0909080000000000, 0x0000000021212121, 43 ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_IMM_SRC1_EQ_DEST( 17, slli.uw, 0x00000080, 0x00000001, 7 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_IMM_DEST_BYPASS( 18, 0, slli.uw, 0x0000000000000080, 0x0000000000000001, 7 ); + TEST_IMM_DEST_BYPASS( 19, 1, slli.uw, 0x0000000000004000, 0x0000000000000001, 14 ); + TEST_IMM_DEST_BYPASS( 20, 2, slli.uw, 0x0000000080000000, 0x0000000000000001, 31 ); + + TEST_IMM_SRC1_BYPASS( 21, 0, slli.uw, 0x0000000000000080, 0x0000000000000001, 7 ); + TEST_IMM_SRC1_BYPASS( 22, 1, slli.uw, 0x0000000000004000, 0x0000000000000001, 14 ); + TEST_IMM_SRC1_BYPASS( 23, 2, slli.uw, 0x0000000080000000, 0x0000000000000001, 31 ); + + TEST_IMM_ZEROSRC1( 24, slli.uw, 0, 31 ); + TEST_IMM_ZERODEST( 25, slli.uw, 33, 20 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64uzbb/Makefrag b/tb/qumcu/isa/rv64uzbb/Makefrag new file mode 100644 index 0000000..2e93897 --- /dev/null +++ b/tb/qumcu/isa/rv64uzbb/Makefrag @@ -0,0 +1,26 @@ +#======================================================================= +# Makefrag for rv64uzbb tests +#----------------------------------------------------------------------- + +rv64uzbb_sc_tests = \ + andn \ + clz clzw \ + cpop cpopw \ + ctz ctzw \ + max maxu \ + min minu \ + orc_b \ + orn \ + rev8 \ + rol rolw \ + ror rorw \ + rori roriw \ + sext_b sext_h \ + xnor \ + zext_h \ + +rv64uzbb_p_tests = $(addprefix rv64uzbb-p-, $(rv64uzbb_sc_tests)) +rv64uzbb_v_tests = $(addprefix rv64uzbb-v-, $(rv64uzbb_sc_tests)) +rv64uzbb_ps_tests = $(addprefix rv64uzbb-ps-, $(rv64uzbb_sc_tests)) + +spike_tests += $(rv64uzbb_p_tests) $(rv64uzbb_v_tests) diff --git a/tb/qumcu/isa/rv64uzbb/andn.S b/tb/qumcu/isa/rv64uzbb/andn.S new file mode 100644 index 0000000..be7f032 --- /dev/null +++ b/tb/qumcu/isa/rv64uzbb/andn.S @@ -0,0 +1,76 @@ +# See LICENSE for license details. + +#***************************************************************************** +# andn.S +#----------------------------------------------------------------------------- +# +# Test and instruction. +# This test is forked from and.S +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Logical tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, andn, 0xfffffffff000f000, 0xffffffffff00ff00, 0x000000000f0f0f0f ); + TEST_RR_OP( 3, andn, 0x000000000f000f00, 0x000000000ff00ff0, 0xfffffffff0f0f0f0 ); + TEST_RR_OP( 4, andn, 0x0000000000f000f0, 0x0000000000ff00ff, 0x000000000f0f0f0f ); + TEST_RR_OP( 5, andn, 0x00000000000f000f, 0xfffffffff00ff00f, 0xfffffffff0f0f0f0 ); + +#if __riscv_xlen == 64 + TEST_RR_OP( 50, andn, 0x0f000f000f000f00, 0x0ff00ff00ff00ff0, 0xf0f0f0f0f0f0f0f0 ); + TEST_RR_OP( 51, andn, 0x00f000f000f000f0, 0x00ff00ff00ff00ff, 0x0f0f0f0f0f0f0f0f ); + TEST_RR_OP( 52, andn, 0x000f000f000f000f, 0xf00ff00ff00ff00f, 0xf0f0f0f0f0f0f0f0 ); +#endif + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 6, andn, 0xfffffffff000f000, 0xffffffffff00ff00, 0x000000000f0f0f0f ); + TEST_RR_SRC2_EQ_DEST( 7, andn, 0x000000000f000f00, 0x000000000ff00ff0, 0xfffffffff0f0f0f0 ); + TEST_RR_SRC12_EQ_DEST( 8, andn, 0x0000000000000000, 0xffffffffff00ff00 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 9, 0, andn, 0xfffffffff000f000, 0xffffffffff00ff00, 0x000000000f0f0f0f ); + TEST_RR_DEST_BYPASS( 10, 1, andn, 0x000000000f000f00, 0x000000000ff00ff0, 0xfffffffff0f0f0f0 ); + TEST_RR_DEST_BYPASS( 11, 2, andn, 0x0000000000f000f0, 0x0000000000ff00ff, 0x000000000f0f0f0f ); + + TEST_RR_SRC12_BYPASS( 12, 0, 0, andn, 0xfffffffff000f000, 0xffffffffff00ff00, 0x000000000f0f0f0f ); + TEST_RR_SRC12_BYPASS( 13, 0, 1, andn, 0x000000000f000f00, 0x000000000ff00ff0, 0xfffffffff0f0f0f0 ); + TEST_RR_SRC12_BYPASS( 14, 0, 2, andn, 0x0000000000f000f0, 0x0000000000ff00ff, 0x000000000f0f0f0f ); + TEST_RR_SRC12_BYPASS( 15, 1, 0, andn, 0xfffffffff000f000, 0xffffffffff00ff00, 0x000000000f0f0f0f ); + TEST_RR_SRC12_BYPASS( 16, 1, 1, andn, 0x000000000f000f00, 0x000000000ff00ff0, 0xfffffffff0f0f0f0 ); + TEST_RR_SRC12_BYPASS( 17, 2, 0, andn, 0x0000000000f000f0, 0x0000000000ff00ff, 0x000000000f0f0f0f ); + + TEST_RR_SRC21_BYPASS( 18, 0, 0, andn, 0xfffffffff000f000, 0xffffffffff00ff00, 0x000000000f0f0f0f ); + TEST_RR_SRC21_BYPASS( 19, 0, 1, andn, 0x000000000f000f00, 0x000000000ff00ff0, 0xfffffffff0f0f0f0 ); + TEST_RR_SRC21_BYPASS( 20, 0, 2, andn, 0x0000000000f000f0, 0x0000000000ff00ff, 0x000000000f0f0f0f ); + TEST_RR_SRC21_BYPASS( 21, 1, 0, andn, 0xfffffffff000f000, 0xffffffffff00ff00, 0x000000000f0f0f0f ); + TEST_RR_SRC21_BYPASS( 22, 1, 1, andn, 0x000000000f000f00, 0x000000000ff00ff0, 0xfffffffff0f0f0f0 ); + TEST_RR_SRC21_BYPASS( 23, 2, 0, andn, 0x0000000000f000f0, 0x0000000000ff00ff, 0x000000000f0f0f0f ); + + TEST_RR_ZEROSRC1( 24, andn, 0, 0xffffffffff00ff00 ); + TEST_RR_ZEROSRC2( 25, andn, 0x0000000000ff00ff, 0x0000000000ff00ff ); + TEST_RR_ZEROSRC12( 26, andn, 0 ); + TEST_RR_ZERODEST( 27, andn, 0x0000000011111111, 0x0000000022222222 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64uzbb/clz.S b/tb/qumcu/isa/rv64uzbb/clz.S new file mode 100644 index 0000000..9df6531 --- /dev/null +++ b/tb/qumcu/isa/rv64uzbb/clz.S @@ -0,0 +1,74 @@ +# See LICENSE for license details. + +#***************************************************************************** +# clz.S +#----------------------------------------------------------------------------- +# +# Test clz instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_R_OP( 2, clz, 64, 0x0000000000000000); + TEST_R_OP( 3, clz, 63, 0x0000000000000001); + TEST_R_OP( 4, clz, 62, 0x0000000000000003); + + TEST_R_OP( 5, clz, 0, 0xffffffffffff8000 ); + TEST_R_OP( 6, clz, 40, 0x0000000000800000 ); + TEST_R_OP( 7, clz, 13, 0x0004ffffffff8000 ); + + TEST_R_OP( 8, clz, 49, 0x0000000000007fff); + TEST_R_OP( 9, clz, 33, 0x000000007fffffff); + TEST_R_OP( 10, clz, 45, 0x000000000007ffff ); + + TEST_R_OP( 11, clz, 0, 0xffffffff80000000); + TEST_R_OP( 12, clz, 8, 0x00ff578f121f5000); + + TEST_R_OP( 13, clz, 0, 0x8000000000000000); + TEST_R_OP( 14, clz, 60, 0x000000000000000e); + TEST_R_OP( 15, clz, 0, 0xa000000320401341); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_R_SRC1_EQ_DEST( 16, clz, 60, 13); + TEST_R_SRC1_EQ_DEST( 17, clz, 60, 11); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_R_DEST_BYPASS( 18, 0, clz, 60, 13); + TEST_R_DEST_BYPASS( 29, 1, clz, 59, 19); + TEST_R_DEST_BYPASS( 20, 2, clz, 58, 34); + + #------------------------------------------------------------- + # Other tests + #------------------------------------------------------------- + + TEST_R_OP( 21, clz, 37, 0x00000000070f8000 ); + TEST_R_OP( 22, clz, 36, 0x0000000008008000 ); + TEST_R_OP( 23, clz, 35, 0x0000000018008000 ); + + TEST_R_OP( 24, clz, 30, 0x0000000300007fff); + TEST_R_OP( 25, clz, 29, 0x000000077fffffff); + TEST_R_OP( 26, clz, 28, 0x0000000f0007ffff); + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64uzbb/clzw.S b/tb/qumcu/isa/rv64uzbb/clzw.S new file mode 100644 index 0000000..24b659d --- /dev/null +++ b/tb/qumcu/isa/rv64uzbb/clzw.S @@ -0,0 +1,76 @@ +# See LICENSE for license details. + +#***************************************************************************** +# clzw.S +#----------------------------------------------------------------------------- +# +# Test clzw instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_R_OP( 2, clzw, 32, 0x00000000); + TEST_R_OP( 3, clzw, 31, 0x00000001); + TEST_R_OP( 4, clzw, 30, 0x00000003); + + TEST_R_OP( 5, clzw, 0, 0xffff8000 ); + TEST_R_OP( 6, clzw, 8, 0x00800000 ); + TEST_R_OP( 7, clzw, 0, 0xffff8000 ); + + TEST_R_OP( 8, clzw, 17, 0x00007fff); + TEST_R_OP( 9, clzw, 1, 0x7fffffff); + TEST_R_OP( 10, clzw, 13, 0x0007ffff ); + + TEST_R_OP( 11, clzw, 0, 0x80000000); + TEST_R_OP( 12, clzw, 3, 0x121f5000); + + TEST_R_OP( 13, clzw, 5, 0x04000000); + TEST_R_OP( 14, clzw, 28, 0x0000000e); + TEST_R_OP( 15, clzw, 2, 0x20401341); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_R_SRC1_EQ_DEST( 16, clzw, 28, 13); + TEST_R_SRC1_EQ_DEST( 17, clzw, 28, 11); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_R_DEST_BYPASS( 18, 0, clzw, 28, 13); + TEST_R_DEST_BYPASS( 29, 1, clzw, 27, 19); + TEST_R_DEST_BYPASS( 20, 2, clzw, 26, 34); + + #------------------------------------------------------------- + # Other tests + #------------------------------------------------------------- + + + TEST_R_OP( 21, clzw, 5, 0x070f8000 ); + TEST_R_OP( 22, clzw, 4, 0x08008000 ); + TEST_R_OP( 23, clzw, 3, 0x18008000 ); + + TEST_R_OP( 24, clzw, 17, 0x00007fff); + TEST_R_OP( 25, clzw, 1, 0x7fffffff); + TEST_R_OP( 26, clzw, 13, 0x0007ffff); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64uzbb/cpop.S b/tb/qumcu/isa/rv64uzbb/cpop.S new file mode 100644 index 0000000..0083a1a --- /dev/null +++ b/tb/qumcu/isa/rv64uzbb/cpop.S @@ -0,0 +1,75 @@ +# See LICENSE for license details. + +#***************************************************************************** +# cpop.S +#----------------------------------------------------------------------------- +# +# Test cpop instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_R_OP( 2, cpop, 0, 0x0000000000000000); + TEST_R_OP( 3, cpop, 1, 0x0000000000000001); + TEST_R_OP( 4, cpop, 2, 0x0000000000000003); + + TEST_R_OP( 5, cpop, 49, 0xffffffffffff8000 ); + TEST_R_OP( 6, cpop, 1, 0x0000000000800000 ); + TEST_R_OP( 7, cpop, 34, 0x0004ffffffff8000 ); + + TEST_R_OP( 8, cpop, 15, 0x0000000000007fff); + TEST_R_OP( 9, cpop, 31, 0x000000007fffffff); + TEST_R_OP( 10, cpop, 19, 0x000000000007ffff ); + + TEST_R_OP( 11, cpop, 33, 0xffffffff80000000); + TEST_R_OP( 12, cpop, 27, 0x00ff578f121f5000); + + TEST_R_OP( 13, cpop, 1, 0x8000000000000000); + TEST_R_OP( 14, cpop, 3, 0x000000000000000e); + TEST_R_OP( 15, cpop, 11, 0xa000000320401341); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_R_SRC1_EQ_DEST( 16, cpop, 3, 13); + TEST_R_SRC1_EQ_DEST( 17, cpop, 3, 11); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_R_DEST_BYPASS( 18, 0, cpop, 3, 13); + TEST_R_DEST_BYPASS( 29, 1, cpop, 3, 19); + TEST_R_DEST_BYPASS( 20, 2, cpop, 2, 34); + + #------------------------------------------------------------- + # Other tests + #------------------------------------------------------------- + + TEST_R_OP( 21, cpop, 8, 0x00000000007f8000 ); + TEST_R_OP( 22, cpop, 2, 0x0000000000808000 ); + TEST_R_OP( 23, cpop, 3, 0x0000000001808000 ); + + TEST_R_OP( 24, cpop, 17, 0x0000000300007fff); + TEST_R_OP( 25, cpop, 34, 0x000000077fffffff); + TEST_R_OP( 26, cpop, 23, 0x0000000f0007ffff); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64uzbb/cpopw.S b/tb/qumcu/isa/rv64uzbb/cpopw.S new file mode 100644 index 0000000..7b73882 --- /dev/null +++ b/tb/qumcu/isa/rv64uzbb/cpopw.S @@ -0,0 +1,75 @@ +# See LICENSE for license details. + +#***************************************************************************** +# cpopw.S +#----------------------------------------------------------------------------- +# +# Test cpopw instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_R_OP( 2, cpopw, 0, 0x00000000); + TEST_R_OP( 3, cpopw, 1, 0x00000001); + TEST_R_OP( 4, cpopw, 2, 0x00000003); + + TEST_R_OP( 5, cpopw, 17, 0xffff8000 ); + TEST_R_OP( 6, cpopw, 1, 0x00800000 ); + TEST_R_OP( 7, cpopw, 18, 0xffff6000 ); + + TEST_R_OP( 8, cpopw, 15, 0x00007fff); + TEST_R_OP( 9, cpopw, 31, 0x7fffffff); + TEST_R_OP( 10, cpopw, 19, 0x0007ffff ); + + TEST_R_OP( 11, cpopw, 1, 0x80000000); + TEST_R_OP( 12, cpopw, 9, 0x121f5000); + + TEST_R_OP( 13, cpopw, 0, 0x00000000); + TEST_R_OP( 14, cpopw, 3, 0x0000000e); + TEST_R_OP( 15, cpopw, 7, 0x20401341); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_R_SRC1_EQ_DEST( 16, cpopw, 3, 13); + TEST_R_SRC1_EQ_DEST( 17, cpopw, 3, 11); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_R_DEST_BYPASS( 18, 0, cpopw, 3, 13); + TEST_R_DEST_BYPASS( 29, 1, cpopw, 3, 19); + TEST_R_DEST_BYPASS( 20, 2, cpopw, 2, 34); + + #------------------------------------------------------------- + # Other tests + #------------------------------------------------------------- + + TEST_R_OP( 21, cpopw, 8, 0x007f8000 ); + TEST_R_OP( 22, cpopw, 2, 0x00808000 ); + TEST_R_OP( 23, cpopw, 3, 0x01808000 ); + + TEST_R_OP( 24, cpopw, 17, 0x30007fff); + TEST_R_OP( 25, cpopw, 30, 0x77ffffff); + TEST_R_OP( 26, cpopw, 19, 0x0007ffff); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64uzbb/ctz.S b/tb/qumcu/isa/rv64uzbb/ctz.S new file mode 100644 index 0000000..21b2426 --- /dev/null +++ b/tb/qumcu/isa/rv64uzbb/ctz.S @@ -0,0 +1,75 @@ +# See LICENSE for license details. + +#***************************************************************************** +# ctz.S +#----------------------------------------------------------------------------- +# +# Test ctz instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_R_OP( 2, ctz, 64, 0x0000000000000000); + TEST_R_OP( 3, ctz, 0, 0x0000000000000001); + TEST_R_OP( 4, ctz, 0, 0x0000000000000003); + + TEST_R_OP( 5, ctz, 15, 0xffffffffffff8000 ); + TEST_R_OP( 6, ctz, 23, 0x0000000000800000 ); + TEST_R_OP( 7, ctz, 15, 0x0004ffffffff8000 ); + + TEST_R_OP( 8, ctz, 0, 0x0000000000007fff); + TEST_R_OP( 9, ctz, 0, 0x000000007fffffff); + TEST_R_OP( 10, ctz, 0, 0x000000000007ffff ); + + TEST_R_OP( 11, ctz, 31, 0xffffffff80000000); + TEST_R_OP( 12, ctz, 12, 0x00ff578f121f5000); + + TEST_R_OP( 13, ctz, 63, 0x8000000000000000); + TEST_R_OP( 14, ctz, 1, 0x000000000000000e); + TEST_R_OP( 15, ctz, 0, 0xa000000320401341); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_R_SRC1_EQ_DEST( 16, ctz, 0, 13); + TEST_R_SRC1_EQ_DEST( 17, ctz, 0, 11); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_R_DEST_BYPASS( 18, 0, ctz, 0, 13); + TEST_R_DEST_BYPASS( 29, 1, ctz, 0, 19); + TEST_R_DEST_BYPASS( 20, 2, ctz, 1, 34); + + #------------------------------------------------------------- + # Other tests + #------------------------------------------------------------- + + TEST_R_OP( 21, ctz, 15, 0x00000000007f8000 ); + TEST_R_OP( 22, ctz, 15, 0x0000000000808000 ); + TEST_R_OP( 23, ctz, 12, 0x0000000001809000 ); + + TEST_R_OP( 24, ctz, 0, 0x0000000300007fff); + TEST_R_OP( 25, ctz, 0, 0x000000077fffffff); + TEST_R_OP( 26, ctz, 0, 0x0000000f0007ffff); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64uzbb/ctzw.S b/tb/qumcu/isa/rv64uzbb/ctzw.S new file mode 100644 index 0000000..9915bf1 --- /dev/null +++ b/tb/qumcu/isa/rv64uzbb/ctzw.S @@ -0,0 +1,75 @@ +# See LICENSE for license details. + +#***************************************************************************** +# ctzw.S +#----------------------------------------------------------------------------- +# +# Test ctzw instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_R_OP( 2, ctzw, 32, 0x00000000); + TEST_R_OP( 3, ctzw, 0, 0x00000001); + TEST_R_OP( 4, ctzw, 0, 0x00000003); + + TEST_R_OP( 5, ctzw, 15, 0xffff8000 ); + TEST_R_OP( 6, ctzw, 23, 0x00800000 ); + TEST_R_OP( 7, ctzw, 15, 0xffff8000 ); + + TEST_R_OP( 8, ctzw, 0, 0x00007fff); + TEST_R_OP( 9, ctzw, 0, 0x7fffffff); + TEST_R_OP( 10, ctzw, 0, 0x0007ffff ); + + TEST_R_OP( 11, ctzw, 31, 0x80000000); + TEST_R_OP( 12, ctzw, 12, 0x121f5000); + + TEST_R_OP( 13, ctzw, 30, 0xc0000000); + TEST_R_OP( 14, ctzw, 1, 0x0000000e); + TEST_R_OP( 15, ctzw, 0, 0x20401341); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_R_SRC1_EQ_DEST( 16, ctzw, 0, 13); + TEST_R_SRC1_EQ_DEST( 17, ctzw, 0, 11); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_R_DEST_BYPASS( 18, 0, ctzw, 0, 13); + TEST_R_DEST_BYPASS( 29, 1, ctzw, 0, 19); + TEST_R_DEST_BYPASS( 20, 2, ctzw, 1, 34); + + #------------------------------------------------------------- + # Other tests + #------------------------------------------------------------- + + TEST_R_OP( 21, ctzw, 15, 0x007f8000 ); + TEST_R_OP( 22, ctzw, 15, 0x00808000 ); + TEST_R_OP( 23, ctzw, 12, 0x01809000 ); + + TEST_R_OP( 24, ctzw, 0, 0x00007fff); + TEST_R_OP( 25, ctzw, 0, 0x7fffffff); + TEST_R_OP( 26, ctzw, 0, 0x0007ffff); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64uzbb/max.S b/tb/qumcu/isa/rv64uzbb/max.S new file mode 100644 index 0000000..92eb9ad --- /dev/null +++ b/tb/qumcu/isa/rv64uzbb/max.S @@ -0,0 +1,84 @@ +# See LICENSE for license details. + +#***************************************************************************** +# max.S +#----------------------------------------------------------------------------- +# +# Test max instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, max, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000 ); + TEST_RR_OP( 3, max, 0x0000000000000001, 0x0000000000000001, 0x0000000000000001 ); + TEST_RR_OP( 4, max, 0x0000000000000007, 0x0000000000000003, 0x0000000000000007 ); + TEST_RR_OP( 5, max, 0x0000000000000007, 0x0000000000000007, 0x0000000000000003 ); + + TEST_RR_OP( 6, max, 0x0000000000000000, 0x0000000000000000, 0xffffffffffff8000 ); + TEST_RR_OP( 7, max, 0x0000000000000000, 0xffffffff80000000, 0x0000000000000000 ); + TEST_RR_OP( 8, max, 0xffffffffffff8000, 0xffffffff80000000, 0xffffffffffff8000 ); + + TEST_RR_OP( 9, max, 0x0000000000007fff, 0x0000000000000000, 0x0000000000007fff ); + TEST_RR_OP( 10, max, 0x000000007fffffff, 0x000000007fffffff, 0x0000000000000000 ); + TEST_RR_OP( 11, max, 0x000000007fffffff, 0x000000007fffffff, 0x0000000000007fff ); + + TEST_RR_OP( 12, max, 0x0000000000007fff, 0xffffffff80000000, 0x0000000000007fff ); + TEST_RR_OP( 13, max, 0x000000007fffffff, 0x000000007fffffff, 0xffffffffffff8000 ); + + TEST_RR_OP( 14, max, 0x0000000000000000, 0x0000000000000000, 0xffffffffffffffff ); + TEST_RR_OP( 15, max, 0x0000000000000001, 0xffffffffffffffff, 0x0000000000000001 ); + TEST_RR_OP( 16, max, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 17, max, 14, 14, 13 ); + TEST_RR_SRC2_EQ_DEST( 18, max, 13, 11, 13 ); + TEST_RR_SRC12_EQ_DEST( 19, max, 13, 13 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 20, 0, max, 13, 11, 13 ); + TEST_RR_DEST_BYPASS( 21, 1, max, 14, 14, 13 ); + TEST_RR_DEST_BYPASS( 22, 2, max, 13, 12, 13 ); + + TEST_RR_SRC12_BYPASS( 23, 0, 0, max, 14, 14, 13 ); + TEST_RR_SRC12_BYPASS( 24, 0, 1, max, 13, 11, 13 ); + TEST_RR_SRC12_BYPASS( 25, 0, 2, max, 15, 15, 13 ); + TEST_RR_SRC12_BYPASS( 26, 1, 0, max, 13, 10, 13 ); + TEST_RR_SRC12_BYPASS( 27, 1, 1, max, 16, 16, 13 ); + TEST_RR_SRC12_BYPASS( 28, 2, 0, max, 13, 9, 13 ); + + TEST_RR_SRC21_BYPASS( 29, 0, 0, max, 17, 17, 13 ); + TEST_RR_SRC21_BYPASS( 30, 0, 1, max, 13, 8, 13 ); + TEST_RR_SRC21_BYPASS( 31, 0, 2, max, 18, 18, 13 ); + TEST_RR_SRC21_BYPASS( 32, 1, 0, max, 13, 7, 13 ); + TEST_RR_SRC21_BYPASS( 33, 1, 1, max, 19, 19, 13 ); + TEST_RR_SRC21_BYPASS( 34, 2, 0, max, 13, 6, 13 ); + + TEST_RR_ZEROSRC1( 35, max, 0, -1 ); + TEST_RR_ZEROSRC2( 36, max, 0, -1 ); + TEST_RR_ZEROSRC12( 37, max, 0 ); + TEST_RR_ZERODEST( 38, max, 16, 30 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64uzbb/maxu.S b/tb/qumcu/isa/rv64uzbb/maxu.S new file mode 100644 index 0000000..78c2055 --- /dev/null +++ b/tb/qumcu/isa/rv64uzbb/maxu.S @@ -0,0 +1,84 @@ +# See LICENSE for license details. + +#***************************************************************************** +# maxu.S +#----------------------------------------------------------------------------- +# +# Test maxu instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, maxu, 0x00000000, 0x00000000, 0x00000000 ); + TEST_RR_OP( 3, maxu, 0x00000001, 0x00000001, 0x00000001 ); + TEST_RR_OP( 4, maxu, 0x00000007, 0x00000003, 0x00000007 ); + TEST_RR_OP( 5, maxu, 0x00000007, 0x00000007, 0x00000003 ); + + TEST_RR_OP( 6, maxu, 0xffff8000, 0x00000000, 0xffff8000 ); + TEST_RR_OP( 7, maxu, 0x80000000, 0x80000000, 0x00000000 ); + TEST_RR_OP( 8, maxu, 0xffff8000, 0x80000000, 0xffff8000 ); + + TEST_RR_OP( 9, maxu, 0x00007fff, 0x00000000, 0x00007fff ); + TEST_RR_OP( 10, maxu, 0x7fffffff, 0x7fffffff, 0x00000000 ); + TEST_RR_OP( 11, maxu, 0x7fffffff, 0x7fffffff, 0x00007fff ); + + TEST_RR_OP( 12, maxu, 0x80000000, 0x80000000, 0x00007fff ); + TEST_RR_OP( 13, maxu, 0xffff8000, 0x7fffffff, 0xffff8000 ); + + TEST_RR_OP( 14, maxu, 0xffffffff, 0x00000000, 0xffffffff ); + TEST_RR_OP( 15, maxu, 0xffffffff, 0xffffffff, 0x00000001 ); + TEST_RR_OP( 16, maxu, 0xffffffff, 0xffffffff, 0xffffffff ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 17, maxu, 14, 14, 13 ); + TEST_RR_SRC2_EQ_DEST( 18, maxu, 13, 11, 13 ); + TEST_RR_SRC12_EQ_DEST( 19, maxu, 13, 13 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 20, 0, maxu, 13, 11, 13 ); + TEST_RR_DEST_BYPASS( 21, 1, maxu, 14, 14, 13 ); + TEST_RR_DEST_BYPASS( 22, 2, maxu, 13, 12, 13 ); + + TEST_RR_SRC12_BYPASS( 23, 0, 0, maxu, 14, 14, 13 ); + TEST_RR_SRC12_BYPASS( 24, 0, 1, maxu, 13, 11, 13 ); + TEST_RR_SRC12_BYPASS( 25, 0, 2, maxu, 15, 15, 13 ); + TEST_RR_SRC12_BYPASS( 26, 1, 0, maxu, 13, 10, 13 ); + TEST_RR_SRC12_BYPASS( 27, 1, 1, maxu, 16, 16, 13 ); + TEST_RR_SRC12_BYPASS( 28, 2, 0, maxu, 13, 9, 13 ); + + TEST_RR_SRC21_BYPASS( 29, 0, 0, maxu, 17, 17, 13 ); + TEST_RR_SRC21_BYPASS( 30, 0, 1, maxu, 13, 8, 13 ); + TEST_RR_SRC21_BYPASS( 31, 0, 2, maxu, 18, 18, 13 ); + TEST_RR_SRC21_BYPASS( 32, 1, 0, maxu, 13, 7, 13 ); + TEST_RR_SRC21_BYPASS( 33, 1, 1, maxu, 19, 19, 13 ); + TEST_RR_SRC21_BYPASS( 34, 2, 0, maxu, 13, 6, 13 ); + + TEST_RR_ZEROSRC1( 35, maxu, -1, -1 ); + TEST_RR_ZEROSRC2( 36, maxu, -1, -1 ); + TEST_RR_ZEROSRC12( 37, maxu, 0 ); + TEST_RR_ZERODEST( 38, maxu, 16, 30 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64uzbb/min.S b/tb/qumcu/isa/rv64uzbb/min.S new file mode 100644 index 0000000..d2e3e29 --- /dev/null +++ b/tb/qumcu/isa/rv64uzbb/min.S @@ -0,0 +1,84 @@ +# See LICENSE for license details. + +#***************************************************************************** +# min.S +#----------------------------------------------------------------------------- +# +# Test min instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, min, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000 ); + TEST_RR_OP( 3, min, 0x0000000000000001, 0x0000000000000001, 0x0000000000000001 ); + TEST_RR_OP( 4, min, 0x0000000000000003, 0x0000000000000003, 0x0000000000000007 ); + TEST_RR_OP( 5, min, 0x0000000000000003, 0x0000000000000007, 0x0000000000000003 ); + + TEST_RR_OP( 6, min, 0xffffffffffff8000, 0x0000000000000000, 0xffffffffffff8000 ); + TEST_RR_OP( 7, min, 0xffffffff80000000, 0xffffffff80000000, 0x0000000000000000 ); + TEST_RR_OP( 8, min, 0xffffffff80000000, 0xffffffff80000000, 0xffffffffffff8000 ); + + TEST_RR_OP( 9, min, 0x0000000000000000, 0x0000000000000000, 0x0000000000007fff ); + TEST_RR_OP( 10, min, 0x0000000000000000, 0x000000007fffffff, 0x0000000000000000 ); + TEST_RR_OP( 11, min, 0x0000000000007fff, 0x000000007fffffff, 0x0000000000007fff ); + + TEST_RR_OP( 12, min, 0xffffffff80000000, 0xffffffff80000000, 0x0000000000007fff ); + TEST_RR_OP( 13, min, 0xffffffffffff8000, 0x000000007fffffff, 0xffffffffffff8000 ); + + TEST_RR_OP( 14, min, 0xffffffffffffffff, 0x0000000000000000, 0xffffffffffffffff ); + TEST_RR_OP( 15, min, 0xffffffffffffffff, 0xffffffffffffffff, 0x0000000000000001 ); + TEST_RR_OP( 16, min, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 17, min, 13, 14, 13 ); + TEST_RR_SRC2_EQ_DEST( 18, min, 11, 11, 13 ); + TEST_RR_SRC12_EQ_DEST( 19, min, 13, 13 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 20, 0, min, 11, 11, 13 ); + TEST_RR_DEST_BYPASS( 21, 1, min, 13, 14, 13 ); + TEST_RR_DEST_BYPASS( 22, 2, min, 12, 12, 13 ); + + TEST_RR_SRC12_BYPASS( 23, 0, 0, min, 13, 14, 13 ); + TEST_RR_SRC12_BYPASS( 24, 0, 1, min, 11, 11, 13 ); + TEST_RR_SRC12_BYPASS( 25, 0, 2, min, 13, 15, 13 ); + TEST_RR_SRC12_BYPASS( 26, 1, 0, min, 10, 10, 13 ); + TEST_RR_SRC12_BYPASS( 27, 1, 1, min, 13, 16, 13 ); + TEST_RR_SRC12_BYPASS( 28, 2, 0, min, 9, 9, 13 ); + + TEST_RR_SRC21_BYPASS( 29, 0, 0, min, 13, 17, 13 ); + TEST_RR_SRC21_BYPASS( 30, 0, 1, min, 8, 8, 13 ); + TEST_RR_SRC21_BYPASS( 31, 0, 2, min, 13, 18, 13 ); + TEST_RR_SRC21_BYPASS( 32, 1, 0, min, 7, 7, 13 ); + TEST_RR_SRC21_BYPASS( 33, 1, 1, min, 13, 19, 13 ); + TEST_RR_SRC21_BYPASS( 34, 2, 0, min, 6, 6, 13 ); + + TEST_RR_ZEROSRC1( 35, min, -1, -1 ); + TEST_RR_ZEROSRC2( 36, min, -1, -1 ); + TEST_RR_ZEROSRC12( 37, min, 0 ); + TEST_RR_ZERODEST( 38, min, 16, 30 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64uzbb/minu.S b/tb/qumcu/isa/rv64uzbb/minu.S new file mode 100644 index 0000000..f92859a --- /dev/null +++ b/tb/qumcu/isa/rv64uzbb/minu.S @@ -0,0 +1,84 @@ +# See LICENSE for license details. + +#***************************************************************************** +# minu.S +#----------------------------------------------------------------------------- +# +# Test minu instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, minu, 0x00000000, 0x00000000, 0x00000000 ); + TEST_RR_OP( 3, minu, 0x00000001, 0x00000001, 0x00000001 ); + TEST_RR_OP( 4, minu, 0x00000003, 0x00000003, 0x00000007 ); + TEST_RR_OP( 5, minu, 0x00000003, 0x00000007, 0x00000003 ); + + TEST_RR_OP( 6, minu, 0x00000000, 0x00000000, 0xffff8000 ); + TEST_RR_OP( 7, minu, 0x00000000, 0x80000000, 0x00000000 ); + TEST_RR_OP( 8, minu, 0x80000000, 0x80000000, 0xffff8000 ); + + TEST_RR_OP( 9, minu, 0x00000000, 0x00000000, 0x00007fff ); + TEST_RR_OP( 10, minu, 0x00000000, 0x7fffffff, 0x00000000 ); + TEST_RR_OP( 11, minu, 0x00007fff, 0x7fffffff, 0x00007fff ); + + TEST_RR_OP( 12, minu, 0x00007fff, 0x80000000, 0x00007fff ); + TEST_RR_OP( 13, minu, 0x7fffffff, 0x7fffffff, 0xffff8000 ); + + TEST_RR_OP( 14, minu, 0x00000000, 0x00000000, 0xffffffff ); + TEST_RR_OP( 15, minu, 0x00000001, 0xffffffff, 0x00000001 ); + TEST_RR_OP( 16, minu, 0xffffffff, 0xffffffff, 0xffffffff ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 17, minu, 13, 14, 13 ); + TEST_RR_SRC2_EQ_DEST( 18, minu, 11, 11, 13 ); + TEST_RR_SRC12_EQ_DEST( 19, minu, 13, 13 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 20, 0, minu, 11, 11, 13 ); + TEST_RR_DEST_BYPASS( 21, 1, minu, 13, 14, 13 ); + TEST_RR_DEST_BYPASS( 22, 2, minu, 12, 12, 13 ); + + TEST_RR_SRC12_BYPASS( 23, 0, 0, minu, 13, 14, 13 ); + TEST_RR_SRC12_BYPASS( 24, 0, 1, minu, 11, 11, 13 ); + TEST_RR_SRC12_BYPASS( 25, 0, 2, minu, 13, 15, 13 ); + TEST_RR_SRC12_BYPASS( 26, 1, 0, minu, 10, 10, 13 ); + TEST_RR_SRC12_BYPASS( 27, 1, 1, minu, 13, 16, 13 ); + TEST_RR_SRC12_BYPASS( 28, 2, 0, minu, 9, 9, 13 ); + + TEST_RR_SRC21_BYPASS( 29, 0, 0, minu, 13, 17, 13 ); + TEST_RR_SRC21_BYPASS( 30, 0, 1, minu, 8, 8, 13 ); + TEST_RR_SRC21_BYPASS( 31, 0, 2, minu, 13, 18, 13 ); + TEST_RR_SRC21_BYPASS( 32, 1, 0, minu, 7, 7, 13 ); + TEST_RR_SRC21_BYPASS( 33, 1, 1, minu, 13, 19, 13 ); + TEST_RR_SRC21_BYPASS( 34, 2, 0, minu, 6, 6, 13 ); + + TEST_RR_ZEROSRC1( 35, minu, 0, -1 ); + TEST_RR_ZEROSRC2( 36, minu, 0, -1 ); + TEST_RR_ZEROSRC12( 37, minu, 0 ); + TEST_RR_ZERODEST( 38, minu, 16, 30 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64uzbb/orc_b.S b/tb/qumcu/isa/rv64uzbb/orc_b.S new file mode 100644 index 0000000..b236bd3 --- /dev/null +++ b/tb/qumcu/isa/rv64uzbb/orc_b.S @@ -0,0 +1,75 @@ +# See LICENSE for license details. + +#***************************************************************************** +# orc.b.S +#----------------------------------------------------------------------------- +# +# Test orc.b instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_R_OP( 2, orc.b, 0x0000000000000000, 0x0000000000000000); + TEST_R_OP( 3, orc.b, 0x00000000000000ff, 0x0000000000000001); + TEST_R_OP( 4, orc.b, 0x00000000000000ff, 0x0000000000000003); + + TEST_R_OP( 5, orc.b, 0xffffffffffffff00, 0xffffffffffff8000 ); + TEST_R_OP( 6, orc.b, 0x0000000000ff0000, 0x0000000000800000 ); + TEST_R_OP( 7, orc.b, 0x00ffffffffffff00, 0x0004ffffffff8000 ); + + TEST_R_OP( 8, orc.b, 0x000000000000ffff, 0x0000000000007fff); + TEST_R_OP( 9, orc.b, 0x00000000ffffffff, 0x000000007fffffff); + TEST_R_OP( 10, orc.b, 0x0000000000ffffff, 0x000000000007ffff ); + + TEST_R_OP( 11, orc.b, 0xffffffffff000000, 0xffffffff80000000); + TEST_R_OP( 12, orc.b, 0x00ffffffffffff00, 0x00ff578f121f5000); + + TEST_R_OP( 13, orc.b, 0xff00000000000000, 0x8000000000000000); + TEST_R_OP( 14, orc.b, 0x00000000000000ff, 0x000000000000000e); + TEST_R_OP( 15, orc.b, 0xff0000ffffffffff, 0xa000000320401341); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_R_SRC1_EQ_DEST( 16, orc.b, 0xff, 13); + TEST_R_SRC1_EQ_DEST( 17, orc.b, 0xff, 11); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_R_DEST_BYPASS( 18, 0, orc.b, 0xff, 13); + TEST_R_DEST_BYPASS( 29, 1, orc.b, 0xff, 19); + TEST_R_DEST_BYPASS( 20, 2, orc.b, 0xff, 34); + + #------------------------------------------------------------- + # Other tests + #------------------------------------------------------------- + + TEST_R_OP( 21, orc.b, 0x0000000000ffff00, 0x00000000007f8000 ); + TEST_R_OP( 22, orc.b, 0x0000000000ffff00, 0x0000000000808000 ); + TEST_R_OP( 23, orc.b, 0x00000000ffffff00, 0x0000000001808000 ); + + TEST_R_OP( 24, orc.b, 0x000000ff0000ffff, 0x0000000300007fff); + TEST_R_OP( 25, orc.b, 0x000000ffffffffff, 0x000000077fffffff); + TEST_R_OP( 26, orc.b, 0x000000ff00ffffff, 0x0000000f0007ffff); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64uzbb/orn.S b/tb/qumcu/isa/rv64uzbb/orn.S new file mode 100644 index 0000000..b610007 --- /dev/null +++ b/tb/qumcu/isa/rv64uzbb/orn.S @@ -0,0 +1,75 @@ +# See LICENSE for license details. + +#***************************************************************************** +# orn.S +#----------------------------------------------------------------------------- +# +# Test orn instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Logical tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, orn, 0xfffffffffff0fff0, 0xffffffffff00ff00, 0x000000000f0f0f0f ); + TEST_RR_OP( 3, orn, 0x000000000fff0fff, 0x000000000ff00ff0, 0xfffffffff0f0f0f0 ); + TEST_RR_OP( 4, orn, 0xfffffffff0fff0ff, 0x0000000000ff00ff, 0x000000000f0f0f0f ); + TEST_RR_OP( 5, orn, 0xffffffffff0fff0f, 0xfffffffff00ff00f, 0xfffffffff0f0f0f0 ); + +#if __riscv_xlen == 64 + TEST_RR_OP( 50, orn, 0x0fff0fff0fff0fff, 0x0ff00ff00ff00ff0, 0xf0f0f0f0f0f0f0f0 ); + TEST_RR_OP( 51, orn, 0xf0fff0fff0fff0ff, 0x00ff00ff00ff00ff, 0x0f0f0f0f0f0f0f0f ); + TEST_RR_OP( 52, orn, 0xff0fff0fff0fff0f, 0xf00ff00ff00ff00f, 0xf0f0f0f0f0f0f0f0 ); +#endif + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 6, orn, 0xfffffffffff0fff0, 0xffffffffff00ff00, 0x000000000f0f0f0f ); + TEST_RR_SRC2_EQ_DEST( 7, orn, 0xfffffffffff0fff0, 0xffffffffff00ff00, 0x000000000f0f0f0f ); + TEST_RR_SRC12_EQ_DEST( 8, orn, 0xffffffffffffffff, 0xffffffffff00ff00 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 9, 0, orn, 0xfffffffffff0fff0, 0xffffffffff00ff00, 0x000000000f0f0f0f ); + TEST_RR_DEST_BYPASS( 10, 1, orn, 0x000000000fff0fff, 0x000000000ff00ff0, 0xfffffffff0f0f0f0 ); + TEST_RR_DEST_BYPASS( 11, 2, orn, 0xfffffffff0fff0ff, 0x0000000000ff00ff, 0x000000000f0f0f0f ); + + TEST_RR_SRC12_BYPASS( 12, 0, 0, orn, 0xfffffffffff0fff0, 0xffffffffff00ff00, 0x000000000f0f0f0f ); + TEST_RR_SRC12_BYPASS( 13, 0, 1, orn, 0x000000000fff0fff, 0x000000000ff00ff0, 0xfffffffff0f0f0f0 ); + TEST_RR_SRC12_BYPASS( 14, 0, 2, orn, 0xfffffffff0fff0ff, 0x0000000000ff00ff, 0x000000000f0f0f0f ); + TEST_RR_SRC12_BYPASS( 15, 1, 0, orn, 0xfffffffffff0fff0, 0xffffffffff00ff00, 0x000000000f0f0f0f ); + TEST_RR_SRC12_BYPASS( 16, 1, 1, orn, 0x000000000fff0fff, 0x000000000ff00ff0, 0xfffffffff0f0f0f0 ); + TEST_RR_SRC12_BYPASS( 17, 2, 0, orn, 0xfffffffff0fff0ff, 0x0000000000ff00ff, 0x000000000f0f0f0f ); + + TEST_RR_SRC21_BYPASS( 18, 0, 0, orn, 0xfffffffffff0fff0, 0xffffffffff00ff00, 0x000000000f0f0f0f ); + TEST_RR_SRC21_BYPASS( 19, 0, 1, orn, 0x000000000fff0fff, 0x000000000ff00ff0, 0xfffffffff0f0f0f0 ); + TEST_RR_SRC21_BYPASS( 20, 0, 2, orn, 0xfffffffff0fff0ff, 0x0000000000ff00ff, 0x000000000f0f0f0f ); + TEST_RR_SRC21_BYPASS( 21, 1, 0, orn, 0xfffffffffff0fff0, 0xffffffffff00ff00, 0x000000000f0f0f0f ); + TEST_RR_SRC21_BYPASS( 22, 1, 1, orn, 0x000000000fff0fff, 0x000000000ff00ff0, 0xfffffffff0f0f0f0 ); + TEST_RR_SRC21_BYPASS( 23, 2, 0, orn, 0xfffffffff0fff0ff, 0x0000000000ff00ff, 0x000000000f0f0f0f ); + + TEST_RR_ZEROSRC1( 24, orn, 0x0000000000ff00ff, 0xffffffffff00ff00 ); + TEST_RR_ZEROSRC2( 25, orn, -1, 0x0000000000ff00ff ); + TEST_RR_ZEROSRC12( 26, orn, -1 ); + TEST_RR_ZERODEST( 27, orn, 0x0000000011111111, 0x0000000022222222 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64uzbb/rev8.S b/tb/qumcu/isa/rv64uzbb/rev8.S new file mode 100644 index 0000000..5e65f37 --- /dev/null +++ b/tb/qumcu/isa/rv64uzbb/rev8.S @@ -0,0 +1,75 @@ +# See LICENSE for license details. + +#***************************************************************************** +# rev8.S +#----------------------------------------------------------------------------- +# +# Test rev8 instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_R_OP( 2, rev8, 0x0000000000000000, 0x0000000000000000); + TEST_R_OP( 3, rev8, 0x0100000000000000, 0x0000000000000001); + TEST_R_OP( 4, rev8, 0x0300000000000000, 0x0000000000000003); + + TEST_R_OP( 5, rev8, 0x0080ffffffffffff, 0xffffffffffff8000 ); + TEST_R_OP( 6, rev8, 0x0000800000000000, 0x0000000000800000 ); + TEST_R_OP( 7, rev8, 0x0080ffffffff0400, 0x0004ffffffff8000 ); + + TEST_R_OP( 8, rev8, 0xff7f000000000000, 0x0000000000007fff); + TEST_R_OP( 9, rev8, 0xffffff7f00000000, 0x000000007fffffff); + TEST_R_OP( 10, rev8, 0xffff070000000000, 0x000000000007ffff ); + + TEST_R_OP( 11, rev8, 0x00000080ffffffff, 0xffffffff80000000); + TEST_R_OP( 12, rev8, 0x00501f128f57ff00, 0x00ff578f121f5000); + + TEST_R_OP( 13, rev8, 0x0000000000000080, 0x8000000000000000); + TEST_R_OP( 14, rev8, 0x0e00000000000000, 0x000000000000000e); + TEST_R_OP( 15, rev8, 0x41134020030000a0, 0xa000000320401341); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_R_SRC1_EQ_DEST( 16, rev8, 0x0d00000000000000, 13); + TEST_R_SRC1_EQ_DEST( 17, rev8, 0x0b00000000000000, 11); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_R_DEST_BYPASS( 18, 0, rev8, 0x0d00000000000000, 13); + TEST_R_DEST_BYPASS( 29, 1, rev8, 0x1300000000000000, 19); + TEST_R_DEST_BYPASS( 20, 2, rev8, 0x2200000000000000, 34); + + #------------------------------------------------------------- + # Other tests + #------------------------------------------------------------- + + TEST_R_OP( 21, rev8, 0x00807f0000000000, 0x00000000007f8000 ); + TEST_R_OP( 22, rev8, 0x0080800000000000, 0x0000000000808000 ); + TEST_R_OP( 23, rev8, 0x0080800100000000, 0x0000000001808000 ); + + TEST_R_OP( 24, rev8, 0xff7f000003000000, 0x0000000300007fff); + TEST_R_OP( 25, rev8, 0xffffff7f07000000, 0x000000077fffffff); + TEST_R_OP( 26, rev8, 0xffff07000f000000, 0x0000000f0007ffff); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64uzbb/rol.S b/tb/qumcu/isa/rv64uzbb/rol.S new file mode 100644 index 0000000..a69bc05 --- /dev/null +++ b/tb/qumcu/isa/rv64uzbb/rol.S @@ -0,0 +1,96 @@ +# See LICENSE for license details. + +#***************************************************************************** +# rol.S +#----------------------------------------------------------------------------- +# +# Test rol instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, rol, 0x0000000000000001, 0x0000000000000001, 0 ); + TEST_RR_OP( 3, rol, 0x0000000000000002, 0x0000000000000001, 1 ); + TEST_RR_OP( 4, rol, 0x0000000000000080, 0x0000000000000001, 7 ); + TEST_RR_OP( 5, rol, 0x0000000000004000, 0x0000000000000001, 14 ); + TEST_RR_OP( 6, rol, 0x0000000080000000, 0x0000000000000001, 31 ); + + TEST_RR_OP( 7, rol, 0xffffffffffffffff, 0xffffffffffffffff, 0 ); + TEST_RR_OP( 8, rol, 0xffffffffffffffff, 0xffffffffffffffff, 1 ); + TEST_RR_OP( 9, rol, 0xffffffffffffffff, 0xffffffffffffffff, 7 ); + TEST_RR_OP( 10, rol, 0xffffffffffffffff, 0xffffffffffffffff, 14 ); + TEST_RR_OP( 11, rol, 0xffffffffffffffff, 0xffffffffffffffff, 31 ); + + TEST_RR_OP( 12, rol, 0x0000000021212121, 0x0000000021212121, 0 ); + TEST_RR_OP( 13, rol, 0x0000000042424242, 0x0000000021212121, 1 ); + TEST_RR_OP( 14, rol, 0x0000001090909080, 0x0000000021212121, 7 ); + TEST_RR_OP( 15, rol, 0x0000084848484000, 0x0000000021212121, 14 ); + TEST_RR_OP( 16, rol, 0x1090909080000000, 0x0000000021212121, 31 ); + + # Verify that rotates only use bottom six(rv64) or five(rv32) bits + + TEST_RR_OP( 17, rol, 0x0000000021212121, 0x0000000021212121, 0xffffffffffffffc0 ); + TEST_RR_OP( 18, rol, 0x0000000042424242, 0x0000000021212121, 0xffffffffffffffc1 ); + TEST_RR_OP( 19, rol, 0x0000001090909080, 0x0000000021212121, 0xffffffffffffffc7 ); + TEST_RR_OP( 20, rol, 0x0000084848484000, 0x0000000021212121, 0xffffffffffffffce ); + +#if __riscv_xlen == 64 + TEST_RR_OP( 21, rol, 0x8000000010909090, 0x0000000021212121, 0xffffffffffffffff ); + TEST_RR_OP( 50, rol, 0x8000000000000000, 0x0000000000000001, 63 ); + TEST_RR_OP( 51, rol, 0xffffffffffffffff, 0xffffffffffffffff, 39 ); + TEST_RR_OP( 52, rol, 0x0909080000000109, 0x0000000021212121, 43 ); +#endif + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 22, rol, 0x00000080, 0x00000001, 7 ); + TEST_RR_SRC2_EQ_DEST( 23, rol, 0x00004000, 0x00000001, 14 ); + TEST_RR_SRC12_EQ_DEST( 24, rol, 24, 3 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 25, 0, rol, 0x0000000000000080, 0x0000000000000001, 7 ); + TEST_RR_DEST_BYPASS( 26, 1, rol, 0x0000000000004000, 0x0000000000000001, 14 ); + TEST_RR_DEST_BYPASS( 27, 2, rol, 0x0000000080000000, 0x0000000000000001, 31 ); + + TEST_RR_SRC12_BYPASS( 28, 0, 0, rol, 0x0000000000000080, 0x0000000000000001, 7 ); + TEST_RR_SRC12_BYPASS( 29, 0, 1, rol, 0x0000000000004000, 0x0000000000000001, 14 ); + TEST_RR_SRC12_BYPASS( 30, 0, 2, rol, 0x0000000080000000, 0x0000000000000001, 31 ); + TEST_RR_SRC12_BYPASS( 31, 1, 0, rol, 0x0000000000000080, 0x0000000000000001, 7 ); + TEST_RR_SRC12_BYPASS( 32, 1, 1, rol, 0x0000000000004000, 0x0000000000000001, 14 ); + TEST_RR_SRC12_BYPASS( 33, 2, 0, rol, 0x0000000080000000, 0x0000000000000001, 31 ); + + TEST_RR_SRC21_BYPASS( 34, 0, 0, rol, 0x0000000000000080, 0x0000000000000001, 7 ); + TEST_RR_SRC21_BYPASS( 35, 0, 1, rol, 0x0000000000004000, 0x0000000000000001, 14 ); + TEST_RR_SRC21_BYPASS( 36, 0, 2, rol, 0x0000000080000000, 0x0000000000000001, 31 ); + TEST_RR_SRC21_BYPASS( 37, 1, 0, rol, 0x0000000000000080, 0x0000000000000001, 7 ); + TEST_RR_SRC21_BYPASS( 38, 1, 1, rol, 0x0000000000004000, 0x0000000000000001, 14 ); + TEST_RR_SRC21_BYPASS( 39, 2, 0, rol, 0x0000000080000000, 0x0000000000000001, 31 ); + + TEST_RR_ZEROSRC1( 40, rol, 0, 15 ); + TEST_RR_ZEROSRC2( 41, rol, 32, 32 ); + TEST_RR_ZEROSRC12( 42, rol, 0 ); + TEST_RR_ZERODEST( 43, rol, 1024, 2048 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64uzbb/rolw.S b/tb/qumcu/isa/rv64uzbb/rolw.S new file mode 100644 index 0000000..fdf4674 --- /dev/null +++ b/tb/qumcu/isa/rv64uzbb/rolw.S @@ -0,0 +1,97 @@ +# See LICENSE for license details. + +#***************************************************************************** +# rolw.S +#----------------------------------------------------------------------------- +# +# Test rolw instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, rolw, 0x0000000000000001, 0x0000000000000001, 0 ); + TEST_RR_OP( 3, rolw, 0x0000000000000002, 0x0000000000000001, 1 ); + TEST_RR_OP( 4, rolw, 0x0000000000000080, 0x0000000000000001, 7 ); + TEST_RR_OP( 5, rolw, 0x0000000000004000, 0x0000000000000001, 14 ); + TEST_RR_OP( 6, rolw, 0xffffffff80000000, 0x0000000000000001, 31 ); + + TEST_RR_OP( 7, rolw, 0xffffffffffffffff, 0xffffffffffffffff, 0 ); + TEST_RR_OP( 8, rolw, 0xffffffffffffffff, 0xffffffffffffffff, 1 ); + TEST_RR_OP( 9, rolw, 0xffffffffffffffff, 0xffffffffffffffff, 7 ); + TEST_RR_OP( 10, rolw, 0xffffffffffffffff, 0xffffffffffffffff, 14 ); + TEST_RR_OP( 11, rolw, 0xffffffffffffffff, 0xffffffffffffffff, 31 ); + + TEST_RR_OP( 12, rolw, 0x0000000021212121, 0x0000000021212121, 0 ); + TEST_RR_OP( 13, rolw, 0x0000000042424242, 0x0000000021212121, 1 ); + TEST_RR_OP( 14, rolw, 0xffffffff90909090, 0x0000000021212121, 7 ); + TEST_RR_OP( 15, rolw, 0x0000000048484848, 0x0000000021212121, 14 ); + TEST_RR_OP( 16, rolw, 0xffffffff90909090, 0x0000000021212121, 31 ); + + # Verify that rotates only use bottom five bits + + TEST_RR_OP( 17, rolw, 0x0000000021212121, 0x0000000021212121, 0xffffffffffffffe0 ); + TEST_RR_OP( 18, rolw, 0x0000000042424242, 0x0000000021212121, 0xffffffffffffffe1 ); + TEST_RR_OP( 19, rolw, 0xffffffff90909090, 0x0000000021212121, 0xffffffffffffffe7 ); + TEST_RR_OP( 20, rolw, 0x0000000048484848, 0x0000000021212121, 0xffffffffffffffee ); + TEST_RR_OP( 21, rolw, 0xffffffff90909090, 0x0000000021212121, 0xffffffffffffffff ); + + # Verify that rotates ignore top 32 (using true 64-bit values) + + TEST_RR_OP( 44, rolw, 0x0000000012345678, 0xffffffff12345678, 0 ); + TEST_RR_OP( 45, rolw, 0x0000000023456781, 0xffffffff12345678, 4 ); + TEST_RR_OP( 46, rolw, 0xffffffff92345678, 0x0000000092345678, 0 ); + TEST_RR_OP( 47, rolw, 0xffffffff93456789, 0x0000000099345678, 4 ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 22, rolw, 0x00000080, 0x00000001, 7 ); + TEST_RR_SRC2_EQ_DEST( 23, rolw, 0x00004000, 0x00000001, 14 ); + TEST_RR_SRC12_EQ_DEST( 24, rolw, 24, 3 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 25, 0, rolw, 0x0000000000000080, 0x0000000000000001, 7 ); + TEST_RR_DEST_BYPASS( 26, 1, rolw, 0x0000000000004000, 0x0000000000000001, 14 ); + TEST_RR_DEST_BYPASS( 27, 2, rolw, 0xffffffff80000000, 0x0000000000000001, 31 ); + + TEST_RR_SRC12_BYPASS( 28, 0, 0, rolw, 0x0000000000000080, 0x0000000000000001, 7 ); + TEST_RR_SRC12_BYPASS( 29, 0, 1, rolw, 0x0000000000004000, 0x0000000000000001, 14 ); + TEST_RR_SRC12_BYPASS( 30, 0, 2, rolw, 0xffffffff80000000, 0x0000000000000001, 31 ); + TEST_RR_SRC12_BYPASS( 31, 1, 0, rolw, 0x0000000000000080, 0x0000000000000001, 7 ); + TEST_RR_SRC12_BYPASS( 32, 1, 1, rolw, 0x0000000000004000, 0x0000000000000001, 14 ); + TEST_RR_SRC12_BYPASS( 33, 2, 0, rolw, 0xffffffff80000000, 0x0000000000000001, 31 ); + + TEST_RR_SRC21_BYPASS( 34, 0, 0, rolw, 0x0000000000000080, 0x0000000000000001, 7 ); + TEST_RR_SRC21_BYPASS( 35, 0, 1, rolw, 0x0000000000004000, 0x0000000000000001, 14 ); + TEST_RR_SRC21_BYPASS( 36, 0, 2, rolw, 0xffffffff80000000, 0x0000000000000001, 31 ); + TEST_RR_SRC21_BYPASS( 37, 1, 0, rolw, 0x0000000000000080, 0x0000000000000001, 7 ); + TEST_RR_SRC21_BYPASS( 38, 1, 1, rolw, 0x0000000000004000, 0x0000000000000001, 14 ); + TEST_RR_SRC21_BYPASS( 39, 2, 0, rolw, 0xffffffff80000000, 0x0000000000000001, 31 ); + + TEST_RR_ZEROSRC1( 40, rolw, 0, 15 ); + TEST_RR_ZEROSRC2( 41, rolw, 32, 32 ); + TEST_RR_ZEROSRC12( 42, rolw, 0 ); + TEST_RR_ZERODEST( 43, rolw, 1024, 2048 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64uzbb/ror.S b/tb/qumcu/isa/rv64uzbb/ror.S new file mode 100644 index 0000000..163333d --- /dev/null +++ b/tb/qumcu/isa/rv64uzbb/ror.S @@ -0,0 +1,94 @@ +# See LICENSE for license details. + +#***************************************************************************** +# ror.S +#----------------------------------------------------------------------------- +# +# Test ror instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, ror, 0x0000000000000001, 0x0000000000000001, 0 ); + TEST_RR_OP( 3, ror, 0x8000000000000000, 0x0000000000000001, 1 ); + TEST_RR_OP( 4, ror, 0x0200000000000000, 0x0000000000000001, 7 ); + TEST_RR_OP( 5, ror, 0x0004000000000000, 0x0000000000000001, 14 ); + TEST_RR_OP( 6, ror, 0x0000000200000000, 0x0000000000000001, 31 ); + + TEST_RR_OP( 7, ror, 0xffffffffffffffff, 0xffffffffffffffff, 0 ); + TEST_RR_OP( 8, ror, 0xffffffffffffffff, 0xffffffffffffffff, 1 ); + TEST_RR_OP( 9, ror, 0xffffffffffffffff, 0xffffffffffffffff, 7 ); + TEST_RR_OP( 10, ror, 0xffffffffffffffff, 0xffffffffffffffff, 14 ); + TEST_RR_OP( 11, ror, 0xffffffffffffffff, 0xffffffffffffffff, 31 ); + + TEST_RR_OP( 12, ror, 0x0000000021212121, 0x0000000021212121, 0 ); + TEST_RR_OP( 13, ror, 0x8000000010909090, 0x0000000021212121, 1 ); + TEST_RR_OP( 14, ror, 0x4200000000424242, 0x0000000021212121, 7 ); + TEST_RR_OP( 15, ror, 0x8484000000008484, 0x0000000021212121, 14 ); + TEST_RR_OP( 16, ror, 0x4242424200000000, 0x0000000021212121, 31 ); + + # Verify that shifts only use bottom six(rv64) or five(rv32) bits + + TEST_RR_OP( 17, ror, 0x0000000021212121, 0x0000000021212121, 0xffffffffffffffc0 ); + TEST_RR_OP( 18, ror, 0x8000000010909090, 0x0000000021212121, 0xffffffffffffffc1 ); + TEST_RR_OP( 19, ror, 0x4200000000424242, 0x0000000021212121, 0xffffffffffffffc7 ); + TEST_RR_OP( 20, ror, 0x8484000000008484, 0x0000000021212121, 0xffffffffffffffce ); + + TEST_RR_OP( 21, ror, 0x0000000042424242, 0x0000000021212121, 0xffffffffffffffff ); + TEST_RR_OP( 50, ror, 0x0000000000000002, 0x0000000000000001, 63 ); + TEST_RR_OP( 51, ror, 0xffffffffffffffff, 0xffffffffffffffff, 39 ); + TEST_RR_OP( 52, ror, 0x0004242424200000, 0x0000000021212121, 43 ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 22, ror, 0x0200000000000000, 0x00000001, 7 ); + TEST_RR_SRC2_EQ_DEST( 23, ror, 0x0004000000000000, 0x00000001, 14 ); + TEST_RR_SRC12_EQ_DEST( 24, ror, 0x6000000000000000, 3 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 25, 0, ror, 0x0200000000000000, 0x0000000000000001, 7 ); + TEST_RR_DEST_BYPASS( 26, 1, ror, 0x0004000000000000, 0x0000000000000001, 14 ); + TEST_RR_DEST_BYPASS( 27, 2, ror, 0x0000000200000000, 0x0000000000000001, 31 ); + + TEST_RR_SRC12_BYPASS( 28, 0, 0, ror, 0x0200000000000000, 0x0000000000000001, 7 ); + TEST_RR_SRC12_BYPASS( 29, 0, 1, ror, 0x0004000000000000, 0x0000000000000001, 14 ); + TEST_RR_SRC12_BYPASS( 30, 0, 2, ror, 0x0000000200000000, 0x0000000000000001, 31 ); + TEST_RR_SRC12_BYPASS( 31, 1, 0, ror, 0x0200000000000000, 0x0000000000000001, 7 ); + TEST_RR_SRC12_BYPASS( 32, 1, 1, ror, 0x0004000000000000, 0x0000000000000001, 14 ); + TEST_RR_SRC12_BYPASS( 33, 2, 0, ror, 0x0000000200000000, 0x0000000000000001, 31 ); + + TEST_RR_SRC21_BYPASS( 34, 0, 0, ror, 0x0200000000000000, 0x0000000000000001, 7 ); + TEST_RR_SRC21_BYPASS( 35, 0, 1, ror, 0x0004000000000000, 0x0000000000000001, 14 ); + TEST_RR_SRC21_BYPASS( 36, 0, 2, ror, 0x0000000200000000, 0x0000000000000001, 31 ); + TEST_RR_SRC21_BYPASS( 37, 1, 0, ror, 0x0200000000000000, 0x0000000000000001, 7 ); + TEST_RR_SRC21_BYPASS( 38, 1, 1, ror, 0x0004000000000000, 0x0000000000000001, 14 ); + TEST_RR_SRC21_BYPASS( 39, 2, 0, ror, 0x0000000200000000, 0x0000000000000001, 31 ); + + TEST_RR_ZEROSRC1( 40, ror, 0, 15 ); + TEST_RR_ZEROSRC2( 41, ror, 32, 32 ); + TEST_RR_ZEROSRC12( 42, ror, 0 ); + TEST_RR_ZERODEST( 43, ror, 1024, 2048 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64uzbb/rori.S b/tb/qumcu/isa/rv64uzbb/rori.S new file mode 100644 index 0000000..153f8e6 --- /dev/null +++ b/tb/qumcu/isa/rv64uzbb/rori.S @@ -0,0 +1,72 @@ +# See LICENSE for license details. + +#***************************************************************************** +# rori.S +#----------------------------------------------------------------------------- +# +# Test rori instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_IMM_OP( 2, rori, 0x0000000000000001, 0x0000000000000001, 0 ); + TEST_IMM_OP( 3, rori, 0x8000000000000000, 0x0000000000000001, 1 ); + TEST_IMM_OP( 4, rori, 0x0200000000000000, 0x0000000000000001, 7 ); + TEST_IMM_OP( 5, rori, 0x0004000000000000, 0x0000000000000001, 14 ); + TEST_IMM_OP( 6, rori, 0x0000000200000000, 0x0000000000000001, 31 ); + + TEST_IMM_OP( 7, rori, 0xffffffffffffffff, 0xffffffffffffffff, 0 ); + TEST_IMM_OP( 8, rori, 0xffffffffffffffff, 0xffffffffffffffff, 1 ); + TEST_IMM_OP( 9, rori, 0xffffffffffffffff, 0xffffffffffffffff, 7 ); + TEST_IMM_OP( 10, rori, 0xffffffffffffffff, 0xffffffffffffffff, 14 ); + TEST_IMM_OP( 11, rori, 0xffffffffffffffff, 0xffffffffffffffff, 31 ); + + TEST_IMM_OP( 12, rori, 0x0000000021212121, 0x0000000021212121, 0 ); + TEST_IMM_OP( 13, rori, 0x8000000010909090, 0x0000000021212121, 1 ); + TEST_IMM_OP( 14, rori, 0x4200000000424242, 0x0000000021212121, 7 ); + TEST_IMM_OP( 15, rori, 0x8484000000008484, 0x0000000021212121, 14 ); + TEST_IMM_OP( 16, rori, 0x4242424200000000, 0x0000000021212121, 31 ); + + TEST_IMM_OP( 17, rori, 0x0000000000000002, 0x0000000000000001, 63 ); + TEST_IMM_OP( 18, rori, 0xffffffffffffffff, 0xffffffffffffffff, 39 ); + TEST_IMM_OP( 19, rori, 0x0004242424200000, 0x0000000021212121, 43 ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_IMM_SRC1_EQ_DEST( 20, rori, 0x0200000000000000, 0x00000001, 7 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_IMM_DEST_BYPASS( 21, 0, rori, 0x0200000000000000, 0x0000000000000001, 7 ); + TEST_IMM_DEST_BYPASS( 22, 1, rori, 0x0004000000000000, 0x0000000000000001, 14 ); + TEST_IMM_DEST_BYPASS( 23, 2, rori, 0x0000000200000000, 0x0000000000000001, 31 ); + + TEST_IMM_SRC1_BYPASS( 24, 0, rori, 0x0200000000000000, 0x0000000000000001, 7 ); + TEST_IMM_SRC1_BYPASS( 25, 1, rori, 0x0004000000000000, 0x0000000000000001, 14 ); + TEST_IMM_SRC1_BYPASS( 26, 2, rori, 0x0000000200000000, 0x0000000000000001, 31 ); + + TEST_IMM_ZEROSRC1( 27, rori, 0, 31 ); + TEST_IMM_ZERODEST( 28, rori, 33, 20 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64uzbb/roriw.S b/tb/qumcu/isa/rv64uzbb/roriw.S new file mode 100644 index 0000000..44f3819 --- /dev/null +++ b/tb/qumcu/isa/rv64uzbb/roriw.S @@ -0,0 +1,68 @@ +# See LICENSE for license details. + +#***************************************************************************** +# rori.S +#----------------------------------------------------------------------------- +# +# Test rori instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_IMM_OP( 2, roriw, 0x0000000000000001, 0x0000000000000001, 0 ); + TEST_IMM_OP( 3, roriw, 0xffffffff80000000, 0x0000000000000001, 1 ); + TEST_IMM_OP( 4, roriw, 0x0000000002000000, 0x0000000000000001, 7 ); + TEST_IMM_OP( 5, roriw, 0x0000000000040000, 0x0000000000000001, 14 ); + TEST_IMM_OP( 6, roriw, 0x0000000000000002, 0x0000000000000001, 31 ); + + TEST_IMM_OP( 7, roriw, 0xffffffffffffffff, 0xffffffffffffffff, 0 ); + TEST_IMM_OP( 8, roriw, 0xffffffffffffffff, 0xffffffffffffffff, 1 ); + TEST_IMM_OP( 9, roriw, 0xffffffffffffffff, 0xffffffffffffffff, 7 ); + TEST_IMM_OP( 10, roriw, 0xffffffffffffffff, 0xffffffffffffffff, 14 ); + TEST_IMM_OP( 11, roriw, 0xffffffffffffffff, 0xffffffffffffffff, 31 ); + + TEST_IMM_OP( 12, roriw, 0x0000000021212121, 0x0000000021212121, 0 ); + TEST_IMM_OP( 13, roriw, 0xffffffff90909090, 0x0000000021212121, 1 ); + TEST_IMM_OP( 14, roriw, 0x0000000042424242, 0x0000000021212121, 7 ); + TEST_IMM_OP( 15, roriw, 0xffffffff84848484, 0x0000000021212121, 14 ); + TEST_IMM_OP( 16, roriw, 0x0000000042424242, 0x0000000021212121, 31 ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_IMM_SRC1_EQ_DEST( 20, roriw, 0x0000000002000000, 0x00000001, 7 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_IMM_DEST_BYPASS( 21, 0, roriw, 0x0000000002000000, 0x0000000000000001, 7 ); + TEST_IMM_DEST_BYPASS( 22, 1, roriw, 0x0000000000040000, 0x0000000000000001, 14 ); + TEST_IMM_DEST_BYPASS( 23, 2, roriw, 0x0000000000000002, 0x0000000000000001, 31 ); + + TEST_IMM_SRC1_BYPASS( 24, 0, roriw, 0x0000000002000000, 0x0000000000000001, 7 ); + TEST_IMM_SRC1_BYPASS( 25, 1, roriw, 0x0000000000040000, 0x0000000000000001, 14 ); + TEST_IMM_SRC1_BYPASS( 26, 2, roriw, 0x0000000000000002, 0x0000000000000001, 31 ); + + TEST_IMM_ZEROSRC1( 27, roriw, 0, 31 ); + TEST_IMM_ZERODEST( 28, roriw, 33, 20 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64uzbb/rorw.S b/tb/qumcu/isa/rv64uzbb/rorw.S new file mode 100644 index 0000000..de11c3c --- /dev/null +++ b/tb/qumcu/isa/rv64uzbb/rorw.S @@ -0,0 +1,91 @@ +# See LICENSE for license details. + +#***************************************************************************** +# rorw.S +#----------------------------------------------------------------------------- +# +# Test rorw instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, rorw, 0x0000000000000001, 0x0000000000000001, 0 ); + TEST_RR_OP( 3, rorw, 0xffffffff80000000, 0x0000000000000001, 1 ); + TEST_RR_OP( 4, rorw, 0x0000000002000000, 0x0000000000000001, 7 ); + TEST_RR_OP( 5, rorw, 0x0000000000040000, 0x0000000000000001, 14 ); + TEST_RR_OP( 6, rorw, 0x0000000000000002, 0x0000000000000001, 31 ); + + TEST_RR_OP( 7, rorw, 0xffffffffffffffff, 0xffffffffffffffff, 0 ); + TEST_RR_OP( 8, rorw, 0xffffffffffffffff, 0xffffffffffffffff, 1 ); + TEST_RR_OP( 9, rorw, 0xffffffffffffffff, 0xffffffffffffffff, 7 ); + TEST_RR_OP( 10, rorw, 0xffffffffffffffff, 0xffffffffffffffff, 14 ); + TEST_RR_OP( 11, rorw, 0xffffffffffffffff, 0xffffffffffffffff, 31 ); + + TEST_RR_OP( 12, rorw, 0x0000000021212121, 0x0000000021212121, 0 ); + TEST_RR_OP( 13, rorw, 0xffffffff90909090, 0x0000000021212121, 1 ); + TEST_RR_OP( 14, rorw, 0x0000000042424242, 0x0000000021212121, 7 ); + TEST_RR_OP( 15, rorw, 0xffffffff84848484, 0x0000000021212121, 14 ); + TEST_RR_OP( 16, rorw, 0x0000000042424242, 0x0000000021212121, 31 ); + + # Verify that shifts only use bottom six(rv64) or five(rv32) bits + + TEST_RR_OP( 17, rorw, 0x0000000021212121, 0x0000000021212121, 0xffffffffffffffc0 ); + TEST_RR_OP( 18, rorw, 0xffffffff90909090, 0x0000000021212121, 0xffffffffffffffc1 ); + TEST_RR_OP( 19, rorw, 0x0000000042424242, 0x0000000021212121, 0xffffffffffffffc7 ); + TEST_RR_OP( 20, rorw, 0xffffffff84848484, 0x0000000021212121, 0xffffffffffffffce ); + + TEST_RR_OP( 21, rorw, 0x0000000042424242, 0x0000000021212121, 0xffffffffffffffff ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 22, rorw, 0x0000000002000000, 0x00000001, 7 ); + TEST_RR_SRC2_EQ_DEST( 23, rorw, 0x0000000000040000, 0x00000001, 14 ); + TEST_RR_SRC12_EQ_DEST( 24, rorw, 0x0000000060000000, 3 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 25, 0, rorw, 0x0000000002000000, 0x0000000000000001, 7 ); + TEST_RR_DEST_BYPASS( 26, 1, rorw, 0x0000000000040000, 0x0000000000000001, 14 ); + TEST_RR_DEST_BYPASS( 27, 2, rorw, 0x0000000000000002, 0x0000000000000001, 31 ); + + TEST_RR_SRC12_BYPASS( 28, 0, 0, rorw, 0x0000000002000000, 0x0000000000000001, 7 ); + TEST_RR_SRC12_BYPASS( 29, 0, 1, rorw, 0x0000000000040000, 0x0000000000000001, 14 ); + TEST_RR_SRC12_BYPASS( 30, 0, 2, rorw, 0x0000000000000002, 0x0000000000000001, 31 ); + TEST_RR_SRC12_BYPASS( 31, 1, 0, rorw, 0x0000000002000000, 0x0000000000000001, 7 ); + TEST_RR_SRC12_BYPASS( 32, 1, 1, rorw, 0x0000000000040000, 0x0000000000000001, 14 ); + TEST_RR_SRC12_BYPASS( 33, 2, 0, rorw, 0x0000000000000002, 0x0000000000000001, 31 ); + + TEST_RR_SRC21_BYPASS( 34, 0, 0, rorw, 0x0000000002000000, 0x0000000000000001, 7 ); + TEST_RR_SRC21_BYPASS( 35, 0, 1, rorw, 0x0000000000040000, 0x0000000000000001, 14 ); + TEST_RR_SRC21_BYPASS( 36, 0, 2, rorw, 0x0000000000000002, 0x0000000000000001, 31 ); + TEST_RR_SRC21_BYPASS( 37, 1, 0, rorw, 0x0000000002000000, 0x0000000000000001, 7 ); + TEST_RR_SRC21_BYPASS( 38, 1, 1, rorw, 0x0000000000040000, 0x0000000000000001, 14 ); + TEST_RR_SRC21_BYPASS( 39, 2, 0, rorw, 0x0000000000000002, 0x0000000000000001, 31 ); + + TEST_RR_ZEROSRC1( 40, rorw, 0, 15 ); + TEST_RR_ZEROSRC2( 41, rorw, 32, 32 ); + TEST_RR_ZEROSRC12( 42, rorw, 0 ); + TEST_RR_ZERODEST( 43, rorw, 1024, 2048 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64uzbb/sext_b.S b/tb/qumcu/isa/rv64uzbb/sext_b.S new file mode 100644 index 0000000..8acf86a --- /dev/null +++ b/tb/qumcu/isa/rv64uzbb/sext_b.S @@ -0,0 +1,75 @@ +# See LICENSE for license details. + +#***************************************************************************** +# sext_b.S +#----------------------------------------------------------------------------- +# +# Test sext.b instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_R_OP( 2, sext.b, 0x0000000000000000, 0x0000000000000000); + TEST_R_OP( 3, sext.b, 0x0000000000000001, 0x0000000000000001); + TEST_R_OP( 4, sext.b, 0x0000000000000003, 0x0000000000000003); + + TEST_R_OP( 5, sext.b, 0x0000000000000000, 0xffffffffffff8000 ); + TEST_R_OP( 6, sext.b, 0x0000000000000000, 0x0000000000800000 ); + TEST_R_OP( 7, sext.b, 0x0000000000000000, 0x0004ffffffff8000 ); + + TEST_R_OP( 8, sext.b, 0xffffffffffffffff, 0x0000000000007fff); + TEST_R_OP( 9, sext.b, 0xffffffffffffffff, 0x000000007fffffff); + TEST_R_OP( 10, sext.b, 0xffffffffffffffff, 0x000000000007ffff ); + + TEST_R_OP( 11, sext.b, 0x0000000000000000, 0xffffffff80000000); + TEST_R_OP( 12, sext.b, 0x0000000000000000, 0x00ff578f121f5000); + + TEST_R_OP( 13, sext.b, 0x0000000000000000, 0x8000000000000000); + TEST_R_OP( 14, sext.b, 0x000000000000000e, 0x000000000000000e); + TEST_R_OP( 15, sext.b, 0x0000000000000041, 0xa000000320401341); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_R_SRC1_EQ_DEST( 16, sext.b, 0x000000000000000d, 13); + TEST_R_SRC1_EQ_DEST( 17, sext.b, 0x000000000000000b, 11); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_R_DEST_BYPASS( 18, 0, sext.b, 0x000000000000000d, 13); + TEST_R_DEST_BYPASS( 29, 1, sext.b, 0x0000000000000013, 19); + TEST_R_DEST_BYPASS( 20, 2, sext.b, 0x0000000000000022, 34); + + #------------------------------------------------------------- + # Other tests + #------------------------------------------------------------- + + TEST_R_OP( 21, sext.b, 0x0000000000000000, 0x00000000007f8000 ); + TEST_R_OP( 22, sext.b, 0x0000000000000000, 0x0000000000808000 ); + TEST_R_OP( 23, sext.b, 0x0000000000000000, 0x0000000001808000 ); + + TEST_R_OP( 24, sext.b, 0xffffffffffffffff, 0x0000000300007fff); + TEST_R_OP( 25, sext.b, 0xffffffffffffffff, 0x000000077fffffff); + TEST_R_OP( 26, sext.b, 0xffffffffffffffff, 0x0000000f0007ffff); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64uzbb/sext_h.S b/tb/qumcu/isa/rv64uzbb/sext_h.S new file mode 100644 index 0000000..59cf386 --- /dev/null +++ b/tb/qumcu/isa/rv64uzbb/sext_h.S @@ -0,0 +1,75 @@ +# See LICENSE for license details. + +#***************************************************************************** +# sext_h.S +#----------------------------------------------------------------------------- +# +# Test sext.h instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_R_OP( 2, sext.h, 0x0000000000000000, 0x0000000000000000); + TEST_R_OP( 3, sext.h, 0x0000000000000001, 0x0000000000000001); + TEST_R_OP( 4, sext.h, 0x0000000000000003, 0x0000000000000003); + + TEST_R_OP( 5, sext.h, 0xffffffffffff8000, 0xffffffffffff8000 ); + TEST_R_OP( 6, sext.h, 0x0000000000000000, 0x0000000000800000 ); + TEST_R_OP( 7, sext.h, 0xffffffffffff8000, 0x0004ffffffff8000 ); + + TEST_R_OP( 8, sext.h, 0x0000000000007fff, 0x0000000000007fff); + TEST_R_OP( 9, sext.h, 0xffffffffffffffff, 0x000000007fffffff); + TEST_R_OP( 10, sext.h, 0xffffffffffffffff, 0x000000000007ffff ); + + TEST_R_OP( 11, sext.h, 0x0000000000000000, 0xffffffff80000000); + TEST_R_OP( 12, sext.h, 0x0000000000005000, 0x00ff578f121f5000); + + TEST_R_OP( 13, sext.h, 0x0000000000000000, 0x8000000000000000); + TEST_R_OP( 14, sext.h, 0x000000000000000e, 0x000000000000000e); + TEST_R_OP( 15, sext.h, 0x0000000000001341, 0xa000000320401341); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_R_SRC1_EQ_DEST( 16, sext.h, 0x000000000000000d, 13); + TEST_R_SRC1_EQ_DEST( 17, sext.h, 0x000000000000000b, 11); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_R_DEST_BYPASS( 18, 0, sext.h, 0x000000000000000d, 13); + TEST_R_DEST_BYPASS( 29, 1, sext.h, 0x0000000000000013, 19); + TEST_R_DEST_BYPASS( 20, 2, sext.h, 0x0000000000000022, 34); + + #------------------------------------------------------------- + # Other tests + #------------------------------------------------------------- + + TEST_R_OP( 21, sext.h, 0xffffffffffff8000, 0x00000000007f8000 ); + TEST_R_OP( 22, sext.h, 0xffffffffffff8000, 0x0000000000808000 ); + TEST_R_OP( 23, sext.h, 0xffffffffffff8000, 0x0000000001808000 ); + + TEST_R_OP( 24, sext.h, 0x0000000000007fff, 0x0000000300007fff); + TEST_R_OP( 25, sext.h, 0xffffffffffffffff, 0x000000077fffffff); + TEST_R_OP( 26, sext.h, 0xffffffffffffffff, 0x0000000f0007ffff); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64uzbb/xnor.S b/tb/qumcu/isa/rv64uzbb/xnor.S new file mode 100644 index 0000000..5a74f86 --- /dev/null +++ b/tb/qumcu/isa/rv64uzbb/xnor.S @@ -0,0 +1,75 @@ +# See LICENSE for license details. + +#***************************************************************************** +# xnor.S +#----------------------------------------------------------------------------- +# +# Test xnor instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Logical tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, xnor, 0x000000000ff00ff0, 0xffffffffff00ff00, 0x000000000f0f0f0f ); + TEST_RR_OP( 3, xnor, 0x0000000000ff00ff, 0x000000000ff00ff0, 0xfffffffff0f0f0f0 ); + TEST_RR_OP( 4, xnor, 0xfffffffff00ff00f, 0x0000000000ff00ff, 0x000000000f0f0f0f ); + TEST_RR_OP( 5, xnor, 0xffffffffff00ff00, 0xfffffffff00ff00f, 0xfffffffff0f0f0f0 ); + +#if __riscv_xlen == 64 + TEST_RR_OP( 50, xnor, 0x00ff00ff00ff00ff, 0x0ff00ff00ff00ff0, 0xf0f0f0f0f0f0f0f0 ); + TEST_RR_OP( 51, xnor, 0xf00ff00ff00ff00f, 0x00ff00ff00ff00ff, 0x0f0f0f0f0f0f0f0f ); + TEST_RR_OP( 52, xnor, 0xff00ff00ff00ff00, 0xf00ff00ff00ff00f, 0xf0f0f0f0f0f0f0f0 ); +#endif + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 6, xnor, 0x000000000ff00ff0, 0xffffffffff00ff00, 0x000000000f0f0f0f ); + TEST_RR_SRC2_EQ_DEST( 7, xnor, 0x000000000ff00ff0, 0xffffffffff00ff00, 0x000000000f0f0f0f ); + TEST_RR_SRC12_EQ_DEST( 8, xnor, 0xffffffffffffffff, 0xffffffffff00ff00 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 9, 0, xnor, 0x000000000ff00ff0, 0xffffffffff00ff00, 0x000000000f0f0f0f ); + TEST_RR_DEST_BYPASS( 10, 1, xnor, 0x0000000000ff00ff, 0x000000000ff00ff0, 0xfffffffff0f0f0f0 ); + TEST_RR_DEST_BYPASS( 11, 2, xnor, 0xfffffffff00ff00f, 0x0000000000ff00ff, 0x000000000f0f0f0f ); + + TEST_RR_SRC12_BYPASS( 12, 0, 0, xnor, 0x000000000ff00ff0, 0xffffffffff00ff00, 0x000000000f0f0f0f ); + TEST_RR_SRC12_BYPASS( 13, 0, 1, xnor, 0x0000000000ff00ff, 0x000000000ff00ff0, 0xfffffffff0f0f0f0 ); + TEST_RR_SRC12_BYPASS( 14, 0, 2, xnor, 0xfffffffff00ff00f, 0x0000000000ff00ff, 0x000000000f0f0f0f ); + TEST_RR_SRC12_BYPASS( 15, 1, 0, xnor, 0x000000000ff00ff0, 0xffffffffff00ff00, 0x000000000f0f0f0f ); + TEST_RR_SRC12_BYPASS( 16, 1, 1, xnor, 0x0000000000ff00ff, 0x000000000ff00ff0, 0xfffffffff0f0f0f0 ); + TEST_RR_SRC12_BYPASS( 17, 2, 0, xnor, 0xfffffffff00ff00f, 0x0000000000ff00ff, 0x000000000f0f0f0f ); + + TEST_RR_SRC21_BYPASS( 18, 0, 0, xnor, 0x000000000ff00ff0, 0xffffffffff00ff00, 0x000000000f0f0f0f ); + TEST_RR_SRC21_BYPASS( 19, 0, 1, xnor, 0x0000000000ff00ff, 0x000000000ff00ff0, 0xfffffffff0f0f0f0 ); + TEST_RR_SRC21_BYPASS( 20, 0, 2, xnor, 0xfffffffff00ff00f, 0x0000000000ff00ff, 0x000000000f0f0f0f ); + TEST_RR_SRC21_BYPASS( 21, 1, 0, xnor, 0x000000000ff00ff0, 0xffffffffff00ff00, 0x000000000f0f0f0f ); + TEST_RR_SRC21_BYPASS( 22, 1, 1, xnor, 0x0000000000ff00ff, 0x000000000ff00ff0, 0xfffffffff0f0f0f0 ); + TEST_RR_SRC21_BYPASS( 23, 2, 0, xnor, 0xfffffffff00ff00f, 0x0000000000ff00ff, 0x000000000f0f0f0f ); + + TEST_RR_ZEROSRC1( 24, xnor, 0x0000000000ff00ff, 0xffffffffff00ff00 ); + TEST_RR_ZEROSRC2( 25, xnor, 0xffffffffff00ff00, 0x0000000000ff00ff ); + TEST_RR_ZEROSRC12( 26, xnor, -1 ); + TEST_RR_ZERODEST( 27, xnor, 0x0000000011111111, 0x0000000022222222 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64uzbb/zext_h.S b/tb/qumcu/isa/rv64uzbb/zext_h.S new file mode 100644 index 0000000..baa0b7a --- /dev/null +++ b/tb/qumcu/isa/rv64uzbb/zext_h.S @@ -0,0 +1,75 @@ +# See LICENSE for license details. + +#***************************************************************************** +# sext_h.S +#----------------------------------------------------------------------------- +# +# Test zext.h instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_R_OP( 2, zext.h, 0x0000000000000000, 0x0000000000000000); + TEST_R_OP( 3, zext.h, 0x0000000000000001, 0x0000000000000001); + TEST_R_OP( 4, zext.h, 0x0000000000000003, 0x0000000000000003); + + TEST_R_OP( 5, zext.h, 0x0000000000008000, 0xffffffffffff8000 ); + TEST_R_OP( 6, zext.h, 0x0000000000000000, 0x0000000000800000 ); + TEST_R_OP( 7, zext.h, 0x0000000000008000, 0x0004ffffffff8000 ); + + TEST_R_OP( 8, zext.h, 0x0000000000007fff, 0x0000000000007fff); + TEST_R_OP( 9, zext.h, 0x000000000000ffff, 0x000000007fffffff); + TEST_R_OP( 10, zext.h, 0x000000000000ffff, 0x000000000007ffff ); + + TEST_R_OP( 11, zext.h, 0x0000000000000000, 0xffffffff80000000); + TEST_R_OP( 12, zext.h, 0x0000000000005000, 0x00ff578f121f5000); + + TEST_R_OP( 13, zext.h, 0x0000000000000000, 0x8000000000000000); + TEST_R_OP( 14, zext.h, 0x000000000000000e, 0x000000000000000e); + TEST_R_OP( 15, zext.h, 0x0000000000001341, 0xa000000320401341); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_R_SRC1_EQ_DEST( 16, zext.h, 0x000000000000000d, 13); + TEST_R_SRC1_EQ_DEST( 17, zext.h, 0x000000000000000b, 11); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_R_DEST_BYPASS( 18, 0, zext.h, 0x000000000000000d, 13); + TEST_R_DEST_BYPASS( 29, 1, zext.h, 0x0000000000000013, 19); + TEST_R_DEST_BYPASS( 20, 2, zext.h, 0x0000000000000022, 34); + + #------------------------------------------------------------- + # Other tests + #------------------------------------------------------------- + + TEST_R_OP( 21, zext.h, 0x0000000000008000, 0x00000000007f8000 ); + TEST_R_OP( 22, zext.h, 0x0000000000008000, 0x0000000000808000 ); + TEST_R_OP( 23, zext.h, 0x0000000000008000, 0x0000000001808000 ); + + TEST_R_OP( 24, zext.h, 0x0000000000007fff, 0x0000000300007fff); + TEST_R_OP( 25, zext.h, 0x000000000000ffff, 0x000000077fffffff); + TEST_R_OP( 26, zext.h, 0x000000000000ffff, 0x0000000f0007ffff); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64uzbc/Makefrag b/tb/qumcu/isa/rv64uzbc/Makefrag new file mode 100644 index 0000000..01ce4e2 --- /dev/null +++ b/tb/qumcu/isa/rv64uzbc/Makefrag @@ -0,0 +1,14 @@ +#======================================================================= +# Makefrag for rv64uzbc tests +#----------------------------------------------------------------------- + +rv64uzbc_sc_tests = \ + clmul \ + clmulh \ + clmulr \ + +rv64uzbc_p_tests = $(addprefix rv64uzbc-p-, $(rv64uzbc_sc_tests)) +rv64uzbc_v_tests = $(addprefix rv64uzbc-v-, $(rv64uzbc_sc_tests)) +rv64uzbc_ps_tests = $(addprefix rv64uzbc-ps-, $(rv64uzbc_sc_tests)) + +spike_tests += $(rv64uzbc_p_tests) $(rv64uzbc_v_tests) diff --git a/tb/qumcu/isa/rv64uzbc/clmul.S b/tb/qumcu/isa/rv64uzbc/clmul.S new file mode 100644 index 0000000..c147791 --- /dev/null +++ b/tb/qumcu/isa/rv64uzbc/clmul.S @@ -0,0 +1,78 @@ +# See LICENSE for license details. + +#***************************************************************************** +# clmul.S +#----------------------------------------------------------------------------- +# +# Test clmul instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP(32, clmul, 0x0000000000005a00, 0x0000000000007e00, 0x6db6db6db6db6db7 ); + TEST_RR_OP(33, clmul, 0x0000000000005b40, 0x0000000000007fc0, 0x6db6db6db6db6db7 ); + + TEST_RR_OP( 2, clmul, 0x00000000, 0x00000000, 0x00000000 ); + TEST_RR_OP( 3, clmul, 0x00000001, 0x00000001, 0x00000001 ); + TEST_RR_OP( 4, clmul, 0x00000009, 0x00000003, 0x00000007 ); + + TEST_RR_OP( 5, clmul, 0x0000000000000000, 0x0000000000000000, 0xffffffffffff8000 ); + TEST_RR_OP( 6, clmul, 0x0000000000000000, 0xffffffff80000000, 0x00000000 ); + TEST_RR_OP( 7, clmul, 0x5555400000000000, 0xffffffff80000000, 0xffffffffffff8000 ); + + TEST_RR_OP(30, clmul, 0xfffffffffffc324f, 0xaaaaaaaaaaaaaaab, 0x000000000002fe7d ); + TEST_RR_OP(31, clmul, 0xfffffffffffc324f, 0x000000000002fe7d, 0xaaaaaaaaaaaaaaab ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 8, clmul, 0x7f, 13, 11 ); + TEST_RR_SRC2_EQ_DEST( 9, clmul, 0x62, 14, 11 ); + TEST_RR_SRC12_EQ_DEST( 10, clmul, 0x51, 13 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 11, 0, clmul, 0x7f, 13, 11 ); + TEST_RR_DEST_BYPASS( 12, 1, clmul, 0x62, 14, 11 ); + TEST_RR_DEST_BYPASS( 13, 2, clmul, 0x69, 15, 11 ); + + TEST_RR_SRC12_BYPASS( 14, 0, 0, clmul, 0x7f, 13, 11 ); + TEST_RR_SRC12_BYPASS( 15, 0, 1, clmul, 0x62, 14, 11 ); + TEST_RR_SRC12_BYPASS( 16, 0, 2, clmul, 0x69, 15, 11 ); + TEST_RR_SRC12_BYPASS( 17, 1, 0, clmul, 0x7f, 13, 11 ); + TEST_RR_SRC12_BYPASS( 18, 1, 1, clmul, 0x62, 14, 11 ); + TEST_RR_SRC12_BYPASS( 19, 2, 0, clmul, 0x69, 15, 11 ); + + TEST_RR_SRC21_BYPASS( 20, 0, 0, clmul, 0x7f, 13, 11 ); + TEST_RR_SRC21_BYPASS( 21, 0, 1, clmul, 0x62, 14, 11 ); + TEST_RR_SRC21_BYPASS( 22, 0, 2, clmul, 0x69, 15, 11 ); + TEST_RR_SRC21_BYPASS( 23, 1, 0, clmul, 0x7f, 13, 11 ); + TEST_RR_SRC21_BYPASS( 24, 1, 1, clmul, 0x62, 14, 11 ); + TEST_RR_SRC21_BYPASS( 25, 2, 0, clmul, 0x69, 15, 11 ); + + TEST_RR_ZEROSRC1( 26, clmul, 0, 31 ); + TEST_RR_ZEROSRC2( 27, clmul, 0, 32 ); + TEST_RR_ZEROSRC12( 28, clmul, 0 ); + TEST_RR_ZERODEST( 29, clmul, 33, 34 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64uzbc/clmulh.S b/tb/qumcu/isa/rv64uzbc/clmulh.S new file mode 100644 index 0000000..c5eaf65 --- /dev/null +++ b/tb/qumcu/isa/rv64uzbc/clmulh.S @@ -0,0 +1,78 @@ +# See LICENSE for license details. + +#***************************************************************************** +# clmulh.S +#----------------------------------------------------------------------------- +# +# Test clmulh instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP(32, clmulh, 0x0000000000001200, 0x0000000000007e00, 0x6db6db6db6db6db7 ); + TEST_RR_OP(33, clmulh, 0x0000000000001240, 0x0000000000007fc0, 0x6db6db6db6db6db7 ); + + TEST_RR_OP( 2, clmulh, 0x00000000, 0x00000000, 0x00000000 ); + TEST_RR_OP( 3, clmulh, 0x00000000, 0x00000001, 0x00000001 ); + TEST_RR_OP( 4, clmulh, 0x00000000, 0x00000003, 0x00000007 ); + + TEST_RR_OP( 5, clmulh, 0x0000000000000000, 0x0000000000000000, 0xffffffffffff8000 ); + TEST_RR_OP( 6, clmulh, 0x0000000000000000, 0xffffffff80000000, 0x00000000 ); + TEST_RR_OP( 7, clmulh, 0x555555557fffd555, 0xffffffff80000000, 0xffffffffffff8000 ); + + TEST_RR_OP(30, clmulh, 0x00000000000133cd, 0xaaaaaaaaaaaaaaab, 0x000000000002fe7d ); + TEST_RR_OP(31, clmulh, 0x00000000000133cd, 0x000000000002fe7d, 0xaaaaaaaaaaaaaaab ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 8, clmulh, 0, 13, 11 ); + TEST_RR_SRC2_EQ_DEST( 9, clmulh, 0, 14, 11 ); + TEST_RR_SRC12_EQ_DEST( 10, clmulh, 0, 13 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 11, 0, clmulh, 0, 13, 11 ); + TEST_RR_DEST_BYPASS( 12, 1, clmulh, 0, 14, 11 ); + TEST_RR_DEST_BYPASS( 13, 2, clmulh, 0, 15, 11 ); + + TEST_RR_SRC12_BYPASS( 14, 0, 0, clmulh, 0, 13, 11 ); + TEST_RR_SRC12_BYPASS( 15, 0, 1, clmulh, 0, 14, 11 ); + TEST_RR_SRC12_BYPASS( 16, 0, 2, clmulh, 0, 15, 11 ); + TEST_RR_SRC12_BYPASS( 17, 1, 0, clmulh, 0, 13, 11 ); + TEST_RR_SRC12_BYPASS( 18, 1, 1, clmulh, 0, 14, 11 ); + TEST_RR_SRC12_BYPASS( 19, 2, 0, clmulh, 0, 15, 11 ); + + TEST_RR_SRC21_BYPASS( 20, 0, 0, clmulh, 0, 13, 11 ); + TEST_RR_SRC21_BYPASS( 21, 0, 1, clmulh, 0, 14, 11 ); + TEST_RR_SRC21_BYPASS( 22, 0, 2, clmulh, 0, 15, 11 ); + TEST_RR_SRC21_BYPASS( 23, 1, 0, clmulh, 0, 13, 11 ); + TEST_RR_SRC21_BYPASS( 24, 1, 1, clmulh, 0, 14, 11 ); + TEST_RR_SRC21_BYPASS( 25, 2, 0, clmulh, 0, 15, 11 ); + + TEST_RR_ZEROSRC1( 26, clmulh, 0, 31 ); + TEST_RR_ZEROSRC2( 27, clmulh, 0, 32 ); + TEST_RR_ZEROSRC12( 28, clmulh, 0 ); + TEST_RR_ZERODEST( 29, clmulh, 33, 34 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64uzbc/clmulr.S b/tb/qumcu/isa/rv64uzbc/clmulr.S new file mode 100644 index 0000000..d2f86df --- /dev/null +++ b/tb/qumcu/isa/rv64uzbc/clmulr.S @@ -0,0 +1,78 @@ +# See LICENSE for license details. + +#***************************************************************************** +# clmulr.S +#----------------------------------------------------------------------------- +# +# Test clmulr instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP(32, clmulr, 0x0000000000002400, 0x0000000000007e00, 0x6db6db6db6db6db7 ); + TEST_RR_OP(33, clmulr, 0x0000000000002480, 0x0000000000007fc0, 0x6db6db6db6db6db7 ); + + TEST_RR_OP( 2, clmulr, 0x00000000, 0x00000000, 0x00000000 ); + TEST_RR_OP( 3, clmulr, 0x00000000, 0x00000001, 0x00000001 ); + TEST_RR_OP( 4, clmulr, 0x00000000, 0x00000003, 0x00000007 ); + + TEST_RR_OP( 5, clmulr, 0x0000000000000000, 0x0000000000000000, 0xffffffffffff8000 ); + TEST_RR_OP( 6, clmulr, 0x0000000000000000, 0xffffffff80000000, 0x00000000 ); + TEST_RR_OP( 7, clmulr, 0xaaaaaaaaffffaaaa, 0xffffffff80000000, 0xffffffffffff8000 ); + + TEST_RR_OP(30, clmulr, 0x000000000002679b, 0xaaaaaaaaaaaaaaab, 0x000000000002fe7d ); + TEST_RR_OP(31, clmulr, 0x000000000002679b, 0x000000000002fe7d, 0xaaaaaaaaaaaaaaab ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 8, clmulr, 0, 13, 11 ); + TEST_RR_SRC2_EQ_DEST( 9, clmulr, 0, 14, 11 ); + TEST_RR_SRC12_EQ_DEST( 10, clmulr, 0, 13 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 11, 0, clmulr, 0, 13, 11 ); + TEST_RR_DEST_BYPASS( 12, 1, clmulr, 0, 14, 11 ); + TEST_RR_DEST_BYPASS( 13, 2, clmulr, 0, 15, 11 ); + + TEST_RR_SRC12_BYPASS( 14, 0, 0, clmulr, 0, 13, 11 ); + TEST_RR_SRC12_BYPASS( 15, 0, 1, clmulr, 0, 14, 11 ); + TEST_RR_SRC12_BYPASS( 16, 0, 2, clmulr, 0, 15, 11 ); + TEST_RR_SRC12_BYPASS( 17, 1, 0, clmulr, 0, 13, 11 ); + TEST_RR_SRC12_BYPASS( 18, 1, 1, clmulr, 0, 14, 11 ); + TEST_RR_SRC12_BYPASS( 19, 2, 0, clmulr, 0, 15, 11 ); + + TEST_RR_SRC21_BYPASS( 20, 0, 0, clmulr, 0, 13, 11 ); + TEST_RR_SRC21_BYPASS( 21, 0, 1, clmulr, 0, 14, 11 ); + TEST_RR_SRC21_BYPASS( 22, 0, 2, clmulr, 0, 15, 11 ); + TEST_RR_SRC21_BYPASS( 23, 1, 0, clmulr, 0, 13, 11 ); + TEST_RR_SRC21_BYPASS( 24, 1, 1, clmulr, 0, 14, 11 ); + TEST_RR_SRC21_BYPASS( 25, 2, 0, clmulr, 0, 15, 11 ); + + TEST_RR_ZEROSRC1( 26, clmulr, 0, 31 ); + TEST_RR_ZEROSRC2( 27, clmulr, 0, 32 ); + TEST_RR_ZEROSRC12( 28, clmulr, 0 ); + TEST_RR_ZERODEST( 29, clmulr, 33, 34 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64uzbs/Makefrag b/tb/qumcu/isa/rv64uzbs/Makefrag new file mode 100644 index 0000000..3264b4d --- /dev/null +++ b/tb/qumcu/isa/rv64uzbs/Makefrag @@ -0,0 +1,15 @@ +#======================================================================= +# Makefrag for rv64uzbs tests +#----------------------------------------------------------------------- + +rv64uzbs_sc_tests = \ + bclr bclri \ + bext bexti \ + binv binvi \ + bset bseti \ + +rv64uzbs_p_tests = $(addprefix rv64uzbs-p-, $(rv64uzbs_sc_tests)) +rv64uzbs_v_tests = $(addprefix rv64uzbs-v-, $(rv64uzbs_sc_tests)) +rv64uzbs_ps_tests = $(addprefix rv64uzbs-ps-, $(rv64uzbs_sc_tests)) + +spike_tests += $(rv64uzbs_p_tests) $(rv64uzbs_v_tests) diff --git a/tb/qumcu/isa/rv64uzbs/bclr.S b/tb/qumcu/isa/rv64uzbs/bclr.S new file mode 100644 index 0000000..75d48de --- /dev/null +++ b/tb/qumcu/isa/rv64uzbs/bclr.S @@ -0,0 +1,96 @@ +# See LICENSE for license details. + +#***************************************************************************** +# bclr.S +#----------------------------------------------------------------------------- +# +# Test bclr instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, bclr, 0xff00ff00, 0xff00ff00, 0 ); + TEST_RR_OP( 3, bclr, 0x00ff00fd, 0x00ff00ff, 1 ); + TEST_RR_OP( 4, bclr, 0xff00fe00, 0xff00ff00, 8 ); + TEST_RR_OP( 5, bclr, 0x0ff00ff0, 0x0ff00ff0, 14 ); + TEST_RR_OP( 6, bclr, 0x07f00ff0, 0x0ff00ff0, 27 ); + + TEST_RR_OP( 7, bclr, 0xfffffffffffffffe, 0xffffffffffffffff, 0 ); + TEST_RR_OP( 8, bclr, 0xfffffffffffffffd, 0xffffffffffffffff, 1 ); + TEST_RR_OP( 9, bclr, 0xffffffffffffff7f, 0xffffffffffffffff, 7 ); + TEST_RR_OP( 10, bclr, 0xffffffffffffbfff, 0xffffffffffffffff, 14 ); + TEST_RR_OP( 11, bclr, 0xfffffffff7ffffff, 0xffffffffffffffff, 27 ); + + TEST_RR_OP( 12, bclr, 0x21212120, 0x21212121, 0 ); + TEST_RR_OP( 13, bclr, 0x21212121, 0x21212121, 1 ); + TEST_RR_OP( 14, bclr, 0x21212121, 0x21212121, 7 ); + TEST_RR_OP( 15, bclr, 0x21210121, 0x21212121, 13 ); + TEST_RR_OP( 16, bclr, 0x04848484, 0x84848484, 31 ); + + # Verify that shifts only use bottom six(rv64) or five(rv32) bits + + TEST_RR_OP( 17, bclr, 0x21212120, 0x21212121, 0xffffffffffffffc0 ); + TEST_RR_OP( 18, bclr, 0x21212121, 0x21212121, 0xffffffffffffffc1 ); + TEST_RR_OP( 19, bclr, 0x21212121, 0x21212121, 0xffffffffffffffc7 ); + TEST_RR_OP( 20, bclr, 0x84848484, 0x84848484, 0xffffffffffffffce ); + +#if __riscv_xlen == 64 + TEST_RR_OP( 21, bclr, 0x4484848421212121, 0xc484848421212121, 0xffffffffffffffff ); + TEST_RR_OP( 50, bclr, 0x0000000000000001, 0x0000000000000001, 63 ); + TEST_RR_OP( 51, bclr, 0xffffff7fffffffff, 0xffffffffffffffff, 39 ); + TEST_RR_OP( 52, bclr, 0xfffff7ff00000000, 0xffffffff00000000, 43 ); +#endif + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 22, bclr, 0x00000001, 0x00000001, 7 ); + TEST_RR_SRC2_EQ_DEST( 23, bclr, 0x00001551, 0x00005551, 14 ); + TEST_RR_SRC12_EQ_DEST( 24, bclr, 3, 3 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 25, 0, bclr, 0xff00ff00, 0xff00ff00, 0 ); + TEST_RR_DEST_BYPASS( 26, 1, bclr, 0x00ff00fd, 0x00ff00ff, 1 ); + TEST_RR_DEST_BYPASS( 27, 2, bclr, 0xff00fe00, 0xff00ff00, 8 ); + + TEST_RR_SRC12_BYPASS( 28, 0, 0, bclr, 0xff00ff00, 0xff00ff00, 0 ); + TEST_RR_SRC12_BYPASS( 29, 0, 1, bclr, 0x00ff00fd, 0x00ff00ff, 1 ); + TEST_RR_SRC12_BYPASS( 30, 0, 2, bclr, 0xff00fe00, 0xff00ff00, 8 ); + TEST_RR_SRC12_BYPASS( 31, 1, 0, bclr, 0xff00ff00, 0xff00ff00, 0 ); + TEST_RR_SRC12_BYPASS( 32, 1, 1, bclr, 0x00ff00fd, 0x00ff00ff, 1 ); + TEST_RR_SRC12_BYPASS( 33, 2, 0, bclr, 0xff00fe00, 0xff00ff00, 8 ); + + TEST_RR_SRC21_BYPASS( 34, 0, 0, bclr, 0xff00fe00, 0xff00ff00, 8 ); + TEST_RR_SRC21_BYPASS( 35, 0, 1, bclr, 0x0ff00ff0, 0x0ff00ff0, 14 ); + TEST_RR_SRC21_BYPASS( 36, 0, 2, bclr, 0x07f00ff0, 0x0ff00ff0, 27 ); + TEST_RR_SRC21_BYPASS( 37, 1, 0, bclr, 0xff00fe00, 0xff00ff00, 8 ); + TEST_RR_SRC21_BYPASS( 38, 1, 1, bclr, 0x0ff00ff0, 0x0ff00ff0, 14 ); + TEST_RR_SRC21_BYPASS( 39, 2, 0, bclr, 0x07f00ff0, 0x0ff00ff0, 27 ); + + TEST_RR_ZEROSRC1( 40, bclr, 0, 15 ); + TEST_RR_ZEROSRC2( 41, bclr, 32, 32 ); + TEST_RR_ZEROSRC12( 42, bclr, 0 ); + TEST_RR_ZERODEST( 43, bclr, 1024, 2048 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64uzbs/bclri.S b/tb/qumcu/isa/rv64uzbs/bclri.S new file mode 100644 index 0000000..3d4fdf9 --- /dev/null +++ b/tb/qumcu/isa/rv64uzbs/bclri.S @@ -0,0 +1,74 @@ +# See LICENSE for license details. + +#***************************************************************************** +# bclri.S +#----------------------------------------------------------------------------- +# +# Test bclri instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_IMM_OP( 2, bclri, 0xff00ff00, 0xff00ff00, 0 ); + TEST_IMM_OP( 3, bclri, 0x00ff00fd, 0x00ff00ff, 1 ); + TEST_IMM_OP( 4, bclri, 0xff00fe00, 0xff00ff00, 8 ); + TEST_IMM_OP( 5, bclri, 0x0ff00ff0, 0x0ff00ff0, 14 ); + TEST_IMM_OP( 6, bclri, 0x07f00ff0, 0x0ff00ff0, 27 ); + + TEST_IMM_OP( 7, bclri, 0xfffffffffffffffe, 0xffffffffffffffff, 0 ); + TEST_IMM_OP( 8, bclri, 0xfffffffffffffffd, 0xffffffffffffffff, 1 ); + TEST_IMM_OP( 9, bclri, 0xffffffffffffff7f, 0xffffffffffffffff, 7 ); + TEST_IMM_OP( 10, bclri, 0xffffffffffffbfff, 0xffffffffffffffff, 14 ); + TEST_IMM_OP( 11, bclri, 0xfffffffff7ffffff, 0xffffffffffffffff, 27 ); + + TEST_IMM_OP( 12, bclri, 0x21212120, 0x21212121, 0 ); + TEST_IMM_OP( 13, bclri, 0x21212121, 0x21212121, 1 ); + TEST_IMM_OP( 14, bclri, 0x21212121, 0x21212121, 7 ); + TEST_IMM_OP( 15, bclri, 0x21210121, 0x21212121, 13 ); + TEST_IMM_OP( 16, bclri, 0x04848484, 0x84848484, 31 ); + +#if __riscv_xlen == 64 + TEST_IMM_OP( 50, bclri, 0x0000000000000001, 0x0000000000000001, 63 ); + TEST_IMM_OP( 51, bclri, 0xffffff7fffffffff, 0xffffffffffffffff, 39 ); + TEST_IMM_OP( 52, bclri, 0xfffff7ff00000000, 0xffffffff00000000, 43 ); +#endif + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_IMM_SRC1_EQ_DEST( 17, bclri, 0x00000001, 0x00000001, 7 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_IMM_DEST_BYPASS( 18, 0, bclri, 0xff00fe00, 0xff00ff00, 8 ); + TEST_IMM_DEST_BYPASS( 19, 1, bclri, 0x0ff00ff0, 0x0ff00ff0, 14 ); + TEST_IMM_DEST_BYPASS( 20, 2, bclri, 0x07f00ff0, 0x0ff00ff0, 27 ); + + TEST_IMM_SRC1_BYPASS( 21, 0, bclri, 0xff00fe00, 0xff00ff00, 8 ); + TEST_IMM_SRC1_BYPASS( 22, 1, bclri, 0x0ff00ff0, 0x0ff00ff0, 14 ); + TEST_IMM_SRC1_BYPASS( 23, 2, bclri, 0x07f00ff0, 0x0ff00ff0, 27 ); + + TEST_IMM_ZEROSRC1( 24, bclri, 0, 31 ); + TEST_IMM_ZERODEST( 25, bclri, 33, 20 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64uzbs/bext.S b/tb/qumcu/isa/rv64uzbs/bext.S new file mode 100644 index 0000000..0440741 --- /dev/null +++ b/tb/qumcu/isa/rv64uzbs/bext.S @@ -0,0 +1,96 @@ +# See LICENSE for license details. + +#***************************************************************************** +# bext.S +#----------------------------------------------------------------------------- +# +# Test bext instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, bext, 0, 0xff00ff00, 0 ); + TEST_RR_OP( 3, bext, 1, 0x00ff00ff, 1 ); + TEST_RR_OP( 4, bext, 1, 0xff00ff00, 8 ); + TEST_RR_OP( 5, bext, 0, 0x0ff00ff0, 14 ); + TEST_RR_OP( 6, bext, 1, 0x0ff00ff0, 27 ); + + TEST_RR_OP( 7, bext, 1, 0xffffffffffffffff, 0 ); + TEST_RR_OP( 8, bext, 1, 0xffffffffffffffff, 1 ); + TEST_RR_OP( 9, bext, 1, 0xffffffffffffffff, 7 ); + TEST_RR_OP( 10, bext, 1, 0xffffffffffffffff, 14 ); + TEST_RR_OP( 11, bext, 1, 0xffffffffffffffff, 27 ); + + TEST_RR_OP( 12, bext, 1, 0x21212121, 0 ); + TEST_RR_OP( 13, bext, 0, 0x21212121, 1 ); + TEST_RR_OP( 14, bext, 0, 0x21212121, 7 ); + TEST_RR_OP( 15, bext, 1, 0x21212121, 13 ); + TEST_RR_OP( 16, bext, 1, 0x84848484, 31 ); + + # Verify that shifts only use bottom six(rv64) or five(rv32) bits + + TEST_RR_OP( 17, bext, 1, 0x21212121, 0xffffffffffffffc0 ); + TEST_RR_OP( 18, bext, 0, 0x21212121, 0xffffffffffffffc1 ); + TEST_RR_OP( 19, bext, 0, 0x21212121, 0xffffffffffffffc7 ); + TEST_RR_OP( 20, bext, 0, 0x84848484, 0xffffffffffffffce ); + +#if __riscv_xlen == 64 + TEST_RR_OP( 21, bext, 1, 0xc484848421212121, 0xffffffffffffffff ); + TEST_RR_OP( 50, bext, 0, 0x0000000000000001, 63 ); + TEST_RR_OP( 51, bext, 1, 0xffffffffffffffff, 39 ); + TEST_RR_OP( 52, bext, 1, 0xffffffff00000000, 43 ); +#endif + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 22, bext, 0, 0x00000001, 7 ); + TEST_RR_SRC2_EQ_DEST( 23, bext, 1, 0x00005551, 14 ); + TEST_RR_SRC12_EQ_DEST( 24, bext, 0, 3 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 25, 0, bext, 0, 0xff00ff00, 0 ); + TEST_RR_DEST_BYPASS( 26, 1, bext, 1, 0x00ff00ff, 1 ); + TEST_RR_DEST_BYPASS( 27, 2, bext, 1, 0xff00ff00, 8 ); + + TEST_RR_SRC12_BYPASS( 28, 0, 0, bext, 0, 0xff00ff00, 0 ); + TEST_RR_SRC12_BYPASS( 29, 0, 1, bext, 1, 0x00ff00ff, 1 ); + TEST_RR_SRC12_BYPASS( 30, 0, 2, bext, 1, 0xff00ff00, 8 ); + TEST_RR_SRC12_BYPASS( 31, 1, 0, bext, 0, 0xff00ff00, 0 ); + TEST_RR_SRC12_BYPASS( 32, 1, 1, bext, 1, 0x00ff00ff, 1 ); + TEST_RR_SRC12_BYPASS( 33, 2, 0, bext, 1, 0xff00ff00, 8 ); + + TEST_RR_SRC21_BYPASS( 34, 0, 0, bext, 1, 0xff00ff00, 8 ); + TEST_RR_SRC21_BYPASS( 35, 0, 1, bext, 0, 0x0ff00ff0, 14 ); + TEST_RR_SRC21_BYPASS( 36, 0, 2, bext, 1, 0x0ff00ff0, 27 ); + TEST_RR_SRC21_BYPASS( 37, 1, 0, bext, 1, 0xff00ff00, 8 ); + TEST_RR_SRC21_BYPASS( 38, 1, 1, bext, 0, 0x0ff00ff0, 14 ); + TEST_RR_SRC21_BYPASS( 39, 2, 0, bext, 1, 0x0ff00ff0, 27 ); + + TEST_RR_ZEROSRC1( 40, bext, 0, 15 ); + TEST_RR_ZEROSRC2( 41, bext, 0, 32 ); + TEST_RR_ZEROSRC12( 42, bext, 0 ); + TEST_RR_ZERODEST( 43, bext, 1024, 2048 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64uzbs/bexti.S b/tb/qumcu/isa/rv64uzbs/bexti.S new file mode 100644 index 0000000..19c9ed5 --- /dev/null +++ b/tb/qumcu/isa/rv64uzbs/bexti.S @@ -0,0 +1,74 @@ +# See LICENSE for license details. + +#***************************************************************************** +# bexti.S +#----------------------------------------------------------------------------- +# +# Test bexti instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_IMM_OP( 2, bexti, 0, 0xff00ff00, 0 ); + TEST_IMM_OP( 3, bexti, 1, 0x00ff00ff, 1 ); + TEST_IMM_OP( 4, bexti, 1, 0xff00ff00, 8 ); + TEST_IMM_OP( 5, bexti, 0, 0x0ff00ff0, 14 ); + TEST_IMM_OP( 6, bexti, 1, 0x0ff00ff0, 27 ); + + TEST_IMM_OP( 7, bexti, 1, 0xffffffffffffffff, 0 ); + TEST_IMM_OP( 8, bexti, 1, 0xffffffffffffffff, 1 ); + TEST_IMM_OP( 9, bexti, 1, 0xffffffffffffffff, 7 ); + TEST_IMM_OP( 10, bexti, 1, 0xffffffffffffffff, 14 ); + TEST_IMM_OP( 11, bexti, 1, 0xffffffffffffffff, 27 ); + + TEST_IMM_OP( 12, bexti, 1, 0x21212121, 0 ); + TEST_IMM_OP( 13, bexti, 0, 0x21212121, 1 ); + TEST_IMM_OP( 14, bexti, 0, 0x21212121, 7 ); + TEST_IMM_OP( 15, bexti, 1, 0x21212121, 13 ); + TEST_IMM_OP( 16, bexti, 1, 0x84848484, 31 ); + +#if __riscv_xlen == 64 + TEST_IMM_OP( 50, bexti, 0, 0x0000000000000001, 63 ); + TEST_IMM_OP( 51, bexti, 1, 0xffffffffffffffff, 39 ); + TEST_IMM_OP( 52, bexti, 1, 0xffffffff00000000, 43 ); +#endif + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_IMM_SRC1_EQ_DEST( 17, bexti, 0, 0x00000001, 7 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_IMM_DEST_BYPASS( 18, 0, bexti, 1, 0xff00ff00, 8 ); + TEST_IMM_DEST_BYPASS( 19, 1, bexti, 0, 0x0ff00ff0, 14 ); + TEST_IMM_DEST_BYPASS( 20, 2, bexti, 1, 0x0ff00ff0, 27 ); + + TEST_IMM_SRC1_BYPASS( 21, 0, bexti, 1, 0xff00ff00, 8 ); + TEST_IMM_SRC1_BYPASS( 22, 1, bexti, 0, 0x0ff00ff0, 14 ); + TEST_IMM_SRC1_BYPASS( 23, 2, bexti, 1, 0x0ff00ff0, 27 ); + + TEST_IMM_ZEROSRC1( 24, bexti, 0, 31 ); + TEST_IMM_ZERODEST( 25, bexti, 33, 20 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64uzbs/binv.S b/tb/qumcu/isa/rv64uzbs/binv.S new file mode 100644 index 0000000..853b398 --- /dev/null +++ b/tb/qumcu/isa/rv64uzbs/binv.S @@ -0,0 +1,96 @@ +# See LICENSE for license details. + +#***************************************************************************** +# binv.S +#----------------------------------------------------------------------------- +# +# Test binv instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, binv, 0x0000000000000000, 0x0000000000000001, 0 ); + TEST_RR_OP( 3, binv, 0x0000000000000003, 0x0000000000000001, 1 ); + TEST_RR_OP( 4, binv, 0x0000000000000081, 0x0000000000000001, 7 ); + TEST_RR_OP( 5, binv, 0x0000000000004001, 0x0000000000000001, 14 ); + TEST_RR_OP( 6, binv, 0x0000000080000001, 0x0000000000000001, 31 ); + + TEST_RR_OP( 7, binv, 0xfffffffffffffffe, 0xffffffffffffffff, 0 ); + TEST_RR_OP( 8, binv, 0xfffffffffffffffd, 0xffffffffffffffff, 1 ); + TEST_RR_OP( 9, binv, 0xffffffffffffff7f, 0xffffffffffffffff, 7 ); + TEST_RR_OP( 10, binv, 0xffffffffffffbfff, 0xffffffffffffffff, 14 ); + TEST_RR_OP( 11, binv, 0xffffffff7fffffff, 0xffffffffffffffff, 31 ); + + TEST_RR_OP( 12, binv, 0x0000000021212120, 0x0000000021212121, 0 ); + TEST_RR_OP( 13, binv, 0x0000000021212123, 0x0000000021212121, 1 ); + TEST_RR_OP( 14, binv, 0x00000000212121a1, 0x0000000021212121, 7 ); + TEST_RR_OP( 15, binv, 0x0000000021216121, 0x0000000021212121, 14 ); + TEST_RR_OP( 16, binv, 0x00000000a1212121, 0x0000000021212121, 31 ); + + # Verify that shifts only use bottom six(rv64) or five(rv32) bits + + TEST_RR_OP( 17, binv, 0x0000000021212120, 0x0000000021212121, 0xffffffffffffffc0 ); + TEST_RR_OP( 18, binv, 0x0000000021212123, 0x0000000021212121, 0xffffffffffffffc1 ); + TEST_RR_OP( 19, binv, 0x00000000212121a1, 0x0000000021212121, 0xffffffffffffffc7 ); + TEST_RR_OP( 20, binv, 0x0000000021216121, 0x0000000021212121, 0xffffffffffffffce ); + +#if __riscv_xlen == 64 + TEST_RR_OP( 21, binv, 0x8000000021212121, 0x0000000021212121, 0xffffffffffffffff ); + TEST_RR_OP( 50, binv, 0x8000000000000001, 0x0000000000000001, 63 ); + TEST_RR_OP( 51, binv, 0xffffff7fffffffff, 0xffffffffffffffff, 39 ); + TEST_RR_OP( 52, binv, 0x0000080021212121, 0x0000000021212121, 43 ); +#endif + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 22, binv, 0x00000081, 0x00000001, 7 ); + TEST_RR_SRC2_EQ_DEST( 23, binv, 0x00004001, 0x00000001, 14 ); + TEST_RR_SRC12_EQ_DEST( 24, binv, 11, 3 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 25, 0, binv, 0x0000000000000081, 0x0000000000000001, 7 ); + TEST_RR_DEST_BYPASS( 26, 1, binv, 0x0000000000004001, 0x0000000000000001, 14 ); + TEST_RR_DEST_BYPASS( 27, 2, binv, 0x0000000080000001, 0x0000000000000001, 31 ); + + TEST_RR_SRC12_BYPASS( 28, 0, 0, binv, 0x0000000000000081, 0x0000000000000001, 7 ); + TEST_RR_SRC12_BYPASS( 29, 0, 1, binv, 0x0000000000004001, 0x0000000000000001, 14 ); + TEST_RR_SRC12_BYPASS( 30, 0, 2, binv, 0x0000000080000001, 0x0000000000000001, 31 ); + TEST_RR_SRC12_BYPASS( 31, 1, 0, binv, 0x0000000000000081, 0x0000000000000001, 7 ); + TEST_RR_SRC12_BYPASS( 32, 1, 1, binv, 0x0000000000004001, 0x0000000000000001, 14 ); + TEST_RR_SRC12_BYPASS( 33, 2, 0, binv, 0x0000000080000001, 0x0000000000000001, 31 ); + + TEST_RR_SRC21_BYPASS( 34, 0, 0, binv, 0x0000000000000081, 0x0000000000000001, 7 ); + TEST_RR_SRC21_BYPASS( 35, 0, 1, binv, 0x0000000000004001, 0x0000000000000001, 14 ); + TEST_RR_SRC21_BYPASS( 36, 0, 2, binv, 0x0000000080000001, 0x0000000000000001, 31 ); + TEST_RR_SRC21_BYPASS( 37, 1, 0, binv, 0x0000000000000081, 0x0000000000000001, 7 ); + TEST_RR_SRC21_BYPASS( 38, 1, 1, binv, 0x0000000000004001, 0x0000000000000001, 14 ); + TEST_RR_SRC21_BYPASS( 39, 2, 0, binv, 0x0000000080000001, 0x0000000000000001, 31 ); + + TEST_RR_ZEROSRC1( 40, binv, 0x00008000, 15 ); + TEST_RR_ZEROSRC2( 41, binv, 33, 32 ); + TEST_RR_ZEROSRC12( 42, binv, 1 ); + TEST_RR_ZERODEST( 43, binv, 1024, 2048 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64uzbs/binvi.S b/tb/qumcu/isa/rv64uzbs/binvi.S new file mode 100644 index 0000000..07af1f4 --- /dev/null +++ b/tb/qumcu/isa/rv64uzbs/binvi.S @@ -0,0 +1,75 @@ +# See LICENSE for license details. + +#***************************************************************************** +# binvi.S +#----------------------------------------------------------------------------- +# +# Test binvi instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_IMM_OP( 2, binvi, 0x0000000000000000, 0x0000000000000001, 0 ); + TEST_IMM_OP( 3, binvi, 0x0000000000000003, 0x0000000000000001, 1 ); + TEST_IMM_OP( 4, binvi, 0x0000000000000081, 0x0000000000000001, 7 ); + TEST_IMM_OP( 5, binvi, 0x0000000000004001, 0x0000000000000001, 14 ); + TEST_IMM_OP( 6, binvi, 0x0000000080000001, 0x0000000000000001, 31 ); + + TEST_IMM_OP( 7, binvi, 0xfffffffffffffffe, 0xffffffffffffffff, 0 ); + TEST_IMM_OP( 8, binvi, 0xfffffffffffffffd, 0xffffffffffffffff, 1 ); + TEST_IMM_OP( 9, binvi, 0xffffffffffffff7f, 0xffffffffffffffff, 7 ); + TEST_IMM_OP( 10, binvi, 0xffffffffffffbfff, 0xffffffffffffffff, 14 ); + TEST_IMM_OP( 11, binvi, 0xffffffff7fffffff, 0xffffffffffffffff, 31 ); + + TEST_IMM_OP( 12, binvi, 0x0000000021212120, 0x0000000021212121, 0 ); + TEST_IMM_OP( 13, binvi, 0x0000000021212123, 0x0000000021212121, 1 ); + TEST_IMM_OP( 14, binvi, 0x00000000212121a1, 0x0000000021212121, 7 ); + TEST_IMM_OP( 15, binvi, 0x0000000021216121, 0x0000000021212121, 14 ); + TEST_IMM_OP( 16, binvi, 0x00000000a1212121, 0x0000000021212121, 31 ); + +#if __riscv_xlen == 64 + TEST_IMM_OP( 50, binvi, 0x8000000000000001, 0x0000000000000001, 63 ); + TEST_IMM_OP( 51, binvi, 0xffffff7fffffffff, 0xffffffffffffffff, 39 ); + TEST_IMM_OP( 52, binvi, 0x0000080021212121, 0x0000000021212121, 43 ); +#endif + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_IMM_SRC1_EQ_DEST( 17, binvi, 0x00000081, 0x00000001, 7 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_IMM_DEST_BYPASS( 18, 0, binvi, 0x0000000000000081, 0x0000000000000001, 7 ); + TEST_IMM_DEST_BYPASS( 19, 1, binvi, 0x0000000000004001, 0x0000000000000001, 14 ); + TEST_IMM_DEST_BYPASS( 20, 2, binvi, 0x0000000080000001, 0x0000000000000001, 31 ); + + TEST_IMM_SRC1_BYPASS( 21, 0, binvi, 0x0000000000000081, 0x0000000000000001, 7 ); + TEST_IMM_SRC1_BYPASS( 22, 1, binvi, 0x0000000000004001, 0x0000000000000001, 14 ); + TEST_IMM_SRC1_BYPASS( 23, 2, binvi, 0x0000000080000001, 0x0000000000000001, 31 ); + + + TEST_IMM_ZEROSRC1( 24, binvi, 0x00008000, 15 ); + TEST_IMM_ZERODEST( 25, binvi, 1024, 10 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64uzbs/bset.S b/tb/qumcu/isa/rv64uzbs/bset.S new file mode 100644 index 0000000..ee80b60 --- /dev/null +++ b/tb/qumcu/isa/rv64uzbs/bset.S @@ -0,0 +1,96 @@ +# See LICENSE for license details. + +#***************************************************************************** +# bset.S +#----------------------------------------------------------------------------- +# +# Test bset instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, bset, 0xff00ff01, 0xff00ff00, 0 ); + TEST_RR_OP( 3, bset, 0x00ff00ff, 0x00ff00ff, 1 ); + TEST_RR_OP( 4, bset, 0xff00ff00, 0xff00ff00, 8 ); + TEST_RR_OP( 5, bset, 0x0ff04ff0, 0x0ff00ff0, 14 ); + TEST_RR_OP( 6, bset, 0x0ff00ff0, 0x0ff00ff0, 27 ); + + TEST_RR_OP( 7, bset, 0x0000000000000001, 0x0000000000000001, 0 ); + TEST_RR_OP( 8, bset, 0x0000000000000003, 0x0000000000000001, 1 ); + TEST_RR_OP( 9, bset, 0x0000000000000081, 0x0000000000000001, 7 ); + TEST_RR_OP( 10, bset, 0x0000000000004001, 0x0000000000000001, 14 ); + TEST_RR_OP( 11, bset, 0x0000000080000001, 0x0000000000000001, 31 ); + + TEST_RR_OP( 12, bset, 0x21212121, 0x21212121, 0 ); + TEST_RR_OP( 13, bset, 0x21212123, 0x21212121, 1 ); + TEST_RR_OP( 14, bset, 0x212121a1, 0x21212121, 7 ); + TEST_RR_OP( 15, bset, 0x21212121, 0x21212121, 13 ); + TEST_RR_OP( 16, bset, 0x84848484, 0x84848484, 31 ); + + # Verify that shifts only use bottom six(rv64) or five(rv32) bits + + TEST_RR_OP( 17, bset, 0x21212121, 0x21212121, 0xffffffffffffffc0 ); + TEST_RR_OP( 18, bset, 0x21212123, 0x21212121, 0xffffffffffffffc1 ); + TEST_RR_OP( 19, bset, 0x212121a1, 0x21212121, 0xffffffffffffffc7 ); + TEST_RR_OP( 20, bset, 0x8484c484, 0x84848484, 0xffffffffffffffce ); + +#if __riscv_xlen == 64 + TEST_RR_OP( 21, bset, 0xc484848421212121, 0xc484848421212121, 0xffffffffffffffff ); + TEST_RR_OP( 50, bset, 0x8000000000000001, 0x0000000000000001, 63 ); + TEST_RR_OP( 51, bset, 0xffffffffffffffff, 0xffffffffffffffff, 39 ); + TEST_RR_OP( 52, bset, 0xffffffff00000000, 0xffffffff00000000, 43 ); +#endif + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 22, bset, 0x00000081, 0x00000001, 7 ); + TEST_RR_SRC2_EQ_DEST( 23, bset, 0x00005551, 0x00005551, 14 ); + TEST_RR_SRC12_EQ_DEST( 24, bset, 11, 3 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 25, 0, bset, 0xff00ff01, 0xff00ff00, 0 ); + TEST_RR_DEST_BYPASS( 26, 1, bset, 0x00ff00ff, 0x00ff00ff, 1 ); + TEST_RR_DEST_BYPASS( 27, 2, bset, 0xff00ff00, 0xff00ff00, 8 ); + + TEST_RR_SRC12_BYPASS( 28, 0, 0, bset, 0xff00ff01, 0xff00ff00, 0 ); + TEST_RR_SRC12_BYPASS( 29, 0, 1, bset, 0x00ff00ff, 0x00ff00ff, 1 ); + TEST_RR_SRC12_BYPASS( 30, 0, 2, bset, 0xff00ff00, 0xff00ff00, 8 ); + TEST_RR_SRC12_BYPASS( 31, 1, 0, bset, 0xff00ff01, 0xff00ff00, 0 ); + TEST_RR_SRC12_BYPASS( 32, 1, 1, bset, 0x00ff00ff, 0x00ff00ff, 1 ); + TEST_RR_SRC12_BYPASS( 33, 2, 0, bset, 0xff00ff00, 0xff00ff00, 8 ); + + TEST_RR_SRC21_BYPASS( 34, 0, 0, bset, 0xff00ff00, 0xff00ff00, 8 ); + TEST_RR_SRC21_BYPASS( 35, 0, 1, bset, 0x0ff04ff0, 0x0ff00ff0, 14 ); + TEST_RR_SRC21_BYPASS( 36, 0, 2, bset, 0x0ff00ff0, 0x0ff00ff0, 27 ); + TEST_RR_SRC21_BYPASS( 37, 1, 0, bset, 0xff00ff00, 0xff00ff00, 8 ); + TEST_RR_SRC21_BYPASS( 38, 1, 1, bset, 0x0ff04ff0, 0x0ff00ff0, 14 ); + TEST_RR_SRC21_BYPASS( 39, 2, 0, bset, 0x0ff00ff0, 0x0ff00ff0, 27 ); + + TEST_RR_ZEROSRC1( 40, bset, 0x00008000, 15 ); + TEST_RR_ZEROSRC2( 41, bset, 33, 32 ); + TEST_RR_ZEROSRC12( 42, bset, 1 ); + TEST_RR_ZERODEST( 43, bset, 1024, 2048 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64uzbs/bseti.S b/tb/qumcu/isa/rv64uzbs/bseti.S new file mode 100644 index 0000000..35a5501 --- /dev/null +++ b/tb/qumcu/isa/rv64uzbs/bseti.S @@ -0,0 +1,74 @@ +# See LICENSE for license details. + +#***************************************************************************** +# bset.S +#----------------------------------------------------------------------------- +# +# Test bset instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_IMM_OP( 2, bset, 0xff00ff01, 0xff00ff00, 0 ); + TEST_IMM_OP( 3, bset, 0x00ff00ff, 0x00ff00ff, 1 ); + TEST_IMM_OP( 4, bset, 0xff00ff00, 0xff00ff00, 8 ); + TEST_IMM_OP( 5, bset, 0x0ff04ff0, 0x0ff00ff0, 14 ); + TEST_IMM_OP( 6, bset, 0x0ff00ff0, 0x0ff00ff0, 27 ); + + TEST_IMM_OP( 7, bset, 0x0000000000000001, 0x0000000000000001, 0 ); + TEST_IMM_OP( 8, bset, 0x0000000000000003, 0x0000000000000001, 1 ); + TEST_IMM_OP( 9, bset, 0x0000000000000081, 0x0000000000000001, 7 ); + TEST_IMM_OP( 10, bset, 0x0000000000004001, 0x0000000000000001, 14 ); + TEST_IMM_OP( 11, bset, 0x0000000080000001, 0x0000000000000001, 31 ); + + TEST_IMM_OP( 12, bset, 0x21212121, 0x21212121, 0 ); + TEST_IMM_OP( 13, bset, 0x21212123, 0x21212121, 1 ); + TEST_IMM_OP( 14, bset, 0x212121a1, 0x21212121, 7 ); + TEST_IMM_OP( 15, bset, 0x21212121, 0x21212121, 13 ); + TEST_IMM_OP( 16, bset, 0x84848484, 0x84848484, 31 ); + +#if __riscv_xlen == 64 + TEST_IMM_OP( 50, bset, 0x8000000000000001, 0x0000000000000001, 63 ); + TEST_IMM_OP( 51, bset, 0xffffffffffffffff, 0xffffffffffffffff, 39 ); + TEST_IMM_OP( 52, bset, 0xffffffff00000000, 0xffffffff00000000, 43 ); +#endif + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_IMM_SRC1_EQ_DEST( 17, bset, 0x00000081, 0x00000001, 7 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_IMM_DEST_BYPASS( 18, 0, bset, 0xff00ff01, 0xff00ff00, 0 ); + TEST_IMM_DEST_BYPASS( 19, 1, bset, 0x00ff00ff, 0x00ff00ff, 1 ); + TEST_IMM_DEST_BYPASS( 20, 2, bset, 0xff00ff00, 0xff00ff00, 8 ); + + TEST_IMM_SRC1_BYPASS( 21, 0, bset, 0xff00ff00, 0xff00ff00, 8 ); + TEST_IMM_SRC1_BYPASS( 22, 1, bset, 0x0ff04ff0, 0x0ff00ff0, 14 ); + TEST_IMM_SRC1_BYPASS( 23, 2, bset, 0x0ff00ff0, 0x0ff00ff0, 27 ); + + TEST_IMM_ZEROSRC1( 24, bset, 0x00008000, 15 ); + TEST_IMM_ZERODEST( 25, bset, 1024, 10 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64uzfh/Makefrag b/tb/qumcu/isa/rv64uzfh/Makefrag new file mode 100644 index 0000000..af247fd --- /dev/null +++ b/tb/qumcu/isa/rv64uzfh/Makefrag @@ -0,0 +1,10 @@ +#======================================================================= +# Makefrag for rv64uzfh tests +#----------------------------------------------------------------------- + +rv64uzfh_sc_tests = \ + fadd fdiv fclass fcmp fcvt fcvt_w fmadd fmin \ + ldst move recoding \ + +rv64uzfh_p_tests = $(addprefix rv64uzfh-p-, $(rv64uzfh_sc_tests)) +rv64uzfh_v_tests = $(addprefix rv64uzfh-v-, $(rv64uzfh_sc_tests)) diff --git a/tb/qumcu/isa/rv64uzfh/fadd.S b/tb/qumcu/isa/rv64uzfh/fadd.S new file mode 100644 index 0000000..6ca7f33 --- /dev/null +++ b/tb/qumcu/isa/rv64uzfh/fadd.S @@ -0,0 +1,44 @@ +# See LICENSE for license details. + +#***************************************************************************** +# fadd.S +#----------------------------------------------------------------------------- +# +# Test f{add|sub|mul}.h instructions. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64UF +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_FP_OP2_H( 2, fadd.h, 0, 3.5, 2.5, 1.0 ); + TEST_FP_OP2_H( 3, fadd.h, 1, -1234, -1235.1, 1.1 ); + TEST_FP_OP2_H( 4, fadd.h, 1, 3.14, 3.13, 0.01 ); + + TEST_FP_OP2_H( 5, fsub.h, 0, 1.5, 2.5, 1.0 ); + TEST_FP_OP2_H( 6, fsub.h, 1, -1234, -1235.1, -1.1 ); + TEST_FP_OP2_H( 7, fsub.h, 1, 3.14, 3.15, 0.01 ); + + TEST_FP_OP2_H( 8, fmul.h, 0, 2.5, 2.5, 1.0 ); + TEST_FP_OP2_H( 9, fmul.h, 0, 1235.1, -1235.1, -1.0 ); + TEST_FP_OP2_H(10, fmul.h, 1, 1.1, 11.0, 0.1 ); + + # Is the canonical NaN generated for Inf - Inf? + TEST_FP_OP2_H(11, fsub.h, 0x10, qNaNh, Inf, Inf); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64uzfh/fclass.S b/tb/qumcu/isa/rv64uzfh/fclass.S new file mode 100644 index 0000000..86af7e5 --- /dev/null +++ b/tb/qumcu/isa/rv64uzfh/fclass.S @@ -0,0 +1,44 @@ +# See LICENSE for license details. + +#***************************************************************************** +# fclass.S +#----------------------------------------------------------------------------- +# +# Test fclass.h instructions. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64UF +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + #define TEST_FCLASS_H(testnum, correct, input) \ + TEST_CASE(testnum, a0, correct, li a0, input; fmv.h.x fa0, a0; \ + fclass.h a0, fa0) + + TEST_FCLASS_H( 2, 1 << 0, 0xfc00 ) + TEST_FCLASS_H( 3, 1 << 1, 0xbc00 ) + TEST_FCLASS_H( 4, 1 << 2, 0x83ff ) + TEST_FCLASS_H( 5, 1 << 3, 0x8000 ) + TEST_FCLASS_H( 6, 1 << 4, 0x0000 ) + TEST_FCLASS_H( 7, 1 << 5, 0x03ff ) + TEST_FCLASS_H( 8, 1 << 6, 0x3c00 ) + TEST_FCLASS_H( 9, 1 << 7, 0x7c00 ) + TEST_FCLASS_H(10, 1 << 8, 0x7c01 ) + TEST_FCLASS_H(11, 1 << 9, 0x7e00 ) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64uzfh/fcmp.S b/tb/qumcu/isa/rv64uzfh/fcmp.S new file mode 100644 index 0000000..9f8a4e3 --- /dev/null +++ b/tb/qumcu/isa/rv64uzfh/fcmp.S @@ -0,0 +1,37 @@ +# See LICENSE for license details. + +#***************************************************************************** +# fcmp.S +#----------------------------------------------------------------------------- +# +# Test f{eq|lt|le}.h instructions. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64UF +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_FP_CMP_OP_H( 2, feq.h, 0x00, 1, -1.36, -1.36) + TEST_FP_CMP_OP_H( 3, fle.h, 0x00, 1, -1.36, -1.36) + TEST_FP_CMP_OP_H( 4, flt.h, 0x00, 0, -1.36, -1.36) + + TEST_FP_CMP_OP_H( 5, feq.h, 0x00, 0, -1.37, -1.36) + TEST_FP_CMP_OP_H( 6, fle.h, 0x00, 1, -1.37, -1.36) + TEST_FP_CMP_OP_H( 7, flt.h, 0x00, 1, -1.37, -1.36) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64uzfh/fcvt.S b/tb/qumcu/isa/rv64uzfh/fcvt.S new file mode 100644 index 0000000..5f130e1 --- /dev/null +++ b/tb/qumcu/isa/rv64uzfh/fcvt.S @@ -0,0 +1,49 @@ +# See LICENSE for license details. + +#***************************************************************************** +# fcvt.S +#----------------------------------------------------------------------------- +# +# Test fcvt.h.{wu|w|lu|l}, fcvt.h.d, and fcvt.d.h instructions. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64UF +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_INT_FP_OP_H( 2, fcvt.h.w, 2.0, 2); + TEST_INT_FP_OP_H( 3, fcvt.h.w, -2.0, -2); + + TEST_INT_FP_OP_H( 4, fcvt.h.wu, 2.0, 2); + TEST_INT_FP_OP_H( 5, fcvt.h.wu, 0h:7c00, -2); + +#if __riscv_xlen >= 64 + TEST_INT_FP_OP_H( 6, fcvt.h.l, 2.0, 2); + TEST_INT_FP_OP_H( 7, fcvt.h.l, -2.0, -2); + + TEST_INT_FP_OP_H( 8, fcvt.h.lu, 2.0, 2); + TEST_INT_FP_OP_H( 9, fcvt.h.lu, 0h:7c00, -2); +#endif + + TEST_FCVT_H_S( 10, -1.5, -1.5) + +#if __riscv_xlen >= 64 + TEST_FCVT_H_D( 11, -1.5, -1.5) +#endif + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64uzfh/fcvt_w.S b/tb/qumcu/isa/rv64uzfh/fcvt_w.S new file mode 100644 index 0000000..013ecac --- /dev/null +++ b/tb/qumcu/isa/rv64uzfh/fcvt_w.S @@ -0,0 +1,104 @@ +# See LICENSE for license details. +#***************************************************************************** +# fcvt_w.S +#----------------------------------------------------------------------------- +# +# Test fcvt{wu|w|lu|l}.h instructions. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64UF +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_FP_INT_OP_H( 2, fcvt.w.h, 0x01, -1, -1.1, rtz); + TEST_FP_INT_OP_H( 3, fcvt.w.h, 0x00, -1, -1.0, rtz); + TEST_FP_INT_OP_H( 4, fcvt.w.h, 0x01, 0, -0.9, rtz); + TEST_FP_INT_OP_H( 5, fcvt.w.h, 0x01, 0, 0.9, rtz); + TEST_FP_INT_OP_H( 6, fcvt.w.h, 0x00, 1, 1.0, rtz); + TEST_FP_INT_OP_H( 7, fcvt.w.h, 0x01, 1, 1.1, rtz); + TEST_FP_INT_OP_H( 8, fcvt.w.h, 0x00, -2054, 0h:e803, rtz); + TEST_FP_INT_OP_H( 9, fcvt.w.h, 0x00, 2054, 0h:6803, rtz); + + TEST_FP_INT_OP_H(12, fcvt.wu.h, 0x10, 0, -3.0, rtz); + TEST_FP_INT_OP_H(13, fcvt.wu.h, 0x10, 0, -1.0, rtz); + TEST_FP_INT_OP_H(14, fcvt.wu.h, 0x01, 0, -0.9, rtz); + TEST_FP_INT_OP_H(15, fcvt.wu.h, 0x01, 0, 0.9, rtz); + TEST_FP_INT_OP_H(16, fcvt.wu.h, 0x00, 1, 1.0, rtz); + TEST_FP_INT_OP_H(17, fcvt.wu.h, 0x01, 1, 1.1, rtz); + TEST_FP_INT_OP_H(18, fcvt.wu.h, 0x10, 0, 0h:e803, rtz); + TEST_FP_INT_OP_H(19, fcvt.wu.h, 0x00, 2054, 0h:6803, rtz); + +#if __riscv_xlen >= 64 + TEST_FP_INT_OP_H(22, fcvt.l.h, 0x01, -1, -1.1, rtz); + TEST_FP_INT_OP_H(23, fcvt.l.h, 0x00, -1, -1.0, rtz); + TEST_FP_INT_OP_H(24, fcvt.l.h, 0x01, 0, -0.9, rtz); + TEST_FP_INT_OP_H(25, fcvt.l.h, 0x01, 0, 0.9, rtz); + TEST_FP_INT_OP_H(26, fcvt.l.h, 0x00, 1, 1.0, rtz); + TEST_FP_INT_OP_H(27, fcvt.l.h, 0x01, 1, 1.1, rtz); + + TEST_FP_INT_OP_H(32, fcvt.lu.h, 0x10, 0, -3.0, rtz); + TEST_FP_INT_OP_H(33, fcvt.lu.h, 0x10, 0, -1.0, rtz); + TEST_FP_INT_OP_H(34, fcvt.lu.h, 0x01, 0, -0.9, rtz); + TEST_FP_INT_OP_H(35, fcvt.lu.h, 0x01, 0, 0.9, rtz); + TEST_FP_INT_OP_H(36, fcvt.lu.h, 0x00, 1, 1.0, rtz); + TEST_FP_INT_OP_H(37, fcvt.lu.h, 0x01, 1, 1.1, rtz); + TEST_FP_INT_OP_H(38, fcvt.lu.h, 0x10, 0, 0h:e483, rtz); +#endif + + # test negative NaN, negative infinity conversion + TEST_CASE( 42, x1, 0x000000007fffffff, la x1, tdat ; flw f1, 0(x1); fcvt.w.h x1, f1) + TEST_CASE( 43, x1, 0xffffffff80000000, la x1, tdat ; flw f1, 8(x1); fcvt.w.h x1, f1) +#if __riscv_xlen >= 64 + TEST_CASE( 44, x1, 0x7fffffffffffffff, la x1, tdat ; flw f1, 0(x1); fcvt.l.h x1, f1) + TEST_CASE( 45, x1, 0x8000000000000000, la x1, tdat ; flw f1, 8(x1); fcvt.l.h x1, f1) +#endif + + # test positive NaN, positive infinity conversion + TEST_CASE( 52, x1, 0x000000007fffffff, la x1, tdat ; flw f1, 4(x1); fcvt.w.h x1, f1) + TEST_CASE( 53, x1, 0x000000007fffffff, la x1, tdat ; flw f1, 12(x1); fcvt.w.h x1, f1) +#if __riscv_xlen >= 64 + TEST_CASE( 54, x1, 0x7fffffffffffffff, la x1, tdat ; flw f1, 4(x1); fcvt.l.h x1, f1) + TEST_CASE( 55, x1, 0x7fffffffffffffff, la x1, tdat ; flw f1, 12(x1); fcvt.l.h x1, f1) +#endif + + # test NaN, infinity conversions to unsigned integer + TEST_CASE( 62, x1, 0xffffffffffffffff, la x1, tdat ; flw f1, 0(x1); fcvt.wu.h x1, f1) + TEST_CASE( 63, x1, 0xffffffffffffffff, la x1, tdat ; flw f1, 4(x1); fcvt.wu.h x1, f1) + TEST_CASE( 64, x1, 0, la x1, tdat ; flw f1, 8(x1); fcvt.wu.h x1, f1) + TEST_CASE( 65, x1, 0xffffffffffffffff, la x1, tdat ; flw f1, 12(x1); fcvt.wu.h x1, f1) +#if __riscv_xlen >= 64 + TEST_CASE( 66, x1, 0xffffffffffffffff, la x1, tdat ; flw f1, 0(x1); fcvt.lu.h x1, f1) + TEST_CASE( 67, x1, 0xffffffffffffffff, la x1, tdat ; flw f1, 4(x1); fcvt.lu.h x1, f1) + TEST_CASE( 68, x1, 0, la x1, tdat ; flw f1, 8(x1); fcvt.lu.h x1, f1) + TEST_CASE( 69, x1, 0xffffffffffffffff, la x1, tdat ; flw f1, 12(x1); fcvt.lu.h x1, f1) +#endif + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +# -NaN, NaN, -inf, +inf +#tdat: +#.word 0xffffffff +#.word 0x7fffffff +#.word 0xff800000 +#.word 0x7f800000 + +tdat: +.word 0xffffffff +.word 0xffff7fff +.word 0xfffffc00 +.word 0xffff7c00 + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64uzfh/fdiv.S b/tb/qumcu/isa/rv64uzfh/fdiv.S new file mode 100644 index 0000000..894ebfc --- /dev/null +++ b/tb/qumcu/isa/rv64uzfh/fdiv.S @@ -0,0 +1,41 @@ +# See LICENSE for license details. + +#***************************************************************************** +# fdiv.S +#----------------------------------------------------------------------------- +# +# Test f{div|sqrt}.h instructions. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64UF +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_FP_OP2_H(2, fdiv.h, 1, 1.1557273520668288, 3.14159265, 2.71828182 ); + TEST_FP_OP2_H(3, fdiv.h, 1,-0.9991093838555584, -1234, 1235.1 ); + TEST_FP_OP2_H(4, fdiv.h, 0, 3.14159265, 3.14159265, 1.0 ); + + TEST_FP_OP1_H(5, fsqrt.h, 1, 1.7724538498928541, 3.14159265 ); + TEST_FP_OP1_H(6, fsqrt.h, 0, 100, 10000 ); + + TEST_FP_OP1_H_DWORD_RESULT(7, fsqrt.h, 0x10, 0x00007e00, -1.0 ); + + TEST_FP_OP1_H(8, fsqrt.h, 1, 13.076696, 171.0); + + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64uzfh/fmadd.S b/tb/qumcu/isa/rv64uzfh/fmadd.S new file mode 100644 index 0000000..2b49763 --- /dev/null +++ b/tb/qumcu/isa/rv64uzfh/fmadd.S @@ -0,0 +1,45 @@ +# See LICENSE for license details. + +#***************************************************************************** +# fmadd.S +#----------------------------------------------------------------------------- +# +# Test f[n]m{add|sub}.h and f[n]m{add|sub}.h instructions. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64UF +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_FP_OP3_H( 2, fmadd.h, 0, 3.5, 1.0, 2.5, 1.0 ); + TEST_FP_OP3_H( 3, fmadd.h, 1, 13.2, -1.0, -12.1, 1.1 ); + TEST_FP_OP3_H( 4, fmadd.h, 0, -12.0, 2.0, -5.0, -2.0 ); + + TEST_FP_OP3_H( 5, fnmadd.h, 0, -3.5, 1.0, 2.5, 1.0 ); + TEST_FP_OP3_H( 6, fnmadd.h, 1, -13.2, -1.0, -12.1, 1.1 ); + TEST_FP_OP3_H( 7, fnmadd.h, 0, 12.0, 2.0, -5.0, -2.0 ); + + TEST_FP_OP3_H( 8, fmsub.h, 0, 1.5, 1.0, 2.5, 1.0 ); + TEST_FP_OP3_H( 9, fmsub.h, 1, 11, -1.0, -12.1, 1.1 ); + TEST_FP_OP3_H(10, fmsub.h, 0, -8.0, 2.0, -5.0, -2.0 ); + + TEST_FP_OP3_H(11, fnmsub.h, 0, -1.5, 1.0, 2.5, 1.0 ); + TEST_FP_OP3_H(12, fnmsub.h, 1, -11, -1.0, -12.1, 1.1 ); + TEST_FP_OP3_H(13, fnmsub.h, 0, 8.0, 2.0, -5.0, -2.0 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64uzfh/fmin.S b/tb/qumcu/isa/rv64uzfh/fmin.S new file mode 100644 index 0000000..3feec99 --- /dev/null +++ b/tb/qumcu/isa/rv64uzfh/fmin.S @@ -0,0 +1,54 @@ +# See LICENSE for license details. + +#***************************************************************************** +# fmin.S +#----------------------------------------------------------------------------- +# +# Test f{min|max}.h instructinos. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64UF +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_FP_OP2_H( 2, fmin.h, 0, 1.0, 2.5, 1.0 ); + TEST_FP_OP2_H( 3, fmin.h, 0, -1235.1, -1235.1, 1.1 ); + TEST_FP_OP2_H( 4, fmin.h, 0, -1235.1, 1.1, -1235.1 ); + TEST_FP_OP2_H( 5, fmin.h, 0, -1235.1, NaN, -1235.1 ); + TEST_FP_OP2_H( 6, fmin.h, 0, 0.00000001, 3.14159265, 0.00000001 ); + TEST_FP_OP2_H( 7, fmin.h, 0, -2.0, -1.0, -2.0 ); + + TEST_FP_OP2_H(12, fmax.h, 0, 2.5, 2.5, 1.0 ); + TEST_FP_OP2_H(13, fmax.h, 0, 1.1, -1235.1, 1.1 ); + TEST_FP_OP2_H(14, fmax.h, 0, 1.1, 1.1, -1235.1 ); + TEST_FP_OP2_H(15, fmax.h, 0, -1235.1, NaN, -1235.1 ); + TEST_FP_OP2_H(16, fmax.h, 0, 3.14159265, 3.14159265, 0.00000001 ); + TEST_FP_OP2_H(17, fmax.h, 0, -1.0, -1.0, -2.0 ); + + # FMIN(hNaN, x) = x + TEST_FP_OP2_H(20, fmax.h, 0x10, 1.0, sNaNh, 1.0); + # FMIN(hNaN, hNaN) = canonical NaN + TEST_FP_OP2_H(21, fmax.h, 0x00, qNaNh, NaN, NaN); + + # -0.0 < +0.0 + TEST_FP_OP2_H(30, fmin.h, 0, -0.0, -0.0, 0.0 ); + TEST_FP_OP2_H(31, fmin.h, 0, -0.0, 0.0, -0.0 ); + TEST_FP_OP2_H(32, fmax.h, 0, 0.0, -0.0, 0.0 ); + TEST_FP_OP2_H(33, fmax.h, 0, 0.0, 0.0, -0.0 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64uzfh/ldst.S b/tb/qumcu/isa/rv64uzfh/ldst.S new file mode 100644 index 0000000..ff1cdab --- /dev/null +++ b/tb/qumcu/isa/rv64uzfh/ldst.S @@ -0,0 +1,38 @@ +# See LICENSE for license details. + +#***************************************************************************** +# ldst.S +#----------------------------------------------------------------------------- +# +# This test verifies that flw, fld, fsw, and fsd work properly. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64UF +RVTEST_CODE_BEGIN + + TEST_CASE(2, a0, 0xcafe1000deadbeef, la a1, tdat; flh f1, 4(a1); fsh f1, 20(a1); ld a0, 16(a1)) + TEST_CASE(3, a0, 0x1337d00dabad0001, la a1, tdat; flh f1, 0(a1); fsh f1, 24(a1); ld a0, 24(a1)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +tdat: +.word 0xbf800001 +.word 0x40001000 +.word 0x40400000 +.word 0xc0800000 +.word 0xdeadbeef +.word 0xcafebabe +.word 0xabad1dea +.word 0x1337d00d + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64uzfh/move.S b/tb/qumcu/isa/rv64uzfh/move.S new file mode 100644 index 0000000..20021df --- /dev/null +++ b/tb/qumcu/isa/rv64uzfh/move.S @@ -0,0 +1,58 @@ +# See LICENSE for license details. + +#***************************************************************************** +# move.S +#----------------------------------------------------------------------------- +# +# This test verifies that the fmv.h.x, fmv.x.h, and fsgnj[x|n].d instructions +# and the fcsr work properly. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64UF +RVTEST_CODE_BEGIN + + TEST_CASE(2, a1, 1, csrwi fcsr, 1; li a0, 0x1234; fssr a1, a0) + TEST_CASE(3, a0, 0x34, frsr a0) + TEST_CASE(4, a0, 0x14, frflags a0) + TEST_CASE(5, a0, 0x01, csrrwi a0, frm, 2) + TEST_CASE(6, a0, 0x54, frsr a0) + TEST_CASE(7, a0, 0x14, csrrci a0, fflags, 4) + TEST_CASE(8, a0, 0x50, frsr a0) + +#define TEST_FSGNJS(n, insn, new_sign, rs1_sign, rs2_sign) \ + TEST_CASE(n, a0, 0x1234 | (-(new_sign) << 15), \ + li a1, ((rs1_sign) << 15) | 0x1234; \ + li a2, -(rs2_sign); \ + fmv.h.x f1, a1; \ + fmv.h.x f2, a2; \ + insn f0, f1, f2; \ + fmv.x.h a0, f0) + + TEST_FSGNJS(10, fsgnj.h, 0, 0, 0) + TEST_FSGNJS(11, fsgnj.h, 1, 0, 1) + TEST_FSGNJS(12, fsgnj.h, 0, 1, 0) + TEST_FSGNJS(13, fsgnj.h, 1, 1, 1) + + TEST_FSGNJS(20, fsgnjn.h, 1, 0, 0) + TEST_FSGNJS(21, fsgnjn.h, 0, 0, 1) + TEST_FSGNJS(22, fsgnjn.h, 1, 1, 0) + TEST_FSGNJS(23, fsgnjn.h, 0, 1, 1) + + TEST_FSGNJS(30, fsgnjx.h, 0, 0, 0) + TEST_FSGNJS(31, fsgnjx.h, 1, 0, 1) + TEST_FSGNJS(32, fsgnjx.h, 1, 1, 0) + TEST_FSGNJS(33, fsgnjx.h, 0, 1, 1) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tb/qumcu/isa/rv64uzfh/recoding.S b/tb/qumcu/isa/rv64uzfh/recoding.S new file mode 100644 index 0000000..802be66 --- /dev/null +++ b/tb/qumcu/isa/rv64uzfh/recoding.S @@ -0,0 +1,46 @@ +# See LICENSE for license details. + +#***************************************************************************** +# recoding.S +#----------------------------------------------------------------------------- +# +# Test corner cases of John Hauser's microarchitectural recoding scheme. +# There are twice as many recoded values as IEEE-754 values; some of these +# extras are redundant (e.g. Inf) and others are illegal (subnormals with +# too many bits set). +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64UF +RVTEST_CODE_BEGIN + + # Make sure infinities with different mantissas compare as equal. + flw f0, minf, a0 + flw f1, three, a0 + fmul.s f1, f1, f0 + TEST_CASE( 2, a0, 1, feq.s a0, f0, f1) + TEST_CASE( 3, a0, 1, fle.s a0, f0, f1) + TEST_CASE( 4, a0, 0, flt.s a0, f0, f1) + + # Likewise, but for zeroes. + fcvt.s.w f0, x0 + li a0, 1 + fcvt.s.w f1, a0 + fmul.s f1, f1, f0 + TEST_CASE(5, a0, 1, feq.s a0, f0, f1) + TEST_CASE(6, a0, 1, fle.s a0, f0, f1) + TEST_CASE(7, a0, 0, flt.s a0, f0, f1) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + +minf: .float -Inf +three: .float 3.0 + +RVTEST_DATA_END diff --git a/tb/spi_if/spi_if.sv b/tb/spi_if/spi_if.sv new file mode 100644 index 0000000..d143592 --- /dev/null +++ b/tb/spi_if/spi_if.sv @@ -0,0 +1,17 @@ + + +interface spi_if(input clk,input rstn); + + //timeunit 1ns; + //timeprecision 1ps; + logic sclk; + logic csn; + logic mosi; + logic miso; + + + +endinterface : spi_if + + + diff --git a/tb/spi_tb/spi_if.sv b/tb/spi_tb/spi_if.sv new file mode 100644 index 0000000..b9e2f7a --- /dev/null +++ b/tb/spi_tb/spi_if.sv @@ -0,0 +1,18 @@ + + +interface spi_if(input clk,input rstn); + + //timeunit 1ns; + //timeprecision 1ps; + logic sclk; + logic csn; + logic mosi; + logic miso; + logic [4:0] cfgid; + + + +endinterface : spi_if + + + diff --git a/tb/spi_tb/spi_monitor.sv b/tb/spi_tb/spi_monitor.sv new file mode 100644 index 0000000..a10370c --- /dev/null +++ b/tb/spi_tb/spi_monitor.sv @@ -0,0 +1,68 @@ +class spi_monitor; + + + virtual spi_if wif; + virtual sram_if#(25,32) xif; + integer fid; + + //collect MOSI(exp) & MISO(act) + spi_trans exp_trans; + spi_trans act_trans; + + + function new(); + endfunction + extern task collect(); + extern task do_mon(); + +endclass : spi_monitor + + +task spi_monitor::do_mon(); + + while(1) begin + collect(); + end + +endtask: do_mon + + + + +task spi_monitor::collect(); + bit temp[$]; + int i=0; + + @(negedge wif.csn); + + //capture cmd-words + temp.delete(); + repeat(32) begin + @(posedge wif.sclk or posedge wif.csn); + if(wif.csn) break; + temp.push_back(wif.mosi); + end + + //capture write-data or read-data + while(1) begin + @(posedge wif.sclk or posedge wif.csn); + if(wif.csn) break; + temp.push_back(temp[0] ? wif.miso : wif.mosi); + end + temp.pop_back(); + + if(!temp[0]) begin + exp_trans = new(); + exp_trans.pack(temp); + exp_trans.print(fid); + end + else begin + act_trans = new(); + act_trans.pack(temp); + act_trans.print(fid); + end + + + if(!wif.csn) @(posedge wif.csn); + +endtask diff --git a/tb/spi_tb/spi_scb.sv b/tb/spi_tb/spi_scb.sv new file mode 100644 index 0000000..8772c82 --- /dev/null +++ b/tb/spi_tb/spi_scb.sv @@ -0,0 +1,54 @@ +function bit spi_scoreboard(int pktnum,bit stream[$],bit[31:0] dout[$]); + bit[31:0] data[$]; + bit[31:0] data_temp; + bit[31:0] data_mon[$]; + bit result=1'b1; + int i=0,j=0; + + + //if cmd==1'b0,get the data written to SRAM + if(stream[0]==1'b0) begin + data.delete(); + for(i=1;i= 0 ; + dout <= 2000; +} + + function new(); + endfunction + + function bit[7:0] compare(ram_trans tr); + + bit result= 1'b0; + + if(tr.dout != dout ) result = 1'b1; + +return result; + endfunction + + function print(bit ctrl,integer fid); + if(ctrl[0]) begin + $fwrite(fid,"s_data =%b\n",dout ); + end + endfunction + +endclass : ram_trans diff --git a/tb/sram_tb/ramreg_scb.sv b/tb/sram_tb/ramreg_scb.sv new file mode 100644 index 0000000..eed0daf --- /dev/null +++ b/tb/sram_tb/ramreg_scb.sv @@ -0,0 +1,46 @@ +class ramreg_scoreboard; + integer fid; + + function new(); + endfunction; + + //extern task do_check(); + +extern function bit compare( + bit[31:0] spi_exp[$], + bit[31:0] spi_act[$] + ); + +endclass + +function bit ramreg_scoreboard::compare( + bit[31:0] spi_exp[$], + bit[31:0] spi_act[$] +); + + bit result=1'b1; + int i=0; + + + if(spi_exp.size() != spi_act.size()) begin + result = 1'b0; + $fwrite(fid,"ScoreBoard(ERROR): write & read datanum ARNT'T equal!\n"); + $fwrite(fid,"Exp spi_data size:%0d\n",spi_exp.size()); + $fwrite(fid,"Act spi_data size:%0d\n",spi_act.size()); + end + + else + for(i=0;iirisr) & dff(irisr->isr) +class sys_refmodel; + + virtual sysreg_if vif; + virtual spi_if wif; + virtual sram_if#(25,32) xif; + + //interrupt buffer + bit[31:0] irisr = 32'b0; + bit irisr_clr = 1'b0; + + //poor-quality register model + bit[31:0] rm[17]; + + //members to be sent to scoreboard + int rst_error[5]; + bit[31:0] dout[$]; + sysreg_trans sysout[$]; + + + + function new(); + endfunction + extern task do_imitate(); + extern task RWreg_write (bit[24:0] addr,bit[32:0] din); + extern task ROreg_update (bit[24:0] addr ); + extern task reg_read (bit[24:0] addr ); + extern task rst_check (bit[31:0] rst_time,int i ); + extern task output_trace (bit[24:0] addr ); + +endclass : sys_refmodel + +task sys_refmodel::do_imitate(); + + int i=0,j=0; + rm[ 0] = 32'h41574743; //IDR + rm[ 1] = 32'h55535443; //VIDR + rm[ 2] = 32'h20220831; //DATER + rm[ 3] = 32'h00000001; //VERR + rm[ 4] = 32'h01234567; //TESTR + rm[ 5] = 32'b0; //IMR + rm[ 6] = 32'b0; //ISR + rm[ 7] = 32'd300; //SFRTR + rm[ 8] = 32'd0; //SFRR + rm[ 9] = 32'd0; //CH0RSTR + rm[10] = 32'd0; //CH1RSTR + rm[11] = 32'd0; //CH2RSTR + rm[12] = 32'd0; //CH3RSTR + rm[13] = 32'd0; //DBGCFGR + rm[14] = 32'd0; + rm[15] = 32'd0; + rm[16] = 32'd0; //MISR + + fork + + + while(1) begin: write_reg_RW + + @(negedge xif.wren); + + RWreg_write(xif.addr,xif.din); + + end: write_reg_RW + + + + while(1) begin: update_reg_RO + + ROreg_update(xif.addr); + + end: update_reg_RO + + + while(1) begin: read_reg + + @(negedge xif.rden); + repeat(3) @(posedge xif.clk); + + reg_read(xif.addr); + + end: read_reg + + + + begin: rst_port + + for(i=0;i<5;i++) begin + automatic int rst_i = i; + fork + while(1) begin + @(negedge xif.wren); + if(xif.addr[24: 2]==23'h08+rst_i) + rst_check(rm[7],rst_i); + end + join_none + end + + wait fork; + + end: rst_port + + + while(1) begin: dbg_port + + @(negedge xif.wren); + + output_trace(xif.addr); + + end: dbg_port + + + join + +endtask: do_imitate + + + +task sys_refmodel::RWreg_write(bit[24:0] addr,bit[32:0] din); + + //delay caused by decoder + @(posedge wif.clk); + + case(addr[24: 2]) + 23'h04: rm[ 4] = din; //TESTR + 23'h05: rm[ 5] = din; //IMR + 23'h07: rm[ 7] = din; //SFRTR + 23'h0d: rm[13] = {rm[13][31:6],din[5:0]}; //DBGCFGR + endcase + // $display("addr:%0h",addr); + // $display("rm[%d]:%h",addr[24:2],rm[addr[24: 2]]); + // $display("din:%h",din); + +endtask: RWreg_write + + + +task sys_refmodel::ROreg_update(bit[24:0] addr); + + //irisr->isr + @(posedge wif.clk); + + rm[ 6] = irisr ; + rm[14] = irisr & rm[5] ; + + //intr_status->irisr + if(irisr_clr) + irisr = vif.status; + else + irisr = irisr | vif.status ; + +endtask: ROreg_update + + +task sys_refmodel::reg_read(bit[24:0] addr); + + + case(addr[24: 2]) + 23'h00: dout.push_back(rm[ 0]); //IDR + 23'h01: dout.push_back(rm[ 1]); //VIDR + 23'h02: dout.push_back(rm[ 2]); //DATER + 23'h03: dout.push_back(rm[ 3]); //VERR + 23'h04: dout.push_back(rm[ 4]); //TESTR + 23'h05: dout.push_back(rm[ 5]); //IMm + 23'h06: dout.push_back(rm[ 6]); //ISR + 23'h07: dout.push_back(rm[ 7]); //SFRTR + 23'h08: dout.push_back(rm[ 8]); //SFRR + 23'h09: dout.push_back(rm[ 9]); //CH0RSTR + 23'h0a: dout.push_back(rm[10]); //CH1RSTR + 23'h0b: dout.push_back(rm[11]); //CH2RSTR + 23'h0c: dout.push_back(rm[12]); //CH3RSTR + 23'h0d: dout.push_back(rm[13]); //DBGCFGR + 23'h0e: dout.push_back(0); + 23'h10: begin //MISR + dout.push_back(rm[16]); + irisr_clr = 1'b1; + end + 23'h11: dout.push_back(0); + endcase +// $display("dout:%h",dout[$]); + + @(posedge wif.clk); + irisr_clr = 1'b0; + +endtask: reg_read + + +task sys_refmodel::rst_check(bit[31:0] rst_time,int i); + int cnt=0; + + //delay caused by decoder + @(posedge wif.clk); + + cnt = rst_time; + //$display("%h",addr); + //$display("rst_time:%h",cnt); + while(cnt>0) begin + @(posedge wif.clk); + if(vif.soft_rstn[i]) + break; + cnt--; + end + + @(negedge wif.clk); + if(cnt!=0 | !vif.soft_rstn[i]) begin + rst_error[i]++; + $display("\nScoreBoard(ERROR): rst_time_error\t@%t",$realtime); + case(i) + 0: $display("rst_module:\tSYS"); + 1: $display("rst_module:\tch0"); + 2: $display("rst_module:\tch1"); + 3: $display("rst_module:\tch2"); + 4: $display("rst_module:\tch3"); + endcase + $display("cnt:\t%d",cnt); + $display("soft_rstn:\t%b",vif.soft_rstn[i]); + end + +endtask: rst_check + + + +task sys_refmodel::output_trace(bit[24:0] addr); + if(addr[24:20] == 5'h0); + begin + sysreg_trans tr_temp; + bit irq = |rm[14]; + + //delay caused by decoder + @(posedge wif.clk); + @(negedge wif.clk); + tr_temp = new(); + tr_temp.dbg_enable = rm[13][0:0]; //DBGCFGR + tr_temp.dbg_data_sel = rm[13][1:1]; + tr_temp.dbg_ch_sel = rm[13][3:2]; + tr_temp.irq = irq; + sysout.push_back(tr_temp); + end + // $display("addr:%0h",addr); + + //$display("rm:%h",rm[addr[24: 2]]); + //$display("din:%h",din); + +endtask: output_trace diff --git a/tb/sysreg_tb/sysreg_driver.sv b/tb/sysreg_tb/sysreg_driver.sv new file mode 100644 index 0000000..ee4cd7c --- /dev/null +++ b/tb/sysreg_tb/sysreg_driver.sv @@ -0,0 +1,92 @@ +class sysreg_driver; + + + sysreg_trans tr; + + //interface + virtual sysreg_if vif; + virtual spi_if wif; + + + function new(); + endfunction + extern task do_drive(); + extern task make_intr(); + +endclass : sysreg_driver + +task sysreg_driver::do_drive(); + + fork + + while(1) begin + make_intr(); + end + + join + +endtask + +task sysreg_driver::make_intr(); + int cnt=0; + + vif.status =32'b0; + + cnt = 0; + + + tr = new(); + if(!tr.randomize()) + $fatal(0,"Randomize Failed"); + + + while(cnt<3000) begin + @(posedge wif.clk); + + cnt = cnt + 1; + + case(cnt) + + tr.status_time[28]: vif.status[28] <=1'b1; + tr.status_time[27]: vif.status[27] <=1'b1; + tr.status_time[26]: vif.status[26] <=1'b1; + tr.status_time[25]: vif.status[25] <=1'b1; + tr.status_time[24]: vif.status[24] <=1'b1; + tr.status_time[19]: vif.status[19] <=1'b1; + tr.status_time[18]: vif.status[18] <=1'b1; + tr.status_time[17]: vif.status[17] <=1'b1; + tr.status_time[16]: vif.status[16] <=1'b1; + tr.status_time[11]: vif.status[11] <=1'b1; + tr.status_time[10]: vif.status[10] <=1'b1; + tr.status_time[ 9]: vif.status[ 9] <=1'b1; + tr.status_time[ 8]: vif.status[ 8] <=1'b1; + tr.status_time[ 3]: vif.status[ 3] <=1'b1; + tr.status_time[ 2]: vif.status[ 2] <=1'b1; + tr.status_time[ 1]: vif.status[ 1] <=1'b1; + tr.status_time[ 0]: vif.status[ 0] <=1'b1; + endcase + //$display(vif.status); + + case(cnt-1) + tr.status_time[28]: vif.status[28] <=1'b0; + tr.status_time[27]: vif.status[27] <=1'b0; + tr.status_time[26]: vif.status[26] <=1'b0; + tr.status_time[25]: vif.status[25] <=1'b0; + tr.status_time[24]: vif.status[24] <=1'b0; + tr.status_time[19]: vif.status[19] <=1'b0; + tr.status_time[18]: vif.status[18] <=1'b0; + tr.status_time[17]: vif.status[17] <=1'b0; + tr.status_time[16]: vif.status[16] <=1'b0; + tr.status_time[11]: vif.status[11] <=1'b0; + tr.status_time[10]: vif.status[10] <=1'b0; + tr.status_time[ 9]: vif.status[ 9] <=1'b0; + tr.status_time[ 8]: vif.status[ 8] <=1'b0; + tr.status_time[ 3]: vif.status[ 3] <=1'b0; + tr.status_time[ 2]: vif.status[ 2] <=1'b0; + tr.status_time[ 1]: vif.status[ 1] <=1'b0; + tr.status_time[ 0]: vif.status[ 0] <=1'b0; + endcase + end + +endtask : make_intr + diff --git a/tb/sysreg_tb/sysreg_env.sv b/tb/sysreg_tb/sysreg_env.sv new file mode 100644 index 0000000..93ac20c --- /dev/null +++ b/tb/sysreg_tb/sysreg_env.sv @@ -0,0 +1,107 @@ +class sysreg_env; + + + static int pktnum; + + //Interface: + virtual sysreg_if vif; + virtual spi_if wif; + virtual sram_if#(25,32) xif; + + //Component: + spi_driver w_driver; + sysreg_driver s_driver; + spi_monitor w_monitor; + sys_refmodel s_model; + sysreg_monitor s_monitor; + sysreg_scoreboard s_scb; + + + function new(); + endfunction; + + extern function build(); + + extern task run(); + +endclass + +function sysreg_env::build(); + + w_driver = new(); + if(!w_driver.randomize() with { + error_time < 0; + }) + $fatal(0,"Randomize Failed"); + w_driver.pktnum = pktnum; + w_driver.vif = wif; + w_driver.autarchy = 1'b1; + w_driver.half_sclk = 4; + + w_monitor = new(); + w_monitor.wif = wif; + w_monitor.xif = xif; + + s_driver = new(); + s_driver.vif = vif; + s_driver.wif = wif; + + s_monitor = new(); + s_monitor.vif = vif; + s_monitor.xif = xif; + + s_model = new(); + s_model.vif = vif; + s_model.wif = wif; + s_model.xif = xif; + + s_scb = new(); + +endfunction + + +task sysreg_env::run(); + int error=0; + + fork + + w_driver.do_drive(); + + s_driver.do_drive(); + + w_monitor.do_mon(); + + s_monitor.do_mon(); + + s_model.do_imitate(); + + + while(1) begin + repeat(2) @(posedge wif.csn); + @(posedge wif.clk); + s_model.dout.pop_back(); + if(s_scb.compare( + s_model.dout , + w_monitor.act_trans.data , + s_model.sysout , + s_monitor.act_trans + )) + error++; + s_model.dout.delete(); + s_model.sysout.delete(); + s_monitor.act_trans.delete(); + end + + + join + + $display("SCOREBOARD:"); + $display("\tError_isr:\t%0d",error); + $display("\tError_sysrst:\t%0d",s_model.rst_error[0]); + $display("\tError_ch0rst:\t%0d",s_model.rst_error[1]); + $display("\tError_ch1rst:\t%0d",s_model.rst_error[2]); + $display("\tError_ch2rst:\t%0d",s_model.rst_error[3]); + $display("\tError_ch3rst:\t%0d",s_model.rst_error[4]); + +endtask + diff --git a/tb/sysreg_tb/sysreg_if.sv b/tb/sysreg_tb/sysreg_if.sv new file mode 100644 index 0000000..96681e4 --- /dev/null +++ b/tb/sysreg_tb/sysreg_if.sv @@ -0,0 +1,18 @@ + + +interface sysreg_if(input clk,input rstn); + +//output port + logic dbg_enable ; + logic dbg_data_sel; + logic [1 :0] dbg_ch_sel ;//[3:0] + logic [32 :0] status ; + logic [ 4 :0] soft_rstn ; + logic irq ; + + + +endinterface : sysreg_if + + + diff --git a/tb/sysreg_tb/sysreg_monitor.sv b/tb/sysreg_tb/sysreg_monitor.sv new file mode 100644 index 0000000..e5904e4 --- /dev/null +++ b/tb/sysreg_tb/sysreg_monitor.sv @@ -0,0 +1,45 @@ +class sysreg_monitor; + + + virtual sysreg_if vif; + virtual sram_if#(25,32) xif; + + //collect + sysreg_trans act_trans[$]; + + + function new(); + endfunction + extern task collect(); + extern task do_mon(); + +endclass : sysreg_monitor + + +task sysreg_monitor::do_mon(); + + while(1) begin + @(negedge xif.wren); + collect(); + end + +endtask: do_mon + + + + +task sysreg_monitor::collect(); + sysreg_trans tr_temp; + + @(posedge xif.clk); + @(negedge xif.clk); + + tr_temp = new(); + tr_temp.dbg_enable = vif.dbg_enable ; + tr_temp.dbg_data_sel = vif.dbg_data_sel ; + tr_temp.dbg_ch_sel = vif.dbg_ch_sel ; + tr_temp.irq = vif.irq ; + + act_trans.push_back(tr_temp); + +endtask: collect diff --git a/tb/sysreg_tb/sysreg_scb.sv b/tb/sysreg_tb/sysreg_scb.sv new file mode 100644 index 0000000..cfe84ad --- /dev/null +++ b/tb/sysreg_tb/sysreg_scb.sv @@ -0,0 +1,94 @@ +class sysreg_scoreboard; + + //Vars in intr_check + int isr_error=0; + integer fid; + + function new(); + endfunction; + + //extern task do_check(); + + extern function bit compare( + bit[31:0] spi_exp[$], + bit[31:0] spi_act[$], + sysreg_trans sys_exp[$], + sysreg_trans sys_act[$] + ); + +endclass + +function bit sysreg_scoreboard::compare( + bit[31:0] spi_exp[$], + bit[31:0] spi_act[$], + sysreg_trans sys_exp[$], + sysreg_trans sys_act[$] +); + + bit result=1'b1; + int i=0; + +//$display(dout); + + if(spi_exp.size() != spi_act.size()) begin + result = 1'b0; + //$display("ScoreBoard(ERROR): write & read datanum ARNT'T equal!"); + //$display("Exp spi_data size:%0d",spi_exp.size()); + //$display("Act spi_data size:%0d",spi_act.size()); + $fwrite(fid,"ScoreBoard(ERROR): write & read datanum ARNT'T equal!\t@%t\n",$realtime); + $fwrite(fid,"Exp spi_data size:%0d\n",spi_exp.size()); + $fwrite(fid,"Act spi_data size:%0d\n",spi_act.size()); + end + + else if(sys_exp.size() != sys_act.size()) begin + result = 1'b0; + //$display("ScoreBoard(ERROR): regmdl & read datanum ARNT'T equal!"); + //$display("Exp sys_trs size:%0d",sys_exp.size()); + //$display("Act sys_trs size:%0d",sys_act.size()); + $fwrite(fid,"ScoreBoard(ERROR): regmdl & read datanum ARNT'T equal!\t@%t\n",$realtime); + $fwrite(fid,"Exp sys_trs size:%0d\n",sys_exp.size()); + $fwrite(fid,"Act sys_trs size:%0d\n",sys_act.size()); + end + + + else + for(i=0;i 0 ; + status_time[ 1] > 0 ; + status_time[ 2] > 0 ; + status_time[ 3] > 0 ; + status_time[ 4] > 0 ; + status_time[ 5] > 0 ; + status_time[ 6] > 0 ; + status_time[ 7] > 0 ; + status_time[ 8] > 0 ; + status_time[ 9] > 0 ; + status_time[10] > 0 ; + status_time[11] > 0 ; + status_time[12] > 0 ; + status_time[13] > 0 ; + status_time[14] > 0 ; + status_time[15] > 0 ; + status_time[16] > 0 ; + status_time[17] > 0 ; + status_time[18] > 0 ; + status_time[19] > 0 ; + status_time[20] > 0 ; + status_time[21] > 0 ; + status_time[22] > 0 ; + status_time[23] > 0 ; + status_time[24] > 0 ; + status_time[25] > 0 ; + status_time[26] > 0 ; + status_time[27] > 0 ; + status_time[28] > 0 ; + status_time[29] > 0 ; + status_time[30] > 0 ; + status_time[31] > 0 ; +} + + function new(); + + endfunction + + function bit[3:0] compare(sysreg_trans tr); + bit[3:0] result=4'b0; + if(tr.dbg_enable != dbg_enable ) result[0]=1'b1; + if(tr.dbg_data_sel != dbg_data_sel) result[1]=1'b1; + if(tr.dbg_ch_sel != dbg_ch_sel ) result[2]=1'b1; + if(tr.irq != irq ) result[3]=1'b1; + return result; + endfunction + + function print(bit[3:0] ctrl,integer fid); + if(ctrl[0]) $fwrite(fid,"dbg_enable:\t%b\n",dbg_enable); + if(ctrl[1]) $fwrite(fid,"dbg_data_sel:\t%b\n",dbg_data_sel); + if(ctrl[2]) $fwrite(fid,"dbg_ch_sel:\t%b\n",dbg_ch_sel); + if(ctrl[3]) $fwrite(fid,"irq:\t\t%b\n",irq); + endfunction + +endclass : sysreg_trans + + + + + + + + + + + + diff --git a/tb/tb.sv b/tb/tb.sv new file mode 100644 index 0000000..ef3f638 --- /dev/null +++ b/tb/tb.sv @@ -0,0 +1,783 @@ +`include "../define/chip_define.v" + +module TB(); + + initial begin + $fsdbDumpfile("TB1.fsdb"); + $fsdbDumpvars(0, TB); + $fsdbDumpMDA(); + end + + logic clk; + logic rstn; + logic clk_rstn; + logic qbmcu_i_start; + + spi_if spi_if(clk,rstn); + sysreg_if sys_if(clk,rstn); + mcureg_if mcu_if(clk,rstn); + awgreg_if awg_if(clk,rstn); + pllreg_if pll_if(clk,rstn); + dacreg_if dac_if(clk,rstn); + + initial begin + #0; + rstn = 1'b0; + clk_rstn = 1'b0; + clk = 1'b0; + qbmcu_i_start = 1'b0; + #10; + rstn = 1'b1; + clk_rstn = 1'b1; + end + + always #0.5 clk = ~clk; + + reg [31:0] cnt; + always@(posedge clk or negedge rstn) + if(!rstn) + cnt <= 32'd0; + else + cnt <= cnt + 32'd1; + + initial begin + wait(cnt[31]==1'b1) + $finish(0); + end + + + wire miso; // Spi Miso + wire miso_oen; // Spi Miso output enable + + + assign spi_if.miso = (!U_xyz_chip_top.U_iopad.oen) ? miso : 1'bz; + + +sram_if#(25,32) mst(clk); + +assign mst.din = U_xyz_chip_top.U_digital_top.U_spi_slave.sys_wrdata; +assign mst.wren = U_xyz_chip_top.U_digital_top.U_spi_slave.sys_wren ; +assign mst.addr = U_xyz_chip_top.U_digital_top.U_spi_slave.sys_rwaddr; +assign mst.rden = U_xyz_chip_top.U_digital_top.U_spi_slave.sys_rden ; +assign mst.dout = U_xyz_chip_top.U_digital_top.U_spi_slave.sys_rddata; + +//mcu_regfile U2_mcu_regfile ( +// .clk ( clk ) +// ,.rst_n ( rst_n ) +// ,.rwaddr ( U_xyz_chip_top.U_digital_top.U_spi_bus_decoder.slv[7].addr[14:0]) +// ,.wrdata ( U_xyz_chip_top.U_digital_top.U_spi_bus_decoder.slv[7].din ) +// ,.wren ( U_xyz_chip_top.U_digital_top.U_spi_bus_decoder.slv[7].wren ) +// ,.wrmask ( U_xyz_chip_top.U_digital_top.U0_channel_top.preg_o_wrmask ) +// ,.rden ( U_xyz_chip_top.U_digital_top.U_spi_bus_decoder.slv[7].rden ) +// ,.rddata ( U_xyz_chip_top.U_digital_top.U_spi_bus_decoder.slv[7].slave.dout ) +// ,.fb_st_info ( U_xyz_chip_top.U_digital_top.U0_channel_top.fb_st_in ) +// ,.run_time ( U_xyz_chip_top.U_digital_top.U0_channel_top.run_time ) +// ,.instr_num ( U_xyz_chip_top.U_digital_top.U0_channel_top.instr_num ) +// ,.mcu_param ( U_xyz_chip_top.U_digital_top.U0_channel_top.mcu_param ) +// ,.mcu_result ( U_xyz_chip_top.U_digital_top.U0_channel_top.mcu_result ) +// ,.mcu_cwfr ( U_xyz_chip_top.U_digital_top.U0_channel_top.mcu_cwfr ) +// ,.mcu_gapr ( U_xyz_chip_top.U_digital_top.U0_channel_top.mcu_gapr ) +// ,.mcu_ampr ( U_xyz_chip_top.U_digital_top.U0_channel_top.mcu_ampr ) +// ,.mcu_baisr ( U_xyz_chip_top.U_digital_top.U0_channel_top.mcu_baisr ) +// ,.mcu_nco_pha_clr ( U_xyz_chip_top.U_digital_top.U0_channel_top.mcu_nco_pha_clr ) +// ,.mcu_rz_pha ( U_xyz_chip_top.U_digital_top.U0_channel_top.mcu_rz_pha ) +//); + +`define CH0_FB 2'b10 + + //////////////////////////////////////////////////////////////////////////////////////// +//DUT +//////////////////////////////////////////////////////////////////////////////////////// +wire async_rstn = rstn; +wire por_rstn = 1'b1; +logic sync_out ; +logic [1 :0] ch0_feedback = `CH0_FB; +wire [4 :0] cfgid = 5'b00000; +logic irq; + +//------------------------------PLL cfg pin---------------------------------------------------- +logic ref_sel ; // Clock source selection for a frequency divider; + // 1'b0:External clock source + // 1'b1:internal phase-locked loop clock source +logic ref_en ; // Input reference clock enable + // 1'b0:enable,1'b1:disable +logic ref_s2d_en ; // Referenced clock differential to single-ended conversion enable + // 1'b0:enable,1'b1:disable +logic [6 :0] p_cnt ; // P counter +logic pfd_delay ; // PFD Dead Zone +logic pfd_dff_Set ; // Setting the PFD register,active high +logic pfd_dff_4and ; // PFD output polarity +logic [3 :0] spd_div ; // SPD Frequency Divider +logic spd_pulse_width ; // Pulse Width of SPD +logic spd_pulse_sw ; // Pulse sw of SPD +logic cpc_sel ; // current source selection +logic [1 :0] swcp_i ; // PTAT current switch +logic [3 :0] sw_ptat_r ; // PTAT current adjustment +logic [1 :0] sw_fll_cpi ; // Phase-locked loop charge pump current +logic sw_fll_delay ; // PLL Dead Zone +logic pfd_sel ; // PFD Loop selection +logic spd_sel ; // SPD Loop selection +logic fll_sel ; // FLL Loop selection +logic vco_tc ; // VCO temperature compensation +logic vco_tcr ; // VCO temperature compensation resistor +logic vco_gain_adj ; // VCO gain adjustment +logic vco_gain_adj_r ; // VCO gain adjustment resistor +logic [2 :0] vco_cur_adj ; // VCO current adjustment +logic vco_buff_en ; // VCO buff enable,active high +logic vco_en ; // VCO enable,active high +logic [2 :0] pll_dpwr_adj ; // PLL frequency division output power adjustment +logic [6 :0] vco_fb_adj ; // VCO frequency band adjustment +logic afc_en ; // AFC enable +logic afc_shutdown ; // AFC module shutdown signal +logic [0 :0] afc_det_speed ; // AFC detection speed +logic [0 :0] flag_out_sel ; // Read and choose the signs +logic afc_reset ; // AFC reset +logic [10 :0] afc_cnt ; // AFC frequency band adjustment function counter + // counting time adjustment +logic [10 :0] afc_ld_cnt ; // Adjust the counting time of the AFC lock detection + // feature counter +logic [3 :0] afc_pres ; // Adjusting the resolution of the AFC comparator +logic [14 :0] afc_ld_tcc ; // AFC Lock Detection Function Target Cycle Count +logic [14 :0] afc_fb_tcc ; // Target number of cycles for AFC frequency band + // adjustment function +logic sync_clr ; // PLL div sync clr,low active +logic pll_rstn ; // PLL reset,active low +logic [0 :0] div_rstn_sel ; // div rstn select, 1'b0: ext clear, 1'b1:inter pll lock +logic [1 :0] test_clk_sel ; // test clk select, 2'b00:DIV1 clk, 2'b01:DIV2 clk, 2'b10:DIV4 clk, 2'b11:DIV8 clk +logic [0 :0] test_clk_oen ; // test clk output enable, 1'b0:disenable, 1'b1:enable +logic [7 :0] dig_clk_sel ; // digital main clk select, one hot code,bit[0]-->0 degree phase,bit[1]-->45 degree phase.....bit[7]-->315degree phae +logic clkrx_pdn ; +logic pll_lock = 1'b1 ; // PLL LOCK + +//DAC cfg +logic [2 :0] ch0_dac_addr ; +logic [2 :0] ch0_dac_dw ; +logic [8 :0] ch0_dac_ref ; +logic [16 :0] ch0_dac_Prbs_rst0 ; +logic [16 :0] ch0_dac_Prbs_set0 ; +logic [16 :0] ch0_dac_Prbs_rst1 ; +logic [16 :0] ch0_dac_Prbs_set1 ; +logic ch0_dac_Cal_sig ; +logic ch0_dac_Cal_rstn ; +logic ch1_dac_Cal_div_rstn ; +logic ch0_dac_Cal_end = 1'b1; + +//DSP output +//`ifdef CHANNEL_XY_ON +logic [15 :0] ch0_xy_dsp_dout0 ; +logic [15 :0] ch0_xy_dsp_dout1 ; +logic [15 :0] ch0_xy_dsp_dout2 ; +logic [15 :0] ch0_xy_dsp_dout3 ; +logic [15 :0] ch0_xy_dsp_dout4 ; +logic [15 :0] ch0_xy_dsp_dout5 ; +logic [15 :0] ch0_xy_dsp_dout6 ; +logic [15 :0] ch0_xy_dsp_dout7 ; +logic [15 :0] ch0_xy_dsp_dout8 ; +logic [15 :0] ch0_xy_dsp_dout9 ; +logic [15 :0] ch0_xy_dsp_dout10; +logic [15 :0] ch0_xy_dsp_dout11; +logic [15 :0] ch0_xy_dsp_dout12; +logic [15 :0] ch0_xy_dsp_dout13; +logic [15 :0] ch0_xy_dsp_dout14; +logic [15 :0] ch0_xy_dsp_dout15; +//`endif +//`ifdef CHANNEL_Z_ON +logic [15 :0] ch0_z_dsp_dout0 ; +logic [15 :0] ch0_z_dsp_dout1 ; +logic [15 :0] ch0_z_dsp_dout2 ; +logic [15 :0] ch0_z_dsp_dout3 ; +//`endif + `ifdef CHANNEL_XY_ON +logic [14:0] ch0_xy_A_DEM_MSB_OUT0; +logic [14:0] ch0_xy_A_DEM_MSB_OUT1; +logic [14:0] ch0_xy_A_DEM_MSB_OUT2; +logic [14:0] ch0_xy_A_DEM_MSB_OUT3; +logic [14:0] ch0_xy_A_DEM_MSB_OUT4; +logic [14:0] ch0_xy_A_DEM_MSB_OUT5; +logic [14:0] ch0_xy_A_DEM_MSB_OUT6; +logic [14:0] ch0_xy_A_DEM_MSB_OUT7; +logic [14:0] ch0_xy_B_DEM_MSB_OUT0; +logic [14:0] ch0_xy_B_DEM_MSB_OUT1; +logic [14:0] ch0_xy_B_DEM_MSB_OUT2; +logic [14:0] ch0_xy_B_DEM_MSB_OUT3; +logic [14:0] ch0_xy_B_DEM_MSB_OUT4; +logic [14:0] ch0_xy_B_DEM_MSB_OUT5; +logic [14:0] ch0_xy_B_DEM_MSB_OUT6; +logic [14:0] ch0_xy_B_DEM_MSB_OUT7; +logic [6 :0] ch0_xy_A_DEM_ISB_OUT0; +logic [6 :0] ch0_xy_A_DEM_ISB_OUT1; +logic [6 :0] ch0_xy_A_DEM_ISB_OUT2; +logic [6 :0] ch0_xy_A_DEM_ISB_OUT3; +logic [6 :0] ch0_xy_A_DEM_ISB_OUT4; +logic [6 :0] ch0_xy_A_DEM_ISB_OUT5; +logic [6 :0] ch0_xy_A_DEM_ISB_OUT6; +logic [6 :0] ch0_xy_A_DEM_ISB_OUT7; +logic [6 :0] ch0_xy_B_DEM_ISB_OUT0; +logic [6 :0] ch0_xy_B_DEM_ISB_OUT1; +logic [6 :0] ch0_xy_B_DEM_ISB_OUT2; +logic [6 :0] ch0_xy_B_DEM_ISB_OUT3; +logic [6 :0] ch0_xy_B_DEM_ISB_OUT4; +logic [6 :0] ch0_xy_B_DEM_ISB_OUT5; +logic [6 :0] ch0_xy_B_DEM_ISB_OUT6; +logic [6 :0] ch0_xy_B_DEM_ISB_OUT7; +logic [8 :0] ch0_xy_A_DEM_LSB_OUT0; +logic [8 :0] ch0_xy_A_DEM_LSB_OUT1; +logic [8 :0] ch0_xy_A_DEM_LSB_OUT2; +logic [8 :0] ch0_xy_A_DEM_LSB_OUT3; +logic [8 :0] ch0_xy_A_DEM_LSB_OUT4; +logic [8 :0] ch0_xy_A_DEM_LSB_OUT5; +logic [8 :0] ch0_xy_A_DEM_LSB_OUT6; +logic [8 :0] ch0_xy_A_DEM_LSB_OUT7; +logic [8 :0] ch0_xy_B_DEM_LSB_OUT0; +logic [8 :0] ch0_xy_B_DEM_LSB_OUT1; +logic [8 :0] ch0_xy_B_DEM_LSB_OUT2; +logic [8 :0] ch0_xy_B_DEM_LSB_OUT3; +logic [8 :0] ch0_xy_B_DEM_LSB_OUT4; +logic [8 :0] ch0_xy_B_DEM_LSB_OUT5; +logic [8 :0] ch0_xy_B_DEM_LSB_OUT6; +logic [8 :0] ch0_xy_B_DEM_LSB_OUT7; +`endif +`ifdef CHANNEL_Z_ON +logic [14 :0] ch0_z_DEM_MSB_OUT0; +logic [14 :0] ch0_z_DEM_MSB_OUT1; +logic [14 :0] ch0_z_DEM_MSB_OUT2; +logic [14 :0] ch0_z_DEM_MSB_OUT3; +logic [6 :0] ch0_z_DEM_ISB_OUT0; +logic [6 :0] ch0_z_DEM_ISB_OUT1; +logic [6 :0] ch0_z_DEM_ISB_OUT2; +logic [6 :0] ch0_z_DEM_ISB_OUT3; +logic [8 :0] ch0_z_DEM_LSB_OUT0; +logic [8 :0] ch0_z_DEM_LSB_OUT1; +logic [8 :0] ch0_z_DEM_LSB_OUT2; +logic [8 :0] ch0_z_DEM_LSB_OUT3; +`endif + + + + + + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +xyz_chip_top U_xyz_chip_top ( + .clk ( clk ) + ,.por_rstn ( por_rstn ) + ,.PI_async_rstn ( async_rstn ) + ,.PI_sync_in ( qbmcu_i_start ) + ,.PO_sync_out ( sync_out ) + ,.PI_ch0_feedback ( ch0_feedback ) + `ifdef CHANNEL_IS_FOUR + ,.PI_ch1_feedback ( ch1_feedback ) + ,.PI_ch2_feedback ( ch2_feedback ) + ,.PI_ch3_feedback ( ch3_feedback ) + `endif + ,.PI_cfgid ( spi_if.cfgid ) + ,.PI_sclk ( spi_if.sclk ) + ,.PI_csn ( spi_if.csn ) + ,.PI_mosi ( spi_if.mosi ) + ,.PO_miso ( miso ) + ,.PO_irq ( irq ) + ,.ref_sel ( ref_sel ) + ,.ref_en ( ref_en ) + ,.ref_s2d_en ( ref_s2d_en ) + ,.p_cnt ( p_cnt ) + ,.pfd_delay ( pfd_delay ) + ,.pfd_dff_Set ( pfd_dff_Set ) + ,.pfd_dff_4and ( pfd_dff_4and ) + ,.spd_div ( spd_div ) + ,.spd_pulse_width ( spd_pulse_width ) + ,.spd_pulse_sw ( spd_pulse_sw ) + ,.cpc_sel ( cpc_sel ) + ,.swcp_i ( swcp_i ) + ,.sw_ptat_r ( sw_ptat_r ) + ,.sw_fll_cpi ( sw_fll_cpi ) + ,.sw_fll_delay ( sw_fll_delay ) + ,.pfd_sel ( pfd_sel ) + ,.spd_sel ( spd_sel ) + ,.fll_sel ( fll_sel ) + ,.vco_tc ( vco_tc ) + ,.vco_tcr ( vco_tcr ) + ,.vco_gain_adj ( vco_gain_adj ) + ,.vco_gain_adj_r ( vco_gain_adj_r ) + ,.vco_cur_adj ( vco_cur_adj ) + ,.vco_buff_en ( vco_buff_en ) + ,.vco_en ( vco_en ) + ,.pll_dpwr_adj ( pll_dpwr_adj ) + ,.vco_fb_adj ( vco_fb_adj ) + ,.afc_en ( afc_en ) + ,.afc_shutdown ( afc_shutdown ) + ,.afc_det_speed ( afc_det_speed ) + ,.flag_out_sel ( flag_out_sel ) + ,.afc_reset ( afc_reset ) + ,.afc_cnt ( afc_cnt ) + ,.afc_ld_cnt ( afc_ld_cnt ) + ,.afc_pres ( afc_pres ) + ,.afc_ld_tcc ( afc_ld_tcc ) + ,.afc_fb_tcc ( afc_fb_tcc ) + ,.sync_clr ( sync_clr ) + ,.pll_rstn ( pll_rstn ) + ,.div_rstn_sel ( div_rstn_sel ) + ,.test_clk_sel ( test_clk_sel ) + ,.test_clk_oen ( test_clk_oen ) + ,.dig_clk_sel ( dig_clk_sel ) + ,.clkrx_pdn ( clkrx_pdn ) + ,.pll_lock ( pll_lock ) + ,.ch0_dac_addr ( ch0_dac_addr ) + ,.ch0_dac_dw ( ch0_dac_dw ) + ,.ch0_dac_ref ( ch0_dac_ref ) + ,.ch0_dac_Prbs_rst0 ( ch0_dac_Prbs_rst0 ) + ,.ch0_dac_Prbs_set0 ( ch0_dac_Prbs_set0 ) + ,.ch0_dac_Prbs_rst1 ( ch0_dac_Prbs_rst1 ) + ,.ch0_dac_Prbs_set1 ( ch0_dac_Prbs_set1 ) + ,.ch0_dac_Cal_sig ( ch0_dac_Cal_sig ) + ,.ch0_dac_Cal_rstn ( ch0_dac_Cal_rstn ) + ,.ch0_dac_Cal_div_rstn ( ch0_dac_Cal_div_rstn ) + ,.ch0_dac_Cal_end ( ch0_dac_Cal_end ) + `ifdef CHANNEL_IS_FOUR + ,.ch1_dac_addr ( ch1_dac_addr ) + ,.ch1_dac_dw ( ch1_dac_dw ) + ,.ch1_dac_ref ( ch1_dac_ref ) + ,.ch1_dac_Prbs_rst0 ( ch1_dac_Prbs_rst0 ) + ,.ch1_dac_Prbs_set0 ( ch1_dac_Prbs_set0 ) + ,.ch1_dac_Prbs_rst1 ( ch1_dac_Prbs_rst1 ) + ,.ch1_dac_Prbs_set1 ( ch1_dac_Prbs_set1 ) + ,.ch1_dac_Cal_sig ( ch1_dac_Cal_sig ) + ,.ch1_dac_Cal_rstn ( ch1_dac_Cal_rstn ) + ,.ch1_dac_Cal_div_rstn ( ch1_dac_Cal_div_rstn ) + ,.ch1_dac_Cal_end ( ch1_dac_Cal_end ) + ,.ch2_dac_addr ( ch2_dac_addr ) + ,.ch2_dac_dw ( ch2_dac_dw ) + ,.ch2_dac_ref ( ch2_dac_ref ) + ,.ch2_dac_Prbs_rst0 ( ch2_dac_Prbs_rst0 ) + ,.ch2_dac_Prbs_set0 ( ch2_dac_Prbs_set0 ) + ,.ch2_dac_Prbs_rst1 ( ch2_dac_Prbs_rst1 ) + ,.ch2_dac_Prbs_set1 ( ch2_dac_Prbs_set1 ) + ,.ch2_dac_Cal_sig ( ch2_dac_Cal_sig ) + ,.ch2_dac_Cal_rstn ( ch2_dac_Cal_rstn ) + ,.ch2_dac_Cal_div_rstn ( ch2_dac_Cal_div_rstn ) + ,.ch2_dac_Cal_end ( ch2_dac_Cal_end ) + ,.ch3_dac_dw ( ch3_dac_dw ) + ,.ch3_dac_ref ( ch3_dac_ref ) + ,.ch3_dac_Prbs_rst0 ( ch3_dac_Prbs_rst0 ) + ,.ch3_dac_Prbs_set0 ( ch3_dac_Prbs_set0 ) + ,.ch3_dac_Prbs_rst1 ( ch3_dac_Prbs_rst1 ) + ,.ch3_dac_Prbs_set1 ( ch3_dac_Prbs_set1 ) + ,.ch3_dac_Cal_sig ( ch3_dac_Cal_sig ) + ,.ch3_dac_Cal_rstn ( ch3_dac_Cal_rstn ) + ,.ch0_dac_Cal_div_rstn ( ch3_dac_Cal_div_rstn ) + ,.ch3_dac_Cal_end ( ch3_dac_Cal_end ) + `endif + //------------------------------Ch0 DSP data out---------------------------------------------------- + `ifdef CHANNEL_XY_ON + ,.ch0_xy_A_DEM_MSB_OUT0 ( ch0_xy_A_DEM_MSB_OUT0 ) + ,.ch0_xy_A_DEM_MSB_OUT1 ( ch0_xy_A_DEM_MSB_OUT1 ) + ,.ch0_xy_A_DEM_MSB_OUT2 ( ch0_xy_A_DEM_MSB_OUT2 ) + ,.ch0_xy_A_DEM_MSB_OUT3 ( ch0_xy_A_DEM_MSB_OUT3 ) + ,.ch0_xy_A_DEM_MSB_OUT4 ( ch0_xy_A_DEM_MSB_OUT4 ) + ,.ch0_xy_A_DEM_MSB_OUT5 ( ch0_xy_A_DEM_MSB_OUT5 ) + ,.ch0_xy_A_DEM_MSB_OUT6 ( ch0_xy_A_DEM_MSB_OUT6 ) + ,.ch0_xy_A_DEM_MSB_OUT7 ( ch0_xy_A_DEM_MSB_OUT7 ) + ,.ch0_xy_B_DEM_MSB_OUT0 ( ch0_xy_B_DEM_MSB_OUT0 ) + ,.ch0_xy_B_DEM_MSB_OUT1 ( ch0_xy_B_DEM_MSB_OUT1 ) + ,.ch0_xy_B_DEM_MSB_OUT2 ( ch0_xy_B_DEM_MSB_OUT2 ) + ,.ch0_xy_B_DEM_MSB_OUT3 ( ch0_xy_B_DEM_MSB_OUT3 ) + ,.ch0_xy_B_DEM_MSB_OUT4 ( ch0_xy_B_DEM_MSB_OUT4 ) + ,.ch0_xy_B_DEM_MSB_OUT5 ( ch0_xy_B_DEM_MSB_OUT5 ) + ,.ch0_xy_B_DEM_MSB_OUT6 ( ch0_xy_B_DEM_MSB_OUT6 ) + ,.ch0_xy_B_DEM_MSB_OUT7 ( ch0_xy_B_DEM_MSB_OUT7 ) + ,.ch0_xy_A_DEM_ISB_OUT0 ( ch0_xy_A_DEM_ISB_OUT0 ) + ,.ch0_xy_A_DEM_ISB_OUT1 ( ch0_xy_A_DEM_ISB_OUT1 ) + ,.ch0_xy_A_DEM_ISB_OUT2 ( ch0_xy_A_DEM_ISB_OUT2 ) + ,.ch0_xy_A_DEM_ISB_OUT3 ( ch0_xy_A_DEM_ISB_OUT3 ) + ,.ch0_xy_A_DEM_ISB_OUT4 ( ch0_xy_A_DEM_ISB_OUT4 ) + ,.ch0_xy_A_DEM_ISB_OUT5 ( ch0_xy_A_DEM_ISB_OUT5 ) + ,.ch0_xy_A_DEM_ISB_OUT6 ( ch0_xy_A_DEM_ISB_OUT6 ) + ,.ch0_xy_A_DEM_ISB_OUT7 ( ch0_xy_A_DEM_ISB_OUT7 ) + ,.ch0_xy_B_DEM_ISB_OUT0 ( ch0_xy_B_DEM_ISB_OUT0 ) + ,.ch0_xy_B_DEM_ISB_OUT1 ( ch0_xy_B_DEM_ISB_OUT1 ) + ,.ch0_xy_B_DEM_ISB_OUT2 ( ch0_xy_B_DEM_ISB_OUT2 ) + ,.ch0_xy_B_DEM_ISB_OUT3 ( ch0_xy_B_DEM_ISB_OUT3 ) + ,.ch0_xy_B_DEM_ISB_OUT4 ( ch0_xy_B_DEM_ISB_OUT4 ) + ,.ch0_xy_B_DEM_ISB_OUT5 ( ch0_xy_B_DEM_ISB_OUT5 ) + ,.ch0_xy_B_DEM_ISB_OUT6 ( ch0_xy_B_DEM_ISB_OUT6 ) + ,.ch0_xy_B_DEM_ISB_OUT7 ( ch0_xy_B_DEM_ISB_OUT7 ) + ,.ch0_xy_A_DEM_LSB_OUT0 ( ch0_xy_A_DEM_LSB_OUT0 ) + ,.ch0_xy_A_DEM_LSB_OUT1 ( ch0_xy_A_DEM_LSB_OUT1 ) + ,.ch0_xy_A_DEM_LSB_OUT2 ( ch0_xy_A_DEM_LSB_OUT2 ) + ,.ch0_xy_A_DEM_LSB_OUT3 ( ch0_xy_A_DEM_LSB_OUT3 ) + ,.ch0_xy_A_DEM_LSB_OUT4 ( ch0_xy_A_DEM_LSB_OUT4 ) + ,.ch0_xy_A_DEM_LSB_OUT5 ( ch0_xy_A_DEM_LSB_OUT5 ) + ,.ch0_xy_A_DEM_LSB_OUT6 ( ch0_xy_A_DEM_LSB_OUT6 ) + ,.ch0_xy_A_DEM_LSB_OUT7 ( ch0_xy_A_DEM_LSB_OUT7 ) + ,.ch0_xy_B_DEM_LSB_OUT0 ( ch0_xy_B_DEM_LSB_OUT0 ) + ,.ch0_xy_B_DEM_LSB_OUT1 ( ch0_xy_B_DEM_LSB_OUT1 ) + ,.ch0_xy_B_DEM_LSB_OUT2 ( ch0_xy_B_DEM_LSB_OUT2 ) + ,.ch0_xy_B_DEM_LSB_OUT3 ( ch0_xy_B_DEM_LSB_OUT3 ) + ,.ch0_xy_B_DEM_LSB_OUT4 ( ch0_xy_B_DEM_LSB_OUT4 ) + ,.ch0_xy_B_DEM_LSB_OUT5 ( ch0_xy_B_DEM_LSB_OUT5 ) + ,.ch0_xy_B_DEM_LSB_OUT6 ( ch0_xy_B_DEM_LSB_OUT6 ) + ,.ch0_xy_B_DEM_LSB_OUT7 ( ch0_xy_B_DEM_LSB_OUT7 ) + `endif + `ifdef CHANNEL_Z_ON + ,.ch0_z_DEM_MSB_OUT0 ( ch0_z_DEM_MSB_OUT0 ) + ,.ch0_z_DEM_MSB_OUT1 ( ch0_z_DEM_MSB_OUT1 ) + ,.ch0_z_DEM_MSB_OUT2 ( ch0_z_DEM_MSB_OUT2 ) + ,.ch0_z_DEM_MSB_OUT3 ( ch0_z_DEM_MSB_OUT3 ) + ,.ch0_z_DEM_ISB_OUT0 ( ch0_z_DEM_ISB_OUT0 ) + ,.ch0_z_DEM_ISB_OUT1 ( ch0_z_DEM_ISB_OUT1 ) + ,.ch0_z_DEM_ISB_OUT2 ( ch0_z_DEM_ISB_OUT2 ) + ,.ch0_z_DEM_ISB_OUT3 ( ch0_z_DEM_ISB_OUT3 ) + ,.ch0_z_DEM_LSB_OUT0 ( ch0_z_DEM_LSB_OUT0 ) + ,.ch0_z_DEM_LSB_OUT1 ( ch0_z_DEM_LSB_OUT1 ) + ,.ch0_z_DEM_LSB_OUT2 ( ch0_z_DEM_LSB_OUT2 ) + ,.ch0_z_DEM_LSB_OUT3 ( ch0_z_DEM_LSB_OUT3 ) + `endif + `ifdef CHANNEL_IS_FOUR + //------------------------------Ch1 DSP data out---------------------------------------------------- + `ifdef CHANNEL_XY_ON + ,.ch1_xy_A_DEM_MSB_OUT0 ( ch1_xy_A_DEM_MSB_OUT0 ) + ,.ch1_xy_A_DEM_MSB_OUT1 ( ch1_xy_A_DEM_MSB_OUT1 ) + ,.ch1_xy_A_DEM_MSB_OUT2 ( ch1_xy_A_DEM_MSB_OUT2 ) + ,.ch1_xy_A_DEM_MSB_OUT3 ( ch1_xy_A_DEM_MSB_OUT3 ) + ,.ch1_xy_A_DEM_MSB_OUT4 ( ch1_xy_A_DEM_MSB_OUT4 ) + ,.ch1_xy_A_DEM_MSB_OUT5 ( ch1_xy_A_DEM_MSB_OUT5 ) + ,.ch1_xy_A_DEM_MSB_OUT6 ( ch1_xy_A_DEM_MSB_OUT6 ) + ,.ch1_xy_A_DEM_MSB_OUT7 ( ch1_xy_A_DEM_MSB_OUT7 ) + ,.ch1_xy_B_DEM_MSB_OUT0 ( ch1_xy_B_DEM_MSB_OUT0 ) + ,.ch1_xy_B_DEM_MSB_OUT1 ( ch1_xy_B_DEM_MSB_OUT1 ) + ,.ch1_xy_B_DEM_MSB_OUT2 ( ch1_xy_B_DEM_MSB_OUT2 ) + ,.ch1_xy_B_DEM_MSB_OUT3 ( ch1_xy_B_DEM_MSB_OUT3 ) + ,.ch1_xy_B_DEM_MSB_OUT4 ( ch1_xy_B_DEM_MSB_OUT4 ) + ,.ch1_xy_B_DEM_MSB_OUT5 ( ch1_xy_B_DEM_MSB_OUT5 ) + ,.ch1_xy_B_DEM_MSB_OUT6 ( ch1_xy_B_DEM_MSB_OUT6 ) + ,.ch1_xy_B_DEM_MSB_OUT7 ( ch1_xy_B_DEM_MSB_OUT7 ) + ,.ch1_xy_A_DEM_ISB_OUT0 ( ch1_xy_A_DEM_ISB_OUT0 ) + ,.ch1_xy_A_DEM_ISB_OUT1 ( ch1_xy_A_DEM_ISB_OUT1 ) + ,.ch1_xy_A_DEM_ISB_OUT2 ( ch1_xy_A_DEM_ISB_OUT2 ) + ,.ch1_xy_A_DEM_ISB_OUT3 ( ch1_xy_A_DEM_ISB_OUT3 ) + ,.ch1_xy_A_DEM_ISB_OUT4 ( ch1_xy_A_DEM_ISB_OUT4 ) + ,.ch1_xy_A_DEM_ISB_OUT5 ( ch1_xy_A_DEM_ISB_OUT5 ) + ,.ch1_xy_A_DEM_ISB_OUT6 ( ch1_xy_A_DEM_ISB_OUT6 ) + ,.ch1_xy_A_DEM_ISB_OUT7 ( ch1_xy_A_DEM_ISB_OUT7 ) + ,.ch1_xy_B_DEM_ISB_OUT0 ( ch1_xy_B_DEM_ISB_OUT0 ) + ,.ch1_xy_B_DEM_ISB_OUT1 ( ch1_xy_B_DEM_ISB_OUT1 ) + ,.ch1_xy_B_DEM_ISB_OUT2 ( ch1_xy_B_DEM_ISB_OUT2 ) + ,.ch1_xy_B_DEM_ISB_OUT3 ( ch1_xy_B_DEM_ISB_OUT3 ) + ,.ch1_xy_B_DEM_ISB_OUT4 ( ch1_xy_B_DEM_ISB_OUT4 ) + ,.ch1_xy_B_DEM_ISB_OUT5 ( ch1_xy_B_DEM_ISB_OUT5 ) + ,.ch1_xy_B_DEM_ISB_OUT6 ( ch1_xy_B_DEM_ISB_OUT6 ) + ,.ch1_xy_B_DEM_ISB_OUT7 ( ch1_xy_B_DEM_ISB_OUT7 ) + ,.ch1_xy_A_DEM_LSB_OUT0 ( ch1_xy_A_DEM_LSB_OUT0 ) + ,.ch1_xy_A_DEM_LSB_OUT1 ( ch1_xy_A_DEM_LSB_OUT1 ) + ,.ch1_xy_A_DEM_LSB_OUT2 ( ch1_xy_A_DEM_LSB_OUT2 ) + ,.ch1_xy_A_DEM_LSB_OUT3 ( ch1_xy_A_DEM_LSB_OUT3 ) + ,.ch1_xy_A_DEM_LSB_OUT4 ( ch1_xy_A_DEM_LSB_OUT4 ) + ,.ch1_xy_A_DEM_LSB_OUT5 ( ch1_xy_A_DEM_LSB_OUT5 ) + ,.ch1_xy_A_DEM_LSB_OUT6 ( ch1_xy_A_DEM_LSB_OUT6 ) + ,.ch1_xy_A_DEM_LSB_OUT7 ( ch1_xy_A_DEM_LSB_OUT7 ) + ,.ch1_xy_B_DEM_LSB_OUT0 ( ch1_xy_B_DEM_LSB_OUT0 ) + ,.ch1_xy_B_DEM_LSB_OUT1 ( ch1_xy_B_DEM_LSB_OUT1 ) + ,.ch1_xy_B_DEM_LSB_OUT2 ( ch1_xy_B_DEM_LSB_OUT2 ) + ,.ch1_xy_B_DEM_LSB_OUT3 ( ch1_xy_B_DEM_LSB_OUT3 ) + ,.ch1_xy_B_DEM_LSB_OUT4 ( ch1_xy_B_DEM_LSB_OUT4 ) + ,.ch1_xy_B_DEM_LSB_OUT5 ( ch1_xy_B_DEM_LSB_OUT5 ) + ,.ch1_xy_B_DEM_LSB_OUT6 ( ch1_xy_B_DEM_LSB_OUT6 ) + ,.ch1_xy_B_DEM_LSB_OUT7 ( ch1_xy_B_DEM_LSB_OUT7 ) + `endif + `ifdef CHANNEL_Z_ON + ,.ch1_z_DEM_MSB_OUT0 ( ch1_z_DEM_MSB_OUT0 ) + ,.ch1_z_DEM_MSB_OUT1 ( ch1_z_DEM_MSB_OUT1 ) + ,.ch1_z_DEM_MSB_OUT2 ( ch1_z_DEM_MSB_OUT2 ) + ,.ch1_z_DEM_MSB_OUT3 ( ch1_z_DEM_MSB_OUT3 ) + ,.ch1_z_DEM_ISB_OUT0 ( ch1_z_DEM_ISB_OUT0 ) + ,.ch1_z_DEM_ISB_OUT1 ( ch1_z_DEM_ISB_OUT1 ) + ,.ch1_z_DEM_ISB_OUT2 ( ch1_z_DEM_ISB_OUT2 ) + ,.ch1_z_DEM_ISB_OUT3 ( ch1_z_DEM_ISB_OUT3 ) + ,.ch1_z_DEM_LSB_OUT0 ( ch1_z_DEM_LSB_OUT0 ) + ,.ch1_z_DEM_LSB_OUT1 ( ch1_z_DEM_LSB_OUT1 ) + ,.ch1_z_DEM_LSB_OUT2 ( ch1_z_DEM_LSB_OUT2 ) + ,.ch1_z_DEM_LSB_OUT3 ( ch1_z_DEM_LSB_OUT3 ) + `endif + //------------------------------Ch2 DSP data out---------------------------------------------------- + `ifdef CHANNEL_XY_ON + ,.ch2_xy_A_DEM_MSB_OUT0 ( ch2_xy_A_DEM_MSB_OUT0 ) + ,.ch2_xy_A_DEM_MSB_OUT1 ( ch2_xy_A_DEM_MSB_OUT1 ) + ,.ch2_xy_A_DEM_MSB_OUT2 ( ch2_xy_A_DEM_MSB_OUT2 ) + ,.ch2_xy_A_DEM_MSB_OUT3 ( ch2_xy_A_DEM_MSB_OUT3 ) + ,.ch2_xy_A_DEM_MSB_OUT4 ( ch2_xy_A_DEM_MSB_OUT4 ) + ,.ch2_xy_A_DEM_MSB_OUT5 ( ch2_xy_A_DEM_MSB_OUT5 ) + ,.ch2_xy_A_DEM_MSB_OUT6 ( ch2_xy_A_DEM_MSB_OUT6 ) + ,.ch2_xy_A_DEM_MSB_OUT7 ( ch2_xy_A_DEM_MSB_OUT7 ) + ,.ch2_xy_B_DEM_MSB_OUT0 ( ch2_xy_B_DEM_MSB_OUT0 ) + ,.ch2_xy_B_DEM_MSB_OUT1 ( ch2_xy_B_DEM_MSB_OUT1 ) + ,.ch2_xy_B_DEM_MSB_OUT2 ( ch2_xy_B_DEM_MSB_OUT2 ) + ,.ch2_xy_B_DEM_MSB_OUT3 ( ch2_xy_B_DEM_MSB_OUT3 ) + ,.ch2_xy_B_DEM_MSB_OUT4 ( ch2_xy_B_DEM_MSB_OUT4 ) + ,.ch2_xy_B_DEM_MSB_OUT5 ( ch2_xy_B_DEM_MSB_OUT5 ) + ,.ch2_xy_B_DEM_MSB_OUT6 ( ch2_xy_B_DEM_MSB_OUT6 ) + ,.ch2_xy_B_DEM_MSB_OUT7 ( ch2_xy_B_DEM_MSB_OUT7 ) + ,.ch2_xy_A_DEM_ISB_OUT0 ( ch2_xy_A_DEM_ISB_OUT0 ) + ,.ch2_xy_A_DEM_ISB_OUT1 ( ch2_xy_A_DEM_ISB_OUT1 ) + ,.ch2_xy_A_DEM_ISB_OUT2 ( ch2_xy_A_DEM_ISB_OUT2 ) + ,.ch2_xy_A_DEM_ISB_OUT3 ( ch2_xy_A_DEM_ISB_OUT3 ) + ,.ch2_xy_A_DEM_ISB_OUT4 ( ch2_xy_A_DEM_ISB_OUT4 ) + ,.ch2_xy_A_DEM_ISB_OUT5 ( ch2_xy_A_DEM_ISB_OUT5 ) + ,.ch2_xy_A_DEM_ISB_OUT6 ( ch2_xy_A_DEM_ISB_OUT6 ) + ,.ch2_xy_A_DEM_ISB_OUT7 ( ch2_xy_A_DEM_ISB_OUT7 ) + ,.ch2_xy_B_DEM_ISB_OUT0 ( ch2_xy_B_DEM_ISB_OUT0 ) + ,.ch2_xy_B_DEM_ISB_OUT1 ( ch2_xy_B_DEM_ISB_OUT1 ) + ,.ch2_xy_B_DEM_ISB_OUT2 ( ch2_xy_B_DEM_ISB_OUT2 ) + ,.ch2_xy_B_DEM_ISB_OUT3 ( ch2_xy_B_DEM_ISB_OUT3 ) + ,.ch2_xy_B_DEM_ISB_OUT4 ( ch2_xy_B_DEM_ISB_OUT4 ) + ,.ch2_xy_B_DEM_ISB_OUT5 ( ch2_xy_B_DEM_ISB_OUT5 ) + ,.ch2_xy_B_DEM_ISB_OUT6 ( ch2_xy_B_DEM_ISB_OUT6 ) + ,.ch2_xy_B_DEM_ISB_OUT7 ( ch2_xy_B_DEM_ISB_OUT7 ) + ,.ch2_xy_A_DEM_LSB_OUT0 ( ch2_xy_A_DEM_LSB_OUT0 ) + ,.ch2_xy_A_DEM_LSB_OUT1 ( ch2_xy_A_DEM_LSB_OUT1 ) + ,.ch2_xy_A_DEM_LSB_OUT2 ( ch2_xy_A_DEM_LSB_OUT2 ) + ,.ch2_xy_A_DEM_LSB_OUT3 ( ch2_xy_A_DEM_LSB_OUT3 ) + ,.ch2_xy_A_DEM_LSB_OUT4 ( ch2_xy_A_DEM_LSB_OUT4 ) + ,.ch2_xy_A_DEM_LSB_OUT5 ( ch2_xy_A_DEM_LSB_OUT5 ) + ,.ch2_xy_A_DEM_LSB_OUT6 ( ch2_xy_A_DEM_LSB_OUT6 ) + ,.ch2_xy_A_DEM_LSB_OUT7 ( ch2_xy_A_DEM_LSB_OUT7 ) + ,.ch2_xy_B_DEM_LSB_OUT0 ( ch2_xy_B_DEM_LSB_OUT0 ) + ,.ch2_xy_B_DEM_LSB_OUT1 ( ch2_xy_B_DEM_LSB_OUT1 ) + ,.ch2_xy_B_DEM_LSB_OUT2 ( ch2_xy_B_DEM_LSB_OUT2 ) + ,.ch2_xy_B_DEM_LSB_OUT3 ( ch2_xy_B_DEM_LSB_OUT3 ) + ,.ch2_xy_B_DEM_LSB_OUT4 ( ch2_xy_B_DEM_LSB_OUT4 ) + ,.ch2_xy_B_DEM_LSB_OUT5 ( ch2_xy_B_DEM_LSB_OUT5 ) + ,.ch2_xy_B_DEM_LSB_OUT6 ( ch2_xy_B_DEM_LSB_OUT6 ) + ,.ch2_xy_B_DEM_LSB_OUT7 ( ch2_xy_B_DEM_LSB_OUT7 ) + `endif + `ifdef CHANNEL_Z_ON + ,.ch2_z_DEM_MSB_OUT0 ( ch2_z_DEM_MSB_OUT0 ) + ,.ch2_z_DEM_MSB_OUT1 ( ch2_z_DEM_MSB_OUT1 ) + ,.ch2_z_DEM_MSB_OUT2 ( ch2_z_DEM_MSB_OUT2 ) + ,.ch2_z_DEM_MSB_OUT3 ( ch2_z_DEM_MSB_OUT3 ) + ,.ch2_z_DEM_ISB_OUT0 ( ch2_z_DEM_ISB_OUT0 ) + ,.ch2_z_DEM_ISB_OUT1 ( ch2_z_DEM_ISB_OUT1 ) + ,.ch2_z_DEM_ISB_OUT2 ( ch2_z_DEM_ISB_OUT2 ) + ,.ch2_z_DEM_ISB_OUT3 ( ch2_z_DEM_ISB_OUT3 ) + ,.ch2_z_DEM_LSB_OUT0 ( ch2_z_DEM_LSB_OUT0 ) + ,.ch2_z_DEM_LSB_OUT1 ( ch2_z_DEM_LSB_OUT1 ) + ,.ch2_z_DEM_LSB_OUT2 ( ch2_z_DEM_LSB_OUT2 ) + ,.ch2_z_DEM_LSB_OUT3 ( ch2_z_DEM_LSB_OUT3 ) + `endif + //------------------------------Ch3 DSP data out---------------------------------------------------- + `ifdef CHANNEL_XY_ON + ,.ch3_xy_A_DEM_MSB_OUT0 ( ch3_xy_A_DEM_MSB_OUT0 ) + ,.ch3_xy_A_DEM_MSB_OUT1 ( ch3_xy_A_DEM_MSB_OUT1 ) + ,.ch3_xy_A_DEM_MSB_OUT2 ( ch3_xy_A_DEM_MSB_OUT2 ) + ,.ch3_xy_A_DEM_MSB_OUT3 ( ch3_xy_A_DEM_MSB_OUT3 ) + ,.ch3_xy_A_DEM_MSB_OUT4 ( ch3_xy_A_DEM_MSB_OUT4 ) + ,.ch3_xy_A_DEM_MSB_OUT5 ( ch3_xy_A_DEM_MSB_OUT5 ) + ,.ch3_xy_A_DEM_MSB_OUT6 ( ch3_xy_A_DEM_MSB_OUT6 ) + ,.ch3_xy_A_DEM_MSB_OUT7 ( ch3_xy_A_DEM_MSB_OUT7 ) + ,.ch3_xy_B_DEM_MSB_OUT0 ( ch3_xy_B_DEM_MSB_OUT0 ) + ,.ch3_xy_B_DEM_MSB_OUT1 ( ch3_xy_B_DEM_MSB_OUT1 ) + ,.ch3_xy_B_DEM_MSB_OUT2 ( ch3_xy_B_DEM_MSB_OUT2 ) + ,.ch3_xy_B_DEM_MSB_OUT3 ( ch3_xy_B_DEM_MSB_OUT3 ) + ,.ch3_xy_B_DEM_MSB_OUT4 ( ch3_xy_B_DEM_MSB_OUT4 ) + ,.ch3_xy_B_DEM_MSB_OUT5 ( ch3_xy_B_DEM_MSB_OUT5 ) + ,.ch3_xy_B_DEM_MSB_OUT6 ( ch3_xy_B_DEM_MSB_OUT6 ) + ,.ch3_xy_B_DEM_MSB_OUT7 ( ch3_xy_B_DEM_MSB_OUT7 ) + ,.ch3_xy_A_DEM_ISB_OUT0 ( ch3_xy_A_DEM_ISB_OUT0 ) + ,.ch3_xy_A_DEM_ISB_OUT1 ( ch3_xy_A_DEM_ISB_OUT1 ) + ,.ch3_xy_A_DEM_ISB_OUT2 ( ch3_xy_A_DEM_ISB_OUT2 ) + ,.ch3_xy_A_DEM_ISB_OUT3 ( ch3_xy_A_DEM_ISB_OUT3 ) + ,.ch3_xy_A_DEM_ISB_OUT4 ( ch3_xy_A_DEM_ISB_OUT4 ) + ,.ch3_xy_A_DEM_ISB_OUT5 ( ch3_xy_A_DEM_ISB_OUT5 ) + ,.ch3_xy_A_DEM_ISB_OUT6 ( ch3_xy_A_DEM_ISB_OUT6 ) + ,.ch3_xy_A_DEM_ISB_OUT7 ( ch3_xy_A_DEM_ISB_OUT7 ) + ,.ch3_xy_B_DEM_ISB_OUT0 ( ch3_xy_B_DEM_ISB_OUT0 ) + ,.ch3_xy_B_DEM_ISB_OUT1 ( ch3_xy_B_DEM_ISB_OUT1 ) + ,.ch3_xy_B_DEM_ISB_OUT2 ( ch3_xy_B_DEM_ISB_OUT2 ) + ,.ch3_xy_B_DEM_ISB_OUT3 ( ch3_xy_B_DEM_ISB_OUT3 ) + ,.ch3_xy_B_DEM_ISB_OUT4 ( ch3_xy_B_DEM_ISB_OUT4 ) + ,.ch3_xy_B_DEM_ISB_OUT5 ( ch3_xy_B_DEM_ISB_OUT5 ) + ,.ch3_xy_B_DEM_ISB_OUT6 ( ch3_xy_B_DEM_ISB_OUT6 ) + ,.ch3_xy_B_DEM_ISB_OUT7 ( ch3_xy_B_DEM_ISB_OUT7 ) + ,.ch3_xy_A_DEM_LSB_OUT0 ( ch3_xy_A_DEM_LSB_OUT0 ) + ,.ch3_xy_A_DEM_LSB_OUT1 ( ch3_xy_A_DEM_LSB_OUT1 ) + ,.ch3_xy_A_DEM_LSB_OUT2 ( ch3_xy_A_DEM_LSB_OUT2 ) + ,.ch3_xy_A_DEM_LSB_OUT3 ( ch3_xy_A_DEM_LSB_OUT3 ) + ,.ch3_xy_A_DEM_LSB_OUT4 ( ch3_xy_A_DEM_LSB_OUT4 ) + ,.ch3_xy_A_DEM_LSB_OUT5 ( ch3_xy_A_DEM_LSB_OUT5 ) + ,.ch3_xy_A_DEM_LSB_OUT6 ( ch3_xy_A_DEM_LSB_OUT6 ) + ,.ch3_xy_A_DEM_LSB_OUT7 ( ch3_xy_A_DEM_LSB_OUT7 ) + ,.ch3_xy_B_DEM_LSB_OUT0 ( ch3_xy_B_DEM_LSB_OUT0 ) + ,.ch3_xy_B_DEM_LSB_OUT1 ( ch3_xy_B_DEM_LSB_OUT1 ) + ,.ch3_xy_B_DEM_LSB_OUT2 ( ch3_xy_B_DEM_LSB_OUT2 ) + ,.ch3_xy_B_DEM_LSB_OUT3 ( ch3_xy_B_DEM_LSB_OUT3 ) + ,.ch3_xy_B_DEM_LSB_OUT4 ( ch3_xy_B_DEM_LSB_OUT4 ) + ,.ch3_xy_B_DEM_LSB_OUT5 ( ch3_xy_B_DEM_LSB_OUT5 ) + ,.ch3_xy_B_DEM_LSB_OUT6 ( ch3_xy_B_DEM_LSB_OUT6 ) + ,.ch3_xy_B_DEM_LSB_OUT7 ( ch3_xy_B_DEM_LSB_OUT7 ) + `endif + `ifdef CHANNEL_Z_ON + ,.ch3_z_DEM_MSB_OUT0 ( ch3_z_DEM_MSB_OUT0 ) + ,.ch3_z_DEM_MSB_OUT1 ( ch3_z_DEM_MSB_OUT1 ) + ,.ch3_z_DEM_MSB_OUT2 ( ch3_z_DEM_MSB_OUT2 ) + ,.ch3_z_DEM_MSB_OUT3 ( ch3_z_DEM_MSB_OUT3 ) + ,.ch3_z_DEM_ISB_OUT0 ( ch3_z_DEM_ISB_OUT0 ) + ,.ch3_z_DEM_ISB_OUT1 ( ch3_z_DEM_ISB_OUT1 ) + ,.ch3_z_DEM_ISB_OUT2 ( ch3_z_DEM_ISB_OUT2 ) + ,.ch3_z_DEM_ISB_OUT3 ( ch3_z_DEM_ISB_OUT3 ) + ,.ch3_z_DEM_LSB_OUT0 ( ch3_z_DEM_LSB_OUT0 ) + ,.ch3_z_DEM_LSB_OUT1 ( ch3_z_DEM_LSB_OUT1 ) + ,.ch3_z_DEM_LSB_OUT2 ( ch3_z_DEM_LSB_OUT2 ) + ,.ch3_z_DEM_LSB_OUT3 ( ch3_z_DEM_LSB_OUT3 ) + `endif + `endif +); + +assign pll_if.ref_sel = U_xyz_chip_top.U_digital_top.U_intpll_regfile.ref_sel ; +assign pll_if.ref_en = U_xyz_chip_top.U_digital_top.U_intpll_regfile.ref_en ; +assign pll_if.ref_s2d_en = U_xyz_chip_top.U_digital_top.U_intpll_regfile.ref_s2d_en ; +assign pll_if.p_cnt = U_xyz_chip_top.U_digital_top.U_intpll_regfile.p_cnt ; +assign pll_if.pfd_delay = U_xyz_chip_top.U_digital_top.U_intpll_regfile.pfd_delay ; +assign pll_if.pfd_dff_Set = U_xyz_chip_top.U_digital_top.U_intpll_regfile.pfd_dff_Set ; +assign pll_if.pfd_dff_4and = U_xyz_chip_top.U_digital_top.U_intpll_regfile.pfd_dff_4and ; +assign pll_if.spd_div = U_xyz_chip_top.U_digital_top.U_intpll_regfile.spd_div ; +assign pll_if.spd_pulse_width = U_xyz_chip_top.U_digital_top.U_intpll_regfile.spd_pulse_width; +assign pll_if.spd_pulse_sw = U_xyz_chip_top.U_digital_top.U_intpll_regfile.spd_pulse_sw ; +assign pll_if.cpc_sel = U_xyz_chip_top.U_digital_top.U_intpll_regfile.cpc_sel ; +assign pll_if.swcp_i = U_xyz_chip_top.U_digital_top.U_intpll_regfile.swcp_i ; +assign pll_if.sw_ptat_r = U_xyz_chip_top.U_digital_top.U_intpll_regfile.sw_ptat_r ; +assign pll_if.sw_fll_cpi = U_xyz_chip_top.U_digital_top.U_intpll_regfile.sw_fll_cpi ; +assign pll_if.sw_fll_delay = U_xyz_chip_top.U_digital_top.U_intpll_regfile.sw_fll_delay ; +assign pll_if.pfd_sel = U_xyz_chip_top.U_digital_top.U_intpll_regfile.pfd_sel ; +assign pll_if.spd_sel = U_xyz_chip_top.U_digital_top.U_intpll_regfile.spd_sel ; +assign pll_if.fll_sel = U_xyz_chip_top.U_digital_top.U_intpll_regfile.fll_sel ; +assign pll_if.vco_tc = U_xyz_chip_top.U_digital_top.U_intpll_regfile.vco_tc ; +assign pll_if.vco_tcr = U_xyz_chip_top.U_digital_top.U_intpll_regfile.vco_tcr ; +assign pll_if.vco_gain_adj = U_xyz_chip_top.U_digital_top.U_intpll_regfile.vco_gain_adj ; +assign pll_if.vco_gain_adj_r = U_xyz_chip_top.U_digital_top.U_intpll_regfile.vco_gain_adj_r ; +assign pll_if.vco_cur_adj = U_xyz_chip_top.U_digital_top.U_intpll_regfile.vco_cur_adj ; +assign pll_if.vco_buff_en = U_xyz_chip_top.U_digital_top.U_intpll_regfile.vco_buff_en ; +assign pll_if.vco_en = U_xyz_chip_top.U_digital_top.U_intpll_regfile.vco_en ; +assign pll_if.pll_dpwr_adj = U_xyz_chip_top.U_digital_top.U_intpll_regfile.pll_dpwr_adj ; +assign pll_if.vco_fb_adj = U_xyz_chip_top.U_digital_top.U_intpll_regfile.vco_fb_adj ; +assign pll_if.afc_en = U_xyz_chip_top.U_digital_top.U_intpll_regfile.afc_en ; +assign pll_if.afc_shutdown = U_xyz_chip_top.U_digital_top.U_intpll_regfile.afc_shutdown ; +assign pll_if.afc_det_speed = U_xyz_chip_top.U_digital_top.U_intpll_regfile.afc_det_speed ; +assign pll_if.flag_out_sel = U_xyz_chip_top.U_digital_top.U_intpll_regfile.flag_out_sel ; +assign pll_if.afc_reset = U_xyz_chip_top.U_digital_top.U_intpll_regfile.afc_reset ; +assign pll_if.afc_cnt = U_xyz_chip_top.U_digital_top.U_intpll_regfile.afc_cnt ; +assign pll_if.afc_ld_cnt = U_xyz_chip_top.U_digital_top.U_intpll_regfile.afc_ld_cnt ; +assign pll_if.afc_pres = U_xyz_chip_top.U_digital_top.U_intpll_regfile.afc_pres ; +assign pll_if.afc_ld_tcc = U_xyz_chip_top.U_digital_top.U_intpll_regfile.afc_ld_tcc ; +assign pll_if.afc_fb_tcc = U_xyz_chip_top.U_digital_top.U_intpll_regfile.afc_fb_tcc ; +assign pll_if.div_rstn_sel = U_xyz_chip_top.U_digital_top.U_intpll_regfile.div_rstn_sel ; +assign pll_if.test_clk_sel = U_xyz_chip_top.U_digital_top.U_intpll_regfile.test_clk_sel ; +assign pll_if.test_clk_oen = U_xyz_chip_top.U_digital_top.U_intpll_regfile.test_clk_oen ; +assign pll_if.dig_clk_sel = U_xyz_chip_top.U_digital_top.U_intpll_regfile.dig_clk_sel ; +assign pll_if.div_sync_en = U_xyz_chip_top.U_digital_top.U_intpll_regfile.div_sync_en ; +assign pll_if.sync_oe = U_xyz_chip_top.U_digital_top.U_intpll_regfile.sync_oe ; +assign pll_if.pll_lock = U_xyz_chip_top.U_digital_top.U_intpll_regfile.pll_lock ; + +assign dac_if.Prbs = U_xyz_chip_top.U_digital_top.ch0_dac_Prbs ; +assign dac_if.Set0 = U_xyz_chip_top.U_digital_top.ch0_dac_Set0 ; +assign dac_if.Set1 = U_xyz_chip_top.U_digital_top.ch0_dac_Set1 ; +assign dac_if.Set2 = U_xyz_chip_top.U_digital_top.ch0_dac_Set2 ; +assign dac_if.Set3 = U_xyz_chip_top.U_digital_top.ch0_dac_Set3 ; +assign dac_if.Set4 = U_xyz_chip_top.U_digital_top.ch0_dac_Set4 ; +assign dac_if.Set5 = U_xyz_chip_top.U_digital_top.ch0_dac_Set5 ; +assign dac_if.Set6 = U_xyz_chip_top.U_digital_top.ch0_dac_Set6 ; +assign dac_if.Set7 = U_xyz_chip_top.U_digital_top.ch0_dac_Set7 ; +assign dac_if.Set8 = U_xyz_chip_top.U_digital_top.ch0_dac_Set8 ; +assign dac_if.Set9 = U_xyz_chip_top.U_digital_top.ch0_dac_Set9 ; +assign dac_if.Set10 = U_xyz_chip_top.U_digital_top.ch0_dac_Set10 ; +assign dac_if.Set11 = U_xyz_chip_top.U_digital_top.ch0_dac_Set11 ; +assign dac_if.Set12 = U_xyz_chip_top.U_digital_top.ch0_dac_Set12 ; +assign dac_if.Set13 = U_xyz_chip_top.U_digital_top.ch0_dac_Set13 ; +assign dac_if.Set14 = U_xyz_chip_top.U_digital_top.ch0_dac_Set14 ; +assign dac_if.Set15 = U_xyz_chip_top.U_digital_top.ch0_dac_Set15 ; +assign dac_if.Dac_addr = U_xyz_chip_top.U_digital_top.ch0_dac_addr ; +assign dac_if.Dac_dw = U_xyz_chip_top.U_digital_top.ch0_dac_dw ; +assign dac_if.Dac_ref = U_xyz_chip_top.U_digital_top.ch0_dac_ref ; +assign dac_if.Prbs_rst0 = U_xyz_chip_top.U_digital_top.ch0_dac_Prbs_rst0 ; +assign dac_if.Prbs_set0 = U_xyz_chip_top.U_digital_top.ch0_dac_Prbs_set0 ; +assign dac_if.Prbs_rst1 = U_xyz_chip_top.U_digital_top.ch0_dac_Prbs_rst1 ; +assign dac_if.Prbs_set1 = U_xyz_chip_top.U_digital_top.ch0_dac_Prbs_set1 ; +assign dac_if.Cal_sig = U_xyz_chip_top.U_digital_top.ch0_dac_Cal_sig ; +assign dac_if.Cal_rstn = U_xyz_chip_top.U_digital_top.ch0_dac_Cal_rstn ; +assign dac_if.Cal_div_rstn = U_xyz_chip_top.U_digital_top.ch0_dac_Cal_div_rstn; +assign dac_if.Cal_end = U_xyz_chip_top.U_digital_top.ch0_dac_Cal_end ; + +assign sys_if.dbg_enable = U_xyz_chip_top.U_digital_top.U_system_regfile.dbg_enable ; +assign sys_if.dbg_data_sel = U_xyz_chip_top.U_digital_top.U_system_regfile.dbg_data_sel ; +assign sys_if.dbg_ch_sel = U_xyz_chip_top.U_digital_top.U_system_regfile.dbg_ch_sel ; +assign sys_if.status[28] = U_xyz_chip_top.U_digital_top.U_system_regfile.dbg_upd ; +assign sys_if.status[ 3] = U_xyz_chip_top.U_digital_top.U_system_regfile.ch0_proc_cft ; +assign sys_if.status[ 2] = U_xyz_chip_top.U_digital_top.U_system_regfile.ch0_ldst_addr_unalgn; +assign sys_if.status[ 1] = U_xyz_chip_top.U_digital_top.U_system_regfile.ch0_dec_err ; +assign sys_if.status[ 0] = U_xyz_chip_top.U_digital_top.U_system_regfile.ch0_exit_irq ; +assign sys_if.status[11] = U_xyz_chip_top.U_digital_top.U_system_regfile.ch1_proc_cft ; +assign sys_if.status[10] = U_xyz_chip_top.U_digital_top.U_system_regfile.ch1_ldst_addr_unalgn; +assign sys_if.status[ 9] = U_xyz_chip_top.U_digital_top.U_system_regfile.ch1_dec_err ; +assign sys_if.status[ 8] = U_xyz_chip_top.U_digital_top.U_system_regfile.ch1_exit_irq ; +assign sys_if.status[19] = U_xyz_chip_top.U_digital_top.U_system_regfile.ch2_proc_cft ; +assign sys_if.status[18] = U_xyz_chip_top.U_digital_top.U_system_regfile.ch2_ldst_addr_unalgn; +assign sys_if.status[17] = U_xyz_chip_top.U_digital_top.U_system_regfile.ch2_dec_err ; +assign sys_if.status[16] = U_xyz_chip_top.U_digital_top.U_system_regfile.ch2_exit_irq ; +assign sys_if.status[27] = U_xyz_chip_top.U_digital_top.U_system_regfile.ch3_proc_cft ; +assign sys_if.status[26] = U_xyz_chip_top.U_digital_top.U_system_regfile.ch3_ldst_addr_unalgn; +assign sys_if.status[25] = U_xyz_chip_top.U_digital_top.U_system_regfile.ch3_dec_err ; +assign sys_if.status[24] = U_xyz_chip_top.U_digital_top.U_system_regfile.ch3_exit_irq ; +assign sys_if.soft_rstn[0] = U_xyz_chip_top.U_digital_top.U_system_regfile.sys_soft_rstn ; +assign sys_if.soft_rstn[1] = U_xyz_chip_top.U_digital_top.U_system_regfile.ch0_soft_rstn ; +assign sys_if.soft_rstn[2] = U_xyz_chip_top.U_digital_top.U_system_regfile.ch1_soft_rstn ; +assign sys_if.soft_rstn[3] = U_xyz_chip_top.U_digital_top.U_system_regfile.ch2_soft_rstn ; +assign sys_if.soft_rstn[4] = U_xyz_chip_top.U_digital_top.U_system_regfile.ch3_soft_rstn ; +assign sys_if.irq = U_xyz_chip_top.U_digital_top.U_system_regfile.irq ; + + +assign mcu_if.wrmask = U_xyz_chip_top.U_digital_top.U0_channel_top.U_mcu_regfile.wrmask ; + +assign awg_if.fb_st_i = U_xyz_chip_top.U_digital_top.U0_channel_top.U_ctrl_regfile.fb_st_i ; +assign awg_if.run_time = U_xyz_chip_top.U_digital_top.U0_channel_top.U_ctrl_regfile.run_time ; +assign awg_if.instr_num = U_xyz_chip_top.U_digital_top.U0_channel_top.U_ctrl_regfile.instr_num ; +assign awg_if.bais_i_ov = U_xyz_chip_top.U_digital_top.U0_channel_top.U_ctrl_regfile.bais_i_ov ; +assign awg_if.bais_q_ov = U_xyz_chip_top.U_digital_top.U0_channel_top.U_ctrl_regfile.bais_q_ov ; +assign awg_if.awg_ctrl_fsm_st = U_xyz_chip_top.U_digital_top.U0_channel_top.U_ctrl_regfile.awg_ctrl_fsm_st ; +assign awg_if.mcu_param0 = U_xyz_chip_top.U_digital_top.U0_channel_top.U_ctrl_regfile.mcu_param0 ; +assign awg_if.mcu_param1 = U_xyz_chip_top.U_digital_top.U0_channel_top.U_ctrl_regfile.mcu_param1 ; +assign awg_if.mcu_param2 = U_xyz_chip_top.U_digital_top.U0_channel_top.U_ctrl_regfile.mcu_param2 ; +assign awg_if.mcu_param3 = U_xyz_chip_top.U_digital_top.U0_channel_top.U_ctrl_regfile.mcu_param3 ; +assign awg_if.mcu_result0 = U_xyz_chip_top.U_digital_top.U0_channel_top.U_ctrl_regfile.mcu_result0 ; +assign awg_if.mcu_result1 = U_xyz_chip_top.U_digital_top.U0_channel_top.U_ctrl_regfile.mcu_result1 ; +assign awg_if.mcu_result2 = U_xyz_chip_top.U_digital_top.U0_channel_top.U_ctrl_regfile.mcu_result2 ; +assign awg_if.mcu_result3 = U_xyz_chip_top.U_digital_top.U0_channel_top.U_ctrl_regfile.mcu_result3 ; +assign awg_if.fb_st_o = U_xyz_chip_top.U_digital_top.U0_channel_top.U_ctrl_regfile.fb_st_o ; +assign awg_if.mod_sel_sideband = U_xyz_chip_top.U_digital_top.U0_channel_top.U_ctrl_regfile.mod_sel_sideband; +assign awg_if.qam_nco_clr = U_xyz_chip_top.U_digital_top.U0_channel_top.U_ctrl_regfile.qam_nco_clr ; +assign awg_if.qam_nco_sclr_en = U_xyz_chip_top.U_digital_top.U0_channel_top.U_ctrl_regfile.qam_nco_sclr_en ; +assign awg_if.qam_fcw = U_xyz_chip_top.U_digital_top.U0_channel_top.U_ctrl_regfile.qam_fcw ; +assign awg_if.qam_pha = U_xyz_chip_top.U_digital_top.U0_channel_top.U_ctrl_regfile.qam_pha ; +assign awg_if.qam_mod = U_xyz_chip_top.U_digital_top.U0_channel_top.U_ctrl_regfile.qam_mod ; +assign awg_if.qam_sel_sideband = U_xyz_chip_top.U_digital_top.U0_channel_top.U_ctrl_regfile.qam_sel_sideband; +assign awg_if.intp_mode = U_xyz_chip_top.U_digital_top.U0_channel_top.U_ctrl_regfile.intp_mode ; +assign awg_if.role_sel = U_xyz_chip_top.U_digital_top.U0_channel_top.U_ctrl_regfile.role_sel ; +assign awg_if.dac_mode_sel = U_xyz_chip_top.U_digital_top.U0_channel_top.U_ctrl_regfile.dac_mode_sel ; +assign awg_if.dout_sel = U_xyz_chip_top.U_digital_top.U0_channel_top.U_ctrl_regfile.dout_sel ; + + +wire [15 :0] ch0_mod_data_i = U_xyz_chip_top.U_digital_top. U_debug_top.U_debug_sampling.ch0_mod_data_i ; +wire [15 :0] ch0_mod_data_q = U_xyz_chip_top.U_digital_top. U_debug_top.U_debug_sampling.ch0_mod_data_q ; +wire ch0_mod_vld = U_xyz_chip_top.U_digital_top. U_debug_top.U_debug_sampling.ch0_mod_vld ; + + +wire [511:0] mod_data_c = U_xyz_chip_top.U_digital_top.U_debug_top.U_debug_sampling.mod_data_c ; +wire mod_cen = U_xyz_chip_top.U_digital_top.U_debug_top.U_debug_sampling.mod_cen ; + + case6 test(spi_if,pll_if,dac_if,sys_if,mcu_if,awg_if,mst); + + +int seed; +initial begin + $value$plusargs("ntb_random_seed=%d", seed); +end + +endmodule + diff --git a/tb/testbench/Makefile b/tb/testbench/Makefile new file mode 100644 index 0000000..9d8864c --- /dev/null +++ b/tb/testbench/Makefile @@ -0,0 +1,17 @@ +VCS = vcs -full64 -sverilog +lint=TFIPC-L +v2k -debug_access+all -q -timescale=1ns/100fs +nospecify -l compile.log + +SIMV = ./simv -l sim.log + +all:comp run + +comp: + ${VCS} -f files.f + +run: + ${SIMV} + +dbg: + verdi -sv -f files.f -top TB -ssf *.fsdb -nologo & + +clean: + rm -rf DVE* simv* *log ucli.key verdiLog urgReport csrc novas.* *.fsdb *.dat *.daidir *.vdb *~ diff --git a/tb/testbench/awgreg_tb/awgreg_driver.sv b/tb/testbench/awgreg_tb/awgreg_driver.sv new file mode 100644 index 0000000..6bb10bf --- /dev/null +++ b/tb/testbench/awgreg_tb/awgreg_driver.sv @@ -0,0 +1,83 @@ +class awgreg_driver; + + + awgreg_trans tr; + + //interface + virtual awgreg_if aif; + virtual spi_if wif; + + int pktnum; + + + function new(); + endfunction + extern task do_drive(); + extern task make_pkt(); + +endclass : awgreg_driver + +task awgreg_driver::do_drive(); + int pkt_i = 0; + + aif.fb_st_i =3'b0 ; + aif.run_time =32'b0 ; + aif.instr_num =32'b0 ; + aif.mcu_result0 =32'b0 ; // MCU result 0 + aif.mcu_result1 =32'b0 ; // MCU result 1 + aif.mcu_result2 =32'b0 ; // MCU result 2 + aif.mcu_result3 =32'b0 ; // MCU result 3 + + + fork + while(1) begin + if(pkt_i == pktnum) break; + make_pkt(); + end + + repeat(pktnum) begin: kill_progress + @(negedge wif.csn); + pkt_i++; + end + join + + +endtask + +task awgreg_driver::make_pkt(); + int cnt=0; + + cnt = 0; + + + tr = new(); + if(!tr.randomize()) + $fatal(0,"Randomize Failed"); + + while(cnt<2000) begin + @(posedge wif.clk); + + cnt = cnt + 1; + + case(cnt) + tr.fb_st_i_time : + aif.fb_st_i <= tr.fb_st_i ; + tr.run_time_time : + aif.run_time <= tr.run_time ; + tr.instr_num_time : + aif.instr_num <= tr.instr_num ; + tr.mcu_result0_time: + aif.mcu_result0 <= tr.mcu_result0 ; + tr.mcu_result1_time: + aif.mcu_result1 <= tr.mcu_result1 ; + tr.mcu_result2_time: + aif.mcu_result2 <= tr.mcu_result2 ; + tr.mcu_result3_time: + aif.mcu_result3 <= tr.mcu_result3 ; + endcase + + end + + +endtask : make_pkt + diff --git a/tb/testbench/awgreg_tb/awgreg_env.sv b/tb/testbench/awgreg_tb/awgreg_env.sv new file mode 100644 index 0000000..6a4b7f6 --- /dev/null +++ b/tb/testbench/awgreg_tb/awgreg_env.sv @@ -0,0 +1,94 @@ +class awgreg_env; + + int pktnum; + + virtual spi_if wif; + virtual awgreg_if aif; + virtual sram_if xif; + + spi_driver w_driver; + awgreg_driver a_driver; + spi_monitor w_monitor; + awgreg_monitor a_monitor; + awgreg_scoreboard a_scb; + + function new(); + endfunction; + + extern function build(); + extern task run(); + +endclass: awgreg_env + +function awgreg_env::build(); + + w_driver = new(); + if(!w_driver.randomize() with {error_time == 0;}) + $fatal(0,"Randomize Failed"); + w_driver.pktnum = pktnum; + w_driver.vif = wif; + w_driver.autarchy = 1'b0; + //my_driver.half_sclk = 16; + + a_driver = new(); + a_driver.pktnum = pktnum; + a_driver.aif = aif; + a_driver.wif = wif; + + w_monitor = new(); + w_monitor.pktnum = pktnum; + w_monitor.wif = wif; + w_monitor.xif = xif; + + a_monitor = new(); + a_monitor.pktnum = pktnum; + a_monitor.aif = aif; + a_monitor.wif = wif; + a_monitor.xif = xif; + + a_scb = new(); + a_scb.pktnum = pktnum; + a_scb.aif = aif; + a_scb.wif = wif; + +endfunction: build + +task awgreg_env::run(); + int pkt_i=0; + + fork + + w_driver.do_drive(); + + a_driver.do_drive(); + + w_monitor.do_mon(); + + a_monitor.do_mon(); + + a_scb.do_check(); + + + //Port: Monitor2Scoreboard + while(1) begin: scb + if(pkt_i==pktnum) break; + @(posedge wif.csn); + repeat(9) @(negedge wif.clk); + a_scb.din = w_monitor.din; + a_scb.dout = w_monitor.dout; + a_scb.awg_tr = a_monitor.awg_tr; + end + + repeat(pktnum) begin: kill_progress + @(negedge wif.csn); + pkt_i++; + end + + join + + $display("SCOREBOARD:"); + $display("\tError:\t\t%0d",a_scb.error); + $display("\tError_FB:\t%0d",a_scb.error_fb); + +endtask: run + diff --git a/tb/testbench/awgreg_tb/awgreg_if.sv b/tb/testbench/awgreg_tb/awgreg_if.sv new file mode 100644 index 0000000..ccc0dcf --- /dev/null +++ b/tb/testbench/awgreg_tb/awgreg_if.sv @@ -0,0 +1,64 @@ + + +interface awgreg_if(input clk,input rstn); + + //input port + logic [2 :0] fb_st_i ; + logic [31 :0] run_time ; + logic [31 :0] instr_num ; + logic [31 :0] mcu_result0 ; // MCU result 0 + logic [31 :0] mcu_result1 ; // MCU result 1 + logic [31 :0] mcu_result2 ; // MCU result 2 + logic [31 :0] mcu_result3 ; // MCU result 3 + + + + //output port + logic [31 :0] mcu_param0 ; // MCU parameter 0 + logic [31 :0] mcu_param1 ; // MCU parameter 1 + logic [31 :0] mcu_param2 ; // MCU parameter 2 + logic [31 :0] mcu_param3 ; // MCU parameter 3 + logic [2 :0] fb_st_o ; + logic mod_sel_sideband ; //1'b0:Upper sideband;1'b1:Lower sideband; + logic qam_nco_clr ; + logic [47 :0] qam_fcw ; + logic [15 :0] qam_pha ; + logic [1 :0] qam_mod ; //2'b00:bypass;2'b01:mix;2'b10:cos;2'b11:sin; + logic qam_sel_sideband ; //1'b0:Upper sideband;1'b1:Lower sideband; + logic [2 :0] intp_mode ; //3'b000:x1;3'b001:x2;3'b010:x4;3'b011:x8;3'b100:x16; + logic [1 :0] intp_sel ; //2'b00:HBF;2'b01:Nearest-neighbor interpolator;2'b10:Median interpolator;2'b00:reserve; + logic [1 :0] dac_mode_sel ; //2'b00:NRZ mode;2'b01:MIX mode;2'b10:2xNRZ mode;2'b00:reserve; + logic tc_bypass ; //1'b0:bypass;1'b1:enable; + logic [31 :0] tcparr0 ; + logic [31 :0] tcparr1 ; + logic [31 :0] tcparr2 ; + logic [31 :0] tcparr3 ; + logic [31 :0] tcparr4 ; + logic [31 :0] tcparr5 ; + logic [31 :0] tcpbrr0 ; + logic [31 :0] tcpbrr1 ; + logic [31 :0] tcpbrr2 ; + logic [31 :0] tcpbrr3 ; + logic [31 :0] tcpbrr4 ; + logic [31 :0] tcpbrr5 ; + logic [31 :0] tcpair0 ; + logic [31 :0] tcpair1 ; + logic [31 :0] tcpair2 ; + logic [31 :0] tcpair3 ; + logic [31 :0] tcpair4 ; + logic [31 :0] tcpair5 ; + logic [31 :0] tcpbir0 ; + logic [31 :0] tcpbir1 ; + logic [31 :0] tcpbir2 ; + logic [31 :0] tcpbir3 ; + logic [31 :0] tcpbir4 ; + logic [31 :0] tcpbir5 ; + + + + + +endinterface : awgreg_if + + + diff --git a/tb/testbench/awgreg_tb/awgreg_monitor.sv b/tb/testbench/awgreg_tb/awgreg_monitor.sv new file mode 100644 index 0000000..d38ef12 --- /dev/null +++ b/tb/testbench/awgreg_tb/awgreg_monitor.sv @@ -0,0 +1,123 @@ +class awgreg_monitor; + + virtual awgreg_if aif; + virtual spi_if wif; + virtual sram_if xif; + + static int pktnum; + + //Collected Vars + awgreg_trans awg_tr[$]; + + + function new(); + endfunction + extern task do_mon(); + extern task collect(); + +endclass : awgreg_monitor + +task awgreg_monitor::do_mon(); + int pkt_i=0; + + fork + + while(1) begin: awgreg_monitor + if(pkt_i==pktnum) break; + if(wif.csn) @(negedge wif.csn); + collect(); + end: awgreg_monitor + + repeat(pktnum) begin: kill_progress + @(negedge wif.csn); + pkt_i++; + end + + join + +endtask: do_mon + + +task awgreg_monitor::collect(); + awgreg_trans awg_tr_temp; + bit[31:0] cmd_temp; + int size=0; + int i=0,j=0; + + for(j=0;j<31;j++) begin + @(posedge wif.sclk or posedge wif.csn) + if(wif.error_check | wif.csn) + break; + cmd_temp[j] = wif.mosi; + end + size = cmd_temp[1] ? 16 : 1; + + awg_tr.delete; + repeat(size) begin + awg_tr_temp = new(); + //if read, sample regfile's input port as exp_data + if(cmd_temp[0]) begin + @(posedge xif.rden); + repeat(1) @(posedge wif.clk); + awg_tr_temp.mcu_result0 = aif.mcu_result0; + awg_tr_temp.mcu_result1 = aif.mcu_result1; + awg_tr_temp.mcu_result2 = aif.mcu_result2; + awg_tr_temp.mcu_result3 = aif.mcu_result3; + awg_tr_temp.fb_st_i = aif.fb_st_i; + awg_tr_temp.run_time = aif.run_time; + awg_tr_temp.instr_num = aif.instr_num; + end + //if write, sample regfile's output port as act_data + else begin + @(posedge xif.wren); + repeat(2) @(posedge wif.clk); + @(negedge wif.clk); + awg_tr_temp.mcu_param0 = aif.mcu_param0 ; + awg_tr_temp.mcu_param1 = aif.mcu_param1 ; + awg_tr_temp.mcu_param2 = aif.mcu_param2 ; + awg_tr_temp.mcu_param3 = aif.mcu_param3 ; + awg_tr_temp.fb_st_o = aif.fb_st_o ; + awg_tr_temp.mod_sel_sideband = aif.mod_sel_sideband; + awg_tr_temp.qam_nco_clr = aif.qam_nco_clr ; + awg_tr_temp.qam_fcw = aif.qam_fcw ; + awg_tr_temp.qam_pha = aif.qam_pha ; + awg_tr_temp.qam_mod = aif.qam_mod ; + awg_tr_temp.qam_sel_sideband = aif.qam_sel_sideband; + awg_tr_temp.intp_mode = aif.intp_mode ; + awg_tr_temp.intp_sel = aif.intp_sel ; + awg_tr_temp.dac_mode_sel = aif.dac_mode_sel ; + awg_tr_temp.tc_bypass = aif.tc_bypass ; + awg_tr_temp.tcparr0 = aif.tcparr0 ; + awg_tr_temp.tcparr1 = aif.tcparr1 ; + awg_tr_temp.tcparr2 = aif.tcparr2 ; + awg_tr_temp.tcparr3 = aif.tcparr3 ; + awg_tr_temp.tcparr4 = aif.tcparr4 ; + awg_tr_temp.tcparr5 = aif.tcparr5 ; + awg_tr_temp.tcpbrr0 = aif.tcpbrr0 ; + awg_tr_temp.tcpbrr1 = aif.tcpbrr1 ; + awg_tr_temp.tcpbrr2 = aif.tcpbrr2 ; + awg_tr_temp.tcpbrr3 = aif.tcpbrr3 ; + awg_tr_temp.tcpbrr4 = aif.tcpbrr4 ; + awg_tr_temp.tcpbrr5 = aif.tcpbrr5 ; + awg_tr_temp.tcpair0 = aif.tcpair0 ; + awg_tr_temp.tcpair1 = aif.tcpair1 ; + awg_tr_temp.tcpair2 = aif.tcpair2 ; + awg_tr_temp.tcpair3 = aif.tcpair3 ; + awg_tr_temp.tcpair4 = aif.tcpair4 ; + awg_tr_temp.tcpair5 = aif.tcpair5 ; + awg_tr_temp.tcpbir0 = aif.tcpbir0 ; + awg_tr_temp.tcpbir1 = aif.tcpbir1 ; + awg_tr_temp.tcpbir2 = aif.tcpbir2 ; + awg_tr_temp.tcpbir3 = aif.tcpbir3 ; + awg_tr_temp.tcpbir4 = aif.tcpbir4 ; + awg_tr_temp.tcpbir5 = aif.tcpbir5 ; + end + awg_tr.push_back(awg_tr_temp); + //$display("one pkt cllct"); + end + + if(cmd_temp[0] & !wif.csn) @(posedge wif.csn); + +endtask + + diff --git a/tb/testbench/awgreg_tb/awgreg_scb.sv b/tb/testbench/awgreg_tb/awgreg_scb.sv new file mode 100644 index 0000000..e1bd9ab --- /dev/null +++ b/tb/testbench/awgreg_tb/awgreg_scb.sv @@ -0,0 +1,600 @@ +class awgreg_scoreboard; + + static int pktnum; + + virtual spi_if wif; + virtual awgreg_if aif; + + bit din[$]; + bit[31:0] dout[$]; + awgreg_trans awg_tr[$]; + + int error=0; + int error_fb=0; + + //FeedBack Static Cache + bit[1:0] fsir; + + + function new(); + endfunction; + + extern function bit compare( + bit din[$], + bit[31:0] dout[$], + awgreg_trans awg_tr[$] + ); + + extern task do_check(); + +endclass: awgreg_scoreboard + + +task awgreg_scoreboard::do_check(); + int pkt_i=0; + + fork + + //awgreg scoreboard + while(1) begin + if(pkt_i==pktnum) break; + @(posedge wif.csn); + repeat(10)@(negedge wif.clk); + if(!compare(din,dout,awg_tr)) + error++; + end + + //Feedback State checker + while(1) begin + if(pkt_i==pktnum) break; + @(posedge wif.clk); + if(aif.fb_st_o != fsir) + error_fb++; + fsir = aif.fb_st_i[1:0]; + end + + + repeat(pktnum) begin: kill_progress + @(negedge wif.csn); + pkt_i++; + end + + join + +endtask + + +function bit awgreg_scoreboard::compare( + bit din[$], + bit[31:0] dout[$], + awgreg_trans awg_tr[$] +); + + bit[31:0] data[$]; + bit[4 :0] chip; + bit[15:0] base; + bit[15:0] addr; + int size; + bit result=1'b1; + int i=0; + +//$display(din); + + chip[ 1: 0] = {>>{din[ 5: 6]}}; + base[15: 0] = {>>{din[11:26]}}; + data = {>>{din[32: $]}}; + size = din[1] ? 16 : 1; + + if(chip != 2'b10) begin + //result = 1'b0; + //$display("ScoreBoard(ERROR): Error chip-select!"); + end + else begin + $display(" "); + + for(i=0;i=16'h00 && addr<=16'h03) begin + if(awg_tr[i].mcu_param0 != data[i]) begin + result = 1'b0; + $display("ScoreBoard(ERROR):"); + $display("\tExp mcu_param0:%b",data[i]); + $display("\tAct mcu_param0:%b",awg_tr[i].mcu_param0); end + else $display("ScoreBoard: MCU_PARA0 register is write successfully!"); + end + + else if(addr>=16'h04 && addr<=16'h07) begin + if(awg_tr[i].mcu_param1 != data[i]) begin + result = 1'b0; + $display("ScoreBoard(ERROR):"); + $display("\tExp mcu_param1:%b",data[i]); + $display("\tAct mcu_param1:%b",awg_tr[i].mcu_param1); end + else $display("ScoreBoard: MCU_PARA1 register is write successfully!"); + end + + else if(addr>=16'h08 && addr<=16'h0B) begin + if(awg_tr[i].mcu_param2 != data[i]) begin + result = 1'b0; + $display("ScoreBoard(ERROR):"); + $display("\tExp mcu_param2:%b",data[i]); + $display("\tAct mcu_param2:%b",awg_tr[i].mcu_param2); end + else $display("ScoreBoard: MCU_PARA2 register is write successfully!"); + end + + else if(addr>=16'h0C && addr<=16'h0F) begin + if(awg_tr[i].mcu_param3 != data[i]) begin + result = 1'b0; + $display("ScoreBoard(ERROR):"); + $display("\tExp mcu_param3:%b",data[i]); + $display("\tAct mcu_param3:%b",awg_tr[i].mcu_param3); end + else $display("ScoreBoard: MCUPARA3 register is write successfully!"); + end + + else if(addr>=16'h100 && addr<=16'h103) begin + if((awg_tr[i].mod_sel_sideband) != data[i][0]) begin + result = 1'b0; + $display("ScoreBoard(ERROR):"); + $display("\tExp mod_sel_sideband:%b",data[i][0]); + $display("\tAct mod_sel_sideband:%b",awg_tr[i].mod_sel_sideband); end + else $display("ScoreBoard: MOD_SEL register is write successfully!"); + end + + else if(addr>=16'h104 && addr<=16'h107) begin + if((awg_tr[i].intp_mode) != data[i][2:0]) begin + result = 1'b0; + $display("ScoreBoard(ERROR):"); + $display("\tExp intp_mode:%b",data[i][2:0]); + $display("\tAct intp_mode:%b",awg_tr[i].intp_mode); end + else $display("ScoreBoard: INTP_MODE register is write successfully!"); + end + + else if(addr>=16'h108 && addr<=16'h10B) begin + if(awg_tr[i].qam_nco_clr != data[i][0]) begin + result = 1'b0; + $display("ScoreBoard(ERROR):"); + $display("\tExp qam_nco_clr:%b",data[i][0]); + $display("\tAct qam_nco_clr:%b",awg_tr[i].qam_nco_clr); end + else $display("ScoreBoard: NCO_CLR register is write successfully!"); + end + + else if(addr>=16'h10C && addr<=16'h10F) begin + if(awg_tr[i].qam_fcw[47:16] != data[i]) begin + result = 1'b0; + $display("ScoreBoard(ERROR):"); + $display("\tExp qam_fcw[47:16]:%b",data[i]); + $display("\tAct qam_fcw[47:16]:%b",awg_tr[i].qam_fcw[47:16]); end + else $display("ScoreBoard: FCW_H32bit register is write successfully!"); + end + + else if(addr>=16'h110 && addr<=16'h113) begin + if(awg_tr[i].qam_fcw[15:0] != data[i][31:16]) begin + result = 1'b0; + $display("ScoreBoard(ERROR):"); + $display("\tExp qam_fcw[15:0]:%b",data[i][31:16]); + $display("\tAct qam_fcw[15:0]:%b",awg_tr[i].qam_fcw[15:0]); end + else $display("ScoreBoard: FCW_L16bit register is write successfully!"); + end + + else if(addr>=16'h114 && addr<=16'h117) begin + if(awg_tr[i].qam_pha != data[i][31:16]) begin + result = 1'b0; + $display("ScoreBoard(ERROR):"); + $display("\tExp qam_pha:%b",data[i][31:16]); + $display("\tAct qam_pha:%b",awg_tr[i].qam_pha); end + else $display("ScoreBoard: PHA register is write successfully!"); + end + + else if(addr>=16'h118 && addr<=16'h11B) begin + if(awg_tr[i].qam_sel_sideband != data[i][0]) begin + result = 1'b0; + $display("ScoreBoard(ERROR):"); + $display("\tExp qam_sel_sideband:%b",data[i][0]); + $display("\tAct qam_sel_sideband:%b",awg_tr[i].qam_sel_sideband); end + else $display("ScoreBoard: QAM_SEL register is write successfully!"); + end + + else if(addr>=16'h11C && addr<=16'h11F) begin + if(awg_tr[i].qam_mod != data[i][1:0]) begin + result = 1'b0; + $display("ScoreBoard(ERROR):"); + $display("\tExp qam_mod:%b",data[i][1:0]); + $display("\tAct qam_mod:%b",awg_tr[i].qam_mod); end + else $display("ScoreBoard: QAM_MOD register is write successfully!"); + end + + else if(addr>=16'h120 && addr<=16'h123) begin + if(awg_tr[i].dac_mode_sel != data[i][1:0]) begin + result = 1'b0; + $display("ScoreBoard(ERROR):"); + $display("\tExp dac_mode_sel:%b",data[i][1:0]); + $display("\tAct dac_mode_sel:%b",awg_tr[i].dac_mode_sel); end + else $display("ScoreBoard: DAC_MOD register is write successfully!"); + end + + else if(addr>=16'h128 && addr<=16'h12B) begin + if(awg_tr[i].intp_sel != data[i][1:0]) begin + result = 1'b0; + $display("ScoreBoard(ERROR):"); + $display("\tExp intp_sel:%b",data[i][1:0]); + $display("\tAct intp_sel:%b",awg_tr[i].intp_sel); end + else $display("ScoreBoard: INTP_SEL register is write successfully!"); + end + + else if(addr>=16'h12C && addr<=16'h12F) begin + if(awg_tr[i].tc_bypass != data[i][0]) begin + result = 1'b0; + $display("ScoreBoard(ERROR):"); + $display("\tExp tc_bypass:%b",data[i][0]); + $display("\tAct tc_bypass:%b",awg_tr[i].tc_bypass); end + else $display("ScoreBoard: TC_BYPASS register is write successfully!"); + end + + else if(addr>=16'h130 && addr<=16'h133) begin + if(awg_tr[i].tcparr0 != data[i]) begin + result = 1'b0; + $display("ScoreBoard(ERROR):"); + $display("\tExp tcparr0:%b",data[i]); + $display("\tAct tcparr0:%b",awg_tr[i].tcparr0); end + else $display("ScoreBoard: TCPA_REAL0 register is write successfully!"); + end + + else if(addr>=16'h134 && addr<=16'h137) begin + if(awg_tr[i].tcparr1 != data[i]) begin + result = 1'b0; + $display("ScoreBoard(ERROR):"); + $display("\tExp tcparr1:%b",data[i]); + $display("\tAct tcparr1:%b",awg_tr[i].tcparr1); end + else $display("ScoreBoard: TCPA_REAL1 register is write successfully!"); + end + + else if(addr>=16'h138 && addr<=16'h13B) begin + if(awg_tr[i].tcparr2 != data[i]) begin + result = 1'b0; + $display("ScoreBoard(ERROR):"); + $display("\tExp tcparr2:%b",data[i]); + $display("\tAct tcparr2:%b",awg_tr[i].tcparr2); end + else $display("ScoreBoard: TCPA_REAL2 register is write successfully!"); + end + + else if(addr>=16'h13C && addr<=16'h13F) begin + if(awg_tr[i].tcparr3 != data[i]) begin + result = 1'b0; + $display("ScoreBoard(ERROR):"); + $display("\tExp tcparr3:%b",data[i]); + $display("\tAct tcparr3:%b",awg_tr[i].tcparr3); end + else $display("ScoreBoard: TCPA_REAL3 register is write successfully!"); + end + + else if(addr>=16'h140 && addr<=16'h143) begin + if(awg_tr[i].tcparr4 != data[i]) begin + result = 1'b0; + $display("ScoreBoard(ERROR):"); + $display("\tExp tcparr4:%b",data[i]); + $display("\tAct tcparr4:%b",awg_tr[i].tcparr4); end + else $display("ScoreBoard: TCPA_REAL4 register is write successfully!"); + end + + else if(addr>=16'h144 && addr<=16'h147) begin + if(awg_tr[i].tcparr5 != data[i]) begin + result = 1'b0; + $display("ScoreBoard(ERROR):"); + $display("\tExp tcparr5:%b",data[i]); + $display("\tAct tcparr5:%b",awg_tr[i].tcparr5); end + else $display("ScoreBoard: TCPA_REAL5 register is write successfully!"); + end + + else if(addr>=16'h148 && addr<=16'h14B) begin + if(awg_tr[i].tcpbrr0 != data[i]) begin + result = 1'b0; + $display("ScoreBoard(ERROR):"); + $display("\tExp tcpbrr0:%b",data[i]); + $display("\tAct tcpbrr0:%b",awg_tr[i].tcpbrr0); end + else $display("ScoreBoard: TCPB_REAL0 register is write successfully!"); + end + + else if(addr>=16'h14C && addr<=16'h14F) begin + if(awg_tr[i].tcpbrr1 != data[i]) begin + result = 1'b0; + $display("ScoreBoard(ERROR):"); + $display("\tExp tcpbrr1:%b",data[i]); + $display("\tAct tcpbrr1:%b",awg_tr[i].tcpbrr1); end + else $display("ScoreBoard: TCPB_REAL1 register is write successfully!"); + end + + else if(addr>=16'h150 && addr<=16'h153) begin + if(awg_tr[i].tcpbrr2 != data[i]) begin + result = 1'b0; + $display("ScoreBoard(ERROR):"); + $display("\tExp tcpbrr2:%b",data[i]); + $display("\tAct tcpbrr2:%b",awg_tr[i].tcpbrr2); end + else $display("ScoreBoard: TCPB_REAL2 register is write successfully!"); + end + + else if(addr>=16'h154 && addr<=16'h157) begin + if(awg_tr[i].tcpbrr3 != data[i]) begin + result = 1'b0; + $display("ScoreBoard(ERROR):"); + $display("\tExp tcpbrr3:%b",data[i]); + $display("\tAct tcpbrr3:%b",awg_tr[i].tcpbrr3); end + else $display("ScoreBoard: TCPB_REAL3 register is write successfully!"); + end + + else if(addr>=16'h158 && addr<=16'h15B) begin + if(awg_tr[i].tcpbrr4 != data[i]) begin + result = 1'b0; + $display("ScoreBoard(ERROR):"); + $display("\tExp tcpbrr4:%b",data[i]); + $display("\tAct tcpbrr4:%b",awg_tr[i].tcpbrr4); end + else $display("ScoreBoard: TCPB_REAL4 register is write successfully!"); + end + + else if(addr>=16'h15C && addr<=16'h15F) begin + if(awg_tr[i].tcpbrr5 != data[i]) begin + result = 1'b0; + $display("ScoreBoard(ERROR):"); + $display("\tExp tcpbrr5:%b",data[i]); + $display("\tAct tcpbrr5:%b",awg_tr[i].tcpbrr5); end + else $display("ScoreBoard: TCPB_REAL5 register is write successfully!"); + end + + else if(addr>=16'h160 && addr<=16'h163) begin + if(awg_tr[i].tcpair0 != data[i]) begin + result = 1'b0; + $display("ScoreBoard(ERROR):"); + $display("\tExp tcpair0:%b",data[i]); + $display("\tAct tcpair0:%b",awg_tr[i].tcpair0); end + else $display("ScoreBoard: TCPA_IMG0 register is write successfully!"); + end + + else if(addr>=16'h164 && addr<=16'h167) begin + if(awg_tr[i].tcpair1 != data[i]) begin + result = 1'b0; + $display("ScoreBoard(ERROR):"); + $display("\tExp tcpair1:%b",data[i]); + $display("\tAct tcpair1:%b",awg_tr[i].tcpair1); end + else $display("ScoreBoard: TCPA_IMG1 register is write successfully!"); + end + + else if(addr>=16'h168 && addr<=16'h16B) begin + if(awg_tr[i].tcpair2 != data[i]) begin + result = 1'b0; + $display("ScoreBoard(ERROR):"); + $display("\tExp tcpair2:%b",data[i]); + $display("\tAct tcpair2:%b",awg_tr[i].tcpair2); end + else $display("ScoreBoard: TCPA_IMG2 register is write successfully!"); + end + + else if(addr>=16'h16C && addr<=16'h16F) begin + if(awg_tr[i].tcpair3 != data[i]) begin + result = 1'b0; + $display("ScoreBoard(ERROR):"); + $display("\tExp tcpair3:%b",data[i]); + $display("\tAct tcpair3:%b",awg_tr[i].tcpair3); end + else $display("ScoreBoard: TCPA_IMG3 register is write successfully!"); + end + + else if(addr>=16'h170 && addr<=16'h173) begin + if(awg_tr[i].tcpair4 != data[i]) begin + result = 1'b0; + $display("ScoreBoard(ERROR):"); + $display("\tExp tcparr4:%b",data[i]); + $display("\tAct tcparr4:%b",awg_tr[i].tcpair4); end + else $display("ScoreBoard: TCPA_IMG4 register is write successfully!"); + end + + else if(addr>=16'h174 && addr<=16'h177) begin + if(awg_tr[i].tcpair5 != data[i]) begin + result = 1'b0; + $display("ScoreBoard(ERROR):"); + $display("\tExp tcpair5:%b",data[i]); + $display("\tAct tcpair5:%b",awg_tr[i].tcpair5); end + else $display("ScoreBoard: TCPA_IMG5 register is write successfully!"); + end + + else if(addr>=16'h178 && addr<=16'h17B) begin + if(awg_tr[i].tcpbir0 != data[i]) begin + result = 1'b0; + $display("ScoreBoard(ERROR):"); + $display("\tExp tcpbir0:%b",data[i]); + $display("\tAct tcpbir0:%b",awg_tr[i].tcpbir0); end + else $display("ScoreBoard: TCPB_IMG0 register is write successfully!"); + end + + else if(addr>=16'h17C && addr<=16'h17F) begin + if(awg_tr[i].tcpbir1 != data[i]) begin + result = 1'b0; + $display("ScoreBoard(ERROR):"); + $display("\tExp tcpbir1:%b",data[i]); + $display("\tAct tcpbir1:%b",awg_tr[i].tcpbir1); end + else $display("ScoreBoard: TCPB_IMG1 register is write successfully!"); + end + + else if(addr>=16'h180 && addr<=16'h183) begin + if(awg_tr[i].tcpbir2 != data[i]) begin + result = 1'b0; + $display("ScoreBoard(ERROR):"); + $display("\tExp tcpbir2:%b",data[i]); + $display("\tAct tcpbir2:%b",awg_tr[i].tcpbir2); end + else $display("ScoreBoard: TCPB_IMG2 register is write successfully!"); + end + + else if(addr>=16'h184 && addr<=16'h187) begin + if(awg_tr[i].tcpbir3 != data[i]) begin + result = 1'b0; + $display("ScoreBoard(ERROR):"); + $display("\tExp tcpbir3:%b",data[i]); + $display("\tAct tcpbir3:%b",awg_tr[i].tcpbir3); end + else $display("ScoreBoard: TCPB_IMG3 register is write successfully!"); + end + + else if(addr>=16'h188 && addr<=16'h18B) begin + if(awg_tr[i].tcpbir4 != data[i]) begin + result = 1'b0; + $display("ScoreBoard(ERROR):"); + $display("\tExp tcpbrr4:%b",data[i]); + $display("\tAct tcpbrr4:%b",awg_tr[i].tcpbir4); end + else $display("ScoreBoard: TCPB_IMG4 register is write successfully!"); + end + + else if(addr>=16'h18C && addr<=16'h18F) begin + if(awg_tr[i].tcpbir5 != data[i]) begin + result = 1'b0; + $display("ScoreBoard(ERROR):"); + $display("\tExp tcpbir5:%b",data[i]); + $display("\tAct tcpbir5:%b",awg_tr[i].tcpbir5); end + else $display("ScoreBoard: TCPB_IMG5 register is write successfully!"); + end + + else if(addr>=16'h010 && addr<=16'h01F || addr>=16'h0A0 && addr<=16'h0A3 || + addr>=16'h098 && addr<=16'h09F) $display("ScoreBoard: read-only register."); + else begin result = 1'b0; $display("ScoreBoard: Error Address!"); end + end + + //if read,COMPARE the "dout" sent by SPI WITH the "tr" collected from regfile's input port or the "data" received last write + else begin + + if(dout.size()!=size | awg_tr.size!=size) begin + result = 1'b0; + $display("ScoreBoard(ERROR): Size ARNT'T equal!"); + $display("Exp size:%0d",awg_tr.size()); + $display("Act size:%0d",dout.size()); + end + + else if(addr>=16'h10 && addr<=16'h13) begin + if(dout[i] != awg_tr[i].mcu_result0) begin + result = 1'b0; + $display("ScoreBoard(ERROR):"); + $display("\tExp mcu_result0:%b",awg_tr[i].mcu_result0); + $display("\tAct mcu_result0:%b",dout[i]); end + else $display("ScoreBoard: awg_PARAM0 register is read successfully!"); + end + + else if(addr>=16'h14 && addr<=16'h17) begin + if(dout[i] != awg_tr[i].mcu_result1) begin + result = 1'b0; + $display("ScoreBoard(ERROR):"); + $display("\tExp mcu_result1:%b",awg_tr[i].mcu_result1); + $display("\tAct mcu_result1:%b",dout[i]); end + else $display("ScoreBoard: awg_PARAM1 register is read successfully!"); + end + + else if(addr>=16'h18 && addr<=16'h1B) begin + if(dout[i] != awg_tr[i].mcu_result2) begin + result = 1'b0; + $display("ScoreBoard(ERROR):"); + $display("\tExp mcu_result2:%b",awg_tr[i].mcu_result2); + $display("\tAct mcu_result2:%b",dout[i]); end + else $display("ScoreBoard: awg_PARAM2 register is read successfully!"); + end + + else if(addr>=16'h1C && addr<=16'h1F) begin + if(dout[i] != awg_tr[i].mcu_result3) begin + result = 1'b0; + $display("ScoreBoard(ERROR):"); + $display("\tExp mcu_result3:%b",awg_tr[i].mcu_result3); + $display("\tAct mcu_result3:%b",dout[i]); end + else $display("ScoreBoard: awg_PARAM2 register is read successfully!"); + end + + else if(addr>=16'h98 && addr<=16'h9B) begin + if(dout[i] != awg_tr[i].run_time) begin + result = 1'b0; + $display("ScoreBoard(ERROR):"); + $display("\tExp run_time:%b",awg_tr[i].run_time); + $display("\tAct run_time:%b",dout[i]); end + else $display("ScoreBoard: RUN_TIME register is read successfully!"); + end + + else if(addr>=16'h9C && addr<=16'h9F) begin + if(dout[i] != awg_tr[i].instr_num) begin + result = 1'b0; + $display("ScoreBoard(ERROR):"); + $display("\tExp instr_num:%b",awg_tr[i].instr_num); + $display("\tAct instr_num:%b",dout[i]); end + else $display("ScoreBoard: INSTR_NUM register is read successfully!"); + end + + else if(addr>=16'hA0 && addr<=16'hA3) begin + if(dout[i][1:0] != awg_tr[i].fb_st_i[1:0]) begin + result = 1'b0; + $display("ScoreBoard(ERROR):"); + $display("\tExp fb_st_i:%b",awg_tr[i].fb_st_i[1:0]); + $display("\tAct fb_st_i:%b",dout[i]); end + else $display("ScoreBoard: FSIR register is read successfully!"); + end + + else if(addr>=16'h000 && addr<=16'h00F || + addr>=16'h10C && addr<=16'h10F || + addr>=16'h130 && addr<=16'h18F) begin + if(dout[i] != data[i]) begin + result = 1'b0; + $display("ScoreBoard(ERROR):"); + $display("\tExp miso:%b",data[i]); + $display("\tAct miso:%b",dout[i]); end + else $display("ScoreBoard: 32bit register is write&read successfully!"); + end + + else if(addr>=16'h110 && addr<=16'h117) begin + if(dout[i][15:0] != data[i][31:16]) begin + result = 1'b0; + $display("ScoreBoard(ERROR):"); + $display("\tExp miso:%b",data[i][31:16]); + $display("\tAct miso:%b",dout[i][15:0]); end + else $display("ScoreBoard: 16bit register is write&read successfully!"); + end + + else if(addr>=16'h104 && addr<=16'h107) begin + if(dout[i][2:0] != data[i][2:0]) begin + result = 1'b0; + $display("ScoreBoard(ERROR):"); + $display("\tExp miso:%b",data[i][2:0]); + $display("\tAct miso:%b",dout[i][2:0]); end + else $display("ScoreBoard: 3bit register is write&read successfully!"); + end + + else if(addr>=16'h11C && addr<=16'h12B) begin + if(dout[i][1:0] != data[i][1:0]) begin + result = 1'b0; + $display("ScoreBoard(ERROR):"); + $display("\tExp miso:%b",data[i][1:0]); + $display("\tAct miso:%b",dout[i][1:0]); end + else $display("ScoreBoard: 2bit register is write&read successfully!"); + end + + else if(addr>=16'h100 && addr<=16'h103 || + addr>=16'h108 && addr<=16'h10B || + addr>=16'h118 && addr<=16'h11B || + addr>=16'h12C && addr<=16'h12F) begin + if(dout[i][0] != data[i][0]) begin + result = 1'b0; + $display("ScoreBoard(ERROR):"); + $display("\tExp miso:%b",data[i][0]); + $display("\tAct miso:%b",dout[i][0]); end + else $display("ScoreBoard: 1bit register is write&read successfully!"); + end + + else begin result = 1'b0; $display("ScoreBoard: Error Address!"); end + end//end_ifelse + end//end_for + $display(""); + end + + return result; + +endfunction: compare + + + diff --git a/tb/testbench/awgreg_tb/awgreg_trans.sv b/tb/testbench/awgreg_tb/awgreg_trans.sv new file mode 100644 index 0000000..ec717e1 --- /dev/null +++ b/tb/testbench/awgreg_tb/awgreg_trans.sv @@ -0,0 +1,95 @@ +class awgreg_trans; + + rand bit[2 :0] fb_st_i ; + rand bit[31 :0] run_time ; + rand bit[31 :0] instr_num ; + rand bit[31 :0] mcu_result0 ; // MCU result 0 + rand bit[31 :0] mcu_result1 ; // MCU result 1 + rand bit[31 :0] mcu_result2 ; // MCU result 2 + rand bit[31 :0] mcu_result3 ; // MCU result 3 + + rand bit[31 :0] fb_st_i_time ; + rand bit[31 :0] run_time_time ; + rand bit[31 :0] instr_num_time ; + rand bit[31 :0] mcu_result0_time ; // MCU result 0 + rand bit[31 :0] mcu_result1_time ; // MCU result 1 + rand bit[31 :0] mcu_result2_time ; // MCU result 2 + rand bit[31 :0] mcu_result3_time ; // MCU result 3 + + + + //output port + rand bit[31 :0] mcu_param0 ; // MCU parameter 0 + rand bit[31 :0] mcu_param1 ; // MCU parameter 1 + rand bit[31 :0] mcu_param2 ; // MCU parameter 2 + rand bit[31 :0] mcu_param3 ; // MCU parameter 3 + rand bit[2 :0] fb_st_o ; + rand bit mod_sel_sideband ; //1'b0:Upper sideband;1'b1:Lower sideband; + rand bit qam_nco_clr ; + rand bit[47 :0] qam_fcw ; + rand bit[15 :0] qam_pha ; + rand bit[1 :0] qam_mod ; //2'b00:bypass;2'b01:mix;2'b10:cos;2'b11:sin; + rand bit qam_sel_sideband ; //1'b0:Upper sideband;1'b1:Lower sideband; + rand bit[2 :0] intp_mode ; //3'b000:x1;3'b001:x2;3'b010:x4;3'b011:x8;3'b100:x16; + rand bit[1 :0] intp_sel ; //2'b00:HBF;2'b01:Nearest-neighbor interpolator;2'b10:Median interpolator;2'b00:reserve; + rand bit[1 :0] dac_mode_sel ; //2'b00:NRZ mode;2'b01:MIX mode;2'b10:2xNRZ mode;2'b00:reserve; + rand bit tc_bypass ; //1'b0:bypass;1'b1:enable; + rand bit[31 :0] tcparr0 ; + rand bit[31 :0] tcparr1 ; + rand bit[31 :0] tcparr2 ; + rand bit[31 :0] tcparr3 ; + rand bit[31 :0] tcparr4 ; + rand bit[31 :0] tcparr5 ; + rand bit[31 :0] tcpbrr0 ; + rand bit[31 :0] tcpbrr1 ; + rand bit[31 :0] tcpbrr2 ; + rand bit[31 :0] tcpbrr3 ; + rand bit[31 :0] tcpbrr4 ; + rand bit[31 :0] tcpbrr5 ; + rand bit[31 :0] tcpair0 ; + rand bit[31 :0] tcpair1 ; + rand bit[31 :0] tcpair2 ; + rand bit[31 :0] tcpair3 ; + rand bit[31 :0] tcpair4 ; + rand bit[31 :0] tcpair5 ; + rand bit[31 :0] tcpbir0 ; + rand bit[31 :0] tcpbir1 ; + rand bit[31 :0] tcpbir2 ; + rand bit[31 :0] tcpbir3 ; + rand bit[31 :0] tcpbir4 ; + rand bit[31 :0] tcpbir5 ; + + +constraint cstr { + fb_st_i_time >= 0 ; + run_time_time >= 0 ; + instr_num_time >= 0 ; + mcu_result0_time >= 0 ; + mcu_result1_time >= 0 ; + mcu_result2_time >= 0 ; + mcu_result3_time >= 0 ; + fb_st_i_time <= 2000 ; + run_time_time <= 2000 ; + instr_num_time <= 2000 ; + mcu_result0_time <= 2000 ; + mcu_result1_time <= 2000 ; + mcu_result2_time <= 2000 ; + mcu_result3_time <= 2000 ; +} + + function new(); + endfunction + +endclass : awgreg_trans + + + + + + + + + + + + diff --git a/tb/testbench/awgreg_tb/case5.sv b/tb/testbench/awgreg_tb/case5.sv new file mode 100644 index 0000000..8776ad4 --- /dev/null +++ b/tb/testbench/awgreg_tb/case5.sv @@ -0,0 +1,26 @@ +//Sclk frequency is randomized +//pkrnum is randomized +//without error-drv +//interval time between 2 pkt is randomized +program case5(spi_if my_if,awgreg_if awg_if,sram_if xif); + + awgreg_env my_env; + + initial begin + + my_env = new(); + + my_env.wif = my_if; + my_env.aif = awg_if; + my_env.xif = xif; + my_env.pktnum = 1000; + + my_env.build(); + + my_env.run(); + + end + +endprogram + + diff --git a/tb/testbench/case6.sv b/tb/testbench/case6.sv new file mode 100644 index 0000000..f241781 --- /dev/null +++ b/tb/testbench/case6.sv @@ -0,0 +1,25 @@ + +program case6(spi_if my_if,sysreg_if sys_if,mcureg_if mcu_if,awgreg_if awg_if,sram_if xif); + + env my_env; + + initial begin + + my_env = new(); + + my_env.wif = my_if; + my_env.vif = sys_if; + my_env.mif = mcu_if; + my_env.aif = awg_if; + my_env.xif = xif; + my_env.pktnum = 1000; + + my_env.build(); + + my_env.run(); + + end + +endprogram + + diff --git a/tb/testbench/env.sv b/tb/testbench/env.sv new file mode 100644 index 0000000..4d702bb --- /dev/null +++ b/tb/testbench/env.sv @@ -0,0 +1,165 @@ +class env; + + + static int pktnum; + + //Interface: + virtual spi_if wif; + virtual sysreg_if vif; + virtual awgreg_if aif; + virtual mcureg_if mif; + virtual sram_if xif; + + //Component: + spi_driver w_driver; + spi_monitor w_monitor; + + sysreg_driver s_driver; + spi2sysreg_refmodel s_mdl; + sysreg_scoreboard s_scb; + + mcureg_driver m_driver; + mcureg_monitor m_monitor; + mcureg_scoreboard m_scb; + + awgreg_driver a_driver; + awgreg_monitor a_monitor; + awgreg_scoreboard a_scb; + + function new(); + endfunction; + + extern function build(); + + extern task run(); + +endclass: env + +function env::build(); + + w_driver = new(); + if(!w_driver.randomize() with { + error_time == 0; + }) + $fatal(0,"Randomize Failed"); + w_driver.pktnum = pktnum; + w_driver.vif = wif; + w_driver.autarchy = 1'b0; + //my_driver.half_sclk = 16; + + w_monitor=new(); + w_monitor.pktnum = pktnum; + w_monitor.wif = wif; + w_monitor.xif = xif; + + s_driver = new(); + s_driver.pktnum = pktnum; + s_driver.vif = vif; + s_driver.wif = wif; + + s_mdl=new(); + s_mdl.pktnum = pktnum; + s_mdl.vif = vif; + s_mdl.wif = wif; + s_mdl.xif = xif; + + s_scb=new(); + s_scb.pktnum = pktnum; + s_scb.wif = wif; + + m_driver = new(); + m_driver.pktnum = pktnum; + m_driver.mif = mif; + m_driver.wif = wif; + + m_monitor = new(); + m_monitor.pktnum = pktnum; + m_monitor.mif = mif; + m_monitor.wif = wif; + m_monitor.xif = xif; + + m_scb = new(); + m_scb.pktnum = pktnum; + m_scb.mif = mif; + m_scb.wif = wif; + m_scb.xif = xif; + + a_driver = new(); + a_driver.pktnum = pktnum; + a_driver.aif = aif; + a_driver.wif = wif; + + a_monitor = new(); + a_monitor.pktnum = pktnum; + a_monitor.aif = aif; + a_monitor.wif = wif; + a_monitor.xif = xif; + + a_scb = new(); + a_scb.pktnum = pktnum; + a_scb.aif = aif; + a_scb.wif = wif; + +endfunction + + +task env::run(); + int pkt_i=0; + + fork + + w_driver.do_drive(); + s_driver.do_drive(); + m_driver.do_drive(); + a_driver.do_drive(); + + + w_monitor.do_mon(); + s_mdl.do_imitate(); + m_monitor.do_mon(); + a_monitor.do_mon(); + + + s_scb.do_check(); + m_scb.do_check(); + a_scb.do_check(); + + + while(1) begin: scb + if(pkt_i==pktnum) break; + @(posedge wif.csn); + repeat(9) @(negedge wif.clk); + a_scb.din = w_monitor.din; + a_scb.dout = w_monitor.dout; + a_scb.awg_tr = a_monitor.awg_tr; + m_scb.din = w_monitor.din; + m_scb.dout= w_monitor.dout; + m_scb.mcu_tr=m_monitor.mcu_tr; + s_scb.my_din = w_monitor.din; + s_scb.my_dout = w_monitor.dout; + s_scb.my_isr = s_mdl.isr; + s_scb.my_imr = s_mdl.imr; + end + + repeat(pktnum) begin: kill_progress + @(negedge wif.csn); + pkt_i++; + end + + join + + $display("SCOREBOARD:"); + $display("SYSTEM_REGFILE:"); + $display("\tError_isr:\t%0d",s_scb.isr_error); + $display("\tError_sysrst:\t%0d",s_mdl.rst_error[0]); + $display("\tError_mcurst:\t%0d",s_mdl.rst_error[1]); + $display("\tError_awgrst:\t%0d",s_mdl.rst_error[2]); + $display("\tError_dacrst:\t%0d",s_mdl.rst_error[3]); + $display("MCU_REGFILE:"); + $display("\tError:\t\t%0d",m_scb.error); + $display("AWG_REGFILE:"); + $display("\tError:\t\t%0d",a_scb.error); + $display("\tError_FB:\t%0d",a_scb.error_fb); + +endtask + diff --git a/tb/testbench/files.f b/tb/testbench/files.f new file mode 100644 index 0000000..01fbf48 --- /dev/null +++ b/tb/testbench/files.f @@ -0,0 +1,35 @@ +./rtl/spram_model_0.v +./rtl/spi_to_sram.v +./rtl/spi_slave.v +./rtl/sram_if.sv +./rtl/sirv_gnrl_xchecker.v +./rtl/sirv_gnrl_dffs.v +./rtl/spi_bus_decoder.sv +./rtl/system_regfile.v +./rtl/awg_regfile.v +./rtl/mcu_regfile.v +./spi_if.sv +./spi_trans.sv +./spi_driver.sv +./sysreg_if.sv +./mcureg_if.sv +./awgreg_if.sv +./sysreg_trans.sv +./mcureg_trans.sv +./awgreg_trans.sv +./sysreg_driver.sv +./mcureg_driver.sv +./awgreg_driver.sv +./spi_monitor.sv +./sysreg_monitor.sv +./mcureg_monitor.sv +./awgreg_monitor.sv +./sysreg_scb.sv +./sysreg_env.sv +./mcureg_scb.sv +./mcureg_env.sv +./awgreg_scb.sv +./awgreg_env.sv +./env.sv +./case6.sv +./tb.sv diff --git a/tb/testbench/mcureg_tb/case4.sv b/tb/testbench/mcureg_tb/case4.sv new file mode 100644 index 0000000..8a5ab50 --- /dev/null +++ b/tb/testbench/mcureg_tb/case4.sv @@ -0,0 +1,25 @@ +//Sclk frequency is randomized +//pkrnum is randomized +//without error-drv +//interval time between 2 pkt is randomized +program case4(spi_if my_if,mcureg_if mcu_if,sram_if xif); + + mcureg_env my_env; + + initial begin + + my_env = new(); + my_env.mif = mcu_if; + my_env.wif = my_if; + my_env.xif = xif; + my_env.pktnum = 1000; + + my_env.build(); + + my_env.run(); + + end + +endprogram + + diff --git a/tb/testbench/mcureg_tb/mcureg_driver.sv b/tb/testbench/mcureg_tb/mcureg_driver.sv new file mode 100644 index 0000000..5c65a45 --- /dev/null +++ b/tb/testbench/mcureg_tb/mcureg_driver.sv @@ -0,0 +1,81 @@ +class mcureg_driver; + + + mcureg_trans tr; + + //interface + virtual mcureg_if mif; + virtual spi_if wif; + + int pktnum; + + + function new(); + endfunction + extern task do_drive(); + extern task make_pkt(); + +endclass : mcureg_driver + +task mcureg_driver::do_drive(); + int pkt_i = 0; + + mif.fb_st_info = 2'b0 ; + mif.run_time = 32'b0 ; + mif.instr_num = 32'b0 ; + mif.mcu_param[3:0] = {32'b0,32'b0,32'b0,32'b0} ; + + fork + while(1) begin + if(pkt_i == pktnum) break; + make_pkt(); + end + + repeat(pktnum) begin: kill_progress + @(negedge wif.csn); + pkt_i++; + end + join + + +endtask + +task mcureg_driver::make_pkt(); + int cnt=0; + + cnt = 0; + + + tr = new(); + if(!tr.randomize()) + $fatal(0,"Randomize Failed"); + + while(cnt<2000) begin + @(posedge wif.clk); + + cnt = cnt + 1; + + case(cnt) + tr.wrmask_time: + mif.wrmask <= tr.wrmask; + tr.fb_st_info_time: + mif.fb_st_info <= tr.fb_st_info; + tr.run_time_time: + mif.run_time <= tr.run_time; + tr.instr_num_time: + mif.instr_num <= tr.instr_num; + tr.mcu_param_time[0]: + mif.mcu_param[0] <= tr.mcu_param[0]; + tr.mcu_param_time[1]: + mif.mcu_param[1] <= tr.mcu_param[1]; + tr.mcu_param_time[2]: + mif.mcu_param[2] <= tr.mcu_param[2]; + tr.mcu_param_time[3]: + mif.mcu_param[3] <= tr.mcu_param[3];//*/ + endcase + + end + + +endtask : make_pkt + diff --git a/tb/testbench/mcureg_tb/mcureg_env.sv b/tb/testbench/mcureg_tb/mcureg_env.sv new file mode 100644 index 0000000..f5e3342 --- /dev/null +++ b/tb/testbench/mcureg_tb/mcureg_env.sv @@ -0,0 +1,95 @@ +class mcureg_env; + + static int pktnum; + + virtual spi_if wif; + virtual mcureg_if mif; + virtual sram_if xif; + + spi_driver w_driver; + mcureg_driver m_driver; + spi_monitor w_monitor; + mcureg_monitor m_monitor; + mcureg_scoreboard m_scb; + + function new(); + endfunction; + + extern function build(); + + extern task run(); + +endclass: mcureg_env + +function mcureg_env::build(); + + w_driver = new(); + if(!w_driver.randomize() with {error_time == 0;}) + $fatal(0,"Randomize Failed"); + w_driver.pktnum = pktnum; + w_driver.vif = wif; + w_driver.autarchy = 1'b0; + //w_driver.half_sclk = 16; + + m_driver = new(); + m_driver.pktnum = pktnum; + m_driver.mif = mif; + m_driver.wif = wif; + + m_monitor = new(); + m_monitor.pktnum = pktnum; + m_monitor.mif = mif; + m_monitor.wif = wif; + m_monitor.xif = xif; + + w_monitor = new(); + w_monitor.pktnum = pktnum; + w_monitor.wif = wif; + w_monitor.xif = xif; + + m_scb = new(); + m_scb.pktnum = pktnum; + m_scb.mif = mif; + m_scb.wif = wif; + m_scb.xif = xif; + +endfunction: build + +task mcureg_env::run(); + int pkt_i=0; + + + fork + + w_driver.do_drive(); + + m_driver.do_drive(); + + w_monitor.do_mon(); + + m_monitor.do_mon(); + + m_scb.do_check(); + + //Port: Monitor2Scoreboard + while(1) begin + if(pkt_i==pktnum) break; + @(posedge wif.csn); + repeat(9) @(negedge wif.clk); + m_scb.din = w_monitor.din; + m_scb.dout= w_monitor.dout; + m_scb.mcu_tr=m_monitor.mcu_tr; + end + + repeat(pktnum) begin: kill_progress + @(negedge wif.csn); + pkt_i++; + end + + join + + $display("SCOREBOARD:"); + $display("\tError:\t%0d",m_scb.error); + +endtask + diff --git a/tb/testbench/mcureg_tb/mcureg_if.sv b/tb/testbench/mcureg_tb/mcureg_if.sv new file mode 100644 index 0000000..3db56bd --- /dev/null +++ b/tb/testbench/mcureg_tb/mcureg_if.sv @@ -0,0 +1,28 @@ + + +interface mcureg_if(input clk,input rstn); + + //input port + logic [3 :0] wrmask ; + logic [2 :0] fb_st_info ; + logic [31 :0] run_time ; + logic [31 :0] instr_num ; + logic [31 :0] mcu_param [3:0] ; // MCU parameter 0~3 + + //output port + logic [31 :0] mcu_result [3:0] ; // MCU result 0~3 + logic [31 :0] mcu_cwfr [3:0] ; // Carrier frequency ctrl word 0~3 + logic [31 :0] mcu_gapr [7:0] ; // Carrier phase ctrl word 0~3 + logic [31 :0] mcu_ampr [3:0] ; // Carrier Amplitude 0~3 + logic [31 :0] mcu_baisr [3:0] ; // Carrier Bais 0~3 + logic [1 :0] mcu_intp_sel ; //2'b00:HBF;2'b01:Nearest-neighbor interpolator; + logic mcu_nco_pha_clr ; + logic [15 :0] mcu_rz_pha ; + + + + +endinterface : mcureg_if + + + diff --git a/tb/testbench/mcureg_tb/mcureg_monitor.sv b/tb/testbench/mcureg_tb/mcureg_monitor.sv new file mode 100644 index 0000000..4175061 --- /dev/null +++ b/tb/testbench/mcureg_tb/mcureg_monitor.sv @@ -0,0 +1,109 @@ +class mcureg_monitor; + + virtual mcureg_if mif; + virtual spi_if wif; + virtual sram_if xif; + + static int pktnum; + + //Mask Cache + bit[3 :0] mask_temp[$]; + + //Collected Vars + mcureg_trans mcu_tr[$]; + + + function new(); + endfunction + extern task do_mon(); + extern task collect(); + +endclass : mcureg_monitor + +task mcureg_monitor::do_mon(); + int pkt_i=0; + + fork + + while(1) begin: mcureg_monitor + if(pkt_i==pktnum) break; + if(wif.csn) @(negedge wif.csn); + collect(); + end: mcureg_monitor + + repeat(pktnum) begin: kill_progress + @(negedge wif.csn); + pkt_i++; + end + + join + +endtask: do_mon + + +task mcureg_monitor::collect(); + mcureg_trans mcu_tr_temp; + bit[31:0] cmd_temp; + int size=0; + int i=0,j=0; + + for(j=0;j<31;j++) begin + @(posedge wif.sclk or posedge wif.csn) + if(wif.error_check | wif.csn) + break; + cmd_temp[j] = wif.mosi; + end + size = cmd_temp[1] ? 16 : 1; + + mcu_tr.delete; + j=0; + repeat(size) begin + + mcu_tr_temp = new(); + + //if read, collect regfile's input port as exp_data + //act_data is monitored by spi_monitor(MISO) + if(cmd_temp[0]) begin: mcureg_in_monitor + //get the "mask" @ the last write_enable + //because registers update "mask" only @ "wren" + mcu_tr_temp.wrmask = mask_temp[j]; + @(posedge xif.rden); + repeat(1) @(posedge wif.clk); + mcu_tr_temp.mcu_param = mif.mcu_param; + mcu_tr_temp.run_time = mif.run_time; + mcu_tr_temp.instr_num = mif.instr_num; + mcu_tr_temp.fb_st_info = mif.fb_st_info; + end: mcureg_in_monitor + + //if write, collect regfile's output port as act_data + //exp_data is monitored by spi_monitor(MOSI) + else begin: mcureg_out_monitor + @(posedge xif.wren); + repeat(2) @(posedge wif.clk); + mcu_tr_temp.wrmask = mif.wrmask; + mask_temp[j] = mif.wrmask; + //wait half_clk to sample output port,for stability + @(negedge wif.clk); + mcu_tr_temp.mcu_result = mif.mcu_result; + mcu_tr_temp.mcu_cwfr = mif.mcu_cwfr; + mcu_tr_temp.mcu_gapr = mif.mcu_gapr; + mcu_tr_temp.mcu_ampr = mif.mcu_ampr; + mcu_tr_temp.mcu_baisr = mif.mcu_baisr; + mcu_tr_temp.mcu_intp_sel = mif.mcu_intp_sel; + mcu_tr_temp.mcu_nco_pha_clr = mif.mcu_nco_pha_clr; + mcu_tr_temp.mcu_rz_pha = mif.mcu_rz_pha; + end: mcureg_out_monitor + + mcu_tr.push_back(mcu_tr_temp); + j++; + //$display("cmd:%0d",cmd_temp[0]); + //$display("size:%0d",size); + //$display("mcu_param[0]:%d",mcu_tr_temp.mcu_param[0]); + //$display("wrmask:%0d",mcu_tr_temp.wrmask); + end + + if(cmd_temp[0] & !wif.csn) @(posedge wif.csn); + +endtask + + diff --git a/tb/testbench/mcureg_tb/mcureg_scb.sv b/tb/testbench/mcureg_tb/mcureg_scb.sv new file mode 100644 index 0000000..e9f4839 --- /dev/null +++ b/tb/testbench/mcureg_tb/mcureg_scb.sv @@ -0,0 +1,471 @@ +class mcureg_scoreboard; + + static int pktnum; + + virtual spi_if wif; + virtual mcureg_if mif; + virtual sram_if xif; + + bit din[$]; + bit[31:0] dout[$]; + mcureg_trans mcu_tr[$]; + + int error=0; + + function new(); + endfunction; + + extern function bit compare( + bit din[$], + bit[31:0] dout[$], + mcureg_trans mcu_tr[$] + ); + + extern task do_check(); + +endclass: mcureg_scoreboard + + +task mcureg_scoreboard::do_check(); + int pkt_i; + int i=0,j=0; + + fork + + //mcureg_scoreboard + while(1) begin: scb + if(pkt_i==pktnum) break; + @(posedge wif.csn); + repeat(10)@(negedge wif.clk); + if(!compare(din,dout,mcu_tr)) + error++; + end: scb + + repeat(pktnum) begin: kill_progress + @(negedge wif.csn); + pkt_i++; + end: kill_progress + + join + +endtask: do_check + + +function bit mcureg_scoreboard::compare( + bit din[$], + bit[31:0] dout[$], + mcureg_trans mcu_tr[$] +); + + bit[31:0] data[$]; + bit[4 :0] chip; + bit[15:0] base; + bit[15:0] addr; + bit[31:0] mask[$]; + int size; + bit result=1'b1; + int i=0; + +//$display(din); + + chip[1 : 0] = {>>{din[ 5: 6]}}; + base[15: 0] = {>>{din[11:26]}}; + data = {>>{din[32: $]}}; + size = din[1] ? 16 : 1; + + if(chip != 2'b1) begin + //result = 1'b0; + //$display("ScoreBoard(ERROR): Error chip-select!"); + end + else begin + $display(" "); + + for(i=0;i=16'h10 && addr<=16'h13) begin + if((mcu_tr[i].mcu_result[0] & mask[i]) != (data[i] & mask[i])) begin + result = 1'b0; + $display("ScoreBoard(ERROR):"); + $display("\tExp mcu_res0:%b",data[i]); + $display("\tAct mcu_res0:%b",mcu_tr[i].mcu_result[0]); end + else $display("ScoreBoard: MCU_RES0 register is write successfully!"); + end + + else if(addr>=16'h14 && addr<=16'h17) begin + if((mcu_tr[i].mcu_result[1] & mask[i]) != (data[i] & mask[i])) begin + result = 1'b0; + $display("ScoreBoard(ERROR):"); + $display("\tExp mcu_res1:%b",data[i]); + $display("\tAct mcu_res1:%b",mcu_tr[i].mcu_result[1]); end + else $display("ScoreBoard: MCU_RES1 register is write successfully!"); + end + + else if(addr>=16'h18 && addr<=16'h1B) begin + if((mcu_tr[i].mcu_result[2] & mask[i]) != (data[i] & mask[i])) begin + result = 1'b0; + $display("ScoreBoard(ERROR):"); + $display("\tExp mcu_res2:%b",data[i]); + $display("\tAct mcu_res2:%b",mcu_tr[i].mcu_result[2]); end + else $display("ScoreBoard: MCU_RES2 register is write successfully!"); + end + + else if(addr>=16'h1C && addr<=16'h1F) begin + if((mcu_tr[i].mcu_result[3] & mask[i]) != (data[i] & mask[i])) begin + result = 1'b0; + $display("ScoreBoard(ERROR):"); + $display("\tExp mcu_res3:%b",data[i]); + $display("\tAct mcu_res3:%b",mcu_tr[i].mcu_result[3]); end + else $display("ScoreBoard: MCU_RES3 register is write successfully!"); + end + + else if(addr>=16'h40 && addr<=16'h43) begin + if((mcu_tr[i].mcu_cwfr[0] & mask[i]) != (data[i] & mask[i])) begin + result = 1'b0; + $display("ScoreBoard(ERROR):"); + $display("\tExp mcu_cwfr0:%b",data[i]); + $display("\tAct mcu_cwfr0:%b",mcu_tr[i].mcu_cwfr[0]); end + else $display("ScoreBoard: MCU_CWFR0 register is write successfully!"); + end + + else if(addr>=16'h44 && addr<=16'h47) begin + if((mcu_tr[i].mcu_cwfr[1] & mask[i]) != (data[i] & mask[i])) begin + result = 1'b0; + $display("ScoreBoard(ERROR):"); + $display("\tExp mcu_cwfr1:%b",data[i]); + $display("\tAct mcu_cwfr1:%b",mcu_tr[i].mcu_cwfr[1]); end + else $display("ScoreBoard: MCU_CWFR1 register is write successfully!"); + end + + else if(addr>=16'h48 && addr<=16'h4B) begin + if((mcu_tr[i].mcu_cwfr[2] & mask[i]) != (data[i] & mask[i])) begin + result = 1'b0; + $display("ScoreBoard(ERROR):"); + $display("\tExp mcu_cwfr2:%b",data[i]); + $display("\tAct mcu_cwfr2:%b",mcu_tr[i].mcu_cwfr[2]); end + else $display("ScoreBoard: MCU_CWFR2 register is write successfully!"); + end + + else if(addr>=16'h4C && addr<=16'h4F) begin + if((mcu_tr[i].mcu_cwfr[3] & mask[i]) != (data[i] & mask[i])) begin + result = 1'b0; + $display("ScoreBoard(ERROR):"); + $display("\tExp mcu_cwfr3:%b",data[i]); + $display("\tAct mcu_cwfr3:%b",mcu_tr[i].mcu_cwfr[3]); end + else $display("ScoreBoard: MCU_CWFR3 register is write successfully!"); + end + + else if(addr>=16'h54 && addr<=16'h57) begin + if((mcu_tr[i].mcu_gapr[0][15:0] & mask[i][31:16]) != (data[i][31:16] & mask[i][31:16])) begin + result = 1'b0; + $display("ScoreBoard(ERROR):"); + $display("\tExp mcu_gapr0:%b",data[i][31:16]); + $display("\tAct mcu_gapr0:%b",mcu_tr[i].mcu_gapr[0][15:0]); end + else $display("ScoreBoard: MCU_GAPR0 register is write successfully!"); + end + + else if(addr>=16'h58 && addr<=16'h5B) begin + if((mcu_tr[i].mcu_gapr[1][15:0] & mask[i][31:16]) != (data[i][31:16] & mask[i][31:16])) begin + result = 1'b0; + $display("ScoreBoard(ERROR):"); + $display("\tExp mcu_gapr1:%b",data[i][31:16]); + $display("\tAct mcu_gapr1:%b",mcu_tr[i].mcu_gapr[1][15:0]); end + else $display("ScoreBoard: MCU_GAPR1 register is write successfully!"); + end + + else if(addr>=16'h5C && addr<=16'h5F) begin + if((mcu_tr[i].mcu_gapr[2][15:0] & mask[i][31:16]) != (data[i][31:16] & mask[i][31:16])) begin + result = 1'b0; + $display("ScoreBoard(ERROR):"); + $display("\tExp mcu_gapr2:%b",data[i][31:16]); + $display("\tAct mcu_gapr2:%b",mcu_tr[i].mcu_gapr[2][15:0]); end + else $display("ScoreBoard: MCU_GAPR2 register is write successfully!"); + end + + else if(addr>=16'h60 && addr<=16'h63) begin + if((mcu_tr[i].mcu_gapr[3][15:0] & mask[i][31:16]) != (data[i][31:16] & mask[i][31:16])) begin + result = 1'b0; + $display("ScoreBoard(ERROR):"); + $display("\tExp mcu_gapr3:%b",data[i][31:16]); + $display("\tAct mcu_gapr3:%b",mcu_tr[i].mcu_gapr[3][15:0]); end + else $display("ScoreBoard: MCU_GAPR3 register is write successfully!"); + end + + else if(addr>=16'h64 && addr<=16'h67) begin + if((mcu_tr[i].mcu_gapr[4][15:0] & mask[i][31:16]) != (data[i][31:16] & mask[i][31:16])) begin + result = 1'b0; + $display("ScoreBoard(ERROR):"); + $display("\tExp mcu_gapr4:%b",data[i][31:16]); + $display("\tAct mcu_gapr4:%b",mcu_tr[i].mcu_gapr[4][15:0]); end + else $display("ScoreBoard: MCU_GAPR4 register is write successfully!"); + end + + else if(addr>=16'h68 && addr<=16'h6B) begin + if((mcu_tr[i].mcu_gapr[5][15:0] & mask[i][31:16]) != (data[i][31:16] & mask[i][31:16])) begin + result = 1'b0; + $display("ScoreBoard(ERROR):"); + $display("\tExp mcu_gapr5:%b",data[i][31:16]); + $display("\tAct mcu_gapr5:%b",mcu_tr[i].mcu_gapr[5][15:0]); end + else $display("ScoreBoard: MCU_GAPR5 register is write successfully!"); + end + + else if(addr>=16'h6C && addr<=16'h6F) begin + if((mcu_tr[i].mcu_gapr[6][15:0] & mask[i][31:16]) != (data[i][31:16] & mask[i][31:16])) begin + result = 1'b0; + $display("ScoreBoard(ERROR):"); + $display("\tExp mcu_gapr6:%b",data[i][31:16]); + $display("\tAct mcu_gapr6:%b",mcu_tr[i].mcu_gapr[6][15:0]); end + else $display("ScoreBoard: MCU_GAPR6 register is write successfully!"); + end + + else if(addr>=16'h70 && addr<=16'h73) begin + if((mcu_tr[i].mcu_gapr[7][15:0] & mask[i][31:16]) != (data[i][31:16] & mask[i][31:16])) begin + result = 1'b0; + $display("ScoreBoard(ERROR):"); + $display("\tExp mcu_gapr7:%b",data[i][31:16]); + $display("\tAct mcu_gapr7:%b",mcu_tr[i].mcu_gapr[7][15:0]); end + else $display("ScoreBoard: MCU_GAPR7 register is write successfully!"); + end + + else if(addr>=16'h78 && addr<=16'h7B) begin + if((mcu_tr[i].mcu_ampr[0][15:0] & mask[i][31:16]) != (data[i][31:16] & mask[i][31:16])) begin + result = 1'b0; + $display("ScoreBoard(ERROR):"); + $display("\tExp mcu_ampr0:%b",data[i][31:16]); + $display("\tAct mcu_ampr0:%b",mcu_tr[i].mcu_ampr[0][15:0]); end + else $display("ScoreBoard: MCU_AMPR0 register is write successfully!"); + end + + else if(addr>=16'h7C && addr<=16'h7F) begin + if((mcu_tr[i].mcu_ampr[1][15:0] & mask[i][31:16]) != (data[i][31:16] & mask[i][31:16])) begin + result = 1'b0; + $display("ScoreBoard(ERROR):"); + $display("\tExp mcu_ampr1:%b",data[i][31:16]); + $display("\tAct mcu_ampr1:%b",mcu_tr[i].mcu_ampr[1][15:0]); end + else $display("ScoreBoard: MCU_AMPR1 register is write successfully!"); + end + + else if(addr>=16'h80 && addr<=16'h83) begin + if((mcu_tr[i].mcu_ampr[2][15:0] & mask[i][31:16]) != (data[i][31:16] & mask[i][31:16])) begin + result = 1'b0; + $display("ScoreBoard(ERROR):"); + $display("\tExp mcu_ampr2:%b",data[i][31:16]); + $display("\tAct mcu_ampr2:%b",mcu_tr[i].mcu_ampr[2][15:0]); end + else $display("ScoreBoard: MCU_AMPR2 register is write successfully!"); + end + + else if(addr>=16'h84 && addr<=16'h87) begin + if((mcu_tr[i].mcu_ampr[3][15:0] & mask[i][31:16]) != (data[i][31:16] & mask[i][31:16])) begin + result = 1'b0; + $display("ScoreBoard(ERROR):"); + $display("\tExp mcu_ampr3:%b",data[i][31:16]); + $display("\tAct mcu_ampr3:%b",mcu_tr[i].mcu_ampr[3][15:0]); end + else $display("ScoreBoard: MCU_AMPR3 register is write successfully!"); + end + + else if(addr>=16'h88 && addr<=16'h8B) begin + if((mcu_tr[i].mcu_baisr[0][15:0] & mask[i][31:16]) != (data[i][31:16] & mask[i][31:16])) begin + result = 1'b0; + $display("ScoreBoard(ERROR):"); + $display("\tExp mcu_baisr0:%b",data[i][31:16]); + $display("\tAct mcu_baisr0:%b",mcu_tr[i].mcu_baisr[0][15:0]); end + else $display("ScoreBoard: MCU_BAIS0 register is write successfully!"); + end + + else if(addr>=16'h8C && addr<=16'h8F) begin + if((mcu_tr[i].mcu_baisr[1][15:0] & mask[i][31:16]) != (data[i][31:16] & mask[i][31:16])) begin + result = 1'b0; + $display("ScoreBoard(ERROR):"); + $display("\tExp mcu_baisr1:%b",data[i][31:16]); + $display("\tAct mcu_baisr1:%b",mcu_tr[i].mcu_baisr[1][15:0]); end + else $display("ScoreBoard: MCU_BAIS1 register is write successfully!"); + end + + else if(addr>=16'h90 && addr<=16'h93) begin + if((mcu_tr[i].mcu_baisr[2][15:0] & mask[i][31:16]) != (data[i][31:16] & mask[i][31:16])) begin + result = 1'b0; + $display("ScoreBoard(ERROR):"); + $display("\tExp mcu_baisr2:%b",data[i][31:16]); + $display("\tAct mcu_baisr2:%b",mcu_tr[i].mcu_baisr[2][15:0]); end + else $display("ScoreBoard: MCU_BAIS2 register is write successfully!"); + end + + else if(addr>=16'h94 && addr<=16'h97) begin + if((mcu_tr[i].mcu_baisr[3][15:0] & mask[i][31:16]) != (data[i][31:16] & mask[i][31:16])) begin + result = 1'b0; + $display("ScoreBoard(ERROR):"); + $display("\tExp mcu_baisr3:%b",data[i][31:16]); + $display("\tAct mcu_baisr3:%b",mcu_tr[i].mcu_baisr[3][15:0]); end + else $display("ScoreBoard: MCU_BAIS3 register is write successfully!"); + end + + else if(addr>=16'h50 && addr<=16'h53) begin + if((mcu_tr[i].mcu_nco_pha_clr & mask[i][0]) != (data[i][0] & mask[i][0])) begin + result = 1'b0; + $display("ScoreBoard(ERROR):"); + $display("\tExp mcu_nco_pha_clr:%b",data[i][0]); + $display("\tAct mcu_nco_pha_clr:%b",mcu_tr[i].mcu_nco_pha_clr); end + else $display("ScoreBoard: PHA_CLR register is write successfully!"); + end + + else if(addr>=16'hA4 && addr<=16'hA7) begin + if((mcu_tr[i].mcu_intp_sel & mask[i][1:0]) != (data[i][1:0] & mask[i][1:0])) begin + result = 1'b0; + $display("ScoreBoard(ERROR):"); + $display("\tExp mcu_intp_sel:%b",data[i][1:0]); + $display("\tAct mcu_intp_sel:%b",mcu_tr[i].mcu_intp_sel); end + else $display("ScoreBoard: INTP_SEL register is write successfully!"); + end + + else if(addr>=16'h74 && addr<=16'h77) begin + if((mcu_tr[i].mcu_rz_pha & mask[i][31:16]) != (data[i][31:16] & mask[i][31:16])) begin + result = 1'b0; + $display("ScoreBoard(ERROR):"); + $display("\tExp mcu_rz_pha:%b",data[i][31:16]); + $display("\tAct mcu_rz_pha:%b",mcu_tr[i].mcu_rz_pha); end + else $display("ScoreBoard: RZ_PHA register is write successfully!"); + end + + else if(addr>=16'h00 && addr<=16'h0F | addr>=16'h98 && addr<=16'hA3) + $display("ScoreBoard: read-only register."); + else begin result = 1'b0; $display("ScoreBoard: Error Address!"); end + + end + + //if read,COMPARE the "dout" sent by SPI WITH the "tr" collected from regfile's input port or the "data" received last write + else begin + + if(dout.size()!=size | mcu_tr.size!=size) begin + result = 1'b0; + $display("ScoreBoard(ERROR): Size ARNT'T equal!"); + $display("Exp size:%0d",mcu_tr.size()); + $display("Act size:%0d",dout.size()); + end + + else if(addr>=16'h00 && addr<=16'h03) begin + if(dout[i] != mcu_tr[i].mcu_param[0]) begin + result = 1'b0; + $display("ScoreBoard(ERROR):"); + $display("\tExp mcu_param0:%b",mcu_tr[i].mcu_param[0]); + $display("\tAct mcu_param0:%b",dout[i]); end + else $display("ScoreBoard: MCU_PARAM0 register is read successfully!"); + end + + else if(addr>=16'h04 && addr<=16'h07) begin + if(dout[i] != mcu_tr[i].mcu_param[1]) begin + result = 1'b0; + $display("ScoreBoard(ERROR):"); + $display("\tExp mcu_param1:%b",mcu_tr[i].mcu_param[1]); + $display("\tAct mcu_param1:%b",dout[i]); end + else $display("ScoreBoard: MCU_PARAM1 register is read successfully!"); + end + + else if(addr>=16'h08 && addr<=16'h0B) begin + if(dout[i] != mcu_tr[i].mcu_param[2]) begin + result = 1'b0; + $display("ScoreBoard(ERROR):"); + $display("\tExp mcu_param2:%b",mcu_tr[i].mcu_param[2]); + $display("\tAct mcu_param2:%b",dout[i]); end + else $display("ScoreBoard: MCU_PARAM2 register is read successfully!"); + end + + else if(addr>=16'h0C && addr<=16'h0F) begin + if(dout[i] != mcu_tr[i].mcu_param[3]) begin + result = 1'b0; + $display("ScoreBoard(ERROR):"); + $display("\tExp mcu_param3:%b",mcu_tr[i].mcu_param[3]); + $display("\tAct mcu_param3:%b",dout[i]); end + else $display("ScoreBoard: MCU_PARAM2 register is read successfully!"); + end + + else if(addr>=16'h98 && addr<=16'h9B) begin + if(dout[i] != mcu_tr[i].run_time) begin + result = 1'b0; + $display("ScoreBoard(ERROR):"); + $display("\tExp run_time:%b",mcu_tr[i].run_time); + $display("\tAct run_time:%b",dout[i]); end + else $display("ScoreBoard: RUN_TIME register is read successfully!"); + end + + else if(addr>=16'h9C && addr<=16'h9F) begin + if(dout[i] != mcu_tr[i].instr_num) begin + result = 1'b0; + $display("ScoreBoard(ERROR):"); + $display("\tExp instr_num:%b",mcu_tr[i].instr_num); + $display("\tAct instr_num:%b",dout[i]); end + else $display("ScoreBoard: INSTR_NUM register is read successfully!"); + end + + else if(addr>=16'hA0 && addr<=16'hA3) begin + if(dout[i][1:0] != mcu_tr[i].fb_st_info[1:0]) begin + result = 1'b0; + $display("ScoreBoard(ERROR):"); + $display("\tExp fb_st_info:%b",mcu_tr[i].fb_st_info[1:0]); + $display("\tAct fb_st_info:%b",dout[i]); end + else $display("ScoreBoard: FSIR register is read successfully!"); + end + + else if(addr>=16'h10 && addr<=16'h1F | + addr>=16'h40 && addr<=16'h4F) begin + if((dout[i] & mask[i]) != (data[i] & mask[i])) begin + result = 1'b0; + $display("ScoreBoard(ERROR):"); + $display("\tExp miso:%b",data[i]); + $display("\tAct miso:%b",dout[i]); end + else $display("ScoreBoard: 32bit register is write&read successfully!"); + end + + else if(addr>=16'h54 && addr<=16'h97) begin + if((dout[i][15:0] & mask[i][31:16]) != (data[i][31:16] & mask[i][31:16])) begin + result = 1'b0; + $display("ScoreBoard(ERROR):"); + $display("\tExp miso:%b",data[i][31:16]); + $display("\tAct miso:%b",dout[i][15:0]); end + else $display("ScoreBoard: 16bit register is write&read successfully!"); + end + + else if(addr>=16'hA4 && addr<=16'hA7) begin + if((dout[i][1:0] & mask[i][1:0]) != (data[i][1:0] & mask[i][1:0])) begin + result = 1'b0; + $display("ScoreBoard(ERROR):"); + $display("\tExp miso:%b",data[i][1:0]); + $display("\tAct miso:%b",dout[i][1:0]); end + else $display("ScoreBoard: INTP_SEL register is write&read successfully!"); + end + + else if(addr>=16'h50 && addr<=16'h53) begin + if(dout[i][0] != 0) begin + result = 1'b0; + $display("ScoreBoard(ERROR):"); + $display("\tExp miso:0"); + $display("\tAct miso:%b",dout[i][0]); end + else $display("ScoreBoard: clr_pha read value 1'b0!"); + end + + else begin result = 1'b0; $display("ScoreBoard: Error Address!"); end + end//end_if(cmd[0]) + end//end_for(size) + $display(""); + end//end_if(chip) + + return result; + +endfunction: compare + + + diff --git a/tb/testbench/mcureg_tb/mcureg_trans.sv b/tb/testbench/mcureg_tb/mcureg_trans.sv new file mode 100644 index 0000000..4144c1d --- /dev/null +++ b/tb/testbench/mcureg_tb/mcureg_trans.sv @@ -0,0 +1,59 @@ +class mcureg_trans; + + rand bit[3 :0] wrmask ; + rand bit[2 :0] fb_st_info ; + rand bit[31 :0] run_time ; + rand bit[31 :0] instr_num ; + rand bit[31 :0] mcu_param[3:0] ; // MCU parameter 0~3 + + rand bit[31 :0] wrmask_time ; + rand bit[31 :0] fb_st_info_time ; + rand bit[31 :0] run_time_time ; + rand bit[31 :0] instr_num_time ; + rand bit[31 :0] mcu_param_time[3:0] ; + + rand bit[31 :0] mcu_result [3:0] ; // MCU result 0~3 + rand bit[31 :0] mcu_cwfr [3:0] ; // Carrier frequency ctrl word 0~3 + rand bit[31 :0] mcu_gapr [7:0] ; // Carrier phase ctrl word 0~3 + rand bit[31 :0] mcu_ampr [3:0] ; // Carrier Amplitude 0~3 + rand bit[31 :0] mcu_baisr [3:0] ; // Carrier Bais 0~3 + rand bit[1 :0] mcu_intp_sel ; //2'b00:HBF;2'b01:Nearest-neighbor interpolator; + rand bit mcu_nco_pha_clr ; + rand bit[15 :0] mcu_rz_pha ; + +constraint cstr { + wrmask == 4'b1111 ; + wrmask_time >= 0 ; + fb_st_info_time >= 0 ; + run_time_time >= 0 ; + instr_num_time >= 0 ; + mcu_param_time[0] >= 0 ; + mcu_param_time[1] >= 0 ; + mcu_param_time[2] >= 0 ; + mcu_param_time[3] >= 0 ; + wrmask_time <= 2000 ; + fb_st_info_time <= 2000 ; + run_time_time <= 2000 ; + instr_num_time <= 2000 ; + mcu_param_time[0] <= 2000 ; + mcu_param_time[1] <= 2000 ; + mcu_param_time[2] <= 2000 ; + mcu_param_time[3] <= 2000 ; +} + + function new(); + endfunction + +endclass : mcureg_trans + + + + + + + + + + + + diff --git a/tb/testbench/rtl/awg_regfile.v b/tb/testbench/rtl/awg_regfile.v new file mode 100644 index 0000000..cf704f5 --- /dev/null +++ b/tb/testbench/rtl/awg_regfile.v @@ -0,0 +1,1001 @@ +//+FHDR-------------------------------------------------------------------------------------------------------- +// Company: +//----------------------------------------------------------------------------------------------------------------- +// File Name : awg_regfile.v +// Department : +// Author : PWY +// Author's Tel : +//----------------------------------------------------------------------------------------------------------------- +// Relese History +// Version Date Author Description +// 0.1 2024-03-13 PWY AWG dedicated register file +//----------------------------------------------------------------------------------------------------------------- +// Keywords : +// +//----------------------------------------------------------------------------------------------------------------- +// Parameter +// +//----------------------------------------------------------------------------------------------------------------- +// Purpose : +// +//----------------------------------------------------------------------------------------------------------------- +// Target Device: +// Tool versions: +//----------------------------------------------------------------------------------------------------------------- +// Reuse Issues +// Reset Strategy: +// Clock Domains: +// Critical Timing: +// Asynchronous I/F: +// Synthesizable (y/n): +// Other: +//-FHDR-------------------------------------------------------------------------------------------------------- + +// ----------------------------------------------------------- +// -- Register address offset macros +// ----------------------------------------------------------- +//MCU parameter register 0 +`define MCUPARAR0 16'h00 +//MCU parameter register 1 +`define MCUPARAR1 16'h04 +//MCU parameter register 2 +`define MCUPARAR2 16'h08 +//MCU parameter register 3 +`define MCUPARAR3 16'h0C +//MCU result register 0 +`define MCURESR0 16'h10 +//MCU result register 1 +`define MCURESR1 16'h14 +//MCU result register 2 +`define MCURESR2 16'h18 +//MCU result register 3 +`define MCURESR3 16'h1C +//Run-time register +`define RTIMR 16'h98 +//Instruction count register +`define ICNTR 16'h9C +//Feedback state information register +`define FSIR 16'hA0 +//Modulator Operation Mode Register +`define MODMR 16'h100 +//Interpolator Operation Mode Register +`define INTPMR 16'h104 +//Frequency Mixer NCO Clear Register +`define MIXNCOCR 16'h108 +//Frequency Mixer NCO Frequency Control Word High 32-bit Register +`define MIXNFCWHR 16'h10C +//Frequency Mixer NCO Frequency Control Word Low 16-bit Register +`define MIXNFCWLR 16'h110 +//Frequency Mixer NCO Phase Control Word Register +`define MIXNPHAR 16'h114 +//Frequency Mixer Operating Mode Register +`define MIXMR 16'h118 +//Frequency Mixer Output Data Type Register +`define MIXODTR 16'h11C +//Frequency Mixer Output Data Format Register +`define MIXODFR 16'h120 +//Interpolator Selection Register +`define INTPSELR 16'h128 +//Tail Correction Bypass Register +`define TCBPR 16'h12C +//Tail Correction A Parameter Real Part Value Register 0 +`define TCPARR0 16'h130 +//Tail Correction A Parameter Real Part Value Register 1 +`define TCPARR1 16'h134 +//Tail Correction A Parameter Real Part Value Register 2 +`define TCPARR2 16'h138 +//Tail Correction A Parameter Real Part Value Register 3 +`define TCPARR3 16'h13C +//Tail Correction A Parameter Real Part Value Register 4 +`define TCPARR4 16'h140 +//Tail Correction A Parameter Real Part Value Register 5 +`define TCPARR5 16'h144 +//Tail Correction B Parameter Real Part Value Register 0 +`define TCPBRR0 16'h148 +//Tail Correction B Parameter Real Part Value Register 1 +`define TCPBRR1 16'h14C +//Tail Correction B Parameter Real Part Value Register 2 +`define TCPBRR2 16'h150 +//Tail Correction B Parameter Real Part Value Register 3 +`define TCPBRR3 16'h154 +//Tail Correction B Parameter Real Part Value Register 4 +`define TCPBRR4 16'h158 +//Tail Correction B Parameter Real Part Value Register 5 +`define TCPBRR5 16'h15C +//Tail Correction A Parameter Imaginary Part Value Register 0 +`define TCPAIR0 16'h160 +//Tail Correction A Parameter Imaginary Part Value Register 1 +`define TCPAIR1 16'h164 +//Tail Correction A Parameter Imaginary Part Value Register 2 +`define TCPAIR2 16'h168 +//Tail Correction A Parameter Imaginary Part Value Register 3 +`define TCPAIR3 16'h16C +//Tail Correction A Parameter Imaginary Part Value Register 4 +`define TCPAIR4 16'h170 +//Tail Correction A Parameter Imaginary Part Value Register 5 +`define TCPAIR5 16'h174 +//Tail Correction B Parameter Imaginary Part Value Register 0 +`define TCPBIR0 16'h178 +//Tail Correction A Parameter Imaginary Part Value Register 1 +`define TCPBIR1 16'h17C +//Tail Correction B Parameter Imaginary Part Value Register 2 +`define TCPBIR2 16'h180 +//Tail Correction B Parameter Imaginary Part Value Register 3 +`define TCPBIR3 16'h184 +//Tail Correction B Parameter Imaginary Part Value Register 4 +`define TCPBIR4 16'h188 +//Tail Correction B Parameter Imaginary Part Value Register 5 +`define TCPBIR5 16'h18C + + +module awg_regfile ( + //system port + input clk // System Main Clock + ,input rst_n // Spi Reset active low + //rw op port + ,input [31 :0] wrdata // write data + ,input wren // write enable + ,input [15 :0] rwaddr // read & write address + ,input rden // read enable + ,output [31 :0] rddata // read data + ,input [2 :0] fb_st_i + ,input [31 :0] run_time + ,input [31 :0] instr_num + //MCU and SPI interface for interaction + ,output [31 :0] mcu_param0 // MCU parameter 0 + ,output [31 :0] mcu_param1 // MCU parameter 1 + ,output [31 :0] mcu_param2 // MCU parameter 2 + ,output [31 :0] mcu_param3 // MCU parameter 3 + ,input [31 :0] mcu_result0 // MCU result 0 + ,input [31 :0] mcu_result1 // MCU result 1 + ,input [31 :0] mcu_result2 // MCU result 2 + ,input [31 :0] mcu_result3 // MCU result 3 + ,output [2 :0] fb_st_o + //awg cfg + ,output mod_sel_sideband //1'b0:Upper sideband;1'b1:Lower sideband; + //DSP cfg + ,output qam_nco_clr + ,output [47:0] qam_fcw///////////////////////////////////////////////////////////////////////////// + ,output [15:0] qam_pha ///////////////////////////////////////////////////////////////////////////// + ,output [1 :0] qam_mod //2'b00:bypass;2'b01:mix; + //2'b10:cos;2'b11:sin; + ,output qam_sel_sideband //1'b0:Upper sideband;1'b1:Lower sideband; + ,output [2 :0] intp_mode //3'b000:x1;3'b001:x2;3'b010:x4; + //3'b011:x8;3'b100:x16; + ,output [1 :0] intp_sel //2'b00:HBF;2'b01:Nearest-neighbor interpolator; + //2'b10:Median interpolator;2'b00:reserve; + ,output [1 :0] dac_mode_sel //2'b00:NRZ mode;2'b01:MIX mode; + //2'b10:2xNRZ mode;2'b00:reserve; + ,output tc_bypass //1'b0:bypass;1'b1:enable; + ,output [31:0] tcparr0 + ,output [31:0] tcparr1 + ,output [31:0] tcparr2 + ,output [31:0] tcparr3 + ,output [31:0] tcparr4 + ,output [31:0] tcparr5 + ,output [31:0] tcpbrr0 + ,output [31:0] tcpbrr1 + ,output [31:0] tcpbrr2 + ,output [31:0] tcpbrr3 + ,output [31:0] tcpbrr4 + ,output [31:0] tcpbrr5 + ,output [31:0] tcpair0 + ,output [31:0] tcpair1 + ,output [31:0] tcpair2 + ,output [31:0] tcpair3 + ,output [31:0] tcpair4 + ,output [31:0] tcpair5 + ,output [31:0] tcpbir0 + ,output [31:0] tcpbir1 + ,output [31:0] tcpbir2 + ,output [31:0] tcpbir3 + ,output [31:0] tcpbir4 + ,output [31:0] tcpbir5 +); + +localparam L = 1'b0, + H = 1'b1; + +// ------------------------------------------------------ +// -- Register enable (select) wires +// ------------------------------------------------------ +wire mcuparar0en ; // MCUPARAR0 select +wire mcuparar1en ; // MCUPARAR1 select +wire mcuparar2en ; // MCUPARAR2 select +wire mcuparar3en ; // MCUPARAR3 select +wire mcuresr0en ; // MCURESR0 select +wire mcuresr1en ; // MCURESR1 select +wire mcuresr2en ; // MCURESR2 select +wire mcuresr3en ; // MCURESR3 select +wire rtimren ; // RTIMR select +wire icntren ; // ICNTR select +wire fsiren ; // FSIR select +wire modmren ; // MODMR select +wire intpmren ; // INTPMR select +wire mixncocren ; // MIXNCOCR select +wire mixnfcwhren ; // MIXNFCWHR select +wire mixnfcwlren ; // MIXNFCWLR select +wire mixnpharen ; // MIXNPHAR select +wire mixmren ; // MIXMR select +wire mixodtren ; // MIXODTR select +wire mixodfren ; // MIXODFR select +wire intpselren ; // INTPSELR select +wire tcbpren ; // TCBPR select +wire tcparr0en ; // TCPARR0 select +wire tcparr1en ; // TCPARR1 select +wire tcparr2en ; // TCPARR2 select +wire tcparr3en ; // TCPARR3 select +wire tcparr4en ; // TCPARR4 select +wire tcparr5en ; // TCPARR5 select +wire tcpbrr0en ; // TCPBRR0 select +wire tcpbrr1en ; // TCPBRR1 select +wire tcpbrr2en ; // TCPBRR2 select +wire tcpbrr3en ; // TCPBRR3 select +wire tcpbrr4en ; // TCPBRR4 select +wire tcpbrr5en ; // TCPBRR5 select +wire tcpair0en ; // TCPAIR0 select +wire tcpair1en ; // TCPAIR1 select +wire tcpair2en ; // TCPAIR2 select +wire tcpair3en ; // TCPAIR3 select +wire tcpair4en ; // TCPAIR4 select +wire tcpair5en ; // TCPAIR5 select +wire tcpbir0en ; // TCPBIR0 select +wire tcpbir1en ; // TCPBIR1 select +wire tcpbir2en ; // TCPBIR2 select +wire tcpbir3en ; // TCPBIR3 select +wire tcpbir4en ; // TCPBIR4 select +wire tcpbir5en ; // TCPBIR5 select + +// ------------------------------------------------------ +// -- Register write enable wires +// ------------------------------------------------------ +wire mcuparar0we ; // MCUPARAR0 write enable +wire mcuparar1we ; // MCUPARAR1 write enable +wire mcuparar2we ; // MCUPARAR2 write enable +wire mcuparar3we ; // MCUPARAR3 write enable +wire intpmrwe ; // INTPMR write enable +wire mixncocrwe ; // MIXNCOCR write enable +wire mixnfcwhrwe ; // MIXNFCWHR write enable +wire mixnfcwlrwe ; // MIXNFCWLR write enable +wire mixnpharwe ; // MIXNPHAR write enable +wire mixmrwe ; // MIXMR write enable +wire mixodtrwe ; // MIXODTR write enable +wire mixodfrwe ; // MIXODFR write enable +wire intpselrwe ; // INTPSELR write enable +wire tcbprwe ; // TCBPR write enable +wire tcparr0we ; // TCPARR0 write enable +wire tcparr1we ; // TCPARR1 write enable +wire tcparr2we ; // TCPARR2 write enable +wire tcparr3we ; // TCPARR3 write enable +wire tcparr4we ; // TCPARR4 write enable +wire tcparr5we ; // TCPARR5 write enable +wire tcpbrr0we ; // TCPBRR0 write enable +wire tcpbrr1we ; // TCPBRR1 write enable +wire tcpbrr2we ; // TCPBRR2 write enable +wire tcpbrr3we ; // TCPBRR3 write enable +wire tcpbrr4we ; // TCPBRR4 write enable +wire tcpbrr5we ; // TCPBRR5 write enable +wire tcpair0we ; // TCPAIR0 write enable +wire tcpair1we ; // TCPAIR1 write enable +wire tcpair2we ; // TCPAIR2 write enable +wire tcpair3we ; // TCPAIR3 write enable +wire tcpair4we ; // TCPAIR4 write enable +wire tcpair5we ; // TCPAIR5 write enable +wire tcpbir0we ; // TCPBIR0 write enable +wire tcpbir1we ; // TCPBIR1 write enable +wire tcpbir2we ; // TCPBIR2 write enable +wire tcpbir3we ; // TCPBIR3 write enable +wire tcpbir4we ; // TCPBIR4 write enable +wire tcpbir5we ; // TCPBIR5 write enable + +// ------------------------------------------------------ +// -- Misc wires +// ------------------------------------------------------ + +// ------------------------------------------------------ +// -- Misc Registers +// ------------------------------------------------------ +reg [31 :0] mcuparar0 ; // MCUPARAR0 register +reg [31 :0] mcuparar1 ; // MCUPARAR1 register +reg [31 :0] mcuparar2 ; // MCUPARAR2 register +reg [31 :0] mcuparar3 ; // MCUPARAR3 register +reg [31 :0] mcuresr0 ; // MCURESR0 register +reg [31 :0] mcuresr1 ; // MCURESR1 register +reg [31 :0] mcuresr2 ; // MCURESR2 register +reg [31 :0] mcuresr3 ; // MCURESR3 register +reg [31 :0] rtimr ; // RTIMR register +reg [31 :0] icntr ; // ICNTR register +reg [1 :0] fsir ; // FSIR register +reg [0 :0] modmr ; // MODMR register +reg [2 :0] intpmr ; // INTPMR register +reg [0 :0] mixncocr ; // MIXNCOCR register +reg [31 :0] mixnfcwhr ; // MIXNFCWHR register +reg [15 :0] mixnfcwlr ; // MIXNFCWLR register +reg [15 :0] mixnphar ; // MIXNPHAR register +reg [0 :0] mixmr ; // MIXMR register +reg [1 :0] mixodtr ; // MIXODTR register +reg [1 :0] mixodfr ; // MIXODFR register +reg [1 :0] intpselr ; // INTPSELR register +reg [0 :0] tcbpr ; // TCBPR register +reg [31 :0] tcparr0 ; // TCPARR0 register +reg [31 :0] tcparr1 ; // TCPARR1 register +reg [31 :0] tcparr2 ; // TCPARR2 register +reg [31 :0] tcparr3 ; // TCPARR3 register +reg [31 :0] tcparr4 ; // TCPARR4 register +reg [31 :0] tcparr5 ; // TCPARR5 register +reg [31 :0] tcpbrr0 ; // TCPBRR0 register +reg [31 :0] tcpbrr1 ; // TCPBRR1 register +reg [31 :0] tcpbrr2 ; // TCPBRR2 register +reg [31 :0] tcpbrr3 ; // TCPBRR3 register +reg [31 :0] tcpbrr4 ; // TCPBRR4 register +reg [31 :0] tcpbrr5 ; // TCPBRR5 register +reg [31 :0] tcpair0 ; // TCPAIR0 register +reg [31 :0] tcpair1 ; // TCPAIR1 register +reg [31 :0] tcpair2 ; // TCPAIR2 register +reg [31 :0] tcpair3 ; // TCPAIR3 register +reg [31 :0] tcpair4 ; // TCPAIR4 register +reg [31 :0] tcpair5 ; // TCPAIR5 register +reg [31 :0] tcpbir0 ; // TCPBIR0 register +reg [31 :0] tcpbir1 ; // TCPBIR1 register +reg [31 :0] tcpbir2 ; // TCPBIR2 register +reg [31 :0] tcpbir3 ; // TCPBIR3 register +reg [31 :0] tcpbir4 ; // TCPBIR4 register +reg [31 :0] tcpbir5 ; // TCPBIR5 register + +reg [31: 0] rddata_reg ; + +// ------------------------------------------------------ +// -- Address decoder +// +// Decodes the register address offset input(reg_addr) +// to produce enable (select) signals for each of the +// SW-registers in the macrocell. The reg_addr input +// is bits [15:0] of the paddr bus. +// ------------------------------------------------------ +assign mcuparar0en = (rwaddr[15:2] == `MCUPARAR0 >> 2) ? 1'b1 : 1'b0; +assign mcuparar1en = (rwaddr[15:2] == `MCUPARAR1 >> 2) ? 1'b1 : 1'b0; +assign mcuparar2en = (rwaddr[15:2] == `MCUPARAR2 >> 2) ? 1'b1 : 1'b0; +assign mcuparar3en = (rwaddr[15:2] == `MCUPARAR3 >> 2) ? 1'b1 : 1'b0; +assign mcuresr0en = (rwaddr[15:2] == `MCURESR0 >> 2) ? 1'b1 : 1'b0; +assign mcuresr1en = (rwaddr[15:2] == `MCURESR1 >> 2) ? 1'b1 : 1'b0; +assign mcuresr2en = (rwaddr[15:2] == `MCURESR2 >> 2) ? 1'b1 : 1'b0; +assign mcuresr3en = (rwaddr[15:2] == `MCURESR3 >> 2) ? 1'b1 : 1'b0; +assign rtimren = (rwaddr[15:2] == `RTIMR >> 2) ? 1'b1 : 1'b0; +assign icntren = (rwaddr[15:2] == `ICNTR >> 2) ? 1'b1 : 1'b0; +assign fsiren = (rwaddr[15:2] == `FSIR >> 2) ? 1'b1 : 1'b0; +assign modmren = (rwaddr[15:2] == `MODMR >> 2) ? 1'b1 : 1'b0; +assign intpmren = (rwaddr[15:2] == `INTPMR >> 2) ? 1'b1 : 1'b0; +assign mixncocren = (rwaddr[15:2] == `MIXNCOCR >> 2) ? 1'b1 : 1'b0; +assign mixnfcwhren = (rwaddr[15:2] == `MIXNFCWHR >> 2) ? 1'b1 : 1'b0; +assign mixnfcwlren = (rwaddr[15:2] == `MIXNFCWLR >> 2) ? 1'b1 : 1'b0; +assign mixnpharen = (rwaddr[15:2] == `MIXNPHAR >> 2) ? 1'b1 : 1'b0; +assign mixmren = (rwaddr[15:2] == `MIXMR >> 2) ? 1'b1 : 1'b0; +assign mixodtren = (rwaddr[15:2] == `MIXODTR >> 2) ? 1'b1 : 1'b0; +assign mixodfren = (rwaddr[15:2] == `MIXODFR >> 2) ? 1'b1 : 1'b0; +assign intpselren = (rwaddr[15:2] == `INTPSELR >> 2) ? 1'b1 : 1'b0; +assign tcbpren = (rwaddr[15:2] == `TCBPR >> 2) ? 1'b1 : 1'b0; +assign tcparr0en = (rwaddr[15:2] == `TCPARR0 >> 2) ? 1'b1 : 1'b0; +assign tcparr1en = (rwaddr[15:2] == `TCPARR1 >> 2) ? 1'b1 : 1'b0; +assign tcparr2en = (rwaddr[15:2] == `TCPARR2 >> 2) ? 1'b1 : 1'b0; +assign tcparr3en = (rwaddr[15:2] == `TCPARR3 >> 2) ? 1'b1 : 1'b0; +assign tcparr4en = (rwaddr[15:2] == `TCPARR4 >> 2) ? 1'b1 : 1'b0; +assign tcparr5en = (rwaddr[15:2] == `TCPARR5 >> 2) ? 1'b1 : 1'b0; +assign tcpbrr0en = (rwaddr[15:2] == `TCPBRR0 >> 2) ? 1'b1 : 1'b0; +assign tcpbrr1en = (rwaddr[15:2] == `TCPBRR1 >> 2) ? 1'b1 : 1'b0; +assign tcpbrr2en = (rwaddr[15:2] == `TCPBRR2 >> 2) ? 1'b1 : 1'b0; +assign tcpbrr3en = (rwaddr[15:2] == `TCPBRR3 >> 2) ? 1'b1 : 1'b0; +assign tcpbrr4en = (rwaddr[15:2] == `TCPBRR4 >> 2) ? 1'b1 : 1'b0; +assign tcpbrr5en = (rwaddr[15:2] == `TCPBRR5 >> 2) ? 1'b1 : 1'b0; +assign tcpair0en = (rwaddr[15:2] == `TCPAIR0 >> 2) ? 1'b1 : 1'b0; +assign tcpair1en = (rwaddr[15:2] == `TCPAIR1 >> 2) ? 1'b1 : 1'b0; +assign tcpair2en = (rwaddr[15:2] == `TCPAIR2 >> 2) ? 1'b1 : 1'b0; +assign tcpair3en = (rwaddr[15:2] == `TCPAIR3 >> 2) ? 1'b1 : 1'b0; +assign tcpair4en = (rwaddr[15:2] == `TCPAIR4 >> 2) ? 1'b1 : 1'b0; +assign tcpair5en = (rwaddr[15:2] == `TCPAIR5 >> 2) ? 1'b1 : 1'b0; +assign tcpbir0en = (rwaddr[15:2] == `TCPBIR0 >> 2) ? 1'b1 : 1'b0; +assign tcpbir1en = (rwaddr[15:2] == `TCPBIR1 >> 2) ? 1'b1 : 1'b0; +assign tcpbir2en = (rwaddr[15:2] == `TCPBIR2 >> 2) ? 1'b1 : 1'b0; +assign tcpbir3en = (rwaddr[15:2] == `TCPBIR3 >> 2) ? 1'b1 : 1'b0; +assign tcpbir4en = (rwaddr[15:2] == `TCPBIR4 >> 2) ? 1'b1 : 1'b0; +assign tcpbir5en = (rwaddr[15:2] == `TCPBIR5 >> 2) ? 1'b1 : 1'b0; + + +// ------------------------------------------------------ +// -- Write enable signals +// +// Write enable signals for writable SW-registers. +// The write enable for each register is the ANDed +// result of the register enable and the input reg_wren +// ------------------------------------------------------ +assign mcuparar0we = mcuparar0en & wren; +assign mcuparar1we = mcuparar1en & wren; +assign mcuparar2we = mcuparar2en & wren; +assign mcuparar3we = mcuparar3en & wren; +assign modmrwe = modmren & wren;/////////// +assign intpmrwe = intpmren & wren; +assign mixncocrwe = mixncocren & wren; +assign mixnfcwhrwe = mixnfcwhren & wren; +assign mixnfcwlrwe = mixnfcwlren & wren; +assign mixnpharwe = mixnpharen & wren; +assign mixmrwe = mixmren & wren; +assign mixodtrwe = mixodtren & wren; +assign mixodfrwe = mixodfren & wren; +assign intpselrwe = intpselren & wren; +assign tcbprwe = tcbpren & wren; +assign tcparr0we = tcparr0en & wren; +assign tcparr1we = tcparr1en & wren; +assign tcparr2we = tcparr2en & wren; +assign tcparr3we = tcparr3en & wren; +assign tcparr4we = tcparr4en & wren; +assign tcparr5we = tcparr5en & wren; +assign tcpbrr0we = tcpbrr0en & wren; +assign tcpbrr1we = tcpbrr1en & wren; +assign tcpbrr2we = tcpbrr2en & wren; +assign tcpbrr3we = tcpbrr3en & wren; +assign tcpbrr4we = tcpbrr4en & wren; +assign tcpbrr5we = tcpbrr5en & wren; +assign tcpair0we = tcpair0en & wren; +assign tcpair1we = tcpair1en & wren; +assign tcpair2we = tcpair2en & wren; +assign tcpair3we = tcpair3en & wren; +assign tcpair4we = tcpair4en & wren; +assign tcpair5we = tcpair5en & wren; +assign tcpbir0we = tcpbir0en & wren; +assign tcpbir1we = tcpbir1en & wren; +assign tcpbir2we = tcpbir2en & wren; +assign tcpbir3we = tcpbir3en & wren; +assign tcpbir4we = tcpbir4en & wren; +assign tcpbir5we = tcpbir5en & wren; + +// ------------------------------------------------------ +// -- mcuparar0 register +// +// Write mcuparar0 for 'MCUPARAR0' : 32-bit register +// Register is split into the following bit fields +// +// [31:0] --> mcuparar0 +// ------------------------------------------------------ +sirv_gnrl_dfflr #(32) mcuparar0_dfflr (mcuparar0we, wrdata[31:0], mcuparar0, clk, rst_n); + +// ------------------------------------------------------ +// -- mcuparar1 register +// +// Write mcuparar1 for 'MCUPARAR1' : 32-bit register +// Register is split into the following bit fields +// +// [31:0] --> mcuparar1 +// ------------------------------------------------------ +sirv_gnrl_dfflr #(32) mcuparar1_dfflr (mcuparar1we, wrdata[31:0], mcuparar1, clk, rst_n); + +// ------------------------------------------------------ +// -- mcuparar2 register +// +// Write mcuparar2 for 'MCUPARAR2' : 32-bit register +// Register is split into the following bit fields +// +// [31:0] --> mcuparar2 +// ------------------------------------------------------ +sirv_gnrl_dfflr #(32) mcuparar2_dfflr (mcuparar2we, wrdata[31:0], mcuparar2, clk, rst_n); + +// ------------------------------------------------------ +// -- mcuparar3 register +// +// Write mcuparar3 for 'MCUPARAR3' : 32-bit register +// Register is split into the following bit fields +// +// [31:0] --> mcuparar3 +// ------------------------------------------------------ +sirv_gnrl_dfflr #(32) mcuparar3_dfflr (mcuparar3we, wrdata[31:0], mcuparar3, clk, rst_n); + +// ------------------------------------------------------ +// -- modmr register +// +// Write modmr for 'MODMR' : 32-bit register +// Register is split into the following bit fields +// +// [0] --> modmr +// ------------------------------------------------------ +sirv_gnrl_dfflr #(1) modmr_dfflr (modmrwe, wrdata[0], modmr, clk, rst_n); + +// ------------------------------------------------------ +// -- intpmr register +// +// Write intpmr for 'INTPMR' : 32-bit register +// Register is split into the following bit fields +// +// [2:0] --> intpmr +// ------------------------------------------------------ +sirv_gnrl_dfflr #(3) intpmr_dfflr (intpmrwe, wrdata[2:0], intpmr, clk, rst_n); + +// ------------------------------------------------------ +// -- mixncocr register +// +// Write mixncocr for 'MIXNCOCR' : 32-bit register +// Register is split into the following bit fields +// +// [0] --> mixncocr +// ------------------------------------------------------ +sirv_gnrl_dfflr #(1) mixncocr_dfflr (mixncocrwe, wrdata[0], mixncocr, clk, rst_n); + +// ------------------------------------------------------ +// -- mixnfcwhr register +// +// Write mixnfcwhr for 'MIXNFCWHR' : 32-bit register +// Register is split into the following bit fields +// +// [31:0] --> mixnfcwhr +// ------------------------------------------------------ +sirv_gnrl_dfflr #(32) mixnfcwhr_dfflr (mixnfcwhrwe, wrdata[31:0], mixnfcwhr, clk, rst_n); + +// ------------------------------------------------------ +// -- mixnfcwlr register +// +// Write mixnfcwlr for 'MIXNFCWHR' : 32-bit register +// Register is split into the following bit fields +// +// [31:16] --> mixnfcwlr +// ------------------------------------------------------ +sirv_gnrl_dfflr #(16) mixnfcwlr_dfflr (mixnfcwlrwe, wrdata[31:16], mixnfcwlr, clk, rst_n); + +// ------------------------------------------------------ +// -- mixnphar register +// +// Write mixnphar for 'MIXNPHAR' : 32-bit register +// Register is split into the following bit fields +// +// [31:16] --> mixnphar +// ------------------------------------------------------ +sirv_gnrl_dfflr #(16) mixnphar_dfflr (mixnpharwe, wrdata[31:16], mixnphar, clk, rst_n); + +// ------------------------------------------------------ +// -- mixmr register +// +// Write mixmr for 'MIXNPHAR' : 32-bit register +// Register is split into the following bit fields +// +// [0] --> mixmr +// ------------------------------------------------------ +sirv_gnrl_dfflr #(1) mixmr_dfflr (mixmrwe, wrdata[0], mixmr, clk, rst_n); + +// ------------------------------------------------------ +// -- mixodtr register +// +// Write mixodtr for 'MIXNPHAR' : 32-bit register +// Register is split into the following bit fields +// +// [1:0] --> mixodtr +// ------------------------------------------------------ +sirv_gnrl_dfflr #(2) mixodtr_dfflr (mixodtrwe, wrdata[1:0], mixodtr, clk, rst_n); + +// ------------------------------------------------------ +// -- mixodfr register +// +// Write mixodfr for 'MIXODFR' : 32-bit register +// Register is split into the following bit fields +// +// [1:0] --> mixodfr +// ------------------------------------------------------ +sirv_gnrl_dfflr #(2) mixodfr_dfflr (mixodfrwe, wrdata[1:0], mixodfr, clk, rst_n); + +// ------------------------------------------------------ +// -- intpselr register +// +// Write intpselr for 'INTPSELR' : 32-bit register +// Register is split into the following bit fields +// +// [1:0] --> intpselr +// ------------------------------------------------------ +sirv_gnrl_dfflr #(2) intpselr_dfflr (intpselrwe, wrdata[1:0], intpselr, clk, rst_n); + +// ------------------------------------------------------ +// -- tcbpr register +// +// Write tcbpr for 'TCBPR' : 32-bit register +// Register is split into the following bit fields +// +// [0] --> tcbpr +// ------------------------------------------------------ +sirv_gnrl_dfflr #(1) tcbpr_dfflr (tcbprwe, wrdata[0], tcbpr, clk, rst_n); + +// ------------------------------------------------------ +// -- tcparr0 register +// +// Write tcparr0 for 'TCPARR0' : 32-bit register +// Register is split into the following bit fields +// +// [31:0] --> tcparr0 +// ------------------------------------------------------ +sirv_gnrl_dfflr #(32) tcparr0_dfflr (tcparr0we, wrdata[31:0], tcparr0, clk, rst_n); + +// ------------------------------------------------------ +// -- tcparr1 register +// +// Write tcparr1 for 'TCPARR1' : 32-bit register +// Register is split into the following bit fields +// +// [0] --> tcparr1 +// ------------------------------------------------------ +sirv_gnrl_dfflr #(32) tcparr1_dfflr (tcparr1we, wrdata[31:0], tcparr1, clk, rst_n);//////// + +// ------------------------------------------------------ +// -- tcparr2 register +// +// Write tcparr2 for 'TCPARR2' : 32-bit register +// Register is split into the following bit fields +// +// [31:0] --> tcparr2 +// ------------------------------------------------------ +sirv_gnrl_dfflr #(32) tcparr2_dfflr (tcparr2we, wrdata[31:0], tcparr2, clk, rst_n); + +// ------------------------------------------------------ +// -- tcparr3 register +// +// Write tcparr3 for 'TCPARR3' : 32-bit register +// Register is split into the following bit fields +// +// [31:0] --> tcparr3 +// ------------------------------------------------------ +sirv_gnrl_dfflr #(32) tcparr3_dfflr (tcparr3we, wrdata[31:0], tcparr3, clk, rst_n); + +// ------------------------------------------------------ +// -- tcparr4 register +// +// Write tcparr4 for 'TCPARR4' : 32-bit register +// Register is split into the following bit fields +// +// [31:0] --> tcparr4 +// ------------------------------------------------------ +sirv_gnrl_dfflr #(32) tcparr4_dfflr (tcparr4we, wrdata[31:0], tcparr4, clk, rst_n); + +// ------------------------------------------------------ +// -- tcparr5 register +// +// Write tcparr5 for 'TCPARR5' : 32-bit register +// Register is split into the following bit fields +// +// [31:0] --> tcparr5 +// ------------------------------------------------------ +sirv_gnrl_dfflr #(32) tcparr5_dfflr (tcparr5we, wrdata[31:0], tcparr5, clk, rst_n); + +// ------------------------------------------------------ +// -- tcpbrr0 register +// +// Write tcpbrr0 for 'tcpbrr0' : 32-bit register +// Register is split into the following bit fields +// +// [31:0] --> tcpbrr0 +// ------------------------------------------------------ +sirv_gnrl_dfflr #(32) tcpbrr0_dfflr (tcpbrr0we, wrdata[31:0], tcpbrr0, clk, rst_n); + +// ------------------------------------------------------ +// -- tcpbrr1 register +// +// Write tcpbrr1 for 'tcpbrr1' : 32-bit register +// Register is split into the following bit fields +// +// [0] --> tcpbrr1 +// ------------------------------------------------------ +sirv_gnrl_dfflr #(32) tcpbrr1_dfflr (tcpbrr1we, wrdata[31:0], tcpbrr1, clk, rst_n);//////////////////// + +// ------------------------------------------------------ +// -- tcpbrr2 register +// +// Write tcpbrr2 for 'tcpbrr2' : 32-bit register +// Register is split into the following bit fields +// +// [31:0] --> tcpbrr2 +// ------------------------------------------------------ +sirv_gnrl_dfflr #(32) tcpbrr2_dfflr (tcpbrr2we, wrdata[31:0], tcpbrr2, clk, rst_n); + +// ------------------------------------------------------ +// -- tcpbrr3 register +// +// Write tcpbrr3 for 'tcpbrr3' : 32-bit register +// Register is split into the following bit fields +// +// [31:0] --> tcpbrr3 +// ------------------------------------------------------ +sirv_gnrl_dfflr #(32) tcpbrr3_dfflr (tcpbrr3we, wrdata[31:0], tcpbrr3, clk, rst_n); + +// ------------------------------------------------------ +// -- tcpbrr4 register +// +// Write tcpbrr4 for 'tcpbrr4' : 32-bit register +// Register is split into the following bit fields +// +// [31:0] --> tcpbrr4 +// ------------------------------------------------------ +sirv_gnrl_dfflr #(32) tcpbrr4_dfflr (tcpbrr4we, wrdata[31:0], tcpbrr4, clk, rst_n); + +// ------------------------------------------------------ +// -- tcpbrr5 register +// +// Write tcpbrr5 for 'tcpbrr5' : 32-bit register +// Register is split into the following bit fields +// +// [31:0] --> tcpbrr5 +// ------------------------------------------------------ +sirv_gnrl_dfflr #(32) tcpbrr5_dfflr (tcpbrr5we, wrdata[31:0], tcpbrr5, clk, rst_n); + +// ------------------------------------------------------ +// -- tcpair0 register +// +// Write tcpair0 for 'tcpair0' : 32-bit register +// Register is split into the following bit fields +// +// [31:0] --> tcpair0 +// ------------------------------------------------------ +sirv_gnrl_dfflr #(32) tcpair0_dfflr (tcpair0we, wrdata[31:0], tcpair0, clk, rst_n); + +// ------------------------------------------------------ +// -- tcpair1 register +// +// Write tcpair1 for 'tcpair1' : 32-bit register +// Register is split into the following bit fields +// +// [0] --> tcpair1 +// ------------------------------------------------------ +sirv_gnrl_dfflr #(32) tcpair1_dfflr (tcpair1we, wrdata[31:0], tcpair1, clk, rst_n); + +// ------------------------------------------------------ +// -- tcpair2 register +// +// Write tcpair2 for 'tcpair2' : 32-bit register +// Register is split into the following bit fields +// +// [31:0] --> tcpair2 +// ------------------------------------------------------ +sirv_gnrl_dfflr #(32) tcpair2_dfflr (tcpair2we, wrdata[31:0], tcpair2, clk, rst_n); + +// ------------------------------------------------------ +// -- tcpair3 register +// +// Write tcpair3 for 'tcpair3' : 32-bit register +// Register is split into the following bit fields +// +// [31:0] --> tcpair3 +// ------------------------------------------------------ +sirv_gnrl_dfflr #(32) tcpair3_dfflr (tcpair3we, wrdata[31:0], tcpair3, clk, rst_n); + +// ------------------------------------------------------ +// -- tcpair4 register +// +// Write tcpair4 for 'tcpair4' : 32-bit register +// Register is split into the following bit fields +// +// [31:0] --> tcpair4 +// ------------------------------------------------------ +sirv_gnrl_dfflr #(32) tcpair4_dfflr (tcpair4we, wrdata[31:0], tcpair4, clk, rst_n); + +// ------------------------------------------------------ +// -- tcpair5 register +// +// Write tcpair5 for 'tcpair5' : 32-bit register +// Register is split into the following bit fields +// +// [31:0] --> tcpair5 +// ------------------------------------------------------ +sirv_gnrl_dfflr #(32) tcpair5_dfflr (tcpair5we, wrdata[31:0], tcpair5, clk, rst_n); + +// ------------------------------------------------------ +// -- tcpbir0 register +// +// Write tcpbir0 for 'tcpbir0' : 32-bit register +// Register is split into the following bit fields +// +// [31:0] --> tcpbir0 +// ------------------------------------------------------ +sirv_gnrl_dfflr #(32) tcpbir0_dfflr (tcpbir0we, wrdata[31:0], tcpbir0, clk, rst_n); + +// ------------------------------------------------------ +// -- tcpbir1 register +// +// Write tcpbir1 for 'tcpbir1' : 32-bit register +// Register is split into the following bit fields +// +// [0] --> tcpbir1 +// ------------------------------------------------------ +sirv_gnrl_dfflr #(32) tcpbir1_dfflr (tcpbir1we, wrdata[31:0], tcpbir1, clk, rst_n);////////// + +// ------------------------------------------------------ +// -- tcpbir2 register +// +// Write tcpbir2 for 'tcpbir2' : 32-bit register +// Register is split into the following bit fields +// +// [31:0] --> tcpbir2 +// ------------------------------------------------------ +sirv_gnrl_dfflr #(32) tcpbir2_dfflr (tcpbir2we, wrdata[31:0], tcpbir2, clk, rst_n); + +// ------------------------------------------------------ +// -- tcpbir3 register +// +// Write tcpbir3 for 'tcpbir3' : 32-bit register +// Register is split into the following bit fields +// +// [31:0] --> tcpbir3 +// ------------------------------------------------------ +sirv_gnrl_dfflr #(32) tcpbir3_dfflr (tcpbir3we, wrdata[31:0], tcpbir3, clk, rst_n); + +// ------------------------------------------------------ +// -- tcpbir4 register +// +// Write tcpbir4 for 'tcpbir4' : 32-bit register +// Register is split into the following bit fields +// +// [31:0] --> tcpbir4 +// ------------------------------------------------------ +sirv_gnrl_dfflr #(32) tcpbir4_dfflr (tcpbir4we, wrdata[31:0], tcpbir4, clk, rst_n); + +// ------------------------------------------------------ +// -- tcpbir5 register +// +// Write tcpbir5 for 'tcpbir5' : 32-bit register +// Register is split into the following bit fields +// +// [31:0] --> tcpbir5 +// ------------------------------------------------------ +sirv_gnrl_dfflr #(32) tcpbir5_dfflr (tcpbir5we, wrdata[31:0], tcpbir5, clk, rst_n); + +// ------------------------------------------------------ +// -- mcuresr0 +// ------------------------------------------------------ +sirv_gnrl_dffr #(32) mcuparar0_dffr (mcu_result0, mcuresr0, clk, rst_n); +// ------------------------------------------------------ +// -- mcuresr1 +// ------------------------------------------------------ +sirv_gnrl_dffr #(32) mcuparar1_dffr (mcu_result1, mcuresr1, clk, rst_n); +// ------------------------------------------------------ +// -- mcuresr2 +// ------------------------------------------------------ +sirv_gnrl_dffr #(32) mcuparar2_dffr (mcu_result2, mcuresr2, clk, rst_n); +// ------------------------------------------------------ +// -- mcuresr3 +// ------------------------------------------------------ +sirv_gnrl_dffr #(32) mcuparar3_dffr (mcu_result3, mcuresr3, clk, rst_n); + +// ------------------------------------------------------ +// -- rtimr +// ------------------------------------------------------ +sirv_gnrl_dffr #(32) rtimr_dffr (run_time, rtimr, clk, rst_n); + +// ------------------------------------------------------ +// -- icntr +// ------------------------------------------------------ +sirv_gnrl_dffr #(32) icntr_dffr (instr_num, icntr, clk, rst_n); + +// ------------------------------------------------------ +// -- fsir +// ------------------------------------------------------ +sirv_gnrl_dffr #(2) fsir_dffr (fb_st_i, fsir, clk, rst_n); + +// ------------------------------------------------------ +// -- Read data mux +// +// -- The data from the selected register is +// -- placed on a zero-padded 32-bit read data bus. +// ------------------------------------------------------ +always @(*) begin : RDDATA_PROC + rddata_reg = {32{1'b0}}; + if(mcuparar0en == H ) rddata_reg[31:0] = mcuparar0 ; + if(mcuparar1en == H ) rddata_reg[31:0] = mcuparar1 ; + if(mcuparar2en == H ) rddata_reg[31:0] = mcuparar2 ; + if(mcuparar3en == H ) rddata_reg[31:0] = mcuparar3 ; + if(mcuresr0en == H ) rddata_reg[31:0] = mcuresr0 ; + if(mcuresr1en == H ) rddata_reg[31:0] = mcuresr1 ; + if(mcuresr2en == H ) rddata_reg[31:0] = mcuresr2 ; + if(mcuresr3en == H ) rddata_reg[31:0] = mcuresr3 ; + if(rtimren == H ) rddata_reg[31:0] = rtimr ; + if(icntren == H ) rddata_reg[31:0] = icntr ; + if(fsiren == H ) rddata_reg[1 :0] = fsir ; + if(modmren == H ) rddata_reg[0 :0] = modmr ; + if(intpmren == H ) rddata_reg[2 :0] = intpmr ; + if(mixncocren == H ) rddata_reg[0 :0] = mixncocr ; + if(mixnfcwhren == H ) rddata_reg[31:0] = mixnfcwhr ; + if(mixnfcwlren == H ) rddata_reg[15:0] = mixnfcwlr ; + if(mixnpharen == H ) rddata_reg[15:0] = mixnphar ; + if(mixmren == H ) rddata_reg[0 :0] = mixmr ; + if(mixodtren == H ) rddata_reg[1 :0] = mixodtr ; + if(mixodfren == H ) rddata_reg[1 :0] = mixodfr ; + if(intpselren == H ) rddata_reg[1 :0] = intpselr ; + if(tcbpren == H ) rddata_reg[0 :0] = tcbpr ; + if(tcparr0en == H ) rddata_reg[31:0] = tcparr0 ; + if(tcparr1en == H ) rddata_reg[31:0] = tcparr1 ; + if(tcparr2en == H ) rddata_reg[31:0] = tcparr2 ; + if(tcparr3en == H ) rddata_reg[31:0] = tcparr3 ; + if(tcparr4en == H ) rddata_reg[31:0] = tcparr4 ; + if(tcparr5en == H ) rddata_reg[31:0] = tcparr5 ; + if(tcpbrr0en == H ) rddata_reg[31:0] = tcpbrr0 ; + if(tcpbrr1en == H ) rddata_reg[31:0] = tcpbrr1 ; + if(tcpbrr2en == H ) rddata_reg[31:0] = tcpbrr2 ; + if(tcpbrr3en == H ) rddata_reg[31:0] = tcpbrr3 ; + if(tcpbrr4en == H ) rddata_reg[31 :0] = tcpbrr4 ;///////// + if(tcpbrr5en == H ) rddata_reg[31:0] = tcpbrr5 ; + if(tcpair0en == H ) rddata_reg[31:0] = tcpair0 ; + if(tcpair1en == H ) rddata_reg[31:0] = tcpair1 ; + if(tcpair2en == H ) rddata_reg[31:0] = tcpair2 ; + if(tcpair3en == H ) rddata_reg[31:0] = tcpair3 ; + if(tcpair4en == H ) rddata_reg[31:0] = tcpair4 ; + if(tcpair5en == H ) rddata_reg[31:0] = tcpair5 ; + if(tcpbir0en == H ) rddata_reg[31:0] = tcpbir0 ; + if(tcpbir1en == H ) rddata_reg[31:0] = tcpbir1 ; + if(tcpbir2en == H ) rddata_reg[31:0] = tcpbir2 ; + if(tcpbir3en == H ) rddata_reg[31 :0] = tcpbir3 ;//////// + if(tcpbir4en == H ) rddata_reg[31:0] = tcpbir4 ; + if(tcpbir5en == H ) rddata_reg[31:0] = tcpbir5 ; +end + +// ------------------------------------------------------ +// -- Output signals assignment +// ------------------------------------------------------ +//mcu result +assign mcu_param0 = mcuparar0 ; +assign mcu_param1 = mcuparar1 ; +assign mcu_param2 = mcuparar2 ; +assign mcu_param3 = mcuparar3 ; + +//fb_st_o +assign fb_st_o = fsir ; +//awg cfg + assign mod_sel_sideband = modmr ; +//DSP cfg +assign qam_nco_clr = mixncocr ; +assign qam_fcw = {mixnfcwhr,mixnfcwlr} ; +assign qam_pha = mixnphar ; +assign qam_mod = mixodtr ; +assign qam_sel_sideband = mixmr ; +assign intp_mode = intpmr ; +assign intp_sel = intpselr ; +assign dac_mode_sel = mixodfr ; +assign tc_bypass = tcbpr ;////////////////////////////////////////////////////////////////////////////////// + +//rddata +sirv_gnrl_dffr #(32) rddata_dffr (rddata_reg, rddata, clk, rst_n); +endmodule + +`undef MCUPARAR0 +`undef MCUPARAR1 +`undef MCUPARAR2 +`undef MCUPARAR3 +`undef MCURESR0 +`undef MCURESR1 +`undef MCURESR2 +`undef MCURESR3 +`undef RTIMR +`undef ICNTR +`undef FSIR +`undef MODMR +`undef INTPMR +`undef MIXNCOCR +`undef MIXNFCWHR +`undef MIXNFCWLR +`undef MIXNPHAR +`undef MIXMR +`undef MIXODTR +`undef MIXODFR +`undef INTPSELR +`undef TCBPR +`undef TCPARR0 +`undef TCPARR1 +`undef TCPARR2 +`undef TCPARR3 +`undef TCPARR4 +`undef TCPARR5 +`undef TCPBRR0 +`undef TCPBRR1 +`undef TCPBRR2 +`undef TCPBRR3 +`undef TCPBRR4 +`undef TCPBRR5 +`undef TCPAIR0 +`undef TCPAIR1 +`undef TCPAIR2 +`undef TCPAIR3 +`undef TCPAIR4 +`undef TCPAIR5 +`undef TCPAIR0 +`undef TCPBIR1 +`undef TCPBIR2 +`undef TCPBIR3 +`undef TCPBIR4 +`undef TCPBIR5 diff --git a/tb/testbench/rtl/mcu_regfile.v b/tb/testbench/rtl/mcu_regfile.v new file mode 100644 index 0000000..7a45031 --- /dev/null +++ b/tb/testbench/rtl/mcu_regfile.v @@ -0,0 +1,840 @@ +//+FHDR-------------------------------------------------------------------------------------------------------- +// Company: +//----------------------------------------------------------------------------------------------------------------- +// File Name : mcu_regfile.v +// Department : +// Author : PWY +// Author's Tel : +//----------------------------------------------------------------------------------------------------------------- +// Relese History +// Version Date Author Description +// 0.1 2024-03-13 PWY MCU dedicated register file +//----------------------------------------------------------------------------------------------------------------- +// Keywords : +// +//----------------------------------------------------------------------------------------------------------------- +// Parameter +// +//----------------------------------------------------------------------------------------------------------------- +// Purpose : +// +//----------------------------------------------------------------------------------------------------------------- +// Target Device: +// Tool versions: +//----------------------------------------------------------------------------------------------------------------- +// Reuse Issues +// Reset Strategy: +// Clock Domains: +// Critical Timing: +// Asynchronous I/F: +// Synthesizable (y/n): +// Other: +//-FHDR-------------------------------------------------------------------------------------------------------- + +// ----------------------------------------------------------- +// -- Register address offset macros +// ----------------------------------------------------------- +//MCU parameter register 0 +`define MCUPARAR0 16'h00 +//MCU parameter register 1 +`define MCUPARAR1 16'h04 +//MCU parameter register 2 +`define MCUPARAR2 16'h08 +//MCU parameter register 3 +`define MCUPARAR3 16'h0C +//MCU result register 0 +`define MCURESR0 16'h10 +//MCU result register 1 +`define MCURESR1 16'h14 +//MCU result register 2 +`define MCURESR2 16'h18 +//MCU result register 3 +`define MCURESR3 16'h1C +//carrier frequency register 0 +`define CWFR0 16'h40 +//carrier frequency register 1 +`define CWFR1 16'h44 +//carrier frequency register 2 +`define CWFR2 16'h48 +//carrier frequency register 3 +`define CWFR3 16'h4C +//carrier phase zeroing register +`define CWPRR 16'h50 +//Gate-attached phase register 0 +`define GAPR0 16'h54 +//Gate-attached phase register 1 +`define GAPR1 16'h58 +//Gate-attached phase register 2 +`define GAPR2 16'h5C +//Gate-attached phase register 3 +`define GAPR3 16'h60 +//Gate-attached phase register 4 +`define GAPR4 16'h64 +//Gate-attached phase register 5 +`define GAPR5 16'h68 +//Gate-attached phase register 6 +`define GAPR6 16'h6C +//Gate-attached phase register 7 +`define GAPR7 16'h70 +//Line correction phase register +`define LCPR 16'h74 +//Amplitude register 0 +`define AMPR0 16'h78 +//Amplitude register 1 +`define AMPR1 16'h7C +//Amplitude register 2 +`define AMPR2 16'h80 +//Amplitude register 3 +`define AMPR3 16'h84 +//Bias Register 0 +`define BIASR0 16'h88 +//Bias Register 1 +`define BIASR1 16'h8C +//Bias Register 2 +`define BIASR2 16'h90 +//Bias Register 3 +`define BIASR3 16'h94 +//Run-time register +`define RTIMR 16'h98 +//Instruction count register +`define ICNTR 16'h9C +//Feedback state information register +`define FSIR 16'hA0 +//Interpolator Selection Register +`define INTPSELR 16'hA4 + +module mcu_regfile ( + //system port + input clk // System Main Clock + ,input rst_n // Spi Reset active low + //rw op port + ,input [31 :0] wrdata // write data + ,input wren // write enable + ,input [3 :0] wrmask + ,input [15 :0] rwaddr // read & write address + ,input rden // read enable + ,output [31 :0] rddata // read data + ,input [2 :0] fb_st_info + ,input [31 :0] run_time + ,input [31 :0] instr_num + //MCU and SPI interface for interaction + ,input [31 :0] mcu_param [3:0] // MCU parameter 0~3 + ,output [31 :0] mcu_result [3:0] // MCU result 0~3 + //lookup table data + ,output [31 :0] mcu_cwfr [3:0] // Carrier frequency ctrl word 0~3 + ,output [31 :0] mcu_gapr [7:0] // Carrier phase ctrl word 0~3 + ,output [31 :0] mcu_ampr [3:0] // Carrier Amplitude 0~3 + ,output [31 :0] mcu_baisr [3:0] // Carrier Bais 0~3 + //CFG Port + ,output [1 :0] mcu_intp_sel //2'b00:HBF;2'b01:Nearest-neighbor interpolator; + ,output mcu_nco_pha_clr + ,output [15 :0] mcu_rz_pha +); + +localparam L = 1'b0, + H = 1'b1; + +// ------------------------------------------------------ +// -- Register enable (select) wires +// ------------------------------------------------------ +wire mcuparar0en ; // MCUPARAR0 select +wire mcuparar1en ; // MCUPARAR1 select +wire mcuparar2en ; // MCUPARAR2 select +wire mcuparar3en ; // MCUPARAR3 select +wire mcuresr0en ; // MCURESR0 select +wire mcuresr1en ; // MCURESR1 select +wire mcuresr2en ; // MCURESR2 select +wire mcuresr3en ; // MCURESR3 select +wire cwfr0en ; // CWFR0 select +wire cwfr1en ; // CWFR1 select +wire cwfr2en ; // CWFR2 select +wire cwfr3en ; // CWFR3 select +wire cwprren ; // CWPRR select +wire gapr0en ; // GAPR0 select +wire gapr1en ; // GAPR1 select +wire gapr2en ; // GAPR2 select +wire gapr3en ; // GAPR3 select +wire gapr4en ; // GAPR4 select +wire gapr5en ; // GAPR5 select +wire gapr6en ; // GAPR6 select +wire gapr7en ; // GAPR7 select +wire lcpren ; // LCPR select +wire ampr0en ; // AMPR0 select +wire ampr1en ; // AMPR1 select +wire ampr2en ; // AMPR2 select +wire ampr3en ; // AMPR3 select +wire baisr0en ; // BIASR0 select +wire baisr1en ; // BIASR1 select +wire baisr2en ; // BIASR2 select +wire baisr3en ; // BIASR3 select +wire rtimren ; // RTIMR select +wire icntren ; // ICNTR select +wire fsiren ; // FSIR select +wire intpselren ; // INTPSELR select + +// ------------------------------------------------------ +// -- Register write enable wires +// ------------------------------------------------------ +wire mcuresr0we ; // MCURESR0 write enable +wire mcuresr1we ; // MCURESR1 write enable +wire mcuresr2we ; // MCURESR2 write enable +wire mcuresr3we ; // MCURESR3 write enable +wire cwfr0we ; // CWFR0 write enable +wire cwfr1we ; // CWFR1 write enable +wire cwfr2we ; // CWFR2 write enable +wire cwfr3we ; // CWFR3 write enable +wire cwprrwe ; // CWPRR write enable +wire gapr0we ; // GAPR0 write enable +wire gapr1we ; // GAPR1 write enable +wire gapr2we ; // GAPR2 write enable +wire gapr3we ; // GAPR3 write enable +wire gapr4we ; // GAPR4 write enable +wire gapr5we ; // GAPR5 write enable +wire gapr6we ; // GAPR6 write enable +wire gapr7we ; // GAPR7 write enable +wire lcprwe ; // LCPR write enable +wire ampr0we ; // AMPR0 write enable +wire ampr1we ; // AMPR1 write enable +wire ampr2we ; // AMPR2 write enable +wire ampr3we ; // AMPR3 write enable +wire baisr0we ; // BIASR0 write enable +wire baisr1we ; // BIASR1 write enable +wire baisr2we ; // BIASR2 write enable +wire baisr3we ; // BIASR3 write enable +wire intpselrwe ; // INTPSELR select + +// ------------------------------------------------------ +// -- Misc wires +// ------------------------------------------------------ + +// ------------------------------------------------------ +// -- Misc Registers +// ------------------------------------------------------ +reg [31 :0] mcuparar0 ; // MCUPARAR0 register +reg [31 :0] mcuparar1 ; // MCUPARAR1 register +reg [31 :0] mcuparar2 ; // MCUPARAR2 register +reg [31 :0] mcuparar3 ; // MCUPARAR3 register +reg [31 :0] mcuresr0 ; // MCURESR0 register +reg [31 :0] mcuresr1 ; // MCURESR1 register +reg [31 :0] mcuresr2 ; // MCURESR2 register +reg [31 :0] mcuresr3 ; // MCURESR3 register +reg [31 :0] cwfr0 ; // CWFR0 register +reg [31 :0] cwfr1 ; // CWFR1 register +reg [31 :0] cwfr2 ; // CWFR2 register +reg [31 :0] cwfr3 ; // CWFR3 register +reg [0 :0] cwprr ; // CWPRR register +reg [15 :0] gapr0 ; // GAPR0 register///////////16bit but assign to 31:16? +reg [15 :0] gapr1 ; // GAPR1 register +reg [15 :0] gapr2 ; // GAPR2 register +reg [15 :0] gapr3 ; // GAPR3 register +reg [15 :0] gapr4 ; // GAPR4 register +reg [15 :0] gapr5 ; // GAPR5 register +reg [15 :0] gapr6 ; // GAPR6 register +reg [15 :0] gapr7 ; // GAPR7 register +reg [15 :0] lcpr ; // LCPR register +reg [15 :0] ampr0 ; // AMPR0 register +reg [15 :0] ampr1 ; // AMPR1 register +reg [15 :0] ampr2 ; // AMPR2 register +reg [15 :0] ampr3 ; // AMPR3 register +reg [15 :0] baisr0 ; // BIASR0 register +reg [15 :0] baisr1 ; // BIASR1 register +reg [15 :0] baisr2 ; // BIASR2 register +reg [15 :0] baisr3 ; // BIASR3 register +reg [31 :0] rtimr ; // RTIMR register +reg [31 :0] icntr ; // ICNTR register +reg [1 :0] fsir ; // FSIR register +wire [1 :0] intpselr ; // INTPSELR register + +reg [31: 0] rddata_reg ; + +// ------------------------------------------------------ +// -- Address decoder +// +// Decodes the register address offset input(reg_addr) +// to produce enable (select) signals for each of the +// SW-registers in the macrocell. The reg_addr input +// is bits [15:0] of the paddr bus. +// ------------------------------------------------------ +assign mcuparar0en = (rwaddr[15:2] == `MCUPARAR0 >> 2) ? 1'b1 : 1'b0; +assign mcuparar1en = (rwaddr[15:2] == `MCUPARAR1 >> 2) ? 1'b1 : 1'b0; +assign mcuparar2en = (rwaddr[15:2] == `MCUPARAR2 >> 2) ? 1'b1 : 1'b0; +assign mcuparar3en = (rwaddr[15:2] == `MCUPARAR3 >> 2) ? 1'b1 : 1'b0; +assign mcuresr0en = (rwaddr[15:2] == `MCURESR0 >> 2) ? 1'b1 : 1'b0; +assign mcuresr1en = (rwaddr[15:2] == `MCURESR1 >> 2) ? 1'b1 : 1'b0; +assign mcuresr2en = (rwaddr[15:2] == `MCURESR2 >> 2) ? 1'b1 : 1'b0; +assign mcuresr3en = (rwaddr[15:2] == `MCURESR3 >> 2) ? 1'b1 : 1'b0; +assign cwfr0en = (rwaddr[15:2] == `CWFR0 >> 2) ? 1'b1 : 1'b0; +assign cwfr1en = (rwaddr[15:2] == `CWFR1 >> 2) ? 1'b1 : 1'b0; +assign cwfr2en = (rwaddr[15:2] == `CWFR2 >> 2) ? 1'b1 : 1'b0; +assign cwfr3en = (rwaddr[15:2] == `CWFR3 >> 2) ? 1'b1 : 1'b0; +assign cwprren = (rwaddr[15:2] == `CWPRR >> 2) ? 1'b1 : 1'b0; +assign gapr0en = (rwaddr[15:2] == `GAPR0 >> 2) ? 1'b1 : 1'b0; +assign gapr1en = (rwaddr[15:2] == `GAPR1 >> 2) ? 1'b1 : 1'b0; +assign gapr2en = (rwaddr[15:2] == `GAPR2 >> 2) ? 1'b1 : 1'b0; +assign gapr3en = (rwaddr[15:2] == `GAPR3 >> 2) ? 1'b1 : 1'b0; +assign gapr4en = (rwaddr[15:2] == `GAPR4 >> 2) ? 1'b1 : 1'b0; +assign gapr5en = (rwaddr[15:2] == `GAPR5 >> 2) ? 1'b1 : 1'b0; +assign gapr6en = (rwaddr[15:2] == `GAPR6 >> 2) ? 1'b1 : 1'b0; +assign gapr7en = (rwaddr[15:2] == `GAPR7 >> 2) ? 1'b1 : 1'b0; +assign lcpren = (rwaddr[15:2] == `LCPR >> 2) ? 1'b1 : 1'b0; +assign ampr0en = (rwaddr[15:2] == `AMPR0 >> 2) ? 1'b1 : 1'b0; +assign ampr1en = (rwaddr[15:2] == `AMPR1 >> 2) ? 1'b1 : 1'b0; +assign ampr2en = (rwaddr[15:2] == `AMPR2 >> 2) ? 1'b1 : 1'b0; +assign ampr3en = (rwaddr[15:2] == `AMPR3 >> 2) ? 1'b1 : 1'b0; +assign baisr0en = (rwaddr[15:2] == `BIASR0 >> 2) ? 1'b1 : 1'b0; +assign baisr1en = (rwaddr[15:2] == `BIASR1 >> 2) ? 1'b1 : 1'b0; +assign baisr2en = (rwaddr[15:2] == `BIASR2 >> 2) ? 1'b1 : 1'b0; +assign baisr3en = (rwaddr[15:2] == `BIASR3 >> 2) ? 1'b1 : 1'b0; +assign rtimren = (rwaddr[15:2] == `RTIMR >> 2) ? 1'b1 : 1'b0; +assign icntren = (rwaddr[15:2] == `ICNTR >> 2) ? 1'b1 : 1'b0; +assign fsiren = (rwaddr[15:2] == `FSIR >> 2) ? 1'b1 : 1'b0; +assign intpselren = (rwaddr[15:2] == `INTPSELR >> 2) ? 1'b1 : 1'b0; + +// ------------------------------------------------------ +// -- Write enable signals +// +// Write enable signals for writable SW-registers. +// The write enable for each register is the ANDed +// result of the register enable and the input reg_wren +// ------------------------------------------------------ +assign mcuresr0we = mcuresr0en & wren; +assign mcuresr1we = mcuresr1en & wren; +assign mcuresr2we = mcuresr2en & wren; +assign mcuresr3we = mcuresr3en & wren; +assign cwfr0we = cwfr0en & wren; +assign cwfr1we = cwfr1en & wren; +assign cwfr2we = cwfr2en & wren; +assign cwfr3we = cwfr3en & wren; +assign cwprrwe = cwprren & wren; +assign gapr0we = gapr0en & wren; +assign gapr1we = gapr1en & wren; +assign gapr2we = gapr2en & wren; +assign gapr3we = gapr3en & wren; +assign gapr4we = gapr4en & wren; +assign gapr5we = gapr5en & wren; +assign gapr6we = gapr6en & wren; +assign gapr7we = gapr7en & wren; +assign lcprwe = lcpren & wren; +assign ampr0we = ampr0en & wren; +assign ampr1we = ampr1en & wren; +assign ampr2we = ampr2en & wren; +assign ampr3we = ampr3en & wren; +assign baisr0we = baisr0en & wren; +assign baisr1we = baisr1en & wren; +assign baisr2we = baisr2en & wren; +assign baisr3we = baisr3en & wren; +assign intpselrwe = intpselren & wren; + +// ------------------------------------------------------ +// -- mcuresr0 register +// +// Write mcuresr0 for 'MCURESR0' : 32-bit register +// Register is split into the following bit fields +// +// [31:0] --> mcuresr0 +// ------------------------------------------------------ +wire [31:0] mcuresr0_w; +assign mcuresr0_w[31:24] = wrmask[3] ? wrdata[31:24] : mcuresr0[31:24]; +assign mcuresr0_w[23:16] = wrmask[2] ? wrdata[23:16] : mcuresr0[23:16]; +assign mcuresr0_w[15 :8] = wrmask[1] ? wrdata[15 :8] : mcuresr0[15 :8]; +assign mcuresr0_w[7 :0] = wrmask[0] ? wrdata[7 :0] : mcuresr0[7 :0]; +sirv_gnrl_dfflr #(32) mcuresr0_dfflr (mcuresr0we, mcuresr0_w[31:0], mcuresr0, clk, rst_n); +// ------------------------------------------------------ +// -- mcuresr1 register +// +// Write mcuresr1 for 'MCURESR1' : 32-bit register +// Register is split into the following bit fields +// +// [31:0] --> mcuresr1 +// ------------------------------------------------------ +wire [31:0] mcuresr1_w; +assign mcuresr1_w[31:24] = wrmask[3] ? wrdata[31:24] : mcuresr1[31:24]; +assign mcuresr1_w[23:16] = wrmask[2] ? wrdata[23:16] : mcuresr1[23:16]; +assign mcuresr1_w[15 :8] = wrmask[1] ? wrdata[15 :8] : mcuresr1[15 :8]; +assign mcuresr1_w[7 :0] = wrmask[0] ? wrdata[7 :0] : mcuresr1[7 :0]; +sirv_gnrl_dfflr #(32) mcuresr1_dfflr (mcuresr1we, mcuresr1_w[31:0], mcuresr1, clk, rst_n); +// ------------------------------------------------------ +// -- mcuresr2 register +// +// Write mcuresr2 for 'MCURESR2' : 32-bit register +// Register is split into the following bit fields +// +// [31:0] --> mcuresr2 +// ------------------------------------------------------ +wire [31:0] mcuresr2_w; +assign mcuresr2_w[31:24] = wrmask[3] ? wrdata[31:24] : mcuresr2[31:24]; +assign mcuresr2_w[23:16] = wrmask[2] ? wrdata[23:16] : mcuresr2[23:16]; +assign mcuresr2_w[15 :8] = wrmask[1] ? wrdata[15 :8] : mcuresr2[15 :8]; +assign mcuresr2_w[7 :0] = wrmask[0] ? wrdata[7 :0] : mcuresr2[7 :0]; +sirv_gnrl_dfflr #(32) mcuresr2_dfflr (mcuresr2we, mcuresr2_w[31:0], mcuresr2, clk, rst_n); +// ------------------------------------------------------ +// -- mcuresr3 register +// +// Write mcuresr3 for 'MCURESR3' : 32-bit register +// Register is split into the following bit fields +// +// [31:0] --> mcuresr3 +// ------------------------------------------------------ +wire [31:0] mcuresr3_w; +assign mcuresr3_w[31:24] = wrmask[3] ? wrdata[31:24] : mcuresr3[31:24]; +assign mcuresr3_w[23:16] = wrmask[2] ? wrdata[23:16] : mcuresr3[23:16]; +assign mcuresr3_w[15 :8] = wrmask[1] ? wrdata[15 :8] : mcuresr3[15 :8]; +assign mcuresr3_w[7 :0] = wrmask[0] ? wrdata[7 :0] : mcuresr3[7 :0]; +sirv_gnrl_dfflr #(32) mcuresr3_dfflr (mcuresr3we, mcuresr3_w[31:0], mcuresr3, clk, rst_n); + +// ------------------------------------------------------ +// -- cwfr0 register +// +// Write cwfr0 for 'CWFR0' : 32-bit register +// Register is split into the following bit fields +// +// [31:0] --> cwfr0 +// ------------------------------------------------------ +wire [31:0] cwfr0_w; +assign cwfr0_w[31:24] = wrmask[3] ? wrdata[31:24] : cwfr0[31:24]; +assign cwfr0_w[23:16] = wrmask[2] ? wrdata[23:16] : cwfr0[23:16]; +assign cwfr0_w[15 :8] = wrmask[1] ? wrdata[15 :8] : cwfr0[15 :8]; +assign cwfr0_w[7 :0] = wrmask[0] ? wrdata[7 :0] : cwfr0[7 :0]; +sirv_gnrl_dfflr #(32) cwfr0_dfflr (cwfr0we, cwfr0_w[31:0], cwfr0, clk, rst_n); +// ------------------------------------------------------ +// -- cwfr1 register +// +// Write cwfr1 for 'CWFR1' : 32-bit register +// Register is split into the following bit fields +// +// [31:16] --> cwfr1 +// ------------------------------------------------------ +wire [31:0] cwfr1_w; +assign cwfr1_w[31:24] = wrmask[3] ? wrdata[31:24] : cwfr1[31:24]; +assign cwfr1_w[23:16] = wrmask[2] ? wrdata[23:16] : cwfr1[23:16]; +assign cwfr1_w[15 :8] = wrmask[1] ? wrdata[15 :8] : cwfr1[15 :8]; +assign cwfr1_w[7 :0] = wrmask[0] ? wrdata[7 :0] : cwfr1[7 :0]; +sirv_gnrl_dfflr #(32) cwfr1_dfflr (cwfr1we, cwfr1_w[31:0], cwfr1, clk, rst_n); +// ------------------------------------------------------ +// -- cwfr2 register +// +// Write cwfr2 for 'CWFR2' : 32-bit register +// Register is split into the following bit fields +// +// [31:16] --> cwfr2 +// ------------------------------------------------------ +wire [31:0] cwfr2_w; +assign cwfr2_w[31:24] = wrmask[3] ? wrdata[31:24] : cwfr2[31:24]; +assign cwfr2_w[23:16] = wrmask[2] ? wrdata[23:16] : cwfr2[23:16]; +assign cwfr2_w[15 :8] = wrmask[1] ? wrdata[15 :8] : cwfr2[15 :8]; +assign cwfr2_w[7 :0] = wrmask[0] ? wrdata[7 :0] : cwfr2[7 :0]; +sirv_gnrl_dfflr #(32) cwfr2_dfflr (cwfr2we, cwfr2_w[31:0], cwfr2, clk, rst_n); +// ------------------------------------------------------ +// -- cwfr3 register +// +// Write cwfr3 for 'CWFR3' : 32-bit register +// Register is split into the following bit fields +// +// [31:16] --> cwfr3 +// ------------------------------------------------------ +wire [31:0] cwfr3_w; +assign cwfr3_w[31:24] = wrmask[3] ? wrdata[31:24] : cwfr3[31:24]; +assign cwfr3_w[23:16] = wrmask[2] ? wrdata[23:16] : cwfr3[23:16]; +assign cwfr3_w[15 :8] = wrmask[1] ? wrdata[15 :8] : cwfr3[15 :8]; +assign cwfr3_w[7 :0] = wrmask[0] ? wrdata[7 :0] : cwfr3[7 :0]; +sirv_gnrl_dfflr #(32) cwfr3_dfflr (cwfr3we, cwfr3_w[31:0], cwfr3, clk, rst_n); + +// ------------------------------------------------------ +// -- cwprr register(self-clearing) +// +// Write cwprr for 'CWPRR' : 32-bit register +// Register is split into the following bit fields +// +// [0] --> cwprr +// ------------------------------------------------------ +wire cwprr_w = wrmask[0] & cwprrwe & wrdata[0]; + +sirv_gnrl_dffr #(1) cwprr_dffr (cwprr_w, cwprr, clk, rst_n); + +// ------------------------------------------------------ +// -- gapr0 register +// +// Write gapr0 for 'GAPR0' : 32-bit register +// Register is split into the following bit fields +// +// [31:16] --> gapr0 +// ------------------------------------------------------ +wire [31:0] gapr0_w; +assign gapr0_w[31:24] = wrmask[3] ? wrdata[31:24] : gapr0[15: 8];///////////////////////////////////////////////////////////// +assign gapr0_w[23:16] = wrmask[2] ? wrdata[23:16] : gapr0[ 7: 0];///////////////////////////////////////////////////////////// +sirv_gnrl_dfflr #(16) gapr0_dfflr (gapr0we, gapr0_w[31:16], gapr0, clk, rst_n); + +// ------------------------------------------------------ +// -- gapr1 register +// +// Write gapr1 for 'GAPR1' : 32-bit register +// Register is split into the following bit fields +// +// [31:16] --> gapr1 +// ------------------------------------------------------ +wire [31:0] gapr1_w; +assign gapr1_w[31:24] = wrmask[3] ? wrdata[31:24] : gapr1[15: 8];///////////////////////////////////////////////////////////// +assign gapr1_w[23:16] = wrmask[2] ? wrdata[23:16] : gapr1[ 7: 0];///////////////////////////////////////////////////////////// +sirv_gnrl_dfflr #(16) gapr1_dfflr (gapr1we, gapr1_w[31:16], gapr1, clk, rst_n); +// ------------------------------------------------------ +// -- gapr2 register +// +// Write gapr2 for 'GAPR2' : 32-bit register +// Register is split into the following bit fields +// +// [31:16] --> gapr2 +// ------------------------------------------------------ +wire [31:0] gapr2_w; +assign gapr2_w[31:24] = wrmask[3] ? wrdata[31:24] : gapr2[15: 8];///////////////////////////////////////////////////////////// +assign gapr2_w[23:16] = wrmask[2] ? wrdata[23:16] : gapr2[ 7: 0];///////////////////////////////////////////////////////////// +sirv_gnrl_dfflr #(16) gapr2_dfflr (gapr2we, gapr2_w[31:16], gapr2, clk, rst_n); +// ------------------------------------------------------ +// -- gapr3 register +// +// Write gapr3 for 'GAPR3' : 32-bit register +// Register is split into the following bit fields +// +// [31:16] --> gapr3 +// ------------------------------------------------------ +wire [31:0] gapr3_w; +assign gapr3_w[31:24] = wrmask[3] ? wrdata[31:24] : gapr3[15: 8];///////////////////////////////////////////////////////////// +assign gapr3_w[23:16] = wrmask[2] ? wrdata[23:16] : gapr3[ 7: 0];///////////////////////////////////////////////////////////// +sirv_gnrl_dfflr #(16) gapr3_dfflr (gapr3we, gapr3_w[31:16], gapr3, clk, rst_n); + +// ------------------------------------------------------ +// -- gapr4 register +// +// Write gapr4 for 'GAPR4' : 32-bit register +// Register is split into the following bit fields +// +// [31:16] --> gapr4 +// ------------------------------------------------------ +wire [31:0] gapr4_w; +assign gapr4_w[31:24] = wrmask[3] ? wrdata[31:24] : gapr4[15: 8];///////////////////////////////////////////////////////////// +assign gapr4_w[23:16] = wrmask[2] ? wrdata[23:16] : gapr4[ 7: 0];///////////////////////////////////////////////////////////// +sirv_gnrl_dfflr #(16) gapr4_dfflr (gapr4we, gapr4_w[31:16], gapr4, clk, rst_n); +// ------------------------------------------------------ +// -- gapr5 register +// +// Write gapr5 for 'GAPR5' : 32-bit register +// Register is split into the following bit fields +// +// [31:16] --> gapr5 +// ------------------------------------------------------ +wire [31:0] gapr5_w; +assign gapr5_w[31:24] = wrmask[3] ? wrdata[31:24] : gapr5[15: 8];///////////////////////////////////////////////////////////// +assign gapr5_w[23:16] = wrmask[2] ? wrdata[23:16] : gapr5[ 7: 0];///////////////////////////////////////////////////////////// +sirv_gnrl_dfflr #(16) gapr5_dfflr (gapr5we, gapr5_w[31:16], gapr5, clk, rst_n); +// ------------------------------------------------------ +// -- gapr6 register +// +// Write gapr6 for 'GAPR6' : 32-bit register +// Register is split into the following bit fields +// +// [31:16] --> gapr6 +// ------------------------------------------------------ +wire [31:0] gapr6_w; +assign gapr6_w[31:24] = wrmask[3] ? wrdata[31:24] : gapr6[15: 8];///////////////////////////////////////////////////////////// +assign gapr6_w[23:16] = wrmask[2] ? wrdata[23:16] : gapr6[ 7: 0];///////////////////////////////////////////////////////////// +sirv_gnrl_dfflr #(16) gapr6_dfflr (gapr6we, gapr6_w[31:16], gapr6, clk, rst_n); +// ------------------------------------------------------ +// -- gapr7 register +// +// Write gapr7 for 'GAPR7' : 32-bit register +// Register is split into the following bit fields +// +// [31:16] --> gapr7 +// ------------------------------------------------------ +wire [31:0] gapr7_w; +assign gapr7_w[31:24] = wrmask[3] ? wrdata[31:24] : gapr7[15: 8];///////////////////////////////////////////////////////////// +assign gapr7_w[23:16] = wrmask[2] ? wrdata[23:16] : gapr7[ 7: 0];///////////////////////////////////////////////////////////// +sirv_gnrl_dfflr #(16) gapr7_dfflr (gapr7we, gapr7_w[31:16], gapr7, clk, rst_n); + + +// ------------------------------------------------------ +// -- lcpr register +// +// Write lcpr for 'LCPR' : 32-bit register +// Register is split into the following bit fields +// +// [31:16] --> lcpr +// ------------------------------------------------------ +wire [31:0] lcpr_w; +assign lcpr_w[31:24] = wrmask[3] ? wrdata[31:24] : lcpr[15: 8];///////////////////////////////////////////////////////////// +assign lcpr_w[23:16] = wrmask[2] ? wrdata[23:16] : lcpr[ 7: 0];///////////////////////////////////////////////////////////// +sirv_gnrl_dfflr #(16) lcpr_dfflr (lcprwe, lcpr_w[31:16], lcpr, clk, rst_n); + +// ------------------------------------------------------ +// -- ampr0 register +// +// Write ampr0 for 'AMPR0' : 32-bit register +// Register is split into the following bit fields +// +// [31:16] --> ampr0 +// ------------------------------------------------------ +wire [31:0] ampr0_w; +assign ampr0_w[31:24] = wrmask[3] ? wrdata[31:24] : ampr0[15: 8];///////////////////////////////////////////////////////////// +assign ampr0_w[23:16] = wrmask[2] ? wrdata[23:16] : ampr0[ 7: 0];///////////////////////////////////////////////////////////// +sirv_gnrl_dfflr #(16) ampr0_dfflr (ampr0we, ampr0_w[31:16], ampr0, clk, rst_n); + +// ------------------------------------------------------ +// -- ampr1 register +// +// Write ampr1 for 'AMPR10' : 32-bit register +// Register is split into the following bit fields +// +// [31:16] --> ampr1 +// ------------------------------------------------------ +wire [31:0] ampr1_w; +assign ampr1_w[31:24] = wrmask[3] ? wrdata[31:24] : ampr1[15: 8];///////////////////////////////////////////////////////////// +assign ampr1_w[23:16] = wrmask[2] ? wrdata[23:16] : ampr1[ 7: 0];///////////////////////////////////////////////////////////// +sirv_gnrl_dfflr #(16) ampr1_dfflr (ampr1we, ampr1_w[31:16], ampr1, clk, rst_n); + +// ------------------------------------------------------ +// -- ampr2 register +// +// Write ampr2 for 'AMPR2' : 32-bit register +// Register is split into the following bit fields +// +// [31:16] --> ampr2 +// ------------------------------------------------------ +wire [31:0] ampr2_w; +assign ampr2_w[31:24] = wrmask[3] ? wrdata[31:24] : ampr2[15: 8];///////////////////////////////////////////////////////////// +assign ampr2_w[23:16] = wrmask[2] ? wrdata[23:16] : ampr2[ 7: 0];///////////////////////////////////////////////////////////// +sirv_gnrl_dfflr #(16) ampr2_dfflr (ampr2we, ampr2_w[31:16], ampr2, clk, rst_n); + +// ------------------------------------------------------ +// -- ampr3 register +// +// Write ampr3 for 'AMPR3' : 32-bit register +// Register is split into the following bit fields +// +// [31:16] --> ampr3 +// ------------------------------------------------------ +wire [31:0] ampr3_w; +assign ampr3_w[31:24] = wrmask[3] ? wrdata[31:24] : ampr3[15: 8];///////////////////////////////////////////////////////////// +assign ampr3_w[23:16] = wrmask[2] ? wrdata[23:16] : ampr3[ 7: 0];///////////////////////////////////////////////////////////// +sirv_gnrl_dfflr #(16) ampr3_dfflr (ampr3we, ampr3_w[31:16], ampr3, clk, rst_n); + + +// ------------------------------------------------------ +// -- baisr0 register +// +// Write baisr0 for 'BIASR0' : 32-bit register +// Register is split into the following bit fields +// +// [31:16] --> baisr0 +// ------------------------------------------------------ +wire [31:0] baisr0_w; +assign baisr0_w[31:24] = wrmask[3] ? wrdata[31:24] : baisr0[15: 8];///////////////////////////////////////////////////////////// +assign baisr0_w[23:16] = wrmask[2] ? wrdata[23:16] : baisr0[ 7: 0];///////////////////////////////////////////////////////////// +sirv_gnrl_dfflr #(16) baisr0_dfflr (baisr0we, baisr0_w[31:16], baisr0, clk, rst_n); +// ------------------------------------------------------ +// -- baisr1 register +// +// Write baisr1 for 'BIASR1' : 32-bit register +// Register is split into the following bit fields +// +// [31:16] --> baisr1 +// ------------------------------------------------------ +wire [31:0] baisr1_w; +assign baisr1_w[31:24] = wrmask[3] ? wrdata[31:24] : baisr1[15: 8];///////////////////////////////////////////////////////////// +assign baisr1_w[23:16] = wrmask[2] ? wrdata[23:16] : baisr1[ 7: 0];///////////////////////////////////////////////////////////// +sirv_gnrl_dfflr #(16) baisr1_dfflr (baisr1we, baisr1_w[31:16], baisr1, clk, rst_n); +// ------------------------------------------------------ +// -- baisr2 register +// +// Write baisr2 for 'BIASR2' : 32-bit register +// Register is split into the following bit fields +// +// [31:16] --> baisr2 +// ------------------------------------------------------ +wire [31:0] baisr2_w; +assign baisr2_w[31:24] = wrmask[3] ? wrdata[31:24] : baisr2[15: 8];///////////////////////////////////////////////////////////// +assign baisr2_w[23:16] = wrmask[2] ? wrdata[23:16] : baisr2[ 7: 0];///////////////////////////////////////////////////////////// +sirv_gnrl_dfflr #(16) baisr2_dfflr (baisr2we, baisr2_w[31:16], baisr2, clk, rst_n); +// ------------------------------------------------------ +// -- baisr3 register +// +// Write baisr3 for 'BIASR3' : 32-bit register +// Register is split into the following bit fields +// +// [31:16] --> baisr3 +// ------------------------------------------------------ +wire [31:0] baisr3_w; +assign baisr3_w[31:24] = wrmask[3] ? wrdata[31:24] : baisr3[15: 8];///////////////////////////////////////////////////////////// +assign baisr3_w[23:16] = wrmask[2] ? wrdata[23:16] : baisr3[ 7: 0];///////////////////////////////////////////////////////////// +sirv_gnrl_dfflr #(16) baisr3_dfflr (baisr3we, baisr3_w[31:16], baisr3, clk, rst_n); + +// ------------------------------------------------------ +// -- intpselr register +// +// Write intpselr for 'INTPSELR' : 32-bit register +// Register is split into the following bit fields +// +// [1:0] --> intpselr +// ------------------------------------------------------ +wire [1:0] intpselr_w; +assign intpselr_w[1:0] = wrmask[0] ? wrdata[1:0] : intpselr[1:0]; +sirv_gnrl_dfflr #(2) intpselr_dfflr (intpselrwe, intpselr_w[1:0], intpselr, clk, rst_n); + + +// ------------------------------------------------------ +// -- mcuparar0 +// ------------------------------------------------------ +sirv_gnrl_dffr #(32) mcuparar0_dffr (mcu_param[0], mcuparar0, clk, rst_n); +// ------------------------------------------------------ +// -- mcuparar1 +// ------------------------------------------------------ +sirv_gnrl_dffr #(32) mcuparar1_dffr (mcu_param[1], mcuparar1, clk, rst_n); +// ------------------------------------------------------ +// -- mcuparar2 +// ------------------------------------------------------ +sirv_gnrl_dffr #(32) mcuparar2_dffr (mcu_param[2], mcuparar2, clk, rst_n); +// ------------------------------------------------------ +// -- mcuparar3 +// ------------------------------------------------------ +sirv_gnrl_dffr #(32) mcuparar3_dffr (mcu_param[3], mcuparar3, clk, rst_n); + +// ------------------------------------------------------ +// -- rtimr +// ------------------------------------------------------ +sirv_gnrl_dffr #(32) rtimr_dffr (run_time, rtimr, clk, rst_n); + +// ------------------------------------------------------ +// -- icntr +// ------------------------------------------------------ +sirv_gnrl_dffr #(32) icntr_dffr (instr_num, icntr, clk, rst_n); + +// ------------------------------------------------------ +// -- fsir +// ------------------------------------------------------ +sirv_gnrl_dffr #(2) fsir_dffr (fb_st_info, fsir, clk, rst_n); + + + + + +// ------------------------------------------------------ +// -- Read data mux +// +// -- The data from the selected register is +// -- placed on a zero-padded 32-bit read data bus. +// ------------------------------------------------------ +always @(*) begin : RDDATA_PROC + rddata_reg = {32{1'b0}}; + if(mcuparar0en == H ) rddata_reg[31:0] = mcuparar0 ; + if(mcuparar1en == H ) rddata_reg[31:0] = mcuparar1 ; + if(mcuparar2en == H ) rddata_reg[31:0] = mcuparar2 ; + if(mcuparar3en == H ) rddata_reg[31:0] = mcuparar3 ; + if(mcuresr0en == H ) rddata_reg[31:0] = mcuresr0 ; + if(mcuresr1en == H ) rddata_reg[31:0] = mcuresr1 ; + if(mcuresr2en == H ) rddata_reg[31:0] = mcuresr2 ; + if(mcuresr3en == H ) rddata_reg[31:0] = mcuresr3 ; + if(cwfr0en == H ) rddata_reg[31:0] = cwfr0 ; + if(cwfr1en == H ) rddata_reg[31:0] = cwfr1 ; + if(cwfr2en == H ) rddata_reg[31:0] = cwfr2 ; + if(cwfr3en == H ) rddata_reg[31:0] = cwfr3 ; + if(cwprren == H ) rddata_reg[0 :0] = cwprr ; + if(gapr0en == H ) rddata_reg[15:0] = gapr0 ; + if(gapr1en == H ) rddata_reg[15:0] = gapr1 ; + if(gapr2en == H ) rddata_reg[15:0] = gapr2 ; + if(gapr3en == H ) rddata_reg[15:0] = gapr3 ; + if(gapr4en == H ) rddata_reg[15:0] = gapr4 ; + if(gapr5en == H ) rddata_reg[15:0] = gapr5 ; + if(gapr6en == H ) rddata_reg[15:0] = gapr6 ; + if(gapr7en == H ) rddata_reg[15:0] = gapr7 ; + if(lcpren == H ) rddata_reg[15:0] = lcpr ; + if(ampr0en == H ) rddata_reg[15:0] = ampr0 ; + if(ampr1en == H ) rddata_reg[15:0] = ampr1 ; + if(ampr2en == H ) rddata_reg[15:0] = ampr2 ; + if(ampr3en == H ) rddata_reg[15:0] = ampr3 ; + if(baisr0en == H ) rddata_reg[15:0] = baisr0 ; + if(baisr1en == H ) rddata_reg[15:0] = baisr1 ; + if(baisr2en == H ) rddata_reg[15:0] = baisr2 ; + if(baisr3en == H ) rddata_reg[15:0] = baisr3 ; + if(rtimren == H ) rddata_reg[31:0] = rtimr ; + if(icntren == H ) rddata_reg[31:0] = icntr ; + if(fsiren == H ) rddata_reg[1 :0] = fsir ; + if(intpselren == H ) rddata_reg[1 :0] = intpselr ;//////////////////////////////////////////////////////////// +end + +// ------------------------------------------------------ +// -- Output signals assignment +// ------------------------------------------------------ +//mcu result +assign mcu_result[0] = mcuresr0 ; +assign mcu_result[1] = mcuresr1 ; +assign mcu_result[2] = mcuresr2 ; +assign mcu_result[3] = mcuresr3 ; + +//nco_fwc lookup table output +assign mcu_cwfr[0] = cwfr0; +assign mcu_cwfr[1] = cwfr1; +assign mcu_cwfr[2] = cwfr2; +assign mcu_cwfr[3] = cwfr3; + +//nco_pha lookup table output +assign mcu_gapr[0] = gapr0; +assign mcu_gapr[1] = gapr1; +assign mcu_gapr[2] = gapr2; +assign mcu_gapr[3] = gapr3; +assign mcu_gapr[4] = gapr4; +assign mcu_gapr[5] = gapr5; +assign mcu_gapr[6] = gapr6; +assign mcu_gapr[7] = gapr7; + +//amp lookup table output +assign mcu_ampr[0] = ampr0; +assign mcu_ampr[1] = ampr1; +assign mcu_ampr[2] = ampr2; +assign mcu_ampr[3] = ampr3; + +//bais lookup table output +assign mcu_baisr[0] = baisr0; +assign mcu_baisr[1] = baisr1; +assign mcu_baisr[2] = baisr2; +assign mcu_baisr[3] = baisr3; + +//CFG Port +assign mcu_nco_pha_clr = cwprr; +assign mcu_rz_pha = lcpr; +assign mcu_intp_sel = intpselr; +//rddata +//assign rddata = rddata_reg ; +sirv_gnrl_dffr #(32) rddata_dffr (rddata_reg, rddata, clk, rst_n);//////////////////////// +endmodule + +`undef MCUPARAR0 +`undef MCUPARAR1 +`undef MCUPARAR2 +`undef MCUPARAR3 +`undef MCURESR0 +`undef MCURESR1 +`undef MCURESR2 +`undef MCURESR3 +`undef CWFR0 +`undef CWFR1 +`undef CWFR2 +`undef CWFR3 +`undef CWPRR +`undef GAPR0 +`undef GAPR1 +`undef GAPR2 +`undef GAPR3 +`undef GAPR4 +`undef GAPR5 +`undef GAPR6 +`undef GAPR7 +`undef LCPR +`undef AMPR0 +`undef AMPR1 +`undef AMPR2 +`undef AMPR3 +`undef BIASR0 +`undef BIASR1 +`undef BIASR2 +`undef BIASR3 +`undef RTIMR +`undef ICNTR +`undef FSIR diff --git a/tb/testbench/rtl/ram_if.sv b/tb/testbench/rtl/ram_if.sv new file mode 100644 index 0000000..e8159d5 --- /dev/null +++ b/tb/testbench/rtl/ram_if.sv @@ -0,0 +1,32 @@ + + + + +interface ram_if(input clk, input rst_n); + +logic [31 :0] wrdata ; // write data +logic wren ; // write enable +logic [24 :0] rwaddr ; // read & write address +logic rden ; // read enable +logic [31 :0] rddata ; // read data + +//master +modport m ( + output wrdata + ,output wren + ,output rwaddr + ,output rden + ,input rddata +); + + +//slave +modport s ( + input wrdata + ,input wren + ,input rwaddr + ,input rden + ,output rddata +); + +endinterface \ No newline at end of file diff --git a/tb/testbench/rtl/sirv_gnrl_dffs.v b/tb/testbench/rtl/sirv_gnrl_dffs.v new file mode 100644 index 0000000..b55ff2c --- /dev/null +++ b/tb/testbench/rtl/sirv_gnrl_dffs.v @@ -0,0 +1,326 @@ + /* + Copyright 2018-2020 Nuclei System Technology, Inc. + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + */ + + + +//===================================================================== +// +// Designer : Bob Hu +// +// Description: +// All of the general DFF and Latch modules +// +// ==================================================================== + +// + + +// +// =========================================================================== +// +// Description: +// Verilog module sirv_gnrl DFF with Load-enable and Reset +// Default reset value is 1 +// +// =========================================================================== +`define DISABLE_SV_ASSERTION +`define dly #0.001 +module sirv_gnrl_dfflrs # ( + parameter DW = 32 +) ( + + input lden, + input [DW-1:0] dnxt, + output [DW-1:0] qout, + + input clk, + input rst_n +); + +reg [DW-1:0] qout_r; + +always @(posedge clk or negedge rst_n) +begin : DFFLRS_PROC + if (rst_n == 1'b0) + qout_r <= {DW{1'b1}}; + else if (lden == 1'b1) + qout_r <= `dly dnxt; +end + +assign qout = qout_r; + +`ifndef FPGA_SOURCE//{ +`ifndef DISABLE_SV_ASSERTION//{ +//synopsys translate_off +sirv_gnrl_xchecker # ( + .DW(1) +) sirv_gnrl_xchecker( + .i_dat(lden), + .clk (clk) +); +//synopsys translate_on +`endif//} +`endif//} + + +endmodule +// =========================================================================== +// +// Description: +// Verilog module sirv_gnrl DFF with Load-enable and Reset +// Default reset value is 0 +// +// =========================================================================== + +module sirv_gnrl_dfflr # ( + parameter DW = 32 +) ( + + input lden, + input [DW-1:0] dnxt, + output [DW-1:0] qout, + + input clk, + input rst_n +); + +reg [DW-1:0] qout_r; + +always @(posedge clk or negedge rst_n) +begin : DFFLR_PROC + if (rst_n == 1'b0) + qout_r <= {DW{1'b0}}; + else if (lden == 1'b1) + qout_r <= `dly dnxt; +end + +assign qout = qout_r; + +`ifndef FPGA_SOURCE//{ +`ifndef DISABLE_SV_ASSERTION//{ +//synopsys translate_off +sirv_gnrl_xchecker # ( + .DW(1) +) sirv_gnrl_xchecker( + .i_dat(lden), + .clk (clk) +); +//synopsys translate_on +`endif//} +`endif//} + + +endmodule + +// =========================================================================== +// +// Description: +// Verilog module sirv_gnrl DFF with Load-enable and Reset +// Default reset value is input +// +// =========================================================================== + +module sirv_gnrl_dfflrd # ( + parameter DW = 32 +) ( + input [DW-1:0] init, + input lden, + input [DW-1:0] dnxt, + output [DW-1:0] qout, + + input clk, + input rst_n +); + +reg [DW-1:0] qout_r; + +always @(posedge clk or negedge rst_n) +begin : DFFLR_PROC + if (rst_n == 1'b0) + qout_r <= init; + else if (lden == 1'b1) + qout_r <= `dly dnxt; +end + +assign qout = qout_r; + +`ifndef FPGA_SOURCE//{ +`ifndef DISABLE_SV_ASSERTION//{ +//synopsys translate_off +sirv_gnrl_xchecker # ( + .DW(1) +) sirv_gnrl_xchecker( + .i_dat(lden), + .clk (clk) +); +//synopsys translate_on +`endif//} +`endif//} + + +endmodule + +// =========================================================================== +// +// Description: +// Verilog module sirv_gnrl DFF with Load-enable, no reset +// +// =========================================================================== + +module sirv_gnrl_dffl # ( + parameter DW = 32 +) ( + + input lden, + input [DW-1:0] dnxt, + output [DW-1:0] qout, + + input clk +); + +reg [DW-1:0] qout_r; + +always @(posedge clk) +begin : DFFL_PROC + if (lden == 1'b1) + qout_r <= `dly dnxt; +end + +assign qout = qout_r; + +`ifndef FPGA_SOURCE//{ +`ifndef DISABLE_SV_ASSERTION//{ +//synopsys translate_off +sirv_gnrl_xchecker # ( + .DW(1) +) sirv_gnrl_xchecker( + .i_dat(lden), + .clk (clk) +); +//synopsys translate_on +`endif//} +`endif//} + + +endmodule +// =========================================================================== +// +// Description: +// Verilog module sirv_gnrl DFF with Reset, no load-enable +// Default reset value is 1 +// +// =========================================================================== + +module sirv_gnrl_dffrs # ( + parameter DW = 32 +) ( + + input [DW-1:0] dnxt, + output [DW-1:0] qout, + + input clk, + input rst_n +); + +reg [DW-1:0] qout_r; + +always @(posedge clk or negedge rst_n) +begin : DFFRS_PROC + if (rst_n == 1'b0) + qout_r <= {DW{1'b1}}; + else + qout_r <= `dly dnxt; +end + +assign qout = qout_r; + +endmodule +// =========================================================================== +// +// Description: +// Verilog module sirv_gnrl DFF with Reset, no load-enable +// Default reset value is 0 +// +// =========================================================================== + +module sirv_gnrl_dffr # ( + parameter DW = 32 +) ( + + input [DW-1:0] dnxt, + output [DW-1:0] qout, + + input clk, + input rst_n +); + +reg [DW-1:0] qout_r; + +always @(posedge clk or negedge rst_n) +begin : DFFR_PROC + if (rst_n == 1'b0) + qout_r <= {DW{1'b0}}; + else + qout_r <= `dly dnxt; +end + +assign qout = qout_r; + +endmodule +// =========================================================================== +// +// Description: +// Verilog module for general latch +// +// =========================================================================== + +module sirv_gnrl_ltch # ( + parameter DW = 32 +) ( + + //input test_mode, + input lden, + input [DW-1:0] dnxt, + output [DW-1:0] qout +); + +reg [DW-1:0] qout_r; + +always @ * +begin : LTCH_PROC + if (lden == 1'b1) + qout_r <= dnxt; +end + +//assign qout = test_mode ? dnxt : qout_r; +assign qout = qout_r; + +`ifndef FPGA_SOURCE//{ +`ifndef DISABLE_SV_ASSERTION//{ +//synopsys translate_off +always_comb +begin + CHECK_THE_X_VALUE: + assert (lden !== 1'bx) + else $fatal ("\n Error: Oops, detected a X value!!! This should never happen. \n"); +end + +//synopsys translate_on +`endif//} +`endif//} + + +endmodule diff --git a/tb/testbench/rtl/sirv_gnrl_xchecker.v b/tb/testbench/rtl/sirv_gnrl_xchecker.v new file mode 100644 index 0000000..6e9df85 --- /dev/null +++ b/tb/testbench/rtl/sirv_gnrl_xchecker.v @@ -0,0 +1,49 @@ + /* + Copyright 2018-2020 Nuclei System Technology, Inc. + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + */ + + + +//===================================================================== +// +// Designer : Bob Hu +// +// Description: +// Verilog module for X checker +// +// ==================================================================== + + +`ifndef FPGA_SOURCE//{ +`ifndef DISABLE_SV_ASSERTION//{ +//synopsys translate_off +module sirv_gnrl_xchecker # ( + parameter DW = 32 +) ( + input [DW-1:0] i_dat, + input clk +); + + +CHECK_THE_X_VALUE: + assert property (@(posedge clk) + ((^(i_dat)) !== 1'bx) + ) + else $fatal ("\n Error: Oops, detected a X value!!! This should never happen. \n"); + +endmodule +//synopsys translate_on +`endif//} +`endif//} diff --git a/tb/testbench/rtl/spi_bus_decoder.sv b/tb/testbench/rtl/spi_bus_decoder.sv new file mode 100644 index 0000000..daa71ce --- /dev/null +++ b/tb/testbench/rtl/spi_bus_decoder.sv @@ -0,0 +1,88 @@ +//+FHDR-------------------------------------------------------------------------------------------------------- +// Company: +//----------------------------------------------------------------------------------------------------------------- +// File Name : spi_bus_decoder.v +// Department : +// Author : PWY +// Author's Tel : +//----------------------------------------------------------------------------------------------------------------- +// Relese History +// Version Date Author Description +// 0.1 2024-03-13 PWY Serial Peripheral Interface BUS Decoder +//----------------------------------------------------------------------------------------------------------------- +// Keywords : +// +//----------------------------------------------------------------------------------------------------------------- +// Parameter +// +//----------------------------------------------------------------------------------------------------------------- +// Purpose : +// +//----------------------------------------------------------------------------------------------------------------- +// Target Device: +// Tool versions: +//----------------------------------------------------------------------------------------------------------------- +// Reuse Issues +// Reset Strategy: +// Clock Domains: +// Critical Timing: +// Asynchronous I/F: +// Synthesizable (y/n): +// Other: +//-FHDR-------------------------------------------------------------------------------------------------------- + +module spi_bus_decoder #( + parameter SLVNUM = 32 + ,parameter SPIBUS_CMD_REG = 1 + ,parameter SPIBUS_OUT_REG = 1 + )( + input clk + ,input rst_n + ,sram_if.slave mst + ,sram_if.master slv [SLVNUM-1:0] //s and m exchange + ); + + +generate + genvar i; + logic [SLVNUM-1:0] cs_slv; + logic [31 :0] dtemp[SLVNUM-1:0]; + + for(i=0;i 0:write,1:read +reg cmd_reg; +//rxs_reg +reg rxs_reg; +//addr_reg--> initial address +reg [24 :0] addr_reg; +//rxd_reg --> recive data +reg [31 :0] rxd_reg; + +//rx; +reg [9 :0] rxcnt; +wire add_rxcnt; +wire end_rxcnt; + +wire wr_times; +reg recv_start; +reg wren_reg; +reg wren_reg_1; +reg [31 :0] wrdata_reg; + +//send data +reg [31 :0] txd_reg; +//tx; +reg [9 :0] txcnt; +wire add_txcnt; +wire end_txcnt; + +reg trans_start; + +//read write address +reg [24:0] rwaddr_reg; +reg address_start; +wire add_addr_wr; +wire add_addr_rd; + +//read rddata to txd_reg +reg rd_times; +//read sram +wire rd_sram; //foreread + +//output enable +reg miso_reg; +reg miso_oen_reg; + +//data form check +reg error_check_reg ; + +reg [9:0] frame_len; + + + + +////////////////////////////////////////////////////////////////////////// +//capture the sck +////////////////////////////////////////////////////////////////////////// +//sync sclk to the main clock using a 3-bits shift register +always @(posedge clk or negedge spi_rstn) begin + if(spi_rstn == L) begin + sclk_reg <= 3'b000; + end + else begin + sclk_reg <= {sclk_reg[1:0],sclk}; + end +end + +//sclk's rising edges +assign sclk_p = (sclk_reg[2:1] == 2'b01); + +//sclk's falling edges +assign sclk_n = (sclk_reg[2:1] == 2'b10); + +////////////////////////////////////////////////////////////////////////// +//capture the csn +////////////////////////////////////////////////////////////////////////// +//sync csn to the main clock using a 3-bits shift register +always @(posedge clk or negedge spi_rstn) begin + if(spi_rstn == L) begin + csn_reg <= 5'b11111; + end + else begin + csn_reg <= {csn_reg[3:0],csn}; + end +end + +// csn is active low +assign csn_active = ~csn_reg[1]; + +////////////////////////////////////////////////////////////////////////// +//capture the mosi +////////////////////////////////////////////////////////////////////////// +//sync mosi to the main clock using a 2-bits shift register +always @(posedge clk or negedge spi_rstn) begin + if(spi_rstn == L) begin + mosi_reg <= 2'b00; + end + else begin + mosi_reg <= {mosi_reg[0],mosi}; + end +end + +//mosi_data +assign mosi_data = mosi_reg[1]; + +////////////////////////////////////////////////////////////////////////// +//rxcnt +////////////////////////////////////////////////////////////////////////// +always @(posedge clk or negedge spi_rstn) begin + if(spi_rstn == L) begin + rxcnt <= 10'd0; + end + else if(end_rxcnt) begin + rxcnt <= 10'd0; + end + else if (add_rxcnt)begin + rxcnt <= rxcnt + 1'b1; + end + else begin + rxcnt <= rxcnt; + end +end + +//add_rxcnt +assign add_rxcnt = sclk_p && csn_active; +assign end_rxcnt = add_rxcnt & (rxcnt == frame_len - 1'b1); +assign wr_times = add_rxcnt & (rxcnt[4:0] == 5'd31) & ~cmd_reg; + +////////////////////////////////////////////////////////////////////////// +//cmd_reg +////////////////////////////////////////////////////////////////////////// +always @(posedge clk or negedge spi_rstn) begin + if(spi_rstn == L) begin + cmd_reg <= 1'b0; + end + else if(add_rxcnt && rxcnt == 10'd0 ) begin + cmd_reg <= mosi_data; + end + else begin + cmd_reg <= cmd_reg; + end +end + +////////////////////////////////////////////////////////////////////////// +//rxs_reg +////////////////////////////////////////////////////////////////////////// +always @(posedge clk or negedge spi_rstn) begin + if(spi_rstn == L ) begin + rxs_reg <= 1'b0; + end + else if(add_rxcnt && rxcnt == 10'd1) begin + rxs_reg <= mosi_data; + end + else begin + rxs_reg <= rxs_reg; + end +end + +////////////////////////////////////////////////////////////////////////// +//addr_reg +////////////////////////////////////////////////////////////////////////// +always @(posedge clk or negedge spi_rstn) begin + if(spi_rstn == L ) begin + addr_reg <= 25'd0; + end + else if(add_rxcnt && rxcnt <= 10'd26 ) begin + addr_reg <= {addr_reg[23:0],mosi_data}; + end + else begin + addr_reg <= addr_reg; + end +end + +////////////////////////////////////////////////////////////////////////// +//rxd_reg +////////////////////////////////////////////////////////////////////////// +always @(posedge clk or negedge spi_rstn) begin + if(spi_rstn == L) begin + rxd_reg <= 32'd0; + end + else if(add_rxcnt) begin + rxd_reg <= {rxd_reg[30:0],mosi_data}; + end + else begin + rxd_reg <= rxd_reg; + end +end + +////////////////////////////////////////////////////////////////////////// +//frame_len +////////////////////////////////////////////////////////////////////////// +always @(posedge clk or negedge spi_rstn) begin + if(spi_rstn == L) begin + frame_len <= 10'd0; + end + else if(add_rxcnt && rxcnt == 10'd2) begin + if(rxs_reg) begin + frame_len <= 10'd544; + end + else begin + frame_len <= 10'd64; + end + end + else begin + frame_len <= frame_len; + end +end +////////////////////////////////////////////////////////////////////////// +//recv_start +////////////////////////////////////////////////////////////////////////// + +always @(posedge clk or negedge spi_rstn) begin + if(spi_rstn == L) begin + recv_start <= 1'b0; + end + else if(~csn_active )begin + recv_start <= 1'b0; + end + else if(wr_times)begin + recv_start <= 1'b1; + end + else begin + recv_start <= recv_start; + end +end + +////////////////////////////////////////////////////////////////////////// +//wren_reg +////////////////////////////////////////////////////////////////////////// + +always @(posedge clk or negedge spi_rstn) begin + if(spi_rstn == L) begin + wren_reg <= 1'b0; + end + else begin + wren_reg <= recv_start & wr_times ; + wren_reg_1 <= wren_reg; + end +end + + +////////////////////////////////////////////////////////////////////////// +//wrdata_reg +////////////////////////////////////////////////////////////////////////// +always @(posedge clk or negedge spi_rstn) begin + if(spi_rstn == L) begin + wrdata_reg <= 32'b0; + end + else if(wren_reg)begin + wrdata_reg <= rxd_reg; + end +end + +////////////////////////////////////////////////////////////////////////// +//txcnt +////////////////////////////////////////////////////////////////////////// +always @(posedge clk or negedge spi_rstn) begin + if(spi_rstn == L) begin + txcnt <= 10'd0; + end + else if(end_txcnt) begin + txcnt <= 10'd0; + end + else if (add_txcnt)begin + txcnt <= txcnt + 1'b1; + end + else begin + txcnt <= txcnt; + end +end +//add_txcnt +assign add_txcnt = sclk_n && csn_active; +//end_txcnt +assign end_txcnt = add_txcnt && (txcnt == frame_len - 1'b1) ; + + + +////////////////////////////////////////////////////////////////////////// +//rd_times +////////////////////////////////////////////////////////////////////////// + +always@(*)begin + if(rxs_reg)begin + rd_times = add_txcnt & (txcnt[4:0] == 5'd31)& (txcnt != 10'd543) & cmd_reg; + end + else begin + rd_times = add_txcnt & (txcnt[4:0] == 5'd31)& (txcnt != 10'd63) & cmd_reg; + end +end + +//rd_sram foreread +//assign rd_sram = (rd_times) | (add_txcnt & (txcnt[9:0] == 5'd30) & cmd_reg) ; +assign rd_sram = rd_times & cmd_reg; + + +////////////////////////////////////////////////////////////////////////// +//trans_start +////////////////////////////////////////////////////////////////////////// + +always @(posedge clk or negedge spi_rstn) begin + if(spi_rstn == L) begin + trans_start <= 1'b0; + end + else if(rd_times)begin + trans_start <= 1'b1; + end + else if(~csn_active)begin + trans_start <= 1'b0; + end + else begin + trans_start <= trans_start; + end +end + + +////////////////////////////////////////////////////////////////////////// +//txd_reg +////////////////////////////////////////////////////////////////////////// + + +reg [2:0] rd_times_r; +always @(posedge clk or negedge spi_rstn) begin + if(spi_rstn == L) begin + rd_times_r <= 3'b0; + end + else begin + rd_times_r <= {rd_times_r[1:0],rd_times}; + end +end + + +always @(posedge clk or negedge spi_rstn) begin + if(spi_rstn == L) begin + txd_reg <= 32'h0; + end + else if(rd_times_r[2]) begin + txd_reg <= rddata; + end + else if(add_txcnt && trans_start && txcnt[4:0]!=5'd31) begin + txd_reg <= {txd_reg[30:0],1'b0}; + end + else begin + txd_reg <= txd_reg; + end +end +////////////////////////////////////////////////////////////////////////// +//address_start +////////////////////////////////////////////////////////////////////////// + +always @(posedge clk or negedge spi_rstn) begin + if(spi_rstn == L) begin + address_start <= 1'b0; + end + else if(txcnt == 10'd29)begin + address_start <= 1'b1; + end + else if(~csn_active)begin + address_start <= 1'b0; + end + else begin + address_start <= address_start; + end +end + +////////////////////////////////////////////////////////////////////////// +//rwaddr_reg +////////////////////////////////////////////////////////////////////////// + +always @(posedge clk or negedge spi_rstn) begin + if(spi_rstn == L) begin + rwaddr_reg <= 25'b0; + end + else if(address_start)begin + if(add_addr_wr)begin + rwaddr_reg <= rwaddr_reg + 3'd4; + end + else if(add_addr_rd)begin + rwaddr_reg <= rwaddr_reg + 3'd4; + end + else begin + rwaddr_reg <= rwaddr_reg; + end + end + else begin + rwaddr_reg <= addr_reg; + end +end + + +assign add_addr_wr = rxs_reg & wren_reg_1 ; +assign add_addr_rd = rxs_reg & rd_sram ; + +////////////////////////////////////////////////////////////////////////// +//miso_reg +////////////////////////////////////////////////////////////////////////// +always @(posedge clk or negedge spi_rstn) begin + if(spi_rstn == L) begin + miso_reg <= 1'b0; + end + else begin + miso_reg <= txd_reg[31]; + end +end + +////////////////////////////////////////////////////////////////////////// +//miso_oen_reg +////////////////////////////////////////////////////////////////////////// +always @(posedge clk or negedge spi_rstn) begin + if(spi_rstn == L) begin + miso_oen_reg <= 1'b1; + end + else begin + miso_oen_reg <= ~(trans_start & cmd_reg); + end +end + +////////////////////////////////////////////////////////////////////////// +//error_check +////////////////////////////////////////////////////////////////////////// +always @(posedge clk or negedge spi_rstn) begin + if(spi_rstn == L) begin + error_check_reg <= 1'b0; + end + else if( (rxcnt != 0 || txcnt != 0)&&(~csn_active) )begin + error_check_reg <= 1'b1; + end +end + +////////////////////////////////////////////////////////////////////////// +//Outputs signals +////////////////////////////////////////////////////////////////////////// +//wren +assign wren = wren_reg_1 ; +//wrdata +assign wrdata = wrdata_reg; +//rden +assign rden = rd_sram ; +//addr +assign addr = rwaddr_reg; +//miso +assign miso = miso_reg; +//miso_oen +assign miso_oen = miso_oen_reg; +//error_check +assign error_check = error_check_reg; + +endmodule + + diff --git a/tb/testbench/rtl/spi_to_sram.v.bak b/tb/testbench/rtl/spi_to_sram.v.bak new file mode 100644 index 0000000..a26bc92 --- /dev/null +++ b/tb/testbench/rtl/spi_to_sram.v.bak @@ -0,0 +1,518 @@ +//+FHDR-------------------------------------------------------------------------------------------------------- +// Company: +//----------------------------------------------------------------------------------------------------------------- +// File Name : spi_to_sram_v1.2.v +// Department : +// Author : ZYZ +// Author's Tel : +//----------------------------------------------------------------------------------------------------------------- +// Relese History +// Version Date Author Description +// 1.2 2024-04-02 ZYZ +//----------------------------------------------------------------------------------------------------------------- +// Keywords : 1.replace stream mode of send 32bit data 16 times +// 2.wrdata_reg address is no longer related to csn_active +//----------------------------------------------------------------------------------------------------------------- +// Parameter +// +//----------------------------------------------------------------------------------------------------------------- +// Purpose : +// +//----------------------------------------------------------------------------------------------------------------- +// Target Device: +// Tool versions: +//----------------------------------------------------------------------------------------------------------------- +// Reuse Issues +// Reset Strategy: +// Clock Domains: +// Critical Timing: +// Asynchronous I/F: +// Synthesizable (y/n): +// Other: +//-FHDR-------------------------------------------------------------------------------------------------------- + + + +module spi_to_sram ( + //system port + input clk // System Main Clock + ,input spi_rstn // Spi Reset active low + //spi port + ,input sclk // Spi Clock + ,input csn // Spi Chip Select active low + ,input mosi // Spi Mosi + ,output miso // Spi Miso + ,output miso_oen // Spi Miso output enable + ,output error_check // spi form check + + ,output [31:0] wrdata //write data to sram + ,output [24:0] addr //sram address + ,output wren //write enable sram + ,output rden //rden enable sram + ,input [31:0] rddata //read data from sram + +); + +localparam L = 1'b0, + H = 1'b1; + +//3-bits shift register for sclk's rising & falling edges +reg [2 :0] sclk_reg; +wire sclk_p; +wire sclk_n; + +//3-bits shift register for csn +reg [4 :0] csn_reg; +wire csn_active; + +//2-bits shift register for mosi +reg [1 :0] mosi_reg; +wire mosi_data; + +//cmd_reg--> 0:write,1:read +reg cmd_reg; +//rxs_reg +reg rxs_reg; +//addr_reg--> initial address +reg [24 :0] addr_reg; +//rxd_reg --> recive data +reg [31 :0] rxd_reg; + +//rx; +reg [9 :0] rxcnt; +wire add_rxcnt; +wire end_rxcnt; + +wire wr_times; +reg recv_start; +reg wren_reg; +reg wren_reg_1; +reg [31 :0] wrdata_reg; + +//send data +reg [31 :0] txd_reg; +//tx; +reg [9 :0] txcnt; +wire add_txcnt; +wire end_txcnt; + +reg trans_start; + +//read write address +reg [24:0] rwaddr_reg; +reg address_start; +wire add_addr_wr; +wire add_addr_rd; + +//read rddata to txd_reg +reg rd_times; +//read sram +wire rd_sram; //foreread + +//output enable +reg miso_reg; +reg miso_oen_reg; + +//data form check +reg error_check_reg ; + +reg [9:0] frame_len; + + + + +////////////////////////////////////////////////////////////////////////// +//capture the sck +////////////////////////////////////////////////////////////////////////// +//sync sclk to the main clock using a 3-bits shift register +always @(posedge clk or negedge spi_rstn) begin + if(spi_rstn == L) begin + sclk_reg <= 3'b000; + end + else begin + sclk_reg <= {sclk_reg[1:0],sclk}; + end +end + +//sclk's rising edges +assign sclk_p = (sclk_reg[2:1] == 2'b01); + +//sclk's falling edges +assign sclk_n = (sclk_reg[2:1] == 2'b10); + +////////////////////////////////////////////////////////////////////////// +//capture the csn +////////////////////////////////////////////////////////////////////////// +//sync csn to the main clock using a 3-bits shift register +always @(posedge clk or negedge spi_rstn) begin + if(spi_rstn == L) begin + csn_reg <= 5'b11111; + end + else begin + csn_reg <= {csn_reg[3:0],csn}; + end +end + +// csn is active low +assign csn_active = ~csn_reg[1]; + +////////////////////////////////////////////////////////////////////////// +//capture the mosi +////////////////////////////////////////////////////////////////////////// +//sync mosi to the main clock using a 2-bits shift register +always @(posedge clk or negedge spi_rstn) begin + if(spi_rstn == L) begin + mosi_reg <= 2'b00; + end + else begin + mosi_reg <= {mosi_reg[0],mosi}; + end +end + +//mosi_data +assign mosi_data = mosi_reg[1]; + +////////////////////////////////////////////////////////////////////////// +//rxcnt +////////////////////////////////////////////////////////////////////////// +always @(posedge clk or negedge spi_rstn) begin + if(spi_rstn == L) begin + rxcnt <= 10'd0; + end + else if(end_rxcnt) begin + rxcnt <= 10'd0; + end + else if (add_rxcnt)begin + rxcnt <= rxcnt + 1'b1; + end + else begin + rxcnt <= rxcnt; + end +end + +//add_rxcnt +assign add_rxcnt = sclk_p && csn_active; +assign end_rxcnt = add_rxcnt & (rxcnt == frame_len - 1'b1); +assign wr_times = add_rxcnt & (rxcnt[4:0] == 5'd31) & ~cmd_reg; + +////////////////////////////////////////////////////////////////////////// +//cmd_reg +////////////////////////////////////////////////////////////////////////// +always @(posedge clk or negedge spi_rstn) begin + if(spi_rstn == L) begin + cmd_reg <= 1'b0; + end + else if(add_rxcnt && rxcnt == 10'd0 ) begin + cmd_reg <= mosi_data; + end + else begin + cmd_reg <= cmd_reg; + end +end + +////////////////////////////////////////////////////////////////////////// +//rxs_reg +////////////////////////////////////////////////////////////////////////// +always @(posedge clk or negedge spi_rstn) begin + if(spi_rstn == L ) begin + rxs_reg <= 1'b0; + end + else if(add_rxcnt && rxcnt == 10'd1) begin + rxs_reg <= mosi_data; + end + else begin + rxs_reg <= rxs_reg; + end +end + +////////////////////////////////////////////////////////////////////////// +//addr_reg +////////////////////////////////////////////////////////////////////////// +always @(posedge clk or negedge spi_rstn) begin + if(spi_rstn == L ) begin + addr_reg <= 25'd0; + end + else if(add_rxcnt && rxcnt <= 10'd26 ) begin + addr_reg <= {addr_reg[23:0],mosi_data}; + end + else begin + addr_reg <= addr_reg; + end +end + +////////////////////////////////////////////////////////////////////////// +//rxd_reg +////////////////////////////////////////////////////////////////////////// +always @(posedge clk or negedge spi_rstn) begin + if(spi_rstn == L) begin + rxd_reg <= 32'd0; + end + else if(add_rxcnt) begin + rxd_reg <= {rxd_reg[30:0],mosi_data}; + end + else begin + rxd_reg <= rxd_reg; + end +end + +////////////////////////////////////////////////////////////////////////// +//frame_len +////////////////////////////////////////////////////////////////////////// +always @(posedge clk or negedge spi_rstn) begin + if(spi_rstn == L) begin + frame_len <= 10'd0; + end + else if(add_rxcnt && rxcnt == 10'd2) begin + if(rxs_reg) begin + frame_len <= 10'd544; + end + else begin + frame_len <= 10'd64; + end + end + else begin + frame_len <= frame_len; + end +end +////////////////////////////////////////////////////////////////////////// +//recv_start +////////////////////////////////////////////////////////////////////////// + +always @(posedge clk or negedge spi_rstn) begin + if(spi_rstn == L) begin + recv_start <= 1'b0; + end + else if(~csn_active )begin + recv_start <= 1'b0; + end + else if(wr_times)begin + recv_start <= 1'b1; + end + else begin + recv_start <= recv_start; + end +end + +////////////////////////////////////////////////////////////////////////// +//wren_reg +////////////////////////////////////////////////////////////////////////// + +always @(posedge clk or negedge spi_rstn) begin + if(spi_rstn == L) begin + wren_reg <= 1'b0; + end + else begin + wren_reg <= recv_start & wr_times ; + wren_reg_1 <= wren_reg; + end +end + + +////////////////////////////////////////////////////////////////////////// +//wrdata_reg +////////////////////////////////////////////////////////////////////////// +always @(posedge clk or negedge spi_rstn) begin + if(spi_rstn == L) begin + wrdata_reg <= 32'b0; + end + else if(wren_reg)begin + wrdata_reg <= rxd_reg; + end +end + +////////////////////////////////////////////////////////////////////////// +//txcnt +////////////////////////////////////////////////////////////////////////// +always @(posedge clk or negedge spi_rstn) begin + if(spi_rstn == L) begin + txcnt <= 10'd0; + end + else if(end_txcnt) begin + txcnt <= 10'd0; + end + else if (add_txcnt)begin + txcnt <= txcnt + 1'b1; + end + else begin + txcnt <= txcnt; + end +end +//add_txcnt +assign add_txcnt = sclk_n && csn_active; +//end_txcnt +assign end_txcnt = add_txcnt && (txcnt == frame_len - 1'b1) ; + + + +////////////////////////////////////////////////////////////////////////// +//rd_times +////////////////////////////////////////////////////////////////////////// + +always@(*)begin + if(rxs_reg)begin + rd_times = add_txcnt & (txcnt[4:0] == 5'd31)& (txcnt != 10'd543) & cmd_reg; + end + else begin + rd_times = add_txcnt & (txcnt[4:0] == 5'd31)& (txcnt != 10'd63) & cmd_reg; + end +end + +//rd_sram foreread +//assign rd_sram = (rd_times) | (add_txcnt & (txcnt[9:0] == 5'd30) & cmd_reg) ; +assign rd_sram = rd_times & cmd_reg; + + +////////////////////////////////////////////////////////////////////////// +//trans_start +////////////////////////////////////////////////////////////////////////// + +always @(posedge clk or negedge spi_rstn) begin + if(spi_rstn == L) begin + trans_start <= 1'b0; + end + else if(rd_times)begin + trans_start <= 1'b1; + end + else if(~csn_active)begin + trans_start <= 1'b0; + end + else begin + trans_start <= trans_start; + end +end + + +////////////////////////////////////////////////////////////////////////// +//txd_reg +////////////////////////////////////////////////////////////////////////// + + +reg rd_times_r; +always @(posedge clk or negedge spi_rstn) begin + if(spi_rstn == L) begin + rd_times_r <= 1'h0; + end + else begin + rd_times_r <= rd_times; + end +end + + +always @(posedge clk or negedge spi_rstn) begin + if(spi_rstn == L) begin + txd_reg <= 32'h0; + end + else if(rd_times_r) begin + txd_reg <= rddata; + end + else if(add_txcnt && trans_start ) begin + txd_reg <= {txd_reg[30:0],1'b0}; + end + else begin + txd_reg <= txd_reg; + end +end +////////////////////////////////////////////////////////////////////////// +//address_start +////////////////////////////////////////////////////////////////////////// + +always @(posedge clk or negedge spi_rstn) begin + if(spi_rstn == L) begin + address_start <= 1'b0; + end + else if(txcnt == 10'd29)begin + address_start <= 1'b1; + end + else if(~csn_active)begin + address_start <= 1'b0; + end + else begin + address_start <= address_start; + end +end + +////////////////////////////////////////////////////////////////////////// +//rwaddr_reg +////////////////////////////////////////////////////////////////////////// + +always @(posedge clk or negedge spi_rstn) begin + if(spi_rstn == L) begin + rwaddr_reg <= 25'b0; + end + else if(address_start)begin + if(add_addr_wr)begin + rwaddr_reg <= rwaddr_reg + 3'd4; + end + else if(add_addr_rd)begin + rwaddr_reg <= rwaddr_reg + 3'd4; + end + else begin + rwaddr_reg <= rwaddr_reg; + end + end + else begin + rwaddr_reg <= addr_reg; + end +end + + +assign add_addr_wr = rxs_reg & wren_reg_1 ; +assign add_addr_rd = rxs_reg & rd_sram ; + +////////////////////////////////////////////////////////////////////////// +//miso_reg +////////////////////////////////////////////////////////////////////////// +always @(posedge clk or negedge spi_rstn) begin + if(spi_rstn == L) begin + miso_reg <= 1'b0; + end + else begin + miso_reg <= txd_reg[31]; + end +end + +////////////////////////////////////////////////////////////////////////// +//miso_oen_reg +////////////////////////////////////////////////////////////////////////// +always @(posedge clk or negedge spi_rstn) begin + if(spi_rstn == L) begin + miso_oen_reg <= 1'b1; + end + else begin + miso_oen_reg <= ~(trans_start & cmd_reg); + end +end + +////////////////////////////////////////////////////////////////////////// +//error_check +////////////////////////////////////////////////////////////////////////// +always @(posedge clk or negedge spi_rstn) begin + if(spi_rstn == L) begin + error_check_reg <= 1'b0; + end + else if( (rxcnt != 0 || txcnt != 0)&&(~csn_active) )begin + error_check_reg <= 1'b1; + end +end + +////////////////////////////////////////////////////////////////////////// +//Outputs signals +////////////////////////////////////////////////////////////////////////// +//wren +assign wren = wren_reg_1 ; +//wrdata +assign wrdata = wrdata_reg; +//rden +assign rden = rd_sram ; +//addr +assign addr = rwaddr_reg; +//miso +assign miso = miso_reg; +//miso_oen +assign miso_oen = miso_oen_reg; +//error_check +assign error_check = error_check_reg; + +endmodule + + diff --git a/tb/testbench/rtl/spram_model_0.v b/tb/testbench/rtl/spram_model_0.v new file mode 100644 index 0000000..38103c1 --- /dev/null +++ b/tb/testbench/rtl/spram_model_0.v @@ -0,0 +1,68 @@ +module spram_model #( + parameter width = 32 + ,parameter depth = 256 +)( + clka, + ena, + dina, + addra, + + clkb, + enb, + doutb, + addrb +); + +//================================================= +function integer clog2(input integer depth); +begin + for(clog2=0;depth>0;clog2=clog2+1) + depth =depth>>1; +end +endfunction +//================================================= + +localparam aw = clog2(depth-1); +//================================================= +input clka; +input ena; +input [width-1:0] dina; +input [aw-1:0] addra; + +input clkb; +input enb; +output [width-1:0] doutb; +input [aw-1:0] addrb; + + +//================================================ +wire clka; +wire ena; +wire [width-1:0] dina; +wire [aw-1:0] addra; + +wire clkb; +wire enb; +reg [width-1:0] doutb; +wire [aw-1:0] addrb; + + +//================================================ +reg [width-1:0] mem[0:depth-1]; + +always@(posedge clka)begin + if(ena)begin + mem[addra] <=dina; + end +end + +always@(posedge clkb)begin + if(enb)begin + doutb <=mem[addrb]; + end + else begin + doutb <=doutb; + end +end + +endmodule diff --git a/tb/testbench/rtl/sram_if.sv b/tb/testbench/rtl/sram_if.sv new file mode 100644 index 0000000..acf8695 --- /dev/null +++ b/tb/testbench/rtl/sram_if.sv @@ -0,0 +1,55 @@ +interface sram_if #(parameter ADDR_WIDTH = 8, parameter DATA_WIDTH = 32)(input bit clk); + // Signals for interfacing with the SRAM + logic [ADDR_WIDTH-1:0] addr; + logic [DATA_WIDTH-1:0] din; + logic [DATA_WIDTH-1:0] dout; + logic rden; + logic wren; + logic [DATA_WIDTH/8-1:0] wben; + + modport master( + output addr, + output din, + input dout, + output wren, + output rden, + output wben + ); + + modport slave ( + input addr, + input din, + output dout, + input wren, + input rden, + input wben + ); + + // write operation + task write; + input logic [ADDR_WIDTH-1:0] addr_in; + input logic [DATA_WIDTH-1:0] data_in; + input logic [DATA_WIDTH/8-1:0] byte_enable; + begin + addr = addr_in; + din = data_in; + wben = byte_enable; + wren = 1; + rden = 0; + @(posedge clk); + wren = 0; + end + endtask + + // read oepration + task read; + input logic [ADDR_WIDTH-1:0] addr_in; + begin + addr = addr_in; + wren = 0; + rden = 1; + @(posedge clk); + rden = 0; + end + endtask +endinterface \ No newline at end of file diff --git a/tb/testbench/rtl/system_regfile.v b/tb/testbench/rtl/system_regfile.v new file mode 100644 index 0000000..0e0c5da --- /dev/null +++ b/tb/testbench/rtl/system_regfile.v @@ -0,0 +1,689 @@ +//+FHDR-------------------------------------------------------------------------------------------------------- +// Company: +//----------------------------------------------------------------------------------------------------------------- +// File Name : ssytem_regfile.v +// Department : +// Author : PWY +// Author's Tel : +//----------------------------------------------------------------------------------------------------------------- +// Relese History +// Version Date Author Description +// 1.0 2022-08-25 PWY +//----------------------------------------------------------------------------------------------------------------- +// Keywords : +// +//----------------------------------------------------------------------------------------------------------------- +// Parameter +// +//----------------------------------------------------------------------------------------------------------------- +// Purpose : +// +//----------------------------------------------------------------------------------------------------------------- +// Target Device: +// Tool versions: +//----------------------------------------------------------------------------------------------------------------- +// Reuse Issues +// Reset Strategy: +// Clock Domains: +// Critical Timing: +// Asynchronous I/F: +// Synthesizable (y/n): +// Other: +//-FHDR-------------------------------------------------------------------------------------------------------- + +// ----------------------------------------------------------- +// -- Register address offset macros +// ----------------------------------------------------------- +//Identity Register +`define IDR 16'h00 +//Vendor Code Register +`define VIDR 16'h04 +//RTL Freeze Date Register +`define DATER 16'h08 +//Version Register +`define VERR 16'h0C +//Wirte And Read Test Register +`define TESTR 16'h10 +//Interrupt Mask Register +//[31 ] --> PLL LOCK Interrupt Mask +//[30 ] --> PLL Lost LOCK Interrupt Mask +//[29 ] --> CH3 DBG UPD Interrupt Mask +//[28 ] --> CH3 DBG FIFO Empty Interrupt Mask +//[27 ] --> CH3 DBG FIFO Full Interrupt Mask +//[26 ] --> CH3 LDST ADDR UNALGN Interrupt Mask +//[25 ] --> CH3 DEC ERR Interrupt Mask +//[24 ] --> CH3 EXITI Interrupt Mask +//[23:22] --> Reserved +//[21 ] --> CH2 DBG UPD Interrupt Mask +//[20 ] --> CH2 DBG FIFO Empty Interrupt Mask +//[19 ] --> CH2 DBG FIFO Full Interrupt Mask +//[18 ] --> CH2 LDST ADDR UNALGN Interrupt Mask +//[17 ] --> CH2 DEC ERR Interrupt Mask +//[16 ] --> CH2 EXITI Interrupt Mask +//[15:14] --> Reserved +//[13 ] --> CH1 DBG UPD Interrupt Mask +//[12 ] --> CH1 DBG FIFO Empty Interrupt Mask +//[11 ] --> CH1 DBG FIFO Full Interrupt Mask +//[10 ] --> CH1 LDST ADDR UNALGN Interrupt Mask +//[9 ] --> CH1 DEC ERR Interrupt Mask +//[8 ] --> CH1 EXITI Interrupt Mask +//[7 :6] --> Reserved +//[5 ] --> CH1 DBG UPD Interrupt Mask +//[4 ] --> CH1 DBG FIFO Empty Interrupt Mask +//[3 ] --> CH1 DBG FIFO Full Interrupt Mask +//[2 ] --> CH1 LDST ADDR UNALGN Interrupt Mask +//[1 ] --> CH1 DEC ERR Interrupt Mask +//[0 ] --> CH1 EXITI Interrupt Mask +`define IMR 16'h14 +//Interrupt Status Register +//[31 ] --> PLL LOCK Interrupt Status +//[30 ] --> PLL Lost LOCK Interrupt Status +//[29 ] --> CH3 DBG UPD Interrupt Status +//[28 ] --> CH3 DBG FIFO Empty Interrupt Status +//[27 ] --> CH3 DBG FIFO Full Interrupt Status +//[26 ] --> CH3 LDST ADDR UNALGN Interrupt Status +//[25 ] --> CH3 DEC ERR Interrupt Status +//[24 ] --> CH3 EXITI Interrupt Status +//[23:22] --> Reserved +//[21 ] --> CH2 DBG UPD Interrupt Status +//[20 ] --> CH2 DBG FIFO Empty Interrupt Status +//[19 ] --> CH2 DBG FIFO Full Interrupt Status +//[18 ] --> CH2 LDST ADDR UNALGN Interrupt Status +//[17 ] --> CH2 DEC ERR Interrupt Status +//[16 ] --> CH2 EXITI Interrupt Status +//[15:14] --> Reserved +//[13 ] --> CH1 DBG UPD Interrupt Status +//[12 ] --> CH1 DBG FIFO Empty Interrupt Status +//[11 ] --> CH1 DBG FIFO Full Interrupt Status +//[10 ] --> CH1 LDST ADDR UNALGN Interrupt Status +//[9 ] --> CH1 DEC ERR Interrupt Status +//[8 ] --> CH1 EXITI Interrupt Status +//[7 :6] --> Reserved +//[5 ] --> CH1 DBG UPD Interrupt Status +//[4 ] --> CH1 DBG FIFO Empty Interrupt Status +//[3 ] --> CH1 DBG FIFO Full Interrupt Status +//[2 ] --> CH1 LDST ADDR UNALGN Interrupt Status +//[1 ] --> CH1 DEC ERR Interrupt Status +//[0 ] --> CH1 EXITI Interrupt Status +`define ISR 16'h18 +//Post Masking Interrupt Status Register +//Interrupt Status Register +//[31 ] --> PLL LOCK Masking Interrupt Status +//[30 ] --> PLL Lost LOCK Masking Interrupt Status +//[29 ] --> CH3 DBG UPD IMasking Interrupt Status +//[28 ] --> CH3 DBG FIFO Empty Masking Interrupt Status +//[27 ] --> CH3 DBG FIFO Full Masking Interrupt Status +//[26 ] --> CH3 LDST ADDR UNALGN Masking Interrupt Status +//[25 ] --> CH3 DEC ERR Masking Interrupt Status +//[24 ] --> CH3 EXITI Masking Interrupt Status +//[23:22] --> Reserved +//[21 ] --> CH2 DBG UPD Masking Interrupt Status +//[20 ] --> CH2 DBG FIFO Empty Masking Interrupt Status +//[19 ] --> CH2 DBG FIFO Full Masking Interrupt Status +//[18 ] --> CH2 LDST ADDR UNALGN Masking Interrupt Status +//[17 ] --> CH2 DEC ERR Masking Interrupt Status +//[16 ] --> CH2 EXITI Masking Interrupt Status +//[15:14] --> Reserved +//[13 ] --> CH1 DBG UPD Masking Interrupt Status +//[12 ] --> CH1 DBG FIFO Empty Masking Interrupt Status +//[11 ] --> CH1 DBG FIFO Full Masking Interrupt Status +//[10 ] --> CH1 LDST ADDR UNALGN Masking Interrupt Status +//[9 ] --> CH1 DEC ERR Masking Interrupt Status +//[8 ] --> CH1 EXITI Masking Interrupt Status +//[7 :6] --> Reserved +//[5 ] --> CH1 DBG UPD Masking Interrupt Status +//[4 ] --> CH1 DBG FIFO Empty Masking Interrupt Status +//[3 ] --> CH1 DBG FIFO Full Masking Interrupt Status +//[2 ] --> CH1 LDST ADDR UNALGN Masking Interrupt Status +//[1 ] --> CH1 DEC ERR Masking Interrupt Status +//[0 ] --> CH1 EXITI Masking Interrupt Status +`define MISR 16'h1C +//Soft Reset Time Register +`define SFRTR 16'h20 +//Soft Reset Register +`define SFRR 16'h24 +//MCU Soft Reset Register +`define MCURSTR 16'h28 +//AWG Soft Reset Register +`define AWGRSTR 16'h2C +//DAC Soft Reset Register +`define DACRSTR 16'h30 + + +module system_regfile ( + //system port + input clk // System Main Clock + ,input rst_n // Spi Reset active low + //rw op port + ,input [31 :0] wrdata // write data + ,input wren // write enable + ,input [15 :0] rwaddr // read & write address + ,input rden // read enable + ,output [31 :0] rddata // read data + //pll status port + ,input pll_lock + ,input pll_lost_lock + //ch0 status Port + ,input ch0_dbg_upd + ,input ch0_dbg_fifo_e + ,input ch0_dbg_fifo_f + ,input ch0_ldst_addr_unalgn + ,input ch0_dec_err + ,input ch0_exit_irq + //ch1 status Port + ,input ch1_dbg_upd + ,input ch1_dbg_fifo_e + ,input ch1_dbg_fifo_f + ,input ch1_ldst_addr_unalgn + ,input ch1_dec_err + ,input ch1_exit_irq + //ch2 status Port + ,input ch2_dbg_upd + ,input ch2_dbg_fifo_e + ,input ch2_dbg_fifo_f + ,input ch2_ldst_addr_unalgn + ,input ch2_dec_err + ,input ch2_exit_irq + //ch3 status Port + ,input ch3_dbg_upd + ,input ch3_dbg_fifo_e + ,input ch3_dbg_fifo_f + ,input ch3_ldst_addr_unalgn + ,input ch3_dec_err + ,input ch3_exit_irq + //Soft Reset out + ,output sys_soft_rstn + ,output mcu_soft_rstn + ,output awg_soft_rstn + ,output dac_soft_rstn + //Interrupt output port + ,output irq +); + +localparam L = 1'b0, + H = 1'b1; + +localparam IDRD = 32'h41574743; +localparam VIDRD = 32'h55535443; +localparam DATERD = 32'h20220831; +localparam VERSION = 32'h00000001; +localparam TESTRD = 32'h01234567; +// ------------------------------------------------------ +// -- Register enable (select) wires +// ------------------------------------------------------ +wire idren; // idr select +wire vidren; // vidr select +wire dateren; // dater select +wire verren; // dater select +wire testren; // testr select +wire imren; // imr select +wire isren; // isr select +wire misren; // imsr select +wire sfrtren; // sfrtr select +wire sfrren; // sfrr select +wire mcurstren; // mcurstr select +wire awgrstren; // awgrstr select +wire adacrstren; // adacrstr select + + +// ------------------------------------------------------ +// -- Register write enable wires +// ------------------------------------------------------ +wire testrwe; // testr write enable +wire imrwe; // imr write enable +wire misrwe; // imsr write enable +wire sfrtrwe; // sfrtr write enable +wire sfrrwe; // sfrr write enable +wire mcurstrwe; // mcurstr write enable +wire awgrstrwe; // awgrstr write enable +wire adacrstrwe; // adacrstr write enable + +// ------------------------------------------------------ +// -- Misc wires +// ------------------------------------------------------ +wire [31 :0] irisr ; // original interrupt status wire +wire icr ; // interrupt status clear wire + +// ------------------------------------------------------ +// -- Misc Registers +// ------------------------------------------------------ +reg [31 :0] testr ; +reg [31 :0] imr ; +reg [31 :0] isr ; +reg [31 :0] misr ; +reg [31 :0] sfrtr ; +reg [0 :0] sfrr ; +reg [0 :0] mcurstr ; +reg [0 :0] awgrstr ; +reg [0 :0] adacrstr ; + +reg [31 :0] rddata_reg ; + +reg pll_lock_r ; +reg pll_lost_lock_r ; +//ch0 status reg +reg ch0_dbg_upd_r ; +reg ch0_dbg_fifo_e_r ; +reg ch0_dbg_fifo_f_r ; +reg ch0_ldst_addr_unalgn_r ; +reg ch0_dec_err_r ; +reg ch0_exit_irq_r ; +//ch1 status reg +reg ch1_dbg_upd_r ; +reg ch1_dbg_fifo_e_r ; +reg ch1_dbg_fifo_f_r ; +reg ch1_ldst_addr_unalgn_r ; +reg ch1_dec_err_r ; +reg ch1_exit_irq_r ; +//ch2 status reg +reg ch2_dbg_upd_r ; +reg ch2_dbg_fifo_e_r ; +reg ch2_dbg_fifo_f_r ; +reg ch2_ldst_addr_unalgn_r ; +reg ch2_dec_err_r ; +reg ch2_exit_irq_r ; +//ch3 status reg +reg ch3_dbg_upd_r ; +reg ch3_dbg_fifo_e_r ; +reg ch3_dbg_fifo_f_r ; +reg ch3_ldst_addr_unalgn_r ; +reg ch3_dec_err_r ; +reg ch3_exit_irq_r ; + +reg sys_soft_rstn_r ; +reg mcu_soft_rstn_r ; +reg awg_soft_rstn_r ; +reg dac_soft_rstn_r ; + +// ------------------------------------------------------ +// -- Address decoder +// +// Decodes the register address offset input(reg_addr) +// to produce enable (select) signals for each of the +// SW-registers in the macrocell. The reg_addr input +// is bits [8:0] of the paddr bus. +// ------------------------------------------------------ +assign idren = (rwaddr[15:2] == `IDR >> 2) ? 1'b1 : 1'b0; +assign vidren = (rwaddr[15:2] == `VIDR >> 2) ? 1'b1 : 1'b0; +assign dateren = (rwaddr[15:2] == `DATER >> 2) ? 1'b1 : 1'b0; +assign verren = (rwaddr[15:2] == `VERR >> 2) ? 1'b1 : 1'b0; +assign testren = (rwaddr[15:2] == `TESTR >> 2) ? 1'b1 : 1'b0; +assign imren = (rwaddr[15:2] == `IMR >> 2) ? 1'b1 : 1'b0; +assign isren = (rwaddr[15:2] == `ISR >> 2) ? 1'b1 : 1'b0; +assign misren = (rwaddr[15:2] == `MISR >> 2) ? 1'b1 : 1'b0; +assign sfrtren = (rwaddr[15:2] == `SFRTR >> 2) ? 1'b1 : 1'b0; +assign sfrren = (rwaddr[15:2] == `SFRR >> 2) ? 1'b1 : 1'b0; +assign mcurstren = (rwaddr[15:2] == `MCURSTR >> 2) ? 1'b1 : 1'b0; +assign awgrstren = (rwaddr[15:2] == `AWGRSTR >> 2) ? 1'b1 : 1'b0; +assign adacrstren = (rwaddr[15:2] == `DACRSTR >> 2) ? 1'b1 : 1'b0; + +// ------------------------------------------------------ +// -- Write enable signals +// +// Write enable signals for writable SW-registers. +// The write enable for each register is the ANDed +// result of the register enable and the input reg_wren +// ------------------------------------------------------ +assign testrwe = testren & wren; +assign imrwe = imren & wren; +assign sfrtrwe = sfrtren & wren; +assign sfrrwe = sfrren & wren; +assign mcurstrwe = mcurstren & wren; +assign awgrstrwe = awgrstren & wren; +assign adacrstrwe = adacrstren & wren; + + +// --------------------------------------------------------------------------------------------------- +// -- interrupt Mask Register +// +// Write interrupt Mask for 'imr' : 12-bit register +// Register is split into the following bit fields +// +//[31 ] --> PLL LOCK Interrupt Mask +//[30 ] --> PLL Lost LOCK Interrupt Mask +//[29 ] --> CH3 DBG UPD Interrupt Mask +//[28 ] --> CH3 DBG FIFO Empty Interrupt Mask +//[27 ] --> CH3 DBG FIFO Full Interrupt Mask +//[26 ] --> CH3 LDST ADDR UNALGN Interrupt Mask +//[25 ] --> CH3 DEC ERR Interrupt Mask +//[24 ] --> CH3 EXITI Interrupt Mask +//[23:22] --> Reserved +//[21 ] --> CH2 DBG UPD Interrupt Mask +//[20 ] --> CH2 DBG FIFO Empty Interrupt Mask +//[19 ] --> CH2 DBG FIFO Full Interrupt Mask +//[18 ] --> CH2 LDST ADDR UNALGN Interrupt Mask +//[17 ] --> CH2 DEC ERR Interrupt Mask +//[16 ] --> CH2 EXITI Interrupt Mask +//[15:14] --> Reserved +//[13 ] --> CH1 DBG UPD Interrupt Mask +//[12 ] --> CH1 DBG FIFO Empty Interrupt Mask +//[11 ] --> CH1 DBG FIFO Full Interrupt Mask +//[10 ] --> CH1 LDST ADDR UNALGN Interrupt Mask +//[9 ] --> CH1 DEC ERR Interrupt Mask +//[8 ] --> CH1 EXITI Interrupt Mask +//[7 :6] --> Reserved +//[5 ] --> CH1 DBG UPD Interrupt Mask +//[4 ] --> CH1 DBG FIFO Empty Interrupt Mask +//[3 ] --> CH1 DBG FIFO Full Interrupt Mask +//[2 ] --> CH1 LDST ADDR UNALGN Interrupt Mask +//[1 ] --> CH1 DEC ERR Interrupt Mask +//[0 ] --> CH1 EXITI Interrupt Mask +// --------------------------------------------------------------------------------------------------- +sirv_gnrl_dfflr #(32) imr_dfflr (imrwe, wrdata[31:0], imr, clk, rst_n); + +// ------------------------------------------------------ +// -- testr Register +// +// Write testr for 'TESTR' : 32-bit register +// Register is split into the following bit fields +// +// [31:0] --> testr +// ------------------------------------------------------ +sirv_gnrl_dfflrd #(32) testr_dfflrd (TESTRD, testrwe, wrdata[31:0], testr, clk, rst_n); + + +// ------------------------------------------------------ +// -- Soft Reset Count Register +// +// Write Soft Reset Count for 'sfrtcr' : 6-bit register +// Register is split into the following bit fields +// +// [31:0] --> sfrtcr,default value 32'd300 +// ------------------------------------------------------ +sirv_gnrl_dfflrd #(32) sfrtr_dfflrd (32'd300, sfrtrwe, wrdata[31:0], sfrtr, clk, rst_n);/////////////////////////////sfrtcr-->sfrtr + +// ------------------------------------------------------ +// -- soft reset count +// ------------------------------------------------------ + +reg [31:0] cnt_c; + +wire add_cnt = (sys_soft_rstn_r == L) + | (mcu_soft_rstn_r == L) + | (awg_soft_rstn_r == L) + | (dac_soft_rstn_r == L); + +wire end_cnt = add_cnt & (cnt_c == sfrtr-1); + +wire [31:0] cnt_n = end_cnt ? 32'h0 : + add_cnt ? cnt_c + 1'b1 : + cnt_c ; + + +sirv_gnrl_dffr #(32) cnt_c_dffr (cnt_n, cnt_c, clk, rst_n); + +// ------------------------------------------------------ +// -- Soft Reset Register +// +// Write Soft Reset for 'sfrtr' : 1-bit register +// Register is split into the following bit fields +// +// [16'h0024] --> System Soft Reset ,low active +// [16'h0028] --> MCU Soft Reset ,low active +// [16'h002C] --> AWG Soft Reset ,low active +// [16'h0030] --> DAC Soft Reset ,low active +// ------------------------------------------------------ + +//sys_soft_rstn_r +wire sys_soft_rstn_en = end_cnt | sfrrwe; +wire sys_soft_rstn_w = end_cnt ? 1'b1 : + sfrrwe ? 1'b0 : + 1'b1 ; +sirv_gnrl_dfflrs #(1) sys_soft_rstn_r_dffls (sys_soft_rstn_en, sys_soft_rstn_w, sys_soft_rstn_r, clk, rst_n); + +//mcu_soft_rstn_r +wire mcu_soft_rstn_en = end_cnt | mcurstrwe; +wire mcu_soft_rstn_w = end_cnt ? 1'b1 : + mcurstrwe ? 1'b0 : + 1'b1 ; +sirv_gnrl_dfflrs #(1) mcu_soft_rstn_r_dffls (mcu_soft_rstn_en, mcu_soft_rstn_w, mcu_soft_rstn_r, clk, rst_n); + +//awg_soft_rstn_r +wire awg_soft_rstn_en = end_cnt | awgrstrwe; +wire awg_soft_rstn_w = end_cnt ? 1'b1 : + awgrstrwe ? 1'b0 : + 1'b1 ; +sirv_gnrl_dfflrs #(1) awg_soft_rstn_r_dffls (awg_soft_rstn_en, awg_soft_rstn_w, awg_soft_rstn_r, clk, rst_n); + +//dac_soft_rstn_r +wire dac_soft_rstn_en = end_cnt | adacrstrwe; +wire dac_soft_rstn_w = end_cnt ? 1'b1 : + adacrstrwe ? 1'b0 : + 1'b1 ; +sirv_gnrl_dfflrs #(1) dac_soft_rstn_r_dffls (dac_soft_rstn_en, dac_soft_rstn_w, dac_soft_rstn_r, clk, rst_n); + + +assign sys_soft_rstn = sys_soft_rstn_r;////////////////////////// +assign mcu_soft_rstn = mcu_soft_rstn_r;////////////////////////// +assign awg_soft_rstn = awg_soft_rstn_r;////////////////////////// +assign dac_soft_rstn = dac_soft_rstn_r;////////////////////////// + +// ------------------------------------------------------ +// -- Read data mux +// +// -- The data from the selected register is +// -- placed on a zero-padded 32-bit read data bus. +// ------------------------------------------------------ +always @(*) begin : RDDATA_PROC + rddata_reg = {32{1'b0}}; + if(idren == H ) rddata_reg[31:0] = IDRD; + if(vidren == H ) rddata_reg[31:0] = VIDRD; + if(dateren == H ) rddata_reg[31:0] = DATERD; + if(verren == H ) rddata_reg[31:0] = VERSION; + if(testren == H ) rddata_reg[31:0] = testr; + if(imren == H ) rddata_reg[31:0] = imr; + if(isren == H ) rddata_reg[31:0] = isr; + if(misren == H ) rddata_reg[31:0] = misr; + if(sfrtren == H ) rddata_reg[31:0] = sfrtr; +end + +//rddata +sirv_gnrl_dffr #(32) rddata_dffr (rddata_reg, rddata, clk, rst_n); + +// ------------------------------------------------------ +// -- interrupt status +// ------------------------------------------------------ + +//read misr clear interrupts +assign icr = (misren) && rden; + +//pll_lock_r +wire pll_lock_en = icr | pll_lock; +wire pll_lock_w = ~icr | pll_lock; +sirv_gnrl_dfflr #(1) pll_lock_r_dfflr (pll_lock_en, pll_lock_w, pll_lock_r, clk, rst_n); + + +//pll_lost_lock_r +wire pll_lost_lock_en = icr | pll_lost_lock; +wire pll_lost_lock_w = ~icr | pll_lost_lock; +sirv_gnrl_dfflr #(1) pll_lost_lock_r_dfflr (pll_lost_lock_en, pll_lost_lock_w, pll_lost_lock_r, clk, rst_n); + + +//ch0_dbg_upd_r +wire ch0_dbg_upd_en = icr | ch0_dbg_upd; +wire ch0_dbg_upd_w = ~icr | ch0_dbg_upd; +sirv_gnrl_dfflr #(1) ch0_dbg_upd_r_dfflr (ch0_dbg_upd_en, ch0_dbg_upd_w, ch0_dbg_upd_r, clk, rst_n); + +//ch0_dbg_fifo_e_r +wire ch0_dbg_fifo_e_en = icr | ch0_dbg_fifo_e; +wire ch0_dbg_fifo_e_w = ~icr | ch0_dbg_fifo_e; +sirv_gnrl_dfflr #(1) ch0_dbg_fifo_e_r_dfflr (ch0_dbg_fifo_e_en, ch0_dbg_fifo_e_w, ch0_dbg_fifo_e_r, clk, rst_n); + +//ch0_dbg_fifo_f_r +wire ch0_dbg_fifo_f_en = icr | ch0_dbg_fifo_f; +wire ch0_dbg_fifo_f_w = ~icr | ch0_dbg_fifo_f; +sirv_gnrl_dfflr #(1) ch0_dbg_fifo_f_r_dfflr (ch0_dbg_fifo_f_en, ch0_dbg_fifo_f_w, ch0_dbg_fifo_f_r, clk, rst_n); + +//ch0_ldst_addr_unalgn_r +wire ch0_ldst_addr_unalgn_en = icr | ch0_ldst_addr_unalgn; +wire ch0_ldst_addr_unalgn_w = ~icr | ch0_ldst_addr_unalgn; +sirv_gnrl_dfflr #(1) ch0_ldst_addr_unalgn_r_dfflr (ch0_ldst_addr_unalgn_en, ch0_ldst_addr_unalgn_w, ch0_ldst_addr_unalgn_r, clk, rst_n); + +//ch0_dec_err_r +wire ch0_dec_err_en = icr | ch0_dec_err; +wire ch0_dec_err_w = ~icr | ch0_dec_err; +sirv_gnrl_dfflr #(1) ch0_dec_err_r_dfflr (ch0_dec_err_en, ch0_dec_err_w, ch0_dec_err_r, clk, rst_n); + +//ch0_exit_irq_r +wire ch0_exit_irq_en = icr | ch0_exit_irq; +wire ch0_exit_irq_w = ~icr | ch0_exit_irq; +sirv_gnrl_dfflr #(1) ch0_exit_irq_r_dfflr (ch0_exit_irq_en, ch0_exit_irq_w, ch0_exit_irq_r, clk, rst_n); + + +//ch1_dbg_upd_r +wire ch1_dbg_upd_en = icr | ch1_dbg_upd; +wire ch1_dbg_upd_w = ~icr | ch1_dbg_upd; +sirv_gnrl_dfflr #(1) ch1_dbg_upd_r_dfflr (ch1_dbg_upd_en, ch1_dbg_upd_w, ch1_dbg_upd_r, clk, rst_n); + +//ch1_dbg_fifo_e_r +wire ch1_dbg_fifo_e_en = icr | ch1_dbg_fifo_e; +wire ch1_dbg_fifo_e_w = ~icr | ch1_dbg_fifo_e; +sirv_gnrl_dfflr #(1) ch1_dbg_fifo_e_r_dfflr (ch1_dbg_fifo_e_en, ch1_dbg_fifo_e_w, ch1_dbg_fifo_e_r, clk, rst_n); + +//ch1_dbg_fifo_f_r +wire ch1_dbg_fifo_f_en = icr | ch1_dbg_fifo_f; +wire ch1_dbg_fifo_f_w = ~icr | ch1_dbg_fifo_f; +sirv_gnrl_dfflr #(1) ch1_dbg_fifo_f_r_dfflr (ch1_dbg_fifo_f_en, ch1_dbg_fifo_f_w, ch1_dbg_fifo_f_r, clk, rst_n); + +//ch1_ldst_addr_unalgn_r +wire ch1_ldst_addr_unalgn_en = icr | ch1_ldst_addr_unalgn; +wire ch1_ldst_addr_unalgn_w = ~icr | ch1_ldst_addr_unalgn; +sirv_gnrl_dfflr #(1) ch1_ldst_addr_unalgn_r_dfflr (ch1_ldst_addr_unalgn_en, ch1_ldst_addr_unalgn_w, ch1_ldst_addr_unalgn_r, clk, rst_n); + +//ch1_dec_err_r +wire ch1_dec_err_en = icr | ch1_dec_err; +wire ch1_dec_err_w = ~icr | ch1_dec_err; +sirv_gnrl_dfflr #(1) ch1_dec_err_r_dfflr (ch1_dec_err_en, ch1_dec_err_w, ch1_dec_err_r, clk, rst_n); + +//ch1_exit_irq_r +wire ch1_exit_irq_en = icr | ch1_exit_irq; +wire ch1_exit_irq_w = ~icr | ch1_exit_irq; +sirv_gnrl_dfflr #(1) ch1_exit_irq_r_dfflr (ch1_exit_irq_en, ch1_exit_irq_w, ch1_exit_irq_r, clk, rst_n); + +//ch2_dbg_upd_r +wire ch2_dbg_upd_en = icr | ch2_dbg_upd; +wire ch2_dbg_upd_w = ~icr | ch2_dbg_upd; +sirv_gnrl_dfflr #(1) ch2_dbg_upd_r_dfflr (ch2_dbg_upd_en, ch2_dbg_upd_w, ch2_dbg_upd_r, clk, rst_n); + +//ch2_dbg_fifo_e_r +wire ch2_dbg_fifo_e_en = icr | ch2_dbg_fifo_e; +wire ch2_dbg_fifo_e_w = ~icr | ch2_dbg_fifo_e; +sirv_gnrl_dfflr #(1) ch2_dbg_fifo_e_r_dfflr (ch2_dbg_fifo_e_en, ch2_dbg_fifo_e_w, ch2_dbg_fifo_e_r, clk, rst_n); + +//ch2_dbg_fifo_f_r +wire ch2_dbg_fifo_f_en = icr | ch2_dbg_fifo_f; +wire ch2_dbg_fifo_f_w = ~icr | ch2_dbg_fifo_f; +sirv_gnrl_dfflr #(1) ch2_dbg_fifo_f_r_dfflr (ch2_dbg_fifo_f_en, ch2_dbg_fifo_f_w, ch2_dbg_fifo_f_r, clk, rst_n); + +//ch2_ldst_addr_unalgn_r +wire ch2_ldst_addr_unalgn_en = icr | ch2_ldst_addr_unalgn; +wire ch2_ldst_addr_unalgn_w = ~icr | ch2_ldst_addr_unalgn; +sirv_gnrl_dfflr #(1) ch2_ldst_addr_unalgn_r_dfflr (ch2_ldst_addr_unalgn_en, ch2_ldst_addr_unalgn_w, ch2_ldst_addr_unalgn_r, clk, rst_n); + +//ch2_dec_err_r +wire ch2_dec_err_en = icr | ch2_dec_err; +wire ch2_dec_err_w = ~icr | ch2_dec_err; +sirv_gnrl_dfflr #(1) ch2_dec_err_r_dfflr (ch2_dec_err_en, ch2_dec_err_w, ch2_dec_err_r, clk, rst_n); + +//ch2_exit_irq_r +wire ch2_exit_irq_en = icr | ch2_exit_irq; +wire ch2_exit_irq_w = ~icr | ch2_exit_irq; +sirv_gnrl_dfflr #(1) ch2_exit_irq_r_dfflr (ch2_exit_irq_en, ch2_exit_irq_w, ch2_exit_irq_r, clk, rst_n); + +//ch3_dbg_upd_r +wire ch3_dbg_upd_en = icr | ch3_dbg_upd; +wire ch3_dbg_upd_w = ~icr | ch3_dbg_upd; +sirv_gnrl_dfflr #(1) ch3_dbg_upd_r_dfflr (ch3_dbg_upd_en, ch3_dbg_upd_w, ch3_dbg_upd_r, clk, rst_n); + +//ch3_dbg_fifo_e_r +wire ch3_dbg_fifo_e_en = icr | ch3_dbg_fifo_e; +wire ch3_dbg_fifo_e_w = ~icr | ch3_dbg_fifo_e; +sirv_gnrl_dfflr #(1) ch3_dbg_fifo_e_r_dfflr (ch3_dbg_fifo_e_en, ch3_dbg_fifo_e_w, ch3_dbg_fifo_e_r, clk, rst_n); + +//ch3_dbg_fifo_f_r +wire ch3_dbg_fifo_f_en = icr | ch3_dbg_fifo_f; +wire ch3_dbg_fifo_f_w = ~icr | ch3_dbg_fifo_f; +sirv_gnrl_dfflr #(1) ch3_dbg_fifo_f_r_dfflr (ch3_dbg_fifo_f_en, ch3_dbg_fifo_f_w, ch3_dbg_fifo_f_r, clk, rst_n); + +//ch3_ldst_addr_unalgn_r +wire ch3_ldst_addr_unalgn_en = icr | ch3_ldst_addr_unalgn; +wire ch3_ldst_addr_unalgn_w = ~icr | ch3_ldst_addr_unalgn; +sirv_gnrl_dfflr #(1) ch3_ldst_addr_unalgn_r_dfflr (ch3_ldst_addr_unalgn_en, ch3_ldst_addr_unalgn_w, ch3_ldst_addr_unalgn_r, clk, rst_n); + +//ch3_dec_err_r +wire ch3_dec_err_en = icr | ch3_dec_err; +wire ch3_dec_err_w = ~icr | ch3_dec_err; +sirv_gnrl_dfflr #(1) ch3_dec_err_r_dfflr (ch3_dec_err_en, ch3_dec_err_w, ch3_dec_err_r, clk, rst_n); + +//ch3_exit_irq_r +wire ch3_exit_irq_en = icr | ch3_exit_irq; +wire ch3_exit_irq_w = ~icr | ch3_exit_irq; +sirv_gnrl_dfflr #(1) ch3_exit_irq_r_dfflr (ch3_exit_irq_en, ch3_exit_irq_w, ch3_exit_irq_r, clk, rst_n); + +//irisr +assign irisr[31] = pll_lock_r ; +assign irisr[30] = pll_lost_lock_r ; +assign irisr[29] = ch3_dbg_upd_r ; +assign irisr[28] = ch3_dbg_fifo_e_r ; +assign irisr[27] = ch3_dbg_fifo_f_r ; +assign irisr[26] = ch3_ldst_addr_unalgn_r ; +assign irisr[25] = ch3_dec_err_r ; +assign irisr[24] = ch3_exit_irq_r ; +assign irisr[23] = L ; +assign irisr[22] = L ; +assign irisr[21] = ch2_dbg_upd_r ; +assign irisr[20] = ch2_dbg_fifo_e_r ; +assign irisr[19] = ch2_dbg_fifo_f_r ; +assign irisr[18] = ch2_ldst_addr_unalgn_r ; +assign irisr[17] = ch2_dec_err_r ; +assign irisr[16] = ch2_exit_irq_r ; +assign irisr[15] = L ; +assign irisr[14] = L ; +assign irisr[13] = ch1_dbg_upd_r ; +assign irisr[12] = ch1_dbg_fifo_e_r ; +assign irisr[11] = ch1_dbg_fifo_f_r ; +assign irisr[10] = ch1_ldst_addr_unalgn_r ; +assign irisr[9 ] = ch1_dec_err_r ; +assign irisr[8 ] = ch1_exit_irq_r ; +assign irisr[7 ] = L ; +assign irisr[6 ] = L ; +assign irisr[5 ] = ch0_dbg_upd_r ; +assign irisr[4 ] = ch0_dbg_fifo_e_r ; +assign irisr[3 ] = ch0_dbg_fifo_f_r ; +assign irisr[2 ] = ch0_ldst_addr_unalgn_r ; +assign irisr[1 ] = ch0_dec_err_r ; +assign irisr[0 ] = ch0_exit_irq_r ; + +// ------------------------------------------------------ +// -- Interrupt Status Register - Read Only +// +// This register contains the status of all +// XYZ Chip interrupts after masking. +// ------------------------------------------------------ +sirv_gnrl_dffr #(32) isr_dffr (irisr, isr, clk, rst_n); + +//misr +wire[31:0] misr_w = imr & irisr; +sirv_gnrl_dffr #(32) misr_dffr (misr_w, misr, clk, rst_n); + +//irq +wire irq_w = |misr; +sirv_gnrl_dffr #(1) irq_dffr (irq_w, irq, clk, rst_n); + + +endmodule + + +`undef IDR +`undef VIDR +`undef DATER +`undef VERR +`undef TESTR +`undef IMR +`undef ISR +`undef MISR +`undef SFRTR +`undef SFRR +`undef MCURSTR +`undef AWGRSTR +`undef DACRSTR diff --git a/tb/testbench/rtl/system_regfile.v.bak b/tb/testbench/rtl/system_regfile.v.bak new file mode 100644 index 0000000..fc579fb --- /dev/null +++ b/tb/testbench/rtl/system_regfile.v.bak @@ -0,0 +1,662 @@ +//+FHDR-------------------------------------------------------------------------------------------------------- +// Company: +//----------------------------------------------------------------------------------------------------------------- +// File Name : ssytem_regfile.v +// Department : +// Author : PWY +// Author's Tel : +//----------------------------------------------------------------------------------------------------------------- +// Relese History +// Version Date Author Description +// 1.0 2022-08-25 PWY +//----------------------------------------------------------------------------------------------------------------- +// Keywords : +// +//----------------------------------------------------------------------------------------------------------------- +// Parameter +// +//----------------------------------------------------------------------------------------------------------------- +// Purpose : +// +//----------------------------------------------------------------------------------------------------------------- +// Target Device: +// Tool versions: +//----------------------------------------------------------------------------------------------------------------- +// Reuse Issues +// Reset Strategy: +// Clock Domains: +// Critical Timing: +// Asynchronous I/F: +// Synthesizable (y/n): +// Other: +//-FHDR-------------------------------------------------------------------------------------------------------- + +// ----------------------------------------------------------- +// -- Register address offset macros +// ----------------------------------------------------------- +//Identity Register +`define IDR 16'h00 +//Vendor Code Register +`define VIDR 16'h04 +//RTL Freeze Date Register +`define DATER 16'h08 +//Version Register +`define VERR 16'h0C +//Wirte And Read Test Register +`define TESTR 16'h10 +//Interrupt Mask Register +//[31 ] --> PLL LOCK Interrupt Mask +//[30 ] --> PLL Lost LOCK Interrupt Mask +//[29 ] --> CH3 DBG UPD Interrupt Mask +//[28 ] --> CH3 DBG FIFO Empty Interrupt Mask +//[27 ] --> CH3 DBG FIFO Full Interrupt Mask +//[26 ] --> CH3 LDST ADDR UNALGN Interrupt Mask +//[25 ] --> CH3 DEC ERR Interrupt Mask +//[24 ] --> CH3 EXITI Interrupt Mask +//[23:22] --> Reserved +//[21 ] --> CH2 DBG UPD Interrupt Mask +//[20 ] --> CH2 DBG FIFO Empty Interrupt Mask +//[19 ] --> CH2 DBG FIFO Full Interrupt Mask +//[18 ] --> CH2 LDST ADDR UNALGN Interrupt Mask +//[17 ] --> CH2 DEC ERR Interrupt Mask +//[16 ] --> CH2 EXITI Interrupt Mask +//[15:14] --> Reserved +//[13 ] --> CH1 DBG UPD Interrupt Mask +//[12 ] --> CH1 DBG FIFO Empty Interrupt Mask +//[11 ] --> CH1 DBG FIFO Full Interrupt Mask +//[10 ] --> CH1 LDST ADDR UNALGN Interrupt Mask +//[9 ] --> CH1 DEC ERR Interrupt Mask +//[8 ] --> CH1 EXITI Interrupt Mask +//[7 :6] --> Reserved +//[5 ] --> CH1 DBG UPD Interrupt Mask +//[4 ] --> CH1 DBG FIFO Empty Interrupt Mask +//[3 ] --> CH1 DBG FIFO Full Interrupt Mask +//[2 ] --> CH1 LDST ADDR UNALGN Interrupt Mask +//[1 ] --> CH1 DEC ERR Interrupt Mask +//[0 ] --> CH1 EXITI Interrupt Mask +`define IMR 16'h14 +//Interrupt Status Register +//[31 ] --> PLL LOCK Interrupt Status +//[30 ] --> PLL Lost LOCK Interrupt Status +//[29 ] --> CH3 DBG UPD Interrupt Status +//[28 ] --> CH3 DBG FIFO Empty Interrupt Status +//[27 ] --> CH3 DBG FIFO Full Interrupt Status +//[26 ] --> CH3 LDST ADDR UNALGN Interrupt Status +//[25 ] --> CH3 DEC ERR Interrupt Status +//[24 ] --> CH3 EXITI Interrupt Status +//[23:22] --> Reserved +//[21 ] --> CH2 DBG UPD Interrupt Status +//[20 ] --> CH2 DBG FIFO Empty Interrupt Status +//[19 ] --> CH2 DBG FIFO Full Interrupt Status +//[18 ] --> CH2 LDST ADDR UNALGN Interrupt Status +//[17 ] --> CH2 DEC ERR Interrupt Status +//[16 ] --> CH2 EXITI Interrupt Status +//[15:14] --> Reserved +//[13 ] --> CH1 DBG UPD Interrupt Status +//[12 ] --> CH1 DBG FIFO Empty Interrupt Status +//[11 ] --> CH1 DBG FIFO Full Interrupt Status +//[10 ] --> CH1 LDST ADDR UNALGN Interrupt Status +//[9 ] --> CH1 DEC ERR Interrupt Status +//[8 ] --> CH1 EXITI Interrupt Status +//[7 :6] --> Reserved +//[5 ] --> CH1 DBG UPD Interrupt Status +//[4 ] --> CH1 DBG FIFO Empty Interrupt Status +//[3 ] --> CH1 DBG FIFO Full Interrupt Status +//[2 ] --> CH1 LDST ADDR UNALGN Interrupt Status +//[1 ] --> CH1 DEC ERR Interrupt Status +//[0 ] --> CH1 EXITI Interrupt Status +`define ISR 16'h18 +//Post Masking Interrupt Status Register +//Interrupt Status Register +//[31 ] --> PLL LOCK Masking Interrupt Status +//[30 ] --> PLL Lost LOCK Masking Interrupt Status +//[29 ] --> CH3 DBG UPD IMasking Interrupt Status +//[28 ] --> CH3 DBG FIFO Empty Masking Interrupt Status +//[27 ] --> CH3 DBG FIFO Full Masking Interrupt Status +//[26 ] --> CH3 LDST ADDR UNALGN Masking Interrupt Status +//[25 ] --> CH3 DEC ERR Masking Interrupt Status +//[24 ] --> CH3 EXITI Masking Interrupt Status +//[23:22] --> Reserved +//[21 ] --> CH2 DBG UPD Masking Interrupt Status +//[20 ] --> CH2 DBG FIFO Empty Masking Interrupt Status +//[19 ] --> CH2 DBG FIFO Full Masking Interrupt Status +//[18 ] --> CH2 LDST ADDR UNALGN Masking Interrupt Status +//[17 ] --> CH2 DEC ERR Masking Interrupt Status +//[16 ] --> CH2 EXITI Masking Interrupt Status +//[15:14] --> Reserved +//[13 ] --> CH1 DBG UPD Masking Interrupt Status +//[12 ] --> CH1 DBG FIFO Empty Masking Interrupt Status +//[11 ] --> CH1 DBG FIFO Full Masking Interrupt Status +//[10 ] --> CH1 LDST ADDR UNALGN Masking Interrupt Status +//[9 ] --> CH1 DEC ERR Masking Interrupt Status +//[8 ] --> CH1 EXITI Masking Interrupt Status +//[7 :6] --> Reserved +//[5 ] --> CH1 DBG UPD Masking Interrupt Status +//[4 ] --> CH1 DBG FIFO Empty Masking Interrupt Status +//[3 ] --> CH1 DBG FIFO Full Masking Interrupt Status +//[2 ] --> CH1 LDST ADDR UNALGN Masking Interrupt Status +//[1 ] --> CH1 DEC ERR Masking Interrupt Status +//[0 ] --> CH1 EXITI Masking Interrupt Status +`define MISR 16'h1C +//Soft Reset Time Register +`define SFRTR 16'h20 +//Soft Reset Register +`define SFRR 16'h24 +//MCU Soft Reset Register +`define MCURSTR 16'h28 +//AWG Soft Reset Register +`define AWGRSTR 16'h2C +//DAC Soft Reset Register +`define DACRSTR 16'h30/////////////////////// + + +module system_regfile ( + //system port + input clk // System Main Clock + ,input rst_n // Spi Reset active low + //rw op port + ,input [31 :0] wrdata // write data + ,input wren // write enable + ,input [15 :0] rwaddr // read & write address + ,input rden // read enable + ,output [31 :0] rddata // read data + //pll status port + ,input pll_lock + ,input pll_lost_lock + //ch0 status Port + ,input ch0_dbg_upd + ,input ch0_dbg_fifo_e + ,input ch0_dbg_fifo_f + ,input ch0_ldst_addr_unalgn + ,input ch0_dec_err + ,input ch0_exit_irq + //ch1 status Port + ,input ch1_dbg_upd + ,input ch1_dbg_fifo_e + ,input ch1_dbg_fifo_f + ,input ch1_ldst_addr_unalgn + ,input ch1_dec_err + ,input ch1_exit_irq + //ch2 status Port + ,input ch2_dbg_upd + ,input ch2_dbg_fifo_e + ,input ch2_dbg_fifo_f + ,input ch2_ldst_addr_unalgn + ,input ch2_dec_err + ,input ch2_exit_irq + //ch3 status Port + ,input ch3_dbg_upd + ,input ch3_dbg_fifo_e + ,input ch3_dbg_fifo_f + ,input ch3_ldst_addr_unalgn + ,input ch3_dec_err + ,input ch3_exit_irq + //Soft Reset out + ,output sys_soft_rstn + ,output mcu_soft_rstn + ,output awg_soft_rstn + ,output dac_soft_rstn + //Interrupt output port + ,output irq +); + +localparam L = 1'b0, + H = 1'b1; + +localparam IDRD = 32'h41574743; +localparam VIDRD = 32'h55535443; +localparam DATERD = 32'h20220831; +localparam VERSION = 32'h00000001; +localparam TESTRD = 32'h01234567; +// ------------------------------------------------------ +// -- Register enable (select) wires +// ------------------------------------------------------ +wire idren; // idr select +wire vidren; // vidr select +wire dateren; // dater select +wire verren; // dater select +wire testren; // testr select +wire imren; // imr select +wire isren; // isr select +wire misren; // imsr select +wire sfrtren; // sfrtr select +wire sfrren; // sfrr select +wire mcurstren; // mcurstr select +wire awgrstren; // awgrstr select +wire adacrstren; // adacrstr select + + +// ------------------------------------------------------ +// -- Register write enable wires +// ------------------------------------------------------ +wire testrwe; // testr write enable +wire imrwe; // imr write enable +wire misrwe; // imsr write enable +wire sfrtrwe; // sfrtr write enable +wire sfrrwe; // sfrr write enable +wire mcurstrwe; // mcurstr write enable +wire awgrstrwe; // awgrstr write enable +wire adacrstrwe; // adacrstr write enable + +// ------------------------------------------------------ +// -- Misc wires +// ------------------------------------------------------ +wire [31 :0] irisr ; // original interrupt status wire +wire icr ; // interrupt status clear wire + +// ------------------------------------------------------ +// -- Misc Registers +// ------------------------------------------------------ +reg [31 :0] testr ; +reg [31 :0] imr ; +reg [31 :0] isr ; +reg [31 :0] misr ; +reg [31 :0] sfrtr ; +reg [0 :0] sfrr ; +reg [0 :0] mcurstr ; +reg [0 :0] awgrstr ; +reg [0 :0] adacrstr ; + +reg [31 :0] rddata_reg ; + +reg pll_lock_r ; +reg pll_lost_lock_r ; +//ch0 status reg +reg ch0_dbg_upd_r ; +reg ch0_dbg_fifo_e_r ; +reg ch0_dbg_fifo_f_r ; +reg ch0_ldst_addr_unalgn_r ; +reg ch0_dec_err_r ; +reg ch0_exit_irq_r ; +//ch1 status reg +reg ch1_dbg_upd_r ; +reg ch1_dbg_fifo_e_r ; +reg ch1_dbg_fifo_f_r ; +reg ch1_ldst_addr_unalgn_r ; +reg ch1_dec_err_r ; +reg ch1_exit_irq_r ; +//ch2 status reg +reg ch2_dbg_upd_r ; +reg ch2_dbg_fifo_e_r ; +reg ch2_dbg_fifo_f_r ; +reg ch2_ldst_addr_unalgn_r ; +reg ch2_dec_err_r ; +reg ch2_exit_irq_r ; +//ch3 status reg +reg ch3_dbg_upd_r ; +reg ch3_dbg_fifo_e_r ; +reg ch3_dbg_fifo_f_r ; +reg ch3_ldst_addr_unalgn_r ; +reg ch3_dec_err_r ; +reg ch3_exit_irq_r ; + +reg sys_soft_rstn_r ; +reg mcu_soft_rstn_r ; +reg awg_soft_rstn_r ; +reg dac_soft_rstn_r ; + +// ------------------------------------------------------ +// -- Address decoder +// +// Decodes the register address offset input(reg_addr) +// to produce enable (select) signals for each of the +// SW-registers in the macrocell. The reg_addr input +// is bits [8:0] of the paddr bus. +// ------------------------------------------------------ +assign idren = (rwaddr[15:2] == `IDR >> 2) ? 1'b1 : 1'b0; +assign vidren = (rwaddr[15:2] == `VIDR >> 2) ? 1'b1 : 1'b0; +assign dateren = (rwaddr[15:2] == `DATER >> 2) ? 1'b1 : 1'b0; +assign testren = (rwaddr[15:2] == `TESTR >> 2) ? 1'b1 : 1'b0; +assign imren = (rwaddr[15:2] == `IMR >> 2) ? 1'b1 : 1'b0; +assign isren = (rwaddr[15:2] == `ISR >> 2) ? 1'b1 : 1'b0; +assign misren = (rwaddr[15:2] == `MISR >> 2) ? 1'b1 : 1'b0; +assign sfrtren = (rwaddr[15:2] == `SFRTR >> 2) ? 1'b1 : 1'b0; +assign sfrren = (rwaddr[15:2] == `SFRR >> 2) ? 1'b1 : 1'b0; +assign mcurstren = (rwaddr[15:2] == `MCURSTR >> 2) ? 1'b1 : 1'b0; +assign awgrstren = (rwaddr[15:2] == `AWGRSTR >> 2) ? 1'b1 : 1'b0; +assign adacrstren = (rwaddr[15:2] == `DACRSTR >> 2) ? 1'b1 : 1'b0; + +// ------------------------------------------------------ +// -- Write enable signals +// +// Write enable signals for writable SW-registers. +// The write enable for each register is the ANDed +// result of the register enable and the input reg_wren +// ------------------------------------------------------ +assign testrwe = testren & wren; +assign imrwe = imren & wren; +assign sfrtrwe = sfrtren & wren; +assign sfrrwe = sfrren & wren; +assign mcurstrwe = mcurstren & wren; +assign awgrstrwe = awgrstren & wren; +assign adacrstrwe = adacrstren & wren; + + +// --------------------------------------------------------------------------------------------------- +// -- interrupt Mask Register +// +// Write interrupt Mask for 'imr' : 12-bit register +// Register is split into the following bit fields +// +//[31 ] --> PLL LOCK Interrupt Mask +//[30 ] --> PLL Lost LOCK Interrupt Mask +//[29 ] --> CH3 DBG UPD Interrupt Mask +//[28 ] --> CH3 DBG FIFO Empty Interrupt Mask +//[27 ] --> CH3 DBG FIFO Full Interrupt Mask +//[26 ] --> CH3 LDST ADDR UNALGN Interrupt Mask +//[25 ] --> CH3 DEC ERR Interrupt Mask +//[24 ] --> CH3 EXITI Interrupt Mask +//[23:22] --> Reserved +//[21 ] --> CH2 DBG UPD Interrupt Mask +//[20 ] --> CH2 DBG FIFO Empty Interrupt Mask +//[19 ] --> CH2 DBG FIFO Full Interrupt Mask +//[18 ] --> CH2 LDST ADDR UNALGN Interrupt Mask +//[17 ] --> CH2 DEC ERR Interrupt Mask +//[16 ] --> CH2 EXITI Interrupt Mask +//[15:14] --> Reserved +//[13 ] --> CH1 DBG UPD Interrupt Mask +//[12 ] --> CH1 DBG FIFO Empty Interrupt Mask +//[11 ] --> CH1 DBG FIFO Full Interrupt Mask +//[10 ] --> CH1 LDST ADDR UNALGN Interrupt Mask +//[9 ] --> CH1 DEC ERR Interrupt Mask +//[8 ] --> CH1 EXITI Interrupt Mask +//[7 :6] --> Reserved +//[5 ] --> CH1 DBG UPD Interrupt Mask +//[4 ] --> CH1 DBG FIFO Empty Interrupt Mask +//[3 ] --> CH1 DBG FIFO Full Interrupt Mask +//[2 ] --> CH1 LDST ADDR UNALGN Interrupt Mask +//[1 ] --> CH1 DEC ERR Interrupt Mask +//[0 ] --> CH1 EXITI Interrupt Mask +// --------------------------------------------------------------------------------------------------- +sirv_gnrl_dfflr #(32) imr_dfflr (imrwe, wrdata[31:0], imr, clk, rst_n); + +// ------------------------------------------------------ +// -- testr Register +// +// Write testr for 'TESTR' : 32-bit register +// Register is split into the following bit fields +// +// [31:0] --> testr +// ------------------------------------------------------ +sirv_gnrl_dfflrd #(32) testr_dfflrd (TESTRD, testrwe, wrdata[31:0], testr, clk, rst_n); + + +// ------------------------------------------------------ +// -- Soft Reset Count Register +// +// Write Soft Reset Count for 'sfrtcr' : 6-bit register +// Register is split into the following bit fields +// +// [31:0] --> sfrtcr,default value 32'd300 +// ------------------------------------------------------ +sirv_gnrl_dfflrd #(32) sfrtcr_dfflrd (32'd300, sfrtrwe, wrdata[31:0], sfrtr, clk, rst_n);/////////////////////////////sfrtcr-->sfrtr + +// ------------------------------------------------------ +// -- soft reset count +// ------------------------------------------------------ + +reg [31:0] cnt_c; + +wire add_cnt = (sys_soft_rstn_r == L) + | (mcu_soft_rstn_r == L) + | (awg_soft_rstn_r == L) + | (dac_soft_rstn_r == L); + +wire end_cnt = add_cnt & (cnt_c == sfrtr-1); + +wire [31:0] cnt_n = end_cnt ? 32'h0 : + add_cnt ? cnt_c + 1'b1 : + cnt_c ; + + +sirv_gnrl_dffr #(32) cnt_c_dffr (cnt_n, cnt_c, clk, rst_n); + +// ------------------------------------------------------ +// -- Soft Reset Register +// +// Write Soft Reset for 'sfrtr' : 1-bit register +// Register is split into the following bit fields +// +// [16'h0024] --> System Soft Reset ,low active +// [16'h0028] --> MCU Soft Reset ,low active +// [16'h002C] --> AWG Soft Reset ,low active +// [16'h0030] --> DAC Soft Reset ,low active +// ------------------------------------------------------ + +//sys_soft_rstn_r +wire sys_soft_rstn_en = end_cnt | sfrrwe; +wire sys_soft_rstn_w = end_cnt ? 1'b1 : + sfrrwe ? 1'b0 : + 1'b1 ; +sirv_gnrl_dfflrs #(1) sys_soft_rstn_r_dffls (sys_soft_rstn_en, sys_soft_rstn_w, sys_soft_rstn_r, clk, rst_n); + +//mcu_soft_rstn_r +wire mcu_soft_rstn_en = end_cnt | mcurstrwe; +wire mcu_soft_rstn_w = end_cnt ? 1'b1 : + mcurstrwe ? 1'b0 : + 1'b1 ; +sirv_gnrl_dfflrs #(1) mcu_soft_rstn_r_dffls (mcu_soft_rstn_en, mcu_soft_rstn_w, mcu_soft_rstn_r, clk, rst_n); + +//awg_soft_rstn_r +wire awg_soft_rstn_en = end_cnt | awgrstrwe; +wire awg_soft_rstn_w = end_cnt ? 1'b1 : + awgrstrwe ? 1'b0 : + 1'b1 ; +sirv_gnrl_dfflrs #(1) awg_soft_rstn_r_dffls (awg_soft_rstn_en, awg_soft_rstn_w, awg_soft_rstn_r, clk, rst_n); + +//dac_soft_rstn_r +wire dac_soft_rstn_en = end_cnt | adacrstrwe; +wire dac_soft_rstn_w = end_cnt ? 1'b1 : + adacrstrwe ? 1'b0 : + 1'b1 ; +sirv_gnrl_dfflrs #(1) dac_soft_rstn_r_dffls (dac_soft_rstn_en, dac_soft_rstn_w, dac_soft_rstn_r, clk, rst_n); + + +assign sys_soft_rstn = sys_soft_rstn_r;////////////////////////// +assign mcu_soft_rstn = mcu_soft_rstn_r;////////////////////////// +assign awg_soft_rstn = awg_soft_rstn_r;////////////////////////// +assign dac_soft_rstn = dac_soft_rstn_r;////////////////////////// + +// ------------------------------------------------------ +// -- Read data mux +// +// -- The data from the selected register is +// -- placed on a zero-padded 32-bit read data bus. +// ------------------------------------------------------ +always @(*) begin : RDDATA_PROC + rddata_reg = {32{1'b0}}; + if(idren == H ) rddata_reg[31:0] = IDRD; + if(vidren == H ) rddata_reg[31:0] = VIDRD; + if(dateren == H ) rddata_reg[31:0] = DATERD; + if(verren == H ) rddata_reg[31:0] = VERSION; + if(testren == H ) rddata_reg[31:0] = testr; + if(imren == H ) rddata_reg[31:0] = imr; + if(isren == H ) rddata_reg[31:0] = isr; + if(misren == H ) rddata_reg[31:0] = misr; + if(sfrtren == H ) rddata_reg[31:0] = sfrtr; +end + +//rddata +sirv_gnrl_dffr #(32) rddata_dffr (rddata_reg, rddata, clk, rst_n); + +// ------------------------------------------------------ +// -- interrupt status +// ------------------------------------------------------ + +//read misr clear interrupts +assign icr = (misren) && rden; + +//pll_lock_r +wire pll_lock_en = icr | pll_lock; +sirv_gnrl_dfflr #(1) pll_lock_r_dfflr (pll_lock_en, pll_lock, pll_lock_r, clk, rst_n); + + +//pll_lost_lock_r +wire pll_lost_lock_en = icr | pll_lock; +sirv_gnrl_dfflr #(1) pll_lost_lock_r_dfflr (pll_lost_lock_en, pll_lost_lock, pll_lost_lock_r, clk, rst_n); + + +//ch0_dbg_upd_r +wire ch0_dbg_upd_en = icr | ch0_dbg_upd; +sirv_gnrl_dfflr #(1) ch0_dbg_upd_r_dfflr (ch0_dbg_upd_en, ch0_dbg_upd, ch0_dbg_upd_r, clk, rst_n); + +//ch0_dbg_fifo_e_r +wire ch0_dbg_fifo_e_en = icr | ch0_dbg_fifo_e; +sirv_gnrl_dfflr #(1) ch0_dbg_fifo_e_r_dfflr (ch0_dbg_fifo_e_en, ch0_dbg_fifo_e, ch0_dbg_fifo_e_r, clk, rst_n); + +//ch0_dbg_fifo_f_r +wire ch0_dbg_fifo_f_en = icr | ch0_dbg_fifo_f; +sirv_gnrl_dfflr #(1) ch0_dbg_fifo_f_r_dfflr (ch0_dbg_fifo_f_en, ch0_dbg_fifo_f, ch0_dbg_fifo_f_r, clk, rst_n); + +//ch0_ldst_addr_unalgn_r +wire ch0_ldst_addr_unalgn_en = icr | ch0_ldst_addr_unalgn; +sirv_gnrl_dfflr #(1) ch0_ldst_addr_unalgn_r_dfflr (ch0_ldst_addr_unalgn_en, ch0_ldst_addr_unalgn, ch0_ldst_addr_unalgn_r, clk, rst_n); + +//ch0_dec_err_r +wire ch0_dec_err_en = icr | ch0_dec_err; +sirv_gnrl_dfflr #(1) ch0_dec_err_r_dfflr (ch0_dec_err_en, ch0_dec_err, ch0_dec_err_r, clk, rst_n); + +//ch0_exit_irq_r +wire ch0_exit_irq_en = icr | ch0_exit_irq; +sirv_gnrl_dfflr #(1) ch0_exit_irq_r_dfflr (ch0_exit_irq_en, ch0_exit_irq, ch0_exit_irq_r, clk, rst_n); + + +//ch1_dbg_upd_r +wire ch1_dbg_upd_en = icr | ch1_dbg_upd; +sirv_gnrl_dfflr #(1) ch1_dbg_upd_r_dfflr (ch1_dbg_upd_en, ch1_dbg_upd, ch1_dbg_upd_r, clk, rst_n); + +//ch1_dbg_fifo_e_r +wire ch1_dbg_fifo_e_en = icr | ch1_dbg_fifo_e; +sirv_gnrl_dfflr #(1) ch1_dbg_fifo_e_r_dfflr (ch1_dbg_fifo_e_en, ch1_dbg_fifo_e, ch1_dbg_fifo_e_r, clk, rst_n); + +//ch1_dbg_fifo_f_r +wire ch1_dbg_fifo_f_en = icr | ch1_dbg_fifo_f; +sirv_gnrl_dfflr #(1) ch1_dbg_fifo_f_r_dfflr (ch1_dbg_fifo_f_en, ch1_dbg_fifo_f, ch1_dbg_fifo_f_r, clk, rst_n); + +//ch1_ldst_addr_unalgn_r +wire ch1_ldst_addr_unalgn_en = icr | ch1_ldst_addr_unalgn; +sirv_gnrl_dfflr #(1) ch1_ldst_addr_unalgn_r_dfflr (ch1_ldst_addr_unalgn_en, ch1_ldst_addr_unalgn, ch1_ldst_addr_unalgn_r, clk, rst_n); + +//ch1_dec_err_r +wire ch1_dec_err_en = icr | ch1_dec_err; +sirv_gnrl_dfflr #(1) ch1_dec_err_r_dfflr (ch1_dec_err_en, ch1_dec_err, ch1_dec_err_r, clk, rst_n); + +//ch1_exit_irq_r +wire ch1_exit_irq_en = icr | ch1_exit_irq; +sirv_gnrl_dfflr #(1) ch1_exit_irq_r_dfflr (ch1_exit_irq_en, ch1_exit_irq, ch1_exit_irq_r, clk, rst_n); + +//ch2_dbg_upd_r +wire ch2_dbg_upd_en = icr | ch2_dbg_upd; +sirv_gnrl_dfflr #(1) ch2_dbg_upd_r_dfflr (ch2_dbg_upd_en, ch2_dbg_upd, ch2_dbg_upd_r, clk, rst_n); + +//ch2_dbg_fifo_e_r +wire ch2_dbg_fifo_e_en = icr | ch2_dbg_fifo_e; +sirv_gnrl_dfflr #(1) ch2_dbg_fifo_e_r_dfflr (ch2_dbg_fifo_e_en, ch2_dbg_fifo_e, ch2_dbg_fifo_e_r, clk, rst_n); + +//ch2_dbg_fifo_f_r +wire ch2_dbg_fifo_f_en = icr | ch2_dbg_fifo_f; +sirv_gnrl_dfflr #(1) ch2_dbg_fifo_f_r_dfflr (ch2_dbg_fifo_f_en, ch2_dbg_fifo_f, ch2_dbg_fifo_f_r, clk, rst_n); + +//ch2_ldst_addr_unalgn_r +wire ch2_ldst_addr_unalgn_en = icr | ch2_ldst_addr_unalgn; +sirv_gnrl_dfflr #(1) ch2_ldst_addr_unalgn_r_dfflr (ch2_ldst_addr_unalgn_en, ch2_ldst_addr_unalgn, ch2_ldst_addr_unalgn_r, clk, rst_n); + +//ch2_dec_err_r +wire ch2_dec_err_en = icr | ch2_dec_err; +sirv_gnrl_dfflr #(1) ch2_dec_err_r_dfflr (ch2_dec_err_en, ch2_dec_err, ch2_dec_err_r, clk, rst_n); + +//ch2_exit_irq_r +wire ch2_exit_irq_en = icr | ch2_exit_irq; +sirv_gnrl_dfflr #(1) ch2_exit_irq_r_dfflr (ch2_exit_irq_en, ch2_exit_irq, ch2_exit_irq_r, clk, rst_n); + +//ch3_dbg_upd_r +wire ch3_dbg_upd_en = icr | ch3_dbg_upd; +sirv_gnrl_dfflr #(1) ch3_dbg_upd_r_dfflr (ch3_dbg_upd_en, ch3_dbg_upd, ch3_dbg_upd_r, clk, rst_n); + +//ch3_dbg_fifo_e_r +wire ch3_dbg_fifo_e_en = icr | ch3_dbg_fifo_e; +sirv_gnrl_dfflr #(1) ch3_dbg_fifo_e_r_dfflr (ch3_dbg_fifo_e_en, ch3_dbg_fifo_e, ch3_dbg_fifo_e_r, clk, rst_n); + +//ch3_dbg_fifo_f_r +wire ch3_dbg_fifo_f_en = icr | ch3_dbg_fifo_f; +sirv_gnrl_dfflr #(1) ch3_dbg_fifo_f_r_dfflr (ch3_dbg_fifo_f_en, ch3_dbg_fifo_f, ch3_dbg_fifo_f_r, clk, rst_n); + +//ch3_ldst_addr_unalgn_r +wire ch3_ldst_addr_unalgn_en = icr | ch3_ldst_addr_unalgn; +sirv_gnrl_dfflr #(1) ch3_ldst_addr_unalgn_r_dfflr (ch3_ldst_addr_unalgn_en, ch3_ldst_addr_unalgn, ch3_ldst_addr_unalgn_r, clk, rst_n); + +//ch3_dec_err_r +wire ch3_dec_err_en = icr | ch3_dec_err; +sirv_gnrl_dfflr #(1) ch3_dec_err_r_dfflr (ch3_dec_err_en, ch3_dec_err, ch3_dec_err_r, clk, rst_n); + +//ch3_exit_irq_r +wire ch3_exit_irq_en = icr | ch3_exit_irq; +sirv_gnrl_dfflr #(1) ch3_exit_irq_r_dfflr (ch3_exit_irq_en, ch3_exit_irq, ch3_exit_irq_r, clk, rst_n); + +//irisr +assign irisr[31] = pll_lock_r ; +assign irisr[30] = pll_lost_lock_r ; +assign irisr[29] = ch3_dbg_upd_r ; +assign irisr[28] = ch3_dbg_fifo_e_r ; +assign irisr[27] = ch3_dbg_fifo_f_r ; +assign irisr[26] = ch3_ldst_addr_unalgn_r ; +assign irisr[25] = ch3_dec_err_r ; +assign irisr[24] = ch3_exit_irq_r ; +assign irisr[23] = L ; +assign irisr[22] = L ; +assign irisr[21] = ch2_dbg_upd_r ; +assign irisr[20] = ch2_dbg_fifo_e_r ; +assign irisr[19] = ch2_dbg_fifo_f_r ; +assign irisr[18] = ch2_ldst_addr_unalgn_r ; +assign irisr[17] = ch2_dec_err_r ; +assign irisr[16] = ch2_exit_irq_r ; +assign irisr[15] = L ; +assign irisr[14] = L ; +assign irisr[13] = ch1_dbg_upd_r ; +assign irisr[12] = ch1_dbg_fifo_e_r ; +assign irisr[11] = ch1_dbg_fifo_f_r ; +assign irisr[10] = ch1_ldst_addr_unalgn_r ; +assign irisr[9 ] = ch1_dec_err_r ; +assign irisr[8 ] = ch1_exit_irq_r ; +assign irisr[7 ] = L ; +assign irisr[6 ] = L ; +assign irisr[5 ] = ch0_dbg_upd_r ; +assign irisr[4 ] = ch0_dbg_fifo_e_r ; +assign irisr[3 ] = ch0_dbg_fifo_f_r ; +assign irisr[2 ] = ch0_ldst_addr_unalgn_r ; +assign irisr[1 ] = ch0_dec_err_r ; +assign irisr[0 ] = ch0_exit_irq_r ; + +// ------------------------------------------------------ +// -- Interrupt Status Register - Read Only +// +// This register contains the status of all +// XYZ Chip interrupts after masking. +// ------------------------------------------------------ +sirv_gnrl_dffr #(32) isr_dffr (irisr, isr, clk, rst_n); + +//misr +wire[31:0] misr_w = imr & irisr; +sirv_gnrl_dffr #(32) misr_dffr (misr_w, misr, clk, rst_n); + +//irq +wire irq_w = |misr; +sirv_gnrl_dffr #(1) irq_dffr (irq_w, irq, clk, rst_n); + + +endmodule + + +`undef IDR +`undef VIDR +`undef DATER +`undef VERR +`undef TESTR +`undef IMR +`undef ISR +`undef MISR +`undef SFRTR +`undef SFRR +`undef MCURSTR +`undef AWGRSTR +`undef DACRSTR diff --git a/tb/testbench/rtl/tb.v b/tb/testbench/rtl/tb.v new file mode 100644 index 0000000..815e9f9 --- /dev/null +++ b/tb/testbench/rtl/tb.v @@ -0,0 +1,121 @@ +module TB(); + +reg clk; +reg rstn; +reg sclk; +reg csn; +reg mosi; +wire error_check; +wire miso_oen; +wire miso; +/* +initial +begin + $fsdbDumpfile("TB.fsdb"); + $fsdbDumpvars(0, TB); +end +*/ +initial begin + #0; + rstn =1'b1; + #3000; + rstn =1'b0; + #3000; + rstn =1'b1; +end + +initial begin + #0; + csn = 1; + #6400; + csn = 0; + #6400; + csn = 1; + #6400; + csn = 0; + #12800; + csn = 1; + #6400; + csn = 0; + #6400; + csn = 1; + #6400; + csn = 0; + #12800; + csn = 1; + + #6400; + csn = 0; + #8000; + csn = 1; + #6400; + csn = 0; + #16000; + csn = 1; +end + + + + + + +reg [623:0] data = 624'h0000_1000_ffff_ffff_4000_4000_aaaa_aaaa_5555_5555_1111_1111_8000_1000_0000_0000_c000_4000_0000_0000_0000_0000_0000_0000_0000_1000_ffff_ffff_ffff_4000_4000_aaaa_aaaa_5555_5555_1111_1111_1111_1111; + + +reg [25:0] data_cnt; + +always@(posedge sclk or negedge rstn) + if(!rstn) + data_cnt <= 26'd623; + else if (data_cnt > 0 && (~csn)) + data_cnt <= data_cnt - 1'b1; + else + data_cnt <= data_cnt; + + + +always@(posedge clk or negedge rstn) + if(!rstn) + mosi <= 1'b0; + else + mosi <= data[data_cnt]; + + + +initial begin + #0; + clk = 1'b1; + sclk = 1'b1; +end + +always #5 clk = ~clk; +always #50 sclk = ~sclk; + +reg [21:0] cnt; +always@(posedge clk or negedge rstn) + if(!rstn) + cnt <= 22'd0; + else + cnt <= cnt + 22'd1; + +initial begin + wait(cnt[16]==1'b1) + $finish(0); +end + + + +spi_top_4 spi_top_4_inst( + .clk(clk) +,.rstn(rstn) +,.sclk(sclk) +,.csn(csn) +,.mosi(mosi) +,.miso(miso) +,.miso_oen(miso_oen) +,.error_check(error_check) + + +); + +endmodule diff --git a/tb/testbench/spi_tb/spi_driver.sv b/tb/testbench/spi_tb/spi_driver.sv new file mode 100644 index 0000000..c574ca8 --- /dev/null +++ b/tb/testbench/spi_tb/spi_driver.sv @@ -0,0 +1,161 @@ +class spi_driver; + + static bit my_cmd=1'b0; + static bit[24:0] last_addr; + static bit last_s; + + //MOSI data pkt, other input_signals are not packed + spi_trans m_trans; + + //interface + virtual spi_if vif; + + //MOSI data_stream input to SPI(DUT) + bit stream[$]; + + //parameter for randomization + int pktnum; + int interval; + rand int error_time; + int half_sclk; + bit autarchy; + + + + constraint cstr{ + error_time <= 544; + error_time >= -544; + } + + function new(); + endfunction + extern task do_drive(); + extern task make_pkt(spi_trans tr); + +endclass : spi_driver + + +task spi_driver::do_drive(); + + $display("pkt_num:\t%0d",pktnum); + + while(!vif.rstn) begin + vif.csn = 1'b1; + vif.sclk = 1'b1; + @(posedge vif.clk); + end + + while(pktnum>0) begin + + //$display(my_cmd); + make_pkt(m_trans); + + repeat(interval) + @(posedge vif.clk); + + pktnum--; + end + +endtask : do_drive + + +task spi_driver::make_pkt(spi_trans tr); + int i=0,j=0; + int cs_time,mo_time; + + + //**********************Create and Randomize a pkt**********************// + tr = new(); + + if(!tr.randomize() with { + cmd==my_cmd; + (cmd==1'b0 || s==last_s); + (cmd==1'b0 || addr==last_addr); + addr[24:20] == 5'b00000 || + addr[24:20] == 5'b00001 || + addr[24:20] == 5'b00010; + }) + $fatal(0,"Randomize Failed"); + + if(tr.cmd == 1'b0) begin + last_addr = tr.addr; + last_s = tr.s; + end + + my_cmd = ~my_cmd; + + + //Autarchy: Testcase force to assign some params + interval = tr.interval; + if(!autarchy) begin + half_sclk = tr.half_sclk; + end + + + //*****************initialize chip_select and input_clk******************// + vif.csn <= 1'b1; + vif.sclk <= 1'b1; + vif.mosi <= stream[0]; + @(posedge vif.clk); + vif.csn <= 1'b0; + vif.sclk <= 1'b1; + + //unpack into bitstream + stream.delete(); + tr.unpack(stream); + + //mosi valid time: time for bitstream to be all sent + //csn valid_time: maybe a delay after or ahead of mosi_finished + mo_time = (stream.size())*2*half_sclk; + cs_time = (pktnum==1) ? (mo_time + error_time%mo_time) : mo_time; + + $display("***************************ONE PKT DRIVERED***************************"); + $display("half_sclk:\t%0d\t\t\t\t\t\t **",half_sclk); + $display("interval:\t%0d\t\t\t\t\t\t **",interval); + //$display("error_time:\t%0d\t\t\t\t\t\t **",error_time); + //$display("data_size:\t%0d\t\t\t\t\t\t **",tr.data.size()); + //$display("cmd:\t\t%0d\t\t\t\t\t\t **",tr.cmd); + //$display(stream); + if(!tr.cmd) + for(i=0;i= 0; + half_sclk <= 32; + half_sclk >= 4; + (addr >= 25'h000_0000 && + addr <= 25'h000_0033 && + s == 1'b0 ) || + (addr >= 25'h010_0000 && + addr <= 25'h010_001F && + s == 1'b0 ) || + (addr >= 25'h010_0040 && + addr <= 25'h010_00A7 && + s == 1'b0 ) || + (addr >= 25'h010_0040 && + addr <= 25'h010_0067 && + s == 1'b1 ) || + (addr >= 25'h020_0000 && + addr <= 25'h020_001F && + s == 1'b0 ) || + (addr >= 25'h020_0098 && + addr <= 25'h020_00A3 && + s == 1'b0 ) || + (addr >= 25'h020_0100 && + addr <= 25'h020_0123 && + s == 1'b0 ) || + (addr >= 25'h020_0128 && + addr <= 25'h020_014F && + s == 1'b1 ) || + (addr >= 25'h020_0128 && + addr <= 25'h020_018F && + s == 1'b0 ); + (addr < 25'h000_0020) || + (addr > 25'h000_0023) || + (data[0] <= 500); + } + + function new(); + endfunction + + extern function bit compare(spi_trans rhs_); + extern function void print(); + extern function void unpack(ref bit stream[$]); + +endclass : spi_trans + + + +function bit spi_trans::compare(spi_trans rhs_); + bit result=1'b1; + int i=0; + + result = ((this.cmd == rhs_.cmd) && + (this.s == rhs_.s) && + (this.addr == rhs_.addr) && + (this.op == rhs_.op)); + + if(this.data.size() != rhs_.data.size()) begin + $display("data_sizes are different"); + result = 1'b0; + end + else + for(i=0;i= -544; + } + + function new(); + endfunction + extern task do_drive(); + extern task make_pkt(spi_trans tr); + +endclass : spi_driver + + +task spi_driver::do_drive(); + + $display("pkt_num:\t%0d",pktnum); + + while(!vif.rstn) begin + vif.csn = 1'b1; + vif.sclk = 1'b1; + @(posedge vif.clk); + end + + while(pktnum>0) begin + + //$display(my_cmd); + make_pkt(m_trans); + + repeat(interval) + @(posedge vif.clk); + + pktnum--; + end + +endtask : do_drive + + +task spi_driver::make_pkt(spi_trans tr); + int i=0,j=0; + int cs_time,mo_time; + + + //**********************Create and Randomize a pkt**********************// + tr = new(); + + if(!tr.randomize() with { + cmd==my_cmd; + (cmd==1'b0 || s==last_s); + (cmd==1'b0 || addr==last_addr); + addr[24:20] == 5'b00000; + }) + $fatal(0,"Randomize Failed"); + + if(tr.cmd == 1'b0) begin + last_addr = tr.addr; + last_s = tr.s; + end + + my_cmd = ~my_cmd; + + + //Autarchy: Testcase force to assign some params + interval = tr.interval; + if(!autarchy) begin + half_sclk = tr.half_sclk; + end + + + //*****************initialize chip_select and input_clk******************// + vif.csn <= 1'b1; + vif.sclk <= 1'b1; + vif.mosi <= stream[0]; + @(posedge vif.clk); + vif.csn <= 1'b0; + vif.sclk <= 1'b1; + + //unpack into bitstream + stream.delete(); + tr.unpack(stream); + + //mosi valid time: time for bitstream to be all sent + //csn valid_time: maybe a delay after or ahead of mosi_finished + mo_time = (stream.size())*2*half_sclk; + cs_time = (pktnum==1) ? (mo_time + error_time%mo_time) : mo_time; + + $display("***************************ONE PKT DRIVERED***************************"); + $display("half_sclk:\t%0d\t\t\t\t\t\t **",half_sclk); + $display("interval:\t%0d\t\t\t\t\t\t **",interval); + //$display("error_time:\t%0d\t\t\t\t\t\t **",error_time); + //$display("data_size:\t%0d\t\t\t\t\t\t **",tr.data.size()); + //$display("cmd:\t\t%0d\t\t\t\t\t\t **",tr.cmd); + //$display(stream); + if(!tr.cmd) + for(i=0;i= 0; + half_sclk <= 32; + half_sclk >= 4; + (addr >= 25'h000_0000 && + addr <= 25'h000_0033 && + s == 1'b0 ) || + (addr >= 25'h010_0000 && + addr <= 25'h010_001F && + s == 1'b0 ) || + (addr >= 25'h010_0040 && + addr <= 25'h010_00A7 && + s == 1'b0 ) || + (addr >= 25'h010_0040 && + addr <= 25'h010_0067 && + s == 1'b1 ) || + (addr >= 25'h020_0000 && + addr <= 25'h020_001F && + s == 1'b0 ) || + (addr >= 25'h020_0098 && + addr <= 25'h020_00A3 && + s == 1'b0 ) || + (addr >= 25'h020_0100 && + addr <= 25'h020_0123 && + s == 1'b0 ) || + (addr >= 25'h020_0128 && + addr <= 25'h020_014F && + s == 1'b1 ) || + (addr >= 25'h020_0128 && + addr <= 25'h020_018F && + s == 1'b0 ); + (addr < 25'h000_0020) || + (addr > 25'h000_0023) || + (data[0] <= 500); + } + + function new(); + endfunction + + extern function bit compare(spi_trans rhs_); + extern function void print(); + extern function void unpack(ref bit stream[$]); + +endclass : spi_trans + + + +function bit spi_trans::compare(spi_trans rhs_); + bit result=1'b1; + int i=0; + + result = ((this.cmd == rhs_.cmd) && + (this.s == rhs_.s) && + (this.addr == rhs_.addr) && + (this.op == rhs_.op)); + + if(this.data.size() != rhs_.data.size()) begin + $display("data_sizes are different"); + result = 1'b0; + end + else + for(i=0;i0) begin + @(posedge wif.clk); + if(vif.soft_rstn[i]) + break; + cnt--; + end + + @(negedge wif.clk); + if(cnt!=0 | !vif.soft_rstn[i]) begin + rst_error[i]++; + $display("\nScoreBoard(ERROR): rst_time_error"); + case(i) + 0: $display("rst_module:\tSYS"); + 1: $display("rst_module:\tMCU"); + 2: $display("rst_module:\tAWG"); + 3: $display("rst_module:\tDAC"); + endcase + $display("cnt:\t%d",cnt); + $display("soft_rstn:\t%b",vif.soft_rstn[i]); + $display("rst cmd time: @%0dth pkt.\n",pkt_i); + end + //else + //$display("\nScoreBoard: @%0dth pkt, sys_rst successfully!\n",sys_i_save); + if(!wif.csn) @(posedge wif.csn); + +endtask: rst_check diff --git a/tb/testbench/sysreg_tb/sysreg_scb.sv b/tb/testbench/sysreg_tb/sysreg_scb.sv new file mode 100644 index 0000000..039f5ea --- /dev/null +++ b/tb/testbench/sysreg_tb/sysreg_scb.sv @@ -0,0 +1,190 @@ +class sysreg_scoreboard; + + + int pktnum; + + virtual spi_if wif; + + bit my_din[$]; + bit[31:0] my_dout[$]; + bit[31:0] my_isr; + bit[31:0] my_imr; + + //Vars in intr_check + int isr_error=0; + + function new(); + endfunction; + + extern task do_check(); + + extern function bit compare( + bit din[$], + bit[31:0] dout[$], + bit[31:0] isr, + bit[31:0] imr + ); + + + +endclass + + +task sysreg_scoreboard::do_check(); + int pkt_i=0; + + + fork + //sysreg_scoreboard + while(1) begin + if(pkt_i==pktnum) break; + @(posedge wif.csn); + repeat(10) @(negedge wif.clk); + if(!compare(my_din,my_dout,my_isr,my_imr)) + isr_error++; + end + + repeat(pktnum) begin: kill_progress + @(negedge wif.csn); + pkt_i++; + end + + join + +endtask + + +function bit sysreg_scoreboard::compare( + bit din[$], + bit[31:0] dout[$], + bit[31:0] isr, + bit[31:0] imr +); + + bit[31:0] data[$]; + bit[4 :0] chip; + bit[15:0] addr; + bit result=1'b1; + +//$display(dout); + + chip[ 1: 0] = {>>{din[ 5: 6]}}; + addr[15: 0] = {>>{din[11:26]}}; + data = {>>{din[32: $]}}; + + if(chip != 2'b0) begin + //result = 1'b0; + //$display("ScoreBoard(ERROR): Error chip-select!"); + end + + //if read,Compare the "data" send via MISO With the data written last cycle + else if(din[0]) begin + + $display("\nScoreBoard: addr:16'h%h",addr); + + if(data.size()!=1 | dout.size()!=1) begin + result = 1'b0; + $display("ScoreBoard(ERROR): Size ARNT'T equal!"); + $display("Exp data size:%0d",data.size()); + $display("Act data size:%0d",dout.size()); + end + + else + + case(addr[15:2]) + 14'h00: + begin + if(dout[0]!=32'h4157_4743) begin + result = 1'b0; + $display("ScoreBoard(IDRD ERROR):"); + $display("\tExp:32'h4157_4743"); + $display("\tAct:%b",dout[0]); end + else $display("ScoreBoard: IDRD register is read successfully!"); + end + 14'h01: + begin + if(dout[0]!=32'h5553_5443) begin + result = 1'b0; + $display("ScoreBoard(VIDR ERROR):"); + $display("\tExp:32'h5553_5443"); + $display("\tAct data:%b",dout[0]); end + else $display("ScoreBoard: VIDR register is read successfully!"); + end + 14'h02: + begin + if(dout[0]!=32'h2022_0831) begin + result = 1'b0; + $display("ScoreBoard(DATERD ERROR):"); + $display("\tExp:32'h2022_0831"); + $display("\tAct:%b",dout[0]); end + else $display("ScoreBoard: DATERD register is read successfully!"); + end + 14'h03: + begin + if(dout[0]!=32'h0000_0001) begin + result = 1'b0; + $display("ScoreBoard(VERSION ERROR):"); + $display("\tExp:32'h0000_0001"); + $display("\tAct:%b",dout[0]); end + else $display("ScoreBoard: VERSION register is read successfully!"); + end + 14'h04: + begin + if(dout[0]!=data[0]) begin + result = 1'b0; + $display("ScoreBoard(ERROR):"); + $display("\tExp testr:%b",data[0]); + $display("\tAct testr:%b",dout[0]); end + else $display("ScoreBoard: TESTR register is write&read successfully!"); + end + 14'h05: + begin + if(dout[0]!=imr) begin + result = 1'b0; + $display("ScoreBoard(ERROR):"); + $display("\tExp imr:%b",imr); + $display("\tAct imr:%b",dout[0]); end + else $display("ScoreBoard: IMR register is read successfully!"); + end + 14'h06: + begin + if(dout[0]!=isr) begin + result = 1'b0; + $display("ScoreBoard(ISR ERROR):"); + $display("\tExp isr:%b",isr); + $display("\tAct isr:%b",dout[0]); end + else $display("ScoreBoard: ISR register is read successfully!"); + end + 14'h07: + begin + if(dout[0]!=(imr & isr)) begin + result = 1'b0; + $display("ScoreBoard(misr ERROR):"); + $display("\tExp misr:%b",imr & isr); + $display("\tAct misr:%b",dout[0]); + $display("\tExp imr:%b",imr); + $display("\tExp isr:%b",isr); end + else $display("ScoreBoard: MISR register is read successfully!"); + end + 14'h08: + begin + if(dout[0]!=data[0]) begin + result = 1'b0; + $display("ScoreBoard(ERROR):"); + $display("\tExp soft_rst_time:%b",data[0]); + $display("\tAct soft_rst_time:%b",dout[0]); end + else $display("ScoreBoard: SFRTR register is write&read successfully!"); + end + default: begin if(addr<16'h33) $display("ScoreBoard: START A RST!"); + else $display("ScoreBoard: Error Address!"); end + endcase + + $display(""); + end + + return result; + +endfunction + + + diff --git a/tb/testbench/sysreg_tb/sysreg_trans.sv b/tb/testbench/sysreg_tb/sysreg_trans.sv new file mode 100644 index 0000000..5d66554 --- /dev/null +++ b/tb/testbench/sysreg_tb/sysreg_trans.sv @@ -0,0 +1,137 @@ +class sysreg_trans; + + //Properties for Randomizing the MOSI + /*bit pll_lock; + bit pll_lost_lock; + bit ch0_dbg_upd ; + bit ch0_dbg_fifo_e; + bit ch0_dbg_fifo_f; + bit ch0_ldst_addr_unalgn; + bit ch0_dec_err; + bit ch0_exit_irq ; + bit ch1_dbg_upd ; + bit ch1_dbg_fifo_e ; + bit ch1_dbg_fifo_f ; + bit ch1_ldst_addr_unalgn ; + bit ch1_dec_err ; + bit ch1_exit_irq ; + bit ch2_dbg_upd ; + bit ch2_dbg_fifo_e ; + bit ch2_dbg_fifo_f ; + bit ch2_ldst_addr_unalgn ; + bit ch2_dec_err ; + bit ch2_exit_irq ; + bit ch3_dbg_upd ; + bit ch3_dbg_fifo_e ; + bit ch3_dbg_fifo_f ; + bit ch3_ldst_addr_unalgn ; + bit ch3_dec_err ; + bit ch3_exit_irq ; + bit sys_soft_rstn ; + bit mcu_soft_rstn ; + bit awg_soft_rstn ; + bit dac_soft_rstn ; + bit irq ;*/ + + rand int pll_lock_time ; + rand int pll_lost_lock_time ; + rand int ch0_dbg_upd_time ; + rand int ch0_dbg_fifo_e_time ; + rand int ch0_dbg_fifo_f_time ; + rand int ch0_ldst_addr_unalgn_time; + rand int ch0_dec_err_time ; + rand int ch0_exit_irq_time ; + rand int ch1_dbg_upd_time ; + rand int ch1_dbg_fifo_e_time ; + rand int ch1_dbg_fifo_f_time ; + rand int ch1_ldst_addr_unalgn_time; + rand int ch1_dec_err_time ; + rand int ch1_exit_irq_time ; + rand int ch2_dbg_upd_time ; + rand int ch2_dbg_fifo_e_time ; + rand int ch2_dbg_fifo_f_time ; + rand int ch2_ldst_addr_unalgn_time ; + rand int ch2_dec_err_time ; + rand int ch2_exit_irq_time ; + rand int ch3_dbg_upd_time ; + rand int ch3_dbg_fifo_e_time ; + rand int ch3_dbg_fifo_f_time ; + rand int ch3_ldst_addr_unalgn_time ; + rand int ch3_dec_err_time ; + rand int ch3_exit_irq_time ; + +constraint cstr { + pll_lock_time <= 5000 ; + pll_lost_lock_time <= 5000 ; + ch0_dbg_upd_time <= 5000 ; + ch0_dbg_fifo_e_time <= 5000 ; + ch0_dbg_fifo_f_time <= 5000 ; + ch0_ldst_addr_unalgn_time <= 5000 ; + ch0_dec_err_time <= 5000 ; + ch0_exit_irq_time <= 5000 ; + ch1_dbg_upd_time <= 5000 ; + ch1_dbg_fifo_e_time <= 5000 ; + ch1_dbg_fifo_f_time <= 5000 ; + ch1_ldst_addr_unalgn_time <= 5000 ; + ch1_dec_err_time <= 5000 ; + ch1_exit_irq_time <= 5000 ; + ch2_dbg_upd_time <= 5000 ; + ch2_dbg_fifo_e_time <= 5000 ; + ch2_dbg_fifo_f_time <= 5000 ; + ch2_ldst_addr_unalgn_time <= 5000 ; + ch2_dec_err_time <= 5000 ; + ch2_exit_irq_time <= 5000 ; + ch3_dbg_upd_time <= 5000 ; + ch3_dbg_fifo_e_time <= 5000 ; + ch3_dbg_fifo_f_time <= 5000 ; + ch3_ldst_addr_unalgn_time <= 5000 ; + ch3_dec_err_time <= 5000 ; + ch3_exit_irq_time <= 5000 ; + pll_lock_time > 10 ; + pll_lost_lock_time > 10 ; + ch0_dbg_upd_time > 10 ; + ch0_dbg_fifo_e_time > 10 ; + ch0_dbg_fifo_f_time > 10 ; + ch0_ldst_addr_unalgn_time > 10 ; + ch0_dec_err_time > 10 ; + ch0_exit_irq_time > 10 ; + ch1_dbg_upd_time > 10 ; + ch1_dbg_fifo_e_time > 10 ; + ch1_dbg_fifo_f_time > 10 ; + ch1_ldst_addr_unalgn_time > 10 ; + ch1_dec_err_time > 10 ; + ch1_exit_irq_time > 10 ; + ch2_dbg_upd_time > 10 ; + ch2_dbg_fifo_e_time > 10 ; + ch2_dbg_fifo_f_time > 10 ; + ch2_ldst_addr_unalgn_time > 10 ; + ch2_dec_err_time > 10 ; + ch2_exit_irq_time > 10 ; + ch3_dbg_upd_time > 10 ; + ch3_dbg_fifo_e_time > 10 ; + ch3_dbg_fifo_f_time > 10 ; + ch3_ldst_addr_unalgn_time > 10 ; + ch3_dec_err_time > 10 ; + ch3_exit_irq_time > 10 ; +} + + function new(); + endfunction + + extern function bit compare(spi_trans rhs_); + extern function void print(); + extern function void unpack(ref bit stream[$]); + +endclass : sysreg_trans + + + + + + + + + + + + diff --git a/tb/testbench/sysreg_tb/tb.sv b/tb/testbench/sysreg_tb/tb.sv new file mode 100644 index 0000000..5b79d8a --- /dev/null +++ b/tb/testbench/sysreg_tb/tb.sv @@ -0,0 +1,297 @@ + +module TB(); + + initial begin + $fsdbDumpfile("TB1.fsdb"); + $fsdbDumpvars(0, TB); + //$fsdbDumpMDA(); + end + + reg clk; + reg rstn; + initial begin + #0; + rstn = 1'b0; + clk = 1'b0; + #10; + rstn = 1'b1; + end + + always #0.5 clk = ~clk; + + reg [31:0] cnt; + always@(posedge clk or negedge rstn) + if(!rstn) + cnt <= 32'd0; + else + cnt <= cnt + 32'd1; + + initial begin + wait(cnt[31]==1'b1) + $finish(0); + end + + + + wire miso; // Spi Miso + wire miso_oen; // Spi Miso output enable + + + spi_if dut_if(clk,rstn); + + /*spi_slave dut( + .clk (clk ) + ,.rstn (rstn ) + ,.sclk (dut_if.sclk ) + ,.csn (dut_if.csn ) + ,.mosi (dut_if.mosi ) + ,.miso (miso ) + ,.miso_oen (miso_oen ) + ,.error_check (dut_if.error_check ) + );//*/ + + + spi_to_sram dut( + .clk (clk ) + ,.spi_rstn (rstn ) + ,.sclk (dut_if.sclk ) + ,.csn (dut_if.csn ) + ,.mosi (dut_if.mosi ) + ,.miso (miso ) + ,.miso_oen (miso_oen ) + ,.error_check (dut_if.error_check ) + ,.addr (mst.addr ) + ,.wren (mst.wren ) + ,.wrdata (mst.din ) + ,.rden (mst.rden ) + ,.rddata (mst.dout ) + );//*/ + + +reg [4:0] scnt; + always@(posedge dut_if.sclk or posedge dut_if.csn) + if(dut_if.csn) + scnt <= 5'd0; + else if(dut_if.csn==1'b0) + scnt <= scnt + 5'd1; + + + +sram_if#(25,32) mst(clk); +sram_if#(25,32) slv[31:0](clk); + generate + genvar i; + for(i=3;i<31;i++) + begin: sram + spram_model #( + .width(32), + .depth(1048576) + ) sram_block( + .clka (clk ) + ,.ena (slv[i].wren ) + ,.dina (slv[i].din ) + ,.addra (slv[i].addr[19:0] ) + + ,.clkb (clk ) + ,.enb (slv[i].rden ) + ,.doutb (slv[i].dout ) + ,.addrb (slv[i].addr[19:0] ) + ); + end + endgenerate//*/ + +//*****************************reg_files inst*************************************** +//**********************************SYS********************************** + +sysreg_if sys_if(clk,rstn); + +system_regfile system_reg_inst( + .clk (clk ) + ,.rst_n (rstn ) + ,.wrdata (slv[0].din ) + ,.wren (slv[0].wren ) + ,.rwaddr (slv[0].addr[15:0] ) + ,.rden (slv[0].rden ) + ,.rddata (slv[0].dout ) + ,.pll_lock (sys_if.pll_lock ) + ,.pll_lost_lock (sys_if.pll_lost_lock ) + ,.ch0_dbg_upd (sys_if.ch0_dbg_upd ) + ,.ch0_dbg_fifo_e (sys_if.ch0_dbg_fifo_e ) + ,.ch0_dbg_fifo_f (sys_if.ch0_dbg_fifo_f ) + ,.ch0_ldst_addr_unalgn (sys_if.ch0_ldst_addr_unalgn ) + ,.ch0_dec_err (sys_if.ch0_dec_err ) + ,.ch0_exit_irq (sys_if.ch0_exit_irq ) + ,.ch1_dbg_upd (sys_if.ch1_dbg_upd ) + ,.ch1_dbg_fifo_e (sys_if.ch1_dbg_fifo_e ) + ,.ch1_dbg_fifo_f (sys_if.ch1_dbg_fifo_f ) + ,.ch1_ldst_addr_unalgn (sys_if.ch1_ldst_addr_unalgn ) + ,.ch1_dec_err (sys_if.ch1_dec_err ) + ,.ch1_exit_irq (sys_if.ch1_exit_irq ) + ,.ch2_dbg_upd (sys_if.ch2_dbg_upd ) + ,.ch2_dbg_fifo_e (sys_if.ch2_dbg_fifo_e ) + ,.ch2_dbg_fifo_f (sys_if.ch2_dbg_fifo_f ) + ,.ch2_ldst_addr_unalgn (sys_if.ch2_ldst_addr_unalgn ) + ,.ch2_dec_err (sys_if.ch2_dec_err ) + ,.ch2_exit_irq (sys_if.ch2_exit_irq ) + ,.ch3_dbg_upd (sys_if.ch3_dbg_upd ) + ,.ch3_dbg_fifo_e (sys_if.ch3_dbg_fifo_e ) + ,.ch3_dbg_fifo_f (sys_if.ch3_dbg_fifo_f ) + ,.ch3_ldst_addr_unalgn (sys_if.ch3_ldst_addr_unalgn ) + ,.ch3_dec_err (sys_if.ch3_dec_err ) + ,.ch3_exit_irq (sys_if.ch3_exit_irq ) + ,.sys_soft_rstn (sys_if.soft_rstn[0] ) + ,.mcu_soft_rstn (sys_if.soft_rstn[1] ) + ,.awg_soft_rstn (sys_if.soft_rstn[2] ) + ,.dac_soft_rstn (sys_if.soft_rstn[3] ) + ,.irq (sys_if.irq ) +); + + + +reg cr; +always@(negedge clk or negedge rstn) begin + if(!rstn) cr <= 1'b0; + else if(cnt=='h3dcd1) + cr <= 1; + else if(cr) + cr <= 0; +end +//assign sys_if.pll_lock = cr; +//assign sys_if.pll_lock = system_reg_inst.icr; +//**********************************MCU********************************** +//MCU and SPI interface for interaction +mcureg_if mcu_if(clk,rstn); + +wire[31:0] mp[3:0]; +reg[31:0] mr; +always@(negedge clk or negedge rstn) begin + if(!rstn) mr <= 32'b0; + else if(cnt=='h124bd) + mr <= 32'hffff_ffff; + else if(mr) + mr <= 0; +end +//assign mcu_if.mcu_param = {32'b0,mr,32'b0,32'b0};//*/ + +mcu_regfile mcu_reg_inst( + .clk (clk ) + ,.rst_n (rstn ) + ,.wrdata (slv[1].din ) + ,.wren (slv[1].wren ) + ,.wrmask (mcu_if.wrmask ) + ,.rwaddr (slv[1].addr[15:0] ) + ,.rden (slv[1].rden ) + ,.rddata (slv[1].dout ) + ,.fb_st_info (mcu_if.fb_st_info ) + ,.run_time (mcu_if.run_time ) + ,.instr_num (mcu_if.instr_num ) + ,.mcu_param (mcu_if.mcu_param ) + ,.mcu_result (mcu_if.mcu_result ) + ,.mcu_cwfr (mcu_if.mcu_cwfr ) + ,.mcu_gapr (mcu_if.mcu_gapr ) + ,.mcu_ampr (mcu_if.mcu_ampr ) + ,.mcu_baisr (mcu_if.mcu_baisr ) + ,.mcu_intp_sel (mcu_if.mcu_intp_sel ) + ,.mcu_nco_pha_clr (mcu_if.mcu_nco_pha_clr ) + ,.mcu_rz_pha (mcu_if.mcu_rz_pha ) +);//*/ + + +//**********************************AWG********************************** +awgreg_if awg_if(clk,rstn); + +wire[31:0] ap; +reg[31:0] ar; +always@(negedge clk or negedge rstn) begin + if(!rstn) ar <= 32'b0; + else if(cnt=='h456f) + ar <= 32'hffff_ffff; + else if(ar) + ar <= 0; +end +//assign awg_if.mcu_result2 = ar; + + +awg_regfile awg_reg_inst( + .clk (clk ) + ,.rst_n (rstn ) + ,.wrdata (slv[2].din ) + ,.wren (slv[2].wren ) + ,.rwaddr (slv[2].addr[15:0] ) + ,.rden (slv[2].rden ) + ,.rddata (slv[2].dout ) + ,.fb_st_i (awg_if.fb_st_i ) + ,.run_time (awg_if.run_time ) + ,.instr_num (awg_if.instr_num ) + + ,.mcu_param0 (awg_if.mcu_param0 ) + ,.mcu_param1 (awg_if.mcu_param1 ) + ,.mcu_param2 (awg_if.mcu_param2 ) + ,.mcu_param3 (awg_if.mcu_param3 ) + ,.mcu_result0 (awg_if.mcu_result0 ) + ,.mcu_result1 (awg_if.mcu_result1 ) + ,.mcu_result2 (awg_if.mcu_result2 ) + ,.mcu_result3 (awg_if.mcu_result3 ) + ,.fb_st_o (awg_if.fb_st_o ) + ,.mod_sel_sideband (awg_if.mod_sel_sideband ) + ,.qam_nco_clr (awg_if.qam_nco_clr ) + ,.qam_fcw (awg_if.qam_fcw ) + ,.qam_pha (awg_if.qam_pha ) + ,.qam_mod (awg_if.qam_mod ) + ,.qam_sel_sideband (awg_if.qam_sel_sideband ) + ,.intp_mode (awg_if.intp_mode ) + ,.intp_sel (awg_if.intp_sel ) + ,.dac_mode_sel (awg_if.dac_mode_sel ) + ,.tc_bypass (awg_if.tc_bypass ) + ,.tcparr0 (awg_if.tcparr0 ) + ,.tcparr1 (awg_if.tcparr1 ) + ,.tcparr2 (awg_if.tcparr2 ) + ,.tcparr3 (awg_if.tcparr3 ) + ,.tcparr4 (awg_if.tcparr4 ) + ,.tcparr5 (awg_if.tcparr5 ) + ,.tcpbrr0 (awg_if.tcpbrr0 ) + ,.tcpbrr1 (awg_if.tcpbrr1 ) + ,.tcpbrr2 (awg_if.tcpbrr2 ) + ,.tcpbrr3 (awg_if.tcpbrr3 ) + ,.tcpbrr4 (awg_if.tcpbrr4 ) + ,.tcpbrr5 (awg_if.tcpbrr5 ) + ,.tcpair0 (awg_if.tcpair0 ) + ,.tcpair1 (awg_if.tcpair1 ) + ,.tcpair2 (awg_if.tcpair2 ) + ,.tcpair3 (awg_if.tcpair3 ) + ,.tcpair4 (awg_if.tcpair4 ) + ,.tcpair5 (awg_if.tcpair5 ) + ,.tcpbir0 (awg_if.tcpbir0 ) + ,.tcpbir1 (awg_if.tcpbir1 ) + ,.tcpbir2 (awg_if.tcpbir2 ) + ,.tcpbir3 (awg_if.tcpbir3 ) + ,.tcpbir4 (awg_if.tcpbir4 ) + ,.tcpbir5 (awg_if.tcpbir5 ) + ); + + + + spi_bus_decoder#(32,1,1) spi_bus_decode_inst( + .clk (clk ) + ,.rst_n (rstn ) + ,.mst (mst.slave ) + ,.slv (slv.master ) + ); + + assign dut_if.miso = (miso_oen) ? 1'bz : miso; + + + + case3 test(dut_if,sys_if,mst); + //case4 test(dut_if,sys_if,mcu_if,mst); + //case5 test(dut_if,sys_if,mcu_if,awg_if,mst); + + + + +endmodule + + + + + diff --git a/tb/testbench/tb.sv b/tb/testbench/tb.sv new file mode 100644 index 0000000..62073d4 --- /dev/null +++ b/tb/testbench/tb.sv @@ -0,0 +1,297 @@ + +module TB(); + + initial begin + $fsdbDumpfile("TB1.fsdb"); + $fsdbDumpvars(0, TB); + //$fsdbDumpMDA(); + end + + reg clk; + reg rstn; + initial begin + #0; + rstn = 1'b0; + clk = 1'b0; + #10; + rstn = 1'b1; + end + + always #0.5 clk = ~clk; + + reg [31:0] cnt; + always@(posedge clk or negedge rstn) + if(!rstn) + cnt <= 32'd0; + else + cnt <= cnt + 32'd1; + + initial begin + wait(cnt[31]==1'b1) + $finish(0); + end + + + + wire miso; // Spi Miso + wire miso_oen; // Spi Miso output enable + + + spi_if dut_if(clk,rstn); + + /*spi_slave dut( + .clk (clk ) + ,.rstn (rstn ) + ,.sclk (dut_if.sclk ) + ,.csn (dut_if.csn ) + ,.mosi (dut_if.mosi ) + ,.miso (miso ) + ,.miso_oen (miso_oen ) + ,.error_check (dut_if.error_check ) + );//*/ + + + spi_to_sram dut( + .clk (clk ) + ,.spi_rstn (rstn ) + ,.sclk (dut_if.sclk ) + ,.csn (dut_if.csn ) + ,.mosi (dut_if.mosi ) + ,.miso (miso ) + ,.miso_oen (miso_oen ) + ,.error_check (dut_if.error_check ) + ,.addr (mst.addr ) + ,.wren (mst.wren ) + ,.wrdata (mst.din ) + ,.rden (mst.rden ) + ,.rddata (mst.dout ) + );//*/ + + +reg [4:0] scnt; + always@(posedge dut_if.sclk or posedge dut_if.csn) + if(dut_if.csn) + scnt <= 5'd0; + else if(dut_if.csn==1'b0) + scnt <= scnt + 5'd1; + + + +sram_if#(25,32) mst(clk); +sram_if#(25,32) slv[31:0](clk); + generate + genvar i; + for(i=3;i<31;i++) + begin: sram + spram_model #( + .width(32), + .depth(1048576) + ) sram_block( + .clka (clk ) + ,.ena (slv[i].wren ) + ,.dina (slv[i].din ) + ,.addra (slv[i].addr[19:0] ) + + ,.clkb (clk ) + ,.enb (slv[i].rden ) + ,.doutb (slv[i].dout ) + ,.addrb (slv[i].addr[19:0] ) + ); + end + endgenerate//*/ + +//*****************************reg_files inst*************************************** +//**********************************SYS********************************** + +sysreg_if sys_if(clk,rstn); + +system_regfile system_reg_inst( + .clk (clk ) + ,.rst_n (rstn ) + ,.wrdata (slv[0].din ) + ,.wren (slv[0].wren ) + ,.rwaddr (slv[0].addr[15:0] ) + ,.rden (slv[0].rden ) + ,.rddata (slv[0].dout ) + ,.pll_lock (sys_if.pll_lock ) + ,.pll_lost_lock (sys_if.pll_lost_lock ) + ,.ch0_dbg_upd (sys_if.ch0_dbg_upd ) + ,.ch0_dbg_fifo_e (sys_if.ch0_dbg_fifo_e ) + ,.ch0_dbg_fifo_f (sys_if.ch0_dbg_fifo_f ) + ,.ch0_ldst_addr_unalgn (sys_if.ch0_ldst_addr_unalgn ) + ,.ch0_dec_err (sys_if.ch0_dec_err ) + ,.ch0_exit_irq (sys_if.ch0_exit_irq ) + ,.ch1_dbg_upd (sys_if.ch1_dbg_upd ) + ,.ch1_dbg_fifo_e (sys_if.ch1_dbg_fifo_e ) + ,.ch1_dbg_fifo_f (sys_if.ch1_dbg_fifo_f ) + ,.ch1_ldst_addr_unalgn (sys_if.ch1_ldst_addr_unalgn ) + ,.ch1_dec_err (sys_if.ch1_dec_err ) + ,.ch1_exit_irq (sys_if.ch1_exit_irq ) + ,.ch2_dbg_upd (sys_if.ch2_dbg_upd ) + ,.ch2_dbg_fifo_e (sys_if.ch2_dbg_fifo_e ) + ,.ch2_dbg_fifo_f (sys_if.ch2_dbg_fifo_f ) + ,.ch2_ldst_addr_unalgn (sys_if.ch2_ldst_addr_unalgn ) + ,.ch2_dec_err (sys_if.ch2_dec_err ) + ,.ch2_exit_irq (sys_if.ch2_exit_irq ) + ,.ch3_dbg_upd (sys_if.ch3_dbg_upd ) + ,.ch3_dbg_fifo_e (sys_if.ch3_dbg_fifo_e ) + ,.ch3_dbg_fifo_f (sys_if.ch3_dbg_fifo_f ) + ,.ch3_ldst_addr_unalgn (sys_if.ch3_ldst_addr_unalgn ) + ,.ch3_dec_err (sys_if.ch3_dec_err ) + ,.ch3_exit_irq (sys_if.ch3_exit_irq ) + ,.sys_soft_rstn (sys_if.soft_rstn[0] ) + ,.mcu_soft_rstn (sys_if.soft_rstn[1] ) + ,.awg_soft_rstn (sys_if.soft_rstn[2] ) + ,.dac_soft_rstn (sys_if.soft_rstn[3] ) + ,.irq (sys_if.irq ) +); + + + +reg cr; +always@(negedge clk or negedge rstn) begin + if(!rstn) cr <= 1'b0; + else if(cnt=='h3dcd1) + cr <= 1; + else if(cr) + cr <= 0; +end +//assign sys_if.pll_lock = cr; +//assign sys_if.pll_lock = system_reg_inst.icr; +//**********************************MCU********************************** +//MCU and SPI interface for interaction +mcureg_if mcu_if(clk,rstn); + +wire[31:0] mp[3:0]; +reg[31:0] mr; +always@(negedge clk or negedge rstn) begin + if(!rstn) mr <= 32'b0; + else if(cnt=='h124bd) + mr <= 32'hffff_ffff; + else if(mr) + mr <= 0; +end +//assign mcu_if.mcu_param = {32'b0,mr,32'b0,32'b0};//*/ + +mcu_regfile mcu_reg_inst( + .clk (clk ) + ,.rst_n (rstn ) + ,.wrdata (slv[1].din ) + ,.wren (slv[1].wren ) + ,.wrmask (mcu_if.wrmask ) + ,.rwaddr (slv[1].addr[15:0] ) + ,.rden (slv[1].rden ) + ,.rddata (slv[1].dout ) + ,.fb_st_info (mcu_if.fb_st_info ) + ,.run_time (mcu_if.run_time ) + ,.instr_num (mcu_if.instr_num ) + ,.mcu_param (mcu_if.mcu_param ) + ,.mcu_result (mcu_if.mcu_result ) + ,.mcu_cwfr (mcu_if.mcu_cwfr ) + ,.mcu_gapr (mcu_if.mcu_gapr ) + ,.mcu_ampr (mcu_if.mcu_ampr ) + ,.mcu_baisr (mcu_if.mcu_baisr ) + ,.mcu_intp_sel (mcu_if.mcu_intp_sel ) + ,.mcu_nco_pha_clr (mcu_if.mcu_nco_pha_clr ) + ,.mcu_rz_pha (mcu_if.mcu_rz_pha ) +);//*/ + + +//**********************************AWG********************************** +awgreg_if awg_if(clk,rstn); + +wire[31:0] ap; +reg[31:0] ar; +always@(negedge clk or negedge rstn) begin + if(!rstn) ar <= 32'b0; + else if(cnt=='h456f) + ar <= 32'hffff_ffff; + else if(ar) + ar <= 0; +end +//assign awg_if.mcu_result2 = ar; + + +awg_regfile awg_reg_inst( + .clk (clk ) + ,.rst_n (rstn ) + ,.wrdata (slv[2].din ) + ,.wren (slv[2].wren ) + ,.rwaddr (slv[2].addr[15:0] ) + ,.rden (slv[2].rden ) + ,.rddata (slv[2].dout ) + ,.fb_st_i (awg_if.fb_st_i ) + ,.run_time (awg_if.run_time ) + ,.instr_num (awg_if.instr_num ) + + ,.mcu_param0 (awg_if.mcu_param0 ) + ,.mcu_param1 (awg_if.mcu_param1 ) + ,.mcu_param2 (awg_if.mcu_param2 ) + ,.mcu_param3 (awg_if.mcu_param3 ) + ,.mcu_result0 (awg_if.mcu_result0 ) + ,.mcu_result1 (awg_if.mcu_result1 ) + ,.mcu_result2 (awg_if.mcu_result2 ) + ,.mcu_result3 (awg_if.mcu_result3 ) + ,.fb_st_o (awg_if.fb_st_o ) + ,.mod_sel_sideband (awg_if.mod_sel_sideband ) + ,.qam_nco_clr (awg_if.qam_nco_clr ) + ,.qam_fcw (awg_if.qam_fcw ) + ,.qam_pha (awg_if.qam_pha ) + ,.qam_mod (awg_if.qam_mod ) + ,.qam_sel_sideband (awg_if.qam_sel_sideband ) + ,.intp_mode (awg_if.intp_mode ) + ,.intp_sel (awg_if.intp_sel ) + ,.dac_mode_sel (awg_if.dac_mode_sel ) + ,.tc_bypass (awg_if.tc_bypass ) + ,.tcparr0 (awg_if.tcparr0 ) + ,.tcparr1 (awg_if.tcparr1 ) + ,.tcparr2 (awg_if.tcparr2 ) + ,.tcparr3 (awg_if.tcparr3 ) + ,.tcparr4 (awg_if.tcparr4 ) + ,.tcparr5 (awg_if.tcparr5 ) + ,.tcpbrr0 (awg_if.tcpbrr0 ) + ,.tcpbrr1 (awg_if.tcpbrr1 ) + ,.tcpbrr2 (awg_if.tcpbrr2 ) + ,.tcpbrr3 (awg_if.tcpbrr3 ) + ,.tcpbrr4 (awg_if.tcpbrr4 ) + ,.tcpbrr5 (awg_if.tcpbrr5 ) + ,.tcpair0 (awg_if.tcpair0 ) + ,.tcpair1 (awg_if.tcpair1 ) + ,.tcpair2 (awg_if.tcpair2 ) + ,.tcpair3 (awg_if.tcpair3 ) + ,.tcpair4 (awg_if.tcpair4 ) + ,.tcpair5 (awg_if.tcpair5 ) + ,.tcpbir0 (awg_if.tcpbir0 ) + ,.tcpbir1 (awg_if.tcpbir1 ) + ,.tcpbir2 (awg_if.tcpbir2 ) + ,.tcpbir3 (awg_if.tcpbir3 ) + ,.tcpbir4 (awg_if.tcpbir4 ) + ,.tcpbir5 (awg_if.tcpbir5 ) + ); + + + + spi_bus_decoder#(32,1,1) spi_bus_decode_inst( + .clk (clk ) + ,.rst_n (rstn ) + ,.mst (mst.slave ) + ,.slv (slv.master ) + ); + + assign dut_if.miso = (miso_oen) ? 1'bz : miso; + + + + //case3 test(dut_if,sys_if,mst); + //case4 test(dut_if,mcu_if,mst); + //case5 test(dut_if,awg_if,mst); + case6 test(dut_if,sys_if,mcu_if,awg_if,mst); + + + +endmodule + + + + +