298 lines
11 KiB
Systemverilog
298 lines
11 KiB
Systemverilog
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module TB();
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initial begin
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$fsdbDumpfile("TB1.fsdb");
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$fsdbDumpvars(0, TB);
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//$fsdbDumpMDA();
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end
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reg clk;
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reg rstn;
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initial begin
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#0;
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rstn = 1'b0;
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clk = 1'b0;
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#10;
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rstn = 1'b1;
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end
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always #0.5 clk = ~clk;
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reg [31:0] cnt;
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always@(posedge clk or negedge rstn)
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if(!rstn)
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cnt <= 32'd0;
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else
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cnt <= cnt + 32'd1;
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initial begin
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wait(cnt[31]==1'b1)
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$finish(0);
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end
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wire miso; // Spi Miso
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wire miso_oen; // Spi Miso output enable
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spi_if dut_if(clk,rstn);
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/*spi_slave dut(
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.clk (clk )
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,.rstn (rstn )
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,.sclk (dut_if.sclk )
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,.csn (dut_if.csn )
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,.mosi (dut_if.mosi )
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,.miso (miso )
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,.miso_oen (miso_oen )
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,.error_check (dut_if.error_check )
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);//*/
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spi_to_sram dut(
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.clk (clk )
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,.spi_rstn (rstn )
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,.sclk (dut_if.sclk )
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,.csn (dut_if.csn )
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,.mosi (dut_if.mosi )
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,.miso (miso )
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,.miso_oen (miso_oen )
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,.error_check (dut_if.error_check )
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,.addr (mst.addr )
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,.wren (mst.wren )
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,.wrdata (mst.din )
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,.rden (mst.rden )
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,.rddata (mst.dout )
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);//*/
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reg [4:0] scnt;
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always@(posedge dut_if.sclk or posedge dut_if.csn)
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if(dut_if.csn)
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scnt <= 5'd0;
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else if(dut_if.csn==1'b0)
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scnt <= scnt + 5'd1;
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sram_if#(25,32) mst(clk);
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sram_if#(25,32) slv[31:0](clk);
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generate
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genvar i;
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for(i=3;i<31;i++)
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begin: sram
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spram_model #(
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.width(32),
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.depth(1048576)
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) sram_block(
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.clka (clk )
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,.ena (slv[i].wren )
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,.dina (slv[i].din )
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,.addra (slv[i].addr[19:0] )
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,.clkb (clk )
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,.enb (slv[i].rden )
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,.doutb (slv[i].dout )
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,.addrb (slv[i].addr[19:0] )
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);
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end
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endgenerate//*/
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//*****************************reg_files inst***************************************
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//**********************************SYS**********************************
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sysreg_if sys_if(clk,rstn);
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system_regfile system_reg_inst(
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.clk (clk )
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,.rst_n (rstn )
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,.wrdata (slv[0].din )
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,.wren (slv[0].wren )
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,.rwaddr (slv[0].addr[15:0] )
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,.rden (slv[0].rden )
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,.rddata (slv[0].dout )
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,.pll_lock (sys_if.pll_lock )
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,.pll_lost_lock (sys_if.pll_lost_lock )
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,.ch0_dbg_upd (sys_if.ch0_dbg_upd )
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,.ch0_dbg_fifo_e (sys_if.ch0_dbg_fifo_e )
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,.ch0_dbg_fifo_f (sys_if.ch0_dbg_fifo_f )
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,.ch0_ldst_addr_unalgn (sys_if.ch0_ldst_addr_unalgn )
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,.ch0_dec_err (sys_if.ch0_dec_err )
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,.ch0_exit_irq (sys_if.ch0_exit_irq )
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,.ch1_dbg_upd (sys_if.ch1_dbg_upd )
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,.ch1_dbg_fifo_e (sys_if.ch1_dbg_fifo_e )
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,.ch1_dbg_fifo_f (sys_if.ch1_dbg_fifo_f )
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,.ch1_ldst_addr_unalgn (sys_if.ch1_ldst_addr_unalgn )
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,.ch1_dec_err (sys_if.ch1_dec_err )
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,.ch1_exit_irq (sys_if.ch1_exit_irq )
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,.ch2_dbg_upd (sys_if.ch2_dbg_upd )
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,.ch2_dbg_fifo_e (sys_if.ch2_dbg_fifo_e )
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,.ch2_dbg_fifo_f (sys_if.ch2_dbg_fifo_f )
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,.ch2_ldst_addr_unalgn (sys_if.ch2_ldst_addr_unalgn )
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,.ch2_dec_err (sys_if.ch2_dec_err )
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,.ch2_exit_irq (sys_if.ch2_exit_irq )
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,.ch3_dbg_upd (sys_if.ch3_dbg_upd )
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,.ch3_dbg_fifo_e (sys_if.ch3_dbg_fifo_e )
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,.ch3_dbg_fifo_f (sys_if.ch3_dbg_fifo_f )
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,.ch3_ldst_addr_unalgn (sys_if.ch3_ldst_addr_unalgn )
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,.ch3_dec_err (sys_if.ch3_dec_err )
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,.ch3_exit_irq (sys_if.ch3_exit_irq )
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,.sys_soft_rstn (sys_if.soft_rstn[0] )
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,.mcu_soft_rstn (sys_if.soft_rstn[1] )
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,.awg_soft_rstn (sys_if.soft_rstn[2] )
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,.dac_soft_rstn (sys_if.soft_rstn[3] )
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,.irq (sys_if.irq )
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);
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reg cr;
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always@(negedge clk or negedge rstn) begin
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if(!rstn) cr <= 1'b0;
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else if(cnt=='h3dcd1)
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cr <= 1;
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else if(cr)
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cr <= 0;
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end
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//assign sys_if.pll_lock = cr;
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//assign sys_if.pll_lock = system_reg_inst.icr;
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//**********************************MCU**********************************
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//MCU and SPI interface for interaction
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mcureg_if mcu_if(clk,rstn);
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wire[31:0] mp[3:0];
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reg[31:0] mr;
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always@(negedge clk or negedge rstn) begin
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if(!rstn) mr <= 32'b0;
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else if(cnt=='h124bd)
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mr <= 32'hffff_ffff;
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else if(mr)
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mr <= 0;
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end
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//assign mcu_if.mcu_param = {32'b0,mr,32'b0,32'b0};//*/
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mcu_regfile mcu_reg_inst(
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.clk (clk )
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,.rst_n (rstn )
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,.wrdata (slv[1].din )
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,.wren (slv[1].wren )
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,.wrmask (mcu_if.wrmask )
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,.rwaddr (slv[1].addr[15:0] )
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,.rden (slv[1].rden )
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,.rddata (slv[1].dout )
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,.fb_st_info (mcu_if.fb_st_info )
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,.run_time (mcu_if.run_time )
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,.instr_num (mcu_if.instr_num )
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,.mcu_param (mcu_if.mcu_param )
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,.mcu_result (mcu_if.mcu_result )
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,.mcu_cwfr (mcu_if.mcu_cwfr )
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,.mcu_gapr (mcu_if.mcu_gapr )
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,.mcu_ampr (mcu_if.mcu_ampr )
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,.mcu_baisr (mcu_if.mcu_baisr )
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,.mcu_intp_sel (mcu_if.mcu_intp_sel )
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,.mcu_nco_pha_clr (mcu_if.mcu_nco_pha_clr )
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,.mcu_rz_pha (mcu_if.mcu_rz_pha )
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);//*/
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//**********************************AWG**********************************
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awgreg_if awg_if(clk,rstn);
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wire[31:0] ap;
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reg[31:0] ar;
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always@(negedge clk or negedge rstn) begin
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if(!rstn) ar <= 32'b0;
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else if(cnt=='h456f)
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ar <= 32'hffff_ffff;
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else if(ar)
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ar <= 0;
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end
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//assign awg_if.mcu_result2 = ar;
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awg_regfile awg_reg_inst(
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.clk (clk )
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,.rst_n (rstn )
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,.wrdata (slv[2].din )
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,.wren (slv[2].wren )
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,.rwaddr (slv[2].addr[15:0] )
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,.rden (slv[2].rden )
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,.rddata (slv[2].dout )
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,.fb_st_i (awg_if.fb_st_i )
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,.run_time (awg_if.run_time )
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,.instr_num (awg_if.instr_num )
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,.mcu_param0 (awg_if.mcu_param0 )
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,.mcu_param1 (awg_if.mcu_param1 )
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,.mcu_param2 (awg_if.mcu_param2 )
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,.mcu_param3 (awg_if.mcu_param3 )
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,.mcu_result0 (awg_if.mcu_result0 )
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,.mcu_result1 (awg_if.mcu_result1 )
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,.mcu_result2 (awg_if.mcu_result2 )
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,.mcu_result3 (awg_if.mcu_result3 )
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,.fb_st_o (awg_if.fb_st_o )
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,.mod_sel_sideband (awg_if.mod_sel_sideband )
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,.qam_nco_clr (awg_if.qam_nco_clr )
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,.qam_fcw (awg_if.qam_fcw )
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,.qam_pha (awg_if.qam_pha )
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,.qam_mod (awg_if.qam_mod )
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,.qam_sel_sideband (awg_if.qam_sel_sideband )
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,.intp_mode (awg_if.intp_mode )
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,.intp_sel (awg_if.intp_sel )
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,.dac_mode_sel (awg_if.dac_mode_sel )
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,.tc_bypass (awg_if.tc_bypass )
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,.tcparr0 (awg_if.tcparr0 )
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,.tcparr1 (awg_if.tcparr1 )
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,.tcparr2 (awg_if.tcparr2 )
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,.tcparr3 (awg_if.tcparr3 )
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,.tcparr4 (awg_if.tcparr4 )
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,.tcparr5 (awg_if.tcparr5 )
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,.tcpbrr0 (awg_if.tcpbrr0 )
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,.tcpbrr1 (awg_if.tcpbrr1 )
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,.tcpbrr2 (awg_if.tcpbrr2 )
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,.tcpbrr3 (awg_if.tcpbrr3 )
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,.tcpbrr4 (awg_if.tcpbrr4 )
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,.tcpbrr5 (awg_if.tcpbrr5 )
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,.tcpair0 (awg_if.tcpair0 )
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,.tcpair1 (awg_if.tcpair1 )
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,.tcpair2 (awg_if.tcpair2 )
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,.tcpair3 (awg_if.tcpair3 )
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,.tcpair4 (awg_if.tcpair4 )
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,.tcpair5 (awg_if.tcpair5 )
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,.tcpbir0 (awg_if.tcpbir0 )
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,.tcpbir1 (awg_if.tcpbir1 )
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,.tcpbir2 (awg_if.tcpbir2 )
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,.tcpbir3 (awg_if.tcpbir3 )
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,.tcpbir4 (awg_if.tcpbir4 )
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,.tcpbir5 (awg_if.tcpbir5 )
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);
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spi_bus_decoder#(32,1,1) spi_bus_decode_inst(
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.clk (clk )
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,.rst_n (rstn )
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,.mst (mst.slave )
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,.slv (slv.master )
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);
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assign dut_if.miso = (miso_oen) ? 1'bz : miso;
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case3 test(dut_if,sys_if,mst);
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//case4 test(dut_if,sys_if,mcu_if,mst);
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//case5 test(dut_if,sys_if,mcu_if,awg_if,mst);
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endmodule
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