40 lines
882 B
Systemverilog
40 lines
882 B
Systemverilog
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interface sysreg_if(input clk,input rstn);
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logic pll_lock;
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logic pll_lost_lock;
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logic ch0_dbg_upd ;
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logic ch0_dbg_fifo_e;
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logic ch0_dbg_fifo_f;
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logic ch0_ldst_addr_unalgn;
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logic ch0_dec_err;
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logic ch0_exit_irq ;
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logic ch1_dbg_upd ;
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logic ch1_dbg_fifo_e ;
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logic ch1_dbg_fifo_f ;
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logic ch1_ldst_addr_unalgn ;
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logic ch1_dec_err ;
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logic ch1_exit_irq ;
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logic ch2_dbg_upd ;
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logic ch2_dbg_fifo_e ;
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logic ch2_dbg_fifo_f ;
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logic ch2_ldst_addr_unalgn ;
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logic ch2_dec_err ;
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logic ch2_exit_irq ;
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logic ch3_dbg_upd ;
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logic ch3_dbg_fifo_e ;
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logic ch3_dbg_fifo_f ;
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logic ch3_ldst_addr_unalgn ;
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logic ch3_dec_err ;
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logic ch3_exit_irq ;
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logic[3:0] soft_rstn;
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logic irq ;
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endinterface : sysreg_if
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