104 lines
2.0 KiB
Systemverilog
104 lines
2.0 KiB
Systemverilog
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class spi_monitor;
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virtual spi_if wif;
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virtual sram_if xif;
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//collect MOSI(din) & MISO(dout)
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bit din[$];
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bit[31:0] dout[$];
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int pktnum;
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int pkt_i;
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function new();
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endfunction
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extern task write_monitor();
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extern task read_monitor();
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extern task do_mon();
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endclass : spi_monitor
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task spi_monitor::do_mon();
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fork
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while(1) begin
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if(pkt_i==pktnum) break;
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write_monitor();
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end
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while(1) begin
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if(pkt_i==pktnum) break;
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read_monitor();
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end
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repeat(pktnum) begin: kill_progress
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@(negedge wif.csn);
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pkt_i++;
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end
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join
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endtask: do_mon
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//monitor1: write_monitor(mosi)
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task spi_monitor::write_monitor();
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bit write_temp[$];
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@(negedge wif.csn);
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while(1) begin
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//Sample miso data @(posedge sclk) as DUT does.
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@(posedge wif.sclk or posedge wif.csn);
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if(wif.error_check | wif.csn)
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break;
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write_temp.push_back(wif.mosi);
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end
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//Keep the write-cycle data until anothor one occurs
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if(write_temp[0]==1'b0)
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din = write_temp;
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din[0] = write_temp[0];
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write_temp.delete();
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endtask: write_monitor
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//monitor2: read_monitor(miso)
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task spi_monitor::read_monitor();
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bit[31:0] read_temp;
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int size;
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int i=0;
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@(negedge wif.csn);
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for(i=0;i<32;i++) begin
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@(posedge wif.sclk or posedge wif.csn)
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if(wif.error_check | wif.csn)
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break;
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read_temp[i] = wif.mosi;
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end
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size = read_temp[0] ? (read_temp[1] ? 16 : 1) : 0;
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read_temp = 32'b0;
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dout.delete();
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repeat(size) begin
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//One 32bit-word is sampled everytime a for-circulation runs
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for(i=0;i<32;i++) begin
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//Sample miso data @(negedge sclk) for stability.
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@(negedge wif.sclk or posedge wif.csn);
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if(wif.csn)
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break;
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read_temp[31-i] = wif.miso;
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end
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if(!wif.csn) begin
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dout.push_back(read_temp);
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$display("miso:\t\t%b\t\t **",read_temp);
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end
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end
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if(!wif.csn) @(posedge wif.csn);
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endtask: read_monitor
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