SPI_Test/tb/testbench/rtl/tb.v

module TB();

reg		clk;
reg		rstn;
reg 	sclk;
reg 	csn;
reg 	mosi;
wire   error_check;
wire 	miso_oen;
wire 	miso;
/*
initial
begin
     $fsdbDumpfile("TB.fsdb");
     $fsdbDumpvars(0, TB);
end
*/
initial	begin
		#0;
		rstn	=1'b1;
		#3000;
		rstn	=1'b0;
		#3000;
		rstn	=1'b1;
end

initial begin
	#0;
	        csn = 1;
	#6400;
		csn = 0;
        #6400;
		csn = 1;
	#6400;
		csn = 0;
        #12800;
		csn = 1;	
	#6400;
		csn = 0;
        #6400;
		csn = 1;
	#6400;
		csn = 0;
        #12800;
		csn = 1;
	
	#6400;
		csn = 0;
        #8000;
		csn = 1;
	#6400;
		csn = 0;
        #16000;
		csn = 1;
end






reg [623:0] data = 624'h0000_1000_ffff_ffff_4000_4000_aaaa_aaaa_5555_5555_1111_1111_8000_1000_0000_0000_c000_4000_0000_0000_0000_0000_0000_0000_0000_1000_ffff_ffff_ffff_4000_4000_aaaa_aaaa_5555_5555_1111_1111_1111_1111;
				
				
reg [25:0] data_cnt;

always@(posedge sclk or negedge rstn)
		if(!rstn)
			data_cnt <= 26'd623;
		else if (data_cnt > 0 && (~csn))
			data_cnt <=	data_cnt - 1'b1;
		else 
			data_cnt <= data_cnt;



always@(posedge clk or negedge rstn)
		if(!rstn)
			mosi <=	1'b0;
		else
			mosi <=	data[data_cnt];



initial	begin
		#0;
		clk = 1'b1;
		sclk = 1'b1;
end

always #5 clk = ~clk;
always #50 sclk = ~sclk;

reg	[21:0]	cnt;
always@(posedge clk or negedge rstn)
		if(!rstn)
			cnt	<=	22'd0;
		else
			cnt	<=	cnt + 22'd1;

initial	begin
	wait(cnt[16]==1'b1)
			$finish(0);
end



spi_top_4 spi_top_4_inst(
 .clk(clk)
,.rstn(rstn)
,.sclk(sclk)
,.csn(csn)
,.mosi(mosi)
,.miso(miso)
,.miso_oen(miso_oen)
,.error_check(error_check)


);

endmodule