663 lines
26 KiB
Coq
663 lines
26 KiB
Coq
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//+FHDR--------------------------------------------------------------------------------------------------------
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// Company:
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//-----------------------------------------------------------------------------------------------------------------
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// File Name : ssytem_regfile.v
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// Department :
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// Author : PWY
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// Author's Tel :
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//-----------------------------------------------------------------------------------------------------------------
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// Relese History
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// Version Date Author Description
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// 1.0 2022-08-25 PWY
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//-----------------------------------------------------------------------------------------------------------------
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// Keywords :
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Parameter
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Purpose :
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Target Device:
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// Tool versions:
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//-----------------------------------------------------------------------------------------------------------------
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// Reuse Issues
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// Reset Strategy:
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// Clock Domains:
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// Critical Timing:
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// Asynchronous I/F:
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// Synthesizable (y/n):
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// Other:
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//-FHDR--------------------------------------------------------------------------------------------------------
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// -----------------------------------------------------------
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// -- Register address offset macros
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// -----------------------------------------------------------
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//Identity Register
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`define IDR 16'h00
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//Vendor Code Register
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`define VIDR 16'h04
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//RTL Freeze Date Register
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`define DATER 16'h08
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//Version Register
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`define VERR 16'h0C
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//Wirte And Read Test Register
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`define TESTR 16'h10
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//Interrupt Mask Register
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//[31 ] --> PLL LOCK Interrupt Mask
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//[30 ] --> PLL Lost LOCK Interrupt Mask
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//[29 ] --> CH3 DBG UPD Interrupt Mask
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//[28 ] --> CH3 DBG FIFO Empty Interrupt Mask
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//[27 ] --> CH3 DBG FIFO Full Interrupt Mask
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//[26 ] --> CH3 LDST ADDR UNALGN Interrupt Mask
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//[25 ] --> CH3 DEC ERR Interrupt Mask
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//[24 ] --> CH3 EXITI Interrupt Mask
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//[23:22] --> Reserved
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//[21 ] --> CH2 DBG UPD Interrupt Mask
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//[20 ] --> CH2 DBG FIFO Empty Interrupt Mask
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//[19 ] --> CH2 DBG FIFO Full Interrupt Mask
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//[18 ] --> CH2 LDST ADDR UNALGN Interrupt Mask
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//[17 ] --> CH2 DEC ERR Interrupt Mask
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//[16 ] --> CH2 EXITI Interrupt Mask
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//[15:14] --> Reserved
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//[13 ] --> CH1 DBG UPD Interrupt Mask
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//[12 ] --> CH1 DBG FIFO Empty Interrupt Mask
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//[11 ] --> CH1 DBG FIFO Full Interrupt Mask
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//[10 ] --> CH1 LDST ADDR UNALGN Interrupt Mask
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//[9 ] --> CH1 DEC ERR Interrupt Mask
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//[8 ] --> CH1 EXITI Interrupt Mask
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//[7 :6] --> Reserved
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//[5 ] --> CH1 DBG UPD Interrupt Mask
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//[4 ] --> CH1 DBG FIFO Empty Interrupt Mask
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//[3 ] --> CH1 DBG FIFO Full Interrupt Mask
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//[2 ] --> CH1 LDST ADDR UNALGN Interrupt Mask
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//[1 ] --> CH1 DEC ERR Interrupt Mask
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//[0 ] --> CH1 EXITI Interrupt Mask
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`define IMR 16'h14
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//Interrupt Status Register
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//[31 ] --> PLL LOCK Interrupt Status
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//[30 ] --> PLL Lost LOCK Interrupt Status
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//[29 ] --> CH3 DBG UPD Interrupt Status
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//[28 ] --> CH3 DBG FIFO Empty Interrupt Status
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//[27 ] --> CH3 DBG FIFO Full Interrupt Status
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//[26 ] --> CH3 LDST ADDR UNALGN Interrupt Status
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//[25 ] --> CH3 DEC ERR Interrupt Status
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//[24 ] --> CH3 EXITI Interrupt Status
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//[23:22] --> Reserved
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//[21 ] --> CH2 DBG UPD Interrupt Status
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//[20 ] --> CH2 DBG FIFO Empty Interrupt Status
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//[19 ] --> CH2 DBG FIFO Full Interrupt Status
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//[18 ] --> CH2 LDST ADDR UNALGN Interrupt Status
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//[17 ] --> CH2 DEC ERR Interrupt Status
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//[16 ] --> CH2 EXITI Interrupt Status
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//[15:14] --> Reserved
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//[13 ] --> CH1 DBG UPD Interrupt Status
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//[12 ] --> CH1 DBG FIFO Empty Interrupt Status
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//[11 ] --> CH1 DBG FIFO Full Interrupt Status
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//[10 ] --> CH1 LDST ADDR UNALGN Interrupt Status
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//[9 ] --> CH1 DEC ERR Interrupt Status
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//[8 ] --> CH1 EXITI Interrupt Status
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//[7 :6] --> Reserved
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//[5 ] --> CH1 DBG UPD Interrupt Status
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//[4 ] --> CH1 DBG FIFO Empty Interrupt Status
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//[3 ] --> CH1 DBG FIFO Full Interrupt Status
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//[2 ] --> CH1 LDST ADDR UNALGN Interrupt Status
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//[1 ] --> CH1 DEC ERR Interrupt Status
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//[0 ] --> CH1 EXITI Interrupt Status
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`define ISR 16'h18
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//Post Masking Interrupt Status Register
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//Interrupt Status Register
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//[31 ] --> PLL LOCK Masking Interrupt Status
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//[30 ] --> PLL Lost LOCK Masking Interrupt Status
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//[29 ] --> CH3 DBG UPD IMasking Interrupt Status
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//[28 ] --> CH3 DBG FIFO Empty Masking Interrupt Status
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//[27 ] --> CH3 DBG FIFO Full Masking Interrupt Status
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//[26 ] --> CH3 LDST ADDR UNALGN Masking Interrupt Status
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//[25 ] --> CH3 DEC ERR Masking Interrupt Status
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//[24 ] --> CH3 EXITI Masking Interrupt Status
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//[23:22] --> Reserved
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//[21 ] --> CH2 DBG UPD Masking Interrupt Status
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//[20 ] --> CH2 DBG FIFO Empty Masking Interrupt Status
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//[19 ] --> CH2 DBG FIFO Full Masking Interrupt Status
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//[18 ] --> CH2 LDST ADDR UNALGN Masking Interrupt Status
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//[17 ] --> CH2 DEC ERR Masking Interrupt Status
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//[16 ] --> CH2 EXITI Masking Interrupt Status
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//[15:14] --> Reserved
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//[13 ] --> CH1 DBG UPD Masking Interrupt Status
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//[12 ] --> CH1 DBG FIFO Empty Masking Interrupt Status
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//[11 ] --> CH1 DBG FIFO Full Masking Interrupt Status
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//[10 ] --> CH1 LDST ADDR UNALGN Masking Interrupt Status
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//[9 ] --> CH1 DEC ERR Masking Interrupt Status
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//[8 ] --> CH1 EXITI Masking Interrupt Status
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//[7 :6] --> Reserved
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//[5 ] --> CH1 DBG UPD Masking Interrupt Status
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//[4 ] --> CH1 DBG FIFO Empty Masking Interrupt Status
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//[3 ] --> CH1 DBG FIFO Full Masking Interrupt Status
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//[2 ] --> CH1 LDST ADDR UNALGN Masking Interrupt Status
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//[1 ] --> CH1 DEC ERR Masking Interrupt Status
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//[0 ] --> CH1 EXITI Masking Interrupt Status
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`define MISR 16'h1C
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//Soft Reset Time Register
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`define SFRTR 16'h20
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//Soft Reset Register
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`define SFRR 16'h24
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//MCU Soft Reset Register
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`define MCURSTR 16'h28
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//AWG Soft Reset Register
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`define AWGRSTR 16'h2C
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//DAC Soft Reset Register
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`define DACRSTR 16'h30///////////////////////
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module system_regfile (
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//system port
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input clk // System Main Clock
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,input rst_n // Spi Reset active low
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//rw op port
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,input [31 :0] wrdata // write data
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,input wren // write enable
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,input [15 :0] rwaddr // read & write address
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,input rden // read enable
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,output [31 :0] rddata // read data
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//pll status port
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,input pll_lock
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,input pll_lost_lock
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//ch0 status Port
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,input ch0_dbg_upd
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,input ch0_dbg_fifo_e
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,input ch0_dbg_fifo_f
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,input ch0_ldst_addr_unalgn
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,input ch0_dec_err
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,input ch0_exit_irq
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//ch1 status Port
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,input ch1_dbg_upd
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,input ch1_dbg_fifo_e
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,input ch1_dbg_fifo_f
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,input ch1_ldst_addr_unalgn
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,input ch1_dec_err
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,input ch1_exit_irq
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//ch2 status Port
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,input ch2_dbg_upd
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,input ch2_dbg_fifo_e
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,input ch2_dbg_fifo_f
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,input ch2_ldst_addr_unalgn
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,input ch2_dec_err
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,input ch2_exit_irq
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//ch3 status Port
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,input ch3_dbg_upd
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,input ch3_dbg_fifo_e
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,input ch3_dbg_fifo_f
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,input ch3_ldst_addr_unalgn
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,input ch3_dec_err
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,input ch3_exit_irq
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//Soft Reset out
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,output sys_soft_rstn
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,output mcu_soft_rstn
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,output awg_soft_rstn
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,output dac_soft_rstn
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//Interrupt output port
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,output irq
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);
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localparam L = 1'b0,
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H = 1'b1;
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localparam IDRD = 32'h41574743;
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localparam VIDRD = 32'h55535443;
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localparam DATERD = 32'h20220831;
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localparam VERSION = 32'h00000001;
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localparam TESTRD = 32'h01234567;
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// ------------------------------------------------------
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// -- Register enable (select) wires
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// ------------------------------------------------------
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wire idren; // idr select
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wire vidren; // vidr select
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wire dateren; // dater select
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wire verren; // dater select
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wire testren; // testr select
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wire imren; // imr select
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wire isren; // isr select
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wire misren; // imsr select
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wire sfrtren; // sfrtr select
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wire sfrren; // sfrr select
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wire mcurstren; // mcurstr select
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wire awgrstren; // awgrstr select
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wire adacrstren; // adacrstr select
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// ------------------------------------------------------
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// -- Register write enable wires
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// ------------------------------------------------------
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wire testrwe; // testr write enable
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wire imrwe; // imr write enable
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wire misrwe; // imsr write enable
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wire sfrtrwe; // sfrtr write enable
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wire sfrrwe; // sfrr write enable
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wire mcurstrwe; // mcurstr write enable
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wire awgrstrwe; // awgrstr write enable
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wire adacrstrwe; // adacrstr write enable
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// ------------------------------------------------------
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// -- Misc wires
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// ------------------------------------------------------
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wire [31 :0] irisr ; // original interrupt status wire
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wire icr ; // interrupt status clear wire
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// ------------------------------------------------------
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// -- Misc Registers
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// ------------------------------------------------------
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reg [31 :0] testr ;
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reg [31 :0] imr ;
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reg [31 :0] isr ;
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reg [31 :0] misr ;
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reg [31 :0] sfrtr ;
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reg [0 :0] sfrr ;
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reg [0 :0] mcurstr ;
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reg [0 :0] awgrstr ;
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reg [0 :0] adacrstr ;
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reg [31 :0] rddata_reg ;
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reg pll_lock_r ;
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reg pll_lost_lock_r ;
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//ch0 status reg
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reg ch0_dbg_upd_r ;
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reg ch0_dbg_fifo_e_r ;
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reg ch0_dbg_fifo_f_r ;
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reg ch0_ldst_addr_unalgn_r ;
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reg ch0_dec_err_r ;
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reg ch0_exit_irq_r ;
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//ch1 status reg
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reg ch1_dbg_upd_r ;
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reg ch1_dbg_fifo_e_r ;
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reg ch1_dbg_fifo_f_r ;
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reg ch1_ldst_addr_unalgn_r ;
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reg ch1_dec_err_r ;
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reg ch1_exit_irq_r ;
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//ch2 status reg
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reg ch2_dbg_upd_r ;
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reg ch2_dbg_fifo_e_r ;
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reg ch2_dbg_fifo_f_r ;
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reg ch2_ldst_addr_unalgn_r ;
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reg ch2_dec_err_r ;
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reg ch2_exit_irq_r ;
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//ch3 status reg
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reg ch3_dbg_upd_r ;
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reg ch3_dbg_fifo_e_r ;
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reg ch3_dbg_fifo_f_r ;
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reg ch3_ldst_addr_unalgn_r ;
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reg ch3_dec_err_r ;
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reg ch3_exit_irq_r ;
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reg sys_soft_rstn_r ;
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reg mcu_soft_rstn_r ;
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reg awg_soft_rstn_r ;
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reg dac_soft_rstn_r ;
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// ------------------------------------------------------
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// -- Address decoder
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//
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// Decodes the register address offset input(reg_addr)
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// to produce enable (select) signals for each of the
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// SW-registers in the macrocell. The reg_addr input
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// is bits [8:0] of the paddr bus.
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// ------------------------------------------------------
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assign idren = (rwaddr[15:2] == `IDR >> 2) ? 1'b1 : 1'b0;
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assign vidren = (rwaddr[15:2] == `VIDR >> 2) ? 1'b1 : 1'b0;
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assign dateren = (rwaddr[15:2] == `DATER >> 2) ? 1'b1 : 1'b0;
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assign testren = (rwaddr[15:2] == `TESTR >> 2) ? 1'b1 : 1'b0;
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assign imren = (rwaddr[15:2] == `IMR >> 2) ? 1'b1 : 1'b0;
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assign isren = (rwaddr[15:2] == `ISR >> 2) ? 1'b1 : 1'b0;
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assign misren = (rwaddr[15:2] == `MISR >> 2) ? 1'b1 : 1'b0;
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assign sfrtren = (rwaddr[15:2] == `SFRTR >> 2) ? 1'b1 : 1'b0;
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assign sfrren = (rwaddr[15:2] == `SFRR >> 2) ? 1'b1 : 1'b0;
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assign mcurstren = (rwaddr[15:2] == `MCURSTR >> 2) ? 1'b1 : 1'b0;
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assign awgrstren = (rwaddr[15:2] == `AWGRSTR >> 2) ? 1'b1 : 1'b0;
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assign adacrstren = (rwaddr[15:2] == `DACRSTR >> 2) ? 1'b1 : 1'b0;
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// ------------------------------------------------------
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// -- Write enable signals
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//
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// Write enable signals for writable SW-registers.
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// The write enable for each register is the ANDed
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// result of the register enable and the input reg_wren
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// ------------------------------------------------------
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assign testrwe = testren & wren;
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assign imrwe = imren & wren;
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assign sfrtrwe = sfrtren & wren;
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assign sfrrwe = sfrren & wren;
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assign mcurstrwe = mcurstren & wren;
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assign awgrstrwe = awgrstren & wren;
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assign adacrstrwe = adacrstren & wren;
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// ---------------------------------------------------------------------------------------------------
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// -- interrupt Mask Register
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//
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// Write interrupt Mask for 'imr' : 12-bit register
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||
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// Register is split into the following bit fields
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//
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||
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//[31 ] --> PLL LOCK Interrupt Mask
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//[30 ] --> PLL Lost LOCK Interrupt Mask
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//[29 ] --> CH3 DBG UPD Interrupt Mask
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||
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//[28 ] --> CH3 DBG FIFO Empty Interrupt Mask
|
||
|
|
//[27 ] --> CH3 DBG FIFO Full Interrupt Mask
|
||
|
|
//[26 ] --> CH3 LDST ADDR UNALGN Interrupt Mask
|
||
|
|
//[25 ] --> CH3 DEC ERR Interrupt Mask
|
||
|
|
//[24 ] --> CH3 EXITI Interrupt Mask
|
||
|
|
//[23:22] --> Reserved
|
||
|
|
//[21 ] --> CH2 DBG UPD Interrupt Mask
|
||
|
|
//[20 ] --> CH2 DBG FIFO Empty Interrupt Mask
|
||
|
|
//[19 ] --> CH2 DBG FIFO Full Interrupt Mask
|
||
|
|
//[18 ] --> CH2 LDST ADDR UNALGN Interrupt Mask
|
||
|
|
//[17 ] --> CH2 DEC ERR Interrupt Mask
|
||
|
|
//[16 ] --> CH2 EXITI Interrupt Mask
|
||
|
|
//[15:14] --> Reserved
|
||
|
|
//[13 ] --> CH1 DBG UPD Interrupt Mask
|
||
|
|
//[12 ] --> CH1 DBG FIFO Empty Interrupt Mask
|
||
|
|
//[11 ] --> CH1 DBG FIFO Full Interrupt Mask
|
||
|
|
//[10 ] --> CH1 LDST ADDR UNALGN Interrupt Mask
|
||
|
|
//[9 ] --> CH1 DEC ERR Interrupt Mask
|
||
|
|
//[8 ] --> CH1 EXITI Interrupt Mask
|
||
|
|
//[7 :6] --> Reserved
|
||
|
|
//[5 ] --> CH1 DBG UPD Interrupt Mask
|
||
|
|
//[4 ] --> CH1 DBG FIFO Empty Interrupt Mask
|
||
|
|
//[3 ] --> CH1 DBG FIFO Full Interrupt Mask
|
||
|
|
//[2 ] --> CH1 LDST ADDR UNALGN Interrupt Mask
|
||
|
|
//[1 ] --> CH1 DEC ERR Interrupt Mask
|
||
|
|
//[0 ] --> CH1 EXITI Interrupt Mask
|
||
|
|
// ---------------------------------------------------------------------------------------------------
|
||
|
|
sirv_gnrl_dfflr #(32) imr_dfflr (imrwe, wrdata[31:0], imr, clk, rst_n);
|
||
|
|
|
||
|
|
// ------------------------------------------------------
|
||
|
|
// -- testr Register
|
||
|
|
//
|
||
|
|
// Write testr for 'TESTR' : 32-bit register
|
||
|
|
// Register is split into the following bit fields
|
||
|
|
//
|
||
|
|
// [31:0] --> testr
|
||
|
|
// ------------------------------------------------------
|
||
|
|
sirv_gnrl_dfflrd #(32) testr_dfflrd (TESTRD, testrwe, wrdata[31:0], testr, clk, rst_n);
|
||
|
|
|
||
|
|
|
||
|
|
// ------------------------------------------------------
|
||
|
|
// -- Soft Reset Count Register
|
||
|
|
//
|
||
|
|
// Write Soft Reset Count for 'sfrtcr' : 6-bit register
|
||
|
|
// Register is split into the following bit fields
|
||
|
|
//
|
||
|
|
// [31:0] --> sfrtcr,default value 32'd300
|
||
|
|
// ------------------------------------------------------
|
||
|
|
sirv_gnrl_dfflrd #(32) sfrtcr_dfflrd (32'd300, sfrtrwe, wrdata[31:0], sfrtr, clk, rst_n);/////////////////////////////sfrtcr-->sfrtr
|
||
|
|
|
||
|
|
// ------------------------------------------------------
|
||
|
|
// -- soft reset count
|
||
|
|
// ------------------------------------------------------
|
||
|
|
|
||
|
|
reg [31:0] cnt_c;
|
||
|
|
|
||
|
|
wire add_cnt = (sys_soft_rstn_r == L)
|
||
|
|
| (mcu_soft_rstn_r == L)
|
||
|
|
| (awg_soft_rstn_r == L)
|
||
|
|
| (dac_soft_rstn_r == L);
|
||
|
|
|
||
|
|
wire end_cnt = add_cnt & (cnt_c == sfrtr-1);
|
||
|
|
|
||
|
|
wire [31:0] cnt_n = end_cnt ? 32'h0 :
|
||
|
|
add_cnt ? cnt_c + 1'b1 :
|
||
|
|
cnt_c ;
|
||
|
|
|
||
|
|
|
||
|
|
sirv_gnrl_dffr #(32) cnt_c_dffr (cnt_n, cnt_c, clk, rst_n);
|
||
|
|
|
||
|
|
// ------------------------------------------------------
|
||
|
|
// -- Soft Reset Register
|
||
|
|
//
|
||
|
|
// Write Soft Reset for 'sfrtr' : 1-bit register
|
||
|
|
// Register is split into the following bit fields
|
||
|
|
//
|
||
|
|
// [16'h0024] --> System Soft Reset ,low active
|
||
|
|
// [16'h0028] --> MCU Soft Reset ,low active
|
||
|
|
// [16'h002C] --> AWG Soft Reset ,low active
|
||
|
|
// [16'h0030] --> DAC Soft Reset ,low active
|
||
|
|
// ------------------------------------------------------
|
||
|
|
|
||
|
|
//sys_soft_rstn_r
|
||
|
|
wire sys_soft_rstn_en = end_cnt | sfrrwe;
|
||
|
|
wire sys_soft_rstn_w = end_cnt ? 1'b1 :
|
||
|
|
sfrrwe ? 1'b0 :
|
||
|
|
1'b1 ;
|
||
|
|
sirv_gnrl_dfflrs #(1) sys_soft_rstn_r_dffls (sys_soft_rstn_en, sys_soft_rstn_w, sys_soft_rstn_r, clk, rst_n);
|
||
|
|
|
||
|
|
//mcu_soft_rstn_r
|
||
|
|
wire mcu_soft_rstn_en = end_cnt | mcurstrwe;
|
||
|
|
wire mcu_soft_rstn_w = end_cnt ? 1'b1 :
|
||
|
|
mcurstrwe ? 1'b0 :
|
||
|
|
1'b1 ;
|
||
|
|
sirv_gnrl_dfflrs #(1) mcu_soft_rstn_r_dffls (mcu_soft_rstn_en, mcu_soft_rstn_w, mcu_soft_rstn_r, clk, rst_n);
|
||
|
|
|
||
|
|
//awg_soft_rstn_r
|
||
|
|
wire awg_soft_rstn_en = end_cnt | awgrstrwe;
|
||
|
|
wire awg_soft_rstn_w = end_cnt ? 1'b1 :
|
||
|
|
awgrstrwe ? 1'b0 :
|
||
|
|
1'b1 ;
|
||
|
|
sirv_gnrl_dfflrs #(1) awg_soft_rstn_r_dffls (awg_soft_rstn_en, awg_soft_rstn_w, awg_soft_rstn_r, clk, rst_n);
|
||
|
|
|
||
|
|
//dac_soft_rstn_r
|
||
|
|
wire dac_soft_rstn_en = end_cnt | adacrstrwe;
|
||
|
|
wire dac_soft_rstn_w = end_cnt ? 1'b1 :
|
||
|
|
adacrstrwe ? 1'b0 :
|
||
|
|
1'b1 ;
|
||
|
|
sirv_gnrl_dfflrs #(1) dac_soft_rstn_r_dffls (dac_soft_rstn_en, dac_soft_rstn_w, dac_soft_rstn_r, clk, rst_n);
|
||
|
|
|
||
|
|
|
||
|
|
assign sys_soft_rstn = sys_soft_rstn_r;//////////////////////////
|
||
|
|
assign mcu_soft_rstn = mcu_soft_rstn_r;//////////////////////////
|
||
|
|
assign awg_soft_rstn = awg_soft_rstn_r;//////////////////////////
|
||
|
|
assign dac_soft_rstn = dac_soft_rstn_r;//////////////////////////
|
||
|
|
|
||
|
|
// ------------------------------------------------------
|
||
|
|
// -- Read data mux
|
||
|
|
//
|
||
|
|
// -- The data from the selected register is
|
||
|
|
// -- placed on a zero-padded 32-bit read data bus.
|
||
|
|
// ------------------------------------------------------
|
||
|
|
always @(*) begin : RDDATA_PROC
|
||
|
|
rddata_reg = {32{1'b0}};
|
||
|
|
if(idren == H ) rddata_reg[31:0] = IDRD;
|
||
|
|
if(vidren == H ) rddata_reg[31:0] = VIDRD;
|
||
|
|
if(dateren == H ) rddata_reg[31:0] = DATERD;
|
||
|
|
if(verren == H ) rddata_reg[31:0] = VERSION;
|
||
|
|
if(testren == H ) rddata_reg[31:0] = testr;
|
||
|
|
if(imren == H ) rddata_reg[31:0] = imr;
|
||
|
|
if(isren == H ) rddata_reg[31:0] = isr;
|
||
|
|
if(misren == H ) rddata_reg[31:0] = misr;
|
||
|
|
if(sfrtren == H ) rddata_reg[31:0] = sfrtr;
|
||
|
|
end
|
||
|
|
|
||
|
|
//rddata
|
||
|
|
sirv_gnrl_dffr #(32) rddata_dffr (rddata_reg, rddata, clk, rst_n);
|
||
|
|
|
||
|
|
// ------------------------------------------------------
|
||
|
|
// -- interrupt status
|
||
|
|
// ------------------------------------------------------
|
||
|
|
|
||
|
|
//read misr clear interrupts
|
||
|
|
assign icr = (misren) && rden;
|
||
|
|
|
||
|
|
//pll_lock_r
|
||
|
|
wire pll_lock_en = icr | pll_lock;
|
||
|
|
sirv_gnrl_dfflr #(1) pll_lock_r_dfflr (pll_lock_en, pll_lock, pll_lock_r, clk, rst_n);
|
||
|
|
|
||
|
|
|
||
|
|
//pll_lost_lock_r
|
||
|
|
wire pll_lost_lock_en = icr | pll_lock;
|
||
|
|
sirv_gnrl_dfflr #(1) pll_lost_lock_r_dfflr (pll_lost_lock_en, pll_lost_lock, pll_lost_lock_r, clk, rst_n);
|
||
|
|
|
||
|
|
|
||
|
|
//ch0_dbg_upd_r
|
||
|
|
wire ch0_dbg_upd_en = icr | ch0_dbg_upd;
|
||
|
|
sirv_gnrl_dfflr #(1) ch0_dbg_upd_r_dfflr (ch0_dbg_upd_en, ch0_dbg_upd, ch0_dbg_upd_r, clk, rst_n);
|
||
|
|
|
||
|
|
//ch0_dbg_fifo_e_r
|
||
|
|
wire ch0_dbg_fifo_e_en = icr | ch0_dbg_fifo_e;
|
||
|
|
sirv_gnrl_dfflr #(1) ch0_dbg_fifo_e_r_dfflr (ch0_dbg_fifo_e_en, ch0_dbg_fifo_e, ch0_dbg_fifo_e_r, clk, rst_n);
|
||
|
|
|
||
|
|
//ch0_dbg_fifo_f_r
|
||
|
|
wire ch0_dbg_fifo_f_en = icr | ch0_dbg_fifo_f;
|
||
|
|
sirv_gnrl_dfflr #(1) ch0_dbg_fifo_f_r_dfflr (ch0_dbg_fifo_f_en, ch0_dbg_fifo_f, ch0_dbg_fifo_f_r, clk, rst_n);
|
||
|
|
|
||
|
|
//ch0_ldst_addr_unalgn_r
|
||
|
|
wire ch0_ldst_addr_unalgn_en = icr | ch0_ldst_addr_unalgn;
|
||
|
|
sirv_gnrl_dfflr #(1) ch0_ldst_addr_unalgn_r_dfflr (ch0_ldst_addr_unalgn_en, ch0_ldst_addr_unalgn, ch0_ldst_addr_unalgn_r, clk, rst_n);
|
||
|
|
|
||
|
|
//ch0_dec_err_r
|
||
|
|
wire ch0_dec_err_en = icr | ch0_dec_err;
|
||
|
|
sirv_gnrl_dfflr #(1) ch0_dec_err_r_dfflr (ch0_dec_err_en, ch0_dec_err, ch0_dec_err_r, clk, rst_n);
|
||
|
|
|
||
|
|
//ch0_exit_irq_r
|
||
|
|
wire ch0_exit_irq_en = icr | ch0_exit_irq;
|
||
|
|
sirv_gnrl_dfflr #(1) ch0_exit_irq_r_dfflr (ch0_exit_irq_en, ch0_exit_irq, ch0_exit_irq_r, clk, rst_n);
|
||
|
|
|
||
|
|
|
||
|
|
//ch1_dbg_upd_r
|
||
|
|
wire ch1_dbg_upd_en = icr | ch1_dbg_upd;
|
||
|
|
sirv_gnrl_dfflr #(1) ch1_dbg_upd_r_dfflr (ch1_dbg_upd_en, ch1_dbg_upd, ch1_dbg_upd_r, clk, rst_n);
|
||
|
|
|
||
|
|
//ch1_dbg_fifo_e_r
|
||
|
|
wire ch1_dbg_fifo_e_en = icr | ch1_dbg_fifo_e;
|
||
|
|
sirv_gnrl_dfflr #(1) ch1_dbg_fifo_e_r_dfflr (ch1_dbg_fifo_e_en, ch1_dbg_fifo_e, ch1_dbg_fifo_e_r, clk, rst_n);
|
||
|
|
|
||
|
|
//ch1_dbg_fifo_f_r
|
||
|
|
wire ch1_dbg_fifo_f_en = icr | ch1_dbg_fifo_f;
|
||
|
|
sirv_gnrl_dfflr #(1) ch1_dbg_fifo_f_r_dfflr (ch1_dbg_fifo_f_en, ch1_dbg_fifo_f, ch1_dbg_fifo_f_r, clk, rst_n);
|
||
|
|
|
||
|
|
//ch1_ldst_addr_unalgn_r
|
||
|
|
wire ch1_ldst_addr_unalgn_en = icr | ch1_ldst_addr_unalgn;
|
||
|
|
sirv_gnrl_dfflr #(1) ch1_ldst_addr_unalgn_r_dfflr (ch1_ldst_addr_unalgn_en, ch1_ldst_addr_unalgn, ch1_ldst_addr_unalgn_r, clk, rst_n);
|
||
|
|
|
||
|
|
//ch1_dec_err_r
|
||
|
|
wire ch1_dec_err_en = icr | ch1_dec_err;
|
||
|
|
sirv_gnrl_dfflr #(1) ch1_dec_err_r_dfflr (ch1_dec_err_en, ch1_dec_err, ch1_dec_err_r, clk, rst_n);
|
||
|
|
|
||
|
|
//ch1_exit_irq_r
|
||
|
|
wire ch1_exit_irq_en = icr | ch1_exit_irq;
|
||
|
|
sirv_gnrl_dfflr #(1) ch1_exit_irq_r_dfflr (ch1_exit_irq_en, ch1_exit_irq, ch1_exit_irq_r, clk, rst_n);
|
||
|
|
|
||
|
|
//ch2_dbg_upd_r
|
||
|
|
wire ch2_dbg_upd_en = icr | ch2_dbg_upd;
|
||
|
|
sirv_gnrl_dfflr #(1) ch2_dbg_upd_r_dfflr (ch2_dbg_upd_en, ch2_dbg_upd, ch2_dbg_upd_r, clk, rst_n);
|
||
|
|
|
||
|
|
//ch2_dbg_fifo_e_r
|
||
|
|
wire ch2_dbg_fifo_e_en = icr | ch2_dbg_fifo_e;
|
||
|
|
sirv_gnrl_dfflr #(1) ch2_dbg_fifo_e_r_dfflr (ch2_dbg_fifo_e_en, ch2_dbg_fifo_e, ch2_dbg_fifo_e_r, clk, rst_n);
|
||
|
|
|
||
|
|
//ch2_dbg_fifo_f_r
|
||
|
|
wire ch2_dbg_fifo_f_en = icr | ch2_dbg_fifo_f;
|
||
|
|
sirv_gnrl_dfflr #(1) ch2_dbg_fifo_f_r_dfflr (ch2_dbg_fifo_f_en, ch2_dbg_fifo_f, ch2_dbg_fifo_f_r, clk, rst_n);
|
||
|
|
|
||
|
|
//ch2_ldst_addr_unalgn_r
|
||
|
|
wire ch2_ldst_addr_unalgn_en = icr | ch2_ldst_addr_unalgn;
|
||
|
|
sirv_gnrl_dfflr #(1) ch2_ldst_addr_unalgn_r_dfflr (ch2_ldst_addr_unalgn_en, ch2_ldst_addr_unalgn, ch2_ldst_addr_unalgn_r, clk, rst_n);
|
||
|
|
|
||
|
|
//ch2_dec_err_r
|
||
|
|
wire ch2_dec_err_en = icr | ch2_dec_err;
|
||
|
|
sirv_gnrl_dfflr #(1) ch2_dec_err_r_dfflr (ch2_dec_err_en, ch2_dec_err, ch2_dec_err_r, clk, rst_n);
|
||
|
|
|
||
|
|
//ch2_exit_irq_r
|
||
|
|
wire ch2_exit_irq_en = icr | ch2_exit_irq;
|
||
|
|
sirv_gnrl_dfflr #(1) ch2_exit_irq_r_dfflr (ch2_exit_irq_en, ch2_exit_irq, ch2_exit_irq_r, clk, rst_n);
|
||
|
|
|
||
|
|
//ch3_dbg_upd_r
|
||
|
|
wire ch3_dbg_upd_en = icr | ch3_dbg_upd;
|
||
|
|
sirv_gnrl_dfflr #(1) ch3_dbg_upd_r_dfflr (ch3_dbg_upd_en, ch3_dbg_upd, ch3_dbg_upd_r, clk, rst_n);
|
||
|
|
|
||
|
|
//ch3_dbg_fifo_e_r
|
||
|
|
wire ch3_dbg_fifo_e_en = icr | ch3_dbg_fifo_e;
|
||
|
|
sirv_gnrl_dfflr #(1) ch3_dbg_fifo_e_r_dfflr (ch3_dbg_fifo_e_en, ch3_dbg_fifo_e, ch3_dbg_fifo_e_r, clk, rst_n);
|
||
|
|
|
||
|
|
//ch3_dbg_fifo_f_r
|
||
|
|
wire ch3_dbg_fifo_f_en = icr | ch3_dbg_fifo_f;
|
||
|
|
sirv_gnrl_dfflr #(1) ch3_dbg_fifo_f_r_dfflr (ch3_dbg_fifo_f_en, ch3_dbg_fifo_f, ch3_dbg_fifo_f_r, clk, rst_n);
|
||
|
|
|
||
|
|
//ch3_ldst_addr_unalgn_r
|
||
|
|
wire ch3_ldst_addr_unalgn_en = icr | ch3_ldst_addr_unalgn;
|
||
|
|
sirv_gnrl_dfflr #(1) ch3_ldst_addr_unalgn_r_dfflr (ch3_ldst_addr_unalgn_en, ch3_ldst_addr_unalgn, ch3_ldst_addr_unalgn_r, clk, rst_n);
|
||
|
|
|
||
|
|
//ch3_dec_err_r
|
||
|
|
wire ch3_dec_err_en = icr | ch3_dec_err;
|
||
|
|
sirv_gnrl_dfflr #(1) ch3_dec_err_r_dfflr (ch3_dec_err_en, ch3_dec_err, ch3_dec_err_r, clk, rst_n);
|
||
|
|
|
||
|
|
//ch3_exit_irq_r
|
||
|
|
wire ch3_exit_irq_en = icr | ch3_exit_irq;
|
||
|
|
sirv_gnrl_dfflr #(1) ch3_exit_irq_r_dfflr (ch3_exit_irq_en, ch3_exit_irq, ch3_exit_irq_r, clk, rst_n);
|
||
|
|
|
||
|
|
//irisr
|
||
|
|
assign irisr[31] = pll_lock_r ;
|
||
|
|
assign irisr[30] = pll_lost_lock_r ;
|
||
|
|
assign irisr[29] = ch3_dbg_upd_r ;
|
||
|
|
assign irisr[28] = ch3_dbg_fifo_e_r ;
|
||
|
|
assign irisr[27] = ch3_dbg_fifo_f_r ;
|
||
|
|
assign irisr[26] = ch3_ldst_addr_unalgn_r ;
|
||
|
|
assign irisr[25] = ch3_dec_err_r ;
|
||
|
|
assign irisr[24] = ch3_exit_irq_r ;
|
||
|
|
assign irisr[23] = L ;
|
||
|
|
assign irisr[22] = L ;
|
||
|
|
assign irisr[21] = ch2_dbg_upd_r ;
|
||
|
|
assign irisr[20] = ch2_dbg_fifo_e_r ;
|
||
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assign irisr[19] = ch2_dbg_fifo_f_r ;
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||
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assign irisr[18] = ch2_ldst_addr_unalgn_r ;
|
||
|
|
assign irisr[17] = ch2_dec_err_r ;
|
||
|
|
assign irisr[16] = ch2_exit_irq_r ;
|
||
|
|
assign irisr[15] = L ;
|
||
|
|
assign irisr[14] = L ;
|
||
|
|
assign irisr[13] = ch1_dbg_upd_r ;
|
||
|
|
assign irisr[12] = ch1_dbg_fifo_e_r ;
|
||
|
|
assign irisr[11] = ch1_dbg_fifo_f_r ;
|
||
|
|
assign irisr[10] = ch1_ldst_addr_unalgn_r ;
|
||
|
|
assign irisr[9 ] = ch1_dec_err_r ;
|
||
|
|
assign irisr[8 ] = ch1_exit_irq_r ;
|
||
|
|
assign irisr[7 ] = L ;
|
||
|
|
assign irisr[6 ] = L ;
|
||
|
|
assign irisr[5 ] = ch0_dbg_upd_r ;
|
||
|
|
assign irisr[4 ] = ch0_dbg_fifo_e_r ;
|
||
|
|
assign irisr[3 ] = ch0_dbg_fifo_f_r ;
|
||
|
|
assign irisr[2 ] = ch0_ldst_addr_unalgn_r ;
|
||
|
|
assign irisr[1 ] = ch0_dec_err_r ;
|
||
|
|
assign irisr[0 ] = ch0_exit_irq_r ;
|
||
|
|
|
||
|
|
// ------------------------------------------------------
|
||
|
|
// -- Interrupt Status Register - Read Only
|
||
|
|
//
|
||
|
|
// This register contains the status of all
|
||
|
|
// XYZ Chip interrupts after masking.
|
||
|
|
// ------------------------------------------------------
|
||
|
|
sirv_gnrl_dffr #(32) isr_dffr (irisr, isr, clk, rst_n);
|
||
|
|
|
||
|
|
//misr
|
||
|
|
wire[31:0] misr_w = imr & irisr;
|
||
|
|
sirv_gnrl_dffr #(32) misr_dffr (misr_w, misr, clk, rst_n);
|
||
|
|
|
||
|
|
//irq
|
||
|
|
wire irq_w = |misr;
|
||
|
|
sirv_gnrl_dffr #(1) irq_dffr (irq_w, irq, clk, rst_n);
|
||
|
|
|
||
|
|
|
||
|
|
endmodule
|
||
|
|
|
||
|
|
|
||
|
|
`undef IDR
|
||
|
|
`undef VIDR
|
||
|
|
`undef DATER
|
||
|
|
`undef VERR
|
||
|
|
`undef TESTR
|
||
|
|
`undef IMR
|
||
|
|
`undef ISR
|
||
|
|
`undef MISR
|
||
|
|
`undef SFRTR
|
||
|
|
`undef SFRR
|
||
|
|
`undef MCURSTR
|
||
|
|
`undef AWGRSTR
|
||
|
|
`undef DACRSTR
|