519 lines
14 KiB
Coq
519 lines
14 KiB
Coq
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//+FHDR--------------------------------------------------------------------------------------------------------
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// Company:
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//-----------------------------------------------------------------------------------------------------------------
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// File Name : spi_to_sram_v1.2.v
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// Department :
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// Author : ZYZ
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// Author's Tel :
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//-----------------------------------------------------------------------------------------------------------------
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// Relese History
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// Version Date Author Description
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// 1.2 2024-04-02 ZYZ
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//-----------------------------------------------------------------------------------------------------------------
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// Keywords : 1.replace stream mode of send 32bit data 16 times
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// 2.wrdata_reg address is no longer related to csn_active
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//-----------------------------------------------------------------------------------------------------------------
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// Parameter
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Purpose :
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Target Device:
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// Tool versions:
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//-----------------------------------------------------------------------------------------------------------------
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// Reuse Issues
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// Reset Strategy:
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// Clock Domains:
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// Critical Timing:
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// Asynchronous I/F:
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// Synthesizable (y/n):
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// Other:
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//-FHDR--------------------------------------------------------------------------------------------------------
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module spi_to_sram (
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//system port
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input clk // System Main Clock
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,input spi_rstn // Spi Reset active low
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//spi port
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,input sclk // Spi Clock
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,input csn // Spi Chip Select active low
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,input mosi // Spi Mosi
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,output miso // Spi Miso
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,output miso_oen // Spi Miso output enable
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,output error_check // spi form check
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,output [31:0] wrdata //write data to sram
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,output [24:0] addr //sram address
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,output wren //write enable sram
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,output rden //rden enable sram
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,input [31:0] rddata //read data from sram
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);
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localparam L = 1'b0,
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H = 1'b1;
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//3-bits shift register for sclk's rising & falling edges
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reg [2 :0] sclk_reg;
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wire sclk_p;
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wire sclk_n;
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//3-bits shift register for csn
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reg [4 :0] csn_reg;
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wire csn_active;
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//2-bits shift register for mosi
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reg [1 :0] mosi_reg;
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wire mosi_data;
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//cmd_reg--> 0:write,1:read
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reg cmd_reg;
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//rxs_reg
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reg rxs_reg;
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//addr_reg--> initial address
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reg [24 :0] addr_reg;
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//rxd_reg --> recive data
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reg [31 :0] rxd_reg;
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//rx;
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reg [9 :0] rxcnt;
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wire add_rxcnt;
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wire end_rxcnt;
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wire wr_times;
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reg recv_start;
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reg wren_reg;
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reg wren_reg_1;
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reg [31 :0] wrdata_reg;
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//send data
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reg [31 :0] txd_reg;
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//tx;
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reg [9 :0] txcnt;
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wire add_txcnt;
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wire end_txcnt;
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reg trans_start;
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//read write address
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reg [24:0] rwaddr_reg;
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reg address_start;
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wire add_addr_wr;
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wire add_addr_rd;
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//read rddata to txd_reg
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reg rd_times;
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//read sram
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wire rd_sram; //foreread
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//output enable
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reg miso_reg;
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reg miso_oen_reg;
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//data form check
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reg error_check_reg ;
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reg [9:0] frame_len;
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//////////////////////////////////////////////////////////////////////////
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//capture the sck
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//////////////////////////////////////////////////////////////////////////
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//sync sclk to the main clock using a 3-bits shift register
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always @(posedge clk or negedge spi_rstn) begin
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if(spi_rstn == L) begin
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sclk_reg <= 3'b000;
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end
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else begin
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sclk_reg <= {sclk_reg[1:0],sclk};
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end
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end
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//sclk's rising edges
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assign sclk_p = (sclk_reg[2:1] == 2'b01);
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//sclk's falling edges
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assign sclk_n = (sclk_reg[2:1] == 2'b10);
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//////////////////////////////////////////////////////////////////////////
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//capture the csn
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//////////////////////////////////////////////////////////////////////////
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//sync csn to the main clock using a 3-bits shift register
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always @(posedge clk or negedge spi_rstn) begin
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if(spi_rstn == L) begin
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csn_reg <= 5'b11111;
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end
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else begin
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csn_reg <= {csn_reg[3:0],csn};
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end
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end
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// csn is active low
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assign csn_active = ~csn_reg[1];
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//////////////////////////////////////////////////////////////////////////
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//capture the mosi
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//////////////////////////////////////////////////////////////////////////
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//sync mosi to the main clock using a 2-bits shift register
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always @(posedge clk or negedge spi_rstn) begin
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if(spi_rstn == L) begin
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mosi_reg <= 2'b00;
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end
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else begin
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mosi_reg <= {mosi_reg[0],mosi};
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end
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end
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//mosi_data
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assign mosi_data = mosi_reg[1];
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//////////////////////////////////////////////////////////////////////////
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//rxcnt
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//////////////////////////////////////////////////////////////////////////
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always @(posedge clk or negedge spi_rstn) begin
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if(spi_rstn == L) begin
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rxcnt <= 10'd0;
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end
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else if(end_rxcnt) begin
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rxcnt <= 10'd0;
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end
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else if (add_rxcnt)begin
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rxcnt <= rxcnt + 1'b1;
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end
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else begin
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rxcnt <= rxcnt;
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end
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end
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//add_rxcnt
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assign add_rxcnt = sclk_p && csn_active;
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assign end_rxcnt = add_rxcnt & (rxcnt == frame_len - 1'b1);
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assign wr_times = add_rxcnt & (rxcnt[4:0] == 5'd31) & ~cmd_reg;
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//////////////////////////////////////////////////////////////////////////
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//cmd_reg
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//////////////////////////////////////////////////////////////////////////
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always @(posedge clk or negedge spi_rstn) begin
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if(spi_rstn == L) begin
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cmd_reg <= 1'b0;
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end
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else if(add_rxcnt && rxcnt == 10'd0 ) begin
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cmd_reg <= mosi_data;
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end
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else begin
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cmd_reg <= cmd_reg;
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end
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end
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//////////////////////////////////////////////////////////////////////////
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//rxs_reg
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//////////////////////////////////////////////////////////////////////////
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always @(posedge clk or negedge spi_rstn) begin
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if(spi_rstn == L ) begin
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rxs_reg <= 1'b0;
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end
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else if(add_rxcnt && rxcnt == 10'd1) begin
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rxs_reg <= mosi_data;
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end
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else begin
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rxs_reg <= rxs_reg;
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end
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end
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//////////////////////////////////////////////////////////////////////////
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//addr_reg
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//////////////////////////////////////////////////////////////////////////
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always @(posedge clk or negedge spi_rstn) begin
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if(spi_rstn == L ) begin
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addr_reg <= 25'd0;
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end
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else if(add_rxcnt && rxcnt <= 10'd26 ) begin
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addr_reg <= {addr_reg[23:0],mosi_data};
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end
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else begin
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addr_reg <= addr_reg;
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end
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end
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//////////////////////////////////////////////////////////////////////////
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//rxd_reg
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//////////////////////////////////////////////////////////////////////////
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always @(posedge clk or negedge spi_rstn) begin
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if(spi_rstn == L) begin
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rxd_reg <= 32'd0;
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end
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else if(add_rxcnt) begin
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rxd_reg <= {rxd_reg[30:0],mosi_data};
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end
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else begin
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rxd_reg <= rxd_reg;
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end
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end
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//////////////////////////////////////////////////////////////////////////
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//frame_len
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//////////////////////////////////////////////////////////////////////////
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always @(posedge clk or negedge spi_rstn) begin
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if(spi_rstn == L) begin
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frame_len <= 10'd0;
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end
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else if(add_rxcnt && rxcnt == 10'd2) begin
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if(rxs_reg) begin
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frame_len <= 10'd544;
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end
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else begin
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frame_len <= 10'd64;
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end
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end
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else begin
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frame_len <= frame_len;
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end
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end
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//////////////////////////////////////////////////////////////////////////
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//recv_start
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//////////////////////////////////////////////////////////////////////////
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always @(posedge clk or negedge spi_rstn) begin
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if(spi_rstn == L) begin
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recv_start <= 1'b0;
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end
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else if(~csn_active )begin
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recv_start <= 1'b0;
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end
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else if(wr_times)begin
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recv_start <= 1'b1;
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end
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else begin
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recv_start <= recv_start;
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end
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end
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//////////////////////////////////////////////////////////////////////////
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//wren_reg
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//////////////////////////////////////////////////////////////////////////
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always @(posedge clk or negedge spi_rstn) begin
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if(spi_rstn == L) begin
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wren_reg <= 1'b0;
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end
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else begin
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wren_reg <= recv_start & wr_times ;
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wren_reg_1 <= wren_reg;
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end
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end
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//////////////////////////////////////////////////////////////////////////
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//wrdata_reg
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//////////////////////////////////////////////////////////////////////////
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always @(posedge clk or negedge spi_rstn) begin
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if(spi_rstn == L) begin
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wrdata_reg <= 32'b0;
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end
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else if(wren_reg)begin
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wrdata_reg <= rxd_reg;
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end
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end
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//////////////////////////////////////////////////////////////////////////
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//txcnt
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//////////////////////////////////////////////////////////////////////////
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always @(posedge clk or negedge spi_rstn) begin
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if(spi_rstn == L) begin
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txcnt <= 10'd0;
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end
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else if(end_txcnt) begin
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txcnt <= 10'd0;
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end
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else if (add_txcnt)begin
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txcnt <= txcnt + 1'b1;
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end
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else begin
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txcnt <= txcnt;
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end
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end
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//add_txcnt
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assign add_txcnt = sclk_n && csn_active;
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//end_txcnt
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assign end_txcnt = add_txcnt && (txcnt == frame_len - 1'b1) ;
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//////////////////////////////////////////////////////////////////////////
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//rd_times
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//////////////////////////////////////////////////////////////////////////
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always@(*)begin
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if(rxs_reg)begin
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rd_times = add_txcnt & (txcnt[4:0] == 5'd31)& (txcnt != 10'd543) & cmd_reg;
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end
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else begin
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rd_times = add_txcnt & (txcnt[4:0] == 5'd31)& (txcnt != 10'd63) & cmd_reg;
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end
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end
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//rd_sram foreread
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//assign rd_sram = (rd_times) | (add_txcnt & (txcnt[9:0] == 5'd30) & cmd_reg) ;
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assign rd_sram = rd_times & cmd_reg;
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//////////////////////////////////////////////////////////////////////////
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//trans_start
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//////////////////////////////////////////////////////////////////////////
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always @(posedge clk or negedge spi_rstn) begin
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if(spi_rstn == L) begin
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trans_start <= 1'b0;
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end
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else if(rd_times)begin
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trans_start <= 1'b1;
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end
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else if(~csn_active)begin
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trans_start <= 1'b0;
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end
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else begin
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trans_start <= trans_start;
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end
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end
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//////////////////////////////////////////////////////////////////////////
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//txd_reg
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//////////////////////////////////////////////////////////////////////////
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reg [2:0] rd_times_r;
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always @(posedge clk or negedge spi_rstn) begin
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if(spi_rstn == L) begin
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rd_times_r <= 3'b0;
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end
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else begin
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rd_times_r <= {rd_times_r[1:0],rd_times};
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end
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end
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always @(posedge clk or negedge spi_rstn) begin
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if(spi_rstn == L) begin
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txd_reg <= 32'h0;
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end
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else if(rd_times_r[2]) begin
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txd_reg <= rddata;
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end
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else if(add_txcnt && trans_start && txcnt[4:0]!=5'd31) begin
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txd_reg <= {txd_reg[30:0],1'b0};
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end
|
||
|
|
else begin
|
||
|
|
txd_reg <= txd_reg;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
//////////////////////////////////////////////////////////////////////////
|
||
|
|
//address_start
|
||
|
|
//////////////////////////////////////////////////////////////////////////
|
||
|
|
|
||
|
|
always @(posedge clk or negedge spi_rstn) begin
|
||
|
|
if(spi_rstn == L) begin
|
||
|
|
address_start <= 1'b0;
|
||
|
|
end
|
||
|
|
else if(txcnt == 10'd29)begin
|
||
|
|
address_start <= 1'b1;
|
||
|
|
end
|
||
|
|
else if(~csn_active)begin
|
||
|
|
address_start <= 1'b0;
|
||
|
|
end
|
||
|
|
else begin
|
||
|
|
address_start <= address_start;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
//////////////////////////////////////////////////////////////////////////
|
||
|
|
//rwaddr_reg
|
||
|
|
//////////////////////////////////////////////////////////////////////////
|
||
|
|
|
||
|
|
always @(posedge clk or negedge spi_rstn) begin
|
||
|
|
if(spi_rstn == L) begin
|
||
|
|
rwaddr_reg <= 25'b0;
|
||
|
|
end
|
||
|
|
else if(address_start)begin
|
||
|
|
if(add_addr_wr)begin
|
||
|
|
rwaddr_reg <= rwaddr_reg + 3'd4;
|
||
|
|
end
|
||
|
|
else if(add_addr_rd)begin
|
||
|
|
rwaddr_reg <= rwaddr_reg + 3'd4;
|
||
|
|
end
|
||
|
|
else begin
|
||
|
|
rwaddr_reg <= rwaddr_reg;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
else begin
|
||
|
|
rwaddr_reg <= addr_reg;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
|
||
|
|
assign add_addr_wr = rxs_reg & wren_reg_1 ;
|
||
|
|
assign add_addr_rd = rxs_reg & rd_sram ;
|
||
|
|
|
||
|
|
//////////////////////////////////////////////////////////////////////////
|
||
|
|
//miso_reg
|
||
|
|
//////////////////////////////////////////////////////////////////////////
|
||
|
|
always @(posedge clk or negedge spi_rstn) begin
|
||
|
|
if(spi_rstn == L) begin
|
||
|
|
miso_reg <= 1'b0;
|
||
|
|
end
|
||
|
|
else begin
|
||
|
|
miso_reg <= txd_reg[31];
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
//////////////////////////////////////////////////////////////////////////
|
||
|
|
//miso_oen_reg
|
||
|
|
//////////////////////////////////////////////////////////////////////////
|
||
|
|
always @(posedge clk or negedge spi_rstn) begin
|
||
|
|
if(spi_rstn == L) begin
|
||
|
|
miso_oen_reg <= 1'b1;
|
||
|
|
end
|
||
|
|
else begin
|
||
|
|
miso_oen_reg <= ~(trans_start & cmd_reg);
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
//////////////////////////////////////////////////////////////////////////
|
||
|
|
//error_check
|
||
|
|
//////////////////////////////////////////////////////////////////////////
|
||
|
|
always @(posedge clk or negedge spi_rstn) begin
|
||
|
|
if(spi_rstn == L) begin
|
||
|
|
error_check_reg <= 1'b0;
|
||
|
|
end
|
||
|
|
else if( (rxcnt != 0 || txcnt != 0)&&(~csn_active) )begin
|
||
|
|
error_check_reg <= 1'b1;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
//////////////////////////////////////////////////////////////////////////
|
||
|
|
//Outputs signals
|
||
|
|
//////////////////////////////////////////////////////////////////////////
|
||
|
|
//wren
|
||
|
|
assign wren = wren_reg_1 ;
|
||
|
|
//wrdata
|
||
|
|
assign wrdata = wrdata_reg;
|
||
|
|
//rden
|
||
|
|
assign rden = rd_sram ;
|
||
|
|
//addr
|
||
|
|
assign addr = rwaddr_reg;
|
||
|
|
//miso
|
||
|
|
assign miso = miso_reg;
|
||
|
|
//miso_oen
|
||
|
|
assign miso_oen = miso_oen_reg;
|
||
|
|
//error_check
|
||
|
|
assign error_check = error_check_reg;
|
||
|
|
|
||
|
|
endmodule
|
||
|
|
|
||
|
|
|