71 lines
2.2 KiB
Coq
71 lines
2.2 KiB
Coq
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module spi_slave (
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//system port
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input clk // System Main Clock
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,input rstn // Spi Reset active low
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//spi port
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,input sclk // Spi Clock
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,input csn // Spi Chip Select active low
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,input mosi // Spi Mosi
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,output miso // Spi Miso
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,output miso_oen // Spi Miso output enable
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//awg read and write signals
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,output error_check
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);
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wire [31 :0] wrdata ;
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wire wren ;
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wire [24 :0] rwaddr ;
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wire rden ;
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wire [31 :0] rddata ;
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//////////////////////////////////////////////////////////////////////////
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//spi_interface inst
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//////////////////////////////////////////////////////////////////////////
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spi_to_sram spi_to_sram_inst (
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//system port
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.clk ( clk )
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,.spi_rstn ( rstn )
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//spi port
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,.sclk ( sclk )
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,.csn ( csn )
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,.mosi ( mosi )
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,.miso ( miso )
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,.miso_oen ( miso_oen )
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,.error_check ( error_check )
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//data & cmd port
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//output
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,.addr ( rwaddr )
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,.wren ( wren )
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,.wrdata ( wrdata )
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,.rden ( rden )
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,.rddata ( rddata )
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);
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//////////////////////////////////////////////////////////////////////////
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//sram
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//////////////////////////////////////////////////////////////////////////
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spram_model #(
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.width(32),
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.depth(33554432)//2^25
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)spram_model_inst(
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.clka(clk)
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,.ena(wren)
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,.dina(wrdata)
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,.addra(rwaddr)
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,.clkb(clk)
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,.enb(rden)
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,.doutb(rddata)
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,.addrb(rwaddr)
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);
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endmodule
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