89 lines
3.3 KiB
Systemverilog
89 lines
3.3 KiB
Systemverilog
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//+FHDR--------------------------------------------------------------------------------------------------------
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// Company:
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//-----------------------------------------------------------------------------------------------------------------
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// File Name : spi_bus_decoder.v
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// Department :
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// Author : PWY
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// Author's Tel :
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//-----------------------------------------------------------------------------------------------------------------
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// Relese History
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// Version Date Author Description
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// 0.1 2024-03-13 PWY Serial Peripheral Interface BUS Decoder
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//-----------------------------------------------------------------------------------------------------------------
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// Keywords :
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Parameter
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Purpose :
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Target Device:
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// Tool versions:
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//-----------------------------------------------------------------------------------------------------------------
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// Reuse Issues
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// Reset Strategy:
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// Clock Domains:
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// Critical Timing:
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// Asynchronous I/F:
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// Synthesizable (y/n):
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// Other:
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//-FHDR--------------------------------------------------------------------------------------------------------
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module spi_bus_decoder #(
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parameter SLVNUM = 32
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,parameter SPIBUS_CMD_REG = 1
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,parameter SPIBUS_OUT_REG = 1
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)(
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input clk
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,input rst_n
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,sram_if.slave mst
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,sram_if.master slv [SLVNUM-1:0] //s and m exchange
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);
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generate
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genvar i;
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logic [SLVNUM-1:0] cs_slv;
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logic [31 :0] dtemp[SLVNUM-1:0];
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for(i=0;i<SLVNUM;i=i+1) begin
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//generating device chip select signal
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//the largest 5bit addr is used to select among 32 SRAM
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assign cs_slv[i] = (mst.addr[24:20] == i );
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//generating device read/write signal
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if(SPIBUS_CMD_REG == 1) begin :CMD_REG
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sirv_gnrl_dffr #(25) rwaddr_dffr ({25{cs_slv[i]}} & {5'b0,mst.addr[19:0]} ,slv[i].addr, clk, rst_n);
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sirv_gnrl_dffr #(32) wrdata_dffr ({32{cs_slv[i]}} & mst.din ,slv[i].din, clk, rst_n);
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sirv_gnrl_dffr #(1) wren_dffr (cs_slv[i] & mst.wren ,slv[i].wren, clk, rst_n);
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sirv_gnrl_dffr #(1) reen_dffr (cs_slv[i] & mst.rden ,slv[i].rden, clk, rst_n);
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end
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else begin :CMD_DONT_REG
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assign slv[i].addr = {25{cs_slv[i]}} & {5'b0,mst.addr[19:0]};
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assign slv[i].wren = cs_slv[i] & mst.wren;
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assign slv[i].rden = cs_slv[i] & mst.rden;
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assign slv[i].din = {32{cs_slv[i]}} & mst.din;
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end
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assign slv[i].wben = {32{cs_slv[i]}} & mst.din;
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if(i==0) begin
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assign dtemp[i] = (cs_slv[i]) ? slv[i].dout : 32'b0;
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end
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else begin
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assign dtemp[i] = (cs_slv[i]) ? slv[i].dout : dtemp[i-1];
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end
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end
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//read data from register
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if(SPIBUS_OUT_REG == 1) begin :OUT_REG
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sirv_gnrl_dffr #(32) rddata_dffr (dtemp[SLVNUM-1], mst.dout, clk, rst_n);
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end
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else begin : OUT_DONT_REG
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assign mst.dout = dtemp[SLVNUM-1];
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end
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endgenerate
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endmodule
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