50 lines
1.9 KiB
Coq
50 lines
1.9 KiB
Coq
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/*
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Copyright 2018-2020 Nuclei System Technology, Inc.
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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//=====================================================================
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//
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// Designer : Bob Hu
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//
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// Description:
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// Verilog module for X checker
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//
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// ====================================================================
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`ifndef FPGA_SOURCE//{
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`ifndef DISABLE_SV_ASSERTION//{
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//synopsys translate_off
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module sirv_gnrl_xchecker # (
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parameter DW = 32
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) (
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input [DW-1:0] i_dat,
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input clk
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);
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CHECK_THE_X_VALUE:
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assert property (@(posedge clk)
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((^(i_dat)) !== 1'bx)
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)
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else $fatal ("\n Error: Oops, detected a X value!!! This should never happen. \n");
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endmodule
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//synopsys translate_on
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`endif//}
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`endif//}
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