32 lines
582 B
Systemverilog
32 lines
582 B
Systemverilog
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interface ram_if(input clk, input rst_n);
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logic [31 :0] wrdata ; // write data
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logic wren ; // write enable
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logic [24 :0] rwaddr ; // read & write address
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logic rden ; // read enable
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logic [31 :0] rddata ; // read data
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//master
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modport m (
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output wrdata
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,output wren
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,output rwaddr
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,output rden
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,input rddata
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);
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//slave
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modport s (
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input wrdata
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,input wren
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,input rwaddr
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,input rden
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,output rddata
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);
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endinterface
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