1002 lines
41 KiB
Coq
1002 lines
41 KiB
Coq
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//+FHDR--------------------------------------------------------------------------------------------------------
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// Company:
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//-----------------------------------------------------------------------------------------------------------------
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// File Name : awg_regfile.v
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// Department :
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// Author : PWY
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// Author's Tel :
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//-----------------------------------------------------------------------------------------------------------------
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// Relese History
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// Version Date Author Description
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// 0.1 2024-03-13 PWY AWG dedicated register file
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//-----------------------------------------------------------------------------------------------------------------
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// Keywords :
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Parameter
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Purpose :
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Target Device:
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// Tool versions:
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//-----------------------------------------------------------------------------------------------------------------
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// Reuse Issues
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// Reset Strategy:
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// Clock Domains:
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// Critical Timing:
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// Asynchronous I/F:
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// Synthesizable (y/n):
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// Other:
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//-FHDR--------------------------------------------------------------------------------------------------------
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// -----------------------------------------------------------
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// -- Register address offset macros
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// -----------------------------------------------------------
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//MCU parameter register 0
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`define MCUPARAR0 16'h00
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//MCU parameter register 1
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`define MCUPARAR1 16'h04
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//MCU parameter register 2
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`define MCUPARAR2 16'h08
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//MCU parameter register 3
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`define MCUPARAR3 16'h0C
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//MCU result register 0
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`define MCURESR0 16'h10
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//MCU result register 1
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`define MCURESR1 16'h14
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//MCU result register 2
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`define MCURESR2 16'h18
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//MCU result register 3
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`define MCURESR3 16'h1C
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//Run-time register
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`define RTIMR 16'h98
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//Instruction count register
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`define ICNTR 16'h9C
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//Feedback state information register
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`define FSIR 16'hA0
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//Modulator Operation Mode Register
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`define MODMR 16'h100
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//Interpolator Operation Mode Register
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`define INTPMR 16'h104
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//Frequency Mixer NCO Clear Register
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`define MIXNCOCR 16'h108
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//Frequency Mixer NCO Frequency Control Word High 32-bit Register
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`define MIXNFCWHR 16'h10C
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//Frequency Mixer NCO Frequency Control Word Low 16-bit Register
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`define MIXNFCWLR 16'h110
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//Frequency Mixer NCO Phase Control Word Register
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`define MIXNPHAR 16'h114
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//Frequency Mixer Operating Mode Register
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`define MIXMR 16'h118
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//Frequency Mixer Output Data Type Register
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`define MIXODTR 16'h11C
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//Frequency Mixer Output Data Format Register
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`define MIXODFR 16'h120
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//Interpolator Selection Register
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`define INTPSELR 16'h128
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//Tail Correction Bypass Register
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`define TCBPR 16'h12C
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//Tail Correction A Parameter Real Part Value Register 0
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`define TCPARR0 16'h130
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//Tail Correction A Parameter Real Part Value Register 1
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`define TCPARR1 16'h134
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//Tail Correction A Parameter Real Part Value Register 2
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`define TCPARR2 16'h138
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//Tail Correction A Parameter Real Part Value Register 3
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`define TCPARR3 16'h13C
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//Tail Correction A Parameter Real Part Value Register 4
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`define TCPARR4 16'h140
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//Tail Correction A Parameter Real Part Value Register 5
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`define TCPARR5 16'h144
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//Tail Correction B Parameter Real Part Value Register 0
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`define TCPBRR0 16'h148
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//Tail Correction B Parameter Real Part Value Register 1
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`define TCPBRR1 16'h14C
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//Tail Correction B Parameter Real Part Value Register 2
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`define TCPBRR2 16'h150
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//Tail Correction B Parameter Real Part Value Register 3
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`define TCPBRR3 16'h154
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//Tail Correction B Parameter Real Part Value Register 4
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`define TCPBRR4 16'h158
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//Tail Correction B Parameter Real Part Value Register 5
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`define TCPBRR5 16'h15C
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//Tail Correction A Parameter Imaginary Part Value Register 0
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`define TCPAIR0 16'h160
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//Tail Correction A Parameter Imaginary Part Value Register 1
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`define TCPAIR1 16'h164
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//Tail Correction A Parameter Imaginary Part Value Register 2
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`define TCPAIR2 16'h168
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//Tail Correction A Parameter Imaginary Part Value Register 3
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`define TCPAIR3 16'h16C
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//Tail Correction A Parameter Imaginary Part Value Register 4
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`define TCPAIR4 16'h170
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//Tail Correction A Parameter Imaginary Part Value Register 5
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`define TCPAIR5 16'h174
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//Tail Correction B Parameter Imaginary Part Value Register 0
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`define TCPBIR0 16'h178
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//Tail Correction A Parameter Imaginary Part Value Register 1
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`define TCPBIR1 16'h17C
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//Tail Correction B Parameter Imaginary Part Value Register 2
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`define TCPBIR2 16'h180
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//Tail Correction B Parameter Imaginary Part Value Register 3
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`define TCPBIR3 16'h184
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//Tail Correction B Parameter Imaginary Part Value Register 4
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`define TCPBIR4 16'h188
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//Tail Correction B Parameter Imaginary Part Value Register 5
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`define TCPBIR5 16'h18C
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module awg_regfile (
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//system port
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input clk // System Main Clock
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,input rst_n // Spi Reset active low
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//rw op port
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,input [31 :0] wrdata // write data
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,input wren // write enable
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,input [15 :0] rwaddr // read & write address
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,input rden // read enable
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,output [31 :0] rddata // read data
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,input [2 :0] fb_st_i
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,input [31 :0] run_time
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,input [31 :0] instr_num
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//MCU and SPI interface for interaction
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,output [31 :0] mcu_param0 // MCU parameter 0
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,output [31 :0] mcu_param1 // MCU parameter 1
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,output [31 :0] mcu_param2 // MCU parameter 2
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,output [31 :0] mcu_param3 // MCU parameter 3
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,input [31 :0] mcu_result0 // MCU result 0
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,input [31 :0] mcu_result1 // MCU result 1
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,input [31 :0] mcu_result2 // MCU result 2
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,input [31 :0] mcu_result3 // MCU result 3
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,output [2 :0] fb_st_o
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//awg cfg
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,output mod_sel_sideband //1'b0:Upper sideband;1'b1:Lower sideband;
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//DSP cfg
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,output qam_nco_clr
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,output [47:0] qam_fcw/////////////////////////////////////////////////////////////////////////////
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,output [15:0] qam_pha /////////////////////////////////////////////////////////////////////////////
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,output [1 :0] qam_mod //2'b00:bypass;2'b01:mix;
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//2'b10:cos;2'b11:sin;
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,output qam_sel_sideband //1'b0:Upper sideband;1'b1:Lower sideband;
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,output [2 :0] intp_mode //3'b000:x1;3'b001:x2;3'b010:x4;
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//3'b011:x8;3'b100:x16;
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,output [1 :0] intp_sel //2'b00:HBF;2'b01:Nearest-neighbor interpolator;
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//2'b10:Median interpolator;2'b00:reserve;
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,output [1 :0] dac_mode_sel //2'b00:NRZ mode;2'b01:MIX mode;
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//2'b10:2xNRZ mode;2'b00:reserve;
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,output tc_bypass //1'b0:bypass;1'b1:enable;
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,output [31:0] tcparr0
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,output [31:0] tcparr1
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,output [31:0] tcparr2
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,output [31:0] tcparr3
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,output [31:0] tcparr4
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,output [31:0] tcparr5
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,output [31:0] tcpbrr0
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,output [31:0] tcpbrr1
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,output [31:0] tcpbrr2
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,output [31:0] tcpbrr3
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,output [31:0] tcpbrr4
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,output [31:0] tcpbrr5
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,output [31:0] tcpair0
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,output [31:0] tcpair1
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,output [31:0] tcpair2
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,output [31:0] tcpair3
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,output [31:0] tcpair4
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,output [31:0] tcpair5
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,output [31:0] tcpbir0
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,output [31:0] tcpbir1
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,output [31:0] tcpbir2
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,output [31:0] tcpbir3
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,output [31:0] tcpbir4
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,output [31:0] tcpbir5
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);
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localparam L = 1'b0,
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H = 1'b1;
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// ------------------------------------------------------
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// -- Register enable (select) wires
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// ------------------------------------------------------
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wire mcuparar0en ; // MCUPARAR0 select
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wire mcuparar1en ; // MCUPARAR1 select
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wire mcuparar2en ; // MCUPARAR2 select
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wire mcuparar3en ; // MCUPARAR3 select
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wire mcuresr0en ; // MCURESR0 select
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wire mcuresr1en ; // MCURESR1 select
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wire mcuresr2en ; // MCURESR2 select
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wire mcuresr3en ; // MCURESR3 select
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wire rtimren ; // RTIMR select
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wire icntren ; // ICNTR select
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wire fsiren ; // FSIR select
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wire modmren ; // MODMR select
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wire intpmren ; // INTPMR select
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wire mixncocren ; // MIXNCOCR select
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wire mixnfcwhren ; // MIXNFCWHR select
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wire mixnfcwlren ; // MIXNFCWLR select
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wire mixnpharen ; // MIXNPHAR select
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wire mixmren ; // MIXMR select
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wire mixodtren ; // MIXODTR select
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wire mixodfren ; // MIXODFR select
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wire intpselren ; // INTPSELR select
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wire tcbpren ; // TCBPR select
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wire tcparr0en ; // TCPARR0 select
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wire tcparr1en ; // TCPARR1 select
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wire tcparr2en ; // TCPARR2 select
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wire tcparr3en ; // TCPARR3 select
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wire tcparr4en ; // TCPARR4 select
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wire tcparr5en ; // TCPARR5 select
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wire tcpbrr0en ; // TCPBRR0 select
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wire tcpbrr1en ; // TCPBRR1 select
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wire tcpbrr2en ; // TCPBRR2 select
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wire tcpbrr3en ; // TCPBRR3 select
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wire tcpbrr4en ; // TCPBRR4 select
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wire tcpbrr5en ; // TCPBRR5 select
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wire tcpair0en ; // TCPAIR0 select
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wire tcpair1en ; // TCPAIR1 select
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wire tcpair2en ; // TCPAIR2 select
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wire tcpair3en ; // TCPAIR3 select
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wire tcpair4en ; // TCPAIR4 select
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wire tcpair5en ; // TCPAIR5 select
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wire tcpbir0en ; // TCPBIR0 select
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wire tcpbir1en ; // TCPBIR1 select
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wire tcpbir2en ; // TCPBIR2 select
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wire tcpbir3en ; // TCPBIR3 select
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wire tcpbir4en ; // TCPBIR4 select
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wire tcpbir5en ; // TCPBIR5 select
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// ------------------------------------------------------
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// -- Register write enable wires
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// ------------------------------------------------------
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wire mcuparar0we ; // MCUPARAR0 write enable
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wire mcuparar1we ; // MCUPARAR1 write enable
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wire mcuparar2we ; // MCUPARAR2 write enable
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wire mcuparar3we ; // MCUPARAR3 write enable
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wire intpmrwe ; // INTPMR write enable
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wire mixncocrwe ; // MIXNCOCR write enable
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wire mixnfcwhrwe ; // MIXNFCWHR write enable
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wire mixnfcwlrwe ; // MIXNFCWLR write enable
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wire mixnpharwe ; // MIXNPHAR write enable
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wire mixmrwe ; // MIXMR write enable
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wire mixodtrwe ; // MIXODTR write enable
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wire mixodfrwe ; // MIXODFR write enable
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wire intpselrwe ; // INTPSELR write enable
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wire tcbprwe ; // TCBPR write enable
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wire tcparr0we ; // TCPARR0 write enable
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wire tcparr1we ; // TCPARR1 write enable
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wire tcparr2we ; // TCPARR2 write enable
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wire tcparr3we ; // TCPARR3 write enable
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wire tcparr4we ; // TCPARR4 write enable
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wire tcparr5we ; // TCPARR5 write enable
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wire tcpbrr0we ; // TCPBRR0 write enable
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wire tcpbrr1we ; // TCPBRR1 write enable
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wire tcpbrr2we ; // TCPBRR2 write enable
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wire tcpbrr3we ; // TCPBRR3 write enable
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wire tcpbrr4we ; // TCPBRR4 write enable
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wire tcpbrr5we ; // TCPBRR5 write enable
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wire tcpair0we ; // TCPAIR0 write enable
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wire tcpair1we ; // TCPAIR1 write enable
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wire tcpair2we ; // TCPAIR2 write enable
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wire tcpair3we ; // TCPAIR3 write enable
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wire tcpair4we ; // TCPAIR4 write enable
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wire tcpair5we ; // TCPAIR5 write enable
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wire tcpbir0we ; // TCPBIR0 write enable
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wire tcpbir1we ; // TCPBIR1 write enable
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wire tcpbir2we ; // TCPBIR2 write enable
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wire tcpbir3we ; // TCPBIR3 write enable
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wire tcpbir4we ; // TCPBIR4 write enable
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wire tcpbir5we ; // TCPBIR5 write enable
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// ------------------------------------------------------
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// -- Misc wires
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// ------------------------------------------------------
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// ------------------------------------------------------
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// -- Misc Registers
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// ------------------------------------------------------
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reg [31 :0] mcuparar0 ; // MCUPARAR0 register
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reg [31 :0] mcuparar1 ; // MCUPARAR1 register
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reg [31 :0] mcuparar2 ; // MCUPARAR2 register
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reg [31 :0] mcuparar3 ; // MCUPARAR3 register
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reg [31 :0] mcuresr0 ; // MCURESR0 register
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reg [31 :0] mcuresr1 ; // MCURESR1 register
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reg [31 :0] mcuresr2 ; // MCURESR2 register
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reg [31 :0] mcuresr3 ; // MCURESR3 register
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reg [31 :0] rtimr ; // RTIMR register
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reg [31 :0] icntr ; // ICNTR register
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reg [1 :0] fsir ; // FSIR register
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reg [0 :0] modmr ; // MODMR register
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reg [2 :0] intpmr ; // INTPMR register
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reg [0 :0] mixncocr ; // MIXNCOCR register
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reg [31 :0] mixnfcwhr ; // MIXNFCWHR register
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reg [15 :0] mixnfcwlr ; // MIXNFCWLR register
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reg [15 :0] mixnphar ; // MIXNPHAR register
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reg [0 :0] mixmr ; // MIXMR register
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reg [1 :0] mixodtr ; // MIXODTR register
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reg [1 :0] mixodfr ; // MIXODFR register
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reg [1 :0] intpselr ; // INTPSELR register
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reg [0 :0] tcbpr ; // TCBPR register
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reg [31 :0] tcparr0 ; // TCPARR0 register
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reg [31 :0] tcparr1 ; // TCPARR1 register
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reg [31 :0] tcparr2 ; // TCPARR2 register
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reg [31 :0] tcparr3 ; // TCPARR3 register
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reg [31 :0] tcparr4 ; // TCPARR4 register
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reg [31 :0] tcparr5 ; // TCPARR5 register
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||
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reg [31 :0] tcpbrr0 ; // TCPBRR0 register
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||
|
|
reg [31 :0] tcpbrr1 ; // TCPBRR1 register
|
||
|
|
reg [31 :0] tcpbrr2 ; // TCPBRR2 register
|
||
|
|
reg [31 :0] tcpbrr3 ; // TCPBRR3 register
|
||
|
|
reg [31 :0] tcpbrr4 ; // TCPBRR4 register
|
||
|
|
reg [31 :0] tcpbrr5 ; // TCPBRR5 register
|
||
|
|
reg [31 :0] tcpair0 ; // TCPAIR0 register
|
||
|
|
reg [31 :0] tcpair1 ; // TCPAIR1 register
|
||
|
|
reg [31 :0] tcpair2 ; // TCPAIR2 register
|
||
|
|
reg [31 :0] tcpair3 ; // TCPAIR3 register
|
||
|
|
reg [31 :0] tcpair4 ; // TCPAIR4 register
|
||
|
|
reg [31 :0] tcpair5 ; // TCPAIR5 register
|
||
|
|
reg [31 :0] tcpbir0 ; // TCPBIR0 register
|
||
|
|
reg [31 :0] tcpbir1 ; // TCPBIR1 register
|
||
|
|
reg [31 :0] tcpbir2 ; // TCPBIR2 register
|
||
|
|
reg [31 :0] tcpbir3 ; // TCPBIR3 register
|
||
|
|
reg [31 :0] tcpbir4 ; // TCPBIR4 register
|
||
|
|
reg [31 :0] tcpbir5 ; // TCPBIR5 register
|
||
|
|
|
||
|
|
reg [31: 0] rddata_reg ;
|
||
|
|
|
||
|
|
// ------------------------------------------------------
|
||
|
|
// -- Address decoder
|
||
|
|
//
|
||
|
|
// Decodes the register address offset input(reg_addr)
|
||
|
|
// to produce enable (select) signals for each of the
|
||
|
|
// SW-registers in the macrocell. The reg_addr input
|
||
|
|
// is bits [15:0] of the paddr bus.
|
||
|
|
// ------------------------------------------------------
|
||
|
|
assign mcuparar0en = (rwaddr[15:2] == `MCUPARAR0 >> 2) ? 1'b1 : 1'b0;
|
||
|
|
assign mcuparar1en = (rwaddr[15:2] == `MCUPARAR1 >> 2) ? 1'b1 : 1'b0;
|
||
|
|
assign mcuparar2en = (rwaddr[15:2] == `MCUPARAR2 >> 2) ? 1'b1 : 1'b0;
|
||
|
|
assign mcuparar3en = (rwaddr[15:2] == `MCUPARAR3 >> 2) ? 1'b1 : 1'b0;
|
||
|
|
assign mcuresr0en = (rwaddr[15:2] == `MCURESR0 >> 2) ? 1'b1 : 1'b0;
|
||
|
|
assign mcuresr1en = (rwaddr[15:2] == `MCURESR1 >> 2) ? 1'b1 : 1'b0;
|
||
|
|
assign mcuresr2en = (rwaddr[15:2] == `MCURESR2 >> 2) ? 1'b1 : 1'b0;
|
||
|
|
assign mcuresr3en = (rwaddr[15:2] == `MCURESR3 >> 2) ? 1'b1 : 1'b0;
|
||
|
|
assign rtimren = (rwaddr[15:2] == `RTIMR >> 2) ? 1'b1 : 1'b0;
|
||
|
|
assign icntren = (rwaddr[15:2] == `ICNTR >> 2) ? 1'b1 : 1'b0;
|
||
|
|
assign fsiren = (rwaddr[15:2] == `FSIR >> 2) ? 1'b1 : 1'b0;
|
||
|
|
assign modmren = (rwaddr[15:2] == `MODMR >> 2) ? 1'b1 : 1'b0;
|
||
|
|
assign intpmren = (rwaddr[15:2] == `INTPMR >> 2) ? 1'b1 : 1'b0;
|
||
|
|
assign mixncocren = (rwaddr[15:2] == `MIXNCOCR >> 2) ? 1'b1 : 1'b0;
|
||
|
|
assign mixnfcwhren = (rwaddr[15:2] == `MIXNFCWHR >> 2) ? 1'b1 : 1'b0;
|
||
|
|
assign mixnfcwlren = (rwaddr[15:2] == `MIXNFCWLR >> 2) ? 1'b1 : 1'b0;
|
||
|
|
assign mixnpharen = (rwaddr[15:2] == `MIXNPHAR >> 2) ? 1'b1 : 1'b0;
|
||
|
|
assign mixmren = (rwaddr[15:2] == `MIXMR >> 2) ? 1'b1 : 1'b0;
|
||
|
|
assign mixodtren = (rwaddr[15:2] == `MIXODTR >> 2) ? 1'b1 : 1'b0;
|
||
|
|
assign mixodfren = (rwaddr[15:2] == `MIXODFR >> 2) ? 1'b1 : 1'b0;
|
||
|
|
assign intpselren = (rwaddr[15:2] == `INTPSELR >> 2) ? 1'b1 : 1'b0;
|
||
|
|
assign tcbpren = (rwaddr[15:2] == `TCBPR >> 2) ? 1'b1 : 1'b0;
|
||
|
|
assign tcparr0en = (rwaddr[15:2] == `TCPARR0 >> 2) ? 1'b1 : 1'b0;
|
||
|
|
assign tcparr1en = (rwaddr[15:2] == `TCPARR1 >> 2) ? 1'b1 : 1'b0;
|
||
|
|
assign tcparr2en = (rwaddr[15:2] == `TCPARR2 >> 2) ? 1'b1 : 1'b0;
|
||
|
|
assign tcparr3en = (rwaddr[15:2] == `TCPARR3 >> 2) ? 1'b1 : 1'b0;
|
||
|
|
assign tcparr4en = (rwaddr[15:2] == `TCPARR4 >> 2) ? 1'b1 : 1'b0;
|
||
|
|
assign tcparr5en = (rwaddr[15:2] == `TCPARR5 >> 2) ? 1'b1 : 1'b0;
|
||
|
|
assign tcpbrr0en = (rwaddr[15:2] == `TCPBRR0 >> 2) ? 1'b1 : 1'b0;
|
||
|
|
assign tcpbrr1en = (rwaddr[15:2] == `TCPBRR1 >> 2) ? 1'b1 : 1'b0;
|
||
|
|
assign tcpbrr2en = (rwaddr[15:2] == `TCPBRR2 >> 2) ? 1'b1 : 1'b0;
|
||
|
|
assign tcpbrr3en = (rwaddr[15:2] == `TCPBRR3 >> 2) ? 1'b1 : 1'b0;
|
||
|
|
assign tcpbrr4en = (rwaddr[15:2] == `TCPBRR4 >> 2) ? 1'b1 : 1'b0;
|
||
|
|
assign tcpbrr5en = (rwaddr[15:2] == `TCPBRR5 >> 2) ? 1'b1 : 1'b0;
|
||
|
|
assign tcpair0en = (rwaddr[15:2] == `TCPAIR0 >> 2) ? 1'b1 : 1'b0;
|
||
|
|
assign tcpair1en = (rwaddr[15:2] == `TCPAIR1 >> 2) ? 1'b1 : 1'b0;
|
||
|
|
assign tcpair2en = (rwaddr[15:2] == `TCPAIR2 >> 2) ? 1'b1 : 1'b0;
|
||
|
|
assign tcpair3en = (rwaddr[15:2] == `TCPAIR3 >> 2) ? 1'b1 : 1'b0;
|
||
|
|
assign tcpair4en = (rwaddr[15:2] == `TCPAIR4 >> 2) ? 1'b1 : 1'b0;
|
||
|
|
assign tcpair5en = (rwaddr[15:2] == `TCPAIR5 >> 2) ? 1'b1 : 1'b0;
|
||
|
|
assign tcpbir0en = (rwaddr[15:2] == `TCPBIR0 >> 2) ? 1'b1 : 1'b0;
|
||
|
|
assign tcpbir1en = (rwaddr[15:2] == `TCPBIR1 >> 2) ? 1'b1 : 1'b0;
|
||
|
|
assign tcpbir2en = (rwaddr[15:2] == `TCPBIR2 >> 2) ? 1'b1 : 1'b0;
|
||
|
|
assign tcpbir3en = (rwaddr[15:2] == `TCPBIR3 >> 2) ? 1'b1 : 1'b0;
|
||
|
|
assign tcpbir4en = (rwaddr[15:2] == `TCPBIR4 >> 2) ? 1'b1 : 1'b0;
|
||
|
|
assign tcpbir5en = (rwaddr[15:2] == `TCPBIR5 >> 2) ? 1'b1 : 1'b0;
|
||
|
|
|
||
|
|
|
||
|
|
// ------------------------------------------------------
|
||
|
|
// -- Write enable signals
|
||
|
|
//
|
||
|
|
// Write enable signals for writable SW-registers.
|
||
|
|
// The write enable for each register is the ANDed
|
||
|
|
// result of the register enable and the input reg_wren
|
||
|
|
// ------------------------------------------------------
|
||
|
|
assign mcuparar0we = mcuparar0en & wren;
|
||
|
|
assign mcuparar1we = mcuparar1en & wren;
|
||
|
|
assign mcuparar2we = mcuparar2en & wren;
|
||
|
|
assign mcuparar3we = mcuparar3en & wren;
|
||
|
|
assign modmrwe = modmren & wren;///////////
|
||
|
|
assign intpmrwe = intpmren & wren;
|
||
|
|
assign mixncocrwe = mixncocren & wren;
|
||
|
|
assign mixnfcwhrwe = mixnfcwhren & wren;
|
||
|
|
assign mixnfcwlrwe = mixnfcwlren & wren;
|
||
|
|
assign mixnpharwe = mixnpharen & wren;
|
||
|
|
assign mixmrwe = mixmren & wren;
|
||
|
|
assign mixodtrwe = mixodtren & wren;
|
||
|
|
assign mixodfrwe = mixodfren & wren;
|
||
|
|
assign intpselrwe = intpselren & wren;
|
||
|
|
assign tcbprwe = tcbpren & wren;
|
||
|
|
assign tcparr0we = tcparr0en & wren;
|
||
|
|
assign tcparr1we = tcparr1en & wren;
|
||
|
|
assign tcparr2we = tcparr2en & wren;
|
||
|
|
assign tcparr3we = tcparr3en & wren;
|
||
|
|
assign tcparr4we = tcparr4en & wren;
|
||
|
|
assign tcparr5we = tcparr5en & wren;
|
||
|
|
assign tcpbrr0we = tcpbrr0en & wren;
|
||
|
|
assign tcpbrr1we = tcpbrr1en & wren;
|
||
|
|
assign tcpbrr2we = tcpbrr2en & wren;
|
||
|
|
assign tcpbrr3we = tcpbrr3en & wren;
|
||
|
|
assign tcpbrr4we = tcpbrr4en & wren;
|
||
|
|
assign tcpbrr5we = tcpbrr5en & wren;
|
||
|
|
assign tcpair0we = tcpair0en & wren;
|
||
|
|
assign tcpair1we = tcpair1en & wren;
|
||
|
|
assign tcpair2we = tcpair2en & wren;
|
||
|
|
assign tcpair3we = tcpair3en & wren;
|
||
|
|
assign tcpair4we = tcpair4en & wren;
|
||
|
|
assign tcpair5we = tcpair5en & wren;
|
||
|
|
assign tcpbir0we = tcpbir0en & wren;
|
||
|
|
assign tcpbir1we = tcpbir1en & wren;
|
||
|
|
assign tcpbir2we = tcpbir2en & wren;
|
||
|
|
assign tcpbir3we = tcpbir3en & wren;
|
||
|
|
assign tcpbir4we = tcpbir4en & wren;
|
||
|
|
assign tcpbir5we = tcpbir5en & wren;
|
||
|
|
|
||
|
|
// ------------------------------------------------------
|
||
|
|
// -- mcuparar0 register
|
||
|
|
//
|
||
|
|
// Write mcuparar0 for 'MCUPARAR0' : 32-bit register
|
||
|
|
// Register is split into the following bit fields
|
||
|
|
//
|
||
|
|
// [31:0] --> mcuparar0
|
||
|
|
// ------------------------------------------------------
|
||
|
|
sirv_gnrl_dfflr #(32) mcuparar0_dfflr (mcuparar0we, wrdata[31:0], mcuparar0, clk, rst_n);
|
||
|
|
|
||
|
|
// ------------------------------------------------------
|
||
|
|
// -- mcuparar1 register
|
||
|
|
//
|
||
|
|
// Write mcuparar1 for 'MCUPARAR1' : 32-bit register
|
||
|
|
// Register is split into the following bit fields
|
||
|
|
//
|
||
|
|
// [31:0] --> mcuparar1
|
||
|
|
// ------------------------------------------------------
|
||
|
|
sirv_gnrl_dfflr #(32) mcuparar1_dfflr (mcuparar1we, wrdata[31:0], mcuparar1, clk, rst_n);
|
||
|
|
|
||
|
|
// ------------------------------------------------------
|
||
|
|
// -- mcuparar2 register
|
||
|
|
//
|
||
|
|
// Write mcuparar2 for 'MCUPARAR2' : 32-bit register
|
||
|
|
// Register is split into the following bit fields
|
||
|
|
//
|
||
|
|
// [31:0] --> mcuparar2
|
||
|
|
// ------------------------------------------------------
|
||
|
|
sirv_gnrl_dfflr #(32) mcuparar2_dfflr (mcuparar2we, wrdata[31:0], mcuparar2, clk, rst_n);
|
||
|
|
|
||
|
|
// ------------------------------------------------------
|
||
|
|
// -- mcuparar3 register
|
||
|
|
//
|
||
|
|
// Write mcuparar3 for 'MCUPARAR3' : 32-bit register
|
||
|
|
// Register is split into the following bit fields
|
||
|
|
//
|
||
|
|
// [31:0] --> mcuparar3
|
||
|
|
// ------------------------------------------------------
|
||
|
|
sirv_gnrl_dfflr #(32) mcuparar3_dfflr (mcuparar3we, wrdata[31:0], mcuparar3, clk, rst_n);
|
||
|
|
|
||
|
|
// ------------------------------------------------------
|
||
|
|
// -- modmr register
|
||
|
|
//
|
||
|
|
// Write modmr for 'MODMR' : 32-bit register
|
||
|
|
// Register is split into the following bit fields
|
||
|
|
//
|
||
|
|
// [0] --> modmr
|
||
|
|
// ------------------------------------------------------
|
||
|
|
sirv_gnrl_dfflr #(1) modmr_dfflr (modmrwe, wrdata[0], modmr, clk, rst_n);
|
||
|
|
|
||
|
|
// ------------------------------------------------------
|
||
|
|
// -- intpmr register
|
||
|
|
//
|
||
|
|
// Write intpmr for 'INTPMR' : 32-bit register
|
||
|
|
// Register is split into the following bit fields
|
||
|
|
//
|
||
|
|
// [2:0] --> intpmr
|
||
|
|
// ------------------------------------------------------
|
||
|
|
sirv_gnrl_dfflr #(3) intpmr_dfflr (intpmrwe, wrdata[2:0], intpmr, clk, rst_n);
|
||
|
|
|
||
|
|
// ------------------------------------------------------
|
||
|
|
// -- mixncocr register
|
||
|
|
//
|
||
|
|
// Write mixncocr for 'MIXNCOCR' : 32-bit register
|
||
|
|
// Register is split into the following bit fields
|
||
|
|
//
|
||
|
|
// [0] --> mixncocr
|
||
|
|
// ------------------------------------------------------
|
||
|
|
sirv_gnrl_dfflr #(1) mixncocr_dfflr (mixncocrwe, wrdata[0], mixncocr, clk, rst_n);
|
||
|
|
|
||
|
|
// ------------------------------------------------------
|
||
|
|
// -- mixnfcwhr register
|
||
|
|
//
|
||
|
|
// Write mixnfcwhr for 'MIXNFCWHR' : 32-bit register
|
||
|
|
// Register is split into the following bit fields
|
||
|
|
//
|
||
|
|
// [31:0] --> mixnfcwhr
|
||
|
|
// ------------------------------------------------------
|
||
|
|
sirv_gnrl_dfflr #(32) mixnfcwhr_dfflr (mixnfcwhrwe, wrdata[31:0], mixnfcwhr, clk, rst_n);
|
||
|
|
|
||
|
|
// ------------------------------------------------------
|
||
|
|
// -- mixnfcwlr register
|
||
|
|
//
|
||
|
|
// Write mixnfcwlr for 'MIXNFCWHR' : 32-bit register
|
||
|
|
// Register is split into the following bit fields
|
||
|
|
//
|
||
|
|
// [31:16] --> mixnfcwlr
|
||
|
|
// ------------------------------------------------------
|
||
|
|
sirv_gnrl_dfflr #(16) mixnfcwlr_dfflr (mixnfcwlrwe, wrdata[31:16], mixnfcwlr, clk, rst_n);
|
||
|
|
|
||
|
|
// ------------------------------------------------------
|
||
|
|
// -- mixnphar register
|
||
|
|
//
|
||
|
|
// Write mixnphar for 'MIXNPHAR' : 32-bit register
|
||
|
|
// Register is split into the following bit fields
|
||
|
|
//
|
||
|
|
// [31:16] --> mixnphar
|
||
|
|
// ------------------------------------------------------
|
||
|
|
sirv_gnrl_dfflr #(16) mixnphar_dfflr (mixnpharwe, wrdata[31:16], mixnphar, clk, rst_n);
|
||
|
|
|
||
|
|
// ------------------------------------------------------
|
||
|
|
// -- mixmr register
|
||
|
|
//
|
||
|
|
// Write mixmr for 'MIXNPHAR' : 32-bit register
|
||
|
|
// Register is split into the following bit fields
|
||
|
|
//
|
||
|
|
// [0] --> mixmr
|
||
|
|
// ------------------------------------------------------
|
||
|
|
sirv_gnrl_dfflr #(1) mixmr_dfflr (mixmrwe, wrdata[0], mixmr, clk, rst_n);
|
||
|
|
|
||
|
|
// ------------------------------------------------------
|
||
|
|
// -- mixodtr register
|
||
|
|
//
|
||
|
|
// Write mixodtr for 'MIXNPHAR' : 32-bit register
|
||
|
|
// Register is split into the following bit fields
|
||
|
|
//
|
||
|
|
// [1:0] --> mixodtr
|
||
|
|
// ------------------------------------------------------
|
||
|
|
sirv_gnrl_dfflr #(2) mixodtr_dfflr (mixodtrwe, wrdata[1:0], mixodtr, clk, rst_n);
|
||
|
|
|
||
|
|
// ------------------------------------------------------
|
||
|
|
// -- mixodfr register
|
||
|
|
//
|
||
|
|
// Write mixodfr for 'MIXODFR' : 32-bit register
|
||
|
|
// Register is split into the following bit fields
|
||
|
|
//
|
||
|
|
// [1:0] --> mixodfr
|
||
|
|
// ------------------------------------------------------
|
||
|
|
sirv_gnrl_dfflr #(2) mixodfr_dfflr (mixodfrwe, wrdata[1:0], mixodfr, clk, rst_n);
|
||
|
|
|
||
|
|
// ------------------------------------------------------
|
||
|
|
// -- intpselr register
|
||
|
|
//
|
||
|
|
// Write intpselr for 'INTPSELR' : 32-bit register
|
||
|
|
// Register is split into the following bit fields
|
||
|
|
//
|
||
|
|
// [1:0] --> intpselr
|
||
|
|
// ------------------------------------------------------
|
||
|
|
sirv_gnrl_dfflr #(2) intpselr_dfflr (intpselrwe, wrdata[1:0], intpselr, clk, rst_n);
|
||
|
|
|
||
|
|
// ------------------------------------------------------
|
||
|
|
// -- tcbpr register
|
||
|
|
//
|
||
|
|
// Write tcbpr for 'TCBPR' : 32-bit register
|
||
|
|
// Register is split into the following bit fields
|
||
|
|
//
|
||
|
|
// [0] --> tcbpr
|
||
|
|
// ------------------------------------------------------
|
||
|
|
sirv_gnrl_dfflr #(1) tcbpr_dfflr (tcbprwe, wrdata[0], tcbpr, clk, rst_n);
|
||
|
|
|
||
|
|
// ------------------------------------------------------
|
||
|
|
// -- tcparr0 register
|
||
|
|
//
|
||
|
|
// Write tcparr0 for 'TCPARR0' : 32-bit register
|
||
|
|
// Register is split into the following bit fields
|
||
|
|
//
|
||
|
|
// [31:0] --> tcparr0
|
||
|
|
// ------------------------------------------------------
|
||
|
|
sirv_gnrl_dfflr #(32) tcparr0_dfflr (tcparr0we, wrdata[31:0], tcparr0, clk, rst_n);
|
||
|
|
|
||
|
|
// ------------------------------------------------------
|
||
|
|
// -- tcparr1 register
|
||
|
|
//
|
||
|
|
// Write tcparr1 for 'TCPARR1' : 32-bit register
|
||
|
|
// Register is split into the following bit fields
|
||
|
|
//
|
||
|
|
// [0] --> tcparr1
|
||
|
|
// ------------------------------------------------------
|
||
|
|
sirv_gnrl_dfflr #(32) tcparr1_dfflr (tcparr1we, wrdata[31:0], tcparr1, clk, rst_n);////////
|
||
|
|
|
||
|
|
// ------------------------------------------------------
|
||
|
|
// -- tcparr2 register
|
||
|
|
//
|
||
|
|
// Write tcparr2 for 'TCPARR2' : 32-bit register
|
||
|
|
// Register is split into the following bit fields
|
||
|
|
//
|
||
|
|
// [31:0] --> tcparr2
|
||
|
|
// ------------------------------------------------------
|
||
|
|
sirv_gnrl_dfflr #(32) tcparr2_dfflr (tcparr2we, wrdata[31:0], tcparr2, clk, rst_n);
|
||
|
|
|
||
|
|
// ------------------------------------------------------
|
||
|
|
// -- tcparr3 register
|
||
|
|
//
|
||
|
|
// Write tcparr3 for 'TCPARR3' : 32-bit register
|
||
|
|
// Register is split into the following bit fields
|
||
|
|
//
|
||
|
|
// [31:0] --> tcparr3
|
||
|
|
// ------------------------------------------------------
|
||
|
|
sirv_gnrl_dfflr #(32) tcparr3_dfflr (tcparr3we, wrdata[31:0], tcparr3, clk, rst_n);
|
||
|
|
|
||
|
|
// ------------------------------------------------------
|
||
|
|
// -- tcparr4 register
|
||
|
|
//
|
||
|
|
// Write tcparr4 for 'TCPARR4' : 32-bit register
|
||
|
|
// Register is split into the following bit fields
|
||
|
|
//
|
||
|
|
// [31:0] --> tcparr4
|
||
|
|
// ------------------------------------------------------
|
||
|
|
sirv_gnrl_dfflr #(32) tcparr4_dfflr (tcparr4we, wrdata[31:0], tcparr4, clk, rst_n);
|
||
|
|
|
||
|
|
// ------------------------------------------------------
|
||
|
|
// -- tcparr5 register
|
||
|
|
//
|
||
|
|
// Write tcparr5 for 'TCPARR5' : 32-bit register
|
||
|
|
// Register is split into the following bit fields
|
||
|
|
//
|
||
|
|
// [31:0] --> tcparr5
|
||
|
|
// ------------------------------------------------------
|
||
|
|
sirv_gnrl_dfflr #(32) tcparr5_dfflr (tcparr5we, wrdata[31:0], tcparr5, clk, rst_n);
|
||
|
|
|
||
|
|
// ------------------------------------------------------
|
||
|
|
// -- tcpbrr0 register
|
||
|
|
//
|
||
|
|
// Write tcpbrr0 for 'tcpbrr0' : 32-bit register
|
||
|
|
// Register is split into the following bit fields
|
||
|
|
//
|
||
|
|
// [31:0] --> tcpbrr0
|
||
|
|
// ------------------------------------------------------
|
||
|
|
sirv_gnrl_dfflr #(32) tcpbrr0_dfflr (tcpbrr0we, wrdata[31:0], tcpbrr0, clk, rst_n);
|
||
|
|
|
||
|
|
// ------------------------------------------------------
|
||
|
|
// -- tcpbrr1 register
|
||
|
|
//
|
||
|
|
// Write tcpbrr1 for 'tcpbrr1' : 32-bit register
|
||
|
|
// Register is split into the following bit fields
|
||
|
|
//
|
||
|
|
// [0] --> tcpbrr1
|
||
|
|
// ------------------------------------------------------
|
||
|
|
sirv_gnrl_dfflr #(32) tcpbrr1_dfflr (tcpbrr1we, wrdata[31:0], tcpbrr1, clk, rst_n);////////////////////
|
||
|
|
|
||
|
|
// ------------------------------------------------------
|
||
|
|
// -- tcpbrr2 register
|
||
|
|
//
|
||
|
|
// Write tcpbrr2 for 'tcpbrr2' : 32-bit register
|
||
|
|
// Register is split into the following bit fields
|
||
|
|
//
|
||
|
|
// [31:0] --> tcpbrr2
|
||
|
|
// ------------------------------------------------------
|
||
|
|
sirv_gnrl_dfflr #(32) tcpbrr2_dfflr (tcpbrr2we, wrdata[31:0], tcpbrr2, clk, rst_n);
|
||
|
|
|
||
|
|
// ------------------------------------------------------
|
||
|
|
// -- tcpbrr3 register
|
||
|
|
//
|
||
|
|
// Write tcpbrr3 for 'tcpbrr3' : 32-bit register
|
||
|
|
// Register is split into the following bit fields
|
||
|
|
//
|
||
|
|
// [31:0] --> tcpbrr3
|
||
|
|
// ------------------------------------------------------
|
||
|
|
sirv_gnrl_dfflr #(32) tcpbrr3_dfflr (tcpbrr3we, wrdata[31:0], tcpbrr3, clk, rst_n);
|
||
|
|
|
||
|
|
// ------------------------------------------------------
|
||
|
|
// -- tcpbrr4 register
|
||
|
|
//
|
||
|
|
// Write tcpbrr4 for 'tcpbrr4' : 32-bit register
|
||
|
|
// Register is split into the following bit fields
|
||
|
|
//
|
||
|
|
// [31:0] --> tcpbrr4
|
||
|
|
// ------------------------------------------------------
|
||
|
|
sirv_gnrl_dfflr #(32) tcpbrr4_dfflr (tcpbrr4we, wrdata[31:0], tcpbrr4, clk, rst_n);
|
||
|
|
|
||
|
|
// ------------------------------------------------------
|
||
|
|
// -- tcpbrr5 register
|
||
|
|
//
|
||
|
|
// Write tcpbrr5 for 'tcpbrr5' : 32-bit register
|
||
|
|
// Register is split into the following bit fields
|
||
|
|
//
|
||
|
|
// [31:0] --> tcpbrr5
|
||
|
|
// ------------------------------------------------------
|
||
|
|
sirv_gnrl_dfflr #(32) tcpbrr5_dfflr (tcpbrr5we, wrdata[31:0], tcpbrr5, clk, rst_n);
|
||
|
|
|
||
|
|
// ------------------------------------------------------
|
||
|
|
// -- tcpair0 register
|
||
|
|
//
|
||
|
|
// Write tcpair0 for 'tcpair0' : 32-bit register
|
||
|
|
// Register is split into the following bit fields
|
||
|
|
//
|
||
|
|
// [31:0] --> tcpair0
|
||
|
|
// ------------------------------------------------------
|
||
|
|
sirv_gnrl_dfflr #(32) tcpair0_dfflr (tcpair0we, wrdata[31:0], tcpair0, clk, rst_n);
|
||
|
|
|
||
|
|
// ------------------------------------------------------
|
||
|
|
// -- tcpair1 register
|
||
|
|
//
|
||
|
|
// Write tcpair1 for 'tcpair1' : 32-bit register
|
||
|
|
// Register is split into the following bit fields
|
||
|
|
//
|
||
|
|
// [0] --> tcpair1
|
||
|
|
// ------------------------------------------------------
|
||
|
|
sirv_gnrl_dfflr #(32) tcpair1_dfflr (tcpair1we, wrdata[31:0], tcpair1, clk, rst_n);
|
||
|
|
|
||
|
|
// ------------------------------------------------------
|
||
|
|
// -- tcpair2 register
|
||
|
|
//
|
||
|
|
// Write tcpair2 for 'tcpair2' : 32-bit register
|
||
|
|
// Register is split into the following bit fields
|
||
|
|
//
|
||
|
|
// [31:0] --> tcpair2
|
||
|
|
// ------------------------------------------------------
|
||
|
|
sirv_gnrl_dfflr #(32) tcpair2_dfflr (tcpair2we, wrdata[31:0], tcpair2, clk, rst_n);
|
||
|
|
|
||
|
|
// ------------------------------------------------------
|
||
|
|
// -- tcpair3 register
|
||
|
|
//
|
||
|
|
// Write tcpair3 for 'tcpair3' : 32-bit register
|
||
|
|
// Register is split into the following bit fields
|
||
|
|
//
|
||
|
|
// [31:0] --> tcpair3
|
||
|
|
// ------------------------------------------------------
|
||
|
|
sirv_gnrl_dfflr #(32) tcpair3_dfflr (tcpair3we, wrdata[31:0], tcpair3, clk, rst_n);
|
||
|
|
|
||
|
|
// ------------------------------------------------------
|
||
|
|
// -- tcpair4 register
|
||
|
|
//
|
||
|
|
// Write tcpair4 for 'tcpair4' : 32-bit register
|
||
|
|
// Register is split into the following bit fields
|
||
|
|
//
|
||
|
|
// [31:0] --> tcpair4
|
||
|
|
// ------------------------------------------------------
|
||
|
|
sirv_gnrl_dfflr #(32) tcpair4_dfflr (tcpair4we, wrdata[31:0], tcpair4, clk, rst_n);
|
||
|
|
|
||
|
|
// ------------------------------------------------------
|
||
|
|
// -- tcpair5 register
|
||
|
|
//
|
||
|
|
// Write tcpair5 for 'tcpair5' : 32-bit register
|
||
|
|
// Register is split into the following bit fields
|
||
|
|
//
|
||
|
|
// [31:0] --> tcpair5
|
||
|
|
// ------------------------------------------------------
|
||
|
|
sirv_gnrl_dfflr #(32) tcpair5_dfflr (tcpair5we, wrdata[31:0], tcpair5, clk, rst_n);
|
||
|
|
|
||
|
|
// ------------------------------------------------------
|
||
|
|
// -- tcpbir0 register
|
||
|
|
//
|
||
|
|
// Write tcpbir0 for 'tcpbir0' : 32-bit register
|
||
|
|
// Register is split into the following bit fields
|
||
|
|
//
|
||
|
|
// [31:0] --> tcpbir0
|
||
|
|
// ------------------------------------------------------
|
||
|
|
sirv_gnrl_dfflr #(32) tcpbir0_dfflr (tcpbir0we, wrdata[31:0], tcpbir0, clk, rst_n);
|
||
|
|
|
||
|
|
// ------------------------------------------------------
|
||
|
|
// -- tcpbir1 register
|
||
|
|
//
|
||
|
|
// Write tcpbir1 for 'tcpbir1' : 32-bit register
|
||
|
|
// Register is split into the following bit fields
|
||
|
|
//
|
||
|
|
// [0] --> tcpbir1
|
||
|
|
// ------------------------------------------------------
|
||
|
|
sirv_gnrl_dfflr #(32) tcpbir1_dfflr (tcpbir1we, wrdata[31:0], tcpbir1, clk, rst_n);//////////
|
||
|
|
|
||
|
|
// ------------------------------------------------------
|
||
|
|
// -- tcpbir2 register
|
||
|
|
//
|
||
|
|
// Write tcpbir2 for 'tcpbir2' : 32-bit register
|
||
|
|
// Register is split into the following bit fields
|
||
|
|
//
|
||
|
|
// [31:0] --> tcpbir2
|
||
|
|
// ------------------------------------------------------
|
||
|
|
sirv_gnrl_dfflr #(32) tcpbir2_dfflr (tcpbir2we, wrdata[31:0], tcpbir2, clk, rst_n);
|
||
|
|
|
||
|
|
// ------------------------------------------------------
|
||
|
|
// -- tcpbir3 register
|
||
|
|
//
|
||
|
|
// Write tcpbir3 for 'tcpbir3' : 32-bit register
|
||
|
|
// Register is split into the following bit fields
|
||
|
|
//
|
||
|
|
// [31:0] --> tcpbir3
|
||
|
|
// ------------------------------------------------------
|
||
|
|
sirv_gnrl_dfflr #(32) tcpbir3_dfflr (tcpbir3we, wrdata[31:0], tcpbir3, clk, rst_n);
|
||
|
|
|
||
|
|
// ------------------------------------------------------
|
||
|
|
// -- tcpbir4 register
|
||
|
|
//
|
||
|
|
// Write tcpbir4 for 'tcpbir4' : 32-bit register
|
||
|
|
// Register is split into the following bit fields
|
||
|
|
//
|
||
|
|
// [31:0] --> tcpbir4
|
||
|
|
// ------------------------------------------------------
|
||
|
|
sirv_gnrl_dfflr #(32) tcpbir4_dfflr (tcpbir4we, wrdata[31:0], tcpbir4, clk, rst_n);
|
||
|
|
|
||
|
|
// ------------------------------------------------------
|
||
|
|
// -- tcpbir5 register
|
||
|
|
//
|
||
|
|
// Write tcpbir5 for 'tcpbir5' : 32-bit register
|
||
|
|
// Register is split into the following bit fields
|
||
|
|
//
|
||
|
|
// [31:0] --> tcpbir5
|
||
|
|
// ------------------------------------------------------
|
||
|
|
sirv_gnrl_dfflr #(32) tcpbir5_dfflr (tcpbir5we, wrdata[31:0], tcpbir5, clk, rst_n);
|
||
|
|
|
||
|
|
// ------------------------------------------------------
|
||
|
|
// -- mcuresr0
|
||
|
|
// ------------------------------------------------------
|
||
|
|
sirv_gnrl_dffr #(32) mcuparar0_dffr (mcu_result0, mcuresr0, clk, rst_n);
|
||
|
|
// ------------------------------------------------------
|
||
|
|
// -- mcuresr1
|
||
|
|
// ------------------------------------------------------
|
||
|
|
sirv_gnrl_dffr #(32) mcuparar1_dffr (mcu_result1, mcuresr1, clk, rst_n);
|
||
|
|
// ------------------------------------------------------
|
||
|
|
// -- mcuresr2
|
||
|
|
// ------------------------------------------------------
|
||
|
|
sirv_gnrl_dffr #(32) mcuparar2_dffr (mcu_result2, mcuresr2, clk, rst_n);
|
||
|
|
// ------------------------------------------------------
|
||
|
|
// -- mcuresr3
|
||
|
|
// ------------------------------------------------------
|
||
|
|
sirv_gnrl_dffr #(32) mcuparar3_dffr (mcu_result3, mcuresr3, clk, rst_n);
|
||
|
|
|
||
|
|
// ------------------------------------------------------
|
||
|
|
// -- rtimr
|
||
|
|
// ------------------------------------------------------
|
||
|
|
sirv_gnrl_dffr #(32) rtimr_dffr (run_time, rtimr, clk, rst_n);
|
||
|
|
|
||
|
|
// ------------------------------------------------------
|
||
|
|
// -- icntr
|
||
|
|
// ------------------------------------------------------
|
||
|
|
sirv_gnrl_dffr #(32) icntr_dffr (instr_num, icntr, clk, rst_n);
|
||
|
|
|
||
|
|
// ------------------------------------------------------
|
||
|
|
// -- fsir
|
||
|
|
// ------------------------------------------------------
|
||
|
|
sirv_gnrl_dffr #(2) fsir_dffr (fb_st_i, fsir, clk, rst_n);
|
||
|
|
|
||
|
|
// ------------------------------------------------------
|
||
|
|
// -- Read data mux
|
||
|
|
//
|
||
|
|
// -- The data from the selected register is
|
||
|
|
// -- placed on a zero-padded 32-bit read data bus.
|
||
|
|
// ------------------------------------------------------
|
||
|
|
always @(*) begin : RDDATA_PROC
|
||
|
|
rddata_reg = {32{1'b0}};
|
||
|
|
if(mcuparar0en == H ) rddata_reg[31:0] = mcuparar0 ;
|
||
|
|
if(mcuparar1en == H ) rddata_reg[31:0] = mcuparar1 ;
|
||
|
|
if(mcuparar2en == H ) rddata_reg[31:0] = mcuparar2 ;
|
||
|
|
if(mcuparar3en == H ) rddata_reg[31:0] = mcuparar3 ;
|
||
|
|
if(mcuresr0en == H ) rddata_reg[31:0] = mcuresr0 ;
|
||
|
|
if(mcuresr1en == H ) rddata_reg[31:0] = mcuresr1 ;
|
||
|
|
if(mcuresr2en == H ) rddata_reg[31:0] = mcuresr2 ;
|
||
|
|
if(mcuresr3en == H ) rddata_reg[31:0] = mcuresr3 ;
|
||
|
|
if(rtimren == H ) rddata_reg[31:0] = rtimr ;
|
||
|
|
if(icntren == H ) rddata_reg[31:0] = icntr ;
|
||
|
|
if(fsiren == H ) rddata_reg[1 :0] = fsir ;
|
||
|
|
if(modmren == H ) rddata_reg[0 :0] = modmr ;
|
||
|
|
if(intpmren == H ) rddata_reg[2 :0] = intpmr ;
|
||
|
|
if(mixncocren == H ) rddata_reg[0 :0] = mixncocr ;
|
||
|
|
if(mixnfcwhren == H ) rddata_reg[31:0] = mixnfcwhr ;
|
||
|
|
if(mixnfcwlren == H ) rddata_reg[15:0] = mixnfcwlr ;
|
||
|
|
if(mixnpharen == H ) rddata_reg[15:0] = mixnphar ;
|
||
|
|
if(mixmren == H ) rddata_reg[0 :0] = mixmr ;
|
||
|
|
if(mixodtren == H ) rddata_reg[1 :0] = mixodtr ;
|
||
|
|
if(mixodfren == H ) rddata_reg[1 :0] = mixodfr ;
|
||
|
|
if(intpselren == H ) rddata_reg[1 :0] = intpselr ;
|
||
|
|
if(tcbpren == H ) rddata_reg[0 :0] = tcbpr ;
|
||
|
|
if(tcparr0en == H ) rddata_reg[31:0] = tcparr0 ;
|
||
|
|
if(tcparr1en == H ) rddata_reg[31:0] = tcparr1 ;
|
||
|
|
if(tcparr2en == H ) rddata_reg[31:0] = tcparr2 ;
|
||
|
|
if(tcparr3en == H ) rddata_reg[31:0] = tcparr3 ;
|
||
|
|
if(tcparr4en == H ) rddata_reg[31:0] = tcparr4 ;
|
||
|
|
if(tcparr5en == H ) rddata_reg[31:0] = tcparr5 ;
|
||
|
|
if(tcpbrr0en == H ) rddata_reg[31:0] = tcpbrr0 ;
|
||
|
|
if(tcpbrr1en == H ) rddata_reg[31:0] = tcpbrr1 ;
|
||
|
|
if(tcpbrr2en == H ) rddata_reg[31:0] = tcpbrr2 ;
|
||
|
|
if(tcpbrr3en == H ) rddata_reg[31:0] = tcpbrr3 ;
|
||
|
|
if(tcpbrr4en == H ) rddata_reg[31 :0] = tcpbrr4 ;/////////
|
||
|
|
if(tcpbrr5en == H ) rddata_reg[31:0] = tcpbrr5 ;
|
||
|
|
if(tcpair0en == H ) rddata_reg[31:0] = tcpair0 ;
|
||
|
|
if(tcpair1en == H ) rddata_reg[31:0] = tcpair1 ;
|
||
|
|
if(tcpair2en == H ) rddata_reg[31:0] = tcpair2 ;
|
||
|
|
if(tcpair3en == H ) rddata_reg[31:0] = tcpair3 ;
|
||
|
|
if(tcpair4en == H ) rddata_reg[31:0] = tcpair4 ;
|
||
|
|
if(tcpair5en == H ) rddata_reg[31:0] = tcpair5 ;
|
||
|
|
if(tcpbir0en == H ) rddata_reg[31:0] = tcpbir0 ;
|
||
|
|
if(tcpbir1en == H ) rddata_reg[31:0] = tcpbir1 ;
|
||
|
|
if(tcpbir2en == H ) rddata_reg[31:0] = tcpbir2 ;
|
||
|
|
if(tcpbir3en == H ) rddata_reg[31 :0] = tcpbir3 ;////////
|
||
|
|
if(tcpbir4en == H ) rddata_reg[31:0] = tcpbir4 ;
|
||
|
|
if(tcpbir5en == H ) rddata_reg[31:0] = tcpbir5 ;
|
||
|
|
end
|
||
|
|
|
||
|
|
// ------------------------------------------------------
|
||
|
|
// -- Output signals assignment
|
||
|
|
// ------------------------------------------------------
|
||
|
|
//mcu result
|
||
|
|
assign mcu_param0 = mcuparar0 ;
|
||
|
|
assign mcu_param1 = mcuparar1 ;
|
||
|
|
assign mcu_param2 = mcuparar2 ;
|
||
|
|
assign mcu_param3 = mcuparar3 ;
|
||
|
|
|
||
|
|
//fb_st_o
|
||
|
|
assign fb_st_o = fsir ;
|
||
|
|
//awg cfg
|
||
|
|
assign mod_sel_sideband = modmr ;
|
||
|
|
//DSP cfg
|
||
|
|
assign qam_nco_clr = mixncocr ;
|
||
|
|
assign qam_fcw = {mixnfcwhr,mixnfcwlr} ;
|
||
|
|
assign qam_pha = mixnphar ;
|
||
|
|
assign qam_mod = mixodtr ;
|
||
|
|
assign qam_sel_sideband = mixmr ;
|
||
|
|
assign intp_mode = intpmr ;
|
||
|
|
assign intp_sel = intpselr ;
|
||
|
|
assign dac_mode_sel = mixodfr ;
|
||
|
|
assign tc_bypass = tcbpr ;//////////////////////////////////////////////////////////////////////////////////
|
||
|
|
|
||
|
|
//rddata
|
||
|
|
sirv_gnrl_dffr #(32) rddata_dffr (rddata_reg, rddata, clk, rst_n);
|
||
|
|
endmodule
|
||
|
|
|
||
|
|
`undef MCUPARAR0
|
||
|
|
`undef MCUPARAR1
|
||
|
|
`undef MCUPARAR2
|
||
|
|
`undef MCUPARAR3
|
||
|
|
`undef MCURESR0
|
||
|
|
`undef MCURESR1
|
||
|
|
`undef MCURESR2
|
||
|
|
`undef MCURESR3
|
||
|
|
`undef RTIMR
|
||
|
|
`undef ICNTR
|
||
|
|
`undef FSIR
|
||
|
|
`undef MODMR
|
||
|
|
`undef INTPMR
|
||
|
|
`undef MIXNCOCR
|
||
|
|
`undef MIXNFCWHR
|
||
|
|
`undef MIXNFCWLR
|
||
|
|
`undef MIXNPHAR
|
||
|
|
`undef MIXMR
|
||
|
|
`undef MIXODTR
|
||
|
|
`undef MIXODFR
|
||
|
|
`undef INTPSELR
|
||
|
|
`undef TCBPR
|
||
|
|
`undef TCPARR0
|
||
|
|
`undef TCPARR1
|
||
|
|
`undef TCPARR2
|
||
|
|
`undef TCPARR3
|
||
|
|
`undef TCPARR4
|
||
|
|
`undef TCPARR5
|
||
|
|
`undef TCPBRR0
|
||
|
|
`undef TCPBRR1
|
||
|
|
`undef TCPBRR2
|
||
|
|
`undef TCPBRR3
|
||
|
|
`undef TCPBRR4
|
||
|
|
`undef TCPBRR5
|
||
|
|
`undef TCPAIR0
|
||
|
|
`undef TCPAIR1
|
||
|
|
`undef TCPAIR2
|
||
|
|
`undef TCPAIR3
|
||
|
|
`undef TCPAIR4
|
||
|
|
`undef TCPAIR5
|
||
|
|
`undef TCPAIR0
|
||
|
|
`undef TCPBIR1
|
||
|
|
`undef TCPBIR2
|
||
|
|
`undef TCPBIR3
|
||
|
|
`undef TCPBIR4
|
||
|
|
`undef TCPBIR5
|