111 lines
2.6 KiB
Systemverilog
111 lines
2.6 KiB
Systemverilog
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class sysreg_trans;
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rand int status_time[32] ;
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rand bit dbg_enable ;
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rand bit dbg_data_sel ;
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rand bit[1:0] dbg_ch_sel ;
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rand bit irq ;
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constraint cstr {
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status_time[ 0] <= 5000 ;
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status_time[ 1] <= 5000 ;
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status_time[ 2] <= 5000 ;
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status_time[ 3] <= 5000 ;
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status_time[ 4] == 5000 ;
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status_time[ 5] == 5000 ;
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status_time[ 6] == 5000 ;
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status_time[ 7] == 5000 ;
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status_time[ 8] <= 5000 ;
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status_time[ 9] <= 5000 ;
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status_time[10] <= 5000 ;
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status_time[11] <= 5000 ;
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status_time[12] == 5000 ;
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status_time[13] == 5000 ;
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status_time[14] == 5000 ;
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status_time[15] == 5000 ;
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status_time[16] <= 5000 ;
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status_time[17] <= 5000 ;
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status_time[18] <= 5000 ;
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status_time[19] <= 5000 ;
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status_time[20] == 5000 ;
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status_time[21] == 5000 ;
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status_time[22] == 5000 ;
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status_time[23] == 5000 ;
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status_time[24] <= 5000 ;
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status_time[25] <= 5000 ;
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status_time[26] <= 5000 ;
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status_time[27] <= 5000 ;
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status_time[28] <= 5000 ;
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status_time[29] == 5000 ;
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status_time[30] == 5000 ;
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status_time[31] == 5000 ;
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status_time[ 0] > 0 ;
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status_time[ 1] > 0 ;
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status_time[ 2] > 0 ;
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status_time[ 3] > 0 ;
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status_time[ 4] > 0 ;
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status_time[ 5] > 0 ;
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status_time[ 6] > 0 ;
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status_time[ 7] > 0 ;
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status_time[ 8] > 0 ;
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status_time[ 9] > 0 ;
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status_time[10] > 0 ;
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status_time[11] > 0 ;
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status_time[12] > 0 ;
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status_time[13] > 0 ;
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status_time[14] > 0 ;
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status_time[15] > 0 ;
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status_time[16] > 0 ;
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status_time[17] > 0 ;
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status_time[18] > 0 ;
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status_time[19] > 0 ;
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status_time[20] > 0 ;
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status_time[21] > 0 ;
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status_time[22] > 0 ;
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status_time[23] > 0 ;
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status_time[24] > 0 ;
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status_time[25] > 0 ;
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status_time[26] > 0 ;
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status_time[27] > 0 ;
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status_time[28] > 0 ;
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status_time[29] > 0 ;
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status_time[30] > 0 ;
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status_time[31] > 0 ;
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}
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function new();
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endfunction
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function bit[3:0] compare(sysreg_trans tr);
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bit[3:0] result=4'b0;
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if(tr.dbg_enable != dbg_enable ) result[0]=1'b1;
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if(tr.dbg_data_sel != dbg_data_sel) result[1]=1'b1;
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if(tr.dbg_ch_sel != dbg_ch_sel ) result[2]=1'b1;
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if(tr.irq != irq ) result[3]=1'b1;
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return result;
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endfunction
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function print(bit[3:0] ctrl,integer fid);
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if(ctrl[0]) $fwrite(fid,"dbg_enable:\t%b\n",dbg_enable);
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if(ctrl[1]) $fwrite(fid,"dbg_data_sel:\t%b\n",dbg_data_sel);
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if(ctrl[2]) $fwrite(fid,"dbg_ch_sel:\t%b\n",dbg_ch_sel);
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if(ctrl[3]) $fwrite(fid,"irq:\t\t%b\n",irq);
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endfunction
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endclass : sysreg_trans
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