29 lines
486 B
Systemverilog
29 lines
486 B
Systemverilog
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class ram_trans;
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rand bit[31 :0] dout [8192];
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constraint cstr {
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dout >= 0 ;
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dout <= 2000;
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}
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function new();
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endfunction
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function bit[7:0] compare(ram_trans tr);
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bit result= 1'b0;
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if(tr.dout != dout ) result = 1'b1;
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return result;
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endfunction
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function print(bit ctrl,integer fid);
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if(ctrl[0]) begin
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$fwrite(fid,"s_data =%b\n",dout );
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end
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endfunction
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endclass : ram_trans
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