134 lines
2.6 KiB
ArmAsm
134 lines
2.6 KiB
ArmAsm
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# See LICENSE for license details.
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#*****************************************************************************
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# dirty.S
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#-----------------------------------------------------------------------------
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#
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# Test VM referenced and dirty bits.
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#
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#include "riscv_test.h"
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#include "test_macros.h"
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#if (DRAM_BASE >> 30 << 30) != DRAM_BASE
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# error This test requires DRAM_BASE be SV39 superpage-aligned
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#endif
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RVTEST_RV64M
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RVTEST_CODE_BEGIN
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# Turn on VM
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li a0, (SATP_MODE & ~(SATP_MODE<<1)) * SATP_MODE_SV39
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la a1, page_table_1
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srl a1, a1, RISCV_PGSHIFT
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or a1, a1, a0
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csrw sptbr, a1
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sfence.vma
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# Set up MPRV with MPP=S, so loads and stores use S-mode
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li a1, ((MSTATUS_MPP & ~(MSTATUS_MPP<<1)) * PRV_S) | MSTATUS_MPRV
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csrs mstatus, a1
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# Try a faulting store to make sure dirty bit is not set
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li TESTNUM, 2
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li t2, 1
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sw t2, dummy - DRAM_BASE, a0
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# Set SUM=1 so user memory access is permitted
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li TESTNUM, 3
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li a1, ((MSTATUS_MPP & ~(MSTATUS_MPP<<1)) * PRV_S) | MSTATUS_SUM
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csrs mstatus, a1
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# Make sure SUM=1 works
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lw t0, dummy - DRAM_BASE
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bnez t0, die
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# Try a non-faulting store to make sure dirty bit is set
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sw t2, dummy - DRAM_BASE, a0
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# Make sure it succeeded
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lw t0, dummy - DRAM_BASE
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bne t0, t2, die
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# Leave MPRV
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li t0, MSTATUS_MPRV
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csrc mstatus, t0
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# Make sure D bit is set
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lw t0, page_table_1
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li a0, PTE_A | PTE_D
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and t0, t0, a0
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bne t0, a0, die
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# Enter MPRV again
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li t0, MSTATUS_MPRV
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csrs mstatus, t0
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# Make sure that superpage entries trap when PPN LSBs are set.
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li TESTNUM, 4
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lw a0, page_table_1 - DRAM_BASE
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or a0, a0, 1 << PTE_PPN_SHIFT
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sw a0, page_table_1 - DRAM_BASE, t0
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sfence.vma
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sw a0, page_table_1 - DRAM_BASE, t0
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j die
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RVTEST_PASS
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TEST_PASSFAIL
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.align 2
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.global mtvec_handler
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mtvec_handler:
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csrr t0, mcause
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add t0, t0, -CAUSE_STORE_PAGE_FAULT
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bnez t0, die
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li t1, 2
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bne TESTNUM, t1, 1f
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# Make sure D bit is clear
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lw t0, page_table_1
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and t1, t0, PTE_D
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bnez t1, die
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skip:
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csrr t0, mepc
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add t0, t0, 4
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csrw mepc, t0
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mret
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1:
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li t1, 3
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bne TESTNUM, t1, 1f
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# The implementation doesn't appear to set D bits in HW.
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# Make sure the D bit really is clear.
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lw t0, page_table_1
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and t1, t0, PTE_D
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bnez t1, die
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# Set the D bit.
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or t0, t0, PTE_D
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sw t0, page_table_1, t1
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sfence.vma
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mret
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1:
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li t1, 4
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bne TESTNUM, t1, 1f
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j pass
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1:
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die:
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RVTEST_FAIL
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RVTEST_CODE_END
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.data
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RVTEST_DATA_BEGIN
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TEST_DATA
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.align 12
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page_table_1: .dword (DRAM_BASE/RISCV_PGSIZE << PTE_PPN_SHIFT) | PTE_V | PTE_U | PTE_R | PTE_W | PTE_X | PTE_A
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dummy: .dword 0
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RVTEST_DATA_END
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