SPI_Test/tb/qumcu/isa/case/Sw_test/main.s

13 lines
151 B
ArmAsm
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2024-06-25 16:41:01 +08:00
lui x3,0x87654
addi x3,x3,0x321
lui x4,0xfedcb
addi x4,x4,0x7f5
lui x1,0x100
lui x2,0x104
loop:
addi x2,x2,-0x4
sw x2 ,0x0(x2)
bne x2, x1, loop
exit: